Commit | Line | Data |
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b534c6d3 | 1 | /* tc-i386.c -- Assemble code for the Intel 80386 |
f7e42eb4 | 2 | Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
d382c579 TG |
3 | 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, |
4 | 2012 | |
47926f60 | 5 | Free Software Foundation, Inc. |
252b5132 RH |
6 | |
7 | This file is part of GAS, the GNU Assembler. | |
8 | ||
9 | GAS is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 11 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
12 | any later version. |
13 | ||
14 | GAS is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
21 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
22 | 02110-1301, USA. */ | |
252b5132 | 23 | |
47926f60 KH |
24 | /* Intel 80386 machine specific gas. |
25 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 26 | x86_64 support by Jan Hubicka (jh@suse.cz) |
0f10071e | 27 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
47926f60 KH |
28 | Bugs & suggestions are completely welcome. This is free software. |
29 | Please help us make it better. */ | |
252b5132 | 30 | |
252b5132 | 31 | #include "as.h" |
3882b010 | 32 | #include "safe-ctype.h" |
252b5132 | 33 | #include "subsegs.h" |
316e2c05 | 34 | #include "dwarf2dbg.h" |
54cfded0 | 35 | #include "dw2gencfi.h" |
d2b2c203 | 36 | #include "elf/x86-64.h" |
40fb9820 | 37 | #include "opcodes/i386-init.h" |
252b5132 | 38 | |
252b5132 RH |
39 | #ifndef REGISTER_WARNINGS |
40 | #define REGISTER_WARNINGS 1 | |
41 | #endif | |
42 | ||
c3332e24 | 43 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 44 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
45 | #endif |
46 | ||
29b0f896 AM |
47 | #ifndef DEFAULT_ARCH |
48 | #define DEFAULT_ARCH "i386" | |
246fcdee | 49 | #endif |
252b5132 | 50 | |
edde18a5 AM |
51 | #ifndef INLINE |
52 | #if __GNUC__ >= 2 | |
53 | #define INLINE __inline__ | |
54 | #else | |
55 | #define INLINE | |
56 | #endif | |
57 | #endif | |
58 | ||
6305a203 L |
59 | /* Prefixes will be emitted in the order defined below. |
60 | WAIT_PREFIX must be the first prefix since FWAIT is really is an | |
61 | instruction, and so must come before any prefixes. | |
62 | The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, | |
42164a71 | 63 | REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */ |
6305a203 L |
64 | #define WAIT_PREFIX 0 |
65 | #define SEG_PREFIX 1 | |
66 | #define ADDR_PREFIX 2 | |
67 | #define DATA_PREFIX 3 | |
c32fa91d | 68 | #define REP_PREFIX 4 |
42164a71 | 69 | #define HLE_PREFIX REP_PREFIX |
c32fa91d L |
70 | #define LOCK_PREFIX 5 |
71 | #define REX_PREFIX 6 /* must come last. */ | |
72 | #define MAX_PREFIXES 7 /* max prefixes per opcode */ | |
6305a203 L |
73 | |
74 | /* we define the syntax here (modulo base,index,scale syntax) */ | |
75 | #define REGISTER_PREFIX '%' | |
76 | #define IMMEDIATE_PREFIX '$' | |
77 | #define ABSOLUTE_PREFIX '*' | |
78 | ||
79 | /* these are the instruction mnemonic suffixes in AT&T syntax or | |
80 | memory operand size in Intel syntax. */ | |
81 | #define WORD_MNEM_SUFFIX 'w' | |
82 | #define BYTE_MNEM_SUFFIX 'b' | |
83 | #define SHORT_MNEM_SUFFIX 's' | |
84 | #define LONG_MNEM_SUFFIX 'l' | |
85 | #define QWORD_MNEM_SUFFIX 'q' | |
86 | #define XMMWORD_MNEM_SUFFIX 'x' | |
c0f3af97 | 87 | #define YMMWORD_MNEM_SUFFIX 'y' |
6305a203 L |
88 | /* Intel Syntax. Use a non-ascii letter since since it never appears |
89 | in instructions. */ | |
90 | #define LONG_DOUBLE_MNEM_SUFFIX '\1' | |
91 | ||
92 | #define END_OF_INSN '\0' | |
93 | ||
94 | /* | |
95 | 'templates' is for grouping together 'template' structures for opcodes | |
96 | of the same name. This is only used for storing the insns in the grand | |
97 | ole hash table of insns. | |
98 | The templates themselves start at START and range up to (but not including) | |
99 | END. | |
100 | */ | |
101 | typedef struct | |
102 | { | |
d3ce72d0 NC |
103 | const insn_template *start; |
104 | const insn_template *end; | |
6305a203 L |
105 | } |
106 | templates; | |
107 | ||
108 | /* 386 operand encoding bytes: see 386 book for details of this. */ | |
109 | typedef struct | |
110 | { | |
111 | unsigned int regmem; /* codes register or memory operand */ | |
112 | unsigned int reg; /* codes register operand (or extended opcode) */ | |
113 | unsigned int mode; /* how to interpret regmem & reg */ | |
114 | } | |
115 | modrm_byte; | |
116 | ||
117 | /* x86-64 extension prefix. */ | |
118 | typedef int rex_byte; | |
119 | ||
6305a203 L |
120 | /* 386 opcode byte to code indirect addressing. */ |
121 | typedef struct | |
122 | { | |
123 | unsigned base; | |
124 | unsigned index; | |
125 | unsigned scale; | |
126 | } | |
127 | sib_byte; | |
128 | ||
6305a203 L |
129 | /* x86 arch names, types and features */ |
130 | typedef struct | |
131 | { | |
132 | const char *name; /* arch name */ | |
8a2c8fef | 133 | unsigned int len; /* arch string length */ |
6305a203 L |
134 | enum processor_type type; /* arch type */ |
135 | i386_cpu_flags flags; /* cpu feature flags */ | |
8a2c8fef | 136 | unsigned int skip; /* show_arch should skip this. */ |
22109423 | 137 | unsigned int negated; /* turn off indicated flags. */ |
6305a203 L |
138 | } |
139 | arch_entry; | |
140 | ||
78f12dd3 | 141 | static void update_code_flag (int, int); |
e3bb37b5 L |
142 | static void set_code_flag (int); |
143 | static void set_16bit_gcc_code_flag (int); | |
144 | static void set_intel_syntax (int); | |
1efbbeb4 | 145 | static void set_intel_mnemonic (int); |
db51cc60 | 146 | static void set_allow_index_reg (int); |
7bab8ab5 | 147 | static void set_check (int); |
e3bb37b5 | 148 | static void set_cpu_arch (int); |
6482c264 | 149 | #ifdef TE_PE |
e3bb37b5 | 150 | static void pe_directive_secrel (int); |
6482c264 | 151 | #endif |
e3bb37b5 L |
152 | static void signed_cons (int); |
153 | static char *output_invalid (int c); | |
ee86248c JB |
154 | static int i386_finalize_immediate (segT, expressionS *, i386_operand_type, |
155 | const char *); | |
156 | static int i386_finalize_displacement (segT, expressionS *, i386_operand_type, | |
157 | const char *); | |
a7619375 | 158 | static int i386_att_operand (char *); |
e3bb37b5 | 159 | static int i386_intel_operand (char *, int); |
ee86248c JB |
160 | static int i386_intel_simplify (expressionS *); |
161 | static int i386_intel_parse_name (const char *, expressionS *); | |
e3bb37b5 L |
162 | static const reg_entry *parse_register (char *, char **); |
163 | static char *parse_insn (char *, char *); | |
164 | static char *parse_operands (char *, const char *); | |
165 | static void swap_operands (void); | |
4d456e3d | 166 | static void swap_2_operands (int, int); |
e3bb37b5 L |
167 | static void optimize_imm (void); |
168 | static void optimize_disp (void); | |
d3ce72d0 | 169 | static const insn_template *match_template (void); |
e3bb37b5 L |
170 | static int check_string (void); |
171 | static int process_suffix (void); | |
172 | static int check_byte_reg (void); | |
173 | static int check_long_reg (void); | |
174 | static int check_qword_reg (void); | |
175 | static int check_word_reg (void); | |
176 | static int finalize_imm (void); | |
177 | static int process_operands (void); | |
178 | static const seg_entry *build_modrm_byte (void); | |
179 | static void output_insn (void); | |
180 | static void output_imm (fragS *, offsetT); | |
181 | static void output_disp (fragS *, offsetT); | |
29b0f896 | 182 | #ifndef I386COFF |
e3bb37b5 | 183 | static void s_bss (int); |
252b5132 | 184 | #endif |
17d4e2a2 L |
185 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
186 | static void handle_large_common (int small ATTRIBUTE_UNUSED); | |
187 | #endif | |
252b5132 | 188 | |
a847613f | 189 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 190 | |
c0f3af97 L |
191 | /* VEX prefix. */ |
192 | typedef struct | |
193 | { | |
194 | /* VEX prefix is either 2 byte or 3 byte. */ | |
195 | unsigned char bytes[3]; | |
196 | unsigned int length; | |
197 | /* Destination or source register specifier. */ | |
198 | const reg_entry *register_specifier; | |
199 | } vex_prefix; | |
200 | ||
252b5132 | 201 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 202 | i386_insn. */ |
252b5132 | 203 | |
520dc8e8 AM |
204 | union i386_op |
205 | { | |
206 | expressionS *disps; | |
207 | expressionS *imms; | |
208 | const reg_entry *regs; | |
209 | }; | |
210 | ||
a65babc9 L |
211 | enum i386_error |
212 | { | |
86e026a4 | 213 | operand_size_mismatch, |
a65babc9 L |
214 | operand_type_mismatch, |
215 | register_type_mismatch, | |
216 | number_of_operands_mismatch, | |
217 | invalid_instruction_suffix, | |
218 | bad_imm4, | |
219 | old_gcc_only, | |
220 | unsupported_with_intel_mnemonic, | |
221 | unsupported_syntax, | |
6c30d220 L |
222 | unsupported, |
223 | invalid_vsib_address, | |
7bab8ab5 | 224 | invalid_vector_register_set, |
6c30d220 | 225 | unsupported_vector_index_register |
a65babc9 L |
226 | }; |
227 | ||
252b5132 RH |
228 | struct _i386_insn |
229 | { | |
47926f60 | 230 | /* TM holds the template for the insn were currently assembling. */ |
d3ce72d0 | 231 | insn_template tm; |
252b5132 | 232 | |
7d5e4556 L |
233 | /* SUFFIX holds the instruction size suffix for byte, word, dword |
234 | or qword, if given. */ | |
252b5132 RH |
235 | char suffix; |
236 | ||
47926f60 | 237 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
238 | unsigned int operands; |
239 | ||
240 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
241 | of given register, displacement, memory operands and immediate | |
47926f60 | 242 | operands. */ |
252b5132 RH |
243 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
244 | ||
245 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 246 | use OP[i] for the corresponding operand. */ |
40fb9820 | 247 | i386_operand_type types[MAX_OPERANDS]; |
252b5132 | 248 | |
520dc8e8 AM |
249 | /* Displacement expression, immediate expression, or register for each |
250 | operand. */ | |
251 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 252 | |
3e73aa7c JH |
253 | /* Flags for operands. */ |
254 | unsigned int flags[MAX_OPERANDS]; | |
255 | #define Operand_PCrel 1 | |
256 | ||
252b5132 | 257 | /* Relocation type for operand */ |
f86103b7 | 258 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
252b5132 | 259 | |
252b5132 RH |
260 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
261 | the base index byte below. */ | |
262 | const reg_entry *base_reg; | |
263 | const reg_entry *index_reg; | |
264 | unsigned int log2_scale_factor; | |
265 | ||
266 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 267 | explicit segment overrides are given. */ |
ce8a8b2f | 268 | const seg_entry *seg[2]; |
252b5132 RH |
269 | |
270 | /* PREFIX holds all the given prefix opcodes (usually null). | |
271 | PREFIXES is the number of prefix opcodes. */ | |
272 | unsigned int prefixes; | |
273 | unsigned char prefix[MAX_PREFIXES]; | |
274 | ||
275 | /* RM and SIB are the modrm byte and the sib byte where the | |
c1e679ec | 276 | addressing modes of this insn are encoded. */ |
252b5132 | 277 | modrm_byte rm; |
3e73aa7c | 278 | rex_byte rex; |
252b5132 | 279 | sib_byte sib; |
c0f3af97 | 280 | vex_prefix vex; |
b6169b20 L |
281 | |
282 | /* Swap operand in encoding. */ | |
4473e004 | 283 | unsigned int swap_operand; |
891edac4 | 284 | |
a501d77e L |
285 | /* Prefer 8bit or 32bit displacement in encoding. */ |
286 | enum | |
287 | { | |
288 | disp_encoding_default = 0, | |
289 | disp_encoding_8bit, | |
290 | disp_encoding_32bit | |
291 | } disp_encoding; | |
f8a5c266 | 292 | |
42164a71 L |
293 | /* Have HLE prefix. */ |
294 | unsigned int have_hle; | |
295 | ||
891edac4 | 296 | /* Error message. */ |
a65babc9 | 297 | enum i386_error error; |
252b5132 RH |
298 | }; |
299 | ||
300 | typedef struct _i386_insn i386_insn; | |
301 | ||
302 | /* List of chars besides those in app.c:symbol_chars that can start an | |
303 | operand. Used to prevent the scrubber eating vital white-space. */ | |
32137342 | 304 | const char extra_symbol_chars[] = "*%-([" |
252b5132 | 305 | #ifdef LEX_AT |
32137342 NC |
306 | "@" |
307 | #endif | |
308 | #ifdef LEX_QM | |
309 | "?" | |
252b5132 | 310 | #endif |
32137342 | 311 | ; |
252b5132 | 312 | |
29b0f896 AM |
313 | #if (defined (TE_I386AIX) \ |
314 | || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ | |
3896cfd5 | 315 | && !defined (TE_GNU) \ |
29b0f896 | 316 | && !defined (TE_LINUX) \ |
8d63c93e RM |
317 | && !defined (TE_NACL) \ |
318 | && !defined (TE_NETWARE) \ | |
29b0f896 | 319 | && !defined (TE_FreeBSD) \ |
5b806d27 | 320 | && !defined (TE_DragonFly) \ |
29b0f896 | 321 | && !defined (TE_NetBSD))) |
252b5132 | 322 | /* This array holds the chars that always start a comment. If the |
b3b91714 AM |
323 | pre-processor is disabled, these aren't very useful. The option |
324 | --divide will remove '/' from this list. */ | |
325 | const char *i386_comment_chars = "#/"; | |
326 | #define SVR4_COMMENT_CHARS 1 | |
252b5132 | 327 | #define PREFIX_SEPARATOR '\\' |
252b5132 | 328 | |
b3b91714 AM |
329 | #else |
330 | const char *i386_comment_chars = "#"; | |
331 | #define PREFIX_SEPARATOR '/' | |
332 | #endif | |
333 | ||
252b5132 RH |
334 | /* This array holds the chars that only start a comment at the beginning of |
335 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
336 | .line and .file directives will appear in the pre-processed output. |
337 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 338 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
339 | #NO_APP at the beginning of its output. |
340 | Also note that comments started like this one will always work if | |
252b5132 | 341 | '/' isn't otherwise defined. */ |
b3b91714 | 342 | const char line_comment_chars[] = "#/"; |
252b5132 | 343 | |
63a0b638 | 344 | const char line_separator_chars[] = ";"; |
252b5132 | 345 | |
ce8a8b2f AM |
346 | /* Chars that can be used to separate mant from exp in floating point |
347 | nums. */ | |
252b5132 RH |
348 | const char EXP_CHARS[] = "eE"; |
349 | ||
ce8a8b2f AM |
350 | /* Chars that mean this number is a floating point constant |
351 | As in 0f12.456 | |
352 | or 0d1.2345e12. */ | |
252b5132 RH |
353 | const char FLT_CHARS[] = "fFdDxX"; |
354 | ||
ce8a8b2f | 355 | /* Tables for lexical analysis. */ |
252b5132 RH |
356 | static char mnemonic_chars[256]; |
357 | static char register_chars[256]; | |
358 | static char operand_chars[256]; | |
359 | static char identifier_chars[256]; | |
360 | static char digit_chars[256]; | |
361 | ||
ce8a8b2f | 362 | /* Lexical macros. */ |
252b5132 RH |
363 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
364 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
365 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
366 | #define is_space_char(x) ((x) == ' ') | |
367 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
368 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
369 | ||
0234cb7c | 370 | /* All non-digit non-letter characters that may occur in an operand. */ |
252b5132 RH |
371 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
372 | ||
373 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
374 | effect this we maintain a stack of saved characters that we've smashed | |
375 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 376 | assembler instruction). */ |
252b5132 | 377 | static char save_stack[32]; |
ce8a8b2f | 378 | static char *save_stack_p; |
252b5132 RH |
379 | #define END_STRING_AND_SAVE(s) \ |
380 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
381 | #define RESTORE_END_STRING(s) \ | |
382 | do { *(s) = *--save_stack_p; } while (0) | |
383 | ||
47926f60 | 384 | /* The instruction we're assembling. */ |
252b5132 RH |
385 | static i386_insn i; |
386 | ||
387 | /* Possible templates for current insn. */ | |
388 | static const templates *current_templates; | |
389 | ||
31b2323c L |
390 | /* Per instruction expressionS buffers: max displacements & immediates. */ |
391 | static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; | |
392 | static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; | |
252b5132 | 393 | |
47926f60 | 394 | /* Current operand we are working on. */ |
ee86248c | 395 | static int this_operand = -1; |
252b5132 | 396 | |
3e73aa7c JH |
397 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
398 | these. */ | |
399 | ||
400 | enum flag_code { | |
401 | CODE_32BIT, | |
402 | CODE_16BIT, | |
403 | CODE_64BIT }; | |
404 | ||
405 | static enum flag_code flag_code; | |
4fa24527 | 406 | static unsigned int object_64bit; |
862be3fb | 407 | static unsigned int disallow_64bit_reloc; |
3e73aa7c JH |
408 | static int use_rela_relocations = 0; |
409 | ||
7af8ed2d NC |
410 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
411 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ | |
412 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) | |
413 | ||
351f65ca L |
414 | /* The ELF ABI to use. */ |
415 | enum x86_elf_abi | |
416 | { | |
417 | I386_ABI, | |
7f56bc95 L |
418 | X86_64_ABI, |
419 | X86_64_X32_ABI | |
351f65ca L |
420 | }; |
421 | ||
422 | static enum x86_elf_abi x86_elf_abi = I386_ABI; | |
7af8ed2d | 423 | #endif |
351f65ca | 424 | |
3e73aa7c | 425 | /* The names used to print error messages. */ |
b77a7acd | 426 | static const char *flag_code_names[] = |
3e73aa7c JH |
427 | { |
428 | "32", | |
429 | "16", | |
430 | "64" | |
431 | }; | |
252b5132 | 432 | |
47926f60 KH |
433 | /* 1 for intel syntax, |
434 | 0 if att syntax. */ | |
435 | static int intel_syntax = 0; | |
252b5132 | 436 | |
1efbbeb4 L |
437 | /* 1 for intel mnemonic, |
438 | 0 if att mnemonic. */ | |
439 | static int intel_mnemonic = !SYSV386_COMPAT; | |
440 | ||
5209009a | 441 | /* 1 if support old (<= 2.8.1) versions of gcc. */ |
1efbbeb4 L |
442 | static int old_gcc = OLDGCC_COMPAT; |
443 | ||
a60de03c JB |
444 | /* 1 if pseudo registers are permitted. */ |
445 | static int allow_pseudo_reg = 0; | |
446 | ||
47926f60 KH |
447 | /* 1 if register prefix % not required. */ |
448 | static int allow_naked_reg = 0; | |
252b5132 | 449 | |
ba104c83 | 450 | /* 1 if pseudo index register, eiz/riz, is allowed . */ |
db51cc60 L |
451 | static int allow_index_reg = 0; |
452 | ||
7bab8ab5 | 453 | static enum check_kind |
daf50ae7 | 454 | { |
7bab8ab5 JB |
455 | check_none = 0, |
456 | check_warning, | |
457 | check_error | |
daf50ae7 | 458 | } |
7bab8ab5 | 459 | sse_check, operand_check = check_warning; |
daf50ae7 | 460 | |
2ca3ace5 L |
461 | /* Register prefix used for error message. */ |
462 | static const char *register_prefix = "%"; | |
463 | ||
47926f60 KH |
464 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
465 | leave, push, and pop instructions so that gcc has the same stack | |
466 | frame as in 32 bit mode. */ | |
467 | static char stackop_size = '\0'; | |
eecb386c | 468 | |
12b55ccc L |
469 | /* Non-zero to optimize code alignment. */ |
470 | int optimize_align_code = 1; | |
471 | ||
47926f60 KH |
472 | /* Non-zero to quieten some warnings. */ |
473 | static int quiet_warnings = 0; | |
a38cf1db | 474 | |
47926f60 KH |
475 | /* CPU name. */ |
476 | static const char *cpu_arch_name = NULL; | |
6305a203 | 477 | static char *cpu_sub_arch_name = NULL; |
a38cf1db | 478 | |
47926f60 | 479 | /* CPU feature flags. */ |
40fb9820 L |
480 | static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; |
481 | ||
ccc9c027 L |
482 | /* If we have selected a cpu we are generating instructions for. */ |
483 | static int cpu_arch_tune_set = 0; | |
484 | ||
9103f4f4 | 485 | /* Cpu we are generating instructions for. */ |
fbf3f584 | 486 | enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; |
9103f4f4 L |
487 | |
488 | /* CPU feature flags of cpu we are generating instructions for. */ | |
40fb9820 | 489 | static i386_cpu_flags cpu_arch_tune_flags; |
9103f4f4 | 490 | |
ccc9c027 | 491 | /* CPU instruction set architecture used. */ |
fbf3f584 | 492 | enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; |
ccc9c027 | 493 | |
9103f4f4 | 494 | /* CPU feature flags of instruction set architecture used. */ |
fbf3f584 | 495 | i386_cpu_flags cpu_arch_isa_flags; |
9103f4f4 | 496 | |
fddf5b5b AM |
497 | /* If set, conditional jumps are not automatically promoted to handle |
498 | larger than a byte offset. */ | |
499 | static unsigned int no_cond_jump_promotion = 0; | |
500 | ||
c0f3af97 L |
501 | /* Encode SSE instructions with VEX prefix. */ |
502 | static unsigned int sse2avx; | |
503 | ||
539f890d L |
504 | /* Encode scalar AVX instructions with specific vector length. */ |
505 | static enum | |
506 | { | |
507 | vex128 = 0, | |
508 | vex256 | |
509 | } avxscalar; | |
510 | ||
29b0f896 | 511 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
87c245cc | 512 | static symbolS *GOT_symbol; |
29b0f896 | 513 | |
a4447b93 RH |
514 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
515 | unsigned int x86_dwarf2_return_column; | |
516 | ||
517 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
518 | int x86_cie_data_alignment; | |
519 | ||
252b5132 | 520 | /* Interface to relax_segment. |
fddf5b5b AM |
521 | There are 3 major relax states for 386 jump insns because the |
522 | different types of jumps add different sizes to frags when we're | |
523 | figuring out what sort of jump to choose to reach a given label. */ | |
252b5132 | 524 | |
47926f60 | 525 | /* Types. */ |
93c2a809 AM |
526 | #define UNCOND_JUMP 0 |
527 | #define COND_JUMP 1 | |
528 | #define COND_JUMP86 2 | |
fddf5b5b | 529 | |
47926f60 | 530 | /* Sizes. */ |
252b5132 RH |
531 | #define CODE16 1 |
532 | #define SMALL 0 | |
29b0f896 | 533 | #define SMALL16 (SMALL | CODE16) |
252b5132 | 534 | #define BIG 2 |
29b0f896 | 535 | #define BIG16 (BIG | CODE16) |
252b5132 RH |
536 | |
537 | #ifndef INLINE | |
538 | #ifdef __GNUC__ | |
539 | #define INLINE __inline__ | |
540 | #else | |
541 | #define INLINE | |
542 | #endif | |
543 | #endif | |
544 | ||
fddf5b5b AM |
545 | #define ENCODE_RELAX_STATE(type, size) \ |
546 | ((relax_substateT) (((type) << 2) | (size))) | |
547 | #define TYPE_FROM_RELAX_STATE(s) \ | |
548 | ((s) >> 2) | |
549 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
550 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
551 | |
552 | /* This table is used by relax_frag to promote short jumps to long | |
553 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
554 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
555 | don't allow a short jump in a 32 bit code segment to be promoted to | |
556 | a 16 bit offset jump because it's slower (requires data size | |
557 | prefix), and doesn't work, unless the destination is in the bottom | |
558 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
559 | ||
560 | const relax_typeS md_relax_table[] = | |
561 | { | |
24eab124 AM |
562 | /* The fields are: |
563 | 1) most positive reach of this state, | |
564 | 2) most negative reach of this state, | |
93c2a809 | 565 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 566 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 567 | |
fddf5b5b | 568 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
569 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
570 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
571 | /* dword jmp adds 4 bytes to frag: | |
572 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 573 | {0, 0, 4, 0}, |
93c2a809 AM |
574 | /* word jmp adds 2 byte2 to frag: |
575 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
576 | {0, 0, 2, 0}, |
577 | ||
93c2a809 AM |
578 | /* COND_JUMP states. */ |
579 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
580 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
581 | /* dword conditionals adds 5 bytes to frag: | |
582 | 1 extra opcode byte, 4 displacement bytes. */ | |
583 | {0, 0, 5, 0}, | |
fddf5b5b | 584 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
585 | 1 extra opcode byte, 2 displacement bytes. */ |
586 | {0, 0, 3, 0}, | |
587 | ||
588 | /* COND_JUMP86 states. */ | |
589 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
590 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
591 | /* dword conditionals adds 5 bytes to frag: | |
592 | 1 extra opcode byte, 4 displacement bytes. */ | |
593 | {0, 0, 5, 0}, | |
594 | /* word conditionals add 4 bytes to frag: | |
595 | 1 displacement byte and a 3 byte long branch insn. */ | |
596 | {0, 0, 4, 0} | |
252b5132 RH |
597 | }; |
598 | ||
9103f4f4 L |
599 | static const arch_entry cpu_arch[] = |
600 | { | |
89507696 JB |
601 | /* Do not replace the first two entries - i386_target_format() |
602 | relies on them being there in this order. */ | |
8a2c8fef | 603 | { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32, |
22109423 | 604 | CPU_GENERIC32_FLAGS, 0, 0 }, |
8a2c8fef | 605 | { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64, |
22109423 | 606 | CPU_GENERIC64_FLAGS, 0, 0 }, |
8a2c8fef | 607 | { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN, |
22109423 | 608 | CPU_NONE_FLAGS, 0, 0 }, |
8a2c8fef | 609 | { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN, |
22109423 | 610 | CPU_I186_FLAGS, 0, 0 }, |
8a2c8fef | 611 | { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN, |
22109423 | 612 | CPU_I286_FLAGS, 0, 0 }, |
8a2c8fef | 613 | { STRING_COMMA_LEN ("i386"), PROCESSOR_I386, |
22109423 | 614 | CPU_I386_FLAGS, 0, 0 }, |
8a2c8fef | 615 | { STRING_COMMA_LEN ("i486"), PROCESSOR_I486, |
22109423 | 616 | CPU_I486_FLAGS, 0, 0 }, |
8a2c8fef | 617 | { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM, |
22109423 | 618 | CPU_I586_FLAGS, 0, 0 }, |
8a2c8fef | 619 | { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO, |
22109423 | 620 | CPU_I686_FLAGS, 0, 0 }, |
8a2c8fef | 621 | { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM, |
22109423 | 622 | CPU_I586_FLAGS, 0, 0 }, |
8a2c8fef | 623 | { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO, |
22109423 | 624 | CPU_PENTIUMPRO_FLAGS, 0, 0 }, |
8a2c8fef | 625 | { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO, |
22109423 | 626 | CPU_P2_FLAGS, 0, 0 }, |
8a2c8fef | 627 | { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO, |
22109423 | 628 | CPU_P3_FLAGS, 0, 0 }, |
8a2c8fef | 629 | { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4, |
22109423 | 630 | CPU_P4_FLAGS, 0, 0 }, |
8a2c8fef | 631 | { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA, |
22109423 | 632 | CPU_CORE_FLAGS, 0, 0 }, |
8a2c8fef | 633 | { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA, |
22109423 | 634 | CPU_NOCONA_FLAGS, 0, 0 }, |
8a2c8fef | 635 | { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE, |
22109423 | 636 | CPU_CORE_FLAGS, 1, 0 }, |
8a2c8fef | 637 | { STRING_COMMA_LEN ("core"), PROCESSOR_CORE, |
22109423 | 638 | CPU_CORE_FLAGS, 0, 0 }, |
8a2c8fef | 639 | { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2, |
22109423 | 640 | CPU_CORE2_FLAGS, 1, 0 }, |
8a2c8fef | 641 | { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2, |
22109423 | 642 | CPU_CORE2_FLAGS, 0, 0 }, |
8a2c8fef | 643 | { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7, |
22109423 | 644 | CPU_COREI7_FLAGS, 0, 0 }, |
8a2c8fef | 645 | { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM, |
22109423 | 646 | CPU_L1OM_FLAGS, 0, 0 }, |
7a9068fe L |
647 | { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM, |
648 | CPU_K1OM_FLAGS, 0, 0 }, | |
8a2c8fef | 649 | { STRING_COMMA_LEN ("k6"), PROCESSOR_K6, |
22109423 | 650 | CPU_K6_FLAGS, 0, 0 }, |
8a2c8fef | 651 | { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6, |
22109423 | 652 | CPU_K6_2_FLAGS, 0, 0 }, |
8a2c8fef | 653 | { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON, |
22109423 | 654 | CPU_ATHLON_FLAGS, 0, 0 }, |
8a2c8fef | 655 | { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8, |
22109423 | 656 | CPU_K8_FLAGS, 1, 0 }, |
8a2c8fef | 657 | { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8, |
22109423 | 658 | CPU_K8_FLAGS, 0, 0 }, |
8a2c8fef | 659 | { STRING_COMMA_LEN ("k8"), PROCESSOR_K8, |
22109423 | 660 | CPU_K8_FLAGS, 0, 0 }, |
8a2c8fef | 661 | { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10, |
22109423 | 662 | CPU_AMDFAM10_FLAGS, 0, 0 }, |
8aedb9fe | 663 | { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD, |
22109423 | 664 | CPU_BDVER1_FLAGS, 0, 0 }, |
8aedb9fe | 665 | { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD, |
af2f724e | 666 | CPU_BDVER2_FLAGS, 0, 0 }, |
8a2c8fef | 667 | { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN, |
22109423 | 668 | CPU_8087_FLAGS, 0, 0 }, |
8a2c8fef | 669 | { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN, |
22109423 | 670 | CPU_287_FLAGS, 0, 0 }, |
8a2c8fef | 671 | { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN, |
22109423 | 672 | CPU_387_FLAGS, 0, 0 }, |
8a2c8fef | 673 | { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN, |
22109423 | 674 | CPU_ANY87_FLAGS, 0, 1 }, |
8a2c8fef | 675 | { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN, |
22109423 | 676 | CPU_MMX_FLAGS, 0, 0 }, |
8a2c8fef | 677 | { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN, |
22109423 | 678 | CPU_3DNOWA_FLAGS, 0, 1 }, |
8a2c8fef | 679 | { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN, |
22109423 | 680 | CPU_SSE_FLAGS, 0, 0 }, |
8a2c8fef | 681 | { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN, |
22109423 | 682 | CPU_SSE2_FLAGS, 0, 0 }, |
8a2c8fef | 683 | { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN, |
22109423 | 684 | CPU_SSE3_FLAGS, 0, 0 }, |
8a2c8fef | 685 | { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN, |
22109423 | 686 | CPU_SSSE3_FLAGS, 0, 0 }, |
8a2c8fef | 687 | { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN, |
22109423 | 688 | CPU_SSE4_1_FLAGS, 0, 0 }, |
8a2c8fef | 689 | { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN, |
22109423 | 690 | CPU_SSE4_2_FLAGS, 0, 0 }, |
8a2c8fef | 691 | { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN, |
22109423 | 692 | CPU_SSE4_2_FLAGS, 0, 0 }, |
8a2c8fef | 693 | { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN, |
22109423 | 694 | CPU_ANY_SSE_FLAGS, 0, 1 }, |
8a2c8fef | 695 | { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN, |
22109423 | 696 | CPU_AVX_FLAGS, 0, 0 }, |
6c30d220 L |
697 | { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN, |
698 | CPU_AVX2_FLAGS, 0, 0 }, | |
8a2c8fef | 699 | { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN, |
22109423 | 700 | CPU_ANY_AVX_FLAGS, 0, 1 }, |
8a2c8fef | 701 | { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN, |
22109423 | 702 | CPU_VMX_FLAGS, 0, 0 }, |
8729a6f6 L |
703 | { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN, |
704 | CPU_VMFUNC_FLAGS, 0, 0 }, | |
8a2c8fef | 705 | { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN, |
22109423 | 706 | CPU_SMX_FLAGS, 0, 0 }, |
8a2c8fef | 707 | { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN, |
22109423 | 708 | CPU_XSAVE_FLAGS, 0, 0 }, |
c7b8aa3a | 709 | { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN, |
22109423 | 710 | CPU_XSAVEOPT_FLAGS, 0, 0 }, |
8a2c8fef | 711 | { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN, |
22109423 | 712 | CPU_AES_FLAGS, 0, 0 }, |
8a2c8fef | 713 | { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN, |
22109423 | 714 | CPU_PCLMUL_FLAGS, 0, 0 }, |
8a2c8fef | 715 | { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN, |
22109423 | 716 | CPU_PCLMUL_FLAGS, 1, 0 }, |
c7b8aa3a | 717 | { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN, |
22109423 | 718 | CPU_FSGSBASE_FLAGS, 0, 0 }, |
c7b8aa3a | 719 | { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN, |
22109423 | 720 | CPU_RDRND_FLAGS, 0, 0 }, |
c7b8aa3a | 721 | { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN, |
22109423 | 722 | CPU_F16C_FLAGS, 0, 0 }, |
6c30d220 L |
723 | { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN, |
724 | CPU_BMI2_FLAGS, 0, 0 }, | |
8a2c8fef | 725 | { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN, |
22109423 | 726 | CPU_FMA_FLAGS, 0, 0 }, |
8a2c8fef | 727 | { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN, |
22109423 | 728 | CPU_FMA4_FLAGS, 0, 0 }, |
8a2c8fef | 729 | { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN, |
22109423 | 730 | CPU_XOP_FLAGS, 0, 0 }, |
8a2c8fef | 731 | { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN, |
22109423 | 732 | CPU_LWP_FLAGS, 0, 0 }, |
8a2c8fef | 733 | { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN, |
22109423 | 734 | CPU_MOVBE_FLAGS, 0, 0 }, |
8a2c8fef | 735 | { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN, |
22109423 | 736 | CPU_EPT_FLAGS, 0, 0 }, |
6c30d220 L |
737 | { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN, |
738 | CPU_LZCNT_FLAGS, 0, 0 }, | |
42164a71 L |
739 | { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN, |
740 | CPU_HLE_FLAGS, 0, 0 }, | |
741 | { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN, | |
742 | CPU_RTM_FLAGS, 0, 0 }, | |
6c30d220 L |
743 | { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN, |
744 | CPU_INVPCID_FLAGS, 0, 0 }, | |
8a2c8fef | 745 | { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN, |
22109423 L |
746 | CPU_CLFLUSH_FLAGS, 0, 0 }, |
747 | { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN, | |
748 | CPU_NOP_FLAGS, 0, 0 }, | |
8a2c8fef | 749 | { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN, |
22109423 | 750 | CPU_SYSCALL_FLAGS, 0, 0 }, |
8a2c8fef | 751 | { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN, |
22109423 | 752 | CPU_RDTSCP_FLAGS, 0, 0 }, |
8a2c8fef | 753 | { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN, |
22109423 | 754 | CPU_3DNOW_FLAGS, 0, 0 }, |
8a2c8fef | 755 | { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN, |
22109423 | 756 | CPU_3DNOWA_FLAGS, 0, 0 }, |
8a2c8fef | 757 | { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN, |
22109423 | 758 | CPU_PADLOCK_FLAGS, 0, 0 }, |
8a2c8fef | 759 | { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN, |
22109423 | 760 | CPU_SVME_FLAGS, 1, 0 }, |
8a2c8fef | 761 | { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN, |
22109423 | 762 | CPU_SVME_FLAGS, 0, 0 }, |
8a2c8fef | 763 | { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, |
22109423 | 764 | CPU_SSE4A_FLAGS, 0, 0 }, |
8a2c8fef | 765 | { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN, |
22109423 | 766 | CPU_ABM_FLAGS, 0, 0 }, |
87973e9f QN |
767 | { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN, |
768 | CPU_BMI_FLAGS, 0, 0 }, | |
2a2a0f38 QN |
769 | { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN, |
770 | CPU_TBM_FLAGS, 0, 0 }, | |
e2e1fcde L |
771 | { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN, |
772 | CPU_ADX_FLAGS, 0, 0 }, | |
773 | { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN, | |
774 | CPU_RDSEED_FLAGS, 0, 0 }, | |
775 | { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN, | |
776 | CPU_PRFCHW_FLAGS, 0, 0 }, | |
e413e4e9 AM |
777 | }; |
778 | ||
704209c0 | 779 | #ifdef I386COFF |
a6c24e68 NC |
780 | /* Like s_lcomm_internal in gas/read.c but the alignment string |
781 | is allowed to be optional. */ | |
782 | ||
783 | static symbolS * | |
784 | pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size) | |
785 | { | |
786 | addressT align = 0; | |
787 | ||
788 | SKIP_WHITESPACE (); | |
789 | ||
7ab9ffdd | 790 | if (needs_align |
a6c24e68 NC |
791 | && *input_line_pointer == ',') |
792 | { | |
793 | align = parse_align (needs_align - 1); | |
7ab9ffdd | 794 | |
a6c24e68 NC |
795 | if (align == (addressT) -1) |
796 | return NULL; | |
797 | } | |
798 | else | |
799 | { | |
800 | if (size >= 8) | |
801 | align = 3; | |
802 | else if (size >= 4) | |
803 | align = 2; | |
804 | else if (size >= 2) | |
805 | align = 1; | |
806 | else | |
807 | align = 0; | |
808 | } | |
809 | ||
810 | bss_alloc (symbolP, size, align); | |
811 | return symbolP; | |
812 | } | |
813 | ||
704209c0 | 814 | static void |
a6c24e68 NC |
815 | pe_lcomm (int needs_align) |
816 | { | |
817 | s_comm_internal (needs_align * 2, pe_lcomm_internal); | |
818 | } | |
704209c0 | 819 | #endif |
a6c24e68 | 820 | |
29b0f896 AM |
821 | const pseudo_typeS md_pseudo_table[] = |
822 | { | |
823 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) | |
824 | {"align", s_align_bytes, 0}, | |
825 | #else | |
826 | {"align", s_align_ptwo, 0}, | |
827 | #endif | |
828 | {"arch", set_cpu_arch, 0}, | |
829 | #ifndef I386COFF | |
830 | {"bss", s_bss, 0}, | |
a6c24e68 NC |
831 | #else |
832 | {"lcomm", pe_lcomm, 1}, | |
29b0f896 AM |
833 | #endif |
834 | {"ffloat", float_cons, 'f'}, | |
835 | {"dfloat", float_cons, 'd'}, | |
836 | {"tfloat", float_cons, 'x'}, | |
837 | {"value", cons, 2}, | |
d182319b | 838 | {"slong", signed_cons, 4}, |
29b0f896 AM |
839 | {"noopt", s_ignore, 0}, |
840 | {"optim", s_ignore, 0}, | |
841 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, | |
842 | {"code16", set_code_flag, CODE_16BIT}, | |
843 | {"code32", set_code_flag, CODE_32BIT}, | |
844 | {"code64", set_code_flag, CODE_64BIT}, | |
845 | {"intel_syntax", set_intel_syntax, 1}, | |
846 | {"att_syntax", set_intel_syntax, 0}, | |
1efbbeb4 L |
847 | {"intel_mnemonic", set_intel_mnemonic, 1}, |
848 | {"att_mnemonic", set_intel_mnemonic, 0}, | |
db51cc60 L |
849 | {"allow_index_reg", set_allow_index_reg, 1}, |
850 | {"disallow_index_reg", set_allow_index_reg, 0}, | |
7bab8ab5 JB |
851 | {"sse_check", set_check, 0}, |
852 | {"operand_check", set_check, 1}, | |
3b22753a L |
853 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
854 | {"largecomm", handle_large_common, 0}, | |
07a53e5c | 855 | #else |
e3bb37b5 | 856 | {"file", (void (*) (int)) dwarf2_directive_file, 0}, |
07a53e5c RH |
857 | {"loc", dwarf2_directive_loc, 0}, |
858 | {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, | |
3b22753a | 859 | #endif |
6482c264 NC |
860 | #ifdef TE_PE |
861 | {"secrel32", pe_directive_secrel, 0}, | |
862 | #endif | |
29b0f896 AM |
863 | {0, 0, 0} |
864 | }; | |
865 | ||
866 | /* For interface with expression (). */ | |
867 | extern char *input_line_pointer; | |
868 | ||
869 | /* Hash table for instruction mnemonic lookup. */ | |
870 | static struct hash_control *op_hash; | |
871 | ||
872 | /* Hash table for register lookup. */ | |
873 | static struct hash_control *reg_hash; | |
874 | \f | |
252b5132 | 875 | void |
e3bb37b5 | 876 | i386_align_code (fragS *fragP, int count) |
252b5132 | 877 | { |
ce8a8b2f AM |
878 | /* Various efficient no-op patterns for aligning code labels. |
879 | Note: Don't try to assemble the instructions in the comments. | |
880 | 0L and 0w are not legal. */ | |
252b5132 RH |
881 | static const char f32_1[] = |
882 | {0x90}; /* nop */ | |
883 | static const char f32_2[] = | |
ccc9c027 | 884 | {0x66,0x90}; /* xchg %ax,%ax */ |
252b5132 RH |
885 | static const char f32_3[] = |
886 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
887 | static const char f32_4[] = | |
888 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
889 | static const char f32_5[] = | |
890 | {0x90, /* nop */ | |
891 | 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
892 | static const char f32_6[] = | |
893 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
894 | static const char f32_7[] = | |
895 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
896 | static const char f32_8[] = | |
897 | {0x90, /* nop */ | |
898 | 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
899 | static const char f32_9[] = | |
900 | {0x89,0xf6, /* movl %esi,%esi */ | |
901 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
902 | static const char f32_10[] = | |
903 | {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ | |
904 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
905 | static const char f32_11[] = | |
906 | {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ | |
907 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
908 | static const char f32_12[] = | |
909 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
910 | 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ | |
911 | static const char f32_13[] = | |
912 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
913 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
914 | static const char f32_14[] = | |
915 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ | |
916 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
c3332e24 AM |
917 | static const char f16_3[] = |
918 | {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */ | |
252b5132 RH |
919 | static const char f16_4[] = |
920 | {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
921 | static const char f16_5[] = | |
922 | {0x90, /* nop */ | |
923 | 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
924 | static const char f16_6[] = | |
925 | {0x89,0xf6, /* mov %si,%si */ | |
926 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
927 | static const char f16_7[] = | |
928 | {0x8d,0x74,0x00, /* lea 0(%si),%si */ | |
929 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
930 | static const char f16_8[] = | |
931 | {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ | |
932 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
76bc74dc L |
933 | static const char jump_31[] = |
934 | {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */ | |
935 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90, | |
936 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90, | |
937 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; | |
252b5132 RH |
938 | static const char *const f32_patt[] = { |
939 | f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, | |
76bc74dc | 940 | f32_9, f32_10, f32_11, f32_12, f32_13, f32_14 |
252b5132 RH |
941 | }; |
942 | static const char *const f16_patt[] = { | |
76bc74dc | 943 | f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8 |
252b5132 | 944 | }; |
ccc9c027 L |
945 | /* nopl (%[re]ax) */ |
946 | static const char alt_3[] = | |
947 | {0x0f,0x1f,0x00}; | |
948 | /* nopl 0(%[re]ax) */ | |
949 | static const char alt_4[] = | |
950 | {0x0f,0x1f,0x40,0x00}; | |
951 | /* nopl 0(%[re]ax,%[re]ax,1) */ | |
952 | static const char alt_5[] = | |
953 | {0x0f,0x1f,0x44,0x00,0x00}; | |
954 | /* nopw 0(%[re]ax,%[re]ax,1) */ | |
955 | static const char alt_6[] = | |
956 | {0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
957 | /* nopl 0L(%[re]ax) */ | |
958 | static const char alt_7[] = | |
959 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
960 | /* nopl 0L(%[re]ax,%[re]ax,1) */ | |
961 | static const char alt_8[] = | |
962 | {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
963 | /* nopw 0L(%[re]ax,%[re]ax,1) */ | |
964 | static const char alt_9[] = | |
965 | {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
966 | /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
967 | static const char alt_10[] = | |
968 | {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
969 | /* data16 | |
970 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
971 | static const char alt_long_11[] = | |
972 | {0x66, | |
973 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
974 | /* data16 | |
975 | data16 | |
976 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
977 | static const char alt_long_12[] = | |
978 | {0x66, | |
979 | 0x66, | |
980 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
981 | /* data16 | |
982 | data16 | |
983 | data16 | |
984 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
985 | static const char alt_long_13[] = | |
986 | {0x66, | |
987 | 0x66, | |
988 | 0x66, | |
989 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
990 | /* data16 | |
991 | data16 | |
992 | data16 | |
993 | data16 | |
994 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
995 | static const char alt_long_14[] = | |
996 | {0x66, | |
997 | 0x66, | |
998 | 0x66, | |
999 | 0x66, | |
1000 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1001 | /* data16 | |
1002 | data16 | |
1003 | data16 | |
1004 | data16 | |
1005 | data16 | |
1006 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
1007 | static const char alt_long_15[] = | |
1008 | {0x66, | |
1009 | 0x66, | |
1010 | 0x66, | |
1011 | 0x66, | |
1012 | 0x66, | |
1013 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1014 | /* nopl 0(%[re]ax,%[re]ax,1) | |
1015 | nopw 0(%[re]ax,%[re]ax,1) */ | |
1016 | static const char alt_short_11[] = | |
1017 | {0x0f,0x1f,0x44,0x00,0x00, | |
1018 | 0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
1019 | /* nopw 0(%[re]ax,%[re]ax,1) | |
1020 | nopw 0(%[re]ax,%[re]ax,1) */ | |
1021 | static const char alt_short_12[] = | |
1022 | {0x66,0x0f,0x1f,0x44,0x00,0x00, | |
1023 | 0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
1024 | /* nopw 0(%[re]ax,%[re]ax,1) | |
1025 | nopl 0L(%[re]ax) */ | |
1026 | static const char alt_short_13[] = | |
1027 | {0x66,0x0f,0x1f,0x44,0x00,0x00, | |
1028 | 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
1029 | /* nopl 0L(%[re]ax) | |
1030 | nopl 0L(%[re]ax) */ | |
1031 | static const char alt_short_14[] = | |
1032 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00, | |
1033 | 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
1034 | /* nopl 0L(%[re]ax) | |
1035 | nopl 0L(%[re]ax,%[re]ax,1) */ | |
1036 | static const char alt_short_15[] = | |
1037 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00, | |
1038 | 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1039 | static const char *const alt_short_patt[] = { | |
1040 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
1041 | alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13, | |
1042 | alt_short_14, alt_short_15 | |
1043 | }; | |
1044 | static const char *const alt_long_patt[] = { | |
1045 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
1046 | alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13, | |
1047 | alt_long_14, alt_long_15 | |
1048 | }; | |
252b5132 | 1049 | |
76bc74dc L |
1050 | /* Only align for at least a positive non-zero boundary. */ |
1051 | if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE) | |
33fef721 | 1052 | return; |
3e73aa7c | 1053 | |
ccc9c027 L |
1054 | /* We need to decide which NOP sequence to use for 32bit and |
1055 | 64bit. When -mtune= is used: | |
4eed87de | 1056 | |
76bc74dc L |
1057 | 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and |
1058 | PROCESSOR_GENERIC32, f32_patt will be used. | |
1059 | 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA, | |
bd5295b2 L |
1060 | PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and |
1061 | PROCESSOR_GENERIC64, alt_long_patt will be used. | |
76bc74dc | 1062 | 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and |
8aedb9fe | 1063 | PROCESSOR_AMDFAM10, and PROCESSOR_BD, alt_short_patt |
69dd9865 | 1064 | will be used. |
ccc9c027 | 1065 | |
76bc74dc | 1066 | When -mtune= isn't used, alt_long_patt will be used if |
22109423 | 1067 | cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will |
76bc74dc | 1068 | be used. |
ccc9c027 L |
1069 | |
1070 | When -march= or .arch is used, we can't use anything beyond | |
1071 | cpu_arch_isa_flags. */ | |
1072 | ||
1073 | if (flag_code == CODE_16BIT) | |
1074 | { | |
ccc9c027 | 1075 | if (count > 8) |
33fef721 | 1076 | { |
76bc74dc L |
1077 | memcpy (fragP->fr_literal + fragP->fr_fix, |
1078 | jump_31, count); | |
1079 | /* Adjust jump offset. */ | |
1080 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; | |
252b5132 | 1081 | } |
76bc74dc L |
1082 | else |
1083 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
1084 | f16_patt[count - 1], count); | |
252b5132 | 1085 | } |
33fef721 | 1086 | else |
ccc9c027 L |
1087 | { |
1088 | const char *const *patt = NULL; | |
1089 | ||
fbf3f584 | 1090 | if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN) |
ccc9c027 L |
1091 | { |
1092 | /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ | |
1093 | switch (cpu_arch_tune) | |
1094 | { | |
1095 | case PROCESSOR_UNKNOWN: | |
1096 | /* We use cpu_arch_isa_flags to check if we SHOULD | |
22109423 L |
1097 | optimize with nops. */ |
1098 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
76bc74dc | 1099 | patt = alt_long_patt; |
ccc9c027 L |
1100 | else |
1101 | patt = f32_patt; | |
1102 | break; | |
ccc9c027 L |
1103 | case PROCESSOR_PENTIUM4: |
1104 | case PROCESSOR_NOCONA: | |
ef05d495 | 1105 | case PROCESSOR_CORE: |
76bc74dc | 1106 | case PROCESSOR_CORE2: |
bd5295b2 | 1107 | case PROCESSOR_COREI7: |
3632d14b | 1108 | case PROCESSOR_L1OM: |
7a9068fe | 1109 | case PROCESSOR_K1OM: |
76bc74dc L |
1110 | case PROCESSOR_GENERIC64: |
1111 | patt = alt_long_patt; | |
1112 | break; | |
ccc9c027 L |
1113 | case PROCESSOR_K6: |
1114 | case PROCESSOR_ATHLON: | |
1115 | case PROCESSOR_K8: | |
4eed87de | 1116 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1117 | case PROCESSOR_BD: |
ccc9c027 L |
1118 | patt = alt_short_patt; |
1119 | break; | |
76bc74dc | 1120 | case PROCESSOR_I386: |
ccc9c027 L |
1121 | case PROCESSOR_I486: |
1122 | case PROCESSOR_PENTIUM: | |
2dde1948 | 1123 | case PROCESSOR_PENTIUMPRO: |
ccc9c027 L |
1124 | case PROCESSOR_GENERIC32: |
1125 | patt = f32_patt; | |
1126 | break; | |
4eed87de | 1127 | } |
ccc9c027 L |
1128 | } |
1129 | else | |
1130 | { | |
fbf3f584 | 1131 | switch (fragP->tc_frag_data.tune) |
ccc9c027 L |
1132 | { |
1133 | case PROCESSOR_UNKNOWN: | |
e6a14101 | 1134 | /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be |
ccc9c027 L |
1135 | PROCESSOR_UNKNOWN. */ |
1136 | abort (); | |
1137 | break; | |
1138 | ||
76bc74dc | 1139 | case PROCESSOR_I386: |
ccc9c027 L |
1140 | case PROCESSOR_I486: |
1141 | case PROCESSOR_PENTIUM: | |
ccc9c027 L |
1142 | case PROCESSOR_K6: |
1143 | case PROCESSOR_ATHLON: | |
1144 | case PROCESSOR_K8: | |
4eed87de | 1145 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1146 | case PROCESSOR_BD: |
ccc9c027 L |
1147 | case PROCESSOR_GENERIC32: |
1148 | /* We use cpu_arch_isa_flags to check if we CAN optimize | |
22109423 L |
1149 | with nops. */ |
1150 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
ccc9c027 L |
1151 | patt = alt_short_patt; |
1152 | else | |
1153 | patt = f32_patt; | |
1154 | break; | |
76bc74dc L |
1155 | case PROCESSOR_PENTIUMPRO: |
1156 | case PROCESSOR_PENTIUM4: | |
1157 | case PROCESSOR_NOCONA: | |
1158 | case PROCESSOR_CORE: | |
ef05d495 | 1159 | case PROCESSOR_CORE2: |
bd5295b2 | 1160 | case PROCESSOR_COREI7: |
3632d14b | 1161 | case PROCESSOR_L1OM: |
7a9068fe | 1162 | case PROCESSOR_K1OM: |
22109423 | 1163 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) |
ccc9c027 L |
1164 | patt = alt_long_patt; |
1165 | else | |
1166 | patt = f32_patt; | |
1167 | break; | |
1168 | case PROCESSOR_GENERIC64: | |
76bc74dc | 1169 | patt = alt_long_patt; |
ccc9c027 | 1170 | break; |
4eed87de | 1171 | } |
ccc9c027 L |
1172 | } |
1173 | ||
76bc74dc L |
1174 | if (patt == f32_patt) |
1175 | { | |
1176 | /* If the padding is less than 15 bytes, we use the normal | |
1177 | ones. Otherwise, we use a jump instruction and adjust | |
711eedef L |
1178 | its offset. */ |
1179 | int limit; | |
76ba9986 | 1180 | |
711eedef L |
1181 | /* For 64bit, the limit is 3 bytes. */ |
1182 | if (flag_code == CODE_64BIT | |
1183 | && fragP->tc_frag_data.isa_flags.bitfield.cpulm) | |
1184 | limit = 3; | |
1185 | else | |
1186 | limit = 15; | |
1187 | if (count < limit) | |
76bc74dc L |
1188 | memcpy (fragP->fr_literal + fragP->fr_fix, |
1189 | patt[count - 1], count); | |
1190 | else | |
1191 | { | |
1192 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
1193 | jump_31, count); | |
1194 | /* Adjust jump offset. */ | |
1195 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; | |
1196 | } | |
1197 | } | |
1198 | else | |
1199 | { | |
1200 | /* Maximum length of an instruction is 15 byte. If the | |
1201 | padding is greater than 15 bytes and we don't use jump, | |
1202 | we have to break it into smaller pieces. */ | |
1203 | int padding = count; | |
1204 | while (padding > 15) | |
1205 | { | |
1206 | padding -= 15; | |
1207 | memcpy (fragP->fr_literal + fragP->fr_fix + padding, | |
1208 | patt [14], 15); | |
1209 | } | |
1210 | ||
1211 | if (padding) | |
1212 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
1213 | patt [padding - 1], padding); | |
1214 | } | |
ccc9c027 | 1215 | } |
33fef721 | 1216 | fragP->fr_var = count; |
252b5132 RH |
1217 | } |
1218 | ||
c6fb90c8 | 1219 | static INLINE int |
0dfbf9d7 | 1220 | operand_type_all_zero (const union i386_operand_type *x) |
40fb9820 | 1221 | { |
0dfbf9d7 | 1222 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1223 | { |
1224 | case 3: | |
0dfbf9d7 | 1225 | if (x->array[2]) |
c6fb90c8 L |
1226 | return 0; |
1227 | case 2: | |
0dfbf9d7 | 1228 | if (x->array[1]) |
c6fb90c8 L |
1229 | return 0; |
1230 | case 1: | |
0dfbf9d7 | 1231 | return !x->array[0]; |
c6fb90c8 L |
1232 | default: |
1233 | abort (); | |
1234 | } | |
40fb9820 L |
1235 | } |
1236 | ||
c6fb90c8 | 1237 | static INLINE void |
0dfbf9d7 | 1238 | operand_type_set (union i386_operand_type *x, unsigned int v) |
40fb9820 | 1239 | { |
0dfbf9d7 | 1240 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1241 | { |
1242 | case 3: | |
0dfbf9d7 | 1243 | x->array[2] = v; |
c6fb90c8 | 1244 | case 2: |
0dfbf9d7 | 1245 | x->array[1] = v; |
c6fb90c8 | 1246 | case 1: |
0dfbf9d7 | 1247 | x->array[0] = v; |
c6fb90c8 L |
1248 | break; |
1249 | default: | |
1250 | abort (); | |
1251 | } | |
1252 | } | |
40fb9820 | 1253 | |
c6fb90c8 | 1254 | static INLINE int |
0dfbf9d7 L |
1255 | operand_type_equal (const union i386_operand_type *x, |
1256 | const union i386_operand_type *y) | |
c6fb90c8 | 1257 | { |
0dfbf9d7 | 1258 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1259 | { |
1260 | case 3: | |
0dfbf9d7 | 1261 | if (x->array[2] != y->array[2]) |
c6fb90c8 L |
1262 | return 0; |
1263 | case 2: | |
0dfbf9d7 | 1264 | if (x->array[1] != y->array[1]) |
c6fb90c8 L |
1265 | return 0; |
1266 | case 1: | |
0dfbf9d7 | 1267 | return x->array[0] == y->array[0]; |
c6fb90c8 L |
1268 | break; |
1269 | default: | |
1270 | abort (); | |
1271 | } | |
1272 | } | |
40fb9820 | 1273 | |
0dfbf9d7 L |
1274 | static INLINE int |
1275 | cpu_flags_all_zero (const union i386_cpu_flags *x) | |
1276 | { | |
1277 | switch (ARRAY_SIZE(x->array)) | |
1278 | { | |
1279 | case 3: | |
1280 | if (x->array[2]) | |
1281 | return 0; | |
1282 | case 2: | |
1283 | if (x->array[1]) | |
1284 | return 0; | |
1285 | case 1: | |
1286 | return !x->array[0]; | |
1287 | default: | |
1288 | abort (); | |
1289 | } | |
1290 | } | |
1291 | ||
1292 | static INLINE void | |
1293 | cpu_flags_set (union i386_cpu_flags *x, unsigned int v) | |
1294 | { | |
1295 | switch (ARRAY_SIZE(x->array)) | |
1296 | { | |
1297 | case 3: | |
1298 | x->array[2] = v; | |
1299 | case 2: | |
1300 | x->array[1] = v; | |
1301 | case 1: | |
1302 | x->array[0] = v; | |
1303 | break; | |
1304 | default: | |
1305 | abort (); | |
1306 | } | |
1307 | } | |
1308 | ||
1309 | static INLINE int | |
1310 | cpu_flags_equal (const union i386_cpu_flags *x, | |
1311 | const union i386_cpu_flags *y) | |
1312 | { | |
1313 | switch (ARRAY_SIZE(x->array)) | |
1314 | { | |
1315 | case 3: | |
1316 | if (x->array[2] != y->array[2]) | |
1317 | return 0; | |
1318 | case 2: | |
1319 | if (x->array[1] != y->array[1]) | |
1320 | return 0; | |
1321 | case 1: | |
1322 | return x->array[0] == y->array[0]; | |
1323 | break; | |
1324 | default: | |
1325 | abort (); | |
1326 | } | |
1327 | } | |
c6fb90c8 L |
1328 | |
1329 | static INLINE int | |
1330 | cpu_flags_check_cpu64 (i386_cpu_flags f) | |
1331 | { | |
1332 | return !((flag_code == CODE_64BIT && f.bitfield.cpuno64) | |
1333 | || (flag_code != CODE_64BIT && f.bitfield.cpu64)); | |
40fb9820 L |
1334 | } |
1335 | ||
c6fb90c8 L |
1336 | static INLINE i386_cpu_flags |
1337 | cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1338 | { |
c6fb90c8 L |
1339 | switch (ARRAY_SIZE (x.array)) |
1340 | { | |
1341 | case 3: | |
1342 | x.array [2] &= y.array [2]; | |
1343 | case 2: | |
1344 | x.array [1] &= y.array [1]; | |
1345 | case 1: | |
1346 | x.array [0] &= y.array [0]; | |
1347 | break; | |
1348 | default: | |
1349 | abort (); | |
1350 | } | |
1351 | return x; | |
1352 | } | |
40fb9820 | 1353 | |
c6fb90c8 L |
1354 | static INLINE i386_cpu_flags |
1355 | cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1356 | { |
c6fb90c8 | 1357 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1358 | { |
c6fb90c8 L |
1359 | case 3: |
1360 | x.array [2] |= y.array [2]; | |
1361 | case 2: | |
1362 | x.array [1] |= y.array [1]; | |
1363 | case 1: | |
1364 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1365 | break; |
1366 | default: | |
1367 | abort (); | |
1368 | } | |
40fb9820 L |
1369 | return x; |
1370 | } | |
1371 | ||
309d3373 JB |
1372 | static INLINE i386_cpu_flags |
1373 | cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y) | |
1374 | { | |
1375 | switch (ARRAY_SIZE (x.array)) | |
1376 | { | |
1377 | case 3: | |
1378 | x.array [2] &= ~y.array [2]; | |
1379 | case 2: | |
1380 | x.array [1] &= ~y.array [1]; | |
1381 | case 1: | |
1382 | x.array [0] &= ~y.array [0]; | |
1383 | break; | |
1384 | default: | |
1385 | abort (); | |
1386 | } | |
1387 | return x; | |
1388 | } | |
1389 | ||
c0f3af97 L |
1390 | #define CPU_FLAGS_ARCH_MATCH 0x1 |
1391 | #define CPU_FLAGS_64BIT_MATCH 0x2 | |
a5ff0eb2 | 1392 | #define CPU_FLAGS_AES_MATCH 0x4 |
ce2f5b3c L |
1393 | #define CPU_FLAGS_PCLMUL_MATCH 0x8 |
1394 | #define CPU_FLAGS_AVX_MATCH 0x10 | |
c0f3af97 | 1395 | |
a5ff0eb2 | 1396 | #define CPU_FLAGS_32BIT_MATCH \ |
ce2f5b3c L |
1397 | (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \ |
1398 | | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH) | |
c0f3af97 L |
1399 | #define CPU_FLAGS_PERFECT_MATCH \ |
1400 | (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH) | |
1401 | ||
1402 | /* Return CPU flags match bits. */ | |
3629bb00 | 1403 | |
40fb9820 | 1404 | static int |
d3ce72d0 | 1405 | cpu_flags_match (const insn_template *t) |
40fb9820 | 1406 | { |
c0f3af97 L |
1407 | i386_cpu_flags x = t->cpu_flags; |
1408 | int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0; | |
40fb9820 L |
1409 | |
1410 | x.bitfield.cpu64 = 0; | |
1411 | x.bitfield.cpuno64 = 0; | |
1412 | ||
0dfbf9d7 | 1413 | if (cpu_flags_all_zero (&x)) |
c0f3af97 L |
1414 | { |
1415 | /* This instruction is available on all archs. */ | |
1416 | match |= CPU_FLAGS_32BIT_MATCH; | |
1417 | } | |
3629bb00 L |
1418 | else |
1419 | { | |
c0f3af97 | 1420 | /* This instruction is available only on some archs. */ |
3629bb00 L |
1421 | i386_cpu_flags cpu = cpu_arch_flags; |
1422 | ||
1423 | cpu.bitfield.cpu64 = 0; | |
1424 | cpu.bitfield.cpuno64 = 0; | |
1425 | cpu = cpu_flags_and (x, cpu); | |
c0f3af97 L |
1426 | if (!cpu_flags_all_zero (&cpu)) |
1427 | { | |
a5ff0eb2 L |
1428 | if (x.bitfield.cpuavx) |
1429 | { | |
ce2f5b3c | 1430 | /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */ |
a5ff0eb2 L |
1431 | if (cpu.bitfield.cpuavx) |
1432 | { | |
1433 | /* Check SSE2AVX. */ | |
1434 | if (!t->opcode_modifier.sse2avx|| sse2avx) | |
1435 | { | |
1436 | match |= (CPU_FLAGS_ARCH_MATCH | |
1437 | | CPU_FLAGS_AVX_MATCH); | |
1438 | /* Check AES. */ | |
1439 | if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes) | |
1440 | match |= CPU_FLAGS_AES_MATCH; | |
ce2f5b3c L |
1441 | /* Check PCLMUL. */ |
1442 | if (!x.bitfield.cpupclmul | |
1443 | || cpu.bitfield.cpupclmul) | |
1444 | match |= CPU_FLAGS_PCLMUL_MATCH; | |
a5ff0eb2 L |
1445 | } |
1446 | } | |
1447 | else | |
1448 | match |= CPU_FLAGS_ARCH_MATCH; | |
1449 | } | |
1450 | else | |
c0f3af97 L |
1451 | match |= CPU_FLAGS_32BIT_MATCH; |
1452 | } | |
3629bb00 | 1453 | } |
c0f3af97 | 1454 | return match; |
40fb9820 L |
1455 | } |
1456 | ||
c6fb90c8 L |
1457 | static INLINE i386_operand_type |
1458 | operand_type_and (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1459 | { |
c6fb90c8 L |
1460 | switch (ARRAY_SIZE (x.array)) |
1461 | { | |
1462 | case 3: | |
1463 | x.array [2] &= y.array [2]; | |
1464 | case 2: | |
1465 | x.array [1] &= y.array [1]; | |
1466 | case 1: | |
1467 | x.array [0] &= y.array [0]; | |
1468 | break; | |
1469 | default: | |
1470 | abort (); | |
1471 | } | |
1472 | return x; | |
40fb9820 L |
1473 | } |
1474 | ||
c6fb90c8 L |
1475 | static INLINE i386_operand_type |
1476 | operand_type_or (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1477 | { |
c6fb90c8 | 1478 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1479 | { |
c6fb90c8 L |
1480 | case 3: |
1481 | x.array [2] |= y.array [2]; | |
1482 | case 2: | |
1483 | x.array [1] |= y.array [1]; | |
1484 | case 1: | |
1485 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1486 | break; |
1487 | default: | |
1488 | abort (); | |
1489 | } | |
c6fb90c8 L |
1490 | return x; |
1491 | } | |
40fb9820 | 1492 | |
c6fb90c8 L |
1493 | static INLINE i386_operand_type |
1494 | operand_type_xor (i386_operand_type x, i386_operand_type y) | |
1495 | { | |
1496 | switch (ARRAY_SIZE (x.array)) | |
1497 | { | |
1498 | case 3: | |
1499 | x.array [2] ^= y.array [2]; | |
1500 | case 2: | |
1501 | x.array [1] ^= y.array [1]; | |
1502 | case 1: | |
1503 | x.array [0] ^= y.array [0]; | |
1504 | break; | |
1505 | default: | |
1506 | abort (); | |
1507 | } | |
40fb9820 L |
1508 | return x; |
1509 | } | |
1510 | ||
1511 | static const i386_operand_type acc32 = OPERAND_TYPE_ACC32; | |
1512 | static const i386_operand_type acc64 = OPERAND_TYPE_ACC64; | |
1513 | static const i386_operand_type control = OPERAND_TYPE_CONTROL; | |
65da13b5 L |
1514 | static const i386_operand_type inoutportreg |
1515 | = OPERAND_TYPE_INOUTPORTREG; | |
40fb9820 L |
1516 | static const i386_operand_type reg16_inoutportreg |
1517 | = OPERAND_TYPE_REG16_INOUTPORTREG; | |
1518 | static const i386_operand_type disp16 = OPERAND_TYPE_DISP16; | |
1519 | static const i386_operand_type disp32 = OPERAND_TYPE_DISP32; | |
1520 | static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S; | |
1521 | static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32; | |
1522 | static const i386_operand_type anydisp | |
1523 | = OPERAND_TYPE_ANYDISP; | |
40fb9820 | 1524 | static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM; |
c0f3af97 | 1525 | static const i386_operand_type regymm = OPERAND_TYPE_REGYMM; |
40fb9820 L |
1526 | static const i386_operand_type imm8 = OPERAND_TYPE_IMM8; |
1527 | static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S; | |
1528 | static const i386_operand_type imm16 = OPERAND_TYPE_IMM16; | |
1529 | static const i386_operand_type imm32 = OPERAND_TYPE_IMM32; | |
1530 | static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S; | |
1531 | static const i386_operand_type imm64 = OPERAND_TYPE_IMM64; | |
1532 | static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32; | |
1533 | static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S; | |
1534 | static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S; | |
a683cc34 | 1535 | static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4; |
40fb9820 L |
1536 | |
1537 | enum operand_type | |
1538 | { | |
1539 | reg, | |
40fb9820 L |
1540 | imm, |
1541 | disp, | |
1542 | anymem | |
1543 | }; | |
1544 | ||
c6fb90c8 | 1545 | static INLINE int |
40fb9820 L |
1546 | operand_type_check (i386_operand_type t, enum operand_type c) |
1547 | { | |
1548 | switch (c) | |
1549 | { | |
1550 | case reg: | |
1551 | return (t.bitfield.reg8 | |
1552 | || t.bitfield.reg16 | |
1553 | || t.bitfield.reg32 | |
1554 | || t.bitfield.reg64); | |
1555 | ||
40fb9820 L |
1556 | case imm: |
1557 | return (t.bitfield.imm8 | |
1558 | || t.bitfield.imm8s | |
1559 | || t.bitfield.imm16 | |
1560 | || t.bitfield.imm32 | |
1561 | || t.bitfield.imm32s | |
1562 | || t.bitfield.imm64); | |
1563 | ||
1564 | case disp: | |
1565 | return (t.bitfield.disp8 | |
1566 | || t.bitfield.disp16 | |
1567 | || t.bitfield.disp32 | |
1568 | || t.bitfield.disp32s | |
1569 | || t.bitfield.disp64); | |
1570 | ||
1571 | case anymem: | |
1572 | return (t.bitfield.disp8 | |
1573 | || t.bitfield.disp16 | |
1574 | || t.bitfield.disp32 | |
1575 | || t.bitfield.disp32s | |
1576 | || t.bitfield.disp64 | |
1577 | || t.bitfield.baseindex); | |
1578 | ||
1579 | default: | |
1580 | abort (); | |
1581 | } | |
2cfe26b6 AM |
1582 | |
1583 | return 0; | |
40fb9820 L |
1584 | } |
1585 | ||
5c07affc L |
1586 | /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on |
1587 | operand J for instruction template T. */ | |
1588 | ||
1589 | static INLINE int | |
d3ce72d0 | 1590 | match_reg_size (const insn_template *t, unsigned int j) |
5c07affc L |
1591 | { |
1592 | return !((i.types[j].bitfield.byte | |
1593 | && !t->operand_types[j].bitfield.byte) | |
1594 | || (i.types[j].bitfield.word | |
1595 | && !t->operand_types[j].bitfield.word) | |
1596 | || (i.types[j].bitfield.dword | |
1597 | && !t->operand_types[j].bitfield.dword) | |
1598 | || (i.types[j].bitfield.qword | |
1599 | && !t->operand_types[j].bitfield.qword)); | |
1600 | } | |
1601 | ||
1602 | /* Return 1 if there is no conflict in any size on operand J for | |
1603 | instruction template T. */ | |
1604 | ||
1605 | static INLINE int | |
d3ce72d0 | 1606 | match_mem_size (const insn_template *t, unsigned int j) |
5c07affc L |
1607 | { |
1608 | return (match_reg_size (t, j) | |
1609 | && !((i.types[j].bitfield.unspecified | |
1610 | && !t->operand_types[j].bitfield.unspecified) | |
1611 | || (i.types[j].bitfield.fword | |
1612 | && !t->operand_types[j].bitfield.fword) | |
1613 | || (i.types[j].bitfield.tbyte | |
1614 | && !t->operand_types[j].bitfield.tbyte) | |
1615 | || (i.types[j].bitfield.xmmword | |
c0f3af97 L |
1616 | && !t->operand_types[j].bitfield.xmmword) |
1617 | || (i.types[j].bitfield.ymmword | |
1618 | && !t->operand_types[j].bitfield.ymmword))); | |
5c07affc L |
1619 | } |
1620 | ||
1621 | /* Return 1 if there is no size conflict on any operands for | |
1622 | instruction template T. */ | |
1623 | ||
1624 | static INLINE int | |
d3ce72d0 | 1625 | operand_size_match (const insn_template *t) |
5c07affc L |
1626 | { |
1627 | unsigned int j; | |
1628 | int match = 1; | |
1629 | ||
1630 | /* Don't check jump instructions. */ | |
1631 | if (t->opcode_modifier.jump | |
1632 | || t->opcode_modifier.jumpbyte | |
1633 | || t->opcode_modifier.jumpdword | |
1634 | || t->opcode_modifier.jumpintersegment) | |
1635 | return match; | |
1636 | ||
1637 | /* Check memory and accumulator operand size. */ | |
1638 | for (j = 0; j < i.operands; j++) | |
1639 | { | |
1640 | if (t->operand_types[j].bitfield.anysize) | |
1641 | continue; | |
1642 | ||
1643 | if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j)) | |
1644 | { | |
1645 | match = 0; | |
1646 | break; | |
1647 | } | |
1648 | ||
1649 | if (i.types[j].bitfield.mem && !match_mem_size (t, j)) | |
1650 | { | |
1651 | match = 0; | |
1652 | break; | |
1653 | } | |
1654 | } | |
1655 | ||
891edac4 | 1656 | if (match) |
5c07affc | 1657 | return match; |
891edac4 L |
1658 | else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd) |
1659 | { | |
1660 | mismatch: | |
86e026a4 | 1661 | i.error = operand_size_mismatch; |
891edac4 L |
1662 | return 0; |
1663 | } | |
5c07affc L |
1664 | |
1665 | /* Check reverse. */ | |
9c2799c2 | 1666 | gas_assert (i.operands == 2); |
5c07affc L |
1667 | |
1668 | match = 1; | |
1669 | for (j = 0; j < 2; j++) | |
1670 | { | |
1671 | if (t->operand_types[j].bitfield.acc | |
1672 | && !match_reg_size (t, j ? 0 : 1)) | |
891edac4 | 1673 | goto mismatch; |
5c07affc L |
1674 | |
1675 | if (i.types[j].bitfield.mem | |
1676 | && !match_mem_size (t, j ? 0 : 1)) | |
891edac4 | 1677 | goto mismatch; |
5c07affc L |
1678 | } |
1679 | ||
1680 | return match; | |
1681 | } | |
1682 | ||
c6fb90c8 | 1683 | static INLINE int |
40fb9820 L |
1684 | operand_type_match (i386_operand_type overlap, |
1685 | i386_operand_type given) | |
1686 | { | |
1687 | i386_operand_type temp = overlap; | |
1688 | ||
1689 | temp.bitfield.jumpabsolute = 0; | |
7d5e4556 | 1690 | temp.bitfield.unspecified = 0; |
5c07affc L |
1691 | temp.bitfield.byte = 0; |
1692 | temp.bitfield.word = 0; | |
1693 | temp.bitfield.dword = 0; | |
1694 | temp.bitfield.fword = 0; | |
1695 | temp.bitfield.qword = 0; | |
1696 | temp.bitfield.tbyte = 0; | |
1697 | temp.bitfield.xmmword = 0; | |
c0f3af97 | 1698 | temp.bitfield.ymmword = 0; |
0dfbf9d7 | 1699 | if (operand_type_all_zero (&temp)) |
891edac4 | 1700 | goto mismatch; |
40fb9820 | 1701 | |
891edac4 L |
1702 | if (given.bitfield.baseindex == overlap.bitfield.baseindex |
1703 | && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute) | |
1704 | return 1; | |
1705 | ||
1706 | mismatch: | |
a65babc9 | 1707 | i.error = operand_type_mismatch; |
891edac4 | 1708 | return 0; |
40fb9820 L |
1709 | } |
1710 | ||
7d5e4556 | 1711 | /* If given types g0 and g1 are registers they must be of the same type |
40fb9820 L |
1712 | unless the expected operand type register overlap is null. |
1713 | Note that Acc in a template matches every size of reg. */ | |
1714 | ||
c6fb90c8 | 1715 | static INLINE int |
40fb9820 L |
1716 | operand_type_register_match (i386_operand_type m0, |
1717 | i386_operand_type g0, | |
1718 | i386_operand_type t0, | |
1719 | i386_operand_type m1, | |
1720 | i386_operand_type g1, | |
1721 | i386_operand_type t1) | |
1722 | { | |
1723 | if (!operand_type_check (g0, reg)) | |
1724 | return 1; | |
1725 | ||
1726 | if (!operand_type_check (g1, reg)) | |
1727 | return 1; | |
1728 | ||
1729 | if (g0.bitfield.reg8 == g1.bitfield.reg8 | |
1730 | && g0.bitfield.reg16 == g1.bitfield.reg16 | |
1731 | && g0.bitfield.reg32 == g1.bitfield.reg32 | |
1732 | && g0.bitfield.reg64 == g1.bitfield.reg64) | |
1733 | return 1; | |
1734 | ||
1735 | if (m0.bitfield.acc) | |
1736 | { | |
1737 | t0.bitfield.reg8 = 1; | |
1738 | t0.bitfield.reg16 = 1; | |
1739 | t0.bitfield.reg32 = 1; | |
1740 | t0.bitfield.reg64 = 1; | |
1741 | } | |
1742 | ||
1743 | if (m1.bitfield.acc) | |
1744 | { | |
1745 | t1.bitfield.reg8 = 1; | |
1746 | t1.bitfield.reg16 = 1; | |
1747 | t1.bitfield.reg32 = 1; | |
1748 | t1.bitfield.reg64 = 1; | |
1749 | } | |
1750 | ||
891edac4 L |
1751 | if (!(t0.bitfield.reg8 & t1.bitfield.reg8) |
1752 | && !(t0.bitfield.reg16 & t1.bitfield.reg16) | |
1753 | && !(t0.bitfield.reg32 & t1.bitfield.reg32) | |
1754 | && !(t0.bitfield.reg64 & t1.bitfield.reg64)) | |
1755 | return 1; | |
1756 | ||
a65babc9 | 1757 | i.error = register_type_mismatch; |
891edac4 L |
1758 | |
1759 | return 0; | |
40fb9820 L |
1760 | } |
1761 | ||
4c692bc7 JB |
1762 | static INLINE unsigned int |
1763 | register_number (const reg_entry *r) | |
1764 | { | |
1765 | unsigned int nr = r->reg_num; | |
1766 | ||
1767 | if (r->reg_flags & RegRex) | |
1768 | nr += 8; | |
1769 | ||
1770 | return nr; | |
1771 | } | |
1772 | ||
252b5132 | 1773 | static INLINE unsigned int |
40fb9820 | 1774 | mode_from_disp_size (i386_operand_type t) |
252b5132 | 1775 | { |
40fb9820 L |
1776 | if (t.bitfield.disp8) |
1777 | return 1; | |
1778 | else if (t.bitfield.disp16 | |
1779 | || t.bitfield.disp32 | |
1780 | || t.bitfield.disp32s) | |
1781 | return 2; | |
1782 | else | |
1783 | return 0; | |
252b5132 RH |
1784 | } |
1785 | ||
1786 | static INLINE int | |
e3bb37b5 | 1787 | fits_in_signed_byte (offsetT num) |
252b5132 RH |
1788 | { |
1789 | return (num >= -128) && (num <= 127); | |
47926f60 | 1790 | } |
252b5132 RH |
1791 | |
1792 | static INLINE int | |
e3bb37b5 | 1793 | fits_in_unsigned_byte (offsetT num) |
252b5132 RH |
1794 | { |
1795 | return (num & 0xff) == num; | |
47926f60 | 1796 | } |
252b5132 RH |
1797 | |
1798 | static INLINE int | |
e3bb37b5 | 1799 | fits_in_unsigned_word (offsetT num) |
252b5132 RH |
1800 | { |
1801 | return (num & 0xffff) == num; | |
47926f60 | 1802 | } |
252b5132 RH |
1803 | |
1804 | static INLINE int | |
e3bb37b5 | 1805 | fits_in_signed_word (offsetT num) |
252b5132 RH |
1806 | { |
1807 | return (-32768 <= num) && (num <= 32767); | |
47926f60 | 1808 | } |
2a962e6d | 1809 | |
3e73aa7c | 1810 | static INLINE int |
e3bb37b5 | 1811 | fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
1812 | { |
1813 | #ifndef BFD64 | |
1814 | return 1; | |
1815 | #else | |
1816 | return (!(((offsetT) -1 << 31) & num) | |
1817 | || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31)); | |
1818 | #endif | |
1819 | } /* fits_in_signed_long() */ | |
2a962e6d | 1820 | |
3e73aa7c | 1821 | static INLINE int |
e3bb37b5 | 1822 | fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
1823 | { |
1824 | #ifndef BFD64 | |
1825 | return 1; | |
1826 | #else | |
1827 | return (num & (((offsetT) 2 << 31) - 1)) == num; | |
1828 | #endif | |
1829 | } /* fits_in_unsigned_long() */ | |
252b5132 | 1830 | |
a683cc34 SP |
1831 | static INLINE int |
1832 | fits_in_imm4 (offsetT num) | |
1833 | { | |
1834 | return (num & 0xf) == num; | |
1835 | } | |
1836 | ||
40fb9820 | 1837 | static i386_operand_type |
e3bb37b5 | 1838 | smallest_imm_type (offsetT num) |
252b5132 | 1839 | { |
40fb9820 | 1840 | i386_operand_type t; |
7ab9ffdd | 1841 | |
0dfbf9d7 | 1842 | operand_type_set (&t, 0); |
40fb9820 L |
1843 | t.bitfield.imm64 = 1; |
1844 | ||
1845 | if (cpu_arch_tune != PROCESSOR_I486 && num == 1) | |
e413e4e9 AM |
1846 | { |
1847 | /* This code is disabled on the 486 because all the Imm1 forms | |
1848 | in the opcode table are slower on the i486. They're the | |
1849 | versions with the implicitly specified single-position | |
1850 | displacement, which has another syntax if you really want to | |
1851 | use that form. */ | |
40fb9820 L |
1852 | t.bitfield.imm1 = 1; |
1853 | t.bitfield.imm8 = 1; | |
1854 | t.bitfield.imm8s = 1; | |
1855 | t.bitfield.imm16 = 1; | |
1856 | t.bitfield.imm32 = 1; | |
1857 | t.bitfield.imm32s = 1; | |
1858 | } | |
1859 | else if (fits_in_signed_byte (num)) | |
1860 | { | |
1861 | t.bitfield.imm8 = 1; | |
1862 | t.bitfield.imm8s = 1; | |
1863 | t.bitfield.imm16 = 1; | |
1864 | t.bitfield.imm32 = 1; | |
1865 | t.bitfield.imm32s = 1; | |
1866 | } | |
1867 | else if (fits_in_unsigned_byte (num)) | |
1868 | { | |
1869 | t.bitfield.imm8 = 1; | |
1870 | t.bitfield.imm16 = 1; | |
1871 | t.bitfield.imm32 = 1; | |
1872 | t.bitfield.imm32s = 1; | |
1873 | } | |
1874 | else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
1875 | { | |
1876 | t.bitfield.imm16 = 1; | |
1877 | t.bitfield.imm32 = 1; | |
1878 | t.bitfield.imm32s = 1; | |
1879 | } | |
1880 | else if (fits_in_signed_long (num)) | |
1881 | { | |
1882 | t.bitfield.imm32 = 1; | |
1883 | t.bitfield.imm32s = 1; | |
1884 | } | |
1885 | else if (fits_in_unsigned_long (num)) | |
1886 | t.bitfield.imm32 = 1; | |
1887 | ||
1888 | return t; | |
47926f60 | 1889 | } |
252b5132 | 1890 | |
847f7ad4 | 1891 | static offsetT |
e3bb37b5 | 1892 | offset_in_range (offsetT val, int size) |
847f7ad4 | 1893 | { |
508866be | 1894 | addressT mask; |
ba2adb93 | 1895 | |
847f7ad4 AM |
1896 | switch (size) |
1897 | { | |
508866be L |
1898 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
1899 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 1900 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
3e73aa7c JH |
1901 | #ifdef BFD64 |
1902 | case 8: mask = ((addressT) 2 << 63) - 1; break; | |
1903 | #endif | |
47926f60 | 1904 | default: abort (); |
847f7ad4 AM |
1905 | } |
1906 | ||
9de868bf L |
1907 | #ifdef BFD64 |
1908 | /* If BFD64, sign extend val for 32bit address mode. */ | |
1909 | if (flag_code != CODE_64BIT | |
1910 | || i.prefix[ADDR_PREFIX]) | |
3e73aa7c JH |
1911 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) |
1912 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
fa289fb8 | 1913 | #endif |
ba2adb93 | 1914 | |
47926f60 | 1915 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
847f7ad4 AM |
1916 | { |
1917 | char buf1[40], buf2[40]; | |
1918 | ||
1919 | sprint_value (buf1, val); | |
1920 | sprint_value (buf2, val & mask); | |
1921 | as_warn (_("%s shortened to %s"), buf1, buf2); | |
1922 | } | |
1923 | return val & mask; | |
1924 | } | |
1925 | ||
c32fa91d L |
1926 | enum PREFIX_GROUP |
1927 | { | |
1928 | PREFIX_EXIST = 0, | |
1929 | PREFIX_LOCK, | |
1930 | PREFIX_REP, | |
1931 | PREFIX_OTHER | |
1932 | }; | |
1933 | ||
1934 | /* Returns | |
1935 | a. PREFIX_EXIST if attempting to add a prefix where one from the | |
1936 | same class already exists. | |
1937 | b. PREFIX_LOCK if lock prefix is added. | |
1938 | c. PREFIX_REP if rep/repne prefix is added. | |
1939 | d. PREFIX_OTHER if other prefix is added. | |
1940 | */ | |
1941 | ||
1942 | static enum PREFIX_GROUP | |
e3bb37b5 | 1943 | add_prefix (unsigned int prefix) |
252b5132 | 1944 | { |
c32fa91d | 1945 | enum PREFIX_GROUP ret = PREFIX_OTHER; |
b1905489 | 1946 | unsigned int q; |
252b5132 | 1947 | |
29b0f896 AM |
1948 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
1949 | && flag_code == CODE_64BIT) | |
b1905489 | 1950 | { |
161a04f6 L |
1951 | if ((i.prefix[REX_PREFIX] & prefix & REX_W) |
1952 | || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B)) | |
1953 | && (prefix & (REX_R | REX_X | REX_B)))) | |
c32fa91d | 1954 | ret = PREFIX_EXIST; |
b1905489 JB |
1955 | q = REX_PREFIX; |
1956 | } | |
3e73aa7c | 1957 | else |
b1905489 JB |
1958 | { |
1959 | switch (prefix) | |
1960 | { | |
1961 | default: | |
1962 | abort (); | |
1963 | ||
1964 | case CS_PREFIX_OPCODE: | |
1965 | case DS_PREFIX_OPCODE: | |
1966 | case ES_PREFIX_OPCODE: | |
1967 | case FS_PREFIX_OPCODE: | |
1968 | case GS_PREFIX_OPCODE: | |
1969 | case SS_PREFIX_OPCODE: | |
1970 | q = SEG_PREFIX; | |
1971 | break; | |
1972 | ||
1973 | case REPNE_PREFIX_OPCODE: | |
1974 | case REPE_PREFIX_OPCODE: | |
c32fa91d L |
1975 | q = REP_PREFIX; |
1976 | ret = PREFIX_REP; | |
1977 | break; | |
1978 | ||
b1905489 | 1979 | case LOCK_PREFIX_OPCODE: |
c32fa91d L |
1980 | q = LOCK_PREFIX; |
1981 | ret = PREFIX_LOCK; | |
b1905489 JB |
1982 | break; |
1983 | ||
1984 | case FWAIT_OPCODE: | |
1985 | q = WAIT_PREFIX; | |
1986 | break; | |
1987 | ||
1988 | case ADDR_PREFIX_OPCODE: | |
1989 | q = ADDR_PREFIX; | |
1990 | break; | |
1991 | ||
1992 | case DATA_PREFIX_OPCODE: | |
1993 | q = DATA_PREFIX; | |
1994 | break; | |
1995 | } | |
1996 | if (i.prefix[q] != 0) | |
c32fa91d | 1997 | ret = PREFIX_EXIST; |
b1905489 | 1998 | } |
252b5132 | 1999 | |
b1905489 | 2000 | if (ret) |
252b5132 | 2001 | { |
b1905489 JB |
2002 | if (!i.prefix[q]) |
2003 | ++i.prefixes; | |
2004 | i.prefix[q] |= prefix; | |
252b5132 | 2005 | } |
b1905489 JB |
2006 | else |
2007 | as_bad (_("same type of prefix used twice")); | |
252b5132 | 2008 | |
252b5132 RH |
2009 | return ret; |
2010 | } | |
2011 | ||
2012 | static void | |
78f12dd3 | 2013 | update_code_flag (int value, int check) |
eecb386c | 2014 | { |
78f12dd3 L |
2015 | PRINTF_LIKE ((*as_error)); |
2016 | ||
1e9cc1c2 | 2017 | flag_code = (enum flag_code) value; |
40fb9820 L |
2018 | if (flag_code == CODE_64BIT) |
2019 | { | |
2020 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2021 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
40fb9820 L |
2022 | } |
2023 | else | |
2024 | { | |
2025 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2026 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
40fb9820 L |
2027 | } |
2028 | if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm ) | |
3e73aa7c | 2029 | { |
78f12dd3 L |
2030 | if (check) |
2031 | as_error = as_fatal; | |
2032 | else | |
2033 | as_error = as_bad; | |
2034 | (*as_error) (_("64bit mode not supported on `%s'."), | |
2035 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2036 | } |
40fb9820 | 2037 | if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) |
3e73aa7c | 2038 | { |
78f12dd3 L |
2039 | if (check) |
2040 | as_error = as_fatal; | |
2041 | else | |
2042 | as_error = as_bad; | |
2043 | (*as_error) (_("32bit mode not supported on `%s'."), | |
2044 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2045 | } |
eecb386c AM |
2046 | stackop_size = '\0'; |
2047 | } | |
2048 | ||
78f12dd3 L |
2049 | static void |
2050 | set_code_flag (int value) | |
2051 | { | |
2052 | update_code_flag (value, 0); | |
2053 | } | |
2054 | ||
eecb386c | 2055 | static void |
e3bb37b5 | 2056 | set_16bit_gcc_code_flag (int new_code_flag) |
252b5132 | 2057 | { |
1e9cc1c2 | 2058 | flag_code = (enum flag_code) new_code_flag; |
40fb9820 L |
2059 | if (flag_code != CODE_16BIT) |
2060 | abort (); | |
2061 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2062 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
9306ca4a | 2063 | stackop_size = LONG_MNEM_SUFFIX; |
252b5132 RH |
2064 | } |
2065 | ||
2066 | static void | |
e3bb37b5 | 2067 | set_intel_syntax (int syntax_flag) |
252b5132 RH |
2068 | { |
2069 | /* Find out if register prefixing is specified. */ | |
2070 | int ask_naked_reg = 0; | |
2071 | ||
2072 | SKIP_WHITESPACE (); | |
29b0f896 | 2073 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
252b5132 RH |
2074 | { |
2075 | char *string = input_line_pointer; | |
2076 | int e = get_symbol_end (); | |
2077 | ||
47926f60 | 2078 | if (strcmp (string, "prefix") == 0) |
252b5132 | 2079 | ask_naked_reg = 1; |
47926f60 | 2080 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
2081 | ask_naked_reg = -1; |
2082 | else | |
d0b47220 | 2083 | as_bad (_("bad argument to syntax directive.")); |
252b5132 RH |
2084 | *input_line_pointer = e; |
2085 | } | |
2086 | demand_empty_rest_of_line (); | |
c3332e24 | 2087 | |
252b5132 RH |
2088 | intel_syntax = syntax_flag; |
2089 | ||
2090 | if (ask_naked_reg == 0) | |
f86103b7 AM |
2091 | allow_naked_reg = (intel_syntax |
2092 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); | |
252b5132 RH |
2093 | else |
2094 | allow_naked_reg = (ask_naked_reg < 0); | |
9306ca4a | 2095 | |
ee86248c | 2096 | expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0); |
7ab9ffdd | 2097 | |
e4a3b5a4 | 2098 | identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; |
9306ca4a | 2099 | identifier_chars['$'] = intel_syntax ? '$' : 0; |
e4a3b5a4 | 2100 | register_prefix = allow_naked_reg ? "" : "%"; |
252b5132 RH |
2101 | } |
2102 | ||
1efbbeb4 L |
2103 | static void |
2104 | set_intel_mnemonic (int mnemonic_flag) | |
2105 | { | |
e1d4d893 | 2106 | intel_mnemonic = mnemonic_flag; |
1efbbeb4 L |
2107 | } |
2108 | ||
db51cc60 L |
2109 | static void |
2110 | set_allow_index_reg (int flag) | |
2111 | { | |
2112 | allow_index_reg = flag; | |
2113 | } | |
2114 | ||
cb19c032 | 2115 | static void |
7bab8ab5 | 2116 | set_check (int what) |
cb19c032 | 2117 | { |
7bab8ab5 JB |
2118 | enum check_kind *kind; |
2119 | const char *str; | |
2120 | ||
2121 | if (what) | |
2122 | { | |
2123 | kind = &operand_check; | |
2124 | str = "operand"; | |
2125 | } | |
2126 | else | |
2127 | { | |
2128 | kind = &sse_check; | |
2129 | str = "sse"; | |
2130 | } | |
2131 | ||
cb19c032 L |
2132 | SKIP_WHITESPACE (); |
2133 | ||
2134 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
2135 | { | |
2136 | char *string = input_line_pointer; | |
2137 | int e = get_symbol_end (); | |
2138 | ||
2139 | if (strcmp (string, "none") == 0) | |
7bab8ab5 | 2140 | *kind = check_none; |
cb19c032 | 2141 | else if (strcmp (string, "warning") == 0) |
7bab8ab5 | 2142 | *kind = check_warning; |
cb19c032 | 2143 | else if (strcmp (string, "error") == 0) |
7bab8ab5 | 2144 | *kind = check_error; |
cb19c032 | 2145 | else |
7bab8ab5 | 2146 | as_bad (_("bad argument to %s_check directive."), str); |
cb19c032 L |
2147 | *input_line_pointer = e; |
2148 | } | |
2149 | else | |
7bab8ab5 | 2150 | as_bad (_("missing argument for %s_check directive"), str); |
cb19c032 L |
2151 | |
2152 | demand_empty_rest_of_line (); | |
2153 | } | |
2154 | ||
8a9036a4 L |
2155 | static void |
2156 | check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED, | |
1e9cc1c2 | 2157 | i386_cpu_flags new_flag ATTRIBUTE_UNUSED) |
8a9036a4 L |
2158 | { |
2159 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2160 | static const char *arch; | |
2161 | ||
2162 | /* Intel LIOM is only supported on ELF. */ | |
2163 | if (!IS_ELF) | |
2164 | return; | |
2165 | ||
2166 | if (!arch) | |
2167 | { | |
2168 | /* Use cpu_arch_name if it is set in md_parse_option. Otherwise | |
2169 | use default_arch. */ | |
2170 | arch = cpu_arch_name; | |
2171 | if (!arch) | |
2172 | arch = default_arch; | |
2173 | } | |
2174 | ||
3632d14b | 2175 | /* If we are targeting Intel L1OM, we must enable it. */ |
8a9036a4 | 2176 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM |
1e9cc1c2 | 2177 | || new_flag.bitfield.cpul1om) |
8a9036a4 | 2178 | return; |
76ba9986 | 2179 | |
7a9068fe L |
2180 | /* If we are targeting Intel K1OM, we must enable it. */ |
2181 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM | |
2182 | || new_flag.bitfield.cpuk1om) | |
2183 | return; | |
2184 | ||
8a9036a4 L |
2185 | as_bad (_("`%s' is not supported on `%s'"), name, arch); |
2186 | #endif | |
2187 | } | |
2188 | ||
e413e4e9 | 2189 | static void |
e3bb37b5 | 2190 | set_cpu_arch (int dummy ATTRIBUTE_UNUSED) |
e413e4e9 | 2191 | { |
47926f60 | 2192 | SKIP_WHITESPACE (); |
e413e4e9 | 2193 | |
29b0f896 | 2194 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
e413e4e9 AM |
2195 | { |
2196 | char *string = input_line_pointer; | |
2197 | int e = get_symbol_end (); | |
91d6fa6a | 2198 | unsigned int j; |
40fb9820 | 2199 | i386_cpu_flags flags; |
e413e4e9 | 2200 | |
91d6fa6a | 2201 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
e413e4e9 | 2202 | { |
91d6fa6a | 2203 | if (strcmp (string, cpu_arch[j].name) == 0) |
e413e4e9 | 2204 | { |
91d6fa6a | 2205 | check_cpu_arch_compatible (string, cpu_arch[j].flags); |
8a9036a4 | 2206 | |
5c6af06e JB |
2207 | if (*string != '.') |
2208 | { | |
91d6fa6a | 2209 | cpu_arch_name = cpu_arch[j].name; |
5c6af06e | 2210 | cpu_sub_arch_name = NULL; |
91d6fa6a | 2211 | cpu_arch_flags = cpu_arch[j].flags; |
40fb9820 L |
2212 | if (flag_code == CODE_64BIT) |
2213 | { | |
2214 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2215 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
2216 | } | |
2217 | else | |
2218 | { | |
2219 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2220 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
2221 | } | |
91d6fa6a NC |
2222 | cpu_arch_isa = cpu_arch[j].type; |
2223 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
ccc9c027 L |
2224 | if (!cpu_arch_tune_set) |
2225 | { | |
2226 | cpu_arch_tune = cpu_arch_isa; | |
2227 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
2228 | } | |
5c6af06e JB |
2229 | break; |
2230 | } | |
40fb9820 | 2231 | |
22109423 | 2232 | if (!cpu_arch[j].negated) |
309d3373 | 2233 | flags = cpu_flags_or (cpu_arch_flags, |
91d6fa6a | 2234 | cpu_arch[j].flags); |
309d3373 JB |
2235 | else |
2236 | flags = cpu_flags_and_not (cpu_arch_flags, | |
49021df2 | 2237 | cpu_arch[j].flags); |
0dfbf9d7 | 2238 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
5c6af06e | 2239 | { |
6305a203 L |
2240 | if (cpu_sub_arch_name) |
2241 | { | |
2242 | char *name = cpu_sub_arch_name; | |
2243 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 2244 | cpu_arch[j].name, |
1bf57e9f | 2245 | (const char *) NULL); |
6305a203 L |
2246 | free (name); |
2247 | } | |
2248 | else | |
91d6fa6a | 2249 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
40fb9820 | 2250 | cpu_arch_flags = flags; |
a586129e | 2251 | cpu_arch_isa_flags = flags; |
5c6af06e JB |
2252 | } |
2253 | *input_line_pointer = e; | |
2254 | demand_empty_rest_of_line (); | |
2255 | return; | |
e413e4e9 AM |
2256 | } |
2257 | } | |
91d6fa6a | 2258 | if (j >= ARRAY_SIZE (cpu_arch)) |
e413e4e9 AM |
2259 | as_bad (_("no such architecture: `%s'"), string); |
2260 | ||
2261 | *input_line_pointer = e; | |
2262 | } | |
2263 | else | |
2264 | as_bad (_("missing cpu architecture")); | |
2265 | ||
fddf5b5b AM |
2266 | no_cond_jump_promotion = 0; |
2267 | if (*input_line_pointer == ',' | |
29b0f896 | 2268 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
fddf5b5b AM |
2269 | { |
2270 | char *string = ++input_line_pointer; | |
2271 | int e = get_symbol_end (); | |
2272 | ||
2273 | if (strcmp (string, "nojumps") == 0) | |
2274 | no_cond_jump_promotion = 1; | |
2275 | else if (strcmp (string, "jumps") == 0) | |
2276 | ; | |
2277 | else | |
2278 | as_bad (_("no such architecture modifier: `%s'"), string); | |
2279 | ||
2280 | *input_line_pointer = e; | |
2281 | } | |
2282 | ||
e413e4e9 AM |
2283 | demand_empty_rest_of_line (); |
2284 | } | |
2285 | ||
8a9036a4 L |
2286 | enum bfd_architecture |
2287 | i386_arch (void) | |
2288 | { | |
3632d14b | 2289 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 L |
2290 | { |
2291 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2292 | || flag_code != CODE_64BIT) | |
2293 | as_fatal (_("Intel L1OM is 64bit ELF only")); | |
2294 | return bfd_arch_l1om; | |
2295 | } | |
7a9068fe L |
2296 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2297 | { | |
2298 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2299 | || flag_code != CODE_64BIT) | |
2300 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2301 | return bfd_arch_k1om; | |
2302 | } | |
8a9036a4 L |
2303 | else |
2304 | return bfd_arch_i386; | |
2305 | } | |
2306 | ||
b9d79e03 | 2307 | unsigned long |
7016a5d5 | 2308 | i386_mach (void) |
b9d79e03 | 2309 | { |
351f65ca | 2310 | if (!strncmp (default_arch, "x86_64", 6)) |
8a9036a4 | 2311 | { |
3632d14b | 2312 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 2313 | { |
351f65ca L |
2314 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour |
2315 | || default_arch[6] != '\0') | |
8a9036a4 L |
2316 | as_fatal (_("Intel L1OM is 64bit ELF only")); |
2317 | return bfd_mach_l1om; | |
2318 | } | |
7a9068fe L |
2319 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2320 | { | |
2321 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2322 | || default_arch[6] != '\0') | |
2323 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2324 | return bfd_mach_k1om; | |
2325 | } | |
351f65ca | 2326 | else if (default_arch[6] == '\0') |
8a9036a4 | 2327 | return bfd_mach_x86_64; |
351f65ca L |
2328 | else |
2329 | return bfd_mach_x64_32; | |
8a9036a4 | 2330 | } |
b9d79e03 JH |
2331 | else if (!strcmp (default_arch, "i386")) |
2332 | return bfd_mach_i386_i386; | |
2333 | else | |
2b5d6a91 | 2334 | as_fatal (_("unknown architecture")); |
b9d79e03 | 2335 | } |
b9d79e03 | 2336 | \f |
252b5132 | 2337 | void |
7016a5d5 | 2338 | md_begin (void) |
252b5132 RH |
2339 | { |
2340 | const char *hash_err; | |
2341 | ||
47926f60 | 2342 | /* Initialize op_hash hash table. */ |
252b5132 RH |
2343 | op_hash = hash_new (); |
2344 | ||
2345 | { | |
d3ce72d0 | 2346 | const insn_template *optab; |
29b0f896 | 2347 | templates *core_optab; |
252b5132 | 2348 | |
47926f60 KH |
2349 | /* Setup for loop. */ |
2350 | optab = i386_optab; | |
252b5132 RH |
2351 | core_optab = (templates *) xmalloc (sizeof (templates)); |
2352 | core_optab->start = optab; | |
2353 | ||
2354 | while (1) | |
2355 | { | |
2356 | ++optab; | |
2357 | if (optab->name == NULL | |
2358 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
2359 | { | |
2360 | /* different name --> ship out current template list; | |
47926f60 | 2361 | add to hash table; & begin anew. */ |
252b5132 RH |
2362 | core_optab->end = optab; |
2363 | hash_err = hash_insert (op_hash, | |
2364 | (optab - 1)->name, | |
5a49b8ac | 2365 | (void *) core_optab); |
252b5132 RH |
2366 | if (hash_err) |
2367 | { | |
2b5d6a91 | 2368 | as_fatal (_("internal Error: Can't hash %s: %s"), |
252b5132 RH |
2369 | (optab - 1)->name, |
2370 | hash_err); | |
2371 | } | |
2372 | if (optab->name == NULL) | |
2373 | break; | |
2374 | core_optab = (templates *) xmalloc (sizeof (templates)); | |
2375 | core_optab->start = optab; | |
2376 | } | |
2377 | } | |
2378 | } | |
2379 | ||
47926f60 | 2380 | /* Initialize reg_hash hash table. */ |
252b5132 RH |
2381 | reg_hash = hash_new (); |
2382 | { | |
29b0f896 | 2383 | const reg_entry *regtab; |
c3fe08fa | 2384 | unsigned int regtab_size = i386_regtab_size; |
252b5132 | 2385 | |
c3fe08fa | 2386 | for (regtab = i386_regtab; regtab_size--; regtab++) |
252b5132 | 2387 | { |
5a49b8ac | 2388 | hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab); |
252b5132 | 2389 | if (hash_err) |
2b5d6a91 | 2390 | as_fatal (_("internal Error: Can't hash %s: %s"), |
3e73aa7c JH |
2391 | regtab->reg_name, |
2392 | hash_err); | |
252b5132 RH |
2393 | } |
2394 | } | |
2395 | ||
47926f60 | 2396 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 | 2397 | { |
29b0f896 AM |
2398 | int c; |
2399 | char *p; | |
252b5132 RH |
2400 | |
2401 | for (c = 0; c < 256; c++) | |
2402 | { | |
3882b010 | 2403 | if (ISDIGIT (c)) |
252b5132 RH |
2404 | { |
2405 | digit_chars[c] = c; | |
2406 | mnemonic_chars[c] = c; | |
2407 | register_chars[c] = c; | |
2408 | operand_chars[c] = c; | |
2409 | } | |
3882b010 | 2410 | else if (ISLOWER (c)) |
252b5132 RH |
2411 | { |
2412 | mnemonic_chars[c] = c; | |
2413 | register_chars[c] = c; | |
2414 | operand_chars[c] = c; | |
2415 | } | |
3882b010 | 2416 | else if (ISUPPER (c)) |
252b5132 | 2417 | { |
3882b010 | 2418 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
2419 | register_chars[c] = mnemonic_chars[c]; |
2420 | operand_chars[c] = c; | |
2421 | } | |
2422 | ||
3882b010 | 2423 | if (ISALPHA (c) || ISDIGIT (c)) |
252b5132 RH |
2424 | identifier_chars[c] = c; |
2425 | else if (c >= 128) | |
2426 | { | |
2427 | identifier_chars[c] = c; | |
2428 | operand_chars[c] = c; | |
2429 | } | |
2430 | } | |
2431 | ||
2432 | #ifdef LEX_AT | |
2433 | identifier_chars['@'] = '@'; | |
32137342 NC |
2434 | #endif |
2435 | #ifdef LEX_QM | |
2436 | identifier_chars['?'] = '?'; | |
2437 | operand_chars['?'] = '?'; | |
252b5132 | 2438 | #endif |
252b5132 | 2439 | digit_chars['-'] = '-'; |
c0f3af97 | 2440 | mnemonic_chars['_'] = '_'; |
791fe849 | 2441 | mnemonic_chars['-'] = '-'; |
0003779b | 2442 | mnemonic_chars['.'] = '.'; |
252b5132 RH |
2443 | identifier_chars['_'] = '_'; |
2444 | identifier_chars['.'] = '.'; | |
2445 | ||
2446 | for (p = operand_special_chars; *p != '\0'; p++) | |
2447 | operand_chars[(unsigned char) *p] = *p; | |
2448 | } | |
2449 | ||
2450 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 2451 | if (IS_ELF) |
252b5132 RH |
2452 | { |
2453 | record_alignment (text_section, 2); | |
2454 | record_alignment (data_section, 2); | |
2455 | record_alignment (bss_section, 2); | |
2456 | } | |
2457 | #endif | |
a4447b93 RH |
2458 | |
2459 | if (flag_code == CODE_64BIT) | |
2460 | { | |
ca19b261 KT |
2461 | #if defined (OBJ_COFF) && defined (TE_PE) |
2462 | x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour | |
2463 | ? 32 : 16); | |
2464 | #else | |
a4447b93 | 2465 | x86_dwarf2_return_column = 16; |
ca19b261 | 2466 | #endif |
61ff971f | 2467 | x86_cie_data_alignment = -8; |
a4447b93 RH |
2468 | } |
2469 | else | |
2470 | { | |
2471 | x86_dwarf2_return_column = 8; | |
2472 | x86_cie_data_alignment = -4; | |
2473 | } | |
252b5132 RH |
2474 | } |
2475 | ||
2476 | void | |
e3bb37b5 | 2477 | i386_print_statistics (FILE *file) |
252b5132 RH |
2478 | { |
2479 | hash_print_statistics (file, "i386 opcode", op_hash); | |
2480 | hash_print_statistics (file, "i386 register", reg_hash); | |
2481 | } | |
2482 | \f | |
252b5132 RH |
2483 | #ifdef DEBUG386 |
2484 | ||
ce8a8b2f | 2485 | /* Debugging routines for md_assemble. */ |
d3ce72d0 | 2486 | static void pte (insn_template *); |
40fb9820 | 2487 | static void pt (i386_operand_type); |
e3bb37b5 L |
2488 | static void pe (expressionS *); |
2489 | static void ps (symbolS *); | |
252b5132 RH |
2490 | |
2491 | static void | |
e3bb37b5 | 2492 | pi (char *line, i386_insn *x) |
252b5132 | 2493 | { |
09137c09 | 2494 | unsigned int j; |
252b5132 RH |
2495 | |
2496 | fprintf (stdout, "%s: template ", line); | |
2497 | pte (&x->tm); | |
09f131f2 JH |
2498 | fprintf (stdout, " address: base %s index %s scale %x\n", |
2499 | x->base_reg ? x->base_reg->reg_name : "none", | |
2500 | x->index_reg ? x->index_reg->reg_name : "none", | |
2501 | x->log2_scale_factor); | |
2502 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 2503 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
2504 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
2505 | x->sib.base, x->sib.index, x->sib.scale); | |
2506 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
161a04f6 L |
2507 | (x->rex & REX_W) != 0, |
2508 | (x->rex & REX_R) != 0, | |
2509 | (x->rex & REX_X) != 0, | |
2510 | (x->rex & REX_B) != 0); | |
09137c09 | 2511 | for (j = 0; j < x->operands; j++) |
252b5132 | 2512 | { |
09137c09 SP |
2513 | fprintf (stdout, " #%d: ", j + 1); |
2514 | pt (x->types[j]); | |
252b5132 | 2515 | fprintf (stdout, "\n"); |
09137c09 SP |
2516 | if (x->types[j].bitfield.reg8 |
2517 | || x->types[j].bitfield.reg16 | |
2518 | || x->types[j].bitfield.reg32 | |
2519 | || x->types[j].bitfield.reg64 | |
2520 | || x->types[j].bitfield.regmmx | |
2521 | || x->types[j].bitfield.regxmm | |
2522 | || x->types[j].bitfield.regymm | |
2523 | || x->types[j].bitfield.sreg2 | |
2524 | || x->types[j].bitfield.sreg3 | |
2525 | || x->types[j].bitfield.control | |
2526 | || x->types[j].bitfield.debug | |
2527 | || x->types[j].bitfield.test) | |
2528 | fprintf (stdout, "%s\n", x->op[j].regs->reg_name); | |
2529 | if (operand_type_check (x->types[j], imm)) | |
2530 | pe (x->op[j].imms); | |
2531 | if (operand_type_check (x->types[j], disp)) | |
2532 | pe (x->op[j].disps); | |
252b5132 RH |
2533 | } |
2534 | } | |
2535 | ||
2536 | static void | |
d3ce72d0 | 2537 | pte (insn_template *t) |
252b5132 | 2538 | { |
09137c09 | 2539 | unsigned int j; |
252b5132 | 2540 | fprintf (stdout, " %d operands ", t->operands); |
47926f60 | 2541 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
2542 | if (t->extension_opcode != None) |
2543 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
40fb9820 | 2544 | if (t->opcode_modifier.d) |
252b5132 | 2545 | fprintf (stdout, "D"); |
40fb9820 | 2546 | if (t->opcode_modifier.w) |
252b5132 RH |
2547 | fprintf (stdout, "W"); |
2548 | fprintf (stdout, "\n"); | |
09137c09 | 2549 | for (j = 0; j < t->operands; j++) |
252b5132 | 2550 | { |
09137c09 SP |
2551 | fprintf (stdout, " #%d type ", j + 1); |
2552 | pt (t->operand_types[j]); | |
252b5132 RH |
2553 | fprintf (stdout, "\n"); |
2554 | } | |
2555 | } | |
2556 | ||
2557 | static void | |
e3bb37b5 | 2558 | pe (expressionS *e) |
252b5132 | 2559 | { |
24eab124 | 2560 | fprintf (stdout, " operation %d\n", e->X_op); |
b77ad1d4 AM |
2561 | fprintf (stdout, " add_number %ld (%lx)\n", |
2562 | (long) e->X_add_number, (long) e->X_add_number); | |
252b5132 RH |
2563 | if (e->X_add_symbol) |
2564 | { | |
2565 | fprintf (stdout, " add_symbol "); | |
2566 | ps (e->X_add_symbol); | |
2567 | fprintf (stdout, "\n"); | |
2568 | } | |
2569 | if (e->X_op_symbol) | |
2570 | { | |
2571 | fprintf (stdout, " op_symbol "); | |
2572 | ps (e->X_op_symbol); | |
2573 | fprintf (stdout, "\n"); | |
2574 | } | |
2575 | } | |
2576 | ||
2577 | static void | |
e3bb37b5 | 2578 | ps (symbolS *s) |
252b5132 RH |
2579 | { |
2580 | fprintf (stdout, "%s type %s%s", | |
2581 | S_GET_NAME (s), | |
2582 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
2583 | segment_name (S_GET_SEGMENT (s))); | |
2584 | } | |
2585 | ||
7b81dfbb | 2586 | static struct type_name |
252b5132 | 2587 | { |
40fb9820 L |
2588 | i386_operand_type mask; |
2589 | const char *name; | |
252b5132 | 2590 | } |
7b81dfbb | 2591 | const type_names[] = |
252b5132 | 2592 | { |
40fb9820 L |
2593 | { OPERAND_TYPE_REG8, "r8" }, |
2594 | { OPERAND_TYPE_REG16, "r16" }, | |
2595 | { OPERAND_TYPE_REG32, "r32" }, | |
2596 | { OPERAND_TYPE_REG64, "r64" }, | |
2597 | { OPERAND_TYPE_IMM8, "i8" }, | |
2598 | { OPERAND_TYPE_IMM8, "i8s" }, | |
2599 | { OPERAND_TYPE_IMM16, "i16" }, | |
2600 | { OPERAND_TYPE_IMM32, "i32" }, | |
2601 | { OPERAND_TYPE_IMM32S, "i32s" }, | |
2602 | { OPERAND_TYPE_IMM64, "i64" }, | |
2603 | { OPERAND_TYPE_IMM1, "i1" }, | |
2604 | { OPERAND_TYPE_BASEINDEX, "BaseIndex" }, | |
2605 | { OPERAND_TYPE_DISP8, "d8" }, | |
2606 | { OPERAND_TYPE_DISP16, "d16" }, | |
2607 | { OPERAND_TYPE_DISP32, "d32" }, | |
2608 | { OPERAND_TYPE_DISP32S, "d32s" }, | |
2609 | { OPERAND_TYPE_DISP64, "d64" }, | |
2610 | { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" }, | |
2611 | { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" }, | |
2612 | { OPERAND_TYPE_CONTROL, "control reg" }, | |
2613 | { OPERAND_TYPE_TEST, "test reg" }, | |
2614 | { OPERAND_TYPE_DEBUG, "debug reg" }, | |
2615 | { OPERAND_TYPE_FLOATREG, "FReg" }, | |
2616 | { OPERAND_TYPE_FLOATACC, "FAcc" }, | |
2617 | { OPERAND_TYPE_SREG2, "SReg2" }, | |
2618 | { OPERAND_TYPE_SREG3, "SReg3" }, | |
2619 | { OPERAND_TYPE_ACC, "Acc" }, | |
2620 | { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" }, | |
2621 | { OPERAND_TYPE_REGMMX, "rMMX" }, | |
2622 | { OPERAND_TYPE_REGXMM, "rXMM" }, | |
0349dc08 | 2623 | { OPERAND_TYPE_REGYMM, "rYMM" }, |
40fb9820 | 2624 | { OPERAND_TYPE_ESSEG, "es" }, |
252b5132 RH |
2625 | }; |
2626 | ||
2627 | static void | |
40fb9820 | 2628 | pt (i386_operand_type t) |
252b5132 | 2629 | { |
40fb9820 | 2630 | unsigned int j; |
c6fb90c8 | 2631 | i386_operand_type a; |
252b5132 | 2632 | |
40fb9820 | 2633 | for (j = 0; j < ARRAY_SIZE (type_names); j++) |
c6fb90c8 L |
2634 | { |
2635 | a = operand_type_and (t, type_names[j].mask); | |
0349dc08 | 2636 | if (!operand_type_all_zero (&a)) |
c6fb90c8 L |
2637 | fprintf (stdout, "%s, ", type_names[j].name); |
2638 | } | |
252b5132 RH |
2639 | fflush (stdout); |
2640 | } | |
2641 | ||
2642 | #endif /* DEBUG386 */ | |
2643 | \f | |
252b5132 | 2644 | static bfd_reloc_code_real_type |
3956db08 | 2645 | reloc (unsigned int size, |
64e74474 AM |
2646 | int pcrel, |
2647 | int sign, | |
2648 | bfd_reloc_code_real_type other) | |
252b5132 | 2649 | { |
47926f60 | 2650 | if (other != NO_RELOC) |
3956db08 | 2651 | { |
91d6fa6a | 2652 | reloc_howto_type *rel; |
3956db08 JB |
2653 | |
2654 | if (size == 8) | |
2655 | switch (other) | |
2656 | { | |
64e74474 AM |
2657 | case BFD_RELOC_X86_64_GOT32: |
2658 | return BFD_RELOC_X86_64_GOT64; | |
2659 | break; | |
2660 | case BFD_RELOC_X86_64_PLTOFF64: | |
2661 | return BFD_RELOC_X86_64_PLTOFF64; | |
2662 | break; | |
2663 | case BFD_RELOC_X86_64_GOTPC32: | |
2664 | other = BFD_RELOC_X86_64_GOTPC64; | |
2665 | break; | |
2666 | case BFD_RELOC_X86_64_GOTPCREL: | |
2667 | other = BFD_RELOC_X86_64_GOTPCREL64; | |
2668 | break; | |
2669 | case BFD_RELOC_X86_64_TPOFF32: | |
2670 | other = BFD_RELOC_X86_64_TPOFF64; | |
2671 | break; | |
2672 | case BFD_RELOC_X86_64_DTPOFF32: | |
2673 | other = BFD_RELOC_X86_64_DTPOFF64; | |
2674 | break; | |
2675 | default: | |
2676 | break; | |
3956db08 | 2677 | } |
e05278af JB |
2678 | |
2679 | /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ | |
f2d8a97c | 2680 | if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc)) |
e05278af JB |
2681 | sign = -1; |
2682 | ||
91d6fa6a NC |
2683 | rel = bfd_reloc_type_lookup (stdoutput, other); |
2684 | if (!rel) | |
3956db08 | 2685 | as_bad (_("unknown relocation (%u)"), other); |
91d6fa6a | 2686 | else if (size != bfd_get_reloc_size (rel)) |
3956db08 | 2687 | as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), |
91d6fa6a | 2688 | bfd_get_reloc_size (rel), |
3956db08 | 2689 | size); |
91d6fa6a | 2690 | else if (pcrel && !rel->pc_relative) |
3956db08 | 2691 | as_bad (_("non-pc-relative relocation for pc-relative field")); |
91d6fa6a | 2692 | else if ((rel->complain_on_overflow == complain_overflow_signed |
3956db08 | 2693 | && !sign) |
91d6fa6a | 2694 | || (rel->complain_on_overflow == complain_overflow_unsigned |
64e74474 | 2695 | && sign > 0)) |
3956db08 JB |
2696 | as_bad (_("relocated field and relocation type differ in signedness")); |
2697 | else | |
2698 | return other; | |
2699 | return NO_RELOC; | |
2700 | } | |
252b5132 RH |
2701 | |
2702 | if (pcrel) | |
2703 | { | |
3e73aa7c | 2704 | if (!sign) |
3956db08 | 2705 | as_bad (_("there are no unsigned pc-relative relocations")); |
252b5132 RH |
2706 | switch (size) |
2707 | { | |
2708 | case 1: return BFD_RELOC_8_PCREL; | |
2709 | case 2: return BFD_RELOC_16_PCREL; | |
2710 | case 4: return BFD_RELOC_32_PCREL; | |
d6ab8113 | 2711 | case 8: return BFD_RELOC_64_PCREL; |
252b5132 | 2712 | } |
3956db08 | 2713 | as_bad (_("cannot do %u byte pc-relative relocation"), size); |
252b5132 RH |
2714 | } |
2715 | else | |
2716 | { | |
3956db08 | 2717 | if (sign > 0) |
e5cb08ac | 2718 | switch (size) |
3e73aa7c JH |
2719 | { |
2720 | case 4: return BFD_RELOC_X86_64_32S; | |
2721 | } | |
2722 | else | |
2723 | switch (size) | |
2724 | { | |
2725 | case 1: return BFD_RELOC_8; | |
2726 | case 2: return BFD_RELOC_16; | |
2727 | case 4: return BFD_RELOC_32; | |
2728 | case 8: return BFD_RELOC_64; | |
2729 | } | |
3956db08 JB |
2730 | as_bad (_("cannot do %s %u byte relocation"), |
2731 | sign > 0 ? "signed" : "unsigned", size); | |
252b5132 RH |
2732 | } |
2733 | ||
0cc9e1d3 | 2734 | return NO_RELOC; |
252b5132 RH |
2735 | } |
2736 | ||
47926f60 KH |
2737 | /* Here we decide which fixups can be adjusted to make them relative to |
2738 | the beginning of the section instead of the symbol. Basically we need | |
2739 | to make sure that the dynamic relocations are done correctly, so in | |
2740 | some cases we force the original symbol to be used. */ | |
2741 | ||
252b5132 | 2742 | int |
e3bb37b5 | 2743 | tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) |
252b5132 | 2744 | { |
6d249963 | 2745 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 2746 | if (!IS_ELF) |
31312f95 AM |
2747 | return 1; |
2748 | ||
a161fe53 AM |
2749 | /* Don't adjust pc-relative references to merge sections in 64-bit |
2750 | mode. */ | |
2751 | if (use_rela_relocations | |
2752 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 | |
2753 | && fixP->fx_pcrel) | |
252b5132 | 2754 | return 0; |
31312f95 | 2755 | |
8d01d9a9 AJ |
2756 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
2757 | and changed later by validate_fix. */ | |
2758 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol | |
2759 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) | |
2760 | return 0; | |
2761 | ||
ce8a8b2f | 2762 | /* adjust_reloc_syms doesn't know about the GOT. */ |
252b5132 RH |
2763 | if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF |
2764 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 | |
2765 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 | |
13ae64f3 JJ |
2766 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
2767 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM | |
2768 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 | |
2769 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 | |
37e55690 JJ |
2770 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
2771 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE | |
13ae64f3 JJ |
2772 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
2773 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE | |
67a4f2b7 AO |
2774 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC |
2775 | || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL | |
3e73aa7c JH |
2776 | || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 |
2777 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 | |
80b3ee89 | 2778 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
bffbf940 JJ |
2779 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
2780 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD | |
2781 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 | |
d6ab8113 | 2782 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 |
bffbf940 JJ |
2783 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF |
2784 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 | |
d6ab8113 JB |
2785 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 |
2786 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 | |
67a4f2b7 AO |
2787 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
2788 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL | |
252b5132 RH |
2789 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
2790 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
2791 | return 0; | |
31312f95 | 2792 | #endif |
252b5132 RH |
2793 | return 1; |
2794 | } | |
252b5132 | 2795 | |
b4cac588 | 2796 | static int |
e3bb37b5 | 2797 | intel_float_operand (const char *mnemonic) |
252b5132 | 2798 | { |
9306ca4a JB |
2799 | /* Note that the value returned is meaningful only for opcodes with (memory) |
2800 | operands, hence the code here is free to improperly handle opcodes that | |
2801 | have no operands (for better performance and smaller code). */ | |
2802 | ||
2803 | if (mnemonic[0] != 'f') | |
2804 | return 0; /* non-math */ | |
2805 | ||
2806 | switch (mnemonic[1]) | |
2807 | { | |
2808 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and | |
2809 | the fs segment override prefix not currently handled because no | |
2810 | call path can make opcodes without operands get here */ | |
2811 | case 'i': | |
2812 | return 2 /* integer op */; | |
2813 | case 'l': | |
2814 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) | |
2815 | return 3; /* fldcw/fldenv */ | |
2816 | break; | |
2817 | case 'n': | |
2818 | if (mnemonic[2] != 'o' /* fnop */) | |
2819 | return 3; /* non-waiting control op */ | |
2820 | break; | |
2821 | case 'r': | |
2822 | if (mnemonic[2] == 's') | |
2823 | return 3; /* frstor/frstpm */ | |
2824 | break; | |
2825 | case 's': | |
2826 | if (mnemonic[2] == 'a') | |
2827 | return 3; /* fsave */ | |
2828 | if (mnemonic[2] == 't') | |
2829 | { | |
2830 | switch (mnemonic[3]) | |
2831 | { | |
2832 | case 'c': /* fstcw */ | |
2833 | case 'd': /* fstdw */ | |
2834 | case 'e': /* fstenv */ | |
2835 | case 's': /* fsts[gw] */ | |
2836 | return 3; | |
2837 | } | |
2838 | } | |
2839 | break; | |
2840 | case 'x': | |
2841 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') | |
2842 | return 0; /* fxsave/fxrstor are not really math ops */ | |
2843 | break; | |
2844 | } | |
252b5132 | 2845 | |
9306ca4a | 2846 | return 1; |
252b5132 RH |
2847 | } |
2848 | ||
c0f3af97 L |
2849 | /* Build the VEX prefix. */ |
2850 | ||
2851 | static void | |
d3ce72d0 | 2852 | build_vex_prefix (const insn_template *t) |
c0f3af97 L |
2853 | { |
2854 | unsigned int register_specifier; | |
2855 | unsigned int implied_prefix; | |
2856 | unsigned int vector_length; | |
2857 | ||
2858 | /* Check register specifier. */ | |
2859 | if (i.vex.register_specifier) | |
4c692bc7 | 2860 | register_specifier = ~register_number (i.vex.register_specifier) & 0xf; |
c0f3af97 L |
2861 | else |
2862 | register_specifier = 0xf; | |
2863 | ||
fa99fab2 L |
2864 | /* Use 2-byte VEX prefix by swappping destination and source |
2865 | operand. */ | |
2866 | if (!i.swap_operand | |
2867 | && i.operands == i.reg_operands | |
7f399153 | 2868 | && i.tm.opcode_modifier.vexopcode == VEX0F |
fa99fab2 L |
2869 | && i.tm.opcode_modifier.s |
2870 | && i.rex == REX_B) | |
2871 | { | |
2872 | unsigned int xchg = i.operands - 1; | |
2873 | union i386_op temp_op; | |
2874 | i386_operand_type temp_type; | |
2875 | ||
2876 | temp_type = i.types[xchg]; | |
2877 | i.types[xchg] = i.types[0]; | |
2878 | i.types[0] = temp_type; | |
2879 | temp_op = i.op[xchg]; | |
2880 | i.op[xchg] = i.op[0]; | |
2881 | i.op[0] = temp_op; | |
2882 | ||
9c2799c2 | 2883 | gas_assert (i.rm.mode == 3); |
fa99fab2 L |
2884 | |
2885 | i.rex = REX_R; | |
2886 | xchg = i.rm.regmem; | |
2887 | i.rm.regmem = i.rm.reg; | |
2888 | i.rm.reg = xchg; | |
2889 | ||
2890 | /* Use the next insn. */ | |
2891 | i.tm = t[1]; | |
2892 | } | |
2893 | ||
539f890d L |
2894 | if (i.tm.opcode_modifier.vex == VEXScalar) |
2895 | vector_length = avxscalar; | |
2896 | else | |
2897 | vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0; | |
c0f3af97 L |
2898 | |
2899 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
2900 | { | |
2901 | case 0: | |
2902 | implied_prefix = 0; | |
2903 | break; | |
2904 | case DATA_PREFIX_OPCODE: | |
2905 | implied_prefix = 1; | |
2906 | break; | |
2907 | case REPE_PREFIX_OPCODE: | |
2908 | implied_prefix = 2; | |
2909 | break; | |
2910 | case REPNE_PREFIX_OPCODE: | |
2911 | implied_prefix = 3; | |
2912 | break; | |
2913 | default: | |
2914 | abort (); | |
2915 | } | |
2916 | ||
2917 | /* Use 2-byte VEX prefix if possible. */ | |
7f399153 | 2918 | if (i.tm.opcode_modifier.vexopcode == VEX0F |
04251de0 | 2919 | && i.tm.opcode_modifier.vexw != VEXW1 |
c0f3af97 L |
2920 | && (i.rex & (REX_W | REX_X | REX_B)) == 0) |
2921 | { | |
2922 | /* 2-byte VEX prefix. */ | |
2923 | unsigned int r; | |
2924 | ||
2925 | i.vex.length = 2; | |
2926 | i.vex.bytes[0] = 0xc5; | |
2927 | ||
2928 | /* Check the REX.R bit. */ | |
2929 | r = (i.rex & REX_R) ? 0 : 1; | |
2930 | i.vex.bytes[1] = (r << 7 | |
2931 | | register_specifier << 3 | |
2932 | | vector_length << 2 | |
2933 | | implied_prefix); | |
2934 | } | |
2935 | else | |
2936 | { | |
2937 | /* 3-byte VEX prefix. */ | |
2938 | unsigned int m, w; | |
2939 | ||
f88c9eb0 | 2940 | i.vex.length = 3; |
f88c9eb0 | 2941 | |
7f399153 | 2942 | switch (i.tm.opcode_modifier.vexopcode) |
5dd85c99 | 2943 | { |
7f399153 L |
2944 | case VEX0F: |
2945 | m = 0x1; | |
80de6e00 | 2946 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
2947 | break; |
2948 | case VEX0F38: | |
2949 | m = 0x2; | |
80de6e00 | 2950 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
2951 | break; |
2952 | case VEX0F3A: | |
2953 | m = 0x3; | |
80de6e00 | 2954 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
2955 | break; |
2956 | case XOP08: | |
5dd85c99 SP |
2957 | m = 0x8; |
2958 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
2959 | break; |
2960 | case XOP09: | |
f88c9eb0 SP |
2961 | m = 0x9; |
2962 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
2963 | break; |
2964 | case XOP0A: | |
f88c9eb0 SP |
2965 | m = 0xa; |
2966 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
2967 | break; |
2968 | default: | |
2969 | abort (); | |
f88c9eb0 | 2970 | } |
c0f3af97 | 2971 | |
c0f3af97 L |
2972 | /* The high 3 bits of the second VEX byte are 1's compliment |
2973 | of RXB bits from REX. */ | |
2974 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
2975 | ||
2976 | /* Check the REX.W bit. */ | |
2977 | w = (i.rex & REX_W) ? 1 : 0; | |
1ef99a7b | 2978 | if (i.tm.opcode_modifier.vexw) |
c0f3af97 L |
2979 | { |
2980 | if (w) | |
2981 | abort (); | |
2982 | ||
1ef99a7b | 2983 | if (i.tm.opcode_modifier.vexw == VEXW1) |
c0f3af97 L |
2984 | w = 1; |
2985 | } | |
2986 | ||
2987 | i.vex.bytes[2] = (w << 7 | |
2988 | | register_specifier << 3 | |
2989 | | vector_length << 2 | |
2990 | | implied_prefix); | |
2991 | } | |
2992 | } | |
2993 | ||
65da13b5 L |
2994 | static void |
2995 | process_immext (void) | |
2996 | { | |
2997 | expressionS *exp; | |
2998 | ||
4c692bc7 JB |
2999 | if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme) |
3000 | && i.operands > 0) | |
65da13b5 | 3001 | { |
4c692bc7 JB |
3002 | /* MONITOR/MWAIT as well as SVME instructions have fixed operands |
3003 | with an opcode suffix which is coded in the same place as an | |
3004 | 8-bit immediate field would be. | |
3005 | Here we check those operands and remove them afterwards. */ | |
65da13b5 L |
3006 | unsigned int x; |
3007 | ||
3008 | for (x = 0; x < i.operands; x++) | |
4c692bc7 | 3009 | if (register_number (i.op[x].regs) != x) |
65da13b5 | 3010 | as_bad (_("can't use register '%s%s' as operand %d in '%s'."), |
1fed0ba1 L |
3011 | register_prefix, i.op[x].regs->reg_name, x + 1, |
3012 | i.tm.name); | |
3013 | ||
3014 | i.operands = 0; | |
65da13b5 L |
3015 | } |
3016 | ||
c0f3af97 | 3017 | /* These AMD 3DNow! and SSE2 instructions have an opcode suffix |
65da13b5 L |
3018 | which is coded in the same place as an 8-bit immediate field |
3019 | would be. Here we fake an 8-bit immediate operand from the | |
3020 | opcode suffix stored in tm.extension_opcode. | |
3021 | ||
c1e679ec | 3022 | AVX instructions also use this encoding, for some of |
c0f3af97 | 3023 | 3 argument instructions. */ |
65da13b5 | 3024 | |
9c2799c2 | 3025 | gas_assert (i.imm_operands == 0 |
7ab9ffdd L |
3026 | && (i.operands <= 2 |
3027 | || (i.tm.opcode_modifier.vex | |
3028 | && i.operands <= 4))); | |
65da13b5 L |
3029 | |
3030 | exp = &im_expressions[i.imm_operands++]; | |
3031 | i.op[i.operands].imms = exp; | |
3032 | i.types[i.operands] = imm8; | |
3033 | i.operands++; | |
3034 | exp->X_op = O_constant; | |
3035 | exp->X_add_number = i.tm.extension_opcode; | |
3036 | i.tm.extension_opcode = None; | |
3037 | } | |
3038 | ||
42164a71 L |
3039 | |
3040 | static int | |
3041 | check_hle (void) | |
3042 | { | |
3043 | switch (i.tm.opcode_modifier.hleprefixok) | |
3044 | { | |
3045 | default: | |
3046 | abort (); | |
82c2def5 | 3047 | case HLEPrefixNone: |
42164a71 L |
3048 | if (i.prefix[HLE_PREFIX] == XACQUIRE_PREFIX_OPCODE) |
3049 | as_bad (_("invalid instruction `%s' after `xacquire'"), | |
3050 | i.tm.name); | |
3051 | else | |
3052 | as_bad (_("invalid instruction `%s' after `xrelease'"), | |
3053 | i.tm.name); | |
3054 | return 0; | |
82c2def5 | 3055 | case HLEPrefixLock: |
42164a71 L |
3056 | if (i.prefix[LOCK_PREFIX]) |
3057 | return 1; | |
3058 | if (i.prefix[HLE_PREFIX] == XACQUIRE_PREFIX_OPCODE) | |
3059 | as_bad (_("missing `lock' with `xacquire'")); | |
3060 | else | |
3061 | as_bad (_("missing `lock' with `xrelease'")); | |
3062 | return 0; | |
82c2def5 | 3063 | case HLEPrefixAny: |
42164a71 | 3064 | return 1; |
82c2def5 | 3065 | case HLEPrefixRelease: |
42164a71 L |
3066 | if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE) |
3067 | { | |
3068 | as_bad (_("instruction `%s' after `xacquire' not allowed"), | |
3069 | i.tm.name); | |
3070 | return 0; | |
3071 | } | |
3072 | if (i.mem_operands == 0 | |
3073 | || !operand_type_check (i.types[i.operands - 1], anymem)) | |
3074 | { | |
3075 | as_bad (_("memory destination needed for instruction `%s'" | |
3076 | " after `xrelease'"), i.tm.name); | |
3077 | return 0; | |
3078 | } | |
3079 | return 1; | |
3080 | } | |
3081 | } | |
3082 | ||
252b5132 RH |
3083 | /* This is the guts of the machine-dependent assembler. LINE points to a |
3084 | machine dependent instruction. This function is supposed to emit | |
3085 | the frags/bytes it assembles to. */ | |
3086 | ||
3087 | void | |
65da13b5 | 3088 | md_assemble (char *line) |
252b5132 | 3089 | { |
40fb9820 | 3090 | unsigned int j; |
252b5132 | 3091 | char mnemonic[MAX_MNEM_SIZE]; |
d3ce72d0 | 3092 | const insn_template *t; |
252b5132 | 3093 | |
47926f60 | 3094 | /* Initialize globals. */ |
252b5132 RH |
3095 | memset (&i, '\0', sizeof (i)); |
3096 | for (j = 0; j < MAX_OPERANDS; j++) | |
1ae12ab7 | 3097 | i.reloc[j] = NO_RELOC; |
252b5132 RH |
3098 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
3099 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 3100 | save_stack_p = save_stack; |
252b5132 RH |
3101 | |
3102 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
3103 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 3104 | start of a (possibly prefixed) mnemonic. */ |
252b5132 | 3105 | |
29b0f896 AM |
3106 | line = parse_insn (line, mnemonic); |
3107 | if (line == NULL) | |
3108 | return; | |
252b5132 | 3109 | |
29b0f896 | 3110 | line = parse_operands (line, mnemonic); |
ee86248c | 3111 | this_operand = -1; |
29b0f896 AM |
3112 | if (line == NULL) |
3113 | return; | |
252b5132 | 3114 | |
29b0f896 AM |
3115 | /* Now we've parsed the mnemonic into a set of templates, and have the |
3116 | operands at hand. */ | |
3117 | ||
3118 | /* All intel opcodes have reversed operands except for "bound" and | |
3119 | "enter". We also don't reverse intersegment "jmp" and "call" | |
3120 | instructions with 2 immediate operands so that the immediate segment | |
050dfa73 | 3121 | precedes the offset, as it does when in AT&T mode. */ |
4d456e3d L |
3122 | if (intel_syntax |
3123 | && i.operands > 1 | |
29b0f896 | 3124 | && (strcmp (mnemonic, "bound") != 0) |
30123838 | 3125 | && (strcmp (mnemonic, "invlpga") != 0) |
40fb9820 L |
3126 | && !(operand_type_check (i.types[0], imm) |
3127 | && operand_type_check (i.types[1], imm))) | |
29b0f896 AM |
3128 | swap_operands (); |
3129 | ||
ec56d5c0 JB |
3130 | /* The order of the immediates should be reversed |
3131 | for 2 immediates extrq and insertq instructions */ | |
3132 | if (i.imm_operands == 2 | |
3133 | && (strcmp (mnemonic, "extrq") == 0 | |
3134 | || strcmp (mnemonic, "insertq") == 0)) | |
3135 | swap_2_operands (0, 1); | |
3136 | ||
29b0f896 AM |
3137 | if (i.imm_operands) |
3138 | optimize_imm (); | |
3139 | ||
b300c311 L |
3140 | /* Don't optimize displacement for movabs since it only takes 64bit |
3141 | displacement. */ | |
3142 | if (i.disp_operands | |
a501d77e | 3143 | && i.disp_encoding != disp_encoding_32bit |
862be3fb L |
3144 | && (flag_code != CODE_64BIT |
3145 | || strcmp (mnemonic, "movabs") != 0)) | |
3146 | optimize_disp (); | |
29b0f896 AM |
3147 | |
3148 | /* Next, we find a template that matches the given insn, | |
3149 | making sure the overlap of the given operands types is consistent | |
3150 | with the template operand types. */ | |
252b5132 | 3151 | |
fa99fab2 | 3152 | if (!(t = match_template ())) |
29b0f896 | 3153 | return; |
252b5132 | 3154 | |
7bab8ab5 | 3155 | if (sse_check != check_none |
81f8a913 | 3156 | && !i.tm.opcode_modifier.noavx |
daf50ae7 L |
3157 | && (i.tm.cpu_flags.bitfield.cpusse |
3158 | || i.tm.cpu_flags.bitfield.cpusse2 | |
3159 | || i.tm.cpu_flags.bitfield.cpusse3 | |
3160 | || i.tm.cpu_flags.bitfield.cpussse3 | |
3161 | || i.tm.cpu_flags.bitfield.cpusse4_1 | |
3162 | || i.tm.cpu_flags.bitfield.cpusse4_2)) | |
3163 | { | |
7bab8ab5 | 3164 | (sse_check == check_warning |
daf50ae7 L |
3165 | ? as_warn |
3166 | : as_bad) (_("SSE instruction `%s' is used"), i.tm.name); | |
3167 | } | |
3168 | ||
321fd21e L |
3169 | /* Zap movzx and movsx suffix. The suffix has been set from |
3170 | "word ptr" or "byte ptr" on the source operand in Intel syntax | |
3171 | or extracted from mnemonic in AT&T syntax. But we'll use | |
3172 | the destination register to choose the suffix for encoding. */ | |
3173 | if ((i.tm.base_opcode & ~9) == 0x0fb6) | |
cd61ebfe | 3174 | { |
321fd21e L |
3175 | /* In Intel syntax, there must be a suffix. In AT&T syntax, if |
3176 | there is no suffix, the default will be byte extension. */ | |
3177 | if (i.reg_operands != 2 | |
3178 | && !i.suffix | |
7ab9ffdd | 3179 | && intel_syntax) |
321fd21e L |
3180 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); |
3181 | ||
3182 | i.suffix = 0; | |
cd61ebfe | 3183 | } |
24eab124 | 3184 | |
40fb9820 | 3185 | if (i.tm.opcode_modifier.fwait) |
29b0f896 AM |
3186 | if (!add_prefix (FWAIT_OPCODE)) |
3187 | return; | |
252b5132 | 3188 | |
c1ba0266 L |
3189 | /* Check for lock without a lockable instruction. Destination operand |
3190 | must be memory unless it is xchg (0x86). */ | |
c32fa91d L |
3191 | if (i.prefix[LOCK_PREFIX] |
3192 | && (!i.tm.opcode_modifier.islockable | |
c1ba0266 L |
3193 | || i.mem_operands == 0 |
3194 | || (i.tm.base_opcode != 0x86 | |
3195 | && !operand_type_check (i.types[i.operands - 1], anymem)))) | |
c32fa91d L |
3196 | { |
3197 | as_bad (_("expecting lockable instruction after `lock'")); | |
3198 | return; | |
3199 | } | |
3200 | ||
42164a71 L |
3201 | /* Check if HLE prefix is OK. */ |
3202 | if (i.have_hle && !check_hle ()) | |
3203 | return; | |
3204 | ||
29b0f896 | 3205 | /* Check string instruction segment overrides. */ |
40fb9820 | 3206 | if (i.tm.opcode_modifier.isstring && i.mem_operands != 0) |
29b0f896 AM |
3207 | { |
3208 | if (!check_string ()) | |
5dd0794d | 3209 | return; |
fc0763e6 | 3210 | i.disp_operands = 0; |
29b0f896 | 3211 | } |
5dd0794d | 3212 | |
29b0f896 AM |
3213 | if (!process_suffix ()) |
3214 | return; | |
e413e4e9 | 3215 | |
bc0844ae L |
3216 | /* Update operand types. */ |
3217 | for (j = 0; j < i.operands; j++) | |
3218 | i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]); | |
3219 | ||
29b0f896 AM |
3220 | /* Make still unresolved immediate matches conform to size of immediate |
3221 | given in i.suffix. */ | |
3222 | if (!finalize_imm ()) | |
3223 | return; | |
252b5132 | 3224 | |
40fb9820 | 3225 | if (i.types[0].bitfield.imm1) |
29b0f896 | 3226 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 | 3227 | |
9afe6eb8 L |
3228 | /* We only need to check those implicit registers for instructions |
3229 | with 3 operands or less. */ | |
3230 | if (i.operands <= 3) | |
3231 | for (j = 0; j < i.operands; j++) | |
3232 | if (i.types[j].bitfield.inoutportreg | |
3233 | || i.types[j].bitfield.shiftcount | |
3234 | || i.types[j].bitfield.acc | |
3235 | || i.types[j].bitfield.floatacc) | |
3236 | i.reg_operands--; | |
40fb9820 | 3237 | |
c0f3af97 L |
3238 | /* ImmExt should be processed after SSE2AVX. */ |
3239 | if (!i.tm.opcode_modifier.sse2avx | |
3240 | && i.tm.opcode_modifier.immext) | |
65da13b5 | 3241 | process_immext (); |
252b5132 | 3242 | |
29b0f896 AM |
3243 | /* For insns with operands there are more diddles to do to the opcode. */ |
3244 | if (i.operands) | |
3245 | { | |
3246 | if (!process_operands ()) | |
3247 | return; | |
3248 | } | |
40fb9820 | 3249 | else if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 AM |
3250 | { |
3251 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ | |
3252 | as_warn (_("translating to `%sp'"), i.tm.name); | |
3253 | } | |
252b5132 | 3254 | |
c0f3af97 | 3255 | if (i.tm.opcode_modifier.vex) |
fa99fab2 | 3256 | build_vex_prefix (t); |
c0f3af97 | 3257 | |
5dd85c99 SP |
3258 | /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4 |
3259 | instructions may define INT_OPCODE as well, so avoid this corner | |
3260 | case for those instructions that use MODRM. */ | |
3261 | if (i.tm.base_opcode == INT_OPCODE | |
a6461c02 SP |
3262 | && !i.tm.opcode_modifier.modrm |
3263 | && i.op[0].imms->X_add_number == 3) | |
29b0f896 AM |
3264 | { |
3265 | i.tm.base_opcode = INT3_OPCODE; | |
3266 | i.imm_operands = 0; | |
3267 | } | |
252b5132 | 3268 | |
40fb9820 L |
3269 | if ((i.tm.opcode_modifier.jump |
3270 | || i.tm.opcode_modifier.jumpbyte | |
3271 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 AM |
3272 | && i.op[0].disps->X_op == O_constant) |
3273 | { | |
3274 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
3275 | the absolute address given by the constant. Since ix86 jumps and | |
3276 | calls are pc relative, we need to generate a reloc. */ | |
3277 | i.op[0].disps->X_add_symbol = &abs_symbol; | |
3278 | i.op[0].disps->X_op = O_symbol; | |
3279 | } | |
252b5132 | 3280 | |
40fb9820 | 3281 | if (i.tm.opcode_modifier.rex64) |
161a04f6 | 3282 | i.rex |= REX_W; |
252b5132 | 3283 | |
29b0f896 AM |
3284 | /* For 8 bit registers we need an empty rex prefix. Also if the |
3285 | instruction already has a prefix, we need to convert old | |
3286 | registers to new ones. */ | |
773f551c | 3287 | |
40fb9820 | 3288 | if ((i.types[0].bitfield.reg8 |
29b0f896 | 3289 | && (i.op[0].regs->reg_flags & RegRex64) != 0) |
40fb9820 | 3290 | || (i.types[1].bitfield.reg8 |
29b0f896 | 3291 | && (i.op[1].regs->reg_flags & RegRex64) != 0) |
40fb9820 L |
3292 | || ((i.types[0].bitfield.reg8 |
3293 | || i.types[1].bitfield.reg8) | |
29b0f896 AM |
3294 | && i.rex != 0)) |
3295 | { | |
3296 | int x; | |
726c5dcd | 3297 | |
29b0f896 AM |
3298 | i.rex |= REX_OPCODE; |
3299 | for (x = 0; x < 2; x++) | |
3300 | { | |
3301 | /* Look for 8 bit operand that uses old registers. */ | |
40fb9820 | 3302 | if (i.types[x].bitfield.reg8 |
29b0f896 | 3303 | && (i.op[x].regs->reg_flags & RegRex64) == 0) |
773f551c | 3304 | { |
29b0f896 AM |
3305 | /* In case it is "hi" register, give up. */ |
3306 | if (i.op[x].regs->reg_num > 3) | |
a540244d | 3307 | as_bad (_("can't encode register '%s%s' in an " |
4eed87de | 3308 | "instruction requiring REX prefix."), |
a540244d | 3309 | register_prefix, i.op[x].regs->reg_name); |
773f551c | 3310 | |
29b0f896 AM |
3311 | /* Otherwise it is equivalent to the extended register. |
3312 | Since the encoding doesn't change this is merely | |
3313 | cosmetic cleanup for debug output. */ | |
3314 | ||
3315 | i.op[x].regs = i.op[x].regs + 8; | |
773f551c | 3316 | } |
29b0f896 AM |
3317 | } |
3318 | } | |
773f551c | 3319 | |
7ab9ffdd | 3320 | if (i.rex != 0) |
29b0f896 AM |
3321 | add_prefix (REX_OPCODE | i.rex); |
3322 | ||
3323 | /* We are ready to output the insn. */ | |
3324 | output_insn (); | |
3325 | } | |
3326 | ||
3327 | static char * | |
e3bb37b5 | 3328 | parse_insn (char *line, char *mnemonic) |
29b0f896 AM |
3329 | { |
3330 | char *l = line; | |
3331 | char *token_start = l; | |
3332 | char *mnem_p; | |
5c6af06e | 3333 | int supported; |
d3ce72d0 | 3334 | const insn_template *t; |
b6169b20 | 3335 | char *dot_p = NULL; |
29b0f896 AM |
3336 | |
3337 | /* Non-zero if we found a prefix only acceptable with string insns. */ | |
3338 | const char *expecting_string_instruction = NULL; | |
45288df1 | 3339 | |
29b0f896 AM |
3340 | while (1) |
3341 | { | |
3342 | mnem_p = mnemonic; | |
3343 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
3344 | { | |
b6169b20 L |
3345 | if (*mnem_p == '.') |
3346 | dot_p = mnem_p; | |
29b0f896 AM |
3347 | mnem_p++; |
3348 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
45288df1 | 3349 | { |
29b0f896 AM |
3350 | as_bad (_("no such instruction: `%s'"), token_start); |
3351 | return NULL; | |
3352 | } | |
3353 | l++; | |
3354 | } | |
3355 | if (!is_space_char (*l) | |
3356 | && *l != END_OF_INSN | |
e44823cf JB |
3357 | && (intel_syntax |
3358 | || (*l != PREFIX_SEPARATOR | |
3359 | && *l != ','))) | |
29b0f896 AM |
3360 | { |
3361 | as_bad (_("invalid character %s in mnemonic"), | |
3362 | output_invalid (*l)); | |
3363 | return NULL; | |
3364 | } | |
3365 | if (token_start == l) | |
3366 | { | |
e44823cf | 3367 | if (!intel_syntax && *l == PREFIX_SEPARATOR) |
29b0f896 AM |
3368 | as_bad (_("expecting prefix; got nothing")); |
3369 | else | |
3370 | as_bad (_("expecting mnemonic; got nothing")); | |
3371 | return NULL; | |
3372 | } | |
45288df1 | 3373 | |
29b0f896 | 3374 | /* Look up instruction (or prefix) via hash table. */ |
d3ce72d0 | 3375 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
47926f60 | 3376 | |
29b0f896 AM |
3377 | if (*l != END_OF_INSN |
3378 | && (!is_space_char (*l) || l[1] != END_OF_INSN) | |
3379 | && current_templates | |
40fb9820 | 3380 | && current_templates->start->opcode_modifier.isprefix) |
29b0f896 | 3381 | { |
c6fb90c8 | 3382 | if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags)) |
2dd88dca JB |
3383 | { |
3384 | as_bad ((flag_code != CODE_64BIT | |
3385 | ? _("`%s' is only supported in 64-bit mode") | |
3386 | : _("`%s' is not supported in 64-bit mode")), | |
3387 | current_templates->start->name); | |
3388 | return NULL; | |
3389 | } | |
29b0f896 AM |
3390 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
3391 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
40fb9820 L |
3392 | if ((current_templates->start->opcode_modifier.size16 |
3393 | || current_templates->start->opcode_modifier.size32) | |
29b0f896 | 3394 | && flag_code != CODE_64BIT |
40fb9820 | 3395 | && (current_templates->start->opcode_modifier.size32 |
29b0f896 AM |
3396 | ^ (flag_code == CODE_16BIT))) |
3397 | { | |
3398 | as_bad (_("redundant %s prefix"), | |
3399 | current_templates->start->name); | |
3400 | return NULL; | |
45288df1 | 3401 | } |
29b0f896 AM |
3402 | /* Add prefix, checking for repeated prefixes. */ |
3403 | switch (add_prefix (current_templates->start->base_opcode)) | |
3404 | { | |
c32fa91d | 3405 | case PREFIX_EXIST: |
29b0f896 | 3406 | return NULL; |
c32fa91d | 3407 | case PREFIX_REP: |
42164a71 L |
3408 | if (current_templates->start->cpu_flags.bitfield.cpuhle) |
3409 | i.have_hle = 1; | |
3410 | else | |
3411 | expecting_string_instruction = current_templates->start->name; | |
29b0f896 | 3412 | break; |
c32fa91d L |
3413 | default: |
3414 | break; | |
29b0f896 AM |
3415 | } |
3416 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
3417 | token_start = ++l; | |
3418 | } | |
3419 | else | |
3420 | break; | |
3421 | } | |
45288df1 | 3422 | |
30a55f88 | 3423 | if (!current_templates) |
b6169b20 | 3424 | { |
f8a5c266 L |
3425 | /* Check if we should swap operand or force 32bit displacement in |
3426 | encoding. */ | |
30a55f88 L |
3427 | if (mnem_p - 2 == dot_p && dot_p[1] == 's') |
3428 | i.swap_operand = 1; | |
8d63c93e | 3429 | else if (mnem_p - 3 == dot_p |
a501d77e L |
3430 | && dot_p[1] == 'd' |
3431 | && dot_p[2] == '8') | |
3432 | i.disp_encoding = disp_encoding_8bit; | |
8d63c93e | 3433 | else if (mnem_p - 4 == dot_p |
f8a5c266 L |
3434 | && dot_p[1] == 'd' |
3435 | && dot_p[2] == '3' | |
3436 | && dot_p[3] == '2') | |
a501d77e | 3437 | i.disp_encoding = disp_encoding_32bit; |
30a55f88 L |
3438 | else |
3439 | goto check_suffix; | |
3440 | mnem_p = dot_p; | |
3441 | *dot_p = '\0'; | |
d3ce72d0 | 3442 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
b6169b20 L |
3443 | } |
3444 | ||
29b0f896 AM |
3445 | if (!current_templates) |
3446 | { | |
b6169b20 | 3447 | check_suffix: |
29b0f896 AM |
3448 | /* See if we can get a match by trimming off a suffix. */ |
3449 | switch (mnem_p[-1]) | |
3450 | { | |
3451 | case WORD_MNEM_SUFFIX: | |
9306ca4a JB |
3452 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) |
3453 | i.suffix = SHORT_MNEM_SUFFIX; | |
3454 | else | |
29b0f896 AM |
3455 | case BYTE_MNEM_SUFFIX: |
3456 | case QWORD_MNEM_SUFFIX: | |
3457 | i.suffix = mnem_p[-1]; | |
3458 | mnem_p[-1] = '\0'; | |
d3ce72d0 NC |
3459 | current_templates = (const templates *) hash_find (op_hash, |
3460 | mnemonic); | |
29b0f896 AM |
3461 | break; |
3462 | case SHORT_MNEM_SUFFIX: | |
3463 | case LONG_MNEM_SUFFIX: | |
3464 | if (!intel_syntax) | |
3465 | { | |
3466 | i.suffix = mnem_p[-1]; | |
3467 | mnem_p[-1] = '\0'; | |
d3ce72d0 NC |
3468 | current_templates = (const templates *) hash_find (op_hash, |
3469 | mnemonic); | |
29b0f896 AM |
3470 | } |
3471 | break; | |
252b5132 | 3472 | |
29b0f896 AM |
3473 | /* Intel Syntax. */ |
3474 | case 'd': | |
3475 | if (intel_syntax) | |
3476 | { | |
9306ca4a | 3477 | if (intel_float_operand (mnemonic) == 1) |
29b0f896 AM |
3478 | i.suffix = SHORT_MNEM_SUFFIX; |
3479 | else | |
3480 | i.suffix = LONG_MNEM_SUFFIX; | |
3481 | mnem_p[-1] = '\0'; | |
d3ce72d0 NC |
3482 | current_templates = (const templates *) hash_find (op_hash, |
3483 | mnemonic); | |
29b0f896 AM |
3484 | } |
3485 | break; | |
3486 | } | |
3487 | if (!current_templates) | |
3488 | { | |
3489 | as_bad (_("no such instruction: `%s'"), token_start); | |
3490 | return NULL; | |
3491 | } | |
3492 | } | |
252b5132 | 3493 | |
40fb9820 L |
3494 | if (current_templates->start->opcode_modifier.jump |
3495 | || current_templates->start->opcode_modifier.jumpbyte) | |
29b0f896 AM |
3496 | { |
3497 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
3498 | predict taken and predict not taken respectively. | |
3499 | I'm not sure that branch hints actually do anything on loop | |
3500 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
3501 | may work in the future and it doesn't hurt to accept them | |
3502 | now. */ | |
3503 | if (l[0] == ',' && l[1] == 'p') | |
3504 | { | |
3505 | if (l[2] == 't') | |
3506 | { | |
3507 | if (!add_prefix (DS_PREFIX_OPCODE)) | |
3508 | return NULL; | |
3509 | l += 3; | |
3510 | } | |
3511 | else if (l[2] == 'n') | |
3512 | { | |
3513 | if (!add_prefix (CS_PREFIX_OPCODE)) | |
3514 | return NULL; | |
3515 | l += 3; | |
3516 | } | |
3517 | } | |
3518 | } | |
3519 | /* Any other comma loses. */ | |
3520 | if (*l == ',') | |
3521 | { | |
3522 | as_bad (_("invalid character %s in mnemonic"), | |
3523 | output_invalid (*l)); | |
3524 | return NULL; | |
3525 | } | |
252b5132 | 3526 | |
29b0f896 | 3527 | /* Check if instruction is supported on specified architecture. */ |
5c6af06e JB |
3528 | supported = 0; |
3529 | for (t = current_templates->start; t < current_templates->end; ++t) | |
3530 | { | |
c0f3af97 L |
3531 | supported |= cpu_flags_match (t); |
3532 | if (supported == CPU_FLAGS_PERFECT_MATCH) | |
3629bb00 | 3533 | goto skip; |
5c6af06e | 3534 | } |
3629bb00 | 3535 | |
c0f3af97 | 3536 | if (!(supported & CPU_FLAGS_64BIT_MATCH)) |
5c6af06e JB |
3537 | { |
3538 | as_bad (flag_code == CODE_64BIT | |
3539 | ? _("`%s' is not supported in 64-bit mode") | |
3540 | : _("`%s' is only supported in 64-bit mode"), | |
3541 | current_templates->start->name); | |
3542 | return NULL; | |
3543 | } | |
c0f3af97 | 3544 | if (supported != CPU_FLAGS_PERFECT_MATCH) |
29b0f896 | 3545 | { |
3629bb00 | 3546 | as_bad (_("`%s' is not supported on `%s%s'"), |
7ab9ffdd | 3547 | current_templates->start->name, |
41aacd83 | 3548 | cpu_arch_name ? cpu_arch_name : default_arch, |
3629bb00 L |
3549 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); |
3550 | return NULL; | |
29b0f896 | 3551 | } |
3629bb00 L |
3552 | |
3553 | skip: | |
3554 | if (!cpu_arch_flags.bitfield.cpui386 | |
40fb9820 | 3555 | && (flag_code != CODE_16BIT)) |
29b0f896 AM |
3556 | { |
3557 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
3558 | } | |
252b5132 | 3559 | |
29c048b6 | 3560 | /* Check for rep/repne without a string (or other allowed) instruction. */ |
f41bbced | 3561 | if (expecting_string_instruction) |
29b0f896 | 3562 | { |
f41bbced JB |
3563 | static templates override; |
3564 | ||
3565 | for (t = current_templates->start; t < current_templates->end; ++t) | |
29c048b6 | 3566 | if (t->opcode_modifier.repprefixok) |
f41bbced JB |
3567 | break; |
3568 | if (t >= current_templates->end) | |
3569 | { | |
3570 | as_bad (_("expecting string instruction after `%s'"), | |
64e74474 | 3571 | expecting_string_instruction); |
f41bbced JB |
3572 | return NULL; |
3573 | } | |
3574 | for (override.start = t; t < current_templates->end; ++t) | |
29c048b6 | 3575 | if (!t->opcode_modifier.repprefixok) |
f41bbced JB |
3576 | break; |
3577 | override.end = t; | |
3578 | current_templates = &override; | |
29b0f896 | 3579 | } |
252b5132 | 3580 | |
29b0f896 AM |
3581 | return l; |
3582 | } | |
252b5132 | 3583 | |
29b0f896 | 3584 | static char * |
e3bb37b5 | 3585 | parse_operands (char *l, const char *mnemonic) |
29b0f896 AM |
3586 | { |
3587 | char *token_start; | |
3138f287 | 3588 | |
29b0f896 AM |
3589 | /* 1 if operand is pending after ','. */ |
3590 | unsigned int expecting_operand = 0; | |
252b5132 | 3591 | |
29b0f896 AM |
3592 | /* Non-zero if operand parens not balanced. */ |
3593 | unsigned int paren_not_balanced; | |
3594 | ||
3595 | while (*l != END_OF_INSN) | |
3596 | { | |
3597 | /* Skip optional white space before operand. */ | |
3598 | if (is_space_char (*l)) | |
3599 | ++l; | |
3600 | if (!is_operand_char (*l) && *l != END_OF_INSN) | |
3601 | { | |
3602 | as_bad (_("invalid character %s before operand %d"), | |
3603 | output_invalid (*l), | |
3604 | i.operands + 1); | |
3605 | return NULL; | |
3606 | } | |
3607 | token_start = l; /* after white space */ | |
3608 | paren_not_balanced = 0; | |
3609 | while (paren_not_balanced || *l != ',') | |
3610 | { | |
3611 | if (*l == END_OF_INSN) | |
3612 | { | |
3613 | if (paren_not_balanced) | |
3614 | { | |
3615 | if (!intel_syntax) | |
3616 | as_bad (_("unbalanced parenthesis in operand %d."), | |
3617 | i.operands + 1); | |
3618 | else | |
3619 | as_bad (_("unbalanced brackets in operand %d."), | |
3620 | i.operands + 1); | |
3621 | return NULL; | |
3622 | } | |
3623 | else | |
3624 | break; /* we are done */ | |
3625 | } | |
3626 | else if (!is_operand_char (*l) && !is_space_char (*l)) | |
3627 | { | |
3628 | as_bad (_("invalid character %s in operand %d"), | |
3629 | output_invalid (*l), | |
3630 | i.operands + 1); | |
3631 | return NULL; | |
3632 | } | |
3633 | if (!intel_syntax) | |
3634 | { | |
3635 | if (*l == '(') | |
3636 | ++paren_not_balanced; | |
3637 | if (*l == ')') | |
3638 | --paren_not_balanced; | |
3639 | } | |
3640 | else | |
3641 | { | |
3642 | if (*l == '[') | |
3643 | ++paren_not_balanced; | |
3644 | if (*l == ']') | |
3645 | --paren_not_balanced; | |
3646 | } | |
3647 | l++; | |
3648 | } | |
3649 | if (l != token_start) | |
3650 | { /* Yes, we've read in another operand. */ | |
3651 | unsigned int operand_ok; | |
3652 | this_operand = i.operands++; | |
7d5e4556 | 3653 | i.types[this_operand].bitfield.unspecified = 1; |
29b0f896 AM |
3654 | if (i.operands > MAX_OPERANDS) |
3655 | { | |
3656 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
3657 | MAX_OPERANDS); | |
3658 | return NULL; | |
3659 | } | |
3660 | /* Now parse operand adding info to 'i' as we go along. */ | |
3661 | END_STRING_AND_SAVE (l); | |
3662 | ||
3663 | if (intel_syntax) | |
3664 | operand_ok = | |
3665 | i386_intel_operand (token_start, | |
3666 | intel_float_operand (mnemonic)); | |
3667 | else | |
a7619375 | 3668 | operand_ok = i386_att_operand (token_start); |
29b0f896 AM |
3669 | |
3670 | RESTORE_END_STRING (l); | |
3671 | if (!operand_ok) | |
3672 | return NULL; | |
3673 | } | |
3674 | else | |
3675 | { | |
3676 | if (expecting_operand) | |
3677 | { | |
3678 | expecting_operand_after_comma: | |
3679 | as_bad (_("expecting operand after ','; got nothing")); | |
3680 | return NULL; | |
3681 | } | |
3682 | if (*l == ',') | |
3683 | { | |
3684 | as_bad (_("expecting operand before ','; got nothing")); | |
3685 | return NULL; | |
3686 | } | |
3687 | } | |
7f3f1ea2 | 3688 | |
29b0f896 AM |
3689 | /* Now *l must be either ',' or END_OF_INSN. */ |
3690 | if (*l == ',') | |
3691 | { | |
3692 | if (*++l == END_OF_INSN) | |
3693 | { | |
3694 | /* Just skip it, if it's \n complain. */ | |
3695 | goto expecting_operand_after_comma; | |
3696 | } | |
3697 | expecting_operand = 1; | |
3698 | } | |
3699 | } | |
3700 | return l; | |
3701 | } | |
7f3f1ea2 | 3702 | |
050dfa73 | 3703 | static void |
4d456e3d | 3704 | swap_2_operands (int xchg1, int xchg2) |
050dfa73 MM |
3705 | { |
3706 | union i386_op temp_op; | |
40fb9820 | 3707 | i386_operand_type temp_type; |
050dfa73 | 3708 | enum bfd_reloc_code_real temp_reloc; |
4eed87de | 3709 | |
050dfa73 MM |
3710 | temp_type = i.types[xchg2]; |
3711 | i.types[xchg2] = i.types[xchg1]; | |
3712 | i.types[xchg1] = temp_type; | |
3713 | temp_op = i.op[xchg2]; | |
3714 | i.op[xchg2] = i.op[xchg1]; | |
3715 | i.op[xchg1] = temp_op; | |
3716 | temp_reloc = i.reloc[xchg2]; | |
3717 | i.reloc[xchg2] = i.reloc[xchg1]; | |
3718 | i.reloc[xchg1] = temp_reloc; | |
3719 | } | |
3720 | ||
29b0f896 | 3721 | static void |
e3bb37b5 | 3722 | swap_operands (void) |
29b0f896 | 3723 | { |
b7c61d9a | 3724 | switch (i.operands) |
050dfa73 | 3725 | { |
c0f3af97 | 3726 | case 5: |
b7c61d9a | 3727 | case 4: |
4d456e3d | 3728 | swap_2_operands (1, i.operands - 2); |
b7c61d9a L |
3729 | case 3: |
3730 | case 2: | |
4d456e3d | 3731 | swap_2_operands (0, i.operands - 1); |
b7c61d9a L |
3732 | break; |
3733 | default: | |
3734 | abort (); | |
29b0f896 | 3735 | } |
29b0f896 AM |
3736 | |
3737 | if (i.mem_operands == 2) | |
3738 | { | |
3739 | const seg_entry *temp_seg; | |
3740 | temp_seg = i.seg[0]; | |
3741 | i.seg[0] = i.seg[1]; | |
3742 | i.seg[1] = temp_seg; | |
3743 | } | |
3744 | } | |
252b5132 | 3745 | |
29b0f896 AM |
3746 | /* Try to ensure constant immediates are represented in the smallest |
3747 | opcode possible. */ | |
3748 | static void | |
e3bb37b5 | 3749 | optimize_imm (void) |
29b0f896 AM |
3750 | { |
3751 | char guess_suffix = 0; | |
3752 | int op; | |
252b5132 | 3753 | |
29b0f896 AM |
3754 | if (i.suffix) |
3755 | guess_suffix = i.suffix; | |
3756 | else if (i.reg_operands) | |
3757 | { | |
3758 | /* Figure out a suffix from the last register operand specified. | |
3759 | We can't do this properly yet, ie. excluding InOutPortReg, | |
3760 | but the following works for instructions with immediates. | |
3761 | In any case, we can't set i.suffix yet. */ | |
3762 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 3763 | if (i.types[op].bitfield.reg8) |
7ab9ffdd | 3764 | { |
40fb9820 L |
3765 | guess_suffix = BYTE_MNEM_SUFFIX; |
3766 | break; | |
3767 | } | |
3768 | else if (i.types[op].bitfield.reg16) | |
252b5132 | 3769 | { |
40fb9820 L |
3770 | guess_suffix = WORD_MNEM_SUFFIX; |
3771 | break; | |
3772 | } | |
3773 | else if (i.types[op].bitfield.reg32) | |
3774 | { | |
3775 | guess_suffix = LONG_MNEM_SUFFIX; | |
3776 | break; | |
3777 | } | |
3778 | else if (i.types[op].bitfield.reg64) | |
3779 | { | |
3780 | guess_suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 | 3781 | break; |
252b5132 | 3782 | } |
29b0f896 AM |
3783 | } |
3784 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) | |
3785 | guess_suffix = WORD_MNEM_SUFFIX; | |
3786 | ||
3787 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 3788 | if (operand_type_check (i.types[op], imm)) |
29b0f896 AM |
3789 | { |
3790 | switch (i.op[op].imms->X_op) | |
252b5132 | 3791 | { |
29b0f896 AM |
3792 | case O_constant: |
3793 | /* If a suffix is given, this operand may be shortened. */ | |
3794 | switch (guess_suffix) | |
252b5132 | 3795 | { |
29b0f896 | 3796 | case LONG_MNEM_SUFFIX: |
40fb9820 L |
3797 | i.types[op].bitfield.imm32 = 1; |
3798 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
3799 | break; |
3800 | case WORD_MNEM_SUFFIX: | |
40fb9820 L |
3801 | i.types[op].bitfield.imm16 = 1; |
3802 | i.types[op].bitfield.imm32 = 1; | |
3803 | i.types[op].bitfield.imm32s = 1; | |
3804 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
3805 | break; |
3806 | case BYTE_MNEM_SUFFIX: | |
40fb9820 L |
3807 | i.types[op].bitfield.imm8 = 1; |
3808 | i.types[op].bitfield.imm8s = 1; | |
3809 | i.types[op].bitfield.imm16 = 1; | |
3810 | i.types[op].bitfield.imm32 = 1; | |
3811 | i.types[op].bitfield.imm32s = 1; | |
3812 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 | 3813 | break; |
252b5132 | 3814 | } |
252b5132 | 3815 | |
29b0f896 AM |
3816 | /* If this operand is at most 16 bits, convert it |
3817 | to a signed 16 bit number before trying to see | |
3818 | whether it will fit in an even smaller size. | |
3819 | This allows a 16-bit operand such as $0xffe0 to | |
3820 | be recognised as within Imm8S range. */ | |
40fb9820 | 3821 | if ((i.types[op].bitfield.imm16) |
29b0f896 | 3822 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) |
252b5132 | 3823 | { |
29b0f896 AM |
3824 | i.op[op].imms->X_add_number = |
3825 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
3826 | } | |
40fb9820 | 3827 | if ((i.types[op].bitfield.imm32) |
29b0f896 AM |
3828 | && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) |
3829 | == 0)) | |
3830 | { | |
3831 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number | |
3832 | ^ ((offsetT) 1 << 31)) | |
3833 | - ((offsetT) 1 << 31)); | |
3834 | } | |
40fb9820 | 3835 | i.types[op] |
c6fb90c8 L |
3836 | = operand_type_or (i.types[op], |
3837 | smallest_imm_type (i.op[op].imms->X_add_number)); | |
252b5132 | 3838 | |
29b0f896 AM |
3839 | /* We must avoid matching of Imm32 templates when 64bit |
3840 | only immediate is available. */ | |
3841 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
40fb9820 | 3842 | i.types[op].bitfield.imm32 = 0; |
29b0f896 | 3843 | break; |
252b5132 | 3844 | |
29b0f896 AM |
3845 | case O_absent: |
3846 | case O_register: | |
3847 | abort (); | |
3848 | ||
3849 | /* Symbols and expressions. */ | |
3850 | default: | |
9cd96992 JB |
3851 | /* Convert symbolic operand to proper sizes for matching, but don't |
3852 | prevent matching a set of insns that only supports sizes other | |
3853 | than those matching the insn suffix. */ | |
3854 | { | |
40fb9820 | 3855 | i386_operand_type mask, allowed; |
d3ce72d0 | 3856 | const insn_template *t; |
9cd96992 | 3857 | |
0dfbf9d7 L |
3858 | operand_type_set (&mask, 0); |
3859 | operand_type_set (&allowed, 0); | |
40fb9820 | 3860 | |
4eed87de AM |
3861 | for (t = current_templates->start; |
3862 | t < current_templates->end; | |
3863 | ++t) | |
c6fb90c8 L |
3864 | allowed = operand_type_or (allowed, |
3865 | t->operand_types[op]); | |
9cd96992 JB |
3866 | switch (guess_suffix) |
3867 | { | |
3868 | case QWORD_MNEM_SUFFIX: | |
40fb9820 L |
3869 | mask.bitfield.imm64 = 1; |
3870 | mask.bitfield.imm32s = 1; | |
9cd96992 JB |
3871 | break; |
3872 | case LONG_MNEM_SUFFIX: | |
40fb9820 | 3873 | mask.bitfield.imm32 = 1; |
9cd96992 JB |
3874 | break; |
3875 | case WORD_MNEM_SUFFIX: | |
40fb9820 | 3876 | mask.bitfield.imm16 = 1; |
9cd96992 JB |
3877 | break; |
3878 | case BYTE_MNEM_SUFFIX: | |
40fb9820 | 3879 | mask.bitfield.imm8 = 1; |
9cd96992 JB |
3880 | break; |
3881 | default: | |
9cd96992 JB |
3882 | break; |
3883 | } | |
c6fb90c8 | 3884 | allowed = operand_type_and (mask, allowed); |
0dfbf9d7 | 3885 | if (!operand_type_all_zero (&allowed)) |
c6fb90c8 | 3886 | i.types[op] = operand_type_and (i.types[op], mask); |
9cd96992 | 3887 | } |
29b0f896 | 3888 | break; |
252b5132 | 3889 | } |
29b0f896 AM |
3890 | } |
3891 | } | |
47926f60 | 3892 | |
29b0f896 AM |
3893 | /* Try to use the smallest displacement type too. */ |
3894 | static void | |
e3bb37b5 | 3895 | optimize_disp (void) |
29b0f896 AM |
3896 | { |
3897 | int op; | |
3e73aa7c | 3898 | |
29b0f896 | 3899 | for (op = i.operands; --op >= 0;) |
40fb9820 | 3900 | if (operand_type_check (i.types[op], disp)) |
252b5132 | 3901 | { |
b300c311 | 3902 | if (i.op[op].disps->X_op == O_constant) |
252b5132 | 3903 | { |
91d6fa6a | 3904 | offsetT op_disp = i.op[op].disps->X_add_number; |
29b0f896 | 3905 | |
40fb9820 | 3906 | if (i.types[op].bitfield.disp16 |
91d6fa6a | 3907 | && (op_disp & ~(offsetT) 0xffff) == 0) |
b300c311 L |
3908 | { |
3909 | /* If this operand is at most 16 bits, convert | |
3910 | to a signed 16 bit number and don't use 64bit | |
3911 | displacement. */ | |
91d6fa6a | 3912 | op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000); |
40fb9820 | 3913 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 3914 | } |
40fb9820 | 3915 | if (i.types[op].bitfield.disp32 |
91d6fa6a | 3916 | && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0) |
b300c311 L |
3917 | { |
3918 | /* If this operand is at most 32 bits, convert | |
3919 | to a signed 32 bit number and don't use 64bit | |
3920 | displacement. */ | |
91d6fa6a NC |
3921 | op_disp &= (((offsetT) 2 << 31) - 1); |
3922 | op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
40fb9820 | 3923 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 3924 | } |
91d6fa6a | 3925 | if (!op_disp && i.types[op].bitfield.baseindex) |
b300c311 | 3926 | { |
40fb9820 L |
3927 | i.types[op].bitfield.disp8 = 0; |
3928 | i.types[op].bitfield.disp16 = 0; | |
3929 | i.types[op].bitfield.disp32 = 0; | |
3930 | i.types[op].bitfield.disp32s = 0; | |
3931 | i.types[op].bitfield.disp64 = 0; | |
b300c311 L |
3932 | i.op[op].disps = 0; |
3933 | i.disp_operands--; | |
3934 | } | |
3935 | else if (flag_code == CODE_64BIT) | |
3936 | { | |
91d6fa6a | 3937 | if (fits_in_signed_long (op_disp)) |
28a9d8f5 | 3938 | { |
40fb9820 L |
3939 | i.types[op].bitfield.disp64 = 0; |
3940 | i.types[op].bitfield.disp32s = 1; | |
28a9d8f5 | 3941 | } |
0e1147d9 | 3942 | if (i.prefix[ADDR_PREFIX] |
91d6fa6a | 3943 | && fits_in_unsigned_long (op_disp)) |
40fb9820 | 3944 | i.types[op].bitfield.disp32 = 1; |
b300c311 | 3945 | } |
40fb9820 L |
3946 | if ((i.types[op].bitfield.disp32 |
3947 | || i.types[op].bitfield.disp32s | |
3948 | || i.types[op].bitfield.disp16) | |
91d6fa6a | 3949 | && fits_in_signed_byte (op_disp)) |
40fb9820 | 3950 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 3951 | } |
67a4f2b7 AO |
3952 | else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
3953 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) | |
3954 | { | |
3955 | fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, | |
3956 | i.op[op].disps, 0, i.reloc[op]); | |
40fb9820 L |
3957 | i.types[op].bitfield.disp8 = 0; |
3958 | i.types[op].bitfield.disp16 = 0; | |
3959 | i.types[op].bitfield.disp32 = 0; | |
3960 | i.types[op].bitfield.disp32s = 0; | |
3961 | i.types[op].bitfield.disp64 = 0; | |
67a4f2b7 AO |
3962 | } |
3963 | else | |
b300c311 | 3964 | /* We only support 64bit displacement on constants. */ |
40fb9820 | 3965 | i.types[op].bitfield.disp64 = 0; |
252b5132 | 3966 | } |
29b0f896 AM |
3967 | } |
3968 | ||
6c30d220 L |
3969 | /* Check if operands are valid for the instruction. */ |
3970 | ||
3971 | static int | |
3972 | check_VecOperands (const insn_template *t) | |
3973 | { | |
3974 | /* Without VSIB byte, we can't have a vector register for index. */ | |
3975 | if (!t->opcode_modifier.vecsib | |
3976 | && i.index_reg | |
3977 | && (i.index_reg->reg_type.bitfield.regxmm | |
3978 | || i.index_reg->reg_type.bitfield.regymm)) | |
3979 | { | |
3980 | i.error = unsupported_vector_index_register; | |
3981 | return 1; | |
3982 | } | |
3983 | ||
7bab8ab5 JB |
3984 | /* For VSIB byte, we need a vector register for index, and all vector |
3985 | registers must be distinct. */ | |
3986 | if (t->opcode_modifier.vecsib) | |
3987 | { | |
3988 | if (!i.index_reg | |
6c30d220 L |
3989 | || !((t->opcode_modifier.vecsib == VecSIB128 |
3990 | && i.index_reg->reg_type.bitfield.regxmm) | |
3991 | || (t->opcode_modifier.vecsib == VecSIB256 | |
7bab8ab5 JB |
3992 | && i.index_reg->reg_type.bitfield.regymm))) |
3993 | { | |
3994 | i.error = invalid_vsib_address; | |
3995 | return 1; | |
3996 | } | |
3997 | ||
3998 | gas_assert (i.reg_operands == 2); | |
3999 | gas_assert (i.types[0].bitfield.regxmm | |
4000 | || i.types[0].bitfield.regymm); | |
4001 | gas_assert (i.types[2].bitfield.regxmm | |
4002 | || i.types[2].bitfield.regymm); | |
4003 | ||
4004 | if (operand_check == check_none) | |
4005 | return 0; | |
4006 | if (register_number (i.op[0].regs) != register_number (i.index_reg) | |
4007 | && register_number (i.op[2].regs) != register_number (i.index_reg) | |
4008 | && register_number (i.op[0].regs) != register_number (i.op[2].regs)) | |
4009 | return 0; | |
4010 | if (operand_check == check_error) | |
4011 | { | |
4012 | i.error = invalid_vector_register_set; | |
4013 | return 1; | |
4014 | } | |
4015 | as_warn (_("mask, index, and destination registers should be distinct")); | |
6c30d220 L |
4016 | } |
4017 | ||
4018 | return 0; | |
4019 | } | |
4020 | ||
43f3e2ee | 4021 | /* Check if operands are valid for the instruction. Update VEX |
a683cc34 SP |
4022 | operand types. */ |
4023 | ||
4024 | static int | |
4025 | VEX_check_operands (const insn_template *t) | |
4026 | { | |
4027 | if (!t->opcode_modifier.vex) | |
4028 | return 0; | |
4029 | ||
4030 | /* Only check VEX_Imm4, which must be the first operand. */ | |
4031 | if (t->operand_types[0].bitfield.vec_imm4) | |
4032 | { | |
4033 | if (i.op[0].imms->X_op != O_constant | |
4034 | || !fits_in_imm4 (i.op[0].imms->X_add_number)) | |
891edac4 | 4035 | { |
a65babc9 | 4036 | i.error = bad_imm4; |
891edac4 L |
4037 | return 1; |
4038 | } | |
a683cc34 SP |
4039 | |
4040 | /* Turn off Imm8 so that update_imm won't complain. */ | |
4041 | i.types[0] = vec_imm4; | |
4042 | } | |
4043 | ||
4044 | return 0; | |
4045 | } | |
4046 | ||
d3ce72d0 | 4047 | static const insn_template * |
e3bb37b5 | 4048 | match_template (void) |
29b0f896 AM |
4049 | { |
4050 | /* Points to template once we've found it. */ | |
d3ce72d0 | 4051 | const insn_template *t; |
40fb9820 | 4052 | i386_operand_type overlap0, overlap1, overlap2, overlap3; |
c0f3af97 | 4053 | i386_operand_type overlap4; |
29b0f896 | 4054 | unsigned int found_reverse_match; |
40fb9820 L |
4055 | i386_opcode_modifier suffix_check; |
4056 | i386_operand_type operand_types [MAX_OPERANDS]; | |
539e75ad | 4057 | int addr_prefix_disp; |
a5c311ca | 4058 | unsigned int j; |
3629bb00 | 4059 | unsigned int found_cpu_match; |
45664ddb | 4060 | unsigned int check_register; |
5614d22c | 4061 | enum i386_error specific_error = 0; |
29b0f896 | 4062 | |
c0f3af97 L |
4063 | #if MAX_OPERANDS != 5 |
4064 | # error "MAX_OPERANDS must be 5." | |
f48ff2ae L |
4065 | #endif |
4066 | ||
29b0f896 | 4067 | found_reverse_match = 0; |
539e75ad | 4068 | addr_prefix_disp = -1; |
40fb9820 L |
4069 | |
4070 | memset (&suffix_check, 0, sizeof (suffix_check)); | |
4071 | if (i.suffix == BYTE_MNEM_SUFFIX) | |
4072 | suffix_check.no_bsuf = 1; | |
4073 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
4074 | suffix_check.no_wsuf = 1; | |
4075 | else if (i.suffix == SHORT_MNEM_SUFFIX) | |
4076 | suffix_check.no_ssuf = 1; | |
4077 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
4078 | suffix_check.no_lsuf = 1; | |
4079 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
4080 | suffix_check.no_qsuf = 1; | |
4081 | else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX) | |
7ce189b3 | 4082 | suffix_check.no_ldsuf = 1; |
29b0f896 | 4083 | |
01559ecc L |
4084 | /* Must have right number of operands. */ |
4085 | i.error = number_of_operands_mismatch; | |
4086 | ||
45aa61fe | 4087 | for (t = current_templates->start; t < current_templates->end; t++) |
29b0f896 | 4088 | { |
539e75ad L |
4089 | addr_prefix_disp = -1; |
4090 | ||
29b0f896 AM |
4091 | if (i.operands != t->operands) |
4092 | continue; | |
4093 | ||
50aecf8c | 4094 | /* Check processor support. */ |
a65babc9 | 4095 | i.error = unsupported; |
c0f3af97 L |
4096 | found_cpu_match = (cpu_flags_match (t) |
4097 | == CPU_FLAGS_PERFECT_MATCH); | |
50aecf8c L |
4098 | if (!found_cpu_match) |
4099 | continue; | |
4100 | ||
e1d4d893 | 4101 | /* Check old gcc support. */ |
a65babc9 | 4102 | i.error = old_gcc_only; |
e1d4d893 L |
4103 | if (!old_gcc && t->opcode_modifier.oldgcc) |
4104 | continue; | |
4105 | ||
4106 | /* Check AT&T mnemonic. */ | |
a65babc9 | 4107 | i.error = unsupported_with_intel_mnemonic; |
e1d4d893 | 4108 | if (intel_mnemonic && t->opcode_modifier.attmnemonic) |
1efbbeb4 L |
4109 | continue; |
4110 | ||
891edac4 | 4111 | /* Check AT&T/Intel syntax. */ |
a65babc9 | 4112 | i.error = unsupported_syntax; |
5c07affc L |
4113 | if ((intel_syntax && t->opcode_modifier.attsyntax) |
4114 | || (!intel_syntax && t->opcode_modifier.intelsyntax)) | |
1efbbeb4 L |
4115 | continue; |
4116 | ||
20592a94 | 4117 | /* Check the suffix, except for some instructions in intel mode. */ |
a65babc9 | 4118 | i.error = invalid_instruction_suffix; |
567e4e96 L |
4119 | if ((!intel_syntax || !t->opcode_modifier.ignoresize) |
4120 | && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf) | |
4121 | || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf) | |
4122 | || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf) | |
4123 | || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf) | |
4124 | || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf) | |
4125 | || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf))) | |
29b0f896 AM |
4126 | continue; |
4127 | ||
5c07affc | 4128 | if (!operand_size_match (t)) |
7d5e4556 | 4129 | continue; |
539e75ad | 4130 | |
5c07affc L |
4131 | for (j = 0; j < MAX_OPERANDS; j++) |
4132 | operand_types[j] = t->operand_types[j]; | |
4133 | ||
45aa61fe AM |
4134 | /* In general, don't allow 64-bit operands in 32-bit mode. */ |
4135 | if (i.suffix == QWORD_MNEM_SUFFIX | |
4136 | && flag_code != CODE_64BIT | |
4137 | && (intel_syntax | |
40fb9820 | 4138 | ? (!t->opcode_modifier.ignoresize |
45aa61fe AM |
4139 | && !intel_float_operand (t->name)) |
4140 | : intel_float_operand (t->name) != 2) | |
40fb9820 | 4141 | && ((!operand_types[0].bitfield.regmmx |
c0f3af97 L |
4142 | && !operand_types[0].bitfield.regxmm |
4143 | && !operand_types[0].bitfield.regymm) | |
40fb9820 | 4144 | || (!operand_types[t->operands > 1].bitfield.regmmx |
c0f3af97 L |
4145 | && !!operand_types[t->operands > 1].bitfield.regxmm |
4146 | && !!operand_types[t->operands > 1].bitfield.regymm)) | |
45aa61fe AM |
4147 | && (t->base_opcode != 0x0fc7 |
4148 | || t->extension_opcode != 1 /* cmpxchg8b */)) | |
4149 | continue; | |
4150 | ||
192dc9c6 JB |
4151 | /* In general, don't allow 32-bit operands on pre-386. */ |
4152 | else if (i.suffix == LONG_MNEM_SUFFIX | |
4153 | && !cpu_arch_flags.bitfield.cpui386 | |
4154 | && (intel_syntax | |
4155 | ? (!t->opcode_modifier.ignoresize | |
4156 | && !intel_float_operand (t->name)) | |
4157 | : intel_float_operand (t->name) != 2) | |
4158 | && ((!operand_types[0].bitfield.regmmx | |
4159 | && !operand_types[0].bitfield.regxmm) | |
4160 | || (!operand_types[t->operands > 1].bitfield.regmmx | |
4161 | && !!operand_types[t->operands > 1].bitfield.regxmm))) | |
4162 | continue; | |
4163 | ||
29b0f896 | 4164 | /* Do not verify operands when there are none. */ |
50aecf8c | 4165 | else |
29b0f896 | 4166 | { |
c6fb90c8 | 4167 | if (!t->operands) |
2dbab7d5 L |
4168 | /* We've found a match; break out of loop. */ |
4169 | break; | |
29b0f896 | 4170 | } |
252b5132 | 4171 | |
539e75ad L |
4172 | /* Address size prefix will turn Disp64/Disp32/Disp16 operand |
4173 | into Disp32/Disp16/Disp32 operand. */ | |
4174 | if (i.prefix[ADDR_PREFIX] != 0) | |
4175 | { | |
40fb9820 | 4176 | /* There should be only one Disp operand. */ |
539e75ad L |
4177 | switch (flag_code) |
4178 | { | |
4179 | case CODE_16BIT: | |
40fb9820 L |
4180 | for (j = 0; j < MAX_OPERANDS; j++) |
4181 | { | |
4182 | if (operand_types[j].bitfield.disp16) | |
4183 | { | |
4184 | addr_prefix_disp = j; | |
4185 | operand_types[j].bitfield.disp32 = 1; | |
4186 | operand_types[j].bitfield.disp16 = 0; | |
4187 | break; | |
4188 | } | |
4189 | } | |
539e75ad L |
4190 | break; |
4191 | case CODE_32BIT: | |
40fb9820 L |
4192 | for (j = 0; j < MAX_OPERANDS; j++) |
4193 | { | |
4194 | if (operand_types[j].bitfield.disp32) | |
4195 | { | |
4196 | addr_prefix_disp = j; | |
4197 | operand_types[j].bitfield.disp32 = 0; | |
4198 | operand_types[j].bitfield.disp16 = 1; | |
4199 | break; | |
4200 | } | |
4201 | } | |
539e75ad L |
4202 | break; |
4203 | case CODE_64BIT: | |
40fb9820 L |
4204 | for (j = 0; j < MAX_OPERANDS; j++) |
4205 | { | |
4206 | if (operand_types[j].bitfield.disp64) | |
4207 | { | |
4208 | addr_prefix_disp = j; | |
4209 | operand_types[j].bitfield.disp64 = 0; | |
4210 | operand_types[j].bitfield.disp32 = 1; | |
4211 | break; | |
4212 | } | |
4213 | } | |
539e75ad L |
4214 | break; |
4215 | } | |
539e75ad L |
4216 | } |
4217 | ||
56ffb741 L |
4218 | /* We check register size if needed. */ |
4219 | check_register = t->opcode_modifier.checkregsize; | |
c6fb90c8 | 4220 | overlap0 = operand_type_and (i.types[0], operand_types[0]); |
29b0f896 AM |
4221 | switch (t->operands) |
4222 | { | |
4223 | case 1: | |
40fb9820 | 4224 | if (!operand_type_match (overlap0, i.types[0])) |
29b0f896 AM |
4225 | continue; |
4226 | break; | |
4227 | case 2: | |
8b38ad71 L |
4228 | /* xchg %eax, %eax is a special case. It is an aliase for nop |
4229 | only in 32bit mode and we can use opcode 0x90. In 64bit | |
4230 | mode, we can't use 0x90 for xchg %eax, %eax since it should | |
4231 | zero-extend %eax to %rax. */ | |
4232 | if (flag_code == CODE_64BIT | |
4233 | && t->base_opcode == 0x90 | |
0dfbf9d7 L |
4234 | && operand_type_equal (&i.types [0], &acc32) |
4235 | && operand_type_equal (&i.types [1], &acc32)) | |
8b38ad71 | 4236 | continue; |
b6169b20 L |
4237 | if (i.swap_operand) |
4238 | { | |
4239 | /* If we swap operand in encoding, we either match | |
4240 | the next one or reverse direction of operands. */ | |
4241 | if (t->opcode_modifier.s) | |
4242 | continue; | |
4243 | else if (t->opcode_modifier.d) | |
4244 | goto check_reverse; | |
4245 | } | |
4246 | ||
29b0f896 | 4247 | case 3: |
fa99fab2 L |
4248 | /* If we swap operand in encoding, we match the next one. */ |
4249 | if (i.swap_operand && t->opcode_modifier.s) | |
4250 | continue; | |
f48ff2ae | 4251 | case 4: |
c0f3af97 | 4252 | case 5: |
c6fb90c8 | 4253 | overlap1 = operand_type_and (i.types[1], operand_types[1]); |
40fb9820 L |
4254 | if (!operand_type_match (overlap0, i.types[0]) |
4255 | || !operand_type_match (overlap1, i.types[1]) | |
45664ddb L |
4256 | || (check_register |
4257 | && !operand_type_register_match (overlap0, i.types[0], | |
40fb9820 L |
4258 | operand_types[0], |
4259 | overlap1, i.types[1], | |
4260 | operand_types[1]))) | |
29b0f896 AM |
4261 | { |
4262 | /* Check if other direction is valid ... */ | |
40fb9820 | 4263 | if (!t->opcode_modifier.d && !t->opcode_modifier.floatd) |
29b0f896 AM |
4264 | continue; |
4265 | ||
b6169b20 | 4266 | check_reverse: |
29b0f896 | 4267 | /* Try reversing direction of operands. */ |
c6fb90c8 L |
4268 | overlap0 = operand_type_and (i.types[0], operand_types[1]); |
4269 | overlap1 = operand_type_and (i.types[1], operand_types[0]); | |
40fb9820 L |
4270 | if (!operand_type_match (overlap0, i.types[0]) |
4271 | || !operand_type_match (overlap1, i.types[1]) | |
45664ddb L |
4272 | || (check_register |
4273 | && !operand_type_register_match (overlap0, | |
4274 | i.types[0], | |
4275 | operand_types[1], | |
4276 | overlap1, | |
4277 | i.types[1], | |
4278 | operand_types[0]))) | |
29b0f896 AM |
4279 | { |
4280 | /* Does not match either direction. */ | |
4281 | continue; | |
4282 | } | |
4283 | /* found_reverse_match holds which of D or FloatDR | |
4284 | we've found. */ | |
40fb9820 | 4285 | if (t->opcode_modifier.d) |
8a2ed489 | 4286 | found_reverse_match = Opcode_D; |
40fb9820 | 4287 | else if (t->opcode_modifier.floatd) |
8a2ed489 L |
4288 | found_reverse_match = Opcode_FloatD; |
4289 | else | |
4290 | found_reverse_match = 0; | |
40fb9820 | 4291 | if (t->opcode_modifier.floatr) |
8a2ed489 | 4292 | found_reverse_match |= Opcode_FloatR; |
29b0f896 | 4293 | } |
f48ff2ae | 4294 | else |
29b0f896 | 4295 | { |
f48ff2ae | 4296 | /* Found a forward 2 operand match here. */ |
d1cbb4db L |
4297 | switch (t->operands) |
4298 | { | |
c0f3af97 L |
4299 | case 5: |
4300 | overlap4 = operand_type_and (i.types[4], | |
4301 | operand_types[4]); | |
d1cbb4db | 4302 | case 4: |
c6fb90c8 L |
4303 | overlap3 = operand_type_and (i.types[3], |
4304 | operand_types[3]); | |
d1cbb4db | 4305 | case 3: |
c6fb90c8 L |
4306 | overlap2 = operand_type_and (i.types[2], |
4307 | operand_types[2]); | |
d1cbb4db L |
4308 | break; |
4309 | } | |
29b0f896 | 4310 | |
f48ff2ae L |
4311 | switch (t->operands) |
4312 | { | |
c0f3af97 L |
4313 | case 5: |
4314 | if (!operand_type_match (overlap4, i.types[4]) | |
4315 | || !operand_type_register_match (overlap3, | |
4316 | i.types[3], | |
4317 | operand_types[3], | |
4318 | overlap4, | |
4319 | i.types[4], | |
4320 | operand_types[4])) | |
4321 | continue; | |
f48ff2ae | 4322 | case 4: |
40fb9820 | 4323 | if (!operand_type_match (overlap3, i.types[3]) |
45664ddb L |
4324 | || (check_register |
4325 | && !operand_type_register_match (overlap2, | |
4326 | i.types[2], | |
4327 | operand_types[2], | |
4328 | overlap3, | |
4329 | i.types[3], | |
4330 | operand_types[3]))) | |
f48ff2ae L |
4331 | continue; |
4332 | case 3: | |
4333 | /* Here we make use of the fact that there are no | |
4334 | reverse match 3 operand instructions, and all 3 | |
4335 | operand instructions only need to be checked for | |
4336 | register consistency between operands 2 and 3. */ | |
40fb9820 | 4337 | if (!operand_type_match (overlap2, i.types[2]) |
45664ddb L |
4338 | || (check_register |
4339 | && !operand_type_register_match (overlap1, | |
4340 | i.types[1], | |
4341 | operand_types[1], | |
4342 | overlap2, | |
4343 | i.types[2], | |
4344 | operand_types[2]))) | |
f48ff2ae L |
4345 | continue; |
4346 | break; | |
4347 | } | |
29b0f896 | 4348 | } |
f48ff2ae | 4349 | /* Found either forward/reverse 2, 3 or 4 operand match here: |
29b0f896 AM |
4350 | slip through to break. */ |
4351 | } | |
3629bb00 | 4352 | if (!found_cpu_match) |
29b0f896 AM |
4353 | { |
4354 | found_reverse_match = 0; | |
4355 | continue; | |
4356 | } | |
c0f3af97 | 4357 | |
5614d22c JB |
4358 | /* Check if vector and VEX operands are valid. */ |
4359 | if (check_VecOperands (t) || VEX_check_operands (t)) | |
4360 | { | |
4361 | specific_error = i.error; | |
4362 | continue; | |
4363 | } | |
a683cc34 | 4364 | |
29b0f896 AM |
4365 | /* We've found a match; break out of loop. */ |
4366 | break; | |
4367 | } | |
4368 | ||
4369 | if (t == current_templates->end) | |
4370 | { | |
4371 | /* We found no match. */ | |
a65babc9 | 4372 | const char *err_msg; |
5614d22c | 4373 | switch (specific_error ? specific_error : i.error) |
a65babc9 L |
4374 | { |
4375 | default: | |
4376 | abort (); | |
86e026a4 | 4377 | case operand_size_mismatch: |
a65babc9 L |
4378 | err_msg = _("operand size mismatch"); |
4379 | break; | |
4380 | case operand_type_mismatch: | |
4381 | err_msg = _("operand type mismatch"); | |
4382 | break; | |
4383 | case register_type_mismatch: | |
4384 | err_msg = _("register type mismatch"); | |
4385 | break; | |
4386 | case number_of_operands_mismatch: | |
4387 | err_msg = _("number of operands mismatch"); | |
4388 | break; | |
4389 | case invalid_instruction_suffix: | |
4390 | err_msg = _("invalid instruction suffix"); | |
4391 | break; | |
4392 | case bad_imm4: | |
4a2608e3 | 4393 | err_msg = _("constant doesn't fit in 4 bits"); |
a65babc9 L |
4394 | break; |
4395 | case old_gcc_only: | |
4396 | err_msg = _("only supported with old gcc"); | |
4397 | break; | |
4398 | case unsupported_with_intel_mnemonic: | |
4399 | err_msg = _("unsupported with Intel mnemonic"); | |
4400 | break; | |
4401 | case unsupported_syntax: | |
4402 | err_msg = _("unsupported syntax"); | |
4403 | break; | |
4404 | case unsupported: | |
35262a23 | 4405 | as_bad (_("unsupported instruction `%s'"), |
10efe3f6 L |
4406 | current_templates->start->name); |
4407 | return NULL; | |
6c30d220 L |
4408 | case invalid_vsib_address: |
4409 | err_msg = _("invalid VSIB address"); | |
4410 | break; | |
7bab8ab5 JB |
4411 | case invalid_vector_register_set: |
4412 | err_msg = _("mask, index, and destination registers must be distinct"); | |
4413 | break; | |
6c30d220 L |
4414 | case unsupported_vector_index_register: |
4415 | err_msg = _("unsupported vector index register"); | |
4416 | break; | |
a65babc9 L |
4417 | } |
4418 | as_bad (_("%s for `%s'"), err_msg, | |
891edac4 | 4419 | current_templates->start->name); |
fa99fab2 | 4420 | return NULL; |
29b0f896 | 4421 | } |
252b5132 | 4422 | |
29b0f896 AM |
4423 | if (!quiet_warnings) |
4424 | { | |
4425 | if (!intel_syntax | |
40fb9820 L |
4426 | && (i.types[0].bitfield.jumpabsolute |
4427 | != operand_types[0].bitfield.jumpabsolute)) | |
29b0f896 AM |
4428 | { |
4429 | as_warn (_("indirect %s without `*'"), t->name); | |
4430 | } | |
4431 | ||
40fb9820 L |
4432 | if (t->opcode_modifier.isprefix |
4433 | && t->opcode_modifier.ignoresize) | |
29b0f896 AM |
4434 | { |
4435 | /* Warn them that a data or address size prefix doesn't | |
4436 | affect assembly of the next line of code. */ | |
4437 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
4438 | } | |
4439 | } | |
4440 | ||
4441 | /* Copy the template we found. */ | |
4442 | i.tm = *t; | |
539e75ad L |
4443 | |
4444 | if (addr_prefix_disp != -1) | |
4445 | i.tm.operand_types[addr_prefix_disp] | |
4446 | = operand_types[addr_prefix_disp]; | |
4447 | ||
29b0f896 AM |
4448 | if (found_reverse_match) |
4449 | { | |
4450 | /* If we found a reverse match we must alter the opcode | |
4451 | direction bit. found_reverse_match holds bits to change | |
4452 | (different for int & float insns). */ | |
4453 | ||
4454 | i.tm.base_opcode ^= found_reverse_match; | |
4455 | ||
539e75ad L |
4456 | i.tm.operand_types[0] = operand_types[1]; |
4457 | i.tm.operand_types[1] = operand_types[0]; | |
29b0f896 AM |
4458 | } |
4459 | ||
fa99fab2 | 4460 | return t; |
29b0f896 AM |
4461 | } |
4462 | ||
4463 | static int | |
e3bb37b5 | 4464 | check_string (void) |
29b0f896 | 4465 | { |
40fb9820 L |
4466 | int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1; |
4467 | if (i.tm.operand_types[mem_op].bitfield.esseg) | |
29b0f896 AM |
4468 | { |
4469 | if (i.seg[0] != NULL && i.seg[0] != &es) | |
4470 | { | |
a87af027 | 4471 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
29b0f896 | 4472 | i.tm.name, |
a87af027 JB |
4473 | mem_op + 1, |
4474 | register_prefix); | |
29b0f896 AM |
4475 | return 0; |
4476 | } | |
4477 | /* There's only ever one segment override allowed per instruction. | |
4478 | This instruction possibly has a legal segment override on the | |
4479 | second operand, so copy the segment to where non-string | |
4480 | instructions store it, allowing common code. */ | |
4481 | i.seg[0] = i.seg[1]; | |
4482 | } | |
40fb9820 | 4483 | else if (i.tm.operand_types[mem_op + 1].bitfield.esseg) |
29b0f896 AM |
4484 | { |
4485 | if (i.seg[1] != NULL && i.seg[1] != &es) | |
4486 | { | |
a87af027 | 4487 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
29b0f896 | 4488 | i.tm.name, |
a87af027 JB |
4489 | mem_op + 2, |
4490 | register_prefix); | |
29b0f896 AM |
4491 | return 0; |
4492 | } | |
4493 | } | |
4494 | return 1; | |
4495 | } | |
4496 | ||
4497 | static int | |
543613e9 | 4498 | process_suffix (void) |
29b0f896 AM |
4499 | { |
4500 | /* If matched instruction specifies an explicit instruction mnemonic | |
4501 | suffix, use it. */ | |
40fb9820 L |
4502 | if (i.tm.opcode_modifier.size16) |
4503 | i.suffix = WORD_MNEM_SUFFIX; | |
4504 | else if (i.tm.opcode_modifier.size32) | |
4505 | i.suffix = LONG_MNEM_SUFFIX; | |
4506 | else if (i.tm.opcode_modifier.size64) | |
4507 | i.suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 AM |
4508 | else if (i.reg_operands) |
4509 | { | |
4510 | /* If there's no instruction mnemonic suffix we try to invent one | |
4511 | based on register operands. */ | |
4512 | if (!i.suffix) | |
4513 | { | |
4514 | /* We take i.suffix from the last register operand specified, | |
4515 | Destination register type is more significant than source | |
381d071f L |
4516 | register type. crc32 in SSE4.2 prefers source register |
4517 | type. */ | |
4518 | if (i.tm.base_opcode == 0xf20f38f1) | |
4519 | { | |
40fb9820 L |
4520 | if (i.types[0].bitfield.reg16) |
4521 | i.suffix = WORD_MNEM_SUFFIX; | |
4522 | else if (i.types[0].bitfield.reg32) | |
4523 | i.suffix = LONG_MNEM_SUFFIX; | |
4524 | else if (i.types[0].bitfield.reg64) | |
4525 | i.suffix = QWORD_MNEM_SUFFIX; | |
381d071f | 4526 | } |
9344ff29 | 4527 | else if (i.tm.base_opcode == 0xf20f38f0) |
20592a94 | 4528 | { |
40fb9820 | 4529 | if (i.types[0].bitfield.reg8) |
20592a94 L |
4530 | i.suffix = BYTE_MNEM_SUFFIX; |
4531 | } | |
381d071f L |
4532 | |
4533 | if (!i.suffix) | |
4534 | { | |
4535 | int op; | |
4536 | ||
20592a94 L |
4537 | if (i.tm.base_opcode == 0xf20f38f1 |
4538 | || i.tm.base_opcode == 0xf20f38f0) | |
4539 | { | |
4540 | /* We have to know the operand size for crc32. */ | |
4541 | as_bad (_("ambiguous memory operand size for `%s`"), | |
4542 | i.tm.name); | |
4543 | return 0; | |
4544 | } | |
4545 | ||
381d071f | 4546 | for (op = i.operands; --op >= 0;) |
40fb9820 | 4547 | if (!i.tm.operand_types[op].bitfield.inoutportreg) |
381d071f | 4548 | { |
40fb9820 L |
4549 | if (i.types[op].bitfield.reg8) |
4550 | { | |
4551 | i.suffix = BYTE_MNEM_SUFFIX; | |
4552 | break; | |
4553 | } | |
4554 | else if (i.types[op].bitfield.reg16) | |
4555 | { | |
4556 | i.suffix = WORD_MNEM_SUFFIX; | |
4557 | break; | |
4558 | } | |
4559 | else if (i.types[op].bitfield.reg32) | |
4560 | { | |
4561 | i.suffix = LONG_MNEM_SUFFIX; | |
4562 | break; | |
4563 | } | |
4564 | else if (i.types[op].bitfield.reg64) | |
4565 | { | |
4566 | i.suffix = QWORD_MNEM_SUFFIX; | |
4567 | break; | |
4568 | } | |
381d071f L |
4569 | } |
4570 | } | |
29b0f896 AM |
4571 | } |
4572 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
4573 | { | |
2eb952a4 L |
4574 | if (intel_syntax |
4575 | && i.tm.opcode_modifier.ignoresize | |
4576 | && i.tm.opcode_modifier.no_bsuf) | |
4577 | i.suffix = 0; | |
4578 | else if (!check_byte_reg ()) | |
29b0f896 AM |
4579 | return 0; |
4580 | } | |
4581 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
4582 | { | |
2eb952a4 L |
4583 | if (intel_syntax |
4584 | && i.tm.opcode_modifier.ignoresize | |
4585 | && i.tm.opcode_modifier.no_lsuf) | |
4586 | i.suffix = 0; | |
4587 | else if (!check_long_reg ()) | |
29b0f896 AM |
4588 | return 0; |
4589 | } | |
4590 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
4591 | { | |
955e1e6a L |
4592 | if (intel_syntax |
4593 | && i.tm.opcode_modifier.ignoresize | |
4594 | && i.tm.opcode_modifier.no_qsuf) | |
4595 | i.suffix = 0; | |
4596 | else if (!check_qword_reg ()) | |
29b0f896 AM |
4597 | return 0; |
4598 | } | |
4599 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
4600 | { | |
2eb952a4 L |
4601 | if (intel_syntax |
4602 | && i.tm.opcode_modifier.ignoresize | |
4603 | && i.tm.opcode_modifier.no_wsuf) | |
4604 | i.suffix = 0; | |
4605 | else if (!check_word_reg ()) | |
29b0f896 AM |
4606 | return 0; |
4607 | } | |
c0f3af97 L |
4608 | else if (i.suffix == XMMWORD_MNEM_SUFFIX |
4609 | || i.suffix == YMMWORD_MNEM_SUFFIX) | |
582d5edd | 4610 | { |
c0f3af97 | 4611 | /* Skip if the instruction has x/y suffix. match_template |
582d5edd L |
4612 | should check if it is a valid suffix. */ |
4613 | } | |
40fb9820 | 4614 | else if (intel_syntax && i.tm.opcode_modifier.ignoresize) |
29b0f896 AM |
4615 | /* Do nothing if the instruction is going to ignore the prefix. */ |
4616 | ; | |
4617 | else | |
4618 | abort (); | |
4619 | } | |
40fb9820 | 4620 | else if (i.tm.opcode_modifier.defaultsize |
9306ca4a JB |
4621 | && !i.suffix |
4622 | /* exclude fldenv/frstor/fsave/fstenv */ | |
40fb9820 | 4623 | && i.tm.opcode_modifier.no_ssuf) |
29b0f896 AM |
4624 | { |
4625 | i.suffix = stackop_size; | |
4626 | } | |
9306ca4a JB |
4627 | else if (intel_syntax |
4628 | && !i.suffix | |
40fb9820 L |
4629 | && (i.tm.operand_types[0].bitfield.jumpabsolute |
4630 | || i.tm.opcode_modifier.jumpbyte | |
4631 | || i.tm.opcode_modifier.jumpintersegment | |
64e74474 AM |
4632 | || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */ |
4633 | && i.tm.extension_opcode <= 3))) | |
9306ca4a JB |
4634 | { |
4635 | switch (flag_code) | |
4636 | { | |
4637 | case CODE_64BIT: | |
40fb9820 | 4638 | if (!i.tm.opcode_modifier.no_qsuf) |
9306ca4a JB |
4639 | { |
4640 | i.suffix = QWORD_MNEM_SUFFIX; | |
4641 | break; | |
4642 | } | |
4643 | case CODE_32BIT: | |
40fb9820 | 4644 | if (!i.tm.opcode_modifier.no_lsuf) |
9306ca4a JB |
4645 | i.suffix = LONG_MNEM_SUFFIX; |
4646 | break; | |
4647 | case CODE_16BIT: | |
40fb9820 | 4648 | if (!i.tm.opcode_modifier.no_wsuf) |
9306ca4a JB |
4649 | i.suffix = WORD_MNEM_SUFFIX; |
4650 | break; | |
4651 | } | |
4652 | } | |
252b5132 | 4653 | |
9306ca4a | 4654 | if (!i.suffix) |
29b0f896 | 4655 | { |
9306ca4a JB |
4656 | if (!intel_syntax) |
4657 | { | |
40fb9820 | 4658 | if (i.tm.opcode_modifier.w) |
9306ca4a | 4659 | { |
4eed87de AM |
4660 | as_bad (_("no instruction mnemonic suffix given and " |
4661 | "no register operands; can't size instruction")); | |
9306ca4a JB |
4662 | return 0; |
4663 | } | |
4664 | } | |
4665 | else | |
4666 | { | |
40fb9820 | 4667 | unsigned int suffixes; |
7ab9ffdd | 4668 | |
40fb9820 L |
4669 | suffixes = !i.tm.opcode_modifier.no_bsuf; |
4670 | if (!i.tm.opcode_modifier.no_wsuf) | |
4671 | suffixes |= 1 << 1; | |
4672 | if (!i.tm.opcode_modifier.no_lsuf) | |
4673 | suffixes |= 1 << 2; | |
fc4adea1 | 4674 | if (!i.tm.opcode_modifier.no_ldsuf) |
40fb9820 L |
4675 | suffixes |= 1 << 3; |
4676 | if (!i.tm.opcode_modifier.no_ssuf) | |
4677 | suffixes |= 1 << 4; | |
4678 | if (!i.tm.opcode_modifier.no_qsuf) | |
4679 | suffixes |= 1 << 5; | |
4680 | ||
4681 | /* There are more than suffix matches. */ | |
4682 | if (i.tm.opcode_modifier.w | |
9306ca4a | 4683 | || ((suffixes & (suffixes - 1)) |
40fb9820 L |
4684 | && !i.tm.opcode_modifier.defaultsize |
4685 | && !i.tm.opcode_modifier.ignoresize)) | |
9306ca4a JB |
4686 | { |
4687 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); | |
4688 | return 0; | |
4689 | } | |
4690 | } | |
29b0f896 | 4691 | } |
252b5132 | 4692 | |
9306ca4a JB |
4693 | /* Change the opcode based on the operand size given by i.suffix; |
4694 | We don't need to change things for byte insns. */ | |
4695 | ||
582d5edd L |
4696 | if (i.suffix |
4697 | && i.suffix != BYTE_MNEM_SUFFIX | |
c0f3af97 L |
4698 | && i.suffix != XMMWORD_MNEM_SUFFIX |
4699 | && i.suffix != YMMWORD_MNEM_SUFFIX) | |
29b0f896 AM |
4700 | { |
4701 | /* It's not a byte, select word/dword operation. */ | |
40fb9820 | 4702 | if (i.tm.opcode_modifier.w) |
29b0f896 | 4703 | { |
40fb9820 | 4704 | if (i.tm.opcode_modifier.shortform) |
29b0f896 AM |
4705 | i.tm.base_opcode |= 8; |
4706 | else | |
4707 | i.tm.base_opcode |= 1; | |
4708 | } | |
0f3f3d8b | 4709 | |
29b0f896 AM |
4710 | /* Now select between word & dword operations via the operand |
4711 | size prefix, except for instructions that will ignore this | |
4712 | prefix anyway. */ | |
ca61edf2 | 4713 | if (i.tm.opcode_modifier.addrprefixop0) |
cb712a9e | 4714 | { |
ca61edf2 L |
4715 | /* The address size override prefix changes the size of the |
4716 | first operand. */ | |
40fb9820 L |
4717 | if ((flag_code == CODE_32BIT |
4718 | && i.op->regs[0].reg_type.bitfield.reg16) | |
4719 | || (flag_code != CODE_32BIT | |
4720 | && i.op->regs[0].reg_type.bitfield.reg32)) | |
cb712a9e L |
4721 | if (!add_prefix (ADDR_PREFIX_OPCODE)) |
4722 | return 0; | |
4723 | } | |
4724 | else if (i.suffix != QWORD_MNEM_SUFFIX | |
4725 | && i.suffix != LONG_DOUBLE_MNEM_SUFFIX | |
40fb9820 L |
4726 | && !i.tm.opcode_modifier.ignoresize |
4727 | && !i.tm.opcode_modifier.floatmf | |
cb712a9e L |
4728 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) |
4729 | || (flag_code == CODE_64BIT | |
40fb9820 | 4730 | && i.tm.opcode_modifier.jumpbyte))) |
24eab124 AM |
4731 | { |
4732 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
543613e9 | 4733 | |
40fb9820 | 4734 | if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */ |
29b0f896 | 4735 | prefix = ADDR_PREFIX_OPCODE; |
252b5132 | 4736 | |
29b0f896 AM |
4737 | if (!add_prefix (prefix)) |
4738 | return 0; | |
24eab124 | 4739 | } |
252b5132 | 4740 | |
29b0f896 AM |
4741 | /* Set mode64 for an operand. */ |
4742 | if (i.suffix == QWORD_MNEM_SUFFIX | |
9146926a | 4743 | && flag_code == CODE_64BIT |
40fb9820 | 4744 | && !i.tm.opcode_modifier.norex64) |
46e883c5 L |
4745 | { |
4746 | /* Special case for xchg %rax,%rax. It is NOP and doesn't | |
d9a5e5e5 L |
4747 | need rex64. cmpxchg8b is also a special case. */ |
4748 | if (! (i.operands == 2 | |
4749 | && i.tm.base_opcode == 0x90 | |
4750 | && i.tm.extension_opcode == None | |
0dfbf9d7 L |
4751 | && operand_type_equal (&i.types [0], &acc64) |
4752 | && operand_type_equal (&i.types [1], &acc64)) | |
d9a5e5e5 L |
4753 | && ! (i.operands == 1 |
4754 | && i.tm.base_opcode == 0xfc7 | |
4755 | && i.tm.extension_opcode == 1 | |
40fb9820 L |
4756 | && !operand_type_check (i.types [0], reg) |
4757 | && operand_type_check (i.types [0], anymem))) | |
f6bee062 | 4758 | i.rex |= REX_W; |
46e883c5 | 4759 | } |
3e73aa7c | 4760 | |
29b0f896 AM |
4761 | /* Size floating point instruction. */ |
4762 | if (i.suffix == LONG_MNEM_SUFFIX) | |
40fb9820 | 4763 | if (i.tm.opcode_modifier.floatmf) |
543613e9 | 4764 | i.tm.base_opcode ^= 4; |
29b0f896 | 4765 | } |
7ecd2f8b | 4766 | |
29b0f896 AM |
4767 | return 1; |
4768 | } | |
3e73aa7c | 4769 | |
29b0f896 | 4770 | static int |
543613e9 | 4771 | check_byte_reg (void) |
29b0f896 AM |
4772 | { |
4773 | int op; | |
543613e9 | 4774 | |
29b0f896 AM |
4775 | for (op = i.operands; --op >= 0;) |
4776 | { | |
4777 | /* If this is an eight bit register, it's OK. If it's the 16 or | |
4778 | 32 bit version of an eight bit register, we will just use the | |
4779 | low portion, and that's OK too. */ | |
40fb9820 | 4780 | if (i.types[op].bitfield.reg8) |
29b0f896 AM |
4781 | continue; |
4782 | ||
5a819eb9 JB |
4783 | /* I/O port address operands are OK too. */ |
4784 | if (i.tm.operand_types[op].bitfield.inoutportreg) | |
4785 | continue; | |
4786 | ||
9344ff29 L |
4787 | /* crc32 doesn't generate this warning. */ |
4788 | if (i.tm.base_opcode == 0xf20f38f0) | |
4789 | continue; | |
4790 | ||
40fb9820 L |
4791 | if ((i.types[op].bitfield.reg16 |
4792 | || i.types[op].bitfield.reg32 | |
4793 | || i.types[op].bitfield.reg64) | |
5a819eb9 JB |
4794 | && i.op[op].regs->reg_num < 4 |
4795 | /* Prohibit these changes in 64bit mode, since the lowering | |
4796 | would be more complicated. */ | |
4797 | && flag_code != CODE_64BIT) | |
29b0f896 | 4798 | { |
29b0f896 | 4799 | #if REGISTER_WARNINGS |
5a819eb9 | 4800 | if (!quiet_warnings) |
a540244d L |
4801 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
4802 | register_prefix, | |
40fb9820 | 4803 | (i.op[op].regs + (i.types[op].bitfield.reg16 |
29b0f896 AM |
4804 | ? REGNAM_AL - REGNAM_AX |
4805 | : REGNAM_AL - REGNAM_EAX))->reg_name, | |
a540244d | 4806 | register_prefix, |
29b0f896 AM |
4807 | i.op[op].regs->reg_name, |
4808 | i.suffix); | |
4809 | #endif | |
4810 | continue; | |
4811 | } | |
4812 | /* Any other register is bad. */ | |
40fb9820 L |
4813 | if (i.types[op].bitfield.reg16 |
4814 | || i.types[op].bitfield.reg32 | |
4815 | || i.types[op].bitfield.reg64 | |
4816 | || i.types[op].bitfield.regmmx | |
4817 | || i.types[op].bitfield.regxmm | |
c0f3af97 | 4818 | || i.types[op].bitfield.regymm |
40fb9820 L |
4819 | || i.types[op].bitfield.sreg2 |
4820 | || i.types[op].bitfield.sreg3 | |
4821 | || i.types[op].bitfield.control | |
4822 | || i.types[op].bitfield.debug | |
4823 | || i.types[op].bitfield.test | |
4824 | || i.types[op].bitfield.floatreg | |
4825 | || i.types[op].bitfield.floatacc) | |
29b0f896 | 4826 | { |
a540244d L |
4827 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
4828 | register_prefix, | |
29b0f896 AM |
4829 | i.op[op].regs->reg_name, |
4830 | i.tm.name, | |
4831 | i.suffix); | |
4832 | return 0; | |
4833 | } | |
4834 | } | |
4835 | return 1; | |
4836 | } | |
4837 | ||
4838 | static int | |
e3bb37b5 | 4839 | check_long_reg (void) |
29b0f896 AM |
4840 | { |
4841 | int op; | |
4842 | ||
4843 | for (op = i.operands; --op >= 0;) | |
4844 | /* Reject eight bit registers, except where the template requires | |
4845 | them. (eg. movzb) */ | |
40fb9820 L |
4846 | if (i.types[op].bitfield.reg8 |
4847 | && (i.tm.operand_types[op].bitfield.reg16 | |
4848 | || i.tm.operand_types[op].bitfield.reg32 | |
4849 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 | 4850 | { |
a540244d L |
4851 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
4852 | register_prefix, | |
29b0f896 AM |
4853 | i.op[op].regs->reg_name, |
4854 | i.tm.name, | |
4855 | i.suffix); | |
4856 | return 0; | |
4857 | } | |
4858 | /* Warn if the e prefix on a general reg is missing. */ | |
4859 | else if ((!quiet_warnings || flag_code == CODE_64BIT) | |
40fb9820 L |
4860 | && i.types[op].bitfield.reg16 |
4861 | && (i.tm.operand_types[op].bitfield.reg32 | |
4862 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 AM |
4863 | { |
4864 | /* Prohibit these changes in the 64bit mode, since the | |
4865 | lowering is more complicated. */ | |
4866 | if (flag_code == CODE_64BIT) | |
252b5132 | 4867 | { |
2b5d6a91 | 4868 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
2ca3ace5 | 4869 | register_prefix, i.op[op].regs->reg_name, |
29b0f896 AM |
4870 | i.suffix); |
4871 | return 0; | |
252b5132 | 4872 | } |
29b0f896 AM |
4873 | #if REGISTER_WARNINGS |
4874 | else | |
a540244d L |
4875 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
4876 | register_prefix, | |
29b0f896 | 4877 | (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name, |
a540244d | 4878 | register_prefix, |
29b0f896 AM |
4879 | i.op[op].regs->reg_name, |
4880 | i.suffix); | |
4881 | #endif | |
252b5132 | 4882 | } |
29b0f896 | 4883 | /* Warn if the r prefix on a general reg is missing. */ |
40fb9820 L |
4884 | else if (i.types[op].bitfield.reg64 |
4885 | && (i.tm.operand_types[op].bitfield.reg32 | |
4886 | || i.tm.operand_types[op].bitfield.acc)) | |
252b5132 | 4887 | { |
34828aad | 4888 | if (intel_syntax |
ca61edf2 | 4889 | && i.tm.opcode_modifier.toqword |
40fb9820 | 4890 | && !i.types[0].bitfield.regxmm) |
34828aad | 4891 | { |
ca61edf2 | 4892 | /* Convert to QWORD. We want REX byte. */ |
34828aad L |
4893 | i.suffix = QWORD_MNEM_SUFFIX; |
4894 | } | |
4895 | else | |
4896 | { | |
2b5d6a91 | 4897 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
4898 | register_prefix, i.op[op].regs->reg_name, |
4899 | i.suffix); | |
4900 | return 0; | |
4901 | } | |
29b0f896 AM |
4902 | } |
4903 | return 1; | |
4904 | } | |
252b5132 | 4905 | |
29b0f896 | 4906 | static int |
e3bb37b5 | 4907 | check_qword_reg (void) |
29b0f896 AM |
4908 | { |
4909 | int op; | |
252b5132 | 4910 | |
29b0f896 AM |
4911 | for (op = i.operands; --op >= 0; ) |
4912 | /* Reject eight bit registers, except where the template requires | |
4913 | them. (eg. movzb) */ | |
40fb9820 L |
4914 | if (i.types[op].bitfield.reg8 |
4915 | && (i.tm.operand_types[op].bitfield.reg16 | |
4916 | || i.tm.operand_types[op].bitfield.reg32 | |
4917 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 | 4918 | { |
a540244d L |
4919 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
4920 | register_prefix, | |
29b0f896 AM |
4921 | i.op[op].regs->reg_name, |
4922 | i.tm.name, | |
4923 | i.suffix); | |
4924 | return 0; | |
4925 | } | |
4926 | /* Warn if the e prefix on a general reg is missing. */ | |
40fb9820 L |
4927 | else if ((i.types[op].bitfield.reg16 |
4928 | || i.types[op].bitfield.reg32) | |
4929 | && (i.tm.operand_types[op].bitfield.reg32 | |
4930 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 AM |
4931 | { |
4932 | /* Prohibit these changes in the 64bit mode, since the | |
4933 | lowering is more complicated. */ | |
34828aad | 4934 | if (intel_syntax |
ca61edf2 | 4935 | && i.tm.opcode_modifier.todword |
40fb9820 | 4936 | && !i.types[0].bitfield.regxmm) |
34828aad | 4937 | { |
ca61edf2 | 4938 | /* Convert to DWORD. We don't want REX byte. */ |
34828aad L |
4939 | i.suffix = LONG_MNEM_SUFFIX; |
4940 | } | |
4941 | else | |
4942 | { | |
2b5d6a91 | 4943 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
4944 | register_prefix, i.op[op].regs->reg_name, |
4945 | i.suffix); | |
4946 | return 0; | |
4947 | } | |
252b5132 | 4948 | } |
29b0f896 AM |
4949 | return 1; |
4950 | } | |
252b5132 | 4951 | |
29b0f896 | 4952 | static int |
e3bb37b5 | 4953 | check_word_reg (void) |
29b0f896 AM |
4954 | { |
4955 | int op; | |
4956 | for (op = i.operands; --op >= 0;) | |
4957 | /* Reject eight bit registers, except where the template requires | |
4958 | them. (eg. movzb) */ | |
40fb9820 L |
4959 | if (i.types[op].bitfield.reg8 |
4960 | && (i.tm.operand_types[op].bitfield.reg16 | |
4961 | || i.tm.operand_types[op].bitfield.reg32 | |
4962 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 | 4963 | { |
a540244d L |
4964 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
4965 | register_prefix, | |
29b0f896 AM |
4966 | i.op[op].regs->reg_name, |
4967 | i.tm.name, | |
4968 | i.suffix); | |
4969 | return 0; | |
4970 | } | |
4971 | /* Warn if the e prefix on a general reg is present. */ | |
4972 | else if ((!quiet_warnings || flag_code == CODE_64BIT) | |
40fb9820 L |
4973 | && i.types[op].bitfield.reg32 |
4974 | && (i.tm.operand_types[op].bitfield.reg16 | |
4975 | || i.tm.operand_types[op].bitfield.acc)) | |
252b5132 | 4976 | { |
29b0f896 AM |
4977 | /* Prohibit these changes in the 64bit mode, since the |
4978 | lowering is more complicated. */ | |
4979 | if (flag_code == CODE_64BIT) | |
252b5132 | 4980 | { |
2b5d6a91 | 4981 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
2ca3ace5 | 4982 | register_prefix, i.op[op].regs->reg_name, |
29b0f896 AM |
4983 | i.suffix); |
4984 | return 0; | |
252b5132 | 4985 | } |
29b0f896 AM |
4986 | else |
4987 | #if REGISTER_WARNINGS | |
a540244d L |
4988 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
4989 | register_prefix, | |
29b0f896 | 4990 | (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name, |
a540244d | 4991 | register_prefix, |
29b0f896 AM |
4992 | i.op[op].regs->reg_name, |
4993 | i.suffix); | |
4994 | #endif | |
4995 | } | |
4996 | return 1; | |
4997 | } | |
252b5132 | 4998 | |
29b0f896 | 4999 | static int |
40fb9820 | 5000 | update_imm (unsigned int j) |
29b0f896 | 5001 | { |
bc0844ae | 5002 | i386_operand_type overlap = i.types[j]; |
40fb9820 L |
5003 | if ((overlap.bitfield.imm8 |
5004 | || overlap.bitfield.imm8s | |
5005 | || overlap.bitfield.imm16 | |
5006 | || overlap.bitfield.imm32 | |
5007 | || overlap.bitfield.imm32s | |
5008 | || overlap.bitfield.imm64) | |
0dfbf9d7 L |
5009 | && !operand_type_equal (&overlap, &imm8) |
5010 | && !operand_type_equal (&overlap, &imm8s) | |
5011 | && !operand_type_equal (&overlap, &imm16) | |
5012 | && !operand_type_equal (&overlap, &imm32) | |
5013 | && !operand_type_equal (&overlap, &imm32s) | |
5014 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 AM |
5015 | { |
5016 | if (i.suffix) | |
5017 | { | |
40fb9820 L |
5018 | i386_operand_type temp; |
5019 | ||
0dfbf9d7 | 5020 | operand_type_set (&temp, 0); |
7ab9ffdd | 5021 | if (i.suffix == BYTE_MNEM_SUFFIX) |
40fb9820 L |
5022 | { |
5023 | temp.bitfield.imm8 = overlap.bitfield.imm8; | |
5024 | temp.bitfield.imm8s = overlap.bitfield.imm8s; | |
5025 | } | |
5026 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
5027 | temp.bitfield.imm16 = overlap.bitfield.imm16; | |
5028 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
5029 | { | |
5030 | temp.bitfield.imm64 = overlap.bitfield.imm64; | |
5031 | temp.bitfield.imm32s = overlap.bitfield.imm32s; | |
5032 | } | |
5033 | else | |
5034 | temp.bitfield.imm32 = overlap.bitfield.imm32; | |
5035 | overlap = temp; | |
29b0f896 | 5036 | } |
0dfbf9d7 L |
5037 | else if (operand_type_equal (&overlap, &imm16_32_32s) |
5038 | || operand_type_equal (&overlap, &imm16_32) | |
5039 | || operand_type_equal (&overlap, &imm16_32s)) | |
29b0f896 | 5040 | { |
40fb9820 | 5041 | if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
65da13b5 | 5042 | overlap = imm16; |
40fb9820 | 5043 | else |
65da13b5 | 5044 | overlap = imm32s; |
29b0f896 | 5045 | } |
0dfbf9d7 L |
5046 | if (!operand_type_equal (&overlap, &imm8) |
5047 | && !operand_type_equal (&overlap, &imm8s) | |
5048 | && !operand_type_equal (&overlap, &imm16) | |
5049 | && !operand_type_equal (&overlap, &imm32) | |
5050 | && !operand_type_equal (&overlap, &imm32s) | |
5051 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 | 5052 | { |
4eed87de AM |
5053 | as_bad (_("no instruction mnemonic suffix given; " |
5054 | "can't determine immediate size")); | |
29b0f896 AM |
5055 | return 0; |
5056 | } | |
5057 | } | |
40fb9820 | 5058 | i.types[j] = overlap; |
29b0f896 | 5059 | |
40fb9820 L |
5060 | return 1; |
5061 | } | |
5062 | ||
5063 | static int | |
5064 | finalize_imm (void) | |
5065 | { | |
bc0844ae | 5066 | unsigned int j, n; |
29b0f896 | 5067 | |
bc0844ae L |
5068 | /* Update the first 2 immediate operands. */ |
5069 | n = i.operands > 2 ? 2 : i.operands; | |
5070 | if (n) | |
5071 | { | |
5072 | for (j = 0; j < n; j++) | |
5073 | if (update_imm (j) == 0) | |
5074 | return 0; | |
40fb9820 | 5075 | |
bc0844ae L |
5076 | /* The 3rd operand can't be immediate operand. */ |
5077 | gas_assert (operand_type_check (i.types[2], imm) == 0); | |
5078 | } | |
29b0f896 AM |
5079 | |
5080 | return 1; | |
5081 | } | |
5082 | ||
c0f3af97 L |
5083 | static int |
5084 | bad_implicit_operand (int xmm) | |
5085 | { | |
91d6fa6a NC |
5086 | const char *ireg = xmm ? "xmm0" : "ymm0"; |
5087 | ||
c0f3af97 L |
5088 | if (intel_syntax) |
5089 | as_bad (_("the last operand of `%s' must be `%s%s'"), | |
91d6fa6a | 5090 | i.tm.name, register_prefix, ireg); |
c0f3af97 L |
5091 | else |
5092 | as_bad (_("the first operand of `%s' must be `%s%s'"), | |
91d6fa6a | 5093 | i.tm.name, register_prefix, ireg); |
c0f3af97 L |
5094 | return 0; |
5095 | } | |
5096 | ||
29b0f896 | 5097 | static int |
e3bb37b5 | 5098 | process_operands (void) |
29b0f896 AM |
5099 | { |
5100 | /* Default segment register this instruction will use for memory | |
5101 | accesses. 0 means unknown. This is only for optimizing out | |
5102 | unnecessary segment overrides. */ | |
5103 | const seg_entry *default_seg = 0; | |
5104 | ||
2426c15f | 5105 | if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv) |
29b0f896 | 5106 | { |
91d6fa6a NC |
5107 | unsigned int dupl = i.operands; |
5108 | unsigned int dest = dupl - 1; | |
9fcfb3d7 L |
5109 | unsigned int j; |
5110 | ||
c0f3af97 | 5111 | /* The destination must be an xmm register. */ |
9c2799c2 | 5112 | gas_assert (i.reg_operands |
91d6fa6a | 5113 | && MAX_OPERANDS > dupl |
7ab9ffdd | 5114 | && operand_type_equal (&i.types[dest], ®xmm)); |
c0f3af97 L |
5115 | |
5116 | if (i.tm.opcode_modifier.firstxmm0) | |
e2ec9d29 | 5117 | { |
c0f3af97 | 5118 | /* The first operand is implicit and must be xmm0. */ |
9c2799c2 | 5119 | gas_assert (operand_type_equal (&i.types[0], ®xmm)); |
4c692bc7 | 5120 | if (register_number (i.op[0].regs) != 0) |
c0f3af97 L |
5121 | return bad_implicit_operand (1); |
5122 | ||
8cd7925b | 5123 | if (i.tm.opcode_modifier.vexsources == VEX3SOURCES) |
c0f3af97 L |
5124 | { |
5125 | /* Keep xmm0 for instructions with VEX prefix and 3 | |
5126 | sources. */ | |
5127 | goto duplicate; | |
5128 | } | |
e2ec9d29 | 5129 | else |
c0f3af97 L |
5130 | { |
5131 | /* We remove the first xmm0 and keep the number of | |
5132 | operands unchanged, which in fact duplicates the | |
5133 | destination. */ | |
5134 | for (j = 1; j < i.operands; j++) | |
5135 | { | |
5136 | i.op[j - 1] = i.op[j]; | |
5137 | i.types[j - 1] = i.types[j]; | |
5138 | i.tm.operand_types[j - 1] = i.tm.operand_types[j]; | |
5139 | } | |
5140 | } | |
5141 | } | |
5142 | else if (i.tm.opcode_modifier.implicit1stxmm0) | |
7ab9ffdd | 5143 | { |
91d6fa6a | 5144 | gas_assert ((MAX_OPERANDS - 1) > dupl |
8cd7925b L |
5145 | && (i.tm.opcode_modifier.vexsources |
5146 | == VEX3SOURCES)); | |
c0f3af97 L |
5147 | |
5148 | /* Add the implicit xmm0 for instructions with VEX prefix | |
5149 | and 3 sources. */ | |
5150 | for (j = i.operands; j > 0; j--) | |
5151 | { | |
5152 | i.op[j] = i.op[j - 1]; | |
5153 | i.types[j] = i.types[j - 1]; | |
5154 | i.tm.operand_types[j] = i.tm.operand_types[j - 1]; | |
5155 | } | |
5156 | i.op[0].regs | |
5157 | = (const reg_entry *) hash_find (reg_hash, "xmm0"); | |
7ab9ffdd | 5158 | i.types[0] = regxmm; |
c0f3af97 L |
5159 | i.tm.operand_types[0] = regxmm; |
5160 | ||
5161 | i.operands += 2; | |
5162 | i.reg_operands += 2; | |
5163 | i.tm.operands += 2; | |
5164 | ||
91d6fa6a | 5165 | dupl++; |
c0f3af97 | 5166 | dest++; |
91d6fa6a NC |
5167 | i.op[dupl] = i.op[dest]; |
5168 | i.types[dupl] = i.types[dest]; | |
5169 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
e2ec9d29 | 5170 | } |
c0f3af97 L |
5171 | else |
5172 | { | |
5173 | duplicate: | |
5174 | i.operands++; | |
5175 | i.reg_operands++; | |
5176 | i.tm.operands++; | |
5177 | ||
91d6fa6a NC |
5178 | i.op[dupl] = i.op[dest]; |
5179 | i.types[dupl] = i.types[dest]; | |
5180 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
c0f3af97 L |
5181 | } |
5182 | ||
5183 | if (i.tm.opcode_modifier.immext) | |
5184 | process_immext (); | |
5185 | } | |
5186 | else if (i.tm.opcode_modifier.firstxmm0) | |
5187 | { | |
5188 | unsigned int j; | |
5189 | ||
5190 | /* The first operand is implicit and must be xmm0/ymm0. */ | |
9c2799c2 | 5191 | gas_assert (i.reg_operands |
7ab9ffdd L |
5192 | && (operand_type_equal (&i.types[0], ®xmm) |
5193 | || operand_type_equal (&i.types[0], ®ymm))); | |
4c692bc7 | 5194 | if (register_number (i.op[0].regs) != 0) |
c0f3af97 | 5195 | return bad_implicit_operand (i.types[0].bitfield.regxmm); |
9fcfb3d7 L |
5196 | |
5197 | for (j = 1; j < i.operands; j++) | |
5198 | { | |
5199 | i.op[j - 1] = i.op[j]; | |
5200 | i.types[j - 1] = i.types[j]; | |
5201 | ||
5202 | /* We need to adjust fields in i.tm since they are used by | |
5203 | build_modrm_byte. */ | |
5204 | i.tm.operand_types [j - 1] = i.tm.operand_types [j]; | |
5205 | } | |
5206 | ||
e2ec9d29 L |
5207 | i.operands--; |
5208 | i.reg_operands--; | |
e2ec9d29 L |
5209 | i.tm.operands--; |
5210 | } | |
5211 | else if (i.tm.opcode_modifier.regkludge) | |
5212 | { | |
5213 | /* The imul $imm, %reg instruction is converted into | |
5214 | imul $imm, %reg, %reg, and the clr %reg instruction | |
5215 | is converted into xor %reg, %reg. */ | |
5216 | ||
5217 | unsigned int first_reg_op; | |
5218 | ||
5219 | if (operand_type_check (i.types[0], reg)) | |
5220 | first_reg_op = 0; | |
5221 | else | |
5222 | first_reg_op = 1; | |
5223 | /* Pretend we saw the extra register operand. */ | |
9c2799c2 | 5224 | gas_assert (i.reg_operands == 1 |
7ab9ffdd | 5225 | && i.op[first_reg_op + 1].regs == 0); |
e2ec9d29 L |
5226 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; |
5227 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
5228 | i.operands++; | |
5229 | i.reg_operands++; | |
29b0f896 AM |
5230 | } |
5231 | ||
40fb9820 | 5232 | if (i.tm.opcode_modifier.shortform) |
29b0f896 | 5233 | { |
40fb9820 L |
5234 | if (i.types[0].bitfield.sreg2 |
5235 | || i.types[0].bitfield.sreg3) | |
29b0f896 | 5236 | { |
4eed87de AM |
5237 | if (i.tm.base_opcode == POP_SEG_SHORT |
5238 | && i.op[0].regs->reg_num == 1) | |
29b0f896 | 5239 | { |
a87af027 | 5240 | as_bad (_("you can't `pop %scs'"), register_prefix); |
4eed87de | 5241 | return 0; |
29b0f896 | 5242 | } |
4eed87de AM |
5243 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); |
5244 | if ((i.op[0].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 5245 | i.rex |= REX_B; |
4eed87de AM |
5246 | } |
5247 | else | |
5248 | { | |
7ab9ffdd | 5249 | /* The register or float register operand is in operand |
85f10a01 | 5250 | 0 or 1. */ |
40fb9820 | 5251 | unsigned int op; |
7ab9ffdd L |
5252 | |
5253 | if (i.types[0].bitfield.floatreg | |
5254 | || operand_type_check (i.types[0], reg)) | |
5255 | op = 0; | |
5256 | else | |
5257 | op = 1; | |
4eed87de AM |
5258 | /* Register goes in low 3 bits of opcode. */ |
5259 | i.tm.base_opcode |= i.op[op].regs->reg_num; | |
5260 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 5261 | i.rex |= REX_B; |
40fb9820 | 5262 | if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 | 5263 | { |
4eed87de AM |
5264 | /* Warn about some common errors, but press on regardless. |
5265 | The first case can be generated by gcc (<= 2.8.1). */ | |
5266 | if (i.operands == 2) | |
5267 | { | |
5268 | /* Reversed arguments on faddp, fsubp, etc. */ | |
a540244d | 5269 | as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, |
d8a1b51e JB |
5270 | register_prefix, i.op[!intel_syntax].regs->reg_name, |
5271 | register_prefix, i.op[intel_syntax].regs->reg_name); | |
4eed87de AM |
5272 | } |
5273 | else | |
5274 | { | |
5275 | /* Extraneous `l' suffix on fp insn. */ | |
a540244d L |
5276 | as_warn (_("translating to `%s %s%s'"), i.tm.name, |
5277 | register_prefix, i.op[0].regs->reg_name); | |
4eed87de | 5278 | } |
29b0f896 AM |
5279 | } |
5280 | } | |
5281 | } | |
40fb9820 | 5282 | else if (i.tm.opcode_modifier.modrm) |
29b0f896 AM |
5283 | { |
5284 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
52271982 AM |
5285 | must be put into the modrm byte). Now, we make the modrm and |
5286 | index base bytes based on all the info we've collected. */ | |
29b0f896 AM |
5287 | |
5288 | default_seg = build_modrm_byte (); | |
5289 | } | |
8a2ed489 | 5290 | else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32) |
29b0f896 AM |
5291 | { |
5292 | default_seg = &ds; | |
5293 | } | |
40fb9820 | 5294 | else if (i.tm.opcode_modifier.isstring) |
29b0f896 AM |
5295 | { |
5296 | /* For the string instructions that allow a segment override | |
5297 | on one of their operands, the default segment is ds. */ | |
5298 | default_seg = &ds; | |
5299 | } | |
5300 | ||
75178d9d L |
5301 | if (i.tm.base_opcode == 0x8d /* lea */ |
5302 | && i.seg[0] | |
5303 | && !quiet_warnings) | |
30123838 | 5304 | as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); |
52271982 AM |
5305 | |
5306 | /* If a segment was explicitly specified, and the specified segment | |
5307 | is not the default, use an opcode prefix to select it. If we | |
5308 | never figured out what the default segment is, then default_seg | |
5309 | will be zero at this point, and the specified segment prefix will | |
5310 | always be used. */ | |
29b0f896 AM |
5311 | if ((i.seg[0]) && (i.seg[0] != default_seg)) |
5312 | { | |
5313 | if (!add_prefix (i.seg[0]->seg_prefix)) | |
5314 | return 0; | |
5315 | } | |
5316 | return 1; | |
5317 | } | |
5318 | ||
5319 | static const seg_entry * | |
e3bb37b5 | 5320 | build_modrm_byte (void) |
29b0f896 AM |
5321 | { |
5322 | const seg_entry *default_seg = 0; | |
c0f3af97 | 5323 | unsigned int source, dest; |
8cd7925b | 5324 | int vex_3_sources; |
c0f3af97 L |
5325 | |
5326 | /* The first operand of instructions with VEX prefix and 3 sources | |
5327 | must be VEX_Imm4. */ | |
8cd7925b | 5328 | vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES; |
c0f3af97 L |
5329 | if (vex_3_sources) |
5330 | { | |
91d6fa6a | 5331 | unsigned int nds, reg_slot; |
4c2c6516 | 5332 | expressionS *exp; |
c0f3af97 | 5333 | |
922d8de8 | 5334 | if (i.tm.opcode_modifier.veximmext |
a683cc34 SP |
5335 | && i.tm.opcode_modifier.immext) |
5336 | { | |
5337 | dest = i.operands - 2; | |
5338 | gas_assert (dest == 3); | |
5339 | } | |
922d8de8 | 5340 | else |
a683cc34 | 5341 | dest = i.operands - 1; |
c0f3af97 | 5342 | nds = dest - 1; |
922d8de8 | 5343 | |
a683cc34 SP |
5344 | /* There are 2 kinds of instructions: |
5345 | 1. 5 operands: 4 register operands or 3 register operands | |
5346 | plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and | |
5347 | VexW0 or VexW1. The destination must be either XMM or YMM | |
5348 | register. | |
5349 | 2. 4 operands: 4 register operands or 3 register operands | |
5350 | plus 1 memory operand, VexXDS, and VexImmExt */ | |
922d8de8 | 5351 | gas_assert ((i.reg_operands == 4 |
a683cc34 SP |
5352 | || (i.reg_operands == 3 && i.mem_operands == 1)) |
5353 | && i.tm.opcode_modifier.vexvvvv == VEXXDS | |
5354 | && (i.tm.opcode_modifier.veximmext | |
5355 | || (i.imm_operands == 1 | |
5356 | && i.types[0].bitfield.vec_imm4 | |
5357 | && (i.tm.opcode_modifier.vexw == VEXW0 | |
5358 | || i.tm.opcode_modifier.vexw == VEXW1) | |
5359 | && (operand_type_equal (&i.tm.operand_types[dest], ®xmm) | |
5360 | || operand_type_equal (&i.tm.operand_types[dest], ®ymm))))); | |
5361 | ||
5362 | if (i.imm_operands == 0) | |
5363 | { | |
5364 | /* When there is no immediate operand, generate an 8bit | |
5365 | immediate operand to encode the first operand. */ | |
5366 | exp = &im_expressions[i.imm_operands++]; | |
5367 | i.op[i.operands].imms = exp; | |
5368 | i.types[i.operands] = imm8; | |
5369 | i.operands++; | |
5370 | /* If VexW1 is set, the first operand is the source and | |
5371 | the second operand is encoded in the immediate operand. */ | |
5372 | if (i.tm.opcode_modifier.vexw == VEXW1) | |
5373 | { | |
5374 | source = 0; | |
5375 | reg_slot = 1; | |
5376 | } | |
5377 | else | |
5378 | { | |
5379 | source = 1; | |
5380 | reg_slot = 0; | |
5381 | } | |
5382 | ||
5383 | /* FMA swaps REG and NDS. */ | |
5384 | if (i.tm.cpu_flags.bitfield.cpufma) | |
5385 | { | |
5386 | unsigned int tmp; | |
5387 | tmp = reg_slot; | |
5388 | reg_slot = nds; | |
5389 | nds = tmp; | |
5390 | } | |
5391 | ||
24981e7b L |
5392 | gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot], |
5393 | ®xmm) | |
a683cc34 SP |
5394 | || operand_type_equal (&i.tm.operand_types[reg_slot], |
5395 | ®ymm)); | |
5396 | exp->X_op = O_constant; | |
4c692bc7 | 5397 | exp->X_add_number = register_number (i.op[reg_slot].regs) << 4; |
a683cc34 | 5398 | } |
922d8de8 | 5399 | else |
a683cc34 SP |
5400 | { |
5401 | unsigned int imm_slot; | |
5402 | ||
5403 | if (i.tm.opcode_modifier.vexw == VEXW0) | |
5404 | { | |
5405 | /* If VexW0 is set, the third operand is the source and | |
5406 | the second operand is encoded in the immediate | |
5407 | operand. */ | |
5408 | source = 2; | |
5409 | reg_slot = 1; | |
5410 | } | |
5411 | else | |
5412 | { | |
5413 | /* VexW1 is set, the second operand is the source and | |
5414 | the third operand is encoded in the immediate | |
5415 | operand. */ | |
5416 | source = 1; | |
5417 | reg_slot = 2; | |
5418 | } | |
5419 | ||
5420 | if (i.tm.opcode_modifier.immext) | |
5421 | { | |
5422 | /* When ImmExt is set, the immdiate byte is the last | |
5423 | operand. */ | |
5424 | imm_slot = i.operands - 1; | |
5425 | source--; | |
5426 | reg_slot--; | |
5427 | } | |
5428 | else | |
5429 | { | |
5430 | imm_slot = 0; | |
5431 | ||
5432 | /* Turn on Imm8 so that output_imm will generate it. */ | |
5433 | i.types[imm_slot].bitfield.imm8 = 1; | |
5434 | } | |
5435 | ||
24981e7b L |
5436 | gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot], |
5437 | ®xmm) | |
5438 | || operand_type_equal (&i.tm.operand_types[reg_slot], | |
5439 | ®ymm)); | |
a683cc34 | 5440 | i.op[imm_slot].imms->X_add_number |
4c692bc7 | 5441 | |= register_number (i.op[reg_slot].regs) << 4; |
a683cc34 SP |
5442 | } |
5443 | ||
5444 | gas_assert (operand_type_equal (&i.tm.operand_types[nds], ®xmm) | |
5445 | || operand_type_equal (&i.tm.operand_types[nds], | |
5446 | ®ymm)); | |
dae39acc | 5447 | i.vex.register_specifier = i.op[nds].regs; |
c0f3af97 L |
5448 | } |
5449 | else | |
5450 | source = dest = 0; | |
29b0f896 AM |
5451 | |
5452 | /* i.reg_operands MUST be the number of real register operands; | |
c0f3af97 L |
5453 | implicit registers do not count. If there are 3 register |
5454 | operands, it must be a instruction with VexNDS. For a | |
5455 | instruction with VexNDD, the destination register is encoded | |
5456 | in VEX prefix. If there are 4 register operands, it must be | |
5457 | a instruction with VEX prefix and 3 sources. */ | |
7ab9ffdd L |
5458 | if (i.mem_operands == 0 |
5459 | && ((i.reg_operands == 2 | |
2426c15f | 5460 | && i.tm.opcode_modifier.vexvvvv <= VEXXDS) |
7ab9ffdd | 5461 | || (i.reg_operands == 3 |
2426c15f | 5462 | && i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd | 5463 | || (i.reg_operands == 4 && vex_3_sources))) |
29b0f896 | 5464 | { |
cab737b9 L |
5465 | switch (i.operands) |
5466 | { | |
5467 | case 2: | |
5468 | source = 0; | |
5469 | break; | |
5470 | case 3: | |
c81128dc L |
5471 | /* When there are 3 operands, one of them may be immediate, |
5472 | which may be the first or the last operand. Otherwise, | |
c0f3af97 L |
5473 | the first operand must be shift count register (cl) or it |
5474 | is an instruction with VexNDS. */ | |
9c2799c2 | 5475 | gas_assert (i.imm_operands == 1 |
7ab9ffdd | 5476 | || (i.imm_operands == 0 |
2426c15f | 5477 | && (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd | 5478 | || i.types[0].bitfield.shiftcount))); |
40fb9820 L |
5479 | if (operand_type_check (i.types[0], imm) |
5480 | || i.types[0].bitfield.shiftcount) | |
5481 | source = 1; | |
5482 | else | |
5483 | source = 0; | |
cab737b9 L |
5484 | break; |
5485 | case 4: | |
368d64cc L |
5486 | /* When there are 4 operands, the first two must be 8bit |
5487 | immediate operands. The source operand will be the 3rd | |
c0f3af97 L |
5488 | one. |
5489 | ||
5490 | For instructions with VexNDS, if the first operand | |
5491 | an imm8, the source operand is the 2nd one. If the last | |
5492 | operand is imm8, the source operand is the first one. */ | |
9c2799c2 | 5493 | gas_assert ((i.imm_operands == 2 |
7ab9ffdd L |
5494 | && i.types[0].bitfield.imm8 |
5495 | && i.types[1].bitfield.imm8) | |
2426c15f | 5496 | || (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd L |
5497 | && i.imm_operands == 1 |
5498 | && (i.types[0].bitfield.imm8 | |
5499 | || i.types[i.operands - 1].bitfield.imm8))); | |
9f2670f2 L |
5500 | if (i.imm_operands == 2) |
5501 | source = 2; | |
5502 | else | |
c0f3af97 L |
5503 | { |
5504 | if (i.types[0].bitfield.imm8) | |
5505 | source = 1; | |
5506 | else | |
5507 | source = 0; | |
5508 | } | |
c0f3af97 L |
5509 | break; |
5510 | case 5: | |
cab737b9 L |
5511 | break; |
5512 | default: | |
5513 | abort (); | |
5514 | } | |
5515 | ||
c0f3af97 L |
5516 | if (!vex_3_sources) |
5517 | { | |
5518 | dest = source + 1; | |
5519 | ||
2426c15f | 5520 | if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
c0f3af97 L |
5521 | { |
5522 | /* For instructions with VexNDS, the register-only | |
f12dc422 L |
5523 | source operand must be 32/64bit integer, XMM or |
5524 | YMM register. It is encoded in VEX prefix. We | |
5525 | need to clear RegMem bit before calling | |
5526 | operand_type_equal. */ | |
5527 | ||
5528 | i386_operand_type op; | |
5529 | unsigned int vvvv; | |
5530 | ||
5531 | /* Check register-only source operand when two source | |
5532 | operands are swapped. */ | |
5533 | if (!i.tm.operand_types[source].bitfield.baseindex | |
5534 | && i.tm.operand_types[dest].bitfield.baseindex) | |
5535 | { | |
5536 | vvvv = source; | |
5537 | source = dest; | |
5538 | } | |
5539 | else | |
5540 | vvvv = dest; | |
5541 | ||
5542 | op = i.tm.operand_types[vvvv]; | |
fa99fab2 | 5543 | op.bitfield.regmem = 0; |
c0f3af97 | 5544 | if ((dest + 1) >= i.operands |
f12dc422 L |
5545 | || (op.bitfield.reg32 != 1 |
5546 | && !op.bitfield.reg64 != 1 | |
5547 | && !operand_type_equal (&op, ®xmm) | |
fa99fab2 | 5548 | && !operand_type_equal (&op, ®ymm))) |
c0f3af97 | 5549 | abort (); |
f12dc422 | 5550 | i.vex.register_specifier = i.op[vvvv].regs; |
c0f3af97 L |
5551 | dest++; |
5552 | } | |
5553 | } | |
29b0f896 AM |
5554 | |
5555 | i.rm.mode = 3; | |
5556 | /* One of the register operands will be encoded in the i.tm.reg | |
5557 | field, the other in the combined i.tm.mode and i.tm.regmem | |
5558 | fields. If no form of this instruction supports a memory | |
5559 | destination operand, then we assume the source operand may | |
5560 | sometimes be a memory operand and so we need to store the | |
5561 | destination in the i.rm.reg field. */ | |
40fb9820 L |
5562 | if (!i.tm.operand_types[dest].bitfield.regmem |
5563 | && operand_type_check (i.tm.operand_types[dest], anymem) == 0) | |
29b0f896 AM |
5564 | { |
5565 | i.rm.reg = i.op[dest].regs->reg_num; | |
5566 | i.rm.regmem = i.op[source].regs->reg_num; | |
5567 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 5568 | i.rex |= REX_R; |
29b0f896 | 5569 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 5570 | i.rex |= REX_B; |
29b0f896 AM |
5571 | } |
5572 | else | |
5573 | { | |
5574 | i.rm.reg = i.op[source].regs->reg_num; | |
5575 | i.rm.regmem = i.op[dest].regs->reg_num; | |
5576 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 5577 | i.rex |= REX_B; |
29b0f896 | 5578 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 5579 | i.rex |= REX_R; |
29b0f896 | 5580 | } |
161a04f6 | 5581 | if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B))) |
c4a530c5 | 5582 | { |
40fb9820 L |
5583 | if (!i.types[0].bitfield.control |
5584 | && !i.types[1].bitfield.control) | |
c4a530c5 | 5585 | abort (); |
161a04f6 | 5586 | i.rex &= ~(REX_R | REX_B); |
c4a530c5 JB |
5587 | add_prefix (LOCK_PREFIX_OPCODE); |
5588 | } | |
29b0f896 AM |
5589 | } |
5590 | else | |
5591 | { /* If it's not 2 reg operands... */ | |
c0f3af97 L |
5592 | unsigned int mem; |
5593 | ||
29b0f896 AM |
5594 | if (i.mem_operands) |
5595 | { | |
5596 | unsigned int fake_zero_displacement = 0; | |
99018f42 | 5597 | unsigned int op; |
4eed87de | 5598 | |
7ab9ffdd L |
5599 | for (op = 0; op < i.operands; op++) |
5600 | if (operand_type_check (i.types[op], anymem)) | |
5601 | break; | |
7ab9ffdd | 5602 | gas_assert (op < i.operands); |
29b0f896 | 5603 | |
6c30d220 L |
5604 | if (i.tm.opcode_modifier.vecsib) |
5605 | { | |
5606 | if (i.index_reg->reg_num == RegEiz | |
5607 | || i.index_reg->reg_num == RegRiz) | |
5608 | abort (); | |
5609 | ||
5610 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
5611 | if (!i.base_reg) | |
5612 | { | |
5613 | i.sib.base = NO_BASE_REGISTER; | |
5614 | i.sib.scale = i.log2_scale_factor; | |
5615 | i.types[op].bitfield.disp8 = 0; | |
5616 | i.types[op].bitfield.disp16 = 0; | |
5617 | i.types[op].bitfield.disp64 = 0; | |
5618 | if (flag_code != CODE_64BIT) | |
5619 | { | |
5620 | /* Must be 32 bit */ | |
5621 | i.types[op].bitfield.disp32 = 1; | |
5622 | i.types[op].bitfield.disp32s = 0; | |
5623 | } | |
5624 | else | |
5625 | { | |
5626 | i.types[op].bitfield.disp32 = 0; | |
5627 | i.types[op].bitfield.disp32s = 1; | |
5628 | } | |
5629 | } | |
5630 | i.sib.index = i.index_reg->reg_num; | |
5631 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
5632 | i.rex |= REX_X; | |
5633 | } | |
5634 | ||
29b0f896 AM |
5635 | default_seg = &ds; |
5636 | ||
5637 | if (i.base_reg == 0) | |
5638 | { | |
5639 | i.rm.mode = 0; | |
5640 | if (!i.disp_operands) | |
6c30d220 L |
5641 | { |
5642 | fake_zero_displacement = 1; | |
5643 | /* Instructions with VSIB byte need 32bit displacement | |
5644 | if there is no base register. */ | |
5645 | if (i.tm.opcode_modifier.vecsib) | |
5646 | i.types[op].bitfield.disp32 = 1; | |
5647 | } | |
29b0f896 AM |
5648 | if (i.index_reg == 0) |
5649 | { | |
6c30d220 | 5650 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 5651 | /* Operand is just <disp> */ |
20f0a1fc | 5652 | if (flag_code == CODE_64BIT) |
29b0f896 AM |
5653 | { |
5654 | /* 64bit mode overwrites the 32bit absolute | |
5655 | addressing by RIP relative addressing and | |
5656 | absolute addressing is encoded by one of the | |
5657 | redundant SIB forms. */ | |
5658 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
5659 | i.sib.base = NO_BASE_REGISTER; | |
5660 | i.sib.index = NO_INDEX_REGISTER; | |
fc225355 | 5661 | i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) |
40fb9820 | 5662 | ? disp32s : disp32); |
20f0a1fc | 5663 | } |
fc225355 L |
5664 | else if ((flag_code == CODE_16BIT) |
5665 | ^ (i.prefix[ADDR_PREFIX] != 0)) | |
20f0a1fc NC |
5666 | { |
5667 | i.rm.regmem = NO_BASE_REGISTER_16; | |
40fb9820 | 5668 | i.types[op] = disp16; |
20f0a1fc NC |
5669 | } |
5670 | else | |
5671 | { | |
5672 | i.rm.regmem = NO_BASE_REGISTER; | |
40fb9820 | 5673 | i.types[op] = disp32; |
29b0f896 AM |
5674 | } |
5675 | } | |
6c30d220 | 5676 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 5677 | { |
6c30d220 | 5678 | /* !i.base_reg && i.index_reg */ |
db51cc60 L |
5679 | if (i.index_reg->reg_num == RegEiz |
5680 | || i.index_reg->reg_num == RegRiz) | |
5681 | i.sib.index = NO_INDEX_REGISTER; | |
5682 | else | |
5683 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
5684 | i.sib.base = NO_BASE_REGISTER; |
5685 | i.sib.scale = i.log2_scale_factor; | |
5686 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
40fb9820 L |
5687 | i.types[op].bitfield.disp8 = 0; |
5688 | i.types[op].bitfield.disp16 = 0; | |
5689 | i.types[op].bitfield.disp64 = 0; | |
29b0f896 | 5690 | if (flag_code != CODE_64BIT) |
40fb9820 L |
5691 | { |
5692 | /* Must be 32 bit */ | |
5693 | i.types[op].bitfield.disp32 = 1; | |
5694 | i.types[op].bitfield.disp32s = 0; | |
5695 | } | |
29b0f896 | 5696 | else |
40fb9820 L |
5697 | { |
5698 | i.types[op].bitfield.disp32 = 0; | |
5699 | i.types[op].bitfield.disp32s = 1; | |
5700 | } | |
29b0f896 | 5701 | if ((i.index_reg->reg_flags & RegRex) != 0) |
161a04f6 | 5702 | i.rex |= REX_X; |
29b0f896 AM |
5703 | } |
5704 | } | |
5705 | /* RIP addressing for 64bit mode. */ | |
9a04903e JB |
5706 | else if (i.base_reg->reg_num == RegRip || |
5707 | i.base_reg->reg_num == RegEip) | |
29b0f896 | 5708 | { |
6c30d220 | 5709 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 5710 | i.rm.regmem = NO_BASE_REGISTER; |
40fb9820 L |
5711 | i.types[op].bitfield.disp8 = 0; |
5712 | i.types[op].bitfield.disp16 = 0; | |
5713 | i.types[op].bitfield.disp32 = 0; | |
5714 | i.types[op].bitfield.disp32s = 1; | |
5715 | i.types[op].bitfield.disp64 = 0; | |
71903a11 | 5716 | i.flags[op] |= Operand_PCrel; |
20f0a1fc NC |
5717 | if (! i.disp_operands) |
5718 | fake_zero_displacement = 1; | |
29b0f896 | 5719 | } |
40fb9820 | 5720 | else if (i.base_reg->reg_type.bitfield.reg16) |
29b0f896 | 5721 | { |
6c30d220 | 5722 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
5723 | switch (i.base_reg->reg_num) |
5724 | { | |
5725 | case 3: /* (%bx) */ | |
5726 | if (i.index_reg == 0) | |
5727 | i.rm.regmem = 7; | |
5728 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
5729 | i.rm.regmem = i.index_reg->reg_num - 6; | |
5730 | break; | |
5731 | case 5: /* (%bp) */ | |
5732 | default_seg = &ss; | |
5733 | if (i.index_reg == 0) | |
5734 | { | |
5735 | i.rm.regmem = 6; | |
40fb9820 | 5736 | if (operand_type_check (i.types[op], disp) == 0) |
29b0f896 AM |
5737 | { |
5738 | /* fake (%bp) into 0(%bp) */ | |
40fb9820 | 5739 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 5740 | fake_zero_displacement = 1; |
29b0f896 AM |
5741 | } |
5742 | } | |
5743 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
5744 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
5745 | break; | |
5746 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
5747 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
5748 | } | |
5749 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
5750 | } | |
5751 | else /* i.base_reg and 32/64 bit mode */ | |
5752 | { | |
5753 | if (flag_code == CODE_64BIT | |
40fb9820 L |
5754 | && operand_type_check (i.types[op], disp)) |
5755 | { | |
5756 | i386_operand_type temp; | |
0dfbf9d7 | 5757 | operand_type_set (&temp, 0); |
40fb9820 L |
5758 | temp.bitfield.disp8 = i.types[op].bitfield.disp8; |
5759 | i.types[op] = temp; | |
5760 | if (i.prefix[ADDR_PREFIX] == 0) | |
5761 | i.types[op].bitfield.disp32s = 1; | |
5762 | else | |
5763 | i.types[op].bitfield.disp32 = 1; | |
5764 | } | |
20f0a1fc | 5765 | |
6c30d220 L |
5766 | if (!i.tm.opcode_modifier.vecsib) |
5767 | i.rm.regmem = i.base_reg->reg_num; | |
29b0f896 | 5768 | if ((i.base_reg->reg_flags & RegRex) != 0) |
161a04f6 | 5769 | i.rex |= REX_B; |
29b0f896 AM |
5770 | i.sib.base = i.base_reg->reg_num; |
5771 | /* x86-64 ignores REX prefix bit here to avoid decoder | |
5772 | complications. */ | |
848930b2 JB |
5773 | if (!(i.base_reg->reg_flags & RegRex) |
5774 | && (i.base_reg->reg_num == EBP_REG_NUM | |
5775 | || i.base_reg->reg_num == ESP_REG_NUM)) | |
29b0f896 | 5776 | default_seg = &ss; |
848930b2 | 5777 | if (i.base_reg->reg_num == 5 && i.disp_operands == 0) |
29b0f896 | 5778 | { |
848930b2 JB |
5779 | fake_zero_displacement = 1; |
5780 | i.types[op].bitfield.disp8 = 1; | |
29b0f896 AM |
5781 | } |
5782 | i.sib.scale = i.log2_scale_factor; | |
5783 | if (i.index_reg == 0) | |
5784 | { | |
6c30d220 | 5785 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
5786 | /* <disp>(%esp) becomes two byte modrm with no index |
5787 | register. We've already stored the code for esp | |
5788 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. | |
5789 | Any base register besides %esp will not use the | |
5790 | extra modrm byte. */ | |
5791 | i.sib.index = NO_INDEX_REGISTER; | |
29b0f896 | 5792 | } |
6c30d220 | 5793 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 5794 | { |
db51cc60 L |
5795 | if (i.index_reg->reg_num == RegEiz |
5796 | || i.index_reg->reg_num == RegRiz) | |
5797 | i.sib.index = NO_INDEX_REGISTER; | |
5798 | else | |
5799 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
5800 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
5801 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
161a04f6 | 5802 | i.rex |= REX_X; |
29b0f896 | 5803 | } |
67a4f2b7 AO |
5804 | |
5805 | if (i.disp_operands | |
5806 | && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL | |
5807 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) | |
5808 | i.rm.mode = 0; | |
5809 | else | |
a501d77e L |
5810 | { |
5811 | if (!fake_zero_displacement | |
5812 | && !i.disp_operands | |
5813 | && i.disp_encoding) | |
5814 | { | |
5815 | fake_zero_displacement = 1; | |
5816 | if (i.disp_encoding == disp_encoding_8bit) | |
5817 | i.types[op].bitfield.disp8 = 1; | |
5818 | else | |
5819 | i.types[op].bitfield.disp32 = 1; | |
5820 | } | |
5821 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
5822 | } | |
29b0f896 | 5823 | } |
252b5132 | 5824 | |
29b0f896 AM |
5825 | if (fake_zero_displacement) |
5826 | { | |
5827 | /* Fakes a zero displacement assuming that i.types[op] | |
5828 | holds the correct displacement size. */ | |
5829 | expressionS *exp; | |
5830 | ||
9c2799c2 | 5831 | gas_assert (i.op[op].disps == 0); |
29b0f896 AM |
5832 | exp = &disp_expressions[i.disp_operands++]; |
5833 | i.op[op].disps = exp; | |
5834 | exp->X_op = O_constant; | |
5835 | exp->X_add_number = 0; | |
5836 | exp->X_add_symbol = (symbolS *) 0; | |
5837 | exp->X_op_symbol = (symbolS *) 0; | |
5838 | } | |
c0f3af97 L |
5839 | |
5840 | mem = op; | |
29b0f896 | 5841 | } |
c0f3af97 L |
5842 | else |
5843 | mem = ~0; | |
252b5132 | 5844 | |
8c43a48b | 5845 | if (i.tm.opcode_modifier.vexsources == XOP2SOURCES) |
5dd85c99 SP |
5846 | { |
5847 | if (operand_type_check (i.types[0], imm)) | |
5848 | i.vex.register_specifier = NULL; | |
5849 | else | |
5850 | { | |
5851 | /* VEX.vvvv encodes one of the sources when the first | |
5852 | operand is not an immediate. */ | |
1ef99a7b | 5853 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
5854 | i.vex.register_specifier = i.op[0].regs; |
5855 | else | |
5856 | i.vex.register_specifier = i.op[1].regs; | |
5857 | } | |
5858 | ||
5859 | /* Destination is a XMM register encoded in the ModRM.reg | |
5860 | and VEX.R bit. */ | |
5861 | i.rm.reg = i.op[2].regs->reg_num; | |
5862 | if ((i.op[2].regs->reg_flags & RegRex) != 0) | |
5863 | i.rex |= REX_R; | |
5864 | ||
5865 | /* ModRM.rm and VEX.B encodes the other source. */ | |
5866 | if (!i.mem_operands) | |
5867 | { | |
5868 | i.rm.mode = 3; | |
5869 | ||
1ef99a7b | 5870 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
5871 | i.rm.regmem = i.op[1].regs->reg_num; |
5872 | else | |
5873 | i.rm.regmem = i.op[0].regs->reg_num; | |
5874 | ||
5875 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
5876 | i.rex |= REX_B; | |
5877 | } | |
5878 | } | |
2426c15f | 5879 | else if (i.tm.opcode_modifier.vexvvvv == VEXLWP) |
f88c9eb0 SP |
5880 | { |
5881 | i.vex.register_specifier = i.op[2].regs; | |
5882 | if (!i.mem_operands) | |
5883 | { | |
5884 | i.rm.mode = 3; | |
5885 | i.rm.regmem = i.op[1].regs->reg_num; | |
5886 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
5887 | i.rex |= REX_B; | |
5888 | } | |
5889 | } | |
29b0f896 AM |
5890 | /* Fill in i.rm.reg or i.rm.regmem field with register operand |
5891 | (if any) based on i.tm.extension_opcode. Again, we must be | |
5892 | careful to make sure that segment/control/debug/test/MMX | |
5893 | registers are coded into the i.rm.reg field. */ | |
f88c9eb0 | 5894 | else if (i.reg_operands) |
29b0f896 | 5895 | { |
99018f42 | 5896 | unsigned int op; |
7ab9ffdd L |
5897 | unsigned int vex_reg = ~0; |
5898 | ||
5899 | for (op = 0; op < i.operands; op++) | |
5900 | if (i.types[op].bitfield.reg8 | |
5901 | || i.types[op].bitfield.reg16 | |
5902 | || i.types[op].bitfield.reg32 | |
5903 | || i.types[op].bitfield.reg64 | |
5904 | || i.types[op].bitfield.regmmx | |
5905 | || i.types[op].bitfield.regxmm | |
5906 | || i.types[op].bitfield.regymm | |
5907 | || i.types[op].bitfield.sreg2 | |
5908 | || i.types[op].bitfield.sreg3 | |
5909 | || i.types[op].bitfield.control | |
5910 | || i.types[op].bitfield.debug | |
5911 | || i.types[op].bitfield.test) | |
5912 | break; | |
c0209578 | 5913 | |
7ab9ffdd L |
5914 | if (vex_3_sources) |
5915 | op = dest; | |
2426c15f | 5916 | else if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd L |
5917 | { |
5918 | /* For instructions with VexNDS, the register-only | |
5919 | source operand is encoded in VEX prefix. */ | |
5920 | gas_assert (mem != (unsigned int) ~0); | |
c0f3af97 | 5921 | |
7ab9ffdd | 5922 | if (op > mem) |
c0f3af97 | 5923 | { |
7ab9ffdd L |
5924 | vex_reg = op++; |
5925 | gas_assert (op < i.operands); | |
c0f3af97 L |
5926 | } |
5927 | else | |
c0f3af97 | 5928 | { |
f12dc422 L |
5929 | /* Check register-only source operand when two source |
5930 | operands are swapped. */ | |
5931 | if (!i.tm.operand_types[op].bitfield.baseindex | |
5932 | && i.tm.operand_types[op + 1].bitfield.baseindex) | |
5933 | { | |
5934 | vex_reg = op; | |
5935 | op += 2; | |
5936 | gas_assert (mem == (vex_reg + 1) | |
5937 | && op < i.operands); | |
5938 | } | |
5939 | else | |
5940 | { | |
5941 | vex_reg = op + 1; | |
5942 | gas_assert (vex_reg < i.operands); | |
5943 | } | |
c0f3af97 | 5944 | } |
7ab9ffdd | 5945 | } |
2426c15f | 5946 | else if (i.tm.opcode_modifier.vexvvvv == VEXNDD) |
7ab9ffdd | 5947 | { |
f12dc422 | 5948 | /* For instructions with VexNDD, the register destination |
7ab9ffdd | 5949 | is encoded in VEX prefix. */ |
f12dc422 L |
5950 | if (i.mem_operands == 0) |
5951 | { | |
5952 | /* There is no memory operand. */ | |
5953 | gas_assert ((op + 2) == i.operands); | |
5954 | vex_reg = op + 1; | |
5955 | } | |
5956 | else | |
8d63c93e | 5957 | { |
f12dc422 L |
5958 | /* There are only 2 operands. */ |
5959 | gas_assert (op < 2 && i.operands == 2); | |
5960 | vex_reg = 1; | |
5961 | } | |
7ab9ffdd L |
5962 | } |
5963 | else | |
5964 | gas_assert (op < i.operands); | |
99018f42 | 5965 | |
7ab9ffdd L |
5966 | if (vex_reg != (unsigned int) ~0) |
5967 | { | |
f12dc422 | 5968 | i386_operand_type *type = &i.tm.operand_types[vex_reg]; |
7ab9ffdd | 5969 | |
f12dc422 L |
5970 | if (type->bitfield.reg32 != 1 |
5971 | && type->bitfield.reg64 != 1 | |
5972 | && !operand_type_equal (type, ®xmm) | |
5973 | && !operand_type_equal (type, ®ymm)) | |
7ab9ffdd | 5974 | abort (); |
f88c9eb0 | 5975 | |
7ab9ffdd L |
5976 | i.vex.register_specifier = i.op[vex_reg].regs; |
5977 | } | |
5978 | ||
1b9f0c97 L |
5979 | /* Don't set OP operand twice. */ |
5980 | if (vex_reg != op) | |
7ab9ffdd | 5981 | { |
1b9f0c97 L |
5982 | /* If there is an extension opcode to put here, the |
5983 | register number must be put into the regmem field. */ | |
5984 | if (i.tm.extension_opcode != None) | |
5985 | { | |
5986 | i.rm.regmem = i.op[op].regs->reg_num; | |
5987 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
5988 | i.rex |= REX_B; | |
5989 | } | |
5990 | else | |
5991 | { | |
5992 | i.rm.reg = i.op[op].regs->reg_num; | |
5993 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
5994 | i.rex |= REX_R; | |
5995 | } | |
7ab9ffdd | 5996 | } |
252b5132 | 5997 | |
29b0f896 AM |
5998 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we |
5999 | must set it to 3 to indicate this is a register operand | |
6000 | in the regmem field. */ | |
6001 | if (!i.mem_operands) | |
6002 | i.rm.mode = 3; | |
6003 | } | |
252b5132 | 6004 | |
29b0f896 | 6005 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
c1e679ec | 6006 | if (i.tm.extension_opcode != None) |
29b0f896 AM |
6007 | i.rm.reg = i.tm.extension_opcode; |
6008 | } | |
6009 | return default_seg; | |
6010 | } | |
252b5132 | 6011 | |
29b0f896 | 6012 | static void |
e3bb37b5 | 6013 | output_branch (void) |
29b0f896 AM |
6014 | { |
6015 | char *p; | |
f8a5c266 | 6016 | int size; |
29b0f896 AM |
6017 | int code16; |
6018 | int prefix; | |
6019 | relax_substateT subtype; | |
6020 | symbolS *sym; | |
6021 | offsetT off; | |
6022 | ||
f8a5c266 | 6023 | code16 = flag_code == CODE_16BIT ? CODE16 : 0; |
a501d77e | 6024 | size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL; |
29b0f896 AM |
6025 | |
6026 | prefix = 0; | |
6027 | if (i.prefix[DATA_PREFIX] != 0) | |
252b5132 | 6028 | { |
29b0f896 AM |
6029 | prefix = 1; |
6030 | i.prefixes -= 1; | |
6031 | code16 ^= CODE16; | |
252b5132 | 6032 | } |
29b0f896 AM |
6033 | /* Pentium4 branch hints. */ |
6034 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
6035 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2f66722d | 6036 | { |
29b0f896 AM |
6037 | prefix++; |
6038 | i.prefixes--; | |
6039 | } | |
6040 | if (i.prefix[REX_PREFIX] != 0) | |
6041 | { | |
6042 | prefix++; | |
6043 | i.prefixes--; | |
2f66722d AM |
6044 | } |
6045 | ||
29b0f896 AM |
6046 | if (i.prefixes != 0 && !intel_syntax) |
6047 | as_warn (_("skipping prefixes on this instruction")); | |
6048 | ||
6049 | /* It's always a symbol; End frag & setup for relax. | |
6050 | Make sure there is enough room in this frag for the largest | |
6051 | instruction we may generate in md_convert_frag. This is 2 | |
6052 | bytes for the opcode and room for the prefix and largest | |
6053 | displacement. */ | |
6054 | frag_grow (prefix + 2 + 4); | |
6055 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
6056 | p = frag_more (prefix + 1); | |
6057 | if (i.prefix[DATA_PREFIX] != 0) | |
6058 | *p++ = DATA_PREFIX_OPCODE; | |
6059 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE | |
6060 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
6061 | *p++ = i.prefix[SEG_PREFIX]; | |
6062 | if (i.prefix[REX_PREFIX] != 0) | |
6063 | *p++ = i.prefix[REX_PREFIX]; | |
6064 | *p = i.tm.base_opcode; | |
6065 | ||
6066 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
f8a5c266 | 6067 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size); |
40fb9820 | 6068 | else if (cpu_arch_flags.bitfield.cpui386) |
f8a5c266 | 6069 | subtype = ENCODE_RELAX_STATE (COND_JUMP, size); |
29b0f896 | 6070 | else |
f8a5c266 | 6071 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, size); |
29b0f896 | 6072 | subtype |= code16; |
3e73aa7c | 6073 | |
29b0f896 AM |
6074 | sym = i.op[0].disps->X_add_symbol; |
6075 | off = i.op[0].disps->X_add_number; | |
3e73aa7c | 6076 | |
29b0f896 AM |
6077 | if (i.op[0].disps->X_op != O_constant |
6078 | && i.op[0].disps->X_op != O_symbol) | |
3e73aa7c | 6079 | { |
29b0f896 AM |
6080 | /* Handle complex expressions. */ |
6081 | sym = make_expr_symbol (i.op[0].disps); | |
6082 | off = 0; | |
6083 | } | |
3e73aa7c | 6084 | |
29b0f896 AM |
6085 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
6086 | Pass reloc in fr_var. */ | |
6087 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); | |
6088 | } | |
3e73aa7c | 6089 | |
29b0f896 | 6090 | static void |
e3bb37b5 | 6091 | output_jump (void) |
29b0f896 AM |
6092 | { |
6093 | char *p; | |
6094 | int size; | |
3e02c1cc | 6095 | fixS *fixP; |
29b0f896 | 6096 | |
40fb9820 | 6097 | if (i.tm.opcode_modifier.jumpbyte) |
29b0f896 AM |
6098 | { |
6099 | /* This is a loop or jecxz type instruction. */ | |
6100 | size = 1; | |
6101 | if (i.prefix[ADDR_PREFIX] != 0) | |
6102 | { | |
6103 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); | |
6104 | i.prefixes -= 1; | |
6105 | } | |
6106 | /* Pentium4 branch hints. */ | |
6107 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
6108 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
6109 | { | |
6110 | FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); | |
6111 | i.prefixes--; | |
3e73aa7c JH |
6112 | } |
6113 | } | |
29b0f896 AM |
6114 | else |
6115 | { | |
6116 | int code16; | |
3e73aa7c | 6117 | |
29b0f896 AM |
6118 | code16 = 0; |
6119 | if (flag_code == CODE_16BIT) | |
6120 | code16 = CODE16; | |
3e73aa7c | 6121 | |
29b0f896 AM |
6122 | if (i.prefix[DATA_PREFIX] != 0) |
6123 | { | |
6124 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); | |
6125 | i.prefixes -= 1; | |
6126 | code16 ^= CODE16; | |
6127 | } | |
252b5132 | 6128 | |
29b0f896 AM |
6129 | size = 4; |
6130 | if (code16) | |
6131 | size = 2; | |
6132 | } | |
9fcc94b6 | 6133 | |
29b0f896 AM |
6134 | if (i.prefix[REX_PREFIX] != 0) |
6135 | { | |
6136 | FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); | |
6137 | i.prefixes -= 1; | |
6138 | } | |
252b5132 | 6139 | |
29b0f896 AM |
6140 | if (i.prefixes != 0 && !intel_syntax) |
6141 | as_warn (_("skipping prefixes on this instruction")); | |
e0890092 | 6142 | |
42164a71 L |
6143 | p = frag_more (i.tm.opcode_length + size); |
6144 | switch (i.tm.opcode_length) | |
6145 | { | |
6146 | case 2: | |
6147 | *p++ = i.tm.base_opcode >> 8; | |
6148 | case 1: | |
6149 | *p++ = i.tm.base_opcode; | |
6150 | break; | |
6151 | default: | |
6152 | abort (); | |
6153 | } | |
e0890092 | 6154 | |
3e02c1cc AM |
6155 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
6156 | i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0])); | |
6157 | ||
6158 | /* All jumps handled here are signed, but don't use a signed limit | |
6159 | check for 32 and 16 bit jumps as we want to allow wrap around at | |
6160 | 4G and 64k respectively. */ | |
6161 | if (size == 1) | |
6162 | fixP->fx_signed = 1; | |
29b0f896 | 6163 | } |
e0890092 | 6164 | |
29b0f896 | 6165 | static void |
e3bb37b5 | 6166 | output_interseg_jump (void) |
29b0f896 AM |
6167 | { |
6168 | char *p; | |
6169 | int size; | |
6170 | int prefix; | |
6171 | int code16; | |
252b5132 | 6172 | |
29b0f896 AM |
6173 | code16 = 0; |
6174 | if (flag_code == CODE_16BIT) | |
6175 | code16 = CODE16; | |
a217f122 | 6176 | |
29b0f896 AM |
6177 | prefix = 0; |
6178 | if (i.prefix[DATA_PREFIX] != 0) | |
6179 | { | |
6180 | prefix = 1; | |
6181 | i.prefixes -= 1; | |
6182 | code16 ^= CODE16; | |
6183 | } | |
6184 | if (i.prefix[REX_PREFIX] != 0) | |
6185 | { | |
6186 | prefix++; | |
6187 | i.prefixes -= 1; | |
6188 | } | |
252b5132 | 6189 | |
29b0f896 AM |
6190 | size = 4; |
6191 | if (code16) | |
6192 | size = 2; | |
252b5132 | 6193 | |
29b0f896 AM |
6194 | if (i.prefixes != 0 && !intel_syntax) |
6195 | as_warn (_("skipping prefixes on this instruction")); | |
252b5132 | 6196 | |
29b0f896 AM |
6197 | /* 1 opcode; 2 segment; offset */ |
6198 | p = frag_more (prefix + 1 + 2 + size); | |
3e73aa7c | 6199 | |
29b0f896 AM |
6200 | if (i.prefix[DATA_PREFIX] != 0) |
6201 | *p++ = DATA_PREFIX_OPCODE; | |
252b5132 | 6202 | |
29b0f896 AM |
6203 | if (i.prefix[REX_PREFIX] != 0) |
6204 | *p++ = i.prefix[REX_PREFIX]; | |
252b5132 | 6205 | |
29b0f896 AM |
6206 | *p++ = i.tm.base_opcode; |
6207 | if (i.op[1].imms->X_op == O_constant) | |
6208 | { | |
6209 | offsetT n = i.op[1].imms->X_add_number; | |
252b5132 | 6210 | |
29b0f896 AM |
6211 | if (size == 2 |
6212 | && !fits_in_unsigned_word (n) | |
6213 | && !fits_in_signed_word (n)) | |
6214 | { | |
6215 | as_bad (_("16-bit jump out of range")); | |
6216 | return; | |
6217 | } | |
6218 | md_number_to_chars (p, n, size); | |
6219 | } | |
6220 | else | |
6221 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
6222 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); | |
6223 | if (i.op[0].imms->X_op != O_constant) | |
6224 | as_bad (_("can't handle non absolute segment in `%s'"), | |
6225 | i.tm.name); | |
6226 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); | |
6227 | } | |
a217f122 | 6228 | |
29b0f896 | 6229 | static void |
e3bb37b5 | 6230 | output_insn (void) |
29b0f896 | 6231 | { |
2bbd9c25 JJ |
6232 | fragS *insn_start_frag; |
6233 | offsetT insn_start_off; | |
6234 | ||
29b0f896 AM |
6235 | /* Tie dwarf2 debug info to the address at the start of the insn. |
6236 | We can't do this after the insn has been output as the current | |
6237 | frag may have been closed off. eg. by frag_var. */ | |
6238 | dwarf2_emit_insn (0); | |
6239 | ||
2bbd9c25 JJ |
6240 | insn_start_frag = frag_now; |
6241 | insn_start_off = frag_now_fix (); | |
6242 | ||
29b0f896 | 6243 | /* Output jumps. */ |
40fb9820 | 6244 | if (i.tm.opcode_modifier.jump) |
29b0f896 | 6245 | output_branch (); |
40fb9820 L |
6246 | else if (i.tm.opcode_modifier.jumpbyte |
6247 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 | 6248 | output_jump (); |
40fb9820 | 6249 | else if (i.tm.opcode_modifier.jumpintersegment) |
29b0f896 AM |
6250 | output_interseg_jump (); |
6251 | else | |
6252 | { | |
6253 | /* Output normal instructions here. */ | |
6254 | char *p; | |
6255 | unsigned char *q; | |
47465058 | 6256 | unsigned int j; |
331d2d0d | 6257 | unsigned int prefix; |
4dffcebc | 6258 | |
c0f3af97 | 6259 | /* Since the VEX prefix contains the implicit prefix, we don't |
89e71f5c | 6260 | need the explicit prefix. */ |
c0f3af97 | 6261 | if (!i.tm.opcode_modifier.vex) |
bc4bd9ab | 6262 | { |
c0f3af97 | 6263 | switch (i.tm.opcode_length) |
bc4bd9ab | 6264 | { |
c0f3af97 L |
6265 | case 3: |
6266 | if (i.tm.base_opcode & 0xff000000) | |
4dffcebc | 6267 | { |
c0f3af97 L |
6268 | prefix = (i.tm.base_opcode >> 24) & 0xff; |
6269 | goto check_prefix; | |
6270 | } | |
6271 | break; | |
6272 | case 2: | |
6273 | if ((i.tm.base_opcode & 0xff0000) != 0) | |
6274 | { | |
6275 | prefix = (i.tm.base_opcode >> 16) & 0xff; | |
6276 | if (i.tm.cpu_flags.bitfield.cpupadlock) | |
6277 | { | |
4dffcebc | 6278 | check_prefix: |
c0f3af97 | 6279 | if (prefix != REPE_PREFIX_OPCODE |
c32fa91d | 6280 | || (i.prefix[REP_PREFIX] |
c0f3af97 L |
6281 | != REPE_PREFIX_OPCODE)) |
6282 | add_prefix (prefix); | |
6283 | } | |
6284 | else | |
4dffcebc L |
6285 | add_prefix (prefix); |
6286 | } | |
c0f3af97 L |
6287 | break; |
6288 | case 1: | |
6289 | break; | |
6290 | default: | |
6291 | abort (); | |
bc4bd9ab | 6292 | } |
c0f3af97 L |
6293 | |
6294 | /* The prefix bytes. */ | |
6295 | for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) | |
6296 | if (*q) | |
6297 | FRAG_APPEND_1_CHAR (*q); | |
0f10071e | 6298 | } |
ae5c1c7b | 6299 | else |
c0f3af97 L |
6300 | { |
6301 | for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++) | |
6302 | if (*q) | |
6303 | switch (j) | |
6304 | { | |
6305 | case REX_PREFIX: | |
6306 | /* REX byte is encoded in VEX prefix. */ | |
6307 | break; | |
6308 | case SEG_PREFIX: | |
6309 | case ADDR_PREFIX: | |
6310 | FRAG_APPEND_1_CHAR (*q); | |
6311 | break; | |
6312 | default: | |
6313 | /* There should be no other prefixes for instructions | |
6314 | with VEX prefix. */ | |
6315 | abort (); | |
6316 | } | |
6317 | ||
6318 | /* Now the VEX prefix. */ | |
6319 | p = frag_more (i.vex.length); | |
6320 | for (j = 0; j < i.vex.length; j++) | |
6321 | p[j] = i.vex.bytes[j]; | |
6322 | } | |
252b5132 | 6323 | |
29b0f896 | 6324 | /* Now the opcode; be careful about word order here! */ |
4dffcebc | 6325 | if (i.tm.opcode_length == 1) |
29b0f896 AM |
6326 | { |
6327 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
6328 | } | |
6329 | else | |
6330 | { | |
4dffcebc | 6331 | switch (i.tm.opcode_length) |
331d2d0d | 6332 | { |
4dffcebc | 6333 | case 3: |
331d2d0d L |
6334 | p = frag_more (3); |
6335 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
4dffcebc L |
6336 | break; |
6337 | case 2: | |
6338 | p = frag_more (2); | |
6339 | break; | |
6340 | default: | |
6341 | abort (); | |
6342 | break; | |
331d2d0d | 6343 | } |
0f10071e | 6344 | |
29b0f896 AM |
6345 | /* Put out high byte first: can't use md_number_to_chars! */ |
6346 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
6347 | *p = i.tm.base_opcode & 0xff; | |
6348 | } | |
3e73aa7c | 6349 | |
29b0f896 | 6350 | /* Now the modrm byte and sib byte (if present). */ |
40fb9820 | 6351 | if (i.tm.opcode_modifier.modrm) |
29b0f896 | 6352 | { |
4a3523fa L |
6353 | FRAG_APPEND_1_CHAR ((i.rm.regmem << 0 |
6354 | | i.rm.reg << 3 | |
6355 | | i.rm.mode << 6)); | |
29b0f896 AM |
6356 | /* If i.rm.regmem == ESP (4) |
6357 | && i.rm.mode != (Register mode) | |
6358 | && not 16 bit | |
6359 | ==> need second modrm byte. */ | |
6360 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
6361 | && i.rm.mode != 3 | |
40fb9820 | 6362 | && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16)) |
4a3523fa L |
6363 | FRAG_APPEND_1_CHAR ((i.sib.base << 0 |
6364 | | i.sib.index << 3 | |
6365 | | i.sib.scale << 6)); | |
29b0f896 | 6366 | } |
3e73aa7c | 6367 | |
29b0f896 | 6368 | if (i.disp_operands) |
2bbd9c25 | 6369 | output_disp (insn_start_frag, insn_start_off); |
3e73aa7c | 6370 | |
29b0f896 | 6371 | if (i.imm_operands) |
2bbd9c25 | 6372 | output_imm (insn_start_frag, insn_start_off); |
29b0f896 | 6373 | } |
252b5132 | 6374 | |
29b0f896 AM |
6375 | #ifdef DEBUG386 |
6376 | if (flag_debug) | |
6377 | { | |
7b81dfbb | 6378 | pi ("" /*line*/, &i); |
29b0f896 AM |
6379 | } |
6380 | #endif /* DEBUG386 */ | |
6381 | } | |
252b5132 | 6382 | |
e205caa7 L |
6383 | /* Return the size of the displacement operand N. */ |
6384 | ||
6385 | static int | |
6386 | disp_size (unsigned int n) | |
6387 | { | |
6388 | int size = 4; | |
40fb9820 L |
6389 | if (i.types[n].bitfield.disp64) |
6390 | size = 8; | |
6391 | else if (i.types[n].bitfield.disp8) | |
6392 | size = 1; | |
6393 | else if (i.types[n].bitfield.disp16) | |
6394 | size = 2; | |
e205caa7 L |
6395 | return size; |
6396 | } | |
6397 | ||
6398 | /* Return the size of the immediate operand N. */ | |
6399 | ||
6400 | static int | |
6401 | imm_size (unsigned int n) | |
6402 | { | |
6403 | int size = 4; | |
40fb9820 L |
6404 | if (i.types[n].bitfield.imm64) |
6405 | size = 8; | |
6406 | else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) | |
6407 | size = 1; | |
6408 | else if (i.types[n].bitfield.imm16) | |
6409 | size = 2; | |
e205caa7 L |
6410 | return size; |
6411 | } | |
6412 | ||
29b0f896 | 6413 | static void |
64e74474 | 6414 | output_disp (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
6415 | { |
6416 | char *p; | |
6417 | unsigned int n; | |
252b5132 | 6418 | |
29b0f896 AM |
6419 | for (n = 0; n < i.operands; n++) |
6420 | { | |
40fb9820 | 6421 | if (operand_type_check (i.types[n], disp)) |
29b0f896 AM |
6422 | { |
6423 | if (i.op[n].disps->X_op == O_constant) | |
6424 | { | |
e205caa7 | 6425 | int size = disp_size (n); |
29b0f896 | 6426 | offsetT val; |
252b5132 | 6427 | |
29b0f896 AM |
6428 | val = offset_in_range (i.op[n].disps->X_add_number, |
6429 | size); | |
6430 | p = frag_more (size); | |
6431 | md_number_to_chars (p, val, size); | |
6432 | } | |
6433 | else | |
6434 | { | |
f86103b7 | 6435 | enum bfd_reloc_code_real reloc_type; |
e205caa7 | 6436 | int size = disp_size (n); |
40fb9820 | 6437 | int sign = i.types[n].bitfield.disp32s; |
29b0f896 AM |
6438 | int pcrel = (i.flags[n] & Operand_PCrel) != 0; |
6439 | ||
e205caa7 | 6440 | /* We can't have 8 bit displacement here. */ |
9c2799c2 | 6441 | gas_assert (!i.types[n].bitfield.disp8); |
e205caa7 | 6442 | |
29b0f896 AM |
6443 | /* The PC relative address is computed relative |
6444 | to the instruction boundary, so in case immediate | |
6445 | fields follows, we need to adjust the value. */ | |
6446 | if (pcrel && i.imm_operands) | |
6447 | { | |
29b0f896 | 6448 | unsigned int n1; |
e205caa7 | 6449 | int sz = 0; |
252b5132 | 6450 | |
29b0f896 | 6451 | for (n1 = 0; n1 < i.operands; n1++) |
40fb9820 | 6452 | if (operand_type_check (i.types[n1], imm)) |
252b5132 | 6453 | { |
e205caa7 L |
6454 | /* Only one immediate is allowed for PC |
6455 | relative address. */ | |
9c2799c2 | 6456 | gas_assert (sz == 0); |
e205caa7 L |
6457 | sz = imm_size (n1); |
6458 | i.op[n].disps->X_add_number -= sz; | |
252b5132 | 6459 | } |
29b0f896 | 6460 | /* We should find the immediate. */ |
9c2799c2 | 6461 | gas_assert (sz != 0); |
29b0f896 | 6462 | } |
520dc8e8 | 6463 | |
29b0f896 | 6464 | p = frag_more (size); |
2bbd9c25 | 6465 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
d6ab8113 | 6466 | if (GOT_symbol |
2bbd9c25 | 6467 | && GOT_symbol == i.op[n].disps->X_add_symbol |
d6ab8113 | 6468 | && (((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
6469 | || reloc_type == BFD_RELOC_X86_64_32S |
6470 | || (reloc_type == BFD_RELOC_64 | |
6471 | && object_64bit)) | |
d6ab8113 JB |
6472 | && (i.op[n].disps->X_op == O_symbol |
6473 | || (i.op[n].disps->X_op == O_add | |
6474 | && ((symbol_get_value_expression | |
6475 | (i.op[n].disps->X_op_symbol)->X_op) | |
6476 | == O_subtract)))) | |
6477 | || reloc_type == BFD_RELOC_32_PCREL)) | |
2bbd9c25 JJ |
6478 | { |
6479 | offsetT add; | |
6480 | ||
6481 | if (insn_start_frag == frag_now) | |
6482 | add = (p - frag_now->fr_literal) - insn_start_off; | |
6483 | else | |
6484 | { | |
6485 | fragS *fr; | |
6486 | ||
6487 | add = insn_start_frag->fr_fix - insn_start_off; | |
6488 | for (fr = insn_start_frag->fr_next; | |
6489 | fr && fr != frag_now; fr = fr->fr_next) | |
6490 | add += fr->fr_fix; | |
6491 | add += p - frag_now->fr_literal; | |
6492 | } | |
6493 | ||
4fa24527 | 6494 | if (!object_64bit) |
7b81dfbb AJ |
6495 | { |
6496 | reloc_type = BFD_RELOC_386_GOTPC; | |
6497 | i.op[n].imms->X_add_number += add; | |
6498 | } | |
6499 | else if (reloc_type == BFD_RELOC_64) | |
6500 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
d6ab8113 | 6501 | else |
7b81dfbb AJ |
6502 | /* Don't do the adjustment for x86-64, as there |
6503 | the pcrel addressing is relative to the _next_ | |
6504 | insn, and that is taken care of in other code. */ | |
d6ab8113 | 6505 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
2bbd9c25 | 6506 | } |
062cd5e7 | 6507 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
2bbd9c25 | 6508 | i.op[n].disps, pcrel, reloc_type); |
29b0f896 AM |
6509 | } |
6510 | } | |
6511 | } | |
6512 | } | |
252b5132 | 6513 | |
29b0f896 | 6514 | static void |
64e74474 | 6515 | output_imm (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
6516 | { |
6517 | char *p; | |
6518 | unsigned int n; | |
252b5132 | 6519 | |
29b0f896 AM |
6520 | for (n = 0; n < i.operands; n++) |
6521 | { | |
40fb9820 | 6522 | if (operand_type_check (i.types[n], imm)) |
29b0f896 AM |
6523 | { |
6524 | if (i.op[n].imms->X_op == O_constant) | |
6525 | { | |
e205caa7 | 6526 | int size = imm_size (n); |
29b0f896 | 6527 | offsetT val; |
b4cac588 | 6528 | |
29b0f896 AM |
6529 | val = offset_in_range (i.op[n].imms->X_add_number, |
6530 | size); | |
6531 | p = frag_more (size); | |
6532 | md_number_to_chars (p, val, size); | |
6533 | } | |
6534 | else | |
6535 | { | |
6536 | /* Not absolute_section. | |
6537 | Need a 32-bit fixup (don't support 8bit | |
6538 | non-absolute imms). Try to support other | |
6539 | sizes ... */ | |
f86103b7 | 6540 | enum bfd_reloc_code_real reloc_type; |
e205caa7 L |
6541 | int size = imm_size (n); |
6542 | int sign; | |
29b0f896 | 6543 | |
40fb9820 | 6544 | if (i.types[n].bitfield.imm32s |
a7d61044 | 6545 | && (i.suffix == QWORD_MNEM_SUFFIX |
40fb9820 | 6546 | || (!i.suffix && i.tm.opcode_modifier.no_lsuf))) |
29b0f896 | 6547 | sign = 1; |
e205caa7 L |
6548 | else |
6549 | sign = 0; | |
520dc8e8 | 6550 | |
29b0f896 AM |
6551 | p = frag_more (size); |
6552 | reloc_type = reloc (size, 0, sign, i.reloc[n]); | |
f86103b7 | 6553 | |
2bbd9c25 JJ |
6554 | /* This is tough to explain. We end up with this one if we |
6555 | * have operands that look like | |
6556 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to | |
6557 | * obtain the absolute address of the GOT, and it is strongly | |
6558 | * preferable from a performance point of view to avoid using | |
6559 | * a runtime relocation for this. The actual sequence of | |
6560 | * instructions often look something like: | |
6561 | * | |
6562 | * call .L66 | |
6563 | * .L66: | |
6564 | * popl %ebx | |
6565 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
6566 | * | |
6567 | * The call and pop essentially return the absolute address | |
6568 | * of the label .L66 and store it in %ebx. The linker itself | |
6569 | * will ultimately change the first operand of the addl so | |
6570 | * that %ebx points to the GOT, but to keep things simple, the | |
6571 | * .o file must have this operand set so that it generates not | |
6572 | * the absolute address of .L66, but the absolute address of | |
6573 | * itself. This allows the linker itself simply treat a GOTPC | |
6574 | * relocation as asking for a pcrel offset to the GOT to be | |
6575 | * added in, and the addend of the relocation is stored in the | |
6576 | * operand field for the instruction itself. | |
6577 | * | |
6578 | * Our job here is to fix the operand so that it would add | |
6579 | * the correct offset so that %ebx would point to itself. The | |
6580 | * thing that is tricky is that .-.L66 will point to the | |
6581 | * beginning of the instruction, so we need to further modify | |
6582 | * the operand so that it will point to itself. There are | |
6583 | * other cases where you have something like: | |
6584 | * | |
6585 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
6586 | * | |
6587 | * and here no correction would be required. Internally in | |
6588 | * the assembler we treat operands of this form as not being | |
6589 | * pcrel since the '.' is explicitly mentioned, and I wonder | |
6590 | * whether it would simplify matters to do it this way. Who | |
6591 | * knows. In earlier versions of the PIC patches, the | |
6592 | * pcrel_adjust field was used to store the correction, but | |
6593 | * since the expression is not pcrel, I felt it would be | |
6594 | * confusing to do it this way. */ | |
6595 | ||
d6ab8113 | 6596 | if ((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
6597 | || reloc_type == BFD_RELOC_X86_64_32S |
6598 | || reloc_type == BFD_RELOC_64) | |
29b0f896 AM |
6599 | && GOT_symbol |
6600 | && GOT_symbol == i.op[n].imms->X_add_symbol | |
6601 | && (i.op[n].imms->X_op == O_symbol | |
6602 | || (i.op[n].imms->X_op == O_add | |
6603 | && ((symbol_get_value_expression | |
6604 | (i.op[n].imms->X_op_symbol)->X_op) | |
6605 | == O_subtract)))) | |
6606 | { | |
2bbd9c25 JJ |
6607 | offsetT add; |
6608 | ||
6609 | if (insn_start_frag == frag_now) | |
6610 | add = (p - frag_now->fr_literal) - insn_start_off; | |
6611 | else | |
6612 | { | |
6613 | fragS *fr; | |
6614 | ||
6615 | add = insn_start_frag->fr_fix - insn_start_off; | |
6616 | for (fr = insn_start_frag->fr_next; | |
6617 | fr && fr != frag_now; fr = fr->fr_next) | |
6618 | add += fr->fr_fix; | |
6619 | add += p - frag_now->fr_literal; | |
6620 | } | |
6621 | ||
4fa24527 | 6622 | if (!object_64bit) |
d6ab8113 | 6623 | reloc_type = BFD_RELOC_386_GOTPC; |
7b81dfbb | 6624 | else if (size == 4) |
d6ab8113 | 6625 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
7b81dfbb AJ |
6626 | else if (size == 8) |
6627 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
2bbd9c25 | 6628 | i.op[n].imms->X_add_number += add; |
29b0f896 | 6629 | } |
29b0f896 AM |
6630 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
6631 | i.op[n].imms, 0, reloc_type); | |
6632 | } | |
6633 | } | |
6634 | } | |
252b5132 RH |
6635 | } |
6636 | \f | |
d182319b JB |
6637 | /* x86_cons_fix_new is called via the expression parsing code when a |
6638 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
6639 | static enum bfd_reloc_code_real got_reloc = NO_RELOC; | |
6640 | static int cons_sign = -1; | |
6641 | ||
6642 | void | |
e3bb37b5 | 6643 | x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, |
64e74474 | 6644 | expressionS *exp) |
d182319b JB |
6645 | { |
6646 | enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc); | |
6647 | ||
6648 | got_reloc = NO_RELOC; | |
6649 | ||
6650 | #ifdef TE_PE | |
6651 | if (exp->X_op == O_secrel) | |
6652 | { | |
6653 | exp->X_op = O_symbol; | |
6654 | r = BFD_RELOC_32_SECREL; | |
6655 | } | |
6656 | #endif | |
6657 | ||
6658 | fix_new_exp (frag, off, len, exp, 0, r); | |
6659 | } | |
6660 | ||
357d1bd8 L |
6661 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
6662 | purpose of the `.dc.a' internal pseudo-op. */ | |
6663 | ||
6664 | int | |
6665 | x86_address_bytes (void) | |
6666 | { | |
6667 | if ((stdoutput->arch_info->mach & bfd_mach_x64_32)) | |
6668 | return 4; | |
6669 | return stdoutput->arch_info->bits_per_address / 8; | |
6670 | } | |
6671 | ||
d382c579 TG |
6672 | #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \ |
6673 | || defined (LEX_AT) | |
718ddfc0 JB |
6674 | # define lex_got(reloc, adjust, types) NULL |
6675 | #else | |
f3c180ae AM |
6676 | /* Parse operands of the form |
6677 | <symbol>@GOTOFF+<nnn> | |
6678 | and similar .plt or .got references. | |
6679 | ||
6680 | If we find one, set up the correct relocation in RELOC and copy the | |
6681 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
6682 | parsing by the calling routine. Return this buffer, and if ADJUST | |
6683 | is non-null set it to the length of the string we removed from the | |
6684 | input line. Otherwise return NULL. */ | |
6685 | static char * | |
91d6fa6a | 6686 | lex_got (enum bfd_reloc_code_real *rel, |
64e74474 | 6687 | int *adjust, |
40fb9820 | 6688 | i386_operand_type *types) |
f3c180ae | 6689 | { |
7b81dfbb AJ |
6690 | /* Some of the relocations depend on the size of what field is to |
6691 | be relocated. But in our callers i386_immediate and i386_displacement | |
6692 | we don't yet know the operand size (this will be set by insn | |
6693 | matching). Hence we record the word32 relocation here, | |
6694 | and adjust the reloc according to the real size in reloc(). */ | |
f3c180ae AM |
6695 | static const struct { |
6696 | const char *str; | |
cff8d58a | 6697 | int len; |
4fa24527 | 6698 | const enum bfd_reloc_code_real rel[2]; |
40fb9820 | 6699 | const i386_operand_type types64; |
f3c180ae | 6700 | } gotrel[] = { |
cff8d58a L |
6701 | { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real, |
6702 | BFD_RELOC_X86_64_PLTOFF64 }, | |
40fb9820 | 6703 | OPERAND_TYPE_IMM64 }, |
cff8d58a L |
6704 | { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32, |
6705 | BFD_RELOC_X86_64_PLT32 }, | |
40fb9820 | 6706 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
6707 | { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real, |
6708 | BFD_RELOC_X86_64_GOTPLT64 }, | |
40fb9820 | 6709 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
6710 | { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF, |
6711 | BFD_RELOC_X86_64_GOTOFF64 }, | |
40fb9820 | 6712 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
6713 | { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real, |
6714 | BFD_RELOC_X86_64_GOTPCREL }, | |
40fb9820 | 6715 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
6716 | { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD, |
6717 | BFD_RELOC_X86_64_TLSGD }, | |
40fb9820 | 6718 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
6719 | { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM, |
6720 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 6721 | OPERAND_TYPE_NONE }, |
cff8d58a L |
6722 | { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real, |
6723 | BFD_RELOC_X86_64_TLSLD }, | |
40fb9820 | 6724 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
6725 | { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32, |
6726 | BFD_RELOC_X86_64_GOTTPOFF }, | |
40fb9820 | 6727 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
6728 | { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32, |
6729 | BFD_RELOC_X86_64_TPOFF32 }, | |
40fb9820 | 6730 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
6731 | { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE, |
6732 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 6733 | OPERAND_TYPE_NONE }, |
cff8d58a L |
6734 | { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32, |
6735 | BFD_RELOC_X86_64_DTPOFF32 }, | |
40fb9820 | 6736 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
6737 | { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE, |
6738 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 6739 | OPERAND_TYPE_NONE }, |
cff8d58a L |
6740 | { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE, |
6741 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 6742 | OPERAND_TYPE_NONE }, |
cff8d58a L |
6743 | { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32, |
6744 | BFD_RELOC_X86_64_GOT32 }, | |
40fb9820 | 6745 | OPERAND_TYPE_IMM32_32S_64_DISP32 }, |
cff8d58a L |
6746 | { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC, |
6747 | BFD_RELOC_X86_64_GOTPC32_TLSDESC }, | |
40fb9820 | 6748 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
6749 | { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL, |
6750 | BFD_RELOC_X86_64_TLSDESC_CALL }, | |
40fb9820 | 6751 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
f3c180ae AM |
6752 | }; |
6753 | char *cp; | |
6754 | unsigned int j; | |
6755 | ||
d382c579 | 6756 | #if defined (OBJ_MAYBE_ELF) |
718ddfc0 JB |
6757 | if (!IS_ELF) |
6758 | return NULL; | |
d382c579 | 6759 | #endif |
718ddfc0 | 6760 | |
f3c180ae | 6761 | for (cp = input_line_pointer; *cp != '@'; cp++) |
67c11a9b | 6762 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') |
f3c180ae AM |
6763 | return NULL; |
6764 | ||
47465058 | 6765 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) |
f3c180ae | 6766 | { |
cff8d58a | 6767 | int len = gotrel[j].len; |
28f81592 | 6768 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae | 6769 | { |
4fa24527 | 6770 | if (gotrel[j].rel[object_64bit] != 0) |
f3c180ae | 6771 | { |
28f81592 AM |
6772 | int first, second; |
6773 | char *tmpbuf, *past_reloc; | |
f3c180ae | 6774 | |
91d6fa6a | 6775 | *rel = gotrel[j].rel[object_64bit]; |
28f81592 AM |
6776 | if (adjust) |
6777 | *adjust = len; | |
f3c180ae | 6778 | |
3956db08 JB |
6779 | if (types) |
6780 | { | |
6781 | if (flag_code != CODE_64BIT) | |
40fb9820 L |
6782 | { |
6783 | types->bitfield.imm32 = 1; | |
6784 | types->bitfield.disp32 = 1; | |
6785 | } | |
3956db08 JB |
6786 | else |
6787 | *types = gotrel[j].types64; | |
6788 | } | |
6789 | ||
f3c180ae AM |
6790 | if (GOT_symbol == NULL) |
6791 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); | |
6792 | ||
28f81592 | 6793 | /* The length of the first part of our input line. */ |
f3c180ae | 6794 | first = cp - input_line_pointer; |
28f81592 AM |
6795 | |
6796 | /* The second part goes from after the reloc token until | |
67c11a9b | 6797 | (and including) an end_of_line char or comma. */ |
28f81592 | 6798 | past_reloc = cp + 1 + len; |
67c11a9b AM |
6799 | cp = past_reloc; |
6800 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
6801 | ++cp; | |
6802 | second = cp + 1 - past_reloc; | |
28f81592 AM |
6803 | |
6804 | /* Allocate and copy string. The trailing NUL shouldn't | |
6805 | be necessary, but be safe. */ | |
1e9cc1c2 | 6806 | tmpbuf = (char *) xmalloc (first + second + 2); |
f3c180ae | 6807 | memcpy (tmpbuf, input_line_pointer, first); |
0787a12d AM |
6808 | if (second != 0 && *past_reloc != ' ') |
6809 | /* Replace the relocation token with ' ', so that | |
6810 | errors like foo@GOTOFF1 will be detected. */ | |
6811 | tmpbuf[first++] = ' '; | |
6812 | memcpy (tmpbuf + first, past_reloc, second); | |
6813 | tmpbuf[first + second] = '\0'; | |
f3c180ae AM |
6814 | return tmpbuf; |
6815 | } | |
6816 | ||
4fa24527 JB |
6817 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
6818 | gotrel[j].str, 1 << (5 + object_64bit)); | |
f3c180ae AM |
6819 | return NULL; |
6820 | } | |
6821 | } | |
6822 | ||
6823 | /* Might be a symbol version string. Don't as_bad here. */ | |
6824 | return NULL; | |
6825 | } | |
4e4f7c87 | 6826 | #endif |
f3c180ae | 6827 | |
a988325c NC |
6828 | #ifdef TE_PE |
6829 | #ifdef lex_got | |
6830 | #undef lex_got | |
6831 | #endif | |
6832 | /* Parse operands of the form | |
6833 | <symbol>@SECREL32+<nnn> | |
6834 | ||
6835 | If we find one, set up the correct relocation in RELOC and copy the | |
6836 | input string, minus the `@SECREL32' into a malloc'd buffer for | |
6837 | parsing by the calling routine. Return this buffer, and if ADJUST | |
6838 | is non-null set it to the length of the string we removed from the | |
6839 | input line. Otherwise return NULL. | |
6840 | ||
6841 | This function is copied from the ELF version above adjusted for PE targets. */ | |
6842 | ||
6843 | static char * | |
6844 | lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED, | |
6845 | int *adjust ATTRIBUTE_UNUSED, | |
6846 | i386_operand_type *types ATTRIBUTE_UNUSED) | |
6847 | { | |
6848 | static const struct | |
6849 | { | |
6850 | const char *str; | |
6851 | int len; | |
6852 | const enum bfd_reloc_code_real rel[2]; | |
6853 | const i386_operand_type types64; | |
6854 | } | |
6855 | gotrel[] = | |
6856 | { | |
6857 | { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL, | |
6858 | BFD_RELOC_32_SECREL }, | |
6859 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, | |
6860 | }; | |
6861 | ||
6862 | char *cp; | |
6863 | unsigned j; | |
6864 | ||
6865 | for (cp = input_line_pointer; *cp != '@'; cp++) | |
6866 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') | |
6867 | return NULL; | |
6868 | ||
6869 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) | |
6870 | { | |
6871 | int len = gotrel[j].len; | |
6872 | ||
6873 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) | |
6874 | { | |
6875 | if (gotrel[j].rel[object_64bit] != 0) | |
6876 | { | |
6877 | int first, second; | |
6878 | char *tmpbuf, *past_reloc; | |
6879 | ||
6880 | *rel = gotrel[j].rel[object_64bit]; | |
6881 | if (adjust) | |
6882 | *adjust = len; | |
6883 | ||
6884 | if (types) | |
6885 | { | |
6886 | if (flag_code != CODE_64BIT) | |
6887 | { | |
6888 | types->bitfield.imm32 = 1; | |
6889 | types->bitfield.disp32 = 1; | |
6890 | } | |
6891 | else | |
6892 | *types = gotrel[j].types64; | |
6893 | } | |
6894 | ||
6895 | /* The length of the first part of our input line. */ | |
6896 | first = cp - input_line_pointer; | |
6897 | ||
6898 | /* The second part goes from after the reloc token until | |
6899 | (and including) an end_of_line char or comma. */ | |
6900 | past_reloc = cp + 1 + len; | |
6901 | cp = past_reloc; | |
6902 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
6903 | ++cp; | |
6904 | second = cp + 1 - past_reloc; | |
6905 | ||
6906 | /* Allocate and copy string. The trailing NUL shouldn't | |
6907 | be necessary, but be safe. */ | |
6908 | tmpbuf = (char *) xmalloc (first + second + 2); | |
6909 | memcpy (tmpbuf, input_line_pointer, first); | |
6910 | if (second != 0 && *past_reloc != ' ') | |
6911 | /* Replace the relocation token with ' ', so that | |
6912 | errors like foo@SECLREL321 will be detected. */ | |
6913 | tmpbuf[first++] = ' '; | |
6914 | memcpy (tmpbuf + first, past_reloc, second); | |
6915 | tmpbuf[first + second] = '\0'; | |
6916 | return tmpbuf; | |
6917 | } | |
6918 | ||
6919 | as_bad (_("@%s reloc is not supported with %d-bit output format"), | |
6920 | gotrel[j].str, 1 << (5 + object_64bit)); | |
6921 | return NULL; | |
6922 | } | |
6923 | } | |
6924 | ||
6925 | /* Might be a symbol version string. Don't as_bad here. */ | |
6926 | return NULL; | |
6927 | } | |
6928 | ||
6929 | #endif /* TE_PE */ | |
6930 | ||
f3c180ae | 6931 | void |
e3bb37b5 | 6932 | x86_cons (expressionS *exp, int size) |
f3c180ae | 6933 | { |
ee86248c JB |
6934 | intel_syntax = -intel_syntax; |
6935 | ||
3c7b9c2c | 6936 | exp->X_md = 0; |
4fa24527 | 6937 | if (size == 4 || (object_64bit && size == 8)) |
f3c180ae AM |
6938 | { |
6939 | /* Handle @GOTOFF and the like in an expression. */ | |
6940 | char *save; | |
6941 | char *gotfree_input_line; | |
4a57f2cf | 6942 | int adjust = 0; |
f3c180ae AM |
6943 | |
6944 | save = input_line_pointer; | |
3956db08 | 6945 | gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); |
f3c180ae AM |
6946 | if (gotfree_input_line) |
6947 | input_line_pointer = gotfree_input_line; | |
6948 | ||
6949 | expression (exp); | |
6950 | ||
6951 | if (gotfree_input_line) | |
6952 | { | |
6953 | /* expression () has merrily parsed up to the end of line, | |
6954 | or a comma - in the wrong buffer. Transfer how far | |
6955 | input_line_pointer has moved to the right buffer. */ | |
6956 | input_line_pointer = (save | |
6957 | + (input_line_pointer - gotfree_input_line) | |
6958 | + adjust); | |
6959 | free (gotfree_input_line); | |
3992d3b7 AM |
6960 | if (exp->X_op == O_constant |
6961 | || exp->X_op == O_absent | |
6962 | || exp->X_op == O_illegal | |
0398aac5 | 6963 | || exp->X_op == O_register |
3992d3b7 AM |
6964 | || exp->X_op == O_big) |
6965 | { | |
6966 | char c = *input_line_pointer; | |
6967 | *input_line_pointer = 0; | |
6968 | as_bad (_("missing or invalid expression `%s'"), save); | |
6969 | *input_line_pointer = c; | |
6970 | } | |
f3c180ae AM |
6971 | } |
6972 | } | |
6973 | else | |
6974 | expression (exp); | |
ee86248c JB |
6975 | |
6976 | intel_syntax = -intel_syntax; | |
6977 | ||
6978 | if (intel_syntax) | |
6979 | i386_intel_simplify (exp); | |
f3c180ae | 6980 | } |
f3c180ae | 6981 | |
9f32dd5b L |
6982 | static void |
6983 | signed_cons (int size) | |
6482c264 | 6984 | { |
d182319b JB |
6985 | if (flag_code == CODE_64BIT) |
6986 | cons_sign = 1; | |
6987 | cons (size); | |
6988 | cons_sign = -1; | |
6482c264 NC |
6989 | } |
6990 | ||
d182319b | 6991 | #ifdef TE_PE |
6482c264 | 6992 | static void |
7016a5d5 | 6993 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
6482c264 NC |
6994 | { |
6995 | expressionS exp; | |
6996 | ||
6997 | do | |
6998 | { | |
6999 | expression (&exp); | |
7000 | if (exp.X_op == O_symbol) | |
7001 | exp.X_op = O_secrel; | |
7002 | ||
7003 | emit_expr (&exp, 4); | |
7004 | } | |
7005 | while (*input_line_pointer++ == ','); | |
7006 | ||
7007 | input_line_pointer--; | |
7008 | demand_empty_rest_of_line (); | |
7009 | } | |
6482c264 NC |
7010 | #endif |
7011 | ||
252b5132 | 7012 | static int |
70e41ade | 7013 | i386_immediate (char *imm_start) |
252b5132 RH |
7014 | { |
7015 | char *save_input_line_pointer; | |
f3c180ae | 7016 | char *gotfree_input_line; |
252b5132 | 7017 | segT exp_seg = 0; |
47926f60 | 7018 | expressionS *exp; |
40fb9820 L |
7019 | i386_operand_type types; |
7020 | ||
0dfbf9d7 | 7021 | operand_type_set (&types, ~0); |
252b5132 RH |
7022 | |
7023 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
7024 | { | |
31b2323c L |
7025 | as_bad (_("at most %d immediate operands are allowed"), |
7026 | MAX_IMMEDIATE_OPERANDS); | |
252b5132 RH |
7027 | return 0; |
7028 | } | |
7029 | ||
7030 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 7031 | i.op[this_operand].imms = exp; |
252b5132 RH |
7032 | |
7033 | if (is_space_char (*imm_start)) | |
7034 | ++imm_start; | |
7035 | ||
7036 | save_input_line_pointer = input_line_pointer; | |
7037 | input_line_pointer = imm_start; | |
7038 | ||
3956db08 | 7039 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
7040 | if (gotfree_input_line) |
7041 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
7042 | |
7043 | exp_seg = expression (exp); | |
7044 | ||
83183c0c | 7045 | SKIP_WHITESPACE (); |
252b5132 | 7046 | if (*input_line_pointer) |
f3c180ae | 7047 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
7048 | |
7049 | input_line_pointer = save_input_line_pointer; | |
f3c180ae | 7050 | if (gotfree_input_line) |
ee86248c JB |
7051 | { |
7052 | free (gotfree_input_line); | |
7053 | ||
7054 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
7055 | exp->X_op = O_illegal; | |
7056 | } | |
7057 | ||
7058 | return i386_finalize_immediate (exp_seg, exp, types, imm_start); | |
7059 | } | |
252b5132 | 7060 | |
ee86248c JB |
7061 | static int |
7062 | i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
7063 | i386_operand_type types, const char *imm_start) | |
7064 | { | |
7065 | if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big) | |
252b5132 | 7066 | { |
313c53d1 L |
7067 | if (imm_start) |
7068 | as_bad (_("missing or invalid immediate expression `%s'"), | |
7069 | imm_start); | |
3992d3b7 | 7070 | return 0; |
252b5132 | 7071 | } |
3e73aa7c | 7072 | else if (exp->X_op == O_constant) |
252b5132 | 7073 | { |
47926f60 | 7074 | /* Size it properly later. */ |
40fb9820 | 7075 | i.types[this_operand].bitfield.imm64 = 1; |
13f864ae L |
7076 | /* If not 64bit, sign extend val. */ |
7077 | if (flag_code != CODE_64BIT | |
4eed87de AM |
7078 | && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) |
7079 | exp->X_add_number | |
7080 | = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
252b5132 | 7081 | } |
4c63da97 | 7082 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
f86103b7 | 7083 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 7084 | && exp_seg != absolute_section |
47926f60 | 7085 | && exp_seg != text_section |
24eab124 AM |
7086 | && exp_seg != data_section |
7087 | && exp_seg != bss_section | |
7088 | && exp_seg != undefined_section | |
f86103b7 | 7089 | && !bfd_is_com_section (exp_seg)) |
252b5132 | 7090 | { |
d0b47220 | 7091 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
252b5132 RH |
7092 | return 0; |
7093 | } | |
7094 | #endif | |
bb8f5920 L |
7095 | else if (!intel_syntax && exp->X_op == O_register) |
7096 | { | |
313c53d1 L |
7097 | if (imm_start) |
7098 | as_bad (_("illegal immediate register operand %s"), imm_start); | |
bb8f5920 L |
7099 | return 0; |
7100 | } | |
252b5132 RH |
7101 | else |
7102 | { | |
7103 | /* This is an address. The size of the address will be | |
24eab124 | 7104 | determined later, depending on destination register, |
3e73aa7c | 7105 | suffix, or the default for the section. */ |
40fb9820 L |
7106 | i.types[this_operand].bitfield.imm8 = 1; |
7107 | i.types[this_operand].bitfield.imm16 = 1; | |
7108 | i.types[this_operand].bitfield.imm32 = 1; | |
7109 | i.types[this_operand].bitfield.imm32s = 1; | |
7110 | i.types[this_operand].bitfield.imm64 = 1; | |
c6fb90c8 L |
7111 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
7112 | types); | |
252b5132 RH |
7113 | } |
7114 | ||
7115 | return 1; | |
7116 | } | |
7117 | ||
551c1ca1 | 7118 | static char * |
e3bb37b5 | 7119 | i386_scale (char *scale) |
252b5132 | 7120 | { |
551c1ca1 AM |
7121 | offsetT val; |
7122 | char *save = input_line_pointer; | |
252b5132 | 7123 | |
551c1ca1 AM |
7124 | input_line_pointer = scale; |
7125 | val = get_absolute_expression (); | |
7126 | ||
7127 | switch (val) | |
252b5132 | 7128 | { |
551c1ca1 | 7129 | case 1: |
252b5132 RH |
7130 | i.log2_scale_factor = 0; |
7131 | break; | |
551c1ca1 | 7132 | case 2: |
252b5132 RH |
7133 | i.log2_scale_factor = 1; |
7134 | break; | |
551c1ca1 | 7135 | case 4: |
252b5132 RH |
7136 | i.log2_scale_factor = 2; |
7137 | break; | |
551c1ca1 | 7138 | case 8: |
252b5132 RH |
7139 | i.log2_scale_factor = 3; |
7140 | break; | |
7141 | default: | |
a724f0f4 JB |
7142 | { |
7143 | char sep = *input_line_pointer; | |
7144 | ||
7145 | *input_line_pointer = '\0'; | |
7146 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
7147 | scale); | |
7148 | *input_line_pointer = sep; | |
7149 | input_line_pointer = save; | |
7150 | return NULL; | |
7151 | } | |
252b5132 | 7152 | } |
29b0f896 | 7153 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
252b5132 RH |
7154 | { |
7155 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 7156 | 1 << i.log2_scale_factor); |
252b5132 | 7157 | i.log2_scale_factor = 0; |
252b5132 | 7158 | } |
551c1ca1 AM |
7159 | scale = input_line_pointer; |
7160 | input_line_pointer = save; | |
7161 | return scale; | |
252b5132 RH |
7162 | } |
7163 | ||
252b5132 | 7164 | static int |
e3bb37b5 | 7165 | i386_displacement (char *disp_start, char *disp_end) |
252b5132 | 7166 | { |
29b0f896 | 7167 | expressionS *exp; |
252b5132 RH |
7168 | segT exp_seg = 0; |
7169 | char *save_input_line_pointer; | |
f3c180ae | 7170 | char *gotfree_input_line; |
40fb9820 L |
7171 | int override; |
7172 | i386_operand_type bigdisp, types = anydisp; | |
3992d3b7 | 7173 | int ret; |
252b5132 | 7174 | |
31b2323c L |
7175 | if (i.disp_operands == MAX_MEMORY_OPERANDS) |
7176 | { | |
7177 | as_bad (_("at most %d displacement operands are allowed"), | |
7178 | MAX_MEMORY_OPERANDS); | |
7179 | return 0; | |
7180 | } | |
7181 | ||
0dfbf9d7 | 7182 | operand_type_set (&bigdisp, 0); |
40fb9820 L |
7183 | if ((i.types[this_operand].bitfield.jumpabsolute) |
7184 | || (!current_templates->start->opcode_modifier.jump | |
7185 | && !current_templates->start->opcode_modifier.jumpdword)) | |
e05278af | 7186 | { |
40fb9820 | 7187 | bigdisp.bitfield.disp32 = 1; |
e05278af | 7188 | override = (i.prefix[ADDR_PREFIX] != 0); |
40fb9820 L |
7189 | if (flag_code == CODE_64BIT) |
7190 | { | |
7191 | if (!override) | |
7192 | { | |
7193 | bigdisp.bitfield.disp32s = 1; | |
7194 | bigdisp.bitfield.disp64 = 1; | |
7195 | } | |
7196 | } | |
7197 | else if ((flag_code == CODE_16BIT) ^ override) | |
7198 | { | |
7199 | bigdisp.bitfield.disp32 = 0; | |
7200 | bigdisp.bitfield.disp16 = 1; | |
7201 | } | |
e05278af JB |
7202 | } |
7203 | else | |
7204 | { | |
7205 | /* For PC-relative branches, the width of the displacement | |
7206 | is dependent upon data size, not address size. */ | |
e05278af | 7207 | override = (i.prefix[DATA_PREFIX] != 0); |
40fb9820 L |
7208 | if (flag_code == CODE_64BIT) |
7209 | { | |
7210 | if (override || i.suffix == WORD_MNEM_SUFFIX) | |
7211 | bigdisp.bitfield.disp16 = 1; | |
7212 | else | |
7213 | { | |
7214 | bigdisp.bitfield.disp32 = 1; | |
7215 | bigdisp.bitfield.disp32s = 1; | |
7216 | } | |
7217 | } | |
7218 | else | |
e05278af JB |
7219 | { |
7220 | if (!override) | |
7221 | override = (i.suffix == (flag_code != CODE_16BIT | |
7222 | ? WORD_MNEM_SUFFIX | |
7223 | : LONG_MNEM_SUFFIX)); | |
40fb9820 L |
7224 | bigdisp.bitfield.disp32 = 1; |
7225 | if ((flag_code == CODE_16BIT) ^ override) | |
7226 | { | |
7227 | bigdisp.bitfield.disp32 = 0; | |
7228 | bigdisp.bitfield.disp16 = 1; | |
7229 | } | |
e05278af | 7230 | } |
e05278af | 7231 | } |
c6fb90c8 L |
7232 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
7233 | bigdisp); | |
252b5132 RH |
7234 | |
7235 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 7236 | i.op[this_operand].disps = exp; |
252b5132 RH |
7237 | i.disp_operands++; |
7238 | save_input_line_pointer = input_line_pointer; | |
7239 | input_line_pointer = disp_start; | |
7240 | END_STRING_AND_SAVE (disp_end); | |
7241 | ||
7242 | #ifndef GCC_ASM_O_HACK | |
7243 | #define GCC_ASM_O_HACK 0 | |
7244 | #endif | |
7245 | #if GCC_ASM_O_HACK | |
7246 | END_STRING_AND_SAVE (disp_end + 1); | |
40fb9820 | 7247 | if (i.types[this_operand].bitfield.baseIndex |
24eab124 | 7248 | && displacement_string_end[-1] == '+') |
252b5132 RH |
7249 | { |
7250 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
7251 | constraint within gcc asm statements. |
7252 | For instance: | |
7253 | ||
7254 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
7255 | __asm__ __volatile__ ( \ | |
7256 | "movw %w2,%0\n\t" \ | |
7257 | "movw %w1,2+%0\n\t" \ | |
7258 | "rorl $16,%1\n\t" \ | |
7259 | "movb %b1,4+%0\n\t" \ | |
7260 | "movb %4,5+%0\n\t" \ | |
7261 | "movb $0,6+%0\n\t" \ | |
7262 | "movb %h1,7+%0\n\t" \ | |
7263 | "rorl $16,%1" \ | |
7264 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
7265 | ||
7266 | This works great except that the output assembler ends | |
7267 | up looking a bit weird if it turns out that there is | |
7268 | no offset. You end up producing code that looks like: | |
7269 | ||
7270 | #APP | |
7271 | movw $235,(%eax) | |
7272 | movw %dx,2+(%eax) | |
7273 | rorl $16,%edx | |
7274 | movb %dl,4+(%eax) | |
7275 | movb $137,5+(%eax) | |
7276 | movb $0,6+(%eax) | |
7277 | movb %dh,7+(%eax) | |
7278 | rorl $16,%edx | |
7279 | #NO_APP | |
7280 | ||
47926f60 | 7281 | So here we provide the missing zero. */ |
24eab124 AM |
7282 | |
7283 | *displacement_string_end = '0'; | |
252b5132 RH |
7284 | } |
7285 | #endif | |
3956db08 | 7286 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
7287 | if (gotfree_input_line) |
7288 | input_line_pointer = gotfree_input_line; | |
252b5132 | 7289 | |
24eab124 | 7290 | exp_seg = expression (exp); |
252b5132 | 7291 | |
636c26b0 AM |
7292 | SKIP_WHITESPACE (); |
7293 | if (*input_line_pointer) | |
7294 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
7295 | #if GCC_ASM_O_HACK | |
7296 | RESTORE_END_STRING (disp_end + 1); | |
7297 | #endif | |
636c26b0 | 7298 | input_line_pointer = save_input_line_pointer; |
636c26b0 | 7299 | if (gotfree_input_line) |
ee86248c JB |
7300 | { |
7301 | free (gotfree_input_line); | |
7302 | ||
7303 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
7304 | exp->X_op = O_illegal; | |
7305 | } | |
7306 | ||
7307 | ret = i386_finalize_displacement (exp_seg, exp, types, disp_start); | |
7308 | ||
7309 | RESTORE_END_STRING (disp_end); | |
7310 | ||
7311 | return ret; | |
7312 | } | |
7313 | ||
7314 | static int | |
7315 | i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
7316 | i386_operand_type types, const char *disp_start) | |
7317 | { | |
7318 | i386_operand_type bigdisp; | |
7319 | int ret = 1; | |
636c26b0 | 7320 | |
24eab124 AM |
7321 | /* We do this to make sure that the section symbol is in |
7322 | the symbol table. We will ultimately change the relocation | |
47926f60 | 7323 | to be relative to the beginning of the section. */ |
1ae12ab7 | 7324 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
d6ab8113 JB |
7325 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
7326 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) | |
24eab124 | 7327 | { |
636c26b0 | 7328 | if (exp->X_op != O_symbol) |
3992d3b7 | 7329 | goto inv_disp; |
636c26b0 | 7330 | |
e5cb08ac | 7331 | if (S_IS_LOCAL (exp->X_add_symbol) |
c64efb4b L |
7332 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section |
7333 | && S_GET_SEGMENT (exp->X_add_symbol) != expr_section) | |
24eab124 | 7334 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); |
24eab124 AM |
7335 | exp->X_op = O_subtract; |
7336 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 | 7337 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
29b0f896 | 7338 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
d6ab8113 JB |
7339 | else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
7340 | i.reloc[this_operand] = BFD_RELOC_64; | |
23df1078 | 7341 | else |
29b0f896 | 7342 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 7343 | } |
252b5132 | 7344 | |
3992d3b7 AM |
7345 | else if (exp->X_op == O_absent |
7346 | || exp->X_op == O_illegal | |
ee86248c | 7347 | || exp->X_op == O_big) |
2daf4fd8 | 7348 | { |
3992d3b7 AM |
7349 | inv_disp: |
7350 | as_bad (_("missing or invalid displacement expression `%s'"), | |
2daf4fd8 | 7351 | disp_start); |
3992d3b7 | 7352 | ret = 0; |
2daf4fd8 AM |
7353 | } |
7354 | ||
0e1147d9 L |
7355 | else if (flag_code == CODE_64BIT |
7356 | && !i.prefix[ADDR_PREFIX] | |
7357 | && exp->X_op == O_constant) | |
7358 | { | |
7359 | /* Since displacement is signed extended to 64bit, don't allow | |
7360 | disp32 and turn off disp32s if they are out of range. */ | |
7361 | i.types[this_operand].bitfield.disp32 = 0; | |
7362 | if (!fits_in_signed_long (exp->X_add_number)) | |
7363 | { | |
7364 | i.types[this_operand].bitfield.disp32s = 0; | |
7365 | if (i.types[this_operand].bitfield.baseindex) | |
7366 | { | |
7367 | as_bad (_("0x%lx out range of signed 32bit displacement"), | |
7368 | (long) exp->X_add_number); | |
7369 | ret = 0; | |
7370 | } | |
7371 | } | |
7372 | } | |
7373 | ||
4c63da97 | 7374 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
3992d3b7 AM |
7375 | else if (exp->X_op != O_constant |
7376 | && OUTPUT_FLAVOR == bfd_target_aout_flavour | |
7377 | && exp_seg != absolute_section | |
7378 | && exp_seg != text_section | |
7379 | && exp_seg != data_section | |
7380 | && exp_seg != bss_section | |
7381 | && exp_seg != undefined_section | |
7382 | && !bfd_is_com_section (exp_seg)) | |
24eab124 | 7383 | { |
d0b47220 | 7384 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
3992d3b7 | 7385 | ret = 0; |
24eab124 | 7386 | } |
252b5132 | 7387 | #endif |
3956db08 | 7388 | |
40fb9820 L |
7389 | /* Check if this is a displacement only operand. */ |
7390 | bigdisp = i.types[this_operand]; | |
7391 | bigdisp.bitfield.disp8 = 0; | |
7392 | bigdisp.bitfield.disp16 = 0; | |
7393 | bigdisp.bitfield.disp32 = 0; | |
7394 | bigdisp.bitfield.disp32s = 0; | |
7395 | bigdisp.bitfield.disp64 = 0; | |
0dfbf9d7 | 7396 | if (operand_type_all_zero (&bigdisp)) |
c6fb90c8 L |
7397 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
7398 | types); | |
3956db08 | 7399 | |
3992d3b7 | 7400 | return ret; |
252b5132 RH |
7401 | } |
7402 | ||
eecb386c | 7403 | /* Make sure the memory operand we've been dealt is valid. |
47926f60 KH |
7404 | Return 1 on success, 0 on a failure. */ |
7405 | ||
252b5132 | 7406 | static int |
e3bb37b5 | 7407 | i386_index_check (const char *operand_string) |
252b5132 | 7408 | { |
3e73aa7c | 7409 | int ok; |
fc0763e6 | 7410 | const char *kind = "base/index"; |
24eab124 | 7411 | #if INFER_ADDR_PREFIX |
eecb386c AM |
7412 | int fudged = 0; |
7413 | ||
24eab124 AM |
7414 | tryprefix: |
7415 | #endif | |
3e73aa7c | 7416 | ok = 1; |
fc0763e6 JB |
7417 | if (current_templates->start->opcode_modifier.isstring |
7418 | && !current_templates->start->opcode_modifier.immext | |
7419 | && (current_templates->end[-1].opcode_modifier.isstring | |
7420 | || i.mem_operands)) | |
7421 | { | |
7422 | /* Memory operands of string insns are special in that they only allow | |
7423 | a single register (rDI, rSI, or rBX) as their memory address. */ | |
7424 | unsigned int expected; | |
7425 | ||
7426 | kind = "string address"; | |
7427 | ||
7428 | if (current_templates->start->opcode_modifier.w) | |
7429 | { | |
7430 | i386_operand_type type = current_templates->end[-1].operand_types[0]; | |
7431 | ||
7432 | if (!type.bitfield.baseindex | |
7433 | || ((!i.mem_operands != !intel_syntax) | |
7434 | && current_templates->end[-1].operand_types[1] | |
7435 | .bitfield.baseindex)) | |
7436 | type = current_templates->end[-1].operand_types[1]; | |
7437 | expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */; | |
7438 | } | |
7439 | else | |
7440 | expected = 3 /* rBX */; | |
7441 | ||
7442 | if (!i.base_reg || i.index_reg | |
7443 | || operand_type_check (i.types[this_operand], disp)) | |
7444 | ok = -1; | |
7445 | else if (!(flag_code == CODE_64BIT | |
7446 | ? i.prefix[ADDR_PREFIX] | |
7447 | ? i.base_reg->reg_type.bitfield.reg32 | |
7448 | : i.base_reg->reg_type.bitfield.reg64 | |
7449 | : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX] | |
7450 | ? i.base_reg->reg_type.bitfield.reg32 | |
7451 | : i.base_reg->reg_type.bitfield.reg16)) | |
7452 | ok = 0; | |
4c692bc7 | 7453 | else if (register_number (i.base_reg) != expected) |
fc0763e6 JB |
7454 | ok = -1; |
7455 | ||
7456 | if (ok < 0) | |
7457 | { | |
7458 | unsigned int j; | |
7459 | ||
7460 | for (j = 0; j < i386_regtab_size; ++j) | |
7461 | if ((flag_code == CODE_64BIT | |
7462 | ? i.prefix[ADDR_PREFIX] | |
7463 | ? i386_regtab[j].reg_type.bitfield.reg32 | |
7464 | : i386_regtab[j].reg_type.bitfield.reg64 | |
7465 | : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX] | |
7466 | ? i386_regtab[j].reg_type.bitfield.reg32 | |
7467 | : i386_regtab[j].reg_type.bitfield.reg16) | |
4c692bc7 | 7468 | && register_number(i386_regtab + j) == expected) |
fc0763e6 | 7469 | break; |
9c2799c2 | 7470 | gas_assert (j < i386_regtab_size); |
fc0763e6 JB |
7471 | as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"), |
7472 | operand_string, | |
7473 | intel_syntax ? '[' : '(', | |
7474 | register_prefix, | |
7475 | i386_regtab[j].reg_name, | |
7476 | intel_syntax ? ']' : ')'); | |
7477 | ok = 1; | |
7478 | } | |
7479 | } | |
7480 | else if (flag_code == CODE_64BIT) | |
64e74474 | 7481 | { |
64e74474 | 7482 | if ((i.base_reg |
40fb9820 L |
7483 | && ((i.prefix[ADDR_PREFIX] == 0 |
7484 | && !i.base_reg->reg_type.bitfield.reg64) | |
7485 | || (i.prefix[ADDR_PREFIX] | |
7486 | && !i.base_reg->reg_type.bitfield.reg32)) | |
7487 | && (i.index_reg | |
9a04903e JB |
7488 | || i.base_reg->reg_num != |
7489 | (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip))) | |
64e74474 | 7490 | || (i.index_reg |
6c30d220 L |
7491 | && !(i.index_reg->reg_type.bitfield.regxmm |
7492 | || i.index_reg->reg_type.bitfield.regymm) | |
40fb9820 L |
7493 | && (!i.index_reg->reg_type.bitfield.baseindex |
7494 | || (i.prefix[ADDR_PREFIX] == 0 | |
db51cc60 L |
7495 | && i.index_reg->reg_num != RegRiz |
7496 | && !i.index_reg->reg_type.bitfield.reg64 | |
7497 | ) | |
40fb9820 | 7498 | || (i.prefix[ADDR_PREFIX] |
db51cc60 | 7499 | && i.index_reg->reg_num != RegEiz |
40fb9820 | 7500 | && !i.index_reg->reg_type.bitfield.reg32)))) |
64e74474 | 7501 | ok = 0; |
3e73aa7c JH |
7502 | } |
7503 | else | |
7504 | { | |
7505 | if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) | |
7506 | { | |
7507 | /* 16bit checks. */ | |
7508 | if ((i.base_reg | |
40fb9820 L |
7509 | && (!i.base_reg->reg_type.bitfield.reg16 |
7510 | || !i.base_reg->reg_type.bitfield.baseindex)) | |
3e73aa7c | 7511 | || (i.index_reg |
40fb9820 L |
7512 | && (!i.index_reg->reg_type.bitfield.reg16 |
7513 | || !i.index_reg->reg_type.bitfield.baseindex | |
29b0f896 AM |
7514 | || !(i.base_reg |
7515 | && i.base_reg->reg_num < 6 | |
7516 | && i.index_reg->reg_num >= 6 | |
7517 | && i.log2_scale_factor == 0)))) | |
3e73aa7c JH |
7518 | ok = 0; |
7519 | } | |
7520 | else | |
e5cb08ac | 7521 | { |
3e73aa7c JH |
7522 | /* 32bit checks. */ |
7523 | if ((i.base_reg | |
40fb9820 | 7524 | && !i.base_reg->reg_type.bitfield.reg32) |
3e73aa7c | 7525 | || (i.index_reg |
6c30d220 L |
7526 | && !i.index_reg->reg_type.bitfield.regxmm |
7527 | && !i.index_reg->reg_type.bitfield.regymm | |
db51cc60 L |
7528 | && ((!i.index_reg->reg_type.bitfield.reg32 |
7529 | && i.index_reg->reg_num != RegEiz) | |
40fb9820 | 7530 | || !i.index_reg->reg_type.bitfield.baseindex))) |
e5cb08ac | 7531 | ok = 0; |
3e73aa7c JH |
7532 | } |
7533 | } | |
7534 | if (!ok) | |
24eab124 AM |
7535 | { |
7536 | #if INFER_ADDR_PREFIX | |
fc0763e6 | 7537 | if (!i.mem_operands && !i.prefix[ADDR_PREFIX]) |
24eab124 AM |
7538 | { |
7539 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
7540 | i.prefixes += 1; | |
b23bac36 AM |
7541 | /* Change the size of any displacement too. At most one of |
7542 | Disp16 or Disp32 is set. | |
7543 | FIXME. There doesn't seem to be any real need for separate | |
7544 | Disp16 and Disp32 flags. The same goes for Imm16 and Imm32. | |
47926f60 | 7545 | Removing them would probably clean up the code quite a lot. */ |
4eed87de | 7546 | if (flag_code != CODE_64BIT |
40fb9820 L |
7547 | && (i.types[this_operand].bitfield.disp16 |
7548 | || i.types[this_operand].bitfield.disp32)) | |
7549 | i.types[this_operand] | |
c6fb90c8 | 7550 | = operand_type_xor (i.types[this_operand], disp16_32); |
eecb386c | 7551 | fudged = 1; |
24eab124 AM |
7552 | goto tryprefix; |
7553 | } | |
eecb386c | 7554 | if (fudged) |
fc0763e6 JB |
7555 | as_bad (_("`%s' is not a valid %s expression"), |
7556 | operand_string, | |
7557 | kind); | |
eecb386c | 7558 | else |
c388dee8 | 7559 | #endif |
fc0763e6 | 7560 | as_bad (_("`%s' is not a valid %s-bit %s expression"), |
eecb386c | 7561 | operand_string, |
fc0763e6 JB |
7562 | flag_code_names[i.prefix[ADDR_PREFIX] |
7563 | ? flag_code == CODE_32BIT | |
7564 | ? CODE_16BIT | |
7565 | : CODE_32BIT | |
7566 | : flag_code], | |
7567 | kind); | |
24eab124 | 7568 | } |
20f0a1fc | 7569 | return ok; |
24eab124 | 7570 | } |
252b5132 | 7571 | |
fc0763e6 | 7572 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero |
47926f60 | 7573 | on error. */ |
252b5132 | 7574 | |
252b5132 | 7575 | static int |
a7619375 | 7576 | i386_att_operand (char *operand_string) |
252b5132 | 7577 | { |
af6bdddf AM |
7578 | const reg_entry *r; |
7579 | char *end_op; | |
24eab124 | 7580 | char *op_string = operand_string; |
252b5132 | 7581 | |
24eab124 | 7582 | if (is_space_char (*op_string)) |
252b5132 RH |
7583 | ++op_string; |
7584 | ||
24eab124 | 7585 | /* We check for an absolute prefix (differentiating, |
47926f60 | 7586 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
7587 | if (*op_string == ABSOLUTE_PREFIX) |
7588 | { | |
7589 | ++op_string; | |
7590 | if (is_space_char (*op_string)) | |
7591 | ++op_string; | |
40fb9820 | 7592 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 | 7593 | } |
252b5132 | 7594 | |
47926f60 | 7595 | /* Check if operand is a register. */ |
4d1bb795 | 7596 | if ((r = parse_register (op_string, &end_op)) != NULL) |
24eab124 | 7597 | { |
40fb9820 L |
7598 | i386_operand_type temp; |
7599 | ||
24eab124 AM |
7600 | /* Check for a segment override by searching for ':' after a |
7601 | segment register. */ | |
7602 | op_string = end_op; | |
7603 | if (is_space_char (*op_string)) | |
7604 | ++op_string; | |
40fb9820 L |
7605 | if (*op_string == ':' |
7606 | && (r->reg_type.bitfield.sreg2 | |
7607 | || r->reg_type.bitfield.sreg3)) | |
24eab124 AM |
7608 | { |
7609 | switch (r->reg_num) | |
7610 | { | |
7611 | case 0: | |
7612 | i.seg[i.mem_operands] = &es; | |
7613 | break; | |
7614 | case 1: | |
7615 | i.seg[i.mem_operands] = &cs; | |
7616 | break; | |
7617 | case 2: | |
7618 | i.seg[i.mem_operands] = &ss; | |
7619 | break; | |
7620 | case 3: | |
7621 | i.seg[i.mem_operands] = &ds; | |
7622 | break; | |
7623 | case 4: | |
7624 | i.seg[i.mem_operands] = &fs; | |
7625 | break; | |
7626 | case 5: | |
7627 | i.seg[i.mem_operands] = &gs; | |
7628 | break; | |
7629 | } | |
252b5132 | 7630 | |
24eab124 | 7631 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
7632 | ++op_string; |
7633 | if (is_space_char (*op_string)) | |
24eab124 | 7634 | ++op_string; |
252b5132 | 7635 | |
24eab124 AM |
7636 | if (!is_digit_char (*op_string) |
7637 | && !is_identifier_char (*op_string) | |
7638 | && *op_string != '(' | |
7639 | && *op_string != ABSOLUTE_PREFIX) | |
7640 | { | |
7641 | as_bad (_("bad memory operand `%s'"), op_string); | |
7642 | return 0; | |
7643 | } | |
47926f60 | 7644 | /* Handle case of %es:*foo. */ |
24eab124 AM |
7645 | if (*op_string == ABSOLUTE_PREFIX) |
7646 | { | |
7647 | ++op_string; | |
7648 | if (is_space_char (*op_string)) | |
7649 | ++op_string; | |
40fb9820 | 7650 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 AM |
7651 | } |
7652 | goto do_memory_reference; | |
7653 | } | |
7654 | if (*op_string) | |
7655 | { | |
d0b47220 | 7656 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
7657 | return 0; |
7658 | } | |
40fb9820 L |
7659 | temp = r->reg_type; |
7660 | temp.bitfield.baseindex = 0; | |
c6fb90c8 L |
7661 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
7662 | temp); | |
7d5e4556 | 7663 | i.types[this_operand].bitfield.unspecified = 0; |
520dc8e8 | 7664 | i.op[this_operand].regs = r; |
24eab124 AM |
7665 | i.reg_operands++; |
7666 | } | |
af6bdddf AM |
7667 | else if (*op_string == REGISTER_PREFIX) |
7668 | { | |
7669 | as_bad (_("bad register name `%s'"), op_string); | |
7670 | return 0; | |
7671 | } | |
24eab124 | 7672 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 7673 | { |
24eab124 | 7674 | ++op_string; |
40fb9820 | 7675 | if (i.types[this_operand].bitfield.jumpabsolute) |
24eab124 | 7676 | { |
d0b47220 | 7677 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
7678 | return 0; |
7679 | } | |
7680 | if (!i386_immediate (op_string)) | |
7681 | return 0; | |
7682 | } | |
7683 | else if (is_digit_char (*op_string) | |
7684 | || is_identifier_char (*op_string) | |
e5cb08ac | 7685 | || *op_string == '(') |
24eab124 | 7686 | { |
47926f60 | 7687 | /* This is a memory reference of some sort. */ |
af6bdddf | 7688 | char *base_string; |
252b5132 | 7689 | |
47926f60 | 7690 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
7691 | char *displacement_string_start; |
7692 | char *displacement_string_end; | |
252b5132 | 7693 | |
24eab124 | 7694 | do_memory_reference: |
24eab124 | 7695 | if ((i.mem_operands == 1 |
40fb9820 | 7696 | && !current_templates->start->opcode_modifier.isstring) |
24eab124 AM |
7697 | || i.mem_operands == 2) |
7698 | { | |
7699 | as_bad (_("too many memory references for `%s'"), | |
7700 | current_templates->start->name); | |
7701 | return 0; | |
7702 | } | |
252b5132 | 7703 | |
24eab124 AM |
7704 | /* Check for base index form. We detect the base index form by |
7705 | looking for an ')' at the end of the operand, searching | |
7706 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
7707 | after the '('. */ | |
af6bdddf | 7708 | base_string = op_string + strlen (op_string); |
c3332e24 | 7709 | |
af6bdddf AM |
7710 | --base_string; |
7711 | if (is_space_char (*base_string)) | |
7712 | --base_string; | |
252b5132 | 7713 | |
47926f60 | 7714 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
7715 | displacement_string_start = op_string; |
7716 | displacement_string_end = base_string + 1; | |
252b5132 | 7717 | |
24eab124 AM |
7718 | if (*base_string == ')') |
7719 | { | |
af6bdddf | 7720 | char *temp_string; |
24eab124 AM |
7721 | unsigned int parens_balanced = 1; |
7722 | /* We've already checked that the number of left & right ()'s are | |
47926f60 | 7723 | equal, so this loop will not be infinite. */ |
24eab124 AM |
7724 | do |
7725 | { | |
7726 | base_string--; | |
7727 | if (*base_string == ')') | |
7728 | parens_balanced++; | |
7729 | if (*base_string == '(') | |
7730 | parens_balanced--; | |
7731 | } | |
7732 | while (parens_balanced); | |
c3332e24 | 7733 | |
af6bdddf | 7734 | temp_string = base_string; |
c3332e24 | 7735 | |
24eab124 | 7736 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
7737 | ++base_string; |
7738 | if (is_space_char (*base_string)) | |
24eab124 | 7739 | ++base_string; |
252b5132 | 7740 | |
af6bdddf | 7741 | if (*base_string == ',' |
4eed87de AM |
7742 | || ((i.base_reg = parse_register (base_string, &end_op)) |
7743 | != NULL)) | |
252b5132 | 7744 | { |
af6bdddf | 7745 | displacement_string_end = temp_string; |
252b5132 | 7746 | |
40fb9820 | 7747 | i.types[this_operand].bitfield.baseindex = 1; |
252b5132 | 7748 | |
af6bdddf | 7749 | if (i.base_reg) |
24eab124 | 7750 | { |
24eab124 AM |
7751 | base_string = end_op; |
7752 | if (is_space_char (*base_string)) | |
7753 | ++base_string; | |
af6bdddf AM |
7754 | } |
7755 | ||
7756 | /* There may be an index reg or scale factor here. */ | |
7757 | if (*base_string == ',') | |
7758 | { | |
7759 | ++base_string; | |
7760 | if (is_space_char (*base_string)) | |
7761 | ++base_string; | |
7762 | ||
4eed87de AM |
7763 | if ((i.index_reg = parse_register (base_string, &end_op)) |
7764 | != NULL) | |
24eab124 | 7765 | { |
af6bdddf | 7766 | base_string = end_op; |
24eab124 AM |
7767 | if (is_space_char (*base_string)) |
7768 | ++base_string; | |
af6bdddf AM |
7769 | if (*base_string == ',') |
7770 | { | |
7771 | ++base_string; | |
7772 | if (is_space_char (*base_string)) | |
7773 | ++base_string; | |
7774 | } | |
e5cb08ac | 7775 | else if (*base_string != ')') |
af6bdddf | 7776 | { |
4eed87de AM |
7777 | as_bad (_("expecting `,' or `)' " |
7778 | "after index register in `%s'"), | |
af6bdddf AM |
7779 | operand_string); |
7780 | return 0; | |
7781 | } | |
24eab124 | 7782 | } |
af6bdddf | 7783 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 7784 | { |
af6bdddf | 7785 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
7786 | return 0; |
7787 | } | |
252b5132 | 7788 | |
47926f60 | 7789 | /* Check for scale factor. */ |
551c1ca1 | 7790 | if (*base_string != ')') |
af6bdddf | 7791 | { |
551c1ca1 AM |
7792 | char *end_scale = i386_scale (base_string); |
7793 | ||
7794 | if (!end_scale) | |
af6bdddf | 7795 | return 0; |
24eab124 | 7796 | |
551c1ca1 | 7797 | base_string = end_scale; |
af6bdddf AM |
7798 | if (is_space_char (*base_string)) |
7799 | ++base_string; | |
7800 | if (*base_string != ')') | |
7801 | { | |
4eed87de AM |
7802 | as_bad (_("expecting `)' " |
7803 | "after scale factor in `%s'"), | |
af6bdddf AM |
7804 | operand_string); |
7805 | return 0; | |
7806 | } | |
7807 | } | |
7808 | else if (!i.index_reg) | |
24eab124 | 7809 | { |
4eed87de AM |
7810 | as_bad (_("expecting index register or scale factor " |
7811 | "after `,'; got '%c'"), | |
af6bdddf | 7812 | *base_string); |
24eab124 AM |
7813 | return 0; |
7814 | } | |
7815 | } | |
af6bdddf | 7816 | else if (*base_string != ')') |
24eab124 | 7817 | { |
4eed87de AM |
7818 | as_bad (_("expecting `,' or `)' " |
7819 | "after base register in `%s'"), | |
af6bdddf | 7820 | operand_string); |
24eab124 AM |
7821 | return 0; |
7822 | } | |
c3332e24 | 7823 | } |
af6bdddf | 7824 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 7825 | { |
af6bdddf | 7826 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 7827 | return 0; |
c3332e24 | 7828 | } |
24eab124 AM |
7829 | } |
7830 | ||
7831 | /* If there's an expression beginning the operand, parse it, | |
7832 | assuming displacement_string_start and | |
7833 | displacement_string_end are meaningful. */ | |
7834 | if (displacement_string_start != displacement_string_end) | |
7835 | { | |
7836 | if (!i386_displacement (displacement_string_start, | |
7837 | displacement_string_end)) | |
7838 | return 0; | |
7839 | } | |
7840 | ||
7841 | /* Special case for (%dx) while doing input/output op. */ | |
7842 | if (i.base_reg | |
0dfbf9d7 L |
7843 | && operand_type_equal (&i.base_reg->reg_type, |
7844 | ®16_inoutportreg) | |
24eab124 AM |
7845 | && i.index_reg == 0 |
7846 | && i.log2_scale_factor == 0 | |
7847 | && i.seg[i.mem_operands] == 0 | |
40fb9820 | 7848 | && !operand_type_check (i.types[this_operand], disp)) |
24eab124 | 7849 | { |
65da13b5 | 7850 | i.types[this_operand] = inoutportreg; |
24eab124 AM |
7851 | return 1; |
7852 | } | |
7853 | ||
eecb386c AM |
7854 | if (i386_index_check (operand_string) == 0) |
7855 | return 0; | |
5c07affc | 7856 | i.types[this_operand].bitfield.mem = 1; |
24eab124 AM |
7857 | i.mem_operands++; |
7858 | } | |
7859 | else | |
ce8a8b2f AM |
7860 | { |
7861 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
7862 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
7863 | output_invalid (*op_string), | |
7864 | this_operand + 1, | |
7865 | op_string); | |
7866 | return 0; | |
7867 | } | |
47926f60 | 7868 | return 1; /* Normal return. */ |
252b5132 RH |
7869 | } |
7870 | \f | |
fa94de6b RM |
7871 | /* Calculate the maximum variable size (i.e., excluding fr_fix) |
7872 | that an rs_machine_dependent frag may reach. */ | |
7873 | ||
7874 | unsigned int | |
7875 | i386_frag_max_var (fragS *frag) | |
7876 | { | |
7877 | /* The only relaxable frags are for jumps. | |
7878 | Unconditional jumps can grow by 4 bytes and others by 5 bytes. */ | |
7879 | gas_assert (frag->fr_type == rs_machine_dependent); | |
7880 | return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5; | |
7881 | } | |
7882 | ||
ee7fcc42 AM |
7883 | /* md_estimate_size_before_relax() |
7884 | ||
7885 | Called just before relax() for rs_machine_dependent frags. The x86 | |
7886 | assembler uses these frags to handle variable size jump | |
7887 | instructions. | |
7888 | ||
7889 | Any symbol that is now undefined will not become defined. | |
7890 | Return the correct fr_subtype in the frag. | |
7891 | Return the initial "guess for variable size of frag" to caller. | |
7892 | The guess is actually the growth beyond the fixed part. Whatever | |
7893 | we do to grow the fixed or variable part contributes to our | |
7894 | returned value. */ | |
7895 | ||
252b5132 | 7896 | int |
7016a5d5 | 7897 | md_estimate_size_before_relax (fragS *fragP, segT segment) |
252b5132 | 7898 | { |
252b5132 | 7899 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
7900 | check for un-relaxable symbols. On an ELF system, we can't relax |
7901 | an externally visible symbol, because it may be overridden by a | |
7902 | shared library. */ | |
7903 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 7904 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 7905 | || (IS_ELF |
31312f95 | 7906 | && (S_IS_EXTERNAL (fragP->fr_symbol) |
915bcca5 L |
7907 | || S_IS_WEAK (fragP->fr_symbol) |
7908 | || ((symbol_get_bfdsym (fragP->fr_symbol)->flags | |
7909 | & BSF_GNU_INDIRECT_FUNCTION)))) | |
fbeb56a4 DK |
7910 | #endif |
7911 | #if defined (OBJ_COFF) && defined (TE_PE) | |
7ab9ffdd | 7912 | || (OUTPUT_FLAVOR == bfd_target_coff_flavour |
fbeb56a4 | 7913 | && S_IS_WEAK (fragP->fr_symbol)) |
b98ef147 AM |
7914 | #endif |
7915 | ) | |
252b5132 | 7916 | { |
b98ef147 AM |
7917 | /* Symbol is undefined in this segment, or we need to keep a |
7918 | reloc so that weak symbols can be overridden. */ | |
7919 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f86103b7 | 7920 | enum bfd_reloc_code_real reloc_type; |
ee7fcc42 AM |
7921 | unsigned char *opcode; |
7922 | int old_fr_fix; | |
f6af82bd | 7923 | |
ee7fcc42 | 7924 | if (fragP->fr_var != NO_RELOC) |
1e9cc1c2 | 7925 | reloc_type = (enum bfd_reloc_code_real) fragP->fr_var; |
b98ef147 | 7926 | else if (size == 2) |
f6af82bd AM |
7927 | reloc_type = BFD_RELOC_16_PCREL; |
7928 | else | |
7929 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 7930 | |
ee7fcc42 AM |
7931 | old_fr_fix = fragP->fr_fix; |
7932 | opcode = (unsigned char *) fragP->fr_opcode; | |
7933 | ||
fddf5b5b | 7934 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 7935 | { |
fddf5b5b AM |
7936 | case UNCOND_JUMP: |
7937 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 7938 | opcode[0] = 0xe9; |
252b5132 | 7939 | fragP->fr_fix += size; |
062cd5e7 AS |
7940 | fix_new (fragP, old_fr_fix, size, |
7941 | fragP->fr_symbol, | |
7942 | fragP->fr_offset, 1, | |
7943 | reloc_type); | |
252b5132 RH |
7944 | break; |
7945 | ||
fddf5b5b | 7946 | case COND_JUMP86: |
412167cb AM |
7947 | if (size == 2 |
7948 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) | |
fddf5b5b AM |
7949 | { |
7950 | /* Negate the condition, and branch past an | |
7951 | unconditional jump. */ | |
7952 | opcode[0] ^= 1; | |
7953 | opcode[1] = 3; | |
7954 | /* Insert an unconditional jump. */ | |
7955 | opcode[2] = 0xe9; | |
7956 | /* We added two extra opcode bytes, and have a two byte | |
7957 | offset. */ | |
7958 | fragP->fr_fix += 2 + 2; | |
062cd5e7 AS |
7959 | fix_new (fragP, old_fr_fix + 2, 2, |
7960 | fragP->fr_symbol, | |
7961 | fragP->fr_offset, 1, | |
7962 | reloc_type); | |
fddf5b5b AM |
7963 | break; |
7964 | } | |
7965 | /* Fall through. */ | |
7966 | ||
7967 | case COND_JUMP: | |
412167cb AM |
7968 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
7969 | { | |
3e02c1cc AM |
7970 | fixS *fixP; |
7971 | ||
412167cb | 7972 | fragP->fr_fix += 1; |
3e02c1cc AM |
7973 | fixP = fix_new (fragP, old_fr_fix, 1, |
7974 | fragP->fr_symbol, | |
7975 | fragP->fr_offset, 1, | |
7976 | BFD_RELOC_8_PCREL); | |
7977 | fixP->fx_signed = 1; | |
412167cb AM |
7978 | break; |
7979 | } | |
93c2a809 | 7980 | |
24eab124 | 7981 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 7982 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 7983 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 7984 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
7985 | /* We've added an opcode byte. */ |
7986 | fragP->fr_fix += 1 + size; | |
062cd5e7 AS |
7987 | fix_new (fragP, old_fr_fix + 1, size, |
7988 | fragP->fr_symbol, | |
7989 | fragP->fr_offset, 1, | |
7990 | reloc_type); | |
252b5132 | 7991 | break; |
fddf5b5b AM |
7992 | |
7993 | default: | |
7994 | BAD_CASE (fragP->fr_subtype); | |
7995 | break; | |
252b5132 RH |
7996 | } |
7997 | frag_wane (fragP); | |
ee7fcc42 | 7998 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 7999 | } |
93c2a809 | 8000 | |
93c2a809 AM |
8001 | /* Guess size depending on current relax state. Initially the relax |
8002 | state will correspond to a short jump and we return 1, because | |
8003 | the variable part of the frag (the branch offset) is one byte | |
8004 | long. However, we can relax a section more than once and in that | |
8005 | case we must either set fr_subtype back to the unrelaxed state, | |
8006 | or return the value for the appropriate branch. */ | |
8007 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
8008 | } |
8009 | ||
47926f60 KH |
8010 | /* Called after relax() is finished. |
8011 | ||
8012 | In: Address of frag. | |
8013 | fr_type == rs_machine_dependent. | |
8014 | fr_subtype is what the address relaxed to. | |
8015 | ||
8016 | Out: Any fixSs and constants are set up. | |
8017 | Caller will turn frag into a ".space 0". */ | |
8018 | ||
252b5132 | 8019 | void |
7016a5d5 TG |
8020 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, |
8021 | fragS *fragP) | |
252b5132 | 8022 | { |
29b0f896 | 8023 | unsigned char *opcode; |
252b5132 | 8024 | unsigned char *where_to_put_displacement = NULL; |
847f7ad4 AM |
8025 | offsetT target_address; |
8026 | offsetT opcode_address; | |
252b5132 | 8027 | unsigned int extension = 0; |
847f7ad4 | 8028 | offsetT displacement_from_opcode_start; |
252b5132 RH |
8029 | |
8030 | opcode = (unsigned char *) fragP->fr_opcode; | |
8031 | ||
47926f60 | 8032 | /* Address we want to reach in file space. */ |
252b5132 | 8033 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 8034 | |
47926f60 | 8035 | /* Address opcode resides at in file space. */ |
252b5132 RH |
8036 | opcode_address = fragP->fr_address + fragP->fr_fix; |
8037 | ||
47926f60 | 8038 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
8039 | displacement_from_opcode_start = target_address - opcode_address; |
8040 | ||
fddf5b5b | 8041 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 8042 | { |
47926f60 KH |
8043 | /* Don't have to change opcode. */ |
8044 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 8045 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
8046 | } |
8047 | else | |
8048 | { | |
8049 | if (no_cond_jump_promotion | |
8050 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4eed87de AM |
8051 | as_warn_where (fragP->fr_file, fragP->fr_line, |
8052 | _("long jump required")); | |
252b5132 | 8053 | |
fddf5b5b AM |
8054 | switch (fragP->fr_subtype) |
8055 | { | |
8056 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
8057 | extension = 4; /* 1 opcode + 4 displacement */ | |
8058 | opcode[0] = 0xe9; | |
8059 | where_to_put_displacement = &opcode[1]; | |
8060 | break; | |
252b5132 | 8061 | |
fddf5b5b AM |
8062 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
8063 | extension = 2; /* 1 opcode + 2 displacement */ | |
8064 | opcode[0] = 0xe9; | |
8065 | where_to_put_displacement = &opcode[1]; | |
8066 | break; | |
252b5132 | 8067 | |
fddf5b5b AM |
8068 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
8069 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
8070 | extension = 5; /* 2 opcode + 4 displacement */ | |
8071 | opcode[1] = opcode[0] + 0x10; | |
8072 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
8073 | where_to_put_displacement = &opcode[2]; | |
8074 | break; | |
252b5132 | 8075 | |
fddf5b5b AM |
8076 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
8077 | extension = 3; /* 2 opcode + 2 displacement */ | |
8078 | opcode[1] = opcode[0] + 0x10; | |
8079 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
8080 | where_to_put_displacement = &opcode[2]; | |
8081 | break; | |
252b5132 | 8082 | |
fddf5b5b AM |
8083 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
8084 | extension = 4; | |
8085 | opcode[0] ^= 1; | |
8086 | opcode[1] = 3; | |
8087 | opcode[2] = 0xe9; | |
8088 | where_to_put_displacement = &opcode[3]; | |
8089 | break; | |
8090 | ||
8091 | default: | |
8092 | BAD_CASE (fragP->fr_subtype); | |
8093 | break; | |
8094 | } | |
252b5132 | 8095 | } |
fddf5b5b | 8096 | |
7b81dfbb AJ |
8097 | /* If size if less then four we are sure that the operand fits, |
8098 | but if it's 4, then it could be that the displacement is larger | |
8099 | then -/+ 2GB. */ | |
8100 | if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 | |
8101 | && object_64bit | |
8102 | && ((addressT) (displacement_from_opcode_start - extension | |
4eed87de AM |
8103 | + ((addressT) 1 << 31)) |
8104 | > (((addressT) 2 << 31) - 1))) | |
7b81dfbb AJ |
8105 | { |
8106 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
8107 | _("jump target out of range")); | |
8108 | /* Make us emit 0. */ | |
8109 | displacement_from_opcode_start = extension; | |
8110 | } | |
47926f60 | 8111 | /* Now put displacement after opcode. */ |
252b5132 RH |
8112 | md_number_to_chars ((char *) where_to_put_displacement, |
8113 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 8114 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
8115 | fragP->fr_fix += extension; |
8116 | } | |
8117 | \f | |
7016a5d5 | 8118 | /* Apply a fixup (fixP) to segment data, once it has been determined |
252b5132 RH |
8119 | by our caller that we have all the info we need to fix it up. |
8120 | ||
7016a5d5 TG |
8121 | Parameter valP is the pointer to the value of the bits. |
8122 | ||
252b5132 RH |
8123 | On the 386, immediates, displacements, and data pointers are all in |
8124 | the same (little-endian) format, so we don't need to care about which | |
8125 | we are handling. */ | |
8126 | ||
94f592af | 8127 | void |
7016a5d5 | 8128 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 8129 | { |
94f592af | 8130 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
c6682705 | 8131 | valueT value = *valP; |
252b5132 | 8132 | |
f86103b7 | 8133 | #if !defined (TE_Mach) |
93382f6d AM |
8134 | if (fixP->fx_pcrel) |
8135 | { | |
8136 | switch (fixP->fx_r_type) | |
8137 | { | |
5865bb77 ILT |
8138 | default: |
8139 | break; | |
8140 | ||
d6ab8113 JB |
8141 | case BFD_RELOC_64: |
8142 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
8143 | break; | |
93382f6d | 8144 | case BFD_RELOC_32: |
ae8887b5 | 8145 | case BFD_RELOC_X86_64_32S: |
93382f6d AM |
8146 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
8147 | break; | |
8148 | case BFD_RELOC_16: | |
8149 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
8150 | break; | |
8151 | case BFD_RELOC_8: | |
8152 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
8153 | break; | |
8154 | } | |
8155 | } | |
252b5132 | 8156 | |
a161fe53 | 8157 | if (fixP->fx_addsy != NULL |
31312f95 | 8158 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
d6ab8113 | 8159 | || fixP->fx_r_type == BFD_RELOC_64_PCREL |
31312f95 AM |
8160 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
8161 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) | |
8162 | && !use_rela_relocations) | |
252b5132 | 8163 | { |
31312f95 AM |
8164 | /* This is a hack. There should be a better way to handle this. |
8165 | This covers for the fact that bfd_install_relocation will | |
8166 | subtract the current location (for partial_inplace, PC relative | |
8167 | relocations); see more below. */ | |
252b5132 | 8168 | #ifndef OBJ_AOUT |
718ddfc0 | 8169 | if (IS_ELF |
252b5132 RH |
8170 | #ifdef TE_PE |
8171 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
8172 | #endif | |
8173 | ) | |
8174 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
8175 | #endif | |
8176 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 8177 | if (IS_ELF) |
252b5132 | 8178 | { |
6539b54b | 8179 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
2f66722d | 8180 | |
6539b54b | 8181 | if ((sym_seg == seg |
2f66722d | 8182 | || (symbol_section_p (fixP->fx_addsy) |
6539b54b | 8183 | && sym_seg != absolute_section)) |
af65af87 | 8184 | && !generic_force_reloc (fixP)) |
2f66722d AM |
8185 | { |
8186 | /* Yes, we add the values in twice. This is because | |
6539b54b AM |
8187 | bfd_install_relocation subtracts them out again. I think |
8188 | bfd_install_relocation is broken, but I don't dare change | |
2f66722d AM |
8189 | it. FIXME. */ |
8190 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
8191 | } | |
252b5132 RH |
8192 | } |
8193 | #endif | |
8194 | #if defined (OBJ_COFF) && defined (TE_PE) | |
977cdf5a NC |
8195 | /* For some reason, the PE format does not store a |
8196 | section address offset for a PC relative symbol. */ | |
8197 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg | |
7be1c489 | 8198 | || S_IS_WEAK (fixP->fx_addsy)) |
252b5132 RH |
8199 | value += md_pcrel_from (fixP); |
8200 | #endif | |
8201 | } | |
fbeb56a4 DK |
8202 | #if defined (OBJ_COFF) && defined (TE_PE) |
8203 | if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) | |
8204 | { | |
8205 | value -= S_GET_VALUE (fixP->fx_addsy); | |
8206 | } | |
8207 | #endif | |
252b5132 RH |
8208 | |
8209 | /* Fix a few things - the dynamic linker expects certain values here, | |
0234cb7c | 8210 | and we must not disappoint it. */ |
252b5132 | 8211 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 8212 | if (IS_ELF && fixP->fx_addsy) |
47926f60 KH |
8213 | switch (fixP->fx_r_type) |
8214 | { | |
8215 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 8216 | case BFD_RELOC_X86_64_PLT32: |
47926f60 KH |
8217 | /* Make the jump instruction point to the address of the operand. At |
8218 | runtime we merely add the offset to the actual PLT entry. */ | |
8219 | value = -4; | |
8220 | break; | |
31312f95 | 8221 | |
13ae64f3 JJ |
8222 | case BFD_RELOC_386_TLS_GD: |
8223 | case BFD_RELOC_386_TLS_LDM: | |
13ae64f3 | 8224 | case BFD_RELOC_386_TLS_IE_32: |
37e55690 JJ |
8225 | case BFD_RELOC_386_TLS_IE: |
8226 | case BFD_RELOC_386_TLS_GOTIE: | |
67a4f2b7 | 8227 | case BFD_RELOC_386_TLS_GOTDESC: |
bffbf940 JJ |
8228 | case BFD_RELOC_X86_64_TLSGD: |
8229 | case BFD_RELOC_X86_64_TLSLD: | |
8230 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 | 8231 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
00f7efb6 JJ |
8232 | value = 0; /* Fully resolved at runtime. No addend. */ |
8233 | /* Fallthrough */ | |
8234 | case BFD_RELOC_386_TLS_LE: | |
8235 | case BFD_RELOC_386_TLS_LDO_32: | |
8236 | case BFD_RELOC_386_TLS_LE_32: | |
8237 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 8238 | case BFD_RELOC_X86_64_DTPOFF64: |
00f7efb6 | 8239 | case BFD_RELOC_X86_64_TPOFF32: |
d6ab8113 | 8240 | case BFD_RELOC_X86_64_TPOFF64: |
00f7efb6 JJ |
8241 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
8242 | break; | |
8243 | ||
67a4f2b7 AO |
8244 | case BFD_RELOC_386_TLS_DESC_CALL: |
8245 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
8246 | value = 0; /* Fully resolved at runtime. No addend. */ | |
8247 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
8248 | fixP->fx_done = 0; | |
8249 | return; | |
8250 | ||
00f7efb6 JJ |
8251 | case BFD_RELOC_386_GOT32: |
8252 | case BFD_RELOC_X86_64_GOT32: | |
47926f60 KH |
8253 | value = 0; /* Fully resolved at runtime. No addend. */ |
8254 | break; | |
47926f60 KH |
8255 | |
8256 | case BFD_RELOC_VTABLE_INHERIT: | |
8257 | case BFD_RELOC_VTABLE_ENTRY: | |
8258 | fixP->fx_done = 0; | |
94f592af | 8259 | return; |
47926f60 KH |
8260 | |
8261 | default: | |
8262 | break; | |
8263 | } | |
8264 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
c6682705 | 8265 | *valP = value; |
f86103b7 | 8266 | #endif /* !defined (TE_Mach) */ |
3e73aa7c | 8267 | |
3e73aa7c | 8268 | /* Are we finished with this relocation now? */ |
c6682705 | 8269 | if (fixP->fx_addsy == NULL) |
3e73aa7c | 8270 | fixP->fx_done = 1; |
fbeb56a4 DK |
8271 | #if defined (OBJ_COFF) && defined (TE_PE) |
8272 | else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) | |
8273 | { | |
8274 | fixP->fx_done = 0; | |
8275 | /* Remember value for tc_gen_reloc. */ | |
8276 | fixP->fx_addnumber = value; | |
8277 | /* Clear out the frag for now. */ | |
8278 | value = 0; | |
8279 | } | |
8280 | #endif | |
3e73aa7c JH |
8281 | else if (use_rela_relocations) |
8282 | { | |
8283 | fixP->fx_no_overflow = 1; | |
062cd5e7 AS |
8284 | /* Remember value for tc_gen_reloc. */ |
8285 | fixP->fx_addnumber = value; | |
3e73aa7c JH |
8286 | value = 0; |
8287 | } | |
f86103b7 | 8288 | |
94f592af | 8289 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 8290 | } |
252b5132 | 8291 | \f |
252b5132 | 8292 | char * |
499ac353 | 8293 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 8294 | { |
499ac353 NC |
8295 | /* This outputs the LITTLENUMs in REVERSE order; |
8296 | in accord with the bigendian 386. */ | |
8297 | return ieee_md_atof (type, litP, sizeP, FALSE); | |
252b5132 RH |
8298 | } |
8299 | \f | |
2d545b82 | 8300 | static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; |
252b5132 | 8301 | |
252b5132 | 8302 | static char * |
e3bb37b5 | 8303 | output_invalid (int c) |
252b5132 | 8304 | { |
3882b010 | 8305 | if (ISPRINT (c)) |
f9f21a03 L |
8306 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
8307 | "'%c'", c); | |
252b5132 | 8308 | else |
f9f21a03 | 8309 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
2d545b82 | 8310 | "(0x%x)", (unsigned char) c); |
252b5132 RH |
8311 | return output_invalid_buf; |
8312 | } | |
8313 | ||
af6bdddf | 8314 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
8315 | |
8316 | static const reg_entry * | |
4d1bb795 | 8317 | parse_real_register (char *reg_string, char **end_op) |
252b5132 | 8318 | { |
af6bdddf AM |
8319 | char *s = reg_string; |
8320 | char *p; | |
252b5132 RH |
8321 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
8322 | const reg_entry *r; | |
8323 | ||
8324 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
8325 | if (*s == REGISTER_PREFIX) | |
8326 | ++s; | |
8327 | ||
8328 | if (is_space_char (*s)) | |
8329 | ++s; | |
8330 | ||
8331 | p = reg_name_given; | |
af6bdddf | 8332 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
8333 | { |
8334 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
8335 | return (const reg_entry *) NULL; |
8336 | s++; | |
252b5132 RH |
8337 | } |
8338 | ||
6588847e DN |
8339 | /* For naked regs, make sure that we are not dealing with an identifier. |
8340 | This prevents confusing an identifier like `eax_var' with register | |
8341 | `eax'. */ | |
8342 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
8343 | return (const reg_entry *) NULL; | |
8344 | ||
af6bdddf | 8345 | *end_op = s; |
252b5132 RH |
8346 | |
8347 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
8348 | ||
5f47d35b | 8349 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
47926f60 | 8350 | if (r == i386_regtab /* %st is first entry of table */) |
5f47d35b | 8351 | { |
5f47d35b AM |
8352 | if (is_space_char (*s)) |
8353 | ++s; | |
8354 | if (*s == '(') | |
8355 | { | |
af6bdddf | 8356 | ++s; |
5f47d35b AM |
8357 | if (is_space_char (*s)) |
8358 | ++s; | |
8359 | if (*s >= '0' && *s <= '7') | |
8360 | { | |
db557034 | 8361 | int fpr = *s - '0'; |
af6bdddf | 8362 | ++s; |
5f47d35b AM |
8363 | if (is_space_char (*s)) |
8364 | ++s; | |
8365 | if (*s == ')') | |
8366 | { | |
8367 | *end_op = s + 1; | |
1e9cc1c2 | 8368 | r = (const reg_entry *) hash_find (reg_hash, "st(0)"); |
db557034 AM |
8369 | know (r); |
8370 | return r + fpr; | |
5f47d35b | 8371 | } |
5f47d35b | 8372 | } |
47926f60 | 8373 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
8374 | return (const reg_entry *) NULL; |
8375 | } | |
8376 | } | |
8377 | ||
a60de03c JB |
8378 | if (r == NULL || allow_pseudo_reg) |
8379 | return r; | |
8380 | ||
0dfbf9d7 | 8381 | if (operand_type_all_zero (&r->reg_type)) |
a60de03c JB |
8382 | return (const reg_entry *) NULL; |
8383 | ||
192dc9c6 JB |
8384 | if ((r->reg_type.bitfield.reg32 |
8385 | || r->reg_type.bitfield.sreg3 | |
8386 | || r->reg_type.bitfield.control | |
8387 | || r->reg_type.bitfield.debug | |
8388 | || r->reg_type.bitfield.test) | |
8389 | && !cpu_arch_flags.bitfield.cpui386) | |
8390 | return (const reg_entry *) NULL; | |
8391 | ||
309d3373 JB |
8392 | if (r->reg_type.bitfield.floatreg |
8393 | && !cpu_arch_flags.bitfield.cpu8087 | |
8394 | && !cpu_arch_flags.bitfield.cpu287 | |
8395 | && !cpu_arch_flags.bitfield.cpu387) | |
8396 | return (const reg_entry *) NULL; | |
8397 | ||
192dc9c6 JB |
8398 | if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx) |
8399 | return (const reg_entry *) NULL; | |
8400 | ||
8401 | if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse) | |
8402 | return (const reg_entry *) NULL; | |
8403 | ||
40f12533 L |
8404 | if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx) |
8405 | return (const reg_entry *) NULL; | |
8406 | ||
db51cc60 | 8407 | /* Don't allow fake index register unless allow_index_reg isn't 0. */ |
a60de03c | 8408 | if (!allow_index_reg |
db51cc60 L |
8409 | && (r->reg_num == RegEiz || r->reg_num == RegRiz)) |
8410 | return (const reg_entry *) NULL; | |
8411 | ||
a60de03c JB |
8412 | if (((r->reg_flags & (RegRex64 | RegRex)) |
8413 | || r->reg_type.bitfield.reg64) | |
40fb9820 | 8414 | && (!cpu_arch_flags.bitfield.cpulm |
0dfbf9d7 | 8415 | || !operand_type_equal (&r->reg_type, &control)) |
1ae00879 | 8416 | && flag_code != CODE_64BIT) |
20f0a1fc | 8417 | return (const reg_entry *) NULL; |
1ae00879 | 8418 | |
b7240065 JB |
8419 | if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax) |
8420 | return (const reg_entry *) NULL; | |
8421 | ||
252b5132 RH |
8422 | return r; |
8423 | } | |
4d1bb795 JB |
8424 | |
8425 | /* REG_STRING starts *before* REGISTER_PREFIX. */ | |
8426 | ||
8427 | static const reg_entry * | |
8428 | parse_register (char *reg_string, char **end_op) | |
8429 | { | |
8430 | const reg_entry *r; | |
8431 | ||
8432 | if (*reg_string == REGISTER_PREFIX || allow_naked_reg) | |
8433 | r = parse_real_register (reg_string, end_op); | |
8434 | else | |
8435 | r = NULL; | |
8436 | if (!r) | |
8437 | { | |
8438 | char *save = input_line_pointer; | |
8439 | char c; | |
8440 | symbolS *symbolP; | |
8441 | ||
8442 | input_line_pointer = reg_string; | |
8443 | c = get_symbol_end (); | |
8444 | symbolP = symbol_find (reg_string); | |
8445 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) | |
8446 | { | |
8447 | const expressionS *e = symbol_get_value_expression (symbolP); | |
8448 | ||
0398aac5 | 8449 | know (e->X_op == O_register); |
4eed87de | 8450 | know (e->X_add_number >= 0 |
c3fe08fa | 8451 | && (valueT) e->X_add_number < i386_regtab_size); |
4d1bb795 JB |
8452 | r = i386_regtab + e->X_add_number; |
8453 | *end_op = input_line_pointer; | |
8454 | } | |
8455 | *input_line_pointer = c; | |
8456 | input_line_pointer = save; | |
8457 | } | |
8458 | return r; | |
8459 | } | |
8460 | ||
8461 | int | |
8462 | i386_parse_name (char *name, expressionS *e, char *nextcharP) | |
8463 | { | |
8464 | const reg_entry *r; | |
8465 | char *end = input_line_pointer; | |
8466 | ||
8467 | *end = *nextcharP; | |
8468 | r = parse_register (name, &input_line_pointer); | |
8469 | if (r && end <= input_line_pointer) | |
8470 | { | |
8471 | *nextcharP = *input_line_pointer; | |
8472 | *input_line_pointer = 0; | |
8473 | e->X_op = O_register; | |
8474 | e->X_add_number = r - i386_regtab; | |
8475 | return 1; | |
8476 | } | |
8477 | input_line_pointer = end; | |
8478 | *end = 0; | |
ee86248c | 8479 | return intel_syntax ? i386_intel_parse_name (name, e) : 0; |
4d1bb795 JB |
8480 | } |
8481 | ||
8482 | void | |
8483 | md_operand (expressionS *e) | |
8484 | { | |
ee86248c JB |
8485 | char *end; |
8486 | const reg_entry *r; | |
4d1bb795 | 8487 | |
ee86248c JB |
8488 | switch (*input_line_pointer) |
8489 | { | |
8490 | case REGISTER_PREFIX: | |
8491 | r = parse_real_register (input_line_pointer, &end); | |
4d1bb795 JB |
8492 | if (r) |
8493 | { | |
8494 | e->X_op = O_register; | |
8495 | e->X_add_number = r - i386_regtab; | |
8496 | input_line_pointer = end; | |
8497 | } | |
ee86248c JB |
8498 | break; |
8499 | ||
8500 | case '[': | |
9c2799c2 | 8501 | gas_assert (intel_syntax); |
ee86248c JB |
8502 | end = input_line_pointer++; |
8503 | expression (e); | |
8504 | if (*input_line_pointer == ']') | |
8505 | { | |
8506 | ++input_line_pointer; | |
8507 | e->X_op_symbol = make_expr_symbol (e); | |
8508 | e->X_add_symbol = NULL; | |
8509 | e->X_add_number = 0; | |
8510 | e->X_op = O_index; | |
8511 | } | |
8512 | else | |
8513 | { | |
8514 | e->X_op = O_absent; | |
8515 | input_line_pointer = end; | |
8516 | } | |
8517 | break; | |
4d1bb795 JB |
8518 | } |
8519 | } | |
8520 | ||
252b5132 | 8521 | \f |
4cc782b5 | 8522 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
12b55ccc | 8523 | const char *md_shortopts = "kVQ:sqn"; |
252b5132 | 8524 | #else |
12b55ccc | 8525 | const char *md_shortopts = "qn"; |
252b5132 | 8526 | #endif |
6e0b89ee | 8527 | |
3e73aa7c | 8528 | #define OPTION_32 (OPTION_MD_BASE + 0) |
b3b91714 AM |
8529 | #define OPTION_64 (OPTION_MD_BASE + 1) |
8530 | #define OPTION_DIVIDE (OPTION_MD_BASE + 2) | |
9103f4f4 L |
8531 | #define OPTION_MARCH (OPTION_MD_BASE + 3) |
8532 | #define OPTION_MTUNE (OPTION_MD_BASE + 4) | |
1efbbeb4 L |
8533 | #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) |
8534 | #define OPTION_MSYNTAX (OPTION_MD_BASE + 6) | |
8535 | #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) | |
8536 | #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) | |
8537 | #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9) | |
c0f3af97 | 8538 | #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10) |
daf50ae7 | 8539 | #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11) |
7bab8ab5 JB |
8540 | #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12) |
8541 | #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13) | |
8542 | #define OPTION_X32 (OPTION_MD_BASE + 14) | |
b3b91714 | 8543 | |
99ad8390 NC |
8544 | struct option md_longopts[] = |
8545 | { | |
3e73aa7c | 8546 | {"32", no_argument, NULL, OPTION_32}, |
321098a5 | 8547 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 8548 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c | 8549 | {"64", no_argument, NULL, OPTION_64}, |
351f65ca L |
8550 | #endif |
8551 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
570561f7 | 8552 | {"x32", no_argument, NULL, OPTION_X32}, |
6e0b89ee | 8553 | #endif |
b3b91714 | 8554 | {"divide", no_argument, NULL, OPTION_DIVIDE}, |
9103f4f4 L |
8555 | {"march", required_argument, NULL, OPTION_MARCH}, |
8556 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1efbbeb4 L |
8557 | {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, |
8558 | {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, | |
8559 | {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, | |
8560 | {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, | |
8561 | {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC}, | |
c0f3af97 | 8562 | {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX}, |
daf50ae7 | 8563 | {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK}, |
7bab8ab5 | 8564 | {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK}, |
539f890d | 8565 | {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR}, |
252b5132 RH |
8566 | {NULL, no_argument, NULL, 0} |
8567 | }; | |
8568 | size_t md_longopts_size = sizeof (md_longopts); | |
8569 | ||
8570 | int | |
9103f4f4 | 8571 | md_parse_option (int c, char *arg) |
252b5132 | 8572 | { |
91d6fa6a | 8573 | unsigned int j; |
6305a203 | 8574 | char *arch, *next; |
9103f4f4 | 8575 | |
252b5132 RH |
8576 | switch (c) |
8577 | { | |
12b55ccc L |
8578 | case 'n': |
8579 | optimize_align_code = 0; | |
8580 | break; | |
8581 | ||
a38cf1db AM |
8582 | case 'q': |
8583 | quiet_warnings = 1; | |
252b5132 RH |
8584 | break; |
8585 | ||
8586 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
8587 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
8588 | should be emitted or not. FIXME: Not implemented. */ | |
8589 | case 'Q': | |
252b5132 RH |
8590 | break; |
8591 | ||
8592 | /* -V: SVR4 argument to print version ID. */ | |
8593 | case 'V': | |
8594 | print_version_id (); | |
8595 | break; | |
8596 | ||
a38cf1db AM |
8597 | /* -k: Ignore for FreeBSD compatibility. */ |
8598 | case 'k': | |
252b5132 | 8599 | break; |
4cc782b5 ILT |
8600 | |
8601 | case 's': | |
8602 | /* -s: On i386 Solaris, this tells the native assembler to use | |
29b0f896 | 8603 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
4cc782b5 | 8604 | break; |
99ad8390 | 8605 | #endif |
321098a5 | 8606 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 8607 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c JH |
8608 | case OPTION_64: |
8609 | { | |
8610 | const char **list, **l; | |
8611 | ||
3e73aa7c JH |
8612 | list = bfd_target_list (); |
8613 | for (l = list; *l != NULL; l++) | |
8620418b | 8614 | if (CONST_STRNEQ (*l, "elf64-x86-64") |
99ad8390 NC |
8615 | || strcmp (*l, "coff-x86-64") == 0 |
8616 | || strcmp (*l, "pe-x86-64") == 0 | |
d382c579 TG |
8617 | || strcmp (*l, "pei-x86-64") == 0 |
8618 | || strcmp (*l, "mach-o-x86-64") == 0) | |
6e0b89ee AM |
8619 | { |
8620 | default_arch = "x86_64"; | |
8621 | break; | |
8622 | } | |
3e73aa7c | 8623 | if (*l == NULL) |
2b5d6a91 | 8624 | as_fatal (_("no compiled in support for x86_64")); |
3e73aa7c JH |
8625 | free (list); |
8626 | } | |
8627 | break; | |
8628 | #endif | |
252b5132 | 8629 | |
351f65ca | 8630 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
570561f7 | 8631 | case OPTION_X32: |
351f65ca L |
8632 | if (IS_ELF) |
8633 | { | |
8634 | const char **list, **l; | |
8635 | ||
8636 | list = bfd_target_list (); | |
8637 | for (l = list; *l != NULL; l++) | |
8638 | if (CONST_STRNEQ (*l, "elf32-x86-64")) | |
8639 | { | |
8640 | default_arch = "x86_64:32"; | |
8641 | break; | |
8642 | } | |
8643 | if (*l == NULL) | |
2b5d6a91 | 8644 | as_fatal (_("no compiled in support for 32bit x86_64")); |
351f65ca L |
8645 | free (list); |
8646 | } | |
8647 | else | |
8648 | as_fatal (_("32bit x86_64 is only supported for ELF")); | |
8649 | break; | |
8650 | #endif | |
8651 | ||
6e0b89ee AM |
8652 | case OPTION_32: |
8653 | default_arch = "i386"; | |
8654 | break; | |
8655 | ||
b3b91714 AM |
8656 | case OPTION_DIVIDE: |
8657 | #ifdef SVR4_COMMENT_CHARS | |
8658 | { | |
8659 | char *n, *t; | |
8660 | const char *s; | |
8661 | ||
8662 | n = (char *) xmalloc (strlen (i386_comment_chars) + 1); | |
8663 | t = n; | |
8664 | for (s = i386_comment_chars; *s != '\0'; s++) | |
8665 | if (*s != '/') | |
8666 | *t++ = *s; | |
8667 | *t = '\0'; | |
8668 | i386_comment_chars = n; | |
8669 | } | |
8670 | #endif | |
8671 | break; | |
8672 | ||
9103f4f4 | 8673 | case OPTION_MARCH: |
6305a203 L |
8674 | arch = xstrdup (arg); |
8675 | do | |
9103f4f4 | 8676 | { |
6305a203 | 8677 | if (*arch == '.') |
2b5d6a91 | 8678 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
8679 | next = strchr (arch, '+'); |
8680 | if (next) | |
8681 | *next++ = '\0'; | |
91d6fa6a | 8682 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 8683 | { |
91d6fa6a | 8684 | if (strcmp (arch, cpu_arch [j].name) == 0) |
ccc9c027 | 8685 | { |
6305a203 | 8686 | /* Processor. */ |
1ded5609 JB |
8687 | if (! cpu_arch[j].flags.bitfield.cpui386) |
8688 | continue; | |
8689 | ||
91d6fa6a | 8690 | cpu_arch_name = cpu_arch[j].name; |
6305a203 | 8691 | cpu_sub_arch_name = NULL; |
91d6fa6a NC |
8692 | cpu_arch_flags = cpu_arch[j].flags; |
8693 | cpu_arch_isa = cpu_arch[j].type; | |
8694 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
6305a203 L |
8695 | if (!cpu_arch_tune_set) |
8696 | { | |
8697 | cpu_arch_tune = cpu_arch_isa; | |
8698 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
8699 | } | |
8700 | break; | |
8701 | } | |
91d6fa6a NC |
8702 | else if (*cpu_arch [j].name == '.' |
8703 | && strcmp (arch, cpu_arch [j].name + 1) == 0) | |
6305a203 L |
8704 | { |
8705 | /* ISA entension. */ | |
8706 | i386_cpu_flags flags; | |
309d3373 | 8707 | |
49021df2 | 8708 | if (!cpu_arch[j].negated) |
309d3373 | 8709 | flags = cpu_flags_or (cpu_arch_flags, |
91d6fa6a | 8710 | cpu_arch[j].flags); |
309d3373 JB |
8711 | else |
8712 | flags = cpu_flags_and_not (cpu_arch_flags, | |
49021df2 | 8713 | cpu_arch[j].flags); |
0dfbf9d7 | 8714 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
6305a203 L |
8715 | { |
8716 | if (cpu_sub_arch_name) | |
8717 | { | |
8718 | char *name = cpu_sub_arch_name; | |
8719 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 8720 | cpu_arch[j].name, |
1bf57e9f | 8721 | (const char *) NULL); |
6305a203 L |
8722 | free (name); |
8723 | } | |
8724 | else | |
91d6fa6a | 8725 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
6305a203 | 8726 | cpu_arch_flags = flags; |
a586129e | 8727 | cpu_arch_isa_flags = flags; |
6305a203 L |
8728 | } |
8729 | break; | |
ccc9c027 | 8730 | } |
9103f4f4 | 8731 | } |
6305a203 | 8732 | |
91d6fa6a | 8733 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 8734 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
8735 | |
8736 | arch = next; | |
9103f4f4 | 8737 | } |
6305a203 | 8738 | while (next != NULL ); |
9103f4f4 L |
8739 | break; |
8740 | ||
8741 | case OPTION_MTUNE: | |
8742 | if (*arg == '.') | |
2b5d6a91 | 8743 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
91d6fa6a | 8744 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 8745 | { |
91d6fa6a | 8746 | if (strcmp (arg, cpu_arch [j].name) == 0) |
9103f4f4 | 8747 | { |
ccc9c027 | 8748 | cpu_arch_tune_set = 1; |
91d6fa6a NC |
8749 | cpu_arch_tune = cpu_arch [j].type; |
8750 | cpu_arch_tune_flags = cpu_arch[j].flags; | |
9103f4f4 L |
8751 | break; |
8752 | } | |
8753 | } | |
91d6fa6a | 8754 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 8755 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
9103f4f4 L |
8756 | break; |
8757 | ||
1efbbeb4 L |
8758 | case OPTION_MMNEMONIC: |
8759 | if (strcasecmp (arg, "att") == 0) | |
8760 | intel_mnemonic = 0; | |
8761 | else if (strcasecmp (arg, "intel") == 0) | |
8762 | intel_mnemonic = 1; | |
8763 | else | |
2b5d6a91 | 8764 | as_fatal (_("invalid -mmnemonic= option: `%s'"), arg); |
1efbbeb4 L |
8765 | break; |
8766 | ||
8767 | case OPTION_MSYNTAX: | |
8768 | if (strcasecmp (arg, "att") == 0) | |
8769 | intel_syntax = 0; | |
8770 | else if (strcasecmp (arg, "intel") == 0) | |
8771 | intel_syntax = 1; | |
8772 | else | |
2b5d6a91 | 8773 | as_fatal (_("invalid -msyntax= option: `%s'"), arg); |
1efbbeb4 L |
8774 | break; |
8775 | ||
8776 | case OPTION_MINDEX_REG: | |
8777 | allow_index_reg = 1; | |
8778 | break; | |
8779 | ||
8780 | case OPTION_MNAKED_REG: | |
8781 | allow_naked_reg = 1; | |
8782 | break; | |
8783 | ||
8784 | case OPTION_MOLD_GCC: | |
8785 | old_gcc = 1; | |
1efbbeb4 L |
8786 | break; |
8787 | ||
c0f3af97 L |
8788 | case OPTION_MSSE2AVX: |
8789 | sse2avx = 1; | |
8790 | break; | |
8791 | ||
daf50ae7 L |
8792 | case OPTION_MSSE_CHECK: |
8793 | if (strcasecmp (arg, "error") == 0) | |
7bab8ab5 | 8794 | sse_check = check_error; |
daf50ae7 | 8795 | else if (strcasecmp (arg, "warning") == 0) |
7bab8ab5 | 8796 | sse_check = check_warning; |
daf50ae7 | 8797 | else if (strcasecmp (arg, "none") == 0) |
7bab8ab5 | 8798 | sse_check = check_none; |
daf50ae7 | 8799 | else |
2b5d6a91 | 8800 | as_fatal (_("invalid -msse-check= option: `%s'"), arg); |
daf50ae7 L |
8801 | break; |
8802 | ||
7bab8ab5 JB |
8803 | case OPTION_MOPERAND_CHECK: |
8804 | if (strcasecmp (arg, "error") == 0) | |
8805 | operand_check = check_error; | |
8806 | else if (strcasecmp (arg, "warning") == 0) | |
8807 | operand_check = check_warning; | |
8808 | else if (strcasecmp (arg, "none") == 0) | |
8809 | operand_check = check_none; | |
8810 | else | |
8811 | as_fatal (_("invalid -moperand-check= option: `%s'"), arg); | |
8812 | break; | |
8813 | ||
539f890d L |
8814 | case OPTION_MAVXSCALAR: |
8815 | if (strcasecmp (arg, "128") == 0) | |
8816 | avxscalar = vex128; | |
8817 | else if (strcasecmp (arg, "256") == 0) | |
8818 | avxscalar = vex256; | |
8819 | else | |
2b5d6a91 | 8820 | as_fatal (_("invalid -mavxscalar= option: `%s'"), arg); |
539f890d L |
8821 | break; |
8822 | ||
252b5132 RH |
8823 | default: |
8824 | return 0; | |
8825 | } | |
8826 | return 1; | |
8827 | } | |
8828 | ||
8a2c8fef L |
8829 | #define MESSAGE_TEMPLATE \ |
8830 | " " | |
8831 | ||
8832 | static void | |
1ded5609 | 8833 | show_arch (FILE *stream, int ext, int check) |
8a2c8fef L |
8834 | { |
8835 | static char message[] = MESSAGE_TEMPLATE; | |
8836 | char *start = message + 27; | |
8837 | char *p; | |
8838 | int size = sizeof (MESSAGE_TEMPLATE); | |
8839 | int left; | |
8840 | const char *name; | |
8841 | int len; | |
8842 | unsigned int j; | |
8843 | ||
8844 | p = start; | |
8845 | left = size - (start - message); | |
8846 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) | |
8847 | { | |
8848 | /* Should it be skipped? */ | |
8849 | if (cpu_arch [j].skip) | |
8850 | continue; | |
8851 | ||
8852 | name = cpu_arch [j].name; | |
8853 | len = cpu_arch [j].len; | |
8854 | if (*name == '.') | |
8855 | { | |
8856 | /* It is an extension. Skip if we aren't asked to show it. */ | |
8857 | if (ext) | |
8858 | { | |
8859 | name++; | |
8860 | len--; | |
8861 | } | |
8862 | else | |
8863 | continue; | |
8864 | } | |
8865 | else if (ext) | |
8866 | { | |
8867 | /* It is an processor. Skip if we show only extension. */ | |
8868 | continue; | |
8869 | } | |
1ded5609 JB |
8870 | else if (check && ! cpu_arch[j].flags.bitfield.cpui386) |
8871 | { | |
8872 | /* It is an impossible processor - skip. */ | |
8873 | continue; | |
8874 | } | |
8a2c8fef L |
8875 | |
8876 | /* Reserve 2 spaces for ", " or ",\0" */ | |
8877 | left -= len + 2; | |
8878 | ||
8879 | /* Check if there is any room. */ | |
8880 | if (left >= 0) | |
8881 | { | |
8882 | if (p != start) | |
8883 | { | |
8884 | *p++ = ','; | |
8885 | *p++ = ' '; | |
8886 | } | |
8887 | p = mempcpy (p, name, len); | |
8888 | } | |
8889 | else | |
8890 | { | |
8891 | /* Output the current message now and start a new one. */ | |
8892 | *p++ = ','; | |
8893 | *p = '\0'; | |
8894 | fprintf (stream, "%s\n", message); | |
8895 | p = start; | |
8896 | left = size - (start - message) - len - 2; | |
8d63c93e | 8897 | |
8a2c8fef L |
8898 | gas_assert (left >= 0); |
8899 | ||
8900 | p = mempcpy (p, name, len); | |
8901 | } | |
8902 | } | |
8903 | ||
8904 | *p = '\0'; | |
8905 | fprintf (stream, "%s\n", message); | |
8906 | } | |
8907 | ||
252b5132 | 8908 | void |
8a2c8fef | 8909 | md_show_usage (FILE *stream) |
252b5132 | 8910 | { |
4cc782b5 ILT |
8911 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8912 | fprintf (stream, _("\ | |
a38cf1db AM |
8913 | -Q ignored\n\ |
8914 | -V print assembler version number\n\ | |
b3b91714 AM |
8915 | -k ignored\n")); |
8916 | #endif | |
8917 | fprintf (stream, _("\ | |
12b55ccc | 8918 | -n Do not optimize code alignment\n\ |
b3b91714 AM |
8919 | -q quieten some warnings\n")); |
8920 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
8921 | fprintf (stream, _("\ | |
a38cf1db | 8922 | -s ignored\n")); |
b3b91714 | 8923 | #endif |
321098a5 L |
8924 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
8925 | || defined (TE_PE) || defined (TE_PEP)) | |
751d281c | 8926 | fprintf (stream, _("\ |
570561f7 | 8927 | --32/--64/--x32 generate 32bit/64bit/x32 code\n")); |
751d281c | 8928 | #endif |
b3b91714 AM |
8929 | #ifdef SVR4_COMMENT_CHARS |
8930 | fprintf (stream, _("\ | |
8931 | --divide do not treat `/' as a comment character\n")); | |
a38cf1db AM |
8932 | #else |
8933 | fprintf (stream, _("\ | |
b3b91714 | 8934 | --divide ignored\n")); |
4cc782b5 | 8935 | #endif |
9103f4f4 | 8936 | fprintf (stream, _("\ |
6305a203 | 8937 | -march=CPU[,+EXTENSION...]\n\ |
8a2c8fef | 8938 | generate code for CPU and EXTENSION, CPU is one of:\n")); |
1ded5609 | 8939 | show_arch (stream, 0, 1); |
8a2c8fef L |
8940 | fprintf (stream, _("\ |
8941 | EXTENSION is combination of:\n")); | |
1ded5609 | 8942 | show_arch (stream, 1, 0); |
6305a203 | 8943 | fprintf (stream, _("\ |
8a2c8fef | 8944 | -mtune=CPU optimize for CPU, CPU is one of:\n")); |
1ded5609 | 8945 | show_arch (stream, 0, 0); |
ba104c83 | 8946 | fprintf (stream, _("\ |
c0f3af97 L |
8947 | -msse2avx encode SSE instructions with VEX prefix\n")); |
8948 | fprintf (stream, _("\ | |
daf50ae7 L |
8949 | -msse-check=[none|error|warning]\n\ |
8950 | check SSE instructions\n")); | |
8951 | fprintf (stream, _("\ | |
7bab8ab5 JB |
8952 | -moperand-check=[none|error|warning]\n\ |
8953 | check operand combinations for validity\n")); | |
8954 | fprintf (stream, _("\ | |
539f890d L |
8955 | -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\ |
8956 | length\n")); | |
8957 | fprintf (stream, _("\ | |
ba104c83 L |
8958 | -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n")); |
8959 | fprintf (stream, _("\ | |
8960 | -msyntax=[att|intel] use AT&T/Intel syntax\n")); | |
8961 | fprintf (stream, _("\ | |
8962 | -mindex-reg support pseudo index registers\n")); | |
8963 | fprintf (stream, _("\ | |
8964 | -mnaked-reg don't require `%%' prefix for registers\n")); | |
8965 | fprintf (stream, _("\ | |
8966 | -mold-gcc support old (<= 2.8.1) versions of gcc\n")); | |
252b5132 RH |
8967 | } |
8968 | ||
3e73aa7c | 8969 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
321098a5 | 8970 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
e57f8c65 | 8971 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
252b5132 RH |
8972 | |
8973 | /* Pick the target format to use. */ | |
8974 | ||
47926f60 | 8975 | const char * |
e3bb37b5 | 8976 | i386_target_format (void) |
252b5132 | 8977 | { |
351f65ca L |
8978 | if (!strncmp (default_arch, "x86_64", 6)) |
8979 | { | |
8980 | update_code_flag (CODE_64BIT, 1); | |
8981 | if (default_arch[6] == '\0') | |
7f56bc95 | 8982 | x86_elf_abi = X86_64_ABI; |
351f65ca | 8983 | else |
7f56bc95 | 8984 | x86_elf_abi = X86_64_X32_ABI; |
351f65ca | 8985 | } |
3e73aa7c | 8986 | else if (!strcmp (default_arch, "i386")) |
78f12dd3 | 8987 | update_code_flag (CODE_32BIT, 1); |
3e73aa7c | 8988 | else |
2b5d6a91 | 8989 | as_fatal (_("unknown architecture")); |
89507696 JB |
8990 | |
8991 | if (cpu_flags_all_zero (&cpu_arch_isa_flags)) | |
8992 | cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
8993 | if (cpu_flags_all_zero (&cpu_arch_tune_flags)) | |
8994 | cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
8995 | ||
252b5132 RH |
8996 | switch (OUTPUT_FLAVOR) |
8997 | { | |
9384f2ff | 8998 | #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT) |
4c63da97 | 8999 | case bfd_target_aout_flavour: |
47926f60 | 9000 | return AOUT_TARGET_FORMAT; |
4c63da97 | 9001 | #endif |
9384f2ff AM |
9002 | #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF) |
9003 | # if defined (TE_PE) || defined (TE_PEP) | |
9004 | case bfd_target_coff_flavour: | |
9005 | return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386"; | |
9006 | # elif defined (TE_GO32) | |
0561d57c JK |
9007 | case bfd_target_coff_flavour: |
9008 | return "coff-go32"; | |
9384f2ff | 9009 | # else |
252b5132 RH |
9010 | case bfd_target_coff_flavour: |
9011 | return "coff-i386"; | |
9384f2ff | 9012 | # endif |
4c63da97 | 9013 | #endif |
3e73aa7c | 9014 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 9015 | case bfd_target_elf_flavour: |
3e73aa7c | 9016 | { |
351f65ca L |
9017 | const char *format; |
9018 | ||
9019 | switch (x86_elf_abi) | |
4fa24527 | 9020 | { |
351f65ca L |
9021 | default: |
9022 | format = ELF_TARGET_FORMAT; | |
9023 | break; | |
7f56bc95 | 9024 | case X86_64_ABI: |
351f65ca | 9025 | use_rela_relocations = 1; |
4fa24527 | 9026 | object_64bit = 1; |
351f65ca L |
9027 | format = ELF_TARGET_FORMAT64; |
9028 | break; | |
7f56bc95 | 9029 | case X86_64_X32_ABI: |
4fa24527 | 9030 | use_rela_relocations = 1; |
351f65ca | 9031 | object_64bit = 1; |
862be3fb | 9032 | disallow_64bit_reloc = 1; |
351f65ca L |
9033 | format = ELF_TARGET_FORMAT32; |
9034 | break; | |
4fa24527 | 9035 | } |
3632d14b | 9036 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 9037 | { |
7f56bc95 | 9038 | if (x86_elf_abi != X86_64_ABI) |
8a9036a4 L |
9039 | as_fatal (_("Intel L1OM is 64bit only")); |
9040 | return ELF_TARGET_L1OM_FORMAT; | |
9041 | } | |
7a9068fe L |
9042 | if (cpu_arch_isa == PROCESSOR_K1OM) |
9043 | { | |
9044 | if (x86_elf_abi != X86_64_ABI) | |
9045 | as_fatal (_("Intel K1OM is 64bit only")); | |
9046 | return ELF_TARGET_K1OM_FORMAT; | |
9047 | } | |
8a9036a4 | 9048 | else |
351f65ca | 9049 | return format; |
3e73aa7c | 9050 | } |
e57f8c65 TG |
9051 | #endif |
9052 | #if defined (OBJ_MACH_O) | |
9053 | case bfd_target_mach_o_flavour: | |
d382c579 TG |
9054 | if (flag_code == CODE_64BIT) |
9055 | { | |
9056 | use_rela_relocations = 1; | |
9057 | object_64bit = 1; | |
9058 | return "mach-o-x86-64"; | |
9059 | } | |
9060 | else | |
9061 | return "mach-o-i386"; | |
4c63da97 | 9062 | #endif |
252b5132 RH |
9063 | default: |
9064 | abort (); | |
9065 | return NULL; | |
9066 | } | |
9067 | } | |
9068 | ||
47926f60 | 9069 | #endif /* OBJ_MAYBE_ more than one */ |
a847613f AM |
9070 | |
9071 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) | |
e3bb37b5 L |
9072 | void |
9073 | i386_elf_emit_arch_note (void) | |
a847613f | 9074 | { |
718ddfc0 | 9075 | if (IS_ELF && cpu_arch_name != NULL) |
a847613f AM |
9076 | { |
9077 | char *p; | |
9078 | asection *seg = now_seg; | |
9079 | subsegT subseg = now_subseg; | |
9080 | Elf_Internal_Note i_note; | |
9081 | Elf_External_Note e_note; | |
9082 | asection *note_secp; | |
9083 | int len; | |
9084 | ||
9085 | /* Create the .note section. */ | |
9086 | note_secp = subseg_new (".note", 0); | |
9087 | bfd_set_section_flags (stdoutput, | |
9088 | note_secp, | |
9089 | SEC_HAS_CONTENTS | SEC_READONLY); | |
9090 | ||
9091 | /* Process the arch string. */ | |
9092 | len = strlen (cpu_arch_name); | |
9093 | ||
9094 | i_note.namesz = len + 1; | |
9095 | i_note.descsz = 0; | |
9096 | i_note.type = NT_ARCH; | |
9097 | p = frag_more (sizeof (e_note.namesz)); | |
9098 | md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz)); | |
9099 | p = frag_more (sizeof (e_note.descsz)); | |
9100 | md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz)); | |
9101 | p = frag_more (sizeof (e_note.type)); | |
9102 | md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type)); | |
9103 | p = frag_more (len + 1); | |
9104 | strcpy (p, cpu_arch_name); | |
9105 | ||
9106 | frag_align (2, 0, 0); | |
9107 | ||
9108 | subseg_set (seg, subseg); | |
9109 | } | |
9110 | } | |
9111 | #endif | |
252b5132 | 9112 | \f |
252b5132 | 9113 | symbolS * |
7016a5d5 | 9114 | md_undefined_symbol (char *name) |
252b5132 | 9115 | { |
18dc2407 ILT |
9116 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
9117 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
9118 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
9119 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
9120 | { |
9121 | if (!GOT_symbol) | |
9122 | { | |
9123 | if (symbol_find (name)) | |
9124 | as_bad (_("GOT already in symbol table")); | |
9125 | GOT_symbol = symbol_new (name, undefined_section, | |
9126 | (valueT) 0, &zero_address_frag); | |
9127 | }; | |
9128 | return GOT_symbol; | |
9129 | } | |
252b5132 RH |
9130 | return 0; |
9131 | } | |
9132 | ||
9133 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 9134 | |
252b5132 | 9135 | valueT |
7016a5d5 | 9136 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
252b5132 | 9137 | { |
4c63da97 AM |
9138 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
9139 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
9140 | { | |
9141 | /* For a.out, force the section size to be aligned. If we don't do | |
9142 | this, BFD will align it for us, but it will not write out the | |
9143 | final bytes of the section. This may be a bug in BFD, but it is | |
9144 | easier to fix it here since that is how the other a.out targets | |
9145 | work. */ | |
9146 | int align; | |
9147 | ||
9148 | align = bfd_get_section_alignment (stdoutput, segment); | |
9149 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); | |
9150 | } | |
252b5132 RH |
9151 | #endif |
9152 | ||
9153 | return size; | |
9154 | } | |
9155 | ||
9156 | /* On the i386, PC-relative offsets are relative to the start of the | |
9157 | next instruction. That is, the address of the offset, plus its | |
9158 | size, since the offset is always the last part of the insn. */ | |
9159 | ||
9160 | long | |
e3bb37b5 | 9161 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
9162 | { |
9163 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
9164 | } | |
9165 | ||
9166 | #ifndef I386COFF | |
9167 | ||
9168 | static void | |
e3bb37b5 | 9169 | s_bss (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 9170 | { |
29b0f896 | 9171 | int temp; |
252b5132 | 9172 | |
8a75718c JB |
9173 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
9174 | if (IS_ELF) | |
9175 | obj_elf_section_change_hook (); | |
9176 | #endif | |
252b5132 RH |
9177 | temp = get_absolute_expression (); |
9178 | subseg_set (bss_section, (subsegT) temp); | |
9179 | demand_empty_rest_of_line (); | |
9180 | } | |
9181 | ||
9182 | #endif | |
9183 | ||
252b5132 | 9184 | void |
e3bb37b5 | 9185 | i386_validate_fix (fixS *fixp) |
252b5132 RH |
9186 | { |
9187 | if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol) | |
9188 | { | |
23df1078 JH |
9189 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
9190 | { | |
4fa24527 | 9191 | if (!object_64bit) |
23df1078 JH |
9192 | abort (); |
9193 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
9194 | } | |
9195 | else | |
9196 | { | |
4fa24527 | 9197 | if (!object_64bit) |
d6ab8113 JB |
9198 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; |
9199 | else | |
9200 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; | |
23df1078 | 9201 | } |
252b5132 RH |
9202 | fixp->fx_subsy = 0; |
9203 | } | |
9204 | } | |
9205 | ||
252b5132 | 9206 | arelent * |
7016a5d5 | 9207 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
9208 | { |
9209 | arelent *rel; | |
9210 | bfd_reloc_code_real_type code; | |
9211 | ||
9212 | switch (fixp->fx_r_type) | |
9213 | { | |
3e73aa7c JH |
9214 | case BFD_RELOC_X86_64_PLT32: |
9215 | case BFD_RELOC_X86_64_GOT32: | |
9216 | case BFD_RELOC_X86_64_GOTPCREL: | |
252b5132 RH |
9217 | case BFD_RELOC_386_PLT32: |
9218 | case BFD_RELOC_386_GOT32: | |
9219 | case BFD_RELOC_386_GOTOFF: | |
9220 | case BFD_RELOC_386_GOTPC: | |
13ae64f3 JJ |
9221 | case BFD_RELOC_386_TLS_GD: |
9222 | case BFD_RELOC_386_TLS_LDM: | |
9223 | case BFD_RELOC_386_TLS_LDO_32: | |
9224 | case BFD_RELOC_386_TLS_IE_32: | |
37e55690 JJ |
9225 | case BFD_RELOC_386_TLS_IE: |
9226 | case BFD_RELOC_386_TLS_GOTIE: | |
13ae64f3 JJ |
9227 | case BFD_RELOC_386_TLS_LE_32: |
9228 | case BFD_RELOC_386_TLS_LE: | |
67a4f2b7 AO |
9229 | case BFD_RELOC_386_TLS_GOTDESC: |
9230 | case BFD_RELOC_386_TLS_DESC_CALL: | |
bffbf940 JJ |
9231 | case BFD_RELOC_X86_64_TLSGD: |
9232 | case BFD_RELOC_X86_64_TLSLD: | |
9233 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 9234 | case BFD_RELOC_X86_64_DTPOFF64: |
bffbf940 JJ |
9235 | case BFD_RELOC_X86_64_GOTTPOFF: |
9236 | case BFD_RELOC_X86_64_TPOFF32: | |
d6ab8113 JB |
9237 | case BFD_RELOC_X86_64_TPOFF64: |
9238 | case BFD_RELOC_X86_64_GOTOFF64: | |
9239 | case BFD_RELOC_X86_64_GOTPC32: | |
7b81dfbb AJ |
9240 | case BFD_RELOC_X86_64_GOT64: |
9241 | case BFD_RELOC_X86_64_GOTPCREL64: | |
9242 | case BFD_RELOC_X86_64_GOTPC64: | |
9243 | case BFD_RELOC_X86_64_GOTPLT64: | |
9244 | case BFD_RELOC_X86_64_PLTOFF64: | |
67a4f2b7 AO |
9245 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
9246 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
252b5132 RH |
9247 | case BFD_RELOC_RVA: |
9248 | case BFD_RELOC_VTABLE_ENTRY: | |
9249 | case BFD_RELOC_VTABLE_INHERIT: | |
6482c264 NC |
9250 | #ifdef TE_PE |
9251 | case BFD_RELOC_32_SECREL: | |
9252 | #endif | |
252b5132 RH |
9253 | code = fixp->fx_r_type; |
9254 | break; | |
dbbaec26 L |
9255 | case BFD_RELOC_X86_64_32S: |
9256 | if (!fixp->fx_pcrel) | |
9257 | { | |
9258 | /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ | |
9259 | code = fixp->fx_r_type; | |
9260 | break; | |
9261 | } | |
252b5132 | 9262 | default: |
93382f6d | 9263 | if (fixp->fx_pcrel) |
252b5132 | 9264 | { |
93382f6d AM |
9265 | switch (fixp->fx_size) |
9266 | { | |
9267 | default: | |
b091f402 AM |
9268 | as_bad_where (fixp->fx_file, fixp->fx_line, |
9269 | _("can not do %d byte pc-relative relocation"), | |
9270 | fixp->fx_size); | |
93382f6d AM |
9271 | code = BFD_RELOC_32_PCREL; |
9272 | break; | |
9273 | case 1: code = BFD_RELOC_8_PCREL; break; | |
9274 | case 2: code = BFD_RELOC_16_PCREL; break; | |
9275 | case 4: code = BFD_RELOC_32_PCREL; break; | |
d6ab8113 JB |
9276 | #ifdef BFD64 |
9277 | case 8: code = BFD_RELOC_64_PCREL; break; | |
9278 | #endif | |
93382f6d AM |
9279 | } |
9280 | } | |
9281 | else | |
9282 | { | |
9283 | switch (fixp->fx_size) | |
9284 | { | |
9285 | default: | |
b091f402 AM |
9286 | as_bad_where (fixp->fx_file, fixp->fx_line, |
9287 | _("can not do %d byte relocation"), | |
9288 | fixp->fx_size); | |
93382f6d AM |
9289 | code = BFD_RELOC_32; |
9290 | break; | |
9291 | case 1: code = BFD_RELOC_8; break; | |
9292 | case 2: code = BFD_RELOC_16; break; | |
9293 | case 4: code = BFD_RELOC_32; break; | |
937149dd | 9294 | #ifdef BFD64 |
3e73aa7c | 9295 | case 8: code = BFD_RELOC_64; break; |
937149dd | 9296 | #endif |
93382f6d | 9297 | } |
252b5132 RH |
9298 | } |
9299 | break; | |
9300 | } | |
252b5132 | 9301 | |
d182319b JB |
9302 | if ((code == BFD_RELOC_32 |
9303 | || code == BFD_RELOC_32_PCREL | |
9304 | || code == BFD_RELOC_X86_64_32S) | |
252b5132 RH |
9305 | && GOT_symbol |
9306 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c | 9307 | { |
4fa24527 | 9308 | if (!object_64bit) |
d6ab8113 JB |
9309 | code = BFD_RELOC_386_GOTPC; |
9310 | else | |
9311 | code = BFD_RELOC_X86_64_GOTPC32; | |
3e73aa7c | 9312 | } |
7b81dfbb AJ |
9313 | if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) |
9314 | && GOT_symbol | |
9315 | && fixp->fx_addsy == GOT_symbol) | |
9316 | { | |
9317 | code = BFD_RELOC_X86_64_GOTPC64; | |
9318 | } | |
252b5132 RH |
9319 | |
9320 | rel = (arelent *) xmalloc (sizeof (arelent)); | |
49309057 ILT |
9321 | rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
9322 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
9323 | |
9324 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
c87db184 | 9325 | |
3e73aa7c JH |
9326 | if (!use_rela_relocations) |
9327 | { | |
9328 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
9329 | vtable entry to be used in the relocation's section offset. */ | |
9330 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
9331 | rel->address = fixp->fx_offset; | |
fbeb56a4 DK |
9332 | #if defined (OBJ_COFF) && defined (TE_PE) |
9333 | else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy)) | |
9334 | rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2); | |
9335 | else | |
9336 | #endif | |
c6682705 | 9337 | rel->addend = 0; |
3e73aa7c JH |
9338 | } |
9339 | /* Use the rela in 64bit mode. */ | |
252b5132 | 9340 | else |
3e73aa7c | 9341 | { |
862be3fb L |
9342 | if (disallow_64bit_reloc) |
9343 | switch (code) | |
9344 | { | |
862be3fb L |
9345 | case BFD_RELOC_X86_64_DTPOFF64: |
9346 | case BFD_RELOC_X86_64_TPOFF64: | |
9347 | case BFD_RELOC_64_PCREL: | |
9348 | case BFD_RELOC_X86_64_GOTOFF64: | |
9349 | case BFD_RELOC_X86_64_GOT64: | |
9350 | case BFD_RELOC_X86_64_GOTPCREL64: | |
9351 | case BFD_RELOC_X86_64_GOTPC64: | |
9352 | case BFD_RELOC_X86_64_GOTPLT64: | |
9353 | case BFD_RELOC_X86_64_PLTOFF64: | |
9354 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
9355 | _("cannot represent relocation type %s in x32 mode"), | |
9356 | bfd_get_reloc_code_name (code)); | |
9357 | break; | |
9358 | default: | |
9359 | break; | |
9360 | } | |
9361 | ||
062cd5e7 AS |
9362 | if (!fixp->fx_pcrel) |
9363 | rel->addend = fixp->fx_offset; | |
9364 | else | |
9365 | switch (code) | |
9366 | { | |
9367 | case BFD_RELOC_X86_64_PLT32: | |
9368 | case BFD_RELOC_X86_64_GOT32: | |
9369 | case BFD_RELOC_X86_64_GOTPCREL: | |
bffbf940 JJ |
9370 | case BFD_RELOC_X86_64_TLSGD: |
9371 | case BFD_RELOC_X86_64_TLSLD: | |
9372 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 AO |
9373 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
9374 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
062cd5e7 AS |
9375 | rel->addend = fixp->fx_offset - fixp->fx_size; |
9376 | break; | |
9377 | default: | |
9378 | rel->addend = (section->vma | |
9379 | - fixp->fx_size | |
9380 | + fixp->fx_addnumber | |
9381 | + md_pcrel_from (fixp)); | |
9382 | break; | |
9383 | } | |
3e73aa7c JH |
9384 | } |
9385 | ||
252b5132 RH |
9386 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
9387 | if (rel->howto == NULL) | |
9388 | { | |
9389 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 9390 | _("cannot represent relocation type %s"), |
252b5132 RH |
9391 | bfd_get_reloc_code_name (code)); |
9392 | /* Set howto to a garbage value so that we can keep going. */ | |
9393 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
9c2799c2 | 9394 | gas_assert (rel->howto != NULL); |
252b5132 RH |
9395 | } |
9396 | ||
9397 | return rel; | |
9398 | } | |
9399 | ||
ee86248c | 9400 | #include "tc-i386-intel.c" |
54cfded0 | 9401 | |
a60de03c JB |
9402 | void |
9403 | tc_x86_parse_to_dw2regnum (expressionS *exp) | |
54cfded0 | 9404 | { |
a60de03c JB |
9405 | int saved_naked_reg; |
9406 | char saved_register_dot; | |
54cfded0 | 9407 | |
a60de03c JB |
9408 | saved_naked_reg = allow_naked_reg; |
9409 | allow_naked_reg = 1; | |
9410 | saved_register_dot = register_chars['.']; | |
9411 | register_chars['.'] = '.'; | |
9412 | allow_pseudo_reg = 1; | |
9413 | expression_and_evaluate (exp); | |
9414 | allow_pseudo_reg = 0; | |
9415 | register_chars['.'] = saved_register_dot; | |
9416 | allow_naked_reg = saved_naked_reg; | |
9417 | ||
e96d56a1 | 9418 | if (exp->X_op == O_register && exp->X_add_number >= 0) |
54cfded0 | 9419 | { |
a60de03c JB |
9420 | if ((addressT) exp->X_add_number < i386_regtab_size) |
9421 | { | |
9422 | exp->X_op = O_constant; | |
9423 | exp->X_add_number = i386_regtab[exp->X_add_number] | |
9424 | .dw2_regnum[flag_code >> 1]; | |
9425 | } | |
9426 | else | |
9427 | exp->X_op = O_illegal; | |
54cfded0 | 9428 | } |
54cfded0 AM |
9429 | } |
9430 | ||
9431 | void | |
9432 | tc_x86_frame_initial_instructions (void) | |
9433 | { | |
a60de03c JB |
9434 | static unsigned int sp_regno[2]; |
9435 | ||
9436 | if (!sp_regno[flag_code >> 1]) | |
9437 | { | |
9438 | char *saved_input = input_line_pointer; | |
9439 | char sp[][4] = {"esp", "rsp"}; | |
9440 | expressionS exp; | |
a4447b93 | 9441 | |
a60de03c JB |
9442 | input_line_pointer = sp[flag_code >> 1]; |
9443 | tc_x86_parse_to_dw2regnum (&exp); | |
9c2799c2 | 9444 | gas_assert (exp.X_op == O_constant); |
a60de03c JB |
9445 | sp_regno[flag_code >> 1] = exp.X_add_number; |
9446 | input_line_pointer = saved_input; | |
9447 | } | |
a4447b93 | 9448 | |
61ff971f L |
9449 | cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment); |
9450 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); | |
54cfded0 | 9451 | } |
d2b2c203 | 9452 | |
d7921315 L |
9453 | int |
9454 | x86_dwarf2_addr_size (void) | |
9455 | { | |
9456 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) | |
9457 | if (x86_elf_abi == X86_64_X32_ABI) | |
9458 | return 4; | |
9459 | #endif | |
9460 | return bfd_arch_bits_per_address (stdoutput) / 8; | |
9461 | } | |
9462 | ||
d2b2c203 DJ |
9463 | int |
9464 | i386_elf_section_type (const char *str, size_t len) | |
9465 | { | |
9466 | if (flag_code == CODE_64BIT | |
9467 | && len == sizeof ("unwind") - 1 | |
9468 | && strncmp (str, "unwind", 6) == 0) | |
9469 | return SHT_X86_64_UNWIND; | |
9470 | ||
9471 | return -1; | |
9472 | } | |
bb41ade5 | 9473 | |
ad5fec3b EB |
9474 | #ifdef TE_SOLARIS |
9475 | void | |
9476 | i386_solaris_fix_up_eh_frame (segT sec) | |
9477 | { | |
9478 | if (flag_code == CODE_64BIT) | |
9479 | elf_section_type (sec) = SHT_X86_64_UNWIND; | |
9480 | } | |
9481 | #endif | |
9482 | ||
bb41ade5 AM |
9483 | #ifdef TE_PE |
9484 | void | |
9485 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) | |
9486 | { | |
91d6fa6a | 9487 | expressionS exp; |
bb41ade5 | 9488 | |
91d6fa6a NC |
9489 | exp.X_op = O_secrel; |
9490 | exp.X_add_symbol = symbol; | |
9491 | exp.X_add_number = 0; | |
9492 | emit_expr (&exp, size); | |
bb41ade5 AM |
9493 | } |
9494 | #endif | |
3b22753a L |
9495 | |
9496 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
9497 | /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ | |
9498 | ||
01e1a5bc | 9499 | bfd_vma |
3b22753a L |
9500 | x86_64_section_letter (int letter, char **ptr_msg) |
9501 | { | |
9502 | if (flag_code == CODE_64BIT) | |
9503 | { | |
9504 | if (letter == 'l') | |
9505 | return SHF_X86_64_LARGE; | |
9506 | ||
8f3bae45 | 9507 | *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string"); |
64e74474 | 9508 | } |
3b22753a | 9509 | else |
8f3bae45 | 9510 | *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string"); |
3b22753a L |
9511 | return -1; |
9512 | } | |
9513 | ||
01e1a5bc | 9514 | bfd_vma |
3b22753a L |
9515 | x86_64_section_word (char *str, size_t len) |
9516 | { | |
8620418b | 9517 | if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large")) |
3b22753a L |
9518 | return SHF_X86_64_LARGE; |
9519 | ||
9520 | return -1; | |
9521 | } | |
9522 | ||
9523 | static void | |
9524 | handle_large_common (int small ATTRIBUTE_UNUSED) | |
9525 | { | |
9526 | if (flag_code != CODE_64BIT) | |
9527 | { | |
9528 | s_comm_internal (0, elf_common_parse); | |
9529 | as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); | |
9530 | } | |
9531 | else | |
9532 | { | |
9533 | static segT lbss_section; | |
9534 | asection *saved_com_section_ptr = elf_com_section_ptr; | |
9535 | asection *saved_bss_section = bss_section; | |
9536 | ||
9537 | if (lbss_section == NULL) | |
9538 | { | |
9539 | flagword applicable; | |
9540 | segT seg = now_seg; | |
9541 | subsegT subseg = now_subseg; | |
9542 | ||
9543 | /* The .lbss section is for local .largecomm symbols. */ | |
9544 | lbss_section = subseg_new (".lbss", 0); | |
9545 | applicable = bfd_applicable_section_flags (stdoutput); | |
9546 | bfd_set_section_flags (stdoutput, lbss_section, | |
9547 | applicable & SEC_ALLOC); | |
9548 | seg_info (lbss_section)->bss = 1; | |
9549 | ||
9550 | subseg_set (seg, subseg); | |
9551 | } | |
9552 | ||
9553 | elf_com_section_ptr = &_bfd_elf_large_com_section; | |
9554 | bss_section = lbss_section; | |
9555 | ||
9556 | s_comm_internal (0, elf_common_parse); | |
9557 | ||
9558 | elf_com_section_ptr = saved_com_section_ptr; | |
9559 | bss_section = saved_bss_section; | |
9560 | } | |
9561 | } | |
9562 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |