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[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
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b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4dc85607 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
252b5132 36
252b5132
RH		 37#ifndef REGISTER_WARNINGS
38#define REGISTER_WARNINGS 1
39#endif
40
c3332e24 41#ifndef INFER_ADDR_PREFIX
eecb386c 42#define INFER_ADDR_PREFIX 1
c3332e24
AM		 43#endif
44
252b5132
RH		 45#ifndef SCALE1_WHEN_NO_INDEX
46/* Specifying a scale factor besides 1 when there is no index is
47 futile. eg. `mov (%ebx,2),%al' does exactly the same as
48 `mov (%ebx),%al'. To slavishly follow what the programmer
49 specified, set SCALE1_WHEN_NO_INDEX to 0. */
50#define SCALE1_WHEN_NO_INDEX 1
51#endif
52
29b0f896
AM		 53#ifndef DEFAULT_ARCH
54#define DEFAULT_ARCH "i386"
246fcdee 55#endif
252b5132 56
edde18a5
AM		 57#ifndef INLINE
58#if __GNUC__ >= 2
59#define INLINE __inline__
60#else
61#define INLINE
62#endif
63#endif
64
e3bb37b5
L		 65static void set_code_flag (int);
66static void set_16bit_gcc_code_flag (int);
67static void set_intel_syntax (int);
68static void set_cpu_arch (int);
6482c264 69#ifdef TE_PE
e3bb37b5 70static void pe_directive_secrel (int);
6482c264 71#endif
e3bb37b5
L		 72static void signed_cons (int);
73static char *output_invalid (int c);
74static int i386_operand (char *);
75static int i386_intel_operand (char *, int);
76static const reg_entry *parse_register (char *, char **);
77static char *parse_insn (char *, char *);
78static char *parse_operands (char *, const char *);
79static void swap_operands (void);
4d456e3d 80static void swap_2_operands (int, int);
e3bb37b5
L		 81static void optimize_imm (void);
82static void optimize_disp (void);
83static int match_template (void);
84static int check_string (void);
85static int process_suffix (void);
86static int check_byte_reg (void);
87static int check_long_reg (void);
88static int check_qword_reg (void);
89static int check_word_reg (void);
90static int finalize_imm (void);
91static int process_operands (void);
92static const seg_entry *build_modrm_byte (void);
93static void output_insn (void);
94static void output_imm (fragS *, offsetT);
95static void output_disp (fragS *, offsetT);
29b0f896 96#ifndef I386COFF
e3bb37b5 97static void s_bss (int);
252b5132 98#endif
17d4e2a2
L		 99#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
100static void handle_large_common (int small ATTRIBUTE_UNUSED);
101#endif
252b5132 102
a847613f 103static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 104
252b5132 105/* 'md_assemble ()' gathers together information and puts it into a
47926f60 106 i386_insn. */
252b5132 107
520dc8e8
AM		 108union i386_op
109 {
110 expressionS *disps;
111 expressionS *imms;
112 const reg_entry *regs;
113 };
114
252b5132
RH		 115struct _i386_insn
116 {
47926f60 117 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 118 template tm;
119
120 /* SUFFIX holds the instruction mnemonic suffix if given.
121 (e.g. 'l' for 'movl') */
122 char suffix;
123
47926f60 124 /* OPERANDS gives the number of given operands. */
252b5132
RH		 125 unsigned int operands;
126
127 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
128 of given register, displacement, memory operands and immediate
47926f60 129 operands. */
252b5132
RH		 130 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
131
132 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 133 use OP[i] for the corresponding operand. */
252b5132
RH		 134 unsigned int types[MAX_OPERANDS];
135
520dc8e8
AM		 136 /* Displacement expression, immediate expression, or register for each
137 operand. */
138 union i386_op op[MAX_OPERANDS];
252b5132 139
3e73aa7c
JH		 140 /* Flags for operands. */
141 unsigned int flags[MAX_OPERANDS];
142#define Operand_PCrel 1
143
252b5132 144 /* Relocation type for operand */
f86103b7 145 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 146
252b5132
RH		 147 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
148 the base index byte below. */
149 const reg_entry *base_reg;
150 const reg_entry *index_reg;
151 unsigned int log2_scale_factor;
152
153 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 154 explicit segment overrides are given. */
ce8a8b2f 155 const seg_entry *seg[2];
252b5132
RH		 156
157 /* PREFIX holds all the given prefix opcodes (usually null).
158 PREFIXES is the number of prefix opcodes. */
159 unsigned int prefixes;
160 unsigned char prefix[MAX_PREFIXES];
161
162 /* RM and SIB are the modrm byte and the sib byte where the
163 addressing modes of this insn are encoded. */
164
165 modrm_byte rm;
3e73aa7c 166 rex_byte rex;
252b5132
RH		 167 sib_byte sib;
168 };
169
170typedef struct _i386_insn i386_insn;
171
172/* List of chars besides those in app.c:symbol_chars that can start an
173 operand. Used to prevent the scrubber eating vital white-space. */
32137342 174const char extra_symbol_chars[] = "*%-(["
252b5132 175#ifdef LEX_AT
32137342
NC		 176 "@"
177#endif
178#ifdef LEX_QM
179 "?"
252b5132 180#endif
32137342 181 ;
252b5132 182
29b0f896
AM		 183#if (defined (TE_I386AIX) \
184 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 185 && !defined (TE_GNU) \
29b0f896 186 && !defined (TE_LINUX) \
32137342 187 && !defined (TE_NETWARE) \
29b0f896
AM		 188 && !defined (TE_FreeBSD) \
189 && !defined (TE_NetBSD)))
252b5132 190/* This array holds the chars that always start a comment. If the
b3b91714
AM		 191 pre-processor is disabled, these aren't very useful. The option
192 --divide will remove '/' from this list. */
193const char *i386_comment_chars = "#/";
194#define SVR4_COMMENT_CHARS 1
252b5132 195#define PREFIX_SEPARATOR '\\'
252b5132 196
b3b91714
AM		 197#else
198const char *i386_comment_chars = "#";
199#define PREFIX_SEPARATOR '/'
200#endif
201
252b5132
RH		 202/* This array holds the chars that only start a comment at the beginning of
203 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 204 .line and .file directives will appear in the pre-processed output.
205 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 206 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 207 #NO_APP at the beginning of its output.
208 Also note that comments started like this one will always work if
252b5132 209 '/' isn't otherwise defined. */
b3b91714 210const char line_comment_chars[] = "#/";
252b5132 211
63a0b638 212const char line_separator_chars[] = ";";
252b5132 213
ce8a8b2f
AM		 214/* Chars that can be used to separate mant from exp in floating point
215 nums. */
252b5132
RH		 216const char EXP_CHARS[] = "eE";
217
ce8a8b2f
AM		 218/* Chars that mean this number is a floating point constant
219 As in 0f12.456
220 or 0d1.2345e12. */
252b5132
RH		 221const char FLT_CHARS[] = "fFdDxX";
222
ce8a8b2f 223/* Tables for lexical analysis. */
252b5132
RH		 224static char mnemonic_chars[256];
225static char register_chars[256];
226static char operand_chars[256];
227static char identifier_chars[256];
228static char digit_chars[256];
229
ce8a8b2f 230/* Lexical macros. */
252b5132
RH		 231#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
232#define is_operand_char(x) (operand_chars[(unsigned char) x])
233#define is_register_char(x) (register_chars[(unsigned char) x])
234#define is_space_char(x) ((x) == ' ')
235#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
236#define is_digit_char(x) (digit_chars[(unsigned char) x])
237
0234cb7c 238/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 239static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
240
241/* md_assemble() always leaves the strings it's passed unaltered. To
242 effect this we maintain a stack of saved characters that we've smashed
243 with '\0's (indicating end of strings for various sub-fields of the
47926f60 244 assembler instruction). */
252b5132 245static char save_stack[32];
ce8a8b2f 246static char *save_stack_p;
252b5132
RH		 247#define END_STRING_AND_SAVE(s) \
248 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
249#define RESTORE_END_STRING(s) \
250 do { *(s) = *--save_stack_p; } while (0)
251
47926f60 252/* The instruction we're assembling. */
252b5132
RH		 253static i386_insn i;
254
255/* Possible templates for current insn. */
256static const templates *current_templates;
257
31b2323c
L		 258/* Per instruction expressionS buffers: max displacements & immediates. */
259static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
260static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 261
47926f60
KH		 262/* Current operand we are working on. */
263static int this_operand;
252b5132 264
3e73aa7c
JH		 265/* We support four different modes. FLAG_CODE variable is used to distinguish
266 these. */
267
268enum flag_code {
269 CODE_32BIT,
270 CODE_16BIT,
271 CODE_64BIT };
f3c180ae 272#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 273
274static enum flag_code flag_code;
4fa24527 275static unsigned int object_64bit;
3e73aa7c
JH		 276static int use_rela_relocations = 0;
277
278/* The names used to print error messages. */
b77a7acd 279static const char *flag_code_names[] =
3e73aa7c
JH		 280 {
281 "32",
282 "16",
283 "64"
284 };
252b5132 285
47926f60
KH		 286/* 1 for intel syntax,
287 0 if att syntax. */
288static int intel_syntax = 0;
252b5132 289
47926f60
KH		 290/* 1 if register prefix % not required. */
291static int allow_naked_reg = 0;
252b5132 292
2ca3ace5
L		 293/* Register prefix used for error message. */
294static const char *register_prefix = "%";
295
47926f60
KH		 296/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
297 leave, push, and pop instructions so that gcc has the same stack
298 frame as in 32 bit mode. */
299static char stackop_size = '\0';
eecb386c 300
12b55ccc
L		 301/* Non-zero to optimize code alignment. */
302int optimize_align_code = 1;
303
47926f60
KH		 304/* Non-zero to quieten some warnings. */
305static int quiet_warnings = 0;
a38cf1db 306
47926f60
KH		 307/* CPU name. */
308static const char *cpu_arch_name = NULL;
5c6af06e 309static const char *cpu_sub_arch_name = NULL;
a38cf1db 310
47926f60 311/* CPU feature flags. */
29b0f896 312static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 313
ccc9c027
L		 314/* If we have selected a cpu we are generating instructions for. */
315static int cpu_arch_tune_set = 0;
316
9103f4f4
L		 317/* Cpu we are generating instructions for. */
318static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
319
320/* CPU feature flags of cpu we are generating instructions for. */
321static unsigned int cpu_arch_tune_flags = 0;
322
ccc9c027
L		 323/* CPU instruction set architecture used. */
324static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
325
9103f4f4
L		 326/* CPU feature flags of instruction set architecture used. */
327static unsigned int cpu_arch_isa_flags = 0;
328
fddf5b5b
AM		 329/* If set, conditional jumps are not automatically promoted to handle
330 larger than a byte offset. */
331static unsigned int no_cond_jump_promotion = 0;
332
29b0f896 333/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 334static symbolS *GOT_symbol;
29b0f896 335
a4447b93
RH		 336/* The dwarf2 return column, adjusted for 32 or 64 bit. */
337unsigned int x86_dwarf2_return_column;
338
339/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
340int x86_cie_data_alignment;
341
252b5132 342/* Interface to relax_segment.
fddf5b5b
AM		 343 There are 3 major relax states for 386 jump insns because the
344 different types of jumps add different sizes to frags when we're
345 figuring out what sort of jump to choose to reach a given label. */
252b5132 346
47926f60 347/* Types. */
93c2a809
AM		 348#define UNCOND_JUMP 0
349#define COND_JUMP 1
350#define COND_JUMP86 2
fddf5b5b 351
47926f60 352/* Sizes. */
252b5132
RH		 353#define CODE16 1
354#define SMALL 0
29b0f896 355#define SMALL16 (SMALL | CODE16)
252b5132 356#define BIG 2
29b0f896 357#define BIG16 (BIG | CODE16)
252b5132
RH		 358
359#ifndef INLINE
360#ifdef __GNUC__
361#define INLINE __inline__
362#else
363#define INLINE
364#endif
365#endif
366
fddf5b5b
AM		 367#define ENCODE_RELAX_STATE(type, size) \
368 ((relax_substateT) (((type) << 2) | (size)))
369#define TYPE_FROM_RELAX_STATE(s) \
370 ((s) >> 2)
371#define DISP_SIZE_FROM_RELAX_STATE(s) \
372 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 373
374/* This table is used by relax_frag to promote short jumps to long
375 ones where necessary. SMALL (short) jumps may be promoted to BIG
376 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
377 don't allow a short jump in a 32 bit code segment to be promoted to
378 a 16 bit offset jump because it's slower (requires data size
379 prefix), and doesn't work, unless the destination is in the bottom
380 64k of the code segment (The top 16 bits of eip are zeroed). */
381
382const relax_typeS md_relax_table[] =
383{
24eab124
AM		 384 /* The fields are:
385 1) most positive reach of this state,
386 2) most negative reach of this state,
93c2a809 387 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 388 4) which index into the table to try if we can't fit into this one. */
252b5132 389
fddf5b5b 390 /* UNCOND_JUMP states. */
93c2a809
AM		 391 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
392 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
393 /* dword jmp adds 4 bytes to frag:
394 0 extra opcode bytes, 4 displacement bytes. */
252b5132 395 {0, 0, 4, 0},
93c2a809
AM		 396 /* word jmp adds 2 byte2 to frag:
397 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 398 {0, 0, 2, 0},
399
93c2a809
AM		 400 /* COND_JUMP states. */
401 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
402 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
403 /* dword conditionals adds 5 bytes to frag:
404 1 extra opcode byte, 4 displacement bytes. */
405 {0, 0, 5, 0},
fddf5b5b 406 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 407 1 extra opcode byte, 2 displacement bytes. */
408 {0, 0, 3, 0},
409
410 /* COND_JUMP86 states. */
411 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
412 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
413 /* dword conditionals adds 5 bytes to frag:
414 1 extra opcode byte, 4 displacement bytes. */
415 {0, 0, 5, 0},
416 /* word conditionals add 4 bytes to frag:
417 1 displacement byte and a 3 byte long branch insn. */
418 {0, 0, 4, 0}
252b5132
RH		 419};
420
9103f4f4
L		 421static const arch_entry cpu_arch[] =
422{
423 {"generic32", PROCESSOR_GENERIC32,
d32cad65 424 Cpu186|Cpu286|Cpu386},
9103f4f4 425 {"generic64", PROCESSOR_GENERIC64,
d32cad65 426 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 427 |CpuMMX2|CpuSSE|CpuSSE2},
428 {"i8086", PROCESSOR_UNKNOWN,
d32cad65 429 0},
9103f4f4 430 {"i186", PROCESSOR_UNKNOWN,
d32cad65 431 Cpu186},
9103f4f4 432 {"i286", PROCESSOR_UNKNOWN,
d32cad65 433 Cpu186|Cpu286},
9103f4f4 434 {"i386", PROCESSOR_GENERIC32,
d32cad65 435 Cpu186|Cpu286|Cpu386},
9103f4f4 436 {"i486", PROCESSOR_I486,
d32cad65 437 Cpu186|Cpu286|Cpu386|Cpu486},
9103f4f4 438 {"i586", PROCESSOR_PENTIUM,
d32cad65 439 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 440 {"i686", PROCESSOR_PENTIUMPRO,
d32cad65 441 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 442 {"pentium", PROCESSOR_PENTIUM,
d32cad65 443 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
9103f4f4 444 {"pentiumpro",PROCESSOR_PENTIUMPRO,
d32cad65 445 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
9103f4f4 446 {"pentiumii", PROCESSOR_PENTIUMPRO,
d32cad65 447 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX},
9103f4f4 448 {"pentiumiii",PROCESSOR_PENTIUMPRO,
d32cad65 449 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE},
9103f4f4 450 {"pentium4", PROCESSOR_PENTIUM4,
d32cad65 451 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 452 |CpuMMX2|CpuSSE|CpuSSE2},
453 {"prescott", PROCESSOR_NOCONA,
d32cad65 454 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4
L		 455 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
456 {"nocona", PROCESSOR_NOCONA,
d32cad65 457 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4 458 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495 459 {"yonah", PROCESSOR_CORE,
d32cad65 460 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
9103f4f4 461 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495 462 {"core", PROCESSOR_CORE,
d32cad65 463 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
ef05d495
L		 464 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
465 {"merom", PROCESSOR_CORE2,
466 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
467 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
468 {"core2", PROCESSOR_CORE2,
469 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
470 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
9103f4f4 471 {"k6", PROCESSOR_K6,
d32cad65 472 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX},
9103f4f4 473 {"k6_2", PROCESSOR_K6,
d32cad65 474 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow},
9103f4f4 475 {"athlon", PROCESSOR_ATHLON,
d32cad65 476 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 477 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
478 {"sledgehammer", PROCESSOR_K8,
d32cad65 479 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 480 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
481 {"opteron", PROCESSOR_K8,
d32cad65 482 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4
L		 483 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
484 {"k8", PROCESSOR_K8,
d32cad65 485 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6
9103f4f4 486 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
050dfa73 487 {"amdfam10", PROCESSOR_AMDFAM10,
d32cad65
L		 488 Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuSledgehammer
489 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a
490 |CpuABM},
9103f4f4
L		 491 {".mmx", PROCESSOR_UNKNOWN,
492 CpuMMX},
493 {".sse", PROCESSOR_UNKNOWN,
494 CpuMMX|CpuMMX2|CpuSSE},
495 {".sse2", PROCESSOR_UNKNOWN,
496 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2},
497 {".sse3", PROCESSOR_UNKNOWN,
498 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
ef05d495
L		 499 {".ssse3", PROCESSOR_UNKNOWN,
500 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3},
42903f7f
L		 501 {".sse4.1", PROCESSOR_UNKNOWN,
502 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1},
381d071f
L		 503 {".sse4.2", PROCESSOR_UNKNOWN,
504 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4},
505 {".sse4", PROCESSOR_UNKNOWN,
506 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4},
9103f4f4
L		 507 {".3dnow", PROCESSOR_UNKNOWN,
508 CpuMMX|Cpu3dnow},
509 {".3dnowa", PROCESSOR_UNKNOWN,
510 CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
511 {".padlock", PROCESSOR_UNKNOWN,
512 CpuPadLock},
513 {".pacifica", PROCESSOR_UNKNOWN,
514 CpuSVME},
515 {".svme", PROCESSOR_UNKNOWN,
050dfa73
MM		 516 CpuSVME},
517 {".sse4a", PROCESSOR_UNKNOWN,
518 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a},
519 {".abm", PROCESSOR_UNKNOWN,
520 CpuABM}
e413e4e9
AM		 521};
522
29b0f896
AM		 523const pseudo_typeS md_pseudo_table[] =
524{
525#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
526 {"align", s_align_bytes, 0},
527#else
528 {"align", s_align_ptwo, 0},
529#endif
530 {"arch", set_cpu_arch, 0},
531#ifndef I386COFF
532 {"bss", s_bss, 0},
533#endif
534 {"ffloat", float_cons, 'f'},
535 {"dfloat", float_cons, 'd'},
536 {"tfloat", float_cons, 'x'},
537 {"value", cons, 2},
d182319b 538 {"slong", signed_cons, 4},
29b0f896
AM		 539 {"noopt", s_ignore, 0},
540 {"optim", s_ignore, 0},
541 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
542 {"code16", set_code_flag, CODE_16BIT},
543 {"code32", set_code_flag, CODE_32BIT},
544 {"code64", set_code_flag, CODE_64BIT},
545 {"intel_syntax", set_intel_syntax, 1},
546 {"att_syntax", set_intel_syntax, 0},
3b22753a
L		 547#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
548 {"largecomm", handle_large_common, 0},
07a53e5c 549#else
e3bb37b5 550 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 551 {"loc", dwarf2_directive_loc, 0},
552 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 553#endif
6482c264
NC		 554#ifdef TE_PE
555 {"secrel32", pe_directive_secrel, 0},
556#endif
29b0f896
AM		 557 {0, 0, 0}
558};
559
560/* For interface with expression (). */
561extern char *input_line_pointer;
562
563/* Hash table for instruction mnemonic lookup. */
564static struct hash_control *op_hash;
565
566/* Hash table for register lookup. */
567static struct hash_control *reg_hash;
568\f
252b5132 569void
e3bb37b5 570i386_align_code (fragS *fragP, int count)
252b5132 571{
ce8a8b2f
AM		 572 /* Various efficient no-op patterns for aligning code labels.
573 Note: Don't try to assemble the instructions in the comments.
574 0L and 0w are not legal. */
252b5132
RH		 575 static const char f32_1[] =
576 {0x90}; /* nop */
577 static const char f32_2[] =
ccc9c027 578 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 579 static const char f32_3[] =
580 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
581 static const char f32_4[] =
582 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
583 static const char f32_5[] =
584 {0x90, /* nop */
585 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
586 static const char f32_6[] =
587 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
588 static const char f32_7[] =
589 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
590 static const char f32_8[] =
591 {0x90, /* nop */
592 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
593 static const char f32_9[] =
594 {0x89,0xf6, /* movl %esi,%esi */
595 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
596 static const char f32_10[] =
597 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
598 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
599 static const char f32_11[] =
600 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
601 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
602 static const char f32_12[] =
603 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
604 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
605 static const char f32_13[] =
606 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
607 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
608 static const char f32_14[] =
609 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
610 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
611 static const char f32_15[] =
612 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
613 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 614 static const char f16_3[] =
615 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 616 static const char f16_4[] =
617 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
618 static const char f16_5[] =
619 {0x90, /* nop */
620 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
621 static const char f16_6[] =
622 {0x89,0xf6, /* mov %si,%si */
623 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
624 static const char f16_7[] =
625 {0x8d,0x74,0x00, /* lea 0(%si),%si */
626 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
627 static const char f16_8[] =
628 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
629 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
630 static const char *const f32_patt[] = {
631 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
632 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
633 };
634 static const char *const f16_patt[] = {
c3332e24 635 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 636 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
637 };
ccc9c027
L		 638 /* nopl (%[re]ax) */
639 static const char alt_3[] =
640 {0x0f,0x1f,0x00};
641 /* nopl 0(%[re]ax) */
642 static const char alt_4[] =
643 {0x0f,0x1f,0x40,0x00};
644 /* nopl 0(%[re]ax,%[re]ax,1) */
645 static const char alt_5[] =
646 {0x0f,0x1f,0x44,0x00,0x00};
647 /* nopw 0(%[re]ax,%[re]ax,1) */
648 static const char alt_6[] =
649 {0x66,0x0f,0x1f,0x44,0x00,0x00};
650 /* nopl 0L(%[re]ax) */
651 static const char alt_7[] =
652 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
653 /* nopl 0L(%[re]ax,%[re]ax,1) */
654 static const char alt_8[] =
655 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
656 /* nopw 0L(%[re]ax,%[re]ax,1) */
657 static const char alt_9[] =
658 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
659 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
660 static const char alt_10[] =
661 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
662 /* data16
663 nopw %cs:0L(%[re]ax,%[re]ax,1) */
664 static const char alt_long_11[] =
665 {0x66,
666 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
667 /* data16
668 data16
669 nopw %cs:0L(%[re]ax,%[re]ax,1) */
670 static const char alt_long_12[] =
671 {0x66,
672 0x66,
673 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
674 /* data16
675 data16
676 data16
677 nopw %cs:0L(%[re]ax,%[re]ax,1) */
678 static const char alt_long_13[] =
679 {0x66,
680 0x66,
681 0x66,
682 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
683 /* data16
684 data16
685 data16
686 data16
687 nopw %cs:0L(%[re]ax,%[re]ax,1) */
688 static const char alt_long_14[] =
689 {0x66,
690 0x66,
691 0x66,
692 0x66,
693 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
694 /* data16
695 data16
696 data16
697 data16
698 data16
699 nopw %cs:0L(%[re]ax,%[re]ax,1) */
700 static const char alt_long_15[] =
701 {0x66,
702 0x66,
703 0x66,
704 0x66,
705 0x66,
706 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
707 /* nopl 0(%[re]ax,%[re]ax,1)
708 nopw 0(%[re]ax,%[re]ax,1) */
709 static const char alt_short_11[] =
710 {0x0f,0x1f,0x44,0x00,0x00,
711 0x66,0x0f,0x1f,0x44,0x00,0x00};
712 /* nopw 0(%[re]ax,%[re]ax,1)
713 nopw 0(%[re]ax,%[re]ax,1) */
714 static const char alt_short_12[] =
715 {0x66,0x0f,0x1f,0x44,0x00,0x00,
716 0x66,0x0f,0x1f,0x44,0x00,0x00};
717 /* nopw 0(%[re]ax,%[re]ax,1)
718 nopl 0L(%[re]ax) */
719 static const char alt_short_13[] =
720 {0x66,0x0f,0x1f,0x44,0x00,0x00,
721 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
722 /* nopl 0L(%[re]ax)
723 nopl 0L(%[re]ax) */
724 static const char alt_short_14[] =
725 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
726 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
727 /* nopl 0L(%[re]ax)
728 nopl 0L(%[re]ax,%[re]ax,1) */
729 static const char alt_short_15[] =
730 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
731 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
732 static const char *const alt_short_patt[] = {
733 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
734 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
735 alt_short_14, alt_short_15
736 };
737 static const char *const alt_long_patt[] = {
738 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
739 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
740 alt_long_14, alt_long_15
741 };
252b5132 742
33fef721
JH		 743 if (count <= 0 || count > 15)
744 return;
3e73aa7c 745
ccc9c027
L		 746 /* We need to decide which NOP sequence to use for 32bit and
747 64bit. When -mtune= is used:
4eed87de 748
ccc9c027
L		 749 1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32,
750 f32_patt will be used.
4eed87de
AM		 751 2. For PROCESSOR_K8 and PROCESSOR_AMDFAM10 in 64bit, NOPs with
752 0x66 prefix will be used.
ef05d495 753 3. For PROCESSOR_CORE2, alt_long_patt will be used.
ccc9c027 754 4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
ef05d495 755 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_K6, PROCESSOR_ATHLON
ccc9c027
L		 756 and PROCESSOR_GENERIC64, alt_short_patt will be used.
757
758 When -mtune= isn't used, alt_short_patt will be used if
759 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will be used.
760
761 When -march= or .arch is used, we can't use anything beyond
762 cpu_arch_isa_flags. */
763
764 if (flag_code == CODE_16BIT)
765 {
766 memcpy (fragP->fr_literal + fragP->fr_fix,
767 f16_patt[count - 1], count);
768 if (count > 8)
769 /* Adjust jump offset. */
770 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
771 }
772 else if (flag_code == CODE_64BIT && cpu_arch_tune == PROCESSOR_K8)
252b5132 773 {
33fef721
JH		 774 int i;
775 int nnops = (count + 3) / 4;
776 int len = count / nnops;
777 int remains = count - nnops * len;
778 int pos = 0;
779
ccc9c027 780 /* The recommended way to pad 64bit code is to use NOPs preceded
4eed87de 781 by maximally four 0x66 prefixes. Balance the size of nops. */
33fef721 782 for (i = 0; i < remains; i++)
252b5132 783 {
33fef721
JH		 784 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
785 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
786 pos += len + 1;
787 }
788 for (; i < nnops; i++)
789 {
790 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
791 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
792 pos += len;
252b5132 793 }
252b5132 794 }
33fef721 795 else
ccc9c027
L		 796 {
797 const char *const *patt = NULL;
798
799 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
800 {
801 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
802 switch (cpu_arch_tune)
803 {
804 case PROCESSOR_UNKNOWN:
805 /* We use cpu_arch_isa_flags to check if we SHOULD
806 optimize for Cpu686. */
807 if ((cpu_arch_isa_flags & Cpu686) != 0)
808 patt = alt_short_patt;
809 else
810 patt = f32_patt;
811 break;
ef05d495 812 case PROCESSOR_CORE2:
ccc9c027
L		 813 patt = alt_long_patt;
814 break;
815 case PROCESSOR_PENTIUMPRO:
816 case PROCESSOR_PENTIUM4:
817 case PROCESSOR_NOCONA:
ef05d495 818 case PROCESSOR_CORE:
ccc9c027
L		 819 case PROCESSOR_K6:
820 case PROCESSOR_ATHLON:
821 case PROCESSOR_K8:
822 case PROCESSOR_GENERIC64:
4eed87de 823 case PROCESSOR_AMDFAM10:
ccc9c027
L		 824 patt = alt_short_patt;
825 break;
826 case PROCESSOR_I486:
827 case PROCESSOR_PENTIUM:
828 case PROCESSOR_GENERIC32:
829 patt = f32_patt;
830 break;
4eed87de 831 }
ccc9c027
L		 832 }
833 else
834 {
835 switch (cpu_arch_tune)
836 {
837 case PROCESSOR_UNKNOWN:
838 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
839 PROCESSOR_UNKNOWN. */
840 abort ();
841 break;
842
843 case PROCESSOR_I486:
844 case PROCESSOR_PENTIUM:
845 case PROCESSOR_PENTIUMPRO:
846 case PROCESSOR_PENTIUM4:
847 case PROCESSOR_NOCONA:
ef05d495 848 case PROCESSOR_CORE:
ccc9c027
L		 849 case PROCESSOR_K6:
850 case PROCESSOR_ATHLON:
851 case PROCESSOR_K8:
4eed87de 852 case PROCESSOR_AMDFAM10:
ccc9c027
L		 853 case PROCESSOR_GENERIC32:
854 /* We use cpu_arch_isa_flags to check if we CAN optimize
855 for Cpu686. */
856 if ((cpu_arch_isa_flags & Cpu686) != 0)
857 patt = alt_short_patt;
858 else
859 patt = f32_patt;
860 break;
ef05d495 861 case PROCESSOR_CORE2:
ccc9c027
L		 862 if ((cpu_arch_isa_flags & Cpu686) != 0)
863 patt = alt_long_patt;
864 else
865 patt = f32_patt;
866 break;
867 case PROCESSOR_GENERIC64:
868 patt = alt_short_patt;
869 break;
4eed87de 870 }
ccc9c027
L		 871 }
872
33fef721 873 memcpy (fragP->fr_literal + fragP->fr_fix,
ccc9c027
L		 874 patt[count - 1], count);
875 }
33fef721 876 fragP->fr_var = count;
252b5132
RH		 877}
878
252b5132 879static INLINE unsigned int
e3bb37b5 880mode_from_disp_size (unsigned int t)
252b5132 881{
3e73aa7c 882 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 883}
884
885static INLINE int
e3bb37b5 886fits_in_signed_byte (offsetT num)
252b5132
RH		 887{
888 return (num >= -128) && (num <= 127);
47926f60 889}
252b5132
RH		 890
891static INLINE int
e3bb37b5 892fits_in_unsigned_byte (offsetT num)
252b5132
RH		 893{
894 return (num & 0xff) == num;
47926f60 895}
252b5132
RH		 896
897static INLINE int
e3bb37b5 898fits_in_unsigned_word (offsetT num)
252b5132
RH		 899{
900 return (num & 0xffff) == num;
47926f60 901}
252b5132
RH		 902
903static INLINE int
e3bb37b5 904fits_in_signed_word (offsetT num)
252b5132
RH		 905{
906 return (-32768 <= num) && (num <= 32767);
47926f60 907}
2a962e6d 908
3e73aa7c 909static INLINE int
e3bb37b5 910fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 911{
912#ifndef BFD64
913 return 1;
914#else
915 return (!(((offsetT) -1 << 31) & num)
916 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
917#endif
918} /* fits_in_signed_long() */
2a962e6d 919
3e73aa7c 920static INLINE int
e3bb37b5 921fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 922{
923#ifndef BFD64
924 return 1;
925#else
926 return (num & (((offsetT) 2 << 31) - 1)) == num;
927#endif
928} /* fits_in_unsigned_long() */
252b5132 929
1509aa9a 930static unsigned int
e3bb37b5 931smallest_imm_type (offsetT num)
252b5132 932{
d32cad65 933 if (cpu_arch_flags != (Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 934 {
935 /* This code is disabled on the 486 because all the Imm1 forms
936 in the opcode table are slower on the i486. They're the
937 versions with the implicitly specified single-position
938 displacement, which has another syntax if you really want to
939 use that form. */
940 if (num == 1)
3e73aa7c 941 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 942 }
252b5132 943 return (fits_in_signed_byte (num)
3e73aa7c 944 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 945 : fits_in_unsigned_byte (num)
3e73aa7c 946 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 947 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 948 ? (Imm16 | Imm32 | Imm32S | Imm64)
949 : fits_in_signed_long (num)
950 ? (Imm32 | Imm32S | Imm64)
951 : fits_in_unsigned_long (num)
952 ? (Imm32 | Imm64)
953 : Imm64);
47926f60 954}
252b5132 955
847f7ad4 956static offsetT
e3bb37b5 957offset_in_range (offsetT val, int size)
847f7ad4 958{
508866be 959 addressT mask;
ba2adb93 960
847f7ad4
AM		 961 switch (size)
962 {
508866be
L		 963 case 1: mask = ((addressT) 1 << 8) - 1; break;
964 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 965 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 966#ifdef BFD64
967 case 8: mask = ((addressT) 2 << 63) - 1; break;
968#endif
47926f60 969 default: abort ();
847f7ad4
AM		 970 }
971
ba2adb93 972 /* If BFD64, sign extend val. */
3e73aa7c
JH		 973 if (!use_rela_relocations)
974 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
975 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 976
47926f60 977 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 978 {
979 char buf1[40], buf2[40];
980
981 sprint_value (buf1, val);
982 sprint_value (buf2, val & mask);
983 as_warn (_("%s shortened to %s"), buf1, buf2);
984 }
985 return val & mask;
986}
987
252b5132
RH		 988/* Returns 0 if attempting to add a prefix where one from the same
989 class already exists, 1 if non rep/repne added, 2 if rep/repne
990 added. */
991static int
e3bb37b5 992add_prefix (unsigned int prefix)
252b5132
RH		 993{
994 int ret = 1;
b1905489 995 unsigned int q;
252b5132 996
29b0f896
AM		 997 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
998 && flag_code == CODE_64BIT)
b1905489 999 {
161a04f6
L		 1000 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1001 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1002 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 1003 ret = 0;
1004 q = REX_PREFIX;
1005 }
3e73aa7c 1006 else
b1905489
JB		 1007 {
1008 switch (prefix)
1009 {
1010 default:
1011 abort ();
1012
1013 case CS_PREFIX_OPCODE:
1014 case DS_PREFIX_OPCODE:
1015 case ES_PREFIX_OPCODE:
1016 case FS_PREFIX_OPCODE:
1017 case GS_PREFIX_OPCODE:
1018 case SS_PREFIX_OPCODE:
1019 q = SEG_PREFIX;
1020 break;
1021
1022 case REPNE_PREFIX_OPCODE:
1023 case REPE_PREFIX_OPCODE:
1024 ret = 2;
1025 /* fall thru */
1026 case LOCK_PREFIX_OPCODE:
1027 q = LOCKREP_PREFIX;
1028 break;
1029
1030 case FWAIT_OPCODE:
1031 q = WAIT_PREFIX;
1032 break;
1033
1034 case ADDR_PREFIX_OPCODE:
1035 q = ADDR_PREFIX;
1036 break;
1037
1038 case DATA_PREFIX_OPCODE:
1039 q = DATA_PREFIX;
1040 break;
1041 }
1042 if (i.prefix[q] != 0)
1043 ret = 0;
1044 }
252b5132 1045
b1905489 1046 if (ret)
252b5132 1047 {
b1905489
JB		 1048 if (!i.prefix[q])
1049 ++i.prefixes;
1050 i.prefix[q] |= prefix;
252b5132 1051 }
b1905489
JB		 1052 else
1053 as_bad (_("same type of prefix used twice"));
252b5132 1054
252b5132
RH		 1055 return ret;
1056}
1057
1058static void
e3bb37b5 1059set_code_flag (int value)
eecb386c 1060{
3e73aa7c
JH		 1061 flag_code = value;
1062 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1063 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
1064 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
1065 {
1066 as_bad (_("64bit mode not supported on this CPU."));
1067 }
1068 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
1069 {
1070 as_bad (_("32bit mode not supported on this CPU."));
1071 }
eecb386c
AM		 1072 stackop_size = '\0';
1073}
1074
1075static void
e3bb37b5 1076set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1077{
3e73aa7c
JH		 1078 flag_code = new_code_flag;
1079 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1080 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
9306ca4a 1081 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1082}
1083
1084static void
e3bb37b5 1085set_intel_syntax (int syntax_flag)
252b5132
RH		 1086{
1087 /* Find out if register prefixing is specified. */
1088 int ask_naked_reg = 0;
1089
1090 SKIP_WHITESPACE ();
29b0f896 1091 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1092 {
1093 char *string = input_line_pointer;
1094 int e = get_symbol_end ();
1095
47926f60 1096 if (strcmp (string, "prefix") == 0)
252b5132 1097 ask_naked_reg = 1;
47926f60 1098 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1099 ask_naked_reg = -1;
1100 else
d0b47220 1101 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1102 *input_line_pointer = e;
1103 }
1104 demand_empty_rest_of_line ();
c3332e24 1105
252b5132
RH		 1106 intel_syntax = syntax_flag;
1107
1108 if (ask_naked_reg == 0)
f86103b7
AM		 1109 allow_naked_reg = (intel_syntax
1110 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1111 else
1112 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1113
e4a3b5a4 1114 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1115 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1116 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1117}
1118
e413e4e9 1119static void
e3bb37b5 1120set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1121{
47926f60 1122 SKIP_WHITESPACE ();
e413e4e9 1123
29b0f896 1124 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1125 {
1126 char *string = input_line_pointer;
1127 int e = get_symbol_end ();
9103f4f4 1128 unsigned int i;
e413e4e9 1129
9103f4f4 1130 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1131 {
1132 if (strcmp (string, cpu_arch[i].name) == 0)
1133 {
5c6af06e
JB		 1134 if (*string != '.')
1135 {
1136 cpu_arch_name = cpu_arch[i].name;
1137 cpu_sub_arch_name = NULL;
1138 cpu_arch_flags = (cpu_arch[i].flags
4eed87de
AM		 1139 | (flag_code == CODE_64BIT
1140 ? Cpu64 : CpuNo64));
ccc9c027 1141 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1142 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1143 if (!cpu_arch_tune_set)
1144 {
1145 cpu_arch_tune = cpu_arch_isa;
1146 cpu_arch_tune_flags = cpu_arch_isa_flags;
1147 }
5c6af06e
JB		 1148 break;
1149 }
1150 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
1151 {
1152 cpu_sub_arch_name = cpu_arch[i].name;
1153 cpu_arch_flags |= cpu_arch[i].flags;
1154 }
1155 *input_line_pointer = e;
1156 demand_empty_rest_of_line ();
1157 return;
e413e4e9
AM		 1158 }
1159 }
9103f4f4 1160 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1161 as_bad (_("no such architecture: `%s'"), string);
1162
1163 *input_line_pointer = e;
1164 }
1165 else
1166 as_bad (_("missing cpu architecture"));
1167
fddf5b5b
AM		 1168 no_cond_jump_promotion = 0;
1169 if (*input_line_pointer == ','
29b0f896 1170 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1171 {
1172 char *string = ++input_line_pointer;
1173 int e = get_symbol_end ();
1174
1175 if (strcmp (string, "nojumps") == 0)
1176 no_cond_jump_promotion = 1;
1177 else if (strcmp (string, "jumps") == 0)
1178 ;
1179 else
1180 as_bad (_("no such architecture modifier: `%s'"), string);
1181
1182 *input_line_pointer = e;
1183 }
1184
e413e4e9
AM		 1185 demand_empty_rest_of_line ();
1186}
1187
b9d79e03
JH		 1188unsigned long
1189i386_mach ()
1190{
1191 if (!strcmp (default_arch, "x86_64"))
1192 return bfd_mach_x86_64;
1193 else if (!strcmp (default_arch, "i386"))
1194 return bfd_mach_i386_i386;
1195 else
1196 as_fatal (_("Unknown architecture"));
1197}
b9d79e03 1198\f
252b5132
RH		 1199void
1200md_begin ()
1201{
1202 const char *hash_err;
1203
47926f60 1204 /* Initialize op_hash hash table. */
252b5132
RH		 1205 op_hash = hash_new ();
1206
1207 {
29b0f896
AM		 1208 const template *optab;
1209 templates *core_optab;
252b5132 1210
47926f60
KH		 1211 /* Setup for loop. */
1212 optab = i386_optab;
252b5132
RH		 1213 core_optab = (templates *) xmalloc (sizeof (templates));
1214 core_optab->start = optab;
1215
1216 while (1)
1217 {
1218 ++optab;
1219 if (optab->name == NULL
1220 || strcmp (optab->name, (optab - 1)->name) != 0)
1221 {
1222 /* different name --> ship out current template list;
47926f60 1223 add to hash table; & begin anew. */
252b5132
RH		 1224 core_optab->end = optab;
1225 hash_err = hash_insert (op_hash,
1226 (optab - 1)->name,
1227 (PTR) core_optab);
1228 if (hash_err)
1229 {
252b5132
RH		 1230 as_fatal (_("Internal Error: Can't hash %s: %s"),
1231 (optab - 1)->name,
1232 hash_err);
1233 }
1234 if (optab->name == NULL)
1235 break;
1236 core_optab = (templates *) xmalloc (sizeof (templates));
1237 core_optab->start = optab;
1238 }
1239 }
1240 }
1241
47926f60 1242 /* Initialize reg_hash hash table. */
252b5132
RH		 1243 reg_hash = hash_new ();
1244 {
29b0f896 1245 const reg_entry *regtab;
c3fe08fa 1246 unsigned int regtab_size = i386_regtab_size;
252b5132 1247
c3fe08fa 1248 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132
RH		 1249 {
1250 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1251 if (hash_err)
3e73aa7c
JH		 1252 as_fatal (_("Internal Error: Can't hash %s: %s"),
1253 regtab->reg_name,
1254 hash_err);
252b5132
RH		 1255 }
1256 }
1257
47926f60 1258 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 1259 {
29b0f896
AM		 1260 int c;
1261 char *p;
252b5132
RH		 1262
1263 for (c = 0; c < 256; c++)
1264 {
3882b010 1265 if (ISDIGIT (c))
252b5132
RH		 1266 {
1267 digit_chars[c] = c;
1268 mnemonic_chars[c] = c;
1269 register_chars[c] = c;
1270 operand_chars[c] = c;
1271 }
3882b010 1272 else if (ISLOWER (c))
252b5132
RH		 1273 {
1274 mnemonic_chars[c] = c;
1275 register_chars[c] = c;
1276 operand_chars[c] = c;
1277 }
3882b010 1278 else if (ISUPPER (c))
252b5132 1279 {
3882b010 1280 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1281 register_chars[c] = mnemonic_chars[c];
1282 operand_chars[c] = c;
1283 }
1284
3882b010 1285 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1286 identifier_chars[c] = c;
1287 else if (c >= 128)
1288 {
1289 identifier_chars[c] = c;
1290 operand_chars[c] = c;
1291 }
1292 }
1293
1294#ifdef LEX_AT
1295 identifier_chars['@'] = '@';
32137342
NC		 1296#endif
1297#ifdef LEX_QM
1298 identifier_chars['?'] = '?';
1299 operand_chars['?'] = '?';
252b5132 1300#endif
252b5132 1301 digit_chars['-'] = '-';
791fe849 1302 mnemonic_chars['-'] = '-';
0003779b 1303 mnemonic_chars['.'] = '.';
252b5132
RH		 1304 identifier_chars['_'] = '_';
1305 identifier_chars['.'] = '.';
1306
1307 for (p = operand_special_chars; *p != '\0'; p++)
1308 operand_chars[(unsigned char) *p] = *p;
1309 }
1310
1311#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1312 if (IS_ELF)
252b5132
RH		 1313 {
1314 record_alignment (text_section, 2);
1315 record_alignment (data_section, 2);
1316 record_alignment (bss_section, 2);
1317 }
1318#endif
a4447b93
RH		 1319
1320 if (flag_code == CODE_64BIT)
1321 {
1322 x86_dwarf2_return_column = 16;
1323 x86_cie_data_alignment = -8;
1324 }
1325 else
1326 {
1327 x86_dwarf2_return_column = 8;
1328 x86_cie_data_alignment = -4;
1329 }
252b5132
RH		 1330}
1331
1332void
e3bb37b5 1333i386_print_statistics (FILE *file)
252b5132
RH		 1334{
1335 hash_print_statistics (file, "i386 opcode", op_hash);
1336 hash_print_statistics (file, "i386 register", reg_hash);
1337}
1338\f
252b5132
RH		 1339#ifdef DEBUG386
1340
ce8a8b2f 1341/* Debugging routines for md_assemble. */
e3bb37b5
L		 1342static void pte (template *);
1343static void pt (unsigned int);
1344static void pe (expressionS *);
1345static void ps (symbolS *);
252b5132
RH		 1346
1347static void
e3bb37b5 1348pi (char *line, i386_insn *x)
252b5132 1349{
09f131f2 1350 unsigned int i;
252b5132
RH		 1351
1352 fprintf (stdout, "%s: template ", line);
1353 pte (&x->tm);
09f131f2
JH		 1354 fprintf (stdout, " address: base %s index %s scale %x\n",
1355 x->base_reg ? x->base_reg->reg_name : "none",
1356 x->index_reg ? x->index_reg->reg_name : "none",
1357 x->log2_scale_factor);
1358 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1359 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1360 fprintf (stdout, " sib: base %x index %x scale %x\n",
1361 x->sib.base, x->sib.index, x->sib.scale);
1362 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 1363 (x->rex & REX_W) != 0,
1364 (x->rex & REX_R) != 0,
1365 (x->rex & REX_X) != 0,
1366 (x->rex & REX_B) != 0);
252b5132
RH		 1367 for (i = 0; i < x->operands; i++)
1368 {
1369 fprintf (stdout, " #%d: ", i + 1);
1370 pt (x->types[i]);
1371 fprintf (stdout, "\n");
1372 if (x->types[i]
3f4438ab 1373 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1374 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1375 if (x->types[i] & Imm)
520dc8e8 1376 pe (x->op[i].imms);
252b5132 1377 if (x->types[i] & Disp)
520dc8e8 1378 pe (x->op[i].disps);
252b5132
RH		 1379 }
1380}
1381
1382static void
e3bb37b5 1383pte (template *t)
252b5132 1384{
09f131f2 1385 unsigned int i;
252b5132 1386 fprintf (stdout, " %d operands ", t->operands);
47926f60 1387 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1388 if (t->extension_opcode != None)
1389 fprintf (stdout, "ext %x ", t->extension_opcode);
1390 if (t->opcode_modifier & D)
1391 fprintf (stdout, "D");
1392 if (t->opcode_modifier & W)
1393 fprintf (stdout, "W");
1394 fprintf (stdout, "\n");
1395 for (i = 0; i < t->operands; i++)
1396 {
1397 fprintf (stdout, " #%d type ", i + 1);
1398 pt (t->operand_types[i]);
1399 fprintf (stdout, "\n");
1400 }
1401}
1402
1403static void
e3bb37b5 1404pe (expressionS *e)
252b5132 1405{
24eab124 1406 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1407 fprintf (stdout, " add_number %ld (%lx)\n",
1408 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1409 if (e->X_add_symbol)
1410 {
1411 fprintf (stdout, " add_symbol ");
1412 ps (e->X_add_symbol);
1413 fprintf (stdout, "\n");
1414 }
1415 if (e->X_op_symbol)
1416 {
1417 fprintf (stdout, " op_symbol ");
1418 ps (e->X_op_symbol);
1419 fprintf (stdout, "\n");
1420 }
1421}
1422
1423static void
e3bb37b5 1424ps (symbolS *s)
252b5132
RH		 1425{
1426 fprintf (stdout, "%s type %s%s",
1427 S_GET_NAME (s),
1428 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1429 segment_name (S_GET_SEGMENT (s)));
1430}
1431
7b81dfbb 1432static struct type_name
252b5132
RH		 1433 {
1434 unsigned int mask;
1435 char *tname;
1436 }
7b81dfbb 1437const type_names[] =
252b5132
RH		 1438{
1439 { Reg8, "r8" },
1440 { Reg16, "r16" },
1441 { Reg32, "r32" },
09f131f2 1442 { Reg64, "r64" },
252b5132
RH		 1443 { Imm8, "i8" },
1444 { Imm8S, "i8s" },
1445 { Imm16, "i16" },
1446 { Imm32, "i32" },
09f131f2
JH		 1447 { Imm32S, "i32s" },
1448 { Imm64, "i64" },
252b5132
RH		 1449 { Imm1, "i1" },
1450 { BaseIndex, "BaseIndex" },
1451 { Disp8, "d8" },
1452 { Disp16, "d16" },
1453 { Disp32, "d32" },
09f131f2
JH		 1454 { Disp32S, "d32s" },
1455 { Disp64, "d64" },
252b5132
RH		 1456 { InOutPortReg, "InOutPortReg" },
1457 { ShiftCount, "ShiftCount" },
1458 { Control, "control reg" },
1459 { Test, "test reg" },
1460 { Debug, "debug reg" },
1461 { FloatReg, "FReg" },
1462 { FloatAcc, "FAcc" },
1463 { SReg2, "SReg2" },
1464 { SReg3, "SReg3" },
1465 { Acc, "Acc" },
1466 { JumpAbsolute, "Jump Absolute" },
1467 { RegMMX, "rMMX" },
3f4438ab 1468 { RegXMM, "rXMM" },
252b5132
RH		 1469 { EsSeg, "es" },
1470 { 0, "" }
1471};
1472
1473static void
1474pt (t)
1475 unsigned int t;
1476{
29b0f896 1477 const struct type_name *ty;
252b5132 1478
09f131f2
JH		 1479 for (ty = type_names; ty->mask; ty++)
1480 if (t & ty->mask)
1481 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1482 fflush (stdout);
1483}
1484
1485#endif /* DEBUG386 */
1486\f
252b5132 1487static bfd_reloc_code_real_type
3956db08 1488reloc (unsigned int size,
64e74474
AM		 1489 int pcrel,
1490 int sign,
1491 bfd_reloc_code_real_type other)
252b5132 1492{
47926f60 1493 if (other != NO_RELOC)
3956db08
JB		 1494 {
1495 reloc_howto_type *reloc;
1496
1497 if (size == 8)
1498 switch (other)
1499 {
64e74474
AM		 1500 case BFD_RELOC_X86_64_GOT32:
1501 return BFD_RELOC_X86_64_GOT64;
1502 break;
1503 case BFD_RELOC_X86_64_PLTOFF64:
1504 return BFD_RELOC_X86_64_PLTOFF64;
1505 break;
1506 case BFD_RELOC_X86_64_GOTPC32:
1507 other = BFD_RELOC_X86_64_GOTPC64;
1508 break;
1509 case BFD_RELOC_X86_64_GOTPCREL:
1510 other = BFD_RELOC_X86_64_GOTPCREL64;
1511 break;
1512 case BFD_RELOC_X86_64_TPOFF32:
1513 other = BFD_RELOC_X86_64_TPOFF64;
1514 break;
1515 case BFD_RELOC_X86_64_DTPOFF32:
1516 other = BFD_RELOC_X86_64_DTPOFF64;
1517 break;
1518 default:
1519 break;
3956db08 1520 }
e05278af
JB		 1521
1522 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1523 if (size == 4 && flag_code != CODE_64BIT)
1524 sign = -1;
1525
3956db08
JB		 1526 reloc = bfd_reloc_type_lookup (stdoutput, other);
1527 if (!reloc)
1528 as_bad (_("unknown relocation (%u)"), other);
1529 else if (size != bfd_get_reloc_size (reloc))
1530 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1531 bfd_get_reloc_size (reloc),
1532 size);
1533 else if (pcrel && !reloc->pc_relative)
1534 as_bad (_("non-pc-relative relocation for pc-relative field"));
1535 else if ((reloc->complain_on_overflow == complain_overflow_signed
1536 && !sign)
1537 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 1538 && sign > 0))
3956db08
JB		 1539 as_bad (_("relocated field and relocation type differ in signedness"));
1540 else
1541 return other;
1542 return NO_RELOC;
1543 }
252b5132
RH		 1544
1545 if (pcrel)
1546 {
3e73aa7c 1547 if (!sign)
3956db08 1548 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1549 switch (size)
1550 {
1551 case 1: return BFD_RELOC_8_PCREL;
1552 case 2: return BFD_RELOC_16_PCREL;
1553 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1554 case 8: return BFD_RELOC_64_PCREL;
252b5132 1555 }
3956db08 1556 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1557 }
1558 else
1559 {
3956db08 1560 if (sign > 0)
e5cb08ac 1561 switch (size)
3e73aa7c
JH		 1562 {
1563 case 4: return BFD_RELOC_X86_64_32S;
1564 }
1565 else
1566 switch (size)
1567 {
1568 case 1: return BFD_RELOC_8;
1569 case 2: return BFD_RELOC_16;
1570 case 4: return BFD_RELOC_32;
1571 case 8: return BFD_RELOC_64;
1572 }
3956db08
JB		 1573 as_bad (_("cannot do %s %u byte relocation"),
1574 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1575 }
1576
bfb32b52 1577 abort ();
252b5132
RH		 1578 return BFD_RELOC_NONE;
1579}
1580
47926f60
KH		 1581/* Here we decide which fixups can be adjusted to make them relative to
1582 the beginning of the section instead of the symbol. Basically we need
1583 to make sure that the dynamic relocations are done correctly, so in
1584 some cases we force the original symbol to be used. */
1585
252b5132 1586int
e3bb37b5 1587tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 1588{
6d249963 1589#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1590 if (!IS_ELF)
31312f95
AM		 1591 return 1;
1592
a161fe53
AM		 1593 /* Don't adjust pc-relative references to merge sections in 64-bit
1594 mode. */
1595 if (use_rela_relocations
1596 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1597 && fixP->fx_pcrel)
252b5132 1598 return 0;
31312f95 1599
8d01d9a9
AJ		 1600 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1601 and changed later by validate_fix. */
1602 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1603 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1604 return 0;
1605
ce8a8b2f 1606 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1607 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1608 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1609 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1610 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1611 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1612 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1613 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1614 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1615 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1616 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1617 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 1618 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
1619 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 1620 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1621 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1622 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 1623 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1624 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1625 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 1626 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 1627 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1628 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 1629 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1630 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 1631 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
1632 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 1633 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1634 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1635 return 0;
31312f95 1636#endif
252b5132
RH		 1637 return 1;
1638}
252b5132 1639
b4cac588 1640static int
e3bb37b5 1641intel_float_operand (const char *mnemonic)
252b5132 1642{
9306ca4a
JB		 1643 /* Note that the value returned is meaningful only for opcodes with (memory)
1644 operands, hence the code here is free to improperly handle opcodes that
1645 have no operands (for better performance and smaller code). */
1646
1647 if (mnemonic[0] != 'f')
1648 return 0; /* non-math */
1649
1650 switch (mnemonic[1])
1651 {
1652 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1653 the fs segment override prefix not currently handled because no
1654 call path can make opcodes without operands get here */
1655 case 'i':
1656 return 2 /* integer op */;
1657 case 'l':
1658 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1659 return 3; /* fldcw/fldenv */
1660 break;
1661 case 'n':
1662 if (mnemonic[2] != 'o' /* fnop */)
1663 return 3; /* non-waiting control op */
1664 break;
1665 case 'r':
1666 if (mnemonic[2] == 's')
1667 return 3; /* frstor/frstpm */
1668 break;
1669 case 's':
1670 if (mnemonic[2] == 'a')
1671 return 3; /* fsave */
1672 if (mnemonic[2] == 't')
1673 {
1674 switch (mnemonic[3])
1675 {
1676 case 'c': /* fstcw */
1677 case 'd': /* fstdw */
1678 case 'e': /* fstenv */
1679 case 's': /* fsts[gw] */
1680 return 3;
1681 }
1682 }
1683 break;
1684 case 'x':
1685 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1686 return 0; /* fxsave/fxrstor are not really math ops */
1687 break;
1688 }
252b5132 1689
9306ca4a 1690 return 1;
252b5132
RH		 1691}
1692
1693/* This is the guts of the machine-dependent assembler. LINE points to a
1694 machine dependent instruction. This function is supposed to emit
1695 the frags/bytes it assembles to. */
1696
1697void
1698md_assemble (line)
1699 char *line;
1700{
252b5132 1701 int j;
252b5132
RH		 1702 char mnemonic[MAX_MNEM_SIZE];
1703
47926f60 1704 /* Initialize globals. */
252b5132
RH		 1705 memset (&i, '\0', sizeof (i));
1706 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1707 i.reloc[j] = NO_RELOC;
252b5132
RH		 1708 memset (disp_expressions, '\0', sizeof (disp_expressions));
1709 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1710 save_stack_p = save_stack;
252b5132
RH		 1711
1712 /* First parse an instruction mnemonic & call i386_operand for the operands.
1713 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1714 start of a (possibly prefixed) mnemonic. */
252b5132 1715
29b0f896
AM		 1716 line = parse_insn (line, mnemonic);
1717 if (line == NULL)
1718 return;
252b5132 1719
29b0f896
AM		 1720 line = parse_operands (line, mnemonic);
1721 if (line == NULL)
1722 return;
252b5132 1723
4eed87de 1724 /* The order of the immediates should be reversed
050dfa73 1725 for 2 immediates extrq and insertq instructions */
4d456e3d
L		 1726 if ((i.imm_operands == 2)
1727 && ((strcmp (mnemonic, "extrq") == 0)
1728 || (strcmp (mnemonic, "insertq") == 0)))
050dfa73 1729 {
4eed87de
AM		 1730 swap_2_operands (0, 1);
1731 /* "extrq" and insertq" are the only two instructions whose operands
050dfa73
MM		 1732 have to be reversed even though they have two immediate operands.
1733 */
1734 if (intel_syntax)
1735 swap_operands ();
1736 }
1737
29b0f896
AM		 1738 /* Now we've parsed the mnemonic into a set of templates, and have the
1739 operands at hand. */
1740
1741 /* All intel opcodes have reversed operands except for "bound" and
1742 "enter". We also don't reverse intersegment "jmp" and "call"
1743 instructions with 2 immediate operands so that the immediate segment
050dfa73 1744 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 1745 if (intel_syntax
1746 && i.operands > 1
29b0f896 1747 && (strcmp (mnemonic, "bound") != 0)
30123838 1748 && (strcmp (mnemonic, "invlpga") != 0)
29b0f896
AM		 1749 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1750 swap_operands ();
1751
1752 if (i.imm_operands)
1753 optimize_imm ();
1754
b300c311
L		 1755 /* Don't optimize displacement for movabs since it only takes 64bit
1756 displacement. */
1757 if (i.disp_operands
1758 && (flag_code != CODE_64BIT
1759 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 1760 optimize_disp ();
1761
1762 /* Next, we find a template that matches the given insn,
1763 making sure the overlap of the given operands types is consistent
1764 with the template operand types. */
252b5132 1765
29b0f896
AM		 1766 if (!match_template ())
1767 return;
252b5132 1768
cd61ebfe
AM		 1769 if (intel_syntax)
1770 {
1771 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1772 if (SYSV386_COMPAT
1773 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
8a2ed489 1774 i.tm.base_opcode ^= Opcode_FloatR;
cd61ebfe
AM		 1775
1776 /* Zap movzx and movsx suffix. The suffix may have been set from
1777 "word ptr" or "byte ptr" on the source operand, but we'll use
1778 the suffix later to choose the destination register. */
1779 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 1780 {
1781 if (i.reg_operands < 2
1782 && !i.suffix
1783 && (~i.tm.opcode_modifier
1784 & (No_bSuf
1785 | No_wSuf
1786 | No_lSuf
1787 | No_sSuf
1788 | No_xSuf
1789 | No_qSuf)))
1790 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1791
1792 i.suffix = 0;
1793 }
cd61ebfe 1794 }
24eab124 1795
29b0f896
AM		 1796 if (i.tm.opcode_modifier & FWait)
1797 if (!add_prefix (FWAIT_OPCODE))
1798 return;
252b5132 1799
29b0f896
AM		 1800 /* Check string instruction segment overrides. */
1801 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1802 {
1803 if (!check_string ())
5dd0794d 1804 return;
29b0f896 1805 }
5dd0794d 1806
29b0f896
AM		 1807 if (!process_suffix ())
1808 return;
e413e4e9 1809
29b0f896
AM		 1810 /* Make still unresolved immediate matches conform to size of immediate
1811 given in i.suffix. */
1812 if (!finalize_imm ())
1813 return;
252b5132 1814
29b0f896
AM		 1815 if (i.types[0] & Imm1)
1816 i.imm_operands = 0; /* kludge for shift insns. */
1817 if (i.types[0] & ImplicitRegister)
1818 i.reg_operands--;
1819 if (i.types[1] & ImplicitRegister)
1820 i.reg_operands--;
1821 if (i.types[2] & ImplicitRegister)
1822 i.reg_operands--;
252b5132 1823
29b0f896
AM		 1824 if (i.tm.opcode_modifier & ImmExt)
1825 {
02fc3089
L		 1826 expressionS *exp;
1827
b7d9ef37 1828 if ((i.tm.cpu_flags & CpuSSE3) && i.operands > 0)
ca164297 1829 {
b7d9ef37 1830 /* Streaming SIMD extensions 3 Instructions have the fixed
ca164297
L		 1831 operands with an opcode suffix which is coded in the same
1832 place as an 8-bit immediate field would be. Here we check
1833 those operands and remove them afterwards. */
1834 unsigned int x;
1835
a4622f40 1836 for (x = 0; x < i.operands; x++)
ca164297 1837 if (i.op[x].regs->reg_num != x)
a540244d
L		 1838 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1839 register_prefix,
1840 i.op[x].regs->reg_name,
1841 x + 1,
1842 i.tm.name);
ca164297
L		 1843 i.operands = 0;
1844 }
1845
29b0f896
AM		 1846 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1847 opcode suffix which is coded in the same place as an 8-bit
1848 immediate field would be. Here we fake an 8-bit immediate
1849 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1850
29b0f896 1851 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1852
29b0f896
AM		 1853 exp = &im_expressions[i.imm_operands++];
1854 i.op[i.operands].imms = exp;
1855 i.types[i.operands++] = Imm8;
1856 exp->X_op = O_constant;
1857 exp->X_add_number = i.tm.extension_opcode;
1858 i.tm.extension_opcode = None;
1859 }
252b5132 1860
29b0f896
AM		 1861 /* For insns with operands there are more diddles to do to the opcode. */
1862 if (i.operands)
1863 {
1864 if (!process_operands ())
1865 return;
1866 }
1867 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1868 {
1869 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1870 as_warn (_("translating to `%sp'"), i.tm.name);
1871 }
252b5132 1872
29b0f896
AM		 1873 /* Handle conversion of 'int $3' --> special int3 insn. */
1874 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1875 {
1876 i.tm.base_opcode = INT3_OPCODE;
1877 i.imm_operands = 0;
1878 }
252b5132 1879
29b0f896
AM		 1880 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1881 && i.op[0].disps->X_op == O_constant)
1882 {
1883 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1884 the absolute address given by the constant. Since ix86 jumps and
1885 calls are pc relative, we need to generate a reloc. */
1886 i.op[0].disps->X_add_symbol = &abs_symbol;
1887 i.op[0].disps->X_op = O_symbol;
1888 }
252b5132 1889
29b0f896 1890 if ((i.tm.opcode_modifier & Rex64) != 0)
161a04f6 1891 i.rex |= REX_W;
252b5132 1892
29b0f896
AM		 1893 /* For 8 bit registers we need an empty rex prefix. Also if the
1894 instruction already has a prefix, we need to convert old
1895 registers to new ones. */
773f551c 1896
29b0f896
AM		 1897 if (((i.types[0] & Reg8) != 0
1898 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1899 || ((i.types[1] & Reg8) != 0
1900 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1901 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1902 && i.rex != 0))
1903 {
1904 int x;
726c5dcd 1905
29b0f896
AM		 1906 i.rex |= REX_OPCODE;
1907 for (x = 0; x < 2; x++)
1908 {
1909 /* Look for 8 bit operand that uses old registers. */
1910 if ((i.types[x] & Reg8) != 0
1911 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1912 {
29b0f896
AM		 1913 /* In case it is "hi" register, give up. */
1914 if (i.op[x].regs->reg_num > 3)
a540244d 1915 as_bad (_("can't encode register '%s%s' in an "
4eed87de 1916 "instruction requiring REX prefix."),
a540244d 1917 register_prefix, i.op[x].regs->reg_name);
773f551c 1918
29b0f896
AM		 1919 /* Otherwise it is equivalent to the extended register.
1920 Since the encoding doesn't change this is merely
1921 cosmetic cleanup for debug output. */
1922
1923 i.op[x].regs = i.op[x].regs + 8;
773f551c 1924 }
29b0f896
AM		 1925 }
1926 }
773f551c 1927
29b0f896
AM		 1928 if (i.rex != 0)
1929 add_prefix (REX_OPCODE | i.rex);
1930
1931 /* We are ready to output the insn. */
1932 output_insn ();
1933}
1934
1935static char *
e3bb37b5 1936parse_insn (char *line, char *mnemonic)
29b0f896
AM		 1937{
1938 char *l = line;
1939 char *token_start = l;
1940 char *mnem_p;
5c6af06e
JB		 1941 int supported;
1942 const template *t;
29b0f896
AM		 1943
1944 /* Non-zero if we found a prefix only acceptable with string insns. */
1945 const char *expecting_string_instruction = NULL;
45288df1 1946
29b0f896
AM		 1947 while (1)
1948 {
1949 mnem_p = mnemonic;
1950 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1951 {
1952 mnem_p++;
1953 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1954 {
29b0f896
AM		 1955 as_bad (_("no such instruction: `%s'"), token_start);
1956 return NULL;
1957 }
1958 l++;
1959 }
1960 if (!is_space_char (*l)
1961 && *l != END_OF_INSN
e44823cf
JB		 1962 && (intel_syntax
1963 || (*l != PREFIX_SEPARATOR
1964 && *l != ',')))
29b0f896
AM		 1965 {
1966 as_bad (_("invalid character %s in mnemonic"),
1967 output_invalid (*l));
1968 return NULL;
1969 }
1970 if (token_start == l)
1971 {
e44823cf 1972 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 1973 as_bad (_("expecting prefix; got nothing"));
1974 else
1975 as_bad (_("expecting mnemonic; got nothing"));
1976 return NULL;
1977 }
45288df1 1978
29b0f896
AM		 1979 /* Look up instruction (or prefix) via hash table. */
1980 current_templates = hash_find (op_hash, mnemonic);
47926f60 1981
29b0f896
AM		 1982 if (*l != END_OF_INSN
1983 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1984 && current_templates
1985 && (current_templates->start->opcode_modifier & IsPrefix))
1986 {
2dd88dca
JB		 1987 if (current_templates->start->cpu_flags
1988 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
1989 {
1990 as_bad ((flag_code != CODE_64BIT
1991 ? _("`%s' is only supported in 64-bit mode")
1992 : _("`%s' is not supported in 64-bit mode")),
1993 current_templates->start->name);
1994 return NULL;
1995 }
29b0f896
AM		 1996 /* If we are in 16-bit mode, do not allow addr16 or data16.
1997 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1998 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1999 && flag_code != CODE_64BIT
2000 && (((current_templates->start->opcode_modifier & Size32) != 0)
2001 ^ (flag_code == CODE_16BIT)))
2002 {
2003 as_bad (_("redundant %s prefix"),
2004 current_templates->start->name);
2005 return NULL;
45288df1 2006 }
29b0f896
AM		 2007 /* Add prefix, checking for repeated prefixes. */
2008 switch (add_prefix (current_templates->start->base_opcode))
2009 {
2010 case 0:
2011 return NULL;
2012 case 2:
2013 expecting_string_instruction = current_templates->start->name;
2014 break;
2015 }
2016 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2017 token_start = ++l;
2018 }
2019 else
2020 break;
2021 }
45288df1 2022
29b0f896
AM		 2023 if (!current_templates)
2024 {
2025 /* See if we can get a match by trimming off a suffix. */
2026 switch (mnem_p[-1])
2027 {
2028 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2029 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2030 i.suffix = SHORT_MNEM_SUFFIX;
2031 else
29b0f896
AM		 2032 case BYTE_MNEM_SUFFIX:
2033 case QWORD_MNEM_SUFFIX:
2034 i.suffix = mnem_p[-1];
2035 mnem_p[-1] = '\0';
2036 current_templates = hash_find (op_hash, mnemonic);
2037 break;
2038 case SHORT_MNEM_SUFFIX:
2039 case LONG_MNEM_SUFFIX:
2040 if (!intel_syntax)
2041 {
2042 i.suffix = mnem_p[-1];
2043 mnem_p[-1] = '\0';
2044 current_templates = hash_find (op_hash, mnemonic);
2045 }
2046 break;
252b5132 2047
29b0f896
AM		 2048 /* Intel Syntax. */
2049 case 'd':
2050 if (intel_syntax)
2051 {
9306ca4a 2052 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2053 i.suffix = SHORT_MNEM_SUFFIX;
2054 else
2055 i.suffix = LONG_MNEM_SUFFIX;
2056 mnem_p[-1] = '\0';
2057 current_templates = hash_find (op_hash, mnemonic);
2058 }
2059 break;
2060 }
2061 if (!current_templates)
2062 {
2063 as_bad (_("no such instruction: `%s'"), token_start);
2064 return NULL;
2065 }
2066 }
252b5132 2067
29b0f896
AM		 2068 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
2069 {
2070 /* Check for a branch hint. We allow ",pt" and ",pn" for
2071 predict taken and predict not taken respectively.
2072 I'm not sure that branch hints actually do anything on loop
2073 and jcxz insns (JumpByte) for current Pentium4 chips. They
2074 may work in the future and it doesn't hurt to accept them
2075 now. */
2076 if (l[0] == ',' && l[1] == 'p')
2077 {
2078 if (l[2] == 't')
2079 {
2080 if (!add_prefix (DS_PREFIX_OPCODE))
2081 return NULL;
2082 l += 3;
2083 }
2084 else if (l[2] == 'n')
2085 {
2086 if (!add_prefix (CS_PREFIX_OPCODE))
2087 return NULL;
2088 l += 3;
2089 }
2090 }
2091 }
2092 /* Any other comma loses. */
2093 if (*l == ',')
2094 {
2095 as_bad (_("invalid character %s in mnemonic"),
2096 output_invalid (*l));
2097 return NULL;
2098 }
252b5132 2099
29b0f896 2100 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 2101 supported = 0;
2102 for (t = current_templates->start; t < current_templates->end; ++t)
2103 {
2104 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
2105 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
64e74474 2106 supported |= 1;
5c6af06e 2107 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
64e74474 2108 supported |= 2;
5c6af06e
JB		 2109 }
2110 if (!(supported & 2))
2111 {
2112 as_bad (flag_code == CODE_64BIT
2113 ? _("`%s' is not supported in 64-bit mode")
2114 : _("`%s' is only supported in 64-bit mode"),
2115 current_templates->start->name);
2116 return NULL;
2117 }
2118 if (!(supported & 1))
29b0f896 2119 {
5c6af06e
JB		 2120 as_warn (_("`%s' is not supported on `%s%s'"),
2121 current_templates->start->name,
2122 cpu_arch_name,
2123 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896
AM		 2124 }
2125 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
2126 {
2127 as_warn (_("use .code16 to ensure correct addressing mode"));
2128 }
252b5132 2129
29b0f896 2130 /* Check for rep/repne without a string instruction. */
f41bbced 2131 if (expecting_string_instruction)
29b0f896 2132 {
f41bbced
JB		 2133 static templates override;
2134
2135 for (t = current_templates->start; t < current_templates->end; ++t)
2136 if (t->opcode_modifier & IsString)
2137 break;
2138 if (t >= current_templates->end)
2139 {
2140 as_bad (_("expecting string instruction after `%s'"),
64e74474 2141 expecting_string_instruction);
f41bbced
JB		 2142 return NULL;
2143 }
2144 for (override.start = t; t < current_templates->end; ++t)
2145 if (!(t->opcode_modifier & IsString))
2146 break;
2147 override.end = t;
2148 current_templates = &override;
29b0f896 2149 }
252b5132 2150
29b0f896
AM		 2151 return l;
2152}
252b5132 2153
29b0f896 2154static char *
e3bb37b5 2155parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 2156{
2157 char *token_start;
3138f287 2158
29b0f896
AM		 2159 /* 1 if operand is pending after ','. */
2160 unsigned int expecting_operand = 0;
252b5132 2161
29b0f896
AM		 2162 /* Non-zero if operand parens not balanced. */
2163 unsigned int paren_not_balanced;
2164
2165 while (*l != END_OF_INSN)
2166 {
2167 /* Skip optional white space before operand. */
2168 if (is_space_char (*l))
2169 ++l;
2170 if (!is_operand_char (*l) && *l != END_OF_INSN)
2171 {
2172 as_bad (_("invalid character %s before operand %d"),
2173 output_invalid (*l),
2174 i.operands + 1);
2175 return NULL;
2176 }
2177 token_start = l; /* after white space */
2178 paren_not_balanced = 0;
2179 while (paren_not_balanced || *l != ',')
2180 {
2181 if (*l == END_OF_INSN)
2182 {
2183 if (paren_not_balanced)
2184 {
2185 if (!intel_syntax)
2186 as_bad (_("unbalanced parenthesis in operand %d."),
2187 i.operands + 1);
2188 else
2189 as_bad (_("unbalanced brackets in operand %d."),
2190 i.operands + 1);
2191 return NULL;
2192 }
2193 else
2194 break; /* we are done */
2195 }
2196 else if (!is_operand_char (*l) && !is_space_char (*l))
2197 {
2198 as_bad (_("invalid character %s in operand %d"),
2199 output_invalid (*l),
2200 i.operands + 1);
2201 return NULL;
2202 }
2203 if (!intel_syntax)
2204 {
2205 if (*l == '(')
2206 ++paren_not_balanced;
2207 if (*l == ')')
2208 --paren_not_balanced;
2209 }
2210 else
2211 {
2212 if (*l == '[')
2213 ++paren_not_balanced;
2214 if (*l == ']')
2215 --paren_not_balanced;
2216 }
2217 l++;
2218 }
2219 if (l != token_start)
2220 { /* Yes, we've read in another operand. */
2221 unsigned int operand_ok;
2222 this_operand = i.operands++;
2223 if (i.operands > MAX_OPERANDS)
2224 {
2225 as_bad (_("spurious operands; (%d operands/instruction max)"),
2226 MAX_OPERANDS);
2227 return NULL;
2228 }
2229 /* Now parse operand adding info to 'i' as we go along. */
2230 END_STRING_AND_SAVE (l);
2231
2232 if (intel_syntax)
2233 operand_ok =
2234 i386_intel_operand (token_start,
2235 intel_float_operand (mnemonic));
2236 else
2237 operand_ok = i386_operand (token_start);
2238
2239 RESTORE_END_STRING (l);
2240 if (!operand_ok)
2241 return NULL;
2242 }
2243 else
2244 {
2245 if (expecting_operand)
2246 {
2247 expecting_operand_after_comma:
2248 as_bad (_("expecting operand after ','; got nothing"));
2249 return NULL;
2250 }
2251 if (*l == ',')
2252 {
2253 as_bad (_("expecting operand before ','; got nothing"));
2254 return NULL;
2255 }
2256 }
7f3f1ea2 2257
29b0f896
AM		 2258 /* Now *l must be either ',' or END_OF_INSN. */
2259 if (*l == ',')
2260 {
2261 if (*++l == END_OF_INSN)
2262 {
2263 /* Just skip it, if it's \n complain. */
2264 goto expecting_operand_after_comma;
2265 }
2266 expecting_operand = 1;
2267 }
2268 }
2269 return l;
2270}
7f3f1ea2 2271
050dfa73 2272static void
4d456e3d 2273swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 2274{
2275 union i386_op temp_op;
2276 unsigned int temp_type;
2277 enum bfd_reloc_code_real temp_reloc;
4eed87de 2278
050dfa73
MM		 2279 temp_type = i.types[xchg2];
2280 i.types[xchg2] = i.types[xchg1];
2281 i.types[xchg1] = temp_type;
2282 temp_op = i.op[xchg2];
2283 i.op[xchg2] = i.op[xchg1];
2284 i.op[xchg1] = temp_op;
2285 temp_reloc = i.reloc[xchg2];
2286 i.reloc[xchg2] = i.reloc[xchg1];
2287 i.reloc[xchg1] = temp_reloc;
2288}
2289
29b0f896 2290static void
e3bb37b5 2291swap_operands (void)
29b0f896 2292{
b7c61d9a 2293 switch (i.operands)
050dfa73 2294 {
b7c61d9a 2295 case 4:
4d456e3d 2296 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 2297 case 3:
2298 case 2:
4d456e3d 2299 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 2300 break;
2301 default:
2302 abort ();
29b0f896 2303 }
29b0f896
AM		 2304
2305 if (i.mem_operands == 2)
2306 {
2307 const seg_entry *temp_seg;
2308 temp_seg = i.seg[0];
2309 i.seg[0] = i.seg[1];
2310 i.seg[1] = temp_seg;
2311 }
2312}
252b5132 2313
29b0f896
AM		 2314/* Try to ensure constant immediates are represented in the smallest
2315 opcode possible. */
2316static void
e3bb37b5 2317optimize_imm (void)
29b0f896
AM		 2318{
2319 char guess_suffix = 0;
2320 int op;
252b5132 2321
29b0f896
AM		 2322 if (i.suffix)
2323 guess_suffix = i.suffix;
2324 else if (i.reg_operands)
2325 {
2326 /* Figure out a suffix from the last register operand specified.
2327 We can't do this properly yet, ie. excluding InOutPortReg,
2328 but the following works for instructions with immediates.
2329 In any case, we can't set i.suffix yet. */
2330 for (op = i.operands; --op >= 0;)
2331 if (i.types[op] & Reg)
252b5132 2332 {
29b0f896
AM		 2333 if (i.types[op] & Reg8)
2334 guess_suffix = BYTE_MNEM_SUFFIX;
2335 else if (i.types[op] & Reg16)
2336 guess_suffix = WORD_MNEM_SUFFIX;
2337 else if (i.types[op] & Reg32)
2338 guess_suffix = LONG_MNEM_SUFFIX;
2339 else if (i.types[op] & Reg64)
2340 guess_suffix = QWORD_MNEM_SUFFIX;
2341 break;
252b5132 2342 }
29b0f896
AM		 2343 }
2344 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2345 guess_suffix = WORD_MNEM_SUFFIX;
2346
2347 for (op = i.operands; --op >= 0;)
2348 if (i.types[op] & Imm)
2349 {
2350 switch (i.op[op].imms->X_op)
252b5132 2351 {
29b0f896
AM		 2352 case O_constant:
2353 /* If a suffix is given, this operand may be shortened. */
2354 switch (guess_suffix)
252b5132 2355 {
29b0f896
AM		 2356 case LONG_MNEM_SUFFIX:
2357 i.types[op] |= Imm32 | Imm64;
2358 break;
2359 case WORD_MNEM_SUFFIX:
2360 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2361 break;
2362 case BYTE_MNEM_SUFFIX:
2363 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2364 break;
252b5132 2365 }
252b5132 2366
29b0f896
AM		 2367 /* If this operand is at most 16 bits, convert it
2368 to a signed 16 bit number before trying to see
2369 whether it will fit in an even smaller size.
2370 This allows a 16-bit operand such as $0xffe0 to
2371 be recognised as within Imm8S range. */
2372 if ((i.types[op] & Imm16)
2373 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2374 {
29b0f896
AM		 2375 i.op[op].imms->X_add_number =
2376 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2377 }
2378 if ((i.types[op] & Imm32)
2379 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2380 == 0))
2381 {
2382 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2383 ^ ((offsetT) 1 << 31))
2384 - ((offsetT) 1 << 31));
2385 }
2386 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 2387
29b0f896
AM		 2388 /* We must avoid matching of Imm32 templates when 64bit
2389 only immediate is available. */
2390 if (guess_suffix == QWORD_MNEM_SUFFIX)
2391 i.types[op] &= ~Imm32;
2392 break;
252b5132 2393
29b0f896
AM		 2394 case O_absent:
2395 case O_register:
2396 abort ();
2397
2398 /* Symbols and expressions. */
2399 default:
9cd96992
JB		 2400 /* Convert symbolic operand to proper sizes for matching, but don't
2401 prevent matching a set of insns that only supports sizes other
2402 than those matching the insn suffix. */
2403 {
2404 unsigned int mask, allowed = 0;
2405 const template *t;
2406
4eed87de
AM		 2407 for (t = current_templates->start;
2408 t < current_templates->end;
2409 ++t)
2410 allowed |= t->operand_types[op];
9cd96992
JB		 2411 switch (guess_suffix)
2412 {
2413 case QWORD_MNEM_SUFFIX:
2414 mask = Imm64 | Imm32S;
2415 break;
2416 case LONG_MNEM_SUFFIX:
2417 mask = Imm32;
2418 break;
2419 case WORD_MNEM_SUFFIX:
2420 mask = Imm16;
2421 break;
2422 case BYTE_MNEM_SUFFIX:
2423 mask = Imm8;
2424 break;
2425 default:
2426 mask = 0;
2427 break;
2428 }
64e74474
AM		 2429 if (mask & allowed)
2430 i.types[op] &= mask;
9cd96992 2431 }
29b0f896 2432 break;
252b5132 2433 }
29b0f896
AM		 2434 }
2435}
47926f60 2436
29b0f896
AM		 2437/* Try to use the smallest displacement type too. */
2438static void
e3bb37b5 2439optimize_disp (void)
29b0f896
AM		 2440{
2441 int op;
3e73aa7c 2442
29b0f896 2443 for (op = i.operands; --op >= 0;)
b300c311 2444 if (i.types[op] & Disp)
252b5132 2445 {
b300c311 2446 if (i.op[op].disps->X_op == O_constant)
252b5132 2447 {
b300c311 2448 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2449
b300c311
L		 2450 if ((i.types[op] & Disp16)
2451 && (disp & ~(offsetT) 0xffff) == 0)
2452 {
2453 /* If this operand is at most 16 bits, convert
2454 to a signed 16 bit number and don't use 64bit
2455 displacement. */
2456 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2457 i.types[op] &= ~Disp64;
2458 }
2459 if ((i.types[op] & Disp32)
2460 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2461 {
2462 /* If this operand is at most 32 bits, convert
2463 to a signed 32 bit number and don't use 64bit
2464 displacement. */
2465 disp &= (((offsetT) 2 << 31) - 1);
2466 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2467 i.types[op] &= ~Disp64;
2468 }
2469 if (!disp && (i.types[op] & BaseIndex))
2470 {
2471 i.types[op] &= ~Disp;
2472 i.op[op].disps = 0;
2473 i.disp_operands--;
2474 }
2475 else if (flag_code == CODE_64BIT)
2476 {
2477 if (fits_in_signed_long (disp))
28a9d8f5
L		 2478 {
2479 i.types[op] &= ~Disp64;
2480 i.types[op] |= Disp32S;
2481 }
b300c311
L		 2482 if (fits_in_unsigned_long (disp))
2483 i.types[op] |= Disp32;
2484 }
2485 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2486 && fits_in_signed_byte (disp))
2487 i.types[op] |= Disp8;
252b5132 2488 }
67a4f2b7
AO		 2489 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2490 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2491 {
2492 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2493 i.op[op].disps, 0, i.reloc[op]);
2494 i.types[op] &= ~Disp;
2495 }
2496 else
b300c311
L		 2497 /* We only support 64bit displacement on constants. */
2498 i.types[op] &= ~Disp64;
252b5132 2499 }
29b0f896
AM		 2500}
2501
2502static int
e3bb37b5 2503match_template (void)
29b0f896
AM		 2504{
2505 /* Points to template once we've found it. */
2506 const template *t;
f48ff2ae 2507 unsigned int overlap0, overlap1, overlap2, overlap3;
29b0f896
AM		 2508 unsigned int found_reverse_match;
2509 int suffix_check;
f48ff2ae 2510 unsigned int operand_types [MAX_OPERANDS];
539e75ad 2511 int addr_prefix_disp;
a5c311ca 2512 unsigned int j;
29b0f896 2513
f48ff2ae
L		 2514#if MAX_OPERANDS != 4
2515# error "MAX_OPERANDS must be 4."
2516#endif
2517
29b0f896
AM		 2518#define MATCH(overlap, given, template) \
2519 ((overlap & ~JumpAbsolute) \
2520 && (((given) & (BaseIndex | JumpAbsolute)) \
2521 == ((overlap) & (BaseIndex | JumpAbsolute))))
2522
2523 /* If given types r0 and r1 are registers they must be of the same type
2524 unless the expected operand type register overlap is null.
2525 Note that Acc in a template matches every size of reg. */
2526#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2527 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2528 || ((g0) & Reg) == ((g1) & Reg) \
2529 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2530
2531 overlap0 = 0;
2532 overlap1 = 0;
2533 overlap2 = 0;
f48ff2ae 2534 overlap3 = 0;
29b0f896 2535 found_reverse_match = 0;
a5c311ca
L		 2536 for (j = 0; j < MAX_OPERANDS; j++)
2537 operand_types [j] = 0;
539e75ad 2538 addr_prefix_disp = -1;
29b0f896
AM		 2539 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2540 ? No_bSuf
2541 : (i.suffix == WORD_MNEM_SUFFIX
2542 ? No_wSuf
2543 : (i.suffix == SHORT_MNEM_SUFFIX
2544 ? No_sSuf
2545 : (i.suffix == LONG_MNEM_SUFFIX
2546 ? No_lSuf
2547 : (i.suffix == QWORD_MNEM_SUFFIX
2548 ? No_qSuf
2549 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2550 ? No_xSuf : 0))))));
2551
45aa61fe 2552 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 2553 {
539e75ad
L		 2554 addr_prefix_disp = -1;
2555
29b0f896
AM		 2556 /* Must have right number of operands. */
2557 if (i.operands != t->operands)
2558 continue;
2559
2560 /* Check the suffix, except for some instructions in intel mode. */
2561 if ((t->opcode_modifier & suffix_check)
2562 && !(intel_syntax
9306ca4a 2563 && (t->opcode_modifier & IgnoreSize)))
29b0f896
AM		 2564 continue;
2565
a5c311ca
L		 2566 for (j = 0; j < MAX_OPERANDS; j++)
2567 operand_types [j] = t->operand_types [j];
539e75ad 2568
45aa61fe
AM		 2569 /* In general, don't allow 64-bit operands in 32-bit mode. */
2570 if (i.suffix == QWORD_MNEM_SUFFIX
2571 && flag_code != CODE_64BIT
2572 && (intel_syntax
2573 ? (!(t->opcode_modifier & IgnoreSize)
2574 && !intel_float_operand (t->name))
2575 : intel_float_operand (t->name) != 2)
539e75ad
L		 2576 && (!(operand_types[0] & (RegMMX | RegXMM))
2577 || !(operand_types[t->operands > 1] & (RegMMX | RegXMM)))
45aa61fe
AM		 2578 && (t->base_opcode != 0x0fc7
2579 || t->extension_opcode != 1 /* cmpxchg8b */))
2580 continue;
2581
29b0f896
AM		 2582 /* Do not verify operands when there are none. */
2583 else if (!t->operands)
2584 {
2585 if (t->cpu_flags & ~cpu_arch_flags)
2586 continue;
2587 /* We've found a match; break out of loop. */
2588 break;
2589 }
252b5132 2590
539e75ad
L		 2591 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
2592 into Disp32/Disp16/Disp32 operand. */
2593 if (i.prefix[ADDR_PREFIX] != 0)
2594 {
a5c311ca 2595 unsigned int DispOn = 0, DispOff = 0;
539e75ad
L		 2596
2597 switch (flag_code)
2598 {
2599 case CODE_16BIT:
2600 DispOn = Disp32;
2601 DispOff = Disp16;
2602 break;
2603 case CODE_32BIT:
2604 DispOn = Disp16;
2605 DispOff = Disp32;
2606 break;
2607 case CODE_64BIT:
2608 DispOn = Disp32;
2609 DispOff = Disp64;
2610 break;
2611 }
2612
f48ff2ae 2613 for (j = 0; j < MAX_OPERANDS; j++)
539e75ad
L		 2614 {
2615 /* There should be only one Disp operand. */
2616 if ((operand_types[j] & DispOff))
2617 {
2618 addr_prefix_disp = j;
2619 operand_types[j] |= DispOn;
2620 operand_types[j] &= ~DispOff;
2621 break;
2622 }
2623 }
2624 }
2625
2626 overlap0 = i.types[0] & operand_types[0];
29b0f896
AM		 2627 switch (t->operands)
2628 {
2629 case 1:
539e75ad 2630 if (!MATCH (overlap0, i.types[0], operand_types[0]))
29b0f896
AM		 2631 continue;
2632 break;
2633 case 2:
8b38ad71
L		 2634 /* xchg %eax, %eax is a special case. It is an aliase for nop
2635 only in 32bit mode and we can use opcode 0x90. In 64bit
2636 mode, we can't use 0x90 for xchg %eax, %eax since it should
2637 zero-extend %eax to %rax. */
2638 if (flag_code == CODE_64BIT
2639 && t->base_opcode == 0x90
2640 && i.types [0] == (Acc | Reg32)
2641 && i.types [1] == (Acc | Reg32))
2642 continue;
29b0f896 2643 case 3:
f48ff2ae 2644 case 4:
539e75ad
L		 2645 overlap1 = i.types[1] & operand_types[1];
2646 if (!MATCH (overlap0, i.types[0], operand_types[0])
2647 || !MATCH (overlap1, i.types[1], operand_types[1])
cb712a9e 2648 /* monitor in SSE3 is a very special case. The first
708587a4 2649 register and the second register may have different
381d071f 2650 sizes. The same applies to crc32 in SSE4.2. */
cb712a9e
L		 2651 || !((t->base_opcode == 0x0f01
2652 && t->extension_opcode == 0xc8)
381d071f 2653 || t->base_opcode == 0xf20f38f1
cb712a9e 2654 || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
539e75ad 2655 operand_types[0],
cb712a9e 2656 overlap1, i.types[1],
539e75ad 2657 operand_types[1])))
29b0f896
AM		 2658 {
2659 /* Check if other direction is valid ... */
2660 if ((t->opcode_modifier & (D | FloatD)) == 0)
2661 continue;
2662
2663 /* Try reversing direction of operands. */
539e75ad
L		 2664 overlap0 = i.types[0] & operand_types[1];
2665 overlap1 = i.types[1] & operand_types[0];
2666 if (!MATCH (overlap0, i.types[0], operand_types[1])
2667 || !MATCH (overlap1, i.types[1], operand_types[0])
29b0f896 2668 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
539e75ad 2669 operand_types[1],
29b0f896 2670 overlap1, i.types[1],
539e75ad 2671 operand_types[0]))
29b0f896
AM		 2672 {
2673 /* Does not match either direction. */
2674 continue;
2675 }
2676 /* found_reverse_match holds which of D or FloatDR
2677 we've found. */
8a2ed489
L		 2678 if ((t->opcode_modifier & D))
2679 found_reverse_match = Opcode_D;
2680 else if ((t->opcode_modifier & FloatD))
2681 found_reverse_match = Opcode_FloatD;
2682 else
2683 found_reverse_match = 0;
2684 if ((t->opcode_modifier & FloatR))
2685 found_reverse_match |= Opcode_FloatR;
29b0f896 2686 }
f48ff2ae 2687 else
29b0f896 2688 {
f48ff2ae 2689 /* Found a forward 2 operand match here. */
d1cbb4db
L		 2690 switch (t->operands)
2691 {
2692 case 4:
2693 overlap3 = i.types[3] & operand_types[3];
2694 case 3:
2695 overlap2 = i.types[2] & operand_types[2];
2696 break;
2697 }
29b0f896 2698
f48ff2ae
L		 2699 switch (t->operands)
2700 {
2701 case 4:
2702 if (!MATCH (overlap3, i.types[3], operand_types[3])
2703 || !CONSISTENT_REGISTER_MATCH (overlap2,
2704 i.types[2],
2705 operand_types[2],
2706 overlap3,
2707 i.types[3],
2708 operand_types[3]))
2709 continue;
2710 case 3:
2711 /* Here we make use of the fact that there are no
2712 reverse match 3 operand instructions, and all 3
2713 operand instructions only need to be checked for
2714 register consistency between operands 2 and 3. */
2715 if (!MATCH (overlap2, i.types[2], operand_types[2])
2716 || !CONSISTENT_REGISTER_MATCH (overlap1,
2717 i.types[1],
2718 operand_types[1],
2719 overlap2,
2720 i.types[2],
2721 operand_types[2]))
2722 continue;
2723 break;
2724 }
29b0f896 2725 }
f48ff2ae 2726 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 2727 slip through to break. */
2728 }
2729 if (t->cpu_flags & ~cpu_arch_flags)
2730 {
2731 found_reverse_match = 0;
2732 continue;
2733 }
2734 /* We've found a match; break out of loop. */
2735 break;
2736 }
2737
2738 if (t == current_templates->end)
2739 {
2740 /* We found no match. */
2741 as_bad (_("suffix or operands invalid for `%s'"),
2742 current_templates->start->name);
2743 return 0;
2744 }
252b5132 2745
29b0f896
AM		 2746 if (!quiet_warnings)
2747 {
2748 if (!intel_syntax
2749 && ((i.types[0] & JumpAbsolute)
539e75ad 2750 != (operand_types[0] & JumpAbsolute)))
29b0f896
AM		 2751 {
2752 as_warn (_("indirect %s without `*'"), t->name);
2753 }
2754
2755 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2756 == (IsPrefix | IgnoreSize))
2757 {
2758 /* Warn them that a data or address size prefix doesn't
2759 affect assembly of the next line of code. */
2760 as_warn (_("stand-alone `%s' prefix"), t->name);
2761 }
2762 }
2763
2764 /* Copy the template we found. */
2765 i.tm = *t;
539e75ad
L		 2766
2767 if (addr_prefix_disp != -1)
2768 i.tm.operand_types[addr_prefix_disp]
2769 = operand_types[addr_prefix_disp];
2770
29b0f896
AM		 2771 if (found_reverse_match)
2772 {
2773 /* If we found a reverse match we must alter the opcode
2774 direction bit. found_reverse_match holds bits to change
2775 (different for int & float insns). */
2776
2777 i.tm.base_opcode ^= found_reverse_match;
2778
539e75ad
L		 2779 i.tm.operand_types[0] = operand_types[1];
2780 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 2781 }
2782
2783 return 1;
2784}
2785
2786static int
e3bb37b5 2787check_string (void)
29b0f896
AM		 2788{
2789 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2790 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2791 {
2792 if (i.seg[0] != NULL && i.seg[0] != &es)
2793 {
2794 as_bad (_("`%s' operand %d must use `%%es' segment"),
2795 i.tm.name,
2796 mem_op + 1);
2797 return 0;
2798 }
2799 /* There's only ever one segment override allowed per instruction.
2800 This instruction possibly has a legal segment override on the
2801 second operand, so copy the segment to where non-string
2802 instructions store it, allowing common code. */
2803 i.seg[0] = i.seg[1];
2804 }
2805 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2806 {
2807 if (i.seg[1] != NULL && i.seg[1] != &es)
2808 {
2809 as_bad (_("`%s' operand %d must use `%%es' segment"),
2810 i.tm.name,
2811 mem_op + 2);
2812 return 0;
2813 }
2814 }
2815 return 1;
2816}
2817
2818static int
543613e9 2819process_suffix (void)
29b0f896
AM		 2820{
2821 /* If matched instruction specifies an explicit instruction mnemonic
2822 suffix, use it. */
2823 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2824 {
2825 if (i.tm.opcode_modifier & Size16)
2826 i.suffix = WORD_MNEM_SUFFIX;
2827 else if (i.tm.opcode_modifier & Size64)
2828 i.suffix = QWORD_MNEM_SUFFIX;
2829 else
2830 i.suffix = LONG_MNEM_SUFFIX;
2831 }
2832 else if (i.reg_operands)
2833 {
2834 /* If there's no instruction mnemonic suffix we try to invent one
2835 based on register operands. */
2836 if (!i.suffix)
2837 {
2838 /* We take i.suffix from the last register operand specified,
2839 Destination register type is more significant than source
381d071f
L		 2840 register type. crc32 in SSE4.2 prefers source register
2841 type. */
2842 if (i.tm.base_opcode == 0xf20f38f1)
2843 {
2844 if ((i.types[0] & Reg))
2845 i.suffix = ((i.types[0] & Reg16) ? WORD_MNEM_SUFFIX :
29b0f896 2846 LONG_MNEM_SUFFIX);
381d071f
L		 2847 }
2848
2849 if (!i.suffix)
2850 {
2851 int op;
2852
2853 for (op = i.operands; --op >= 0;)
2854 if ((i.types[op] & Reg)
2855 && !(i.tm.operand_types[op] & InOutPortReg))
2856 {
2857 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2858 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2859 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2860 LONG_MNEM_SUFFIX);
2861 break;
2862 }
2863 }
29b0f896
AM		 2864 }
2865 else if (i.suffix == BYTE_MNEM_SUFFIX)
2866 {
2867 if (!check_byte_reg ())
2868 return 0;
2869 }
2870 else if (i.suffix == LONG_MNEM_SUFFIX)
2871 {
2872 if (!check_long_reg ())
2873 return 0;
2874 }
2875 else if (i.suffix == QWORD_MNEM_SUFFIX)
2876 {
2877 if (!check_qword_reg ())
2878 return 0;
2879 }
2880 else if (i.suffix == WORD_MNEM_SUFFIX)
2881 {
2882 if (!check_word_reg ())
2883 return 0;
2884 }
2885 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2886 /* Do nothing if the instruction is going to ignore the prefix. */
2887 ;
2888 else
2889 abort ();
2890 }
9306ca4a
JB		 2891 else if ((i.tm.opcode_modifier & DefaultSize)
2892 && !i.suffix
2893 /* exclude fldenv/frstor/fsave/fstenv */
2894 && (i.tm.opcode_modifier & No_sSuf))
29b0f896
AM		 2895 {
2896 i.suffix = stackop_size;
2897 }
9306ca4a
JB		 2898 else if (intel_syntax
2899 && !i.suffix
2900 && ((i.tm.operand_types[0] & JumpAbsolute)
64e74474
AM		 2901 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2902 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2903 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 2904 {
2905 switch (flag_code)
2906 {
2907 case CODE_64BIT:
2908 if (!(i.tm.opcode_modifier & No_qSuf))
2909 {
2910 i.suffix = QWORD_MNEM_SUFFIX;
2911 break;
2912 }
2913 case CODE_32BIT:
2914 if (!(i.tm.opcode_modifier & No_lSuf))
2915 i.suffix = LONG_MNEM_SUFFIX;
2916 break;
2917 case CODE_16BIT:
2918 if (!(i.tm.opcode_modifier & No_wSuf))
2919 i.suffix = WORD_MNEM_SUFFIX;
2920 break;
2921 }
2922 }
252b5132 2923
9306ca4a 2924 if (!i.suffix)
29b0f896 2925 {
9306ca4a
JB		 2926 if (!intel_syntax)
2927 {
2928 if (i.tm.opcode_modifier & W)
2929 {
4eed87de
AM		 2930 as_bad (_("no instruction mnemonic suffix given and "
2931 "no register operands; can't size instruction"));
9306ca4a
JB		 2932 return 0;
2933 }
2934 }
2935 else
2936 {
64e74474
AM		 2937 unsigned int suffixes = (~i.tm.opcode_modifier
2938 & (No_bSuf
2939 | No_wSuf
2940 | No_lSuf
2941 | No_sSuf
2942 | No_xSuf
2943 | No_qSuf));
9306ca4a
JB		 2944
2945 if ((i.tm.opcode_modifier & W)
2946 || ((suffixes & (suffixes - 1))
2947 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2948 {
2949 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2950 return 0;
2951 }
2952 }
29b0f896 2953 }
252b5132 2954
9306ca4a
JB		 2955 /* Change the opcode based on the operand size given by i.suffix;
2956 We don't need to change things for byte insns. */
2957
29b0f896
AM		 2958 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2959 {
2960 /* It's not a byte, select word/dword operation. */
2961 if (i.tm.opcode_modifier & W)
2962 {
2963 if (i.tm.opcode_modifier & ShortForm)
2964 i.tm.base_opcode |= 8;
2965 else
2966 i.tm.base_opcode |= 1;
2967 }
0f3f3d8b 2968
29b0f896
AM		 2969 /* Now select between word & dword operations via the operand
2970 size prefix, except for instructions that will ignore this
2971 prefix anyway. */
cb712a9e
L		 2972 if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8)
2973 {
2974 /* monitor in SSE3 is a very special case. The default size
2975 of AX is the size of mode. The address size override
2976 prefix will change the size of AX. */
2977 if (i.op->regs[0].reg_type &
2978 (flag_code == CODE_32BIT ? Reg16 : Reg32))
2979 if (!add_prefix (ADDR_PREFIX_OPCODE))
2980 return 0;
2981 }
2982 else if (i.suffix != QWORD_MNEM_SUFFIX
2983 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2984 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
2985 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2986 || (flag_code == CODE_64BIT
2987 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 2988 {
2989 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 2990
29b0f896
AM		 2991 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2992 prefix = ADDR_PREFIX_OPCODE;
252b5132 2993
29b0f896
AM		 2994 if (!add_prefix (prefix))
2995 return 0;
24eab124 2996 }
252b5132 2997
29b0f896
AM		 2998 /* Set mode64 for an operand. */
2999 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 3000 && flag_code == CODE_64BIT
29b0f896 3001 && (i.tm.opcode_modifier & NoRex64) == 0)
46e883c5
L		 3002 {
3003 /* Special case for xchg %rax,%rax. It is NOP and doesn't
3004 need rex64. */
3005 if (i.operands != 2
3006 || i.types [0] != (Acc | Reg64)
3007 || i.types [1] != (Acc | Reg64)
13a1e313 3008 || i.tm.base_opcode != 0x90)
f6bee062 3009 i.rex |= REX_W;
46e883c5 3010 }
3e73aa7c 3011
29b0f896
AM		 3012 /* Size floating point instruction. */
3013 if (i.suffix == LONG_MNEM_SUFFIX)
543613e9
NC		 3014 if (i.tm.opcode_modifier & FloatMF)
3015 i.tm.base_opcode ^= 4;
29b0f896 3016 }
7ecd2f8b 3017
29b0f896
AM		 3018 return 1;
3019}
3e73aa7c 3020
29b0f896 3021static int
543613e9 3022check_byte_reg (void)
29b0f896
AM		 3023{
3024 int op;
543613e9 3025
29b0f896
AM		 3026 for (op = i.operands; --op >= 0;)
3027 {
3028 /* If this is an eight bit register, it's OK. If it's the 16 or
3029 32 bit version of an eight bit register, we will just use the
3030 low portion, and that's OK too. */
3031 if (i.types[op] & Reg8)
3032 continue;
3033
3034 /* movzx and movsx should not generate this warning. */
3035 if (intel_syntax
3036 && (i.tm.base_opcode == 0xfb7
3037 || i.tm.base_opcode == 0xfb6
3038 || i.tm.base_opcode == 0x63
3039 || i.tm.base_opcode == 0xfbe
3040 || i.tm.base_opcode == 0xfbf))
3041 continue;
3042
65ec77d2 3043 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
29b0f896
AM		 3044 {
3045 /* Prohibit these changes in the 64bit mode, since the
3046 lowering is more complicated. */
3047 if (flag_code == CODE_64BIT
3048 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3049 {
2ca3ace5
L		 3050 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3051 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3052 i.suffix);
3053 return 0;
3054 }
3055#if REGISTER_WARNINGS
3056 if (!quiet_warnings
3057 && (i.tm.operand_types[op] & InOutPortReg) == 0)
a540244d
L		 3058 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3059 register_prefix,
29b0f896
AM		 3060 (i.op[op].regs + (i.types[op] & Reg16
3061 ? REGNAM_AL - REGNAM_AX
3062 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 3063 register_prefix,
29b0f896
AM		 3064 i.op[op].regs->reg_name,
3065 i.suffix);
3066#endif
3067 continue;
3068 }
3069 /* Any other register is bad. */
3070 if (i.types[op] & (Reg | RegMMX | RegXMM
3071 | SReg2 | SReg3
3072 | Control | Debug | Test
3073 | FloatReg | FloatAcc))
3074 {
a540244d
L		 3075 as_bad (_("`%s%s' not allowed with `%s%c'"),
3076 register_prefix,
29b0f896
AM		 3077 i.op[op].regs->reg_name,
3078 i.tm.name,
3079 i.suffix);
3080 return 0;
3081 }
3082 }
3083 return 1;
3084}
3085
3086static int
e3bb37b5 3087check_long_reg (void)
29b0f896
AM		 3088{
3089 int op;
3090
3091 for (op = i.operands; --op >= 0;)
3092 /* Reject eight bit registers, except where the template requires
3093 them. (eg. movzb) */
3094 if ((i.types[op] & Reg8) != 0
3095 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3096 {
a540244d
L		 3097 as_bad (_("`%s%s' not allowed with `%s%c'"),
3098 register_prefix,
29b0f896
AM		 3099 i.op[op].regs->reg_name,
3100 i.tm.name,
3101 i.suffix);
3102 return 0;
3103 }
3104 /* Warn if the e prefix on a general reg is missing. */
3105 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3106 && (i.types[op] & Reg16) != 0
3107 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3108 {
3109 /* Prohibit these changes in the 64bit mode, since the
3110 lowering is more complicated. */
3111 if (flag_code == CODE_64BIT)
252b5132 3112 {
2ca3ace5
L		 3113 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3114 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3115 i.suffix);
3116 return 0;
252b5132 3117 }
29b0f896
AM		 3118#if REGISTER_WARNINGS
3119 else
a540244d
L		 3120 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3121 register_prefix,
29b0f896 3122 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 3123 register_prefix,
29b0f896
AM		 3124 i.op[op].regs->reg_name,
3125 i.suffix);
3126#endif
252b5132 3127 }
29b0f896
AM		 3128 /* Warn if the r prefix on a general reg is missing. */
3129 else if ((i.types[op] & Reg64) != 0
3130 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 3131 {
2ca3ace5
L		 3132 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3133 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3134 i.suffix);
3135 return 0;
3136 }
3137 return 1;
3138}
252b5132 3139
29b0f896 3140static int
e3bb37b5 3141check_qword_reg (void)
29b0f896
AM		 3142{
3143 int op;
252b5132 3144
29b0f896
AM		 3145 for (op = i.operands; --op >= 0; )
3146 /* Reject eight bit registers, except where the template requires
3147 them. (eg. movzb) */
3148 if ((i.types[op] & Reg8) != 0
3149 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3150 {
a540244d
L		 3151 as_bad (_("`%s%s' not allowed with `%s%c'"),
3152 register_prefix,
29b0f896
AM		 3153 i.op[op].regs->reg_name,
3154 i.tm.name,
3155 i.suffix);
3156 return 0;
3157 }
3158 /* Warn if the e prefix on a general reg is missing. */
3159 else if (((i.types[op] & Reg16) != 0
3160 || (i.types[op] & Reg32) != 0)
3161 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3162 {
3163 /* Prohibit these changes in the 64bit mode, since the
3164 lowering is more complicated. */
2ca3ace5
L		 3165 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3166 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3167 i.suffix);
3168 return 0;
252b5132 3169 }
29b0f896
AM		 3170 return 1;
3171}
252b5132 3172
29b0f896 3173static int
e3bb37b5 3174check_word_reg (void)
29b0f896
AM		 3175{
3176 int op;
3177 for (op = i.operands; --op >= 0;)
3178 /* Reject eight bit registers, except where the template requires
3179 them. (eg. movzb) */
3180 if ((i.types[op] & Reg8) != 0
3181 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3182 {
a540244d
L		 3183 as_bad (_("`%s%s' not allowed with `%s%c'"),
3184 register_prefix,
29b0f896
AM		 3185 i.op[op].regs->reg_name,
3186 i.tm.name,
3187 i.suffix);
3188 return 0;
3189 }
3190 /* Warn if the e prefix on a general reg is present. */
3191 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3192 && (i.types[op] & Reg32) != 0
3193 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 3194 {
29b0f896
AM		 3195 /* Prohibit these changes in the 64bit mode, since the
3196 lowering is more complicated. */
3197 if (flag_code == CODE_64BIT)
252b5132 3198 {
2ca3ace5
L		 3199 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3200 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3201 i.suffix);
3202 return 0;
252b5132 3203 }
29b0f896
AM		 3204 else
3205#if REGISTER_WARNINGS
a540244d
L		 3206 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3207 register_prefix,
29b0f896 3208 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 3209 register_prefix,
29b0f896
AM		 3210 i.op[op].regs->reg_name,
3211 i.suffix);
3212#endif
3213 }
3214 return 1;
3215}
252b5132 3216
29b0f896 3217static int
e3bb37b5 3218finalize_imm (void)
29b0f896
AM		 3219{
3220 unsigned int overlap0, overlap1, overlap2;
3221
3222 overlap0 = i.types[0] & i.tm.operand_types[0];
20f0a1fc 3223 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
29b0f896
AM		 3224 && overlap0 != Imm8 && overlap0 != Imm8S
3225 && overlap0 != Imm16 && overlap0 != Imm32S
3226 && overlap0 != Imm32 && overlap0 != Imm64)
3227 {
3228 if (i.suffix)
3229 {
3230 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
3231 ? Imm8 | Imm8S
3232 : (i.suffix == WORD_MNEM_SUFFIX
3233 ? Imm16
3234 : (i.suffix == QWORD_MNEM_SUFFIX
3235 ? Imm64 | Imm32S
3236 : Imm32)));
3237 }
3238 else if (overlap0 == (Imm16 | Imm32S | Imm32)
3239 || overlap0 == (Imm16 | Imm32)
3240 || overlap0 == (Imm16 | Imm32S))
3241 {
3242 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3243 ? Imm16 : Imm32S);
3244 }
3245 if (overlap0 != Imm8 && overlap0 != Imm8S
3246 && overlap0 != Imm16 && overlap0 != Imm32S
3247 && overlap0 != Imm32 && overlap0 != Imm64)
3248 {
4eed87de
AM		 3249 as_bad (_("no instruction mnemonic suffix given; "
3250 "can't determine immediate size"));
29b0f896
AM		 3251 return 0;
3252 }
3253 }
3254 i.types[0] = overlap0;
3255
3256 overlap1 = i.types[1] & i.tm.operand_types[1];
37edbb65 3257 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
29b0f896
AM		 3258 && overlap1 != Imm8 && overlap1 != Imm8S
3259 && overlap1 != Imm16 && overlap1 != Imm32S
3260 && overlap1 != Imm32 && overlap1 != Imm64)
3261 {
3262 if (i.suffix)
3263 {
3264 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
3265 ? Imm8 | Imm8S
3266 : (i.suffix == WORD_MNEM_SUFFIX
3267 ? Imm16
3268 : (i.suffix == QWORD_MNEM_SUFFIX
3269 ? Imm64 | Imm32S
3270 : Imm32)));
3271 }
3272 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
3273 || overlap1 == (Imm16 | Imm32)
3274 || overlap1 == (Imm16 | Imm32S))
3275 {
3276 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3277 ? Imm16 : Imm32S);
3278 }
3279 if (overlap1 != Imm8 && overlap1 != Imm8S
3280 && overlap1 != Imm16 && overlap1 != Imm32S
3281 && overlap1 != Imm32 && overlap1 != Imm64)
3282 {
4eed87de
AM		 3283 as_bad (_("no instruction mnemonic suffix given; "
3284 "can't determine immediate size %x %c"),
3285 overlap1, i.suffix);
29b0f896
AM		 3286 return 0;
3287 }
3288 }
3289 i.types[1] = overlap1;
3290
3291 overlap2 = i.types[2] & i.tm.operand_types[2];
3292 assert ((overlap2 & Imm) == 0);
3293 i.types[2] = overlap2;
3294
3295 return 1;
3296}
3297
3298static int
e3bb37b5 3299process_operands (void)
29b0f896
AM		 3300{
3301 /* Default segment register this instruction will use for memory
3302 accesses. 0 means unknown. This is only for optimizing out
3303 unnecessary segment overrides. */
3304 const seg_entry *default_seg = 0;
3305
3306 /* The imul $imm, %reg instruction is converted into
3307 imul $imm, %reg, %reg, and the clr %reg instruction
3308 is converted into xor %reg, %reg. */
3309 if (i.tm.opcode_modifier & regKludge)
3310 {
42903f7f
L		 3311 if ((i.tm.cpu_flags & CpuSSE4_1))
3312 {
3313 /* The first operand in instruction blendvpd, blendvps and
3314 pblendvb in SSE4.1 is implicit and must be xmm0. */
3315 assert (i.operands == 3
3316 && i.reg_operands >= 2
3317 && i.types[0] == RegXMM);
3318 if (i.op[0].regs->reg_num != 0)
3319 {
3320 if (intel_syntax)
3321 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
3322 i.tm.name, register_prefix);
3323 else
3324 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
3325 i.tm.name, register_prefix);
3326 return 0;
3327 }
3328 i.op[0] = i.op[1];
3329 i.op[1] = i.op[2];
3330 i.types[0] = i.types[1];
3331 i.types[1] = i.types[2];
3332 i.operands--;
3333 i.reg_operands--;
3334
3335 /* We need to adjust fields in i.tm since they are used by
3336 build_modrm_byte. */
3337 i.tm.operand_types [0] = i.tm.operand_types [1];
3338 i.tm.operand_types [1] = i.tm.operand_types [2];
3339 i.tm.operands--;
3340 }
3341 else
3342 {
3343 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
3344 /* Pretend we saw the extra register operand. */
3345 assert (i.reg_operands == 1
3346 && i.op[first_reg_op + 1].regs == 0);
3347 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
3348 i.types[first_reg_op + 1] = i.types[first_reg_op];
3349 i.operands++;
3350 i.reg_operands++;
3351 }
29b0f896
AM		 3352 }
3353
3354 if (i.tm.opcode_modifier & ShortForm)
3355 {
4eed87de 3356 if (i.types[0] & (SReg2 | SReg3))
29b0f896 3357 {
4eed87de
AM		 3358 if (i.tm.base_opcode == POP_SEG_SHORT
3359 && i.op[0].regs->reg_num == 1)
29b0f896 3360 {
4eed87de
AM		 3361 as_bad (_("you can't `pop %%cs'"));
3362 return 0;
29b0f896 3363 }
4eed87de
AM		 3364 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
3365 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 3366 i.rex |= REX_B;
4eed87de
AM		 3367 }
3368 else
3369 {
3370 /* The register or float register operand is in operand 0 or 1. */
3371 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
3372 /* Register goes in low 3 bits of opcode. */
3373 i.tm.base_opcode |= i.op[op].regs->reg_num;
3374 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 3375 i.rex |= REX_B;
4eed87de 3376 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
29b0f896 3377 {
4eed87de
AM		 3378 /* Warn about some common errors, but press on regardless.
3379 The first case can be generated by gcc (<= 2.8.1). */
3380 if (i.operands == 2)
3381 {
3382 /* Reversed arguments on faddp, fsubp, etc. */
a540244d
L		 3383 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
3384 register_prefix, i.op[1].regs->reg_name,
3385 register_prefix, i.op[0].regs->reg_name);
4eed87de
AM		 3386 }
3387 else
3388 {
3389 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 3390 as_warn (_("translating to `%s %s%s'"), i.tm.name,
3391 register_prefix, i.op[0].regs->reg_name);
4eed87de 3392 }
29b0f896
AM		 3393 }
3394 }
3395 }
3396 else if (i.tm.opcode_modifier & Modrm)
3397 {
3398 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 3399 must be put into the modrm byte). Now, we make the modrm and
3400 index base bytes based on all the info we've collected. */
29b0f896
AM		 3401
3402 default_seg = build_modrm_byte ();
3403 }
8a2ed489 3404 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 3405 {
3406 default_seg = &ds;
3407 }
3408 else if ((i.tm.opcode_modifier & IsString) != 0)
3409 {
3410 /* For the string instructions that allow a segment override
3411 on one of their operands, the default segment is ds. */
3412 default_seg = &ds;
3413 }
3414
30123838
JB		 3415 if ((i.tm.base_opcode == 0x8d /* lea */
3416 || (i.tm.cpu_flags & CpuSVME))
3417 && i.seg[0] && !quiet_warnings)
3418 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 3419
3420 /* If a segment was explicitly specified, and the specified segment
3421 is not the default, use an opcode prefix to select it. If we
3422 never figured out what the default segment is, then default_seg
3423 will be zero at this point, and the specified segment prefix will
3424 always be used. */
29b0f896
AM		 3425 if ((i.seg[0]) && (i.seg[0] != default_seg))
3426 {
3427 if (!add_prefix (i.seg[0]->seg_prefix))
3428 return 0;
3429 }
3430 return 1;
3431}
3432
3433static const seg_entry *
e3bb37b5 3434build_modrm_byte (void)
29b0f896
AM		 3435{
3436 const seg_entry *default_seg = 0;
3437
3438 /* i.reg_operands MUST be the number of real register operands;
3439 implicit registers do not count. */
3440 if (i.reg_operands == 2)
3441 {
3442 unsigned int source, dest;
cab737b9
L		 3443
3444 switch (i.operands)
3445 {
3446 case 2:
3447 source = 0;
3448 break;
3449 case 3:
c81128dc
L		 3450 /* When there are 3 operands, one of them may be immediate,
3451 which may be the first or the last operand. Otherwise,
3452 the first operand must be shift count register (cl). */
3453 assert (i.imm_operands == 1
3454 || (i.imm_operands == 0
3455 && (i.types[0] & ShiftCount)));
3456 source = (i.types[0] & (Imm | ShiftCount)) ? 1 : 0;
cab737b9
L		 3457 break;
3458 case 4:
3459 /* When there are 4 operands, the first two must be immediate
3460 operands. The source operand will be the 3rd one. */
3461 assert (i.imm_operands == 2
3462 && (i.types[0] & Imm)
3463 && (i.types[1] & Imm));
3464 source = 2;
3465 break;
3466 default:
3467 abort ();
3468 }
3469
29b0f896
AM		 3470 dest = source + 1;
3471
3472 i.rm.mode = 3;
3473 /* One of the register operands will be encoded in the i.tm.reg
3474 field, the other in the combined i.tm.mode and i.tm.regmem
3475 fields. If no form of this instruction supports a memory
3476 destination operand, then we assume the source operand may
3477 sometimes be a memory operand and so we need to store the
3478 destination in the i.rm.reg field. */
e72cf3ec 3479 if ((i.tm.operand_types[dest] & (AnyMem | RegMem)) == 0)
29b0f896
AM		 3480 {
3481 i.rm.reg = i.op[dest].regs->reg_num;
3482 i.rm.regmem = i.op[source].regs->reg_num;
3483 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 3484 i.rex |= REX_R;
29b0f896 3485 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 3486 i.rex |= REX_B;
29b0f896
AM		 3487 }
3488 else
3489 {
3490 i.rm.reg = i.op[source].regs->reg_num;
3491 i.rm.regmem = i.op[dest].regs->reg_num;
3492 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 3493 i.rex |= REX_B;
29b0f896 3494 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 3495 i.rex |= REX_R;
29b0f896 3496 }
161a04f6 3497 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5
JB		 3498 {
3499 if (!((i.types[0] | i.types[1]) & Control))
3500 abort ();
161a04f6 3501 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 3502 add_prefix (LOCK_PREFIX_OPCODE);
3503 }
29b0f896
AM		 3504 }
3505 else
3506 { /* If it's not 2 reg operands... */
3507 if (i.mem_operands)
3508 {
3509 unsigned int fake_zero_displacement = 0;
99018f42 3510 unsigned int op;
4eed87de 3511
99018f42
L		 3512 for (op = 0; op < i.operands; op++)
3513 if ((i.types[op] & AnyMem))
3514 break;
3515 assert (op < i.operands);
29b0f896
AM		 3516
3517 default_seg = &ds;
3518
3519 if (i.base_reg == 0)
3520 {
3521 i.rm.mode = 0;
3522 if (!i.disp_operands)
3523 fake_zero_displacement = 1;
3524 if (i.index_reg == 0)
3525 {
3526 /* Operand is just <disp> */
20f0a1fc 3527 if (flag_code == CODE_64BIT)
29b0f896
AM		 3528 {
3529 /* 64bit mode overwrites the 32bit absolute
3530 addressing by RIP relative addressing and
3531 absolute addressing is encoded by one of the
3532 redundant SIB forms. */
3533 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3534 i.sib.base = NO_BASE_REGISTER;
3535 i.sib.index = NO_INDEX_REGISTER;
fc225355
L		 3536 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
3537 ? Disp32S : Disp32);
20f0a1fc 3538 }
fc225355
L		 3539 else if ((flag_code == CODE_16BIT)
3540 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 3541 {
3542 i.rm.regmem = NO_BASE_REGISTER_16;
3543 i.types[op] = Disp16;
3544 }
3545 else
3546 {
3547 i.rm.regmem = NO_BASE_REGISTER;
3548 i.types[op] = Disp32;
29b0f896
AM		 3549 }
3550 }
3551 else /* !i.base_reg && i.index_reg */
3552 {
3553 i.sib.index = i.index_reg->reg_num;
3554 i.sib.base = NO_BASE_REGISTER;
3555 i.sib.scale = i.log2_scale_factor;
3556 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3557 i.types[op] &= ~Disp;
3558 if (flag_code != CODE_64BIT)
3559 i.types[op] |= Disp32; /* Must be 32 bit */
3560 else
3561 i.types[op] |= Disp32S;
3562 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 3563 i.rex |= REX_X;
29b0f896
AM		 3564 }
3565 }
3566 /* RIP addressing for 64bit mode. */
3567 else if (i.base_reg->reg_type == BaseIndex)
3568 {
3569 i.rm.regmem = NO_BASE_REGISTER;
20f0a1fc 3570 i.types[op] &= ~ Disp;
29b0f896 3571 i.types[op] |= Disp32S;
71903a11 3572 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 3573 if (! i.disp_operands)
3574 fake_zero_displacement = 1;
29b0f896
AM		 3575 }
3576 else if (i.base_reg->reg_type & Reg16)
3577 {
3578 switch (i.base_reg->reg_num)
3579 {
3580 case 3: /* (%bx) */
3581 if (i.index_reg == 0)
3582 i.rm.regmem = 7;
3583 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3584 i.rm.regmem = i.index_reg->reg_num - 6;
3585 break;
3586 case 5: /* (%bp) */
3587 default_seg = &ss;
3588 if (i.index_reg == 0)
3589 {
3590 i.rm.regmem = 6;
3591 if ((i.types[op] & Disp) == 0)
3592 {
3593 /* fake (%bp) into 0(%bp) */
3594 i.types[op] |= Disp8;
252b5132 3595 fake_zero_displacement = 1;
29b0f896
AM		 3596 }
3597 }
3598 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3599 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3600 break;
3601 default: /* (%si) -> 4 or (%di) -> 5 */
3602 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3603 }
3604 i.rm.mode = mode_from_disp_size (i.types[op]);
3605 }
3606 else /* i.base_reg and 32/64 bit mode */
3607 {
3608 if (flag_code == CODE_64BIT
3609 && (i.types[op] & Disp))
fc225355
L		 3610 i.types[op] = ((i.types[op] & Disp8)
3611 | (i.prefix[ADDR_PREFIX] == 0
3612 ? Disp32S : Disp32));
20f0a1fc 3613
29b0f896
AM		 3614 i.rm.regmem = i.base_reg->reg_num;
3615 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 3616 i.rex |= REX_B;
29b0f896
AM		 3617 i.sib.base = i.base_reg->reg_num;
3618 /* x86-64 ignores REX prefix bit here to avoid decoder
3619 complications. */
3620 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3621 {
3622 default_seg = &ss;
3623 if (i.disp_operands == 0)
3624 {
3625 fake_zero_displacement = 1;
3626 i.types[op] |= Disp8;
3627 }
3628 }
3629 else if (i.base_reg->reg_num == ESP_REG_NUM)
3630 {
3631 default_seg = &ss;
3632 }
3633 i.sib.scale = i.log2_scale_factor;
3634 if (i.index_reg == 0)
3635 {
3636 /* <disp>(%esp) becomes two byte modrm with no index
3637 register. We've already stored the code for esp
3638 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3639 Any base register besides %esp will not use the
3640 extra modrm byte. */
3641 i.sib.index = NO_INDEX_REGISTER;
3642#if !SCALE1_WHEN_NO_INDEX
3643 /* Another case where we force the second modrm byte. */
3644 if (i.log2_scale_factor)
3645 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 3646#endif
29b0f896
AM		 3647 }
3648 else
3649 {
3650 i.sib.index = i.index_reg->reg_num;
3651 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3652 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 3653 i.rex |= REX_X;
29b0f896 3654 }
67a4f2b7
AO		 3655
3656 if (i.disp_operands
3657 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3658 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
3659 i.rm.mode = 0;
3660 else
3661 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 3662 }
252b5132 3663
29b0f896
AM		 3664 if (fake_zero_displacement)
3665 {
3666 /* Fakes a zero displacement assuming that i.types[op]
3667 holds the correct displacement size. */
3668 expressionS *exp;
3669
3670 assert (i.op[op].disps == 0);
3671 exp = &disp_expressions[i.disp_operands++];
3672 i.op[op].disps = exp;
3673 exp->X_op = O_constant;
3674 exp->X_add_number = 0;
3675 exp->X_add_symbol = (symbolS *) 0;
3676 exp->X_op_symbol = (symbolS *) 0;
3677 }
3678 }
252b5132 3679
29b0f896
AM		 3680 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3681 (if any) based on i.tm.extension_opcode. Again, we must be
3682 careful to make sure that segment/control/debug/test/MMX
3683 registers are coded into the i.rm.reg field. */
3684 if (i.reg_operands)
3685 {
99018f42
L		 3686 unsigned int op;
3687
3688 for (op = 0; op < i.operands; op++)
3689 if ((i.types[op] & (Reg | RegMMX | RegXMM
3690 | SReg2 | SReg3
3691 | Control | Debug | Test)))
3692 break;
3693 assert (op < i.operands);
3694
29b0f896
AM		 3695 /* If there is an extension opcode to put here, the register
3696 number must be put into the regmem field. */
3697 if (i.tm.extension_opcode != None)
3698 {
3699 i.rm.regmem = i.op[op].regs->reg_num;
3700 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 3701 i.rex |= REX_B;
29b0f896
AM		 3702 }
3703 else
3704 {
3705 i.rm.reg = i.op[op].regs->reg_num;
3706 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 3707 i.rex |= REX_R;
29b0f896 3708 }
252b5132 3709
29b0f896
AM		 3710 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3711 must set it to 3 to indicate this is a register operand
3712 in the regmem field. */
3713 if (!i.mem_operands)
3714 i.rm.mode = 3;
3715 }
252b5132 3716
29b0f896
AM		 3717 /* Fill in i.rm.reg field with extension opcode (if any). */
3718 if (i.tm.extension_opcode != None)
3719 i.rm.reg = i.tm.extension_opcode;
3720 }
3721 return default_seg;
3722}
252b5132 3723
29b0f896 3724static void
e3bb37b5 3725output_branch (void)
29b0f896
AM		 3726{
3727 char *p;
3728 int code16;
3729 int prefix;
3730 relax_substateT subtype;
3731 symbolS *sym;
3732 offsetT off;
3733
3734 code16 = 0;
3735 if (flag_code == CODE_16BIT)
3736 code16 = CODE16;
3737
3738 prefix = 0;
3739 if (i.prefix[DATA_PREFIX] != 0)
252b5132 3740 {
29b0f896
AM		 3741 prefix = 1;
3742 i.prefixes -= 1;
3743 code16 ^= CODE16;
252b5132 3744 }
29b0f896
AM		 3745 /* Pentium4 branch hints. */
3746 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3747 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 3748 {
29b0f896
AM		 3749 prefix++;
3750 i.prefixes--;
3751 }
3752 if (i.prefix[REX_PREFIX] != 0)
3753 {
3754 prefix++;
3755 i.prefixes--;
2f66722d
AM		 3756 }
3757
29b0f896
AM		 3758 if (i.prefixes != 0 && !intel_syntax)
3759 as_warn (_("skipping prefixes on this instruction"));
3760
3761 /* It's always a symbol; End frag & setup for relax.
3762 Make sure there is enough room in this frag for the largest
3763 instruction we may generate in md_convert_frag. This is 2
3764 bytes for the opcode and room for the prefix and largest
3765 displacement. */
3766 frag_grow (prefix + 2 + 4);
3767 /* Prefix and 1 opcode byte go in fr_fix. */
3768 p = frag_more (prefix + 1);
3769 if (i.prefix[DATA_PREFIX] != 0)
3770 *p++ = DATA_PREFIX_OPCODE;
3771 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3772 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3773 *p++ = i.prefix[SEG_PREFIX];
3774 if (i.prefix[REX_PREFIX] != 0)
3775 *p++ = i.prefix[REX_PREFIX];
3776 *p = i.tm.base_opcode;
3777
3778 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3779 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3780 else if ((cpu_arch_flags & Cpu386) != 0)
3781 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3782 else
3783 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3784 subtype |= code16;
3e73aa7c 3785
29b0f896
AM		 3786 sym = i.op[0].disps->X_add_symbol;
3787 off = i.op[0].disps->X_add_number;
3e73aa7c 3788
29b0f896
AM		 3789 if (i.op[0].disps->X_op != O_constant
3790 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 3791 {
29b0f896
AM		 3792 /* Handle complex expressions. */
3793 sym = make_expr_symbol (i.op[0].disps);
3794 off = 0;
3795 }
3e73aa7c 3796
29b0f896
AM		 3797 /* 1 possible extra opcode + 4 byte displacement go in var part.
3798 Pass reloc in fr_var. */
3799 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3800}
3e73aa7c 3801
29b0f896 3802static void
e3bb37b5 3803output_jump (void)
29b0f896
AM		 3804{
3805 char *p;
3806 int size;
3e02c1cc 3807 fixS *fixP;
29b0f896
AM		 3808
3809 if (i.tm.opcode_modifier & JumpByte)
3810 {
3811 /* This is a loop or jecxz type instruction. */
3812 size = 1;
3813 if (i.prefix[ADDR_PREFIX] != 0)
3814 {
3815 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3816 i.prefixes -= 1;
3817 }
3818 /* Pentium4 branch hints. */
3819 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3820 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3821 {
3822 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3823 i.prefixes--;
3e73aa7c
JH		 3824 }
3825 }
29b0f896
AM		 3826 else
3827 {
3828 int code16;
3e73aa7c 3829
29b0f896
AM		 3830 code16 = 0;
3831 if (flag_code == CODE_16BIT)
3832 code16 = CODE16;
3e73aa7c 3833
29b0f896
AM		 3834 if (i.prefix[DATA_PREFIX] != 0)
3835 {
3836 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3837 i.prefixes -= 1;
3838 code16 ^= CODE16;
3839 }
252b5132 3840
29b0f896
AM		 3841 size = 4;
3842 if (code16)
3843 size = 2;
3844 }
9fcc94b6 3845
29b0f896
AM		 3846 if (i.prefix[REX_PREFIX] != 0)
3847 {
3848 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3849 i.prefixes -= 1;
3850 }
252b5132 3851
29b0f896
AM		 3852 if (i.prefixes != 0 && !intel_syntax)
3853 as_warn (_("skipping prefixes on this instruction"));
e0890092 3854
29b0f896
AM		 3855 p = frag_more (1 + size);
3856 *p++ = i.tm.base_opcode;
e0890092 3857
3e02c1cc
AM		 3858 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3859 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3860
3861 /* All jumps handled here are signed, but don't use a signed limit
3862 check for 32 and 16 bit jumps as we want to allow wrap around at
3863 4G and 64k respectively. */
3864 if (size == 1)
3865 fixP->fx_signed = 1;
29b0f896 3866}
e0890092 3867
29b0f896 3868static void
e3bb37b5 3869output_interseg_jump (void)
29b0f896
AM		 3870{
3871 char *p;
3872 int size;
3873 int prefix;
3874 int code16;
252b5132 3875
29b0f896
AM		 3876 code16 = 0;
3877 if (flag_code == CODE_16BIT)
3878 code16 = CODE16;
a217f122 3879
29b0f896
AM		 3880 prefix = 0;
3881 if (i.prefix[DATA_PREFIX] != 0)
3882 {
3883 prefix = 1;
3884 i.prefixes -= 1;
3885 code16 ^= CODE16;
3886 }
3887 if (i.prefix[REX_PREFIX] != 0)
3888 {
3889 prefix++;
3890 i.prefixes -= 1;
3891 }
252b5132 3892
29b0f896
AM		 3893 size = 4;
3894 if (code16)
3895 size = 2;
252b5132 3896
29b0f896
AM		 3897 if (i.prefixes != 0 && !intel_syntax)
3898 as_warn (_("skipping prefixes on this instruction"));
252b5132 3899
29b0f896
AM		 3900 /* 1 opcode; 2 segment; offset */
3901 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3902
29b0f896
AM		 3903 if (i.prefix[DATA_PREFIX] != 0)
3904 *p++ = DATA_PREFIX_OPCODE;
252b5132 3905
29b0f896
AM		 3906 if (i.prefix[REX_PREFIX] != 0)
3907 *p++ = i.prefix[REX_PREFIX];
252b5132 3908
29b0f896
AM		 3909 *p++ = i.tm.base_opcode;
3910 if (i.op[1].imms->X_op == O_constant)
3911 {
3912 offsetT n = i.op[1].imms->X_add_number;
252b5132 3913
29b0f896
AM		 3914 if (size == 2
3915 && !fits_in_unsigned_word (n)
3916 && !fits_in_signed_word (n))
3917 {
3918 as_bad (_("16-bit jump out of range"));
3919 return;
3920 }
3921 md_number_to_chars (p, n, size);
3922 }
3923 else
3924 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3925 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3926 if (i.op[0].imms->X_op != O_constant)
3927 as_bad (_("can't handle non absolute segment in `%s'"),
3928 i.tm.name);
3929 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3930}
a217f122 3931
29b0f896 3932static void
e3bb37b5 3933output_insn (void)
29b0f896 3934{
2bbd9c25
JJ		 3935 fragS *insn_start_frag;
3936 offsetT insn_start_off;
3937
29b0f896
AM		 3938 /* Tie dwarf2 debug info to the address at the start of the insn.
3939 We can't do this after the insn has been output as the current
3940 frag may have been closed off. eg. by frag_var. */
3941 dwarf2_emit_insn (0);
3942
2bbd9c25
JJ		 3943 insn_start_frag = frag_now;
3944 insn_start_off = frag_now_fix ();
3945
29b0f896
AM		 3946 /* Output jumps. */
3947 if (i.tm.opcode_modifier & Jump)
3948 output_branch ();
3949 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3950 output_jump ();
3951 else if (i.tm.opcode_modifier & JumpInterSegment)
3952 output_interseg_jump ();
3953 else
3954 {
3955 /* Output normal instructions here. */
3956 char *p;
3957 unsigned char *q;
331d2d0d 3958 unsigned int prefix;
252b5132 3959
42903f7f 3960 /* All opcodes on i386 have either 1 or 2 bytes. SSSE3 and
381d071f
L		 3961 SSE4 instructions have 3 bytes. We may use one more higher
3962 byte to specify a prefix the instruction requires. Exclude
3963 instructions which are in both SSE4 and ABM. */
3964 if ((i.tm.cpu_flags & (CpuSSSE3 | CpuSSE4)) != 0
3965 && (i.tm.cpu_flags & CpuABM) == 0)
bc4bd9ab 3966 {
331d2d0d
L		 3967 if (i.tm.base_opcode & 0xff000000)
3968 {
3969 prefix = (i.tm.base_opcode >> 24) & 0xff;
3970 goto check_prefix;
3971 }
3972 }
3973 else if ((i.tm.base_opcode & 0xff0000) != 0)
3974 {
3975 prefix = (i.tm.base_opcode >> 16) & 0xff;
bc4bd9ab
MK		 3976 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3977 {
64e74474 3978 check_prefix:
bc4bd9ab
MK		 3979 if (prefix != REPE_PREFIX_OPCODE
3980 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3981 add_prefix (prefix);
3982 }
3983 else
331d2d0d 3984 add_prefix (prefix);
0f10071e 3985 }
252b5132 3986
29b0f896
AM		 3987 /* The prefix bytes. */
3988 for (q = i.prefix;
3989 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3990 q++)
3991 {
3992 if (*q)
3993 {
3994 p = frag_more (1);
3995 md_number_to_chars (p, (valueT) *q, 1);
3996 }
3997 }
252b5132 3998
29b0f896
AM		 3999 /* Now the opcode; be careful about word order here! */
4000 if (fits_in_unsigned_byte (i.tm.base_opcode))
4001 {
4002 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
4003 }
4004 else
4005 {
381d071f
L		 4006 if ((i.tm.cpu_flags & (CpuSSSE3 | CpuSSE4)) != 0
4007 && (i.tm.cpu_flags & CpuABM) == 0)
331d2d0d
L		 4008 {
4009 p = frag_more (3);
4010 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4011 }
4012 else
4013 p = frag_more (2);
0f10071e 4014
29b0f896
AM		 4015 /* Put out high byte first: can't use md_number_to_chars! */
4016 *p++ = (i.tm.base_opcode >> 8) & 0xff;
4017 *p = i.tm.base_opcode & 0xff;
4018 }
3e73aa7c 4019
29b0f896
AM		 4020 /* Now the modrm byte and sib byte (if present). */
4021 if (i.tm.opcode_modifier & Modrm)
4022 {
4023 p = frag_more (1);
4024 md_number_to_chars (p,
4025 (valueT) (i.rm.regmem << 0
4026 | i.rm.reg << 3
4027 | i.rm.mode << 6),
4028 1);
4029 /* If i.rm.regmem == ESP (4)
4030 && i.rm.mode != (Register mode)
4031 && not 16 bit
4032 ==> need second modrm byte. */
4033 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
4034 && i.rm.mode != 3
4035 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
4036 {
4037 p = frag_more (1);
4038 md_number_to_chars (p,
4039 (valueT) (i.sib.base << 0
4040 | i.sib.index << 3
4041 | i.sib.scale << 6),
4042 1);
4043 }
4044 }
3e73aa7c 4045
29b0f896 4046 if (i.disp_operands)
2bbd9c25 4047 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 4048
29b0f896 4049 if (i.imm_operands)
2bbd9c25 4050 output_imm (insn_start_frag, insn_start_off);
29b0f896 4051 }
252b5132 4052
29b0f896
AM		 4053#ifdef DEBUG386
4054 if (flag_debug)
4055 {
7b81dfbb 4056 pi ("" /*line*/, &i);
29b0f896
AM		 4057 }
4058#endif /* DEBUG386 */
4059}
252b5132 4060
29b0f896 4061static void
64e74474 4062output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 4063{
4064 char *p;
4065 unsigned int n;
252b5132 4066
29b0f896
AM		 4067 for (n = 0; n < i.operands; n++)
4068 {
4069 if (i.types[n] & Disp)
4070 {
4071 if (i.op[n].disps->X_op == O_constant)
4072 {
4073 int size;
4074 offsetT val;
252b5132 4075
29b0f896
AM		 4076 size = 4;
4077 if (i.types[n] & (Disp8 | Disp16 | Disp64))
4078 {
4079 size = 2;
4080 if (i.types[n] & Disp8)
4081 size = 1;
4082 if (i.types[n] & Disp64)
4083 size = 8;
4084 }
4085 val = offset_in_range (i.op[n].disps->X_add_number,
4086 size);
4087 p = frag_more (size);
4088 md_number_to_chars (p, val, size);
4089 }
4090 else
4091 {
f86103b7 4092 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 4093 int size = 4;
4094 int sign = 0;
4095 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
4096
4097 /* The PC relative address is computed relative
4098 to the instruction boundary, so in case immediate
4099 fields follows, we need to adjust the value. */
4100 if (pcrel && i.imm_operands)
4101 {
4102 int imm_size = 4;
4103 unsigned int n1;
252b5132 4104
29b0f896
AM		 4105 for (n1 = 0; n1 < i.operands; n1++)
4106 if (i.types[n1] & Imm)
252b5132 4107 {
29b0f896 4108 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 4109 {
29b0f896
AM		 4110 imm_size = 2;
4111 if (i.types[n1] & (Imm8 | Imm8S))
4112 imm_size = 1;
4113 if (i.types[n1] & Imm64)
4114 imm_size = 8;
252b5132 4115 }
29b0f896 4116 break;
252b5132 4117 }
29b0f896
AM		 4118 /* We should find the immediate. */
4119 if (n1 == i.operands)
4120 abort ();
4121 i.op[n].disps->X_add_number -= imm_size;
4122 }
520dc8e8 4123
29b0f896
AM		 4124 if (i.types[n] & Disp32S)
4125 sign = 1;
3e73aa7c 4126
29b0f896
AM		 4127 if (i.types[n] & (Disp16 | Disp64))
4128 {
4129 size = 2;
4130 if (i.types[n] & Disp64)
4131 size = 8;
4132 }
520dc8e8 4133
29b0f896 4134 p = frag_more (size);
2bbd9c25 4135 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 4136 if (GOT_symbol
2bbd9c25 4137 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 4138 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4139 || reloc_type == BFD_RELOC_X86_64_32S
4140 || (reloc_type == BFD_RELOC_64
4141 && object_64bit))
d6ab8113
JB		 4142 && (i.op[n].disps->X_op == O_symbol
4143 || (i.op[n].disps->X_op == O_add
4144 && ((symbol_get_value_expression
4145 (i.op[n].disps->X_op_symbol)->X_op)
4146 == O_subtract))))
4147 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 4148 {
4149 offsetT add;
4150
4151 if (insn_start_frag == frag_now)
4152 add = (p - frag_now->fr_literal) - insn_start_off;
4153 else
4154 {
4155 fragS *fr;
4156
4157 add = insn_start_frag->fr_fix - insn_start_off;
4158 for (fr = insn_start_frag->fr_next;
4159 fr && fr != frag_now; fr = fr->fr_next)
4160 add += fr->fr_fix;
4161 add += p - frag_now->fr_literal;
4162 }
4163
4fa24527 4164 if (!object_64bit)
7b81dfbb
AJ		 4165 {
4166 reloc_type = BFD_RELOC_386_GOTPC;
4167 i.op[n].imms->X_add_number += add;
4168 }
4169 else if (reloc_type == BFD_RELOC_64)
4170 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 4171 else
7b81dfbb
AJ		 4172 /* Don't do the adjustment for x86-64, as there
4173 the pcrel addressing is relative to the _next_
4174 insn, and that is taken care of in other code. */
d6ab8113 4175 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 4176 }
062cd5e7 4177 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 4178 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 4179 }
4180 }
4181 }
4182}
252b5132 4183
29b0f896 4184static void
64e74474 4185output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 4186{
4187 char *p;
4188 unsigned int n;
252b5132 4189
29b0f896
AM		 4190 for (n = 0; n < i.operands; n++)
4191 {
4192 if (i.types[n] & Imm)
4193 {
4194 if (i.op[n].imms->X_op == O_constant)
4195 {
4196 int size;
4197 offsetT val;
b4cac588 4198
29b0f896
AM		 4199 size = 4;
4200 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4201 {
4202 size = 2;
4203 if (i.types[n] & (Imm8 | Imm8S))
4204 size = 1;
4205 else if (i.types[n] & Imm64)
4206 size = 8;
4207 }
4208 val = offset_in_range (i.op[n].imms->X_add_number,
4209 size);
4210 p = frag_more (size);
4211 md_number_to_chars (p, val, size);
4212 }
4213 else
4214 {
4215 /* Not absolute_section.
4216 Need a 32-bit fixup (don't support 8bit
4217 non-absolute imms). Try to support other
4218 sizes ... */
f86103b7 4219 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 4220 int size = 4;
4221 int sign = 0;
4222
4223 if ((i.types[n] & (Imm32S))
a7d61044
JB		 4224 && (i.suffix == QWORD_MNEM_SUFFIX
4225 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
29b0f896
AM		 4226 sign = 1;
4227 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4228 {
4229 size = 2;
4230 if (i.types[n] & (Imm8 | Imm8S))
4231 size = 1;
4232 if (i.types[n] & Imm64)
4233 size = 8;
4234 }
520dc8e8 4235
29b0f896
AM		 4236 p = frag_more (size);
4237 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 4238
2bbd9c25
JJ		 4239 /* This is tough to explain. We end up with this one if we
4240 * have operands that look like
4241 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4242 * obtain the absolute address of the GOT, and it is strongly
4243 * preferable from a performance point of view to avoid using
4244 * a runtime relocation for this. The actual sequence of
4245 * instructions often look something like:
4246 *
4247 * call .L66
4248 * .L66:
4249 * popl %ebx
4250 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4251 *
4252 * The call and pop essentially return the absolute address
4253 * of the label .L66 and store it in %ebx. The linker itself
4254 * will ultimately change the first operand of the addl so
4255 * that %ebx points to the GOT, but to keep things simple, the
4256 * .o file must have this operand set so that it generates not
4257 * the absolute address of .L66, but the absolute address of
4258 * itself. This allows the linker itself simply treat a GOTPC
4259 * relocation as asking for a pcrel offset to the GOT to be
4260 * added in, and the addend of the relocation is stored in the
4261 * operand field for the instruction itself.
4262 *
4263 * Our job here is to fix the operand so that it would add
4264 * the correct offset so that %ebx would point to itself. The
4265 * thing that is tricky is that .-.L66 will point to the
4266 * beginning of the instruction, so we need to further modify
4267 * the operand so that it will point to itself. There are
4268 * other cases where you have something like:
4269 *
4270 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4271 *
4272 * and here no correction would be required. Internally in
4273 * the assembler we treat operands of this form as not being
4274 * pcrel since the '.' is explicitly mentioned, and I wonder
4275 * whether it would simplify matters to do it this way. Who
4276 * knows. In earlier versions of the PIC patches, the
4277 * pcrel_adjust field was used to store the correction, but
4278 * since the expression is not pcrel, I felt it would be
4279 * confusing to do it this way. */
4280
d6ab8113 4281 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4282 || reloc_type == BFD_RELOC_X86_64_32S
4283 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 4284 && GOT_symbol
4285 && GOT_symbol == i.op[n].imms->X_add_symbol
4286 && (i.op[n].imms->X_op == O_symbol
4287 || (i.op[n].imms->X_op == O_add
4288 && ((symbol_get_value_expression
4289 (i.op[n].imms->X_op_symbol)->X_op)
4290 == O_subtract))))
4291 {
2bbd9c25
JJ		 4292 offsetT add;
4293
4294 if (insn_start_frag == frag_now)
4295 add = (p - frag_now->fr_literal) - insn_start_off;
4296 else
4297 {
4298 fragS *fr;
4299
4300 add = insn_start_frag->fr_fix - insn_start_off;
4301 for (fr = insn_start_frag->fr_next;
4302 fr && fr != frag_now; fr = fr->fr_next)
4303 add += fr->fr_fix;
4304 add += p - frag_now->fr_literal;
4305 }
4306
4fa24527 4307 if (!object_64bit)
d6ab8113 4308 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 4309 else if (size == 4)
d6ab8113 4310 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 4311 else if (size == 8)
4312 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 4313 i.op[n].imms->X_add_number += add;
29b0f896 4314 }
29b0f896
AM		 4315 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4316 i.op[n].imms, 0, reloc_type);
4317 }
4318 }
4319 }
252b5132
RH		 4320}
4321\f
d182319b
JB		 4322/* x86_cons_fix_new is called via the expression parsing code when a
4323 reloc is needed. We use this hook to get the correct .got reloc. */
4324static enum bfd_reloc_code_real got_reloc = NO_RELOC;
4325static int cons_sign = -1;
4326
4327void
e3bb37b5 4328x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 4329 expressionS *exp)
d182319b
JB		 4330{
4331 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
4332
4333 got_reloc = NO_RELOC;
4334
4335#ifdef TE_PE
4336 if (exp->X_op == O_secrel)
4337 {
4338 exp->X_op = O_symbol;
4339 r = BFD_RELOC_32_SECREL;
4340 }
4341#endif
4342
4343 fix_new_exp (frag, off, len, exp, 0, r);
4344}
4345
718ddfc0
JB		 4346#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4347# define lex_got(reloc, adjust, types) NULL
4348#else
f3c180ae
AM		 4349/* Parse operands of the form
4350 <symbol>@GOTOFF+<nnn>
4351 and similar .plt or .got references.
4352
4353 If we find one, set up the correct relocation in RELOC and copy the
4354 input string, minus the `@GOTOFF' into a malloc'd buffer for
4355 parsing by the calling routine. Return this buffer, and if ADJUST
4356 is non-null set it to the length of the string we removed from the
4357 input line. Otherwise return NULL. */
4358static char *
3956db08 4359lex_got (enum bfd_reloc_code_real *reloc,
64e74474
AM		 4360 int *adjust,
4361 unsigned int *types)
f3c180ae 4362{
7b81dfbb
AJ		 4363 /* Some of the relocations depend on the size of what field is to
4364 be relocated. But in our callers i386_immediate and i386_displacement
4365 we don't yet know the operand size (this will be set by insn
4366 matching). Hence we record the word32 relocation here,
4367 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 4368 static const struct {
4369 const char *str;
4fa24527 4370 const enum bfd_reloc_code_real rel[2];
3956db08 4371 const unsigned int types64;
f3c180ae 4372 } gotrel[] = {
4eed87de
AM		 4373 { "PLTOFF", { 0,
4374 BFD_RELOC_X86_64_PLTOFF64 },
4375 Imm64 },
4376 { "PLT", { BFD_RELOC_386_PLT32,
4377 BFD_RELOC_X86_64_PLT32 },
4378 Imm32 | Imm32S | Disp32 },
4379 { "GOTPLT", { 0,
4380 BFD_RELOC_X86_64_GOTPLT64 },
4381 Imm64 | Disp64 },
4382 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
4383 BFD_RELOC_X86_64_GOTOFF64 },
4384 Imm64 | Disp64 },
4385 { "GOTPCREL", { 0,
4386 BFD_RELOC_X86_64_GOTPCREL },
4387 Imm32 | Imm32S | Disp32 },
4388 { "TLSGD", { BFD_RELOC_386_TLS_GD,
4389 BFD_RELOC_X86_64_TLSGD },
4390 Imm32 | Imm32S | Disp32 },
4391 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
4392 0 },
4393 0 },
4394 { "TLSLD", { 0,
4395 BFD_RELOC_X86_64_TLSLD },
4396 Imm32 | Imm32S | Disp32 },
4397 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
4398 BFD_RELOC_X86_64_GOTTPOFF },
4399 Imm32 | Imm32S | Disp32 },
4400 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
4401 BFD_RELOC_X86_64_TPOFF32 },
4402 Imm32 | Imm32S | Imm64 | Disp32 | Disp64 },
4403 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
4404 0 },
4405 0 },
4406 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
4407 BFD_RELOC_X86_64_DTPOFF32 },
4408 Imm32 | Imm32S | Imm64 | Disp32 | Disp64 },
4409 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
4410 0 },
4411 0 },
4412 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
4413 0 },
4414 0 },
4415 { "GOT", { BFD_RELOC_386_GOT32,
4416 BFD_RELOC_X86_64_GOT32 },
4417 Imm32 | Imm32S | Disp32 | Imm64 },
4418 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
4419 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
4420 Imm32 | Imm32S | Disp32 },
4421 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
4422 BFD_RELOC_X86_64_TLSDESC_CALL },
4423 Imm32 | Imm32S | Disp32 }
f3c180ae
AM		 4424 };
4425 char *cp;
4426 unsigned int j;
4427
718ddfc0
JB		 4428 if (!IS_ELF)
4429 return NULL;
4430
f3c180ae
AM		 4431 for (cp = input_line_pointer; *cp != '@'; cp++)
4432 if (is_end_of_line[(unsigned char) *cp])
4433 return NULL;
4434
4435 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
4436 {
4437 int len;
4438
4439 len = strlen (gotrel[j].str);
28f81592 4440 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 4441 {
4fa24527 4442 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 4443 {
28f81592
AM		 4444 int first, second;
4445 char *tmpbuf, *past_reloc;
f3c180ae 4446
4fa24527 4447 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 4448 if (adjust)
4449 *adjust = len;
f3c180ae 4450
3956db08
JB		 4451 if (types)
4452 {
4453 if (flag_code != CODE_64BIT)
4eed87de 4454 *types = Imm32 | Disp32;
3956db08
JB		 4455 else
4456 *types = gotrel[j].types64;
4457 }
4458
f3c180ae
AM		 4459 if (GOT_symbol == NULL)
4460 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
4461
4462 /* Replace the relocation token with ' ', so that
4463 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 4464
4465 /* The length of the first part of our input line. */
f3c180ae 4466 first = cp - input_line_pointer;
28f81592
AM		 4467
4468 /* The second part goes from after the reloc token until
4469 (and including) an end_of_line char. Don't use strlen
4470 here as the end_of_line char may not be a NUL. */
4471 past_reloc = cp + 1 + len;
4472 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
4473 ;
4474 second = cp - past_reloc;
4475
4476 /* Allocate and copy string. The trailing NUL shouldn't
4477 be necessary, but be safe. */
4478 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 4479 memcpy (tmpbuf, input_line_pointer, first);
4480 tmpbuf[first] = ' ';
28f81592
AM		 4481 memcpy (tmpbuf + first + 1, past_reloc, second);
4482 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 4483 return tmpbuf;
4484 }
4485
4fa24527
JB		 4486 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4487 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 4488 return NULL;
4489 }
4490 }
4491
4492 /* Might be a symbol version string. Don't as_bad here. */
4493 return NULL;
4494}
4495
f3c180ae 4496void
e3bb37b5 4497x86_cons (expressionS *exp, int size)
f3c180ae 4498{
4fa24527 4499 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 4500 {
4501 /* Handle @GOTOFF and the like in an expression. */
4502 char *save;
4503 char *gotfree_input_line;
4504 int adjust;
4505
4506 save = input_line_pointer;
3956db08 4507 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 4508 if (gotfree_input_line)
4509 input_line_pointer = gotfree_input_line;
4510
4511 expression (exp);
4512
4513 if (gotfree_input_line)
4514 {
4515 /* expression () has merrily parsed up to the end of line,
4516 or a comma - in the wrong buffer. Transfer how far
4517 input_line_pointer has moved to the right buffer. */
4518 input_line_pointer = (save
4519 + (input_line_pointer - gotfree_input_line)
4520 + adjust);
4521 free (gotfree_input_line);
4522 }
4523 }
4524 else
4525 expression (exp);
4526}
4527#endif
4528
d182319b 4529static void signed_cons (int size)
6482c264 4530{
d182319b
JB		 4531 if (flag_code == CODE_64BIT)
4532 cons_sign = 1;
4533 cons (size);
4534 cons_sign = -1;
6482c264
NC		 4535}
4536
d182319b 4537#ifdef TE_PE
6482c264
NC		 4538static void
4539pe_directive_secrel (dummy)
4540 int dummy ATTRIBUTE_UNUSED;
4541{
4542 expressionS exp;
4543
4544 do
4545 {
4546 expression (&exp);
4547 if (exp.X_op == O_symbol)
4548 exp.X_op = O_secrel;
4549
4550 emit_expr (&exp, 4);
4551 }
4552 while (*input_line_pointer++ == ',');
4553
4554 input_line_pointer--;
4555 demand_empty_rest_of_line ();
4556}
6482c264
NC		 4557#endif
4558
252b5132 4559static int
70e41ade 4560i386_immediate (char *imm_start)
252b5132
RH		 4561{
4562 char *save_input_line_pointer;
f3c180ae 4563 char *gotfree_input_line;
252b5132 4564 segT exp_seg = 0;
47926f60 4565 expressionS *exp;
3956db08 4566 unsigned int types = ~0U;
252b5132
RH		 4567
4568 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
4569 {
31b2323c
L		 4570 as_bad (_("at most %d immediate operands are allowed"),
4571 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 4572 return 0;
4573 }
4574
4575 exp = &im_expressions[i.imm_operands++];
520dc8e8 4576 i.op[this_operand].imms = exp;
252b5132
RH		 4577
4578 if (is_space_char (*imm_start))
4579 ++imm_start;
4580
4581 save_input_line_pointer = input_line_pointer;
4582 input_line_pointer = imm_start;
4583
3956db08 4584 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4585 if (gotfree_input_line)
4586 input_line_pointer = gotfree_input_line;
252b5132
RH		 4587
4588 exp_seg = expression (exp);
4589
83183c0c 4590 SKIP_WHITESPACE ();
252b5132 4591 if (*input_line_pointer)
f3c180ae 4592 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 4593
4594 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 4595 if (gotfree_input_line)
4596 free (gotfree_input_line);
252b5132 4597
2daf4fd8 4598 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 4599 {
47926f60 4600 /* Missing or bad expr becomes absolute 0. */
d0b47220 4601 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 4602 imm_start);
252b5132
RH		 4603 exp->X_op = O_constant;
4604 exp->X_add_number = 0;
4605 exp->X_add_symbol = (symbolS *) 0;
4606 exp->X_op_symbol = (symbolS *) 0;
252b5132 4607 }
3e73aa7c 4608 else if (exp->X_op == O_constant)
252b5132 4609 {
47926f60 4610 /* Size it properly later. */
3e73aa7c
JH		 4611 i.types[this_operand] |= Imm64;
4612 /* If BFD64, sign extend val. */
4eed87de
AM		 4613 if (!use_rela_relocations
4614 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4615 exp->X_add_number
4616 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 4617 }
4c63da97 4618#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 4619 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4620 && exp_seg != absolute_section
47926f60 4621 && exp_seg != text_section
24eab124
AM		 4622 && exp_seg != data_section
4623 && exp_seg != bss_section
4624 && exp_seg != undefined_section
f86103b7 4625 && !bfd_is_com_section (exp_seg))
252b5132 4626 {
d0b47220 4627 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 4628 return 0;
4629 }
4630#endif
bb8f5920
L		 4631 else if (!intel_syntax && exp->X_op == O_register)
4632 {
4633 as_bad (_("illegal immediate register operand %s"), imm_start);
4634 return 0;
4635 }
252b5132
RH		 4636 else
4637 {
4638 /* This is an address. The size of the address will be
24eab124 4639 determined later, depending on destination register,
3e73aa7c
JH		 4640 suffix, or the default for the section. */
4641 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3956db08 4642 i.types[this_operand] &= types;
252b5132
RH		 4643 }
4644
4645 return 1;
4646}
4647
551c1ca1 4648static char *
e3bb37b5 4649i386_scale (char *scale)
252b5132 4650{
551c1ca1
AM		 4651 offsetT val;
4652 char *save = input_line_pointer;
252b5132 4653
551c1ca1
AM		 4654 input_line_pointer = scale;
4655 val = get_absolute_expression ();
4656
4657 switch (val)
252b5132 4658 {
551c1ca1 4659 case 1:
252b5132
RH		 4660 i.log2_scale_factor = 0;
4661 break;
551c1ca1 4662 case 2:
252b5132
RH		 4663 i.log2_scale_factor = 1;
4664 break;
551c1ca1 4665 case 4:
252b5132
RH		 4666 i.log2_scale_factor = 2;
4667 break;
551c1ca1 4668 case 8:
252b5132
RH		 4669 i.log2_scale_factor = 3;
4670 break;
4671 default:
a724f0f4
JB		 4672 {
4673 char sep = *input_line_pointer;
4674
4675 *input_line_pointer = '\0';
4676 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4677 scale);
4678 *input_line_pointer = sep;
4679 input_line_pointer = save;
4680 return NULL;
4681 }
252b5132 4682 }
29b0f896 4683 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 4684 {
4685 as_warn (_("scale factor of %d without an index register"),
24eab124 4686 1 << i.log2_scale_factor);
252b5132
RH		 4687#if SCALE1_WHEN_NO_INDEX
4688 i.log2_scale_factor = 0;
4689#endif
4690 }
551c1ca1
AM		 4691 scale = input_line_pointer;
4692 input_line_pointer = save;
4693 return scale;
252b5132
RH		 4694}
4695
252b5132 4696static int
e3bb37b5 4697i386_displacement (char *disp_start, char *disp_end)
252b5132 4698{
29b0f896 4699 expressionS *exp;
252b5132
RH		 4700 segT exp_seg = 0;
4701 char *save_input_line_pointer;
f3c180ae 4702 char *gotfree_input_line;
e05278af 4703 int bigdisp, override;
3956db08 4704 unsigned int types = Disp;
252b5132 4705
31b2323c
L		 4706 if (i.disp_operands == MAX_MEMORY_OPERANDS)
4707 {
4708 as_bad (_("at most %d displacement operands are allowed"),
4709 MAX_MEMORY_OPERANDS);
4710 return 0;
4711 }
4712
e05278af
JB		 4713 if ((i.types[this_operand] & JumpAbsolute)
4714 || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
4715 {
4716 bigdisp = Disp32;
4717 override = (i.prefix[ADDR_PREFIX] != 0);
4718 }
4719 else
4720 {
4721 /* For PC-relative branches, the width of the displacement
4722 is dependent upon data size, not address size. */
4723 bigdisp = 0;
4724 override = (i.prefix[DATA_PREFIX] != 0);
4725 }
3e73aa7c 4726 if (flag_code == CODE_64BIT)
7ecd2f8b 4727 {
e05278af 4728 if (!bigdisp)
64e74474
AM		 4729 bigdisp = ((override || i.suffix == WORD_MNEM_SUFFIX)
4730 ? Disp16
4731 : Disp32S | Disp32);
e05278af 4732 else if (!override)
3956db08 4733 bigdisp = Disp64 | Disp32S | Disp32;
7ecd2f8b 4734 }
e05278af
JB		 4735 else
4736 {
4737 if (!bigdisp)
4738 {
4739 if (!override)
4740 override = (i.suffix == (flag_code != CODE_16BIT
4741 ? WORD_MNEM_SUFFIX
4742 : LONG_MNEM_SUFFIX));
4743 bigdisp = Disp32;
4744 }
4745 if ((flag_code == CODE_16BIT) ^ override)
4746 bigdisp = Disp16;
4747 }
252b5132
RH		 4748 i.types[this_operand] |= bigdisp;
4749
4750 exp = &disp_expressions[i.disp_operands];
520dc8e8 4751 i.op[this_operand].disps = exp;
252b5132
RH		 4752 i.disp_operands++;
4753 save_input_line_pointer = input_line_pointer;
4754 input_line_pointer = disp_start;
4755 END_STRING_AND_SAVE (disp_end);
4756
4757#ifndef GCC_ASM_O_HACK
4758#define GCC_ASM_O_HACK 0
4759#endif
4760#if GCC_ASM_O_HACK
4761 END_STRING_AND_SAVE (disp_end + 1);
4762 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 4763 && displacement_string_end[-1] == '+')
252b5132
RH		 4764 {
4765 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 4766 constraint within gcc asm statements.
4767 For instance:
4768
4769 #define _set_tssldt_desc(n,addr,limit,type) \
4770 __asm__ __volatile__ ( \
4771 "movw %w2,%0\n\t" \
4772 "movw %w1,2+%0\n\t" \
4773 "rorl $16,%1\n\t" \
4774 "movb %b1,4+%0\n\t" \
4775 "movb %4,5+%0\n\t" \
4776 "movb $0,6+%0\n\t" \
4777 "movb %h1,7+%0\n\t" \
4778 "rorl $16,%1" \
4779 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4780
4781 This works great except that the output assembler ends
4782 up looking a bit weird if it turns out that there is
4783 no offset. You end up producing code that looks like:
4784
4785 #APP
4786 movw $235,(%eax)
4787 movw %dx,2+(%eax)
4788 rorl $16,%edx
4789 movb %dl,4+(%eax)
4790 movb $137,5+(%eax)
4791 movb $0,6+(%eax)
4792 movb %dh,7+(%eax)
4793 rorl $16,%edx
4794 #NO_APP
4795
47926f60 4796 So here we provide the missing zero. */
24eab124
AM		 4797
4798 *displacement_string_end = '0';
252b5132
RH		 4799 }
4800#endif
3956db08 4801 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4802 if (gotfree_input_line)
4803 input_line_pointer = gotfree_input_line;
252b5132 4804
24eab124 4805 exp_seg = expression (exp);
252b5132 4806
636c26b0
AM		 4807 SKIP_WHITESPACE ();
4808 if (*input_line_pointer)
4809 as_bad (_("junk `%s' after expression"), input_line_pointer);
4810#if GCC_ASM_O_HACK
4811 RESTORE_END_STRING (disp_end + 1);
4812#endif
4813 RESTORE_END_STRING (disp_end);
4814 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 4815 if (gotfree_input_line)
4816 free (gotfree_input_line);
636c26b0 4817
24eab124
AM		 4818 /* We do this to make sure that the section symbol is in
4819 the symbol table. We will ultimately change the relocation
47926f60 4820 to be relative to the beginning of the section. */
1ae12ab7 4821 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 4822 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4823 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 4824 {
636c26b0
AM		 4825 if (exp->X_op != O_symbol)
4826 {
4827 as_bad (_("bad expression used with @%s"),
4828 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4829 ? "GOTPCREL"
4830 : "GOTOFF"));
4831 return 0;
4832 }
4833
e5cb08ac 4834 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 4835 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4836 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 4837 exp->X_op = O_subtract;
4838 exp->X_op_symbol = GOT_symbol;
1ae12ab7 4839 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 4840 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 4841 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4842 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 4843 else
29b0f896 4844 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 4845 }
252b5132 4846
2daf4fd8
AM		 4847 if (exp->X_op == O_absent || exp->X_op == O_big)
4848 {
47926f60 4849 /* Missing or bad expr becomes absolute 0. */
d0b47220 4850 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 4851 disp_start);
4852 exp->X_op = O_constant;
4853 exp->X_add_number = 0;
4854 exp->X_add_symbol = (symbolS *) 0;
4855 exp->X_op_symbol = (symbolS *) 0;
4856 }
4857
4c63da97 4858#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 4859 if (exp->X_op != O_constant
45288df1 4860 && OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4861 && exp_seg != absolute_section
45288df1
AM		 4862 && exp_seg != text_section
4863 && exp_seg != data_section
4864 && exp_seg != bss_section
31312f95 4865 && exp_seg != undefined_section
f86103b7 4866 && !bfd_is_com_section (exp_seg))
24eab124 4867 {
d0b47220 4868 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
24eab124
AM		 4869 return 0;
4870 }
252b5132 4871#endif
3956db08
JB		 4872
4873 if (!(i.types[this_operand] & ~Disp))
4874 i.types[this_operand] &= types;
4875
252b5132
RH		 4876 return 1;
4877}
4878
eecb386c 4879/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 4880 Return 1 on success, 0 on a failure. */
4881
252b5132 4882static int
e3bb37b5 4883i386_index_check (const char *operand_string)
252b5132 4884{
3e73aa7c 4885 int ok;
24eab124 4886#if INFER_ADDR_PREFIX
eecb386c
AM		 4887 int fudged = 0;
4888
24eab124
AM		 4889 tryprefix:
4890#endif
3e73aa7c 4891 ok = 1;
30123838
JB		 4892 if ((current_templates->start->cpu_flags & CpuSVME)
4893 && current_templates->end[-1].operand_types[0] == AnyMem)
4894 {
4895 /* Memory operands of SVME insns are special in that they only allow
4896 rAX as their memory address and ignore any segment override. */
4897 unsigned RegXX;
4898
4899 /* SKINIT is even more restrictive: it always requires EAX. */
4900 if (strcmp (current_templates->start->name, "skinit") == 0)
4901 RegXX = Reg32;
4902 else if (flag_code == CODE_64BIT)
4903 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4904 else
64e74474
AM		 4905 RegXX = ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4906 ? Reg16
4907 : Reg32);
30123838
JB		 4908 if (!i.base_reg
4909 || !(i.base_reg->reg_type & Acc)
4910 || !(i.base_reg->reg_type & RegXX)
4911 || i.index_reg
4912 || (i.types[0] & Disp))
4913 ok = 0;
4914 }
4915 else if (flag_code == CODE_64BIT)
64e74474
AM		 4916 {
4917 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4918
4919 if ((i.base_reg
4920 && ((i.base_reg->reg_type & RegXX) == 0)
4921 && (i.base_reg->reg_type != BaseIndex
4922 || i.index_reg))
4923 || (i.index_reg
4924 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4925 != (RegXX | BaseIndex))))
4926 ok = 0;
3e73aa7c
JH		 4927 }
4928 else
4929 {
4930 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4931 {
4932 /* 16bit checks. */
4933 if ((i.base_reg
29b0f896
AM		 4934 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4935 != (Reg16 | BaseIndex)))
3e73aa7c 4936 || (i.index_reg
29b0f896
AM		 4937 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4938 != (Reg16 | BaseIndex))
4939 || !(i.base_reg
4940 && i.base_reg->reg_num < 6
4941 && i.index_reg->reg_num >= 6
4942 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 4943 ok = 0;
4944 }
4945 else
e5cb08ac 4946 {
3e73aa7c
JH		 4947 /* 32bit checks. */
4948 if ((i.base_reg
4949 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4950 || (i.index_reg
29b0f896
AM		 4951 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4952 != (Reg32 | BaseIndex))))
e5cb08ac 4953 ok = 0;
3e73aa7c
JH		 4954 }
4955 }
4956 if (!ok)
24eab124
AM		 4957 {
4958#if INFER_ADDR_PREFIX
20f0a1fc 4959 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 4960 {
4961 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4962 i.prefixes += 1;
b23bac36
AM		 4963 /* Change the size of any displacement too. At most one of
4964 Disp16 or Disp32 is set.
4965 FIXME. There doesn't seem to be any real need for separate
4966 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 4967 Removing them would probably clean up the code quite a lot. */
4eed87de
AM		 4968 if (flag_code != CODE_64BIT
4969 && (i.types[this_operand] & (Disp16 | Disp32)))
64e74474 4970 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 4971 fudged = 1;
24eab124
AM		 4972 goto tryprefix;
4973 }
eecb386c
AM		 4974 if (fudged)
4975 as_bad (_("`%s' is not a valid base/index expression"),
4976 operand_string);
4977 else
c388dee8 4978#endif
eecb386c
AM		 4979 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4980 operand_string,
3e73aa7c 4981 flag_code_names[flag_code]);
24eab124 4982 }
20f0a1fc 4983 return ok;
24eab124 4984}
252b5132 4985
252b5132 4986/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 4987 on error. */
252b5132 4988
252b5132 4989static int
e3bb37b5 4990i386_operand (char *operand_string)
252b5132 4991{
af6bdddf
AM		 4992 const reg_entry *r;
4993 char *end_op;
24eab124 4994 char *op_string = operand_string;
252b5132 4995
24eab124 4996 if (is_space_char (*op_string))
252b5132
RH		 4997 ++op_string;
4998
24eab124 4999 /* We check for an absolute prefix (differentiating,
47926f60 5000 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 5001 if (*op_string == ABSOLUTE_PREFIX)
5002 {
5003 ++op_string;
5004 if (is_space_char (*op_string))
5005 ++op_string;
5006 i.types[this_operand] |= JumpAbsolute;
5007 }
252b5132 5008
47926f60 5009 /* Check if operand is a register. */
4d1bb795 5010 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 5011 {
24eab124
AM		 5012 /* Check for a segment override by searching for ':' after a
5013 segment register. */
5014 op_string = end_op;
5015 if (is_space_char (*op_string))
5016 ++op_string;
5017 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
5018 {
5019 switch (r->reg_num)
5020 {
5021 case 0:
5022 i.seg[i.mem_operands] = &es;
5023 break;
5024 case 1:
5025 i.seg[i.mem_operands] = &cs;
5026 break;
5027 case 2:
5028 i.seg[i.mem_operands] = &ss;
5029 break;
5030 case 3:
5031 i.seg[i.mem_operands] = &ds;
5032 break;
5033 case 4:
5034 i.seg[i.mem_operands] = &fs;
5035 break;
5036 case 5:
5037 i.seg[i.mem_operands] = &gs;
5038 break;
5039 }
252b5132 5040
24eab124 5041 /* Skip the ':' and whitespace. */
252b5132
RH		 5042 ++op_string;
5043 if (is_space_char (*op_string))
24eab124 5044 ++op_string;
252b5132 5045
24eab124
AM		 5046 if (!is_digit_char (*op_string)
5047 && !is_identifier_char (*op_string)
5048 && *op_string != '('
5049 && *op_string != ABSOLUTE_PREFIX)
5050 {
5051 as_bad (_("bad memory operand `%s'"), op_string);
5052 return 0;
5053 }
47926f60 5054 /* Handle case of %es:*foo. */
24eab124
AM		 5055 if (*op_string == ABSOLUTE_PREFIX)
5056 {
5057 ++op_string;
5058 if (is_space_char (*op_string))
5059 ++op_string;
5060 i.types[this_operand] |= JumpAbsolute;
5061 }
5062 goto do_memory_reference;
5063 }
5064 if (*op_string)
5065 {
d0b47220 5066 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 5067 return 0;
5068 }
5069 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 5070 i.op[this_operand].regs = r;
24eab124
AM		 5071 i.reg_operands++;
5072 }
af6bdddf
AM		 5073 else if (*op_string == REGISTER_PREFIX)
5074 {
5075 as_bad (_("bad register name `%s'"), op_string);
5076 return 0;
5077 }
24eab124 5078 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 5079 {
24eab124
AM		 5080 ++op_string;
5081 if (i.types[this_operand] & JumpAbsolute)
5082 {
d0b47220 5083 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 5084 return 0;
5085 }
5086 if (!i386_immediate (op_string))
5087 return 0;
5088 }
5089 else if (is_digit_char (*op_string)
5090 || is_identifier_char (*op_string)
e5cb08ac 5091 || *op_string == '(')
24eab124 5092 {
47926f60 5093 /* This is a memory reference of some sort. */
af6bdddf 5094 char *base_string;
252b5132 5095
47926f60 5096 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 5097 char *displacement_string_start;
5098 char *displacement_string_end;
252b5132 5099
24eab124 5100 do_memory_reference:
24eab124
AM		 5101 if ((i.mem_operands == 1
5102 && (current_templates->start->opcode_modifier & IsString) == 0)
5103 || i.mem_operands == 2)
5104 {
5105 as_bad (_("too many memory references for `%s'"),
5106 current_templates->start->name);
5107 return 0;
5108 }
252b5132 5109
24eab124
AM		 5110 /* Check for base index form. We detect the base index form by
5111 looking for an ')' at the end of the operand, searching
5112 for the '(' matching it, and finding a REGISTER_PREFIX or ','
5113 after the '('. */
af6bdddf 5114 base_string = op_string + strlen (op_string);
c3332e24 5115
af6bdddf
AM		 5116 --base_string;
5117 if (is_space_char (*base_string))
5118 --base_string;
252b5132 5119
47926f60 5120 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 5121 displacement_string_start = op_string;
5122 displacement_string_end = base_string + 1;
252b5132 5123
24eab124
AM		 5124 if (*base_string == ')')
5125 {
af6bdddf 5126 char *temp_string;
24eab124
AM		 5127 unsigned int parens_balanced = 1;
5128 /* We've already checked that the number of left & right ()'s are
47926f60 5129 equal, so this loop will not be infinite. */
24eab124
AM		 5130 do
5131 {
5132 base_string--;
5133 if (*base_string == ')')
5134 parens_balanced++;
5135 if (*base_string == '(')
5136 parens_balanced--;
5137 }
5138 while (parens_balanced);
c3332e24 5139
af6bdddf 5140 temp_string = base_string;
c3332e24 5141
24eab124 5142 /* Skip past '(' and whitespace. */
252b5132
RH		 5143 ++base_string;
5144 if (is_space_char (*base_string))
24eab124 5145 ++base_string;
252b5132 5146
af6bdddf 5147 if (*base_string == ','
4eed87de
AM		 5148 || ((i.base_reg = parse_register (base_string, &end_op))
5149 != NULL))
252b5132 5150 {
af6bdddf 5151 displacement_string_end = temp_string;
252b5132 5152
af6bdddf 5153 i.types[this_operand] |= BaseIndex;
252b5132 5154
af6bdddf 5155 if (i.base_reg)
24eab124 5156 {
24eab124
AM		 5157 base_string = end_op;
5158 if (is_space_char (*base_string))
5159 ++base_string;
af6bdddf
AM		 5160 }
5161
5162 /* There may be an index reg or scale factor here. */
5163 if (*base_string == ',')
5164 {
5165 ++base_string;
5166 if (is_space_char (*base_string))
5167 ++base_string;
5168
4eed87de
AM		 5169 if ((i.index_reg = parse_register (base_string, &end_op))
5170 != NULL)
24eab124 5171 {
af6bdddf 5172 base_string = end_op;
24eab124
AM		 5173 if (is_space_char (*base_string))
5174 ++base_string;
af6bdddf
AM		 5175 if (*base_string == ',')
5176 {
5177 ++base_string;
5178 if (is_space_char (*base_string))
5179 ++base_string;
5180 }
e5cb08ac 5181 else if (*base_string != ')')
af6bdddf 5182 {
4eed87de
AM		 5183 as_bad (_("expecting `,' or `)' "
5184 "after index register in `%s'"),
af6bdddf
AM		 5185 operand_string);
5186 return 0;
5187 }
24eab124 5188 }
af6bdddf 5189 else if (*base_string == REGISTER_PREFIX)
24eab124 5190 {
af6bdddf 5191 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 5192 return 0;
5193 }
252b5132 5194
47926f60 5195 /* Check for scale factor. */
551c1ca1 5196 if (*base_string != ')')
af6bdddf 5197 {
551c1ca1
AM		 5198 char *end_scale = i386_scale (base_string);
5199
5200 if (!end_scale)
af6bdddf 5201 return 0;
24eab124 5202
551c1ca1 5203 base_string = end_scale;
af6bdddf
AM		 5204 if (is_space_char (*base_string))
5205 ++base_string;
5206 if (*base_string != ')')
5207 {
4eed87de
AM		 5208 as_bad (_("expecting `)' "
5209 "after scale factor in `%s'"),
af6bdddf
AM		 5210 operand_string);
5211 return 0;
5212 }
5213 }
5214 else if (!i.index_reg)
24eab124 5215 {
4eed87de
AM		 5216 as_bad (_("expecting index register or scale factor "
5217 "after `,'; got '%c'"),
af6bdddf 5218 *base_string);
24eab124
AM		 5219 return 0;
5220 }
5221 }
af6bdddf 5222 else if (*base_string != ')')
24eab124 5223 {
4eed87de
AM		 5224 as_bad (_("expecting `,' or `)' "
5225 "after base register in `%s'"),
af6bdddf 5226 operand_string);
24eab124
AM		 5227 return 0;
5228 }
c3332e24 5229 }
af6bdddf 5230 else if (*base_string == REGISTER_PREFIX)
c3332e24 5231 {
af6bdddf 5232 as_bad (_("bad register name `%s'"), base_string);
24eab124 5233 return 0;
c3332e24 5234 }
24eab124
AM		 5235 }
5236
5237 /* If there's an expression beginning the operand, parse it,
5238 assuming displacement_string_start and
5239 displacement_string_end are meaningful. */
5240 if (displacement_string_start != displacement_string_end)
5241 {
5242 if (!i386_displacement (displacement_string_start,
5243 displacement_string_end))
5244 return 0;
5245 }
5246
5247 /* Special case for (%dx) while doing input/output op. */
5248 if (i.base_reg
5249 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
5250 && i.index_reg == 0
5251 && i.log2_scale_factor == 0
5252 && i.seg[i.mem_operands] == 0
5253 && (i.types[this_operand] & Disp) == 0)
5254 {
5255 i.types[this_operand] = InOutPortReg;
5256 return 1;
5257 }
5258
eecb386c
AM		 5259 if (i386_index_check (operand_string) == 0)
5260 return 0;
24eab124
AM		 5261 i.mem_operands++;
5262 }
5263 else
ce8a8b2f
AM		 5264 {
5265 /* It's not a memory operand; argh! */
24eab124
AM		 5266 as_bad (_("invalid char %s beginning operand %d `%s'"),
5267 output_invalid (*op_string),
5268 this_operand + 1,
5269 op_string);
5270 return 0;
5271 }
47926f60 5272 return 1; /* Normal return. */
252b5132
RH		 5273}
5274\f
ee7fcc42
AM		 5275/* md_estimate_size_before_relax()
5276
5277 Called just before relax() for rs_machine_dependent frags. The x86
5278 assembler uses these frags to handle variable size jump
5279 instructions.
5280
5281 Any symbol that is now undefined will not become defined.
5282 Return the correct fr_subtype in the frag.
5283 Return the initial "guess for variable size of frag" to caller.
5284 The guess is actually the growth beyond the fixed part. Whatever
5285 we do to grow the fixed or variable part contributes to our
5286 returned value. */
5287
252b5132
RH		 5288int
5289md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 5290 fragS *fragP;
5291 segT segment;
252b5132 5292{
252b5132 5293 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 5294 check for un-relaxable symbols. On an ELF system, we can't relax
5295 an externally visible symbol, because it may be overridden by a
5296 shared library. */
5297 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 5298#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5299 || (IS_ELF
31312f95
AM		 5300 && (S_IS_EXTERNAL (fragP->fr_symbol)
5301 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 5302#endif
5303 )
252b5132 5304 {
b98ef147
AM		 5305 /* Symbol is undefined in this segment, or we need to keep a
5306 reloc so that weak symbols can be overridden. */
5307 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 5308 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 5309 unsigned char *opcode;
5310 int old_fr_fix;
f6af82bd 5311
ee7fcc42
AM		 5312 if (fragP->fr_var != NO_RELOC)
5313 reloc_type = fragP->fr_var;
b98ef147 5314 else if (size == 2)
f6af82bd
AM		 5315 reloc_type = BFD_RELOC_16_PCREL;
5316 else
5317 reloc_type = BFD_RELOC_32_PCREL;
252b5132 5318
ee7fcc42
AM		 5319 old_fr_fix = fragP->fr_fix;
5320 opcode = (unsigned char *) fragP->fr_opcode;
5321
fddf5b5b 5322 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 5323 {
fddf5b5b
AM		 5324 case UNCOND_JUMP:
5325 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 5326 opcode[0] = 0xe9;
252b5132 5327 fragP->fr_fix += size;
062cd5e7
AS		 5328 fix_new (fragP, old_fr_fix, size,
5329 fragP->fr_symbol,
5330 fragP->fr_offset, 1,
5331 reloc_type);
252b5132
RH		 5332 break;
5333
fddf5b5b 5334 case COND_JUMP86:
412167cb
AM		 5335 if (size == 2
5336 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 5337 {
5338 /* Negate the condition, and branch past an
5339 unconditional jump. */
5340 opcode[0] ^= 1;
5341 opcode[1] = 3;
5342 /* Insert an unconditional jump. */
5343 opcode[2] = 0xe9;
5344 /* We added two extra opcode bytes, and have a two byte
5345 offset. */
5346 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 5347 fix_new (fragP, old_fr_fix + 2, 2,
5348 fragP->fr_symbol,
5349 fragP->fr_offset, 1,
5350 reloc_type);
fddf5b5b
AM		 5351 break;
5352 }
5353 /* Fall through. */
5354
5355 case COND_JUMP:
412167cb
AM		 5356 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
5357 {
3e02c1cc
AM		 5358 fixS *fixP;
5359
412167cb 5360 fragP->fr_fix += 1;
3e02c1cc
AM		 5361 fixP = fix_new (fragP, old_fr_fix, 1,
5362 fragP->fr_symbol,
5363 fragP->fr_offset, 1,
5364 BFD_RELOC_8_PCREL);
5365 fixP->fx_signed = 1;
412167cb
AM		 5366 break;
5367 }
93c2a809 5368
24eab124 5369 /* This changes the byte-displacement jump 0x7N
fddf5b5b 5370 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 5371 opcode[1] = opcode[0] + 0x10;
f6af82bd 5372 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 5373 /* We've added an opcode byte. */
5374 fragP->fr_fix += 1 + size;
062cd5e7
AS		 5375 fix_new (fragP, old_fr_fix + 1, size,
5376 fragP->fr_symbol,
5377 fragP->fr_offset, 1,
5378 reloc_type);
252b5132 5379 break;
fddf5b5b
AM		 5380
5381 default:
5382 BAD_CASE (fragP->fr_subtype);
5383 break;
252b5132
RH		 5384 }
5385 frag_wane (fragP);
ee7fcc42 5386 return fragP->fr_fix - old_fr_fix;
252b5132 5387 }
93c2a809 5388
93c2a809
AM		 5389 /* Guess size depending on current relax state. Initially the relax
5390 state will correspond to a short jump and we return 1, because
5391 the variable part of the frag (the branch offset) is one byte
5392 long. However, we can relax a section more than once and in that
5393 case we must either set fr_subtype back to the unrelaxed state,
5394 or return the value for the appropriate branch. */
5395 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 5396}
5397
47926f60
KH		 5398/* Called after relax() is finished.
5399
5400 In: Address of frag.
5401 fr_type == rs_machine_dependent.
5402 fr_subtype is what the address relaxed to.
5403
5404 Out: Any fixSs and constants are set up.
5405 Caller will turn frag into a ".space 0". */
5406
252b5132
RH		 5407void
5408md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 5409 bfd *abfd ATTRIBUTE_UNUSED;
5410 segT sec ATTRIBUTE_UNUSED;
29b0f896 5411 fragS *fragP;
252b5132 5412{
29b0f896 5413 unsigned char *opcode;
252b5132 5414 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 5415 offsetT target_address;
5416 offsetT opcode_address;
252b5132 5417 unsigned int extension = 0;
847f7ad4 5418 offsetT displacement_from_opcode_start;
252b5132
RH		 5419
5420 opcode = (unsigned char *) fragP->fr_opcode;
5421
47926f60 5422 /* Address we want to reach in file space. */
252b5132 5423 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 5424
47926f60 5425 /* Address opcode resides at in file space. */
252b5132
RH		 5426 opcode_address = fragP->fr_address + fragP->fr_fix;
5427
47926f60 5428 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 5429 displacement_from_opcode_start = target_address - opcode_address;
5430
fddf5b5b 5431 if ((fragP->fr_subtype & BIG) == 0)
252b5132 5432 {
47926f60
KH		 5433 /* Don't have to change opcode. */
5434 extension = 1; /* 1 opcode + 1 displacement */
252b5132 5435 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 5436 }
5437 else
5438 {
5439 if (no_cond_jump_promotion
5440 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 5441 as_warn_where (fragP->fr_file, fragP->fr_line,
5442 _("long jump required"));
252b5132 5443
fddf5b5b
AM		 5444 switch (fragP->fr_subtype)
5445 {
5446 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
5447 extension = 4; /* 1 opcode + 4 displacement */
5448 opcode[0] = 0xe9;
5449 where_to_put_displacement = &opcode[1];
5450 break;
252b5132 5451
fddf5b5b
AM		 5452 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
5453 extension = 2; /* 1 opcode + 2 displacement */
5454 opcode[0] = 0xe9;
5455 where_to_put_displacement = &opcode[1];
5456 break;
252b5132 5457
fddf5b5b
AM		 5458 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
5459 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
5460 extension = 5; /* 2 opcode + 4 displacement */
5461 opcode[1] = opcode[0] + 0x10;
5462 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5463 where_to_put_displacement = &opcode[2];
5464 break;
252b5132 5465
fddf5b5b
AM		 5466 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
5467 extension = 3; /* 2 opcode + 2 displacement */
5468 opcode[1] = opcode[0] + 0x10;
5469 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5470 where_to_put_displacement = &opcode[2];
5471 break;
252b5132 5472
fddf5b5b
AM		 5473 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
5474 extension = 4;
5475 opcode[0] ^= 1;
5476 opcode[1] = 3;
5477 opcode[2] = 0xe9;
5478 where_to_put_displacement = &opcode[3];
5479 break;
5480
5481 default:
5482 BAD_CASE (fragP->fr_subtype);
5483 break;
5484 }
252b5132 5485 }
fddf5b5b 5486
7b81dfbb
AJ		 5487 /* If size if less then four we are sure that the operand fits,
5488 but if it's 4, then it could be that the displacement is larger
5489 then -/+ 2GB. */
5490 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
5491 && object_64bit
5492 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 5493 + ((addressT) 1 << 31))
5494 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 5495 {
5496 as_bad_where (fragP->fr_file, fragP->fr_line,
5497 _("jump target out of range"));
5498 /* Make us emit 0. */
5499 displacement_from_opcode_start = extension;
5500 }
47926f60 5501 /* Now put displacement after opcode. */
252b5132
RH		 5502 md_number_to_chars ((char *) where_to_put_displacement,
5503 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 5504 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 5505 fragP->fr_fix += extension;
5506}
5507\f
47926f60
KH		 5508/* Size of byte displacement jmp. */
5509int md_short_jump_size = 2;
5510
5511/* Size of dword displacement jmp. */
5512int md_long_jump_size = 5;
252b5132 5513
252b5132
RH		 5514void
5515md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
5516 char *ptr;
5517 addressT from_addr, to_addr;
ab9da554
ILT		 5518 fragS *frag ATTRIBUTE_UNUSED;
5519 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5520{
847f7ad4 5521 offsetT offset;
252b5132
RH		 5522
5523 offset = to_addr - (from_addr + 2);
47926f60
KH		 5524 /* Opcode for byte-disp jump. */
5525 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 5526 md_number_to_chars (ptr + 1, (valueT) offset, 1);
5527}
5528
5529void
5530md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
5531 char *ptr;
5532 addressT from_addr, to_addr;
a38cf1db
AM		 5533 fragS *frag ATTRIBUTE_UNUSED;
5534 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5535{
847f7ad4 5536 offsetT offset;
252b5132 5537
a38cf1db
AM		 5538 offset = to_addr - (from_addr + 5);
5539 md_number_to_chars (ptr, (valueT) 0xe9, 1);
5540 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 5541}
5542\f
5543/* Apply a fixup (fixS) to segment data, once it has been determined
5544 by our caller that we have all the info we need to fix it up.
5545
5546 On the 386, immediates, displacements, and data pointers are all in
5547 the same (little-endian) format, so we don't need to care about which
5548 we are handling. */
5549
94f592af 5550void
55cf6793 5551md_apply_fix (fixP, valP, seg)
47926f60
KH		 5552 /* The fix we're to put in. */
5553 fixS *fixP;
47926f60 5554 /* Pointer to the value of the bits. */
c6682705 5555 valueT *valP;
47926f60
KH		 5556 /* Segment fix is from. */
5557 segT seg ATTRIBUTE_UNUSED;
252b5132 5558{
94f592af 5559 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 5560 valueT value = *valP;
252b5132 5561
f86103b7 5562#if !defined (TE_Mach)
93382f6d
AM		 5563 if (fixP->fx_pcrel)
5564 {
5565 switch (fixP->fx_r_type)
5566 {
5865bb77
ILT		 5567 default:
5568 break;
5569
d6ab8113
JB		 5570 case BFD_RELOC_64:
5571 fixP->fx_r_type = BFD_RELOC_64_PCREL;
5572 break;
93382f6d 5573 case BFD_RELOC_32:
ae8887b5 5574 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 5575 fixP->fx_r_type = BFD_RELOC_32_PCREL;
5576 break;
5577 case BFD_RELOC_16:
5578 fixP->fx_r_type = BFD_RELOC_16_PCREL;
5579 break;
5580 case BFD_RELOC_8:
5581 fixP->fx_r_type = BFD_RELOC_8_PCREL;
5582 break;
5583 }
5584 }
252b5132 5585
a161fe53 5586 if (fixP->fx_addsy != NULL
31312f95 5587 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 5588 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 5589 || fixP->fx_r_type == BFD_RELOC_16_PCREL
5590 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
5591 && !use_rela_relocations)
252b5132 5592 {
31312f95
AM		 5593 /* This is a hack. There should be a better way to handle this.
5594 This covers for the fact that bfd_install_relocation will
5595 subtract the current location (for partial_inplace, PC relative
5596 relocations); see more below. */
252b5132 5597#ifndef OBJ_AOUT
718ddfc0 5598 if (IS_ELF
252b5132
RH		 5599#ifdef TE_PE
5600 || OUTPUT_FLAVOR == bfd_target_coff_flavour
5601#endif
5602 )
5603 value += fixP->fx_where + fixP->fx_frag->fr_address;
5604#endif
5605#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5606 if (IS_ELF)
252b5132 5607 {
6539b54b 5608 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 5609
6539b54b 5610 if ((sym_seg == seg
2f66722d 5611 || (symbol_section_p (fixP->fx_addsy)
6539b54b 5612 && sym_seg != absolute_section))
ae6063d4 5613 && !generic_force_reloc (fixP))
2f66722d
AM		 5614 {
5615 /* Yes, we add the values in twice. This is because
6539b54b
AM		 5616 bfd_install_relocation subtracts them out again. I think
5617 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 5618 it. FIXME. */
5619 value += fixP->fx_where + fixP->fx_frag->fr_address;
5620 }
252b5132
RH		 5621 }
5622#endif
5623#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 5624 /* For some reason, the PE format does not store a
5625 section address offset for a PC relative symbol. */
5626 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 5627 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 5628 value += md_pcrel_from (fixP);
5629#endif
5630 }
5631
5632 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 5633 and we must not disappoint it. */
252b5132 5634#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5635 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 5636 switch (fixP->fx_r_type)
5637 {
5638 case BFD_RELOC_386_PLT32:
3e73aa7c 5639 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 5640 /* Make the jump instruction point to the address of the operand. At
5641 runtime we merely add the offset to the actual PLT entry. */
5642 value = -4;
5643 break;
31312f95 5644
13ae64f3
JJ		 5645 case BFD_RELOC_386_TLS_GD:
5646 case BFD_RELOC_386_TLS_LDM:
13ae64f3 5647 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5648 case BFD_RELOC_386_TLS_IE:
5649 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 5650 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 5651 case BFD_RELOC_X86_64_TLSGD:
5652 case BFD_RELOC_X86_64_TLSLD:
5653 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 5654 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 5655 value = 0; /* Fully resolved at runtime. No addend. */
5656 /* Fallthrough */
5657 case BFD_RELOC_386_TLS_LE:
5658 case BFD_RELOC_386_TLS_LDO_32:
5659 case BFD_RELOC_386_TLS_LE_32:
5660 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5661 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 5662 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 5663 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 5664 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5665 break;
5666
67a4f2b7
AO		 5667 case BFD_RELOC_386_TLS_DESC_CALL:
5668 case BFD_RELOC_X86_64_TLSDESC_CALL:
5669 value = 0; /* Fully resolved at runtime. No addend. */
5670 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5671 fixP->fx_done = 0;
5672 return;
5673
00f7efb6
JJ		 5674 case BFD_RELOC_386_GOT32:
5675 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 5676 value = 0; /* Fully resolved at runtime. No addend. */
5677 break;
47926f60
KH		 5678
5679 case BFD_RELOC_VTABLE_INHERIT:
5680 case BFD_RELOC_VTABLE_ENTRY:
5681 fixP->fx_done = 0;
94f592af 5682 return;
47926f60
KH		 5683
5684 default:
5685 break;
5686 }
5687#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 5688 *valP = value;
f86103b7 5689#endif /* !defined (TE_Mach) */
3e73aa7c 5690
3e73aa7c 5691 /* Are we finished with this relocation now? */
c6682705 5692 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 5693 fixP->fx_done = 1;
5694 else if (use_rela_relocations)
5695 {
5696 fixP->fx_no_overflow = 1;
062cd5e7
AS		 5697 /* Remember value for tc_gen_reloc. */
5698 fixP->fx_addnumber = value;
3e73aa7c
JH		 5699 value = 0;
5700 }
f86103b7 5701
94f592af 5702 md_number_to_chars (p, value, fixP->fx_size);
252b5132 5703}
252b5132 5704\f
252b5132
RH		 5705#define MAX_LITTLENUMS 6
5706
47926f60
KH		 5707/* Turn the string pointed to by litP into a floating point constant
5708 of type TYPE, and emit the appropriate bytes. The number of
5709 LITTLENUMS emitted is stored in *SIZEP. An error message is
5710 returned, or NULL on OK. */
5711
252b5132
RH		 5712char *
5713md_atof (type, litP, sizeP)
2ab9b79e 5714 int type;
252b5132
RH		 5715 char *litP;
5716 int *sizeP;
5717{
5718 int prec;
5719 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5720 LITTLENUM_TYPE *wordP;
5721 char *t;
5722
5723 switch (type)
5724 {
5725 case 'f':
5726 case 'F':
5727 prec = 2;
5728 break;
5729
5730 case 'd':
5731 case 'D':
5732 prec = 4;
5733 break;
5734
5735 case 'x':
5736 case 'X':
5737 prec = 5;
5738 break;
5739
5740 default:
5741 *sizeP = 0;
5742 return _("Bad call to md_atof ()");
5743 }
5744 t = atof_ieee (input_line_pointer, type, words);
5745 if (t)
5746 input_line_pointer = t;
5747
5748 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5749 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5750 the bigendian 386. */
5751 for (wordP = words + prec - 1; prec--;)
5752 {
5753 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5754 litP += sizeof (LITTLENUM_TYPE);
5755 }
5756 return 0;
5757}
5758\f
2d545b82 5759static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 5760
252b5132 5761static char *
e3bb37b5 5762output_invalid (int c)
252b5132 5763{
3882b010 5764 if (ISPRINT (c))
f9f21a03
L		 5765 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5766 "'%c'", c);
252b5132 5767 else
f9f21a03 5768 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 5769 "(0x%x)", (unsigned char) c);
252b5132
RH		 5770 return output_invalid_buf;
5771}
5772
af6bdddf 5773/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 5774
5775static const reg_entry *
4d1bb795 5776parse_real_register (char *reg_string, char **end_op)
252b5132 5777{
af6bdddf
AM		 5778 char *s = reg_string;
5779 char *p;
252b5132
RH		 5780 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5781 const reg_entry *r;
5782
5783 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5784 if (*s == REGISTER_PREFIX)
5785 ++s;
5786
5787 if (is_space_char (*s))
5788 ++s;
5789
5790 p = reg_name_given;
af6bdddf 5791 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 5792 {
5793 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 5794 return (const reg_entry *) NULL;
5795 s++;
252b5132
RH		 5796 }
5797
6588847e
DN		 5798 /* For naked regs, make sure that we are not dealing with an identifier.
5799 This prevents confusing an identifier like `eax_var' with register
5800 `eax'. */
5801 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5802 return (const reg_entry *) NULL;
5803
af6bdddf 5804 *end_op = s;
252b5132
RH		 5805
5806 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5807
5f47d35b 5808 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 5809 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 5810 {
5f47d35b
AM		 5811 if (is_space_char (*s))
5812 ++s;
5813 if (*s == '(')
5814 {
af6bdddf 5815 ++s;
5f47d35b
AM		 5816 if (is_space_char (*s))
5817 ++s;
5818 if (*s >= '0' && *s <= '7')
5819 {
db557034 5820 int fpr = *s - '0';
af6bdddf 5821 ++s;
5f47d35b
AM		 5822 if (is_space_char (*s))
5823 ++s;
5824 if (*s == ')')
5825 {
5826 *end_op = s + 1;
db557034
AM		 5827 r = hash_find (reg_hash, "st(0)");
5828 know (r);
5829 return r + fpr;
5f47d35b 5830 }
5f47d35b 5831 }
47926f60 5832 /* We have "%st(" then garbage. */
5f47d35b
AM		 5833 return (const reg_entry *) NULL;
5834 }
5835 }
5836
1ae00879 5837 if (r != NULL
20f0a1fc 5838 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
c4a530c5 5839 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
1ae00879 5840 && flag_code != CODE_64BIT)
20f0a1fc 5841 return (const reg_entry *) NULL;
1ae00879 5842
252b5132
RH		 5843 return r;
5844}
4d1bb795
JB		 5845
5846/* REG_STRING starts *before* REGISTER_PREFIX. */
5847
5848static const reg_entry *
5849parse_register (char *reg_string, char **end_op)
5850{
5851 const reg_entry *r;
5852
5853 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
5854 r = parse_real_register (reg_string, end_op);
5855 else
5856 r = NULL;
5857 if (!r)
5858 {
5859 char *save = input_line_pointer;
5860 char c;
5861 symbolS *symbolP;
5862
5863 input_line_pointer = reg_string;
5864 c = get_symbol_end ();
5865 symbolP = symbol_find (reg_string);
5866 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
5867 {
5868 const expressionS *e = symbol_get_value_expression (symbolP);
5869
5870 know (e->X_op == O_register);
4eed87de 5871 know (e->X_add_number >= 0
c3fe08fa 5872 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 5873 r = i386_regtab + e->X_add_number;
5874 *end_op = input_line_pointer;
5875 }
5876 *input_line_pointer = c;
5877 input_line_pointer = save;
5878 }
5879 return r;
5880}
5881
5882int
5883i386_parse_name (char *name, expressionS *e, char *nextcharP)
5884{
5885 const reg_entry *r;
5886 char *end = input_line_pointer;
5887
5888 *end = *nextcharP;
5889 r = parse_register (name, &input_line_pointer);
5890 if (r && end <= input_line_pointer)
5891 {
5892 *nextcharP = *input_line_pointer;
5893 *input_line_pointer = 0;
5894 e->X_op = O_register;
5895 e->X_add_number = r - i386_regtab;
5896 return 1;
5897 }
5898 input_line_pointer = end;
5899 *end = 0;
5900 return 0;
5901}
5902
5903void
5904md_operand (expressionS *e)
5905{
5906 if (*input_line_pointer == REGISTER_PREFIX)
5907 {
5908 char *end;
5909 const reg_entry *r = parse_real_register (input_line_pointer, &end);
5910
5911 if (r)
5912 {
5913 e->X_op = O_register;
5914 e->X_add_number = r - i386_regtab;
5915 input_line_pointer = end;
5916 }
5917 }
5918}
5919
252b5132 5920\f
4cc782b5 5921#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 5922const char *md_shortopts = "kVQ:sqn";
252b5132 5923#else
12b55ccc 5924const char *md_shortopts = "qn";
252b5132 5925#endif
6e0b89ee 5926
3e73aa7c 5927#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 5928#define OPTION_64 (OPTION_MD_BASE + 1)
5929#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 5930#define OPTION_MARCH (OPTION_MD_BASE + 3)
5931#define OPTION_MTUNE (OPTION_MD_BASE + 4)
b3b91714 5932
99ad8390
NC		 5933struct option md_longopts[] =
5934{
3e73aa7c 5935 {"32", no_argument, NULL, OPTION_32},
99ad8390 5936#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 5937 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 5938#endif
b3b91714 5939 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 5940 {"march", required_argument, NULL, OPTION_MARCH},
5941 {"mtune", required_argument, NULL, OPTION_MTUNE},
252b5132
RH		 5942 {NULL, no_argument, NULL, 0}
5943};
5944size_t md_longopts_size = sizeof (md_longopts);
5945
5946int
9103f4f4 5947md_parse_option (int c, char *arg)
252b5132 5948{
9103f4f4
L		 5949 unsigned int i;
5950
252b5132
RH		 5951 switch (c)
5952 {
12b55ccc
L		 5953 case 'n':
5954 optimize_align_code = 0;
5955 break;
5956
a38cf1db
AM		 5957 case 'q':
5958 quiet_warnings = 1;
252b5132
RH		 5959 break;
5960
5961#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 5962 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5963 should be emitted or not. FIXME: Not implemented. */
5964 case 'Q':
252b5132
RH		 5965 break;
5966
5967 /* -V: SVR4 argument to print version ID. */
5968 case 'V':
5969 print_version_id ();
5970 break;
5971
a38cf1db
AM		 5972 /* -k: Ignore for FreeBSD compatibility. */
5973 case 'k':
252b5132 5974 break;
4cc782b5
ILT		 5975
5976 case 's':
5977 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 5978 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 5979 break;
99ad8390
NC		 5980#endif
5981#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 5982 case OPTION_64:
5983 {
5984 const char **list, **l;
5985
3e73aa7c
JH		 5986 list = bfd_target_list ();
5987 for (l = list; *l != NULL; l++)
8620418b 5988 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 5989 || strcmp (*l, "coff-x86-64") == 0
5990 || strcmp (*l, "pe-x86-64") == 0
5991 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 5992 {
5993 default_arch = "x86_64";
5994 break;
5995 }
3e73aa7c 5996 if (*l == NULL)
6e0b89ee 5997 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 5998 free (list);
5999 }
6000 break;
6001#endif
252b5132 6002
6e0b89ee
AM		 6003 case OPTION_32:
6004 default_arch = "i386";
6005 break;
6006
b3b91714
AM		 6007 case OPTION_DIVIDE:
6008#ifdef SVR4_COMMENT_CHARS
6009 {
6010 char *n, *t;
6011 const char *s;
6012
6013 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
6014 t = n;
6015 for (s = i386_comment_chars; *s != '\0'; s++)
6016 if (*s != '/')
6017 *t++ = *s;
6018 *t = '\0';
6019 i386_comment_chars = n;
6020 }
6021#endif
6022 break;
6023
9103f4f4
L		 6024 case OPTION_MARCH:
6025 if (*arg == '.')
6026 as_fatal (_("Invalid -march= option: `%s'"), arg);
6027 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
6028 {
6029 if (strcmp (arg, cpu_arch [i].name) == 0)
6030 {
ccc9c027 6031 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 6032 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 6033 if (!cpu_arch_tune_set)
6034 {
6035 cpu_arch_tune = cpu_arch_isa;
6036 cpu_arch_tune_flags = cpu_arch_isa_flags;
6037 }
9103f4f4
L		 6038 break;
6039 }
6040 }
6041 if (i >= ARRAY_SIZE (cpu_arch))
6042 as_fatal (_("Invalid -march= option: `%s'"), arg);
6043 break;
6044
6045 case OPTION_MTUNE:
6046 if (*arg == '.')
6047 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
6048 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
6049 {
6050 if (strcmp (arg, cpu_arch [i].name) == 0)
6051 {
ccc9c027 6052 cpu_arch_tune_set = 1;
9103f4f4
L		 6053 cpu_arch_tune = cpu_arch [i].type;
6054 cpu_arch_tune_flags = cpu_arch[i].flags;
6055 break;
6056 }
6057 }
6058 if (i >= ARRAY_SIZE (cpu_arch))
6059 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
6060 break;
6061
252b5132
RH		 6062 default:
6063 return 0;
6064 }
6065 return 1;
6066}
6067
6068void
6069md_show_usage (stream)
6070 FILE *stream;
6071{
4cc782b5
ILT		 6072#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6073 fprintf (stream, _("\
a38cf1db
AM		 6074 -Q ignored\n\
6075 -V print assembler version number\n\
b3b91714
AM		 6076 -k ignored\n"));
6077#endif
6078 fprintf (stream, _("\
12b55ccc 6079 -n Do not optimize code alignment\n\
b3b91714
AM		 6080 -q quieten some warnings\n"));
6081#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6082 fprintf (stream, _("\
a38cf1db 6083 -s ignored\n"));
b3b91714 6084#endif
751d281c
L		 6085#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
6086 fprintf (stream, _("\
6087 --32/--64 generate 32bit/64bit code\n"));
6088#endif
b3b91714
AM		 6089#ifdef SVR4_COMMENT_CHARS
6090 fprintf (stream, _("\
6091 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 6092#else
6093 fprintf (stream, _("\
b3b91714 6094 --divide ignored\n"));
4cc782b5 6095#endif
9103f4f4
L		 6096 fprintf (stream, _("\
6097 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
6098 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
4eed87de 6099 core, core2, k6, athlon, k8, generic32, generic64\n"));
9103f4f4 6100
252b5132
RH		 6101}
6102
99ad8390
NC		 6103#if defined(TE_PEP)
6104const char *
6105x86_64_target_format (void)
6106{
6107 if (strcmp (default_arch, "x86_64") == 0)
6108 {
6109 set_code_flag (CODE_64BIT);
6110 return COFF_TARGET_FORMAT;
6111 }
6112 else if (strcmp (default_arch, "i386") == 0)
6113 {
6114 set_code_flag (CODE_32BIT);
6115 return "coff-i386";
6116 }
6117
6118 as_fatal (_("Unknown architecture"));
6119 return NULL;
6120}
6121#endif
6122
3e73aa7c
JH		 6123#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
6124 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 6125
6126/* Pick the target format to use. */
6127
47926f60 6128const char *
e3bb37b5 6129i386_target_format (void)
252b5132 6130{
3e73aa7c 6131 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 6132 {
6133 set_code_flag (CODE_64BIT);
6134 if (cpu_arch_isa_flags == 0)
d32cad65 6135 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386|Cpu486
9103f4f4
L		 6136 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6137 |CpuSSE|CpuSSE2;
ccc9c027 6138 if (cpu_arch_tune_flags == 0)
d32cad65 6139 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386|Cpu486
ccc9c027
L		 6140 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
6141 |CpuSSE|CpuSSE2;
9103f4f4 6142 }
3e73aa7c 6143 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 6144 {
6145 set_code_flag (CODE_32BIT);
6146 if (cpu_arch_isa_flags == 0)
d32cad65 6147 cpu_arch_isa_flags = Cpu186|Cpu286|Cpu386;
ccc9c027 6148 if (cpu_arch_tune_flags == 0)
d32cad65 6149 cpu_arch_tune_flags = Cpu186|Cpu286|Cpu386;
9103f4f4 6150 }
3e73aa7c
JH		 6151 else
6152 as_fatal (_("Unknown architecture"));
252b5132
RH		 6153 switch (OUTPUT_FLAVOR)
6154 {
4c63da97
AM		 6155#ifdef OBJ_MAYBE_AOUT
6156 case bfd_target_aout_flavour:
47926f60 6157 return AOUT_TARGET_FORMAT;
4c63da97
AM		 6158#endif
6159#ifdef OBJ_MAYBE_COFF
252b5132
RH		 6160 case bfd_target_coff_flavour:
6161 return "coff-i386";
4c63da97 6162#endif
3e73aa7c 6163#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 6164 case bfd_target_elf_flavour:
3e73aa7c 6165 {
e5cb08ac 6166 if (flag_code == CODE_64BIT)
4fa24527
JB		 6167 {
6168 object_64bit = 1;
6169 use_rela_relocations = 1;
6170 }
9d7cbccd 6171 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 6172 }
4c63da97 6173#endif
252b5132
RH		 6174 default:
6175 abort ();
6176 return NULL;
6177 }
6178}
6179
47926f60 6180#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 6181
6182#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 6183void
6184i386_elf_emit_arch_note (void)
a847613f 6185{
718ddfc0 6186 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 6187 {
6188 char *p;
6189 asection *seg = now_seg;
6190 subsegT subseg = now_subseg;
6191 Elf_Internal_Note i_note;
6192 Elf_External_Note e_note;
6193 asection *note_secp;
6194 int len;
6195
6196 /* Create the .note section. */
6197 note_secp = subseg_new (".note", 0);
6198 bfd_set_section_flags (stdoutput,
6199 note_secp,
6200 SEC_HAS_CONTENTS | SEC_READONLY);
6201
6202 /* Process the arch string. */
6203 len = strlen (cpu_arch_name);
6204
6205 i_note.namesz = len + 1;
6206 i_note.descsz = 0;
6207 i_note.type = NT_ARCH;
6208 p = frag_more (sizeof (e_note.namesz));
6209 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
6210 p = frag_more (sizeof (e_note.descsz));
6211 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
6212 p = frag_more (sizeof (e_note.type));
6213 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
6214 p = frag_more (len + 1);
6215 strcpy (p, cpu_arch_name);
6216
6217 frag_align (2, 0, 0);
6218
6219 subseg_set (seg, subseg);
6220 }
6221}
6222#endif
252b5132 6223\f
252b5132
RH		 6224symbolS *
6225md_undefined_symbol (name)
6226 char *name;
6227{
18dc2407
ILT		 6228 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
6229 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
6230 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
6231 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 6232 {
6233 if (!GOT_symbol)
6234 {
6235 if (symbol_find (name))
6236 as_bad (_("GOT already in symbol table"));
6237 GOT_symbol = symbol_new (name, undefined_section,
6238 (valueT) 0, &zero_address_frag);
6239 };
6240 return GOT_symbol;
6241 }
252b5132
RH		 6242 return 0;
6243}
6244
6245/* Round up a section size to the appropriate boundary. */
47926f60 6246
252b5132
RH		 6247valueT
6248md_section_align (segment, size)
ab9da554 6249 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 6250 valueT size;
6251{
4c63da97
AM		 6252#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6253 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
6254 {
6255 /* For a.out, force the section size to be aligned. If we don't do
6256 this, BFD will align it for us, but it will not write out the
6257 final bytes of the section. This may be a bug in BFD, but it is
6258 easier to fix it here since that is how the other a.out targets
6259 work. */
6260 int align;
6261
6262 align = bfd_get_section_alignment (stdoutput, segment);
6263 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6264 }
252b5132
RH		 6265#endif
6266
6267 return size;
6268}
6269
6270/* On the i386, PC-relative offsets are relative to the start of the
6271 next instruction. That is, the address of the offset, plus its
6272 size, since the offset is always the last part of the insn. */
6273
6274long
e3bb37b5 6275md_pcrel_from (fixS *fixP)
252b5132
RH		 6276{
6277 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
6278}
6279
6280#ifndef I386COFF
6281
6282static void
e3bb37b5 6283s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 6284{
29b0f896 6285 int temp;
252b5132 6286
8a75718c
JB		 6287#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6288 if (IS_ELF)
6289 obj_elf_section_change_hook ();
6290#endif
252b5132
RH		 6291 temp = get_absolute_expression ();
6292 subseg_set (bss_section, (subsegT) temp);
6293 demand_empty_rest_of_line ();
6294}
6295
6296#endif
6297
252b5132 6298void
e3bb37b5 6299i386_validate_fix (fixS *fixp)
252b5132
RH		 6300{
6301 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
6302 {
23df1078
JH		 6303 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
6304 {
4fa24527 6305 if (!object_64bit)
23df1078
JH		 6306 abort ();
6307 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
6308 }
6309 else
6310 {
4fa24527 6311 if (!object_64bit)
d6ab8113
JB		 6312 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
6313 else
6314 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 6315 }
252b5132
RH		 6316 fixp->fx_subsy = 0;
6317 }
6318}
6319
252b5132
RH		 6320arelent *
6321tc_gen_reloc (section, fixp)
ab9da554 6322 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 6323 fixS *fixp;
6324{
6325 arelent *rel;
6326 bfd_reloc_code_real_type code;
6327
6328 switch (fixp->fx_r_type)
6329 {
3e73aa7c
JH		 6330 case BFD_RELOC_X86_64_PLT32:
6331 case BFD_RELOC_X86_64_GOT32:
6332 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 6333 case BFD_RELOC_386_PLT32:
6334 case BFD_RELOC_386_GOT32:
6335 case BFD_RELOC_386_GOTOFF:
6336 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 6337 case BFD_RELOC_386_TLS_GD:
6338 case BFD_RELOC_386_TLS_LDM:
6339 case BFD_RELOC_386_TLS_LDO_32:
6340 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 6341 case BFD_RELOC_386_TLS_IE:
6342 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 6343 case BFD_RELOC_386_TLS_LE_32:
6344 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 6345 case BFD_RELOC_386_TLS_GOTDESC:
6346 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 6347 case BFD_RELOC_X86_64_TLSGD:
6348 case BFD_RELOC_X86_64_TLSLD:
6349 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 6350 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 6351 case BFD_RELOC_X86_64_GOTTPOFF:
6352 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 6353 case BFD_RELOC_X86_64_TPOFF64:
6354 case BFD_RELOC_X86_64_GOTOFF64:
6355 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 6356 case BFD_RELOC_X86_64_GOT64:
6357 case BFD_RELOC_X86_64_GOTPCREL64:
6358 case BFD_RELOC_X86_64_GOTPC64:
6359 case BFD_RELOC_X86_64_GOTPLT64:
6360 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 6361 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6362 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 6363 case BFD_RELOC_RVA:
6364 case BFD_RELOC_VTABLE_ENTRY:
6365 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 6366#ifdef TE_PE
6367 case BFD_RELOC_32_SECREL:
6368#endif
252b5132
RH		 6369 code = fixp->fx_r_type;
6370 break;
dbbaec26
L		 6371 case BFD_RELOC_X86_64_32S:
6372 if (!fixp->fx_pcrel)
6373 {
6374 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6375 code = fixp->fx_r_type;
6376 break;
6377 }
252b5132 6378 default:
93382f6d 6379 if (fixp->fx_pcrel)
252b5132 6380 {
93382f6d
AM		 6381 switch (fixp->fx_size)
6382 {
6383 default:
b091f402
AM		 6384 as_bad_where (fixp->fx_file, fixp->fx_line,
6385 _("can not do %d byte pc-relative relocation"),
6386 fixp->fx_size);
93382f6d
AM		 6387 code = BFD_RELOC_32_PCREL;
6388 break;
6389 case 1: code = BFD_RELOC_8_PCREL; break;
6390 case 2: code = BFD_RELOC_16_PCREL; break;
6391 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 6392#ifdef BFD64
6393 case 8: code = BFD_RELOC_64_PCREL; break;
6394#endif
93382f6d
AM		 6395 }
6396 }
6397 else
6398 {
6399 switch (fixp->fx_size)
6400 {
6401 default:
b091f402
AM		 6402 as_bad_where (fixp->fx_file, fixp->fx_line,
6403 _("can not do %d byte relocation"),
6404 fixp->fx_size);
93382f6d
AM		 6405 code = BFD_RELOC_32;
6406 break;
6407 case 1: code = BFD_RELOC_8; break;
6408 case 2: code = BFD_RELOC_16; break;
6409 case 4: code = BFD_RELOC_32; break;
937149dd 6410#ifdef BFD64
3e73aa7c 6411 case 8: code = BFD_RELOC_64; break;
937149dd 6412#endif
93382f6d 6413 }
252b5132
RH		 6414 }
6415 break;
6416 }
252b5132 6417
d182319b
JB		 6418 if ((code == BFD_RELOC_32
6419 || code == BFD_RELOC_32_PCREL
6420 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 6421 && GOT_symbol
6422 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 6423 {
4fa24527 6424 if (!object_64bit)
d6ab8113
JB		 6425 code = BFD_RELOC_386_GOTPC;
6426 else
6427 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 6428 }
7b81dfbb
AJ		 6429 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
6430 && GOT_symbol
6431 && fixp->fx_addsy == GOT_symbol)
6432 {
6433 code = BFD_RELOC_X86_64_GOTPC64;
6434 }
252b5132
RH		 6435
6436 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 6437 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
6438 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 6439
6440 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 6441
3e73aa7c
JH		 6442 if (!use_rela_relocations)
6443 {
6444 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
6445 vtable entry to be used in the relocation's section offset. */
6446 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6447 rel->address = fixp->fx_offset;
252b5132 6448
c6682705 6449 rel->addend = 0;
3e73aa7c
JH		 6450 }
6451 /* Use the rela in 64bit mode. */
252b5132 6452 else
3e73aa7c 6453 {
062cd5e7
AS		 6454 if (!fixp->fx_pcrel)
6455 rel->addend = fixp->fx_offset;
6456 else
6457 switch (code)
6458 {
6459 case BFD_RELOC_X86_64_PLT32:
6460 case BFD_RELOC_X86_64_GOT32:
6461 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 6462 case BFD_RELOC_X86_64_TLSGD:
6463 case BFD_RELOC_X86_64_TLSLD:
6464 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 6465 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6466 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 6467 rel->addend = fixp->fx_offset - fixp->fx_size;
6468 break;
6469 default:
6470 rel->addend = (section->vma
6471 - fixp->fx_size
6472 + fixp->fx_addnumber
6473 + md_pcrel_from (fixp));
6474 break;
6475 }
3e73aa7c
JH		 6476 }
6477
252b5132
RH		 6478 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
6479 if (rel->howto == NULL)
6480 {
6481 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 6482 _("cannot represent relocation type %s"),
252b5132
RH		 6483 bfd_get_reloc_code_name (code));
6484 /* Set howto to a garbage value so that we can keep going. */
6485 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
6486 assert (rel->howto != NULL);
6487 }
6488
6489 return rel;
6490}
6491
64a0c779
DN		 6492\f
6493/* Parse operands using Intel syntax. This implements a recursive descent
6494 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6495 Programmer's Guide.
6496
6497 FIXME: We do not recognize the full operand grammar defined in the MASM
6498 documentation. In particular, all the structure/union and
6499 high-level macro operands are missing.
6500
6501 Uppercase words are terminals, lower case words are non-terminals.
6502 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6503 bars '|' denote choices. Most grammar productions are implemented in
6504 functions called 'intel_<production>'.
6505
6506 Initial production is 'expr'.
6507
9306ca4a 6508 addOp + | -
64a0c779
DN		 6509
6510 alpha [a-zA-Z]
6511
9306ca4a
JB		 6512 binOp & | AND | \| | OR | ^ | XOR
6513
64a0c779
DN		 6514 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6515
6516 constant digits [[ radixOverride ]]
6517
9306ca4a 6518 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 6519
6520 digits decdigit
b77a7acd
AJ		 6521 | digits decdigit
6522 | digits hexdigit
64a0c779
DN		 6523
6524 decdigit [0-9]
6525
9306ca4a
JB		 6526 e04 e04 addOp e05
6527 | e05
6528
6529 e05 e05 binOp e06
b77a7acd 6530 | e06
64a0c779
DN		 6531
6532 e06 e06 mulOp e09
b77a7acd 6533 | e09
64a0c779
DN		 6534
6535 e09 OFFSET e10
a724f0f4
JB		 6536 | SHORT e10
6537 | + e10
6538 | - e10
9306ca4a
JB		 6539 | ~ e10
6540 | NOT e10
64a0c779
DN		 6541 | e09 PTR e10
6542 | e09 : e10
6543 | e10
6544
6545 e10 e10 [ expr ]
b77a7acd 6546 | e11
64a0c779
DN		 6547
6548 e11 ( expr )
b77a7acd 6549 | [ expr ]
64a0c779
DN		 6550 | constant
6551 | dataType
6552 | id
6553 | $
6554 | register
6555
a724f0f4 6556 => expr expr cmpOp e04
9306ca4a 6557 | e04
64a0c779
DN		 6558
6559 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 6560 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 6561
6562 hexdigit a | b | c | d | e | f
b77a7acd 6563 | A | B | C | D | E | F
64a0c779
DN		 6564
6565 id alpha
b77a7acd 6566 | id alpha
64a0c779
DN		 6567 | id decdigit
6568
9306ca4a 6569 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 6570
6571 quote " | '
6572
6573 register specialRegister
b77a7acd 6574 | gpRegister
64a0c779
DN		 6575 | byteRegister
6576
6577 segmentRegister CS | DS | ES | FS | GS | SS
6578
9306ca4a 6579 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 6580 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 6581 | TR3 | TR4 | TR5 | TR6 | TR7
6582
64a0c779
DN		 6583 We simplify the grammar in obvious places (e.g., register parsing is
6584 done by calling parse_register) and eliminate immediate left recursion
6585 to implement a recursive-descent parser.
6586
a724f0f4
JB		 6587 expr e04 expr'
6588
6589 expr' cmpOp e04 expr'
6590 | Empty
9306ca4a
JB		 6591
6592 e04 e05 e04'
6593
6594 e04' addOp e05 e04'
6595 | Empty
64a0c779
DN		 6596
6597 e05 e06 e05'
6598
9306ca4a 6599 e05' binOp e06 e05'
b77a7acd 6600 | Empty
64a0c779
DN		 6601
6602 e06 e09 e06'
6603
6604 e06' mulOp e09 e06'
b77a7acd 6605 | Empty
64a0c779
DN		 6606
6607 e09 OFFSET e10 e09'
a724f0f4
JB		 6608 | SHORT e10'
6609 | + e10'
6610 | - e10'
6611 | ~ e10'
6612 | NOT e10'
b77a7acd 6613 | e10 e09'
64a0c779
DN		 6614
6615 e09' PTR e10 e09'
b77a7acd 6616 | : e10 e09'
64a0c779
DN		 6617 | Empty
6618
6619 e10 e11 e10'
6620
6621 e10' [ expr ] e10'
b77a7acd 6622 | Empty
64a0c779
DN		 6623
6624 e11 ( expr )
b77a7acd 6625 | [ expr ]
64a0c779
DN		 6626 | BYTE
6627 | WORD
6628 | DWORD
9306ca4a 6629 | FWORD
64a0c779 6630 | QWORD
9306ca4a
JB		 6631 | TBYTE
6632 | OWORD
6633 | XMMWORD
64a0c779
DN		 6634 | .
6635 | $
6636 | register
6637 | id
6638 | constant */
6639
6640/* Parsing structure for the intel syntax parser. Used to implement the
6641 semantic actions for the operand grammar. */
6642struct intel_parser_s
6643 {
6644 char *op_string; /* The string being parsed. */
6645 int got_a_float; /* Whether the operand is a float. */
4a1805b1 6646 int op_modifier; /* Operand modifier. */
64a0c779 6647 int is_mem; /* 1 if operand is memory reference. */
4eed87de
AM		 6648 int in_offset; /* >=1 if parsing operand of offset. */
6649 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 6650 const reg_entry *reg; /* Last register reference found. */
6651 char *disp; /* Displacement string being built. */
a724f0f4 6652 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 6653 };
6654
6655static struct intel_parser_s intel_parser;
6656
6657/* Token structure for parsing intel syntax. */
6658struct intel_token
6659 {
6660 int code; /* Token code. */
6661 const reg_entry *reg; /* Register entry for register tokens. */
6662 char *str; /* String representation. */
6663 };
6664
6665static struct intel_token cur_token, prev_token;
6666
50705ef4
AM		 6667/* Token codes for the intel parser. Since T_SHORT is already used
6668 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 6669#define T_NIL -1
6670#define T_CONST 1
6671#define T_REG 2
6672#define T_BYTE 3
6673#define T_WORD 4
9306ca4a
JB		 6674#define T_DWORD 5
6675#define T_FWORD 6
6676#define T_QWORD 7
6677#define T_TBYTE 8
6678#define T_XMMWORD 9
50705ef4 6679#undef T_SHORT
9306ca4a
JB		 6680#define T_SHORT 10
6681#define T_OFFSET 11
6682#define T_PTR 12
6683#define T_ID 13
6684#define T_SHL 14
6685#define T_SHR 15
64a0c779
DN		 6686
6687/* Prototypes for intel parser functions. */
e3bb37b5
L		 6688static int intel_match_token (int);
6689static void intel_putback_token (void);
6690static void intel_get_token (void);
6691static int intel_expr (void);
6692static int intel_e04 (void);
6693static int intel_e05 (void);
6694static int intel_e06 (void);
6695static int intel_e09 (void);
6696static int intel_e10 (void);
6697static int intel_e11 (void);
64a0c779 6698
64a0c779 6699static int
e3bb37b5 6700i386_intel_operand (char *operand_string, int got_a_float)
64a0c779
DN		 6701{
6702 int ret;
6703 char *p;
6704
a724f0f4
JB		 6705 p = intel_parser.op_string = xstrdup (operand_string);
6706 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
6707
6708 for (;;)
64a0c779 6709 {
a724f0f4
JB		 6710 /* Initialize token holders. */
6711 cur_token.code = prev_token.code = T_NIL;
6712 cur_token.reg = prev_token.reg = NULL;
6713 cur_token.str = prev_token.str = NULL;
6714
6715 /* Initialize parser structure. */
6716 intel_parser.got_a_float = got_a_float;
6717 intel_parser.op_modifier = 0;
6718 intel_parser.is_mem = 0;
6719 intel_parser.in_offset = 0;
6720 intel_parser.in_bracket = 0;
6721 intel_parser.reg = NULL;
6722 intel_parser.disp[0] = '\0';
6723 intel_parser.next_operand = NULL;
6724
6725 /* Read the first token and start the parser. */
6726 intel_get_token ();
6727 ret = intel_expr ();
6728
6729 if (!ret)
6730 break;
6731
9306ca4a
JB		 6732 if (cur_token.code != T_NIL)
6733 {
6734 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6735 current_templates->start->name, cur_token.str);
6736 ret = 0;
6737 }
64a0c779
DN		 6738 /* If we found a memory reference, hand it over to i386_displacement
6739 to fill in the rest of the operand fields. */
9306ca4a 6740 else if (intel_parser.is_mem)
64a0c779
DN		 6741 {
6742 if ((i.mem_operands == 1
6743 && (current_templates->start->opcode_modifier & IsString) == 0)
6744 || i.mem_operands == 2)
6745 {
6746 as_bad (_("too many memory references for '%s'"),
6747 current_templates->start->name);
6748 ret = 0;
6749 }
6750 else
6751 {
6752 char *s = intel_parser.disp;
6753 i.mem_operands++;
6754
a724f0f4
JB		 6755 if (!quiet_warnings && intel_parser.is_mem < 0)
6756 /* See the comments in intel_bracket_expr. */
6757 as_warn (_("Treating `%s' as memory reference"), operand_string);
6758
64a0c779
DN		 6759 /* Add the displacement expression. */
6760 if (*s != '\0')
a4622f40
AM		 6761 ret = i386_displacement (s, s + strlen (s));
6762 if (ret)
a724f0f4
JB		 6763 {
6764 /* Swap base and index in 16-bit memory operands like
6765 [si+bx]. Since i386_index_check is also used in AT&T
6766 mode we have to do that here. */
6767 if (i.base_reg
6768 && i.index_reg
6769 && (i.base_reg->reg_type & Reg16)
6770 && (i.index_reg->reg_type & Reg16)
6771 && i.base_reg->reg_num >= 6
6772 && i.index_reg->reg_num < 6)
6773 {
6774 const reg_entry *base = i.index_reg;
6775
6776 i.index_reg = i.base_reg;
6777 i.base_reg = base;
6778 }
6779 ret = i386_index_check (operand_string);
6780 }
64a0c779
DN		 6781 }
6782 }
6783
6784 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 6785 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 6786 || intel_parser.reg == NULL)
6787 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 6788
6789 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
4eed87de 6790 ret = 0;
a724f0f4
JB		 6791 if (!ret || !intel_parser.next_operand)
6792 break;
6793 intel_parser.op_string = intel_parser.next_operand;
6794 this_operand = i.operands++;
64a0c779
DN		 6795 }
6796
6797 free (p);
6798 free (intel_parser.disp);
6799
6800 return ret;
6801}
6802
a724f0f4
JB		 6803#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6804
6805/* expr e04 expr'
6806
6807 expr' cmpOp e04 expr'
6808 | Empty */
64a0c779 6809static int
e3bb37b5 6810intel_expr (void)
64a0c779 6811{
a724f0f4
JB		 6812 /* XXX Implement the comparison operators. */
6813 return intel_e04 ();
9306ca4a
JB		 6814}
6815
a724f0f4 6816/* e04 e05 e04'
9306ca4a 6817
a724f0f4 6818 e04' addOp e05 e04'
9306ca4a
JB		 6819 | Empty */
6820static int
e3bb37b5 6821intel_e04 (void)
9306ca4a 6822{
a724f0f4 6823 int nregs = -1;
9306ca4a 6824
a724f0f4 6825 for (;;)
9306ca4a 6826 {
a724f0f4
JB		 6827 if (!intel_e05())
6828 return 0;
9306ca4a 6829
a724f0f4
JB		 6830 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6831 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 6832
a724f0f4
JB		 6833 if (cur_token.code == '+')
6834 nregs = -1;
6835 else if (cur_token.code == '-')
6836 nregs = NUM_ADDRESS_REGS;
6837 else
6838 return 1;
64a0c779 6839
a724f0f4
JB		 6840 strcat (intel_parser.disp, cur_token.str);
6841 intel_match_token (cur_token.code);
6842 }
64a0c779
DN		 6843}
6844
64a0c779
DN		 6845/* e05 e06 e05'
6846
9306ca4a 6847 e05' binOp e06 e05'
64a0c779
DN		 6848 | Empty */
6849static int
e3bb37b5 6850intel_e05 (void)
64a0c779 6851{
a724f0f4 6852 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6853
a724f0f4 6854 for (;;)
64a0c779 6855 {
a724f0f4
JB		 6856 if (!intel_e06())
6857 return 0;
6858
4eed87de
AM		 6859 if (cur_token.code == '&'
6860 || cur_token.code == '|'
6861 || cur_token.code == '^')
a724f0f4
JB		 6862 {
6863 char str[2];
6864
6865 str[0] = cur_token.code;
6866 str[1] = 0;
6867 strcat (intel_parser.disp, str);
6868 }
6869 else
6870 break;
9306ca4a 6871
64a0c779
DN		 6872 intel_match_token (cur_token.code);
6873
a724f0f4
JB		 6874 if (nregs < 0)
6875 nregs = ~nregs;
64a0c779 6876 }
a724f0f4
JB		 6877 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6878 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6879 return 1;
4a1805b1 6880}
64a0c779
DN		 6881
6882/* e06 e09 e06'
6883
6884 e06' mulOp e09 e06'
b77a7acd 6885 | Empty */
64a0c779 6886static int
e3bb37b5 6887intel_e06 (void)
64a0c779 6888{
a724f0f4 6889 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6890
a724f0f4 6891 for (;;)
64a0c779 6892 {
a724f0f4
JB		 6893 if (!intel_e09())
6894 return 0;
9306ca4a 6895
4eed87de
AM		 6896 if (cur_token.code == '*'
6897 || cur_token.code == '/'
6898 || cur_token.code == '%')
a724f0f4
JB		 6899 {
6900 char str[2];
9306ca4a 6901
a724f0f4
JB		 6902 str[0] = cur_token.code;
6903 str[1] = 0;
6904 strcat (intel_parser.disp, str);
6905 }
6906 else if (cur_token.code == T_SHL)
6907 strcat (intel_parser.disp, "<<");
6908 else if (cur_token.code == T_SHR)
6909 strcat (intel_parser.disp, ">>");
6910 else
6911 break;
9306ca4a 6912
64e74474 6913 intel_match_token (cur_token.code);
64a0c779 6914
a724f0f4
JB		 6915 if (nregs < 0)
6916 nregs = ~nregs;
64a0c779 6917 }
a724f0f4
JB		 6918 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6919 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6920 return 1;
64a0c779
DN		 6921}
6922
a724f0f4
JB		 6923/* e09 OFFSET e09
6924 | SHORT e09
6925 | + e09
6926 | - e09
6927 | ~ e09
6928 | NOT e09
9306ca4a
JB		 6929 | e10 e09'
6930
64a0c779 6931 e09' PTR e10 e09'
b77a7acd 6932 | : e10 e09'
64a0c779
DN		 6933 | Empty */
6934static int
e3bb37b5 6935intel_e09 (void)
64a0c779 6936{
a724f0f4
JB		 6937 int nregs = ~NUM_ADDRESS_REGS;
6938 int in_offset = 0;
6939
6940 for (;;)
64a0c779 6941 {
a724f0f4
JB		 6942 /* Don't consume constants here. */
6943 if (cur_token.code == '+' || cur_token.code == '-')
6944 {
6945 /* Need to look one token ahead - if the next token
6946 is a constant, the current token is its sign. */
6947 int next_code;
6948
6949 intel_match_token (cur_token.code);
6950 next_code = cur_token.code;
6951 intel_putback_token ();
6952 if (next_code == T_CONST)
6953 break;
6954 }
6955
6956 /* e09 OFFSET e09 */
6957 if (cur_token.code == T_OFFSET)
6958 {
6959 if (!in_offset++)
6960 ++intel_parser.in_offset;
6961 }
6962
6963 /* e09 SHORT e09 */
6964 else if (cur_token.code == T_SHORT)
6965 intel_parser.op_modifier |= 1 << T_SHORT;
6966
6967 /* e09 + e09 */
6968 else if (cur_token.code == '+')
6969 strcat (intel_parser.disp, "+");
6970
6971 /* e09 - e09
6972 | ~ e09
6973 | NOT e09 */
6974 else if (cur_token.code == '-' || cur_token.code == '~')
6975 {
6976 char str[2];
64a0c779 6977
a724f0f4
JB		 6978 if (nregs < 0)
6979 nregs = ~nregs;
6980 str[0] = cur_token.code;
6981 str[1] = 0;
6982 strcat (intel_parser.disp, str);
6983 }
6984
6985 /* e09 e10 e09' */
6986 else
6987 break;
6988
6989 intel_match_token (cur_token.code);
64a0c779
DN		 6990 }
6991
a724f0f4 6992 for (;;)
9306ca4a 6993 {
a724f0f4
JB		 6994 if (!intel_e10 ())
6995 return 0;
9306ca4a 6996
a724f0f4
JB		 6997 /* e09' PTR e10 e09' */
6998 if (cur_token.code == T_PTR)
6999 {
7000 char suffix;
9306ca4a 7001
a724f0f4
JB		 7002 if (prev_token.code == T_BYTE)
7003 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 7004
a724f0f4
JB		 7005 else if (prev_token.code == T_WORD)
7006 {
7007 if (current_templates->start->name[0] == 'l'
7008 && current_templates->start->name[2] == 's'
7009 && current_templates->start->name[3] == 0)
7010 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7011 else if (intel_parser.got_a_float == 2) /* "fi..." */
7012 suffix = SHORT_MNEM_SUFFIX;
7013 else
7014 suffix = WORD_MNEM_SUFFIX;
7015 }
64a0c779 7016
a724f0f4
JB		 7017 else if (prev_token.code == T_DWORD)
7018 {
7019 if (current_templates->start->name[0] == 'l'
7020 && current_templates->start->name[2] == 's'
7021 && current_templates->start->name[3] == 0)
7022 suffix = WORD_MNEM_SUFFIX;
7023 else if (flag_code == CODE_16BIT
7024 && (current_templates->start->opcode_modifier
435acd52 7025 & (Jump | JumpDword)))
a724f0f4
JB		 7026 suffix = LONG_DOUBLE_MNEM_SUFFIX;
7027 else if (intel_parser.got_a_float == 1) /* "f..." */
7028 suffix = SHORT_MNEM_SUFFIX;
7029 else
7030 suffix = LONG_MNEM_SUFFIX;
7031 }
9306ca4a 7032
a724f0f4
JB		 7033 else if (prev_token.code == T_FWORD)
7034 {
7035 if (current_templates->start->name[0] == 'l'
7036 && current_templates->start->name[2] == 's'
7037 && current_templates->start->name[3] == 0)
7038 suffix = LONG_MNEM_SUFFIX;
7039 else if (!intel_parser.got_a_float)
7040 {
7041 if (flag_code == CODE_16BIT)
7042 add_prefix (DATA_PREFIX_OPCODE);
7043 suffix = LONG_DOUBLE_MNEM_SUFFIX;
7044 }
7045 else
7046 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7047 }
64a0c779 7048
a724f0f4
JB		 7049 else if (prev_token.code == T_QWORD)
7050 {
7051 if (intel_parser.got_a_float == 1) /* "f..." */
7052 suffix = LONG_MNEM_SUFFIX;
7053 else
7054 suffix = QWORD_MNEM_SUFFIX;
7055 }
64a0c779 7056
a724f0f4
JB		 7057 else if (prev_token.code == T_TBYTE)
7058 {
7059 if (intel_parser.got_a_float == 1)
7060 suffix = LONG_DOUBLE_MNEM_SUFFIX;
7061 else
7062 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7063 }
9306ca4a 7064
a724f0f4 7065 else if (prev_token.code == T_XMMWORD)
9306ca4a 7066 {
a724f0f4
JB		 7067 /* XXX ignored for now, but accepted since gcc uses it */
7068 suffix = 0;
9306ca4a 7069 }
64a0c779 7070
f16b83df 7071 else
a724f0f4
JB		 7072 {
7073 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
7074 return 0;
7075 }
7076
435acd52
JB		 7077 /* Operands for jump/call using 'ptr' notation denote absolute
7078 addresses. */
7079 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7080 i.types[this_operand] |= JumpAbsolute;
7081
a724f0f4
JB		 7082 if (current_templates->start->base_opcode == 0x8d /* lea */)
7083 ;
7084 else if (!i.suffix)
7085 i.suffix = suffix;
7086 else if (i.suffix != suffix)
7087 {
7088 as_bad (_("Conflicting operand modifiers"));
7089 return 0;
7090 }
64a0c779 7091
9306ca4a
JB		 7092 }
7093
a724f0f4
JB		 7094 /* e09' : e10 e09' */
7095 else if (cur_token.code == ':')
9306ca4a 7096 {
a724f0f4
JB		 7097 if (prev_token.code != T_REG)
7098 {
7099 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
7100 segment/group identifier (which we don't have), using comma
7101 as the operand separator there is even less consistent, since
7102 there all branches only have a single operand. */
7103 if (this_operand != 0
7104 || intel_parser.in_offset
7105 || intel_parser.in_bracket
7106 || (!(current_templates->start->opcode_modifier
7107 & (Jump|JumpDword|JumpInterSegment))
7108 && !(current_templates->start->operand_types[0]
7109 & JumpAbsolute)))
7110 return intel_match_token (T_NIL);
7111 /* Remember the start of the 2nd operand and terminate 1st
7112 operand here.
7113 XXX This isn't right, yet (when SSSS:OOOO is right operand of
7114 another expression), but it gets at least the simplest case
7115 (a plain number or symbol on the left side) right. */
7116 intel_parser.next_operand = intel_parser.op_string;
7117 *--intel_parser.op_string = '\0';
7118 return intel_match_token (':');
7119 }
9306ca4a 7120 }
64a0c779 7121
a724f0f4 7122 /* e09' Empty */
64a0c779 7123 else
a724f0f4 7124 break;
64a0c779 7125
a724f0f4
JB		 7126 intel_match_token (cur_token.code);
7127
7128 }
7129
7130 if (in_offset)
7131 {
7132 --intel_parser.in_offset;
7133 if (nregs < 0)
7134 nregs = ~nregs;
7135 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 7136 {
a724f0f4 7137 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 7138 return 0;
7139 }
a724f0f4
JB		 7140 intel_parser.op_modifier |= 1 << T_OFFSET;
7141 }
9306ca4a 7142
a724f0f4
JB		 7143 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7144 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
7145 return 1;
7146}
64a0c779 7147
a724f0f4 7148static int
e3bb37b5 7149intel_bracket_expr (void)
a724f0f4
JB		 7150{
7151 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
7152 const char *start = intel_parser.op_string;
7153 int len;
7154
7155 if (i.op[this_operand].regs)
7156 return intel_match_token (T_NIL);
7157
7158 intel_match_token ('[');
7159
7160 /* Mark as a memory operand only if it's not already known to be an
7161 offset expression. If it's an offset expression, we need to keep
7162 the brace in. */
7163 if (!intel_parser.in_offset)
7164 {
7165 ++intel_parser.in_bracket;
435acd52
JB		 7166
7167 /* Operands for jump/call inside brackets denote absolute addresses. */
7168 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
7169 i.types[this_operand] |= JumpAbsolute;
7170
a724f0f4
JB		 7171 /* Unfortunately gas always diverged from MASM in a respect that can't
7172 be easily fixed without risking to break code sequences likely to be
7173 encountered (the testsuite even check for this): MASM doesn't consider
7174 an expression inside brackets unconditionally as a memory reference.
7175 When that is e.g. a constant, an offset expression, or the sum of the
7176 two, this is still taken as a constant load. gas, however, always
7177 treated these as memory references. As a compromise, we'll try to make
7178 offset expressions inside brackets work the MASM way (since that's
7179 less likely to be found in real world code), but make constants alone
7180 continue to work the traditional gas way. In either case, issue a
7181 warning. */
7182 intel_parser.op_modifier &= ~was_offset;
64a0c779 7183 }
a724f0f4 7184 else
64e74474 7185 strcat (intel_parser.disp, "[");
a724f0f4
JB		 7186
7187 /* Add a '+' to the displacement string if necessary. */
7188 if (*intel_parser.disp != '\0'
7189 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
7190 strcat (intel_parser.disp, "+");
64a0c779 7191
a724f0f4
JB		 7192 if (intel_expr ()
7193 && (len = intel_parser.op_string - start - 1,
7194 intel_match_token (']')))
64a0c779 7195 {
a724f0f4
JB		 7196 /* Preserve brackets when the operand is an offset expression. */
7197 if (intel_parser.in_offset)
7198 strcat (intel_parser.disp, "]");
7199 else
7200 {
7201 --intel_parser.in_bracket;
7202 if (i.base_reg || i.index_reg)
7203 intel_parser.is_mem = 1;
7204 if (!intel_parser.is_mem)
7205 {
7206 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
7207 /* Defer the warning until all of the operand was parsed. */
7208 intel_parser.is_mem = -1;
7209 else if (!quiet_warnings)
4eed87de
AM		 7210 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
7211 len, start, len, start);
a724f0f4
JB		 7212 }
7213 }
7214 intel_parser.op_modifier |= was_offset;
64a0c779 7215
a724f0f4 7216 return 1;
64a0c779 7217 }
a724f0f4 7218 return 0;
64a0c779
DN		 7219}
7220
7221/* e10 e11 e10'
7222
7223 e10' [ expr ] e10'
b77a7acd 7224 | Empty */
64a0c779 7225static int
e3bb37b5 7226intel_e10 (void)
64a0c779 7227{
a724f0f4
JB		 7228 if (!intel_e11 ())
7229 return 0;
64a0c779 7230
a724f0f4 7231 while (cur_token.code == '[')
64a0c779 7232 {
a724f0f4 7233 if (!intel_bracket_expr ())
21d6c4af 7234 return 0;
64a0c779
DN		 7235 }
7236
a724f0f4 7237 return 1;
64a0c779
DN		 7238}
7239
64a0c779 7240/* e11 ( expr )
b77a7acd 7241 | [ expr ]
64a0c779
DN		 7242 | BYTE
7243 | WORD
7244 | DWORD
9306ca4a 7245 | FWORD
64a0c779 7246 | QWORD
9306ca4a
JB		 7247 | TBYTE
7248 | OWORD
7249 | XMMWORD
4a1805b1 7250 | $
64a0c779
DN		 7251 | .
7252 | register
7253 | id
7254 | constant */
7255static int
e3bb37b5 7256intel_e11 (void)
64a0c779 7257{
a724f0f4 7258 switch (cur_token.code)
64a0c779 7259 {
a724f0f4
JB		 7260 /* e11 ( expr ) */
7261 case '(':
64a0c779
DN		 7262 intel_match_token ('(');
7263 strcat (intel_parser.disp, "(");
7264
7265 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 7266 {
7267 strcat (intel_parser.disp, ")");
7268 return 1;
7269 }
a724f0f4 7270 return 0;
4a1805b1 7271
a724f0f4
JB		 7272 /* e11 [ expr ] */
7273 case '[':
a724f0f4 7274 return intel_bracket_expr ();
64a0c779 7275
a724f0f4
JB		 7276 /* e11 $
7277 | . */
7278 case '.':
64a0c779
DN		 7279 strcat (intel_parser.disp, cur_token.str);
7280 intel_match_token (cur_token.code);
21d6c4af
DN		 7281
7282 /* Mark as a memory operand only if it's not already known to be an
7283 offset expression. */
a724f0f4 7284 if (!intel_parser.in_offset)
21d6c4af 7285 intel_parser.is_mem = 1;
64a0c779
DN		 7286
7287 return 1;
64a0c779 7288
a724f0f4
JB		 7289 /* e11 register */
7290 case T_REG:
7291 {
7292 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 7293
a724f0f4 7294 intel_match_token (T_REG);
64a0c779 7295
a724f0f4
JB		 7296 /* Check for segment change. */
7297 if (cur_token.code == ':')
7298 {
7299 if (!(reg->reg_type & (SReg2 | SReg3)))
7300 {
4eed87de
AM		 7301 as_bad (_("`%s' is not a valid segment register"),
7302 reg->reg_name);
a724f0f4
JB		 7303 return 0;
7304 }
7305 else if (i.seg[i.mem_operands])
7306 as_warn (_("Extra segment override ignored"));
7307 else
7308 {
7309 if (!intel_parser.in_offset)
7310 intel_parser.is_mem = 1;
7311 switch (reg->reg_num)
7312 {
7313 case 0:
7314 i.seg[i.mem_operands] = &es;
7315 break;
7316 case 1:
7317 i.seg[i.mem_operands] = &cs;
7318 break;
7319 case 2:
7320 i.seg[i.mem_operands] = &ss;
7321 break;
7322 case 3:
7323 i.seg[i.mem_operands] = &ds;
7324 break;
7325 case 4:
7326 i.seg[i.mem_operands] = &fs;
7327 break;
7328 case 5:
7329 i.seg[i.mem_operands] = &gs;
7330 break;
7331 }
7332 }
7333 }
64a0c779 7334
a724f0f4
JB		 7335 /* Not a segment register. Check for register scaling. */
7336 else if (cur_token.code == '*')
7337 {
7338 if (!intel_parser.in_bracket)
7339 {
7340 as_bad (_("Register scaling only allowed in memory operands"));
7341 return 0;
7342 }
64a0c779 7343
a724f0f4
JB		 7344 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
7345 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7346 else if (i.index_reg)
7347 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 7348
a724f0f4
JB		 7349 /* What follows must be a valid scale. */
7350 intel_match_token ('*');
7351 i.index_reg = reg;
7352 i.types[this_operand] |= BaseIndex;
64a0c779 7353
a724f0f4
JB		 7354 /* Set the scale after setting the register (otherwise,
7355 i386_scale will complain) */
7356 if (cur_token.code == '+' || cur_token.code == '-')
7357 {
7358 char *str, sign = cur_token.code;
7359 intel_match_token (cur_token.code);
7360 if (cur_token.code != T_CONST)
7361 {
7362 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7363 cur_token.str);
7364 return 0;
7365 }
7366 str = (char *) xmalloc (strlen (cur_token.str) + 2);
7367 strcpy (str + 1, cur_token.str);
7368 *str = sign;
7369 if (!i386_scale (str))
7370 return 0;
7371 free (str);
7372 }
7373 else if (!i386_scale (cur_token.str))
64a0c779 7374 return 0;
a724f0f4
JB		 7375 intel_match_token (cur_token.code);
7376 }
64a0c779 7377
a724f0f4
JB		 7378 /* No scaling. If this is a memory operand, the register is either a
7379 base register (first occurrence) or an index register (second
7380 occurrence). */
7b0441f6 7381 else if (intel_parser.in_bracket)
a724f0f4 7382 {
64a0c779 7383
a724f0f4
JB		 7384 if (!i.base_reg)
7385 i.base_reg = reg;
7386 else if (!i.index_reg)
7387 i.index_reg = reg;
7388 else
7389 {
7390 as_bad (_("Too many register references in memory operand"));
7391 return 0;
7392 }
64a0c779 7393
a724f0f4
JB		 7394 i.types[this_operand] |= BaseIndex;
7395 }
4a1805b1 7396
4d1bb795
JB		 7397 /* It's neither base nor index. */
7398 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4
JB		 7399 {
7400 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
7401 i.op[this_operand].regs = reg;
7402 i.reg_operands++;
7403 }
7404 else
7405 {
7406 as_bad (_("Invalid use of register"));
7407 return 0;
7408 }
64a0c779 7409
a724f0f4
JB		 7410 /* Since registers are not part of the displacement string (except
7411 when we're parsing offset operands), we may need to remove any
7412 preceding '+' from the displacement string. */
7413 if (*intel_parser.disp != '\0'
7414 && !intel_parser.in_offset)
7415 {
7416 char *s = intel_parser.disp;
7417 s += strlen (s) - 1;
7418 if (*s == '+')
7419 *s = '\0';
7420 }
4a1805b1 7421
a724f0f4
JB		 7422 return 1;
7423 }
7424
7425 /* e11 BYTE
7426 | WORD
7427 | DWORD
7428 | FWORD
7429 | QWORD
7430 | TBYTE
7431 | OWORD
7432 | XMMWORD */
7433 case T_BYTE:
7434 case T_WORD:
7435 case T_DWORD:
7436 case T_FWORD:
7437 case T_QWORD:
7438 case T_TBYTE:
7439 case T_XMMWORD:
7440 intel_match_token (cur_token.code);
64a0c779 7441
a724f0f4
JB		 7442 if (cur_token.code == T_PTR)
7443 return 1;
7444
7445 /* It must have been an identifier. */
7446 intel_putback_token ();
7447 cur_token.code = T_ID;
7448 /* FALLTHRU */
7449
7450 /* e11 id
7451 | constant */
7452 case T_ID:
7453 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 7454 {
7455 symbolS *symbolP;
7456
a724f0f4
JB		 7457 /* The identifier represents a memory reference only if it's not
7458 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 7459 symbolP = symbol_find(cur_token.str);
7460 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
7461 intel_parser.is_mem = 1;
7462 }
a724f0f4 7463 /* FALLTHRU */
64a0c779 7464
a724f0f4
JB		 7465 case T_CONST:
7466 case '-':
7467 case '+':
7468 {
7469 char *save_str, sign = 0;
64a0c779 7470
a724f0f4
JB		 7471 /* Allow constants that start with `+' or `-'. */
7472 if (cur_token.code == '-' || cur_token.code == '+')
7473 {
7474 sign = cur_token.code;
7475 intel_match_token (cur_token.code);
7476 if (cur_token.code != T_CONST)
7477 {
7478 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7479 cur_token.str);
7480 return 0;
7481 }
7482 }
64a0c779 7483
a724f0f4
JB		 7484 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
7485 strcpy (save_str + !!sign, cur_token.str);
7486 if (sign)
7487 *save_str = sign;
64a0c779 7488
a724f0f4
JB		 7489 /* Get the next token to check for register scaling. */
7490 intel_match_token (cur_token.code);
64a0c779 7491
4eed87de
AM		 7492 /* Check if this constant is a scaling factor for an
7493 index register. */
a724f0f4
JB		 7494 if (cur_token.code == '*')
7495 {
7496 if (intel_match_token ('*') && cur_token.code == T_REG)
7497 {
7498 const reg_entry *reg = cur_token.reg;
7499
7500 if (!intel_parser.in_bracket)
7501 {
4eed87de
AM		 7502 as_bad (_("Register scaling only allowed "
7503 "in memory operands"));
a724f0f4
JB		 7504 return 0;
7505 }
7506
4eed87de
AM		 7507 /* Disallow things like [1*si].
7508 sp and esp are invalid as index. */
7509 if (reg->reg_type & Reg16)
7510 reg = i386_regtab + REGNAM_AX + 4;
a724f0f4 7511 else if (i.index_reg)
4eed87de 7512 reg = i386_regtab + REGNAM_EAX + 4;
a724f0f4
JB		 7513
7514 /* The constant is followed by `* reg', so it must be
7515 a valid scale. */
7516 i.index_reg = reg;
7517 i.types[this_operand] |= BaseIndex;
7518
7519 /* Set the scale after setting the register (otherwise,
7520 i386_scale will complain) */
7521 if (!i386_scale (save_str))
64a0c779 7522 return 0;
a724f0f4
JB		 7523 intel_match_token (T_REG);
7524
7525 /* Since registers are not part of the displacement
7526 string, we may need to remove any preceding '+' from
7527 the displacement string. */
7528 if (*intel_parser.disp != '\0')
7529 {
7530 char *s = intel_parser.disp;
7531 s += strlen (s) - 1;
7532 if (*s == '+')
7533 *s = '\0';
7534 }
7535
7536 free (save_str);
7537
7538 return 1;
7539 }
64a0c779 7540
a724f0f4
JB		 7541 /* The constant was not used for register scaling. Since we have
7542 already consumed the token following `*' we now need to put it
7543 back in the stream. */
64a0c779 7544 intel_putback_token ();
a724f0f4 7545 }
64a0c779 7546
a724f0f4
JB		 7547 /* Add the constant to the displacement string. */
7548 strcat (intel_parser.disp, save_str);
7549 free (save_str);
64a0c779 7550
a724f0f4
JB		 7551 return 1;
7552 }
64a0c779
DN		 7553 }
7554
64a0c779
DN		 7555 as_bad (_("Unrecognized token '%s'"), cur_token.str);
7556 return 0;
7557}
7558
64a0c779
DN		 7559/* Match the given token against cur_token. If they match, read the next
7560 token from the operand string. */
7561static int
e3bb37b5 7562intel_match_token (int code)
64a0c779
DN		 7563{
7564 if (cur_token.code == code)
7565 {
7566 intel_get_token ();
7567 return 1;
7568 }
7569 else
7570 {
0477af35 7571 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 7572 return 0;
7573 }
7574}
7575
64a0c779
DN		 7576/* Read a new token from intel_parser.op_string and store it in cur_token. */
7577static void
e3bb37b5 7578intel_get_token (void)
64a0c779
DN		 7579{
7580 char *end_op;
7581 const reg_entry *reg;
7582 struct intel_token new_token;
7583
7584 new_token.code = T_NIL;
7585 new_token.reg = NULL;
7586 new_token.str = NULL;
7587
4a1805b1 7588 /* Free the memory allocated to the previous token and move
64a0c779
DN		 7589 cur_token to prev_token. */
7590 if (prev_token.str)
7591 free (prev_token.str);
7592
7593 prev_token = cur_token;
7594
7595 /* Skip whitespace. */
7596 while (is_space_char (*intel_parser.op_string))
7597 intel_parser.op_string++;
7598
7599 /* Return an empty token if we find nothing else on the line. */
7600 if (*intel_parser.op_string == '\0')
7601 {
7602 cur_token = new_token;
7603 return;
7604 }
7605
7606 /* The new token cannot be larger than the remainder of the operand
7607 string. */
a724f0f4 7608 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 7609 new_token.str[0] = '\0';
7610
7611 if (strchr ("0123456789", *intel_parser.op_string))
7612 {
7613 char *p = new_token.str;
7614 char *q = intel_parser.op_string;
7615 new_token.code = T_CONST;
7616
7617 /* Allow any kind of identifier char to encompass floating point and
7618 hexadecimal numbers. */
7619 while (is_identifier_char (*q))
7620 *p++ = *q++;
7621 *p = '\0';
7622
7623 /* Recognize special symbol names [0-9][bf]. */
7624 if (strlen (intel_parser.op_string) == 2
4a1805b1 7625 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 7626 || intel_parser.op_string[1] == 'f'))
7627 new_token.code = T_ID;
7628 }
7629
4d1bb795 7630 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 7631 {
4d1bb795
JB		 7632 size_t len = end_op - intel_parser.op_string;
7633
64a0c779
DN		 7634 new_token.code = T_REG;
7635 new_token.reg = reg;
7636
4d1bb795
JB		 7637 memcpy (new_token.str, intel_parser.op_string, len);
7638 new_token.str[len] = '\0';
64a0c779
DN		 7639 }
7640
7641 else if (is_identifier_char (*intel_parser.op_string))
7642 {
7643 char *p = new_token.str;
7644 char *q = intel_parser.op_string;
7645
7646 /* A '.' or '$' followed by an identifier char is an identifier.
7647 Otherwise, it's operator '.' followed by an expression. */
7648 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
7649 {
9306ca4a
JB		 7650 new_token.code = '.';
7651 new_token.str[0] = '.';
64a0c779
DN		 7652 new_token.str[1] = '\0';
7653 }
7654 else
7655 {
7656 while (is_identifier_char (*q) || *q == '@')
7657 *p++ = *q++;
7658 *p = '\0';
7659
9306ca4a
JB		 7660 if (strcasecmp (new_token.str, "NOT") == 0)
7661 new_token.code = '~';
7662
7663 else if (strcasecmp (new_token.str, "MOD") == 0)
7664 new_token.code = '%';
7665
7666 else if (strcasecmp (new_token.str, "AND") == 0)
7667 new_token.code = '&';
7668
7669 else if (strcasecmp (new_token.str, "OR") == 0)
7670 new_token.code = '|';
7671
7672 else if (strcasecmp (new_token.str, "XOR") == 0)
7673 new_token.code = '^';
7674
7675 else if (strcasecmp (new_token.str, "SHL") == 0)
7676 new_token.code = T_SHL;
7677
7678 else if (strcasecmp (new_token.str, "SHR") == 0)
7679 new_token.code = T_SHR;
7680
7681 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 7682 new_token.code = T_BYTE;
7683
7684 else if (strcasecmp (new_token.str, "WORD") == 0)
7685 new_token.code = T_WORD;
7686
7687 else if (strcasecmp (new_token.str, "DWORD") == 0)
7688 new_token.code = T_DWORD;
7689
9306ca4a
JB		 7690 else if (strcasecmp (new_token.str, "FWORD") == 0)
7691 new_token.code = T_FWORD;
7692
64a0c779
DN		 7693 else if (strcasecmp (new_token.str, "QWORD") == 0)
7694 new_token.code = T_QWORD;
7695
9306ca4a
JB		 7696 else if (strcasecmp (new_token.str, "TBYTE") == 0
7697 /* XXX remove (gcc still uses it) */
7698 || strcasecmp (new_token.str, "XWORD") == 0)
7699 new_token.code = T_TBYTE;
7700
7701 else if (strcasecmp (new_token.str, "XMMWORD") == 0
7702 || strcasecmp (new_token.str, "OWORD") == 0)
7703 new_token.code = T_XMMWORD;
64a0c779
DN		 7704
7705 else if (strcasecmp (new_token.str, "PTR") == 0)
7706 new_token.code = T_PTR;
7707
7708 else if (strcasecmp (new_token.str, "SHORT") == 0)
7709 new_token.code = T_SHORT;
7710
7711 else if (strcasecmp (new_token.str, "OFFSET") == 0)
7712 {
7713 new_token.code = T_OFFSET;
7714
7715 /* ??? This is not mentioned in the MASM grammar but gcc
7716 makes use of it with -mintel-syntax. OFFSET may be
7717 followed by FLAT: */
7718 if (strncasecmp (q, " FLAT:", 6) == 0)
7719 strcat (new_token.str, " FLAT:");
7720 }
7721
7722 /* ??? This is not mentioned in the MASM grammar. */
7723 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 7724 {
7725 new_token.code = T_OFFSET;
7726 if (*q == ':')
7727 strcat (new_token.str, ":");
7728 else
7729 as_bad (_("`:' expected"));
7730 }
64a0c779
DN		 7731
7732 else
7733 new_token.code = T_ID;
7734 }
7735 }
7736
9306ca4a
JB		 7737 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
7738 {
7739 new_token.code = *intel_parser.op_string;
7740 new_token.str[0] = *intel_parser.op_string;
7741 new_token.str[1] = '\0';
7742 }
7743
7744 else if (strchr ("<>", *intel_parser.op_string)
7745 && *intel_parser.op_string == *(intel_parser.op_string + 1))
7746 {
7747 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
7748 new_token.str[0] = *intel_parser.op_string;
7749 new_token.str[1] = *intel_parser.op_string;
7750 new_token.str[2] = '\0';
7751 }
7752
64a0c779 7753 else
0477af35 7754 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 7755
7756 intel_parser.op_string += strlen (new_token.str);
7757 cur_token = new_token;
7758}
7759
64a0c779
DN		 7760/* Put cur_token back into the token stream and make cur_token point to
7761 prev_token. */
7762static void
e3bb37b5 7763intel_putback_token (void)
64a0c779 7764{
a724f0f4
JB		 7765 if (cur_token.code != T_NIL)
7766 {
7767 intel_parser.op_string -= strlen (cur_token.str);
7768 free (cur_token.str);
7769 }
64a0c779 7770 cur_token = prev_token;
4a1805b1 7771
64a0c779
DN		 7772 /* Forget prev_token. */
7773 prev_token.code = T_NIL;
7774 prev_token.reg = NULL;
7775 prev_token.str = NULL;
7776}
54cfded0 7777
a4447b93 7778int
1df69f4f 7779tc_x86_regname_to_dw2regnum (char *regname)
54cfded0
AM		 7780{
7781 unsigned int regnum;
7782 unsigned int regnames_count;
089dfecd 7783 static const char *const regnames_32[] =
54cfded0 7784 {
a4447b93
RH		 7785 "eax", "ecx", "edx", "ebx",
7786 "esp", "ebp", "esi", "edi",
089dfecd
JB		 7787 "eip", "eflags", NULL,
7788 "st0", "st1", "st2", "st3",
7789 "st4", "st5", "st6", "st7",
7790 NULL, NULL,
7791 "xmm0", "xmm1", "xmm2", "xmm3",
7792 "xmm4", "xmm5", "xmm6", "xmm7",
7793 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7794 "mm4", "mm5", "mm6", "mm7",
7795 "fcw", "fsw", "mxcsr",
7796 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7797 "tr", "ldtr"
54cfded0 7798 };
089dfecd 7799 static const char *const regnames_64[] =
54cfded0 7800 {
089dfecd
JB		 7801 "rax", "rdx", "rcx", "rbx",
7802 "rsi", "rdi", "rbp", "rsp",
7803 "r8", "r9", "r10", "r11",
54cfded0 7804 "r12", "r13", "r14", "r15",
089dfecd
JB		 7805 "rip",
7806 "xmm0", "xmm1", "xmm2", "xmm3",
7807 "xmm4", "xmm5", "xmm6", "xmm7",
7808 "xmm8", "xmm9", "xmm10", "xmm11",
7809 "xmm12", "xmm13", "xmm14", "xmm15",
7810 "st0", "st1", "st2", "st3",
7811 "st4", "st5", "st6", "st7",
7812 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7813 "mm4", "mm5", "mm6", "mm7",
7814 "rflags",
7815 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7816 "fs.base", "gs.base", NULL, NULL,
7817 "tr", "ldtr",
7818 "mxcsr", "fcw", "fsw"
54cfded0 7819 };
089dfecd 7820 const char *const *regnames;
54cfded0
AM		 7821
7822 if (flag_code == CODE_64BIT)
7823 {
7824 regnames = regnames_64;
0cea6190 7825 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 7826 }
7827 else
7828 {
7829 regnames = regnames_32;
0cea6190 7830 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 7831 }
7832
7833 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 7834 if (regnames[regnum] != NULL
7835 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 7836 return regnum;
7837
54cfded0
AM		 7838 return -1;
7839}
7840
7841void
7842tc_x86_frame_initial_instructions (void)
7843{
a4447b93
RH		 7844 static unsigned int sp_regno;
7845
7846 if (!sp_regno)
7847 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
7848 ? "rsp" : "esp");
7849
7850 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
7851 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 7852}
d2b2c203
DJ		 7853
7854int
7855i386_elf_section_type (const char *str, size_t len)
7856{
7857 if (flag_code == CODE_64BIT
7858 && len == sizeof ("unwind") - 1
7859 && strncmp (str, "unwind", 6) == 0)
7860 return SHT_X86_64_UNWIND;
7861
7862 return -1;
7863}
bb41ade5
AM		 7864
7865#ifdef TE_PE
7866void
7867tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7868{
7869 expressionS expr;
7870
7871 expr.X_op = O_secrel;
7872 expr.X_add_symbol = symbol;
7873 expr.X_add_number = 0;
7874 emit_expr (&expr, size);
7875}
7876#endif
3b22753a
L		 7877
7878#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7879/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7880
7881int
7882x86_64_section_letter (int letter, char **ptr_msg)
7883{
7884 if (flag_code == CODE_64BIT)
7885 {
7886 if (letter == 'l')
7887 return SHF_X86_64_LARGE;
7888
7889 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 7890 }
3b22753a 7891 else
64e74474 7892 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 7893 return -1;
7894}
7895
7896int
7897x86_64_section_word (char *str, size_t len)
7898{
8620418b 7899 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 7900 return SHF_X86_64_LARGE;
7901
7902 return -1;
7903}
7904
7905static void
7906handle_large_common (int small ATTRIBUTE_UNUSED)
7907{
7908 if (flag_code != CODE_64BIT)
7909 {
7910 s_comm_internal (0, elf_common_parse);
7911 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7912 }
7913 else
7914 {
7915 static segT lbss_section;
7916 asection *saved_com_section_ptr = elf_com_section_ptr;
7917 asection *saved_bss_section = bss_section;
7918
7919 if (lbss_section == NULL)
7920 {
7921 flagword applicable;
7922 segT seg = now_seg;
7923 subsegT subseg = now_subseg;
7924
7925 /* The .lbss section is for local .largecomm symbols. */
7926 lbss_section = subseg_new (".lbss", 0);
7927 applicable = bfd_applicable_section_flags (stdoutput);
7928 bfd_set_section_flags (stdoutput, lbss_section,
7929 applicable & SEC_ALLOC);
7930 seg_info (lbss_section)->bss = 1;
7931
7932 subseg_set (seg, subseg);
7933 }
7934
7935 elf_com_section_ptr = &_bfd_elf_large_com_section;
7936 bss_section = lbss_section;
7937
7938 s_comm_internal (0, elf_common_parse);
7939
7940 elf_com_section_ptr = saved_com_section_ptr;
7941 bss_section = saved_bss_section;
7942 }
7943}
7944#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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