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b534c6d3 | 1 | /* tc-i386.c -- Assemble code for the Intel 80386 |
82704155 | 2 | Copyright (C) 1989-2019 Free Software Foundation, Inc. |
252b5132 RH |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
19 | 02110-1301, USA. */ | |
252b5132 | 20 | |
47926f60 KH |
21 | /* Intel 80386 machine specific gas. |
22 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 23 | x86_64 support by Jan Hubicka (jh@suse.cz) |
0f10071e | 24 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
47926f60 KH |
25 | Bugs & suggestions are completely welcome. This is free software. |
26 | Please help us make it better. */ | |
252b5132 | 27 | |
252b5132 | 28 | #include "as.h" |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | #include "subsegs.h" |
316e2c05 | 31 | #include "dwarf2dbg.h" |
54cfded0 | 32 | #include "dw2gencfi.h" |
d2b2c203 | 33 | #include "elf/x86-64.h" |
40fb9820 | 34 | #include "opcodes/i386-init.h" |
252b5132 | 35 | |
41fd2579 L |
36 | #ifdef HAVE_LIMITS_H |
37 | #include <limits.h> | |
38 | #else | |
39 | #ifdef HAVE_SYS_PARAM_H | |
40 | #include <sys/param.h> | |
41 | #endif | |
42 | #ifndef INT_MAX | |
43 | #define INT_MAX (int) (((unsigned) (-1)) >> 1) | |
44 | #endif | |
45 | #endif | |
46 | ||
252b5132 RH |
47 | #ifndef REGISTER_WARNINGS |
48 | #define REGISTER_WARNINGS 1 | |
49 | #endif | |
50 | ||
c3332e24 | 51 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 52 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
53 | #endif |
54 | ||
29b0f896 AM |
55 | #ifndef DEFAULT_ARCH |
56 | #define DEFAULT_ARCH "i386" | |
246fcdee | 57 | #endif |
252b5132 | 58 | |
edde18a5 AM |
59 | #ifndef INLINE |
60 | #if __GNUC__ >= 2 | |
61 | #define INLINE __inline__ | |
62 | #else | |
63 | #define INLINE | |
64 | #endif | |
65 | #endif | |
66 | ||
6305a203 L |
67 | /* Prefixes will be emitted in the order defined below. |
68 | WAIT_PREFIX must be the first prefix since FWAIT is really is an | |
69 | instruction, and so must come before any prefixes. | |
70 | The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, | |
42164a71 | 71 | REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */ |
6305a203 L |
72 | #define WAIT_PREFIX 0 |
73 | #define SEG_PREFIX 1 | |
74 | #define ADDR_PREFIX 2 | |
75 | #define DATA_PREFIX 3 | |
c32fa91d | 76 | #define REP_PREFIX 4 |
42164a71 | 77 | #define HLE_PREFIX REP_PREFIX |
7e8b059b | 78 | #define BND_PREFIX REP_PREFIX |
c32fa91d | 79 | #define LOCK_PREFIX 5 |
4e9ac44a L |
80 | #define REX_PREFIX 6 /* must come last. */ |
81 | #define MAX_PREFIXES 7 /* max prefixes per opcode */ | |
6305a203 L |
82 | |
83 | /* we define the syntax here (modulo base,index,scale syntax) */ | |
84 | #define REGISTER_PREFIX '%' | |
85 | #define IMMEDIATE_PREFIX '$' | |
86 | #define ABSOLUTE_PREFIX '*' | |
87 | ||
88 | /* these are the instruction mnemonic suffixes in AT&T syntax or | |
89 | memory operand size in Intel syntax. */ | |
90 | #define WORD_MNEM_SUFFIX 'w' | |
91 | #define BYTE_MNEM_SUFFIX 'b' | |
92 | #define SHORT_MNEM_SUFFIX 's' | |
93 | #define LONG_MNEM_SUFFIX 'l' | |
94 | #define QWORD_MNEM_SUFFIX 'q' | |
6305a203 L |
95 | /* Intel Syntax. Use a non-ascii letter since since it never appears |
96 | in instructions. */ | |
97 | #define LONG_DOUBLE_MNEM_SUFFIX '\1' | |
98 | ||
99 | #define END_OF_INSN '\0' | |
100 | ||
101 | /* | |
102 | 'templates' is for grouping together 'template' structures for opcodes | |
103 | of the same name. This is only used for storing the insns in the grand | |
104 | ole hash table of insns. | |
105 | The templates themselves start at START and range up to (but not including) | |
106 | END. | |
107 | */ | |
108 | typedef struct | |
109 | { | |
d3ce72d0 NC |
110 | const insn_template *start; |
111 | const insn_template *end; | |
6305a203 L |
112 | } |
113 | templates; | |
114 | ||
115 | /* 386 operand encoding bytes: see 386 book for details of this. */ | |
116 | typedef struct | |
117 | { | |
118 | unsigned int regmem; /* codes register or memory operand */ | |
119 | unsigned int reg; /* codes register operand (or extended opcode) */ | |
120 | unsigned int mode; /* how to interpret regmem & reg */ | |
121 | } | |
122 | modrm_byte; | |
123 | ||
124 | /* x86-64 extension prefix. */ | |
125 | typedef int rex_byte; | |
126 | ||
6305a203 L |
127 | /* 386 opcode byte to code indirect addressing. */ |
128 | typedef struct | |
129 | { | |
130 | unsigned base; | |
131 | unsigned index; | |
132 | unsigned scale; | |
133 | } | |
134 | sib_byte; | |
135 | ||
6305a203 L |
136 | /* x86 arch names, types and features */ |
137 | typedef struct | |
138 | { | |
139 | const char *name; /* arch name */ | |
8a2c8fef | 140 | unsigned int len; /* arch string length */ |
6305a203 L |
141 | enum processor_type type; /* arch type */ |
142 | i386_cpu_flags flags; /* cpu feature flags */ | |
8a2c8fef | 143 | unsigned int skip; /* show_arch should skip this. */ |
6305a203 L |
144 | } |
145 | arch_entry; | |
146 | ||
293f5f65 L |
147 | /* Used to turn off indicated flags. */ |
148 | typedef struct | |
149 | { | |
150 | const char *name; /* arch name */ | |
151 | unsigned int len; /* arch string length */ | |
152 | i386_cpu_flags flags; /* cpu feature flags */ | |
153 | } | |
154 | noarch_entry; | |
155 | ||
78f12dd3 | 156 | static void update_code_flag (int, int); |
e3bb37b5 L |
157 | static void set_code_flag (int); |
158 | static void set_16bit_gcc_code_flag (int); | |
159 | static void set_intel_syntax (int); | |
1efbbeb4 | 160 | static void set_intel_mnemonic (int); |
db51cc60 | 161 | static void set_allow_index_reg (int); |
7bab8ab5 | 162 | static void set_check (int); |
e3bb37b5 | 163 | static void set_cpu_arch (int); |
6482c264 | 164 | #ifdef TE_PE |
e3bb37b5 | 165 | static void pe_directive_secrel (int); |
6482c264 | 166 | #endif |
e3bb37b5 L |
167 | static void signed_cons (int); |
168 | static char *output_invalid (int c); | |
ee86248c JB |
169 | static int i386_finalize_immediate (segT, expressionS *, i386_operand_type, |
170 | const char *); | |
171 | static int i386_finalize_displacement (segT, expressionS *, i386_operand_type, | |
172 | const char *); | |
a7619375 | 173 | static int i386_att_operand (char *); |
e3bb37b5 | 174 | static int i386_intel_operand (char *, int); |
ee86248c JB |
175 | static int i386_intel_simplify (expressionS *); |
176 | static int i386_intel_parse_name (const char *, expressionS *); | |
e3bb37b5 L |
177 | static const reg_entry *parse_register (char *, char **); |
178 | static char *parse_insn (char *, char *); | |
179 | static char *parse_operands (char *, const char *); | |
180 | static void swap_operands (void); | |
4d456e3d | 181 | static void swap_2_operands (int, int); |
e3bb37b5 L |
182 | static void optimize_imm (void); |
183 | static void optimize_disp (void); | |
83b16ac6 | 184 | static const insn_template *match_template (char); |
e3bb37b5 L |
185 | static int check_string (void); |
186 | static int process_suffix (void); | |
187 | static int check_byte_reg (void); | |
188 | static int check_long_reg (void); | |
189 | static int check_qword_reg (void); | |
190 | static int check_word_reg (void); | |
191 | static int finalize_imm (void); | |
192 | static int process_operands (void); | |
193 | static const seg_entry *build_modrm_byte (void); | |
194 | static void output_insn (void); | |
195 | static void output_imm (fragS *, offsetT); | |
196 | static void output_disp (fragS *, offsetT); | |
29b0f896 | 197 | #ifndef I386COFF |
e3bb37b5 | 198 | static void s_bss (int); |
252b5132 | 199 | #endif |
17d4e2a2 L |
200 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
201 | static void handle_large_common (int small ATTRIBUTE_UNUSED); | |
b4a3a7b4 L |
202 | |
203 | /* GNU_PROPERTY_X86_ISA_1_USED. */ | |
204 | static unsigned int x86_isa_1_used; | |
205 | /* GNU_PROPERTY_X86_FEATURE_2_USED. */ | |
206 | static unsigned int x86_feature_2_used; | |
207 | /* Generate x86 used ISA and feature properties. */ | |
208 | static unsigned int x86_used_note = DEFAULT_X86_USED_NOTE; | |
17d4e2a2 | 209 | #endif |
252b5132 | 210 | |
a847613f | 211 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 212 | |
43234a1e L |
213 | /* This struct describes rounding control and SAE in the instruction. */ |
214 | struct RC_Operation | |
215 | { | |
216 | enum rc_type | |
217 | { | |
218 | rne = 0, | |
219 | rd, | |
220 | ru, | |
221 | rz, | |
222 | saeonly | |
223 | } type; | |
224 | int operand; | |
225 | }; | |
226 | ||
227 | static struct RC_Operation rc_op; | |
228 | ||
229 | /* The struct describes masking, applied to OPERAND in the instruction. | |
230 | MASK is a pointer to the corresponding mask register. ZEROING tells | |
231 | whether merging or zeroing mask is used. */ | |
232 | struct Mask_Operation | |
233 | { | |
234 | const reg_entry *mask; | |
235 | unsigned int zeroing; | |
236 | /* The operand where this operation is associated. */ | |
237 | int operand; | |
238 | }; | |
239 | ||
240 | static struct Mask_Operation mask_op; | |
241 | ||
242 | /* The struct describes broadcasting, applied to OPERAND. FACTOR is | |
243 | broadcast factor. */ | |
244 | struct Broadcast_Operation | |
245 | { | |
8e6e0792 | 246 | /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */ |
43234a1e L |
247 | int type; |
248 | ||
249 | /* Index of broadcasted operand. */ | |
250 | int operand; | |
4a1b91ea L |
251 | |
252 | /* Number of bytes to broadcast. */ | |
253 | int bytes; | |
43234a1e L |
254 | }; |
255 | ||
256 | static struct Broadcast_Operation broadcast_op; | |
257 | ||
c0f3af97 L |
258 | /* VEX prefix. */ |
259 | typedef struct | |
260 | { | |
43234a1e L |
261 | /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */ |
262 | unsigned char bytes[4]; | |
c0f3af97 L |
263 | unsigned int length; |
264 | /* Destination or source register specifier. */ | |
265 | const reg_entry *register_specifier; | |
266 | } vex_prefix; | |
267 | ||
252b5132 | 268 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 269 | i386_insn. */ |
252b5132 | 270 | |
520dc8e8 AM |
271 | union i386_op |
272 | { | |
273 | expressionS *disps; | |
274 | expressionS *imms; | |
275 | const reg_entry *regs; | |
276 | }; | |
277 | ||
a65babc9 L |
278 | enum i386_error |
279 | { | |
86e026a4 | 280 | operand_size_mismatch, |
a65babc9 L |
281 | operand_type_mismatch, |
282 | register_type_mismatch, | |
283 | number_of_operands_mismatch, | |
284 | invalid_instruction_suffix, | |
285 | bad_imm4, | |
a65babc9 L |
286 | unsupported_with_intel_mnemonic, |
287 | unsupported_syntax, | |
6c30d220 L |
288 | unsupported, |
289 | invalid_vsib_address, | |
7bab8ab5 | 290 | invalid_vector_register_set, |
43234a1e L |
291 | unsupported_vector_index_register, |
292 | unsupported_broadcast, | |
43234a1e L |
293 | broadcast_needed, |
294 | unsupported_masking, | |
295 | mask_not_on_destination, | |
296 | no_default_mask, | |
297 | unsupported_rc_sae, | |
298 | rc_sae_operand_not_last_imm, | |
299 | invalid_register_operand, | |
a65babc9 L |
300 | }; |
301 | ||
252b5132 RH |
302 | struct _i386_insn |
303 | { | |
47926f60 | 304 | /* TM holds the template for the insn were currently assembling. */ |
d3ce72d0 | 305 | insn_template tm; |
252b5132 | 306 | |
7d5e4556 L |
307 | /* SUFFIX holds the instruction size suffix for byte, word, dword |
308 | or qword, if given. */ | |
252b5132 RH |
309 | char suffix; |
310 | ||
47926f60 | 311 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
312 | unsigned int operands; |
313 | ||
314 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
315 | of given register, displacement, memory operands and immediate | |
47926f60 | 316 | operands. */ |
252b5132 RH |
317 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
318 | ||
319 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 320 | use OP[i] for the corresponding operand. */ |
40fb9820 | 321 | i386_operand_type types[MAX_OPERANDS]; |
252b5132 | 322 | |
520dc8e8 AM |
323 | /* Displacement expression, immediate expression, or register for each |
324 | operand. */ | |
325 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 326 | |
3e73aa7c JH |
327 | /* Flags for operands. */ |
328 | unsigned int flags[MAX_OPERANDS]; | |
329 | #define Operand_PCrel 1 | |
c48dadc9 | 330 | #define Operand_Mem 2 |
3e73aa7c | 331 | |
252b5132 | 332 | /* Relocation type for operand */ |
f86103b7 | 333 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
252b5132 | 334 | |
252b5132 RH |
335 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
336 | the base index byte below. */ | |
337 | const reg_entry *base_reg; | |
338 | const reg_entry *index_reg; | |
339 | unsigned int log2_scale_factor; | |
340 | ||
341 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 342 | explicit segment overrides are given. */ |
ce8a8b2f | 343 | const seg_entry *seg[2]; |
252b5132 | 344 | |
8325cc63 JB |
345 | /* Copied first memory operand string, for re-checking. */ |
346 | char *memop1_string; | |
347 | ||
252b5132 RH |
348 | /* PREFIX holds all the given prefix opcodes (usually null). |
349 | PREFIXES is the number of prefix opcodes. */ | |
350 | unsigned int prefixes; | |
351 | unsigned char prefix[MAX_PREFIXES]; | |
352 | ||
b4a3a7b4 L |
353 | /* Has MMX register operands. */ |
354 | bfd_boolean has_regmmx; | |
355 | ||
356 | /* Has XMM register operands. */ | |
357 | bfd_boolean has_regxmm; | |
358 | ||
359 | /* Has YMM register operands. */ | |
360 | bfd_boolean has_regymm; | |
361 | ||
362 | /* Has ZMM register operands. */ | |
363 | bfd_boolean has_regzmm; | |
364 | ||
252b5132 | 365 | /* RM and SIB are the modrm byte and the sib byte where the |
c1e679ec | 366 | addressing modes of this insn are encoded. */ |
252b5132 | 367 | modrm_byte rm; |
3e73aa7c | 368 | rex_byte rex; |
43234a1e | 369 | rex_byte vrex; |
252b5132 | 370 | sib_byte sib; |
c0f3af97 | 371 | vex_prefix vex; |
b6169b20 | 372 | |
43234a1e L |
373 | /* Masking attributes. */ |
374 | struct Mask_Operation *mask; | |
375 | ||
376 | /* Rounding control and SAE attributes. */ | |
377 | struct RC_Operation *rounding; | |
378 | ||
379 | /* Broadcasting attributes. */ | |
380 | struct Broadcast_Operation *broadcast; | |
381 | ||
382 | /* Compressed disp8*N attribute. */ | |
383 | unsigned int memshift; | |
384 | ||
86fa6981 L |
385 | /* Prefer load or store in encoding. */ |
386 | enum | |
387 | { | |
388 | dir_encoding_default = 0, | |
389 | dir_encoding_load, | |
64c49ab3 JB |
390 | dir_encoding_store, |
391 | dir_encoding_swap | |
86fa6981 | 392 | } dir_encoding; |
891edac4 | 393 | |
a501d77e L |
394 | /* Prefer 8bit or 32bit displacement in encoding. */ |
395 | enum | |
396 | { | |
397 | disp_encoding_default = 0, | |
398 | disp_encoding_8bit, | |
399 | disp_encoding_32bit | |
400 | } disp_encoding; | |
f8a5c266 | 401 | |
6b6b6807 L |
402 | /* Prefer the REX byte in encoding. */ |
403 | bfd_boolean rex_encoding; | |
404 | ||
b6f8c7c4 L |
405 | /* Disable instruction size optimization. */ |
406 | bfd_boolean no_optimize; | |
407 | ||
86fa6981 L |
408 | /* How to encode vector instructions. */ |
409 | enum | |
410 | { | |
411 | vex_encoding_default = 0, | |
412 | vex_encoding_vex2, | |
413 | vex_encoding_vex3, | |
414 | vex_encoding_evex | |
415 | } vec_encoding; | |
416 | ||
d5de92cf L |
417 | /* REP prefix. */ |
418 | const char *rep_prefix; | |
419 | ||
165de32a L |
420 | /* HLE prefix. */ |
421 | const char *hle_prefix; | |
42164a71 | 422 | |
7e8b059b L |
423 | /* Have BND prefix. */ |
424 | const char *bnd_prefix; | |
425 | ||
04ef582a L |
426 | /* Have NOTRACK prefix. */ |
427 | const char *notrack_prefix; | |
428 | ||
891edac4 | 429 | /* Error message. */ |
a65babc9 | 430 | enum i386_error error; |
252b5132 RH |
431 | }; |
432 | ||
433 | typedef struct _i386_insn i386_insn; | |
434 | ||
43234a1e L |
435 | /* Link RC type with corresponding string, that'll be looked for in |
436 | asm. */ | |
437 | struct RC_name | |
438 | { | |
439 | enum rc_type type; | |
440 | const char *name; | |
441 | unsigned int len; | |
442 | }; | |
443 | ||
444 | static const struct RC_name RC_NamesTable[] = | |
445 | { | |
446 | { rne, STRING_COMMA_LEN ("rn-sae") }, | |
447 | { rd, STRING_COMMA_LEN ("rd-sae") }, | |
448 | { ru, STRING_COMMA_LEN ("ru-sae") }, | |
449 | { rz, STRING_COMMA_LEN ("rz-sae") }, | |
450 | { saeonly, STRING_COMMA_LEN ("sae") }, | |
451 | }; | |
452 | ||
252b5132 RH |
453 | /* List of chars besides those in app.c:symbol_chars that can start an |
454 | operand. Used to prevent the scrubber eating vital white-space. */ | |
86fa6981 | 455 | const char extra_symbol_chars[] = "*%-([{}" |
252b5132 | 456 | #ifdef LEX_AT |
32137342 NC |
457 | "@" |
458 | #endif | |
459 | #ifdef LEX_QM | |
460 | "?" | |
252b5132 | 461 | #endif |
32137342 | 462 | ; |
252b5132 | 463 | |
29b0f896 AM |
464 | #if (defined (TE_I386AIX) \ |
465 | || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ | |
3896cfd5 | 466 | && !defined (TE_GNU) \ |
29b0f896 | 467 | && !defined (TE_LINUX) \ |
8d63c93e | 468 | && !defined (TE_NACL) \ |
29b0f896 | 469 | && !defined (TE_FreeBSD) \ |
5b806d27 | 470 | && !defined (TE_DragonFly) \ |
29b0f896 | 471 | && !defined (TE_NetBSD))) |
252b5132 | 472 | /* This array holds the chars that always start a comment. If the |
b3b91714 AM |
473 | pre-processor is disabled, these aren't very useful. The option |
474 | --divide will remove '/' from this list. */ | |
475 | const char *i386_comment_chars = "#/"; | |
476 | #define SVR4_COMMENT_CHARS 1 | |
252b5132 | 477 | #define PREFIX_SEPARATOR '\\' |
252b5132 | 478 | |
b3b91714 AM |
479 | #else |
480 | const char *i386_comment_chars = "#"; | |
481 | #define PREFIX_SEPARATOR '/' | |
482 | #endif | |
483 | ||
252b5132 RH |
484 | /* This array holds the chars that only start a comment at the beginning of |
485 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
486 | .line and .file directives will appear in the pre-processed output. |
487 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 488 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
489 | #NO_APP at the beginning of its output. |
490 | Also note that comments started like this one will always work if | |
252b5132 | 491 | '/' isn't otherwise defined. */ |
b3b91714 | 492 | const char line_comment_chars[] = "#/"; |
252b5132 | 493 | |
63a0b638 | 494 | const char line_separator_chars[] = ";"; |
252b5132 | 495 | |
ce8a8b2f AM |
496 | /* Chars that can be used to separate mant from exp in floating point |
497 | nums. */ | |
252b5132 RH |
498 | const char EXP_CHARS[] = "eE"; |
499 | ||
ce8a8b2f AM |
500 | /* Chars that mean this number is a floating point constant |
501 | As in 0f12.456 | |
502 | or 0d1.2345e12. */ | |
252b5132 RH |
503 | const char FLT_CHARS[] = "fFdDxX"; |
504 | ||
ce8a8b2f | 505 | /* Tables for lexical analysis. */ |
252b5132 RH |
506 | static char mnemonic_chars[256]; |
507 | static char register_chars[256]; | |
508 | static char operand_chars[256]; | |
509 | static char identifier_chars[256]; | |
510 | static char digit_chars[256]; | |
511 | ||
ce8a8b2f | 512 | /* Lexical macros. */ |
252b5132 RH |
513 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
514 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
515 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
516 | #define is_space_char(x) ((x) == ' ') | |
517 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
518 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
519 | ||
0234cb7c | 520 | /* All non-digit non-letter characters that may occur in an operand. */ |
252b5132 RH |
521 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
522 | ||
523 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
524 | effect this we maintain a stack of saved characters that we've smashed | |
525 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 526 | assembler instruction). */ |
252b5132 | 527 | static char save_stack[32]; |
ce8a8b2f | 528 | static char *save_stack_p; |
252b5132 RH |
529 | #define END_STRING_AND_SAVE(s) \ |
530 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
531 | #define RESTORE_END_STRING(s) \ | |
532 | do { *(s) = *--save_stack_p; } while (0) | |
533 | ||
47926f60 | 534 | /* The instruction we're assembling. */ |
252b5132 RH |
535 | static i386_insn i; |
536 | ||
537 | /* Possible templates for current insn. */ | |
538 | static const templates *current_templates; | |
539 | ||
31b2323c L |
540 | /* Per instruction expressionS buffers: max displacements & immediates. */ |
541 | static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; | |
542 | static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; | |
252b5132 | 543 | |
47926f60 | 544 | /* Current operand we are working on. */ |
ee86248c | 545 | static int this_operand = -1; |
252b5132 | 546 | |
3e73aa7c JH |
547 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
548 | these. */ | |
549 | ||
550 | enum flag_code { | |
551 | CODE_32BIT, | |
552 | CODE_16BIT, | |
553 | CODE_64BIT }; | |
554 | ||
555 | static enum flag_code flag_code; | |
4fa24527 | 556 | static unsigned int object_64bit; |
862be3fb | 557 | static unsigned int disallow_64bit_reloc; |
3e73aa7c JH |
558 | static int use_rela_relocations = 0; |
559 | ||
7af8ed2d NC |
560 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
561 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ | |
562 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) | |
563 | ||
351f65ca L |
564 | /* The ELF ABI to use. */ |
565 | enum x86_elf_abi | |
566 | { | |
567 | I386_ABI, | |
7f56bc95 L |
568 | X86_64_ABI, |
569 | X86_64_X32_ABI | |
351f65ca L |
570 | }; |
571 | ||
572 | static enum x86_elf_abi x86_elf_abi = I386_ABI; | |
7af8ed2d | 573 | #endif |
351f65ca | 574 | |
167ad85b TG |
575 | #if defined (TE_PE) || defined (TE_PEP) |
576 | /* Use big object file format. */ | |
577 | static int use_big_obj = 0; | |
578 | #endif | |
579 | ||
8dcea932 L |
580 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
581 | /* 1 if generating code for a shared library. */ | |
582 | static int shared = 0; | |
583 | #endif | |
584 | ||
47926f60 KH |
585 | /* 1 for intel syntax, |
586 | 0 if att syntax. */ | |
587 | static int intel_syntax = 0; | |
252b5132 | 588 | |
e89c5eaa L |
589 | /* 1 for Intel64 ISA, |
590 | 0 if AMD64 ISA. */ | |
591 | static int intel64; | |
592 | ||
1efbbeb4 L |
593 | /* 1 for intel mnemonic, |
594 | 0 if att mnemonic. */ | |
595 | static int intel_mnemonic = !SYSV386_COMPAT; | |
596 | ||
a60de03c JB |
597 | /* 1 if pseudo registers are permitted. */ |
598 | static int allow_pseudo_reg = 0; | |
599 | ||
47926f60 KH |
600 | /* 1 if register prefix % not required. */ |
601 | static int allow_naked_reg = 0; | |
252b5132 | 602 | |
33eaf5de | 603 | /* 1 if the assembler should add BND prefix for all control-transferring |
7e8b059b L |
604 | instructions supporting it, even if this prefix wasn't specified |
605 | explicitly. */ | |
606 | static int add_bnd_prefix = 0; | |
607 | ||
ba104c83 | 608 | /* 1 if pseudo index register, eiz/riz, is allowed . */ |
db51cc60 L |
609 | static int allow_index_reg = 0; |
610 | ||
d022bddd IT |
611 | /* 1 if the assembler should ignore LOCK prefix, even if it was |
612 | specified explicitly. */ | |
613 | static int omit_lock_prefix = 0; | |
614 | ||
e4e00185 AS |
615 | /* 1 if the assembler should encode lfence, mfence, and sfence as |
616 | "lock addl $0, (%{re}sp)". */ | |
617 | static int avoid_fence = 0; | |
618 | ||
0cb4071e L |
619 | /* 1 if the assembler should generate relax relocations. */ |
620 | ||
621 | static int generate_relax_relocations | |
622 | = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS; | |
623 | ||
7bab8ab5 | 624 | static enum check_kind |
daf50ae7 | 625 | { |
7bab8ab5 JB |
626 | check_none = 0, |
627 | check_warning, | |
628 | check_error | |
daf50ae7 | 629 | } |
7bab8ab5 | 630 | sse_check, operand_check = check_warning; |
daf50ae7 | 631 | |
b6f8c7c4 L |
632 | /* Optimization: |
633 | 1. Clear the REX_W bit with register operand if possible. | |
634 | 2. Above plus use 128bit vector instruction to clear the full vector | |
635 | register. | |
636 | */ | |
637 | static int optimize = 0; | |
638 | ||
639 | /* Optimization: | |
640 | 1. Clear the REX_W bit with register operand if possible. | |
641 | 2. Above plus use 128bit vector instruction to clear the full vector | |
642 | register. | |
643 | 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to | |
644 | "testb $imm7,%r8". | |
645 | */ | |
646 | static int optimize_for_space = 0; | |
647 | ||
2ca3ace5 L |
648 | /* Register prefix used for error message. */ |
649 | static const char *register_prefix = "%"; | |
650 | ||
47926f60 KH |
651 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
652 | leave, push, and pop instructions so that gcc has the same stack | |
653 | frame as in 32 bit mode. */ | |
654 | static char stackop_size = '\0'; | |
eecb386c | 655 | |
12b55ccc L |
656 | /* Non-zero to optimize code alignment. */ |
657 | int optimize_align_code = 1; | |
658 | ||
47926f60 KH |
659 | /* Non-zero to quieten some warnings. */ |
660 | static int quiet_warnings = 0; | |
a38cf1db | 661 | |
47926f60 KH |
662 | /* CPU name. */ |
663 | static const char *cpu_arch_name = NULL; | |
6305a203 | 664 | static char *cpu_sub_arch_name = NULL; |
a38cf1db | 665 | |
47926f60 | 666 | /* CPU feature flags. */ |
40fb9820 L |
667 | static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; |
668 | ||
ccc9c027 L |
669 | /* If we have selected a cpu we are generating instructions for. */ |
670 | static int cpu_arch_tune_set = 0; | |
671 | ||
9103f4f4 | 672 | /* Cpu we are generating instructions for. */ |
fbf3f584 | 673 | enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; |
9103f4f4 L |
674 | |
675 | /* CPU feature flags of cpu we are generating instructions for. */ | |
40fb9820 | 676 | static i386_cpu_flags cpu_arch_tune_flags; |
9103f4f4 | 677 | |
ccc9c027 | 678 | /* CPU instruction set architecture used. */ |
fbf3f584 | 679 | enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; |
ccc9c027 | 680 | |
9103f4f4 | 681 | /* CPU feature flags of instruction set architecture used. */ |
fbf3f584 | 682 | i386_cpu_flags cpu_arch_isa_flags; |
9103f4f4 | 683 | |
fddf5b5b AM |
684 | /* If set, conditional jumps are not automatically promoted to handle |
685 | larger than a byte offset. */ | |
686 | static unsigned int no_cond_jump_promotion = 0; | |
687 | ||
c0f3af97 L |
688 | /* Encode SSE instructions with VEX prefix. */ |
689 | static unsigned int sse2avx; | |
690 | ||
539f890d L |
691 | /* Encode scalar AVX instructions with specific vector length. */ |
692 | static enum | |
693 | { | |
694 | vex128 = 0, | |
695 | vex256 | |
696 | } avxscalar; | |
697 | ||
03751133 L |
698 | /* Encode VEX WIG instructions with specific vex.w. */ |
699 | static enum | |
700 | { | |
701 | vexw0 = 0, | |
702 | vexw1 | |
703 | } vexwig; | |
704 | ||
43234a1e L |
705 | /* Encode scalar EVEX LIG instructions with specific vector length. */ |
706 | static enum | |
707 | { | |
708 | evexl128 = 0, | |
709 | evexl256, | |
710 | evexl512 | |
711 | } evexlig; | |
712 | ||
713 | /* Encode EVEX WIG instructions with specific evex.w. */ | |
714 | static enum | |
715 | { | |
716 | evexw0 = 0, | |
717 | evexw1 | |
718 | } evexwig; | |
719 | ||
d3d3c6db IT |
720 | /* Value to encode in EVEX RC bits, for SAE-only instructions. */ |
721 | static enum rc_type evexrcig = rne; | |
722 | ||
29b0f896 | 723 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
87c245cc | 724 | static symbolS *GOT_symbol; |
29b0f896 | 725 | |
a4447b93 RH |
726 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
727 | unsigned int x86_dwarf2_return_column; | |
728 | ||
729 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
730 | int x86_cie_data_alignment; | |
731 | ||
252b5132 | 732 | /* Interface to relax_segment. |
fddf5b5b AM |
733 | There are 3 major relax states for 386 jump insns because the |
734 | different types of jumps add different sizes to frags when we're | |
735 | figuring out what sort of jump to choose to reach a given label. */ | |
252b5132 | 736 | |
47926f60 | 737 | /* Types. */ |
93c2a809 AM |
738 | #define UNCOND_JUMP 0 |
739 | #define COND_JUMP 1 | |
740 | #define COND_JUMP86 2 | |
fddf5b5b | 741 | |
47926f60 | 742 | /* Sizes. */ |
252b5132 RH |
743 | #define CODE16 1 |
744 | #define SMALL 0 | |
29b0f896 | 745 | #define SMALL16 (SMALL | CODE16) |
252b5132 | 746 | #define BIG 2 |
29b0f896 | 747 | #define BIG16 (BIG | CODE16) |
252b5132 RH |
748 | |
749 | #ifndef INLINE | |
750 | #ifdef __GNUC__ | |
751 | #define INLINE __inline__ | |
752 | #else | |
753 | #define INLINE | |
754 | #endif | |
755 | #endif | |
756 | ||
fddf5b5b AM |
757 | #define ENCODE_RELAX_STATE(type, size) \ |
758 | ((relax_substateT) (((type) << 2) | (size))) | |
759 | #define TYPE_FROM_RELAX_STATE(s) \ | |
760 | ((s) >> 2) | |
761 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
762 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
763 | |
764 | /* This table is used by relax_frag to promote short jumps to long | |
765 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
766 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
767 | don't allow a short jump in a 32 bit code segment to be promoted to | |
768 | a 16 bit offset jump because it's slower (requires data size | |
769 | prefix), and doesn't work, unless the destination is in the bottom | |
770 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
771 | ||
772 | const relax_typeS md_relax_table[] = | |
773 | { | |
24eab124 AM |
774 | /* The fields are: |
775 | 1) most positive reach of this state, | |
776 | 2) most negative reach of this state, | |
93c2a809 | 777 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 778 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 779 | |
fddf5b5b | 780 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
781 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
782 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
783 | /* dword jmp adds 4 bytes to frag: | |
784 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 785 | {0, 0, 4, 0}, |
93c2a809 AM |
786 | /* word jmp adds 2 byte2 to frag: |
787 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
788 | {0, 0, 2, 0}, |
789 | ||
93c2a809 AM |
790 | /* COND_JUMP states. */ |
791 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
792 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
793 | /* dword conditionals adds 5 bytes to frag: | |
794 | 1 extra opcode byte, 4 displacement bytes. */ | |
795 | {0, 0, 5, 0}, | |
fddf5b5b | 796 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
797 | 1 extra opcode byte, 2 displacement bytes. */ |
798 | {0, 0, 3, 0}, | |
799 | ||
800 | /* COND_JUMP86 states. */ | |
801 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
802 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
803 | /* dword conditionals adds 5 bytes to frag: | |
804 | 1 extra opcode byte, 4 displacement bytes. */ | |
805 | {0, 0, 5, 0}, | |
806 | /* word conditionals add 4 bytes to frag: | |
807 | 1 displacement byte and a 3 byte long branch insn. */ | |
808 | {0, 0, 4, 0} | |
252b5132 RH |
809 | }; |
810 | ||
9103f4f4 L |
811 | static const arch_entry cpu_arch[] = |
812 | { | |
89507696 JB |
813 | /* Do not replace the first two entries - i386_target_format() |
814 | relies on them being there in this order. */ | |
8a2c8fef | 815 | { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32, |
293f5f65 | 816 | CPU_GENERIC32_FLAGS, 0 }, |
8a2c8fef | 817 | { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64, |
293f5f65 | 818 | CPU_GENERIC64_FLAGS, 0 }, |
8a2c8fef | 819 | { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN, |
293f5f65 | 820 | CPU_NONE_FLAGS, 0 }, |
8a2c8fef | 821 | { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN, |
293f5f65 | 822 | CPU_I186_FLAGS, 0 }, |
8a2c8fef | 823 | { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN, |
293f5f65 | 824 | CPU_I286_FLAGS, 0 }, |
8a2c8fef | 825 | { STRING_COMMA_LEN ("i386"), PROCESSOR_I386, |
293f5f65 | 826 | CPU_I386_FLAGS, 0 }, |
8a2c8fef | 827 | { STRING_COMMA_LEN ("i486"), PROCESSOR_I486, |
293f5f65 | 828 | CPU_I486_FLAGS, 0 }, |
8a2c8fef | 829 | { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM, |
293f5f65 | 830 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 831 | { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 832 | CPU_I686_FLAGS, 0 }, |
8a2c8fef | 833 | { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM, |
293f5f65 | 834 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 835 | { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 836 | CPU_PENTIUMPRO_FLAGS, 0 }, |
8a2c8fef | 837 | { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 838 | CPU_P2_FLAGS, 0 }, |
8a2c8fef | 839 | { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO, |
293f5f65 | 840 | CPU_P3_FLAGS, 0 }, |
8a2c8fef | 841 | { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4, |
293f5f65 | 842 | CPU_P4_FLAGS, 0 }, |
8a2c8fef | 843 | { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA, |
293f5f65 | 844 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 845 | { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA, |
293f5f65 | 846 | CPU_NOCONA_FLAGS, 0 }, |
8a2c8fef | 847 | { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE, |
293f5f65 | 848 | CPU_CORE_FLAGS, 1 }, |
8a2c8fef | 849 | { STRING_COMMA_LEN ("core"), PROCESSOR_CORE, |
293f5f65 | 850 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 851 | { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2, |
293f5f65 | 852 | CPU_CORE2_FLAGS, 1 }, |
8a2c8fef | 853 | { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2, |
293f5f65 | 854 | CPU_CORE2_FLAGS, 0 }, |
8a2c8fef | 855 | { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7, |
293f5f65 | 856 | CPU_COREI7_FLAGS, 0 }, |
8a2c8fef | 857 | { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM, |
293f5f65 | 858 | CPU_L1OM_FLAGS, 0 }, |
7a9068fe | 859 | { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM, |
293f5f65 | 860 | CPU_K1OM_FLAGS, 0 }, |
81486035 | 861 | { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU, |
293f5f65 | 862 | CPU_IAMCU_FLAGS, 0 }, |
8a2c8fef | 863 | { STRING_COMMA_LEN ("k6"), PROCESSOR_K6, |
293f5f65 | 864 | CPU_K6_FLAGS, 0 }, |
8a2c8fef | 865 | { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6, |
293f5f65 | 866 | CPU_K6_2_FLAGS, 0 }, |
8a2c8fef | 867 | { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON, |
293f5f65 | 868 | CPU_ATHLON_FLAGS, 0 }, |
8a2c8fef | 869 | { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8, |
293f5f65 | 870 | CPU_K8_FLAGS, 1 }, |
8a2c8fef | 871 | { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8, |
293f5f65 | 872 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 873 | { STRING_COMMA_LEN ("k8"), PROCESSOR_K8, |
293f5f65 | 874 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 875 | { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10, |
293f5f65 | 876 | CPU_AMDFAM10_FLAGS, 0 }, |
8aedb9fe | 877 | { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD, |
293f5f65 | 878 | CPU_BDVER1_FLAGS, 0 }, |
8aedb9fe | 879 | { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD, |
293f5f65 | 880 | CPU_BDVER2_FLAGS, 0 }, |
5e5c50d3 | 881 | { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD, |
293f5f65 | 882 | CPU_BDVER3_FLAGS, 0 }, |
c7b0bd56 | 883 | { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD, |
293f5f65 | 884 | CPU_BDVER4_FLAGS, 0 }, |
029f3522 | 885 | { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER, |
293f5f65 | 886 | CPU_ZNVER1_FLAGS, 0 }, |
a9660a6f AP |
887 | { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER, |
888 | CPU_ZNVER2_FLAGS, 0 }, | |
7b458c12 | 889 | { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT, |
293f5f65 | 890 | CPU_BTVER1_FLAGS, 0 }, |
7b458c12 | 891 | { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT, |
293f5f65 | 892 | CPU_BTVER2_FLAGS, 0 }, |
8a2c8fef | 893 | { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN, |
293f5f65 | 894 | CPU_8087_FLAGS, 0 }, |
8a2c8fef | 895 | { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN, |
293f5f65 | 896 | CPU_287_FLAGS, 0 }, |
8a2c8fef | 897 | { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN, |
293f5f65 | 898 | CPU_387_FLAGS, 0 }, |
1848e567 L |
899 | { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN, |
900 | CPU_687_FLAGS, 0 }, | |
d871f3f4 L |
901 | { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN, |
902 | CPU_CMOV_FLAGS, 0 }, | |
903 | { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN, | |
904 | CPU_FXSR_FLAGS, 0 }, | |
8a2c8fef | 905 | { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 906 | CPU_MMX_FLAGS, 0 }, |
8a2c8fef | 907 | { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN, |
293f5f65 | 908 | CPU_SSE_FLAGS, 0 }, |
8a2c8fef | 909 | { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN, |
293f5f65 | 910 | CPU_SSE2_FLAGS, 0 }, |
8a2c8fef | 911 | { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 912 | CPU_SSE3_FLAGS, 0 }, |
8a2c8fef | 913 | { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 914 | CPU_SSSE3_FLAGS, 0 }, |
8a2c8fef | 915 | { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN, |
293f5f65 | 916 | CPU_SSE4_1_FLAGS, 0 }, |
8a2c8fef | 917 | { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN, |
293f5f65 | 918 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 919 | { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN, |
293f5f65 | 920 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 921 | { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN, |
293f5f65 | 922 | CPU_AVX_FLAGS, 0 }, |
6c30d220 | 923 | { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN, |
293f5f65 | 924 | CPU_AVX2_FLAGS, 0 }, |
43234a1e | 925 | { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN, |
293f5f65 | 926 | CPU_AVX512F_FLAGS, 0 }, |
43234a1e | 927 | { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN, |
293f5f65 | 928 | CPU_AVX512CD_FLAGS, 0 }, |
43234a1e | 929 | { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN, |
293f5f65 | 930 | CPU_AVX512ER_FLAGS, 0 }, |
43234a1e | 931 | { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN, |
293f5f65 | 932 | CPU_AVX512PF_FLAGS, 0 }, |
1dfc6506 | 933 | { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN, |
293f5f65 | 934 | CPU_AVX512DQ_FLAGS, 0 }, |
1dfc6506 | 935 | { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN, |
293f5f65 | 936 | CPU_AVX512BW_FLAGS, 0 }, |
1dfc6506 | 937 | { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN, |
293f5f65 | 938 | CPU_AVX512VL_FLAGS, 0 }, |
8a2c8fef | 939 | { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 940 | CPU_VMX_FLAGS, 0 }, |
8729a6f6 | 941 | { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN, |
293f5f65 | 942 | CPU_VMFUNC_FLAGS, 0 }, |
8a2c8fef | 943 | { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN, |
293f5f65 | 944 | CPU_SMX_FLAGS, 0 }, |
8a2c8fef | 945 | { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN, |
293f5f65 | 946 | CPU_XSAVE_FLAGS, 0 }, |
c7b8aa3a | 947 | { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 948 | CPU_XSAVEOPT_FLAGS, 0 }, |
1dfc6506 | 949 | { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN, |
293f5f65 | 950 | CPU_XSAVEC_FLAGS, 0 }, |
1dfc6506 | 951 | { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN, |
293f5f65 | 952 | CPU_XSAVES_FLAGS, 0 }, |
8a2c8fef | 953 | { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN, |
293f5f65 | 954 | CPU_AES_FLAGS, 0 }, |
8a2c8fef | 955 | { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 956 | CPU_PCLMUL_FLAGS, 0 }, |
8a2c8fef | 957 | { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 958 | CPU_PCLMUL_FLAGS, 1 }, |
c7b8aa3a | 959 | { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN, |
293f5f65 | 960 | CPU_FSGSBASE_FLAGS, 0 }, |
c7b8aa3a | 961 | { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN, |
293f5f65 | 962 | CPU_RDRND_FLAGS, 0 }, |
c7b8aa3a | 963 | { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN, |
293f5f65 | 964 | CPU_F16C_FLAGS, 0 }, |
6c30d220 | 965 | { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN, |
293f5f65 | 966 | CPU_BMI2_FLAGS, 0 }, |
8a2c8fef | 967 | { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN, |
293f5f65 | 968 | CPU_FMA_FLAGS, 0 }, |
8a2c8fef | 969 | { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN, |
293f5f65 | 970 | CPU_FMA4_FLAGS, 0 }, |
8a2c8fef | 971 | { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN, |
293f5f65 | 972 | CPU_XOP_FLAGS, 0 }, |
8a2c8fef | 973 | { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN, |
293f5f65 | 974 | CPU_LWP_FLAGS, 0 }, |
8a2c8fef | 975 | { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN, |
293f5f65 | 976 | CPU_MOVBE_FLAGS, 0 }, |
60aa667e | 977 | { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN, |
293f5f65 | 978 | CPU_CX16_FLAGS, 0 }, |
8a2c8fef | 979 | { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN, |
293f5f65 | 980 | CPU_EPT_FLAGS, 0 }, |
6c30d220 | 981 | { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN, |
293f5f65 | 982 | CPU_LZCNT_FLAGS, 0 }, |
42164a71 | 983 | { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN, |
293f5f65 | 984 | CPU_HLE_FLAGS, 0 }, |
42164a71 | 985 | { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN, |
293f5f65 | 986 | CPU_RTM_FLAGS, 0 }, |
6c30d220 | 987 | { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN, |
293f5f65 | 988 | CPU_INVPCID_FLAGS, 0 }, |
8a2c8fef | 989 | { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN, |
293f5f65 | 990 | CPU_CLFLUSH_FLAGS, 0 }, |
22109423 | 991 | { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN, |
293f5f65 | 992 | CPU_NOP_FLAGS, 0 }, |
8a2c8fef | 993 | { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN, |
293f5f65 | 994 | CPU_SYSCALL_FLAGS, 0 }, |
8a2c8fef | 995 | { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN, |
293f5f65 | 996 | CPU_RDTSCP_FLAGS, 0 }, |
8a2c8fef | 997 | { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN, |
293f5f65 | 998 | CPU_3DNOW_FLAGS, 0 }, |
8a2c8fef | 999 | { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN, |
293f5f65 | 1000 | CPU_3DNOWA_FLAGS, 0 }, |
8a2c8fef | 1001 | { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN, |
293f5f65 | 1002 | CPU_PADLOCK_FLAGS, 0 }, |
8a2c8fef | 1003 | { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN, |
293f5f65 | 1004 | CPU_SVME_FLAGS, 1 }, |
8a2c8fef | 1005 | { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN, |
293f5f65 | 1006 | CPU_SVME_FLAGS, 0 }, |
8a2c8fef | 1007 | { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, |
293f5f65 | 1008 | CPU_SSE4A_FLAGS, 0 }, |
8a2c8fef | 1009 | { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN, |
293f5f65 | 1010 | CPU_ABM_FLAGS, 0 }, |
87973e9f | 1011 | { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 1012 | CPU_BMI_FLAGS, 0 }, |
2a2a0f38 | 1013 | { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN, |
293f5f65 | 1014 | CPU_TBM_FLAGS, 0 }, |
e2e1fcde | 1015 | { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1016 | CPU_ADX_FLAGS, 0 }, |
e2e1fcde | 1017 | { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN, |
293f5f65 | 1018 | CPU_RDSEED_FLAGS, 0 }, |
e2e1fcde | 1019 | { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN, |
293f5f65 | 1020 | CPU_PRFCHW_FLAGS, 0 }, |
5c111e37 | 1021 | { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN, |
293f5f65 | 1022 | CPU_SMAP_FLAGS, 0 }, |
7e8b059b | 1023 | { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1024 | CPU_MPX_FLAGS, 0 }, |
a0046408 | 1025 | { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN, |
293f5f65 | 1026 | CPU_SHA_FLAGS, 0 }, |
963f3586 | 1027 | { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 1028 | CPU_CLFLUSHOPT_FLAGS, 0 }, |
dcf893b5 | 1029 | { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN, |
293f5f65 | 1030 | CPU_PREFETCHWT1_FLAGS, 0 }, |
2cf200a4 | 1031 | { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN, |
293f5f65 | 1032 | CPU_SE1_FLAGS, 0 }, |
c5e7287a | 1033 | { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN, |
293f5f65 | 1034 | CPU_CLWB_FLAGS, 0 }, |
2cc1b5aa | 1035 | { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN, |
293f5f65 | 1036 | CPU_AVX512IFMA_FLAGS, 0 }, |
14f195c9 | 1037 | { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 1038 | CPU_AVX512VBMI_FLAGS, 0 }, |
920d2ddc IT |
1039 | { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN, |
1040 | CPU_AVX512_4FMAPS_FLAGS, 0 }, | |
47acf0bd IT |
1041 | { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN, |
1042 | CPU_AVX512_4VNNIW_FLAGS, 0 }, | |
620214f7 IT |
1043 | { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN, |
1044 | CPU_AVX512_VPOPCNTDQ_FLAGS, 0 }, | |
53467f57 IT |
1045 | { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN, |
1046 | CPU_AVX512_VBMI2_FLAGS, 0 }, | |
8cfcb765 IT |
1047 | { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN, |
1048 | CPU_AVX512_VNNI_FLAGS, 0 }, | |
ee6872be IT |
1049 | { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN, |
1050 | CPU_AVX512_BITALG_FLAGS, 0 }, | |
029f3522 | 1051 | { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN, |
293f5f65 | 1052 | CPU_CLZERO_FLAGS, 0 }, |
9916071f | 1053 | { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1054 | CPU_MWAITX_FLAGS, 0 }, |
8eab4136 | 1055 | { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN, |
293f5f65 | 1056 | CPU_OSPKE_FLAGS, 0 }, |
8bc52696 | 1057 | { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN, |
293f5f65 | 1058 | CPU_RDPID_FLAGS, 0 }, |
6b40c462 L |
1059 | { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN, |
1060 | CPU_PTWRITE_FLAGS, 0 }, | |
d777820b IT |
1061 | { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN, |
1062 | CPU_IBT_FLAGS, 0 }, | |
1063 | { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN, | |
1064 | CPU_SHSTK_FLAGS, 0 }, | |
48521003 IT |
1065 | { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN, |
1066 | CPU_GFNI_FLAGS, 0 }, | |
8dcf1fad IT |
1067 | { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN, |
1068 | CPU_VAES_FLAGS, 0 }, | |
ff1982d5 IT |
1069 | { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN, |
1070 | CPU_VPCLMULQDQ_FLAGS, 0 }, | |
3233d7d0 IT |
1071 | { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN, |
1072 | CPU_WBNOINVD_FLAGS, 0 }, | |
be3a8dca IT |
1073 | { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN, |
1074 | CPU_PCONFIG_FLAGS, 0 }, | |
de89d0a3 IT |
1075 | { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN, |
1076 | CPU_WAITPKG_FLAGS, 0 }, | |
c48935d7 IT |
1077 | { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN, |
1078 | CPU_CLDEMOTE_FLAGS, 0 }, | |
c0a30a9f L |
1079 | { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN, |
1080 | CPU_MOVDIRI_FLAGS, 0 }, | |
1081 | { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN, | |
1082 | CPU_MOVDIR64B_FLAGS, 0 }, | |
293f5f65 L |
1083 | }; |
1084 | ||
1085 | static const noarch_entry cpu_noarch[] = | |
1086 | { | |
1087 | { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS }, | |
1848e567 L |
1088 | { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS }, |
1089 | { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS }, | |
1090 | { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS }, | |
d871f3f4 L |
1091 | { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS }, |
1092 | { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS }, | |
293f5f65 L |
1093 | { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS }, |
1094 | { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS }, | |
1848e567 L |
1095 | { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS }, |
1096 | { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS }, | |
1097 | { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS }, | |
1098 | { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS }, | |
1099 | { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS }, | |
1100 | { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS }, | |
293f5f65 | 1101 | { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS }, |
1848e567 | 1102 | { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS }, |
144b71e2 L |
1103 | { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS }, |
1104 | { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS }, | |
1105 | { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS }, | |
1106 | { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS }, | |
1107 | { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS }, | |
1108 | { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS }, | |
1109 | { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS }, | |
1110 | { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS }, | |
1111 | { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS }, | |
920d2ddc | 1112 | { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS }, |
47acf0bd | 1113 | { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS }, |
620214f7 | 1114 | { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS }, |
53467f57 | 1115 | { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS }, |
8cfcb765 | 1116 | { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS }, |
ee6872be | 1117 | { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS }, |
d777820b IT |
1118 | { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS }, |
1119 | { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS }, | |
c0a30a9f L |
1120 | { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS }, |
1121 | { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS }, | |
e413e4e9 AM |
1122 | }; |
1123 | ||
704209c0 | 1124 | #ifdef I386COFF |
a6c24e68 NC |
1125 | /* Like s_lcomm_internal in gas/read.c but the alignment string |
1126 | is allowed to be optional. */ | |
1127 | ||
1128 | static symbolS * | |
1129 | pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size) | |
1130 | { | |
1131 | addressT align = 0; | |
1132 | ||
1133 | SKIP_WHITESPACE (); | |
1134 | ||
7ab9ffdd | 1135 | if (needs_align |
a6c24e68 NC |
1136 | && *input_line_pointer == ',') |
1137 | { | |
1138 | align = parse_align (needs_align - 1); | |
7ab9ffdd | 1139 | |
a6c24e68 NC |
1140 | if (align == (addressT) -1) |
1141 | return NULL; | |
1142 | } | |
1143 | else | |
1144 | { | |
1145 | if (size >= 8) | |
1146 | align = 3; | |
1147 | else if (size >= 4) | |
1148 | align = 2; | |
1149 | else if (size >= 2) | |
1150 | align = 1; | |
1151 | else | |
1152 | align = 0; | |
1153 | } | |
1154 | ||
1155 | bss_alloc (symbolP, size, align); | |
1156 | return symbolP; | |
1157 | } | |
1158 | ||
704209c0 | 1159 | static void |
a6c24e68 NC |
1160 | pe_lcomm (int needs_align) |
1161 | { | |
1162 | s_comm_internal (needs_align * 2, pe_lcomm_internal); | |
1163 | } | |
704209c0 | 1164 | #endif |
a6c24e68 | 1165 | |
29b0f896 AM |
1166 | const pseudo_typeS md_pseudo_table[] = |
1167 | { | |
1168 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) | |
1169 | {"align", s_align_bytes, 0}, | |
1170 | #else | |
1171 | {"align", s_align_ptwo, 0}, | |
1172 | #endif | |
1173 | {"arch", set_cpu_arch, 0}, | |
1174 | #ifndef I386COFF | |
1175 | {"bss", s_bss, 0}, | |
a6c24e68 NC |
1176 | #else |
1177 | {"lcomm", pe_lcomm, 1}, | |
29b0f896 AM |
1178 | #endif |
1179 | {"ffloat", float_cons, 'f'}, | |
1180 | {"dfloat", float_cons, 'd'}, | |
1181 | {"tfloat", float_cons, 'x'}, | |
1182 | {"value", cons, 2}, | |
d182319b | 1183 | {"slong", signed_cons, 4}, |
29b0f896 AM |
1184 | {"noopt", s_ignore, 0}, |
1185 | {"optim", s_ignore, 0}, | |
1186 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, | |
1187 | {"code16", set_code_flag, CODE_16BIT}, | |
1188 | {"code32", set_code_flag, CODE_32BIT}, | |
da5f19a2 | 1189 | #ifdef BFD64 |
29b0f896 | 1190 | {"code64", set_code_flag, CODE_64BIT}, |
da5f19a2 | 1191 | #endif |
29b0f896 AM |
1192 | {"intel_syntax", set_intel_syntax, 1}, |
1193 | {"att_syntax", set_intel_syntax, 0}, | |
1efbbeb4 L |
1194 | {"intel_mnemonic", set_intel_mnemonic, 1}, |
1195 | {"att_mnemonic", set_intel_mnemonic, 0}, | |
db51cc60 L |
1196 | {"allow_index_reg", set_allow_index_reg, 1}, |
1197 | {"disallow_index_reg", set_allow_index_reg, 0}, | |
7bab8ab5 JB |
1198 | {"sse_check", set_check, 0}, |
1199 | {"operand_check", set_check, 1}, | |
3b22753a L |
1200 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
1201 | {"largecomm", handle_large_common, 0}, | |
07a53e5c | 1202 | #else |
68d20676 | 1203 | {"file", dwarf2_directive_file, 0}, |
07a53e5c RH |
1204 | {"loc", dwarf2_directive_loc, 0}, |
1205 | {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, | |
3b22753a | 1206 | #endif |
6482c264 NC |
1207 | #ifdef TE_PE |
1208 | {"secrel32", pe_directive_secrel, 0}, | |
1209 | #endif | |
29b0f896 AM |
1210 | {0, 0, 0} |
1211 | }; | |
1212 | ||
1213 | /* For interface with expression (). */ | |
1214 | extern char *input_line_pointer; | |
1215 | ||
1216 | /* Hash table for instruction mnemonic lookup. */ | |
1217 | static struct hash_control *op_hash; | |
1218 | ||
1219 | /* Hash table for register lookup. */ | |
1220 | static struct hash_control *reg_hash; | |
1221 | \f | |
ce8a8b2f AM |
1222 | /* Various efficient no-op patterns for aligning code labels. |
1223 | Note: Don't try to assemble the instructions in the comments. | |
1224 | 0L and 0w are not legal. */ | |
62a02d25 L |
1225 | static const unsigned char f32_1[] = |
1226 | {0x90}; /* nop */ | |
1227 | static const unsigned char f32_2[] = | |
1228 | {0x66,0x90}; /* xchg %ax,%ax */ | |
1229 | static const unsigned char f32_3[] = | |
1230 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
1231 | static const unsigned char f32_4[] = | |
1232 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
62a02d25 L |
1233 | static const unsigned char f32_6[] = |
1234 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
1235 | static const unsigned char f32_7[] = | |
1236 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
62a02d25 | 1237 | static const unsigned char f16_3[] = |
3ae729d5 | 1238 | {0x8d,0x74,0x00}; /* lea 0(%si),%si */ |
62a02d25 | 1239 | static const unsigned char f16_4[] = |
3ae729d5 L |
1240 | {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */ |
1241 | static const unsigned char jump_disp8[] = | |
1242 | {0xeb}; /* jmp disp8 */ | |
1243 | static const unsigned char jump32_disp32[] = | |
1244 | {0xe9}; /* jmp disp32 */ | |
1245 | static const unsigned char jump16_disp32[] = | |
1246 | {0x66,0xe9}; /* jmp disp32 */ | |
62a02d25 L |
1247 | /* 32-bit NOPs patterns. */ |
1248 | static const unsigned char *const f32_patt[] = { | |
3ae729d5 | 1249 | f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7 |
62a02d25 L |
1250 | }; |
1251 | /* 16-bit NOPs patterns. */ | |
1252 | static const unsigned char *const f16_patt[] = { | |
3ae729d5 | 1253 | f32_1, f32_2, f16_3, f16_4 |
62a02d25 L |
1254 | }; |
1255 | /* nopl (%[re]ax) */ | |
1256 | static const unsigned char alt_3[] = | |
1257 | {0x0f,0x1f,0x00}; | |
1258 | /* nopl 0(%[re]ax) */ | |
1259 | static const unsigned char alt_4[] = | |
1260 | {0x0f,0x1f,0x40,0x00}; | |
1261 | /* nopl 0(%[re]ax,%[re]ax,1) */ | |
1262 | static const unsigned char alt_5[] = | |
1263 | {0x0f,0x1f,0x44,0x00,0x00}; | |
1264 | /* nopw 0(%[re]ax,%[re]ax,1) */ | |
1265 | static const unsigned char alt_6[] = | |
1266 | {0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
1267 | /* nopl 0L(%[re]ax) */ | |
1268 | static const unsigned char alt_7[] = | |
1269 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
1270 | /* nopl 0L(%[re]ax,%[re]ax,1) */ | |
1271 | static const unsigned char alt_8[] = | |
1272 | {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1273 | /* nopw 0L(%[re]ax,%[re]ax,1) */ | |
1274 | static const unsigned char alt_9[] = | |
1275 | {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1276 | /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
1277 | static const unsigned char alt_10[] = | |
1278 | {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
3ae729d5 L |
1279 | /* data16 nopw %cs:0L(%eax,%eax,1) */ |
1280 | static const unsigned char alt_11[] = | |
1281 | {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
62a02d25 L |
1282 | /* 32-bit and 64-bit NOPs patterns. */ |
1283 | static const unsigned char *const alt_patt[] = { | |
1284 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
3ae729d5 | 1285 | alt_9, alt_10, alt_11 |
62a02d25 L |
1286 | }; |
1287 | ||
1288 | /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum | |
1289 | size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */ | |
1290 | ||
1291 | static void | |
1292 | i386_output_nops (char *where, const unsigned char *const *patt, | |
1293 | int count, int max_single_nop_size) | |
1294 | ||
1295 | { | |
3ae729d5 L |
1296 | /* Place the longer NOP first. */ |
1297 | int last; | |
1298 | int offset; | |
1299 | const unsigned char *nops = patt[max_single_nop_size - 1]; | |
1300 | ||
1301 | /* Use the smaller one if the requsted one isn't available. */ | |
1302 | if (nops == NULL) | |
62a02d25 | 1303 | { |
3ae729d5 L |
1304 | max_single_nop_size--; |
1305 | nops = patt[max_single_nop_size - 1]; | |
62a02d25 L |
1306 | } |
1307 | ||
3ae729d5 L |
1308 | last = count % max_single_nop_size; |
1309 | ||
1310 | count -= last; | |
1311 | for (offset = 0; offset < count; offset += max_single_nop_size) | |
1312 | memcpy (where + offset, nops, max_single_nop_size); | |
1313 | ||
1314 | if (last) | |
1315 | { | |
1316 | nops = patt[last - 1]; | |
1317 | if (nops == NULL) | |
1318 | { | |
1319 | /* Use the smaller one plus one-byte NOP if the needed one | |
1320 | isn't available. */ | |
1321 | last--; | |
1322 | nops = patt[last - 1]; | |
1323 | memcpy (where + offset, nops, last); | |
1324 | where[offset + last] = *patt[0]; | |
1325 | } | |
1326 | else | |
1327 | memcpy (where + offset, nops, last); | |
1328 | } | |
62a02d25 L |
1329 | } |
1330 | ||
3ae729d5 L |
1331 | static INLINE int |
1332 | fits_in_imm7 (offsetT num) | |
1333 | { | |
1334 | return (num & 0x7f) == num; | |
1335 | } | |
1336 | ||
1337 | static INLINE int | |
1338 | fits_in_imm31 (offsetT num) | |
1339 | { | |
1340 | return (num & 0x7fffffff) == num; | |
1341 | } | |
62a02d25 L |
1342 | |
1343 | /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a | |
1344 | single NOP instruction LIMIT. */ | |
1345 | ||
1346 | void | |
3ae729d5 | 1347 | i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit) |
62a02d25 | 1348 | { |
3ae729d5 | 1349 | const unsigned char *const *patt = NULL; |
62a02d25 | 1350 | int max_single_nop_size; |
3ae729d5 L |
1351 | /* Maximum number of NOPs before switching to jump over NOPs. */ |
1352 | int max_number_of_nops; | |
62a02d25 | 1353 | |
3ae729d5 | 1354 | switch (fragP->fr_type) |
62a02d25 | 1355 | { |
3ae729d5 L |
1356 | case rs_fill_nop: |
1357 | case rs_align_code: | |
1358 | break; | |
1359 | default: | |
62a02d25 L |
1360 | return; |
1361 | } | |
1362 | ||
ccc9c027 L |
1363 | /* We need to decide which NOP sequence to use for 32bit and |
1364 | 64bit. When -mtune= is used: | |
4eed87de | 1365 | |
76bc74dc L |
1366 | 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and |
1367 | PROCESSOR_GENERIC32, f32_patt will be used. | |
80b8656c L |
1368 | 2. For the rest, alt_patt will be used. |
1369 | ||
1370 | When -mtune= isn't used, alt_patt will be used if | |
22109423 | 1371 | cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will |
76bc74dc | 1372 | be used. |
ccc9c027 L |
1373 | |
1374 | When -march= or .arch is used, we can't use anything beyond | |
1375 | cpu_arch_isa_flags. */ | |
1376 | ||
1377 | if (flag_code == CODE_16BIT) | |
1378 | { | |
3ae729d5 L |
1379 | patt = f16_patt; |
1380 | max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]); | |
1381 | /* Limit number of NOPs to 2 in 16-bit mode. */ | |
1382 | max_number_of_nops = 2; | |
252b5132 | 1383 | } |
33fef721 | 1384 | else |
ccc9c027 | 1385 | { |
fbf3f584 | 1386 | if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN) |
ccc9c027 L |
1387 | { |
1388 | /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ | |
1389 | switch (cpu_arch_tune) | |
1390 | { | |
1391 | case PROCESSOR_UNKNOWN: | |
1392 | /* We use cpu_arch_isa_flags to check if we SHOULD | |
22109423 L |
1393 | optimize with nops. */ |
1394 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1395 | patt = alt_patt; |
ccc9c027 L |
1396 | else |
1397 | patt = f32_patt; | |
1398 | break; | |
ccc9c027 L |
1399 | case PROCESSOR_PENTIUM4: |
1400 | case PROCESSOR_NOCONA: | |
ef05d495 | 1401 | case PROCESSOR_CORE: |
76bc74dc | 1402 | case PROCESSOR_CORE2: |
bd5295b2 | 1403 | case PROCESSOR_COREI7: |
3632d14b | 1404 | case PROCESSOR_L1OM: |
7a9068fe | 1405 | case PROCESSOR_K1OM: |
76bc74dc | 1406 | case PROCESSOR_GENERIC64: |
ccc9c027 L |
1407 | case PROCESSOR_K6: |
1408 | case PROCESSOR_ATHLON: | |
1409 | case PROCESSOR_K8: | |
4eed87de | 1410 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1411 | case PROCESSOR_BD: |
029f3522 | 1412 | case PROCESSOR_ZNVER: |
7b458c12 | 1413 | case PROCESSOR_BT: |
80b8656c | 1414 | patt = alt_patt; |
ccc9c027 | 1415 | break; |
76bc74dc | 1416 | case PROCESSOR_I386: |
ccc9c027 L |
1417 | case PROCESSOR_I486: |
1418 | case PROCESSOR_PENTIUM: | |
2dde1948 | 1419 | case PROCESSOR_PENTIUMPRO: |
81486035 | 1420 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1421 | case PROCESSOR_GENERIC32: |
1422 | patt = f32_patt; | |
1423 | break; | |
4eed87de | 1424 | } |
ccc9c027 L |
1425 | } |
1426 | else | |
1427 | { | |
fbf3f584 | 1428 | switch (fragP->tc_frag_data.tune) |
ccc9c027 L |
1429 | { |
1430 | case PROCESSOR_UNKNOWN: | |
e6a14101 | 1431 | /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be |
ccc9c027 L |
1432 | PROCESSOR_UNKNOWN. */ |
1433 | abort (); | |
1434 | break; | |
1435 | ||
76bc74dc | 1436 | case PROCESSOR_I386: |
ccc9c027 L |
1437 | case PROCESSOR_I486: |
1438 | case PROCESSOR_PENTIUM: | |
81486035 | 1439 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1440 | case PROCESSOR_K6: |
1441 | case PROCESSOR_ATHLON: | |
1442 | case PROCESSOR_K8: | |
4eed87de | 1443 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1444 | case PROCESSOR_BD: |
029f3522 | 1445 | case PROCESSOR_ZNVER: |
7b458c12 | 1446 | case PROCESSOR_BT: |
ccc9c027 L |
1447 | case PROCESSOR_GENERIC32: |
1448 | /* We use cpu_arch_isa_flags to check if we CAN optimize | |
22109423 L |
1449 | with nops. */ |
1450 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1451 | patt = alt_patt; |
ccc9c027 L |
1452 | else |
1453 | patt = f32_patt; | |
1454 | break; | |
76bc74dc L |
1455 | case PROCESSOR_PENTIUMPRO: |
1456 | case PROCESSOR_PENTIUM4: | |
1457 | case PROCESSOR_NOCONA: | |
1458 | case PROCESSOR_CORE: | |
ef05d495 | 1459 | case PROCESSOR_CORE2: |
bd5295b2 | 1460 | case PROCESSOR_COREI7: |
3632d14b | 1461 | case PROCESSOR_L1OM: |
7a9068fe | 1462 | case PROCESSOR_K1OM: |
22109423 | 1463 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) |
80b8656c | 1464 | patt = alt_patt; |
ccc9c027 L |
1465 | else |
1466 | patt = f32_patt; | |
1467 | break; | |
1468 | case PROCESSOR_GENERIC64: | |
80b8656c | 1469 | patt = alt_patt; |
ccc9c027 | 1470 | break; |
4eed87de | 1471 | } |
ccc9c027 L |
1472 | } |
1473 | ||
76bc74dc L |
1474 | if (patt == f32_patt) |
1475 | { | |
3ae729d5 L |
1476 | max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]); |
1477 | /* Limit number of NOPs to 2 for older processors. */ | |
1478 | max_number_of_nops = 2; | |
76bc74dc L |
1479 | } |
1480 | else | |
1481 | { | |
3ae729d5 L |
1482 | max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]); |
1483 | /* Limit number of NOPs to 7 for newer processors. */ | |
1484 | max_number_of_nops = 7; | |
1485 | } | |
1486 | } | |
1487 | ||
1488 | if (limit == 0) | |
1489 | limit = max_single_nop_size; | |
1490 | ||
1491 | if (fragP->fr_type == rs_fill_nop) | |
1492 | { | |
1493 | /* Output NOPs for .nop directive. */ | |
1494 | if (limit > max_single_nop_size) | |
1495 | { | |
1496 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1497 | _("invalid single nop size: %d " | |
1498 | "(expect within [0, %d])"), | |
1499 | limit, max_single_nop_size); | |
1500 | return; | |
1501 | } | |
1502 | } | |
1503 | else | |
1504 | fragP->fr_var = count; | |
1505 | ||
1506 | if ((count / max_single_nop_size) > max_number_of_nops) | |
1507 | { | |
1508 | /* Generate jump over NOPs. */ | |
1509 | offsetT disp = count - 2; | |
1510 | if (fits_in_imm7 (disp)) | |
1511 | { | |
1512 | /* Use "jmp disp8" if possible. */ | |
1513 | count = disp; | |
1514 | where[0] = jump_disp8[0]; | |
1515 | where[1] = count; | |
1516 | where += 2; | |
1517 | } | |
1518 | else | |
1519 | { | |
1520 | unsigned int size_of_jump; | |
1521 | ||
1522 | if (flag_code == CODE_16BIT) | |
1523 | { | |
1524 | where[0] = jump16_disp32[0]; | |
1525 | where[1] = jump16_disp32[1]; | |
1526 | size_of_jump = 2; | |
1527 | } | |
1528 | else | |
1529 | { | |
1530 | where[0] = jump32_disp32[0]; | |
1531 | size_of_jump = 1; | |
1532 | } | |
1533 | ||
1534 | count -= size_of_jump + 4; | |
1535 | if (!fits_in_imm31 (count)) | |
1536 | { | |
1537 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1538 | _("jump over nop padding out of range")); | |
1539 | return; | |
1540 | } | |
1541 | ||
1542 | md_number_to_chars (where + size_of_jump, count, 4); | |
1543 | where += size_of_jump + 4; | |
76bc74dc | 1544 | } |
ccc9c027 | 1545 | } |
3ae729d5 L |
1546 | |
1547 | /* Generate multiple NOPs. */ | |
1548 | i386_output_nops (where, patt, count, limit); | |
252b5132 RH |
1549 | } |
1550 | ||
c6fb90c8 | 1551 | static INLINE int |
0dfbf9d7 | 1552 | operand_type_all_zero (const union i386_operand_type *x) |
40fb9820 | 1553 | { |
0dfbf9d7 | 1554 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1555 | { |
1556 | case 3: | |
0dfbf9d7 | 1557 | if (x->array[2]) |
c6fb90c8 | 1558 | return 0; |
1a0670f3 | 1559 | /* Fall through. */ |
c6fb90c8 | 1560 | case 2: |
0dfbf9d7 | 1561 | if (x->array[1]) |
c6fb90c8 | 1562 | return 0; |
1a0670f3 | 1563 | /* Fall through. */ |
c6fb90c8 | 1564 | case 1: |
0dfbf9d7 | 1565 | return !x->array[0]; |
c6fb90c8 L |
1566 | default: |
1567 | abort (); | |
1568 | } | |
40fb9820 L |
1569 | } |
1570 | ||
c6fb90c8 | 1571 | static INLINE void |
0dfbf9d7 | 1572 | operand_type_set (union i386_operand_type *x, unsigned int v) |
40fb9820 | 1573 | { |
0dfbf9d7 | 1574 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1575 | { |
1576 | case 3: | |
0dfbf9d7 | 1577 | x->array[2] = v; |
1a0670f3 | 1578 | /* Fall through. */ |
c6fb90c8 | 1579 | case 2: |
0dfbf9d7 | 1580 | x->array[1] = v; |
1a0670f3 | 1581 | /* Fall through. */ |
c6fb90c8 | 1582 | case 1: |
0dfbf9d7 | 1583 | x->array[0] = v; |
1a0670f3 | 1584 | /* Fall through. */ |
c6fb90c8 L |
1585 | break; |
1586 | default: | |
1587 | abort (); | |
1588 | } | |
1589 | } | |
40fb9820 | 1590 | |
c6fb90c8 | 1591 | static INLINE int |
0dfbf9d7 L |
1592 | operand_type_equal (const union i386_operand_type *x, |
1593 | const union i386_operand_type *y) | |
c6fb90c8 | 1594 | { |
0dfbf9d7 | 1595 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1596 | { |
1597 | case 3: | |
0dfbf9d7 | 1598 | if (x->array[2] != y->array[2]) |
c6fb90c8 | 1599 | return 0; |
1a0670f3 | 1600 | /* Fall through. */ |
c6fb90c8 | 1601 | case 2: |
0dfbf9d7 | 1602 | if (x->array[1] != y->array[1]) |
c6fb90c8 | 1603 | return 0; |
1a0670f3 | 1604 | /* Fall through. */ |
c6fb90c8 | 1605 | case 1: |
0dfbf9d7 | 1606 | return x->array[0] == y->array[0]; |
c6fb90c8 L |
1607 | break; |
1608 | default: | |
1609 | abort (); | |
1610 | } | |
1611 | } | |
40fb9820 | 1612 | |
0dfbf9d7 L |
1613 | static INLINE int |
1614 | cpu_flags_all_zero (const union i386_cpu_flags *x) | |
1615 | { | |
1616 | switch (ARRAY_SIZE(x->array)) | |
1617 | { | |
53467f57 IT |
1618 | case 4: |
1619 | if (x->array[3]) | |
1620 | return 0; | |
1621 | /* Fall through. */ | |
0dfbf9d7 L |
1622 | case 3: |
1623 | if (x->array[2]) | |
1624 | return 0; | |
1a0670f3 | 1625 | /* Fall through. */ |
0dfbf9d7 L |
1626 | case 2: |
1627 | if (x->array[1]) | |
1628 | return 0; | |
1a0670f3 | 1629 | /* Fall through. */ |
0dfbf9d7 L |
1630 | case 1: |
1631 | return !x->array[0]; | |
1632 | default: | |
1633 | abort (); | |
1634 | } | |
1635 | } | |
1636 | ||
0dfbf9d7 L |
1637 | static INLINE int |
1638 | cpu_flags_equal (const union i386_cpu_flags *x, | |
1639 | const union i386_cpu_flags *y) | |
1640 | { | |
1641 | switch (ARRAY_SIZE(x->array)) | |
1642 | { | |
53467f57 IT |
1643 | case 4: |
1644 | if (x->array[3] != y->array[3]) | |
1645 | return 0; | |
1646 | /* Fall through. */ | |
0dfbf9d7 L |
1647 | case 3: |
1648 | if (x->array[2] != y->array[2]) | |
1649 | return 0; | |
1a0670f3 | 1650 | /* Fall through. */ |
0dfbf9d7 L |
1651 | case 2: |
1652 | if (x->array[1] != y->array[1]) | |
1653 | return 0; | |
1a0670f3 | 1654 | /* Fall through. */ |
0dfbf9d7 L |
1655 | case 1: |
1656 | return x->array[0] == y->array[0]; | |
1657 | break; | |
1658 | default: | |
1659 | abort (); | |
1660 | } | |
1661 | } | |
c6fb90c8 L |
1662 | |
1663 | static INLINE int | |
1664 | cpu_flags_check_cpu64 (i386_cpu_flags f) | |
1665 | { | |
1666 | return !((flag_code == CODE_64BIT && f.bitfield.cpuno64) | |
1667 | || (flag_code != CODE_64BIT && f.bitfield.cpu64)); | |
40fb9820 L |
1668 | } |
1669 | ||
c6fb90c8 L |
1670 | static INLINE i386_cpu_flags |
1671 | cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1672 | { |
c6fb90c8 L |
1673 | switch (ARRAY_SIZE (x.array)) |
1674 | { | |
53467f57 IT |
1675 | case 4: |
1676 | x.array [3] &= y.array [3]; | |
1677 | /* Fall through. */ | |
c6fb90c8 L |
1678 | case 3: |
1679 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1680 | /* Fall through. */ |
c6fb90c8 L |
1681 | case 2: |
1682 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1683 | /* Fall through. */ |
c6fb90c8 L |
1684 | case 1: |
1685 | x.array [0] &= y.array [0]; | |
1686 | break; | |
1687 | default: | |
1688 | abort (); | |
1689 | } | |
1690 | return x; | |
1691 | } | |
40fb9820 | 1692 | |
c6fb90c8 L |
1693 | static INLINE i386_cpu_flags |
1694 | cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1695 | { |
c6fb90c8 | 1696 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1697 | { |
53467f57 IT |
1698 | case 4: |
1699 | x.array [3] |= y.array [3]; | |
1700 | /* Fall through. */ | |
c6fb90c8 L |
1701 | case 3: |
1702 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1703 | /* Fall through. */ |
c6fb90c8 L |
1704 | case 2: |
1705 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1706 | /* Fall through. */ |
c6fb90c8 L |
1707 | case 1: |
1708 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1709 | break; |
1710 | default: | |
1711 | abort (); | |
1712 | } | |
40fb9820 L |
1713 | return x; |
1714 | } | |
1715 | ||
309d3373 JB |
1716 | static INLINE i386_cpu_flags |
1717 | cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y) | |
1718 | { | |
1719 | switch (ARRAY_SIZE (x.array)) | |
1720 | { | |
53467f57 IT |
1721 | case 4: |
1722 | x.array [3] &= ~y.array [3]; | |
1723 | /* Fall through. */ | |
309d3373 JB |
1724 | case 3: |
1725 | x.array [2] &= ~y.array [2]; | |
1a0670f3 | 1726 | /* Fall through. */ |
309d3373 JB |
1727 | case 2: |
1728 | x.array [1] &= ~y.array [1]; | |
1a0670f3 | 1729 | /* Fall through. */ |
309d3373 JB |
1730 | case 1: |
1731 | x.array [0] &= ~y.array [0]; | |
1732 | break; | |
1733 | default: | |
1734 | abort (); | |
1735 | } | |
1736 | return x; | |
1737 | } | |
1738 | ||
c0f3af97 L |
1739 | #define CPU_FLAGS_ARCH_MATCH 0x1 |
1740 | #define CPU_FLAGS_64BIT_MATCH 0x2 | |
1741 | ||
c0f3af97 | 1742 | #define CPU_FLAGS_PERFECT_MATCH \ |
db12e14e | 1743 | (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH) |
c0f3af97 L |
1744 | |
1745 | /* Return CPU flags match bits. */ | |
3629bb00 | 1746 | |
40fb9820 | 1747 | static int |
d3ce72d0 | 1748 | cpu_flags_match (const insn_template *t) |
40fb9820 | 1749 | { |
c0f3af97 L |
1750 | i386_cpu_flags x = t->cpu_flags; |
1751 | int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0; | |
40fb9820 L |
1752 | |
1753 | x.bitfield.cpu64 = 0; | |
1754 | x.bitfield.cpuno64 = 0; | |
1755 | ||
0dfbf9d7 | 1756 | if (cpu_flags_all_zero (&x)) |
c0f3af97 L |
1757 | { |
1758 | /* This instruction is available on all archs. */ | |
db12e14e | 1759 | match |= CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1760 | } |
3629bb00 L |
1761 | else |
1762 | { | |
c0f3af97 | 1763 | /* This instruction is available only on some archs. */ |
3629bb00 L |
1764 | i386_cpu_flags cpu = cpu_arch_flags; |
1765 | ||
ab592e75 JB |
1766 | /* AVX512VL is no standalone feature - match it and then strip it. */ |
1767 | if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl) | |
1768 | return match; | |
1769 | x.bitfield.cpuavx512vl = 0; | |
1770 | ||
3629bb00 | 1771 | cpu = cpu_flags_and (x, cpu); |
c0f3af97 L |
1772 | if (!cpu_flags_all_zero (&cpu)) |
1773 | { | |
a5ff0eb2 L |
1774 | if (x.bitfield.cpuavx) |
1775 | { | |
929f69fa | 1776 | /* We need to check a few extra flags with AVX. */ |
b9d49817 JB |
1777 | if (cpu.bitfield.cpuavx |
1778 | && (!t->opcode_modifier.sse2avx || sse2avx) | |
1779 | && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes) | |
929f69fa | 1780 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) |
b9d49817 JB |
1781 | && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul)) |
1782 | match |= CPU_FLAGS_ARCH_MATCH; | |
a5ff0eb2 | 1783 | } |
929f69fa JB |
1784 | else if (x.bitfield.cpuavx512f) |
1785 | { | |
1786 | /* We need to check a few extra flags with AVX512F. */ | |
1787 | if (cpu.bitfield.cpuavx512f | |
1788 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) | |
1789 | && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes) | |
1790 | && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq)) | |
1791 | match |= CPU_FLAGS_ARCH_MATCH; | |
1792 | } | |
a5ff0eb2 | 1793 | else |
db12e14e | 1794 | match |= CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1795 | } |
3629bb00 | 1796 | } |
c0f3af97 | 1797 | return match; |
40fb9820 L |
1798 | } |
1799 | ||
c6fb90c8 L |
1800 | static INLINE i386_operand_type |
1801 | operand_type_and (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1802 | { |
c6fb90c8 L |
1803 | switch (ARRAY_SIZE (x.array)) |
1804 | { | |
1805 | case 3: | |
1806 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1807 | /* Fall through. */ |
c6fb90c8 L |
1808 | case 2: |
1809 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1810 | /* Fall through. */ |
c6fb90c8 L |
1811 | case 1: |
1812 | x.array [0] &= y.array [0]; | |
1813 | break; | |
1814 | default: | |
1815 | abort (); | |
1816 | } | |
1817 | return x; | |
40fb9820 L |
1818 | } |
1819 | ||
73053c1f JB |
1820 | static INLINE i386_operand_type |
1821 | operand_type_and_not (i386_operand_type x, i386_operand_type y) | |
1822 | { | |
1823 | switch (ARRAY_SIZE (x.array)) | |
1824 | { | |
1825 | case 3: | |
1826 | x.array [2] &= ~y.array [2]; | |
1827 | /* Fall through. */ | |
1828 | case 2: | |
1829 | x.array [1] &= ~y.array [1]; | |
1830 | /* Fall through. */ | |
1831 | case 1: | |
1832 | x.array [0] &= ~y.array [0]; | |
1833 | break; | |
1834 | default: | |
1835 | abort (); | |
1836 | } | |
1837 | return x; | |
1838 | } | |
1839 | ||
c6fb90c8 L |
1840 | static INLINE i386_operand_type |
1841 | operand_type_or (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1842 | { |
c6fb90c8 | 1843 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1844 | { |
c6fb90c8 L |
1845 | case 3: |
1846 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1847 | /* Fall through. */ |
c6fb90c8 L |
1848 | case 2: |
1849 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1850 | /* Fall through. */ |
c6fb90c8 L |
1851 | case 1: |
1852 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1853 | break; |
1854 | default: | |
1855 | abort (); | |
1856 | } | |
c6fb90c8 L |
1857 | return x; |
1858 | } | |
40fb9820 | 1859 | |
c6fb90c8 L |
1860 | static INLINE i386_operand_type |
1861 | operand_type_xor (i386_operand_type x, i386_operand_type y) | |
1862 | { | |
1863 | switch (ARRAY_SIZE (x.array)) | |
1864 | { | |
1865 | case 3: | |
1866 | x.array [2] ^= y.array [2]; | |
1a0670f3 | 1867 | /* Fall through. */ |
c6fb90c8 L |
1868 | case 2: |
1869 | x.array [1] ^= y.array [1]; | |
1a0670f3 | 1870 | /* Fall through. */ |
c6fb90c8 L |
1871 | case 1: |
1872 | x.array [0] ^= y.array [0]; | |
1873 | break; | |
1874 | default: | |
1875 | abort (); | |
1876 | } | |
40fb9820 L |
1877 | return x; |
1878 | } | |
1879 | ||
1880 | static const i386_operand_type acc32 = OPERAND_TYPE_ACC32; | |
1881 | static const i386_operand_type acc64 = OPERAND_TYPE_ACC64; | |
40fb9820 L |
1882 | static const i386_operand_type disp16 = OPERAND_TYPE_DISP16; |
1883 | static const i386_operand_type disp32 = OPERAND_TYPE_DISP32; | |
1884 | static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S; | |
1885 | static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32; | |
1886 | static const i386_operand_type anydisp | |
1887 | = OPERAND_TYPE_ANYDISP; | |
40fb9820 | 1888 | static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM; |
43234a1e | 1889 | static const i386_operand_type regmask = OPERAND_TYPE_REGMASK; |
40fb9820 L |
1890 | static const i386_operand_type imm8 = OPERAND_TYPE_IMM8; |
1891 | static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S; | |
1892 | static const i386_operand_type imm16 = OPERAND_TYPE_IMM16; | |
1893 | static const i386_operand_type imm32 = OPERAND_TYPE_IMM32; | |
1894 | static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S; | |
1895 | static const i386_operand_type imm64 = OPERAND_TYPE_IMM64; | |
1896 | static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32; | |
1897 | static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S; | |
1898 | static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S; | |
a683cc34 | 1899 | static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4; |
40fb9820 L |
1900 | |
1901 | enum operand_type | |
1902 | { | |
1903 | reg, | |
40fb9820 L |
1904 | imm, |
1905 | disp, | |
1906 | anymem | |
1907 | }; | |
1908 | ||
c6fb90c8 | 1909 | static INLINE int |
40fb9820 L |
1910 | operand_type_check (i386_operand_type t, enum operand_type c) |
1911 | { | |
1912 | switch (c) | |
1913 | { | |
1914 | case reg: | |
dc821c5f | 1915 | return t.bitfield.reg; |
40fb9820 | 1916 | |
40fb9820 L |
1917 | case imm: |
1918 | return (t.bitfield.imm8 | |
1919 | || t.bitfield.imm8s | |
1920 | || t.bitfield.imm16 | |
1921 | || t.bitfield.imm32 | |
1922 | || t.bitfield.imm32s | |
1923 | || t.bitfield.imm64); | |
1924 | ||
1925 | case disp: | |
1926 | return (t.bitfield.disp8 | |
1927 | || t.bitfield.disp16 | |
1928 | || t.bitfield.disp32 | |
1929 | || t.bitfield.disp32s | |
1930 | || t.bitfield.disp64); | |
1931 | ||
1932 | case anymem: | |
1933 | return (t.bitfield.disp8 | |
1934 | || t.bitfield.disp16 | |
1935 | || t.bitfield.disp32 | |
1936 | || t.bitfield.disp32s | |
1937 | || t.bitfield.disp64 | |
1938 | || t.bitfield.baseindex); | |
1939 | ||
1940 | default: | |
1941 | abort (); | |
1942 | } | |
2cfe26b6 AM |
1943 | |
1944 | return 0; | |
40fb9820 L |
1945 | } |
1946 | ||
7a54636a L |
1947 | /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size |
1948 | between operand GIVEN and opeand WANTED for instruction template T. */ | |
5c07affc L |
1949 | |
1950 | static INLINE int | |
7a54636a L |
1951 | match_operand_size (const insn_template *t, unsigned int wanted, |
1952 | unsigned int given) | |
5c07affc | 1953 | { |
3ac21baa JB |
1954 | return !((i.types[given].bitfield.byte |
1955 | && !t->operand_types[wanted].bitfield.byte) | |
1956 | || (i.types[given].bitfield.word | |
1957 | && !t->operand_types[wanted].bitfield.word) | |
1958 | || (i.types[given].bitfield.dword | |
1959 | && !t->operand_types[wanted].bitfield.dword) | |
1960 | || (i.types[given].bitfield.qword | |
1961 | && !t->operand_types[wanted].bitfield.qword) | |
1962 | || (i.types[given].bitfield.tbyte | |
1963 | && !t->operand_types[wanted].bitfield.tbyte)); | |
5c07affc L |
1964 | } |
1965 | ||
dd40ce22 L |
1966 | /* Return 1 if there is no conflict in SIMD register between operand |
1967 | GIVEN and opeand WANTED for instruction template T. */ | |
1b54b8d7 JB |
1968 | |
1969 | static INLINE int | |
dd40ce22 L |
1970 | match_simd_size (const insn_template *t, unsigned int wanted, |
1971 | unsigned int given) | |
1b54b8d7 | 1972 | { |
3ac21baa JB |
1973 | return !((i.types[given].bitfield.xmmword |
1974 | && !t->operand_types[wanted].bitfield.xmmword) | |
1975 | || (i.types[given].bitfield.ymmword | |
1976 | && !t->operand_types[wanted].bitfield.ymmword) | |
1977 | || (i.types[given].bitfield.zmmword | |
1978 | && !t->operand_types[wanted].bitfield.zmmword)); | |
1b54b8d7 JB |
1979 | } |
1980 | ||
7a54636a L |
1981 | /* Return 1 if there is no conflict in any size between operand GIVEN |
1982 | and opeand WANTED for instruction template T. */ | |
5c07affc L |
1983 | |
1984 | static INLINE int | |
dd40ce22 L |
1985 | match_mem_size (const insn_template *t, unsigned int wanted, |
1986 | unsigned int given) | |
5c07affc | 1987 | { |
7a54636a | 1988 | return (match_operand_size (t, wanted, given) |
3ac21baa | 1989 | && !((i.types[given].bitfield.unspecified |
af508cb9 | 1990 | && !i.broadcast |
3ac21baa JB |
1991 | && !t->operand_types[wanted].bitfield.unspecified) |
1992 | || (i.types[given].bitfield.fword | |
1993 | && !t->operand_types[wanted].bitfield.fword) | |
1b54b8d7 JB |
1994 | /* For scalar opcode templates to allow register and memory |
1995 | operands at the same time, some special casing is needed | |
d6793fa1 JB |
1996 | here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and |
1997 | down-conversion vpmov*. */ | |
3ac21baa | 1998 | || ((t->operand_types[wanted].bitfield.regsimd |
1b54b8d7 | 1999 | && !t->opcode_modifier.broadcast |
3ac21baa JB |
2000 | && (t->operand_types[wanted].bitfield.byte |
2001 | || t->operand_types[wanted].bitfield.word | |
2002 | || t->operand_types[wanted].bitfield.dword | |
2003 | || t->operand_types[wanted].bitfield.qword)) | |
2004 | ? (i.types[given].bitfield.xmmword | |
2005 | || i.types[given].bitfield.ymmword | |
2006 | || i.types[given].bitfield.zmmword) | |
2007 | : !match_simd_size(t, wanted, given)))); | |
5c07affc L |
2008 | } |
2009 | ||
3ac21baa JB |
2010 | /* Return value has MATCH_STRAIGHT set if there is no size conflict on any |
2011 | operands for instruction template T, and it has MATCH_REVERSE set if there | |
2012 | is no size conflict on any operands for the template with operands reversed | |
2013 | (and the template allows for reversing in the first place). */ | |
5c07affc | 2014 | |
3ac21baa JB |
2015 | #define MATCH_STRAIGHT 1 |
2016 | #define MATCH_REVERSE 2 | |
2017 | ||
2018 | static INLINE unsigned int | |
d3ce72d0 | 2019 | operand_size_match (const insn_template *t) |
5c07affc | 2020 | { |
3ac21baa | 2021 | unsigned int j, match = MATCH_STRAIGHT; |
5c07affc L |
2022 | |
2023 | /* Don't check jump instructions. */ | |
2024 | if (t->opcode_modifier.jump | |
2025 | || t->opcode_modifier.jumpbyte | |
2026 | || t->opcode_modifier.jumpdword | |
2027 | || t->opcode_modifier.jumpintersegment) | |
2028 | return match; | |
2029 | ||
2030 | /* Check memory and accumulator operand size. */ | |
2031 | for (j = 0; j < i.operands; j++) | |
2032 | { | |
1b54b8d7 JB |
2033 | if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd |
2034 | && t->operand_types[j].bitfield.anysize) | |
5c07affc L |
2035 | continue; |
2036 | ||
1b54b8d7 | 2037 | if (t->operand_types[j].bitfield.reg |
7a54636a | 2038 | && !match_operand_size (t, j, j)) |
5c07affc L |
2039 | { |
2040 | match = 0; | |
2041 | break; | |
2042 | } | |
2043 | ||
1b54b8d7 | 2044 | if (t->operand_types[j].bitfield.regsimd |
3ac21baa | 2045 | && !match_simd_size (t, j, j)) |
1b54b8d7 JB |
2046 | { |
2047 | match = 0; | |
2048 | break; | |
2049 | } | |
2050 | ||
2051 | if (t->operand_types[j].bitfield.acc | |
7a54636a | 2052 | && (!match_operand_size (t, j, j) || !match_simd_size (t, j, j))) |
1b54b8d7 JB |
2053 | { |
2054 | match = 0; | |
2055 | break; | |
2056 | } | |
2057 | ||
c48dadc9 | 2058 | if ((i.flags[j] & Operand_Mem) && !match_mem_size (t, j, j)) |
5c07affc L |
2059 | { |
2060 | match = 0; | |
2061 | break; | |
2062 | } | |
2063 | } | |
2064 | ||
3ac21baa | 2065 | if (!t->opcode_modifier.d) |
891edac4 L |
2066 | { |
2067 | mismatch: | |
3ac21baa JB |
2068 | if (!match) |
2069 | i.error = operand_size_mismatch; | |
2070 | return match; | |
891edac4 | 2071 | } |
5c07affc L |
2072 | |
2073 | /* Check reverse. */ | |
f5eb1d70 | 2074 | gas_assert (i.operands >= 2 && i.operands <= 3); |
5c07affc | 2075 | |
f5eb1d70 | 2076 | for (j = 0; j < i.operands; j++) |
5c07affc | 2077 | { |
f5eb1d70 JB |
2078 | unsigned int given = i.operands - j - 1; |
2079 | ||
dbbc8b7e | 2080 | if (t->operand_types[j].bitfield.reg |
f5eb1d70 | 2081 | && !match_operand_size (t, j, given)) |
891edac4 | 2082 | goto mismatch; |
5c07affc | 2083 | |
dbbc8b7e | 2084 | if (t->operand_types[j].bitfield.regsimd |
f5eb1d70 | 2085 | && !match_simd_size (t, j, given)) |
dbbc8b7e JB |
2086 | goto mismatch; |
2087 | ||
2088 | if (t->operand_types[j].bitfield.acc | |
f5eb1d70 JB |
2089 | && (!match_operand_size (t, j, given) |
2090 | || !match_simd_size (t, j, given))) | |
dbbc8b7e JB |
2091 | goto mismatch; |
2092 | ||
f5eb1d70 | 2093 | if ((i.flags[given] & Operand_Mem) && !match_mem_size (t, j, given)) |
891edac4 | 2094 | goto mismatch; |
5c07affc L |
2095 | } |
2096 | ||
3ac21baa | 2097 | return match | MATCH_REVERSE; |
5c07affc L |
2098 | } |
2099 | ||
c6fb90c8 | 2100 | static INLINE int |
40fb9820 L |
2101 | operand_type_match (i386_operand_type overlap, |
2102 | i386_operand_type given) | |
2103 | { | |
2104 | i386_operand_type temp = overlap; | |
2105 | ||
2106 | temp.bitfield.jumpabsolute = 0; | |
7d5e4556 | 2107 | temp.bitfield.unspecified = 0; |
5c07affc L |
2108 | temp.bitfield.byte = 0; |
2109 | temp.bitfield.word = 0; | |
2110 | temp.bitfield.dword = 0; | |
2111 | temp.bitfield.fword = 0; | |
2112 | temp.bitfield.qword = 0; | |
2113 | temp.bitfield.tbyte = 0; | |
2114 | temp.bitfield.xmmword = 0; | |
c0f3af97 | 2115 | temp.bitfield.ymmword = 0; |
43234a1e | 2116 | temp.bitfield.zmmword = 0; |
0dfbf9d7 | 2117 | if (operand_type_all_zero (&temp)) |
891edac4 | 2118 | goto mismatch; |
40fb9820 | 2119 | |
891edac4 L |
2120 | if (given.bitfield.baseindex == overlap.bitfield.baseindex |
2121 | && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute) | |
2122 | return 1; | |
2123 | ||
2124 | mismatch: | |
a65babc9 | 2125 | i.error = operand_type_mismatch; |
891edac4 | 2126 | return 0; |
40fb9820 L |
2127 | } |
2128 | ||
7d5e4556 | 2129 | /* If given types g0 and g1 are registers they must be of the same type |
10c17abd JB |
2130 | unless the expected operand type register overlap is null. |
2131 | Memory operand size of certain SIMD instructions is also being checked | |
2132 | here. */ | |
40fb9820 | 2133 | |
c6fb90c8 | 2134 | static INLINE int |
dc821c5f | 2135 | operand_type_register_match (i386_operand_type g0, |
40fb9820 | 2136 | i386_operand_type t0, |
40fb9820 L |
2137 | i386_operand_type g1, |
2138 | i386_operand_type t1) | |
2139 | { | |
10c17abd JB |
2140 | if (!g0.bitfield.reg |
2141 | && !g0.bitfield.regsimd | |
2142 | && (!operand_type_check (g0, anymem) | |
2143 | || g0.bitfield.unspecified | |
2144 | || !t0.bitfield.regsimd)) | |
40fb9820 L |
2145 | return 1; |
2146 | ||
10c17abd JB |
2147 | if (!g1.bitfield.reg |
2148 | && !g1.bitfield.regsimd | |
2149 | && (!operand_type_check (g1, anymem) | |
2150 | || g1.bitfield.unspecified | |
2151 | || !t1.bitfield.regsimd)) | |
40fb9820 L |
2152 | return 1; |
2153 | ||
dc821c5f JB |
2154 | if (g0.bitfield.byte == g1.bitfield.byte |
2155 | && g0.bitfield.word == g1.bitfield.word | |
2156 | && g0.bitfield.dword == g1.bitfield.dword | |
10c17abd JB |
2157 | && g0.bitfield.qword == g1.bitfield.qword |
2158 | && g0.bitfield.xmmword == g1.bitfield.xmmword | |
2159 | && g0.bitfield.ymmword == g1.bitfield.ymmword | |
2160 | && g0.bitfield.zmmword == g1.bitfield.zmmword) | |
40fb9820 L |
2161 | return 1; |
2162 | ||
dc821c5f JB |
2163 | if (!(t0.bitfield.byte & t1.bitfield.byte) |
2164 | && !(t0.bitfield.word & t1.bitfield.word) | |
2165 | && !(t0.bitfield.dword & t1.bitfield.dword) | |
10c17abd JB |
2166 | && !(t0.bitfield.qword & t1.bitfield.qword) |
2167 | && !(t0.bitfield.xmmword & t1.bitfield.xmmword) | |
2168 | && !(t0.bitfield.ymmword & t1.bitfield.ymmword) | |
2169 | && !(t0.bitfield.zmmword & t1.bitfield.zmmword)) | |
891edac4 L |
2170 | return 1; |
2171 | ||
a65babc9 | 2172 | i.error = register_type_mismatch; |
891edac4 L |
2173 | |
2174 | return 0; | |
40fb9820 L |
2175 | } |
2176 | ||
4c692bc7 JB |
2177 | static INLINE unsigned int |
2178 | register_number (const reg_entry *r) | |
2179 | { | |
2180 | unsigned int nr = r->reg_num; | |
2181 | ||
2182 | if (r->reg_flags & RegRex) | |
2183 | nr += 8; | |
2184 | ||
200cbe0f L |
2185 | if (r->reg_flags & RegVRex) |
2186 | nr += 16; | |
2187 | ||
4c692bc7 JB |
2188 | return nr; |
2189 | } | |
2190 | ||
252b5132 | 2191 | static INLINE unsigned int |
40fb9820 | 2192 | mode_from_disp_size (i386_operand_type t) |
252b5132 | 2193 | { |
b5014f7a | 2194 | if (t.bitfield.disp8) |
40fb9820 L |
2195 | return 1; |
2196 | else if (t.bitfield.disp16 | |
2197 | || t.bitfield.disp32 | |
2198 | || t.bitfield.disp32s) | |
2199 | return 2; | |
2200 | else | |
2201 | return 0; | |
252b5132 RH |
2202 | } |
2203 | ||
2204 | static INLINE int | |
65879393 | 2205 | fits_in_signed_byte (addressT num) |
252b5132 | 2206 | { |
65879393 | 2207 | return num + 0x80 <= 0xff; |
47926f60 | 2208 | } |
252b5132 RH |
2209 | |
2210 | static INLINE int | |
65879393 | 2211 | fits_in_unsigned_byte (addressT num) |
252b5132 | 2212 | { |
65879393 | 2213 | return num <= 0xff; |
47926f60 | 2214 | } |
252b5132 RH |
2215 | |
2216 | static INLINE int | |
65879393 | 2217 | fits_in_unsigned_word (addressT num) |
252b5132 | 2218 | { |
65879393 | 2219 | return num <= 0xffff; |
47926f60 | 2220 | } |
252b5132 RH |
2221 | |
2222 | static INLINE int | |
65879393 | 2223 | fits_in_signed_word (addressT num) |
252b5132 | 2224 | { |
65879393 | 2225 | return num + 0x8000 <= 0xffff; |
47926f60 | 2226 | } |
2a962e6d | 2227 | |
3e73aa7c | 2228 | static INLINE int |
65879393 | 2229 | fits_in_signed_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2230 | { |
2231 | #ifndef BFD64 | |
2232 | return 1; | |
2233 | #else | |
65879393 | 2234 | return num + 0x80000000 <= 0xffffffff; |
3e73aa7c JH |
2235 | #endif |
2236 | } /* fits_in_signed_long() */ | |
2a962e6d | 2237 | |
3e73aa7c | 2238 | static INLINE int |
65879393 | 2239 | fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2240 | { |
2241 | #ifndef BFD64 | |
2242 | return 1; | |
2243 | #else | |
65879393 | 2244 | return num <= 0xffffffff; |
3e73aa7c JH |
2245 | #endif |
2246 | } /* fits_in_unsigned_long() */ | |
252b5132 | 2247 | |
43234a1e | 2248 | static INLINE int |
b5014f7a | 2249 | fits_in_disp8 (offsetT num) |
43234a1e L |
2250 | { |
2251 | int shift = i.memshift; | |
2252 | unsigned int mask; | |
2253 | ||
2254 | if (shift == -1) | |
2255 | abort (); | |
2256 | ||
2257 | mask = (1 << shift) - 1; | |
2258 | ||
2259 | /* Return 0 if NUM isn't properly aligned. */ | |
2260 | if ((num & mask)) | |
2261 | return 0; | |
2262 | ||
2263 | /* Check if NUM will fit in 8bit after shift. */ | |
2264 | return fits_in_signed_byte (num >> shift); | |
2265 | } | |
2266 | ||
a683cc34 SP |
2267 | static INLINE int |
2268 | fits_in_imm4 (offsetT num) | |
2269 | { | |
2270 | return (num & 0xf) == num; | |
2271 | } | |
2272 | ||
40fb9820 | 2273 | static i386_operand_type |
e3bb37b5 | 2274 | smallest_imm_type (offsetT num) |
252b5132 | 2275 | { |
40fb9820 | 2276 | i386_operand_type t; |
7ab9ffdd | 2277 | |
0dfbf9d7 | 2278 | operand_type_set (&t, 0); |
40fb9820 L |
2279 | t.bitfield.imm64 = 1; |
2280 | ||
2281 | if (cpu_arch_tune != PROCESSOR_I486 && num == 1) | |
e413e4e9 AM |
2282 | { |
2283 | /* This code is disabled on the 486 because all the Imm1 forms | |
2284 | in the opcode table are slower on the i486. They're the | |
2285 | versions with the implicitly specified single-position | |
2286 | displacement, which has another syntax if you really want to | |
2287 | use that form. */ | |
40fb9820 L |
2288 | t.bitfield.imm1 = 1; |
2289 | t.bitfield.imm8 = 1; | |
2290 | t.bitfield.imm8s = 1; | |
2291 | t.bitfield.imm16 = 1; | |
2292 | t.bitfield.imm32 = 1; | |
2293 | t.bitfield.imm32s = 1; | |
2294 | } | |
2295 | else if (fits_in_signed_byte (num)) | |
2296 | { | |
2297 | t.bitfield.imm8 = 1; | |
2298 | t.bitfield.imm8s = 1; | |
2299 | t.bitfield.imm16 = 1; | |
2300 | t.bitfield.imm32 = 1; | |
2301 | t.bitfield.imm32s = 1; | |
2302 | } | |
2303 | else if (fits_in_unsigned_byte (num)) | |
2304 | { | |
2305 | t.bitfield.imm8 = 1; | |
2306 | t.bitfield.imm16 = 1; | |
2307 | t.bitfield.imm32 = 1; | |
2308 | t.bitfield.imm32s = 1; | |
2309 | } | |
2310 | else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
2311 | { | |
2312 | t.bitfield.imm16 = 1; | |
2313 | t.bitfield.imm32 = 1; | |
2314 | t.bitfield.imm32s = 1; | |
2315 | } | |
2316 | else if (fits_in_signed_long (num)) | |
2317 | { | |
2318 | t.bitfield.imm32 = 1; | |
2319 | t.bitfield.imm32s = 1; | |
2320 | } | |
2321 | else if (fits_in_unsigned_long (num)) | |
2322 | t.bitfield.imm32 = 1; | |
2323 | ||
2324 | return t; | |
47926f60 | 2325 | } |
252b5132 | 2326 | |
847f7ad4 | 2327 | static offsetT |
e3bb37b5 | 2328 | offset_in_range (offsetT val, int size) |
847f7ad4 | 2329 | { |
508866be | 2330 | addressT mask; |
ba2adb93 | 2331 | |
847f7ad4 AM |
2332 | switch (size) |
2333 | { | |
508866be L |
2334 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
2335 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 2336 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
3e73aa7c JH |
2337 | #ifdef BFD64 |
2338 | case 8: mask = ((addressT) 2 << 63) - 1; break; | |
2339 | #endif | |
47926f60 | 2340 | default: abort (); |
847f7ad4 AM |
2341 | } |
2342 | ||
9de868bf L |
2343 | #ifdef BFD64 |
2344 | /* If BFD64, sign extend val for 32bit address mode. */ | |
2345 | if (flag_code != CODE_64BIT | |
2346 | || i.prefix[ADDR_PREFIX]) | |
3e73aa7c JH |
2347 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) |
2348 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
fa289fb8 | 2349 | #endif |
ba2adb93 | 2350 | |
47926f60 | 2351 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
847f7ad4 AM |
2352 | { |
2353 | char buf1[40], buf2[40]; | |
2354 | ||
2355 | sprint_value (buf1, val); | |
2356 | sprint_value (buf2, val & mask); | |
2357 | as_warn (_("%s shortened to %s"), buf1, buf2); | |
2358 | } | |
2359 | return val & mask; | |
2360 | } | |
2361 | ||
c32fa91d L |
2362 | enum PREFIX_GROUP |
2363 | { | |
2364 | PREFIX_EXIST = 0, | |
2365 | PREFIX_LOCK, | |
2366 | PREFIX_REP, | |
04ef582a | 2367 | PREFIX_DS, |
c32fa91d L |
2368 | PREFIX_OTHER |
2369 | }; | |
2370 | ||
2371 | /* Returns | |
2372 | a. PREFIX_EXIST if attempting to add a prefix where one from the | |
2373 | same class already exists. | |
2374 | b. PREFIX_LOCK if lock prefix is added. | |
2375 | c. PREFIX_REP if rep/repne prefix is added. | |
04ef582a L |
2376 | d. PREFIX_DS if ds prefix is added. |
2377 | e. PREFIX_OTHER if other prefix is added. | |
c32fa91d L |
2378 | */ |
2379 | ||
2380 | static enum PREFIX_GROUP | |
e3bb37b5 | 2381 | add_prefix (unsigned int prefix) |
252b5132 | 2382 | { |
c32fa91d | 2383 | enum PREFIX_GROUP ret = PREFIX_OTHER; |
b1905489 | 2384 | unsigned int q; |
252b5132 | 2385 | |
29b0f896 AM |
2386 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
2387 | && flag_code == CODE_64BIT) | |
b1905489 | 2388 | { |
161a04f6 | 2389 | if ((i.prefix[REX_PREFIX] & prefix & REX_W) |
44846f29 JB |
2390 | || (i.prefix[REX_PREFIX] & prefix & REX_R) |
2391 | || (i.prefix[REX_PREFIX] & prefix & REX_X) | |
2392 | || (i.prefix[REX_PREFIX] & prefix & REX_B)) | |
c32fa91d | 2393 | ret = PREFIX_EXIST; |
b1905489 JB |
2394 | q = REX_PREFIX; |
2395 | } | |
3e73aa7c | 2396 | else |
b1905489 JB |
2397 | { |
2398 | switch (prefix) | |
2399 | { | |
2400 | default: | |
2401 | abort (); | |
2402 | ||
b1905489 | 2403 | case DS_PREFIX_OPCODE: |
04ef582a L |
2404 | ret = PREFIX_DS; |
2405 | /* Fall through. */ | |
2406 | case CS_PREFIX_OPCODE: | |
b1905489 JB |
2407 | case ES_PREFIX_OPCODE: |
2408 | case FS_PREFIX_OPCODE: | |
2409 | case GS_PREFIX_OPCODE: | |
2410 | case SS_PREFIX_OPCODE: | |
2411 | q = SEG_PREFIX; | |
2412 | break; | |
2413 | ||
2414 | case REPNE_PREFIX_OPCODE: | |
2415 | case REPE_PREFIX_OPCODE: | |
c32fa91d L |
2416 | q = REP_PREFIX; |
2417 | ret = PREFIX_REP; | |
2418 | break; | |
2419 | ||
b1905489 | 2420 | case LOCK_PREFIX_OPCODE: |
c32fa91d L |
2421 | q = LOCK_PREFIX; |
2422 | ret = PREFIX_LOCK; | |
b1905489 JB |
2423 | break; |
2424 | ||
2425 | case FWAIT_OPCODE: | |
2426 | q = WAIT_PREFIX; | |
2427 | break; | |
2428 | ||
2429 | case ADDR_PREFIX_OPCODE: | |
2430 | q = ADDR_PREFIX; | |
2431 | break; | |
2432 | ||
2433 | case DATA_PREFIX_OPCODE: | |
2434 | q = DATA_PREFIX; | |
2435 | break; | |
2436 | } | |
2437 | if (i.prefix[q] != 0) | |
c32fa91d | 2438 | ret = PREFIX_EXIST; |
b1905489 | 2439 | } |
252b5132 | 2440 | |
b1905489 | 2441 | if (ret) |
252b5132 | 2442 | { |
b1905489 JB |
2443 | if (!i.prefix[q]) |
2444 | ++i.prefixes; | |
2445 | i.prefix[q] |= prefix; | |
252b5132 | 2446 | } |
b1905489 JB |
2447 | else |
2448 | as_bad (_("same type of prefix used twice")); | |
252b5132 | 2449 | |
252b5132 RH |
2450 | return ret; |
2451 | } | |
2452 | ||
2453 | static void | |
78f12dd3 | 2454 | update_code_flag (int value, int check) |
eecb386c | 2455 | { |
78f12dd3 L |
2456 | PRINTF_LIKE ((*as_error)); |
2457 | ||
1e9cc1c2 | 2458 | flag_code = (enum flag_code) value; |
40fb9820 L |
2459 | if (flag_code == CODE_64BIT) |
2460 | { | |
2461 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2462 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
40fb9820 L |
2463 | } |
2464 | else | |
2465 | { | |
2466 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2467 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
40fb9820 L |
2468 | } |
2469 | if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm ) | |
3e73aa7c | 2470 | { |
78f12dd3 L |
2471 | if (check) |
2472 | as_error = as_fatal; | |
2473 | else | |
2474 | as_error = as_bad; | |
2475 | (*as_error) (_("64bit mode not supported on `%s'."), | |
2476 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2477 | } |
40fb9820 | 2478 | if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) |
3e73aa7c | 2479 | { |
78f12dd3 L |
2480 | if (check) |
2481 | as_error = as_fatal; | |
2482 | else | |
2483 | as_error = as_bad; | |
2484 | (*as_error) (_("32bit mode not supported on `%s'."), | |
2485 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2486 | } |
eecb386c AM |
2487 | stackop_size = '\0'; |
2488 | } | |
2489 | ||
78f12dd3 L |
2490 | static void |
2491 | set_code_flag (int value) | |
2492 | { | |
2493 | update_code_flag (value, 0); | |
2494 | } | |
2495 | ||
eecb386c | 2496 | static void |
e3bb37b5 | 2497 | set_16bit_gcc_code_flag (int new_code_flag) |
252b5132 | 2498 | { |
1e9cc1c2 | 2499 | flag_code = (enum flag_code) new_code_flag; |
40fb9820 L |
2500 | if (flag_code != CODE_16BIT) |
2501 | abort (); | |
2502 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2503 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
9306ca4a | 2504 | stackop_size = LONG_MNEM_SUFFIX; |
252b5132 RH |
2505 | } |
2506 | ||
2507 | static void | |
e3bb37b5 | 2508 | set_intel_syntax (int syntax_flag) |
252b5132 RH |
2509 | { |
2510 | /* Find out if register prefixing is specified. */ | |
2511 | int ask_naked_reg = 0; | |
2512 | ||
2513 | SKIP_WHITESPACE (); | |
29b0f896 | 2514 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
252b5132 | 2515 | { |
d02603dc NC |
2516 | char *string; |
2517 | int e = get_symbol_name (&string); | |
252b5132 | 2518 | |
47926f60 | 2519 | if (strcmp (string, "prefix") == 0) |
252b5132 | 2520 | ask_naked_reg = 1; |
47926f60 | 2521 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
2522 | ask_naked_reg = -1; |
2523 | else | |
d0b47220 | 2524 | as_bad (_("bad argument to syntax directive.")); |
d02603dc | 2525 | (void) restore_line_pointer (e); |
252b5132 RH |
2526 | } |
2527 | demand_empty_rest_of_line (); | |
c3332e24 | 2528 | |
252b5132 RH |
2529 | intel_syntax = syntax_flag; |
2530 | ||
2531 | if (ask_naked_reg == 0) | |
f86103b7 AM |
2532 | allow_naked_reg = (intel_syntax |
2533 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); | |
252b5132 RH |
2534 | else |
2535 | allow_naked_reg = (ask_naked_reg < 0); | |
9306ca4a | 2536 | |
ee86248c | 2537 | expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0); |
7ab9ffdd | 2538 | |
e4a3b5a4 | 2539 | identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; |
9306ca4a | 2540 | identifier_chars['$'] = intel_syntax ? '$' : 0; |
e4a3b5a4 | 2541 | register_prefix = allow_naked_reg ? "" : "%"; |
252b5132 RH |
2542 | } |
2543 | ||
1efbbeb4 L |
2544 | static void |
2545 | set_intel_mnemonic (int mnemonic_flag) | |
2546 | { | |
e1d4d893 | 2547 | intel_mnemonic = mnemonic_flag; |
1efbbeb4 L |
2548 | } |
2549 | ||
db51cc60 L |
2550 | static void |
2551 | set_allow_index_reg (int flag) | |
2552 | { | |
2553 | allow_index_reg = flag; | |
2554 | } | |
2555 | ||
cb19c032 | 2556 | static void |
7bab8ab5 | 2557 | set_check (int what) |
cb19c032 | 2558 | { |
7bab8ab5 JB |
2559 | enum check_kind *kind; |
2560 | const char *str; | |
2561 | ||
2562 | if (what) | |
2563 | { | |
2564 | kind = &operand_check; | |
2565 | str = "operand"; | |
2566 | } | |
2567 | else | |
2568 | { | |
2569 | kind = &sse_check; | |
2570 | str = "sse"; | |
2571 | } | |
2572 | ||
cb19c032 L |
2573 | SKIP_WHITESPACE (); |
2574 | ||
2575 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
2576 | { | |
d02603dc NC |
2577 | char *string; |
2578 | int e = get_symbol_name (&string); | |
cb19c032 L |
2579 | |
2580 | if (strcmp (string, "none") == 0) | |
7bab8ab5 | 2581 | *kind = check_none; |
cb19c032 | 2582 | else if (strcmp (string, "warning") == 0) |
7bab8ab5 | 2583 | *kind = check_warning; |
cb19c032 | 2584 | else if (strcmp (string, "error") == 0) |
7bab8ab5 | 2585 | *kind = check_error; |
cb19c032 | 2586 | else |
7bab8ab5 | 2587 | as_bad (_("bad argument to %s_check directive."), str); |
d02603dc | 2588 | (void) restore_line_pointer (e); |
cb19c032 L |
2589 | } |
2590 | else | |
7bab8ab5 | 2591 | as_bad (_("missing argument for %s_check directive"), str); |
cb19c032 L |
2592 | |
2593 | demand_empty_rest_of_line (); | |
2594 | } | |
2595 | ||
8a9036a4 L |
2596 | static void |
2597 | check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED, | |
1e9cc1c2 | 2598 | i386_cpu_flags new_flag ATTRIBUTE_UNUSED) |
8a9036a4 L |
2599 | { |
2600 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2601 | static const char *arch; | |
2602 | ||
2603 | /* Intel LIOM is only supported on ELF. */ | |
2604 | if (!IS_ELF) | |
2605 | return; | |
2606 | ||
2607 | if (!arch) | |
2608 | { | |
2609 | /* Use cpu_arch_name if it is set in md_parse_option. Otherwise | |
2610 | use default_arch. */ | |
2611 | arch = cpu_arch_name; | |
2612 | if (!arch) | |
2613 | arch = default_arch; | |
2614 | } | |
2615 | ||
81486035 L |
2616 | /* If we are targeting Intel MCU, we must enable it. */ |
2617 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU | |
2618 | || new_flag.bitfield.cpuiamcu) | |
2619 | return; | |
2620 | ||
3632d14b | 2621 | /* If we are targeting Intel L1OM, we must enable it. */ |
8a9036a4 | 2622 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM |
1e9cc1c2 | 2623 | || new_flag.bitfield.cpul1om) |
8a9036a4 | 2624 | return; |
76ba9986 | 2625 | |
7a9068fe L |
2626 | /* If we are targeting Intel K1OM, we must enable it. */ |
2627 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM | |
2628 | || new_flag.bitfield.cpuk1om) | |
2629 | return; | |
2630 | ||
8a9036a4 L |
2631 | as_bad (_("`%s' is not supported on `%s'"), name, arch); |
2632 | #endif | |
2633 | } | |
2634 | ||
e413e4e9 | 2635 | static void |
e3bb37b5 | 2636 | set_cpu_arch (int dummy ATTRIBUTE_UNUSED) |
e413e4e9 | 2637 | { |
47926f60 | 2638 | SKIP_WHITESPACE (); |
e413e4e9 | 2639 | |
29b0f896 | 2640 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
e413e4e9 | 2641 | { |
d02603dc NC |
2642 | char *string; |
2643 | int e = get_symbol_name (&string); | |
91d6fa6a | 2644 | unsigned int j; |
40fb9820 | 2645 | i386_cpu_flags flags; |
e413e4e9 | 2646 | |
91d6fa6a | 2647 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
e413e4e9 | 2648 | { |
91d6fa6a | 2649 | if (strcmp (string, cpu_arch[j].name) == 0) |
e413e4e9 | 2650 | { |
91d6fa6a | 2651 | check_cpu_arch_compatible (string, cpu_arch[j].flags); |
8a9036a4 | 2652 | |
5c6af06e JB |
2653 | if (*string != '.') |
2654 | { | |
91d6fa6a | 2655 | cpu_arch_name = cpu_arch[j].name; |
5c6af06e | 2656 | cpu_sub_arch_name = NULL; |
91d6fa6a | 2657 | cpu_arch_flags = cpu_arch[j].flags; |
40fb9820 L |
2658 | if (flag_code == CODE_64BIT) |
2659 | { | |
2660 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2661 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
2662 | } | |
2663 | else | |
2664 | { | |
2665 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2666 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
2667 | } | |
91d6fa6a NC |
2668 | cpu_arch_isa = cpu_arch[j].type; |
2669 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
ccc9c027 L |
2670 | if (!cpu_arch_tune_set) |
2671 | { | |
2672 | cpu_arch_tune = cpu_arch_isa; | |
2673 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
2674 | } | |
5c6af06e JB |
2675 | break; |
2676 | } | |
40fb9820 | 2677 | |
293f5f65 L |
2678 | flags = cpu_flags_or (cpu_arch_flags, |
2679 | cpu_arch[j].flags); | |
81486035 | 2680 | |
5b64d091 | 2681 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
5c6af06e | 2682 | { |
6305a203 L |
2683 | if (cpu_sub_arch_name) |
2684 | { | |
2685 | char *name = cpu_sub_arch_name; | |
2686 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 2687 | cpu_arch[j].name, |
1bf57e9f | 2688 | (const char *) NULL); |
6305a203 L |
2689 | free (name); |
2690 | } | |
2691 | else | |
91d6fa6a | 2692 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
40fb9820 | 2693 | cpu_arch_flags = flags; |
a586129e | 2694 | cpu_arch_isa_flags = flags; |
5c6af06e | 2695 | } |
0089dace L |
2696 | else |
2697 | cpu_arch_isa_flags | |
2698 | = cpu_flags_or (cpu_arch_isa_flags, | |
2699 | cpu_arch[j].flags); | |
d02603dc | 2700 | (void) restore_line_pointer (e); |
5c6af06e JB |
2701 | demand_empty_rest_of_line (); |
2702 | return; | |
e413e4e9 AM |
2703 | } |
2704 | } | |
293f5f65 L |
2705 | |
2706 | if (*string == '.' && j >= ARRAY_SIZE (cpu_arch)) | |
2707 | { | |
33eaf5de | 2708 | /* Disable an ISA extension. */ |
293f5f65 L |
2709 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
2710 | if (strcmp (string + 1, cpu_noarch [j].name) == 0) | |
2711 | { | |
2712 | flags = cpu_flags_and_not (cpu_arch_flags, | |
2713 | cpu_noarch[j].flags); | |
2714 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
2715 | { | |
2716 | if (cpu_sub_arch_name) | |
2717 | { | |
2718 | char *name = cpu_sub_arch_name; | |
2719 | cpu_sub_arch_name = concat (name, string, | |
2720 | (const char *) NULL); | |
2721 | free (name); | |
2722 | } | |
2723 | else | |
2724 | cpu_sub_arch_name = xstrdup (string); | |
2725 | cpu_arch_flags = flags; | |
2726 | cpu_arch_isa_flags = flags; | |
2727 | } | |
2728 | (void) restore_line_pointer (e); | |
2729 | demand_empty_rest_of_line (); | |
2730 | return; | |
2731 | } | |
2732 | ||
2733 | j = ARRAY_SIZE (cpu_arch); | |
2734 | } | |
2735 | ||
91d6fa6a | 2736 | if (j >= ARRAY_SIZE (cpu_arch)) |
e413e4e9 AM |
2737 | as_bad (_("no such architecture: `%s'"), string); |
2738 | ||
2739 | *input_line_pointer = e; | |
2740 | } | |
2741 | else | |
2742 | as_bad (_("missing cpu architecture")); | |
2743 | ||
fddf5b5b AM |
2744 | no_cond_jump_promotion = 0; |
2745 | if (*input_line_pointer == ',' | |
29b0f896 | 2746 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
fddf5b5b | 2747 | { |
d02603dc NC |
2748 | char *string; |
2749 | char e; | |
2750 | ||
2751 | ++input_line_pointer; | |
2752 | e = get_symbol_name (&string); | |
fddf5b5b AM |
2753 | |
2754 | if (strcmp (string, "nojumps") == 0) | |
2755 | no_cond_jump_promotion = 1; | |
2756 | else if (strcmp (string, "jumps") == 0) | |
2757 | ; | |
2758 | else | |
2759 | as_bad (_("no such architecture modifier: `%s'"), string); | |
2760 | ||
d02603dc | 2761 | (void) restore_line_pointer (e); |
fddf5b5b AM |
2762 | } |
2763 | ||
e413e4e9 AM |
2764 | demand_empty_rest_of_line (); |
2765 | } | |
2766 | ||
8a9036a4 L |
2767 | enum bfd_architecture |
2768 | i386_arch (void) | |
2769 | { | |
3632d14b | 2770 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 L |
2771 | { |
2772 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2773 | || flag_code != CODE_64BIT) | |
2774 | as_fatal (_("Intel L1OM is 64bit ELF only")); | |
2775 | return bfd_arch_l1om; | |
2776 | } | |
7a9068fe L |
2777 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2778 | { | |
2779 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2780 | || flag_code != CODE_64BIT) | |
2781 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2782 | return bfd_arch_k1om; | |
2783 | } | |
81486035 L |
2784 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
2785 | { | |
2786 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2787 | || flag_code == CODE_64BIT) | |
2788 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2789 | return bfd_arch_iamcu; | |
2790 | } | |
8a9036a4 L |
2791 | else |
2792 | return bfd_arch_i386; | |
2793 | } | |
2794 | ||
b9d79e03 | 2795 | unsigned long |
7016a5d5 | 2796 | i386_mach (void) |
b9d79e03 | 2797 | { |
351f65ca | 2798 | if (!strncmp (default_arch, "x86_64", 6)) |
8a9036a4 | 2799 | { |
3632d14b | 2800 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 2801 | { |
351f65ca L |
2802 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour |
2803 | || default_arch[6] != '\0') | |
8a9036a4 L |
2804 | as_fatal (_("Intel L1OM is 64bit ELF only")); |
2805 | return bfd_mach_l1om; | |
2806 | } | |
7a9068fe L |
2807 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2808 | { | |
2809 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2810 | || default_arch[6] != '\0') | |
2811 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2812 | return bfd_mach_k1om; | |
2813 | } | |
351f65ca | 2814 | else if (default_arch[6] == '\0') |
8a9036a4 | 2815 | return bfd_mach_x86_64; |
351f65ca L |
2816 | else |
2817 | return bfd_mach_x64_32; | |
8a9036a4 | 2818 | } |
5197d474 L |
2819 | else if (!strcmp (default_arch, "i386") |
2820 | || !strcmp (default_arch, "iamcu")) | |
81486035 L |
2821 | { |
2822 | if (cpu_arch_isa == PROCESSOR_IAMCU) | |
2823 | { | |
2824 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
2825 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2826 | return bfd_mach_i386_iamcu; | |
2827 | } | |
2828 | else | |
2829 | return bfd_mach_i386_i386; | |
2830 | } | |
b9d79e03 | 2831 | else |
2b5d6a91 | 2832 | as_fatal (_("unknown architecture")); |
b9d79e03 | 2833 | } |
b9d79e03 | 2834 | \f |
252b5132 | 2835 | void |
7016a5d5 | 2836 | md_begin (void) |
252b5132 RH |
2837 | { |
2838 | const char *hash_err; | |
2839 | ||
86fa6981 L |
2840 | /* Support pseudo prefixes like {disp32}. */ |
2841 | lex_type ['{'] = LEX_BEGIN_NAME; | |
2842 | ||
47926f60 | 2843 | /* Initialize op_hash hash table. */ |
252b5132 RH |
2844 | op_hash = hash_new (); |
2845 | ||
2846 | { | |
d3ce72d0 | 2847 | const insn_template *optab; |
29b0f896 | 2848 | templates *core_optab; |
252b5132 | 2849 | |
47926f60 KH |
2850 | /* Setup for loop. */ |
2851 | optab = i386_optab; | |
add39d23 | 2852 | core_optab = XNEW (templates); |
252b5132 RH |
2853 | core_optab->start = optab; |
2854 | ||
2855 | while (1) | |
2856 | { | |
2857 | ++optab; | |
2858 | if (optab->name == NULL | |
2859 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
2860 | { | |
2861 | /* different name --> ship out current template list; | |
47926f60 | 2862 | add to hash table; & begin anew. */ |
252b5132 RH |
2863 | core_optab->end = optab; |
2864 | hash_err = hash_insert (op_hash, | |
2865 | (optab - 1)->name, | |
5a49b8ac | 2866 | (void *) core_optab); |
252b5132 RH |
2867 | if (hash_err) |
2868 | { | |
b37df7c4 | 2869 | as_fatal (_("can't hash %s: %s"), |
252b5132 RH |
2870 | (optab - 1)->name, |
2871 | hash_err); | |
2872 | } | |
2873 | if (optab->name == NULL) | |
2874 | break; | |
add39d23 | 2875 | core_optab = XNEW (templates); |
252b5132 RH |
2876 | core_optab->start = optab; |
2877 | } | |
2878 | } | |
2879 | } | |
2880 | ||
47926f60 | 2881 | /* Initialize reg_hash hash table. */ |
252b5132 RH |
2882 | reg_hash = hash_new (); |
2883 | { | |
29b0f896 | 2884 | const reg_entry *regtab; |
c3fe08fa | 2885 | unsigned int regtab_size = i386_regtab_size; |
252b5132 | 2886 | |
c3fe08fa | 2887 | for (regtab = i386_regtab; regtab_size--; regtab++) |
252b5132 | 2888 | { |
5a49b8ac | 2889 | hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab); |
252b5132 | 2890 | if (hash_err) |
b37df7c4 | 2891 | as_fatal (_("can't hash %s: %s"), |
3e73aa7c JH |
2892 | regtab->reg_name, |
2893 | hash_err); | |
252b5132 RH |
2894 | } |
2895 | } | |
2896 | ||
47926f60 | 2897 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 | 2898 | { |
29b0f896 AM |
2899 | int c; |
2900 | char *p; | |
252b5132 RH |
2901 | |
2902 | for (c = 0; c < 256; c++) | |
2903 | { | |
3882b010 | 2904 | if (ISDIGIT (c)) |
252b5132 RH |
2905 | { |
2906 | digit_chars[c] = c; | |
2907 | mnemonic_chars[c] = c; | |
2908 | register_chars[c] = c; | |
2909 | operand_chars[c] = c; | |
2910 | } | |
3882b010 | 2911 | else if (ISLOWER (c)) |
252b5132 RH |
2912 | { |
2913 | mnemonic_chars[c] = c; | |
2914 | register_chars[c] = c; | |
2915 | operand_chars[c] = c; | |
2916 | } | |
3882b010 | 2917 | else if (ISUPPER (c)) |
252b5132 | 2918 | { |
3882b010 | 2919 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
2920 | register_chars[c] = mnemonic_chars[c]; |
2921 | operand_chars[c] = c; | |
2922 | } | |
43234a1e | 2923 | else if (c == '{' || c == '}') |
86fa6981 L |
2924 | { |
2925 | mnemonic_chars[c] = c; | |
2926 | operand_chars[c] = c; | |
2927 | } | |
252b5132 | 2928 | |
3882b010 | 2929 | if (ISALPHA (c) || ISDIGIT (c)) |
252b5132 RH |
2930 | identifier_chars[c] = c; |
2931 | else if (c >= 128) | |
2932 | { | |
2933 | identifier_chars[c] = c; | |
2934 | operand_chars[c] = c; | |
2935 | } | |
2936 | } | |
2937 | ||
2938 | #ifdef LEX_AT | |
2939 | identifier_chars['@'] = '@'; | |
32137342 NC |
2940 | #endif |
2941 | #ifdef LEX_QM | |
2942 | identifier_chars['?'] = '?'; | |
2943 | operand_chars['?'] = '?'; | |
252b5132 | 2944 | #endif |
252b5132 | 2945 | digit_chars['-'] = '-'; |
c0f3af97 | 2946 | mnemonic_chars['_'] = '_'; |
791fe849 | 2947 | mnemonic_chars['-'] = '-'; |
0003779b | 2948 | mnemonic_chars['.'] = '.'; |
252b5132 RH |
2949 | identifier_chars['_'] = '_'; |
2950 | identifier_chars['.'] = '.'; | |
2951 | ||
2952 | for (p = operand_special_chars; *p != '\0'; p++) | |
2953 | operand_chars[(unsigned char) *p] = *p; | |
2954 | } | |
2955 | ||
a4447b93 RH |
2956 | if (flag_code == CODE_64BIT) |
2957 | { | |
ca19b261 KT |
2958 | #if defined (OBJ_COFF) && defined (TE_PE) |
2959 | x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour | |
2960 | ? 32 : 16); | |
2961 | #else | |
a4447b93 | 2962 | x86_dwarf2_return_column = 16; |
ca19b261 | 2963 | #endif |
61ff971f | 2964 | x86_cie_data_alignment = -8; |
a4447b93 RH |
2965 | } |
2966 | else | |
2967 | { | |
2968 | x86_dwarf2_return_column = 8; | |
2969 | x86_cie_data_alignment = -4; | |
2970 | } | |
252b5132 RH |
2971 | } |
2972 | ||
2973 | void | |
e3bb37b5 | 2974 | i386_print_statistics (FILE *file) |
252b5132 RH |
2975 | { |
2976 | hash_print_statistics (file, "i386 opcode", op_hash); | |
2977 | hash_print_statistics (file, "i386 register", reg_hash); | |
2978 | } | |
2979 | \f | |
252b5132 RH |
2980 | #ifdef DEBUG386 |
2981 | ||
ce8a8b2f | 2982 | /* Debugging routines for md_assemble. */ |
d3ce72d0 | 2983 | static void pte (insn_template *); |
40fb9820 | 2984 | static void pt (i386_operand_type); |
e3bb37b5 L |
2985 | static void pe (expressionS *); |
2986 | static void ps (symbolS *); | |
252b5132 RH |
2987 | |
2988 | static void | |
e3bb37b5 | 2989 | pi (char *line, i386_insn *x) |
252b5132 | 2990 | { |
09137c09 | 2991 | unsigned int j; |
252b5132 RH |
2992 | |
2993 | fprintf (stdout, "%s: template ", line); | |
2994 | pte (&x->tm); | |
09f131f2 JH |
2995 | fprintf (stdout, " address: base %s index %s scale %x\n", |
2996 | x->base_reg ? x->base_reg->reg_name : "none", | |
2997 | x->index_reg ? x->index_reg->reg_name : "none", | |
2998 | x->log2_scale_factor); | |
2999 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 3000 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
3001 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
3002 | x->sib.base, x->sib.index, x->sib.scale); | |
3003 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
161a04f6 L |
3004 | (x->rex & REX_W) != 0, |
3005 | (x->rex & REX_R) != 0, | |
3006 | (x->rex & REX_X) != 0, | |
3007 | (x->rex & REX_B) != 0); | |
09137c09 | 3008 | for (j = 0; j < x->operands; j++) |
252b5132 | 3009 | { |
09137c09 SP |
3010 | fprintf (stdout, " #%d: ", j + 1); |
3011 | pt (x->types[j]); | |
252b5132 | 3012 | fprintf (stdout, "\n"); |
dc821c5f | 3013 | if (x->types[j].bitfield.reg |
09137c09 | 3014 | || x->types[j].bitfield.regmmx |
1b54b8d7 | 3015 | || x->types[j].bitfield.regsimd |
09137c09 SP |
3016 | || x->types[j].bitfield.sreg2 |
3017 | || x->types[j].bitfield.sreg3 | |
3018 | || x->types[j].bitfield.control | |
3019 | || x->types[j].bitfield.debug | |
3020 | || x->types[j].bitfield.test) | |
3021 | fprintf (stdout, "%s\n", x->op[j].regs->reg_name); | |
3022 | if (operand_type_check (x->types[j], imm)) | |
3023 | pe (x->op[j].imms); | |
3024 | if (operand_type_check (x->types[j], disp)) | |
3025 | pe (x->op[j].disps); | |
252b5132 RH |
3026 | } |
3027 | } | |
3028 | ||
3029 | static void | |
d3ce72d0 | 3030 | pte (insn_template *t) |
252b5132 | 3031 | { |
09137c09 | 3032 | unsigned int j; |
252b5132 | 3033 | fprintf (stdout, " %d operands ", t->operands); |
47926f60 | 3034 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
3035 | if (t->extension_opcode != None) |
3036 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
40fb9820 | 3037 | if (t->opcode_modifier.d) |
252b5132 | 3038 | fprintf (stdout, "D"); |
40fb9820 | 3039 | if (t->opcode_modifier.w) |
252b5132 RH |
3040 | fprintf (stdout, "W"); |
3041 | fprintf (stdout, "\n"); | |
09137c09 | 3042 | for (j = 0; j < t->operands; j++) |
252b5132 | 3043 | { |
09137c09 SP |
3044 | fprintf (stdout, " #%d type ", j + 1); |
3045 | pt (t->operand_types[j]); | |
252b5132 RH |
3046 | fprintf (stdout, "\n"); |
3047 | } | |
3048 | } | |
3049 | ||
3050 | static void | |
e3bb37b5 | 3051 | pe (expressionS *e) |
252b5132 | 3052 | { |
24eab124 | 3053 | fprintf (stdout, " operation %d\n", e->X_op); |
b77ad1d4 AM |
3054 | fprintf (stdout, " add_number %ld (%lx)\n", |
3055 | (long) e->X_add_number, (long) e->X_add_number); | |
252b5132 RH |
3056 | if (e->X_add_symbol) |
3057 | { | |
3058 | fprintf (stdout, " add_symbol "); | |
3059 | ps (e->X_add_symbol); | |
3060 | fprintf (stdout, "\n"); | |
3061 | } | |
3062 | if (e->X_op_symbol) | |
3063 | { | |
3064 | fprintf (stdout, " op_symbol "); | |
3065 | ps (e->X_op_symbol); | |
3066 | fprintf (stdout, "\n"); | |
3067 | } | |
3068 | } | |
3069 | ||
3070 | static void | |
e3bb37b5 | 3071 | ps (symbolS *s) |
252b5132 RH |
3072 | { |
3073 | fprintf (stdout, "%s type %s%s", | |
3074 | S_GET_NAME (s), | |
3075 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
3076 | segment_name (S_GET_SEGMENT (s))); | |
3077 | } | |
3078 | ||
7b81dfbb | 3079 | static struct type_name |
252b5132 | 3080 | { |
40fb9820 L |
3081 | i386_operand_type mask; |
3082 | const char *name; | |
252b5132 | 3083 | } |
7b81dfbb | 3084 | const type_names[] = |
252b5132 | 3085 | { |
40fb9820 L |
3086 | { OPERAND_TYPE_REG8, "r8" }, |
3087 | { OPERAND_TYPE_REG16, "r16" }, | |
3088 | { OPERAND_TYPE_REG32, "r32" }, | |
3089 | { OPERAND_TYPE_REG64, "r64" }, | |
3090 | { OPERAND_TYPE_IMM8, "i8" }, | |
3091 | { OPERAND_TYPE_IMM8, "i8s" }, | |
3092 | { OPERAND_TYPE_IMM16, "i16" }, | |
3093 | { OPERAND_TYPE_IMM32, "i32" }, | |
3094 | { OPERAND_TYPE_IMM32S, "i32s" }, | |
3095 | { OPERAND_TYPE_IMM64, "i64" }, | |
3096 | { OPERAND_TYPE_IMM1, "i1" }, | |
3097 | { OPERAND_TYPE_BASEINDEX, "BaseIndex" }, | |
3098 | { OPERAND_TYPE_DISP8, "d8" }, | |
3099 | { OPERAND_TYPE_DISP16, "d16" }, | |
3100 | { OPERAND_TYPE_DISP32, "d32" }, | |
3101 | { OPERAND_TYPE_DISP32S, "d32s" }, | |
3102 | { OPERAND_TYPE_DISP64, "d64" }, | |
3103 | { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" }, | |
3104 | { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" }, | |
3105 | { OPERAND_TYPE_CONTROL, "control reg" }, | |
3106 | { OPERAND_TYPE_TEST, "test reg" }, | |
3107 | { OPERAND_TYPE_DEBUG, "debug reg" }, | |
3108 | { OPERAND_TYPE_FLOATREG, "FReg" }, | |
3109 | { OPERAND_TYPE_FLOATACC, "FAcc" }, | |
3110 | { OPERAND_TYPE_SREG2, "SReg2" }, | |
3111 | { OPERAND_TYPE_SREG3, "SReg3" }, | |
3112 | { OPERAND_TYPE_ACC, "Acc" }, | |
3113 | { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" }, | |
3114 | { OPERAND_TYPE_REGMMX, "rMMX" }, | |
3115 | { OPERAND_TYPE_REGXMM, "rXMM" }, | |
0349dc08 | 3116 | { OPERAND_TYPE_REGYMM, "rYMM" }, |
43234a1e L |
3117 | { OPERAND_TYPE_REGZMM, "rZMM" }, |
3118 | { OPERAND_TYPE_REGMASK, "Mask reg" }, | |
40fb9820 | 3119 | { OPERAND_TYPE_ESSEG, "es" }, |
252b5132 RH |
3120 | }; |
3121 | ||
3122 | static void | |
40fb9820 | 3123 | pt (i386_operand_type t) |
252b5132 | 3124 | { |
40fb9820 | 3125 | unsigned int j; |
c6fb90c8 | 3126 | i386_operand_type a; |
252b5132 | 3127 | |
40fb9820 | 3128 | for (j = 0; j < ARRAY_SIZE (type_names); j++) |
c6fb90c8 L |
3129 | { |
3130 | a = operand_type_and (t, type_names[j].mask); | |
0349dc08 | 3131 | if (!operand_type_all_zero (&a)) |
c6fb90c8 L |
3132 | fprintf (stdout, "%s, ", type_names[j].name); |
3133 | } | |
252b5132 RH |
3134 | fflush (stdout); |
3135 | } | |
3136 | ||
3137 | #endif /* DEBUG386 */ | |
3138 | \f | |
252b5132 | 3139 | static bfd_reloc_code_real_type |
3956db08 | 3140 | reloc (unsigned int size, |
64e74474 AM |
3141 | int pcrel, |
3142 | int sign, | |
3143 | bfd_reloc_code_real_type other) | |
252b5132 | 3144 | { |
47926f60 | 3145 | if (other != NO_RELOC) |
3956db08 | 3146 | { |
91d6fa6a | 3147 | reloc_howto_type *rel; |
3956db08 JB |
3148 | |
3149 | if (size == 8) | |
3150 | switch (other) | |
3151 | { | |
64e74474 AM |
3152 | case BFD_RELOC_X86_64_GOT32: |
3153 | return BFD_RELOC_X86_64_GOT64; | |
3154 | break; | |
553d1284 L |
3155 | case BFD_RELOC_X86_64_GOTPLT64: |
3156 | return BFD_RELOC_X86_64_GOTPLT64; | |
3157 | break; | |
64e74474 AM |
3158 | case BFD_RELOC_X86_64_PLTOFF64: |
3159 | return BFD_RELOC_X86_64_PLTOFF64; | |
3160 | break; | |
3161 | case BFD_RELOC_X86_64_GOTPC32: | |
3162 | other = BFD_RELOC_X86_64_GOTPC64; | |
3163 | break; | |
3164 | case BFD_RELOC_X86_64_GOTPCREL: | |
3165 | other = BFD_RELOC_X86_64_GOTPCREL64; | |
3166 | break; | |
3167 | case BFD_RELOC_X86_64_TPOFF32: | |
3168 | other = BFD_RELOC_X86_64_TPOFF64; | |
3169 | break; | |
3170 | case BFD_RELOC_X86_64_DTPOFF32: | |
3171 | other = BFD_RELOC_X86_64_DTPOFF64; | |
3172 | break; | |
3173 | default: | |
3174 | break; | |
3956db08 | 3175 | } |
e05278af | 3176 | |
8ce3d284 | 3177 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
3178 | if (other == BFD_RELOC_SIZE32) |
3179 | { | |
3180 | if (size == 8) | |
1ab668bf | 3181 | other = BFD_RELOC_SIZE64; |
8fd4256d | 3182 | if (pcrel) |
1ab668bf AM |
3183 | { |
3184 | as_bad (_("there are no pc-relative size relocations")); | |
3185 | return NO_RELOC; | |
3186 | } | |
8fd4256d | 3187 | } |
8ce3d284 | 3188 | #endif |
8fd4256d | 3189 | |
e05278af | 3190 | /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ |
f2d8a97c | 3191 | if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc)) |
e05278af JB |
3192 | sign = -1; |
3193 | ||
91d6fa6a NC |
3194 | rel = bfd_reloc_type_lookup (stdoutput, other); |
3195 | if (!rel) | |
3956db08 | 3196 | as_bad (_("unknown relocation (%u)"), other); |
91d6fa6a | 3197 | else if (size != bfd_get_reloc_size (rel)) |
3956db08 | 3198 | as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), |
91d6fa6a | 3199 | bfd_get_reloc_size (rel), |
3956db08 | 3200 | size); |
91d6fa6a | 3201 | else if (pcrel && !rel->pc_relative) |
3956db08 | 3202 | as_bad (_("non-pc-relative relocation for pc-relative field")); |
91d6fa6a | 3203 | else if ((rel->complain_on_overflow == complain_overflow_signed |
3956db08 | 3204 | && !sign) |
91d6fa6a | 3205 | || (rel->complain_on_overflow == complain_overflow_unsigned |
64e74474 | 3206 | && sign > 0)) |
3956db08 JB |
3207 | as_bad (_("relocated field and relocation type differ in signedness")); |
3208 | else | |
3209 | return other; | |
3210 | return NO_RELOC; | |
3211 | } | |
252b5132 RH |
3212 | |
3213 | if (pcrel) | |
3214 | { | |
3e73aa7c | 3215 | if (!sign) |
3956db08 | 3216 | as_bad (_("there are no unsigned pc-relative relocations")); |
252b5132 RH |
3217 | switch (size) |
3218 | { | |
3219 | case 1: return BFD_RELOC_8_PCREL; | |
3220 | case 2: return BFD_RELOC_16_PCREL; | |
d258b828 | 3221 | case 4: return BFD_RELOC_32_PCREL; |
d6ab8113 | 3222 | case 8: return BFD_RELOC_64_PCREL; |
252b5132 | 3223 | } |
3956db08 | 3224 | as_bad (_("cannot do %u byte pc-relative relocation"), size); |
252b5132 RH |
3225 | } |
3226 | else | |
3227 | { | |
3956db08 | 3228 | if (sign > 0) |
e5cb08ac | 3229 | switch (size) |
3e73aa7c JH |
3230 | { |
3231 | case 4: return BFD_RELOC_X86_64_32S; | |
3232 | } | |
3233 | else | |
3234 | switch (size) | |
3235 | { | |
3236 | case 1: return BFD_RELOC_8; | |
3237 | case 2: return BFD_RELOC_16; | |
3238 | case 4: return BFD_RELOC_32; | |
3239 | case 8: return BFD_RELOC_64; | |
3240 | } | |
3956db08 JB |
3241 | as_bad (_("cannot do %s %u byte relocation"), |
3242 | sign > 0 ? "signed" : "unsigned", size); | |
252b5132 RH |
3243 | } |
3244 | ||
0cc9e1d3 | 3245 | return NO_RELOC; |
252b5132 RH |
3246 | } |
3247 | ||
47926f60 KH |
3248 | /* Here we decide which fixups can be adjusted to make them relative to |
3249 | the beginning of the section instead of the symbol. Basically we need | |
3250 | to make sure that the dynamic relocations are done correctly, so in | |
3251 | some cases we force the original symbol to be used. */ | |
3252 | ||
252b5132 | 3253 | int |
e3bb37b5 | 3254 | tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) |
252b5132 | 3255 | { |
6d249963 | 3256 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 3257 | if (!IS_ELF) |
31312f95 AM |
3258 | return 1; |
3259 | ||
a161fe53 AM |
3260 | /* Don't adjust pc-relative references to merge sections in 64-bit |
3261 | mode. */ | |
3262 | if (use_rela_relocations | |
3263 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 | |
3264 | && fixP->fx_pcrel) | |
252b5132 | 3265 | return 0; |
31312f95 | 3266 | |
8d01d9a9 AJ |
3267 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
3268 | and changed later by validate_fix. */ | |
3269 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol | |
3270 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) | |
3271 | return 0; | |
3272 | ||
8fd4256d L |
3273 | /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol |
3274 | for size relocations. */ | |
3275 | if (fixP->fx_r_type == BFD_RELOC_SIZE32 | |
3276 | || fixP->fx_r_type == BFD_RELOC_SIZE64 | |
3277 | || fixP->fx_r_type == BFD_RELOC_386_GOTOFF | |
252b5132 RH |
3278 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 |
3279 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 | |
02a86693 | 3280 | || fixP->fx_r_type == BFD_RELOC_386_GOT32X |
13ae64f3 JJ |
3281 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
3282 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM | |
3283 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 | |
3284 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 | |
37e55690 JJ |
3285 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
3286 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE | |
13ae64f3 JJ |
3287 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
3288 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE | |
67a4f2b7 AO |
3289 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC |
3290 | || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL | |
3e73aa7c JH |
3291 | || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 |
3292 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 | |
80b3ee89 | 3293 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
56ceb5b5 L |
3294 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX |
3295 | || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX | |
bffbf940 JJ |
3296 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
3297 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD | |
3298 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 | |
d6ab8113 | 3299 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 |
bffbf940 JJ |
3300 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF |
3301 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 | |
d6ab8113 JB |
3302 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 |
3303 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 | |
67a4f2b7 AO |
3304 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
3305 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL | |
252b5132 RH |
3306 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
3307 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
3308 | return 0; | |
31312f95 | 3309 | #endif |
252b5132 RH |
3310 | return 1; |
3311 | } | |
252b5132 | 3312 | |
b4cac588 | 3313 | static int |
e3bb37b5 | 3314 | intel_float_operand (const char *mnemonic) |
252b5132 | 3315 | { |
9306ca4a JB |
3316 | /* Note that the value returned is meaningful only for opcodes with (memory) |
3317 | operands, hence the code here is free to improperly handle opcodes that | |
3318 | have no operands (for better performance and smaller code). */ | |
3319 | ||
3320 | if (mnemonic[0] != 'f') | |
3321 | return 0; /* non-math */ | |
3322 | ||
3323 | switch (mnemonic[1]) | |
3324 | { | |
3325 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and | |
3326 | the fs segment override prefix not currently handled because no | |
3327 | call path can make opcodes without operands get here */ | |
3328 | case 'i': | |
3329 | return 2 /* integer op */; | |
3330 | case 'l': | |
3331 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) | |
3332 | return 3; /* fldcw/fldenv */ | |
3333 | break; | |
3334 | case 'n': | |
3335 | if (mnemonic[2] != 'o' /* fnop */) | |
3336 | return 3; /* non-waiting control op */ | |
3337 | break; | |
3338 | case 'r': | |
3339 | if (mnemonic[2] == 's') | |
3340 | return 3; /* frstor/frstpm */ | |
3341 | break; | |
3342 | case 's': | |
3343 | if (mnemonic[2] == 'a') | |
3344 | return 3; /* fsave */ | |
3345 | if (mnemonic[2] == 't') | |
3346 | { | |
3347 | switch (mnemonic[3]) | |
3348 | { | |
3349 | case 'c': /* fstcw */ | |
3350 | case 'd': /* fstdw */ | |
3351 | case 'e': /* fstenv */ | |
3352 | case 's': /* fsts[gw] */ | |
3353 | return 3; | |
3354 | } | |
3355 | } | |
3356 | break; | |
3357 | case 'x': | |
3358 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') | |
3359 | return 0; /* fxsave/fxrstor are not really math ops */ | |
3360 | break; | |
3361 | } | |
252b5132 | 3362 | |
9306ca4a | 3363 | return 1; |
252b5132 RH |
3364 | } |
3365 | ||
c0f3af97 L |
3366 | /* Build the VEX prefix. */ |
3367 | ||
3368 | static void | |
d3ce72d0 | 3369 | build_vex_prefix (const insn_template *t) |
c0f3af97 L |
3370 | { |
3371 | unsigned int register_specifier; | |
3372 | unsigned int implied_prefix; | |
3373 | unsigned int vector_length; | |
03751133 | 3374 | unsigned int w; |
c0f3af97 L |
3375 | |
3376 | /* Check register specifier. */ | |
3377 | if (i.vex.register_specifier) | |
43234a1e L |
3378 | { |
3379 | register_specifier = | |
3380 | ~register_number (i.vex.register_specifier) & 0xf; | |
3381 | gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0); | |
3382 | } | |
c0f3af97 L |
3383 | else |
3384 | register_specifier = 0xf; | |
3385 | ||
79f0fa25 L |
3386 | /* Use 2-byte VEX prefix by swapping destination and source operand |
3387 | if there are more than 1 register operand. */ | |
3388 | if (i.reg_operands > 1 | |
3389 | && i.vec_encoding != vex_encoding_vex3 | |
86fa6981 | 3390 | && i.dir_encoding == dir_encoding_default |
fa99fab2 | 3391 | && i.operands == i.reg_operands |
dbbc8b7e | 3392 | && operand_type_equal (&i.types[0], &i.types[i.operands - 1]) |
7f399153 | 3393 | && i.tm.opcode_modifier.vexopcode == VEX0F |
dbbc8b7e | 3394 | && (i.tm.opcode_modifier.load || i.tm.opcode_modifier.d) |
fa99fab2 L |
3395 | && i.rex == REX_B) |
3396 | { | |
3397 | unsigned int xchg = i.operands - 1; | |
3398 | union i386_op temp_op; | |
3399 | i386_operand_type temp_type; | |
3400 | ||
3401 | temp_type = i.types[xchg]; | |
3402 | i.types[xchg] = i.types[0]; | |
3403 | i.types[0] = temp_type; | |
3404 | temp_op = i.op[xchg]; | |
3405 | i.op[xchg] = i.op[0]; | |
3406 | i.op[0] = temp_op; | |
3407 | ||
9c2799c2 | 3408 | gas_assert (i.rm.mode == 3); |
fa99fab2 L |
3409 | |
3410 | i.rex = REX_R; | |
3411 | xchg = i.rm.regmem; | |
3412 | i.rm.regmem = i.rm.reg; | |
3413 | i.rm.reg = xchg; | |
3414 | ||
dbbc8b7e JB |
3415 | if (i.tm.opcode_modifier.d) |
3416 | i.tm.base_opcode ^= (i.tm.base_opcode & 0xee) != 0x6e | |
3417 | ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD; | |
3418 | else /* Use the next insn. */ | |
3419 | i.tm = t[1]; | |
fa99fab2 L |
3420 | } |
3421 | ||
539f890d L |
3422 | if (i.tm.opcode_modifier.vex == VEXScalar) |
3423 | vector_length = avxscalar; | |
10c17abd JB |
3424 | else if (i.tm.opcode_modifier.vex == VEX256) |
3425 | vector_length = 1; | |
539f890d | 3426 | else |
10c17abd | 3427 | { |
56522fc5 | 3428 | unsigned int op; |
10c17abd | 3429 | |
c7213af9 L |
3430 | /* Determine vector length from the last multi-length vector |
3431 | operand. */ | |
10c17abd | 3432 | vector_length = 0; |
56522fc5 | 3433 | for (op = t->operands; op--;) |
10c17abd JB |
3434 | if (t->operand_types[op].bitfield.xmmword |
3435 | && t->operand_types[op].bitfield.ymmword | |
3436 | && i.types[op].bitfield.ymmword) | |
3437 | { | |
3438 | vector_length = 1; | |
3439 | break; | |
3440 | } | |
3441 | } | |
c0f3af97 L |
3442 | |
3443 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
3444 | { | |
3445 | case 0: | |
3446 | implied_prefix = 0; | |
3447 | break; | |
3448 | case DATA_PREFIX_OPCODE: | |
3449 | implied_prefix = 1; | |
3450 | break; | |
3451 | case REPE_PREFIX_OPCODE: | |
3452 | implied_prefix = 2; | |
3453 | break; | |
3454 | case REPNE_PREFIX_OPCODE: | |
3455 | implied_prefix = 3; | |
3456 | break; | |
3457 | default: | |
3458 | abort (); | |
3459 | } | |
3460 | ||
03751133 L |
3461 | /* Check the REX.W bit and VEXW. */ |
3462 | if (i.tm.opcode_modifier.vexw == VEXWIG) | |
3463 | w = (vexwig == vexw1 || (i.rex & REX_W)) ? 1 : 0; | |
3464 | else if (i.tm.opcode_modifier.vexw) | |
3465 | w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0; | |
3466 | else | |
931d03b7 | 3467 | w = (flag_code == CODE_64BIT ? i.rex & REX_W : vexwig == vexw1) ? 1 : 0; |
03751133 | 3468 | |
c0f3af97 | 3469 | /* Use 2-byte VEX prefix if possible. */ |
03751133 L |
3470 | if (w == 0 |
3471 | && i.vec_encoding != vex_encoding_vex3 | |
86fa6981 | 3472 | && i.tm.opcode_modifier.vexopcode == VEX0F |
c0f3af97 L |
3473 | && (i.rex & (REX_W | REX_X | REX_B)) == 0) |
3474 | { | |
3475 | /* 2-byte VEX prefix. */ | |
3476 | unsigned int r; | |
3477 | ||
3478 | i.vex.length = 2; | |
3479 | i.vex.bytes[0] = 0xc5; | |
3480 | ||
3481 | /* Check the REX.R bit. */ | |
3482 | r = (i.rex & REX_R) ? 0 : 1; | |
3483 | i.vex.bytes[1] = (r << 7 | |
3484 | | register_specifier << 3 | |
3485 | | vector_length << 2 | |
3486 | | implied_prefix); | |
3487 | } | |
3488 | else | |
3489 | { | |
3490 | /* 3-byte VEX prefix. */ | |
03751133 | 3491 | unsigned int m; |
c0f3af97 | 3492 | |
f88c9eb0 | 3493 | i.vex.length = 3; |
f88c9eb0 | 3494 | |
7f399153 | 3495 | switch (i.tm.opcode_modifier.vexopcode) |
5dd85c99 | 3496 | { |
7f399153 L |
3497 | case VEX0F: |
3498 | m = 0x1; | |
80de6e00 | 3499 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3500 | break; |
3501 | case VEX0F38: | |
3502 | m = 0x2; | |
80de6e00 | 3503 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3504 | break; |
3505 | case VEX0F3A: | |
3506 | m = 0x3; | |
80de6e00 | 3507 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3508 | break; |
3509 | case XOP08: | |
5dd85c99 SP |
3510 | m = 0x8; |
3511 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3512 | break; |
3513 | case XOP09: | |
f88c9eb0 SP |
3514 | m = 0x9; |
3515 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3516 | break; |
3517 | case XOP0A: | |
f88c9eb0 SP |
3518 | m = 0xa; |
3519 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3520 | break; |
3521 | default: | |
3522 | abort (); | |
f88c9eb0 | 3523 | } |
c0f3af97 | 3524 | |
c0f3af97 L |
3525 | /* The high 3 bits of the second VEX byte are 1's compliment |
3526 | of RXB bits from REX. */ | |
3527 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
3528 | ||
c0f3af97 L |
3529 | i.vex.bytes[2] = (w << 7 |
3530 | | register_specifier << 3 | |
3531 | | vector_length << 2 | |
3532 | | implied_prefix); | |
3533 | } | |
3534 | } | |
3535 | ||
e771e7c9 JB |
3536 | static INLINE bfd_boolean |
3537 | is_evex_encoding (const insn_template *t) | |
3538 | { | |
7091c612 | 3539 | return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift |
e771e7c9 JB |
3540 | || t->opcode_modifier.broadcast || t->opcode_modifier.masking |
3541 | || t->opcode_modifier.staticrounding || t->opcode_modifier.sae; | |
3542 | } | |
3543 | ||
7a8655d2 JB |
3544 | static INLINE bfd_boolean |
3545 | is_any_vex_encoding (const insn_template *t) | |
3546 | { | |
3547 | return t->opcode_modifier.vex || t->opcode_modifier.vexopcode | |
3548 | || is_evex_encoding (t); | |
3549 | } | |
3550 | ||
43234a1e L |
3551 | /* Build the EVEX prefix. */ |
3552 | ||
3553 | static void | |
3554 | build_evex_prefix (void) | |
3555 | { | |
3556 | unsigned int register_specifier; | |
3557 | unsigned int implied_prefix; | |
3558 | unsigned int m, w; | |
3559 | rex_byte vrex_used = 0; | |
3560 | ||
3561 | /* Check register specifier. */ | |
3562 | if (i.vex.register_specifier) | |
3563 | { | |
3564 | gas_assert ((i.vrex & REX_X) == 0); | |
3565 | ||
3566 | register_specifier = i.vex.register_specifier->reg_num; | |
3567 | if ((i.vex.register_specifier->reg_flags & RegRex)) | |
3568 | register_specifier += 8; | |
3569 | /* The upper 16 registers are encoded in the fourth byte of the | |
3570 | EVEX prefix. */ | |
3571 | if (!(i.vex.register_specifier->reg_flags & RegVRex)) | |
3572 | i.vex.bytes[3] = 0x8; | |
3573 | register_specifier = ~register_specifier & 0xf; | |
3574 | } | |
3575 | else | |
3576 | { | |
3577 | register_specifier = 0xf; | |
3578 | ||
3579 | /* Encode upper 16 vector index register in the fourth byte of | |
3580 | the EVEX prefix. */ | |
3581 | if (!(i.vrex & REX_X)) | |
3582 | i.vex.bytes[3] = 0x8; | |
3583 | else | |
3584 | vrex_used |= REX_X; | |
3585 | } | |
3586 | ||
3587 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
3588 | { | |
3589 | case 0: | |
3590 | implied_prefix = 0; | |
3591 | break; | |
3592 | case DATA_PREFIX_OPCODE: | |
3593 | implied_prefix = 1; | |
3594 | break; | |
3595 | case REPE_PREFIX_OPCODE: | |
3596 | implied_prefix = 2; | |
3597 | break; | |
3598 | case REPNE_PREFIX_OPCODE: | |
3599 | implied_prefix = 3; | |
3600 | break; | |
3601 | default: | |
3602 | abort (); | |
3603 | } | |
3604 | ||
3605 | /* 4 byte EVEX prefix. */ | |
3606 | i.vex.length = 4; | |
3607 | i.vex.bytes[0] = 0x62; | |
3608 | ||
3609 | /* mmmm bits. */ | |
3610 | switch (i.tm.opcode_modifier.vexopcode) | |
3611 | { | |
3612 | case VEX0F: | |
3613 | m = 1; | |
3614 | break; | |
3615 | case VEX0F38: | |
3616 | m = 2; | |
3617 | break; | |
3618 | case VEX0F3A: | |
3619 | m = 3; | |
3620 | break; | |
3621 | default: | |
3622 | abort (); | |
3623 | break; | |
3624 | } | |
3625 | ||
3626 | /* The high 3 bits of the second EVEX byte are 1's compliment of RXB | |
3627 | bits from REX. */ | |
3628 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
3629 | ||
3630 | /* The fifth bit of the second EVEX byte is 1's compliment of the | |
3631 | REX_R bit in VREX. */ | |
3632 | if (!(i.vrex & REX_R)) | |
3633 | i.vex.bytes[1] |= 0x10; | |
3634 | else | |
3635 | vrex_used |= REX_R; | |
3636 | ||
3637 | if ((i.reg_operands + i.imm_operands) == i.operands) | |
3638 | { | |
3639 | /* When all operands are registers, the REX_X bit in REX is not | |
3640 | used. We reuse it to encode the upper 16 registers, which is | |
3641 | indicated by the REX_B bit in VREX. The REX_X bit is encoded | |
3642 | as 1's compliment. */ | |
3643 | if ((i.vrex & REX_B)) | |
3644 | { | |
3645 | vrex_used |= REX_B; | |
3646 | i.vex.bytes[1] &= ~0x40; | |
3647 | } | |
3648 | } | |
3649 | ||
3650 | /* EVEX instructions shouldn't need the REX prefix. */ | |
3651 | i.vrex &= ~vrex_used; | |
3652 | gas_assert (i.vrex == 0); | |
3653 | ||
6865c043 L |
3654 | /* Check the REX.W bit and VEXW. */ |
3655 | if (i.tm.opcode_modifier.vexw == VEXWIG) | |
3656 | w = (evexwig == evexw1 || (i.rex & REX_W)) ? 1 : 0; | |
3657 | else if (i.tm.opcode_modifier.vexw) | |
3658 | w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0; | |
3659 | else | |
931d03b7 | 3660 | w = (flag_code == CODE_64BIT ? i.rex & REX_W : evexwig == evexw1) ? 1 : 0; |
43234a1e L |
3661 | |
3662 | /* Encode the U bit. */ | |
3663 | implied_prefix |= 0x4; | |
3664 | ||
3665 | /* The third byte of the EVEX prefix. */ | |
3666 | i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix); | |
3667 | ||
3668 | /* The fourth byte of the EVEX prefix. */ | |
3669 | /* The zeroing-masking bit. */ | |
3670 | if (i.mask && i.mask->zeroing) | |
3671 | i.vex.bytes[3] |= 0x80; | |
3672 | ||
3673 | /* Don't always set the broadcast bit if there is no RC. */ | |
3674 | if (!i.rounding) | |
3675 | { | |
3676 | /* Encode the vector length. */ | |
3677 | unsigned int vec_length; | |
3678 | ||
e771e7c9 JB |
3679 | if (!i.tm.opcode_modifier.evex |
3680 | || i.tm.opcode_modifier.evex == EVEXDYN) | |
3681 | { | |
56522fc5 | 3682 | unsigned int op; |
e771e7c9 | 3683 | |
c7213af9 L |
3684 | /* Determine vector length from the last multi-length vector |
3685 | operand. */ | |
e771e7c9 | 3686 | vec_length = 0; |
56522fc5 | 3687 | for (op = i.operands; op--;) |
e771e7c9 JB |
3688 | if (i.tm.operand_types[op].bitfield.xmmword |
3689 | + i.tm.operand_types[op].bitfield.ymmword | |
3690 | + i.tm.operand_types[op].bitfield.zmmword > 1) | |
3691 | { | |
3692 | if (i.types[op].bitfield.zmmword) | |
c7213af9 L |
3693 | { |
3694 | i.tm.opcode_modifier.evex = EVEX512; | |
3695 | break; | |
3696 | } | |
e771e7c9 | 3697 | else if (i.types[op].bitfield.ymmword) |
c7213af9 L |
3698 | { |
3699 | i.tm.opcode_modifier.evex = EVEX256; | |
3700 | break; | |
3701 | } | |
e771e7c9 | 3702 | else if (i.types[op].bitfield.xmmword) |
c7213af9 L |
3703 | { |
3704 | i.tm.opcode_modifier.evex = EVEX128; | |
3705 | break; | |
3706 | } | |
625cbd7a JB |
3707 | else if (i.broadcast && (int) op == i.broadcast->operand) |
3708 | { | |
4a1b91ea | 3709 | switch (i.broadcast->bytes) |
625cbd7a JB |
3710 | { |
3711 | case 64: | |
3712 | i.tm.opcode_modifier.evex = EVEX512; | |
3713 | break; | |
3714 | case 32: | |
3715 | i.tm.opcode_modifier.evex = EVEX256; | |
3716 | break; | |
3717 | case 16: | |
3718 | i.tm.opcode_modifier.evex = EVEX128; | |
3719 | break; | |
3720 | default: | |
c7213af9 | 3721 | abort (); |
625cbd7a | 3722 | } |
c7213af9 | 3723 | break; |
625cbd7a | 3724 | } |
e771e7c9 | 3725 | } |
c7213af9 | 3726 | |
56522fc5 | 3727 | if (op >= MAX_OPERANDS) |
c7213af9 | 3728 | abort (); |
e771e7c9 JB |
3729 | } |
3730 | ||
43234a1e L |
3731 | switch (i.tm.opcode_modifier.evex) |
3732 | { | |
3733 | case EVEXLIG: /* LL' is ignored */ | |
3734 | vec_length = evexlig << 5; | |
3735 | break; | |
3736 | case EVEX128: | |
3737 | vec_length = 0 << 5; | |
3738 | break; | |
3739 | case EVEX256: | |
3740 | vec_length = 1 << 5; | |
3741 | break; | |
3742 | case EVEX512: | |
3743 | vec_length = 2 << 5; | |
3744 | break; | |
3745 | default: | |
3746 | abort (); | |
3747 | break; | |
3748 | } | |
3749 | i.vex.bytes[3] |= vec_length; | |
3750 | /* Encode the broadcast bit. */ | |
3751 | if (i.broadcast) | |
3752 | i.vex.bytes[3] |= 0x10; | |
3753 | } | |
3754 | else | |
3755 | { | |
3756 | if (i.rounding->type != saeonly) | |
3757 | i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5); | |
3758 | else | |
d3d3c6db | 3759 | i.vex.bytes[3] |= 0x10 | (evexrcig << 5); |
43234a1e L |
3760 | } |
3761 | ||
3762 | if (i.mask && i.mask->mask) | |
3763 | i.vex.bytes[3] |= i.mask->mask->reg_num; | |
3764 | } | |
3765 | ||
65da13b5 L |
3766 | static void |
3767 | process_immext (void) | |
3768 | { | |
3769 | expressionS *exp; | |
3770 | ||
4c692bc7 JB |
3771 | if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme) |
3772 | && i.operands > 0) | |
65da13b5 | 3773 | { |
4c692bc7 JB |
3774 | /* MONITOR/MWAIT as well as SVME instructions have fixed operands |
3775 | with an opcode suffix which is coded in the same place as an | |
3776 | 8-bit immediate field would be. | |
3777 | Here we check those operands and remove them afterwards. */ | |
65da13b5 L |
3778 | unsigned int x; |
3779 | ||
3780 | for (x = 0; x < i.operands; x++) | |
4c692bc7 | 3781 | if (register_number (i.op[x].regs) != x) |
65da13b5 | 3782 | as_bad (_("can't use register '%s%s' as operand %d in '%s'."), |
1fed0ba1 L |
3783 | register_prefix, i.op[x].regs->reg_name, x + 1, |
3784 | i.tm.name); | |
3785 | ||
3786 | i.operands = 0; | |
65da13b5 L |
3787 | } |
3788 | ||
9916071f AP |
3789 | if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0) |
3790 | { | |
3791 | /* MONITORX/MWAITX instructions have fixed operands with an opcode | |
3792 | suffix which is coded in the same place as an 8-bit immediate | |
3793 | field would be. | |
3794 | Here we check those operands and remove them afterwards. */ | |
3795 | unsigned int x; | |
3796 | ||
3797 | if (i.operands != 3) | |
3798 | abort(); | |
3799 | ||
3800 | for (x = 0; x < 2; x++) | |
3801 | if (register_number (i.op[x].regs) != x) | |
3802 | goto bad_register_operand; | |
3803 | ||
3804 | /* Check for third operand for mwaitx/monitorx insn. */ | |
3805 | if (register_number (i.op[x].regs) | |
3806 | != (x + (i.tm.extension_opcode == 0xfb))) | |
3807 | { | |
3808 | bad_register_operand: | |
3809 | as_bad (_("can't use register '%s%s' as operand %d in '%s'."), | |
3810 | register_prefix, i.op[x].regs->reg_name, x+1, | |
3811 | i.tm.name); | |
3812 | } | |
3813 | ||
3814 | i.operands = 0; | |
3815 | } | |
3816 | ||
c0f3af97 | 3817 | /* These AMD 3DNow! and SSE2 instructions have an opcode suffix |
65da13b5 L |
3818 | which is coded in the same place as an 8-bit immediate field |
3819 | would be. Here we fake an 8-bit immediate operand from the | |
3820 | opcode suffix stored in tm.extension_opcode. | |
3821 | ||
c1e679ec | 3822 | AVX instructions also use this encoding, for some of |
c0f3af97 | 3823 | 3 argument instructions. */ |
65da13b5 | 3824 | |
43234a1e | 3825 | gas_assert (i.imm_operands <= 1 |
7ab9ffdd | 3826 | && (i.operands <= 2 |
7a8655d2 | 3827 | || (is_any_vex_encoding (&i.tm) |
7ab9ffdd | 3828 | && i.operands <= 4))); |
65da13b5 L |
3829 | |
3830 | exp = &im_expressions[i.imm_operands++]; | |
3831 | i.op[i.operands].imms = exp; | |
3832 | i.types[i.operands] = imm8; | |
3833 | i.operands++; | |
3834 | exp->X_op = O_constant; | |
3835 | exp->X_add_number = i.tm.extension_opcode; | |
3836 | i.tm.extension_opcode = None; | |
3837 | } | |
3838 | ||
42164a71 L |
3839 | |
3840 | static int | |
3841 | check_hle (void) | |
3842 | { | |
3843 | switch (i.tm.opcode_modifier.hleprefixok) | |
3844 | { | |
3845 | default: | |
3846 | abort (); | |
82c2def5 | 3847 | case HLEPrefixNone: |
165de32a L |
3848 | as_bad (_("invalid instruction `%s' after `%s'"), |
3849 | i.tm.name, i.hle_prefix); | |
42164a71 | 3850 | return 0; |
82c2def5 | 3851 | case HLEPrefixLock: |
42164a71 L |
3852 | if (i.prefix[LOCK_PREFIX]) |
3853 | return 1; | |
165de32a | 3854 | as_bad (_("missing `lock' with `%s'"), i.hle_prefix); |
42164a71 | 3855 | return 0; |
82c2def5 | 3856 | case HLEPrefixAny: |
42164a71 | 3857 | return 1; |
82c2def5 | 3858 | case HLEPrefixRelease: |
42164a71 L |
3859 | if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE) |
3860 | { | |
3861 | as_bad (_("instruction `%s' after `xacquire' not allowed"), | |
3862 | i.tm.name); | |
3863 | return 0; | |
3864 | } | |
3865 | if (i.mem_operands == 0 | |
3866 | || !operand_type_check (i.types[i.operands - 1], anymem)) | |
3867 | { | |
3868 | as_bad (_("memory destination needed for instruction `%s'" | |
3869 | " after `xrelease'"), i.tm.name); | |
3870 | return 0; | |
3871 | } | |
3872 | return 1; | |
3873 | } | |
3874 | } | |
3875 | ||
b6f8c7c4 L |
3876 | /* Try the shortest encoding by shortening operand size. */ |
3877 | ||
3878 | static void | |
3879 | optimize_encoding (void) | |
3880 | { | |
3881 | int j; | |
3882 | ||
3883 | if (optimize_for_space | |
3884 | && i.reg_operands == 1 | |
3885 | && i.imm_operands == 1 | |
3886 | && !i.types[1].bitfield.byte | |
3887 | && i.op[0].imms->X_op == O_constant | |
3888 | && fits_in_imm7 (i.op[0].imms->X_add_number) | |
3889 | && ((i.tm.base_opcode == 0xa8 | |
3890 | && i.tm.extension_opcode == None) | |
3891 | || (i.tm.base_opcode == 0xf6 | |
3892 | && i.tm.extension_opcode == 0x0))) | |
3893 | { | |
3894 | /* Optimize: -Os: | |
3895 | test $imm7, %r64/%r32/%r16 -> test $imm7, %r8 | |
3896 | */ | |
3897 | unsigned int base_regnum = i.op[1].regs->reg_num; | |
3898 | if (flag_code == CODE_64BIT || base_regnum < 4) | |
3899 | { | |
3900 | i.types[1].bitfield.byte = 1; | |
3901 | /* Ignore the suffix. */ | |
3902 | i.suffix = 0; | |
3903 | if (base_regnum >= 4 | |
3904 | && !(i.op[1].regs->reg_flags & RegRex)) | |
3905 | { | |
3906 | /* Handle SP, BP, SI and DI registers. */ | |
3907 | if (i.types[1].bitfield.word) | |
3908 | j = 16; | |
3909 | else if (i.types[1].bitfield.dword) | |
3910 | j = 32; | |
3911 | else | |
3912 | j = 48; | |
3913 | i.op[1].regs -= j; | |
3914 | } | |
3915 | } | |
3916 | } | |
3917 | else if (flag_code == CODE_64BIT | |
d3d50934 L |
3918 | && ((i.types[1].bitfield.qword |
3919 | && i.reg_operands == 1 | |
b6f8c7c4 L |
3920 | && i.imm_operands == 1 |
3921 | && i.op[0].imms->X_op == O_constant | |
3922 | && ((i.tm.base_opcode == 0xb0 | |
3923 | && i.tm.extension_opcode == None | |
3924 | && fits_in_unsigned_long (i.op[0].imms->X_add_number)) | |
3925 | || (fits_in_imm31 (i.op[0].imms->X_add_number) | |
3926 | && (((i.tm.base_opcode == 0x24 | |
3927 | || i.tm.base_opcode == 0xa8) | |
3928 | && i.tm.extension_opcode == None) | |
3929 | || (i.tm.base_opcode == 0x80 | |
3930 | && i.tm.extension_opcode == 0x4) | |
3931 | || ((i.tm.base_opcode == 0xf6 | |
3932 | || i.tm.base_opcode == 0xc6) | |
3933 | && i.tm.extension_opcode == 0x0))))) | |
d3d50934 L |
3934 | || (i.types[0].bitfield.qword |
3935 | && ((i.reg_operands == 2 | |
3936 | && i.op[0].regs == i.op[1].regs | |
3937 | && ((i.tm.base_opcode == 0x30 | |
3938 | || i.tm.base_opcode == 0x28) | |
3939 | && i.tm.extension_opcode == None)) | |
3940 | || (i.reg_operands == 1 | |
3941 | && i.operands == 1 | |
3942 | && i.tm.base_opcode == 0x30 | |
3943 | && i.tm.extension_opcode == None))))) | |
b6f8c7c4 L |
3944 | { |
3945 | /* Optimize: -O: | |
3946 | andq $imm31, %r64 -> andl $imm31, %r32 | |
3947 | testq $imm31, %r64 -> testl $imm31, %r32 | |
3948 | xorq %r64, %r64 -> xorl %r32, %r32 | |
3949 | subq %r64, %r64 -> subl %r32, %r32 | |
3950 | movq $imm31, %r64 -> movl $imm31, %r32 | |
3951 | movq $imm32, %r64 -> movl $imm32, %r32 | |
3952 | */ | |
3953 | i.tm.opcode_modifier.norex64 = 1; | |
3954 | if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6) | |
3955 | { | |
3956 | /* Handle | |
3957 | movq $imm31, %r64 -> movl $imm31, %r32 | |
3958 | movq $imm32, %r64 -> movl $imm32, %r32 | |
3959 | */ | |
3960 | i.tm.operand_types[0].bitfield.imm32 = 1; | |
3961 | i.tm.operand_types[0].bitfield.imm32s = 0; | |
3962 | i.tm.operand_types[0].bitfield.imm64 = 0; | |
3963 | i.types[0].bitfield.imm32 = 1; | |
3964 | i.types[0].bitfield.imm32s = 0; | |
3965 | i.types[0].bitfield.imm64 = 0; | |
3966 | i.types[1].bitfield.dword = 1; | |
3967 | i.types[1].bitfield.qword = 0; | |
3968 | if (i.tm.base_opcode == 0xc6) | |
3969 | { | |
3970 | /* Handle | |
3971 | movq $imm31, %r64 -> movl $imm31, %r32 | |
3972 | */ | |
3973 | i.tm.base_opcode = 0xb0; | |
3974 | i.tm.extension_opcode = None; | |
3975 | i.tm.opcode_modifier.shortform = 1; | |
3976 | i.tm.opcode_modifier.modrm = 0; | |
3977 | } | |
3978 | } | |
3979 | } | |
99112332 | 3980 | else if (i.reg_operands == 3 |
b6f8c7c4 L |
3981 | && i.op[0].regs == i.op[1].regs |
3982 | && !i.types[2].bitfield.xmmword | |
3983 | && (i.tm.opcode_modifier.vex | |
7a69eac3 | 3984 | || ((!i.mask || i.mask->zeroing) |
b6f8c7c4 | 3985 | && !i.rounding |
e771e7c9 | 3986 | && is_evex_encoding (&i.tm) |
80c34c38 | 3987 | && (i.vec_encoding != vex_encoding_evex |
dd22218c | 3988 | || cpu_arch_isa_flags.bitfield.cpuavx512vl |
80c34c38 | 3989 | || i.tm.cpu_flags.bitfield.cpuavx512vl |
7091c612 | 3990 | || (i.tm.operand_types[2].bitfield.zmmword |
dd22218c | 3991 | && i.types[2].bitfield.ymmword)))) |
b6f8c7c4 L |
3992 | && ((i.tm.base_opcode == 0x55 |
3993 | || i.tm.base_opcode == 0x6655 | |
3994 | || i.tm.base_opcode == 0x66df | |
3995 | || i.tm.base_opcode == 0x57 | |
3996 | || i.tm.base_opcode == 0x6657 | |
8305403a L |
3997 | || i.tm.base_opcode == 0x66ef |
3998 | || i.tm.base_opcode == 0x66f8 | |
3999 | || i.tm.base_opcode == 0x66f9 | |
4000 | || i.tm.base_opcode == 0x66fa | |
1424ad86 JB |
4001 | || i.tm.base_opcode == 0x66fb |
4002 | || i.tm.base_opcode == 0x42 | |
4003 | || i.tm.base_opcode == 0x6642 | |
4004 | || i.tm.base_opcode == 0x47 | |
4005 | || i.tm.base_opcode == 0x6647) | |
b6f8c7c4 L |
4006 | && i.tm.extension_opcode == None)) |
4007 | { | |
99112332 | 4008 | /* Optimize: -O1: |
8305403a L |
4009 | VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd, |
4010 | vpsubq and vpsubw: | |
b6f8c7c4 L |
4011 | EVEX VOP %zmmM, %zmmM, %zmmN |
4012 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4013 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4014 | EVEX VOP %ymmM, %ymmM, %ymmN |
4015 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4016 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4017 | VEX VOP %ymmM, %ymmM, %ymmN |
4018 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
4019 | VOP, one of vpandn and vpxor: | |
4020 | VEX VOP %ymmM, %ymmM, %ymmN | |
4021 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
4022 | VOP, one of vpandnd and vpandnq: | |
4023 | EVEX VOP %zmmM, %zmmM, %zmmN | |
4024 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4025 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4026 | EVEX VOP %ymmM, %ymmM, %ymmN |
4027 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4028 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4029 | VOP, one of vpxord and vpxorq: |
4030 | EVEX VOP %zmmM, %zmmM, %zmmN | |
4031 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4032 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4033 | EVEX VOP %ymmM, %ymmM, %ymmN |
4034 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4035 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
1424ad86 JB |
4036 | VOP, one of kxord and kxorq: |
4037 | VEX VOP %kM, %kM, %kN | |
4038 | -> VEX kxorw %kM, %kM, %kN | |
4039 | VOP, one of kandnd and kandnq: | |
4040 | VEX VOP %kM, %kM, %kN | |
4041 | -> VEX kandnw %kM, %kM, %kN | |
b6f8c7c4 | 4042 | */ |
e771e7c9 | 4043 | if (is_evex_encoding (&i.tm)) |
b6f8c7c4 | 4044 | { |
7b1d7ca1 | 4045 | if (i.vec_encoding != vex_encoding_evex) |
b6f8c7c4 L |
4046 | { |
4047 | i.tm.opcode_modifier.vex = VEX128; | |
4048 | i.tm.opcode_modifier.vexw = VEXW0; | |
4049 | i.tm.opcode_modifier.evex = 0; | |
4050 | } | |
7b1d7ca1 | 4051 | else if (optimize > 1) |
dd22218c L |
4052 | i.tm.opcode_modifier.evex = EVEX128; |
4053 | else | |
4054 | return; | |
b6f8c7c4 | 4055 | } |
1424ad86 JB |
4056 | else if (i.tm.operand_types[0].bitfield.regmask) |
4057 | { | |
4058 | i.tm.base_opcode &= 0xff; | |
4059 | i.tm.opcode_modifier.vexw = VEXW0; | |
4060 | } | |
b6f8c7c4 L |
4061 | else |
4062 | i.tm.opcode_modifier.vex = VEX128; | |
4063 | ||
4064 | if (i.tm.opcode_modifier.vex) | |
4065 | for (j = 0; j < 3; j++) | |
4066 | { | |
4067 | i.types[j].bitfield.xmmword = 1; | |
4068 | i.types[j].bitfield.ymmword = 0; | |
4069 | } | |
4070 | } | |
392a5972 | 4071 | else if (i.vec_encoding != vex_encoding_evex |
97ed31ae | 4072 | && !i.types[0].bitfield.zmmword |
392a5972 | 4073 | && !i.types[1].bitfield.zmmword |
97ed31ae L |
4074 | && !i.mask |
4075 | && is_evex_encoding (&i.tm) | |
392a5972 L |
4076 | && ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0x666f |
4077 | || (i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf36f | |
4078 | || (i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf26f) | |
97ed31ae L |
4079 | && i.tm.extension_opcode == None) |
4080 | { | |
4081 | /* Optimize: -O1: | |
4082 | VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, | |
4083 | vmovdqu32 and vmovdqu64: | |
4084 | EVEX VOP %xmmM, %xmmN | |
4085 | -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16) | |
4086 | EVEX VOP %ymmM, %ymmN | |
4087 | -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16) | |
4088 | EVEX VOP %xmmM, mem | |
4089 | -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16) | |
4090 | EVEX VOP %ymmM, mem | |
4091 | -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16) | |
4092 | EVEX VOP mem, %xmmN | |
4093 | -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16) | |
4094 | EVEX VOP mem, %ymmN | |
4095 | -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16) | |
4096 | */ | |
392a5972 L |
4097 | for (j = 0; j < 2; j++) |
4098 | if (operand_type_check (i.types[j], disp) | |
4099 | && i.op[j].disps->X_op == O_constant) | |
4100 | { | |
4101 | /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix | |
4102 | has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4 | |
4103 | bytes, we choose EVEX Disp8 over VEX Disp32. */ | |
4104 | int evex_disp8, vex_disp8; | |
4105 | unsigned int memshift = i.memshift; | |
4106 | offsetT n = i.op[j].disps->X_add_number; | |
4107 | ||
4108 | evex_disp8 = fits_in_disp8 (n); | |
4109 | i.memshift = 0; | |
4110 | vex_disp8 = fits_in_disp8 (n); | |
4111 | if (evex_disp8 != vex_disp8) | |
4112 | { | |
4113 | i.memshift = memshift; | |
4114 | return; | |
4115 | } | |
4116 | ||
4117 | i.types[j].bitfield.disp8 = vex_disp8; | |
4118 | break; | |
4119 | } | |
4120 | if ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf26f) | |
4121 | i.tm.base_opcode ^= 0xf36f ^ 0xf26f; | |
97ed31ae L |
4122 | i.tm.opcode_modifier.vex |
4123 | = i.types[0].bitfield.ymmword ? VEX256 : VEX128; | |
4124 | i.tm.opcode_modifier.vexw = VEXW0; | |
4125 | i.tm.opcode_modifier.evex = 0; | |
4126 | i.tm.opcode_modifier.masking = 0; | |
4127 | i.tm.opcode_modifier.disp8memshift = 0; | |
4128 | i.memshift = 0; | |
4129 | for (j = 0; j < 2; j++) | |
4130 | if (operand_type_check (i.types[j], disp) | |
4131 | && i.op[j].disps->X_op == O_constant) | |
4132 | { | |
4133 | i.types[j].bitfield.disp8 | |
4134 | = fits_in_disp8 (i.op[j].disps->X_add_number); | |
4135 | break; | |
4136 | } | |
4137 | } | |
b6f8c7c4 L |
4138 | } |
4139 | ||
252b5132 RH |
4140 | /* This is the guts of the machine-dependent assembler. LINE points to a |
4141 | machine dependent instruction. This function is supposed to emit | |
4142 | the frags/bytes it assembles to. */ | |
4143 | ||
4144 | void | |
65da13b5 | 4145 | md_assemble (char *line) |
252b5132 | 4146 | { |
40fb9820 | 4147 | unsigned int j; |
83b16ac6 | 4148 | char mnemonic[MAX_MNEM_SIZE], mnem_suffix; |
d3ce72d0 | 4149 | const insn_template *t; |
252b5132 | 4150 | |
47926f60 | 4151 | /* Initialize globals. */ |
252b5132 RH |
4152 | memset (&i, '\0', sizeof (i)); |
4153 | for (j = 0; j < MAX_OPERANDS; j++) | |
1ae12ab7 | 4154 | i.reloc[j] = NO_RELOC; |
252b5132 RH |
4155 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
4156 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 4157 | save_stack_p = save_stack; |
252b5132 RH |
4158 | |
4159 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
4160 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 4161 | start of a (possibly prefixed) mnemonic. */ |
252b5132 | 4162 | |
29b0f896 AM |
4163 | line = parse_insn (line, mnemonic); |
4164 | if (line == NULL) | |
4165 | return; | |
83b16ac6 | 4166 | mnem_suffix = i.suffix; |
252b5132 | 4167 | |
29b0f896 | 4168 | line = parse_operands (line, mnemonic); |
ee86248c | 4169 | this_operand = -1; |
8325cc63 JB |
4170 | xfree (i.memop1_string); |
4171 | i.memop1_string = NULL; | |
29b0f896 AM |
4172 | if (line == NULL) |
4173 | return; | |
252b5132 | 4174 | |
29b0f896 AM |
4175 | /* Now we've parsed the mnemonic into a set of templates, and have the |
4176 | operands at hand. */ | |
4177 | ||
4178 | /* All intel opcodes have reversed operands except for "bound" and | |
4179 | "enter". We also don't reverse intersegment "jmp" and "call" | |
4180 | instructions with 2 immediate operands so that the immediate segment | |
050dfa73 | 4181 | precedes the offset, as it does when in AT&T mode. */ |
4d456e3d L |
4182 | if (intel_syntax |
4183 | && i.operands > 1 | |
29b0f896 | 4184 | && (strcmp (mnemonic, "bound") != 0) |
30123838 | 4185 | && (strcmp (mnemonic, "invlpga") != 0) |
40fb9820 L |
4186 | && !(operand_type_check (i.types[0], imm) |
4187 | && operand_type_check (i.types[1], imm))) | |
29b0f896 AM |
4188 | swap_operands (); |
4189 | ||
ec56d5c0 JB |
4190 | /* The order of the immediates should be reversed |
4191 | for 2 immediates extrq and insertq instructions */ | |
4192 | if (i.imm_operands == 2 | |
4193 | && (strcmp (mnemonic, "extrq") == 0 | |
4194 | || strcmp (mnemonic, "insertq") == 0)) | |
4195 | swap_2_operands (0, 1); | |
4196 | ||
29b0f896 AM |
4197 | if (i.imm_operands) |
4198 | optimize_imm (); | |
4199 | ||
b300c311 L |
4200 | /* Don't optimize displacement for movabs since it only takes 64bit |
4201 | displacement. */ | |
4202 | if (i.disp_operands | |
a501d77e | 4203 | && i.disp_encoding != disp_encoding_32bit |
862be3fb L |
4204 | && (flag_code != CODE_64BIT |
4205 | || strcmp (mnemonic, "movabs") != 0)) | |
4206 | optimize_disp (); | |
29b0f896 AM |
4207 | |
4208 | /* Next, we find a template that matches the given insn, | |
4209 | making sure the overlap of the given operands types is consistent | |
4210 | with the template operand types. */ | |
252b5132 | 4211 | |
83b16ac6 | 4212 | if (!(t = match_template (mnem_suffix))) |
29b0f896 | 4213 | return; |
252b5132 | 4214 | |
7bab8ab5 | 4215 | if (sse_check != check_none |
81f8a913 | 4216 | && !i.tm.opcode_modifier.noavx |
6e3e5c9e | 4217 | && !i.tm.cpu_flags.bitfield.cpuavx |
daf50ae7 L |
4218 | && (i.tm.cpu_flags.bitfield.cpusse |
4219 | || i.tm.cpu_flags.bitfield.cpusse2 | |
4220 | || i.tm.cpu_flags.bitfield.cpusse3 | |
4221 | || i.tm.cpu_flags.bitfield.cpussse3 | |
4222 | || i.tm.cpu_flags.bitfield.cpusse4_1 | |
6e3e5c9e JB |
4223 | || i.tm.cpu_flags.bitfield.cpusse4_2 |
4224 | || i.tm.cpu_flags.bitfield.cpupclmul | |
4225 | || i.tm.cpu_flags.bitfield.cpuaes | |
4226 | || i.tm.cpu_flags.bitfield.cpugfni)) | |
daf50ae7 | 4227 | { |
7bab8ab5 | 4228 | (sse_check == check_warning |
daf50ae7 L |
4229 | ? as_warn |
4230 | : as_bad) (_("SSE instruction `%s' is used"), i.tm.name); | |
4231 | } | |
4232 | ||
321fd21e L |
4233 | /* Zap movzx and movsx suffix. The suffix has been set from |
4234 | "word ptr" or "byte ptr" on the source operand in Intel syntax | |
4235 | or extracted from mnemonic in AT&T syntax. But we'll use | |
4236 | the destination register to choose the suffix for encoding. */ | |
4237 | if ((i.tm.base_opcode & ~9) == 0x0fb6) | |
cd61ebfe | 4238 | { |
321fd21e L |
4239 | /* In Intel syntax, there must be a suffix. In AT&T syntax, if |
4240 | there is no suffix, the default will be byte extension. */ | |
4241 | if (i.reg_operands != 2 | |
4242 | && !i.suffix | |
7ab9ffdd | 4243 | && intel_syntax) |
321fd21e L |
4244 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); |
4245 | ||
4246 | i.suffix = 0; | |
cd61ebfe | 4247 | } |
24eab124 | 4248 | |
40fb9820 | 4249 | if (i.tm.opcode_modifier.fwait) |
29b0f896 AM |
4250 | if (!add_prefix (FWAIT_OPCODE)) |
4251 | return; | |
252b5132 | 4252 | |
d5de92cf L |
4253 | /* Check if REP prefix is OK. */ |
4254 | if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok) | |
4255 | { | |
4256 | as_bad (_("invalid instruction `%s' after `%s'"), | |
4257 | i.tm.name, i.rep_prefix); | |
4258 | return; | |
4259 | } | |
4260 | ||
c1ba0266 L |
4261 | /* Check for lock without a lockable instruction. Destination operand |
4262 | must be memory unless it is xchg (0x86). */ | |
c32fa91d L |
4263 | if (i.prefix[LOCK_PREFIX] |
4264 | && (!i.tm.opcode_modifier.islockable | |
c1ba0266 L |
4265 | || i.mem_operands == 0 |
4266 | || (i.tm.base_opcode != 0x86 | |
4267 | && !operand_type_check (i.types[i.operands - 1], anymem)))) | |
c32fa91d L |
4268 | { |
4269 | as_bad (_("expecting lockable instruction after `lock'")); | |
4270 | return; | |
4271 | } | |
4272 | ||
7a8655d2 JB |
4273 | /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */ |
4274 | if (i.prefix[DATA_PREFIX] && is_any_vex_encoding (&i.tm)) | |
4275 | { | |
4276 | as_bad (_("data size prefix invalid with `%s'"), i.tm.name); | |
4277 | return; | |
4278 | } | |
4279 | ||
42164a71 | 4280 | /* Check if HLE prefix is OK. */ |
165de32a | 4281 | if (i.hle_prefix && !check_hle ()) |
42164a71 L |
4282 | return; |
4283 | ||
7e8b059b L |
4284 | /* Check BND prefix. */ |
4285 | if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok) | |
4286 | as_bad (_("expecting valid branch instruction after `bnd'")); | |
4287 | ||
04ef582a | 4288 | /* Check NOTRACK prefix. */ |
9fef80d6 L |
4289 | if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok) |
4290 | as_bad (_("expecting indirect branch instruction after `notrack'")); | |
04ef582a | 4291 | |
327e8c42 JB |
4292 | if (i.tm.cpu_flags.bitfield.cpumpx) |
4293 | { | |
4294 | if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX]) | |
4295 | as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions.")); | |
4296 | else if (flag_code != CODE_16BIT | |
4297 | ? i.prefix[ADDR_PREFIX] | |
4298 | : i.mem_operands && !i.prefix[ADDR_PREFIX]) | |
4299 | as_bad (_("16-bit address isn't allowed in MPX instructions")); | |
4300 | } | |
7e8b059b L |
4301 | |
4302 | /* Insert BND prefix. */ | |
76d3a78a JB |
4303 | if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok) |
4304 | { | |
4305 | if (!i.prefix[BND_PREFIX]) | |
4306 | add_prefix (BND_PREFIX_OPCODE); | |
4307 | else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE) | |
4308 | { | |
4309 | as_warn (_("replacing `rep'/`repe' prefix by `bnd'")); | |
4310 | i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE; | |
4311 | } | |
4312 | } | |
7e8b059b | 4313 | |
29b0f896 | 4314 | /* Check string instruction segment overrides. */ |
40fb9820 | 4315 | if (i.tm.opcode_modifier.isstring && i.mem_operands != 0) |
29b0f896 AM |
4316 | { |
4317 | if (!check_string ()) | |
5dd0794d | 4318 | return; |
fc0763e6 | 4319 | i.disp_operands = 0; |
29b0f896 | 4320 | } |
5dd0794d | 4321 | |
b6f8c7c4 L |
4322 | if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize) |
4323 | optimize_encoding (); | |
4324 | ||
29b0f896 AM |
4325 | if (!process_suffix ()) |
4326 | return; | |
e413e4e9 | 4327 | |
bc0844ae L |
4328 | /* Update operand types. */ |
4329 | for (j = 0; j < i.operands; j++) | |
4330 | i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]); | |
4331 | ||
29b0f896 AM |
4332 | /* Make still unresolved immediate matches conform to size of immediate |
4333 | given in i.suffix. */ | |
4334 | if (!finalize_imm ()) | |
4335 | return; | |
252b5132 | 4336 | |
40fb9820 | 4337 | if (i.types[0].bitfield.imm1) |
29b0f896 | 4338 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 | 4339 | |
9afe6eb8 L |
4340 | /* We only need to check those implicit registers for instructions |
4341 | with 3 operands or less. */ | |
4342 | if (i.operands <= 3) | |
4343 | for (j = 0; j < i.operands; j++) | |
4344 | if (i.types[j].bitfield.inoutportreg | |
4345 | || i.types[j].bitfield.shiftcount | |
1b54b8d7 | 4346 | || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword)) |
9afe6eb8 | 4347 | i.reg_operands--; |
40fb9820 | 4348 | |
c0f3af97 L |
4349 | /* ImmExt should be processed after SSE2AVX. */ |
4350 | if (!i.tm.opcode_modifier.sse2avx | |
4351 | && i.tm.opcode_modifier.immext) | |
65da13b5 | 4352 | process_immext (); |
252b5132 | 4353 | |
29b0f896 AM |
4354 | /* For insns with operands there are more diddles to do to the opcode. */ |
4355 | if (i.operands) | |
4356 | { | |
4357 | if (!process_operands ()) | |
4358 | return; | |
4359 | } | |
40fb9820 | 4360 | else if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 AM |
4361 | { |
4362 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ | |
4363 | as_warn (_("translating to `%sp'"), i.tm.name); | |
4364 | } | |
252b5132 | 4365 | |
7a8655d2 | 4366 | if (is_any_vex_encoding (&i.tm)) |
9e5e5283 L |
4367 | { |
4368 | if (flag_code == CODE_16BIT) | |
4369 | { | |
4370 | as_bad (_("instruction `%s' isn't supported in 16-bit mode."), | |
4371 | i.tm.name); | |
4372 | return; | |
4373 | } | |
c0f3af97 | 4374 | |
9e5e5283 L |
4375 | if (i.tm.opcode_modifier.vex) |
4376 | build_vex_prefix (t); | |
4377 | else | |
4378 | build_evex_prefix (); | |
4379 | } | |
43234a1e | 4380 | |
5dd85c99 SP |
4381 | /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4 |
4382 | instructions may define INT_OPCODE as well, so avoid this corner | |
4383 | case for those instructions that use MODRM. */ | |
4384 | if (i.tm.base_opcode == INT_OPCODE | |
a6461c02 SP |
4385 | && !i.tm.opcode_modifier.modrm |
4386 | && i.op[0].imms->X_add_number == 3) | |
29b0f896 AM |
4387 | { |
4388 | i.tm.base_opcode = INT3_OPCODE; | |
4389 | i.imm_operands = 0; | |
4390 | } | |
252b5132 | 4391 | |
40fb9820 L |
4392 | if ((i.tm.opcode_modifier.jump |
4393 | || i.tm.opcode_modifier.jumpbyte | |
4394 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 AM |
4395 | && i.op[0].disps->X_op == O_constant) |
4396 | { | |
4397 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
4398 | the absolute address given by the constant. Since ix86 jumps and | |
4399 | calls are pc relative, we need to generate a reloc. */ | |
4400 | i.op[0].disps->X_add_symbol = &abs_symbol; | |
4401 | i.op[0].disps->X_op = O_symbol; | |
4402 | } | |
252b5132 | 4403 | |
40fb9820 | 4404 | if (i.tm.opcode_modifier.rex64) |
161a04f6 | 4405 | i.rex |= REX_W; |
252b5132 | 4406 | |
29b0f896 AM |
4407 | /* For 8 bit registers we need an empty rex prefix. Also if the |
4408 | instruction already has a prefix, we need to convert old | |
4409 | registers to new ones. */ | |
773f551c | 4410 | |
dc821c5f | 4411 | if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte |
29b0f896 | 4412 | && (i.op[0].regs->reg_flags & RegRex64) != 0) |
dc821c5f | 4413 | || (i.types[1].bitfield.reg && i.types[1].bitfield.byte |
29b0f896 | 4414 | && (i.op[1].regs->reg_flags & RegRex64) != 0) |
dc821c5f JB |
4415 | || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte) |
4416 | || (i.types[1].bitfield.reg && i.types[1].bitfield.byte)) | |
29b0f896 AM |
4417 | && i.rex != 0)) |
4418 | { | |
4419 | int x; | |
726c5dcd | 4420 | |
29b0f896 AM |
4421 | i.rex |= REX_OPCODE; |
4422 | for (x = 0; x < 2; x++) | |
4423 | { | |
4424 | /* Look for 8 bit operand that uses old registers. */ | |
dc821c5f | 4425 | if (i.types[x].bitfield.reg && i.types[x].bitfield.byte |
29b0f896 | 4426 | && (i.op[x].regs->reg_flags & RegRex64) == 0) |
773f551c | 4427 | { |
29b0f896 AM |
4428 | /* In case it is "hi" register, give up. */ |
4429 | if (i.op[x].regs->reg_num > 3) | |
a540244d | 4430 | as_bad (_("can't encode register '%s%s' in an " |
4eed87de | 4431 | "instruction requiring REX prefix."), |
a540244d | 4432 | register_prefix, i.op[x].regs->reg_name); |
773f551c | 4433 | |
29b0f896 AM |
4434 | /* Otherwise it is equivalent to the extended register. |
4435 | Since the encoding doesn't change this is merely | |
4436 | cosmetic cleanup for debug output. */ | |
4437 | ||
4438 | i.op[x].regs = i.op[x].regs + 8; | |
773f551c | 4439 | } |
29b0f896 AM |
4440 | } |
4441 | } | |
773f551c | 4442 | |
6b6b6807 L |
4443 | if (i.rex == 0 && i.rex_encoding) |
4444 | { | |
4445 | /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand | |
4446 | that uses legacy register. If it is "hi" register, don't add | |
4447 | the REX_OPCODE byte. */ | |
4448 | int x; | |
4449 | for (x = 0; x < 2; x++) | |
4450 | if (i.types[x].bitfield.reg | |
4451 | && i.types[x].bitfield.byte | |
4452 | && (i.op[x].regs->reg_flags & RegRex64) == 0 | |
4453 | && i.op[x].regs->reg_num > 3) | |
4454 | { | |
4455 | i.rex_encoding = FALSE; | |
4456 | break; | |
4457 | } | |
4458 | ||
4459 | if (i.rex_encoding) | |
4460 | i.rex = REX_OPCODE; | |
4461 | } | |
4462 | ||
7ab9ffdd | 4463 | if (i.rex != 0) |
29b0f896 AM |
4464 | add_prefix (REX_OPCODE | i.rex); |
4465 | ||
4466 | /* We are ready to output the insn. */ | |
4467 | output_insn (); | |
4468 | } | |
4469 | ||
4470 | static char * | |
e3bb37b5 | 4471 | parse_insn (char *line, char *mnemonic) |
29b0f896 AM |
4472 | { |
4473 | char *l = line; | |
4474 | char *token_start = l; | |
4475 | char *mnem_p; | |
5c6af06e | 4476 | int supported; |
d3ce72d0 | 4477 | const insn_template *t; |
b6169b20 | 4478 | char *dot_p = NULL; |
29b0f896 | 4479 | |
29b0f896 AM |
4480 | while (1) |
4481 | { | |
4482 | mnem_p = mnemonic; | |
4483 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
4484 | { | |
b6169b20 L |
4485 | if (*mnem_p == '.') |
4486 | dot_p = mnem_p; | |
29b0f896 AM |
4487 | mnem_p++; |
4488 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
45288df1 | 4489 | { |
29b0f896 AM |
4490 | as_bad (_("no such instruction: `%s'"), token_start); |
4491 | return NULL; | |
4492 | } | |
4493 | l++; | |
4494 | } | |
4495 | if (!is_space_char (*l) | |
4496 | && *l != END_OF_INSN | |
e44823cf JB |
4497 | && (intel_syntax |
4498 | || (*l != PREFIX_SEPARATOR | |
4499 | && *l != ','))) | |
29b0f896 AM |
4500 | { |
4501 | as_bad (_("invalid character %s in mnemonic"), | |
4502 | output_invalid (*l)); | |
4503 | return NULL; | |
4504 | } | |
4505 | if (token_start == l) | |
4506 | { | |
e44823cf | 4507 | if (!intel_syntax && *l == PREFIX_SEPARATOR) |
29b0f896 AM |
4508 | as_bad (_("expecting prefix; got nothing")); |
4509 | else | |
4510 | as_bad (_("expecting mnemonic; got nothing")); | |
4511 | return NULL; | |
4512 | } | |
45288df1 | 4513 | |
29b0f896 | 4514 | /* Look up instruction (or prefix) via hash table. */ |
d3ce72d0 | 4515 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
47926f60 | 4516 | |
29b0f896 AM |
4517 | if (*l != END_OF_INSN |
4518 | && (!is_space_char (*l) || l[1] != END_OF_INSN) | |
4519 | && current_templates | |
40fb9820 | 4520 | && current_templates->start->opcode_modifier.isprefix) |
29b0f896 | 4521 | { |
c6fb90c8 | 4522 | if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags)) |
2dd88dca JB |
4523 | { |
4524 | as_bad ((flag_code != CODE_64BIT | |
4525 | ? _("`%s' is only supported in 64-bit mode") | |
4526 | : _("`%s' is not supported in 64-bit mode")), | |
4527 | current_templates->start->name); | |
4528 | return NULL; | |
4529 | } | |
29b0f896 AM |
4530 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
4531 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
673fe0f0 JB |
4532 | if ((current_templates->start->opcode_modifier.size == SIZE16 |
4533 | || current_templates->start->opcode_modifier.size == SIZE32) | |
29b0f896 | 4534 | && flag_code != CODE_64BIT |
673fe0f0 | 4535 | && ((current_templates->start->opcode_modifier.size == SIZE32) |
29b0f896 AM |
4536 | ^ (flag_code == CODE_16BIT))) |
4537 | { | |
4538 | as_bad (_("redundant %s prefix"), | |
4539 | current_templates->start->name); | |
4540 | return NULL; | |
45288df1 | 4541 | } |
86fa6981 | 4542 | if (current_templates->start->opcode_length == 0) |
29b0f896 | 4543 | { |
86fa6981 L |
4544 | /* Handle pseudo prefixes. */ |
4545 | switch (current_templates->start->base_opcode) | |
4546 | { | |
4547 | case 0x0: | |
4548 | /* {disp8} */ | |
4549 | i.disp_encoding = disp_encoding_8bit; | |
4550 | break; | |
4551 | case 0x1: | |
4552 | /* {disp32} */ | |
4553 | i.disp_encoding = disp_encoding_32bit; | |
4554 | break; | |
4555 | case 0x2: | |
4556 | /* {load} */ | |
4557 | i.dir_encoding = dir_encoding_load; | |
4558 | break; | |
4559 | case 0x3: | |
4560 | /* {store} */ | |
4561 | i.dir_encoding = dir_encoding_store; | |
4562 | break; | |
4563 | case 0x4: | |
4564 | /* {vex2} */ | |
4565 | i.vec_encoding = vex_encoding_vex2; | |
4566 | break; | |
4567 | case 0x5: | |
4568 | /* {vex3} */ | |
4569 | i.vec_encoding = vex_encoding_vex3; | |
4570 | break; | |
4571 | case 0x6: | |
4572 | /* {evex} */ | |
4573 | i.vec_encoding = vex_encoding_evex; | |
4574 | break; | |
6b6b6807 L |
4575 | case 0x7: |
4576 | /* {rex} */ | |
4577 | i.rex_encoding = TRUE; | |
4578 | break; | |
b6f8c7c4 L |
4579 | case 0x8: |
4580 | /* {nooptimize} */ | |
4581 | i.no_optimize = TRUE; | |
4582 | break; | |
86fa6981 L |
4583 | default: |
4584 | abort (); | |
4585 | } | |
4586 | } | |
4587 | else | |
4588 | { | |
4589 | /* Add prefix, checking for repeated prefixes. */ | |
4e9ac44a | 4590 | switch (add_prefix (current_templates->start->base_opcode)) |
86fa6981 | 4591 | { |
4e9ac44a L |
4592 | case PREFIX_EXIST: |
4593 | return NULL; | |
4594 | case PREFIX_DS: | |
d777820b | 4595 | if (current_templates->start->cpu_flags.bitfield.cpuibt) |
4e9ac44a L |
4596 | i.notrack_prefix = current_templates->start->name; |
4597 | break; | |
4598 | case PREFIX_REP: | |
4599 | if (current_templates->start->cpu_flags.bitfield.cpuhle) | |
4600 | i.hle_prefix = current_templates->start->name; | |
4601 | else if (current_templates->start->cpu_flags.bitfield.cpumpx) | |
4602 | i.bnd_prefix = current_templates->start->name; | |
4603 | else | |
4604 | i.rep_prefix = current_templates->start->name; | |
4605 | break; | |
4606 | default: | |
4607 | break; | |
86fa6981 | 4608 | } |
29b0f896 AM |
4609 | } |
4610 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
4611 | token_start = ++l; | |
4612 | } | |
4613 | else | |
4614 | break; | |
4615 | } | |
45288df1 | 4616 | |
30a55f88 | 4617 | if (!current_templates) |
b6169b20 | 4618 | { |
07d5e953 JB |
4619 | /* Deprecated functionality (new code should use pseudo-prefixes instead): |
4620 | Check if we should swap operand or force 32bit displacement in | |
f8a5c266 | 4621 | encoding. */ |
30a55f88 | 4622 | if (mnem_p - 2 == dot_p && dot_p[1] == 's') |
64c49ab3 | 4623 | i.dir_encoding = dir_encoding_swap; |
8d63c93e | 4624 | else if (mnem_p - 3 == dot_p |
a501d77e L |
4625 | && dot_p[1] == 'd' |
4626 | && dot_p[2] == '8') | |
4627 | i.disp_encoding = disp_encoding_8bit; | |
8d63c93e | 4628 | else if (mnem_p - 4 == dot_p |
f8a5c266 L |
4629 | && dot_p[1] == 'd' |
4630 | && dot_p[2] == '3' | |
4631 | && dot_p[3] == '2') | |
a501d77e | 4632 | i.disp_encoding = disp_encoding_32bit; |
30a55f88 L |
4633 | else |
4634 | goto check_suffix; | |
4635 | mnem_p = dot_p; | |
4636 | *dot_p = '\0'; | |
d3ce72d0 | 4637 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
b6169b20 L |
4638 | } |
4639 | ||
29b0f896 AM |
4640 | if (!current_templates) |
4641 | { | |
b6169b20 | 4642 | check_suffix: |
1c529385 | 4643 | if (mnem_p > mnemonic) |
29b0f896 | 4644 | { |
1c529385 LH |
4645 | /* See if we can get a match by trimming off a suffix. */ |
4646 | switch (mnem_p[-1]) | |
29b0f896 | 4647 | { |
1c529385 LH |
4648 | case WORD_MNEM_SUFFIX: |
4649 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) | |
29b0f896 AM |
4650 | i.suffix = SHORT_MNEM_SUFFIX; |
4651 | else | |
1c529385 LH |
4652 | /* Fall through. */ |
4653 | case BYTE_MNEM_SUFFIX: | |
4654 | case QWORD_MNEM_SUFFIX: | |
4655 | i.suffix = mnem_p[-1]; | |
29b0f896 | 4656 | mnem_p[-1] = '\0'; |
d3ce72d0 | 4657 | current_templates = (const templates *) hash_find (op_hash, |
1c529385 LH |
4658 | mnemonic); |
4659 | break; | |
4660 | case SHORT_MNEM_SUFFIX: | |
4661 | case LONG_MNEM_SUFFIX: | |
4662 | if (!intel_syntax) | |
4663 | { | |
4664 | i.suffix = mnem_p[-1]; | |
4665 | mnem_p[-1] = '\0'; | |
4666 | current_templates = (const templates *) hash_find (op_hash, | |
4667 | mnemonic); | |
4668 | } | |
4669 | break; | |
4670 | ||
4671 | /* Intel Syntax. */ | |
4672 | case 'd': | |
4673 | if (intel_syntax) | |
4674 | { | |
4675 | if (intel_float_operand (mnemonic) == 1) | |
4676 | i.suffix = SHORT_MNEM_SUFFIX; | |
4677 | else | |
4678 | i.suffix = LONG_MNEM_SUFFIX; | |
4679 | mnem_p[-1] = '\0'; | |
4680 | current_templates = (const templates *) hash_find (op_hash, | |
4681 | mnemonic); | |
4682 | } | |
4683 | break; | |
29b0f896 | 4684 | } |
29b0f896 | 4685 | } |
1c529385 | 4686 | |
29b0f896 AM |
4687 | if (!current_templates) |
4688 | { | |
4689 | as_bad (_("no such instruction: `%s'"), token_start); | |
4690 | return NULL; | |
4691 | } | |
4692 | } | |
252b5132 | 4693 | |
40fb9820 L |
4694 | if (current_templates->start->opcode_modifier.jump |
4695 | || current_templates->start->opcode_modifier.jumpbyte) | |
29b0f896 AM |
4696 | { |
4697 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
4698 | predict taken and predict not taken respectively. | |
4699 | I'm not sure that branch hints actually do anything on loop | |
4700 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
4701 | may work in the future and it doesn't hurt to accept them | |
4702 | now. */ | |
4703 | if (l[0] == ',' && l[1] == 'p') | |
4704 | { | |
4705 | if (l[2] == 't') | |
4706 | { | |
4707 | if (!add_prefix (DS_PREFIX_OPCODE)) | |
4708 | return NULL; | |
4709 | l += 3; | |
4710 | } | |
4711 | else if (l[2] == 'n') | |
4712 | { | |
4713 | if (!add_prefix (CS_PREFIX_OPCODE)) | |
4714 | return NULL; | |
4715 | l += 3; | |
4716 | } | |
4717 | } | |
4718 | } | |
4719 | /* Any other comma loses. */ | |
4720 | if (*l == ',') | |
4721 | { | |
4722 | as_bad (_("invalid character %s in mnemonic"), | |
4723 | output_invalid (*l)); | |
4724 | return NULL; | |
4725 | } | |
252b5132 | 4726 | |
29b0f896 | 4727 | /* Check if instruction is supported on specified architecture. */ |
5c6af06e JB |
4728 | supported = 0; |
4729 | for (t = current_templates->start; t < current_templates->end; ++t) | |
4730 | { | |
c0f3af97 L |
4731 | supported |= cpu_flags_match (t); |
4732 | if (supported == CPU_FLAGS_PERFECT_MATCH) | |
548d0ee6 JB |
4733 | { |
4734 | if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT)) | |
4735 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
3629bb00 | 4736 | |
548d0ee6 JB |
4737 | return l; |
4738 | } | |
29b0f896 | 4739 | } |
3629bb00 | 4740 | |
548d0ee6 JB |
4741 | if (!(supported & CPU_FLAGS_64BIT_MATCH)) |
4742 | as_bad (flag_code == CODE_64BIT | |
4743 | ? _("`%s' is not supported in 64-bit mode") | |
4744 | : _("`%s' is only supported in 64-bit mode"), | |
4745 | current_templates->start->name); | |
4746 | else | |
4747 | as_bad (_("`%s' is not supported on `%s%s'"), | |
4748 | current_templates->start->name, | |
4749 | cpu_arch_name ? cpu_arch_name : default_arch, | |
4750 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); | |
252b5132 | 4751 | |
548d0ee6 | 4752 | return NULL; |
29b0f896 | 4753 | } |
252b5132 | 4754 | |
29b0f896 | 4755 | static char * |
e3bb37b5 | 4756 | parse_operands (char *l, const char *mnemonic) |
29b0f896 AM |
4757 | { |
4758 | char *token_start; | |
3138f287 | 4759 | |
29b0f896 AM |
4760 | /* 1 if operand is pending after ','. */ |
4761 | unsigned int expecting_operand = 0; | |
252b5132 | 4762 | |
29b0f896 AM |
4763 | /* Non-zero if operand parens not balanced. */ |
4764 | unsigned int paren_not_balanced; | |
4765 | ||
4766 | while (*l != END_OF_INSN) | |
4767 | { | |
4768 | /* Skip optional white space before operand. */ | |
4769 | if (is_space_char (*l)) | |
4770 | ++l; | |
d02603dc | 4771 | if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"') |
29b0f896 AM |
4772 | { |
4773 | as_bad (_("invalid character %s before operand %d"), | |
4774 | output_invalid (*l), | |
4775 | i.operands + 1); | |
4776 | return NULL; | |
4777 | } | |
d02603dc | 4778 | token_start = l; /* After white space. */ |
29b0f896 AM |
4779 | paren_not_balanced = 0; |
4780 | while (paren_not_balanced || *l != ',') | |
4781 | { | |
4782 | if (*l == END_OF_INSN) | |
4783 | { | |
4784 | if (paren_not_balanced) | |
4785 | { | |
4786 | if (!intel_syntax) | |
4787 | as_bad (_("unbalanced parenthesis in operand %d."), | |
4788 | i.operands + 1); | |
4789 | else | |
4790 | as_bad (_("unbalanced brackets in operand %d."), | |
4791 | i.operands + 1); | |
4792 | return NULL; | |
4793 | } | |
4794 | else | |
4795 | break; /* we are done */ | |
4796 | } | |
d02603dc | 4797 | else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"') |
29b0f896 AM |
4798 | { |
4799 | as_bad (_("invalid character %s in operand %d"), | |
4800 | output_invalid (*l), | |
4801 | i.operands + 1); | |
4802 | return NULL; | |
4803 | } | |
4804 | if (!intel_syntax) | |
4805 | { | |
4806 | if (*l == '(') | |
4807 | ++paren_not_balanced; | |
4808 | if (*l == ')') | |
4809 | --paren_not_balanced; | |
4810 | } | |
4811 | else | |
4812 | { | |
4813 | if (*l == '[') | |
4814 | ++paren_not_balanced; | |
4815 | if (*l == ']') | |
4816 | --paren_not_balanced; | |
4817 | } | |
4818 | l++; | |
4819 | } | |
4820 | if (l != token_start) | |
4821 | { /* Yes, we've read in another operand. */ | |
4822 | unsigned int operand_ok; | |
4823 | this_operand = i.operands++; | |
4824 | if (i.operands > MAX_OPERANDS) | |
4825 | { | |
4826 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
4827 | MAX_OPERANDS); | |
4828 | return NULL; | |
4829 | } | |
9d46ce34 | 4830 | i.types[this_operand].bitfield.unspecified = 1; |
29b0f896 AM |
4831 | /* Now parse operand adding info to 'i' as we go along. */ |
4832 | END_STRING_AND_SAVE (l); | |
4833 | ||
1286ab78 L |
4834 | if (i.mem_operands > 1) |
4835 | { | |
4836 | as_bad (_("too many memory references for `%s'"), | |
4837 | mnemonic); | |
4838 | return 0; | |
4839 | } | |
4840 | ||
29b0f896 AM |
4841 | if (intel_syntax) |
4842 | operand_ok = | |
4843 | i386_intel_operand (token_start, | |
4844 | intel_float_operand (mnemonic)); | |
4845 | else | |
a7619375 | 4846 | operand_ok = i386_att_operand (token_start); |
29b0f896 AM |
4847 | |
4848 | RESTORE_END_STRING (l); | |
4849 | if (!operand_ok) | |
4850 | return NULL; | |
4851 | } | |
4852 | else | |
4853 | { | |
4854 | if (expecting_operand) | |
4855 | { | |
4856 | expecting_operand_after_comma: | |
4857 | as_bad (_("expecting operand after ','; got nothing")); | |
4858 | return NULL; | |
4859 | } | |
4860 | if (*l == ',') | |
4861 | { | |
4862 | as_bad (_("expecting operand before ','; got nothing")); | |
4863 | return NULL; | |
4864 | } | |
4865 | } | |
7f3f1ea2 | 4866 | |
29b0f896 AM |
4867 | /* Now *l must be either ',' or END_OF_INSN. */ |
4868 | if (*l == ',') | |
4869 | { | |
4870 | if (*++l == END_OF_INSN) | |
4871 | { | |
4872 | /* Just skip it, if it's \n complain. */ | |
4873 | goto expecting_operand_after_comma; | |
4874 | } | |
4875 | expecting_operand = 1; | |
4876 | } | |
4877 | } | |
4878 | return l; | |
4879 | } | |
7f3f1ea2 | 4880 | |
050dfa73 | 4881 | static void |
4d456e3d | 4882 | swap_2_operands (int xchg1, int xchg2) |
050dfa73 MM |
4883 | { |
4884 | union i386_op temp_op; | |
40fb9820 | 4885 | i386_operand_type temp_type; |
c48dadc9 | 4886 | unsigned int temp_flags; |
050dfa73 | 4887 | enum bfd_reloc_code_real temp_reloc; |
4eed87de | 4888 | |
050dfa73 MM |
4889 | temp_type = i.types[xchg2]; |
4890 | i.types[xchg2] = i.types[xchg1]; | |
4891 | i.types[xchg1] = temp_type; | |
c48dadc9 JB |
4892 | |
4893 | temp_flags = i.flags[xchg2]; | |
4894 | i.flags[xchg2] = i.flags[xchg1]; | |
4895 | i.flags[xchg1] = temp_flags; | |
4896 | ||
050dfa73 MM |
4897 | temp_op = i.op[xchg2]; |
4898 | i.op[xchg2] = i.op[xchg1]; | |
4899 | i.op[xchg1] = temp_op; | |
c48dadc9 | 4900 | |
050dfa73 MM |
4901 | temp_reloc = i.reloc[xchg2]; |
4902 | i.reloc[xchg2] = i.reloc[xchg1]; | |
4903 | i.reloc[xchg1] = temp_reloc; | |
43234a1e L |
4904 | |
4905 | if (i.mask) | |
4906 | { | |
4907 | if (i.mask->operand == xchg1) | |
4908 | i.mask->operand = xchg2; | |
4909 | else if (i.mask->operand == xchg2) | |
4910 | i.mask->operand = xchg1; | |
4911 | } | |
4912 | if (i.broadcast) | |
4913 | { | |
4914 | if (i.broadcast->operand == xchg1) | |
4915 | i.broadcast->operand = xchg2; | |
4916 | else if (i.broadcast->operand == xchg2) | |
4917 | i.broadcast->operand = xchg1; | |
4918 | } | |
4919 | if (i.rounding) | |
4920 | { | |
4921 | if (i.rounding->operand == xchg1) | |
4922 | i.rounding->operand = xchg2; | |
4923 | else if (i.rounding->operand == xchg2) | |
4924 | i.rounding->operand = xchg1; | |
4925 | } | |
050dfa73 MM |
4926 | } |
4927 | ||
29b0f896 | 4928 | static void |
e3bb37b5 | 4929 | swap_operands (void) |
29b0f896 | 4930 | { |
b7c61d9a | 4931 | switch (i.operands) |
050dfa73 | 4932 | { |
c0f3af97 | 4933 | case 5: |
b7c61d9a | 4934 | case 4: |
4d456e3d | 4935 | swap_2_operands (1, i.operands - 2); |
1a0670f3 | 4936 | /* Fall through. */ |
b7c61d9a L |
4937 | case 3: |
4938 | case 2: | |
4d456e3d | 4939 | swap_2_operands (0, i.operands - 1); |
b7c61d9a L |
4940 | break; |
4941 | default: | |
4942 | abort (); | |
29b0f896 | 4943 | } |
29b0f896 AM |
4944 | |
4945 | if (i.mem_operands == 2) | |
4946 | { | |
4947 | const seg_entry *temp_seg; | |
4948 | temp_seg = i.seg[0]; | |
4949 | i.seg[0] = i.seg[1]; | |
4950 | i.seg[1] = temp_seg; | |
4951 | } | |
4952 | } | |
252b5132 | 4953 | |
29b0f896 AM |
4954 | /* Try to ensure constant immediates are represented in the smallest |
4955 | opcode possible. */ | |
4956 | static void | |
e3bb37b5 | 4957 | optimize_imm (void) |
29b0f896 AM |
4958 | { |
4959 | char guess_suffix = 0; | |
4960 | int op; | |
252b5132 | 4961 | |
29b0f896 AM |
4962 | if (i.suffix) |
4963 | guess_suffix = i.suffix; | |
4964 | else if (i.reg_operands) | |
4965 | { | |
4966 | /* Figure out a suffix from the last register operand specified. | |
4967 | We can't do this properly yet, ie. excluding InOutPortReg, | |
4968 | but the following works for instructions with immediates. | |
4969 | In any case, we can't set i.suffix yet. */ | |
4970 | for (op = i.operands; --op >= 0;) | |
dc821c5f | 4971 | if (i.types[op].bitfield.reg && i.types[op].bitfield.byte) |
7ab9ffdd | 4972 | { |
40fb9820 L |
4973 | guess_suffix = BYTE_MNEM_SUFFIX; |
4974 | break; | |
4975 | } | |
dc821c5f | 4976 | else if (i.types[op].bitfield.reg && i.types[op].bitfield.word) |
252b5132 | 4977 | { |
40fb9820 L |
4978 | guess_suffix = WORD_MNEM_SUFFIX; |
4979 | break; | |
4980 | } | |
dc821c5f | 4981 | else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword) |
40fb9820 L |
4982 | { |
4983 | guess_suffix = LONG_MNEM_SUFFIX; | |
4984 | break; | |
4985 | } | |
dc821c5f | 4986 | else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword) |
40fb9820 L |
4987 | { |
4988 | guess_suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 | 4989 | break; |
252b5132 | 4990 | } |
29b0f896 AM |
4991 | } |
4992 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) | |
4993 | guess_suffix = WORD_MNEM_SUFFIX; | |
4994 | ||
4995 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 4996 | if (operand_type_check (i.types[op], imm)) |
29b0f896 AM |
4997 | { |
4998 | switch (i.op[op].imms->X_op) | |
252b5132 | 4999 | { |
29b0f896 AM |
5000 | case O_constant: |
5001 | /* If a suffix is given, this operand may be shortened. */ | |
5002 | switch (guess_suffix) | |
252b5132 | 5003 | { |
29b0f896 | 5004 | case LONG_MNEM_SUFFIX: |
40fb9820 L |
5005 | i.types[op].bitfield.imm32 = 1; |
5006 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
5007 | break; |
5008 | case WORD_MNEM_SUFFIX: | |
40fb9820 L |
5009 | i.types[op].bitfield.imm16 = 1; |
5010 | i.types[op].bitfield.imm32 = 1; | |
5011 | i.types[op].bitfield.imm32s = 1; | |
5012 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
5013 | break; |
5014 | case BYTE_MNEM_SUFFIX: | |
40fb9820 L |
5015 | i.types[op].bitfield.imm8 = 1; |
5016 | i.types[op].bitfield.imm8s = 1; | |
5017 | i.types[op].bitfield.imm16 = 1; | |
5018 | i.types[op].bitfield.imm32 = 1; | |
5019 | i.types[op].bitfield.imm32s = 1; | |
5020 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 | 5021 | break; |
252b5132 | 5022 | } |
252b5132 | 5023 | |
29b0f896 AM |
5024 | /* If this operand is at most 16 bits, convert it |
5025 | to a signed 16 bit number before trying to see | |
5026 | whether it will fit in an even smaller size. | |
5027 | This allows a 16-bit operand such as $0xffe0 to | |
5028 | be recognised as within Imm8S range. */ | |
40fb9820 | 5029 | if ((i.types[op].bitfield.imm16) |
29b0f896 | 5030 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) |
252b5132 | 5031 | { |
29b0f896 AM |
5032 | i.op[op].imms->X_add_number = |
5033 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
5034 | } | |
a28def75 L |
5035 | #ifdef BFD64 |
5036 | /* Store 32-bit immediate in 64-bit for 64-bit BFD. */ | |
40fb9820 | 5037 | if ((i.types[op].bitfield.imm32) |
29b0f896 AM |
5038 | && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) |
5039 | == 0)) | |
5040 | { | |
5041 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number | |
5042 | ^ ((offsetT) 1 << 31)) | |
5043 | - ((offsetT) 1 << 31)); | |
5044 | } | |
a28def75 | 5045 | #endif |
40fb9820 | 5046 | i.types[op] |
c6fb90c8 L |
5047 | = operand_type_or (i.types[op], |
5048 | smallest_imm_type (i.op[op].imms->X_add_number)); | |
252b5132 | 5049 | |
29b0f896 AM |
5050 | /* We must avoid matching of Imm32 templates when 64bit |
5051 | only immediate is available. */ | |
5052 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
40fb9820 | 5053 | i.types[op].bitfield.imm32 = 0; |
29b0f896 | 5054 | break; |
252b5132 | 5055 | |
29b0f896 AM |
5056 | case O_absent: |
5057 | case O_register: | |
5058 | abort (); | |
5059 | ||
5060 | /* Symbols and expressions. */ | |
5061 | default: | |
9cd96992 JB |
5062 | /* Convert symbolic operand to proper sizes for matching, but don't |
5063 | prevent matching a set of insns that only supports sizes other | |
5064 | than those matching the insn suffix. */ | |
5065 | { | |
40fb9820 | 5066 | i386_operand_type mask, allowed; |
d3ce72d0 | 5067 | const insn_template *t; |
9cd96992 | 5068 | |
0dfbf9d7 L |
5069 | operand_type_set (&mask, 0); |
5070 | operand_type_set (&allowed, 0); | |
40fb9820 | 5071 | |
4eed87de AM |
5072 | for (t = current_templates->start; |
5073 | t < current_templates->end; | |
5074 | ++t) | |
c6fb90c8 L |
5075 | allowed = operand_type_or (allowed, |
5076 | t->operand_types[op]); | |
9cd96992 JB |
5077 | switch (guess_suffix) |
5078 | { | |
5079 | case QWORD_MNEM_SUFFIX: | |
40fb9820 L |
5080 | mask.bitfield.imm64 = 1; |
5081 | mask.bitfield.imm32s = 1; | |
9cd96992 JB |
5082 | break; |
5083 | case LONG_MNEM_SUFFIX: | |
40fb9820 | 5084 | mask.bitfield.imm32 = 1; |
9cd96992 JB |
5085 | break; |
5086 | case WORD_MNEM_SUFFIX: | |
40fb9820 | 5087 | mask.bitfield.imm16 = 1; |
9cd96992 JB |
5088 | break; |
5089 | case BYTE_MNEM_SUFFIX: | |
40fb9820 | 5090 | mask.bitfield.imm8 = 1; |
9cd96992 JB |
5091 | break; |
5092 | default: | |
9cd96992 JB |
5093 | break; |
5094 | } | |
c6fb90c8 | 5095 | allowed = operand_type_and (mask, allowed); |
0dfbf9d7 | 5096 | if (!operand_type_all_zero (&allowed)) |
c6fb90c8 | 5097 | i.types[op] = operand_type_and (i.types[op], mask); |
9cd96992 | 5098 | } |
29b0f896 | 5099 | break; |
252b5132 | 5100 | } |
29b0f896 AM |
5101 | } |
5102 | } | |
47926f60 | 5103 | |
29b0f896 AM |
5104 | /* Try to use the smallest displacement type too. */ |
5105 | static void | |
e3bb37b5 | 5106 | optimize_disp (void) |
29b0f896 AM |
5107 | { |
5108 | int op; | |
3e73aa7c | 5109 | |
29b0f896 | 5110 | for (op = i.operands; --op >= 0;) |
40fb9820 | 5111 | if (operand_type_check (i.types[op], disp)) |
252b5132 | 5112 | { |
b300c311 | 5113 | if (i.op[op].disps->X_op == O_constant) |
252b5132 | 5114 | { |
91d6fa6a | 5115 | offsetT op_disp = i.op[op].disps->X_add_number; |
29b0f896 | 5116 | |
40fb9820 | 5117 | if (i.types[op].bitfield.disp16 |
91d6fa6a | 5118 | && (op_disp & ~(offsetT) 0xffff) == 0) |
b300c311 L |
5119 | { |
5120 | /* If this operand is at most 16 bits, convert | |
5121 | to a signed 16 bit number and don't use 64bit | |
5122 | displacement. */ | |
91d6fa6a | 5123 | op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000); |
40fb9820 | 5124 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 5125 | } |
a28def75 L |
5126 | #ifdef BFD64 |
5127 | /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */ | |
40fb9820 | 5128 | if (i.types[op].bitfield.disp32 |
91d6fa6a | 5129 | && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0) |
b300c311 L |
5130 | { |
5131 | /* If this operand is at most 32 bits, convert | |
5132 | to a signed 32 bit number and don't use 64bit | |
5133 | displacement. */ | |
91d6fa6a NC |
5134 | op_disp &= (((offsetT) 2 << 31) - 1); |
5135 | op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
40fb9820 | 5136 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 5137 | } |
a28def75 | 5138 | #endif |
91d6fa6a | 5139 | if (!op_disp && i.types[op].bitfield.baseindex) |
b300c311 | 5140 | { |
40fb9820 L |
5141 | i.types[op].bitfield.disp8 = 0; |
5142 | i.types[op].bitfield.disp16 = 0; | |
5143 | i.types[op].bitfield.disp32 = 0; | |
5144 | i.types[op].bitfield.disp32s = 0; | |
5145 | i.types[op].bitfield.disp64 = 0; | |
b300c311 L |
5146 | i.op[op].disps = 0; |
5147 | i.disp_operands--; | |
5148 | } | |
5149 | else if (flag_code == CODE_64BIT) | |
5150 | { | |
91d6fa6a | 5151 | if (fits_in_signed_long (op_disp)) |
28a9d8f5 | 5152 | { |
40fb9820 L |
5153 | i.types[op].bitfield.disp64 = 0; |
5154 | i.types[op].bitfield.disp32s = 1; | |
28a9d8f5 | 5155 | } |
0e1147d9 | 5156 | if (i.prefix[ADDR_PREFIX] |
91d6fa6a | 5157 | && fits_in_unsigned_long (op_disp)) |
40fb9820 | 5158 | i.types[op].bitfield.disp32 = 1; |
b300c311 | 5159 | } |
40fb9820 L |
5160 | if ((i.types[op].bitfield.disp32 |
5161 | || i.types[op].bitfield.disp32s | |
5162 | || i.types[op].bitfield.disp16) | |
b5014f7a | 5163 | && fits_in_disp8 (op_disp)) |
40fb9820 | 5164 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 5165 | } |
67a4f2b7 AO |
5166 | else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
5167 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) | |
5168 | { | |
5169 | fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, | |
5170 | i.op[op].disps, 0, i.reloc[op]); | |
40fb9820 L |
5171 | i.types[op].bitfield.disp8 = 0; |
5172 | i.types[op].bitfield.disp16 = 0; | |
5173 | i.types[op].bitfield.disp32 = 0; | |
5174 | i.types[op].bitfield.disp32s = 0; | |
5175 | i.types[op].bitfield.disp64 = 0; | |
67a4f2b7 AO |
5176 | } |
5177 | else | |
b300c311 | 5178 | /* We only support 64bit displacement on constants. */ |
40fb9820 | 5179 | i.types[op].bitfield.disp64 = 0; |
252b5132 | 5180 | } |
29b0f896 AM |
5181 | } |
5182 | ||
4a1b91ea L |
5183 | /* Return 1 if there is a match in broadcast bytes between operand |
5184 | GIVEN and instruction template T. */ | |
5185 | ||
5186 | static INLINE int | |
5187 | match_broadcast_size (const insn_template *t, unsigned int given) | |
5188 | { | |
5189 | return ((t->opcode_modifier.broadcast == BYTE_BROADCAST | |
5190 | && i.types[given].bitfield.byte) | |
5191 | || (t->opcode_modifier.broadcast == WORD_BROADCAST | |
5192 | && i.types[given].bitfield.word) | |
5193 | || (t->opcode_modifier.broadcast == DWORD_BROADCAST | |
5194 | && i.types[given].bitfield.dword) | |
5195 | || (t->opcode_modifier.broadcast == QWORD_BROADCAST | |
5196 | && i.types[given].bitfield.qword)); | |
5197 | } | |
5198 | ||
6c30d220 L |
5199 | /* Check if operands are valid for the instruction. */ |
5200 | ||
5201 | static int | |
5202 | check_VecOperands (const insn_template *t) | |
5203 | { | |
43234a1e | 5204 | unsigned int op; |
e2195274 JB |
5205 | i386_cpu_flags cpu; |
5206 | static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS; | |
5207 | ||
5208 | /* Templates allowing for ZMMword as well as YMMword and/or XMMword for | |
5209 | any one operand are implicity requiring AVX512VL support if the actual | |
5210 | operand size is YMMword or XMMword. Since this function runs after | |
5211 | template matching, there's no need to check for YMMword/XMMword in | |
5212 | the template. */ | |
5213 | cpu = cpu_flags_and (t->cpu_flags, avx512); | |
5214 | if (!cpu_flags_all_zero (&cpu) | |
5215 | && !t->cpu_flags.bitfield.cpuavx512vl | |
5216 | && !cpu_arch_flags.bitfield.cpuavx512vl) | |
5217 | { | |
5218 | for (op = 0; op < t->operands; ++op) | |
5219 | { | |
5220 | if (t->operand_types[op].bitfield.zmmword | |
5221 | && (i.types[op].bitfield.ymmword | |
5222 | || i.types[op].bitfield.xmmword)) | |
5223 | { | |
5224 | i.error = unsupported; | |
5225 | return 1; | |
5226 | } | |
5227 | } | |
5228 | } | |
43234a1e | 5229 | |
6c30d220 L |
5230 | /* Without VSIB byte, we can't have a vector register for index. */ |
5231 | if (!t->opcode_modifier.vecsib | |
5232 | && i.index_reg | |
1b54b8d7 JB |
5233 | && (i.index_reg->reg_type.bitfield.xmmword |
5234 | || i.index_reg->reg_type.bitfield.ymmword | |
5235 | || i.index_reg->reg_type.bitfield.zmmword)) | |
6c30d220 L |
5236 | { |
5237 | i.error = unsupported_vector_index_register; | |
5238 | return 1; | |
5239 | } | |
5240 | ||
ad8ecc81 MZ |
5241 | /* Check if default mask is allowed. */ |
5242 | if (t->opcode_modifier.nodefmask | |
5243 | && (!i.mask || i.mask->mask->reg_num == 0)) | |
5244 | { | |
5245 | i.error = no_default_mask; | |
5246 | return 1; | |
5247 | } | |
5248 | ||
7bab8ab5 JB |
5249 | /* For VSIB byte, we need a vector register for index, and all vector |
5250 | registers must be distinct. */ | |
5251 | if (t->opcode_modifier.vecsib) | |
5252 | { | |
5253 | if (!i.index_reg | |
6c30d220 | 5254 | || !((t->opcode_modifier.vecsib == VecSIB128 |
1b54b8d7 | 5255 | && i.index_reg->reg_type.bitfield.xmmword) |
6c30d220 | 5256 | || (t->opcode_modifier.vecsib == VecSIB256 |
1b54b8d7 | 5257 | && i.index_reg->reg_type.bitfield.ymmword) |
43234a1e | 5258 | || (t->opcode_modifier.vecsib == VecSIB512 |
1b54b8d7 | 5259 | && i.index_reg->reg_type.bitfield.zmmword))) |
7bab8ab5 JB |
5260 | { |
5261 | i.error = invalid_vsib_address; | |
5262 | return 1; | |
5263 | } | |
5264 | ||
43234a1e L |
5265 | gas_assert (i.reg_operands == 2 || i.mask); |
5266 | if (i.reg_operands == 2 && !i.mask) | |
5267 | { | |
1b54b8d7 JB |
5268 | gas_assert (i.types[0].bitfield.regsimd); |
5269 | gas_assert (i.types[0].bitfield.xmmword | |
5270 | || i.types[0].bitfield.ymmword); | |
5271 | gas_assert (i.types[2].bitfield.regsimd); | |
5272 | gas_assert (i.types[2].bitfield.xmmword | |
5273 | || i.types[2].bitfield.ymmword); | |
43234a1e L |
5274 | if (operand_check == check_none) |
5275 | return 0; | |
5276 | if (register_number (i.op[0].regs) | |
5277 | != register_number (i.index_reg) | |
5278 | && register_number (i.op[2].regs) | |
5279 | != register_number (i.index_reg) | |
5280 | && register_number (i.op[0].regs) | |
5281 | != register_number (i.op[2].regs)) | |
5282 | return 0; | |
5283 | if (operand_check == check_error) | |
5284 | { | |
5285 | i.error = invalid_vector_register_set; | |
5286 | return 1; | |
5287 | } | |
5288 | as_warn (_("mask, index, and destination registers should be distinct")); | |
5289 | } | |
8444f82a MZ |
5290 | else if (i.reg_operands == 1 && i.mask) |
5291 | { | |
1b54b8d7 JB |
5292 | if (i.types[1].bitfield.regsimd |
5293 | && (i.types[1].bitfield.xmmword | |
5294 | || i.types[1].bitfield.ymmword | |
5295 | || i.types[1].bitfield.zmmword) | |
8444f82a MZ |
5296 | && (register_number (i.op[1].regs) |
5297 | == register_number (i.index_reg))) | |
5298 | { | |
5299 | if (operand_check == check_error) | |
5300 | { | |
5301 | i.error = invalid_vector_register_set; | |
5302 | return 1; | |
5303 | } | |
5304 | if (operand_check != check_none) | |
5305 | as_warn (_("index and destination registers should be distinct")); | |
5306 | } | |
5307 | } | |
43234a1e | 5308 | } |
7bab8ab5 | 5309 | |
43234a1e L |
5310 | /* Check if broadcast is supported by the instruction and is applied |
5311 | to the memory operand. */ | |
5312 | if (i.broadcast) | |
5313 | { | |
8e6e0792 | 5314 | i386_operand_type type, overlap; |
43234a1e L |
5315 | |
5316 | /* Check if specified broadcast is supported in this instruction, | |
4a1b91ea | 5317 | and its broadcast bytes match the memory operand. */ |
32546502 | 5318 | op = i.broadcast->operand; |
8e6e0792 | 5319 | if (!t->opcode_modifier.broadcast |
c48dadc9 | 5320 | || !(i.flags[op] & Operand_Mem) |
c39e5b26 | 5321 | || (!i.types[op].bitfield.unspecified |
4a1b91ea | 5322 | && !match_broadcast_size (t, op))) |
43234a1e L |
5323 | { |
5324 | bad_broadcast: | |
5325 | i.error = unsupported_broadcast; | |
5326 | return 1; | |
5327 | } | |
8e6e0792 | 5328 | |
4a1b91ea L |
5329 | i.broadcast->bytes = ((1 << (t->opcode_modifier.broadcast - 1)) |
5330 | * i.broadcast->type); | |
8e6e0792 | 5331 | operand_type_set (&type, 0); |
4a1b91ea | 5332 | switch (i.broadcast->bytes) |
8e6e0792 | 5333 | { |
4a1b91ea L |
5334 | case 2: |
5335 | type.bitfield.word = 1; | |
5336 | break; | |
5337 | case 4: | |
5338 | type.bitfield.dword = 1; | |
5339 | break; | |
8e6e0792 JB |
5340 | case 8: |
5341 | type.bitfield.qword = 1; | |
5342 | break; | |
5343 | case 16: | |
5344 | type.bitfield.xmmword = 1; | |
5345 | break; | |
5346 | case 32: | |
5347 | type.bitfield.ymmword = 1; | |
5348 | break; | |
5349 | case 64: | |
5350 | type.bitfield.zmmword = 1; | |
5351 | break; | |
5352 | default: | |
5353 | goto bad_broadcast; | |
5354 | } | |
5355 | ||
5356 | overlap = operand_type_and (type, t->operand_types[op]); | |
5357 | if (operand_type_all_zero (&overlap)) | |
5358 | goto bad_broadcast; | |
5359 | ||
5360 | if (t->opcode_modifier.checkregsize) | |
5361 | { | |
5362 | unsigned int j; | |
5363 | ||
e2195274 | 5364 | type.bitfield.baseindex = 1; |
8e6e0792 JB |
5365 | for (j = 0; j < i.operands; ++j) |
5366 | { | |
5367 | if (j != op | |
5368 | && !operand_type_register_match(i.types[j], | |
5369 | t->operand_types[j], | |
5370 | type, | |
5371 | t->operand_types[op])) | |
5372 | goto bad_broadcast; | |
5373 | } | |
5374 | } | |
43234a1e L |
5375 | } |
5376 | /* If broadcast is supported in this instruction, we need to check if | |
5377 | operand of one-element size isn't specified without broadcast. */ | |
5378 | else if (t->opcode_modifier.broadcast && i.mem_operands) | |
5379 | { | |
5380 | /* Find memory operand. */ | |
5381 | for (op = 0; op < i.operands; op++) | |
5382 | if (operand_type_check (i.types[op], anymem)) | |
5383 | break; | |
5384 | gas_assert (op < i.operands); | |
5385 | /* Check size of the memory operand. */ | |
4a1b91ea | 5386 | if (match_broadcast_size (t, op)) |
43234a1e L |
5387 | { |
5388 | i.error = broadcast_needed; | |
5389 | return 1; | |
5390 | } | |
5391 | } | |
c39e5b26 JB |
5392 | else |
5393 | op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */ | |
43234a1e L |
5394 | |
5395 | /* Check if requested masking is supported. */ | |
ae2387fe | 5396 | if (i.mask) |
43234a1e | 5397 | { |
ae2387fe JB |
5398 | switch (t->opcode_modifier.masking) |
5399 | { | |
5400 | case BOTH_MASKING: | |
5401 | break; | |
5402 | case MERGING_MASKING: | |
5403 | if (i.mask->zeroing) | |
5404 | { | |
5405 | case 0: | |
5406 | i.error = unsupported_masking; | |
5407 | return 1; | |
5408 | } | |
5409 | break; | |
5410 | case DYNAMIC_MASKING: | |
5411 | /* Memory destinations allow only merging masking. */ | |
5412 | if (i.mask->zeroing && i.mem_operands) | |
5413 | { | |
5414 | /* Find memory operand. */ | |
5415 | for (op = 0; op < i.operands; op++) | |
c48dadc9 | 5416 | if (i.flags[op] & Operand_Mem) |
ae2387fe JB |
5417 | break; |
5418 | gas_assert (op < i.operands); | |
5419 | if (op == i.operands - 1) | |
5420 | { | |
5421 | i.error = unsupported_masking; | |
5422 | return 1; | |
5423 | } | |
5424 | } | |
5425 | break; | |
5426 | default: | |
5427 | abort (); | |
5428 | } | |
43234a1e L |
5429 | } |
5430 | ||
5431 | /* Check if masking is applied to dest operand. */ | |
5432 | if (i.mask && (i.mask->operand != (int) (i.operands - 1))) | |
5433 | { | |
5434 | i.error = mask_not_on_destination; | |
5435 | return 1; | |
5436 | } | |
5437 | ||
43234a1e L |
5438 | /* Check RC/SAE. */ |
5439 | if (i.rounding) | |
5440 | { | |
5441 | if ((i.rounding->type != saeonly | |
5442 | && !t->opcode_modifier.staticrounding) | |
5443 | || (i.rounding->type == saeonly | |
5444 | && (t->opcode_modifier.staticrounding | |
5445 | || !t->opcode_modifier.sae))) | |
5446 | { | |
5447 | i.error = unsupported_rc_sae; | |
5448 | return 1; | |
5449 | } | |
5450 | /* If the instruction has several immediate operands and one of | |
5451 | them is rounding, the rounding operand should be the last | |
5452 | immediate operand. */ | |
5453 | if (i.imm_operands > 1 | |
5454 | && i.rounding->operand != (int) (i.imm_operands - 1)) | |
7bab8ab5 | 5455 | { |
43234a1e | 5456 | i.error = rc_sae_operand_not_last_imm; |
7bab8ab5 JB |
5457 | return 1; |
5458 | } | |
6c30d220 L |
5459 | } |
5460 | ||
43234a1e | 5461 | /* Check vector Disp8 operand. */ |
b5014f7a JB |
5462 | if (t->opcode_modifier.disp8memshift |
5463 | && i.disp_encoding != disp_encoding_32bit) | |
43234a1e L |
5464 | { |
5465 | if (i.broadcast) | |
4a1b91ea | 5466 | i.memshift = t->opcode_modifier.broadcast - 1; |
7091c612 | 5467 | else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL) |
43234a1e | 5468 | i.memshift = t->opcode_modifier.disp8memshift; |
7091c612 JB |
5469 | else |
5470 | { | |
5471 | const i386_operand_type *type = NULL; | |
5472 | ||
5473 | i.memshift = 0; | |
5474 | for (op = 0; op < i.operands; op++) | |
5475 | if (operand_type_check (i.types[op], anymem)) | |
5476 | { | |
4174bfff JB |
5477 | if (t->opcode_modifier.evex == EVEXLIG) |
5478 | i.memshift = 2 + (i.suffix == QWORD_MNEM_SUFFIX); | |
5479 | else if (t->operand_types[op].bitfield.xmmword | |
5480 | + t->operand_types[op].bitfield.ymmword | |
5481 | + t->operand_types[op].bitfield.zmmword <= 1) | |
7091c612 JB |
5482 | type = &t->operand_types[op]; |
5483 | else if (!i.types[op].bitfield.unspecified) | |
5484 | type = &i.types[op]; | |
5485 | } | |
4174bfff JB |
5486 | else if (i.types[op].bitfield.regsimd |
5487 | && t->opcode_modifier.evex != EVEXLIG) | |
7091c612 JB |
5488 | { |
5489 | if (i.types[op].bitfield.zmmword) | |
5490 | i.memshift = 6; | |
5491 | else if (i.types[op].bitfield.ymmword && i.memshift < 5) | |
5492 | i.memshift = 5; | |
5493 | else if (i.types[op].bitfield.xmmword && i.memshift < 4) | |
5494 | i.memshift = 4; | |
5495 | } | |
5496 | ||
5497 | if (type) | |
5498 | { | |
5499 | if (type->bitfield.zmmword) | |
5500 | i.memshift = 6; | |
5501 | else if (type->bitfield.ymmword) | |
5502 | i.memshift = 5; | |
5503 | else if (type->bitfield.xmmword) | |
5504 | i.memshift = 4; | |
5505 | } | |
5506 | ||
5507 | /* For the check in fits_in_disp8(). */ | |
5508 | if (i.memshift == 0) | |
5509 | i.memshift = -1; | |
5510 | } | |
43234a1e L |
5511 | |
5512 | for (op = 0; op < i.operands; op++) | |
5513 | if (operand_type_check (i.types[op], disp) | |
5514 | && i.op[op].disps->X_op == O_constant) | |
5515 | { | |
b5014f7a | 5516 | if (fits_in_disp8 (i.op[op].disps->X_add_number)) |
43234a1e | 5517 | { |
b5014f7a JB |
5518 | i.types[op].bitfield.disp8 = 1; |
5519 | return 0; | |
43234a1e | 5520 | } |
b5014f7a | 5521 | i.types[op].bitfield.disp8 = 0; |
43234a1e L |
5522 | } |
5523 | } | |
b5014f7a JB |
5524 | |
5525 | i.memshift = 0; | |
43234a1e | 5526 | |
6c30d220 L |
5527 | return 0; |
5528 | } | |
5529 | ||
43f3e2ee | 5530 | /* Check if operands are valid for the instruction. Update VEX |
a683cc34 SP |
5531 | operand types. */ |
5532 | ||
5533 | static int | |
5534 | VEX_check_operands (const insn_template *t) | |
5535 | { | |
86fa6981 | 5536 | if (i.vec_encoding == vex_encoding_evex) |
43234a1e | 5537 | { |
86fa6981 | 5538 | /* This instruction must be encoded with EVEX prefix. */ |
e771e7c9 | 5539 | if (!is_evex_encoding (t)) |
86fa6981 L |
5540 | { |
5541 | i.error = unsupported; | |
5542 | return 1; | |
5543 | } | |
5544 | return 0; | |
43234a1e L |
5545 | } |
5546 | ||
a683cc34 | 5547 | if (!t->opcode_modifier.vex) |
86fa6981 L |
5548 | { |
5549 | /* This instruction template doesn't have VEX prefix. */ | |
5550 | if (i.vec_encoding != vex_encoding_default) | |
5551 | { | |
5552 | i.error = unsupported; | |
5553 | return 1; | |
5554 | } | |
5555 | return 0; | |
5556 | } | |
a683cc34 SP |
5557 | |
5558 | /* Only check VEX_Imm4, which must be the first operand. */ | |
5559 | if (t->operand_types[0].bitfield.vec_imm4) | |
5560 | { | |
5561 | if (i.op[0].imms->X_op != O_constant | |
5562 | || !fits_in_imm4 (i.op[0].imms->X_add_number)) | |
891edac4 | 5563 | { |
a65babc9 | 5564 | i.error = bad_imm4; |
891edac4 L |
5565 | return 1; |
5566 | } | |
a683cc34 SP |
5567 | |
5568 | /* Turn off Imm8 so that update_imm won't complain. */ | |
5569 | i.types[0] = vec_imm4; | |
5570 | } | |
5571 | ||
5572 | return 0; | |
5573 | } | |
5574 | ||
d3ce72d0 | 5575 | static const insn_template * |
83b16ac6 | 5576 | match_template (char mnem_suffix) |
29b0f896 AM |
5577 | { |
5578 | /* Points to template once we've found it. */ | |
d3ce72d0 | 5579 | const insn_template *t; |
40fb9820 | 5580 | i386_operand_type overlap0, overlap1, overlap2, overlap3; |
c0f3af97 | 5581 | i386_operand_type overlap4; |
29b0f896 | 5582 | unsigned int found_reverse_match; |
83b16ac6 | 5583 | i386_opcode_modifier suffix_check, mnemsuf_check; |
40fb9820 | 5584 | i386_operand_type operand_types [MAX_OPERANDS]; |
539e75ad | 5585 | int addr_prefix_disp; |
a5c311ca | 5586 | unsigned int j; |
3ac21baa | 5587 | unsigned int found_cpu_match, size_match; |
45664ddb | 5588 | unsigned int check_register; |
5614d22c | 5589 | enum i386_error specific_error = 0; |
29b0f896 | 5590 | |
c0f3af97 L |
5591 | #if MAX_OPERANDS != 5 |
5592 | # error "MAX_OPERANDS must be 5." | |
f48ff2ae L |
5593 | #endif |
5594 | ||
29b0f896 | 5595 | found_reverse_match = 0; |
539e75ad | 5596 | addr_prefix_disp = -1; |
40fb9820 L |
5597 | |
5598 | memset (&suffix_check, 0, sizeof (suffix_check)); | |
e2195274 JB |
5599 | if (intel_syntax && i.broadcast) |
5600 | /* nothing */; | |
5601 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
40fb9820 L |
5602 | suffix_check.no_bsuf = 1; |
5603 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
5604 | suffix_check.no_wsuf = 1; | |
5605 | else if (i.suffix == SHORT_MNEM_SUFFIX) | |
5606 | suffix_check.no_ssuf = 1; | |
5607 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
5608 | suffix_check.no_lsuf = 1; | |
5609 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
5610 | suffix_check.no_qsuf = 1; | |
5611 | else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX) | |
7ce189b3 | 5612 | suffix_check.no_ldsuf = 1; |
29b0f896 | 5613 | |
83b16ac6 JB |
5614 | memset (&mnemsuf_check, 0, sizeof (mnemsuf_check)); |
5615 | if (intel_syntax) | |
5616 | { | |
5617 | switch (mnem_suffix) | |
5618 | { | |
5619 | case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break; | |
5620 | case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break; | |
5621 | case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break; | |
5622 | case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break; | |
5623 | case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break; | |
5624 | } | |
5625 | } | |
5626 | ||
01559ecc L |
5627 | /* Must have right number of operands. */ |
5628 | i.error = number_of_operands_mismatch; | |
5629 | ||
45aa61fe | 5630 | for (t = current_templates->start; t < current_templates->end; t++) |
29b0f896 | 5631 | { |
539e75ad | 5632 | addr_prefix_disp = -1; |
dbbc8b7e | 5633 | found_reverse_match = 0; |
539e75ad | 5634 | |
29b0f896 AM |
5635 | if (i.operands != t->operands) |
5636 | continue; | |
5637 | ||
50aecf8c | 5638 | /* Check processor support. */ |
a65babc9 | 5639 | i.error = unsupported; |
c0f3af97 L |
5640 | found_cpu_match = (cpu_flags_match (t) |
5641 | == CPU_FLAGS_PERFECT_MATCH); | |
50aecf8c L |
5642 | if (!found_cpu_match) |
5643 | continue; | |
5644 | ||
e1d4d893 | 5645 | /* Check AT&T mnemonic. */ |
a65babc9 | 5646 | i.error = unsupported_with_intel_mnemonic; |
e1d4d893 | 5647 | if (intel_mnemonic && t->opcode_modifier.attmnemonic) |
1efbbeb4 L |
5648 | continue; |
5649 | ||
e92bae62 | 5650 | /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */ |
a65babc9 | 5651 | i.error = unsupported_syntax; |
5c07affc | 5652 | if ((intel_syntax && t->opcode_modifier.attsyntax) |
e92bae62 L |
5653 | || (!intel_syntax && t->opcode_modifier.intelsyntax) |
5654 | || (intel64 && t->opcode_modifier.amd64) | |
5655 | || (!intel64 && t->opcode_modifier.intel64)) | |
1efbbeb4 L |
5656 | continue; |
5657 | ||
20592a94 | 5658 | /* Check the suffix, except for some instructions in intel mode. */ |
a65babc9 | 5659 | i.error = invalid_instruction_suffix; |
567e4e96 L |
5660 | if ((!intel_syntax || !t->opcode_modifier.ignoresize) |
5661 | && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf) | |
5662 | || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf) | |
5663 | || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf) | |
5664 | || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf) | |
5665 | || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf) | |
5666 | || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf))) | |
29b0f896 | 5667 | continue; |
83b16ac6 JB |
5668 | /* In Intel mode all mnemonic suffixes must be explicitly allowed. */ |
5669 | if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf) | |
5670 | || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf) | |
5671 | || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf) | |
5672 | || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf) | |
5673 | || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf) | |
5674 | || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf)) | |
5675 | continue; | |
29b0f896 | 5676 | |
3ac21baa JB |
5677 | size_match = operand_size_match (t); |
5678 | if (!size_match) | |
7d5e4556 | 5679 | continue; |
539e75ad | 5680 | |
5c07affc L |
5681 | for (j = 0; j < MAX_OPERANDS; j++) |
5682 | operand_types[j] = t->operand_types[j]; | |
5683 | ||
45aa61fe AM |
5684 | /* In general, don't allow 64-bit operands in 32-bit mode. */ |
5685 | if (i.suffix == QWORD_MNEM_SUFFIX | |
5686 | && flag_code != CODE_64BIT | |
5687 | && (intel_syntax | |
40fb9820 | 5688 | ? (!t->opcode_modifier.ignoresize |
625cbd7a | 5689 | && !t->opcode_modifier.broadcast |
45aa61fe AM |
5690 | && !intel_float_operand (t->name)) |
5691 | : intel_float_operand (t->name) != 2) | |
40fb9820 | 5692 | && ((!operand_types[0].bitfield.regmmx |
1b54b8d7 | 5693 | && !operand_types[0].bitfield.regsimd) |
40fb9820 | 5694 | || (!operand_types[t->operands > 1].bitfield.regmmx |
1b54b8d7 | 5695 | && !operand_types[t->operands > 1].bitfield.regsimd)) |
45aa61fe AM |
5696 | && (t->base_opcode != 0x0fc7 |
5697 | || t->extension_opcode != 1 /* cmpxchg8b */)) | |
5698 | continue; | |
5699 | ||
192dc9c6 JB |
5700 | /* In general, don't allow 32-bit operands on pre-386. */ |
5701 | else if (i.suffix == LONG_MNEM_SUFFIX | |
5702 | && !cpu_arch_flags.bitfield.cpui386 | |
5703 | && (intel_syntax | |
5704 | ? (!t->opcode_modifier.ignoresize | |
5705 | && !intel_float_operand (t->name)) | |
5706 | : intel_float_operand (t->name) != 2) | |
5707 | && ((!operand_types[0].bitfield.regmmx | |
1b54b8d7 | 5708 | && !operand_types[0].bitfield.regsimd) |
192dc9c6 | 5709 | || (!operand_types[t->operands > 1].bitfield.regmmx |
1b54b8d7 | 5710 | && !operand_types[t->operands > 1].bitfield.regsimd))) |
192dc9c6 JB |
5711 | continue; |
5712 | ||
29b0f896 | 5713 | /* Do not verify operands when there are none. */ |
50aecf8c | 5714 | else |
29b0f896 | 5715 | { |
c6fb90c8 | 5716 | if (!t->operands) |
2dbab7d5 L |
5717 | /* We've found a match; break out of loop. */ |
5718 | break; | |
29b0f896 | 5719 | } |
252b5132 | 5720 | |
539e75ad L |
5721 | /* Address size prefix will turn Disp64/Disp32/Disp16 operand |
5722 | into Disp32/Disp16/Disp32 operand. */ | |
5723 | if (i.prefix[ADDR_PREFIX] != 0) | |
5724 | { | |
40fb9820 | 5725 | /* There should be only one Disp operand. */ |
539e75ad L |
5726 | switch (flag_code) |
5727 | { | |
5728 | case CODE_16BIT: | |
40fb9820 L |
5729 | for (j = 0; j < MAX_OPERANDS; j++) |
5730 | { | |
5731 | if (operand_types[j].bitfield.disp16) | |
5732 | { | |
5733 | addr_prefix_disp = j; | |
5734 | operand_types[j].bitfield.disp32 = 1; | |
5735 | operand_types[j].bitfield.disp16 = 0; | |
5736 | break; | |
5737 | } | |
5738 | } | |
539e75ad L |
5739 | break; |
5740 | case CODE_32BIT: | |
40fb9820 L |
5741 | for (j = 0; j < MAX_OPERANDS; j++) |
5742 | { | |
5743 | if (operand_types[j].bitfield.disp32) | |
5744 | { | |
5745 | addr_prefix_disp = j; | |
5746 | operand_types[j].bitfield.disp32 = 0; | |
5747 | operand_types[j].bitfield.disp16 = 1; | |
5748 | break; | |
5749 | } | |
5750 | } | |
539e75ad L |
5751 | break; |
5752 | case CODE_64BIT: | |
40fb9820 L |
5753 | for (j = 0; j < MAX_OPERANDS; j++) |
5754 | { | |
5755 | if (operand_types[j].bitfield.disp64) | |
5756 | { | |
5757 | addr_prefix_disp = j; | |
5758 | operand_types[j].bitfield.disp64 = 0; | |
5759 | operand_types[j].bitfield.disp32 = 1; | |
5760 | break; | |
5761 | } | |
5762 | } | |
539e75ad L |
5763 | break; |
5764 | } | |
539e75ad L |
5765 | } |
5766 | ||
02a86693 L |
5767 | /* Force 0x8b encoding for "mov foo@GOT, %eax". */ |
5768 | if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0) | |
5769 | continue; | |
5770 | ||
56ffb741 | 5771 | /* We check register size if needed. */ |
e2195274 JB |
5772 | if (t->opcode_modifier.checkregsize) |
5773 | { | |
5774 | check_register = (1 << t->operands) - 1; | |
5775 | if (i.broadcast) | |
5776 | check_register &= ~(1 << i.broadcast->operand); | |
5777 | } | |
5778 | else | |
5779 | check_register = 0; | |
5780 | ||
c6fb90c8 | 5781 | overlap0 = operand_type_and (i.types[0], operand_types[0]); |
29b0f896 AM |
5782 | switch (t->operands) |
5783 | { | |
5784 | case 1: | |
40fb9820 | 5785 | if (!operand_type_match (overlap0, i.types[0])) |
29b0f896 AM |
5786 | continue; |
5787 | break; | |
5788 | case 2: | |
33eaf5de | 5789 | /* xchg %eax, %eax is a special case. It is an alias for nop |
8b38ad71 L |
5790 | only in 32bit mode and we can use opcode 0x90. In 64bit |
5791 | mode, we can't use 0x90 for xchg %eax, %eax since it should | |
5792 | zero-extend %eax to %rax. */ | |
5793 | if (flag_code == CODE_64BIT | |
5794 | && t->base_opcode == 0x90 | |
0dfbf9d7 L |
5795 | && operand_type_equal (&i.types [0], &acc32) |
5796 | && operand_type_equal (&i.types [1], &acc32)) | |
8b38ad71 | 5797 | continue; |
1212781b JB |
5798 | /* xrelease mov %eax, <disp> is another special case. It must not |
5799 | match the accumulator-only encoding of mov. */ | |
5800 | if (flag_code != CODE_64BIT | |
5801 | && i.hle_prefix | |
5802 | && t->base_opcode == 0xa0 | |
5803 | && i.types[0].bitfield.acc | |
5804 | && operand_type_check (i.types[1], anymem)) | |
5805 | continue; | |
f5eb1d70 JB |
5806 | /* Fall through. */ |
5807 | ||
5808 | case 3: | |
3ac21baa JB |
5809 | if (!(size_match & MATCH_STRAIGHT)) |
5810 | goto check_reverse; | |
64c49ab3 JB |
5811 | /* Reverse direction of operands if swapping is possible in the first |
5812 | place (operands need to be symmetric) and | |
5813 | - the load form is requested, and the template is a store form, | |
5814 | - the store form is requested, and the template is a load form, | |
5815 | - the non-default (swapped) form is requested. */ | |
5816 | overlap1 = operand_type_and (operand_types[0], operand_types[1]); | |
f5eb1d70 | 5817 | if (t->opcode_modifier.d && i.reg_operands == i.operands |
64c49ab3 JB |
5818 | && !operand_type_all_zero (&overlap1)) |
5819 | switch (i.dir_encoding) | |
5820 | { | |
5821 | case dir_encoding_load: | |
5822 | if (operand_type_check (operand_types[i.operands - 1], anymem) | |
5823 | || operand_types[i.operands - 1].bitfield.regmem) | |
5824 | goto check_reverse; | |
5825 | break; | |
5826 | ||
5827 | case dir_encoding_store: | |
5828 | if (!operand_type_check (operand_types[i.operands - 1], anymem) | |
5829 | && !operand_types[i.operands - 1].bitfield.regmem) | |
5830 | goto check_reverse; | |
5831 | break; | |
5832 | ||
5833 | case dir_encoding_swap: | |
5834 | goto check_reverse; | |
5835 | ||
5836 | case dir_encoding_default: | |
5837 | break; | |
5838 | } | |
86fa6981 | 5839 | /* If we want store form, we skip the current load. */ |
64c49ab3 JB |
5840 | if ((i.dir_encoding == dir_encoding_store |
5841 | || i.dir_encoding == dir_encoding_swap) | |
86fa6981 L |
5842 | && i.mem_operands == 0 |
5843 | && t->opcode_modifier.load) | |
fa99fab2 | 5844 | continue; |
1a0670f3 | 5845 | /* Fall through. */ |
f48ff2ae | 5846 | case 4: |
c0f3af97 | 5847 | case 5: |
c6fb90c8 | 5848 | overlap1 = operand_type_and (i.types[1], operand_types[1]); |
40fb9820 L |
5849 | if (!operand_type_match (overlap0, i.types[0]) |
5850 | || !operand_type_match (overlap1, i.types[1]) | |
e2195274 | 5851 | || ((check_register & 3) == 3 |
dc821c5f | 5852 | && !operand_type_register_match (i.types[0], |
40fb9820 | 5853 | operand_types[0], |
dc821c5f | 5854 | i.types[1], |
40fb9820 | 5855 | operand_types[1]))) |
29b0f896 AM |
5856 | { |
5857 | /* Check if other direction is valid ... */ | |
38e314eb | 5858 | if (!t->opcode_modifier.d) |
29b0f896 AM |
5859 | continue; |
5860 | ||
b6169b20 | 5861 | check_reverse: |
3ac21baa JB |
5862 | if (!(size_match & MATCH_REVERSE)) |
5863 | continue; | |
29b0f896 | 5864 | /* Try reversing direction of operands. */ |
f5eb1d70 JB |
5865 | overlap0 = operand_type_and (i.types[0], operand_types[i.operands - 1]); |
5866 | overlap1 = operand_type_and (i.types[i.operands - 1], operand_types[0]); | |
40fb9820 | 5867 | if (!operand_type_match (overlap0, i.types[0]) |
f5eb1d70 | 5868 | || !operand_type_match (overlap1, i.types[i.operands - 1]) |
45664ddb | 5869 | || (check_register |
dc821c5f | 5870 | && !operand_type_register_match (i.types[0], |
f5eb1d70 JB |
5871 | operand_types[i.operands - 1], |
5872 | i.types[i.operands - 1], | |
45664ddb | 5873 | operand_types[0]))) |
29b0f896 AM |
5874 | { |
5875 | /* Does not match either direction. */ | |
5876 | continue; | |
5877 | } | |
38e314eb | 5878 | /* found_reverse_match holds which of D or FloatR |
29b0f896 | 5879 | we've found. */ |
38e314eb JB |
5880 | if (!t->opcode_modifier.d) |
5881 | found_reverse_match = 0; | |
5882 | else if (operand_types[0].bitfield.tbyte) | |
8a2ed489 | 5883 | found_reverse_match = Opcode_FloatD; |
dbbc8b7e | 5884 | else if (operand_types[0].bitfield.xmmword |
f5eb1d70 | 5885 | || operand_types[i.operands - 1].bitfield.xmmword |
dbbc8b7e | 5886 | || operand_types[0].bitfield.regmmx |
f5eb1d70 | 5887 | || operand_types[i.operands - 1].bitfield.regmmx |
dbbc8b7e JB |
5888 | || is_any_vex_encoding(t)) |
5889 | found_reverse_match = (t->base_opcode & 0xee) != 0x6e | |
5890 | ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD; | |
8a2ed489 | 5891 | else |
38e314eb | 5892 | found_reverse_match = Opcode_D; |
40fb9820 | 5893 | if (t->opcode_modifier.floatr) |
8a2ed489 | 5894 | found_reverse_match |= Opcode_FloatR; |
29b0f896 | 5895 | } |
f48ff2ae | 5896 | else |
29b0f896 | 5897 | { |
f48ff2ae | 5898 | /* Found a forward 2 operand match here. */ |
d1cbb4db L |
5899 | switch (t->operands) |
5900 | { | |
c0f3af97 L |
5901 | case 5: |
5902 | overlap4 = operand_type_and (i.types[4], | |
5903 | operand_types[4]); | |
1a0670f3 | 5904 | /* Fall through. */ |
d1cbb4db | 5905 | case 4: |
c6fb90c8 L |
5906 | overlap3 = operand_type_and (i.types[3], |
5907 | operand_types[3]); | |
1a0670f3 | 5908 | /* Fall through. */ |
d1cbb4db | 5909 | case 3: |
c6fb90c8 L |
5910 | overlap2 = operand_type_and (i.types[2], |
5911 | operand_types[2]); | |
d1cbb4db L |
5912 | break; |
5913 | } | |
29b0f896 | 5914 | |
f48ff2ae L |
5915 | switch (t->operands) |
5916 | { | |
c0f3af97 L |
5917 | case 5: |
5918 | if (!operand_type_match (overlap4, i.types[4]) | |
dc821c5f | 5919 | || !operand_type_register_match (i.types[3], |
c0f3af97 | 5920 | operand_types[3], |
c0f3af97 L |
5921 | i.types[4], |
5922 | operand_types[4])) | |
5923 | continue; | |
1a0670f3 | 5924 | /* Fall through. */ |
f48ff2ae | 5925 | case 4: |
40fb9820 | 5926 | if (!operand_type_match (overlap3, i.types[3]) |
e2195274 JB |
5927 | || ((check_register & 0xa) == 0xa |
5928 | && !operand_type_register_match (i.types[1], | |
f7768225 JB |
5929 | operand_types[1], |
5930 | i.types[3], | |
e2195274 JB |
5931 | operand_types[3])) |
5932 | || ((check_register & 0xc) == 0xc | |
5933 | && !operand_type_register_match (i.types[2], | |
5934 | operand_types[2], | |
5935 | i.types[3], | |
5936 | operand_types[3]))) | |
f48ff2ae | 5937 | continue; |
1a0670f3 | 5938 | /* Fall through. */ |
f48ff2ae L |
5939 | case 3: |
5940 | /* Here we make use of the fact that there are no | |
23e42951 | 5941 | reverse match 3 operand instructions. */ |
40fb9820 | 5942 | if (!operand_type_match (overlap2, i.types[2]) |
e2195274 JB |
5943 | || ((check_register & 5) == 5 |
5944 | && !operand_type_register_match (i.types[0], | |
23e42951 JB |
5945 | operand_types[0], |
5946 | i.types[2], | |
e2195274 JB |
5947 | operand_types[2])) |
5948 | || ((check_register & 6) == 6 | |
5949 | && !operand_type_register_match (i.types[1], | |
5950 | operand_types[1], | |
5951 | i.types[2], | |
5952 | operand_types[2]))) | |
f48ff2ae L |
5953 | continue; |
5954 | break; | |
5955 | } | |
29b0f896 | 5956 | } |
f48ff2ae | 5957 | /* Found either forward/reverse 2, 3 or 4 operand match here: |
29b0f896 AM |
5958 | slip through to break. */ |
5959 | } | |
3629bb00 | 5960 | if (!found_cpu_match) |
dbbc8b7e | 5961 | continue; |
c0f3af97 | 5962 | |
5614d22c JB |
5963 | /* Check if vector and VEX operands are valid. */ |
5964 | if (check_VecOperands (t) || VEX_check_operands (t)) | |
5965 | { | |
5966 | specific_error = i.error; | |
5967 | continue; | |
5968 | } | |
a683cc34 | 5969 | |
29b0f896 AM |
5970 | /* We've found a match; break out of loop. */ |
5971 | break; | |
5972 | } | |
5973 | ||
5974 | if (t == current_templates->end) | |
5975 | { | |
5976 | /* We found no match. */ | |
a65babc9 | 5977 | const char *err_msg; |
5614d22c | 5978 | switch (specific_error ? specific_error : i.error) |
a65babc9 L |
5979 | { |
5980 | default: | |
5981 | abort (); | |
86e026a4 | 5982 | case operand_size_mismatch: |
a65babc9 L |
5983 | err_msg = _("operand size mismatch"); |
5984 | break; | |
5985 | case operand_type_mismatch: | |
5986 | err_msg = _("operand type mismatch"); | |
5987 | break; | |
5988 | case register_type_mismatch: | |
5989 | err_msg = _("register type mismatch"); | |
5990 | break; | |
5991 | case number_of_operands_mismatch: | |
5992 | err_msg = _("number of operands mismatch"); | |
5993 | break; | |
5994 | case invalid_instruction_suffix: | |
5995 | err_msg = _("invalid instruction suffix"); | |
5996 | break; | |
5997 | case bad_imm4: | |
4a2608e3 | 5998 | err_msg = _("constant doesn't fit in 4 bits"); |
a65babc9 | 5999 | break; |
a65babc9 L |
6000 | case unsupported_with_intel_mnemonic: |
6001 | err_msg = _("unsupported with Intel mnemonic"); | |
6002 | break; | |
6003 | case unsupported_syntax: | |
6004 | err_msg = _("unsupported syntax"); | |
6005 | break; | |
6006 | case unsupported: | |
35262a23 | 6007 | as_bad (_("unsupported instruction `%s'"), |
10efe3f6 L |
6008 | current_templates->start->name); |
6009 | return NULL; | |
6c30d220 L |
6010 | case invalid_vsib_address: |
6011 | err_msg = _("invalid VSIB address"); | |
6012 | break; | |
7bab8ab5 JB |
6013 | case invalid_vector_register_set: |
6014 | err_msg = _("mask, index, and destination registers must be distinct"); | |
6015 | break; | |
6c30d220 L |
6016 | case unsupported_vector_index_register: |
6017 | err_msg = _("unsupported vector index register"); | |
6018 | break; | |
43234a1e L |
6019 | case unsupported_broadcast: |
6020 | err_msg = _("unsupported broadcast"); | |
6021 | break; | |
43234a1e L |
6022 | case broadcast_needed: |
6023 | err_msg = _("broadcast is needed for operand of such type"); | |
6024 | break; | |
6025 | case unsupported_masking: | |
6026 | err_msg = _("unsupported masking"); | |
6027 | break; | |
6028 | case mask_not_on_destination: | |
6029 | err_msg = _("mask not on destination operand"); | |
6030 | break; | |
6031 | case no_default_mask: | |
6032 | err_msg = _("default mask isn't allowed"); | |
6033 | break; | |
6034 | case unsupported_rc_sae: | |
6035 | err_msg = _("unsupported static rounding/sae"); | |
6036 | break; | |
6037 | case rc_sae_operand_not_last_imm: | |
6038 | if (intel_syntax) | |
6039 | err_msg = _("RC/SAE operand must precede immediate operands"); | |
6040 | else | |
6041 | err_msg = _("RC/SAE operand must follow immediate operands"); | |
6042 | break; | |
6043 | case invalid_register_operand: | |
6044 | err_msg = _("invalid register operand"); | |
6045 | break; | |
a65babc9 L |
6046 | } |
6047 | as_bad (_("%s for `%s'"), err_msg, | |
891edac4 | 6048 | current_templates->start->name); |
fa99fab2 | 6049 | return NULL; |
29b0f896 | 6050 | } |
252b5132 | 6051 | |
29b0f896 AM |
6052 | if (!quiet_warnings) |
6053 | { | |
6054 | if (!intel_syntax | |
40fb9820 L |
6055 | && (i.types[0].bitfield.jumpabsolute |
6056 | != operand_types[0].bitfield.jumpabsolute)) | |
29b0f896 AM |
6057 | { |
6058 | as_warn (_("indirect %s without `*'"), t->name); | |
6059 | } | |
6060 | ||
40fb9820 L |
6061 | if (t->opcode_modifier.isprefix |
6062 | && t->opcode_modifier.ignoresize) | |
29b0f896 AM |
6063 | { |
6064 | /* Warn them that a data or address size prefix doesn't | |
6065 | affect assembly of the next line of code. */ | |
6066 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
6067 | } | |
6068 | } | |
6069 | ||
6070 | /* Copy the template we found. */ | |
6071 | i.tm = *t; | |
539e75ad L |
6072 | |
6073 | if (addr_prefix_disp != -1) | |
6074 | i.tm.operand_types[addr_prefix_disp] | |
6075 | = operand_types[addr_prefix_disp]; | |
6076 | ||
29b0f896 AM |
6077 | if (found_reverse_match) |
6078 | { | |
6079 | /* If we found a reverse match we must alter the opcode | |
6080 | direction bit. found_reverse_match holds bits to change | |
6081 | (different for int & float insns). */ | |
6082 | ||
6083 | i.tm.base_opcode ^= found_reverse_match; | |
6084 | ||
f5eb1d70 JB |
6085 | i.tm.operand_types[0] = operand_types[i.operands - 1]; |
6086 | i.tm.operand_types[i.operands - 1] = operand_types[0]; | |
29b0f896 AM |
6087 | } |
6088 | ||
fa99fab2 | 6089 | return t; |
29b0f896 AM |
6090 | } |
6091 | ||
6092 | static int | |
e3bb37b5 | 6093 | check_string (void) |
29b0f896 | 6094 | { |
40fb9820 L |
6095 | int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1; |
6096 | if (i.tm.operand_types[mem_op].bitfield.esseg) | |
29b0f896 AM |
6097 | { |
6098 | if (i.seg[0] != NULL && i.seg[0] != &es) | |
6099 | { | |
a87af027 | 6100 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
29b0f896 | 6101 | i.tm.name, |
a87af027 JB |
6102 | mem_op + 1, |
6103 | register_prefix); | |
29b0f896 AM |
6104 | return 0; |
6105 | } | |
6106 | /* There's only ever one segment override allowed per instruction. | |
6107 | This instruction possibly has a legal segment override on the | |
6108 | second operand, so copy the segment to where non-string | |
6109 | instructions store it, allowing common code. */ | |
6110 | i.seg[0] = i.seg[1]; | |
6111 | } | |
40fb9820 | 6112 | else if (i.tm.operand_types[mem_op + 1].bitfield.esseg) |
29b0f896 AM |
6113 | { |
6114 | if (i.seg[1] != NULL && i.seg[1] != &es) | |
6115 | { | |
a87af027 | 6116 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
29b0f896 | 6117 | i.tm.name, |
a87af027 JB |
6118 | mem_op + 2, |
6119 | register_prefix); | |
29b0f896 AM |
6120 | return 0; |
6121 | } | |
6122 | } | |
6123 | return 1; | |
6124 | } | |
6125 | ||
6126 | static int | |
543613e9 | 6127 | process_suffix (void) |
29b0f896 AM |
6128 | { |
6129 | /* If matched instruction specifies an explicit instruction mnemonic | |
6130 | suffix, use it. */ | |
673fe0f0 | 6131 | if (i.tm.opcode_modifier.size == SIZE16) |
40fb9820 | 6132 | i.suffix = WORD_MNEM_SUFFIX; |
673fe0f0 | 6133 | else if (i.tm.opcode_modifier.size == SIZE32) |
40fb9820 | 6134 | i.suffix = LONG_MNEM_SUFFIX; |
673fe0f0 | 6135 | else if (i.tm.opcode_modifier.size == SIZE64) |
40fb9820 | 6136 | i.suffix = QWORD_MNEM_SUFFIX; |
29b0f896 AM |
6137 | else if (i.reg_operands) |
6138 | { | |
6139 | /* If there's no instruction mnemonic suffix we try to invent one | |
6140 | based on register operands. */ | |
6141 | if (!i.suffix) | |
6142 | { | |
6143 | /* We take i.suffix from the last register operand specified, | |
6144 | Destination register type is more significant than source | |
381d071f L |
6145 | register type. crc32 in SSE4.2 prefers source register |
6146 | type. */ | |
556059dd | 6147 | if (i.tm.base_opcode == 0xf20f38f0 && i.types[0].bitfield.reg) |
381d071f | 6148 | { |
556059dd JB |
6149 | if (i.types[0].bitfield.byte) |
6150 | i.suffix = BYTE_MNEM_SUFFIX; | |
6151 | else if (i.types[0].bitfield.word) | |
40fb9820 | 6152 | i.suffix = WORD_MNEM_SUFFIX; |
556059dd | 6153 | else if (i.types[0].bitfield.dword) |
40fb9820 | 6154 | i.suffix = LONG_MNEM_SUFFIX; |
556059dd | 6155 | else if (i.types[0].bitfield.qword) |
40fb9820 | 6156 | i.suffix = QWORD_MNEM_SUFFIX; |
381d071f L |
6157 | } |
6158 | ||
6159 | if (!i.suffix) | |
6160 | { | |
6161 | int op; | |
6162 | ||
556059dd | 6163 | if (i.tm.base_opcode == 0xf20f38f0) |
20592a94 L |
6164 | { |
6165 | /* We have to know the operand size for crc32. */ | |
6166 | as_bad (_("ambiguous memory operand size for `%s`"), | |
6167 | i.tm.name); | |
6168 | return 0; | |
6169 | } | |
6170 | ||
381d071f | 6171 | for (op = i.operands; --op >= 0;) |
b76bc5d5 JB |
6172 | if (!i.tm.operand_types[op].bitfield.inoutportreg |
6173 | && !i.tm.operand_types[op].bitfield.shiftcount) | |
381d071f | 6174 | { |
8819ada6 JB |
6175 | if (!i.types[op].bitfield.reg) |
6176 | continue; | |
6177 | if (i.types[op].bitfield.byte) | |
6178 | i.suffix = BYTE_MNEM_SUFFIX; | |
6179 | else if (i.types[op].bitfield.word) | |
6180 | i.suffix = WORD_MNEM_SUFFIX; | |
6181 | else if (i.types[op].bitfield.dword) | |
6182 | i.suffix = LONG_MNEM_SUFFIX; | |
6183 | else if (i.types[op].bitfield.qword) | |
6184 | i.suffix = QWORD_MNEM_SUFFIX; | |
6185 | else | |
6186 | continue; | |
6187 | break; | |
381d071f L |
6188 | } |
6189 | } | |
29b0f896 AM |
6190 | } |
6191 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
6192 | { | |
2eb952a4 L |
6193 | if (intel_syntax |
6194 | && i.tm.opcode_modifier.ignoresize | |
6195 | && i.tm.opcode_modifier.no_bsuf) | |
6196 | i.suffix = 0; | |
6197 | else if (!check_byte_reg ()) | |
29b0f896 AM |
6198 | return 0; |
6199 | } | |
6200 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
6201 | { | |
2eb952a4 L |
6202 | if (intel_syntax |
6203 | && i.tm.opcode_modifier.ignoresize | |
9f123b91 JB |
6204 | && i.tm.opcode_modifier.no_lsuf |
6205 | && !i.tm.opcode_modifier.todword | |
6206 | && !i.tm.opcode_modifier.toqword) | |
2eb952a4 L |
6207 | i.suffix = 0; |
6208 | else if (!check_long_reg ()) | |
29b0f896 AM |
6209 | return 0; |
6210 | } | |
6211 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
6212 | { | |
955e1e6a L |
6213 | if (intel_syntax |
6214 | && i.tm.opcode_modifier.ignoresize | |
9f123b91 JB |
6215 | && i.tm.opcode_modifier.no_qsuf |
6216 | && !i.tm.opcode_modifier.todword | |
6217 | && !i.tm.opcode_modifier.toqword) | |
955e1e6a L |
6218 | i.suffix = 0; |
6219 | else if (!check_qword_reg ()) | |
29b0f896 AM |
6220 | return 0; |
6221 | } | |
6222 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
6223 | { | |
2eb952a4 L |
6224 | if (intel_syntax |
6225 | && i.tm.opcode_modifier.ignoresize | |
6226 | && i.tm.opcode_modifier.no_wsuf) | |
6227 | i.suffix = 0; | |
6228 | else if (!check_word_reg ()) | |
29b0f896 AM |
6229 | return 0; |
6230 | } | |
40fb9820 | 6231 | else if (intel_syntax && i.tm.opcode_modifier.ignoresize) |
29b0f896 AM |
6232 | /* Do nothing if the instruction is going to ignore the prefix. */ |
6233 | ; | |
6234 | else | |
6235 | abort (); | |
6236 | } | |
40fb9820 | 6237 | else if (i.tm.opcode_modifier.defaultsize |
9306ca4a JB |
6238 | && !i.suffix |
6239 | /* exclude fldenv/frstor/fsave/fstenv */ | |
40fb9820 | 6240 | && i.tm.opcode_modifier.no_ssuf) |
29b0f896 AM |
6241 | { |
6242 | i.suffix = stackop_size; | |
6243 | } | |
9306ca4a JB |
6244 | else if (intel_syntax |
6245 | && !i.suffix | |
40fb9820 L |
6246 | && (i.tm.operand_types[0].bitfield.jumpabsolute |
6247 | || i.tm.opcode_modifier.jumpbyte | |
6248 | || i.tm.opcode_modifier.jumpintersegment | |
64e74474 AM |
6249 | || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */ |
6250 | && i.tm.extension_opcode <= 3))) | |
9306ca4a JB |
6251 | { |
6252 | switch (flag_code) | |
6253 | { | |
6254 | case CODE_64BIT: | |
40fb9820 | 6255 | if (!i.tm.opcode_modifier.no_qsuf) |
9306ca4a JB |
6256 | { |
6257 | i.suffix = QWORD_MNEM_SUFFIX; | |
6258 | break; | |
6259 | } | |
1a0670f3 | 6260 | /* Fall through. */ |
9306ca4a | 6261 | case CODE_32BIT: |
40fb9820 | 6262 | if (!i.tm.opcode_modifier.no_lsuf) |
9306ca4a JB |
6263 | i.suffix = LONG_MNEM_SUFFIX; |
6264 | break; | |
6265 | case CODE_16BIT: | |
40fb9820 | 6266 | if (!i.tm.opcode_modifier.no_wsuf) |
9306ca4a JB |
6267 | i.suffix = WORD_MNEM_SUFFIX; |
6268 | break; | |
6269 | } | |
6270 | } | |
252b5132 | 6271 | |
9306ca4a | 6272 | if (!i.suffix) |
29b0f896 | 6273 | { |
9306ca4a JB |
6274 | if (!intel_syntax) |
6275 | { | |
40fb9820 | 6276 | if (i.tm.opcode_modifier.w) |
9306ca4a | 6277 | { |
4eed87de AM |
6278 | as_bad (_("no instruction mnemonic suffix given and " |
6279 | "no register operands; can't size instruction")); | |
9306ca4a JB |
6280 | return 0; |
6281 | } | |
6282 | } | |
6283 | else | |
6284 | { | |
40fb9820 | 6285 | unsigned int suffixes; |
7ab9ffdd | 6286 | |
40fb9820 L |
6287 | suffixes = !i.tm.opcode_modifier.no_bsuf; |
6288 | if (!i.tm.opcode_modifier.no_wsuf) | |
6289 | suffixes |= 1 << 1; | |
6290 | if (!i.tm.opcode_modifier.no_lsuf) | |
6291 | suffixes |= 1 << 2; | |
fc4adea1 | 6292 | if (!i.tm.opcode_modifier.no_ldsuf) |
40fb9820 L |
6293 | suffixes |= 1 << 3; |
6294 | if (!i.tm.opcode_modifier.no_ssuf) | |
6295 | suffixes |= 1 << 4; | |
c2b9da16 | 6296 | if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf) |
40fb9820 L |
6297 | suffixes |= 1 << 5; |
6298 | ||
6299 | /* There are more than suffix matches. */ | |
6300 | if (i.tm.opcode_modifier.w | |
9306ca4a | 6301 | || ((suffixes & (suffixes - 1)) |
40fb9820 L |
6302 | && !i.tm.opcode_modifier.defaultsize |
6303 | && !i.tm.opcode_modifier.ignoresize)) | |
9306ca4a JB |
6304 | { |
6305 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); | |
6306 | return 0; | |
6307 | } | |
6308 | } | |
29b0f896 | 6309 | } |
252b5132 | 6310 | |
d2224064 JB |
6311 | /* Change the opcode based on the operand size given by i.suffix. */ |
6312 | switch (i.suffix) | |
29b0f896 | 6313 | { |
d2224064 JB |
6314 | /* Size floating point instruction. */ |
6315 | case LONG_MNEM_SUFFIX: | |
6316 | if (i.tm.opcode_modifier.floatmf) | |
6317 | { | |
6318 | i.tm.base_opcode ^= 4; | |
6319 | break; | |
6320 | } | |
6321 | /* fall through */ | |
6322 | case WORD_MNEM_SUFFIX: | |
6323 | case QWORD_MNEM_SUFFIX: | |
29b0f896 | 6324 | /* It's not a byte, select word/dword operation. */ |
40fb9820 | 6325 | if (i.tm.opcode_modifier.w) |
29b0f896 | 6326 | { |
40fb9820 | 6327 | if (i.tm.opcode_modifier.shortform) |
29b0f896 AM |
6328 | i.tm.base_opcode |= 8; |
6329 | else | |
6330 | i.tm.base_opcode |= 1; | |
6331 | } | |
d2224064 JB |
6332 | /* fall through */ |
6333 | case SHORT_MNEM_SUFFIX: | |
29b0f896 AM |
6334 | /* Now select between word & dword operations via the operand |
6335 | size prefix, except for instructions that will ignore this | |
6336 | prefix anyway. */ | |
75c0a438 L |
6337 | if (i.reg_operands > 0 |
6338 | && i.types[0].bitfield.reg | |
6339 | && i.tm.opcode_modifier.addrprefixopreg | |
6340 | && (i.tm.opcode_modifier.immext | |
6341 | || i.operands == 1)) | |
cb712a9e | 6342 | { |
ca61edf2 L |
6343 | /* The address size override prefix changes the size of the |
6344 | first operand. */ | |
40fb9820 | 6345 | if ((flag_code == CODE_32BIT |
75c0a438 | 6346 | && i.op[0].regs->reg_type.bitfield.word) |
40fb9820 | 6347 | || (flag_code != CODE_32BIT |
75c0a438 | 6348 | && i.op[0].regs->reg_type.bitfield.dword)) |
cb712a9e L |
6349 | if (!add_prefix (ADDR_PREFIX_OPCODE)) |
6350 | return 0; | |
6351 | } | |
6352 | else if (i.suffix != QWORD_MNEM_SUFFIX | |
40fb9820 L |
6353 | && !i.tm.opcode_modifier.ignoresize |
6354 | && !i.tm.opcode_modifier.floatmf | |
7a8655d2 JB |
6355 | && !i.tm.opcode_modifier.vex |
6356 | && !i.tm.opcode_modifier.vexopcode | |
6357 | && !is_evex_encoding (&i.tm) | |
cb712a9e L |
6358 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) |
6359 | || (flag_code == CODE_64BIT | |
40fb9820 | 6360 | && i.tm.opcode_modifier.jumpbyte))) |
24eab124 AM |
6361 | { |
6362 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
543613e9 | 6363 | |
40fb9820 | 6364 | if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */ |
29b0f896 | 6365 | prefix = ADDR_PREFIX_OPCODE; |
252b5132 | 6366 | |
29b0f896 AM |
6367 | if (!add_prefix (prefix)) |
6368 | return 0; | |
24eab124 | 6369 | } |
252b5132 | 6370 | |
29b0f896 AM |
6371 | /* Set mode64 for an operand. */ |
6372 | if (i.suffix == QWORD_MNEM_SUFFIX | |
9146926a | 6373 | && flag_code == CODE_64BIT |
d2224064 | 6374 | && !i.tm.opcode_modifier.norex64 |
46e883c5 | 6375 | /* Special case for xchg %rax,%rax. It is NOP and doesn't |
d2224064 JB |
6376 | need rex64. */ |
6377 | && ! (i.operands == 2 | |
6378 | && i.tm.base_opcode == 0x90 | |
6379 | && i.tm.extension_opcode == None | |
6380 | && operand_type_equal (&i.types [0], &acc64) | |
6381 | && operand_type_equal (&i.types [1], &acc64))) | |
6382 | i.rex |= REX_W; | |
3e73aa7c | 6383 | |
d2224064 | 6384 | break; |
29b0f896 | 6385 | } |
7ecd2f8b | 6386 | |
c0a30a9f L |
6387 | if (i.reg_operands != 0 |
6388 | && i.operands > 1 | |
6389 | && i.tm.opcode_modifier.addrprefixopreg | |
6390 | && !i.tm.opcode_modifier.immext) | |
6391 | { | |
6392 | /* Check invalid register operand when the address size override | |
6393 | prefix changes the size of register operands. */ | |
6394 | unsigned int op; | |
6395 | enum { need_word, need_dword, need_qword } need; | |
6396 | ||
6397 | if (flag_code == CODE_32BIT) | |
6398 | need = i.prefix[ADDR_PREFIX] ? need_word : need_dword; | |
6399 | else | |
6400 | { | |
6401 | if (i.prefix[ADDR_PREFIX]) | |
6402 | need = need_dword; | |
6403 | else | |
6404 | need = flag_code == CODE_64BIT ? need_qword : need_word; | |
6405 | } | |
6406 | ||
6407 | for (op = 0; op < i.operands; op++) | |
6408 | if (i.types[op].bitfield.reg | |
6409 | && ((need == need_word | |
6410 | && !i.op[op].regs->reg_type.bitfield.word) | |
6411 | || (need == need_dword | |
6412 | && !i.op[op].regs->reg_type.bitfield.dword) | |
6413 | || (need == need_qword | |
6414 | && !i.op[op].regs->reg_type.bitfield.qword))) | |
6415 | { | |
6416 | as_bad (_("invalid register operand size for `%s'"), | |
6417 | i.tm.name); | |
6418 | return 0; | |
6419 | } | |
6420 | } | |
6421 | ||
29b0f896 AM |
6422 | return 1; |
6423 | } | |
3e73aa7c | 6424 | |
29b0f896 | 6425 | static int |
543613e9 | 6426 | check_byte_reg (void) |
29b0f896 AM |
6427 | { |
6428 | int op; | |
543613e9 | 6429 | |
29b0f896 AM |
6430 | for (op = i.operands; --op >= 0;) |
6431 | { | |
dc821c5f JB |
6432 | /* Skip non-register operands. */ |
6433 | if (!i.types[op].bitfield.reg) | |
6434 | continue; | |
6435 | ||
29b0f896 AM |
6436 | /* If this is an eight bit register, it's OK. If it's the 16 or |
6437 | 32 bit version of an eight bit register, we will just use the | |
6438 | low portion, and that's OK too. */ | |
dc821c5f | 6439 | if (i.types[op].bitfield.byte) |
29b0f896 AM |
6440 | continue; |
6441 | ||
5a819eb9 JB |
6442 | /* I/O port address operands are OK too. */ |
6443 | if (i.tm.operand_types[op].bitfield.inoutportreg) | |
6444 | continue; | |
6445 | ||
9344ff29 L |
6446 | /* crc32 doesn't generate this warning. */ |
6447 | if (i.tm.base_opcode == 0xf20f38f0) | |
6448 | continue; | |
6449 | ||
dc821c5f JB |
6450 | if ((i.types[op].bitfield.word |
6451 | || i.types[op].bitfield.dword | |
6452 | || i.types[op].bitfield.qword) | |
5a819eb9 JB |
6453 | && i.op[op].regs->reg_num < 4 |
6454 | /* Prohibit these changes in 64bit mode, since the lowering | |
6455 | would be more complicated. */ | |
6456 | && flag_code != CODE_64BIT) | |
29b0f896 | 6457 | { |
29b0f896 | 6458 | #if REGISTER_WARNINGS |
5a819eb9 | 6459 | if (!quiet_warnings) |
a540244d L |
6460 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
6461 | register_prefix, | |
dc821c5f | 6462 | (i.op[op].regs + (i.types[op].bitfield.word |
29b0f896 AM |
6463 | ? REGNAM_AL - REGNAM_AX |
6464 | : REGNAM_AL - REGNAM_EAX))->reg_name, | |
a540244d | 6465 | register_prefix, |
29b0f896 AM |
6466 | i.op[op].regs->reg_name, |
6467 | i.suffix); | |
6468 | #endif | |
6469 | continue; | |
6470 | } | |
6471 | /* Any other register is bad. */ | |
dc821c5f | 6472 | if (i.types[op].bitfield.reg |
40fb9820 | 6473 | || i.types[op].bitfield.regmmx |
1b54b8d7 | 6474 | || i.types[op].bitfield.regsimd |
40fb9820 L |
6475 | || i.types[op].bitfield.sreg2 |
6476 | || i.types[op].bitfield.sreg3 | |
6477 | || i.types[op].bitfield.control | |
6478 | || i.types[op].bitfield.debug | |
ca0d63fe | 6479 | || i.types[op].bitfield.test) |
29b0f896 | 6480 | { |
a540244d L |
6481 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6482 | register_prefix, | |
29b0f896 AM |
6483 | i.op[op].regs->reg_name, |
6484 | i.tm.name, | |
6485 | i.suffix); | |
6486 | return 0; | |
6487 | } | |
6488 | } | |
6489 | return 1; | |
6490 | } | |
6491 | ||
6492 | static int | |
e3bb37b5 | 6493 | check_long_reg (void) |
29b0f896 AM |
6494 | { |
6495 | int op; | |
6496 | ||
6497 | for (op = i.operands; --op >= 0;) | |
dc821c5f JB |
6498 | /* Skip non-register operands. */ |
6499 | if (!i.types[op].bitfield.reg) | |
6500 | continue; | |
29b0f896 AM |
6501 | /* Reject eight bit registers, except where the template requires |
6502 | them. (eg. movzb) */ | |
dc821c5f JB |
6503 | else if (i.types[op].bitfield.byte |
6504 | && (i.tm.operand_types[op].bitfield.reg | |
6505 | || i.tm.operand_types[op].bitfield.acc) | |
6506 | && (i.tm.operand_types[op].bitfield.word | |
6507 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 6508 | { |
a540244d L |
6509 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6510 | register_prefix, | |
29b0f896 AM |
6511 | i.op[op].regs->reg_name, |
6512 | i.tm.name, | |
6513 | i.suffix); | |
6514 | return 0; | |
6515 | } | |
e4630f71 | 6516 | /* Warn if the e prefix on a general reg is missing. */ |
29b0f896 | 6517 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
dc821c5f JB |
6518 | && i.types[op].bitfield.word |
6519 | && (i.tm.operand_types[op].bitfield.reg | |
6520 | || i.tm.operand_types[op].bitfield.acc) | |
6521 | && i.tm.operand_types[op].bitfield.dword) | |
29b0f896 AM |
6522 | { |
6523 | /* Prohibit these changes in the 64bit mode, since the | |
6524 | lowering is more complicated. */ | |
6525 | if (flag_code == CODE_64BIT) | |
252b5132 | 6526 | { |
2b5d6a91 | 6527 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
2ca3ace5 | 6528 | register_prefix, i.op[op].regs->reg_name, |
29b0f896 AM |
6529 | i.suffix); |
6530 | return 0; | |
252b5132 | 6531 | } |
29b0f896 | 6532 | #if REGISTER_WARNINGS |
cecf1424 JB |
6533 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
6534 | register_prefix, | |
6535 | (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name, | |
6536 | register_prefix, i.op[op].regs->reg_name, i.suffix); | |
29b0f896 | 6537 | #endif |
252b5132 | 6538 | } |
e4630f71 | 6539 | /* Warn if the r prefix on a general reg is present. */ |
dc821c5f JB |
6540 | else if (i.types[op].bitfield.qword |
6541 | && (i.tm.operand_types[op].bitfield.reg | |
6542 | || i.tm.operand_types[op].bitfield.acc) | |
6543 | && i.tm.operand_types[op].bitfield.dword) | |
252b5132 | 6544 | { |
34828aad | 6545 | if (intel_syntax |
ca61edf2 | 6546 | && i.tm.opcode_modifier.toqword |
1b54b8d7 | 6547 | && !i.types[0].bitfield.regsimd) |
34828aad | 6548 | { |
ca61edf2 | 6549 | /* Convert to QWORD. We want REX byte. */ |
34828aad L |
6550 | i.suffix = QWORD_MNEM_SUFFIX; |
6551 | } | |
6552 | else | |
6553 | { | |
2b5d6a91 | 6554 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
6555 | register_prefix, i.op[op].regs->reg_name, |
6556 | i.suffix); | |
6557 | return 0; | |
6558 | } | |
29b0f896 AM |
6559 | } |
6560 | return 1; | |
6561 | } | |
252b5132 | 6562 | |
29b0f896 | 6563 | static int |
e3bb37b5 | 6564 | check_qword_reg (void) |
29b0f896 AM |
6565 | { |
6566 | int op; | |
252b5132 | 6567 | |
29b0f896 | 6568 | for (op = i.operands; --op >= 0; ) |
dc821c5f JB |
6569 | /* Skip non-register operands. */ |
6570 | if (!i.types[op].bitfield.reg) | |
6571 | continue; | |
29b0f896 AM |
6572 | /* Reject eight bit registers, except where the template requires |
6573 | them. (eg. movzb) */ | |
dc821c5f JB |
6574 | else if (i.types[op].bitfield.byte |
6575 | && (i.tm.operand_types[op].bitfield.reg | |
6576 | || i.tm.operand_types[op].bitfield.acc) | |
6577 | && (i.tm.operand_types[op].bitfield.word | |
6578 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 6579 | { |
a540244d L |
6580 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6581 | register_prefix, | |
29b0f896 AM |
6582 | i.op[op].regs->reg_name, |
6583 | i.tm.name, | |
6584 | i.suffix); | |
6585 | return 0; | |
6586 | } | |
e4630f71 | 6587 | /* Warn if the r prefix on a general reg is missing. */ |
dc821c5f JB |
6588 | else if ((i.types[op].bitfield.word |
6589 | || i.types[op].bitfield.dword) | |
6590 | && (i.tm.operand_types[op].bitfield.reg | |
6591 | || i.tm.operand_types[op].bitfield.acc) | |
6592 | && i.tm.operand_types[op].bitfield.qword) | |
29b0f896 AM |
6593 | { |
6594 | /* Prohibit these changes in the 64bit mode, since the | |
6595 | lowering is more complicated. */ | |
34828aad | 6596 | if (intel_syntax |
ca61edf2 | 6597 | && i.tm.opcode_modifier.todword |
1b54b8d7 | 6598 | && !i.types[0].bitfield.regsimd) |
34828aad | 6599 | { |
ca61edf2 | 6600 | /* Convert to DWORD. We don't want REX byte. */ |
34828aad L |
6601 | i.suffix = LONG_MNEM_SUFFIX; |
6602 | } | |
6603 | else | |
6604 | { | |
2b5d6a91 | 6605 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
6606 | register_prefix, i.op[op].regs->reg_name, |
6607 | i.suffix); | |
6608 | return 0; | |
6609 | } | |
252b5132 | 6610 | } |
29b0f896 AM |
6611 | return 1; |
6612 | } | |
252b5132 | 6613 | |
29b0f896 | 6614 | static int |
e3bb37b5 | 6615 | check_word_reg (void) |
29b0f896 AM |
6616 | { |
6617 | int op; | |
6618 | for (op = i.operands; --op >= 0;) | |
dc821c5f JB |
6619 | /* Skip non-register operands. */ |
6620 | if (!i.types[op].bitfield.reg) | |
6621 | continue; | |
29b0f896 AM |
6622 | /* Reject eight bit registers, except where the template requires |
6623 | them. (eg. movzb) */ | |
dc821c5f JB |
6624 | else if (i.types[op].bitfield.byte |
6625 | && (i.tm.operand_types[op].bitfield.reg | |
6626 | || i.tm.operand_types[op].bitfield.acc) | |
6627 | && (i.tm.operand_types[op].bitfield.word | |
6628 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 6629 | { |
a540244d L |
6630 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6631 | register_prefix, | |
29b0f896 AM |
6632 | i.op[op].regs->reg_name, |
6633 | i.tm.name, | |
6634 | i.suffix); | |
6635 | return 0; | |
6636 | } | |
e4630f71 | 6637 | /* Warn if the e or r prefix on a general reg is present. */ |
29b0f896 | 6638 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
dc821c5f JB |
6639 | && (i.types[op].bitfield.dword |
6640 | || i.types[op].bitfield.qword) | |
6641 | && (i.tm.operand_types[op].bitfield.reg | |
6642 | || i.tm.operand_types[op].bitfield.acc) | |
6643 | && i.tm.operand_types[op].bitfield.word) | |
252b5132 | 6644 | { |
29b0f896 AM |
6645 | /* Prohibit these changes in the 64bit mode, since the |
6646 | lowering is more complicated. */ | |
6647 | if (flag_code == CODE_64BIT) | |
252b5132 | 6648 | { |
2b5d6a91 | 6649 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
2ca3ace5 | 6650 | register_prefix, i.op[op].regs->reg_name, |
29b0f896 AM |
6651 | i.suffix); |
6652 | return 0; | |
252b5132 | 6653 | } |
29b0f896 | 6654 | #if REGISTER_WARNINGS |
cecf1424 JB |
6655 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
6656 | register_prefix, | |
6657 | (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name, | |
6658 | register_prefix, i.op[op].regs->reg_name, i.suffix); | |
29b0f896 AM |
6659 | #endif |
6660 | } | |
6661 | return 1; | |
6662 | } | |
252b5132 | 6663 | |
29b0f896 | 6664 | static int |
40fb9820 | 6665 | update_imm (unsigned int j) |
29b0f896 | 6666 | { |
bc0844ae | 6667 | i386_operand_type overlap = i.types[j]; |
40fb9820 L |
6668 | if ((overlap.bitfield.imm8 |
6669 | || overlap.bitfield.imm8s | |
6670 | || overlap.bitfield.imm16 | |
6671 | || overlap.bitfield.imm32 | |
6672 | || overlap.bitfield.imm32s | |
6673 | || overlap.bitfield.imm64) | |
0dfbf9d7 L |
6674 | && !operand_type_equal (&overlap, &imm8) |
6675 | && !operand_type_equal (&overlap, &imm8s) | |
6676 | && !operand_type_equal (&overlap, &imm16) | |
6677 | && !operand_type_equal (&overlap, &imm32) | |
6678 | && !operand_type_equal (&overlap, &imm32s) | |
6679 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 AM |
6680 | { |
6681 | if (i.suffix) | |
6682 | { | |
40fb9820 L |
6683 | i386_operand_type temp; |
6684 | ||
0dfbf9d7 | 6685 | operand_type_set (&temp, 0); |
7ab9ffdd | 6686 | if (i.suffix == BYTE_MNEM_SUFFIX) |
40fb9820 L |
6687 | { |
6688 | temp.bitfield.imm8 = overlap.bitfield.imm8; | |
6689 | temp.bitfield.imm8s = overlap.bitfield.imm8s; | |
6690 | } | |
6691 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
6692 | temp.bitfield.imm16 = overlap.bitfield.imm16; | |
6693 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
6694 | { | |
6695 | temp.bitfield.imm64 = overlap.bitfield.imm64; | |
6696 | temp.bitfield.imm32s = overlap.bitfield.imm32s; | |
6697 | } | |
6698 | else | |
6699 | temp.bitfield.imm32 = overlap.bitfield.imm32; | |
6700 | overlap = temp; | |
29b0f896 | 6701 | } |
0dfbf9d7 L |
6702 | else if (operand_type_equal (&overlap, &imm16_32_32s) |
6703 | || operand_type_equal (&overlap, &imm16_32) | |
6704 | || operand_type_equal (&overlap, &imm16_32s)) | |
29b0f896 | 6705 | { |
40fb9820 | 6706 | if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
65da13b5 | 6707 | overlap = imm16; |
40fb9820 | 6708 | else |
65da13b5 | 6709 | overlap = imm32s; |
29b0f896 | 6710 | } |
0dfbf9d7 L |
6711 | if (!operand_type_equal (&overlap, &imm8) |
6712 | && !operand_type_equal (&overlap, &imm8s) | |
6713 | && !operand_type_equal (&overlap, &imm16) | |
6714 | && !operand_type_equal (&overlap, &imm32) | |
6715 | && !operand_type_equal (&overlap, &imm32s) | |
6716 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 | 6717 | { |
4eed87de AM |
6718 | as_bad (_("no instruction mnemonic suffix given; " |
6719 | "can't determine immediate size")); | |
29b0f896 AM |
6720 | return 0; |
6721 | } | |
6722 | } | |
40fb9820 | 6723 | i.types[j] = overlap; |
29b0f896 | 6724 | |
40fb9820 L |
6725 | return 1; |
6726 | } | |
6727 | ||
6728 | static int | |
6729 | finalize_imm (void) | |
6730 | { | |
bc0844ae | 6731 | unsigned int j, n; |
29b0f896 | 6732 | |
bc0844ae L |
6733 | /* Update the first 2 immediate operands. */ |
6734 | n = i.operands > 2 ? 2 : i.operands; | |
6735 | if (n) | |
6736 | { | |
6737 | for (j = 0; j < n; j++) | |
6738 | if (update_imm (j) == 0) | |
6739 | return 0; | |
40fb9820 | 6740 | |
bc0844ae L |
6741 | /* The 3rd operand can't be immediate operand. */ |
6742 | gas_assert (operand_type_check (i.types[2], imm) == 0); | |
6743 | } | |
29b0f896 AM |
6744 | |
6745 | return 1; | |
6746 | } | |
6747 | ||
6748 | static int | |
e3bb37b5 | 6749 | process_operands (void) |
29b0f896 AM |
6750 | { |
6751 | /* Default segment register this instruction will use for memory | |
6752 | accesses. 0 means unknown. This is only for optimizing out | |
6753 | unnecessary segment overrides. */ | |
6754 | const seg_entry *default_seg = 0; | |
6755 | ||
2426c15f | 6756 | if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv) |
29b0f896 | 6757 | { |
91d6fa6a NC |
6758 | unsigned int dupl = i.operands; |
6759 | unsigned int dest = dupl - 1; | |
9fcfb3d7 L |
6760 | unsigned int j; |
6761 | ||
c0f3af97 | 6762 | /* The destination must be an xmm register. */ |
9c2799c2 | 6763 | gas_assert (i.reg_operands |
91d6fa6a | 6764 | && MAX_OPERANDS > dupl |
7ab9ffdd | 6765 | && operand_type_equal (&i.types[dest], ®xmm)); |
c0f3af97 | 6766 | |
1b54b8d7 JB |
6767 | if (i.tm.operand_types[0].bitfield.acc |
6768 | && i.tm.operand_types[0].bitfield.xmmword) | |
e2ec9d29 | 6769 | { |
8cd7925b | 6770 | if (i.tm.opcode_modifier.vexsources == VEX3SOURCES) |
c0f3af97 L |
6771 | { |
6772 | /* Keep xmm0 for instructions with VEX prefix and 3 | |
6773 | sources. */ | |
1b54b8d7 JB |
6774 | i.tm.operand_types[0].bitfield.acc = 0; |
6775 | i.tm.operand_types[0].bitfield.regsimd = 1; | |
c0f3af97 L |
6776 | goto duplicate; |
6777 | } | |
e2ec9d29 | 6778 | else |
c0f3af97 L |
6779 | { |
6780 | /* We remove the first xmm0 and keep the number of | |
6781 | operands unchanged, which in fact duplicates the | |
6782 | destination. */ | |
6783 | for (j = 1; j < i.operands; j++) | |
6784 | { | |
6785 | i.op[j - 1] = i.op[j]; | |
6786 | i.types[j - 1] = i.types[j]; | |
6787 | i.tm.operand_types[j - 1] = i.tm.operand_types[j]; | |
6788 | } | |
6789 | } | |
6790 | } | |
6791 | else if (i.tm.opcode_modifier.implicit1stxmm0) | |
7ab9ffdd | 6792 | { |
91d6fa6a | 6793 | gas_assert ((MAX_OPERANDS - 1) > dupl |
8cd7925b L |
6794 | && (i.tm.opcode_modifier.vexsources |
6795 | == VEX3SOURCES)); | |
c0f3af97 L |
6796 | |
6797 | /* Add the implicit xmm0 for instructions with VEX prefix | |
6798 | and 3 sources. */ | |
6799 | for (j = i.operands; j > 0; j--) | |
6800 | { | |
6801 | i.op[j] = i.op[j - 1]; | |
6802 | i.types[j] = i.types[j - 1]; | |
6803 | i.tm.operand_types[j] = i.tm.operand_types[j - 1]; | |
6804 | } | |
6805 | i.op[0].regs | |
6806 | = (const reg_entry *) hash_find (reg_hash, "xmm0"); | |
7ab9ffdd | 6807 | i.types[0] = regxmm; |
c0f3af97 L |
6808 | i.tm.operand_types[0] = regxmm; |
6809 | ||
6810 | i.operands += 2; | |
6811 | i.reg_operands += 2; | |
6812 | i.tm.operands += 2; | |
6813 | ||
91d6fa6a | 6814 | dupl++; |
c0f3af97 | 6815 | dest++; |
91d6fa6a NC |
6816 | i.op[dupl] = i.op[dest]; |
6817 | i.types[dupl] = i.types[dest]; | |
6818 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
e2ec9d29 | 6819 | } |
c0f3af97 L |
6820 | else |
6821 | { | |
6822 | duplicate: | |
6823 | i.operands++; | |
6824 | i.reg_operands++; | |
6825 | i.tm.operands++; | |
6826 | ||
91d6fa6a NC |
6827 | i.op[dupl] = i.op[dest]; |
6828 | i.types[dupl] = i.types[dest]; | |
6829 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
c0f3af97 L |
6830 | } |
6831 | ||
6832 | if (i.tm.opcode_modifier.immext) | |
6833 | process_immext (); | |
6834 | } | |
1b54b8d7 JB |
6835 | else if (i.tm.operand_types[0].bitfield.acc |
6836 | && i.tm.operand_types[0].bitfield.xmmword) | |
c0f3af97 L |
6837 | { |
6838 | unsigned int j; | |
6839 | ||
9fcfb3d7 L |
6840 | for (j = 1; j < i.operands; j++) |
6841 | { | |
6842 | i.op[j - 1] = i.op[j]; | |
6843 | i.types[j - 1] = i.types[j]; | |
6844 | ||
6845 | /* We need to adjust fields in i.tm since they are used by | |
6846 | build_modrm_byte. */ | |
6847 | i.tm.operand_types [j - 1] = i.tm.operand_types [j]; | |
6848 | } | |
6849 | ||
e2ec9d29 L |
6850 | i.operands--; |
6851 | i.reg_operands--; | |
e2ec9d29 L |
6852 | i.tm.operands--; |
6853 | } | |
920d2ddc IT |
6854 | else if (i.tm.opcode_modifier.implicitquadgroup) |
6855 | { | |
a477a8c4 JB |
6856 | unsigned int regnum, first_reg_in_group, last_reg_in_group; |
6857 | ||
920d2ddc | 6858 | /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */ |
10c17abd | 6859 | gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd); |
a477a8c4 JB |
6860 | regnum = register_number (i.op[1].regs); |
6861 | first_reg_in_group = regnum & ~3; | |
6862 | last_reg_in_group = first_reg_in_group + 3; | |
6863 | if (regnum != first_reg_in_group) | |
6864 | as_warn (_("source register `%s%s' implicitly denotes" | |
6865 | " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"), | |
6866 | register_prefix, i.op[1].regs->reg_name, | |
6867 | register_prefix, i.op[1].regs->reg_name, first_reg_in_group, | |
6868 | register_prefix, i.op[1].regs->reg_name, last_reg_in_group, | |
6869 | i.tm.name); | |
6870 | } | |
e2ec9d29 L |
6871 | else if (i.tm.opcode_modifier.regkludge) |
6872 | { | |
6873 | /* The imul $imm, %reg instruction is converted into | |
6874 | imul $imm, %reg, %reg, and the clr %reg instruction | |
6875 | is converted into xor %reg, %reg. */ | |
6876 | ||
6877 | unsigned int first_reg_op; | |
6878 | ||
6879 | if (operand_type_check (i.types[0], reg)) | |
6880 | first_reg_op = 0; | |
6881 | else | |
6882 | first_reg_op = 1; | |
6883 | /* Pretend we saw the extra register operand. */ | |
9c2799c2 | 6884 | gas_assert (i.reg_operands == 1 |
7ab9ffdd | 6885 | && i.op[first_reg_op + 1].regs == 0); |
e2ec9d29 L |
6886 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; |
6887 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
6888 | i.operands++; | |
6889 | i.reg_operands++; | |
29b0f896 AM |
6890 | } |
6891 | ||
40fb9820 | 6892 | if (i.tm.opcode_modifier.shortform) |
29b0f896 | 6893 | { |
40fb9820 L |
6894 | if (i.types[0].bitfield.sreg2 |
6895 | || i.types[0].bitfield.sreg3) | |
29b0f896 | 6896 | { |
4eed87de AM |
6897 | if (i.tm.base_opcode == POP_SEG_SHORT |
6898 | && i.op[0].regs->reg_num == 1) | |
29b0f896 | 6899 | { |
a87af027 | 6900 | as_bad (_("you can't `pop %scs'"), register_prefix); |
4eed87de | 6901 | return 0; |
29b0f896 | 6902 | } |
4eed87de AM |
6903 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); |
6904 | if ((i.op[0].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 6905 | i.rex |= REX_B; |
4eed87de AM |
6906 | } |
6907 | else | |
6908 | { | |
7ab9ffdd | 6909 | /* The register or float register operand is in operand |
85f10a01 | 6910 | 0 or 1. */ |
40fb9820 | 6911 | unsigned int op; |
7ab9ffdd | 6912 | |
ca0d63fe | 6913 | if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte) |
7ab9ffdd L |
6914 | || operand_type_check (i.types[0], reg)) |
6915 | op = 0; | |
6916 | else | |
6917 | op = 1; | |
4eed87de AM |
6918 | /* Register goes in low 3 bits of opcode. */ |
6919 | i.tm.base_opcode |= i.op[op].regs->reg_num; | |
6920 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 6921 | i.rex |= REX_B; |
40fb9820 | 6922 | if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 | 6923 | { |
4eed87de AM |
6924 | /* Warn about some common errors, but press on regardless. |
6925 | The first case can be generated by gcc (<= 2.8.1). */ | |
6926 | if (i.operands == 2) | |
6927 | { | |
6928 | /* Reversed arguments on faddp, fsubp, etc. */ | |
a540244d | 6929 | as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, |
d8a1b51e JB |
6930 | register_prefix, i.op[!intel_syntax].regs->reg_name, |
6931 | register_prefix, i.op[intel_syntax].regs->reg_name); | |
4eed87de AM |
6932 | } |
6933 | else | |
6934 | { | |
6935 | /* Extraneous `l' suffix on fp insn. */ | |
a540244d L |
6936 | as_warn (_("translating to `%s %s%s'"), i.tm.name, |
6937 | register_prefix, i.op[0].regs->reg_name); | |
4eed87de | 6938 | } |
29b0f896 AM |
6939 | } |
6940 | } | |
6941 | } | |
40fb9820 | 6942 | else if (i.tm.opcode_modifier.modrm) |
29b0f896 AM |
6943 | { |
6944 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
52271982 AM |
6945 | must be put into the modrm byte). Now, we make the modrm and |
6946 | index base bytes based on all the info we've collected. */ | |
29b0f896 AM |
6947 | |
6948 | default_seg = build_modrm_byte (); | |
6949 | } | |
8a2ed489 | 6950 | else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32) |
29b0f896 AM |
6951 | { |
6952 | default_seg = &ds; | |
6953 | } | |
40fb9820 | 6954 | else if (i.tm.opcode_modifier.isstring) |
29b0f896 AM |
6955 | { |
6956 | /* For the string instructions that allow a segment override | |
6957 | on one of their operands, the default segment is ds. */ | |
6958 | default_seg = &ds; | |
6959 | } | |
6960 | ||
75178d9d L |
6961 | if (i.tm.base_opcode == 0x8d /* lea */ |
6962 | && i.seg[0] | |
6963 | && !quiet_warnings) | |
30123838 | 6964 | as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); |
52271982 AM |
6965 | |
6966 | /* If a segment was explicitly specified, and the specified segment | |
6967 | is not the default, use an opcode prefix to select it. If we | |
6968 | never figured out what the default segment is, then default_seg | |
6969 | will be zero at this point, and the specified segment prefix will | |
6970 | always be used. */ | |
29b0f896 AM |
6971 | if ((i.seg[0]) && (i.seg[0] != default_seg)) |
6972 | { | |
6973 | if (!add_prefix (i.seg[0]->seg_prefix)) | |
6974 | return 0; | |
6975 | } | |
6976 | return 1; | |
6977 | } | |
6978 | ||
6979 | static const seg_entry * | |
e3bb37b5 | 6980 | build_modrm_byte (void) |
29b0f896 AM |
6981 | { |
6982 | const seg_entry *default_seg = 0; | |
c0f3af97 | 6983 | unsigned int source, dest; |
8cd7925b | 6984 | int vex_3_sources; |
c0f3af97 | 6985 | |
8cd7925b | 6986 | vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES; |
c0f3af97 L |
6987 | if (vex_3_sources) |
6988 | { | |
91d6fa6a | 6989 | unsigned int nds, reg_slot; |
4c2c6516 | 6990 | expressionS *exp; |
c0f3af97 | 6991 | |
6b8d3588 | 6992 | dest = i.operands - 1; |
c0f3af97 | 6993 | nds = dest - 1; |
922d8de8 | 6994 | |
a683cc34 | 6995 | /* There are 2 kinds of instructions: |
bed3d976 JB |
6996 | 1. 5 operands: 4 register operands or 3 register operands |
6997 | plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and | |
6998 | VexW0 or VexW1. The destination must be either XMM, YMM or | |
43234a1e | 6999 | ZMM register. |
bed3d976 | 7000 | 2. 4 operands: 4 register operands or 3 register operands |
2f1bada2 | 7001 | plus 1 memory operand, with VexXDS. */ |
922d8de8 | 7002 | gas_assert ((i.reg_operands == 4 |
bed3d976 JB |
7003 | || (i.reg_operands == 3 && i.mem_operands == 1)) |
7004 | && i.tm.opcode_modifier.vexvvvv == VEXXDS | |
dcd7e323 JB |
7005 | && i.tm.opcode_modifier.vexw |
7006 | && i.tm.operand_types[dest].bitfield.regsimd); | |
a683cc34 | 7007 | |
48db9223 JB |
7008 | /* If VexW1 is set, the first non-immediate operand is the source and |
7009 | the second non-immediate one is encoded in the immediate operand. */ | |
7010 | if (i.tm.opcode_modifier.vexw == VEXW1) | |
7011 | { | |
7012 | source = i.imm_operands; | |
7013 | reg_slot = i.imm_operands + 1; | |
7014 | } | |
7015 | else | |
7016 | { | |
7017 | source = i.imm_operands + 1; | |
7018 | reg_slot = i.imm_operands; | |
7019 | } | |
7020 | ||
a683cc34 | 7021 | if (i.imm_operands == 0) |
bed3d976 JB |
7022 | { |
7023 | /* When there is no immediate operand, generate an 8bit | |
7024 | immediate operand to encode the first operand. */ | |
7025 | exp = &im_expressions[i.imm_operands++]; | |
7026 | i.op[i.operands].imms = exp; | |
7027 | i.types[i.operands] = imm8; | |
7028 | i.operands++; | |
7029 | ||
7030 | gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd); | |
7031 | exp->X_op = O_constant; | |
7032 | exp->X_add_number = register_number (i.op[reg_slot].regs) << 4; | |
43234a1e L |
7033 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
7034 | } | |
922d8de8 | 7035 | else |
bed3d976 JB |
7036 | { |
7037 | unsigned int imm_slot; | |
a683cc34 | 7038 | |
2f1bada2 JB |
7039 | gas_assert (i.imm_operands == 1 && i.types[0].bitfield.vec_imm4); |
7040 | ||
bed3d976 JB |
7041 | if (i.tm.opcode_modifier.immext) |
7042 | { | |
7043 | /* When ImmExt is set, the immediate byte is the last | |
7044 | operand. */ | |
7045 | imm_slot = i.operands - 1; | |
7046 | source--; | |
7047 | reg_slot--; | |
7048 | } | |
7049 | else | |
7050 | { | |
7051 | imm_slot = 0; | |
7052 | ||
7053 | /* Turn on Imm8 so that output_imm will generate it. */ | |
7054 | i.types[imm_slot].bitfield.imm8 = 1; | |
7055 | } | |
7056 | ||
7057 | gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd); | |
7058 | i.op[imm_slot].imms->X_add_number | |
7059 | |= register_number (i.op[reg_slot].regs) << 4; | |
43234a1e | 7060 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
bed3d976 | 7061 | } |
a683cc34 | 7062 | |
10c17abd | 7063 | gas_assert (i.tm.operand_types[nds].bitfield.regsimd); |
dae39acc | 7064 | i.vex.register_specifier = i.op[nds].regs; |
c0f3af97 L |
7065 | } |
7066 | else | |
7067 | source = dest = 0; | |
29b0f896 AM |
7068 | |
7069 | /* i.reg_operands MUST be the number of real register operands; | |
c0f3af97 L |
7070 | implicit registers do not count. If there are 3 register |
7071 | operands, it must be a instruction with VexNDS. For a | |
7072 | instruction with VexNDD, the destination register is encoded | |
7073 | in VEX prefix. If there are 4 register operands, it must be | |
7074 | a instruction with VEX prefix and 3 sources. */ | |
7ab9ffdd L |
7075 | if (i.mem_operands == 0 |
7076 | && ((i.reg_operands == 2 | |
2426c15f | 7077 | && i.tm.opcode_modifier.vexvvvv <= VEXXDS) |
7ab9ffdd | 7078 | || (i.reg_operands == 3 |
2426c15f | 7079 | && i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd | 7080 | || (i.reg_operands == 4 && vex_3_sources))) |
29b0f896 | 7081 | { |
cab737b9 L |
7082 | switch (i.operands) |
7083 | { | |
7084 | case 2: | |
7085 | source = 0; | |
7086 | break; | |
7087 | case 3: | |
c81128dc L |
7088 | /* When there are 3 operands, one of them may be immediate, |
7089 | which may be the first or the last operand. Otherwise, | |
c0f3af97 L |
7090 | the first operand must be shift count register (cl) or it |
7091 | is an instruction with VexNDS. */ | |
9c2799c2 | 7092 | gas_assert (i.imm_operands == 1 |
7ab9ffdd | 7093 | || (i.imm_operands == 0 |
2426c15f | 7094 | && (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd | 7095 | || i.types[0].bitfield.shiftcount))); |
40fb9820 L |
7096 | if (operand_type_check (i.types[0], imm) |
7097 | || i.types[0].bitfield.shiftcount) | |
7098 | source = 1; | |
7099 | else | |
7100 | source = 0; | |
cab737b9 L |
7101 | break; |
7102 | case 4: | |
368d64cc L |
7103 | /* When there are 4 operands, the first two must be 8bit |
7104 | immediate operands. The source operand will be the 3rd | |
c0f3af97 L |
7105 | one. |
7106 | ||
7107 | For instructions with VexNDS, if the first operand | |
7108 | an imm8, the source operand is the 2nd one. If the last | |
7109 | operand is imm8, the source operand is the first one. */ | |
9c2799c2 | 7110 | gas_assert ((i.imm_operands == 2 |
7ab9ffdd L |
7111 | && i.types[0].bitfield.imm8 |
7112 | && i.types[1].bitfield.imm8) | |
2426c15f | 7113 | || (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd L |
7114 | && i.imm_operands == 1 |
7115 | && (i.types[0].bitfield.imm8 | |
43234a1e L |
7116 | || i.types[i.operands - 1].bitfield.imm8 |
7117 | || i.rounding))); | |
9f2670f2 L |
7118 | if (i.imm_operands == 2) |
7119 | source = 2; | |
7120 | else | |
c0f3af97 L |
7121 | { |
7122 | if (i.types[0].bitfield.imm8) | |
7123 | source = 1; | |
7124 | else | |
7125 | source = 0; | |
7126 | } | |
c0f3af97 L |
7127 | break; |
7128 | case 5: | |
e771e7c9 | 7129 | if (is_evex_encoding (&i.tm)) |
43234a1e L |
7130 | { |
7131 | /* For EVEX instructions, when there are 5 operands, the | |
7132 | first one must be immediate operand. If the second one | |
7133 | is immediate operand, the source operand is the 3th | |
7134 | one. If the last one is immediate operand, the source | |
7135 | operand is the 2nd one. */ | |
7136 | gas_assert (i.imm_operands == 2 | |
7137 | && i.tm.opcode_modifier.sae | |
7138 | && operand_type_check (i.types[0], imm)); | |
7139 | if (operand_type_check (i.types[1], imm)) | |
7140 | source = 2; | |
7141 | else if (operand_type_check (i.types[4], imm)) | |
7142 | source = 1; | |
7143 | else | |
7144 | abort (); | |
7145 | } | |
cab737b9 L |
7146 | break; |
7147 | default: | |
7148 | abort (); | |
7149 | } | |
7150 | ||
c0f3af97 L |
7151 | if (!vex_3_sources) |
7152 | { | |
7153 | dest = source + 1; | |
7154 | ||
43234a1e L |
7155 | /* RC/SAE operand could be between DEST and SRC. That happens |
7156 | when one operand is GPR and the other one is XMM/YMM/ZMM | |
7157 | register. */ | |
7158 | if (i.rounding && i.rounding->operand == (int) dest) | |
7159 | dest++; | |
7160 | ||
2426c15f | 7161 | if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
c0f3af97 | 7162 | { |
43234a1e | 7163 | /* For instructions with VexNDS, the register-only source |
c5d0745b | 7164 | operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask |
43234a1e L |
7165 | register. It is encoded in VEX prefix. We need to |
7166 | clear RegMem bit before calling operand_type_equal. */ | |
f12dc422 L |
7167 | |
7168 | i386_operand_type op; | |
7169 | unsigned int vvvv; | |
7170 | ||
7171 | /* Check register-only source operand when two source | |
7172 | operands are swapped. */ | |
7173 | if (!i.tm.operand_types[source].bitfield.baseindex | |
7174 | && i.tm.operand_types[dest].bitfield.baseindex) | |
7175 | { | |
7176 | vvvv = source; | |
7177 | source = dest; | |
7178 | } | |
7179 | else | |
7180 | vvvv = dest; | |
7181 | ||
7182 | op = i.tm.operand_types[vvvv]; | |
fa99fab2 | 7183 | op.bitfield.regmem = 0; |
c0f3af97 | 7184 | if ((dest + 1) >= i.operands |
dc821c5f JB |
7185 | || ((!op.bitfield.reg |
7186 | || (!op.bitfield.dword && !op.bitfield.qword)) | |
10c17abd | 7187 | && !op.bitfield.regsimd |
43234a1e | 7188 | && !operand_type_equal (&op, ®mask))) |
c0f3af97 | 7189 | abort (); |
f12dc422 | 7190 | i.vex.register_specifier = i.op[vvvv].regs; |
c0f3af97 L |
7191 | dest++; |
7192 | } | |
7193 | } | |
29b0f896 AM |
7194 | |
7195 | i.rm.mode = 3; | |
7196 | /* One of the register operands will be encoded in the i.tm.reg | |
7197 | field, the other in the combined i.tm.mode and i.tm.regmem | |
7198 | fields. If no form of this instruction supports a memory | |
7199 | destination operand, then we assume the source operand may | |
7200 | sometimes be a memory operand and so we need to store the | |
7201 | destination in the i.rm.reg field. */ | |
40fb9820 L |
7202 | if (!i.tm.operand_types[dest].bitfield.regmem |
7203 | && operand_type_check (i.tm.operand_types[dest], anymem) == 0) | |
29b0f896 AM |
7204 | { |
7205 | i.rm.reg = i.op[dest].regs->reg_num; | |
7206 | i.rm.regmem = i.op[source].regs->reg_num; | |
b4a3a7b4 L |
7207 | if (i.op[dest].regs->reg_type.bitfield.regmmx |
7208 | || i.op[source].regs->reg_type.bitfield.regmmx) | |
7209 | i.has_regmmx = TRUE; | |
7210 | else if (i.op[dest].regs->reg_type.bitfield.regsimd | |
7211 | || i.op[source].regs->reg_type.bitfield.regsimd) | |
7212 | { | |
7213 | if (i.types[dest].bitfield.zmmword | |
7214 | || i.types[source].bitfield.zmmword) | |
7215 | i.has_regzmm = TRUE; | |
7216 | else if (i.types[dest].bitfield.ymmword | |
7217 | || i.types[source].bitfield.ymmword) | |
7218 | i.has_regymm = TRUE; | |
7219 | else | |
7220 | i.has_regxmm = TRUE; | |
7221 | } | |
29b0f896 | 7222 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) |
161a04f6 | 7223 | i.rex |= REX_R; |
43234a1e L |
7224 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
7225 | i.vrex |= REX_R; | |
29b0f896 | 7226 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 7227 | i.rex |= REX_B; |
43234a1e L |
7228 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
7229 | i.vrex |= REX_B; | |
29b0f896 AM |
7230 | } |
7231 | else | |
7232 | { | |
7233 | i.rm.reg = i.op[source].regs->reg_num; | |
7234 | i.rm.regmem = i.op[dest].regs->reg_num; | |
7235 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 7236 | i.rex |= REX_B; |
43234a1e L |
7237 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
7238 | i.vrex |= REX_B; | |
29b0f896 | 7239 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 7240 | i.rex |= REX_R; |
43234a1e L |
7241 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
7242 | i.vrex |= REX_R; | |
29b0f896 | 7243 | } |
e0c7f900 | 7244 | if (flag_code != CODE_64BIT && (i.rex & REX_R)) |
c4a530c5 | 7245 | { |
e0c7f900 | 7246 | if (!i.types[i.tm.operand_types[0].bitfield.regmem].bitfield.control) |
c4a530c5 | 7247 | abort (); |
e0c7f900 | 7248 | i.rex &= ~REX_R; |
c4a530c5 JB |
7249 | add_prefix (LOCK_PREFIX_OPCODE); |
7250 | } | |
29b0f896 AM |
7251 | } |
7252 | else | |
7253 | { /* If it's not 2 reg operands... */ | |
c0f3af97 L |
7254 | unsigned int mem; |
7255 | ||
29b0f896 AM |
7256 | if (i.mem_operands) |
7257 | { | |
7258 | unsigned int fake_zero_displacement = 0; | |
99018f42 | 7259 | unsigned int op; |
4eed87de | 7260 | |
7ab9ffdd L |
7261 | for (op = 0; op < i.operands; op++) |
7262 | if (operand_type_check (i.types[op], anymem)) | |
7263 | break; | |
7ab9ffdd | 7264 | gas_assert (op < i.operands); |
29b0f896 | 7265 | |
6c30d220 L |
7266 | if (i.tm.opcode_modifier.vecsib) |
7267 | { | |
e968fc9b | 7268 | if (i.index_reg->reg_num == RegIZ) |
6c30d220 L |
7269 | abort (); |
7270 | ||
7271 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
7272 | if (!i.base_reg) | |
7273 | { | |
7274 | i.sib.base = NO_BASE_REGISTER; | |
7275 | i.sib.scale = i.log2_scale_factor; | |
7276 | i.types[op].bitfield.disp8 = 0; | |
7277 | i.types[op].bitfield.disp16 = 0; | |
7278 | i.types[op].bitfield.disp64 = 0; | |
43083a50 | 7279 | if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX]) |
6c30d220 L |
7280 | { |
7281 | /* Must be 32 bit */ | |
7282 | i.types[op].bitfield.disp32 = 1; | |
7283 | i.types[op].bitfield.disp32s = 0; | |
7284 | } | |
7285 | else | |
7286 | { | |
7287 | i.types[op].bitfield.disp32 = 0; | |
7288 | i.types[op].bitfield.disp32s = 1; | |
7289 | } | |
7290 | } | |
7291 | i.sib.index = i.index_reg->reg_num; | |
7292 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
7293 | i.rex |= REX_X; | |
43234a1e L |
7294 | if ((i.index_reg->reg_flags & RegVRex) != 0) |
7295 | i.vrex |= REX_X; | |
6c30d220 L |
7296 | } |
7297 | ||
29b0f896 AM |
7298 | default_seg = &ds; |
7299 | ||
7300 | if (i.base_reg == 0) | |
7301 | { | |
7302 | i.rm.mode = 0; | |
7303 | if (!i.disp_operands) | |
9bb129e8 | 7304 | fake_zero_displacement = 1; |
29b0f896 AM |
7305 | if (i.index_reg == 0) |
7306 | { | |
73053c1f JB |
7307 | i386_operand_type newdisp; |
7308 | ||
6c30d220 | 7309 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 7310 | /* Operand is just <disp> */ |
20f0a1fc | 7311 | if (flag_code == CODE_64BIT) |
29b0f896 AM |
7312 | { |
7313 | /* 64bit mode overwrites the 32bit absolute | |
7314 | addressing by RIP relative addressing and | |
7315 | absolute addressing is encoded by one of the | |
7316 | redundant SIB forms. */ | |
7317 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
7318 | i.sib.base = NO_BASE_REGISTER; | |
7319 | i.sib.index = NO_INDEX_REGISTER; | |
73053c1f | 7320 | newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32); |
20f0a1fc | 7321 | } |
fc225355 L |
7322 | else if ((flag_code == CODE_16BIT) |
7323 | ^ (i.prefix[ADDR_PREFIX] != 0)) | |
20f0a1fc NC |
7324 | { |
7325 | i.rm.regmem = NO_BASE_REGISTER_16; | |
73053c1f | 7326 | newdisp = disp16; |
20f0a1fc NC |
7327 | } |
7328 | else | |
7329 | { | |
7330 | i.rm.regmem = NO_BASE_REGISTER; | |
73053c1f | 7331 | newdisp = disp32; |
29b0f896 | 7332 | } |
73053c1f JB |
7333 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
7334 | i.types[op] = operand_type_or (i.types[op], newdisp); | |
29b0f896 | 7335 | } |
6c30d220 | 7336 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 7337 | { |
6c30d220 | 7338 | /* !i.base_reg && i.index_reg */ |
e968fc9b | 7339 | if (i.index_reg->reg_num == RegIZ) |
db51cc60 L |
7340 | i.sib.index = NO_INDEX_REGISTER; |
7341 | else | |
7342 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
7343 | i.sib.base = NO_BASE_REGISTER; |
7344 | i.sib.scale = i.log2_scale_factor; | |
7345 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
40fb9820 L |
7346 | i.types[op].bitfield.disp8 = 0; |
7347 | i.types[op].bitfield.disp16 = 0; | |
7348 | i.types[op].bitfield.disp64 = 0; | |
43083a50 | 7349 | if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX]) |
40fb9820 L |
7350 | { |
7351 | /* Must be 32 bit */ | |
7352 | i.types[op].bitfield.disp32 = 1; | |
7353 | i.types[op].bitfield.disp32s = 0; | |
7354 | } | |
29b0f896 | 7355 | else |
40fb9820 L |
7356 | { |
7357 | i.types[op].bitfield.disp32 = 0; | |
7358 | i.types[op].bitfield.disp32s = 1; | |
7359 | } | |
29b0f896 | 7360 | if ((i.index_reg->reg_flags & RegRex) != 0) |
161a04f6 | 7361 | i.rex |= REX_X; |
29b0f896 AM |
7362 | } |
7363 | } | |
7364 | /* RIP addressing for 64bit mode. */ | |
e968fc9b | 7365 | else if (i.base_reg->reg_num == RegIP) |
29b0f896 | 7366 | { |
6c30d220 | 7367 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 7368 | i.rm.regmem = NO_BASE_REGISTER; |
40fb9820 L |
7369 | i.types[op].bitfield.disp8 = 0; |
7370 | i.types[op].bitfield.disp16 = 0; | |
7371 | i.types[op].bitfield.disp32 = 0; | |
7372 | i.types[op].bitfield.disp32s = 1; | |
7373 | i.types[op].bitfield.disp64 = 0; | |
71903a11 | 7374 | i.flags[op] |= Operand_PCrel; |
20f0a1fc NC |
7375 | if (! i.disp_operands) |
7376 | fake_zero_displacement = 1; | |
29b0f896 | 7377 | } |
dc821c5f | 7378 | else if (i.base_reg->reg_type.bitfield.word) |
29b0f896 | 7379 | { |
6c30d220 | 7380 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
7381 | switch (i.base_reg->reg_num) |
7382 | { | |
7383 | case 3: /* (%bx) */ | |
7384 | if (i.index_reg == 0) | |
7385 | i.rm.regmem = 7; | |
7386 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
7387 | i.rm.regmem = i.index_reg->reg_num - 6; | |
7388 | break; | |
7389 | case 5: /* (%bp) */ | |
7390 | default_seg = &ss; | |
7391 | if (i.index_reg == 0) | |
7392 | { | |
7393 | i.rm.regmem = 6; | |
40fb9820 | 7394 | if (operand_type_check (i.types[op], disp) == 0) |
29b0f896 AM |
7395 | { |
7396 | /* fake (%bp) into 0(%bp) */ | |
b5014f7a | 7397 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 7398 | fake_zero_displacement = 1; |
29b0f896 AM |
7399 | } |
7400 | } | |
7401 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
7402 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
7403 | break; | |
7404 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
7405 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
7406 | } | |
7407 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
7408 | } | |
7409 | else /* i.base_reg and 32/64 bit mode */ | |
7410 | { | |
7411 | if (flag_code == CODE_64BIT | |
40fb9820 L |
7412 | && operand_type_check (i.types[op], disp)) |
7413 | { | |
73053c1f JB |
7414 | i.types[op].bitfield.disp16 = 0; |
7415 | i.types[op].bitfield.disp64 = 0; | |
40fb9820 | 7416 | if (i.prefix[ADDR_PREFIX] == 0) |
73053c1f JB |
7417 | { |
7418 | i.types[op].bitfield.disp32 = 0; | |
7419 | i.types[op].bitfield.disp32s = 1; | |
7420 | } | |
40fb9820 | 7421 | else |
73053c1f JB |
7422 | { |
7423 | i.types[op].bitfield.disp32 = 1; | |
7424 | i.types[op].bitfield.disp32s = 0; | |
7425 | } | |
40fb9820 | 7426 | } |
20f0a1fc | 7427 | |
6c30d220 L |
7428 | if (!i.tm.opcode_modifier.vecsib) |
7429 | i.rm.regmem = i.base_reg->reg_num; | |
29b0f896 | 7430 | if ((i.base_reg->reg_flags & RegRex) != 0) |
161a04f6 | 7431 | i.rex |= REX_B; |
29b0f896 AM |
7432 | i.sib.base = i.base_reg->reg_num; |
7433 | /* x86-64 ignores REX prefix bit here to avoid decoder | |
7434 | complications. */ | |
848930b2 JB |
7435 | if (!(i.base_reg->reg_flags & RegRex) |
7436 | && (i.base_reg->reg_num == EBP_REG_NUM | |
7437 | || i.base_reg->reg_num == ESP_REG_NUM)) | |
29b0f896 | 7438 | default_seg = &ss; |
848930b2 | 7439 | if (i.base_reg->reg_num == 5 && i.disp_operands == 0) |
29b0f896 | 7440 | { |
848930b2 | 7441 | fake_zero_displacement = 1; |
b5014f7a | 7442 | i.types[op].bitfield.disp8 = 1; |
29b0f896 AM |
7443 | } |
7444 | i.sib.scale = i.log2_scale_factor; | |
7445 | if (i.index_reg == 0) | |
7446 | { | |
6c30d220 | 7447 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
7448 | /* <disp>(%esp) becomes two byte modrm with no index |
7449 | register. We've already stored the code for esp | |
7450 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. | |
7451 | Any base register besides %esp will not use the | |
7452 | extra modrm byte. */ | |
7453 | i.sib.index = NO_INDEX_REGISTER; | |
29b0f896 | 7454 | } |
6c30d220 | 7455 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 7456 | { |
e968fc9b | 7457 | if (i.index_reg->reg_num == RegIZ) |
db51cc60 L |
7458 | i.sib.index = NO_INDEX_REGISTER; |
7459 | else | |
7460 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
7461 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
7462 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
161a04f6 | 7463 | i.rex |= REX_X; |
29b0f896 | 7464 | } |
67a4f2b7 AO |
7465 | |
7466 | if (i.disp_operands | |
7467 | && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL | |
7468 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) | |
7469 | i.rm.mode = 0; | |
7470 | else | |
a501d77e L |
7471 | { |
7472 | if (!fake_zero_displacement | |
7473 | && !i.disp_operands | |
7474 | && i.disp_encoding) | |
7475 | { | |
7476 | fake_zero_displacement = 1; | |
7477 | if (i.disp_encoding == disp_encoding_8bit) | |
7478 | i.types[op].bitfield.disp8 = 1; | |
7479 | else | |
7480 | i.types[op].bitfield.disp32 = 1; | |
7481 | } | |
7482 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
7483 | } | |
29b0f896 | 7484 | } |
252b5132 | 7485 | |
29b0f896 AM |
7486 | if (fake_zero_displacement) |
7487 | { | |
7488 | /* Fakes a zero displacement assuming that i.types[op] | |
7489 | holds the correct displacement size. */ | |
7490 | expressionS *exp; | |
7491 | ||
9c2799c2 | 7492 | gas_assert (i.op[op].disps == 0); |
29b0f896 AM |
7493 | exp = &disp_expressions[i.disp_operands++]; |
7494 | i.op[op].disps = exp; | |
7495 | exp->X_op = O_constant; | |
7496 | exp->X_add_number = 0; | |
7497 | exp->X_add_symbol = (symbolS *) 0; | |
7498 | exp->X_op_symbol = (symbolS *) 0; | |
7499 | } | |
c0f3af97 L |
7500 | |
7501 | mem = op; | |
29b0f896 | 7502 | } |
c0f3af97 L |
7503 | else |
7504 | mem = ~0; | |
252b5132 | 7505 | |
8c43a48b | 7506 | if (i.tm.opcode_modifier.vexsources == XOP2SOURCES) |
5dd85c99 SP |
7507 | { |
7508 | if (operand_type_check (i.types[0], imm)) | |
7509 | i.vex.register_specifier = NULL; | |
7510 | else | |
7511 | { | |
7512 | /* VEX.vvvv encodes one of the sources when the first | |
7513 | operand is not an immediate. */ | |
1ef99a7b | 7514 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
7515 | i.vex.register_specifier = i.op[0].regs; |
7516 | else | |
7517 | i.vex.register_specifier = i.op[1].regs; | |
7518 | } | |
7519 | ||
7520 | /* Destination is a XMM register encoded in the ModRM.reg | |
7521 | and VEX.R bit. */ | |
7522 | i.rm.reg = i.op[2].regs->reg_num; | |
7523 | if ((i.op[2].regs->reg_flags & RegRex) != 0) | |
7524 | i.rex |= REX_R; | |
7525 | ||
7526 | /* ModRM.rm and VEX.B encodes the other source. */ | |
7527 | if (!i.mem_operands) | |
7528 | { | |
7529 | i.rm.mode = 3; | |
7530 | ||
1ef99a7b | 7531 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
7532 | i.rm.regmem = i.op[1].regs->reg_num; |
7533 | else | |
7534 | i.rm.regmem = i.op[0].regs->reg_num; | |
7535 | ||
7536 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
7537 | i.rex |= REX_B; | |
7538 | } | |
7539 | } | |
2426c15f | 7540 | else if (i.tm.opcode_modifier.vexvvvv == VEXLWP) |
f88c9eb0 SP |
7541 | { |
7542 | i.vex.register_specifier = i.op[2].regs; | |
7543 | if (!i.mem_operands) | |
7544 | { | |
7545 | i.rm.mode = 3; | |
7546 | i.rm.regmem = i.op[1].regs->reg_num; | |
7547 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
7548 | i.rex |= REX_B; | |
7549 | } | |
7550 | } | |
29b0f896 AM |
7551 | /* Fill in i.rm.reg or i.rm.regmem field with register operand |
7552 | (if any) based on i.tm.extension_opcode. Again, we must be | |
7553 | careful to make sure that segment/control/debug/test/MMX | |
7554 | registers are coded into the i.rm.reg field. */ | |
f88c9eb0 | 7555 | else if (i.reg_operands) |
29b0f896 | 7556 | { |
99018f42 | 7557 | unsigned int op; |
7ab9ffdd L |
7558 | unsigned int vex_reg = ~0; |
7559 | ||
7560 | for (op = 0; op < i.operands; op++) | |
b4a3a7b4 L |
7561 | { |
7562 | if (i.types[op].bitfield.reg | |
7563 | || i.types[op].bitfield.regbnd | |
7564 | || i.types[op].bitfield.regmask | |
7565 | || i.types[op].bitfield.sreg2 | |
7566 | || i.types[op].bitfield.sreg3 | |
7567 | || i.types[op].bitfield.control | |
7568 | || i.types[op].bitfield.debug | |
7569 | || i.types[op].bitfield.test) | |
7570 | break; | |
7571 | if (i.types[op].bitfield.regsimd) | |
7572 | { | |
7573 | if (i.types[op].bitfield.zmmword) | |
7574 | i.has_regzmm = TRUE; | |
7575 | else if (i.types[op].bitfield.ymmword) | |
7576 | i.has_regymm = TRUE; | |
7577 | else | |
7578 | i.has_regxmm = TRUE; | |
7579 | break; | |
7580 | } | |
7581 | if (i.types[op].bitfield.regmmx) | |
7582 | { | |
7583 | i.has_regmmx = TRUE; | |
7584 | break; | |
7585 | } | |
7586 | } | |
c0209578 | 7587 | |
7ab9ffdd L |
7588 | if (vex_3_sources) |
7589 | op = dest; | |
2426c15f | 7590 | else if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd L |
7591 | { |
7592 | /* For instructions with VexNDS, the register-only | |
7593 | source operand is encoded in VEX prefix. */ | |
7594 | gas_assert (mem != (unsigned int) ~0); | |
c0f3af97 | 7595 | |
7ab9ffdd | 7596 | if (op > mem) |
c0f3af97 | 7597 | { |
7ab9ffdd L |
7598 | vex_reg = op++; |
7599 | gas_assert (op < i.operands); | |
c0f3af97 L |
7600 | } |
7601 | else | |
c0f3af97 | 7602 | { |
f12dc422 L |
7603 | /* Check register-only source operand when two source |
7604 | operands are swapped. */ | |
7605 | if (!i.tm.operand_types[op].bitfield.baseindex | |
7606 | && i.tm.operand_types[op + 1].bitfield.baseindex) | |
7607 | { | |
7608 | vex_reg = op; | |
7609 | op += 2; | |
7610 | gas_assert (mem == (vex_reg + 1) | |
7611 | && op < i.operands); | |
7612 | } | |
7613 | else | |
7614 | { | |
7615 | vex_reg = op + 1; | |
7616 | gas_assert (vex_reg < i.operands); | |
7617 | } | |
c0f3af97 | 7618 | } |
7ab9ffdd | 7619 | } |
2426c15f | 7620 | else if (i.tm.opcode_modifier.vexvvvv == VEXNDD) |
7ab9ffdd | 7621 | { |
f12dc422 | 7622 | /* For instructions with VexNDD, the register destination |
7ab9ffdd | 7623 | is encoded in VEX prefix. */ |
f12dc422 L |
7624 | if (i.mem_operands == 0) |
7625 | { | |
7626 | /* There is no memory operand. */ | |
7627 | gas_assert ((op + 2) == i.operands); | |
7628 | vex_reg = op + 1; | |
7629 | } | |
7630 | else | |
8d63c93e | 7631 | { |
ed438a93 JB |
7632 | /* There are only 2 non-immediate operands. */ |
7633 | gas_assert (op < i.imm_operands + 2 | |
7634 | && i.operands == i.imm_operands + 2); | |
7635 | vex_reg = i.imm_operands + 1; | |
f12dc422 | 7636 | } |
7ab9ffdd L |
7637 | } |
7638 | else | |
7639 | gas_assert (op < i.operands); | |
99018f42 | 7640 | |
7ab9ffdd L |
7641 | if (vex_reg != (unsigned int) ~0) |
7642 | { | |
f12dc422 | 7643 | i386_operand_type *type = &i.tm.operand_types[vex_reg]; |
7ab9ffdd | 7644 | |
dc821c5f JB |
7645 | if ((!type->bitfield.reg |
7646 | || (!type->bitfield.dword && !type->bitfield.qword)) | |
10c17abd | 7647 | && !type->bitfield.regsimd |
43234a1e | 7648 | && !operand_type_equal (type, ®mask)) |
7ab9ffdd | 7649 | abort (); |
f88c9eb0 | 7650 | |
7ab9ffdd L |
7651 | i.vex.register_specifier = i.op[vex_reg].regs; |
7652 | } | |
7653 | ||
1b9f0c97 L |
7654 | /* Don't set OP operand twice. */ |
7655 | if (vex_reg != op) | |
7ab9ffdd | 7656 | { |
1b9f0c97 L |
7657 | /* If there is an extension opcode to put here, the |
7658 | register number must be put into the regmem field. */ | |
7659 | if (i.tm.extension_opcode != None) | |
7660 | { | |
7661 | i.rm.regmem = i.op[op].regs->reg_num; | |
7662 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
7663 | i.rex |= REX_B; | |
43234a1e L |
7664 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
7665 | i.vrex |= REX_B; | |
1b9f0c97 L |
7666 | } |
7667 | else | |
7668 | { | |
7669 | i.rm.reg = i.op[op].regs->reg_num; | |
7670 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
7671 | i.rex |= REX_R; | |
43234a1e L |
7672 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
7673 | i.vrex |= REX_R; | |
1b9f0c97 | 7674 | } |
7ab9ffdd | 7675 | } |
252b5132 | 7676 | |
29b0f896 AM |
7677 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we |
7678 | must set it to 3 to indicate this is a register operand | |
7679 | in the regmem field. */ | |
7680 | if (!i.mem_operands) | |
7681 | i.rm.mode = 3; | |
7682 | } | |
252b5132 | 7683 | |
29b0f896 | 7684 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
c1e679ec | 7685 | if (i.tm.extension_opcode != None) |
29b0f896 AM |
7686 | i.rm.reg = i.tm.extension_opcode; |
7687 | } | |
7688 | return default_seg; | |
7689 | } | |
252b5132 | 7690 | |
29b0f896 | 7691 | static void |
e3bb37b5 | 7692 | output_branch (void) |
29b0f896 AM |
7693 | { |
7694 | char *p; | |
f8a5c266 | 7695 | int size; |
29b0f896 AM |
7696 | int code16; |
7697 | int prefix; | |
7698 | relax_substateT subtype; | |
7699 | symbolS *sym; | |
7700 | offsetT off; | |
7701 | ||
f8a5c266 | 7702 | code16 = flag_code == CODE_16BIT ? CODE16 : 0; |
a501d77e | 7703 | size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL; |
29b0f896 AM |
7704 | |
7705 | prefix = 0; | |
7706 | if (i.prefix[DATA_PREFIX] != 0) | |
252b5132 | 7707 | { |
29b0f896 AM |
7708 | prefix = 1; |
7709 | i.prefixes -= 1; | |
7710 | code16 ^= CODE16; | |
252b5132 | 7711 | } |
29b0f896 AM |
7712 | /* Pentium4 branch hints. */ |
7713 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
7714 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2f66722d | 7715 | { |
29b0f896 AM |
7716 | prefix++; |
7717 | i.prefixes--; | |
7718 | } | |
7719 | if (i.prefix[REX_PREFIX] != 0) | |
7720 | { | |
7721 | prefix++; | |
7722 | i.prefixes--; | |
2f66722d AM |
7723 | } |
7724 | ||
7e8b059b L |
7725 | /* BND prefixed jump. */ |
7726 | if (i.prefix[BND_PREFIX] != 0) | |
7727 | { | |
7728 | FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]); | |
7729 | i.prefixes -= 1; | |
7730 | } | |
7731 | ||
29b0f896 AM |
7732 | if (i.prefixes != 0 && !intel_syntax) |
7733 | as_warn (_("skipping prefixes on this instruction")); | |
7734 | ||
7735 | /* It's always a symbol; End frag & setup for relax. | |
7736 | Make sure there is enough room in this frag for the largest | |
7737 | instruction we may generate in md_convert_frag. This is 2 | |
7738 | bytes for the opcode and room for the prefix and largest | |
7739 | displacement. */ | |
7740 | frag_grow (prefix + 2 + 4); | |
7741 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
7742 | p = frag_more (prefix + 1); | |
7743 | if (i.prefix[DATA_PREFIX] != 0) | |
7744 | *p++ = DATA_PREFIX_OPCODE; | |
7745 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE | |
7746 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
7747 | *p++ = i.prefix[SEG_PREFIX]; | |
7748 | if (i.prefix[REX_PREFIX] != 0) | |
7749 | *p++ = i.prefix[REX_PREFIX]; | |
7750 | *p = i.tm.base_opcode; | |
7751 | ||
7752 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
f8a5c266 | 7753 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size); |
40fb9820 | 7754 | else if (cpu_arch_flags.bitfield.cpui386) |
f8a5c266 | 7755 | subtype = ENCODE_RELAX_STATE (COND_JUMP, size); |
29b0f896 | 7756 | else |
f8a5c266 | 7757 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, size); |
29b0f896 | 7758 | subtype |= code16; |
3e73aa7c | 7759 | |
29b0f896 AM |
7760 | sym = i.op[0].disps->X_add_symbol; |
7761 | off = i.op[0].disps->X_add_number; | |
3e73aa7c | 7762 | |
29b0f896 AM |
7763 | if (i.op[0].disps->X_op != O_constant |
7764 | && i.op[0].disps->X_op != O_symbol) | |
3e73aa7c | 7765 | { |
29b0f896 AM |
7766 | /* Handle complex expressions. */ |
7767 | sym = make_expr_symbol (i.op[0].disps); | |
7768 | off = 0; | |
7769 | } | |
3e73aa7c | 7770 | |
29b0f896 AM |
7771 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
7772 | Pass reloc in fr_var. */ | |
d258b828 | 7773 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); |
29b0f896 | 7774 | } |
3e73aa7c | 7775 | |
bd7ab16b L |
7776 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
7777 | /* Return TRUE iff PLT32 relocation should be used for branching to | |
7778 | symbol S. */ | |
7779 | ||
7780 | static bfd_boolean | |
7781 | need_plt32_p (symbolS *s) | |
7782 | { | |
7783 | /* PLT32 relocation is ELF only. */ | |
7784 | if (!IS_ELF) | |
7785 | return FALSE; | |
7786 | ||
7787 | /* Since there is no need to prepare for PLT branch on x86-64, we | |
7788 | can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can | |
7789 | be used as a marker for 32-bit PC-relative branches. */ | |
7790 | if (!object_64bit) | |
7791 | return FALSE; | |
7792 | ||
7793 | /* Weak or undefined symbol need PLT32 relocation. */ | |
7794 | if (S_IS_WEAK (s) || !S_IS_DEFINED (s)) | |
7795 | return TRUE; | |
7796 | ||
7797 | /* Non-global symbol doesn't need PLT32 relocation. */ | |
7798 | if (! S_IS_EXTERNAL (s)) | |
7799 | return FALSE; | |
7800 | ||
7801 | /* Other global symbols need PLT32 relocation. NB: Symbol with | |
7802 | non-default visibilities are treated as normal global symbol | |
7803 | so that PLT32 relocation can be used as a marker for 32-bit | |
7804 | PC-relative branches. It is useful for linker relaxation. */ | |
7805 | return TRUE; | |
7806 | } | |
7807 | #endif | |
7808 | ||
29b0f896 | 7809 | static void |
e3bb37b5 | 7810 | output_jump (void) |
29b0f896 AM |
7811 | { |
7812 | char *p; | |
7813 | int size; | |
3e02c1cc | 7814 | fixS *fixP; |
bd7ab16b | 7815 | bfd_reloc_code_real_type jump_reloc = i.reloc[0]; |
29b0f896 | 7816 | |
40fb9820 | 7817 | if (i.tm.opcode_modifier.jumpbyte) |
29b0f896 AM |
7818 | { |
7819 | /* This is a loop or jecxz type instruction. */ | |
7820 | size = 1; | |
7821 | if (i.prefix[ADDR_PREFIX] != 0) | |
7822 | { | |
7823 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); | |
7824 | i.prefixes -= 1; | |
7825 | } | |
7826 | /* Pentium4 branch hints. */ | |
7827 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
7828 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
7829 | { | |
7830 | FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); | |
7831 | i.prefixes--; | |
3e73aa7c JH |
7832 | } |
7833 | } | |
29b0f896 AM |
7834 | else |
7835 | { | |
7836 | int code16; | |
3e73aa7c | 7837 | |
29b0f896 AM |
7838 | code16 = 0; |
7839 | if (flag_code == CODE_16BIT) | |
7840 | code16 = CODE16; | |
3e73aa7c | 7841 | |
29b0f896 AM |
7842 | if (i.prefix[DATA_PREFIX] != 0) |
7843 | { | |
7844 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); | |
7845 | i.prefixes -= 1; | |
7846 | code16 ^= CODE16; | |
7847 | } | |
252b5132 | 7848 | |
29b0f896 AM |
7849 | size = 4; |
7850 | if (code16) | |
7851 | size = 2; | |
7852 | } | |
9fcc94b6 | 7853 | |
29b0f896 AM |
7854 | if (i.prefix[REX_PREFIX] != 0) |
7855 | { | |
7856 | FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); | |
7857 | i.prefixes -= 1; | |
7858 | } | |
252b5132 | 7859 | |
7e8b059b L |
7860 | /* BND prefixed jump. */ |
7861 | if (i.prefix[BND_PREFIX] != 0) | |
7862 | { | |
7863 | FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]); | |
7864 | i.prefixes -= 1; | |
7865 | } | |
7866 | ||
29b0f896 AM |
7867 | if (i.prefixes != 0 && !intel_syntax) |
7868 | as_warn (_("skipping prefixes on this instruction")); | |
e0890092 | 7869 | |
42164a71 L |
7870 | p = frag_more (i.tm.opcode_length + size); |
7871 | switch (i.tm.opcode_length) | |
7872 | { | |
7873 | case 2: | |
7874 | *p++ = i.tm.base_opcode >> 8; | |
1a0670f3 | 7875 | /* Fall through. */ |
42164a71 L |
7876 | case 1: |
7877 | *p++ = i.tm.base_opcode; | |
7878 | break; | |
7879 | default: | |
7880 | abort (); | |
7881 | } | |
e0890092 | 7882 | |
bd7ab16b L |
7883 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
7884 | if (size == 4 | |
7885 | && jump_reloc == NO_RELOC | |
7886 | && need_plt32_p (i.op[0].disps->X_add_symbol)) | |
7887 | jump_reloc = BFD_RELOC_X86_64_PLT32; | |
7888 | #endif | |
7889 | ||
7890 | jump_reloc = reloc (size, 1, 1, jump_reloc); | |
7891 | ||
3e02c1cc | 7892 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
bd7ab16b | 7893 | i.op[0].disps, 1, jump_reloc); |
3e02c1cc AM |
7894 | |
7895 | /* All jumps handled here are signed, but don't use a signed limit | |
7896 | check for 32 and 16 bit jumps as we want to allow wrap around at | |
7897 | 4G and 64k respectively. */ | |
7898 | if (size == 1) | |
7899 | fixP->fx_signed = 1; | |
29b0f896 | 7900 | } |
e0890092 | 7901 | |
29b0f896 | 7902 | static void |
e3bb37b5 | 7903 | output_interseg_jump (void) |
29b0f896 AM |
7904 | { |
7905 | char *p; | |
7906 | int size; | |
7907 | int prefix; | |
7908 | int code16; | |
252b5132 | 7909 | |
29b0f896 AM |
7910 | code16 = 0; |
7911 | if (flag_code == CODE_16BIT) | |
7912 | code16 = CODE16; | |
a217f122 | 7913 | |
29b0f896 AM |
7914 | prefix = 0; |
7915 | if (i.prefix[DATA_PREFIX] != 0) | |
7916 | { | |
7917 | prefix = 1; | |
7918 | i.prefixes -= 1; | |
7919 | code16 ^= CODE16; | |
7920 | } | |
7921 | if (i.prefix[REX_PREFIX] != 0) | |
7922 | { | |
7923 | prefix++; | |
7924 | i.prefixes -= 1; | |
7925 | } | |
252b5132 | 7926 | |
29b0f896 AM |
7927 | size = 4; |
7928 | if (code16) | |
7929 | size = 2; | |
252b5132 | 7930 | |
29b0f896 AM |
7931 | if (i.prefixes != 0 && !intel_syntax) |
7932 | as_warn (_("skipping prefixes on this instruction")); | |
252b5132 | 7933 | |
29b0f896 AM |
7934 | /* 1 opcode; 2 segment; offset */ |
7935 | p = frag_more (prefix + 1 + 2 + size); | |
3e73aa7c | 7936 | |
29b0f896 AM |
7937 | if (i.prefix[DATA_PREFIX] != 0) |
7938 | *p++ = DATA_PREFIX_OPCODE; | |
252b5132 | 7939 | |
29b0f896 AM |
7940 | if (i.prefix[REX_PREFIX] != 0) |
7941 | *p++ = i.prefix[REX_PREFIX]; | |
252b5132 | 7942 | |
29b0f896 AM |
7943 | *p++ = i.tm.base_opcode; |
7944 | if (i.op[1].imms->X_op == O_constant) | |
7945 | { | |
7946 | offsetT n = i.op[1].imms->X_add_number; | |
252b5132 | 7947 | |
29b0f896 AM |
7948 | if (size == 2 |
7949 | && !fits_in_unsigned_word (n) | |
7950 | && !fits_in_signed_word (n)) | |
7951 | { | |
7952 | as_bad (_("16-bit jump out of range")); | |
7953 | return; | |
7954 | } | |
7955 | md_number_to_chars (p, n, size); | |
7956 | } | |
7957 | else | |
7958 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
d258b828 | 7959 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); |
29b0f896 AM |
7960 | if (i.op[0].imms->X_op != O_constant) |
7961 | as_bad (_("can't handle non absolute segment in `%s'"), | |
7962 | i.tm.name); | |
7963 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); | |
7964 | } | |
a217f122 | 7965 | |
b4a3a7b4 L |
7966 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
7967 | void | |
7968 | x86_cleanup (void) | |
7969 | { | |
7970 | char *p; | |
7971 | asection *seg = now_seg; | |
7972 | subsegT subseg = now_subseg; | |
7973 | asection *sec; | |
7974 | unsigned int alignment, align_size_1; | |
7975 | unsigned int isa_1_descsz, feature_2_descsz, descsz; | |
7976 | unsigned int isa_1_descsz_raw, feature_2_descsz_raw; | |
7977 | unsigned int padding; | |
7978 | ||
7979 | if (!IS_ELF || !x86_used_note) | |
7980 | return; | |
7981 | ||
b4a3a7b4 L |
7982 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X86; |
7983 | ||
7984 | /* The .note.gnu.property section layout: | |
7985 | ||
7986 | Field Length Contents | |
7987 | ---- ---- ---- | |
7988 | n_namsz 4 4 | |
7989 | n_descsz 4 The note descriptor size | |
7990 | n_type 4 NT_GNU_PROPERTY_TYPE_0 | |
7991 | n_name 4 "GNU" | |
7992 | n_desc n_descsz The program property array | |
7993 | .... .... .... | |
7994 | */ | |
7995 | ||
7996 | /* Create the .note.gnu.property section. */ | |
7997 | sec = subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME, 0); | |
7998 | bfd_set_section_flags (stdoutput, sec, | |
7999 | (SEC_ALLOC | |
8000 | | SEC_LOAD | |
8001 | | SEC_DATA | |
8002 | | SEC_HAS_CONTENTS | |
8003 | | SEC_READONLY)); | |
8004 | ||
8005 | if (get_elf_backend_data (stdoutput)->s->elfclass == ELFCLASS64) | |
8006 | { | |
8007 | align_size_1 = 7; | |
8008 | alignment = 3; | |
8009 | } | |
8010 | else | |
8011 | { | |
8012 | align_size_1 = 3; | |
8013 | alignment = 2; | |
8014 | } | |
8015 | ||
8016 | bfd_set_section_alignment (stdoutput, sec, alignment); | |
8017 | elf_section_type (sec) = SHT_NOTE; | |
8018 | ||
8019 | /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size | |
8020 | + 4-byte data */ | |
8021 | isa_1_descsz_raw = 4 + 4 + 4; | |
8022 | /* Align GNU_PROPERTY_X86_ISA_1_USED. */ | |
8023 | isa_1_descsz = (isa_1_descsz_raw + align_size_1) & ~align_size_1; | |
8024 | ||
8025 | feature_2_descsz_raw = isa_1_descsz; | |
8026 | /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size | |
8027 | + 4-byte data */ | |
8028 | feature_2_descsz_raw += 4 + 4 + 4; | |
8029 | /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */ | |
8030 | feature_2_descsz = ((feature_2_descsz_raw + align_size_1) | |
8031 | & ~align_size_1); | |
8032 | ||
8033 | descsz = feature_2_descsz; | |
8034 | /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */ | |
8035 | p = frag_more (4 + 4 + 4 + 4 + descsz); | |
8036 | ||
8037 | /* Write n_namsz. */ | |
8038 | md_number_to_chars (p, (valueT) 4, 4); | |
8039 | ||
8040 | /* Write n_descsz. */ | |
8041 | md_number_to_chars (p + 4, (valueT) descsz, 4); | |
8042 | ||
8043 | /* Write n_type. */ | |
8044 | md_number_to_chars (p + 4 * 2, (valueT) NT_GNU_PROPERTY_TYPE_0, 4); | |
8045 | ||
8046 | /* Write n_name. */ | |
8047 | memcpy (p + 4 * 3, "GNU", 4); | |
8048 | ||
8049 | /* Write 4-byte type. */ | |
8050 | md_number_to_chars (p + 4 * 4, | |
8051 | (valueT) GNU_PROPERTY_X86_ISA_1_USED, 4); | |
8052 | ||
8053 | /* Write 4-byte data size. */ | |
8054 | md_number_to_chars (p + 4 * 5, (valueT) 4, 4); | |
8055 | ||
8056 | /* Write 4-byte data. */ | |
8057 | md_number_to_chars (p + 4 * 6, (valueT) x86_isa_1_used, 4); | |
8058 | ||
8059 | /* Zero out paddings. */ | |
8060 | padding = isa_1_descsz - isa_1_descsz_raw; | |
8061 | if (padding) | |
8062 | memset (p + 4 * 7, 0, padding); | |
8063 | ||
8064 | /* Write 4-byte type. */ | |
8065 | md_number_to_chars (p + isa_1_descsz + 4 * 4, | |
8066 | (valueT) GNU_PROPERTY_X86_FEATURE_2_USED, 4); | |
8067 | ||
8068 | /* Write 4-byte data size. */ | |
8069 | md_number_to_chars (p + isa_1_descsz + 4 * 5, (valueT) 4, 4); | |
8070 | ||
8071 | /* Write 4-byte data. */ | |
8072 | md_number_to_chars (p + isa_1_descsz + 4 * 6, | |
8073 | (valueT) x86_feature_2_used, 4); | |
8074 | ||
8075 | /* Zero out paddings. */ | |
8076 | padding = feature_2_descsz - feature_2_descsz_raw; | |
8077 | if (padding) | |
8078 | memset (p + isa_1_descsz + 4 * 7, 0, padding); | |
8079 | ||
8080 | /* We probably can't restore the current segment, for there likely | |
8081 | isn't one yet... */ | |
8082 | if (seg && subseg) | |
8083 | subseg_set (seg, subseg); | |
8084 | } | |
8085 | #endif | |
8086 | ||
29b0f896 | 8087 | static void |
e3bb37b5 | 8088 | output_insn (void) |
29b0f896 | 8089 | { |
2bbd9c25 JJ |
8090 | fragS *insn_start_frag; |
8091 | offsetT insn_start_off; | |
8092 | ||
b4a3a7b4 L |
8093 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8094 | if (IS_ELF && x86_used_note) | |
8095 | { | |
8096 | if (i.tm.cpu_flags.bitfield.cpucmov) | |
8097 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_CMOV; | |
8098 | if (i.tm.cpu_flags.bitfield.cpusse) | |
8099 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE; | |
8100 | if (i.tm.cpu_flags.bitfield.cpusse2) | |
8101 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE2; | |
8102 | if (i.tm.cpu_flags.bitfield.cpusse3) | |
8103 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE3; | |
8104 | if (i.tm.cpu_flags.bitfield.cpussse3) | |
8105 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSSE3; | |
8106 | if (i.tm.cpu_flags.bitfield.cpusse4_1) | |
8107 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_1; | |
8108 | if (i.tm.cpu_flags.bitfield.cpusse4_2) | |
8109 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_2; | |
8110 | if (i.tm.cpu_flags.bitfield.cpuavx) | |
8111 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX; | |
8112 | if (i.tm.cpu_flags.bitfield.cpuavx2) | |
8113 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX2; | |
8114 | if (i.tm.cpu_flags.bitfield.cpufma) | |
8115 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_FMA; | |
8116 | if (i.tm.cpu_flags.bitfield.cpuavx512f) | |
8117 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512F; | |
8118 | if (i.tm.cpu_flags.bitfield.cpuavx512cd) | |
8119 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512CD; | |
8120 | if (i.tm.cpu_flags.bitfield.cpuavx512er) | |
8121 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512ER; | |
8122 | if (i.tm.cpu_flags.bitfield.cpuavx512pf) | |
8123 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512PF; | |
8124 | if (i.tm.cpu_flags.bitfield.cpuavx512vl) | |
8125 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512VL; | |
8126 | if (i.tm.cpu_flags.bitfield.cpuavx512dq) | |
8127 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512DQ; | |
8128 | if (i.tm.cpu_flags.bitfield.cpuavx512bw) | |
8129 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512BW; | |
8130 | if (i.tm.cpu_flags.bitfield.cpuavx512_4fmaps) | |
8131 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS; | |
8132 | if (i.tm.cpu_flags.bitfield.cpuavx512_4vnniw) | |
8133 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW; | |
8134 | if (i.tm.cpu_flags.bitfield.cpuavx512_bitalg) | |
8135 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG; | |
8136 | if (i.tm.cpu_flags.bitfield.cpuavx512ifma) | |
8137 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA; | |
8138 | if (i.tm.cpu_flags.bitfield.cpuavx512vbmi) | |
8139 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI; | |
8140 | if (i.tm.cpu_flags.bitfield.cpuavx512_vbmi2) | |
8141 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2; | |
8142 | if (i.tm.cpu_flags.bitfield.cpuavx512_vnni) | |
8143 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI; | |
8144 | ||
8145 | if (i.tm.cpu_flags.bitfield.cpu8087 | |
8146 | || i.tm.cpu_flags.bitfield.cpu287 | |
8147 | || i.tm.cpu_flags.bitfield.cpu387 | |
8148 | || i.tm.cpu_flags.bitfield.cpu687 | |
8149 | || i.tm.cpu_flags.bitfield.cpufisttp) | |
8150 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X87; | |
8151 | /* Don't set GNU_PROPERTY_X86_FEATURE_2_MMX for prefetchtXXX nor | |
8152 | Xfence instructions. */ | |
8153 | if (i.tm.base_opcode != 0xf18 | |
8154 | && i.tm.base_opcode != 0xf0d | |
8155 | && i.tm.base_opcode != 0xfae | |
8156 | && (i.has_regmmx | |
8157 | || i.tm.cpu_flags.bitfield.cpummx | |
8158 | || i.tm.cpu_flags.bitfield.cpua3dnow | |
8159 | || i.tm.cpu_flags.bitfield.cpua3dnowa)) | |
8160 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MMX; | |
8161 | if (i.has_regxmm) | |
8162 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XMM; | |
8163 | if (i.has_regymm) | |
8164 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_YMM; | |
8165 | if (i.has_regzmm) | |
8166 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_ZMM; | |
8167 | if (i.tm.cpu_flags.bitfield.cpufxsr) | |
8168 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_FXSR; | |
8169 | if (i.tm.cpu_flags.bitfield.cpuxsave) | |
8170 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVE; | |
8171 | if (i.tm.cpu_flags.bitfield.cpuxsaveopt) | |
8172 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT; | |
8173 | if (i.tm.cpu_flags.bitfield.cpuxsavec) | |
8174 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEC; | |
8175 | } | |
8176 | #endif | |
8177 | ||
29b0f896 AM |
8178 | /* Tie dwarf2 debug info to the address at the start of the insn. |
8179 | We can't do this after the insn has been output as the current | |
8180 | frag may have been closed off. eg. by frag_var. */ | |
8181 | dwarf2_emit_insn (0); | |
8182 | ||
2bbd9c25 JJ |
8183 | insn_start_frag = frag_now; |
8184 | insn_start_off = frag_now_fix (); | |
8185 | ||
29b0f896 | 8186 | /* Output jumps. */ |
40fb9820 | 8187 | if (i.tm.opcode_modifier.jump) |
29b0f896 | 8188 | output_branch (); |
40fb9820 L |
8189 | else if (i.tm.opcode_modifier.jumpbyte |
8190 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 | 8191 | output_jump (); |
40fb9820 | 8192 | else if (i.tm.opcode_modifier.jumpintersegment) |
29b0f896 AM |
8193 | output_interseg_jump (); |
8194 | else | |
8195 | { | |
8196 | /* Output normal instructions here. */ | |
8197 | char *p; | |
8198 | unsigned char *q; | |
47465058 | 8199 | unsigned int j; |
331d2d0d | 8200 | unsigned int prefix; |
4dffcebc | 8201 | |
e4e00185 AS |
8202 | if (avoid_fence |
8203 | && i.tm.base_opcode == 0xfae | |
8204 | && i.operands == 1 | |
8205 | && i.imm_operands == 1 | |
8206 | && (i.op[0].imms->X_add_number == 0xe8 | |
8207 | || i.op[0].imms->X_add_number == 0xf0 | |
8208 | || i.op[0].imms->X_add_number == 0xf8)) | |
8209 | { | |
8210 | /* Encode lfence, mfence, and sfence as | |
8211 | f0 83 04 24 00 lock addl $0x0, (%{re}sp). */ | |
8212 | offsetT val = 0x240483f0ULL; | |
8213 | p = frag_more (5); | |
8214 | md_number_to_chars (p, val, 5); | |
8215 | return; | |
8216 | } | |
8217 | ||
d022bddd IT |
8218 | /* Some processors fail on LOCK prefix. This options makes |
8219 | assembler ignore LOCK prefix and serves as a workaround. */ | |
8220 | if (omit_lock_prefix) | |
8221 | { | |
8222 | if (i.tm.base_opcode == LOCK_PREFIX_OPCODE) | |
8223 | return; | |
8224 | i.prefix[LOCK_PREFIX] = 0; | |
8225 | } | |
8226 | ||
43234a1e L |
8227 | /* Since the VEX/EVEX prefix contains the implicit prefix, we |
8228 | don't need the explicit prefix. */ | |
8229 | if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex) | |
bc4bd9ab | 8230 | { |
c0f3af97 | 8231 | switch (i.tm.opcode_length) |
bc4bd9ab | 8232 | { |
c0f3af97 L |
8233 | case 3: |
8234 | if (i.tm.base_opcode & 0xff000000) | |
4dffcebc | 8235 | { |
c0f3af97 | 8236 | prefix = (i.tm.base_opcode >> 24) & 0xff; |
bd59a631 | 8237 | add_prefix (prefix); |
c0f3af97 L |
8238 | } |
8239 | break; | |
8240 | case 2: | |
8241 | if ((i.tm.base_opcode & 0xff0000) != 0) | |
8242 | { | |
8243 | prefix = (i.tm.base_opcode >> 16) & 0xff; | |
bd59a631 JB |
8244 | if (!i.tm.cpu_flags.bitfield.cpupadlock |
8245 | || prefix != REPE_PREFIX_OPCODE | |
8246 | || (i.prefix[REP_PREFIX] != REPE_PREFIX_OPCODE)) | |
4dffcebc L |
8247 | add_prefix (prefix); |
8248 | } | |
c0f3af97 L |
8249 | break; |
8250 | case 1: | |
8251 | break; | |
390c91cf L |
8252 | case 0: |
8253 | /* Check for pseudo prefixes. */ | |
8254 | as_bad_where (insn_start_frag->fr_file, | |
8255 | insn_start_frag->fr_line, | |
8256 | _("pseudo prefix without instruction")); | |
8257 | return; | |
c0f3af97 L |
8258 | default: |
8259 | abort (); | |
bc4bd9ab | 8260 | } |
c0f3af97 | 8261 | |
6d19a37a | 8262 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
cf61b747 L |
8263 | /* For x32, add a dummy REX_OPCODE prefix for mov/add with |
8264 | R_X86_64_GOTTPOFF relocation so that linker can safely | |
8265 | perform IE->LE optimization. */ | |
8266 | if (x86_elf_abi == X86_64_X32_ABI | |
8267 | && i.operands == 2 | |
8268 | && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF | |
8269 | && i.prefix[REX_PREFIX] == 0) | |
8270 | add_prefix (REX_OPCODE); | |
6d19a37a | 8271 | #endif |
cf61b747 | 8272 | |
c0f3af97 L |
8273 | /* The prefix bytes. */ |
8274 | for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) | |
8275 | if (*q) | |
8276 | FRAG_APPEND_1_CHAR (*q); | |
0f10071e | 8277 | } |
ae5c1c7b | 8278 | else |
c0f3af97 L |
8279 | { |
8280 | for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++) | |
8281 | if (*q) | |
8282 | switch (j) | |
8283 | { | |
8284 | case REX_PREFIX: | |
8285 | /* REX byte is encoded in VEX prefix. */ | |
8286 | break; | |
8287 | case SEG_PREFIX: | |
8288 | case ADDR_PREFIX: | |
8289 | FRAG_APPEND_1_CHAR (*q); | |
8290 | break; | |
8291 | default: | |
8292 | /* There should be no other prefixes for instructions | |
8293 | with VEX prefix. */ | |
8294 | abort (); | |
8295 | } | |
8296 | ||
43234a1e L |
8297 | /* For EVEX instructions i.vrex should become 0 after |
8298 | build_evex_prefix. For VEX instructions upper 16 registers | |
8299 | aren't available, so VREX should be 0. */ | |
8300 | if (i.vrex) | |
8301 | abort (); | |
c0f3af97 L |
8302 | /* Now the VEX prefix. */ |
8303 | p = frag_more (i.vex.length); | |
8304 | for (j = 0; j < i.vex.length; j++) | |
8305 | p[j] = i.vex.bytes[j]; | |
8306 | } | |
252b5132 | 8307 | |
29b0f896 | 8308 | /* Now the opcode; be careful about word order here! */ |
4dffcebc | 8309 | if (i.tm.opcode_length == 1) |
29b0f896 AM |
8310 | { |
8311 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
8312 | } | |
8313 | else | |
8314 | { | |
4dffcebc | 8315 | switch (i.tm.opcode_length) |
331d2d0d | 8316 | { |
43234a1e L |
8317 | case 4: |
8318 | p = frag_more (4); | |
8319 | *p++ = (i.tm.base_opcode >> 24) & 0xff; | |
8320 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
8321 | break; | |
4dffcebc | 8322 | case 3: |
331d2d0d L |
8323 | p = frag_more (3); |
8324 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
4dffcebc L |
8325 | break; |
8326 | case 2: | |
8327 | p = frag_more (2); | |
8328 | break; | |
8329 | default: | |
8330 | abort (); | |
8331 | break; | |
331d2d0d | 8332 | } |
0f10071e | 8333 | |
29b0f896 AM |
8334 | /* Put out high byte first: can't use md_number_to_chars! */ |
8335 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
8336 | *p = i.tm.base_opcode & 0xff; | |
8337 | } | |
3e73aa7c | 8338 | |
29b0f896 | 8339 | /* Now the modrm byte and sib byte (if present). */ |
40fb9820 | 8340 | if (i.tm.opcode_modifier.modrm) |
29b0f896 | 8341 | { |
4a3523fa L |
8342 | FRAG_APPEND_1_CHAR ((i.rm.regmem << 0 |
8343 | | i.rm.reg << 3 | |
8344 | | i.rm.mode << 6)); | |
29b0f896 AM |
8345 | /* If i.rm.regmem == ESP (4) |
8346 | && i.rm.mode != (Register mode) | |
8347 | && not 16 bit | |
8348 | ==> need second modrm byte. */ | |
8349 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
8350 | && i.rm.mode != 3 | |
dc821c5f | 8351 | && !(i.base_reg && i.base_reg->reg_type.bitfield.word)) |
4a3523fa L |
8352 | FRAG_APPEND_1_CHAR ((i.sib.base << 0 |
8353 | | i.sib.index << 3 | |
8354 | | i.sib.scale << 6)); | |
29b0f896 | 8355 | } |
3e73aa7c | 8356 | |
29b0f896 | 8357 | if (i.disp_operands) |
2bbd9c25 | 8358 | output_disp (insn_start_frag, insn_start_off); |
3e73aa7c | 8359 | |
29b0f896 | 8360 | if (i.imm_operands) |
2bbd9c25 | 8361 | output_imm (insn_start_frag, insn_start_off); |
29b0f896 | 8362 | } |
252b5132 | 8363 | |
29b0f896 AM |
8364 | #ifdef DEBUG386 |
8365 | if (flag_debug) | |
8366 | { | |
7b81dfbb | 8367 | pi ("" /*line*/, &i); |
29b0f896 AM |
8368 | } |
8369 | #endif /* DEBUG386 */ | |
8370 | } | |
252b5132 | 8371 | |
e205caa7 L |
8372 | /* Return the size of the displacement operand N. */ |
8373 | ||
8374 | static int | |
8375 | disp_size (unsigned int n) | |
8376 | { | |
8377 | int size = 4; | |
43234a1e | 8378 | |
b5014f7a | 8379 | if (i.types[n].bitfield.disp64) |
40fb9820 L |
8380 | size = 8; |
8381 | else if (i.types[n].bitfield.disp8) | |
8382 | size = 1; | |
8383 | else if (i.types[n].bitfield.disp16) | |
8384 | size = 2; | |
e205caa7 L |
8385 | return size; |
8386 | } | |
8387 | ||
8388 | /* Return the size of the immediate operand N. */ | |
8389 | ||
8390 | static int | |
8391 | imm_size (unsigned int n) | |
8392 | { | |
8393 | int size = 4; | |
40fb9820 L |
8394 | if (i.types[n].bitfield.imm64) |
8395 | size = 8; | |
8396 | else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) | |
8397 | size = 1; | |
8398 | else if (i.types[n].bitfield.imm16) | |
8399 | size = 2; | |
e205caa7 L |
8400 | return size; |
8401 | } | |
8402 | ||
29b0f896 | 8403 | static void |
64e74474 | 8404 | output_disp (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
8405 | { |
8406 | char *p; | |
8407 | unsigned int n; | |
252b5132 | 8408 | |
29b0f896 AM |
8409 | for (n = 0; n < i.operands; n++) |
8410 | { | |
b5014f7a | 8411 | if (operand_type_check (i.types[n], disp)) |
29b0f896 AM |
8412 | { |
8413 | if (i.op[n].disps->X_op == O_constant) | |
8414 | { | |
e205caa7 | 8415 | int size = disp_size (n); |
43234a1e | 8416 | offsetT val = i.op[n].disps->X_add_number; |
252b5132 | 8417 | |
629cfaf1 JB |
8418 | val = offset_in_range (val >> (size == 1 ? i.memshift : 0), |
8419 | size); | |
29b0f896 AM |
8420 | p = frag_more (size); |
8421 | md_number_to_chars (p, val, size); | |
8422 | } | |
8423 | else | |
8424 | { | |
f86103b7 | 8425 | enum bfd_reloc_code_real reloc_type; |
e205caa7 | 8426 | int size = disp_size (n); |
40fb9820 | 8427 | int sign = i.types[n].bitfield.disp32s; |
29b0f896 | 8428 | int pcrel = (i.flags[n] & Operand_PCrel) != 0; |
02a86693 | 8429 | fixS *fixP; |
29b0f896 | 8430 | |
e205caa7 | 8431 | /* We can't have 8 bit displacement here. */ |
9c2799c2 | 8432 | gas_assert (!i.types[n].bitfield.disp8); |
e205caa7 | 8433 | |
29b0f896 AM |
8434 | /* The PC relative address is computed relative |
8435 | to the instruction boundary, so in case immediate | |
8436 | fields follows, we need to adjust the value. */ | |
8437 | if (pcrel && i.imm_operands) | |
8438 | { | |
29b0f896 | 8439 | unsigned int n1; |
e205caa7 | 8440 | int sz = 0; |
252b5132 | 8441 | |
29b0f896 | 8442 | for (n1 = 0; n1 < i.operands; n1++) |
40fb9820 | 8443 | if (operand_type_check (i.types[n1], imm)) |
252b5132 | 8444 | { |
e205caa7 L |
8445 | /* Only one immediate is allowed for PC |
8446 | relative address. */ | |
9c2799c2 | 8447 | gas_assert (sz == 0); |
e205caa7 L |
8448 | sz = imm_size (n1); |
8449 | i.op[n].disps->X_add_number -= sz; | |
252b5132 | 8450 | } |
29b0f896 | 8451 | /* We should find the immediate. */ |
9c2799c2 | 8452 | gas_assert (sz != 0); |
29b0f896 | 8453 | } |
520dc8e8 | 8454 | |
29b0f896 | 8455 | p = frag_more (size); |
d258b828 | 8456 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
d6ab8113 | 8457 | if (GOT_symbol |
2bbd9c25 | 8458 | && GOT_symbol == i.op[n].disps->X_add_symbol |
d6ab8113 | 8459 | && (((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
8460 | || reloc_type == BFD_RELOC_X86_64_32S |
8461 | || (reloc_type == BFD_RELOC_64 | |
8462 | && object_64bit)) | |
d6ab8113 JB |
8463 | && (i.op[n].disps->X_op == O_symbol |
8464 | || (i.op[n].disps->X_op == O_add | |
8465 | && ((symbol_get_value_expression | |
8466 | (i.op[n].disps->X_op_symbol)->X_op) | |
8467 | == O_subtract)))) | |
8468 | || reloc_type == BFD_RELOC_32_PCREL)) | |
2bbd9c25 JJ |
8469 | { |
8470 | offsetT add; | |
8471 | ||
8472 | if (insn_start_frag == frag_now) | |
8473 | add = (p - frag_now->fr_literal) - insn_start_off; | |
8474 | else | |
8475 | { | |
8476 | fragS *fr; | |
8477 | ||
8478 | add = insn_start_frag->fr_fix - insn_start_off; | |
8479 | for (fr = insn_start_frag->fr_next; | |
8480 | fr && fr != frag_now; fr = fr->fr_next) | |
8481 | add += fr->fr_fix; | |
8482 | add += p - frag_now->fr_literal; | |
8483 | } | |
8484 | ||
4fa24527 | 8485 | if (!object_64bit) |
7b81dfbb AJ |
8486 | { |
8487 | reloc_type = BFD_RELOC_386_GOTPC; | |
8488 | i.op[n].imms->X_add_number += add; | |
8489 | } | |
8490 | else if (reloc_type == BFD_RELOC_64) | |
8491 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
d6ab8113 | 8492 | else |
7b81dfbb AJ |
8493 | /* Don't do the adjustment for x86-64, as there |
8494 | the pcrel addressing is relative to the _next_ | |
8495 | insn, and that is taken care of in other code. */ | |
d6ab8113 | 8496 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
2bbd9c25 | 8497 | } |
02a86693 L |
8498 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, |
8499 | size, i.op[n].disps, pcrel, | |
8500 | reloc_type); | |
8501 | /* Check for "call/jmp *mem", "mov mem, %reg", | |
8502 | "test %reg, mem" and "binop mem, %reg" where binop | |
8503 | is one of adc, add, and, cmp, or, sbb, sub, xor | |
e60f4d3b L |
8504 | instructions without data prefix. Always generate |
8505 | R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */ | |
8506 | if (i.prefix[DATA_PREFIX] == 0 | |
8507 | && (generate_relax_relocations | |
8508 | || (!object_64bit | |
8509 | && i.rm.mode == 0 | |
8510 | && i.rm.regmem == 5)) | |
0cb4071e L |
8511 | && (i.rm.mode == 2 |
8512 | || (i.rm.mode == 0 && i.rm.regmem == 5)) | |
02a86693 L |
8513 | && ((i.operands == 1 |
8514 | && i.tm.base_opcode == 0xff | |
8515 | && (i.rm.reg == 2 || i.rm.reg == 4)) | |
8516 | || (i.operands == 2 | |
8517 | && (i.tm.base_opcode == 0x8b | |
8518 | || i.tm.base_opcode == 0x85 | |
8519 | || (i.tm.base_opcode & 0xc7) == 0x03)))) | |
8520 | { | |
8521 | if (object_64bit) | |
8522 | { | |
8523 | fixP->fx_tcbit = i.rex != 0; | |
8524 | if (i.base_reg | |
e968fc9b | 8525 | && (i.base_reg->reg_num == RegIP)) |
02a86693 L |
8526 | fixP->fx_tcbit2 = 1; |
8527 | } | |
8528 | else | |
8529 | fixP->fx_tcbit2 = 1; | |
8530 | } | |
29b0f896 AM |
8531 | } |
8532 | } | |
8533 | } | |
8534 | } | |
252b5132 | 8535 | |
29b0f896 | 8536 | static void |
64e74474 | 8537 | output_imm (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
8538 | { |
8539 | char *p; | |
8540 | unsigned int n; | |
252b5132 | 8541 | |
29b0f896 AM |
8542 | for (n = 0; n < i.operands; n++) |
8543 | { | |
43234a1e L |
8544 | /* Skip SAE/RC Imm operand in EVEX. They are already handled. */ |
8545 | if (i.rounding && (int) n == i.rounding->operand) | |
8546 | continue; | |
8547 | ||
40fb9820 | 8548 | if (operand_type_check (i.types[n], imm)) |
29b0f896 AM |
8549 | { |
8550 | if (i.op[n].imms->X_op == O_constant) | |
8551 | { | |
e205caa7 | 8552 | int size = imm_size (n); |
29b0f896 | 8553 | offsetT val; |
b4cac588 | 8554 | |
29b0f896 AM |
8555 | val = offset_in_range (i.op[n].imms->X_add_number, |
8556 | size); | |
8557 | p = frag_more (size); | |
8558 | md_number_to_chars (p, val, size); | |
8559 | } | |
8560 | else | |
8561 | { | |
8562 | /* Not absolute_section. | |
8563 | Need a 32-bit fixup (don't support 8bit | |
8564 | non-absolute imms). Try to support other | |
8565 | sizes ... */ | |
f86103b7 | 8566 | enum bfd_reloc_code_real reloc_type; |
e205caa7 L |
8567 | int size = imm_size (n); |
8568 | int sign; | |
29b0f896 | 8569 | |
40fb9820 | 8570 | if (i.types[n].bitfield.imm32s |
a7d61044 | 8571 | && (i.suffix == QWORD_MNEM_SUFFIX |
40fb9820 | 8572 | || (!i.suffix && i.tm.opcode_modifier.no_lsuf))) |
29b0f896 | 8573 | sign = 1; |
e205caa7 L |
8574 | else |
8575 | sign = 0; | |
520dc8e8 | 8576 | |
29b0f896 | 8577 | p = frag_more (size); |
d258b828 | 8578 | reloc_type = reloc (size, 0, sign, i.reloc[n]); |
f86103b7 | 8579 | |
2bbd9c25 JJ |
8580 | /* This is tough to explain. We end up with this one if we |
8581 | * have operands that look like | |
8582 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to | |
8583 | * obtain the absolute address of the GOT, and it is strongly | |
8584 | * preferable from a performance point of view to avoid using | |
8585 | * a runtime relocation for this. The actual sequence of | |
8586 | * instructions often look something like: | |
8587 | * | |
8588 | * call .L66 | |
8589 | * .L66: | |
8590 | * popl %ebx | |
8591 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
8592 | * | |
8593 | * The call and pop essentially return the absolute address | |
8594 | * of the label .L66 and store it in %ebx. The linker itself | |
8595 | * will ultimately change the first operand of the addl so | |
8596 | * that %ebx points to the GOT, but to keep things simple, the | |
8597 | * .o file must have this operand set so that it generates not | |
8598 | * the absolute address of .L66, but the absolute address of | |
8599 | * itself. This allows the linker itself simply treat a GOTPC | |
8600 | * relocation as asking for a pcrel offset to the GOT to be | |
8601 | * added in, and the addend of the relocation is stored in the | |
8602 | * operand field for the instruction itself. | |
8603 | * | |
8604 | * Our job here is to fix the operand so that it would add | |
8605 | * the correct offset so that %ebx would point to itself. The | |
8606 | * thing that is tricky is that .-.L66 will point to the | |
8607 | * beginning of the instruction, so we need to further modify | |
8608 | * the operand so that it will point to itself. There are | |
8609 | * other cases where you have something like: | |
8610 | * | |
8611 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
8612 | * | |
8613 | * and here no correction would be required. Internally in | |
8614 | * the assembler we treat operands of this form as not being | |
8615 | * pcrel since the '.' is explicitly mentioned, and I wonder | |
8616 | * whether it would simplify matters to do it this way. Who | |
8617 | * knows. In earlier versions of the PIC patches, the | |
8618 | * pcrel_adjust field was used to store the correction, but | |
8619 | * since the expression is not pcrel, I felt it would be | |
8620 | * confusing to do it this way. */ | |
8621 | ||
d6ab8113 | 8622 | if ((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
8623 | || reloc_type == BFD_RELOC_X86_64_32S |
8624 | || reloc_type == BFD_RELOC_64) | |
29b0f896 AM |
8625 | && GOT_symbol |
8626 | && GOT_symbol == i.op[n].imms->X_add_symbol | |
8627 | && (i.op[n].imms->X_op == O_symbol | |
8628 | || (i.op[n].imms->X_op == O_add | |
8629 | && ((symbol_get_value_expression | |
8630 | (i.op[n].imms->X_op_symbol)->X_op) | |
8631 | == O_subtract)))) | |
8632 | { | |
2bbd9c25 JJ |
8633 | offsetT add; |
8634 | ||
8635 | if (insn_start_frag == frag_now) | |
8636 | add = (p - frag_now->fr_literal) - insn_start_off; | |
8637 | else | |
8638 | { | |
8639 | fragS *fr; | |
8640 | ||
8641 | add = insn_start_frag->fr_fix - insn_start_off; | |
8642 | for (fr = insn_start_frag->fr_next; | |
8643 | fr && fr != frag_now; fr = fr->fr_next) | |
8644 | add += fr->fr_fix; | |
8645 | add += p - frag_now->fr_literal; | |
8646 | } | |
8647 | ||
4fa24527 | 8648 | if (!object_64bit) |
d6ab8113 | 8649 | reloc_type = BFD_RELOC_386_GOTPC; |
7b81dfbb | 8650 | else if (size == 4) |
d6ab8113 | 8651 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
7b81dfbb AJ |
8652 | else if (size == 8) |
8653 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
2bbd9c25 | 8654 | i.op[n].imms->X_add_number += add; |
29b0f896 | 8655 | } |
29b0f896 AM |
8656 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
8657 | i.op[n].imms, 0, reloc_type); | |
8658 | } | |
8659 | } | |
8660 | } | |
252b5132 RH |
8661 | } |
8662 | \f | |
d182319b JB |
8663 | /* x86_cons_fix_new is called via the expression parsing code when a |
8664 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
d182319b JB |
8665 | static int cons_sign = -1; |
8666 | ||
8667 | void | |
e3bb37b5 | 8668 | x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, |
62ebcb5c | 8669 | expressionS *exp, bfd_reloc_code_real_type r) |
d182319b | 8670 | { |
d258b828 | 8671 | r = reloc (len, 0, cons_sign, r); |
d182319b JB |
8672 | |
8673 | #ifdef TE_PE | |
8674 | if (exp->X_op == O_secrel) | |
8675 | { | |
8676 | exp->X_op = O_symbol; | |
8677 | r = BFD_RELOC_32_SECREL; | |
8678 | } | |
8679 | #endif | |
8680 | ||
8681 | fix_new_exp (frag, off, len, exp, 0, r); | |
8682 | } | |
8683 | ||
357d1bd8 L |
8684 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
8685 | purpose of the `.dc.a' internal pseudo-op. */ | |
8686 | ||
8687 | int | |
8688 | x86_address_bytes (void) | |
8689 | { | |
8690 | if ((stdoutput->arch_info->mach & bfd_mach_x64_32)) | |
8691 | return 4; | |
8692 | return stdoutput->arch_info->bits_per_address / 8; | |
8693 | } | |
8694 | ||
d382c579 TG |
8695 | #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \ |
8696 | || defined (LEX_AT) | |
d258b828 | 8697 | # define lex_got(reloc, adjust, types) NULL |
718ddfc0 | 8698 | #else |
f3c180ae AM |
8699 | /* Parse operands of the form |
8700 | <symbol>@GOTOFF+<nnn> | |
8701 | and similar .plt or .got references. | |
8702 | ||
8703 | If we find one, set up the correct relocation in RELOC and copy the | |
8704 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
8705 | parsing by the calling routine. Return this buffer, and if ADJUST | |
8706 | is non-null set it to the length of the string we removed from the | |
8707 | input line. Otherwise return NULL. */ | |
8708 | static char * | |
91d6fa6a | 8709 | lex_got (enum bfd_reloc_code_real *rel, |
64e74474 | 8710 | int *adjust, |
d258b828 | 8711 | i386_operand_type *types) |
f3c180ae | 8712 | { |
7b81dfbb AJ |
8713 | /* Some of the relocations depend on the size of what field is to |
8714 | be relocated. But in our callers i386_immediate and i386_displacement | |
8715 | we don't yet know the operand size (this will be set by insn | |
8716 | matching). Hence we record the word32 relocation here, | |
8717 | and adjust the reloc according to the real size in reloc(). */ | |
f3c180ae AM |
8718 | static const struct { |
8719 | const char *str; | |
cff8d58a | 8720 | int len; |
4fa24527 | 8721 | const enum bfd_reloc_code_real rel[2]; |
40fb9820 | 8722 | const i386_operand_type types64; |
f3c180ae | 8723 | } gotrel[] = { |
8ce3d284 | 8724 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
8725 | { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32, |
8726 | BFD_RELOC_SIZE32 }, | |
8727 | OPERAND_TYPE_IMM32_64 }, | |
8ce3d284 | 8728 | #endif |
cff8d58a L |
8729 | { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real, |
8730 | BFD_RELOC_X86_64_PLTOFF64 }, | |
40fb9820 | 8731 | OPERAND_TYPE_IMM64 }, |
cff8d58a L |
8732 | { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32, |
8733 | BFD_RELOC_X86_64_PLT32 }, | |
40fb9820 | 8734 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8735 | { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real, |
8736 | BFD_RELOC_X86_64_GOTPLT64 }, | |
40fb9820 | 8737 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
8738 | { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF, |
8739 | BFD_RELOC_X86_64_GOTOFF64 }, | |
40fb9820 | 8740 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
8741 | { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real, |
8742 | BFD_RELOC_X86_64_GOTPCREL }, | |
40fb9820 | 8743 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8744 | { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD, |
8745 | BFD_RELOC_X86_64_TLSGD }, | |
40fb9820 | 8746 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8747 | { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM, |
8748 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 8749 | OPERAND_TYPE_NONE }, |
cff8d58a L |
8750 | { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real, |
8751 | BFD_RELOC_X86_64_TLSLD }, | |
40fb9820 | 8752 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8753 | { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32, |
8754 | BFD_RELOC_X86_64_GOTTPOFF }, | |
40fb9820 | 8755 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8756 | { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32, |
8757 | BFD_RELOC_X86_64_TPOFF32 }, | |
40fb9820 | 8758 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
8759 | { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE, |
8760 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 8761 | OPERAND_TYPE_NONE }, |
cff8d58a L |
8762 | { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32, |
8763 | BFD_RELOC_X86_64_DTPOFF32 }, | |
40fb9820 | 8764 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
8765 | { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE, |
8766 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 8767 | OPERAND_TYPE_NONE }, |
cff8d58a L |
8768 | { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE, |
8769 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 8770 | OPERAND_TYPE_NONE }, |
cff8d58a L |
8771 | { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32, |
8772 | BFD_RELOC_X86_64_GOT32 }, | |
40fb9820 | 8773 | OPERAND_TYPE_IMM32_32S_64_DISP32 }, |
cff8d58a L |
8774 | { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC, |
8775 | BFD_RELOC_X86_64_GOTPC32_TLSDESC }, | |
40fb9820 | 8776 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8777 | { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL, |
8778 | BFD_RELOC_X86_64_TLSDESC_CALL }, | |
40fb9820 | 8779 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
f3c180ae AM |
8780 | }; |
8781 | char *cp; | |
8782 | unsigned int j; | |
8783 | ||
d382c579 | 8784 | #if defined (OBJ_MAYBE_ELF) |
718ddfc0 JB |
8785 | if (!IS_ELF) |
8786 | return NULL; | |
d382c579 | 8787 | #endif |
718ddfc0 | 8788 | |
f3c180ae | 8789 | for (cp = input_line_pointer; *cp != '@'; cp++) |
67c11a9b | 8790 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') |
f3c180ae AM |
8791 | return NULL; |
8792 | ||
47465058 | 8793 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) |
f3c180ae | 8794 | { |
cff8d58a | 8795 | int len = gotrel[j].len; |
28f81592 | 8796 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae | 8797 | { |
4fa24527 | 8798 | if (gotrel[j].rel[object_64bit] != 0) |
f3c180ae | 8799 | { |
28f81592 AM |
8800 | int first, second; |
8801 | char *tmpbuf, *past_reloc; | |
f3c180ae | 8802 | |
91d6fa6a | 8803 | *rel = gotrel[j].rel[object_64bit]; |
f3c180ae | 8804 | |
3956db08 JB |
8805 | if (types) |
8806 | { | |
8807 | if (flag_code != CODE_64BIT) | |
40fb9820 L |
8808 | { |
8809 | types->bitfield.imm32 = 1; | |
8810 | types->bitfield.disp32 = 1; | |
8811 | } | |
3956db08 JB |
8812 | else |
8813 | *types = gotrel[j].types64; | |
8814 | } | |
8815 | ||
8fd4256d | 8816 | if (j != 0 && GOT_symbol == NULL) |
f3c180ae AM |
8817 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); |
8818 | ||
28f81592 | 8819 | /* The length of the first part of our input line. */ |
f3c180ae | 8820 | first = cp - input_line_pointer; |
28f81592 AM |
8821 | |
8822 | /* The second part goes from after the reloc token until | |
67c11a9b | 8823 | (and including) an end_of_line char or comma. */ |
28f81592 | 8824 | past_reloc = cp + 1 + len; |
67c11a9b AM |
8825 | cp = past_reloc; |
8826 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
8827 | ++cp; | |
8828 | second = cp + 1 - past_reloc; | |
28f81592 AM |
8829 | |
8830 | /* Allocate and copy string. The trailing NUL shouldn't | |
8831 | be necessary, but be safe. */ | |
add39d23 | 8832 | tmpbuf = XNEWVEC (char, first + second + 2); |
f3c180ae | 8833 | memcpy (tmpbuf, input_line_pointer, first); |
0787a12d AM |
8834 | if (second != 0 && *past_reloc != ' ') |
8835 | /* Replace the relocation token with ' ', so that | |
8836 | errors like foo@GOTOFF1 will be detected. */ | |
8837 | tmpbuf[first++] = ' '; | |
af89796a L |
8838 | else |
8839 | /* Increment length by 1 if the relocation token is | |
8840 | removed. */ | |
8841 | len++; | |
8842 | if (adjust) | |
8843 | *adjust = len; | |
0787a12d AM |
8844 | memcpy (tmpbuf + first, past_reloc, second); |
8845 | tmpbuf[first + second] = '\0'; | |
f3c180ae AM |
8846 | return tmpbuf; |
8847 | } | |
8848 | ||
4fa24527 JB |
8849 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
8850 | gotrel[j].str, 1 << (5 + object_64bit)); | |
f3c180ae AM |
8851 | return NULL; |
8852 | } | |
8853 | } | |
8854 | ||
8855 | /* Might be a symbol version string. Don't as_bad here. */ | |
8856 | return NULL; | |
8857 | } | |
4e4f7c87 | 8858 | #endif |
f3c180ae | 8859 | |
a988325c NC |
8860 | #ifdef TE_PE |
8861 | #ifdef lex_got | |
8862 | #undef lex_got | |
8863 | #endif | |
8864 | /* Parse operands of the form | |
8865 | <symbol>@SECREL32+<nnn> | |
8866 | ||
8867 | If we find one, set up the correct relocation in RELOC and copy the | |
8868 | input string, minus the `@SECREL32' into a malloc'd buffer for | |
8869 | parsing by the calling routine. Return this buffer, and if ADJUST | |
8870 | is non-null set it to the length of the string we removed from the | |
34bca508 L |
8871 | input line. Otherwise return NULL. |
8872 | ||
a988325c NC |
8873 | This function is copied from the ELF version above adjusted for PE targets. */ |
8874 | ||
8875 | static char * | |
8876 | lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED, | |
8877 | int *adjust ATTRIBUTE_UNUSED, | |
d258b828 | 8878 | i386_operand_type *types) |
a988325c NC |
8879 | { |
8880 | static const struct | |
8881 | { | |
8882 | const char *str; | |
8883 | int len; | |
8884 | const enum bfd_reloc_code_real rel[2]; | |
8885 | const i386_operand_type types64; | |
8886 | } | |
8887 | gotrel[] = | |
8888 | { | |
8889 | { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL, | |
8890 | BFD_RELOC_32_SECREL }, | |
8891 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, | |
8892 | }; | |
8893 | ||
8894 | char *cp; | |
8895 | unsigned j; | |
8896 | ||
8897 | for (cp = input_line_pointer; *cp != '@'; cp++) | |
8898 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') | |
8899 | return NULL; | |
8900 | ||
8901 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) | |
8902 | { | |
8903 | int len = gotrel[j].len; | |
8904 | ||
8905 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) | |
8906 | { | |
8907 | if (gotrel[j].rel[object_64bit] != 0) | |
8908 | { | |
8909 | int first, second; | |
8910 | char *tmpbuf, *past_reloc; | |
8911 | ||
8912 | *rel = gotrel[j].rel[object_64bit]; | |
8913 | if (adjust) | |
8914 | *adjust = len; | |
8915 | ||
8916 | if (types) | |
8917 | { | |
8918 | if (flag_code != CODE_64BIT) | |
8919 | { | |
8920 | types->bitfield.imm32 = 1; | |
8921 | types->bitfield.disp32 = 1; | |
8922 | } | |
8923 | else | |
8924 | *types = gotrel[j].types64; | |
8925 | } | |
8926 | ||
8927 | /* The length of the first part of our input line. */ | |
8928 | first = cp - input_line_pointer; | |
8929 | ||
8930 | /* The second part goes from after the reloc token until | |
8931 | (and including) an end_of_line char or comma. */ | |
8932 | past_reloc = cp + 1 + len; | |
8933 | cp = past_reloc; | |
8934 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
8935 | ++cp; | |
8936 | second = cp + 1 - past_reloc; | |
8937 | ||
8938 | /* Allocate and copy string. The trailing NUL shouldn't | |
8939 | be necessary, but be safe. */ | |
add39d23 | 8940 | tmpbuf = XNEWVEC (char, first + second + 2); |
a988325c NC |
8941 | memcpy (tmpbuf, input_line_pointer, first); |
8942 | if (second != 0 && *past_reloc != ' ') | |
8943 | /* Replace the relocation token with ' ', so that | |
8944 | errors like foo@SECLREL321 will be detected. */ | |
8945 | tmpbuf[first++] = ' '; | |
8946 | memcpy (tmpbuf + first, past_reloc, second); | |
8947 | tmpbuf[first + second] = '\0'; | |
8948 | return tmpbuf; | |
8949 | } | |
8950 | ||
8951 | as_bad (_("@%s reloc is not supported with %d-bit output format"), | |
8952 | gotrel[j].str, 1 << (5 + object_64bit)); | |
8953 | return NULL; | |
8954 | } | |
8955 | } | |
8956 | ||
8957 | /* Might be a symbol version string. Don't as_bad here. */ | |
8958 | return NULL; | |
8959 | } | |
8960 | ||
8961 | #endif /* TE_PE */ | |
8962 | ||
62ebcb5c | 8963 | bfd_reloc_code_real_type |
e3bb37b5 | 8964 | x86_cons (expressionS *exp, int size) |
f3c180ae | 8965 | { |
62ebcb5c AM |
8966 | bfd_reloc_code_real_type got_reloc = NO_RELOC; |
8967 | ||
ee86248c JB |
8968 | intel_syntax = -intel_syntax; |
8969 | ||
3c7b9c2c | 8970 | exp->X_md = 0; |
4fa24527 | 8971 | if (size == 4 || (object_64bit && size == 8)) |
f3c180ae AM |
8972 | { |
8973 | /* Handle @GOTOFF and the like in an expression. */ | |
8974 | char *save; | |
8975 | char *gotfree_input_line; | |
4a57f2cf | 8976 | int adjust = 0; |
f3c180ae AM |
8977 | |
8978 | save = input_line_pointer; | |
d258b828 | 8979 | gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); |
f3c180ae AM |
8980 | if (gotfree_input_line) |
8981 | input_line_pointer = gotfree_input_line; | |
8982 | ||
8983 | expression (exp); | |
8984 | ||
8985 | if (gotfree_input_line) | |
8986 | { | |
8987 | /* expression () has merrily parsed up to the end of line, | |
8988 | or a comma - in the wrong buffer. Transfer how far | |
8989 | input_line_pointer has moved to the right buffer. */ | |
8990 | input_line_pointer = (save | |
8991 | + (input_line_pointer - gotfree_input_line) | |
8992 | + adjust); | |
8993 | free (gotfree_input_line); | |
3992d3b7 AM |
8994 | if (exp->X_op == O_constant |
8995 | || exp->X_op == O_absent | |
8996 | || exp->X_op == O_illegal | |
0398aac5 | 8997 | || exp->X_op == O_register |
3992d3b7 AM |
8998 | || exp->X_op == O_big) |
8999 | { | |
9000 | char c = *input_line_pointer; | |
9001 | *input_line_pointer = 0; | |
9002 | as_bad (_("missing or invalid expression `%s'"), save); | |
9003 | *input_line_pointer = c; | |
9004 | } | |
b9519cfe L |
9005 | else if ((got_reloc == BFD_RELOC_386_PLT32 |
9006 | || got_reloc == BFD_RELOC_X86_64_PLT32) | |
9007 | && exp->X_op != O_symbol) | |
9008 | { | |
9009 | char c = *input_line_pointer; | |
9010 | *input_line_pointer = 0; | |
9011 | as_bad (_("invalid PLT expression `%s'"), save); | |
9012 | *input_line_pointer = c; | |
9013 | } | |
f3c180ae AM |
9014 | } |
9015 | } | |
9016 | else | |
9017 | expression (exp); | |
ee86248c JB |
9018 | |
9019 | intel_syntax = -intel_syntax; | |
9020 | ||
9021 | if (intel_syntax) | |
9022 | i386_intel_simplify (exp); | |
62ebcb5c AM |
9023 | |
9024 | return got_reloc; | |
f3c180ae | 9025 | } |
f3c180ae | 9026 | |
9f32dd5b L |
9027 | static void |
9028 | signed_cons (int size) | |
6482c264 | 9029 | { |
d182319b JB |
9030 | if (flag_code == CODE_64BIT) |
9031 | cons_sign = 1; | |
9032 | cons (size); | |
9033 | cons_sign = -1; | |
6482c264 NC |
9034 | } |
9035 | ||
d182319b | 9036 | #ifdef TE_PE |
6482c264 | 9037 | static void |
7016a5d5 | 9038 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
6482c264 NC |
9039 | { |
9040 | expressionS exp; | |
9041 | ||
9042 | do | |
9043 | { | |
9044 | expression (&exp); | |
9045 | if (exp.X_op == O_symbol) | |
9046 | exp.X_op = O_secrel; | |
9047 | ||
9048 | emit_expr (&exp, 4); | |
9049 | } | |
9050 | while (*input_line_pointer++ == ','); | |
9051 | ||
9052 | input_line_pointer--; | |
9053 | demand_empty_rest_of_line (); | |
9054 | } | |
6482c264 NC |
9055 | #endif |
9056 | ||
43234a1e L |
9057 | /* Handle Vector operations. */ |
9058 | ||
9059 | static char * | |
9060 | check_VecOperations (char *op_string, char *op_end) | |
9061 | { | |
9062 | const reg_entry *mask; | |
9063 | const char *saved; | |
9064 | char *end_op; | |
9065 | ||
9066 | while (*op_string | |
9067 | && (op_end == NULL || op_string < op_end)) | |
9068 | { | |
9069 | saved = op_string; | |
9070 | if (*op_string == '{') | |
9071 | { | |
9072 | op_string++; | |
9073 | ||
9074 | /* Check broadcasts. */ | |
9075 | if (strncmp (op_string, "1to", 3) == 0) | |
9076 | { | |
9077 | int bcst_type; | |
9078 | ||
9079 | if (i.broadcast) | |
9080 | goto duplicated_vec_op; | |
9081 | ||
9082 | op_string += 3; | |
9083 | if (*op_string == '8') | |
8e6e0792 | 9084 | bcst_type = 8; |
b28d1bda | 9085 | else if (*op_string == '4') |
8e6e0792 | 9086 | bcst_type = 4; |
b28d1bda | 9087 | else if (*op_string == '2') |
8e6e0792 | 9088 | bcst_type = 2; |
43234a1e L |
9089 | else if (*op_string == '1' |
9090 | && *(op_string+1) == '6') | |
9091 | { | |
8e6e0792 | 9092 | bcst_type = 16; |
43234a1e L |
9093 | op_string++; |
9094 | } | |
9095 | else | |
9096 | { | |
9097 | as_bad (_("Unsupported broadcast: `%s'"), saved); | |
9098 | return NULL; | |
9099 | } | |
9100 | op_string++; | |
9101 | ||
9102 | broadcast_op.type = bcst_type; | |
9103 | broadcast_op.operand = this_operand; | |
1f75763a | 9104 | broadcast_op.bytes = 0; |
43234a1e L |
9105 | i.broadcast = &broadcast_op; |
9106 | } | |
9107 | /* Check masking operation. */ | |
9108 | else if ((mask = parse_register (op_string, &end_op)) != NULL) | |
9109 | { | |
9110 | /* k0 can't be used for write mask. */ | |
6d2cd6b2 | 9111 | if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0) |
43234a1e | 9112 | { |
6d2cd6b2 JB |
9113 | as_bad (_("`%s%s' can't be used for write mask"), |
9114 | register_prefix, mask->reg_name); | |
43234a1e L |
9115 | return NULL; |
9116 | } | |
9117 | ||
9118 | if (!i.mask) | |
9119 | { | |
9120 | mask_op.mask = mask; | |
9121 | mask_op.zeroing = 0; | |
9122 | mask_op.operand = this_operand; | |
9123 | i.mask = &mask_op; | |
9124 | } | |
9125 | else | |
9126 | { | |
9127 | if (i.mask->mask) | |
9128 | goto duplicated_vec_op; | |
9129 | ||
9130 | i.mask->mask = mask; | |
9131 | ||
9132 | /* Only "{z}" is allowed here. No need to check | |
9133 | zeroing mask explicitly. */ | |
9134 | if (i.mask->operand != this_operand) | |
9135 | { | |
9136 | as_bad (_("invalid write mask `%s'"), saved); | |
9137 | return NULL; | |
9138 | } | |
9139 | } | |
9140 | ||
9141 | op_string = end_op; | |
9142 | } | |
9143 | /* Check zeroing-flag for masking operation. */ | |
9144 | else if (*op_string == 'z') | |
9145 | { | |
9146 | if (!i.mask) | |
9147 | { | |
9148 | mask_op.mask = NULL; | |
9149 | mask_op.zeroing = 1; | |
9150 | mask_op.operand = this_operand; | |
9151 | i.mask = &mask_op; | |
9152 | } | |
9153 | else | |
9154 | { | |
9155 | if (i.mask->zeroing) | |
9156 | { | |
9157 | duplicated_vec_op: | |
9158 | as_bad (_("duplicated `%s'"), saved); | |
9159 | return NULL; | |
9160 | } | |
9161 | ||
9162 | i.mask->zeroing = 1; | |
9163 | ||
9164 | /* Only "{%k}" is allowed here. No need to check mask | |
9165 | register explicitly. */ | |
9166 | if (i.mask->operand != this_operand) | |
9167 | { | |
9168 | as_bad (_("invalid zeroing-masking `%s'"), | |
9169 | saved); | |
9170 | return NULL; | |
9171 | } | |
9172 | } | |
9173 | ||
9174 | op_string++; | |
9175 | } | |
9176 | else | |
9177 | goto unknown_vec_op; | |
9178 | ||
9179 | if (*op_string != '}') | |
9180 | { | |
9181 | as_bad (_("missing `}' in `%s'"), saved); | |
9182 | return NULL; | |
9183 | } | |
9184 | op_string++; | |
0ba3a731 L |
9185 | |
9186 | /* Strip whitespace since the addition of pseudo prefixes | |
9187 | changed how the scrubber treats '{'. */ | |
9188 | if (is_space_char (*op_string)) | |
9189 | ++op_string; | |
9190 | ||
43234a1e L |
9191 | continue; |
9192 | } | |
9193 | unknown_vec_op: | |
9194 | /* We don't know this one. */ | |
9195 | as_bad (_("unknown vector operation: `%s'"), saved); | |
9196 | return NULL; | |
9197 | } | |
9198 | ||
6d2cd6b2 JB |
9199 | if (i.mask && i.mask->zeroing && !i.mask->mask) |
9200 | { | |
9201 | as_bad (_("zeroing-masking only allowed with write mask")); | |
9202 | return NULL; | |
9203 | } | |
9204 | ||
43234a1e L |
9205 | return op_string; |
9206 | } | |
9207 | ||
252b5132 | 9208 | static int |
70e41ade | 9209 | i386_immediate (char *imm_start) |
252b5132 RH |
9210 | { |
9211 | char *save_input_line_pointer; | |
f3c180ae | 9212 | char *gotfree_input_line; |
252b5132 | 9213 | segT exp_seg = 0; |
47926f60 | 9214 | expressionS *exp; |
40fb9820 L |
9215 | i386_operand_type types; |
9216 | ||
0dfbf9d7 | 9217 | operand_type_set (&types, ~0); |
252b5132 RH |
9218 | |
9219 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
9220 | { | |
31b2323c L |
9221 | as_bad (_("at most %d immediate operands are allowed"), |
9222 | MAX_IMMEDIATE_OPERANDS); | |
252b5132 RH |
9223 | return 0; |
9224 | } | |
9225 | ||
9226 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 9227 | i.op[this_operand].imms = exp; |
252b5132 RH |
9228 | |
9229 | if (is_space_char (*imm_start)) | |
9230 | ++imm_start; | |
9231 | ||
9232 | save_input_line_pointer = input_line_pointer; | |
9233 | input_line_pointer = imm_start; | |
9234 | ||
d258b828 | 9235 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
9236 | if (gotfree_input_line) |
9237 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
9238 | |
9239 | exp_seg = expression (exp); | |
9240 | ||
83183c0c | 9241 | SKIP_WHITESPACE (); |
43234a1e L |
9242 | |
9243 | /* Handle vector operations. */ | |
9244 | if (*input_line_pointer == '{') | |
9245 | { | |
9246 | input_line_pointer = check_VecOperations (input_line_pointer, | |
9247 | NULL); | |
9248 | if (input_line_pointer == NULL) | |
9249 | return 0; | |
9250 | } | |
9251 | ||
252b5132 | 9252 | if (*input_line_pointer) |
f3c180ae | 9253 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
9254 | |
9255 | input_line_pointer = save_input_line_pointer; | |
f3c180ae | 9256 | if (gotfree_input_line) |
ee86248c JB |
9257 | { |
9258 | free (gotfree_input_line); | |
9259 | ||
9260 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
9261 | exp->X_op = O_illegal; | |
9262 | } | |
9263 | ||
9264 | return i386_finalize_immediate (exp_seg, exp, types, imm_start); | |
9265 | } | |
252b5132 | 9266 | |
ee86248c JB |
9267 | static int |
9268 | i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
9269 | i386_operand_type types, const char *imm_start) | |
9270 | { | |
9271 | if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big) | |
252b5132 | 9272 | { |
313c53d1 L |
9273 | if (imm_start) |
9274 | as_bad (_("missing or invalid immediate expression `%s'"), | |
9275 | imm_start); | |
3992d3b7 | 9276 | return 0; |
252b5132 | 9277 | } |
3e73aa7c | 9278 | else if (exp->X_op == O_constant) |
252b5132 | 9279 | { |
47926f60 | 9280 | /* Size it properly later. */ |
40fb9820 | 9281 | i.types[this_operand].bitfield.imm64 = 1; |
13f864ae L |
9282 | /* If not 64bit, sign extend val. */ |
9283 | if (flag_code != CODE_64BIT | |
4eed87de AM |
9284 | && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) |
9285 | exp->X_add_number | |
9286 | = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
252b5132 | 9287 | } |
4c63da97 | 9288 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
f86103b7 | 9289 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 9290 | && exp_seg != absolute_section |
47926f60 | 9291 | && exp_seg != text_section |
24eab124 AM |
9292 | && exp_seg != data_section |
9293 | && exp_seg != bss_section | |
9294 | && exp_seg != undefined_section | |
f86103b7 | 9295 | && !bfd_is_com_section (exp_seg)) |
252b5132 | 9296 | { |
d0b47220 | 9297 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
252b5132 RH |
9298 | return 0; |
9299 | } | |
9300 | #endif | |
a841bdf5 | 9301 | else if (!intel_syntax && exp_seg == reg_section) |
bb8f5920 | 9302 | { |
313c53d1 L |
9303 | if (imm_start) |
9304 | as_bad (_("illegal immediate register operand %s"), imm_start); | |
bb8f5920 L |
9305 | return 0; |
9306 | } | |
252b5132 RH |
9307 | else |
9308 | { | |
9309 | /* This is an address. The size of the address will be | |
24eab124 | 9310 | determined later, depending on destination register, |
3e73aa7c | 9311 | suffix, or the default for the section. */ |
40fb9820 L |
9312 | i.types[this_operand].bitfield.imm8 = 1; |
9313 | i.types[this_operand].bitfield.imm16 = 1; | |
9314 | i.types[this_operand].bitfield.imm32 = 1; | |
9315 | i.types[this_operand].bitfield.imm32s = 1; | |
9316 | i.types[this_operand].bitfield.imm64 = 1; | |
c6fb90c8 L |
9317 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
9318 | types); | |
252b5132 RH |
9319 | } |
9320 | ||
9321 | return 1; | |
9322 | } | |
9323 | ||
551c1ca1 | 9324 | static char * |
e3bb37b5 | 9325 | i386_scale (char *scale) |
252b5132 | 9326 | { |
551c1ca1 AM |
9327 | offsetT val; |
9328 | char *save = input_line_pointer; | |
252b5132 | 9329 | |
551c1ca1 AM |
9330 | input_line_pointer = scale; |
9331 | val = get_absolute_expression (); | |
9332 | ||
9333 | switch (val) | |
252b5132 | 9334 | { |
551c1ca1 | 9335 | case 1: |
252b5132 RH |
9336 | i.log2_scale_factor = 0; |
9337 | break; | |
551c1ca1 | 9338 | case 2: |
252b5132 RH |
9339 | i.log2_scale_factor = 1; |
9340 | break; | |
551c1ca1 | 9341 | case 4: |
252b5132 RH |
9342 | i.log2_scale_factor = 2; |
9343 | break; | |
551c1ca1 | 9344 | case 8: |
252b5132 RH |
9345 | i.log2_scale_factor = 3; |
9346 | break; | |
9347 | default: | |
a724f0f4 JB |
9348 | { |
9349 | char sep = *input_line_pointer; | |
9350 | ||
9351 | *input_line_pointer = '\0'; | |
9352 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
9353 | scale); | |
9354 | *input_line_pointer = sep; | |
9355 | input_line_pointer = save; | |
9356 | return NULL; | |
9357 | } | |
252b5132 | 9358 | } |
29b0f896 | 9359 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
252b5132 RH |
9360 | { |
9361 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 9362 | 1 << i.log2_scale_factor); |
252b5132 | 9363 | i.log2_scale_factor = 0; |
252b5132 | 9364 | } |
551c1ca1 AM |
9365 | scale = input_line_pointer; |
9366 | input_line_pointer = save; | |
9367 | return scale; | |
252b5132 RH |
9368 | } |
9369 | ||
252b5132 | 9370 | static int |
e3bb37b5 | 9371 | i386_displacement (char *disp_start, char *disp_end) |
252b5132 | 9372 | { |
29b0f896 | 9373 | expressionS *exp; |
252b5132 RH |
9374 | segT exp_seg = 0; |
9375 | char *save_input_line_pointer; | |
f3c180ae | 9376 | char *gotfree_input_line; |
40fb9820 L |
9377 | int override; |
9378 | i386_operand_type bigdisp, types = anydisp; | |
3992d3b7 | 9379 | int ret; |
252b5132 | 9380 | |
31b2323c L |
9381 | if (i.disp_operands == MAX_MEMORY_OPERANDS) |
9382 | { | |
9383 | as_bad (_("at most %d displacement operands are allowed"), | |
9384 | MAX_MEMORY_OPERANDS); | |
9385 | return 0; | |
9386 | } | |
9387 | ||
0dfbf9d7 | 9388 | operand_type_set (&bigdisp, 0); |
40fb9820 L |
9389 | if ((i.types[this_operand].bitfield.jumpabsolute) |
9390 | || (!current_templates->start->opcode_modifier.jump | |
9391 | && !current_templates->start->opcode_modifier.jumpdword)) | |
e05278af | 9392 | { |
40fb9820 | 9393 | bigdisp.bitfield.disp32 = 1; |
e05278af | 9394 | override = (i.prefix[ADDR_PREFIX] != 0); |
40fb9820 L |
9395 | if (flag_code == CODE_64BIT) |
9396 | { | |
9397 | if (!override) | |
9398 | { | |
9399 | bigdisp.bitfield.disp32s = 1; | |
9400 | bigdisp.bitfield.disp64 = 1; | |
9401 | } | |
9402 | } | |
9403 | else if ((flag_code == CODE_16BIT) ^ override) | |
9404 | { | |
9405 | bigdisp.bitfield.disp32 = 0; | |
9406 | bigdisp.bitfield.disp16 = 1; | |
9407 | } | |
e05278af JB |
9408 | } |
9409 | else | |
9410 | { | |
9411 | /* For PC-relative branches, the width of the displacement | |
9412 | is dependent upon data size, not address size. */ | |
e05278af | 9413 | override = (i.prefix[DATA_PREFIX] != 0); |
40fb9820 L |
9414 | if (flag_code == CODE_64BIT) |
9415 | { | |
9416 | if (override || i.suffix == WORD_MNEM_SUFFIX) | |
9417 | bigdisp.bitfield.disp16 = 1; | |
9418 | else | |
9419 | { | |
9420 | bigdisp.bitfield.disp32 = 1; | |
9421 | bigdisp.bitfield.disp32s = 1; | |
9422 | } | |
9423 | } | |
9424 | else | |
e05278af JB |
9425 | { |
9426 | if (!override) | |
9427 | override = (i.suffix == (flag_code != CODE_16BIT | |
9428 | ? WORD_MNEM_SUFFIX | |
9429 | : LONG_MNEM_SUFFIX)); | |
40fb9820 L |
9430 | bigdisp.bitfield.disp32 = 1; |
9431 | if ((flag_code == CODE_16BIT) ^ override) | |
9432 | { | |
9433 | bigdisp.bitfield.disp32 = 0; | |
9434 | bigdisp.bitfield.disp16 = 1; | |
9435 | } | |
e05278af | 9436 | } |
e05278af | 9437 | } |
c6fb90c8 L |
9438 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
9439 | bigdisp); | |
252b5132 RH |
9440 | |
9441 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 9442 | i.op[this_operand].disps = exp; |
252b5132 RH |
9443 | i.disp_operands++; |
9444 | save_input_line_pointer = input_line_pointer; | |
9445 | input_line_pointer = disp_start; | |
9446 | END_STRING_AND_SAVE (disp_end); | |
9447 | ||
9448 | #ifndef GCC_ASM_O_HACK | |
9449 | #define GCC_ASM_O_HACK 0 | |
9450 | #endif | |
9451 | #if GCC_ASM_O_HACK | |
9452 | END_STRING_AND_SAVE (disp_end + 1); | |
40fb9820 | 9453 | if (i.types[this_operand].bitfield.baseIndex |
24eab124 | 9454 | && displacement_string_end[-1] == '+') |
252b5132 RH |
9455 | { |
9456 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
9457 | constraint within gcc asm statements. |
9458 | For instance: | |
9459 | ||
9460 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
9461 | __asm__ __volatile__ ( \ | |
9462 | "movw %w2,%0\n\t" \ | |
9463 | "movw %w1,2+%0\n\t" \ | |
9464 | "rorl $16,%1\n\t" \ | |
9465 | "movb %b1,4+%0\n\t" \ | |
9466 | "movb %4,5+%0\n\t" \ | |
9467 | "movb $0,6+%0\n\t" \ | |
9468 | "movb %h1,7+%0\n\t" \ | |
9469 | "rorl $16,%1" \ | |
9470 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
9471 | ||
9472 | This works great except that the output assembler ends | |
9473 | up looking a bit weird if it turns out that there is | |
9474 | no offset. You end up producing code that looks like: | |
9475 | ||
9476 | #APP | |
9477 | movw $235,(%eax) | |
9478 | movw %dx,2+(%eax) | |
9479 | rorl $16,%edx | |
9480 | movb %dl,4+(%eax) | |
9481 | movb $137,5+(%eax) | |
9482 | movb $0,6+(%eax) | |
9483 | movb %dh,7+(%eax) | |
9484 | rorl $16,%edx | |
9485 | #NO_APP | |
9486 | ||
47926f60 | 9487 | So here we provide the missing zero. */ |
24eab124 AM |
9488 | |
9489 | *displacement_string_end = '0'; | |
252b5132 RH |
9490 | } |
9491 | #endif | |
d258b828 | 9492 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
9493 | if (gotfree_input_line) |
9494 | input_line_pointer = gotfree_input_line; | |
252b5132 | 9495 | |
24eab124 | 9496 | exp_seg = expression (exp); |
252b5132 | 9497 | |
636c26b0 AM |
9498 | SKIP_WHITESPACE (); |
9499 | if (*input_line_pointer) | |
9500 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
9501 | #if GCC_ASM_O_HACK | |
9502 | RESTORE_END_STRING (disp_end + 1); | |
9503 | #endif | |
636c26b0 | 9504 | input_line_pointer = save_input_line_pointer; |
636c26b0 | 9505 | if (gotfree_input_line) |
ee86248c JB |
9506 | { |
9507 | free (gotfree_input_line); | |
9508 | ||
9509 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
9510 | exp->X_op = O_illegal; | |
9511 | } | |
9512 | ||
9513 | ret = i386_finalize_displacement (exp_seg, exp, types, disp_start); | |
9514 | ||
9515 | RESTORE_END_STRING (disp_end); | |
9516 | ||
9517 | return ret; | |
9518 | } | |
9519 | ||
9520 | static int | |
9521 | i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
9522 | i386_operand_type types, const char *disp_start) | |
9523 | { | |
9524 | i386_operand_type bigdisp; | |
9525 | int ret = 1; | |
636c26b0 | 9526 | |
24eab124 AM |
9527 | /* We do this to make sure that the section symbol is in |
9528 | the symbol table. We will ultimately change the relocation | |
47926f60 | 9529 | to be relative to the beginning of the section. */ |
1ae12ab7 | 9530 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
d6ab8113 JB |
9531 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
9532 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) | |
24eab124 | 9533 | { |
636c26b0 | 9534 | if (exp->X_op != O_symbol) |
3992d3b7 | 9535 | goto inv_disp; |
636c26b0 | 9536 | |
e5cb08ac | 9537 | if (S_IS_LOCAL (exp->X_add_symbol) |
c64efb4b L |
9538 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section |
9539 | && S_GET_SEGMENT (exp->X_add_symbol) != expr_section) | |
24eab124 | 9540 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); |
24eab124 AM |
9541 | exp->X_op = O_subtract; |
9542 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 | 9543 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
29b0f896 | 9544 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
d6ab8113 JB |
9545 | else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
9546 | i.reloc[this_operand] = BFD_RELOC_64; | |
23df1078 | 9547 | else |
29b0f896 | 9548 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 9549 | } |
252b5132 | 9550 | |
3992d3b7 AM |
9551 | else if (exp->X_op == O_absent |
9552 | || exp->X_op == O_illegal | |
ee86248c | 9553 | || exp->X_op == O_big) |
2daf4fd8 | 9554 | { |
3992d3b7 AM |
9555 | inv_disp: |
9556 | as_bad (_("missing or invalid displacement expression `%s'"), | |
2daf4fd8 | 9557 | disp_start); |
3992d3b7 | 9558 | ret = 0; |
2daf4fd8 AM |
9559 | } |
9560 | ||
0e1147d9 L |
9561 | else if (flag_code == CODE_64BIT |
9562 | && !i.prefix[ADDR_PREFIX] | |
9563 | && exp->X_op == O_constant) | |
9564 | { | |
9565 | /* Since displacement is signed extended to 64bit, don't allow | |
9566 | disp32 and turn off disp32s if they are out of range. */ | |
9567 | i.types[this_operand].bitfield.disp32 = 0; | |
9568 | if (!fits_in_signed_long (exp->X_add_number)) | |
9569 | { | |
9570 | i.types[this_operand].bitfield.disp32s = 0; | |
9571 | if (i.types[this_operand].bitfield.baseindex) | |
9572 | { | |
9573 | as_bad (_("0x%lx out range of signed 32bit displacement"), | |
9574 | (long) exp->X_add_number); | |
9575 | ret = 0; | |
9576 | } | |
9577 | } | |
9578 | } | |
9579 | ||
4c63da97 | 9580 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
3992d3b7 AM |
9581 | else if (exp->X_op != O_constant |
9582 | && OUTPUT_FLAVOR == bfd_target_aout_flavour | |
9583 | && exp_seg != absolute_section | |
9584 | && exp_seg != text_section | |
9585 | && exp_seg != data_section | |
9586 | && exp_seg != bss_section | |
9587 | && exp_seg != undefined_section | |
9588 | && !bfd_is_com_section (exp_seg)) | |
24eab124 | 9589 | { |
d0b47220 | 9590 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
3992d3b7 | 9591 | ret = 0; |
24eab124 | 9592 | } |
252b5132 | 9593 | #endif |
3956db08 | 9594 | |
40fb9820 L |
9595 | /* Check if this is a displacement only operand. */ |
9596 | bigdisp = i.types[this_operand]; | |
9597 | bigdisp.bitfield.disp8 = 0; | |
9598 | bigdisp.bitfield.disp16 = 0; | |
9599 | bigdisp.bitfield.disp32 = 0; | |
9600 | bigdisp.bitfield.disp32s = 0; | |
9601 | bigdisp.bitfield.disp64 = 0; | |
0dfbf9d7 | 9602 | if (operand_type_all_zero (&bigdisp)) |
c6fb90c8 L |
9603 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
9604 | types); | |
3956db08 | 9605 | |
3992d3b7 | 9606 | return ret; |
252b5132 RH |
9607 | } |
9608 | ||
2abc2bec JB |
9609 | /* Return the active addressing mode, taking address override and |
9610 | registers forming the address into consideration. Update the | |
9611 | address override prefix if necessary. */ | |
47926f60 | 9612 | |
2abc2bec JB |
9613 | static enum flag_code |
9614 | i386_addressing_mode (void) | |
252b5132 | 9615 | { |
be05d201 L |
9616 | enum flag_code addr_mode; |
9617 | ||
9618 | if (i.prefix[ADDR_PREFIX]) | |
9619 | addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT; | |
9620 | else | |
9621 | { | |
9622 | addr_mode = flag_code; | |
9623 | ||
24eab124 | 9624 | #if INFER_ADDR_PREFIX |
be05d201 L |
9625 | if (i.mem_operands == 0) |
9626 | { | |
9627 | /* Infer address prefix from the first memory operand. */ | |
9628 | const reg_entry *addr_reg = i.base_reg; | |
9629 | ||
9630 | if (addr_reg == NULL) | |
9631 | addr_reg = i.index_reg; | |
eecb386c | 9632 | |
be05d201 L |
9633 | if (addr_reg) |
9634 | { | |
e968fc9b | 9635 | if (addr_reg->reg_type.bitfield.dword) |
be05d201 L |
9636 | addr_mode = CODE_32BIT; |
9637 | else if (flag_code != CODE_64BIT | |
dc821c5f | 9638 | && addr_reg->reg_type.bitfield.word) |
be05d201 L |
9639 | addr_mode = CODE_16BIT; |
9640 | ||
9641 | if (addr_mode != flag_code) | |
9642 | { | |
9643 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
9644 | i.prefixes += 1; | |
9645 | /* Change the size of any displacement too. At most one | |
9646 | of Disp16 or Disp32 is set. | |
9647 | FIXME. There doesn't seem to be any real need for | |
9648 | separate Disp16 and Disp32 flags. The same goes for | |
9649 | Imm16 and Imm32. Removing them would probably clean | |
9650 | up the code quite a lot. */ | |
9651 | if (flag_code != CODE_64BIT | |
9652 | && (i.types[this_operand].bitfield.disp16 | |
9653 | || i.types[this_operand].bitfield.disp32)) | |
9654 | i.types[this_operand] | |
9655 | = operand_type_xor (i.types[this_operand], disp16_32); | |
9656 | } | |
9657 | } | |
9658 | } | |
24eab124 | 9659 | #endif |
be05d201 L |
9660 | } |
9661 | ||
2abc2bec JB |
9662 | return addr_mode; |
9663 | } | |
9664 | ||
9665 | /* Make sure the memory operand we've been dealt is valid. | |
9666 | Return 1 on success, 0 on a failure. */ | |
9667 | ||
9668 | static int | |
9669 | i386_index_check (const char *operand_string) | |
9670 | { | |
9671 | const char *kind = "base/index"; | |
9672 | enum flag_code addr_mode = i386_addressing_mode (); | |
9673 | ||
fc0763e6 JB |
9674 | if (current_templates->start->opcode_modifier.isstring |
9675 | && !current_templates->start->opcode_modifier.immext | |
9676 | && (current_templates->end[-1].opcode_modifier.isstring | |
9677 | || i.mem_operands)) | |
9678 | { | |
9679 | /* Memory operands of string insns are special in that they only allow | |
9680 | a single register (rDI, rSI, or rBX) as their memory address. */ | |
be05d201 L |
9681 | const reg_entry *expected_reg; |
9682 | static const char *di_si[][2] = | |
9683 | { | |
9684 | { "esi", "edi" }, | |
9685 | { "si", "di" }, | |
9686 | { "rsi", "rdi" } | |
9687 | }; | |
9688 | static const char *bx[] = { "ebx", "bx", "rbx" }; | |
fc0763e6 JB |
9689 | |
9690 | kind = "string address"; | |
9691 | ||
8325cc63 | 9692 | if (current_templates->start->opcode_modifier.repprefixok) |
fc0763e6 JB |
9693 | { |
9694 | i386_operand_type type = current_templates->end[-1].operand_types[0]; | |
9695 | ||
9696 | if (!type.bitfield.baseindex | |
9697 | || ((!i.mem_operands != !intel_syntax) | |
9698 | && current_templates->end[-1].operand_types[1] | |
9699 | .bitfield.baseindex)) | |
9700 | type = current_templates->end[-1].operand_types[1]; | |
be05d201 L |
9701 | expected_reg = hash_find (reg_hash, |
9702 | di_si[addr_mode][type.bitfield.esseg]); | |
9703 | ||
fc0763e6 JB |
9704 | } |
9705 | else | |
be05d201 | 9706 | expected_reg = hash_find (reg_hash, bx[addr_mode]); |
fc0763e6 | 9707 | |
be05d201 L |
9708 | if (i.base_reg != expected_reg |
9709 | || i.index_reg | |
fc0763e6 | 9710 | || operand_type_check (i.types[this_operand], disp)) |
fc0763e6 | 9711 | { |
be05d201 L |
9712 | /* The second memory operand must have the same size as |
9713 | the first one. */ | |
9714 | if (i.mem_operands | |
9715 | && i.base_reg | |
9716 | && !((addr_mode == CODE_64BIT | |
dc821c5f | 9717 | && i.base_reg->reg_type.bitfield.qword) |
be05d201 | 9718 | || (addr_mode == CODE_32BIT |
dc821c5f JB |
9719 | ? i.base_reg->reg_type.bitfield.dword |
9720 | : i.base_reg->reg_type.bitfield.word))) | |
be05d201 L |
9721 | goto bad_address; |
9722 | ||
fc0763e6 JB |
9723 | as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"), |
9724 | operand_string, | |
9725 | intel_syntax ? '[' : '(', | |
9726 | register_prefix, | |
be05d201 | 9727 | expected_reg->reg_name, |
fc0763e6 | 9728 | intel_syntax ? ']' : ')'); |
be05d201 | 9729 | return 1; |
fc0763e6 | 9730 | } |
be05d201 L |
9731 | else |
9732 | return 1; | |
9733 | ||
9734 | bad_address: | |
9735 | as_bad (_("`%s' is not a valid %s expression"), | |
9736 | operand_string, kind); | |
9737 | return 0; | |
3e73aa7c JH |
9738 | } |
9739 | else | |
9740 | { | |
be05d201 L |
9741 | if (addr_mode != CODE_16BIT) |
9742 | { | |
9743 | /* 32-bit/64-bit checks. */ | |
9744 | if ((i.base_reg | |
e968fc9b JB |
9745 | && ((addr_mode == CODE_64BIT |
9746 | ? !i.base_reg->reg_type.bitfield.qword | |
9747 | : !i.base_reg->reg_type.bitfield.dword) | |
9748 | || (i.index_reg && i.base_reg->reg_num == RegIP) | |
9749 | || i.base_reg->reg_num == RegIZ)) | |
be05d201 | 9750 | || (i.index_reg |
1b54b8d7 JB |
9751 | && !i.index_reg->reg_type.bitfield.xmmword |
9752 | && !i.index_reg->reg_type.bitfield.ymmword | |
9753 | && !i.index_reg->reg_type.bitfield.zmmword | |
be05d201 | 9754 | && ((addr_mode == CODE_64BIT |
e968fc9b JB |
9755 | ? !i.index_reg->reg_type.bitfield.qword |
9756 | : !i.index_reg->reg_type.bitfield.dword) | |
be05d201 L |
9757 | || !i.index_reg->reg_type.bitfield.baseindex))) |
9758 | goto bad_address; | |
8178be5b JB |
9759 | |
9760 | /* bndmk, bndldx, and bndstx have special restrictions. */ | |
9761 | if (current_templates->start->base_opcode == 0xf30f1b | |
9762 | || (current_templates->start->base_opcode & ~1) == 0x0f1a) | |
9763 | { | |
9764 | /* They cannot use RIP-relative addressing. */ | |
e968fc9b | 9765 | if (i.base_reg && i.base_reg->reg_num == RegIP) |
8178be5b JB |
9766 | { |
9767 | as_bad (_("`%s' cannot be used here"), operand_string); | |
9768 | return 0; | |
9769 | } | |
9770 | ||
9771 | /* bndldx and bndstx ignore their scale factor. */ | |
9772 | if (current_templates->start->base_opcode != 0xf30f1b | |
9773 | && i.log2_scale_factor) | |
9774 | as_warn (_("register scaling is being ignored here")); | |
9775 | } | |
be05d201 L |
9776 | } |
9777 | else | |
3e73aa7c | 9778 | { |
be05d201 | 9779 | /* 16-bit checks. */ |
3e73aa7c | 9780 | if ((i.base_reg |
dc821c5f | 9781 | && (!i.base_reg->reg_type.bitfield.word |
40fb9820 | 9782 | || !i.base_reg->reg_type.bitfield.baseindex)) |
3e73aa7c | 9783 | || (i.index_reg |
dc821c5f | 9784 | && (!i.index_reg->reg_type.bitfield.word |
40fb9820 | 9785 | || !i.index_reg->reg_type.bitfield.baseindex |
29b0f896 AM |
9786 | || !(i.base_reg |
9787 | && i.base_reg->reg_num < 6 | |
9788 | && i.index_reg->reg_num >= 6 | |
9789 | && i.log2_scale_factor == 0)))) | |
be05d201 | 9790 | goto bad_address; |
3e73aa7c JH |
9791 | } |
9792 | } | |
be05d201 | 9793 | return 1; |
24eab124 | 9794 | } |
252b5132 | 9795 | |
43234a1e L |
9796 | /* Handle vector immediates. */ |
9797 | ||
9798 | static int | |
9799 | RC_SAE_immediate (const char *imm_start) | |
9800 | { | |
9801 | unsigned int match_found, j; | |
9802 | const char *pstr = imm_start; | |
9803 | expressionS *exp; | |
9804 | ||
9805 | if (*pstr != '{') | |
9806 | return 0; | |
9807 | ||
9808 | pstr++; | |
9809 | match_found = 0; | |
9810 | for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++) | |
9811 | { | |
9812 | if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len)) | |
9813 | { | |
9814 | if (!i.rounding) | |
9815 | { | |
9816 | rc_op.type = RC_NamesTable[j].type; | |
9817 | rc_op.operand = this_operand; | |
9818 | i.rounding = &rc_op; | |
9819 | } | |
9820 | else | |
9821 | { | |
9822 | as_bad (_("duplicated `%s'"), imm_start); | |
9823 | return 0; | |
9824 | } | |
9825 | pstr += RC_NamesTable[j].len; | |
9826 | match_found = 1; | |
9827 | break; | |
9828 | } | |
9829 | } | |
9830 | if (!match_found) | |
9831 | return 0; | |
9832 | ||
9833 | if (*pstr++ != '}') | |
9834 | { | |
9835 | as_bad (_("Missing '}': '%s'"), imm_start); | |
9836 | return 0; | |
9837 | } | |
9838 | /* RC/SAE immediate string should contain nothing more. */; | |
9839 | if (*pstr != 0) | |
9840 | { | |
9841 | as_bad (_("Junk after '}': '%s'"), imm_start); | |
9842 | return 0; | |
9843 | } | |
9844 | ||
9845 | exp = &im_expressions[i.imm_operands++]; | |
9846 | i.op[this_operand].imms = exp; | |
9847 | ||
9848 | exp->X_op = O_constant; | |
9849 | exp->X_add_number = 0; | |
9850 | exp->X_add_symbol = (symbolS *) 0; | |
9851 | exp->X_op_symbol = (symbolS *) 0; | |
9852 | ||
9853 | i.types[this_operand].bitfield.imm8 = 1; | |
9854 | return 1; | |
9855 | } | |
9856 | ||
8325cc63 JB |
9857 | /* Only string instructions can have a second memory operand, so |
9858 | reduce current_templates to just those if it contains any. */ | |
9859 | static int | |
9860 | maybe_adjust_templates (void) | |
9861 | { | |
9862 | const insn_template *t; | |
9863 | ||
9864 | gas_assert (i.mem_operands == 1); | |
9865 | ||
9866 | for (t = current_templates->start; t < current_templates->end; ++t) | |
9867 | if (t->opcode_modifier.isstring) | |
9868 | break; | |
9869 | ||
9870 | if (t < current_templates->end) | |
9871 | { | |
9872 | static templates aux_templates; | |
9873 | bfd_boolean recheck; | |
9874 | ||
9875 | aux_templates.start = t; | |
9876 | for (; t < current_templates->end; ++t) | |
9877 | if (!t->opcode_modifier.isstring) | |
9878 | break; | |
9879 | aux_templates.end = t; | |
9880 | ||
9881 | /* Determine whether to re-check the first memory operand. */ | |
9882 | recheck = (aux_templates.start != current_templates->start | |
9883 | || t != current_templates->end); | |
9884 | ||
9885 | current_templates = &aux_templates; | |
9886 | ||
9887 | if (recheck) | |
9888 | { | |
9889 | i.mem_operands = 0; | |
9890 | if (i.memop1_string != NULL | |
9891 | && i386_index_check (i.memop1_string) == 0) | |
9892 | return 0; | |
9893 | i.mem_operands = 1; | |
9894 | } | |
9895 | } | |
9896 | ||
9897 | return 1; | |
9898 | } | |
9899 | ||
fc0763e6 | 9900 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero |
47926f60 | 9901 | on error. */ |
252b5132 | 9902 | |
252b5132 | 9903 | static int |
a7619375 | 9904 | i386_att_operand (char *operand_string) |
252b5132 | 9905 | { |
af6bdddf AM |
9906 | const reg_entry *r; |
9907 | char *end_op; | |
24eab124 | 9908 | char *op_string = operand_string; |
252b5132 | 9909 | |
24eab124 | 9910 | if (is_space_char (*op_string)) |
252b5132 RH |
9911 | ++op_string; |
9912 | ||
24eab124 | 9913 | /* We check for an absolute prefix (differentiating, |
47926f60 | 9914 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
9915 | if (*op_string == ABSOLUTE_PREFIX) |
9916 | { | |
9917 | ++op_string; | |
9918 | if (is_space_char (*op_string)) | |
9919 | ++op_string; | |
40fb9820 | 9920 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 | 9921 | } |
252b5132 | 9922 | |
47926f60 | 9923 | /* Check if operand is a register. */ |
4d1bb795 | 9924 | if ((r = parse_register (op_string, &end_op)) != NULL) |
24eab124 | 9925 | { |
40fb9820 L |
9926 | i386_operand_type temp; |
9927 | ||
24eab124 AM |
9928 | /* Check for a segment override by searching for ':' after a |
9929 | segment register. */ | |
9930 | op_string = end_op; | |
9931 | if (is_space_char (*op_string)) | |
9932 | ++op_string; | |
40fb9820 L |
9933 | if (*op_string == ':' |
9934 | && (r->reg_type.bitfield.sreg2 | |
9935 | || r->reg_type.bitfield.sreg3)) | |
24eab124 AM |
9936 | { |
9937 | switch (r->reg_num) | |
9938 | { | |
9939 | case 0: | |
9940 | i.seg[i.mem_operands] = &es; | |
9941 | break; | |
9942 | case 1: | |
9943 | i.seg[i.mem_operands] = &cs; | |
9944 | break; | |
9945 | case 2: | |
9946 | i.seg[i.mem_operands] = &ss; | |
9947 | break; | |
9948 | case 3: | |
9949 | i.seg[i.mem_operands] = &ds; | |
9950 | break; | |
9951 | case 4: | |
9952 | i.seg[i.mem_operands] = &fs; | |
9953 | break; | |
9954 | case 5: | |
9955 | i.seg[i.mem_operands] = &gs; | |
9956 | break; | |
9957 | } | |
252b5132 | 9958 | |
24eab124 | 9959 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
9960 | ++op_string; |
9961 | if (is_space_char (*op_string)) | |
24eab124 | 9962 | ++op_string; |
252b5132 | 9963 | |
24eab124 AM |
9964 | if (!is_digit_char (*op_string) |
9965 | && !is_identifier_char (*op_string) | |
9966 | && *op_string != '(' | |
9967 | && *op_string != ABSOLUTE_PREFIX) | |
9968 | { | |
9969 | as_bad (_("bad memory operand `%s'"), op_string); | |
9970 | return 0; | |
9971 | } | |
47926f60 | 9972 | /* Handle case of %es:*foo. */ |
24eab124 AM |
9973 | if (*op_string == ABSOLUTE_PREFIX) |
9974 | { | |
9975 | ++op_string; | |
9976 | if (is_space_char (*op_string)) | |
9977 | ++op_string; | |
40fb9820 | 9978 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 AM |
9979 | } |
9980 | goto do_memory_reference; | |
9981 | } | |
43234a1e L |
9982 | |
9983 | /* Handle vector operations. */ | |
9984 | if (*op_string == '{') | |
9985 | { | |
9986 | op_string = check_VecOperations (op_string, NULL); | |
9987 | if (op_string == NULL) | |
9988 | return 0; | |
9989 | } | |
9990 | ||
24eab124 AM |
9991 | if (*op_string) |
9992 | { | |
d0b47220 | 9993 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
9994 | return 0; |
9995 | } | |
40fb9820 L |
9996 | temp = r->reg_type; |
9997 | temp.bitfield.baseindex = 0; | |
c6fb90c8 L |
9998 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
9999 | temp); | |
7d5e4556 | 10000 | i.types[this_operand].bitfield.unspecified = 0; |
520dc8e8 | 10001 | i.op[this_operand].regs = r; |
24eab124 AM |
10002 | i.reg_operands++; |
10003 | } | |
af6bdddf AM |
10004 | else if (*op_string == REGISTER_PREFIX) |
10005 | { | |
10006 | as_bad (_("bad register name `%s'"), op_string); | |
10007 | return 0; | |
10008 | } | |
24eab124 | 10009 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 10010 | { |
24eab124 | 10011 | ++op_string; |
40fb9820 | 10012 | if (i.types[this_operand].bitfield.jumpabsolute) |
24eab124 | 10013 | { |
d0b47220 | 10014 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
10015 | return 0; |
10016 | } | |
10017 | if (!i386_immediate (op_string)) | |
10018 | return 0; | |
10019 | } | |
43234a1e L |
10020 | else if (RC_SAE_immediate (operand_string)) |
10021 | { | |
10022 | /* If it is a RC or SAE immediate, do nothing. */ | |
10023 | ; | |
10024 | } | |
24eab124 AM |
10025 | else if (is_digit_char (*op_string) |
10026 | || is_identifier_char (*op_string) | |
d02603dc | 10027 | || *op_string == '"' |
e5cb08ac | 10028 | || *op_string == '(') |
24eab124 | 10029 | { |
47926f60 | 10030 | /* This is a memory reference of some sort. */ |
af6bdddf | 10031 | char *base_string; |
252b5132 | 10032 | |
47926f60 | 10033 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
10034 | char *displacement_string_start; |
10035 | char *displacement_string_end; | |
43234a1e | 10036 | char *vop_start; |
252b5132 | 10037 | |
24eab124 | 10038 | do_memory_reference: |
8325cc63 JB |
10039 | if (i.mem_operands == 1 && !maybe_adjust_templates ()) |
10040 | return 0; | |
24eab124 | 10041 | if ((i.mem_operands == 1 |
40fb9820 | 10042 | && !current_templates->start->opcode_modifier.isstring) |
24eab124 AM |
10043 | || i.mem_operands == 2) |
10044 | { | |
10045 | as_bad (_("too many memory references for `%s'"), | |
10046 | current_templates->start->name); | |
10047 | return 0; | |
10048 | } | |
252b5132 | 10049 | |
24eab124 AM |
10050 | /* Check for base index form. We detect the base index form by |
10051 | looking for an ')' at the end of the operand, searching | |
10052 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
10053 | after the '('. */ | |
af6bdddf | 10054 | base_string = op_string + strlen (op_string); |
c3332e24 | 10055 | |
43234a1e L |
10056 | /* Handle vector operations. */ |
10057 | vop_start = strchr (op_string, '{'); | |
10058 | if (vop_start && vop_start < base_string) | |
10059 | { | |
10060 | if (check_VecOperations (vop_start, base_string) == NULL) | |
10061 | return 0; | |
10062 | base_string = vop_start; | |
10063 | } | |
10064 | ||
af6bdddf AM |
10065 | --base_string; |
10066 | if (is_space_char (*base_string)) | |
10067 | --base_string; | |
252b5132 | 10068 | |
47926f60 | 10069 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
10070 | displacement_string_start = op_string; |
10071 | displacement_string_end = base_string + 1; | |
252b5132 | 10072 | |
24eab124 AM |
10073 | if (*base_string == ')') |
10074 | { | |
af6bdddf | 10075 | char *temp_string; |
24eab124 AM |
10076 | unsigned int parens_balanced = 1; |
10077 | /* We've already checked that the number of left & right ()'s are | |
47926f60 | 10078 | equal, so this loop will not be infinite. */ |
24eab124 AM |
10079 | do |
10080 | { | |
10081 | base_string--; | |
10082 | if (*base_string == ')') | |
10083 | parens_balanced++; | |
10084 | if (*base_string == '(') | |
10085 | parens_balanced--; | |
10086 | } | |
10087 | while (parens_balanced); | |
c3332e24 | 10088 | |
af6bdddf | 10089 | temp_string = base_string; |
c3332e24 | 10090 | |
24eab124 | 10091 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
10092 | ++base_string; |
10093 | if (is_space_char (*base_string)) | |
24eab124 | 10094 | ++base_string; |
252b5132 | 10095 | |
af6bdddf | 10096 | if (*base_string == ',' |
4eed87de AM |
10097 | || ((i.base_reg = parse_register (base_string, &end_op)) |
10098 | != NULL)) | |
252b5132 | 10099 | { |
af6bdddf | 10100 | displacement_string_end = temp_string; |
252b5132 | 10101 | |
40fb9820 | 10102 | i.types[this_operand].bitfield.baseindex = 1; |
252b5132 | 10103 | |
af6bdddf | 10104 | if (i.base_reg) |
24eab124 | 10105 | { |
24eab124 AM |
10106 | base_string = end_op; |
10107 | if (is_space_char (*base_string)) | |
10108 | ++base_string; | |
af6bdddf AM |
10109 | } |
10110 | ||
10111 | /* There may be an index reg or scale factor here. */ | |
10112 | if (*base_string == ',') | |
10113 | { | |
10114 | ++base_string; | |
10115 | if (is_space_char (*base_string)) | |
10116 | ++base_string; | |
10117 | ||
4eed87de AM |
10118 | if ((i.index_reg = parse_register (base_string, &end_op)) |
10119 | != NULL) | |
24eab124 | 10120 | { |
af6bdddf | 10121 | base_string = end_op; |
24eab124 AM |
10122 | if (is_space_char (*base_string)) |
10123 | ++base_string; | |
af6bdddf AM |
10124 | if (*base_string == ',') |
10125 | { | |
10126 | ++base_string; | |
10127 | if (is_space_char (*base_string)) | |
10128 | ++base_string; | |
10129 | } | |
e5cb08ac | 10130 | else if (*base_string != ')') |
af6bdddf | 10131 | { |
4eed87de AM |
10132 | as_bad (_("expecting `,' or `)' " |
10133 | "after index register in `%s'"), | |
af6bdddf AM |
10134 | operand_string); |
10135 | return 0; | |
10136 | } | |
24eab124 | 10137 | } |
af6bdddf | 10138 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 10139 | { |
f76bf5e0 L |
10140 | end_op = strchr (base_string, ','); |
10141 | if (end_op) | |
10142 | *end_op = '\0'; | |
af6bdddf | 10143 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
10144 | return 0; |
10145 | } | |
252b5132 | 10146 | |
47926f60 | 10147 | /* Check for scale factor. */ |
551c1ca1 | 10148 | if (*base_string != ')') |
af6bdddf | 10149 | { |
551c1ca1 AM |
10150 | char *end_scale = i386_scale (base_string); |
10151 | ||
10152 | if (!end_scale) | |
af6bdddf | 10153 | return 0; |
24eab124 | 10154 | |
551c1ca1 | 10155 | base_string = end_scale; |
af6bdddf AM |
10156 | if (is_space_char (*base_string)) |
10157 | ++base_string; | |
10158 | if (*base_string != ')') | |
10159 | { | |
4eed87de AM |
10160 | as_bad (_("expecting `)' " |
10161 | "after scale factor in `%s'"), | |
af6bdddf AM |
10162 | operand_string); |
10163 | return 0; | |
10164 | } | |
10165 | } | |
10166 | else if (!i.index_reg) | |
24eab124 | 10167 | { |
4eed87de AM |
10168 | as_bad (_("expecting index register or scale factor " |
10169 | "after `,'; got '%c'"), | |
af6bdddf | 10170 | *base_string); |
24eab124 AM |
10171 | return 0; |
10172 | } | |
10173 | } | |
af6bdddf | 10174 | else if (*base_string != ')') |
24eab124 | 10175 | { |
4eed87de AM |
10176 | as_bad (_("expecting `,' or `)' " |
10177 | "after base register in `%s'"), | |
af6bdddf | 10178 | operand_string); |
24eab124 AM |
10179 | return 0; |
10180 | } | |
c3332e24 | 10181 | } |
af6bdddf | 10182 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 10183 | { |
f76bf5e0 L |
10184 | end_op = strchr (base_string, ','); |
10185 | if (end_op) | |
10186 | *end_op = '\0'; | |
af6bdddf | 10187 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 10188 | return 0; |
c3332e24 | 10189 | } |
24eab124 AM |
10190 | } |
10191 | ||
10192 | /* If there's an expression beginning the operand, parse it, | |
10193 | assuming displacement_string_start and | |
10194 | displacement_string_end are meaningful. */ | |
10195 | if (displacement_string_start != displacement_string_end) | |
10196 | { | |
10197 | if (!i386_displacement (displacement_string_start, | |
10198 | displacement_string_end)) | |
10199 | return 0; | |
10200 | } | |
10201 | ||
10202 | /* Special case for (%dx) while doing input/output op. */ | |
10203 | if (i.base_reg | |
2fb5be8d | 10204 | && i.base_reg->reg_type.bitfield.inoutportreg |
24eab124 AM |
10205 | && i.index_reg == 0 |
10206 | && i.log2_scale_factor == 0 | |
10207 | && i.seg[i.mem_operands] == 0 | |
40fb9820 | 10208 | && !operand_type_check (i.types[this_operand], disp)) |
24eab124 | 10209 | { |
2fb5be8d | 10210 | i.types[this_operand] = i.base_reg->reg_type; |
24eab124 AM |
10211 | return 1; |
10212 | } | |
10213 | ||
eecb386c AM |
10214 | if (i386_index_check (operand_string) == 0) |
10215 | return 0; | |
c48dadc9 | 10216 | i.flags[this_operand] |= Operand_Mem; |
8325cc63 JB |
10217 | if (i.mem_operands == 0) |
10218 | i.memop1_string = xstrdup (operand_string); | |
24eab124 AM |
10219 | i.mem_operands++; |
10220 | } | |
10221 | else | |
ce8a8b2f AM |
10222 | { |
10223 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
10224 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
10225 | output_invalid (*op_string), | |
10226 | this_operand + 1, | |
10227 | op_string); | |
10228 | return 0; | |
10229 | } | |
47926f60 | 10230 | return 1; /* Normal return. */ |
252b5132 RH |
10231 | } |
10232 | \f | |
fa94de6b RM |
10233 | /* Calculate the maximum variable size (i.e., excluding fr_fix) |
10234 | that an rs_machine_dependent frag may reach. */ | |
10235 | ||
10236 | unsigned int | |
10237 | i386_frag_max_var (fragS *frag) | |
10238 | { | |
10239 | /* The only relaxable frags are for jumps. | |
10240 | Unconditional jumps can grow by 4 bytes and others by 5 bytes. */ | |
10241 | gas_assert (frag->fr_type == rs_machine_dependent); | |
10242 | return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5; | |
10243 | } | |
10244 | ||
b084df0b L |
10245 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
10246 | static int | |
8dcea932 | 10247 | elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var) |
b084df0b L |
10248 | { |
10249 | /* STT_GNU_IFUNC symbol must go through PLT. */ | |
10250 | if ((symbol_get_bfdsym (fr_symbol)->flags | |
10251 | & BSF_GNU_INDIRECT_FUNCTION) != 0) | |
10252 | return 0; | |
10253 | ||
10254 | if (!S_IS_EXTERNAL (fr_symbol)) | |
10255 | /* Symbol may be weak or local. */ | |
10256 | return !S_IS_WEAK (fr_symbol); | |
10257 | ||
8dcea932 L |
10258 | /* Global symbols with non-default visibility can't be preempted. */ |
10259 | if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT) | |
10260 | return 1; | |
10261 | ||
10262 | if (fr_var != NO_RELOC) | |
10263 | switch ((enum bfd_reloc_code_real) fr_var) | |
10264 | { | |
10265 | case BFD_RELOC_386_PLT32: | |
10266 | case BFD_RELOC_X86_64_PLT32: | |
33eaf5de | 10267 | /* Symbol with PLT relocation may be preempted. */ |
8dcea932 L |
10268 | return 0; |
10269 | default: | |
10270 | abort (); | |
10271 | } | |
10272 | ||
b084df0b L |
10273 | /* Global symbols with default visibility in a shared library may be |
10274 | preempted by another definition. */ | |
8dcea932 | 10275 | return !shared; |
b084df0b L |
10276 | } |
10277 | #endif | |
10278 | ||
ee7fcc42 AM |
10279 | /* md_estimate_size_before_relax() |
10280 | ||
10281 | Called just before relax() for rs_machine_dependent frags. The x86 | |
10282 | assembler uses these frags to handle variable size jump | |
10283 | instructions. | |
10284 | ||
10285 | Any symbol that is now undefined will not become defined. | |
10286 | Return the correct fr_subtype in the frag. | |
10287 | Return the initial "guess for variable size of frag" to caller. | |
10288 | The guess is actually the growth beyond the fixed part. Whatever | |
10289 | we do to grow the fixed or variable part contributes to our | |
10290 | returned value. */ | |
10291 | ||
252b5132 | 10292 | int |
7016a5d5 | 10293 | md_estimate_size_before_relax (fragS *fragP, segT segment) |
252b5132 | 10294 | { |
252b5132 | 10295 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
10296 | check for un-relaxable symbols. On an ELF system, we can't relax |
10297 | an externally visible symbol, because it may be overridden by a | |
10298 | shared library. */ | |
10299 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 10300 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 10301 | || (IS_ELF |
8dcea932 L |
10302 | && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol, |
10303 | fragP->fr_var)) | |
fbeb56a4 DK |
10304 | #endif |
10305 | #if defined (OBJ_COFF) && defined (TE_PE) | |
7ab9ffdd | 10306 | || (OUTPUT_FLAVOR == bfd_target_coff_flavour |
fbeb56a4 | 10307 | && S_IS_WEAK (fragP->fr_symbol)) |
b98ef147 AM |
10308 | #endif |
10309 | ) | |
252b5132 | 10310 | { |
b98ef147 AM |
10311 | /* Symbol is undefined in this segment, or we need to keep a |
10312 | reloc so that weak symbols can be overridden. */ | |
10313 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f86103b7 | 10314 | enum bfd_reloc_code_real reloc_type; |
ee7fcc42 AM |
10315 | unsigned char *opcode; |
10316 | int old_fr_fix; | |
f6af82bd | 10317 | |
ee7fcc42 | 10318 | if (fragP->fr_var != NO_RELOC) |
1e9cc1c2 | 10319 | reloc_type = (enum bfd_reloc_code_real) fragP->fr_var; |
b98ef147 | 10320 | else if (size == 2) |
f6af82bd | 10321 | reloc_type = BFD_RELOC_16_PCREL; |
bd7ab16b L |
10322 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
10323 | else if (need_plt32_p (fragP->fr_symbol)) | |
10324 | reloc_type = BFD_RELOC_X86_64_PLT32; | |
10325 | #endif | |
f6af82bd AM |
10326 | else |
10327 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 10328 | |
ee7fcc42 AM |
10329 | old_fr_fix = fragP->fr_fix; |
10330 | opcode = (unsigned char *) fragP->fr_opcode; | |
10331 | ||
fddf5b5b | 10332 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 10333 | { |
fddf5b5b AM |
10334 | case UNCOND_JUMP: |
10335 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 10336 | opcode[0] = 0xe9; |
252b5132 | 10337 | fragP->fr_fix += size; |
062cd5e7 AS |
10338 | fix_new (fragP, old_fr_fix, size, |
10339 | fragP->fr_symbol, | |
10340 | fragP->fr_offset, 1, | |
10341 | reloc_type); | |
252b5132 RH |
10342 | break; |
10343 | ||
fddf5b5b | 10344 | case COND_JUMP86: |
412167cb AM |
10345 | if (size == 2 |
10346 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) | |
fddf5b5b AM |
10347 | { |
10348 | /* Negate the condition, and branch past an | |
10349 | unconditional jump. */ | |
10350 | opcode[0] ^= 1; | |
10351 | opcode[1] = 3; | |
10352 | /* Insert an unconditional jump. */ | |
10353 | opcode[2] = 0xe9; | |
10354 | /* We added two extra opcode bytes, and have a two byte | |
10355 | offset. */ | |
10356 | fragP->fr_fix += 2 + 2; | |
062cd5e7 AS |
10357 | fix_new (fragP, old_fr_fix + 2, 2, |
10358 | fragP->fr_symbol, | |
10359 | fragP->fr_offset, 1, | |
10360 | reloc_type); | |
fddf5b5b AM |
10361 | break; |
10362 | } | |
10363 | /* Fall through. */ | |
10364 | ||
10365 | case COND_JUMP: | |
412167cb AM |
10366 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
10367 | { | |
3e02c1cc AM |
10368 | fixS *fixP; |
10369 | ||
412167cb | 10370 | fragP->fr_fix += 1; |
3e02c1cc AM |
10371 | fixP = fix_new (fragP, old_fr_fix, 1, |
10372 | fragP->fr_symbol, | |
10373 | fragP->fr_offset, 1, | |
10374 | BFD_RELOC_8_PCREL); | |
10375 | fixP->fx_signed = 1; | |
412167cb AM |
10376 | break; |
10377 | } | |
93c2a809 | 10378 | |
24eab124 | 10379 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 10380 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 10381 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 10382 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
10383 | /* We've added an opcode byte. */ |
10384 | fragP->fr_fix += 1 + size; | |
062cd5e7 AS |
10385 | fix_new (fragP, old_fr_fix + 1, size, |
10386 | fragP->fr_symbol, | |
10387 | fragP->fr_offset, 1, | |
10388 | reloc_type); | |
252b5132 | 10389 | break; |
fddf5b5b AM |
10390 | |
10391 | default: | |
10392 | BAD_CASE (fragP->fr_subtype); | |
10393 | break; | |
252b5132 RH |
10394 | } |
10395 | frag_wane (fragP); | |
ee7fcc42 | 10396 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 10397 | } |
93c2a809 | 10398 | |
93c2a809 AM |
10399 | /* Guess size depending on current relax state. Initially the relax |
10400 | state will correspond to a short jump and we return 1, because | |
10401 | the variable part of the frag (the branch offset) is one byte | |
10402 | long. However, we can relax a section more than once and in that | |
10403 | case we must either set fr_subtype back to the unrelaxed state, | |
10404 | or return the value for the appropriate branch. */ | |
10405 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
10406 | } |
10407 | ||
47926f60 KH |
10408 | /* Called after relax() is finished. |
10409 | ||
10410 | In: Address of frag. | |
10411 | fr_type == rs_machine_dependent. | |
10412 | fr_subtype is what the address relaxed to. | |
10413 | ||
10414 | Out: Any fixSs and constants are set up. | |
10415 | Caller will turn frag into a ".space 0". */ | |
10416 | ||
252b5132 | 10417 | void |
7016a5d5 TG |
10418 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, |
10419 | fragS *fragP) | |
252b5132 | 10420 | { |
29b0f896 | 10421 | unsigned char *opcode; |
252b5132 | 10422 | unsigned char *where_to_put_displacement = NULL; |
847f7ad4 AM |
10423 | offsetT target_address; |
10424 | offsetT opcode_address; | |
252b5132 | 10425 | unsigned int extension = 0; |
847f7ad4 | 10426 | offsetT displacement_from_opcode_start; |
252b5132 RH |
10427 | |
10428 | opcode = (unsigned char *) fragP->fr_opcode; | |
10429 | ||
47926f60 | 10430 | /* Address we want to reach in file space. */ |
252b5132 | 10431 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 10432 | |
47926f60 | 10433 | /* Address opcode resides at in file space. */ |
252b5132 RH |
10434 | opcode_address = fragP->fr_address + fragP->fr_fix; |
10435 | ||
47926f60 | 10436 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
10437 | displacement_from_opcode_start = target_address - opcode_address; |
10438 | ||
fddf5b5b | 10439 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 10440 | { |
47926f60 KH |
10441 | /* Don't have to change opcode. */ |
10442 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 10443 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
10444 | } |
10445 | else | |
10446 | { | |
10447 | if (no_cond_jump_promotion | |
10448 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4eed87de AM |
10449 | as_warn_where (fragP->fr_file, fragP->fr_line, |
10450 | _("long jump required")); | |
252b5132 | 10451 | |
fddf5b5b AM |
10452 | switch (fragP->fr_subtype) |
10453 | { | |
10454 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
10455 | extension = 4; /* 1 opcode + 4 displacement */ | |
10456 | opcode[0] = 0xe9; | |
10457 | where_to_put_displacement = &opcode[1]; | |
10458 | break; | |
252b5132 | 10459 | |
fddf5b5b AM |
10460 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
10461 | extension = 2; /* 1 opcode + 2 displacement */ | |
10462 | opcode[0] = 0xe9; | |
10463 | where_to_put_displacement = &opcode[1]; | |
10464 | break; | |
252b5132 | 10465 | |
fddf5b5b AM |
10466 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
10467 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
10468 | extension = 5; /* 2 opcode + 4 displacement */ | |
10469 | opcode[1] = opcode[0] + 0x10; | |
10470 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
10471 | where_to_put_displacement = &opcode[2]; | |
10472 | break; | |
252b5132 | 10473 | |
fddf5b5b AM |
10474 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
10475 | extension = 3; /* 2 opcode + 2 displacement */ | |
10476 | opcode[1] = opcode[0] + 0x10; | |
10477 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
10478 | where_to_put_displacement = &opcode[2]; | |
10479 | break; | |
252b5132 | 10480 | |
fddf5b5b AM |
10481 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
10482 | extension = 4; | |
10483 | opcode[0] ^= 1; | |
10484 | opcode[1] = 3; | |
10485 | opcode[2] = 0xe9; | |
10486 | where_to_put_displacement = &opcode[3]; | |
10487 | break; | |
10488 | ||
10489 | default: | |
10490 | BAD_CASE (fragP->fr_subtype); | |
10491 | break; | |
10492 | } | |
252b5132 | 10493 | } |
fddf5b5b | 10494 | |
7b81dfbb AJ |
10495 | /* If size if less then four we are sure that the operand fits, |
10496 | but if it's 4, then it could be that the displacement is larger | |
10497 | then -/+ 2GB. */ | |
10498 | if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 | |
10499 | && object_64bit | |
10500 | && ((addressT) (displacement_from_opcode_start - extension | |
4eed87de AM |
10501 | + ((addressT) 1 << 31)) |
10502 | > (((addressT) 2 << 31) - 1))) | |
7b81dfbb AJ |
10503 | { |
10504 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
10505 | _("jump target out of range")); | |
10506 | /* Make us emit 0. */ | |
10507 | displacement_from_opcode_start = extension; | |
10508 | } | |
47926f60 | 10509 | /* Now put displacement after opcode. */ |
252b5132 RH |
10510 | md_number_to_chars ((char *) where_to_put_displacement, |
10511 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 10512 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
10513 | fragP->fr_fix += extension; |
10514 | } | |
10515 | \f | |
7016a5d5 | 10516 | /* Apply a fixup (fixP) to segment data, once it has been determined |
252b5132 RH |
10517 | by our caller that we have all the info we need to fix it up. |
10518 | ||
7016a5d5 TG |
10519 | Parameter valP is the pointer to the value of the bits. |
10520 | ||
252b5132 RH |
10521 | On the 386, immediates, displacements, and data pointers are all in |
10522 | the same (little-endian) format, so we don't need to care about which | |
10523 | we are handling. */ | |
10524 | ||
94f592af | 10525 | void |
7016a5d5 | 10526 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 10527 | { |
94f592af | 10528 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
c6682705 | 10529 | valueT value = *valP; |
252b5132 | 10530 | |
f86103b7 | 10531 | #if !defined (TE_Mach) |
93382f6d AM |
10532 | if (fixP->fx_pcrel) |
10533 | { | |
10534 | switch (fixP->fx_r_type) | |
10535 | { | |
5865bb77 ILT |
10536 | default: |
10537 | break; | |
10538 | ||
d6ab8113 JB |
10539 | case BFD_RELOC_64: |
10540 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
10541 | break; | |
93382f6d | 10542 | case BFD_RELOC_32: |
ae8887b5 | 10543 | case BFD_RELOC_X86_64_32S: |
93382f6d AM |
10544 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
10545 | break; | |
10546 | case BFD_RELOC_16: | |
10547 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
10548 | break; | |
10549 | case BFD_RELOC_8: | |
10550 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
10551 | break; | |
10552 | } | |
10553 | } | |
252b5132 | 10554 | |
a161fe53 | 10555 | if (fixP->fx_addsy != NULL |
31312f95 | 10556 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
d6ab8113 | 10557 | || fixP->fx_r_type == BFD_RELOC_64_PCREL |
31312f95 | 10558 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
d258b828 | 10559 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) |
31312f95 | 10560 | && !use_rela_relocations) |
252b5132 | 10561 | { |
31312f95 AM |
10562 | /* This is a hack. There should be a better way to handle this. |
10563 | This covers for the fact that bfd_install_relocation will | |
10564 | subtract the current location (for partial_inplace, PC relative | |
10565 | relocations); see more below. */ | |
252b5132 | 10566 | #ifndef OBJ_AOUT |
718ddfc0 | 10567 | if (IS_ELF |
252b5132 RH |
10568 | #ifdef TE_PE |
10569 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
10570 | #endif | |
10571 | ) | |
10572 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
10573 | #endif | |
10574 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 10575 | if (IS_ELF) |
252b5132 | 10576 | { |
6539b54b | 10577 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
2f66722d | 10578 | |
6539b54b | 10579 | if ((sym_seg == seg |
2f66722d | 10580 | || (symbol_section_p (fixP->fx_addsy) |
6539b54b | 10581 | && sym_seg != absolute_section)) |
af65af87 | 10582 | && !generic_force_reloc (fixP)) |
2f66722d AM |
10583 | { |
10584 | /* Yes, we add the values in twice. This is because | |
6539b54b AM |
10585 | bfd_install_relocation subtracts them out again. I think |
10586 | bfd_install_relocation is broken, but I don't dare change | |
2f66722d AM |
10587 | it. FIXME. */ |
10588 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
10589 | } | |
252b5132 RH |
10590 | } |
10591 | #endif | |
10592 | #if defined (OBJ_COFF) && defined (TE_PE) | |
977cdf5a NC |
10593 | /* For some reason, the PE format does not store a |
10594 | section address offset for a PC relative symbol. */ | |
10595 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg | |
7be1c489 | 10596 | || S_IS_WEAK (fixP->fx_addsy)) |
252b5132 RH |
10597 | value += md_pcrel_from (fixP); |
10598 | #endif | |
10599 | } | |
fbeb56a4 | 10600 | #if defined (OBJ_COFF) && defined (TE_PE) |
f01c1a09 NC |
10601 | if (fixP->fx_addsy != NULL |
10602 | && S_IS_WEAK (fixP->fx_addsy) | |
10603 | /* PR 16858: Do not modify weak function references. */ | |
10604 | && ! fixP->fx_pcrel) | |
fbeb56a4 | 10605 | { |
296a8689 NC |
10606 | #if !defined (TE_PEP) |
10607 | /* For x86 PE weak function symbols are neither PC-relative | |
10608 | nor do they set S_IS_FUNCTION. So the only reliable way | |
10609 | to detect them is to check the flags of their containing | |
10610 | section. */ | |
10611 | if (S_GET_SEGMENT (fixP->fx_addsy) != NULL | |
10612 | && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE) | |
10613 | ; | |
10614 | else | |
10615 | #endif | |
fbeb56a4 DK |
10616 | value -= S_GET_VALUE (fixP->fx_addsy); |
10617 | } | |
10618 | #endif | |
252b5132 RH |
10619 | |
10620 | /* Fix a few things - the dynamic linker expects certain values here, | |
0234cb7c | 10621 | and we must not disappoint it. */ |
252b5132 | 10622 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 10623 | if (IS_ELF && fixP->fx_addsy) |
47926f60 KH |
10624 | switch (fixP->fx_r_type) |
10625 | { | |
10626 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 10627 | case BFD_RELOC_X86_64_PLT32: |
b9519cfe L |
10628 | /* Make the jump instruction point to the address of the operand. |
10629 | At runtime we merely add the offset to the actual PLT entry. | |
10630 | NB: Subtract the offset size only for jump instructions. */ | |
10631 | if (fixP->fx_pcrel) | |
10632 | value = -4; | |
47926f60 | 10633 | break; |
31312f95 | 10634 | |
13ae64f3 JJ |
10635 | case BFD_RELOC_386_TLS_GD: |
10636 | case BFD_RELOC_386_TLS_LDM: | |
13ae64f3 | 10637 | case BFD_RELOC_386_TLS_IE_32: |
37e55690 JJ |
10638 | case BFD_RELOC_386_TLS_IE: |
10639 | case BFD_RELOC_386_TLS_GOTIE: | |
67a4f2b7 | 10640 | case BFD_RELOC_386_TLS_GOTDESC: |
bffbf940 JJ |
10641 | case BFD_RELOC_X86_64_TLSGD: |
10642 | case BFD_RELOC_X86_64_TLSLD: | |
10643 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 | 10644 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
00f7efb6 JJ |
10645 | value = 0; /* Fully resolved at runtime. No addend. */ |
10646 | /* Fallthrough */ | |
10647 | case BFD_RELOC_386_TLS_LE: | |
10648 | case BFD_RELOC_386_TLS_LDO_32: | |
10649 | case BFD_RELOC_386_TLS_LE_32: | |
10650 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 10651 | case BFD_RELOC_X86_64_DTPOFF64: |
00f7efb6 | 10652 | case BFD_RELOC_X86_64_TPOFF32: |
d6ab8113 | 10653 | case BFD_RELOC_X86_64_TPOFF64: |
00f7efb6 JJ |
10654 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
10655 | break; | |
10656 | ||
67a4f2b7 AO |
10657 | case BFD_RELOC_386_TLS_DESC_CALL: |
10658 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
10659 | value = 0; /* Fully resolved at runtime. No addend. */ | |
10660 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
10661 | fixP->fx_done = 0; | |
10662 | return; | |
10663 | ||
47926f60 KH |
10664 | case BFD_RELOC_VTABLE_INHERIT: |
10665 | case BFD_RELOC_VTABLE_ENTRY: | |
10666 | fixP->fx_done = 0; | |
94f592af | 10667 | return; |
47926f60 KH |
10668 | |
10669 | default: | |
10670 | break; | |
10671 | } | |
10672 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
c6682705 | 10673 | *valP = value; |
f86103b7 | 10674 | #endif /* !defined (TE_Mach) */ |
3e73aa7c | 10675 | |
3e73aa7c | 10676 | /* Are we finished with this relocation now? */ |
c6682705 | 10677 | if (fixP->fx_addsy == NULL) |
3e73aa7c | 10678 | fixP->fx_done = 1; |
fbeb56a4 DK |
10679 | #if defined (OBJ_COFF) && defined (TE_PE) |
10680 | else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) | |
10681 | { | |
10682 | fixP->fx_done = 0; | |
10683 | /* Remember value for tc_gen_reloc. */ | |
10684 | fixP->fx_addnumber = value; | |
10685 | /* Clear out the frag for now. */ | |
10686 | value = 0; | |
10687 | } | |
10688 | #endif | |
3e73aa7c JH |
10689 | else if (use_rela_relocations) |
10690 | { | |
10691 | fixP->fx_no_overflow = 1; | |
062cd5e7 AS |
10692 | /* Remember value for tc_gen_reloc. */ |
10693 | fixP->fx_addnumber = value; | |
3e73aa7c JH |
10694 | value = 0; |
10695 | } | |
f86103b7 | 10696 | |
94f592af | 10697 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 10698 | } |
252b5132 | 10699 | \f |
6d4af3c2 | 10700 | const char * |
499ac353 | 10701 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 10702 | { |
499ac353 NC |
10703 | /* This outputs the LITTLENUMs in REVERSE order; |
10704 | in accord with the bigendian 386. */ | |
10705 | return ieee_md_atof (type, litP, sizeP, FALSE); | |
252b5132 RH |
10706 | } |
10707 | \f | |
2d545b82 | 10708 | static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; |
252b5132 | 10709 | |
252b5132 | 10710 | static char * |
e3bb37b5 | 10711 | output_invalid (int c) |
252b5132 | 10712 | { |
3882b010 | 10713 | if (ISPRINT (c)) |
f9f21a03 L |
10714 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
10715 | "'%c'", c); | |
252b5132 | 10716 | else |
f9f21a03 | 10717 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
2d545b82 | 10718 | "(0x%x)", (unsigned char) c); |
252b5132 RH |
10719 | return output_invalid_buf; |
10720 | } | |
10721 | ||
af6bdddf | 10722 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
10723 | |
10724 | static const reg_entry * | |
4d1bb795 | 10725 | parse_real_register (char *reg_string, char **end_op) |
252b5132 | 10726 | { |
af6bdddf AM |
10727 | char *s = reg_string; |
10728 | char *p; | |
252b5132 RH |
10729 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
10730 | const reg_entry *r; | |
10731 | ||
10732 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
10733 | if (*s == REGISTER_PREFIX) | |
10734 | ++s; | |
10735 | ||
10736 | if (is_space_char (*s)) | |
10737 | ++s; | |
10738 | ||
10739 | p = reg_name_given; | |
af6bdddf | 10740 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
10741 | { |
10742 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
10743 | return (const reg_entry *) NULL; |
10744 | s++; | |
252b5132 RH |
10745 | } |
10746 | ||
6588847e DN |
10747 | /* For naked regs, make sure that we are not dealing with an identifier. |
10748 | This prevents confusing an identifier like `eax_var' with register | |
10749 | `eax'. */ | |
10750 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
10751 | return (const reg_entry *) NULL; | |
10752 | ||
af6bdddf | 10753 | *end_op = s; |
252b5132 RH |
10754 | |
10755 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
10756 | ||
5f47d35b | 10757 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
47926f60 | 10758 | if (r == i386_regtab /* %st is first entry of table */) |
5f47d35b | 10759 | { |
0e0eea78 JB |
10760 | if (!cpu_arch_flags.bitfield.cpu8087 |
10761 | && !cpu_arch_flags.bitfield.cpu287 | |
10762 | && !cpu_arch_flags.bitfield.cpu387) | |
10763 | return (const reg_entry *) NULL; | |
10764 | ||
5f47d35b AM |
10765 | if (is_space_char (*s)) |
10766 | ++s; | |
10767 | if (*s == '(') | |
10768 | { | |
af6bdddf | 10769 | ++s; |
5f47d35b AM |
10770 | if (is_space_char (*s)) |
10771 | ++s; | |
10772 | if (*s >= '0' && *s <= '7') | |
10773 | { | |
db557034 | 10774 | int fpr = *s - '0'; |
af6bdddf | 10775 | ++s; |
5f47d35b AM |
10776 | if (is_space_char (*s)) |
10777 | ++s; | |
10778 | if (*s == ')') | |
10779 | { | |
10780 | *end_op = s + 1; | |
1e9cc1c2 | 10781 | r = (const reg_entry *) hash_find (reg_hash, "st(0)"); |
db557034 AM |
10782 | know (r); |
10783 | return r + fpr; | |
5f47d35b | 10784 | } |
5f47d35b | 10785 | } |
47926f60 | 10786 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
10787 | return (const reg_entry *) NULL; |
10788 | } | |
10789 | } | |
10790 | ||
a60de03c JB |
10791 | if (r == NULL || allow_pseudo_reg) |
10792 | return r; | |
10793 | ||
0dfbf9d7 | 10794 | if (operand_type_all_zero (&r->reg_type)) |
a60de03c JB |
10795 | return (const reg_entry *) NULL; |
10796 | ||
dc821c5f | 10797 | if ((r->reg_type.bitfield.dword |
192dc9c6 JB |
10798 | || r->reg_type.bitfield.sreg3 |
10799 | || r->reg_type.bitfield.control | |
10800 | || r->reg_type.bitfield.debug | |
10801 | || r->reg_type.bitfield.test) | |
10802 | && !cpu_arch_flags.bitfield.cpui386) | |
10803 | return (const reg_entry *) NULL; | |
10804 | ||
6e041cf4 | 10805 | if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx) |
192dc9c6 JB |
10806 | return (const reg_entry *) NULL; |
10807 | ||
6e041cf4 JB |
10808 | if (!cpu_arch_flags.bitfield.cpuavx512f) |
10809 | { | |
10810 | if (r->reg_type.bitfield.zmmword || r->reg_type.bitfield.regmask) | |
10811 | return (const reg_entry *) NULL; | |
40f12533 | 10812 | |
6e041cf4 JB |
10813 | if (!cpu_arch_flags.bitfield.cpuavx) |
10814 | { | |
10815 | if (r->reg_type.bitfield.ymmword) | |
10816 | return (const reg_entry *) NULL; | |
1848e567 | 10817 | |
6e041cf4 JB |
10818 | if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword) |
10819 | return (const reg_entry *) NULL; | |
10820 | } | |
10821 | } | |
43234a1e | 10822 | |
1adf7f56 JB |
10823 | if (r->reg_type.bitfield.regbnd && !cpu_arch_flags.bitfield.cpumpx) |
10824 | return (const reg_entry *) NULL; | |
10825 | ||
db51cc60 | 10826 | /* Don't allow fake index register unless allow_index_reg isn't 0. */ |
e968fc9b | 10827 | if (!allow_index_reg && r->reg_num == RegIZ) |
db51cc60 L |
10828 | return (const reg_entry *) NULL; |
10829 | ||
1d3f8286 JB |
10830 | /* Upper 16 vector registers are only available with VREX in 64bit |
10831 | mode, and require EVEX encoding. */ | |
10832 | if (r->reg_flags & RegVRex) | |
43234a1e | 10833 | { |
e951d5ca | 10834 | if (!cpu_arch_flags.bitfield.cpuavx512f |
43234a1e L |
10835 | || flag_code != CODE_64BIT) |
10836 | return (const reg_entry *) NULL; | |
1d3f8286 JB |
10837 | |
10838 | i.vec_encoding = vex_encoding_evex; | |
43234a1e L |
10839 | } |
10840 | ||
4787f4a5 JB |
10841 | if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword) |
10842 | && (!cpu_arch_flags.bitfield.cpulm || !r->reg_type.bitfield.control) | |
1ae00879 | 10843 | && flag_code != CODE_64BIT) |
20f0a1fc | 10844 | return (const reg_entry *) NULL; |
1ae00879 | 10845 | |
b7240065 JB |
10846 | if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax) |
10847 | return (const reg_entry *) NULL; | |
10848 | ||
252b5132 RH |
10849 | return r; |
10850 | } | |
4d1bb795 JB |
10851 | |
10852 | /* REG_STRING starts *before* REGISTER_PREFIX. */ | |
10853 | ||
10854 | static const reg_entry * | |
10855 | parse_register (char *reg_string, char **end_op) | |
10856 | { | |
10857 | const reg_entry *r; | |
10858 | ||
10859 | if (*reg_string == REGISTER_PREFIX || allow_naked_reg) | |
10860 | r = parse_real_register (reg_string, end_op); | |
10861 | else | |
10862 | r = NULL; | |
10863 | if (!r) | |
10864 | { | |
10865 | char *save = input_line_pointer; | |
10866 | char c; | |
10867 | symbolS *symbolP; | |
10868 | ||
10869 | input_line_pointer = reg_string; | |
d02603dc | 10870 | c = get_symbol_name (®_string); |
4d1bb795 JB |
10871 | symbolP = symbol_find (reg_string); |
10872 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) | |
10873 | { | |
10874 | const expressionS *e = symbol_get_value_expression (symbolP); | |
10875 | ||
0398aac5 | 10876 | know (e->X_op == O_register); |
4eed87de | 10877 | know (e->X_add_number >= 0 |
c3fe08fa | 10878 | && (valueT) e->X_add_number < i386_regtab_size); |
4d1bb795 | 10879 | r = i386_regtab + e->X_add_number; |
d3bb6b49 | 10880 | if ((r->reg_flags & RegVRex)) |
86fa6981 | 10881 | i.vec_encoding = vex_encoding_evex; |
4d1bb795 JB |
10882 | *end_op = input_line_pointer; |
10883 | } | |
10884 | *input_line_pointer = c; | |
10885 | input_line_pointer = save; | |
10886 | } | |
10887 | return r; | |
10888 | } | |
10889 | ||
10890 | int | |
10891 | i386_parse_name (char *name, expressionS *e, char *nextcharP) | |
10892 | { | |
10893 | const reg_entry *r; | |
10894 | char *end = input_line_pointer; | |
10895 | ||
10896 | *end = *nextcharP; | |
10897 | r = parse_register (name, &input_line_pointer); | |
10898 | if (r && end <= input_line_pointer) | |
10899 | { | |
10900 | *nextcharP = *input_line_pointer; | |
10901 | *input_line_pointer = 0; | |
10902 | e->X_op = O_register; | |
10903 | e->X_add_number = r - i386_regtab; | |
10904 | return 1; | |
10905 | } | |
10906 | input_line_pointer = end; | |
10907 | *end = 0; | |
ee86248c | 10908 | return intel_syntax ? i386_intel_parse_name (name, e) : 0; |
4d1bb795 JB |
10909 | } |
10910 | ||
10911 | void | |
10912 | md_operand (expressionS *e) | |
10913 | { | |
ee86248c JB |
10914 | char *end; |
10915 | const reg_entry *r; | |
4d1bb795 | 10916 | |
ee86248c JB |
10917 | switch (*input_line_pointer) |
10918 | { | |
10919 | case REGISTER_PREFIX: | |
10920 | r = parse_real_register (input_line_pointer, &end); | |
4d1bb795 JB |
10921 | if (r) |
10922 | { | |
10923 | e->X_op = O_register; | |
10924 | e->X_add_number = r - i386_regtab; | |
10925 | input_line_pointer = end; | |
10926 | } | |
ee86248c JB |
10927 | break; |
10928 | ||
10929 | case '[': | |
9c2799c2 | 10930 | gas_assert (intel_syntax); |
ee86248c JB |
10931 | end = input_line_pointer++; |
10932 | expression (e); | |
10933 | if (*input_line_pointer == ']') | |
10934 | { | |
10935 | ++input_line_pointer; | |
10936 | e->X_op_symbol = make_expr_symbol (e); | |
10937 | e->X_add_symbol = NULL; | |
10938 | e->X_add_number = 0; | |
10939 | e->X_op = O_index; | |
10940 | } | |
10941 | else | |
10942 | { | |
10943 | e->X_op = O_absent; | |
10944 | input_line_pointer = end; | |
10945 | } | |
10946 | break; | |
4d1bb795 JB |
10947 | } |
10948 | } | |
10949 | ||
252b5132 | 10950 | \f |
4cc782b5 | 10951 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
b6f8c7c4 | 10952 | const char *md_shortopts = "kVQ:sqnO::"; |
252b5132 | 10953 | #else |
b6f8c7c4 | 10954 | const char *md_shortopts = "qnO::"; |
252b5132 | 10955 | #endif |
6e0b89ee | 10956 | |
3e73aa7c | 10957 | #define OPTION_32 (OPTION_MD_BASE + 0) |
b3b91714 AM |
10958 | #define OPTION_64 (OPTION_MD_BASE + 1) |
10959 | #define OPTION_DIVIDE (OPTION_MD_BASE + 2) | |
9103f4f4 L |
10960 | #define OPTION_MARCH (OPTION_MD_BASE + 3) |
10961 | #define OPTION_MTUNE (OPTION_MD_BASE + 4) | |
1efbbeb4 L |
10962 | #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) |
10963 | #define OPTION_MSYNTAX (OPTION_MD_BASE + 6) | |
10964 | #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) | |
10965 | #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) | |
bd5dea88 | 10966 | #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9) |
c0f3af97 | 10967 | #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10) |
daf50ae7 | 10968 | #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11) |
7bab8ab5 JB |
10969 | #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12) |
10970 | #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13) | |
10971 | #define OPTION_X32 (OPTION_MD_BASE + 14) | |
7e8b059b | 10972 | #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15) |
43234a1e L |
10973 | #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16) |
10974 | #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17) | |
167ad85b | 10975 | #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18) |
d1982f93 | 10976 | #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19) |
d3d3c6db | 10977 | #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20) |
8dcea932 | 10978 | #define OPTION_MSHARED (OPTION_MD_BASE + 21) |
5db04b09 L |
10979 | #define OPTION_MAMD64 (OPTION_MD_BASE + 22) |
10980 | #define OPTION_MINTEL64 (OPTION_MD_BASE + 23) | |
e4e00185 | 10981 | #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24) |
b4a3a7b4 | 10982 | #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25) |
03751133 | 10983 | #define OPTION_MVEXWIG (OPTION_MD_BASE + 26) |
b3b91714 | 10984 | |
99ad8390 NC |
10985 | struct option md_longopts[] = |
10986 | { | |
3e73aa7c | 10987 | {"32", no_argument, NULL, OPTION_32}, |
321098a5 | 10988 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 10989 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c | 10990 | {"64", no_argument, NULL, OPTION_64}, |
351f65ca L |
10991 | #endif |
10992 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
570561f7 | 10993 | {"x32", no_argument, NULL, OPTION_X32}, |
8dcea932 | 10994 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
b4a3a7b4 | 10995 | {"mx86-used-note", required_argument, NULL, OPTION_X86_USED_NOTE}, |
6e0b89ee | 10996 | #endif |
b3b91714 | 10997 | {"divide", no_argument, NULL, OPTION_DIVIDE}, |
9103f4f4 L |
10998 | {"march", required_argument, NULL, OPTION_MARCH}, |
10999 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1efbbeb4 L |
11000 | {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, |
11001 | {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, | |
11002 | {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, | |
11003 | {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, | |
c0f3af97 | 11004 | {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX}, |
daf50ae7 | 11005 | {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK}, |
7bab8ab5 | 11006 | {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK}, |
539f890d | 11007 | {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR}, |
03751133 | 11008 | {"mvexwig", required_argument, NULL, OPTION_MVEXWIG}, |
7e8b059b | 11009 | {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX}, |
43234a1e L |
11010 | {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG}, |
11011 | {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG}, | |
167ad85b TG |
11012 | # if defined (TE_PE) || defined (TE_PEP) |
11013 | {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ}, | |
11014 | #endif | |
d1982f93 | 11015 | {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX}, |
e4e00185 | 11016 | {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD}, |
0cb4071e | 11017 | {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS}, |
d3d3c6db | 11018 | {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG}, |
5db04b09 L |
11019 | {"mamd64", no_argument, NULL, OPTION_MAMD64}, |
11020 | {"mintel64", no_argument, NULL, OPTION_MINTEL64}, | |
252b5132 RH |
11021 | {NULL, no_argument, NULL, 0} |
11022 | }; | |
11023 | size_t md_longopts_size = sizeof (md_longopts); | |
11024 | ||
11025 | int | |
17b9d67d | 11026 | md_parse_option (int c, const char *arg) |
252b5132 | 11027 | { |
91d6fa6a | 11028 | unsigned int j; |
293f5f65 | 11029 | char *arch, *next, *saved; |
9103f4f4 | 11030 | |
252b5132 RH |
11031 | switch (c) |
11032 | { | |
12b55ccc L |
11033 | case 'n': |
11034 | optimize_align_code = 0; | |
11035 | break; | |
11036 | ||
a38cf1db AM |
11037 | case 'q': |
11038 | quiet_warnings = 1; | |
252b5132 RH |
11039 | break; |
11040 | ||
11041 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
11042 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
11043 | should be emitted or not. FIXME: Not implemented. */ | |
11044 | case 'Q': | |
252b5132 RH |
11045 | break; |
11046 | ||
11047 | /* -V: SVR4 argument to print version ID. */ | |
11048 | case 'V': | |
11049 | print_version_id (); | |
11050 | break; | |
11051 | ||
a38cf1db AM |
11052 | /* -k: Ignore for FreeBSD compatibility. */ |
11053 | case 'k': | |
252b5132 | 11054 | break; |
4cc782b5 ILT |
11055 | |
11056 | case 's': | |
11057 | /* -s: On i386 Solaris, this tells the native assembler to use | |
29b0f896 | 11058 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
4cc782b5 | 11059 | break; |
8dcea932 L |
11060 | |
11061 | case OPTION_MSHARED: | |
11062 | shared = 1; | |
11063 | break; | |
b4a3a7b4 L |
11064 | |
11065 | case OPTION_X86_USED_NOTE: | |
11066 | if (strcasecmp (arg, "yes") == 0) | |
11067 | x86_used_note = 1; | |
11068 | else if (strcasecmp (arg, "no") == 0) | |
11069 | x86_used_note = 0; | |
11070 | else | |
11071 | as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg); | |
11072 | break; | |
11073 | ||
11074 | ||
99ad8390 | 11075 | #endif |
321098a5 | 11076 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 11077 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c JH |
11078 | case OPTION_64: |
11079 | { | |
11080 | const char **list, **l; | |
11081 | ||
3e73aa7c JH |
11082 | list = bfd_target_list (); |
11083 | for (l = list; *l != NULL; l++) | |
8620418b | 11084 | if (CONST_STRNEQ (*l, "elf64-x86-64") |
99ad8390 NC |
11085 | || strcmp (*l, "coff-x86-64") == 0 |
11086 | || strcmp (*l, "pe-x86-64") == 0 | |
d382c579 TG |
11087 | || strcmp (*l, "pei-x86-64") == 0 |
11088 | || strcmp (*l, "mach-o-x86-64") == 0) | |
6e0b89ee AM |
11089 | { |
11090 | default_arch = "x86_64"; | |
11091 | break; | |
11092 | } | |
3e73aa7c | 11093 | if (*l == NULL) |
2b5d6a91 | 11094 | as_fatal (_("no compiled in support for x86_64")); |
3e73aa7c JH |
11095 | free (list); |
11096 | } | |
11097 | break; | |
11098 | #endif | |
252b5132 | 11099 | |
351f65ca | 11100 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
570561f7 | 11101 | case OPTION_X32: |
351f65ca L |
11102 | if (IS_ELF) |
11103 | { | |
11104 | const char **list, **l; | |
11105 | ||
11106 | list = bfd_target_list (); | |
11107 | for (l = list; *l != NULL; l++) | |
11108 | if (CONST_STRNEQ (*l, "elf32-x86-64")) | |
11109 | { | |
11110 | default_arch = "x86_64:32"; | |
11111 | break; | |
11112 | } | |
11113 | if (*l == NULL) | |
2b5d6a91 | 11114 | as_fatal (_("no compiled in support for 32bit x86_64")); |
351f65ca L |
11115 | free (list); |
11116 | } | |
11117 | else | |
11118 | as_fatal (_("32bit x86_64 is only supported for ELF")); | |
11119 | break; | |
11120 | #endif | |
11121 | ||
6e0b89ee AM |
11122 | case OPTION_32: |
11123 | default_arch = "i386"; | |
11124 | break; | |
11125 | ||
b3b91714 AM |
11126 | case OPTION_DIVIDE: |
11127 | #ifdef SVR4_COMMENT_CHARS | |
11128 | { | |
11129 | char *n, *t; | |
11130 | const char *s; | |
11131 | ||
add39d23 | 11132 | n = XNEWVEC (char, strlen (i386_comment_chars) + 1); |
b3b91714 AM |
11133 | t = n; |
11134 | for (s = i386_comment_chars; *s != '\0'; s++) | |
11135 | if (*s != '/') | |
11136 | *t++ = *s; | |
11137 | *t = '\0'; | |
11138 | i386_comment_chars = n; | |
11139 | } | |
11140 | #endif | |
11141 | break; | |
11142 | ||
9103f4f4 | 11143 | case OPTION_MARCH: |
293f5f65 L |
11144 | saved = xstrdup (arg); |
11145 | arch = saved; | |
11146 | /* Allow -march=+nosse. */ | |
11147 | if (*arch == '+') | |
11148 | arch++; | |
6305a203 | 11149 | do |
9103f4f4 | 11150 | { |
6305a203 | 11151 | if (*arch == '.') |
2b5d6a91 | 11152 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
11153 | next = strchr (arch, '+'); |
11154 | if (next) | |
11155 | *next++ = '\0'; | |
91d6fa6a | 11156 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 11157 | { |
91d6fa6a | 11158 | if (strcmp (arch, cpu_arch [j].name) == 0) |
ccc9c027 | 11159 | { |
6305a203 | 11160 | /* Processor. */ |
1ded5609 JB |
11161 | if (! cpu_arch[j].flags.bitfield.cpui386) |
11162 | continue; | |
11163 | ||
91d6fa6a | 11164 | cpu_arch_name = cpu_arch[j].name; |
6305a203 | 11165 | cpu_sub_arch_name = NULL; |
91d6fa6a NC |
11166 | cpu_arch_flags = cpu_arch[j].flags; |
11167 | cpu_arch_isa = cpu_arch[j].type; | |
11168 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
6305a203 L |
11169 | if (!cpu_arch_tune_set) |
11170 | { | |
11171 | cpu_arch_tune = cpu_arch_isa; | |
11172 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
11173 | } | |
11174 | break; | |
11175 | } | |
91d6fa6a NC |
11176 | else if (*cpu_arch [j].name == '.' |
11177 | && strcmp (arch, cpu_arch [j].name + 1) == 0) | |
6305a203 | 11178 | { |
33eaf5de | 11179 | /* ISA extension. */ |
6305a203 | 11180 | i386_cpu_flags flags; |
309d3373 | 11181 | |
293f5f65 L |
11182 | flags = cpu_flags_or (cpu_arch_flags, |
11183 | cpu_arch[j].flags); | |
81486035 | 11184 | |
5b64d091 | 11185 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
6305a203 L |
11186 | { |
11187 | if (cpu_sub_arch_name) | |
11188 | { | |
11189 | char *name = cpu_sub_arch_name; | |
11190 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 11191 | cpu_arch[j].name, |
1bf57e9f | 11192 | (const char *) NULL); |
6305a203 L |
11193 | free (name); |
11194 | } | |
11195 | else | |
91d6fa6a | 11196 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
6305a203 | 11197 | cpu_arch_flags = flags; |
a586129e | 11198 | cpu_arch_isa_flags = flags; |
6305a203 | 11199 | } |
0089dace L |
11200 | else |
11201 | cpu_arch_isa_flags | |
11202 | = cpu_flags_or (cpu_arch_isa_flags, | |
11203 | cpu_arch[j].flags); | |
6305a203 | 11204 | break; |
ccc9c027 | 11205 | } |
9103f4f4 | 11206 | } |
6305a203 | 11207 | |
293f5f65 L |
11208 | if (j >= ARRAY_SIZE (cpu_arch)) |
11209 | { | |
33eaf5de | 11210 | /* Disable an ISA extension. */ |
293f5f65 L |
11211 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
11212 | if (strcmp (arch, cpu_noarch [j].name) == 0) | |
11213 | { | |
11214 | i386_cpu_flags flags; | |
11215 | ||
11216 | flags = cpu_flags_and_not (cpu_arch_flags, | |
11217 | cpu_noarch[j].flags); | |
11218 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
11219 | { | |
11220 | if (cpu_sub_arch_name) | |
11221 | { | |
11222 | char *name = cpu_sub_arch_name; | |
11223 | cpu_sub_arch_name = concat (arch, | |
11224 | (const char *) NULL); | |
11225 | free (name); | |
11226 | } | |
11227 | else | |
11228 | cpu_sub_arch_name = xstrdup (arch); | |
11229 | cpu_arch_flags = flags; | |
11230 | cpu_arch_isa_flags = flags; | |
11231 | } | |
11232 | break; | |
11233 | } | |
11234 | ||
11235 | if (j >= ARRAY_SIZE (cpu_noarch)) | |
11236 | j = ARRAY_SIZE (cpu_arch); | |
11237 | } | |
11238 | ||
91d6fa6a | 11239 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 11240 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
11241 | |
11242 | arch = next; | |
9103f4f4 | 11243 | } |
293f5f65 L |
11244 | while (next != NULL); |
11245 | free (saved); | |
9103f4f4 L |
11246 | break; |
11247 | ||
11248 | case OPTION_MTUNE: | |
11249 | if (*arg == '.') | |
2b5d6a91 | 11250 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
91d6fa6a | 11251 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 11252 | { |
91d6fa6a | 11253 | if (strcmp (arg, cpu_arch [j].name) == 0) |
9103f4f4 | 11254 | { |
ccc9c027 | 11255 | cpu_arch_tune_set = 1; |
91d6fa6a NC |
11256 | cpu_arch_tune = cpu_arch [j].type; |
11257 | cpu_arch_tune_flags = cpu_arch[j].flags; | |
9103f4f4 L |
11258 | break; |
11259 | } | |
11260 | } | |
91d6fa6a | 11261 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 11262 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
9103f4f4 L |
11263 | break; |
11264 | ||
1efbbeb4 L |
11265 | case OPTION_MMNEMONIC: |
11266 | if (strcasecmp (arg, "att") == 0) | |
11267 | intel_mnemonic = 0; | |
11268 | else if (strcasecmp (arg, "intel") == 0) | |
11269 | intel_mnemonic = 1; | |
11270 | else | |
2b5d6a91 | 11271 | as_fatal (_("invalid -mmnemonic= option: `%s'"), arg); |
1efbbeb4 L |
11272 | break; |
11273 | ||
11274 | case OPTION_MSYNTAX: | |
11275 | if (strcasecmp (arg, "att") == 0) | |
11276 | intel_syntax = 0; | |
11277 | else if (strcasecmp (arg, "intel") == 0) | |
11278 | intel_syntax = 1; | |
11279 | else | |
2b5d6a91 | 11280 | as_fatal (_("invalid -msyntax= option: `%s'"), arg); |
1efbbeb4 L |
11281 | break; |
11282 | ||
11283 | case OPTION_MINDEX_REG: | |
11284 | allow_index_reg = 1; | |
11285 | break; | |
11286 | ||
11287 | case OPTION_MNAKED_REG: | |
11288 | allow_naked_reg = 1; | |
11289 | break; | |
11290 | ||
c0f3af97 L |
11291 | case OPTION_MSSE2AVX: |
11292 | sse2avx = 1; | |
11293 | break; | |
11294 | ||
daf50ae7 L |
11295 | case OPTION_MSSE_CHECK: |
11296 | if (strcasecmp (arg, "error") == 0) | |
7bab8ab5 | 11297 | sse_check = check_error; |
daf50ae7 | 11298 | else if (strcasecmp (arg, "warning") == 0) |
7bab8ab5 | 11299 | sse_check = check_warning; |
daf50ae7 | 11300 | else if (strcasecmp (arg, "none") == 0) |
7bab8ab5 | 11301 | sse_check = check_none; |
daf50ae7 | 11302 | else |
2b5d6a91 | 11303 | as_fatal (_("invalid -msse-check= option: `%s'"), arg); |
daf50ae7 L |
11304 | break; |
11305 | ||
7bab8ab5 JB |
11306 | case OPTION_MOPERAND_CHECK: |
11307 | if (strcasecmp (arg, "error") == 0) | |
11308 | operand_check = check_error; | |
11309 | else if (strcasecmp (arg, "warning") == 0) | |
11310 | operand_check = check_warning; | |
11311 | else if (strcasecmp (arg, "none") == 0) | |
11312 | operand_check = check_none; | |
11313 | else | |
11314 | as_fatal (_("invalid -moperand-check= option: `%s'"), arg); | |
11315 | break; | |
11316 | ||
539f890d L |
11317 | case OPTION_MAVXSCALAR: |
11318 | if (strcasecmp (arg, "128") == 0) | |
11319 | avxscalar = vex128; | |
11320 | else if (strcasecmp (arg, "256") == 0) | |
11321 | avxscalar = vex256; | |
11322 | else | |
2b5d6a91 | 11323 | as_fatal (_("invalid -mavxscalar= option: `%s'"), arg); |
539f890d L |
11324 | break; |
11325 | ||
03751133 L |
11326 | case OPTION_MVEXWIG: |
11327 | if (strcmp (arg, "0") == 0) | |
11328 | vexwig = evexw0; | |
11329 | else if (strcmp (arg, "1") == 0) | |
11330 | vexwig = evexw1; | |
11331 | else | |
11332 | as_fatal (_("invalid -mvexwig= option: `%s'"), arg); | |
11333 | break; | |
11334 | ||
7e8b059b L |
11335 | case OPTION_MADD_BND_PREFIX: |
11336 | add_bnd_prefix = 1; | |
11337 | break; | |
11338 | ||
43234a1e L |
11339 | case OPTION_MEVEXLIG: |
11340 | if (strcmp (arg, "128") == 0) | |
11341 | evexlig = evexl128; | |
11342 | else if (strcmp (arg, "256") == 0) | |
11343 | evexlig = evexl256; | |
11344 | else if (strcmp (arg, "512") == 0) | |
11345 | evexlig = evexl512; | |
11346 | else | |
11347 | as_fatal (_("invalid -mevexlig= option: `%s'"), arg); | |
11348 | break; | |
11349 | ||
d3d3c6db IT |
11350 | case OPTION_MEVEXRCIG: |
11351 | if (strcmp (arg, "rne") == 0) | |
11352 | evexrcig = rne; | |
11353 | else if (strcmp (arg, "rd") == 0) | |
11354 | evexrcig = rd; | |
11355 | else if (strcmp (arg, "ru") == 0) | |
11356 | evexrcig = ru; | |
11357 | else if (strcmp (arg, "rz") == 0) | |
11358 | evexrcig = rz; | |
11359 | else | |
11360 | as_fatal (_("invalid -mevexrcig= option: `%s'"), arg); | |
11361 | break; | |
11362 | ||
43234a1e L |
11363 | case OPTION_MEVEXWIG: |
11364 | if (strcmp (arg, "0") == 0) | |
11365 | evexwig = evexw0; | |
11366 | else if (strcmp (arg, "1") == 0) | |
11367 | evexwig = evexw1; | |
11368 | else | |
11369 | as_fatal (_("invalid -mevexwig= option: `%s'"), arg); | |
11370 | break; | |
11371 | ||
167ad85b TG |
11372 | # if defined (TE_PE) || defined (TE_PEP) |
11373 | case OPTION_MBIG_OBJ: | |
11374 | use_big_obj = 1; | |
11375 | break; | |
11376 | #endif | |
11377 | ||
d1982f93 | 11378 | case OPTION_MOMIT_LOCK_PREFIX: |
d022bddd IT |
11379 | if (strcasecmp (arg, "yes") == 0) |
11380 | omit_lock_prefix = 1; | |
11381 | else if (strcasecmp (arg, "no") == 0) | |
11382 | omit_lock_prefix = 0; | |
11383 | else | |
11384 | as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg); | |
11385 | break; | |
11386 | ||
e4e00185 AS |
11387 | case OPTION_MFENCE_AS_LOCK_ADD: |
11388 | if (strcasecmp (arg, "yes") == 0) | |
11389 | avoid_fence = 1; | |
11390 | else if (strcasecmp (arg, "no") == 0) | |
11391 | avoid_fence = 0; | |
11392 | else | |
11393 | as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg); | |
11394 | break; | |
11395 | ||
0cb4071e L |
11396 | case OPTION_MRELAX_RELOCATIONS: |
11397 | if (strcasecmp (arg, "yes") == 0) | |
11398 | generate_relax_relocations = 1; | |
11399 | else if (strcasecmp (arg, "no") == 0) | |
11400 | generate_relax_relocations = 0; | |
11401 | else | |
11402 | as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg); | |
11403 | break; | |
11404 | ||
5db04b09 | 11405 | case OPTION_MAMD64: |
e89c5eaa | 11406 | intel64 = 0; |
5db04b09 L |
11407 | break; |
11408 | ||
11409 | case OPTION_MINTEL64: | |
e89c5eaa | 11410 | intel64 = 1; |
5db04b09 L |
11411 | break; |
11412 | ||
b6f8c7c4 L |
11413 | case 'O': |
11414 | if (arg == NULL) | |
11415 | { | |
11416 | optimize = 1; | |
11417 | /* Turn off -Os. */ | |
11418 | optimize_for_space = 0; | |
11419 | } | |
11420 | else if (*arg == 's') | |
11421 | { | |
11422 | optimize_for_space = 1; | |
11423 | /* Turn on all encoding optimizations. */ | |
41fd2579 | 11424 | optimize = INT_MAX; |
b6f8c7c4 L |
11425 | } |
11426 | else | |
11427 | { | |
11428 | optimize = atoi (arg); | |
11429 | /* Turn off -Os. */ | |
11430 | optimize_for_space = 0; | |
11431 | } | |
11432 | break; | |
11433 | ||
252b5132 RH |
11434 | default: |
11435 | return 0; | |
11436 | } | |
11437 | return 1; | |
11438 | } | |
11439 | ||
8a2c8fef L |
11440 | #define MESSAGE_TEMPLATE \ |
11441 | " " | |
11442 | ||
293f5f65 L |
11443 | static char * |
11444 | output_message (FILE *stream, char *p, char *message, char *start, | |
11445 | int *left_p, const char *name, int len) | |
11446 | { | |
11447 | int size = sizeof (MESSAGE_TEMPLATE); | |
11448 | int left = *left_p; | |
11449 | ||
11450 | /* Reserve 2 spaces for ", " or ",\0" */ | |
11451 | left -= len + 2; | |
11452 | ||
11453 | /* Check if there is any room. */ | |
11454 | if (left >= 0) | |
11455 | { | |
11456 | if (p != start) | |
11457 | { | |
11458 | *p++ = ','; | |
11459 | *p++ = ' '; | |
11460 | } | |
11461 | p = mempcpy (p, name, len); | |
11462 | } | |
11463 | else | |
11464 | { | |
11465 | /* Output the current message now and start a new one. */ | |
11466 | *p++ = ','; | |
11467 | *p = '\0'; | |
11468 | fprintf (stream, "%s\n", message); | |
11469 | p = start; | |
11470 | left = size - (start - message) - len - 2; | |
11471 | ||
11472 | gas_assert (left >= 0); | |
11473 | ||
11474 | p = mempcpy (p, name, len); | |
11475 | } | |
11476 | ||
11477 | *left_p = left; | |
11478 | return p; | |
11479 | } | |
11480 | ||
8a2c8fef | 11481 | static void |
1ded5609 | 11482 | show_arch (FILE *stream, int ext, int check) |
8a2c8fef L |
11483 | { |
11484 | static char message[] = MESSAGE_TEMPLATE; | |
11485 | char *start = message + 27; | |
11486 | char *p; | |
11487 | int size = sizeof (MESSAGE_TEMPLATE); | |
11488 | int left; | |
11489 | const char *name; | |
11490 | int len; | |
11491 | unsigned int j; | |
11492 | ||
11493 | p = start; | |
11494 | left = size - (start - message); | |
11495 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) | |
11496 | { | |
11497 | /* Should it be skipped? */ | |
11498 | if (cpu_arch [j].skip) | |
11499 | continue; | |
11500 | ||
11501 | name = cpu_arch [j].name; | |
11502 | len = cpu_arch [j].len; | |
11503 | if (*name == '.') | |
11504 | { | |
11505 | /* It is an extension. Skip if we aren't asked to show it. */ | |
11506 | if (ext) | |
11507 | { | |
11508 | name++; | |
11509 | len--; | |
11510 | } | |
11511 | else | |
11512 | continue; | |
11513 | } | |
11514 | else if (ext) | |
11515 | { | |
11516 | /* It is an processor. Skip if we show only extension. */ | |
11517 | continue; | |
11518 | } | |
1ded5609 JB |
11519 | else if (check && ! cpu_arch[j].flags.bitfield.cpui386) |
11520 | { | |
11521 | /* It is an impossible processor - skip. */ | |
11522 | continue; | |
11523 | } | |
8a2c8fef | 11524 | |
293f5f65 | 11525 | p = output_message (stream, p, message, start, &left, name, len); |
8a2c8fef L |
11526 | } |
11527 | ||
293f5f65 L |
11528 | /* Display disabled extensions. */ |
11529 | if (ext) | |
11530 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) | |
11531 | { | |
11532 | name = cpu_noarch [j].name; | |
11533 | len = cpu_noarch [j].len; | |
11534 | p = output_message (stream, p, message, start, &left, name, | |
11535 | len); | |
11536 | } | |
11537 | ||
8a2c8fef L |
11538 | *p = '\0'; |
11539 | fprintf (stream, "%s\n", message); | |
11540 | } | |
11541 | ||
252b5132 | 11542 | void |
8a2c8fef | 11543 | md_show_usage (FILE *stream) |
252b5132 | 11544 | { |
4cc782b5 ILT |
11545 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
11546 | fprintf (stream, _("\ | |
a38cf1db AM |
11547 | -Q ignored\n\ |
11548 | -V print assembler version number\n\ | |
b3b91714 AM |
11549 | -k ignored\n")); |
11550 | #endif | |
11551 | fprintf (stream, _("\ | |
12b55ccc | 11552 | -n Do not optimize code alignment\n\ |
b3b91714 AM |
11553 | -q quieten some warnings\n")); |
11554 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
11555 | fprintf (stream, _("\ | |
a38cf1db | 11556 | -s ignored\n")); |
b3b91714 | 11557 | #endif |
d7f449c0 L |
11558 | #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
11559 | || defined (TE_PE) || defined (TE_PEP)) | |
751d281c | 11560 | fprintf (stream, _("\ |
570561f7 | 11561 | --32/--64/--x32 generate 32bit/64bit/x32 code\n")); |
751d281c | 11562 | #endif |
b3b91714 AM |
11563 | #ifdef SVR4_COMMENT_CHARS |
11564 | fprintf (stream, _("\ | |
11565 | --divide do not treat `/' as a comment character\n")); | |
a38cf1db AM |
11566 | #else |
11567 | fprintf (stream, _("\ | |
b3b91714 | 11568 | --divide ignored\n")); |
4cc782b5 | 11569 | #endif |
9103f4f4 | 11570 | fprintf (stream, _("\ |
6305a203 | 11571 | -march=CPU[,+EXTENSION...]\n\ |
8a2c8fef | 11572 | generate code for CPU and EXTENSION, CPU is one of:\n")); |
1ded5609 | 11573 | show_arch (stream, 0, 1); |
8a2c8fef L |
11574 | fprintf (stream, _("\ |
11575 | EXTENSION is combination of:\n")); | |
1ded5609 | 11576 | show_arch (stream, 1, 0); |
6305a203 | 11577 | fprintf (stream, _("\ |
8a2c8fef | 11578 | -mtune=CPU optimize for CPU, CPU is one of:\n")); |
1ded5609 | 11579 | show_arch (stream, 0, 0); |
ba104c83 | 11580 | fprintf (stream, _("\ |
c0f3af97 L |
11581 | -msse2avx encode SSE instructions with VEX prefix\n")); |
11582 | fprintf (stream, _("\ | |
7c5c05ef | 11583 | -msse-check=[none|error|warning] (default: warning)\n\ |
daf50ae7 L |
11584 | check SSE instructions\n")); |
11585 | fprintf (stream, _("\ | |
7c5c05ef | 11586 | -moperand-check=[none|error|warning] (default: warning)\n\ |
7bab8ab5 JB |
11587 | check operand combinations for validity\n")); |
11588 | fprintf (stream, _("\ | |
7c5c05ef L |
11589 | -mavxscalar=[128|256] (default: 128)\n\ |
11590 | encode scalar AVX instructions with specific vector\n\ | |
539f890d L |
11591 | length\n")); |
11592 | fprintf (stream, _("\ | |
03751133 L |
11593 | -mvexwig=[0|1] (default: 0)\n\ |
11594 | encode VEX instructions with specific VEX.W value\n\ | |
11595 | for VEX.W bit ignored instructions\n")); | |
11596 | fprintf (stream, _("\ | |
7c5c05ef L |
11597 | -mevexlig=[128|256|512] (default: 128)\n\ |
11598 | encode scalar EVEX instructions with specific vector\n\ | |
43234a1e L |
11599 | length\n")); |
11600 | fprintf (stream, _("\ | |
7c5c05ef L |
11601 | -mevexwig=[0|1] (default: 0)\n\ |
11602 | encode EVEX instructions with specific EVEX.W value\n\ | |
43234a1e L |
11603 | for EVEX.W bit ignored instructions\n")); |
11604 | fprintf (stream, _("\ | |
7c5c05ef | 11605 | -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\ |
d3d3c6db IT |
11606 | encode EVEX instructions with specific EVEX.RC value\n\ |
11607 | for SAE-only ignored instructions\n")); | |
11608 | fprintf (stream, _("\ | |
7c5c05ef L |
11609 | -mmnemonic=[att|intel] ")); |
11610 | if (SYSV386_COMPAT) | |
11611 | fprintf (stream, _("(default: att)\n")); | |
11612 | else | |
11613 | fprintf (stream, _("(default: intel)\n")); | |
11614 | fprintf (stream, _("\ | |
11615 | use AT&T/Intel mnemonic\n")); | |
ba104c83 | 11616 | fprintf (stream, _("\ |
7c5c05ef L |
11617 | -msyntax=[att|intel] (default: att)\n\ |
11618 | use AT&T/Intel syntax\n")); | |
ba104c83 L |
11619 | fprintf (stream, _("\ |
11620 | -mindex-reg support pseudo index registers\n")); | |
11621 | fprintf (stream, _("\ | |
11622 | -mnaked-reg don't require `%%' prefix for registers\n")); | |
11623 | fprintf (stream, _("\ | |
7e8b059b | 11624 | -madd-bnd-prefix add BND prefix for all valid branches\n")); |
b4a3a7b4 | 11625 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8dcea932 L |
11626 | fprintf (stream, _("\ |
11627 | -mshared disable branch optimization for shared code\n")); | |
b4a3a7b4 L |
11628 | fprintf (stream, _("\ |
11629 | -mx86-used-note=[no|yes] ")); | |
11630 | if (DEFAULT_X86_USED_NOTE) | |
11631 | fprintf (stream, _("(default: yes)\n")); | |
11632 | else | |
11633 | fprintf (stream, _("(default: no)\n")); | |
11634 | fprintf (stream, _("\ | |
11635 | generate x86 used ISA and feature properties\n")); | |
11636 | #endif | |
11637 | #if defined (TE_PE) || defined (TE_PEP) | |
167ad85b TG |
11638 | fprintf (stream, _("\ |
11639 | -mbig-obj generate big object files\n")); | |
11640 | #endif | |
d022bddd | 11641 | fprintf (stream, _("\ |
7c5c05ef | 11642 | -momit-lock-prefix=[no|yes] (default: no)\n\ |
d022bddd | 11643 | strip all lock prefixes\n")); |
5db04b09 | 11644 | fprintf (stream, _("\ |
7c5c05ef | 11645 | -mfence-as-lock-add=[no|yes] (default: no)\n\ |
e4e00185 AS |
11646 | encode lfence, mfence and sfence as\n\ |
11647 | lock addl $0x0, (%%{re}sp)\n")); | |
11648 | fprintf (stream, _("\ | |
7c5c05ef L |
11649 | -mrelax-relocations=[no|yes] ")); |
11650 | if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS) | |
11651 | fprintf (stream, _("(default: yes)\n")); | |
11652 | else | |
11653 | fprintf (stream, _("(default: no)\n")); | |
11654 | fprintf (stream, _("\ | |
0cb4071e L |
11655 | generate relax relocations\n")); |
11656 | fprintf (stream, _("\ | |
7c5c05ef | 11657 | -mamd64 accept only AMD64 ISA [default]\n")); |
5db04b09 L |
11658 | fprintf (stream, _("\ |
11659 | -mintel64 accept only Intel64 ISA\n")); | |
252b5132 RH |
11660 | } |
11661 | ||
3e73aa7c | 11662 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
321098a5 | 11663 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
e57f8c65 | 11664 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
252b5132 RH |
11665 | |
11666 | /* Pick the target format to use. */ | |
11667 | ||
47926f60 | 11668 | const char * |
e3bb37b5 | 11669 | i386_target_format (void) |
252b5132 | 11670 | { |
351f65ca L |
11671 | if (!strncmp (default_arch, "x86_64", 6)) |
11672 | { | |
11673 | update_code_flag (CODE_64BIT, 1); | |
11674 | if (default_arch[6] == '\0') | |
7f56bc95 | 11675 | x86_elf_abi = X86_64_ABI; |
351f65ca | 11676 | else |
7f56bc95 | 11677 | x86_elf_abi = X86_64_X32_ABI; |
351f65ca | 11678 | } |
3e73aa7c | 11679 | else if (!strcmp (default_arch, "i386")) |
78f12dd3 | 11680 | update_code_flag (CODE_32BIT, 1); |
5197d474 L |
11681 | else if (!strcmp (default_arch, "iamcu")) |
11682 | { | |
11683 | update_code_flag (CODE_32BIT, 1); | |
11684 | if (cpu_arch_isa == PROCESSOR_UNKNOWN) | |
11685 | { | |
11686 | static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS; | |
11687 | cpu_arch_name = "iamcu"; | |
11688 | cpu_sub_arch_name = NULL; | |
11689 | cpu_arch_flags = iamcu_flags; | |
11690 | cpu_arch_isa = PROCESSOR_IAMCU; | |
11691 | cpu_arch_isa_flags = iamcu_flags; | |
11692 | if (!cpu_arch_tune_set) | |
11693 | { | |
11694 | cpu_arch_tune = cpu_arch_isa; | |
11695 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
11696 | } | |
11697 | } | |
8d471ec1 | 11698 | else if (cpu_arch_isa != PROCESSOR_IAMCU) |
5197d474 L |
11699 | as_fatal (_("Intel MCU doesn't support `%s' architecture"), |
11700 | cpu_arch_name); | |
11701 | } | |
3e73aa7c | 11702 | else |
2b5d6a91 | 11703 | as_fatal (_("unknown architecture")); |
89507696 JB |
11704 | |
11705 | if (cpu_flags_all_zero (&cpu_arch_isa_flags)) | |
11706 | cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
11707 | if (cpu_flags_all_zero (&cpu_arch_tune_flags)) | |
11708 | cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
11709 | ||
252b5132 RH |
11710 | switch (OUTPUT_FLAVOR) |
11711 | { | |
9384f2ff | 11712 | #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT) |
4c63da97 | 11713 | case bfd_target_aout_flavour: |
47926f60 | 11714 | return AOUT_TARGET_FORMAT; |
4c63da97 | 11715 | #endif |
9384f2ff AM |
11716 | #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF) |
11717 | # if defined (TE_PE) || defined (TE_PEP) | |
11718 | case bfd_target_coff_flavour: | |
167ad85b TG |
11719 | if (flag_code == CODE_64BIT) |
11720 | return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64"; | |
11721 | else | |
11722 | return "pe-i386"; | |
9384f2ff | 11723 | # elif defined (TE_GO32) |
0561d57c JK |
11724 | case bfd_target_coff_flavour: |
11725 | return "coff-go32"; | |
9384f2ff | 11726 | # else |
252b5132 RH |
11727 | case bfd_target_coff_flavour: |
11728 | return "coff-i386"; | |
9384f2ff | 11729 | # endif |
4c63da97 | 11730 | #endif |
3e73aa7c | 11731 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 11732 | case bfd_target_elf_flavour: |
3e73aa7c | 11733 | { |
351f65ca L |
11734 | const char *format; |
11735 | ||
11736 | switch (x86_elf_abi) | |
4fa24527 | 11737 | { |
351f65ca L |
11738 | default: |
11739 | format = ELF_TARGET_FORMAT; | |
11740 | break; | |
7f56bc95 | 11741 | case X86_64_ABI: |
351f65ca | 11742 | use_rela_relocations = 1; |
4fa24527 | 11743 | object_64bit = 1; |
351f65ca L |
11744 | format = ELF_TARGET_FORMAT64; |
11745 | break; | |
7f56bc95 | 11746 | case X86_64_X32_ABI: |
4fa24527 | 11747 | use_rela_relocations = 1; |
351f65ca | 11748 | object_64bit = 1; |
862be3fb | 11749 | disallow_64bit_reloc = 1; |
351f65ca L |
11750 | format = ELF_TARGET_FORMAT32; |
11751 | break; | |
4fa24527 | 11752 | } |
3632d14b | 11753 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 11754 | { |
7f56bc95 | 11755 | if (x86_elf_abi != X86_64_ABI) |
8a9036a4 L |
11756 | as_fatal (_("Intel L1OM is 64bit only")); |
11757 | return ELF_TARGET_L1OM_FORMAT; | |
11758 | } | |
b49f93f6 | 11759 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
7a9068fe L |
11760 | { |
11761 | if (x86_elf_abi != X86_64_ABI) | |
11762 | as_fatal (_("Intel K1OM is 64bit only")); | |
11763 | return ELF_TARGET_K1OM_FORMAT; | |
11764 | } | |
81486035 L |
11765 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
11766 | { | |
11767 | if (x86_elf_abi != I386_ABI) | |
11768 | as_fatal (_("Intel MCU is 32bit only")); | |
11769 | return ELF_TARGET_IAMCU_FORMAT; | |
11770 | } | |
8a9036a4 | 11771 | else |
351f65ca | 11772 | return format; |
3e73aa7c | 11773 | } |
e57f8c65 TG |
11774 | #endif |
11775 | #if defined (OBJ_MACH_O) | |
11776 | case bfd_target_mach_o_flavour: | |
d382c579 TG |
11777 | if (flag_code == CODE_64BIT) |
11778 | { | |
11779 | use_rela_relocations = 1; | |
11780 | object_64bit = 1; | |
11781 | return "mach-o-x86-64"; | |
11782 | } | |
11783 | else | |
11784 | return "mach-o-i386"; | |
4c63da97 | 11785 | #endif |
252b5132 RH |
11786 | default: |
11787 | abort (); | |
11788 | return NULL; | |
11789 | } | |
11790 | } | |
11791 | ||
47926f60 | 11792 | #endif /* OBJ_MAYBE_ more than one */ |
252b5132 | 11793 | \f |
252b5132 | 11794 | symbolS * |
7016a5d5 | 11795 | md_undefined_symbol (char *name) |
252b5132 | 11796 | { |
18dc2407 ILT |
11797 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
11798 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
11799 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
11800 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
11801 | { |
11802 | if (!GOT_symbol) | |
11803 | { | |
11804 | if (symbol_find (name)) | |
11805 | as_bad (_("GOT already in symbol table")); | |
11806 | GOT_symbol = symbol_new (name, undefined_section, | |
11807 | (valueT) 0, &zero_address_frag); | |
11808 | }; | |
11809 | return GOT_symbol; | |
11810 | } | |
252b5132 RH |
11811 | return 0; |
11812 | } | |
11813 | ||
11814 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 11815 | |
252b5132 | 11816 | valueT |
7016a5d5 | 11817 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
252b5132 | 11818 | { |
4c63da97 AM |
11819 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
11820 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
11821 | { | |
11822 | /* For a.out, force the section size to be aligned. If we don't do | |
11823 | this, BFD will align it for us, but it will not write out the | |
11824 | final bytes of the section. This may be a bug in BFD, but it is | |
11825 | easier to fix it here since that is how the other a.out targets | |
11826 | work. */ | |
11827 | int align; | |
11828 | ||
11829 | align = bfd_get_section_alignment (stdoutput, segment); | |
8d3842cd | 11830 | size = ((size + (1 << align) - 1) & (-((valueT) 1 << align))); |
4c63da97 | 11831 | } |
252b5132 RH |
11832 | #endif |
11833 | ||
11834 | return size; | |
11835 | } | |
11836 | ||
11837 | /* On the i386, PC-relative offsets are relative to the start of the | |
11838 | next instruction. That is, the address of the offset, plus its | |
11839 | size, since the offset is always the last part of the insn. */ | |
11840 | ||
11841 | long | |
e3bb37b5 | 11842 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
11843 | { |
11844 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
11845 | } | |
11846 | ||
11847 | #ifndef I386COFF | |
11848 | ||
11849 | static void | |
e3bb37b5 | 11850 | s_bss (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 11851 | { |
29b0f896 | 11852 | int temp; |
252b5132 | 11853 | |
8a75718c JB |
11854 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
11855 | if (IS_ELF) | |
11856 | obj_elf_section_change_hook (); | |
11857 | #endif | |
252b5132 RH |
11858 | temp = get_absolute_expression (); |
11859 | subseg_set (bss_section, (subsegT) temp); | |
11860 | demand_empty_rest_of_line (); | |
11861 | } | |
11862 | ||
11863 | #endif | |
11864 | ||
252b5132 | 11865 | void |
e3bb37b5 | 11866 | i386_validate_fix (fixS *fixp) |
252b5132 | 11867 | { |
02a86693 | 11868 | if (fixp->fx_subsy) |
252b5132 | 11869 | { |
02a86693 | 11870 | if (fixp->fx_subsy == GOT_symbol) |
23df1078 | 11871 | { |
02a86693 L |
11872 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
11873 | { | |
11874 | if (!object_64bit) | |
11875 | abort (); | |
11876 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
11877 | if (fixp->fx_tcbit2) | |
56ceb5b5 L |
11878 | fixp->fx_r_type = (fixp->fx_tcbit |
11879 | ? BFD_RELOC_X86_64_REX_GOTPCRELX | |
11880 | : BFD_RELOC_X86_64_GOTPCRELX); | |
02a86693 L |
11881 | else |
11882 | #endif | |
11883 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
11884 | } | |
d6ab8113 | 11885 | else |
02a86693 L |
11886 | { |
11887 | if (!object_64bit) | |
11888 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
11889 | else | |
11890 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; | |
11891 | } | |
11892 | fixp->fx_subsy = 0; | |
23df1078 | 11893 | } |
252b5132 | 11894 | } |
02a86693 L |
11895 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
11896 | else if (!object_64bit) | |
11897 | { | |
11898 | if (fixp->fx_r_type == BFD_RELOC_386_GOT32 | |
11899 | && fixp->fx_tcbit2) | |
11900 | fixp->fx_r_type = BFD_RELOC_386_GOT32X; | |
11901 | } | |
11902 | #endif | |
252b5132 RH |
11903 | } |
11904 | ||
252b5132 | 11905 | arelent * |
7016a5d5 | 11906 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
11907 | { |
11908 | arelent *rel; | |
11909 | bfd_reloc_code_real_type code; | |
11910 | ||
11911 | switch (fixp->fx_r_type) | |
11912 | { | |
8ce3d284 | 11913 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
11914 | case BFD_RELOC_SIZE32: |
11915 | case BFD_RELOC_SIZE64: | |
11916 | if (S_IS_DEFINED (fixp->fx_addsy) | |
11917 | && !S_IS_EXTERNAL (fixp->fx_addsy)) | |
11918 | { | |
11919 | /* Resolve size relocation against local symbol to size of | |
11920 | the symbol plus addend. */ | |
11921 | valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset; | |
11922 | if (fixp->fx_r_type == BFD_RELOC_SIZE32 | |
11923 | && !fits_in_unsigned_long (value)) | |
11924 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
11925 | _("symbol size computation overflow")); | |
11926 | fixp->fx_addsy = NULL; | |
11927 | fixp->fx_subsy = NULL; | |
11928 | md_apply_fix (fixp, (valueT *) &value, NULL); | |
11929 | return NULL; | |
11930 | } | |
8ce3d284 | 11931 | #endif |
1a0670f3 | 11932 | /* Fall through. */ |
8fd4256d | 11933 | |
3e73aa7c JH |
11934 | case BFD_RELOC_X86_64_PLT32: |
11935 | case BFD_RELOC_X86_64_GOT32: | |
11936 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
11937 | case BFD_RELOC_X86_64_GOTPCRELX: |
11938 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
252b5132 RH |
11939 | case BFD_RELOC_386_PLT32: |
11940 | case BFD_RELOC_386_GOT32: | |
02a86693 | 11941 | case BFD_RELOC_386_GOT32X: |
252b5132 RH |
11942 | case BFD_RELOC_386_GOTOFF: |
11943 | case BFD_RELOC_386_GOTPC: | |
13ae64f3 JJ |
11944 | case BFD_RELOC_386_TLS_GD: |
11945 | case BFD_RELOC_386_TLS_LDM: | |
11946 | case BFD_RELOC_386_TLS_LDO_32: | |
11947 | case BFD_RELOC_386_TLS_IE_32: | |
37e55690 JJ |
11948 | case BFD_RELOC_386_TLS_IE: |
11949 | case BFD_RELOC_386_TLS_GOTIE: | |
13ae64f3 JJ |
11950 | case BFD_RELOC_386_TLS_LE_32: |
11951 | case BFD_RELOC_386_TLS_LE: | |
67a4f2b7 AO |
11952 | case BFD_RELOC_386_TLS_GOTDESC: |
11953 | case BFD_RELOC_386_TLS_DESC_CALL: | |
bffbf940 JJ |
11954 | case BFD_RELOC_X86_64_TLSGD: |
11955 | case BFD_RELOC_X86_64_TLSLD: | |
11956 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 11957 | case BFD_RELOC_X86_64_DTPOFF64: |
bffbf940 JJ |
11958 | case BFD_RELOC_X86_64_GOTTPOFF: |
11959 | case BFD_RELOC_X86_64_TPOFF32: | |
d6ab8113 JB |
11960 | case BFD_RELOC_X86_64_TPOFF64: |
11961 | case BFD_RELOC_X86_64_GOTOFF64: | |
11962 | case BFD_RELOC_X86_64_GOTPC32: | |
7b81dfbb AJ |
11963 | case BFD_RELOC_X86_64_GOT64: |
11964 | case BFD_RELOC_X86_64_GOTPCREL64: | |
11965 | case BFD_RELOC_X86_64_GOTPC64: | |
11966 | case BFD_RELOC_X86_64_GOTPLT64: | |
11967 | case BFD_RELOC_X86_64_PLTOFF64: | |
67a4f2b7 AO |
11968 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
11969 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
252b5132 RH |
11970 | case BFD_RELOC_RVA: |
11971 | case BFD_RELOC_VTABLE_ENTRY: | |
11972 | case BFD_RELOC_VTABLE_INHERIT: | |
6482c264 NC |
11973 | #ifdef TE_PE |
11974 | case BFD_RELOC_32_SECREL: | |
11975 | #endif | |
252b5132 RH |
11976 | code = fixp->fx_r_type; |
11977 | break; | |
dbbaec26 L |
11978 | case BFD_RELOC_X86_64_32S: |
11979 | if (!fixp->fx_pcrel) | |
11980 | { | |
11981 | /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ | |
11982 | code = fixp->fx_r_type; | |
11983 | break; | |
11984 | } | |
1a0670f3 | 11985 | /* Fall through. */ |
252b5132 | 11986 | default: |
93382f6d | 11987 | if (fixp->fx_pcrel) |
252b5132 | 11988 | { |
93382f6d AM |
11989 | switch (fixp->fx_size) |
11990 | { | |
11991 | default: | |
b091f402 AM |
11992 | as_bad_where (fixp->fx_file, fixp->fx_line, |
11993 | _("can not do %d byte pc-relative relocation"), | |
11994 | fixp->fx_size); | |
93382f6d AM |
11995 | code = BFD_RELOC_32_PCREL; |
11996 | break; | |
11997 | case 1: code = BFD_RELOC_8_PCREL; break; | |
11998 | case 2: code = BFD_RELOC_16_PCREL; break; | |
d258b828 | 11999 | case 4: code = BFD_RELOC_32_PCREL; break; |
d6ab8113 JB |
12000 | #ifdef BFD64 |
12001 | case 8: code = BFD_RELOC_64_PCREL; break; | |
12002 | #endif | |
93382f6d AM |
12003 | } |
12004 | } | |
12005 | else | |
12006 | { | |
12007 | switch (fixp->fx_size) | |
12008 | { | |
12009 | default: | |
b091f402 AM |
12010 | as_bad_where (fixp->fx_file, fixp->fx_line, |
12011 | _("can not do %d byte relocation"), | |
12012 | fixp->fx_size); | |
93382f6d AM |
12013 | code = BFD_RELOC_32; |
12014 | break; | |
12015 | case 1: code = BFD_RELOC_8; break; | |
12016 | case 2: code = BFD_RELOC_16; break; | |
12017 | case 4: code = BFD_RELOC_32; break; | |
937149dd | 12018 | #ifdef BFD64 |
3e73aa7c | 12019 | case 8: code = BFD_RELOC_64; break; |
937149dd | 12020 | #endif |
93382f6d | 12021 | } |
252b5132 RH |
12022 | } |
12023 | break; | |
12024 | } | |
252b5132 | 12025 | |
d182319b JB |
12026 | if ((code == BFD_RELOC_32 |
12027 | || code == BFD_RELOC_32_PCREL | |
12028 | || code == BFD_RELOC_X86_64_32S) | |
252b5132 RH |
12029 | && GOT_symbol |
12030 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c | 12031 | { |
4fa24527 | 12032 | if (!object_64bit) |
d6ab8113 JB |
12033 | code = BFD_RELOC_386_GOTPC; |
12034 | else | |
12035 | code = BFD_RELOC_X86_64_GOTPC32; | |
3e73aa7c | 12036 | } |
7b81dfbb AJ |
12037 | if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) |
12038 | && GOT_symbol | |
12039 | && fixp->fx_addsy == GOT_symbol) | |
12040 | { | |
12041 | code = BFD_RELOC_X86_64_GOTPC64; | |
12042 | } | |
252b5132 | 12043 | |
add39d23 TS |
12044 | rel = XNEW (arelent); |
12045 | rel->sym_ptr_ptr = XNEW (asymbol *); | |
49309057 | 12046 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
12047 | |
12048 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
c87db184 | 12049 | |
3e73aa7c JH |
12050 | if (!use_rela_relocations) |
12051 | { | |
12052 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
12053 | vtable entry to be used in the relocation's section offset. */ | |
12054 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
12055 | rel->address = fixp->fx_offset; | |
fbeb56a4 DK |
12056 | #if defined (OBJ_COFF) && defined (TE_PE) |
12057 | else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy)) | |
12058 | rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2); | |
12059 | else | |
12060 | #endif | |
c6682705 | 12061 | rel->addend = 0; |
3e73aa7c JH |
12062 | } |
12063 | /* Use the rela in 64bit mode. */ | |
252b5132 | 12064 | else |
3e73aa7c | 12065 | { |
862be3fb L |
12066 | if (disallow_64bit_reloc) |
12067 | switch (code) | |
12068 | { | |
862be3fb L |
12069 | case BFD_RELOC_X86_64_DTPOFF64: |
12070 | case BFD_RELOC_X86_64_TPOFF64: | |
12071 | case BFD_RELOC_64_PCREL: | |
12072 | case BFD_RELOC_X86_64_GOTOFF64: | |
12073 | case BFD_RELOC_X86_64_GOT64: | |
12074 | case BFD_RELOC_X86_64_GOTPCREL64: | |
12075 | case BFD_RELOC_X86_64_GOTPC64: | |
12076 | case BFD_RELOC_X86_64_GOTPLT64: | |
12077 | case BFD_RELOC_X86_64_PLTOFF64: | |
12078 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
12079 | _("cannot represent relocation type %s in x32 mode"), | |
12080 | bfd_get_reloc_code_name (code)); | |
12081 | break; | |
12082 | default: | |
12083 | break; | |
12084 | } | |
12085 | ||
062cd5e7 AS |
12086 | if (!fixp->fx_pcrel) |
12087 | rel->addend = fixp->fx_offset; | |
12088 | else | |
12089 | switch (code) | |
12090 | { | |
12091 | case BFD_RELOC_X86_64_PLT32: | |
12092 | case BFD_RELOC_X86_64_GOT32: | |
12093 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
12094 | case BFD_RELOC_X86_64_GOTPCRELX: |
12095 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
bffbf940 JJ |
12096 | case BFD_RELOC_X86_64_TLSGD: |
12097 | case BFD_RELOC_X86_64_TLSLD: | |
12098 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 AO |
12099 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
12100 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
062cd5e7 AS |
12101 | rel->addend = fixp->fx_offset - fixp->fx_size; |
12102 | break; | |
12103 | default: | |
12104 | rel->addend = (section->vma | |
12105 | - fixp->fx_size | |
12106 | + fixp->fx_addnumber | |
12107 | + md_pcrel_from (fixp)); | |
12108 | break; | |
12109 | } | |
3e73aa7c JH |
12110 | } |
12111 | ||
252b5132 RH |
12112 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
12113 | if (rel->howto == NULL) | |
12114 | { | |
12115 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 12116 | _("cannot represent relocation type %s"), |
252b5132 RH |
12117 | bfd_get_reloc_code_name (code)); |
12118 | /* Set howto to a garbage value so that we can keep going. */ | |
12119 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
9c2799c2 | 12120 | gas_assert (rel->howto != NULL); |
252b5132 RH |
12121 | } |
12122 | ||
12123 | return rel; | |
12124 | } | |
12125 | ||
ee86248c | 12126 | #include "tc-i386-intel.c" |
54cfded0 | 12127 | |
a60de03c JB |
12128 | void |
12129 | tc_x86_parse_to_dw2regnum (expressionS *exp) | |
54cfded0 | 12130 | { |
a60de03c JB |
12131 | int saved_naked_reg; |
12132 | char saved_register_dot; | |
54cfded0 | 12133 | |
a60de03c JB |
12134 | saved_naked_reg = allow_naked_reg; |
12135 | allow_naked_reg = 1; | |
12136 | saved_register_dot = register_chars['.']; | |
12137 | register_chars['.'] = '.'; | |
12138 | allow_pseudo_reg = 1; | |
12139 | expression_and_evaluate (exp); | |
12140 | allow_pseudo_reg = 0; | |
12141 | register_chars['.'] = saved_register_dot; | |
12142 | allow_naked_reg = saved_naked_reg; | |
12143 | ||
e96d56a1 | 12144 | if (exp->X_op == O_register && exp->X_add_number >= 0) |
54cfded0 | 12145 | { |
a60de03c JB |
12146 | if ((addressT) exp->X_add_number < i386_regtab_size) |
12147 | { | |
12148 | exp->X_op = O_constant; | |
12149 | exp->X_add_number = i386_regtab[exp->X_add_number] | |
12150 | .dw2_regnum[flag_code >> 1]; | |
12151 | } | |
12152 | else | |
12153 | exp->X_op = O_illegal; | |
54cfded0 | 12154 | } |
54cfded0 AM |
12155 | } |
12156 | ||
12157 | void | |
12158 | tc_x86_frame_initial_instructions (void) | |
12159 | { | |
a60de03c JB |
12160 | static unsigned int sp_regno[2]; |
12161 | ||
12162 | if (!sp_regno[flag_code >> 1]) | |
12163 | { | |
12164 | char *saved_input = input_line_pointer; | |
12165 | char sp[][4] = {"esp", "rsp"}; | |
12166 | expressionS exp; | |
a4447b93 | 12167 | |
a60de03c JB |
12168 | input_line_pointer = sp[flag_code >> 1]; |
12169 | tc_x86_parse_to_dw2regnum (&exp); | |
9c2799c2 | 12170 | gas_assert (exp.X_op == O_constant); |
a60de03c JB |
12171 | sp_regno[flag_code >> 1] = exp.X_add_number; |
12172 | input_line_pointer = saved_input; | |
12173 | } | |
a4447b93 | 12174 | |
61ff971f L |
12175 | cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment); |
12176 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); | |
54cfded0 | 12177 | } |
d2b2c203 | 12178 | |
d7921315 L |
12179 | int |
12180 | x86_dwarf2_addr_size (void) | |
12181 | { | |
12182 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) | |
12183 | if (x86_elf_abi == X86_64_X32_ABI) | |
12184 | return 4; | |
12185 | #endif | |
12186 | return bfd_arch_bits_per_address (stdoutput) / 8; | |
12187 | } | |
12188 | ||
d2b2c203 DJ |
12189 | int |
12190 | i386_elf_section_type (const char *str, size_t len) | |
12191 | { | |
12192 | if (flag_code == CODE_64BIT | |
12193 | && len == sizeof ("unwind") - 1 | |
12194 | && strncmp (str, "unwind", 6) == 0) | |
12195 | return SHT_X86_64_UNWIND; | |
12196 | ||
12197 | return -1; | |
12198 | } | |
bb41ade5 | 12199 | |
ad5fec3b EB |
12200 | #ifdef TE_SOLARIS |
12201 | void | |
12202 | i386_solaris_fix_up_eh_frame (segT sec) | |
12203 | { | |
12204 | if (flag_code == CODE_64BIT) | |
12205 | elf_section_type (sec) = SHT_X86_64_UNWIND; | |
12206 | } | |
12207 | #endif | |
12208 | ||
bb41ade5 AM |
12209 | #ifdef TE_PE |
12210 | void | |
12211 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) | |
12212 | { | |
91d6fa6a | 12213 | expressionS exp; |
bb41ade5 | 12214 | |
91d6fa6a NC |
12215 | exp.X_op = O_secrel; |
12216 | exp.X_add_symbol = symbol; | |
12217 | exp.X_add_number = 0; | |
12218 | emit_expr (&exp, size); | |
bb41ade5 AM |
12219 | } |
12220 | #endif | |
3b22753a L |
12221 | |
12222 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
12223 | /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ | |
12224 | ||
01e1a5bc | 12225 | bfd_vma |
6d4af3c2 | 12226 | x86_64_section_letter (int letter, const char **ptr_msg) |
3b22753a L |
12227 | { |
12228 | if (flag_code == CODE_64BIT) | |
12229 | { | |
12230 | if (letter == 'l') | |
12231 | return SHF_X86_64_LARGE; | |
12232 | ||
8f3bae45 | 12233 | *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string"); |
64e74474 | 12234 | } |
3b22753a | 12235 | else |
8f3bae45 | 12236 | *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string"); |
3b22753a L |
12237 | return -1; |
12238 | } | |
12239 | ||
01e1a5bc | 12240 | bfd_vma |
3b22753a L |
12241 | x86_64_section_word (char *str, size_t len) |
12242 | { | |
8620418b | 12243 | if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large")) |
3b22753a L |
12244 | return SHF_X86_64_LARGE; |
12245 | ||
12246 | return -1; | |
12247 | } | |
12248 | ||
12249 | static void | |
12250 | handle_large_common (int small ATTRIBUTE_UNUSED) | |
12251 | { | |
12252 | if (flag_code != CODE_64BIT) | |
12253 | { | |
12254 | s_comm_internal (0, elf_common_parse); | |
12255 | as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); | |
12256 | } | |
12257 | else | |
12258 | { | |
12259 | static segT lbss_section; | |
12260 | asection *saved_com_section_ptr = elf_com_section_ptr; | |
12261 | asection *saved_bss_section = bss_section; | |
12262 | ||
12263 | if (lbss_section == NULL) | |
12264 | { | |
12265 | flagword applicable; | |
12266 | segT seg = now_seg; | |
12267 | subsegT subseg = now_subseg; | |
12268 | ||
12269 | /* The .lbss section is for local .largecomm symbols. */ | |
12270 | lbss_section = subseg_new (".lbss", 0); | |
12271 | applicable = bfd_applicable_section_flags (stdoutput); | |
12272 | bfd_set_section_flags (stdoutput, lbss_section, | |
12273 | applicable & SEC_ALLOC); | |
12274 | seg_info (lbss_section)->bss = 1; | |
12275 | ||
12276 | subseg_set (seg, subseg); | |
12277 | } | |
12278 | ||
12279 | elf_com_section_ptr = &_bfd_elf_large_com_section; | |
12280 | bss_section = lbss_section; | |
12281 | ||
12282 | s_comm_internal (0, elf_common_parse); | |
12283 | ||
12284 | elf_com_section_ptr = saved_com_section_ptr; | |
12285 | bss_section = saved_bss_section; | |
12286 | } | |
12287 | } | |
12288 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |