Commit | Line | Data |
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252b5132 | 1 | /* i386.c -- Assemble code for the Intel 80386 |
f7e42eb4 NC |
2 | Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
3 | 2000, 2001 | |
47926f60 | 4 | Free Software Foundation, Inc. |
252b5132 RH |
5 | |
6 | This file is part of GAS, the GNU Assembler. | |
7 | ||
8 | GAS is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GAS is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GAS; see the file COPYING. If not, write to the Free | |
20 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
21 | 02111-1307, USA. */ | |
22 | ||
47926f60 KH |
23 | /* Intel 80386 machine specific gas. |
24 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 25 | x86_64 support by Jan Hubicka (jh@suse.cz) |
47926f60 KH |
26 | Bugs & suggestions are completely welcome. This is free software. |
27 | Please help us make it better. */ | |
252b5132 | 28 | |
252b5132 | 29 | #include "as.h" |
3882b010 | 30 | #include "safe-ctype.h" |
252b5132 | 31 | #include "subsegs.h" |
316e2c05 | 32 | #include "dwarf2dbg.h" |
252b5132 RH |
33 | #include "opcode/i386.h" |
34 | ||
252b5132 RH |
35 | #ifndef REGISTER_WARNINGS |
36 | #define REGISTER_WARNINGS 1 | |
37 | #endif | |
38 | ||
c3332e24 | 39 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 40 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
41 | #endif |
42 | ||
252b5132 RH |
43 | #ifndef SCALE1_WHEN_NO_INDEX |
44 | /* Specifying a scale factor besides 1 when there is no index is | |
45 | futile. eg. `mov (%ebx,2),%al' does exactly the same as | |
46 | `mov (%ebx),%al'. To slavishly follow what the programmer | |
47 | specified, set SCALE1_WHEN_NO_INDEX to 0. */ | |
48 | #define SCALE1_WHEN_NO_INDEX 1 | |
49 | #endif | |
50 | ||
246fcdee | 51 | #ifndef true |
252b5132 | 52 | #define true 1 |
246fcdee DJ |
53 | #endif |
54 | #ifndef false | |
252b5132 | 55 | #define false 0 |
246fcdee | 56 | #endif |
252b5132 RH |
57 | |
58 | static unsigned int mode_from_disp_size PARAMS ((unsigned int)); | |
847f7ad4 AM |
59 | static int fits_in_signed_byte PARAMS ((offsetT)); |
60 | static int fits_in_unsigned_byte PARAMS ((offsetT)); | |
61 | static int fits_in_unsigned_word PARAMS ((offsetT)); | |
62 | static int fits_in_signed_word PARAMS ((offsetT)); | |
3e73aa7c JH |
63 | static int fits_in_unsigned_long PARAMS ((offsetT)); |
64 | static int fits_in_signed_long PARAMS ((offsetT)); | |
847f7ad4 AM |
65 | static int smallest_imm_type PARAMS ((offsetT)); |
66 | static offsetT offset_in_range PARAMS ((offsetT, int)); | |
252b5132 | 67 | static int add_prefix PARAMS ((unsigned int)); |
3e73aa7c | 68 | static void set_code_flag PARAMS ((int)); |
47926f60 | 69 | static void set_16bit_gcc_code_flag PARAMS ((int)); |
252b5132 | 70 | static void set_intel_syntax PARAMS ((int)); |
e413e4e9 | 71 | static void set_cpu_arch PARAMS ((int)); |
252b5132 RH |
72 | |
73 | #ifdef BFD_ASSEMBLER | |
74 | static bfd_reloc_code_real_type reloc | |
3e73aa7c | 75 | PARAMS ((int, int, int, bfd_reloc_code_real_type)); |
f3c180ae AM |
76 | #define RELOC_ENUM enum bfd_reloc_code_real |
77 | #else | |
78 | #define RELOC_ENUM int | |
252b5132 RH |
79 | #endif |
80 | ||
3e73aa7c JH |
81 | #ifndef DEFAULT_ARCH |
82 | #define DEFAULT_ARCH "i386" | |
83 | #endif | |
a847613f | 84 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 85 | |
252b5132 | 86 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 87 | i386_insn. */ |
252b5132 | 88 | |
520dc8e8 AM |
89 | union i386_op |
90 | { | |
91 | expressionS *disps; | |
92 | expressionS *imms; | |
93 | const reg_entry *regs; | |
94 | }; | |
95 | ||
252b5132 RH |
96 | struct _i386_insn |
97 | { | |
47926f60 | 98 | /* TM holds the template for the insn were currently assembling. */ |
252b5132 RH |
99 | template tm; |
100 | ||
101 | /* SUFFIX holds the instruction mnemonic suffix if given. | |
102 | (e.g. 'l' for 'movl') */ | |
103 | char suffix; | |
104 | ||
47926f60 | 105 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
106 | unsigned int operands; |
107 | ||
108 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
109 | of given register, displacement, memory operands and immediate | |
47926f60 | 110 | operands. */ |
252b5132 RH |
111 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
112 | ||
113 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 114 | use OP[i] for the corresponding operand. */ |
252b5132 RH |
115 | unsigned int types[MAX_OPERANDS]; |
116 | ||
520dc8e8 AM |
117 | /* Displacement expression, immediate expression, or register for each |
118 | operand. */ | |
119 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 120 | |
3e73aa7c JH |
121 | /* Flags for operands. */ |
122 | unsigned int flags[MAX_OPERANDS]; | |
123 | #define Operand_PCrel 1 | |
124 | ||
252b5132 | 125 | /* Relocation type for operand */ |
f3c180ae | 126 | RELOC_ENUM reloc[MAX_OPERANDS]; |
252b5132 | 127 | |
252b5132 RH |
128 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
129 | the base index byte below. */ | |
130 | const reg_entry *base_reg; | |
131 | const reg_entry *index_reg; | |
132 | unsigned int log2_scale_factor; | |
133 | ||
134 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 135 | explicit segment overrides are given. */ |
ce8a8b2f | 136 | const seg_entry *seg[2]; |
252b5132 RH |
137 | |
138 | /* PREFIX holds all the given prefix opcodes (usually null). | |
139 | PREFIXES is the number of prefix opcodes. */ | |
140 | unsigned int prefixes; | |
141 | unsigned char prefix[MAX_PREFIXES]; | |
142 | ||
143 | /* RM and SIB are the modrm byte and the sib byte where the | |
144 | addressing modes of this insn are encoded. */ | |
145 | ||
146 | modrm_byte rm; | |
3e73aa7c | 147 | rex_byte rex; |
252b5132 RH |
148 | sib_byte sib; |
149 | }; | |
150 | ||
151 | typedef struct _i386_insn i386_insn; | |
152 | ||
153 | /* List of chars besides those in app.c:symbol_chars that can start an | |
154 | operand. Used to prevent the scrubber eating vital white-space. */ | |
155 | #ifdef LEX_AT | |
156 | const char extra_symbol_chars[] = "*%-(@"; | |
157 | #else | |
158 | const char extra_symbol_chars[] = "*%-("; | |
159 | #endif | |
160 | ||
161 | /* This array holds the chars that always start a comment. If the | |
ce8a8b2f | 162 | pre-processor is disabled, these aren't very useful. */ |
5bae9b28 | 163 | #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD) && !defined(TE_NetBSD)) |
252b5132 RH |
164 | /* Putting '/' here makes it impossible to use the divide operator. |
165 | However, we need it for compatibility with SVR4 systems. */ | |
166 | const char comment_chars[] = "#/"; | |
167 | #define PREFIX_SEPARATOR '\\' | |
168 | #else | |
169 | const char comment_chars[] = "#"; | |
170 | #define PREFIX_SEPARATOR '/' | |
171 | #endif | |
172 | ||
173 | /* This array holds the chars that only start a comment at the beginning of | |
174 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
175 | .line and .file directives will appear in the pre-processed output. |
176 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 177 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
178 | #NO_APP at the beginning of its output. |
179 | Also note that comments started like this one will always work if | |
252b5132 | 180 | '/' isn't otherwise defined. */ |
5bae9b28 | 181 | #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD) && !defined(TE_NetBSD)) |
252b5132 RH |
182 | const char line_comment_chars[] = ""; |
183 | #else | |
184 | const char line_comment_chars[] = "/"; | |
185 | #endif | |
186 | ||
63a0b638 | 187 | const char line_separator_chars[] = ";"; |
252b5132 | 188 | |
ce8a8b2f AM |
189 | /* Chars that can be used to separate mant from exp in floating point |
190 | nums. */ | |
252b5132 RH |
191 | const char EXP_CHARS[] = "eE"; |
192 | ||
ce8a8b2f AM |
193 | /* Chars that mean this number is a floating point constant |
194 | As in 0f12.456 | |
195 | or 0d1.2345e12. */ | |
252b5132 RH |
196 | const char FLT_CHARS[] = "fFdDxX"; |
197 | ||
ce8a8b2f | 198 | /* Tables for lexical analysis. */ |
252b5132 RH |
199 | static char mnemonic_chars[256]; |
200 | static char register_chars[256]; | |
201 | static char operand_chars[256]; | |
202 | static char identifier_chars[256]; | |
203 | static char digit_chars[256]; | |
204 | ||
ce8a8b2f | 205 | /* Lexical macros. */ |
252b5132 RH |
206 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
207 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
208 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
209 | #define is_space_char(x) ((x) == ' ') | |
210 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
211 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
212 | ||
ce8a8b2f | 213 | /* All non-digit non-letter charcters that may occur in an operand. */ |
252b5132 RH |
214 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
215 | ||
216 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
217 | effect this we maintain a stack of saved characters that we've smashed | |
218 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 219 | assembler instruction). */ |
252b5132 | 220 | static char save_stack[32]; |
ce8a8b2f | 221 | static char *save_stack_p; |
252b5132 RH |
222 | #define END_STRING_AND_SAVE(s) \ |
223 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
224 | #define RESTORE_END_STRING(s) \ | |
225 | do { *(s) = *--save_stack_p; } while (0) | |
226 | ||
47926f60 | 227 | /* The instruction we're assembling. */ |
252b5132 RH |
228 | static i386_insn i; |
229 | ||
230 | /* Possible templates for current insn. */ | |
231 | static const templates *current_templates; | |
232 | ||
47926f60 | 233 | /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */ |
252b5132 RH |
234 | static expressionS disp_expressions[2], im_expressions[2]; |
235 | ||
47926f60 KH |
236 | /* Current operand we are working on. */ |
237 | static int this_operand; | |
252b5132 | 238 | |
3e73aa7c JH |
239 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
240 | these. */ | |
241 | ||
242 | enum flag_code { | |
243 | CODE_32BIT, | |
244 | CODE_16BIT, | |
245 | CODE_64BIT }; | |
f3c180ae | 246 | #define NUM_FLAG_CODE ((int) CODE_64BIT + 1) |
3e73aa7c JH |
247 | |
248 | static enum flag_code flag_code; | |
249 | static int use_rela_relocations = 0; | |
250 | ||
251 | /* The names used to print error messages. */ | |
b77a7acd | 252 | static const char *flag_code_names[] = |
3e73aa7c JH |
253 | { |
254 | "32", | |
255 | "16", | |
256 | "64" | |
257 | }; | |
252b5132 | 258 | |
47926f60 KH |
259 | /* 1 for intel syntax, |
260 | 0 if att syntax. */ | |
261 | static int intel_syntax = 0; | |
252b5132 | 262 | |
47926f60 KH |
263 | /* 1 if register prefix % not required. */ |
264 | static int allow_naked_reg = 0; | |
252b5132 | 265 | |
47926f60 KH |
266 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
267 | leave, push, and pop instructions so that gcc has the same stack | |
268 | frame as in 32 bit mode. */ | |
269 | static char stackop_size = '\0'; | |
eecb386c | 270 | |
47926f60 KH |
271 | /* Non-zero to quieten some warnings. */ |
272 | static int quiet_warnings = 0; | |
a38cf1db | 273 | |
47926f60 KH |
274 | /* CPU name. */ |
275 | static const char *cpu_arch_name = NULL; | |
a38cf1db | 276 | |
47926f60 | 277 | /* CPU feature flags. */ |
3e73aa7c | 278 | static unsigned int cpu_arch_flags = CpuUnknownFlags|CpuNo64; |
a38cf1db | 279 | |
fddf5b5b AM |
280 | /* If set, conditional jumps are not automatically promoted to handle |
281 | larger than a byte offset. */ | |
282 | static unsigned int no_cond_jump_promotion = 0; | |
283 | ||
252b5132 | 284 | /* Interface to relax_segment. |
fddf5b5b AM |
285 | There are 3 major relax states for 386 jump insns because the |
286 | different types of jumps add different sizes to frags when we're | |
287 | figuring out what sort of jump to choose to reach a given label. */ | |
252b5132 | 288 | |
47926f60 | 289 | /* Types. */ |
93c2a809 AM |
290 | #define UNCOND_JUMP 0 |
291 | #define COND_JUMP 1 | |
292 | #define COND_JUMP86 2 | |
fddf5b5b | 293 | |
47926f60 | 294 | /* Sizes. */ |
252b5132 RH |
295 | #define CODE16 1 |
296 | #define SMALL 0 | |
297 | #define SMALL16 (SMALL|CODE16) | |
298 | #define BIG 2 | |
299 | #define BIG16 (BIG|CODE16) | |
300 | ||
301 | #ifndef INLINE | |
302 | #ifdef __GNUC__ | |
303 | #define INLINE __inline__ | |
304 | #else | |
305 | #define INLINE | |
306 | #endif | |
307 | #endif | |
308 | ||
fddf5b5b AM |
309 | #define ENCODE_RELAX_STATE(type, size) \ |
310 | ((relax_substateT) (((type) << 2) | (size))) | |
311 | #define TYPE_FROM_RELAX_STATE(s) \ | |
312 | ((s) >> 2) | |
313 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
314 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
315 | |
316 | /* This table is used by relax_frag to promote short jumps to long | |
317 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
318 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
319 | don't allow a short jump in a 32 bit code segment to be promoted to | |
320 | a 16 bit offset jump because it's slower (requires data size | |
321 | prefix), and doesn't work, unless the destination is in the bottom | |
322 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
323 | ||
324 | const relax_typeS md_relax_table[] = | |
325 | { | |
24eab124 AM |
326 | /* The fields are: |
327 | 1) most positive reach of this state, | |
328 | 2) most negative reach of this state, | |
93c2a809 | 329 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 330 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 331 | |
fddf5b5b | 332 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
333 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
334 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
335 | /* dword jmp adds 4 bytes to frag: | |
336 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 337 | {0, 0, 4, 0}, |
93c2a809 AM |
338 | /* word jmp adds 2 byte2 to frag: |
339 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
340 | {0, 0, 2, 0}, |
341 | ||
93c2a809 AM |
342 | /* COND_JUMP states. */ |
343 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
344 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
345 | /* dword conditionals adds 5 bytes to frag: | |
346 | 1 extra opcode byte, 4 displacement bytes. */ | |
347 | {0, 0, 5, 0}, | |
fddf5b5b | 348 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
349 | 1 extra opcode byte, 2 displacement bytes. */ |
350 | {0, 0, 3, 0}, | |
351 | ||
352 | /* COND_JUMP86 states. */ | |
353 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
354 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
355 | /* dword conditionals adds 5 bytes to frag: | |
356 | 1 extra opcode byte, 4 displacement bytes. */ | |
357 | {0, 0, 5, 0}, | |
358 | /* word conditionals add 4 bytes to frag: | |
359 | 1 displacement byte and a 3 byte long branch insn. */ | |
360 | {0, 0, 4, 0} | |
252b5132 RH |
361 | }; |
362 | ||
e413e4e9 AM |
363 | static const arch_entry cpu_arch[] = { |
364 | {"i8086", Cpu086 }, | |
365 | {"i186", Cpu086|Cpu186 }, | |
366 | {"i286", Cpu086|Cpu186|Cpu286 }, | |
367 | {"i386", Cpu086|Cpu186|Cpu286|Cpu386 }, | |
368 | {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 }, | |
369 | {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX }, | |
370 | {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE }, | |
371 | {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX }, | |
372 | {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE }, | |
a167610d | 373 | {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2 }, |
3e73aa7c JH |
374 | {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow }, |
375 | {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|Cpu3dnow }, | |
a167610d | 376 | {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|Cpu3dnow|CpuSSE|CpuSSE2 }, |
e413e4e9 AM |
377 | {NULL, 0 } |
378 | }; | |
379 | ||
252b5132 RH |
380 | void |
381 | i386_align_code (fragP, count) | |
382 | fragS *fragP; | |
383 | int count; | |
384 | { | |
ce8a8b2f AM |
385 | /* Various efficient no-op patterns for aligning code labels. |
386 | Note: Don't try to assemble the instructions in the comments. | |
387 | 0L and 0w are not legal. */ | |
252b5132 RH |
388 | static const char f32_1[] = |
389 | {0x90}; /* nop */ | |
390 | static const char f32_2[] = | |
391 | {0x89,0xf6}; /* movl %esi,%esi */ | |
392 | static const char f32_3[] = | |
393 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
394 | static const char f32_4[] = | |
395 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
396 | static const char f32_5[] = | |
397 | {0x90, /* nop */ | |
398 | 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
399 | static const char f32_6[] = | |
400 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
401 | static const char f32_7[] = | |
402 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
403 | static const char f32_8[] = | |
404 | {0x90, /* nop */ | |
405 | 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
406 | static const char f32_9[] = | |
407 | {0x89,0xf6, /* movl %esi,%esi */ | |
408 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
409 | static const char f32_10[] = | |
410 | {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ | |
411 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
412 | static const char f32_11[] = | |
413 | {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ | |
414 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
415 | static const char f32_12[] = | |
416 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
417 | 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ | |
418 | static const char f32_13[] = | |
419 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
420 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
421 | static const char f32_14[] = | |
422 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ | |
423 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
424 | static const char f32_15[] = | |
425 | {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */ | |
426 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; | |
c3332e24 AM |
427 | static const char f16_3[] = |
428 | {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */ | |
252b5132 RH |
429 | static const char f16_4[] = |
430 | {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
431 | static const char f16_5[] = | |
432 | {0x90, /* nop */ | |
433 | 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
434 | static const char f16_6[] = | |
435 | {0x89,0xf6, /* mov %si,%si */ | |
436 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
437 | static const char f16_7[] = | |
438 | {0x8d,0x74,0x00, /* lea 0(%si),%si */ | |
439 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
440 | static const char f16_8[] = | |
441 | {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ | |
442 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
443 | static const char *const f32_patt[] = { | |
444 | f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, | |
445 | f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15 | |
446 | }; | |
447 | static const char *const f16_patt[] = { | |
c3332e24 | 448 | f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8, |
252b5132 RH |
449 | f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15 |
450 | }; | |
451 | ||
3e73aa7c JH |
452 | /* ??? We can't use these fillers for x86_64, since they often kills the |
453 | upper halves. Solve later. */ | |
454 | if (flag_code == CODE_64BIT) | |
455 | count = 1; | |
456 | ||
252b5132 RH |
457 | if (count > 0 && count <= 15) |
458 | { | |
3e73aa7c | 459 | if (flag_code == CODE_16BIT) |
252b5132 | 460 | { |
47926f60 KH |
461 | memcpy (fragP->fr_literal + fragP->fr_fix, |
462 | f16_patt[count - 1], count); | |
463 | if (count > 8) | |
464 | /* Adjust jump offset. */ | |
252b5132 RH |
465 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; |
466 | } | |
467 | else | |
47926f60 KH |
468 | memcpy (fragP->fr_literal + fragP->fr_fix, |
469 | f32_patt[count - 1], count); | |
252b5132 RH |
470 | fragP->fr_var = count; |
471 | } | |
472 | } | |
473 | ||
474 | static char *output_invalid PARAMS ((int c)); | |
475 | static int i386_operand PARAMS ((char *operand_string)); | |
476 | static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float)); | |
477 | static const reg_entry *parse_register PARAMS ((char *reg_string, | |
478 | char **end_op)); | |
479 | ||
480 | #ifndef I386COFF | |
481 | static void s_bss PARAMS ((int)); | |
482 | #endif | |
483 | ||
ce8a8b2f | 484 | symbolS *GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
252b5132 RH |
485 | |
486 | static INLINE unsigned int | |
487 | mode_from_disp_size (t) | |
488 | unsigned int t; | |
489 | { | |
3e73aa7c | 490 | return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0; |
252b5132 RH |
491 | } |
492 | ||
493 | static INLINE int | |
494 | fits_in_signed_byte (num) | |
847f7ad4 | 495 | offsetT num; |
252b5132 RH |
496 | { |
497 | return (num >= -128) && (num <= 127); | |
47926f60 | 498 | } |
252b5132 RH |
499 | |
500 | static INLINE int | |
501 | fits_in_unsigned_byte (num) | |
847f7ad4 | 502 | offsetT num; |
252b5132 RH |
503 | { |
504 | return (num & 0xff) == num; | |
47926f60 | 505 | } |
252b5132 RH |
506 | |
507 | static INLINE int | |
508 | fits_in_unsigned_word (num) | |
847f7ad4 | 509 | offsetT num; |
252b5132 RH |
510 | { |
511 | return (num & 0xffff) == num; | |
47926f60 | 512 | } |
252b5132 RH |
513 | |
514 | static INLINE int | |
515 | fits_in_signed_word (num) | |
847f7ad4 | 516 | offsetT num; |
252b5132 RH |
517 | { |
518 | return (-32768 <= num) && (num <= 32767); | |
47926f60 | 519 | } |
3e73aa7c JH |
520 | static INLINE int |
521 | fits_in_signed_long (num) | |
522 | offsetT num ATTRIBUTE_UNUSED; | |
523 | { | |
524 | #ifndef BFD64 | |
525 | return 1; | |
526 | #else | |
527 | return (!(((offsetT) -1 << 31) & num) | |
528 | || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31)); | |
529 | #endif | |
530 | } /* fits_in_signed_long() */ | |
531 | static INLINE int | |
532 | fits_in_unsigned_long (num) | |
533 | offsetT num ATTRIBUTE_UNUSED; | |
534 | { | |
535 | #ifndef BFD64 | |
536 | return 1; | |
537 | #else | |
538 | return (num & (((offsetT) 2 << 31) - 1)) == num; | |
539 | #endif | |
540 | } /* fits_in_unsigned_long() */ | |
252b5132 RH |
541 | |
542 | static int | |
543 | smallest_imm_type (num) | |
847f7ad4 | 544 | offsetT num; |
252b5132 | 545 | { |
a847613f | 546 | if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64)) |
e413e4e9 AM |
547 | { |
548 | /* This code is disabled on the 486 because all the Imm1 forms | |
549 | in the opcode table are slower on the i486. They're the | |
550 | versions with the implicitly specified single-position | |
551 | displacement, which has another syntax if you really want to | |
552 | use that form. */ | |
553 | if (num == 1) | |
3e73aa7c | 554 | return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64; |
e413e4e9 | 555 | } |
252b5132 | 556 | return (fits_in_signed_byte (num) |
3e73aa7c | 557 | ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64) |
252b5132 | 558 | : fits_in_unsigned_byte (num) |
3e73aa7c | 559 | ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64) |
252b5132 | 560 | : (fits_in_signed_word (num) || fits_in_unsigned_word (num)) |
3e73aa7c JH |
561 | ? (Imm16 | Imm32 | Imm32S | Imm64) |
562 | : fits_in_signed_long (num) | |
563 | ? (Imm32 | Imm32S | Imm64) | |
564 | : fits_in_unsigned_long (num) | |
565 | ? (Imm32 | Imm64) | |
566 | : Imm64); | |
47926f60 | 567 | } |
252b5132 | 568 | |
847f7ad4 AM |
569 | static offsetT |
570 | offset_in_range (val, size) | |
571 | offsetT val; | |
572 | int size; | |
573 | { | |
508866be | 574 | addressT mask; |
ba2adb93 | 575 | |
847f7ad4 AM |
576 | switch (size) |
577 | { | |
508866be L |
578 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
579 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 580 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
3e73aa7c JH |
581 | #ifdef BFD64 |
582 | case 8: mask = ((addressT) 2 << 63) - 1; break; | |
583 | #endif | |
47926f60 | 584 | default: abort (); |
847f7ad4 AM |
585 | } |
586 | ||
ba2adb93 | 587 | /* If BFD64, sign extend val. */ |
3e73aa7c JH |
588 | if (!use_rela_relocations) |
589 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) | |
590 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
ba2adb93 | 591 | |
47926f60 | 592 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
847f7ad4 AM |
593 | { |
594 | char buf1[40], buf2[40]; | |
595 | ||
596 | sprint_value (buf1, val); | |
597 | sprint_value (buf2, val & mask); | |
598 | as_warn (_("%s shortened to %s"), buf1, buf2); | |
599 | } | |
600 | return val & mask; | |
601 | } | |
602 | ||
252b5132 RH |
603 | /* Returns 0 if attempting to add a prefix where one from the same |
604 | class already exists, 1 if non rep/repne added, 2 if rep/repne | |
605 | added. */ | |
606 | static int | |
607 | add_prefix (prefix) | |
608 | unsigned int prefix; | |
609 | { | |
610 | int ret = 1; | |
611 | int q; | |
612 | ||
3e73aa7c JH |
613 | if (prefix >= 0x40 && prefix < 0x50 && flag_code == CODE_64BIT) |
614 | q = REX_PREFIX; | |
615 | else | |
616 | switch (prefix) | |
617 | { | |
618 | default: | |
619 | abort (); | |
620 | ||
621 | case CS_PREFIX_OPCODE: | |
622 | case DS_PREFIX_OPCODE: | |
623 | case ES_PREFIX_OPCODE: | |
624 | case FS_PREFIX_OPCODE: | |
625 | case GS_PREFIX_OPCODE: | |
626 | case SS_PREFIX_OPCODE: | |
627 | q = SEG_PREFIX; | |
628 | break; | |
252b5132 | 629 | |
3e73aa7c JH |
630 | case REPNE_PREFIX_OPCODE: |
631 | case REPE_PREFIX_OPCODE: | |
632 | ret = 2; | |
633 | /* fall thru */ | |
634 | case LOCK_PREFIX_OPCODE: | |
635 | q = LOCKREP_PREFIX; | |
636 | break; | |
252b5132 | 637 | |
3e73aa7c JH |
638 | case FWAIT_OPCODE: |
639 | q = WAIT_PREFIX; | |
640 | break; | |
252b5132 | 641 | |
3e73aa7c JH |
642 | case ADDR_PREFIX_OPCODE: |
643 | q = ADDR_PREFIX; | |
644 | break; | |
252b5132 | 645 | |
3e73aa7c JH |
646 | case DATA_PREFIX_OPCODE: |
647 | q = DATA_PREFIX; | |
648 | break; | |
649 | } | |
252b5132 RH |
650 | |
651 | if (i.prefix[q]) | |
652 | { | |
653 | as_bad (_("same type of prefix used twice")); | |
654 | return 0; | |
655 | } | |
656 | ||
657 | i.prefixes += 1; | |
658 | i.prefix[q] = prefix; | |
659 | return ret; | |
660 | } | |
661 | ||
662 | static void | |
3e73aa7c | 663 | set_code_flag (value) |
e5cb08ac | 664 | int value; |
eecb386c | 665 | { |
3e73aa7c JH |
666 | flag_code = value; |
667 | cpu_arch_flags &= ~(Cpu64 | CpuNo64); | |
668 | cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64); | |
669 | if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer)) | |
670 | { | |
671 | as_bad (_("64bit mode not supported on this CPU.")); | |
672 | } | |
673 | if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386)) | |
674 | { | |
675 | as_bad (_("32bit mode not supported on this CPU.")); | |
676 | } | |
eecb386c AM |
677 | stackop_size = '\0'; |
678 | } | |
679 | ||
680 | static void | |
3e73aa7c JH |
681 | set_16bit_gcc_code_flag (new_code_flag) |
682 | int new_code_flag; | |
252b5132 | 683 | { |
3e73aa7c JH |
684 | flag_code = new_code_flag; |
685 | cpu_arch_flags &= ~(Cpu64 | CpuNo64); | |
686 | cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64); | |
687 | stackop_size = 'l'; | |
252b5132 RH |
688 | } |
689 | ||
690 | static void | |
691 | set_intel_syntax (syntax_flag) | |
eecb386c | 692 | int syntax_flag; |
252b5132 RH |
693 | { |
694 | /* Find out if register prefixing is specified. */ | |
695 | int ask_naked_reg = 0; | |
696 | ||
697 | SKIP_WHITESPACE (); | |
698 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
699 | { | |
700 | char *string = input_line_pointer; | |
701 | int e = get_symbol_end (); | |
702 | ||
47926f60 | 703 | if (strcmp (string, "prefix") == 0) |
252b5132 | 704 | ask_naked_reg = 1; |
47926f60 | 705 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
706 | ask_naked_reg = -1; |
707 | else | |
d0b47220 | 708 | as_bad (_("bad argument to syntax directive.")); |
252b5132 RH |
709 | *input_line_pointer = e; |
710 | } | |
711 | demand_empty_rest_of_line (); | |
c3332e24 | 712 | |
252b5132 RH |
713 | intel_syntax = syntax_flag; |
714 | ||
715 | if (ask_naked_reg == 0) | |
716 | { | |
717 | #ifdef BFD_ASSEMBLER | |
718 | allow_naked_reg = (intel_syntax | |
24eab124 | 719 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); |
252b5132 | 720 | #else |
47926f60 KH |
721 | /* Conservative default. */ |
722 | allow_naked_reg = 0; | |
252b5132 RH |
723 | #endif |
724 | } | |
725 | else | |
726 | allow_naked_reg = (ask_naked_reg < 0); | |
727 | } | |
728 | ||
e413e4e9 AM |
729 | static void |
730 | set_cpu_arch (dummy) | |
47926f60 | 731 | int dummy ATTRIBUTE_UNUSED; |
e413e4e9 | 732 | { |
47926f60 | 733 | SKIP_WHITESPACE (); |
e413e4e9 AM |
734 | |
735 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
736 | { | |
737 | char *string = input_line_pointer; | |
738 | int e = get_symbol_end (); | |
739 | int i; | |
740 | ||
741 | for (i = 0; cpu_arch[i].name; i++) | |
742 | { | |
743 | if (strcmp (string, cpu_arch[i].name) == 0) | |
744 | { | |
745 | cpu_arch_name = cpu_arch[i].name; | |
fddf5b5b AM |
746 | cpu_arch_flags = (cpu_arch[i].flags |
747 | | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64)); | |
e413e4e9 AM |
748 | break; |
749 | } | |
750 | } | |
751 | if (!cpu_arch[i].name) | |
752 | as_bad (_("no such architecture: `%s'"), string); | |
753 | ||
754 | *input_line_pointer = e; | |
755 | } | |
756 | else | |
757 | as_bad (_("missing cpu architecture")); | |
758 | ||
fddf5b5b AM |
759 | no_cond_jump_promotion = 0; |
760 | if (*input_line_pointer == ',' | |
761 | && ! is_end_of_line[(unsigned char) input_line_pointer[1]]) | |
762 | { | |
763 | char *string = ++input_line_pointer; | |
764 | int e = get_symbol_end (); | |
765 | ||
766 | if (strcmp (string, "nojumps") == 0) | |
767 | no_cond_jump_promotion = 1; | |
768 | else if (strcmp (string, "jumps") == 0) | |
769 | ; | |
770 | else | |
771 | as_bad (_("no such architecture modifier: `%s'"), string); | |
772 | ||
773 | *input_line_pointer = e; | |
774 | } | |
775 | ||
e413e4e9 AM |
776 | demand_empty_rest_of_line (); |
777 | } | |
778 | ||
252b5132 RH |
779 | const pseudo_typeS md_pseudo_table[] = |
780 | { | |
252b5132 RH |
781 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) |
782 | {"align", s_align_bytes, 0}, | |
783 | #else | |
784 | {"align", s_align_ptwo, 0}, | |
e413e4e9 AM |
785 | #endif |
786 | {"arch", set_cpu_arch, 0}, | |
787 | #ifndef I386COFF | |
788 | {"bss", s_bss, 0}, | |
252b5132 RH |
789 | #endif |
790 | {"ffloat", float_cons, 'f'}, | |
791 | {"dfloat", float_cons, 'd'}, | |
792 | {"tfloat", float_cons, 'x'}, | |
793 | {"value", cons, 2}, | |
794 | {"noopt", s_ignore, 0}, | |
795 | {"optim", s_ignore, 0}, | |
3e73aa7c JH |
796 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, |
797 | {"code16", set_code_flag, CODE_16BIT}, | |
798 | {"code32", set_code_flag, CODE_32BIT}, | |
799 | {"code64", set_code_flag, CODE_64BIT}, | |
252b5132 RH |
800 | {"intel_syntax", set_intel_syntax, 1}, |
801 | {"att_syntax", set_intel_syntax, 0}, | |
316e2c05 RH |
802 | {"file", dwarf2_directive_file, 0}, |
803 | {"loc", dwarf2_directive_loc, 0}, | |
252b5132 RH |
804 | {0, 0, 0} |
805 | }; | |
806 | ||
47926f60 | 807 | /* For interface with expression (). */ |
252b5132 RH |
808 | extern char *input_line_pointer; |
809 | ||
47926f60 | 810 | /* Hash table for instruction mnemonic lookup. */ |
252b5132 | 811 | static struct hash_control *op_hash; |
47926f60 KH |
812 | |
813 | /* Hash table for register lookup. */ | |
252b5132 RH |
814 | static struct hash_control *reg_hash; |
815 | \f | |
b9d79e03 JH |
816 | #ifdef BFD_ASSEMBLER |
817 | unsigned long | |
818 | i386_mach () | |
819 | { | |
820 | if (!strcmp (default_arch, "x86_64")) | |
821 | return bfd_mach_x86_64; | |
822 | else if (!strcmp (default_arch, "i386")) | |
823 | return bfd_mach_i386_i386; | |
824 | else | |
825 | as_fatal (_("Unknown architecture")); | |
826 | } | |
827 | #endif | |
828 | \f | |
252b5132 RH |
829 | void |
830 | md_begin () | |
831 | { | |
832 | const char *hash_err; | |
833 | ||
47926f60 | 834 | /* Initialize op_hash hash table. */ |
252b5132 RH |
835 | op_hash = hash_new (); |
836 | ||
837 | { | |
838 | register const template *optab; | |
839 | register templates *core_optab; | |
840 | ||
47926f60 KH |
841 | /* Setup for loop. */ |
842 | optab = i386_optab; | |
252b5132 RH |
843 | core_optab = (templates *) xmalloc (sizeof (templates)); |
844 | core_optab->start = optab; | |
845 | ||
846 | while (1) | |
847 | { | |
848 | ++optab; | |
849 | if (optab->name == NULL | |
850 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
851 | { | |
852 | /* different name --> ship out current template list; | |
47926f60 | 853 | add to hash table; & begin anew. */ |
252b5132 RH |
854 | core_optab->end = optab; |
855 | hash_err = hash_insert (op_hash, | |
856 | (optab - 1)->name, | |
857 | (PTR) core_optab); | |
858 | if (hash_err) | |
859 | { | |
252b5132 RH |
860 | as_fatal (_("Internal Error: Can't hash %s: %s"), |
861 | (optab - 1)->name, | |
862 | hash_err); | |
863 | } | |
864 | if (optab->name == NULL) | |
865 | break; | |
866 | core_optab = (templates *) xmalloc (sizeof (templates)); | |
867 | core_optab->start = optab; | |
868 | } | |
869 | } | |
870 | } | |
871 | ||
47926f60 | 872 | /* Initialize reg_hash hash table. */ |
252b5132 RH |
873 | reg_hash = hash_new (); |
874 | { | |
875 | register const reg_entry *regtab; | |
876 | ||
877 | for (regtab = i386_regtab; | |
878 | regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]); | |
879 | regtab++) | |
880 | { | |
881 | hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab); | |
882 | if (hash_err) | |
3e73aa7c JH |
883 | as_fatal (_("Internal Error: Can't hash %s: %s"), |
884 | regtab->reg_name, | |
885 | hash_err); | |
252b5132 RH |
886 | } |
887 | } | |
888 | ||
47926f60 | 889 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 RH |
890 | { |
891 | register int c; | |
892 | register char *p; | |
893 | ||
894 | for (c = 0; c < 256; c++) | |
895 | { | |
3882b010 | 896 | if (ISDIGIT (c)) |
252b5132 RH |
897 | { |
898 | digit_chars[c] = c; | |
899 | mnemonic_chars[c] = c; | |
900 | register_chars[c] = c; | |
901 | operand_chars[c] = c; | |
902 | } | |
3882b010 | 903 | else if (ISLOWER (c)) |
252b5132 RH |
904 | { |
905 | mnemonic_chars[c] = c; | |
906 | register_chars[c] = c; | |
907 | operand_chars[c] = c; | |
908 | } | |
3882b010 | 909 | else if (ISUPPER (c)) |
252b5132 | 910 | { |
3882b010 | 911 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
912 | register_chars[c] = mnemonic_chars[c]; |
913 | operand_chars[c] = c; | |
914 | } | |
915 | ||
3882b010 | 916 | if (ISALPHA (c) || ISDIGIT (c)) |
252b5132 RH |
917 | identifier_chars[c] = c; |
918 | else if (c >= 128) | |
919 | { | |
920 | identifier_chars[c] = c; | |
921 | operand_chars[c] = c; | |
922 | } | |
923 | } | |
924 | ||
925 | #ifdef LEX_AT | |
926 | identifier_chars['@'] = '@'; | |
927 | #endif | |
252b5132 RH |
928 | digit_chars['-'] = '-'; |
929 | identifier_chars['_'] = '_'; | |
930 | identifier_chars['.'] = '.'; | |
931 | ||
932 | for (p = operand_special_chars; *p != '\0'; p++) | |
933 | operand_chars[(unsigned char) *p] = *p; | |
934 | } | |
935 | ||
936 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
937 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
938 | { | |
939 | record_alignment (text_section, 2); | |
940 | record_alignment (data_section, 2); | |
941 | record_alignment (bss_section, 2); | |
942 | } | |
943 | #endif | |
944 | } | |
945 | ||
946 | void | |
947 | i386_print_statistics (file) | |
948 | FILE *file; | |
949 | { | |
950 | hash_print_statistics (file, "i386 opcode", op_hash); | |
951 | hash_print_statistics (file, "i386 register", reg_hash); | |
952 | } | |
953 | \f | |
252b5132 RH |
954 | #ifdef DEBUG386 |
955 | ||
ce8a8b2f | 956 | /* Debugging routines for md_assemble. */ |
252b5132 RH |
957 | static void pi PARAMS ((char *, i386_insn *)); |
958 | static void pte PARAMS ((template *)); | |
959 | static void pt PARAMS ((unsigned int)); | |
960 | static void pe PARAMS ((expressionS *)); | |
961 | static void ps PARAMS ((symbolS *)); | |
962 | ||
963 | static void | |
964 | pi (line, x) | |
965 | char *line; | |
966 | i386_insn *x; | |
967 | { | |
09f131f2 | 968 | unsigned int i; |
252b5132 RH |
969 | |
970 | fprintf (stdout, "%s: template ", line); | |
971 | pte (&x->tm); | |
09f131f2 JH |
972 | fprintf (stdout, " address: base %s index %s scale %x\n", |
973 | x->base_reg ? x->base_reg->reg_name : "none", | |
974 | x->index_reg ? x->index_reg->reg_name : "none", | |
975 | x->log2_scale_factor); | |
976 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 977 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
978 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
979 | x->sib.base, x->sib.index, x->sib.scale); | |
980 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
981 | x->rex.mode64, x->rex.extX, x->rex.extY, x->rex.extZ); | |
252b5132 RH |
982 | for (i = 0; i < x->operands; i++) |
983 | { | |
984 | fprintf (stdout, " #%d: ", i + 1); | |
985 | pt (x->types[i]); | |
986 | fprintf (stdout, "\n"); | |
987 | if (x->types[i] | |
3f4438ab | 988 | & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM)) |
520dc8e8 | 989 | fprintf (stdout, "%s\n", x->op[i].regs->reg_name); |
252b5132 | 990 | if (x->types[i] & Imm) |
520dc8e8 | 991 | pe (x->op[i].imms); |
252b5132 | 992 | if (x->types[i] & Disp) |
520dc8e8 | 993 | pe (x->op[i].disps); |
252b5132 RH |
994 | } |
995 | } | |
996 | ||
997 | static void | |
998 | pte (t) | |
999 | template *t; | |
1000 | { | |
09f131f2 | 1001 | unsigned int i; |
252b5132 | 1002 | fprintf (stdout, " %d operands ", t->operands); |
47926f60 | 1003 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
1004 | if (t->extension_opcode != None) |
1005 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
1006 | if (t->opcode_modifier & D) | |
1007 | fprintf (stdout, "D"); | |
1008 | if (t->opcode_modifier & W) | |
1009 | fprintf (stdout, "W"); | |
1010 | fprintf (stdout, "\n"); | |
1011 | for (i = 0; i < t->operands; i++) | |
1012 | { | |
1013 | fprintf (stdout, " #%d type ", i + 1); | |
1014 | pt (t->operand_types[i]); | |
1015 | fprintf (stdout, "\n"); | |
1016 | } | |
1017 | } | |
1018 | ||
1019 | static void | |
1020 | pe (e) | |
1021 | expressionS *e; | |
1022 | { | |
24eab124 | 1023 | fprintf (stdout, " operation %d\n", e->X_op); |
b77ad1d4 AM |
1024 | fprintf (stdout, " add_number %ld (%lx)\n", |
1025 | (long) e->X_add_number, (long) e->X_add_number); | |
252b5132 RH |
1026 | if (e->X_add_symbol) |
1027 | { | |
1028 | fprintf (stdout, " add_symbol "); | |
1029 | ps (e->X_add_symbol); | |
1030 | fprintf (stdout, "\n"); | |
1031 | } | |
1032 | if (e->X_op_symbol) | |
1033 | { | |
1034 | fprintf (stdout, " op_symbol "); | |
1035 | ps (e->X_op_symbol); | |
1036 | fprintf (stdout, "\n"); | |
1037 | } | |
1038 | } | |
1039 | ||
1040 | static void | |
1041 | ps (s) | |
1042 | symbolS *s; | |
1043 | { | |
1044 | fprintf (stdout, "%s type %s%s", | |
1045 | S_GET_NAME (s), | |
1046 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
1047 | segment_name (S_GET_SEGMENT (s))); | |
1048 | } | |
1049 | ||
1050 | struct type_name | |
1051 | { | |
1052 | unsigned int mask; | |
1053 | char *tname; | |
1054 | } | |
1055 | ||
1056 | type_names[] = | |
1057 | { | |
1058 | { Reg8, "r8" }, | |
1059 | { Reg16, "r16" }, | |
1060 | { Reg32, "r32" }, | |
09f131f2 | 1061 | { Reg64, "r64" }, |
252b5132 RH |
1062 | { Imm8, "i8" }, |
1063 | { Imm8S, "i8s" }, | |
1064 | { Imm16, "i16" }, | |
1065 | { Imm32, "i32" }, | |
09f131f2 JH |
1066 | { Imm32S, "i32s" }, |
1067 | { Imm64, "i64" }, | |
252b5132 RH |
1068 | { Imm1, "i1" }, |
1069 | { BaseIndex, "BaseIndex" }, | |
1070 | { Disp8, "d8" }, | |
1071 | { Disp16, "d16" }, | |
1072 | { Disp32, "d32" }, | |
09f131f2 JH |
1073 | { Disp32S, "d32s" }, |
1074 | { Disp64, "d64" }, | |
252b5132 RH |
1075 | { InOutPortReg, "InOutPortReg" }, |
1076 | { ShiftCount, "ShiftCount" }, | |
1077 | { Control, "control reg" }, | |
1078 | { Test, "test reg" }, | |
1079 | { Debug, "debug reg" }, | |
1080 | { FloatReg, "FReg" }, | |
1081 | { FloatAcc, "FAcc" }, | |
1082 | { SReg2, "SReg2" }, | |
1083 | { SReg3, "SReg3" }, | |
1084 | { Acc, "Acc" }, | |
1085 | { JumpAbsolute, "Jump Absolute" }, | |
1086 | { RegMMX, "rMMX" }, | |
3f4438ab | 1087 | { RegXMM, "rXMM" }, |
252b5132 RH |
1088 | { EsSeg, "es" }, |
1089 | { 0, "" } | |
1090 | }; | |
1091 | ||
1092 | static void | |
1093 | pt (t) | |
1094 | unsigned int t; | |
1095 | { | |
1096 | register struct type_name *ty; | |
1097 | ||
09f131f2 JH |
1098 | for (ty = type_names; ty->mask; ty++) |
1099 | if (t & ty->mask) | |
1100 | fprintf (stdout, "%s, ", ty->tname); | |
252b5132 RH |
1101 | fflush (stdout); |
1102 | } | |
1103 | ||
1104 | #endif /* DEBUG386 */ | |
1105 | \f | |
1106 | int | |
1107 | tc_i386_force_relocation (fixp) | |
1108 | struct fix *fixp; | |
1109 | { | |
1110 | #ifdef BFD_ASSEMBLER | |
1111 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
1112 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
1113 | return 1; | |
1114 | return 0; | |
1115 | #else | |
ce8a8b2f | 1116 | /* For COFF. */ |
f6af82bd | 1117 | return fixp->fx_r_type == 7; |
252b5132 RH |
1118 | #endif |
1119 | } | |
1120 | ||
1121 | #ifdef BFD_ASSEMBLER | |
252b5132 RH |
1122 | |
1123 | static bfd_reloc_code_real_type | |
3e73aa7c | 1124 | reloc (size, pcrel, sign, other) |
252b5132 RH |
1125 | int size; |
1126 | int pcrel; | |
3e73aa7c | 1127 | int sign; |
252b5132 RH |
1128 | bfd_reloc_code_real_type other; |
1129 | { | |
47926f60 KH |
1130 | if (other != NO_RELOC) |
1131 | return other; | |
252b5132 RH |
1132 | |
1133 | if (pcrel) | |
1134 | { | |
3e73aa7c | 1135 | if (!sign) |
e5cb08ac | 1136 | as_bad (_("There are no unsigned pc-relative relocations")); |
252b5132 RH |
1137 | switch (size) |
1138 | { | |
1139 | case 1: return BFD_RELOC_8_PCREL; | |
1140 | case 2: return BFD_RELOC_16_PCREL; | |
1141 | case 4: return BFD_RELOC_32_PCREL; | |
1142 | } | |
d0b47220 | 1143 | as_bad (_("can not do %d byte pc-relative relocation"), size); |
252b5132 RH |
1144 | } |
1145 | else | |
1146 | { | |
3e73aa7c | 1147 | if (sign) |
e5cb08ac | 1148 | switch (size) |
3e73aa7c JH |
1149 | { |
1150 | case 4: return BFD_RELOC_X86_64_32S; | |
1151 | } | |
1152 | else | |
1153 | switch (size) | |
1154 | { | |
1155 | case 1: return BFD_RELOC_8; | |
1156 | case 2: return BFD_RELOC_16; | |
1157 | case 4: return BFD_RELOC_32; | |
1158 | case 8: return BFD_RELOC_64; | |
1159 | } | |
1160 | as_bad (_("can not do %s %d byte relocation"), | |
1161 | sign ? "signed" : "unsigned", size); | |
252b5132 RH |
1162 | } |
1163 | ||
bfb32b52 | 1164 | abort (); |
252b5132 RH |
1165 | return BFD_RELOC_NONE; |
1166 | } | |
1167 | ||
47926f60 KH |
1168 | /* Here we decide which fixups can be adjusted to make them relative to |
1169 | the beginning of the section instead of the symbol. Basically we need | |
1170 | to make sure that the dynamic relocations are done correctly, so in | |
1171 | some cases we force the original symbol to be used. */ | |
1172 | ||
252b5132 | 1173 | int |
c0c949c7 | 1174 | tc_i386_fix_adjustable (fixP) |
47926f60 | 1175 | fixS *fixP; |
252b5132 | 1176 | { |
6d249963 | 1177 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
79d292aa ILT |
1178 | /* Prevent all adjustments to global symbols, or else dynamic |
1179 | linking will not work correctly. */ | |
b98ef147 | 1180 | if (S_IS_EXTERNAL (fixP->fx_addsy) |
3bf057fa AS |
1181 | || S_IS_WEAK (fixP->fx_addsy) |
1182 | /* Don't adjust pc-relative references to merge sections in 64-bit | |
1183 | mode. */ | |
1184 | || (use_rela_relocations | |
1185 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 | |
1186 | && fixP->fx_pcrel)) | |
252b5132 RH |
1187 | return 0; |
1188 | #endif | |
ce8a8b2f | 1189 | /* adjust_reloc_syms doesn't know about the GOT. */ |
252b5132 RH |
1190 | if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF |
1191 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 | |
1192 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 | |
3e73aa7c JH |
1193 | || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 |
1194 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 | |
80b3ee89 | 1195 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
252b5132 RH |
1196 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
1197 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
1198 | return 0; | |
1199 | return 1; | |
1200 | } | |
1201 | #else | |
ec56dfb4 L |
1202 | #define reloc(SIZE,PCREL,SIGN,OTHER) 0 |
1203 | #define BFD_RELOC_16 0 | |
1204 | #define BFD_RELOC_32 0 | |
1205 | #define BFD_RELOC_16_PCREL 0 | |
1206 | #define BFD_RELOC_32_PCREL 0 | |
1207 | #define BFD_RELOC_386_PLT32 0 | |
1208 | #define BFD_RELOC_386_GOT32 0 | |
1209 | #define BFD_RELOC_386_GOTOFF 0 | |
1210 | #define BFD_RELOC_X86_64_PLT32 0 | |
1211 | #define BFD_RELOC_X86_64_GOT32 0 | |
1212 | #define BFD_RELOC_X86_64_GOTPCREL 0 | |
252b5132 RH |
1213 | #endif |
1214 | ||
47926f60 | 1215 | static int intel_float_operand PARAMS ((char *mnemonic)); |
b4cac588 AM |
1216 | |
1217 | static int | |
252b5132 RH |
1218 | intel_float_operand (mnemonic) |
1219 | char *mnemonic; | |
1220 | { | |
47926f60 | 1221 | if (mnemonic[0] == 'f' && mnemonic[1] == 'i') |
cc5ca5ce | 1222 | return 2; |
252b5132 RH |
1223 | |
1224 | if (mnemonic[0] == 'f') | |
1225 | return 1; | |
1226 | ||
1227 | return 0; | |
1228 | } | |
1229 | ||
1230 | /* This is the guts of the machine-dependent assembler. LINE points to a | |
1231 | machine dependent instruction. This function is supposed to emit | |
1232 | the frags/bytes it assembles to. */ | |
1233 | ||
1234 | void | |
1235 | md_assemble (line) | |
1236 | char *line; | |
1237 | { | |
47926f60 | 1238 | /* Points to template once we've found it. */ |
252b5132 RH |
1239 | const template *t; |
1240 | ||
252b5132 RH |
1241 | int j; |
1242 | ||
1243 | char mnemonic[MAX_MNEM_SIZE]; | |
1244 | ||
47926f60 | 1245 | /* Initialize globals. */ |
252b5132 RH |
1246 | memset (&i, '\0', sizeof (i)); |
1247 | for (j = 0; j < MAX_OPERANDS; j++) | |
1ae12ab7 | 1248 | i.reloc[j] = NO_RELOC; |
252b5132 RH |
1249 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
1250 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 1251 | save_stack_p = save_stack; |
252b5132 RH |
1252 | |
1253 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
1254 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 1255 | start of a (possibly prefixed) mnemonic. */ |
252b5132 RH |
1256 | { |
1257 | char *l = line; | |
1258 | char *token_start = l; | |
1259 | char *mnem_p; | |
1260 | ||
47926f60 | 1261 | /* Non-zero if we found a prefix only acceptable with string insns. */ |
252b5132 RH |
1262 | const char *expecting_string_instruction = NULL; |
1263 | ||
1264 | while (1) | |
1265 | { | |
1266 | mnem_p = mnemonic; | |
1267 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
1268 | { | |
1269 | mnem_p++; | |
1270 | if (mnem_p >= mnemonic + sizeof (mnemonic)) | |
1271 | { | |
e413e4e9 | 1272 | as_bad (_("no such instruction: `%s'"), token_start); |
252b5132 RH |
1273 | return; |
1274 | } | |
1275 | l++; | |
1276 | } | |
1277 | if (!is_space_char (*l) | |
1278 | && *l != END_OF_INSN | |
5dd0794d AM |
1279 | && *l != PREFIX_SEPARATOR |
1280 | && *l != ',') | |
252b5132 RH |
1281 | { |
1282 | as_bad (_("invalid character %s in mnemonic"), | |
1283 | output_invalid (*l)); | |
1284 | return; | |
1285 | } | |
1286 | if (token_start == l) | |
1287 | { | |
1288 | if (*l == PREFIX_SEPARATOR) | |
1289 | as_bad (_("expecting prefix; got nothing")); | |
1290 | else | |
1291 | as_bad (_("expecting mnemonic; got nothing")); | |
1292 | return; | |
1293 | } | |
1294 | ||
1295 | /* Look up instruction (or prefix) via hash table. */ | |
1296 | current_templates = hash_find (op_hash, mnemonic); | |
1297 | ||
1298 | if (*l != END_OF_INSN | |
1299 | && (! is_space_char (*l) || l[1] != END_OF_INSN) | |
1300 | && current_templates | |
1301 | && (current_templates->start->opcode_modifier & IsPrefix)) | |
1302 | { | |
1303 | /* If we are in 16-bit mode, do not allow addr16 or data16. | |
1304 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
1305 | if ((current_templates->start->opcode_modifier & (Size16 | Size32)) | |
7ecd2f8b | 1306 | && flag_code != CODE_64BIT |
252b5132 | 1307 | && (((current_templates->start->opcode_modifier & Size32) != 0) |
3e73aa7c | 1308 | ^ (flag_code == CODE_16BIT))) |
252b5132 RH |
1309 | { |
1310 | as_bad (_("redundant %s prefix"), | |
1311 | current_templates->start->name); | |
1312 | return; | |
1313 | } | |
1314 | /* Add prefix, checking for repeated prefixes. */ | |
1315 | switch (add_prefix (current_templates->start->base_opcode)) | |
1316 | { | |
1317 | case 0: | |
1318 | return; | |
1319 | case 2: | |
47926f60 | 1320 | expecting_string_instruction = current_templates->start->name; |
252b5132 RH |
1321 | break; |
1322 | } | |
1323 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
1324 | token_start = ++l; | |
1325 | } | |
1326 | else | |
1327 | break; | |
1328 | } | |
1329 | ||
1330 | if (!current_templates) | |
1331 | { | |
24eab124 | 1332 | /* See if we can get a match by trimming off a suffix. */ |
252b5132 RH |
1333 | switch (mnem_p[-1]) |
1334 | { | |
252b5132 RH |
1335 | case WORD_MNEM_SUFFIX: |
1336 | case BYTE_MNEM_SUFFIX: | |
3e73aa7c | 1337 | case QWORD_MNEM_SUFFIX: |
252b5132 RH |
1338 | i.suffix = mnem_p[-1]; |
1339 | mnem_p[-1] = '\0'; | |
1340 | current_templates = hash_find (op_hash, mnemonic); | |
24eab124 | 1341 | break; |
f16b83df JH |
1342 | case SHORT_MNEM_SUFFIX: |
1343 | case LONG_MNEM_SUFFIX: | |
1344 | if (!intel_syntax) | |
1345 | { | |
1346 | i.suffix = mnem_p[-1]; | |
1347 | mnem_p[-1] = '\0'; | |
1348 | current_templates = hash_find (op_hash, mnemonic); | |
1349 | } | |
1350 | break; | |
24eab124 | 1351 | |
ce8a8b2f | 1352 | /* Intel Syntax. */ |
f16b83df | 1353 | case 'd': |
24eab124 AM |
1354 | if (intel_syntax) |
1355 | { | |
f16b83df JH |
1356 | if (intel_float_operand (mnemonic)) |
1357 | i.suffix = SHORT_MNEM_SUFFIX; | |
1358 | else | |
1359 | i.suffix = LONG_MNEM_SUFFIX; | |
24eab124 AM |
1360 | mnem_p[-1] = '\0'; |
1361 | current_templates = hash_find (op_hash, mnemonic); | |
24eab124 | 1362 | } |
f16b83df | 1363 | break; |
252b5132 RH |
1364 | } |
1365 | if (!current_templates) | |
1366 | { | |
e413e4e9 | 1367 | as_bad (_("no such instruction: `%s'"), token_start); |
252b5132 RH |
1368 | return; |
1369 | } | |
1370 | } | |
1371 | ||
5dd0794d AM |
1372 | if (current_templates->start->opcode_modifier & (Jump | JumpByte)) |
1373 | { | |
1374 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
1375 | predict taken and predict not taken respectively. | |
1376 | I'm not sure that branch hints actually do anything on loop | |
1377 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
1378 | may work in the future and it doesn't hurt to accept them | |
1379 | now. */ | |
1380 | if (l[0] == ',' && l[1] == 'p') | |
1381 | { | |
1382 | if (l[2] == 't') | |
1383 | { | |
1384 | if (! add_prefix (DS_PREFIX_OPCODE)) | |
1385 | return; | |
1386 | l += 3; | |
1387 | } | |
1388 | else if (l[2] == 'n') | |
1389 | { | |
1390 | if (! add_prefix (CS_PREFIX_OPCODE)) | |
1391 | return; | |
1392 | l += 3; | |
1393 | } | |
1394 | } | |
1395 | } | |
1396 | /* Any other comma loses. */ | |
1397 | if (*l == ',') | |
1398 | { | |
1399 | as_bad (_("invalid character %s in mnemonic"), | |
1400 | output_invalid (*l)); | |
1401 | return; | |
1402 | } | |
1403 | ||
e413e4e9 | 1404 | /* Check if instruction is supported on specified architecture. */ |
a847613f AM |
1405 | if ((current_templates->start->cpu_flags & ~(Cpu64 | CpuNo64)) |
1406 | & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))) | |
e413e4e9 | 1407 | { |
a847613f AM |
1408 | as_warn (_("`%s' is not supported on `%s'"), |
1409 | current_templates->start->name, cpu_arch_name); | |
1410 | } | |
1411 | else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT)) | |
1412 | { | |
1413 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
e413e4e9 AM |
1414 | } |
1415 | ||
ce8a8b2f | 1416 | /* Check for rep/repne without a string instruction. */ |
252b5132 RH |
1417 | if (expecting_string_instruction |
1418 | && !(current_templates->start->opcode_modifier & IsString)) | |
1419 | { | |
1420 | as_bad (_("expecting string instruction after `%s'"), | |
1421 | expecting_string_instruction); | |
1422 | return; | |
1423 | } | |
1424 | ||
47926f60 | 1425 | /* There may be operands to parse. */ |
252b5132 RH |
1426 | if (*l != END_OF_INSN) |
1427 | { | |
47926f60 | 1428 | /* 1 if operand is pending after ','. */ |
252b5132 RH |
1429 | unsigned int expecting_operand = 0; |
1430 | ||
47926f60 | 1431 | /* Non-zero if operand parens not balanced. */ |
252b5132 RH |
1432 | unsigned int paren_not_balanced; |
1433 | ||
1434 | do | |
1435 | { | |
ce8a8b2f | 1436 | /* Skip optional white space before operand. */ |
252b5132 RH |
1437 | if (is_space_char (*l)) |
1438 | ++l; | |
1439 | if (!is_operand_char (*l) && *l != END_OF_INSN) | |
1440 | { | |
1441 | as_bad (_("invalid character %s before operand %d"), | |
1442 | output_invalid (*l), | |
1443 | i.operands + 1); | |
1444 | return; | |
1445 | } | |
1446 | token_start = l; /* after white space */ | |
1447 | paren_not_balanced = 0; | |
1448 | while (paren_not_balanced || *l != ',') | |
1449 | { | |
1450 | if (*l == END_OF_INSN) | |
1451 | { | |
1452 | if (paren_not_balanced) | |
1453 | { | |
24eab124 | 1454 | if (!intel_syntax) |
252b5132 RH |
1455 | as_bad (_("unbalanced parenthesis in operand %d."), |
1456 | i.operands + 1); | |
24eab124 | 1457 | else |
252b5132 RH |
1458 | as_bad (_("unbalanced brackets in operand %d."), |
1459 | i.operands + 1); | |
1460 | return; | |
1461 | } | |
1462 | else | |
1463 | break; /* we are done */ | |
1464 | } | |
1465 | else if (!is_operand_char (*l) && !is_space_char (*l)) | |
1466 | { | |
1467 | as_bad (_("invalid character %s in operand %d"), | |
1468 | output_invalid (*l), | |
1469 | i.operands + 1); | |
1470 | return; | |
1471 | } | |
24eab124 AM |
1472 | if (!intel_syntax) |
1473 | { | |
252b5132 RH |
1474 | if (*l == '(') |
1475 | ++paren_not_balanced; | |
1476 | if (*l == ')') | |
1477 | --paren_not_balanced; | |
24eab124 AM |
1478 | } |
1479 | else | |
1480 | { | |
252b5132 RH |
1481 | if (*l == '[') |
1482 | ++paren_not_balanced; | |
1483 | if (*l == ']') | |
1484 | --paren_not_balanced; | |
24eab124 | 1485 | } |
252b5132 RH |
1486 | l++; |
1487 | } | |
1488 | if (l != token_start) | |
47926f60 | 1489 | { /* Yes, we've read in another operand. */ |
252b5132 RH |
1490 | unsigned int operand_ok; |
1491 | this_operand = i.operands++; | |
1492 | if (i.operands > MAX_OPERANDS) | |
1493 | { | |
1494 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
1495 | MAX_OPERANDS); | |
1496 | return; | |
1497 | } | |
47926f60 | 1498 | /* Now parse operand adding info to 'i' as we go along. */ |
252b5132 RH |
1499 | END_STRING_AND_SAVE (l); |
1500 | ||
24eab124 | 1501 | if (intel_syntax) |
47926f60 KH |
1502 | operand_ok = |
1503 | i386_intel_operand (token_start, | |
1504 | intel_float_operand (mnemonic)); | |
24eab124 AM |
1505 | else |
1506 | operand_ok = i386_operand (token_start); | |
252b5132 | 1507 | |
ce8a8b2f | 1508 | RESTORE_END_STRING (l); |
252b5132 RH |
1509 | if (!operand_ok) |
1510 | return; | |
1511 | } | |
1512 | else | |
1513 | { | |
1514 | if (expecting_operand) | |
1515 | { | |
1516 | expecting_operand_after_comma: | |
1517 | as_bad (_("expecting operand after ','; got nothing")); | |
1518 | return; | |
1519 | } | |
1520 | if (*l == ',') | |
1521 | { | |
1522 | as_bad (_("expecting operand before ','; got nothing")); | |
1523 | return; | |
1524 | } | |
1525 | } | |
1526 | ||
ce8a8b2f | 1527 | /* Now *l must be either ',' or END_OF_INSN. */ |
252b5132 RH |
1528 | if (*l == ',') |
1529 | { | |
1530 | if (*++l == END_OF_INSN) | |
ce8a8b2f AM |
1531 | { |
1532 | /* Just skip it, if it's \n complain. */ | |
252b5132 RH |
1533 | goto expecting_operand_after_comma; |
1534 | } | |
1535 | expecting_operand = 1; | |
1536 | } | |
1537 | } | |
ce8a8b2f | 1538 | while (*l != END_OF_INSN); |
252b5132 RH |
1539 | } |
1540 | } | |
1541 | ||
1542 | /* Now we've parsed the mnemonic into a set of templates, and have the | |
1543 | operands at hand. | |
1544 | ||
1545 | Next, we find a template that matches the given insn, | |
1546 | making sure the overlap of the given operands types is consistent | |
47926f60 | 1547 | with the template operand types. */ |
252b5132 RH |
1548 | |
1549 | #define MATCH(overlap, given, template) \ | |
3138f287 AM |
1550 | ((overlap & ~JumpAbsolute) \ |
1551 | && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute))) | |
252b5132 RH |
1552 | |
1553 | /* If given types r0 and r1 are registers they must be of the same type | |
1554 | unless the expected operand type register overlap is null. | |
1555 | Note that Acc in a template matches every size of reg. */ | |
1556 | #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \ | |
1557 | ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \ | |
1558 | ((g0) & Reg) == ((g1) & Reg) || \ | |
1559 | ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 ) | |
1560 | ||
1561 | { | |
1562 | register unsigned int overlap0, overlap1; | |
252b5132 RH |
1563 | unsigned int overlap2; |
1564 | unsigned int found_reverse_match; | |
1565 | int suffix_check; | |
1566 | ||
cc5ca5ce AM |
1567 | /* All intel opcodes have reversed operands except for "bound" and |
1568 | "enter". We also don't reverse intersegment "jmp" and "call" | |
1569 | instructions with 2 immediate operands so that the immediate segment | |
1570 | precedes the offset, as it does when in AT&T mode. "enter" and the | |
1571 | intersegment "jmp" and "call" instructions are the only ones that | |
1572 | have two immediate operands. */ | |
520dc8e8 | 1573 | if (intel_syntax && i.operands > 1 |
cc5ca5ce AM |
1574 | && (strcmp (mnemonic, "bound") != 0) |
1575 | && !((i.types[0] & Imm) && (i.types[1] & Imm))) | |
252b5132 | 1576 | { |
520dc8e8 | 1577 | union i386_op temp_op; |
24eab124 | 1578 | unsigned int temp_type; |
f3c180ae | 1579 | RELOC_ENUM temp_reloc; |
24eab124 | 1580 | int xchg1 = 0; |
ab9da554 | 1581 | int xchg2 = 0; |
252b5132 | 1582 | |
24eab124 AM |
1583 | if (i.operands == 2) |
1584 | { | |
1585 | xchg1 = 0; | |
1586 | xchg2 = 1; | |
1587 | } | |
1588 | else if (i.operands == 3) | |
1589 | { | |
1590 | xchg1 = 0; | |
1591 | xchg2 = 2; | |
1592 | } | |
520dc8e8 AM |
1593 | temp_type = i.types[xchg2]; |
1594 | i.types[xchg2] = i.types[xchg1]; | |
1595 | i.types[xchg1] = temp_type; | |
1596 | temp_op = i.op[xchg2]; | |
1597 | i.op[xchg2] = i.op[xchg1]; | |
1598 | i.op[xchg1] = temp_op; | |
1ae12ab7 AM |
1599 | temp_reloc = i.reloc[xchg2]; |
1600 | i.reloc[xchg2] = i.reloc[xchg1]; | |
1601 | i.reloc[xchg1] = temp_reloc; | |
36bf8ab9 AM |
1602 | |
1603 | if (i.mem_operands == 2) | |
1604 | { | |
1605 | const seg_entry *temp_seg; | |
1606 | temp_seg = i.seg[0]; | |
1607 | i.seg[0] = i.seg[1]; | |
1608 | i.seg[1] = temp_seg; | |
1609 | } | |
24eab124 | 1610 | } |
773f551c AM |
1611 | |
1612 | if (i.imm_operands) | |
1613 | { | |
1614 | /* Try to ensure constant immediates are represented in the smallest | |
1615 | opcode possible. */ | |
1616 | char guess_suffix = 0; | |
1617 | int op; | |
1618 | ||
1619 | if (i.suffix) | |
1620 | guess_suffix = i.suffix; | |
1621 | else if (i.reg_operands) | |
1622 | { | |
1623 | /* Figure out a suffix from the last register operand specified. | |
1624 | We can't do this properly yet, ie. excluding InOutPortReg, | |
1625 | but the following works for instructions with immediates. | |
1626 | In any case, we can't set i.suffix yet. */ | |
47926f60 | 1627 | for (op = i.operands; --op >= 0;) |
773f551c AM |
1628 | if (i.types[op] & Reg) |
1629 | { | |
1630 | if (i.types[op] & Reg8) | |
1631 | guess_suffix = BYTE_MNEM_SUFFIX; | |
1632 | else if (i.types[op] & Reg16) | |
1633 | guess_suffix = WORD_MNEM_SUFFIX; | |
3e73aa7c JH |
1634 | else if (i.types[op] & Reg32) |
1635 | guess_suffix = LONG_MNEM_SUFFIX; | |
1636 | else if (i.types[op] & Reg64) | |
1637 | guess_suffix = QWORD_MNEM_SUFFIX; | |
773f551c AM |
1638 | break; |
1639 | } | |
1640 | } | |
3e73aa7c | 1641 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
726c5dcd AM |
1642 | guess_suffix = WORD_MNEM_SUFFIX; |
1643 | ||
47926f60 | 1644 | for (op = i.operands; --op >= 0;) |
3e73aa7c | 1645 | if (i.types[op] & Imm) |
773f551c | 1646 | { |
3e73aa7c | 1647 | switch (i.op[op].imms->X_op) |
e5cb08ac | 1648 | { |
3e73aa7c JH |
1649 | case O_constant: |
1650 | /* If a suffix is given, this operand may be shortened. */ | |
1651 | switch (guess_suffix) | |
1652 | { | |
1653 | case LONG_MNEM_SUFFIX: | |
1654 | i.types[op] |= Imm32 | Imm64; | |
1655 | break; | |
1656 | case WORD_MNEM_SUFFIX: | |
1657 | i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64; | |
1658 | break; | |
1659 | case BYTE_MNEM_SUFFIX: | |
1660 | i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64; | |
1661 | break; | |
1662 | } | |
773f551c | 1663 | |
e5cb08ac KH |
1664 | /* If this operand is at most 16 bits, convert it |
1665 | to a signed 16 bit number before trying to see | |
1666 | whether it will fit in an even smaller size. | |
1667 | This allows a 16-bit operand such as $0xffe0 to | |
1668 | be recognised as within Imm8S range. */ | |
3e73aa7c | 1669 | if ((i.types[op] & Imm16) |
e5cb08ac | 1670 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) |
3e73aa7c JH |
1671 | { |
1672 | i.op[op].imms->X_add_number = | |
1673 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
1674 | } | |
1675 | if ((i.types[op] & Imm32) | |
1676 | && (i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) == 0) | |
1677 | { | |
1678 | i.op[op].imms->X_add_number = | |
1679 | (i.op[op].imms->X_add_number ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
1680 | } | |
1681 | i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number); | |
1682 | /* We must avoid matching of Imm32 templates when 64bit only immediate is available. */ | |
1683 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
1684 | i.types[op] &= ~Imm32; | |
1685 | break; | |
1686 | case O_absent: | |
1687 | case O_register: | |
bfb32b52 | 1688 | abort (); |
3e73aa7c JH |
1689 | /* Symbols and expressions. */ |
1690 | default: | |
1691 | /* Convert symbolic operand to proper sizes for matching. */ | |
1692 | switch (guess_suffix) | |
1693 | { | |
1694 | case QWORD_MNEM_SUFFIX: | |
1695 | i.types[op] = Imm64 | Imm32S; | |
1696 | break; | |
1697 | case LONG_MNEM_SUFFIX: | |
1698 | i.types[op] = Imm32 | Imm64; | |
1699 | break; | |
1700 | case WORD_MNEM_SUFFIX: | |
1701 | i.types[op] = Imm16 | Imm32 | Imm64; | |
1702 | break; | |
1703 | break; | |
1704 | case BYTE_MNEM_SUFFIX: | |
1705 | i.types[op] = Imm8 | Imm8S | Imm16 | Imm32S | Imm32; | |
1706 | break; | |
1707 | break; | |
1708 | } | |
1709 | break; | |
773f551c | 1710 | } |
773f551c AM |
1711 | } |
1712 | } | |
1713 | ||
45288df1 AM |
1714 | if (i.disp_operands) |
1715 | { | |
1716 | /* Try to use the smallest displacement type too. */ | |
1717 | int op; | |
1718 | ||
47926f60 | 1719 | for (op = i.operands; --op >= 0;) |
45288df1 | 1720 | if ((i.types[op] & Disp) |
1ae12ab7 | 1721 | && i.op[op].disps->X_op == O_constant) |
45288df1 AM |
1722 | { |
1723 | offsetT disp = i.op[op].disps->X_add_number; | |
1724 | ||
1725 | if (i.types[op] & Disp16) | |
1726 | { | |
1727 | /* We know this operand is at most 16 bits, so | |
1728 | convert to a signed 16 bit number before trying | |
1729 | to see whether it will fit in an even smaller | |
1730 | size. */ | |
47926f60 | 1731 | |
45288df1 AM |
1732 | disp = (((disp & 0xffff) ^ 0x8000) - 0x8000); |
1733 | } | |
3e73aa7c JH |
1734 | else if (i.types[op] & Disp32) |
1735 | { | |
1736 | /* We know this operand is at most 32 bits, so convert to a | |
1737 | signed 32 bit number before trying to see whether it will | |
1738 | fit in an even smaller size. */ | |
1739 | disp &= (((offsetT) 2 << 31) - 1); | |
1740 | disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
1741 | } | |
1742 | if (flag_code == CODE_64BIT) | |
1743 | { | |
1744 | if (fits_in_signed_long (disp)) | |
1745 | i.types[op] |= Disp32S; | |
1746 | if (fits_in_unsigned_long (disp)) | |
1747 | i.types[op] |= Disp32; | |
1748 | } | |
1749 | if ((i.types[op] & (Disp32 | Disp32S | Disp16)) | |
1750 | && fits_in_signed_byte (disp)) | |
45288df1 AM |
1751 | i.types[op] |= Disp8; |
1752 | } | |
1753 | } | |
1754 | ||
252b5132 RH |
1755 | overlap0 = 0; |
1756 | overlap1 = 0; | |
1757 | overlap2 = 0; | |
1758 | found_reverse_match = 0; | |
1759 | suffix_check = (i.suffix == BYTE_MNEM_SUFFIX | |
1760 | ? No_bSuf | |
1761 | : (i.suffix == WORD_MNEM_SUFFIX | |
1762 | ? No_wSuf | |
1763 | : (i.suffix == SHORT_MNEM_SUFFIX | |
1764 | ? No_sSuf | |
1765 | : (i.suffix == LONG_MNEM_SUFFIX | |
24eab124 | 1766 | ? No_lSuf |
3e73aa7c JH |
1767 | : (i.suffix == QWORD_MNEM_SUFFIX |
1768 | ? No_qSuf | |
1769 | : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX ? No_xSuf : 0)))))); | |
252b5132 RH |
1770 | |
1771 | for (t = current_templates->start; | |
1772 | t < current_templates->end; | |
1773 | t++) | |
1774 | { | |
47926f60 | 1775 | /* Must have right number of operands. */ |
252b5132 RH |
1776 | if (i.operands != t->operands) |
1777 | continue; | |
1778 | ||
7f3f1ea2 AM |
1779 | /* Check the suffix, except for some instructions in intel mode. */ |
1780 | if ((t->opcode_modifier & suffix_check) | |
fa2255cb DN |
1781 | && !(intel_syntax |
1782 | && (t->opcode_modifier & IgnoreSize)) | |
7f3f1ea2 AM |
1783 | && !(intel_syntax |
1784 | && t->base_opcode == 0xd9 | |
ce8a8b2f AM |
1785 | && (t->extension_opcode == 5 /* 0xd9,5 "fldcw" */ |
1786 | || t->extension_opcode == 7))) /* 0xd9,7 "f{n}stcw" */ | |
24eab124 | 1787 | continue; |
252b5132 | 1788 | |
e2914f48 | 1789 | /* Do not verify operands when there are none. */ |
252b5132 | 1790 | else if (!t->operands) |
e2914f48 JH |
1791 | { |
1792 | if (t->cpu_flags & ~cpu_arch_flags) | |
1793 | continue; | |
1794 | /* We've found a match; break out of loop. */ | |
1795 | break; | |
e5cb08ac | 1796 | } |
252b5132 RH |
1797 | |
1798 | overlap0 = i.types[0] & t->operand_types[0]; | |
1799 | switch (t->operands) | |
1800 | { | |
1801 | case 1: | |
1802 | if (!MATCH (overlap0, i.types[0], t->operand_types[0])) | |
1803 | continue; | |
1804 | break; | |
1805 | case 2: | |
1806 | case 3: | |
1807 | overlap1 = i.types[1] & t->operand_types[1]; | |
1808 | if (!MATCH (overlap0, i.types[0], t->operand_types[0]) | |
1809 | || !MATCH (overlap1, i.types[1], t->operand_types[1]) | |
1810 | || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], | |
1811 | t->operand_types[0], | |
1812 | overlap1, i.types[1], | |
1813 | t->operand_types[1])) | |
1814 | { | |
47926f60 | 1815 | /* Check if other direction is valid ... */ |
252b5132 RH |
1816 | if ((t->opcode_modifier & (D|FloatD)) == 0) |
1817 | continue; | |
1818 | ||
47926f60 | 1819 | /* Try reversing direction of operands. */ |
252b5132 RH |
1820 | overlap0 = i.types[0] & t->operand_types[1]; |
1821 | overlap1 = i.types[1] & t->operand_types[0]; | |
1822 | if (!MATCH (overlap0, i.types[0], t->operand_types[1]) | |
1823 | || !MATCH (overlap1, i.types[1], t->operand_types[0]) | |
1824 | || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], | |
1825 | t->operand_types[1], | |
1826 | overlap1, i.types[1], | |
1827 | t->operand_types[0])) | |
1828 | { | |
47926f60 | 1829 | /* Does not match either direction. */ |
252b5132 RH |
1830 | continue; |
1831 | } | |
1832 | /* found_reverse_match holds which of D or FloatDR | |
1833 | we've found. */ | |
1834 | found_reverse_match = t->opcode_modifier & (D|FloatDR); | |
252b5132 | 1835 | } |
47926f60 | 1836 | /* Found a forward 2 operand match here. */ |
3e73aa7c | 1837 | else if (t->operands == 3) |
252b5132 RH |
1838 | { |
1839 | /* Here we make use of the fact that there are no | |
1840 | reverse match 3 operand instructions, and all 3 | |
1841 | operand instructions only need to be checked for | |
1842 | register consistency between operands 2 and 3. */ | |
1843 | overlap2 = i.types[2] & t->operand_types[2]; | |
1844 | if (!MATCH (overlap2, i.types[2], t->operand_types[2]) | |
1845 | || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1], | |
1846 | t->operand_types[1], | |
1847 | overlap2, i.types[2], | |
24eab124 | 1848 | t->operand_types[2])) |
252b5132 | 1849 | |
24eab124 | 1850 | continue; |
252b5132 | 1851 | } |
47926f60 | 1852 | /* Found either forward/reverse 2 or 3 operand match here: |
ce8a8b2f | 1853 | slip through to break. */ |
252b5132 | 1854 | } |
3e73aa7c JH |
1855 | if (t->cpu_flags & ~cpu_arch_flags) |
1856 | { | |
1857 | found_reverse_match = 0; | |
1858 | continue; | |
1859 | } | |
47926f60 KH |
1860 | /* We've found a match; break out of loop. */ |
1861 | break; | |
ce8a8b2f | 1862 | } |
252b5132 | 1863 | if (t == current_templates->end) |
47926f60 KH |
1864 | { |
1865 | /* We found no match. */ | |
252b5132 RH |
1866 | as_bad (_("suffix or operands invalid for `%s'"), |
1867 | current_templates->start->name); | |
1868 | return; | |
1869 | } | |
1870 | ||
a38cf1db | 1871 | if (!quiet_warnings) |
3138f287 | 1872 | { |
a38cf1db AM |
1873 | if (!intel_syntax |
1874 | && ((i.types[0] & JumpAbsolute) | |
1875 | != (t->operand_types[0] & JumpAbsolute))) | |
1876 | { | |
1877 | as_warn (_("indirect %s without `*'"), t->name); | |
1878 | } | |
3138f287 | 1879 | |
a38cf1db AM |
1880 | if ((t->opcode_modifier & (IsPrefix|IgnoreSize)) |
1881 | == (IsPrefix|IgnoreSize)) | |
1882 | { | |
1883 | /* Warn them that a data or address size prefix doesn't | |
1884 | affect assembly of the next line of code. */ | |
1885 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
1886 | } | |
252b5132 RH |
1887 | } |
1888 | ||
1889 | /* Copy the template we found. */ | |
1890 | i.tm = *t; | |
1891 | if (found_reverse_match) | |
1892 | { | |
7f3f1ea2 AM |
1893 | /* If we found a reverse match we must alter the opcode |
1894 | direction bit. found_reverse_match holds bits to change | |
1895 | (different for int & float insns). */ | |
1896 | ||
1897 | i.tm.base_opcode ^= found_reverse_match; | |
1898 | ||
252b5132 RH |
1899 | i.tm.operand_types[0] = t->operand_types[1]; |
1900 | i.tm.operand_types[1] = t->operand_types[0]; | |
1901 | } | |
1902 | ||
d0b47220 | 1903 | /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */ |
e5cb08ac KH |
1904 | if (SYSV386_COMPAT |
1905 | && intel_syntax | |
1906 | && (i.tm.base_opcode & 0xfffffde0) == 0xdce0) | |
1907 | i.tm.base_opcode ^= FloatR; | |
252b5132 RH |
1908 | |
1909 | if (i.tm.opcode_modifier & FWait) | |
1910 | if (! add_prefix (FWAIT_OPCODE)) | |
1911 | return; | |
1912 | ||
ce8a8b2f | 1913 | /* Check string instruction segment overrides. */ |
252b5132 RH |
1914 | if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0) |
1915 | { | |
1916 | int mem_op = (i.types[0] & AnyMem) ? 0 : 1; | |
1917 | if ((i.tm.operand_types[mem_op] & EsSeg) != 0) | |
1918 | { | |
1919 | if (i.seg[0] != NULL && i.seg[0] != &es) | |
1920 | { | |
1921 | as_bad (_("`%s' operand %d must use `%%es' segment"), | |
1922 | i.tm.name, | |
1923 | mem_op + 1); | |
1924 | return; | |
1925 | } | |
1926 | /* There's only ever one segment override allowed per instruction. | |
1927 | This instruction possibly has a legal segment override on the | |
1928 | second operand, so copy the segment to where non-string | |
1929 | instructions store it, allowing common code. */ | |
1930 | i.seg[0] = i.seg[1]; | |
1931 | } | |
1932 | else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0) | |
1933 | { | |
1934 | if (i.seg[1] != NULL && i.seg[1] != &es) | |
1935 | { | |
1936 | as_bad (_("`%s' operand %d must use `%%es' segment"), | |
1937 | i.tm.name, | |
1938 | mem_op + 2); | |
1939 | return; | |
1940 | } | |
1941 | } | |
1942 | } | |
1943 | ||
1944 | /* If matched instruction specifies an explicit instruction mnemonic | |
1945 | suffix, use it. */ | |
3e73aa7c | 1946 | if (i.tm.opcode_modifier & (Size16 | Size32 | Size64)) |
252b5132 RH |
1947 | { |
1948 | if (i.tm.opcode_modifier & Size16) | |
1949 | i.suffix = WORD_MNEM_SUFFIX; | |
3e73aa7c JH |
1950 | else if (i.tm.opcode_modifier & Size64) |
1951 | i.suffix = QWORD_MNEM_SUFFIX; | |
252b5132 | 1952 | else |
add0c677 | 1953 | i.suffix = LONG_MNEM_SUFFIX; |
252b5132 RH |
1954 | } |
1955 | else if (i.reg_operands) | |
1956 | { | |
1957 | /* If there's no instruction mnemonic suffix we try to invent one | |
47926f60 | 1958 | based on register operands. */ |
252b5132 RH |
1959 | if (!i.suffix) |
1960 | { | |
1961 | /* We take i.suffix from the last register operand specified, | |
1962 | Destination register type is more significant than source | |
1963 | register type. */ | |
1964 | int op; | |
47926f60 | 1965 | for (op = i.operands; --op >= 0;) |
cc5ca5ce AM |
1966 | if ((i.types[op] & Reg) |
1967 | && !(i.tm.operand_types[op] & InOutPortReg)) | |
252b5132 RH |
1968 | { |
1969 | i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX : | |
1970 | (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX : | |
3e73aa7c | 1971 | (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX : |
add0c677 | 1972 | LONG_MNEM_SUFFIX); |
252b5132 RH |
1973 | break; |
1974 | } | |
1975 | } | |
1976 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
1977 | { | |
1978 | int op; | |
47926f60 | 1979 | for (op = i.operands; --op >= 0;) |
252b5132 RH |
1980 | { |
1981 | /* If this is an eight bit register, it's OK. If it's | |
1982 | the 16 or 32 bit version of an eight bit register, | |
47926f60 | 1983 | we will just use the low portion, and that's OK too. */ |
252b5132 RH |
1984 | if (i.types[op] & Reg8) |
1985 | continue; | |
1986 | ||
47926f60 | 1987 | /* movzx and movsx should not generate this warning. */ |
24eab124 AM |
1988 | if (intel_syntax |
1989 | && (i.tm.base_opcode == 0xfb7 | |
1990 | || i.tm.base_opcode == 0xfb6 | |
3e73aa7c | 1991 | || i.tm.base_opcode == 0x63 |
24eab124 AM |
1992 | || i.tm.base_opcode == 0xfbe |
1993 | || i.tm.base_opcode == 0xfbf)) | |
1994 | continue; | |
252b5132 | 1995 | |
520dc8e8 | 1996 | if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4 |
252b5132 RH |
1997 | #if 0 |
1998 | /* Check that the template allows eight bit regs | |
1999 | This kills insns such as `orb $1,%edx', which | |
2000 | maybe should be allowed. */ | |
2001 | && (i.tm.operand_types[op] & (Reg8|InOutPortReg)) | |
2002 | #endif | |
2003 | ) | |
2004 | { | |
3e73aa7c JH |
2005 | /* Prohibit these changes in the 64bit mode, since |
2006 | the lowering is more complicated. */ | |
2007 | if (flag_code == CODE_64BIT | |
2008 | && (i.tm.operand_types[op] & InOutPortReg) == 0) | |
2009 | as_bad (_("Incorrect register `%%%s' used with`%c' suffix"), | |
2010 | i.op[op].regs->reg_name, | |
2011 | i.suffix); | |
252b5132 | 2012 | #if REGISTER_WARNINGS |
a38cf1db AM |
2013 | if (!quiet_warnings |
2014 | && (i.tm.operand_types[op] & InOutPortReg) == 0) | |
252b5132 | 2015 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), |
2e98d2de AM |
2016 | (i.op[op].regs |
2017 | + (i.types[op] & Reg16 | |
2018 | ? REGNAM_AL - REGNAM_AX | |
2019 | : REGNAM_AL - REGNAM_EAX))->reg_name, | |
520dc8e8 | 2020 | i.op[op].regs->reg_name, |
252b5132 RH |
2021 | i.suffix); |
2022 | #endif | |
2023 | continue; | |
2024 | } | |
ce8a8b2f | 2025 | /* Any other register is bad. */ |
3f4438ab AM |
2026 | if (i.types[op] & (Reg | RegMMX | RegXMM |
2027 | | SReg2 | SReg3 | |
2028 | | Control | Debug | Test | |
2029 | | FloatReg | FloatAcc)) | |
252b5132 RH |
2030 | { |
2031 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
520dc8e8 | 2032 | i.op[op].regs->reg_name, |
252b5132 RH |
2033 | i.tm.name, |
2034 | i.suffix); | |
2035 | return; | |
2036 | } | |
2037 | } | |
2038 | } | |
add0c677 | 2039 | else if (i.suffix == LONG_MNEM_SUFFIX) |
252b5132 RH |
2040 | { |
2041 | int op; | |
47926f60 KH |
2042 | |
2043 | for (op = i.operands; --op >= 0;) | |
252b5132 RH |
2044 | /* Reject eight bit registers, except where the template |
2045 | requires them. (eg. movzb) */ | |
2046 | if ((i.types[op] & Reg8) != 0 | |
47926f60 | 2047 | && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0) |
252b5132 RH |
2048 | { |
2049 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
520dc8e8 | 2050 | i.op[op].regs->reg_name, |
252b5132 RH |
2051 | i.tm.name, |
2052 | i.suffix); | |
2053 | return; | |
2054 | } | |
252b5132 | 2055 | /* Warn if the e prefix on a general reg is missing. */ |
3e73aa7c | 2056 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
a38cf1db | 2057 | && (i.types[op] & Reg16) != 0 |
252b5132 RH |
2058 | && (i.tm.operand_types[op] & (Reg32|Acc)) != 0) |
2059 | { | |
3e73aa7c JH |
2060 | /* Prohibit these changes in the 64bit mode, since |
2061 | the lowering is more complicated. */ | |
2062 | if (flag_code == CODE_64BIT) | |
2063 | as_bad (_("Incorrect register `%%%s' used with`%c' suffix"), | |
2064 | i.op[op].regs->reg_name, | |
2065 | i.suffix); | |
2066 | #if REGISTER_WARNINGS | |
2067 | else | |
2068 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), | |
2e98d2de | 2069 | (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name, |
3e73aa7c JH |
2070 | i.op[op].regs->reg_name, |
2071 | i.suffix); | |
252b5132 | 2072 | #endif |
3e73aa7c JH |
2073 | } |
2074 | /* Warn if the r prefix on a general reg is missing. */ | |
2075 | else if ((i.types[op] & Reg64) != 0 | |
2076 | && (i.tm.operand_types[op] & (Reg32|Acc)) != 0) | |
2077 | { | |
2078 | as_bad (_("Incorrect register `%%%s' used with`%c' suffix"), | |
2079 | i.op[op].regs->reg_name, | |
2080 | i.suffix); | |
2081 | } | |
2082 | } | |
2083 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
2084 | { | |
2085 | int op; | |
3e73aa7c JH |
2086 | |
2087 | for (op = i.operands; --op >= 0; ) | |
2088 | /* Reject eight bit registers, except where the template | |
2089 | requires them. (eg. movzb) */ | |
2090 | if ((i.types[op] & Reg8) != 0 | |
2091 | && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0) | |
2092 | { | |
2093 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
2094 | i.op[op].regs->reg_name, | |
2095 | i.tm.name, | |
2096 | i.suffix); | |
2097 | return; | |
2098 | } | |
2099 | /* Warn if the e prefix on a general reg is missing. */ | |
2100 | else if (((i.types[op] & Reg16) != 0 | |
2101 | || (i.types[op] & Reg32) != 0) | |
2102 | && (i.tm.operand_types[op] & (Reg32|Acc)) != 0) | |
2103 | { | |
2104 | /* Prohibit these changes in the 64bit mode, since | |
2105 | the lowering is more complicated. */ | |
2106 | as_bad (_("Incorrect register `%%%s' used with`%c' suffix"), | |
2107 | i.op[op].regs->reg_name, | |
2108 | i.suffix); | |
2109 | } | |
252b5132 RH |
2110 | } |
2111 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
2112 | { | |
2113 | int op; | |
47926f60 | 2114 | for (op = i.operands; --op >= 0;) |
252b5132 RH |
2115 | /* Reject eight bit registers, except where the template |
2116 | requires them. (eg. movzb) */ | |
2117 | if ((i.types[op] & Reg8) != 0 | |
2118 | && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0) | |
2119 | { | |
2120 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
520dc8e8 | 2121 | i.op[op].regs->reg_name, |
252b5132 RH |
2122 | i.tm.name, |
2123 | i.suffix); | |
2124 | return; | |
2125 | } | |
252b5132 | 2126 | /* Warn if the e prefix on a general reg is present. */ |
3e73aa7c | 2127 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
a38cf1db | 2128 | && (i.types[op] & Reg32) != 0 |
252b5132 RH |
2129 | && (i.tm.operand_types[op] & (Reg16|Acc)) != 0) |
2130 | { | |
3e73aa7c JH |
2131 | /* Prohibit these changes in the 64bit mode, since |
2132 | the lowering is more complicated. */ | |
2133 | if (flag_code == CODE_64BIT) | |
2134 | as_bad (_("Incorrect register `%%%s' used with`%c' suffix"), | |
2135 | i.op[op].regs->reg_name, | |
2136 | i.suffix); | |
2137 | else | |
2138 | #if REGISTER_WARNINGS | |
2139 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), | |
2e98d2de | 2140 | (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name, |
3e73aa7c JH |
2141 | i.op[op].regs->reg_name, |
2142 | i.suffix); | |
252b5132 | 2143 | #endif |
3e73aa7c | 2144 | } |
252b5132 | 2145 | } |
fa2255cb DN |
2146 | else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize)) |
2147 | /* Do nothing if the instruction is going to ignore the prefix. */ | |
2148 | ; | |
252b5132 | 2149 | else |
47926f60 | 2150 | abort (); |
252b5132 | 2151 | } |
eecb386c AM |
2152 | else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix) |
2153 | { | |
2154 | i.suffix = stackop_size; | |
2155 | } | |
252b5132 RH |
2156 | /* Make still unresolved immediate matches conform to size of immediate |
2157 | given in i.suffix. Note: overlap2 cannot be an immediate! */ | |
3e73aa7c | 2158 | if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S)) |
252b5132 | 2159 | && overlap0 != Imm8 && overlap0 != Imm8S |
e5cb08ac | 2160 | && overlap0 != Imm16 && overlap0 != Imm32S |
b77a7acd | 2161 | && overlap0 != Imm32 && overlap0 != Imm64) |
252b5132 RH |
2162 | { |
2163 | if (i.suffix) | |
2164 | { | |
24eab124 | 2165 | overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) : |
b77a7acd | 2166 | (i.suffix == WORD_MNEM_SUFFIX ? Imm16 : |
3e73aa7c | 2167 | (i.suffix == QWORD_MNEM_SUFFIX ? Imm64 | Imm32S : Imm32))); |
252b5132 | 2168 | } |
3e73aa7c JH |
2169 | else if (overlap0 == (Imm16 | Imm32S | Imm32) |
2170 | || overlap0 == (Imm16 | Imm32) | |
2171 | || overlap0 == (Imm16 | Imm32S)) | |
252b5132 | 2172 | { |
24eab124 | 2173 | overlap0 = |
3e73aa7c | 2174 | ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32S; |
252b5132 | 2175 | } |
3e73aa7c JH |
2176 | if (overlap0 != Imm8 && overlap0 != Imm8S |
2177 | && overlap0 != Imm16 && overlap0 != Imm32S | |
2178 | && overlap0 != Imm32 && overlap0 != Imm64) | |
252b5132 RH |
2179 | { |
2180 | as_bad (_("no instruction mnemonic suffix given; can't determine immediate size")); | |
2181 | return; | |
2182 | } | |
2183 | } | |
3e73aa7c | 2184 | if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32)) |
252b5132 | 2185 | && overlap1 != Imm8 && overlap1 != Imm8S |
e5cb08ac | 2186 | && overlap1 != Imm16 && overlap1 != Imm32S |
b77a7acd | 2187 | && overlap1 != Imm32 && overlap1 != Imm64) |
252b5132 RH |
2188 | { |
2189 | if (i.suffix) | |
2190 | { | |
24eab124 | 2191 | overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) : |
b77a7acd AJ |
2192 | (i.suffix == WORD_MNEM_SUFFIX ? Imm16 : |
2193 | (i.suffix == QWORD_MNEM_SUFFIX ? Imm64 | Imm32S : Imm32))); | |
252b5132 | 2194 | } |
3e73aa7c JH |
2195 | else if (overlap1 == (Imm16 | Imm32 | Imm32S) |
2196 | || overlap1 == (Imm16 | Imm32) | |
2197 | || overlap1 == (Imm16 | Imm32S)) | |
252b5132 | 2198 | { |
24eab124 | 2199 | overlap1 = |
3e73aa7c | 2200 | ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32S; |
252b5132 | 2201 | } |
3e73aa7c JH |
2202 | if (overlap1 != Imm8 && overlap1 != Imm8S |
2203 | && overlap1 != Imm16 && overlap1 != Imm32S | |
2204 | && overlap1 != Imm32 && overlap1 != Imm64) | |
252b5132 | 2205 | { |
3e73aa7c | 2206 | as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix); |
252b5132 RH |
2207 | return; |
2208 | } | |
2209 | } | |
2210 | assert ((overlap2 & Imm) == 0); | |
2211 | ||
2212 | i.types[0] = overlap0; | |
2213 | if (overlap0 & ImplicitRegister) | |
2214 | i.reg_operands--; | |
2215 | if (overlap0 & Imm1) | |
ce8a8b2f | 2216 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 RH |
2217 | |
2218 | i.types[1] = overlap1; | |
2219 | if (overlap1 & ImplicitRegister) | |
2220 | i.reg_operands--; | |
2221 | ||
2222 | i.types[2] = overlap2; | |
2223 | if (overlap2 & ImplicitRegister) | |
2224 | i.reg_operands--; | |
2225 | ||
2226 | /* Finalize opcode. First, we change the opcode based on the operand | |
2227 | size given by i.suffix: We need not change things for byte insns. */ | |
2228 | ||
2229 | if (!i.suffix && (i.tm.opcode_modifier & W)) | |
2230 | { | |
2231 | as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction")); | |
2232 | return; | |
2233 | } | |
2234 | ||
ce8a8b2f | 2235 | /* For movzx and movsx, need to check the register type. */ |
252b5132 | 2236 | if (intel_syntax |
24eab124 | 2237 | && (i.tm.base_opcode == 0xfb6 || i.tm.base_opcode == 0xfbe)) |
252b5132 | 2238 | if (i.suffix && i.suffix == BYTE_MNEM_SUFFIX) |
24eab124 AM |
2239 | { |
2240 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
252b5132 | 2241 | |
520dc8e8 | 2242 | if ((i.op[1].regs->reg_type & Reg16) != 0) |
24eab124 AM |
2243 | if (!add_prefix (prefix)) |
2244 | return; | |
2245 | } | |
252b5132 RH |
2246 | |
2247 | if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX) | |
2248 | { | |
2249 | /* It's not a byte, select word/dword operation. */ | |
2250 | if (i.tm.opcode_modifier & W) | |
2251 | { | |
2252 | if (i.tm.opcode_modifier & ShortForm) | |
2253 | i.tm.base_opcode |= 8; | |
2254 | else | |
2255 | i.tm.base_opcode |= 1; | |
2256 | } | |
2257 | /* Now select between word & dword operations via the operand | |
2258 | size prefix, except for instructions that will ignore this | |
2259 | prefix anyway. */ | |
3e73aa7c JH |
2260 | if (i.suffix != QWORD_MNEM_SUFFIX |
2261 | && (i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) | |
252b5132 RH |
2262 | && !(i.tm.opcode_modifier & IgnoreSize)) |
2263 | { | |
2264 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
2265 | if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */ | |
2266 | prefix = ADDR_PREFIX_OPCODE; | |
2267 | ||
2268 | if (! add_prefix (prefix)) | |
2269 | return; | |
2270 | } | |
3e73aa7c | 2271 | |
7ecd2f8b JH |
2272 | if (i.suffix != QWORD_MNEM_SUFFIX && (flag_code == CODE_64BIT) |
2273 | && !(i.tm.opcode_modifier & IgnoreSize) | |
2274 | && (i.tm.opcode_modifier & JumpByte)) | |
2275 | { | |
2276 | if (! add_prefix (ADDR_PREFIX_OPCODE)) | |
2277 | return; | |
2278 | } | |
2279 | ||
3e73aa7c JH |
2280 | /* Set mode64 for an operand. */ |
2281 | if (i.suffix == QWORD_MNEM_SUFFIX | |
2282 | && !(i.tm.opcode_modifier & NoRex64)) | |
b96d3a20 | 2283 | { |
3e73aa7c | 2284 | i.rex.mode64 = 1; |
b96d3a20 JH |
2285 | if (flag_code < CODE_64BIT) |
2286 | { | |
e5cb08ac KH |
2287 | as_bad (_("64bit operations available only in 64bit modes.")); |
2288 | return; | |
b96d3a20 JH |
2289 | } |
2290 | } | |
3e73aa7c | 2291 | |
252b5132 | 2292 | /* Size floating point instruction. */ |
f16b83df | 2293 | if (i.suffix == LONG_MNEM_SUFFIX) |
252b5132 RH |
2294 | { |
2295 | if (i.tm.opcode_modifier & FloatMF) | |
2296 | i.tm.base_opcode ^= 4; | |
2297 | } | |
252b5132 RH |
2298 | } |
2299 | ||
3f4438ab | 2300 | if (i.tm.opcode_modifier & ImmExt) |
252b5132 | 2301 | { |
3f4438ab AM |
2302 | /* These AMD 3DNow! and Intel Katmai New Instructions have an |
2303 | opcode suffix which is coded in the same place as an 8-bit | |
2304 | immediate field would be. Here we fake an 8-bit immediate | |
2305 | operand from the opcode suffix stored in tm.extension_opcode. */ | |
252b5132 RH |
2306 | |
2307 | expressionS *exp; | |
2308 | ||
47926f60 | 2309 | assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS); |
252b5132 RH |
2310 | |
2311 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 2312 | i.op[i.operands].imms = exp; |
252b5132 RH |
2313 | i.types[i.operands++] = Imm8; |
2314 | exp->X_op = O_constant; | |
2315 | exp->X_add_number = i.tm.extension_opcode; | |
2316 | i.tm.extension_opcode = None; | |
2317 | } | |
2318 | ||
47926f60 | 2319 | /* For insns with operands there are more diddles to do to the opcode. */ |
252b5132 RH |
2320 | if (i.operands) |
2321 | { | |
24eab124 | 2322 | /* Default segment register this instruction will use |
252b5132 RH |
2323 | for memory accesses. 0 means unknown. |
2324 | This is only for optimizing out unnecessary segment overrides. */ | |
2325 | const seg_entry *default_seg = 0; | |
2326 | ||
252b5132 RH |
2327 | /* The imul $imm, %reg instruction is converted into |
2328 | imul $imm, %reg, %reg, and the clr %reg instruction | |
2329 | is converted into xor %reg, %reg. */ | |
2330 | if (i.tm.opcode_modifier & regKludge) | |
2331 | { | |
2332 | unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1; | |
47926f60 KH |
2333 | /* Pretend we saw the extra register operand. */ |
2334 | assert (i.op[first_reg_op + 1].regs == 0); | |
2335 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; | |
2336 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
252b5132 RH |
2337 | i.reg_operands = 2; |
2338 | } | |
2339 | ||
2340 | if (i.tm.opcode_modifier & ShortForm) | |
2341 | { | |
47926f60 | 2342 | /* The register or float register operand is in operand 0 or 1. */ |
252b5132 | 2343 | unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1; |
47926f60 | 2344 | /* Register goes in low 3 bits of opcode. */ |
520dc8e8 | 2345 | i.tm.base_opcode |= i.op[op].regs->reg_num; |
3e73aa7c | 2346 | if (i.op[op].regs->reg_flags & RegRex) |
e5cb08ac | 2347 | i.rex.extZ = 1; |
a38cf1db | 2348 | if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0) |
252b5132 RH |
2349 | { |
2350 | /* Warn about some common errors, but press on regardless. | |
2351 | The first case can be generated by gcc (<= 2.8.1). */ | |
2352 | if (i.operands == 2) | |
2353 | { | |
47926f60 | 2354 | /* Reversed arguments on faddp, fsubp, etc. */ |
252b5132 | 2355 | as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name, |
520dc8e8 AM |
2356 | i.op[1].regs->reg_name, |
2357 | i.op[0].regs->reg_name); | |
252b5132 RH |
2358 | } |
2359 | else | |
2360 | { | |
47926f60 | 2361 | /* Extraneous `l' suffix on fp insn. */ |
252b5132 | 2362 | as_warn (_("translating to `%s %%%s'"), i.tm.name, |
520dc8e8 | 2363 | i.op[0].regs->reg_name); |
252b5132 RH |
2364 | } |
2365 | } | |
2366 | } | |
2367 | else if (i.tm.opcode_modifier & Modrm) | |
2368 | { | |
2369 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
2370 | must be put into the modrm byte). | |
2371 | Now, we make the modrm & index base bytes based on all the | |
47926f60 | 2372 | info we've collected. */ |
252b5132 RH |
2373 | |
2374 | /* i.reg_operands MUST be the number of real register operands; | |
47926f60 | 2375 | implicit registers do not count. */ |
252b5132 RH |
2376 | if (i.reg_operands == 2) |
2377 | { | |
2378 | unsigned int source, dest; | |
2379 | source = ((i.types[0] | |
3f4438ab AM |
2380 | & (Reg | RegMMX | RegXMM |
2381 | | SReg2 | SReg3 | |
2382 | | Control | Debug | Test)) | |
252b5132 RH |
2383 | ? 0 : 1); |
2384 | dest = source + 1; | |
2385 | ||
252b5132 | 2386 | i.rm.mode = 3; |
3f4438ab AM |
2387 | /* One of the register operands will be encoded in the |
2388 | i.tm.reg field, the other in the combined i.tm.mode | |
2389 | and i.tm.regmem fields. If no form of this | |
2390 | instruction supports a memory destination operand, | |
2391 | then we assume the source operand may sometimes be | |
2392 | a memory operand and so we need to store the | |
2393 | destination in the i.rm.reg field. */ | |
2394 | if ((i.tm.operand_types[dest] & AnyMem) == 0) | |
252b5132 | 2395 | { |
520dc8e8 AM |
2396 | i.rm.reg = i.op[dest].regs->reg_num; |
2397 | i.rm.regmem = i.op[source].regs->reg_num; | |
3e73aa7c | 2398 | if (i.op[dest].regs->reg_flags & RegRex) |
e5cb08ac | 2399 | i.rex.extX = 1; |
3e73aa7c | 2400 | if (i.op[source].regs->reg_flags & RegRex) |
e5cb08ac | 2401 | i.rex.extZ = 1; |
252b5132 RH |
2402 | } |
2403 | else | |
2404 | { | |
520dc8e8 AM |
2405 | i.rm.reg = i.op[source].regs->reg_num; |
2406 | i.rm.regmem = i.op[dest].regs->reg_num; | |
3e73aa7c | 2407 | if (i.op[dest].regs->reg_flags & RegRex) |
e5cb08ac | 2408 | i.rex.extZ = 1; |
3e73aa7c | 2409 | if (i.op[source].regs->reg_flags & RegRex) |
e5cb08ac | 2410 | i.rex.extX = 1; |
252b5132 RH |
2411 | } |
2412 | } | |
2413 | else | |
47926f60 | 2414 | { /* If it's not 2 reg operands... */ |
252b5132 RH |
2415 | if (i.mem_operands) |
2416 | { | |
2417 | unsigned int fake_zero_displacement = 0; | |
2418 | unsigned int op = ((i.types[0] & AnyMem) | |
2419 | ? 0 | |
2420 | : (i.types[1] & AnyMem) ? 1 : 2); | |
2421 | ||
2422 | default_seg = &ds; | |
2423 | ||
2424 | if (! i.base_reg) | |
2425 | { | |
2426 | i.rm.mode = 0; | |
2427 | if (! i.disp_operands) | |
2428 | fake_zero_displacement = 1; | |
2429 | if (! i.index_reg) | |
2430 | { | |
47926f60 | 2431 | /* Operand is just <disp> */ |
7ecd2f8b JH |
2432 | if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0) |
2433 | && (flag_code != CODE_64BIT)) | |
252b5132 RH |
2434 | { |
2435 | i.rm.regmem = NO_BASE_REGISTER_16; | |
2436 | i.types[op] &= ~Disp; | |
2437 | i.types[op] |= Disp16; | |
2438 | } | |
7ecd2f8b JH |
2439 | else if (flag_code != CODE_64BIT |
2440 | || (i.prefix[ADDR_PREFIX] != 0)) | |
252b5132 RH |
2441 | { |
2442 | i.rm.regmem = NO_BASE_REGISTER; | |
2443 | i.types[op] &= ~Disp; | |
2444 | i.types[op] |= Disp32; | |
2445 | } | |
3e73aa7c JH |
2446 | else |
2447 | { | |
e5cb08ac KH |
2448 | /* 64bit mode overwrites the 32bit |
2449 | absolute addressing by RIP relative | |
2450 | addressing and absolute addressing | |
2451 | is encoded by one of the redundant | |
2452 | SIB forms. */ | |
3e73aa7c JH |
2453 | |
2454 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
2455 | i.sib.base = NO_BASE_REGISTER; | |
2456 | i.sib.index = NO_INDEX_REGISTER; | |
2457 | i.types[op] &= ~Disp; | |
2458 | i.types[op] |= Disp32S; | |
2459 | } | |
252b5132 | 2460 | } |
47926f60 | 2461 | else /* ! i.base_reg && i.index_reg */ |
252b5132 RH |
2462 | { |
2463 | i.sib.index = i.index_reg->reg_num; | |
2464 | i.sib.base = NO_BASE_REGISTER; | |
2465 | i.sib.scale = i.log2_scale_factor; | |
2466 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
2467 | i.types[op] &= ~Disp; | |
3e73aa7c JH |
2468 | if (flag_code != CODE_64BIT) |
2469 | i.types[op] |= Disp32; /* Must be 32 bit */ | |
2470 | else | |
2471 | i.types[op] |= Disp32S; | |
2472 | if (i.index_reg->reg_flags & RegRex) | |
e5cb08ac | 2473 | i.rex.extY = 1; |
252b5132 RH |
2474 | } |
2475 | } | |
3e73aa7c JH |
2476 | /* RIP addressing for 64bit mode. */ |
2477 | else if (i.base_reg->reg_type == BaseIndex) | |
2478 | { | |
2479 | i.rm.regmem = NO_BASE_REGISTER; | |
2480 | i.types[op] &= ~Disp; | |
2481 | i.types[op] |= Disp32S; | |
2482 | i.flags[op] = Operand_PCrel; | |
2483 | } | |
252b5132 RH |
2484 | else if (i.base_reg->reg_type & Reg16) |
2485 | { | |
2486 | switch (i.base_reg->reg_num) | |
2487 | { | |
47926f60 | 2488 | case 3: /* (%bx) */ |
252b5132 RH |
2489 | if (! i.index_reg) |
2490 | i.rm.regmem = 7; | |
47926f60 | 2491 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ |
252b5132 RH |
2492 | i.rm.regmem = i.index_reg->reg_num - 6; |
2493 | break; | |
47926f60 | 2494 | case 5: /* (%bp) */ |
252b5132 RH |
2495 | default_seg = &ss; |
2496 | if (! i.index_reg) | |
2497 | { | |
2498 | i.rm.regmem = 6; | |
2499 | if ((i.types[op] & Disp) == 0) | |
2500 | { | |
47926f60 | 2501 | /* fake (%bp) into 0(%bp) */ |
252b5132 RH |
2502 | i.types[op] |= Disp8; |
2503 | fake_zero_displacement = 1; | |
2504 | } | |
2505 | } | |
47926f60 | 2506 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ |
252b5132 RH |
2507 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; |
2508 | break; | |
47926f60 | 2509 | default: /* (%si) -> 4 or (%di) -> 5 */ |
252b5132 RH |
2510 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; |
2511 | } | |
2512 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
2513 | } | |
3e73aa7c | 2514 | else /* i.base_reg and 32/64 bit mode */ |
252b5132 | 2515 | { |
3e73aa7c JH |
2516 | if (flag_code == CODE_64BIT |
2517 | && (i.types[op] & Disp)) | |
2518 | { | |
2519 | if (i.types[op] & Disp8) | |
2520 | i.types[op] = Disp8 | Disp32S; | |
2521 | else | |
2522 | i.types[op] = Disp32S; | |
2523 | } | |
252b5132 | 2524 | i.rm.regmem = i.base_reg->reg_num; |
3e73aa7c | 2525 | if (i.base_reg->reg_flags & RegRex) |
e5cb08ac | 2526 | i.rex.extZ = 1; |
252b5132 | 2527 | i.sib.base = i.base_reg->reg_num; |
3e73aa7c JH |
2528 | /* x86-64 ignores REX prefix bit here to avoid |
2529 | decoder complications. */ | |
2530 | if ((i.base_reg->reg_num & 7) == EBP_REG_NUM) | |
252b5132 RH |
2531 | { |
2532 | default_seg = &ss; | |
2533 | if (i.disp_operands == 0) | |
2534 | { | |
2535 | fake_zero_displacement = 1; | |
2536 | i.types[op] |= Disp8; | |
2537 | } | |
2538 | } | |
2539 | else if (i.base_reg->reg_num == ESP_REG_NUM) | |
2540 | { | |
2541 | default_seg = &ss; | |
2542 | } | |
2543 | i.sib.scale = i.log2_scale_factor; | |
2544 | if (! i.index_reg) | |
2545 | { | |
2546 | /* <disp>(%esp) becomes two byte modrm | |
2547 | with no index register. We've already | |
2548 | stored the code for esp in i.rm.regmem | |
2549 | ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any | |
2550 | base register besides %esp will not use | |
2551 | the extra modrm byte. */ | |
2552 | i.sib.index = NO_INDEX_REGISTER; | |
2553 | #if ! SCALE1_WHEN_NO_INDEX | |
2554 | /* Another case where we force the second | |
2555 | modrm byte. */ | |
2556 | if (i.log2_scale_factor) | |
2557 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
2558 | #endif | |
2559 | } | |
2560 | else | |
2561 | { | |
2562 | i.sib.index = i.index_reg->reg_num; | |
2563 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
3e73aa7c | 2564 | if (i.index_reg->reg_flags & RegRex) |
e5cb08ac | 2565 | i.rex.extY = 1; |
252b5132 RH |
2566 | } |
2567 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
2568 | } | |
2569 | ||
2570 | if (fake_zero_displacement) | |
2571 | { | |
2572 | /* Fakes a zero displacement assuming that i.types[op] | |
47926f60 | 2573 | holds the correct displacement size. */ |
b4cac588 AM |
2574 | expressionS *exp; |
2575 | ||
520dc8e8 | 2576 | assert (i.op[op].disps == 0); |
252b5132 | 2577 | exp = &disp_expressions[i.disp_operands++]; |
520dc8e8 | 2578 | i.op[op].disps = exp; |
252b5132 RH |
2579 | exp->X_op = O_constant; |
2580 | exp->X_add_number = 0; | |
2581 | exp->X_add_symbol = (symbolS *) 0; | |
2582 | exp->X_op_symbol = (symbolS *) 0; | |
2583 | } | |
2584 | } | |
2585 | ||
2586 | /* Fill in i.rm.reg or i.rm.regmem field with register | |
2587 | operand (if any) based on i.tm.extension_opcode. | |
2588 | Again, we must be careful to make sure that | |
2589 | segment/control/debug/test/MMX registers are coded | |
47926f60 | 2590 | into the i.rm.reg field. */ |
252b5132 RH |
2591 | if (i.reg_operands) |
2592 | { | |
2593 | unsigned int op = | |
2594 | ((i.types[0] | |
3f4438ab AM |
2595 | & (Reg | RegMMX | RegXMM |
2596 | | SReg2 | SReg3 | |
2597 | | Control | Debug | Test)) | |
252b5132 RH |
2598 | ? 0 |
2599 | : ((i.types[1] | |
3f4438ab AM |
2600 | & (Reg | RegMMX | RegXMM |
2601 | | SReg2 | SReg3 | |
2602 | | Control | Debug | Test)) | |
252b5132 RH |
2603 | ? 1 |
2604 | : 2)); | |
2605 | /* If there is an extension opcode to put here, the | |
47926f60 | 2606 | register number must be put into the regmem field. */ |
252b5132 | 2607 | if (i.tm.extension_opcode != None) |
3e73aa7c JH |
2608 | { |
2609 | i.rm.regmem = i.op[op].regs->reg_num; | |
2610 | if (i.op[op].regs->reg_flags & RegRex) | |
e5cb08ac | 2611 | i.rex.extZ = 1; |
3e73aa7c | 2612 | } |
252b5132 | 2613 | else |
3e73aa7c JH |
2614 | { |
2615 | i.rm.reg = i.op[op].regs->reg_num; | |
2616 | if (i.op[op].regs->reg_flags & RegRex) | |
e5cb08ac | 2617 | i.rex.extX = 1; |
3e73aa7c | 2618 | } |
252b5132 RH |
2619 | |
2620 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 | |
2621 | we must set it to 3 to indicate this is a register | |
2622 | operand in the regmem field. */ | |
2623 | if (!i.mem_operands) | |
2624 | i.rm.mode = 3; | |
2625 | } | |
2626 | ||
47926f60 | 2627 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
252b5132 RH |
2628 | if (i.tm.extension_opcode != None) |
2629 | i.rm.reg = i.tm.extension_opcode; | |
2630 | } | |
2631 | } | |
2632 | else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm)) | |
2633 | { | |
47926f60 KH |
2634 | if (i.tm.base_opcode == POP_SEG_SHORT |
2635 | && i.op[0].regs->reg_num == 1) | |
252b5132 RH |
2636 | { |
2637 | as_bad (_("you can't `pop %%cs'")); | |
2638 | return; | |
2639 | } | |
520dc8e8 | 2640 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); |
3e73aa7c JH |
2641 | if (i.op[0].regs->reg_flags & RegRex) |
2642 | i.rex.extZ = 1; | |
252b5132 RH |
2643 | } |
2644 | else if ((i.tm.base_opcode & ~(D|W)) == MOV_AX_DISP32) | |
2645 | { | |
2646 | default_seg = &ds; | |
2647 | } | |
2648 | else if ((i.tm.opcode_modifier & IsString) != 0) | |
2649 | { | |
2650 | /* For the string instructions that allow a segment override | |
2651 | on one of their operands, the default segment is ds. */ | |
2652 | default_seg = &ds; | |
2653 | } | |
2654 | ||
2655 | /* If a segment was explicitly specified, | |
2656 | and the specified segment is not the default, | |
2657 | use an opcode prefix to select it. | |
2658 | If we never figured out what the default segment is, | |
2659 | then default_seg will be zero at this point, | |
2660 | and the specified segment prefix will always be used. */ | |
2661 | if ((i.seg[0]) && (i.seg[0] != default_seg)) | |
2662 | { | |
2663 | if (! add_prefix (i.seg[0]->seg_prefix)) | |
2664 | return; | |
2665 | } | |
2666 | } | |
a38cf1db | 2667 | else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0) |
252b5132 | 2668 | { |
24eab124 AM |
2669 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ |
2670 | as_warn (_("translating to `%sp'"), i.tm.name); | |
252b5132 RH |
2671 | } |
2672 | } | |
2673 | ||
47926f60 | 2674 | /* Handle conversion of 'int $3' --> special int3 insn. */ |
520dc8e8 | 2675 | if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3) |
252b5132 RH |
2676 | { |
2677 | i.tm.base_opcode = INT3_OPCODE; | |
2678 | i.imm_operands = 0; | |
2679 | } | |
2680 | ||
2f66722d | 2681 | if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword)) |
520dc8e8 | 2682 | && i.op[0].disps->X_op == O_constant) |
2f66722d AM |
2683 | { |
2684 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
2685 | the absolute address given by the constant. Since ix86 jumps and | |
2686 | calls are pc relative, we need to generate a reloc. */ | |
520dc8e8 AM |
2687 | i.op[0].disps->X_add_symbol = &abs_symbol; |
2688 | i.op[0].disps->X_op = O_symbol; | |
2f66722d AM |
2689 | } |
2690 | ||
3e73aa7c JH |
2691 | if (i.tm.opcode_modifier & Rex64) |
2692 | i.rex.mode64 = 1; | |
2693 | ||
2694 | /* For 8bit registers we would need an empty rex prefix. | |
2695 | Also in the case instruction is already having prefix, | |
2696 | we need to convert old registers to new ones. */ | |
2697 | ||
2698 | if (((i.types[0] & Reg8) && (i.op[0].regs->reg_flags & RegRex64)) | |
2699 | || ((i.types[1] & Reg8) && (i.op[1].regs->reg_flags & RegRex64)) | |
2700 | || ((i.rex.mode64 || i.rex.extX || i.rex.extY || i.rex.extZ || i.rex.empty) | |
2701 | && ((i.types[0] & Reg8) || (i.types[1] & Reg8)))) | |
2702 | { | |
2703 | int x; | |
e5cb08ac | 2704 | i.rex.empty = 1; |
3e73aa7c JH |
2705 | for (x = 0; x < 2; x++) |
2706 | { | |
2707 | /* Look for 8bit operand that does use old registers. */ | |
2708 | if (i.types[x] & Reg8 | |
2709 | && !(i.op[x].regs->reg_flags & RegRex64)) | |
2710 | { | |
2711 | /* In case it is "hi" register, give up. */ | |
2712 | if (i.op[x].regs->reg_num > 3) | |
2713 | as_bad (_("Can't encode registers '%%%s' in the instruction requiring REX prefix.\n"), | |
2714 | i.op[x].regs->reg_name); | |
2715 | ||
2716 | /* Otherwise it is equivalent to the extended register. | |
2717 | Since the encoding don't change this is merely cosmetical | |
2718 | cleanup for debug output. */ | |
2719 | ||
2720 | i.op[x].regs = i.op[x].regs + 8; | |
2721 | } | |
2722 | } | |
2723 | } | |
2724 | ||
2725 | if (i.rex.mode64 || i.rex.extX || i.rex.extY || i.rex.extZ || i.rex.empty) | |
2726 | add_prefix (0x40 | |
2727 | | (i.rex.mode64 ? 8 : 0) | |
2728 | | (i.rex.extX ? 4 : 0) | |
2729 | | (i.rex.extY ? 2 : 0) | |
2730 | | (i.rex.extZ ? 1 : 0)); | |
2731 | ||
47926f60 | 2732 | /* We are ready to output the insn. */ |
252b5132 RH |
2733 | { |
2734 | register char *p; | |
2735 | ||
9fcc94b6 AM |
2736 | /* Tie dwarf2 debug info to the address at the start of the insn. |
2737 | We can't do this after the insn has been output as the current | |
2738 | frag may have been closed off. eg. by frag_var. */ | |
2739 | dwarf2_emit_insn (0); | |
2740 | ||
47926f60 | 2741 | /* Output jumps. */ |
252b5132 RH |
2742 | if (i.tm.opcode_modifier & Jump) |
2743 | { | |
a217f122 AM |
2744 | int code16; |
2745 | int prefix; | |
e0890092 AM |
2746 | relax_substateT subtype; |
2747 | symbolS *sym; | |
2748 | offsetT off; | |
252b5132 | 2749 | |
a217f122 | 2750 | code16 = 0; |
3e73aa7c | 2751 | if (flag_code == CODE_16BIT) |
a217f122 AM |
2752 | code16 = CODE16; |
2753 | ||
2754 | prefix = 0; | |
2755 | if (i.prefix[DATA_PREFIX]) | |
252b5132 | 2756 | { |
a217f122 | 2757 | prefix = 1; |
252b5132 | 2758 | i.prefixes -= 1; |
a217f122 | 2759 | code16 ^= CODE16; |
252b5132 | 2760 | } |
cb9401fc AM |
2761 | /* Pentium4 branch hints. */ |
2762 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
2763 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2764 | { | |
2765 | prefix++; | |
2766 | i.prefixes--; | |
2767 | } | |
3e73aa7c JH |
2768 | if (i.prefix[REX_PREFIX]) |
2769 | { | |
2770 | prefix++; | |
e5cb08ac | 2771 | i.prefixes--; |
3e73aa7c | 2772 | } |
252b5132 | 2773 | |
a217f122 | 2774 | if (i.prefixes != 0 && !intel_syntax) |
252b5132 RH |
2775 | as_warn (_("skipping prefixes on this instruction")); |
2776 | ||
2f66722d AM |
2777 | /* It's always a symbol; End frag & setup for relax. |
2778 | Make sure there is enough room in this frag for the largest | |
2779 | instruction we may generate in md_convert_frag. This is 2 | |
2780 | bytes for the opcode and room for the prefix and largest | |
2781 | displacement. */ | |
fddf5b5b | 2782 | frag_grow (prefix + 2 + 4); |
2f66722d AM |
2783 | /* Prefix and 1 opcode byte go in fr_fix. */ |
2784 | p = frag_more (prefix + 1); | |
3e73aa7c | 2785 | if (i.prefix[DATA_PREFIX]) |
2f66722d | 2786 | *p++ = DATA_PREFIX_OPCODE; |
cb9401fc AM |
2787 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE |
2788 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
2789 | *p++ = i.prefix[SEG_PREFIX]; | |
3e73aa7c JH |
2790 | if (i.prefix[REX_PREFIX]) |
2791 | *p++ = i.prefix[REX_PREFIX]; | |
2f66722d | 2792 | *p = i.tm.base_opcode; |
e0890092 AM |
2793 | |
2794 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
2795 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL); | |
2796 | else if ((cpu_arch_flags & Cpu386) != 0) | |
2797 | subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL); | |
2798 | else | |
2799 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL); | |
2800 | subtype |= code16; | |
2801 | ||
2802 | sym = i.op[0].disps->X_add_symbol; | |
2803 | off = i.op[0].disps->X_add_number; | |
2804 | ||
2805 | if (i.op[0].disps->X_op != O_constant | |
2806 | && i.op[0].disps->X_op != O_symbol) | |
2807 | { | |
2808 | /* Handle complex expressions. */ | |
2809 | sym = make_expr_symbol (i.op[0].disps); | |
2810 | off = 0; | |
2811 | } | |
2812 | ||
2813 | /* 1 possible extra opcode + 4 byte displacement go in var part. | |
ee7fcc42 | 2814 | Pass reloc in fr_var. */ |
e0890092 | 2815 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); |
252b5132 RH |
2816 | } |
2817 | else if (i.tm.opcode_modifier & (JumpByte | JumpDword)) | |
2818 | { | |
a217f122 | 2819 | int size; |
252b5132 | 2820 | |
a217f122 | 2821 | if (i.tm.opcode_modifier & JumpByte) |
252b5132 | 2822 | { |
a217f122 AM |
2823 | /* This is a loop or jecxz type instruction. */ |
2824 | size = 1; | |
252b5132 RH |
2825 | if (i.prefix[ADDR_PREFIX]) |
2826 | { | |
252b5132 RH |
2827 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); |
2828 | i.prefixes -= 1; | |
2829 | } | |
cb9401fc AM |
2830 | /* Pentium4 branch hints. */ |
2831 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
2832 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2833 | { | |
2834 | FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); | |
2835 | i.prefixes--; | |
2836 | } | |
252b5132 RH |
2837 | } |
2838 | else | |
2839 | { | |
a217f122 AM |
2840 | int code16; |
2841 | ||
2842 | code16 = 0; | |
3e73aa7c | 2843 | if (flag_code == CODE_16BIT) |
a217f122 | 2844 | code16 = CODE16; |
252b5132 RH |
2845 | |
2846 | if (i.prefix[DATA_PREFIX]) | |
2847 | { | |
252b5132 RH |
2848 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); |
2849 | i.prefixes -= 1; | |
a217f122 | 2850 | code16 ^= CODE16; |
252b5132 | 2851 | } |
252b5132 | 2852 | |
a217f122 | 2853 | size = 4; |
252b5132 RH |
2854 | if (code16) |
2855 | size = 2; | |
2856 | } | |
2857 | ||
3e73aa7c JH |
2858 | if (i.prefix[REX_PREFIX]) |
2859 | { | |
2860 | FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); | |
3e73aa7c JH |
2861 | i.prefixes -= 1; |
2862 | } | |
2863 | ||
a217f122 | 2864 | if (i.prefixes != 0 && !intel_syntax) |
252b5132 RH |
2865 | as_warn (_("skipping prefixes on this instruction")); |
2866 | ||
cb9401fc AM |
2867 | p = frag_more (1 + size); |
2868 | *p++ = i.tm.base_opcode; | |
252b5132 | 2869 | |
2f66722d | 2870 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
1ae12ab7 | 2871 | i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0])); |
252b5132 RH |
2872 | } |
2873 | else if (i.tm.opcode_modifier & JumpInterSegment) | |
2874 | { | |
2875 | int size; | |
a217f122 AM |
2876 | int prefix; |
2877 | int code16; | |
252b5132 | 2878 | |
a217f122 | 2879 | code16 = 0; |
3e73aa7c | 2880 | if (flag_code == CODE_16BIT) |
a217f122 AM |
2881 | code16 = CODE16; |
2882 | ||
2883 | prefix = 0; | |
2884 | if (i.prefix[DATA_PREFIX]) | |
252b5132 | 2885 | { |
a217f122 | 2886 | prefix = 1; |
252b5132 | 2887 | i.prefixes -= 1; |
a217f122 | 2888 | code16 ^= CODE16; |
252b5132 | 2889 | } |
3e73aa7c JH |
2890 | if (i.prefix[REX_PREFIX]) |
2891 | { | |
2892 | prefix++; | |
2893 | i.prefixes -= 1; | |
2894 | } | |
252b5132 RH |
2895 | |
2896 | size = 4; | |
252b5132 | 2897 | if (code16) |
f6af82bd | 2898 | size = 2; |
252b5132 | 2899 | |
a217f122 | 2900 | if (i.prefixes != 0 && !intel_syntax) |
252b5132 RH |
2901 | as_warn (_("skipping prefixes on this instruction")); |
2902 | ||
47926f60 | 2903 | /* 1 opcode; 2 segment; offset */ |
252b5132 | 2904 | p = frag_more (prefix + 1 + 2 + size); |
3e73aa7c JH |
2905 | |
2906 | if (i.prefix[DATA_PREFIX]) | |
252b5132 | 2907 | *p++ = DATA_PREFIX_OPCODE; |
3e73aa7c JH |
2908 | |
2909 | if (i.prefix[REX_PREFIX]) | |
2910 | *p++ = i.prefix[REX_PREFIX]; | |
2911 | ||
252b5132 | 2912 | *p++ = i.tm.base_opcode; |
520dc8e8 | 2913 | if (i.op[1].imms->X_op == O_constant) |
252b5132 | 2914 | { |
847f7ad4 | 2915 | offsetT n = i.op[1].imms->X_add_number; |
252b5132 | 2916 | |
773f551c AM |
2917 | if (size == 2 |
2918 | && !fits_in_unsigned_word (n) | |
2919 | && !fits_in_signed_word (n)) | |
252b5132 RH |
2920 | { |
2921 | as_bad (_("16-bit jump out of range")); | |
2922 | return; | |
2923 | } | |
847f7ad4 | 2924 | md_number_to_chars (p, n, size); |
252b5132 RH |
2925 | } |
2926 | else | |
2927 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
1ae12ab7 | 2928 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); |
520dc8e8 | 2929 | if (i.op[0].imms->X_op != O_constant) |
252b5132 RH |
2930 | as_bad (_("can't handle non absolute segment in `%s'"), |
2931 | i.tm.name); | |
520dc8e8 | 2932 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); |
252b5132 RH |
2933 | } |
2934 | else | |
2935 | { | |
47926f60 | 2936 | /* Output normal instructions here. */ |
252b5132 RH |
2937 | unsigned char *q; |
2938 | ||
7bc70a8e JH |
2939 | /* All opcodes on i386 have eighter 1 or 2 bytes. We may use third |
2940 | byte for the SSE instructions to specify prefix they require. */ | |
2941 | if (i.tm.base_opcode & 0xff0000) | |
2942 | add_prefix ((i.tm.base_opcode >> 16) & 0xff); | |
2943 | ||
47926f60 | 2944 | /* The prefix bytes. */ |
252b5132 RH |
2945 | for (q = i.prefix; |
2946 | q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]); | |
2947 | q++) | |
2948 | { | |
2949 | if (*q) | |
2950 | { | |
252b5132 RH |
2951 | p = frag_more (1); |
2952 | md_number_to_chars (p, (valueT) *q, 1); | |
2953 | } | |
2954 | } | |
2955 | ||
47926f60 | 2956 | /* Now the opcode; be careful about word order here! */ |
252b5132 RH |
2957 | if (fits_in_unsigned_byte (i.tm.base_opcode)) |
2958 | { | |
252b5132 RH |
2959 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); |
2960 | } | |
7bc70a8e | 2961 | else |
252b5132 | 2962 | { |
252b5132 | 2963 | p = frag_more (2); |
47926f60 | 2964 | /* Put out high byte first: can't use md_number_to_chars! */ |
252b5132 RH |
2965 | *p++ = (i.tm.base_opcode >> 8) & 0xff; |
2966 | *p = i.tm.base_opcode & 0xff; | |
2967 | } | |
252b5132 RH |
2968 | |
2969 | /* Now the modrm byte and sib byte (if present). */ | |
2970 | if (i.tm.opcode_modifier & Modrm) | |
2971 | { | |
252b5132 RH |
2972 | p = frag_more (1); |
2973 | md_number_to_chars (p, | |
2974 | (valueT) (i.rm.regmem << 0 | |
2975 | | i.rm.reg << 3 | |
2976 | | i.rm.mode << 6), | |
2977 | 1); | |
2978 | /* If i.rm.regmem == ESP (4) | |
2979 | && i.rm.mode != (Register mode) | |
2980 | && not 16 bit | |
2981 | ==> need second modrm byte. */ | |
2982 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
2983 | && i.rm.mode != 3 | |
2984 | && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0)) | |
2985 | { | |
252b5132 RH |
2986 | p = frag_more (1); |
2987 | md_number_to_chars (p, | |
2988 | (valueT) (i.sib.base << 0 | |
2989 | | i.sib.index << 3 | |
2990 | | i.sib.scale << 6), | |
2991 | 1); | |
2992 | } | |
2993 | } | |
2994 | ||
2995 | if (i.disp_operands) | |
2996 | { | |
2997 | register unsigned int n; | |
2998 | ||
2999 | for (n = 0; n < i.operands; n++) | |
3000 | { | |
520dc8e8 | 3001 | if (i.types[n] & Disp) |
252b5132 | 3002 | { |
520dc8e8 | 3003 | if (i.op[n].disps->X_op == O_constant) |
252b5132 | 3004 | { |
847f7ad4 AM |
3005 | int size; |
3006 | offsetT val; | |
b4cac588 | 3007 | |
847f7ad4 | 3008 | size = 4; |
3e73aa7c | 3009 | if (i.types[n] & (Disp8 | Disp16 | Disp64)) |
252b5132 | 3010 | { |
b4cac588 | 3011 | size = 2; |
b4cac588 | 3012 | if (i.types[n] & Disp8) |
847f7ad4 | 3013 | size = 1; |
3e73aa7c JH |
3014 | if (i.types[n] & Disp64) |
3015 | size = 8; | |
252b5132 | 3016 | } |
847f7ad4 AM |
3017 | val = offset_in_range (i.op[n].disps->X_add_number, |
3018 | size); | |
b4cac588 | 3019 | p = frag_more (size); |
847f7ad4 | 3020 | md_number_to_chars (p, val, size); |
252b5132 | 3021 | } |
252b5132 | 3022 | else |
520dc8e8 AM |
3023 | { |
3024 | int size = 4; | |
3e73aa7c JH |
3025 | int sign = 0; |
3026 | int pcrel = (i.flags[n] & Operand_PCrel) != 0; | |
3027 | ||
3028 | /* The PC relative address is computed relative | |
3029 | to the instruction boundary, so in case immediate | |
3030 | fields follows, we need to adjust the value. */ | |
3031 | if (pcrel && i.imm_operands) | |
3032 | { | |
3033 | int imm_size = 4; | |
3034 | register unsigned int n1; | |
3035 | ||
3036 | for (n1 = 0; n1 < i.operands; n1++) | |
3037 | if (i.types[n1] & Imm) | |
3038 | { | |
3039 | if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64)) | |
3040 | { | |
3041 | imm_size = 2; | |
3042 | if (i.types[n1] & (Imm8 | Imm8S)) | |
3043 | imm_size = 1; | |
3044 | if (i.types[n1] & Imm64) | |
3045 | imm_size = 8; | |
3046 | } | |
3047 | break; | |
3048 | } | |
3049 | /* We should find the immediate. */ | |
3050 | if (n1 == i.operands) | |
bfb32b52 | 3051 | abort (); |
3e73aa7c JH |
3052 | i.op[n].disps->X_add_number -= imm_size; |
3053 | } | |
520dc8e8 | 3054 | |
3e73aa7c JH |
3055 | if (i.types[n] & Disp32S) |
3056 | sign = 1; | |
3057 | ||
e5cb08ac | 3058 | if (i.types[n] & (Disp16 | Disp64)) |
3e73aa7c JH |
3059 | { |
3060 | size = 2; | |
3061 | if (i.types[n] & Disp64) | |
3062 | size = 8; | |
3063 | } | |
520dc8e8 | 3064 | |
520dc8e8 AM |
3065 | p = frag_more (size); |
3066 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
3e73aa7c | 3067 | i.op[n].disps, pcrel, |
1ae12ab7 | 3068 | reloc (size, pcrel, sign, i.reloc[n])); |
252b5132 RH |
3069 | } |
3070 | } | |
3071 | } | |
ce8a8b2f | 3072 | } |
252b5132 | 3073 | |
47926f60 | 3074 | /* Output immediate. */ |
252b5132 RH |
3075 | if (i.imm_operands) |
3076 | { | |
3077 | register unsigned int n; | |
3078 | ||
3079 | for (n = 0; n < i.operands; n++) | |
3080 | { | |
520dc8e8 | 3081 | if (i.types[n] & Imm) |
252b5132 | 3082 | { |
520dc8e8 | 3083 | if (i.op[n].imms->X_op == O_constant) |
252b5132 | 3084 | { |
847f7ad4 AM |
3085 | int size; |
3086 | offsetT val; | |
b4cac588 | 3087 | |
847f7ad4 | 3088 | size = 4; |
3e73aa7c | 3089 | if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64)) |
252b5132 | 3090 | { |
b4cac588 | 3091 | size = 2; |
b4cac588 | 3092 | if (i.types[n] & (Imm8 | Imm8S)) |
847f7ad4 | 3093 | size = 1; |
3e73aa7c JH |
3094 | else if (i.types[n] & Imm64) |
3095 | size = 8; | |
252b5132 | 3096 | } |
847f7ad4 AM |
3097 | val = offset_in_range (i.op[n].imms->X_add_number, |
3098 | size); | |
b4cac588 | 3099 | p = frag_more (size); |
847f7ad4 | 3100 | md_number_to_chars (p, val, size); |
252b5132 RH |
3101 | } |
3102 | else | |
ce8a8b2f AM |
3103 | { |
3104 | /* Not absolute_section. | |
3105 | Need a 32-bit fixup (don't support 8bit | |
520dc8e8 | 3106 | non-absolute imms). Try to support other |
47926f60 | 3107 | sizes ... */ |
f3c180ae | 3108 | RELOC_ENUM reloc_type; |
520dc8e8 | 3109 | int size = 4; |
3e73aa7c | 3110 | int sign = 0; |
252b5132 | 3111 | |
3e73aa7c JH |
3112 | if ((i.types[n] & (Imm32S)) |
3113 | && i.suffix == QWORD_MNEM_SUFFIX) | |
3114 | sign = 1; | |
3115 | if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64)) | |
3116 | { | |
3117 | size = 2; | |
3118 | if (i.types[n] & (Imm8 | Imm8S)) | |
3119 | size = 1; | |
3120 | if (i.types[n] & Imm64) | |
3121 | size = 8; | |
3122 | } | |
520dc8e8 | 3123 | |
252b5132 | 3124 | p = frag_more (size); |
1ae12ab7 | 3125 | reloc_type = reloc (size, 0, sign, i.reloc[n]); |
252b5132 | 3126 | #ifdef BFD_ASSEMBLER |
f6af82bd | 3127 | if (reloc_type == BFD_RELOC_32 |
252b5132 | 3128 | && GOT_symbol |
520dc8e8 AM |
3129 | && GOT_symbol == i.op[n].imms->X_add_symbol |
3130 | && (i.op[n].imms->X_op == O_symbol | |
3131 | || (i.op[n].imms->X_op == O_add | |
49309057 | 3132 | && ((symbol_get_value_expression |
520dc8e8 | 3133 | (i.op[n].imms->X_op_symbol)->X_op) |
252b5132 RH |
3134 | == O_subtract)))) |
3135 | { | |
3e73aa7c JH |
3136 | /* We don't support dynamic linking on x86-64 yet. */ |
3137 | if (flag_code == CODE_64BIT) | |
bfb32b52 | 3138 | abort (); |
f6af82bd | 3139 | reloc_type = BFD_RELOC_386_GOTPC; |
520dc8e8 | 3140 | i.op[n].imms->X_add_number += 3; |
252b5132 RH |
3141 | } |
3142 | #endif | |
3143 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
520dc8e8 | 3144 | i.op[n].imms, 0, reloc_type); |
252b5132 RH |
3145 | } |
3146 | } | |
3147 | } | |
ce8a8b2f | 3148 | } |
252b5132 RH |
3149 | } |
3150 | ||
3151 | #ifdef DEBUG386 | |
3152 | if (flag_debug) | |
3153 | { | |
3154 | pi (line, &i); | |
3155 | } | |
47926f60 | 3156 | #endif /* DEBUG386 */ |
252b5132 RH |
3157 | } |
3158 | } | |
3159 | \f | |
f3c180ae AM |
3160 | #ifndef LEX_AT |
3161 | static char *lex_got PARAMS ((RELOC_ENUM *, int *)); | |
3162 | ||
3163 | /* Parse operands of the form | |
3164 | <symbol>@GOTOFF+<nnn> | |
3165 | and similar .plt or .got references. | |
3166 | ||
3167 | If we find one, set up the correct relocation in RELOC and copy the | |
3168 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
3169 | parsing by the calling routine. Return this buffer, and if ADJUST | |
3170 | is non-null set it to the length of the string we removed from the | |
3171 | input line. Otherwise return NULL. */ | |
3172 | static char * | |
3173 | lex_got (reloc, adjust) | |
3174 | RELOC_ENUM *reloc; | |
3175 | int *adjust; | |
3176 | { | |
3177 | static const char * const mode_name[NUM_FLAG_CODE] = { "32", "16", "64" }; | |
3178 | static const struct { | |
3179 | const char *str; | |
3180 | const RELOC_ENUM rel[NUM_FLAG_CODE]; | |
3181 | } gotrel[] = { | |
3182 | { "PLT", { BFD_RELOC_386_PLT32, 0, BFD_RELOC_X86_64_PLT32 } }, | |
3183 | { "GOTOFF", { BFD_RELOC_386_GOTOFF, 0, 0 } }, | |
3184 | { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL } }, | |
3185 | { "GOT", { BFD_RELOC_386_GOT32, 0, BFD_RELOC_X86_64_GOT32 } } | |
3186 | }; | |
3187 | char *cp; | |
3188 | unsigned int j; | |
3189 | ||
3190 | for (cp = input_line_pointer; *cp != '@'; cp++) | |
3191 | if (is_end_of_line[(unsigned char) *cp]) | |
3192 | return NULL; | |
3193 | ||
3194 | for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++) | |
3195 | { | |
3196 | int len; | |
3197 | ||
3198 | len = strlen (gotrel[j].str); | |
28f81592 | 3199 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae AM |
3200 | { |
3201 | if (gotrel[j].rel[(unsigned int) flag_code] != 0) | |
3202 | { | |
28f81592 AM |
3203 | int first, second; |
3204 | char *tmpbuf, *past_reloc; | |
f3c180ae AM |
3205 | |
3206 | *reloc = gotrel[j].rel[(unsigned int) flag_code]; | |
28f81592 AM |
3207 | if (adjust) |
3208 | *adjust = len; | |
f3c180ae AM |
3209 | |
3210 | if (GOT_symbol == NULL) | |
3211 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); | |
3212 | ||
3213 | /* Replace the relocation token with ' ', so that | |
3214 | errors like foo@GOTOFF1 will be detected. */ | |
28f81592 AM |
3215 | |
3216 | /* The length of the first part of our input line. */ | |
f3c180ae | 3217 | first = cp - input_line_pointer; |
28f81592 AM |
3218 | |
3219 | /* The second part goes from after the reloc token until | |
3220 | (and including) an end_of_line char. Don't use strlen | |
3221 | here as the end_of_line char may not be a NUL. */ | |
3222 | past_reloc = cp + 1 + len; | |
3223 | for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; ) | |
3224 | ; | |
3225 | second = cp - past_reloc; | |
3226 | ||
3227 | /* Allocate and copy string. The trailing NUL shouldn't | |
3228 | be necessary, but be safe. */ | |
3229 | tmpbuf = xmalloc (first + second + 2); | |
f3c180ae AM |
3230 | memcpy (tmpbuf, input_line_pointer, first); |
3231 | tmpbuf[first] = ' '; | |
28f81592 AM |
3232 | memcpy (tmpbuf + first + 1, past_reloc, second); |
3233 | tmpbuf[first + second + 1] = '\0'; | |
f3c180ae AM |
3234 | return tmpbuf; |
3235 | } | |
3236 | ||
3237 | as_bad (_("@%s reloc is not supported in %s bit mode"), | |
3238 | gotrel[j].str, mode_name[(unsigned int) flag_code]); | |
3239 | return NULL; | |
3240 | } | |
3241 | } | |
3242 | ||
3243 | /* Might be a symbol version string. Don't as_bad here. */ | |
3244 | return NULL; | |
3245 | } | |
3246 | ||
3247 | /* x86_cons_fix_new is called via the expression parsing code when a | |
3248 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
3249 | static RELOC_ENUM got_reloc = NO_RELOC; | |
3250 | ||
3251 | void | |
3252 | x86_cons_fix_new (frag, off, len, exp) | |
3253 | fragS *frag; | |
3254 | unsigned int off; | |
3255 | unsigned int len; | |
3256 | expressionS *exp; | |
3257 | { | |
3258 | RELOC_ENUM r = reloc (len, 0, 0, got_reloc); | |
3259 | got_reloc = NO_RELOC; | |
3260 | fix_new_exp (frag, off, len, exp, 0, r); | |
3261 | } | |
3262 | ||
3263 | void | |
3264 | x86_cons (exp, size) | |
3265 | expressionS *exp; | |
3266 | int size; | |
3267 | { | |
3268 | if (size == 4) | |
3269 | { | |
3270 | /* Handle @GOTOFF and the like in an expression. */ | |
3271 | char *save; | |
3272 | char *gotfree_input_line; | |
3273 | int adjust; | |
3274 | ||
3275 | save = input_line_pointer; | |
3276 | gotfree_input_line = lex_got (&got_reloc, &adjust); | |
3277 | if (gotfree_input_line) | |
3278 | input_line_pointer = gotfree_input_line; | |
3279 | ||
3280 | expression (exp); | |
3281 | ||
3282 | if (gotfree_input_line) | |
3283 | { | |
3284 | /* expression () has merrily parsed up to the end of line, | |
3285 | or a comma - in the wrong buffer. Transfer how far | |
3286 | input_line_pointer has moved to the right buffer. */ | |
3287 | input_line_pointer = (save | |
3288 | + (input_line_pointer - gotfree_input_line) | |
3289 | + adjust); | |
3290 | free (gotfree_input_line); | |
3291 | } | |
3292 | } | |
3293 | else | |
3294 | expression (exp); | |
3295 | } | |
3296 | #endif | |
3297 | ||
252b5132 RH |
3298 | static int i386_immediate PARAMS ((char *)); |
3299 | ||
3300 | static int | |
3301 | i386_immediate (imm_start) | |
3302 | char *imm_start; | |
3303 | { | |
3304 | char *save_input_line_pointer; | |
f3c180ae AM |
3305 | #ifndef LEX_AT |
3306 | char *gotfree_input_line; | |
3307 | #endif | |
252b5132 | 3308 | segT exp_seg = 0; |
47926f60 | 3309 | expressionS *exp; |
252b5132 RH |
3310 | |
3311 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
3312 | { | |
d0b47220 | 3313 | as_bad (_("only 1 or 2 immediate operands are allowed")); |
252b5132 RH |
3314 | return 0; |
3315 | } | |
3316 | ||
3317 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 3318 | i.op[this_operand].imms = exp; |
252b5132 RH |
3319 | |
3320 | if (is_space_char (*imm_start)) | |
3321 | ++imm_start; | |
3322 | ||
3323 | save_input_line_pointer = input_line_pointer; | |
3324 | input_line_pointer = imm_start; | |
3325 | ||
3326 | #ifndef LEX_AT | |
f3c180ae AM |
3327 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL); |
3328 | if (gotfree_input_line) | |
3329 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
3330 | #endif |
3331 | ||
3332 | exp_seg = expression (exp); | |
3333 | ||
83183c0c | 3334 | SKIP_WHITESPACE (); |
252b5132 | 3335 | if (*input_line_pointer) |
f3c180ae | 3336 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
3337 | |
3338 | input_line_pointer = save_input_line_pointer; | |
f3c180ae AM |
3339 | #ifndef LEX_AT |
3340 | if (gotfree_input_line) | |
3341 | free (gotfree_input_line); | |
3342 | #endif | |
252b5132 | 3343 | |
2daf4fd8 | 3344 | if (exp->X_op == O_absent || exp->X_op == O_big) |
252b5132 | 3345 | { |
47926f60 | 3346 | /* Missing or bad expr becomes absolute 0. */ |
d0b47220 | 3347 | as_bad (_("missing or invalid immediate expression `%s' taken as 0"), |
24eab124 | 3348 | imm_start); |
252b5132 RH |
3349 | exp->X_op = O_constant; |
3350 | exp->X_add_number = 0; | |
3351 | exp->X_add_symbol = (symbolS *) 0; | |
3352 | exp->X_op_symbol = (symbolS *) 0; | |
252b5132 | 3353 | } |
3e73aa7c | 3354 | else if (exp->X_op == O_constant) |
252b5132 | 3355 | { |
47926f60 | 3356 | /* Size it properly later. */ |
3e73aa7c JH |
3357 | i.types[this_operand] |= Imm64; |
3358 | /* If BFD64, sign extend val. */ | |
3359 | if (!use_rela_relocations) | |
3360 | if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) | |
3361 | exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
252b5132 | 3362 | } |
4c63da97 | 3363 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
47926f60 | 3364 | else if (1 |
4c63da97 | 3365 | #ifdef BFD_ASSEMBLER |
47926f60 | 3366 | && OUTPUT_FLAVOR == bfd_target_aout_flavour |
4c63da97 | 3367 | #endif |
47926f60 | 3368 | && exp_seg != text_section |
24eab124 AM |
3369 | && exp_seg != data_section |
3370 | && exp_seg != bss_section | |
3371 | && exp_seg != undefined_section | |
252b5132 | 3372 | #ifdef BFD_ASSEMBLER |
24eab124 | 3373 | && !bfd_is_com_section (exp_seg) |
252b5132 | 3374 | #endif |
24eab124 | 3375 | ) |
252b5132 | 3376 | { |
4c63da97 | 3377 | #ifdef BFD_ASSEMBLER |
d0b47220 | 3378 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
4c63da97 | 3379 | #else |
d0b47220 | 3380 | as_bad (_("unimplemented segment type %d in operand"), exp_seg); |
4c63da97 | 3381 | #endif |
252b5132 RH |
3382 | return 0; |
3383 | } | |
3384 | #endif | |
3385 | else | |
3386 | { | |
3387 | /* This is an address. The size of the address will be | |
24eab124 | 3388 | determined later, depending on destination register, |
3e73aa7c JH |
3389 | suffix, or the default for the section. */ |
3390 | i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64; | |
252b5132 RH |
3391 | } |
3392 | ||
3393 | return 1; | |
3394 | } | |
3395 | ||
551c1ca1 | 3396 | static char *i386_scale PARAMS ((char *)); |
252b5132 | 3397 | |
551c1ca1 | 3398 | static char * |
252b5132 RH |
3399 | i386_scale (scale) |
3400 | char *scale; | |
3401 | { | |
551c1ca1 AM |
3402 | offsetT val; |
3403 | char *save = input_line_pointer; | |
252b5132 | 3404 | |
551c1ca1 AM |
3405 | input_line_pointer = scale; |
3406 | val = get_absolute_expression (); | |
3407 | ||
3408 | switch (val) | |
252b5132 | 3409 | { |
551c1ca1 AM |
3410 | case 0: |
3411 | case 1: | |
252b5132 RH |
3412 | i.log2_scale_factor = 0; |
3413 | break; | |
551c1ca1 | 3414 | case 2: |
252b5132 RH |
3415 | i.log2_scale_factor = 1; |
3416 | break; | |
551c1ca1 | 3417 | case 4: |
252b5132 RH |
3418 | i.log2_scale_factor = 2; |
3419 | break; | |
551c1ca1 | 3420 | case 8: |
252b5132 RH |
3421 | i.log2_scale_factor = 3; |
3422 | break; | |
3423 | default: | |
252b5132 | 3424 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), |
24eab124 | 3425 | scale); |
551c1ca1 AM |
3426 | input_line_pointer = save; |
3427 | return NULL; | |
252b5132 RH |
3428 | } |
3429 | if (i.log2_scale_factor != 0 && ! i.index_reg) | |
3430 | { | |
3431 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 3432 | 1 << i.log2_scale_factor); |
252b5132 RH |
3433 | #if SCALE1_WHEN_NO_INDEX |
3434 | i.log2_scale_factor = 0; | |
3435 | #endif | |
3436 | } | |
551c1ca1 AM |
3437 | scale = input_line_pointer; |
3438 | input_line_pointer = save; | |
3439 | return scale; | |
252b5132 RH |
3440 | } |
3441 | ||
3442 | static int i386_displacement PARAMS ((char *, char *)); | |
3443 | ||
3444 | static int | |
3445 | i386_displacement (disp_start, disp_end) | |
3446 | char *disp_start; | |
3447 | char *disp_end; | |
3448 | { | |
3449 | register expressionS *exp; | |
3450 | segT exp_seg = 0; | |
3451 | char *save_input_line_pointer; | |
f3c180ae AM |
3452 | #ifndef LEX_AT |
3453 | char *gotfree_input_line; | |
3454 | #endif | |
252b5132 RH |
3455 | int bigdisp = Disp32; |
3456 | ||
3e73aa7c | 3457 | if (flag_code == CODE_64BIT) |
7ecd2f8b JH |
3458 | { |
3459 | if (!i.prefix[ADDR_PREFIX]) | |
3460 | bigdisp = Disp64; | |
3461 | } | |
3462 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) | |
3463 | bigdisp = Disp16; | |
252b5132 RH |
3464 | i.types[this_operand] |= bigdisp; |
3465 | ||
3466 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 3467 | i.op[this_operand].disps = exp; |
252b5132 RH |
3468 | i.disp_operands++; |
3469 | save_input_line_pointer = input_line_pointer; | |
3470 | input_line_pointer = disp_start; | |
3471 | END_STRING_AND_SAVE (disp_end); | |
3472 | ||
3473 | #ifndef GCC_ASM_O_HACK | |
3474 | #define GCC_ASM_O_HACK 0 | |
3475 | #endif | |
3476 | #if GCC_ASM_O_HACK | |
3477 | END_STRING_AND_SAVE (disp_end + 1); | |
3478 | if ((i.types[this_operand] & BaseIndex) != 0 | |
24eab124 | 3479 | && displacement_string_end[-1] == '+') |
252b5132 RH |
3480 | { |
3481 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
3482 | constraint within gcc asm statements. |
3483 | For instance: | |
3484 | ||
3485 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
3486 | __asm__ __volatile__ ( \ | |
3487 | "movw %w2,%0\n\t" \ | |
3488 | "movw %w1,2+%0\n\t" \ | |
3489 | "rorl $16,%1\n\t" \ | |
3490 | "movb %b1,4+%0\n\t" \ | |
3491 | "movb %4,5+%0\n\t" \ | |
3492 | "movb $0,6+%0\n\t" \ | |
3493 | "movb %h1,7+%0\n\t" \ | |
3494 | "rorl $16,%1" \ | |
3495 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
3496 | ||
3497 | This works great except that the output assembler ends | |
3498 | up looking a bit weird if it turns out that there is | |
3499 | no offset. You end up producing code that looks like: | |
3500 | ||
3501 | #APP | |
3502 | movw $235,(%eax) | |
3503 | movw %dx,2+(%eax) | |
3504 | rorl $16,%edx | |
3505 | movb %dl,4+(%eax) | |
3506 | movb $137,5+(%eax) | |
3507 | movb $0,6+(%eax) | |
3508 | movb %dh,7+(%eax) | |
3509 | rorl $16,%edx | |
3510 | #NO_APP | |
3511 | ||
47926f60 | 3512 | So here we provide the missing zero. */ |
24eab124 AM |
3513 | |
3514 | *displacement_string_end = '0'; | |
252b5132 RH |
3515 | } |
3516 | #endif | |
3517 | #ifndef LEX_AT | |
f3c180ae AM |
3518 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL); |
3519 | if (gotfree_input_line) | |
3520 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
3521 | #endif |
3522 | ||
24eab124 | 3523 | exp_seg = expression (exp); |
252b5132 | 3524 | |
636c26b0 AM |
3525 | SKIP_WHITESPACE (); |
3526 | if (*input_line_pointer) | |
3527 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
3528 | #if GCC_ASM_O_HACK | |
3529 | RESTORE_END_STRING (disp_end + 1); | |
3530 | #endif | |
3531 | RESTORE_END_STRING (disp_end); | |
3532 | input_line_pointer = save_input_line_pointer; | |
3533 | #ifndef LEX_AT | |
3534 | if (gotfree_input_line) | |
3535 | free (gotfree_input_line); | |
3536 | #endif | |
3537 | ||
252b5132 | 3538 | #ifdef BFD_ASSEMBLER |
24eab124 AM |
3539 | /* We do this to make sure that the section symbol is in |
3540 | the symbol table. We will ultimately change the relocation | |
47926f60 | 3541 | to be relative to the beginning of the section. */ |
1ae12ab7 AM |
3542 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
3543 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) | |
24eab124 | 3544 | { |
636c26b0 AM |
3545 | if (exp->X_op != O_symbol) |
3546 | { | |
3547 | as_bad (_("bad expression used with @%s"), | |
3548 | (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL | |
3549 | ? "GOTPCREL" | |
3550 | : "GOTOFF")); | |
3551 | return 0; | |
3552 | } | |
3553 | ||
e5cb08ac | 3554 | if (S_IS_LOCAL (exp->X_add_symbol) |
24eab124 AM |
3555 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section) |
3556 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); | |
24eab124 AM |
3557 | exp->X_op = O_subtract; |
3558 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 AM |
3559 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
3560 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; | |
23df1078 | 3561 | else |
1ae12ab7 | 3562 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 3563 | } |
252b5132 RH |
3564 | #endif |
3565 | ||
2daf4fd8 AM |
3566 | if (exp->X_op == O_absent || exp->X_op == O_big) |
3567 | { | |
47926f60 | 3568 | /* Missing or bad expr becomes absolute 0. */ |
d0b47220 | 3569 | as_bad (_("missing or invalid displacement expression `%s' taken as 0"), |
2daf4fd8 AM |
3570 | disp_start); |
3571 | exp->X_op = O_constant; | |
3572 | exp->X_add_number = 0; | |
3573 | exp->X_add_symbol = (symbolS *) 0; | |
3574 | exp->X_op_symbol = (symbolS *) 0; | |
3575 | } | |
3576 | ||
4c63da97 | 3577 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
45288df1 | 3578 | if (exp->X_op != O_constant |
4c63da97 | 3579 | #ifdef BFD_ASSEMBLER |
45288df1 | 3580 | && OUTPUT_FLAVOR == bfd_target_aout_flavour |
4c63da97 | 3581 | #endif |
45288df1 AM |
3582 | && exp_seg != text_section |
3583 | && exp_seg != data_section | |
3584 | && exp_seg != bss_section | |
3585 | && exp_seg != undefined_section) | |
24eab124 | 3586 | { |
4c63da97 | 3587 | #ifdef BFD_ASSEMBLER |
d0b47220 | 3588 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
4c63da97 | 3589 | #else |
d0b47220 | 3590 | as_bad (_("unimplemented segment type %d in operand"), exp_seg); |
4c63da97 | 3591 | #endif |
24eab124 AM |
3592 | return 0; |
3593 | } | |
252b5132 | 3594 | #endif |
3e73aa7c JH |
3595 | else if (flag_code == CODE_64BIT) |
3596 | i.types[this_operand] |= Disp32S | Disp32; | |
252b5132 RH |
3597 | return 1; |
3598 | } | |
3599 | ||
e5cb08ac | 3600 | static int i386_index_check PARAMS ((const char *)); |
252b5132 | 3601 | |
eecb386c | 3602 | /* Make sure the memory operand we've been dealt is valid. |
47926f60 KH |
3603 | Return 1 on success, 0 on a failure. */ |
3604 | ||
252b5132 | 3605 | static int |
eecb386c AM |
3606 | i386_index_check (operand_string) |
3607 | const char *operand_string; | |
252b5132 | 3608 | { |
3e73aa7c | 3609 | int ok; |
24eab124 | 3610 | #if INFER_ADDR_PREFIX |
eecb386c AM |
3611 | int fudged = 0; |
3612 | ||
24eab124 AM |
3613 | tryprefix: |
3614 | #endif | |
3e73aa7c JH |
3615 | ok = 1; |
3616 | if (flag_code == CODE_64BIT) | |
3617 | { | |
7ecd2f8b JH |
3618 | if (i.prefix[ADDR_PREFIX] == 0) |
3619 | { | |
3620 | /* 64bit checks. */ | |
3621 | if ((i.base_reg | |
3622 | && ((i.base_reg->reg_type & Reg64) == 0) | |
3623 | && (i.base_reg->reg_type != BaseIndex | |
3624 | || i.index_reg)) | |
3625 | || (i.index_reg | |
3626 | && ((i.index_reg->reg_type & (Reg64|BaseIndex)) | |
3627 | != (Reg64|BaseIndex)))) | |
3628 | ok = 0; | |
3629 | } | |
3630 | else | |
3631 | { | |
3632 | /* 32bit checks. */ | |
3633 | if ((i.base_reg | |
3634 | && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32) | |
3635 | || (i.index_reg | |
3636 | && ((i.index_reg->reg_type & (Reg32|BaseIndex|RegRex)) | |
3637 | != (Reg32|BaseIndex)))) | |
3638 | ok = 0; | |
3639 | } | |
3e73aa7c JH |
3640 | } |
3641 | else | |
3642 | { | |
3643 | if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) | |
3644 | { | |
3645 | /* 16bit checks. */ | |
3646 | if ((i.base_reg | |
3647 | && ((i.base_reg->reg_type & (Reg16|BaseIndex|RegRex)) | |
3648 | != (Reg16|BaseIndex))) | |
3649 | || (i.index_reg | |
3650 | && (((i.index_reg->reg_type & (Reg16|BaseIndex)) | |
3651 | != (Reg16|BaseIndex)) | |
3652 | || ! (i.base_reg | |
3653 | && i.base_reg->reg_num < 6 | |
3654 | && i.index_reg->reg_num >= 6 | |
3655 | && i.log2_scale_factor == 0)))) | |
3656 | ok = 0; | |
3657 | } | |
3658 | else | |
e5cb08ac | 3659 | { |
3e73aa7c JH |
3660 | /* 32bit checks. */ |
3661 | if ((i.base_reg | |
3662 | && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32) | |
3663 | || (i.index_reg | |
3664 | && ((i.index_reg->reg_type & (Reg32|BaseIndex|RegRex)) | |
3665 | != (Reg32|BaseIndex)))) | |
e5cb08ac | 3666 | ok = 0; |
3e73aa7c JH |
3667 | } |
3668 | } | |
3669 | if (!ok) | |
24eab124 AM |
3670 | { |
3671 | #if INFER_ADDR_PREFIX | |
3e73aa7c JH |
3672 | if (flag_code != CODE_64BIT |
3673 | && i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0') | |
24eab124 AM |
3674 | { |
3675 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
3676 | i.prefixes += 1; | |
b23bac36 AM |
3677 | /* Change the size of any displacement too. At most one of |
3678 | Disp16 or Disp32 is set. | |
3679 | FIXME. There doesn't seem to be any real need for separate | |
3680 | Disp16 and Disp32 flags. The same goes for Imm16 and Imm32. | |
47926f60 | 3681 | Removing them would probably clean up the code quite a lot. */ |
b23bac36 AM |
3682 | if (i.types[this_operand] & (Disp16|Disp32)) |
3683 | i.types[this_operand] ^= (Disp16|Disp32); | |
eecb386c | 3684 | fudged = 1; |
24eab124 AM |
3685 | goto tryprefix; |
3686 | } | |
eecb386c AM |
3687 | if (fudged) |
3688 | as_bad (_("`%s' is not a valid base/index expression"), | |
3689 | operand_string); | |
3690 | else | |
c388dee8 | 3691 | #endif |
eecb386c AM |
3692 | as_bad (_("`%s' is not a valid %s bit base/index expression"), |
3693 | operand_string, | |
3e73aa7c | 3694 | flag_code_names[flag_code]); |
eecb386c | 3695 | return 0; |
24eab124 AM |
3696 | } |
3697 | return 1; | |
3698 | } | |
252b5132 | 3699 | |
252b5132 | 3700 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero |
47926f60 | 3701 | on error. */ |
252b5132 | 3702 | |
252b5132 RH |
3703 | static int |
3704 | i386_operand (operand_string) | |
3705 | char *operand_string; | |
3706 | { | |
af6bdddf AM |
3707 | const reg_entry *r; |
3708 | char *end_op; | |
24eab124 | 3709 | char *op_string = operand_string; |
252b5132 | 3710 | |
24eab124 | 3711 | if (is_space_char (*op_string)) |
252b5132 RH |
3712 | ++op_string; |
3713 | ||
24eab124 | 3714 | /* We check for an absolute prefix (differentiating, |
47926f60 | 3715 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
3716 | if (*op_string == ABSOLUTE_PREFIX) |
3717 | { | |
3718 | ++op_string; | |
3719 | if (is_space_char (*op_string)) | |
3720 | ++op_string; | |
3721 | i.types[this_operand] |= JumpAbsolute; | |
3722 | } | |
252b5132 | 3723 | |
47926f60 | 3724 | /* Check if operand is a register. */ |
af6bdddf AM |
3725 | if ((*op_string == REGISTER_PREFIX || allow_naked_reg) |
3726 | && (r = parse_register (op_string, &end_op)) != NULL) | |
24eab124 | 3727 | { |
24eab124 AM |
3728 | /* Check for a segment override by searching for ':' after a |
3729 | segment register. */ | |
3730 | op_string = end_op; | |
3731 | if (is_space_char (*op_string)) | |
3732 | ++op_string; | |
3733 | if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3))) | |
3734 | { | |
3735 | switch (r->reg_num) | |
3736 | { | |
3737 | case 0: | |
3738 | i.seg[i.mem_operands] = &es; | |
3739 | break; | |
3740 | case 1: | |
3741 | i.seg[i.mem_operands] = &cs; | |
3742 | break; | |
3743 | case 2: | |
3744 | i.seg[i.mem_operands] = &ss; | |
3745 | break; | |
3746 | case 3: | |
3747 | i.seg[i.mem_operands] = &ds; | |
3748 | break; | |
3749 | case 4: | |
3750 | i.seg[i.mem_operands] = &fs; | |
3751 | break; | |
3752 | case 5: | |
3753 | i.seg[i.mem_operands] = &gs; | |
3754 | break; | |
3755 | } | |
252b5132 | 3756 | |
24eab124 | 3757 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
3758 | ++op_string; |
3759 | if (is_space_char (*op_string)) | |
24eab124 | 3760 | ++op_string; |
252b5132 | 3761 | |
24eab124 AM |
3762 | if (!is_digit_char (*op_string) |
3763 | && !is_identifier_char (*op_string) | |
3764 | && *op_string != '(' | |
3765 | && *op_string != ABSOLUTE_PREFIX) | |
3766 | { | |
3767 | as_bad (_("bad memory operand `%s'"), op_string); | |
3768 | return 0; | |
3769 | } | |
47926f60 | 3770 | /* Handle case of %es:*foo. */ |
24eab124 AM |
3771 | if (*op_string == ABSOLUTE_PREFIX) |
3772 | { | |
3773 | ++op_string; | |
3774 | if (is_space_char (*op_string)) | |
3775 | ++op_string; | |
3776 | i.types[this_operand] |= JumpAbsolute; | |
3777 | } | |
3778 | goto do_memory_reference; | |
3779 | } | |
3780 | if (*op_string) | |
3781 | { | |
d0b47220 | 3782 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
3783 | return 0; |
3784 | } | |
3785 | i.types[this_operand] |= r->reg_type & ~BaseIndex; | |
520dc8e8 | 3786 | i.op[this_operand].regs = r; |
24eab124 AM |
3787 | i.reg_operands++; |
3788 | } | |
af6bdddf AM |
3789 | else if (*op_string == REGISTER_PREFIX) |
3790 | { | |
3791 | as_bad (_("bad register name `%s'"), op_string); | |
3792 | return 0; | |
3793 | } | |
24eab124 | 3794 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 3795 | { |
24eab124 AM |
3796 | ++op_string; |
3797 | if (i.types[this_operand] & JumpAbsolute) | |
3798 | { | |
d0b47220 | 3799 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
3800 | return 0; |
3801 | } | |
3802 | if (!i386_immediate (op_string)) | |
3803 | return 0; | |
3804 | } | |
3805 | else if (is_digit_char (*op_string) | |
3806 | || is_identifier_char (*op_string) | |
e5cb08ac | 3807 | || *op_string == '(') |
24eab124 | 3808 | { |
47926f60 | 3809 | /* This is a memory reference of some sort. */ |
af6bdddf | 3810 | char *base_string; |
252b5132 | 3811 | |
47926f60 | 3812 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
3813 | char *displacement_string_start; |
3814 | char *displacement_string_end; | |
252b5132 | 3815 | |
24eab124 | 3816 | do_memory_reference: |
24eab124 AM |
3817 | if ((i.mem_operands == 1 |
3818 | && (current_templates->start->opcode_modifier & IsString) == 0) | |
3819 | || i.mem_operands == 2) | |
3820 | { | |
3821 | as_bad (_("too many memory references for `%s'"), | |
3822 | current_templates->start->name); | |
3823 | return 0; | |
3824 | } | |
252b5132 | 3825 | |
24eab124 AM |
3826 | /* Check for base index form. We detect the base index form by |
3827 | looking for an ')' at the end of the operand, searching | |
3828 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
3829 | after the '('. */ | |
af6bdddf | 3830 | base_string = op_string + strlen (op_string); |
c3332e24 | 3831 | |
af6bdddf AM |
3832 | --base_string; |
3833 | if (is_space_char (*base_string)) | |
3834 | --base_string; | |
252b5132 | 3835 | |
47926f60 | 3836 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
3837 | displacement_string_start = op_string; |
3838 | displacement_string_end = base_string + 1; | |
252b5132 | 3839 | |
24eab124 AM |
3840 | if (*base_string == ')') |
3841 | { | |
af6bdddf | 3842 | char *temp_string; |
24eab124 AM |
3843 | unsigned int parens_balanced = 1; |
3844 | /* We've already checked that the number of left & right ()'s are | |
47926f60 | 3845 | equal, so this loop will not be infinite. */ |
24eab124 AM |
3846 | do |
3847 | { | |
3848 | base_string--; | |
3849 | if (*base_string == ')') | |
3850 | parens_balanced++; | |
3851 | if (*base_string == '(') | |
3852 | parens_balanced--; | |
3853 | } | |
3854 | while (parens_balanced); | |
c3332e24 | 3855 | |
af6bdddf | 3856 | temp_string = base_string; |
c3332e24 | 3857 | |
24eab124 | 3858 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
3859 | ++base_string; |
3860 | if (is_space_char (*base_string)) | |
24eab124 | 3861 | ++base_string; |
252b5132 | 3862 | |
af6bdddf AM |
3863 | if (*base_string == ',' |
3864 | || ((*base_string == REGISTER_PREFIX || allow_naked_reg) | |
3865 | && (i.base_reg = parse_register (base_string, &end_op)) != NULL)) | |
252b5132 | 3866 | { |
af6bdddf | 3867 | displacement_string_end = temp_string; |
252b5132 | 3868 | |
af6bdddf | 3869 | i.types[this_operand] |= BaseIndex; |
252b5132 | 3870 | |
af6bdddf | 3871 | if (i.base_reg) |
24eab124 | 3872 | { |
24eab124 AM |
3873 | base_string = end_op; |
3874 | if (is_space_char (*base_string)) | |
3875 | ++base_string; | |
af6bdddf AM |
3876 | } |
3877 | ||
3878 | /* There may be an index reg or scale factor here. */ | |
3879 | if (*base_string == ',') | |
3880 | { | |
3881 | ++base_string; | |
3882 | if (is_space_char (*base_string)) | |
3883 | ++base_string; | |
3884 | ||
3885 | if ((*base_string == REGISTER_PREFIX || allow_naked_reg) | |
3886 | && (i.index_reg = parse_register (base_string, &end_op)) != NULL) | |
24eab124 | 3887 | { |
af6bdddf | 3888 | base_string = end_op; |
24eab124 AM |
3889 | if (is_space_char (*base_string)) |
3890 | ++base_string; | |
af6bdddf AM |
3891 | if (*base_string == ',') |
3892 | { | |
3893 | ++base_string; | |
3894 | if (is_space_char (*base_string)) | |
3895 | ++base_string; | |
3896 | } | |
e5cb08ac | 3897 | else if (*base_string != ')') |
af6bdddf AM |
3898 | { |
3899 | as_bad (_("expecting `,' or `)' after index register in `%s'"), | |
3900 | operand_string); | |
3901 | return 0; | |
3902 | } | |
24eab124 | 3903 | } |
af6bdddf | 3904 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 3905 | { |
af6bdddf | 3906 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
3907 | return 0; |
3908 | } | |
252b5132 | 3909 | |
47926f60 | 3910 | /* Check for scale factor. */ |
551c1ca1 | 3911 | if (*base_string != ')') |
af6bdddf | 3912 | { |
551c1ca1 AM |
3913 | char *end_scale = i386_scale (base_string); |
3914 | ||
3915 | if (!end_scale) | |
af6bdddf | 3916 | return 0; |
24eab124 | 3917 | |
551c1ca1 | 3918 | base_string = end_scale; |
af6bdddf AM |
3919 | if (is_space_char (*base_string)) |
3920 | ++base_string; | |
3921 | if (*base_string != ')') | |
3922 | { | |
3923 | as_bad (_("expecting `)' after scale factor in `%s'"), | |
3924 | operand_string); | |
3925 | return 0; | |
3926 | } | |
3927 | } | |
3928 | else if (!i.index_reg) | |
24eab124 | 3929 | { |
af6bdddf AM |
3930 | as_bad (_("expecting index register or scale factor after `,'; got '%c'"), |
3931 | *base_string); | |
24eab124 AM |
3932 | return 0; |
3933 | } | |
3934 | } | |
af6bdddf | 3935 | else if (*base_string != ')') |
24eab124 | 3936 | { |
af6bdddf AM |
3937 | as_bad (_("expecting `,' or `)' after base register in `%s'"), |
3938 | operand_string); | |
24eab124 AM |
3939 | return 0; |
3940 | } | |
c3332e24 | 3941 | } |
af6bdddf | 3942 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 3943 | { |
af6bdddf | 3944 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 3945 | return 0; |
c3332e24 | 3946 | } |
24eab124 AM |
3947 | } |
3948 | ||
3949 | /* If there's an expression beginning the operand, parse it, | |
3950 | assuming displacement_string_start and | |
3951 | displacement_string_end are meaningful. */ | |
3952 | if (displacement_string_start != displacement_string_end) | |
3953 | { | |
3954 | if (!i386_displacement (displacement_string_start, | |
3955 | displacement_string_end)) | |
3956 | return 0; | |
3957 | } | |
3958 | ||
3959 | /* Special case for (%dx) while doing input/output op. */ | |
3960 | if (i.base_reg | |
3961 | && i.base_reg->reg_type == (Reg16 | InOutPortReg) | |
3962 | && i.index_reg == 0 | |
3963 | && i.log2_scale_factor == 0 | |
3964 | && i.seg[i.mem_operands] == 0 | |
3965 | && (i.types[this_operand] & Disp) == 0) | |
3966 | { | |
3967 | i.types[this_operand] = InOutPortReg; | |
3968 | return 1; | |
3969 | } | |
3970 | ||
eecb386c AM |
3971 | if (i386_index_check (operand_string) == 0) |
3972 | return 0; | |
24eab124 AM |
3973 | i.mem_operands++; |
3974 | } | |
3975 | else | |
ce8a8b2f AM |
3976 | { |
3977 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
3978 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
3979 | output_invalid (*op_string), | |
3980 | this_operand + 1, | |
3981 | op_string); | |
3982 | return 0; | |
3983 | } | |
47926f60 | 3984 | return 1; /* Normal return. */ |
252b5132 RH |
3985 | } |
3986 | \f | |
ee7fcc42 AM |
3987 | /* md_estimate_size_before_relax() |
3988 | ||
3989 | Called just before relax() for rs_machine_dependent frags. The x86 | |
3990 | assembler uses these frags to handle variable size jump | |
3991 | instructions. | |
3992 | ||
3993 | Any symbol that is now undefined will not become defined. | |
3994 | Return the correct fr_subtype in the frag. | |
3995 | Return the initial "guess for variable size of frag" to caller. | |
3996 | The guess is actually the growth beyond the fixed part. Whatever | |
3997 | we do to grow the fixed or variable part contributes to our | |
3998 | returned value. */ | |
3999 | ||
252b5132 RH |
4000 | int |
4001 | md_estimate_size_before_relax (fragP, segment) | |
4002 | register fragS *fragP; | |
4003 | register segT segment; | |
4004 | { | |
252b5132 | 4005 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
4006 | check for un-relaxable symbols. On an ELF system, we can't relax |
4007 | an externally visible symbol, because it may be overridden by a | |
4008 | shared library. */ | |
4009 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 4010 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
b98ef147 AM |
4011 | || S_IS_EXTERNAL (fragP->fr_symbol) |
4012 | || S_IS_WEAK (fragP->fr_symbol) | |
4013 | #endif | |
4014 | ) | |
252b5132 | 4015 | { |
b98ef147 AM |
4016 | /* Symbol is undefined in this segment, or we need to keep a |
4017 | reloc so that weak symbols can be overridden. */ | |
4018 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f3c180ae | 4019 | RELOC_ENUM reloc_type; |
ee7fcc42 AM |
4020 | unsigned char *opcode; |
4021 | int old_fr_fix; | |
f6af82bd | 4022 | |
ee7fcc42 AM |
4023 | if (fragP->fr_var != NO_RELOC) |
4024 | reloc_type = fragP->fr_var; | |
b98ef147 | 4025 | else if (size == 2) |
f6af82bd AM |
4026 | reloc_type = BFD_RELOC_16_PCREL; |
4027 | else | |
4028 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 4029 | |
ee7fcc42 AM |
4030 | old_fr_fix = fragP->fr_fix; |
4031 | opcode = (unsigned char *) fragP->fr_opcode; | |
4032 | ||
fddf5b5b | 4033 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 4034 | { |
fddf5b5b AM |
4035 | case UNCOND_JUMP: |
4036 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 4037 | opcode[0] = 0xe9; |
252b5132 RH |
4038 | fragP->fr_fix += size; |
4039 | fix_new (fragP, old_fr_fix, size, | |
4040 | fragP->fr_symbol, | |
4041 | fragP->fr_offset, 1, | |
f6af82bd | 4042 | reloc_type); |
252b5132 RH |
4043 | break; |
4044 | ||
fddf5b5b AM |
4045 | case COND_JUMP86: |
4046 | if (no_cond_jump_promotion) | |
93c2a809 AM |
4047 | goto relax_guess; |
4048 | ||
fddf5b5b AM |
4049 | if (size == 2) |
4050 | { | |
4051 | /* Negate the condition, and branch past an | |
4052 | unconditional jump. */ | |
4053 | opcode[0] ^= 1; | |
4054 | opcode[1] = 3; | |
4055 | /* Insert an unconditional jump. */ | |
4056 | opcode[2] = 0xe9; | |
4057 | /* We added two extra opcode bytes, and have a two byte | |
4058 | offset. */ | |
4059 | fragP->fr_fix += 2 + 2; | |
4060 | fix_new (fragP, old_fr_fix + 2, 2, | |
4061 | fragP->fr_symbol, | |
4062 | fragP->fr_offset, 1, | |
4063 | reloc_type); | |
4064 | break; | |
4065 | } | |
4066 | /* Fall through. */ | |
4067 | ||
4068 | case COND_JUMP: | |
4069 | if (no_cond_jump_promotion) | |
93c2a809 AM |
4070 | goto relax_guess; |
4071 | ||
24eab124 | 4072 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 4073 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 4074 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 4075 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
4076 | /* We've added an opcode byte. */ |
4077 | fragP->fr_fix += 1 + size; | |
252b5132 RH |
4078 | fix_new (fragP, old_fr_fix + 1, size, |
4079 | fragP->fr_symbol, | |
4080 | fragP->fr_offset, 1, | |
f6af82bd | 4081 | reloc_type); |
252b5132 | 4082 | break; |
fddf5b5b AM |
4083 | |
4084 | default: | |
4085 | BAD_CASE (fragP->fr_subtype); | |
4086 | break; | |
252b5132 RH |
4087 | } |
4088 | frag_wane (fragP); | |
ee7fcc42 | 4089 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 4090 | } |
93c2a809 AM |
4091 | |
4092 | relax_guess: | |
4093 | /* Guess size depending on current relax state. Initially the relax | |
4094 | state will correspond to a short jump and we return 1, because | |
4095 | the variable part of the frag (the branch offset) is one byte | |
4096 | long. However, we can relax a section more than once and in that | |
4097 | case we must either set fr_subtype back to the unrelaxed state, | |
4098 | or return the value for the appropriate branch. */ | |
4099 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
4100 | } |
4101 | ||
47926f60 KH |
4102 | /* Called after relax() is finished. |
4103 | ||
4104 | In: Address of frag. | |
4105 | fr_type == rs_machine_dependent. | |
4106 | fr_subtype is what the address relaxed to. | |
4107 | ||
4108 | Out: Any fixSs and constants are set up. | |
4109 | Caller will turn frag into a ".space 0". */ | |
4110 | ||
252b5132 RH |
4111 | #ifndef BFD_ASSEMBLER |
4112 | void | |
4113 | md_convert_frag (headers, sec, fragP) | |
a04b544b ILT |
4114 | object_headers *headers ATTRIBUTE_UNUSED; |
4115 | segT sec ATTRIBUTE_UNUSED; | |
252b5132 RH |
4116 | register fragS *fragP; |
4117 | #else | |
4118 | void | |
4119 | md_convert_frag (abfd, sec, fragP) | |
ab9da554 ILT |
4120 | bfd *abfd ATTRIBUTE_UNUSED; |
4121 | segT sec ATTRIBUTE_UNUSED; | |
252b5132 RH |
4122 | register fragS *fragP; |
4123 | #endif | |
4124 | { | |
4125 | register unsigned char *opcode; | |
4126 | unsigned char *where_to_put_displacement = NULL; | |
847f7ad4 AM |
4127 | offsetT target_address; |
4128 | offsetT opcode_address; | |
252b5132 | 4129 | unsigned int extension = 0; |
847f7ad4 | 4130 | offsetT displacement_from_opcode_start; |
252b5132 RH |
4131 | |
4132 | opcode = (unsigned char *) fragP->fr_opcode; | |
4133 | ||
47926f60 | 4134 | /* Address we want to reach in file space. */ |
252b5132 | 4135 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 4136 | |
47926f60 | 4137 | /* Address opcode resides at in file space. */ |
252b5132 RH |
4138 | opcode_address = fragP->fr_address + fragP->fr_fix; |
4139 | ||
47926f60 | 4140 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
4141 | displacement_from_opcode_start = target_address - opcode_address; |
4142 | ||
fddf5b5b | 4143 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 4144 | { |
47926f60 KH |
4145 | /* Don't have to change opcode. */ |
4146 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 4147 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
4148 | } |
4149 | else | |
4150 | { | |
4151 | if (no_cond_jump_promotion | |
4152 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4153 | as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required")); | |
252b5132 | 4154 | |
fddf5b5b AM |
4155 | switch (fragP->fr_subtype) |
4156 | { | |
4157 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
4158 | extension = 4; /* 1 opcode + 4 displacement */ | |
4159 | opcode[0] = 0xe9; | |
4160 | where_to_put_displacement = &opcode[1]; | |
4161 | break; | |
252b5132 | 4162 | |
fddf5b5b AM |
4163 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
4164 | extension = 2; /* 1 opcode + 2 displacement */ | |
4165 | opcode[0] = 0xe9; | |
4166 | where_to_put_displacement = &opcode[1]; | |
4167 | break; | |
252b5132 | 4168 | |
fddf5b5b AM |
4169 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
4170 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
4171 | extension = 5; /* 2 opcode + 4 displacement */ | |
4172 | opcode[1] = opcode[0] + 0x10; | |
4173 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
4174 | where_to_put_displacement = &opcode[2]; | |
4175 | break; | |
252b5132 | 4176 | |
fddf5b5b AM |
4177 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
4178 | extension = 3; /* 2 opcode + 2 displacement */ | |
4179 | opcode[1] = opcode[0] + 0x10; | |
4180 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
4181 | where_to_put_displacement = &opcode[2]; | |
4182 | break; | |
252b5132 | 4183 | |
fddf5b5b AM |
4184 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
4185 | extension = 4; | |
4186 | opcode[0] ^= 1; | |
4187 | opcode[1] = 3; | |
4188 | opcode[2] = 0xe9; | |
4189 | where_to_put_displacement = &opcode[3]; | |
4190 | break; | |
4191 | ||
4192 | default: | |
4193 | BAD_CASE (fragP->fr_subtype); | |
4194 | break; | |
4195 | } | |
252b5132 | 4196 | } |
fddf5b5b | 4197 | |
47926f60 | 4198 | /* Now put displacement after opcode. */ |
252b5132 RH |
4199 | md_number_to_chars ((char *) where_to_put_displacement, |
4200 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 4201 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
4202 | fragP->fr_fix += extension; |
4203 | } | |
4204 | \f | |
47926f60 KH |
4205 | /* Size of byte displacement jmp. */ |
4206 | int md_short_jump_size = 2; | |
4207 | ||
4208 | /* Size of dword displacement jmp. */ | |
4209 | int md_long_jump_size = 5; | |
252b5132 | 4210 | |
47926f60 KH |
4211 | /* Size of relocation record. */ |
4212 | const int md_reloc_size = 8; | |
252b5132 RH |
4213 | |
4214 | void | |
4215 | md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol) | |
4216 | char *ptr; | |
4217 | addressT from_addr, to_addr; | |
ab9da554 ILT |
4218 | fragS *frag ATTRIBUTE_UNUSED; |
4219 | symbolS *to_symbol ATTRIBUTE_UNUSED; | |
252b5132 | 4220 | { |
847f7ad4 | 4221 | offsetT offset; |
252b5132 RH |
4222 | |
4223 | offset = to_addr - (from_addr + 2); | |
47926f60 KH |
4224 | /* Opcode for byte-disp jump. */ |
4225 | md_number_to_chars (ptr, (valueT) 0xeb, 1); | |
252b5132 RH |
4226 | md_number_to_chars (ptr + 1, (valueT) offset, 1); |
4227 | } | |
4228 | ||
4229 | void | |
4230 | md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol) | |
4231 | char *ptr; | |
4232 | addressT from_addr, to_addr; | |
a38cf1db AM |
4233 | fragS *frag ATTRIBUTE_UNUSED; |
4234 | symbolS *to_symbol ATTRIBUTE_UNUSED; | |
252b5132 | 4235 | { |
847f7ad4 | 4236 | offsetT offset; |
252b5132 | 4237 | |
a38cf1db AM |
4238 | offset = to_addr - (from_addr + 5); |
4239 | md_number_to_chars (ptr, (valueT) 0xe9, 1); | |
4240 | md_number_to_chars (ptr + 1, (valueT) offset, 4); | |
252b5132 RH |
4241 | } |
4242 | \f | |
4243 | /* Apply a fixup (fixS) to segment data, once it has been determined | |
4244 | by our caller that we have all the info we need to fix it up. | |
4245 | ||
4246 | On the 386, immediates, displacements, and data pointers are all in | |
4247 | the same (little-endian) format, so we don't need to care about which | |
4248 | we are handling. */ | |
4249 | ||
94f592af NC |
4250 | void |
4251 | md_apply_fix3 (fixP, valP, seg) | |
47926f60 KH |
4252 | /* The fix we're to put in. */ |
4253 | fixS *fixP; | |
47926f60 | 4254 | /* Pointer to the value of the bits. */ |
94f592af | 4255 | valueT * valP; |
47926f60 KH |
4256 | /* Segment fix is from. */ |
4257 | segT seg ATTRIBUTE_UNUSED; | |
252b5132 | 4258 | { |
94f592af NC |
4259 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
4260 | valueT value = * valP; | |
252b5132 | 4261 | |
e1b283bb | 4262 | #if defined (BFD_ASSEMBLER) && !defined (TE_Mach) |
93382f6d AM |
4263 | if (fixP->fx_pcrel) |
4264 | { | |
4265 | switch (fixP->fx_r_type) | |
4266 | { | |
5865bb77 ILT |
4267 | default: |
4268 | break; | |
4269 | ||
93382f6d AM |
4270 | case BFD_RELOC_32: |
4271 | fixP->fx_r_type = BFD_RELOC_32_PCREL; | |
4272 | break; | |
4273 | case BFD_RELOC_16: | |
4274 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
4275 | break; | |
4276 | case BFD_RELOC_8: | |
4277 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
4278 | break; | |
4279 | } | |
4280 | } | |
252b5132 | 4281 | |
0723899b ILT |
4282 | /* This is a hack. There should be a better way to handle this. |
4283 | This covers for the fact that bfd_install_relocation will | |
4284 | subtract the current location (for partial_inplace, PC relative | |
4285 | relocations); see more below. */ | |
93382f6d AM |
4286 | if ((fixP->fx_r_type == BFD_RELOC_32_PCREL |
4287 | || fixP->fx_r_type == BFD_RELOC_16_PCREL | |
4288 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) | |
7c44d1d3 | 4289 | && fixP->fx_addsy && !use_rela_relocations) |
252b5132 RH |
4290 | { |
4291 | #ifndef OBJ_AOUT | |
4292 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
4293 | #ifdef TE_PE | |
4294 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
4295 | #endif | |
4296 | ) | |
4297 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
4298 | #endif | |
4299 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2f66722d | 4300 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
252b5132 | 4301 | { |
2f66722d AM |
4302 | segT fseg = S_GET_SEGMENT (fixP->fx_addsy); |
4303 | ||
4304 | if ((fseg == seg | |
4305 | || (symbol_section_p (fixP->fx_addsy) | |
4306 | && fseg != absolute_section)) | |
4307 | && ! S_IS_EXTERNAL (fixP->fx_addsy) | |
4308 | && ! S_IS_WEAK (fixP->fx_addsy) | |
4309 | && S_IS_DEFINED (fixP->fx_addsy) | |
4310 | && ! S_IS_COMMON (fixP->fx_addsy)) | |
4311 | { | |
4312 | /* Yes, we add the values in twice. This is because | |
4313 | bfd_perform_relocation subtracts them out again. I think | |
4314 | bfd_perform_relocation is broken, but I don't dare change | |
4315 | it. FIXME. */ | |
4316 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
4317 | } | |
252b5132 RH |
4318 | } |
4319 | #endif | |
4320 | #if defined (OBJ_COFF) && defined (TE_PE) | |
4321 | /* For some reason, the PE format does not store a section | |
24eab124 | 4322 | address offset for a PC relative symbol. */ |
252b5132 RH |
4323 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg) |
4324 | value += md_pcrel_from (fixP); | |
4325 | #endif | |
4326 | } | |
4327 | ||
4328 | /* Fix a few things - the dynamic linker expects certain values here, | |
47926f60 | 4329 | and we must not dissappoint it. */ |
252b5132 RH |
4330 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
4331 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
4332 | && fixP->fx_addsy) | |
47926f60 KH |
4333 | switch (fixP->fx_r_type) |
4334 | { | |
4335 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 4336 | case BFD_RELOC_X86_64_PLT32: |
47926f60 KH |
4337 | /* Make the jump instruction point to the address of the operand. At |
4338 | runtime we merely add the offset to the actual PLT entry. */ | |
4339 | value = -4; | |
4340 | break; | |
4341 | case BFD_RELOC_386_GOTPC: | |
4342 | ||
4343 | /* This is tough to explain. We end up with this one if we have | |
252b5132 RH |
4344 | * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal |
4345 | * here is to obtain the absolute address of the GOT, and it is strongly | |
4346 | * preferable from a performance point of view to avoid using a runtime | |
c3332e24 | 4347 | * relocation for this. The actual sequence of instructions often look |
252b5132 | 4348 | * something like: |
c3332e24 | 4349 | * |
24eab124 | 4350 | * call .L66 |
252b5132 | 4351 | * .L66: |
24eab124 AM |
4352 | * popl %ebx |
4353 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
c3332e24 | 4354 | * |
24eab124 | 4355 | * The call and pop essentially return the absolute address of |
252b5132 RH |
4356 | * the label .L66 and store it in %ebx. The linker itself will |
4357 | * ultimately change the first operand of the addl so that %ebx points to | |
4358 | * the GOT, but to keep things simple, the .o file must have this operand | |
4359 | * set so that it generates not the absolute address of .L66, but the | |
4360 | * absolute address of itself. This allows the linker itself simply | |
4361 | * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be | |
4362 | * added in, and the addend of the relocation is stored in the operand | |
4363 | * field for the instruction itself. | |
c3332e24 | 4364 | * |
24eab124 | 4365 | * Our job here is to fix the operand so that it would add the correct |
252b5132 RH |
4366 | * offset so that %ebx would point to itself. The thing that is tricky is |
4367 | * that .-.L66 will point to the beginning of the instruction, so we need | |
4368 | * to further modify the operand so that it will point to itself. | |
4369 | * There are other cases where you have something like: | |
c3332e24 | 4370 | * |
24eab124 | 4371 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] |
c3332e24 | 4372 | * |
252b5132 | 4373 | * and here no correction would be required. Internally in the assembler |
c3332e24 | 4374 | * we treat operands of this form as not being pcrel since the '.' is |
252b5132 RH |
4375 | * explicitly mentioned, and I wonder whether it would simplify matters |
4376 | * to do it this way. Who knows. In earlier versions of the PIC patches, | |
4377 | * the pcrel_adjust field was used to store the correction, but since the | |
47926f60 KH |
4378 | * expression is not pcrel, I felt it would be confusing to do it this |
4379 | * way. */ | |
4380 | ||
4381 | value -= 1; | |
4382 | break; | |
4383 | case BFD_RELOC_386_GOT32: | |
3e73aa7c | 4384 | case BFD_RELOC_X86_64_GOT32: |
47926f60 KH |
4385 | value = 0; /* Fully resolved at runtime. No addend. */ |
4386 | break; | |
4387 | case BFD_RELOC_386_GOTOFF: | |
3e73aa7c | 4388 | case BFD_RELOC_X86_64_GOTPCREL: |
47926f60 KH |
4389 | break; |
4390 | ||
4391 | case BFD_RELOC_VTABLE_INHERIT: | |
4392 | case BFD_RELOC_VTABLE_ENTRY: | |
4393 | fixP->fx_done = 0; | |
94f592af | 4394 | return; |
47926f60 KH |
4395 | |
4396 | default: | |
4397 | break; | |
4398 | } | |
4399 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
94f592af | 4400 | * valP = value; |
47926f60 | 4401 | #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */ |
3e73aa7c | 4402 | |
3e73aa7c | 4403 | /* Are we finished with this relocation now? */ |
94f592af | 4404 | if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0) |
3e73aa7c | 4405 | fixP->fx_done = 1; |
94f592af | 4406 | #ifdef BFD_ASSEMBLER |
3e73aa7c JH |
4407 | else if (use_rela_relocations) |
4408 | { | |
4409 | fixP->fx_no_overflow = 1; | |
4410 | value = 0; | |
4411 | } | |
3e73aa7c | 4412 | #endif |
94f592af | 4413 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 4414 | } |
252b5132 | 4415 | \f |
252b5132 RH |
4416 | #define MAX_LITTLENUMS 6 |
4417 | ||
47926f60 KH |
4418 | /* Turn the string pointed to by litP into a floating point constant |
4419 | of type TYPE, and emit the appropriate bytes. The number of | |
4420 | LITTLENUMS emitted is stored in *SIZEP. An error message is | |
4421 | returned, or NULL on OK. */ | |
4422 | ||
252b5132 RH |
4423 | char * |
4424 | md_atof (type, litP, sizeP) | |
2ab9b79e | 4425 | int type; |
252b5132 RH |
4426 | char *litP; |
4427 | int *sizeP; | |
4428 | { | |
4429 | int prec; | |
4430 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
4431 | LITTLENUM_TYPE *wordP; | |
4432 | char *t; | |
4433 | ||
4434 | switch (type) | |
4435 | { | |
4436 | case 'f': | |
4437 | case 'F': | |
4438 | prec = 2; | |
4439 | break; | |
4440 | ||
4441 | case 'd': | |
4442 | case 'D': | |
4443 | prec = 4; | |
4444 | break; | |
4445 | ||
4446 | case 'x': | |
4447 | case 'X': | |
4448 | prec = 5; | |
4449 | break; | |
4450 | ||
4451 | default: | |
4452 | *sizeP = 0; | |
4453 | return _("Bad call to md_atof ()"); | |
4454 | } | |
4455 | t = atof_ieee (input_line_pointer, type, words); | |
4456 | if (t) | |
4457 | input_line_pointer = t; | |
4458 | ||
4459 | *sizeP = prec * sizeof (LITTLENUM_TYPE); | |
4460 | /* This loops outputs the LITTLENUMs in REVERSE order; in accord with | |
4461 | the bigendian 386. */ | |
4462 | for (wordP = words + prec - 1; prec--;) | |
4463 | { | |
4464 | md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE)); | |
4465 | litP += sizeof (LITTLENUM_TYPE); | |
4466 | } | |
4467 | return 0; | |
4468 | } | |
4469 | \f | |
4470 | char output_invalid_buf[8]; | |
4471 | ||
252b5132 RH |
4472 | static char * |
4473 | output_invalid (c) | |
4474 | int c; | |
4475 | { | |
3882b010 | 4476 | if (ISPRINT (c)) |
252b5132 RH |
4477 | sprintf (output_invalid_buf, "'%c'", c); |
4478 | else | |
4479 | sprintf (output_invalid_buf, "(0x%x)", (unsigned) c); | |
4480 | return output_invalid_buf; | |
4481 | } | |
4482 | ||
af6bdddf | 4483 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
4484 | |
4485 | static const reg_entry * | |
4486 | parse_register (reg_string, end_op) | |
4487 | char *reg_string; | |
4488 | char **end_op; | |
4489 | { | |
af6bdddf AM |
4490 | char *s = reg_string; |
4491 | char *p; | |
252b5132 RH |
4492 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
4493 | const reg_entry *r; | |
4494 | ||
4495 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
4496 | if (*s == REGISTER_PREFIX) | |
4497 | ++s; | |
4498 | ||
4499 | if (is_space_char (*s)) | |
4500 | ++s; | |
4501 | ||
4502 | p = reg_name_given; | |
af6bdddf | 4503 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
4504 | { |
4505 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
4506 | return (const reg_entry *) NULL; |
4507 | s++; | |
252b5132 RH |
4508 | } |
4509 | ||
6588847e DN |
4510 | /* For naked regs, make sure that we are not dealing with an identifier. |
4511 | This prevents confusing an identifier like `eax_var' with register | |
4512 | `eax'. */ | |
4513 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
4514 | return (const reg_entry *) NULL; | |
4515 | ||
af6bdddf | 4516 | *end_op = s; |
252b5132 RH |
4517 | |
4518 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
4519 | ||
5f47d35b | 4520 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
47926f60 | 4521 | if (r == i386_regtab /* %st is first entry of table */) |
5f47d35b | 4522 | { |
5f47d35b AM |
4523 | if (is_space_char (*s)) |
4524 | ++s; | |
4525 | if (*s == '(') | |
4526 | { | |
af6bdddf | 4527 | ++s; |
5f47d35b AM |
4528 | if (is_space_char (*s)) |
4529 | ++s; | |
4530 | if (*s >= '0' && *s <= '7') | |
4531 | { | |
4532 | r = &i386_float_regtab[*s - '0']; | |
af6bdddf | 4533 | ++s; |
5f47d35b AM |
4534 | if (is_space_char (*s)) |
4535 | ++s; | |
4536 | if (*s == ')') | |
4537 | { | |
4538 | *end_op = s + 1; | |
4539 | return r; | |
4540 | } | |
5f47d35b | 4541 | } |
47926f60 | 4542 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
4543 | return (const reg_entry *) NULL; |
4544 | } | |
4545 | } | |
4546 | ||
1ae00879 AM |
4547 | if (r != NULL |
4548 | && r->reg_flags & (RegRex64|RegRex) | |
4549 | && flag_code != CODE_64BIT) | |
4550 | { | |
4551 | return (const reg_entry *) NULL; | |
4552 | } | |
4553 | ||
252b5132 RH |
4554 | return r; |
4555 | } | |
4556 | \f | |
4cc782b5 | 4557 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
65172ab8 | 4558 | const char *md_shortopts = "kVQ:sq"; |
252b5132 | 4559 | #else |
65172ab8 | 4560 | const char *md_shortopts = "q"; |
252b5132 | 4561 | #endif |
6e0b89ee | 4562 | |
252b5132 | 4563 | struct option md_longopts[] = { |
3e73aa7c JH |
4564 | #define OPTION_32 (OPTION_MD_BASE + 0) |
4565 | {"32", no_argument, NULL, OPTION_32}, | |
6e0b89ee | 4566 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
3e73aa7c JH |
4567 | #define OPTION_64 (OPTION_MD_BASE + 1) |
4568 | {"64", no_argument, NULL, OPTION_64}, | |
6e0b89ee | 4569 | #endif |
252b5132 RH |
4570 | {NULL, no_argument, NULL, 0} |
4571 | }; | |
4572 | size_t md_longopts_size = sizeof (md_longopts); | |
4573 | ||
4574 | int | |
4575 | md_parse_option (c, arg) | |
4576 | int c; | |
ab9da554 | 4577 | char *arg ATTRIBUTE_UNUSED; |
252b5132 RH |
4578 | { |
4579 | switch (c) | |
4580 | { | |
a38cf1db AM |
4581 | case 'q': |
4582 | quiet_warnings = 1; | |
252b5132 RH |
4583 | break; |
4584 | ||
4585 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
4586 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
4587 | should be emitted or not. FIXME: Not implemented. */ | |
4588 | case 'Q': | |
252b5132 RH |
4589 | break; |
4590 | ||
4591 | /* -V: SVR4 argument to print version ID. */ | |
4592 | case 'V': | |
4593 | print_version_id (); | |
4594 | break; | |
4595 | ||
a38cf1db AM |
4596 | /* -k: Ignore for FreeBSD compatibility. */ |
4597 | case 'k': | |
252b5132 | 4598 | break; |
4cc782b5 ILT |
4599 | |
4600 | case 's': | |
4601 | /* -s: On i386 Solaris, this tells the native assembler to use | |
4602 | .stab instead of .stab.excl. We always use .stab anyhow. */ | |
4603 | break; | |
6e0b89ee | 4604 | |
3e73aa7c JH |
4605 | case OPTION_64: |
4606 | { | |
4607 | const char **list, **l; | |
4608 | ||
3e73aa7c JH |
4609 | list = bfd_target_list (); |
4610 | for (l = list; *l != NULL; l++) | |
6e0b89ee AM |
4611 | if (strcmp (*l, "elf64-x86-64") == 0) |
4612 | { | |
4613 | default_arch = "x86_64"; | |
4614 | break; | |
4615 | } | |
3e73aa7c | 4616 | if (*l == NULL) |
6e0b89ee | 4617 | as_fatal (_("No compiled in support for x86_64")); |
3e73aa7c JH |
4618 | free (list); |
4619 | } | |
4620 | break; | |
4621 | #endif | |
252b5132 | 4622 | |
6e0b89ee AM |
4623 | case OPTION_32: |
4624 | default_arch = "i386"; | |
4625 | break; | |
4626 | ||
252b5132 RH |
4627 | default: |
4628 | return 0; | |
4629 | } | |
4630 | return 1; | |
4631 | } | |
4632 | ||
4633 | void | |
4634 | md_show_usage (stream) | |
4635 | FILE *stream; | |
4636 | { | |
4cc782b5 ILT |
4637 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
4638 | fprintf (stream, _("\ | |
a38cf1db AM |
4639 | -Q ignored\n\ |
4640 | -V print assembler version number\n\ | |
4641 | -k ignored\n\ | |
4642 | -q quieten some warnings\n\ | |
4643 | -s ignored\n")); | |
4644 | #else | |
4645 | fprintf (stream, _("\ | |
4646 | -q quieten some warnings\n")); | |
4cc782b5 | 4647 | #endif |
252b5132 RH |
4648 | } |
4649 | ||
4650 | #ifdef BFD_ASSEMBLER | |
3e73aa7c JH |
4651 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
4652 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) | |
252b5132 RH |
4653 | |
4654 | /* Pick the target format to use. */ | |
4655 | ||
47926f60 | 4656 | const char * |
252b5132 RH |
4657 | i386_target_format () |
4658 | { | |
3e73aa7c JH |
4659 | if (!strcmp (default_arch, "x86_64")) |
4660 | set_code_flag (CODE_64BIT); | |
4661 | else if (!strcmp (default_arch, "i386")) | |
4662 | set_code_flag (CODE_32BIT); | |
4663 | else | |
4664 | as_fatal (_("Unknown architecture")); | |
252b5132 RH |
4665 | switch (OUTPUT_FLAVOR) |
4666 | { | |
4c63da97 AM |
4667 | #ifdef OBJ_MAYBE_AOUT |
4668 | case bfd_target_aout_flavour: | |
47926f60 | 4669 | return AOUT_TARGET_FORMAT; |
4c63da97 AM |
4670 | #endif |
4671 | #ifdef OBJ_MAYBE_COFF | |
252b5132 RH |
4672 | case bfd_target_coff_flavour: |
4673 | return "coff-i386"; | |
4c63da97 | 4674 | #endif |
3e73aa7c | 4675 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 4676 | case bfd_target_elf_flavour: |
3e73aa7c | 4677 | { |
e5cb08ac KH |
4678 | if (flag_code == CODE_64BIT) |
4679 | use_rela_relocations = 1; | |
4680 | return flag_code == CODE_64BIT ? "elf64-x86-64" : "elf32-i386"; | |
3e73aa7c | 4681 | } |
4c63da97 | 4682 | #endif |
252b5132 RH |
4683 | default: |
4684 | abort (); | |
4685 | return NULL; | |
4686 | } | |
4687 | } | |
4688 | ||
47926f60 | 4689 | #endif /* OBJ_MAYBE_ more than one */ |
a847613f AM |
4690 | |
4691 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) | |
4692 | void i386_elf_emit_arch_note () | |
4693 | { | |
4694 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
4695 | && cpu_arch_name != NULL) | |
4696 | { | |
4697 | char *p; | |
4698 | asection *seg = now_seg; | |
4699 | subsegT subseg = now_subseg; | |
4700 | Elf_Internal_Note i_note; | |
4701 | Elf_External_Note e_note; | |
4702 | asection *note_secp; | |
4703 | int len; | |
4704 | ||
4705 | /* Create the .note section. */ | |
4706 | note_secp = subseg_new (".note", 0); | |
4707 | bfd_set_section_flags (stdoutput, | |
4708 | note_secp, | |
4709 | SEC_HAS_CONTENTS | SEC_READONLY); | |
4710 | ||
4711 | /* Process the arch string. */ | |
4712 | len = strlen (cpu_arch_name); | |
4713 | ||
4714 | i_note.namesz = len + 1; | |
4715 | i_note.descsz = 0; | |
4716 | i_note.type = NT_ARCH; | |
4717 | p = frag_more (sizeof (e_note.namesz)); | |
4718 | md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz)); | |
4719 | p = frag_more (sizeof (e_note.descsz)); | |
4720 | md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz)); | |
4721 | p = frag_more (sizeof (e_note.type)); | |
4722 | md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type)); | |
4723 | p = frag_more (len + 1); | |
4724 | strcpy (p, cpu_arch_name); | |
4725 | ||
4726 | frag_align (2, 0, 0); | |
4727 | ||
4728 | subseg_set (seg, subseg); | |
4729 | } | |
4730 | } | |
4731 | #endif | |
47926f60 | 4732 | #endif /* BFD_ASSEMBLER */ |
252b5132 | 4733 | \f |
252b5132 RH |
4734 | symbolS * |
4735 | md_undefined_symbol (name) | |
4736 | char *name; | |
4737 | { | |
18dc2407 ILT |
4738 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
4739 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
4740 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
4741 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
4742 | { |
4743 | if (!GOT_symbol) | |
4744 | { | |
4745 | if (symbol_find (name)) | |
4746 | as_bad (_("GOT already in symbol table")); | |
4747 | GOT_symbol = symbol_new (name, undefined_section, | |
4748 | (valueT) 0, &zero_address_frag); | |
4749 | }; | |
4750 | return GOT_symbol; | |
4751 | } | |
252b5132 RH |
4752 | return 0; |
4753 | } | |
4754 | ||
4755 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 4756 | |
252b5132 RH |
4757 | valueT |
4758 | md_section_align (segment, size) | |
ab9da554 | 4759 | segT segment ATTRIBUTE_UNUSED; |
252b5132 RH |
4760 | valueT size; |
4761 | { | |
252b5132 | 4762 | #ifdef BFD_ASSEMBLER |
4c63da97 AM |
4763 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
4764 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
4765 | { | |
4766 | /* For a.out, force the section size to be aligned. If we don't do | |
4767 | this, BFD will align it for us, but it will not write out the | |
4768 | final bytes of the section. This may be a bug in BFD, but it is | |
4769 | easier to fix it here since that is how the other a.out targets | |
4770 | work. */ | |
4771 | int align; | |
4772 | ||
4773 | align = bfd_get_section_alignment (stdoutput, segment); | |
4774 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); | |
4775 | } | |
252b5132 RH |
4776 | #endif |
4777 | #endif | |
4778 | ||
4779 | return size; | |
4780 | } | |
4781 | ||
4782 | /* On the i386, PC-relative offsets are relative to the start of the | |
4783 | next instruction. That is, the address of the offset, plus its | |
4784 | size, since the offset is always the last part of the insn. */ | |
4785 | ||
4786 | long | |
4787 | md_pcrel_from (fixP) | |
4788 | fixS *fixP; | |
4789 | { | |
4790 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
4791 | } | |
4792 | ||
4793 | #ifndef I386COFF | |
4794 | ||
4795 | static void | |
4796 | s_bss (ignore) | |
ab9da554 | 4797 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
4798 | { |
4799 | register int temp; | |
4800 | ||
4801 | temp = get_absolute_expression (); | |
4802 | subseg_set (bss_section, (subsegT) temp); | |
4803 | demand_empty_rest_of_line (); | |
4804 | } | |
4805 | ||
4806 | #endif | |
4807 | ||
252b5132 RH |
4808 | #ifdef BFD_ASSEMBLER |
4809 | ||
4810 | void | |
4811 | i386_validate_fix (fixp) | |
4812 | fixS *fixp; | |
4813 | { | |
4814 | if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol) | |
4815 | { | |
3e73aa7c | 4816 | /* GOTOFF relocation are nonsense in 64bit mode. */ |
23df1078 JH |
4817 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
4818 | { | |
4819 | if (flag_code != CODE_64BIT) | |
4820 | abort (); | |
4821 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
4822 | } | |
4823 | else | |
4824 | { | |
4825 | if (flag_code == CODE_64BIT) | |
4826 | abort (); | |
4827 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
4828 | } | |
252b5132 RH |
4829 | fixp->fx_subsy = 0; |
4830 | } | |
4831 | } | |
4832 | ||
252b5132 RH |
4833 | arelent * |
4834 | tc_gen_reloc (section, fixp) | |
ab9da554 | 4835 | asection *section ATTRIBUTE_UNUSED; |
252b5132 RH |
4836 | fixS *fixp; |
4837 | { | |
4838 | arelent *rel; | |
4839 | bfd_reloc_code_real_type code; | |
4840 | ||
4841 | switch (fixp->fx_r_type) | |
4842 | { | |
3e73aa7c JH |
4843 | case BFD_RELOC_X86_64_PLT32: |
4844 | case BFD_RELOC_X86_64_GOT32: | |
4845 | case BFD_RELOC_X86_64_GOTPCREL: | |
252b5132 RH |
4846 | case BFD_RELOC_386_PLT32: |
4847 | case BFD_RELOC_386_GOT32: | |
4848 | case BFD_RELOC_386_GOTOFF: | |
4849 | case BFD_RELOC_386_GOTPC: | |
3e73aa7c | 4850 | case BFD_RELOC_X86_64_32S: |
252b5132 RH |
4851 | case BFD_RELOC_RVA: |
4852 | case BFD_RELOC_VTABLE_ENTRY: | |
4853 | case BFD_RELOC_VTABLE_INHERIT: | |
4854 | code = fixp->fx_r_type; | |
4855 | break; | |
4856 | default: | |
93382f6d | 4857 | if (fixp->fx_pcrel) |
252b5132 | 4858 | { |
93382f6d AM |
4859 | switch (fixp->fx_size) |
4860 | { | |
4861 | default: | |
b091f402 AM |
4862 | as_bad_where (fixp->fx_file, fixp->fx_line, |
4863 | _("can not do %d byte pc-relative relocation"), | |
4864 | fixp->fx_size); | |
93382f6d AM |
4865 | code = BFD_RELOC_32_PCREL; |
4866 | break; | |
4867 | case 1: code = BFD_RELOC_8_PCREL; break; | |
4868 | case 2: code = BFD_RELOC_16_PCREL; break; | |
4869 | case 4: code = BFD_RELOC_32_PCREL; break; | |
4870 | } | |
4871 | } | |
4872 | else | |
4873 | { | |
4874 | switch (fixp->fx_size) | |
4875 | { | |
4876 | default: | |
b091f402 AM |
4877 | as_bad_where (fixp->fx_file, fixp->fx_line, |
4878 | _("can not do %d byte relocation"), | |
4879 | fixp->fx_size); | |
93382f6d AM |
4880 | code = BFD_RELOC_32; |
4881 | break; | |
4882 | case 1: code = BFD_RELOC_8; break; | |
4883 | case 2: code = BFD_RELOC_16; break; | |
4884 | case 4: code = BFD_RELOC_32; break; | |
3e73aa7c | 4885 | case 8: code = BFD_RELOC_64; break; |
93382f6d | 4886 | } |
252b5132 RH |
4887 | } |
4888 | break; | |
4889 | } | |
252b5132 RH |
4890 | |
4891 | if (code == BFD_RELOC_32 | |
4892 | && GOT_symbol | |
4893 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c JH |
4894 | { |
4895 | /* We don't support GOTPC on 64bit targets. */ | |
4896 | if (flag_code == CODE_64BIT) | |
bfb32b52 | 4897 | abort (); |
3e73aa7c JH |
4898 | code = BFD_RELOC_386_GOTPC; |
4899 | } | |
252b5132 RH |
4900 | |
4901 | rel = (arelent *) xmalloc (sizeof (arelent)); | |
49309057 ILT |
4902 | rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
4903 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
4904 | |
4905 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
3e73aa7c JH |
4906 | if (!use_rela_relocations) |
4907 | { | |
4908 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
4909 | vtable entry to be used in the relocation's section offset. */ | |
4910 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
4911 | rel->address = fixp->fx_offset; | |
252b5132 | 4912 | |
3e73aa7c JH |
4913 | if (fixp->fx_pcrel) |
4914 | rel->addend = fixp->fx_addnumber; | |
4915 | else | |
4916 | rel->addend = 0; | |
4917 | } | |
4918 | /* Use the rela in 64bit mode. */ | |
252b5132 | 4919 | else |
3e73aa7c JH |
4920 | { |
4921 | rel->addend = fixp->fx_offset; | |
3e73aa7c JH |
4922 | if (fixp->fx_pcrel) |
4923 | rel->addend -= fixp->fx_size; | |
4924 | } | |
4925 | ||
252b5132 RH |
4926 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
4927 | if (rel->howto == NULL) | |
4928 | { | |
4929 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 4930 | _("cannot represent relocation type %s"), |
252b5132 RH |
4931 | bfd_get_reloc_code_name (code)); |
4932 | /* Set howto to a garbage value so that we can keep going. */ | |
4933 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
4934 | assert (rel->howto != NULL); | |
4935 | } | |
4936 | ||
4937 | return rel; | |
4938 | } | |
4939 | ||
47926f60 | 4940 | #else /* ! BFD_ASSEMBLER */ |
252b5132 RH |
4941 | |
4942 | #if (defined(OBJ_AOUT) | defined(OBJ_BOUT)) | |
4943 | void | |
4944 | tc_aout_fix_to_chars (where, fixP, segment_address_in_file) | |
4945 | char *where; | |
4946 | fixS *fixP; | |
4947 | relax_addressT segment_address_in_file; | |
4948 | { | |
47926f60 KH |
4949 | /* In: length of relocation (or of address) in chars: 1, 2 or 4. |
4950 | Out: GNU LD relocation length code: 0, 1, or 2. */ | |
252b5132 | 4951 | |
47926f60 | 4952 | static const unsigned char nbytes_r_length[] = { 42, 0, 1, 42, 2 }; |
252b5132 RH |
4953 | long r_symbolnum; |
4954 | ||
4955 | know (fixP->fx_addsy != NULL); | |
4956 | ||
4957 | md_number_to_chars (where, | |
4958 | (valueT) (fixP->fx_frag->fr_address | |
4959 | + fixP->fx_where - segment_address_in_file), | |
4960 | 4); | |
4961 | ||
4962 | r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy) | |
4963 | ? S_GET_TYPE (fixP->fx_addsy) | |
4964 | : fixP->fx_addsy->sy_number); | |
4965 | ||
4966 | where[6] = (r_symbolnum >> 16) & 0x0ff; | |
4967 | where[5] = (r_symbolnum >> 8) & 0x0ff; | |
4968 | where[4] = r_symbolnum & 0x0ff; | |
4969 | where[7] = ((((!S_IS_DEFINED (fixP->fx_addsy)) << 3) & 0x08) | |
4970 | | ((nbytes_r_length[fixP->fx_size] << 1) & 0x06) | |
4971 | | (((fixP->fx_pcrel << 0) & 0x01) & 0x0f)); | |
4972 | } | |
4973 | ||
47926f60 | 4974 | #endif /* OBJ_AOUT or OBJ_BOUT. */ |
252b5132 RH |
4975 | |
4976 | #if defined (I386COFF) | |
4977 | ||
4978 | short | |
4979 | tc_coff_fix2rtype (fixP) | |
4980 | fixS *fixP; | |
4981 | { | |
4982 | if (fixP->fx_r_type == R_IMAGEBASE) | |
4983 | return R_IMAGEBASE; | |
4984 | ||
4985 | return (fixP->fx_pcrel ? | |
4986 | (fixP->fx_size == 1 ? R_PCRBYTE : | |
4987 | fixP->fx_size == 2 ? R_PCRWORD : | |
4988 | R_PCRLONG) : | |
4989 | (fixP->fx_size == 1 ? R_RELBYTE : | |
4990 | fixP->fx_size == 2 ? R_RELWORD : | |
4991 | R_DIR32)); | |
4992 | } | |
4993 | ||
4994 | int | |
4995 | tc_coff_sizemachdep (frag) | |
4996 | fragS *frag; | |
4997 | { | |
4998 | if (frag->fr_next) | |
4999 | return (frag->fr_next->fr_address - frag->fr_address); | |
5000 | else | |
5001 | return 0; | |
5002 | } | |
5003 | ||
47926f60 | 5004 | #endif /* I386COFF */ |
252b5132 | 5005 | |
47926f60 | 5006 | #endif /* ! BFD_ASSEMBLER */ |
64a0c779 DN |
5007 | \f |
5008 | /* Parse operands using Intel syntax. This implements a recursive descent | |
5009 | parser based on the BNF grammar published in Appendix B of the MASM 6.1 | |
5010 | Programmer's Guide. | |
5011 | ||
5012 | FIXME: We do not recognize the full operand grammar defined in the MASM | |
5013 | documentation. In particular, all the structure/union and | |
5014 | high-level macro operands are missing. | |
5015 | ||
5016 | Uppercase words are terminals, lower case words are non-terminals. | |
5017 | Objects surrounded by double brackets '[[' ']]' are optional. Vertical | |
5018 | bars '|' denote choices. Most grammar productions are implemented in | |
5019 | functions called 'intel_<production>'. | |
5020 | ||
5021 | Initial production is 'expr'. | |
5022 | ||
64a0c779 DN |
5023 | addOp + | - |
5024 | ||
5025 | alpha [a-zA-Z] | |
5026 | ||
5027 | byteRegister AL | AH | BL | BH | CL | CH | DL | DH | |
5028 | ||
5029 | constant digits [[ radixOverride ]] | |
5030 | ||
5031 | dataType BYTE | WORD | DWORD | QWORD | XWORD | |
5032 | ||
5033 | digits decdigit | |
b77a7acd AJ |
5034 | | digits decdigit |
5035 | | digits hexdigit | |
64a0c779 DN |
5036 | |
5037 | decdigit [0-9] | |
5038 | ||
5039 | e05 e05 addOp e06 | |
b77a7acd | 5040 | | e06 |
64a0c779 DN |
5041 | |
5042 | e06 e06 mulOp e09 | |
b77a7acd | 5043 | | e09 |
64a0c779 DN |
5044 | |
5045 | e09 OFFSET e10 | |
5046 | | e09 PTR e10 | |
5047 | | e09 : e10 | |
5048 | | e10 | |
5049 | ||
5050 | e10 e10 [ expr ] | |
b77a7acd | 5051 | | e11 |
64a0c779 DN |
5052 | |
5053 | e11 ( expr ) | |
b77a7acd | 5054 | | [ expr ] |
64a0c779 DN |
5055 | | constant |
5056 | | dataType | |
5057 | | id | |
5058 | | $ | |
5059 | | register | |
5060 | ||
5061 | => expr SHORT e05 | |
b77a7acd | 5062 | | e05 |
64a0c779 DN |
5063 | |
5064 | gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX | |
b77a7acd | 5065 | | BP | EBP | SP | ESP | DI | EDI | SI | ESI |
64a0c779 DN |
5066 | |
5067 | hexdigit a | b | c | d | e | f | |
b77a7acd | 5068 | | A | B | C | D | E | F |
64a0c779 DN |
5069 | |
5070 | id alpha | |
b77a7acd | 5071 | | id alpha |
64a0c779 DN |
5072 | | id decdigit |
5073 | ||
5074 | mulOp * | / | MOD | |
5075 | ||
5076 | quote " | ' | |
5077 | ||
5078 | register specialRegister | |
b77a7acd | 5079 | | gpRegister |
64a0c779 DN |
5080 | | byteRegister |
5081 | ||
5082 | segmentRegister CS | DS | ES | FS | GS | SS | |
5083 | ||
5084 | specialRegister CR0 | CR2 | CR3 | |
b77a7acd | 5085 | | DR0 | DR1 | DR2 | DR3 | DR6 | DR7 |
64a0c779 DN |
5086 | | TR3 | TR4 | TR5 | TR6 | TR7 |
5087 | ||
64a0c779 DN |
5088 | We simplify the grammar in obvious places (e.g., register parsing is |
5089 | done by calling parse_register) and eliminate immediate left recursion | |
5090 | to implement a recursive-descent parser. | |
5091 | ||
5092 | expr SHORT e05 | |
b77a7acd | 5093 | | e05 |
64a0c779 DN |
5094 | |
5095 | e05 e06 e05' | |
5096 | ||
5097 | e05' addOp e06 e05' | |
b77a7acd | 5098 | | Empty |
64a0c779 DN |
5099 | |
5100 | e06 e09 e06' | |
5101 | ||
5102 | e06' mulOp e09 e06' | |
b77a7acd | 5103 | | Empty |
64a0c779 DN |
5104 | |
5105 | e09 OFFSET e10 e09' | |
b77a7acd | 5106 | | e10 e09' |
64a0c779 DN |
5107 | |
5108 | e09' PTR e10 e09' | |
b77a7acd | 5109 | | : e10 e09' |
64a0c779 DN |
5110 | | Empty |
5111 | ||
5112 | e10 e11 e10' | |
5113 | ||
5114 | e10' [ expr ] e10' | |
b77a7acd | 5115 | | Empty |
64a0c779 DN |
5116 | |
5117 | e11 ( expr ) | |
b77a7acd | 5118 | | [ expr ] |
64a0c779 DN |
5119 | | BYTE |
5120 | | WORD | |
5121 | | DWORD | |
5122 | | QWORD | |
5123 | | XWORD | |
5124 | | . | |
5125 | | $ | |
5126 | | register | |
5127 | | id | |
5128 | | constant */ | |
5129 | ||
5130 | /* Parsing structure for the intel syntax parser. Used to implement the | |
5131 | semantic actions for the operand grammar. */ | |
5132 | struct intel_parser_s | |
5133 | { | |
5134 | char *op_string; /* The string being parsed. */ | |
5135 | int got_a_float; /* Whether the operand is a float. */ | |
4a1805b1 | 5136 | int op_modifier; /* Operand modifier. */ |
64a0c779 DN |
5137 | int is_mem; /* 1 if operand is memory reference. */ |
5138 | const reg_entry *reg; /* Last register reference found. */ | |
5139 | char *disp; /* Displacement string being built. */ | |
5140 | }; | |
5141 | ||
5142 | static struct intel_parser_s intel_parser; | |
5143 | ||
5144 | /* Token structure for parsing intel syntax. */ | |
5145 | struct intel_token | |
5146 | { | |
5147 | int code; /* Token code. */ | |
5148 | const reg_entry *reg; /* Register entry for register tokens. */ | |
5149 | char *str; /* String representation. */ | |
5150 | }; | |
5151 | ||
5152 | static struct intel_token cur_token, prev_token; | |
5153 | ||
50705ef4 AM |
5154 | /* Token codes for the intel parser. Since T_SHORT is already used |
5155 | by COFF, undefine it first to prevent a warning. */ | |
64a0c779 DN |
5156 | #define T_NIL -1 |
5157 | #define T_CONST 1 | |
5158 | #define T_REG 2 | |
5159 | #define T_BYTE 3 | |
5160 | #define T_WORD 4 | |
5161 | #define T_DWORD 5 | |
5162 | #define T_QWORD 6 | |
5163 | #define T_XWORD 7 | |
50705ef4 | 5164 | #undef T_SHORT |
64a0c779 DN |
5165 | #define T_SHORT 8 |
5166 | #define T_OFFSET 9 | |
5167 | #define T_PTR 10 | |
5168 | #define T_ID 11 | |
5169 | ||
5170 | /* Prototypes for intel parser functions. */ | |
5171 | static int intel_match_token PARAMS ((int code)); | |
cce0cbdc DN |
5172 | static void intel_get_token PARAMS ((void)); |
5173 | static void intel_putback_token PARAMS ((void)); | |
5174 | static int intel_expr PARAMS ((void)); | |
5175 | static int intel_e05 PARAMS ((void)); | |
5176 | static int intel_e05_1 PARAMS ((void)); | |
5177 | static int intel_e06 PARAMS ((void)); | |
5178 | static int intel_e06_1 PARAMS ((void)); | |
5179 | static int intel_e09 PARAMS ((void)); | |
5180 | static int intel_e09_1 PARAMS ((void)); | |
5181 | static int intel_e10 PARAMS ((void)); | |
5182 | static int intel_e10_1 PARAMS ((void)); | |
5183 | static int intel_e11 PARAMS ((void)); | |
64a0c779 | 5184 | |
64a0c779 DN |
5185 | static int |
5186 | i386_intel_operand (operand_string, got_a_float) | |
5187 | char *operand_string; | |
5188 | int got_a_float; | |
5189 | { | |
5190 | int ret; | |
5191 | char *p; | |
5192 | ||
5193 | /* Initialize token holders. */ | |
5194 | cur_token.code = prev_token.code = T_NIL; | |
5195 | cur_token.reg = prev_token.reg = NULL; | |
5196 | cur_token.str = prev_token.str = NULL; | |
5197 | ||
5198 | /* Initialize parser structure. */ | |
e5cb08ac | 5199 | p = intel_parser.op_string = (char *) malloc (strlen (operand_string) + 1); |
64a0c779 DN |
5200 | if (p == NULL) |
5201 | abort (); | |
5202 | strcpy (intel_parser.op_string, operand_string); | |
5203 | intel_parser.got_a_float = got_a_float; | |
5204 | intel_parser.op_modifier = -1; | |
5205 | intel_parser.is_mem = 0; | |
5206 | intel_parser.reg = NULL; | |
e5cb08ac | 5207 | intel_parser.disp = (char *) malloc (strlen (operand_string) + 1); |
64a0c779 DN |
5208 | if (intel_parser.disp == NULL) |
5209 | abort (); | |
5210 | intel_parser.disp[0] = '\0'; | |
5211 | ||
5212 | /* Read the first token and start the parser. */ | |
5213 | intel_get_token (); | |
5214 | ret = intel_expr (); | |
5215 | ||
5216 | if (ret) | |
5217 | { | |
5218 | /* If we found a memory reference, hand it over to i386_displacement | |
5219 | to fill in the rest of the operand fields. */ | |
5220 | if (intel_parser.is_mem) | |
5221 | { | |
5222 | if ((i.mem_operands == 1 | |
5223 | && (current_templates->start->opcode_modifier & IsString) == 0) | |
5224 | || i.mem_operands == 2) | |
5225 | { | |
5226 | as_bad (_("too many memory references for '%s'"), | |
5227 | current_templates->start->name); | |
5228 | ret = 0; | |
5229 | } | |
5230 | else | |
5231 | { | |
5232 | char *s = intel_parser.disp; | |
5233 | i.mem_operands++; | |
5234 | ||
5235 | /* Add the displacement expression. */ | |
5236 | if (*s != '\0') | |
5237 | ret = i386_displacement (s, s + strlen (s)) | |
5238 | && i386_index_check (s); | |
5239 | } | |
5240 | } | |
5241 | ||
5242 | /* Constant and OFFSET expressions are handled by i386_immediate. */ | |
5243 | else if (intel_parser.op_modifier == OFFSET_FLAT | |
5244 | || intel_parser.reg == NULL) | |
5245 | ret = i386_immediate (intel_parser.disp); | |
5246 | } | |
5247 | ||
5248 | free (p); | |
5249 | free (intel_parser.disp); | |
5250 | ||
5251 | return ret; | |
5252 | } | |
5253 | ||
64a0c779 | 5254 | /* expr SHORT e05 |
b77a7acd | 5255 | | e05 */ |
64a0c779 DN |
5256 | static int |
5257 | intel_expr () | |
5258 | { | |
5259 | /* expr SHORT e05 */ | |
5260 | if (cur_token.code == T_SHORT) | |
5261 | { | |
5262 | intel_parser.op_modifier = SHORT; | |
5263 | intel_match_token (T_SHORT); | |
5264 | ||
5265 | return (intel_e05 ()); | |
5266 | } | |
5267 | ||
5268 | /* expr e05 */ | |
5269 | else | |
5270 | return intel_e05 (); | |
5271 | } | |
5272 | ||
64a0c779 DN |
5273 | /* e05 e06 e05' |
5274 | ||
4a1805b1 | 5275 | e05' addOp e06 e05' |
64a0c779 DN |
5276 | | Empty */ |
5277 | static int | |
5278 | intel_e05 () | |
5279 | { | |
5280 | return (intel_e06 () && intel_e05_1 ()); | |
5281 | } | |
5282 | ||
5283 | static int | |
5284 | intel_e05_1 () | |
5285 | { | |
5286 | /* e05' addOp e06 e05' */ | |
5287 | if (cur_token.code == '+' || cur_token.code == '-') | |
5288 | { | |
5289 | strcat (intel_parser.disp, cur_token.str); | |
5290 | intel_match_token (cur_token.code); | |
5291 | ||
5292 | return (intel_e06 () && intel_e05_1 ()); | |
5293 | } | |
5294 | ||
5295 | /* e05' Empty */ | |
5296 | else | |
5297 | return 1; | |
4a1805b1 | 5298 | } |
64a0c779 DN |
5299 | |
5300 | /* e06 e09 e06' | |
5301 | ||
5302 | e06' mulOp e09 e06' | |
b77a7acd | 5303 | | Empty */ |
64a0c779 DN |
5304 | static int |
5305 | intel_e06 () | |
5306 | { | |
5307 | return (intel_e09 () && intel_e06_1 ()); | |
5308 | } | |
5309 | ||
5310 | static int | |
5311 | intel_e06_1 () | |
5312 | { | |
5313 | /* e06' mulOp e09 e06' */ | |
5314 | if (cur_token.code == '*' || cur_token.code == '/') | |
5315 | { | |
5316 | strcat (intel_parser.disp, cur_token.str); | |
5317 | intel_match_token (cur_token.code); | |
5318 | ||
5319 | return (intel_e09 () && intel_e06_1 ()); | |
5320 | } | |
4a1805b1 | 5321 | |
64a0c779 | 5322 | /* e06' Empty */ |
4a1805b1 | 5323 | else |
64a0c779 DN |
5324 | return 1; |
5325 | } | |
5326 | ||
64a0c779 | 5327 | /* e09 OFFSET e10 e09' |
b77a7acd | 5328 | | e10 e09' |
64a0c779 DN |
5329 | |
5330 | e09' PTR e10 e09' | |
b77a7acd | 5331 | | : e10 e09' |
64a0c779 DN |
5332 | | Empty */ |
5333 | static int | |
5334 | intel_e09 () | |
5335 | { | |
5336 | /* e09 OFFSET e10 e09' */ | |
5337 | if (cur_token.code == T_OFFSET) | |
5338 | { | |
5339 | intel_parser.is_mem = 0; | |
5340 | intel_parser.op_modifier = OFFSET_FLAT; | |
5341 | intel_match_token (T_OFFSET); | |
5342 | ||
5343 | return (intel_e10 () && intel_e09_1 ()); | |
5344 | } | |
5345 | ||
5346 | /* e09 e10 e09' */ | |
5347 | else | |
5348 | return (intel_e10 () && intel_e09_1 ()); | |
5349 | } | |
5350 | ||
5351 | static int | |
5352 | intel_e09_1 () | |
5353 | { | |
5354 | /* e09' PTR e10 e09' */ | |
5355 | if (cur_token.code == T_PTR) | |
5356 | { | |
5357 | if (prev_token.code == T_BYTE) | |
5358 | i.suffix = BYTE_MNEM_SUFFIX; | |
5359 | ||
5360 | else if (prev_token.code == T_WORD) | |
5361 | { | |
5362 | if (intel_parser.got_a_float == 2) /* "fi..." */ | |
5363 | i.suffix = SHORT_MNEM_SUFFIX; | |
5364 | else | |
5365 | i.suffix = WORD_MNEM_SUFFIX; | |
5366 | } | |
5367 | ||
5368 | else if (prev_token.code == T_DWORD) | |
5369 | { | |
5370 | if (intel_parser.got_a_float == 1) /* "f..." */ | |
5371 | i.suffix = SHORT_MNEM_SUFFIX; | |
5372 | else | |
5373 | i.suffix = LONG_MNEM_SUFFIX; | |
5374 | } | |
5375 | ||
5376 | else if (prev_token.code == T_QWORD) | |
f16b83df JH |
5377 | { |
5378 | if (intel_parser.got_a_float == 1) /* "f..." */ | |
5379 | i.suffix = LONG_MNEM_SUFFIX; | |
5380 | else | |
3e73aa7c | 5381 | i.suffix = QWORD_MNEM_SUFFIX; |
f16b83df | 5382 | } |
64a0c779 DN |
5383 | |
5384 | else if (prev_token.code == T_XWORD) | |
5385 | i.suffix = LONG_DOUBLE_MNEM_SUFFIX; | |
5386 | ||
5387 | else | |
5388 | { | |
5389 | as_bad (_("Unknown operand modifier `%s'\n"), prev_token.str); | |
5390 | return 0; | |
5391 | } | |
5392 | ||
5393 | intel_match_token (T_PTR); | |
5394 | ||
5395 | return (intel_e10 () && intel_e09_1 ()); | |
5396 | } | |
5397 | ||
5398 | /* e09 : e10 e09' */ | |
5399 | else if (cur_token.code == ':') | |
5400 | { | |
21d6c4af DN |
5401 | /* Mark as a memory operand only if it's not already known to be an |
5402 | offset expression. */ | |
5403 | if (intel_parser.op_modifier != OFFSET_FLAT) | |
5404 | intel_parser.is_mem = 1; | |
64a0c779 DN |
5405 | |
5406 | return (intel_match_token (':') && intel_e10 () && intel_e09_1 ()); | |
5407 | } | |
5408 | ||
5409 | /* e09' Empty */ | |
5410 | else | |
5411 | return 1; | |
5412 | } | |
5413 | ||
5414 | /* e10 e11 e10' | |
5415 | ||
5416 | e10' [ expr ] e10' | |
b77a7acd | 5417 | | Empty */ |
64a0c779 DN |
5418 | static int |
5419 | intel_e10 () | |
5420 | { | |
5421 | return (intel_e11 () && intel_e10_1 ()); | |
5422 | } | |
5423 | ||
5424 | static int | |
5425 | intel_e10_1 () | |
5426 | { | |
5427 | /* e10' [ expr ] e10' */ | |
5428 | if (cur_token.code == '[') | |
5429 | { | |
5430 | intel_match_token ('['); | |
21d6c4af DN |
5431 | |
5432 | /* Mark as a memory operand only if it's not already known to be an | |
5433 | offset expression. If it's an offset expression, we need to keep | |
5434 | the brace in. */ | |
5435 | if (intel_parser.op_modifier != OFFSET_FLAT) | |
5436 | intel_parser.is_mem = 1; | |
5437 | else | |
5438 | strcat (intel_parser.disp, "["); | |
4a1805b1 | 5439 | |
64a0c779 | 5440 | /* Add a '+' to the displacement string if necessary. */ |
21d6c4af DN |
5441 | if (*intel_parser.disp != '\0' |
5442 | && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+') | |
64a0c779 DN |
5443 | strcat (intel_parser.disp, "+"); |
5444 | ||
21d6c4af DN |
5445 | if (intel_expr () && intel_match_token (']')) |
5446 | { | |
5447 | /* Preserve brackets when the operand is an offset expression. */ | |
5448 | if (intel_parser.op_modifier == OFFSET_FLAT) | |
5449 | strcat (intel_parser.disp, "]"); | |
5450 | ||
5451 | return intel_e10_1 (); | |
5452 | } | |
5453 | else | |
5454 | return 0; | |
64a0c779 DN |
5455 | } |
5456 | ||
5457 | /* e10' Empty */ | |
5458 | else | |
5459 | return 1; | |
5460 | } | |
5461 | ||
64a0c779 | 5462 | /* e11 ( expr ) |
b77a7acd | 5463 | | [ expr ] |
64a0c779 DN |
5464 | | BYTE |
5465 | | WORD | |
5466 | | DWORD | |
5467 | | QWORD | |
5468 | | XWORD | |
4a1805b1 | 5469 | | $ |
64a0c779 DN |
5470 | | . |
5471 | | register | |
5472 | | id | |
5473 | | constant */ | |
5474 | static int | |
5475 | intel_e11 () | |
5476 | { | |
5477 | /* e11 ( expr ) */ | |
5478 | if (cur_token.code == '(') | |
5479 | { | |
5480 | intel_match_token ('('); | |
5481 | strcat (intel_parser.disp, "("); | |
5482 | ||
5483 | if (intel_expr () && intel_match_token (')')) | |
e5cb08ac KH |
5484 | { |
5485 | strcat (intel_parser.disp, ")"); | |
5486 | return 1; | |
5487 | } | |
64a0c779 DN |
5488 | else |
5489 | return 0; | |
5490 | } | |
5491 | ||
5492 | /* e11 [ expr ] */ | |
5493 | else if (cur_token.code == '[') | |
5494 | { | |
5495 | intel_match_token ('['); | |
21d6c4af DN |
5496 | |
5497 | /* Mark as a memory operand only if it's not already known to be an | |
5498 | offset expression. If it's an offset expression, we need to keep | |
5499 | the brace in. */ | |
5500 | if (intel_parser.op_modifier != OFFSET_FLAT) | |
5501 | intel_parser.is_mem = 1; | |
5502 | else | |
5503 | strcat (intel_parser.disp, "["); | |
4a1805b1 | 5504 | |
64a0c779 DN |
5505 | /* Operands for jump/call inside brackets denote absolute addresses. */ |
5506 | if (current_templates->start->opcode_modifier & Jump | |
5507 | || current_templates->start->opcode_modifier & JumpDword | |
5508 | || current_templates->start->opcode_modifier & JumpByte | |
5509 | || current_templates->start->opcode_modifier & JumpInterSegment) | |
5510 | i.types[this_operand] |= JumpAbsolute; | |
5511 | ||
5512 | /* Add a '+' to the displacement string if necessary. */ | |
21d6c4af DN |
5513 | if (*intel_parser.disp != '\0' |
5514 | && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+') | |
64a0c779 DN |
5515 | strcat (intel_parser.disp, "+"); |
5516 | ||
21d6c4af DN |
5517 | if (intel_expr () && intel_match_token (']')) |
5518 | { | |
5519 | /* Preserve brackets when the operand is an offset expression. */ | |
5520 | if (intel_parser.op_modifier == OFFSET_FLAT) | |
5521 | strcat (intel_parser.disp, "]"); | |
5522 | ||
5523 | return 1; | |
5524 | } | |
5525 | else | |
5526 | return 0; | |
64a0c779 DN |
5527 | } |
5528 | ||
4a1805b1 | 5529 | /* e11 BYTE |
64a0c779 DN |
5530 | | WORD |
5531 | | DWORD | |
5532 | | QWORD | |
5533 | | XWORD */ | |
5534 | else if (cur_token.code == T_BYTE | |
5535 | || cur_token.code == T_WORD | |
5536 | || cur_token.code == T_DWORD | |
5537 | || cur_token.code == T_QWORD | |
5538 | || cur_token.code == T_XWORD) | |
5539 | { | |
5540 | intel_match_token (cur_token.code); | |
5541 | ||
5542 | return 1; | |
5543 | } | |
5544 | ||
5545 | /* e11 $ | |
5546 | | . */ | |
5547 | else if (cur_token.code == '$' || cur_token.code == '.') | |
5548 | { | |
5549 | strcat (intel_parser.disp, cur_token.str); | |
5550 | intel_match_token (cur_token.code); | |
21d6c4af DN |
5551 | |
5552 | /* Mark as a memory operand only if it's not already known to be an | |
5553 | offset expression. */ | |
5554 | if (intel_parser.op_modifier != OFFSET_FLAT) | |
5555 | intel_parser.is_mem = 1; | |
64a0c779 DN |
5556 | |
5557 | return 1; | |
5558 | } | |
5559 | ||
5560 | /* e11 register */ | |
5561 | else if (cur_token.code == T_REG) | |
5562 | { | |
5563 | const reg_entry *reg = intel_parser.reg = cur_token.reg; | |
5564 | ||
5565 | intel_match_token (T_REG); | |
5566 | ||
5567 | /* Check for segment change. */ | |
5568 | if (cur_token.code == ':') | |
5569 | { | |
5570 | if (reg->reg_type & (SReg2 | SReg3)) | |
5571 | { | |
5572 | switch (reg->reg_num) | |
5573 | { | |
5574 | case 0: | |
5575 | i.seg[i.mem_operands] = &es; | |
5576 | break; | |
5577 | case 1: | |
5578 | i.seg[i.mem_operands] = &cs; | |
5579 | break; | |
5580 | case 2: | |
5581 | i.seg[i.mem_operands] = &ss; | |
5582 | break; | |
5583 | case 3: | |
5584 | i.seg[i.mem_operands] = &ds; | |
5585 | break; | |
5586 | case 4: | |
5587 | i.seg[i.mem_operands] = &fs; | |
5588 | break; | |
5589 | case 5: | |
5590 | i.seg[i.mem_operands] = &gs; | |
5591 | break; | |
5592 | } | |
5593 | } | |
5594 | else | |
5595 | { | |
5596 | as_bad (_("`%s' is not a valid segment register"), reg->reg_name); | |
5597 | return 0; | |
5598 | } | |
5599 | } | |
5600 | ||
5601 | /* Not a segment register. Check for register scaling. */ | |
5602 | else if (cur_token.code == '*') | |
5603 | { | |
5604 | if (!intel_parser.is_mem) | |
5605 | { | |
5606 | as_bad (_("Register scaling only allowed in memory operands.")); | |
5607 | return 0; | |
5608 | } | |
5609 | ||
4a1805b1 | 5610 | /* What follows must be a valid scale. */ |
64a0c779 DN |
5611 | if (intel_match_token ('*') |
5612 | && strchr ("01248", *cur_token.str)) | |
5613 | { | |
5614 | i.index_reg = reg; | |
5615 | i.types[this_operand] |= BaseIndex; | |
5616 | ||
5617 | /* Set the scale after setting the register (otherwise, | |
5618 | i386_scale will complain) */ | |
5619 | i386_scale (cur_token.str); | |
5620 | intel_match_token (T_CONST); | |
5621 | } | |
5622 | else | |
5623 | { | |
5624 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
5625 | cur_token.str); | |
5626 | return 0; | |
5627 | } | |
5628 | } | |
5629 | ||
5630 | /* No scaling. If this is a memory operand, the register is either a | |
5631 | base register (first occurrence) or an index register (second | |
5632 | occurrence). */ | |
5633 | else if (intel_parser.is_mem && !(reg->reg_type & (SReg2 | SReg3))) | |
5634 | { | |
5635 | if (i.base_reg && i.index_reg) | |
5636 | { | |
5637 | as_bad (_("Too many register references in memory operand.\n")); | |
5638 | return 0; | |
5639 | } | |
5640 | ||
5641 | if (i.base_reg == NULL) | |
5642 | i.base_reg = reg; | |
5643 | else | |
5644 | i.index_reg = reg; | |
5645 | ||
5646 | i.types[this_operand] |= BaseIndex; | |
5647 | } | |
5648 | ||
5649 | /* Offset modifier. Add the register to the displacement string to be | |
5650 | parsed as an immediate expression after we're done. */ | |
5651 | else if (intel_parser.op_modifier == OFFSET_FLAT) | |
5652 | strcat (intel_parser.disp, reg->reg_name); | |
4a1805b1 | 5653 | |
64a0c779 DN |
5654 | /* It's neither base nor index nor offset. */ |
5655 | else | |
5656 | { | |
5657 | i.types[this_operand] |= reg->reg_type & ~BaseIndex; | |
5658 | i.op[this_operand].regs = reg; | |
5659 | i.reg_operands++; | |
5660 | } | |
5661 | ||
5662 | /* Since registers are not part of the displacement string (except | |
5663 | when we're parsing offset operands), we may need to remove any | |
5664 | preceding '+' from the displacement string. */ | |
5665 | if (*intel_parser.disp != '\0' | |
5666 | && intel_parser.op_modifier != OFFSET_FLAT) | |
5667 | { | |
5668 | char *s = intel_parser.disp; | |
5669 | s += strlen (s) - 1; | |
5670 | if (*s == '+') | |
5671 | *s = '\0'; | |
5672 | } | |
5673 | ||
5674 | return 1; | |
5675 | } | |
4a1805b1 | 5676 | |
64a0c779 DN |
5677 | /* e11 id */ |
5678 | else if (cur_token.code == T_ID) | |
5679 | { | |
5680 | /* Add the identifier to the displacement string. */ | |
5681 | strcat (intel_parser.disp, cur_token.str); | |
5682 | intel_match_token (T_ID); | |
5683 | ||
5684 | /* The identifier represents a memory reference only if it's not | |
5685 | preceded by an offset modifier. */ | |
21d6c4af | 5686 | if (intel_parser.op_modifier != OFFSET_FLAT) |
64a0c779 DN |
5687 | intel_parser.is_mem = 1; |
5688 | ||
5689 | return 1; | |
5690 | } | |
5691 | ||
5692 | /* e11 constant */ | |
5693 | else if (cur_token.code == T_CONST | |
e5cb08ac | 5694 | || cur_token.code == '-' |
64a0c779 DN |
5695 | || cur_token.code == '+') |
5696 | { | |
5697 | char *save_str; | |
5698 | ||
5699 | /* Allow constants that start with `+' or `-'. */ | |
5700 | if (cur_token.code == '-' || cur_token.code == '+') | |
5701 | { | |
5702 | strcat (intel_parser.disp, cur_token.str); | |
5703 | intel_match_token (cur_token.code); | |
5704 | if (cur_token.code != T_CONST) | |
5705 | { | |
5706 | as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"), | |
5707 | cur_token.str); | |
5708 | return 0; | |
5709 | } | |
5710 | } | |
5711 | ||
e5cb08ac | 5712 | save_str = (char *) malloc (strlen (cur_token.str) + 1); |
64a0c779 | 5713 | if (save_str == NULL) |
bc805888 | 5714 | abort (); |
64a0c779 DN |
5715 | strcpy (save_str, cur_token.str); |
5716 | ||
5717 | /* Get the next token to check for register scaling. */ | |
5718 | intel_match_token (cur_token.code); | |
5719 | ||
5720 | /* Check if this constant is a scaling factor for an index register. */ | |
5721 | if (cur_token.code == '*') | |
5722 | { | |
5723 | if (intel_match_token ('*') && cur_token.code == T_REG) | |
5724 | { | |
5725 | if (!intel_parser.is_mem) | |
5726 | { | |
5727 | as_bad (_("Register scaling only allowed in memory operands.")); | |
5728 | return 0; | |
5729 | } | |
5730 | ||
4a1805b1 | 5731 | /* The constant is followed by `* reg', so it must be |
64a0c779 DN |
5732 | a valid scale. */ |
5733 | if (strchr ("01248", *save_str)) | |
5734 | { | |
5735 | i.index_reg = cur_token.reg; | |
5736 | i.types[this_operand] |= BaseIndex; | |
5737 | ||
5738 | /* Set the scale after setting the register (otherwise, | |
5739 | i386_scale will complain) */ | |
5740 | i386_scale (save_str); | |
5741 | intel_match_token (T_REG); | |
5742 | ||
5743 | /* Since registers are not part of the displacement | |
5744 | string, we may need to remove any preceding '+' from | |
5745 | the displacement string. */ | |
5746 | if (*intel_parser.disp != '\0') | |
5747 | { | |
5748 | char *s = intel_parser.disp; | |
5749 | s += strlen (s) - 1; | |
5750 | if (*s == '+') | |
5751 | *s = '\0'; | |
5752 | } | |
5753 | ||
5754 | free (save_str); | |
5755 | ||
5756 | return 1; | |
5757 | } | |
5758 | else | |
5759 | return 0; | |
5760 | } | |
5761 | ||
5762 | /* The constant was not used for register scaling. Since we have | |
5763 | already consumed the token following `*' we now need to put it | |
5764 | back in the stream. */ | |
5765 | else | |
5766 | intel_putback_token (); | |
5767 | } | |
5768 | ||
5769 | /* Add the constant to the displacement string. */ | |
5770 | strcat (intel_parser.disp, save_str); | |
5771 | free (save_str); | |
5772 | ||
5773 | return 1; | |
5774 | } | |
5775 | ||
64a0c779 DN |
5776 | as_bad (_("Unrecognized token '%s'"), cur_token.str); |
5777 | return 0; | |
5778 | } | |
5779 | ||
64a0c779 DN |
5780 | /* Match the given token against cur_token. If they match, read the next |
5781 | token from the operand string. */ | |
5782 | static int | |
5783 | intel_match_token (code) | |
e5cb08ac | 5784 | int code; |
64a0c779 DN |
5785 | { |
5786 | if (cur_token.code == code) | |
5787 | { | |
5788 | intel_get_token (); | |
5789 | return 1; | |
5790 | } | |
5791 | else | |
5792 | { | |
5793 | as_bad (_("Unexpected token `%s'\n"), cur_token.str); | |
5794 | return 0; | |
5795 | } | |
5796 | } | |
5797 | ||
64a0c779 DN |
5798 | /* Read a new token from intel_parser.op_string and store it in cur_token. */ |
5799 | static void | |
5800 | intel_get_token () | |
5801 | { | |
5802 | char *end_op; | |
5803 | const reg_entry *reg; | |
5804 | struct intel_token new_token; | |
5805 | ||
5806 | new_token.code = T_NIL; | |
5807 | new_token.reg = NULL; | |
5808 | new_token.str = NULL; | |
5809 | ||
4a1805b1 | 5810 | /* Free the memory allocated to the previous token and move |
64a0c779 DN |
5811 | cur_token to prev_token. */ |
5812 | if (prev_token.str) | |
5813 | free (prev_token.str); | |
5814 | ||
5815 | prev_token = cur_token; | |
5816 | ||
5817 | /* Skip whitespace. */ | |
5818 | while (is_space_char (*intel_parser.op_string)) | |
5819 | intel_parser.op_string++; | |
5820 | ||
5821 | /* Return an empty token if we find nothing else on the line. */ | |
5822 | if (*intel_parser.op_string == '\0') | |
5823 | { | |
5824 | cur_token = new_token; | |
5825 | return; | |
5826 | } | |
5827 | ||
5828 | /* The new token cannot be larger than the remainder of the operand | |
5829 | string. */ | |
e5cb08ac | 5830 | new_token.str = (char *) malloc (strlen (intel_parser.op_string) + 1); |
64a0c779 | 5831 | if (new_token.str == NULL) |
bc805888 | 5832 | abort (); |
64a0c779 DN |
5833 | new_token.str[0] = '\0'; |
5834 | ||
5835 | if (strchr ("0123456789", *intel_parser.op_string)) | |
5836 | { | |
5837 | char *p = new_token.str; | |
5838 | char *q = intel_parser.op_string; | |
5839 | new_token.code = T_CONST; | |
5840 | ||
5841 | /* Allow any kind of identifier char to encompass floating point and | |
5842 | hexadecimal numbers. */ | |
5843 | while (is_identifier_char (*q)) | |
5844 | *p++ = *q++; | |
5845 | *p = '\0'; | |
5846 | ||
5847 | /* Recognize special symbol names [0-9][bf]. */ | |
5848 | if (strlen (intel_parser.op_string) == 2 | |
4a1805b1 | 5849 | && (intel_parser.op_string[1] == 'b' |
64a0c779 DN |
5850 | || intel_parser.op_string[1] == 'f')) |
5851 | new_token.code = T_ID; | |
5852 | } | |
5853 | ||
5854 | else if (strchr ("+-/*:[]()", *intel_parser.op_string)) | |
5855 | { | |
5856 | new_token.code = *intel_parser.op_string; | |
5857 | new_token.str[0] = *intel_parser.op_string; | |
5858 | new_token.str[1] = '\0'; | |
5859 | } | |
5860 | ||
5861 | else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg) | |
5862 | && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)) | |
5863 | { | |
5864 | new_token.code = T_REG; | |
5865 | new_token.reg = reg; | |
5866 | ||
5867 | if (*intel_parser.op_string == REGISTER_PREFIX) | |
5868 | { | |
5869 | new_token.str[0] = REGISTER_PREFIX; | |
5870 | new_token.str[1] = '\0'; | |
5871 | } | |
5872 | ||
5873 | strcat (new_token.str, reg->reg_name); | |
5874 | } | |
5875 | ||
5876 | else if (is_identifier_char (*intel_parser.op_string)) | |
5877 | { | |
5878 | char *p = new_token.str; | |
5879 | char *q = intel_parser.op_string; | |
5880 | ||
5881 | /* A '.' or '$' followed by an identifier char is an identifier. | |
5882 | Otherwise, it's operator '.' followed by an expression. */ | |
5883 | if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1))) | |
5884 | { | |
5885 | new_token.code = *q; | |
5886 | new_token.str[0] = *q; | |
5887 | new_token.str[1] = '\0'; | |
5888 | } | |
5889 | else | |
5890 | { | |
5891 | while (is_identifier_char (*q) || *q == '@') | |
5892 | *p++ = *q++; | |
5893 | *p = '\0'; | |
5894 | ||
5895 | if (strcasecmp (new_token.str, "BYTE") == 0) | |
5896 | new_token.code = T_BYTE; | |
5897 | ||
5898 | else if (strcasecmp (new_token.str, "WORD") == 0) | |
5899 | new_token.code = T_WORD; | |
5900 | ||
5901 | else if (strcasecmp (new_token.str, "DWORD") == 0) | |
5902 | new_token.code = T_DWORD; | |
5903 | ||
5904 | else if (strcasecmp (new_token.str, "QWORD") == 0) | |
5905 | new_token.code = T_QWORD; | |
5906 | ||
5907 | else if (strcasecmp (new_token.str, "XWORD") == 0) | |
5908 | new_token.code = T_XWORD; | |
5909 | ||
5910 | else if (strcasecmp (new_token.str, "PTR") == 0) | |
5911 | new_token.code = T_PTR; | |
5912 | ||
5913 | else if (strcasecmp (new_token.str, "SHORT") == 0) | |
5914 | new_token.code = T_SHORT; | |
5915 | ||
5916 | else if (strcasecmp (new_token.str, "OFFSET") == 0) | |
5917 | { | |
5918 | new_token.code = T_OFFSET; | |
5919 | ||
5920 | /* ??? This is not mentioned in the MASM grammar but gcc | |
5921 | makes use of it with -mintel-syntax. OFFSET may be | |
5922 | followed by FLAT: */ | |
5923 | if (strncasecmp (q, " FLAT:", 6) == 0) | |
5924 | strcat (new_token.str, " FLAT:"); | |
5925 | } | |
5926 | ||
5927 | /* ??? This is not mentioned in the MASM grammar. */ | |
5928 | else if (strcasecmp (new_token.str, "FLAT") == 0) | |
5929 | new_token.code = T_OFFSET; | |
5930 | ||
5931 | else | |
5932 | new_token.code = T_ID; | |
5933 | } | |
5934 | } | |
5935 | ||
5936 | else | |
5937 | as_bad (_("Unrecognized token `%s'\n"), intel_parser.op_string); | |
5938 | ||
5939 | intel_parser.op_string += strlen (new_token.str); | |
5940 | cur_token = new_token; | |
5941 | } | |
5942 | ||
64a0c779 DN |
5943 | /* Put cur_token back into the token stream and make cur_token point to |
5944 | prev_token. */ | |
5945 | static void | |
5946 | intel_putback_token () | |
5947 | { | |
5948 | intel_parser.op_string -= strlen (cur_token.str); | |
5949 | free (cur_token.str); | |
5950 | cur_token = prev_token; | |
4a1805b1 | 5951 | |
64a0c779 DN |
5952 | /* Forget prev_token. */ |
5953 | prev_token.code = T_NIL; | |
5954 | prev_token.reg = NULL; | |
5955 | prev_token.str = NULL; | |
5956 | } |