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b534c6d3 | 1 | /* tc-i386.c -- Assemble code for the Intel 80386 |
b3adc24a | 2 | Copyright (C) 1989-2020 Free Software Foundation, Inc. |
252b5132 RH |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
19 | 02110-1301, USA. */ | |
252b5132 | 20 | |
47926f60 KH |
21 | /* Intel 80386 machine specific gas. |
22 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 23 | x86_64 support by Jan Hubicka (jh@suse.cz) |
0f10071e | 24 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
47926f60 KH |
25 | Bugs & suggestions are completely welcome. This is free software. |
26 | Please help us make it better. */ | |
252b5132 | 27 | |
252b5132 | 28 | #include "as.h" |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | #include "subsegs.h" |
316e2c05 | 31 | #include "dwarf2dbg.h" |
54cfded0 | 32 | #include "dw2gencfi.h" |
d2b2c203 | 33 | #include "elf/x86-64.h" |
40fb9820 | 34 | #include "opcodes/i386-init.h" |
252b5132 | 35 | |
41fd2579 L |
36 | #ifdef HAVE_LIMITS_H |
37 | #include <limits.h> | |
38 | #else | |
39 | #ifdef HAVE_SYS_PARAM_H | |
40 | #include <sys/param.h> | |
41 | #endif | |
42 | #ifndef INT_MAX | |
43 | #define INT_MAX (int) (((unsigned) (-1)) >> 1) | |
44 | #endif | |
45 | #endif | |
46 | ||
252b5132 RH |
47 | #ifndef REGISTER_WARNINGS |
48 | #define REGISTER_WARNINGS 1 | |
49 | #endif | |
50 | ||
c3332e24 | 51 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 52 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
53 | #endif |
54 | ||
29b0f896 AM |
55 | #ifndef DEFAULT_ARCH |
56 | #define DEFAULT_ARCH "i386" | |
246fcdee | 57 | #endif |
252b5132 | 58 | |
edde18a5 AM |
59 | #ifndef INLINE |
60 | #if __GNUC__ >= 2 | |
61 | #define INLINE __inline__ | |
62 | #else | |
63 | #define INLINE | |
64 | #endif | |
65 | #endif | |
66 | ||
6305a203 L |
67 | /* Prefixes will be emitted in the order defined below. |
68 | WAIT_PREFIX must be the first prefix since FWAIT is really is an | |
69 | instruction, and so must come before any prefixes. | |
70 | The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, | |
42164a71 | 71 | REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */ |
6305a203 L |
72 | #define WAIT_PREFIX 0 |
73 | #define SEG_PREFIX 1 | |
74 | #define ADDR_PREFIX 2 | |
75 | #define DATA_PREFIX 3 | |
c32fa91d | 76 | #define REP_PREFIX 4 |
42164a71 | 77 | #define HLE_PREFIX REP_PREFIX |
7e8b059b | 78 | #define BND_PREFIX REP_PREFIX |
c32fa91d | 79 | #define LOCK_PREFIX 5 |
4e9ac44a L |
80 | #define REX_PREFIX 6 /* must come last. */ |
81 | #define MAX_PREFIXES 7 /* max prefixes per opcode */ | |
6305a203 L |
82 | |
83 | /* we define the syntax here (modulo base,index,scale syntax) */ | |
84 | #define REGISTER_PREFIX '%' | |
85 | #define IMMEDIATE_PREFIX '$' | |
86 | #define ABSOLUTE_PREFIX '*' | |
87 | ||
88 | /* these are the instruction mnemonic suffixes in AT&T syntax or | |
89 | memory operand size in Intel syntax. */ | |
90 | #define WORD_MNEM_SUFFIX 'w' | |
91 | #define BYTE_MNEM_SUFFIX 'b' | |
92 | #define SHORT_MNEM_SUFFIX 's' | |
93 | #define LONG_MNEM_SUFFIX 'l' | |
94 | #define QWORD_MNEM_SUFFIX 'q' | |
6305a203 L |
95 | /* Intel Syntax. Use a non-ascii letter since since it never appears |
96 | in instructions. */ | |
97 | #define LONG_DOUBLE_MNEM_SUFFIX '\1' | |
98 | ||
99 | #define END_OF_INSN '\0' | |
100 | ||
79dec6b7 JB |
101 | /* This matches the C -> StaticRounding alias in the opcode table. */ |
102 | #define commutative staticrounding | |
103 | ||
6305a203 L |
104 | /* |
105 | 'templates' is for grouping together 'template' structures for opcodes | |
106 | of the same name. This is only used for storing the insns in the grand | |
107 | ole hash table of insns. | |
108 | The templates themselves start at START and range up to (but not including) | |
109 | END. | |
110 | */ | |
111 | typedef struct | |
112 | { | |
d3ce72d0 NC |
113 | const insn_template *start; |
114 | const insn_template *end; | |
6305a203 L |
115 | } |
116 | templates; | |
117 | ||
118 | /* 386 operand encoding bytes: see 386 book for details of this. */ | |
119 | typedef struct | |
120 | { | |
121 | unsigned int regmem; /* codes register or memory operand */ | |
122 | unsigned int reg; /* codes register operand (or extended opcode) */ | |
123 | unsigned int mode; /* how to interpret regmem & reg */ | |
124 | } | |
125 | modrm_byte; | |
126 | ||
127 | /* x86-64 extension prefix. */ | |
128 | typedef int rex_byte; | |
129 | ||
6305a203 L |
130 | /* 386 opcode byte to code indirect addressing. */ |
131 | typedef struct | |
132 | { | |
133 | unsigned base; | |
134 | unsigned index; | |
135 | unsigned scale; | |
136 | } | |
137 | sib_byte; | |
138 | ||
6305a203 L |
139 | /* x86 arch names, types and features */ |
140 | typedef struct | |
141 | { | |
142 | const char *name; /* arch name */ | |
8a2c8fef | 143 | unsigned int len; /* arch string length */ |
6305a203 L |
144 | enum processor_type type; /* arch type */ |
145 | i386_cpu_flags flags; /* cpu feature flags */ | |
8a2c8fef | 146 | unsigned int skip; /* show_arch should skip this. */ |
6305a203 L |
147 | } |
148 | arch_entry; | |
149 | ||
293f5f65 L |
150 | /* Used to turn off indicated flags. */ |
151 | typedef struct | |
152 | { | |
153 | const char *name; /* arch name */ | |
154 | unsigned int len; /* arch string length */ | |
155 | i386_cpu_flags flags; /* cpu feature flags */ | |
156 | } | |
157 | noarch_entry; | |
158 | ||
78f12dd3 | 159 | static void update_code_flag (int, int); |
e3bb37b5 L |
160 | static void set_code_flag (int); |
161 | static void set_16bit_gcc_code_flag (int); | |
162 | static void set_intel_syntax (int); | |
1efbbeb4 | 163 | static void set_intel_mnemonic (int); |
db51cc60 | 164 | static void set_allow_index_reg (int); |
7bab8ab5 | 165 | static void set_check (int); |
e3bb37b5 | 166 | static void set_cpu_arch (int); |
6482c264 | 167 | #ifdef TE_PE |
e3bb37b5 | 168 | static void pe_directive_secrel (int); |
6482c264 | 169 | #endif |
e3bb37b5 L |
170 | static void signed_cons (int); |
171 | static char *output_invalid (int c); | |
ee86248c JB |
172 | static int i386_finalize_immediate (segT, expressionS *, i386_operand_type, |
173 | const char *); | |
174 | static int i386_finalize_displacement (segT, expressionS *, i386_operand_type, | |
175 | const char *); | |
a7619375 | 176 | static int i386_att_operand (char *); |
e3bb37b5 | 177 | static int i386_intel_operand (char *, int); |
ee86248c JB |
178 | static int i386_intel_simplify (expressionS *); |
179 | static int i386_intel_parse_name (const char *, expressionS *); | |
e3bb37b5 L |
180 | static const reg_entry *parse_register (char *, char **); |
181 | static char *parse_insn (char *, char *); | |
182 | static char *parse_operands (char *, const char *); | |
183 | static void swap_operands (void); | |
4d456e3d | 184 | static void swap_2_operands (int, int); |
48bcea9f | 185 | static enum flag_code i386_addressing_mode (void); |
e3bb37b5 L |
186 | static void optimize_imm (void); |
187 | static void optimize_disp (void); | |
83b16ac6 | 188 | static const insn_template *match_template (char); |
e3bb37b5 L |
189 | static int check_string (void); |
190 | static int process_suffix (void); | |
191 | static int check_byte_reg (void); | |
192 | static int check_long_reg (void); | |
193 | static int check_qword_reg (void); | |
194 | static int check_word_reg (void); | |
195 | static int finalize_imm (void); | |
196 | static int process_operands (void); | |
197 | static const seg_entry *build_modrm_byte (void); | |
198 | static void output_insn (void); | |
199 | static void output_imm (fragS *, offsetT); | |
200 | static void output_disp (fragS *, offsetT); | |
29b0f896 | 201 | #ifndef I386COFF |
e3bb37b5 | 202 | static void s_bss (int); |
252b5132 | 203 | #endif |
17d4e2a2 L |
204 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
205 | static void handle_large_common (int small ATTRIBUTE_UNUSED); | |
b4a3a7b4 L |
206 | |
207 | /* GNU_PROPERTY_X86_ISA_1_USED. */ | |
208 | static unsigned int x86_isa_1_used; | |
209 | /* GNU_PROPERTY_X86_FEATURE_2_USED. */ | |
210 | static unsigned int x86_feature_2_used; | |
211 | /* Generate x86 used ISA and feature properties. */ | |
212 | static unsigned int x86_used_note = DEFAULT_X86_USED_NOTE; | |
17d4e2a2 | 213 | #endif |
252b5132 | 214 | |
a847613f | 215 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 216 | |
43234a1e L |
217 | /* This struct describes rounding control and SAE in the instruction. */ |
218 | struct RC_Operation | |
219 | { | |
220 | enum rc_type | |
221 | { | |
222 | rne = 0, | |
223 | rd, | |
224 | ru, | |
225 | rz, | |
226 | saeonly | |
227 | } type; | |
228 | int operand; | |
229 | }; | |
230 | ||
231 | static struct RC_Operation rc_op; | |
232 | ||
233 | /* The struct describes masking, applied to OPERAND in the instruction. | |
234 | MASK is a pointer to the corresponding mask register. ZEROING tells | |
235 | whether merging or zeroing mask is used. */ | |
236 | struct Mask_Operation | |
237 | { | |
238 | const reg_entry *mask; | |
239 | unsigned int zeroing; | |
240 | /* The operand where this operation is associated. */ | |
241 | int operand; | |
242 | }; | |
243 | ||
244 | static struct Mask_Operation mask_op; | |
245 | ||
246 | /* The struct describes broadcasting, applied to OPERAND. FACTOR is | |
247 | broadcast factor. */ | |
248 | struct Broadcast_Operation | |
249 | { | |
8e6e0792 | 250 | /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */ |
43234a1e L |
251 | int type; |
252 | ||
253 | /* Index of broadcasted operand. */ | |
254 | int operand; | |
4a1b91ea L |
255 | |
256 | /* Number of bytes to broadcast. */ | |
257 | int bytes; | |
43234a1e L |
258 | }; |
259 | ||
260 | static struct Broadcast_Operation broadcast_op; | |
261 | ||
c0f3af97 L |
262 | /* VEX prefix. */ |
263 | typedef struct | |
264 | { | |
43234a1e L |
265 | /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */ |
266 | unsigned char bytes[4]; | |
c0f3af97 L |
267 | unsigned int length; |
268 | /* Destination or source register specifier. */ | |
269 | const reg_entry *register_specifier; | |
270 | } vex_prefix; | |
271 | ||
252b5132 | 272 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 273 | i386_insn. */ |
252b5132 | 274 | |
520dc8e8 AM |
275 | union i386_op |
276 | { | |
277 | expressionS *disps; | |
278 | expressionS *imms; | |
279 | const reg_entry *regs; | |
280 | }; | |
281 | ||
a65babc9 L |
282 | enum i386_error |
283 | { | |
86e026a4 | 284 | operand_size_mismatch, |
a65babc9 L |
285 | operand_type_mismatch, |
286 | register_type_mismatch, | |
287 | number_of_operands_mismatch, | |
288 | invalid_instruction_suffix, | |
289 | bad_imm4, | |
a65babc9 L |
290 | unsupported_with_intel_mnemonic, |
291 | unsupported_syntax, | |
6c30d220 L |
292 | unsupported, |
293 | invalid_vsib_address, | |
7bab8ab5 | 294 | invalid_vector_register_set, |
43234a1e L |
295 | unsupported_vector_index_register, |
296 | unsupported_broadcast, | |
43234a1e L |
297 | broadcast_needed, |
298 | unsupported_masking, | |
299 | mask_not_on_destination, | |
300 | no_default_mask, | |
301 | unsupported_rc_sae, | |
302 | rc_sae_operand_not_last_imm, | |
303 | invalid_register_operand, | |
a65babc9 L |
304 | }; |
305 | ||
252b5132 RH |
306 | struct _i386_insn |
307 | { | |
47926f60 | 308 | /* TM holds the template for the insn were currently assembling. */ |
d3ce72d0 | 309 | insn_template tm; |
252b5132 | 310 | |
7d5e4556 L |
311 | /* SUFFIX holds the instruction size suffix for byte, word, dword |
312 | or qword, if given. */ | |
252b5132 RH |
313 | char suffix; |
314 | ||
47926f60 | 315 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
316 | unsigned int operands; |
317 | ||
318 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
319 | of given register, displacement, memory operands and immediate | |
47926f60 | 320 | operands. */ |
252b5132 RH |
321 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
322 | ||
323 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 324 | use OP[i] for the corresponding operand. */ |
40fb9820 | 325 | i386_operand_type types[MAX_OPERANDS]; |
252b5132 | 326 | |
520dc8e8 AM |
327 | /* Displacement expression, immediate expression, or register for each |
328 | operand. */ | |
329 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 330 | |
3e73aa7c JH |
331 | /* Flags for operands. */ |
332 | unsigned int flags[MAX_OPERANDS]; | |
333 | #define Operand_PCrel 1 | |
c48dadc9 | 334 | #define Operand_Mem 2 |
3e73aa7c | 335 | |
252b5132 | 336 | /* Relocation type for operand */ |
f86103b7 | 337 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
252b5132 | 338 | |
252b5132 RH |
339 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
340 | the base index byte below. */ | |
341 | const reg_entry *base_reg; | |
342 | const reg_entry *index_reg; | |
343 | unsigned int log2_scale_factor; | |
344 | ||
345 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 346 | explicit segment overrides are given. */ |
ce8a8b2f | 347 | const seg_entry *seg[2]; |
252b5132 | 348 | |
8325cc63 JB |
349 | /* Copied first memory operand string, for re-checking. */ |
350 | char *memop1_string; | |
351 | ||
252b5132 RH |
352 | /* PREFIX holds all the given prefix opcodes (usually null). |
353 | PREFIXES is the number of prefix opcodes. */ | |
354 | unsigned int prefixes; | |
355 | unsigned char prefix[MAX_PREFIXES]; | |
356 | ||
6f2f06be JB |
357 | /* The operand to a branch insn indicates an absolute branch. */ |
358 | bfd_boolean jumpabsolute; | |
359 | ||
b4a3a7b4 L |
360 | /* Has MMX register operands. */ |
361 | bfd_boolean has_regmmx; | |
362 | ||
363 | /* Has XMM register operands. */ | |
364 | bfd_boolean has_regxmm; | |
365 | ||
366 | /* Has YMM register operands. */ | |
367 | bfd_boolean has_regymm; | |
368 | ||
369 | /* Has ZMM register operands. */ | |
370 | bfd_boolean has_regzmm; | |
371 | ||
e379e5f3 L |
372 | /* Has GOTPC or TLS relocation. */ |
373 | bfd_boolean has_gotpc_tls_reloc; | |
374 | ||
252b5132 | 375 | /* RM and SIB are the modrm byte and the sib byte where the |
c1e679ec | 376 | addressing modes of this insn are encoded. */ |
252b5132 | 377 | modrm_byte rm; |
3e73aa7c | 378 | rex_byte rex; |
43234a1e | 379 | rex_byte vrex; |
252b5132 | 380 | sib_byte sib; |
c0f3af97 | 381 | vex_prefix vex; |
b6169b20 | 382 | |
43234a1e L |
383 | /* Masking attributes. */ |
384 | struct Mask_Operation *mask; | |
385 | ||
386 | /* Rounding control and SAE attributes. */ | |
387 | struct RC_Operation *rounding; | |
388 | ||
389 | /* Broadcasting attributes. */ | |
390 | struct Broadcast_Operation *broadcast; | |
391 | ||
392 | /* Compressed disp8*N attribute. */ | |
393 | unsigned int memshift; | |
394 | ||
86fa6981 L |
395 | /* Prefer load or store in encoding. */ |
396 | enum | |
397 | { | |
398 | dir_encoding_default = 0, | |
399 | dir_encoding_load, | |
64c49ab3 JB |
400 | dir_encoding_store, |
401 | dir_encoding_swap | |
86fa6981 | 402 | } dir_encoding; |
891edac4 | 403 | |
a501d77e L |
404 | /* Prefer 8bit or 32bit displacement in encoding. */ |
405 | enum | |
406 | { | |
407 | disp_encoding_default = 0, | |
408 | disp_encoding_8bit, | |
409 | disp_encoding_32bit | |
410 | } disp_encoding; | |
f8a5c266 | 411 | |
6b6b6807 L |
412 | /* Prefer the REX byte in encoding. */ |
413 | bfd_boolean rex_encoding; | |
414 | ||
b6f8c7c4 L |
415 | /* Disable instruction size optimization. */ |
416 | bfd_boolean no_optimize; | |
417 | ||
86fa6981 L |
418 | /* How to encode vector instructions. */ |
419 | enum | |
420 | { | |
421 | vex_encoding_default = 0, | |
422 | vex_encoding_vex2, | |
423 | vex_encoding_vex3, | |
424 | vex_encoding_evex | |
425 | } vec_encoding; | |
426 | ||
d5de92cf L |
427 | /* REP prefix. */ |
428 | const char *rep_prefix; | |
429 | ||
165de32a L |
430 | /* HLE prefix. */ |
431 | const char *hle_prefix; | |
42164a71 | 432 | |
7e8b059b L |
433 | /* Have BND prefix. */ |
434 | const char *bnd_prefix; | |
435 | ||
04ef582a L |
436 | /* Have NOTRACK prefix. */ |
437 | const char *notrack_prefix; | |
438 | ||
891edac4 | 439 | /* Error message. */ |
a65babc9 | 440 | enum i386_error error; |
252b5132 RH |
441 | }; |
442 | ||
443 | typedef struct _i386_insn i386_insn; | |
444 | ||
43234a1e L |
445 | /* Link RC type with corresponding string, that'll be looked for in |
446 | asm. */ | |
447 | struct RC_name | |
448 | { | |
449 | enum rc_type type; | |
450 | const char *name; | |
451 | unsigned int len; | |
452 | }; | |
453 | ||
454 | static const struct RC_name RC_NamesTable[] = | |
455 | { | |
456 | { rne, STRING_COMMA_LEN ("rn-sae") }, | |
457 | { rd, STRING_COMMA_LEN ("rd-sae") }, | |
458 | { ru, STRING_COMMA_LEN ("ru-sae") }, | |
459 | { rz, STRING_COMMA_LEN ("rz-sae") }, | |
460 | { saeonly, STRING_COMMA_LEN ("sae") }, | |
461 | }; | |
462 | ||
252b5132 RH |
463 | /* List of chars besides those in app.c:symbol_chars that can start an |
464 | operand. Used to prevent the scrubber eating vital white-space. */ | |
86fa6981 | 465 | const char extra_symbol_chars[] = "*%-([{}" |
252b5132 | 466 | #ifdef LEX_AT |
32137342 NC |
467 | "@" |
468 | #endif | |
469 | #ifdef LEX_QM | |
470 | "?" | |
252b5132 | 471 | #endif |
32137342 | 472 | ; |
252b5132 | 473 | |
29b0f896 AM |
474 | #if (defined (TE_I386AIX) \ |
475 | || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ | |
3896cfd5 | 476 | && !defined (TE_GNU) \ |
29b0f896 | 477 | && !defined (TE_LINUX) \ |
8d63c93e | 478 | && !defined (TE_NACL) \ |
29b0f896 | 479 | && !defined (TE_FreeBSD) \ |
5b806d27 | 480 | && !defined (TE_DragonFly) \ |
29b0f896 | 481 | && !defined (TE_NetBSD))) |
252b5132 | 482 | /* This array holds the chars that always start a comment. If the |
b3b91714 AM |
483 | pre-processor is disabled, these aren't very useful. The option |
484 | --divide will remove '/' from this list. */ | |
485 | const char *i386_comment_chars = "#/"; | |
486 | #define SVR4_COMMENT_CHARS 1 | |
252b5132 | 487 | #define PREFIX_SEPARATOR '\\' |
252b5132 | 488 | |
b3b91714 AM |
489 | #else |
490 | const char *i386_comment_chars = "#"; | |
491 | #define PREFIX_SEPARATOR '/' | |
492 | #endif | |
493 | ||
252b5132 RH |
494 | /* This array holds the chars that only start a comment at the beginning of |
495 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
496 | .line and .file directives will appear in the pre-processed output. |
497 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 498 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
499 | #NO_APP at the beginning of its output. |
500 | Also note that comments started like this one will always work if | |
252b5132 | 501 | '/' isn't otherwise defined. */ |
b3b91714 | 502 | const char line_comment_chars[] = "#/"; |
252b5132 | 503 | |
63a0b638 | 504 | const char line_separator_chars[] = ";"; |
252b5132 | 505 | |
ce8a8b2f AM |
506 | /* Chars that can be used to separate mant from exp in floating point |
507 | nums. */ | |
252b5132 RH |
508 | const char EXP_CHARS[] = "eE"; |
509 | ||
ce8a8b2f AM |
510 | /* Chars that mean this number is a floating point constant |
511 | As in 0f12.456 | |
512 | or 0d1.2345e12. */ | |
252b5132 RH |
513 | const char FLT_CHARS[] = "fFdDxX"; |
514 | ||
ce8a8b2f | 515 | /* Tables for lexical analysis. */ |
252b5132 RH |
516 | static char mnemonic_chars[256]; |
517 | static char register_chars[256]; | |
518 | static char operand_chars[256]; | |
519 | static char identifier_chars[256]; | |
520 | static char digit_chars[256]; | |
521 | ||
ce8a8b2f | 522 | /* Lexical macros. */ |
252b5132 RH |
523 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
524 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
525 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
526 | #define is_space_char(x) ((x) == ' ') | |
527 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
528 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
529 | ||
0234cb7c | 530 | /* All non-digit non-letter characters that may occur in an operand. */ |
252b5132 RH |
531 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
532 | ||
533 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
534 | effect this we maintain a stack of saved characters that we've smashed | |
535 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 536 | assembler instruction). */ |
252b5132 | 537 | static char save_stack[32]; |
ce8a8b2f | 538 | static char *save_stack_p; |
252b5132 RH |
539 | #define END_STRING_AND_SAVE(s) \ |
540 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
541 | #define RESTORE_END_STRING(s) \ | |
542 | do { *(s) = *--save_stack_p; } while (0) | |
543 | ||
47926f60 | 544 | /* The instruction we're assembling. */ |
252b5132 RH |
545 | static i386_insn i; |
546 | ||
547 | /* Possible templates for current insn. */ | |
548 | static const templates *current_templates; | |
549 | ||
31b2323c L |
550 | /* Per instruction expressionS buffers: max displacements & immediates. */ |
551 | static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; | |
552 | static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; | |
252b5132 | 553 | |
47926f60 | 554 | /* Current operand we are working on. */ |
ee86248c | 555 | static int this_operand = -1; |
252b5132 | 556 | |
3e73aa7c JH |
557 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
558 | these. */ | |
559 | ||
560 | enum flag_code { | |
561 | CODE_32BIT, | |
562 | CODE_16BIT, | |
563 | CODE_64BIT }; | |
564 | ||
565 | static enum flag_code flag_code; | |
4fa24527 | 566 | static unsigned int object_64bit; |
862be3fb | 567 | static unsigned int disallow_64bit_reloc; |
3e73aa7c | 568 | static int use_rela_relocations = 0; |
e379e5f3 L |
569 | /* __tls_get_addr/___tls_get_addr symbol for TLS. */ |
570 | static const char *tls_get_addr; | |
3e73aa7c | 571 | |
7af8ed2d NC |
572 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
573 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ | |
574 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) | |
575 | ||
351f65ca L |
576 | /* The ELF ABI to use. */ |
577 | enum x86_elf_abi | |
578 | { | |
579 | I386_ABI, | |
7f56bc95 L |
580 | X86_64_ABI, |
581 | X86_64_X32_ABI | |
351f65ca L |
582 | }; |
583 | ||
584 | static enum x86_elf_abi x86_elf_abi = I386_ABI; | |
7af8ed2d | 585 | #endif |
351f65ca | 586 | |
167ad85b TG |
587 | #if defined (TE_PE) || defined (TE_PEP) |
588 | /* Use big object file format. */ | |
589 | static int use_big_obj = 0; | |
590 | #endif | |
591 | ||
8dcea932 L |
592 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
593 | /* 1 if generating code for a shared library. */ | |
594 | static int shared = 0; | |
595 | #endif | |
596 | ||
47926f60 KH |
597 | /* 1 for intel syntax, |
598 | 0 if att syntax. */ | |
599 | static int intel_syntax = 0; | |
252b5132 | 600 | |
e89c5eaa L |
601 | /* 1 for Intel64 ISA, |
602 | 0 if AMD64 ISA. */ | |
603 | static int intel64; | |
604 | ||
1efbbeb4 L |
605 | /* 1 for intel mnemonic, |
606 | 0 if att mnemonic. */ | |
607 | static int intel_mnemonic = !SYSV386_COMPAT; | |
608 | ||
a60de03c JB |
609 | /* 1 if pseudo registers are permitted. */ |
610 | static int allow_pseudo_reg = 0; | |
611 | ||
47926f60 KH |
612 | /* 1 if register prefix % not required. */ |
613 | static int allow_naked_reg = 0; | |
252b5132 | 614 | |
33eaf5de | 615 | /* 1 if the assembler should add BND prefix for all control-transferring |
7e8b059b L |
616 | instructions supporting it, even if this prefix wasn't specified |
617 | explicitly. */ | |
618 | static int add_bnd_prefix = 0; | |
619 | ||
ba104c83 | 620 | /* 1 if pseudo index register, eiz/riz, is allowed . */ |
db51cc60 L |
621 | static int allow_index_reg = 0; |
622 | ||
d022bddd IT |
623 | /* 1 if the assembler should ignore LOCK prefix, even if it was |
624 | specified explicitly. */ | |
625 | static int omit_lock_prefix = 0; | |
626 | ||
e4e00185 AS |
627 | /* 1 if the assembler should encode lfence, mfence, and sfence as |
628 | "lock addl $0, (%{re}sp)". */ | |
629 | static int avoid_fence = 0; | |
630 | ||
e379e5f3 L |
631 | /* Type of the previous instruction. */ |
632 | static struct | |
633 | { | |
634 | segT seg; | |
635 | const char *file; | |
636 | const char *name; | |
637 | unsigned int line; | |
638 | enum last_insn_kind | |
639 | { | |
640 | last_insn_other = 0, | |
641 | last_insn_directive, | |
642 | last_insn_prefix | |
643 | } kind; | |
644 | } last_insn; | |
645 | ||
0cb4071e L |
646 | /* 1 if the assembler should generate relax relocations. */ |
647 | ||
648 | static int generate_relax_relocations | |
649 | = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS; | |
650 | ||
7bab8ab5 | 651 | static enum check_kind |
daf50ae7 | 652 | { |
7bab8ab5 JB |
653 | check_none = 0, |
654 | check_warning, | |
655 | check_error | |
daf50ae7 | 656 | } |
7bab8ab5 | 657 | sse_check, operand_check = check_warning; |
daf50ae7 | 658 | |
e379e5f3 L |
659 | /* Non-zero if branches should be aligned within power of 2 boundary. */ |
660 | static int align_branch_power = 0; | |
661 | ||
662 | /* Types of branches to align. */ | |
663 | enum align_branch_kind | |
664 | { | |
665 | align_branch_none = 0, | |
666 | align_branch_jcc = 1, | |
667 | align_branch_fused = 2, | |
668 | align_branch_jmp = 3, | |
669 | align_branch_call = 4, | |
670 | align_branch_indirect = 5, | |
671 | align_branch_ret = 6 | |
672 | }; | |
673 | ||
674 | /* Type bits of branches to align. */ | |
675 | enum align_branch_bit | |
676 | { | |
677 | align_branch_jcc_bit = 1 << align_branch_jcc, | |
678 | align_branch_fused_bit = 1 << align_branch_fused, | |
679 | align_branch_jmp_bit = 1 << align_branch_jmp, | |
680 | align_branch_call_bit = 1 << align_branch_call, | |
681 | align_branch_indirect_bit = 1 << align_branch_indirect, | |
682 | align_branch_ret_bit = 1 << align_branch_ret | |
683 | }; | |
684 | ||
685 | static unsigned int align_branch = (align_branch_jcc_bit | |
686 | | align_branch_fused_bit | |
687 | | align_branch_jmp_bit); | |
688 | ||
689 | /* The maximum padding size for fused jcc. CMP like instruction can | |
690 | be 9 bytes and jcc can be 6 bytes. Leave room just in case for | |
691 | prefixes. */ | |
692 | #define MAX_FUSED_JCC_PADDING_SIZE 20 | |
693 | ||
694 | /* The maximum number of prefixes added for an instruction. */ | |
695 | static unsigned int align_branch_prefix_size = 5; | |
696 | ||
b6f8c7c4 L |
697 | /* Optimization: |
698 | 1. Clear the REX_W bit with register operand if possible. | |
699 | 2. Above plus use 128bit vector instruction to clear the full vector | |
700 | register. | |
701 | */ | |
702 | static int optimize = 0; | |
703 | ||
704 | /* Optimization: | |
705 | 1. Clear the REX_W bit with register operand if possible. | |
706 | 2. Above plus use 128bit vector instruction to clear the full vector | |
707 | register. | |
708 | 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to | |
709 | "testb $imm7,%r8". | |
710 | */ | |
711 | static int optimize_for_space = 0; | |
712 | ||
2ca3ace5 L |
713 | /* Register prefix used for error message. */ |
714 | static const char *register_prefix = "%"; | |
715 | ||
47926f60 KH |
716 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
717 | leave, push, and pop instructions so that gcc has the same stack | |
718 | frame as in 32 bit mode. */ | |
719 | static char stackop_size = '\0'; | |
eecb386c | 720 | |
12b55ccc L |
721 | /* Non-zero to optimize code alignment. */ |
722 | int optimize_align_code = 1; | |
723 | ||
47926f60 KH |
724 | /* Non-zero to quieten some warnings. */ |
725 | static int quiet_warnings = 0; | |
a38cf1db | 726 | |
47926f60 KH |
727 | /* CPU name. */ |
728 | static const char *cpu_arch_name = NULL; | |
6305a203 | 729 | static char *cpu_sub_arch_name = NULL; |
a38cf1db | 730 | |
47926f60 | 731 | /* CPU feature flags. */ |
40fb9820 L |
732 | static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; |
733 | ||
ccc9c027 L |
734 | /* If we have selected a cpu we are generating instructions for. */ |
735 | static int cpu_arch_tune_set = 0; | |
736 | ||
9103f4f4 | 737 | /* Cpu we are generating instructions for. */ |
fbf3f584 | 738 | enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; |
9103f4f4 L |
739 | |
740 | /* CPU feature flags of cpu we are generating instructions for. */ | |
40fb9820 | 741 | static i386_cpu_flags cpu_arch_tune_flags; |
9103f4f4 | 742 | |
ccc9c027 | 743 | /* CPU instruction set architecture used. */ |
fbf3f584 | 744 | enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; |
ccc9c027 | 745 | |
9103f4f4 | 746 | /* CPU feature flags of instruction set architecture used. */ |
fbf3f584 | 747 | i386_cpu_flags cpu_arch_isa_flags; |
9103f4f4 | 748 | |
fddf5b5b AM |
749 | /* If set, conditional jumps are not automatically promoted to handle |
750 | larger than a byte offset. */ | |
751 | static unsigned int no_cond_jump_promotion = 0; | |
752 | ||
c0f3af97 L |
753 | /* Encode SSE instructions with VEX prefix. */ |
754 | static unsigned int sse2avx; | |
755 | ||
539f890d L |
756 | /* Encode scalar AVX instructions with specific vector length. */ |
757 | static enum | |
758 | { | |
759 | vex128 = 0, | |
760 | vex256 | |
761 | } avxscalar; | |
762 | ||
03751133 L |
763 | /* Encode VEX WIG instructions with specific vex.w. */ |
764 | static enum | |
765 | { | |
766 | vexw0 = 0, | |
767 | vexw1 | |
768 | } vexwig; | |
769 | ||
43234a1e L |
770 | /* Encode scalar EVEX LIG instructions with specific vector length. */ |
771 | static enum | |
772 | { | |
773 | evexl128 = 0, | |
774 | evexl256, | |
775 | evexl512 | |
776 | } evexlig; | |
777 | ||
778 | /* Encode EVEX WIG instructions with specific evex.w. */ | |
779 | static enum | |
780 | { | |
781 | evexw0 = 0, | |
782 | evexw1 | |
783 | } evexwig; | |
784 | ||
d3d3c6db IT |
785 | /* Value to encode in EVEX RC bits, for SAE-only instructions. */ |
786 | static enum rc_type evexrcig = rne; | |
787 | ||
29b0f896 | 788 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
87c245cc | 789 | static symbolS *GOT_symbol; |
29b0f896 | 790 | |
a4447b93 RH |
791 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
792 | unsigned int x86_dwarf2_return_column; | |
793 | ||
794 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
795 | int x86_cie_data_alignment; | |
796 | ||
252b5132 | 797 | /* Interface to relax_segment. |
fddf5b5b AM |
798 | There are 3 major relax states for 386 jump insns because the |
799 | different types of jumps add different sizes to frags when we're | |
e379e5f3 L |
800 | figuring out what sort of jump to choose to reach a given label. |
801 | ||
802 | BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align | |
803 | branches which are handled by md_estimate_size_before_relax() and | |
804 | i386_generic_table_relax_frag(). */ | |
252b5132 | 805 | |
47926f60 | 806 | /* Types. */ |
93c2a809 AM |
807 | #define UNCOND_JUMP 0 |
808 | #define COND_JUMP 1 | |
809 | #define COND_JUMP86 2 | |
e379e5f3 L |
810 | #define BRANCH_PADDING 3 |
811 | #define BRANCH_PREFIX 4 | |
812 | #define FUSED_JCC_PADDING 5 | |
fddf5b5b | 813 | |
47926f60 | 814 | /* Sizes. */ |
252b5132 RH |
815 | #define CODE16 1 |
816 | #define SMALL 0 | |
29b0f896 | 817 | #define SMALL16 (SMALL | CODE16) |
252b5132 | 818 | #define BIG 2 |
29b0f896 | 819 | #define BIG16 (BIG | CODE16) |
252b5132 RH |
820 | |
821 | #ifndef INLINE | |
822 | #ifdef __GNUC__ | |
823 | #define INLINE __inline__ | |
824 | #else | |
825 | #define INLINE | |
826 | #endif | |
827 | #endif | |
828 | ||
fddf5b5b AM |
829 | #define ENCODE_RELAX_STATE(type, size) \ |
830 | ((relax_substateT) (((type) << 2) | (size))) | |
831 | #define TYPE_FROM_RELAX_STATE(s) \ | |
832 | ((s) >> 2) | |
833 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
834 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
835 | |
836 | /* This table is used by relax_frag to promote short jumps to long | |
837 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
838 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
839 | don't allow a short jump in a 32 bit code segment to be promoted to | |
840 | a 16 bit offset jump because it's slower (requires data size | |
841 | prefix), and doesn't work, unless the destination is in the bottom | |
842 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
843 | ||
844 | const relax_typeS md_relax_table[] = | |
845 | { | |
24eab124 AM |
846 | /* The fields are: |
847 | 1) most positive reach of this state, | |
848 | 2) most negative reach of this state, | |
93c2a809 | 849 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 850 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 851 | |
fddf5b5b | 852 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
853 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
854 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
855 | /* dword jmp adds 4 bytes to frag: | |
856 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 857 | {0, 0, 4, 0}, |
93c2a809 AM |
858 | /* word jmp adds 2 byte2 to frag: |
859 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
860 | {0, 0, 2, 0}, |
861 | ||
93c2a809 AM |
862 | /* COND_JUMP states. */ |
863 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
864 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
865 | /* dword conditionals adds 5 bytes to frag: | |
866 | 1 extra opcode byte, 4 displacement bytes. */ | |
867 | {0, 0, 5, 0}, | |
fddf5b5b | 868 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
869 | 1 extra opcode byte, 2 displacement bytes. */ |
870 | {0, 0, 3, 0}, | |
871 | ||
872 | /* COND_JUMP86 states. */ | |
873 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
874 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
875 | /* dword conditionals adds 5 bytes to frag: | |
876 | 1 extra opcode byte, 4 displacement bytes. */ | |
877 | {0, 0, 5, 0}, | |
878 | /* word conditionals add 4 bytes to frag: | |
879 | 1 displacement byte and a 3 byte long branch insn. */ | |
880 | {0, 0, 4, 0} | |
252b5132 RH |
881 | }; |
882 | ||
9103f4f4 L |
883 | static const arch_entry cpu_arch[] = |
884 | { | |
89507696 JB |
885 | /* Do not replace the first two entries - i386_target_format() |
886 | relies on them being there in this order. */ | |
8a2c8fef | 887 | { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32, |
293f5f65 | 888 | CPU_GENERIC32_FLAGS, 0 }, |
8a2c8fef | 889 | { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64, |
293f5f65 | 890 | CPU_GENERIC64_FLAGS, 0 }, |
8a2c8fef | 891 | { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN, |
293f5f65 | 892 | CPU_NONE_FLAGS, 0 }, |
8a2c8fef | 893 | { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN, |
293f5f65 | 894 | CPU_I186_FLAGS, 0 }, |
8a2c8fef | 895 | { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN, |
293f5f65 | 896 | CPU_I286_FLAGS, 0 }, |
8a2c8fef | 897 | { STRING_COMMA_LEN ("i386"), PROCESSOR_I386, |
293f5f65 | 898 | CPU_I386_FLAGS, 0 }, |
8a2c8fef | 899 | { STRING_COMMA_LEN ("i486"), PROCESSOR_I486, |
293f5f65 | 900 | CPU_I486_FLAGS, 0 }, |
8a2c8fef | 901 | { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM, |
293f5f65 | 902 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 903 | { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 904 | CPU_I686_FLAGS, 0 }, |
8a2c8fef | 905 | { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM, |
293f5f65 | 906 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 907 | { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 908 | CPU_PENTIUMPRO_FLAGS, 0 }, |
8a2c8fef | 909 | { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 910 | CPU_P2_FLAGS, 0 }, |
8a2c8fef | 911 | { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO, |
293f5f65 | 912 | CPU_P3_FLAGS, 0 }, |
8a2c8fef | 913 | { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4, |
293f5f65 | 914 | CPU_P4_FLAGS, 0 }, |
8a2c8fef | 915 | { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA, |
293f5f65 | 916 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 917 | { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA, |
293f5f65 | 918 | CPU_NOCONA_FLAGS, 0 }, |
8a2c8fef | 919 | { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE, |
293f5f65 | 920 | CPU_CORE_FLAGS, 1 }, |
8a2c8fef | 921 | { STRING_COMMA_LEN ("core"), PROCESSOR_CORE, |
293f5f65 | 922 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 923 | { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2, |
293f5f65 | 924 | CPU_CORE2_FLAGS, 1 }, |
8a2c8fef | 925 | { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2, |
293f5f65 | 926 | CPU_CORE2_FLAGS, 0 }, |
8a2c8fef | 927 | { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7, |
293f5f65 | 928 | CPU_COREI7_FLAGS, 0 }, |
8a2c8fef | 929 | { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM, |
293f5f65 | 930 | CPU_L1OM_FLAGS, 0 }, |
7a9068fe | 931 | { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM, |
293f5f65 | 932 | CPU_K1OM_FLAGS, 0 }, |
81486035 | 933 | { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU, |
293f5f65 | 934 | CPU_IAMCU_FLAGS, 0 }, |
8a2c8fef | 935 | { STRING_COMMA_LEN ("k6"), PROCESSOR_K6, |
293f5f65 | 936 | CPU_K6_FLAGS, 0 }, |
8a2c8fef | 937 | { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6, |
293f5f65 | 938 | CPU_K6_2_FLAGS, 0 }, |
8a2c8fef | 939 | { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON, |
293f5f65 | 940 | CPU_ATHLON_FLAGS, 0 }, |
8a2c8fef | 941 | { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8, |
293f5f65 | 942 | CPU_K8_FLAGS, 1 }, |
8a2c8fef | 943 | { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8, |
293f5f65 | 944 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 945 | { STRING_COMMA_LEN ("k8"), PROCESSOR_K8, |
293f5f65 | 946 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 947 | { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10, |
293f5f65 | 948 | CPU_AMDFAM10_FLAGS, 0 }, |
8aedb9fe | 949 | { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD, |
293f5f65 | 950 | CPU_BDVER1_FLAGS, 0 }, |
8aedb9fe | 951 | { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD, |
293f5f65 | 952 | CPU_BDVER2_FLAGS, 0 }, |
5e5c50d3 | 953 | { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD, |
293f5f65 | 954 | CPU_BDVER3_FLAGS, 0 }, |
c7b0bd56 | 955 | { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD, |
293f5f65 | 956 | CPU_BDVER4_FLAGS, 0 }, |
029f3522 | 957 | { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER, |
293f5f65 | 958 | CPU_ZNVER1_FLAGS, 0 }, |
a9660a6f AP |
959 | { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER, |
960 | CPU_ZNVER2_FLAGS, 0 }, | |
7b458c12 | 961 | { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT, |
293f5f65 | 962 | CPU_BTVER1_FLAGS, 0 }, |
7b458c12 | 963 | { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT, |
293f5f65 | 964 | CPU_BTVER2_FLAGS, 0 }, |
8a2c8fef | 965 | { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN, |
293f5f65 | 966 | CPU_8087_FLAGS, 0 }, |
8a2c8fef | 967 | { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN, |
293f5f65 | 968 | CPU_287_FLAGS, 0 }, |
8a2c8fef | 969 | { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN, |
293f5f65 | 970 | CPU_387_FLAGS, 0 }, |
1848e567 L |
971 | { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN, |
972 | CPU_687_FLAGS, 0 }, | |
d871f3f4 L |
973 | { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN, |
974 | CPU_CMOV_FLAGS, 0 }, | |
975 | { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN, | |
976 | CPU_FXSR_FLAGS, 0 }, | |
8a2c8fef | 977 | { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 978 | CPU_MMX_FLAGS, 0 }, |
8a2c8fef | 979 | { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN, |
293f5f65 | 980 | CPU_SSE_FLAGS, 0 }, |
8a2c8fef | 981 | { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN, |
293f5f65 | 982 | CPU_SSE2_FLAGS, 0 }, |
8a2c8fef | 983 | { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 984 | CPU_SSE3_FLAGS, 0 }, |
8a2c8fef | 985 | { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 986 | CPU_SSSE3_FLAGS, 0 }, |
8a2c8fef | 987 | { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN, |
293f5f65 | 988 | CPU_SSE4_1_FLAGS, 0 }, |
8a2c8fef | 989 | { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN, |
293f5f65 | 990 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 991 | { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN, |
293f5f65 | 992 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 993 | { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN, |
293f5f65 | 994 | CPU_AVX_FLAGS, 0 }, |
6c30d220 | 995 | { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN, |
293f5f65 | 996 | CPU_AVX2_FLAGS, 0 }, |
43234a1e | 997 | { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN, |
293f5f65 | 998 | CPU_AVX512F_FLAGS, 0 }, |
43234a1e | 999 | { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN, |
293f5f65 | 1000 | CPU_AVX512CD_FLAGS, 0 }, |
43234a1e | 1001 | { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN, |
293f5f65 | 1002 | CPU_AVX512ER_FLAGS, 0 }, |
43234a1e | 1003 | { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN, |
293f5f65 | 1004 | CPU_AVX512PF_FLAGS, 0 }, |
1dfc6506 | 1005 | { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN, |
293f5f65 | 1006 | CPU_AVX512DQ_FLAGS, 0 }, |
1dfc6506 | 1007 | { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN, |
293f5f65 | 1008 | CPU_AVX512BW_FLAGS, 0 }, |
1dfc6506 | 1009 | { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN, |
293f5f65 | 1010 | CPU_AVX512VL_FLAGS, 0 }, |
8a2c8fef | 1011 | { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1012 | CPU_VMX_FLAGS, 0 }, |
8729a6f6 | 1013 | { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN, |
293f5f65 | 1014 | CPU_VMFUNC_FLAGS, 0 }, |
8a2c8fef | 1015 | { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1016 | CPU_SMX_FLAGS, 0 }, |
8a2c8fef | 1017 | { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN, |
293f5f65 | 1018 | CPU_XSAVE_FLAGS, 0 }, |
c7b8aa3a | 1019 | { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 1020 | CPU_XSAVEOPT_FLAGS, 0 }, |
1dfc6506 | 1021 | { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN, |
293f5f65 | 1022 | CPU_XSAVEC_FLAGS, 0 }, |
1dfc6506 | 1023 | { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN, |
293f5f65 | 1024 | CPU_XSAVES_FLAGS, 0 }, |
8a2c8fef | 1025 | { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN, |
293f5f65 | 1026 | CPU_AES_FLAGS, 0 }, |
8a2c8fef | 1027 | { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 1028 | CPU_PCLMUL_FLAGS, 0 }, |
8a2c8fef | 1029 | { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 1030 | CPU_PCLMUL_FLAGS, 1 }, |
c7b8aa3a | 1031 | { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN, |
293f5f65 | 1032 | CPU_FSGSBASE_FLAGS, 0 }, |
c7b8aa3a | 1033 | { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN, |
293f5f65 | 1034 | CPU_RDRND_FLAGS, 0 }, |
c7b8aa3a | 1035 | { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN, |
293f5f65 | 1036 | CPU_F16C_FLAGS, 0 }, |
6c30d220 | 1037 | { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN, |
293f5f65 | 1038 | CPU_BMI2_FLAGS, 0 }, |
8a2c8fef | 1039 | { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN, |
293f5f65 | 1040 | CPU_FMA_FLAGS, 0 }, |
8a2c8fef | 1041 | { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN, |
293f5f65 | 1042 | CPU_FMA4_FLAGS, 0 }, |
8a2c8fef | 1043 | { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN, |
293f5f65 | 1044 | CPU_XOP_FLAGS, 0 }, |
8a2c8fef | 1045 | { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN, |
293f5f65 | 1046 | CPU_LWP_FLAGS, 0 }, |
8a2c8fef | 1047 | { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN, |
293f5f65 | 1048 | CPU_MOVBE_FLAGS, 0 }, |
60aa667e | 1049 | { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN, |
293f5f65 | 1050 | CPU_CX16_FLAGS, 0 }, |
8a2c8fef | 1051 | { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN, |
293f5f65 | 1052 | CPU_EPT_FLAGS, 0 }, |
6c30d220 | 1053 | { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN, |
293f5f65 | 1054 | CPU_LZCNT_FLAGS, 0 }, |
42164a71 | 1055 | { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN, |
293f5f65 | 1056 | CPU_HLE_FLAGS, 0 }, |
42164a71 | 1057 | { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN, |
293f5f65 | 1058 | CPU_RTM_FLAGS, 0 }, |
6c30d220 | 1059 | { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN, |
293f5f65 | 1060 | CPU_INVPCID_FLAGS, 0 }, |
8a2c8fef | 1061 | { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN, |
293f5f65 | 1062 | CPU_CLFLUSH_FLAGS, 0 }, |
22109423 | 1063 | { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN, |
293f5f65 | 1064 | CPU_NOP_FLAGS, 0 }, |
8a2c8fef | 1065 | { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN, |
293f5f65 | 1066 | CPU_SYSCALL_FLAGS, 0 }, |
8a2c8fef | 1067 | { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN, |
293f5f65 | 1068 | CPU_RDTSCP_FLAGS, 0 }, |
8a2c8fef | 1069 | { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN, |
293f5f65 | 1070 | CPU_3DNOW_FLAGS, 0 }, |
8a2c8fef | 1071 | { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN, |
293f5f65 | 1072 | CPU_3DNOWA_FLAGS, 0 }, |
8a2c8fef | 1073 | { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN, |
293f5f65 | 1074 | CPU_PADLOCK_FLAGS, 0 }, |
8a2c8fef | 1075 | { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN, |
293f5f65 | 1076 | CPU_SVME_FLAGS, 1 }, |
8a2c8fef | 1077 | { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN, |
293f5f65 | 1078 | CPU_SVME_FLAGS, 0 }, |
8a2c8fef | 1079 | { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, |
293f5f65 | 1080 | CPU_SSE4A_FLAGS, 0 }, |
8a2c8fef | 1081 | { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN, |
293f5f65 | 1082 | CPU_ABM_FLAGS, 0 }, |
87973e9f | 1083 | { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 1084 | CPU_BMI_FLAGS, 0 }, |
2a2a0f38 | 1085 | { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN, |
293f5f65 | 1086 | CPU_TBM_FLAGS, 0 }, |
e2e1fcde | 1087 | { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1088 | CPU_ADX_FLAGS, 0 }, |
e2e1fcde | 1089 | { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN, |
293f5f65 | 1090 | CPU_RDSEED_FLAGS, 0 }, |
e2e1fcde | 1091 | { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN, |
293f5f65 | 1092 | CPU_PRFCHW_FLAGS, 0 }, |
5c111e37 | 1093 | { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN, |
293f5f65 | 1094 | CPU_SMAP_FLAGS, 0 }, |
7e8b059b | 1095 | { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1096 | CPU_MPX_FLAGS, 0 }, |
a0046408 | 1097 | { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN, |
293f5f65 | 1098 | CPU_SHA_FLAGS, 0 }, |
963f3586 | 1099 | { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 1100 | CPU_CLFLUSHOPT_FLAGS, 0 }, |
dcf893b5 | 1101 | { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN, |
293f5f65 | 1102 | CPU_PREFETCHWT1_FLAGS, 0 }, |
2cf200a4 | 1103 | { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN, |
293f5f65 | 1104 | CPU_SE1_FLAGS, 0 }, |
c5e7287a | 1105 | { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN, |
293f5f65 | 1106 | CPU_CLWB_FLAGS, 0 }, |
2cc1b5aa | 1107 | { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN, |
293f5f65 | 1108 | CPU_AVX512IFMA_FLAGS, 0 }, |
14f195c9 | 1109 | { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 1110 | CPU_AVX512VBMI_FLAGS, 0 }, |
920d2ddc IT |
1111 | { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN, |
1112 | CPU_AVX512_4FMAPS_FLAGS, 0 }, | |
47acf0bd IT |
1113 | { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN, |
1114 | CPU_AVX512_4VNNIW_FLAGS, 0 }, | |
620214f7 IT |
1115 | { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN, |
1116 | CPU_AVX512_VPOPCNTDQ_FLAGS, 0 }, | |
53467f57 IT |
1117 | { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN, |
1118 | CPU_AVX512_VBMI2_FLAGS, 0 }, | |
8cfcb765 IT |
1119 | { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN, |
1120 | CPU_AVX512_VNNI_FLAGS, 0 }, | |
ee6872be IT |
1121 | { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN, |
1122 | CPU_AVX512_BITALG_FLAGS, 0 }, | |
029f3522 | 1123 | { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN, |
293f5f65 | 1124 | CPU_CLZERO_FLAGS, 0 }, |
9916071f | 1125 | { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1126 | CPU_MWAITX_FLAGS, 0 }, |
8eab4136 | 1127 | { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN, |
293f5f65 | 1128 | CPU_OSPKE_FLAGS, 0 }, |
8bc52696 | 1129 | { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN, |
293f5f65 | 1130 | CPU_RDPID_FLAGS, 0 }, |
6b40c462 L |
1131 | { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN, |
1132 | CPU_PTWRITE_FLAGS, 0 }, | |
d777820b IT |
1133 | { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN, |
1134 | CPU_IBT_FLAGS, 0 }, | |
1135 | { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN, | |
1136 | CPU_SHSTK_FLAGS, 0 }, | |
48521003 IT |
1137 | { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN, |
1138 | CPU_GFNI_FLAGS, 0 }, | |
8dcf1fad IT |
1139 | { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN, |
1140 | CPU_VAES_FLAGS, 0 }, | |
ff1982d5 IT |
1141 | { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN, |
1142 | CPU_VPCLMULQDQ_FLAGS, 0 }, | |
3233d7d0 IT |
1143 | { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN, |
1144 | CPU_WBNOINVD_FLAGS, 0 }, | |
be3a8dca IT |
1145 | { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN, |
1146 | CPU_PCONFIG_FLAGS, 0 }, | |
de89d0a3 IT |
1147 | { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN, |
1148 | CPU_WAITPKG_FLAGS, 0 }, | |
c48935d7 IT |
1149 | { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN, |
1150 | CPU_CLDEMOTE_FLAGS, 0 }, | |
c0a30a9f L |
1151 | { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN, |
1152 | CPU_MOVDIRI_FLAGS, 0 }, | |
1153 | { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN, | |
1154 | CPU_MOVDIR64B_FLAGS, 0 }, | |
d6aab7a1 XG |
1155 | { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN, |
1156 | CPU_AVX512_BF16_FLAGS, 0 }, | |
9186c494 L |
1157 | { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN, |
1158 | CPU_AVX512_VP2INTERSECT_FLAGS, 0 }, | |
dd455cf5 L |
1159 | { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN, |
1160 | CPU_ENQCMD_FLAGS, 0 }, | |
142861df JB |
1161 | { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN, |
1162 | CPU_RDPRU_FLAGS, 0 }, | |
1163 | { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN, | |
1164 | CPU_MCOMMIT_FLAGS, 0 }, | |
293f5f65 L |
1165 | }; |
1166 | ||
1167 | static const noarch_entry cpu_noarch[] = | |
1168 | { | |
1169 | { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS }, | |
1848e567 L |
1170 | { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS }, |
1171 | { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS }, | |
1172 | { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS }, | |
d871f3f4 L |
1173 | { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS }, |
1174 | { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS }, | |
293f5f65 L |
1175 | { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS }, |
1176 | { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS }, | |
1848e567 L |
1177 | { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS }, |
1178 | { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS }, | |
1179 | { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS }, | |
1180 | { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS }, | |
1181 | { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS }, | |
1182 | { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS }, | |
293f5f65 | 1183 | { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS }, |
1848e567 | 1184 | { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS }, |
144b71e2 L |
1185 | { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS }, |
1186 | { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS }, | |
1187 | { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS }, | |
1188 | { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS }, | |
1189 | { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS }, | |
1190 | { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS }, | |
1191 | { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS }, | |
1192 | { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS }, | |
1193 | { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS }, | |
920d2ddc | 1194 | { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS }, |
47acf0bd | 1195 | { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS }, |
620214f7 | 1196 | { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS }, |
53467f57 | 1197 | { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS }, |
8cfcb765 | 1198 | { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS }, |
ee6872be | 1199 | { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS }, |
d777820b IT |
1200 | { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS }, |
1201 | { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS }, | |
c0a30a9f L |
1202 | { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS }, |
1203 | { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS }, | |
d6aab7a1 | 1204 | { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS }, |
9186c494 | 1205 | { STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS }, |
dd455cf5 | 1206 | { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS }, |
e413e4e9 AM |
1207 | }; |
1208 | ||
704209c0 | 1209 | #ifdef I386COFF |
a6c24e68 NC |
1210 | /* Like s_lcomm_internal in gas/read.c but the alignment string |
1211 | is allowed to be optional. */ | |
1212 | ||
1213 | static symbolS * | |
1214 | pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size) | |
1215 | { | |
1216 | addressT align = 0; | |
1217 | ||
1218 | SKIP_WHITESPACE (); | |
1219 | ||
7ab9ffdd | 1220 | if (needs_align |
a6c24e68 NC |
1221 | && *input_line_pointer == ',') |
1222 | { | |
1223 | align = parse_align (needs_align - 1); | |
7ab9ffdd | 1224 | |
a6c24e68 NC |
1225 | if (align == (addressT) -1) |
1226 | return NULL; | |
1227 | } | |
1228 | else | |
1229 | { | |
1230 | if (size >= 8) | |
1231 | align = 3; | |
1232 | else if (size >= 4) | |
1233 | align = 2; | |
1234 | else if (size >= 2) | |
1235 | align = 1; | |
1236 | else | |
1237 | align = 0; | |
1238 | } | |
1239 | ||
1240 | bss_alloc (symbolP, size, align); | |
1241 | return symbolP; | |
1242 | } | |
1243 | ||
704209c0 | 1244 | static void |
a6c24e68 NC |
1245 | pe_lcomm (int needs_align) |
1246 | { | |
1247 | s_comm_internal (needs_align * 2, pe_lcomm_internal); | |
1248 | } | |
704209c0 | 1249 | #endif |
a6c24e68 | 1250 | |
29b0f896 AM |
1251 | const pseudo_typeS md_pseudo_table[] = |
1252 | { | |
1253 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) | |
1254 | {"align", s_align_bytes, 0}, | |
1255 | #else | |
1256 | {"align", s_align_ptwo, 0}, | |
1257 | #endif | |
1258 | {"arch", set_cpu_arch, 0}, | |
1259 | #ifndef I386COFF | |
1260 | {"bss", s_bss, 0}, | |
a6c24e68 NC |
1261 | #else |
1262 | {"lcomm", pe_lcomm, 1}, | |
29b0f896 AM |
1263 | #endif |
1264 | {"ffloat", float_cons, 'f'}, | |
1265 | {"dfloat", float_cons, 'd'}, | |
1266 | {"tfloat", float_cons, 'x'}, | |
1267 | {"value", cons, 2}, | |
d182319b | 1268 | {"slong", signed_cons, 4}, |
29b0f896 AM |
1269 | {"noopt", s_ignore, 0}, |
1270 | {"optim", s_ignore, 0}, | |
1271 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, | |
1272 | {"code16", set_code_flag, CODE_16BIT}, | |
1273 | {"code32", set_code_flag, CODE_32BIT}, | |
da5f19a2 | 1274 | #ifdef BFD64 |
29b0f896 | 1275 | {"code64", set_code_flag, CODE_64BIT}, |
da5f19a2 | 1276 | #endif |
29b0f896 AM |
1277 | {"intel_syntax", set_intel_syntax, 1}, |
1278 | {"att_syntax", set_intel_syntax, 0}, | |
1efbbeb4 L |
1279 | {"intel_mnemonic", set_intel_mnemonic, 1}, |
1280 | {"att_mnemonic", set_intel_mnemonic, 0}, | |
db51cc60 L |
1281 | {"allow_index_reg", set_allow_index_reg, 1}, |
1282 | {"disallow_index_reg", set_allow_index_reg, 0}, | |
7bab8ab5 JB |
1283 | {"sse_check", set_check, 0}, |
1284 | {"operand_check", set_check, 1}, | |
3b22753a L |
1285 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
1286 | {"largecomm", handle_large_common, 0}, | |
07a53e5c | 1287 | #else |
68d20676 | 1288 | {"file", dwarf2_directive_file, 0}, |
07a53e5c RH |
1289 | {"loc", dwarf2_directive_loc, 0}, |
1290 | {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, | |
3b22753a | 1291 | #endif |
6482c264 NC |
1292 | #ifdef TE_PE |
1293 | {"secrel32", pe_directive_secrel, 0}, | |
1294 | #endif | |
29b0f896 AM |
1295 | {0, 0, 0} |
1296 | }; | |
1297 | ||
1298 | /* For interface with expression (). */ | |
1299 | extern char *input_line_pointer; | |
1300 | ||
1301 | /* Hash table for instruction mnemonic lookup. */ | |
1302 | static struct hash_control *op_hash; | |
1303 | ||
1304 | /* Hash table for register lookup. */ | |
1305 | static struct hash_control *reg_hash; | |
1306 | \f | |
ce8a8b2f AM |
1307 | /* Various efficient no-op patterns for aligning code labels. |
1308 | Note: Don't try to assemble the instructions in the comments. | |
1309 | 0L and 0w are not legal. */ | |
62a02d25 L |
1310 | static const unsigned char f32_1[] = |
1311 | {0x90}; /* nop */ | |
1312 | static const unsigned char f32_2[] = | |
1313 | {0x66,0x90}; /* xchg %ax,%ax */ | |
1314 | static const unsigned char f32_3[] = | |
1315 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
1316 | static const unsigned char f32_4[] = | |
1317 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
62a02d25 L |
1318 | static const unsigned char f32_6[] = |
1319 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
1320 | static const unsigned char f32_7[] = | |
1321 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
62a02d25 | 1322 | static const unsigned char f16_3[] = |
3ae729d5 | 1323 | {0x8d,0x74,0x00}; /* lea 0(%si),%si */ |
62a02d25 | 1324 | static const unsigned char f16_4[] = |
3ae729d5 L |
1325 | {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */ |
1326 | static const unsigned char jump_disp8[] = | |
1327 | {0xeb}; /* jmp disp8 */ | |
1328 | static const unsigned char jump32_disp32[] = | |
1329 | {0xe9}; /* jmp disp32 */ | |
1330 | static const unsigned char jump16_disp32[] = | |
1331 | {0x66,0xe9}; /* jmp disp32 */ | |
62a02d25 L |
1332 | /* 32-bit NOPs patterns. */ |
1333 | static const unsigned char *const f32_patt[] = { | |
3ae729d5 | 1334 | f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7 |
62a02d25 L |
1335 | }; |
1336 | /* 16-bit NOPs patterns. */ | |
1337 | static const unsigned char *const f16_patt[] = { | |
3ae729d5 | 1338 | f32_1, f32_2, f16_3, f16_4 |
62a02d25 L |
1339 | }; |
1340 | /* nopl (%[re]ax) */ | |
1341 | static const unsigned char alt_3[] = | |
1342 | {0x0f,0x1f,0x00}; | |
1343 | /* nopl 0(%[re]ax) */ | |
1344 | static const unsigned char alt_4[] = | |
1345 | {0x0f,0x1f,0x40,0x00}; | |
1346 | /* nopl 0(%[re]ax,%[re]ax,1) */ | |
1347 | static const unsigned char alt_5[] = | |
1348 | {0x0f,0x1f,0x44,0x00,0x00}; | |
1349 | /* nopw 0(%[re]ax,%[re]ax,1) */ | |
1350 | static const unsigned char alt_6[] = | |
1351 | {0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
1352 | /* nopl 0L(%[re]ax) */ | |
1353 | static const unsigned char alt_7[] = | |
1354 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
1355 | /* nopl 0L(%[re]ax,%[re]ax,1) */ | |
1356 | static const unsigned char alt_8[] = | |
1357 | {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1358 | /* nopw 0L(%[re]ax,%[re]ax,1) */ | |
1359 | static const unsigned char alt_9[] = | |
1360 | {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1361 | /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
1362 | static const unsigned char alt_10[] = | |
1363 | {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
3ae729d5 L |
1364 | /* data16 nopw %cs:0L(%eax,%eax,1) */ |
1365 | static const unsigned char alt_11[] = | |
1366 | {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
62a02d25 L |
1367 | /* 32-bit and 64-bit NOPs patterns. */ |
1368 | static const unsigned char *const alt_patt[] = { | |
1369 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
3ae729d5 | 1370 | alt_9, alt_10, alt_11 |
62a02d25 L |
1371 | }; |
1372 | ||
1373 | /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum | |
1374 | size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */ | |
1375 | ||
1376 | static void | |
1377 | i386_output_nops (char *where, const unsigned char *const *patt, | |
1378 | int count, int max_single_nop_size) | |
1379 | ||
1380 | { | |
3ae729d5 L |
1381 | /* Place the longer NOP first. */ |
1382 | int last; | |
1383 | int offset; | |
3076e594 NC |
1384 | const unsigned char *nops; |
1385 | ||
1386 | if (max_single_nop_size < 1) | |
1387 | { | |
1388 | as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"), | |
1389 | max_single_nop_size); | |
1390 | return; | |
1391 | } | |
1392 | ||
1393 | nops = patt[max_single_nop_size - 1]; | |
3ae729d5 L |
1394 | |
1395 | /* Use the smaller one if the requsted one isn't available. */ | |
1396 | if (nops == NULL) | |
62a02d25 | 1397 | { |
3ae729d5 L |
1398 | max_single_nop_size--; |
1399 | nops = patt[max_single_nop_size - 1]; | |
62a02d25 L |
1400 | } |
1401 | ||
3ae729d5 L |
1402 | last = count % max_single_nop_size; |
1403 | ||
1404 | count -= last; | |
1405 | for (offset = 0; offset < count; offset += max_single_nop_size) | |
1406 | memcpy (where + offset, nops, max_single_nop_size); | |
1407 | ||
1408 | if (last) | |
1409 | { | |
1410 | nops = patt[last - 1]; | |
1411 | if (nops == NULL) | |
1412 | { | |
1413 | /* Use the smaller one plus one-byte NOP if the needed one | |
1414 | isn't available. */ | |
1415 | last--; | |
1416 | nops = patt[last - 1]; | |
1417 | memcpy (where + offset, nops, last); | |
1418 | where[offset + last] = *patt[0]; | |
1419 | } | |
1420 | else | |
1421 | memcpy (where + offset, nops, last); | |
1422 | } | |
62a02d25 L |
1423 | } |
1424 | ||
3ae729d5 L |
1425 | static INLINE int |
1426 | fits_in_imm7 (offsetT num) | |
1427 | { | |
1428 | return (num & 0x7f) == num; | |
1429 | } | |
1430 | ||
1431 | static INLINE int | |
1432 | fits_in_imm31 (offsetT num) | |
1433 | { | |
1434 | return (num & 0x7fffffff) == num; | |
1435 | } | |
62a02d25 L |
1436 | |
1437 | /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a | |
1438 | single NOP instruction LIMIT. */ | |
1439 | ||
1440 | void | |
3ae729d5 | 1441 | i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit) |
62a02d25 | 1442 | { |
3ae729d5 | 1443 | const unsigned char *const *patt = NULL; |
62a02d25 | 1444 | int max_single_nop_size; |
3ae729d5 L |
1445 | /* Maximum number of NOPs before switching to jump over NOPs. */ |
1446 | int max_number_of_nops; | |
62a02d25 | 1447 | |
3ae729d5 | 1448 | switch (fragP->fr_type) |
62a02d25 | 1449 | { |
3ae729d5 L |
1450 | case rs_fill_nop: |
1451 | case rs_align_code: | |
1452 | break; | |
e379e5f3 L |
1453 | case rs_machine_dependent: |
1454 | /* Allow NOP padding for jumps and calls. */ | |
1455 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING | |
1456 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
1457 | break; | |
1458 | /* Fall through. */ | |
3ae729d5 | 1459 | default: |
62a02d25 L |
1460 | return; |
1461 | } | |
1462 | ||
ccc9c027 L |
1463 | /* We need to decide which NOP sequence to use for 32bit and |
1464 | 64bit. When -mtune= is used: | |
4eed87de | 1465 | |
76bc74dc L |
1466 | 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and |
1467 | PROCESSOR_GENERIC32, f32_patt will be used. | |
80b8656c L |
1468 | 2. For the rest, alt_patt will be used. |
1469 | ||
1470 | When -mtune= isn't used, alt_patt will be used if | |
22109423 | 1471 | cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will |
76bc74dc | 1472 | be used. |
ccc9c027 L |
1473 | |
1474 | When -march= or .arch is used, we can't use anything beyond | |
1475 | cpu_arch_isa_flags. */ | |
1476 | ||
1477 | if (flag_code == CODE_16BIT) | |
1478 | { | |
3ae729d5 L |
1479 | patt = f16_patt; |
1480 | max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]); | |
1481 | /* Limit number of NOPs to 2 in 16-bit mode. */ | |
1482 | max_number_of_nops = 2; | |
252b5132 | 1483 | } |
33fef721 | 1484 | else |
ccc9c027 | 1485 | { |
fbf3f584 | 1486 | if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN) |
ccc9c027 L |
1487 | { |
1488 | /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ | |
1489 | switch (cpu_arch_tune) | |
1490 | { | |
1491 | case PROCESSOR_UNKNOWN: | |
1492 | /* We use cpu_arch_isa_flags to check if we SHOULD | |
22109423 L |
1493 | optimize with nops. */ |
1494 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1495 | patt = alt_patt; |
ccc9c027 L |
1496 | else |
1497 | patt = f32_patt; | |
1498 | break; | |
ccc9c027 L |
1499 | case PROCESSOR_PENTIUM4: |
1500 | case PROCESSOR_NOCONA: | |
ef05d495 | 1501 | case PROCESSOR_CORE: |
76bc74dc | 1502 | case PROCESSOR_CORE2: |
bd5295b2 | 1503 | case PROCESSOR_COREI7: |
3632d14b | 1504 | case PROCESSOR_L1OM: |
7a9068fe | 1505 | case PROCESSOR_K1OM: |
76bc74dc | 1506 | case PROCESSOR_GENERIC64: |
ccc9c027 L |
1507 | case PROCESSOR_K6: |
1508 | case PROCESSOR_ATHLON: | |
1509 | case PROCESSOR_K8: | |
4eed87de | 1510 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1511 | case PROCESSOR_BD: |
029f3522 | 1512 | case PROCESSOR_ZNVER: |
7b458c12 | 1513 | case PROCESSOR_BT: |
80b8656c | 1514 | patt = alt_patt; |
ccc9c027 | 1515 | break; |
76bc74dc | 1516 | case PROCESSOR_I386: |
ccc9c027 L |
1517 | case PROCESSOR_I486: |
1518 | case PROCESSOR_PENTIUM: | |
2dde1948 | 1519 | case PROCESSOR_PENTIUMPRO: |
81486035 | 1520 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1521 | case PROCESSOR_GENERIC32: |
1522 | patt = f32_patt; | |
1523 | break; | |
4eed87de | 1524 | } |
ccc9c027 L |
1525 | } |
1526 | else | |
1527 | { | |
fbf3f584 | 1528 | switch (fragP->tc_frag_data.tune) |
ccc9c027 L |
1529 | { |
1530 | case PROCESSOR_UNKNOWN: | |
e6a14101 | 1531 | /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be |
ccc9c027 L |
1532 | PROCESSOR_UNKNOWN. */ |
1533 | abort (); | |
1534 | break; | |
1535 | ||
76bc74dc | 1536 | case PROCESSOR_I386: |
ccc9c027 L |
1537 | case PROCESSOR_I486: |
1538 | case PROCESSOR_PENTIUM: | |
81486035 | 1539 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1540 | case PROCESSOR_K6: |
1541 | case PROCESSOR_ATHLON: | |
1542 | case PROCESSOR_K8: | |
4eed87de | 1543 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1544 | case PROCESSOR_BD: |
029f3522 | 1545 | case PROCESSOR_ZNVER: |
7b458c12 | 1546 | case PROCESSOR_BT: |
ccc9c027 L |
1547 | case PROCESSOR_GENERIC32: |
1548 | /* We use cpu_arch_isa_flags to check if we CAN optimize | |
22109423 L |
1549 | with nops. */ |
1550 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1551 | patt = alt_patt; |
ccc9c027 L |
1552 | else |
1553 | patt = f32_patt; | |
1554 | break; | |
76bc74dc L |
1555 | case PROCESSOR_PENTIUMPRO: |
1556 | case PROCESSOR_PENTIUM4: | |
1557 | case PROCESSOR_NOCONA: | |
1558 | case PROCESSOR_CORE: | |
ef05d495 | 1559 | case PROCESSOR_CORE2: |
bd5295b2 | 1560 | case PROCESSOR_COREI7: |
3632d14b | 1561 | case PROCESSOR_L1OM: |
7a9068fe | 1562 | case PROCESSOR_K1OM: |
22109423 | 1563 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) |
80b8656c | 1564 | patt = alt_patt; |
ccc9c027 L |
1565 | else |
1566 | patt = f32_patt; | |
1567 | break; | |
1568 | case PROCESSOR_GENERIC64: | |
80b8656c | 1569 | patt = alt_patt; |
ccc9c027 | 1570 | break; |
4eed87de | 1571 | } |
ccc9c027 L |
1572 | } |
1573 | ||
76bc74dc L |
1574 | if (patt == f32_patt) |
1575 | { | |
3ae729d5 L |
1576 | max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]); |
1577 | /* Limit number of NOPs to 2 for older processors. */ | |
1578 | max_number_of_nops = 2; | |
76bc74dc L |
1579 | } |
1580 | else | |
1581 | { | |
3ae729d5 L |
1582 | max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]); |
1583 | /* Limit number of NOPs to 7 for newer processors. */ | |
1584 | max_number_of_nops = 7; | |
1585 | } | |
1586 | } | |
1587 | ||
1588 | if (limit == 0) | |
1589 | limit = max_single_nop_size; | |
1590 | ||
1591 | if (fragP->fr_type == rs_fill_nop) | |
1592 | { | |
1593 | /* Output NOPs for .nop directive. */ | |
1594 | if (limit > max_single_nop_size) | |
1595 | { | |
1596 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1597 | _("invalid single nop size: %d " | |
1598 | "(expect within [0, %d])"), | |
1599 | limit, max_single_nop_size); | |
1600 | return; | |
1601 | } | |
1602 | } | |
e379e5f3 | 1603 | else if (fragP->fr_type != rs_machine_dependent) |
3ae729d5 L |
1604 | fragP->fr_var = count; |
1605 | ||
1606 | if ((count / max_single_nop_size) > max_number_of_nops) | |
1607 | { | |
1608 | /* Generate jump over NOPs. */ | |
1609 | offsetT disp = count - 2; | |
1610 | if (fits_in_imm7 (disp)) | |
1611 | { | |
1612 | /* Use "jmp disp8" if possible. */ | |
1613 | count = disp; | |
1614 | where[0] = jump_disp8[0]; | |
1615 | where[1] = count; | |
1616 | where += 2; | |
1617 | } | |
1618 | else | |
1619 | { | |
1620 | unsigned int size_of_jump; | |
1621 | ||
1622 | if (flag_code == CODE_16BIT) | |
1623 | { | |
1624 | where[0] = jump16_disp32[0]; | |
1625 | where[1] = jump16_disp32[1]; | |
1626 | size_of_jump = 2; | |
1627 | } | |
1628 | else | |
1629 | { | |
1630 | where[0] = jump32_disp32[0]; | |
1631 | size_of_jump = 1; | |
1632 | } | |
1633 | ||
1634 | count -= size_of_jump + 4; | |
1635 | if (!fits_in_imm31 (count)) | |
1636 | { | |
1637 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1638 | _("jump over nop padding out of range")); | |
1639 | return; | |
1640 | } | |
1641 | ||
1642 | md_number_to_chars (where + size_of_jump, count, 4); | |
1643 | where += size_of_jump + 4; | |
76bc74dc | 1644 | } |
ccc9c027 | 1645 | } |
3ae729d5 L |
1646 | |
1647 | /* Generate multiple NOPs. */ | |
1648 | i386_output_nops (where, patt, count, limit); | |
252b5132 RH |
1649 | } |
1650 | ||
c6fb90c8 | 1651 | static INLINE int |
0dfbf9d7 | 1652 | operand_type_all_zero (const union i386_operand_type *x) |
40fb9820 | 1653 | { |
0dfbf9d7 | 1654 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1655 | { |
1656 | case 3: | |
0dfbf9d7 | 1657 | if (x->array[2]) |
c6fb90c8 | 1658 | return 0; |
1a0670f3 | 1659 | /* Fall through. */ |
c6fb90c8 | 1660 | case 2: |
0dfbf9d7 | 1661 | if (x->array[1]) |
c6fb90c8 | 1662 | return 0; |
1a0670f3 | 1663 | /* Fall through. */ |
c6fb90c8 | 1664 | case 1: |
0dfbf9d7 | 1665 | return !x->array[0]; |
c6fb90c8 L |
1666 | default: |
1667 | abort (); | |
1668 | } | |
40fb9820 L |
1669 | } |
1670 | ||
c6fb90c8 | 1671 | static INLINE void |
0dfbf9d7 | 1672 | operand_type_set (union i386_operand_type *x, unsigned int v) |
40fb9820 | 1673 | { |
0dfbf9d7 | 1674 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1675 | { |
1676 | case 3: | |
0dfbf9d7 | 1677 | x->array[2] = v; |
1a0670f3 | 1678 | /* Fall through. */ |
c6fb90c8 | 1679 | case 2: |
0dfbf9d7 | 1680 | x->array[1] = v; |
1a0670f3 | 1681 | /* Fall through. */ |
c6fb90c8 | 1682 | case 1: |
0dfbf9d7 | 1683 | x->array[0] = v; |
1a0670f3 | 1684 | /* Fall through. */ |
c6fb90c8 L |
1685 | break; |
1686 | default: | |
1687 | abort (); | |
1688 | } | |
bab6aec1 JB |
1689 | |
1690 | x->bitfield.class = ClassNone; | |
75e5731b | 1691 | x->bitfield.instance = InstanceNone; |
c6fb90c8 | 1692 | } |
40fb9820 | 1693 | |
c6fb90c8 | 1694 | static INLINE int |
0dfbf9d7 L |
1695 | operand_type_equal (const union i386_operand_type *x, |
1696 | const union i386_operand_type *y) | |
c6fb90c8 | 1697 | { |
0dfbf9d7 | 1698 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1699 | { |
1700 | case 3: | |
0dfbf9d7 | 1701 | if (x->array[2] != y->array[2]) |
c6fb90c8 | 1702 | return 0; |
1a0670f3 | 1703 | /* Fall through. */ |
c6fb90c8 | 1704 | case 2: |
0dfbf9d7 | 1705 | if (x->array[1] != y->array[1]) |
c6fb90c8 | 1706 | return 0; |
1a0670f3 | 1707 | /* Fall through. */ |
c6fb90c8 | 1708 | case 1: |
0dfbf9d7 | 1709 | return x->array[0] == y->array[0]; |
c6fb90c8 L |
1710 | break; |
1711 | default: | |
1712 | abort (); | |
1713 | } | |
1714 | } | |
40fb9820 | 1715 | |
0dfbf9d7 L |
1716 | static INLINE int |
1717 | cpu_flags_all_zero (const union i386_cpu_flags *x) | |
1718 | { | |
1719 | switch (ARRAY_SIZE(x->array)) | |
1720 | { | |
53467f57 IT |
1721 | case 4: |
1722 | if (x->array[3]) | |
1723 | return 0; | |
1724 | /* Fall through. */ | |
0dfbf9d7 L |
1725 | case 3: |
1726 | if (x->array[2]) | |
1727 | return 0; | |
1a0670f3 | 1728 | /* Fall through. */ |
0dfbf9d7 L |
1729 | case 2: |
1730 | if (x->array[1]) | |
1731 | return 0; | |
1a0670f3 | 1732 | /* Fall through. */ |
0dfbf9d7 L |
1733 | case 1: |
1734 | return !x->array[0]; | |
1735 | default: | |
1736 | abort (); | |
1737 | } | |
1738 | } | |
1739 | ||
0dfbf9d7 L |
1740 | static INLINE int |
1741 | cpu_flags_equal (const union i386_cpu_flags *x, | |
1742 | const union i386_cpu_flags *y) | |
1743 | { | |
1744 | switch (ARRAY_SIZE(x->array)) | |
1745 | { | |
53467f57 IT |
1746 | case 4: |
1747 | if (x->array[3] != y->array[3]) | |
1748 | return 0; | |
1749 | /* Fall through. */ | |
0dfbf9d7 L |
1750 | case 3: |
1751 | if (x->array[2] != y->array[2]) | |
1752 | return 0; | |
1a0670f3 | 1753 | /* Fall through. */ |
0dfbf9d7 L |
1754 | case 2: |
1755 | if (x->array[1] != y->array[1]) | |
1756 | return 0; | |
1a0670f3 | 1757 | /* Fall through. */ |
0dfbf9d7 L |
1758 | case 1: |
1759 | return x->array[0] == y->array[0]; | |
1760 | break; | |
1761 | default: | |
1762 | abort (); | |
1763 | } | |
1764 | } | |
c6fb90c8 L |
1765 | |
1766 | static INLINE int | |
1767 | cpu_flags_check_cpu64 (i386_cpu_flags f) | |
1768 | { | |
1769 | return !((flag_code == CODE_64BIT && f.bitfield.cpuno64) | |
1770 | || (flag_code != CODE_64BIT && f.bitfield.cpu64)); | |
40fb9820 L |
1771 | } |
1772 | ||
c6fb90c8 L |
1773 | static INLINE i386_cpu_flags |
1774 | cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1775 | { |
c6fb90c8 L |
1776 | switch (ARRAY_SIZE (x.array)) |
1777 | { | |
53467f57 IT |
1778 | case 4: |
1779 | x.array [3] &= y.array [3]; | |
1780 | /* Fall through. */ | |
c6fb90c8 L |
1781 | case 3: |
1782 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1783 | /* Fall through. */ |
c6fb90c8 L |
1784 | case 2: |
1785 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1786 | /* Fall through. */ |
c6fb90c8 L |
1787 | case 1: |
1788 | x.array [0] &= y.array [0]; | |
1789 | break; | |
1790 | default: | |
1791 | abort (); | |
1792 | } | |
1793 | return x; | |
1794 | } | |
40fb9820 | 1795 | |
c6fb90c8 L |
1796 | static INLINE i386_cpu_flags |
1797 | cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1798 | { |
c6fb90c8 | 1799 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1800 | { |
53467f57 IT |
1801 | case 4: |
1802 | x.array [3] |= y.array [3]; | |
1803 | /* Fall through. */ | |
c6fb90c8 L |
1804 | case 3: |
1805 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1806 | /* Fall through. */ |
c6fb90c8 L |
1807 | case 2: |
1808 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1809 | /* Fall through. */ |
c6fb90c8 L |
1810 | case 1: |
1811 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1812 | break; |
1813 | default: | |
1814 | abort (); | |
1815 | } | |
40fb9820 L |
1816 | return x; |
1817 | } | |
1818 | ||
309d3373 JB |
1819 | static INLINE i386_cpu_flags |
1820 | cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y) | |
1821 | { | |
1822 | switch (ARRAY_SIZE (x.array)) | |
1823 | { | |
53467f57 IT |
1824 | case 4: |
1825 | x.array [3] &= ~y.array [3]; | |
1826 | /* Fall through. */ | |
309d3373 JB |
1827 | case 3: |
1828 | x.array [2] &= ~y.array [2]; | |
1a0670f3 | 1829 | /* Fall through. */ |
309d3373 JB |
1830 | case 2: |
1831 | x.array [1] &= ~y.array [1]; | |
1a0670f3 | 1832 | /* Fall through. */ |
309d3373 JB |
1833 | case 1: |
1834 | x.array [0] &= ~y.array [0]; | |
1835 | break; | |
1836 | default: | |
1837 | abort (); | |
1838 | } | |
1839 | return x; | |
1840 | } | |
1841 | ||
c0f3af97 L |
1842 | #define CPU_FLAGS_ARCH_MATCH 0x1 |
1843 | #define CPU_FLAGS_64BIT_MATCH 0x2 | |
1844 | ||
c0f3af97 | 1845 | #define CPU_FLAGS_PERFECT_MATCH \ |
db12e14e | 1846 | (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH) |
c0f3af97 L |
1847 | |
1848 | /* Return CPU flags match bits. */ | |
3629bb00 | 1849 | |
40fb9820 | 1850 | static int |
d3ce72d0 | 1851 | cpu_flags_match (const insn_template *t) |
40fb9820 | 1852 | { |
c0f3af97 L |
1853 | i386_cpu_flags x = t->cpu_flags; |
1854 | int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0; | |
40fb9820 L |
1855 | |
1856 | x.bitfield.cpu64 = 0; | |
1857 | x.bitfield.cpuno64 = 0; | |
1858 | ||
0dfbf9d7 | 1859 | if (cpu_flags_all_zero (&x)) |
c0f3af97 L |
1860 | { |
1861 | /* This instruction is available on all archs. */ | |
db12e14e | 1862 | match |= CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1863 | } |
3629bb00 L |
1864 | else |
1865 | { | |
c0f3af97 | 1866 | /* This instruction is available only on some archs. */ |
3629bb00 L |
1867 | i386_cpu_flags cpu = cpu_arch_flags; |
1868 | ||
ab592e75 JB |
1869 | /* AVX512VL is no standalone feature - match it and then strip it. */ |
1870 | if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl) | |
1871 | return match; | |
1872 | x.bitfield.cpuavx512vl = 0; | |
1873 | ||
3629bb00 | 1874 | cpu = cpu_flags_and (x, cpu); |
c0f3af97 L |
1875 | if (!cpu_flags_all_zero (&cpu)) |
1876 | { | |
a5ff0eb2 L |
1877 | if (x.bitfield.cpuavx) |
1878 | { | |
929f69fa | 1879 | /* We need to check a few extra flags with AVX. */ |
b9d49817 JB |
1880 | if (cpu.bitfield.cpuavx |
1881 | && (!t->opcode_modifier.sse2avx || sse2avx) | |
1882 | && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes) | |
929f69fa | 1883 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) |
b9d49817 JB |
1884 | && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul)) |
1885 | match |= CPU_FLAGS_ARCH_MATCH; | |
a5ff0eb2 | 1886 | } |
929f69fa JB |
1887 | else if (x.bitfield.cpuavx512f) |
1888 | { | |
1889 | /* We need to check a few extra flags with AVX512F. */ | |
1890 | if (cpu.bitfield.cpuavx512f | |
1891 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) | |
1892 | && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes) | |
1893 | && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq)) | |
1894 | match |= CPU_FLAGS_ARCH_MATCH; | |
1895 | } | |
a5ff0eb2 | 1896 | else |
db12e14e | 1897 | match |= CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1898 | } |
3629bb00 | 1899 | } |
c0f3af97 | 1900 | return match; |
40fb9820 L |
1901 | } |
1902 | ||
c6fb90c8 L |
1903 | static INLINE i386_operand_type |
1904 | operand_type_and (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1905 | { |
bab6aec1 JB |
1906 | if (x.bitfield.class != y.bitfield.class) |
1907 | x.bitfield.class = ClassNone; | |
75e5731b JB |
1908 | if (x.bitfield.instance != y.bitfield.instance) |
1909 | x.bitfield.instance = InstanceNone; | |
bab6aec1 | 1910 | |
c6fb90c8 L |
1911 | switch (ARRAY_SIZE (x.array)) |
1912 | { | |
1913 | case 3: | |
1914 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1915 | /* Fall through. */ |
c6fb90c8 L |
1916 | case 2: |
1917 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1918 | /* Fall through. */ |
c6fb90c8 L |
1919 | case 1: |
1920 | x.array [0] &= y.array [0]; | |
1921 | break; | |
1922 | default: | |
1923 | abort (); | |
1924 | } | |
1925 | return x; | |
40fb9820 L |
1926 | } |
1927 | ||
73053c1f JB |
1928 | static INLINE i386_operand_type |
1929 | operand_type_and_not (i386_operand_type x, i386_operand_type y) | |
1930 | { | |
bab6aec1 | 1931 | gas_assert (y.bitfield.class == ClassNone); |
75e5731b | 1932 | gas_assert (y.bitfield.instance == InstanceNone); |
bab6aec1 | 1933 | |
73053c1f JB |
1934 | switch (ARRAY_SIZE (x.array)) |
1935 | { | |
1936 | case 3: | |
1937 | x.array [2] &= ~y.array [2]; | |
1938 | /* Fall through. */ | |
1939 | case 2: | |
1940 | x.array [1] &= ~y.array [1]; | |
1941 | /* Fall through. */ | |
1942 | case 1: | |
1943 | x.array [0] &= ~y.array [0]; | |
1944 | break; | |
1945 | default: | |
1946 | abort (); | |
1947 | } | |
1948 | return x; | |
1949 | } | |
1950 | ||
c6fb90c8 L |
1951 | static INLINE i386_operand_type |
1952 | operand_type_or (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1953 | { |
bab6aec1 JB |
1954 | gas_assert (x.bitfield.class == ClassNone || |
1955 | y.bitfield.class == ClassNone || | |
1956 | x.bitfield.class == y.bitfield.class); | |
75e5731b JB |
1957 | gas_assert (x.bitfield.instance == InstanceNone || |
1958 | y.bitfield.instance == InstanceNone || | |
1959 | x.bitfield.instance == y.bitfield.instance); | |
bab6aec1 | 1960 | |
c6fb90c8 | 1961 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1962 | { |
c6fb90c8 L |
1963 | case 3: |
1964 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1965 | /* Fall through. */ |
c6fb90c8 L |
1966 | case 2: |
1967 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1968 | /* Fall through. */ |
c6fb90c8 L |
1969 | case 1: |
1970 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1971 | break; |
1972 | default: | |
1973 | abort (); | |
1974 | } | |
c6fb90c8 L |
1975 | return x; |
1976 | } | |
40fb9820 | 1977 | |
c6fb90c8 L |
1978 | static INLINE i386_operand_type |
1979 | operand_type_xor (i386_operand_type x, i386_operand_type y) | |
1980 | { | |
bab6aec1 | 1981 | gas_assert (y.bitfield.class == ClassNone); |
75e5731b | 1982 | gas_assert (y.bitfield.instance == InstanceNone); |
bab6aec1 | 1983 | |
c6fb90c8 L |
1984 | switch (ARRAY_SIZE (x.array)) |
1985 | { | |
1986 | case 3: | |
1987 | x.array [2] ^= y.array [2]; | |
1a0670f3 | 1988 | /* Fall through. */ |
c6fb90c8 L |
1989 | case 2: |
1990 | x.array [1] ^= y.array [1]; | |
1a0670f3 | 1991 | /* Fall through. */ |
c6fb90c8 L |
1992 | case 1: |
1993 | x.array [0] ^= y.array [0]; | |
1994 | break; | |
1995 | default: | |
1996 | abort (); | |
1997 | } | |
40fb9820 L |
1998 | return x; |
1999 | } | |
2000 | ||
40fb9820 L |
2001 | static const i386_operand_type disp16 = OPERAND_TYPE_DISP16; |
2002 | static const i386_operand_type disp32 = OPERAND_TYPE_DISP32; | |
2003 | static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S; | |
2004 | static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32; | |
bab6aec1 JB |
2005 | static const i386_operand_type anydisp = OPERAND_TYPE_ANYDISP; |
2006 | static const i386_operand_type anyimm = OPERAND_TYPE_ANYIMM; | |
40fb9820 | 2007 | static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM; |
43234a1e | 2008 | static const i386_operand_type regmask = OPERAND_TYPE_REGMASK; |
40fb9820 L |
2009 | static const i386_operand_type imm8 = OPERAND_TYPE_IMM8; |
2010 | static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S; | |
2011 | static const i386_operand_type imm16 = OPERAND_TYPE_IMM16; | |
2012 | static const i386_operand_type imm32 = OPERAND_TYPE_IMM32; | |
2013 | static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S; | |
2014 | static const i386_operand_type imm64 = OPERAND_TYPE_IMM64; | |
2015 | static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32; | |
2016 | static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S; | |
2017 | static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S; | |
2018 | ||
2019 | enum operand_type | |
2020 | { | |
2021 | reg, | |
40fb9820 L |
2022 | imm, |
2023 | disp, | |
2024 | anymem | |
2025 | }; | |
2026 | ||
c6fb90c8 | 2027 | static INLINE int |
40fb9820 L |
2028 | operand_type_check (i386_operand_type t, enum operand_type c) |
2029 | { | |
2030 | switch (c) | |
2031 | { | |
2032 | case reg: | |
bab6aec1 | 2033 | return t.bitfield.class == Reg; |
40fb9820 | 2034 | |
40fb9820 L |
2035 | case imm: |
2036 | return (t.bitfield.imm8 | |
2037 | || t.bitfield.imm8s | |
2038 | || t.bitfield.imm16 | |
2039 | || t.bitfield.imm32 | |
2040 | || t.bitfield.imm32s | |
2041 | || t.bitfield.imm64); | |
2042 | ||
2043 | case disp: | |
2044 | return (t.bitfield.disp8 | |
2045 | || t.bitfield.disp16 | |
2046 | || t.bitfield.disp32 | |
2047 | || t.bitfield.disp32s | |
2048 | || t.bitfield.disp64); | |
2049 | ||
2050 | case anymem: | |
2051 | return (t.bitfield.disp8 | |
2052 | || t.bitfield.disp16 | |
2053 | || t.bitfield.disp32 | |
2054 | || t.bitfield.disp32s | |
2055 | || t.bitfield.disp64 | |
2056 | || t.bitfield.baseindex); | |
2057 | ||
2058 | default: | |
2059 | abort (); | |
2060 | } | |
2cfe26b6 AM |
2061 | |
2062 | return 0; | |
40fb9820 L |
2063 | } |
2064 | ||
7a54636a L |
2065 | /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size |
2066 | between operand GIVEN and opeand WANTED for instruction template T. */ | |
5c07affc L |
2067 | |
2068 | static INLINE int | |
7a54636a L |
2069 | match_operand_size (const insn_template *t, unsigned int wanted, |
2070 | unsigned int given) | |
5c07affc | 2071 | { |
3ac21baa JB |
2072 | return !((i.types[given].bitfield.byte |
2073 | && !t->operand_types[wanted].bitfield.byte) | |
2074 | || (i.types[given].bitfield.word | |
2075 | && !t->operand_types[wanted].bitfield.word) | |
2076 | || (i.types[given].bitfield.dword | |
2077 | && !t->operand_types[wanted].bitfield.dword) | |
2078 | || (i.types[given].bitfield.qword | |
2079 | && !t->operand_types[wanted].bitfield.qword) | |
2080 | || (i.types[given].bitfield.tbyte | |
2081 | && !t->operand_types[wanted].bitfield.tbyte)); | |
5c07affc L |
2082 | } |
2083 | ||
dd40ce22 L |
2084 | /* Return 1 if there is no conflict in SIMD register between operand |
2085 | GIVEN and opeand WANTED for instruction template T. */ | |
1b54b8d7 JB |
2086 | |
2087 | static INLINE int | |
dd40ce22 L |
2088 | match_simd_size (const insn_template *t, unsigned int wanted, |
2089 | unsigned int given) | |
1b54b8d7 | 2090 | { |
3ac21baa JB |
2091 | return !((i.types[given].bitfield.xmmword |
2092 | && !t->operand_types[wanted].bitfield.xmmword) | |
2093 | || (i.types[given].bitfield.ymmword | |
2094 | && !t->operand_types[wanted].bitfield.ymmword) | |
2095 | || (i.types[given].bitfield.zmmword | |
2096 | && !t->operand_types[wanted].bitfield.zmmword)); | |
1b54b8d7 JB |
2097 | } |
2098 | ||
7a54636a L |
2099 | /* Return 1 if there is no conflict in any size between operand GIVEN |
2100 | and opeand WANTED for instruction template T. */ | |
5c07affc L |
2101 | |
2102 | static INLINE int | |
dd40ce22 L |
2103 | match_mem_size (const insn_template *t, unsigned int wanted, |
2104 | unsigned int given) | |
5c07affc | 2105 | { |
7a54636a | 2106 | return (match_operand_size (t, wanted, given) |
3ac21baa | 2107 | && !((i.types[given].bitfield.unspecified |
af508cb9 | 2108 | && !i.broadcast |
3ac21baa JB |
2109 | && !t->operand_types[wanted].bitfield.unspecified) |
2110 | || (i.types[given].bitfield.fword | |
2111 | && !t->operand_types[wanted].bitfield.fword) | |
1b54b8d7 JB |
2112 | /* For scalar opcode templates to allow register and memory |
2113 | operands at the same time, some special casing is needed | |
d6793fa1 JB |
2114 | here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and |
2115 | down-conversion vpmov*. */ | |
3528c362 | 2116 | || ((t->operand_types[wanted].bitfield.class == RegSIMD |
1b54b8d7 | 2117 | && !t->opcode_modifier.broadcast |
3ac21baa JB |
2118 | && (t->operand_types[wanted].bitfield.byte |
2119 | || t->operand_types[wanted].bitfield.word | |
2120 | || t->operand_types[wanted].bitfield.dword | |
2121 | || t->operand_types[wanted].bitfield.qword)) | |
2122 | ? (i.types[given].bitfield.xmmword | |
2123 | || i.types[given].bitfield.ymmword | |
2124 | || i.types[given].bitfield.zmmword) | |
2125 | : !match_simd_size(t, wanted, given)))); | |
5c07affc L |
2126 | } |
2127 | ||
3ac21baa JB |
2128 | /* Return value has MATCH_STRAIGHT set if there is no size conflict on any |
2129 | operands for instruction template T, and it has MATCH_REVERSE set if there | |
2130 | is no size conflict on any operands for the template with operands reversed | |
2131 | (and the template allows for reversing in the first place). */ | |
5c07affc | 2132 | |
3ac21baa JB |
2133 | #define MATCH_STRAIGHT 1 |
2134 | #define MATCH_REVERSE 2 | |
2135 | ||
2136 | static INLINE unsigned int | |
d3ce72d0 | 2137 | operand_size_match (const insn_template *t) |
5c07affc | 2138 | { |
3ac21baa | 2139 | unsigned int j, match = MATCH_STRAIGHT; |
5c07affc | 2140 | |
0cfa3eb3 | 2141 | /* Don't check non-absolute jump instructions. */ |
5c07affc | 2142 | if (t->opcode_modifier.jump |
0cfa3eb3 | 2143 | && t->opcode_modifier.jump != JUMP_ABSOLUTE) |
5c07affc L |
2144 | return match; |
2145 | ||
2146 | /* Check memory and accumulator operand size. */ | |
2147 | for (j = 0; j < i.operands; j++) | |
2148 | { | |
3528c362 JB |
2149 | if (i.types[j].bitfield.class != Reg |
2150 | && i.types[j].bitfield.class != RegSIMD | |
601e8564 | 2151 | && t->opcode_modifier.anysize) |
5c07affc L |
2152 | continue; |
2153 | ||
bab6aec1 | 2154 | if (t->operand_types[j].bitfield.class == Reg |
7a54636a | 2155 | && !match_operand_size (t, j, j)) |
5c07affc L |
2156 | { |
2157 | match = 0; | |
2158 | break; | |
2159 | } | |
2160 | ||
3528c362 | 2161 | if (t->operand_types[j].bitfield.class == RegSIMD |
3ac21baa | 2162 | && !match_simd_size (t, j, j)) |
1b54b8d7 JB |
2163 | { |
2164 | match = 0; | |
2165 | break; | |
2166 | } | |
2167 | ||
75e5731b | 2168 | if (t->operand_types[j].bitfield.instance == Accum |
7a54636a | 2169 | && (!match_operand_size (t, j, j) || !match_simd_size (t, j, j))) |
1b54b8d7 JB |
2170 | { |
2171 | match = 0; | |
2172 | break; | |
2173 | } | |
2174 | ||
c48dadc9 | 2175 | if ((i.flags[j] & Operand_Mem) && !match_mem_size (t, j, j)) |
5c07affc L |
2176 | { |
2177 | match = 0; | |
2178 | break; | |
2179 | } | |
2180 | } | |
2181 | ||
3ac21baa | 2182 | if (!t->opcode_modifier.d) |
891edac4 L |
2183 | { |
2184 | mismatch: | |
3ac21baa JB |
2185 | if (!match) |
2186 | i.error = operand_size_mismatch; | |
2187 | return match; | |
891edac4 | 2188 | } |
5c07affc L |
2189 | |
2190 | /* Check reverse. */ | |
f5eb1d70 | 2191 | gas_assert (i.operands >= 2 && i.operands <= 3); |
5c07affc | 2192 | |
f5eb1d70 | 2193 | for (j = 0; j < i.operands; j++) |
5c07affc | 2194 | { |
f5eb1d70 JB |
2195 | unsigned int given = i.operands - j - 1; |
2196 | ||
bab6aec1 | 2197 | if (t->operand_types[j].bitfield.class == Reg |
f5eb1d70 | 2198 | && !match_operand_size (t, j, given)) |
891edac4 | 2199 | goto mismatch; |
5c07affc | 2200 | |
3528c362 | 2201 | if (t->operand_types[j].bitfield.class == RegSIMD |
f5eb1d70 | 2202 | && !match_simd_size (t, j, given)) |
dbbc8b7e JB |
2203 | goto mismatch; |
2204 | ||
75e5731b | 2205 | if (t->operand_types[j].bitfield.instance == Accum |
f5eb1d70 JB |
2206 | && (!match_operand_size (t, j, given) |
2207 | || !match_simd_size (t, j, given))) | |
dbbc8b7e JB |
2208 | goto mismatch; |
2209 | ||
f5eb1d70 | 2210 | if ((i.flags[given] & Operand_Mem) && !match_mem_size (t, j, given)) |
891edac4 | 2211 | goto mismatch; |
5c07affc L |
2212 | } |
2213 | ||
3ac21baa | 2214 | return match | MATCH_REVERSE; |
5c07affc L |
2215 | } |
2216 | ||
c6fb90c8 | 2217 | static INLINE int |
40fb9820 L |
2218 | operand_type_match (i386_operand_type overlap, |
2219 | i386_operand_type given) | |
2220 | { | |
2221 | i386_operand_type temp = overlap; | |
2222 | ||
7d5e4556 | 2223 | temp.bitfield.unspecified = 0; |
5c07affc L |
2224 | temp.bitfield.byte = 0; |
2225 | temp.bitfield.word = 0; | |
2226 | temp.bitfield.dword = 0; | |
2227 | temp.bitfield.fword = 0; | |
2228 | temp.bitfield.qword = 0; | |
2229 | temp.bitfield.tbyte = 0; | |
2230 | temp.bitfield.xmmword = 0; | |
c0f3af97 | 2231 | temp.bitfield.ymmword = 0; |
43234a1e | 2232 | temp.bitfield.zmmword = 0; |
0dfbf9d7 | 2233 | if (operand_type_all_zero (&temp)) |
891edac4 | 2234 | goto mismatch; |
40fb9820 | 2235 | |
6f2f06be | 2236 | if (given.bitfield.baseindex == overlap.bitfield.baseindex) |
891edac4 L |
2237 | return 1; |
2238 | ||
2239 | mismatch: | |
a65babc9 | 2240 | i.error = operand_type_mismatch; |
891edac4 | 2241 | return 0; |
40fb9820 L |
2242 | } |
2243 | ||
7d5e4556 | 2244 | /* If given types g0 and g1 are registers they must be of the same type |
10c17abd JB |
2245 | unless the expected operand type register overlap is null. |
2246 | Memory operand size of certain SIMD instructions is also being checked | |
2247 | here. */ | |
40fb9820 | 2248 | |
c6fb90c8 | 2249 | static INLINE int |
dc821c5f | 2250 | operand_type_register_match (i386_operand_type g0, |
40fb9820 | 2251 | i386_operand_type t0, |
40fb9820 L |
2252 | i386_operand_type g1, |
2253 | i386_operand_type t1) | |
2254 | { | |
bab6aec1 | 2255 | if (g0.bitfield.class != Reg |
3528c362 | 2256 | && g0.bitfield.class != RegSIMD |
10c17abd JB |
2257 | && (!operand_type_check (g0, anymem) |
2258 | || g0.bitfield.unspecified | |
3528c362 | 2259 | || t0.bitfield.class != RegSIMD)) |
40fb9820 L |
2260 | return 1; |
2261 | ||
bab6aec1 | 2262 | if (g1.bitfield.class != Reg |
3528c362 | 2263 | && g1.bitfield.class != RegSIMD |
10c17abd JB |
2264 | && (!operand_type_check (g1, anymem) |
2265 | || g1.bitfield.unspecified | |
3528c362 | 2266 | || t1.bitfield.class != RegSIMD)) |
40fb9820 L |
2267 | return 1; |
2268 | ||
dc821c5f JB |
2269 | if (g0.bitfield.byte == g1.bitfield.byte |
2270 | && g0.bitfield.word == g1.bitfield.word | |
2271 | && g0.bitfield.dword == g1.bitfield.dword | |
10c17abd JB |
2272 | && g0.bitfield.qword == g1.bitfield.qword |
2273 | && g0.bitfield.xmmword == g1.bitfield.xmmword | |
2274 | && g0.bitfield.ymmword == g1.bitfield.ymmword | |
2275 | && g0.bitfield.zmmword == g1.bitfield.zmmword) | |
40fb9820 L |
2276 | return 1; |
2277 | ||
dc821c5f JB |
2278 | if (!(t0.bitfield.byte & t1.bitfield.byte) |
2279 | && !(t0.bitfield.word & t1.bitfield.word) | |
2280 | && !(t0.bitfield.dword & t1.bitfield.dword) | |
10c17abd JB |
2281 | && !(t0.bitfield.qword & t1.bitfield.qword) |
2282 | && !(t0.bitfield.xmmword & t1.bitfield.xmmword) | |
2283 | && !(t0.bitfield.ymmword & t1.bitfield.ymmword) | |
2284 | && !(t0.bitfield.zmmword & t1.bitfield.zmmword)) | |
891edac4 L |
2285 | return 1; |
2286 | ||
a65babc9 | 2287 | i.error = register_type_mismatch; |
891edac4 L |
2288 | |
2289 | return 0; | |
40fb9820 L |
2290 | } |
2291 | ||
4c692bc7 JB |
2292 | static INLINE unsigned int |
2293 | register_number (const reg_entry *r) | |
2294 | { | |
2295 | unsigned int nr = r->reg_num; | |
2296 | ||
2297 | if (r->reg_flags & RegRex) | |
2298 | nr += 8; | |
2299 | ||
200cbe0f L |
2300 | if (r->reg_flags & RegVRex) |
2301 | nr += 16; | |
2302 | ||
4c692bc7 JB |
2303 | return nr; |
2304 | } | |
2305 | ||
252b5132 | 2306 | static INLINE unsigned int |
40fb9820 | 2307 | mode_from_disp_size (i386_operand_type t) |
252b5132 | 2308 | { |
b5014f7a | 2309 | if (t.bitfield.disp8) |
40fb9820 L |
2310 | return 1; |
2311 | else if (t.bitfield.disp16 | |
2312 | || t.bitfield.disp32 | |
2313 | || t.bitfield.disp32s) | |
2314 | return 2; | |
2315 | else | |
2316 | return 0; | |
252b5132 RH |
2317 | } |
2318 | ||
2319 | static INLINE int | |
65879393 | 2320 | fits_in_signed_byte (addressT num) |
252b5132 | 2321 | { |
65879393 | 2322 | return num + 0x80 <= 0xff; |
47926f60 | 2323 | } |
252b5132 RH |
2324 | |
2325 | static INLINE int | |
65879393 | 2326 | fits_in_unsigned_byte (addressT num) |
252b5132 | 2327 | { |
65879393 | 2328 | return num <= 0xff; |
47926f60 | 2329 | } |
252b5132 RH |
2330 | |
2331 | static INLINE int | |
65879393 | 2332 | fits_in_unsigned_word (addressT num) |
252b5132 | 2333 | { |
65879393 | 2334 | return num <= 0xffff; |
47926f60 | 2335 | } |
252b5132 RH |
2336 | |
2337 | static INLINE int | |
65879393 | 2338 | fits_in_signed_word (addressT num) |
252b5132 | 2339 | { |
65879393 | 2340 | return num + 0x8000 <= 0xffff; |
47926f60 | 2341 | } |
2a962e6d | 2342 | |
3e73aa7c | 2343 | static INLINE int |
65879393 | 2344 | fits_in_signed_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2345 | { |
2346 | #ifndef BFD64 | |
2347 | return 1; | |
2348 | #else | |
65879393 | 2349 | return num + 0x80000000 <= 0xffffffff; |
3e73aa7c JH |
2350 | #endif |
2351 | } /* fits_in_signed_long() */ | |
2a962e6d | 2352 | |
3e73aa7c | 2353 | static INLINE int |
65879393 | 2354 | fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2355 | { |
2356 | #ifndef BFD64 | |
2357 | return 1; | |
2358 | #else | |
65879393 | 2359 | return num <= 0xffffffff; |
3e73aa7c JH |
2360 | #endif |
2361 | } /* fits_in_unsigned_long() */ | |
252b5132 | 2362 | |
43234a1e | 2363 | static INLINE int |
b5014f7a | 2364 | fits_in_disp8 (offsetT num) |
43234a1e L |
2365 | { |
2366 | int shift = i.memshift; | |
2367 | unsigned int mask; | |
2368 | ||
2369 | if (shift == -1) | |
2370 | abort (); | |
2371 | ||
2372 | mask = (1 << shift) - 1; | |
2373 | ||
2374 | /* Return 0 if NUM isn't properly aligned. */ | |
2375 | if ((num & mask)) | |
2376 | return 0; | |
2377 | ||
2378 | /* Check if NUM will fit in 8bit after shift. */ | |
2379 | return fits_in_signed_byte (num >> shift); | |
2380 | } | |
2381 | ||
a683cc34 SP |
2382 | static INLINE int |
2383 | fits_in_imm4 (offsetT num) | |
2384 | { | |
2385 | return (num & 0xf) == num; | |
2386 | } | |
2387 | ||
40fb9820 | 2388 | static i386_operand_type |
e3bb37b5 | 2389 | smallest_imm_type (offsetT num) |
252b5132 | 2390 | { |
40fb9820 | 2391 | i386_operand_type t; |
7ab9ffdd | 2392 | |
0dfbf9d7 | 2393 | operand_type_set (&t, 0); |
40fb9820 L |
2394 | t.bitfield.imm64 = 1; |
2395 | ||
2396 | if (cpu_arch_tune != PROCESSOR_I486 && num == 1) | |
e413e4e9 AM |
2397 | { |
2398 | /* This code is disabled on the 486 because all the Imm1 forms | |
2399 | in the opcode table are slower on the i486. They're the | |
2400 | versions with the implicitly specified single-position | |
2401 | displacement, which has another syntax if you really want to | |
2402 | use that form. */ | |
40fb9820 L |
2403 | t.bitfield.imm1 = 1; |
2404 | t.bitfield.imm8 = 1; | |
2405 | t.bitfield.imm8s = 1; | |
2406 | t.bitfield.imm16 = 1; | |
2407 | t.bitfield.imm32 = 1; | |
2408 | t.bitfield.imm32s = 1; | |
2409 | } | |
2410 | else if (fits_in_signed_byte (num)) | |
2411 | { | |
2412 | t.bitfield.imm8 = 1; | |
2413 | t.bitfield.imm8s = 1; | |
2414 | t.bitfield.imm16 = 1; | |
2415 | t.bitfield.imm32 = 1; | |
2416 | t.bitfield.imm32s = 1; | |
2417 | } | |
2418 | else if (fits_in_unsigned_byte (num)) | |
2419 | { | |
2420 | t.bitfield.imm8 = 1; | |
2421 | t.bitfield.imm16 = 1; | |
2422 | t.bitfield.imm32 = 1; | |
2423 | t.bitfield.imm32s = 1; | |
2424 | } | |
2425 | else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
2426 | { | |
2427 | t.bitfield.imm16 = 1; | |
2428 | t.bitfield.imm32 = 1; | |
2429 | t.bitfield.imm32s = 1; | |
2430 | } | |
2431 | else if (fits_in_signed_long (num)) | |
2432 | { | |
2433 | t.bitfield.imm32 = 1; | |
2434 | t.bitfield.imm32s = 1; | |
2435 | } | |
2436 | else if (fits_in_unsigned_long (num)) | |
2437 | t.bitfield.imm32 = 1; | |
2438 | ||
2439 | return t; | |
47926f60 | 2440 | } |
252b5132 | 2441 | |
847f7ad4 | 2442 | static offsetT |
e3bb37b5 | 2443 | offset_in_range (offsetT val, int size) |
847f7ad4 | 2444 | { |
508866be | 2445 | addressT mask; |
ba2adb93 | 2446 | |
847f7ad4 AM |
2447 | switch (size) |
2448 | { | |
508866be L |
2449 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
2450 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 2451 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
3e73aa7c JH |
2452 | #ifdef BFD64 |
2453 | case 8: mask = ((addressT) 2 << 63) - 1; break; | |
2454 | #endif | |
47926f60 | 2455 | default: abort (); |
847f7ad4 AM |
2456 | } |
2457 | ||
9de868bf L |
2458 | #ifdef BFD64 |
2459 | /* If BFD64, sign extend val for 32bit address mode. */ | |
2460 | if (flag_code != CODE_64BIT | |
2461 | || i.prefix[ADDR_PREFIX]) | |
3e73aa7c JH |
2462 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) |
2463 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
fa289fb8 | 2464 | #endif |
ba2adb93 | 2465 | |
47926f60 | 2466 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
847f7ad4 AM |
2467 | { |
2468 | char buf1[40], buf2[40]; | |
2469 | ||
2470 | sprint_value (buf1, val); | |
2471 | sprint_value (buf2, val & mask); | |
2472 | as_warn (_("%s shortened to %s"), buf1, buf2); | |
2473 | } | |
2474 | return val & mask; | |
2475 | } | |
2476 | ||
c32fa91d L |
2477 | enum PREFIX_GROUP |
2478 | { | |
2479 | PREFIX_EXIST = 0, | |
2480 | PREFIX_LOCK, | |
2481 | PREFIX_REP, | |
04ef582a | 2482 | PREFIX_DS, |
c32fa91d L |
2483 | PREFIX_OTHER |
2484 | }; | |
2485 | ||
2486 | /* Returns | |
2487 | a. PREFIX_EXIST if attempting to add a prefix where one from the | |
2488 | same class already exists. | |
2489 | b. PREFIX_LOCK if lock prefix is added. | |
2490 | c. PREFIX_REP if rep/repne prefix is added. | |
04ef582a L |
2491 | d. PREFIX_DS if ds prefix is added. |
2492 | e. PREFIX_OTHER if other prefix is added. | |
c32fa91d L |
2493 | */ |
2494 | ||
2495 | static enum PREFIX_GROUP | |
e3bb37b5 | 2496 | add_prefix (unsigned int prefix) |
252b5132 | 2497 | { |
c32fa91d | 2498 | enum PREFIX_GROUP ret = PREFIX_OTHER; |
b1905489 | 2499 | unsigned int q; |
252b5132 | 2500 | |
29b0f896 AM |
2501 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
2502 | && flag_code == CODE_64BIT) | |
b1905489 | 2503 | { |
161a04f6 | 2504 | if ((i.prefix[REX_PREFIX] & prefix & REX_W) |
44846f29 JB |
2505 | || (i.prefix[REX_PREFIX] & prefix & REX_R) |
2506 | || (i.prefix[REX_PREFIX] & prefix & REX_X) | |
2507 | || (i.prefix[REX_PREFIX] & prefix & REX_B)) | |
c32fa91d | 2508 | ret = PREFIX_EXIST; |
b1905489 JB |
2509 | q = REX_PREFIX; |
2510 | } | |
3e73aa7c | 2511 | else |
b1905489 JB |
2512 | { |
2513 | switch (prefix) | |
2514 | { | |
2515 | default: | |
2516 | abort (); | |
2517 | ||
b1905489 | 2518 | case DS_PREFIX_OPCODE: |
04ef582a L |
2519 | ret = PREFIX_DS; |
2520 | /* Fall through. */ | |
2521 | case CS_PREFIX_OPCODE: | |
b1905489 JB |
2522 | case ES_PREFIX_OPCODE: |
2523 | case FS_PREFIX_OPCODE: | |
2524 | case GS_PREFIX_OPCODE: | |
2525 | case SS_PREFIX_OPCODE: | |
2526 | q = SEG_PREFIX; | |
2527 | break; | |
2528 | ||
2529 | case REPNE_PREFIX_OPCODE: | |
2530 | case REPE_PREFIX_OPCODE: | |
c32fa91d L |
2531 | q = REP_PREFIX; |
2532 | ret = PREFIX_REP; | |
2533 | break; | |
2534 | ||
b1905489 | 2535 | case LOCK_PREFIX_OPCODE: |
c32fa91d L |
2536 | q = LOCK_PREFIX; |
2537 | ret = PREFIX_LOCK; | |
b1905489 JB |
2538 | break; |
2539 | ||
2540 | case FWAIT_OPCODE: | |
2541 | q = WAIT_PREFIX; | |
2542 | break; | |
2543 | ||
2544 | case ADDR_PREFIX_OPCODE: | |
2545 | q = ADDR_PREFIX; | |
2546 | break; | |
2547 | ||
2548 | case DATA_PREFIX_OPCODE: | |
2549 | q = DATA_PREFIX; | |
2550 | break; | |
2551 | } | |
2552 | if (i.prefix[q] != 0) | |
c32fa91d | 2553 | ret = PREFIX_EXIST; |
b1905489 | 2554 | } |
252b5132 | 2555 | |
b1905489 | 2556 | if (ret) |
252b5132 | 2557 | { |
b1905489 JB |
2558 | if (!i.prefix[q]) |
2559 | ++i.prefixes; | |
2560 | i.prefix[q] |= prefix; | |
252b5132 | 2561 | } |
b1905489 JB |
2562 | else |
2563 | as_bad (_("same type of prefix used twice")); | |
252b5132 | 2564 | |
252b5132 RH |
2565 | return ret; |
2566 | } | |
2567 | ||
2568 | static void | |
78f12dd3 | 2569 | update_code_flag (int value, int check) |
eecb386c | 2570 | { |
78f12dd3 L |
2571 | PRINTF_LIKE ((*as_error)); |
2572 | ||
1e9cc1c2 | 2573 | flag_code = (enum flag_code) value; |
40fb9820 L |
2574 | if (flag_code == CODE_64BIT) |
2575 | { | |
2576 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2577 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
40fb9820 L |
2578 | } |
2579 | else | |
2580 | { | |
2581 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2582 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
40fb9820 L |
2583 | } |
2584 | if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm ) | |
3e73aa7c | 2585 | { |
78f12dd3 L |
2586 | if (check) |
2587 | as_error = as_fatal; | |
2588 | else | |
2589 | as_error = as_bad; | |
2590 | (*as_error) (_("64bit mode not supported on `%s'."), | |
2591 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2592 | } |
40fb9820 | 2593 | if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) |
3e73aa7c | 2594 | { |
78f12dd3 L |
2595 | if (check) |
2596 | as_error = as_fatal; | |
2597 | else | |
2598 | as_error = as_bad; | |
2599 | (*as_error) (_("32bit mode not supported on `%s'."), | |
2600 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2601 | } |
eecb386c AM |
2602 | stackop_size = '\0'; |
2603 | } | |
2604 | ||
78f12dd3 L |
2605 | static void |
2606 | set_code_flag (int value) | |
2607 | { | |
2608 | update_code_flag (value, 0); | |
2609 | } | |
2610 | ||
eecb386c | 2611 | static void |
e3bb37b5 | 2612 | set_16bit_gcc_code_flag (int new_code_flag) |
252b5132 | 2613 | { |
1e9cc1c2 | 2614 | flag_code = (enum flag_code) new_code_flag; |
40fb9820 L |
2615 | if (flag_code != CODE_16BIT) |
2616 | abort (); | |
2617 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2618 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
9306ca4a | 2619 | stackop_size = LONG_MNEM_SUFFIX; |
252b5132 RH |
2620 | } |
2621 | ||
2622 | static void | |
e3bb37b5 | 2623 | set_intel_syntax (int syntax_flag) |
252b5132 RH |
2624 | { |
2625 | /* Find out if register prefixing is specified. */ | |
2626 | int ask_naked_reg = 0; | |
2627 | ||
2628 | SKIP_WHITESPACE (); | |
29b0f896 | 2629 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
252b5132 | 2630 | { |
d02603dc NC |
2631 | char *string; |
2632 | int e = get_symbol_name (&string); | |
252b5132 | 2633 | |
47926f60 | 2634 | if (strcmp (string, "prefix") == 0) |
252b5132 | 2635 | ask_naked_reg = 1; |
47926f60 | 2636 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
2637 | ask_naked_reg = -1; |
2638 | else | |
d0b47220 | 2639 | as_bad (_("bad argument to syntax directive.")); |
d02603dc | 2640 | (void) restore_line_pointer (e); |
252b5132 RH |
2641 | } |
2642 | demand_empty_rest_of_line (); | |
c3332e24 | 2643 | |
252b5132 RH |
2644 | intel_syntax = syntax_flag; |
2645 | ||
2646 | if (ask_naked_reg == 0) | |
f86103b7 AM |
2647 | allow_naked_reg = (intel_syntax |
2648 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); | |
252b5132 RH |
2649 | else |
2650 | allow_naked_reg = (ask_naked_reg < 0); | |
9306ca4a | 2651 | |
ee86248c | 2652 | expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0); |
7ab9ffdd | 2653 | |
e4a3b5a4 | 2654 | identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; |
9306ca4a | 2655 | identifier_chars['$'] = intel_syntax ? '$' : 0; |
e4a3b5a4 | 2656 | register_prefix = allow_naked_reg ? "" : "%"; |
252b5132 RH |
2657 | } |
2658 | ||
1efbbeb4 L |
2659 | static void |
2660 | set_intel_mnemonic (int mnemonic_flag) | |
2661 | { | |
e1d4d893 | 2662 | intel_mnemonic = mnemonic_flag; |
1efbbeb4 L |
2663 | } |
2664 | ||
db51cc60 L |
2665 | static void |
2666 | set_allow_index_reg (int flag) | |
2667 | { | |
2668 | allow_index_reg = flag; | |
2669 | } | |
2670 | ||
cb19c032 | 2671 | static void |
7bab8ab5 | 2672 | set_check (int what) |
cb19c032 | 2673 | { |
7bab8ab5 JB |
2674 | enum check_kind *kind; |
2675 | const char *str; | |
2676 | ||
2677 | if (what) | |
2678 | { | |
2679 | kind = &operand_check; | |
2680 | str = "operand"; | |
2681 | } | |
2682 | else | |
2683 | { | |
2684 | kind = &sse_check; | |
2685 | str = "sse"; | |
2686 | } | |
2687 | ||
cb19c032 L |
2688 | SKIP_WHITESPACE (); |
2689 | ||
2690 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
2691 | { | |
d02603dc NC |
2692 | char *string; |
2693 | int e = get_symbol_name (&string); | |
cb19c032 L |
2694 | |
2695 | if (strcmp (string, "none") == 0) | |
7bab8ab5 | 2696 | *kind = check_none; |
cb19c032 | 2697 | else if (strcmp (string, "warning") == 0) |
7bab8ab5 | 2698 | *kind = check_warning; |
cb19c032 | 2699 | else if (strcmp (string, "error") == 0) |
7bab8ab5 | 2700 | *kind = check_error; |
cb19c032 | 2701 | else |
7bab8ab5 | 2702 | as_bad (_("bad argument to %s_check directive."), str); |
d02603dc | 2703 | (void) restore_line_pointer (e); |
cb19c032 L |
2704 | } |
2705 | else | |
7bab8ab5 | 2706 | as_bad (_("missing argument for %s_check directive"), str); |
cb19c032 L |
2707 | |
2708 | demand_empty_rest_of_line (); | |
2709 | } | |
2710 | ||
8a9036a4 L |
2711 | static void |
2712 | check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED, | |
1e9cc1c2 | 2713 | i386_cpu_flags new_flag ATTRIBUTE_UNUSED) |
8a9036a4 L |
2714 | { |
2715 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2716 | static const char *arch; | |
2717 | ||
2718 | /* Intel LIOM is only supported on ELF. */ | |
2719 | if (!IS_ELF) | |
2720 | return; | |
2721 | ||
2722 | if (!arch) | |
2723 | { | |
2724 | /* Use cpu_arch_name if it is set in md_parse_option. Otherwise | |
2725 | use default_arch. */ | |
2726 | arch = cpu_arch_name; | |
2727 | if (!arch) | |
2728 | arch = default_arch; | |
2729 | } | |
2730 | ||
81486035 L |
2731 | /* If we are targeting Intel MCU, we must enable it. */ |
2732 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU | |
2733 | || new_flag.bitfield.cpuiamcu) | |
2734 | return; | |
2735 | ||
3632d14b | 2736 | /* If we are targeting Intel L1OM, we must enable it. */ |
8a9036a4 | 2737 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM |
1e9cc1c2 | 2738 | || new_flag.bitfield.cpul1om) |
8a9036a4 | 2739 | return; |
76ba9986 | 2740 | |
7a9068fe L |
2741 | /* If we are targeting Intel K1OM, we must enable it. */ |
2742 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM | |
2743 | || new_flag.bitfield.cpuk1om) | |
2744 | return; | |
2745 | ||
8a9036a4 L |
2746 | as_bad (_("`%s' is not supported on `%s'"), name, arch); |
2747 | #endif | |
2748 | } | |
2749 | ||
e413e4e9 | 2750 | static void |
e3bb37b5 | 2751 | set_cpu_arch (int dummy ATTRIBUTE_UNUSED) |
e413e4e9 | 2752 | { |
47926f60 | 2753 | SKIP_WHITESPACE (); |
e413e4e9 | 2754 | |
29b0f896 | 2755 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
e413e4e9 | 2756 | { |
d02603dc NC |
2757 | char *string; |
2758 | int e = get_symbol_name (&string); | |
91d6fa6a | 2759 | unsigned int j; |
40fb9820 | 2760 | i386_cpu_flags flags; |
e413e4e9 | 2761 | |
91d6fa6a | 2762 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
e413e4e9 | 2763 | { |
91d6fa6a | 2764 | if (strcmp (string, cpu_arch[j].name) == 0) |
e413e4e9 | 2765 | { |
91d6fa6a | 2766 | check_cpu_arch_compatible (string, cpu_arch[j].flags); |
8a9036a4 | 2767 | |
5c6af06e JB |
2768 | if (*string != '.') |
2769 | { | |
91d6fa6a | 2770 | cpu_arch_name = cpu_arch[j].name; |
5c6af06e | 2771 | cpu_sub_arch_name = NULL; |
91d6fa6a | 2772 | cpu_arch_flags = cpu_arch[j].flags; |
40fb9820 L |
2773 | if (flag_code == CODE_64BIT) |
2774 | { | |
2775 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2776 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
2777 | } | |
2778 | else | |
2779 | { | |
2780 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2781 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
2782 | } | |
91d6fa6a NC |
2783 | cpu_arch_isa = cpu_arch[j].type; |
2784 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
ccc9c027 L |
2785 | if (!cpu_arch_tune_set) |
2786 | { | |
2787 | cpu_arch_tune = cpu_arch_isa; | |
2788 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
2789 | } | |
5c6af06e JB |
2790 | break; |
2791 | } | |
40fb9820 | 2792 | |
293f5f65 L |
2793 | flags = cpu_flags_or (cpu_arch_flags, |
2794 | cpu_arch[j].flags); | |
81486035 | 2795 | |
5b64d091 | 2796 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
5c6af06e | 2797 | { |
6305a203 L |
2798 | if (cpu_sub_arch_name) |
2799 | { | |
2800 | char *name = cpu_sub_arch_name; | |
2801 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 2802 | cpu_arch[j].name, |
1bf57e9f | 2803 | (const char *) NULL); |
6305a203 L |
2804 | free (name); |
2805 | } | |
2806 | else | |
91d6fa6a | 2807 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
40fb9820 | 2808 | cpu_arch_flags = flags; |
a586129e | 2809 | cpu_arch_isa_flags = flags; |
5c6af06e | 2810 | } |
0089dace L |
2811 | else |
2812 | cpu_arch_isa_flags | |
2813 | = cpu_flags_or (cpu_arch_isa_flags, | |
2814 | cpu_arch[j].flags); | |
d02603dc | 2815 | (void) restore_line_pointer (e); |
5c6af06e JB |
2816 | demand_empty_rest_of_line (); |
2817 | return; | |
e413e4e9 AM |
2818 | } |
2819 | } | |
293f5f65 L |
2820 | |
2821 | if (*string == '.' && j >= ARRAY_SIZE (cpu_arch)) | |
2822 | { | |
33eaf5de | 2823 | /* Disable an ISA extension. */ |
293f5f65 L |
2824 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
2825 | if (strcmp (string + 1, cpu_noarch [j].name) == 0) | |
2826 | { | |
2827 | flags = cpu_flags_and_not (cpu_arch_flags, | |
2828 | cpu_noarch[j].flags); | |
2829 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
2830 | { | |
2831 | if (cpu_sub_arch_name) | |
2832 | { | |
2833 | char *name = cpu_sub_arch_name; | |
2834 | cpu_sub_arch_name = concat (name, string, | |
2835 | (const char *) NULL); | |
2836 | free (name); | |
2837 | } | |
2838 | else | |
2839 | cpu_sub_arch_name = xstrdup (string); | |
2840 | cpu_arch_flags = flags; | |
2841 | cpu_arch_isa_flags = flags; | |
2842 | } | |
2843 | (void) restore_line_pointer (e); | |
2844 | demand_empty_rest_of_line (); | |
2845 | return; | |
2846 | } | |
2847 | ||
2848 | j = ARRAY_SIZE (cpu_arch); | |
2849 | } | |
2850 | ||
91d6fa6a | 2851 | if (j >= ARRAY_SIZE (cpu_arch)) |
e413e4e9 AM |
2852 | as_bad (_("no such architecture: `%s'"), string); |
2853 | ||
2854 | *input_line_pointer = e; | |
2855 | } | |
2856 | else | |
2857 | as_bad (_("missing cpu architecture")); | |
2858 | ||
fddf5b5b AM |
2859 | no_cond_jump_promotion = 0; |
2860 | if (*input_line_pointer == ',' | |
29b0f896 | 2861 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
fddf5b5b | 2862 | { |
d02603dc NC |
2863 | char *string; |
2864 | char e; | |
2865 | ||
2866 | ++input_line_pointer; | |
2867 | e = get_symbol_name (&string); | |
fddf5b5b AM |
2868 | |
2869 | if (strcmp (string, "nojumps") == 0) | |
2870 | no_cond_jump_promotion = 1; | |
2871 | else if (strcmp (string, "jumps") == 0) | |
2872 | ; | |
2873 | else | |
2874 | as_bad (_("no such architecture modifier: `%s'"), string); | |
2875 | ||
d02603dc | 2876 | (void) restore_line_pointer (e); |
fddf5b5b AM |
2877 | } |
2878 | ||
e413e4e9 AM |
2879 | demand_empty_rest_of_line (); |
2880 | } | |
2881 | ||
8a9036a4 L |
2882 | enum bfd_architecture |
2883 | i386_arch (void) | |
2884 | { | |
3632d14b | 2885 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 L |
2886 | { |
2887 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2888 | || flag_code != CODE_64BIT) | |
2889 | as_fatal (_("Intel L1OM is 64bit ELF only")); | |
2890 | return bfd_arch_l1om; | |
2891 | } | |
7a9068fe L |
2892 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2893 | { | |
2894 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2895 | || flag_code != CODE_64BIT) | |
2896 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2897 | return bfd_arch_k1om; | |
2898 | } | |
81486035 L |
2899 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
2900 | { | |
2901 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2902 | || flag_code == CODE_64BIT) | |
2903 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2904 | return bfd_arch_iamcu; | |
2905 | } | |
8a9036a4 L |
2906 | else |
2907 | return bfd_arch_i386; | |
2908 | } | |
2909 | ||
b9d79e03 | 2910 | unsigned long |
7016a5d5 | 2911 | i386_mach (void) |
b9d79e03 | 2912 | { |
351f65ca | 2913 | if (!strncmp (default_arch, "x86_64", 6)) |
8a9036a4 | 2914 | { |
3632d14b | 2915 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 2916 | { |
351f65ca L |
2917 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour |
2918 | || default_arch[6] != '\0') | |
8a9036a4 L |
2919 | as_fatal (_("Intel L1OM is 64bit ELF only")); |
2920 | return bfd_mach_l1om; | |
2921 | } | |
7a9068fe L |
2922 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2923 | { | |
2924 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2925 | || default_arch[6] != '\0') | |
2926 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2927 | return bfd_mach_k1om; | |
2928 | } | |
351f65ca | 2929 | else if (default_arch[6] == '\0') |
8a9036a4 | 2930 | return bfd_mach_x86_64; |
351f65ca L |
2931 | else |
2932 | return bfd_mach_x64_32; | |
8a9036a4 | 2933 | } |
5197d474 L |
2934 | else if (!strcmp (default_arch, "i386") |
2935 | || !strcmp (default_arch, "iamcu")) | |
81486035 L |
2936 | { |
2937 | if (cpu_arch_isa == PROCESSOR_IAMCU) | |
2938 | { | |
2939 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
2940 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2941 | return bfd_mach_i386_iamcu; | |
2942 | } | |
2943 | else | |
2944 | return bfd_mach_i386_i386; | |
2945 | } | |
b9d79e03 | 2946 | else |
2b5d6a91 | 2947 | as_fatal (_("unknown architecture")); |
b9d79e03 | 2948 | } |
b9d79e03 | 2949 | \f |
252b5132 | 2950 | void |
7016a5d5 | 2951 | md_begin (void) |
252b5132 RH |
2952 | { |
2953 | const char *hash_err; | |
2954 | ||
86fa6981 L |
2955 | /* Support pseudo prefixes like {disp32}. */ |
2956 | lex_type ['{'] = LEX_BEGIN_NAME; | |
2957 | ||
47926f60 | 2958 | /* Initialize op_hash hash table. */ |
252b5132 RH |
2959 | op_hash = hash_new (); |
2960 | ||
2961 | { | |
d3ce72d0 | 2962 | const insn_template *optab; |
29b0f896 | 2963 | templates *core_optab; |
252b5132 | 2964 | |
47926f60 KH |
2965 | /* Setup for loop. */ |
2966 | optab = i386_optab; | |
add39d23 | 2967 | core_optab = XNEW (templates); |
252b5132 RH |
2968 | core_optab->start = optab; |
2969 | ||
2970 | while (1) | |
2971 | { | |
2972 | ++optab; | |
2973 | if (optab->name == NULL | |
2974 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
2975 | { | |
2976 | /* different name --> ship out current template list; | |
47926f60 | 2977 | add to hash table; & begin anew. */ |
252b5132 RH |
2978 | core_optab->end = optab; |
2979 | hash_err = hash_insert (op_hash, | |
2980 | (optab - 1)->name, | |
5a49b8ac | 2981 | (void *) core_optab); |
252b5132 RH |
2982 | if (hash_err) |
2983 | { | |
b37df7c4 | 2984 | as_fatal (_("can't hash %s: %s"), |
252b5132 RH |
2985 | (optab - 1)->name, |
2986 | hash_err); | |
2987 | } | |
2988 | if (optab->name == NULL) | |
2989 | break; | |
add39d23 | 2990 | core_optab = XNEW (templates); |
252b5132 RH |
2991 | core_optab->start = optab; |
2992 | } | |
2993 | } | |
2994 | } | |
2995 | ||
47926f60 | 2996 | /* Initialize reg_hash hash table. */ |
252b5132 RH |
2997 | reg_hash = hash_new (); |
2998 | { | |
29b0f896 | 2999 | const reg_entry *regtab; |
c3fe08fa | 3000 | unsigned int regtab_size = i386_regtab_size; |
252b5132 | 3001 | |
c3fe08fa | 3002 | for (regtab = i386_regtab; regtab_size--; regtab++) |
252b5132 | 3003 | { |
5a49b8ac | 3004 | hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab); |
252b5132 | 3005 | if (hash_err) |
b37df7c4 | 3006 | as_fatal (_("can't hash %s: %s"), |
3e73aa7c JH |
3007 | regtab->reg_name, |
3008 | hash_err); | |
252b5132 RH |
3009 | } |
3010 | } | |
3011 | ||
47926f60 | 3012 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 | 3013 | { |
29b0f896 AM |
3014 | int c; |
3015 | char *p; | |
252b5132 RH |
3016 | |
3017 | for (c = 0; c < 256; c++) | |
3018 | { | |
3882b010 | 3019 | if (ISDIGIT (c)) |
252b5132 RH |
3020 | { |
3021 | digit_chars[c] = c; | |
3022 | mnemonic_chars[c] = c; | |
3023 | register_chars[c] = c; | |
3024 | operand_chars[c] = c; | |
3025 | } | |
3882b010 | 3026 | else if (ISLOWER (c)) |
252b5132 RH |
3027 | { |
3028 | mnemonic_chars[c] = c; | |
3029 | register_chars[c] = c; | |
3030 | operand_chars[c] = c; | |
3031 | } | |
3882b010 | 3032 | else if (ISUPPER (c)) |
252b5132 | 3033 | { |
3882b010 | 3034 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
3035 | register_chars[c] = mnemonic_chars[c]; |
3036 | operand_chars[c] = c; | |
3037 | } | |
43234a1e | 3038 | else if (c == '{' || c == '}') |
86fa6981 L |
3039 | { |
3040 | mnemonic_chars[c] = c; | |
3041 | operand_chars[c] = c; | |
3042 | } | |
252b5132 | 3043 | |
3882b010 | 3044 | if (ISALPHA (c) || ISDIGIT (c)) |
252b5132 RH |
3045 | identifier_chars[c] = c; |
3046 | else if (c >= 128) | |
3047 | { | |
3048 | identifier_chars[c] = c; | |
3049 | operand_chars[c] = c; | |
3050 | } | |
3051 | } | |
3052 | ||
3053 | #ifdef LEX_AT | |
3054 | identifier_chars['@'] = '@'; | |
32137342 NC |
3055 | #endif |
3056 | #ifdef LEX_QM | |
3057 | identifier_chars['?'] = '?'; | |
3058 | operand_chars['?'] = '?'; | |
252b5132 | 3059 | #endif |
252b5132 | 3060 | digit_chars['-'] = '-'; |
c0f3af97 | 3061 | mnemonic_chars['_'] = '_'; |
791fe849 | 3062 | mnemonic_chars['-'] = '-'; |
0003779b | 3063 | mnemonic_chars['.'] = '.'; |
252b5132 RH |
3064 | identifier_chars['_'] = '_'; |
3065 | identifier_chars['.'] = '.'; | |
3066 | ||
3067 | for (p = operand_special_chars; *p != '\0'; p++) | |
3068 | operand_chars[(unsigned char) *p] = *p; | |
3069 | } | |
3070 | ||
a4447b93 RH |
3071 | if (flag_code == CODE_64BIT) |
3072 | { | |
ca19b261 KT |
3073 | #if defined (OBJ_COFF) && defined (TE_PE) |
3074 | x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour | |
3075 | ? 32 : 16); | |
3076 | #else | |
a4447b93 | 3077 | x86_dwarf2_return_column = 16; |
ca19b261 | 3078 | #endif |
61ff971f | 3079 | x86_cie_data_alignment = -8; |
a4447b93 RH |
3080 | } |
3081 | else | |
3082 | { | |
3083 | x86_dwarf2_return_column = 8; | |
3084 | x86_cie_data_alignment = -4; | |
3085 | } | |
e379e5f3 L |
3086 | |
3087 | /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it | |
3088 | can be turned into BRANCH_PREFIX frag. */ | |
3089 | if (align_branch_prefix_size > MAX_FUSED_JCC_PADDING_SIZE) | |
3090 | abort (); | |
252b5132 RH |
3091 | } |
3092 | ||
3093 | void | |
e3bb37b5 | 3094 | i386_print_statistics (FILE *file) |
252b5132 RH |
3095 | { |
3096 | hash_print_statistics (file, "i386 opcode", op_hash); | |
3097 | hash_print_statistics (file, "i386 register", reg_hash); | |
3098 | } | |
3099 | \f | |
252b5132 RH |
3100 | #ifdef DEBUG386 |
3101 | ||
ce8a8b2f | 3102 | /* Debugging routines for md_assemble. */ |
d3ce72d0 | 3103 | static void pte (insn_template *); |
40fb9820 | 3104 | static void pt (i386_operand_type); |
e3bb37b5 L |
3105 | static void pe (expressionS *); |
3106 | static void ps (symbolS *); | |
252b5132 RH |
3107 | |
3108 | static void | |
2c703856 | 3109 | pi (const char *line, i386_insn *x) |
252b5132 | 3110 | { |
09137c09 | 3111 | unsigned int j; |
252b5132 RH |
3112 | |
3113 | fprintf (stdout, "%s: template ", line); | |
3114 | pte (&x->tm); | |
09f131f2 JH |
3115 | fprintf (stdout, " address: base %s index %s scale %x\n", |
3116 | x->base_reg ? x->base_reg->reg_name : "none", | |
3117 | x->index_reg ? x->index_reg->reg_name : "none", | |
3118 | x->log2_scale_factor); | |
3119 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 3120 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
3121 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
3122 | x->sib.base, x->sib.index, x->sib.scale); | |
3123 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
161a04f6 L |
3124 | (x->rex & REX_W) != 0, |
3125 | (x->rex & REX_R) != 0, | |
3126 | (x->rex & REX_X) != 0, | |
3127 | (x->rex & REX_B) != 0); | |
09137c09 | 3128 | for (j = 0; j < x->operands; j++) |
252b5132 | 3129 | { |
09137c09 SP |
3130 | fprintf (stdout, " #%d: ", j + 1); |
3131 | pt (x->types[j]); | |
252b5132 | 3132 | fprintf (stdout, "\n"); |
bab6aec1 | 3133 | if (x->types[j].bitfield.class == Reg |
3528c362 JB |
3134 | || x->types[j].bitfield.class == RegMMX |
3135 | || x->types[j].bitfield.class == RegSIMD | |
00cee14f | 3136 | || x->types[j].bitfield.class == SReg |
4a5c67ed JB |
3137 | || x->types[j].bitfield.class == RegCR |
3138 | || x->types[j].bitfield.class == RegDR | |
3139 | || x->types[j].bitfield.class == RegTR) | |
09137c09 SP |
3140 | fprintf (stdout, "%s\n", x->op[j].regs->reg_name); |
3141 | if (operand_type_check (x->types[j], imm)) | |
3142 | pe (x->op[j].imms); | |
3143 | if (operand_type_check (x->types[j], disp)) | |
3144 | pe (x->op[j].disps); | |
252b5132 RH |
3145 | } |
3146 | } | |
3147 | ||
3148 | static void | |
d3ce72d0 | 3149 | pte (insn_template *t) |
252b5132 | 3150 | { |
09137c09 | 3151 | unsigned int j; |
252b5132 | 3152 | fprintf (stdout, " %d operands ", t->operands); |
47926f60 | 3153 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
3154 | if (t->extension_opcode != None) |
3155 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
40fb9820 | 3156 | if (t->opcode_modifier.d) |
252b5132 | 3157 | fprintf (stdout, "D"); |
40fb9820 | 3158 | if (t->opcode_modifier.w) |
252b5132 RH |
3159 | fprintf (stdout, "W"); |
3160 | fprintf (stdout, "\n"); | |
09137c09 | 3161 | for (j = 0; j < t->operands; j++) |
252b5132 | 3162 | { |
09137c09 SP |
3163 | fprintf (stdout, " #%d type ", j + 1); |
3164 | pt (t->operand_types[j]); | |
252b5132 RH |
3165 | fprintf (stdout, "\n"); |
3166 | } | |
3167 | } | |
3168 | ||
3169 | static void | |
e3bb37b5 | 3170 | pe (expressionS *e) |
252b5132 | 3171 | { |
24eab124 | 3172 | fprintf (stdout, " operation %d\n", e->X_op); |
b77ad1d4 AM |
3173 | fprintf (stdout, " add_number %ld (%lx)\n", |
3174 | (long) e->X_add_number, (long) e->X_add_number); | |
252b5132 RH |
3175 | if (e->X_add_symbol) |
3176 | { | |
3177 | fprintf (stdout, " add_symbol "); | |
3178 | ps (e->X_add_symbol); | |
3179 | fprintf (stdout, "\n"); | |
3180 | } | |
3181 | if (e->X_op_symbol) | |
3182 | { | |
3183 | fprintf (stdout, " op_symbol "); | |
3184 | ps (e->X_op_symbol); | |
3185 | fprintf (stdout, "\n"); | |
3186 | } | |
3187 | } | |
3188 | ||
3189 | static void | |
e3bb37b5 | 3190 | ps (symbolS *s) |
252b5132 RH |
3191 | { |
3192 | fprintf (stdout, "%s type %s%s", | |
3193 | S_GET_NAME (s), | |
3194 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
3195 | segment_name (S_GET_SEGMENT (s))); | |
3196 | } | |
3197 | ||
7b81dfbb | 3198 | static struct type_name |
252b5132 | 3199 | { |
40fb9820 L |
3200 | i386_operand_type mask; |
3201 | const char *name; | |
252b5132 | 3202 | } |
7b81dfbb | 3203 | const type_names[] = |
252b5132 | 3204 | { |
40fb9820 L |
3205 | { OPERAND_TYPE_REG8, "r8" }, |
3206 | { OPERAND_TYPE_REG16, "r16" }, | |
3207 | { OPERAND_TYPE_REG32, "r32" }, | |
3208 | { OPERAND_TYPE_REG64, "r64" }, | |
2c703856 JB |
3209 | { OPERAND_TYPE_ACC8, "acc8" }, |
3210 | { OPERAND_TYPE_ACC16, "acc16" }, | |
3211 | { OPERAND_TYPE_ACC32, "acc32" }, | |
3212 | { OPERAND_TYPE_ACC64, "acc64" }, | |
40fb9820 L |
3213 | { OPERAND_TYPE_IMM8, "i8" }, |
3214 | { OPERAND_TYPE_IMM8, "i8s" }, | |
3215 | { OPERAND_TYPE_IMM16, "i16" }, | |
3216 | { OPERAND_TYPE_IMM32, "i32" }, | |
3217 | { OPERAND_TYPE_IMM32S, "i32s" }, | |
3218 | { OPERAND_TYPE_IMM64, "i64" }, | |
3219 | { OPERAND_TYPE_IMM1, "i1" }, | |
3220 | { OPERAND_TYPE_BASEINDEX, "BaseIndex" }, | |
3221 | { OPERAND_TYPE_DISP8, "d8" }, | |
3222 | { OPERAND_TYPE_DISP16, "d16" }, | |
3223 | { OPERAND_TYPE_DISP32, "d32" }, | |
3224 | { OPERAND_TYPE_DISP32S, "d32s" }, | |
3225 | { OPERAND_TYPE_DISP64, "d64" }, | |
3226 | { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" }, | |
3227 | { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" }, | |
3228 | { OPERAND_TYPE_CONTROL, "control reg" }, | |
3229 | { OPERAND_TYPE_TEST, "test reg" }, | |
3230 | { OPERAND_TYPE_DEBUG, "debug reg" }, | |
3231 | { OPERAND_TYPE_FLOATREG, "FReg" }, | |
3232 | { OPERAND_TYPE_FLOATACC, "FAcc" }, | |
21df382b | 3233 | { OPERAND_TYPE_SREG, "SReg" }, |
40fb9820 L |
3234 | { OPERAND_TYPE_REGMMX, "rMMX" }, |
3235 | { OPERAND_TYPE_REGXMM, "rXMM" }, | |
0349dc08 | 3236 | { OPERAND_TYPE_REGYMM, "rYMM" }, |
43234a1e L |
3237 | { OPERAND_TYPE_REGZMM, "rZMM" }, |
3238 | { OPERAND_TYPE_REGMASK, "Mask reg" }, | |
252b5132 RH |
3239 | }; |
3240 | ||
3241 | static void | |
40fb9820 | 3242 | pt (i386_operand_type t) |
252b5132 | 3243 | { |
40fb9820 | 3244 | unsigned int j; |
c6fb90c8 | 3245 | i386_operand_type a; |
252b5132 | 3246 | |
40fb9820 | 3247 | for (j = 0; j < ARRAY_SIZE (type_names); j++) |
c6fb90c8 L |
3248 | { |
3249 | a = operand_type_and (t, type_names[j].mask); | |
2c703856 | 3250 | if (operand_type_equal (&a, &type_names[j].mask)) |
c6fb90c8 L |
3251 | fprintf (stdout, "%s, ", type_names[j].name); |
3252 | } | |
252b5132 RH |
3253 | fflush (stdout); |
3254 | } | |
3255 | ||
3256 | #endif /* DEBUG386 */ | |
3257 | \f | |
252b5132 | 3258 | static bfd_reloc_code_real_type |
3956db08 | 3259 | reloc (unsigned int size, |
64e74474 AM |
3260 | int pcrel, |
3261 | int sign, | |
3262 | bfd_reloc_code_real_type other) | |
252b5132 | 3263 | { |
47926f60 | 3264 | if (other != NO_RELOC) |
3956db08 | 3265 | { |
91d6fa6a | 3266 | reloc_howto_type *rel; |
3956db08 JB |
3267 | |
3268 | if (size == 8) | |
3269 | switch (other) | |
3270 | { | |
64e74474 AM |
3271 | case BFD_RELOC_X86_64_GOT32: |
3272 | return BFD_RELOC_X86_64_GOT64; | |
3273 | break; | |
553d1284 L |
3274 | case BFD_RELOC_X86_64_GOTPLT64: |
3275 | return BFD_RELOC_X86_64_GOTPLT64; | |
3276 | break; | |
64e74474 AM |
3277 | case BFD_RELOC_X86_64_PLTOFF64: |
3278 | return BFD_RELOC_X86_64_PLTOFF64; | |
3279 | break; | |
3280 | case BFD_RELOC_X86_64_GOTPC32: | |
3281 | other = BFD_RELOC_X86_64_GOTPC64; | |
3282 | break; | |
3283 | case BFD_RELOC_X86_64_GOTPCREL: | |
3284 | other = BFD_RELOC_X86_64_GOTPCREL64; | |
3285 | break; | |
3286 | case BFD_RELOC_X86_64_TPOFF32: | |
3287 | other = BFD_RELOC_X86_64_TPOFF64; | |
3288 | break; | |
3289 | case BFD_RELOC_X86_64_DTPOFF32: | |
3290 | other = BFD_RELOC_X86_64_DTPOFF64; | |
3291 | break; | |
3292 | default: | |
3293 | break; | |
3956db08 | 3294 | } |
e05278af | 3295 | |
8ce3d284 | 3296 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
3297 | if (other == BFD_RELOC_SIZE32) |
3298 | { | |
3299 | if (size == 8) | |
1ab668bf | 3300 | other = BFD_RELOC_SIZE64; |
8fd4256d | 3301 | if (pcrel) |
1ab668bf AM |
3302 | { |
3303 | as_bad (_("there are no pc-relative size relocations")); | |
3304 | return NO_RELOC; | |
3305 | } | |
8fd4256d | 3306 | } |
8ce3d284 | 3307 | #endif |
8fd4256d | 3308 | |
e05278af | 3309 | /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ |
f2d8a97c | 3310 | if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc)) |
e05278af JB |
3311 | sign = -1; |
3312 | ||
91d6fa6a NC |
3313 | rel = bfd_reloc_type_lookup (stdoutput, other); |
3314 | if (!rel) | |
3956db08 | 3315 | as_bad (_("unknown relocation (%u)"), other); |
91d6fa6a | 3316 | else if (size != bfd_get_reloc_size (rel)) |
3956db08 | 3317 | as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), |
91d6fa6a | 3318 | bfd_get_reloc_size (rel), |
3956db08 | 3319 | size); |
91d6fa6a | 3320 | else if (pcrel && !rel->pc_relative) |
3956db08 | 3321 | as_bad (_("non-pc-relative relocation for pc-relative field")); |
91d6fa6a | 3322 | else if ((rel->complain_on_overflow == complain_overflow_signed |
3956db08 | 3323 | && !sign) |
91d6fa6a | 3324 | || (rel->complain_on_overflow == complain_overflow_unsigned |
64e74474 | 3325 | && sign > 0)) |
3956db08 JB |
3326 | as_bad (_("relocated field and relocation type differ in signedness")); |
3327 | else | |
3328 | return other; | |
3329 | return NO_RELOC; | |
3330 | } | |
252b5132 RH |
3331 | |
3332 | if (pcrel) | |
3333 | { | |
3e73aa7c | 3334 | if (!sign) |
3956db08 | 3335 | as_bad (_("there are no unsigned pc-relative relocations")); |
252b5132 RH |
3336 | switch (size) |
3337 | { | |
3338 | case 1: return BFD_RELOC_8_PCREL; | |
3339 | case 2: return BFD_RELOC_16_PCREL; | |
d258b828 | 3340 | case 4: return BFD_RELOC_32_PCREL; |
d6ab8113 | 3341 | case 8: return BFD_RELOC_64_PCREL; |
252b5132 | 3342 | } |
3956db08 | 3343 | as_bad (_("cannot do %u byte pc-relative relocation"), size); |
252b5132 RH |
3344 | } |
3345 | else | |
3346 | { | |
3956db08 | 3347 | if (sign > 0) |
e5cb08ac | 3348 | switch (size) |
3e73aa7c JH |
3349 | { |
3350 | case 4: return BFD_RELOC_X86_64_32S; | |
3351 | } | |
3352 | else | |
3353 | switch (size) | |
3354 | { | |
3355 | case 1: return BFD_RELOC_8; | |
3356 | case 2: return BFD_RELOC_16; | |
3357 | case 4: return BFD_RELOC_32; | |
3358 | case 8: return BFD_RELOC_64; | |
3359 | } | |
3956db08 JB |
3360 | as_bad (_("cannot do %s %u byte relocation"), |
3361 | sign > 0 ? "signed" : "unsigned", size); | |
252b5132 RH |
3362 | } |
3363 | ||
0cc9e1d3 | 3364 | return NO_RELOC; |
252b5132 RH |
3365 | } |
3366 | ||
47926f60 KH |
3367 | /* Here we decide which fixups can be adjusted to make them relative to |
3368 | the beginning of the section instead of the symbol. Basically we need | |
3369 | to make sure that the dynamic relocations are done correctly, so in | |
3370 | some cases we force the original symbol to be used. */ | |
3371 | ||
252b5132 | 3372 | int |
e3bb37b5 | 3373 | tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) |
252b5132 | 3374 | { |
6d249963 | 3375 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 3376 | if (!IS_ELF) |
31312f95 AM |
3377 | return 1; |
3378 | ||
a161fe53 AM |
3379 | /* Don't adjust pc-relative references to merge sections in 64-bit |
3380 | mode. */ | |
3381 | if (use_rela_relocations | |
3382 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 | |
3383 | && fixP->fx_pcrel) | |
252b5132 | 3384 | return 0; |
31312f95 | 3385 | |
8d01d9a9 AJ |
3386 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
3387 | and changed later by validate_fix. */ | |
3388 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol | |
3389 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) | |
3390 | return 0; | |
3391 | ||
8fd4256d L |
3392 | /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol |
3393 | for size relocations. */ | |
3394 | if (fixP->fx_r_type == BFD_RELOC_SIZE32 | |
3395 | || fixP->fx_r_type == BFD_RELOC_SIZE64 | |
3396 | || fixP->fx_r_type == BFD_RELOC_386_GOTOFF | |
252b5132 RH |
3397 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 |
3398 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 | |
02a86693 | 3399 | || fixP->fx_r_type == BFD_RELOC_386_GOT32X |
13ae64f3 JJ |
3400 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
3401 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM | |
3402 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 | |
3403 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 | |
37e55690 JJ |
3404 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
3405 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE | |
13ae64f3 JJ |
3406 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
3407 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE | |
67a4f2b7 AO |
3408 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC |
3409 | || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL | |
3e73aa7c JH |
3410 | || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 |
3411 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 | |
80b3ee89 | 3412 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
56ceb5b5 L |
3413 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX |
3414 | || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX | |
bffbf940 JJ |
3415 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
3416 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD | |
3417 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 | |
d6ab8113 | 3418 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 |
bffbf940 JJ |
3419 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF |
3420 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 | |
d6ab8113 JB |
3421 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 |
3422 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 | |
67a4f2b7 AO |
3423 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
3424 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL | |
252b5132 RH |
3425 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
3426 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
3427 | return 0; | |
31312f95 | 3428 | #endif |
252b5132 RH |
3429 | return 1; |
3430 | } | |
252b5132 | 3431 | |
b4cac588 | 3432 | static int |
e3bb37b5 | 3433 | intel_float_operand (const char *mnemonic) |
252b5132 | 3434 | { |
9306ca4a JB |
3435 | /* Note that the value returned is meaningful only for opcodes with (memory) |
3436 | operands, hence the code here is free to improperly handle opcodes that | |
3437 | have no operands (for better performance and smaller code). */ | |
3438 | ||
3439 | if (mnemonic[0] != 'f') | |
3440 | return 0; /* non-math */ | |
3441 | ||
3442 | switch (mnemonic[1]) | |
3443 | { | |
3444 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and | |
3445 | the fs segment override prefix not currently handled because no | |
3446 | call path can make opcodes without operands get here */ | |
3447 | case 'i': | |
3448 | return 2 /* integer op */; | |
3449 | case 'l': | |
3450 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) | |
3451 | return 3; /* fldcw/fldenv */ | |
3452 | break; | |
3453 | case 'n': | |
3454 | if (mnemonic[2] != 'o' /* fnop */) | |
3455 | return 3; /* non-waiting control op */ | |
3456 | break; | |
3457 | case 'r': | |
3458 | if (mnemonic[2] == 's') | |
3459 | return 3; /* frstor/frstpm */ | |
3460 | break; | |
3461 | case 's': | |
3462 | if (mnemonic[2] == 'a') | |
3463 | return 3; /* fsave */ | |
3464 | if (mnemonic[2] == 't') | |
3465 | { | |
3466 | switch (mnemonic[3]) | |
3467 | { | |
3468 | case 'c': /* fstcw */ | |
3469 | case 'd': /* fstdw */ | |
3470 | case 'e': /* fstenv */ | |
3471 | case 's': /* fsts[gw] */ | |
3472 | return 3; | |
3473 | } | |
3474 | } | |
3475 | break; | |
3476 | case 'x': | |
3477 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') | |
3478 | return 0; /* fxsave/fxrstor are not really math ops */ | |
3479 | break; | |
3480 | } | |
252b5132 | 3481 | |
9306ca4a | 3482 | return 1; |
252b5132 RH |
3483 | } |
3484 | ||
c0f3af97 L |
3485 | /* Build the VEX prefix. */ |
3486 | ||
3487 | static void | |
d3ce72d0 | 3488 | build_vex_prefix (const insn_template *t) |
c0f3af97 L |
3489 | { |
3490 | unsigned int register_specifier; | |
3491 | unsigned int implied_prefix; | |
3492 | unsigned int vector_length; | |
03751133 | 3493 | unsigned int w; |
c0f3af97 L |
3494 | |
3495 | /* Check register specifier. */ | |
3496 | if (i.vex.register_specifier) | |
43234a1e L |
3497 | { |
3498 | register_specifier = | |
3499 | ~register_number (i.vex.register_specifier) & 0xf; | |
3500 | gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0); | |
3501 | } | |
c0f3af97 L |
3502 | else |
3503 | register_specifier = 0xf; | |
3504 | ||
79f0fa25 L |
3505 | /* Use 2-byte VEX prefix by swapping destination and source operand |
3506 | if there are more than 1 register operand. */ | |
3507 | if (i.reg_operands > 1 | |
3508 | && i.vec_encoding != vex_encoding_vex3 | |
86fa6981 | 3509 | && i.dir_encoding == dir_encoding_default |
fa99fab2 | 3510 | && i.operands == i.reg_operands |
dbbc8b7e | 3511 | && operand_type_equal (&i.types[0], &i.types[i.operands - 1]) |
7f399153 | 3512 | && i.tm.opcode_modifier.vexopcode == VEX0F |
dbbc8b7e | 3513 | && (i.tm.opcode_modifier.load || i.tm.opcode_modifier.d) |
fa99fab2 L |
3514 | && i.rex == REX_B) |
3515 | { | |
3516 | unsigned int xchg = i.operands - 1; | |
3517 | union i386_op temp_op; | |
3518 | i386_operand_type temp_type; | |
3519 | ||
3520 | temp_type = i.types[xchg]; | |
3521 | i.types[xchg] = i.types[0]; | |
3522 | i.types[0] = temp_type; | |
3523 | temp_op = i.op[xchg]; | |
3524 | i.op[xchg] = i.op[0]; | |
3525 | i.op[0] = temp_op; | |
3526 | ||
9c2799c2 | 3527 | gas_assert (i.rm.mode == 3); |
fa99fab2 L |
3528 | |
3529 | i.rex = REX_R; | |
3530 | xchg = i.rm.regmem; | |
3531 | i.rm.regmem = i.rm.reg; | |
3532 | i.rm.reg = xchg; | |
3533 | ||
dbbc8b7e JB |
3534 | if (i.tm.opcode_modifier.d) |
3535 | i.tm.base_opcode ^= (i.tm.base_opcode & 0xee) != 0x6e | |
3536 | ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD; | |
3537 | else /* Use the next insn. */ | |
3538 | i.tm = t[1]; | |
fa99fab2 L |
3539 | } |
3540 | ||
79dec6b7 JB |
3541 | /* Use 2-byte VEX prefix by swapping commutative source operands if there |
3542 | are no memory operands and at least 3 register ones. */ | |
3543 | if (i.reg_operands >= 3 | |
3544 | && i.vec_encoding != vex_encoding_vex3 | |
3545 | && i.reg_operands == i.operands - i.imm_operands | |
3546 | && i.tm.opcode_modifier.vex | |
3547 | && i.tm.opcode_modifier.commutative | |
3548 | && (i.tm.opcode_modifier.sse2avx || optimize > 1) | |
3549 | && i.rex == REX_B | |
3550 | && i.vex.register_specifier | |
3551 | && !(i.vex.register_specifier->reg_flags & RegRex)) | |
3552 | { | |
3553 | unsigned int xchg = i.operands - i.reg_operands; | |
3554 | union i386_op temp_op; | |
3555 | i386_operand_type temp_type; | |
3556 | ||
3557 | gas_assert (i.tm.opcode_modifier.vexopcode == VEX0F); | |
3558 | gas_assert (!i.tm.opcode_modifier.sae); | |
3559 | gas_assert (operand_type_equal (&i.types[i.operands - 2], | |
3560 | &i.types[i.operands - 3])); | |
3561 | gas_assert (i.rm.mode == 3); | |
3562 | ||
3563 | temp_type = i.types[xchg]; | |
3564 | i.types[xchg] = i.types[xchg + 1]; | |
3565 | i.types[xchg + 1] = temp_type; | |
3566 | temp_op = i.op[xchg]; | |
3567 | i.op[xchg] = i.op[xchg + 1]; | |
3568 | i.op[xchg + 1] = temp_op; | |
3569 | ||
3570 | i.rex = 0; | |
3571 | xchg = i.rm.regmem | 8; | |
3572 | i.rm.regmem = ~register_specifier & 0xf; | |
3573 | gas_assert (!(i.rm.regmem & 8)); | |
3574 | i.vex.register_specifier += xchg - i.rm.regmem; | |
3575 | register_specifier = ~xchg & 0xf; | |
3576 | } | |
3577 | ||
539f890d L |
3578 | if (i.tm.opcode_modifier.vex == VEXScalar) |
3579 | vector_length = avxscalar; | |
10c17abd JB |
3580 | else if (i.tm.opcode_modifier.vex == VEX256) |
3581 | vector_length = 1; | |
539f890d | 3582 | else |
10c17abd | 3583 | { |
56522fc5 | 3584 | unsigned int op; |
10c17abd | 3585 | |
c7213af9 L |
3586 | /* Determine vector length from the last multi-length vector |
3587 | operand. */ | |
10c17abd | 3588 | vector_length = 0; |
56522fc5 | 3589 | for (op = t->operands; op--;) |
10c17abd JB |
3590 | if (t->operand_types[op].bitfield.xmmword |
3591 | && t->operand_types[op].bitfield.ymmword | |
3592 | && i.types[op].bitfield.ymmword) | |
3593 | { | |
3594 | vector_length = 1; | |
3595 | break; | |
3596 | } | |
3597 | } | |
c0f3af97 L |
3598 | |
3599 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
3600 | { | |
3601 | case 0: | |
3602 | implied_prefix = 0; | |
3603 | break; | |
3604 | case DATA_PREFIX_OPCODE: | |
3605 | implied_prefix = 1; | |
3606 | break; | |
3607 | case REPE_PREFIX_OPCODE: | |
3608 | implied_prefix = 2; | |
3609 | break; | |
3610 | case REPNE_PREFIX_OPCODE: | |
3611 | implied_prefix = 3; | |
3612 | break; | |
3613 | default: | |
3614 | abort (); | |
3615 | } | |
3616 | ||
03751133 L |
3617 | /* Check the REX.W bit and VEXW. */ |
3618 | if (i.tm.opcode_modifier.vexw == VEXWIG) | |
3619 | w = (vexwig == vexw1 || (i.rex & REX_W)) ? 1 : 0; | |
3620 | else if (i.tm.opcode_modifier.vexw) | |
3621 | w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0; | |
3622 | else | |
931d03b7 | 3623 | w = (flag_code == CODE_64BIT ? i.rex & REX_W : vexwig == vexw1) ? 1 : 0; |
03751133 | 3624 | |
c0f3af97 | 3625 | /* Use 2-byte VEX prefix if possible. */ |
03751133 L |
3626 | if (w == 0 |
3627 | && i.vec_encoding != vex_encoding_vex3 | |
86fa6981 | 3628 | && i.tm.opcode_modifier.vexopcode == VEX0F |
c0f3af97 L |
3629 | && (i.rex & (REX_W | REX_X | REX_B)) == 0) |
3630 | { | |
3631 | /* 2-byte VEX prefix. */ | |
3632 | unsigned int r; | |
3633 | ||
3634 | i.vex.length = 2; | |
3635 | i.vex.bytes[0] = 0xc5; | |
3636 | ||
3637 | /* Check the REX.R bit. */ | |
3638 | r = (i.rex & REX_R) ? 0 : 1; | |
3639 | i.vex.bytes[1] = (r << 7 | |
3640 | | register_specifier << 3 | |
3641 | | vector_length << 2 | |
3642 | | implied_prefix); | |
3643 | } | |
3644 | else | |
3645 | { | |
3646 | /* 3-byte VEX prefix. */ | |
03751133 | 3647 | unsigned int m; |
c0f3af97 | 3648 | |
f88c9eb0 | 3649 | i.vex.length = 3; |
f88c9eb0 | 3650 | |
7f399153 | 3651 | switch (i.tm.opcode_modifier.vexopcode) |
5dd85c99 | 3652 | { |
7f399153 L |
3653 | case VEX0F: |
3654 | m = 0x1; | |
80de6e00 | 3655 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3656 | break; |
3657 | case VEX0F38: | |
3658 | m = 0x2; | |
80de6e00 | 3659 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3660 | break; |
3661 | case VEX0F3A: | |
3662 | m = 0x3; | |
80de6e00 | 3663 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3664 | break; |
3665 | case XOP08: | |
5dd85c99 SP |
3666 | m = 0x8; |
3667 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3668 | break; |
3669 | case XOP09: | |
f88c9eb0 SP |
3670 | m = 0x9; |
3671 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3672 | break; |
3673 | case XOP0A: | |
f88c9eb0 SP |
3674 | m = 0xa; |
3675 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3676 | break; |
3677 | default: | |
3678 | abort (); | |
f88c9eb0 | 3679 | } |
c0f3af97 | 3680 | |
c0f3af97 L |
3681 | /* The high 3 bits of the second VEX byte are 1's compliment |
3682 | of RXB bits from REX. */ | |
3683 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
3684 | ||
c0f3af97 L |
3685 | i.vex.bytes[2] = (w << 7 |
3686 | | register_specifier << 3 | |
3687 | | vector_length << 2 | |
3688 | | implied_prefix); | |
3689 | } | |
3690 | } | |
3691 | ||
e771e7c9 JB |
3692 | static INLINE bfd_boolean |
3693 | is_evex_encoding (const insn_template *t) | |
3694 | { | |
7091c612 | 3695 | return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift |
e771e7c9 | 3696 | || t->opcode_modifier.broadcast || t->opcode_modifier.masking |
a80195f1 | 3697 | || t->opcode_modifier.sae; |
e771e7c9 JB |
3698 | } |
3699 | ||
7a8655d2 JB |
3700 | static INLINE bfd_boolean |
3701 | is_any_vex_encoding (const insn_template *t) | |
3702 | { | |
3703 | return t->opcode_modifier.vex || t->opcode_modifier.vexopcode | |
3704 | || is_evex_encoding (t); | |
3705 | } | |
3706 | ||
43234a1e L |
3707 | /* Build the EVEX prefix. */ |
3708 | ||
3709 | static void | |
3710 | build_evex_prefix (void) | |
3711 | { | |
3712 | unsigned int register_specifier; | |
3713 | unsigned int implied_prefix; | |
3714 | unsigned int m, w; | |
3715 | rex_byte vrex_used = 0; | |
3716 | ||
3717 | /* Check register specifier. */ | |
3718 | if (i.vex.register_specifier) | |
3719 | { | |
3720 | gas_assert ((i.vrex & REX_X) == 0); | |
3721 | ||
3722 | register_specifier = i.vex.register_specifier->reg_num; | |
3723 | if ((i.vex.register_specifier->reg_flags & RegRex)) | |
3724 | register_specifier += 8; | |
3725 | /* The upper 16 registers are encoded in the fourth byte of the | |
3726 | EVEX prefix. */ | |
3727 | if (!(i.vex.register_specifier->reg_flags & RegVRex)) | |
3728 | i.vex.bytes[3] = 0x8; | |
3729 | register_specifier = ~register_specifier & 0xf; | |
3730 | } | |
3731 | else | |
3732 | { | |
3733 | register_specifier = 0xf; | |
3734 | ||
3735 | /* Encode upper 16 vector index register in the fourth byte of | |
3736 | the EVEX prefix. */ | |
3737 | if (!(i.vrex & REX_X)) | |
3738 | i.vex.bytes[3] = 0x8; | |
3739 | else | |
3740 | vrex_used |= REX_X; | |
3741 | } | |
3742 | ||
3743 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
3744 | { | |
3745 | case 0: | |
3746 | implied_prefix = 0; | |
3747 | break; | |
3748 | case DATA_PREFIX_OPCODE: | |
3749 | implied_prefix = 1; | |
3750 | break; | |
3751 | case REPE_PREFIX_OPCODE: | |
3752 | implied_prefix = 2; | |
3753 | break; | |
3754 | case REPNE_PREFIX_OPCODE: | |
3755 | implied_prefix = 3; | |
3756 | break; | |
3757 | default: | |
3758 | abort (); | |
3759 | } | |
3760 | ||
3761 | /* 4 byte EVEX prefix. */ | |
3762 | i.vex.length = 4; | |
3763 | i.vex.bytes[0] = 0x62; | |
3764 | ||
3765 | /* mmmm bits. */ | |
3766 | switch (i.tm.opcode_modifier.vexopcode) | |
3767 | { | |
3768 | case VEX0F: | |
3769 | m = 1; | |
3770 | break; | |
3771 | case VEX0F38: | |
3772 | m = 2; | |
3773 | break; | |
3774 | case VEX0F3A: | |
3775 | m = 3; | |
3776 | break; | |
3777 | default: | |
3778 | abort (); | |
3779 | break; | |
3780 | } | |
3781 | ||
3782 | /* The high 3 bits of the second EVEX byte are 1's compliment of RXB | |
3783 | bits from REX. */ | |
3784 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
3785 | ||
3786 | /* The fifth bit of the second EVEX byte is 1's compliment of the | |
3787 | REX_R bit in VREX. */ | |
3788 | if (!(i.vrex & REX_R)) | |
3789 | i.vex.bytes[1] |= 0x10; | |
3790 | else | |
3791 | vrex_used |= REX_R; | |
3792 | ||
3793 | if ((i.reg_operands + i.imm_operands) == i.operands) | |
3794 | { | |
3795 | /* When all operands are registers, the REX_X bit in REX is not | |
3796 | used. We reuse it to encode the upper 16 registers, which is | |
3797 | indicated by the REX_B bit in VREX. The REX_X bit is encoded | |
3798 | as 1's compliment. */ | |
3799 | if ((i.vrex & REX_B)) | |
3800 | { | |
3801 | vrex_used |= REX_B; | |
3802 | i.vex.bytes[1] &= ~0x40; | |
3803 | } | |
3804 | } | |
3805 | ||
3806 | /* EVEX instructions shouldn't need the REX prefix. */ | |
3807 | i.vrex &= ~vrex_used; | |
3808 | gas_assert (i.vrex == 0); | |
3809 | ||
6865c043 L |
3810 | /* Check the REX.W bit and VEXW. */ |
3811 | if (i.tm.opcode_modifier.vexw == VEXWIG) | |
3812 | w = (evexwig == evexw1 || (i.rex & REX_W)) ? 1 : 0; | |
3813 | else if (i.tm.opcode_modifier.vexw) | |
3814 | w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0; | |
3815 | else | |
931d03b7 | 3816 | w = (flag_code == CODE_64BIT ? i.rex & REX_W : evexwig == evexw1) ? 1 : 0; |
43234a1e L |
3817 | |
3818 | /* Encode the U bit. */ | |
3819 | implied_prefix |= 0x4; | |
3820 | ||
3821 | /* The third byte of the EVEX prefix. */ | |
3822 | i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix); | |
3823 | ||
3824 | /* The fourth byte of the EVEX prefix. */ | |
3825 | /* The zeroing-masking bit. */ | |
3826 | if (i.mask && i.mask->zeroing) | |
3827 | i.vex.bytes[3] |= 0x80; | |
3828 | ||
3829 | /* Don't always set the broadcast bit if there is no RC. */ | |
3830 | if (!i.rounding) | |
3831 | { | |
3832 | /* Encode the vector length. */ | |
3833 | unsigned int vec_length; | |
3834 | ||
e771e7c9 JB |
3835 | if (!i.tm.opcode_modifier.evex |
3836 | || i.tm.opcode_modifier.evex == EVEXDYN) | |
3837 | { | |
56522fc5 | 3838 | unsigned int op; |
e771e7c9 | 3839 | |
c7213af9 L |
3840 | /* Determine vector length from the last multi-length vector |
3841 | operand. */ | |
e771e7c9 | 3842 | vec_length = 0; |
56522fc5 | 3843 | for (op = i.operands; op--;) |
e771e7c9 JB |
3844 | if (i.tm.operand_types[op].bitfield.xmmword |
3845 | + i.tm.operand_types[op].bitfield.ymmword | |
3846 | + i.tm.operand_types[op].bitfield.zmmword > 1) | |
3847 | { | |
3848 | if (i.types[op].bitfield.zmmword) | |
c7213af9 L |
3849 | { |
3850 | i.tm.opcode_modifier.evex = EVEX512; | |
3851 | break; | |
3852 | } | |
e771e7c9 | 3853 | else if (i.types[op].bitfield.ymmword) |
c7213af9 L |
3854 | { |
3855 | i.tm.opcode_modifier.evex = EVEX256; | |
3856 | break; | |
3857 | } | |
e771e7c9 | 3858 | else if (i.types[op].bitfield.xmmword) |
c7213af9 L |
3859 | { |
3860 | i.tm.opcode_modifier.evex = EVEX128; | |
3861 | break; | |
3862 | } | |
625cbd7a JB |
3863 | else if (i.broadcast && (int) op == i.broadcast->operand) |
3864 | { | |
4a1b91ea | 3865 | switch (i.broadcast->bytes) |
625cbd7a JB |
3866 | { |
3867 | case 64: | |
3868 | i.tm.opcode_modifier.evex = EVEX512; | |
3869 | break; | |
3870 | case 32: | |
3871 | i.tm.opcode_modifier.evex = EVEX256; | |
3872 | break; | |
3873 | case 16: | |
3874 | i.tm.opcode_modifier.evex = EVEX128; | |
3875 | break; | |
3876 | default: | |
c7213af9 | 3877 | abort (); |
625cbd7a | 3878 | } |
c7213af9 | 3879 | break; |
625cbd7a | 3880 | } |
e771e7c9 | 3881 | } |
c7213af9 | 3882 | |
56522fc5 | 3883 | if (op >= MAX_OPERANDS) |
c7213af9 | 3884 | abort (); |
e771e7c9 JB |
3885 | } |
3886 | ||
43234a1e L |
3887 | switch (i.tm.opcode_modifier.evex) |
3888 | { | |
3889 | case EVEXLIG: /* LL' is ignored */ | |
3890 | vec_length = evexlig << 5; | |
3891 | break; | |
3892 | case EVEX128: | |
3893 | vec_length = 0 << 5; | |
3894 | break; | |
3895 | case EVEX256: | |
3896 | vec_length = 1 << 5; | |
3897 | break; | |
3898 | case EVEX512: | |
3899 | vec_length = 2 << 5; | |
3900 | break; | |
3901 | default: | |
3902 | abort (); | |
3903 | break; | |
3904 | } | |
3905 | i.vex.bytes[3] |= vec_length; | |
3906 | /* Encode the broadcast bit. */ | |
3907 | if (i.broadcast) | |
3908 | i.vex.bytes[3] |= 0x10; | |
3909 | } | |
3910 | else | |
3911 | { | |
3912 | if (i.rounding->type != saeonly) | |
3913 | i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5); | |
3914 | else | |
d3d3c6db | 3915 | i.vex.bytes[3] |= 0x10 | (evexrcig << 5); |
43234a1e L |
3916 | } |
3917 | ||
3918 | if (i.mask && i.mask->mask) | |
3919 | i.vex.bytes[3] |= i.mask->mask->reg_num; | |
3920 | } | |
3921 | ||
65da13b5 L |
3922 | static void |
3923 | process_immext (void) | |
3924 | { | |
3925 | expressionS *exp; | |
3926 | ||
c0f3af97 | 3927 | /* These AMD 3DNow! and SSE2 instructions have an opcode suffix |
65da13b5 L |
3928 | which is coded in the same place as an 8-bit immediate field |
3929 | would be. Here we fake an 8-bit immediate operand from the | |
3930 | opcode suffix stored in tm.extension_opcode. | |
3931 | ||
c1e679ec | 3932 | AVX instructions also use this encoding, for some of |
c0f3af97 | 3933 | 3 argument instructions. */ |
65da13b5 | 3934 | |
43234a1e | 3935 | gas_assert (i.imm_operands <= 1 |
7ab9ffdd | 3936 | && (i.operands <= 2 |
7a8655d2 | 3937 | || (is_any_vex_encoding (&i.tm) |
7ab9ffdd | 3938 | && i.operands <= 4))); |
65da13b5 L |
3939 | |
3940 | exp = &im_expressions[i.imm_operands++]; | |
3941 | i.op[i.operands].imms = exp; | |
3942 | i.types[i.operands] = imm8; | |
3943 | i.operands++; | |
3944 | exp->X_op = O_constant; | |
3945 | exp->X_add_number = i.tm.extension_opcode; | |
3946 | i.tm.extension_opcode = None; | |
3947 | } | |
3948 | ||
42164a71 L |
3949 | |
3950 | static int | |
3951 | check_hle (void) | |
3952 | { | |
3953 | switch (i.tm.opcode_modifier.hleprefixok) | |
3954 | { | |
3955 | default: | |
3956 | abort (); | |
82c2def5 | 3957 | case HLEPrefixNone: |
165de32a L |
3958 | as_bad (_("invalid instruction `%s' after `%s'"), |
3959 | i.tm.name, i.hle_prefix); | |
42164a71 | 3960 | return 0; |
82c2def5 | 3961 | case HLEPrefixLock: |
42164a71 L |
3962 | if (i.prefix[LOCK_PREFIX]) |
3963 | return 1; | |
165de32a | 3964 | as_bad (_("missing `lock' with `%s'"), i.hle_prefix); |
42164a71 | 3965 | return 0; |
82c2def5 | 3966 | case HLEPrefixAny: |
42164a71 | 3967 | return 1; |
82c2def5 | 3968 | case HLEPrefixRelease: |
42164a71 L |
3969 | if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE) |
3970 | { | |
3971 | as_bad (_("instruction `%s' after `xacquire' not allowed"), | |
3972 | i.tm.name); | |
3973 | return 0; | |
3974 | } | |
8dc0818e | 3975 | if (i.mem_operands == 0 || !(i.flags[i.operands - 1] & Operand_Mem)) |
42164a71 L |
3976 | { |
3977 | as_bad (_("memory destination needed for instruction `%s'" | |
3978 | " after `xrelease'"), i.tm.name); | |
3979 | return 0; | |
3980 | } | |
3981 | return 1; | |
3982 | } | |
3983 | } | |
3984 | ||
b6f8c7c4 L |
3985 | /* Try the shortest encoding by shortening operand size. */ |
3986 | ||
3987 | static void | |
3988 | optimize_encoding (void) | |
3989 | { | |
a0a1771e | 3990 | unsigned int j; |
b6f8c7c4 L |
3991 | |
3992 | if (optimize_for_space | |
3993 | && i.reg_operands == 1 | |
3994 | && i.imm_operands == 1 | |
3995 | && !i.types[1].bitfield.byte | |
3996 | && i.op[0].imms->X_op == O_constant | |
3997 | && fits_in_imm7 (i.op[0].imms->X_add_number) | |
3998 | && ((i.tm.base_opcode == 0xa8 | |
3999 | && i.tm.extension_opcode == None) | |
4000 | || (i.tm.base_opcode == 0xf6 | |
4001 | && i.tm.extension_opcode == 0x0))) | |
4002 | { | |
4003 | /* Optimize: -Os: | |
4004 | test $imm7, %r64/%r32/%r16 -> test $imm7, %r8 | |
4005 | */ | |
4006 | unsigned int base_regnum = i.op[1].regs->reg_num; | |
4007 | if (flag_code == CODE_64BIT || base_regnum < 4) | |
4008 | { | |
4009 | i.types[1].bitfield.byte = 1; | |
4010 | /* Ignore the suffix. */ | |
4011 | i.suffix = 0; | |
7697afb6 JB |
4012 | /* Convert to byte registers. */ |
4013 | if (i.types[1].bitfield.word) | |
4014 | j = 16; | |
4015 | else if (i.types[1].bitfield.dword) | |
4016 | j = 32; | |
4017 | else | |
4018 | j = 48; | |
4019 | if (!(i.op[1].regs->reg_flags & RegRex) && base_regnum < 4) | |
4020 | j += 8; | |
4021 | i.op[1].regs -= j; | |
b6f8c7c4 L |
4022 | } |
4023 | } | |
4024 | else if (flag_code == CODE_64BIT | |
d3d50934 L |
4025 | && ((i.types[1].bitfield.qword |
4026 | && i.reg_operands == 1 | |
b6f8c7c4 L |
4027 | && i.imm_operands == 1 |
4028 | && i.op[0].imms->X_op == O_constant | |
507916b8 | 4029 | && ((i.tm.base_opcode == 0xb8 |
b6f8c7c4 L |
4030 | && i.tm.extension_opcode == None |
4031 | && fits_in_unsigned_long (i.op[0].imms->X_add_number)) | |
4032 | || (fits_in_imm31 (i.op[0].imms->X_add_number) | |
4033 | && (((i.tm.base_opcode == 0x24 | |
4034 | || i.tm.base_opcode == 0xa8) | |
4035 | && i.tm.extension_opcode == None) | |
4036 | || (i.tm.base_opcode == 0x80 | |
4037 | && i.tm.extension_opcode == 0x4) | |
4038 | || ((i.tm.base_opcode == 0xf6 | |
507916b8 | 4039 | || (i.tm.base_opcode | 1) == 0xc7) |
b8364fa7 JB |
4040 | && i.tm.extension_opcode == 0x0))) |
4041 | || (fits_in_imm7 (i.op[0].imms->X_add_number) | |
4042 | && i.tm.base_opcode == 0x83 | |
4043 | && i.tm.extension_opcode == 0x4))) | |
d3d50934 L |
4044 | || (i.types[0].bitfield.qword |
4045 | && ((i.reg_operands == 2 | |
4046 | && i.op[0].regs == i.op[1].regs | |
4047 | && ((i.tm.base_opcode == 0x30 | |
4048 | || i.tm.base_opcode == 0x28) | |
4049 | && i.tm.extension_opcode == None)) | |
4050 | || (i.reg_operands == 1 | |
4051 | && i.operands == 1 | |
4052 | && i.tm.base_opcode == 0x30 | |
4053 | && i.tm.extension_opcode == None))))) | |
b6f8c7c4 L |
4054 | { |
4055 | /* Optimize: -O: | |
4056 | andq $imm31, %r64 -> andl $imm31, %r32 | |
b8364fa7 | 4057 | andq $imm7, %r64 -> andl $imm7, %r32 |
b6f8c7c4 L |
4058 | testq $imm31, %r64 -> testl $imm31, %r32 |
4059 | xorq %r64, %r64 -> xorl %r32, %r32 | |
4060 | subq %r64, %r64 -> subl %r32, %r32 | |
4061 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4062 | movq $imm32, %r64 -> movl $imm32, %r32 | |
4063 | */ | |
4064 | i.tm.opcode_modifier.norex64 = 1; | |
507916b8 | 4065 | if (i.tm.base_opcode == 0xb8 || (i.tm.base_opcode | 1) == 0xc7) |
b6f8c7c4 L |
4066 | { |
4067 | /* Handle | |
4068 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4069 | movq $imm32, %r64 -> movl $imm32, %r32 | |
4070 | */ | |
4071 | i.tm.operand_types[0].bitfield.imm32 = 1; | |
4072 | i.tm.operand_types[0].bitfield.imm32s = 0; | |
4073 | i.tm.operand_types[0].bitfield.imm64 = 0; | |
4074 | i.types[0].bitfield.imm32 = 1; | |
4075 | i.types[0].bitfield.imm32s = 0; | |
4076 | i.types[0].bitfield.imm64 = 0; | |
4077 | i.types[1].bitfield.dword = 1; | |
4078 | i.types[1].bitfield.qword = 0; | |
507916b8 | 4079 | if ((i.tm.base_opcode | 1) == 0xc7) |
b6f8c7c4 L |
4080 | { |
4081 | /* Handle | |
4082 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4083 | */ | |
507916b8 | 4084 | i.tm.base_opcode = 0xb8; |
b6f8c7c4 | 4085 | i.tm.extension_opcode = None; |
507916b8 | 4086 | i.tm.opcode_modifier.w = 0; |
b6f8c7c4 L |
4087 | i.tm.opcode_modifier.shortform = 1; |
4088 | i.tm.opcode_modifier.modrm = 0; | |
4089 | } | |
4090 | } | |
4091 | } | |
5641ec01 JB |
4092 | else if (optimize > 1 |
4093 | && !optimize_for_space | |
4094 | && i.reg_operands == 2 | |
4095 | && i.op[0].regs == i.op[1].regs | |
4096 | && ((i.tm.base_opcode & ~(Opcode_D | 1)) == 0x8 | |
4097 | || (i.tm.base_opcode & ~(Opcode_D | 1)) == 0x20) | |
4098 | && (flag_code != CODE_64BIT || !i.types[0].bitfield.dword)) | |
4099 | { | |
4100 | /* Optimize: -O2: | |
4101 | andb %rN, %rN -> testb %rN, %rN | |
4102 | andw %rN, %rN -> testw %rN, %rN | |
4103 | andq %rN, %rN -> testq %rN, %rN | |
4104 | orb %rN, %rN -> testb %rN, %rN | |
4105 | orw %rN, %rN -> testw %rN, %rN | |
4106 | orq %rN, %rN -> testq %rN, %rN | |
4107 | ||
4108 | and outside of 64-bit mode | |
4109 | ||
4110 | andl %rN, %rN -> testl %rN, %rN | |
4111 | orl %rN, %rN -> testl %rN, %rN | |
4112 | */ | |
4113 | i.tm.base_opcode = 0x84 | (i.tm.base_opcode & 1); | |
4114 | } | |
99112332 | 4115 | else if (i.reg_operands == 3 |
b6f8c7c4 L |
4116 | && i.op[0].regs == i.op[1].regs |
4117 | && !i.types[2].bitfield.xmmword | |
4118 | && (i.tm.opcode_modifier.vex | |
7a69eac3 | 4119 | || ((!i.mask || i.mask->zeroing) |
b6f8c7c4 | 4120 | && !i.rounding |
e771e7c9 | 4121 | && is_evex_encoding (&i.tm) |
80c34c38 | 4122 | && (i.vec_encoding != vex_encoding_evex |
dd22218c | 4123 | || cpu_arch_isa_flags.bitfield.cpuavx512vl |
80c34c38 | 4124 | || i.tm.cpu_flags.bitfield.cpuavx512vl |
7091c612 | 4125 | || (i.tm.operand_types[2].bitfield.zmmword |
dd22218c | 4126 | && i.types[2].bitfield.ymmword)))) |
b6f8c7c4 L |
4127 | && ((i.tm.base_opcode == 0x55 |
4128 | || i.tm.base_opcode == 0x6655 | |
4129 | || i.tm.base_opcode == 0x66df | |
4130 | || i.tm.base_opcode == 0x57 | |
4131 | || i.tm.base_opcode == 0x6657 | |
8305403a L |
4132 | || i.tm.base_opcode == 0x66ef |
4133 | || i.tm.base_opcode == 0x66f8 | |
4134 | || i.tm.base_opcode == 0x66f9 | |
4135 | || i.tm.base_opcode == 0x66fa | |
1424ad86 JB |
4136 | || i.tm.base_opcode == 0x66fb |
4137 | || i.tm.base_opcode == 0x42 | |
4138 | || i.tm.base_opcode == 0x6642 | |
4139 | || i.tm.base_opcode == 0x47 | |
4140 | || i.tm.base_opcode == 0x6647) | |
b6f8c7c4 L |
4141 | && i.tm.extension_opcode == None)) |
4142 | { | |
99112332 | 4143 | /* Optimize: -O1: |
8305403a L |
4144 | VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd, |
4145 | vpsubq and vpsubw: | |
b6f8c7c4 L |
4146 | EVEX VOP %zmmM, %zmmM, %zmmN |
4147 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4148 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4149 | EVEX VOP %ymmM, %ymmM, %ymmN |
4150 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4151 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4152 | VEX VOP %ymmM, %ymmM, %ymmN |
4153 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
4154 | VOP, one of vpandn and vpxor: | |
4155 | VEX VOP %ymmM, %ymmM, %ymmN | |
4156 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
4157 | VOP, one of vpandnd and vpandnq: | |
4158 | EVEX VOP %zmmM, %zmmM, %zmmN | |
4159 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4160 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4161 | EVEX VOP %ymmM, %ymmM, %ymmN |
4162 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4163 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4164 | VOP, one of vpxord and vpxorq: |
4165 | EVEX VOP %zmmM, %zmmM, %zmmN | |
4166 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4167 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4168 | EVEX VOP %ymmM, %ymmM, %ymmN |
4169 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4170 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
1424ad86 JB |
4171 | VOP, one of kxord and kxorq: |
4172 | VEX VOP %kM, %kM, %kN | |
4173 | -> VEX kxorw %kM, %kM, %kN | |
4174 | VOP, one of kandnd and kandnq: | |
4175 | VEX VOP %kM, %kM, %kN | |
4176 | -> VEX kandnw %kM, %kM, %kN | |
b6f8c7c4 | 4177 | */ |
e771e7c9 | 4178 | if (is_evex_encoding (&i.tm)) |
b6f8c7c4 | 4179 | { |
7b1d7ca1 | 4180 | if (i.vec_encoding != vex_encoding_evex) |
b6f8c7c4 L |
4181 | { |
4182 | i.tm.opcode_modifier.vex = VEX128; | |
4183 | i.tm.opcode_modifier.vexw = VEXW0; | |
4184 | i.tm.opcode_modifier.evex = 0; | |
4185 | } | |
7b1d7ca1 | 4186 | else if (optimize > 1) |
dd22218c L |
4187 | i.tm.opcode_modifier.evex = EVEX128; |
4188 | else | |
4189 | return; | |
b6f8c7c4 | 4190 | } |
f74a6307 | 4191 | else if (i.tm.operand_types[0].bitfield.class == RegMask) |
1424ad86 JB |
4192 | { |
4193 | i.tm.base_opcode &= 0xff; | |
4194 | i.tm.opcode_modifier.vexw = VEXW0; | |
4195 | } | |
b6f8c7c4 L |
4196 | else |
4197 | i.tm.opcode_modifier.vex = VEX128; | |
4198 | ||
4199 | if (i.tm.opcode_modifier.vex) | |
4200 | for (j = 0; j < 3; j++) | |
4201 | { | |
4202 | i.types[j].bitfield.xmmword = 1; | |
4203 | i.types[j].bitfield.ymmword = 0; | |
4204 | } | |
4205 | } | |
392a5972 | 4206 | else if (i.vec_encoding != vex_encoding_evex |
97ed31ae | 4207 | && !i.types[0].bitfield.zmmword |
392a5972 | 4208 | && !i.types[1].bitfield.zmmword |
97ed31ae | 4209 | && !i.mask |
a0a1771e | 4210 | && !i.broadcast |
97ed31ae | 4211 | && is_evex_encoding (&i.tm) |
392a5972 L |
4212 | && ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0x666f |
4213 | || (i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf36f | |
a0a1771e JB |
4214 | || (i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf26f |
4215 | || (i.tm.base_opcode & ~4) == 0x66db | |
4216 | || (i.tm.base_opcode & ~4) == 0x66eb) | |
97ed31ae L |
4217 | && i.tm.extension_opcode == None) |
4218 | { | |
4219 | /* Optimize: -O1: | |
4220 | VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, | |
4221 | vmovdqu32 and vmovdqu64: | |
4222 | EVEX VOP %xmmM, %xmmN | |
4223 | -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16) | |
4224 | EVEX VOP %ymmM, %ymmN | |
4225 | -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16) | |
4226 | EVEX VOP %xmmM, mem | |
4227 | -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16) | |
4228 | EVEX VOP %ymmM, mem | |
4229 | -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16) | |
4230 | EVEX VOP mem, %xmmN | |
4231 | -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16) | |
4232 | EVEX VOP mem, %ymmN | |
4233 | -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16) | |
a0a1771e JB |
4234 | VOP, one of vpand, vpandn, vpor, vpxor: |
4235 | EVEX VOP{d,q} %xmmL, %xmmM, %xmmN | |
4236 | -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16) | |
4237 | EVEX VOP{d,q} %ymmL, %ymmM, %ymmN | |
4238 | -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16) | |
4239 | EVEX VOP{d,q} mem, %xmmM, %xmmN | |
4240 | -> VEX VOP mem, %xmmM, %xmmN (M and N < 16) | |
4241 | EVEX VOP{d,q} mem, %ymmM, %ymmN | |
4242 | -> VEX VOP mem, %ymmM, %ymmN (M and N < 16) | |
97ed31ae | 4243 | */ |
a0a1771e | 4244 | for (j = 0; j < i.operands; j++) |
392a5972 L |
4245 | if (operand_type_check (i.types[j], disp) |
4246 | && i.op[j].disps->X_op == O_constant) | |
4247 | { | |
4248 | /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix | |
4249 | has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4 | |
4250 | bytes, we choose EVEX Disp8 over VEX Disp32. */ | |
4251 | int evex_disp8, vex_disp8; | |
4252 | unsigned int memshift = i.memshift; | |
4253 | offsetT n = i.op[j].disps->X_add_number; | |
4254 | ||
4255 | evex_disp8 = fits_in_disp8 (n); | |
4256 | i.memshift = 0; | |
4257 | vex_disp8 = fits_in_disp8 (n); | |
4258 | if (evex_disp8 != vex_disp8) | |
4259 | { | |
4260 | i.memshift = memshift; | |
4261 | return; | |
4262 | } | |
4263 | ||
4264 | i.types[j].bitfield.disp8 = vex_disp8; | |
4265 | break; | |
4266 | } | |
4267 | if ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf26f) | |
4268 | i.tm.base_opcode ^= 0xf36f ^ 0xf26f; | |
97ed31ae L |
4269 | i.tm.opcode_modifier.vex |
4270 | = i.types[0].bitfield.ymmword ? VEX256 : VEX128; | |
4271 | i.tm.opcode_modifier.vexw = VEXW0; | |
79dec6b7 JB |
4272 | /* VPAND, VPOR, and VPXOR are commutative. */ |
4273 | if (i.reg_operands == 3 && i.tm.base_opcode != 0x66df) | |
4274 | i.tm.opcode_modifier.commutative = 1; | |
97ed31ae L |
4275 | i.tm.opcode_modifier.evex = 0; |
4276 | i.tm.opcode_modifier.masking = 0; | |
a0a1771e | 4277 | i.tm.opcode_modifier.broadcast = 0; |
97ed31ae L |
4278 | i.tm.opcode_modifier.disp8memshift = 0; |
4279 | i.memshift = 0; | |
a0a1771e JB |
4280 | if (j < i.operands) |
4281 | i.types[j].bitfield.disp8 | |
4282 | = fits_in_disp8 (i.op[j].disps->X_add_number); | |
97ed31ae | 4283 | } |
b6f8c7c4 L |
4284 | } |
4285 | ||
252b5132 RH |
4286 | /* This is the guts of the machine-dependent assembler. LINE points to a |
4287 | machine dependent instruction. This function is supposed to emit | |
4288 | the frags/bytes it assembles to. */ | |
4289 | ||
4290 | void | |
65da13b5 | 4291 | md_assemble (char *line) |
252b5132 | 4292 | { |
40fb9820 | 4293 | unsigned int j; |
83b16ac6 | 4294 | char mnemonic[MAX_MNEM_SIZE], mnem_suffix; |
d3ce72d0 | 4295 | const insn_template *t; |
252b5132 | 4296 | |
47926f60 | 4297 | /* Initialize globals. */ |
252b5132 RH |
4298 | memset (&i, '\0', sizeof (i)); |
4299 | for (j = 0; j < MAX_OPERANDS; j++) | |
1ae12ab7 | 4300 | i.reloc[j] = NO_RELOC; |
252b5132 RH |
4301 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
4302 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 4303 | save_stack_p = save_stack; |
252b5132 RH |
4304 | |
4305 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
4306 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 4307 | start of a (possibly prefixed) mnemonic. */ |
252b5132 | 4308 | |
29b0f896 AM |
4309 | line = parse_insn (line, mnemonic); |
4310 | if (line == NULL) | |
4311 | return; | |
83b16ac6 | 4312 | mnem_suffix = i.suffix; |
252b5132 | 4313 | |
29b0f896 | 4314 | line = parse_operands (line, mnemonic); |
ee86248c | 4315 | this_operand = -1; |
8325cc63 JB |
4316 | xfree (i.memop1_string); |
4317 | i.memop1_string = NULL; | |
29b0f896 AM |
4318 | if (line == NULL) |
4319 | return; | |
252b5132 | 4320 | |
29b0f896 AM |
4321 | /* Now we've parsed the mnemonic into a set of templates, and have the |
4322 | operands at hand. */ | |
4323 | ||
4324 | /* All intel opcodes have reversed operands except for "bound" and | |
4325 | "enter". We also don't reverse intersegment "jmp" and "call" | |
4326 | instructions with 2 immediate operands so that the immediate segment | |
050dfa73 | 4327 | precedes the offset, as it does when in AT&T mode. */ |
4d456e3d L |
4328 | if (intel_syntax |
4329 | && i.operands > 1 | |
29b0f896 | 4330 | && (strcmp (mnemonic, "bound") != 0) |
30123838 | 4331 | && (strcmp (mnemonic, "invlpga") != 0) |
40fb9820 L |
4332 | && !(operand_type_check (i.types[0], imm) |
4333 | && operand_type_check (i.types[1], imm))) | |
29b0f896 AM |
4334 | swap_operands (); |
4335 | ||
ec56d5c0 JB |
4336 | /* The order of the immediates should be reversed |
4337 | for 2 immediates extrq and insertq instructions */ | |
4338 | if (i.imm_operands == 2 | |
4339 | && (strcmp (mnemonic, "extrq") == 0 | |
4340 | || strcmp (mnemonic, "insertq") == 0)) | |
4341 | swap_2_operands (0, 1); | |
4342 | ||
29b0f896 AM |
4343 | if (i.imm_operands) |
4344 | optimize_imm (); | |
4345 | ||
b300c311 L |
4346 | /* Don't optimize displacement for movabs since it only takes 64bit |
4347 | displacement. */ | |
4348 | if (i.disp_operands | |
a501d77e | 4349 | && i.disp_encoding != disp_encoding_32bit |
862be3fb L |
4350 | && (flag_code != CODE_64BIT |
4351 | || strcmp (mnemonic, "movabs") != 0)) | |
4352 | optimize_disp (); | |
29b0f896 AM |
4353 | |
4354 | /* Next, we find a template that matches the given insn, | |
4355 | making sure the overlap of the given operands types is consistent | |
4356 | with the template operand types. */ | |
252b5132 | 4357 | |
83b16ac6 | 4358 | if (!(t = match_template (mnem_suffix))) |
29b0f896 | 4359 | return; |
252b5132 | 4360 | |
7bab8ab5 | 4361 | if (sse_check != check_none |
81f8a913 | 4362 | && !i.tm.opcode_modifier.noavx |
6e3e5c9e | 4363 | && !i.tm.cpu_flags.bitfield.cpuavx |
569d50f1 | 4364 | && !i.tm.cpu_flags.bitfield.cpuavx512f |
daf50ae7 L |
4365 | && (i.tm.cpu_flags.bitfield.cpusse |
4366 | || i.tm.cpu_flags.bitfield.cpusse2 | |
4367 | || i.tm.cpu_flags.bitfield.cpusse3 | |
4368 | || i.tm.cpu_flags.bitfield.cpussse3 | |
4369 | || i.tm.cpu_flags.bitfield.cpusse4_1 | |
6e3e5c9e | 4370 | || i.tm.cpu_flags.bitfield.cpusse4_2 |
569d50f1 | 4371 | || i.tm.cpu_flags.bitfield.cpusse4a |
6e3e5c9e JB |
4372 | || i.tm.cpu_flags.bitfield.cpupclmul |
4373 | || i.tm.cpu_flags.bitfield.cpuaes | |
569d50f1 | 4374 | || i.tm.cpu_flags.bitfield.cpusha |
6e3e5c9e | 4375 | || i.tm.cpu_flags.bitfield.cpugfni)) |
daf50ae7 | 4376 | { |
7bab8ab5 | 4377 | (sse_check == check_warning |
daf50ae7 L |
4378 | ? as_warn |
4379 | : as_bad) (_("SSE instruction `%s' is used"), i.tm.name); | |
4380 | } | |
4381 | ||
321fd21e L |
4382 | /* Zap movzx and movsx suffix. The suffix has been set from |
4383 | "word ptr" or "byte ptr" on the source operand in Intel syntax | |
4384 | or extracted from mnemonic in AT&T syntax. But we'll use | |
4385 | the destination register to choose the suffix for encoding. */ | |
4386 | if ((i.tm.base_opcode & ~9) == 0x0fb6) | |
cd61ebfe | 4387 | { |
321fd21e L |
4388 | /* In Intel syntax, there must be a suffix. In AT&T syntax, if |
4389 | there is no suffix, the default will be byte extension. */ | |
4390 | if (i.reg_operands != 2 | |
4391 | && !i.suffix | |
7ab9ffdd | 4392 | && intel_syntax) |
321fd21e L |
4393 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); |
4394 | ||
4395 | i.suffix = 0; | |
cd61ebfe | 4396 | } |
24eab124 | 4397 | |
40fb9820 | 4398 | if (i.tm.opcode_modifier.fwait) |
29b0f896 AM |
4399 | if (!add_prefix (FWAIT_OPCODE)) |
4400 | return; | |
252b5132 | 4401 | |
d5de92cf L |
4402 | /* Check if REP prefix is OK. */ |
4403 | if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok) | |
4404 | { | |
4405 | as_bad (_("invalid instruction `%s' after `%s'"), | |
4406 | i.tm.name, i.rep_prefix); | |
4407 | return; | |
4408 | } | |
4409 | ||
c1ba0266 L |
4410 | /* Check for lock without a lockable instruction. Destination operand |
4411 | must be memory unless it is xchg (0x86). */ | |
c32fa91d L |
4412 | if (i.prefix[LOCK_PREFIX] |
4413 | && (!i.tm.opcode_modifier.islockable | |
c1ba0266 L |
4414 | || i.mem_operands == 0 |
4415 | || (i.tm.base_opcode != 0x86 | |
8dc0818e | 4416 | && !(i.flags[i.operands - 1] & Operand_Mem)))) |
c32fa91d L |
4417 | { |
4418 | as_bad (_("expecting lockable instruction after `lock'")); | |
4419 | return; | |
4420 | } | |
4421 | ||
7a8655d2 JB |
4422 | /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */ |
4423 | if (i.prefix[DATA_PREFIX] && is_any_vex_encoding (&i.tm)) | |
4424 | { | |
4425 | as_bad (_("data size prefix invalid with `%s'"), i.tm.name); | |
4426 | return; | |
4427 | } | |
4428 | ||
42164a71 | 4429 | /* Check if HLE prefix is OK. */ |
165de32a | 4430 | if (i.hle_prefix && !check_hle ()) |
42164a71 L |
4431 | return; |
4432 | ||
7e8b059b L |
4433 | /* Check BND prefix. */ |
4434 | if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok) | |
4435 | as_bad (_("expecting valid branch instruction after `bnd'")); | |
4436 | ||
04ef582a | 4437 | /* Check NOTRACK prefix. */ |
9fef80d6 L |
4438 | if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok) |
4439 | as_bad (_("expecting indirect branch instruction after `notrack'")); | |
04ef582a | 4440 | |
327e8c42 JB |
4441 | if (i.tm.cpu_flags.bitfield.cpumpx) |
4442 | { | |
4443 | if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX]) | |
4444 | as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions.")); | |
4445 | else if (flag_code != CODE_16BIT | |
4446 | ? i.prefix[ADDR_PREFIX] | |
4447 | : i.mem_operands && !i.prefix[ADDR_PREFIX]) | |
4448 | as_bad (_("16-bit address isn't allowed in MPX instructions")); | |
4449 | } | |
7e8b059b L |
4450 | |
4451 | /* Insert BND prefix. */ | |
76d3a78a JB |
4452 | if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok) |
4453 | { | |
4454 | if (!i.prefix[BND_PREFIX]) | |
4455 | add_prefix (BND_PREFIX_OPCODE); | |
4456 | else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE) | |
4457 | { | |
4458 | as_warn (_("replacing `rep'/`repe' prefix by `bnd'")); | |
4459 | i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE; | |
4460 | } | |
4461 | } | |
7e8b059b | 4462 | |
29b0f896 | 4463 | /* Check string instruction segment overrides. */ |
51c8edf6 | 4464 | if (i.tm.opcode_modifier.isstring >= IS_STRING_ES_OP0) |
29b0f896 | 4465 | { |
51c8edf6 | 4466 | gas_assert (i.mem_operands); |
29b0f896 | 4467 | if (!check_string ()) |
5dd0794d | 4468 | return; |
fc0763e6 | 4469 | i.disp_operands = 0; |
29b0f896 | 4470 | } |
5dd0794d | 4471 | |
b6f8c7c4 L |
4472 | if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize) |
4473 | optimize_encoding (); | |
4474 | ||
29b0f896 AM |
4475 | if (!process_suffix ()) |
4476 | return; | |
e413e4e9 | 4477 | |
bc0844ae L |
4478 | /* Update operand types. */ |
4479 | for (j = 0; j < i.operands; j++) | |
4480 | i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]); | |
4481 | ||
29b0f896 AM |
4482 | /* Make still unresolved immediate matches conform to size of immediate |
4483 | given in i.suffix. */ | |
4484 | if (!finalize_imm ()) | |
4485 | return; | |
252b5132 | 4486 | |
40fb9820 | 4487 | if (i.types[0].bitfield.imm1) |
29b0f896 | 4488 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 | 4489 | |
9afe6eb8 L |
4490 | /* We only need to check those implicit registers for instructions |
4491 | with 3 operands or less. */ | |
4492 | if (i.operands <= 3) | |
4493 | for (j = 0; j < i.operands; j++) | |
75e5731b JB |
4494 | if (i.types[j].bitfield.instance != InstanceNone |
4495 | && !i.types[j].bitfield.xmmword) | |
9afe6eb8 | 4496 | i.reg_operands--; |
40fb9820 | 4497 | |
c0f3af97 L |
4498 | /* ImmExt should be processed after SSE2AVX. */ |
4499 | if (!i.tm.opcode_modifier.sse2avx | |
4500 | && i.tm.opcode_modifier.immext) | |
65da13b5 | 4501 | process_immext (); |
252b5132 | 4502 | |
29b0f896 AM |
4503 | /* For insns with operands there are more diddles to do to the opcode. */ |
4504 | if (i.operands) | |
4505 | { | |
4506 | if (!process_operands ()) | |
4507 | return; | |
4508 | } | |
40fb9820 | 4509 | else if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 AM |
4510 | { |
4511 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ | |
4512 | as_warn (_("translating to `%sp'"), i.tm.name); | |
4513 | } | |
252b5132 | 4514 | |
7a8655d2 | 4515 | if (is_any_vex_encoding (&i.tm)) |
9e5e5283 | 4516 | { |
c1dc7af5 | 4517 | if (!cpu_arch_flags.bitfield.cpui286) |
9e5e5283 | 4518 | { |
c1dc7af5 | 4519 | as_bad (_("instruction `%s' isn't supported outside of protected mode."), |
9e5e5283 L |
4520 | i.tm.name); |
4521 | return; | |
4522 | } | |
c0f3af97 | 4523 | |
9e5e5283 L |
4524 | if (i.tm.opcode_modifier.vex) |
4525 | build_vex_prefix (t); | |
4526 | else | |
4527 | build_evex_prefix (); | |
4528 | } | |
43234a1e | 4529 | |
5dd85c99 SP |
4530 | /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4 |
4531 | instructions may define INT_OPCODE as well, so avoid this corner | |
4532 | case for those instructions that use MODRM. */ | |
4533 | if (i.tm.base_opcode == INT_OPCODE | |
a6461c02 SP |
4534 | && !i.tm.opcode_modifier.modrm |
4535 | && i.op[0].imms->X_add_number == 3) | |
29b0f896 AM |
4536 | { |
4537 | i.tm.base_opcode = INT3_OPCODE; | |
4538 | i.imm_operands = 0; | |
4539 | } | |
252b5132 | 4540 | |
0cfa3eb3 JB |
4541 | if ((i.tm.opcode_modifier.jump == JUMP |
4542 | || i.tm.opcode_modifier.jump == JUMP_BYTE | |
4543 | || i.tm.opcode_modifier.jump == JUMP_DWORD) | |
29b0f896 AM |
4544 | && i.op[0].disps->X_op == O_constant) |
4545 | { | |
4546 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
4547 | the absolute address given by the constant. Since ix86 jumps and | |
4548 | calls are pc relative, we need to generate a reloc. */ | |
4549 | i.op[0].disps->X_add_symbol = &abs_symbol; | |
4550 | i.op[0].disps->X_op = O_symbol; | |
4551 | } | |
252b5132 | 4552 | |
40fb9820 | 4553 | if (i.tm.opcode_modifier.rex64) |
161a04f6 | 4554 | i.rex |= REX_W; |
252b5132 | 4555 | |
29b0f896 AM |
4556 | /* For 8 bit registers we need an empty rex prefix. Also if the |
4557 | instruction already has a prefix, we need to convert old | |
4558 | registers to new ones. */ | |
773f551c | 4559 | |
bab6aec1 | 4560 | if ((i.types[0].bitfield.class == Reg && i.types[0].bitfield.byte |
29b0f896 | 4561 | && (i.op[0].regs->reg_flags & RegRex64) != 0) |
bab6aec1 | 4562 | || (i.types[1].bitfield.class == Reg && i.types[1].bitfield.byte |
29b0f896 | 4563 | && (i.op[1].regs->reg_flags & RegRex64) != 0) |
bab6aec1 JB |
4564 | || (((i.types[0].bitfield.class == Reg && i.types[0].bitfield.byte) |
4565 | || (i.types[1].bitfield.class == Reg && i.types[1].bitfield.byte)) | |
29b0f896 AM |
4566 | && i.rex != 0)) |
4567 | { | |
4568 | int x; | |
726c5dcd | 4569 | |
29b0f896 AM |
4570 | i.rex |= REX_OPCODE; |
4571 | for (x = 0; x < 2; x++) | |
4572 | { | |
4573 | /* Look for 8 bit operand that uses old registers. */ | |
bab6aec1 | 4574 | if (i.types[x].bitfield.class == Reg && i.types[x].bitfield.byte |
29b0f896 | 4575 | && (i.op[x].regs->reg_flags & RegRex64) == 0) |
773f551c | 4576 | { |
3f93af61 | 4577 | gas_assert (!(i.op[x].regs->reg_flags & RegRex)); |
29b0f896 AM |
4578 | /* In case it is "hi" register, give up. */ |
4579 | if (i.op[x].regs->reg_num > 3) | |
a540244d | 4580 | as_bad (_("can't encode register '%s%s' in an " |
4eed87de | 4581 | "instruction requiring REX prefix."), |
a540244d | 4582 | register_prefix, i.op[x].regs->reg_name); |
773f551c | 4583 | |
29b0f896 AM |
4584 | /* Otherwise it is equivalent to the extended register. |
4585 | Since the encoding doesn't change this is merely | |
4586 | cosmetic cleanup for debug output. */ | |
4587 | ||
4588 | i.op[x].regs = i.op[x].regs + 8; | |
773f551c | 4589 | } |
29b0f896 AM |
4590 | } |
4591 | } | |
773f551c | 4592 | |
6b6b6807 L |
4593 | if (i.rex == 0 && i.rex_encoding) |
4594 | { | |
4595 | /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand | |
3f93af61 | 4596 | that uses legacy register. If it is "hi" register, don't add |
6b6b6807 L |
4597 | the REX_OPCODE byte. */ |
4598 | int x; | |
4599 | for (x = 0; x < 2; x++) | |
bab6aec1 | 4600 | if (i.types[x].bitfield.class == Reg |
6b6b6807 L |
4601 | && i.types[x].bitfield.byte |
4602 | && (i.op[x].regs->reg_flags & RegRex64) == 0 | |
4603 | && i.op[x].regs->reg_num > 3) | |
4604 | { | |
3f93af61 | 4605 | gas_assert (!(i.op[x].regs->reg_flags & RegRex)); |
6b6b6807 L |
4606 | i.rex_encoding = FALSE; |
4607 | break; | |
4608 | } | |
4609 | ||
4610 | if (i.rex_encoding) | |
4611 | i.rex = REX_OPCODE; | |
4612 | } | |
4613 | ||
7ab9ffdd | 4614 | if (i.rex != 0) |
29b0f896 AM |
4615 | add_prefix (REX_OPCODE | i.rex); |
4616 | ||
4617 | /* We are ready to output the insn. */ | |
4618 | output_insn (); | |
e379e5f3 L |
4619 | |
4620 | last_insn.seg = now_seg; | |
4621 | ||
4622 | if (i.tm.opcode_modifier.isprefix) | |
4623 | { | |
4624 | last_insn.kind = last_insn_prefix; | |
4625 | last_insn.name = i.tm.name; | |
4626 | last_insn.file = as_where (&last_insn.line); | |
4627 | } | |
4628 | else | |
4629 | last_insn.kind = last_insn_other; | |
29b0f896 AM |
4630 | } |
4631 | ||
4632 | static char * | |
e3bb37b5 | 4633 | parse_insn (char *line, char *mnemonic) |
29b0f896 AM |
4634 | { |
4635 | char *l = line; | |
4636 | char *token_start = l; | |
4637 | char *mnem_p; | |
5c6af06e | 4638 | int supported; |
d3ce72d0 | 4639 | const insn_template *t; |
b6169b20 | 4640 | char *dot_p = NULL; |
29b0f896 | 4641 | |
29b0f896 AM |
4642 | while (1) |
4643 | { | |
4644 | mnem_p = mnemonic; | |
4645 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
4646 | { | |
b6169b20 L |
4647 | if (*mnem_p == '.') |
4648 | dot_p = mnem_p; | |
29b0f896 AM |
4649 | mnem_p++; |
4650 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
45288df1 | 4651 | { |
29b0f896 AM |
4652 | as_bad (_("no such instruction: `%s'"), token_start); |
4653 | return NULL; | |
4654 | } | |
4655 | l++; | |
4656 | } | |
4657 | if (!is_space_char (*l) | |
4658 | && *l != END_OF_INSN | |
e44823cf JB |
4659 | && (intel_syntax |
4660 | || (*l != PREFIX_SEPARATOR | |
4661 | && *l != ','))) | |
29b0f896 AM |
4662 | { |
4663 | as_bad (_("invalid character %s in mnemonic"), | |
4664 | output_invalid (*l)); | |
4665 | return NULL; | |
4666 | } | |
4667 | if (token_start == l) | |
4668 | { | |
e44823cf | 4669 | if (!intel_syntax && *l == PREFIX_SEPARATOR) |
29b0f896 AM |
4670 | as_bad (_("expecting prefix; got nothing")); |
4671 | else | |
4672 | as_bad (_("expecting mnemonic; got nothing")); | |
4673 | return NULL; | |
4674 | } | |
45288df1 | 4675 | |
29b0f896 | 4676 | /* Look up instruction (or prefix) via hash table. */ |
d3ce72d0 | 4677 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
47926f60 | 4678 | |
29b0f896 AM |
4679 | if (*l != END_OF_INSN |
4680 | && (!is_space_char (*l) || l[1] != END_OF_INSN) | |
4681 | && current_templates | |
40fb9820 | 4682 | && current_templates->start->opcode_modifier.isprefix) |
29b0f896 | 4683 | { |
c6fb90c8 | 4684 | if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags)) |
2dd88dca JB |
4685 | { |
4686 | as_bad ((flag_code != CODE_64BIT | |
4687 | ? _("`%s' is only supported in 64-bit mode") | |
4688 | : _("`%s' is not supported in 64-bit mode")), | |
4689 | current_templates->start->name); | |
4690 | return NULL; | |
4691 | } | |
29b0f896 AM |
4692 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
4693 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
673fe0f0 JB |
4694 | if ((current_templates->start->opcode_modifier.size == SIZE16 |
4695 | || current_templates->start->opcode_modifier.size == SIZE32) | |
29b0f896 | 4696 | && flag_code != CODE_64BIT |
673fe0f0 | 4697 | && ((current_templates->start->opcode_modifier.size == SIZE32) |
29b0f896 AM |
4698 | ^ (flag_code == CODE_16BIT))) |
4699 | { | |
4700 | as_bad (_("redundant %s prefix"), | |
4701 | current_templates->start->name); | |
4702 | return NULL; | |
45288df1 | 4703 | } |
86fa6981 | 4704 | if (current_templates->start->opcode_length == 0) |
29b0f896 | 4705 | { |
86fa6981 L |
4706 | /* Handle pseudo prefixes. */ |
4707 | switch (current_templates->start->base_opcode) | |
4708 | { | |
4709 | case 0x0: | |
4710 | /* {disp8} */ | |
4711 | i.disp_encoding = disp_encoding_8bit; | |
4712 | break; | |
4713 | case 0x1: | |
4714 | /* {disp32} */ | |
4715 | i.disp_encoding = disp_encoding_32bit; | |
4716 | break; | |
4717 | case 0x2: | |
4718 | /* {load} */ | |
4719 | i.dir_encoding = dir_encoding_load; | |
4720 | break; | |
4721 | case 0x3: | |
4722 | /* {store} */ | |
4723 | i.dir_encoding = dir_encoding_store; | |
4724 | break; | |
4725 | case 0x4: | |
4726 | /* {vex2} */ | |
4727 | i.vec_encoding = vex_encoding_vex2; | |
4728 | break; | |
4729 | case 0x5: | |
4730 | /* {vex3} */ | |
4731 | i.vec_encoding = vex_encoding_vex3; | |
4732 | break; | |
4733 | case 0x6: | |
4734 | /* {evex} */ | |
4735 | i.vec_encoding = vex_encoding_evex; | |
4736 | break; | |
6b6b6807 L |
4737 | case 0x7: |
4738 | /* {rex} */ | |
4739 | i.rex_encoding = TRUE; | |
4740 | break; | |
b6f8c7c4 L |
4741 | case 0x8: |
4742 | /* {nooptimize} */ | |
4743 | i.no_optimize = TRUE; | |
4744 | break; | |
86fa6981 L |
4745 | default: |
4746 | abort (); | |
4747 | } | |
4748 | } | |
4749 | else | |
4750 | { | |
4751 | /* Add prefix, checking for repeated prefixes. */ | |
4e9ac44a | 4752 | switch (add_prefix (current_templates->start->base_opcode)) |
86fa6981 | 4753 | { |
4e9ac44a L |
4754 | case PREFIX_EXIST: |
4755 | return NULL; | |
4756 | case PREFIX_DS: | |
d777820b | 4757 | if (current_templates->start->cpu_flags.bitfield.cpuibt) |
4e9ac44a L |
4758 | i.notrack_prefix = current_templates->start->name; |
4759 | break; | |
4760 | case PREFIX_REP: | |
4761 | if (current_templates->start->cpu_flags.bitfield.cpuhle) | |
4762 | i.hle_prefix = current_templates->start->name; | |
4763 | else if (current_templates->start->cpu_flags.bitfield.cpumpx) | |
4764 | i.bnd_prefix = current_templates->start->name; | |
4765 | else | |
4766 | i.rep_prefix = current_templates->start->name; | |
4767 | break; | |
4768 | default: | |
4769 | break; | |
86fa6981 | 4770 | } |
29b0f896 AM |
4771 | } |
4772 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
4773 | token_start = ++l; | |
4774 | } | |
4775 | else | |
4776 | break; | |
4777 | } | |
45288df1 | 4778 | |
30a55f88 | 4779 | if (!current_templates) |
b6169b20 | 4780 | { |
07d5e953 JB |
4781 | /* Deprecated functionality (new code should use pseudo-prefixes instead): |
4782 | Check if we should swap operand or force 32bit displacement in | |
f8a5c266 | 4783 | encoding. */ |
30a55f88 | 4784 | if (mnem_p - 2 == dot_p && dot_p[1] == 's') |
64c49ab3 | 4785 | i.dir_encoding = dir_encoding_swap; |
8d63c93e | 4786 | else if (mnem_p - 3 == dot_p |
a501d77e L |
4787 | && dot_p[1] == 'd' |
4788 | && dot_p[2] == '8') | |
4789 | i.disp_encoding = disp_encoding_8bit; | |
8d63c93e | 4790 | else if (mnem_p - 4 == dot_p |
f8a5c266 L |
4791 | && dot_p[1] == 'd' |
4792 | && dot_p[2] == '3' | |
4793 | && dot_p[3] == '2') | |
a501d77e | 4794 | i.disp_encoding = disp_encoding_32bit; |
30a55f88 L |
4795 | else |
4796 | goto check_suffix; | |
4797 | mnem_p = dot_p; | |
4798 | *dot_p = '\0'; | |
d3ce72d0 | 4799 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
b6169b20 L |
4800 | } |
4801 | ||
29b0f896 AM |
4802 | if (!current_templates) |
4803 | { | |
b6169b20 | 4804 | check_suffix: |
1c529385 | 4805 | if (mnem_p > mnemonic) |
29b0f896 | 4806 | { |
1c529385 LH |
4807 | /* See if we can get a match by trimming off a suffix. */ |
4808 | switch (mnem_p[-1]) | |
29b0f896 | 4809 | { |
1c529385 LH |
4810 | case WORD_MNEM_SUFFIX: |
4811 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) | |
29b0f896 AM |
4812 | i.suffix = SHORT_MNEM_SUFFIX; |
4813 | else | |
1c529385 LH |
4814 | /* Fall through. */ |
4815 | case BYTE_MNEM_SUFFIX: | |
4816 | case QWORD_MNEM_SUFFIX: | |
4817 | i.suffix = mnem_p[-1]; | |
29b0f896 | 4818 | mnem_p[-1] = '\0'; |
d3ce72d0 | 4819 | current_templates = (const templates *) hash_find (op_hash, |
1c529385 LH |
4820 | mnemonic); |
4821 | break; | |
4822 | case SHORT_MNEM_SUFFIX: | |
4823 | case LONG_MNEM_SUFFIX: | |
4824 | if (!intel_syntax) | |
4825 | { | |
4826 | i.suffix = mnem_p[-1]; | |
4827 | mnem_p[-1] = '\0'; | |
4828 | current_templates = (const templates *) hash_find (op_hash, | |
4829 | mnemonic); | |
4830 | } | |
4831 | break; | |
4832 | ||
4833 | /* Intel Syntax. */ | |
4834 | case 'd': | |
4835 | if (intel_syntax) | |
4836 | { | |
4837 | if (intel_float_operand (mnemonic) == 1) | |
4838 | i.suffix = SHORT_MNEM_SUFFIX; | |
4839 | else | |
4840 | i.suffix = LONG_MNEM_SUFFIX; | |
4841 | mnem_p[-1] = '\0'; | |
4842 | current_templates = (const templates *) hash_find (op_hash, | |
4843 | mnemonic); | |
4844 | } | |
4845 | break; | |
29b0f896 | 4846 | } |
29b0f896 | 4847 | } |
1c529385 | 4848 | |
29b0f896 AM |
4849 | if (!current_templates) |
4850 | { | |
4851 | as_bad (_("no such instruction: `%s'"), token_start); | |
4852 | return NULL; | |
4853 | } | |
4854 | } | |
252b5132 | 4855 | |
0cfa3eb3 JB |
4856 | if (current_templates->start->opcode_modifier.jump == JUMP |
4857 | || current_templates->start->opcode_modifier.jump == JUMP_BYTE) | |
29b0f896 AM |
4858 | { |
4859 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
4860 | predict taken and predict not taken respectively. | |
4861 | I'm not sure that branch hints actually do anything on loop | |
4862 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
4863 | may work in the future and it doesn't hurt to accept them | |
4864 | now. */ | |
4865 | if (l[0] == ',' && l[1] == 'p') | |
4866 | { | |
4867 | if (l[2] == 't') | |
4868 | { | |
4869 | if (!add_prefix (DS_PREFIX_OPCODE)) | |
4870 | return NULL; | |
4871 | l += 3; | |
4872 | } | |
4873 | else if (l[2] == 'n') | |
4874 | { | |
4875 | if (!add_prefix (CS_PREFIX_OPCODE)) | |
4876 | return NULL; | |
4877 | l += 3; | |
4878 | } | |
4879 | } | |
4880 | } | |
4881 | /* Any other comma loses. */ | |
4882 | if (*l == ',') | |
4883 | { | |
4884 | as_bad (_("invalid character %s in mnemonic"), | |
4885 | output_invalid (*l)); | |
4886 | return NULL; | |
4887 | } | |
252b5132 | 4888 | |
29b0f896 | 4889 | /* Check if instruction is supported on specified architecture. */ |
5c6af06e JB |
4890 | supported = 0; |
4891 | for (t = current_templates->start; t < current_templates->end; ++t) | |
4892 | { | |
c0f3af97 L |
4893 | supported |= cpu_flags_match (t); |
4894 | if (supported == CPU_FLAGS_PERFECT_MATCH) | |
548d0ee6 JB |
4895 | { |
4896 | if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT)) | |
4897 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
3629bb00 | 4898 | |
548d0ee6 JB |
4899 | return l; |
4900 | } | |
29b0f896 | 4901 | } |
3629bb00 | 4902 | |
548d0ee6 JB |
4903 | if (!(supported & CPU_FLAGS_64BIT_MATCH)) |
4904 | as_bad (flag_code == CODE_64BIT | |
4905 | ? _("`%s' is not supported in 64-bit mode") | |
4906 | : _("`%s' is only supported in 64-bit mode"), | |
4907 | current_templates->start->name); | |
4908 | else | |
4909 | as_bad (_("`%s' is not supported on `%s%s'"), | |
4910 | current_templates->start->name, | |
4911 | cpu_arch_name ? cpu_arch_name : default_arch, | |
4912 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); | |
252b5132 | 4913 | |
548d0ee6 | 4914 | return NULL; |
29b0f896 | 4915 | } |
252b5132 | 4916 | |
29b0f896 | 4917 | static char * |
e3bb37b5 | 4918 | parse_operands (char *l, const char *mnemonic) |
29b0f896 AM |
4919 | { |
4920 | char *token_start; | |
3138f287 | 4921 | |
29b0f896 AM |
4922 | /* 1 if operand is pending after ','. */ |
4923 | unsigned int expecting_operand = 0; | |
252b5132 | 4924 | |
29b0f896 AM |
4925 | /* Non-zero if operand parens not balanced. */ |
4926 | unsigned int paren_not_balanced; | |
4927 | ||
4928 | while (*l != END_OF_INSN) | |
4929 | { | |
4930 | /* Skip optional white space before operand. */ | |
4931 | if (is_space_char (*l)) | |
4932 | ++l; | |
d02603dc | 4933 | if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"') |
29b0f896 AM |
4934 | { |
4935 | as_bad (_("invalid character %s before operand %d"), | |
4936 | output_invalid (*l), | |
4937 | i.operands + 1); | |
4938 | return NULL; | |
4939 | } | |
d02603dc | 4940 | token_start = l; /* After white space. */ |
29b0f896 AM |
4941 | paren_not_balanced = 0; |
4942 | while (paren_not_balanced || *l != ',') | |
4943 | { | |
4944 | if (*l == END_OF_INSN) | |
4945 | { | |
4946 | if (paren_not_balanced) | |
4947 | { | |
4948 | if (!intel_syntax) | |
4949 | as_bad (_("unbalanced parenthesis in operand %d."), | |
4950 | i.operands + 1); | |
4951 | else | |
4952 | as_bad (_("unbalanced brackets in operand %d."), | |
4953 | i.operands + 1); | |
4954 | return NULL; | |
4955 | } | |
4956 | else | |
4957 | break; /* we are done */ | |
4958 | } | |
d02603dc | 4959 | else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"') |
29b0f896 AM |
4960 | { |
4961 | as_bad (_("invalid character %s in operand %d"), | |
4962 | output_invalid (*l), | |
4963 | i.operands + 1); | |
4964 | return NULL; | |
4965 | } | |
4966 | if (!intel_syntax) | |
4967 | { | |
4968 | if (*l == '(') | |
4969 | ++paren_not_balanced; | |
4970 | if (*l == ')') | |
4971 | --paren_not_balanced; | |
4972 | } | |
4973 | else | |
4974 | { | |
4975 | if (*l == '[') | |
4976 | ++paren_not_balanced; | |
4977 | if (*l == ']') | |
4978 | --paren_not_balanced; | |
4979 | } | |
4980 | l++; | |
4981 | } | |
4982 | if (l != token_start) | |
4983 | { /* Yes, we've read in another operand. */ | |
4984 | unsigned int operand_ok; | |
4985 | this_operand = i.operands++; | |
4986 | if (i.operands > MAX_OPERANDS) | |
4987 | { | |
4988 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
4989 | MAX_OPERANDS); | |
4990 | return NULL; | |
4991 | } | |
9d46ce34 | 4992 | i.types[this_operand].bitfield.unspecified = 1; |
29b0f896 AM |
4993 | /* Now parse operand adding info to 'i' as we go along. */ |
4994 | END_STRING_AND_SAVE (l); | |
4995 | ||
1286ab78 L |
4996 | if (i.mem_operands > 1) |
4997 | { | |
4998 | as_bad (_("too many memory references for `%s'"), | |
4999 | mnemonic); | |
5000 | return 0; | |
5001 | } | |
5002 | ||
29b0f896 AM |
5003 | if (intel_syntax) |
5004 | operand_ok = | |
5005 | i386_intel_operand (token_start, | |
5006 | intel_float_operand (mnemonic)); | |
5007 | else | |
a7619375 | 5008 | operand_ok = i386_att_operand (token_start); |
29b0f896 AM |
5009 | |
5010 | RESTORE_END_STRING (l); | |
5011 | if (!operand_ok) | |
5012 | return NULL; | |
5013 | } | |
5014 | else | |
5015 | { | |
5016 | if (expecting_operand) | |
5017 | { | |
5018 | expecting_operand_after_comma: | |
5019 | as_bad (_("expecting operand after ','; got nothing")); | |
5020 | return NULL; | |
5021 | } | |
5022 | if (*l == ',') | |
5023 | { | |
5024 | as_bad (_("expecting operand before ','; got nothing")); | |
5025 | return NULL; | |
5026 | } | |
5027 | } | |
7f3f1ea2 | 5028 | |
29b0f896 AM |
5029 | /* Now *l must be either ',' or END_OF_INSN. */ |
5030 | if (*l == ',') | |
5031 | { | |
5032 | if (*++l == END_OF_INSN) | |
5033 | { | |
5034 | /* Just skip it, if it's \n complain. */ | |
5035 | goto expecting_operand_after_comma; | |
5036 | } | |
5037 | expecting_operand = 1; | |
5038 | } | |
5039 | } | |
5040 | return l; | |
5041 | } | |
7f3f1ea2 | 5042 | |
050dfa73 | 5043 | static void |
4d456e3d | 5044 | swap_2_operands (int xchg1, int xchg2) |
050dfa73 MM |
5045 | { |
5046 | union i386_op temp_op; | |
40fb9820 | 5047 | i386_operand_type temp_type; |
c48dadc9 | 5048 | unsigned int temp_flags; |
050dfa73 | 5049 | enum bfd_reloc_code_real temp_reloc; |
4eed87de | 5050 | |
050dfa73 MM |
5051 | temp_type = i.types[xchg2]; |
5052 | i.types[xchg2] = i.types[xchg1]; | |
5053 | i.types[xchg1] = temp_type; | |
c48dadc9 JB |
5054 | |
5055 | temp_flags = i.flags[xchg2]; | |
5056 | i.flags[xchg2] = i.flags[xchg1]; | |
5057 | i.flags[xchg1] = temp_flags; | |
5058 | ||
050dfa73 MM |
5059 | temp_op = i.op[xchg2]; |
5060 | i.op[xchg2] = i.op[xchg1]; | |
5061 | i.op[xchg1] = temp_op; | |
c48dadc9 | 5062 | |
050dfa73 MM |
5063 | temp_reloc = i.reloc[xchg2]; |
5064 | i.reloc[xchg2] = i.reloc[xchg1]; | |
5065 | i.reloc[xchg1] = temp_reloc; | |
43234a1e L |
5066 | |
5067 | if (i.mask) | |
5068 | { | |
5069 | if (i.mask->operand == xchg1) | |
5070 | i.mask->operand = xchg2; | |
5071 | else if (i.mask->operand == xchg2) | |
5072 | i.mask->operand = xchg1; | |
5073 | } | |
5074 | if (i.broadcast) | |
5075 | { | |
5076 | if (i.broadcast->operand == xchg1) | |
5077 | i.broadcast->operand = xchg2; | |
5078 | else if (i.broadcast->operand == xchg2) | |
5079 | i.broadcast->operand = xchg1; | |
5080 | } | |
5081 | if (i.rounding) | |
5082 | { | |
5083 | if (i.rounding->operand == xchg1) | |
5084 | i.rounding->operand = xchg2; | |
5085 | else if (i.rounding->operand == xchg2) | |
5086 | i.rounding->operand = xchg1; | |
5087 | } | |
050dfa73 MM |
5088 | } |
5089 | ||
29b0f896 | 5090 | static void |
e3bb37b5 | 5091 | swap_operands (void) |
29b0f896 | 5092 | { |
b7c61d9a | 5093 | switch (i.operands) |
050dfa73 | 5094 | { |
c0f3af97 | 5095 | case 5: |
b7c61d9a | 5096 | case 4: |
4d456e3d | 5097 | swap_2_operands (1, i.operands - 2); |
1a0670f3 | 5098 | /* Fall through. */ |
b7c61d9a L |
5099 | case 3: |
5100 | case 2: | |
4d456e3d | 5101 | swap_2_operands (0, i.operands - 1); |
b7c61d9a L |
5102 | break; |
5103 | default: | |
5104 | abort (); | |
29b0f896 | 5105 | } |
29b0f896 AM |
5106 | |
5107 | if (i.mem_operands == 2) | |
5108 | { | |
5109 | const seg_entry *temp_seg; | |
5110 | temp_seg = i.seg[0]; | |
5111 | i.seg[0] = i.seg[1]; | |
5112 | i.seg[1] = temp_seg; | |
5113 | } | |
5114 | } | |
252b5132 | 5115 | |
29b0f896 AM |
5116 | /* Try to ensure constant immediates are represented in the smallest |
5117 | opcode possible. */ | |
5118 | static void | |
e3bb37b5 | 5119 | optimize_imm (void) |
29b0f896 AM |
5120 | { |
5121 | char guess_suffix = 0; | |
5122 | int op; | |
252b5132 | 5123 | |
29b0f896 AM |
5124 | if (i.suffix) |
5125 | guess_suffix = i.suffix; | |
5126 | else if (i.reg_operands) | |
5127 | { | |
5128 | /* Figure out a suffix from the last register operand specified. | |
75e5731b JB |
5129 | We can't do this properly yet, i.e. excluding special register |
5130 | instances, but the following works for instructions with | |
5131 | immediates. In any case, we can't set i.suffix yet. */ | |
29b0f896 | 5132 | for (op = i.operands; --op >= 0;) |
bab6aec1 JB |
5133 | if (i.types[op].bitfield.class != Reg) |
5134 | continue; | |
5135 | else if (i.types[op].bitfield.byte) | |
7ab9ffdd | 5136 | { |
40fb9820 L |
5137 | guess_suffix = BYTE_MNEM_SUFFIX; |
5138 | break; | |
5139 | } | |
bab6aec1 | 5140 | else if (i.types[op].bitfield.word) |
252b5132 | 5141 | { |
40fb9820 L |
5142 | guess_suffix = WORD_MNEM_SUFFIX; |
5143 | break; | |
5144 | } | |
bab6aec1 | 5145 | else if (i.types[op].bitfield.dword) |
40fb9820 L |
5146 | { |
5147 | guess_suffix = LONG_MNEM_SUFFIX; | |
5148 | break; | |
5149 | } | |
bab6aec1 | 5150 | else if (i.types[op].bitfield.qword) |
40fb9820 L |
5151 | { |
5152 | guess_suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 | 5153 | break; |
252b5132 | 5154 | } |
29b0f896 AM |
5155 | } |
5156 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) | |
5157 | guess_suffix = WORD_MNEM_SUFFIX; | |
5158 | ||
5159 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 5160 | if (operand_type_check (i.types[op], imm)) |
29b0f896 AM |
5161 | { |
5162 | switch (i.op[op].imms->X_op) | |
252b5132 | 5163 | { |
29b0f896 AM |
5164 | case O_constant: |
5165 | /* If a suffix is given, this operand may be shortened. */ | |
5166 | switch (guess_suffix) | |
252b5132 | 5167 | { |
29b0f896 | 5168 | case LONG_MNEM_SUFFIX: |
40fb9820 L |
5169 | i.types[op].bitfield.imm32 = 1; |
5170 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
5171 | break; |
5172 | case WORD_MNEM_SUFFIX: | |
40fb9820 L |
5173 | i.types[op].bitfield.imm16 = 1; |
5174 | i.types[op].bitfield.imm32 = 1; | |
5175 | i.types[op].bitfield.imm32s = 1; | |
5176 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
5177 | break; |
5178 | case BYTE_MNEM_SUFFIX: | |
40fb9820 L |
5179 | i.types[op].bitfield.imm8 = 1; |
5180 | i.types[op].bitfield.imm8s = 1; | |
5181 | i.types[op].bitfield.imm16 = 1; | |
5182 | i.types[op].bitfield.imm32 = 1; | |
5183 | i.types[op].bitfield.imm32s = 1; | |
5184 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 | 5185 | break; |
252b5132 | 5186 | } |
252b5132 | 5187 | |
29b0f896 AM |
5188 | /* If this operand is at most 16 bits, convert it |
5189 | to a signed 16 bit number before trying to see | |
5190 | whether it will fit in an even smaller size. | |
5191 | This allows a 16-bit operand such as $0xffe0 to | |
5192 | be recognised as within Imm8S range. */ | |
40fb9820 | 5193 | if ((i.types[op].bitfield.imm16) |
29b0f896 | 5194 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) |
252b5132 | 5195 | { |
29b0f896 AM |
5196 | i.op[op].imms->X_add_number = |
5197 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
5198 | } | |
a28def75 L |
5199 | #ifdef BFD64 |
5200 | /* Store 32-bit immediate in 64-bit for 64-bit BFD. */ | |
40fb9820 | 5201 | if ((i.types[op].bitfield.imm32) |
29b0f896 AM |
5202 | && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) |
5203 | == 0)) | |
5204 | { | |
5205 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number | |
5206 | ^ ((offsetT) 1 << 31)) | |
5207 | - ((offsetT) 1 << 31)); | |
5208 | } | |
a28def75 | 5209 | #endif |
40fb9820 | 5210 | i.types[op] |
c6fb90c8 L |
5211 | = operand_type_or (i.types[op], |
5212 | smallest_imm_type (i.op[op].imms->X_add_number)); | |
252b5132 | 5213 | |
29b0f896 AM |
5214 | /* We must avoid matching of Imm32 templates when 64bit |
5215 | only immediate is available. */ | |
5216 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
40fb9820 | 5217 | i.types[op].bitfield.imm32 = 0; |
29b0f896 | 5218 | break; |
252b5132 | 5219 | |
29b0f896 AM |
5220 | case O_absent: |
5221 | case O_register: | |
5222 | abort (); | |
5223 | ||
5224 | /* Symbols and expressions. */ | |
5225 | default: | |
9cd96992 JB |
5226 | /* Convert symbolic operand to proper sizes for matching, but don't |
5227 | prevent matching a set of insns that only supports sizes other | |
5228 | than those matching the insn suffix. */ | |
5229 | { | |
40fb9820 | 5230 | i386_operand_type mask, allowed; |
d3ce72d0 | 5231 | const insn_template *t; |
9cd96992 | 5232 | |
0dfbf9d7 L |
5233 | operand_type_set (&mask, 0); |
5234 | operand_type_set (&allowed, 0); | |
40fb9820 | 5235 | |
4eed87de AM |
5236 | for (t = current_templates->start; |
5237 | t < current_templates->end; | |
5238 | ++t) | |
bab6aec1 JB |
5239 | { |
5240 | allowed = operand_type_or (allowed, t->operand_types[op]); | |
5241 | allowed = operand_type_and (allowed, anyimm); | |
5242 | } | |
9cd96992 JB |
5243 | switch (guess_suffix) |
5244 | { | |
5245 | case QWORD_MNEM_SUFFIX: | |
40fb9820 L |
5246 | mask.bitfield.imm64 = 1; |
5247 | mask.bitfield.imm32s = 1; | |
9cd96992 JB |
5248 | break; |
5249 | case LONG_MNEM_SUFFIX: | |
40fb9820 | 5250 | mask.bitfield.imm32 = 1; |
9cd96992 JB |
5251 | break; |
5252 | case WORD_MNEM_SUFFIX: | |
40fb9820 | 5253 | mask.bitfield.imm16 = 1; |
9cd96992 JB |
5254 | break; |
5255 | case BYTE_MNEM_SUFFIX: | |
40fb9820 | 5256 | mask.bitfield.imm8 = 1; |
9cd96992 JB |
5257 | break; |
5258 | default: | |
9cd96992 JB |
5259 | break; |
5260 | } | |
c6fb90c8 | 5261 | allowed = operand_type_and (mask, allowed); |
0dfbf9d7 | 5262 | if (!operand_type_all_zero (&allowed)) |
c6fb90c8 | 5263 | i.types[op] = operand_type_and (i.types[op], mask); |
9cd96992 | 5264 | } |
29b0f896 | 5265 | break; |
252b5132 | 5266 | } |
29b0f896 AM |
5267 | } |
5268 | } | |
47926f60 | 5269 | |
29b0f896 AM |
5270 | /* Try to use the smallest displacement type too. */ |
5271 | static void | |
e3bb37b5 | 5272 | optimize_disp (void) |
29b0f896 AM |
5273 | { |
5274 | int op; | |
3e73aa7c | 5275 | |
29b0f896 | 5276 | for (op = i.operands; --op >= 0;) |
40fb9820 | 5277 | if (operand_type_check (i.types[op], disp)) |
252b5132 | 5278 | { |
b300c311 | 5279 | if (i.op[op].disps->X_op == O_constant) |
252b5132 | 5280 | { |
91d6fa6a | 5281 | offsetT op_disp = i.op[op].disps->X_add_number; |
29b0f896 | 5282 | |
40fb9820 | 5283 | if (i.types[op].bitfield.disp16 |
91d6fa6a | 5284 | && (op_disp & ~(offsetT) 0xffff) == 0) |
b300c311 L |
5285 | { |
5286 | /* If this operand is at most 16 bits, convert | |
5287 | to a signed 16 bit number and don't use 64bit | |
5288 | displacement. */ | |
91d6fa6a | 5289 | op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000); |
40fb9820 | 5290 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 5291 | } |
a28def75 L |
5292 | #ifdef BFD64 |
5293 | /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */ | |
40fb9820 | 5294 | if (i.types[op].bitfield.disp32 |
91d6fa6a | 5295 | && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0) |
b300c311 L |
5296 | { |
5297 | /* If this operand is at most 32 bits, convert | |
5298 | to a signed 32 bit number and don't use 64bit | |
5299 | displacement. */ | |
91d6fa6a NC |
5300 | op_disp &= (((offsetT) 2 << 31) - 1); |
5301 | op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
40fb9820 | 5302 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 5303 | } |
a28def75 | 5304 | #endif |
91d6fa6a | 5305 | if (!op_disp && i.types[op].bitfield.baseindex) |
b300c311 | 5306 | { |
40fb9820 L |
5307 | i.types[op].bitfield.disp8 = 0; |
5308 | i.types[op].bitfield.disp16 = 0; | |
5309 | i.types[op].bitfield.disp32 = 0; | |
5310 | i.types[op].bitfield.disp32s = 0; | |
5311 | i.types[op].bitfield.disp64 = 0; | |
b300c311 L |
5312 | i.op[op].disps = 0; |
5313 | i.disp_operands--; | |
5314 | } | |
5315 | else if (flag_code == CODE_64BIT) | |
5316 | { | |
91d6fa6a | 5317 | if (fits_in_signed_long (op_disp)) |
28a9d8f5 | 5318 | { |
40fb9820 L |
5319 | i.types[op].bitfield.disp64 = 0; |
5320 | i.types[op].bitfield.disp32s = 1; | |
28a9d8f5 | 5321 | } |
0e1147d9 | 5322 | if (i.prefix[ADDR_PREFIX] |
91d6fa6a | 5323 | && fits_in_unsigned_long (op_disp)) |
40fb9820 | 5324 | i.types[op].bitfield.disp32 = 1; |
b300c311 | 5325 | } |
40fb9820 L |
5326 | if ((i.types[op].bitfield.disp32 |
5327 | || i.types[op].bitfield.disp32s | |
5328 | || i.types[op].bitfield.disp16) | |
b5014f7a | 5329 | && fits_in_disp8 (op_disp)) |
40fb9820 | 5330 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 5331 | } |
67a4f2b7 AO |
5332 | else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
5333 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) | |
5334 | { | |
5335 | fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, | |
5336 | i.op[op].disps, 0, i.reloc[op]); | |
40fb9820 L |
5337 | i.types[op].bitfield.disp8 = 0; |
5338 | i.types[op].bitfield.disp16 = 0; | |
5339 | i.types[op].bitfield.disp32 = 0; | |
5340 | i.types[op].bitfield.disp32s = 0; | |
5341 | i.types[op].bitfield.disp64 = 0; | |
67a4f2b7 AO |
5342 | } |
5343 | else | |
b300c311 | 5344 | /* We only support 64bit displacement on constants. */ |
40fb9820 | 5345 | i.types[op].bitfield.disp64 = 0; |
252b5132 | 5346 | } |
29b0f896 AM |
5347 | } |
5348 | ||
4a1b91ea L |
5349 | /* Return 1 if there is a match in broadcast bytes between operand |
5350 | GIVEN and instruction template T. */ | |
5351 | ||
5352 | static INLINE int | |
5353 | match_broadcast_size (const insn_template *t, unsigned int given) | |
5354 | { | |
5355 | return ((t->opcode_modifier.broadcast == BYTE_BROADCAST | |
5356 | && i.types[given].bitfield.byte) | |
5357 | || (t->opcode_modifier.broadcast == WORD_BROADCAST | |
5358 | && i.types[given].bitfield.word) | |
5359 | || (t->opcode_modifier.broadcast == DWORD_BROADCAST | |
5360 | && i.types[given].bitfield.dword) | |
5361 | || (t->opcode_modifier.broadcast == QWORD_BROADCAST | |
5362 | && i.types[given].bitfield.qword)); | |
5363 | } | |
5364 | ||
6c30d220 L |
5365 | /* Check if operands are valid for the instruction. */ |
5366 | ||
5367 | static int | |
5368 | check_VecOperands (const insn_template *t) | |
5369 | { | |
43234a1e | 5370 | unsigned int op; |
e2195274 JB |
5371 | i386_cpu_flags cpu; |
5372 | static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS; | |
5373 | ||
5374 | /* Templates allowing for ZMMword as well as YMMword and/or XMMword for | |
5375 | any one operand are implicity requiring AVX512VL support if the actual | |
5376 | operand size is YMMword or XMMword. Since this function runs after | |
5377 | template matching, there's no need to check for YMMword/XMMword in | |
5378 | the template. */ | |
5379 | cpu = cpu_flags_and (t->cpu_flags, avx512); | |
5380 | if (!cpu_flags_all_zero (&cpu) | |
5381 | && !t->cpu_flags.bitfield.cpuavx512vl | |
5382 | && !cpu_arch_flags.bitfield.cpuavx512vl) | |
5383 | { | |
5384 | for (op = 0; op < t->operands; ++op) | |
5385 | { | |
5386 | if (t->operand_types[op].bitfield.zmmword | |
5387 | && (i.types[op].bitfield.ymmword | |
5388 | || i.types[op].bitfield.xmmword)) | |
5389 | { | |
5390 | i.error = unsupported; | |
5391 | return 1; | |
5392 | } | |
5393 | } | |
5394 | } | |
43234a1e | 5395 | |
6c30d220 L |
5396 | /* Without VSIB byte, we can't have a vector register for index. */ |
5397 | if (!t->opcode_modifier.vecsib | |
5398 | && i.index_reg | |
1b54b8d7 JB |
5399 | && (i.index_reg->reg_type.bitfield.xmmword |
5400 | || i.index_reg->reg_type.bitfield.ymmword | |
5401 | || i.index_reg->reg_type.bitfield.zmmword)) | |
6c30d220 L |
5402 | { |
5403 | i.error = unsupported_vector_index_register; | |
5404 | return 1; | |
5405 | } | |
5406 | ||
ad8ecc81 MZ |
5407 | /* Check if default mask is allowed. */ |
5408 | if (t->opcode_modifier.nodefmask | |
5409 | && (!i.mask || i.mask->mask->reg_num == 0)) | |
5410 | { | |
5411 | i.error = no_default_mask; | |
5412 | return 1; | |
5413 | } | |
5414 | ||
7bab8ab5 JB |
5415 | /* For VSIB byte, we need a vector register for index, and all vector |
5416 | registers must be distinct. */ | |
5417 | if (t->opcode_modifier.vecsib) | |
5418 | { | |
5419 | if (!i.index_reg | |
6c30d220 | 5420 | || !((t->opcode_modifier.vecsib == VecSIB128 |
1b54b8d7 | 5421 | && i.index_reg->reg_type.bitfield.xmmword) |
6c30d220 | 5422 | || (t->opcode_modifier.vecsib == VecSIB256 |
1b54b8d7 | 5423 | && i.index_reg->reg_type.bitfield.ymmword) |
43234a1e | 5424 | || (t->opcode_modifier.vecsib == VecSIB512 |
1b54b8d7 | 5425 | && i.index_reg->reg_type.bitfield.zmmword))) |
7bab8ab5 JB |
5426 | { |
5427 | i.error = invalid_vsib_address; | |
5428 | return 1; | |
5429 | } | |
5430 | ||
43234a1e L |
5431 | gas_assert (i.reg_operands == 2 || i.mask); |
5432 | if (i.reg_operands == 2 && !i.mask) | |
5433 | { | |
3528c362 | 5434 | gas_assert (i.types[0].bitfield.class == RegSIMD); |
1b54b8d7 JB |
5435 | gas_assert (i.types[0].bitfield.xmmword |
5436 | || i.types[0].bitfield.ymmword); | |
3528c362 | 5437 | gas_assert (i.types[2].bitfield.class == RegSIMD); |
1b54b8d7 JB |
5438 | gas_assert (i.types[2].bitfield.xmmword |
5439 | || i.types[2].bitfield.ymmword); | |
43234a1e L |
5440 | if (operand_check == check_none) |
5441 | return 0; | |
5442 | if (register_number (i.op[0].regs) | |
5443 | != register_number (i.index_reg) | |
5444 | && register_number (i.op[2].regs) | |
5445 | != register_number (i.index_reg) | |
5446 | && register_number (i.op[0].regs) | |
5447 | != register_number (i.op[2].regs)) | |
5448 | return 0; | |
5449 | if (operand_check == check_error) | |
5450 | { | |
5451 | i.error = invalid_vector_register_set; | |
5452 | return 1; | |
5453 | } | |
5454 | as_warn (_("mask, index, and destination registers should be distinct")); | |
5455 | } | |
8444f82a MZ |
5456 | else if (i.reg_operands == 1 && i.mask) |
5457 | { | |
3528c362 | 5458 | if (i.types[1].bitfield.class == RegSIMD |
1b54b8d7 JB |
5459 | && (i.types[1].bitfield.xmmword |
5460 | || i.types[1].bitfield.ymmword | |
5461 | || i.types[1].bitfield.zmmword) | |
8444f82a MZ |
5462 | && (register_number (i.op[1].regs) |
5463 | == register_number (i.index_reg))) | |
5464 | { | |
5465 | if (operand_check == check_error) | |
5466 | { | |
5467 | i.error = invalid_vector_register_set; | |
5468 | return 1; | |
5469 | } | |
5470 | if (operand_check != check_none) | |
5471 | as_warn (_("index and destination registers should be distinct")); | |
5472 | } | |
5473 | } | |
43234a1e | 5474 | } |
7bab8ab5 | 5475 | |
43234a1e L |
5476 | /* Check if broadcast is supported by the instruction and is applied |
5477 | to the memory operand. */ | |
5478 | if (i.broadcast) | |
5479 | { | |
8e6e0792 | 5480 | i386_operand_type type, overlap; |
43234a1e L |
5481 | |
5482 | /* Check if specified broadcast is supported in this instruction, | |
4a1b91ea | 5483 | and its broadcast bytes match the memory operand. */ |
32546502 | 5484 | op = i.broadcast->operand; |
8e6e0792 | 5485 | if (!t->opcode_modifier.broadcast |
c48dadc9 | 5486 | || !(i.flags[op] & Operand_Mem) |
c39e5b26 | 5487 | || (!i.types[op].bitfield.unspecified |
4a1b91ea | 5488 | && !match_broadcast_size (t, op))) |
43234a1e L |
5489 | { |
5490 | bad_broadcast: | |
5491 | i.error = unsupported_broadcast; | |
5492 | return 1; | |
5493 | } | |
8e6e0792 | 5494 | |
4a1b91ea L |
5495 | i.broadcast->bytes = ((1 << (t->opcode_modifier.broadcast - 1)) |
5496 | * i.broadcast->type); | |
8e6e0792 | 5497 | operand_type_set (&type, 0); |
4a1b91ea | 5498 | switch (i.broadcast->bytes) |
8e6e0792 | 5499 | { |
4a1b91ea L |
5500 | case 2: |
5501 | type.bitfield.word = 1; | |
5502 | break; | |
5503 | case 4: | |
5504 | type.bitfield.dword = 1; | |
5505 | break; | |
8e6e0792 JB |
5506 | case 8: |
5507 | type.bitfield.qword = 1; | |
5508 | break; | |
5509 | case 16: | |
5510 | type.bitfield.xmmword = 1; | |
5511 | break; | |
5512 | case 32: | |
5513 | type.bitfield.ymmword = 1; | |
5514 | break; | |
5515 | case 64: | |
5516 | type.bitfield.zmmword = 1; | |
5517 | break; | |
5518 | default: | |
5519 | goto bad_broadcast; | |
5520 | } | |
5521 | ||
5522 | overlap = operand_type_and (type, t->operand_types[op]); | |
5523 | if (operand_type_all_zero (&overlap)) | |
5524 | goto bad_broadcast; | |
5525 | ||
5526 | if (t->opcode_modifier.checkregsize) | |
5527 | { | |
5528 | unsigned int j; | |
5529 | ||
e2195274 | 5530 | type.bitfield.baseindex = 1; |
8e6e0792 JB |
5531 | for (j = 0; j < i.operands; ++j) |
5532 | { | |
5533 | if (j != op | |
5534 | && !operand_type_register_match(i.types[j], | |
5535 | t->operand_types[j], | |
5536 | type, | |
5537 | t->operand_types[op])) | |
5538 | goto bad_broadcast; | |
5539 | } | |
5540 | } | |
43234a1e L |
5541 | } |
5542 | /* If broadcast is supported in this instruction, we need to check if | |
5543 | operand of one-element size isn't specified without broadcast. */ | |
5544 | else if (t->opcode_modifier.broadcast && i.mem_operands) | |
5545 | { | |
5546 | /* Find memory operand. */ | |
5547 | for (op = 0; op < i.operands; op++) | |
8dc0818e | 5548 | if (i.flags[op] & Operand_Mem) |
43234a1e L |
5549 | break; |
5550 | gas_assert (op < i.operands); | |
5551 | /* Check size of the memory operand. */ | |
4a1b91ea | 5552 | if (match_broadcast_size (t, op)) |
43234a1e L |
5553 | { |
5554 | i.error = broadcast_needed; | |
5555 | return 1; | |
5556 | } | |
5557 | } | |
c39e5b26 JB |
5558 | else |
5559 | op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */ | |
43234a1e L |
5560 | |
5561 | /* Check if requested masking is supported. */ | |
ae2387fe | 5562 | if (i.mask) |
43234a1e | 5563 | { |
ae2387fe JB |
5564 | switch (t->opcode_modifier.masking) |
5565 | { | |
5566 | case BOTH_MASKING: | |
5567 | break; | |
5568 | case MERGING_MASKING: | |
5569 | if (i.mask->zeroing) | |
5570 | { | |
5571 | case 0: | |
5572 | i.error = unsupported_masking; | |
5573 | return 1; | |
5574 | } | |
5575 | break; | |
5576 | case DYNAMIC_MASKING: | |
5577 | /* Memory destinations allow only merging masking. */ | |
5578 | if (i.mask->zeroing && i.mem_operands) | |
5579 | { | |
5580 | /* Find memory operand. */ | |
5581 | for (op = 0; op < i.operands; op++) | |
c48dadc9 | 5582 | if (i.flags[op] & Operand_Mem) |
ae2387fe JB |
5583 | break; |
5584 | gas_assert (op < i.operands); | |
5585 | if (op == i.operands - 1) | |
5586 | { | |
5587 | i.error = unsupported_masking; | |
5588 | return 1; | |
5589 | } | |
5590 | } | |
5591 | break; | |
5592 | default: | |
5593 | abort (); | |
5594 | } | |
43234a1e L |
5595 | } |
5596 | ||
5597 | /* Check if masking is applied to dest operand. */ | |
5598 | if (i.mask && (i.mask->operand != (int) (i.operands - 1))) | |
5599 | { | |
5600 | i.error = mask_not_on_destination; | |
5601 | return 1; | |
5602 | } | |
5603 | ||
43234a1e L |
5604 | /* Check RC/SAE. */ |
5605 | if (i.rounding) | |
5606 | { | |
a80195f1 JB |
5607 | if (!t->opcode_modifier.sae |
5608 | || (i.rounding->type != saeonly && !t->opcode_modifier.staticrounding)) | |
43234a1e L |
5609 | { |
5610 | i.error = unsupported_rc_sae; | |
5611 | return 1; | |
5612 | } | |
5613 | /* If the instruction has several immediate operands and one of | |
5614 | them is rounding, the rounding operand should be the last | |
5615 | immediate operand. */ | |
5616 | if (i.imm_operands > 1 | |
5617 | && i.rounding->operand != (int) (i.imm_operands - 1)) | |
7bab8ab5 | 5618 | { |
43234a1e | 5619 | i.error = rc_sae_operand_not_last_imm; |
7bab8ab5 JB |
5620 | return 1; |
5621 | } | |
6c30d220 L |
5622 | } |
5623 | ||
43234a1e | 5624 | /* Check vector Disp8 operand. */ |
b5014f7a JB |
5625 | if (t->opcode_modifier.disp8memshift |
5626 | && i.disp_encoding != disp_encoding_32bit) | |
43234a1e L |
5627 | { |
5628 | if (i.broadcast) | |
4a1b91ea | 5629 | i.memshift = t->opcode_modifier.broadcast - 1; |
7091c612 | 5630 | else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL) |
43234a1e | 5631 | i.memshift = t->opcode_modifier.disp8memshift; |
7091c612 JB |
5632 | else |
5633 | { | |
5634 | const i386_operand_type *type = NULL; | |
5635 | ||
5636 | i.memshift = 0; | |
5637 | for (op = 0; op < i.operands; op++) | |
8dc0818e | 5638 | if (i.flags[op] & Operand_Mem) |
7091c612 | 5639 | { |
4174bfff JB |
5640 | if (t->opcode_modifier.evex == EVEXLIG) |
5641 | i.memshift = 2 + (i.suffix == QWORD_MNEM_SUFFIX); | |
5642 | else if (t->operand_types[op].bitfield.xmmword | |
5643 | + t->operand_types[op].bitfield.ymmword | |
5644 | + t->operand_types[op].bitfield.zmmword <= 1) | |
7091c612 JB |
5645 | type = &t->operand_types[op]; |
5646 | else if (!i.types[op].bitfield.unspecified) | |
5647 | type = &i.types[op]; | |
5648 | } | |
3528c362 | 5649 | else if (i.types[op].bitfield.class == RegSIMD |
4174bfff | 5650 | && t->opcode_modifier.evex != EVEXLIG) |
7091c612 JB |
5651 | { |
5652 | if (i.types[op].bitfield.zmmword) | |
5653 | i.memshift = 6; | |
5654 | else if (i.types[op].bitfield.ymmword && i.memshift < 5) | |
5655 | i.memshift = 5; | |
5656 | else if (i.types[op].bitfield.xmmword && i.memshift < 4) | |
5657 | i.memshift = 4; | |
5658 | } | |
5659 | ||
5660 | if (type) | |
5661 | { | |
5662 | if (type->bitfield.zmmword) | |
5663 | i.memshift = 6; | |
5664 | else if (type->bitfield.ymmword) | |
5665 | i.memshift = 5; | |
5666 | else if (type->bitfield.xmmword) | |
5667 | i.memshift = 4; | |
5668 | } | |
5669 | ||
5670 | /* For the check in fits_in_disp8(). */ | |
5671 | if (i.memshift == 0) | |
5672 | i.memshift = -1; | |
5673 | } | |
43234a1e L |
5674 | |
5675 | for (op = 0; op < i.operands; op++) | |
5676 | if (operand_type_check (i.types[op], disp) | |
5677 | && i.op[op].disps->X_op == O_constant) | |
5678 | { | |
b5014f7a | 5679 | if (fits_in_disp8 (i.op[op].disps->X_add_number)) |
43234a1e | 5680 | { |
b5014f7a JB |
5681 | i.types[op].bitfield.disp8 = 1; |
5682 | return 0; | |
43234a1e | 5683 | } |
b5014f7a | 5684 | i.types[op].bitfield.disp8 = 0; |
43234a1e L |
5685 | } |
5686 | } | |
b5014f7a JB |
5687 | |
5688 | i.memshift = 0; | |
43234a1e | 5689 | |
6c30d220 L |
5690 | return 0; |
5691 | } | |
5692 | ||
43f3e2ee | 5693 | /* Check if operands are valid for the instruction. Update VEX |
a683cc34 SP |
5694 | operand types. */ |
5695 | ||
5696 | static int | |
5697 | VEX_check_operands (const insn_template *t) | |
5698 | { | |
86fa6981 | 5699 | if (i.vec_encoding == vex_encoding_evex) |
43234a1e | 5700 | { |
86fa6981 | 5701 | /* This instruction must be encoded with EVEX prefix. */ |
e771e7c9 | 5702 | if (!is_evex_encoding (t)) |
86fa6981 L |
5703 | { |
5704 | i.error = unsupported; | |
5705 | return 1; | |
5706 | } | |
5707 | return 0; | |
43234a1e L |
5708 | } |
5709 | ||
a683cc34 | 5710 | if (!t->opcode_modifier.vex) |
86fa6981 L |
5711 | { |
5712 | /* This instruction template doesn't have VEX prefix. */ | |
5713 | if (i.vec_encoding != vex_encoding_default) | |
5714 | { | |
5715 | i.error = unsupported; | |
5716 | return 1; | |
5717 | } | |
5718 | return 0; | |
5719 | } | |
a683cc34 | 5720 | |
9d3bf266 JB |
5721 | /* Check the special Imm4 cases; must be the first operand. */ |
5722 | if (t->cpu_flags.bitfield.cpuxop && t->operands == 5) | |
a683cc34 SP |
5723 | { |
5724 | if (i.op[0].imms->X_op != O_constant | |
5725 | || !fits_in_imm4 (i.op[0].imms->X_add_number)) | |
891edac4 | 5726 | { |
a65babc9 | 5727 | i.error = bad_imm4; |
891edac4 L |
5728 | return 1; |
5729 | } | |
a683cc34 | 5730 | |
9d3bf266 JB |
5731 | /* Turn off Imm<N> so that update_imm won't complain. */ |
5732 | operand_type_set (&i.types[0], 0); | |
a683cc34 SP |
5733 | } |
5734 | ||
5735 | return 0; | |
5736 | } | |
5737 | ||
d3ce72d0 | 5738 | static const insn_template * |
83b16ac6 | 5739 | match_template (char mnem_suffix) |
29b0f896 AM |
5740 | { |
5741 | /* Points to template once we've found it. */ | |
d3ce72d0 | 5742 | const insn_template *t; |
40fb9820 | 5743 | i386_operand_type overlap0, overlap1, overlap2, overlap3; |
c0f3af97 | 5744 | i386_operand_type overlap4; |
29b0f896 | 5745 | unsigned int found_reverse_match; |
dc2be329 | 5746 | i386_opcode_modifier suffix_check; |
40fb9820 | 5747 | i386_operand_type operand_types [MAX_OPERANDS]; |
539e75ad | 5748 | int addr_prefix_disp; |
a5c311ca | 5749 | unsigned int j; |
3ac21baa | 5750 | unsigned int found_cpu_match, size_match; |
45664ddb | 5751 | unsigned int check_register; |
5614d22c | 5752 | enum i386_error specific_error = 0; |
29b0f896 | 5753 | |
c0f3af97 L |
5754 | #if MAX_OPERANDS != 5 |
5755 | # error "MAX_OPERANDS must be 5." | |
f48ff2ae L |
5756 | #endif |
5757 | ||
29b0f896 | 5758 | found_reverse_match = 0; |
539e75ad | 5759 | addr_prefix_disp = -1; |
40fb9820 | 5760 | |
dc2be329 | 5761 | /* Prepare for mnemonic suffix check. */ |
40fb9820 | 5762 | memset (&suffix_check, 0, sizeof (suffix_check)); |
dc2be329 L |
5763 | switch (mnem_suffix) |
5764 | { | |
5765 | case BYTE_MNEM_SUFFIX: | |
5766 | suffix_check.no_bsuf = 1; | |
5767 | break; | |
5768 | case WORD_MNEM_SUFFIX: | |
5769 | suffix_check.no_wsuf = 1; | |
5770 | break; | |
5771 | case SHORT_MNEM_SUFFIX: | |
5772 | suffix_check.no_ssuf = 1; | |
5773 | break; | |
5774 | case LONG_MNEM_SUFFIX: | |
5775 | suffix_check.no_lsuf = 1; | |
5776 | break; | |
5777 | case QWORD_MNEM_SUFFIX: | |
5778 | suffix_check.no_qsuf = 1; | |
5779 | break; | |
5780 | default: | |
5781 | /* NB: In Intel syntax, normally we can check for memory operand | |
5782 | size when there is no mnemonic suffix. But jmp and call have | |
5783 | 2 different encodings with Dword memory operand size, one with | |
5784 | No_ldSuf and the other without. i.suffix is set to | |
5785 | LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */ | |
5786 | if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX) | |
5787 | suffix_check.no_ldsuf = 1; | |
83b16ac6 JB |
5788 | } |
5789 | ||
01559ecc L |
5790 | /* Must have right number of operands. */ |
5791 | i.error = number_of_operands_mismatch; | |
5792 | ||
45aa61fe | 5793 | for (t = current_templates->start; t < current_templates->end; t++) |
29b0f896 | 5794 | { |
539e75ad | 5795 | addr_prefix_disp = -1; |
dbbc8b7e | 5796 | found_reverse_match = 0; |
539e75ad | 5797 | |
29b0f896 AM |
5798 | if (i.operands != t->operands) |
5799 | continue; | |
5800 | ||
50aecf8c | 5801 | /* Check processor support. */ |
a65babc9 | 5802 | i.error = unsupported; |
c0f3af97 L |
5803 | found_cpu_match = (cpu_flags_match (t) |
5804 | == CPU_FLAGS_PERFECT_MATCH); | |
50aecf8c L |
5805 | if (!found_cpu_match) |
5806 | continue; | |
5807 | ||
e1d4d893 | 5808 | /* Check AT&T mnemonic. */ |
a65babc9 | 5809 | i.error = unsupported_with_intel_mnemonic; |
e1d4d893 | 5810 | if (intel_mnemonic && t->opcode_modifier.attmnemonic) |
1efbbeb4 L |
5811 | continue; |
5812 | ||
e92bae62 | 5813 | /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */ |
a65babc9 | 5814 | i.error = unsupported_syntax; |
5c07affc | 5815 | if ((intel_syntax && t->opcode_modifier.attsyntax) |
e92bae62 L |
5816 | || (!intel_syntax && t->opcode_modifier.intelsyntax) |
5817 | || (intel64 && t->opcode_modifier.amd64) | |
5818 | || (!intel64 && t->opcode_modifier.intel64)) | |
1efbbeb4 L |
5819 | continue; |
5820 | ||
dc2be329 | 5821 | /* Check the suffix. */ |
a65babc9 | 5822 | i.error = invalid_instruction_suffix; |
dc2be329 L |
5823 | if ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf) |
5824 | || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf) | |
5825 | || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf) | |
5826 | || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf) | |
5827 | || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf) | |
5828 | || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)) | |
83b16ac6 | 5829 | continue; |
29b0f896 | 5830 | |
3ac21baa JB |
5831 | size_match = operand_size_match (t); |
5832 | if (!size_match) | |
7d5e4556 | 5833 | continue; |
539e75ad | 5834 | |
6f2f06be JB |
5835 | /* This is intentionally not |
5836 | ||
0cfa3eb3 | 5837 | if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE)) |
6f2f06be JB |
5838 | |
5839 | as the case of a missing * on the operand is accepted (perhaps with | |
5840 | a warning, issued further down). */ | |
0cfa3eb3 | 5841 | if (i.jumpabsolute && t->opcode_modifier.jump != JUMP_ABSOLUTE) |
6f2f06be JB |
5842 | { |
5843 | i.error = operand_type_mismatch; | |
5844 | continue; | |
5845 | } | |
5846 | ||
5c07affc L |
5847 | for (j = 0; j < MAX_OPERANDS; j++) |
5848 | operand_types[j] = t->operand_types[j]; | |
5849 | ||
45aa61fe AM |
5850 | /* In general, don't allow 64-bit operands in 32-bit mode. */ |
5851 | if (i.suffix == QWORD_MNEM_SUFFIX | |
5852 | && flag_code != CODE_64BIT | |
5853 | && (intel_syntax | |
40fb9820 | 5854 | ? (!t->opcode_modifier.ignoresize |
625cbd7a | 5855 | && !t->opcode_modifier.broadcast |
45aa61fe AM |
5856 | && !intel_float_operand (t->name)) |
5857 | : intel_float_operand (t->name) != 2) | |
3528c362 JB |
5858 | && ((operand_types[0].bitfield.class != RegMMX |
5859 | && operand_types[0].bitfield.class != RegSIMD) | |
5860 | || (operand_types[t->operands > 1].bitfield.class != RegMMX | |
5861 | && operand_types[t->operands > 1].bitfield.class != RegSIMD)) | |
45aa61fe AM |
5862 | && (t->base_opcode != 0x0fc7 |
5863 | || t->extension_opcode != 1 /* cmpxchg8b */)) | |
5864 | continue; | |
5865 | ||
192dc9c6 JB |
5866 | /* In general, don't allow 32-bit operands on pre-386. */ |
5867 | else if (i.suffix == LONG_MNEM_SUFFIX | |
5868 | && !cpu_arch_flags.bitfield.cpui386 | |
5869 | && (intel_syntax | |
5870 | ? (!t->opcode_modifier.ignoresize | |
5871 | && !intel_float_operand (t->name)) | |
5872 | : intel_float_operand (t->name) != 2) | |
3528c362 JB |
5873 | && ((operand_types[0].bitfield.class != RegMMX |
5874 | && operand_types[0].bitfield.class != RegSIMD) | |
5875 | || (operand_types[t->operands > 1].bitfield.class != RegMMX | |
5876 | && operand_types[t->operands > 1].bitfield.class | |
5877 | != RegSIMD))) | |
192dc9c6 JB |
5878 | continue; |
5879 | ||
29b0f896 | 5880 | /* Do not verify operands when there are none. */ |
50aecf8c | 5881 | else |
29b0f896 | 5882 | { |
c6fb90c8 | 5883 | if (!t->operands) |
2dbab7d5 L |
5884 | /* We've found a match; break out of loop. */ |
5885 | break; | |
29b0f896 | 5886 | } |
252b5132 | 5887 | |
48bcea9f JB |
5888 | if (!t->opcode_modifier.jump |
5889 | || t->opcode_modifier.jump == JUMP_ABSOLUTE) | |
5890 | { | |
5891 | /* There should be only one Disp operand. */ | |
5892 | for (j = 0; j < MAX_OPERANDS; j++) | |
5893 | if (operand_type_check (operand_types[j], disp)) | |
539e75ad | 5894 | break; |
48bcea9f JB |
5895 | if (j < MAX_OPERANDS) |
5896 | { | |
5897 | bfd_boolean override = (i.prefix[ADDR_PREFIX] != 0); | |
5898 | ||
5899 | addr_prefix_disp = j; | |
5900 | ||
5901 | /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16 | |
5902 | operand into Disp32/Disp32/Disp16/Disp32 operand. */ | |
5903 | switch (flag_code) | |
40fb9820 | 5904 | { |
48bcea9f JB |
5905 | case CODE_16BIT: |
5906 | override = !override; | |
5907 | /* Fall through. */ | |
5908 | case CODE_32BIT: | |
5909 | if (operand_types[j].bitfield.disp32 | |
5910 | && operand_types[j].bitfield.disp16) | |
40fb9820 | 5911 | { |
48bcea9f JB |
5912 | operand_types[j].bitfield.disp16 = override; |
5913 | operand_types[j].bitfield.disp32 = !override; | |
40fb9820 | 5914 | } |
48bcea9f JB |
5915 | operand_types[j].bitfield.disp32s = 0; |
5916 | operand_types[j].bitfield.disp64 = 0; | |
5917 | break; | |
5918 | ||
5919 | case CODE_64BIT: | |
5920 | if (operand_types[j].bitfield.disp32s | |
5921 | || operand_types[j].bitfield.disp64) | |
40fb9820 | 5922 | { |
48bcea9f JB |
5923 | operand_types[j].bitfield.disp64 &= !override; |
5924 | operand_types[j].bitfield.disp32s &= !override; | |
5925 | operand_types[j].bitfield.disp32 = override; | |
40fb9820 | 5926 | } |
48bcea9f JB |
5927 | operand_types[j].bitfield.disp16 = 0; |
5928 | break; | |
40fb9820 | 5929 | } |
539e75ad | 5930 | } |
48bcea9f | 5931 | } |
539e75ad | 5932 | |
02a86693 L |
5933 | /* Force 0x8b encoding for "mov foo@GOT, %eax". */ |
5934 | if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0) | |
5935 | continue; | |
5936 | ||
56ffb741 | 5937 | /* We check register size if needed. */ |
e2195274 JB |
5938 | if (t->opcode_modifier.checkregsize) |
5939 | { | |
5940 | check_register = (1 << t->operands) - 1; | |
5941 | if (i.broadcast) | |
5942 | check_register &= ~(1 << i.broadcast->operand); | |
5943 | } | |
5944 | else | |
5945 | check_register = 0; | |
5946 | ||
c6fb90c8 | 5947 | overlap0 = operand_type_and (i.types[0], operand_types[0]); |
29b0f896 AM |
5948 | switch (t->operands) |
5949 | { | |
5950 | case 1: | |
40fb9820 | 5951 | if (!operand_type_match (overlap0, i.types[0])) |
29b0f896 AM |
5952 | continue; |
5953 | break; | |
5954 | case 2: | |
33eaf5de | 5955 | /* xchg %eax, %eax is a special case. It is an alias for nop |
8b38ad71 L |
5956 | only in 32bit mode and we can use opcode 0x90. In 64bit |
5957 | mode, we can't use 0x90 for xchg %eax, %eax since it should | |
5958 | zero-extend %eax to %rax. */ | |
5959 | if (flag_code == CODE_64BIT | |
5960 | && t->base_opcode == 0x90 | |
75e5731b JB |
5961 | && i.types[0].bitfield.instance == Accum |
5962 | && i.types[0].bitfield.dword | |
5963 | && i.types[1].bitfield.instance == Accum | |
5964 | && i.types[1].bitfield.dword) | |
8b38ad71 | 5965 | continue; |
1212781b JB |
5966 | /* xrelease mov %eax, <disp> is another special case. It must not |
5967 | match the accumulator-only encoding of mov. */ | |
5968 | if (flag_code != CODE_64BIT | |
5969 | && i.hle_prefix | |
5970 | && t->base_opcode == 0xa0 | |
75e5731b | 5971 | && i.types[0].bitfield.instance == Accum |
8dc0818e | 5972 | && (i.flags[1] & Operand_Mem)) |
1212781b | 5973 | continue; |
f5eb1d70 JB |
5974 | /* Fall through. */ |
5975 | ||
5976 | case 3: | |
3ac21baa JB |
5977 | if (!(size_match & MATCH_STRAIGHT)) |
5978 | goto check_reverse; | |
64c49ab3 JB |
5979 | /* Reverse direction of operands if swapping is possible in the first |
5980 | place (operands need to be symmetric) and | |
5981 | - the load form is requested, and the template is a store form, | |
5982 | - the store form is requested, and the template is a load form, | |
5983 | - the non-default (swapped) form is requested. */ | |
5984 | overlap1 = operand_type_and (operand_types[0], operand_types[1]); | |
f5eb1d70 | 5985 | if (t->opcode_modifier.d && i.reg_operands == i.operands |
64c49ab3 JB |
5986 | && !operand_type_all_zero (&overlap1)) |
5987 | switch (i.dir_encoding) | |
5988 | { | |
5989 | case dir_encoding_load: | |
5990 | if (operand_type_check (operand_types[i.operands - 1], anymem) | |
dfd69174 | 5991 | || t->opcode_modifier.regmem) |
64c49ab3 JB |
5992 | goto check_reverse; |
5993 | break; | |
5994 | ||
5995 | case dir_encoding_store: | |
5996 | if (!operand_type_check (operand_types[i.operands - 1], anymem) | |
dfd69174 | 5997 | && !t->opcode_modifier.regmem) |
64c49ab3 JB |
5998 | goto check_reverse; |
5999 | break; | |
6000 | ||
6001 | case dir_encoding_swap: | |
6002 | goto check_reverse; | |
6003 | ||
6004 | case dir_encoding_default: | |
6005 | break; | |
6006 | } | |
86fa6981 | 6007 | /* If we want store form, we skip the current load. */ |
64c49ab3 JB |
6008 | if ((i.dir_encoding == dir_encoding_store |
6009 | || i.dir_encoding == dir_encoding_swap) | |
86fa6981 L |
6010 | && i.mem_operands == 0 |
6011 | && t->opcode_modifier.load) | |
fa99fab2 | 6012 | continue; |
1a0670f3 | 6013 | /* Fall through. */ |
f48ff2ae | 6014 | case 4: |
c0f3af97 | 6015 | case 5: |
c6fb90c8 | 6016 | overlap1 = operand_type_and (i.types[1], operand_types[1]); |
40fb9820 L |
6017 | if (!operand_type_match (overlap0, i.types[0]) |
6018 | || !operand_type_match (overlap1, i.types[1]) | |
e2195274 | 6019 | || ((check_register & 3) == 3 |
dc821c5f | 6020 | && !operand_type_register_match (i.types[0], |
40fb9820 | 6021 | operand_types[0], |
dc821c5f | 6022 | i.types[1], |
40fb9820 | 6023 | operand_types[1]))) |
29b0f896 AM |
6024 | { |
6025 | /* Check if other direction is valid ... */ | |
38e314eb | 6026 | if (!t->opcode_modifier.d) |
29b0f896 AM |
6027 | continue; |
6028 | ||
b6169b20 | 6029 | check_reverse: |
3ac21baa JB |
6030 | if (!(size_match & MATCH_REVERSE)) |
6031 | continue; | |
29b0f896 | 6032 | /* Try reversing direction of operands. */ |
f5eb1d70 JB |
6033 | overlap0 = operand_type_and (i.types[0], operand_types[i.operands - 1]); |
6034 | overlap1 = operand_type_and (i.types[i.operands - 1], operand_types[0]); | |
40fb9820 | 6035 | if (!operand_type_match (overlap0, i.types[0]) |
f5eb1d70 | 6036 | || !operand_type_match (overlap1, i.types[i.operands - 1]) |
45664ddb | 6037 | || (check_register |
dc821c5f | 6038 | && !operand_type_register_match (i.types[0], |
f5eb1d70 JB |
6039 | operand_types[i.operands - 1], |
6040 | i.types[i.operands - 1], | |
45664ddb | 6041 | operand_types[0]))) |
29b0f896 AM |
6042 | { |
6043 | /* Does not match either direction. */ | |
6044 | continue; | |
6045 | } | |
38e314eb | 6046 | /* found_reverse_match holds which of D or FloatR |
29b0f896 | 6047 | we've found. */ |
38e314eb JB |
6048 | if (!t->opcode_modifier.d) |
6049 | found_reverse_match = 0; | |
6050 | else if (operand_types[0].bitfield.tbyte) | |
8a2ed489 | 6051 | found_reverse_match = Opcode_FloatD; |
dbbc8b7e | 6052 | else if (operand_types[0].bitfield.xmmword |
f5eb1d70 | 6053 | || operand_types[i.operands - 1].bitfield.xmmword |
3528c362 JB |
6054 | || operand_types[0].bitfield.class == RegMMX |
6055 | || operand_types[i.operands - 1].bitfield.class == RegMMX | |
dbbc8b7e JB |
6056 | || is_any_vex_encoding(t)) |
6057 | found_reverse_match = (t->base_opcode & 0xee) != 0x6e | |
6058 | ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD; | |
8a2ed489 | 6059 | else |
38e314eb | 6060 | found_reverse_match = Opcode_D; |
40fb9820 | 6061 | if (t->opcode_modifier.floatr) |
8a2ed489 | 6062 | found_reverse_match |= Opcode_FloatR; |
29b0f896 | 6063 | } |
f48ff2ae | 6064 | else |
29b0f896 | 6065 | { |
f48ff2ae | 6066 | /* Found a forward 2 operand match here. */ |
d1cbb4db L |
6067 | switch (t->operands) |
6068 | { | |
c0f3af97 L |
6069 | case 5: |
6070 | overlap4 = operand_type_and (i.types[4], | |
6071 | operand_types[4]); | |
1a0670f3 | 6072 | /* Fall through. */ |
d1cbb4db | 6073 | case 4: |
c6fb90c8 L |
6074 | overlap3 = operand_type_and (i.types[3], |
6075 | operand_types[3]); | |
1a0670f3 | 6076 | /* Fall through. */ |
d1cbb4db | 6077 | case 3: |
c6fb90c8 L |
6078 | overlap2 = operand_type_and (i.types[2], |
6079 | operand_types[2]); | |
d1cbb4db L |
6080 | break; |
6081 | } | |
29b0f896 | 6082 | |
f48ff2ae L |
6083 | switch (t->operands) |
6084 | { | |
c0f3af97 L |
6085 | case 5: |
6086 | if (!operand_type_match (overlap4, i.types[4]) | |
dc821c5f | 6087 | || !operand_type_register_match (i.types[3], |
c0f3af97 | 6088 | operand_types[3], |
c0f3af97 L |
6089 | i.types[4], |
6090 | operand_types[4])) | |
6091 | continue; | |
1a0670f3 | 6092 | /* Fall through. */ |
f48ff2ae | 6093 | case 4: |
40fb9820 | 6094 | if (!operand_type_match (overlap3, i.types[3]) |
e2195274 JB |
6095 | || ((check_register & 0xa) == 0xa |
6096 | && !operand_type_register_match (i.types[1], | |
f7768225 JB |
6097 | operand_types[1], |
6098 | i.types[3], | |
e2195274 JB |
6099 | operand_types[3])) |
6100 | || ((check_register & 0xc) == 0xc | |
6101 | && !operand_type_register_match (i.types[2], | |
6102 | operand_types[2], | |
6103 | i.types[3], | |
6104 | operand_types[3]))) | |
f48ff2ae | 6105 | continue; |
1a0670f3 | 6106 | /* Fall through. */ |
f48ff2ae L |
6107 | case 3: |
6108 | /* Here we make use of the fact that there are no | |
23e42951 | 6109 | reverse match 3 operand instructions. */ |
40fb9820 | 6110 | if (!operand_type_match (overlap2, i.types[2]) |
e2195274 JB |
6111 | || ((check_register & 5) == 5 |
6112 | && !operand_type_register_match (i.types[0], | |
23e42951 JB |
6113 | operand_types[0], |
6114 | i.types[2], | |
e2195274 JB |
6115 | operand_types[2])) |
6116 | || ((check_register & 6) == 6 | |
6117 | && !operand_type_register_match (i.types[1], | |
6118 | operand_types[1], | |
6119 | i.types[2], | |
6120 | operand_types[2]))) | |
f48ff2ae L |
6121 | continue; |
6122 | break; | |
6123 | } | |
29b0f896 | 6124 | } |
f48ff2ae | 6125 | /* Found either forward/reverse 2, 3 or 4 operand match here: |
29b0f896 AM |
6126 | slip through to break. */ |
6127 | } | |
3629bb00 | 6128 | if (!found_cpu_match) |
dbbc8b7e | 6129 | continue; |
c0f3af97 | 6130 | |
5614d22c JB |
6131 | /* Check if vector and VEX operands are valid. */ |
6132 | if (check_VecOperands (t) || VEX_check_operands (t)) | |
6133 | { | |
6134 | specific_error = i.error; | |
6135 | continue; | |
6136 | } | |
a683cc34 | 6137 | |
29b0f896 AM |
6138 | /* We've found a match; break out of loop. */ |
6139 | break; | |
6140 | } | |
6141 | ||
6142 | if (t == current_templates->end) | |
6143 | { | |
6144 | /* We found no match. */ | |
a65babc9 | 6145 | const char *err_msg; |
5614d22c | 6146 | switch (specific_error ? specific_error : i.error) |
a65babc9 L |
6147 | { |
6148 | default: | |
6149 | abort (); | |
86e026a4 | 6150 | case operand_size_mismatch: |
a65babc9 L |
6151 | err_msg = _("operand size mismatch"); |
6152 | break; | |
6153 | case operand_type_mismatch: | |
6154 | err_msg = _("operand type mismatch"); | |
6155 | break; | |
6156 | case register_type_mismatch: | |
6157 | err_msg = _("register type mismatch"); | |
6158 | break; | |
6159 | case number_of_operands_mismatch: | |
6160 | err_msg = _("number of operands mismatch"); | |
6161 | break; | |
6162 | case invalid_instruction_suffix: | |
6163 | err_msg = _("invalid instruction suffix"); | |
6164 | break; | |
6165 | case bad_imm4: | |
4a2608e3 | 6166 | err_msg = _("constant doesn't fit in 4 bits"); |
a65babc9 | 6167 | break; |
a65babc9 L |
6168 | case unsupported_with_intel_mnemonic: |
6169 | err_msg = _("unsupported with Intel mnemonic"); | |
6170 | break; | |
6171 | case unsupported_syntax: | |
6172 | err_msg = _("unsupported syntax"); | |
6173 | break; | |
6174 | case unsupported: | |
35262a23 | 6175 | as_bad (_("unsupported instruction `%s'"), |
10efe3f6 L |
6176 | current_templates->start->name); |
6177 | return NULL; | |
6c30d220 L |
6178 | case invalid_vsib_address: |
6179 | err_msg = _("invalid VSIB address"); | |
6180 | break; | |
7bab8ab5 JB |
6181 | case invalid_vector_register_set: |
6182 | err_msg = _("mask, index, and destination registers must be distinct"); | |
6183 | break; | |
6c30d220 L |
6184 | case unsupported_vector_index_register: |
6185 | err_msg = _("unsupported vector index register"); | |
6186 | break; | |
43234a1e L |
6187 | case unsupported_broadcast: |
6188 | err_msg = _("unsupported broadcast"); | |
6189 | break; | |
43234a1e L |
6190 | case broadcast_needed: |
6191 | err_msg = _("broadcast is needed for operand of such type"); | |
6192 | break; | |
6193 | case unsupported_masking: | |
6194 | err_msg = _("unsupported masking"); | |
6195 | break; | |
6196 | case mask_not_on_destination: | |
6197 | err_msg = _("mask not on destination operand"); | |
6198 | break; | |
6199 | case no_default_mask: | |
6200 | err_msg = _("default mask isn't allowed"); | |
6201 | break; | |
6202 | case unsupported_rc_sae: | |
6203 | err_msg = _("unsupported static rounding/sae"); | |
6204 | break; | |
6205 | case rc_sae_operand_not_last_imm: | |
6206 | if (intel_syntax) | |
6207 | err_msg = _("RC/SAE operand must precede immediate operands"); | |
6208 | else | |
6209 | err_msg = _("RC/SAE operand must follow immediate operands"); | |
6210 | break; | |
6211 | case invalid_register_operand: | |
6212 | err_msg = _("invalid register operand"); | |
6213 | break; | |
a65babc9 L |
6214 | } |
6215 | as_bad (_("%s for `%s'"), err_msg, | |
891edac4 | 6216 | current_templates->start->name); |
fa99fab2 | 6217 | return NULL; |
29b0f896 | 6218 | } |
252b5132 | 6219 | |
29b0f896 AM |
6220 | if (!quiet_warnings) |
6221 | { | |
6222 | if (!intel_syntax | |
0cfa3eb3 | 6223 | && (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))) |
6f2f06be | 6224 | as_warn (_("indirect %s without `*'"), t->name); |
29b0f896 | 6225 | |
40fb9820 L |
6226 | if (t->opcode_modifier.isprefix |
6227 | && t->opcode_modifier.ignoresize) | |
29b0f896 AM |
6228 | { |
6229 | /* Warn them that a data or address size prefix doesn't | |
6230 | affect assembly of the next line of code. */ | |
6231 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
6232 | } | |
6233 | } | |
6234 | ||
6235 | /* Copy the template we found. */ | |
6236 | i.tm = *t; | |
539e75ad L |
6237 | |
6238 | if (addr_prefix_disp != -1) | |
6239 | i.tm.operand_types[addr_prefix_disp] | |
6240 | = operand_types[addr_prefix_disp]; | |
6241 | ||
29b0f896 AM |
6242 | if (found_reverse_match) |
6243 | { | |
dfd69174 JB |
6244 | /* If we found a reverse match we must alter the opcode direction |
6245 | bit and clear/flip the regmem modifier one. found_reverse_match | |
6246 | holds bits to change (different for int & float insns). */ | |
29b0f896 AM |
6247 | |
6248 | i.tm.base_opcode ^= found_reverse_match; | |
6249 | ||
f5eb1d70 JB |
6250 | i.tm.operand_types[0] = operand_types[i.operands - 1]; |
6251 | i.tm.operand_types[i.operands - 1] = operand_types[0]; | |
dfd69174 JB |
6252 | |
6253 | /* Certain SIMD insns have their load forms specified in the opcode | |
6254 | table, and hence we need to _set_ RegMem instead of clearing it. | |
6255 | We need to avoid setting the bit though on insns like KMOVW. */ | |
6256 | i.tm.opcode_modifier.regmem | |
6257 | = i.tm.opcode_modifier.modrm && i.tm.opcode_modifier.d | |
6258 | && i.tm.operands > 2U - i.tm.opcode_modifier.sse2avx | |
6259 | && !i.tm.opcode_modifier.regmem; | |
29b0f896 AM |
6260 | } |
6261 | ||
fa99fab2 | 6262 | return t; |
29b0f896 AM |
6263 | } |
6264 | ||
6265 | static int | |
e3bb37b5 | 6266 | check_string (void) |
29b0f896 | 6267 | { |
51c8edf6 JB |
6268 | unsigned int es_op = i.tm.opcode_modifier.isstring - IS_STRING_ES_OP0; |
6269 | unsigned int op = i.tm.operand_types[0].bitfield.baseindex ? es_op : 0; | |
8dc0818e | 6270 | |
51c8edf6 | 6271 | if (i.seg[op] != NULL && i.seg[op] != &es) |
29b0f896 | 6272 | { |
51c8edf6 JB |
6273 | as_bad (_("`%s' operand %u must use `%ses' segment"), |
6274 | i.tm.name, | |
6275 | intel_syntax ? i.tm.operands - es_op : es_op + 1, | |
6276 | register_prefix); | |
6277 | return 0; | |
29b0f896 | 6278 | } |
51c8edf6 JB |
6279 | |
6280 | /* There's only ever one segment override allowed per instruction. | |
6281 | This instruction possibly has a legal segment override on the | |
6282 | second operand, so copy the segment to where non-string | |
6283 | instructions store it, allowing common code. */ | |
6284 | i.seg[op] = i.seg[1]; | |
6285 | ||
29b0f896 AM |
6286 | return 1; |
6287 | } | |
6288 | ||
6289 | static int | |
543613e9 | 6290 | process_suffix (void) |
29b0f896 AM |
6291 | { |
6292 | /* If matched instruction specifies an explicit instruction mnemonic | |
6293 | suffix, use it. */ | |
673fe0f0 | 6294 | if (i.tm.opcode_modifier.size == SIZE16) |
40fb9820 | 6295 | i.suffix = WORD_MNEM_SUFFIX; |
673fe0f0 | 6296 | else if (i.tm.opcode_modifier.size == SIZE32) |
40fb9820 | 6297 | i.suffix = LONG_MNEM_SUFFIX; |
673fe0f0 | 6298 | else if (i.tm.opcode_modifier.size == SIZE64) |
40fb9820 | 6299 | i.suffix = QWORD_MNEM_SUFFIX; |
13e600d0 JB |
6300 | else if (i.reg_operands |
6301 | && (i.operands > 1 || i.types[0].bitfield.class == Reg)) | |
29b0f896 AM |
6302 | { |
6303 | /* If there's no instruction mnemonic suffix we try to invent one | |
13e600d0 | 6304 | based on GPR operands. */ |
29b0f896 AM |
6305 | if (!i.suffix) |
6306 | { | |
6307 | /* We take i.suffix from the last register operand specified, | |
6308 | Destination register type is more significant than source | |
381d071f L |
6309 | register type. crc32 in SSE4.2 prefers source register |
6310 | type. */ | |
bab6aec1 JB |
6311 | if (i.tm.base_opcode == 0xf20f38f0 |
6312 | && i.types[0].bitfield.class == Reg) | |
381d071f | 6313 | { |
556059dd JB |
6314 | if (i.types[0].bitfield.byte) |
6315 | i.suffix = BYTE_MNEM_SUFFIX; | |
6316 | else if (i.types[0].bitfield.word) | |
40fb9820 | 6317 | i.suffix = WORD_MNEM_SUFFIX; |
556059dd | 6318 | else if (i.types[0].bitfield.dword) |
40fb9820 | 6319 | i.suffix = LONG_MNEM_SUFFIX; |
556059dd | 6320 | else if (i.types[0].bitfield.qword) |
40fb9820 | 6321 | i.suffix = QWORD_MNEM_SUFFIX; |
381d071f L |
6322 | } |
6323 | ||
6324 | if (!i.suffix) | |
6325 | { | |
6326 | int op; | |
6327 | ||
556059dd | 6328 | if (i.tm.base_opcode == 0xf20f38f0) |
20592a94 L |
6329 | { |
6330 | /* We have to know the operand size for crc32. */ | |
6331 | as_bad (_("ambiguous memory operand size for `%s`"), | |
6332 | i.tm.name); | |
6333 | return 0; | |
6334 | } | |
6335 | ||
381d071f | 6336 | for (op = i.operands; --op >= 0;) |
75e5731b JB |
6337 | if (i.tm.operand_types[op].bitfield.instance == InstanceNone |
6338 | || i.tm.operand_types[op].bitfield.instance == Accum) | |
381d071f | 6339 | { |
bab6aec1 | 6340 | if (i.types[op].bitfield.class != Reg) |
8819ada6 JB |
6341 | continue; |
6342 | if (i.types[op].bitfield.byte) | |
6343 | i.suffix = BYTE_MNEM_SUFFIX; | |
6344 | else if (i.types[op].bitfield.word) | |
6345 | i.suffix = WORD_MNEM_SUFFIX; | |
6346 | else if (i.types[op].bitfield.dword) | |
6347 | i.suffix = LONG_MNEM_SUFFIX; | |
6348 | else if (i.types[op].bitfield.qword) | |
6349 | i.suffix = QWORD_MNEM_SUFFIX; | |
6350 | else | |
6351 | continue; | |
6352 | break; | |
381d071f L |
6353 | } |
6354 | } | |
29b0f896 AM |
6355 | } |
6356 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
6357 | { | |
2eb952a4 L |
6358 | if (intel_syntax |
6359 | && i.tm.opcode_modifier.ignoresize | |
6360 | && i.tm.opcode_modifier.no_bsuf) | |
6361 | i.suffix = 0; | |
6362 | else if (!check_byte_reg ()) | |
29b0f896 AM |
6363 | return 0; |
6364 | } | |
6365 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
6366 | { | |
2eb952a4 L |
6367 | if (intel_syntax |
6368 | && i.tm.opcode_modifier.ignoresize | |
9f123b91 JB |
6369 | && i.tm.opcode_modifier.no_lsuf |
6370 | && !i.tm.opcode_modifier.todword | |
6371 | && !i.tm.opcode_modifier.toqword) | |
2eb952a4 L |
6372 | i.suffix = 0; |
6373 | else if (!check_long_reg ()) | |
29b0f896 AM |
6374 | return 0; |
6375 | } | |
6376 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
6377 | { | |
955e1e6a L |
6378 | if (intel_syntax |
6379 | && i.tm.opcode_modifier.ignoresize | |
9f123b91 JB |
6380 | && i.tm.opcode_modifier.no_qsuf |
6381 | && !i.tm.opcode_modifier.todword | |
6382 | && !i.tm.opcode_modifier.toqword) | |
955e1e6a L |
6383 | i.suffix = 0; |
6384 | else if (!check_qword_reg ()) | |
29b0f896 AM |
6385 | return 0; |
6386 | } | |
6387 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
6388 | { | |
2eb952a4 L |
6389 | if (intel_syntax |
6390 | && i.tm.opcode_modifier.ignoresize | |
6391 | && i.tm.opcode_modifier.no_wsuf) | |
6392 | i.suffix = 0; | |
6393 | else if (!check_word_reg ()) | |
29b0f896 AM |
6394 | return 0; |
6395 | } | |
40fb9820 | 6396 | else if (intel_syntax && i.tm.opcode_modifier.ignoresize) |
29b0f896 AM |
6397 | /* Do nothing if the instruction is going to ignore the prefix. */ |
6398 | ; | |
6399 | else | |
6400 | abort (); | |
6401 | } | |
40fb9820 | 6402 | else if (i.tm.opcode_modifier.defaultsize |
9306ca4a JB |
6403 | && !i.suffix |
6404 | /* exclude fldenv/frstor/fsave/fstenv */ | |
3036c899 JB |
6405 | && i.tm.opcode_modifier.no_ssuf |
6406 | /* exclude sysret */ | |
6407 | && i.tm.base_opcode != 0x0f07) | |
29b0f896 | 6408 | { |
13e600d0 JB |
6409 | i.suffix = stackop_size; |
6410 | if (stackop_size == LONG_MNEM_SUFFIX) | |
06f74c5c L |
6411 | { |
6412 | /* stackop_size is set to LONG_MNEM_SUFFIX for the | |
6413 | .code16gcc directive to support 16-bit mode with | |
6414 | 32-bit address. For IRET without a suffix, generate | |
6415 | 16-bit IRET (opcode 0xcf) to return from an interrupt | |
6416 | handler. */ | |
13e600d0 JB |
6417 | if (i.tm.base_opcode == 0xcf) |
6418 | { | |
6419 | i.suffix = WORD_MNEM_SUFFIX; | |
6420 | as_warn (_("generating 16-bit `iret' for .code16gcc directive")); | |
6421 | } | |
6422 | /* Warn about changed behavior for segment register push/pop. */ | |
6423 | else if ((i.tm.base_opcode | 1) == 0x07) | |
6424 | as_warn (_("generating 32-bit `%s', unlike earlier gas versions"), | |
6425 | i.tm.name); | |
06f74c5c | 6426 | } |
29b0f896 | 6427 | } |
9306ca4a JB |
6428 | else if (intel_syntax |
6429 | && !i.suffix | |
0cfa3eb3 JB |
6430 | && (i.tm.opcode_modifier.jump == JUMP_ABSOLUTE |
6431 | || i.tm.opcode_modifier.jump == JUMP_BYTE | |
6432 | || i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT | |
64e74474 AM |
6433 | || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */ |
6434 | && i.tm.extension_opcode <= 3))) | |
9306ca4a JB |
6435 | { |
6436 | switch (flag_code) | |
6437 | { | |
6438 | case CODE_64BIT: | |
40fb9820 | 6439 | if (!i.tm.opcode_modifier.no_qsuf) |
9306ca4a JB |
6440 | { |
6441 | i.suffix = QWORD_MNEM_SUFFIX; | |
6442 | break; | |
6443 | } | |
1a0670f3 | 6444 | /* Fall through. */ |
9306ca4a | 6445 | case CODE_32BIT: |
40fb9820 | 6446 | if (!i.tm.opcode_modifier.no_lsuf) |
9306ca4a JB |
6447 | i.suffix = LONG_MNEM_SUFFIX; |
6448 | break; | |
6449 | case CODE_16BIT: | |
40fb9820 | 6450 | if (!i.tm.opcode_modifier.no_wsuf) |
9306ca4a JB |
6451 | i.suffix = WORD_MNEM_SUFFIX; |
6452 | break; | |
6453 | } | |
6454 | } | |
252b5132 | 6455 | |
9306ca4a | 6456 | if (!i.suffix) |
29b0f896 | 6457 | { |
9306ca4a JB |
6458 | if (!intel_syntax) |
6459 | { | |
40fb9820 | 6460 | if (i.tm.opcode_modifier.w) |
9306ca4a | 6461 | { |
4eed87de AM |
6462 | as_bad (_("no instruction mnemonic suffix given and " |
6463 | "no register operands; can't size instruction")); | |
9306ca4a JB |
6464 | return 0; |
6465 | } | |
6466 | } | |
6467 | else | |
6468 | { | |
40fb9820 | 6469 | unsigned int suffixes; |
7ab9ffdd | 6470 | |
40fb9820 L |
6471 | suffixes = !i.tm.opcode_modifier.no_bsuf; |
6472 | if (!i.tm.opcode_modifier.no_wsuf) | |
6473 | suffixes |= 1 << 1; | |
6474 | if (!i.tm.opcode_modifier.no_lsuf) | |
6475 | suffixes |= 1 << 2; | |
fc4adea1 | 6476 | if (!i.tm.opcode_modifier.no_ldsuf) |
40fb9820 L |
6477 | suffixes |= 1 << 3; |
6478 | if (!i.tm.opcode_modifier.no_ssuf) | |
6479 | suffixes |= 1 << 4; | |
c2b9da16 | 6480 | if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf) |
40fb9820 L |
6481 | suffixes |= 1 << 5; |
6482 | ||
6483 | /* There are more than suffix matches. */ | |
6484 | if (i.tm.opcode_modifier.w | |
9306ca4a | 6485 | || ((suffixes & (suffixes - 1)) |
40fb9820 L |
6486 | && !i.tm.opcode_modifier.defaultsize |
6487 | && !i.tm.opcode_modifier.ignoresize)) | |
9306ca4a JB |
6488 | { |
6489 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); | |
6490 | return 0; | |
6491 | } | |
6492 | } | |
29b0f896 | 6493 | } |
252b5132 | 6494 | |
d2224064 JB |
6495 | /* Change the opcode based on the operand size given by i.suffix. */ |
6496 | switch (i.suffix) | |
29b0f896 | 6497 | { |
d2224064 JB |
6498 | /* Size floating point instruction. */ |
6499 | case LONG_MNEM_SUFFIX: | |
6500 | if (i.tm.opcode_modifier.floatmf) | |
6501 | { | |
6502 | i.tm.base_opcode ^= 4; | |
6503 | break; | |
6504 | } | |
6505 | /* fall through */ | |
6506 | case WORD_MNEM_SUFFIX: | |
6507 | case QWORD_MNEM_SUFFIX: | |
29b0f896 | 6508 | /* It's not a byte, select word/dword operation. */ |
40fb9820 | 6509 | if (i.tm.opcode_modifier.w) |
29b0f896 | 6510 | { |
40fb9820 | 6511 | if (i.tm.opcode_modifier.shortform) |
29b0f896 AM |
6512 | i.tm.base_opcode |= 8; |
6513 | else | |
6514 | i.tm.base_opcode |= 1; | |
6515 | } | |
d2224064 JB |
6516 | /* fall through */ |
6517 | case SHORT_MNEM_SUFFIX: | |
29b0f896 AM |
6518 | /* Now select between word & dword operations via the operand |
6519 | size prefix, except for instructions that will ignore this | |
6520 | prefix anyway. */ | |
75c0a438 | 6521 | if (i.reg_operands > 0 |
bab6aec1 | 6522 | && i.types[0].bitfield.class == Reg |
75c0a438 | 6523 | && i.tm.opcode_modifier.addrprefixopreg |
474da251 | 6524 | && (i.tm.operand_types[0].bitfield.instance == Accum |
75c0a438 | 6525 | || i.operands == 1)) |
cb712a9e | 6526 | { |
ca61edf2 L |
6527 | /* The address size override prefix changes the size of the |
6528 | first operand. */ | |
40fb9820 | 6529 | if ((flag_code == CODE_32BIT |
75c0a438 | 6530 | && i.op[0].regs->reg_type.bitfield.word) |
40fb9820 | 6531 | || (flag_code != CODE_32BIT |
75c0a438 | 6532 | && i.op[0].regs->reg_type.bitfield.dword)) |
cb712a9e L |
6533 | if (!add_prefix (ADDR_PREFIX_OPCODE)) |
6534 | return 0; | |
6535 | } | |
6536 | else if (i.suffix != QWORD_MNEM_SUFFIX | |
40fb9820 L |
6537 | && !i.tm.opcode_modifier.ignoresize |
6538 | && !i.tm.opcode_modifier.floatmf | |
a38d7118 | 6539 | && !is_any_vex_encoding (&i.tm) |
cb712a9e L |
6540 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) |
6541 | || (flag_code == CODE_64BIT | |
0cfa3eb3 | 6542 | && i.tm.opcode_modifier.jump == JUMP_BYTE))) |
24eab124 AM |
6543 | { |
6544 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
543613e9 | 6545 | |
0cfa3eb3 | 6546 | if (i.tm.opcode_modifier.jump == JUMP_BYTE) /* jcxz, loop */ |
29b0f896 | 6547 | prefix = ADDR_PREFIX_OPCODE; |
252b5132 | 6548 | |
29b0f896 AM |
6549 | if (!add_prefix (prefix)) |
6550 | return 0; | |
24eab124 | 6551 | } |
252b5132 | 6552 | |
29b0f896 AM |
6553 | /* Set mode64 for an operand. */ |
6554 | if (i.suffix == QWORD_MNEM_SUFFIX | |
9146926a | 6555 | && flag_code == CODE_64BIT |
d2224064 | 6556 | && !i.tm.opcode_modifier.norex64 |
46e883c5 | 6557 | /* Special case for xchg %rax,%rax. It is NOP and doesn't |
d2224064 JB |
6558 | need rex64. */ |
6559 | && ! (i.operands == 2 | |
6560 | && i.tm.base_opcode == 0x90 | |
6561 | && i.tm.extension_opcode == None | |
75e5731b JB |
6562 | && i.types[0].bitfield.instance == Accum |
6563 | && i.types[0].bitfield.qword | |
6564 | && i.types[1].bitfield.instance == Accum | |
6565 | && i.types[1].bitfield.qword)) | |
d2224064 | 6566 | i.rex |= REX_W; |
3e73aa7c | 6567 | |
d2224064 | 6568 | break; |
29b0f896 | 6569 | } |
7ecd2f8b | 6570 | |
c0a30a9f L |
6571 | if (i.reg_operands != 0 |
6572 | && i.operands > 1 | |
6573 | && i.tm.opcode_modifier.addrprefixopreg | |
474da251 | 6574 | && i.tm.operand_types[0].bitfield.instance != Accum) |
c0a30a9f L |
6575 | { |
6576 | /* Check invalid register operand when the address size override | |
6577 | prefix changes the size of register operands. */ | |
6578 | unsigned int op; | |
6579 | enum { need_word, need_dword, need_qword } need; | |
6580 | ||
6581 | if (flag_code == CODE_32BIT) | |
6582 | need = i.prefix[ADDR_PREFIX] ? need_word : need_dword; | |
6583 | else | |
6584 | { | |
6585 | if (i.prefix[ADDR_PREFIX]) | |
6586 | need = need_dword; | |
6587 | else | |
6588 | need = flag_code == CODE_64BIT ? need_qword : need_word; | |
6589 | } | |
6590 | ||
6591 | for (op = 0; op < i.operands; op++) | |
bab6aec1 | 6592 | if (i.types[op].bitfield.class == Reg |
c0a30a9f L |
6593 | && ((need == need_word |
6594 | && !i.op[op].regs->reg_type.bitfield.word) | |
6595 | || (need == need_dword | |
6596 | && !i.op[op].regs->reg_type.bitfield.dword) | |
6597 | || (need == need_qword | |
6598 | && !i.op[op].regs->reg_type.bitfield.qword))) | |
6599 | { | |
6600 | as_bad (_("invalid register operand size for `%s'"), | |
6601 | i.tm.name); | |
6602 | return 0; | |
6603 | } | |
6604 | } | |
6605 | ||
29b0f896 AM |
6606 | return 1; |
6607 | } | |
3e73aa7c | 6608 | |
29b0f896 | 6609 | static int |
543613e9 | 6610 | check_byte_reg (void) |
29b0f896 AM |
6611 | { |
6612 | int op; | |
543613e9 | 6613 | |
29b0f896 AM |
6614 | for (op = i.operands; --op >= 0;) |
6615 | { | |
dc821c5f | 6616 | /* Skip non-register operands. */ |
bab6aec1 | 6617 | if (i.types[op].bitfield.class != Reg) |
dc821c5f JB |
6618 | continue; |
6619 | ||
29b0f896 AM |
6620 | /* If this is an eight bit register, it's OK. If it's the 16 or |
6621 | 32 bit version of an eight bit register, we will just use the | |
6622 | low portion, and that's OK too. */ | |
dc821c5f | 6623 | if (i.types[op].bitfield.byte) |
29b0f896 AM |
6624 | continue; |
6625 | ||
5a819eb9 | 6626 | /* I/O port address operands are OK too. */ |
75e5731b JB |
6627 | if (i.tm.operand_types[op].bitfield.instance == RegD |
6628 | && i.tm.operand_types[op].bitfield.word) | |
5a819eb9 JB |
6629 | continue; |
6630 | ||
9344ff29 L |
6631 | /* crc32 doesn't generate this warning. */ |
6632 | if (i.tm.base_opcode == 0xf20f38f0) | |
6633 | continue; | |
6634 | ||
dc821c5f JB |
6635 | if ((i.types[op].bitfield.word |
6636 | || i.types[op].bitfield.dword | |
6637 | || i.types[op].bitfield.qword) | |
5a819eb9 JB |
6638 | && i.op[op].regs->reg_num < 4 |
6639 | /* Prohibit these changes in 64bit mode, since the lowering | |
6640 | would be more complicated. */ | |
6641 | && flag_code != CODE_64BIT) | |
29b0f896 | 6642 | { |
29b0f896 | 6643 | #if REGISTER_WARNINGS |
5a819eb9 | 6644 | if (!quiet_warnings) |
a540244d L |
6645 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
6646 | register_prefix, | |
dc821c5f | 6647 | (i.op[op].regs + (i.types[op].bitfield.word |
29b0f896 AM |
6648 | ? REGNAM_AL - REGNAM_AX |
6649 | : REGNAM_AL - REGNAM_EAX))->reg_name, | |
a540244d | 6650 | register_prefix, |
29b0f896 AM |
6651 | i.op[op].regs->reg_name, |
6652 | i.suffix); | |
6653 | #endif | |
6654 | continue; | |
6655 | } | |
6656 | /* Any other register is bad. */ | |
bab6aec1 | 6657 | if (i.types[op].bitfield.class == Reg |
3528c362 JB |
6658 | || i.types[op].bitfield.class == RegMMX |
6659 | || i.types[op].bitfield.class == RegSIMD | |
00cee14f | 6660 | || i.types[op].bitfield.class == SReg |
4a5c67ed JB |
6661 | || i.types[op].bitfield.class == RegCR |
6662 | || i.types[op].bitfield.class == RegDR | |
6663 | || i.types[op].bitfield.class == RegTR) | |
29b0f896 | 6664 | { |
a540244d L |
6665 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6666 | register_prefix, | |
29b0f896 AM |
6667 | i.op[op].regs->reg_name, |
6668 | i.tm.name, | |
6669 | i.suffix); | |
6670 | return 0; | |
6671 | } | |
6672 | } | |
6673 | return 1; | |
6674 | } | |
6675 | ||
6676 | static int | |
e3bb37b5 | 6677 | check_long_reg (void) |
29b0f896 AM |
6678 | { |
6679 | int op; | |
6680 | ||
6681 | for (op = i.operands; --op >= 0;) | |
dc821c5f | 6682 | /* Skip non-register operands. */ |
bab6aec1 | 6683 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 6684 | continue; |
29b0f896 AM |
6685 | /* Reject eight bit registers, except where the template requires |
6686 | them. (eg. movzb) */ | |
dc821c5f | 6687 | else if (i.types[op].bitfield.byte |
bab6aec1 | 6688 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 6689 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f JB |
6690 | && (i.tm.operand_types[op].bitfield.word |
6691 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 6692 | { |
a540244d L |
6693 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6694 | register_prefix, | |
29b0f896 AM |
6695 | i.op[op].regs->reg_name, |
6696 | i.tm.name, | |
6697 | i.suffix); | |
6698 | return 0; | |
6699 | } | |
e4630f71 | 6700 | /* Warn if the e prefix on a general reg is missing. */ |
29b0f896 | 6701 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
dc821c5f | 6702 | && i.types[op].bitfield.word |
bab6aec1 | 6703 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 6704 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 6705 | && i.tm.operand_types[op].bitfield.dword) |
29b0f896 AM |
6706 | { |
6707 | /* Prohibit these changes in the 64bit mode, since the | |
6708 | lowering is more complicated. */ | |
6709 | if (flag_code == CODE_64BIT) | |
252b5132 | 6710 | { |
2b5d6a91 | 6711 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
2ca3ace5 | 6712 | register_prefix, i.op[op].regs->reg_name, |
29b0f896 AM |
6713 | i.suffix); |
6714 | return 0; | |
252b5132 | 6715 | } |
29b0f896 | 6716 | #if REGISTER_WARNINGS |
cecf1424 JB |
6717 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
6718 | register_prefix, | |
6719 | (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name, | |
6720 | register_prefix, i.op[op].regs->reg_name, i.suffix); | |
29b0f896 | 6721 | #endif |
252b5132 | 6722 | } |
e4630f71 | 6723 | /* Warn if the r prefix on a general reg is present. */ |
dc821c5f | 6724 | else if (i.types[op].bitfield.qword |
bab6aec1 | 6725 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 6726 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 6727 | && i.tm.operand_types[op].bitfield.dword) |
252b5132 | 6728 | { |
34828aad | 6729 | if (intel_syntax |
ca61edf2 | 6730 | && i.tm.opcode_modifier.toqword |
3528c362 | 6731 | && i.types[0].bitfield.class != RegSIMD) |
34828aad | 6732 | { |
ca61edf2 | 6733 | /* Convert to QWORD. We want REX byte. */ |
34828aad L |
6734 | i.suffix = QWORD_MNEM_SUFFIX; |
6735 | } | |
6736 | else | |
6737 | { | |
2b5d6a91 | 6738 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
6739 | register_prefix, i.op[op].regs->reg_name, |
6740 | i.suffix); | |
6741 | return 0; | |
6742 | } | |
29b0f896 AM |
6743 | } |
6744 | return 1; | |
6745 | } | |
252b5132 | 6746 | |
29b0f896 | 6747 | static int |
e3bb37b5 | 6748 | check_qword_reg (void) |
29b0f896 AM |
6749 | { |
6750 | int op; | |
252b5132 | 6751 | |
29b0f896 | 6752 | for (op = i.operands; --op >= 0; ) |
dc821c5f | 6753 | /* Skip non-register operands. */ |
bab6aec1 | 6754 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 6755 | continue; |
29b0f896 AM |
6756 | /* Reject eight bit registers, except where the template requires |
6757 | them. (eg. movzb) */ | |
dc821c5f | 6758 | else if (i.types[op].bitfield.byte |
bab6aec1 | 6759 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 6760 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f JB |
6761 | && (i.tm.operand_types[op].bitfield.word |
6762 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 6763 | { |
a540244d L |
6764 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6765 | register_prefix, | |
29b0f896 AM |
6766 | i.op[op].regs->reg_name, |
6767 | i.tm.name, | |
6768 | i.suffix); | |
6769 | return 0; | |
6770 | } | |
e4630f71 | 6771 | /* Warn if the r prefix on a general reg is missing. */ |
dc821c5f JB |
6772 | else if ((i.types[op].bitfield.word |
6773 | || i.types[op].bitfield.dword) | |
bab6aec1 | 6774 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 6775 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 6776 | && i.tm.operand_types[op].bitfield.qword) |
29b0f896 AM |
6777 | { |
6778 | /* Prohibit these changes in the 64bit mode, since the | |
6779 | lowering is more complicated. */ | |
34828aad | 6780 | if (intel_syntax |
ca61edf2 | 6781 | && i.tm.opcode_modifier.todword |
3528c362 | 6782 | && i.types[0].bitfield.class != RegSIMD) |
34828aad | 6783 | { |
ca61edf2 | 6784 | /* Convert to DWORD. We don't want REX byte. */ |
34828aad L |
6785 | i.suffix = LONG_MNEM_SUFFIX; |
6786 | } | |
6787 | else | |
6788 | { | |
2b5d6a91 | 6789 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
6790 | register_prefix, i.op[op].regs->reg_name, |
6791 | i.suffix); | |
6792 | return 0; | |
6793 | } | |
252b5132 | 6794 | } |
29b0f896 AM |
6795 | return 1; |
6796 | } | |
252b5132 | 6797 | |
29b0f896 | 6798 | static int |
e3bb37b5 | 6799 | check_word_reg (void) |
29b0f896 AM |
6800 | { |
6801 | int op; | |
6802 | for (op = i.operands; --op >= 0;) | |
dc821c5f | 6803 | /* Skip non-register operands. */ |
bab6aec1 | 6804 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 6805 | continue; |
29b0f896 AM |
6806 | /* Reject eight bit registers, except where the template requires |
6807 | them. (eg. movzb) */ | |
dc821c5f | 6808 | else if (i.types[op].bitfield.byte |
bab6aec1 | 6809 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 6810 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f JB |
6811 | && (i.tm.operand_types[op].bitfield.word |
6812 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 6813 | { |
a540244d L |
6814 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6815 | register_prefix, | |
29b0f896 AM |
6816 | i.op[op].regs->reg_name, |
6817 | i.tm.name, | |
6818 | i.suffix); | |
6819 | return 0; | |
6820 | } | |
e4630f71 | 6821 | /* Warn if the e or r prefix on a general reg is present. */ |
29b0f896 | 6822 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
dc821c5f JB |
6823 | && (i.types[op].bitfield.dword |
6824 | || i.types[op].bitfield.qword) | |
bab6aec1 | 6825 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 6826 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 6827 | && i.tm.operand_types[op].bitfield.word) |
252b5132 | 6828 | { |
29b0f896 AM |
6829 | /* Prohibit these changes in the 64bit mode, since the |
6830 | lowering is more complicated. */ | |
6831 | if (flag_code == CODE_64BIT) | |
252b5132 | 6832 | { |
2b5d6a91 | 6833 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
2ca3ace5 | 6834 | register_prefix, i.op[op].regs->reg_name, |
29b0f896 AM |
6835 | i.suffix); |
6836 | return 0; | |
252b5132 | 6837 | } |
29b0f896 | 6838 | #if REGISTER_WARNINGS |
cecf1424 JB |
6839 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
6840 | register_prefix, | |
6841 | (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name, | |
6842 | register_prefix, i.op[op].regs->reg_name, i.suffix); | |
29b0f896 AM |
6843 | #endif |
6844 | } | |
6845 | return 1; | |
6846 | } | |
252b5132 | 6847 | |
29b0f896 | 6848 | static int |
40fb9820 | 6849 | update_imm (unsigned int j) |
29b0f896 | 6850 | { |
bc0844ae | 6851 | i386_operand_type overlap = i.types[j]; |
40fb9820 L |
6852 | if ((overlap.bitfield.imm8 |
6853 | || overlap.bitfield.imm8s | |
6854 | || overlap.bitfield.imm16 | |
6855 | || overlap.bitfield.imm32 | |
6856 | || overlap.bitfield.imm32s | |
6857 | || overlap.bitfield.imm64) | |
0dfbf9d7 L |
6858 | && !operand_type_equal (&overlap, &imm8) |
6859 | && !operand_type_equal (&overlap, &imm8s) | |
6860 | && !operand_type_equal (&overlap, &imm16) | |
6861 | && !operand_type_equal (&overlap, &imm32) | |
6862 | && !operand_type_equal (&overlap, &imm32s) | |
6863 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 AM |
6864 | { |
6865 | if (i.suffix) | |
6866 | { | |
40fb9820 L |
6867 | i386_operand_type temp; |
6868 | ||
0dfbf9d7 | 6869 | operand_type_set (&temp, 0); |
7ab9ffdd | 6870 | if (i.suffix == BYTE_MNEM_SUFFIX) |
40fb9820 L |
6871 | { |
6872 | temp.bitfield.imm8 = overlap.bitfield.imm8; | |
6873 | temp.bitfield.imm8s = overlap.bitfield.imm8s; | |
6874 | } | |
6875 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
6876 | temp.bitfield.imm16 = overlap.bitfield.imm16; | |
6877 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
6878 | { | |
6879 | temp.bitfield.imm64 = overlap.bitfield.imm64; | |
6880 | temp.bitfield.imm32s = overlap.bitfield.imm32s; | |
6881 | } | |
6882 | else | |
6883 | temp.bitfield.imm32 = overlap.bitfield.imm32; | |
6884 | overlap = temp; | |
29b0f896 | 6885 | } |
0dfbf9d7 L |
6886 | else if (operand_type_equal (&overlap, &imm16_32_32s) |
6887 | || operand_type_equal (&overlap, &imm16_32) | |
6888 | || operand_type_equal (&overlap, &imm16_32s)) | |
29b0f896 | 6889 | { |
40fb9820 | 6890 | if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
65da13b5 | 6891 | overlap = imm16; |
40fb9820 | 6892 | else |
65da13b5 | 6893 | overlap = imm32s; |
29b0f896 | 6894 | } |
0dfbf9d7 L |
6895 | if (!operand_type_equal (&overlap, &imm8) |
6896 | && !operand_type_equal (&overlap, &imm8s) | |
6897 | && !operand_type_equal (&overlap, &imm16) | |
6898 | && !operand_type_equal (&overlap, &imm32) | |
6899 | && !operand_type_equal (&overlap, &imm32s) | |
6900 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 | 6901 | { |
4eed87de AM |
6902 | as_bad (_("no instruction mnemonic suffix given; " |
6903 | "can't determine immediate size")); | |
29b0f896 AM |
6904 | return 0; |
6905 | } | |
6906 | } | |
40fb9820 | 6907 | i.types[j] = overlap; |
29b0f896 | 6908 | |
40fb9820 L |
6909 | return 1; |
6910 | } | |
6911 | ||
6912 | static int | |
6913 | finalize_imm (void) | |
6914 | { | |
bc0844ae | 6915 | unsigned int j, n; |
29b0f896 | 6916 | |
bc0844ae L |
6917 | /* Update the first 2 immediate operands. */ |
6918 | n = i.operands > 2 ? 2 : i.operands; | |
6919 | if (n) | |
6920 | { | |
6921 | for (j = 0; j < n; j++) | |
6922 | if (update_imm (j) == 0) | |
6923 | return 0; | |
40fb9820 | 6924 | |
bc0844ae L |
6925 | /* The 3rd operand can't be immediate operand. */ |
6926 | gas_assert (operand_type_check (i.types[2], imm) == 0); | |
6927 | } | |
29b0f896 AM |
6928 | |
6929 | return 1; | |
6930 | } | |
6931 | ||
6932 | static int | |
e3bb37b5 | 6933 | process_operands (void) |
29b0f896 AM |
6934 | { |
6935 | /* Default segment register this instruction will use for memory | |
6936 | accesses. 0 means unknown. This is only for optimizing out | |
6937 | unnecessary segment overrides. */ | |
6938 | const seg_entry *default_seg = 0; | |
6939 | ||
2426c15f | 6940 | if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv) |
29b0f896 | 6941 | { |
91d6fa6a NC |
6942 | unsigned int dupl = i.operands; |
6943 | unsigned int dest = dupl - 1; | |
9fcfb3d7 L |
6944 | unsigned int j; |
6945 | ||
c0f3af97 | 6946 | /* The destination must be an xmm register. */ |
9c2799c2 | 6947 | gas_assert (i.reg_operands |
91d6fa6a | 6948 | && MAX_OPERANDS > dupl |
7ab9ffdd | 6949 | && operand_type_equal (&i.types[dest], ®xmm)); |
c0f3af97 | 6950 | |
75e5731b | 6951 | if (i.tm.operand_types[0].bitfield.instance == Accum |
1b54b8d7 | 6952 | && i.tm.operand_types[0].bitfield.xmmword) |
e2ec9d29 | 6953 | { |
8cd7925b | 6954 | if (i.tm.opcode_modifier.vexsources == VEX3SOURCES) |
c0f3af97 L |
6955 | { |
6956 | /* Keep xmm0 for instructions with VEX prefix and 3 | |
6957 | sources. */ | |
75e5731b | 6958 | i.tm.operand_types[0].bitfield.instance = InstanceNone; |
3528c362 | 6959 | i.tm.operand_types[0].bitfield.class = RegSIMD; |
c0f3af97 L |
6960 | goto duplicate; |
6961 | } | |
e2ec9d29 | 6962 | else |
c0f3af97 L |
6963 | { |
6964 | /* We remove the first xmm0 and keep the number of | |
6965 | operands unchanged, which in fact duplicates the | |
6966 | destination. */ | |
6967 | for (j = 1; j < i.operands; j++) | |
6968 | { | |
6969 | i.op[j - 1] = i.op[j]; | |
6970 | i.types[j - 1] = i.types[j]; | |
6971 | i.tm.operand_types[j - 1] = i.tm.operand_types[j]; | |
8dc0818e | 6972 | i.flags[j - 1] = i.flags[j]; |
c0f3af97 L |
6973 | } |
6974 | } | |
6975 | } | |
6976 | else if (i.tm.opcode_modifier.implicit1stxmm0) | |
7ab9ffdd | 6977 | { |
91d6fa6a | 6978 | gas_assert ((MAX_OPERANDS - 1) > dupl |
8cd7925b L |
6979 | && (i.tm.opcode_modifier.vexsources |
6980 | == VEX3SOURCES)); | |
c0f3af97 L |
6981 | |
6982 | /* Add the implicit xmm0 for instructions with VEX prefix | |
6983 | and 3 sources. */ | |
6984 | for (j = i.operands; j > 0; j--) | |
6985 | { | |
6986 | i.op[j] = i.op[j - 1]; | |
6987 | i.types[j] = i.types[j - 1]; | |
6988 | i.tm.operand_types[j] = i.tm.operand_types[j - 1]; | |
8dc0818e | 6989 | i.flags[j] = i.flags[j - 1]; |
c0f3af97 L |
6990 | } |
6991 | i.op[0].regs | |
6992 | = (const reg_entry *) hash_find (reg_hash, "xmm0"); | |
7ab9ffdd | 6993 | i.types[0] = regxmm; |
c0f3af97 L |
6994 | i.tm.operand_types[0] = regxmm; |
6995 | ||
6996 | i.operands += 2; | |
6997 | i.reg_operands += 2; | |
6998 | i.tm.operands += 2; | |
6999 | ||
91d6fa6a | 7000 | dupl++; |
c0f3af97 | 7001 | dest++; |
91d6fa6a NC |
7002 | i.op[dupl] = i.op[dest]; |
7003 | i.types[dupl] = i.types[dest]; | |
7004 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
8dc0818e | 7005 | i.flags[dupl] = i.flags[dest]; |
e2ec9d29 | 7006 | } |
c0f3af97 L |
7007 | else |
7008 | { | |
7009 | duplicate: | |
7010 | i.operands++; | |
7011 | i.reg_operands++; | |
7012 | i.tm.operands++; | |
7013 | ||
91d6fa6a NC |
7014 | i.op[dupl] = i.op[dest]; |
7015 | i.types[dupl] = i.types[dest]; | |
7016 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
8dc0818e | 7017 | i.flags[dupl] = i.flags[dest]; |
c0f3af97 L |
7018 | } |
7019 | ||
7020 | if (i.tm.opcode_modifier.immext) | |
7021 | process_immext (); | |
7022 | } | |
75e5731b | 7023 | else if (i.tm.operand_types[0].bitfield.instance == Accum |
1b54b8d7 | 7024 | && i.tm.operand_types[0].bitfield.xmmword) |
c0f3af97 L |
7025 | { |
7026 | unsigned int j; | |
7027 | ||
9fcfb3d7 L |
7028 | for (j = 1; j < i.operands; j++) |
7029 | { | |
7030 | i.op[j - 1] = i.op[j]; | |
7031 | i.types[j - 1] = i.types[j]; | |
7032 | ||
7033 | /* We need to adjust fields in i.tm since they are used by | |
7034 | build_modrm_byte. */ | |
7035 | i.tm.operand_types [j - 1] = i.tm.operand_types [j]; | |
8dc0818e JB |
7036 | |
7037 | i.flags[j - 1] = i.flags[j]; | |
9fcfb3d7 L |
7038 | } |
7039 | ||
e2ec9d29 L |
7040 | i.operands--; |
7041 | i.reg_operands--; | |
e2ec9d29 L |
7042 | i.tm.operands--; |
7043 | } | |
920d2ddc IT |
7044 | else if (i.tm.opcode_modifier.implicitquadgroup) |
7045 | { | |
a477a8c4 JB |
7046 | unsigned int regnum, first_reg_in_group, last_reg_in_group; |
7047 | ||
920d2ddc | 7048 | /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */ |
3528c362 | 7049 | gas_assert (i.operands >= 2 && i.types[1].bitfield.class == RegSIMD); |
a477a8c4 JB |
7050 | regnum = register_number (i.op[1].regs); |
7051 | first_reg_in_group = regnum & ~3; | |
7052 | last_reg_in_group = first_reg_in_group + 3; | |
7053 | if (regnum != first_reg_in_group) | |
7054 | as_warn (_("source register `%s%s' implicitly denotes" | |
7055 | " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"), | |
7056 | register_prefix, i.op[1].regs->reg_name, | |
7057 | register_prefix, i.op[1].regs->reg_name, first_reg_in_group, | |
7058 | register_prefix, i.op[1].regs->reg_name, last_reg_in_group, | |
7059 | i.tm.name); | |
7060 | } | |
e2ec9d29 L |
7061 | else if (i.tm.opcode_modifier.regkludge) |
7062 | { | |
7063 | /* The imul $imm, %reg instruction is converted into | |
7064 | imul $imm, %reg, %reg, and the clr %reg instruction | |
7065 | is converted into xor %reg, %reg. */ | |
7066 | ||
7067 | unsigned int first_reg_op; | |
7068 | ||
7069 | if (operand_type_check (i.types[0], reg)) | |
7070 | first_reg_op = 0; | |
7071 | else | |
7072 | first_reg_op = 1; | |
7073 | /* Pretend we saw the extra register operand. */ | |
9c2799c2 | 7074 | gas_assert (i.reg_operands == 1 |
7ab9ffdd | 7075 | && i.op[first_reg_op + 1].regs == 0); |
e2ec9d29 L |
7076 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; |
7077 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
7078 | i.operands++; | |
7079 | i.reg_operands++; | |
29b0f896 AM |
7080 | } |
7081 | ||
85b80b0f | 7082 | if (i.tm.opcode_modifier.modrm) |
29b0f896 AM |
7083 | { |
7084 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
52271982 AM |
7085 | must be put into the modrm byte). Now, we make the modrm and |
7086 | index base bytes based on all the info we've collected. */ | |
29b0f896 AM |
7087 | |
7088 | default_seg = build_modrm_byte (); | |
7089 | } | |
00cee14f | 7090 | else if (i.types[0].bitfield.class == SReg) |
85b80b0f JB |
7091 | { |
7092 | if (flag_code != CODE_64BIT | |
7093 | ? i.tm.base_opcode == POP_SEG_SHORT | |
7094 | && i.op[0].regs->reg_num == 1 | |
7095 | : (i.tm.base_opcode | 1) == POP_SEG386_SHORT | |
7096 | && i.op[0].regs->reg_num < 4) | |
7097 | { | |
7098 | as_bad (_("you can't `%s %s%s'"), | |
7099 | i.tm.name, register_prefix, i.op[0].regs->reg_name); | |
7100 | return 0; | |
7101 | } | |
7102 | if ( i.op[0].regs->reg_num > 3 && i.tm.opcode_length == 1 ) | |
7103 | { | |
7104 | i.tm.base_opcode ^= POP_SEG_SHORT ^ POP_SEG386_SHORT; | |
7105 | i.tm.opcode_length = 2; | |
7106 | } | |
7107 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); | |
7108 | } | |
8a2ed489 | 7109 | else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32) |
29b0f896 AM |
7110 | { |
7111 | default_seg = &ds; | |
7112 | } | |
40fb9820 | 7113 | else if (i.tm.opcode_modifier.isstring) |
29b0f896 AM |
7114 | { |
7115 | /* For the string instructions that allow a segment override | |
7116 | on one of their operands, the default segment is ds. */ | |
7117 | default_seg = &ds; | |
7118 | } | |
85b80b0f JB |
7119 | else if (i.tm.opcode_modifier.shortform) |
7120 | { | |
7121 | /* The register or float register operand is in operand | |
7122 | 0 or 1. */ | |
bab6aec1 | 7123 | unsigned int op = i.tm.operand_types[0].bitfield.class != Reg; |
85b80b0f JB |
7124 | |
7125 | /* Register goes in low 3 bits of opcode. */ | |
7126 | i.tm.base_opcode |= i.op[op].regs->reg_num; | |
7127 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
7128 | i.rex |= REX_B; | |
7129 | if (!quiet_warnings && i.tm.opcode_modifier.ugh) | |
7130 | { | |
7131 | /* Warn about some common errors, but press on regardless. | |
7132 | The first case can be generated by gcc (<= 2.8.1). */ | |
7133 | if (i.operands == 2) | |
7134 | { | |
7135 | /* Reversed arguments on faddp, fsubp, etc. */ | |
7136 | as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, | |
7137 | register_prefix, i.op[!intel_syntax].regs->reg_name, | |
7138 | register_prefix, i.op[intel_syntax].regs->reg_name); | |
7139 | } | |
7140 | else | |
7141 | { | |
7142 | /* Extraneous `l' suffix on fp insn. */ | |
7143 | as_warn (_("translating to `%s %s%s'"), i.tm.name, | |
7144 | register_prefix, i.op[0].regs->reg_name); | |
7145 | } | |
7146 | } | |
7147 | } | |
29b0f896 | 7148 | |
75178d9d L |
7149 | if (i.tm.base_opcode == 0x8d /* lea */ |
7150 | && i.seg[0] | |
7151 | && !quiet_warnings) | |
30123838 | 7152 | as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); |
52271982 AM |
7153 | |
7154 | /* If a segment was explicitly specified, and the specified segment | |
7155 | is not the default, use an opcode prefix to select it. If we | |
7156 | never figured out what the default segment is, then default_seg | |
7157 | will be zero at this point, and the specified segment prefix will | |
7158 | always be used. */ | |
29b0f896 AM |
7159 | if ((i.seg[0]) && (i.seg[0] != default_seg)) |
7160 | { | |
7161 | if (!add_prefix (i.seg[0]->seg_prefix)) | |
7162 | return 0; | |
7163 | } | |
7164 | return 1; | |
7165 | } | |
7166 | ||
7167 | static const seg_entry * | |
e3bb37b5 | 7168 | build_modrm_byte (void) |
29b0f896 AM |
7169 | { |
7170 | const seg_entry *default_seg = 0; | |
c0f3af97 | 7171 | unsigned int source, dest; |
8cd7925b | 7172 | int vex_3_sources; |
c0f3af97 | 7173 | |
8cd7925b | 7174 | vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES; |
c0f3af97 L |
7175 | if (vex_3_sources) |
7176 | { | |
91d6fa6a | 7177 | unsigned int nds, reg_slot; |
4c2c6516 | 7178 | expressionS *exp; |
c0f3af97 | 7179 | |
6b8d3588 | 7180 | dest = i.operands - 1; |
c0f3af97 | 7181 | nds = dest - 1; |
922d8de8 | 7182 | |
a683cc34 | 7183 | /* There are 2 kinds of instructions: |
bed3d976 | 7184 | 1. 5 operands: 4 register operands or 3 register operands |
9d3bf266 | 7185 | plus 1 memory operand plus one Imm4 operand, VexXDS, and |
bed3d976 | 7186 | VexW0 or VexW1. The destination must be either XMM, YMM or |
43234a1e | 7187 | ZMM register. |
bed3d976 | 7188 | 2. 4 operands: 4 register operands or 3 register operands |
2f1bada2 | 7189 | plus 1 memory operand, with VexXDS. */ |
922d8de8 | 7190 | gas_assert ((i.reg_operands == 4 |
bed3d976 JB |
7191 | || (i.reg_operands == 3 && i.mem_operands == 1)) |
7192 | && i.tm.opcode_modifier.vexvvvv == VEXXDS | |
dcd7e323 | 7193 | && i.tm.opcode_modifier.vexw |
3528c362 | 7194 | && i.tm.operand_types[dest].bitfield.class == RegSIMD); |
a683cc34 | 7195 | |
48db9223 JB |
7196 | /* If VexW1 is set, the first non-immediate operand is the source and |
7197 | the second non-immediate one is encoded in the immediate operand. */ | |
7198 | if (i.tm.opcode_modifier.vexw == VEXW1) | |
7199 | { | |
7200 | source = i.imm_operands; | |
7201 | reg_slot = i.imm_operands + 1; | |
7202 | } | |
7203 | else | |
7204 | { | |
7205 | source = i.imm_operands + 1; | |
7206 | reg_slot = i.imm_operands; | |
7207 | } | |
7208 | ||
a683cc34 | 7209 | if (i.imm_operands == 0) |
bed3d976 JB |
7210 | { |
7211 | /* When there is no immediate operand, generate an 8bit | |
7212 | immediate operand to encode the first operand. */ | |
7213 | exp = &im_expressions[i.imm_operands++]; | |
7214 | i.op[i.operands].imms = exp; | |
7215 | i.types[i.operands] = imm8; | |
7216 | i.operands++; | |
7217 | ||
3528c362 | 7218 | gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD); |
bed3d976 JB |
7219 | exp->X_op = O_constant; |
7220 | exp->X_add_number = register_number (i.op[reg_slot].regs) << 4; | |
43234a1e L |
7221 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
7222 | } | |
922d8de8 | 7223 | else |
bed3d976 | 7224 | { |
9d3bf266 JB |
7225 | gas_assert (i.imm_operands == 1); |
7226 | gas_assert (fits_in_imm4 (i.op[0].imms->X_add_number)); | |
7227 | gas_assert (!i.tm.opcode_modifier.immext); | |
a683cc34 | 7228 | |
9d3bf266 JB |
7229 | /* Turn on Imm8 again so that output_imm will generate it. */ |
7230 | i.types[0].bitfield.imm8 = 1; | |
bed3d976 | 7231 | |
3528c362 | 7232 | gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD); |
9d3bf266 | 7233 | i.op[0].imms->X_add_number |
bed3d976 | 7234 | |= register_number (i.op[reg_slot].regs) << 4; |
43234a1e | 7235 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
bed3d976 | 7236 | } |
a683cc34 | 7237 | |
3528c362 | 7238 | gas_assert (i.tm.operand_types[nds].bitfield.class == RegSIMD); |
dae39acc | 7239 | i.vex.register_specifier = i.op[nds].regs; |
c0f3af97 L |
7240 | } |
7241 | else | |
7242 | source = dest = 0; | |
29b0f896 AM |
7243 | |
7244 | /* i.reg_operands MUST be the number of real register operands; | |
c0f3af97 L |
7245 | implicit registers do not count. If there are 3 register |
7246 | operands, it must be a instruction with VexNDS. For a | |
7247 | instruction with VexNDD, the destination register is encoded | |
7248 | in VEX prefix. If there are 4 register operands, it must be | |
7249 | a instruction with VEX prefix and 3 sources. */ | |
7ab9ffdd L |
7250 | if (i.mem_operands == 0 |
7251 | && ((i.reg_operands == 2 | |
2426c15f | 7252 | && i.tm.opcode_modifier.vexvvvv <= VEXXDS) |
7ab9ffdd | 7253 | || (i.reg_operands == 3 |
2426c15f | 7254 | && i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd | 7255 | || (i.reg_operands == 4 && vex_3_sources))) |
29b0f896 | 7256 | { |
cab737b9 L |
7257 | switch (i.operands) |
7258 | { | |
7259 | case 2: | |
7260 | source = 0; | |
7261 | break; | |
7262 | case 3: | |
c81128dc L |
7263 | /* When there are 3 operands, one of them may be immediate, |
7264 | which may be the first or the last operand. Otherwise, | |
c0f3af97 L |
7265 | the first operand must be shift count register (cl) or it |
7266 | is an instruction with VexNDS. */ | |
9c2799c2 | 7267 | gas_assert (i.imm_operands == 1 |
7ab9ffdd | 7268 | || (i.imm_operands == 0 |
2426c15f | 7269 | && (i.tm.opcode_modifier.vexvvvv == VEXXDS |
75e5731b JB |
7270 | || (i.types[0].bitfield.instance == RegC |
7271 | && i.types[0].bitfield.byte)))); | |
40fb9820 | 7272 | if (operand_type_check (i.types[0], imm) |
75e5731b JB |
7273 | || (i.types[0].bitfield.instance == RegC |
7274 | && i.types[0].bitfield.byte)) | |
40fb9820 L |
7275 | source = 1; |
7276 | else | |
7277 | source = 0; | |
cab737b9 L |
7278 | break; |
7279 | case 4: | |
368d64cc L |
7280 | /* When there are 4 operands, the first two must be 8bit |
7281 | immediate operands. The source operand will be the 3rd | |
c0f3af97 L |
7282 | one. |
7283 | ||
7284 | For instructions with VexNDS, if the first operand | |
7285 | an imm8, the source operand is the 2nd one. If the last | |
7286 | operand is imm8, the source operand is the first one. */ | |
9c2799c2 | 7287 | gas_assert ((i.imm_operands == 2 |
7ab9ffdd L |
7288 | && i.types[0].bitfield.imm8 |
7289 | && i.types[1].bitfield.imm8) | |
2426c15f | 7290 | || (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd L |
7291 | && i.imm_operands == 1 |
7292 | && (i.types[0].bitfield.imm8 | |
43234a1e L |
7293 | || i.types[i.operands - 1].bitfield.imm8 |
7294 | || i.rounding))); | |
9f2670f2 L |
7295 | if (i.imm_operands == 2) |
7296 | source = 2; | |
7297 | else | |
c0f3af97 L |
7298 | { |
7299 | if (i.types[0].bitfield.imm8) | |
7300 | source = 1; | |
7301 | else | |
7302 | source = 0; | |
7303 | } | |
c0f3af97 L |
7304 | break; |
7305 | case 5: | |
e771e7c9 | 7306 | if (is_evex_encoding (&i.tm)) |
43234a1e L |
7307 | { |
7308 | /* For EVEX instructions, when there are 5 operands, the | |
7309 | first one must be immediate operand. If the second one | |
7310 | is immediate operand, the source operand is the 3th | |
7311 | one. If the last one is immediate operand, the source | |
7312 | operand is the 2nd one. */ | |
7313 | gas_assert (i.imm_operands == 2 | |
7314 | && i.tm.opcode_modifier.sae | |
7315 | && operand_type_check (i.types[0], imm)); | |
7316 | if (operand_type_check (i.types[1], imm)) | |
7317 | source = 2; | |
7318 | else if (operand_type_check (i.types[4], imm)) | |
7319 | source = 1; | |
7320 | else | |
7321 | abort (); | |
7322 | } | |
cab737b9 L |
7323 | break; |
7324 | default: | |
7325 | abort (); | |
7326 | } | |
7327 | ||
c0f3af97 L |
7328 | if (!vex_3_sources) |
7329 | { | |
7330 | dest = source + 1; | |
7331 | ||
43234a1e L |
7332 | /* RC/SAE operand could be between DEST and SRC. That happens |
7333 | when one operand is GPR and the other one is XMM/YMM/ZMM | |
7334 | register. */ | |
7335 | if (i.rounding && i.rounding->operand == (int) dest) | |
7336 | dest++; | |
7337 | ||
2426c15f | 7338 | if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
c0f3af97 | 7339 | { |
43234a1e | 7340 | /* For instructions with VexNDS, the register-only source |
c5d0745b | 7341 | operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask |
dfd69174 | 7342 | register. It is encoded in VEX prefix. */ |
f12dc422 L |
7343 | |
7344 | i386_operand_type op; | |
7345 | unsigned int vvvv; | |
7346 | ||
7347 | /* Check register-only source operand when two source | |
7348 | operands are swapped. */ | |
7349 | if (!i.tm.operand_types[source].bitfield.baseindex | |
7350 | && i.tm.operand_types[dest].bitfield.baseindex) | |
7351 | { | |
7352 | vvvv = source; | |
7353 | source = dest; | |
7354 | } | |
7355 | else | |
7356 | vvvv = dest; | |
7357 | ||
7358 | op = i.tm.operand_types[vvvv]; | |
c0f3af97 | 7359 | if ((dest + 1) >= i.operands |
bab6aec1 | 7360 | || ((op.bitfield.class != Reg |
dc821c5f | 7361 | || (!op.bitfield.dword && !op.bitfield.qword)) |
3528c362 | 7362 | && op.bitfield.class != RegSIMD |
43234a1e | 7363 | && !operand_type_equal (&op, ®mask))) |
c0f3af97 | 7364 | abort (); |
f12dc422 | 7365 | i.vex.register_specifier = i.op[vvvv].regs; |
c0f3af97 L |
7366 | dest++; |
7367 | } | |
7368 | } | |
29b0f896 AM |
7369 | |
7370 | i.rm.mode = 3; | |
dfd69174 JB |
7371 | /* One of the register operands will be encoded in the i.rm.reg |
7372 | field, the other in the combined i.rm.mode and i.rm.regmem | |
29b0f896 AM |
7373 | fields. If no form of this instruction supports a memory |
7374 | destination operand, then we assume the source operand may | |
7375 | sometimes be a memory operand and so we need to store the | |
7376 | destination in the i.rm.reg field. */ | |
dfd69174 | 7377 | if (!i.tm.opcode_modifier.regmem |
40fb9820 | 7378 | && operand_type_check (i.tm.operand_types[dest], anymem) == 0) |
29b0f896 AM |
7379 | { |
7380 | i.rm.reg = i.op[dest].regs->reg_num; | |
7381 | i.rm.regmem = i.op[source].regs->reg_num; | |
3528c362 JB |
7382 | if (i.op[dest].regs->reg_type.bitfield.class == RegMMX |
7383 | || i.op[source].regs->reg_type.bitfield.class == RegMMX) | |
b4a3a7b4 | 7384 | i.has_regmmx = TRUE; |
3528c362 JB |
7385 | else if (i.op[dest].regs->reg_type.bitfield.class == RegSIMD |
7386 | || i.op[source].regs->reg_type.bitfield.class == RegSIMD) | |
b4a3a7b4 L |
7387 | { |
7388 | if (i.types[dest].bitfield.zmmword | |
7389 | || i.types[source].bitfield.zmmword) | |
7390 | i.has_regzmm = TRUE; | |
7391 | else if (i.types[dest].bitfield.ymmword | |
7392 | || i.types[source].bitfield.ymmword) | |
7393 | i.has_regymm = TRUE; | |
7394 | else | |
7395 | i.has_regxmm = TRUE; | |
7396 | } | |
29b0f896 | 7397 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) |
161a04f6 | 7398 | i.rex |= REX_R; |
43234a1e L |
7399 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
7400 | i.vrex |= REX_R; | |
29b0f896 | 7401 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 7402 | i.rex |= REX_B; |
43234a1e L |
7403 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
7404 | i.vrex |= REX_B; | |
29b0f896 AM |
7405 | } |
7406 | else | |
7407 | { | |
7408 | i.rm.reg = i.op[source].regs->reg_num; | |
7409 | i.rm.regmem = i.op[dest].regs->reg_num; | |
7410 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 7411 | i.rex |= REX_B; |
43234a1e L |
7412 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
7413 | i.vrex |= REX_B; | |
29b0f896 | 7414 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 7415 | i.rex |= REX_R; |
43234a1e L |
7416 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
7417 | i.vrex |= REX_R; | |
29b0f896 | 7418 | } |
e0c7f900 | 7419 | if (flag_code != CODE_64BIT && (i.rex & REX_R)) |
c4a530c5 | 7420 | { |
4a5c67ed | 7421 | if (i.types[!i.tm.opcode_modifier.regmem].bitfield.class != RegCR) |
c4a530c5 | 7422 | abort (); |
e0c7f900 | 7423 | i.rex &= ~REX_R; |
c4a530c5 JB |
7424 | add_prefix (LOCK_PREFIX_OPCODE); |
7425 | } | |
29b0f896 AM |
7426 | } |
7427 | else | |
7428 | { /* If it's not 2 reg operands... */ | |
c0f3af97 L |
7429 | unsigned int mem; |
7430 | ||
29b0f896 AM |
7431 | if (i.mem_operands) |
7432 | { | |
7433 | unsigned int fake_zero_displacement = 0; | |
99018f42 | 7434 | unsigned int op; |
4eed87de | 7435 | |
7ab9ffdd | 7436 | for (op = 0; op < i.operands; op++) |
8dc0818e | 7437 | if (i.flags[op] & Operand_Mem) |
7ab9ffdd | 7438 | break; |
7ab9ffdd | 7439 | gas_assert (op < i.operands); |
29b0f896 | 7440 | |
6c30d220 L |
7441 | if (i.tm.opcode_modifier.vecsib) |
7442 | { | |
e968fc9b | 7443 | if (i.index_reg->reg_num == RegIZ) |
6c30d220 L |
7444 | abort (); |
7445 | ||
7446 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
7447 | if (!i.base_reg) | |
7448 | { | |
7449 | i.sib.base = NO_BASE_REGISTER; | |
7450 | i.sib.scale = i.log2_scale_factor; | |
7451 | i.types[op].bitfield.disp8 = 0; | |
7452 | i.types[op].bitfield.disp16 = 0; | |
7453 | i.types[op].bitfield.disp64 = 0; | |
43083a50 | 7454 | if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX]) |
6c30d220 L |
7455 | { |
7456 | /* Must be 32 bit */ | |
7457 | i.types[op].bitfield.disp32 = 1; | |
7458 | i.types[op].bitfield.disp32s = 0; | |
7459 | } | |
7460 | else | |
7461 | { | |
7462 | i.types[op].bitfield.disp32 = 0; | |
7463 | i.types[op].bitfield.disp32s = 1; | |
7464 | } | |
7465 | } | |
7466 | i.sib.index = i.index_reg->reg_num; | |
7467 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
7468 | i.rex |= REX_X; | |
43234a1e L |
7469 | if ((i.index_reg->reg_flags & RegVRex) != 0) |
7470 | i.vrex |= REX_X; | |
6c30d220 L |
7471 | } |
7472 | ||
29b0f896 AM |
7473 | default_seg = &ds; |
7474 | ||
7475 | if (i.base_reg == 0) | |
7476 | { | |
7477 | i.rm.mode = 0; | |
7478 | if (!i.disp_operands) | |
9bb129e8 | 7479 | fake_zero_displacement = 1; |
29b0f896 AM |
7480 | if (i.index_reg == 0) |
7481 | { | |
73053c1f JB |
7482 | i386_operand_type newdisp; |
7483 | ||
6c30d220 | 7484 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 7485 | /* Operand is just <disp> */ |
20f0a1fc | 7486 | if (flag_code == CODE_64BIT) |
29b0f896 AM |
7487 | { |
7488 | /* 64bit mode overwrites the 32bit absolute | |
7489 | addressing by RIP relative addressing and | |
7490 | absolute addressing is encoded by one of the | |
7491 | redundant SIB forms. */ | |
7492 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
7493 | i.sib.base = NO_BASE_REGISTER; | |
7494 | i.sib.index = NO_INDEX_REGISTER; | |
73053c1f | 7495 | newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32); |
20f0a1fc | 7496 | } |
fc225355 L |
7497 | else if ((flag_code == CODE_16BIT) |
7498 | ^ (i.prefix[ADDR_PREFIX] != 0)) | |
20f0a1fc NC |
7499 | { |
7500 | i.rm.regmem = NO_BASE_REGISTER_16; | |
73053c1f | 7501 | newdisp = disp16; |
20f0a1fc NC |
7502 | } |
7503 | else | |
7504 | { | |
7505 | i.rm.regmem = NO_BASE_REGISTER; | |
73053c1f | 7506 | newdisp = disp32; |
29b0f896 | 7507 | } |
73053c1f JB |
7508 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
7509 | i.types[op] = operand_type_or (i.types[op], newdisp); | |
29b0f896 | 7510 | } |
6c30d220 | 7511 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 7512 | { |
6c30d220 | 7513 | /* !i.base_reg && i.index_reg */ |
e968fc9b | 7514 | if (i.index_reg->reg_num == RegIZ) |
db51cc60 L |
7515 | i.sib.index = NO_INDEX_REGISTER; |
7516 | else | |
7517 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
7518 | i.sib.base = NO_BASE_REGISTER; |
7519 | i.sib.scale = i.log2_scale_factor; | |
7520 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
40fb9820 L |
7521 | i.types[op].bitfield.disp8 = 0; |
7522 | i.types[op].bitfield.disp16 = 0; | |
7523 | i.types[op].bitfield.disp64 = 0; | |
43083a50 | 7524 | if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX]) |
40fb9820 L |
7525 | { |
7526 | /* Must be 32 bit */ | |
7527 | i.types[op].bitfield.disp32 = 1; | |
7528 | i.types[op].bitfield.disp32s = 0; | |
7529 | } | |
29b0f896 | 7530 | else |
40fb9820 L |
7531 | { |
7532 | i.types[op].bitfield.disp32 = 0; | |
7533 | i.types[op].bitfield.disp32s = 1; | |
7534 | } | |
29b0f896 | 7535 | if ((i.index_reg->reg_flags & RegRex) != 0) |
161a04f6 | 7536 | i.rex |= REX_X; |
29b0f896 AM |
7537 | } |
7538 | } | |
7539 | /* RIP addressing for 64bit mode. */ | |
e968fc9b | 7540 | else if (i.base_reg->reg_num == RegIP) |
29b0f896 | 7541 | { |
6c30d220 | 7542 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 7543 | i.rm.regmem = NO_BASE_REGISTER; |
40fb9820 L |
7544 | i.types[op].bitfield.disp8 = 0; |
7545 | i.types[op].bitfield.disp16 = 0; | |
7546 | i.types[op].bitfield.disp32 = 0; | |
7547 | i.types[op].bitfield.disp32s = 1; | |
7548 | i.types[op].bitfield.disp64 = 0; | |
71903a11 | 7549 | i.flags[op] |= Operand_PCrel; |
20f0a1fc NC |
7550 | if (! i.disp_operands) |
7551 | fake_zero_displacement = 1; | |
29b0f896 | 7552 | } |
dc821c5f | 7553 | else if (i.base_reg->reg_type.bitfield.word) |
29b0f896 | 7554 | { |
6c30d220 | 7555 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
7556 | switch (i.base_reg->reg_num) |
7557 | { | |
7558 | case 3: /* (%bx) */ | |
7559 | if (i.index_reg == 0) | |
7560 | i.rm.regmem = 7; | |
7561 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
7562 | i.rm.regmem = i.index_reg->reg_num - 6; | |
7563 | break; | |
7564 | case 5: /* (%bp) */ | |
7565 | default_seg = &ss; | |
7566 | if (i.index_reg == 0) | |
7567 | { | |
7568 | i.rm.regmem = 6; | |
40fb9820 | 7569 | if (operand_type_check (i.types[op], disp) == 0) |
29b0f896 AM |
7570 | { |
7571 | /* fake (%bp) into 0(%bp) */ | |
b5014f7a | 7572 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 7573 | fake_zero_displacement = 1; |
29b0f896 AM |
7574 | } |
7575 | } | |
7576 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
7577 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
7578 | break; | |
7579 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
7580 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
7581 | } | |
7582 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
7583 | } | |
7584 | else /* i.base_reg and 32/64 bit mode */ | |
7585 | { | |
7586 | if (flag_code == CODE_64BIT | |
40fb9820 L |
7587 | && operand_type_check (i.types[op], disp)) |
7588 | { | |
73053c1f JB |
7589 | i.types[op].bitfield.disp16 = 0; |
7590 | i.types[op].bitfield.disp64 = 0; | |
40fb9820 | 7591 | if (i.prefix[ADDR_PREFIX] == 0) |
73053c1f JB |
7592 | { |
7593 | i.types[op].bitfield.disp32 = 0; | |
7594 | i.types[op].bitfield.disp32s = 1; | |
7595 | } | |
40fb9820 | 7596 | else |
73053c1f JB |
7597 | { |
7598 | i.types[op].bitfield.disp32 = 1; | |
7599 | i.types[op].bitfield.disp32s = 0; | |
7600 | } | |
40fb9820 | 7601 | } |
20f0a1fc | 7602 | |
6c30d220 L |
7603 | if (!i.tm.opcode_modifier.vecsib) |
7604 | i.rm.regmem = i.base_reg->reg_num; | |
29b0f896 | 7605 | if ((i.base_reg->reg_flags & RegRex) != 0) |
161a04f6 | 7606 | i.rex |= REX_B; |
29b0f896 AM |
7607 | i.sib.base = i.base_reg->reg_num; |
7608 | /* x86-64 ignores REX prefix bit here to avoid decoder | |
7609 | complications. */ | |
848930b2 JB |
7610 | if (!(i.base_reg->reg_flags & RegRex) |
7611 | && (i.base_reg->reg_num == EBP_REG_NUM | |
7612 | || i.base_reg->reg_num == ESP_REG_NUM)) | |
29b0f896 | 7613 | default_seg = &ss; |
848930b2 | 7614 | if (i.base_reg->reg_num == 5 && i.disp_operands == 0) |
29b0f896 | 7615 | { |
848930b2 | 7616 | fake_zero_displacement = 1; |
b5014f7a | 7617 | i.types[op].bitfield.disp8 = 1; |
29b0f896 AM |
7618 | } |
7619 | i.sib.scale = i.log2_scale_factor; | |
7620 | if (i.index_reg == 0) | |
7621 | { | |
6c30d220 | 7622 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
7623 | /* <disp>(%esp) becomes two byte modrm with no index |
7624 | register. We've already stored the code for esp | |
7625 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. | |
7626 | Any base register besides %esp will not use the | |
7627 | extra modrm byte. */ | |
7628 | i.sib.index = NO_INDEX_REGISTER; | |
29b0f896 | 7629 | } |
6c30d220 | 7630 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 7631 | { |
e968fc9b | 7632 | if (i.index_reg->reg_num == RegIZ) |
db51cc60 L |
7633 | i.sib.index = NO_INDEX_REGISTER; |
7634 | else | |
7635 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
7636 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
7637 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
161a04f6 | 7638 | i.rex |= REX_X; |
29b0f896 | 7639 | } |
67a4f2b7 AO |
7640 | |
7641 | if (i.disp_operands | |
7642 | && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL | |
7643 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) | |
7644 | i.rm.mode = 0; | |
7645 | else | |
a501d77e L |
7646 | { |
7647 | if (!fake_zero_displacement | |
7648 | && !i.disp_operands | |
7649 | && i.disp_encoding) | |
7650 | { | |
7651 | fake_zero_displacement = 1; | |
7652 | if (i.disp_encoding == disp_encoding_8bit) | |
7653 | i.types[op].bitfield.disp8 = 1; | |
7654 | else | |
7655 | i.types[op].bitfield.disp32 = 1; | |
7656 | } | |
7657 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
7658 | } | |
29b0f896 | 7659 | } |
252b5132 | 7660 | |
29b0f896 AM |
7661 | if (fake_zero_displacement) |
7662 | { | |
7663 | /* Fakes a zero displacement assuming that i.types[op] | |
7664 | holds the correct displacement size. */ | |
7665 | expressionS *exp; | |
7666 | ||
9c2799c2 | 7667 | gas_assert (i.op[op].disps == 0); |
29b0f896 AM |
7668 | exp = &disp_expressions[i.disp_operands++]; |
7669 | i.op[op].disps = exp; | |
7670 | exp->X_op = O_constant; | |
7671 | exp->X_add_number = 0; | |
7672 | exp->X_add_symbol = (symbolS *) 0; | |
7673 | exp->X_op_symbol = (symbolS *) 0; | |
7674 | } | |
c0f3af97 L |
7675 | |
7676 | mem = op; | |
29b0f896 | 7677 | } |
c0f3af97 L |
7678 | else |
7679 | mem = ~0; | |
252b5132 | 7680 | |
8c43a48b | 7681 | if (i.tm.opcode_modifier.vexsources == XOP2SOURCES) |
5dd85c99 SP |
7682 | { |
7683 | if (operand_type_check (i.types[0], imm)) | |
7684 | i.vex.register_specifier = NULL; | |
7685 | else | |
7686 | { | |
7687 | /* VEX.vvvv encodes one of the sources when the first | |
7688 | operand is not an immediate. */ | |
1ef99a7b | 7689 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
7690 | i.vex.register_specifier = i.op[0].regs; |
7691 | else | |
7692 | i.vex.register_specifier = i.op[1].regs; | |
7693 | } | |
7694 | ||
7695 | /* Destination is a XMM register encoded in the ModRM.reg | |
7696 | and VEX.R bit. */ | |
7697 | i.rm.reg = i.op[2].regs->reg_num; | |
7698 | if ((i.op[2].regs->reg_flags & RegRex) != 0) | |
7699 | i.rex |= REX_R; | |
7700 | ||
7701 | /* ModRM.rm and VEX.B encodes the other source. */ | |
7702 | if (!i.mem_operands) | |
7703 | { | |
7704 | i.rm.mode = 3; | |
7705 | ||
1ef99a7b | 7706 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
7707 | i.rm.regmem = i.op[1].regs->reg_num; |
7708 | else | |
7709 | i.rm.regmem = i.op[0].regs->reg_num; | |
7710 | ||
7711 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
7712 | i.rex |= REX_B; | |
7713 | } | |
7714 | } | |
2426c15f | 7715 | else if (i.tm.opcode_modifier.vexvvvv == VEXLWP) |
f88c9eb0 SP |
7716 | { |
7717 | i.vex.register_specifier = i.op[2].regs; | |
7718 | if (!i.mem_operands) | |
7719 | { | |
7720 | i.rm.mode = 3; | |
7721 | i.rm.regmem = i.op[1].regs->reg_num; | |
7722 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
7723 | i.rex |= REX_B; | |
7724 | } | |
7725 | } | |
29b0f896 AM |
7726 | /* Fill in i.rm.reg or i.rm.regmem field with register operand |
7727 | (if any) based on i.tm.extension_opcode. Again, we must be | |
7728 | careful to make sure that segment/control/debug/test/MMX | |
7729 | registers are coded into the i.rm.reg field. */ | |
f88c9eb0 | 7730 | else if (i.reg_operands) |
29b0f896 | 7731 | { |
99018f42 | 7732 | unsigned int op; |
7ab9ffdd L |
7733 | unsigned int vex_reg = ~0; |
7734 | ||
7735 | for (op = 0; op < i.operands; op++) | |
b4a3a7b4 | 7736 | { |
bab6aec1 | 7737 | if (i.types[op].bitfield.class == Reg |
f74a6307 JB |
7738 | || i.types[op].bitfield.class == RegBND |
7739 | || i.types[op].bitfield.class == RegMask | |
00cee14f | 7740 | || i.types[op].bitfield.class == SReg |
4a5c67ed JB |
7741 | || i.types[op].bitfield.class == RegCR |
7742 | || i.types[op].bitfield.class == RegDR | |
7743 | || i.types[op].bitfield.class == RegTR) | |
b4a3a7b4 | 7744 | break; |
3528c362 | 7745 | if (i.types[op].bitfield.class == RegSIMD) |
b4a3a7b4 L |
7746 | { |
7747 | if (i.types[op].bitfield.zmmword) | |
7748 | i.has_regzmm = TRUE; | |
7749 | else if (i.types[op].bitfield.ymmword) | |
7750 | i.has_regymm = TRUE; | |
7751 | else | |
7752 | i.has_regxmm = TRUE; | |
7753 | break; | |
7754 | } | |
3528c362 | 7755 | if (i.types[op].bitfield.class == RegMMX) |
b4a3a7b4 L |
7756 | { |
7757 | i.has_regmmx = TRUE; | |
7758 | break; | |
7759 | } | |
7760 | } | |
c0209578 | 7761 | |
7ab9ffdd L |
7762 | if (vex_3_sources) |
7763 | op = dest; | |
2426c15f | 7764 | else if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd L |
7765 | { |
7766 | /* For instructions with VexNDS, the register-only | |
7767 | source operand is encoded in VEX prefix. */ | |
7768 | gas_assert (mem != (unsigned int) ~0); | |
c0f3af97 | 7769 | |
7ab9ffdd | 7770 | if (op > mem) |
c0f3af97 | 7771 | { |
7ab9ffdd L |
7772 | vex_reg = op++; |
7773 | gas_assert (op < i.operands); | |
c0f3af97 L |
7774 | } |
7775 | else | |
c0f3af97 | 7776 | { |
f12dc422 L |
7777 | /* Check register-only source operand when two source |
7778 | operands are swapped. */ | |
7779 | if (!i.tm.operand_types[op].bitfield.baseindex | |
7780 | && i.tm.operand_types[op + 1].bitfield.baseindex) | |
7781 | { | |
7782 | vex_reg = op; | |
7783 | op += 2; | |
7784 | gas_assert (mem == (vex_reg + 1) | |
7785 | && op < i.operands); | |
7786 | } | |
7787 | else | |
7788 | { | |
7789 | vex_reg = op + 1; | |
7790 | gas_assert (vex_reg < i.operands); | |
7791 | } | |
c0f3af97 | 7792 | } |
7ab9ffdd | 7793 | } |
2426c15f | 7794 | else if (i.tm.opcode_modifier.vexvvvv == VEXNDD) |
7ab9ffdd | 7795 | { |
f12dc422 | 7796 | /* For instructions with VexNDD, the register destination |
7ab9ffdd | 7797 | is encoded in VEX prefix. */ |
f12dc422 L |
7798 | if (i.mem_operands == 0) |
7799 | { | |
7800 | /* There is no memory operand. */ | |
7801 | gas_assert ((op + 2) == i.operands); | |
7802 | vex_reg = op + 1; | |
7803 | } | |
7804 | else | |
8d63c93e | 7805 | { |
ed438a93 JB |
7806 | /* There are only 2 non-immediate operands. */ |
7807 | gas_assert (op < i.imm_operands + 2 | |
7808 | && i.operands == i.imm_operands + 2); | |
7809 | vex_reg = i.imm_operands + 1; | |
f12dc422 | 7810 | } |
7ab9ffdd L |
7811 | } |
7812 | else | |
7813 | gas_assert (op < i.operands); | |
99018f42 | 7814 | |
7ab9ffdd L |
7815 | if (vex_reg != (unsigned int) ~0) |
7816 | { | |
f12dc422 | 7817 | i386_operand_type *type = &i.tm.operand_types[vex_reg]; |
7ab9ffdd | 7818 | |
bab6aec1 | 7819 | if ((type->bitfield.class != Reg |
dc821c5f | 7820 | || (!type->bitfield.dword && !type->bitfield.qword)) |
3528c362 | 7821 | && type->bitfield.class != RegSIMD |
43234a1e | 7822 | && !operand_type_equal (type, ®mask)) |
7ab9ffdd | 7823 | abort (); |
f88c9eb0 | 7824 | |
7ab9ffdd L |
7825 | i.vex.register_specifier = i.op[vex_reg].regs; |
7826 | } | |
7827 | ||
1b9f0c97 L |
7828 | /* Don't set OP operand twice. */ |
7829 | if (vex_reg != op) | |
7ab9ffdd | 7830 | { |
1b9f0c97 L |
7831 | /* If there is an extension opcode to put here, the |
7832 | register number must be put into the regmem field. */ | |
7833 | if (i.tm.extension_opcode != None) | |
7834 | { | |
7835 | i.rm.regmem = i.op[op].regs->reg_num; | |
7836 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
7837 | i.rex |= REX_B; | |
43234a1e L |
7838 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
7839 | i.vrex |= REX_B; | |
1b9f0c97 L |
7840 | } |
7841 | else | |
7842 | { | |
7843 | i.rm.reg = i.op[op].regs->reg_num; | |
7844 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
7845 | i.rex |= REX_R; | |
43234a1e L |
7846 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
7847 | i.vrex |= REX_R; | |
1b9f0c97 | 7848 | } |
7ab9ffdd | 7849 | } |
252b5132 | 7850 | |
29b0f896 AM |
7851 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we |
7852 | must set it to 3 to indicate this is a register operand | |
7853 | in the regmem field. */ | |
7854 | if (!i.mem_operands) | |
7855 | i.rm.mode = 3; | |
7856 | } | |
252b5132 | 7857 | |
29b0f896 | 7858 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
c1e679ec | 7859 | if (i.tm.extension_opcode != None) |
29b0f896 AM |
7860 | i.rm.reg = i.tm.extension_opcode; |
7861 | } | |
7862 | return default_seg; | |
7863 | } | |
252b5132 | 7864 | |
376cd056 JB |
7865 | static unsigned int |
7866 | flip_code16 (unsigned int code16) | |
7867 | { | |
7868 | gas_assert (i.tm.operands == 1); | |
7869 | ||
7870 | return !(i.prefix[REX_PREFIX] & REX_W) | |
7871 | && (code16 ? i.tm.operand_types[0].bitfield.disp32 | |
7872 | || i.tm.operand_types[0].bitfield.disp32s | |
7873 | : i.tm.operand_types[0].bitfield.disp16) | |
7874 | ? CODE16 : 0; | |
7875 | } | |
7876 | ||
29b0f896 | 7877 | static void |
e3bb37b5 | 7878 | output_branch (void) |
29b0f896 AM |
7879 | { |
7880 | char *p; | |
f8a5c266 | 7881 | int size; |
29b0f896 AM |
7882 | int code16; |
7883 | int prefix; | |
7884 | relax_substateT subtype; | |
7885 | symbolS *sym; | |
7886 | offsetT off; | |
7887 | ||
f8a5c266 | 7888 | code16 = flag_code == CODE_16BIT ? CODE16 : 0; |
a501d77e | 7889 | size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL; |
29b0f896 AM |
7890 | |
7891 | prefix = 0; | |
7892 | if (i.prefix[DATA_PREFIX] != 0) | |
252b5132 | 7893 | { |
29b0f896 AM |
7894 | prefix = 1; |
7895 | i.prefixes -= 1; | |
376cd056 | 7896 | code16 ^= flip_code16(code16); |
252b5132 | 7897 | } |
29b0f896 AM |
7898 | /* Pentium4 branch hints. */ |
7899 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
7900 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2f66722d | 7901 | { |
29b0f896 AM |
7902 | prefix++; |
7903 | i.prefixes--; | |
7904 | } | |
7905 | if (i.prefix[REX_PREFIX] != 0) | |
7906 | { | |
7907 | prefix++; | |
7908 | i.prefixes--; | |
2f66722d AM |
7909 | } |
7910 | ||
7e8b059b L |
7911 | /* BND prefixed jump. */ |
7912 | if (i.prefix[BND_PREFIX] != 0) | |
7913 | { | |
6cb0a70e JB |
7914 | prefix++; |
7915 | i.prefixes--; | |
7e8b059b L |
7916 | } |
7917 | ||
f2810fe0 JB |
7918 | if (i.prefixes != 0) |
7919 | as_warn (_("skipping prefixes on `%s'"), i.tm.name); | |
29b0f896 AM |
7920 | |
7921 | /* It's always a symbol; End frag & setup for relax. | |
7922 | Make sure there is enough room in this frag for the largest | |
7923 | instruction we may generate in md_convert_frag. This is 2 | |
7924 | bytes for the opcode and room for the prefix and largest | |
7925 | displacement. */ | |
7926 | frag_grow (prefix + 2 + 4); | |
7927 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
7928 | p = frag_more (prefix + 1); | |
7929 | if (i.prefix[DATA_PREFIX] != 0) | |
7930 | *p++ = DATA_PREFIX_OPCODE; | |
7931 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE | |
7932 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
7933 | *p++ = i.prefix[SEG_PREFIX]; | |
6cb0a70e JB |
7934 | if (i.prefix[BND_PREFIX] != 0) |
7935 | *p++ = BND_PREFIX_OPCODE; | |
29b0f896 AM |
7936 | if (i.prefix[REX_PREFIX] != 0) |
7937 | *p++ = i.prefix[REX_PREFIX]; | |
7938 | *p = i.tm.base_opcode; | |
7939 | ||
7940 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
f8a5c266 | 7941 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size); |
40fb9820 | 7942 | else if (cpu_arch_flags.bitfield.cpui386) |
f8a5c266 | 7943 | subtype = ENCODE_RELAX_STATE (COND_JUMP, size); |
29b0f896 | 7944 | else |
f8a5c266 | 7945 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, size); |
29b0f896 | 7946 | subtype |= code16; |
3e73aa7c | 7947 | |
29b0f896 AM |
7948 | sym = i.op[0].disps->X_add_symbol; |
7949 | off = i.op[0].disps->X_add_number; | |
3e73aa7c | 7950 | |
29b0f896 AM |
7951 | if (i.op[0].disps->X_op != O_constant |
7952 | && i.op[0].disps->X_op != O_symbol) | |
3e73aa7c | 7953 | { |
29b0f896 AM |
7954 | /* Handle complex expressions. */ |
7955 | sym = make_expr_symbol (i.op[0].disps); | |
7956 | off = 0; | |
7957 | } | |
3e73aa7c | 7958 | |
29b0f896 AM |
7959 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
7960 | Pass reloc in fr_var. */ | |
d258b828 | 7961 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); |
29b0f896 | 7962 | } |
3e73aa7c | 7963 | |
bd7ab16b L |
7964 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
7965 | /* Return TRUE iff PLT32 relocation should be used for branching to | |
7966 | symbol S. */ | |
7967 | ||
7968 | static bfd_boolean | |
7969 | need_plt32_p (symbolS *s) | |
7970 | { | |
7971 | /* PLT32 relocation is ELF only. */ | |
7972 | if (!IS_ELF) | |
7973 | return FALSE; | |
7974 | ||
a5def729 RO |
7975 | #ifdef TE_SOLARIS |
7976 | /* Don't emit PLT32 relocation on Solaris: neither native linker nor | |
7977 | krtld support it. */ | |
7978 | return FALSE; | |
7979 | #endif | |
7980 | ||
bd7ab16b L |
7981 | /* Since there is no need to prepare for PLT branch on x86-64, we |
7982 | can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can | |
7983 | be used as a marker for 32-bit PC-relative branches. */ | |
7984 | if (!object_64bit) | |
7985 | return FALSE; | |
7986 | ||
7987 | /* Weak or undefined symbol need PLT32 relocation. */ | |
7988 | if (S_IS_WEAK (s) || !S_IS_DEFINED (s)) | |
7989 | return TRUE; | |
7990 | ||
7991 | /* Non-global symbol doesn't need PLT32 relocation. */ | |
7992 | if (! S_IS_EXTERNAL (s)) | |
7993 | return FALSE; | |
7994 | ||
7995 | /* Other global symbols need PLT32 relocation. NB: Symbol with | |
7996 | non-default visibilities are treated as normal global symbol | |
7997 | so that PLT32 relocation can be used as a marker for 32-bit | |
7998 | PC-relative branches. It is useful for linker relaxation. */ | |
7999 | return TRUE; | |
8000 | } | |
8001 | #endif | |
8002 | ||
29b0f896 | 8003 | static void |
e3bb37b5 | 8004 | output_jump (void) |
29b0f896 AM |
8005 | { |
8006 | char *p; | |
8007 | int size; | |
3e02c1cc | 8008 | fixS *fixP; |
bd7ab16b | 8009 | bfd_reloc_code_real_type jump_reloc = i.reloc[0]; |
29b0f896 | 8010 | |
0cfa3eb3 | 8011 | if (i.tm.opcode_modifier.jump == JUMP_BYTE) |
29b0f896 AM |
8012 | { |
8013 | /* This is a loop or jecxz type instruction. */ | |
8014 | size = 1; | |
8015 | if (i.prefix[ADDR_PREFIX] != 0) | |
8016 | { | |
8017 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); | |
8018 | i.prefixes -= 1; | |
8019 | } | |
8020 | /* Pentium4 branch hints. */ | |
8021 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
8022 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
8023 | { | |
8024 | FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); | |
8025 | i.prefixes--; | |
3e73aa7c JH |
8026 | } |
8027 | } | |
29b0f896 AM |
8028 | else |
8029 | { | |
8030 | int code16; | |
3e73aa7c | 8031 | |
29b0f896 AM |
8032 | code16 = 0; |
8033 | if (flag_code == CODE_16BIT) | |
8034 | code16 = CODE16; | |
3e73aa7c | 8035 | |
29b0f896 AM |
8036 | if (i.prefix[DATA_PREFIX] != 0) |
8037 | { | |
8038 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); | |
8039 | i.prefixes -= 1; | |
376cd056 | 8040 | code16 ^= flip_code16(code16); |
29b0f896 | 8041 | } |
252b5132 | 8042 | |
29b0f896 AM |
8043 | size = 4; |
8044 | if (code16) | |
8045 | size = 2; | |
8046 | } | |
9fcc94b6 | 8047 | |
6cb0a70e JB |
8048 | /* BND prefixed jump. */ |
8049 | if (i.prefix[BND_PREFIX] != 0) | |
29b0f896 | 8050 | { |
6cb0a70e | 8051 | FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]); |
29b0f896 AM |
8052 | i.prefixes -= 1; |
8053 | } | |
252b5132 | 8054 | |
6cb0a70e | 8055 | if (i.prefix[REX_PREFIX] != 0) |
7e8b059b | 8056 | { |
6cb0a70e | 8057 | FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); |
7e8b059b L |
8058 | i.prefixes -= 1; |
8059 | } | |
8060 | ||
f2810fe0 JB |
8061 | if (i.prefixes != 0) |
8062 | as_warn (_("skipping prefixes on `%s'"), i.tm.name); | |
e0890092 | 8063 | |
42164a71 L |
8064 | p = frag_more (i.tm.opcode_length + size); |
8065 | switch (i.tm.opcode_length) | |
8066 | { | |
8067 | case 2: | |
8068 | *p++ = i.tm.base_opcode >> 8; | |
1a0670f3 | 8069 | /* Fall through. */ |
42164a71 L |
8070 | case 1: |
8071 | *p++ = i.tm.base_opcode; | |
8072 | break; | |
8073 | default: | |
8074 | abort (); | |
8075 | } | |
e0890092 | 8076 | |
bd7ab16b L |
8077 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8078 | if (size == 4 | |
8079 | && jump_reloc == NO_RELOC | |
8080 | && need_plt32_p (i.op[0].disps->X_add_symbol)) | |
8081 | jump_reloc = BFD_RELOC_X86_64_PLT32; | |
8082 | #endif | |
8083 | ||
8084 | jump_reloc = reloc (size, 1, 1, jump_reloc); | |
8085 | ||
3e02c1cc | 8086 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
bd7ab16b | 8087 | i.op[0].disps, 1, jump_reloc); |
3e02c1cc AM |
8088 | |
8089 | /* All jumps handled here are signed, but don't use a signed limit | |
8090 | check for 32 and 16 bit jumps as we want to allow wrap around at | |
8091 | 4G and 64k respectively. */ | |
8092 | if (size == 1) | |
8093 | fixP->fx_signed = 1; | |
29b0f896 | 8094 | } |
e0890092 | 8095 | |
29b0f896 | 8096 | static void |
e3bb37b5 | 8097 | output_interseg_jump (void) |
29b0f896 AM |
8098 | { |
8099 | char *p; | |
8100 | int size; | |
8101 | int prefix; | |
8102 | int code16; | |
252b5132 | 8103 | |
29b0f896 AM |
8104 | code16 = 0; |
8105 | if (flag_code == CODE_16BIT) | |
8106 | code16 = CODE16; | |
a217f122 | 8107 | |
29b0f896 AM |
8108 | prefix = 0; |
8109 | if (i.prefix[DATA_PREFIX] != 0) | |
8110 | { | |
8111 | prefix = 1; | |
8112 | i.prefixes -= 1; | |
8113 | code16 ^= CODE16; | |
8114 | } | |
6cb0a70e JB |
8115 | |
8116 | gas_assert (!i.prefix[REX_PREFIX]); | |
252b5132 | 8117 | |
29b0f896 AM |
8118 | size = 4; |
8119 | if (code16) | |
8120 | size = 2; | |
252b5132 | 8121 | |
f2810fe0 JB |
8122 | if (i.prefixes != 0) |
8123 | as_warn (_("skipping prefixes on `%s'"), i.tm.name); | |
252b5132 | 8124 | |
29b0f896 AM |
8125 | /* 1 opcode; 2 segment; offset */ |
8126 | p = frag_more (prefix + 1 + 2 + size); | |
3e73aa7c | 8127 | |
29b0f896 AM |
8128 | if (i.prefix[DATA_PREFIX] != 0) |
8129 | *p++ = DATA_PREFIX_OPCODE; | |
252b5132 | 8130 | |
29b0f896 AM |
8131 | if (i.prefix[REX_PREFIX] != 0) |
8132 | *p++ = i.prefix[REX_PREFIX]; | |
252b5132 | 8133 | |
29b0f896 AM |
8134 | *p++ = i.tm.base_opcode; |
8135 | if (i.op[1].imms->X_op == O_constant) | |
8136 | { | |
8137 | offsetT n = i.op[1].imms->X_add_number; | |
252b5132 | 8138 | |
29b0f896 AM |
8139 | if (size == 2 |
8140 | && !fits_in_unsigned_word (n) | |
8141 | && !fits_in_signed_word (n)) | |
8142 | { | |
8143 | as_bad (_("16-bit jump out of range")); | |
8144 | return; | |
8145 | } | |
8146 | md_number_to_chars (p, n, size); | |
8147 | } | |
8148 | else | |
8149 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
d258b828 | 8150 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); |
29b0f896 AM |
8151 | if (i.op[0].imms->X_op != O_constant) |
8152 | as_bad (_("can't handle non absolute segment in `%s'"), | |
8153 | i.tm.name); | |
8154 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); | |
8155 | } | |
a217f122 | 8156 | |
b4a3a7b4 L |
8157 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8158 | void | |
8159 | x86_cleanup (void) | |
8160 | { | |
8161 | char *p; | |
8162 | asection *seg = now_seg; | |
8163 | subsegT subseg = now_subseg; | |
8164 | asection *sec; | |
8165 | unsigned int alignment, align_size_1; | |
8166 | unsigned int isa_1_descsz, feature_2_descsz, descsz; | |
8167 | unsigned int isa_1_descsz_raw, feature_2_descsz_raw; | |
8168 | unsigned int padding; | |
8169 | ||
8170 | if (!IS_ELF || !x86_used_note) | |
8171 | return; | |
8172 | ||
b4a3a7b4 L |
8173 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X86; |
8174 | ||
8175 | /* The .note.gnu.property section layout: | |
8176 | ||
8177 | Field Length Contents | |
8178 | ---- ---- ---- | |
8179 | n_namsz 4 4 | |
8180 | n_descsz 4 The note descriptor size | |
8181 | n_type 4 NT_GNU_PROPERTY_TYPE_0 | |
8182 | n_name 4 "GNU" | |
8183 | n_desc n_descsz The program property array | |
8184 | .... .... .... | |
8185 | */ | |
8186 | ||
8187 | /* Create the .note.gnu.property section. */ | |
8188 | sec = subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME, 0); | |
fd361982 | 8189 | bfd_set_section_flags (sec, |
b4a3a7b4 L |
8190 | (SEC_ALLOC |
8191 | | SEC_LOAD | |
8192 | | SEC_DATA | |
8193 | | SEC_HAS_CONTENTS | |
8194 | | SEC_READONLY)); | |
8195 | ||
8196 | if (get_elf_backend_data (stdoutput)->s->elfclass == ELFCLASS64) | |
8197 | { | |
8198 | align_size_1 = 7; | |
8199 | alignment = 3; | |
8200 | } | |
8201 | else | |
8202 | { | |
8203 | align_size_1 = 3; | |
8204 | alignment = 2; | |
8205 | } | |
8206 | ||
fd361982 | 8207 | bfd_set_section_alignment (sec, alignment); |
b4a3a7b4 L |
8208 | elf_section_type (sec) = SHT_NOTE; |
8209 | ||
8210 | /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size | |
8211 | + 4-byte data */ | |
8212 | isa_1_descsz_raw = 4 + 4 + 4; | |
8213 | /* Align GNU_PROPERTY_X86_ISA_1_USED. */ | |
8214 | isa_1_descsz = (isa_1_descsz_raw + align_size_1) & ~align_size_1; | |
8215 | ||
8216 | feature_2_descsz_raw = isa_1_descsz; | |
8217 | /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size | |
8218 | + 4-byte data */ | |
8219 | feature_2_descsz_raw += 4 + 4 + 4; | |
8220 | /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */ | |
8221 | feature_2_descsz = ((feature_2_descsz_raw + align_size_1) | |
8222 | & ~align_size_1); | |
8223 | ||
8224 | descsz = feature_2_descsz; | |
8225 | /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */ | |
8226 | p = frag_more (4 + 4 + 4 + 4 + descsz); | |
8227 | ||
8228 | /* Write n_namsz. */ | |
8229 | md_number_to_chars (p, (valueT) 4, 4); | |
8230 | ||
8231 | /* Write n_descsz. */ | |
8232 | md_number_to_chars (p + 4, (valueT) descsz, 4); | |
8233 | ||
8234 | /* Write n_type. */ | |
8235 | md_number_to_chars (p + 4 * 2, (valueT) NT_GNU_PROPERTY_TYPE_0, 4); | |
8236 | ||
8237 | /* Write n_name. */ | |
8238 | memcpy (p + 4 * 3, "GNU", 4); | |
8239 | ||
8240 | /* Write 4-byte type. */ | |
8241 | md_number_to_chars (p + 4 * 4, | |
8242 | (valueT) GNU_PROPERTY_X86_ISA_1_USED, 4); | |
8243 | ||
8244 | /* Write 4-byte data size. */ | |
8245 | md_number_to_chars (p + 4 * 5, (valueT) 4, 4); | |
8246 | ||
8247 | /* Write 4-byte data. */ | |
8248 | md_number_to_chars (p + 4 * 6, (valueT) x86_isa_1_used, 4); | |
8249 | ||
8250 | /* Zero out paddings. */ | |
8251 | padding = isa_1_descsz - isa_1_descsz_raw; | |
8252 | if (padding) | |
8253 | memset (p + 4 * 7, 0, padding); | |
8254 | ||
8255 | /* Write 4-byte type. */ | |
8256 | md_number_to_chars (p + isa_1_descsz + 4 * 4, | |
8257 | (valueT) GNU_PROPERTY_X86_FEATURE_2_USED, 4); | |
8258 | ||
8259 | /* Write 4-byte data size. */ | |
8260 | md_number_to_chars (p + isa_1_descsz + 4 * 5, (valueT) 4, 4); | |
8261 | ||
8262 | /* Write 4-byte data. */ | |
8263 | md_number_to_chars (p + isa_1_descsz + 4 * 6, | |
8264 | (valueT) x86_feature_2_used, 4); | |
8265 | ||
8266 | /* Zero out paddings. */ | |
8267 | padding = feature_2_descsz - feature_2_descsz_raw; | |
8268 | if (padding) | |
8269 | memset (p + isa_1_descsz + 4 * 7, 0, padding); | |
8270 | ||
8271 | /* We probably can't restore the current segment, for there likely | |
8272 | isn't one yet... */ | |
8273 | if (seg && subseg) | |
8274 | subseg_set (seg, subseg); | |
8275 | } | |
8276 | #endif | |
8277 | ||
9c33702b JB |
8278 | static unsigned int |
8279 | encoding_length (const fragS *start_frag, offsetT start_off, | |
8280 | const char *frag_now_ptr) | |
8281 | { | |
8282 | unsigned int len = 0; | |
8283 | ||
8284 | if (start_frag != frag_now) | |
8285 | { | |
8286 | const fragS *fr = start_frag; | |
8287 | ||
8288 | do { | |
8289 | len += fr->fr_fix; | |
8290 | fr = fr->fr_next; | |
8291 | } while (fr && fr != frag_now); | |
8292 | } | |
8293 | ||
8294 | return len - start_off + (frag_now_ptr - frag_now->fr_literal); | |
8295 | } | |
8296 | ||
e379e5f3 L |
8297 | /* Return 1 for test, and, cmp, add, sub, inc and dec which may |
8298 | be macro-fused with conditional jumps. */ | |
8299 | ||
8300 | static int | |
8301 | maybe_fused_with_jcc_p (void) | |
8302 | { | |
8303 | /* No RIP address. */ | |
8304 | if (i.base_reg && i.base_reg->reg_num == RegIP) | |
8305 | return 0; | |
8306 | ||
8307 | /* No VEX/EVEX encoding. */ | |
8308 | if (is_any_vex_encoding (&i.tm)) | |
8309 | return 0; | |
8310 | ||
8311 | /* and, add, sub with destination register. */ | |
8312 | if ((i.tm.base_opcode >= 0x20 && i.tm.base_opcode <= 0x25) | |
8313 | || i.tm.base_opcode <= 5 | |
8314 | || (i.tm.base_opcode >= 0x28 && i.tm.base_opcode <= 0x2d) | |
8315 | || ((i.tm.base_opcode | 3) == 0x83 | |
8316 | && ((i.tm.extension_opcode | 1) == 0x5 | |
8317 | || i.tm.extension_opcode == 0x0))) | |
8318 | return (i.types[1].bitfield.class == Reg | |
8319 | || i.types[1].bitfield.instance == Accum); | |
8320 | ||
8321 | /* test, cmp with any register. */ | |
8322 | if ((i.tm.base_opcode | 1) == 0x85 | |
8323 | || (i.tm.base_opcode | 1) == 0xa9 | |
8324 | || ((i.tm.base_opcode | 1) == 0xf7 | |
8325 | && i.tm.extension_opcode == 0) | |
8326 | || (i.tm.base_opcode >= 0x38 && i.tm.base_opcode <= 0x3d) | |
8327 | || ((i.tm.base_opcode | 3) == 0x83 | |
8328 | && (i.tm.extension_opcode == 0x7))) | |
8329 | return (i.types[0].bitfield.class == Reg | |
8330 | || i.types[0].bitfield.instance == Accum | |
8331 | || i.types[1].bitfield.class == Reg | |
8332 | || i.types[1].bitfield.instance == Accum); | |
8333 | ||
8334 | /* inc, dec with any register. */ | |
8335 | if ((i.tm.cpu_flags.bitfield.cpuno64 | |
8336 | && (i.tm.base_opcode | 0xf) == 0x4f) | |
8337 | || ((i.tm.base_opcode | 1) == 0xff | |
8338 | && i.tm.extension_opcode <= 0x1)) | |
8339 | return (i.types[0].bitfield.class == Reg | |
8340 | || i.types[0].bitfield.instance == Accum); | |
8341 | ||
8342 | return 0; | |
8343 | } | |
8344 | ||
8345 | /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */ | |
8346 | ||
8347 | static int | |
8348 | add_fused_jcc_padding_frag_p (void) | |
8349 | { | |
8350 | /* NB: Don't work with COND_JUMP86 without i386. */ | |
8351 | if (!align_branch_power | |
8352 | || now_seg == absolute_section | |
8353 | || !cpu_arch_flags.bitfield.cpui386 | |
8354 | || !(align_branch & align_branch_fused_bit)) | |
8355 | return 0; | |
8356 | ||
8357 | if (maybe_fused_with_jcc_p ()) | |
8358 | { | |
8359 | if (last_insn.kind == last_insn_other | |
8360 | || last_insn.seg != now_seg) | |
8361 | return 1; | |
8362 | if (flag_debug) | |
8363 | as_warn_where (last_insn.file, last_insn.line, | |
8364 | _("`%s` skips -malign-branch-boundary on `%s`"), | |
8365 | last_insn.name, i.tm.name); | |
8366 | } | |
8367 | ||
8368 | return 0; | |
8369 | } | |
8370 | ||
8371 | /* Return 1 if a BRANCH_PREFIX frag should be generated. */ | |
8372 | ||
8373 | static int | |
8374 | add_branch_prefix_frag_p (void) | |
8375 | { | |
8376 | /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix | |
8377 | to PadLock instructions since they include prefixes in opcode. */ | |
8378 | if (!align_branch_power | |
8379 | || !align_branch_prefix_size | |
8380 | || now_seg == absolute_section | |
8381 | || i.tm.cpu_flags.bitfield.cpupadlock | |
8382 | || !cpu_arch_flags.bitfield.cpui386) | |
8383 | return 0; | |
8384 | ||
8385 | /* Don't add prefix if it is a prefix or there is no operand in case | |
8386 | that segment prefix is special. */ | |
8387 | if (!i.operands || i.tm.opcode_modifier.isprefix) | |
8388 | return 0; | |
8389 | ||
8390 | if (last_insn.kind == last_insn_other | |
8391 | || last_insn.seg != now_seg) | |
8392 | return 1; | |
8393 | ||
8394 | if (flag_debug) | |
8395 | as_warn_where (last_insn.file, last_insn.line, | |
8396 | _("`%s` skips -malign-branch-boundary on `%s`"), | |
8397 | last_insn.name, i.tm.name); | |
8398 | ||
8399 | return 0; | |
8400 | } | |
8401 | ||
8402 | /* Return 1 if a BRANCH_PADDING frag should be generated. */ | |
8403 | ||
8404 | static int | |
8405 | add_branch_padding_frag_p (enum align_branch_kind *branch_p) | |
8406 | { | |
8407 | int add_padding; | |
8408 | ||
8409 | /* NB: Don't work with COND_JUMP86 without i386. */ | |
8410 | if (!align_branch_power | |
8411 | || now_seg == absolute_section | |
8412 | || !cpu_arch_flags.bitfield.cpui386) | |
8413 | return 0; | |
8414 | ||
8415 | add_padding = 0; | |
8416 | ||
8417 | /* Check for jcc and direct jmp. */ | |
8418 | if (i.tm.opcode_modifier.jump == JUMP) | |
8419 | { | |
8420 | if (i.tm.base_opcode == JUMP_PC_RELATIVE) | |
8421 | { | |
8422 | *branch_p = align_branch_jmp; | |
8423 | add_padding = align_branch & align_branch_jmp_bit; | |
8424 | } | |
8425 | else | |
8426 | { | |
8427 | *branch_p = align_branch_jcc; | |
8428 | if ((align_branch & align_branch_jcc_bit)) | |
8429 | add_padding = 1; | |
8430 | } | |
8431 | } | |
8432 | else if (is_any_vex_encoding (&i.tm)) | |
8433 | return 0; | |
8434 | else if ((i.tm.base_opcode | 1) == 0xc3) | |
8435 | { | |
8436 | /* Near ret. */ | |
8437 | *branch_p = align_branch_ret; | |
8438 | if ((align_branch & align_branch_ret_bit)) | |
8439 | add_padding = 1; | |
8440 | } | |
8441 | else | |
8442 | { | |
8443 | /* Check for indirect jmp, direct and indirect calls. */ | |
8444 | if (i.tm.base_opcode == 0xe8) | |
8445 | { | |
8446 | /* Direct call. */ | |
8447 | *branch_p = align_branch_call; | |
8448 | if ((align_branch & align_branch_call_bit)) | |
8449 | add_padding = 1; | |
8450 | } | |
8451 | else if (i.tm.base_opcode == 0xff | |
8452 | && (i.tm.extension_opcode == 2 | |
8453 | || i.tm.extension_opcode == 4)) | |
8454 | { | |
8455 | /* Indirect call and jmp. */ | |
8456 | *branch_p = align_branch_indirect; | |
8457 | if ((align_branch & align_branch_indirect_bit)) | |
8458 | add_padding = 1; | |
8459 | } | |
8460 | ||
8461 | if (add_padding | |
8462 | && i.disp_operands | |
8463 | && tls_get_addr | |
8464 | && (i.op[0].disps->X_op == O_symbol | |
8465 | || (i.op[0].disps->X_op == O_subtract | |
8466 | && i.op[0].disps->X_op_symbol == GOT_symbol))) | |
8467 | { | |
8468 | symbolS *s = i.op[0].disps->X_add_symbol; | |
8469 | /* No padding to call to global or undefined tls_get_addr. */ | |
8470 | if ((S_IS_EXTERNAL (s) || !S_IS_DEFINED (s)) | |
8471 | && strcmp (S_GET_NAME (s), tls_get_addr) == 0) | |
8472 | return 0; | |
8473 | } | |
8474 | } | |
8475 | ||
8476 | if (add_padding | |
8477 | && last_insn.kind != last_insn_other | |
8478 | && last_insn.seg == now_seg) | |
8479 | { | |
8480 | if (flag_debug) | |
8481 | as_warn_where (last_insn.file, last_insn.line, | |
8482 | _("`%s` skips -malign-branch-boundary on `%s`"), | |
8483 | last_insn.name, i.tm.name); | |
8484 | return 0; | |
8485 | } | |
8486 | ||
8487 | return add_padding; | |
8488 | } | |
8489 | ||
29b0f896 | 8490 | static void |
e3bb37b5 | 8491 | output_insn (void) |
29b0f896 | 8492 | { |
2bbd9c25 JJ |
8493 | fragS *insn_start_frag; |
8494 | offsetT insn_start_off; | |
e379e5f3 L |
8495 | fragS *fragP = NULL; |
8496 | enum align_branch_kind branch = align_branch_none; | |
2bbd9c25 | 8497 | |
b4a3a7b4 L |
8498 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8499 | if (IS_ELF && x86_used_note) | |
8500 | { | |
8501 | if (i.tm.cpu_flags.bitfield.cpucmov) | |
8502 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_CMOV; | |
8503 | if (i.tm.cpu_flags.bitfield.cpusse) | |
8504 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE; | |
8505 | if (i.tm.cpu_flags.bitfield.cpusse2) | |
8506 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE2; | |
8507 | if (i.tm.cpu_flags.bitfield.cpusse3) | |
8508 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE3; | |
8509 | if (i.tm.cpu_flags.bitfield.cpussse3) | |
8510 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSSE3; | |
8511 | if (i.tm.cpu_flags.bitfield.cpusse4_1) | |
8512 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_1; | |
8513 | if (i.tm.cpu_flags.bitfield.cpusse4_2) | |
8514 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_2; | |
8515 | if (i.tm.cpu_flags.bitfield.cpuavx) | |
8516 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX; | |
8517 | if (i.tm.cpu_flags.bitfield.cpuavx2) | |
8518 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX2; | |
8519 | if (i.tm.cpu_flags.bitfield.cpufma) | |
8520 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_FMA; | |
8521 | if (i.tm.cpu_flags.bitfield.cpuavx512f) | |
8522 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512F; | |
8523 | if (i.tm.cpu_flags.bitfield.cpuavx512cd) | |
8524 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512CD; | |
8525 | if (i.tm.cpu_flags.bitfield.cpuavx512er) | |
8526 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512ER; | |
8527 | if (i.tm.cpu_flags.bitfield.cpuavx512pf) | |
8528 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512PF; | |
8529 | if (i.tm.cpu_flags.bitfield.cpuavx512vl) | |
8530 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512VL; | |
8531 | if (i.tm.cpu_flags.bitfield.cpuavx512dq) | |
8532 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512DQ; | |
8533 | if (i.tm.cpu_flags.bitfield.cpuavx512bw) | |
8534 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512BW; | |
8535 | if (i.tm.cpu_flags.bitfield.cpuavx512_4fmaps) | |
8536 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS; | |
8537 | if (i.tm.cpu_flags.bitfield.cpuavx512_4vnniw) | |
8538 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW; | |
8539 | if (i.tm.cpu_flags.bitfield.cpuavx512_bitalg) | |
8540 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG; | |
8541 | if (i.tm.cpu_flags.bitfield.cpuavx512ifma) | |
8542 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA; | |
8543 | if (i.tm.cpu_flags.bitfield.cpuavx512vbmi) | |
8544 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI; | |
8545 | if (i.tm.cpu_flags.bitfield.cpuavx512_vbmi2) | |
8546 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2; | |
8547 | if (i.tm.cpu_flags.bitfield.cpuavx512_vnni) | |
8548 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI; | |
462cac58 L |
8549 | if (i.tm.cpu_flags.bitfield.cpuavx512_bf16) |
8550 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_BF16; | |
b4a3a7b4 L |
8551 | |
8552 | if (i.tm.cpu_flags.bitfield.cpu8087 | |
8553 | || i.tm.cpu_flags.bitfield.cpu287 | |
8554 | || i.tm.cpu_flags.bitfield.cpu387 | |
8555 | || i.tm.cpu_flags.bitfield.cpu687 | |
8556 | || i.tm.cpu_flags.bitfield.cpufisttp) | |
8557 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X87; | |
319ff62c JB |
8558 | if (i.has_regmmx |
8559 | || i.tm.base_opcode == 0xf77 /* emms */ | |
8560 | || i.tm.base_opcode == 0xf0e /* femms */) | |
b4a3a7b4 L |
8561 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MMX; |
8562 | if (i.has_regxmm) | |
8563 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XMM; | |
8564 | if (i.has_regymm) | |
8565 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_YMM; | |
8566 | if (i.has_regzmm) | |
8567 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_ZMM; | |
8568 | if (i.tm.cpu_flags.bitfield.cpufxsr) | |
8569 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_FXSR; | |
8570 | if (i.tm.cpu_flags.bitfield.cpuxsave) | |
8571 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVE; | |
8572 | if (i.tm.cpu_flags.bitfield.cpuxsaveopt) | |
8573 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT; | |
8574 | if (i.tm.cpu_flags.bitfield.cpuxsavec) | |
8575 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEC; | |
8576 | } | |
8577 | #endif | |
8578 | ||
29b0f896 AM |
8579 | /* Tie dwarf2 debug info to the address at the start of the insn. |
8580 | We can't do this after the insn has been output as the current | |
8581 | frag may have been closed off. eg. by frag_var. */ | |
8582 | dwarf2_emit_insn (0); | |
8583 | ||
2bbd9c25 JJ |
8584 | insn_start_frag = frag_now; |
8585 | insn_start_off = frag_now_fix (); | |
8586 | ||
e379e5f3 L |
8587 | if (add_branch_padding_frag_p (&branch)) |
8588 | { | |
8589 | char *p; | |
8590 | /* Branch can be 8 bytes. Leave some room for prefixes. */ | |
8591 | unsigned int max_branch_padding_size = 14; | |
8592 | ||
8593 | /* Align section to boundary. */ | |
8594 | record_alignment (now_seg, align_branch_power); | |
8595 | ||
8596 | /* Make room for padding. */ | |
8597 | frag_grow (max_branch_padding_size); | |
8598 | ||
8599 | /* Start of the padding. */ | |
8600 | p = frag_more (0); | |
8601 | ||
8602 | fragP = frag_now; | |
8603 | ||
8604 | frag_var (rs_machine_dependent, max_branch_padding_size, 0, | |
8605 | ENCODE_RELAX_STATE (BRANCH_PADDING, 0), | |
8606 | NULL, 0, p); | |
8607 | ||
8608 | fragP->tc_frag_data.branch_type = branch; | |
8609 | fragP->tc_frag_data.max_bytes = max_branch_padding_size; | |
8610 | } | |
8611 | ||
29b0f896 | 8612 | /* Output jumps. */ |
0cfa3eb3 | 8613 | if (i.tm.opcode_modifier.jump == JUMP) |
29b0f896 | 8614 | output_branch (); |
0cfa3eb3 JB |
8615 | else if (i.tm.opcode_modifier.jump == JUMP_BYTE |
8616 | || i.tm.opcode_modifier.jump == JUMP_DWORD) | |
29b0f896 | 8617 | output_jump (); |
0cfa3eb3 | 8618 | else if (i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT) |
29b0f896 AM |
8619 | output_interseg_jump (); |
8620 | else | |
8621 | { | |
8622 | /* Output normal instructions here. */ | |
8623 | char *p; | |
8624 | unsigned char *q; | |
47465058 | 8625 | unsigned int j; |
331d2d0d | 8626 | unsigned int prefix; |
4dffcebc | 8627 | |
e4e00185 | 8628 | if (avoid_fence |
c3949f43 JB |
8629 | && (i.tm.base_opcode == 0xfaee8 |
8630 | || i.tm.base_opcode == 0xfaef0 | |
8631 | || i.tm.base_opcode == 0xfaef8)) | |
e4e00185 AS |
8632 | { |
8633 | /* Encode lfence, mfence, and sfence as | |
8634 | f0 83 04 24 00 lock addl $0x0, (%{re}sp). */ | |
8635 | offsetT val = 0x240483f0ULL; | |
8636 | p = frag_more (5); | |
8637 | md_number_to_chars (p, val, 5); | |
8638 | return; | |
8639 | } | |
8640 | ||
d022bddd IT |
8641 | /* Some processors fail on LOCK prefix. This options makes |
8642 | assembler ignore LOCK prefix and serves as a workaround. */ | |
8643 | if (omit_lock_prefix) | |
8644 | { | |
8645 | if (i.tm.base_opcode == LOCK_PREFIX_OPCODE) | |
8646 | return; | |
8647 | i.prefix[LOCK_PREFIX] = 0; | |
8648 | } | |
8649 | ||
e379e5f3 L |
8650 | if (branch) |
8651 | /* Skip if this is a branch. */ | |
8652 | ; | |
8653 | else if (add_fused_jcc_padding_frag_p ()) | |
8654 | { | |
8655 | /* Make room for padding. */ | |
8656 | frag_grow (MAX_FUSED_JCC_PADDING_SIZE); | |
8657 | p = frag_more (0); | |
8658 | ||
8659 | fragP = frag_now; | |
8660 | ||
8661 | frag_var (rs_machine_dependent, MAX_FUSED_JCC_PADDING_SIZE, 0, | |
8662 | ENCODE_RELAX_STATE (FUSED_JCC_PADDING, 0), | |
8663 | NULL, 0, p); | |
8664 | ||
8665 | fragP->tc_frag_data.branch_type = align_branch_fused; | |
8666 | fragP->tc_frag_data.max_bytes = MAX_FUSED_JCC_PADDING_SIZE; | |
8667 | } | |
8668 | else if (add_branch_prefix_frag_p ()) | |
8669 | { | |
8670 | unsigned int max_prefix_size = align_branch_prefix_size; | |
8671 | ||
8672 | /* Make room for padding. */ | |
8673 | frag_grow (max_prefix_size); | |
8674 | p = frag_more (0); | |
8675 | ||
8676 | fragP = frag_now; | |
8677 | ||
8678 | frag_var (rs_machine_dependent, max_prefix_size, 0, | |
8679 | ENCODE_RELAX_STATE (BRANCH_PREFIX, 0), | |
8680 | NULL, 0, p); | |
8681 | ||
8682 | fragP->tc_frag_data.max_bytes = max_prefix_size; | |
8683 | } | |
8684 | ||
43234a1e L |
8685 | /* Since the VEX/EVEX prefix contains the implicit prefix, we |
8686 | don't need the explicit prefix. */ | |
8687 | if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex) | |
bc4bd9ab | 8688 | { |
c0f3af97 | 8689 | switch (i.tm.opcode_length) |
bc4bd9ab | 8690 | { |
c0f3af97 L |
8691 | case 3: |
8692 | if (i.tm.base_opcode & 0xff000000) | |
4dffcebc | 8693 | { |
c0f3af97 | 8694 | prefix = (i.tm.base_opcode >> 24) & 0xff; |
c3949f43 JB |
8695 | if (!i.tm.cpu_flags.bitfield.cpupadlock |
8696 | || prefix != REPE_PREFIX_OPCODE | |
8697 | || (i.prefix[REP_PREFIX] != REPE_PREFIX_OPCODE)) | |
8698 | add_prefix (prefix); | |
c0f3af97 L |
8699 | } |
8700 | break; | |
8701 | case 2: | |
8702 | if ((i.tm.base_opcode & 0xff0000) != 0) | |
8703 | { | |
8704 | prefix = (i.tm.base_opcode >> 16) & 0xff; | |
c3949f43 | 8705 | add_prefix (prefix); |
4dffcebc | 8706 | } |
c0f3af97 L |
8707 | break; |
8708 | case 1: | |
8709 | break; | |
390c91cf L |
8710 | case 0: |
8711 | /* Check for pseudo prefixes. */ | |
8712 | as_bad_where (insn_start_frag->fr_file, | |
8713 | insn_start_frag->fr_line, | |
8714 | _("pseudo prefix without instruction")); | |
8715 | return; | |
c0f3af97 L |
8716 | default: |
8717 | abort (); | |
bc4bd9ab | 8718 | } |
c0f3af97 | 8719 | |
6d19a37a | 8720 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
cf61b747 L |
8721 | /* For x32, add a dummy REX_OPCODE prefix for mov/add with |
8722 | R_X86_64_GOTTPOFF relocation so that linker can safely | |
8723 | perform IE->LE optimization. */ | |
8724 | if (x86_elf_abi == X86_64_X32_ABI | |
8725 | && i.operands == 2 | |
8726 | && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF | |
8727 | && i.prefix[REX_PREFIX] == 0) | |
8728 | add_prefix (REX_OPCODE); | |
6d19a37a | 8729 | #endif |
cf61b747 | 8730 | |
c0f3af97 L |
8731 | /* The prefix bytes. */ |
8732 | for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) | |
8733 | if (*q) | |
8734 | FRAG_APPEND_1_CHAR (*q); | |
0f10071e | 8735 | } |
ae5c1c7b | 8736 | else |
c0f3af97 L |
8737 | { |
8738 | for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++) | |
8739 | if (*q) | |
8740 | switch (j) | |
8741 | { | |
8742 | case REX_PREFIX: | |
8743 | /* REX byte is encoded in VEX prefix. */ | |
8744 | break; | |
8745 | case SEG_PREFIX: | |
8746 | case ADDR_PREFIX: | |
8747 | FRAG_APPEND_1_CHAR (*q); | |
8748 | break; | |
8749 | default: | |
8750 | /* There should be no other prefixes for instructions | |
8751 | with VEX prefix. */ | |
8752 | abort (); | |
8753 | } | |
8754 | ||
43234a1e L |
8755 | /* For EVEX instructions i.vrex should become 0 after |
8756 | build_evex_prefix. For VEX instructions upper 16 registers | |
8757 | aren't available, so VREX should be 0. */ | |
8758 | if (i.vrex) | |
8759 | abort (); | |
c0f3af97 L |
8760 | /* Now the VEX prefix. */ |
8761 | p = frag_more (i.vex.length); | |
8762 | for (j = 0; j < i.vex.length; j++) | |
8763 | p[j] = i.vex.bytes[j]; | |
8764 | } | |
252b5132 | 8765 | |
29b0f896 | 8766 | /* Now the opcode; be careful about word order here! */ |
4dffcebc | 8767 | if (i.tm.opcode_length == 1) |
29b0f896 AM |
8768 | { |
8769 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
8770 | } | |
8771 | else | |
8772 | { | |
4dffcebc | 8773 | switch (i.tm.opcode_length) |
331d2d0d | 8774 | { |
43234a1e L |
8775 | case 4: |
8776 | p = frag_more (4); | |
8777 | *p++ = (i.tm.base_opcode >> 24) & 0xff; | |
8778 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
8779 | break; | |
4dffcebc | 8780 | case 3: |
331d2d0d L |
8781 | p = frag_more (3); |
8782 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
4dffcebc L |
8783 | break; |
8784 | case 2: | |
8785 | p = frag_more (2); | |
8786 | break; | |
8787 | default: | |
8788 | abort (); | |
8789 | break; | |
331d2d0d | 8790 | } |
0f10071e | 8791 | |
29b0f896 AM |
8792 | /* Put out high byte first: can't use md_number_to_chars! */ |
8793 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
8794 | *p = i.tm.base_opcode & 0xff; | |
8795 | } | |
3e73aa7c | 8796 | |
29b0f896 | 8797 | /* Now the modrm byte and sib byte (if present). */ |
40fb9820 | 8798 | if (i.tm.opcode_modifier.modrm) |
29b0f896 | 8799 | { |
4a3523fa L |
8800 | FRAG_APPEND_1_CHAR ((i.rm.regmem << 0 |
8801 | | i.rm.reg << 3 | |
8802 | | i.rm.mode << 6)); | |
29b0f896 AM |
8803 | /* If i.rm.regmem == ESP (4) |
8804 | && i.rm.mode != (Register mode) | |
8805 | && not 16 bit | |
8806 | ==> need second modrm byte. */ | |
8807 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
8808 | && i.rm.mode != 3 | |
dc821c5f | 8809 | && !(i.base_reg && i.base_reg->reg_type.bitfield.word)) |
4a3523fa L |
8810 | FRAG_APPEND_1_CHAR ((i.sib.base << 0 |
8811 | | i.sib.index << 3 | |
8812 | | i.sib.scale << 6)); | |
29b0f896 | 8813 | } |
3e73aa7c | 8814 | |
29b0f896 | 8815 | if (i.disp_operands) |
2bbd9c25 | 8816 | output_disp (insn_start_frag, insn_start_off); |
3e73aa7c | 8817 | |
29b0f896 | 8818 | if (i.imm_operands) |
2bbd9c25 | 8819 | output_imm (insn_start_frag, insn_start_off); |
9c33702b JB |
8820 | |
8821 | /* | |
8822 | * frag_now_fix () returning plain abs_section_offset when we're in the | |
8823 | * absolute section, and abs_section_offset not getting updated as data | |
8824 | * gets added to the frag breaks the logic below. | |
8825 | */ | |
8826 | if (now_seg != absolute_section) | |
8827 | { | |
8828 | j = encoding_length (insn_start_frag, insn_start_off, frag_more (0)); | |
8829 | if (j > 15) | |
8830 | as_warn (_("instruction length of %u bytes exceeds the limit of 15"), | |
8831 | j); | |
e379e5f3 L |
8832 | else if (fragP) |
8833 | { | |
8834 | /* NB: Don't add prefix with GOTPC relocation since | |
8835 | output_disp() above depends on the fixed encoding | |
8836 | length. Can't add prefix with TLS relocation since | |
8837 | it breaks TLS linker optimization. */ | |
8838 | unsigned int max = i.has_gotpc_tls_reloc ? 0 : 15 - j; | |
8839 | /* Prefix count on the current instruction. */ | |
8840 | unsigned int count = i.vex.length; | |
8841 | unsigned int k; | |
8842 | for (k = 0; k < ARRAY_SIZE (i.prefix); k++) | |
8843 | /* REX byte is encoded in VEX/EVEX prefix. */ | |
8844 | if (i.prefix[k] && (k != REX_PREFIX || !i.vex.length)) | |
8845 | count++; | |
8846 | ||
8847 | /* Count prefixes for extended opcode maps. */ | |
8848 | if (!i.vex.length) | |
8849 | switch (i.tm.opcode_length) | |
8850 | { | |
8851 | case 3: | |
8852 | if (((i.tm.base_opcode >> 16) & 0xff) == 0xf) | |
8853 | { | |
8854 | count++; | |
8855 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
8856 | { | |
8857 | case 0x38: | |
8858 | case 0x3a: | |
8859 | count++; | |
8860 | break; | |
8861 | default: | |
8862 | break; | |
8863 | } | |
8864 | } | |
8865 | break; | |
8866 | case 2: | |
8867 | if (((i.tm.base_opcode >> 8) & 0xff) == 0xf) | |
8868 | count++; | |
8869 | break; | |
8870 | case 1: | |
8871 | break; | |
8872 | default: | |
8873 | abort (); | |
8874 | } | |
8875 | ||
8876 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
8877 | == BRANCH_PREFIX) | |
8878 | { | |
8879 | /* Set the maximum prefix size in BRANCH_PREFIX | |
8880 | frag. */ | |
8881 | if (fragP->tc_frag_data.max_bytes > max) | |
8882 | fragP->tc_frag_data.max_bytes = max; | |
8883 | if (fragP->tc_frag_data.max_bytes > count) | |
8884 | fragP->tc_frag_data.max_bytes -= count; | |
8885 | else | |
8886 | fragP->tc_frag_data.max_bytes = 0; | |
8887 | } | |
8888 | else | |
8889 | { | |
8890 | /* Remember the maximum prefix size in FUSED_JCC_PADDING | |
8891 | frag. */ | |
8892 | unsigned int max_prefix_size; | |
8893 | if (align_branch_prefix_size > max) | |
8894 | max_prefix_size = max; | |
8895 | else | |
8896 | max_prefix_size = align_branch_prefix_size; | |
8897 | if (max_prefix_size > count) | |
8898 | fragP->tc_frag_data.max_prefix_length | |
8899 | = max_prefix_size - count; | |
8900 | } | |
8901 | ||
8902 | /* Use existing segment prefix if possible. Use CS | |
8903 | segment prefix in 64-bit mode. In 32-bit mode, use SS | |
8904 | segment prefix with ESP/EBP base register and use DS | |
8905 | segment prefix without ESP/EBP base register. */ | |
8906 | if (i.prefix[SEG_PREFIX]) | |
8907 | fragP->tc_frag_data.default_prefix = i.prefix[SEG_PREFIX]; | |
8908 | else if (flag_code == CODE_64BIT) | |
8909 | fragP->tc_frag_data.default_prefix = CS_PREFIX_OPCODE; | |
8910 | else if (i.base_reg | |
8911 | && (i.base_reg->reg_num == 4 | |
8912 | || i.base_reg->reg_num == 5)) | |
8913 | fragP->tc_frag_data.default_prefix = SS_PREFIX_OPCODE; | |
8914 | else | |
8915 | fragP->tc_frag_data.default_prefix = DS_PREFIX_OPCODE; | |
8916 | } | |
9c33702b | 8917 | } |
29b0f896 | 8918 | } |
252b5132 | 8919 | |
e379e5f3 L |
8920 | /* NB: Don't work with COND_JUMP86 without i386. */ |
8921 | if (align_branch_power | |
8922 | && now_seg != absolute_section | |
8923 | && cpu_arch_flags.bitfield.cpui386) | |
8924 | { | |
8925 | /* Terminate each frag so that we can add prefix and check for | |
8926 | fused jcc. */ | |
8927 | frag_wane (frag_now); | |
8928 | frag_new (0); | |
8929 | } | |
8930 | ||
29b0f896 AM |
8931 | #ifdef DEBUG386 |
8932 | if (flag_debug) | |
8933 | { | |
7b81dfbb | 8934 | pi ("" /*line*/, &i); |
29b0f896 AM |
8935 | } |
8936 | #endif /* DEBUG386 */ | |
8937 | } | |
252b5132 | 8938 | |
e205caa7 L |
8939 | /* Return the size of the displacement operand N. */ |
8940 | ||
8941 | static int | |
8942 | disp_size (unsigned int n) | |
8943 | { | |
8944 | int size = 4; | |
43234a1e | 8945 | |
b5014f7a | 8946 | if (i.types[n].bitfield.disp64) |
40fb9820 L |
8947 | size = 8; |
8948 | else if (i.types[n].bitfield.disp8) | |
8949 | size = 1; | |
8950 | else if (i.types[n].bitfield.disp16) | |
8951 | size = 2; | |
e205caa7 L |
8952 | return size; |
8953 | } | |
8954 | ||
8955 | /* Return the size of the immediate operand N. */ | |
8956 | ||
8957 | static int | |
8958 | imm_size (unsigned int n) | |
8959 | { | |
8960 | int size = 4; | |
40fb9820 L |
8961 | if (i.types[n].bitfield.imm64) |
8962 | size = 8; | |
8963 | else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) | |
8964 | size = 1; | |
8965 | else if (i.types[n].bitfield.imm16) | |
8966 | size = 2; | |
e205caa7 L |
8967 | return size; |
8968 | } | |
8969 | ||
29b0f896 | 8970 | static void |
64e74474 | 8971 | output_disp (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
8972 | { |
8973 | char *p; | |
8974 | unsigned int n; | |
252b5132 | 8975 | |
29b0f896 AM |
8976 | for (n = 0; n < i.operands; n++) |
8977 | { | |
b5014f7a | 8978 | if (operand_type_check (i.types[n], disp)) |
29b0f896 AM |
8979 | { |
8980 | if (i.op[n].disps->X_op == O_constant) | |
8981 | { | |
e205caa7 | 8982 | int size = disp_size (n); |
43234a1e | 8983 | offsetT val = i.op[n].disps->X_add_number; |
252b5132 | 8984 | |
629cfaf1 JB |
8985 | val = offset_in_range (val >> (size == 1 ? i.memshift : 0), |
8986 | size); | |
29b0f896 AM |
8987 | p = frag_more (size); |
8988 | md_number_to_chars (p, val, size); | |
8989 | } | |
8990 | else | |
8991 | { | |
f86103b7 | 8992 | enum bfd_reloc_code_real reloc_type; |
e205caa7 | 8993 | int size = disp_size (n); |
40fb9820 | 8994 | int sign = i.types[n].bitfield.disp32s; |
29b0f896 | 8995 | int pcrel = (i.flags[n] & Operand_PCrel) != 0; |
02a86693 | 8996 | fixS *fixP; |
29b0f896 | 8997 | |
e205caa7 | 8998 | /* We can't have 8 bit displacement here. */ |
9c2799c2 | 8999 | gas_assert (!i.types[n].bitfield.disp8); |
e205caa7 | 9000 | |
29b0f896 AM |
9001 | /* The PC relative address is computed relative |
9002 | to the instruction boundary, so in case immediate | |
9003 | fields follows, we need to adjust the value. */ | |
9004 | if (pcrel && i.imm_operands) | |
9005 | { | |
29b0f896 | 9006 | unsigned int n1; |
e205caa7 | 9007 | int sz = 0; |
252b5132 | 9008 | |
29b0f896 | 9009 | for (n1 = 0; n1 < i.operands; n1++) |
40fb9820 | 9010 | if (operand_type_check (i.types[n1], imm)) |
252b5132 | 9011 | { |
e205caa7 L |
9012 | /* Only one immediate is allowed for PC |
9013 | relative address. */ | |
9c2799c2 | 9014 | gas_assert (sz == 0); |
e205caa7 L |
9015 | sz = imm_size (n1); |
9016 | i.op[n].disps->X_add_number -= sz; | |
252b5132 | 9017 | } |
29b0f896 | 9018 | /* We should find the immediate. */ |
9c2799c2 | 9019 | gas_assert (sz != 0); |
29b0f896 | 9020 | } |
520dc8e8 | 9021 | |
29b0f896 | 9022 | p = frag_more (size); |
d258b828 | 9023 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
d6ab8113 | 9024 | if (GOT_symbol |
2bbd9c25 | 9025 | && GOT_symbol == i.op[n].disps->X_add_symbol |
d6ab8113 | 9026 | && (((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
9027 | || reloc_type == BFD_RELOC_X86_64_32S |
9028 | || (reloc_type == BFD_RELOC_64 | |
9029 | && object_64bit)) | |
d6ab8113 JB |
9030 | && (i.op[n].disps->X_op == O_symbol |
9031 | || (i.op[n].disps->X_op == O_add | |
9032 | && ((symbol_get_value_expression | |
9033 | (i.op[n].disps->X_op_symbol)->X_op) | |
9034 | == O_subtract)))) | |
9035 | || reloc_type == BFD_RELOC_32_PCREL)) | |
2bbd9c25 | 9036 | { |
4fa24527 | 9037 | if (!object_64bit) |
7b81dfbb AJ |
9038 | { |
9039 | reloc_type = BFD_RELOC_386_GOTPC; | |
e379e5f3 | 9040 | i.has_gotpc_tls_reloc = TRUE; |
d583596c JB |
9041 | i.op[n].imms->X_add_number += |
9042 | encoding_length (insn_start_frag, insn_start_off, p); | |
7b81dfbb AJ |
9043 | } |
9044 | else if (reloc_type == BFD_RELOC_64) | |
9045 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
d6ab8113 | 9046 | else |
7b81dfbb AJ |
9047 | /* Don't do the adjustment for x86-64, as there |
9048 | the pcrel addressing is relative to the _next_ | |
9049 | insn, and that is taken care of in other code. */ | |
d6ab8113 | 9050 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
2bbd9c25 | 9051 | } |
e379e5f3 L |
9052 | else if (align_branch_power) |
9053 | { | |
9054 | switch (reloc_type) | |
9055 | { | |
9056 | case BFD_RELOC_386_TLS_GD: | |
9057 | case BFD_RELOC_386_TLS_LDM: | |
9058 | case BFD_RELOC_386_TLS_IE: | |
9059 | case BFD_RELOC_386_TLS_IE_32: | |
9060 | case BFD_RELOC_386_TLS_GOTIE: | |
9061 | case BFD_RELOC_386_TLS_GOTDESC: | |
9062 | case BFD_RELOC_386_TLS_DESC_CALL: | |
9063 | case BFD_RELOC_X86_64_TLSGD: | |
9064 | case BFD_RELOC_X86_64_TLSLD: | |
9065 | case BFD_RELOC_X86_64_GOTTPOFF: | |
9066 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: | |
9067 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
9068 | i.has_gotpc_tls_reloc = TRUE; | |
9069 | default: | |
9070 | break; | |
9071 | } | |
9072 | } | |
02a86693 L |
9073 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, |
9074 | size, i.op[n].disps, pcrel, | |
9075 | reloc_type); | |
9076 | /* Check for "call/jmp *mem", "mov mem, %reg", | |
9077 | "test %reg, mem" and "binop mem, %reg" where binop | |
9078 | is one of adc, add, and, cmp, or, sbb, sub, xor | |
e60f4d3b L |
9079 | instructions without data prefix. Always generate |
9080 | R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */ | |
9081 | if (i.prefix[DATA_PREFIX] == 0 | |
9082 | && (generate_relax_relocations | |
9083 | || (!object_64bit | |
9084 | && i.rm.mode == 0 | |
9085 | && i.rm.regmem == 5)) | |
0cb4071e L |
9086 | && (i.rm.mode == 2 |
9087 | || (i.rm.mode == 0 && i.rm.regmem == 5)) | |
02a86693 L |
9088 | && ((i.operands == 1 |
9089 | && i.tm.base_opcode == 0xff | |
9090 | && (i.rm.reg == 2 || i.rm.reg == 4)) | |
9091 | || (i.operands == 2 | |
9092 | && (i.tm.base_opcode == 0x8b | |
9093 | || i.tm.base_opcode == 0x85 | |
9094 | || (i.tm.base_opcode & 0xc7) == 0x03)))) | |
9095 | { | |
9096 | if (object_64bit) | |
9097 | { | |
9098 | fixP->fx_tcbit = i.rex != 0; | |
9099 | if (i.base_reg | |
e968fc9b | 9100 | && (i.base_reg->reg_num == RegIP)) |
02a86693 L |
9101 | fixP->fx_tcbit2 = 1; |
9102 | } | |
9103 | else | |
9104 | fixP->fx_tcbit2 = 1; | |
9105 | } | |
29b0f896 AM |
9106 | } |
9107 | } | |
9108 | } | |
9109 | } | |
252b5132 | 9110 | |
29b0f896 | 9111 | static void |
64e74474 | 9112 | output_imm (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
9113 | { |
9114 | char *p; | |
9115 | unsigned int n; | |
252b5132 | 9116 | |
29b0f896 AM |
9117 | for (n = 0; n < i.operands; n++) |
9118 | { | |
43234a1e L |
9119 | /* Skip SAE/RC Imm operand in EVEX. They are already handled. */ |
9120 | if (i.rounding && (int) n == i.rounding->operand) | |
9121 | continue; | |
9122 | ||
40fb9820 | 9123 | if (operand_type_check (i.types[n], imm)) |
29b0f896 AM |
9124 | { |
9125 | if (i.op[n].imms->X_op == O_constant) | |
9126 | { | |
e205caa7 | 9127 | int size = imm_size (n); |
29b0f896 | 9128 | offsetT val; |
b4cac588 | 9129 | |
29b0f896 AM |
9130 | val = offset_in_range (i.op[n].imms->X_add_number, |
9131 | size); | |
9132 | p = frag_more (size); | |
9133 | md_number_to_chars (p, val, size); | |
9134 | } | |
9135 | else | |
9136 | { | |
9137 | /* Not absolute_section. | |
9138 | Need a 32-bit fixup (don't support 8bit | |
9139 | non-absolute imms). Try to support other | |
9140 | sizes ... */ | |
f86103b7 | 9141 | enum bfd_reloc_code_real reloc_type; |
e205caa7 L |
9142 | int size = imm_size (n); |
9143 | int sign; | |
29b0f896 | 9144 | |
40fb9820 | 9145 | if (i.types[n].bitfield.imm32s |
a7d61044 | 9146 | && (i.suffix == QWORD_MNEM_SUFFIX |
40fb9820 | 9147 | || (!i.suffix && i.tm.opcode_modifier.no_lsuf))) |
29b0f896 | 9148 | sign = 1; |
e205caa7 L |
9149 | else |
9150 | sign = 0; | |
520dc8e8 | 9151 | |
29b0f896 | 9152 | p = frag_more (size); |
d258b828 | 9153 | reloc_type = reloc (size, 0, sign, i.reloc[n]); |
f86103b7 | 9154 | |
2bbd9c25 JJ |
9155 | /* This is tough to explain. We end up with this one if we |
9156 | * have operands that look like | |
9157 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to | |
9158 | * obtain the absolute address of the GOT, and it is strongly | |
9159 | * preferable from a performance point of view to avoid using | |
9160 | * a runtime relocation for this. The actual sequence of | |
9161 | * instructions often look something like: | |
9162 | * | |
9163 | * call .L66 | |
9164 | * .L66: | |
9165 | * popl %ebx | |
9166 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
9167 | * | |
9168 | * The call and pop essentially return the absolute address | |
9169 | * of the label .L66 and store it in %ebx. The linker itself | |
9170 | * will ultimately change the first operand of the addl so | |
9171 | * that %ebx points to the GOT, but to keep things simple, the | |
9172 | * .o file must have this operand set so that it generates not | |
9173 | * the absolute address of .L66, but the absolute address of | |
9174 | * itself. This allows the linker itself simply treat a GOTPC | |
9175 | * relocation as asking for a pcrel offset to the GOT to be | |
9176 | * added in, and the addend of the relocation is stored in the | |
9177 | * operand field for the instruction itself. | |
9178 | * | |
9179 | * Our job here is to fix the operand so that it would add | |
9180 | * the correct offset so that %ebx would point to itself. The | |
9181 | * thing that is tricky is that .-.L66 will point to the | |
9182 | * beginning of the instruction, so we need to further modify | |
9183 | * the operand so that it will point to itself. There are | |
9184 | * other cases where you have something like: | |
9185 | * | |
9186 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
9187 | * | |
9188 | * and here no correction would be required. Internally in | |
9189 | * the assembler we treat operands of this form as not being | |
9190 | * pcrel since the '.' is explicitly mentioned, and I wonder | |
9191 | * whether it would simplify matters to do it this way. Who | |
9192 | * knows. In earlier versions of the PIC patches, the | |
9193 | * pcrel_adjust field was used to store the correction, but | |
9194 | * since the expression is not pcrel, I felt it would be | |
9195 | * confusing to do it this way. */ | |
9196 | ||
d6ab8113 | 9197 | if ((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
9198 | || reloc_type == BFD_RELOC_X86_64_32S |
9199 | || reloc_type == BFD_RELOC_64) | |
29b0f896 AM |
9200 | && GOT_symbol |
9201 | && GOT_symbol == i.op[n].imms->X_add_symbol | |
9202 | && (i.op[n].imms->X_op == O_symbol | |
9203 | || (i.op[n].imms->X_op == O_add | |
9204 | && ((symbol_get_value_expression | |
9205 | (i.op[n].imms->X_op_symbol)->X_op) | |
9206 | == O_subtract)))) | |
9207 | { | |
4fa24527 | 9208 | if (!object_64bit) |
d6ab8113 | 9209 | reloc_type = BFD_RELOC_386_GOTPC; |
7b81dfbb | 9210 | else if (size == 4) |
d6ab8113 | 9211 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
7b81dfbb AJ |
9212 | else if (size == 8) |
9213 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
e379e5f3 | 9214 | i.has_gotpc_tls_reloc = TRUE; |
d583596c JB |
9215 | i.op[n].imms->X_add_number += |
9216 | encoding_length (insn_start_frag, insn_start_off, p); | |
29b0f896 | 9217 | } |
29b0f896 AM |
9218 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
9219 | i.op[n].imms, 0, reloc_type); | |
9220 | } | |
9221 | } | |
9222 | } | |
252b5132 RH |
9223 | } |
9224 | \f | |
d182319b JB |
9225 | /* x86_cons_fix_new is called via the expression parsing code when a |
9226 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
d182319b JB |
9227 | static int cons_sign = -1; |
9228 | ||
9229 | void | |
e3bb37b5 | 9230 | x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, |
62ebcb5c | 9231 | expressionS *exp, bfd_reloc_code_real_type r) |
d182319b | 9232 | { |
d258b828 | 9233 | r = reloc (len, 0, cons_sign, r); |
d182319b JB |
9234 | |
9235 | #ifdef TE_PE | |
9236 | if (exp->X_op == O_secrel) | |
9237 | { | |
9238 | exp->X_op = O_symbol; | |
9239 | r = BFD_RELOC_32_SECREL; | |
9240 | } | |
9241 | #endif | |
9242 | ||
9243 | fix_new_exp (frag, off, len, exp, 0, r); | |
9244 | } | |
9245 | ||
357d1bd8 L |
9246 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
9247 | purpose of the `.dc.a' internal pseudo-op. */ | |
9248 | ||
9249 | int | |
9250 | x86_address_bytes (void) | |
9251 | { | |
9252 | if ((stdoutput->arch_info->mach & bfd_mach_x64_32)) | |
9253 | return 4; | |
9254 | return stdoutput->arch_info->bits_per_address / 8; | |
9255 | } | |
9256 | ||
d382c579 TG |
9257 | #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \ |
9258 | || defined (LEX_AT) | |
d258b828 | 9259 | # define lex_got(reloc, adjust, types) NULL |
718ddfc0 | 9260 | #else |
f3c180ae AM |
9261 | /* Parse operands of the form |
9262 | <symbol>@GOTOFF+<nnn> | |
9263 | and similar .plt or .got references. | |
9264 | ||
9265 | If we find one, set up the correct relocation in RELOC and copy the | |
9266 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
9267 | parsing by the calling routine. Return this buffer, and if ADJUST | |
9268 | is non-null set it to the length of the string we removed from the | |
9269 | input line. Otherwise return NULL. */ | |
9270 | static char * | |
91d6fa6a | 9271 | lex_got (enum bfd_reloc_code_real *rel, |
64e74474 | 9272 | int *adjust, |
d258b828 | 9273 | i386_operand_type *types) |
f3c180ae | 9274 | { |
7b81dfbb AJ |
9275 | /* Some of the relocations depend on the size of what field is to |
9276 | be relocated. But in our callers i386_immediate and i386_displacement | |
9277 | we don't yet know the operand size (this will be set by insn | |
9278 | matching). Hence we record the word32 relocation here, | |
9279 | and adjust the reloc according to the real size in reloc(). */ | |
f3c180ae AM |
9280 | static const struct { |
9281 | const char *str; | |
cff8d58a | 9282 | int len; |
4fa24527 | 9283 | const enum bfd_reloc_code_real rel[2]; |
40fb9820 | 9284 | const i386_operand_type types64; |
f3c180ae | 9285 | } gotrel[] = { |
8ce3d284 | 9286 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
9287 | { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32, |
9288 | BFD_RELOC_SIZE32 }, | |
9289 | OPERAND_TYPE_IMM32_64 }, | |
8ce3d284 | 9290 | #endif |
cff8d58a L |
9291 | { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real, |
9292 | BFD_RELOC_X86_64_PLTOFF64 }, | |
40fb9820 | 9293 | OPERAND_TYPE_IMM64 }, |
cff8d58a L |
9294 | { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32, |
9295 | BFD_RELOC_X86_64_PLT32 }, | |
40fb9820 | 9296 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
9297 | { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real, |
9298 | BFD_RELOC_X86_64_GOTPLT64 }, | |
40fb9820 | 9299 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
9300 | { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF, |
9301 | BFD_RELOC_X86_64_GOTOFF64 }, | |
40fb9820 | 9302 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
9303 | { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real, |
9304 | BFD_RELOC_X86_64_GOTPCREL }, | |
40fb9820 | 9305 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
9306 | { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD, |
9307 | BFD_RELOC_X86_64_TLSGD }, | |
40fb9820 | 9308 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
9309 | { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM, |
9310 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 9311 | OPERAND_TYPE_NONE }, |
cff8d58a L |
9312 | { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real, |
9313 | BFD_RELOC_X86_64_TLSLD }, | |
40fb9820 | 9314 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
9315 | { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32, |
9316 | BFD_RELOC_X86_64_GOTTPOFF }, | |
40fb9820 | 9317 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
9318 | { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32, |
9319 | BFD_RELOC_X86_64_TPOFF32 }, | |
40fb9820 | 9320 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
9321 | { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE, |
9322 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 9323 | OPERAND_TYPE_NONE }, |
cff8d58a L |
9324 | { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32, |
9325 | BFD_RELOC_X86_64_DTPOFF32 }, | |
40fb9820 | 9326 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
9327 | { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE, |
9328 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 9329 | OPERAND_TYPE_NONE }, |
cff8d58a L |
9330 | { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE, |
9331 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 9332 | OPERAND_TYPE_NONE }, |
cff8d58a L |
9333 | { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32, |
9334 | BFD_RELOC_X86_64_GOT32 }, | |
40fb9820 | 9335 | OPERAND_TYPE_IMM32_32S_64_DISP32 }, |
cff8d58a L |
9336 | { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC, |
9337 | BFD_RELOC_X86_64_GOTPC32_TLSDESC }, | |
40fb9820 | 9338 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
9339 | { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL, |
9340 | BFD_RELOC_X86_64_TLSDESC_CALL }, | |
40fb9820 | 9341 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
f3c180ae AM |
9342 | }; |
9343 | char *cp; | |
9344 | unsigned int j; | |
9345 | ||
d382c579 | 9346 | #if defined (OBJ_MAYBE_ELF) |
718ddfc0 JB |
9347 | if (!IS_ELF) |
9348 | return NULL; | |
d382c579 | 9349 | #endif |
718ddfc0 | 9350 | |
f3c180ae | 9351 | for (cp = input_line_pointer; *cp != '@'; cp++) |
67c11a9b | 9352 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') |
f3c180ae AM |
9353 | return NULL; |
9354 | ||
47465058 | 9355 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) |
f3c180ae | 9356 | { |
cff8d58a | 9357 | int len = gotrel[j].len; |
28f81592 | 9358 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae | 9359 | { |
4fa24527 | 9360 | if (gotrel[j].rel[object_64bit] != 0) |
f3c180ae | 9361 | { |
28f81592 AM |
9362 | int first, second; |
9363 | char *tmpbuf, *past_reloc; | |
f3c180ae | 9364 | |
91d6fa6a | 9365 | *rel = gotrel[j].rel[object_64bit]; |
f3c180ae | 9366 | |
3956db08 JB |
9367 | if (types) |
9368 | { | |
9369 | if (flag_code != CODE_64BIT) | |
40fb9820 L |
9370 | { |
9371 | types->bitfield.imm32 = 1; | |
9372 | types->bitfield.disp32 = 1; | |
9373 | } | |
3956db08 JB |
9374 | else |
9375 | *types = gotrel[j].types64; | |
9376 | } | |
9377 | ||
8fd4256d | 9378 | if (j != 0 && GOT_symbol == NULL) |
f3c180ae AM |
9379 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); |
9380 | ||
28f81592 | 9381 | /* The length of the first part of our input line. */ |
f3c180ae | 9382 | first = cp - input_line_pointer; |
28f81592 AM |
9383 | |
9384 | /* The second part goes from after the reloc token until | |
67c11a9b | 9385 | (and including) an end_of_line char or comma. */ |
28f81592 | 9386 | past_reloc = cp + 1 + len; |
67c11a9b AM |
9387 | cp = past_reloc; |
9388 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
9389 | ++cp; | |
9390 | second = cp + 1 - past_reloc; | |
28f81592 AM |
9391 | |
9392 | /* Allocate and copy string. The trailing NUL shouldn't | |
9393 | be necessary, but be safe. */ | |
add39d23 | 9394 | tmpbuf = XNEWVEC (char, first + second + 2); |
f3c180ae | 9395 | memcpy (tmpbuf, input_line_pointer, first); |
0787a12d AM |
9396 | if (second != 0 && *past_reloc != ' ') |
9397 | /* Replace the relocation token with ' ', so that | |
9398 | errors like foo@GOTOFF1 will be detected. */ | |
9399 | tmpbuf[first++] = ' '; | |
af89796a L |
9400 | else |
9401 | /* Increment length by 1 if the relocation token is | |
9402 | removed. */ | |
9403 | len++; | |
9404 | if (adjust) | |
9405 | *adjust = len; | |
0787a12d AM |
9406 | memcpy (tmpbuf + first, past_reloc, second); |
9407 | tmpbuf[first + second] = '\0'; | |
f3c180ae AM |
9408 | return tmpbuf; |
9409 | } | |
9410 | ||
4fa24527 JB |
9411 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
9412 | gotrel[j].str, 1 << (5 + object_64bit)); | |
f3c180ae AM |
9413 | return NULL; |
9414 | } | |
9415 | } | |
9416 | ||
9417 | /* Might be a symbol version string. Don't as_bad here. */ | |
9418 | return NULL; | |
9419 | } | |
4e4f7c87 | 9420 | #endif |
f3c180ae | 9421 | |
a988325c NC |
9422 | #ifdef TE_PE |
9423 | #ifdef lex_got | |
9424 | #undef lex_got | |
9425 | #endif | |
9426 | /* Parse operands of the form | |
9427 | <symbol>@SECREL32+<nnn> | |
9428 | ||
9429 | If we find one, set up the correct relocation in RELOC and copy the | |
9430 | input string, minus the `@SECREL32' into a malloc'd buffer for | |
9431 | parsing by the calling routine. Return this buffer, and if ADJUST | |
9432 | is non-null set it to the length of the string we removed from the | |
34bca508 L |
9433 | input line. Otherwise return NULL. |
9434 | ||
a988325c NC |
9435 | This function is copied from the ELF version above adjusted for PE targets. */ |
9436 | ||
9437 | static char * | |
9438 | lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED, | |
9439 | int *adjust ATTRIBUTE_UNUSED, | |
d258b828 | 9440 | i386_operand_type *types) |
a988325c NC |
9441 | { |
9442 | static const struct | |
9443 | { | |
9444 | const char *str; | |
9445 | int len; | |
9446 | const enum bfd_reloc_code_real rel[2]; | |
9447 | const i386_operand_type types64; | |
9448 | } | |
9449 | gotrel[] = | |
9450 | { | |
9451 | { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL, | |
9452 | BFD_RELOC_32_SECREL }, | |
9453 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, | |
9454 | }; | |
9455 | ||
9456 | char *cp; | |
9457 | unsigned j; | |
9458 | ||
9459 | for (cp = input_line_pointer; *cp != '@'; cp++) | |
9460 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') | |
9461 | return NULL; | |
9462 | ||
9463 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) | |
9464 | { | |
9465 | int len = gotrel[j].len; | |
9466 | ||
9467 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) | |
9468 | { | |
9469 | if (gotrel[j].rel[object_64bit] != 0) | |
9470 | { | |
9471 | int first, second; | |
9472 | char *tmpbuf, *past_reloc; | |
9473 | ||
9474 | *rel = gotrel[j].rel[object_64bit]; | |
9475 | if (adjust) | |
9476 | *adjust = len; | |
9477 | ||
9478 | if (types) | |
9479 | { | |
9480 | if (flag_code != CODE_64BIT) | |
9481 | { | |
9482 | types->bitfield.imm32 = 1; | |
9483 | types->bitfield.disp32 = 1; | |
9484 | } | |
9485 | else | |
9486 | *types = gotrel[j].types64; | |
9487 | } | |
9488 | ||
9489 | /* The length of the first part of our input line. */ | |
9490 | first = cp - input_line_pointer; | |
9491 | ||
9492 | /* The second part goes from after the reloc token until | |
9493 | (and including) an end_of_line char or comma. */ | |
9494 | past_reloc = cp + 1 + len; | |
9495 | cp = past_reloc; | |
9496 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
9497 | ++cp; | |
9498 | second = cp + 1 - past_reloc; | |
9499 | ||
9500 | /* Allocate and copy string. The trailing NUL shouldn't | |
9501 | be necessary, but be safe. */ | |
add39d23 | 9502 | tmpbuf = XNEWVEC (char, first + second + 2); |
a988325c NC |
9503 | memcpy (tmpbuf, input_line_pointer, first); |
9504 | if (second != 0 && *past_reloc != ' ') | |
9505 | /* Replace the relocation token with ' ', so that | |
9506 | errors like foo@SECLREL321 will be detected. */ | |
9507 | tmpbuf[first++] = ' '; | |
9508 | memcpy (tmpbuf + first, past_reloc, second); | |
9509 | tmpbuf[first + second] = '\0'; | |
9510 | return tmpbuf; | |
9511 | } | |
9512 | ||
9513 | as_bad (_("@%s reloc is not supported with %d-bit output format"), | |
9514 | gotrel[j].str, 1 << (5 + object_64bit)); | |
9515 | return NULL; | |
9516 | } | |
9517 | } | |
9518 | ||
9519 | /* Might be a symbol version string. Don't as_bad here. */ | |
9520 | return NULL; | |
9521 | } | |
9522 | ||
9523 | #endif /* TE_PE */ | |
9524 | ||
62ebcb5c | 9525 | bfd_reloc_code_real_type |
e3bb37b5 | 9526 | x86_cons (expressionS *exp, int size) |
f3c180ae | 9527 | { |
62ebcb5c AM |
9528 | bfd_reloc_code_real_type got_reloc = NO_RELOC; |
9529 | ||
ee86248c JB |
9530 | intel_syntax = -intel_syntax; |
9531 | ||
3c7b9c2c | 9532 | exp->X_md = 0; |
4fa24527 | 9533 | if (size == 4 || (object_64bit && size == 8)) |
f3c180ae AM |
9534 | { |
9535 | /* Handle @GOTOFF and the like in an expression. */ | |
9536 | char *save; | |
9537 | char *gotfree_input_line; | |
4a57f2cf | 9538 | int adjust = 0; |
f3c180ae AM |
9539 | |
9540 | save = input_line_pointer; | |
d258b828 | 9541 | gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); |
f3c180ae AM |
9542 | if (gotfree_input_line) |
9543 | input_line_pointer = gotfree_input_line; | |
9544 | ||
9545 | expression (exp); | |
9546 | ||
9547 | if (gotfree_input_line) | |
9548 | { | |
9549 | /* expression () has merrily parsed up to the end of line, | |
9550 | or a comma - in the wrong buffer. Transfer how far | |
9551 | input_line_pointer has moved to the right buffer. */ | |
9552 | input_line_pointer = (save | |
9553 | + (input_line_pointer - gotfree_input_line) | |
9554 | + adjust); | |
9555 | free (gotfree_input_line); | |
3992d3b7 AM |
9556 | if (exp->X_op == O_constant |
9557 | || exp->X_op == O_absent | |
9558 | || exp->X_op == O_illegal | |
0398aac5 | 9559 | || exp->X_op == O_register |
3992d3b7 AM |
9560 | || exp->X_op == O_big) |
9561 | { | |
9562 | char c = *input_line_pointer; | |
9563 | *input_line_pointer = 0; | |
9564 | as_bad (_("missing or invalid expression `%s'"), save); | |
9565 | *input_line_pointer = c; | |
9566 | } | |
b9519cfe L |
9567 | else if ((got_reloc == BFD_RELOC_386_PLT32 |
9568 | || got_reloc == BFD_RELOC_X86_64_PLT32) | |
9569 | && exp->X_op != O_symbol) | |
9570 | { | |
9571 | char c = *input_line_pointer; | |
9572 | *input_line_pointer = 0; | |
9573 | as_bad (_("invalid PLT expression `%s'"), save); | |
9574 | *input_line_pointer = c; | |
9575 | } | |
f3c180ae AM |
9576 | } |
9577 | } | |
9578 | else | |
9579 | expression (exp); | |
ee86248c JB |
9580 | |
9581 | intel_syntax = -intel_syntax; | |
9582 | ||
9583 | if (intel_syntax) | |
9584 | i386_intel_simplify (exp); | |
62ebcb5c AM |
9585 | |
9586 | return got_reloc; | |
f3c180ae | 9587 | } |
f3c180ae | 9588 | |
9f32dd5b L |
9589 | static void |
9590 | signed_cons (int size) | |
6482c264 | 9591 | { |
d182319b JB |
9592 | if (flag_code == CODE_64BIT) |
9593 | cons_sign = 1; | |
9594 | cons (size); | |
9595 | cons_sign = -1; | |
6482c264 NC |
9596 | } |
9597 | ||
d182319b | 9598 | #ifdef TE_PE |
6482c264 | 9599 | static void |
7016a5d5 | 9600 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
6482c264 NC |
9601 | { |
9602 | expressionS exp; | |
9603 | ||
9604 | do | |
9605 | { | |
9606 | expression (&exp); | |
9607 | if (exp.X_op == O_symbol) | |
9608 | exp.X_op = O_secrel; | |
9609 | ||
9610 | emit_expr (&exp, 4); | |
9611 | } | |
9612 | while (*input_line_pointer++ == ','); | |
9613 | ||
9614 | input_line_pointer--; | |
9615 | demand_empty_rest_of_line (); | |
9616 | } | |
6482c264 NC |
9617 | #endif |
9618 | ||
43234a1e L |
9619 | /* Handle Vector operations. */ |
9620 | ||
9621 | static char * | |
9622 | check_VecOperations (char *op_string, char *op_end) | |
9623 | { | |
9624 | const reg_entry *mask; | |
9625 | const char *saved; | |
9626 | char *end_op; | |
9627 | ||
9628 | while (*op_string | |
9629 | && (op_end == NULL || op_string < op_end)) | |
9630 | { | |
9631 | saved = op_string; | |
9632 | if (*op_string == '{') | |
9633 | { | |
9634 | op_string++; | |
9635 | ||
9636 | /* Check broadcasts. */ | |
9637 | if (strncmp (op_string, "1to", 3) == 0) | |
9638 | { | |
9639 | int bcst_type; | |
9640 | ||
9641 | if (i.broadcast) | |
9642 | goto duplicated_vec_op; | |
9643 | ||
9644 | op_string += 3; | |
9645 | if (*op_string == '8') | |
8e6e0792 | 9646 | bcst_type = 8; |
b28d1bda | 9647 | else if (*op_string == '4') |
8e6e0792 | 9648 | bcst_type = 4; |
b28d1bda | 9649 | else if (*op_string == '2') |
8e6e0792 | 9650 | bcst_type = 2; |
43234a1e L |
9651 | else if (*op_string == '1' |
9652 | && *(op_string+1) == '6') | |
9653 | { | |
8e6e0792 | 9654 | bcst_type = 16; |
43234a1e L |
9655 | op_string++; |
9656 | } | |
9657 | else | |
9658 | { | |
9659 | as_bad (_("Unsupported broadcast: `%s'"), saved); | |
9660 | return NULL; | |
9661 | } | |
9662 | op_string++; | |
9663 | ||
9664 | broadcast_op.type = bcst_type; | |
9665 | broadcast_op.operand = this_operand; | |
1f75763a | 9666 | broadcast_op.bytes = 0; |
43234a1e L |
9667 | i.broadcast = &broadcast_op; |
9668 | } | |
9669 | /* Check masking operation. */ | |
9670 | else if ((mask = parse_register (op_string, &end_op)) != NULL) | |
9671 | { | |
9672 | /* k0 can't be used for write mask. */ | |
f74a6307 | 9673 | if (mask->reg_type.bitfield.class != RegMask || !mask->reg_num) |
43234a1e | 9674 | { |
6d2cd6b2 JB |
9675 | as_bad (_("`%s%s' can't be used for write mask"), |
9676 | register_prefix, mask->reg_name); | |
43234a1e L |
9677 | return NULL; |
9678 | } | |
9679 | ||
9680 | if (!i.mask) | |
9681 | { | |
9682 | mask_op.mask = mask; | |
9683 | mask_op.zeroing = 0; | |
9684 | mask_op.operand = this_operand; | |
9685 | i.mask = &mask_op; | |
9686 | } | |
9687 | else | |
9688 | { | |
9689 | if (i.mask->mask) | |
9690 | goto duplicated_vec_op; | |
9691 | ||
9692 | i.mask->mask = mask; | |
9693 | ||
9694 | /* Only "{z}" is allowed here. No need to check | |
9695 | zeroing mask explicitly. */ | |
9696 | if (i.mask->operand != this_operand) | |
9697 | { | |
9698 | as_bad (_("invalid write mask `%s'"), saved); | |
9699 | return NULL; | |
9700 | } | |
9701 | } | |
9702 | ||
9703 | op_string = end_op; | |
9704 | } | |
9705 | /* Check zeroing-flag for masking operation. */ | |
9706 | else if (*op_string == 'z') | |
9707 | { | |
9708 | if (!i.mask) | |
9709 | { | |
9710 | mask_op.mask = NULL; | |
9711 | mask_op.zeroing = 1; | |
9712 | mask_op.operand = this_operand; | |
9713 | i.mask = &mask_op; | |
9714 | } | |
9715 | else | |
9716 | { | |
9717 | if (i.mask->zeroing) | |
9718 | { | |
9719 | duplicated_vec_op: | |
9720 | as_bad (_("duplicated `%s'"), saved); | |
9721 | return NULL; | |
9722 | } | |
9723 | ||
9724 | i.mask->zeroing = 1; | |
9725 | ||
9726 | /* Only "{%k}" is allowed here. No need to check mask | |
9727 | register explicitly. */ | |
9728 | if (i.mask->operand != this_operand) | |
9729 | { | |
9730 | as_bad (_("invalid zeroing-masking `%s'"), | |
9731 | saved); | |
9732 | return NULL; | |
9733 | } | |
9734 | } | |
9735 | ||
9736 | op_string++; | |
9737 | } | |
9738 | else | |
9739 | goto unknown_vec_op; | |
9740 | ||
9741 | if (*op_string != '}') | |
9742 | { | |
9743 | as_bad (_("missing `}' in `%s'"), saved); | |
9744 | return NULL; | |
9745 | } | |
9746 | op_string++; | |
0ba3a731 L |
9747 | |
9748 | /* Strip whitespace since the addition of pseudo prefixes | |
9749 | changed how the scrubber treats '{'. */ | |
9750 | if (is_space_char (*op_string)) | |
9751 | ++op_string; | |
9752 | ||
43234a1e L |
9753 | continue; |
9754 | } | |
9755 | unknown_vec_op: | |
9756 | /* We don't know this one. */ | |
9757 | as_bad (_("unknown vector operation: `%s'"), saved); | |
9758 | return NULL; | |
9759 | } | |
9760 | ||
6d2cd6b2 JB |
9761 | if (i.mask && i.mask->zeroing && !i.mask->mask) |
9762 | { | |
9763 | as_bad (_("zeroing-masking only allowed with write mask")); | |
9764 | return NULL; | |
9765 | } | |
9766 | ||
43234a1e L |
9767 | return op_string; |
9768 | } | |
9769 | ||
252b5132 | 9770 | static int |
70e41ade | 9771 | i386_immediate (char *imm_start) |
252b5132 RH |
9772 | { |
9773 | char *save_input_line_pointer; | |
f3c180ae | 9774 | char *gotfree_input_line; |
252b5132 | 9775 | segT exp_seg = 0; |
47926f60 | 9776 | expressionS *exp; |
40fb9820 L |
9777 | i386_operand_type types; |
9778 | ||
0dfbf9d7 | 9779 | operand_type_set (&types, ~0); |
252b5132 RH |
9780 | |
9781 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
9782 | { | |
31b2323c L |
9783 | as_bad (_("at most %d immediate operands are allowed"), |
9784 | MAX_IMMEDIATE_OPERANDS); | |
252b5132 RH |
9785 | return 0; |
9786 | } | |
9787 | ||
9788 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 9789 | i.op[this_operand].imms = exp; |
252b5132 RH |
9790 | |
9791 | if (is_space_char (*imm_start)) | |
9792 | ++imm_start; | |
9793 | ||
9794 | save_input_line_pointer = input_line_pointer; | |
9795 | input_line_pointer = imm_start; | |
9796 | ||
d258b828 | 9797 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
9798 | if (gotfree_input_line) |
9799 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
9800 | |
9801 | exp_seg = expression (exp); | |
9802 | ||
83183c0c | 9803 | SKIP_WHITESPACE (); |
43234a1e L |
9804 | |
9805 | /* Handle vector operations. */ | |
9806 | if (*input_line_pointer == '{') | |
9807 | { | |
9808 | input_line_pointer = check_VecOperations (input_line_pointer, | |
9809 | NULL); | |
9810 | if (input_line_pointer == NULL) | |
9811 | return 0; | |
9812 | } | |
9813 | ||
252b5132 | 9814 | if (*input_line_pointer) |
f3c180ae | 9815 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
9816 | |
9817 | input_line_pointer = save_input_line_pointer; | |
f3c180ae | 9818 | if (gotfree_input_line) |
ee86248c JB |
9819 | { |
9820 | free (gotfree_input_line); | |
9821 | ||
9822 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
9823 | exp->X_op = O_illegal; | |
9824 | } | |
9825 | ||
9826 | return i386_finalize_immediate (exp_seg, exp, types, imm_start); | |
9827 | } | |
252b5132 | 9828 | |
ee86248c JB |
9829 | static int |
9830 | i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
9831 | i386_operand_type types, const char *imm_start) | |
9832 | { | |
9833 | if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big) | |
252b5132 | 9834 | { |
313c53d1 L |
9835 | if (imm_start) |
9836 | as_bad (_("missing or invalid immediate expression `%s'"), | |
9837 | imm_start); | |
3992d3b7 | 9838 | return 0; |
252b5132 | 9839 | } |
3e73aa7c | 9840 | else if (exp->X_op == O_constant) |
252b5132 | 9841 | { |
47926f60 | 9842 | /* Size it properly later. */ |
40fb9820 | 9843 | i.types[this_operand].bitfield.imm64 = 1; |
13f864ae L |
9844 | /* If not 64bit, sign extend val. */ |
9845 | if (flag_code != CODE_64BIT | |
4eed87de AM |
9846 | && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) |
9847 | exp->X_add_number | |
9848 | = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
252b5132 | 9849 | } |
4c63da97 | 9850 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
f86103b7 | 9851 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 9852 | && exp_seg != absolute_section |
47926f60 | 9853 | && exp_seg != text_section |
24eab124 AM |
9854 | && exp_seg != data_section |
9855 | && exp_seg != bss_section | |
9856 | && exp_seg != undefined_section | |
f86103b7 | 9857 | && !bfd_is_com_section (exp_seg)) |
252b5132 | 9858 | { |
d0b47220 | 9859 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
252b5132 RH |
9860 | return 0; |
9861 | } | |
9862 | #endif | |
a841bdf5 | 9863 | else if (!intel_syntax && exp_seg == reg_section) |
bb8f5920 | 9864 | { |
313c53d1 L |
9865 | if (imm_start) |
9866 | as_bad (_("illegal immediate register operand %s"), imm_start); | |
bb8f5920 L |
9867 | return 0; |
9868 | } | |
252b5132 RH |
9869 | else |
9870 | { | |
9871 | /* This is an address. The size of the address will be | |
24eab124 | 9872 | determined later, depending on destination register, |
3e73aa7c | 9873 | suffix, or the default for the section. */ |
40fb9820 L |
9874 | i.types[this_operand].bitfield.imm8 = 1; |
9875 | i.types[this_operand].bitfield.imm16 = 1; | |
9876 | i.types[this_operand].bitfield.imm32 = 1; | |
9877 | i.types[this_operand].bitfield.imm32s = 1; | |
9878 | i.types[this_operand].bitfield.imm64 = 1; | |
c6fb90c8 L |
9879 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
9880 | types); | |
252b5132 RH |
9881 | } |
9882 | ||
9883 | return 1; | |
9884 | } | |
9885 | ||
551c1ca1 | 9886 | static char * |
e3bb37b5 | 9887 | i386_scale (char *scale) |
252b5132 | 9888 | { |
551c1ca1 AM |
9889 | offsetT val; |
9890 | char *save = input_line_pointer; | |
252b5132 | 9891 | |
551c1ca1 AM |
9892 | input_line_pointer = scale; |
9893 | val = get_absolute_expression (); | |
9894 | ||
9895 | switch (val) | |
252b5132 | 9896 | { |
551c1ca1 | 9897 | case 1: |
252b5132 RH |
9898 | i.log2_scale_factor = 0; |
9899 | break; | |
551c1ca1 | 9900 | case 2: |
252b5132 RH |
9901 | i.log2_scale_factor = 1; |
9902 | break; | |
551c1ca1 | 9903 | case 4: |
252b5132 RH |
9904 | i.log2_scale_factor = 2; |
9905 | break; | |
551c1ca1 | 9906 | case 8: |
252b5132 RH |
9907 | i.log2_scale_factor = 3; |
9908 | break; | |
9909 | default: | |
a724f0f4 JB |
9910 | { |
9911 | char sep = *input_line_pointer; | |
9912 | ||
9913 | *input_line_pointer = '\0'; | |
9914 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
9915 | scale); | |
9916 | *input_line_pointer = sep; | |
9917 | input_line_pointer = save; | |
9918 | return NULL; | |
9919 | } | |
252b5132 | 9920 | } |
29b0f896 | 9921 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
252b5132 RH |
9922 | { |
9923 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 9924 | 1 << i.log2_scale_factor); |
252b5132 | 9925 | i.log2_scale_factor = 0; |
252b5132 | 9926 | } |
551c1ca1 AM |
9927 | scale = input_line_pointer; |
9928 | input_line_pointer = save; | |
9929 | return scale; | |
252b5132 RH |
9930 | } |
9931 | ||
252b5132 | 9932 | static int |
e3bb37b5 | 9933 | i386_displacement (char *disp_start, char *disp_end) |
252b5132 | 9934 | { |
29b0f896 | 9935 | expressionS *exp; |
252b5132 RH |
9936 | segT exp_seg = 0; |
9937 | char *save_input_line_pointer; | |
f3c180ae | 9938 | char *gotfree_input_line; |
40fb9820 L |
9939 | int override; |
9940 | i386_operand_type bigdisp, types = anydisp; | |
3992d3b7 | 9941 | int ret; |
252b5132 | 9942 | |
31b2323c L |
9943 | if (i.disp_operands == MAX_MEMORY_OPERANDS) |
9944 | { | |
9945 | as_bad (_("at most %d displacement operands are allowed"), | |
9946 | MAX_MEMORY_OPERANDS); | |
9947 | return 0; | |
9948 | } | |
9949 | ||
0dfbf9d7 | 9950 | operand_type_set (&bigdisp, 0); |
6f2f06be | 9951 | if (i.jumpabsolute |
48bcea9f | 9952 | || i.types[this_operand].bitfield.baseindex |
0cfa3eb3 JB |
9953 | || (current_templates->start->opcode_modifier.jump != JUMP |
9954 | && current_templates->start->opcode_modifier.jump != JUMP_DWORD)) | |
e05278af | 9955 | { |
48bcea9f | 9956 | i386_addressing_mode (); |
e05278af | 9957 | override = (i.prefix[ADDR_PREFIX] != 0); |
40fb9820 L |
9958 | if (flag_code == CODE_64BIT) |
9959 | { | |
9960 | if (!override) | |
9961 | { | |
9962 | bigdisp.bitfield.disp32s = 1; | |
9963 | bigdisp.bitfield.disp64 = 1; | |
9964 | } | |
48bcea9f JB |
9965 | else |
9966 | bigdisp.bitfield.disp32 = 1; | |
40fb9820 L |
9967 | } |
9968 | else if ((flag_code == CODE_16BIT) ^ override) | |
40fb9820 | 9969 | bigdisp.bitfield.disp16 = 1; |
48bcea9f JB |
9970 | else |
9971 | bigdisp.bitfield.disp32 = 1; | |
e05278af JB |
9972 | } |
9973 | else | |
9974 | { | |
376cd056 JB |
9975 | /* For PC-relative branches, the width of the displacement may be |
9976 | dependent upon data size, but is never dependent upon address size. | |
9977 | Also make sure to not unintentionally match against a non-PC-relative | |
9978 | branch template. */ | |
9979 | static templates aux_templates; | |
9980 | const insn_template *t = current_templates->start; | |
9981 | bfd_boolean has_intel64 = FALSE; | |
9982 | ||
9983 | aux_templates.start = t; | |
9984 | while (++t < current_templates->end) | |
9985 | { | |
9986 | if (t->opcode_modifier.jump | |
9987 | != current_templates->start->opcode_modifier.jump) | |
9988 | break; | |
9989 | if (t->opcode_modifier.intel64) | |
9990 | has_intel64 = TRUE; | |
9991 | } | |
9992 | if (t < current_templates->end) | |
9993 | { | |
9994 | aux_templates.end = t; | |
9995 | current_templates = &aux_templates; | |
9996 | } | |
9997 | ||
e05278af | 9998 | override = (i.prefix[DATA_PREFIX] != 0); |
40fb9820 L |
9999 | if (flag_code == CODE_64BIT) |
10000 | { | |
376cd056 JB |
10001 | if ((override || i.suffix == WORD_MNEM_SUFFIX) |
10002 | && (!intel64 || !has_intel64)) | |
40fb9820 L |
10003 | bigdisp.bitfield.disp16 = 1; |
10004 | else | |
48bcea9f | 10005 | bigdisp.bitfield.disp32s = 1; |
40fb9820 L |
10006 | } |
10007 | else | |
e05278af JB |
10008 | { |
10009 | if (!override) | |
10010 | override = (i.suffix == (flag_code != CODE_16BIT | |
10011 | ? WORD_MNEM_SUFFIX | |
10012 | : LONG_MNEM_SUFFIX)); | |
40fb9820 L |
10013 | bigdisp.bitfield.disp32 = 1; |
10014 | if ((flag_code == CODE_16BIT) ^ override) | |
10015 | { | |
10016 | bigdisp.bitfield.disp32 = 0; | |
10017 | bigdisp.bitfield.disp16 = 1; | |
10018 | } | |
e05278af | 10019 | } |
e05278af | 10020 | } |
c6fb90c8 L |
10021 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
10022 | bigdisp); | |
252b5132 RH |
10023 | |
10024 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 10025 | i.op[this_operand].disps = exp; |
252b5132 RH |
10026 | i.disp_operands++; |
10027 | save_input_line_pointer = input_line_pointer; | |
10028 | input_line_pointer = disp_start; | |
10029 | END_STRING_AND_SAVE (disp_end); | |
10030 | ||
10031 | #ifndef GCC_ASM_O_HACK | |
10032 | #define GCC_ASM_O_HACK 0 | |
10033 | #endif | |
10034 | #if GCC_ASM_O_HACK | |
10035 | END_STRING_AND_SAVE (disp_end + 1); | |
40fb9820 | 10036 | if (i.types[this_operand].bitfield.baseIndex |
24eab124 | 10037 | && displacement_string_end[-1] == '+') |
252b5132 RH |
10038 | { |
10039 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
10040 | constraint within gcc asm statements. |
10041 | For instance: | |
10042 | ||
10043 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
10044 | __asm__ __volatile__ ( \ | |
10045 | "movw %w2,%0\n\t" \ | |
10046 | "movw %w1,2+%0\n\t" \ | |
10047 | "rorl $16,%1\n\t" \ | |
10048 | "movb %b1,4+%0\n\t" \ | |
10049 | "movb %4,5+%0\n\t" \ | |
10050 | "movb $0,6+%0\n\t" \ | |
10051 | "movb %h1,7+%0\n\t" \ | |
10052 | "rorl $16,%1" \ | |
10053 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
10054 | ||
10055 | This works great except that the output assembler ends | |
10056 | up looking a bit weird if it turns out that there is | |
10057 | no offset. You end up producing code that looks like: | |
10058 | ||
10059 | #APP | |
10060 | movw $235,(%eax) | |
10061 | movw %dx,2+(%eax) | |
10062 | rorl $16,%edx | |
10063 | movb %dl,4+(%eax) | |
10064 | movb $137,5+(%eax) | |
10065 | movb $0,6+(%eax) | |
10066 | movb %dh,7+(%eax) | |
10067 | rorl $16,%edx | |
10068 | #NO_APP | |
10069 | ||
47926f60 | 10070 | So here we provide the missing zero. */ |
24eab124 AM |
10071 | |
10072 | *displacement_string_end = '0'; | |
252b5132 RH |
10073 | } |
10074 | #endif | |
d258b828 | 10075 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
10076 | if (gotfree_input_line) |
10077 | input_line_pointer = gotfree_input_line; | |
252b5132 | 10078 | |
24eab124 | 10079 | exp_seg = expression (exp); |
252b5132 | 10080 | |
636c26b0 AM |
10081 | SKIP_WHITESPACE (); |
10082 | if (*input_line_pointer) | |
10083 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
10084 | #if GCC_ASM_O_HACK | |
10085 | RESTORE_END_STRING (disp_end + 1); | |
10086 | #endif | |
636c26b0 | 10087 | input_line_pointer = save_input_line_pointer; |
636c26b0 | 10088 | if (gotfree_input_line) |
ee86248c JB |
10089 | { |
10090 | free (gotfree_input_line); | |
10091 | ||
10092 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
10093 | exp->X_op = O_illegal; | |
10094 | } | |
10095 | ||
10096 | ret = i386_finalize_displacement (exp_seg, exp, types, disp_start); | |
10097 | ||
10098 | RESTORE_END_STRING (disp_end); | |
10099 | ||
10100 | return ret; | |
10101 | } | |
10102 | ||
10103 | static int | |
10104 | i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
10105 | i386_operand_type types, const char *disp_start) | |
10106 | { | |
10107 | i386_operand_type bigdisp; | |
10108 | int ret = 1; | |
636c26b0 | 10109 | |
24eab124 AM |
10110 | /* We do this to make sure that the section symbol is in |
10111 | the symbol table. We will ultimately change the relocation | |
47926f60 | 10112 | to be relative to the beginning of the section. */ |
1ae12ab7 | 10113 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
d6ab8113 JB |
10114 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
10115 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) | |
24eab124 | 10116 | { |
636c26b0 | 10117 | if (exp->X_op != O_symbol) |
3992d3b7 | 10118 | goto inv_disp; |
636c26b0 | 10119 | |
e5cb08ac | 10120 | if (S_IS_LOCAL (exp->X_add_symbol) |
c64efb4b L |
10121 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section |
10122 | && S_GET_SEGMENT (exp->X_add_symbol) != expr_section) | |
24eab124 | 10123 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); |
24eab124 AM |
10124 | exp->X_op = O_subtract; |
10125 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 | 10126 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
29b0f896 | 10127 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
d6ab8113 JB |
10128 | else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
10129 | i.reloc[this_operand] = BFD_RELOC_64; | |
23df1078 | 10130 | else |
29b0f896 | 10131 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 10132 | } |
252b5132 | 10133 | |
3992d3b7 AM |
10134 | else if (exp->X_op == O_absent |
10135 | || exp->X_op == O_illegal | |
ee86248c | 10136 | || exp->X_op == O_big) |
2daf4fd8 | 10137 | { |
3992d3b7 AM |
10138 | inv_disp: |
10139 | as_bad (_("missing or invalid displacement expression `%s'"), | |
2daf4fd8 | 10140 | disp_start); |
3992d3b7 | 10141 | ret = 0; |
2daf4fd8 AM |
10142 | } |
10143 | ||
0e1147d9 L |
10144 | else if (flag_code == CODE_64BIT |
10145 | && !i.prefix[ADDR_PREFIX] | |
10146 | && exp->X_op == O_constant) | |
10147 | { | |
10148 | /* Since displacement is signed extended to 64bit, don't allow | |
10149 | disp32 and turn off disp32s if they are out of range. */ | |
10150 | i.types[this_operand].bitfield.disp32 = 0; | |
10151 | if (!fits_in_signed_long (exp->X_add_number)) | |
10152 | { | |
10153 | i.types[this_operand].bitfield.disp32s = 0; | |
10154 | if (i.types[this_operand].bitfield.baseindex) | |
10155 | { | |
10156 | as_bad (_("0x%lx out range of signed 32bit displacement"), | |
10157 | (long) exp->X_add_number); | |
10158 | ret = 0; | |
10159 | } | |
10160 | } | |
10161 | } | |
10162 | ||
4c63da97 | 10163 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
3992d3b7 AM |
10164 | else if (exp->X_op != O_constant |
10165 | && OUTPUT_FLAVOR == bfd_target_aout_flavour | |
10166 | && exp_seg != absolute_section | |
10167 | && exp_seg != text_section | |
10168 | && exp_seg != data_section | |
10169 | && exp_seg != bss_section | |
10170 | && exp_seg != undefined_section | |
10171 | && !bfd_is_com_section (exp_seg)) | |
24eab124 | 10172 | { |
d0b47220 | 10173 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
3992d3b7 | 10174 | ret = 0; |
24eab124 | 10175 | } |
252b5132 | 10176 | #endif |
3956db08 | 10177 | |
48bcea9f JB |
10178 | if (current_templates->start->opcode_modifier.jump == JUMP_BYTE |
10179 | /* Constants get taken care of by optimize_disp(). */ | |
10180 | && exp->X_op != O_constant) | |
10181 | i.types[this_operand].bitfield.disp8 = 1; | |
10182 | ||
40fb9820 L |
10183 | /* Check if this is a displacement only operand. */ |
10184 | bigdisp = i.types[this_operand]; | |
10185 | bigdisp.bitfield.disp8 = 0; | |
10186 | bigdisp.bitfield.disp16 = 0; | |
10187 | bigdisp.bitfield.disp32 = 0; | |
10188 | bigdisp.bitfield.disp32s = 0; | |
10189 | bigdisp.bitfield.disp64 = 0; | |
0dfbf9d7 | 10190 | if (operand_type_all_zero (&bigdisp)) |
c6fb90c8 L |
10191 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
10192 | types); | |
3956db08 | 10193 | |
3992d3b7 | 10194 | return ret; |
252b5132 RH |
10195 | } |
10196 | ||
2abc2bec JB |
10197 | /* Return the active addressing mode, taking address override and |
10198 | registers forming the address into consideration. Update the | |
10199 | address override prefix if necessary. */ | |
47926f60 | 10200 | |
2abc2bec JB |
10201 | static enum flag_code |
10202 | i386_addressing_mode (void) | |
252b5132 | 10203 | { |
be05d201 L |
10204 | enum flag_code addr_mode; |
10205 | ||
10206 | if (i.prefix[ADDR_PREFIX]) | |
10207 | addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT; | |
10208 | else | |
10209 | { | |
10210 | addr_mode = flag_code; | |
10211 | ||
24eab124 | 10212 | #if INFER_ADDR_PREFIX |
be05d201 L |
10213 | if (i.mem_operands == 0) |
10214 | { | |
10215 | /* Infer address prefix from the first memory operand. */ | |
10216 | const reg_entry *addr_reg = i.base_reg; | |
10217 | ||
10218 | if (addr_reg == NULL) | |
10219 | addr_reg = i.index_reg; | |
eecb386c | 10220 | |
be05d201 L |
10221 | if (addr_reg) |
10222 | { | |
e968fc9b | 10223 | if (addr_reg->reg_type.bitfield.dword) |
be05d201 L |
10224 | addr_mode = CODE_32BIT; |
10225 | else if (flag_code != CODE_64BIT | |
dc821c5f | 10226 | && addr_reg->reg_type.bitfield.word) |
be05d201 L |
10227 | addr_mode = CODE_16BIT; |
10228 | ||
10229 | if (addr_mode != flag_code) | |
10230 | { | |
10231 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
10232 | i.prefixes += 1; | |
10233 | /* Change the size of any displacement too. At most one | |
10234 | of Disp16 or Disp32 is set. | |
10235 | FIXME. There doesn't seem to be any real need for | |
10236 | separate Disp16 and Disp32 flags. The same goes for | |
10237 | Imm16 and Imm32. Removing them would probably clean | |
10238 | up the code quite a lot. */ | |
10239 | if (flag_code != CODE_64BIT | |
10240 | && (i.types[this_operand].bitfield.disp16 | |
10241 | || i.types[this_operand].bitfield.disp32)) | |
10242 | i.types[this_operand] | |
10243 | = operand_type_xor (i.types[this_operand], disp16_32); | |
10244 | } | |
10245 | } | |
10246 | } | |
24eab124 | 10247 | #endif |
be05d201 L |
10248 | } |
10249 | ||
2abc2bec JB |
10250 | return addr_mode; |
10251 | } | |
10252 | ||
10253 | /* Make sure the memory operand we've been dealt is valid. | |
10254 | Return 1 on success, 0 on a failure. */ | |
10255 | ||
10256 | static int | |
10257 | i386_index_check (const char *operand_string) | |
10258 | { | |
10259 | const char *kind = "base/index"; | |
10260 | enum flag_code addr_mode = i386_addressing_mode (); | |
10261 | ||
fc0763e6 | 10262 | if (current_templates->start->opcode_modifier.isstring |
c3949f43 | 10263 | && !current_templates->start->cpu_flags.bitfield.cpupadlock |
fc0763e6 JB |
10264 | && (current_templates->end[-1].opcode_modifier.isstring |
10265 | || i.mem_operands)) | |
10266 | { | |
10267 | /* Memory operands of string insns are special in that they only allow | |
10268 | a single register (rDI, rSI, or rBX) as their memory address. */ | |
be05d201 L |
10269 | const reg_entry *expected_reg; |
10270 | static const char *di_si[][2] = | |
10271 | { | |
10272 | { "esi", "edi" }, | |
10273 | { "si", "di" }, | |
10274 | { "rsi", "rdi" } | |
10275 | }; | |
10276 | static const char *bx[] = { "ebx", "bx", "rbx" }; | |
fc0763e6 JB |
10277 | |
10278 | kind = "string address"; | |
10279 | ||
8325cc63 | 10280 | if (current_templates->start->opcode_modifier.repprefixok) |
fc0763e6 | 10281 | { |
51c8edf6 JB |
10282 | int es_op = current_templates->end[-1].opcode_modifier.isstring |
10283 | - IS_STRING_ES_OP0; | |
10284 | int op = 0; | |
fc0763e6 | 10285 | |
51c8edf6 | 10286 | if (!current_templates->end[-1].operand_types[0].bitfield.baseindex |
fc0763e6 JB |
10287 | || ((!i.mem_operands != !intel_syntax) |
10288 | && current_templates->end[-1].operand_types[1] | |
10289 | .bitfield.baseindex)) | |
51c8edf6 JB |
10290 | op = 1; |
10291 | expected_reg = hash_find (reg_hash, di_si[addr_mode][op == es_op]); | |
fc0763e6 JB |
10292 | } |
10293 | else | |
be05d201 | 10294 | expected_reg = hash_find (reg_hash, bx[addr_mode]); |
fc0763e6 | 10295 | |
be05d201 L |
10296 | if (i.base_reg != expected_reg |
10297 | || i.index_reg | |
fc0763e6 | 10298 | || operand_type_check (i.types[this_operand], disp)) |
fc0763e6 | 10299 | { |
be05d201 L |
10300 | /* The second memory operand must have the same size as |
10301 | the first one. */ | |
10302 | if (i.mem_operands | |
10303 | && i.base_reg | |
10304 | && !((addr_mode == CODE_64BIT | |
dc821c5f | 10305 | && i.base_reg->reg_type.bitfield.qword) |
be05d201 | 10306 | || (addr_mode == CODE_32BIT |
dc821c5f JB |
10307 | ? i.base_reg->reg_type.bitfield.dword |
10308 | : i.base_reg->reg_type.bitfield.word))) | |
be05d201 L |
10309 | goto bad_address; |
10310 | ||
fc0763e6 JB |
10311 | as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"), |
10312 | operand_string, | |
10313 | intel_syntax ? '[' : '(', | |
10314 | register_prefix, | |
be05d201 | 10315 | expected_reg->reg_name, |
fc0763e6 | 10316 | intel_syntax ? ']' : ')'); |
be05d201 | 10317 | return 1; |
fc0763e6 | 10318 | } |
be05d201 L |
10319 | else |
10320 | return 1; | |
10321 | ||
10322 | bad_address: | |
10323 | as_bad (_("`%s' is not a valid %s expression"), | |
10324 | operand_string, kind); | |
10325 | return 0; | |
3e73aa7c JH |
10326 | } |
10327 | else | |
10328 | { | |
be05d201 L |
10329 | if (addr_mode != CODE_16BIT) |
10330 | { | |
10331 | /* 32-bit/64-bit checks. */ | |
10332 | if ((i.base_reg | |
e968fc9b JB |
10333 | && ((addr_mode == CODE_64BIT |
10334 | ? !i.base_reg->reg_type.bitfield.qword | |
10335 | : !i.base_reg->reg_type.bitfield.dword) | |
10336 | || (i.index_reg && i.base_reg->reg_num == RegIP) | |
10337 | || i.base_reg->reg_num == RegIZ)) | |
be05d201 | 10338 | || (i.index_reg |
1b54b8d7 JB |
10339 | && !i.index_reg->reg_type.bitfield.xmmword |
10340 | && !i.index_reg->reg_type.bitfield.ymmword | |
10341 | && !i.index_reg->reg_type.bitfield.zmmword | |
be05d201 | 10342 | && ((addr_mode == CODE_64BIT |
e968fc9b JB |
10343 | ? !i.index_reg->reg_type.bitfield.qword |
10344 | : !i.index_reg->reg_type.bitfield.dword) | |
be05d201 L |
10345 | || !i.index_reg->reg_type.bitfield.baseindex))) |
10346 | goto bad_address; | |
8178be5b JB |
10347 | |
10348 | /* bndmk, bndldx, and bndstx have special restrictions. */ | |
10349 | if (current_templates->start->base_opcode == 0xf30f1b | |
10350 | || (current_templates->start->base_opcode & ~1) == 0x0f1a) | |
10351 | { | |
10352 | /* They cannot use RIP-relative addressing. */ | |
e968fc9b | 10353 | if (i.base_reg && i.base_reg->reg_num == RegIP) |
8178be5b JB |
10354 | { |
10355 | as_bad (_("`%s' cannot be used here"), operand_string); | |
10356 | return 0; | |
10357 | } | |
10358 | ||
10359 | /* bndldx and bndstx ignore their scale factor. */ | |
10360 | if (current_templates->start->base_opcode != 0xf30f1b | |
10361 | && i.log2_scale_factor) | |
10362 | as_warn (_("register scaling is being ignored here")); | |
10363 | } | |
be05d201 L |
10364 | } |
10365 | else | |
3e73aa7c | 10366 | { |
be05d201 | 10367 | /* 16-bit checks. */ |
3e73aa7c | 10368 | if ((i.base_reg |
dc821c5f | 10369 | && (!i.base_reg->reg_type.bitfield.word |
40fb9820 | 10370 | || !i.base_reg->reg_type.bitfield.baseindex)) |
3e73aa7c | 10371 | || (i.index_reg |
dc821c5f | 10372 | && (!i.index_reg->reg_type.bitfield.word |
40fb9820 | 10373 | || !i.index_reg->reg_type.bitfield.baseindex |
29b0f896 AM |
10374 | || !(i.base_reg |
10375 | && i.base_reg->reg_num < 6 | |
10376 | && i.index_reg->reg_num >= 6 | |
10377 | && i.log2_scale_factor == 0)))) | |
be05d201 | 10378 | goto bad_address; |
3e73aa7c JH |
10379 | } |
10380 | } | |
be05d201 | 10381 | return 1; |
24eab124 | 10382 | } |
252b5132 | 10383 | |
43234a1e L |
10384 | /* Handle vector immediates. */ |
10385 | ||
10386 | static int | |
10387 | RC_SAE_immediate (const char *imm_start) | |
10388 | { | |
10389 | unsigned int match_found, j; | |
10390 | const char *pstr = imm_start; | |
10391 | expressionS *exp; | |
10392 | ||
10393 | if (*pstr != '{') | |
10394 | return 0; | |
10395 | ||
10396 | pstr++; | |
10397 | match_found = 0; | |
10398 | for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++) | |
10399 | { | |
10400 | if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len)) | |
10401 | { | |
10402 | if (!i.rounding) | |
10403 | { | |
10404 | rc_op.type = RC_NamesTable[j].type; | |
10405 | rc_op.operand = this_operand; | |
10406 | i.rounding = &rc_op; | |
10407 | } | |
10408 | else | |
10409 | { | |
10410 | as_bad (_("duplicated `%s'"), imm_start); | |
10411 | return 0; | |
10412 | } | |
10413 | pstr += RC_NamesTable[j].len; | |
10414 | match_found = 1; | |
10415 | break; | |
10416 | } | |
10417 | } | |
10418 | if (!match_found) | |
10419 | return 0; | |
10420 | ||
10421 | if (*pstr++ != '}') | |
10422 | { | |
10423 | as_bad (_("Missing '}': '%s'"), imm_start); | |
10424 | return 0; | |
10425 | } | |
10426 | /* RC/SAE immediate string should contain nothing more. */; | |
10427 | if (*pstr != 0) | |
10428 | { | |
10429 | as_bad (_("Junk after '}': '%s'"), imm_start); | |
10430 | return 0; | |
10431 | } | |
10432 | ||
10433 | exp = &im_expressions[i.imm_operands++]; | |
10434 | i.op[this_operand].imms = exp; | |
10435 | ||
10436 | exp->X_op = O_constant; | |
10437 | exp->X_add_number = 0; | |
10438 | exp->X_add_symbol = (symbolS *) 0; | |
10439 | exp->X_op_symbol = (symbolS *) 0; | |
10440 | ||
10441 | i.types[this_operand].bitfield.imm8 = 1; | |
10442 | return 1; | |
10443 | } | |
10444 | ||
8325cc63 JB |
10445 | /* Only string instructions can have a second memory operand, so |
10446 | reduce current_templates to just those if it contains any. */ | |
10447 | static int | |
10448 | maybe_adjust_templates (void) | |
10449 | { | |
10450 | const insn_template *t; | |
10451 | ||
10452 | gas_assert (i.mem_operands == 1); | |
10453 | ||
10454 | for (t = current_templates->start; t < current_templates->end; ++t) | |
10455 | if (t->opcode_modifier.isstring) | |
10456 | break; | |
10457 | ||
10458 | if (t < current_templates->end) | |
10459 | { | |
10460 | static templates aux_templates; | |
10461 | bfd_boolean recheck; | |
10462 | ||
10463 | aux_templates.start = t; | |
10464 | for (; t < current_templates->end; ++t) | |
10465 | if (!t->opcode_modifier.isstring) | |
10466 | break; | |
10467 | aux_templates.end = t; | |
10468 | ||
10469 | /* Determine whether to re-check the first memory operand. */ | |
10470 | recheck = (aux_templates.start != current_templates->start | |
10471 | || t != current_templates->end); | |
10472 | ||
10473 | current_templates = &aux_templates; | |
10474 | ||
10475 | if (recheck) | |
10476 | { | |
10477 | i.mem_operands = 0; | |
10478 | if (i.memop1_string != NULL | |
10479 | && i386_index_check (i.memop1_string) == 0) | |
10480 | return 0; | |
10481 | i.mem_operands = 1; | |
10482 | } | |
10483 | } | |
10484 | ||
10485 | return 1; | |
10486 | } | |
10487 | ||
fc0763e6 | 10488 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero |
47926f60 | 10489 | on error. */ |
252b5132 | 10490 | |
252b5132 | 10491 | static int |
a7619375 | 10492 | i386_att_operand (char *operand_string) |
252b5132 | 10493 | { |
af6bdddf AM |
10494 | const reg_entry *r; |
10495 | char *end_op; | |
24eab124 | 10496 | char *op_string = operand_string; |
252b5132 | 10497 | |
24eab124 | 10498 | if (is_space_char (*op_string)) |
252b5132 RH |
10499 | ++op_string; |
10500 | ||
24eab124 | 10501 | /* We check for an absolute prefix (differentiating, |
47926f60 | 10502 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
10503 | if (*op_string == ABSOLUTE_PREFIX) |
10504 | { | |
10505 | ++op_string; | |
10506 | if (is_space_char (*op_string)) | |
10507 | ++op_string; | |
6f2f06be | 10508 | i.jumpabsolute = TRUE; |
24eab124 | 10509 | } |
252b5132 | 10510 | |
47926f60 | 10511 | /* Check if operand is a register. */ |
4d1bb795 | 10512 | if ((r = parse_register (op_string, &end_op)) != NULL) |
24eab124 | 10513 | { |
40fb9820 L |
10514 | i386_operand_type temp; |
10515 | ||
24eab124 AM |
10516 | /* Check for a segment override by searching for ':' after a |
10517 | segment register. */ | |
10518 | op_string = end_op; | |
10519 | if (is_space_char (*op_string)) | |
10520 | ++op_string; | |
00cee14f | 10521 | if (*op_string == ':' && r->reg_type.bitfield.class == SReg) |
24eab124 AM |
10522 | { |
10523 | switch (r->reg_num) | |
10524 | { | |
10525 | case 0: | |
10526 | i.seg[i.mem_operands] = &es; | |
10527 | break; | |
10528 | case 1: | |
10529 | i.seg[i.mem_operands] = &cs; | |
10530 | break; | |
10531 | case 2: | |
10532 | i.seg[i.mem_operands] = &ss; | |
10533 | break; | |
10534 | case 3: | |
10535 | i.seg[i.mem_operands] = &ds; | |
10536 | break; | |
10537 | case 4: | |
10538 | i.seg[i.mem_operands] = &fs; | |
10539 | break; | |
10540 | case 5: | |
10541 | i.seg[i.mem_operands] = &gs; | |
10542 | break; | |
10543 | } | |
252b5132 | 10544 | |
24eab124 | 10545 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
10546 | ++op_string; |
10547 | if (is_space_char (*op_string)) | |
24eab124 | 10548 | ++op_string; |
252b5132 | 10549 | |
24eab124 AM |
10550 | if (!is_digit_char (*op_string) |
10551 | && !is_identifier_char (*op_string) | |
10552 | && *op_string != '(' | |
10553 | && *op_string != ABSOLUTE_PREFIX) | |
10554 | { | |
10555 | as_bad (_("bad memory operand `%s'"), op_string); | |
10556 | return 0; | |
10557 | } | |
47926f60 | 10558 | /* Handle case of %es:*foo. */ |
24eab124 AM |
10559 | if (*op_string == ABSOLUTE_PREFIX) |
10560 | { | |
10561 | ++op_string; | |
10562 | if (is_space_char (*op_string)) | |
10563 | ++op_string; | |
6f2f06be | 10564 | i.jumpabsolute = TRUE; |
24eab124 AM |
10565 | } |
10566 | goto do_memory_reference; | |
10567 | } | |
43234a1e L |
10568 | |
10569 | /* Handle vector operations. */ | |
10570 | if (*op_string == '{') | |
10571 | { | |
10572 | op_string = check_VecOperations (op_string, NULL); | |
10573 | if (op_string == NULL) | |
10574 | return 0; | |
10575 | } | |
10576 | ||
24eab124 AM |
10577 | if (*op_string) |
10578 | { | |
d0b47220 | 10579 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
10580 | return 0; |
10581 | } | |
40fb9820 L |
10582 | temp = r->reg_type; |
10583 | temp.bitfield.baseindex = 0; | |
c6fb90c8 L |
10584 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
10585 | temp); | |
7d5e4556 | 10586 | i.types[this_operand].bitfield.unspecified = 0; |
520dc8e8 | 10587 | i.op[this_operand].regs = r; |
24eab124 AM |
10588 | i.reg_operands++; |
10589 | } | |
af6bdddf AM |
10590 | else if (*op_string == REGISTER_PREFIX) |
10591 | { | |
10592 | as_bad (_("bad register name `%s'"), op_string); | |
10593 | return 0; | |
10594 | } | |
24eab124 | 10595 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 10596 | { |
24eab124 | 10597 | ++op_string; |
6f2f06be | 10598 | if (i.jumpabsolute) |
24eab124 | 10599 | { |
d0b47220 | 10600 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
10601 | return 0; |
10602 | } | |
10603 | if (!i386_immediate (op_string)) | |
10604 | return 0; | |
10605 | } | |
43234a1e L |
10606 | else if (RC_SAE_immediate (operand_string)) |
10607 | { | |
10608 | /* If it is a RC or SAE immediate, do nothing. */ | |
10609 | ; | |
10610 | } | |
24eab124 AM |
10611 | else if (is_digit_char (*op_string) |
10612 | || is_identifier_char (*op_string) | |
d02603dc | 10613 | || *op_string == '"' |
e5cb08ac | 10614 | || *op_string == '(') |
24eab124 | 10615 | { |
47926f60 | 10616 | /* This is a memory reference of some sort. */ |
af6bdddf | 10617 | char *base_string; |
252b5132 | 10618 | |
47926f60 | 10619 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
10620 | char *displacement_string_start; |
10621 | char *displacement_string_end; | |
43234a1e | 10622 | char *vop_start; |
252b5132 | 10623 | |
24eab124 | 10624 | do_memory_reference: |
8325cc63 JB |
10625 | if (i.mem_operands == 1 && !maybe_adjust_templates ()) |
10626 | return 0; | |
24eab124 | 10627 | if ((i.mem_operands == 1 |
40fb9820 | 10628 | && !current_templates->start->opcode_modifier.isstring) |
24eab124 AM |
10629 | || i.mem_operands == 2) |
10630 | { | |
10631 | as_bad (_("too many memory references for `%s'"), | |
10632 | current_templates->start->name); | |
10633 | return 0; | |
10634 | } | |
252b5132 | 10635 | |
24eab124 AM |
10636 | /* Check for base index form. We detect the base index form by |
10637 | looking for an ')' at the end of the operand, searching | |
10638 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
10639 | after the '('. */ | |
af6bdddf | 10640 | base_string = op_string + strlen (op_string); |
c3332e24 | 10641 | |
43234a1e L |
10642 | /* Handle vector operations. */ |
10643 | vop_start = strchr (op_string, '{'); | |
10644 | if (vop_start && vop_start < base_string) | |
10645 | { | |
10646 | if (check_VecOperations (vop_start, base_string) == NULL) | |
10647 | return 0; | |
10648 | base_string = vop_start; | |
10649 | } | |
10650 | ||
af6bdddf AM |
10651 | --base_string; |
10652 | if (is_space_char (*base_string)) | |
10653 | --base_string; | |
252b5132 | 10654 | |
47926f60 | 10655 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
10656 | displacement_string_start = op_string; |
10657 | displacement_string_end = base_string + 1; | |
252b5132 | 10658 | |
24eab124 AM |
10659 | if (*base_string == ')') |
10660 | { | |
af6bdddf | 10661 | char *temp_string; |
24eab124 AM |
10662 | unsigned int parens_balanced = 1; |
10663 | /* We've already checked that the number of left & right ()'s are | |
47926f60 | 10664 | equal, so this loop will not be infinite. */ |
24eab124 AM |
10665 | do |
10666 | { | |
10667 | base_string--; | |
10668 | if (*base_string == ')') | |
10669 | parens_balanced++; | |
10670 | if (*base_string == '(') | |
10671 | parens_balanced--; | |
10672 | } | |
10673 | while (parens_balanced); | |
c3332e24 | 10674 | |
af6bdddf | 10675 | temp_string = base_string; |
c3332e24 | 10676 | |
24eab124 | 10677 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
10678 | ++base_string; |
10679 | if (is_space_char (*base_string)) | |
24eab124 | 10680 | ++base_string; |
252b5132 | 10681 | |
af6bdddf | 10682 | if (*base_string == ',' |
4eed87de AM |
10683 | || ((i.base_reg = parse_register (base_string, &end_op)) |
10684 | != NULL)) | |
252b5132 | 10685 | { |
af6bdddf | 10686 | displacement_string_end = temp_string; |
252b5132 | 10687 | |
40fb9820 | 10688 | i.types[this_operand].bitfield.baseindex = 1; |
252b5132 | 10689 | |
af6bdddf | 10690 | if (i.base_reg) |
24eab124 | 10691 | { |
24eab124 AM |
10692 | base_string = end_op; |
10693 | if (is_space_char (*base_string)) | |
10694 | ++base_string; | |
af6bdddf AM |
10695 | } |
10696 | ||
10697 | /* There may be an index reg or scale factor here. */ | |
10698 | if (*base_string == ',') | |
10699 | { | |
10700 | ++base_string; | |
10701 | if (is_space_char (*base_string)) | |
10702 | ++base_string; | |
10703 | ||
4eed87de AM |
10704 | if ((i.index_reg = parse_register (base_string, &end_op)) |
10705 | != NULL) | |
24eab124 | 10706 | { |
af6bdddf | 10707 | base_string = end_op; |
24eab124 AM |
10708 | if (is_space_char (*base_string)) |
10709 | ++base_string; | |
af6bdddf AM |
10710 | if (*base_string == ',') |
10711 | { | |
10712 | ++base_string; | |
10713 | if (is_space_char (*base_string)) | |
10714 | ++base_string; | |
10715 | } | |
e5cb08ac | 10716 | else if (*base_string != ')') |
af6bdddf | 10717 | { |
4eed87de AM |
10718 | as_bad (_("expecting `,' or `)' " |
10719 | "after index register in `%s'"), | |
af6bdddf AM |
10720 | operand_string); |
10721 | return 0; | |
10722 | } | |
24eab124 | 10723 | } |
af6bdddf | 10724 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 10725 | { |
f76bf5e0 L |
10726 | end_op = strchr (base_string, ','); |
10727 | if (end_op) | |
10728 | *end_op = '\0'; | |
af6bdddf | 10729 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
10730 | return 0; |
10731 | } | |
252b5132 | 10732 | |
47926f60 | 10733 | /* Check for scale factor. */ |
551c1ca1 | 10734 | if (*base_string != ')') |
af6bdddf | 10735 | { |
551c1ca1 AM |
10736 | char *end_scale = i386_scale (base_string); |
10737 | ||
10738 | if (!end_scale) | |
af6bdddf | 10739 | return 0; |
24eab124 | 10740 | |
551c1ca1 | 10741 | base_string = end_scale; |
af6bdddf AM |
10742 | if (is_space_char (*base_string)) |
10743 | ++base_string; | |
10744 | if (*base_string != ')') | |
10745 | { | |
4eed87de AM |
10746 | as_bad (_("expecting `)' " |
10747 | "after scale factor in `%s'"), | |
af6bdddf AM |
10748 | operand_string); |
10749 | return 0; | |
10750 | } | |
10751 | } | |
10752 | else if (!i.index_reg) | |
24eab124 | 10753 | { |
4eed87de AM |
10754 | as_bad (_("expecting index register or scale factor " |
10755 | "after `,'; got '%c'"), | |
af6bdddf | 10756 | *base_string); |
24eab124 AM |
10757 | return 0; |
10758 | } | |
10759 | } | |
af6bdddf | 10760 | else if (*base_string != ')') |
24eab124 | 10761 | { |
4eed87de AM |
10762 | as_bad (_("expecting `,' or `)' " |
10763 | "after base register in `%s'"), | |
af6bdddf | 10764 | operand_string); |
24eab124 AM |
10765 | return 0; |
10766 | } | |
c3332e24 | 10767 | } |
af6bdddf | 10768 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 10769 | { |
f76bf5e0 L |
10770 | end_op = strchr (base_string, ','); |
10771 | if (end_op) | |
10772 | *end_op = '\0'; | |
af6bdddf | 10773 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 10774 | return 0; |
c3332e24 | 10775 | } |
24eab124 AM |
10776 | } |
10777 | ||
10778 | /* If there's an expression beginning the operand, parse it, | |
10779 | assuming displacement_string_start and | |
10780 | displacement_string_end are meaningful. */ | |
10781 | if (displacement_string_start != displacement_string_end) | |
10782 | { | |
10783 | if (!i386_displacement (displacement_string_start, | |
10784 | displacement_string_end)) | |
10785 | return 0; | |
10786 | } | |
10787 | ||
10788 | /* Special case for (%dx) while doing input/output op. */ | |
10789 | if (i.base_reg | |
75e5731b JB |
10790 | && i.base_reg->reg_type.bitfield.instance == RegD |
10791 | && i.base_reg->reg_type.bitfield.word | |
24eab124 AM |
10792 | && i.index_reg == 0 |
10793 | && i.log2_scale_factor == 0 | |
10794 | && i.seg[i.mem_operands] == 0 | |
40fb9820 | 10795 | && !operand_type_check (i.types[this_operand], disp)) |
24eab124 | 10796 | { |
2fb5be8d | 10797 | i.types[this_operand] = i.base_reg->reg_type; |
24eab124 AM |
10798 | return 1; |
10799 | } | |
10800 | ||
eecb386c AM |
10801 | if (i386_index_check (operand_string) == 0) |
10802 | return 0; | |
c48dadc9 | 10803 | i.flags[this_operand] |= Operand_Mem; |
8325cc63 JB |
10804 | if (i.mem_operands == 0) |
10805 | i.memop1_string = xstrdup (operand_string); | |
24eab124 AM |
10806 | i.mem_operands++; |
10807 | } | |
10808 | else | |
ce8a8b2f AM |
10809 | { |
10810 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
10811 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
10812 | output_invalid (*op_string), | |
10813 | this_operand + 1, | |
10814 | op_string); | |
10815 | return 0; | |
10816 | } | |
47926f60 | 10817 | return 1; /* Normal return. */ |
252b5132 RH |
10818 | } |
10819 | \f | |
fa94de6b RM |
10820 | /* Calculate the maximum variable size (i.e., excluding fr_fix) |
10821 | that an rs_machine_dependent frag may reach. */ | |
10822 | ||
10823 | unsigned int | |
10824 | i386_frag_max_var (fragS *frag) | |
10825 | { | |
10826 | /* The only relaxable frags are for jumps. | |
10827 | Unconditional jumps can grow by 4 bytes and others by 5 bytes. */ | |
10828 | gas_assert (frag->fr_type == rs_machine_dependent); | |
10829 | return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5; | |
10830 | } | |
10831 | ||
b084df0b L |
10832 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
10833 | static int | |
8dcea932 | 10834 | elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var) |
b084df0b L |
10835 | { |
10836 | /* STT_GNU_IFUNC symbol must go through PLT. */ | |
10837 | if ((symbol_get_bfdsym (fr_symbol)->flags | |
10838 | & BSF_GNU_INDIRECT_FUNCTION) != 0) | |
10839 | return 0; | |
10840 | ||
10841 | if (!S_IS_EXTERNAL (fr_symbol)) | |
10842 | /* Symbol may be weak or local. */ | |
10843 | return !S_IS_WEAK (fr_symbol); | |
10844 | ||
8dcea932 L |
10845 | /* Global symbols with non-default visibility can't be preempted. */ |
10846 | if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT) | |
10847 | return 1; | |
10848 | ||
10849 | if (fr_var != NO_RELOC) | |
10850 | switch ((enum bfd_reloc_code_real) fr_var) | |
10851 | { | |
10852 | case BFD_RELOC_386_PLT32: | |
10853 | case BFD_RELOC_X86_64_PLT32: | |
33eaf5de | 10854 | /* Symbol with PLT relocation may be preempted. */ |
8dcea932 L |
10855 | return 0; |
10856 | default: | |
10857 | abort (); | |
10858 | } | |
10859 | ||
b084df0b L |
10860 | /* Global symbols with default visibility in a shared library may be |
10861 | preempted by another definition. */ | |
8dcea932 | 10862 | return !shared; |
b084df0b L |
10863 | } |
10864 | #endif | |
10865 | ||
e379e5f3 L |
10866 | /* Return the next non-empty frag. */ |
10867 | ||
10868 | static fragS * | |
10869 | i386_next_non_empty_frag (fragS *fragP) | |
10870 | { | |
10871 | /* There may be a frag with a ".fill 0" when there is no room in | |
10872 | the current frag for frag_grow in output_insn. */ | |
10873 | for (fragP = fragP->fr_next; | |
10874 | (fragP != NULL | |
10875 | && fragP->fr_type == rs_fill | |
10876 | && fragP->fr_fix == 0); | |
10877 | fragP = fragP->fr_next) | |
10878 | ; | |
10879 | return fragP; | |
10880 | } | |
10881 | ||
10882 | /* Return the next jcc frag after BRANCH_PADDING. */ | |
10883 | ||
10884 | static fragS * | |
10885 | i386_next_jcc_frag (fragS *fragP) | |
10886 | { | |
10887 | if (!fragP) | |
10888 | return NULL; | |
10889 | ||
10890 | if (fragP->fr_type == rs_machine_dependent | |
10891 | && (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
10892 | == BRANCH_PADDING)) | |
10893 | { | |
10894 | fragP = i386_next_non_empty_frag (fragP); | |
10895 | if (fragP->fr_type != rs_machine_dependent) | |
10896 | return NULL; | |
10897 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == COND_JUMP) | |
10898 | return fragP; | |
10899 | } | |
10900 | ||
10901 | return NULL; | |
10902 | } | |
10903 | ||
10904 | /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */ | |
10905 | ||
10906 | static void | |
10907 | i386_classify_machine_dependent_frag (fragS *fragP) | |
10908 | { | |
10909 | fragS *cmp_fragP; | |
10910 | fragS *pad_fragP; | |
10911 | fragS *branch_fragP; | |
10912 | fragS *next_fragP; | |
10913 | unsigned int max_prefix_length; | |
10914 | ||
10915 | if (fragP->tc_frag_data.classified) | |
10916 | return; | |
10917 | ||
10918 | /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert | |
10919 | FUSED_JCC_PADDING and merge BRANCH_PADDING. */ | |
10920 | for (next_fragP = fragP; | |
10921 | next_fragP != NULL; | |
10922 | next_fragP = next_fragP->fr_next) | |
10923 | { | |
10924 | next_fragP->tc_frag_data.classified = 1; | |
10925 | if (next_fragP->fr_type == rs_machine_dependent) | |
10926 | switch (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)) | |
10927 | { | |
10928 | case BRANCH_PADDING: | |
10929 | /* The BRANCH_PADDING frag must be followed by a branch | |
10930 | frag. */ | |
10931 | branch_fragP = i386_next_non_empty_frag (next_fragP); | |
10932 | next_fragP->tc_frag_data.u.branch_fragP = branch_fragP; | |
10933 | break; | |
10934 | case FUSED_JCC_PADDING: | |
10935 | /* Check if this is a fused jcc: | |
10936 | FUSED_JCC_PADDING | |
10937 | CMP like instruction | |
10938 | BRANCH_PADDING | |
10939 | COND_JUMP | |
10940 | */ | |
10941 | cmp_fragP = i386_next_non_empty_frag (next_fragP); | |
10942 | pad_fragP = i386_next_non_empty_frag (cmp_fragP); | |
10943 | branch_fragP = i386_next_jcc_frag (pad_fragP); | |
10944 | if (branch_fragP) | |
10945 | { | |
10946 | /* The BRANCH_PADDING frag is merged with the | |
10947 | FUSED_JCC_PADDING frag. */ | |
10948 | next_fragP->tc_frag_data.u.branch_fragP = branch_fragP; | |
10949 | /* CMP like instruction size. */ | |
10950 | next_fragP->tc_frag_data.cmp_size = cmp_fragP->fr_fix; | |
10951 | frag_wane (pad_fragP); | |
10952 | /* Skip to branch_fragP. */ | |
10953 | next_fragP = branch_fragP; | |
10954 | } | |
10955 | else if (next_fragP->tc_frag_data.max_prefix_length) | |
10956 | { | |
10957 | /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't | |
10958 | a fused jcc. */ | |
10959 | next_fragP->fr_subtype | |
10960 | = ENCODE_RELAX_STATE (BRANCH_PREFIX, 0); | |
10961 | next_fragP->tc_frag_data.max_bytes | |
10962 | = next_fragP->tc_frag_data.max_prefix_length; | |
10963 | /* This will be updated in the BRANCH_PREFIX scan. */ | |
10964 | next_fragP->tc_frag_data.max_prefix_length = 0; | |
10965 | } | |
10966 | else | |
10967 | frag_wane (next_fragP); | |
10968 | break; | |
10969 | } | |
10970 | } | |
10971 | ||
10972 | /* Stop if there is no BRANCH_PREFIX. */ | |
10973 | if (!align_branch_prefix_size) | |
10974 | return; | |
10975 | ||
10976 | /* Scan for BRANCH_PREFIX. */ | |
10977 | for (; fragP != NULL; fragP = fragP->fr_next) | |
10978 | { | |
10979 | if (fragP->fr_type != rs_machine_dependent | |
10980 | || (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
10981 | != BRANCH_PREFIX)) | |
10982 | continue; | |
10983 | ||
10984 | /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and | |
10985 | COND_JUMP_PREFIX. */ | |
10986 | max_prefix_length = 0; | |
10987 | for (next_fragP = fragP; | |
10988 | next_fragP != NULL; | |
10989 | next_fragP = next_fragP->fr_next) | |
10990 | { | |
10991 | if (next_fragP->fr_type == rs_fill) | |
10992 | /* Skip rs_fill frags. */ | |
10993 | continue; | |
10994 | else if (next_fragP->fr_type != rs_machine_dependent) | |
10995 | /* Stop for all other frags. */ | |
10996 | break; | |
10997 | ||
10998 | /* rs_machine_dependent frags. */ | |
10999 | if (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
11000 | == BRANCH_PREFIX) | |
11001 | { | |
11002 | /* Count BRANCH_PREFIX frags. */ | |
11003 | if (max_prefix_length >= MAX_FUSED_JCC_PADDING_SIZE) | |
11004 | { | |
11005 | max_prefix_length = MAX_FUSED_JCC_PADDING_SIZE; | |
11006 | frag_wane (next_fragP); | |
11007 | } | |
11008 | else | |
11009 | max_prefix_length | |
11010 | += next_fragP->tc_frag_data.max_bytes; | |
11011 | } | |
11012 | else if ((TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
11013 | == BRANCH_PADDING) | |
11014 | || (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
11015 | == FUSED_JCC_PADDING)) | |
11016 | { | |
11017 | /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */ | |
11018 | fragP->tc_frag_data.u.padding_fragP = next_fragP; | |
11019 | break; | |
11020 | } | |
11021 | else | |
11022 | /* Stop for other rs_machine_dependent frags. */ | |
11023 | break; | |
11024 | } | |
11025 | ||
11026 | fragP->tc_frag_data.max_prefix_length = max_prefix_length; | |
11027 | ||
11028 | /* Skip to the next frag. */ | |
11029 | fragP = next_fragP; | |
11030 | } | |
11031 | } | |
11032 | ||
11033 | /* Compute padding size for | |
11034 | ||
11035 | FUSED_JCC_PADDING | |
11036 | CMP like instruction | |
11037 | BRANCH_PADDING | |
11038 | COND_JUMP/UNCOND_JUMP | |
11039 | ||
11040 | or | |
11041 | ||
11042 | BRANCH_PADDING | |
11043 | COND_JUMP/UNCOND_JUMP | |
11044 | */ | |
11045 | ||
11046 | static int | |
11047 | i386_branch_padding_size (fragS *fragP, offsetT address) | |
11048 | { | |
11049 | unsigned int offset, size, padding_size; | |
11050 | fragS *branch_fragP = fragP->tc_frag_data.u.branch_fragP; | |
11051 | ||
11052 | /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */ | |
11053 | if (!address) | |
11054 | address = fragP->fr_address; | |
11055 | address += fragP->fr_fix; | |
11056 | ||
11057 | /* CMP like instrunction size. */ | |
11058 | size = fragP->tc_frag_data.cmp_size; | |
11059 | ||
11060 | /* The base size of the branch frag. */ | |
11061 | size += branch_fragP->fr_fix; | |
11062 | ||
11063 | /* Add opcode and displacement bytes for the rs_machine_dependent | |
11064 | branch frag. */ | |
11065 | if (branch_fragP->fr_type == rs_machine_dependent) | |
11066 | size += md_relax_table[branch_fragP->fr_subtype].rlx_length; | |
11067 | ||
11068 | /* Check if branch is within boundary and doesn't end at the last | |
11069 | byte. */ | |
11070 | offset = address & ((1U << align_branch_power) - 1); | |
11071 | if ((offset + size) >= (1U << align_branch_power)) | |
11072 | /* Padding needed to avoid crossing boundary. */ | |
11073 | padding_size = (1U << align_branch_power) - offset; | |
11074 | else | |
11075 | /* No padding needed. */ | |
11076 | padding_size = 0; | |
11077 | ||
11078 | /* The return value may be saved in tc_frag_data.length which is | |
11079 | unsigned byte. */ | |
11080 | if (!fits_in_unsigned_byte (padding_size)) | |
11081 | abort (); | |
11082 | ||
11083 | return padding_size; | |
11084 | } | |
11085 | ||
11086 | /* i386_generic_table_relax_frag() | |
11087 | ||
11088 | Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to | |
11089 | grow/shrink padding to align branch frags. Hand others to | |
11090 | relax_frag(). */ | |
11091 | ||
11092 | long | |
11093 | i386_generic_table_relax_frag (segT segment, fragS *fragP, long stretch) | |
11094 | { | |
11095 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING | |
11096 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
11097 | { | |
11098 | long padding_size = i386_branch_padding_size (fragP, 0); | |
11099 | long grow = padding_size - fragP->tc_frag_data.length; | |
11100 | ||
11101 | /* When the BRANCH_PREFIX frag is used, the computed address | |
11102 | must match the actual address and there should be no padding. */ | |
11103 | if (fragP->tc_frag_data.padding_address | |
11104 | && (fragP->tc_frag_data.padding_address != fragP->fr_address | |
11105 | || padding_size)) | |
11106 | abort (); | |
11107 | ||
11108 | /* Update the padding size. */ | |
11109 | if (grow) | |
11110 | fragP->tc_frag_data.length = padding_size; | |
11111 | ||
11112 | return grow; | |
11113 | } | |
11114 | else if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
11115 | { | |
11116 | fragS *padding_fragP, *next_fragP; | |
11117 | long padding_size, left_size, last_size; | |
11118 | ||
11119 | padding_fragP = fragP->tc_frag_data.u.padding_fragP; | |
11120 | if (!padding_fragP) | |
11121 | /* Use the padding set by the leading BRANCH_PREFIX frag. */ | |
11122 | return (fragP->tc_frag_data.length | |
11123 | - fragP->tc_frag_data.last_length); | |
11124 | ||
11125 | /* Compute the relative address of the padding frag in the very | |
11126 | first time where the BRANCH_PREFIX frag sizes are zero. */ | |
11127 | if (!fragP->tc_frag_data.padding_address) | |
11128 | fragP->tc_frag_data.padding_address | |
11129 | = padding_fragP->fr_address - (fragP->fr_address - stretch); | |
11130 | ||
11131 | /* First update the last length from the previous interation. */ | |
11132 | left_size = fragP->tc_frag_data.prefix_length; | |
11133 | for (next_fragP = fragP; | |
11134 | next_fragP != padding_fragP; | |
11135 | next_fragP = next_fragP->fr_next) | |
11136 | if (next_fragP->fr_type == rs_machine_dependent | |
11137 | && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
11138 | == BRANCH_PREFIX)) | |
11139 | { | |
11140 | if (left_size) | |
11141 | { | |
11142 | int max = next_fragP->tc_frag_data.max_bytes; | |
11143 | if (max) | |
11144 | { | |
11145 | int size; | |
11146 | if (max > left_size) | |
11147 | size = left_size; | |
11148 | else | |
11149 | size = max; | |
11150 | left_size -= size; | |
11151 | next_fragP->tc_frag_data.last_length = size; | |
11152 | } | |
11153 | } | |
11154 | else | |
11155 | next_fragP->tc_frag_data.last_length = 0; | |
11156 | } | |
11157 | ||
11158 | /* Check the padding size for the padding frag. */ | |
11159 | padding_size = i386_branch_padding_size | |
11160 | (padding_fragP, (fragP->fr_address | |
11161 | + fragP->tc_frag_data.padding_address)); | |
11162 | ||
11163 | last_size = fragP->tc_frag_data.prefix_length; | |
11164 | /* Check if there is change from the last interation. */ | |
11165 | if (padding_size == last_size) | |
11166 | { | |
11167 | /* Update the expected address of the padding frag. */ | |
11168 | padding_fragP->tc_frag_data.padding_address | |
11169 | = (fragP->fr_address + padding_size | |
11170 | + fragP->tc_frag_data.padding_address); | |
11171 | return 0; | |
11172 | } | |
11173 | ||
11174 | if (padding_size > fragP->tc_frag_data.max_prefix_length) | |
11175 | { | |
11176 | /* No padding if there is no sufficient room. Clear the | |
11177 | expected address of the padding frag. */ | |
11178 | padding_fragP->tc_frag_data.padding_address = 0; | |
11179 | padding_size = 0; | |
11180 | } | |
11181 | else | |
11182 | /* Store the expected address of the padding frag. */ | |
11183 | padding_fragP->tc_frag_data.padding_address | |
11184 | = (fragP->fr_address + padding_size | |
11185 | + fragP->tc_frag_data.padding_address); | |
11186 | ||
11187 | fragP->tc_frag_data.prefix_length = padding_size; | |
11188 | ||
11189 | /* Update the length for the current interation. */ | |
11190 | left_size = padding_size; | |
11191 | for (next_fragP = fragP; | |
11192 | next_fragP != padding_fragP; | |
11193 | next_fragP = next_fragP->fr_next) | |
11194 | if (next_fragP->fr_type == rs_machine_dependent | |
11195 | && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
11196 | == BRANCH_PREFIX)) | |
11197 | { | |
11198 | if (left_size) | |
11199 | { | |
11200 | int max = next_fragP->tc_frag_data.max_bytes; | |
11201 | if (max) | |
11202 | { | |
11203 | int size; | |
11204 | if (max > left_size) | |
11205 | size = left_size; | |
11206 | else | |
11207 | size = max; | |
11208 | left_size -= size; | |
11209 | next_fragP->tc_frag_data.length = size; | |
11210 | } | |
11211 | } | |
11212 | else | |
11213 | next_fragP->tc_frag_data.length = 0; | |
11214 | } | |
11215 | ||
11216 | return (fragP->tc_frag_data.length | |
11217 | - fragP->tc_frag_data.last_length); | |
11218 | } | |
11219 | return relax_frag (segment, fragP, stretch); | |
11220 | } | |
11221 | ||
ee7fcc42 AM |
11222 | /* md_estimate_size_before_relax() |
11223 | ||
11224 | Called just before relax() for rs_machine_dependent frags. The x86 | |
11225 | assembler uses these frags to handle variable size jump | |
11226 | instructions. | |
11227 | ||
11228 | Any symbol that is now undefined will not become defined. | |
11229 | Return the correct fr_subtype in the frag. | |
11230 | Return the initial "guess for variable size of frag" to caller. | |
11231 | The guess is actually the growth beyond the fixed part. Whatever | |
11232 | we do to grow the fixed or variable part contributes to our | |
11233 | returned value. */ | |
11234 | ||
252b5132 | 11235 | int |
7016a5d5 | 11236 | md_estimate_size_before_relax (fragS *fragP, segT segment) |
252b5132 | 11237 | { |
e379e5f3 L |
11238 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING |
11239 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX | |
11240 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
11241 | { | |
11242 | i386_classify_machine_dependent_frag (fragP); | |
11243 | return fragP->tc_frag_data.length; | |
11244 | } | |
11245 | ||
252b5132 | 11246 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
11247 | check for un-relaxable symbols. On an ELF system, we can't relax |
11248 | an externally visible symbol, because it may be overridden by a | |
11249 | shared library. */ | |
11250 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 11251 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 11252 | || (IS_ELF |
8dcea932 L |
11253 | && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol, |
11254 | fragP->fr_var)) | |
fbeb56a4 DK |
11255 | #endif |
11256 | #if defined (OBJ_COFF) && defined (TE_PE) | |
7ab9ffdd | 11257 | || (OUTPUT_FLAVOR == bfd_target_coff_flavour |
fbeb56a4 | 11258 | && S_IS_WEAK (fragP->fr_symbol)) |
b98ef147 AM |
11259 | #endif |
11260 | ) | |
252b5132 | 11261 | { |
b98ef147 AM |
11262 | /* Symbol is undefined in this segment, or we need to keep a |
11263 | reloc so that weak symbols can be overridden. */ | |
11264 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f86103b7 | 11265 | enum bfd_reloc_code_real reloc_type; |
ee7fcc42 AM |
11266 | unsigned char *opcode; |
11267 | int old_fr_fix; | |
f6af82bd | 11268 | |
ee7fcc42 | 11269 | if (fragP->fr_var != NO_RELOC) |
1e9cc1c2 | 11270 | reloc_type = (enum bfd_reloc_code_real) fragP->fr_var; |
b98ef147 | 11271 | else if (size == 2) |
f6af82bd | 11272 | reloc_type = BFD_RELOC_16_PCREL; |
bd7ab16b L |
11273 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
11274 | else if (need_plt32_p (fragP->fr_symbol)) | |
11275 | reloc_type = BFD_RELOC_X86_64_PLT32; | |
11276 | #endif | |
f6af82bd AM |
11277 | else |
11278 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 11279 | |
ee7fcc42 AM |
11280 | old_fr_fix = fragP->fr_fix; |
11281 | opcode = (unsigned char *) fragP->fr_opcode; | |
11282 | ||
fddf5b5b | 11283 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 11284 | { |
fddf5b5b AM |
11285 | case UNCOND_JUMP: |
11286 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 11287 | opcode[0] = 0xe9; |
252b5132 | 11288 | fragP->fr_fix += size; |
062cd5e7 AS |
11289 | fix_new (fragP, old_fr_fix, size, |
11290 | fragP->fr_symbol, | |
11291 | fragP->fr_offset, 1, | |
11292 | reloc_type); | |
252b5132 RH |
11293 | break; |
11294 | ||
fddf5b5b | 11295 | case COND_JUMP86: |
412167cb AM |
11296 | if (size == 2 |
11297 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) | |
fddf5b5b AM |
11298 | { |
11299 | /* Negate the condition, and branch past an | |
11300 | unconditional jump. */ | |
11301 | opcode[0] ^= 1; | |
11302 | opcode[1] = 3; | |
11303 | /* Insert an unconditional jump. */ | |
11304 | opcode[2] = 0xe9; | |
11305 | /* We added two extra opcode bytes, and have a two byte | |
11306 | offset. */ | |
11307 | fragP->fr_fix += 2 + 2; | |
062cd5e7 AS |
11308 | fix_new (fragP, old_fr_fix + 2, 2, |
11309 | fragP->fr_symbol, | |
11310 | fragP->fr_offset, 1, | |
11311 | reloc_type); | |
fddf5b5b AM |
11312 | break; |
11313 | } | |
11314 | /* Fall through. */ | |
11315 | ||
11316 | case COND_JUMP: | |
412167cb AM |
11317 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
11318 | { | |
3e02c1cc AM |
11319 | fixS *fixP; |
11320 | ||
412167cb | 11321 | fragP->fr_fix += 1; |
3e02c1cc AM |
11322 | fixP = fix_new (fragP, old_fr_fix, 1, |
11323 | fragP->fr_symbol, | |
11324 | fragP->fr_offset, 1, | |
11325 | BFD_RELOC_8_PCREL); | |
11326 | fixP->fx_signed = 1; | |
412167cb AM |
11327 | break; |
11328 | } | |
93c2a809 | 11329 | |
24eab124 | 11330 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 11331 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 11332 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 11333 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
11334 | /* We've added an opcode byte. */ |
11335 | fragP->fr_fix += 1 + size; | |
062cd5e7 AS |
11336 | fix_new (fragP, old_fr_fix + 1, size, |
11337 | fragP->fr_symbol, | |
11338 | fragP->fr_offset, 1, | |
11339 | reloc_type); | |
252b5132 | 11340 | break; |
fddf5b5b AM |
11341 | |
11342 | default: | |
11343 | BAD_CASE (fragP->fr_subtype); | |
11344 | break; | |
252b5132 RH |
11345 | } |
11346 | frag_wane (fragP); | |
ee7fcc42 | 11347 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 11348 | } |
93c2a809 | 11349 | |
93c2a809 AM |
11350 | /* Guess size depending on current relax state. Initially the relax |
11351 | state will correspond to a short jump and we return 1, because | |
11352 | the variable part of the frag (the branch offset) is one byte | |
11353 | long. However, we can relax a section more than once and in that | |
11354 | case we must either set fr_subtype back to the unrelaxed state, | |
11355 | or return the value for the appropriate branch. */ | |
11356 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
11357 | } |
11358 | ||
47926f60 KH |
11359 | /* Called after relax() is finished. |
11360 | ||
11361 | In: Address of frag. | |
11362 | fr_type == rs_machine_dependent. | |
11363 | fr_subtype is what the address relaxed to. | |
11364 | ||
11365 | Out: Any fixSs and constants are set up. | |
11366 | Caller will turn frag into a ".space 0". */ | |
11367 | ||
252b5132 | 11368 | void |
7016a5d5 TG |
11369 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, |
11370 | fragS *fragP) | |
252b5132 | 11371 | { |
29b0f896 | 11372 | unsigned char *opcode; |
252b5132 | 11373 | unsigned char *where_to_put_displacement = NULL; |
847f7ad4 AM |
11374 | offsetT target_address; |
11375 | offsetT opcode_address; | |
252b5132 | 11376 | unsigned int extension = 0; |
847f7ad4 | 11377 | offsetT displacement_from_opcode_start; |
252b5132 | 11378 | |
e379e5f3 L |
11379 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING |
11380 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING | |
11381 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
11382 | { | |
11383 | /* Generate nop padding. */ | |
11384 | unsigned int size = fragP->tc_frag_data.length; | |
11385 | if (size) | |
11386 | { | |
11387 | if (size > fragP->tc_frag_data.max_bytes) | |
11388 | abort (); | |
11389 | ||
11390 | if (flag_debug) | |
11391 | { | |
11392 | const char *msg; | |
11393 | const char *branch = "branch"; | |
11394 | const char *prefix = ""; | |
11395 | fragS *padding_fragP; | |
11396 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
11397 | == BRANCH_PREFIX) | |
11398 | { | |
11399 | padding_fragP = fragP->tc_frag_data.u.padding_fragP; | |
11400 | switch (fragP->tc_frag_data.default_prefix) | |
11401 | { | |
11402 | default: | |
11403 | abort (); | |
11404 | break; | |
11405 | case CS_PREFIX_OPCODE: | |
11406 | prefix = " cs"; | |
11407 | break; | |
11408 | case DS_PREFIX_OPCODE: | |
11409 | prefix = " ds"; | |
11410 | break; | |
11411 | case ES_PREFIX_OPCODE: | |
11412 | prefix = " es"; | |
11413 | break; | |
11414 | case FS_PREFIX_OPCODE: | |
11415 | prefix = " fs"; | |
11416 | break; | |
11417 | case GS_PREFIX_OPCODE: | |
11418 | prefix = " gs"; | |
11419 | break; | |
11420 | case SS_PREFIX_OPCODE: | |
11421 | prefix = " ss"; | |
11422 | break; | |
11423 | } | |
11424 | if (padding_fragP) | |
11425 | msg = _("%s:%u: add %d%s at 0x%llx to align " | |
11426 | "%s within %d-byte boundary\n"); | |
11427 | else | |
11428 | msg = _("%s:%u: add additional %d%s at 0x%llx to " | |
11429 | "align %s within %d-byte boundary\n"); | |
11430 | } | |
11431 | else | |
11432 | { | |
11433 | padding_fragP = fragP; | |
11434 | msg = _("%s:%u: add %d%s-byte nop at 0x%llx to align " | |
11435 | "%s within %d-byte boundary\n"); | |
11436 | } | |
11437 | ||
11438 | if (padding_fragP) | |
11439 | switch (padding_fragP->tc_frag_data.branch_type) | |
11440 | { | |
11441 | case align_branch_jcc: | |
11442 | branch = "jcc"; | |
11443 | break; | |
11444 | case align_branch_fused: | |
11445 | branch = "fused jcc"; | |
11446 | break; | |
11447 | case align_branch_jmp: | |
11448 | branch = "jmp"; | |
11449 | break; | |
11450 | case align_branch_call: | |
11451 | branch = "call"; | |
11452 | break; | |
11453 | case align_branch_indirect: | |
11454 | branch = "indiret branch"; | |
11455 | break; | |
11456 | case align_branch_ret: | |
11457 | branch = "ret"; | |
11458 | break; | |
11459 | default: | |
11460 | break; | |
11461 | } | |
11462 | ||
11463 | fprintf (stdout, msg, | |
11464 | fragP->fr_file, fragP->fr_line, size, prefix, | |
11465 | (long long) fragP->fr_address, branch, | |
11466 | 1 << align_branch_power); | |
11467 | } | |
11468 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
11469 | memset (fragP->fr_opcode, | |
11470 | fragP->tc_frag_data.default_prefix, size); | |
11471 | else | |
11472 | i386_generate_nops (fragP, (char *) fragP->fr_opcode, | |
11473 | size, 0); | |
11474 | fragP->fr_fix += size; | |
11475 | } | |
11476 | return; | |
11477 | } | |
11478 | ||
252b5132 RH |
11479 | opcode = (unsigned char *) fragP->fr_opcode; |
11480 | ||
47926f60 | 11481 | /* Address we want to reach in file space. */ |
252b5132 | 11482 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 11483 | |
47926f60 | 11484 | /* Address opcode resides at in file space. */ |
252b5132 RH |
11485 | opcode_address = fragP->fr_address + fragP->fr_fix; |
11486 | ||
47926f60 | 11487 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
11488 | displacement_from_opcode_start = target_address - opcode_address; |
11489 | ||
fddf5b5b | 11490 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 11491 | { |
47926f60 KH |
11492 | /* Don't have to change opcode. */ |
11493 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 11494 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
11495 | } |
11496 | else | |
11497 | { | |
11498 | if (no_cond_jump_promotion | |
11499 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4eed87de AM |
11500 | as_warn_where (fragP->fr_file, fragP->fr_line, |
11501 | _("long jump required")); | |
252b5132 | 11502 | |
fddf5b5b AM |
11503 | switch (fragP->fr_subtype) |
11504 | { | |
11505 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
11506 | extension = 4; /* 1 opcode + 4 displacement */ | |
11507 | opcode[0] = 0xe9; | |
11508 | where_to_put_displacement = &opcode[1]; | |
11509 | break; | |
252b5132 | 11510 | |
fddf5b5b AM |
11511 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
11512 | extension = 2; /* 1 opcode + 2 displacement */ | |
11513 | opcode[0] = 0xe9; | |
11514 | where_to_put_displacement = &opcode[1]; | |
11515 | break; | |
252b5132 | 11516 | |
fddf5b5b AM |
11517 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
11518 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
11519 | extension = 5; /* 2 opcode + 4 displacement */ | |
11520 | opcode[1] = opcode[0] + 0x10; | |
11521 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
11522 | where_to_put_displacement = &opcode[2]; | |
11523 | break; | |
252b5132 | 11524 | |
fddf5b5b AM |
11525 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
11526 | extension = 3; /* 2 opcode + 2 displacement */ | |
11527 | opcode[1] = opcode[0] + 0x10; | |
11528 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
11529 | where_to_put_displacement = &opcode[2]; | |
11530 | break; | |
252b5132 | 11531 | |
fddf5b5b AM |
11532 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
11533 | extension = 4; | |
11534 | opcode[0] ^= 1; | |
11535 | opcode[1] = 3; | |
11536 | opcode[2] = 0xe9; | |
11537 | where_to_put_displacement = &opcode[3]; | |
11538 | break; | |
11539 | ||
11540 | default: | |
11541 | BAD_CASE (fragP->fr_subtype); | |
11542 | break; | |
11543 | } | |
252b5132 | 11544 | } |
fddf5b5b | 11545 | |
7b81dfbb AJ |
11546 | /* If size if less then four we are sure that the operand fits, |
11547 | but if it's 4, then it could be that the displacement is larger | |
11548 | then -/+ 2GB. */ | |
11549 | if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 | |
11550 | && object_64bit | |
11551 | && ((addressT) (displacement_from_opcode_start - extension | |
4eed87de AM |
11552 | + ((addressT) 1 << 31)) |
11553 | > (((addressT) 2 << 31) - 1))) | |
7b81dfbb AJ |
11554 | { |
11555 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
11556 | _("jump target out of range")); | |
11557 | /* Make us emit 0. */ | |
11558 | displacement_from_opcode_start = extension; | |
11559 | } | |
47926f60 | 11560 | /* Now put displacement after opcode. */ |
252b5132 RH |
11561 | md_number_to_chars ((char *) where_to_put_displacement, |
11562 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 11563 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
11564 | fragP->fr_fix += extension; |
11565 | } | |
11566 | \f | |
7016a5d5 | 11567 | /* Apply a fixup (fixP) to segment data, once it has been determined |
252b5132 RH |
11568 | by our caller that we have all the info we need to fix it up. |
11569 | ||
7016a5d5 TG |
11570 | Parameter valP is the pointer to the value of the bits. |
11571 | ||
252b5132 RH |
11572 | On the 386, immediates, displacements, and data pointers are all in |
11573 | the same (little-endian) format, so we don't need to care about which | |
11574 | we are handling. */ | |
11575 | ||
94f592af | 11576 | void |
7016a5d5 | 11577 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 11578 | { |
94f592af | 11579 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
c6682705 | 11580 | valueT value = *valP; |
252b5132 | 11581 | |
f86103b7 | 11582 | #if !defined (TE_Mach) |
93382f6d AM |
11583 | if (fixP->fx_pcrel) |
11584 | { | |
11585 | switch (fixP->fx_r_type) | |
11586 | { | |
5865bb77 ILT |
11587 | default: |
11588 | break; | |
11589 | ||
d6ab8113 JB |
11590 | case BFD_RELOC_64: |
11591 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
11592 | break; | |
93382f6d | 11593 | case BFD_RELOC_32: |
ae8887b5 | 11594 | case BFD_RELOC_X86_64_32S: |
93382f6d AM |
11595 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
11596 | break; | |
11597 | case BFD_RELOC_16: | |
11598 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
11599 | break; | |
11600 | case BFD_RELOC_8: | |
11601 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
11602 | break; | |
11603 | } | |
11604 | } | |
252b5132 | 11605 | |
a161fe53 | 11606 | if (fixP->fx_addsy != NULL |
31312f95 | 11607 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
d6ab8113 | 11608 | || fixP->fx_r_type == BFD_RELOC_64_PCREL |
31312f95 | 11609 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
d258b828 | 11610 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) |
31312f95 | 11611 | && !use_rela_relocations) |
252b5132 | 11612 | { |
31312f95 AM |
11613 | /* This is a hack. There should be a better way to handle this. |
11614 | This covers for the fact that bfd_install_relocation will | |
11615 | subtract the current location (for partial_inplace, PC relative | |
11616 | relocations); see more below. */ | |
252b5132 | 11617 | #ifndef OBJ_AOUT |
718ddfc0 | 11618 | if (IS_ELF |
252b5132 RH |
11619 | #ifdef TE_PE |
11620 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
11621 | #endif | |
11622 | ) | |
11623 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
11624 | #endif | |
11625 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 11626 | if (IS_ELF) |
252b5132 | 11627 | { |
6539b54b | 11628 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
2f66722d | 11629 | |
6539b54b | 11630 | if ((sym_seg == seg |
2f66722d | 11631 | || (symbol_section_p (fixP->fx_addsy) |
6539b54b | 11632 | && sym_seg != absolute_section)) |
af65af87 | 11633 | && !generic_force_reloc (fixP)) |
2f66722d AM |
11634 | { |
11635 | /* Yes, we add the values in twice. This is because | |
6539b54b AM |
11636 | bfd_install_relocation subtracts them out again. I think |
11637 | bfd_install_relocation is broken, but I don't dare change | |
2f66722d AM |
11638 | it. FIXME. */ |
11639 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
11640 | } | |
252b5132 RH |
11641 | } |
11642 | #endif | |
11643 | #if defined (OBJ_COFF) && defined (TE_PE) | |
977cdf5a NC |
11644 | /* For some reason, the PE format does not store a |
11645 | section address offset for a PC relative symbol. */ | |
11646 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg | |
7be1c489 | 11647 | || S_IS_WEAK (fixP->fx_addsy)) |
252b5132 RH |
11648 | value += md_pcrel_from (fixP); |
11649 | #endif | |
11650 | } | |
fbeb56a4 | 11651 | #if defined (OBJ_COFF) && defined (TE_PE) |
f01c1a09 NC |
11652 | if (fixP->fx_addsy != NULL |
11653 | && S_IS_WEAK (fixP->fx_addsy) | |
11654 | /* PR 16858: Do not modify weak function references. */ | |
11655 | && ! fixP->fx_pcrel) | |
fbeb56a4 | 11656 | { |
296a8689 NC |
11657 | #if !defined (TE_PEP) |
11658 | /* For x86 PE weak function symbols are neither PC-relative | |
11659 | nor do they set S_IS_FUNCTION. So the only reliable way | |
11660 | to detect them is to check the flags of their containing | |
11661 | section. */ | |
11662 | if (S_GET_SEGMENT (fixP->fx_addsy) != NULL | |
11663 | && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE) | |
11664 | ; | |
11665 | else | |
11666 | #endif | |
fbeb56a4 DK |
11667 | value -= S_GET_VALUE (fixP->fx_addsy); |
11668 | } | |
11669 | #endif | |
252b5132 RH |
11670 | |
11671 | /* Fix a few things - the dynamic linker expects certain values here, | |
0234cb7c | 11672 | and we must not disappoint it. */ |
252b5132 | 11673 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 11674 | if (IS_ELF && fixP->fx_addsy) |
47926f60 KH |
11675 | switch (fixP->fx_r_type) |
11676 | { | |
11677 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 11678 | case BFD_RELOC_X86_64_PLT32: |
b9519cfe L |
11679 | /* Make the jump instruction point to the address of the operand. |
11680 | At runtime we merely add the offset to the actual PLT entry. | |
11681 | NB: Subtract the offset size only for jump instructions. */ | |
11682 | if (fixP->fx_pcrel) | |
11683 | value = -4; | |
47926f60 | 11684 | break; |
31312f95 | 11685 | |
13ae64f3 JJ |
11686 | case BFD_RELOC_386_TLS_GD: |
11687 | case BFD_RELOC_386_TLS_LDM: | |
13ae64f3 | 11688 | case BFD_RELOC_386_TLS_IE_32: |
37e55690 JJ |
11689 | case BFD_RELOC_386_TLS_IE: |
11690 | case BFD_RELOC_386_TLS_GOTIE: | |
67a4f2b7 | 11691 | case BFD_RELOC_386_TLS_GOTDESC: |
bffbf940 JJ |
11692 | case BFD_RELOC_X86_64_TLSGD: |
11693 | case BFD_RELOC_X86_64_TLSLD: | |
11694 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 | 11695 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
00f7efb6 JJ |
11696 | value = 0; /* Fully resolved at runtime. No addend. */ |
11697 | /* Fallthrough */ | |
11698 | case BFD_RELOC_386_TLS_LE: | |
11699 | case BFD_RELOC_386_TLS_LDO_32: | |
11700 | case BFD_RELOC_386_TLS_LE_32: | |
11701 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 11702 | case BFD_RELOC_X86_64_DTPOFF64: |
00f7efb6 | 11703 | case BFD_RELOC_X86_64_TPOFF32: |
d6ab8113 | 11704 | case BFD_RELOC_X86_64_TPOFF64: |
00f7efb6 JJ |
11705 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
11706 | break; | |
11707 | ||
67a4f2b7 AO |
11708 | case BFD_RELOC_386_TLS_DESC_CALL: |
11709 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
11710 | value = 0; /* Fully resolved at runtime. No addend. */ | |
11711 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
11712 | fixP->fx_done = 0; | |
11713 | return; | |
11714 | ||
47926f60 KH |
11715 | case BFD_RELOC_VTABLE_INHERIT: |
11716 | case BFD_RELOC_VTABLE_ENTRY: | |
11717 | fixP->fx_done = 0; | |
94f592af | 11718 | return; |
47926f60 KH |
11719 | |
11720 | default: | |
11721 | break; | |
11722 | } | |
11723 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
c6682705 | 11724 | *valP = value; |
f86103b7 | 11725 | #endif /* !defined (TE_Mach) */ |
3e73aa7c | 11726 | |
3e73aa7c | 11727 | /* Are we finished with this relocation now? */ |
c6682705 | 11728 | if (fixP->fx_addsy == NULL) |
3e73aa7c | 11729 | fixP->fx_done = 1; |
fbeb56a4 DK |
11730 | #if defined (OBJ_COFF) && defined (TE_PE) |
11731 | else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) | |
11732 | { | |
11733 | fixP->fx_done = 0; | |
11734 | /* Remember value for tc_gen_reloc. */ | |
11735 | fixP->fx_addnumber = value; | |
11736 | /* Clear out the frag for now. */ | |
11737 | value = 0; | |
11738 | } | |
11739 | #endif | |
3e73aa7c JH |
11740 | else if (use_rela_relocations) |
11741 | { | |
11742 | fixP->fx_no_overflow = 1; | |
062cd5e7 AS |
11743 | /* Remember value for tc_gen_reloc. */ |
11744 | fixP->fx_addnumber = value; | |
3e73aa7c JH |
11745 | value = 0; |
11746 | } | |
f86103b7 | 11747 | |
94f592af | 11748 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 11749 | } |
252b5132 | 11750 | \f |
6d4af3c2 | 11751 | const char * |
499ac353 | 11752 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 11753 | { |
499ac353 NC |
11754 | /* This outputs the LITTLENUMs in REVERSE order; |
11755 | in accord with the bigendian 386. */ | |
11756 | return ieee_md_atof (type, litP, sizeP, FALSE); | |
252b5132 RH |
11757 | } |
11758 | \f | |
2d545b82 | 11759 | static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; |
252b5132 | 11760 | |
252b5132 | 11761 | static char * |
e3bb37b5 | 11762 | output_invalid (int c) |
252b5132 | 11763 | { |
3882b010 | 11764 | if (ISPRINT (c)) |
f9f21a03 L |
11765 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
11766 | "'%c'", c); | |
252b5132 | 11767 | else |
f9f21a03 | 11768 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
2d545b82 | 11769 | "(0x%x)", (unsigned char) c); |
252b5132 RH |
11770 | return output_invalid_buf; |
11771 | } | |
11772 | ||
af6bdddf | 11773 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
11774 | |
11775 | static const reg_entry * | |
4d1bb795 | 11776 | parse_real_register (char *reg_string, char **end_op) |
252b5132 | 11777 | { |
af6bdddf AM |
11778 | char *s = reg_string; |
11779 | char *p; | |
252b5132 RH |
11780 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
11781 | const reg_entry *r; | |
11782 | ||
11783 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
11784 | if (*s == REGISTER_PREFIX) | |
11785 | ++s; | |
11786 | ||
11787 | if (is_space_char (*s)) | |
11788 | ++s; | |
11789 | ||
11790 | p = reg_name_given; | |
af6bdddf | 11791 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
11792 | { |
11793 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
11794 | return (const reg_entry *) NULL; |
11795 | s++; | |
252b5132 RH |
11796 | } |
11797 | ||
6588847e DN |
11798 | /* For naked regs, make sure that we are not dealing with an identifier. |
11799 | This prevents confusing an identifier like `eax_var' with register | |
11800 | `eax'. */ | |
11801 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
11802 | return (const reg_entry *) NULL; | |
11803 | ||
af6bdddf | 11804 | *end_op = s; |
252b5132 RH |
11805 | |
11806 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
11807 | ||
5f47d35b | 11808 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
47926f60 | 11809 | if (r == i386_regtab /* %st is first entry of table */) |
5f47d35b | 11810 | { |
0e0eea78 JB |
11811 | if (!cpu_arch_flags.bitfield.cpu8087 |
11812 | && !cpu_arch_flags.bitfield.cpu287 | |
11813 | && !cpu_arch_flags.bitfield.cpu387) | |
11814 | return (const reg_entry *) NULL; | |
11815 | ||
5f47d35b AM |
11816 | if (is_space_char (*s)) |
11817 | ++s; | |
11818 | if (*s == '(') | |
11819 | { | |
af6bdddf | 11820 | ++s; |
5f47d35b AM |
11821 | if (is_space_char (*s)) |
11822 | ++s; | |
11823 | if (*s >= '0' && *s <= '7') | |
11824 | { | |
db557034 | 11825 | int fpr = *s - '0'; |
af6bdddf | 11826 | ++s; |
5f47d35b AM |
11827 | if (is_space_char (*s)) |
11828 | ++s; | |
11829 | if (*s == ')') | |
11830 | { | |
11831 | *end_op = s + 1; | |
1e9cc1c2 | 11832 | r = (const reg_entry *) hash_find (reg_hash, "st(0)"); |
db557034 AM |
11833 | know (r); |
11834 | return r + fpr; | |
5f47d35b | 11835 | } |
5f47d35b | 11836 | } |
47926f60 | 11837 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
11838 | return (const reg_entry *) NULL; |
11839 | } | |
11840 | } | |
11841 | ||
a60de03c JB |
11842 | if (r == NULL || allow_pseudo_reg) |
11843 | return r; | |
11844 | ||
0dfbf9d7 | 11845 | if (operand_type_all_zero (&r->reg_type)) |
a60de03c JB |
11846 | return (const reg_entry *) NULL; |
11847 | ||
dc821c5f | 11848 | if ((r->reg_type.bitfield.dword |
00cee14f | 11849 | || (r->reg_type.bitfield.class == SReg && r->reg_num > 3) |
4a5c67ed JB |
11850 | || r->reg_type.bitfield.class == RegCR |
11851 | || r->reg_type.bitfield.class == RegDR | |
11852 | || r->reg_type.bitfield.class == RegTR) | |
192dc9c6 JB |
11853 | && !cpu_arch_flags.bitfield.cpui386) |
11854 | return (const reg_entry *) NULL; | |
11855 | ||
3528c362 | 11856 | if (r->reg_type.bitfield.class == RegMMX && !cpu_arch_flags.bitfield.cpummx) |
192dc9c6 JB |
11857 | return (const reg_entry *) NULL; |
11858 | ||
6e041cf4 JB |
11859 | if (!cpu_arch_flags.bitfield.cpuavx512f) |
11860 | { | |
f74a6307 JB |
11861 | if (r->reg_type.bitfield.zmmword |
11862 | || r->reg_type.bitfield.class == RegMask) | |
6e041cf4 | 11863 | return (const reg_entry *) NULL; |
40f12533 | 11864 | |
6e041cf4 JB |
11865 | if (!cpu_arch_flags.bitfield.cpuavx) |
11866 | { | |
11867 | if (r->reg_type.bitfield.ymmword) | |
11868 | return (const reg_entry *) NULL; | |
1848e567 | 11869 | |
6e041cf4 JB |
11870 | if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword) |
11871 | return (const reg_entry *) NULL; | |
11872 | } | |
11873 | } | |
43234a1e | 11874 | |
f74a6307 | 11875 | if (r->reg_type.bitfield.class == RegBND && !cpu_arch_flags.bitfield.cpumpx) |
1adf7f56 JB |
11876 | return (const reg_entry *) NULL; |
11877 | ||
db51cc60 | 11878 | /* Don't allow fake index register unless allow_index_reg isn't 0. */ |
e968fc9b | 11879 | if (!allow_index_reg && r->reg_num == RegIZ) |
db51cc60 L |
11880 | return (const reg_entry *) NULL; |
11881 | ||
1d3f8286 JB |
11882 | /* Upper 16 vector registers are only available with VREX in 64bit |
11883 | mode, and require EVEX encoding. */ | |
11884 | if (r->reg_flags & RegVRex) | |
43234a1e | 11885 | { |
e951d5ca | 11886 | if (!cpu_arch_flags.bitfield.cpuavx512f |
43234a1e L |
11887 | || flag_code != CODE_64BIT) |
11888 | return (const reg_entry *) NULL; | |
1d3f8286 JB |
11889 | |
11890 | i.vec_encoding = vex_encoding_evex; | |
43234a1e L |
11891 | } |
11892 | ||
4787f4a5 | 11893 | if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword) |
4a5c67ed | 11894 | && (!cpu_arch_flags.bitfield.cpulm || r->reg_type.bitfield.class != RegCR) |
1ae00879 | 11895 | && flag_code != CODE_64BIT) |
20f0a1fc | 11896 | return (const reg_entry *) NULL; |
1ae00879 | 11897 | |
00cee14f JB |
11898 | if (r->reg_type.bitfield.class == SReg && r->reg_num == RegFlat |
11899 | && !intel_syntax) | |
b7240065 JB |
11900 | return (const reg_entry *) NULL; |
11901 | ||
252b5132 RH |
11902 | return r; |
11903 | } | |
4d1bb795 JB |
11904 | |
11905 | /* REG_STRING starts *before* REGISTER_PREFIX. */ | |
11906 | ||
11907 | static const reg_entry * | |
11908 | parse_register (char *reg_string, char **end_op) | |
11909 | { | |
11910 | const reg_entry *r; | |
11911 | ||
11912 | if (*reg_string == REGISTER_PREFIX || allow_naked_reg) | |
11913 | r = parse_real_register (reg_string, end_op); | |
11914 | else | |
11915 | r = NULL; | |
11916 | if (!r) | |
11917 | { | |
11918 | char *save = input_line_pointer; | |
11919 | char c; | |
11920 | symbolS *symbolP; | |
11921 | ||
11922 | input_line_pointer = reg_string; | |
d02603dc | 11923 | c = get_symbol_name (®_string); |
4d1bb795 JB |
11924 | symbolP = symbol_find (reg_string); |
11925 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) | |
11926 | { | |
11927 | const expressionS *e = symbol_get_value_expression (symbolP); | |
11928 | ||
0398aac5 | 11929 | know (e->X_op == O_register); |
4eed87de | 11930 | know (e->X_add_number >= 0 |
c3fe08fa | 11931 | && (valueT) e->X_add_number < i386_regtab_size); |
4d1bb795 | 11932 | r = i386_regtab + e->X_add_number; |
d3bb6b49 | 11933 | if ((r->reg_flags & RegVRex)) |
86fa6981 | 11934 | i.vec_encoding = vex_encoding_evex; |
4d1bb795 JB |
11935 | *end_op = input_line_pointer; |
11936 | } | |
11937 | *input_line_pointer = c; | |
11938 | input_line_pointer = save; | |
11939 | } | |
11940 | return r; | |
11941 | } | |
11942 | ||
11943 | int | |
11944 | i386_parse_name (char *name, expressionS *e, char *nextcharP) | |
11945 | { | |
11946 | const reg_entry *r; | |
11947 | char *end = input_line_pointer; | |
11948 | ||
11949 | *end = *nextcharP; | |
11950 | r = parse_register (name, &input_line_pointer); | |
11951 | if (r && end <= input_line_pointer) | |
11952 | { | |
11953 | *nextcharP = *input_line_pointer; | |
11954 | *input_line_pointer = 0; | |
11955 | e->X_op = O_register; | |
11956 | e->X_add_number = r - i386_regtab; | |
11957 | return 1; | |
11958 | } | |
11959 | input_line_pointer = end; | |
11960 | *end = 0; | |
ee86248c | 11961 | return intel_syntax ? i386_intel_parse_name (name, e) : 0; |
4d1bb795 JB |
11962 | } |
11963 | ||
11964 | void | |
11965 | md_operand (expressionS *e) | |
11966 | { | |
ee86248c JB |
11967 | char *end; |
11968 | const reg_entry *r; | |
4d1bb795 | 11969 | |
ee86248c JB |
11970 | switch (*input_line_pointer) |
11971 | { | |
11972 | case REGISTER_PREFIX: | |
11973 | r = parse_real_register (input_line_pointer, &end); | |
4d1bb795 JB |
11974 | if (r) |
11975 | { | |
11976 | e->X_op = O_register; | |
11977 | e->X_add_number = r - i386_regtab; | |
11978 | input_line_pointer = end; | |
11979 | } | |
ee86248c JB |
11980 | break; |
11981 | ||
11982 | case '[': | |
9c2799c2 | 11983 | gas_assert (intel_syntax); |
ee86248c JB |
11984 | end = input_line_pointer++; |
11985 | expression (e); | |
11986 | if (*input_line_pointer == ']') | |
11987 | { | |
11988 | ++input_line_pointer; | |
11989 | e->X_op_symbol = make_expr_symbol (e); | |
11990 | e->X_add_symbol = NULL; | |
11991 | e->X_add_number = 0; | |
11992 | e->X_op = O_index; | |
11993 | } | |
11994 | else | |
11995 | { | |
11996 | e->X_op = O_absent; | |
11997 | input_line_pointer = end; | |
11998 | } | |
11999 | break; | |
4d1bb795 JB |
12000 | } |
12001 | } | |
12002 | ||
252b5132 | 12003 | \f |
4cc782b5 | 12004 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
b6f8c7c4 | 12005 | const char *md_shortopts = "kVQ:sqnO::"; |
252b5132 | 12006 | #else |
b6f8c7c4 | 12007 | const char *md_shortopts = "qnO::"; |
252b5132 | 12008 | #endif |
6e0b89ee | 12009 | |
3e73aa7c | 12010 | #define OPTION_32 (OPTION_MD_BASE + 0) |
b3b91714 AM |
12011 | #define OPTION_64 (OPTION_MD_BASE + 1) |
12012 | #define OPTION_DIVIDE (OPTION_MD_BASE + 2) | |
9103f4f4 L |
12013 | #define OPTION_MARCH (OPTION_MD_BASE + 3) |
12014 | #define OPTION_MTUNE (OPTION_MD_BASE + 4) | |
1efbbeb4 L |
12015 | #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) |
12016 | #define OPTION_MSYNTAX (OPTION_MD_BASE + 6) | |
12017 | #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) | |
12018 | #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) | |
bd5dea88 | 12019 | #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9) |
c0f3af97 | 12020 | #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10) |
daf50ae7 | 12021 | #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11) |
7bab8ab5 JB |
12022 | #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12) |
12023 | #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13) | |
12024 | #define OPTION_X32 (OPTION_MD_BASE + 14) | |
7e8b059b | 12025 | #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15) |
43234a1e L |
12026 | #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16) |
12027 | #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17) | |
167ad85b | 12028 | #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18) |
d1982f93 | 12029 | #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19) |
d3d3c6db | 12030 | #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20) |
8dcea932 | 12031 | #define OPTION_MSHARED (OPTION_MD_BASE + 21) |
5db04b09 L |
12032 | #define OPTION_MAMD64 (OPTION_MD_BASE + 22) |
12033 | #define OPTION_MINTEL64 (OPTION_MD_BASE + 23) | |
e4e00185 | 12034 | #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24) |
b4a3a7b4 | 12035 | #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25) |
03751133 | 12036 | #define OPTION_MVEXWIG (OPTION_MD_BASE + 26) |
e379e5f3 L |
12037 | #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27) |
12038 | #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28) | |
12039 | #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29) | |
76cf450b | 12040 | #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30) |
b3b91714 | 12041 | |
99ad8390 NC |
12042 | struct option md_longopts[] = |
12043 | { | |
3e73aa7c | 12044 | {"32", no_argument, NULL, OPTION_32}, |
321098a5 | 12045 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 12046 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c | 12047 | {"64", no_argument, NULL, OPTION_64}, |
351f65ca L |
12048 | #endif |
12049 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
570561f7 | 12050 | {"x32", no_argument, NULL, OPTION_X32}, |
8dcea932 | 12051 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
b4a3a7b4 | 12052 | {"mx86-used-note", required_argument, NULL, OPTION_X86_USED_NOTE}, |
6e0b89ee | 12053 | #endif |
b3b91714 | 12054 | {"divide", no_argument, NULL, OPTION_DIVIDE}, |
9103f4f4 L |
12055 | {"march", required_argument, NULL, OPTION_MARCH}, |
12056 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1efbbeb4 L |
12057 | {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, |
12058 | {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, | |
12059 | {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, | |
12060 | {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, | |
c0f3af97 | 12061 | {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX}, |
daf50ae7 | 12062 | {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK}, |
7bab8ab5 | 12063 | {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK}, |
539f890d | 12064 | {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR}, |
03751133 | 12065 | {"mvexwig", required_argument, NULL, OPTION_MVEXWIG}, |
7e8b059b | 12066 | {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX}, |
43234a1e L |
12067 | {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG}, |
12068 | {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG}, | |
167ad85b TG |
12069 | # if defined (TE_PE) || defined (TE_PEP) |
12070 | {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ}, | |
12071 | #endif | |
d1982f93 | 12072 | {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX}, |
e4e00185 | 12073 | {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD}, |
0cb4071e | 12074 | {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS}, |
d3d3c6db | 12075 | {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG}, |
e379e5f3 L |
12076 | {"malign-branch-boundary", required_argument, NULL, OPTION_MALIGN_BRANCH_BOUNDARY}, |
12077 | {"malign-branch-prefix-size", required_argument, NULL, OPTION_MALIGN_BRANCH_PREFIX_SIZE}, | |
12078 | {"malign-branch", required_argument, NULL, OPTION_MALIGN_BRANCH}, | |
76cf450b | 12079 | {"mbranches-within-32B-boundaries", no_argument, NULL, OPTION_MBRANCHES_WITH_32B_BOUNDARIES}, |
5db04b09 L |
12080 | {"mamd64", no_argument, NULL, OPTION_MAMD64}, |
12081 | {"mintel64", no_argument, NULL, OPTION_MINTEL64}, | |
252b5132 RH |
12082 | {NULL, no_argument, NULL, 0} |
12083 | }; | |
12084 | size_t md_longopts_size = sizeof (md_longopts); | |
12085 | ||
12086 | int | |
17b9d67d | 12087 | md_parse_option (int c, const char *arg) |
252b5132 | 12088 | { |
91d6fa6a | 12089 | unsigned int j; |
e379e5f3 | 12090 | char *arch, *next, *saved, *type; |
9103f4f4 | 12091 | |
252b5132 RH |
12092 | switch (c) |
12093 | { | |
12b55ccc L |
12094 | case 'n': |
12095 | optimize_align_code = 0; | |
12096 | break; | |
12097 | ||
a38cf1db AM |
12098 | case 'q': |
12099 | quiet_warnings = 1; | |
252b5132 RH |
12100 | break; |
12101 | ||
12102 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
12103 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
12104 | should be emitted or not. FIXME: Not implemented. */ | |
12105 | case 'Q': | |
d4693039 JB |
12106 | if ((arg[0] != 'y' && arg[0] != 'n') || arg[1]) |
12107 | return 0; | |
252b5132 RH |
12108 | break; |
12109 | ||
12110 | /* -V: SVR4 argument to print version ID. */ | |
12111 | case 'V': | |
12112 | print_version_id (); | |
12113 | break; | |
12114 | ||
a38cf1db AM |
12115 | /* -k: Ignore for FreeBSD compatibility. */ |
12116 | case 'k': | |
252b5132 | 12117 | break; |
4cc782b5 ILT |
12118 | |
12119 | case 's': | |
12120 | /* -s: On i386 Solaris, this tells the native assembler to use | |
29b0f896 | 12121 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
4cc782b5 | 12122 | break; |
8dcea932 L |
12123 | |
12124 | case OPTION_MSHARED: | |
12125 | shared = 1; | |
12126 | break; | |
b4a3a7b4 L |
12127 | |
12128 | case OPTION_X86_USED_NOTE: | |
12129 | if (strcasecmp (arg, "yes") == 0) | |
12130 | x86_used_note = 1; | |
12131 | else if (strcasecmp (arg, "no") == 0) | |
12132 | x86_used_note = 0; | |
12133 | else | |
12134 | as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg); | |
12135 | break; | |
12136 | ||
12137 | ||
99ad8390 | 12138 | #endif |
321098a5 | 12139 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 12140 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c JH |
12141 | case OPTION_64: |
12142 | { | |
12143 | const char **list, **l; | |
12144 | ||
3e73aa7c JH |
12145 | list = bfd_target_list (); |
12146 | for (l = list; *l != NULL; l++) | |
8620418b | 12147 | if (CONST_STRNEQ (*l, "elf64-x86-64") |
99ad8390 NC |
12148 | || strcmp (*l, "coff-x86-64") == 0 |
12149 | || strcmp (*l, "pe-x86-64") == 0 | |
d382c579 TG |
12150 | || strcmp (*l, "pei-x86-64") == 0 |
12151 | || strcmp (*l, "mach-o-x86-64") == 0) | |
6e0b89ee AM |
12152 | { |
12153 | default_arch = "x86_64"; | |
12154 | break; | |
12155 | } | |
3e73aa7c | 12156 | if (*l == NULL) |
2b5d6a91 | 12157 | as_fatal (_("no compiled in support for x86_64")); |
3e73aa7c JH |
12158 | free (list); |
12159 | } | |
12160 | break; | |
12161 | #endif | |
252b5132 | 12162 | |
351f65ca | 12163 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
570561f7 | 12164 | case OPTION_X32: |
351f65ca L |
12165 | if (IS_ELF) |
12166 | { | |
12167 | const char **list, **l; | |
12168 | ||
12169 | list = bfd_target_list (); | |
12170 | for (l = list; *l != NULL; l++) | |
12171 | if (CONST_STRNEQ (*l, "elf32-x86-64")) | |
12172 | { | |
12173 | default_arch = "x86_64:32"; | |
12174 | break; | |
12175 | } | |
12176 | if (*l == NULL) | |
2b5d6a91 | 12177 | as_fatal (_("no compiled in support for 32bit x86_64")); |
351f65ca L |
12178 | free (list); |
12179 | } | |
12180 | else | |
12181 | as_fatal (_("32bit x86_64 is only supported for ELF")); | |
12182 | break; | |
12183 | #endif | |
12184 | ||
6e0b89ee AM |
12185 | case OPTION_32: |
12186 | default_arch = "i386"; | |
12187 | break; | |
12188 | ||
b3b91714 AM |
12189 | case OPTION_DIVIDE: |
12190 | #ifdef SVR4_COMMENT_CHARS | |
12191 | { | |
12192 | char *n, *t; | |
12193 | const char *s; | |
12194 | ||
add39d23 | 12195 | n = XNEWVEC (char, strlen (i386_comment_chars) + 1); |
b3b91714 AM |
12196 | t = n; |
12197 | for (s = i386_comment_chars; *s != '\0'; s++) | |
12198 | if (*s != '/') | |
12199 | *t++ = *s; | |
12200 | *t = '\0'; | |
12201 | i386_comment_chars = n; | |
12202 | } | |
12203 | #endif | |
12204 | break; | |
12205 | ||
9103f4f4 | 12206 | case OPTION_MARCH: |
293f5f65 L |
12207 | saved = xstrdup (arg); |
12208 | arch = saved; | |
12209 | /* Allow -march=+nosse. */ | |
12210 | if (*arch == '+') | |
12211 | arch++; | |
6305a203 | 12212 | do |
9103f4f4 | 12213 | { |
6305a203 | 12214 | if (*arch == '.') |
2b5d6a91 | 12215 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
12216 | next = strchr (arch, '+'); |
12217 | if (next) | |
12218 | *next++ = '\0'; | |
91d6fa6a | 12219 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 12220 | { |
91d6fa6a | 12221 | if (strcmp (arch, cpu_arch [j].name) == 0) |
ccc9c027 | 12222 | { |
6305a203 | 12223 | /* Processor. */ |
1ded5609 JB |
12224 | if (! cpu_arch[j].flags.bitfield.cpui386) |
12225 | continue; | |
12226 | ||
91d6fa6a | 12227 | cpu_arch_name = cpu_arch[j].name; |
6305a203 | 12228 | cpu_sub_arch_name = NULL; |
91d6fa6a NC |
12229 | cpu_arch_flags = cpu_arch[j].flags; |
12230 | cpu_arch_isa = cpu_arch[j].type; | |
12231 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
6305a203 L |
12232 | if (!cpu_arch_tune_set) |
12233 | { | |
12234 | cpu_arch_tune = cpu_arch_isa; | |
12235 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
12236 | } | |
12237 | break; | |
12238 | } | |
91d6fa6a NC |
12239 | else if (*cpu_arch [j].name == '.' |
12240 | && strcmp (arch, cpu_arch [j].name + 1) == 0) | |
6305a203 | 12241 | { |
33eaf5de | 12242 | /* ISA extension. */ |
6305a203 | 12243 | i386_cpu_flags flags; |
309d3373 | 12244 | |
293f5f65 L |
12245 | flags = cpu_flags_or (cpu_arch_flags, |
12246 | cpu_arch[j].flags); | |
81486035 | 12247 | |
5b64d091 | 12248 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
6305a203 L |
12249 | { |
12250 | if (cpu_sub_arch_name) | |
12251 | { | |
12252 | char *name = cpu_sub_arch_name; | |
12253 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 12254 | cpu_arch[j].name, |
1bf57e9f | 12255 | (const char *) NULL); |
6305a203 L |
12256 | free (name); |
12257 | } | |
12258 | else | |
91d6fa6a | 12259 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
6305a203 | 12260 | cpu_arch_flags = flags; |
a586129e | 12261 | cpu_arch_isa_flags = flags; |
6305a203 | 12262 | } |
0089dace L |
12263 | else |
12264 | cpu_arch_isa_flags | |
12265 | = cpu_flags_or (cpu_arch_isa_flags, | |
12266 | cpu_arch[j].flags); | |
6305a203 | 12267 | break; |
ccc9c027 | 12268 | } |
9103f4f4 | 12269 | } |
6305a203 | 12270 | |
293f5f65 L |
12271 | if (j >= ARRAY_SIZE (cpu_arch)) |
12272 | { | |
33eaf5de | 12273 | /* Disable an ISA extension. */ |
293f5f65 L |
12274 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
12275 | if (strcmp (arch, cpu_noarch [j].name) == 0) | |
12276 | { | |
12277 | i386_cpu_flags flags; | |
12278 | ||
12279 | flags = cpu_flags_and_not (cpu_arch_flags, | |
12280 | cpu_noarch[j].flags); | |
12281 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
12282 | { | |
12283 | if (cpu_sub_arch_name) | |
12284 | { | |
12285 | char *name = cpu_sub_arch_name; | |
12286 | cpu_sub_arch_name = concat (arch, | |
12287 | (const char *) NULL); | |
12288 | free (name); | |
12289 | } | |
12290 | else | |
12291 | cpu_sub_arch_name = xstrdup (arch); | |
12292 | cpu_arch_flags = flags; | |
12293 | cpu_arch_isa_flags = flags; | |
12294 | } | |
12295 | break; | |
12296 | } | |
12297 | ||
12298 | if (j >= ARRAY_SIZE (cpu_noarch)) | |
12299 | j = ARRAY_SIZE (cpu_arch); | |
12300 | } | |
12301 | ||
91d6fa6a | 12302 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 12303 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
12304 | |
12305 | arch = next; | |
9103f4f4 | 12306 | } |
293f5f65 L |
12307 | while (next != NULL); |
12308 | free (saved); | |
9103f4f4 L |
12309 | break; |
12310 | ||
12311 | case OPTION_MTUNE: | |
12312 | if (*arg == '.') | |
2b5d6a91 | 12313 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
91d6fa6a | 12314 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 12315 | { |
91d6fa6a | 12316 | if (strcmp (arg, cpu_arch [j].name) == 0) |
9103f4f4 | 12317 | { |
ccc9c027 | 12318 | cpu_arch_tune_set = 1; |
91d6fa6a NC |
12319 | cpu_arch_tune = cpu_arch [j].type; |
12320 | cpu_arch_tune_flags = cpu_arch[j].flags; | |
9103f4f4 L |
12321 | break; |
12322 | } | |
12323 | } | |
91d6fa6a | 12324 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 12325 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
9103f4f4 L |
12326 | break; |
12327 | ||
1efbbeb4 L |
12328 | case OPTION_MMNEMONIC: |
12329 | if (strcasecmp (arg, "att") == 0) | |
12330 | intel_mnemonic = 0; | |
12331 | else if (strcasecmp (arg, "intel") == 0) | |
12332 | intel_mnemonic = 1; | |
12333 | else | |
2b5d6a91 | 12334 | as_fatal (_("invalid -mmnemonic= option: `%s'"), arg); |
1efbbeb4 L |
12335 | break; |
12336 | ||
12337 | case OPTION_MSYNTAX: | |
12338 | if (strcasecmp (arg, "att") == 0) | |
12339 | intel_syntax = 0; | |
12340 | else if (strcasecmp (arg, "intel") == 0) | |
12341 | intel_syntax = 1; | |
12342 | else | |
2b5d6a91 | 12343 | as_fatal (_("invalid -msyntax= option: `%s'"), arg); |
1efbbeb4 L |
12344 | break; |
12345 | ||
12346 | case OPTION_MINDEX_REG: | |
12347 | allow_index_reg = 1; | |
12348 | break; | |
12349 | ||
12350 | case OPTION_MNAKED_REG: | |
12351 | allow_naked_reg = 1; | |
12352 | break; | |
12353 | ||
c0f3af97 L |
12354 | case OPTION_MSSE2AVX: |
12355 | sse2avx = 1; | |
12356 | break; | |
12357 | ||
daf50ae7 L |
12358 | case OPTION_MSSE_CHECK: |
12359 | if (strcasecmp (arg, "error") == 0) | |
7bab8ab5 | 12360 | sse_check = check_error; |
daf50ae7 | 12361 | else if (strcasecmp (arg, "warning") == 0) |
7bab8ab5 | 12362 | sse_check = check_warning; |
daf50ae7 | 12363 | else if (strcasecmp (arg, "none") == 0) |
7bab8ab5 | 12364 | sse_check = check_none; |
daf50ae7 | 12365 | else |
2b5d6a91 | 12366 | as_fatal (_("invalid -msse-check= option: `%s'"), arg); |
daf50ae7 L |
12367 | break; |
12368 | ||
7bab8ab5 JB |
12369 | case OPTION_MOPERAND_CHECK: |
12370 | if (strcasecmp (arg, "error") == 0) | |
12371 | operand_check = check_error; | |
12372 | else if (strcasecmp (arg, "warning") == 0) | |
12373 | operand_check = check_warning; | |
12374 | else if (strcasecmp (arg, "none") == 0) | |
12375 | operand_check = check_none; | |
12376 | else | |
12377 | as_fatal (_("invalid -moperand-check= option: `%s'"), arg); | |
12378 | break; | |
12379 | ||
539f890d L |
12380 | case OPTION_MAVXSCALAR: |
12381 | if (strcasecmp (arg, "128") == 0) | |
12382 | avxscalar = vex128; | |
12383 | else if (strcasecmp (arg, "256") == 0) | |
12384 | avxscalar = vex256; | |
12385 | else | |
2b5d6a91 | 12386 | as_fatal (_("invalid -mavxscalar= option: `%s'"), arg); |
539f890d L |
12387 | break; |
12388 | ||
03751133 L |
12389 | case OPTION_MVEXWIG: |
12390 | if (strcmp (arg, "0") == 0) | |
40c9c8de | 12391 | vexwig = vexw0; |
03751133 | 12392 | else if (strcmp (arg, "1") == 0) |
40c9c8de | 12393 | vexwig = vexw1; |
03751133 L |
12394 | else |
12395 | as_fatal (_("invalid -mvexwig= option: `%s'"), arg); | |
12396 | break; | |
12397 | ||
7e8b059b L |
12398 | case OPTION_MADD_BND_PREFIX: |
12399 | add_bnd_prefix = 1; | |
12400 | break; | |
12401 | ||
43234a1e L |
12402 | case OPTION_MEVEXLIG: |
12403 | if (strcmp (arg, "128") == 0) | |
12404 | evexlig = evexl128; | |
12405 | else if (strcmp (arg, "256") == 0) | |
12406 | evexlig = evexl256; | |
12407 | else if (strcmp (arg, "512") == 0) | |
12408 | evexlig = evexl512; | |
12409 | else | |
12410 | as_fatal (_("invalid -mevexlig= option: `%s'"), arg); | |
12411 | break; | |
12412 | ||
d3d3c6db IT |
12413 | case OPTION_MEVEXRCIG: |
12414 | if (strcmp (arg, "rne") == 0) | |
12415 | evexrcig = rne; | |
12416 | else if (strcmp (arg, "rd") == 0) | |
12417 | evexrcig = rd; | |
12418 | else if (strcmp (arg, "ru") == 0) | |
12419 | evexrcig = ru; | |
12420 | else if (strcmp (arg, "rz") == 0) | |
12421 | evexrcig = rz; | |
12422 | else | |
12423 | as_fatal (_("invalid -mevexrcig= option: `%s'"), arg); | |
12424 | break; | |
12425 | ||
43234a1e L |
12426 | case OPTION_MEVEXWIG: |
12427 | if (strcmp (arg, "0") == 0) | |
12428 | evexwig = evexw0; | |
12429 | else if (strcmp (arg, "1") == 0) | |
12430 | evexwig = evexw1; | |
12431 | else | |
12432 | as_fatal (_("invalid -mevexwig= option: `%s'"), arg); | |
12433 | break; | |
12434 | ||
167ad85b TG |
12435 | # if defined (TE_PE) || defined (TE_PEP) |
12436 | case OPTION_MBIG_OBJ: | |
12437 | use_big_obj = 1; | |
12438 | break; | |
12439 | #endif | |
12440 | ||
d1982f93 | 12441 | case OPTION_MOMIT_LOCK_PREFIX: |
d022bddd IT |
12442 | if (strcasecmp (arg, "yes") == 0) |
12443 | omit_lock_prefix = 1; | |
12444 | else if (strcasecmp (arg, "no") == 0) | |
12445 | omit_lock_prefix = 0; | |
12446 | else | |
12447 | as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg); | |
12448 | break; | |
12449 | ||
e4e00185 AS |
12450 | case OPTION_MFENCE_AS_LOCK_ADD: |
12451 | if (strcasecmp (arg, "yes") == 0) | |
12452 | avoid_fence = 1; | |
12453 | else if (strcasecmp (arg, "no") == 0) | |
12454 | avoid_fence = 0; | |
12455 | else | |
12456 | as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg); | |
12457 | break; | |
12458 | ||
0cb4071e L |
12459 | case OPTION_MRELAX_RELOCATIONS: |
12460 | if (strcasecmp (arg, "yes") == 0) | |
12461 | generate_relax_relocations = 1; | |
12462 | else if (strcasecmp (arg, "no") == 0) | |
12463 | generate_relax_relocations = 0; | |
12464 | else | |
12465 | as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg); | |
12466 | break; | |
12467 | ||
e379e5f3 L |
12468 | case OPTION_MALIGN_BRANCH_BOUNDARY: |
12469 | { | |
12470 | char *end; | |
12471 | long int align = strtoul (arg, &end, 0); | |
12472 | if (*end == '\0') | |
12473 | { | |
12474 | if (align == 0) | |
12475 | { | |
12476 | align_branch_power = 0; | |
12477 | break; | |
12478 | } | |
12479 | else if (align >= 16) | |
12480 | { | |
12481 | int align_power; | |
12482 | for (align_power = 0; | |
12483 | (align & 1) == 0; | |
12484 | align >>= 1, align_power++) | |
12485 | continue; | |
12486 | /* Limit alignment power to 31. */ | |
12487 | if (align == 1 && align_power < 32) | |
12488 | { | |
12489 | align_branch_power = align_power; | |
12490 | break; | |
12491 | } | |
12492 | } | |
12493 | } | |
12494 | as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg); | |
12495 | } | |
12496 | break; | |
12497 | ||
12498 | case OPTION_MALIGN_BRANCH_PREFIX_SIZE: | |
12499 | { | |
12500 | char *end; | |
12501 | int align = strtoul (arg, &end, 0); | |
12502 | /* Some processors only support 5 prefixes. */ | |
12503 | if (*end == '\0' && align >= 0 && align < 6) | |
12504 | { | |
12505 | align_branch_prefix_size = align; | |
12506 | break; | |
12507 | } | |
12508 | as_fatal (_("invalid -malign-branch-prefix-size= value: %s"), | |
12509 | arg); | |
12510 | } | |
12511 | break; | |
12512 | ||
12513 | case OPTION_MALIGN_BRANCH: | |
12514 | align_branch = 0; | |
12515 | saved = xstrdup (arg); | |
12516 | type = saved; | |
12517 | do | |
12518 | { | |
12519 | next = strchr (type, '+'); | |
12520 | if (next) | |
12521 | *next++ = '\0'; | |
12522 | if (strcasecmp (type, "jcc") == 0) | |
12523 | align_branch |= align_branch_jcc_bit; | |
12524 | else if (strcasecmp (type, "fused") == 0) | |
12525 | align_branch |= align_branch_fused_bit; | |
12526 | else if (strcasecmp (type, "jmp") == 0) | |
12527 | align_branch |= align_branch_jmp_bit; | |
12528 | else if (strcasecmp (type, "call") == 0) | |
12529 | align_branch |= align_branch_call_bit; | |
12530 | else if (strcasecmp (type, "ret") == 0) | |
12531 | align_branch |= align_branch_ret_bit; | |
12532 | else if (strcasecmp (type, "indirect") == 0) | |
12533 | align_branch |= align_branch_indirect_bit; | |
12534 | else | |
12535 | as_fatal (_("invalid -malign-branch= option: `%s'"), arg); | |
12536 | type = next; | |
12537 | } | |
12538 | while (next != NULL); | |
12539 | free (saved); | |
12540 | break; | |
12541 | ||
76cf450b L |
12542 | case OPTION_MBRANCHES_WITH_32B_BOUNDARIES: |
12543 | align_branch_power = 5; | |
12544 | align_branch_prefix_size = 5; | |
12545 | align_branch = (align_branch_jcc_bit | |
12546 | | align_branch_fused_bit | |
12547 | | align_branch_jmp_bit); | |
12548 | break; | |
12549 | ||
5db04b09 | 12550 | case OPTION_MAMD64: |
e89c5eaa | 12551 | intel64 = 0; |
5db04b09 L |
12552 | break; |
12553 | ||
12554 | case OPTION_MINTEL64: | |
e89c5eaa | 12555 | intel64 = 1; |
5db04b09 L |
12556 | break; |
12557 | ||
b6f8c7c4 L |
12558 | case 'O': |
12559 | if (arg == NULL) | |
12560 | { | |
12561 | optimize = 1; | |
12562 | /* Turn off -Os. */ | |
12563 | optimize_for_space = 0; | |
12564 | } | |
12565 | else if (*arg == 's') | |
12566 | { | |
12567 | optimize_for_space = 1; | |
12568 | /* Turn on all encoding optimizations. */ | |
41fd2579 | 12569 | optimize = INT_MAX; |
b6f8c7c4 L |
12570 | } |
12571 | else | |
12572 | { | |
12573 | optimize = atoi (arg); | |
12574 | /* Turn off -Os. */ | |
12575 | optimize_for_space = 0; | |
12576 | } | |
12577 | break; | |
12578 | ||
252b5132 RH |
12579 | default: |
12580 | return 0; | |
12581 | } | |
12582 | return 1; | |
12583 | } | |
12584 | ||
8a2c8fef L |
12585 | #define MESSAGE_TEMPLATE \ |
12586 | " " | |
12587 | ||
293f5f65 L |
12588 | static char * |
12589 | output_message (FILE *stream, char *p, char *message, char *start, | |
12590 | int *left_p, const char *name, int len) | |
12591 | { | |
12592 | int size = sizeof (MESSAGE_TEMPLATE); | |
12593 | int left = *left_p; | |
12594 | ||
12595 | /* Reserve 2 spaces for ", " or ",\0" */ | |
12596 | left -= len + 2; | |
12597 | ||
12598 | /* Check if there is any room. */ | |
12599 | if (left >= 0) | |
12600 | { | |
12601 | if (p != start) | |
12602 | { | |
12603 | *p++ = ','; | |
12604 | *p++ = ' '; | |
12605 | } | |
12606 | p = mempcpy (p, name, len); | |
12607 | } | |
12608 | else | |
12609 | { | |
12610 | /* Output the current message now and start a new one. */ | |
12611 | *p++ = ','; | |
12612 | *p = '\0'; | |
12613 | fprintf (stream, "%s\n", message); | |
12614 | p = start; | |
12615 | left = size - (start - message) - len - 2; | |
12616 | ||
12617 | gas_assert (left >= 0); | |
12618 | ||
12619 | p = mempcpy (p, name, len); | |
12620 | } | |
12621 | ||
12622 | *left_p = left; | |
12623 | return p; | |
12624 | } | |
12625 | ||
8a2c8fef | 12626 | static void |
1ded5609 | 12627 | show_arch (FILE *stream, int ext, int check) |
8a2c8fef L |
12628 | { |
12629 | static char message[] = MESSAGE_TEMPLATE; | |
12630 | char *start = message + 27; | |
12631 | char *p; | |
12632 | int size = sizeof (MESSAGE_TEMPLATE); | |
12633 | int left; | |
12634 | const char *name; | |
12635 | int len; | |
12636 | unsigned int j; | |
12637 | ||
12638 | p = start; | |
12639 | left = size - (start - message); | |
12640 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) | |
12641 | { | |
12642 | /* Should it be skipped? */ | |
12643 | if (cpu_arch [j].skip) | |
12644 | continue; | |
12645 | ||
12646 | name = cpu_arch [j].name; | |
12647 | len = cpu_arch [j].len; | |
12648 | if (*name == '.') | |
12649 | { | |
12650 | /* It is an extension. Skip if we aren't asked to show it. */ | |
12651 | if (ext) | |
12652 | { | |
12653 | name++; | |
12654 | len--; | |
12655 | } | |
12656 | else | |
12657 | continue; | |
12658 | } | |
12659 | else if (ext) | |
12660 | { | |
12661 | /* It is an processor. Skip if we show only extension. */ | |
12662 | continue; | |
12663 | } | |
1ded5609 JB |
12664 | else if (check && ! cpu_arch[j].flags.bitfield.cpui386) |
12665 | { | |
12666 | /* It is an impossible processor - skip. */ | |
12667 | continue; | |
12668 | } | |
8a2c8fef | 12669 | |
293f5f65 | 12670 | p = output_message (stream, p, message, start, &left, name, len); |
8a2c8fef L |
12671 | } |
12672 | ||
293f5f65 L |
12673 | /* Display disabled extensions. */ |
12674 | if (ext) | |
12675 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) | |
12676 | { | |
12677 | name = cpu_noarch [j].name; | |
12678 | len = cpu_noarch [j].len; | |
12679 | p = output_message (stream, p, message, start, &left, name, | |
12680 | len); | |
12681 | } | |
12682 | ||
8a2c8fef L |
12683 | *p = '\0'; |
12684 | fprintf (stream, "%s\n", message); | |
12685 | } | |
12686 | ||
252b5132 | 12687 | void |
8a2c8fef | 12688 | md_show_usage (FILE *stream) |
252b5132 | 12689 | { |
4cc782b5 ILT |
12690 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
12691 | fprintf (stream, _("\ | |
d4693039 | 12692 | -Qy, -Qn ignored\n\ |
a38cf1db | 12693 | -V print assembler version number\n\ |
b3b91714 AM |
12694 | -k ignored\n")); |
12695 | #endif | |
12696 | fprintf (stream, _("\ | |
12b55ccc | 12697 | -n Do not optimize code alignment\n\ |
b3b91714 AM |
12698 | -q quieten some warnings\n")); |
12699 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
12700 | fprintf (stream, _("\ | |
a38cf1db | 12701 | -s ignored\n")); |
b3b91714 | 12702 | #endif |
d7f449c0 L |
12703 | #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
12704 | || defined (TE_PE) || defined (TE_PEP)) | |
751d281c | 12705 | fprintf (stream, _("\ |
570561f7 | 12706 | --32/--64/--x32 generate 32bit/64bit/x32 code\n")); |
751d281c | 12707 | #endif |
b3b91714 AM |
12708 | #ifdef SVR4_COMMENT_CHARS |
12709 | fprintf (stream, _("\ | |
12710 | --divide do not treat `/' as a comment character\n")); | |
a38cf1db AM |
12711 | #else |
12712 | fprintf (stream, _("\ | |
b3b91714 | 12713 | --divide ignored\n")); |
4cc782b5 | 12714 | #endif |
9103f4f4 | 12715 | fprintf (stream, _("\ |
6305a203 | 12716 | -march=CPU[,+EXTENSION...]\n\ |
8a2c8fef | 12717 | generate code for CPU and EXTENSION, CPU is one of:\n")); |
1ded5609 | 12718 | show_arch (stream, 0, 1); |
8a2c8fef L |
12719 | fprintf (stream, _("\ |
12720 | EXTENSION is combination of:\n")); | |
1ded5609 | 12721 | show_arch (stream, 1, 0); |
6305a203 | 12722 | fprintf (stream, _("\ |
8a2c8fef | 12723 | -mtune=CPU optimize for CPU, CPU is one of:\n")); |
1ded5609 | 12724 | show_arch (stream, 0, 0); |
ba104c83 | 12725 | fprintf (stream, _("\ |
c0f3af97 L |
12726 | -msse2avx encode SSE instructions with VEX prefix\n")); |
12727 | fprintf (stream, _("\ | |
7c5c05ef | 12728 | -msse-check=[none|error|warning] (default: warning)\n\ |
daf50ae7 L |
12729 | check SSE instructions\n")); |
12730 | fprintf (stream, _("\ | |
7c5c05ef | 12731 | -moperand-check=[none|error|warning] (default: warning)\n\ |
7bab8ab5 JB |
12732 | check operand combinations for validity\n")); |
12733 | fprintf (stream, _("\ | |
7c5c05ef L |
12734 | -mavxscalar=[128|256] (default: 128)\n\ |
12735 | encode scalar AVX instructions with specific vector\n\ | |
539f890d L |
12736 | length\n")); |
12737 | fprintf (stream, _("\ | |
03751133 L |
12738 | -mvexwig=[0|1] (default: 0)\n\ |
12739 | encode VEX instructions with specific VEX.W value\n\ | |
12740 | for VEX.W bit ignored instructions\n")); | |
12741 | fprintf (stream, _("\ | |
7c5c05ef L |
12742 | -mevexlig=[128|256|512] (default: 128)\n\ |
12743 | encode scalar EVEX instructions with specific vector\n\ | |
43234a1e L |
12744 | length\n")); |
12745 | fprintf (stream, _("\ | |
7c5c05ef L |
12746 | -mevexwig=[0|1] (default: 0)\n\ |
12747 | encode EVEX instructions with specific EVEX.W value\n\ | |
43234a1e L |
12748 | for EVEX.W bit ignored instructions\n")); |
12749 | fprintf (stream, _("\ | |
7c5c05ef | 12750 | -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\ |
d3d3c6db IT |
12751 | encode EVEX instructions with specific EVEX.RC value\n\ |
12752 | for SAE-only ignored instructions\n")); | |
12753 | fprintf (stream, _("\ | |
7c5c05ef L |
12754 | -mmnemonic=[att|intel] ")); |
12755 | if (SYSV386_COMPAT) | |
12756 | fprintf (stream, _("(default: att)\n")); | |
12757 | else | |
12758 | fprintf (stream, _("(default: intel)\n")); | |
12759 | fprintf (stream, _("\ | |
12760 | use AT&T/Intel mnemonic\n")); | |
ba104c83 | 12761 | fprintf (stream, _("\ |
7c5c05ef L |
12762 | -msyntax=[att|intel] (default: att)\n\ |
12763 | use AT&T/Intel syntax\n")); | |
ba104c83 L |
12764 | fprintf (stream, _("\ |
12765 | -mindex-reg support pseudo index registers\n")); | |
12766 | fprintf (stream, _("\ | |
12767 | -mnaked-reg don't require `%%' prefix for registers\n")); | |
12768 | fprintf (stream, _("\ | |
7e8b059b | 12769 | -madd-bnd-prefix add BND prefix for all valid branches\n")); |
b4a3a7b4 | 12770 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8dcea932 L |
12771 | fprintf (stream, _("\ |
12772 | -mshared disable branch optimization for shared code\n")); | |
b4a3a7b4 L |
12773 | fprintf (stream, _("\ |
12774 | -mx86-used-note=[no|yes] ")); | |
12775 | if (DEFAULT_X86_USED_NOTE) | |
12776 | fprintf (stream, _("(default: yes)\n")); | |
12777 | else | |
12778 | fprintf (stream, _("(default: no)\n")); | |
12779 | fprintf (stream, _("\ | |
12780 | generate x86 used ISA and feature properties\n")); | |
12781 | #endif | |
12782 | #if defined (TE_PE) || defined (TE_PEP) | |
167ad85b TG |
12783 | fprintf (stream, _("\ |
12784 | -mbig-obj generate big object files\n")); | |
12785 | #endif | |
d022bddd | 12786 | fprintf (stream, _("\ |
7c5c05ef | 12787 | -momit-lock-prefix=[no|yes] (default: no)\n\ |
d022bddd | 12788 | strip all lock prefixes\n")); |
5db04b09 | 12789 | fprintf (stream, _("\ |
7c5c05ef | 12790 | -mfence-as-lock-add=[no|yes] (default: no)\n\ |
e4e00185 AS |
12791 | encode lfence, mfence and sfence as\n\ |
12792 | lock addl $0x0, (%%{re}sp)\n")); | |
12793 | fprintf (stream, _("\ | |
7c5c05ef L |
12794 | -mrelax-relocations=[no|yes] ")); |
12795 | if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS) | |
12796 | fprintf (stream, _("(default: yes)\n")); | |
12797 | else | |
12798 | fprintf (stream, _("(default: no)\n")); | |
12799 | fprintf (stream, _("\ | |
0cb4071e L |
12800 | generate relax relocations\n")); |
12801 | fprintf (stream, _("\ | |
e379e5f3 L |
12802 | -malign-branch-boundary=NUM (default: 0)\n\ |
12803 | align branches within NUM byte boundary\n")); | |
12804 | fprintf (stream, _("\ | |
12805 | -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\ | |
12806 | TYPE is combination of jcc, fused, jmp, call, ret,\n\ | |
12807 | indirect\n\ | |
12808 | specify types of branches to align\n")); | |
12809 | fprintf (stream, _("\ | |
12810 | -malign-branch-prefix-size=NUM (default: 5)\n\ | |
12811 | align branches with NUM prefixes per instruction\n")); | |
12812 | fprintf (stream, _("\ | |
76cf450b L |
12813 | -mbranches-within-32B-boundaries\n\ |
12814 | align branches within 32 byte boundary\n")); | |
12815 | fprintf (stream, _("\ | |
7c5c05ef | 12816 | -mamd64 accept only AMD64 ISA [default]\n")); |
5db04b09 L |
12817 | fprintf (stream, _("\ |
12818 | -mintel64 accept only Intel64 ISA\n")); | |
252b5132 RH |
12819 | } |
12820 | ||
3e73aa7c | 12821 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
321098a5 | 12822 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
e57f8c65 | 12823 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
252b5132 RH |
12824 | |
12825 | /* Pick the target format to use. */ | |
12826 | ||
47926f60 | 12827 | const char * |
e3bb37b5 | 12828 | i386_target_format (void) |
252b5132 | 12829 | { |
351f65ca L |
12830 | if (!strncmp (default_arch, "x86_64", 6)) |
12831 | { | |
12832 | update_code_flag (CODE_64BIT, 1); | |
12833 | if (default_arch[6] == '\0') | |
7f56bc95 | 12834 | x86_elf_abi = X86_64_ABI; |
351f65ca | 12835 | else |
7f56bc95 | 12836 | x86_elf_abi = X86_64_X32_ABI; |
351f65ca | 12837 | } |
3e73aa7c | 12838 | else if (!strcmp (default_arch, "i386")) |
78f12dd3 | 12839 | update_code_flag (CODE_32BIT, 1); |
5197d474 L |
12840 | else if (!strcmp (default_arch, "iamcu")) |
12841 | { | |
12842 | update_code_flag (CODE_32BIT, 1); | |
12843 | if (cpu_arch_isa == PROCESSOR_UNKNOWN) | |
12844 | { | |
12845 | static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS; | |
12846 | cpu_arch_name = "iamcu"; | |
12847 | cpu_sub_arch_name = NULL; | |
12848 | cpu_arch_flags = iamcu_flags; | |
12849 | cpu_arch_isa = PROCESSOR_IAMCU; | |
12850 | cpu_arch_isa_flags = iamcu_flags; | |
12851 | if (!cpu_arch_tune_set) | |
12852 | { | |
12853 | cpu_arch_tune = cpu_arch_isa; | |
12854 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
12855 | } | |
12856 | } | |
8d471ec1 | 12857 | else if (cpu_arch_isa != PROCESSOR_IAMCU) |
5197d474 L |
12858 | as_fatal (_("Intel MCU doesn't support `%s' architecture"), |
12859 | cpu_arch_name); | |
12860 | } | |
3e73aa7c | 12861 | else |
2b5d6a91 | 12862 | as_fatal (_("unknown architecture")); |
89507696 JB |
12863 | |
12864 | if (cpu_flags_all_zero (&cpu_arch_isa_flags)) | |
12865 | cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
12866 | if (cpu_flags_all_zero (&cpu_arch_tune_flags)) | |
12867 | cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
12868 | ||
252b5132 RH |
12869 | switch (OUTPUT_FLAVOR) |
12870 | { | |
9384f2ff | 12871 | #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT) |
4c63da97 | 12872 | case bfd_target_aout_flavour: |
47926f60 | 12873 | return AOUT_TARGET_FORMAT; |
4c63da97 | 12874 | #endif |
9384f2ff AM |
12875 | #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF) |
12876 | # if defined (TE_PE) || defined (TE_PEP) | |
12877 | case bfd_target_coff_flavour: | |
167ad85b TG |
12878 | if (flag_code == CODE_64BIT) |
12879 | return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64"; | |
12880 | else | |
12881 | return "pe-i386"; | |
9384f2ff | 12882 | # elif defined (TE_GO32) |
0561d57c JK |
12883 | case bfd_target_coff_flavour: |
12884 | return "coff-go32"; | |
9384f2ff | 12885 | # else |
252b5132 RH |
12886 | case bfd_target_coff_flavour: |
12887 | return "coff-i386"; | |
9384f2ff | 12888 | # endif |
4c63da97 | 12889 | #endif |
3e73aa7c | 12890 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 12891 | case bfd_target_elf_flavour: |
3e73aa7c | 12892 | { |
351f65ca L |
12893 | const char *format; |
12894 | ||
12895 | switch (x86_elf_abi) | |
4fa24527 | 12896 | { |
351f65ca L |
12897 | default: |
12898 | format = ELF_TARGET_FORMAT; | |
e379e5f3 L |
12899 | #ifndef TE_SOLARIS |
12900 | tls_get_addr = "___tls_get_addr"; | |
12901 | #endif | |
351f65ca | 12902 | break; |
7f56bc95 | 12903 | case X86_64_ABI: |
351f65ca | 12904 | use_rela_relocations = 1; |
4fa24527 | 12905 | object_64bit = 1; |
e379e5f3 L |
12906 | #ifndef TE_SOLARIS |
12907 | tls_get_addr = "__tls_get_addr"; | |
12908 | #endif | |
351f65ca L |
12909 | format = ELF_TARGET_FORMAT64; |
12910 | break; | |
7f56bc95 | 12911 | case X86_64_X32_ABI: |
4fa24527 | 12912 | use_rela_relocations = 1; |
351f65ca | 12913 | object_64bit = 1; |
e379e5f3 L |
12914 | #ifndef TE_SOLARIS |
12915 | tls_get_addr = "__tls_get_addr"; | |
12916 | #endif | |
862be3fb | 12917 | disallow_64bit_reloc = 1; |
351f65ca L |
12918 | format = ELF_TARGET_FORMAT32; |
12919 | break; | |
4fa24527 | 12920 | } |
3632d14b | 12921 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 12922 | { |
7f56bc95 | 12923 | if (x86_elf_abi != X86_64_ABI) |
8a9036a4 L |
12924 | as_fatal (_("Intel L1OM is 64bit only")); |
12925 | return ELF_TARGET_L1OM_FORMAT; | |
12926 | } | |
b49f93f6 | 12927 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
7a9068fe L |
12928 | { |
12929 | if (x86_elf_abi != X86_64_ABI) | |
12930 | as_fatal (_("Intel K1OM is 64bit only")); | |
12931 | return ELF_TARGET_K1OM_FORMAT; | |
12932 | } | |
81486035 L |
12933 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
12934 | { | |
12935 | if (x86_elf_abi != I386_ABI) | |
12936 | as_fatal (_("Intel MCU is 32bit only")); | |
12937 | return ELF_TARGET_IAMCU_FORMAT; | |
12938 | } | |
8a9036a4 | 12939 | else |
351f65ca | 12940 | return format; |
3e73aa7c | 12941 | } |
e57f8c65 TG |
12942 | #endif |
12943 | #if defined (OBJ_MACH_O) | |
12944 | case bfd_target_mach_o_flavour: | |
d382c579 TG |
12945 | if (flag_code == CODE_64BIT) |
12946 | { | |
12947 | use_rela_relocations = 1; | |
12948 | object_64bit = 1; | |
12949 | return "mach-o-x86-64"; | |
12950 | } | |
12951 | else | |
12952 | return "mach-o-i386"; | |
4c63da97 | 12953 | #endif |
252b5132 RH |
12954 | default: |
12955 | abort (); | |
12956 | return NULL; | |
12957 | } | |
12958 | } | |
12959 | ||
47926f60 | 12960 | #endif /* OBJ_MAYBE_ more than one */ |
252b5132 | 12961 | \f |
252b5132 | 12962 | symbolS * |
7016a5d5 | 12963 | md_undefined_symbol (char *name) |
252b5132 | 12964 | { |
18dc2407 ILT |
12965 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
12966 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
12967 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
12968 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
12969 | { |
12970 | if (!GOT_symbol) | |
12971 | { | |
12972 | if (symbol_find (name)) | |
12973 | as_bad (_("GOT already in symbol table")); | |
12974 | GOT_symbol = symbol_new (name, undefined_section, | |
12975 | (valueT) 0, &zero_address_frag); | |
12976 | }; | |
12977 | return GOT_symbol; | |
12978 | } | |
252b5132 RH |
12979 | return 0; |
12980 | } | |
12981 | ||
12982 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 12983 | |
252b5132 | 12984 | valueT |
7016a5d5 | 12985 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
252b5132 | 12986 | { |
4c63da97 AM |
12987 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
12988 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
12989 | { | |
12990 | /* For a.out, force the section size to be aligned. If we don't do | |
12991 | this, BFD will align it for us, but it will not write out the | |
12992 | final bytes of the section. This may be a bug in BFD, but it is | |
12993 | easier to fix it here since that is how the other a.out targets | |
12994 | work. */ | |
12995 | int align; | |
12996 | ||
fd361982 | 12997 | align = bfd_section_alignment (segment); |
8d3842cd | 12998 | size = ((size + (1 << align) - 1) & (-((valueT) 1 << align))); |
4c63da97 | 12999 | } |
252b5132 RH |
13000 | #endif |
13001 | ||
13002 | return size; | |
13003 | } | |
13004 | ||
13005 | /* On the i386, PC-relative offsets are relative to the start of the | |
13006 | next instruction. That is, the address of the offset, plus its | |
13007 | size, since the offset is always the last part of the insn. */ | |
13008 | ||
13009 | long | |
e3bb37b5 | 13010 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
13011 | { |
13012 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
13013 | } | |
13014 | ||
13015 | #ifndef I386COFF | |
13016 | ||
13017 | static void | |
e3bb37b5 | 13018 | s_bss (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13019 | { |
29b0f896 | 13020 | int temp; |
252b5132 | 13021 | |
8a75718c JB |
13022 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
13023 | if (IS_ELF) | |
13024 | obj_elf_section_change_hook (); | |
13025 | #endif | |
252b5132 RH |
13026 | temp = get_absolute_expression (); |
13027 | subseg_set (bss_section, (subsegT) temp); | |
13028 | demand_empty_rest_of_line (); | |
13029 | } | |
13030 | ||
13031 | #endif | |
13032 | ||
e379e5f3 L |
13033 | /* Remember constant directive. */ |
13034 | ||
13035 | void | |
13036 | i386_cons_align (int ignore ATTRIBUTE_UNUSED) | |
13037 | { | |
13038 | if (last_insn.kind != last_insn_directive | |
13039 | && (bfd_section_flags (now_seg) & SEC_CODE)) | |
13040 | { | |
13041 | last_insn.seg = now_seg; | |
13042 | last_insn.kind = last_insn_directive; | |
13043 | last_insn.name = "constant directive"; | |
13044 | last_insn.file = as_where (&last_insn.line); | |
13045 | } | |
13046 | } | |
13047 | ||
252b5132 | 13048 | void |
e3bb37b5 | 13049 | i386_validate_fix (fixS *fixp) |
252b5132 | 13050 | { |
02a86693 | 13051 | if (fixp->fx_subsy) |
252b5132 | 13052 | { |
02a86693 | 13053 | if (fixp->fx_subsy == GOT_symbol) |
23df1078 | 13054 | { |
02a86693 L |
13055 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
13056 | { | |
13057 | if (!object_64bit) | |
13058 | abort (); | |
13059 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
13060 | if (fixp->fx_tcbit2) | |
56ceb5b5 L |
13061 | fixp->fx_r_type = (fixp->fx_tcbit |
13062 | ? BFD_RELOC_X86_64_REX_GOTPCRELX | |
13063 | : BFD_RELOC_X86_64_GOTPCRELX); | |
02a86693 L |
13064 | else |
13065 | #endif | |
13066 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
13067 | } | |
d6ab8113 | 13068 | else |
02a86693 L |
13069 | { |
13070 | if (!object_64bit) | |
13071 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
13072 | else | |
13073 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; | |
13074 | } | |
13075 | fixp->fx_subsy = 0; | |
23df1078 | 13076 | } |
252b5132 | 13077 | } |
02a86693 L |
13078 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
13079 | else if (!object_64bit) | |
13080 | { | |
13081 | if (fixp->fx_r_type == BFD_RELOC_386_GOT32 | |
13082 | && fixp->fx_tcbit2) | |
13083 | fixp->fx_r_type = BFD_RELOC_386_GOT32X; | |
13084 | } | |
13085 | #endif | |
252b5132 RH |
13086 | } |
13087 | ||
252b5132 | 13088 | arelent * |
7016a5d5 | 13089 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
13090 | { |
13091 | arelent *rel; | |
13092 | bfd_reloc_code_real_type code; | |
13093 | ||
13094 | switch (fixp->fx_r_type) | |
13095 | { | |
8ce3d284 | 13096 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
13097 | case BFD_RELOC_SIZE32: |
13098 | case BFD_RELOC_SIZE64: | |
13099 | if (S_IS_DEFINED (fixp->fx_addsy) | |
13100 | && !S_IS_EXTERNAL (fixp->fx_addsy)) | |
13101 | { | |
13102 | /* Resolve size relocation against local symbol to size of | |
13103 | the symbol plus addend. */ | |
13104 | valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset; | |
13105 | if (fixp->fx_r_type == BFD_RELOC_SIZE32 | |
13106 | && !fits_in_unsigned_long (value)) | |
13107 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
13108 | _("symbol size computation overflow")); | |
13109 | fixp->fx_addsy = NULL; | |
13110 | fixp->fx_subsy = NULL; | |
13111 | md_apply_fix (fixp, (valueT *) &value, NULL); | |
13112 | return NULL; | |
13113 | } | |
8ce3d284 | 13114 | #endif |
1a0670f3 | 13115 | /* Fall through. */ |
8fd4256d | 13116 | |
3e73aa7c JH |
13117 | case BFD_RELOC_X86_64_PLT32: |
13118 | case BFD_RELOC_X86_64_GOT32: | |
13119 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
13120 | case BFD_RELOC_X86_64_GOTPCRELX: |
13121 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
252b5132 RH |
13122 | case BFD_RELOC_386_PLT32: |
13123 | case BFD_RELOC_386_GOT32: | |
02a86693 | 13124 | case BFD_RELOC_386_GOT32X: |
252b5132 RH |
13125 | case BFD_RELOC_386_GOTOFF: |
13126 | case BFD_RELOC_386_GOTPC: | |
13ae64f3 JJ |
13127 | case BFD_RELOC_386_TLS_GD: |
13128 | case BFD_RELOC_386_TLS_LDM: | |
13129 | case BFD_RELOC_386_TLS_LDO_32: | |
13130 | case BFD_RELOC_386_TLS_IE_32: | |
37e55690 JJ |
13131 | case BFD_RELOC_386_TLS_IE: |
13132 | case BFD_RELOC_386_TLS_GOTIE: | |
13ae64f3 JJ |
13133 | case BFD_RELOC_386_TLS_LE_32: |
13134 | case BFD_RELOC_386_TLS_LE: | |
67a4f2b7 AO |
13135 | case BFD_RELOC_386_TLS_GOTDESC: |
13136 | case BFD_RELOC_386_TLS_DESC_CALL: | |
bffbf940 JJ |
13137 | case BFD_RELOC_X86_64_TLSGD: |
13138 | case BFD_RELOC_X86_64_TLSLD: | |
13139 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 13140 | case BFD_RELOC_X86_64_DTPOFF64: |
bffbf940 JJ |
13141 | case BFD_RELOC_X86_64_GOTTPOFF: |
13142 | case BFD_RELOC_X86_64_TPOFF32: | |
d6ab8113 JB |
13143 | case BFD_RELOC_X86_64_TPOFF64: |
13144 | case BFD_RELOC_X86_64_GOTOFF64: | |
13145 | case BFD_RELOC_X86_64_GOTPC32: | |
7b81dfbb AJ |
13146 | case BFD_RELOC_X86_64_GOT64: |
13147 | case BFD_RELOC_X86_64_GOTPCREL64: | |
13148 | case BFD_RELOC_X86_64_GOTPC64: | |
13149 | case BFD_RELOC_X86_64_GOTPLT64: | |
13150 | case BFD_RELOC_X86_64_PLTOFF64: | |
67a4f2b7 AO |
13151 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
13152 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
252b5132 RH |
13153 | case BFD_RELOC_RVA: |
13154 | case BFD_RELOC_VTABLE_ENTRY: | |
13155 | case BFD_RELOC_VTABLE_INHERIT: | |
6482c264 NC |
13156 | #ifdef TE_PE |
13157 | case BFD_RELOC_32_SECREL: | |
13158 | #endif | |
252b5132 RH |
13159 | code = fixp->fx_r_type; |
13160 | break; | |
dbbaec26 L |
13161 | case BFD_RELOC_X86_64_32S: |
13162 | if (!fixp->fx_pcrel) | |
13163 | { | |
13164 | /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ | |
13165 | code = fixp->fx_r_type; | |
13166 | break; | |
13167 | } | |
1a0670f3 | 13168 | /* Fall through. */ |
252b5132 | 13169 | default: |
93382f6d | 13170 | if (fixp->fx_pcrel) |
252b5132 | 13171 | { |
93382f6d AM |
13172 | switch (fixp->fx_size) |
13173 | { | |
13174 | default: | |
b091f402 AM |
13175 | as_bad_where (fixp->fx_file, fixp->fx_line, |
13176 | _("can not do %d byte pc-relative relocation"), | |
13177 | fixp->fx_size); | |
93382f6d AM |
13178 | code = BFD_RELOC_32_PCREL; |
13179 | break; | |
13180 | case 1: code = BFD_RELOC_8_PCREL; break; | |
13181 | case 2: code = BFD_RELOC_16_PCREL; break; | |
d258b828 | 13182 | case 4: code = BFD_RELOC_32_PCREL; break; |
d6ab8113 JB |
13183 | #ifdef BFD64 |
13184 | case 8: code = BFD_RELOC_64_PCREL; break; | |
13185 | #endif | |
93382f6d AM |
13186 | } |
13187 | } | |
13188 | else | |
13189 | { | |
13190 | switch (fixp->fx_size) | |
13191 | { | |
13192 | default: | |
b091f402 AM |
13193 | as_bad_where (fixp->fx_file, fixp->fx_line, |
13194 | _("can not do %d byte relocation"), | |
13195 | fixp->fx_size); | |
93382f6d AM |
13196 | code = BFD_RELOC_32; |
13197 | break; | |
13198 | case 1: code = BFD_RELOC_8; break; | |
13199 | case 2: code = BFD_RELOC_16; break; | |
13200 | case 4: code = BFD_RELOC_32; break; | |
937149dd | 13201 | #ifdef BFD64 |
3e73aa7c | 13202 | case 8: code = BFD_RELOC_64; break; |
937149dd | 13203 | #endif |
93382f6d | 13204 | } |
252b5132 RH |
13205 | } |
13206 | break; | |
13207 | } | |
252b5132 | 13208 | |
d182319b JB |
13209 | if ((code == BFD_RELOC_32 |
13210 | || code == BFD_RELOC_32_PCREL | |
13211 | || code == BFD_RELOC_X86_64_32S) | |
252b5132 RH |
13212 | && GOT_symbol |
13213 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c | 13214 | { |
4fa24527 | 13215 | if (!object_64bit) |
d6ab8113 JB |
13216 | code = BFD_RELOC_386_GOTPC; |
13217 | else | |
13218 | code = BFD_RELOC_X86_64_GOTPC32; | |
3e73aa7c | 13219 | } |
7b81dfbb AJ |
13220 | if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) |
13221 | && GOT_symbol | |
13222 | && fixp->fx_addsy == GOT_symbol) | |
13223 | { | |
13224 | code = BFD_RELOC_X86_64_GOTPC64; | |
13225 | } | |
252b5132 | 13226 | |
add39d23 TS |
13227 | rel = XNEW (arelent); |
13228 | rel->sym_ptr_ptr = XNEW (asymbol *); | |
49309057 | 13229 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
13230 | |
13231 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
c87db184 | 13232 | |
3e73aa7c JH |
13233 | if (!use_rela_relocations) |
13234 | { | |
13235 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
13236 | vtable entry to be used in the relocation's section offset. */ | |
13237 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
13238 | rel->address = fixp->fx_offset; | |
fbeb56a4 DK |
13239 | #if defined (OBJ_COFF) && defined (TE_PE) |
13240 | else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy)) | |
13241 | rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2); | |
13242 | else | |
13243 | #endif | |
c6682705 | 13244 | rel->addend = 0; |
3e73aa7c JH |
13245 | } |
13246 | /* Use the rela in 64bit mode. */ | |
252b5132 | 13247 | else |
3e73aa7c | 13248 | { |
862be3fb L |
13249 | if (disallow_64bit_reloc) |
13250 | switch (code) | |
13251 | { | |
862be3fb L |
13252 | case BFD_RELOC_X86_64_DTPOFF64: |
13253 | case BFD_RELOC_X86_64_TPOFF64: | |
13254 | case BFD_RELOC_64_PCREL: | |
13255 | case BFD_RELOC_X86_64_GOTOFF64: | |
13256 | case BFD_RELOC_X86_64_GOT64: | |
13257 | case BFD_RELOC_X86_64_GOTPCREL64: | |
13258 | case BFD_RELOC_X86_64_GOTPC64: | |
13259 | case BFD_RELOC_X86_64_GOTPLT64: | |
13260 | case BFD_RELOC_X86_64_PLTOFF64: | |
13261 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
13262 | _("cannot represent relocation type %s in x32 mode"), | |
13263 | bfd_get_reloc_code_name (code)); | |
13264 | break; | |
13265 | default: | |
13266 | break; | |
13267 | } | |
13268 | ||
062cd5e7 AS |
13269 | if (!fixp->fx_pcrel) |
13270 | rel->addend = fixp->fx_offset; | |
13271 | else | |
13272 | switch (code) | |
13273 | { | |
13274 | case BFD_RELOC_X86_64_PLT32: | |
13275 | case BFD_RELOC_X86_64_GOT32: | |
13276 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
13277 | case BFD_RELOC_X86_64_GOTPCRELX: |
13278 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
bffbf940 JJ |
13279 | case BFD_RELOC_X86_64_TLSGD: |
13280 | case BFD_RELOC_X86_64_TLSLD: | |
13281 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 AO |
13282 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
13283 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
062cd5e7 AS |
13284 | rel->addend = fixp->fx_offset - fixp->fx_size; |
13285 | break; | |
13286 | default: | |
13287 | rel->addend = (section->vma | |
13288 | - fixp->fx_size | |
13289 | + fixp->fx_addnumber | |
13290 | + md_pcrel_from (fixp)); | |
13291 | break; | |
13292 | } | |
3e73aa7c JH |
13293 | } |
13294 | ||
252b5132 RH |
13295 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
13296 | if (rel->howto == NULL) | |
13297 | { | |
13298 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 13299 | _("cannot represent relocation type %s"), |
252b5132 RH |
13300 | bfd_get_reloc_code_name (code)); |
13301 | /* Set howto to a garbage value so that we can keep going. */ | |
13302 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
9c2799c2 | 13303 | gas_assert (rel->howto != NULL); |
252b5132 RH |
13304 | } |
13305 | ||
13306 | return rel; | |
13307 | } | |
13308 | ||
ee86248c | 13309 | #include "tc-i386-intel.c" |
54cfded0 | 13310 | |
a60de03c JB |
13311 | void |
13312 | tc_x86_parse_to_dw2regnum (expressionS *exp) | |
54cfded0 | 13313 | { |
a60de03c JB |
13314 | int saved_naked_reg; |
13315 | char saved_register_dot; | |
54cfded0 | 13316 | |
a60de03c JB |
13317 | saved_naked_reg = allow_naked_reg; |
13318 | allow_naked_reg = 1; | |
13319 | saved_register_dot = register_chars['.']; | |
13320 | register_chars['.'] = '.'; | |
13321 | allow_pseudo_reg = 1; | |
13322 | expression_and_evaluate (exp); | |
13323 | allow_pseudo_reg = 0; | |
13324 | register_chars['.'] = saved_register_dot; | |
13325 | allow_naked_reg = saved_naked_reg; | |
13326 | ||
e96d56a1 | 13327 | if (exp->X_op == O_register && exp->X_add_number >= 0) |
54cfded0 | 13328 | { |
a60de03c JB |
13329 | if ((addressT) exp->X_add_number < i386_regtab_size) |
13330 | { | |
13331 | exp->X_op = O_constant; | |
13332 | exp->X_add_number = i386_regtab[exp->X_add_number] | |
13333 | .dw2_regnum[flag_code >> 1]; | |
13334 | } | |
13335 | else | |
13336 | exp->X_op = O_illegal; | |
54cfded0 | 13337 | } |
54cfded0 AM |
13338 | } |
13339 | ||
13340 | void | |
13341 | tc_x86_frame_initial_instructions (void) | |
13342 | { | |
a60de03c JB |
13343 | static unsigned int sp_regno[2]; |
13344 | ||
13345 | if (!sp_regno[flag_code >> 1]) | |
13346 | { | |
13347 | char *saved_input = input_line_pointer; | |
13348 | char sp[][4] = {"esp", "rsp"}; | |
13349 | expressionS exp; | |
a4447b93 | 13350 | |
a60de03c JB |
13351 | input_line_pointer = sp[flag_code >> 1]; |
13352 | tc_x86_parse_to_dw2regnum (&exp); | |
9c2799c2 | 13353 | gas_assert (exp.X_op == O_constant); |
a60de03c JB |
13354 | sp_regno[flag_code >> 1] = exp.X_add_number; |
13355 | input_line_pointer = saved_input; | |
13356 | } | |
a4447b93 | 13357 | |
61ff971f L |
13358 | cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment); |
13359 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); | |
54cfded0 | 13360 | } |
d2b2c203 | 13361 | |
d7921315 L |
13362 | int |
13363 | x86_dwarf2_addr_size (void) | |
13364 | { | |
13365 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) | |
13366 | if (x86_elf_abi == X86_64_X32_ABI) | |
13367 | return 4; | |
13368 | #endif | |
13369 | return bfd_arch_bits_per_address (stdoutput) / 8; | |
13370 | } | |
13371 | ||
d2b2c203 DJ |
13372 | int |
13373 | i386_elf_section_type (const char *str, size_t len) | |
13374 | { | |
13375 | if (flag_code == CODE_64BIT | |
13376 | && len == sizeof ("unwind") - 1 | |
13377 | && strncmp (str, "unwind", 6) == 0) | |
13378 | return SHT_X86_64_UNWIND; | |
13379 | ||
13380 | return -1; | |
13381 | } | |
bb41ade5 | 13382 | |
ad5fec3b EB |
13383 | #ifdef TE_SOLARIS |
13384 | void | |
13385 | i386_solaris_fix_up_eh_frame (segT sec) | |
13386 | { | |
13387 | if (flag_code == CODE_64BIT) | |
13388 | elf_section_type (sec) = SHT_X86_64_UNWIND; | |
13389 | } | |
13390 | #endif | |
13391 | ||
bb41ade5 AM |
13392 | #ifdef TE_PE |
13393 | void | |
13394 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) | |
13395 | { | |
91d6fa6a | 13396 | expressionS exp; |
bb41ade5 | 13397 | |
91d6fa6a NC |
13398 | exp.X_op = O_secrel; |
13399 | exp.X_add_symbol = symbol; | |
13400 | exp.X_add_number = 0; | |
13401 | emit_expr (&exp, size); | |
bb41ade5 AM |
13402 | } |
13403 | #endif | |
3b22753a L |
13404 | |
13405 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
13406 | /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ | |
13407 | ||
01e1a5bc | 13408 | bfd_vma |
6d4af3c2 | 13409 | x86_64_section_letter (int letter, const char **ptr_msg) |
3b22753a L |
13410 | { |
13411 | if (flag_code == CODE_64BIT) | |
13412 | { | |
13413 | if (letter == 'l') | |
13414 | return SHF_X86_64_LARGE; | |
13415 | ||
8f3bae45 | 13416 | *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string"); |
64e74474 | 13417 | } |
3b22753a | 13418 | else |
8f3bae45 | 13419 | *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string"); |
3b22753a L |
13420 | return -1; |
13421 | } | |
13422 | ||
01e1a5bc | 13423 | bfd_vma |
3b22753a L |
13424 | x86_64_section_word (char *str, size_t len) |
13425 | { | |
8620418b | 13426 | if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large")) |
3b22753a L |
13427 | return SHF_X86_64_LARGE; |
13428 | ||
13429 | return -1; | |
13430 | } | |
13431 | ||
13432 | static void | |
13433 | handle_large_common (int small ATTRIBUTE_UNUSED) | |
13434 | { | |
13435 | if (flag_code != CODE_64BIT) | |
13436 | { | |
13437 | s_comm_internal (0, elf_common_parse); | |
13438 | as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); | |
13439 | } | |
13440 | else | |
13441 | { | |
13442 | static segT lbss_section; | |
13443 | asection *saved_com_section_ptr = elf_com_section_ptr; | |
13444 | asection *saved_bss_section = bss_section; | |
13445 | ||
13446 | if (lbss_section == NULL) | |
13447 | { | |
13448 | flagword applicable; | |
13449 | segT seg = now_seg; | |
13450 | subsegT subseg = now_subseg; | |
13451 | ||
13452 | /* The .lbss section is for local .largecomm symbols. */ | |
13453 | lbss_section = subseg_new (".lbss", 0); | |
13454 | applicable = bfd_applicable_section_flags (stdoutput); | |
fd361982 | 13455 | bfd_set_section_flags (lbss_section, applicable & SEC_ALLOC); |
3b22753a L |
13456 | seg_info (lbss_section)->bss = 1; |
13457 | ||
13458 | subseg_set (seg, subseg); | |
13459 | } | |
13460 | ||
13461 | elf_com_section_ptr = &_bfd_elf_large_com_section; | |
13462 | bss_section = lbss_section; | |
13463 | ||
13464 | s_comm_internal (0, elf_common_parse); | |
13465 | ||
13466 | elf_com_section_ptr = saved_com_section_ptr; | |
13467 | bss_section = saved_bss_section; | |
13468 | } | |
13469 | } | |
13470 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |