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xtensa: implement NPTL helpers
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
b90efa5b 2 Copyright (C) 1989-2015 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
89e7505f
L		 36#ifdef TE_LINUX
37/* Default to compress debug sections for Linux. */
151411f8 38enum compressed_debug_section_type flag_compress_debug
189ebcf9 39 = COMPRESS_DEBUG_GABI_ZLIB;
89e7505f
L		 40#endif
41
252b5132
RH		 42#ifndef REGISTER_WARNINGS
43#define REGISTER_WARNINGS 1
44#endif
45
c3332e24 46#ifndef INFER_ADDR_PREFIX
eecb386c 47#define INFER_ADDR_PREFIX 1
c3332e24
AM		 48#endif
49
29b0f896
AM		 50#ifndef DEFAULT_ARCH
51#define DEFAULT_ARCH "i386"
246fcdee 52#endif
252b5132 53
edde18a5
AM		 54#ifndef INLINE
55#if __GNUC__ >= 2
56#define INLINE __inline__
57#else
58#define INLINE
59#endif
60#endif
61
6305a203
L		 62/* Prefixes will be emitted in the order defined below.
63 WAIT_PREFIX must be the first prefix since FWAIT is really is an
64 instruction, and so must come before any prefixes.
65 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 66 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 67#define WAIT_PREFIX 0
68#define SEG_PREFIX 1
69#define ADDR_PREFIX 2
70#define DATA_PREFIX 3
c32fa91d 71#define REP_PREFIX 4
42164a71 72#define HLE_PREFIX REP_PREFIX
7e8b059b 73#define BND_PREFIX REP_PREFIX
c32fa91d
L		 74#define LOCK_PREFIX 5
75#define REX_PREFIX 6 /* must come last. */
76#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 77
78/* we define the syntax here (modulo base,index,scale syntax) */
79#define REGISTER_PREFIX '%'
80#define IMMEDIATE_PREFIX '$'
81#define ABSOLUTE_PREFIX '*'
82
83/* these are the instruction mnemonic suffixes in AT&T syntax or
84 memory operand size in Intel syntax. */
85#define WORD_MNEM_SUFFIX 'w'
86#define BYTE_MNEM_SUFFIX 'b'
87#define SHORT_MNEM_SUFFIX 's'
88#define LONG_MNEM_SUFFIX 'l'
89#define QWORD_MNEM_SUFFIX 'q'
90#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 91#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 92#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 93/* Intel Syntax. Use a non-ascii letter since since it never appears
94 in instructions. */
95#define LONG_DOUBLE_MNEM_SUFFIX '\1'
96
97#define END_OF_INSN '\0'
98
99/*
100 'templates' is for grouping together 'template' structures for opcodes
101 of the same name. This is only used for storing the insns in the grand
102 ole hash table of insns.
103 The templates themselves start at START and range up to (but not including)
104 END.
105 */
106typedef struct
107{
d3ce72d0
NC		 108 const insn_template *start;
109 const insn_template *end;
6305a203
L		 110}
111templates;
112
113/* 386 operand encoding bytes: see 386 book for details of this. */
114typedef struct
115{
116 unsigned int regmem; /* codes register or memory operand */
117 unsigned int reg; /* codes register operand (or extended opcode) */
118 unsigned int mode; /* how to interpret regmem & reg */
119}
120modrm_byte;
121
122/* x86-64 extension prefix. */
123typedef int rex_byte;
124
6305a203
L		 125/* 386 opcode byte to code indirect addressing. */
126typedef struct
127{
128 unsigned base;
129 unsigned index;
130 unsigned scale;
131}
132sib_byte;
133
6305a203
L		 134/* x86 arch names, types and features */
135typedef struct
136{
137 const char *name; /* arch name */
8a2c8fef 138 unsigned int len; /* arch string length */
6305a203
L		 139 enum processor_type type; /* arch type */
140 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 141 unsigned int skip; /* show_arch should skip this. */
22109423 142 unsigned int negated; /* turn off indicated flags. */
6305a203
L		 143}
144arch_entry;
145
78f12dd3 146static void update_code_flag (int, int);
e3bb37b5
L		 147static void set_code_flag (int);
148static void set_16bit_gcc_code_flag (int);
149static void set_intel_syntax (int);
1efbbeb4 150static void set_intel_mnemonic (int);
db51cc60 151static void set_allow_index_reg (int);
7bab8ab5 152static void set_check (int);
e3bb37b5 153static void set_cpu_arch (int);
6482c264 154#ifdef TE_PE
e3bb37b5 155static void pe_directive_secrel (int);
6482c264 156#endif
e3bb37b5
L		 157static void signed_cons (int);
158static char *output_invalid (int c);
ee86248c
JB		 159static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
160 const char *);
161static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
162 const char *);
a7619375 163static int i386_att_operand (char *);
e3bb37b5 164static int i386_intel_operand (char *, int);
ee86248c
JB		 165static int i386_intel_simplify (expressionS *);
166static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 167static const reg_entry *parse_register (char *, char **);
168static char *parse_insn (char *, char *);
169static char *parse_operands (char *, const char *);
170static void swap_operands (void);
4d456e3d 171static void swap_2_operands (int, int);
e3bb37b5
L		 172static void optimize_imm (void);
173static void optimize_disp (void);
d3ce72d0 174static const insn_template *match_template (void);
e3bb37b5
L		 175static int check_string (void);
176static int process_suffix (void);
177static int check_byte_reg (void);
178static int check_long_reg (void);
179static int check_qword_reg (void);
180static int check_word_reg (void);
181static int finalize_imm (void);
182static int process_operands (void);
183static const seg_entry *build_modrm_byte (void);
184static void output_insn (void);
185static void output_imm (fragS *, offsetT);
186static void output_disp (fragS *, offsetT);
29b0f896 187#ifndef I386COFF
e3bb37b5 188static void s_bss (int);
252b5132 189#endif
17d4e2a2
L		 190#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
191static void handle_large_common (int small ATTRIBUTE_UNUSED);
192#endif
252b5132 193
a847613f 194static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 195
43234a1e
L		 196/* This struct describes rounding control and SAE in the instruction. */
197struct RC_Operation
198{
199 enum rc_type
200 {
201 rne = 0,
202 rd,
203 ru,
204 rz,
205 saeonly
206 } type;
207 int operand;
208};
209
210static struct RC_Operation rc_op;
211
212/* The struct describes masking, applied to OPERAND in the instruction.
213 MASK is a pointer to the corresponding mask register. ZEROING tells
214 whether merging or zeroing mask is used. */
215struct Mask_Operation
216{
217 const reg_entry *mask;
218 unsigned int zeroing;
219 /* The operand where this operation is associated. */
220 int operand;
221};
222
223static struct Mask_Operation mask_op;
224
225/* The struct describes broadcasting, applied to OPERAND. FACTOR is
226 broadcast factor. */
227struct Broadcast_Operation
228{
229 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
230 int type;
231
232 /* Index of broadcasted operand. */
233 int operand;
234};
235
236static struct Broadcast_Operation broadcast_op;
237
c0f3af97
L		 238/* VEX prefix. */
239typedef struct
240{
43234a1e
L		 241 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
242 unsigned char bytes[4];
c0f3af97
L		 243 unsigned int length;
244 /* Destination or source register specifier. */
245 const reg_entry *register_specifier;
246} vex_prefix;
247
252b5132 248/* 'md_assemble ()' gathers together information and puts it into a
47926f60 249 i386_insn. */
252b5132 250
520dc8e8
AM		 251union i386_op
252 {
253 expressionS *disps;
254 expressionS *imms;
255 const reg_entry *regs;
256 };
257
a65babc9
L		 258enum i386_error
259 {
86e026a4 260 operand_size_mismatch,
a65babc9
L		 261 operand_type_mismatch,
262 register_type_mismatch,
263 number_of_operands_mismatch,
264 invalid_instruction_suffix,
265 bad_imm4,
266 old_gcc_only,
267 unsupported_with_intel_mnemonic,
268 unsupported_syntax,
6c30d220
L		 269 unsupported,
270 invalid_vsib_address,
7bab8ab5 271 invalid_vector_register_set,
43234a1e
L		 272 unsupported_vector_index_register,
273 unsupported_broadcast,
274 broadcast_not_on_src_operand,
275 broadcast_needed,
276 unsupported_masking,
277 mask_not_on_destination,
278 no_default_mask,
279 unsupported_rc_sae,
280 rc_sae_operand_not_last_imm,
281 invalid_register_operand,
282 try_vector_disp8
a65babc9
L		 283 };
284
252b5132
RH		 285struct _i386_insn
286 {
47926f60 287 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 288 insn_template tm;
252b5132 289
7d5e4556
L		 290 /* SUFFIX holds the instruction size suffix for byte, word, dword
291 or qword, if given. */
252b5132
RH		 292 char suffix;
293
47926f60 294 /* OPERANDS gives the number of given operands. */
252b5132
RH		 295 unsigned int operands;
296
297 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
298 of given register, displacement, memory operands and immediate
47926f60 299 operands. */
252b5132
RH		 300 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
301
302 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 303 use OP[i] for the corresponding operand. */
40fb9820 304 i386_operand_type types[MAX_OPERANDS];
252b5132 305
520dc8e8
AM		 306 /* Displacement expression, immediate expression, or register for each
307 operand. */
308 union i386_op op[MAX_OPERANDS];
252b5132 309
3e73aa7c
JH		 310 /* Flags for operands. */
311 unsigned int flags[MAX_OPERANDS];
312#define Operand_PCrel 1
313
252b5132 314 /* Relocation type for operand */
f86103b7 315 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 316
252b5132
RH		 317 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
318 the base index byte below. */
319 const reg_entry *base_reg;
320 const reg_entry *index_reg;
321 unsigned int log2_scale_factor;
322
323 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 324 explicit segment overrides are given. */
ce8a8b2f 325 const seg_entry *seg[2];
252b5132
RH		 326
327 /* PREFIX holds all the given prefix opcodes (usually null).
328 PREFIXES is the number of prefix opcodes. */
329 unsigned int prefixes;
330 unsigned char prefix[MAX_PREFIXES];
331
332 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 333 addressing modes of this insn are encoded. */
252b5132 334 modrm_byte rm;
3e73aa7c 335 rex_byte rex;
43234a1e 336 rex_byte vrex;
252b5132 337 sib_byte sib;
c0f3af97 338 vex_prefix vex;
b6169b20 339
43234a1e
L		 340 /* Masking attributes. */
341 struct Mask_Operation *mask;
342
343 /* Rounding control and SAE attributes. */
344 struct RC_Operation *rounding;
345
346 /* Broadcasting attributes. */
347 struct Broadcast_Operation *broadcast;
348
349 /* Compressed disp8*N attribute. */
350 unsigned int memshift;
351
b6169b20 352 /* Swap operand in encoding. */
4473e004 353 unsigned int swap_operand;
891edac4 354
a501d77e
L		 355 /* Prefer 8bit or 32bit displacement in encoding. */
356 enum
357 {
358 disp_encoding_default = 0,
359 disp_encoding_8bit,
360 disp_encoding_32bit
361 } disp_encoding;
f8a5c266 362
d5de92cf
L		 363 /* REP prefix. */
364 const char *rep_prefix;
365
165de32a
L		 366 /* HLE prefix. */
367 const char *hle_prefix;
42164a71 368
7e8b059b
L		 369 /* Have BND prefix. */
370 const char *bnd_prefix;
371
43234a1e
L		 372 /* Need VREX to support upper 16 registers. */
373 int need_vrex;
374
891edac4 375 /* Error message. */
a65babc9 376 enum i386_error error;
252b5132
RH		 377 };
378
379typedef struct _i386_insn i386_insn;
380
43234a1e
L		 381/* Link RC type with corresponding string, that'll be looked for in
382 asm. */
383struct RC_name
384{
385 enum rc_type type;
386 const char *name;
387 unsigned int len;
388};
389
390static const struct RC_name RC_NamesTable[] =
391{
392 { rne, STRING_COMMA_LEN ("rn-sae") },
393 { rd, STRING_COMMA_LEN ("rd-sae") },
394 { ru, STRING_COMMA_LEN ("ru-sae") },
395 { rz, STRING_COMMA_LEN ("rz-sae") },
396 { saeonly, STRING_COMMA_LEN ("sae") },
397};
398
252b5132
RH		 399/* List of chars besides those in app.c:symbol_chars that can start an
400 operand. Used to prevent the scrubber eating vital white-space. */
43234a1e 401const char extra_symbol_chars[] = "*%-([{"
252b5132 402#ifdef LEX_AT
32137342
NC		 403 "@"
404#endif
405#ifdef LEX_QM
406 "?"
252b5132 407#endif
32137342 408 ;
252b5132 409
29b0f896
AM		 410#if (defined (TE_I386AIX) \
411 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 412 && !defined (TE_GNU) \
29b0f896 413 && !defined (TE_LINUX) \
8d63c93e
RM		 414 && !defined (TE_NACL) \
415 && !defined (TE_NETWARE) \
29b0f896 416 && !defined (TE_FreeBSD) \
5b806d27 417 && !defined (TE_DragonFly) \
29b0f896 418 && !defined (TE_NetBSD)))
252b5132 419/* This array holds the chars that always start a comment. If the
b3b91714
AM		 420 pre-processor is disabled, these aren't very useful. The option
421 --divide will remove '/' from this list. */
422const char *i386_comment_chars = "#/";
423#define SVR4_COMMENT_CHARS 1
252b5132 424#define PREFIX_SEPARATOR '\\'
252b5132 425
b3b91714
AM		 426#else
427const char *i386_comment_chars = "#";
428#define PREFIX_SEPARATOR '/'
429#endif
430
252b5132
RH		 431/* This array holds the chars that only start a comment at the beginning of
432 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 433 .line and .file directives will appear in the pre-processed output.
434 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 435 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 436 #NO_APP at the beginning of its output.
437 Also note that comments started like this one will always work if
252b5132 438 '/' isn't otherwise defined. */
b3b91714 439const char line_comment_chars[] = "#/";
252b5132 440
63a0b638 441const char line_separator_chars[] = ";";
252b5132 442
ce8a8b2f
AM		 443/* Chars that can be used to separate mant from exp in floating point
444 nums. */
252b5132
RH		 445const char EXP_CHARS[] = "eE";
446
ce8a8b2f
AM		 447/* Chars that mean this number is a floating point constant
448 As in 0f12.456
449 or 0d1.2345e12. */
252b5132
RH		 450const char FLT_CHARS[] = "fFdDxX";
451
ce8a8b2f 452/* Tables for lexical analysis. */
252b5132
RH		 453static char mnemonic_chars[256];
454static char register_chars[256];
455static char operand_chars[256];
456static char identifier_chars[256];
457static char digit_chars[256];
458
ce8a8b2f 459/* Lexical macros. */
252b5132
RH		 460#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
461#define is_operand_char(x) (operand_chars[(unsigned char) x])
462#define is_register_char(x) (register_chars[(unsigned char) x])
463#define is_space_char(x) ((x) == ' ')
464#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
465#define is_digit_char(x) (digit_chars[(unsigned char) x])
466
0234cb7c 467/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 468static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
469
470/* md_assemble() always leaves the strings it's passed unaltered. To
471 effect this we maintain a stack of saved characters that we've smashed
472 with '\0's (indicating end of strings for various sub-fields of the
47926f60 473 assembler instruction). */
252b5132 474static char save_stack[32];
ce8a8b2f 475static char *save_stack_p;
252b5132
RH		 476#define END_STRING_AND_SAVE(s) \
477 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
478#define RESTORE_END_STRING(s) \
479 do { *(s) = *--save_stack_p; } while (0)
480
47926f60 481/* The instruction we're assembling. */
252b5132
RH		 482static i386_insn i;
483
484/* Possible templates for current insn. */
485static const templates *current_templates;
486
31b2323c
L		 487/* Per instruction expressionS buffers: max displacements & immediates. */
488static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
489static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 490
47926f60 491/* Current operand we are working on. */
ee86248c 492static int this_operand = -1;
252b5132 493
3e73aa7c
JH		 494/* We support four different modes. FLAG_CODE variable is used to distinguish
495 these. */
496
497enum flag_code {
498 CODE_32BIT,
499 CODE_16BIT,
500 CODE_64BIT };
501
502static enum flag_code flag_code;
4fa24527 503static unsigned int object_64bit;
862be3fb 504static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 505static int use_rela_relocations = 0;
506
7af8ed2d
NC		 507#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
508 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
509 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
510
351f65ca
L		 511/* The ELF ABI to use. */
512enum x86_elf_abi
513{
514 I386_ABI,
7f56bc95
L		 515 X86_64_ABI,
516 X86_64_X32_ABI
351f65ca
L		 517};
518
519static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 520#endif
351f65ca 521
167ad85b
TG		 522#if defined (TE_PE) || defined (TE_PEP)
523/* Use big object file format. */
524static int use_big_obj = 0;
525#endif
526
8dcea932
L		 527#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
528/* 1 if generating code for a shared library. */
529static int shared = 0;
530#endif
531
47926f60
KH		 532/* 1 for intel syntax,
533 0 if att syntax. */
534static int intel_syntax = 0;
252b5132 535
1efbbeb4
L		 536/* 1 for intel mnemonic,
537 0 if att mnemonic. */
538static int intel_mnemonic = !SYSV386_COMPAT;
539
5209009a 540/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 541static int old_gcc = OLDGCC_COMPAT;
542
a60de03c
JB		 543/* 1 if pseudo registers are permitted. */
544static int allow_pseudo_reg = 0;
545
47926f60
KH		 546/* 1 if register prefix % not required. */
547static int allow_naked_reg = 0;
252b5132 548
7e8b059b
L		 549/* 1 if the assembler should add BND prefix for all control-tranferring
550 instructions supporting it, even if this prefix wasn't specified
551 explicitly. */
552static int add_bnd_prefix = 0;
553
ba104c83 554/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 555static int allow_index_reg = 0;
556
d022bddd
IT		 557/* 1 if the assembler should ignore LOCK prefix, even if it was
558 specified explicitly. */
559static int omit_lock_prefix = 0;
560
7bab8ab5 561static enum check_kind
daf50ae7 562 {
7bab8ab5
JB		 563 check_none = 0,
564 check_warning,
565 check_error
daf50ae7 566 }
7bab8ab5 567sse_check, operand_check = check_warning;
daf50ae7 568
2ca3ace5
L		 569/* Register prefix used for error message. */
570static const char *register_prefix = "%";
571
47926f60
KH		 572/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
573 leave, push, and pop instructions so that gcc has the same stack
574 frame as in 32 bit mode. */
575static char stackop_size = '\0';
eecb386c 576
12b55ccc
L		 577/* Non-zero to optimize code alignment. */
578int optimize_align_code = 1;
579
47926f60
KH		 580/* Non-zero to quieten some warnings. */
581static int quiet_warnings = 0;
a38cf1db 582
47926f60
KH		 583/* CPU name. */
584static const char *cpu_arch_name = NULL;
6305a203 585static char *cpu_sub_arch_name = NULL;
a38cf1db 586
47926f60 587/* CPU feature flags. */
40fb9820
L		 588static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
589
ccc9c027
L		 590/* If we have selected a cpu we are generating instructions for. */
591static int cpu_arch_tune_set = 0;
592
9103f4f4 593/* Cpu we are generating instructions for. */
fbf3f584 594enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 595
596/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 597static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 598
ccc9c027 599/* CPU instruction set architecture used. */
fbf3f584 600enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 601
9103f4f4 602/* CPU feature flags of instruction set architecture used. */
fbf3f584 603i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 604
fddf5b5b
AM		 605/* If set, conditional jumps are not automatically promoted to handle
606 larger than a byte offset. */
607static unsigned int no_cond_jump_promotion = 0;
608
c0f3af97
L		 609/* Encode SSE instructions with VEX prefix. */
610static unsigned int sse2avx;
611
539f890d
L		 612/* Encode scalar AVX instructions with specific vector length. */
613static enum
614 {
615 vex128 = 0,
616 vex256
617 } avxscalar;
618
43234a1e
L		 619/* Encode scalar EVEX LIG instructions with specific vector length. */
620static enum
621 {
622 evexl128 = 0,
623 evexl256,
624 evexl512
625 } evexlig;
626
627/* Encode EVEX WIG instructions with specific evex.w. */
628static enum
629 {
630 evexw0 = 0,
631 evexw1
632 } evexwig;
633
d3d3c6db
IT		 634/* Value to encode in EVEX RC bits, for SAE-only instructions. */
635static enum rc_type evexrcig = rne;
636
29b0f896 637/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 638static symbolS *GOT_symbol;
29b0f896 639
a4447b93
RH		 640/* The dwarf2 return column, adjusted for 32 or 64 bit. */
641unsigned int x86_dwarf2_return_column;
642
643/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
644int x86_cie_data_alignment;
645
252b5132 646/* Interface to relax_segment.
fddf5b5b
AM		 647 There are 3 major relax states for 386 jump insns because the
648 different types of jumps add different sizes to frags when we're
649 figuring out what sort of jump to choose to reach a given label. */
252b5132 650
47926f60 651/* Types. */
93c2a809
AM		 652#define UNCOND_JUMP 0
653#define COND_JUMP 1
654#define COND_JUMP86 2
fddf5b5b 655
47926f60 656/* Sizes. */
252b5132
RH		 657#define CODE16 1
658#define SMALL 0
29b0f896 659#define SMALL16 (SMALL | CODE16)
252b5132 660#define BIG 2
29b0f896 661#define BIG16 (BIG | CODE16)
252b5132
RH		 662
663#ifndef INLINE
664#ifdef __GNUC__
665#define INLINE __inline__
666#else
667#define INLINE
668#endif
669#endif
670
fddf5b5b
AM		 671#define ENCODE_RELAX_STATE(type, size) \
672 ((relax_substateT) (((type) << 2) | (size)))
673#define TYPE_FROM_RELAX_STATE(s) \
674 ((s) >> 2)
675#define DISP_SIZE_FROM_RELAX_STATE(s) \
676 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 677
678/* This table is used by relax_frag to promote short jumps to long
679 ones where necessary. SMALL (short) jumps may be promoted to BIG
680 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
681 don't allow a short jump in a 32 bit code segment to be promoted to
682 a 16 bit offset jump because it's slower (requires data size
683 prefix), and doesn't work, unless the destination is in the bottom
684 64k of the code segment (The top 16 bits of eip are zeroed). */
685
686const relax_typeS md_relax_table[] =
687{
24eab124
AM		 688 /* The fields are:
689 1) most positive reach of this state,
690 2) most negative reach of this state,
93c2a809 691 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 692 4) which index into the table to try if we can't fit into this one. */
252b5132 693
fddf5b5b 694 /* UNCOND_JUMP states. */
93c2a809
AM		 695 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
696 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
697 /* dword jmp adds 4 bytes to frag:
698 0 extra opcode bytes, 4 displacement bytes. */
252b5132 699 {0, 0, 4, 0},
93c2a809
AM		 700 /* word jmp adds 2 byte2 to frag:
701 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 702 {0, 0, 2, 0},
703
93c2a809
AM		 704 /* COND_JUMP states. */
705 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
706 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
707 /* dword conditionals adds 5 bytes to frag:
708 1 extra opcode byte, 4 displacement bytes. */
709 {0, 0, 5, 0},
fddf5b5b 710 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 711 1 extra opcode byte, 2 displacement bytes. */
712 {0, 0, 3, 0},
713
714 /* COND_JUMP86 states. */
715 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
716 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
717 /* dword conditionals adds 5 bytes to frag:
718 1 extra opcode byte, 4 displacement bytes. */
719 {0, 0, 5, 0},
720 /* word conditionals add 4 bytes to frag:
721 1 displacement byte and a 3 byte long branch insn. */
722 {0, 0, 4, 0}
252b5132
RH		 723};
724
9103f4f4
L		 725static const arch_entry cpu_arch[] =
726{
89507696
JB		 727 /* Do not replace the first two entries - i386_target_format()
728 relies on them being there in this order. */
8a2c8fef 729 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
22109423 730 CPU_GENERIC32_FLAGS, 0, 0 },
8a2c8fef 731 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
22109423 732 CPU_GENERIC64_FLAGS, 0, 0 },
8a2c8fef 733 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
22109423 734 CPU_NONE_FLAGS, 0, 0 },
8a2c8fef 735 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
22109423 736 CPU_I186_FLAGS, 0, 0 },
8a2c8fef 737 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
22109423 738 CPU_I286_FLAGS, 0, 0 },
8a2c8fef 739 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
22109423 740 CPU_I386_FLAGS, 0, 0 },
8a2c8fef 741 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
22109423 742 CPU_I486_FLAGS, 0, 0 },
8a2c8fef 743 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
22109423 744 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 745 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
22109423 746 CPU_I686_FLAGS, 0, 0 },
8a2c8fef 747 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
22109423 748 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 749 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
22109423 750 CPU_PENTIUMPRO_FLAGS, 0, 0 },
8a2c8fef 751 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
22109423 752 CPU_P2_FLAGS, 0, 0 },
8a2c8fef 753 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
22109423 754 CPU_P3_FLAGS, 0, 0 },
8a2c8fef 755 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
22109423 756 CPU_P4_FLAGS, 0, 0 },
8a2c8fef 757 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
22109423 758 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 759 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
22109423 760 CPU_NOCONA_FLAGS, 0, 0 },
8a2c8fef 761 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
22109423 762 CPU_CORE_FLAGS, 1, 0 },
8a2c8fef 763 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
22109423 764 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 765 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
22109423 766 CPU_CORE2_FLAGS, 1, 0 },
8a2c8fef 767 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
22109423 768 CPU_CORE2_FLAGS, 0, 0 },
8a2c8fef 769 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
22109423 770 CPU_COREI7_FLAGS, 0, 0 },
8a2c8fef 771 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
22109423 772 CPU_L1OM_FLAGS, 0, 0 },
7a9068fe
L		 773 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
774 CPU_K1OM_FLAGS, 0, 0 },
81486035
L		 775 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
776 CPU_IAMCU_FLAGS, 0, 0 },
8a2c8fef 777 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
22109423 778 CPU_K6_FLAGS, 0, 0 },
8a2c8fef 779 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
22109423 780 CPU_K6_2_FLAGS, 0, 0 },
8a2c8fef 781 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
22109423 782 CPU_ATHLON_FLAGS, 0, 0 },
8a2c8fef 783 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
22109423 784 CPU_K8_FLAGS, 1, 0 },
8a2c8fef 785 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
22109423 786 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 787 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
22109423 788 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 789 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
22109423 790 CPU_AMDFAM10_FLAGS, 0, 0 },
8aedb9fe 791 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
22109423 792 CPU_BDVER1_FLAGS, 0, 0 },
8aedb9fe 793 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
af2f724e 794 CPU_BDVER2_FLAGS, 0, 0 },
5e5c50d3
NE		 795 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
796 CPU_BDVER3_FLAGS, 0, 0 },
c7b0bd56
SE		 797 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
798 CPU_BDVER4_FLAGS, 0, 0 },
029f3522 799 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
3739860c 800 CPU_ZNVER1_FLAGS, 0, 0 },
7b458c12
L		 801 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
802 CPU_BTVER1_FLAGS, 0, 0 },
803 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
804 CPU_BTVER2_FLAGS, 0, 0 },
8a2c8fef 805 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
22109423 806 CPU_8087_FLAGS, 0, 0 },
8a2c8fef 807 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
22109423 808 CPU_287_FLAGS, 0, 0 },
8a2c8fef 809 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
22109423 810 CPU_387_FLAGS, 0, 0 },
8a2c8fef 811 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
22109423 812 CPU_ANY87_FLAGS, 0, 1 },
8a2c8fef 813 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
22109423 814 CPU_MMX_FLAGS, 0, 0 },
8a2c8fef 815 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
22109423 816 CPU_3DNOWA_FLAGS, 0, 1 },
8a2c8fef 817 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
22109423 818 CPU_SSE_FLAGS, 0, 0 },
8a2c8fef 819 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
22109423 820 CPU_SSE2_FLAGS, 0, 0 },
8a2c8fef 821 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
22109423 822 CPU_SSE3_FLAGS, 0, 0 },
8a2c8fef 823 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
22109423 824 CPU_SSSE3_FLAGS, 0, 0 },
8a2c8fef 825 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
22109423 826 CPU_SSE4_1_FLAGS, 0, 0 },
8a2c8fef 827 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
22109423 828 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 829 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
22109423 830 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 831 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
22109423 832 CPU_ANY_SSE_FLAGS, 0, 1 },
8a2c8fef 833 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
22109423 834 CPU_AVX_FLAGS, 0, 0 },
6c30d220
L		 835 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
836 CPU_AVX2_FLAGS, 0, 0 },
43234a1e
L		 837 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
838 CPU_AVX512F_FLAGS, 0, 0 },
839 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
840 CPU_AVX512CD_FLAGS, 0, 0 },
841 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
842 CPU_AVX512ER_FLAGS, 0, 0 },
843 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
844 CPU_AVX512PF_FLAGS, 0, 0 },
1dfc6506
L		 845 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
846 CPU_AVX512DQ_FLAGS, 0, 0 },
847 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
848 CPU_AVX512BW_FLAGS, 0, 0 },
849 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
850 CPU_AVX512VL_FLAGS, 0, 0 },
8a2c8fef 851 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
22109423 852 CPU_ANY_AVX_FLAGS, 0, 1 },
8a2c8fef 853 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
22109423 854 CPU_VMX_FLAGS, 0, 0 },
8729a6f6
L		 855 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
856 CPU_VMFUNC_FLAGS, 0, 0 },
8a2c8fef 857 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
22109423 858 CPU_SMX_FLAGS, 0, 0 },
8a2c8fef 859 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
22109423 860 CPU_XSAVE_FLAGS, 0, 0 },
c7b8aa3a 861 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
22109423 862 CPU_XSAVEOPT_FLAGS, 0, 0 },
1dfc6506
L		 863 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
864 CPU_XSAVEC_FLAGS, 0, 0 },
865 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
866 CPU_XSAVES_FLAGS, 0, 0 },
8a2c8fef 867 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
22109423 868 CPU_AES_FLAGS, 0, 0 },
8a2c8fef 869 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
22109423 870 CPU_PCLMUL_FLAGS, 0, 0 },
8a2c8fef 871 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
22109423 872 CPU_PCLMUL_FLAGS, 1, 0 },
c7b8aa3a 873 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
22109423 874 CPU_FSGSBASE_FLAGS, 0, 0 },
c7b8aa3a 875 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
22109423 876 CPU_RDRND_FLAGS, 0, 0 },
c7b8aa3a 877 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
22109423 878 CPU_F16C_FLAGS, 0, 0 },
6c30d220
L		 879 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
880 CPU_BMI2_FLAGS, 0, 0 },
8a2c8fef 881 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
22109423 882 CPU_FMA_FLAGS, 0, 0 },
8a2c8fef 883 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
22109423 884 CPU_FMA4_FLAGS, 0, 0 },
8a2c8fef 885 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
22109423 886 CPU_XOP_FLAGS, 0, 0 },
8a2c8fef 887 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
22109423 888 CPU_LWP_FLAGS, 0, 0 },
8a2c8fef 889 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
22109423 890 CPU_MOVBE_FLAGS, 0, 0 },
60aa667e
L		 891 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
892 CPU_CX16_FLAGS, 0, 0 },
8a2c8fef 893 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
22109423 894 CPU_EPT_FLAGS, 0, 0 },
6c30d220
L		 895 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
896 CPU_LZCNT_FLAGS, 0, 0 },
42164a71
L		 897 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
898 CPU_HLE_FLAGS, 0, 0 },
899 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
900 CPU_RTM_FLAGS, 0, 0 },
6c30d220
L		 901 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
902 CPU_INVPCID_FLAGS, 0, 0 },
8a2c8fef 903 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
22109423
L		 904 CPU_CLFLUSH_FLAGS, 0, 0 },
905 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
906 CPU_NOP_FLAGS, 0, 0 },
8a2c8fef 907 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
22109423 908 CPU_SYSCALL_FLAGS, 0, 0 },
8a2c8fef 909 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
22109423 910 CPU_RDTSCP_FLAGS, 0, 0 },
8a2c8fef 911 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
22109423 912 CPU_3DNOW_FLAGS, 0, 0 },
8a2c8fef 913 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
22109423 914 CPU_3DNOWA_FLAGS, 0, 0 },
8a2c8fef 915 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
22109423 916 CPU_PADLOCK_FLAGS, 0, 0 },
8a2c8fef 917 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
22109423 918 CPU_SVME_FLAGS, 1, 0 },
8a2c8fef 919 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
22109423 920 CPU_SVME_FLAGS, 0, 0 },
8a2c8fef 921 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
22109423 922 CPU_SSE4A_FLAGS, 0, 0 },
8a2c8fef 923 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
22109423 924 CPU_ABM_FLAGS, 0, 0 },
87973e9f
QN		 925 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
926 CPU_BMI_FLAGS, 0, 0 },
2a2a0f38
QN		 927 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
928 CPU_TBM_FLAGS, 0, 0 },
e2e1fcde
L		 929 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
930 CPU_ADX_FLAGS, 0, 0 },
931 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
932 CPU_RDSEED_FLAGS, 0, 0 },
933 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
934 CPU_PRFCHW_FLAGS, 0, 0 },
5c111e37
L		 935 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
936 CPU_SMAP_FLAGS, 0, 0 },
7e8b059b
L		 937 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
938 CPU_MPX_FLAGS, 0, 0 },
a0046408
L		 939 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
940 CPU_SHA_FLAGS, 0, 0 },
963f3586
IT		 941 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
942 CPU_CLFLUSHOPT_FLAGS, 0, 0 },
dcf893b5
IT		 943 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
944 CPU_PREFETCHWT1_FLAGS, 0, 0 },
2cf200a4
IT		 945 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
946 CPU_SE1_FLAGS, 0, 0 },
c5e7287a
IT		 947 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
948 CPU_CLWB_FLAGS, 0, 0 },
9d8596f0
IT		 949 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN,
950 CPU_PCOMMIT_FLAGS, 0, 0 },
2cc1b5aa
IT		 951 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
952 CPU_AVX512IFMA_FLAGS, 0, 0 },
14f195c9
IT		 953 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
954 CPU_AVX512VBMI_FLAGS, 0, 0 },
029f3522
GG		 955 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
956 CPU_CLZERO_FLAGS, 0, 0 },
9916071f
AP		 957 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
958 CPU_MWAITX_FLAGS, 0, 0 },
e413e4e9
AM		 959};
960
704209c0 961#ifdef I386COFF
a6c24e68
NC		 962/* Like s_lcomm_internal in gas/read.c but the alignment string
963 is allowed to be optional. */
964
965static symbolS *
966pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
967{
968 addressT align = 0;
969
970 SKIP_WHITESPACE ();
971
7ab9ffdd 972 if (needs_align
a6c24e68
NC		 973 && *input_line_pointer == ',')
974 {
975 align = parse_align (needs_align - 1);
7ab9ffdd 976
a6c24e68
NC		 977 if (align == (addressT) -1)
978 return NULL;
979 }
980 else
981 {
982 if (size >= 8)
983 align = 3;
984 else if (size >= 4)
985 align = 2;
986 else if (size >= 2)
987 align = 1;
988 else
989 align = 0;
990 }
991
992 bss_alloc (symbolP, size, align);
993 return symbolP;
994}
995
704209c0 996static void
a6c24e68
NC		 997pe_lcomm (int needs_align)
998{
999 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1000}
704209c0 1001#endif
a6c24e68 1002
29b0f896
AM		 1003const pseudo_typeS md_pseudo_table[] =
1004{
1005#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1006 {"align", s_align_bytes, 0},
1007#else
1008 {"align", s_align_ptwo, 0},
1009#endif
1010 {"arch", set_cpu_arch, 0},
1011#ifndef I386COFF
1012 {"bss", s_bss, 0},
a6c24e68
NC		 1013#else
1014 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1015#endif
1016 {"ffloat", float_cons, 'f'},
1017 {"dfloat", float_cons, 'd'},
1018 {"tfloat", float_cons, 'x'},
1019 {"value", cons, 2},
d182319b 1020 {"slong", signed_cons, 4},
29b0f896
AM		 1021 {"noopt", s_ignore, 0},
1022 {"optim", s_ignore, 0},
1023 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1024 {"code16", set_code_flag, CODE_16BIT},
1025 {"code32", set_code_flag, CODE_32BIT},
1026 {"code64", set_code_flag, CODE_64BIT},
1027 {"intel_syntax", set_intel_syntax, 1},
1028 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1029 {"intel_mnemonic", set_intel_mnemonic, 1},
1030 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1031 {"allow_index_reg", set_allow_index_reg, 1},
1032 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1033 {"sse_check", set_check, 0},
1034 {"operand_check", set_check, 1},
3b22753a
L		 1035#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1036 {"largecomm", handle_large_common, 0},
07a53e5c 1037#else
e3bb37b5 1038 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 1039 {"loc", dwarf2_directive_loc, 0},
1040 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1041#endif
6482c264
NC		 1042#ifdef TE_PE
1043 {"secrel32", pe_directive_secrel, 0},
1044#endif
29b0f896
AM		 1045 {0, 0, 0}
1046};
1047
1048/* For interface with expression (). */
1049extern char *input_line_pointer;
1050
1051/* Hash table for instruction mnemonic lookup. */
1052static struct hash_control *op_hash;
1053
1054/* Hash table for register lookup. */
1055static struct hash_control *reg_hash;
1056\f
252b5132 1057void
e3bb37b5 1058i386_align_code (fragS *fragP, int count)
252b5132 1059{
ce8a8b2f
AM		 1060 /* Various efficient no-op patterns for aligning code labels.
1061 Note: Don't try to assemble the instructions in the comments.
1062 0L and 0w are not legal. */
252b5132
RH		 1063 static const char f32_1[] =
1064 {0x90}; /* nop */
1065 static const char f32_2[] =
ccc9c027 1066 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 1067 static const char f32_3[] =
1068 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1069 static const char f32_4[] =
1070 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1071 static const char f32_5[] =
1072 {0x90, /* nop */
1073 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1074 static const char f32_6[] =
1075 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1076 static const char f32_7[] =
1077 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1078 static const char f32_8[] =
1079 {0x90, /* nop */
1080 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1081 static const char f32_9[] =
1082 {0x89,0xf6, /* movl %esi,%esi */
1083 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1084 static const char f32_10[] =
1085 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1086 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1087 static const char f32_11[] =
1088 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1089 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1090 static const char f32_12[] =
1091 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1092 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1093 static const char f32_13[] =
1094 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1095 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1096 static const char f32_14[] =
1097 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1098 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 1099 static const char f16_3[] =
1100 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 1101 static const char f16_4[] =
1102 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1103 static const char f16_5[] =
1104 {0x90, /* nop */
1105 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1106 static const char f16_6[] =
1107 {0x89,0xf6, /* mov %si,%si */
1108 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1109 static const char f16_7[] =
1110 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1111 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1112 static const char f16_8[] =
1113 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1114 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 1115 static const char jump_31[] =
1116 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1117 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1118 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1119 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 1120 static const char *const f32_patt[] = {
1121 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1122 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 1123 };
1124 static const char *const f16_patt[] = {
76bc74dc 1125 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1126 };
ccc9c027
L		 1127 /* nopl (%[re]ax) */
1128 static const char alt_3[] =
1129 {0x0f,0x1f,0x00};
1130 /* nopl 0(%[re]ax) */
1131 static const char alt_4[] =
1132 {0x0f,0x1f,0x40,0x00};
1133 /* nopl 0(%[re]ax,%[re]ax,1) */
1134 static const char alt_5[] =
1135 {0x0f,0x1f,0x44,0x00,0x00};
1136 /* nopw 0(%[re]ax,%[re]ax,1) */
1137 static const char alt_6[] =
1138 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1139 /* nopl 0L(%[re]ax) */
1140 static const char alt_7[] =
1141 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1142 /* nopl 0L(%[re]ax,%[re]ax,1) */
1143 static const char alt_8[] =
1144 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1145 /* nopw 0L(%[re]ax,%[re]ax,1) */
1146 static const char alt_9[] =
1147 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1148 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1149 static const char alt_10[] =
1150 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
80b8656c 1151 static const char *const alt_patt[] = {
ccc9c027 1152 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
80b8656c 1153 alt_9, alt_10
ccc9c027 1154 };
252b5132 1155
76bc74dc
L		 1156 /* Only align for at least a positive non-zero boundary. */
1157 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1158 return;
3e73aa7c 1159
ccc9c027
L		 1160 /* We need to decide which NOP sequence to use for 32bit and
1161 64bit. When -mtune= is used:
4eed87de 1162
76bc74dc
L		 1163 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1164 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1165 2. For the rest, alt_patt will be used.
1166
1167 When -mtune= isn't used, alt_patt will be used if
22109423 1168 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1169 be used.
ccc9c027
L		 1170
1171 When -march= or .arch is used, we can't use anything beyond
1172 cpu_arch_isa_flags. */
1173
1174 if (flag_code == CODE_16BIT)
1175 {
ccc9c027 1176 if (count > 8)
33fef721 1177 {
76bc74dc
L		 1178 memcpy (fragP->fr_literal + fragP->fr_fix,
1179 jump_31, count);
1180 /* Adjust jump offset. */
1181 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1182 }
76bc74dc
L		 1183 else
1184 memcpy (fragP->fr_literal + fragP->fr_fix,
1185 f16_patt[count - 1], count);
252b5132 1186 }
33fef721 1187 else
ccc9c027
L		 1188 {
1189 const char *const *patt = NULL;
1190
fbf3f584 1191 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1192 {
1193 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1194 switch (cpu_arch_tune)
1195 {
1196 case PROCESSOR_UNKNOWN:
1197 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1198 optimize with nops. */
1199 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1200 patt = alt_patt;
ccc9c027
L		 1201 else
1202 patt = f32_patt;
1203 break;
ccc9c027
L		 1204 case PROCESSOR_PENTIUM4:
1205 case PROCESSOR_NOCONA:
ef05d495 1206 case PROCESSOR_CORE:
76bc74dc 1207 case PROCESSOR_CORE2:
bd5295b2 1208 case PROCESSOR_COREI7:
3632d14b 1209 case PROCESSOR_L1OM:
7a9068fe 1210 case PROCESSOR_K1OM:
76bc74dc 1211 case PROCESSOR_GENERIC64:
ccc9c027
L		 1212 case PROCESSOR_K6:
1213 case PROCESSOR_ATHLON:
1214 case PROCESSOR_K8:
4eed87de 1215 case PROCESSOR_AMDFAM10:
8aedb9fe 1216 case PROCESSOR_BD:
029f3522 1217 case PROCESSOR_ZNVER:
7b458c12 1218 case PROCESSOR_BT:
80b8656c 1219 patt = alt_patt;
ccc9c027 1220 break;
76bc74dc 1221 case PROCESSOR_I386:
ccc9c027
L		 1222 case PROCESSOR_I486:
1223 case PROCESSOR_PENTIUM:
2dde1948 1224 case PROCESSOR_PENTIUMPRO:
81486035 1225 case PROCESSOR_IAMCU:
ccc9c027
L		 1226 case PROCESSOR_GENERIC32:
1227 patt = f32_patt;
1228 break;
4eed87de 1229 }
ccc9c027
L		 1230 }
1231 else
1232 {
fbf3f584 1233 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1234 {
1235 case PROCESSOR_UNKNOWN:
e6a14101 1236 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1237 PROCESSOR_UNKNOWN. */
1238 abort ();
1239 break;
1240
76bc74dc 1241 case PROCESSOR_I386:
ccc9c027
L		 1242 case PROCESSOR_I486:
1243 case PROCESSOR_PENTIUM:
81486035 1244 case PROCESSOR_IAMCU:
ccc9c027
L		 1245 case PROCESSOR_K6:
1246 case PROCESSOR_ATHLON:
1247 case PROCESSOR_K8:
4eed87de 1248 case PROCESSOR_AMDFAM10:
8aedb9fe 1249 case PROCESSOR_BD:
029f3522 1250 case PROCESSOR_ZNVER:
7b458c12 1251 case PROCESSOR_BT:
ccc9c027
L		 1252 case PROCESSOR_GENERIC32:
1253 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1254 with nops. */
1255 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1256 patt = alt_patt;
ccc9c027
L		 1257 else
1258 patt = f32_patt;
1259 break;
76bc74dc
L		 1260 case PROCESSOR_PENTIUMPRO:
1261 case PROCESSOR_PENTIUM4:
1262 case PROCESSOR_NOCONA:
1263 case PROCESSOR_CORE:
ef05d495 1264 case PROCESSOR_CORE2:
bd5295b2 1265 case PROCESSOR_COREI7:
3632d14b 1266 case PROCESSOR_L1OM:
7a9068fe 1267 case PROCESSOR_K1OM:
22109423 1268 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1269 patt = alt_patt;
ccc9c027
L		 1270 else
1271 patt = f32_patt;
1272 break;
1273 case PROCESSOR_GENERIC64:
80b8656c 1274 patt = alt_patt;
ccc9c027 1275 break;
4eed87de 1276 }
ccc9c027
L		 1277 }
1278
76bc74dc
L		 1279 if (patt == f32_patt)
1280 {
1281 /* If the padding is less than 15 bytes, we use the normal
1282 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1283 its offset. */
1284 int limit;
76ba9986 1285
711eedef
L		 1286 /* For 64bit, the limit is 3 bytes. */
1287 if (flag_code == CODE_64BIT
1288 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1289 limit = 3;
1290 else
1291 limit = 15;
1292 if (count < limit)
76bc74dc
L		 1293 memcpy (fragP->fr_literal + fragP->fr_fix,
1294 patt[count - 1], count);
1295 else
1296 {
1297 memcpy (fragP->fr_literal + fragP->fr_fix,
1298 jump_31, count);
1299 /* Adjust jump offset. */
1300 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1301 }
1302 }
1303 else
1304 {
80b8656c
L		 1305 /* Maximum length of an instruction is 10 byte. If the
1306 padding is greater than 10 bytes and we don't use jump,
76bc74dc
L		 1307 we have to break it into smaller pieces. */
1308 int padding = count;
80b8656c 1309 while (padding > 10)
76bc74dc 1310 {
80b8656c 1311 padding -= 10;
76bc74dc 1312 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
80b8656c 1313 patt [9], 10);
76bc74dc
L		 1314 }
1315
1316 if (padding)
1317 memcpy (fragP->fr_literal + fragP->fr_fix,
1318 patt [padding - 1], padding);
1319 }
ccc9c027 1320 }
33fef721 1321 fragP->fr_var = count;
252b5132
RH		 1322}
1323
c6fb90c8 1324static INLINE int
0dfbf9d7 1325operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1326{
0dfbf9d7 1327 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1328 {
1329 case 3:
0dfbf9d7 1330 if (x->array[2])
c6fb90c8
L		 1331 return 0;
1332 case 2:
0dfbf9d7 1333 if (x->array[1])
c6fb90c8
L		 1334 return 0;
1335 case 1:
0dfbf9d7 1336 return !x->array[0];
c6fb90c8
L		 1337 default:
1338 abort ();
1339 }
40fb9820
L		 1340}
1341
c6fb90c8 1342static INLINE void
0dfbf9d7 1343operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1344{
0dfbf9d7 1345 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1346 {
1347 case 3:
0dfbf9d7 1348 x->array[2] = v;
c6fb90c8 1349 case 2:
0dfbf9d7 1350 x->array[1] = v;
c6fb90c8 1351 case 1:
0dfbf9d7 1352 x->array[0] = v;
c6fb90c8
L		 1353 break;
1354 default:
1355 abort ();
1356 }
1357}
40fb9820 1358
c6fb90c8 1359static INLINE int
0dfbf9d7
L		 1360operand_type_equal (const union i386_operand_type *x,
1361 const union i386_operand_type *y)
c6fb90c8 1362{
0dfbf9d7 1363 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1364 {
1365 case 3:
0dfbf9d7 1366 if (x->array[2] != y->array[2])
c6fb90c8
L		 1367 return 0;
1368 case 2:
0dfbf9d7 1369 if (x->array[1] != y->array[1])
c6fb90c8
L		 1370 return 0;
1371 case 1:
0dfbf9d7 1372 return x->array[0] == y->array[0];
c6fb90c8
L		 1373 break;
1374 default:
1375 abort ();
1376 }
1377}
40fb9820 1378
0dfbf9d7
L		 1379static INLINE int
1380cpu_flags_all_zero (const union i386_cpu_flags *x)
1381{
1382 switch (ARRAY_SIZE(x->array))
1383 {
1384 case 3:
1385 if (x->array[2])
1386 return 0;
1387 case 2:
1388 if (x->array[1])
1389 return 0;
1390 case 1:
1391 return !x->array[0];
1392 default:
1393 abort ();
1394 }
1395}
1396
0dfbf9d7
L		 1397static INLINE int
1398cpu_flags_equal (const union i386_cpu_flags *x,
1399 const union i386_cpu_flags *y)
1400{
1401 switch (ARRAY_SIZE(x->array))
1402 {
1403 case 3:
1404 if (x->array[2] != y->array[2])
1405 return 0;
1406 case 2:
1407 if (x->array[1] != y->array[1])
1408 return 0;
1409 case 1:
1410 return x->array[0] == y->array[0];
1411 break;
1412 default:
1413 abort ();
1414 }
1415}
c6fb90c8
L		 1416
1417static INLINE int
1418cpu_flags_check_cpu64 (i386_cpu_flags f)
1419{
1420 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1421 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1422}
1423
c6fb90c8
L		 1424static INLINE i386_cpu_flags
1425cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1426{
c6fb90c8
L		 1427 switch (ARRAY_SIZE (x.array))
1428 {
1429 case 3:
1430 x.array [2] &= y.array [2];
1431 case 2:
1432 x.array [1] &= y.array [1];
1433 case 1:
1434 x.array [0] &= y.array [0];
1435 break;
1436 default:
1437 abort ();
1438 }
1439 return x;
1440}
40fb9820 1441
c6fb90c8
L		 1442static INLINE i386_cpu_flags
1443cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1444{
c6fb90c8 1445 switch (ARRAY_SIZE (x.array))
40fb9820 1446 {
c6fb90c8
L		 1447 case 3:
1448 x.array [2] |= y.array [2];
1449 case 2:
1450 x.array [1] |= y.array [1];
1451 case 1:
1452 x.array [0] |= y.array [0];
40fb9820
L		 1453 break;
1454 default:
1455 abort ();
1456 }
40fb9820
L		 1457 return x;
1458}
1459
309d3373
JB		 1460static INLINE i386_cpu_flags
1461cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1462{
1463 switch (ARRAY_SIZE (x.array))
1464 {
1465 case 3:
1466 x.array [2] &= ~y.array [2];
1467 case 2:
1468 x.array [1] &= ~y.array [1];
1469 case 1:
1470 x.array [0] &= ~y.array [0];
1471 break;
1472 default:
1473 abort ();
1474 }
1475 return x;
1476}
1477
81486035
L		 1478static int
1479valid_iamcu_cpu_flags (const i386_cpu_flags *flags)
1480{
1481 if (cpu_arch_isa == PROCESSOR_IAMCU)
1482 {
1483 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_COMPAT_FLAGS;
1484 i386_cpu_flags compat_flags;
1485 compat_flags = cpu_flags_and_not (*flags, iamcu_flags);
1486 return cpu_flags_all_zero (&compat_flags);
1487 }
1488 else
1489 return 1;
1490}
1491
c0f3af97
L		 1492#define CPU_FLAGS_ARCH_MATCH 0x1
1493#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1494#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1495#define CPU_FLAGS_PCLMUL_MATCH 0x8
1496#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1497
a5ff0eb2 1498#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1499 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1500 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1501#define CPU_FLAGS_PERFECT_MATCH \
1502 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1503
1504/* Return CPU flags match bits. */
3629bb00 1505
40fb9820 1506static int
d3ce72d0 1507cpu_flags_match (const insn_template *t)
40fb9820 1508{
c0f3af97
L		 1509 i386_cpu_flags x = t->cpu_flags;
1510 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1511
1512 x.bitfield.cpu64 = 0;
1513 x.bitfield.cpuno64 = 0;
1514
0dfbf9d7 1515 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1516 {
1517 /* This instruction is available on all archs. */
1518 match |= CPU_FLAGS_32BIT_MATCH;
1519 }
3629bb00
L		 1520 else
1521 {
c0f3af97 1522 /* This instruction is available only on some archs. */
3629bb00
L		 1523 i386_cpu_flags cpu = cpu_arch_flags;
1524
1525 cpu.bitfield.cpu64 = 0;
1526 cpu.bitfield.cpuno64 = 0;
1527 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1528 if (!cpu_flags_all_zero (&cpu))
1529 {
a5ff0eb2
L		 1530 if (x.bitfield.cpuavx)
1531 {
ce2f5b3c 1532 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1533 if (cpu.bitfield.cpuavx)
1534 {
1535 /* Check SSE2AVX. */
1536 if (!t->opcode_modifier.sse2avx|| sse2avx)
1537 {
1538 match |= (CPU_FLAGS_ARCH_MATCH
1539 | CPU_FLAGS_AVX_MATCH);
1540 /* Check AES. */
1541 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1542 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1543 /* Check PCLMUL. */
1544 if (!x.bitfield.cpupclmul
1545 || cpu.bitfield.cpupclmul)
1546 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1547 }
1548 }
1549 else
1550 match |= CPU_FLAGS_ARCH_MATCH;
1551 }
1552 else
c0f3af97
L		 1553 match |= CPU_FLAGS_32BIT_MATCH;
1554 }
3629bb00 1555 }
c0f3af97 1556 return match;
40fb9820
L		 1557}
1558
c6fb90c8
L		 1559static INLINE i386_operand_type
1560operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1561{
c6fb90c8
L		 1562 switch (ARRAY_SIZE (x.array))
1563 {
1564 case 3:
1565 x.array [2] &= y.array [2];
1566 case 2:
1567 x.array [1] &= y.array [1];
1568 case 1:
1569 x.array [0] &= y.array [0];
1570 break;
1571 default:
1572 abort ();
1573 }
1574 return x;
40fb9820
L		 1575}
1576
c6fb90c8
L		 1577static INLINE i386_operand_type
1578operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1579{
c6fb90c8 1580 switch (ARRAY_SIZE (x.array))
40fb9820 1581 {
c6fb90c8
L		 1582 case 3:
1583 x.array [2] |= y.array [2];
1584 case 2:
1585 x.array [1] |= y.array [1];
1586 case 1:
1587 x.array [0] |= y.array [0];
40fb9820
L		 1588 break;
1589 default:
1590 abort ();
1591 }
c6fb90c8
L		 1592 return x;
1593}
40fb9820 1594
c6fb90c8
L		 1595static INLINE i386_operand_type
1596operand_type_xor (i386_operand_type x, i386_operand_type y)
1597{
1598 switch (ARRAY_SIZE (x.array))
1599 {
1600 case 3:
1601 x.array [2] ^= y.array [2];
1602 case 2:
1603 x.array [1] ^= y.array [1];
1604 case 1:
1605 x.array [0] ^= y.array [0];
1606 break;
1607 default:
1608 abort ();
1609 }
40fb9820
L		 1610 return x;
1611}
1612
1613static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1614static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1615static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1616static const i386_operand_type inoutportreg
1617 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1618static const i386_operand_type reg16_inoutportreg
1619 = OPERAND_TYPE_REG16_INOUTPORTREG;
1620static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1621static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1622static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1623static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1624static const i386_operand_type anydisp
1625 = OPERAND_TYPE_ANYDISP;
40fb9820 1626static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1627static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1628static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1629static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1630static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1631static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1632static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1633static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1634static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1635static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1636static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1637static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1638static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1639static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1640
1641enum operand_type
1642{
1643 reg,
40fb9820
L		 1644 imm,
1645 disp,
1646 anymem
1647};
1648
c6fb90c8 1649static INLINE int
40fb9820
L		 1650operand_type_check (i386_operand_type t, enum operand_type c)
1651{
1652 switch (c)
1653 {
1654 case reg:
1655 return (t.bitfield.reg8
1656 || t.bitfield.reg16
1657 || t.bitfield.reg32
1658 || t.bitfield.reg64);
1659
40fb9820
L		 1660 case imm:
1661 return (t.bitfield.imm8
1662 || t.bitfield.imm8s
1663 || t.bitfield.imm16
1664 || t.bitfield.imm32
1665 || t.bitfield.imm32s
1666 || t.bitfield.imm64);
1667
1668 case disp:
1669 return (t.bitfield.disp8
1670 || t.bitfield.disp16
1671 || t.bitfield.disp32
1672 || t.bitfield.disp32s
1673 || t.bitfield.disp64);
1674
1675 case anymem:
1676 return (t.bitfield.disp8
1677 || t.bitfield.disp16
1678 || t.bitfield.disp32
1679 || t.bitfield.disp32s
1680 || t.bitfield.disp64
1681 || t.bitfield.baseindex);
1682
1683 default:
1684 abort ();
1685 }
2cfe26b6
AM		 1686
1687 return 0;
40fb9820
L		 1688}
1689
5c07affc
L		 1690/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1691 operand J for instruction template T. */
1692
1693static INLINE int
d3ce72d0 1694match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1695{
1696 return !((i.types[j].bitfield.byte
1697 && !t->operand_types[j].bitfield.byte)
1698 || (i.types[j].bitfield.word
1699 && !t->operand_types[j].bitfield.word)
1700 || (i.types[j].bitfield.dword
1701 && !t->operand_types[j].bitfield.dword)
1702 || (i.types[j].bitfield.qword
1703 && !t->operand_types[j].bitfield.qword));
1704}
1705
1706/* Return 1 if there is no conflict in any size on operand J for
1707 instruction template T. */
1708
1709static INLINE int
d3ce72d0 1710match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1711{
1712 return (match_reg_size (t, j)
1713 && !((i.types[j].bitfield.unspecified
af508cb9 1714 && !i.broadcast
5c07affc
L		 1715 && !t->operand_types[j].bitfield.unspecified)
1716 || (i.types[j].bitfield.fword
1717 && !t->operand_types[j].bitfield.fword)
1718 || (i.types[j].bitfield.tbyte
1719 && !t->operand_types[j].bitfield.tbyte)
1720 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1721 && !t->operand_types[j].bitfield.xmmword)
1722 || (i.types[j].bitfield.ymmword
43234a1e
L		 1723 && !t->operand_types[j].bitfield.ymmword)
1724 || (i.types[j].bitfield.zmmword
1725 && !t->operand_types[j].bitfield.zmmword)));
5c07affc
L		 1726}
1727
1728/* Return 1 if there is no size conflict on any operands for
1729 instruction template T. */
1730
1731static INLINE int
d3ce72d0 1732operand_size_match (const insn_template *t)
5c07affc
L		 1733{
1734 unsigned int j;
1735 int match = 1;
1736
1737 /* Don't check jump instructions. */
1738 if (t->opcode_modifier.jump
1739 || t->opcode_modifier.jumpbyte
1740 || t->opcode_modifier.jumpdword
1741 || t->opcode_modifier.jumpintersegment)
1742 return match;
1743
1744 /* Check memory and accumulator operand size. */
1745 for (j = 0; j < i.operands; j++)
1746 {
1747 if (t->operand_types[j].bitfield.anysize)
1748 continue;
1749
1750 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1751 {
1752 match = 0;
1753 break;
1754 }
1755
1756 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1757 {
1758 match = 0;
1759 break;
1760 }
1761 }
1762
891edac4 1763 if (match)
5c07affc 1764 return match;
891edac4
L		 1765 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1766 {
1767mismatch:
86e026a4 1768 i.error = operand_size_mismatch;
891edac4
L		 1769 return 0;
1770 }
5c07affc
L		 1771
1772 /* Check reverse. */
9c2799c2 1773 gas_assert (i.operands == 2);
5c07affc
L		 1774
1775 match = 1;
1776 for (j = 0; j < 2; j++)
1777 {
1778 if (t->operand_types[j].bitfield.acc
1779 && !match_reg_size (t, j ? 0 : 1))
891edac4 1780 goto mismatch;
5c07affc
L		 1781
1782 if (i.types[j].bitfield.mem
1783 && !match_mem_size (t, j ? 0 : 1))
891edac4 1784 goto mismatch;
5c07affc
L		 1785 }
1786
1787 return match;
1788}
1789
c6fb90c8 1790static INLINE int
40fb9820
L		 1791operand_type_match (i386_operand_type overlap,
1792 i386_operand_type given)
1793{
1794 i386_operand_type temp = overlap;
1795
1796 temp.bitfield.jumpabsolute = 0;
7d5e4556 1797 temp.bitfield.unspecified = 0;
5c07affc
L		 1798 temp.bitfield.byte = 0;
1799 temp.bitfield.word = 0;
1800 temp.bitfield.dword = 0;
1801 temp.bitfield.fword = 0;
1802 temp.bitfield.qword = 0;
1803 temp.bitfield.tbyte = 0;
1804 temp.bitfield.xmmword = 0;
c0f3af97 1805 temp.bitfield.ymmword = 0;
43234a1e 1806 temp.bitfield.zmmword = 0;
0dfbf9d7 1807 if (operand_type_all_zero (&temp))
891edac4 1808 goto mismatch;
40fb9820 1809
891edac4
L		 1810 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1811 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1812 return 1;
1813
1814mismatch:
a65babc9 1815 i.error = operand_type_mismatch;
891edac4 1816 return 0;
40fb9820
L		 1817}
1818
7d5e4556 1819/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1820 unless the expected operand type register overlap is null.
1821 Note that Acc in a template matches every size of reg. */
1822
c6fb90c8 1823static INLINE int
40fb9820
L		 1824operand_type_register_match (i386_operand_type m0,
1825 i386_operand_type g0,
1826 i386_operand_type t0,
1827 i386_operand_type m1,
1828 i386_operand_type g1,
1829 i386_operand_type t1)
1830{
1831 if (!operand_type_check (g0, reg))
1832 return 1;
1833
1834 if (!operand_type_check (g1, reg))
1835 return 1;
1836
1837 if (g0.bitfield.reg8 == g1.bitfield.reg8
1838 && g0.bitfield.reg16 == g1.bitfield.reg16
1839 && g0.bitfield.reg32 == g1.bitfield.reg32
1840 && g0.bitfield.reg64 == g1.bitfield.reg64)
1841 return 1;
1842
1843 if (m0.bitfield.acc)
1844 {
1845 t0.bitfield.reg8 = 1;
1846 t0.bitfield.reg16 = 1;
1847 t0.bitfield.reg32 = 1;
1848 t0.bitfield.reg64 = 1;
1849 }
1850
1851 if (m1.bitfield.acc)
1852 {
1853 t1.bitfield.reg8 = 1;
1854 t1.bitfield.reg16 = 1;
1855 t1.bitfield.reg32 = 1;
1856 t1.bitfield.reg64 = 1;
1857 }
1858
891edac4
L		 1859 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1860 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1861 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1862 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1863 return 1;
1864
a65babc9 1865 i.error = register_type_mismatch;
891edac4
L		 1866
1867 return 0;
40fb9820
L		 1868}
1869
4c692bc7
JB		 1870static INLINE unsigned int
1871register_number (const reg_entry *r)
1872{
1873 unsigned int nr = r->reg_num;
1874
1875 if (r->reg_flags & RegRex)
1876 nr += 8;
1877
1878 return nr;
1879}
1880
252b5132 1881static INLINE unsigned int
40fb9820 1882mode_from_disp_size (i386_operand_type t)
252b5132 1883{
43234a1e 1884 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
40fb9820
L		 1885 return 1;
1886 else if (t.bitfield.disp16
1887 || t.bitfield.disp32
1888 || t.bitfield.disp32s)
1889 return 2;
1890 else
1891 return 0;
252b5132
RH		 1892}
1893
1894static INLINE int
65879393 1895fits_in_signed_byte (addressT num)
252b5132 1896{
65879393 1897 return num + 0x80 <= 0xff;
47926f60 1898}
252b5132
RH		 1899
1900static INLINE int
65879393 1901fits_in_unsigned_byte (addressT num)
252b5132 1902{
65879393 1903 return num <= 0xff;
47926f60 1904}
252b5132
RH		 1905
1906static INLINE int
65879393 1907fits_in_unsigned_word (addressT num)
252b5132 1908{
65879393 1909 return num <= 0xffff;
47926f60 1910}
252b5132
RH		 1911
1912static INLINE int
65879393 1913fits_in_signed_word (addressT num)
252b5132 1914{
65879393 1915 return num + 0x8000 <= 0xffff;
47926f60 1916}
2a962e6d 1917
3e73aa7c 1918static INLINE int
65879393 1919fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1920{
1921#ifndef BFD64
1922 return 1;
1923#else
65879393 1924 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 1925#endif
1926} /* fits_in_signed_long() */
2a962e6d 1927
3e73aa7c 1928static INLINE int
65879393 1929fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1930{
1931#ifndef BFD64
1932 return 1;
1933#else
65879393 1934 return num <= 0xffffffff;
3e73aa7c
JH		 1935#endif
1936} /* fits_in_unsigned_long() */
252b5132 1937
43234a1e
L		 1938static INLINE int
1939fits_in_vec_disp8 (offsetT num)
1940{
1941 int shift = i.memshift;
1942 unsigned int mask;
1943
1944 if (shift == -1)
1945 abort ();
1946
1947 mask = (1 << shift) - 1;
1948
1949 /* Return 0 if NUM isn't properly aligned. */
1950 if ((num & mask))
1951 return 0;
1952
1953 /* Check if NUM will fit in 8bit after shift. */
1954 return fits_in_signed_byte (num >> shift);
1955}
1956
a683cc34
SP		 1957static INLINE int
1958fits_in_imm4 (offsetT num)
1959{
1960 return (num & 0xf) == num;
1961}
1962
40fb9820 1963static i386_operand_type
e3bb37b5 1964smallest_imm_type (offsetT num)
252b5132 1965{
40fb9820 1966 i386_operand_type t;
7ab9ffdd 1967
0dfbf9d7 1968 operand_type_set (&t, 0);
40fb9820
L		 1969 t.bitfield.imm64 = 1;
1970
1971 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1972 {
1973 /* This code is disabled on the 486 because all the Imm1 forms
1974 in the opcode table are slower on the i486. They're the
1975 versions with the implicitly specified single-position
1976 displacement, which has another syntax if you really want to
1977 use that form. */
40fb9820
L		 1978 t.bitfield.imm1 = 1;
1979 t.bitfield.imm8 = 1;
1980 t.bitfield.imm8s = 1;
1981 t.bitfield.imm16 = 1;
1982 t.bitfield.imm32 = 1;
1983 t.bitfield.imm32s = 1;
1984 }
1985 else if (fits_in_signed_byte (num))
1986 {
1987 t.bitfield.imm8 = 1;
1988 t.bitfield.imm8s = 1;
1989 t.bitfield.imm16 = 1;
1990 t.bitfield.imm32 = 1;
1991 t.bitfield.imm32s = 1;
1992 }
1993 else if (fits_in_unsigned_byte (num))
1994 {
1995 t.bitfield.imm8 = 1;
1996 t.bitfield.imm16 = 1;
1997 t.bitfield.imm32 = 1;
1998 t.bitfield.imm32s = 1;
1999 }
2000 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2001 {
2002 t.bitfield.imm16 = 1;
2003 t.bitfield.imm32 = 1;
2004 t.bitfield.imm32s = 1;
2005 }
2006 else if (fits_in_signed_long (num))
2007 {
2008 t.bitfield.imm32 = 1;
2009 t.bitfield.imm32s = 1;
2010 }
2011 else if (fits_in_unsigned_long (num))
2012 t.bitfield.imm32 = 1;
2013
2014 return t;
47926f60 2015}
252b5132 2016
847f7ad4 2017static offsetT
e3bb37b5 2018offset_in_range (offsetT val, int size)
847f7ad4 2019{
508866be 2020 addressT mask;
ba2adb93 2021
847f7ad4
AM		 2022 switch (size)
2023 {
508866be
L		 2024 case 1: mask = ((addressT) 1 << 8) - 1; break;
2025 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2026 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2027#ifdef BFD64
2028 case 8: mask = ((addressT) 2 << 63) - 1; break;
2029#endif
47926f60 2030 default: abort ();
847f7ad4
AM		 2031 }
2032
9de868bf
L		 2033#ifdef BFD64
2034 /* If BFD64, sign extend val for 32bit address mode. */
2035 if (flag_code != CODE_64BIT
2036 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2037 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2038 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2039#endif
ba2adb93 2040
47926f60 2041 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2042 {
2043 char buf1[40], buf2[40];
2044
2045 sprint_value (buf1, val);
2046 sprint_value (buf2, val & mask);
2047 as_warn (_("%s shortened to %s"), buf1, buf2);
2048 }
2049 return val & mask;
2050}
2051
c32fa91d
L		 2052enum PREFIX_GROUP
2053{
2054 PREFIX_EXIST = 0,
2055 PREFIX_LOCK,
2056 PREFIX_REP,
2057 PREFIX_OTHER
2058};
2059
2060/* Returns
2061 a. PREFIX_EXIST if attempting to add a prefix where one from the
2062 same class already exists.
2063 b. PREFIX_LOCK if lock prefix is added.
2064 c. PREFIX_REP if rep/repne prefix is added.
2065 d. PREFIX_OTHER if other prefix is added.
2066 */
2067
2068static enum PREFIX_GROUP
e3bb37b5 2069add_prefix (unsigned int prefix)
252b5132 2070{
c32fa91d 2071 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2072 unsigned int q;
252b5132 2073
29b0f896
AM		 2074 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2075 && flag_code == CODE_64BIT)
b1905489 2076 {
161a04f6
L		 2077 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2078 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2079 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2080 ret = PREFIX_EXIST;
b1905489
JB		 2081 q = REX_PREFIX;
2082 }
3e73aa7c 2083 else
b1905489
JB		 2084 {
2085 switch (prefix)
2086 {
2087 default:
2088 abort ();
2089
2090 case CS_PREFIX_OPCODE:
2091 case DS_PREFIX_OPCODE:
2092 case ES_PREFIX_OPCODE:
2093 case FS_PREFIX_OPCODE:
2094 case GS_PREFIX_OPCODE:
2095 case SS_PREFIX_OPCODE:
2096 q = SEG_PREFIX;
2097 break;
2098
2099 case REPNE_PREFIX_OPCODE:
2100 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2101 q = REP_PREFIX;
2102 ret = PREFIX_REP;
2103 break;
2104
b1905489 2105 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2106 q = LOCK_PREFIX;
2107 ret = PREFIX_LOCK;
b1905489
JB		 2108 break;
2109
2110 case FWAIT_OPCODE:
2111 q = WAIT_PREFIX;
2112 break;
2113
2114 case ADDR_PREFIX_OPCODE:
2115 q = ADDR_PREFIX;
2116 break;
2117
2118 case DATA_PREFIX_OPCODE:
2119 q = DATA_PREFIX;
2120 break;
2121 }
2122 if (i.prefix[q] != 0)
c32fa91d 2123 ret = PREFIX_EXIST;
b1905489 2124 }
252b5132 2125
b1905489 2126 if (ret)
252b5132 2127 {
b1905489
JB		 2128 if (!i.prefix[q])
2129 ++i.prefixes;
2130 i.prefix[q] |= prefix;
252b5132 2131 }
b1905489
JB		 2132 else
2133 as_bad (_("same type of prefix used twice"));
252b5132 2134
252b5132
RH		 2135 return ret;
2136}
2137
2138static void
78f12dd3 2139update_code_flag (int value, int check)
eecb386c 2140{
78f12dd3
L		 2141 PRINTF_LIKE ((*as_error));
2142
1e9cc1c2 2143 flag_code = (enum flag_code) value;
40fb9820
L		 2144 if (flag_code == CODE_64BIT)
2145 {
2146 cpu_arch_flags.bitfield.cpu64 = 1;
2147 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2148 }
2149 else
2150 {
2151 cpu_arch_flags.bitfield.cpu64 = 0;
2152 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2153 }
2154 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2155 {
78f12dd3
L		 2156 if (check)
2157 as_error = as_fatal;
2158 else
2159 as_error = as_bad;
2160 (*as_error) (_("64bit mode not supported on `%s'."),
2161 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2162 }
40fb9820 2163 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2164 {
78f12dd3
L		 2165 if (check)
2166 as_error = as_fatal;
2167 else
2168 as_error = as_bad;
2169 (*as_error) (_("32bit mode not supported on `%s'."),
2170 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2171 }
eecb386c
AM		 2172 stackop_size = '\0';
2173}
2174
78f12dd3
L		 2175static void
2176set_code_flag (int value)
2177{
2178 update_code_flag (value, 0);
2179}
2180
eecb386c 2181static void
e3bb37b5 2182set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2183{
1e9cc1c2 2184 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2185 if (flag_code != CODE_16BIT)
2186 abort ();
2187 cpu_arch_flags.bitfield.cpu64 = 0;
2188 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2189 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2190}
2191
2192static void
e3bb37b5 2193set_intel_syntax (int syntax_flag)
252b5132
RH		 2194{
2195 /* Find out if register prefixing is specified. */
2196 int ask_naked_reg = 0;
2197
2198 SKIP_WHITESPACE ();
29b0f896 2199 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 2200 {
2201 char *string = input_line_pointer;
2202 int e = get_symbol_end ();
2203
47926f60 2204 if (strcmp (string, "prefix") == 0)
252b5132 2205 ask_naked_reg = 1;
47926f60 2206 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2207 ask_naked_reg = -1;
2208 else
d0b47220 2209 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 2210 *input_line_pointer = e;
2211 }
2212 demand_empty_rest_of_line ();
c3332e24 2213
252b5132
RH		 2214 intel_syntax = syntax_flag;
2215
2216 if (ask_naked_reg == 0)
f86103b7
AM		 2217 allow_naked_reg = (intel_syntax
2218 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2219 else
2220 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2221
ee86248c 2222 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2223
e4a3b5a4 2224 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2225 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2226 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2227}
2228
1efbbeb4
L		 2229static void
2230set_intel_mnemonic (int mnemonic_flag)
2231{
e1d4d893 2232 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2233}
2234
db51cc60
L		 2235static void
2236set_allow_index_reg (int flag)
2237{
2238 allow_index_reg = flag;
2239}
2240
cb19c032 2241static void
7bab8ab5 2242set_check (int what)
cb19c032 2243{
7bab8ab5
JB		 2244 enum check_kind *kind;
2245 const char *str;
2246
2247 if (what)
2248 {
2249 kind = &operand_check;
2250 str = "operand";
2251 }
2252 else
2253 {
2254 kind = &sse_check;
2255 str = "sse";
2256 }
2257
cb19c032
L		 2258 SKIP_WHITESPACE ();
2259
2260 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2261 {
2262 char *string = input_line_pointer;
2263 int e = get_symbol_end ();
2264
2265 if (strcmp (string, "none") == 0)
7bab8ab5 2266 *kind = check_none;
cb19c032 2267 else if (strcmp (string, "warning") == 0)
7bab8ab5 2268 *kind = check_warning;
cb19c032 2269 else if (strcmp (string, "error") == 0)
7bab8ab5 2270 *kind = check_error;
cb19c032 2271 else
7bab8ab5 2272 as_bad (_("bad argument to %s_check directive."), str);
cb19c032
L		 2273 *input_line_pointer = e;
2274 }
2275 else
7bab8ab5 2276 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2277
2278 demand_empty_rest_of_line ();
2279}
2280
8a9036a4
L		 2281static void
2282check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2283 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2284{
2285#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2286 static const char *arch;
2287
2288 /* Intel LIOM is only supported on ELF. */
2289 if (!IS_ELF)
2290 return;
2291
2292 if (!arch)
2293 {
2294 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2295 use default_arch. */
2296 arch = cpu_arch_name;
2297 if (!arch)
2298 arch = default_arch;
2299 }
2300
81486035
L		 2301 /* If we are targeting Intel MCU, we must enable it. */
2302 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2303 || new_flag.bitfield.cpuiamcu)
2304 return;
2305
3632d14b 2306 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2307 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2308 || new_flag.bitfield.cpul1om)
8a9036a4 2309 return;
76ba9986 2310
7a9068fe
L		 2311 /* If we are targeting Intel K1OM, we must enable it. */
2312 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2313 || new_flag.bitfield.cpuk1om)
2314 return;
2315
8a9036a4
L		 2316 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2317#endif
2318}
2319
e413e4e9 2320static void
e3bb37b5 2321set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2322{
47926f60 2323 SKIP_WHITESPACE ();
e413e4e9 2324
29b0f896 2325 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2326 {
2327 char *string = input_line_pointer;
2328 int e = get_symbol_end ();
91d6fa6a 2329 unsigned int j;
40fb9820 2330 i386_cpu_flags flags;
e413e4e9 2331
91d6fa6a 2332 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2333 {
91d6fa6a 2334 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2335 {
91d6fa6a 2336 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2337
5c6af06e
JB		 2338 if (*string != '.')
2339 {
91d6fa6a 2340 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2341 cpu_sub_arch_name = NULL;
91d6fa6a 2342 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2343 if (flag_code == CODE_64BIT)
2344 {
2345 cpu_arch_flags.bitfield.cpu64 = 1;
2346 cpu_arch_flags.bitfield.cpuno64 = 0;
2347 }
2348 else
2349 {
2350 cpu_arch_flags.bitfield.cpu64 = 0;
2351 cpu_arch_flags.bitfield.cpuno64 = 1;
2352 }
91d6fa6a
NC		 2353 cpu_arch_isa = cpu_arch[j].type;
2354 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2355 if (!cpu_arch_tune_set)
2356 {
2357 cpu_arch_tune = cpu_arch_isa;
2358 cpu_arch_tune_flags = cpu_arch_isa_flags;
2359 }
5c6af06e
JB		 2360 break;
2361 }
40fb9820 2362
22109423 2363 if (!cpu_arch[j].negated)
309d3373 2364 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2365 cpu_arch[j].flags);
309d3373
JB		 2366 else
2367 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 2368 cpu_arch[j].flags);
81486035
L		 2369
2370 if (!valid_iamcu_cpu_flags (&flags))
2371 as_fatal (_("`%s' isn't valid for Intel MCU"),
2372 cpu_arch[j].name);
2373 else if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2374 {
6305a203
L		 2375 if (cpu_sub_arch_name)
2376 {
2377 char *name = cpu_sub_arch_name;
2378 cpu_sub_arch_name = concat (name,
91d6fa6a 2379 cpu_arch[j].name,
1bf57e9f 2380 (const char *) NULL);
6305a203
L		 2381 free (name);
2382 }
2383 else
91d6fa6a 2384 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2385 cpu_arch_flags = flags;
a586129e 2386 cpu_arch_isa_flags = flags;
5c6af06e
JB		 2387 }
2388 *input_line_pointer = e;
2389 demand_empty_rest_of_line ();
2390 return;
e413e4e9
AM		 2391 }
2392 }
91d6fa6a 2393 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2394 as_bad (_("no such architecture: `%s'"), string);
2395
2396 *input_line_pointer = e;
2397 }
2398 else
2399 as_bad (_("missing cpu architecture"));
2400
fddf5b5b
AM		 2401 no_cond_jump_promotion = 0;
2402 if (*input_line_pointer == ','
29b0f896 2403 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2404 {
2405 char *string = ++input_line_pointer;
2406 int e = get_symbol_end ();
2407
2408 if (strcmp (string, "nojumps") == 0)
2409 no_cond_jump_promotion = 1;
2410 else if (strcmp (string, "jumps") == 0)
2411 ;
2412 else
2413 as_bad (_("no such architecture modifier: `%s'"), string);
2414
2415 *input_line_pointer = e;
2416 }
2417
e413e4e9
AM		 2418 demand_empty_rest_of_line ();
2419}
2420
8a9036a4
L		 2421enum bfd_architecture
2422i386_arch (void)
2423{
3632d14b 2424 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2425 {
2426 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2427 || flag_code != CODE_64BIT)
2428 as_fatal (_("Intel L1OM is 64bit ELF only"));
2429 return bfd_arch_l1om;
2430 }
7a9068fe
L		 2431 else if (cpu_arch_isa == PROCESSOR_K1OM)
2432 {
2433 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2434 || flag_code != CODE_64BIT)
2435 as_fatal (_("Intel K1OM is 64bit ELF only"));
2436 return bfd_arch_k1om;
2437 }
81486035
L		 2438 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2439 {
2440 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2441 || flag_code == CODE_64BIT)
2442 as_fatal (_("Intel MCU is 32bit ELF only"));
2443 return bfd_arch_iamcu;
2444 }
8a9036a4
L		 2445 else
2446 return bfd_arch_i386;
2447}
2448
b9d79e03 2449unsigned long
7016a5d5 2450i386_mach (void)
b9d79e03 2451{
351f65ca 2452 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2453 {
3632d14b 2454 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2455 {
351f65ca
L		 2456 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2457 || default_arch[6] != '\0')
8a9036a4
L		 2458 as_fatal (_("Intel L1OM is 64bit ELF only"));
2459 return bfd_mach_l1om;
2460 }
7a9068fe
L		 2461 else if (cpu_arch_isa == PROCESSOR_K1OM)
2462 {
2463 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2464 || default_arch[6] != '\0')
2465 as_fatal (_("Intel K1OM is 64bit ELF only"));
2466 return bfd_mach_k1om;
2467 }
351f65ca 2468 else if (default_arch[6] == '\0')
8a9036a4 2469 return bfd_mach_x86_64;
351f65ca
L		 2470 else
2471 return bfd_mach_x64_32;
8a9036a4 2472 }
5197d474
L		 2473 else if (!strcmp (default_arch, "i386")
2474 || !strcmp (default_arch, "iamcu"))
81486035
L		 2475 {
2476 if (cpu_arch_isa == PROCESSOR_IAMCU)
2477 {
2478 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2479 as_fatal (_("Intel MCU is 32bit ELF only"));
2480 return bfd_mach_i386_iamcu;
2481 }
2482 else
2483 return bfd_mach_i386_i386;
2484 }
b9d79e03 2485 else
2b5d6a91 2486 as_fatal (_("unknown architecture"));
b9d79e03 2487}
b9d79e03 2488\f
252b5132 2489void
7016a5d5 2490md_begin (void)
252b5132
RH		 2491{
2492 const char *hash_err;
2493
47926f60 2494 /* Initialize op_hash hash table. */
252b5132
RH		 2495 op_hash = hash_new ();
2496
2497 {
d3ce72d0 2498 const insn_template *optab;
29b0f896 2499 templates *core_optab;
252b5132 2500
47926f60
KH		 2501 /* Setup for loop. */
2502 optab = i386_optab;
252b5132
RH		 2503 core_optab = (templates *) xmalloc (sizeof (templates));
2504 core_optab->start = optab;
2505
2506 while (1)
2507 {
2508 ++optab;
2509 if (optab->name == NULL
2510 || strcmp (optab->name, (optab - 1)->name) != 0)
2511 {
2512 /* different name --> ship out current template list;
47926f60 2513 add to hash table; & begin anew. */
252b5132
RH		 2514 core_optab->end = optab;
2515 hash_err = hash_insert (op_hash,
2516 (optab - 1)->name,
5a49b8ac 2517 (void *) core_optab);
252b5132
RH		 2518 if (hash_err)
2519 {
b37df7c4 2520 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2521 (optab - 1)->name,
2522 hash_err);
2523 }
2524 if (optab->name == NULL)
2525 break;
2526 core_optab = (templates *) xmalloc (sizeof (templates));
2527 core_optab->start = optab;
2528 }
2529 }
2530 }
2531
47926f60 2532 /* Initialize reg_hash hash table. */
252b5132
RH		 2533 reg_hash = hash_new ();
2534 {
29b0f896 2535 const reg_entry *regtab;
c3fe08fa 2536 unsigned int regtab_size = i386_regtab_size;
252b5132 2537
c3fe08fa 2538 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2539 {
5a49b8ac 2540 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2541 if (hash_err)
b37df7c4 2542 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2543 regtab->reg_name,
2544 hash_err);
252b5132
RH		 2545 }
2546 }
2547
47926f60 2548 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2549 {
29b0f896
AM		 2550 int c;
2551 char *p;
252b5132
RH		 2552
2553 for (c = 0; c < 256; c++)
2554 {
3882b010 2555 if (ISDIGIT (c))
252b5132
RH		 2556 {
2557 digit_chars[c] = c;
2558 mnemonic_chars[c] = c;
2559 register_chars[c] = c;
2560 operand_chars[c] = c;
2561 }
3882b010 2562 else if (ISLOWER (c))
252b5132
RH		 2563 {
2564 mnemonic_chars[c] = c;
2565 register_chars[c] = c;
2566 operand_chars[c] = c;
2567 }
3882b010 2568 else if (ISUPPER (c))
252b5132 2569 {
3882b010 2570 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2571 register_chars[c] = mnemonic_chars[c];
2572 operand_chars[c] = c;
2573 }
43234a1e
L		 2574 else if (c == '{' || c == '}')
2575 operand_chars[c] = c;
252b5132 2576
3882b010 2577 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2578 identifier_chars[c] = c;
2579 else if (c >= 128)
2580 {
2581 identifier_chars[c] = c;
2582 operand_chars[c] = c;
2583 }
2584 }
2585
2586#ifdef LEX_AT
2587 identifier_chars['@'] = '@';
32137342
NC		 2588#endif
2589#ifdef LEX_QM
2590 identifier_chars['?'] = '?';
2591 operand_chars['?'] = '?';
252b5132 2592#endif
252b5132 2593 digit_chars['-'] = '-';
c0f3af97 2594 mnemonic_chars['_'] = '_';
791fe849 2595 mnemonic_chars['-'] = '-';
0003779b 2596 mnemonic_chars['.'] = '.';
252b5132
RH		 2597 identifier_chars['_'] = '_';
2598 identifier_chars['.'] = '.';
2599
2600 for (p = operand_special_chars; *p != '\0'; p++)
2601 operand_chars[(unsigned char) *p] = *p;
2602 }
2603
a4447b93
RH		 2604 if (flag_code == CODE_64BIT)
2605 {
ca19b261
KT		 2606#if defined (OBJ_COFF) && defined (TE_PE)
2607 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2608 ? 32 : 16);
2609#else
a4447b93 2610 x86_dwarf2_return_column = 16;
ca19b261 2611#endif
61ff971f 2612 x86_cie_data_alignment = -8;
a4447b93
RH		 2613 }
2614 else
2615 {
2616 x86_dwarf2_return_column = 8;
2617 x86_cie_data_alignment = -4;
2618 }
252b5132
RH		 2619}
2620
2621void
e3bb37b5 2622i386_print_statistics (FILE *file)
252b5132
RH		 2623{
2624 hash_print_statistics (file, "i386 opcode", op_hash);
2625 hash_print_statistics (file, "i386 register", reg_hash);
2626}
2627\f
252b5132
RH		 2628#ifdef DEBUG386
2629
ce8a8b2f 2630/* Debugging routines for md_assemble. */
d3ce72d0 2631static void pte (insn_template *);
40fb9820 2632static void pt (i386_operand_type);
e3bb37b5
L		 2633static void pe (expressionS *);
2634static void ps (symbolS *);
252b5132
RH		 2635
2636static void
e3bb37b5 2637pi (char *line, i386_insn *x)
252b5132 2638{
09137c09 2639 unsigned int j;
252b5132
RH		 2640
2641 fprintf (stdout, "%s: template ", line);
2642 pte (&x->tm);
09f131f2
JH		 2643 fprintf (stdout, " address: base %s index %s scale %x\n",
2644 x->base_reg ? x->base_reg->reg_name : "none",
2645 x->index_reg ? x->index_reg->reg_name : "none",
2646 x->log2_scale_factor);
2647 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2648 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2649 fprintf (stdout, " sib: base %x index %x scale %x\n",
2650 x->sib.base, x->sib.index, x->sib.scale);
2651 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2652 (x->rex & REX_W) != 0,
2653 (x->rex & REX_R) != 0,
2654 (x->rex & REX_X) != 0,
2655 (x->rex & REX_B) != 0);
09137c09 2656 for (j = 0; j < x->operands; j++)
252b5132 2657 {
09137c09
SP		 2658 fprintf (stdout, " #%d: ", j + 1);
2659 pt (x->types[j]);
252b5132 2660 fprintf (stdout, "\n");
09137c09
SP		 2661 if (x->types[j].bitfield.reg8
2662 || x->types[j].bitfield.reg16
2663 || x->types[j].bitfield.reg32
2664 || x->types[j].bitfield.reg64
2665 || x->types[j].bitfield.regmmx
2666 || x->types[j].bitfield.regxmm
2667 || x->types[j].bitfield.regymm
43234a1e 2668 || x->types[j].bitfield.regzmm
09137c09
SP		 2669 || x->types[j].bitfield.sreg2
2670 || x->types[j].bitfield.sreg3
2671 || x->types[j].bitfield.control
2672 || x->types[j].bitfield.debug
2673 || x->types[j].bitfield.test)
2674 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2675 if (operand_type_check (x->types[j], imm))
2676 pe (x->op[j].imms);
2677 if (operand_type_check (x->types[j], disp))
2678 pe (x->op[j].disps);
252b5132
RH		 2679 }
2680}
2681
2682static void
d3ce72d0 2683pte (insn_template *t)
252b5132 2684{
09137c09 2685 unsigned int j;
252b5132 2686 fprintf (stdout, " %d operands ", t->operands);
47926f60 2687 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2688 if (t->extension_opcode != None)
2689 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2690 if (t->opcode_modifier.d)
252b5132 2691 fprintf (stdout, "D");
40fb9820 2692 if (t->opcode_modifier.w)
252b5132
RH		 2693 fprintf (stdout, "W");
2694 fprintf (stdout, "\n");
09137c09 2695 for (j = 0; j < t->operands; j++)
252b5132 2696 {
09137c09
SP		 2697 fprintf (stdout, " #%d type ", j + 1);
2698 pt (t->operand_types[j]);
252b5132
RH		 2699 fprintf (stdout, "\n");
2700 }
2701}
2702
2703static void
e3bb37b5 2704pe (expressionS *e)
252b5132 2705{
24eab124 2706 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2707 fprintf (stdout, " add_number %ld (%lx)\n",
2708 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2709 if (e->X_add_symbol)
2710 {
2711 fprintf (stdout, " add_symbol ");
2712 ps (e->X_add_symbol);
2713 fprintf (stdout, "\n");
2714 }
2715 if (e->X_op_symbol)
2716 {
2717 fprintf (stdout, " op_symbol ");
2718 ps (e->X_op_symbol);
2719 fprintf (stdout, "\n");
2720 }
2721}
2722
2723static void
e3bb37b5 2724ps (symbolS *s)
252b5132
RH		 2725{
2726 fprintf (stdout, "%s type %s%s",
2727 S_GET_NAME (s),
2728 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2729 segment_name (S_GET_SEGMENT (s)));
2730}
2731
7b81dfbb 2732static struct type_name
252b5132 2733 {
40fb9820
L		 2734 i386_operand_type mask;
2735 const char *name;
252b5132 2736 }
7b81dfbb 2737const type_names[] =
252b5132 2738{
40fb9820
L		 2739 { OPERAND_TYPE_REG8, "r8" },
2740 { OPERAND_TYPE_REG16, "r16" },
2741 { OPERAND_TYPE_REG32, "r32" },
2742 { OPERAND_TYPE_REG64, "r64" },
2743 { OPERAND_TYPE_IMM8, "i8" },
2744 { OPERAND_TYPE_IMM8, "i8s" },
2745 { OPERAND_TYPE_IMM16, "i16" },
2746 { OPERAND_TYPE_IMM32, "i32" },
2747 { OPERAND_TYPE_IMM32S, "i32s" },
2748 { OPERAND_TYPE_IMM64, "i64" },
2749 { OPERAND_TYPE_IMM1, "i1" },
2750 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2751 { OPERAND_TYPE_DISP8, "d8" },
2752 { OPERAND_TYPE_DISP16, "d16" },
2753 { OPERAND_TYPE_DISP32, "d32" },
2754 { OPERAND_TYPE_DISP32S, "d32s" },
2755 { OPERAND_TYPE_DISP64, "d64" },
43234a1e 2756 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
40fb9820
L		 2757 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2758 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2759 { OPERAND_TYPE_CONTROL, "control reg" },
2760 { OPERAND_TYPE_TEST, "test reg" },
2761 { OPERAND_TYPE_DEBUG, "debug reg" },
2762 { OPERAND_TYPE_FLOATREG, "FReg" },
2763 { OPERAND_TYPE_FLOATACC, "FAcc" },
2764 { OPERAND_TYPE_SREG2, "SReg2" },
2765 { OPERAND_TYPE_SREG3, "SReg3" },
2766 { OPERAND_TYPE_ACC, "Acc" },
2767 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2768 { OPERAND_TYPE_REGMMX, "rMMX" },
2769 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2770 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2771 { OPERAND_TYPE_REGZMM, "rZMM" },
2772 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2773 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2774};
2775
2776static void
40fb9820 2777pt (i386_operand_type t)
252b5132 2778{
40fb9820 2779 unsigned int j;
c6fb90c8 2780 i386_operand_type a;
252b5132 2781
40fb9820 2782 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2783 {
2784 a = operand_type_and (t, type_names[j].mask);
0349dc08 2785 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2786 fprintf (stdout, "%s, ", type_names[j].name);
2787 }
252b5132
RH		 2788 fflush (stdout);
2789}
2790
2791#endif /* DEBUG386 */
2792\f
252b5132 2793static bfd_reloc_code_real_type
3956db08 2794reloc (unsigned int size,
64e74474
AM		 2795 int pcrel,
2796 int sign,
2797 bfd_reloc_code_real_type other)
252b5132 2798{
47926f60 2799 if (other != NO_RELOC)
3956db08 2800 {
91d6fa6a 2801 reloc_howto_type *rel;
3956db08
JB		 2802
2803 if (size == 8)
2804 switch (other)
2805 {
64e74474
AM		 2806 case BFD_RELOC_X86_64_GOT32:
2807 return BFD_RELOC_X86_64_GOT64;
2808 break;
553d1284
L		 2809 case BFD_RELOC_X86_64_GOTPLT64:
2810 return BFD_RELOC_X86_64_GOTPLT64;
2811 break;
64e74474
AM		 2812 case BFD_RELOC_X86_64_PLTOFF64:
2813 return BFD_RELOC_X86_64_PLTOFF64;
2814 break;
2815 case BFD_RELOC_X86_64_GOTPC32:
2816 other = BFD_RELOC_X86_64_GOTPC64;
2817 break;
2818 case BFD_RELOC_X86_64_GOTPCREL:
2819 other = BFD_RELOC_X86_64_GOTPCREL64;
2820 break;
2821 case BFD_RELOC_X86_64_TPOFF32:
2822 other = BFD_RELOC_X86_64_TPOFF64;
2823 break;
2824 case BFD_RELOC_X86_64_DTPOFF32:
2825 other = BFD_RELOC_X86_64_DTPOFF64;
2826 break;
2827 default:
2828 break;
3956db08 2829 }
e05278af 2830
8ce3d284 2831#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2832 if (other == BFD_RELOC_SIZE32)
2833 {
2834 if (size == 8)
1ab668bf 2835 other = BFD_RELOC_SIZE64;
8fd4256d 2836 if (pcrel)
1ab668bf
AM		 2837 {
2838 as_bad (_("there are no pc-relative size relocations"));
2839 return NO_RELOC;
2840 }
8fd4256d 2841 }
8ce3d284 2842#endif
8fd4256d 2843
e05278af 2844 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2845 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2846 sign = -1;
2847
91d6fa6a
NC		 2848 rel = bfd_reloc_type_lookup (stdoutput, other);
2849 if (!rel)
3956db08 2850 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2851 else if (size != bfd_get_reloc_size (rel))
3956db08 2852 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2853 bfd_get_reloc_size (rel),
3956db08 2854 size);
91d6fa6a 2855 else if (pcrel && !rel->pc_relative)
3956db08 2856 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2857 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2858 && !sign)
91d6fa6a 2859 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2860 && sign > 0))
3956db08
JB		 2861 as_bad (_("relocated field and relocation type differ in signedness"));
2862 else
2863 return other;
2864 return NO_RELOC;
2865 }
252b5132
RH		 2866
2867 if (pcrel)
2868 {
3e73aa7c 2869 if (!sign)
3956db08 2870 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2871 switch (size)
2872 {
2873 case 1: return BFD_RELOC_8_PCREL;
2874 case 2: return BFD_RELOC_16_PCREL;
d258b828 2875 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2876 case 8: return BFD_RELOC_64_PCREL;
252b5132 2877 }
3956db08 2878 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2879 }
2880 else
2881 {
3956db08 2882 if (sign > 0)
e5cb08ac 2883 switch (size)
3e73aa7c
JH		 2884 {
2885 case 4: return BFD_RELOC_X86_64_32S;
2886 }
2887 else
2888 switch (size)
2889 {
2890 case 1: return BFD_RELOC_8;
2891 case 2: return BFD_RELOC_16;
2892 case 4: return BFD_RELOC_32;
2893 case 8: return BFD_RELOC_64;
2894 }
3956db08
JB		 2895 as_bad (_("cannot do %s %u byte relocation"),
2896 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2897 }
2898
0cc9e1d3 2899 return NO_RELOC;
252b5132
RH		 2900}
2901
47926f60
KH		 2902/* Here we decide which fixups can be adjusted to make them relative to
2903 the beginning of the section instead of the symbol. Basically we need
2904 to make sure that the dynamic relocations are done correctly, so in
2905 some cases we force the original symbol to be used. */
2906
252b5132 2907int
e3bb37b5 2908tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2909{
6d249963 2910#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2911 if (!IS_ELF)
31312f95
AM		 2912 return 1;
2913
a161fe53
AM		 2914 /* Don't adjust pc-relative references to merge sections in 64-bit
2915 mode. */
2916 if (use_rela_relocations
2917 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2918 && fixP->fx_pcrel)
252b5132 2919 return 0;
31312f95 2920
8d01d9a9
AJ		 2921 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2922 and changed later by validate_fix. */
2923 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2924 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2925 return 0;
2926
8fd4256d
L		 2927 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2928 for size relocations. */
2929 if (fixP->fx_r_type == BFD_RELOC_SIZE32
2930 || fixP->fx_r_type == BFD_RELOC_SIZE64
2931 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 2932 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2933 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2934 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2935 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2936 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2937 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2938 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2939 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2940 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2941 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2942 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2943 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2944 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2945 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2946 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2947 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2948 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2949 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2950 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2951 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2952 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2953 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2954 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2955 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2956 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2957 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2958 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2959 return 0;
31312f95 2960#endif
252b5132
RH		 2961 return 1;
2962}
252b5132 2963
b4cac588 2964static int
e3bb37b5 2965intel_float_operand (const char *mnemonic)
252b5132 2966{
9306ca4a
JB		 2967 /* Note that the value returned is meaningful only for opcodes with (memory)
2968 operands, hence the code here is free to improperly handle opcodes that
2969 have no operands (for better performance and smaller code). */
2970
2971 if (mnemonic[0] != 'f')
2972 return 0; /* non-math */
2973
2974 switch (mnemonic[1])
2975 {
2976 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2977 the fs segment override prefix not currently handled because no
2978 call path can make opcodes without operands get here */
2979 case 'i':
2980 return 2 /* integer op */;
2981 case 'l':
2982 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2983 return 3; /* fldcw/fldenv */
2984 break;
2985 case 'n':
2986 if (mnemonic[2] != 'o' /* fnop */)
2987 return 3; /* non-waiting control op */
2988 break;
2989 case 'r':
2990 if (mnemonic[2] == 's')
2991 return 3; /* frstor/frstpm */
2992 break;
2993 case 's':
2994 if (mnemonic[2] == 'a')
2995 return 3; /* fsave */
2996 if (mnemonic[2] == 't')
2997 {
2998 switch (mnemonic[3])
2999 {
3000 case 'c': /* fstcw */
3001 case 'd': /* fstdw */
3002 case 'e': /* fstenv */
3003 case 's': /* fsts[gw] */
3004 return 3;
3005 }
3006 }
3007 break;
3008 case 'x':
3009 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3010 return 0; /* fxsave/fxrstor are not really math ops */
3011 break;
3012 }
252b5132 3013
9306ca4a 3014 return 1;
252b5132
RH		 3015}
3016
c0f3af97
L		 3017/* Build the VEX prefix. */
3018
3019static void
d3ce72d0 3020build_vex_prefix (const insn_template *t)
c0f3af97
L		 3021{
3022 unsigned int register_specifier;
3023 unsigned int implied_prefix;
3024 unsigned int vector_length;
3025
3026 /* Check register specifier. */
3027 if (i.vex.register_specifier)
43234a1e
L		 3028 {
3029 register_specifier =
3030 ~register_number (i.vex.register_specifier) & 0xf;
3031 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3032 }
c0f3af97
L		 3033 else
3034 register_specifier = 0xf;
3035
fa99fab2
L		 3036 /* Use 2-byte VEX prefix by swappping destination and source
3037 operand. */
3038 if (!i.swap_operand
3039 && i.operands == i.reg_operands
7f399153 3040 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 3041 && i.tm.opcode_modifier.s
3042 && i.rex == REX_B)
3043 {
3044 unsigned int xchg = i.operands - 1;
3045 union i386_op temp_op;
3046 i386_operand_type temp_type;
3047
3048 temp_type = i.types[xchg];
3049 i.types[xchg] = i.types[0];
3050 i.types[0] = temp_type;
3051 temp_op = i.op[xchg];
3052 i.op[xchg] = i.op[0];
3053 i.op[0] = temp_op;
3054
9c2799c2 3055 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3056
3057 i.rex = REX_R;
3058 xchg = i.rm.regmem;
3059 i.rm.regmem = i.rm.reg;
3060 i.rm.reg = xchg;
3061
3062 /* Use the next insn. */
3063 i.tm = t[1];
3064 }
3065
539f890d
L		 3066 if (i.tm.opcode_modifier.vex == VEXScalar)
3067 vector_length = avxscalar;
3068 else
3069 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3070
3071 switch ((i.tm.base_opcode >> 8) & 0xff)
3072 {
3073 case 0:
3074 implied_prefix = 0;
3075 break;
3076 case DATA_PREFIX_OPCODE:
3077 implied_prefix = 1;
3078 break;
3079 case REPE_PREFIX_OPCODE:
3080 implied_prefix = 2;
3081 break;
3082 case REPNE_PREFIX_OPCODE:
3083 implied_prefix = 3;
3084 break;
3085 default:
3086 abort ();
3087 }
3088
3089 /* Use 2-byte VEX prefix if possible. */
7f399153 3090 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3091 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3092 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3093 {
3094 /* 2-byte VEX prefix. */
3095 unsigned int r;
3096
3097 i.vex.length = 2;
3098 i.vex.bytes[0] = 0xc5;
3099
3100 /* Check the REX.R bit. */
3101 r = (i.rex & REX_R) ? 0 : 1;
3102 i.vex.bytes[1] = (r << 7
3103 | register_specifier << 3
3104 | vector_length << 2
3105 | implied_prefix);
3106 }
3107 else
3108 {
3109 /* 3-byte VEX prefix. */
3110 unsigned int m, w;
3111
f88c9eb0 3112 i.vex.length = 3;
f88c9eb0 3113
7f399153 3114 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3115 {
7f399153
L		 3116 case VEX0F:
3117 m = 0x1;
80de6e00 3118 i.vex.bytes[0] = 0xc4;
7f399153
L		 3119 break;
3120 case VEX0F38:
3121 m = 0x2;
80de6e00 3122 i.vex.bytes[0] = 0xc4;
7f399153
L		 3123 break;
3124 case VEX0F3A:
3125 m = 0x3;
80de6e00 3126 i.vex.bytes[0] = 0xc4;
7f399153
L		 3127 break;
3128 case XOP08:
5dd85c99
SP		 3129 m = 0x8;
3130 i.vex.bytes[0] = 0x8f;
7f399153
L		 3131 break;
3132 case XOP09:
f88c9eb0
SP		 3133 m = 0x9;
3134 i.vex.bytes[0] = 0x8f;
7f399153
L		 3135 break;
3136 case XOP0A:
f88c9eb0
SP		 3137 m = 0xa;
3138 i.vex.bytes[0] = 0x8f;
7f399153
L		 3139 break;
3140 default:
3141 abort ();
f88c9eb0 3142 }
c0f3af97 3143
c0f3af97
L		 3144 /* The high 3 bits of the second VEX byte are 1's compliment
3145 of RXB bits from REX. */
3146 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3147
3148 /* Check the REX.W bit. */
3149 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3150 if (i.tm.opcode_modifier.vexw == VEXW1)
3151 w = 1;
c0f3af97
L		 3152
3153 i.vex.bytes[2] = (w << 7
3154 | register_specifier << 3
3155 | vector_length << 2
3156 | implied_prefix);
3157 }
3158}
3159
43234a1e
L		 3160/* Build the EVEX prefix. */
3161
3162static void
3163build_evex_prefix (void)
3164{
3165 unsigned int register_specifier;
3166 unsigned int implied_prefix;
3167 unsigned int m, w;
3168 rex_byte vrex_used = 0;
3169
3170 /* Check register specifier. */
3171 if (i.vex.register_specifier)
3172 {
3173 gas_assert ((i.vrex & REX_X) == 0);
3174
3175 register_specifier = i.vex.register_specifier->reg_num;
3176 if ((i.vex.register_specifier->reg_flags & RegRex))
3177 register_specifier += 8;
3178 /* The upper 16 registers are encoded in the fourth byte of the
3179 EVEX prefix. */
3180 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3181 i.vex.bytes[3] = 0x8;
3182 register_specifier = ~register_specifier & 0xf;
3183 }
3184 else
3185 {
3186 register_specifier = 0xf;
3187
3188 /* Encode upper 16 vector index register in the fourth byte of
3189 the EVEX prefix. */
3190 if (!(i.vrex & REX_X))
3191 i.vex.bytes[3] = 0x8;
3192 else
3193 vrex_used |= REX_X;
3194 }
3195
3196 switch ((i.tm.base_opcode >> 8) & 0xff)
3197 {
3198 case 0:
3199 implied_prefix = 0;
3200 break;
3201 case DATA_PREFIX_OPCODE:
3202 implied_prefix = 1;
3203 break;
3204 case REPE_PREFIX_OPCODE:
3205 implied_prefix = 2;
3206 break;
3207 case REPNE_PREFIX_OPCODE:
3208 implied_prefix = 3;
3209 break;
3210 default:
3211 abort ();
3212 }
3213
3214 /* 4 byte EVEX prefix. */
3215 i.vex.length = 4;
3216 i.vex.bytes[0] = 0x62;
3217
3218 /* mmmm bits. */
3219 switch (i.tm.opcode_modifier.vexopcode)
3220 {
3221 case VEX0F:
3222 m = 1;
3223 break;
3224 case VEX0F38:
3225 m = 2;
3226 break;
3227 case VEX0F3A:
3228 m = 3;
3229 break;
3230 default:
3231 abort ();
3232 break;
3233 }
3234
3235 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3236 bits from REX. */
3237 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3238
3239 /* The fifth bit of the second EVEX byte is 1's compliment of the
3240 REX_R bit in VREX. */
3241 if (!(i.vrex & REX_R))
3242 i.vex.bytes[1] |= 0x10;
3243 else
3244 vrex_used |= REX_R;
3245
3246 if ((i.reg_operands + i.imm_operands) == i.operands)
3247 {
3248 /* When all operands are registers, the REX_X bit in REX is not
3249 used. We reuse it to encode the upper 16 registers, which is
3250 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3251 as 1's compliment. */
3252 if ((i.vrex & REX_B))
3253 {
3254 vrex_used |= REX_B;
3255 i.vex.bytes[1] &= ~0x40;
3256 }
3257 }
3258
3259 /* EVEX instructions shouldn't need the REX prefix. */
3260 i.vrex &= ~vrex_used;
3261 gas_assert (i.vrex == 0);
3262
3263 /* Check the REX.W bit. */
3264 w = (i.rex & REX_W) ? 1 : 0;
3265 if (i.tm.opcode_modifier.vexw)
3266 {
3267 if (i.tm.opcode_modifier.vexw == VEXW1)
3268 w = 1;
3269 }
3270 /* If w is not set it means we are dealing with WIG instruction. */
3271 else if (!w)
3272 {
3273 if (evexwig == evexw1)
3274 w = 1;
3275 }
3276
3277 /* Encode the U bit. */
3278 implied_prefix |= 0x4;
3279
3280 /* The third byte of the EVEX prefix. */
3281 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3282
3283 /* The fourth byte of the EVEX prefix. */
3284 /* The zeroing-masking bit. */
3285 if (i.mask && i.mask->zeroing)
3286 i.vex.bytes[3] |= 0x80;
3287
3288 /* Don't always set the broadcast bit if there is no RC. */
3289 if (!i.rounding)
3290 {
3291 /* Encode the vector length. */
3292 unsigned int vec_length;
3293
3294 switch (i.tm.opcode_modifier.evex)
3295 {
3296 case EVEXLIG: /* LL' is ignored */
3297 vec_length = evexlig << 5;
3298 break;
3299 case EVEX128:
3300 vec_length = 0 << 5;
3301 break;
3302 case EVEX256:
3303 vec_length = 1 << 5;
3304 break;
3305 case EVEX512:
3306 vec_length = 2 << 5;
3307 break;
3308 default:
3309 abort ();
3310 break;
3311 }
3312 i.vex.bytes[3] |= vec_length;
3313 /* Encode the broadcast bit. */
3314 if (i.broadcast)
3315 i.vex.bytes[3] |= 0x10;
3316 }
3317 else
3318 {
3319 if (i.rounding->type != saeonly)
3320 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3321 else
d3d3c6db 3322 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3323 }
3324
3325 if (i.mask && i.mask->mask)
3326 i.vex.bytes[3] |= i.mask->mask->reg_num;
3327}
3328
65da13b5
L		 3329static void
3330process_immext (void)
3331{
3332 expressionS *exp;
3333
4c692bc7
JB		 3334 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3335 && i.operands > 0)
65da13b5 3336 {
4c692bc7
JB		 3337 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3338 with an opcode suffix which is coded in the same place as an
3339 8-bit immediate field would be.
3340 Here we check those operands and remove them afterwards. */
65da13b5
L		 3341 unsigned int x;
3342
3343 for (x = 0; x < i.operands; x++)
4c692bc7 3344 if (register_number (i.op[x].regs) != x)
65da13b5 3345 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3346 register_prefix, i.op[x].regs->reg_name, x + 1,
3347 i.tm.name);
3348
3349 i.operands = 0;
65da13b5
L		 3350 }
3351
9916071f
AP		 3352 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3353 {
3354 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3355 suffix which is coded in the same place as an 8-bit immediate
3356 field would be.
3357 Here we check those operands and remove them afterwards. */
3358 unsigned int x;
3359
3360 if (i.operands != 3)
3361 abort();
3362
3363 for (x = 0; x < 2; x++)
3364 if (register_number (i.op[x].regs) != x)
3365 goto bad_register_operand;
3366
3367 /* Check for third operand for mwaitx/monitorx insn. */
3368 if (register_number (i.op[x].regs)
3369 != (x + (i.tm.extension_opcode == 0xfb)))
3370 {
3371bad_register_operand:
3372 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3373 register_prefix, i.op[x].regs->reg_name, x+1,
3374 i.tm.name);
3375 }
3376
3377 i.operands = 0;
3378 }
3379
c0f3af97 3380 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3381 which is coded in the same place as an 8-bit immediate field
3382 would be. Here we fake an 8-bit immediate operand from the
3383 opcode suffix stored in tm.extension_opcode.
3384
c1e679ec 3385 AVX instructions also use this encoding, for some of
c0f3af97 3386 3 argument instructions. */
65da13b5 3387
43234a1e 3388 gas_assert (i.imm_operands <= 1
7ab9ffdd 3389 && (i.operands <= 2
43234a1e
L		 3390 || ((i.tm.opcode_modifier.vex
3391 || i.tm.opcode_modifier.evex)
7ab9ffdd 3392 && i.operands <= 4)));
65da13b5
L		 3393
3394 exp = &im_expressions[i.imm_operands++];
3395 i.op[i.operands].imms = exp;
3396 i.types[i.operands] = imm8;
3397 i.operands++;
3398 exp->X_op = O_constant;
3399 exp->X_add_number = i.tm.extension_opcode;
3400 i.tm.extension_opcode = None;
3401}
3402
42164a71
L		 3403
3404static int
3405check_hle (void)
3406{
3407 switch (i.tm.opcode_modifier.hleprefixok)
3408 {
3409 default:
3410 abort ();
82c2def5 3411 case HLEPrefixNone:
165de32a
L		 3412 as_bad (_("invalid instruction `%s' after `%s'"),
3413 i.tm.name, i.hle_prefix);
42164a71 3414 return 0;
82c2def5 3415 case HLEPrefixLock:
42164a71
L		 3416 if (i.prefix[LOCK_PREFIX])
3417 return 1;
165de32a 3418 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3419 return 0;
82c2def5 3420 case HLEPrefixAny:
42164a71 3421 return 1;
82c2def5 3422 case HLEPrefixRelease:
42164a71
L		 3423 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3424 {
3425 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3426 i.tm.name);
3427 return 0;
3428 }
3429 if (i.mem_operands == 0
3430 || !operand_type_check (i.types[i.operands - 1], anymem))
3431 {
3432 as_bad (_("memory destination needed for instruction `%s'"
3433 " after `xrelease'"), i.tm.name);
3434 return 0;
3435 }
3436 return 1;
3437 }
3438}
3439
252b5132
RH		 3440/* This is the guts of the machine-dependent assembler. LINE points to a
3441 machine dependent instruction. This function is supposed to emit
3442 the frags/bytes it assembles to. */
3443
3444void
65da13b5 3445md_assemble (char *line)
252b5132 3446{
40fb9820 3447 unsigned int j;
252b5132 3448 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 3449 const insn_template *t;
252b5132 3450
47926f60 3451 /* Initialize globals. */
252b5132
RH		 3452 memset (&i, '\0', sizeof (i));
3453 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3454 i.reloc[j] = NO_RELOC;
252b5132
RH		 3455 memset (disp_expressions, '\0', sizeof (disp_expressions));
3456 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3457 save_stack_p = save_stack;
252b5132
RH		 3458
3459 /* First parse an instruction mnemonic & call i386_operand for the operands.
3460 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3461 start of a (possibly prefixed) mnemonic. */
252b5132 3462
29b0f896
AM		 3463 line = parse_insn (line, mnemonic);
3464 if (line == NULL)
3465 return;
252b5132 3466
29b0f896 3467 line = parse_operands (line, mnemonic);
ee86248c 3468 this_operand = -1;
29b0f896
AM		 3469 if (line == NULL)
3470 return;
252b5132 3471
29b0f896
AM		 3472 /* Now we've parsed the mnemonic into a set of templates, and have the
3473 operands at hand. */
3474
3475 /* All intel opcodes have reversed operands except for "bound" and
3476 "enter". We also don't reverse intersegment "jmp" and "call"
3477 instructions with 2 immediate operands so that the immediate segment
050dfa73 3478 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3479 if (intel_syntax
3480 && i.operands > 1
29b0f896 3481 && (strcmp (mnemonic, "bound") != 0)
30123838 3482 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3483 && !(operand_type_check (i.types[0], imm)
3484 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3485 swap_operands ();
3486
ec56d5c0
JB		 3487 /* The order of the immediates should be reversed
3488 for 2 immediates extrq and insertq instructions */
3489 if (i.imm_operands == 2
3490 && (strcmp (mnemonic, "extrq") == 0
3491 || strcmp (mnemonic, "insertq") == 0))
3492 swap_2_operands (0, 1);
3493
29b0f896
AM		 3494 if (i.imm_operands)
3495 optimize_imm ();
3496
b300c311
L		 3497 /* Don't optimize displacement for movabs since it only takes 64bit
3498 displacement. */
3499 if (i.disp_operands
a501d77e 3500 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3501 && (flag_code != CODE_64BIT
3502 || strcmp (mnemonic, "movabs") != 0))
3503 optimize_disp ();
29b0f896
AM		 3504
3505 /* Next, we find a template that matches the given insn,
3506 making sure the overlap of the given operands types is consistent
3507 with the template operand types. */
252b5132 3508
fa99fab2 3509 if (!(t = match_template ()))
29b0f896 3510 return;
252b5132 3511
7bab8ab5 3512 if (sse_check != check_none
81f8a913 3513 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3514 && (i.tm.cpu_flags.bitfield.cpusse
3515 || i.tm.cpu_flags.bitfield.cpusse2
3516 || i.tm.cpu_flags.bitfield.cpusse3
3517 || i.tm.cpu_flags.bitfield.cpussse3
3518 || i.tm.cpu_flags.bitfield.cpusse4_1
3519 || i.tm.cpu_flags.bitfield.cpusse4_2))
3520 {
7bab8ab5 3521 (sse_check == check_warning
daf50ae7
L		 3522 ? as_warn
3523 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3524 }
3525
321fd21e
L		 3526 /* Zap movzx and movsx suffix. The suffix has been set from
3527 "word ptr" or "byte ptr" on the source operand in Intel syntax
3528 or extracted from mnemonic in AT&T syntax. But we'll use
3529 the destination register to choose the suffix for encoding. */
3530 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3531 {
321fd21e
L		 3532 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3533 there is no suffix, the default will be byte extension. */
3534 if (i.reg_operands != 2
3535 && !i.suffix
7ab9ffdd 3536 && intel_syntax)
321fd21e
L		 3537 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3538
3539 i.suffix = 0;
cd61ebfe 3540 }
24eab124 3541
40fb9820 3542 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3543 if (!add_prefix (FWAIT_OPCODE))
3544 return;
252b5132 3545
d5de92cf
L		 3546 /* Check if REP prefix is OK. */
3547 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3548 {
3549 as_bad (_("invalid instruction `%s' after `%s'"),
3550 i.tm.name, i.rep_prefix);
3551 return;
3552 }
3553
c1ba0266
L		 3554 /* Check for lock without a lockable instruction. Destination operand
3555 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3556 if (i.prefix[LOCK_PREFIX]
3557 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3558 || i.mem_operands == 0
3559 || (i.tm.base_opcode != 0x86
3560 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3561 {
3562 as_bad (_("expecting lockable instruction after `lock'"));
3563 return;
3564 }
3565
42164a71 3566 /* Check if HLE prefix is OK. */
165de32a 3567 if (i.hle_prefix && !check_hle ())
42164a71
L		 3568 return;
3569
7e8b059b
L		 3570 /* Check BND prefix. */
3571 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3572 as_bad (_("expecting valid branch instruction after `bnd'"));
3573
3574 if (i.tm.cpu_flags.bitfield.cpumpx
3575 && flag_code == CODE_64BIT
3576 && i.prefix[ADDR_PREFIX])
3577 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3578
3579 /* Insert BND prefix. */
3580 if (add_bnd_prefix
3581 && i.tm.opcode_modifier.bndprefixok
3582 && !i.prefix[BND_PREFIX])
3583 add_prefix (BND_PREFIX_OPCODE);
3584
29b0f896 3585 /* Check string instruction segment overrides. */
40fb9820 3586 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3587 {
3588 if (!check_string ())
5dd0794d 3589 return;
fc0763e6 3590 i.disp_operands = 0;
29b0f896 3591 }
5dd0794d 3592
29b0f896
AM		 3593 if (!process_suffix ())
3594 return;
e413e4e9 3595
bc0844ae
L		 3596 /* Update operand types. */
3597 for (j = 0; j < i.operands; j++)
3598 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3599
29b0f896
AM		 3600 /* Make still unresolved immediate matches conform to size of immediate
3601 given in i.suffix. */
3602 if (!finalize_imm ())
3603 return;
252b5132 3604
40fb9820 3605 if (i.types[0].bitfield.imm1)
29b0f896 3606 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3607
9afe6eb8
L		 3608 /* We only need to check those implicit registers for instructions
3609 with 3 operands or less. */
3610 if (i.operands <= 3)
3611 for (j = 0; j < i.operands; j++)
3612 if (i.types[j].bitfield.inoutportreg
3613 || i.types[j].bitfield.shiftcount
3614 || i.types[j].bitfield.acc
3615 || i.types[j].bitfield.floatacc)
3616 i.reg_operands--;
40fb9820 3617
c0f3af97
L		 3618 /* ImmExt should be processed after SSE2AVX. */
3619 if (!i.tm.opcode_modifier.sse2avx
3620 && i.tm.opcode_modifier.immext)
65da13b5 3621 process_immext ();
252b5132 3622
29b0f896
AM		 3623 /* For insns with operands there are more diddles to do to the opcode. */
3624 if (i.operands)
3625 {
3626 if (!process_operands ())
3627 return;
3628 }
40fb9820 3629 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3630 {
3631 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3632 as_warn (_("translating to `%sp'"), i.tm.name);
3633 }
252b5132 3634
9e5e5283
L		 3635 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3636 {
3637 if (flag_code == CODE_16BIT)
3638 {
3639 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3640 i.tm.name);
3641 return;
3642 }
c0f3af97 3643
9e5e5283
L		 3644 if (i.tm.opcode_modifier.vex)
3645 build_vex_prefix (t);
3646 else
3647 build_evex_prefix ();
3648 }
43234a1e 3649
5dd85c99
SP		 3650 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3651 instructions may define INT_OPCODE as well, so avoid this corner
3652 case for those instructions that use MODRM. */
3653 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3654 && !i.tm.opcode_modifier.modrm
3655 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3656 {
3657 i.tm.base_opcode = INT3_OPCODE;
3658 i.imm_operands = 0;
3659 }
252b5132 3660
40fb9820
L		 3661 if ((i.tm.opcode_modifier.jump
3662 || i.tm.opcode_modifier.jumpbyte
3663 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3664 && i.op[0].disps->X_op == O_constant)
3665 {
3666 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3667 the absolute address given by the constant. Since ix86 jumps and
3668 calls are pc relative, we need to generate a reloc. */
3669 i.op[0].disps->X_add_symbol = &abs_symbol;
3670 i.op[0].disps->X_op = O_symbol;
3671 }
252b5132 3672
40fb9820 3673 if (i.tm.opcode_modifier.rex64)
161a04f6 3674 i.rex |= REX_W;
252b5132 3675
29b0f896
AM		 3676 /* For 8 bit registers we need an empty rex prefix. Also if the
3677 instruction already has a prefix, we need to convert old
3678 registers to new ones. */
773f551c 3679
40fb9820 3680 if ((i.types[0].bitfield.reg8
29b0f896 3681 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3682 || (i.types[1].bitfield.reg8
29b0f896 3683 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3684 || ((i.types[0].bitfield.reg8
3685 || i.types[1].bitfield.reg8)
29b0f896
AM		 3686 && i.rex != 0))
3687 {
3688 int x;
726c5dcd 3689
29b0f896
AM		 3690 i.rex |= REX_OPCODE;
3691 for (x = 0; x < 2; x++)
3692 {
3693 /* Look for 8 bit operand that uses old registers. */
40fb9820 3694 if (i.types[x].bitfield.reg8
29b0f896 3695 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3696 {
29b0f896
AM		 3697 /* In case it is "hi" register, give up. */
3698 if (i.op[x].regs->reg_num > 3)
a540244d 3699 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3700 "instruction requiring REX prefix."),
a540244d 3701 register_prefix, i.op[x].regs->reg_name);
773f551c 3702
29b0f896
AM		 3703 /* Otherwise it is equivalent to the extended register.
3704 Since the encoding doesn't change this is merely
3705 cosmetic cleanup for debug output. */
3706
3707 i.op[x].regs = i.op[x].regs + 8;
773f551c 3708 }
29b0f896
AM		 3709 }
3710 }
773f551c 3711
7ab9ffdd 3712 if (i.rex != 0)
29b0f896
AM		 3713 add_prefix (REX_OPCODE | i.rex);
3714
3715 /* We are ready to output the insn. */
3716 output_insn ();
3717}
3718
3719static char *
e3bb37b5 3720parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3721{
3722 char *l = line;
3723 char *token_start = l;
3724 char *mnem_p;
5c6af06e 3725 int supported;
d3ce72d0 3726 const insn_template *t;
b6169b20 3727 char *dot_p = NULL;
29b0f896 3728
29b0f896
AM		 3729 while (1)
3730 {
3731 mnem_p = mnemonic;
3732 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3733 {
b6169b20
L		 3734 if (*mnem_p == '.')
3735 dot_p = mnem_p;
29b0f896
AM		 3736 mnem_p++;
3737 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3738 {
29b0f896
AM		 3739 as_bad (_("no such instruction: `%s'"), token_start);
3740 return NULL;
3741 }
3742 l++;
3743 }
3744 if (!is_space_char (*l)
3745 && *l != END_OF_INSN
e44823cf
JB		 3746 && (intel_syntax
3747 || (*l != PREFIX_SEPARATOR
3748 && *l != ',')))
29b0f896
AM		 3749 {
3750 as_bad (_("invalid character %s in mnemonic"),
3751 output_invalid (*l));
3752 return NULL;
3753 }
3754 if (token_start == l)
3755 {
e44823cf 3756 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3757 as_bad (_("expecting prefix; got nothing"));
3758 else
3759 as_bad (_("expecting mnemonic; got nothing"));
3760 return NULL;
3761 }
45288df1 3762
29b0f896 3763 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3764 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3765
29b0f896
AM		 3766 if (*l != END_OF_INSN
3767 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3768 && current_templates
40fb9820 3769 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3770 {
c6fb90c8 3771 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3772 {
3773 as_bad ((flag_code != CODE_64BIT
3774 ? _("`%s' is only supported in 64-bit mode")
3775 : _("`%s' is not supported in 64-bit mode")),
3776 current_templates->start->name);
3777 return NULL;
3778 }
29b0f896
AM		 3779 /* If we are in 16-bit mode, do not allow addr16 or data16.
3780 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3781 if ((current_templates->start->opcode_modifier.size16
3782 || current_templates->start->opcode_modifier.size32)
29b0f896 3783 && flag_code != CODE_64BIT
40fb9820 3784 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3785 ^ (flag_code == CODE_16BIT)))
3786 {
3787 as_bad (_("redundant %s prefix"),
3788 current_templates->start->name);
3789 return NULL;
45288df1 3790 }
29b0f896
AM		 3791 /* Add prefix, checking for repeated prefixes. */
3792 switch (add_prefix (current_templates->start->base_opcode))
3793 {
c32fa91d 3794 case PREFIX_EXIST:
29b0f896 3795 return NULL;
c32fa91d 3796 case PREFIX_REP:
42164a71 3797 if (current_templates->start->cpu_flags.bitfield.cpuhle)
165de32a 3798 i.hle_prefix = current_templates->start->name;
7e8b059b
L		 3799 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3800 i.bnd_prefix = current_templates->start->name;
42164a71 3801 else
d5de92cf 3802 i.rep_prefix = current_templates->start->name;
29b0f896 3803 break;
c32fa91d
L		 3804 default:
3805 break;
29b0f896
AM		 3806 }
3807 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3808 token_start = ++l;
3809 }
3810 else
3811 break;
3812 }
45288df1 3813
30a55f88 3814 if (!current_templates)
b6169b20 3815 {
f8a5c266
L		 3816 /* Check if we should swap operand or force 32bit displacement in
3817 encoding. */
30a55f88
L		 3818 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3819 i.swap_operand = 1;
8d63c93e 3820 else if (mnem_p - 3 == dot_p
a501d77e
L		 3821 && dot_p[1] == 'd'
3822 && dot_p[2] == '8')
3823 i.disp_encoding = disp_encoding_8bit;
8d63c93e 3824 else if (mnem_p - 4 == dot_p
f8a5c266
L		 3825 && dot_p[1] == 'd'
3826 && dot_p[2] == '3'
3827 && dot_p[3] == '2')
a501d77e 3828 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 3829 else
3830 goto check_suffix;
3831 mnem_p = dot_p;
3832 *dot_p = '\0';
d3ce72d0 3833 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3834 }
3835
29b0f896
AM		 3836 if (!current_templates)
3837 {
b6169b20 3838check_suffix:
29b0f896
AM		 3839 /* See if we can get a match by trimming off a suffix. */
3840 switch (mnem_p[-1])
3841 {
3842 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3843 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3844 i.suffix = SHORT_MNEM_SUFFIX;
3845 else
29b0f896
AM		 3846 case BYTE_MNEM_SUFFIX:
3847 case QWORD_MNEM_SUFFIX:
3848 i.suffix = mnem_p[-1];
3849 mnem_p[-1] = '\0';
d3ce72d0
NC		 3850 current_templates = (const templates *) hash_find (op_hash,
3851 mnemonic);
29b0f896
AM		 3852 break;
3853 case SHORT_MNEM_SUFFIX:
3854 case LONG_MNEM_SUFFIX:
3855 if (!intel_syntax)
3856 {
3857 i.suffix = mnem_p[-1];
3858 mnem_p[-1] = '\0';
d3ce72d0
NC		 3859 current_templates = (const templates *) hash_find (op_hash,
3860 mnemonic);
29b0f896
AM		 3861 }
3862 break;
252b5132 3863
29b0f896
AM		 3864 /* Intel Syntax. */
3865 case 'd':
3866 if (intel_syntax)
3867 {
9306ca4a 3868 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3869 i.suffix = SHORT_MNEM_SUFFIX;
3870 else
3871 i.suffix = LONG_MNEM_SUFFIX;
3872 mnem_p[-1] = '\0';
d3ce72d0
NC		 3873 current_templates = (const templates *) hash_find (op_hash,
3874 mnemonic);
29b0f896
AM		 3875 }
3876 break;
3877 }
3878 if (!current_templates)
3879 {
3880 as_bad (_("no such instruction: `%s'"), token_start);
3881 return NULL;
3882 }
3883 }
252b5132 3884
40fb9820
L		 3885 if (current_templates->start->opcode_modifier.jump
3886 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3887 {
3888 /* Check for a branch hint. We allow ",pt" and ",pn" for
3889 predict taken and predict not taken respectively.
3890 I'm not sure that branch hints actually do anything on loop
3891 and jcxz insns (JumpByte) for current Pentium4 chips. They
3892 may work in the future and it doesn't hurt to accept them
3893 now. */
3894 if (l[0] == ',' && l[1] == 'p')
3895 {
3896 if (l[2] == 't')
3897 {
3898 if (!add_prefix (DS_PREFIX_OPCODE))
3899 return NULL;
3900 l += 3;
3901 }
3902 else if (l[2] == 'n')
3903 {
3904 if (!add_prefix (CS_PREFIX_OPCODE))
3905 return NULL;
3906 l += 3;
3907 }
3908 }
3909 }
3910 /* Any other comma loses. */
3911 if (*l == ',')
3912 {
3913 as_bad (_("invalid character %s in mnemonic"),
3914 output_invalid (*l));
3915 return NULL;
3916 }
252b5132 3917
29b0f896 3918 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3919 supported = 0;
3920 for (t = current_templates->start; t < current_templates->end; ++t)
3921 {
c0f3af97
L		 3922 supported |= cpu_flags_match (t);
3923 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3924 goto skip;
5c6af06e 3925 }
3629bb00 3926
c0f3af97 3927 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3928 {
3929 as_bad (flag_code == CODE_64BIT
3930 ? _("`%s' is not supported in 64-bit mode")
3931 : _("`%s' is only supported in 64-bit mode"),
3932 current_templates->start->name);
3933 return NULL;
3934 }
c0f3af97 3935 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3936 {
3629bb00 3937 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3938 current_templates->start->name,
41aacd83 3939 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3940 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3941 return NULL;
29b0f896 3942 }
3629bb00
L		 3943
3944skip:
3945 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3946 && (flag_code != CODE_16BIT))
29b0f896
AM		 3947 {
3948 as_warn (_("use .code16 to ensure correct addressing mode"));
3949 }
252b5132 3950
29b0f896
AM		 3951 return l;
3952}
252b5132 3953
29b0f896 3954static char *
e3bb37b5 3955parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3956{
3957 char *token_start;
3138f287 3958
29b0f896
AM		 3959 /* 1 if operand is pending after ','. */
3960 unsigned int expecting_operand = 0;
252b5132 3961
29b0f896
AM		 3962 /* Non-zero if operand parens not balanced. */
3963 unsigned int paren_not_balanced;
3964
3965 while (*l != END_OF_INSN)
3966 {
3967 /* Skip optional white space before operand. */
3968 if (is_space_char (*l))
3969 ++l;
3970 if (!is_operand_char (*l) && *l != END_OF_INSN)
3971 {
3972 as_bad (_("invalid character %s before operand %d"),
3973 output_invalid (*l),
3974 i.operands + 1);
3975 return NULL;
3976 }
3977 token_start = l; /* after white space */
3978 paren_not_balanced = 0;
3979 while (paren_not_balanced || *l != ',')
3980 {
3981 if (*l == END_OF_INSN)
3982 {
3983 if (paren_not_balanced)
3984 {
3985 if (!intel_syntax)
3986 as_bad (_("unbalanced parenthesis in operand %d."),
3987 i.operands + 1);
3988 else
3989 as_bad (_("unbalanced brackets in operand %d."),
3990 i.operands + 1);
3991 return NULL;
3992 }
3993 else
3994 break; /* we are done */
3995 }
3996 else if (!is_operand_char (*l) && !is_space_char (*l))
3997 {
3998 as_bad (_("invalid character %s in operand %d"),
3999 output_invalid (*l),
4000 i.operands + 1);
4001 return NULL;
4002 }
4003 if (!intel_syntax)
4004 {
4005 if (*l == '(')
4006 ++paren_not_balanced;
4007 if (*l == ')')
4008 --paren_not_balanced;
4009 }
4010 else
4011 {
4012 if (*l == '[')
4013 ++paren_not_balanced;
4014 if (*l == ']')
4015 --paren_not_balanced;
4016 }
4017 l++;
4018 }
4019 if (l != token_start)
4020 { /* Yes, we've read in another operand. */
4021 unsigned int operand_ok;
4022 this_operand = i.operands++;
7d5e4556 4023 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4024 if (i.operands > MAX_OPERANDS)
4025 {
4026 as_bad (_("spurious operands; (%d operands/instruction max)"),
4027 MAX_OPERANDS);
4028 return NULL;
4029 }
4030 /* Now parse operand adding info to 'i' as we go along. */
4031 END_STRING_AND_SAVE (l);
4032
4033 if (intel_syntax)
4034 operand_ok =
4035 i386_intel_operand (token_start,
4036 intel_float_operand (mnemonic));
4037 else
a7619375 4038 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4039
4040 RESTORE_END_STRING (l);
4041 if (!operand_ok)
4042 return NULL;
4043 }
4044 else
4045 {
4046 if (expecting_operand)
4047 {
4048 expecting_operand_after_comma:
4049 as_bad (_("expecting operand after ','; got nothing"));
4050 return NULL;
4051 }
4052 if (*l == ',')
4053 {
4054 as_bad (_("expecting operand before ','; got nothing"));
4055 return NULL;
4056 }
4057 }
7f3f1ea2 4058
29b0f896
AM		 4059 /* Now *l must be either ',' or END_OF_INSN. */
4060 if (*l == ',')
4061 {
4062 if (*++l == END_OF_INSN)
4063 {
4064 /* Just skip it, if it's \n complain. */
4065 goto expecting_operand_after_comma;
4066 }
4067 expecting_operand = 1;
4068 }
4069 }
4070 return l;
4071}
7f3f1ea2 4072
050dfa73 4073static void
4d456e3d 4074swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4075{
4076 union i386_op temp_op;
40fb9820 4077 i386_operand_type temp_type;
050dfa73 4078 enum bfd_reloc_code_real temp_reloc;
4eed87de 4079
050dfa73
MM		 4080 temp_type = i.types[xchg2];
4081 i.types[xchg2] = i.types[xchg1];
4082 i.types[xchg1] = temp_type;
4083 temp_op = i.op[xchg2];
4084 i.op[xchg2] = i.op[xchg1];
4085 i.op[xchg1] = temp_op;
4086 temp_reloc = i.reloc[xchg2];
4087 i.reloc[xchg2] = i.reloc[xchg1];
4088 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4089
4090 if (i.mask)
4091 {
4092 if (i.mask->operand == xchg1)
4093 i.mask->operand = xchg2;
4094 else if (i.mask->operand == xchg2)
4095 i.mask->operand = xchg1;
4096 }
4097 if (i.broadcast)
4098 {
4099 if (i.broadcast->operand == xchg1)
4100 i.broadcast->operand = xchg2;
4101 else if (i.broadcast->operand == xchg2)
4102 i.broadcast->operand = xchg1;
4103 }
4104 if (i.rounding)
4105 {
4106 if (i.rounding->operand == xchg1)
4107 i.rounding->operand = xchg2;
4108 else if (i.rounding->operand == xchg2)
4109 i.rounding->operand = xchg1;
4110 }
050dfa73
MM		 4111}
4112
29b0f896 4113static void
e3bb37b5 4114swap_operands (void)
29b0f896 4115{
b7c61d9a 4116 switch (i.operands)
050dfa73 4117 {
c0f3af97 4118 case 5:
b7c61d9a 4119 case 4:
4d456e3d 4120 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 4121 case 3:
4122 case 2:
4d456e3d 4123 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4124 break;
4125 default:
4126 abort ();
29b0f896 4127 }
29b0f896
AM		 4128
4129 if (i.mem_operands == 2)
4130 {
4131 const seg_entry *temp_seg;
4132 temp_seg = i.seg[0];
4133 i.seg[0] = i.seg[1];
4134 i.seg[1] = temp_seg;
4135 }
4136}
252b5132 4137
29b0f896
AM		 4138/* Try to ensure constant immediates are represented in the smallest
4139 opcode possible. */
4140static void
e3bb37b5 4141optimize_imm (void)
29b0f896
AM		 4142{
4143 char guess_suffix = 0;
4144 int op;
252b5132 4145
29b0f896
AM		 4146 if (i.suffix)
4147 guess_suffix = i.suffix;
4148 else if (i.reg_operands)
4149 {
4150 /* Figure out a suffix from the last register operand specified.
4151 We can't do this properly yet, ie. excluding InOutPortReg,
4152 but the following works for instructions with immediates.
4153 In any case, we can't set i.suffix yet. */
4154 for (op = i.operands; --op >= 0;)
40fb9820 4155 if (i.types[op].bitfield.reg8)
7ab9ffdd 4156 {
40fb9820
L		 4157 guess_suffix = BYTE_MNEM_SUFFIX;
4158 break;
4159 }
4160 else if (i.types[op].bitfield.reg16)
252b5132 4161 {
40fb9820
L		 4162 guess_suffix = WORD_MNEM_SUFFIX;
4163 break;
4164 }
4165 else if (i.types[op].bitfield.reg32)
4166 {
4167 guess_suffix = LONG_MNEM_SUFFIX;
4168 break;
4169 }
4170 else if (i.types[op].bitfield.reg64)
4171 {
4172 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4173 break;
252b5132 4174 }
29b0f896
AM		 4175 }
4176 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4177 guess_suffix = WORD_MNEM_SUFFIX;
4178
4179 for (op = i.operands; --op >= 0;)
40fb9820 4180 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4181 {
4182 switch (i.op[op].imms->X_op)
252b5132 4183 {
29b0f896
AM		 4184 case O_constant:
4185 /* If a suffix is given, this operand may be shortened. */
4186 switch (guess_suffix)
252b5132 4187 {
29b0f896 4188 case LONG_MNEM_SUFFIX:
40fb9820
L		 4189 i.types[op].bitfield.imm32 = 1;
4190 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4191 break;
4192 case WORD_MNEM_SUFFIX:
40fb9820
L		 4193 i.types[op].bitfield.imm16 = 1;
4194 i.types[op].bitfield.imm32 = 1;
4195 i.types[op].bitfield.imm32s = 1;
4196 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4197 break;
4198 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4199 i.types[op].bitfield.imm8 = 1;
4200 i.types[op].bitfield.imm8s = 1;
4201 i.types[op].bitfield.imm16 = 1;
4202 i.types[op].bitfield.imm32 = 1;
4203 i.types[op].bitfield.imm32s = 1;
4204 i.types[op].bitfield.imm64 = 1;
29b0f896 4205 break;
252b5132 4206 }
252b5132 4207
29b0f896
AM		 4208 /* If this operand is at most 16 bits, convert it
4209 to a signed 16 bit number before trying to see
4210 whether it will fit in an even smaller size.
4211 This allows a 16-bit operand such as $0xffe0 to
4212 be recognised as within Imm8S range. */
40fb9820 4213 if ((i.types[op].bitfield.imm16)
29b0f896 4214 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4215 {
29b0f896
AM		 4216 i.op[op].imms->X_add_number =
4217 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4218 }
40fb9820 4219 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4220 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4221 == 0))
4222 {
4223 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4224 ^ ((offsetT) 1 << 31))
4225 - ((offsetT) 1 << 31));
4226 }
40fb9820 4227 i.types[op]
c6fb90c8
L		 4228 = operand_type_or (i.types[op],
4229 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4230
29b0f896
AM		 4231 /* We must avoid matching of Imm32 templates when 64bit
4232 only immediate is available. */
4233 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4234 i.types[op].bitfield.imm32 = 0;
29b0f896 4235 break;
252b5132 4236
29b0f896
AM		 4237 case O_absent:
4238 case O_register:
4239 abort ();
4240
4241 /* Symbols and expressions. */
4242 default:
9cd96992
JB		 4243 /* Convert symbolic operand to proper sizes for matching, but don't
4244 prevent matching a set of insns that only supports sizes other
4245 than those matching the insn suffix. */
4246 {
40fb9820 4247 i386_operand_type mask, allowed;
d3ce72d0 4248 const insn_template *t;
9cd96992 4249
0dfbf9d7
L		 4250 operand_type_set (&mask, 0);
4251 operand_type_set (&allowed, 0);
40fb9820 4252
4eed87de
AM		 4253 for (t = current_templates->start;
4254 t < current_templates->end;
4255 ++t)
c6fb90c8
L		 4256 allowed = operand_type_or (allowed,
4257 t->operand_types[op]);
9cd96992
JB		 4258 switch (guess_suffix)
4259 {
4260 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4261 mask.bitfield.imm64 = 1;
4262 mask.bitfield.imm32s = 1;
9cd96992
JB		 4263 break;
4264 case LONG_MNEM_SUFFIX:
40fb9820 4265 mask.bitfield.imm32 = 1;
9cd96992
JB		 4266 break;
4267 case WORD_MNEM_SUFFIX:
40fb9820 4268 mask.bitfield.imm16 = 1;
9cd96992
JB		 4269 break;
4270 case BYTE_MNEM_SUFFIX:
40fb9820 4271 mask.bitfield.imm8 = 1;
9cd96992
JB		 4272 break;
4273 default:
9cd96992
JB		 4274 break;
4275 }
c6fb90c8 4276 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4277 if (!operand_type_all_zero (&allowed))
c6fb90c8 4278 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4279 }
29b0f896 4280 break;
252b5132 4281 }
29b0f896
AM		 4282 }
4283}
47926f60 4284
29b0f896
AM		 4285/* Try to use the smallest displacement type too. */
4286static void
e3bb37b5 4287optimize_disp (void)
29b0f896
AM		 4288{
4289 int op;
3e73aa7c 4290
29b0f896 4291 for (op = i.operands; --op >= 0;)
40fb9820 4292 if (operand_type_check (i.types[op], disp))
252b5132 4293 {
b300c311 4294 if (i.op[op].disps->X_op == O_constant)
252b5132 4295 {
91d6fa6a 4296 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4297
40fb9820 4298 if (i.types[op].bitfield.disp16
91d6fa6a 4299 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4300 {
4301 /* If this operand is at most 16 bits, convert
4302 to a signed 16 bit number and don't use 64bit
4303 displacement. */
91d6fa6a 4304 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4305 i.types[op].bitfield.disp64 = 0;
b300c311 4306 }
40fb9820 4307 if (i.types[op].bitfield.disp32
91d6fa6a 4308 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4309 {
4310 /* If this operand is at most 32 bits, convert
4311 to a signed 32 bit number and don't use 64bit
4312 displacement. */
91d6fa6a
NC		 4313 op_disp &= (((offsetT) 2 << 31) - 1);
4314 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4315 i.types[op].bitfield.disp64 = 0;
b300c311 4316 }
91d6fa6a 4317 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4318 {
40fb9820
L		 4319 i.types[op].bitfield.disp8 = 0;
4320 i.types[op].bitfield.disp16 = 0;
4321 i.types[op].bitfield.disp32 = 0;
4322 i.types[op].bitfield.disp32s = 0;
4323 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4324 i.op[op].disps = 0;
4325 i.disp_operands--;
4326 }
4327 else if (flag_code == CODE_64BIT)
4328 {
91d6fa6a 4329 if (fits_in_signed_long (op_disp))
28a9d8f5 4330 {
40fb9820
L		 4331 i.types[op].bitfield.disp64 = 0;
4332 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4333 }
0e1147d9 4334 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4335 && fits_in_unsigned_long (op_disp))
40fb9820 4336 i.types[op].bitfield.disp32 = 1;
b300c311 4337 }
40fb9820
L		 4338 if ((i.types[op].bitfield.disp32
4339 || i.types[op].bitfield.disp32s
4340 || i.types[op].bitfield.disp16)
91d6fa6a 4341 && fits_in_signed_byte (op_disp))
40fb9820 4342 i.types[op].bitfield.disp8 = 1;
252b5132 4343 }
67a4f2b7
AO		 4344 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4345 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4346 {
4347 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4348 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4349 i.types[op].bitfield.disp8 = 0;
4350 i.types[op].bitfield.disp16 = 0;
4351 i.types[op].bitfield.disp32 = 0;
4352 i.types[op].bitfield.disp32s = 0;
4353 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4354 }
4355 else
b300c311 4356 /* We only support 64bit displacement on constants. */
40fb9820 4357 i.types[op].bitfield.disp64 = 0;
252b5132 4358 }
29b0f896
AM		 4359}
4360
6c30d220
L		 4361/* Check if operands are valid for the instruction. */
4362
4363static int
4364check_VecOperands (const insn_template *t)
4365{
43234a1e
L		 4366 unsigned int op;
4367
6c30d220
L		 4368 /* Without VSIB byte, we can't have a vector register for index. */
4369 if (!t->opcode_modifier.vecsib
4370 && i.index_reg
4371 && (i.index_reg->reg_type.bitfield.regxmm
43234a1e
L		 4372 || i.index_reg->reg_type.bitfield.regymm
4373 || i.index_reg->reg_type.bitfield.regzmm))
6c30d220
L		 4374 {
4375 i.error = unsupported_vector_index_register;
4376 return 1;
4377 }
4378
ad8ecc81
MZ		 4379 /* Check if default mask is allowed. */
4380 if (t->opcode_modifier.nodefmask
4381 && (!i.mask || i.mask->mask->reg_num == 0))
4382 {
4383 i.error = no_default_mask;
4384 return 1;
4385 }
4386
7bab8ab5
JB		 4387 /* For VSIB byte, we need a vector register for index, and all vector
4388 registers must be distinct. */
4389 if (t->opcode_modifier.vecsib)
4390 {
4391 if (!i.index_reg
6c30d220
L		 4392 || !((t->opcode_modifier.vecsib == VecSIB128
4393 && i.index_reg->reg_type.bitfield.regxmm)
4394 || (t->opcode_modifier.vecsib == VecSIB256
43234a1e
L		 4395 && i.index_reg->reg_type.bitfield.regymm)
4396 || (t->opcode_modifier.vecsib == VecSIB512
4397 && i.index_reg->reg_type.bitfield.regzmm)))
7bab8ab5
JB		 4398 {
4399 i.error = invalid_vsib_address;
4400 return 1;
4401 }
4402
43234a1e
L		 4403 gas_assert (i.reg_operands == 2 || i.mask);
4404 if (i.reg_operands == 2 && !i.mask)
4405 {
4406 gas_assert (i.types[0].bitfield.regxmm
7c84a0ca 4407 || i.types[0].bitfield.regymm);
43234a1e 4408 gas_assert (i.types[2].bitfield.regxmm
7c84a0ca 4409 || i.types[2].bitfield.regymm);
43234a1e
L		 4410 if (operand_check == check_none)
4411 return 0;
4412 if (register_number (i.op[0].regs)
4413 != register_number (i.index_reg)
4414 && register_number (i.op[2].regs)
4415 != register_number (i.index_reg)
4416 && register_number (i.op[0].regs)
4417 != register_number (i.op[2].regs))
4418 return 0;
4419 if (operand_check == check_error)
4420 {
4421 i.error = invalid_vector_register_set;
4422 return 1;
4423 }
4424 as_warn (_("mask, index, and destination registers should be distinct"));
4425 }
8444f82a
MZ		 4426 else if (i.reg_operands == 1 && i.mask)
4427 {
4428 if ((i.types[1].bitfield.regymm
4429 || i.types[1].bitfield.regzmm)
4430 && (register_number (i.op[1].regs)
4431 == register_number (i.index_reg)))
4432 {
4433 if (operand_check == check_error)
4434 {
4435 i.error = invalid_vector_register_set;
4436 return 1;
4437 }
4438 if (operand_check != check_none)
4439 as_warn (_("index and destination registers should be distinct"));
4440 }
4441 }
43234a1e 4442 }
7bab8ab5 4443
43234a1e
L		 4444 /* Check if broadcast is supported by the instruction and is applied
4445 to the memory operand. */
4446 if (i.broadcast)
4447 {
4448 int broadcasted_opnd_size;
4449
4450 /* Check if specified broadcast is supported in this instruction,
4451 and it's applied to memory operand of DWORD or QWORD type,
4452 depending on VecESize. */
4453 if (i.broadcast->type != t->opcode_modifier.broadcast
4454 || !i.types[i.broadcast->operand].bitfield.mem
4455 || (t->opcode_modifier.vecesize == 0
4456 && !i.types[i.broadcast->operand].bitfield.dword
4457 && !i.types[i.broadcast->operand].bitfield.unspecified)
4458 || (t->opcode_modifier.vecesize == 1
4459 && !i.types[i.broadcast->operand].bitfield.qword
4460 && !i.types[i.broadcast->operand].bitfield.unspecified))
4461 goto bad_broadcast;
4462
4463 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4464 if (i.broadcast->type == BROADCAST_1TO16)
4465 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4466 else if (i.broadcast->type == BROADCAST_1TO8)
4467 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
b28d1bda
IT		 4468 else if (i.broadcast->type == BROADCAST_1TO4)
4469 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4470 else if (i.broadcast->type == BROADCAST_1TO2)
4471 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
43234a1e
L		 4472 else
4473 goto bad_broadcast;
4474
4475 if ((broadcasted_opnd_size == 256
4476 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4477 || (broadcasted_opnd_size == 512
4478 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4479 {
4480 bad_broadcast:
4481 i.error = unsupported_broadcast;
4482 return 1;
4483 }
4484 }
4485 /* If broadcast is supported in this instruction, we need to check if
4486 operand of one-element size isn't specified without broadcast. */
4487 else if (t->opcode_modifier.broadcast && i.mem_operands)
4488 {
4489 /* Find memory operand. */
4490 for (op = 0; op < i.operands; op++)
4491 if (operand_type_check (i.types[op], anymem))
4492 break;
4493 gas_assert (op < i.operands);
4494 /* Check size of the memory operand. */
4495 if ((t->opcode_modifier.vecesize == 0
4496 && i.types[op].bitfield.dword)
4497 || (t->opcode_modifier.vecesize == 1
4498 && i.types[op].bitfield.qword))
4499 {
4500 i.error = broadcast_needed;
4501 return 1;
4502 }
4503 }
4504
4505 /* Check if requested masking is supported. */
4506 if (i.mask
4507 && (!t->opcode_modifier.masking
4508 || (i.mask->zeroing
4509 && t->opcode_modifier.masking == MERGING_MASKING)))
4510 {
4511 i.error = unsupported_masking;
4512 return 1;
4513 }
4514
4515 /* Check if masking is applied to dest operand. */
4516 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4517 {
4518 i.error = mask_not_on_destination;
4519 return 1;
4520 }
4521
43234a1e
L		 4522 /* Check RC/SAE. */
4523 if (i.rounding)
4524 {
4525 if ((i.rounding->type != saeonly
4526 && !t->opcode_modifier.staticrounding)
4527 || (i.rounding->type == saeonly
4528 && (t->opcode_modifier.staticrounding
4529 || !t->opcode_modifier.sae)))
4530 {
4531 i.error = unsupported_rc_sae;
4532 return 1;
4533 }
4534 /* If the instruction has several immediate operands and one of
4535 them is rounding, the rounding operand should be the last
4536 immediate operand. */
4537 if (i.imm_operands > 1
4538 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4539 {
43234a1e 4540 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4541 return 1;
4542 }
6c30d220
L		 4543 }
4544
43234a1e
L		 4545 /* Check vector Disp8 operand. */
4546 if (t->opcode_modifier.disp8memshift)
4547 {
4548 if (i.broadcast)
4549 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4550 else
4551 i.memshift = t->opcode_modifier.disp8memshift;
4552
4553 for (op = 0; op < i.operands; op++)
4554 if (operand_type_check (i.types[op], disp)
4555 && i.op[op].disps->X_op == O_constant)
4556 {
4557 offsetT value = i.op[op].disps->X_add_number;
4558 int vec_disp8_ok = fits_in_vec_disp8 (value);
4559 if (t->operand_types [op].bitfield.vec_disp8)
4560 {
4561 if (vec_disp8_ok)
4562 i.types[op].bitfield.vec_disp8 = 1;
4563 else
4564 {
4565 /* Vector insn can only have Vec_Disp8/Disp32 in
4566 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4567 mode. */
4568 i.types[op].bitfield.disp8 = 0;
4569 if (flag_code != CODE_16BIT)
4570 i.types[op].bitfield.disp16 = 0;
4571 }
4572 }
4573 else if (flag_code != CODE_16BIT)
4574 {
4575 /* One form of this instruction supports vector Disp8.
4576 Try vector Disp8 if we need to use Disp32. */
4577 if (vec_disp8_ok && !fits_in_signed_byte (value))
4578 {
4579 i.error = try_vector_disp8;
4580 return 1;
4581 }
4582 }
4583 }
4584 }
4585 else
4586 i.memshift = -1;
4587
6c30d220
L		 4588 return 0;
4589}
4590
43f3e2ee 4591/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4592 operand types. */
4593
4594static int
4595VEX_check_operands (const insn_template *t)
4596{
43234a1e
L		 4597 /* VREX is only valid with EVEX prefix. */
4598 if (i.need_vrex && !t->opcode_modifier.evex)
4599 {
4600 i.error = invalid_register_operand;
4601 return 1;
4602 }
4603
a683cc34
SP		 4604 if (!t->opcode_modifier.vex)
4605 return 0;
4606
4607 /* Only check VEX_Imm4, which must be the first operand. */
4608 if (t->operand_types[0].bitfield.vec_imm4)
4609 {
4610 if (i.op[0].imms->X_op != O_constant
4611 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4612 {
a65babc9 4613 i.error = bad_imm4;
891edac4
L		 4614 return 1;
4615 }
a683cc34
SP		 4616
4617 /* Turn off Imm8 so that update_imm won't complain. */
4618 i.types[0] = vec_imm4;
4619 }
4620
4621 return 0;
4622}
4623
d3ce72d0 4624static const insn_template *
e3bb37b5 4625match_template (void)
29b0f896
AM		 4626{
4627 /* Points to template once we've found it. */
d3ce72d0 4628 const insn_template *t;
40fb9820 4629 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4630 i386_operand_type overlap4;
29b0f896 4631 unsigned int found_reverse_match;
40fb9820
L		 4632 i386_opcode_modifier suffix_check;
4633 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4634 int addr_prefix_disp;
a5c311ca 4635 unsigned int j;
3629bb00 4636 unsigned int found_cpu_match;
45664ddb 4637 unsigned int check_register;
5614d22c 4638 enum i386_error specific_error = 0;
29b0f896 4639
c0f3af97
L		 4640#if MAX_OPERANDS != 5
4641# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4642#endif
4643
29b0f896 4644 found_reverse_match = 0;
539e75ad 4645 addr_prefix_disp = -1;
40fb9820
L		 4646
4647 memset (&suffix_check, 0, sizeof (suffix_check));
4648 if (i.suffix == BYTE_MNEM_SUFFIX)
4649 suffix_check.no_bsuf = 1;
4650 else if (i.suffix == WORD_MNEM_SUFFIX)
4651 suffix_check.no_wsuf = 1;
4652 else if (i.suffix == SHORT_MNEM_SUFFIX)
4653 suffix_check.no_ssuf = 1;
4654 else if (i.suffix == LONG_MNEM_SUFFIX)
4655 suffix_check.no_lsuf = 1;
4656 else if (i.suffix == QWORD_MNEM_SUFFIX)
4657 suffix_check.no_qsuf = 1;
4658 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4659 suffix_check.no_ldsuf = 1;
29b0f896 4660
01559ecc
L		 4661 /* Must have right number of operands. */
4662 i.error = number_of_operands_mismatch;
4663
45aa61fe 4664 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4665 {
539e75ad
L		 4666 addr_prefix_disp = -1;
4667
29b0f896
AM		 4668 if (i.operands != t->operands)
4669 continue;
4670
50aecf8c 4671 /* Check processor support. */
a65babc9 4672 i.error = unsupported;
c0f3af97
L		 4673 found_cpu_match = (cpu_flags_match (t)
4674 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4675 if (!found_cpu_match)
4676 continue;
4677
e1d4d893 4678 /* Check old gcc support. */
a65babc9 4679 i.error = old_gcc_only;
e1d4d893
L		 4680 if (!old_gcc && t->opcode_modifier.oldgcc)
4681 continue;
4682
4683 /* Check AT&T mnemonic. */
a65babc9 4684 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4685 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4686 continue;
4687
891edac4 4688 /* Check AT&T/Intel syntax. */
a65babc9 4689 i.error = unsupported_syntax;
5c07affc
L		 4690 if ((intel_syntax && t->opcode_modifier.attsyntax)
4691 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 4692 continue;
4693
20592a94 4694 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4695 i.error = invalid_instruction_suffix;
567e4e96
L		 4696 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4697 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4698 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4699 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4700 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4701 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4702 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 4703 continue;
4704
5c07affc 4705 if (!operand_size_match (t))
7d5e4556 4706 continue;
539e75ad 4707
5c07affc
L		 4708 for (j = 0; j < MAX_OPERANDS; j++)
4709 operand_types[j] = t->operand_types[j];
4710
45aa61fe
AM		 4711 /* In general, don't allow 64-bit operands in 32-bit mode. */
4712 if (i.suffix == QWORD_MNEM_SUFFIX
4713 && flag_code != CODE_64BIT
4714 && (intel_syntax
40fb9820 4715 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4716 && !intel_float_operand (t->name))
4717 : intel_float_operand (t->name) != 2)
40fb9820 4718 && ((!operand_types[0].bitfield.regmmx
c0f3af97 4719 && !operand_types[0].bitfield.regxmm
43234a1e
L		 4720 && !operand_types[0].bitfield.regymm
4721 && !operand_types[0].bitfield.regzmm)
40fb9820 4722 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736
AM		 4723 && operand_types[t->operands > 1].bitfield.regxmm
4724 && operand_types[t->operands > 1].bitfield.regymm
4725 && operand_types[t->operands > 1].bitfield.regzmm))
45aa61fe
AM		 4726 && (t->base_opcode != 0x0fc7
4727 || t->extension_opcode != 1 /* cmpxchg8b */))
4728 continue;
4729
192dc9c6
JB		 4730 /* In general, don't allow 32-bit operands on pre-386. */
4731 else if (i.suffix == LONG_MNEM_SUFFIX
4732 && !cpu_arch_flags.bitfield.cpui386
4733 && (intel_syntax
4734 ? (!t->opcode_modifier.ignoresize
4735 && !intel_float_operand (t->name))
4736 : intel_float_operand (t->name) != 2)
4737 && ((!operand_types[0].bitfield.regmmx
4738 && !operand_types[0].bitfield.regxmm)
4739 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736 4740 && operand_types[t->operands > 1].bitfield.regxmm)))
192dc9c6
JB		 4741 continue;
4742
29b0f896 4743 /* Do not verify operands when there are none. */
50aecf8c 4744 else
29b0f896 4745 {
c6fb90c8 4746 if (!t->operands)
2dbab7d5
L		 4747 /* We've found a match; break out of loop. */
4748 break;
29b0f896 4749 }
252b5132 4750
539e75ad
L		 4751 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4752 into Disp32/Disp16/Disp32 operand. */
4753 if (i.prefix[ADDR_PREFIX] != 0)
4754 {
40fb9820 4755 /* There should be only one Disp operand. */
539e75ad
L		 4756 switch (flag_code)
4757 {
4758 case CODE_16BIT:
40fb9820
L		 4759 for (j = 0; j < MAX_OPERANDS; j++)
4760 {
4761 if (operand_types[j].bitfield.disp16)
4762 {
4763 addr_prefix_disp = j;
4764 operand_types[j].bitfield.disp32 = 1;
4765 operand_types[j].bitfield.disp16 = 0;
4766 break;
4767 }
4768 }
539e75ad
L		 4769 break;
4770 case CODE_32BIT:
40fb9820
L		 4771 for (j = 0; j < MAX_OPERANDS; j++)
4772 {
4773 if (operand_types[j].bitfield.disp32)
4774 {
4775 addr_prefix_disp = j;
4776 operand_types[j].bitfield.disp32 = 0;
4777 operand_types[j].bitfield.disp16 = 1;
4778 break;
4779 }
4780 }
539e75ad
L		 4781 break;
4782 case CODE_64BIT:
40fb9820
L		 4783 for (j = 0; j < MAX_OPERANDS; j++)
4784 {
4785 if (operand_types[j].bitfield.disp64)
4786 {
4787 addr_prefix_disp = j;
4788 operand_types[j].bitfield.disp64 = 0;
4789 operand_types[j].bitfield.disp32 = 1;
4790 break;
4791 }
4792 }
539e75ad
L		 4793 break;
4794 }
539e75ad
L		 4795 }
4796
56ffb741
L		 4797 /* We check register size if needed. */
4798 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4799 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4800 switch (t->operands)
4801 {
4802 case 1:
40fb9820 4803 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4804 continue;
4805 break;
4806 case 2:
8b38ad71
L		 4807 /* xchg %eax, %eax is a special case. It is an aliase for nop
4808 only in 32bit mode and we can use opcode 0x90. In 64bit
4809 mode, we can't use 0x90 for xchg %eax, %eax since it should
4810 zero-extend %eax to %rax. */
4811 if (flag_code == CODE_64BIT
4812 && t->base_opcode == 0x90
0dfbf9d7
L		 4813 && operand_type_equal (&i.types [0], &acc32)
4814 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4815 continue;
b6169b20
L		 4816 if (i.swap_operand)
4817 {
4818 /* If we swap operand in encoding, we either match
4819 the next one or reverse direction of operands. */
4820 if (t->opcode_modifier.s)
4821 continue;
4822 else if (t->opcode_modifier.d)
4823 goto check_reverse;
4824 }
4825
29b0f896 4826 case 3:
fa99fab2
L		 4827 /* If we swap operand in encoding, we match the next one. */
4828 if (i.swap_operand && t->opcode_modifier.s)
4829 continue;
f48ff2ae 4830 case 4:
c0f3af97 4831 case 5:
c6fb90c8 4832 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4833 if (!operand_type_match (overlap0, i.types[0])
4834 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4835 || (check_register
4836 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4837 operand_types[0],
4838 overlap1, i.types[1],
4839 operand_types[1])))
29b0f896
AM		 4840 {
4841 /* Check if other direction is valid ... */
40fb9820 4842 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4843 continue;
4844
b6169b20 4845check_reverse:
29b0f896 4846 /* Try reversing direction of operands. */
c6fb90c8
L		 4847 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4848 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4849 if (!operand_type_match (overlap0, i.types[0])
4850 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4851 || (check_register
4852 && !operand_type_register_match (overlap0,
4853 i.types[0],
4854 operand_types[1],
4855 overlap1,
4856 i.types[1],
4857 operand_types[0])))
29b0f896
AM		 4858 {
4859 /* Does not match either direction. */
4860 continue;
4861 }
4862 /* found_reverse_match holds which of D or FloatDR
4863 we've found. */
40fb9820 4864 if (t->opcode_modifier.d)
8a2ed489 4865 found_reverse_match = Opcode_D;
40fb9820 4866 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4867 found_reverse_match = Opcode_FloatD;
4868 else
4869 found_reverse_match = 0;
40fb9820 4870 if (t->opcode_modifier.floatr)
8a2ed489 4871 found_reverse_match |= Opcode_FloatR;
29b0f896 4872 }
f48ff2ae 4873 else
29b0f896 4874 {
f48ff2ae 4875 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4876 switch (t->operands)
4877 {
c0f3af97
L		 4878 case 5:
4879 overlap4 = operand_type_and (i.types[4],
4880 operand_types[4]);
d1cbb4db 4881 case 4:
c6fb90c8
L		 4882 overlap3 = operand_type_and (i.types[3],
4883 operand_types[3]);
d1cbb4db 4884 case 3:
c6fb90c8
L		 4885 overlap2 = operand_type_and (i.types[2],
4886 operand_types[2]);
d1cbb4db
L		 4887 break;
4888 }
29b0f896 4889
f48ff2ae
L		 4890 switch (t->operands)
4891 {
c0f3af97
L		 4892 case 5:
4893 if (!operand_type_match (overlap4, i.types[4])
4894 || !operand_type_register_match (overlap3,
4895 i.types[3],
4896 operand_types[3],
4897 overlap4,
4898 i.types[4],
4899 operand_types[4]))
4900 continue;
f48ff2ae 4901 case 4:
40fb9820 4902 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4903 || (check_register
4904 && !operand_type_register_match (overlap2,
4905 i.types[2],
4906 operand_types[2],
4907 overlap3,
4908 i.types[3],
4909 operand_types[3])))
f48ff2ae
L		 4910 continue;
4911 case 3:
4912 /* Here we make use of the fact that there are no
4913 reverse match 3 operand instructions, and all 3
4914 operand instructions only need to be checked for
4915 register consistency between operands 2 and 3. */
40fb9820 4916 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4917 || (check_register
4918 && !operand_type_register_match (overlap1,
4919 i.types[1],
4920 operand_types[1],
4921 overlap2,
4922 i.types[2],
4923 operand_types[2])))
f48ff2ae
L		 4924 continue;
4925 break;
4926 }
29b0f896 4927 }
f48ff2ae 4928 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4929 slip through to break. */
4930 }
3629bb00 4931 if (!found_cpu_match)
29b0f896
AM		 4932 {
4933 found_reverse_match = 0;
4934 continue;
4935 }
c0f3af97 4936
5614d22c
JB		 4937 /* Check if vector and VEX operands are valid. */
4938 if (check_VecOperands (t) || VEX_check_operands (t))
4939 {
4940 specific_error = i.error;
4941 continue;
4942 }
a683cc34 4943
29b0f896
AM		 4944 /* We've found a match; break out of loop. */
4945 break;
4946 }
4947
4948 if (t == current_templates->end)
4949 {
4950 /* We found no match. */
a65babc9 4951 const char *err_msg;
5614d22c 4952 switch (specific_error ? specific_error : i.error)
a65babc9
L		 4953 {
4954 default:
4955 abort ();
86e026a4 4956 case operand_size_mismatch:
a65babc9
L		 4957 err_msg = _("operand size mismatch");
4958 break;
4959 case operand_type_mismatch:
4960 err_msg = _("operand type mismatch");
4961 break;
4962 case register_type_mismatch:
4963 err_msg = _("register type mismatch");
4964 break;
4965 case number_of_operands_mismatch:
4966 err_msg = _("number of operands mismatch");
4967 break;
4968 case invalid_instruction_suffix:
4969 err_msg = _("invalid instruction suffix");
4970 break;
4971 case bad_imm4:
4a2608e3 4972 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 4973 break;
4974 case old_gcc_only:
4975 err_msg = _("only supported with old gcc");
4976 break;
4977 case unsupported_with_intel_mnemonic:
4978 err_msg = _("unsupported with Intel mnemonic");
4979 break;
4980 case unsupported_syntax:
4981 err_msg = _("unsupported syntax");
4982 break;
4983 case unsupported:
35262a23 4984 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 4985 current_templates->start->name);
4986 return NULL;
6c30d220
L		 4987 case invalid_vsib_address:
4988 err_msg = _("invalid VSIB address");
4989 break;
7bab8ab5
JB		 4990 case invalid_vector_register_set:
4991 err_msg = _("mask, index, and destination registers must be distinct");
4992 break;
6c30d220
L		 4993 case unsupported_vector_index_register:
4994 err_msg = _("unsupported vector index register");
4995 break;
43234a1e
L		 4996 case unsupported_broadcast:
4997 err_msg = _("unsupported broadcast");
4998 break;
4999 case broadcast_not_on_src_operand:
5000 err_msg = _("broadcast not on source memory operand");
5001 break;
5002 case broadcast_needed:
5003 err_msg = _("broadcast is needed for operand of such type");
5004 break;
5005 case unsupported_masking:
5006 err_msg = _("unsupported masking");
5007 break;
5008 case mask_not_on_destination:
5009 err_msg = _("mask not on destination operand");
5010 break;
5011 case no_default_mask:
5012 err_msg = _("default mask isn't allowed");
5013 break;
5014 case unsupported_rc_sae:
5015 err_msg = _("unsupported static rounding/sae");
5016 break;
5017 case rc_sae_operand_not_last_imm:
5018 if (intel_syntax)
5019 err_msg = _("RC/SAE operand must precede immediate operands");
5020 else
5021 err_msg = _("RC/SAE operand must follow immediate operands");
5022 break;
5023 case invalid_register_operand:
5024 err_msg = _("invalid register operand");
5025 break;
a65babc9
L		 5026 }
5027 as_bad (_("%s for `%s'"), err_msg,
891edac4 5028 current_templates->start->name);
fa99fab2 5029 return NULL;
29b0f896 5030 }
252b5132 5031
29b0f896
AM		 5032 if (!quiet_warnings)
5033 {
5034 if (!intel_syntax
40fb9820
L		 5035 && (i.types[0].bitfield.jumpabsolute
5036 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5037 {
5038 as_warn (_("indirect %s without `*'"), t->name);
5039 }
5040
40fb9820
L		 5041 if (t->opcode_modifier.isprefix
5042 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5043 {
5044 /* Warn them that a data or address size prefix doesn't
5045 affect assembly of the next line of code. */
5046 as_warn (_("stand-alone `%s' prefix"), t->name);
5047 }
5048 }
5049
5050 /* Copy the template we found. */
5051 i.tm = *t;
539e75ad
L		 5052
5053 if (addr_prefix_disp != -1)
5054 i.tm.operand_types[addr_prefix_disp]
5055 = operand_types[addr_prefix_disp];
5056
29b0f896
AM		 5057 if (found_reverse_match)
5058 {
5059 /* If we found a reverse match we must alter the opcode
5060 direction bit. found_reverse_match holds bits to change
5061 (different for int & float insns). */
5062
5063 i.tm.base_opcode ^= found_reverse_match;
5064
539e75ad
L		 5065 i.tm.operand_types[0] = operand_types[1];
5066 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5067 }
5068
fa99fab2 5069 return t;
29b0f896
AM		 5070}
5071
5072static int
e3bb37b5 5073check_string (void)
29b0f896 5074{
40fb9820
L		 5075 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5076 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5077 {
5078 if (i.seg[0] != NULL && i.seg[0] != &es)
5079 {
a87af027 5080 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5081 i.tm.name,
a87af027
JB		 5082 mem_op + 1,
5083 register_prefix);
29b0f896
AM		 5084 return 0;
5085 }
5086 /* There's only ever one segment override allowed per instruction.
5087 This instruction possibly has a legal segment override on the
5088 second operand, so copy the segment to where non-string
5089 instructions store it, allowing common code. */
5090 i.seg[0] = i.seg[1];
5091 }
40fb9820 5092 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5093 {
5094 if (i.seg[1] != NULL && i.seg[1] != &es)
5095 {
a87af027 5096 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5097 i.tm.name,
a87af027
JB		 5098 mem_op + 2,
5099 register_prefix);
29b0f896
AM		 5100 return 0;
5101 }
5102 }
5103 return 1;
5104}
5105
5106static int
543613e9 5107process_suffix (void)
29b0f896
AM		 5108{
5109 /* If matched instruction specifies an explicit instruction mnemonic
5110 suffix, use it. */
40fb9820
L		 5111 if (i.tm.opcode_modifier.size16)
5112 i.suffix = WORD_MNEM_SUFFIX;
5113 else if (i.tm.opcode_modifier.size32)
5114 i.suffix = LONG_MNEM_SUFFIX;
5115 else if (i.tm.opcode_modifier.size64)
5116 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5117 else if (i.reg_operands)
5118 {
5119 /* If there's no instruction mnemonic suffix we try to invent one
5120 based on register operands. */
5121 if (!i.suffix)
5122 {
5123 /* We take i.suffix from the last register operand specified,
5124 Destination register type is more significant than source
381d071f
L		 5125 register type. crc32 in SSE4.2 prefers source register
5126 type. */
5127 if (i.tm.base_opcode == 0xf20f38f1)
5128 {
40fb9820
L		 5129 if (i.types[0].bitfield.reg16)
5130 i.suffix = WORD_MNEM_SUFFIX;
5131 else if (i.types[0].bitfield.reg32)
5132 i.suffix = LONG_MNEM_SUFFIX;
5133 else if (i.types[0].bitfield.reg64)
5134 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5135 }
9344ff29 5136 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5137 {
40fb9820 5138 if (i.types[0].bitfield.reg8)
20592a94
L		 5139 i.suffix = BYTE_MNEM_SUFFIX;
5140 }
381d071f
L		 5141
5142 if (!i.suffix)
5143 {
5144 int op;
5145
20592a94
L		 5146 if (i.tm.base_opcode == 0xf20f38f1
5147 || i.tm.base_opcode == 0xf20f38f0)
5148 {
5149 /* We have to know the operand size for crc32. */
5150 as_bad (_("ambiguous memory operand size for `%s`"),
5151 i.tm.name);
5152 return 0;
5153 }
5154
381d071f 5155 for (op = i.operands; --op >= 0;)
40fb9820 5156 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 5157 {
40fb9820
L		 5158 if (i.types[op].bitfield.reg8)
5159 {
5160 i.suffix = BYTE_MNEM_SUFFIX;
5161 break;
5162 }
5163 else if (i.types[op].bitfield.reg16)
5164 {
5165 i.suffix = WORD_MNEM_SUFFIX;
5166 break;
5167 }
5168 else if (i.types[op].bitfield.reg32)
5169 {
5170 i.suffix = LONG_MNEM_SUFFIX;
5171 break;
5172 }
5173 else if (i.types[op].bitfield.reg64)
5174 {
5175 i.suffix = QWORD_MNEM_SUFFIX;
5176 break;
5177 }
381d071f
L		 5178 }
5179 }
29b0f896
AM		 5180 }
5181 else if (i.suffix == BYTE_MNEM_SUFFIX)
5182 {
2eb952a4
L		 5183 if (intel_syntax
5184 && i.tm.opcode_modifier.ignoresize
5185 && i.tm.opcode_modifier.no_bsuf)
5186 i.suffix = 0;
5187 else if (!check_byte_reg ())
29b0f896
AM		 5188 return 0;
5189 }
5190 else if (i.suffix == LONG_MNEM_SUFFIX)
5191 {
2eb952a4
L		 5192 if (intel_syntax
5193 && i.tm.opcode_modifier.ignoresize
5194 && i.tm.opcode_modifier.no_lsuf)
5195 i.suffix = 0;
5196 else if (!check_long_reg ())
29b0f896
AM		 5197 return 0;
5198 }
5199 else if (i.suffix == QWORD_MNEM_SUFFIX)
5200 {
955e1e6a
L		 5201 if (intel_syntax
5202 && i.tm.opcode_modifier.ignoresize
5203 && i.tm.opcode_modifier.no_qsuf)
5204 i.suffix = 0;
5205 else if (!check_qword_reg ())
29b0f896
AM		 5206 return 0;
5207 }
5208 else if (i.suffix == WORD_MNEM_SUFFIX)
5209 {
2eb952a4
L		 5210 if (intel_syntax
5211 && i.tm.opcode_modifier.ignoresize
5212 && i.tm.opcode_modifier.no_wsuf)
5213 i.suffix = 0;
5214 else if (!check_word_reg ())
29b0f896
AM		 5215 return 0;
5216 }
c0f3af97 5217 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5218 || i.suffix == YMMWORD_MNEM_SUFFIX
5219 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5220 {
43234a1e 5221 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5222 should check if it is a valid suffix. */
5223 }
40fb9820 5224 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5225 /* Do nothing if the instruction is going to ignore the prefix. */
5226 ;
5227 else
5228 abort ();
5229 }
40fb9820 5230 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5231 && !i.suffix
5232 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5233 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5234 {
5235 i.suffix = stackop_size;
5236 }
9306ca4a
JB		 5237 else if (intel_syntax
5238 && !i.suffix
40fb9820
L		 5239 && (i.tm.operand_types[0].bitfield.jumpabsolute
5240 || i.tm.opcode_modifier.jumpbyte
5241 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5242 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5243 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5244 {
5245 switch (flag_code)
5246 {
5247 case CODE_64BIT:
40fb9820 5248 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5249 {
5250 i.suffix = QWORD_MNEM_SUFFIX;
5251 break;
5252 }
5253 case CODE_32BIT:
40fb9820 5254 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5255 i.suffix = LONG_MNEM_SUFFIX;
5256 break;
5257 case CODE_16BIT:
40fb9820 5258 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5259 i.suffix = WORD_MNEM_SUFFIX;
5260 break;
5261 }
5262 }
252b5132 5263
9306ca4a 5264 if (!i.suffix)
29b0f896 5265 {
9306ca4a
JB		 5266 if (!intel_syntax)
5267 {
40fb9820 5268 if (i.tm.opcode_modifier.w)
9306ca4a 5269 {
4eed87de
AM		 5270 as_bad (_("no instruction mnemonic suffix given and "
5271 "no register operands; can't size instruction"));
9306ca4a
JB		 5272 return 0;
5273 }
5274 }
5275 else
5276 {
40fb9820 5277 unsigned int suffixes;
7ab9ffdd 5278
40fb9820
L		 5279 suffixes = !i.tm.opcode_modifier.no_bsuf;
5280 if (!i.tm.opcode_modifier.no_wsuf)
5281 suffixes |= 1 << 1;
5282 if (!i.tm.opcode_modifier.no_lsuf)
5283 suffixes |= 1 << 2;
fc4adea1 5284 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5285 suffixes |= 1 << 3;
5286 if (!i.tm.opcode_modifier.no_ssuf)
5287 suffixes |= 1 << 4;
5288 if (!i.tm.opcode_modifier.no_qsuf)
5289 suffixes |= 1 << 5;
5290
5291 /* There are more than suffix matches. */
5292 if (i.tm.opcode_modifier.w
9306ca4a 5293 || ((suffixes & (suffixes - 1))
40fb9820
L		 5294 && !i.tm.opcode_modifier.defaultsize
5295 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5296 {
5297 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5298 return 0;
5299 }
5300 }
29b0f896 5301 }
252b5132 5302
9306ca4a
JB		 5303 /* Change the opcode based on the operand size given by i.suffix;
5304 We don't need to change things for byte insns. */
5305
582d5edd
L		 5306 if (i.suffix
5307 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5308 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5309 && i.suffix != YMMWORD_MNEM_SUFFIX
5310 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5311 {
5312 /* It's not a byte, select word/dword operation. */
40fb9820 5313 if (i.tm.opcode_modifier.w)
29b0f896 5314 {
40fb9820 5315 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5316 i.tm.base_opcode |= 8;
5317 else
5318 i.tm.base_opcode |= 1;
5319 }
0f3f3d8b 5320
29b0f896
AM		 5321 /* Now select between word & dword operations via the operand
5322 size prefix, except for instructions that will ignore this
5323 prefix anyway. */
ca61edf2 5324 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5325 {
ca61edf2
L		 5326 /* The address size override prefix changes the size of the
5327 first operand. */
40fb9820
L		 5328 if ((flag_code == CODE_32BIT
5329 && i.op->regs[0].reg_type.bitfield.reg16)
5330 || (flag_code != CODE_32BIT
5331 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 5332 if (!add_prefix (ADDR_PREFIX_OPCODE))
5333 return 0;
5334 }
5335 else if (i.suffix != QWORD_MNEM_SUFFIX
5336 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5337 && !i.tm.opcode_modifier.ignoresize
5338 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5339 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5340 || (flag_code == CODE_64BIT
40fb9820 5341 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5342 {
5343 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5344
40fb9820 5345 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5346 prefix = ADDR_PREFIX_OPCODE;
252b5132 5347
29b0f896
AM		 5348 if (!add_prefix (prefix))
5349 return 0;
24eab124 5350 }
252b5132 5351
29b0f896
AM		 5352 /* Set mode64 for an operand. */
5353 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5354 && flag_code == CODE_64BIT
40fb9820 5355 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5356 {
5357 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5358 need rex64. cmpxchg8b is also a special case. */
5359 if (! (i.operands == 2
5360 && i.tm.base_opcode == 0x90
5361 && i.tm.extension_opcode == None
0dfbf9d7
L		 5362 && operand_type_equal (&i.types [0], &acc64)
5363 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5364 && ! (i.operands == 1
5365 && i.tm.base_opcode == 0xfc7
5366 && i.tm.extension_opcode == 1
40fb9820
L		 5367 && !operand_type_check (i.types [0], reg)
5368 && operand_type_check (i.types [0], anymem)))
f6bee062 5369 i.rex |= REX_W;
46e883c5 5370 }
3e73aa7c 5371
29b0f896
AM		 5372 /* Size floating point instruction. */
5373 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5374 if (i.tm.opcode_modifier.floatmf)
543613e9 5375 i.tm.base_opcode ^= 4;
29b0f896 5376 }
7ecd2f8b 5377
29b0f896
AM		 5378 return 1;
5379}
3e73aa7c 5380
29b0f896 5381static int
543613e9 5382check_byte_reg (void)
29b0f896
AM		 5383{
5384 int op;
543613e9 5385
29b0f896
AM		 5386 for (op = i.operands; --op >= 0;)
5387 {
5388 /* If this is an eight bit register, it's OK. If it's the 16 or
5389 32 bit version of an eight bit register, we will just use the
5390 low portion, and that's OK too. */
40fb9820 5391 if (i.types[op].bitfield.reg8)
29b0f896
AM		 5392 continue;
5393
5a819eb9
JB		 5394 /* I/O port address operands are OK too. */
5395 if (i.tm.operand_types[op].bitfield.inoutportreg)
5396 continue;
5397
9344ff29
L		 5398 /* crc32 doesn't generate this warning. */
5399 if (i.tm.base_opcode == 0xf20f38f0)
5400 continue;
5401
40fb9820
L		 5402 if ((i.types[op].bitfield.reg16
5403 || i.types[op].bitfield.reg32
5404 || i.types[op].bitfield.reg64)
5a819eb9
JB		 5405 && i.op[op].regs->reg_num < 4
5406 /* Prohibit these changes in 64bit mode, since the lowering
5407 would be more complicated. */
5408 && flag_code != CODE_64BIT)
29b0f896 5409 {
29b0f896 5410#if REGISTER_WARNINGS
5a819eb9 5411 if (!quiet_warnings)
a540244d
L		 5412 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5413 register_prefix,
40fb9820 5414 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 5415 ? REGNAM_AL - REGNAM_AX
5416 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5417 register_prefix,
29b0f896
AM		 5418 i.op[op].regs->reg_name,
5419 i.suffix);
5420#endif
5421 continue;
5422 }
5423 /* Any other register is bad. */
40fb9820
L		 5424 if (i.types[op].bitfield.reg16
5425 || i.types[op].bitfield.reg32
5426 || i.types[op].bitfield.reg64
5427 || i.types[op].bitfield.regmmx
5428 || i.types[op].bitfield.regxmm
c0f3af97 5429 || i.types[op].bitfield.regymm
43234a1e 5430 || i.types[op].bitfield.regzmm
40fb9820
L		 5431 || i.types[op].bitfield.sreg2
5432 || i.types[op].bitfield.sreg3
5433 || i.types[op].bitfield.control
5434 || i.types[op].bitfield.debug
5435 || i.types[op].bitfield.test
5436 || i.types[op].bitfield.floatreg
5437 || i.types[op].bitfield.floatacc)
29b0f896 5438 {
a540244d
L		 5439 as_bad (_("`%s%s' not allowed with `%s%c'"),
5440 register_prefix,
29b0f896
AM		 5441 i.op[op].regs->reg_name,
5442 i.tm.name,
5443 i.suffix);
5444 return 0;
5445 }
5446 }
5447 return 1;
5448}
5449
5450static int
e3bb37b5 5451check_long_reg (void)
29b0f896
AM		 5452{
5453 int op;
5454
5455 for (op = i.operands; --op >= 0;)
5456 /* Reject eight bit registers, except where the template requires
5457 them. (eg. movzb) */
40fb9820
L		 5458 if (i.types[op].bitfield.reg8
5459 && (i.tm.operand_types[op].bitfield.reg16
5460 || i.tm.operand_types[op].bitfield.reg32
5461 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5462 {
a540244d
L		 5463 as_bad (_("`%s%s' not allowed with `%s%c'"),
5464 register_prefix,
29b0f896
AM		 5465 i.op[op].regs->reg_name,
5466 i.tm.name,
5467 i.suffix);
5468 return 0;
5469 }
e4630f71 5470 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5471 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5472 && i.types[op].bitfield.reg16
5473 && (i.tm.operand_types[op].bitfield.reg32
5474 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5475 {
5476 /* Prohibit these changes in the 64bit mode, since the
5477 lowering is more complicated. */
5478 if (flag_code == CODE_64BIT)
252b5132 5479 {
2b5d6a91 5480 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5481 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5482 i.suffix);
5483 return 0;
252b5132 5484 }
29b0f896 5485#if REGISTER_WARNINGS
cecf1424
JB		 5486 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5487 register_prefix,
5488 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5489 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5490#endif
252b5132 5491 }
e4630f71 5492 /* Warn if the r prefix on a general reg is present. */
40fb9820
L		 5493 else if (i.types[op].bitfield.reg64
5494 && (i.tm.operand_types[op].bitfield.reg32
5495 || i.tm.operand_types[op].bitfield.acc))
252b5132 5496 {
34828aad 5497 if (intel_syntax
ca61edf2 5498 && i.tm.opcode_modifier.toqword
40fb9820 5499 && !i.types[0].bitfield.regxmm)
34828aad 5500 {
ca61edf2 5501 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5502 i.suffix = QWORD_MNEM_SUFFIX;
5503 }
5504 else
5505 {
2b5d6a91 5506 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5507 register_prefix, i.op[op].regs->reg_name,
5508 i.suffix);
5509 return 0;
5510 }
29b0f896
AM		 5511 }
5512 return 1;
5513}
252b5132 5514
29b0f896 5515static int
e3bb37b5 5516check_qword_reg (void)
29b0f896
AM		 5517{
5518 int op;
252b5132 5519
29b0f896
AM		 5520 for (op = i.operands; --op >= 0; )
5521 /* Reject eight bit registers, except where the template requires
5522 them. (eg. movzb) */
40fb9820
L		 5523 if (i.types[op].bitfield.reg8
5524 && (i.tm.operand_types[op].bitfield.reg16
5525 || i.tm.operand_types[op].bitfield.reg32
5526 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5527 {
a540244d
L		 5528 as_bad (_("`%s%s' not allowed with `%s%c'"),
5529 register_prefix,
29b0f896
AM		 5530 i.op[op].regs->reg_name,
5531 i.tm.name,
5532 i.suffix);
5533 return 0;
5534 }
e4630f71 5535 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 5536 else if ((i.types[op].bitfield.reg16
5537 || i.types[op].bitfield.reg32)
5538 && (i.tm.operand_types[op].bitfield.reg32
5539 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5540 {
5541 /* Prohibit these changes in the 64bit mode, since the
5542 lowering is more complicated. */
34828aad 5543 if (intel_syntax
ca61edf2 5544 && i.tm.opcode_modifier.todword
40fb9820 5545 && !i.types[0].bitfield.regxmm)
34828aad 5546 {
ca61edf2 5547 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5548 i.suffix = LONG_MNEM_SUFFIX;
5549 }
5550 else
5551 {
2b5d6a91 5552 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5553 register_prefix, i.op[op].regs->reg_name,
5554 i.suffix);
5555 return 0;
5556 }
252b5132 5557 }
29b0f896
AM		 5558 return 1;
5559}
252b5132 5560
29b0f896 5561static int
e3bb37b5 5562check_word_reg (void)
29b0f896
AM		 5563{
5564 int op;
5565 for (op = i.operands; --op >= 0;)
5566 /* Reject eight bit registers, except where the template requires
5567 them. (eg. movzb) */
40fb9820
L		 5568 if (i.types[op].bitfield.reg8
5569 && (i.tm.operand_types[op].bitfield.reg16
5570 || i.tm.operand_types[op].bitfield.reg32
5571 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5572 {
a540244d
L		 5573 as_bad (_("`%s%s' not allowed with `%s%c'"),
5574 register_prefix,
29b0f896
AM		 5575 i.op[op].regs->reg_name,
5576 i.tm.name,
5577 i.suffix);
5578 return 0;
5579 }
e4630f71 5580 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5581 else if ((!quiet_warnings || flag_code == CODE_64BIT)
e4630f71
JB		 5582 && (i.types[op].bitfield.reg32
5583 || i.types[op].bitfield.reg64)
40fb9820
L		 5584 && (i.tm.operand_types[op].bitfield.reg16
5585 || i.tm.operand_types[op].bitfield.acc))
252b5132 5586 {
29b0f896
AM		 5587 /* Prohibit these changes in the 64bit mode, since the
5588 lowering is more complicated. */
5589 if (flag_code == CODE_64BIT)
252b5132 5590 {
2b5d6a91 5591 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5592 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5593 i.suffix);
5594 return 0;
252b5132 5595 }
29b0f896 5596#if REGISTER_WARNINGS
cecf1424
JB		 5597 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5598 register_prefix,
5599 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5600 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5601#endif
5602 }
5603 return 1;
5604}
252b5132 5605
29b0f896 5606static int
40fb9820 5607update_imm (unsigned int j)
29b0f896 5608{
bc0844ae 5609 i386_operand_type overlap = i.types[j];
40fb9820
L		 5610 if ((overlap.bitfield.imm8
5611 || overlap.bitfield.imm8s
5612 || overlap.bitfield.imm16
5613 || overlap.bitfield.imm32
5614 || overlap.bitfield.imm32s
5615 || overlap.bitfield.imm64)
0dfbf9d7
L		 5616 && !operand_type_equal (&overlap, &imm8)
5617 && !operand_type_equal (&overlap, &imm8s)
5618 && !operand_type_equal (&overlap, &imm16)
5619 && !operand_type_equal (&overlap, &imm32)
5620 && !operand_type_equal (&overlap, &imm32s)
5621 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5622 {
5623 if (i.suffix)
5624 {
40fb9820
L		 5625 i386_operand_type temp;
5626
0dfbf9d7 5627 operand_type_set (&temp, 0);
7ab9ffdd 5628 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5629 {
5630 temp.bitfield.imm8 = overlap.bitfield.imm8;
5631 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5632 }
5633 else if (i.suffix == WORD_MNEM_SUFFIX)
5634 temp.bitfield.imm16 = overlap.bitfield.imm16;
5635 else if (i.suffix == QWORD_MNEM_SUFFIX)
5636 {
5637 temp.bitfield.imm64 = overlap.bitfield.imm64;
5638 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5639 }
5640 else
5641 temp.bitfield.imm32 = overlap.bitfield.imm32;
5642 overlap = temp;
29b0f896 5643 }
0dfbf9d7
L		 5644 else if (operand_type_equal (&overlap, &imm16_32_32s)
5645 || operand_type_equal (&overlap, &imm16_32)
5646 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5647 {
40fb9820 5648 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5649 overlap = imm16;
40fb9820 5650 else
65da13b5 5651 overlap = imm32s;
29b0f896 5652 }
0dfbf9d7
L		 5653 if (!operand_type_equal (&overlap, &imm8)
5654 && !operand_type_equal (&overlap, &imm8s)
5655 && !operand_type_equal (&overlap, &imm16)
5656 && !operand_type_equal (&overlap, &imm32)
5657 && !operand_type_equal (&overlap, &imm32s)
5658 && !operand_type_equal (&overlap, &imm64))
29b0f896 5659 {
4eed87de
AM		 5660 as_bad (_("no instruction mnemonic suffix given; "
5661 "can't determine immediate size"));
29b0f896
AM		 5662 return 0;
5663 }
5664 }
40fb9820 5665 i.types[j] = overlap;
29b0f896 5666
40fb9820
L		 5667 return 1;
5668}
5669
5670static int
5671finalize_imm (void)
5672{
bc0844ae 5673 unsigned int j, n;
29b0f896 5674
bc0844ae
L		 5675 /* Update the first 2 immediate operands. */
5676 n = i.operands > 2 ? 2 : i.operands;
5677 if (n)
5678 {
5679 for (j = 0; j < n; j++)
5680 if (update_imm (j) == 0)
5681 return 0;
40fb9820 5682
bc0844ae
L		 5683 /* The 3rd operand can't be immediate operand. */
5684 gas_assert (operand_type_check (i.types[2], imm) == 0);
5685 }
29b0f896
AM		 5686
5687 return 1;
5688}
5689
c0f3af97
L		 5690static int
5691bad_implicit_operand (int xmm)
5692{
91d6fa6a
NC		 5693 const char *ireg = xmm ? "xmm0" : "ymm0";
5694
c0f3af97
L		 5695 if (intel_syntax)
5696 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5697 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5698 else
5699 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5700 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5701 return 0;
5702}
5703
29b0f896 5704static int
e3bb37b5 5705process_operands (void)
29b0f896
AM		 5706{
5707 /* Default segment register this instruction will use for memory
5708 accesses. 0 means unknown. This is only for optimizing out
5709 unnecessary segment overrides. */
5710 const seg_entry *default_seg = 0;
5711
2426c15f 5712 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5713 {
91d6fa6a
NC		 5714 unsigned int dupl = i.operands;
5715 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5716 unsigned int j;
5717
c0f3af97 5718 /* The destination must be an xmm register. */
9c2799c2 5719 gas_assert (i.reg_operands
91d6fa6a 5720 && MAX_OPERANDS > dupl
7ab9ffdd 5721 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5722
5723 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5724 {
c0f3af97 5725 /* The first operand is implicit and must be xmm0. */
9c2799c2 5726 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5727 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5728 return bad_implicit_operand (1);
5729
8cd7925b 5730 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5731 {
5732 /* Keep xmm0 for instructions with VEX prefix and 3
5733 sources. */
5734 goto duplicate;
5735 }
e2ec9d29 5736 else
c0f3af97
L		 5737 {
5738 /* We remove the first xmm0 and keep the number of
5739 operands unchanged, which in fact duplicates the
5740 destination. */
5741 for (j = 1; j < i.operands; j++)
5742 {
5743 i.op[j - 1] = i.op[j];
5744 i.types[j - 1] = i.types[j];
5745 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5746 }
5747 }
5748 }
5749 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5750 {
91d6fa6a 5751 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5752 && (i.tm.opcode_modifier.vexsources
5753 == VEX3SOURCES));
c0f3af97
L		 5754
5755 /* Add the implicit xmm0 for instructions with VEX prefix
5756 and 3 sources. */
5757 for (j = i.operands; j > 0; j--)
5758 {
5759 i.op[j] = i.op[j - 1];
5760 i.types[j] = i.types[j - 1];
5761 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5762 }
5763 i.op[0].regs
5764 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5765 i.types[0] = regxmm;
c0f3af97
L		 5766 i.tm.operand_types[0] = regxmm;
5767
5768 i.operands += 2;
5769 i.reg_operands += 2;
5770 i.tm.operands += 2;
5771
91d6fa6a 5772 dupl++;
c0f3af97 5773 dest++;
91d6fa6a
NC		 5774 i.op[dupl] = i.op[dest];
5775 i.types[dupl] = i.types[dest];
5776 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5777 }
c0f3af97
L		 5778 else
5779 {
5780duplicate:
5781 i.operands++;
5782 i.reg_operands++;
5783 i.tm.operands++;
5784
91d6fa6a
NC		 5785 i.op[dupl] = i.op[dest];
5786 i.types[dupl] = i.types[dest];
5787 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5788 }
5789
5790 if (i.tm.opcode_modifier.immext)
5791 process_immext ();
5792 }
5793 else if (i.tm.opcode_modifier.firstxmm0)
5794 {
5795 unsigned int j;
5796
43234a1e 5797 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
9c2799c2 5798 gas_assert (i.reg_operands
7ab9ffdd 5799 && (operand_type_equal (&i.types[0], &regxmm)
43234a1e
L		 5800 || operand_type_equal (&i.types[0], &regymm)
5801 || operand_type_equal (&i.types[0], &regzmm)));
4c692bc7 5802 if (register_number (i.op[0].regs) != 0)
c0f3af97 5803 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5804
5805 for (j = 1; j < i.operands; j++)
5806 {
5807 i.op[j - 1] = i.op[j];
5808 i.types[j - 1] = i.types[j];
5809
5810 /* We need to adjust fields in i.tm since they are used by
5811 build_modrm_byte. */
5812 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5813 }
5814
e2ec9d29
L		 5815 i.operands--;
5816 i.reg_operands--;
e2ec9d29
L		 5817 i.tm.operands--;
5818 }
5819 else if (i.tm.opcode_modifier.regkludge)
5820 {
5821 /* The imul $imm, %reg instruction is converted into
5822 imul $imm, %reg, %reg, and the clr %reg instruction
5823 is converted into xor %reg, %reg. */
5824
5825 unsigned int first_reg_op;
5826
5827 if (operand_type_check (i.types[0], reg))
5828 first_reg_op = 0;
5829 else
5830 first_reg_op = 1;
5831 /* Pretend we saw the extra register operand. */
9c2799c2 5832 gas_assert (i.reg_operands == 1
7ab9ffdd 5833 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5834 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5835 i.types[first_reg_op + 1] = i.types[first_reg_op];
5836 i.operands++;
5837 i.reg_operands++;
29b0f896
AM		 5838 }
5839
40fb9820 5840 if (i.tm.opcode_modifier.shortform)
29b0f896 5841 {
40fb9820
L		 5842 if (i.types[0].bitfield.sreg2
5843 || i.types[0].bitfield.sreg3)
29b0f896 5844 {
4eed87de
AM		 5845 if (i.tm.base_opcode == POP_SEG_SHORT
5846 && i.op[0].regs->reg_num == 1)
29b0f896 5847 {
a87af027 5848 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5849 return 0;
29b0f896 5850 }
4eed87de
AM		 5851 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5852 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5853 i.rex |= REX_B;
4eed87de
AM		 5854 }
5855 else
5856 {
7ab9ffdd 5857 /* The register or float register operand is in operand
85f10a01 5858 0 or 1. */
40fb9820 5859 unsigned int op;
7ab9ffdd
L		 5860
5861 if (i.types[0].bitfield.floatreg
5862 || operand_type_check (i.types[0], reg))
5863 op = 0;
5864 else
5865 op = 1;
4eed87de
AM		 5866 /* Register goes in low 3 bits of opcode. */
5867 i.tm.base_opcode |= i.op[op].regs->reg_num;
5868 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5869 i.rex |= REX_B;
40fb9820 5870 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5871 {
4eed87de
AM		 5872 /* Warn about some common errors, but press on regardless.
5873 The first case can be generated by gcc (<= 2.8.1). */
5874 if (i.operands == 2)
5875 {
5876 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5877 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5878 register_prefix, i.op[!intel_syntax].regs->reg_name,
5879 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5880 }
5881 else
5882 {
5883 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5884 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5885 register_prefix, i.op[0].regs->reg_name);
4eed87de 5886 }
29b0f896
AM		 5887 }
5888 }
5889 }
40fb9820 5890 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5891 {
5892 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5893 must be put into the modrm byte). Now, we make the modrm and
5894 index base bytes based on all the info we've collected. */
29b0f896
AM		 5895
5896 default_seg = build_modrm_byte ();
5897 }
8a2ed489 5898 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5899 {
5900 default_seg = &ds;
5901 }
40fb9820 5902 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5903 {
5904 /* For the string instructions that allow a segment override
5905 on one of their operands, the default segment is ds. */
5906 default_seg = &ds;
5907 }
5908
75178d9d
L		 5909 if (i.tm.base_opcode == 0x8d /* lea */
5910 && i.seg[0]
5911 && !quiet_warnings)
30123838 5912 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5913
5914 /* If a segment was explicitly specified, and the specified segment
5915 is not the default, use an opcode prefix to select it. If we
5916 never figured out what the default segment is, then default_seg
5917 will be zero at this point, and the specified segment prefix will
5918 always be used. */
29b0f896
AM		 5919 if ((i.seg[0]) && (i.seg[0] != default_seg))
5920 {
5921 if (!add_prefix (i.seg[0]->seg_prefix))
5922 return 0;
5923 }
5924 return 1;
5925}
5926
5927static const seg_entry *
e3bb37b5 5928build_modrm_byte (void)
29b0f896
AM		 5929{
5930 const seg_entry *default_seg = 0;
c0f3af97 5931 unsigned int source, dest;
8cd7925b 5932 int vex_3_sources;
c0f3af97
L		 5933
5934 /* The first operand of instructions with VEX prefix and 3 sources
5935 must be VEX_Imm4. */
8cd7925b 5936 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5937 if (vex_3_sources)
5938 {
91d6fa6a 5939 unsigned int nds, reg_slot;
4c2c6516 5940 expressionS *exp;
c0f3af97 5941
922d8de8 5942 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5943 && i.tm.opcode_modifier.immext)
5944 {
5945 dest = i.operands - 2;
5946 gas_assert (dest == 3);
5947 }
922d8de8 5948 else
a683cc34 5949 dest = i.operands - 1;
c0f3af97 5950 nds = dest - 1;
922d8de8 5951
a683cc34
SP		 5952 /* There are 2 kinds of instructions:
5953 1. 5 operands: 4 register operands or 3 register operands
5954 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 5955 VexW0 or VexW1. The destination must be either XMM, YMM or
5956 ZMM register.
a683cc34
SP		 5957 2. 4 operands: 4 register operands or 3 register operands
5958 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5959 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5960 || (i.reg_operands == 3 && i.mem_operands == 1))
5961 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5962 && (i.tm.opcode_modifier.veximmext
5963 || (i.imm_operands == 1
5964 && i.types[0].bitfield.vec_imm4
5965 && (i.tm.opcode_modifier.vexw == VEXW0
5966 || i.tm.opcode_modifier.vexw == VEXW1)
5967 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 5968 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
5969 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 5970
5971 if (i.imm_operands == 0)
5972 {
5973 /* When there is no immediate operand, generate an 8bit
5974 immediate operand to encode the first operand. */
5975 exp = &im_expressions[i.imm_operands++];
5976 i.op[i.operands].imms = exp;
5977 i.types[i.operands] = imm8;
5978 i.operands++;
5979 /* If VexW1 is set, the first operand is the source and
5980 the second operand is encoded in the immediate operand. */
5981 if (i.tm.opcode_modifier.vexw == VEXW1)
5982 {
5983 source = 0;
5984 reg_slot = 1;
5985 }
5986 else
5987 {
5988 source = 1;
5989 reg_slot = 0;
5990 }
5991
5992 /* FMA swaps REG and NDS. */
5993 if (i.tm.cpu_flags.bitfield.cpufma)
5994 {
5995 unsigned int tmp;
5996 tmp = reg_slot;
5997 reg_slot = nds;
5998 nds = tmp;
5999 }
6000
24981e7b
L		 6001 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6002 &regxmm)
a683cc34 6003 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6004 &regymm)
6005 || operand_type_equal (&i.tm.operand_types[reg_slot],
6006 &regzmm));
a683cc34 6007 exp->X_op = O_constant;
4c692bc7 6008 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6009 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6010 }
922d8de8 6011 else
a683cc34
SP		 6012 {
6013 unsigned int imm_slot;
6014
6015 if (i.tm.opcode_modifier.vexw == VEXW0)
6016 {
6017 /* If VexW0 is set, the third operand is the source and
6018 the second operand is encoded in the immediate
6019 operand. */
6020 source = 2;
6021 reg_slot = 1;
6022 }
6023 else
6024 {
6025 /* VexW1 is set, the second operand is the source and
6026 the third operand is encoded in the immediate
6027 operand. */
6028 source = 1;
6029 reg_slot = 2;
6030 }
6031
6032 if (i.tm.opcode_modifier.immext)
6033 {
6034 /* When ImmExt is set, the immdiate byte is the last
6035 operand. */
6036 imm_slot = i.operands - 1;
6037 source--;
6038 reg_slot--;
6039 }
6040 else
6041 {
6042 imm_slot = 0;
6043
6044 /* Turn on Imm8 so that output_imm will generate it. */
6045 i.types[imm_slot].bitfield.imm8 = 1;
6046 }
6047
24981e7b
L		 6048 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6049 &regxmm)
6050 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6051 &regymm)
6052 || operand_type_equal (&i.tm.operand_types[reg_slot],
6053 &regzmm));
a683cc34 6054 i.op[imm_slot].imms->X_add_number
4c692bc7 6055 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6056 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6057 }
6058
6059 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6060 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 6061 &regymm)
6062 || operand_type_equal (&i.tm.operand_types[nds],
6063 &regzmm));
dae39acc 6064 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6065 }
6066 else
6067 source = dest = 0;
29b0f896
AM		 6068
6069 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6070 implicit registers do not count. If there are 3 register
6071 operands, it must be a instruction with VexNDS. For a
6072 instruction with VexNDD, the destination register is encoded
6073 in VEX prefix. If there are 4 register operands, it must be
6074 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6075 if (i.mem_operands == 0
6076 && ((i.reg_operands == 2
2426c15f 6077 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6078 || (i.reg_operands == 3
2426c15f 6079 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6080 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6081 {
cab737b9
L		 6082 switch (i.operands)
6083 {
6084 case 2:
6085 source = 0;
6086 break;
6087 case 3:
c81128dc
L		 6088 /* When there are 3 operands, one of them may be immediate,
6089 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6090 the first operand must be shift count register (cl) or it
6091 is an instruction with VexNDS. */
9c2799c2 6092 gas_assert (i.imm_operands == 1
7ab9ffdd 6093 || (i.imm_operands == 0
2426c15f 6094 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6095 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6096 if (operand_type_check (i.types[0], imm)
6097 || i.types[0].bitfield.shiftcount)
6098 source = 1;
6099 else
6100 source = 0;
cab737b9
L		 6101 break;
6102 case 4:
368d64cc
L		 6103 /* When there are 4 operands, the first two must be 8bit
6104 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6105 one.
6106
6107 For instructions with VexNDS, if the first operand
6108 an imm8, the source operand is the 2nd one. If the last
6109 operand is imm8, the source operand is the first one. */
9c2799c2 6110 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6111 && i.types[0].bitfield.imm8
6112 && i.types[1].bitfield.imm8)
2426c15f 6113 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6114 && i.imm_operands == 1
6115 && (i.types[0].bitfield.imm8
43234a1e
L		 6116 || i.types[i.operands - 1].bitfield.imm8
6117 || i.rounding)));
9f2670f2
L		 6118 if (i.imm_operands == 2)
6119 source = 2;
6120 else
c0f3af97
L		 6121 {
6122 if (i.types[0].bitfield.imm8)
6123 source = 1;
6124 else
6125 source = 0;
6126 }
c0f3af97
L		 6127 break;
6128 case 5:
43234a1e
L		 6129 if (i.tm.opcode_modifier.evex)
6130 {
6131 /* For EVEX instructions, when there are 5 operands, the
6132 first one must be immediate operand. If the second one
6133 is immediate operand, the source operand is the 3th
6134 one. If the last one is immediate operand, the source
6135 operand is the 2nd one. */
6136 gas_assert (i.imm_operands == 2
6137 && i.tm.opcode_modifier.sae
6138 && operand_type_check (i.types[0], imm));
6139 if (operand_type_check (i.types[1], imm))
6140 source = 2;
6141 else if (operand_type_check (i.types[4], imm))
6142 source = 1;
6143 else
6144 abort ();
6145 }
cab737b9
L		 6146 break;
6147 default:
6148 abort ();
6149 }
6150
c0f3af97
L		 6151 if (!vex_3_sources)
6152 {
6153 dest = source + 1;
6154
43234a1e
L		 6155 /* RC/SAE operand could be between DEST and SRC. That happens
6156 when one operand is GPR and the other one is XMM/YMM/ZMM
6157 register. */
6158 if (i.rounding && i.rounding->operand == (int) dest)
6159 dest++;
6160
2426c15f 6161 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6162 {
43234a1e
L		 6163 /* For instructions with VexNDS, the register-only source
6164 operand must be 32/64bit integer, XMM, YMM or ZMM
6165 register. It is encoded in VEX prefix. We need to
6166 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6167
6168 i386_operand_type op;
6169 unsigned int vvvv;
6170
6171 /* Check register-only source operand when two source
6172 operands are swapped. */
6173 if (!i.tm.operand_types[source].bitfield.baseindex
6174 && i.tm.operand_types[dest].bitfield.baseindex)
6175 {
6176 vvvv = source;
6177 source = dest;
6178 }
6179 else
6180 vvvv = dest;
6181
6182 op = i.tm.operand_types[vvvv];
fa99fab2 6183 op.bitfield.regmem = 0;
c0f3af97 6184 if ((dest + 1) >= i.operands
ac4eb736
AM		 6185 || (!op.bitfield.reg32
6186 && op.bitfield.reg64
f12dc422 6187 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6188 && !operand_type_equal (&op, &regymm)
6189 && !operand_type_equal (&op, &regzmm)
6190 && !operand_type_equal (&op, &regmask)))
c0f3af97 6191 abort ();
f12dc422 6192 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6193 dest++;
6194 }
6195 }
29b0f896
AM		 6196
6197 i.rm.mode = 3;
6198 /* One of the register operands will be encoded in the i.tm.reg
6199 field, the other in the combined i.tm.mode and i.tm.regmem
6200 fields. If no form of this instruction supports a memory
6201 destination operand, then we assume the source operand may
6202 sometimes be a memory operand and so we need to store the
6203 destination in the i.rm.reg field. */
40fb9820
L		 6204 if (!i.tm.operand_types[dest].bitfield.regmem
6205 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6206 {
6207 i.rm.reg = i.op[dest].regs->reg_num;
6208 i.rm.regmem = i.op[source].regs->reg_num;
6209 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6210 i.rex |= REX_R;
43234a1e
L		 6211 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6212 i.vrex |= REX_R;
29b0f896 6213 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6214 i.rex |= REX_B;
43234a1e
L		 6215 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6216 i.vrex |= REX_B;
29b0f896
AM		 6217 }
6218 else
6219 {
6220 i.rm.reg = i.op[source].regs->reg_num;
6221 i.rm.regmem = i.op[dest].regs->reg_num;
6222 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6223 i.rex |= REX_B;
43234a1e
L		 6224 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6225 i.vrex |= REX_B;
29b0f896 6226 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6227 i.rex |= REX_R;
43234a1e
L		 6228 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6229 i.vrex |= REX_R;
29b0f896 6230 }
161a04f6 6231 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6232 {
40fb9820
L		 6233 if (!i.types[0].bitfield.control
6234 && !i.types[1].bitfield.control)
c4a530c5 6235 abort ();
161a04f6 6236 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6237 add_prefix (LOCK_PREFIX_OPCODE);
6238 }
29b0f896
AM		 6239 }
6240 else
6241 { /* If it's not 2 reg operands... */
c0f3af97
L		 6242 unsigned int mem;
6243
29b0f896
AM		 6244 if (i.mem_operands)
6245 {
6246 unsigned int fake_zero_displacement = 0;
99018f42 6247 unsigned int op;
4eed87de 6248
7ab9ffdd
L		 6249 for (op = 0; op < i.operands; op++)
6250 if (operand_type_check (i.types[op], anymem))
6251 break;
7ab9ffdd 6252 gas_assert (op < i.operands);
29b0f896 6253
6c30d220
L		 6254 if (i.tm.opcode_modifier.vecsib)
6255 {
6256 if (i.index_reg->reg_num == RegEiz
6257 || i.index_reg->reg_num == RegRiz)
6258 abort ();
6259
6260 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6261 if (!i.base_reg)
6262 {
6263 i.sib.base = NO_BASE_REGISTER;
6264 i.sib.scale = i.log2_scale_factor;
43234a1e
L		 6265 /* No Vec_Disp8 if there is no base. */
6266 i.types[op].bitfield.vec_disp8 = 0;
6c30d220
L		 6267 i.types[op].bitfield.disp8 = 0;
6268 i.types[op].bitfield.disp16 = 0;
6269 i.types[op].bitfield.disp64 = 0;
6270 if (flag_code != CODE_64BIT)
6271 {
6272 /* Must be 32 bit */
6273 i.types[op].bitfield.disp32 = 1;
6274 i.types[op].bitfield.disp32s = 0;
6275 }
6276 else
6277 {
6278 i.types[op].bitfield.disp32 = 0;
6279 i.types[op].bitfield.disp32s = 1;
6280 }
6281 }
6282 i.sib.index = i.index_reg->reg_num;
6283 if ((i.index_reg->reg_flags & RegRex) != 0)
6284 i.rex |= REX_X;
43234a1e
L		 6285 if ((i.index_reg->reg_flags & RegVRex) != 0)
6286 i.vrex |= REX_X;
6c30d220
L		 6287 }
6288
29b0f896
AM		 6289 default_seg = &ds;
6290
6291 if (i.base_reg == 0)
6292 {
6293 i.rm.mode = 0;
6294 if (!i.disp_operands)
6c30d220
L		 6295 {
6296 fake_zero_displacement = 1;
6297 /* Instructions with VSIB byte need 32bit displacement
6298 if there is no base register. */
6299 if (i.tm.opcode_modifier.vecsib)
6300 i.types[op].bitfield.disp32 = 1;
6301 }
29b0f896
AM		 6302 if (i.index_reg == 0)
6303 {
6c30d220 6304 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6305 /* Operand is just <disp> */
20f0a1fc 6306 if (flag_code == CODE_64BIT)
29b0f896
AM		 6307 {
6308 /* 64bit mode overwrites the 32bit absolute
6309 addressing by RIP relative addressing and
6310 absolute addressing is encoded by one of the
6311 redundant SIB forms. */
6312 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6313 i.sib.base = NO_BASE_REGISTER;
6314 i.sib.index = NO_INDEX_REGISTER;
fc225355 6315 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6316 ? disp32s : disp32);
20f0a1fc 6317 }
fc225355
L		 6318 else if ((flag_code == CODE_16BIT)
6319 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6320 {
6321 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6322 i.types[op] = disp16;
20f0a1fc
NC		 6323 }
6324 else
6325 {
6326 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6327 i.types[op] = disp32;
29b0f896
AM		 6328 }
6329 }
6c30d220 6330 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6331 {
6c30d220 6332 /* !i.base_reg && i.index_reg */
db51cc60
L		 6333 if (i.index_reg->reg_num == RegEiz
6334 || i.index_reg->reg_num == RegRiz)
6335 i.sib.index = NO_INDEX_REGISTER;
6336 else
6337 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6338 i.sib.base = NO_BASE_REGISTER;
6339 i.sib.scale = i.log2_scale_factor;
6340 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
43234a1e
L		 6341 /* No Vec_Disp8 if there is no base. */
6342 i.types[op].bitfield.vec_disp8 = 0;
40fb9820
L		 6343 i.types[op].bitfield.disp8 = 0;
6344 i.types[op].bitfield.disp16 = 0;
6345 i.types[op].bitfield.disp64 = 0;
29b0f896 6346 if (flag_code != CODE_64BIT)
40fb9820
L		 6347 {
6348 /* Must be 32 bit */
6349 i.types[op].bitfield.disp32 = 1;
6350 i.types[op].bitfield.disp32s = 0;
6351 }
29b0f896 6352 else
40fb9820
L		 6353 {
6354 i.types[op].bitfield.disp32 = 0;
6355 i.types[op].bitfield.disp32s = 1;
6356 }
29b0f896 6357 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6358 i.rex |= REX_X;
29b0f896
AM		 6359 }
6360 }
6361 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6362 else if (i.base_reg->reg_num == RegRip ||
6363 i.base_reg->reg_num == RegEip)
29b0f896 6364 {
6c30d220 6365 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6366 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6367 i.types[op].bitfield.disp8 = 0;
6368 i.types[op].bitfield.disp16 = 0;
6369 i.types[op].bitfield.disp32 = 0;
6370 i.types[op].bitfield.disp32s = 1;
6371 i.types[op].bitfield.disp64 = 0;
43234a1e 6372 i.types[op].bitfield.vec_disp8 = 0;
71903a11 6373 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6374 if (! i.disp_operands)
6375 fake_zero_displacement = 1;
29b0f896 6376 }
40fb9820 6377 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 6378 {
6c30d220 6379 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6380 switch (i.base_reg->reg_num)
6381 {
6382 case 3: /* (%bx) */
6383 if (i.index_reg == 0)
6384 i.rm.regmem = 7;
6385 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6386 i.rm.regmem = i.index_reg->reg_num - 6;
6387 break;
6388 case 5: /* (%bp) */
6389 default_seg = &ss;
6390 if (i.index_reg == 0)
6391 {
6392 i.rm.regmem = 6;
40fb9820 6393 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6394 {
6395 /* fake (%bp) into 0(%bp) */
43234a1e
L		 6396 if (i.tm.operand_types[op].bitfield.vec_disp8)
6397 i.types[op].bitfield.vec_disp8 = 1;
6398 else
6399 i.types[op].bitfield.disp8 = 1;
252b5132 6400 fake_zero_displacement = 1;
29b0f896
AM		 6401 }
6402 }
6403 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6404 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6405 break;
6406 default: /* (%si) -> 4 or (%di) -> 5 */
6407 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6408 }
6409 i.rm.mode = mode_from_disp_size (i.types[op]);
6410 }
6411 else /* i.base_reg and 32/64 bit mode */
6412 {
6413 if (flag_code == CODE_64BIT
40fb9820
L		 6414 && operand_type_check (i.types[op], disp))
6415 {
6416 i386_operand_type temp;
0dfbf9d7 6417 operand_type_set (&temp, 0);
40fb9820 6418 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
43234a1e
L		 6419 temp.bitfield.vec_disp8
6420 = i.types[op].bitfield.vec_disp8;
40fb9820
L		 6421 i.types[op] = temp;
6422 if (i.prefix[ADDR_PREFIX] == 0)
6423 i.types[op].bitfield.disp32s = 1;
6424 else
6425 i.types[op].bitfield.disp32 = 1;
6426 }
20f0a1fc 6427
6c30d220
L		 6428 if (!i.tm.opcode_modifier.vecsib)
6429 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6430 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6431 i.rex |= REX_B;
29b0f896
AM		 6432 i.sib.base = i.base_reg->reg_num;
6433 /* x86-64 ignores REX prefix bit here to avoid decoder
6434 complications. */
848930b2
JB		 6435 if (!(i.base_reg->reg_flags & RegRex)
6436 && (i.base_reg->reg_num == EBP_REG_NUM
6437 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6438 default_seg = &ss;
848930b2 6439 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6440 {
848930b2 6441 fake_zero_displacement = 1;
43234a1e
L		 6442 if (i.tm.operand_types [op].bitfield.vec_disp8)
6443 i.types[op].bitfield.vec_disp8 = 1;
6444 else
6445 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6446 }
6447 i.sib.scale = i.log2_scale_factor;
6448 if (i.index_reg == 0)
6449 {
6c30d220 6450 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6451 /* <disp>(%esp) becomes two byte modrm with no index
6452 register. We've already stored the code for esp
6453 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6454 Any base register besides %esp will not use the
6455 extra modrm byte. */
6456 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6457 }
6c30d220 6458 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6459 {
db51cc60
L		 6460 if (i.index_reg->reg_num == RegEiz
6461 || i.index_reg->reg_num == RegRiz)
6462 i.sib.index = NO_INDEX_REGISTER;
6463 else
6464 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6465 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6466 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6467 i.rex |= REX_X;
29b0f896 6468 }
67a4f2b7
AO		 6469
6470 if (i.disp_operands
6471 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6472 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6473 i.rm.mode = 0;
6474 else
a501d77e
L		 6475 {
6476 if (!fake_zero_displacement
6477 && !i.disp_operands
6478 && i.disp_encoding)
6479 {
6480 fake_zero_displacement = 1;
6481 if (i.disp_encoding == disp_encoding_8bit)
6482 i.types[op].bitfield.disp8 = 1;
6483 else
6484 i.types[op].bitfield.disp32 = 1;
6485 }
6486 i.rm.mode = mode_from_disp_size (i.types[op]);
6487 }
29b0f896 6488 }
252b5132 6489
29b0f896
AM		 6490 if (fake_zero_displacement)
6491 {
6492 /* Fakes a zero displacement assuming that i.types[op]
6493 holds the correct displacement size. */
6494 expressionS *exp;
6495
9c2799c2 6496 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6497 exp = &disp_expressions[i.disp_operands++];
6498 i.op[op].disps = exp;
6499 exp->X_op = O_constant;
6500 exp->X_add_number = 0;
6501 exp->X_add_symbol = (symbolS *) 0;
6502 exp->X_op_symbol = (symbolS *) 0;
6503 }
c0f3af97
L		 6504
6505 mem = op;
29b0f896 6506 }
c0f3af97
L		 6507 else
6508 mem = ~0;
252b5132 6509
8c43a48b 6510 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6511 {
6512 if (operand_type_check (i.types[0], imm))
6513 i.vex.register_specifier = NULL;
6514 else
6515 {
6516 /* VEX.vvvv encodes one of the sources when the first
6517 operand is not an immediate. */
1ef99a7b 6518 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6519 i.vex.register_specifier = i.op[0].regs;
6520 else
6521 i.vex.register_specifier = i.op[1].regs;
6522 }
6523
6524 /* Destination is a XMM register encoded in the ModRM.reg
6525 and VEX.R bit. */
6526 i.rm.reg = i.op[2].regs->reg_num;
6527 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6528 i.rex |= REX_R;
6529
6530 /* ModRM.rm and VEX.B encodes the other source. */
6531 if (!i.mem_operands)
6532 {
6533 i.rm.mode = 3;
6534
1ef99a7b 6535 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6536 i.rm.regmem = i.op[1].regs->reg_num;
6537 else
6538 i.rm.regmem = i.op[0].regs->reg_num;
6539
6540 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6541 i.rex |= REX_B;
6542 }
6543 }
2426c15f 6544 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6545 {
6546 i.vex.register_specifier = i.op[2].regs;
6547 if (!i.mem_operands)
6548 {
6549 i.rm.mode = 3;
6550 i.rm.regmem = i.op[1].regs->reg_num;
6551 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6552 i.rex |= REX_B;
6553 }
6554 }
29b0f896
AM		 6555 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6556 (if any) based on i.tm.extension_opcode. Again, we must be
6557 careful to make sure that segment/control/debug/test/MMX
6558 registers are coded into the i.rm.reg field. */
f88c9eb0 6559 else if (i.reg_operands)
29b0f896 6560 {
99018f42 6561 unsigned int op;
7ab9ffdd
L		 6562 unsigned int vex_reg = ~0;
6563
6564 for (op = 0; op < i.operands; op++)
6565 if (i.types[op].bitfield.reg8
6566 || i.types[op].bitfield.reg16
6567 || i.types[op].bitfield.reg32
6568 || i.types[op].bitfield.reg64
6569 || i.types[op].bitfield.regmmx
6570 || i.types[op].bitfield.regxmm
6571 || i.types[op].bitfield.regymm
7e8b059b 6572 || i.types[op].bitfield.regbnd
43234a1e
L		 6573 || i.types[op].bitfield.regzmm
6574 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6575 || i.types[op].bitfield.sreg2
6576 || i.types[op].bitfield.sreg3
6577 || i.types[op].bitfield.control
6578 || i.types[op].bitfield.debug
6579 || i.types[op].bitfield.test)
6580 break;
c0209578 6581
7ab9ffdd
L		 6582 if (vex_3_sources)
6583 op = dest;
2426c15f 6584 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6585 {
6586 /* For instructions with VexNDS, the register-only
6587 source operand is encoded in VEX prefix. */
6588 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6589
7ab9ffdd 6590 if (op > mem)
c0f3af97 6591 {
7ab9ffdd
L		 6592 vex_reg = op++;
6593 gas_assert (op < i.operands);
c0f3af97
L		 6594 }
6595 else
c0f3af97 6596 {
f12dc422
L		 6597 /* Check register-only source operand when two source
6598 operands are swapped. */
6599 if (!i.tm.operand_types[op].bitfield.baseindex
6600 && i.tm.operand_types[op + 1].bitfield.baseindex)
6601 {
6602 vex_reg = op;
6603 op += 2;
6604 gas_assert (mem == (vex_reg + 1)
6605 && op < i.operands);
6606 }
6607 else
6608 {
6609 vex_reg = op + 1;
6610 gas_assert (vex_reg < i.operands);
6611 }
c0f3af97 6612 }
7ab9ffdd 6613 }
2426c15f 6614 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6615 {
f12dc422 6616 /* For instructions with VexNDD, the register destination
7ab9ffdd 6617 is encoded in VEX prefix. */
f12dc422
L		 6618 if (i.mem_operands == 0)
6619 {
6620 /* There is no memory operand. */
6621 gas_assert ((op + 2) == i.operands);
6622 vex_reg = op + 1;
6623 }
6624 else
8d63c93e 6625 {
f12dc422
L		 6626 /* There are only 2 operands. */
6627 gas_assert (op < 2 && i.operands == 2);
6628 vex_reg = 1;
6629 }
7ab9ffdd
L		 6630 }
6631 else
6632 gas_assert (op < i.operands);
99018f42 6633
7ab9ffdd
L		 6634 if (vex_reg != (unsigned int) ~0)
6635 {
f12dc422 6636 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6637
f12dc422
L		 6638 if (type->bitfield.reg32 != 1
6639 && type->bitfield.reg64 != 1
6640 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6641 && !operand_type_equal (type, &regymm)
6642 && !operand_type_equal (type, &regzmm)
6643 && !operand_type_equal (type, &regmask))
7ab9ffdd 6644 abort ();
f88c9eb0 6645
7ab9ffdd
L		 6646 i.vex.register_specifier = i.op[vex_reg].regs;
6647 }
6648
1b9f0c97
L		 6649 /* Don't set OP operand twice. */
6650 if (vex_reg != op)
7ab9ffdd 6651 {
1b9f0c97
L		 6652 /* If there is an extension opcode to put here, the
6653 register number must be put into the regmem field. */
6654 if (i.tm.extension_opcode != None)
6655 {
6656 i.rm.regmem = i.op[op].regs->reg_num;
6657 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6658 i.rex |= REX_B;
43234a1e
L		 6659 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6660 i.vrex |= REX_B;
1b9f0c97
L		 6661 }
6662 else
6663 {
6664 i.rm.reg = i.op[op].regs->reg_num;
6665 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6666 i.rex |= REX_R;
43234a1e
L		 6667 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6668 i.vrex |= REX_R;
1b9f0c97 6669 }
7ab9ffdd 6670 }
252b5132 6671
29b0f896
AM		 6672 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6673 must set it to 3 to indicate this is a register operand
6674 in the regmem field. */
6675 if (!i.mem_operands)
6676 i.rm.mode = 3;
6677 }
252b5132 6678
29b0f896 6679 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6680 if (i.tm.extension_opcode != None)
29b0f896
AM		 6681 i.rm.reg = i.tm.extension_opcode;
6682 }
6683 return default_seg;
6684}
252b5132 6685
29b0f896 6686static void
e3bb37b5 6687output_branch (void)
29b0f896
AM		 6688{
6689 char *p;
f8a5c266 6690 int size;
29b0f896
AM		 6691 int code16;
6692 int prefix;
6693 relax_substateT subtype;
6694 symbolS *sym;
6695 offsetT off;
6696
f8a5c266 6697 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6698 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6699
6700 prefix = 0;
6701 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6702 {
29b0f896
AM		 6703 prefix = 1;
6704 i.prefixes -= 1;
6705 code16 ^= CODE16;
252b5132 6706 }
29b0f896
AM		 6707 /* Pentium4 branch hints. */
6708 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6709 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6710 {
29b0f896
AM		 6711 prefix++;
6712 i.prefixes--;
6713 }
6714 if (i.prefix[REX_PREFIX] != 0)
6715 {
6716 prefix++;
6717 i.prefixes--;
2f66722d
AM		 6718 }
6719
7e8b059b
L		 6720 /* BND prefixed jump. */
6721 if (i.prefix[BND_PREFIX] != 0)
6722 {
6723 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6724 i.prefixes -= 1;
6725 }
6726
29b0f896
AM		 6727 if (i.prefixes != 0 && !intel_syntax)
6728 as_warn (_("skipping prefixes on this instruction"));
6729
6730 /* It's always a symbol; End frag & setup for relax.
6731 Make sure there is enough room in this frag for the largest
6732 instruction we may generate in md_convert_frag. This is 2
6733 bytes for the opcode and room for the prefix and largest
6734 displacement. */
6735 frag_grow (prefix + 2 + 4);
6736 /* Prefix and 1 opcode byte go in fr_fix. */
6737 p = frag_more (prefix + 1);
6738 if (i.prefix[DATA_PREFIX] != 0)
6739 *p++ = DATA_PREFIX_OPCODE;
6740 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6741 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6742 *p++ = i.prefix[SEG_PREFIX];
6743 if (i.prefix[REX_PREFIX] != 0)
6744 *p++ = i.prefix[REX_PREFIX];
6745 *p = i.tm.base_opcode;
6746
6747 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6748 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6749 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6750 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6751 else
f8a5c266 6752 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 6753 subtype |= code16;
3e73aa7c 6754
29b0f896
AM		 6755 sym = i.op[0].disps->X_add_symbol;
6756 off = i.op[0].disps->X_add_number;
3e73aa7c 6757
29b0f896
AM		 6758 if (i.op[0].disps->X_op != O_constant
6759 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 6760 {
29b0f896
AM		 6761 /* Handle complex expressions. */
6762 sym = make_expr_symbol (i.op[0].disps);
6763 off = 0;
6764 }
3e73aa7c 6765
29b0f896
AM		 6766 /* 1 possible extra opcode + 4 byte displacement go in var part.
6767 Pass reloc in fr_var. */
d258b828 6768 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 6769}
3e73aa7c 6770
29b0f896 6771static void
e3bb37b5 6772output_jump (void)
29b0f896
AM		 6773{
6774 char *p;
6775 int size;
3e02c1cc 6776 fixS *fixP;
29b0f896 6777
40fb9820 6778 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 6779 {
6780 /* This is a loop or jecxz type instruction. */
6781 size = 1;
6782 if (i.prefix[ADDR_PREFIX] != 0)
6783 {
6784 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6785 i.prefixes -= 1;
6786 }
6787 /* Pentium4 branch hints. */
6788 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6789 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6790 {
6791 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6792 i.prefixes--;
3e73aa7c
JH		 6793 }
6794 }
29b0f896
AM		 6795 else
6796 {
6797 int code16;
3e73aa7c 6798
29b0f896
AM		 6799 code16 = 0;
6800 if (flag_code == CODE_16BIT)
6801 code16 = CODE16;
3e73aa7c 6802
29b0f896
AM		 6803 if (i.prefix[DATA_PREFIX] != 0)
6804 {
6805 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6806 i.prefixes -= 1;
6807 code16 ^= CODE16;
6808 }
252b5132 6809
29b0f896
AM		 6810 size = 4;
6811 if (code16)
6812 size = 2;
6813 }
9fcc94b6 6814
29b0f896
AM		 6815 if (i.prefix[REX_PREFIX] != 0)
6816 {
6817 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6818 i.prefixes -= 1;
6819 }
252b5132 6820
7e8b059b
L		 6821 /* BND prefixed jump. */
6822 if (i.prefix[BND_PREFIX] != 0)
6823 {
6824 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6825 i.prefixes -= 1;
6826 }
6827
29b0f896
AM		 6828 if (i.prefixes != 0 && !intel_syntax)
6829 as_warn (_("skipping prefixes on this instruction"));
e0890092 6830
42164a71
L		 6831 p = frag_more (i.tm.opcode_length + size);
6832 switch (i.tm.opcode_length)
6833 {
6834 case 2:
6835 *p++ = i.tm.base_opcode >> 8;
6836 case 1:
6837 *p++ = i.tm.base_opcode;
6838 break;
6839 default:
6840 abort ();
6841 }
e0890092 6842
3e02c1cc 6843 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 6844 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3e02c1cc
AM		 6845
6846 /* All jumps handled here are signed, but don't use a signed limit
6847 check for 32 and 16 bit jumps as we want to allow wrap around at
6848 4G and 64k respectively. */
6849 if (size == 1)
6850 fixP->fx_signed = 1;
29b0f896 6851}
e0890092 6852
29b0f896 6853static void
e3bb37b5 6854output_interseg_jump (void)
29b0f896
AM		 6855{
6856 char *p;
6857 int size;
6858 int prefix;
6859 int code16;
252b5132 6860
29b0f896
AM		 6861 code16 = 0;
6862 if (flag_code == CODE_16BIT)
6863 code16 = CODE16;
a217f122 6864
29b0f896
AM		 6865 prefix = 0;
6866 if (i.prefix[DATA_PREFIX] != 0)
6867 {
6868 prefix = 1;
6869 i.prefixes -= 1;
6870 code16 ^= CODE16;
6871 }
6872 if (i.prefix[REX_PREFIX] != 0)
6873 {
6874 prefix++;
6875 i.prefixes -= 1;
6876 }
252b5132 6877
29b0f896
AM		 6878 size = 4;
6879 if (code16)
6880 size = 2;
252b5132 6881
29b0f896
AM		 6882 if (i.prefixes != 0 && !intel_syntax)
6883 as_warn (_("skipping prefixes on this instruction"));
252b5132 6884
29b0f896
AM		 6885 /* 1 opcode; 2 segment; offset */
6886 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 6887
29b0f896
AM		 6888 if (i.prefix[DATA_PREFIX] != 0)
6889 *p++ = DATA_PREFIX_OPCODE;
252b5132 6890
29b0f896
AM		 6891 if (i.prefix[REX_PREFIX] != 0)
6892 *p++ = i.prefix[REX_PREFIX];
252b5132 6893
29b0f896
AM		 6894 *p++ = i.tm.base_opcode;
6895 if (i.op[1].imms->X_op == O_constant)
6896 {
6897 offsetT n = i.op[1].imms->X_add_number;
252b5132 6898
29b0f896
AM		 6899 if (size == 2
6900 && !fits_in_unsigned_word (n)
6901 && !fits_in_signed_word (n))
6902 {
6903 as_bad (_("16-bit jump out of range"));
6904 return;
6905 }
6906 md_number_to_chars (p, n, size);
6907 }
6908 else
6909 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 6910 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 6911 if (i.op[0].imms->X_op != O_constant)
6912 as_bad (_("can't handle non absolute segment in `%s'"),
6913 i.tm.name);
6914 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6915}
a217f122 6916
29b0f896 6917static void
e3bb37b5 6918output_insn (void)
29b0f896 6919{
2bbd9c25
JJ		 6920 fragS *insn_start_frag;
6921 offsetT insn_start_off;
6922
29b0f896
AM		 6923 /* Tie dwarf2 debug info to the address at the start of the insn.
6924 We can't do this after the insn has been output as the current
6925 frag may have been closed off. eg. by frag_var. */
6926 dwarf2_emit_insn (0);
6927
2bbd9c25
JJ		 6928 insn_start_frag = frag_now;
6929 insn_start_off = frag_now_fix ();
6930
29b0f896 6931 /* Output jumps. */
40fb9820 6932 if (i.tm.opcode_modifier.jump)
29b0f896 6933 output_branch ();
40fb9820
L		 6934 else if (i.tm.opcode_modifier.jumpbyte
6935 || i.tm.opcode_modifier.jumpdword)
29b0f896 6936 output_jump ();
40fb9820 6937 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 6938 output_interseg_jump ();
6939 else
6940 {
6941 /* Output normal instructions here. */
6942 char *p;
6943 unsigned char *q;
47465058 6944 unsigned int j;
331d2d0d 6945 unsigned int prefix;
4dffcebc 6946
d022bddd
IT		 6947 /* Some processors fail on LOCK prefix. This options makes
6948 assembler ignore LOCK prefix and serves as a workaround. */
6949 if (omit_lock_prefix)
6950 {
6951 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
6952 return;
6953 i.prefix[LOCK_PREFIX] = 0;
6954 }
6955
43234a1e
L		 6956 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6957 don't need the explicit prefix. */
6958 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 6959 {
c0f3af97 6960 switch (i.tm.opcode_length)
bc4bd9ab 6961 {
c0f3af97
L		 6962 case 3:
6963 if (i.tm.base_opcode & 0xff000000)
4dffcebc 6964 {
c0f3af97
L		 6965 prefix = (i.tm.base_opcode >> 24) & 0xff;
6966 goto check_prefix;
6967 }
6968 break;
6969 case 2:
6970 if ((i.tm.base_opcode & 0xff0000) != 0)
6971 {
6972 prefix = (i.tm.base_opcode >> 16) & 0xff;
6973 if (i.tm.cpu_flags.bitfield.cpupadlock)
6974 {
4dffcebc 6975check_prefix:
c0f3af97 6976 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 6977 || (i.prefix[REP_PREFIX]
c0f3af97
L		 6978 != REPE_PREFIX_OPCODE))
6979 add_prefix (prefix);
6980 }
6981 else
4dffcebc
L		 6982 add_prefix (prefix);
6983 }
c0f3af97
L		 6984 break;
6985 case 1:
6986 break;
6987 default:
6988 abort ();
bc4bd9ab 6989 }
c0f3af97 6990
6d19a37a 6991#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 6992 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
6993 R_X86_64_GOTTPOFF relocation so that linker can safely
6994 perform IE->LE optimization. */
6995 if (x86_elf_abi == X86_64_X32_ABI
6996 && i.operands == 2
6997 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
6998 && i.prefix[REX_PREFIX] == 0)
6999 add_prefix (REX_OPCODE);
6d19a37a 7000#endif
cf61b747 7001
c0f3af97
L		 7002 /* The prefix bytes. */
7003 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7004 if (*q)
7005 FRAG_APPEND_1_CHAR (*q);
0f10071e 7006 }
ae5c1c7b 7007 else
c0f3af97
L		 7008 {
7009 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7010 if (*q)
7011 switch (j)
7012 {
7013 case REX_PREFIX:
7014 /* REX byte is encoded in VEX prefix. */
7015 break;
7016 case SEG_PREFIX:
7017 case ADDR_PREFIX:
7018 FRAG_APPEND_1_CHAR (*q);
7019 break;
7020 default:
7021 /* There should be no other prefixes for instructions
7022 with VEX prefix. */
7023 abort ();
7024 }
7025
43234a1e
L		 7026 /* For EVEX instructions i.vrex should become 0 after
7027 build_evex_prefix. For VEX instructions upper 16 registers
7028 aren't available, so VREX should be 0. */
7029 if (i.vrex)
7030 abort ();
c0f3af97
L		 7031 /* Now the VEX prefix. */
7032 p = frag_more (i.vex.length);
7033 for (j = 0; j < i.vex.length; j++)
7034 p[j] = i.vex.bytes[j];
7035 }
252b5132 7036
29b0f896 7037 /* Now the opcode; be careful about word order here! */
4dffcebc 7038 if (i.tm.opcode_length == 1)
29b0f896
AM		 7039 {
7040 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7041 }
7042 else
7043 {
4dffcebc 7044 switch (i.tm.opcode_length)
331d2d0d 7045 {
43234a1e
L		 7046 case 4:
7047 p = frag_more (4);
7048 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7049 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7050 break;
4dffcebc 7051 case 3:
331d2d0d
L		 7052 p = frag_more (3);
7053 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7054 break;
7055 case 2:
7056 p = frag_more (2);
7057 break;
7058 default:
7059 abort ();
7060 break;
331d2d0d 7061 }
0f10071e 7062
29b0f896
AM		 7063 /* Put out high byte first: can't use md_number_to_chars! */
7064 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7065 *p = i.tm.base_opcode & 0xff;
7066 }
3e73aa7c 7067
29b0f896 7068 /* Now the modrm byte and sib byte (if present). */
40fb9820 7069 if (i.tm.opcode_modifier.modrm)
29b0f896 7070 {
4a3523fa
L		 7071 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7072 | i.rm.reg << 3
7073 | i.rm.mode << 6));
29b0f896
AM		 7074 /* If i.rm.regmem == ESP (4)
7075 && i.rm.mode != (Register mode)
7076 && not 16 bit
7077 ==> need second modrm byte. */
7078 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7079 && i.rm.mode != 3
40fb9820 7080 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 7081 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7082 | i.sib.index << 3
7083 | i.sib.scale << 6));
29b0f896 7084 }
3e73aa7c 7085
29b0f896 7086 if (i.disp_operands)
2bbd9c25 7087 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7088
29b0f896 7089 if (i.imm_operands)
2bbd9c25 7090 output_imm (insn_start_frag, insn_start_off);
29b0f896 7091 }
252b5132 7092
29b0f896
AM		 7093#ifdef DEBUG386
7094 if (flag_debug)
7095 {
7b81dfbb 7096 pi ("" /*line*/, &i);
29b0f896
AM		 7097 }
7098#endif /* DEBUG386 */
7099}
252b5132 7100
e205caa7
L		 7101/* Return the size of the displacement operand N. */
7102
7103static int
7104disp_size (unsigned int n)
7105{
7106 int size = 4;
43234a1e
L		 7107
7108 /* Vec_Disp8 has to be 8bit. */
7109 if (i.types[n].bitfield.vec_disp8)
7110 size = 1;
7111 else if (i.types[n].bitfield.disp64)
40fb9820
L		 7112 size = 8;
7113 else if (i.types[n].bitfield.disp8)
7114 size = 1;
7115 else if (i.types[n].bitfield.disp16)
7116 size = 2;
e205caa7
L		 7117 return size;
7118}
7119
7120/* Return the size of the immediate operand N. */
7121
7122static int
7123imm_size (unsigned int n)
7124{
7125 int size = 4;
40fb9820
L		 7126 if (i.types[n].bitfield.imm64)
7127 size = 8;
7128 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7129 size = 1;
7130 else if (i.types[n].bitfield.imm16)
7131 size = 2;
e205caa7
L		 7132 return size;
7133}
7134
29b0f896 7135static void
64e74474 7136output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7137{
7138 char *p;
7139 unsigned int n;
252b5132 7140
29b0f896
AM		 7141 for (n = 0; n < i.operands; n++)
7142 {
43234a1e
L		 7143 if (i.types[n].bitfield.vec_disp8
7144 || operand_type_check (i.types[n], disp))
29b0f896
AM		 7145 {
7146 if (i.op[n].disps->X_op == O_constant)
7147 {
e205caa7 7148 int size = disp_size (n);
43234a1e 7149 offsetT val = i.op[n].disps->X_add_number;
252b5132 7150
43234a1e
L		 7151 if (i.types[n].bitfield.vec_disp8)
7152 val >>= i.memshift;
7153 val = offset_in_range (val, size);
29b0f896
AM		 7154 p = frag_more (size);
7155 md_number_to_chars (p, val, size);
7156 }
7157 else
7158 {
f86103b7 7159 enum bfd_reloc_code_real reloc_type;
e205caa7 7160 int size = disp_size (n);
40fb9820 7161 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 7162 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7163
e205caa7 7164 /* We can't have 8 bit displacement here. */
9c2799c2 7165 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7166
29b0f896
AM		 7167 /* The PC relative address is computed relative
7168 to the instruction boundary, so in case immediate
7169 fields follows, we need to adjust the value. */
7170 if (pcrel && i.imm_operands)
7171 {
29b0f896 7172 unsigned int n1;
e205caa7 7173 int sz = 0;
252b5132 7174
29b0f896 7175 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7176 if (operand_type_check (i.types[n1], imm))
252b5132 7177 {
e205caa7
L		 7178 /* Only one immediate is allowed for PC
7179 relative address. */
9c2799c2 7180 gas_assert (sz == 0);
e205caa7
L		 7181 sz = imm_size (n1);
7182 i.op[n].disps->X_add_number -= sz;
252b5132 7183 }
29b0f896 7184 /* We should find the immediate. */
9c2799c2 7185 gas_assert (sz != 0);
29b0f896 7186 }
520dc8e8 7187
29b0f896 7188 p = frag_more (size);
d258b828 7189 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7190 if (GOT_symbol
2bbd9c25 7191 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7192 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7193 || reloc_type == BFD_RELOC_X86_64_32S
7194 || (reloc_type == BFD_RELOC_64
7195 && object_64bit))
d6ab8113
JB		 7196 && (i.op[n].disps->X_op == O_symbol
7197 || (i.op[n].disps->X_op == O_add
7198 && ((symbol_get_value_expression
7199 (i.op[n].disps->X_op_symbol)->X_op)
7200 == O_subtract))))
7201 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7202 {
7203 offsetT add;
7204
7205 if (insn_start_frag == frag_now)
7206 add = (p - frag_now->fr_literal) - insn_start_off;
7207 else
7208 {
7209 fragS *fr;
7210
7211 add = insn_start_frag->fr_fix - insn_start_off;
7212 for (fr = insn_start_frag->fr_next;
7213 fr && fr != frag_now; fr = fr->fr_next)
7214 add += fr->fr_fix;
7215 add += p - frag_now->fr_literal;
7216 }
7217
4fa24527 7218 if (!object_64bit)
7b81dfbb
AJ		 7219 {
7220 reloc_type = BFD_RELOC_386_GOTPC;
7221 i.op[n].imms->X_add_number += add;
7222 }
7223 else if (reloc_type == BFD_RELOC_64)
7224 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7225 else
7b81dfbb
AJ		 7226 /* Don't do the adjustment for x86-64, as there
7227 the pcrel addressing is relative to the _next_
7228 insn, and that is taken care of in other code. */
d6ab8113 7229 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7230 }
062cd5e7 7231 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 7232 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 7233 }
7234 }
7235 }
7236}
252b5132 7237
29b0f896 7238static void
64e74474 7239output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7240{
7241 char *p;
7242 unsigned int n;
252b5132 7243
29b0f896
AM		 7244 for (n = 0; n < i.operands; n++)
7245 {
43234a1e
L		 7246 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7247 if (i.rounding && (int) n == i.rounding->operand)
7248 continue;
7249
40fb9820 7250 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7251 {
7252 if (i.op[n].imms->X_op == O_constant)
7253 {
e205caa7 7254 int size = imm_size (n);
29b0f896 7255 offsetT val;
b4cac588 7256
29b0f896
AM		 7257 val = offset_in_range (i.op[n].imms->X_add_number,
7258 size);
7259 p = frag_more (size);
7260 md_number_to_chars (p, val, size);
7261 }
7262 else
7263 {
7264 /* Not absolute_section.
7265 Need a 32-bit fixup (don't support 8bit
7266 non-absolute imms). Try to support other
7267 sizes ... */
f86103b7 7268 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7269 int size = imm_size (n);
7270 int sign;
29b0f896 7271
40fb9820 7272 if (i.types[n].bitfield.imm32s
a7d61044 7273 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7274 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7275 sign = 1;
e205caa7
L		 7276 else
7277 sign = 0;
520dc8e8 7278
29b0f896 7279 p = frag_more (size);
d258b828 7280 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 7281
2bbd9c25
JJ		 7282 /* This is tough to explain. We end up with this one if we
7283 * have operands that look like
7284 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7285 * obtain the absolute address of the GOT, and it is strongly
7286 * preferable from a performance point of view to avoid using
7287 * a runtime relocation for this. The actual sequence of
7288 * instructions often look something like:
7289 *
7290 * call .L66
7291 * .L66:
7292 * popl %ebx
7293 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7294 *
7295 * The call and pop essentially return the absolute address
7296 * of the label .L66 and store it in %ebx. The linker itself
7297 * will ultimately change the first operand of the addl so
7298 * that %ebx points to the GOT, but to keep things simple, the
7299 * .o file must have this operand set so that it generates not
7300 * the absolute address of .L66, but the absolute address of
7301 * itself. This allows the linker itself simply treat a GOTPC
7302 * relocation as asking for a pcrel offset to the GOT to be
7303 * added in, and the addend of the relocation is stored in the
7304 * operand field for the instruction itself.
7305 *
7306 * Our job here is to fix the operand so that it would add
7307 * the correct offset so that %ebx would point to itself. The
7308 * thing that is tricky is that .-.L66 will point to the
7309 * beginning of the instruction, so we need to further modify
7310 * the operand so that it will point to itself. There are
7311 * other cases where you have something like:
7312 *
7313 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7314 *
7315 * and here no correction would be required. Internally in
7316 * the assembler we treat operands of this form as not being
7317 * pcrel since the '.' is explicitly mentioned, and I wonder
7318 * whether it would simplify matters to do it this way. Who
7319 * knows. In earlier versions of the PIC patches, the
7320 * pcrel_adjust field was used to store the correction, but
7321 * since the expression is not pcrel, I felt it would be
7322 * confusing to do it this way. */
7323
d6ab8113 7324 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7325 || reloc_type == BFD_RELOC_X86_64_32S
7326 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7327 && GOT_symbol
7328 && GOT_symbol == i.op[n].imms->X_add_symbol
7329 && (i.op[n].imms->X_op == O_symbol
7330 || (i.op[n].imms->X_op == O_add
7331 && ((symbol_get_value_expression
7332 (i.op[n].imms->X_op_symbol)->X_op)
7333 == O_subtract))))
7334 {
2bbd9c25
JJ		 7335 offsetT add;
7336
7337 if (insn_start_frag == frag_now)
7338 add = (p - frag_now->fr_literal) - insn_start_off;
7339 else
7340 {
7341 fragS *fr;
7342
7343 add = insn_start_frag->fr_fix - insn_start_off;
7344 for (fr = insn_start_frag->fr_next;
7345 fr && fr != frag_now; fr = fr->fr_next)
7346 add += fr->fr_fix;
7347 add += p - frag_now->fr_literal;
7348 }
7349
4fa24527 7350 if (!object_64bit)
d6ab8113 7351 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7352 else if (size == 4)
d6ab8113 7353 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7354 else if (size == 8)
7355 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7356 i.op[n].imms->X_add_number += add;
29b0f896 7357 }
29b0f896
AM		 7358 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7359 i.op[n].imms, 0, reloc_type);
7360 }
7361 }
7362 }
252b5132
RH		 7363}
7364\f
d182319b
JB		 7365/* x86_cons_fix_new is called via the expression parsing code when a
7366 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 7367static int cons_sign = -1;
7368
7369void
e3bb37b5 7370x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 7371 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 7372{
d258b828 7373 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 7374
7375#ifdef TE_PE
7376 if (exp->X_op == O_secrel)
7377 {
7378 exp->X_op = O_symbol;
7379 r = BFD_RELOC_32_SECREL;
7380 }
7381#endif
7382
7383 fix_new_exp (frag, off, len, exp, 0, r);
7384}
7385
357d1bd8
L		 7386/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7387 purpose of the `.dc.a' internal pseudo-op. */
7388
7389int
7390x86_address_bytes (void)
7391{
7392 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7393 return 4;
7394 return stdoutput->arch_info->bits_per_address / 8;
7395}
7396
d382c579
TG		 7397#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7398 || defined (LEX_AT)
d258b828 7399# define lex_got(reloc, adjust, types) NULL
718ddfc0 7400#else
f3c180ae
AM		 7401/* Parse operands of the form
7402 <symbol>@GOTOFF+<nnn>
7403 and similar .plt or .got references.
7404
7405 If we find one, set up the correct relocation in RELOC and copy the
7406 input string, minus the `@GOTOFF' into a malloc'd buffer for
7407 parsing by the calling routine. Return this buffer, and if ADJUST
7408 is non-null set it to the length of the string we removed from the
7409 input line. Otherwise return NULL. */
7410static char *
91d6fa6a 7411lex_got (enum bfd_reloc_code_real *rel,
64e74474 7412 int *adjust,
d258b828 7413 i386_operand_type *types)
f3c180ae 7414{
7b81dfbb
AJ		 7415 /* Some of the relocations depend on the size of what field is to
7416 be relocated. But in our callers i386_immediate and i386_displacement
7417 we don't yet know the operand size (this will be set by insn
7418 matching). Hence we record the word32 relocation here,
7419 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7420 static const struct {
7421 const char *str;
cff8d58a 7422 int len;
4fa24527 7423 const enum bfd_reloc_code_real rel[2];
40fb9820 7424 const i386_operand_type types64;
f3c180ae 7425 } gotrel[] = {
8ce3d284 7426#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7427 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7428 BFD_RELOC_SIZE32 },
7429 OPERAND_TYPE_IMM32_64 },
8ce3d284 7430#endif
cff8d58a
L		 7431 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7432 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7433 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7434 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7435 BFD_RELOC_X86_64_PLT32 },
40fb9820 7436 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7437 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7438 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7439 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7440 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7441 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7442 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7443 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7444 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7445 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7446 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7447 BFD_RELOC_X86_64_TLSGD },
40fb9820 7448 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7449 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7450 _dummy_first_bfd_reloc_code_real },
40fb9820 7451 OPERAND_TYPE_NONE },
cff8d58a
L		 7452 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7453 BFD_RELOC_X86_64_TLSLD },
40fb9820 7454 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7455 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7456 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7457 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7458 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7459 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7460 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7461 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7462 _dummy_first_bfd_reloc_code_real },
40fb9820 7463 OPERAND_TYPE_NONE },
cff8d58a
L		 7464 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7465 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7466 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7467 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7468 _dummy_first_bfd_reloc_code_real },
40fb9820 7469 OPERAND_TYPE_NONE },
cff8d58a
L		 7470 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7471 _dummy_first_bfd_reloc_code_real },
40fb9820 7472 OPERAND_TYPE_NONE },
cff8d58a
L		 7473 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7474 BFD_RELOC_X86_64_GOT32 },
40fb9820 7475 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7476 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7477 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7478 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7479 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7480 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7481 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7482 };
7483 char *cp;
7484 unsigned int j;
7485
d382c579 7486#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7487 if (!IS_ELF)
7488 return NULL;
d382c579 7489#endif
718ddfc0 7490
f3c180ae 7491 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7492 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7493 return NULL;
7494
47465058 7495 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7496 {
cff8d58a 7497 int len = gotrel[j].len;
28f81592 7498 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7499 {
4fa24527 7500 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7501 {
28f81592
AM		 7502 int first, second;
7503 char *tmpbuf, *past_reloc;
f3c180ae 7504
91d6fa6a 7505 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7506
3956db08
JB		 7507 if (types)
7508 {
7509 if (flag_code != CODE_64BIT)
40fb9820
L		 7510 {
7511 types->bitfield.imm32 = 1;
7512 types->bitfield.disp32 = 1;
7513 }
3956db08
JB		 7514 else
7515 *types = gotrel[j].types64;
7516 }
7517
8fd4256d 7518 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7519 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7520
28f81592 7521 /* The length of the first part of our input line. */
f3c180ae 7522 first = cp - input_line_pointer;
28f81592
AM		 7523
7524 /* The second part goes from after the reloc token until
67c11a9b 7525 (and including) an end_of_line char or comma. */
28f81592 7526 past_reloc = cp + 1 + len;
67c11a9b
AM		 7527 cp = past_reloc;
7528 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7529 ++cp;
7530 second = cp + 1 - past_reloc;
28f81592
AM		 7531
7532 /* Allocate and copy string. The trailing NUL shouldn't
7533 be necessary, but be safe. */
1e9cc1c2 7534 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 7535 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7536 if (second != 0 && *past_reloc != ' ')
7537 /* Replace the relocation token with ' ', so that
7538 errors like foo@GOTOFF1 will be detected. */
7539 tmpbuf[first++] = ' ';
af89796a
L		 7540 else
7541 /* Increment length by 1 if the relocation token is
7542 removed. */
7543 len++;
7544 if (adjust)
7545 *adjust = len;
0787a12d
AM		 7546 memcpy (tmpbuf + first, past_reloc, second);
7547 tmpbuf[first + second] = '\0';
f3c180ae
AM		 7548 return tmpbuf;
7549 }
7550
4fa24527
JB		 7551 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7552 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7553 return NULL;
7554 }
7555 }
7556
7557 /* Might be a symbol version string. Don't as_bad here. */
7558 return NULL;
7559}
4e4f7c87 7560#endif
f3c180ae 7561
a988325c
NC		 7562#ifdef TE_PE
7563#ifdef lex_got
7564#undef lex_got
7565#endif
7566/* Parse operands of the form
7567 <symbol>@SECREL32+<nnn>
7568
7569 If we find one, set up the correct relocation in RELOC and copy the
7570 input string, minus the `@SECREL32' into a malloc'd buffer for
7571 parsing by the calling routine. Return this buffer, and if ADJUST
7572 is non-null set it to the length of the string we removed from the
34bca508
L		 7573 input line. Otherwise return NULL.
7574
a988325c
NC		 7575 This function is copied from the ELF version above adjusted for PE targets. */
7576
7577static char *
7578lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7579 int *adjust ATTRIBUTE_UNUSED,
d258b828 7580 i386_operand_type *types)
a988325c
NC		 7581{
7582 static const struct
7583 {
7584 const char *str;
7585 int len;
7586 const enum bfd_reloc_code_real rel[2];
7587 const i386_operand_type types64;
7588 }
7589 gotrel[] =
7590 {
7591 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7592 BFD_RELOC_32_SECREL },
7593 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7594 };
7595
7596 char *cp;
7597 unsigned j;
7598
7599 for (cp = input_line_pointer; *cp != '@'; cp++)
7600 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7601 return NULL;
7602
7603 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7604 {
7605 int len = gotrel[j].len;
7606
7607 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7608 {
7609 if (gotrel[j].rel[object_64bit] != 0)
7610 {
7611 int first, second;
7612 char *tmpbuf, *past_reloc;
7613
7614 *rel = gotrel[j].rel[object_64bit];
7615 if (adjust)
7616 *adjust = len;
7617
7618 if (types)
7619 {
7620 if (flag_code != CODE_64BIT)
7621 {
7622 types->bitfield.imm32 = 1;
7623 types->bitfield.disp32 = 1;
7624 }
7625 else
7626 *types = gotrel[j].types64;
7627 }
7628
7629 /* The length of the first part of our input line. */
7630 first = cp - input_line_pointer;
7631
7632 /* The second part goes from after the reloc token until
7633 (and including) an end_of_line char or comma. */
7634 past_reloc = cp + 1 + len;
7635 cp = past_reloc;
7636 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7637 ++cp;
7638 second = cp + 1 - past_reloc;
7639
7640 /* Allocate and copy string. The trailing NUL shouldn't
7641 be necessary, but be safe. */
7642 tmpbuf = (char *) xmalloc (first + second + 2);
7643 memcpy (tmpbuf, input_line_pointer, first);
7644 if (second != 0 && *past_reloc != ' ')
7645 /* Replace the relocation token with ' ', so that
7646 errors like foo@SECLREL321 will be detected. */
7647 tmpbuf[first++] = ' ';
7648 memcpy (tmpbuf + first, past_reloc, second);
7649 tmpbuf[first + second] = '\0';
7650 return tmpbuf;
7651 }
7652
7653 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7654 gotrel[j].str, 1 << (5 + object_64bit));
7655 return NULL;
7656 }
7657 }
7658
7659 /* Might be a symbol version string. Don't as_bad here. */
7660 return NULL;
7661}
7662
7663#endif /* TE_PE */
7664
62ebcb5c 7665bfd_reloc_code_real_type
e3bb37b5 7666x86_cons (expressionS *exp, int size)
f3c180ae 7667{
62ebcb5c
AM		 7668 bfd_reloc_code_real_type got_reloc = NO_RELOC;
7669
ee86248c
JB		 7670 intel_syntax = -intel_syntax;
7671
3c7b9c2c 7672 exp->X_md = 0;
4fa24527 7673 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 7674 {
7675 /* Handle @GOTOFF and the like in an expression. */
7676 char *save;
7677 char *gotfree_input_line;
4a57f2cf 7678 int adjust = 0;
f3c180ae
AM		 7679
7680 save = input_line_pointer;
d258b828 7681 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 7682 if (gotfree_input_line)
7683 input_line_pointer = gotfree_input_line;
7684
7685 expression (exp);
7686
7687 if (gotfree_input_line)
7688 {
7689 /* expression () has merrily parsed up to the end of line,
7690 or a comma - in the wrong buffer. Transfer how far
7691 input_line_pointer has moved to the right buffer. */
7692 input_line_pointer = (save
7693 + (input_line_pointer - gotfree_input_line)
7694 + adjust);
7695 free (gotfree_input_line);
3992d3b7
AM		 7696 if (exp->X_op == O_constant
7697 || exp->X_op == O_absent
7698 || exp->X_op == O_illegal
0398aac5 7699 || exp->X_op == O_register
3992d3b7
AM		 7700 || exp->X_op == O_big)
7701 {
7702 char c = *input_line_pointer;
7703 *input_line_pointer = 0;
7704 as_bad (_("missing or invalid expression `%s'"), save);
7705 *input_line_pointer = c;
7706 }
f3c180ae
AM		 7707 }
7708 }
7709 else
7710 expression (exp);
ee86248c
JB		 7711
7712 intel_syntax = -intel_syntax;
7713
7714 if (intel_syntax)
7715 i386_intel_simplify (exp);
62ebcb5c
AM		 7716
7717 return got_reloc;
f3c180ae 7718}
f3c180ae 7719
9f32dd5b
L		 7720static void
7721signed_cons (int size)
6482c264 7722{
d182319b
JB		 7723 if (flag_code == CODE_64BIT)
7724 cons_sign = 1;
7725 cons (size);
7726 cons_sign = -1;
6482c264
NC		 7727}
7728
d182319b 7729#ifdef TE_PE
6482c264 7730static void
7016a5d5 7731pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 7732{
7733 expressionS exp;
7734
7735 do
7736 {
7737 expression (&exp);
7738 if (exp.X_op == O_symbol)
7739 exp.X_op = O_secrel;
7740
7741 emit_expr (&exp, 4);
7742 }
7743 while (*input_line_pointer++ == ',');
7744
7745 input_line_pointer--;
7746 demand_empty_rest_of_line ();
7747}
6482c264
NC		 7748#endif
7749
43234a1e
L		 7750/* Handle Vector operations. */
7751
7752static char *
7753check_VecOperations (char *op_string, char *op_end)
7754{
7755 const reg_entry *mask;
7756 const char *saved;
7757 char *end_op;
7758
7759 while (*op_string
7760 && (op_end == NULL || op_string < op_end))
7761 {
7762 saved = op_string;
7763 if (*op_string == '{')
7764 {
7765 op_string++;
7766
7767 /* Check broadcasts. */
7768 if (strncmp (op_string, "1to", 3) == 0)
7769 {
7770 int bcst_type;
7771
7772 if (i.broadcast)
7773 goto duplicated_vec_op;
7774
7775 op_string += 3;
7776 if (*op_string == '8')
7777 bcst_type = BROADCAST_1TO8;
b28d1bda
IT		 7778 else if (*op_string == '4')
7779 bcst_type = BROADCAST_1TO4;
7780 else if (*op_string == '2')
7781 bcst_type = BROADCAST_1TO2;
43234a1e
L		 7782 else if (*op_string == '1'
7783 && *(op_string+1) == '6')
7784 {
7785 bcst_type = BROADCAST_1TO16;
7786 op_string++;
7787 }
7788 else
7789 {
7790 as_bad (_("Unsupported broadcast: `%s'"), saved);
7791 return NULL;
7792 }
7793 op_string++;
7794
7795 broadcast_op.type = bcst_type;
7796 broadcast_op.operand = this_operand;
7797 i.broadcast = &broadcast_op;
7798 }
7799 /* Check masking operation. */
7800 else if ((mask = parse_register (op_string, &end_op)) != NULL)
7801 {
7802 /* k0 can't be used for write mask. */
7803 if (mask->reg_num == 0)
7804 {
7805 as_bad (_("`%s' can't be used for write mask"),
7806 op_string);
7807 return NULL;
7808 }
7809
7810 if (!i.mask)
7811 {
7812 mask_op.mask = mask;
7813 mask_op.zeroing = 0;
7814 mask_op.operand = this_operand;
7815 i.mask = &mask_op;
7816 }
7817 else
7818 {
7819 if (i.mask->mask)
7820 goto duplicated_vec_op;
7821
7822 i.mask->mask = mask;
7823
7824 /* Only "{z}" is allowed here. No need to check
7825 zeroing mask explicitly. */
7826 if (i.mask->operand != this_operand)
7827 {
7828 as_bad (_("invalid write mask `%s'"), saved);
7829 return NULL;
7830 }
7831 }
7832
7833 op_string = end_op;
7834 }
7835 /* Check zeroing-flag for masking operation. */
7836 else if (*op_string == 'z')
7837 {
7838 if (!i.mask)
7839 {
7840 mask_op.mask = NULL;
7841 mask_op.zeroing = 1;
7842 mask_op.operand = this_operand;
7843 i.mask = &mask_op;
7844 }
7845 else
7846 {
7847 if (i.mask->zeroing)
7848 {
7849 duplicated_vec_op:
7850 as_bad (_("duplicated `%s'"), saved);
7851 return NULL;
7852 }
7853
7854 i.mask->zeroing = 1;
7855
7856 /* Only "{%k}" is allowed here. No need to check mask
7857 register explicitly. */
7858 if (i.mask->operand != this_operand)
7859 {
7860 as_bad (_("invalid zeroing-masking `%s'"),
7861 saved);
7862 return NULL;
7863 }
7864 }
7865
7866 op_string++;
7867 }
7868 else
7869 goto unknown_vec_op;
7870
7871 if (*op_string != '}')
7872 {
7873 as_bad (_("missing `}' in `%s'"), saved);
7874 return NULL;
7875 }
7876 op_string++;
7877 continue;
7878 }
7879 unknown_vec_op:
7880 /* We don't know this one. */
7881 as_bad (_("unknown vector operation: `%s'"), saved);
7882 return NULL;
7883 }
7884
7885 return op_string;
7886}
7887
252b5132 7888static int
70e41ade 7889i386_immediate (char *imm_start)
252b5132
RH		 7890{
7891 char *save_input_line_pointer;
f3c180ae 7892 char *gotfree_input_line;
252b5132 7893 segT exp_seg = 0;
47926f60 7894 expressionS *exp;
40fb9820
L		 7895 i386_operand_type types;
7896
0dfbf9d7 7897 operand_type_set (&types, ~0);
252b5132
RH		 7898
7899 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
7900 {
31b2323c
L		 7901 as_bad (_("at most %d immediate operands are allowed"),
7902 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 7903 return 0;
7904 }
7905
7906 exp = &im_expressions[i.imm_operands++];
520dc8e8 7907 i.op[this_operand].imms = exp;
252b5132
RH		 7908
7909 if (is_space_char (*imm_start))
7910 ++imm_start;
7911
7912 save_input_line_pointer = input_line_pointer;
7913 input_line_pointer = imm_start;
7914
d258b828 7915 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 7916 if (gotfree_input_line)
7917 input_line_pointer = gotfree_input_line;
252b5132
RH		 7918
7919 exp_seg = expression (exp);
7920
83183c0c 7921 SKIP_WHITESPACE ();
43234a1e
L		 7922
7923 /* Handle vector operations. */
7924 if (*input_line_pointer == '{')
7925 {
7926 input_line_pointer = check_VecOperations (input_line_pointer,
7927 NULL);
7928 if (input_line_pointer == NULL)
7929 return 0;
7930 }
7931
252b5132 7932 if (*input_line_pointer)
f3c180ae 7933 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 7934
7935 input_line_pointer = save_input_line_pointer;
f3c180ae 7936 if (gotfree_input_line)
ee86248c
JB		 7937 {
7938 free (gotfree_input_line);
7939
7940 if (exp->X_op == O_constant || exp->X_op == O_register)
7941 exp->X_op = O_illegal;
7942 }
7943
7944 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
7945}
252b5132 7946
ee86248c
JB		 7947static int
7948i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7949 i386_operand_type types, const char *imm_start)
7950{
7951 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 7952 {
313c53d1
L		 7953 if (imm_start)
7954 as_bad (_("missing or invalid immediate expression `%s'"),
7955 imm_start);
3992d3b7 7956 return 0;
252b5132 7957 }
3e73aa7c 7958 else if (exp->X_op == O_constant)
252b5132 7959 {
47926f60 7960 /* Size it properly later. */
40fb9820 7961 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 7962 /* If not 64bit, sign extend val. */
7963 if (flag_code != CODE_64BIT
4eed87de
AM		 7964 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
7965 exp->X_add_number
7966 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 7967 }
4c63da97 7968#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 7969 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 7970 && exp_seg != absolute_section
47926f60 7971 && exp_seg != text_section
24eab124
AM		 7972 && exp_seg != data_section
7973 && exp_seg != bss_section
7974 && exp_seg != undefined_section
f86103b7 7975 && !bfd_is_com_section (exp_seg))
252b5132 7976 {
d0b47220 7977 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 7978 return 0;
7979 }
7980#endif
a841bdf5 7981 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 7982 {
313c53d1
L		 7983 if (imm_start)
7984 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 7985 return 0;
7986 }
252b5132
RH		 7987 else
7988 {
7989 /* This is an address. The size of the address will be
24eab124 7990 determined later, depending on destination register,
3e73aa7c 7991 suffix, or the default for the section. */
40fb9820
L		 7992 i.types[this_operand].bitfield.imm8 = 1;
7993 i.types[this_operand].bitfield.imm16 = 1;
7994 i.types[this_operand].bitfield.imm32 = 1;
7995 i.types[this_operand].bitfield.imm32s = 1;
7996 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 7997 i.types[this_operand] = operand_type_and (i.types[this_operand],
7998 types);
252b5132
RH		 7999 }
8000
8001 return 1;
8002}
8003
551c1ca1 8004static char *
e3bb37b5 8005i386_scale (char *scale)
252b5132 8006{
551c1ca1
AM		 8007 offsetT val;
8008 char *save = input_line_pointer;
252b5132 8009
551c1ca1
AM		 8010 input_line_pointer = scale;
8011 val = get_absolute_expression ();
8012
8013 switch (val)
252b5132 8014 {
551c1ca1 8015 case 1:
252b5132
RH		 8016 i.log2_scale_factor = 0;
8017 break;
551c1ca1 8018 case 2:
252b5132
RH		 8019 i.log2_scale_factor = 1;
8020 break;
551c1ca1 8021 case 4:
252b5132
RH		 8022 i.log2_scale_factor = 2;
8023 break;
551c1ca1 8024 case 8:
252b5132
RH		 8025 i.log2_scale_factor = 3;
8026 break;
8027 default:
a724f0f4
JB		 8028 {
8029 char sep = *input_line_pointer;
8030
8031 *input_line_pointer = '\0';
8032 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8033 scale);
8034 *input_line_pointer = sep;
8035 input_line_pointer = save;
8036 return NULL;
8037 }
252b5132 8038 }
29b0f896 8039 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8040 {
8041 as_warn (_("scale factor of %d without an index register"),
24eab124 8042 1 << i.log2_scale_factor);
252b5132 8043 i.log2_scale_factor = 0;
252b5132 8044 }
551c1ca1
AM		 8045 scale = input_line_pointer;
8046 input_line_pointer = save;
8047 return scale;
252b5132
RH		 8048}
8049
252b5132 8050static int
e3bb37b5 8051i386_displacement (char *disp_start, char *disp_end)
252b5132 8052{
29b0f896 8053 expressionS *exp;
252b5132
RH		 8054 segT exp_seg = 0;
8055 char *save_input_line_pointer;
f3c180ae 8056 char *gotfree_input_line;
40fb9820
L		 8057 int override;
8058 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8059 int ret;
252b5132 8060
31b2323c
L		 8061 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8062 {
8063 as_bad (_("at most %d displacement operands are allowed"),
8064 MAX_MEMORY_OPERANDS);
8065 return 0;
8066 }
8067
0dfbf9d7 8068 operand_type_set (&bigdisp, 0);
40fb9820
L		 8069 if ((i.types[this_operand].bitfield.jumpabsolute)
8070 || (!current_templates->start->opcode_modifier.jump
8071 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8072 {
40fb9820 8073 bigdisp.bitfield.disp32 = 1;
e05278af 8074 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8075 if (flag_code == CODE_64BIT)
8076 {
8077 if (!override)
8078 {
8079 bigdisp.bitfield.disp32s = 1;
8080 bigdisp.bitfield.disp64 = 1;
8081 }
8082 }
8083 else if ((flag_code == CODE_16BIT) ^ override)
8084 {
8085 bigdisp.bitfield.disp32 = 0;
8086 bigdisp.bitfield.disp16 = 1;
8087 }
e05278af
JB		 8088 }
8089 else
8090 {
8091 /* For PC-relative branches, the width of the displacement
8092 is dependent upon data size, not address size. */
e05278af 8093 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8094 if (flag_code == CODE_64BIT)
8095 {
8096 if (override || i.suffix == WORD_MNEM_SUFFIX)
8097 bigdisp.bitfield.disp16 = 1;
8098 else
8099 {
8100 bigdisp.bitfield.disp32 = 1;
8101 bigdisp.bitfield.disp32s = 1;
8102 }
8103 }
8104 else
e05278af
JB		 8105 {
8106 if (!override)
8107 override = (i.suffix == (flag_code != CODE_16BIT
8108 ? WORD_MNEM_SUFFIX
8109 : LONG_MNEM_SUFFIX));
40fb9820
L		 8110 bigdisp.bitfield.disp32 = 1;
8111 if ((flag_code == CODE_16BIT) ^ override)
8112 {
8113 bigdisp.bitfield.disp32 = 0;
8114 bigdisp.bitfield.disp16 = 1;
8115 }
e05278af 8116 }
e05278af 8117 }
c6fb90c8
L		 8118 i.types[this_operand] = operand_type_or (i.types[this_operand],
8119 bigdisp);
252b5132
RH		 8120
8121 exp = &disp_expressions[i.disp_operands];
520dc8e8 8122 i.op[this_operand].disps = exp;
252b5132
RH		 8123 i.disp_operands++;
8124 save_input_line_pointer = input_line_pointer;
8125 input_line_pointer = disp_start;
8126 END_STRING_AND_SAVE (disp_end);
8127
8128#ifndef GCC_ASM_O_HACK
8129#define GCC_ASM_O_HACK 0
8130#endif
8131#if GCC_ASM_O_HACK
8132 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8133 if (i.types[this_operand].bitfield.baseIndex
24eab124 8134 && displacement_string_end[-1] == '+')
252b5132
RH		 8135 {
8136 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8137 constraint within gcc asm statements.
8138 For instance:
8139
8140 #define _set_tssldt_desc(n,addr,limit,type) \
8141 __asm__ __volatile__ ( \
8142 "movw %w2,%0\n\t" \
8143 "movw %w1,2+%0\n\t" \
8144 "rorl $16,%1\n\t" \
8145 "movb %b1,4+%0\n\t" \
8146 "movb %4,5+%0\n\t" \
8147 "movb $0,6+%0\n\t" \
8148 "movb %h1,7+%0\n\t" \
8149 "rorl $16,%1" \
8150 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8151
8152 This works great except that the output assembler ends
8153 up looking a bit weird if it turns out that there is
8154 no offset. You end up producing code that looks like:
8155
8156 #APP
8157 movw $235,(%eax)
8158 movw %dx,2+(%eax)
8159 rorl $16,%edx
8160 movb %dl,4+(%eax)
8161 movb $137,5+(%eax)
8162 movb $0,6+(%eax)
8163 movb %dh,7+(%eax)
8164 rorl $16,%edx
8165 #NO_APP
8166
47926f60 8167 So here we provide the missing zero. */
24eab124
AM		 8168
8169 *displacement_string_end = '0';
252b5132
RH		 8170 }
8171#endif
d258b828 8172 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8173 if (gotfree_input_line)
8174 input_line_pointer = gotfree_input_line;
252b5132 8175
24eab124 8176 exp_seg = expression (exp);
252b5132 8177
636c26b0
AM		 8178 SKIP_WHITESPACE ();
8179 if (*input_line_pointer)
8180 as_bad (_("junk `%s' after expression"), input_line_pointer);
8181#if GCC_ASM_O_HACK
8182 RESTORE_END_STRING (disp_end + 1);
8183#endif
636c26b0 8184 input_line_pointer = save_input_line_pointer;
636c26b0 8185 if (gotfree_input_line)
ee86248c
JB		 8186 {
8187 free (gotfree_input_line);
8188
8189 if (exp->X_op == O_constant || exp->X_op == O_register)
8190 exp->X_op = O_illegal;
8191 }
8192
8193 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8194
8195 RESTORE_END_STRING (disp_end);
8196
8197 return ret;
8198}
8199
8200static int
8201i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8202 i386_operand_type types, const char *disp_start)
8203{
8204 i386_operand_type bigdisp;
8205 int ret = 1;
636c26b0 8206
24eab124
AM		 8207 /* We do this to make sure that the section symbol is in
8208 the symbol table. We will ultimately change the relocation
47926f60 8209 to be relative to the beginning of the section. */
1ae12ab7 8210 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8211 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8212 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8213 {
636c26b0 8214 if (exp->X_op != O_symbol)
3992d3b7 8215 goto inv_disp;
636c26b0 8216
e5cb08ac 8217 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8218 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8219 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8220 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8221 exp->X_op = O_subtract;
8222 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8223 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8224 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8225 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8226 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8227 else
29b0f896 8228 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8229 }
252b5132 8230
3992d3b7
AM		 8231 else if (exp->X_op == O_absent
8232 || exp->X_op == O_illegal
ee86248c 8233 || exp->X_op == O_big)
2daf4fd8 8234 {
3992d3b7
AM		 8235 inv_disp:
8236 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8237 disp_start);
3992d3b7 8238 ret = 0;
2daf4fd8
AM		 8239 }
8240
0e1147d9
L		 8241 else if (flag_code == CODE_64BIT
8242 && !i.prefix[ADDR_PREFIX]
8243 && exp->X_op == O_constant)
8244 {
8245 /* Since displacement is signed extended to 64bit, don't allow
8246 disp32 and turn off disp32s if they are out of range. */
8247 i.types[this_operand].bitfield.disp32 = 0;
8248 if (!fits_in_signed_long (exp->X_add_number))
8249 {
8250 i.types[this_operand].bitfield.disp32s = 0;
8251 if (i.types[this_operand].bitfield.baseindex)
8252 {
8253 as_bad (_("0x%lx out range of signed 32bit displacement"),
8254 (long) exp->X_add_number);
8255 ret = 0;
8256 }
8257 }
8258 }
8259
4c63da97 8260#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8261 else if (exp->X_op != O_constant
8262 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8263 && exp_seg != absolute_section
8264 && exp_seg != text_section
8265 && exp_seg != data_section
8266 && exp_seg != bss_section
8267 && exp_seg != undefined_section
8268 && !bfd_is_com_section (exp_seg))
24eab124 8269 {
d0b47220 8270 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8271 ret = 0;
24eab124 8272 }
252b5132 8273#endif
3956db08 8274
40fb9820
L		 8275 /* Check if this is a displacement only operand. */
8276 bigdisp = i.types[this_operand];
8277 bigdisp.bitfield.disp8 = 0;
8278 bigdisp.bitfield.disp16 = 0;
8279 bigdisp.bitfield.disp32 = 0;
8280 bigdisp.bitfield.disp32s = 0;
8281 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8282 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8283 i.types[this_operand] = operand_type_and (i.types[this_operand],
8284 types);
3956db08 8285
3992d3b7 8286 return ret;
252b5132
RH		 8287}
8288
eecb386c 8289/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 8290 Return 1 on success, 0 on a failure. */
8291
252b5132 8292static int
e3bb37b5 8293i386_index_check (const char *operand_string)
252b5132 8294{
fc0763e6 8295 const char *kind = "base/index";
be05d201
L		 8296 enum flag_code addr_mode;
8297
8298 if (i.prefix[ADDR_PREFIX])
8299 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8300 else
8301 {
8302 addr_mode = flag_code;
8303
24eab124 8304#if INFER_ADDR_PREFIX
be05d201
L		 8305 if (i.mem_operands == 0)
8306 {
8307 /* Infer address prefix from the first memory operand. */
8308 const reg_entry *addr_reg = i.base_reg;
8309
8310 if (addr_reg == NULL)
8311 addr_reg = i.index_reg;
eecb386c 8312
be05d201
L		 8313 if (addr_reg)
8314 {
8315 if (addr_reg->reg_num == RegEip
8316 || addr_reg->reg_num == RegEiz
8317 || addr_reg->reg_type.bitfield.reg32)
8318 addr_mode = CODE_32BIT;
8319 else if (flag_code != CODE_64BIT
8320 && addr_reg->reg_type.bitfield.reg16)
8321 addr_mode = CODE_16BIT;
8322
8323 if (addr_mode != flag_code)
8324 {
8325 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8326 i.prefixes += 1;
8327 /* Change the size of any displacement too. At most one
8328 of Disp16 or Disp32 is set.
8329 FIXME. There doesn't seem to be any real need for
8330 separate Disp16 and Disp32 flags. The same goes for
8331 Imm16 and Imm32. Removing them would probably clean
8332 up the code quite a lot. */
8333 if (flag_code != CODE_64BIT
8334 && (i.types[this_operand].bitfield.disp16
8335 || i.types[this_operand].bitfield.disp32))
8336 i.types[this_operand]
8337 = operand_type_xor (i.types[this_operand], disp16_32);
8338 }
8339 }
8340 }
24eab124 8341#endif
be05d201
L		 8342 }
8343
fc0763e6
JB		 8344 if (current_templates->start->opcode_modifier.isstring
8345 && !current_templates->start->opcode_modifier.immext
8346 && (current_templates->end[-1].opcode_modifier.isstring
8347 || i.mem_operands))
8348 {
8349 /* Memory operands of string insns are special in that they only allow
8350 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8351 const reg_entry *expected_reg;
8352 static const char *di_si[][2] =
8353 {
8354 { "esi", "edi" },
8355 { "si", "di" },
8356 { "rsi", "rdi" }
8357 };
8358 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8359
8360 kind = "string address";
8361
8362 if (current_templates->start->opcode_modifier.w)
8363 {
8364 i386_operand_type type = current_templates->end[-1].operand_types[0];
8365
8366 if (!type.bitfield.baseindex
8367 || ((!i.mem_operands != !intel_syntax)
8368 && current_templates->end[-1].operand_types[1]
8369 .bitfield.baseindex))
8370 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8371 expected_reg = hash_find (reg_hash,
8372 di_si[addr_mode][type.bitfield.esseg]);
8373
fc0763e6
JB		 8374 }
8375 else
be05d201 8376 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8377
be05d201
L		 8378 if (i.base_reg != expected_reg
8379 || i.index_reg
fc0763e6 8380 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8381 {
be05d201
L		 8382 /* The second memory operand must have the same size as
8383 the first one. */
8384 if (i.mem_operands
8385 && i.base_reg
8386 && !((addr_mode == CODE_64BIT
8387 && i.base_reg->reg_type.bitfield.reg64)
8388 || (addr_mode == CODE_32BIT
8389 ? i.base_reg->reg_type.bitfield.reg32
8390 : i.base_reg->reg_type.bitfield.reg16)))
8391 goto bad_address;
8392
fc0763e6
JB		 8393 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8394 operand_string,
8395 intel_syntax ? '[' : '(',
8396 register_prefix,
be05d201 8397 expected_reg->reg_name,
fc0763e6 8398 intel_syntax ? ']' : ')');
be05d201 8399 return 1;
fc0763e6 8400 }
be05d201
L		 8401 else
8402 return 1;
8403
8404bad_address:
8405 as_bad (_("`%s' is not a valid %s expression"),
8406 operand_string, kind);
8407 return 0;
3e73aa7c
JH		 8408 }
8409 else
8410 {
be05d201
L		 8411 if (addr_mode != CODE_16BIT)
8412 {
8413 /* 32-bit/64-bit checks. */
8414 if ((i.base_reg
8415 && (addr_mode == CODE_64BIT
8416 ? !i.base_reg->reg_type.bitfield.reg64
8417 : !i.base_reg->reg_type.bitfield.reg32)
8418 && (i.index_reg
8419 || (i.base_reg->reg_num
8420 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8421 || (i.index_reg
8422 && !i.index_reg->reg_type.bitfield.regxmm
8423 && !i.index_reg->reg_type.bitfield.regymm
43234a1e 8424 && !i.index_reg->reg_type.bitfield.regzmm
be05d201
L		 8425 && ((addr_mode == CODE_64BIT
8426 ? !(i.index_reg->reg_type.bitfield.reg64
8427 || i.index_reg->reg_num == RegRiz)
8428 : !(i.index_reg->reg_type.bitfield.reg32
8429 || i.index_reg->reg_num == RegEiz))
8430 || !i.index_reg->reg_type.bitfield.baseindex)))
8431 goto bad_address;
8432 }
8433 else
3e73aa7c 8434 {
be05d201 8435 /* 16-bit checks. */
3e73aa7c 8436 if ((i.base_reg
40fb9820
L		 8437 && (!i.base_reg->reg_type.bitfield.reg16
8438 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8439 || (i.index_reg
40fb9820
L		 8440 && (!i.index_reg->reg_type.bitfield.reg16
8441 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8442 || !(i.base_reg
8443 && i.base_reg->reg_num < 6
8444 && i.index_reg->reg_num >= 6
8445 && i.log2_scale_factor == 0))))
be05d201 8446 goto bad_address;
3e73aa7c
JH		 8447 }
8448 }
be05d201 8449 return 1;
24eab124 8450}
252b5132 8451
43234a1e
L		 8452/* Handle vector immediates. */
8453
8454static int
8455RC_SAE_immediate (const char *imm_start)
8456{
8457 unsigned int match_found, j;
8458 const char *pstr = imm_start;
8459 expressionS *exp;
8460
8461 if (*pstr != '{')
8462 return 0;
8463
8464 pstr++;
8465 match_found = 0;
8466 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8467 {
8468 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8469 {
8470 if (!i.rounding)
8471 {
8472 rc_op.type = RC_NamesTable[j].type;
8473 rc_op.operand = this_operand;
8474 i.rounding = &rc_op;
8475 }
8476 else
8477 {
8478 as_bad (_("duplicated `%s'"), imm_start);
8479 return 0;
8480 }
8481 pstr += RC_NamesTable[j].len;
8482 match_found = 1;
8483 break;
8484 }
8485 }
8486 if (!match_found)
8487 return 0;
8488
8489 if (*pstr++ != '}')
8490 {
8491 as_bad (_("Missing '}': '%s'"), imm_start);
8492 return 0;
8493 }
8494 /* RC/SAE immediate string should contain nothing more. */;
8495 if (*pstr != 0)
8496 {
8497 as_bad (_("Junk after '}': '%s'"), imm_start);
8498 return 0;
8499 }
8500
8501 exp = &im_expressions[i.imm_operands++];
8502 i.op[this_operand].imms = exp;
8503
8504 exp->X_op = O_constant;
8505 exp->X_add_number = 0;
8506 exp->X_add_symbol = (symbolS *) 0;
8507 exp->X_op_symbol = (symbolS *) 0;
8508
8509 i.types[this_operand].bitfield.imm8 = 1;
8510 return 1;
8511}
8512
fc0763e6 8513/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8514 on error. */
252b5132 8515
252b5132 8516static int
a7619375 8517i386_att_operand (char *operand_string)
252b5132 8518{
af6bdddf
AM		 8519 const reg_entry *r;
8520 char *end_op;
24eab124 8521 char *op_string = operand_string;
252b5132 8522
24eab124 8523 if (is_space_char (*op_string))
252b5132
RH		 8524 ++op_string;
8525
24eab124 8526 /* We check for an absolute prefix (differentiating,
47926f60 8527 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8528 if (*op_string == ABSOLUTE_PREFIX)
8529 {
8530 ++op_string;
8531 if (is_space_char (*op_string))
8532 ++op_string;
40fb9820 8533 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8534 }
252b5132 8535
47926f60 8536 /* Check if operand is a register. */
4d1bb795 8537 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8538 {
40fb9820
L		 8539 i386_operand_type temp;
8540
24eab124
AM		 8541 /* Check for a segment override by searching for ':' after a
8542 segment register. */
8543 op_string = end_op;
8544 if (is_space_char (*op_string))
8545 ++op_string;
40fb9820
L		 8546 if (*op_string == ':'
8547 && (r->reg_type.bitfield.sreg2
8548 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8549 {
8550 switch (r->reg_num)
8551 {
8552 case 0:
8553 i.seg[i.mem_operands] = &es;
8554 break;
8555 case 1:
8556 i.seg[i.mem_operands] = &cs;
8557 break;
8558 case 2:
8559 i.seg[i.mem_operands] = &ss;
8560 break;
8561 case 3:
8562 i.seg[i.mem_operands] = &ds;
8563 break;
8564 case 4:
8565 i.seg[i.mem_operands] = &fs;
8566 break;
8567 case 5:
8568 i.seg[i.mem_operands] = &gs;
8569 break;
8570 }
252b5132 8571
24eab124 8572 /* Skip the ':' and whitespace. */
252b5132
RH		 8573 ++op_string;
8574 if (is_space_char (*op_string))
24eab124 8575 ++op_string;
252b5132 8576
24eab124
AM		 8577 if (!is_digit_char (*op_string)
8578 && !is_identifier_char (*op_string)
8579 && *op_string != '('
8580 && *op_string != ABSOLUTE_PREFIX)
8581 {
8582 as_bad (_("bad memory operand `%s'"), op_string);
8583 return 0;
8584 }
47926f60 8585 /* Handle case of %es:*foo. */
24eab124
AM		 8586 if (*op_string == ABSOLUTE_PREFIX)
8587 {
8588 ++op_string;
8589 if (is_space_char (*op_string))
8590 ++op_string;
40fb9820 8591 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8592 }
8593 goto do_memory_reference;
8594 }
43234a1e
L		 8595
8596 /* Handle vector operations. */
8597 if (*op_string == '{')
8598 {
8599 op_string = check_VecOperations (op_string, NULL);
8600 if (op_string == NULL)
8601 return 0;
8602 }
8603
24eab124
AM		 8604 if (*op_string)
8605 {
d0b47220 8606 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 8607 return 0;
8608 }
40fb9820
L		 8609 temp = r->reg_type;
8610 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8611 i.types[this_operand] = operand_type_or (i.types[this_operand],
8612 temp);
7d5e4556 8613 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 8614 i.op[this_operand].regs = r;
24eab124
AM		 8615 i.reg_operands++;
8616 }
af6bdddf
AM		 8617 else if (*op_string == REGISTER_PREFIX)
8618 {
8619 as_bad (_("bad register name `%s'"), op_string);
8620 return 0;
8621 }
24eab124 8622 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 8623 {
24eab124 8624 ++op_string;
40fb9820 8625 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 8626 {
d0b47220 8627 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 8628 return 0;
8629 }
8630 if (!i386_immediate (op_string))
8631 return 0;
8632 }
43234a1e
L		 8633 else if (RC_SAE_immediate (operand_string))
8634 {
8635 /* If it is a RC or SAE immediate, do nothing. */
8636 ;
8637 }
24eab124
AM		 8638 else if (is_digit_char (*op_string)
8639 || is_identifier_char (*op_string)
e5cb08ac 8640 || *op_string == '(')
24eab124 8641 {
47926f60 8642 /* This is a memory reference of some sort. */
af6bdddf 8643 char *base_string;
252b5132 8644
47926f60 8645 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 8646 char *displacement_string_start;
8647 char *displacement_string_end;
43234a1e 8648 char *vop_start;
252b5132 8649
24eab124 8650 do_memory_reference:
24eab124 8651 if ((i.mem_operands == 1
40fb9820 8652 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 8653 || i.mem_operands == 2)
8654 {
8655 as_bad (_("too many memory references for `%s'"),
8656 current_templates->start->name);
8657 return 0;
8658 }
252b5132 8659
24eab124
AM		 8660 /* Check for base index form. We detect the base index form by
8661 looking for an ')' at the end of the operand, searching
8662 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8663 after the '('. */
af6bdddf 8664 base_string = op_string + strlen (op_string);
c3332e24 8665
43234a1e
L		 8666 /* Handle vector operations. */
8667 vop_start = strchr (op_string, '{');
8668 if (vop_start && vop_start < base_string)
8669 {
8670 if (check_VecOperations (vop_start, base_string) == NULL)
8671 return 0;
8672 base_string = vop_start;
8673 }
8674
af6bdddf
AM		 8675 --base_string;
8676 if (is_space_char (*base_string))
8677 --base_string;
252b5132 8678
47926f60 8679 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 8680 displacement_string_start = op_string;
8681 displacement_string_end = base_string + 1;
252b5132 8682
24eab124
AM		 8683 if (*base_string == ')')
8684 {
af6bdddf 8685 char *temp_string;
24eab124
AM		 8686 unsigned int parens_balanced = 1;
8687 /* We've already checked that the number of left & right ()'s are
47926f60 8688 equal, so this loop will not be infinite. */
24eab124
AM		 8689 do
8690 {
8691 base_string--;
8692 if (*base_string == ')')
8693 parens_balanced++;
8694 if (*base_string == '(')
8695 parens_balanced--;
8696 }
8697 while (parens_balanced);
c3332e24 8698
af6bdddf 8699 temp_string = base_string;
c3332e24 8700
24eab124 8701 /* Skip past '(' and whitespace. */
252b5132
RH		 8702 ++base_string;
8703 if (is_space_char (*base_string))
24eab124 8704 ++base_string;
252b5132 8705
af6bdddf 8706 if (*base_string == ','
4eed87de
AM		 8707 || ((i.base_reg = parse_register (base_string, &end_op))
8708 != NULL))
252b5132 8709 {
af6bdddf 8710 displacement_string_end = temp_string;
252b5132 8711
40fb9820 8712 i.types[this_operand].bitfield.baseindex = 1;
252b5132 8713
af6bdddf 8714 if (i.base_reg)
24eab124 8715 {
24eab124
AM		 8716 base_string = end_op;
8717 if (is_space_char (*base_string))
8718 ++base_string;
af6bdddf
AM		 8719 }
8720
8721 /* There may be an index reg or scale factor here. */
8722 if (*base_string == ',')
8723 {
8724 ++base_string;
8725 if (is_space_char (*base_string))
8726 ++base_string;
8727
4eed87de
AM		 8728 if ((i.index_reg = parse_register (base_string, &end_op))
8729 != NULL)
24eab124 8730 {
af6bdddf 8731 base_string = end_op;
24eab124
AM		 8732 if (is_space_char (*base_string))
8733 ++base_string;
af6bdddf
AM		 8734 if (*base_string == ',')
8735 {
8736 ++base_string;
8737 if (is_space_char (*base_string))
8738 ++base_string;
8739 }
e5cb08ac 8740 else if (*base_string != ')')
af6bdddf 8741 {
4eed87de
AM		 8742 as_bad (_("expecting `,' or `)' "
8743 "after index register in `%s'"),
af6bdddf
AM		 8744 operand_string);
8745 return 0;
8746 }
24eab124 8747 }
af6bdddf 8748 else if (*base_string == REGISTER_PREFIX)
24eab124 8749 {
f76bf5e0
L		 8750 end_op = strchr (base_string, ',');
8751 if (end_op)
8752 *end_op = '\0';
af6bdddf 8753 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 8754 return 0;
8755 }
252b5132 8756
47926f60 8757 /* Check for scale factor. */
551c1ca1 8758 if (*base_string != ')')
af6bdddf 8759 {
551c1ca1
AM		 8760 char *end_scale = i386_scale (base_string);
8761
8762 if (!end_scale)
af6bdddf 8763 return 0;
24eab124 8764
551c1ca1 8765 base_string = end_scale;
af6bdddf
AM		 8766 if (is_space_char (*base_string))
8767 ++base_string;
8768 if (*base_string != ')')
8769 {
4eed87de
AM		 8770 as_bad (_("expecting `)' "
8771 "after scale factor in `%s'"),
af6bdddf
AM		 8772 operand_string);
8773 return 0;
8774 }
8775 }
8776 else if (!i.index_reg)
24eab124 8777 {
4eed87de
AM		 8778 as_bad (_("expecting index register or scale factor "
8779 "after `,'; got '%c'"),
af6bdddf 8780 *base_string);
24eab124
AM		 8781 return 0;
8782 }
8783 }
af6bdddf 8784 else if (*base_string != ')')
24eab124 8785 {
4eed87de
AM		 8786 as_bad (_("expecting `,' or `)' "
8787 "after base register in `%s'"),
af6bdddf 8788 operand_string);
24eab124
AM		 8789 return 0;
8790 }
c3332e24 8791 }
af6bdddf 8792 else if (*base_string == REGISTER_PREFIX)
c3332e24 8793 {
f76bf5e0
L		 8794 end_op = strchr (base_string, ',');
8795 if (end_op)
8796 *end_op = '\0';
af6bdddf 8797 as_bad (_("bad register name `%s'"), base_string);
24eab124 8798 return 0;
c3332e24 8799 }
24eab124
AM		 8800 }
8801
8802 /* If there's an expression beginning the operand, parse it,
8803 assuming displacement_string_start and
8804 displacement_string_end are meaningful. */
8805 if (displacement_string_start != displacement_string_end)
8806 {
8807 if (!i386_displacement (displacement_string_start,
8808 displacement_string_end))
8809 return 0;
8810 }
8811
8812 /* Special case for (%dx) while doing input/output op. */
8813 if (i.base_reg
0dfbf9d7
L		 8814 && operand_type_equal (&i.base_reg->reg_type,
8815 &reg16_inoutportreg)
24eab124
AM		 8816 && i.index_reg == 0
8817 && i.log2_scale_factor == 0
8818 && i.seg[i.mem_operands] == 0
40fb9820 8819 && !operand_type_check (i.types[this_operand], disp))
24eab124 8820 {
65da13b5 8821 i.types[this_operand] = inoutportreg;
24eab124
AM		 8822 return 1;
8823 }
8824
eecb386c
AM		 8825 if (i386_index_check (operand_string) == 0)
8826 return 0;
5c07affc 8827 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 8828 i.mem_operands++;
8829 }
8830 else
ce8a8b2f
AM		 8831 {
8832 /* It's not a memory operand; argh! */
24eab124
AM		 8833 as_bad (_("invalid char %s beginning operand %d `%s'"),
8834 output_invalid (*op_string),
8835 this_operand + 1,
8836 op_string);
8837 return 0;
8838 }
47926f60 8839 return 1; /* Normal return. */
252b5132
RH		 8840}
8841\f
fa94de6b
RM		 8842/* Calculate the maximum variable size (i.e., excluding fr_fix)
8843 that an rs_machine_dependent frag may reach. */
8844
8845unsigned int
8846i386_frag_max_var (fragS *frag)
8847{
8848 /* The only relaxable frags are for jumps.
8849 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8850 gas_assert (frag->fr_type == rs_machine_dependent);
8851 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
8852}
8853
b084df0b
L		 8854#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8855static int
8dcea932 8856elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
b084df0b
L		 8857{
8858 /* STT_GNU_IFUNC symbol must go through PLT. */
8859 if ((symbol_get_bfdsym (fr_symbol)->flags
8860 & BSF_GNU_INDIRECT_FUNCTION) != 0)
8861 return 0;
8862
8863 if (!S_IS_EXTERNAL (fr_symbol))
8864 /* Symbol may be weak or local. */
8865 return !S_IS_WEAK (fr_symbol);
8866
8dcea932
L		 8867 /* Global symbols with non-default visibility can't be preempted. */
8868 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
8869 return 1;
8870
8871 if (fr_var != NO_RELOC)
8872 switch ((enum bfd_reloc_code_real) fr_var)
8873 {
8874 case BFD_RELOC_386_PLT32:
8875 case BFD_RELOC_X86_64_PLT32:
8876 /* Symbol with PLT relocatin may be preempted. */
8877 return 0;
8878 default:
8879 abort ();
8880 }
8881
b084df0b
L		 8882 /* Global symbols with default visibility in a shared library may be
8883 preempted by another definition. */
8dcea932 8884 return !shared;
b084df0b
L		 8885}
8886#endif
8887
ee7fcc42
AM		 8888/* md_estimate_size_before_relax()
8889
8890 Called just before relax() for rs_machine_dependent frags. The x86
8891 assembler uses these frags to handle variable size jump
8892 instructions.
8893
8894 Any symbol that is now undefined will not become defined.
8895 Return the correct fr_subtype in the frag.
8896 Return the initial "guess for variable size of frag" to caller.
8897 The guess is actually the growth beyond the fixed part. Whatever
8898 we do to grow the fixed or variable part contributes to our
8899 returned value. */
8900
252b5132 8901int
7016a5d5 8902md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 8903{
252b5132 8904 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 8905 check for un-relaxable symbols. On an ELF system, we can't relax
8906 an externally visible symbol, because it may be overridden by a
8907 shared library. */
8908 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 8909#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 8910 || (IS_ELF
8dcea932
L		 8911 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
8912 fragP->fr_var))
fbeb56a4
DK		 8913#endif
8914#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 8915 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 8916 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 8917#endif
8918 )
252b5132 8919 {
b98ef147
AM		 8920 /* Symbol is undefined in this segment, or we need to keep a
8921 reloc so that weak symbols can be overridden. */
8922 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 8923 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 8924 unsigned char *opcode;
8925 int old_fr_fix;
f6af82bd 8926
ee7fcc42 8927 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 8928 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 8929 else if (size == 2)
f6af82bd
AM		 8930 reloc_type = BFD_RELOC_16_PCREL;
8931 else
8932 reloc_type = BFD_RELOC_32_PCREL;
252b5132 8933
ee7fcc42
AM		 8934 old_fr_fix = fragP->fr_fix;
8935 opcode = (unsigned char *) fragP->fr_opcode;
8936
fddf5b5b 8937 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 8938 {
fddf5b5b
AM		 8939 case UNCOND_JUMP:
8940 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 8941 opcode[0] = 0xe9;
252b5132 8942 fragP->fr_fix += size;
062cd5e7
AS		 8943 fix_new (fragP, old_fr_fix, size,
8944 fragP->fr_symbol,
8945 fragP->fr_offset, 1,
8946 reloc_type);
252b5132
RH		 8947 break;
8948
fddf5b5b 8949 case COND_JUMP86:
412167cb
AM		 8950 if (size == 2
8951 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 8952 {
8953 /* Negate the condition, and branch past an
8954 unconditional jump. */
8955 opcode[0] ^= 1;
8956 opcode[1] = 3;
8957 /* Insert an unconditional jump. */
8958 opcode[2] = 0xe9;
8959 /* We added two extra opcode bytes, and have a two byte
8960 offset. */
8961 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 8962 fix_new (fragP, old_fr_fix + 2, 2,
8963 fragP->fr_symbol,
8964 fragP->fr_offset, 1,
8965 reloc_type);
fddf5b5b
AM		 8966 break;
8967 }
8968 /* Fall through. */
8969
8970 case COND_JUMP:
412167cb
AM		 8971 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
8972 {
3e02c1cc
AM		 8973 fixS *fixP;
8974
412167cb 8975 fragP->fr_fix += 1;
3e02c1cc
AM		 8976 fixP = fix_new (fragP, old_fr_fix, 1,
8977 fragP->fr_symbol,
8978 fragP->fr_offset, 1,
8979 BFD_RELOC_8_PCREL);
8980 fixP->fx_signed = 1;
412167cb
AM		 8981 break;
8982 }
93c2a809 8983
24eab124 8984 /* This changes the byte-displacement jump 0x7N
fddf5b5b 8985 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 8986 opcode[1] = opcode[0] + 0x10;
f6af82bd 8987 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 8988 /* We've added an opcode byte. */
8989 fragP->fr_fix += 1 + size;
062cd5e7
AS		 8990 fix_new (fragP, old_fr_fix + 1, size,
8991 fragP->fr_symbol,
8992 fragP->fr_offset, 1,
8993 reloc_type);
252b5132 8994 break;
fddf5b5b
AM		 8995
8996 default:
8997 BAD_CASE (fragP->fr_subtype);
8998 break;
252b5132
RH		 8999 }
9000 frag_wane (fragP);
ee7fcc42 9001 return fragP->fr_fix - old_fr_fix;
252b5132 9002 }
93c2a809 9003
93c2a809
AM		 9004 /* Guess size depending on current relax state. Initially the relax
9005 state will correspond to a short jump and we return 1, because
9006 the variable part of the frag (the branch offset) is one byte
9007 long. However, we can relax a section more than once and in that
9008 case we must either set fr_subtype back to the unrelaxed state,
9009 or return the value for the appropriate branch. */
9010 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 9011}
9012
47926f60
KH		 9013/* Called after relax() is finished.
9014
9015 In: Address of frag.
9016 fr_type == rs_machine_dependent.
9017 fr_subtype is what the address relaxed to.
9018
9019 Out: Any fixSs and constants are set up.
9020 Caller will turn frag into a ".space 0". */
9021
252b5132 9022void
7016a5d5
TG		 9023md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9024 fragS *fragP)
252b5132 9025{
29b0f896 9026 unsigned char *opcode;
252b5132 9027 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9028 offsetT target_address;
9029 offsetT opcode_address;
252b5132 9030 unsigned int extension = 0;
847f7ad4 9031 offsetT displacement_from_opcode_start;
252b5132
RH		 9032
9033 opcode = (unsigned char *) fragP->fr_opcode;
9034
47926f60 9035 /* Address we want to reach in file space. */
252b5132 9036 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9037
47926f60 9038 /* Address opcode resides at in file space. */
252b5132
RH		 9039 opcode_address = fragP->fr_address + fragP->fr_fix;
9040
47926f60 9041 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9042 displacement_from_opcode_start = target_address - opcode_address;
9043
fddf5b5b 9044 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9045 {
47926f60
KH		 9046 /* Don't have to change opcode. */
9047 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9048 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9049 }
9050 else
9051 {
9052 if (no_cond_jump_promotion
9053 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9054 as_warn_where (fragP->fr_file, fragP->fr_line,
9055 _("long jump required"));
252b5132 9056
fddf5b5b
AM		 9057 switch (fragP->fr_subtype)
9058 {
9059 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9060 extension = 4; /* 1 opcode + 4 displacement */
9061 opcode[0] = 0xe9;
9062 where_to_put_displacement = &opcode[1];
9063 break;
252b5132 9064
fddf5b5b
AM		 9065 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9066 extension = 2; /* 1 opcode + 2 displacement */
9067 opcode[0] = 0xe9;
9068 where_to_put_displacement = &opcode[1];
9069 break;
252b5132 9070
fddf5b5b
AM		 9071 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9072 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9073 extension = 5; /* 2 opcode + 4 displacement */
9074 opcode[1] = opcode[0] + 0x10;
9075 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9076 where_to_put_displacement = &opcode[2];
9077 break;
252b5132 9078
fddf5b5b
AM		 9079 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9080 extension = 3; /* 2 opcode + 2 displacement */
9081 opcode[1] = opcode[0] + 0x10;
9082 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9083 where_to_put_displacement = &opcode[2];
9084 break;
252b5132 9085
fddf5b5b
AM		 9086 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9087 extension = 4;
9088 opcode[0] ^= 1;
9089 opcode[1] = 3;
9090 opcode[2] = 0xe9;
9091 where_to_put_displacement = &opcode[3];
9092 break;
9093
9094 default:
9095 BAD_CASE (fragP->fr_subtype);
9096 break;
9097 }
252b5132 9098 }
fddf5b5b 9099
7b81dfbb
AJ		 9100 /* If size if less then four we are sure that the operand fits,
9101 but if it's 4, then it could be that the displacement is larger
9102 then -/+ 2GB. */
9103 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9104 && object_64bit
9105 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9106 + ((addressT) 1 << 31))
9107 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9108 {
9109 as_bad_where (fragP->fr_file, fragP->fr_line,
9110 _("jump target out of range"));
9111 /* Make us emit 0. */
9112 displacement_from_opcode_start = extension;
9113 }
47926f60 9114 /* Now put displacement after opcode. */
252b5132
RH		 9115 md_number_to_chars ((char *) where_to_put_displacement,
9116 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9117 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9118 fragP->fr_fix += extension;
9119}
9120\f
7016a5d5 9121/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9122 by our caller that we have all the info we need to fix it up.
9123
7016a5d5
TG		 9124 Parameter valP is the pointer to the value of the bits.
9125
252b5132
RH		 9126 On the 386, immediates, displacements, and data pointers are all in
9127 the same (little-endian) format, so we don't need to care about which
9128 we are handling. */
9129
94f592af 9130void
7016a5d5 9131md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9132{
94f592af 9133 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9134 valueT value = *valP;
252b5132 9135
f86103b7 9136#if !defined (TE_Mach)
93382f6d
AM		 9137 if (fixP->fx_pcrel)
9138 {
9139 switch (fixP->fx_r_type)
9140 {
5865bb77
ILT		 9141 default:
9142 break;
9143
d6ab8113
JB		 9144 case BFD_RELOC_64:
9145 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9146 break;
93382f6d 9147 case BFD_RELOC_32:
ae8887b5 9148 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9149 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9150 break;
9151 case BFD_RELOC_16:
9152 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9153 break;
9154 case BFD_RELOC_8:
9155 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9156 break;
9157 }
9158 }
252b5132 9159
a161fe53 9160 if (fixP->fx_addsy != NULL
31312f95 9161 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9162 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9163 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 9164 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 9165 && !use_rela_relocations)
252b5132 9166 {
31312f95
AM		 9167 /* This is a hack. There should be a better way to handle this.
9168 This covers for the fact that bfd_install_relocation will
9169 subtract the current location (for partial_inplace, PC relative
9170 relocations); see more below. */
252b5132 9171#ifndef OBJ_AOUT
718ddfc0 9172 if (IS_ELF
252b5132
RH		 9173#ifdef TE_PE
9174 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9175#endif
9176 )
9177 value += fixP->fx_where + fixP->fx_frag->fr_address;
9178#endif
9179#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9180 if (IS_ELF)
252b5132 9181 {
6539b54b 9182 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9183
6539b54b 9184 if ((sym_seg == seg
2f66722d 9185 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9186 && sym_seg != absolute_section))
af65af87 9187 && !generic_force_reloc (fixP))
2f66722d
AM		 9188 {
9189 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9190 bfd_install_relocation subtracts them out again. I think
9191 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9192 it. FIXME. */
9193 value += fixP->fx_where + fixP->fx_frag->fr_address;
9194 }
252b5132
RH		 9195 }
9196#endif
9197#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9198 /* For some reason, the PE format does not store a
9199 section address offset for a PC relative symbol. */
9200 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9201 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9202 value += md_pcrel_from (fixP);
9203#endif
9204 }
fbeb56a4 9205#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9206 if (fixP->fx_addsy != NULL
9207 && S_IS_WEAK (fixP->fx_addsy)
9208 /* PR 16858: Do not modify weak function references. */
9209 && ! fixP->fx_pcrel)
fbeb56a4 9210 {
296a8689
NC		 9211#if !defined (TE_PEP)
9212 /* For x86 PE weak function symbols are neither PC-relative
9213 nor do they set S_IS_FUNCTION. So the only reliable way
9214 to detect them is to check the flags of their containing
9215 section. */
9216 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9217 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9218 ;
9219 else
9220#endif
fbeb56a4
DK		 9221 value -= S_GET_VALUE (fixP->fx_addsy);
9222 }
9223#endif
252b5132
RH		 9224
9225 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9226 and we must not disappoint it. */
252b5132 9227#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9228 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9229 switch (fixP->fx_r_type)
9230 {
9231 case BFD_RELOC_386_PLT32:
3e73aa7c 9232 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 9233 /* Make the jump instruction point to the address of the operand. At
9234 runtime we merely add the offset to the actual PLT entry. */
9235 value = -4;
9236 break;
31312f95 9237
13ae64f3
JJ		 9238 case BFD_RELOC_386_TLS_GD:
9239 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9240 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9241 case BFD_RELOC_386_TLS_IE:
9242 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9243 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9244 case BFD_RELOC_X86_64_TLSGD:
9245 case BFD_RELOC_X86_64_TLSLD:
9246 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9247 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9248 value = 0; /* Fully resolved at runtime. No addend. */
9249 /* Fallthrough */
9250 case BFD_RELOC_386_TLS_LE:
9251 case BFD_RELOC_386_TLS_LDO_32:
9252 case BFD_RELOC_386_TLS_LE_32:
9253 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9254 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9255 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9256 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9257 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9258 break;
9259
67a4f2b7
AO		 9260 case BFD_RELOC_386_TLS_DESC_CALL:
9261 case BFD_RELOC_X86_64_TLSDESC_CALL:
9262 value = 0; /* Fully resolved at runtime. No addend. */
9263 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9264 fixP->fx_done = 0;
9265 return;
9266
00f7efb6
JJ		 9267 case BFD_RELOC_386_GOT32:
9268 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 9269 value = 0; /* Fully resolved at runtime. No addend. */
9270 break;
47926f60
KH		 9271
9272 case BFD_RELOC_VTABLE_INHERIT:
9273 case BFD_RELOC_VTABLE_ENTRY:
9274 fixP->fx_done = 0;
94f592af 9275 return;
47926f60
KH		 9276
9277 default:
9278 break;
9279 }
9280#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9281 *valP = value;
f86103b7 9282#endif /* !defined (TE_Mach) */
3e73aa7c 9283
3e73aa7c 9284 /* Are we finished with this relocation now? */
c6682705 9285 if (fixP->fx_addsy == NULL)
3e73aa7c 9286 fixP->fx_done = 1;
fbeb56a4
DK		 9287#if defined (OBJ_COFF) && defined (TE_PE)
9288 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9289 {
9290 fixP->fx_done = 0;
9291 /* Remember value for tc_gen_reloc. */
9292 fixP->fx_addnumber = value;
9293 /* Clear out the frag for now. */
9294 value = 0;
9295 }
9296#endif
3e73aa7c
JH		 9297 else if (use_rela_relocations)
9298 {
9299 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9300 /* Remember value for tc_gen_reloc. */
9301 fixP->fx_addnumber = value;
3e73aa7c
JH		 9302 value = 0;
9303 }
f86103b7 9304
94f592af 9305 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9306}
252b5132 9307\f
252b5132 9308char *
499ac353 9309md_atof (int type, char *litP, int *sizeP)
252b5132 9310{
499ac353
NC		 9311 /* This outputs the LITTLENUMs in REVERSE order;
9312 in accord with the bigendian 386. */
9313 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9314}
9315\f
2d545b82 9316static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9317
252b5132 9318static char *
e3bb37b5 9319output_invalid (int c)
252b5132 9320{
3882b010 9321 if (ISPRINT (c))
f9f21a03
L		 9322 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9323 "'%c'", c);
252b5132 9324 else
f9f21a03 9325 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9326 "(0x%x)", (unsigned char) c);
252b5132
RH		 9327 return output_invalid_buf;
9328}
9329
af6bdddf 9330/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9331
9332static const reg_entry *
4d1bb795 9333parse_real_register (char *reg_string, char **end_op)
252b5132 9334{
af6bdddf
AM		 9335 char *s = reg_string;
9336 char *p;
252b5132
RH		 9337 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9338 const reg_entry *r;
9339
9340 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9341 if (*s == REGISTER_PREFIX)
9342 ++s;
9343
9344 if (is_space_char (*s))
9345 ++s;
9346
9347 p = reg_name_given;
af6bdddf 9348 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9349 {
9350 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9351 return (const reg_entry *) NULL;
9352 s++;
252b5132
RH		 9353 }
9354
6588847e
DN		 9355 /* For naked regs, make sure that we are not dealing with an identifier.
9356 This prevents confusing an identifier like `eax_var' with register
9357 `eax'. */
9358 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9359 return (const reg_entry *) NULL;
9360
af6bdddf 9361 *end_op = s;
252b5132
RH		 9362
9363 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9364
5f47d35b 9365 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9366 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9367 {
5f47d35b
AM		 9368 if (is_space_char (*s))
9369 ++s;
9370 if (*s == '(')
9371 {
af6bdddf 9372 ++s;
5f47d35b
AM		 9373 if (is_space_char (*s))
9374 ++s;
9375 if (*s >= '0' && *s <= '7')
9376 {
db557034 9377 int fpr = *s - '0';
af6bdddf 9378 ++s;
5f47d35b
AM		 9379 if (is_space_char (*s))
9380 ++s;
9381 if (*s == ')')
9382 {
9383 *end_op = s + 1;
1e9cc1c2 9384 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9385 know (r);
9386 return r + fpr;
5f47d35b 9387 }
5f47d35b 9388 }
47926f60 9389 /* We have "%st(" then garbage. */
5f47d35b
AM		 9390 return (const reg_entry *) NULL;
9391 }
9392 }
9393
a60de03c
JB		 9394 if (r == NULL || allow_pseudo_reg)
9395 return r;
9396
0dfbf9d7 9397 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9398 return (const reg_entry *) NULL;
9399
192dc9c6
JB		 9400 if ((r->reg_type.bitfield.reg32
9401 || r->reg_type.bitfield.sreg3
9402 || r->reg_type.bitfield.control
9403 || r->reg_type.bitfield.debug
9404 || r->reg_type.bitfield.test)
9405 && !cpu_arch_flags.bitfield.cpui386)
9406 return (const reg_entry *) NULL;
9407
309d3373
JB		 9408 if (r->reg_type.bitfield.floatreg
9409 && !cpu_arch_flags.bitfield.cpu8087
9410 && !cpu_arch_flags.bitfield.cpu287
9411 && !cpu_arch_flags.bitfield.cpu387)
9412 return (const reg_entry *) NULL;
9413
192dc9c6
JB		 9414 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
9415 return (const reg_entry *) NULL;
9416
9417 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
9418 return (const reg_entry *) NULL;
9419
40f12533
L		 9420 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
9421 return (const reg_entry *) NULL;
9422
43234a1e
L		 9423 if ((r->reg_type.bitfield.regzmm || r->reg_type.bitfield.regmask)
9424 && !cpu_arch_flags.bitfield.cpuavx512f)
9425 return (const reg_entry *) NULL;
9426
db51cc60 9427 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9428 if (!allow_index_reg
db51cc60
L		 9429 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9430 return (const reg_entry *) NULL;
9431
43234a1e
L		 9432 /* Upper 16 vector register is only available with VREX in 64bit
9433 mode. */
9434 if ((r->reg_flags & RegVRex))
9435 {
9436 if (!cpu_arch_flags.bitfield.cpuvrex
9437 || flag_code != CODE_64BIT)
9438 return (const reg_entry *) NULL;
9439
9440 i.need_vrex = 1;
9441 }
9442
a60de03c
JB		 9443 if (((r->reg_flags & (RegRex64 | RegRex))
9444 || r->reg_type.bitfield.reg64)
40fb9820 9445 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9446 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9447 && flag_code != CODE_64BIT)
20f0a1fc 9448 return (const reg_entry *) NULL;
1ae00879 9449
b7240065
JB		 9450 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9451 return (const reg_entry *) NULL;
9452
252b5132
RH		 9453 return r;
9454}
4d1bb795
JB		 9455
9456/* REG_STRING starts *before* REGISTER_PREFIX. */
9457
9458static const reg_entry *
9459parse_register (char *reg_string, char **end_op)
9460{
9461 const reg_entry *r;
9462
9463 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9464 r = parse_real_register (reg_string, end_op);
9465 else
9466 r = NULL;
9467 if (!r)
9468 {
9469 char *save = input_line_pointer;
9470 char c;
9471 symbolS *symbolP;
9472
9473 input_line_pointer = reg_string;
9474 c = get_symbol_end ();
9475 symbolP = symbol_find (reg_string);
9476 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9477 {
9478 const expressionS *e = symbol_get_value_expression (symbolP);
9479
0398aac5 9480 know (e->X_op == O_register);
4eed87de 9481 know (e->X_add_number >= 0
c3fe08fa 9482 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 9483 r = i386_regtab + e->X_add_number;
d3bb6b49
IT		 9484 if ((r->reg_flags & RegVRex))
9485 i.need_vrex = 1;
4d1bb795
JB		 9486 *end_op = input_line_pointer;
9487 }
9488 *input_line_pointer = c;
9489 input_line_pointer = save;
9490 }
9491 return r;
9492}
9493
9494int
9495i386_parse_name (char *name, expressionS *e, char *nextcharP)
9496{
9497 const reg_entry *r;
9498 char *end = input_line_pointer;
9499
9500 *end = *nextcharP;
9501 r = parse_register (name, &input_line_pointer);
9502 if (r && end <= input_line_pointer)
9503 {
9504 *nextcharP = *input_line_pointer;
9505 *input_line_pointer = 0;
9506 e->X_op = O_register;
9507 e->X_add_number = r - i386_regtab;
9508 return 1;
9509 }
9510 input_line_pointer = end;
9511 *end = 0;
ee86248c 9512 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9513}
9514
9515void
9516md_operand (expressionS *e)
9517{
ee86248c
JB		 9518 char *end;
9519 const reg_entry *r;
4d1bb795 9520
ee86248c
JB		 9521 switch (*input_line_pointer)
9522 {
9523 case REGISTER_PREFIX:
9524 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9525 if (r)
9526 {
9527 e->X_op = O_register;
9528 e->X_add_number = r - i386_regtab;
9529 input_line_pointer = end;
9530 }
ee86248c
JB		 9531 break;
9532
9533 case '[':
9c2799c2 9534 gas_assert (intel_syntax);
ee86248c
JB		 9535 end = input_line_pointer++;
9536 expression (e);
9537 if (*input_line_pointer == ']')
9538 {
9539 ++input_line_pointer;
9540 e->X_op_symbol = make_expr_symbol (e);
9541 e->X_add_symbol = NULL;
9542 e->X_add_number = 0;
9543 e->X_op = O_index;
9544 }
9545 else
9546 {
9547 e->X_op = O_absent;
9548 input_line_pointer = end;
9549 }
9550 break;
4d1bb795
JB		 9551 }
9552}
9553
252b5132 9554\f
4cc782b5 9555#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9556const char *md_shortopts = "kVQ:sqn";
252b5132 9557#else
12b55ccc 9558const char *md_shortopts = "qn";
252b5132 9559#endif
6e0b89ee 9560
3e73aa7c 9561#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9562#define OPTION_64 (OPTION_MD_BASE + 1)
9563#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9564#define OPTION_MARCH (OPTION_MD_BASE + 3)
9565#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9566#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9567#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9568#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9569#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9570#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9571#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9572#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9573#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9574#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9575#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9576#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9577#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9578#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 9579#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
a5094208 9580#define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 9581#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
8dcea932 9582#define OPTION_MSHARED (OPTION_MD_BASE + 21)
5db04b09
L		 9583#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9584#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
b3b91714 9585
99ad8390
NC		 9586struct option md_longopts[] =
9587{
3e73aa7c 9588 {"32", no_argument, NULL, OPTION_32},
321098a5 9589#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9590 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9591 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 9592#endif
9593#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9594 {"x32", no_argument, NULL, OPTION_X32},
8dcea932 9595 {"mshared", no_argument, NULL, OPTION_MSHARED},
6e0b89ee 9596#endif
b3b91714 9597 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 9598 {"march", required_argument, NULL, OPTION_MARCH},
9599 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 9600 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9601 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9602 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9603 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9604 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 9605 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 9606 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 9607 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 9608 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 9609 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 9610 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9611 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 9612# if defined (TE_PE) || defined (TE_PEP)
9613 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
9614#endif
a5094208 9615 {"momit-lock-prefix", required_argument, NULL, OPTION_OMIT_LOCK_PREFIX},
d3d3c6db 9616 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
5db04b09
L		 9617 {"mamd64", no_argument, NULL, OPTION_MAMD64},
9618 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
252b5132
RH		 9619 {NULL, no_argument, NULL, 0}
9620};
9621size_t md_longopts_size = sizeof (md_longopts);
9622
9623int
9103f4f4 9624md_parse_option (int c, char *arg)
252b5132 9625{
91d6fa6a 9626 unsigned int j;
6305a203 9627 char *arch, *next;
9103f4f4 9628
252b5132
RH		 9629 switch (c)
9630 {
12b55ccc
L		 9631 case 'n':
9632 optimize_align_code = 0;
9633 break;
9634
a38cf1db
AM		 9635 case 'q':
9636 quiet_warnings = 1;
252b5132
RH		 9637 break;
9638
9639#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 9640 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9641 should be emitted or not. FIXME: Not implemented. */
9642 case 'Q':
252b5132
RH		 9643 break;
9644
9645 /* -V: SVR4 argument to print version ID. */
9646 case 'V':
9647 print_version_id ();
9648 break;
9649
a38cf1db
AM		 9650 /* -k: Ignore for FreeBSD compatibility. */
9651 case 'k':
252b5132 9652 break;
4cc782b5
ILT		 9653
9654 case 's':
9655 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 9656 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 9657 break;
8dcea932
L		 9658
9659 case OPTION_MSHARED:
9660 shared = 1;
9661 break;
99ad8390 9662#endif
321098a5 9663#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9664 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 9665 case OPTION_64:
9666 {
9667 const char **list, **l;
9668
3e73aa7c
JH		 9669 list = bfd_target_list ();
9670 for (l = list; *l != NULL; l++)
8620418b 9671 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 9672 || strcmp (*l, "coff-x86-64") == 0
9673 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 9674 || strcmp (*l, "pei-x86-64") == 0
9675 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 9676 {
9677 default_arch = "x86_64";
9678 break;
9679 }
3e73aa7c 9680 if (*l == NULL)
2b5d6a91 9681 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 9682 free (list);
9683 }
9684 break;
9685#endif
252b5132 9686
351f65ca 9687#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9688 case OPTION_X32:
351f65ca
L		 9689 if (IS_ELF)
9690 {
9691 const char **list, **l;
9692
9693 list = bfd_target_list ();
9694 for (l = list; *l != NULL; l++)
9695 if (CONST_STRNEQ (*l, "elf32-x86-64"))
9696 {
9697 default_arch = "x86_64:32";
9698 break;
9699 }
9700 if (*l == NULL)
2b5d6a91 9701 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 9702 free (list);
9703 }
9704 else
9705 as_fatal (_("32bit x86_64 is only supported for ELF"));
9706 break;
9707#endif
9708
6e0b89ee
AM		 9709 case OPTION_32:
9710 default_arch = "i386";
9711 break;
9712
b3b91714
AM		 9713 case OPTION_DIVIDE:
9714#ifdef SVR4_COMMENT_CHARS
9715 {
9716 char *n, *t;
9717 const char *s;
9718
9719 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
9720 t = n;
9721 for (s = i386_comment_chars; *s != '\0'; s++)
9722 if (*s != '/')
9723 *t++ = *s;
9724 *t = '\0';
9725 i386_comment_chars = n;
9726 }
9727#endif
9728 break;
9729
9103f4f4 9730 case OPTION_MARCH:
6305a203
L		 9731 arch = xstrdup (arg);
9732 do
9103f4f4 9733 {
6305a203 9734 if (*arch == '.')
2b5d6a91 9735 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9736 next = strchr (arch, '+');
9737 if (next)
9738 *next++ = '\0';
91d6fa6a 9739 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9740 {
91d6fa6a 9741 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 9742 {
6305a203 9743 /* Processor. */
1ded5609
JB		 9744 if (! cpu_arch[j].flags.bitfield.cpui386)
9745 continue;
9746
91d6fa6a 9747 cpu_arch_name = cpu_arch[j].name;
6305a203 9748 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 9749 cpu_arch_flags = cpu_arch[j].flags;
9750 cpu_arch_isa = cpu_arch[j].type;
9751 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 9752 if (!cpu_arch_tune_set)
9753 {
9754 cpu_arch_tune = cpu_arch_isa;
9755 cpu_arch_tune_flags = cpu_arch_isa_flags;
9756 }
9757 break;
9758 }
91d6fa6a
NC		 9759 else if (*cpu_arch [j].name == '.'
9760 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 9761 {
9762 /* ISA entension. */
9763 i386_cpu_flags flags;
309d3373 9764
49021df2 9765 if (!cpu_arch[j].negated)
309d3373 9766 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 9767 cpu_arch[j].flags);
309d3373
JB		 9768 else
9769 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 9770 cpu_arch[j].flags);
81486035
L		 9771
9772 if (!valid_iamcu_cpu_flags (&flags))
9773 as_fatal (_("`%s' isn't valid for Intel MCU"), arch);
9774 else if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 9775 {
9776 if (cpu_sub_arch_name)
9777 {
9778 char *name = cpu_sub_arch_name;
9779 cpu_sub_arch_name = concat (name,
91d6fa6a 9780 cpu_arch[j].name,
1bf57e9f 9781 (const char *) NULL);
6305a203
L		 9782 free (name);
9783 }
9784 else
91d6fa6a 9785 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 9786 cpu_arch_flags = flags;
a586129e 9787 cpu_arch_isa_flags = flags;
6305a203
L		 9788 }
9789 break;
ccc9c027 9790 }
9103f4f4 9791 }
6305a203 9792
91d6fa6a 9793 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9794 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9795
9796 arch = next;
9103f4f4 9797 }
6305a203 9798 while (next != NULL );
9103f4f4
L		 9799 break;
9800
9801 case OPTION_MTUNE:
9802 if (*arg == '.')
2b5d6a91 9803 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 9804 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9805 {
91d6fa6a 9806 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 9807 {
ccc9c027 9808 cpu_arch_tune_set = 1;
91d6fa6a
NC		 9809 cpu_arch_tune = cpu_arch [j].type;
9810 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 9811 break;
9812 }
9813 }
91d6fa6a 9814 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9815 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 9816 break;
9817
1efbbeb4
L		 9818 case OPTION_MMNEMONIC:
9819 if (strcasecmp (arg, "att") == 0)
9820 intel_mnemonic = 0;
9821 else if (strcasecmp (arg, "intel") == 0)
9822 intel_mnemonic = 1;
9823 else
2b5d6a91 9824 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 9825 break;
9826
9827 case OPTION_MSYNTAX:
9828 if (strcasecmp (arg, "att") == 0)
9829 intel_syntax = 0;
9830 else if (strcasecmp (arg, "intel") == 0)
9831 intel_syntax = 1;
9832 else
2b5d6a91 9833 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 9834 break;
9835
9836 case OPTION_MINDEX_REG:
9837 allow_index_reg = 1;
9838 break;
9839
9840 case OPTION_MNAKED_REG:
9841 allow_naked_reg = 1;
9842 break;
9843
9844 case OPTION_MOLD_GCC:
9845 old_gcc = 1;
1efbbeb4
L		 9846 break;
9847
c0f3af97
L		 9848 case OPTION_MSSE2AVX:
9849 sse2avx = 1;
9850 break;
9851
daf50ae7
L		 9852 case OPTION_MSSE_CHECK:
9853 if (strcasecmp (arg, "error") == 0)
7bab8ab5 9854 sse_check = check_error;
daf50ae7 9855 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 9856 sse_check = check_warning;
daf50ae7 9857 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 9858 sse_check = check_none;
daf50ae7 9859 else
2b5d6a91 9860 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 9861 break;
9862
7bab8ab5
JB		 9863 case OPTION_MOPERAND_CHECK:
9864 if (strcasecmp (arg, "error") == 0)
9865 operand_check = check_error;
9866 else if (strcasecmp (arg, "warning") == 0)
9867 operand_check = check_warning;
9868 else if (strcasecmp (arg, "none") == 0)
9869 operand_check = check_none;
9870 else
9871 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
9872 break;
9873
539f890d
L		 9874 case OPTION_MAVXSCALAR:
9875 if (strcasecmp (arg, "128") == 0)
9876 avxscalar = vex128;
9877 else if (strcasecmp (arg, "256") == 0)
9878 avxscalar = vex256;
9879 else
2b5d6a91 9880 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 9881 break;
9882
7e8b059b
L		 9883 case OPTION_MADD_BND_PREFIX:
9884 add_bnd_prefix = 1;
9885 break;
9886
43234a1e
L		 9887 case OPTION_MEVEXLIG:
9888 if (strcmp (arg, "128") == 0)
9889 evexlig = evexl128;
9890 else if (strcmp (arg, "256") == 0)
9891 evexlig = evexl256;
9892 else if (strcmp (arg, "512") == 0)
9893 evexlig = evexl512;
9894 else
9895 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
9896 break;
9897
d3d3c6db
IT		 9898 case OPTION_MEVEXRCIG:
9899 if (strcmp (arg, "rne") == 0)
9900 evexrcig = rne;
9901 else if (strcmp (arg, "rd") == 0)
9902 evexrcig = rd;
9903 else if (strcmp (arg, "ru") == 0)
9904 evexrcig = ru;
9905 else if (strcmp (arg, "rz") == 0)
9906 evexrcig = rz;
9907 else
9908 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
9909 break;
9910
43234a1e
L		 9911 case OPTION_MEVEXWIG:
9912 if (strcmp (arg, "0") == 0)
9913 evexwig = evexw0;
9914 else if (strcmp (arg, "1") == 0)
9915 evexwig = evexw1;
9916 else
9917 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
9918 break;
9919
167ad85b
TG		 9920# if defined (TE_PE) || defined (TE_PEP)
9921 case OPTION_MBIG_OBJ:
9922 use_big_obj = 1;
9923 break;
9924#endif
9925
a5094208 9926 case OPTION_OMIT_LOCK_PREFIX:
d022bddd
IT		 9927 if (strcasecmp (arg, "yes") == 0)
9928 omit_lock_prefix = 1;
9929 else if (strcasecmp (arg, "no") == 0)
9930 omit_lock_prefix = 0;
9931 else
9932 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
9933 break;
9934
5db04b09
L		 9935 case OPTION_MAMD64:
9936 cpu_arch_flags.bitfield.cpuamd64 = 1;
9937 cpu_arch_flags.bitfield.cpuintel64 = 0;
9938 cpu_arch_isa_flags.bitfield.cpuamd64 = 1;
9939 cpu_arch_isa_flags.bitfield.cpuintel64 = 0;
9940 break;
9941
9942 case OPTION_MINTEL64:
9943 cpu_arch_flags.bitfield.cpuamd64 = 0;
9944 cpu_arch_flags.bitfield.cpuintel64 = 1;
9945 cpu_arch_isa_flags.bitfield.cpuamd64 = 0;
9946 cpu_arch_isa_flags.bitfield.cpuintel64 = 1;
9947 break;
9948
252b5132
RH		 9949 default:
9950 return 0;
9951 }
9952 return 1;
9953}
9954
8a2c8fef
L		 9955#define MESSAGE_TEMPLATE \
9956" "
9957
9958static void
1ded5609 9959show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 9960{
9961 static char message[] = MESSAGE_TEMPLATE;
9962 char *start = message + 27;
9963 char *p;
9964 int size = sizeof (MESSAGE_TEMPLATE);
9965 int left;
9966 const char *name;
9967 int len;
9968 unsigned int j;
9969
9970 p = start;
9971 left = size - (start - message);
9972 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9973 {
9974 /* Should it be skipped? */
9975 if (cpu_arch [j].skip)
9976 continue;
9977
9978 name = cpu_arch [j].name;
9979 len = cpu_arch [j].len;
9980 if (*name == '.')
9981 {
9982 /* It is an extension. Skip if we aren't asked to show it. */
9983 if (ext)
9984 {
9985 name++;
9986 len--;
9987 }
9988 else
9989 continue;
9990 }
9991 else if (ext)
9992 {
9993 /* It is an processor. Skip if we show only extension. */
9994 continue;
9995 }
1ded5609
JB		 9996 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
9997 {
9998 /* It is an impossible processor - skip. */
9999 continue;
10000 }
8a2c8fef
L		 10001
10002 /* Reserve 2 spaces for ", " or ",\0" */
10003 left -= len + 2;
10004
10005 /* Check if there is any room. */
10006 if (left >= 0)
10007 {
10008 if (p != start)
10009 {
10010 *p++ = ',';
10011 *p++ = ' ';
10012 }
10013 p = mempcpy (p, name, len);
10014 }
10015 else
10016 {
10017 /* Output the current message now and start a new one. */
10018 *p++ = ',';
10019 *p = '\0';
10020 fprintf (stream, "%s\n", message);
10021 p = start;
10022 left = size - (start - message) - len - 2;
8d63c93e 10023
8a2c8fef
L		 10024 gas_assert (left >= 0);
10025
10026 p = mempcpy (p, name, len);
10027 }
10028 }
10029
10030 *p = '\0';
10031 fprintf (stream, "%s\n", message);
10032}
10033
252b5132 10034void
8a2c8fef 10035md_show_usage (FILE *stream)
252b5132 10036{
4cc782b5
ILT		 10037#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10038 fprintf (stream, _("\
a38cf1db
AM		 10039 -Q ignored\n\
10040 -V print assembler version number\n\
b3b91714
AM		 10041 -k ignored\n"));
10042#endif
10043 fprintf (stream, _("\
12b55ccc 10044 -n Do not optimize code alignment\n\
b3b91714
AM		 10045 -q quieten some warnings\n"));
10046#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10047 fprintf (stream, _("\
a38cf1db 10048 -s ignored\n"));
b3b91714 10049#endif
321098a5
L		 10050#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10051 || defined (TE_PE) || defined (TE_PEP))
751d281c 10052 fprintf (stream, _("\
570561f7 10053 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10054#endif
b3b91714
AM		 10055#ifdef SVR4_COMMENT_CHARS
10056 fprintf (stream, _("\
10057 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10058#else
10059 fprintf (stream, _("\
b3b91714 10060 --divide ignored\n"));
4cc782b5 10061#endif
9103f4f4 10062 fprintf (stream, _("\
6305a203 10063 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10064 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10065 show_arch (stream, 0, 1);
8a2c8fef
L		 10066 fprintf (stream, _("\
10067 EXTENSION is combination of:\n"));
1ded5609 10068 show_arch (stream, 1, 0);
6305a203 10069 fprintf (stream, _("\
8a2c8fef 10070 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10071 show_arch (stream, 0, 0);
ba104c83 10072 fprintf (stream, _("\
c0f3af97
L		 10073 -msse2avx encode SSE instructions with VEX prefix\n"));
10074 fprintf (stream, _("\
daf50ae7
L		 10075 -msse-check=[none|error|warning]\n\
10076 check SSE instructions\n"));
10077 fprintf (stream, _("\
7bab8ab5
JB		 10078 -moperand-check=[none|error|warning]\n\
10079 check operand combinations for validity\n"));
10080 fprintf (stream, _("\
539f890d
L		 10081 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10082 length\n"));
10083 fprintf (stream, _("\
43234a1e
L		 10084 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10085 length\n"));
10086 fprintf (stream, _("\
10087 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10088 for EVEX.W bit ignored instructions\n"));
10089 fprintf (stream, _("\
d3d3c6db
IT		 10090 -mevexrcig=[rne|rd|ru|rz]\n\
10091 encode EVEX instructions with specific EVEX.RC value\n\
10092 for SAE-only ignored instructions\n"));
10093 fprintf (stream, _("\
ba104c83
L		 10094 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10095 fprintf (stream, _("\
10096 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10097 fprintf (stream, _("\
10098 -mindex-reg support pseudo index registers\n"));
10099 fprintf (stream, _("\
10100 -mnaked-reg don't require `%%' prefix for registers\n"));
10101 fprintf (stream, _("\
10102 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 10103 fprintf (stream, _("\
10104 -madd-bnd-prefix add BND prefix for all valid branches\n"));
8dcea932
L		 10105 fprintf (stream, _("\
10106 -mshared disable branch optimization for shared code\n"));
167ad85b
TG		 10107# if defined (TE_PE) || defined (TE_PEP)
10108 fprintf (stream, _("\
10109 -mbig-obj generate big object files\n"));
10110#endif
d022bddd
IT		 10111 fprintf (stream, _("\
10112 -momit-lock-prefix=[no|yes]\n\
10113 strip all lock prefixes\n"));
5db04b09
L		 10114 fprintf (stream, _("\
10115 -mamd64 accept only AMD64 ISA\n"));
10116 fprintf (stream, _("\
10117 -mintel64 accept only Intel64 ISA\n"));
252b5132
RH		 10118}
10119
3e73aa7c 10120#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 10121 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 10122 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 10123
10124/* Pick the target format to use. */
10125
47926f60 10126const char *
e3bb37b5 10127i386_target_format (void)
252b5132 10128{
351f65ca
L		 10129 if (!strncmp (default_arch, "x86_64", 6))
10130 {
10131 update_code_flag (CODE_64BIT, 1);
10132 if (default_arch[6] == '\0')
7f56bc95 10133 x86_elf_abi = X86_64_ABI;
351f65ca 10134 else
7f56bc95 10135 x86_elf_abi = X86_64_X32_ABI;
351f65ca 10136 }
3e73aa7c 10137 else if (!strcmp (default_arch, "i386"))
78f12dd3 10138 update_code_flag (CODE_32BIT, 1);
5197d474
L		 10139 else if (!strcmp (default_arch, "iamcu"))
10140 {
10141 update_code_flag (CODE_32BIT, 1);
10142 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10143 {
10144 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10145 cpu_arch_name = "iamcu";
10146 cpu_sub_arch_name = NULL;
10147 cpu_arch_flags = iamcu_flags;
10148 cpu_arch_isa = PROCESSOR_IAMCU;
10149 cpu_arch_isa_flags = iamcu_flags;
10150 if (!cpu_arch_tune_set)
10151 {
10152 cpu_arch_tune = cpu_arch_isa;
10153 cpu_arch_tune_flags = cpu_arch_isa_flags;
10154 }
10155 }
10156 else
10157 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10158 cpu_arch_name);
10159 }
3e73aa7c 10160 else
2b5d6a91 10161 as_fatal (_("unknown architecture"));
89507696
JB		 10162
10163 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10164 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10165 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10166 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10167
252b5132
RH		 10168 switch (OUTPUT_FLAVOR)
10169 {
9384f2ff 10170#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 10171 case bfd_target_aout_flavour:
47926f60 10172 return AOUT_TARGET_FORMAT;
4c63da97 10173#endif
9384f2ff
AM		 10174#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10175# if defined (TE_PE) || defined (TE_PEP)
10176 case bfd_target_coff_flavour:
167ad85b
TG		 10177 if (flag_code == CODE_64BIT)
10178 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10179 else
10180 return "pe-i386";
9384f2ff 10181# elif defined (TE_GO32)
0561d57c
JK		 10182 case bfd_target_coff_flavour:
10183 return "coff-go32";
9384f2ff 10184# else
252b5132
RH		 10185 case bfd_target_coff_flavour:
10186 return "coff-i386";
9384f2ff 10187# endif
4c63da97 10188#endif
3e73aa7c 10189#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 10190 case bfd_target_elf_flavour:
3e73aa7c 10191 {
351f65ca
L		 10192 const char *format;
10193
10194 switch (x86_elf_abi)
4fa24527 10195 {
351f65ca
L		 10196 default:
10197 format = ELF_TARGET_FORMAT;
10198 break;
7f56bc95 10199 case X86_64_ABI:
351f65ca 10200 use_rela_relocations = 1;
4fa24527 10201 object_64bit = 1;
351f65ca
L		 10202 format = ELF_TARGET_FORMAT64;
10203 break;
7f56bc95 10204 case X86_64_X32_ABI:
4fa24527 10205 use_rela_relocations = 1;
351f65ca 10206 object_64bit = 1;
862be3fb 10207 disallow_64bit_reloc = 1;
351f65ca
L		 10208 format = ELF_TARGET_FORMAT32;
10209 break;
4fa24527 10210 }
3632d14b 10211 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10212 {
7f56bc95 10213 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10214 as_fatal (_("Intel L1OM is 64bit only"));
10215 return ELF_TARGET_L1OM_FORMAT;
10216 }
b49f93f6 10217 else if (cpu_arch_isa == PROCESSOR_K1OM)
7a9068fe
L		 10218 {
10219 if (x86_elf_abi != X86_64_ABI)
10220 as_fatal (_("Intel K1OM is 64bit only"));
10221 return ELF_TARGET_K1OM_FORMAT;
10222 }
81486035
L		 10223 else if (cpu_arch_isa == PROCESSOR_IAMCU)
10224 {
10225 if (x86_elf_abi != I386_ABI)
10226 as_fatal (_("Intel MCU is 32bit only"));
10227 return ELF_TARGET_IAMCU_FORMAT;
10228 }
8a9036a4 10229 else
351f65ca 10230 return format;
3e73aa7c 10231 }
e57f8c65
TG		 10232#endif
10233#if defined (OBJ_MACH_O)
10234 case bfd_target_mach_o_flavour:
d382c579
TG		 10235 if (flag_code == CODE_64BIT)
10236 {
10237 use_rela_relocations = 1;
10238 object_64bit = 1;
10239 return "mach-o-x86-64";
10240 }
10241 else
10242 return "mach-o-i386";
4c63da97 10243#endif
252b5132
RH		 10244 default:
10245 abort ();
10246 return NULL;
10247 }
10248}
10249
47926f60 10250#endif /* OBJ_MAYBE_ more than one */
252b5132 10251\f
252b5132 10252symbolS *
7016a5d5 10253md_undefined_symbol (char *name)
252b5132 10254{
18dc2407
ILT		 10255 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10256 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10257 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10258 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10259 {
10260 if (!GOT_symbol)
10261 {
10262 if (symbol_find (name))
10263 as_bad (_("GOT already in symbol table"));
10264 GOT_symbol = symbol_new (name, undefined_section,
10265 (valueT) 0, &zero_address_frag);
10266 };
10267 return GOT_symbol;
10268 }
252b5132
RH		 10269 return 0;
10270}
10271
10272/* Round up a section size to the appropriate boundary. */
47926f60 10273
252b5132 10274valueT
7016a5d5 10275md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10276{
4c63da97
AM		 10277#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10278 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10279 {
10280 /* For a.out, force the section size to be aligned. If we don't do
10281 this, BFD will align it for us, but it will not write out the
10282 final bytes of the section. This may be a bug in BFD, but it is
10283 easier to fix it here since that is how the other a.out targets
10284 work. */
10285 int align;
10286
10287 align = bfd_get_section_alignment (stdoutput, segment);
10288 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
10289 }
252b5132
RH		 10290#endif
10291
10292 return size;
10293}
10294
10295/* On the i386, PC-relative offsets are relative to the start of the
10296 next instruction. That is, the address of the offset, plus its
10297 size, since the offset is always the last part of the insn. */
10298
10299long
e3bb37b5 10300md_pcrel_from (fixS *fixP)
252b5132
RH		 10301{
10302 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10303}
10304
10305#ifndef I386COFF
10306
10307static void
e3bb37b5 10308s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10309{
29b0f896 10310 int temp;
252b5132 10311
8a75718c
JB		 10312#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10313 if (IS_ELF)
10314 obj_elf_section_change_hook ();
10315#endif
252b5132
RH		 10316 temp = get_absolute_expression ();
10317 subseg_set (bss_section, (subsegT) temp);
10318 demand_empty_rest_of_line ();
10319}
10320
10321#endif
10322
252b5132 10323void
e3bb37b5 10324i386_validate_fix (fixS *fixp)
252b5132
RH		 10325{
10326 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
10327 {
23df1078
JH		 10328 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10329 {
4fa24527 10330 if (!object_64bit)
23df1078
JH		 10331 abort ();
10332 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10333 }
10334 else
10335 {
4fa24527 10336 if (!object_64bit)
d6ab8113
JB		 10337 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10338 else
10339 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 10340 }
252b5132
RH		 10341 fixp->fx_subsy = 0;
10342 }
10343}
10344
252b5132 10345arelent *
7016a5d5 10346tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10347{
10348 arelent *rel;
10349 bfd_reloc_code_real_type code;
10350
10351 switch (fixp->fx_r_type)
10352 {
8ce3d284 10353#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10354 case BFD_RELOC_SIZE32:
10355 case BFD_RELOC_SIZE64:
10356 if (S_IS_DEFINED (fixp->fx_addsy)
10357 && !S_IS_EXTERNAL (fixp->fx_addsy))
10358 {
10359 /* Resolve size relocation against local symbol to size of
10360 the symbol plus addend. */
10361 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10362 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10363 && !fits_in_unsigned_long (value))
10364 as_bad_where (fixp->fx_file, fixp->fx_line,
10365 _("symbol size computation overflow"));
10366 fixp->fx_addsy = NULL;
10367 fixp->fx_subsy = NULL;
10368 md_apply_fix (fixp, (valueT *) &value, NULL);
10369 return NULL;
10370 }
8ce3d284 10371#endif
8fd4256d 10372
3e73aa7c
JH		 10373 case BFD_RELOC_X86_64_PLT32:
10374 case BFD_RELOC_X86_64_GOT32:
10375 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 10376 case BFD_RELOC_386_PLT32:
10377 case BFD_RELOC_386_GOT32:
10378 case BFD_RELOC_386_GOTOFF:
10379 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10380 case BFD_RELOC_386_TLS_GD:
10381 case BFD_RELOC_386_TLS_LDM:
10382 case BFD_RELOC_386_TLS_LDO_32:
10383 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10384 case BFD_RELOC_386_TLS_IE:
10385 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10386 case BFD_RELOC_386_TLS_LE_32:
10387 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10388 case BFD_RELOC_386_TLS_GOTDESC:
10389 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10390 case BFD_RELOC_X86_64_TLSGD:
10391 case BFD_RELOC_X86_64_TLSLD:
10392 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10393 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10394 case BFD_RELOC_X86_64_GOTTPOFF:
10395 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10396 case BFD_RELOC_X86_64_TPOFF64:
10397 case BFD_RELOC_X86_64_GOTOFF64:
10398 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10399 case BFD_RELOC_X86_64_GOT64:
10400 case BFD_RELOC_X86_64_GOTPCREL64:
10401 case BFD_RELOC_X86_64_GOTPC64:
10402 case BFD_RELOC_X86_64_GOTPLT64:
10403 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10404 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10405 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10406 case BFD_RELOC_RVA:
10407 case BFD_RELOC_VTABLE_ENTRY:
10408 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10409#ifdef TE_PE
10410 case BFD_RELOC_32_SECREL:
10411#endif
252b5132
RH		 10412 code = fixp->fx_r_type;
10413 break;
dbbaec26
L		 10414 case BFD_RELOC_X86_64_32S:
10415 if (!fixp->fx_pcrel)
10416 {
10417 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10418 code = fixp->fx_r_type;
10419 break;
10420 }
252b5132 10421 default:
93382f6d 10422 if (fixp->fx_pcrel)
252b5132 10423 {
93382f6d
AM		 10424 switch (fixp->fx_size)
10425 {
10426 default:
b091f402
AM		 10427 as_bad_where (fixp->fx_file, fixp->fx_line,
10428 _("can not do %d byte pc-relative relocation"),
10429 fixp->fx_size);
93382f6d
AM		 10430 code = BFD_RELOC_32_PCREL;
10431 break;
10432 case 1: code = BFD_RELOC_8_PCREL; break;
10433 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 10434 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 10435#ifdef BFD64
10436 case 8: code = BFD_RELOC_64_PCREL; break;
10437#endif
93382f6d
AM		 10438 }
10439 }
10440 else
10441 {
10442 switch (fixp->fx_size)
10443 {
10444 default:
b091f402
AM		 10445 as_bad_where (fixp->fx_file, fixp->fx_line,
10446 _("can not do %d byte relocation"),
10447 fixp->fx_size);
93382f6d
AM		 10448 code = BFD_RELOC_32;
10449 break;
10450 case 1: code = BFD_RELOC_8; break;
10451 case 2: code = BFD_RELOC_16; break;
10452 case 4: code = BFD_RELOC_32; break;
937149dd 10453#ifdef BFD64
3e73aa7c 10454 case 8: code = BFD_RELOC_64; break;
937149dd 10455#endif
93382f6d 10456 }
252b5132
RH		 10457 }
10458 break;
10459 }
252b5132 10460
d182319b
JB		 10461 if ((code == BFD_RELOC_32
10462 || code == BFD_RELOC_32_PCREL
10463 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10464 && GOT_symbol
10465 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10466 {
4fa24527 10467 if (!object_64bit)
d6ab8113
JB		 10468 code = BFD_RELOC_386_GOTPC;
10469 else
10470 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10471 }
7b81dfbb
AJ		 10472 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10473 && GOT_symbol
10474 && fixp->fx_addsy == GOT_symbol)
10475 {
10476 code = BFD_RELOC_X86_64_GOTPC64;
10477 }
252b5132
RH		 10478
10479 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 10480 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
10481 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10482
10483 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10484
3e73aa7c
JH		 10485 if (!use_rela_relocations)
10486 {
10487 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10488 vtable entry to be used in the relocation's section offset. */
10489 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10490 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10491#if defined (OBJ_COFF) && defined (TE_PE)
10492 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10493 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10494 else
10495#endif
c6682705 10496 rel->addend = 0;
3e73aa7c
JH		 10497 }
10498 /* Use the rela in 64bit mode. */
252b5132 10499 else
3e73aa7c 10500 {
862be3fb
L		 10501 if (disallow_64bit_reloc)
10502 switch (code)
10503 {
862be3fb
L		 10504 case BFD_RELOC_X86_64_DTPOFF64:
10505 case BFD_RELOC_X86_64_TPOFF64:
10506 case BFD_RELOC_64_PCREL:
10507 case BFD_RELOC_X86_64_GOTOFF64:
10508 case BFD_RELOC_X86_64_GOT64:
10509 case BFD_RELOC_X86_64_GOTPCREL64:
10510 case BFD_RELOC_X86_64_GOTPC64:
10511 case BFD_RELOC_X86_64_GOTPLT64:
10512 case BFD_RELOC_X86_64_PLTOFF64:
10513 as_bad_where (fixp->fx_file, fixp->fx_line,
10514 _("cannot represent relocation type %s in x32 mode"),
10515 bfd_get_reloc_code_name (code));
10516 break;
10517 default:
10518 break;
10519 }
10520
062cd5e7
AS		 10521 if (!fixp->fx_pcrel)
10522 rel->addend = fixp->fx_offset;
10523 else
10524 switch (code)
10525 {
10526 case BFD_RELOC_X86_64_PLT32:
10527 case BFD_RELOC_X86_64_GOT32:
10528 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 10529 case BFD_RELOC_X86_64_TLSGD:
10530 case BFD_RELOC_X86_64_TLSLD:
10531 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 10532 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10533 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 10534 rel->addend = fixp->fx_offset - fixp->fx_size;
10535 break;
10536 default:
10537 rel->addend = (section->vma
10538 - fixp->fx_size
10539 + fixp->fx_addnumber
10540 + md_pcrel_from (fixp));
10541 break;
10542 }
3e73aa7c
JH		 10543 }
10544
252b5132
RH		 10545 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
10546 if (rel->howto == NULL)
10547 {
10548 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 10549 _("cannot represent relocation type %s"),
252b5132
RH		 10550 bfd_get_reloc_code_name (code));
10551 /* Set howto to a garbage value so that we can keep going. */
10552 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 10553 gas_assert (rel->howto != NULL);
252b5132
RH		 10554 }
10555
10556 return rel;
10557}
10558
ee86248c 10559#include "tc-i386-intel.c"
54cfded0 10560
a60de03c
JB		 10561void
10562tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 10563{
a60de03c
JB		 10564 int saved_naked_reg;
10565 char saved_register_dot;
54cfded0 10566
a60de03c
JB		 10567 saved_naked_reg = allow_naked_reg;
10568 allow_naked_reg = 1;
10569 saved_register_dot = register_chars['.'];
10570 register_chars['.'] = '.';
10571 allow_pseudo_reg = 1;
10572 expression_and_evaluate (exp);
10573 allow_pseudo_reg = 0;
10574 register_chars['.'] = saved_register_dot;
10575 allow_naked_reg = saved_naked_reg;
10576
e96d56a1 10577 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 10578 {
a60de03c
JB		 10579 if ((addressT) exp->X_add_number < i386_regtab_size)
10580 {
10581 exp->X_op = O_constant;
10582 exp->X_add_number = i386_regtab[exp->X_add_number]
10583 .dw2_regnum[flag_code >> 1];
10584 }
10585 else
10586 exp->X_op = O_illegal;
54cfded0 10587 }
54cfded0
AM		 10588}
10589
10590void
10591tc_x86_frame_initial_instructions (void)
10592{
a60de03c
JB		 10593 static unsigned int sp_regno[2];
10594
10595 if (!sp_regno[flag_code >> 1])
10596 {
10597 char *saved_input = input_line_pointer;
10598 char sp[][4] = {"esp", "rsp"};
10599 expressionS exp;
a4447b93 10600
a60de03c
JB		 10601 input_line_pointer = sp[flag_code >> 1];
10602 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 10603 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 10604 sp_regno[flag_code >> 1] = exp.X_add_number;
10605 input_line_pointer = saved_input;
10606 }
a4447b93 10607
61ff971f
L		 10608 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
10609 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 10610}
d2b2c203 10611
d7921315
L		 10612int
10613x86_dwarf2_addr_size (void)
10614{
10615#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10616 if (x86_elf_abi == X86_64_X32_ABI)
10617 return 4;
10618#endif
10619 return bfd_arch_bits_per_address (stdoutput) / 8;
10620}
10621
d2b2c203
DJ		 10622int
10623i386_elf_section_type (const char *str, size_t len)
10624{
10625 if (flag_code == CODE_64BIT
10626 && len == sizeof ("unwind") - 1
10627 && strncmp (str, "unwind", 6) == 0)
10628 return SHT_X86_64_UNWIND;
10629
10630 return -1;
10631}
bb41ade5 10632
ad5fec3b
EB		 10633#ifdef TE_SOLARIS
10634void
10635i386_solaris_fix_up_eh_frame (segT sec)
10636{
10637 if (flag_code == CODE_64BIT)
10638 elf_section_type (sec) = SHT_X86_64_UNWIND;
10639}
10640#endif
10641
bb41ade5
AM		 10642#ifdef TE_PE
10643void
10644tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10645{
91d6fa6a 10646 expressionS exp;
bb41ade5 10647
91d6fa6a
NC		 10648 exp.X_op = O_secrel;
10649 exp.X_add_symbol = symbol;
10650 exp.X_add_number = 0;
10651 emit_expr (&exp, size);
bb41ade5
AM		 10652}
10653#endif
3b22753a
L		 10654
10655#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10656/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10657
01e1a5bc 10658bfd_vma
3b22753a
L		 10659x86_64_section_letter (int letter, char **ptr_msg)
10660{
10661 if (flag_code == CODE_64BIT)
10662 {
10663 if (letter == 'l')
10664 return SHF_X86_64_LARGE;
10665
8f3bae45 10666 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 10667 }
3b22753a 10668 else
8f3bae45 10669 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 10670 return -1;
10671}
10672
01e1a5bc 10673bfd_vma
3b22753a
L		 10674x86_64_section_word (char *str, size_t len)
10675{
8620418b 10676 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 10677 return SHF_X86_64_LARGE;
10678
10679 return -1;
10680}
10681
10682static void
10683handle_large_common (int small ATTRIBUTE_UNUSED)
10684{
10685 if (flag_code != CODE_64BIT)
10686 {
10687 s_comm_internal (0, elf_common_parse);
10688 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10689 }
10690 else
10691 {
10692 static segT lbss_section;
10693 asection *saved_com_section_ptr = elf_com_section_ptr;
10694 asection *saved_bss_section = bss_section;
10695
10696 if (lbss_section == NULL)
10697 {
10698 flagword applicable;
10699 segT seg = now_seg;
10700 subsegT subseg = now_subseg;
10701
10702 /* The .lbss section is for local .largecomm symbols. */
10703 lbss_section = subseg_new (".lbss", 0);
10704 applicable = bfd_applicable_section_flags (stdoutput);
10705 bfd_set_section_flags (stdoutput, lbss_section,
10706 applicable & SEC_ALLOC);
10707 seg_info (lbss_section)->bss = 1;
10708
10709 subseg_set (seg, subseg);
10710 }
10711
10712 elf_com_section_ptr = &_bfd_elf_large_com_section;
10713 bss_section = lbss_section;
10714
10715 s_comm_internal (0, elf_common_parse);
10716
10717 elf_com_section_ptr = saved_com_section_ptr;
10718 bss_section = saved_bss_section;
10719 }
10720}
10721#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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