Commit | Line | Data |
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fecd2382 | 1 | /* i386.c -- Assemble code for the Intel 80386 |
0b476c53 | 2 | Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 1997 Free Software Foundation. |
355afbcd | 3 | |
a39116f1 | 4 | This file is part of GAS, the GNU Assembler. |
355afbcd | 5 | |
a39116f1 RP |
6 | GAS is free software; you can redistribute it and/or modify |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
355afbcd | 10 | |
a39116f1 RP |
11 | GAS is distributed in the hope that it will be useful, |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
355afbcd | 15 | |
a39116f1 | 16 | You should have received a copy of the GNU General Public License |
e592f0e6 ILT |
17 | along with GAS; see the file COPYING. If not, write to the Free |
18 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
19 | 02111-1307, USA. */ | |
fecd2382 | 20 | |
fecd2382 RP |
21 | /* |
22 | Intel 80386 machine specific gas. | |
23 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
24 | Bugs & suggestions are completely welcome. This is free software. | |
25 | Please help us make it better. | |
a39116f1 | 26 | */ |
fecd2382 | 27 | |
4b77b129 ILT |
28 | #include <ctype.h> |
29 | ||
fecd2382 | 30 | #include "as.h" |
0877841d | 31 | #include "subsegs.h" |
fecd2382 RP |
32 | |
33 | #include "obstack.h" | |
a39116f1 | 34 | #include "opcode/i386.h" |
fecd2382 | 35 | |
f0b37b4a KR |
36 | #ifndef TC_RELOC |
37 | #define TC_RELOC(X,Y) (Y) | |
38 | #endif | |
39 | ||
f59fb6ca ILT |
40 | static unsigned long mode_from_disp_size PARAMS ((unsigned long)); |
41 | static int fits_in_signed_byte PARAMS ((long)); | |
42 | static int fits_in_unsigned_byte PARAMS ((long)); | |
43 | static int fits_in_unsigned_word PARAMS ((long)); | |
44 | static int fits_in_signed_word PARAMS ((long)); | |
45 | static int smallest_imm_type PARAMS ((long)); | |
46 | static void set_16bit_code_flag PARAMS ((int)); | |
47 | #ifdef BFD_ASSEMBLER | |
48 | static bfd_reloc_code_real_type reloc | |
49 | PARAMS ((int, int, bfd_reloc_code_real_type)); | |
50 | #endif | |
51 | ||
fecd2382 RP |
52 | /* 'md_assemble ()' gathers together information and puts it into a |
53 | i386_insn. */ | |
54 | ||
3c8df4ba | 55 | struct _i386_insn |
355afbcd KR |
56 | { |
57 | /* TM holds the template for the insn were currently assembling. */ | |
58 | template tm; | |
59 | /* SUFFIX holds the opcode suffix (e.g. 'l' for 'movl') if given. */ | |
60 | char suffix; | |
61 | /* Operands are coded with OPERANDS, TYPES, DISPS, IMMS, and REGS. */ | |
62 | ||
63 | /* OPERANDS gives the number of given operands. */ | |
64 | unsigned int operands; | |
65 | ||
49864cfa KR |
66 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number |
67 | of given register, displacement, memory operands and immediate | |
68 | operands. */ | |
355afbcd KR |
69 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
70 | ||
71 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
49864cfa KR |
72 | search through DISPS [i] & IMMS [i] & REGS [i] for the required |
73 | operand. */ | |
355afbcd KR |
74 | unsigned int types[MAX_OPERANDS]; |
75 | ||
76 | /* Displacements (if given) for each operand. */ | |
77 | expressionS *disps[MAX_OPERANDS]; | |
78 | ||
f0b37b4a KR |
79 | /* Relocation type for operand */ |
80 | #ifdef BFD_ASSEMBLER | |
81 | enum bfd_reloc_code_real disp_reloc[MAX_OPERANDS]; | |
82 | #else | |
83 | int disp_reloc[MAX_OPERANDS]; | |
84 | #endif | |
85 | ||
355afbcd KR |
86 | /* Immediate operands (if given) for each operand. */ |
87 | expressionS *imms[MAX_OPERANDS]; | |
88 | ||
89 | /* Register operands (if given) for each operand. */ | |
90 | reg_entry *regs[MAX_OPERANDS]; | |
91 | ||
92 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode | |
49864cfa | 93 | the base index byte below. */ |
355afbcd KR |
94 | reg_entry *base_reg; |
95 | reg_entry *index_reg; | |
96 | unsigned int log2_scale_factor; | |
97 | ||
98 | /* SEG gives the seg_entry of this insn. It is equal to zero unless | |
49864cfa | 99 | an explicit segment override is given. */ |
355afbcd KR |
100 | const seg_entry *seg; /* segment for memory operands (if given) */ |
101 | ||
102 | /* PREFIX holds all the given prefix opcodes (usually null). | |
49864cfa | 103 | PREFIXES is the size of PREFIX. */ |
355afbcd KR |
104 | /* richfix: really unsigned? */ |
105 | unsigned char prefix[MAX_PREFIXES]; | |
106 | unsigned int prefixes; | |
107 | ||
49864cfa KR |
108 | /* RM and IB are the modrm byte and the base index byte where the |
109 | addressing modes of this insn are encoded. */ | |
355afbcd KR |
110 | |
111 | modrm_byte rm; | |
112 | base_index_byte bi; | |
3c8df4ba | 113 | }; |
355afbcd | 114 | |
3c8df4ba | 115 | typedef struct _i386_insn i386_insn; |
fecd2382 | 116 | |
a39116f1 RP |
117 | /* This array holds the chars that always start a comment. If the |
118 | pre-processor is disabled, these aren't very useful */ | |
590c50d8 | 119 | #if defined (TE_I386AIX) || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
49864cfa KR |
120 | const char comment_chars[] = "#/"; |
121 | #else | |
a39116f1 | 122 | const char comment_chars[] = "#"; |
49864cfa | 123 | #endif |
fecd2382 | 124 | |
a39116f1 RP |
125 | /* This array holds the chars that only start a comment at the beginning of |
126 | a line. If the line seems to have the form '# 123 filename' | |
127 | .line and .file directives will appear in the pre-processed output */ | |
128 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
129 | first line of the input file. This is because the compiler outputs | |
130 | #NO_APP at the beginning of its output. */ | |
131 | /* Also note that comments started like this one will always work if | |
f3d817d8 | 132 | '/' isn't otherwise defined. */ |
590c50d8 | 133 | #if defined (TE_I386AIX) || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
ad660eb1 | 134 | const char line_comment_chars[] = ""; |
7b23213f KR |
135 | #else |
136 | const char line_comment_chars[] = "/"; | |
137 | #endif | |
355afbcd | 138 | const char line_separator_chars[] = ""; |
fecd2382 | 139 | |
a39116f1 RP |
140 | /* Chars that can be used to separate mant from exp in floating point nums */ |
141 | const char EXP_CHARS[] = "eE"; | |
fecd2382 | 142 | |
a39116f1 RP |
143 | /* Chars that mean this number is a floating point constant */ |
144 | /* As in 0f12.456 */ | |
145 | /* or 0d1.2345e12 */ | |
146 | const char FLT_CHARS[] = "fFdDxX"; | |
fecd2382 RP |
147 | |
148 | /* tables for lexical analysis */ | |
149 | static char opcode_chars[256]; | |
150 | static char register_chars[256]; | |
151 | static char operand_chars[256]; | |
152 | static char space_chars[256]; | |
153 | static char identifier_chars[256]; | |
154 | static char digit_chars[256]; | |
155 | ||
156 | /* lexical macros */ | |
157 | #define is_opcode_char(x) (opcode_chars[(unsigned char) x]) | |
158 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
159 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
160 | #define is_space_char(x) (space_chars[(unsigned char) x]) | |
161 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
162 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
163 | ||
164 | /* put here all non-digit non-letter charcters that may occur in an operand */ | |
f0b37b4a | 165 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
fecd2382 | 166 | |
3c8df4ba | 167 | static char *ordinal_names[] = {"first", "second", "third"}; /* for printfs */ |
fecd2382 RP |
168 | |
169 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
170 | effect this we maintain a stack of saved characters that we've smashed | |
171 | with '\0's (indicating end of strings for various sub-fields of the | |
172 | assembler instruction). */ | |
173 | static char save_stack[32]; | |
174 | static char *save_stack_p; /* stack pointer */ | |
175 | #define END_STRING_AND_SAVE(s) *save_stack_p++ = *s; *s = '\0' | |
176 | #define RESTORE_END_STRING(s) *s = *--save_stack_p | |
355afbcd KR |
177 | |
178 | /* The instruction we're assembling. */ | |
179 | static i386_insn i; | |
fecd2382 RP |
180 | |
181 | /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */ | |
182 | static expressionS disp_expressions[2], im_expressions[2]; | |
183 | ||
184 | /* pointers to ebp & esp entries in reg_hash hash table */ | |
185 | static reg_entry *ebp, *esp; | |
186 | ||
187 | static int this_operand; /* current operand we are working on */ | |
188 | ||
ade614d5 KR |
189 | static int flag_do_long_jump; /* FIXME what does this do? */ |
190 | ||
c54c7aac KR |
191 | static int flag_16bit_code; /* 1 if we're writing 16-bit code, 0 if 32-bit */ |
192 | ||
3c8df4ba KR |
193 | /* Interface to relax_segment. |
194 | There are 2 relax states for 386 jump insns: one for conditional & | |
195 | one for unconditional jumps. This is because the these two types | |
196 | of jumps add different sizes to frags when we're figuring out what | |
197 | sort of jump to choose to reach a given label. */ | |
fecd2382 RP |
198 | |
199 | /* types */ | |
200 | #define COND_JUMP 1 /* conditional jump */ | |
201 | #define UNCOND_JUMP 2 /* unconditional jump */ | |
202 | /* sizes */ | |
203 | #define BYTE 0 | |
204 | #define WORD 1 | |
205 | #define DWORD 2 | |
206 | #define UNKNOWN_SIZE 3 | |
207 | ||
3c8df4ba KR |
208 | #ifndef INLINE |
209 | #ifdef __GNUC__ | |
210 | #define INLINE __inline__ | |
211 | #else | |
212 | #define INLINE | |
213 | #endif | |
214 | #endif | |
215 | ||
ad660eb1 ILT |
216 | #define ENCODE_RELAX_STATE(type,size) \ |
217 | ((relax_substateT)((type<<2) | (size))) | |
fecd2382 | 218 | #define SIZE_FROM_RELAX_STATE(s) \ |
a39116f1 | 219 | ( (((s) & 0x3) == BYTE ? 1 : (((s) & 0x3) == WORD ? 2 : 4)) ) |
fecd2382 | 220 | |
355afbcd KR |
221 | const relax_typeS md_relax_table[] = |
222 | { | |
49864cfa KR |
223 | /* The fields are: |
224 | 1) most positive reach of this state, | |
225 | 2) most negative reach of this state, | |
226 | 3) how many bytes this mode will add to the size of the current frag | |
227 | 4) which index into the table to try if we can't fit into this one. | |
228 | */ | |
355afbcd KR |
229 | {1, 1, 0, 0}, |
230 | {1, 1, 0, 0}, | |
231 | {1, 1, 0, 0}, | |
232 | {1, 1, 0, 0}, | |
233 | ||
3c8df4ba KR |
234 | /* For now we don't use word displacement jumps; they may be |
235 | untrustworthy. */ | |
355afbcd | 236 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, DWORD)}, |
3c8df4ba KR |
237 | /* word conditionals add 3 bytes to frag: |
238 | 2 opcode prefix; 1 displacement bytes */ | |
355afbcd | 239 | {32767 + 2, -32768 + 2, 3, ENCODE_RELAX_STATE (COND_JUMP, DWORD)}, |
3c8df4ba KR |
240 | /* dword conditionals adds 4 bytes to frag: |
241 | 1 opcode prefix; 3 displacement bytes */ | |
355afbcd KR |
242 | {0, 0, 4, 0}, |
243 | {1, 1, 0, 0}, | |
244 | ||
245 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, DWORD)}, | |
3c8df4ba KR |
246 | /* word jmp adds 2 bytes to frag: |
247 | 1 opcode prefix; 1 displacement bytes */ | |
355afbcd | 248 | {32767 + 2, -32768 + 2, 2, ENCODE_RELAX_STATE (UNCOND_JUMP, DWORD)}, |
3c8df4ba KR |
249 | /* dword jmp adds 3 bytes to frag: |
250 | 0 opcode prefix; 3 displacement bytes */ | |
355afbcd KR |
251 | {0, 0, 3, 0}, |
252 | {1, 1, 0, 0}, | |
253 | ||
fecd2382 RP |
254 | }; |
255 | ||
3ea36b53 ILT |
256 | |
257 | void | |
258 | i386_align_code (fragP, count) | |
259 | fragS *fragP; | |
260 | int count; | |
261 | { | |
262 | /* Various efficient no-op patterns for aligning code labels. */ | |
fb50cd4e ILT |
263 | /* Note: Don't try to assemble the instructions in the comments. */ |
264 | /* 0L and 0w are not legal */ | |
265 | static const char f32_1[] = | |
266 | {0x90}; /* nop */ | |
267 | static const char f32_2[] = | |
268 | {0x89,0xf6}; /* movl %esi,%esi */ | |
269 | static const char f32_3[] = | |
270 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
271 | static const char f32_4[] = | |
272 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
273 | static const char f32_5[] = | |
274 | {0x90, /* nop */ | |
275 | 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
276 | static const char f32_6[] = | |
277 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
278 | static const char f32_7[] = | |
279 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
280 | static const char f32_8[] = | |
281 | {0x90, /* nop */ | |
282 | 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
283 | static const char f32_9[] = | |
284 | {0x89,0xf6, /* movl %esi,%esi */ | |
285 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
286 | static const char f32_10[] = | |
287 | {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ | |
288 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
289 | static const char f32_11[] = | |
290 | {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ | |
291 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
292 | static const char f32_12[] = | |
293 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
294 | 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ | |
295 | static const char f32_13[] = | |
296 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
297 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
298 | static const char f32_14[] = | |
299 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ | |
300 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
301 | static const char f32_15[] = | |
302 | {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */ | |
303 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; | |
304 | static const char f16_4[] = | |
305 | {0x8d,0xb6,0x00,0x00}; /* lea 0w(%si),%si */ | |
306 | static const char f16_5[] = | |
307 | {0x90, /* nop */ | |
308 | 0x8d,0xb6,0x00,0x00}; /* lea 0w(%si),%si */ | |
309 | static const char f16_6[] = | |
310 | {0x89,0xf6, /* mov %si,%si */ | |
311 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
312 | static const char f16_7[] = | |
313 | {0x8d,0x76,0x00, /* lea 0(%si),%si */ | |
314 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
315 | static const char f16_8[] = | |
316 | {0x8d,0xb6,0x00,0x00, /* lea 0w(%si),%si */ | |
317 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
3ea36b53 ILT |
318 | static const char *const f32_patt[] = { |
319 | f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, | |
320 | f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15 | |
321 | }; | |
322 | static const char *const f16_patt[] = { | |
323 | f32_1, f32_2, f32_3, f16_4, f16_5, f16_6, f16_7, f16_8, | |
324 | f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15 | |
325 | }; | |
326 | ||
327 | if (count > 0 && count <= 15) | |
328 | { | |
329 | if (flag_16bit_code) | |
330 | { | |
331 | memcpy(fragP->fr_literal + fragP->fr_fix, | |
332 | f16_patt[count - 1], count); | |
333 | if (count > 8) /* adjust jump offset */ | |
334 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; | |
335 | } | |
336 | else | |
337 | memcpy(fragP->fr_literal + fragP->fr_fix, | |
338 | f32_patt[count - 1], count); | |
339 | fragP->fr_var = count; | |
340 | } | |
341 | } | |
342 | ||
49864cfa KR |
343 | static char *output_invalid PARAMS ((int c)); |
344 | static int i386_operand PARAMS ((char *operand_string)); | |
345 | static reg_entry *parse_register PARAMS ((char *reg_string)); | |
346 | #ifndef I386COFF | |
ad660eb1 | 347 | static void s_bss PARAMS ((int)); |
49864cfa | 348 | #endif |
fecd2382 | 349 | |
f0b37b4a KR |
350 | symbolS *GOT_symbol; /* Pre-defined "__GLOBAL_OFFSET_TABLE" */ |
351 | ||
3c8df4ba | 352 | static INLINE unsigned long |
49864cfa KR |
353 | mode_from_disp_size (t) |
354 | unsigned long t; | |
355 | { | |
3c8df4ba KR |
356 | return (t & Disp8) ? 1 : (t & Disp32) ? 2 : 0; |
357 | } | |
49864cfa | 358 | |
ad660eb1 ILT |
359 | #if 0 |
360 | /* Not used. */ | |
3c8df4ba | 361 | /* convert opcode suffix ('b' 'w' 'l' typically) into type specifier */ |
49864cfa | 362 | |
3c8df4ba | 363 | static INLINE unsigned long |
49864cfa KR |
364 | opcode_suffix_to_type (s) |
365 | unsigned long s; | |
366 | { | |
367 | return (s == BYTE_OPCODE_SUFFIX | |
368 | ? Byte : (s == WORD_OPCODE_SUFFIX | |
369 | ? Word : DWord)); | |
370 | } /* opcode_suffix_to_type() */ | |
ad660eb1 | 371 | #endif |
49864cfa | 372 | |
3c8df4ba | 373 | static INLINE int |
49864cfa KR |
374 | fits_in_signed_byte (num) |
375 | long num; | |
376 | { | |
3c8df4ba | 377 | return (num >= -128) && (num <= 127); |
49864cfa KR |
378 | } /* fits_in_signed_byte() */ |
379 | ||
3c8df4ba | 380 | static INLINE int |
49864cfa KR |
381 | fits_in_unsigned_byte (num) |
382 | long num; | |
383 | { | |
3c8df4ba | 384 | return (num & 0xff) == num; |
49864cfa KR |
385 | } /* fits_in_unsigned_byte() */ |
386 | ||
3c8df4ba | 387 | static INLINE int |
49864cfa KR |
388 | fits_in_unsigned_word (num) |
389 | long num; | |
390 | { | |
3c8df4ba | 391 | return (num & 0xffff) == num; |
49864cfa KR |
392 | } /* fits_in_unsigned_word() */ |
393 | ||
3c8df4ba | 394 | static INLINE int |
49864cfa KR |
395 | fits_in_signed_word (num) |
396 | long num; | |
397 | { | |
3c8df4ba | 398 | return (-32768 <= num) && (num <= 32767); |
49864cfa KR |
399 | } /* fits_in_signed_word() */ |
400 | ||
401 | static int | |
402 | smallest_imm_type (num) | |
403 | long num; | |
404 | { | |
f3d817d8 DM |
405 | #if 0 |
406 | /* This code is disabled because all the Imm1 forms in the opcode table | |
407 | are slower on the i486, and they're the versions with the implicitly | |
408 | specified single-position displacement, which has another syntax if | |
409 | you really want to use that form. If you really prefer to have the | |
410 | one-byte-shorter Imm1 form despite these problems, re-enable this | |
411 | code. */ | |
412 | if (num == 1) | |
413 | return Imm1 | Imm8 | Imm8S | Imm16 | Imm32; | |
414 | #endif | |
415 | return (fits_in_signed_byte (num) | |
3c8df4ba KR |
416 | ? (Imm8S | Imm8 | Imm16 | Imm32) |
417 | : fits_in_unsigned_byte (num) | |
418 | ? (Imm8 | Imm16 | Imm32) | |
419 | : (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
420 | ? (Imm16 | Imm32) | |
421 | : (Imm32)); | |
49864cfa | 422 | } /* smallest_imm_type() */ |
fecd2382 | 423 | |
f59fb6ca ILT |
424 | static void |
425 | set_16bit_code_flag (new_16bit_code_flag) | |
c54c7aac KR |
426 | int new_16bit_code_flag; |
427 | { | |
428 | flag_16bit_code = new_16bit_code_flag; | |
429 | } | |
430 | ||
355afbcd KR |
431 | const pseudo_typeS md_pseudo_table[] = |
432 | { | |
49864cfa | 433 | #ifndef I386COFF |
355afbcd | 434 | {"bss", s_bss, 0}, |
49864cfa | 435 | #endif |
3c8df4ba | 436 | #ifndef OBJ_AOUT |
355afbcd | 437 | {"align", s_align_bytes, 0}, |
49864cfa KR |
438 | #else |
439 | {"align", s_align_ptwo, 0}, | |
440 | #endif | |
355afbcd KR |
441 | {"ffloat", float_cons, 'f'}, |
442 | {"dfloat", float_cons, 'd'}, | |
443 | {"tfloat", float_cons, 'x'}, | |
444 | {"value", cons, 2}, | |
49864cfa KR |
445 | {"noopt", s_ignore, 0}, |
446 | {"optim", s_ignore, 0}, | |
c54c7aac KR |
447 | {"code16", set_16bit_code_flag, 1}, |
448 | {"code32", set_16bit_code_flag, 0}, | |
355afbcd | 449 | {0, 0, 0} |
fecd2382 RP |
450 | }; |
451 | ||
452 | /* for interface with expression () */ | |
355afbcd | 453 | extern char *input_line_pointer; |
fecd2382 RP |
454 | |
455 | /* obstack for constructing various things in md_begin */ | |
456 | struct obstack o; | |
457 | ||
458 | /* hash table for opcode lookup */ | |
f3d817d8 | 459 | static struct hash_control *op_hash; |
fecd2382 | 460 | /* hash table for register lookup */ |
f3d817d8 | 461 | static struct hash_control *reg_hash; |
fecd2382 | 462 | /* hash table for prefix lookup */ |
f3d817d8 | 463 | static struct hash_control *prefix_hash; |
fecd2382 | 464 | \f |
355afbcd KR |
465 | |
466 | void | |
467 | md_begin () | |
fecd2382 | 468 | { |
ad660eb1 | 469 | const char *hash_err; |
355afbcd KR |
470 | |
471 | obstack_begin (&o, 4096); | |
472 | ||
473 | /* initialize op_hash hash table */ | |
f3d817d8 | 474 | op_hash = hash_new (); |
355afbcd KR |
475 | |
476 | { | |
477 | register const template *optab; | |
478 | register templates *core_optab; | |
479 | char *prev_name; | |
480 | ||
481 | optab = i386_optab; /* setup for loop */ | |
482 | prev_name = optab->name; | |
483 | obstack_grow (&o, optab, sizeof (template)); | |
484 | core_optab = (templates *) xmalloc (sizeof (templates)); | |
485 | ||
486 | for (optab++; optab < i386_optab_end; optab++) | |
487 | { | |
488 | if (!strcmp (optab->name, prev_name)) | |
489 | { | |
490 | /* same name as before --> append to current template list */ | |
491 | obstack_grow (&o, optab, sizeof (template)); | |
492 | } | |
493 | else | |
494 | { | |
495 | /* different name --> ship out current template list; | |
49864cfa KR |
496 | add to hash table; & begin anew */ |
497 | /* Note: end must be set before start! since obstack_next_free | |
498 | changes upon opstack_finish */ | |
355afbcd KR |
499 | core_optab->end = (template *) obstack_next_free (&o); |
500 | core_optab->start = (template *) obstack_finish (&o); | |
501 | hash_err = hash_insert (op_hash, prev_name, (char *) core_optab); | |
ad660eb1 | 502 | if (hash_err) |
355afbcd KR |
503 | { |
504 | hash_error: | |
3c8df4ba KR |
505 | as_fatal ("Internal Error: Can't hash %s: %s", prev_name, |
506 | hash_err); | |
355afbcd KR |
507 | } |
508 | prev_name = optab->name; | |
509 | core_optab = (templates *) xmalloc (sizeof (templates)); | |
510 | obstack_grow (&o, optab, sizeof (template)); | |
511 | } | |
512 | } | |
513 | } | |
514 | ||
515 | /* initialize reg_hash hash table */ | |
516 | reg_hash = hash_new (); | |
517 | { | |
518 | register const reg_entry *regtab; | |
519 | ||
520 | for (regtab = i386_regtab; regtab < i386_regtab_end; regtab++) | |
521 | { | |
ad660eb1 ILT |
522 | hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab); |
523 | if (hash_err) | |
355afbcd KR |
524 | goto hash_error; |
525 | } | |
526 | } | |
527 | ||
528 | esp = (reg_entry *) hash_find (reg_hash, "esp"); | |
529 | ebp = (reg_entry *) hash_find (reg_hash, "ebp"); | |
530 | ||
531 | /* initialize reg_hash hash table */ | |
532 | prefix_hash = hash_new (); | |
533 | { | |
534 | register const prefix_entry *prefixtab; | |
535 | ||
536 | for (prefixtab = i386_prefixtab; | |
537 | prefixtab < i386_prefixtab_end; prefixtab++) | |
538 | { | |
ad660eb1 ILT |
539 | hash_err = hash_insert (prefix_hash, prefixtab->prefix_name, |
540 | (PTR) prefixtab); | |
541 | if (hash_err) | |
355afbcd KR |
542 | goto hash_error; |
543 | } | |
544 | } | |
545 | ||
546 | /* fill in lexical tables: opcode_chars, operand_chars, space_chars */ | |
547 | { | |
ad660eb1 ILT |
548 | register int c; |
549 | register char *p; | |
355afbcd KR |
550 | |
551 | for (c = 0; c < 256; c++) | |
552 | { | |
553 | if (islower (c) || isdigit (c)) | |
554 | { | |
555 | opcode_chars[c] = c; | |
556 | register_chars[c] = c; | |
557 | } | |
558 | else if (isupper (c)) | |
559 | { | |
560 | opcode_chars[c] = tolower (c); | |
561 | register_chars[c] = opcode_chars[c]; | |
562 | } | |
563 | else if (c == PREFIX_SEPERATOR) | |
564 | { | |
565 | opcode_chars[c] = c; | |
566 | } | |
567 | else if (c == ')' || c == '(') | |
568 | { | |
569 | register_chars[c] = c; | |
570 | } | |
571 | ||
572 | if (isupper (c) || islower (c) || isdigit (c)) | |
573 | operand_chars[c] = c; | |
355afbcd KR |
574 | |
575 | if (isdigit (c) || c == '-') | |
576 | digit_chars[c] = c; | |
577 | ||
578 | if (isalpha (c) || c == '_' || c == '.' || isdigit (c)) | |
579 | identifier_chars[c] = c; | |
580 | ||
30355216 SC |
581 | #ifdef LEX_AT |
582 | identifier_chars['@'] = '@'; | |
583 | #endif | |
584 | ||
355afbcd KR |
585 | if (c == ' ' || c == '\t') |
586 | space_chars[c] = c; | |
587 | } | |
ad660eb1 ILT |
588 | |
589 | for (p = operand_special_chars; *p != '\0'; p++) | |
590 | operand_chars[(unsigned char) *p] = *p; | |
355afbcd | 591 | } |
ad660eb1 | 592 | |
590c50d8 ILT |
593 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
594 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
595 | { | |
596 | record_alignment (text_section, 2); | |
597 | record_alignment (data_section, 2); | |
598 | record_alignment (bss_section, 2); | |
599 | } | |
ad660eb1 | 600 | #endif |
fecd2382 | 601 | } |
3ea36b53 ILT |
602 | |
603 | void | |
604 | i386_print_statistics (file) | |
605 | FILE *file; | |
606 | { | |
607 | hash_print_statistics (file, "i386 opcode", op_hash); | |
608 | hash_print_statistics (file, "i386 register", reg_hash); | |
609 | hash_print_statistics (file, "i386 prefix", prefix_hash); | |
610 | } | |
fecd2382 | 611 | \f |
355afbcd | 612 | |
fecd2382 RP |
613 | #ifdef DEBUG386 |
614 | ||
615 | /* debugging routines for md_assemble */ | |
ad660eb1 ILT |
616 | static void pi PARAMS ((char *, i386_insn *)); |
617 | static void pte PARAMS ((template *)); | |
618 | static void pt PARAMS ((unsigned int)); | |
619 | static void pe PARAMS ((expressionS *)); | |
620 | static void ps PARAMS ((symbolS *)); | |
fecd2382 | 621 | |
355afbcd KR |
622 | static void |
623 | pi (line, x) | |
624 | char *line; | |
625 | i386_insn *x; | |
fecd2382 | 626 | { |
355afbcd KR |
627 | register template *p; |
628 | int i; | |
629 | ||
630 | fprintf (stdout, "%s: template ", line); | |
631 | pte (&x->tm); | |
632 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x", | |
633 | x->rm.mode, x->rm.reg, x->rm.regmem); | |
634 | fprintf (stdout, " base %x index %x scale %x\n", | |
635 | x->bi.base, x->bi.index, x->bi.scale); | |
636 | for (i = 0; i < x->operands; i++) | |
637 | { | |
638 | fprintf (stdout, " #%d: ", i + 1); | |
639 | pt (x->types[i]); | |
640 | fprintf (stdout, "\n"); | |
454b0ccd | 641 | if (x->types[i] & (Reg | SReg2 | SReg3 | Control | Debug | Test)) |
355afbcd KR |
642 | fprintf (stdout, "%s\n", x->regs[i]->reg_name); |
643 | if (x->types[i] & Imm) | |
644 | pe (x->imms[i]); | |
645 | if (x->types[i] & (Disp | Abs)) | |
646 | pe (x->disps[i]); | |
647 | } | |
fecd2382 RP |
648 | } |
649 | ||
355afbcd KR |
650 | static void |
651 | pte (t) | |
652 | template *t; | |
fecd2382 | 653 | { |
355afbcd KR |
654 | int i; |
655 | fprintf (stdout, " %d operands ", t->operands); | |
656 | fprintf (stdout, "opcode %x ", | |
657 | t->base_opcode); | |
658 | if (t->extension_opcode != None) | |
659 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
660 | if (t->opcode_modifier & D) | |
661 | fprintf (stdout, "D"); | |
662 | if (t->opcode_modifier & W) | |
663 | fprintf (stdout, "W"); | |
664 | fprintf (stdout, "\n"); | |
665 | for (i = 0; i < t->operands; i++) | |
666 | { | |
667 | fprintf (stdout, " #%d type ", i + 1); | |
668 | pt (t->operand_types[i]); | |
669 | fprintf (stdout, "\n"); | |
670 | } | |
fecd2382 RP |
671 | } |
672 | ||
355afbcd KR |
673 | static void |
674 | pe (e) | |
675 | expressionS *e; | |
fecd2382 | 676 | { |
5ac34ac3 | 677 | fprintf (stdout, " operation %d\n", e->X_op); |
355afbcd KR |
678 | fprintf (stdout, " add_number %d (%x)\n", |
679 | e->X_add_number, e->X_add_number); | |
680 | if (e->X_add_symbol) | |
681 | { | |
682 | fprintf (stdout, " add_symbol "); | |
683 | ps (e->X_add_symbol); | |
684 | fprintf (stdout, "\n"); | |
685 | } | |
5ac34ac3 | 686 | if (e->X_op_symbol) |
355afbcd | 687 | { |
5ac34ac3 ILT |
688 | fprintf (stdout, " op_symbol "); |
689 | ps (e->X_op_symbol); | |
355afbcd KR |
690 | fprintf (stdout, "\n"); |
691 | } | |
fecd2382 RP |
692 | } |
693 | ||
355afbcd KR |
694 | static void |
695 | ps (s) | |
696 | symbolS *s; | |
fecd2382 | 697 | { |
355afbcd KR |
698 | fprintf (stdout, "%s type %s%s", |
699 | S_GET_NAME (s), | |
700 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
701 | segment_name (S_GET_SEGMENT (s))); | |
fecd2382 RP |
702 | } |
703 | ||
355afbcd KR |
704 | struct type_name |
705 | { | |
706 | unsigned int mask; | |
707 | char *tname; | |
708 | } | |
709 | ||
710 | type_names[] = | |
711 | { | |
712 | { Reg8, "r8" }, | |
713 | { Reg16, "r16" }, | |
714 | { Reg32, "r32" }, | |
715 | { Imm8, "i8" }, | |
716 | { Imm8S, "i8s" }, | |
717 | { Imm16, "i16" }, | |
718 | { Imm32, "i32" }, | |
719 | { Mem8, "Mem8" }, | |
720 | { Mem16, "Mem16" }, | |
721 | { Mem32, "Mem32" }, | |
722 | { BaseIndex, "BaseIndex" }, | |
723 | { Abs8, "Abs8" }, | |
724 | { Abs16, "Abs16" }, | |
725 | { Abs32, "Abs32" }, | |
726 | { Disp8, "d8" }, | |
727 | { Disp16, "d16" }, | |
728 | { Disp32, "d32" }, | |
729 | { SReg2, "SReg2" }, | |
730 | { SReg3, "SReg3" }, | |
731 | { Acc, "Acc" }, | |
732 | { InOutPortReg, "InOutPortReg" }, | |
733 | { ShiftCount, "ShiftCount" }, | |
734 | { Imm1, "i1" }, | |
735 | { Control, "control reg" }, | |
736 | { Test, "test reg" }, | |
737 | { FloatReg, "FReg" }, | |
738 | { FloatAcc, "FAcc" }, | |
739 | { JumpAbsolute, "Jump Absolute" }, | |
454b0ccd | 740 | { RegMMX, "rMMX" }, |
355afbcd | 741 | { 0, "" } |
fecd2382 RP |
742 | }; |
743 | ||
355afbcd KR |
744 | static void |
745 | pt (t) | |
746 | unsigned int t; | |
fecd2382 | 747 | { |
355afbcd KR |
748 | register struct type_name *ty; |
749 | ||
750 | if (t == Unknown) | |
751 | { | |
752 | fprintf (stdout, "Unknown"); | |
753 | } | |
754 | else | |
755 | { | |
756 | for (ty = type_names; ty->mask; ty++) | |
757 | if (t & ty->mask) | |
758 | fprintf (stdout, "%s, ", ty->tname); | |
759 | } | |
760 | fflush (stdout); | |
fecd2382 RP |
761 | } |
762 | ||
763 | #endif /* DEBUG386 */ | |
764 | \f | |
49864cfa KR |
765 | #ifdef BFD_ASSEMBLER |
766 | static bfd_reloc_code_real_type | |
f0b37b4a | 767 | reloc (size, pcrel, other) |
49864cfa KR |
768 | int size; |
769 | int pcrel; | |
f0b37b4a | 770 | bfd_reloc_code_real_type other; |
49864cfa | 771 | { |
f0b37b4a KR |
772 | if (other != NO_RELOC) return other; |
773 | ||
49864cfa KR |
774 | if (pcrel) |
775 | switch (size) | |
776 | { | |
777 | case 1: return BFD_RELOC_8_PCREL; | |
778 | case 2: return BFD_RELOC_16_PCREL; | |
779 | case 4: return BFD_RELOC_32_PCREL; | |
780 | } | |
781 | else | |
782 | switch (size) | |
783 | { | |
784 | case 1: return BFD_RELOC_8; | |
785 | case 2: return BFD_RELOC_16; | |
786 | case 4: return BFD_RELOC_32; | |
787 | } | |
ad660eb1 ILT |
788 | |
789 | as_bad ("Can not do %d byte %srelocation", size, | |
c54c7aac | 790 | pcrel ? "pc-relative " : ""); |
ad660eb1 | 791 | return BFD_RELOC_NONE; |
49864cfa | 792 | } |
49864cfa | 793 | |
f0b37b4a KR |
794 | /* |
795 | * Here we decide which fixups can be adjusted to make them relative to | |
796 | * the beginning of the section instead of the symbol. Basically we need | |
797 | * to make sure that the dynamic relocations are done correctly, so in | |
798 | * some cases we force the original symbol to be used. | |
799 | */ | |
0877841d | 800 | int |
f0b37b4a KR |
801 | tc_i386_fix_adjustable(fixP) |
802 | fixS * fixP; | |
803 | { | |
0877841d | 804 | #ifndef OBJ_AOUT |
c54c7aac | 805 | /* Prevent all adjustments to global symbols. */ |
0877841d | 806 | if (S_IS_EXTERN (fixP->fx_addsy)) |
c54c7aac | 807 | return 0; |
0b476c53 ILT |
808 | if (S_IS_WEAK (fixP->fx_addsy)) |
809 | return 0; | |
0b476c53 | 810 | #endif /* ! defined (OBJ_AOUT) */ |
c54c7aac | 811 | /* adjust_reloc_syms doesn't know about the GOT */ |
0877841d ILT |
812 | if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF |
813 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 | |
814 | || fixP->fx_r_type == BFD_RELOC_386_GOT32) | |
c54c7aac | 815 | return 0; |
c54c7aac | 816 | return 1; |
f0b37b4a | 817 | } |
454b0ccd ILT |
818 | #else |
819 | #define reloc(SIZE,PCREL,OTHER) 0 | |
820 | #define BFD_RELOC_32 0 | |
821 | #define BFD_RELOC_32_PCREL 0 | |
822 | #define BFD_RELOC_386_PLT32 0 | |
823 | #define BFD_RELOC_386_GOT32 0 | |
824 | #define BFD_RELOC_386_GOTOFF 0 | |
825 | #endif | |
f0b37b4a | 826 | |
49864cfa | 827 | /* This is the guts of the machine-dependent assembler. LINE points to a |
3c8df4ba | 828 | machine dependent instruction. This function is supposed to emit |
49864cfa | 829 | the frags/bytes it assembles to. */ |
f0b37b4a | 830 | |
355afbcd KR |
831 | void |
832 | md_assemble (line) | |
833 | char *line; | |
fecd2382 | 834 | { |
ad660eb1 | 835 | /* Holds template once we've found it. */ |
f0b37b4a | 836 | template *t; |
355afbcd | 837 | |
ad660eb1 ILT |
838 | /* Count the size of the instruction generated. */ |
839 | int insn_size = 0; | |
840 | ||
355afbcd KR |
841 | /* Possible templates for current insn */ |
842 | templates *current_templates = (templates *) 0; | |
843 | ||
f0b37b4a KR |
844 | int j; |
845 | ||
355afbcd KR |
846 | /* Initialize globals. */ |
847 | memset (&i, '\0', sizeof (i)); | |
f0b37b4a KR |
848 | for (j = 0; j < MAX_OPERANDS; j++) |
849 | i.disp_reloc[j] = NO_RELOC; | |
355afbcd KR |
850 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
851 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
852 | save_stack_p = save_stack; /* reset stack pointer */ | |
853 | ||
854 | /* Fist parse an opcode & call i386_operand for the operands. | |
49864cfa KR |
855 | We assume that the scrubber has arranged it so that line[0] is the valid |
856 | start of a (possibly prefixed) opcode. */ | |
355afbcd | 857 | { |
f3d817d8 | 858 | char *l = line; |
355afbcd KR |
859 | |
860 | /* 1 if operand is pending after ','. */ | |
861 | unsigned int expecting_operand = 0; | |
862 | /* 1 if we found a prefix only acceptable with string insns. */ | |
863 | unsigned int expecting_string_instruction = 0; | |
0b476c53 ILT |
864 | /* Non-zero if operand parens not balanced. */ |
865 | unsigned int paren_not_balanced; | |
355afbcd KR |
866 | char *token_start = l; |
867 | ||
868 | while (!is_space_char (*l) && *l != END_OF_INSN) | |
869 | { | |
870 | if (!is_opcode_char (*l)) | |
871 | { | |
872 | as_bad ("invalid character %s in opcode", output_invalid (*l)); | |
873 | return; | |
874 | } | |
875 | else if (*l != PREFIX_SEPERATOR) | |
876 | { | |
877 | *l = opcode_chars[(unsigned char) *l]; /* fold case of opcodes */ | |
878 | l++; | |
879 | } | |
880 | else | |
f3d817d8 DM |
881 | { |
882 | /* This opcode's got a prefix. */ | |
883 | unsigned int q; | |
884 | prefix_entry *prefix; | |
355afbcd KR |
885 | |
886 | if (l == token_start) | |
887 | { | |
888 | as_bad ("expecting prefix; got nothing"); | |
889 | return; | |
890 | } | |
891 | END_STRING_AND_SAVE (l); | |
892 | prefix = (prefix_entry *) hash_find (prefix_hash, token_start); | |
893 | if (!prefix) | |
894 | { | |
895 | as_bad ("no such opcode prefix ('%s')", token_start); | |
896 | return; | |
897 | } | |
898 | RESTORE_END_STRING (l); | |
899 | /* check for repeated prefix */ | |
900 | for (q = 0; q < i.prefixes; q++) | |
901 | if (i.prefix[q] == prefix->prefix_code) | |
902 | { | |
903 | as_bad ("same prefix used twice; you don't really want this!"); | |
904 | return; | |
a39116f1 | 905 | } |
355afbcd KR |
906 | if (i.prefixes == MAX_PREFIXES) |
907 | { | |
908 | as_bad ("too many opcode prefixes"); | |
909 | return; | |
910 | } | |
911 | i.prefix[i.prefixes++] = prefix->prefix_code; | |
912 | if (prefix->prefix_code == REPE || prefix->prefix_code == REPNE) | |
913 | expecting_string_instruction = 1; | |
914 | /* skip past PREFIX_SEPERATOR and reset token_start */ | |
915 | token_start = ++l; | |
916 | } | |
917 | } | |
918 | END_STRING_AND_SAVE (l); | |
919 | if (token_start == l) | |
920 | { | |
921 | as_bad ("expecting opcode; got nothing"); | |
922 | return; | |
923 | } | |
924 | ||
925 | /* Lookup insn in hash; try intel & att naming conventions if appropriate; | |
49864cfa | 926 | that is: we only use the opcode suffix 'b' 'w' or 'l' if we need to. */ |
355afbcd KR |
927 | current_templates = (templates *) hash_find (op_hash, token_start); |
928 | if (!current_templates) | |
929 | { | |
930 | int last_index = strlen (token_start) - 1; | |
931 | char last_char = token_start[last_index]; | |
932 | switch (last_char) | |
933 | { | |
934 | case DWORD_OPCODE_SUFFIX: | |
935 | case WORD_OPCODE_SUFFIX: | |
936 | case BYTE_OPCODE_SUFFIX: | |
937 | token_start[last_index] = '\0'; | |
938 | current_templates = (templates *) hash_find (op_hash, token_start); | |
939 | token_start[last_index] = last_char; | |
940 | i.suffix = last_char; | |
941 | } | |
942 | if (!current_templates) | |
943 | { | |
944 | as_bad ("no such 386 instruction: `%s'", token_start); | |
945 | return; | |
946 | } | |
947 | } | |
948 | RESTORE_END_STRING (l); | |
949 | ||
950 | /* check for rep/repne without a string instruction */ | |
951 | if (expecting_string_instruction && | |
952 | !IS_STRING_INSTRUCTION (current_templates-> | |
953 | start->base_opcode)) | |
954 | { | |
955 | as_bad ("expecting string instruction after rep/repne"); | |
956 | return; | |
957 | } | |
958 | ||
959 | /* There may be operands to parse. */ | |
960 | if (*l != END_OF_INSN && | |
c5dd66a1 KR |
961 | /* For string instructions, we ignore any operands if given. This |
962 | kludges, for example, 'rep/movsb %ds:(%esi), %es:(%edi)' where | |
963 | the operands are always going to be the same, and are not really | |
964 | encoded in machine code. */ | |
355afbcd KR |
965 | !IS_STRING_INSTRUCTION (current_templates-> |
966 | start->base_opcode)) | |
967 | { | |
968 | /* parse operands */ | |
969 | do | |
970 | { | |
971 | /* skip optional white space before operand */ | |
972 | while (!is_operand_char (*l) && *l != END_OF_INSN) | |
973 | { | |
974 | if (!is_space_char (*l)) | |
975 | { | |
976 | as_bad ("invalid character %s before %s operand", | |
977 | output_invalid (*l), | |
978 | ordinal_names[i.operands]); | |
979 | return; | |
980 | } | |
981 | l++; | |
982 | } | |
983 | token_start = l; /* after white space */ | |
0b476c53 ILT |
984 | paren_not_balanced = 0; |
985 | while (paren_not_balanced || *l != ',') | |
355afbcd KR |
986 | { |
987 | if (*l == END_OF_INSN) | |
988 | { | |
0b476c53 | 989 | if (paren_not_balanced) |
355afbcd | 990 | { |
0b476c53 | 991 | as_bad ("unbalanced parenthesis in %s operand.", |
355afbcd KR |
992 | ordinal_names[i.operands]); |
993 | return; | |
994 | } | |
995 | else | |
996 | break; /* we are done */ | |
997 | } | |
ad660eb1 | 998 | else if (!is_operand_char (*l) && !is_space_char (*l)) |
355afbcd KR |
999 | { |
1000 | as_bad ("invalid character %s in %s operand", | |
1001 | output_invalid (*l), | |
1002 | ordinal_names[i.operands]); | |
1003 | return; | |
1004 | } | |
1005 | if (*l == '(') | |
0b476c53 | 1006 | ++paren_not_balanced; |
355afbcd | 1007 | if (*l == ')') |
0b476c53 | 1008 | --paren_not_balanced; |
355afbcd KR |
1009 | l++; |
1010 | } | |
1011 | if (l != token_start) | |
1012 | { /* yes, we've read in another operand */ | |
1013 | unsigned int operand_ok; | |
1014 | this_operand = i.operands++; | |
1015 | if (i.operands > MAX_OPERANDS) | |
1016 | { | |
1017 | as_bad ("spurious operands; (%d operands/instruction max)", | |
1018 | MAX_OPERANDS); | |
1019 | return; | |
1020 | } | |
1021 | /* now parse operand adding info to 'i' as we go along */ | |
1022 | END_STRING_AND_SAVE (l); | |
1023 | operand_ok = i386_operand (token_start); | |
1024 | RESTORE_END_STRING (l); /* restore old contents */ | |
1025 | if (!operand_ok) | |
1026 | return; | |
1027 | } | |
1028 | else | |
1029 | { | |
1030 | if (expecting_operand) | |
1031 | { | |
1032 | expecting_operand_after_comma: | |
1033 | as_bad ("expecting operand after ','; got nothing"); | |
1034 | return; | |
1035 | } | |
1036 | if (*l == ',') | |
1037 | { | |
1038 | as_bad ("expecting operand before ','; got nothing"); | |
1039 | return; | |
1040 | } | |
1041 | } | |
1042 | ||
1043 | /* now *l must be either ',' or END_OF_INSN */ | |
1044 | if (*l == ',') | |
1045 | { | |
1046 | if (*++l == END_OF_INSN) | |
1047 | { /* just skip it, if it's \n complain */ | |
1048 | goto expecting_operand_after_comma; | |
1049 | } | |
1050 | expecting_operand = 1; | |
1051 | } | |
1052 | } | |
1053 | while (*l != END_OF_INSN); /* until we get end of insn */ | |
1054 | } | |
1055 | } | |
1056 | ||
1057 | /* Now we've parsed the opcode into a set of templates, and have the | |
c5dd66a1 KR |
1058 | operands at hand. |
1059 | ||
1060 | Next, we find a template that matches the given insn, | |
1061 | making sure the overlap of the given operands types is consistent | |
1062 | with the template operand types. */ | |
355afbcd | 1063 | |
fecd2382 | 1064 | #define MATCH(overlap,given_type) \ |
a39116f1 | 1065 | (overlap && \ |
49864cfa KR |
1066 | (((overlap & (JumpAbsolute|BaseIndex|Mem8)) \ |
1067 | == (given_type & (JumpAbsolute|BaseIndex|Mem8))) \ | |
1068 | || (overlap == InOutPortReg))) | |
1069 | ||
355afbcd KR |
1070 | |
1071 | /* If m0 and m1 are register matches they must be consistent | |
c5dd66a1 KR |
1072 | with the expected operand types t0 and t1. |
1073 | That is, if both m0 & m1 are register matches | |
1074 | i.e. ( ((m0 & (Reg)) && (m1 & (Reg)) ) ? | |
1075 | then, either 1. or 2. must be true: | |
1076 | 1. the expected operand type register overlap is null: | |
1077 | (t0 & t1 & Reg) == 0 | |
1078 | AND | |
1079 | the given register overlap is null: | |
1080 | (m0 & m1 & Reg) == 0 | |
1081 | 2. the expected operand type register overlap == the given | |
1082 | operand type overlap: (t0 & t1 & m0 & m1 & Reg). | |
1083 | */ | |
a39116f1 RP |
1084 | #define CONSISTENT_REGISTER_MATCH(m0, m1, t0, t1) \ |
1085 | ( ((m0 & (Reg)) && (m1 & (Reg))) ? \ | |
1086 | ( ((t0 & t1 & (Reg)) == 0 && (m0 & m1 & (Reg)) == 0) || \ | |
1087 | ((t0 & t1) & (m0 & m1) & (Reg)) \ | |
1088 | ) : 1) | |
355afbcd KR |
1089 | { |
1090 | register unsigned int overlap0, overlap1; | |
1091 | expressionS *exp; | |
1092 | unsigned int overlap2; | |
1093 | unsigned int found_reverse_match; | |
1094 | ||
1095 | overlap0 = overlap1 = overlap2 = found_reverse_match = 0; | |
1096 | for (t = current_templates->start; | |
1097 | t < current_templates->end; | |
1098 | t++) | |
1099 | { | |
355afbcd KR |
1100 | /* must have right number of operands */ |
1101 | if (i.operands != t->operands) | |
1102 | continue; | |
1103 | else if (!t->operands) | |
1104 | break; /* 0 operands always matches */ | |
1105 | ||
1106 | overlap0 = i.types[0] & t->operand_types[0]; | |
1107 | switch (t->operands) | |
1108 | { | |
1109 | case 1: | |
1110 | if (!MATCH (overlap0, i.types[0])) | |
1111 | continue; | |
1112 | break; | |
1113 | case 2: | |
1114 | case 3: | |
1115 | overlap1 = i.types[1] & t->operand_types[1]; | |
1116 | if (!MATCH (overlap0, i.types[0]) || | |
1117 | !MATCH (overlap1, i.types[1]) || | |
1118 | !CONSISTENT_REGISTER_MATCH (overlap0, overlap1, | |
1119 | t->operand_types[0], | |
1120 | t->operand_types[1])) | |
542e1629 | 1121 | { |
355afbcd KR |
1122 | |
1123 | /* check if other direction is valid ... */ | |
1124 | if (!(t->opcode_modifier & COMES_IN_BOTH_DIRECTIONS)) | |
1125 | continue; | |
1126 | ||
1127 | /* try reversing direction of operands */ | |
1128 | overlap0 = i.types[0] & t->operand_types[1]; | |
1129 | overlap1 = i.types[1] & t->operand_types[0]; | |
1130 | if (!MATCH (overlap0, i.types[0]) || | |
1131 | !MATCH (overlap1, i.types[1]) || | |
1132 | !CONSISTENT_REGISTER_MATCH (overlap0, overlap1, | |
1133 | t->operand_types[0], | |
1134 | t->operand_types[1])) | |
1135 | { | |
1136 | /* does not match either direction */ | |
1137 | continue; | |
1138 | } | |
1139 | /* found a reverse match here -- slip through */ | |
1140 | /* found_reverse_match holds which of D or FloatD we've found */ | |
1141 | found_reverse_match = t->opcode_modifier & COMES_IN_BOTH_DIRECTIONS; | |
1142 | } /* endif: not forward match */ | |
1143 | /* found either forward/reverse 2 operand match here */ | |
1144 | if (t->operands == 3) | |
1145 | { | |
1146 | overlap2 = i.types[2] & t->operand_types[2]; | |
1147 | if (!MATCH (overlap2, i.types[2]) || | |
1148 | !CONSISTENT_REGISTER_MATCH (overlap0, overlap2, | |
1149 | t->operand_types[0], | |
1150 | t->operand_types[2]) || | |
1151 | !CONSISTENT_REGISTER_MATCH (overlap1, overlap2, | |
1152 | t->operand_types[1], | |
1153 | t->operand_types[2])) | |
1154 | continue; | |
1155 | } | |
1156 | /* found either forward/reverse 2 or 3 operand match here: | |
c5dd66a1 | 1157 | slip through to break */ |
355afbcd KR |
1158 | } |
1159 | break; /* we've found a match; break out of loop */ | |
1160 | } /* for (t = ... */ | |
1161 | if (t == current_templates->end) | |
1162 | { /* we found no match */ | |
1163 | as_bad ("operands given don't match any known 386 instruction"); | |
1164 | return; | |
1165 | } | |
1166 | ||
1167 | /* Copy the template we found (we may change it!). */ | |
f3d817d8 | 1168 | i.tm = *t; |
355afbcd KR |
1169 | t = &i.tm; /* alter new copy of template */ |
1170 | ||
c54c7aac KR |
1171 | /* If the matched instruction specifies an explicit opcode suffix, |
1172 | use it - and make sure none has already been specified. */ | |
1173 | if (t->opcode_modifier & (Data16|Data32)) | |
1174 | { | |
1175 | if (i.suffix) | |
1176 | { | |
1177 | as_bad ("extraneous opcode suffix given"); | |
1178 | return; | |
1179 | } | |
1180 | if (t->opcode_modifier & Data16) | |
1181 | i.suffix = WORD_OPCODE_SUFFIX; | |
1182 | else | |
1183 | i.suffix = DWORD_OPCODE_SUFFIX; | |
1184 | } | |
1185 | ||
355afbcd | 1186 | /* If there's no opcode suffix we try to invent one based on register |
c5dd66a1 | 1187 | operands. */ |
355afbcd KR |
1188 | if (!i.suffix && i.reg_operands) |
1189 | { | |
1190 | /* We take i.suffix from the LAST register operand specified. This | |
c5dd66a1 KR |
1191 | assumes that the last register operands is the destination register |
1192 | operand. */ | |
ad660eb1 ILT |
1193 | int op; |
1194 | for (op = 0; op < MAX_OPERANDS; op++) | |
1195 | if (i.types[op] & Reg) | |
355afbcd | 1196 | { |
e592f0e6 ILT |
1197 | i.suffix = ((i.types[op] & Reg8) ? BYTE_OPCODE_SUFFIX : |
1198 | (i.types[op] & Reg16) ? WORD_OPCODE_SUFFIX : | |
ad660eb1 | 1199 | DWORD_OPCODE_SUFFIX); |
355afbcd KR |
1200 | } |
1201 | } | |
3ea36b53 ILT |
1202 | else if (i.suffix != 0 |
1203 | && i.reg_operands != 0 | |
1204 | && (i.types[i.operands - 1] & Reg) != 0) | |
1205 | { | |
e592f0e6 | 1206 | int bad; |
3ea36b53 ILT |
1207 | |
1208 | /* If the last operand is a register, make sure it is | |
1209 | compatible with the suffix. */ | |
1210 | ||
e592f0e6 | 1211 | bad = 0; |
3ea36b53 ILT |
1212 | switch (i.suffix) |
1213 | { | |
1214 | default: | |
1215 | abort (); | |
1216 | case BYTE_OPCODE_SUFFIX: | |
e592f0e6 ILT |
1217 | /* If this is an eight bit register, it's OK. If it's the |
1218 | 16 or 32 bit version of an eight bit register, we will | |
1219 | just use the low portion, and that's OK too. */ | |
1220 | if ((i.types[i.operands - 1] & Reg8) == 0 | |
1221 | && i.regs[i.operands - 1]->reg_num >= 4) | |
1222 | bad = 1; | |
3ea36b53 ILT |
1223 | break; |
1224 | case WORD_OPCODE_SUFFIX: | |
3ea36b53 | 1225 | case DWORD_OPCODE_SUFFIX: |
e592f0e6 ILT |
1226 | /* We don't insist on the presence or absence of the e |
1227 | prefix on the register, but we reject eight bit | |
1228 | registers. */ | |
1229 | if ((i.types[i.operands - 1] & Reg8) != 0) | |
1230 | bad = 1; | |
3ea36b53 | 1231 | } |
e592f0e6 | 1232 | if (bad) |
3ea36b53 ILT |
1233 | as_bad ("register does not match opcode suffix"); |
1234 | } | |
355afbcd KR |
1235 | |
1236 | /* Make still unresolved immediate matches conform to size of immediate | |
c5dd66a1 KR |
1237 | given in i.suffix. Note: overlap2 cannot be an immediate! |
1238 | We assume this. */ | |
355afbcd KR |
1239 | if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32)) |
1240 | && overlap0 != Imm8 && overlap0 != Imm8S | |
1241 | && overlap0 != Imm16 && overlap0 != Imm32) | |
1242 | { | |
1243 | if (!i.suffix) | |
1244 | { | |
1245 | as_bad ("no opcode suffix given; can't determine immediate size"); | |
1246 | return; | |
1247 | } | |
1248 | overlap0 &= (i.suffix == BYTE_OPCODE_SUFFIX ? (Imm8 | Imm8S) : | |
1249 | (i.suffix == WORD_OPCODE_SUFFIX ? Imm16 : Imm32)); | |
1250 | } | |
1251 | if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32)) | |
1252 | && overlap1 != Imm8 && overlap1 != Imm8S | |
1253 | && overlap1 != Imm16 && overlap1 != Imm32) | |
1254 | { | |
1255 | if (!i.suffix) | |
1256 | { | |
1257 | as_bad ("no opcode suffix given; can't determine immediate size"); | |
1258 | return; | |
1259 | } | |
1260 | overlap1 &= (i.suffix == BYTE_OPCODE_SUFFIX ? (Imm8 | Imm8S) : | |
1261 | (i.suffix == WORD_OPCODE_SUFFIX ? Imm16 : Imm32)); | |
1262 | } | |
1263 | ||
1264 | i.types[0] = overlap0; | |
1265 | i.types[1] = overlap1; | |
1266 | i.types[2] = overlap2; | |
1267 | ||
1268 | if (overlap0 & ImplicitRegister) | |
1269 | i.reg_operands--; | |
1270 | if (overlap1 & ImplicitRegister) | |
1271 | i.reg_operands--; | |
1272 | if (overlap2 & ImplicitRegister) | |
1273 | i.reg_operands--; | |
1274 | if (overlap0 & Imm1) | |
1275 | i.imm_operands = 0; /* kludge for shift insns */ | |
1276 | ||
1277 | if (found_reverse_match) | |
1278 | { | |
1279 | unsigned int save; | |
1280 | save = t->operand_types[0]; | |
1281 | t->operand_types[0] = t->operand_types[1]; | |
1282 | t->operand_types[1] = save; | |
1283 | } | |
1284 | ||
1285 | /* Finalize opcode. First, we change the opcode based on the operand | |
c5dd66a1 KR |
1286 | size given by i.suffix: we never have to change things for byte insns, |
1287 | or when no opcode suffix is need to size the operands. */ | |
355afbcd KR |
1288 | |
1289 | if (!i.suffix && (t->opcode_modifier & W)) | |
1290 | { | |
1291 | as_bad ("no opcode suffix given and no register operands; can't size instruction"); | |
1292 | return; | |
1293 | } | |
1294 | ||
1295 | if (i.suffix && i.suffix != BYTE_OPCODE_SUFFIX) | |
1296 | { | |
1297 | /* Select between byte and word/dword operations. */ | |
1298 | if (t->opcode_modifier & W) | |
1299 | t->base_opcode |= W; | |
1300 | /* Now select between word & dword operations via the | |
a39116f1 | 1301 | operand size prefix. */ |
c54c7aac | 1302 | if ((i.suffix == WORD_OPCODE_SUFFIX) ^ flag_16bit_code) |
355afbcd KR |
1303 | { |
1304 | if (i.prefixes == MAX_PREFIXES) | |
1305 | { | |
1306 | as_bad ("%d prefixes given and 'w' opcode suffix gives too many prefixes", | |
1307 | MAX_PREFIXES); | |
1308 | return; | |
1309 | } | |
1310 | i.prefix[i.prefixes++] = WORD_PREFIX_OPCODE; | |
1311 | } | |
1312 | } | |
1313 | ||
1314 | /* For insns with operands there are more diddles to do to the opcode. */ | |
1315 | if (i.operands) | |
1316 | { | |
c54c7aac KR |
1317 | /* Default segment register this instruction will use |
1318 | for memory accesses. 0 means unknown. | |
1319 | This is only for optimizing out unnecessary segment overrides. */ | |
1320 | const seg_entry *default_seg = 0; | |
1321 | ||
1322 | /* True if this instruction uses a memory addressing mode, | |
1323 | and therefore may need an address-size prefix. */ | |
1324 | int uses_mem_addrmode = 0; | |
1325 | ||
1326 | ||
355afbcd | 1327 | /* If we found a reverse match we must alter the opcode direction bit |
c5dd66a1 KR |
1328 | found_reverse_match holds bit to set (different for int & |
1329 | float insns). */ | |
355afbcd KR |
1330 | |
1331 | if (found_reverse_match) | |
1332 | { | |
1333 | t->base_opcode |= found_reverse_match; | |
1334 | } | |
1335 | ||
c5dd66a1 KR |
1336 | /* The imul $imm, %reg instruction is converted into |
1337 | imul $imm, %reg, %reg. */ | |
355afbcd KR |
1338 | if (t->opcode_modifier & imulKludge) |
1339 | { | |
c5dd66a1 KR |
1340 | /* Pretend we saw the 3 operand case. */ |
1341 | i.regs[2] = i.regs[1]; | |
355afbcd KR |
1342 | i.reg_operands = 2; |
1343 | } | |
1344 | ||
2fb44892 ILT |
1345 | /* The clr %reg instruction is converted into xor %reg, %reg. */ |
1346 | if (t->opcode_modifier & iclrKludge) | |
1347 | { | |
1348 | i.regs[1] = i.regs[0]; | |
1349 | i.reg_operands = 2; | |
1350 | } | |
1351 | ||
355afbcd | 1352 | /* Certain instructions expect the destination to be in the i.rm.reg |
c5dd66a1 KR |
1353 | field. This is by far the exceptional case. For these |
1354 | instructions, if the source operand is a register, we must reverse | |
1355 | the i.rm.reg and i.rm.regmem fields. We accomplish this by faking | |
1356 | that the two register operands were given in the reverse order. */ | |
355afbcd KR |
1357 | if ((t->opcode_modifier & ReverseRegRegmem) && i.reg_operands == 2) |
1358 | { | |
1359 | unsigned int first_reg_operand = (i.types[0] & Reg) ? 0 : 1; | |
1360 | unsigned int second_reg_operand = first_reg_operand + 1; | |
1361 | reg_entry *tmp = i.regs[first_reg_operand]; | |
1362 | i.regs[first_reg_operand] = i.regs[second_reg_operand]; | |
1363 | i.regs[second_reg_operand] = tmp; | |
1364 | } | |
1365 | ||
1366 | if (t->opcode_modifier & ShortForm) | |
1367 | { | |
1368 | /* The register or float register operand is in operand 0 or 1. */ | |
ad660eb1 | 1369 | unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1; |
355afbcd | 1370 | /* Register goes in low 3 bits of opcode. */ |
ad660eb1 | 1371 | t->base_opcode |= i.regs[op]->reg_num; |
355afbcd KR |
1372 | } |
1373 | else if (t->opcode_modifier & ShortFormW) | |
1374 | { | |
1375 | /* Short form with 0x8 width bit. Register is always dest. operand */ | |
1376 | t->base_opcode |= i.regs[1]->reg_num; | |
1377 | if (i.suffix == WORD_OPCODE_SUFFIX || | |
1378 | i.suffix == DWORD_OPCODE_SUFFIX) | |
1379 | t->base_opcode |= 0x8; | |
1380 | } | |
1381 | else if (t->opcode_modifier & Seg2ShortForm) | |
1382 | { | |
1383 | if (t->base_opcode == POP_SEG_SHORT && i.regs[0]->reg_num == 1) | |
1384 | { | |
1385 | as_bad ("you can't 'pop cs' on the 386."); | |
1386 | return; | |
1387 | } | |
1388 | t->base_opcode |= (i.regs[0]->reg_num << 3); | |
1389 | } | |
1390 | else if (t->opcode_modifier & Seg3ShortForm) | |
1391 | { | |
1392 | /* 'push %fs' is 0x0fa0; 'pop %fs' is 0x0fa1. | |
c5dd66a1 KR |
1393 | 'push %gs' is 0x0fa8; 'pop %fs' is 0x0fa9. |
1394 | So, only if i.regs[0]->reg_num == 5 (%gs) do we need | |
1395 | to change the opcode. */ | |
355afbcd KR |
1396 | if (i.regs[0]->reg_num == 5) |
1397 | t->base_opcode |= 0x08; | |
1398 | } | |
c54c7aac KR |
1399 | else if ((t->base_opcode & ~DW) == MOV_AX_DISP32) |
1400 | { | |
1401 | /* This is a special non-modrm instruction | |
1402 | that addresses memory with a 32-bit displacement mode anyway, | |
1403 | and thus requires an address-size prefix if in 16-bit mode. */ | |
1404 | uses_mem_addrmode = 1; | |
1405 | default_seg = &ds; | |
1406 | } | |
355afbcd KR |
1407 | else if (t->opcode_modifier & Modrm) |
1408 | { | |
1409 | /* The opcode is completed (modulo t->extension_opcode which must | |
c5dd66a1 KR |
1410 | be put into the modrm byte. |
1411 | Now, we make the modrm & index base bytes based on all the info | |
1412 | we've collected. */ | |
355afbcd KR |
1413 | |
1414 | /* i.reg_operands MUST be the number of real register operands; | |
c5dd66a1 | 1415 | implicit registers do not count. */ |
355afbcd KR |
1416 | if (i.reg_operands == 2) |
1417 | { | |
1418 | unsigned int source, dest; | |
454b0ccd ILT |
1419 | source = ((i.types[0] |
1420 | & (Reg | |
1421 | | SReg2 | |
1422 | | SReg3 | |
1423 | | Control | |
1424 | | Debug | |
1425 | | Test | |
1426 | | RegMMX)) | |
1427 | ? 0 : 1); | |
355afbcd KR |
1428 | dest = source + 1; |
1429 | i.rm.mode = 3; | |
c5dd66a1 | 1430 | /* We must be careful to make sure that all |
454b0ccd ILT |
1431 | segment/control/test/debug/MMX registers go into |
1432 | the i.rm.reg field (despite the whether they are | |
1433 | source or destination operands). */ | |
1434 | if (i.regs[dest]->reg_type | |
1435 | & (SReg2 | SReg3 | Control | Debug | Test | RegMMX)) | |
355afbcd KR |
1436 | { |
1437 | i.rm.reg = i.regs[dest]->reg_num; | |
1438 | i.rm.regmem = i.regs[source]->reg_num; | |
1439 | } | |
1440 | else | |
1441 | { | |
1442 | i.rm.reg = i.regs[source]->reg_num; | |
1443 | i.rm.regmem = i.regs[dest]->reg_num; | |
1444 | } | |
1445 | } | |
1446 | else | |
1447 | { /* if it's not 2 reg operands... */ | |
1448 | if (i.mem_operands) | |
1449 | { | |
1450 | unsigned int fake_zero_displacement = 0; | |
ad660eb1 | 1451 | unsigned int op = (i.types[0] & Mem) ? 0 : ((i.types[1] & Mem) ? 1 : 2); |
355afbcd | 1452 | |
49864cfa KR |
1453 | /* Encode memory operand into modrm byte and base index |
1454 | byte. */ | |
355afbcd KR |
1455 | |
1456 | if (i.base_reg == esp && !i.index_reg) | |
1457 | { | |
49864cfa KR |
1458 | /* <disp>(%esp) becomes two byte modrm with no index |
1459 | register. */ | |
355afbcd | 1460 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
ad660eb1 | 1461 | i.rm.mode = mode_from_disp_size (i.types[op]); |
355afbcd KR |
1462 | i.bi.base = ESP_REG_NUM; |
1463 | i.bi.index = NO_INDEX_REGISTER; | |
1464 | i.bi.scale = 0; /* Must be zero! */ | |
1465 | } | |
1466 | else if (i.base_reg == ebp && !i.index_reg) | |
1467 | { | |
ad660eb1 | 1468 | if (!(i.types[op] & Disp)) |
355afbcd | 1469 | { |
49864cfa KR |
1470 | /* Must fake a zero byte displacement. There is |
1471 | no direct way to code '(%ebp)' directly. */ | |
355afbcd KR |
1472 | fake_zero_displacement = 1; |
1473 | /* fake_zero_displacement code does not set this. */ | |
ad660eb1 | 1474 | i.types[op] |= Disp8; |
355afbcd | 1475 | } |
ad660eb1 | 1476 | i.rm.mode = mode_from_disp_size (i.types[op]); |
355afbcd KR |
1477 | i.rm.regmem = EBP_REG_NUM; |
1478 | } | |
ad660eb1 | 1479 | else if (!i.base_reg && (i.types[op] & BaseIndex)) |
355afbcd KR |
1480 | { |
1481 | /* There are three cases here. | |
c5dd66a1 KR |
1482 | Case 1: '<32bit disp>(,1)' -- indirect absolute. |
1483 | (Same as cases 2 & 3 with NO index register) | |
1484 | Case 2: <32bit disp> (,<index>) -- no base register with disp | |
1485 | Case 3: (, <index>) --- no base register; | |
1486 | no disp (must add 32bit 0 disp). */ | |
355afbcd KR |
1487 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
1488 | i.rm.mode = 0; /* 32bit mode */ | |
1489 | i.bi.base = NO_BASE_REGISTER; | |
ad660eb1 ILT |
1490 | i.types[op] &= ~Disp; |
1491 | i.types[op] |= Disp32; /* Must be 32bit! */ | |
355afbcd KR |
1492 | if (i.index_reg) |
1493 | { /* case 2 or case 3 */ | |
1494 | i.bi.index = i.index_reg->reg_num; | |
1495 | i.bi.scale = i.log2_scale_factor; | |
1496 | if (i.disp_operands == 0) | |
1497 | fake_zero_displacement = 1; /* case 3 */ | |
1498 | } | |
1499 | else | |
1500 | { | |
1501 | i.bi.index = NO_INDEX_REGISTER; | |
1502 | i.bi.scale = 0; | |
1503 | } | |
1504 | } | |
1505 | else if (i.disp_operands && !i.base_reg && !i.index_reg) | |
1506 | { | |
1507 | /* Operand is just <32bit disp> */ | |
1508 | i.rm.regmem = EBP_REG_NUM; | |
1509 | i.rm.mode = 0; | |
ad660eb1 ILT |
1510 | i.types[op] &= ~Disp; |
1511 | i.types[op] |= Disp32; | |
355afbcd KR |
1512 | } |
1513 | else | |
1514 | { | |
1515 | /* It's not a special case; rev'em up. */ | |
1516 | i.rm.regmem = i.base_reg->reg_num; | |
ad660eb1 | 1517 | i.rm.mode = mode_from_disp_size (i.types[op]); |
355afbcd KR |
1518 | if (i.index_reg) |
1519 | { | |
1520 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
1521 | i.bi.base = i.base_reg->reg_num; | |
1522 | i.bi.index = i.index_reg->reg_num; | |
1523 | i.bi.scale = i.log2_scale_factor; | |
1524 | if (i.base_reg == ebp && i.disp_operands == 0) | |
1525 | { /* pace */ | |
1526 | fake_zero_displacement = 1; | |
ad660eb1 ILT |
1527 | i.types[op] |= Disp8; |
1528 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
355afbcd KR |
1529 | } |
1530 | } | |
1531 | } | |
1532 | if (fake_zero_displacement) | |
1533 | { | |
ad660eb1 | 1534 | /* Fakes a zero displacement assuming that i.types[op] |
c5dd66a1 | 1535 | holds the correct displacement size. */ |
355afbcd | 1536 | exp = &disp_expressions[i.disp_operands++]; |
ad660eb1 | 1537 | i.disps[op] = exp; |
5ac34ac3 | 1538 | exp->X_op = O_constant; |
355afbcd KR |
1539 | exp->X_add_number = 0; |
1540 | exp->X_add_symbol = (symbolS *) 0; | |
5ac34ac3 | 1541 | exp->X_op_symbol = (symbolS *) 0; |
355afbcd KR |
1542 | } |
1543 | ||
c54c7aac KR |
1544 | /* Find the default segment for the memory operand. |
1545 | Used to optimize out explicit segment specifications. */ | |
355afbcd KR |
1546 | if (i.seg) |
1547 | { | |
1548 | unsigned int seg_index; | |
355afbcd KR |
1549 | |
1550 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING) | |
1551 | { | |
1552 | seg_index = (i.rm.mode << 3) | i.bi.base; | |
1553 | default_seg = two_byte_segment_defaults[seg_index]; | |
1554 | } | |
1555 | else | |
1556 | { | |
1557 | seg_index = (i.rm.mode << 3) | i.rm.regmem; | |
1558 | default_seg = one_byte_segment_defaults[seg_index]; | |
1559 | } | |
355afbcd KR |
1560 | } |
1561 | } | |
1562 | ||
454b0ccd ILT |
1563 | /* Fill in i.rm.reg or i.rm.regmem field with register |
1564 | operand (if any) based on | |
1565 | t->extension_opcode. Again, we must be careful to | |
1566 | make sure that segment/control/debug/test/MMX | |
c5dd66a1 | 1567 | registers are coded into the i.rm.reg field. */ |
355afbcd KR |
1568 | if (i.reg_operands) |
1569 | { | |
ad660eb1 | 1570 | unsigned int op = |
454b0ccd ILT |
1571 | ((i.types[0] |
1572 | & (Reg | SReg2 | SReg3 | Control | Debug | |
1573 | | Test | RegMMX)) | |
1574 | ? 0 | |
1575 | : ((i.types[1] | |
1576 | & (Reg | SReg2 | SReg3 | Control | Debug | |
1577 | | Test | RegMMX)) | |
1578 | ? 1 | |
1579 | : 2)); | |
c5dd66a1 KR |
1580 | /* If there is an extension opcode to put here, the |
1581 | register number must be put into the regmem field. */ | |
355afbcd | 1582 | if (t->extension_opcode != None) |
ad660eb1 | 1583 | i.rm.regmem = i.regs[op]->reg_num; |
355afbcd | 1584 | else |
ad660eb1 | 1585 | i.rm.reg = i.regs[op]->reg_num; |
355afbcd KR |
1586 | |
1587 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 | |
c5dd66a1 KR |
1588 | we must set it to 3 to indicate this is a register |
1589 | operand int the regmem field */ | |
355afbcd KR |
1590 | if (!i.mem_operands) |
1591 | i.rm.mode = 3; | |
1592 | } | |
1593 | ||
1594 | /* Fill in i.rm.reg field with extension opcode (if any). */ | |
1595 | if (t->extension_opcode != None) | |
1596 | i.rm.reg = t->extension_opcode; | |
1597 | } | |
c54c7aac KR |
1598 | |
1599 | if (i.rm.mode != 3) | |
1600 | uses_mem_addrmode = 1; | |
1601 | } | |
1602 | ||
1603 | /* GAS currently doesn't support 16-bit memory addressing modes at all, | |
1604 | so if we're writing 16-bit code and using a memory addressing mode, | |
1605 | always spew out an address size prefix. */ | |
1606 | if (uses_mem_addrmode && flag_16bit_code) | |
1607 | { | |
1608 | if (i.prefixes == MAX_PREFIXES) | |
1609 | { | |
1610 | as_bad ("%d prefixes given and address size override gives too many prefixes", | |
1611 | MAX_PREFIXES); | |
1612 | return; | |
1613 | } | |
1614 | i.prefix[i.prefixes++] = ADDR_PREFIX_OPCODE; | |
1615 | } | |
1616 | ||
1617 | /* If a segment was explicitly specified, | |
1618 | and the specified segment is not the default, | |
1619 | use an opcode prefix to select it. | |
1620 | If we never figured out what the default segment is, | |
1621 | then default_seg will be zero at this point, | |
1622 | and the specified segment prefix will always be used. */ | |
1623 | if ((i.seg) && (i.seg != default_seg)) | |
1624 | { | |
1625 | if (i.prefixes == MAX_PREFIXES) | |
1626 | { | |
1627 | as_bad ("%d prefixes given and %s segment override gives too many prefixes", | |
1628 | MAX_PREFIXES, i.seg->seg_name); | |
1629 | return; | |
1630 | } | |
1631 | i.prefix[i.prefixes++] = i.seg->seg_prefix; | |
355afbcd KR |
1632 | } |
1633 | } | |
1634 | } | |
1635 | ||
1636 | /* Handle conversion of 'int $3' --> special int3 insn. */ | |
1637 | if (t->base_opcode == INT_OPCODE && i.imms[0]->X_add_number == 3) | |
1638 | { | |
1639 | t->base_opcode = INT3_OPCODE; | |
1640 | i.imm_operands = 0; | |
1641 | } | |
1642 | ||
1643 | /* We are ready to output the insn. */ | |
1644 | { | |
1645 | register char *p; | |
1646 | ||
1647 | /* Output jumps. */ | |
1648 | if (t->opcode_modifier & Jump) | |
1649 | { | |
ad660eb1 | 1650 | unsigned long n = i.disps[0]->X_add_number; |
355afbcd | 1651 | |
5ac34ac3 | 1652 | if (i.disps[0]->X_op == O_constant) |
355afbcd | 1653 | { |
355afbcd KR |
1654 | if (fits_in_signed_byte (n)) |
1655 | { | |
1656 | p = frag_more (2); | |
ad660eb1 | 1657 | insn_size += 2; |
355afbcd KR |
1658 | p[0] = t->base_opcode; |
1659 | p[1] = n; | |
355afbcd | 1660 | } |
355afbcd | 1661 | else |
c54c7aac KR |
1662 | { /* It's an absolute word/dword displacement. */ |
1663 | ||
1664 | /* Use only 16-bit jumps for 16-bit code, | |
1665 | because text segments are limited to 64K anyway; | |
1666 | use only 32-bit jumps for 32-bit code, | |
1667 | because they're faster. */ | |
1668 | int jmp_size = flag_16bit_code ? 2 : 4; | |
1669 | if (flag_16bit_code && !fits_in_signed_word (n)) | |
1670 | { | |
1671 | as_bad ("16-bit jump out of range"); | |
1672 | return; | |
1673 | } | |
1674 | ||
355afbcd KR |
1675 | if (t->base_opcode == JUMP_PC_RELATIVE) |
1676 | { /* pace */ | |
1677 | /* unconditional jump */ | |
c54c7aac KR |
1678 | p = frag_more (1 + jmp_size); |
1679 | insn_size += 1 + jmp_size; | |
7b23213f | 1680 | p[0] = (char) 0xe9; |
c54c7aac | 1681 | md_number_to_chars (&p[1], (valueT) n, jmp_size); |
355afbcd KR |
1682 | } |
1683 | else | |
1684 | { | |
1685 | /* conditional jump */ | |
c54c7aac KR |
1686 | p = frag_more (2 + jmp_size); |
1687 | insn_size += 2 + jmp_size; | |
355afbcd KR |
1688 | p[0] = TWO_BYTE_OPCODE_ESCAPE; |
1689 | p[1] = t->base_opcode + 0x10; | |
c54c7aac | 1690 | md_number_to_chars (&p[2], (valueT) n, jmp_size); |
355afbcd KR |
1691 | } |
1692 | } | |
49864cfa KR |
1693 | } |
1694 | else | |
1695 | { | |
c54c7aac KR |
1696 | if (flag_16bit_code) |
1697 | { | |
1698 | FRAG_APPEND_1_CHAR (WORD_PREFIX_OPCODE); | |
1699 | insn_size += 1; | |
1700 | } | |
1701 | ||
355afbcd | 1702 | /* It's a symbol; end frag & setup for relax. |
49864cfa KR |
1703 | Make sure there are more than 6 chars left in the current frag; |
1704 | if not we'll have to start a new one. */ | |
3ea36b53 | 1705 | frag_grow (7); |
355afbcd | 1706 | p = frag_more (1); |
ad660eb1 | 1707 | insn_size += 1; |
355afbcd KR |
1708 | p[0] = t->base_opcode; |
1709 | frag_var (rs_machine_dependent, | |
1710 | 6, /* 2 opcode/prefix + 4 displacement */ | |
1711 | 1, | |
1712 | ((unsigned char) *p == JUMP_PC_RELATIVE | |
1713 | ? ENCODE_RELAX_STATE (UNCOND_JUMP, BYTE) | |
1714 | : ENCODE_RELAX_STATE (COND_JUMP, BYTE)), | |
1715 | i.disps[0]->X_add_symbol, | |
f59fb6ca | 1716 | (offsetT) n, p); |
355afbcd KR |
1717 | } |
1718 | } | |
1719 | else if (t->opcode_modifier & (JumpByte | JumpDword)) | |
1720 | { | |
1721 | int size = (t->opcode_modifier & JumpByte) ? 1 : 4; | |
ad660eb1 | 1722 | unsigned long n = i.disps[0]->X_add_number; |
c54c7aac KR |
1723 | unsigned char *q; |
1724 | ||
1725 | /* The jcx/jecx instruction might need a data size prefix. */ | |
1726 | for (q = i.prefix; q < i.prefix + i.prefixes; q++) | |
1727 | { | |
1728 | if (*q == WORD_PREFIX_OPCODE) | |
1729 | { | |
1730 | FRAG_APPEND_1_CHAR (WORD_PREFIX_OPCODE); | |
1731 | insn_size += 1; | |
1732 | break; | |
1733 | } | |
1734 | } | |
1735 | ||
1736 | if ((size == 4) && (flag_16bit_code)) | |
1737 | { | |
1738 | FRAG_APPEND_1_CHAR (WORD_PREFIX_OPCODE); | |
1739 | insn_size += 1; | |
1740 | } | |
355afbcd KR |
1741 | |
1742 | if (fits_in_unsigned_byte (t->base_opcode)) | |
1743 | { | |
1744 | FRAG_APPEND_1_CHAR (t->base_opcode); | |
ad660eb1 | 1745 | insn_size += 1; |
355afbcd KR |
1746 | } |
1747 | else | |
1748 | { | |
1749 | p = frag_more (2); /* opcode can be at most two bytes */ | |
ad660eb1 | 1750 | insn_size += 2; |
355afbcd KR |
1751 | /* put out high byte first: can't use md_number_to_chars! */ |
1752 | *p++ = (t->base_opcode >> 8) & 0xff; | |
1753 | *p = t->base_opcode & 0xff; | |
1754 | } | |
1755 | ||
1756 | p = frag_more (size); | |
ad660eb1 | 1757 | insn_size += size; |
5ac34ac3 | 1758 | if (i.disps[0]->X_op == O_constant) |
355afbcd | 1759 | { |
ad660eb1 | 1760 | md_number_to_chars (p, (valueT) n, size); |
355afbcd KR |
1761 | if (size == 1 && !fits_in_signed_byte (n)) |
1762 | { | |
ad660eb1 | 1763 | as_bad ("loop/jecx only takes byte displacement; %lu shortened to %d", |
355afbcd KR |
1764 | n, *p); |
1765 | } | |
49864cfa KR |
1766 | } |
1767 | else | |
1768 | { | |
5ac34ac3 | 1769 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
f0b37b4a KR |
1770 | i.disps[0], 1, reloc (size, 1, i.disp_reloc[0])); |
1771 | ||
355afbcd KR |
1772 | } |
1773 | } | |
1774 | else if (t->opcode_modifier & JumpInterSegment) | |
1775 | { | |
c54c7aac KR |
1776 | if (flag_16bit_code) |
1777 | { | |
1778 | FRAG_APPEND_1_CHAR (WORD_PREFIX_OPCODE); | |
1779 | insn_size += 1; | |
1780 | } | |
1781 | ||
355afbcd | 1782 | p = frag_more (1 + 2 + 4); /* 1 opcode; 2 segment; 4 offset */ |
ad660eb1 | 1783 | insn_size += 1 + 2 + 4; |
355afbcd | 1784 | p[0] = t->base_opcode; |
5ac34ac3 | 1785 | if (i.imms[1]->X_op == O_constant) |
ad660eb1 | 1786 | md_number_to_chars (p + 1, (valueT) i.imms[1]->X_add_number, 4); |
355afbcd | 1787 | else |
5ac34ac3 | 1788 | fix_new_exp (frag_now, p + 1 - frag_now->fr_literal, 4, |
7b23213f | 1789 | i.imms[1], 0, BFD_RELOC_32); |
5ac34ac3 | 1790 | if (i.imms[0]->X_op != O_constant) |
355afbcd | 1791 | as_bad ("can't handle non absolute segment in long call/jmp"); |
ad660eb1 | 1792 | md_number_to_chars (p + 5, (valueT) i.imms[0]->X_add_number, 2); |
355afbcd KR |
1793 | } |
1794 | else | |
1795 | { | |
1796 | /* Output normal instructions here. */ | |
1797 | unsigned char *q; | |
1798 | ||
1799 | /* First the prefix bytes. */ | |
1800 | for (q = i.prefix; q < i.prefix + i.prefixes; q++) | |
1801 | { | |
1802 | p = frag_more (1); | |
ad660eb1 ILT |
1803 | insn_size += 1; |
1804 | md_number_to_chars (p, (valueT) *q, 1); | |
355afbcd KR |
1805 | } |
1806 | ||
1807 | /* Now the opcode; be careful about word order here! */ | |
1808 | if (fits_in_unsigned_byte (t->base_opcode)) | |
1809 | { | |
1810 | FRAG_APPEND_1_CHAR (t->base_opcode); | |
ad660eb1 | 1811 | insn_size += 1; |
355afbcd KR |
1812 | } |
1813 | else if (fits_in_unsigned_word (t->base_opcode)) | |
1814 | { | |
1815 | p = frag_more (2); | |
ad660eb1 | 1816 | insn_size += 2; |
355afbcd KR |
1817 | /* put out high byte first: can't use md_number_to_chars! */ |
1818 | *p++ = (t->base_opcode >> 8) & 0xff; | |
1819 | *p = t->base_opcode & 0xff; | |
1820 | } | |
1821 | else | |
1822 | { /* opcode is either 3 or 4 bytes */ | |
1823 | if (t->base_opcode & 0xff000000) | |
1824 | { | |
1825 | p = frag_more (4); | |
ad660eb1 | 1826 | insn_size += 4; |
355afbcd KR |
1827 | *p++ = (t->base_opcode >> 24) & 0xff; |
1828 | } | |
1829 | else | |
ad660eb1 ILT |
1830 | { |
1831 | p = frag_more (3); | |
1832 | insn_size += 3; | |
1833 | } | |
355afbcd KR |
1834 | *p++ = (t->base_opcode >> 16) & 0xff; |
1835 | *p++ = (t->base_opcode >> 8) & 0xff; | |
1836 | *p = (t->base_opcode) & 0xff; | |
1837 | } | |
1838 | ||
1839 | /* Now the modrm byte and base index byte (if present). */ | |
1840 | if (t->opcode_modifier & Modrm) | |
1841 | { | |
1842 | p = frag_more (1); | |
ad660eb1 | 1843 | insn_size += 1; |
355afbcd | 1844 | /* md_number_to_chars (p, i.rm, 1); */ |
ad660eb1 ILT |
1845 | md_number_to_chars (p, |
1846 | (valueT) (i.rm.regmem << 0 | |
1847 | | i.rm.reg << 3 | |
1848 | | i.rm.mode << 6), | |
1849 | 1); | |
355afbcd | 1850 | /* If i.rm.regmem == ESP (4) && i.rm.mode != Mode 3 (Register mode) |
a39116f1 | 1851 | ==> need second modrm byte. */ |
355afbcd KR |
1852 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING && i.rm.mode != 3) |
1853 | { | |
1854 | p = frag_more (1); | |
ad660eb1 | 1855 | insn_size += 1; |
355afbcd | 1856 | /* md_number_to_chars (p, i.bi, 1); */ |
ad660eb1 ILT |
1857 | md_number_to_chars (p, (valueT) (i.bi.base << 0 |
1858 | | i.bi.index << 3 | |
1859 | | i.bi.scale << 6), | |
1860 | 1); | |
355afbcd KR |
1861 | } |
1862 | } | |
1863 | ||
1864 | if (i.disp_operands) | |
1865 | { | |
1866 | register unsigned int n; | |
1867 | ||
1868 | for (n = 0; n < i.operands; n++) | |
1869 | { | |
1870 | if (i.disps[n]) | |
1871 | { | |
5ac34ac3 | 1872 | if (i.disps[n]->X_op == O_constant) |
355afbcd KR |
1873 | { |
1874 | if (i.types[n] & (Disp8 | Abs8)) | |
1875 | { | |
1876 | p = frag_more (1); | |
ad660eb1 ILT |
1877 | insn_size += 1; |
1878 | md_number_to_chars (p, | |
1879 | (valueT) i.disps[n]->X_add_number, | |
1880 | 1); | |
355afbcd KR |
1881 | } |
1882 | else if (i.types[n] & (Disp16 | Abs16)) | |
1883 | { | |
1884 | p = frag_more (2); | |
ad660eb1 ILT |
1885 | insn_size += 2; |
1886 | md_number_to_chars (p, | |
1887 | (valueT) i.disps[n]->X_add_number, | |
1888 | 2); | |
355afbcd KR |
1889 | } |
1890 | else | |
1891 | { /* Disp32|Abs32 */ | |
1892 | p = frag_more (4); | |
ad660eb1 ILT |
1893 | insn_size += 4; |
1894 | md_number_to_chars (p, | |
1895 | (valueT) i.disps[n]->X_add_number, | |
1896 | 4); | |
355afbcd KR |
1897 | } |
1898 | } | |
1899 | else | |
49864cfa | 1900 | { /* not absolute_section */ |
355afbcd KR |
1901 | /* need a 32-bit fixup (don't support 8bit non-absolute disps) */ |
1902 | p = frag_more (4); | |
ad660eb1 | 1903 | insn_size += 4; |
5ac34ac3 | 1904 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, |
f0b37b4a KR |
1905 | i.disps[n], 0, |
1906 | TC_RELOC(i.disp_reloc[n], BFD_RELOC_32)); | |
355afbcd KR |
1907 | } |
1908 | } | |
1909 | } | |
1910 | } /* end displacement output */ | |
1911 | ||
1912 | /* output immediate */ | |
1913 | if (i.imm_operands) | |
1914 | { | |
1915 | register unsigned int n; | |
1916 | ||
1917 | for (n = 0; n < i.operands; n++) | |
1918 | { | |
1919 | if (i.imms[n]) | |
1920 | { | |
5ac34ac3 | 1921 | if (i.imms[n]->X_op == O_constant) |
355afbcd KR |
1922 | { |
1923 | if (i.types[n] & (Imm8 | Imm8S)) | |
1924 | { | |
1925 | p = frag_more (1); | |
ad660eb1 ILT |
1926 | insn_size += 1; |
1927 | md_number_to_chars (p, | |
1928 | (valueT) i.imms[n]->X_add_number, | |
1929 | 1); | |
355afbcd KR |
1930 | } |
1931 | else if (i.types[n] & Imm16) | |
1932 | { | |
1933 | p = frag_more (2); | |
ad660eb1 ILT |
1934 | insn_size += 2; |
1935 | md_number_to_chars (p, | |
1936 | (valueT) i.imms[n]->X_add_number, | |
1937 | 2); | |
355afbcd KR |
1938 | } |
1939 | else | |
1940 | { | |
1941 | p = frag_more (4); | |
ad660eb1 ILT |
1942 | insn_size += 4; |
1943 | md_number_to_chars (p, | |
1944 | (valueT) i.imms[n]->X_add_number, | |
1945 | 4); | |
355afbcd KR |
1946 | } |
1947 | } | |
1948 | else | |
49864cfa | 1949 | { /* not absolute_section */ |
f0b37b4a KR |
1950 | /* Need a 32-bit fixup (don't support 8bit |
1951 | non-absolute ims). Try to support other | |
1952 | sizes ... */ | |
1953 | int r_type; | |
355afbcd | 1954 | int size; |
f0b37b4a KR |
1955 | int pcrel = 0; |
1956 | ||
355afbcd KR |
1957 | if (i.types[n] & (Imm8 | Imm8S)) |
1958 | size = 1; | |
1959 | else if (i.types[n] & Imm16) | |
1960 | size = 2; | |
1961 | else | |
1962 | size = 4; | |
f0b37b4a | 1963 | r_type = reloc (size, 0, i.disp_reloc[0]); |
355afbcd | 1964 | p = frag_more (size); |
ad660eb1 | 1965 | insn_size += size; |
f0b37b4a | 1966 | #ifdef BFD_ASSEMBLER |
c54c7aac | 1967 | if (r_type == BFD_RELOC_32 |
f0b37b4a | 1968 | && GOT_symbol |
0877841d ILT |
1969 | && GOT_symbol == i.imms[n]->X_add_symbol |
1970 | && (i.imms[n]->X_op == O_symbol | |
1971 | || (i.imms[n]->X_op == O_add | |
1972 | && (i.imms[n]->X_op_symbol->sy_value.X_op | |
1973 | == O_subtract)))) | |
f0b37b4a KR |
1974 | { |
1975 | r_type = BFD_RELOC_386_GOTPC; | |
1976 | i.imms[n]->X_add_number += 3; | |
1977 | } | |
1978 | #endif | |
5ac34ac3 | 1979 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
f0b37b4a | 1980 | i.imms[n], pcrel, r_type); |
355afbcd KR |
1981 | } |
1982 | } | |
1983 | } | |
1984 | } /* end immediate output */ | |
1985 | } | |
1986 | ||
fecd2382 | 1987 | #ifdef DEBUG386 |
ade614d5 | 1988 | if (flag_debug) |
355afbcd KR |
1989 | { |
1990 | pi (line, &i); | |
1991 | } | |
fecd2382 | 1992 | #endif /* DEBUG386 */ |
355afbcd | 1993 | } |
fecd2382 RP |
1994 | } |
1995 | \f | |
1996 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero | |
1997 | on error. */ | |
1998 | ||
355afbcd KR |
1999 | static int |
2000 | i386_operand (operand_string) | |
2001 | char *operand_string; | |
fecd2382 | 2002 | { |
355afbcd KR |
2003 | register char *op_string = operand_string; |
2004 | ||
2005 | /* Address of '\0' at end of operand_string. */ | |
2006 | char *end_of_operand_string = operand_string + strlen (operand_string); | |
2007 | ||
2008 | /* Start and end of displacement string expression (if found). */ | |
2009 | char *displacement_string_start = NULL; | |
2010 | char *displacement_string_end = NULL; | |
2011 | ||
2012 | /* We check for an absolute prefix (differentiating, | |
3c8df4ba | 2013 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
355afbcd KR |
2014 | if (*op_string == ABSOLUTE_PREFIX) |
2015 | { | |
2016 | op_string++; | |
2017 | i.types[this_operand] |= JumpAbsolute; | |
2018 | } | |
2019 | ||
2020 | /* Check if operand is a register. */ | |
2021 | if (*op_string == REGISTER_PREFIX) | |
2022 | { | |
2023 | register reg_entry *r; | |
2024 | if (!(r = parse_register (op_string))) | |
2025 | { | |
2026 | as_bad ("bad register name ('%s')", op_string); | |
2027 | return 0; | |
fecd2382 | 2028 | } |
355afbcd | 2029 | /* Check for segment override, rather than segment register by |
3c8df4ba | 2030 | searching for ':' after %<x>s where <x> = s, c, d, e, f, g. */ |
355afbcd KR |
2031 | if ((r->reg_type & (SReg2 | SReg3)) && op_string[3] == ':') |
2032 | { | |
2033 | switch (r->reg_num) | |
2034 | { | |
2035 | case 0: | |
2036 | i.seg = (seg_entry *) & es; | |
2037 | break; | |
2038 | case 1: | |
2039 | i.seg = (seg_entry *) & cs; | |
2040 | break; | |
2041 | case 2: | |
2042 | i.seg = (seg_entry *) & ss; | |
2043 | break; | |
2044 | case 3: | |
2045 | i.seg = (seg_entry *) & ds; | |
2046 | break; | |
2047 | case 4: | |
2048 | i.seg = (seg_entry *) & fs; | |
2049 | break; | |
2050 | case 5: | |
2051 | i.seg = (seg_entry *) & gs; | |
2052 | break; | |
2053 | } | |
2054 | op_string += 4; /* skip % <x> s : */ | |
2055 | operand_string = op_string; /* Pretend given string starts here. */ | |
2056 | if (!is_digit_char (*op_string) && !is_identifier_char (*op_string) | |
2057 | && *op_string != '(' && *op_string != ABSOLUTE_PREFIX) | |
2058 | { | |
2059 | as_bad ("bad memory operand after segment override"); | |
2060 | return 0; | |
2061 | } | |
2062 | /* Handle case of %es:*foo. */ | |
2063 | if (*op_string == ABSOLUTE_PREFIX) | |
2064 | { | |
2065 | op_string++; | |
2066 | i.types[this_operand] |= JumpAbsolute; | |
2067 | } | |
2068 | goto do_memory_reference; | |
2069 | } | |
2070 | i.types[this_operand] |= r->reg_type; | |
2071 | i.regs[this_operand] = r; | |
2072 | i.reg_operands++; | |
2073 | } | |
2074 | else if (*op_string == IMMEDIATE_PREFIX) | |
2075 | { /* ... or an immediate */ | |
2076 | char *save_input_line_pointer; | |
49864cfa | 2077 | segT exp_seg = 0; |
355afbcd KR |
2078 | expressionS *exp; |
2079 | ||
2080 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
2081 | { | |
2082 | as_bad ("only 1 or 2 immediate operands are allowed"); | |
2083 | return 0; | |
2084 | } | |
542e1629 | 2085 | |
355afbcd KR |
2086 | exp = &im_expressions[i.imm_operands++]; |
2087 | i.imms[this_operand] = exp; | |
2088 | save_input_line_pointer = input_line_pointer; | |
2089 | input_line_pointer = ++op_string; /* must advance op_string! */ | |
ad660eb1 | 2090 | SKIP_WHITESPACE (); |
355afbcd KR |
2091 | exp_seg = expression (exp); |
2092 | input_line_pointer = save_input_line_pointer; | |
2093 | ||
7b23213f | 2094 | if (exp->X_op == O_absent) |
355afbcd | 2095 | { |
49864cfa | 2096 | /* missing or bad expr becomes absolute 0 */ |
355afbcd KR |
2097 | as_bad ("missing or invalid immediate expression '%s' taken as 0", |
2098 | operand_string); | |
5ac34ac3 | 2099 | exp->X_op = O_constant; |
355afbcd KR |
2100 | exp->X_add_number = 0; |
2101 | exp->X_add_symbol = (symbolS *) 0; | |
5ac34ac3 | 2102 | exp->X_op_symbol = (symbolS *) 0; |
355afbcd | 2103 | i.types[this_operand] |= Imm; |
49864cfa | 2104 | } |
7b23213f | 2105 | else if (exp->X_op == O_constant) |
49864cfa | 2106 | { |
ad660eb1 ILT |
2107 | i.types[this_operand] |= |
2108 | smallest_imm_type ((unsigned long) exp->X_add_number); | |
49864cfa | 2109 | } |
7b23213f | 2110 | #ifdef OBJ_AOUT |
49864cfa KR |
2111 | else if (exp_seg != text_section |
2112 | && exp_seg != data_section | |
2113 | && exp_seg != bss_section | |
2114 | && exp_seg != undefined_section | |
2115 | #ifdef BFD_ASSEMBLER | |
2116 | && ! bfd_is_com_section (exp_seg) | |
2117 | #endif | |
2118 | ) | |
2119 | { | |
355afbcd KR |
2120 | seg_unimplemented: |
2121 | as_bad ("Unimplemented segment type %d in parse_operand", exp_seg); | |
2122 | return 0; | |
2123 | } | |
49864cfa KR |
2124 | #endif |
2125 | else | |
2126 | { | |
2127 | /* this is an address ==> 32bit */ | |
2128 | i.types[this_operand] |= Imm32; | |
2129 | } | |
355afbcd | 2130 | /* shorten this type of this operand if the instruction wants |
49864cfa KR |
2131 | * fewer bits than are present in the immediate. The bit field |
2132 | * code can put out 'andb $0xffffff, %al', for example. pace | |
2133 | * also 'movw $foo,(%eax)' | |
2134 | */ | |
355afbcd KR |
2135 | switch (i.suffix) |
2136 | { | |
2137 | case WORD_OPCODE_SUFFIX: | |
2138 | i.types[this_operand] |= Imm16; | |
2139 | break; | |
2140 | case BYTE_OPCODE_SUFFIX: | |
2141 | i.types[this_operand] |= Imm16 | Imm8 | Imm8S; | |
2142 | break; | |
2143 | } | |
2144 | } | |
2145 | else if (is_digit_char (*op_string) || is_identifier_char (*op_string) | |
2146 | || *op_string == '(') | |
2147 | { | |
2148 | /* This is a memory reference of some sort. */ | |
2149 | register char *base_string; | |
2150 | unsigned int found_base_index_form; | |
2151 | ||
2152 | do_memory_reference: | |
2153 | if (i.mem_operands == MAX_MEMORY_OPERANDS) | |
2154 | { | |
2155 | as_bad ("more than 1 memory reference in instruction"); | |
2156 | return 0; | |
2157 | } | |
2158 | i.mem_operands++; | |
2159 | ||
2160 | /* Determine type of memory operand from opcode_suffix; | |
a39116f1 | 2161 | no opcode suffix implies general memory references. */ |
355afbcd KR |
2162 | switch (i.suffix) |
2163 | { | |
2164 | case BYTE_OPCODE_SUFFIX: | |
2165 | i.types[this_operand] |= Mem8; | |
2166 | break; | |
2167 | case WORD_OPCODE_SUFFIX: | |
2168 | i.types[this_operand] |= Mem16; | |
2169 | break; | |
2170 | case DWORD_OPCODE_SUFFIX: | |
2171 | default: | |
2172 | i.types[this_operand] |= Mem32; | |
2173 | } | |
2174 | ||
49864cfa KR |
2175 | /* Check for base index form. We detect the base index form by |
2176 | looking for an ')' at the end of the operand, searching | |
2177 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
2178 | after it. */ | |
355afbcd KR |
2179 | base_string = end_of_operand_string - 1; |
2180 | found_base_index_form = 0; | |
2181 | if (*base_string == ')') | |
2182 | { | |
0b476c53 | 2183 | unsigned int parens_balanced = 1; |
49864cfa KR |
2184 | /* We've already checked that the number of left & right ()'s are |
2185 | equal, so this loop will not be infinite. */ | |
355afbcd KR |
2186 | do |
2187 | { | |
2188 | base_string--; | |
2189 | if (*base_string == ')') | |
0b476c53 | 2190 | parens_balanced++; |
355afbcd | 2191 | if (*base_string == '(') |
0b476c53 | 2192 | parens_balanced--; |
355afbcd | 2193 | } |
0b476c53 | 2194 | while (parens_balanced); |
355afbcd KR |
2195 | base_string++; /* Skip past '('. */ |
2196 | if (*base_string == REGISTER_PREFIX || *base_string == ',') | |
2197 | found_base_index_form = 1; | |
2198 | } | |
2199 | ||
2200 | /* If we can't parse a base index register expression, we've found | |
49864cfa KR |
2201 | a pure displacement expression. We set up displacement_string_start |
2202 | and displacement_string_end for the code below. */ | |
355afbcd KR |
2203 | if (!found_base_index_form) |
2204 | { | |
2205 | displacement_string_start = op_string; | |
2206 | displacement_string_end = end_of_operand_string; | |
2207 | } | |
2208 | else | |
2209 | { | |
2210 | char *base_reg_name, *index_reg_name, *num_string; | |
2211 | int num; | |
2212 | ||
2213 | i.types[this_operand] |= BaseIndex; | |
2214 | ||
2215 | /* If there is a displacement set-up for it to be parsed later. */ | |
2216 | if (base_string != op_string + 1) | |
2217 | { | |
2218 | displacement_string_start = op_string; | |
2219 | displacement_string_end = base_string - 1; | |
2220 | } | |
2221 | ||
2222 | /* Find base register (if any). */ | |
2223 | if (*base_string != ',') | |
2224 | { | |
2225 | base_reg_name = base_string++; | |
2226 | /* skip past register name & parse it */ | |
2227 | while (isalpha (*base_string)) | |
2228 | base_string++; | |
2229 | if (base_string == base_reg_name + 1) | |
2230 | { | |
2231 | as_bad ("can't find base register name after '(%c'", | |
2232 | REGISTER_PREFIX); | |
2233 | return 0; | |
2234 | } | |
2235 | END_STRING_AND_SAVE (base_string); | |
2236 | if (!(i.base_reg = parse_register (base_reg_name))) | |
2237 | { | |
2238 | as_bad ("bad base register name ('%s')", base_reg_name); | |
2239 | return 0; | |
2240 | } | |
2241 | RESTORE_END_STRING (base_string); | |
2242 | } | |
2243 | ||
2244 | /* Now check seperator; must be ',' ==> index reg | |
a39116f1 RP |
2245 | OR num ==> no index reg. just scale factor |
2246 | OR ')' ==> end. (scale factor = 1) */ | |
355afbcd KR |
2247 | if (*base_string != ',' && *base_string != ')') |
2248 | { | |
2249 | as_bad ("expecting ',' or ')' after base register in `%s'", | |
2250 | operand_string); | |
2251 | return 0; | |
2252 | } | |
2253 | ||
2254 | /* There may index reg here; and there may be a scale factor. */ | |
2255 | if (*base_string == ',' && *(base_string + 1) == REGISTER_PREFIX) | |
2256 | { | |
2257 | index_reg_name = ++base_string; | |
2258 | while (isalpha (*++base_string)); | |
2259 | END_STRING_AND_SAVE (base_string); | |
2260 | if (!(i.index_reg = parse_register (index_reg_name))) | |
2261 | { | |
2262 | as_bad ("bad index register name ('%s')", index_reg_name); | |
2263 | return 0; | |
a39116f1 | 2264 | } |
355afbcd KR |
2265 | RESTORE_END_STRING (base_string); |
2266 | } | |
2267 | ||
2268 | /* Check for scale factor. */ | |
2269 | if (*base_string == ',' && isdigit (*(base_string + 1))) | |
2270 | { | |
2271 | num_string = ++base_string; | |
2272 | while (is_digit_char (*base_string)) | |
2273 | base_string++; | |
2274 | if (base_string == num_string) | |
2275 | { | |
2276 | as_bad ("can't find a scale factor after ','"); | |
2277 | return 0; | |
a39116f1 | 2278 | } |
355afbcd KR |
2279 | END_STRING_AND_SAVE (base_string); |
2280 | /* We've got a scale factor. */ | |
2281 | if (!sscanf (num_string, "%d", &num)) | |
2282 | { | |
2283 | as_bad ("can't parse scale factor from '%s'", num_string); | |
2284 | return 0; | |
a39116f1 | 2285 | } |
355afbcd KR |
2286 | RESTORE_END_STRING (base_string); |
2287 | switch (num) | |
2288 | { /* must be 1 digit scale */ | |
2289 | case 1: | |
2290 | i.log2_scale_factor = 0; | |
2291 | break; | |
2292 | case 2: | |
2293 | i.log2_scale_factor = 1; | |
2294 | break; | |
2295 | case 4: | |
2296 | i.log2_scale_factor = 2; | |
2297 | break; | |
2298 | case 8: | |
2299 | i.log2_scale_factor = 3; | |
2300 | break; | |
2301 | default: | |
2302 | as_bad ("expecting scale factor of 1, 2, 4, 8; got %d", num); | |
2303 | return 0; | |
a39116f1 | 2304 | } |
355afbcd KR |
2305 | } |
2306 | else | |
2307 | { | |
2308 | if (!i.index_reg && *base_string == ',') | |
2309 | { | |
2310 | as_bad ("expecting index register or scale factor after ','; got '%c'", | |
2311 | *(base_string + 1)); | |
2312 | return 0; | |
a39116f1 | 2313 | } |
355afbcd KR |
2314 | } |
2315 | } | |
2316 | ||
2317 | /* If there's an expression begining the operand, parse it, | |
49864cfa KR |
2318 | assuming displacement_string_start and displacement_string_end |
2319 | are meaningful. */ | |
355afbcd KR |
2320 | if (displacement_string_start) |
2321 | { | |
2322 | register expressionS *exp; | |
49864cfa | 2323 | segT exp_seg = 0; |
355afbcd KR |
2324 | char *save_input_line_pointer; |
2325 | exp = &disp_expressions[i.disp_operands]; | |
2326 | i.disps[this_operand] = exp; | |
f0b37b4a | 2327 | i.disp_reloc[this_operand] = NO_RELOC; |
355afbcd KR |
2328 | i.disp_operands++; |
2329 | save_input_line_pointer = input_line_pointer; | |
2330 | input_line_pointer = displacement_string_start; | |
2331 | END_STRING_AND_SAVE (displacement_string_end); | |
30355216 | 2332 | #ifndef LEX_AT |
f0b37b4a KR |
2333 | { |
2334 | /* | |
2335 | * We can have operands of the form | |
2336 | * <symbol>@GOTOFF+<nnn> | |
2337 | * Take the easy way out here and copy everything | |
2338 | * into a temporary buffer... | |
2339 | */ | |
2340 | register char *cp; | |
0877841d | 2341 | if ((cp = strchr (input_line_pointer,'@')) != NULL) { |
f0b37b4a KR |
2342 | char tmpbuf[BUFSIZ]; |
2343 | ||
2344 | if(!GOT_symbol) | |
2345 | GOT_symbol = symbol_find_or_make(GLOBAL_OFFSET_TABLE_NAME); | |
2346 | ||
2347 | if (strncmp(cp+1, "PLT", 3) == 0) { | |
2348 | i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32; | |
2349 | *cp = '\0'; | |
2350 | strcpy(tmpbuf, input_line_pointer); | |
2351 | strcat(tmpbuf, cp+1+3); | |
2352 | *cp = '@'; | |
2353 | } else if (strncmp(cp+1, "GOTOFF", 6) == 0) { | |
2354 | i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF; | |
2355 | *cp = '\0'; | |
2356 | strcpy(tmpbuf, input_line_pointer); | |
2357 | strcat(tmpbuf, cp+1+6); | |
2358 | *cp = '@'; | |
2359 | } else if (strncmp(cp+1, "GOT", 3) == 0) { | |
2360 | i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32; | |
2361 | *cp = '\0'; | |
2362 | strcpy(tmpbuf, input_line_pointer); | |
2363 | strcat(tmpbuf, cp+1+3); | |
2364 | *cp = '@'; | |
2365 | } else | |
2366 | as_bad("Bad reloc specifier '%s' in expression", cp+1); | |
2367 | input_line_pointer = tmpbuf; | |
2368 | } | |
2369 | } | |
30355216 | 2370 | #endif |
355afbcd | 2371 | exp_seg = expression (exp); |
f0b37b4a KR |
2372 | |
2373 | #ifdef BFD_ASSEMBLER | |
2374 | /* We do this to make sure that the section symbol is in | |
2375 | the symbol table. We will ultimately change the relocation | |
2376 | to be relative to the beginning of the section */ | |
c54c7aac KR |
2377 | if (i.disp_reloc[this_operand] == BFD_RELOC_386_GOTOFF) |
2378 | { | |
2379 | if (S_IS_LOCAL(exp->X_add_symbol) | |
2380 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section) | |
2381 | section_symbol(exp->X_add_symbol->bsym->section); | |
2382 | assert (exp->X_op == O_symbol); | |
2383 | exp->X_op = O_subtract; | |
2384 | exp->X_op_symbol = GOT_symbol; | |
2385 | i.disp_reloc[this_operand] = BFD_RELOC_32; | |
2386 | } | |
f0b37b4a KR |
2387 | #endif |
2388 | ||
355afbcd KR |
2389 | if (*input_line_pointer) |
2390 | as_bad ("Ignoring junk '%s' after expression", input_line_pointer); | |
2391 | RESTORE_END_STRING (displacement_string_end); | |
2392 | input_line_pointer = save_input_line_pointer; | |
7b23213f | 2393 | if (exp->X_op == O_absent) |
355afbcd | 2394 | { |
355afbcd KR |
2395 | /* missing expr becomes absolute 0 */ |
2396 | as_bad ("missing or invalid displacement '%s' taken as 0", | |
2397 | operand_string); | |
2398 | i.types[this_operand] |= (Disp | Abs); | |
5ac34ac3 | 2399 | exp->X_op = O_constant; |
355afbcd KR |
2400 | exp->X_add_number = 0; |
2401 | exp->X_add_symbol = (symbolS *) 0; | |
5ac34ac3 | 2402 | exp->X_op_symbol = (symbolS *) 0; |
49864cfa | 2403 | } |
7b23213f | 2404 | else if (exp->X_op == O_constant) |
49864cfa | 2405 | { |
355afbcd | 2406 | i.types[this_operand] |= SMALLEST_DISP_TYPE (exp->X_add_number); |
49864cfa KR |
2407 | } |
2408 | else if (exp_seg == text_section | |
2409 | || exp_seg == data_section | |
2410 | || exp_seg == bss_section | |
2411 | || exp_seg == undefined_section) | |
2412 | { | |
355afbcd | 2413 | i.types[this_operand] |= Disp32; |
49864cfa KR |
2414 | } |
2415 | else | |
2416 | { | |
7b23213f | 2417 | #ifndef OBJ_AOUT |
49864cfa KR |
2418 | i.types[this_operand] |= Disp32; |
2419 | #else | |
355afbcd | 2420 | goto seg_unimplemented; |
49864cfa | 2421 | #endif |
355afbcd KR |
2422 | } |
2423 | } | |
2424 | ||
2425 | /* Make sure the memory operand we've been dealt is valid. */ | |
2426 | if (i.base_reg && i.index_reg && | |
2427 | !(i.base_reg->reg_type & i.index_reg->reg_type & Reg)) | |
2428 | { | |
2429 | as_bad ("register size mismatch in (base,index,scale) expression"); | |
2430 | return 0; | |
2431 | } | |
2432 | /* | |
49864cfa KR |
2433 | * special case for (%dx) while doing input/output op |
2434 | */ | |
355afbcd KR |
2435 | if ((i.base_reg && |
2436 | (i.base_reg->reg_type == (Reg16 | InOutPortReg)) && | |
2437 | (i.index_reg == 0))) | |
49864cfa KR |
2438 | { |
2439 | i.types[this_operand] |= InOutPortReg; | |
2440 | return 1; | |
2441 | } | |
355afbcd KR |
2442 | if ((i.base_reg && (i.base_reg->reg_type & Reg32) == 0) || |
2443 | (i.index_reg && (i.index_reg->reg_type & Reg32) == 0)) | |
2444 | { | |
2445 | as_bad ("base/index register must be 32 bit register"); | |
2446 | return 0; | |
2447 | } | |
2448 | if (i.index_reg && i.index_reg == esp) | |
2449 | { | |
2450 | as_bad ("%s may not be used as an index register", esp->reg_name); | |
2451 | return 0; | |
fecd2382 | 2452 | } |
355afbcd KR |
2453 | } |
2454 | else | |
2455 | { /* it's not a memory operand; argh! */ | |
2456 | as_bad ("invalid char %s begining %s operand '%s'", | |
2457 | output_invalid (*op_string), ordinal_names[this_operand], | |
2458 | op_string); | |
2459 | return 0; | |
2460 | } | |
2461 | return 1; /* normal return */ | |
fecd2382 RP |
2462 | } |
2463 | \f | |
2464 | /* | |
2465 | * md_estimate_size_before_relax() | |
2466 | * | |
2467 | * Called just before relax(). | |
2468 | * Any symbol that is now undefined will not become defined. | |
2469 | * Return the correct fr_subtype in the frag. | |
2470 | * Return the initial "guess for fr_var" to caller. | |
2471 | * The guess for fr_var is ACTUALLY the growth beyond fr_fix. | |
2472 | * Whatever we do to grow fr_fix or fr_var contributes to our returned value. | |
2473 | * Although it may not be explicit in the frag, pretend fr_var starts with a | |
2474 | * 0 value. | |
2475 | */ | |
2476 | int | |
355afbcd KR |
2477 | md_estimate_size_before_relax (fragP, segment) |
2478 | register fragS *fragP; | |
2479 | register segT segment; | |
fecd2382 | 2480 | { |
355afbcd KR |
2481 | register unsigned char *opcode; |
2482 | register int old_fr_fix; | |
2483 | ||
2484 | old_fr_fix = fragP->fr_fix; | |
2485 | opcode = (unsigned char *) fragP->fr_opcode; | |
2486 | /* We've already got fragP->fr_subtype right; all we have to do is check | |
a39116f1 | 2487 | for un-relaxable symbols. */ |
355afbcd KR |
2488 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment) |
2489 | { | |
2490 | /* symbol is undefined in this segment */ | |
2491 | switch (opcode[0]) | |
2492 | { | |
2493 | case JUMP_PC_RELATIVE: /* make jmp (0xeb) a dword displacement jump */ | |
2494 | opcode[0] = 0xe9; /* dword disp jmp */ | |
2495 | fragP->fr_fix += 4; | |
2496 | fix_new (fragP, old_fr_fix, 4, | |
f0b37b4a KR |
2497 | fragP->fr_symbol, |
2498 | fragP->fr_offset, 1, | |
2499 | (GOT_symbol && /* Not quite right - we should switch on | |
2500 | presence of @PLT, but I cannot see how | |
2501 | to get to that from here. We should have | |
2502 | done this in md_assemble to really | |
2503 | get it right all of the time, but I | |
2504 | think it does not matter that much, as | |
2505 | this will be right most of the time. ERY*/ | |
2506 | S_GET_SEGMENT(fragP->fr_symbol) == undefined_section)? | |
2507 | BFD_RELOC_386_PLT32 : BFD_RELOC_32_PCREL); | |
355afbcd KR |
2508 | break; |
2509 | ||
2510 | default: | |
2511 | /* This changes the byte-displacement jump 0x7N --> | |
a39116f1 | 2512 | the dword-displacement jump 0x0f8N */ |
355afbcd KR |
2513 | opcode[1] = opcode[0] + 0x10; |
2514 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; /* two-byte escape */ | |
2515 | fragP->fr_fix += 1 + 4; /* we've added an opcode byte */ | |
2516 | fix_new (fragP, old_fr_fix + 1, 4, | |
2517 | fragP->fr_symbol, | |
f0b37b4a KR |
2518 | fragP->fr_offset, 1, |
2519 | (GOT_symbol && /* Not quite right - we should switch on | |
2520 | presence of @PLT, but I cannot see how | |
2521 | to get to that from here. ERY */ | |
2522 | S_GET_SEGMENT(fragP->fr_symbol) == undefined_section)? | |
2523 | BFD_RELOC_386_PLT32 : BFD_RELOC_32_PCREL); | |
355afbcd | 2524 | break; |
a39116f1 | 2525 | } |
355afbcd KR |
2526 | frag_wane (fragP); |
2527 | } | |
2528 | return (fragP->fr_var + fragP->fr_fix - old_fr_fix); | |
fecd2382 RP |
2529 | } /* md_estimate_size_before_relax() */ |
2530 | \f | |
2531 | /* | |
2532 | * md_convert_frag(); | |
2533 | * | |
2534 | * Called after relax() is finished. | |
2535 | * In: Address of frag. | |
2536 | * fr_type == rs_machine_dependent. | |
2537 | * fr_subtype is what the address relaxed to. | |
2538 | * | |
2539 | * Out: Any fixSs and constants are set up. | |
2540 | * Caller will turn frag into a ".space 0". | |
2541 | */ | |
49864cfa | 2542 | #ifndef BFD_ASSEMBLER |
fecd2382 | 2543 | void |
3ea36b53 | 2544 | md_convert_frag (headers, sec, fragP) |
355afbcd | 2545 | object_headers *headers; |
3ea36b53 | 2546 | segT sec; |
355afbcd | 2547 | register fragS *fragP; |
49864cfa KR |
2548 | #else |
2549 | void | |
2550 | md_convert_frag (abfd, sec, fragP) | |
2551 | bfd *abfd; | |
2552 | segT sec; | |
2553 | register fragS *fragP; | |
2554 | #endif | |
fecd2382 | 2555 | { |
355afbcd KR |
2556 | register unsigned char *opcode; |
2557 | unsigned char *where_to_put_displacement = NULL; | |
2558 | unsigned int target_address; | |
2559 | unsigned int opcode_address; | |
2560 | unsigned int extension = 0; | |
2561 | int displacement_from_opcode_start; | |
2562 | ||
2563 | opcode = (unsigned char *) fragP->fr_opcode; | |
2564 | ||
2565 | /* Address we want to reach in file space. */ | |
2566 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; | |
7b23213f KR |
2567 | #ifdef BFD_ASSEMBLER /* not needed otherwise? */ |
2568 | target_address += fragP->fr_symbol->sy_frag->fr_address; | |
2569 | #endif | |
355afbcd KR |
2570 | |
2571 | /* Address opcode resides at in file space. */ | |
2572 | opcode_address = fragP->fr_address + fragP->fr_fix; | |
2573 | ||
2574 | /* Displacement from opcode start to fill into instruction. */ | |
2575 | displacement_from_opcode_start = target_address - opcode_address; | |
2576 | ||
2577 | switch (fragP->fr_subtype) | |
2578 | { | |
2579 | case ENCODE_RELAX_STATE (COND_JUMP, BYTE): | |
a39116f1 | 2580 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BYTE): |
355afbcd KR |
2581 | /* don't have to change opcode */ |
2582 | extension = 1; /* 1 opcode + 1 displacement */ | |
2583 | where_to_put_displacement = &opcode[1]; | |
2584 | break; | |
2585 | ||
2586 | case ENCODE_RELAX_STATE (COND_JUMP, WORD): | |
2587 | opcode[1] = TWO_BYTE_OPCODE_ESCAPE; | |
2588 | opcode[2] = opcode[0] + 0x10; | |
2589 | opcode[0] = WORD_PREFIX_OPCODE; | |
2590 | extension = 4; /* 3 opcode + 2 displacement */ | |
2591 | where_to_put_displacement = &opcode[3]; | |
2592 | break; | |
2593 | ||
2594 | case ENCODE_RELAX_STATE (UNCOND_JUMP, WORD): | |
2595 | opcode[1] = 0xe9; | |
2596 | opcode[0] = WORD_PREFIX_OPCODE; | |
2597 | extension = 3; /* 2 opcode + 2 displacement */ | |
2598 | where_to_put_displacement = &opcode[2]; | |
2599 | break; | |
2600 | ||
2601 | case ENCODE_RELAX_STATE (COND_JUMP, DWORD): | |
2602 | opcode[1] = opcode[0] + 0x10; | |
2603 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
2604 | extension = 5; /* 2 opcode + 4 displacement */ | |
2605 | where_to_put_displacement = &opcode[2]; | |
2606 | break; | |
2607 | ||
2608 | case ENCODE_RELAX_STATE (UNCOND_JUMP, DWORD): | |
2609 | opcode[0] = 0xe9; | |
2610 | extension = 4; /* 1 opcode + 4 displacement */ | |
2611 | where_to_put_displacement = &opcode[1]; | |
2612 | break; | |
2613 | ||
2614 | default: | |
2615 | BAD_CASE (fragP->fr_subtype); | |
2616 | break; | |
2617 | } | |
2618 | /* now put displacement after opcode */ | |
2619 | md_number_to_chars ((char *) where_to_put_displacement, | |
ad660eb1 | 2620 | (valueT) (displacement_from_opcode_start - extension), |
355afbcd KR |
2621 | SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
2622 | fragP->fr_fix += extension; | |
fecd2382 | 2623 | } |
fecd2382 | 2624 | \f |
355afbcd | 2625 | |
fecd2382 | 2626 | int md_short_jump_size = 2; /* size of byte displacement jmp */ |
355afbcd | 2627 | int md_long_jump_size = 5; /* size of dword displacement jmp */ |
49864cfa | 2628 | const int md_reloc_size = 8; /* Size of relocation record */ |
fecd2382 | 2629 | |
355afbcd KR |
2630 | void |
2631 | md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol) | |
2632 | char *ptr; | |
025b0302 | 2633 | addressT from_addr, to_addr; |
355afbcd KR |
2634 | fragS *frag; |
2635 | symbolS *to_symbol; | |
fecd2382 | 2636 | { |
355afbcd KR |
2637 | long offset; |
2638 | ||
2639 | offset = to_addr - (from_addr + 2); | |
ad660eb1 ILT |
2640 | md_number_to_chars (ptr, (valueT) 0xeb, 1); /* opcode for byte-disp jump */ |
2641 | md_number_to_chars (ptr + 1, (valueT) offset, 1); | |
fecd2382 RP |
2642 | } |
2643 | ||
355afbcd KR |
2644 | void |
2645 | md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol) | |
2646 | char *ptr; | |
025b0302 | 2647 | addressT from_addr, to_addr; |
355afbcd KR |
2648 | fragS *frag; |
2649 | symbolS *to_symbol; | |
fecd2382 | 2650 | { |
355afbcd KR |
2651 | long offset; |
2652 | ||
ade614d5 | 2653 | if (flag_do_long_jump) |
355afbcd KR |
2654 | { |
2655 | offset = to_addr - S_GET_VALUE (to_symbol); | |
ad660eb1 ILT |
2656 | md_number_to_chars (ptr, (valueT) 0xe9, 1);/* opcode for long jmp */ |
2657 | md_number_to_chars (ptr + 1, (valueT) offset, 4); | |
355afbcd | 2658 | fix_new (frag, (ptr + 1) - frag->fr_literal, 4, |
7b23213f | 2659 | to_symbol, (offsetT) 0, 0, BFD_RELOC_32); |
355afbcd KR |
2660 | } |
2661 | else | |
2662 | { | |
2663 | offset = to_addr - (from_addr + 5); | |
ad660eb1 ILT |
2664 | md_number_to_chars (ptr, (valueT) 0xe9, 1); |
2665 | md_number_to_chars (ptr + 1, (valueT) offset, 4); | |
355afbcd | 2666 | } |
fecd2382 RP |
2667 | } |
2668 | \f | |
fecd2382 | 2669 | /* Apply a fixup (fixS) to segment data, once it has been determined |
355afbcd KR |
2670 | by our caller that we have all the info we need to fix it up. |
2671 | ||
fecd2382 RP |
2672 | On the 386, immediates, displacements, and data pointers are all in |
2673 | the same (little-endian) format, so we don't need to care about which | |
2674 | we are handling. */ | |
2675 | ||
3ea36b53 ILT |
2676 | int |
2677 | md_apply_fix3 (fixP, valp, seg) | |
2678 | fixS *fixP; /* The fix we're to put in. */ | |
2679 | valueT *valp; /* Pointer to the value of the bits. */ | |
2680 | segT seg; /* Segment fix is from. */ | |
fecd2382 | 2681 | { |
355afbcd | 2682 | register char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
3ea36b53 | 2683 | valueT value = *valp; |
355afbcd | 2684 | |
f3d817d8 | 2685 | #if defined (BFD_ASSEMBLER) && !defined (TE_Mach) |
7b23213f KR |
2686 | /* |
2687 | * This is a hack. There should be a better way to | |
2688 | * handle this. | |
2689 | */ | |
2690 | if (fixP->fx_r_type == BFD_RELOC_32_PCREL && fixP->fx_addsy) | |
2691 | { | |
0b476c53 | 2692 | #ifndef OBJ_AOUT |
590c50d8 ILT |
2693 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
2694 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
0b476c53 | 2695 | #endif |
590c50d8 ILT |
2696 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
2697 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
2698 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg | |
2699 | || (fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0)) | |
f3d817d8 DM |
2700 | { |
2701 | /* Yes, we add the values in twice. This is because | |
2702 | bfd_perform_relocation subtracts them out again. I think | |
2703 | bfd_perform_relocation is broken, but I don't dare change | |
2704 | it. FIXME. */ | |
2705 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
2706 | } | |
7b23213f | 2707 | #endif |
355afbcd | 2708 | } |
f0b37b4a KR |
2709 | |
2710 | /* Fix a few things - the dynamic linker expects certain values here, | |
2711 | and we must not dissappoint it. */ | |
590c50d8 ILT |
2712 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
2713 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
2714 | && fixP->fx_addsy) | |
f0b37b4a KR |
2715 | switch(fixP->fx_r_type) { |
2716 | case BFD_RELOC_386_PLT32: | |
2717 | /* Make the jump instruction point to the address of the operand. At | |
2718 | runtime we merely add the offset to the actual PLT entry. */ | |
2719 | value = 0xfffffffc; | |
2720 | break; | |
2721 | case BFD_RELOC_386_GOTPC: | |
2722 | /* | |
2723 | * This is tough to explain. We end up with this one if we have | |
2724 | * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal | |
2725 | * here is to obtain the absolute address of the GOT, and it is strongly | |
2726 | * preferable from a performance point of view to avoid using a runtime | |
2727 | * relocation for this. The actual sequence of instructions often look | |
2728 | * something like: | |
2729 | * | |
2730 | * call .L66 | |
2731 | * .L66: | |
2732 | * popl %ebx | |
2733 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
2734 | * | |
2735 | * The call and pop essentially return the absolute address of | |
2736 | * the label .L66 and store it in %ebx. The linker itself will | |
2737 | * ultimately change the first operand of the addl so that %ebx points to | |
2738 | * the GOT, but to keep things simple, the .o file must have this operand | |
2739 | * set so that it generates not the absolute address of .L66, but the | |
2740 | * absolute address of itself. This allows the linker itself simply | |
2741 | * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be | |
2742 | * added in, and the addend of the relocation is stored in the operand | |
2743 | * field for the instruction itself. | |
2744 | * | |
2745 | * Our job here is to fix the operand so that it would add the correct | |
2746 | * offset so that %ebx would point to itself. The thing that is tricky is | |
2747 | * that .-.L66 will point to the beginning of the instruction, so we need | |
2748 | * to further modify the operand so that it will point to itself. | |
2749 | * There are other cases where you have something like: | |
2750 | * | |
2751 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
2752 | * | |
2753 | * and here no correction would be required. Internally in the assembler | |
2754 | * we treat operands of this form as not being pcrel since the '.' is | |
2755 | * explicitly mentioned, and I wonder whether it would simplify matters | |
2756 | * to do it this way. Who knows. In earlier versions of the PIC patches, | |
2757 | * the pcrel_adjust field was used to store the correction, but since the | |
2758 | * expression is not pcrel, I felt it would be confusing to do it this way. | |
2759 | */ | |
c54c7aac | 2760 | value -= 1; |
f0b37b4a KR |
2761 | break; |
2762 | case BFD_RELOC_386_GOT32: | |
2763 | value = 0; /* Fully resolved at runtime. No addend. */ | |
c54c7aac | 2764 | break; |
f0b37b4a | 2765 | case BFD_RELOC_386_GOTOFF: |
c54c7aac KR |
2766 | break; |
2767 | ||
f0b37b4a KR |
2768 | default: |
2769 | break; | |
2770 | } | |
2771 | #endif | |
2772 | ||
f3d817d8 DM |
2773 | #endif |
2774 | md_number_to_chars (p, value, fixP->fx_size); | |
fecd2382 | 2775 | |
49864cfa KR |
2776 | return 1; |
2777 | } | |
49864cfa | 2778 | |
ad660eb1 ILT |
2779 | #if 0 |
2780 | /* This is never used. */ | |
355afbcd KR |
2781 | long /* Knows about the byte order in a word. */ |
2782 | md_chars_to_number (con, nbytes) | |
2783 | unsigned char con[]; /* Low order byte 1st. */ | |
2784 | int nbytes; /* Number of bytes in the input. */ | |
fecd2382 | 2785 | { |
355afbcd KR |
2786 | long retval; |
2787 | for (retval = 0, con += nbytes - 1; nbytes--; con--) | |
2788 | { | |
2789 | retval <<= BITS_PER_CHAR; | |
2790 | retval |= *con; | |
2791 | } | |
2792 | return retval; | |
fecd2382 | 2793 | } |
ad660eb1 | 2794 | #endif /* 0 */ |
fecd2382 | 2795 | \f |
355afbcd | 2796 | |
fecd2382 RP |
2797 | #define MAX_LITTLENUMS 6 |
2798 | ||
2799 | /* Turn the string pointed to by litP into a floating point constant of type | |
2800 | type, and emit the appropriate bytes. The number of LITTLENUMS emitted | |
3c8df4ba | 2801 | is stored in *sizeP . An error message is returned, or NULL on OK. */ |
fecd2382 | 2802 | char * |
355afbcd KR |
2803 | md_atof (type, litP, sizeP) |
2804 | char type; | |
2805 | char *litP; | |
2806 | int *sizeP; | |
fecd2382 | 2807 | { |
355afbcd KR |
2808 | int prec; |
2809 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
2810 | LITTLENUM_TYPE *wordP; | |
2811 | char *t; | |
2812 | ||
2813 | switch (type) | |
2814 | { | |
2815 | case 'f': | |
2816 | case 'F': | |
2817 | prec = 2; | |
2818 | break; | |
2819 | ||
2820 | case 'd': | |
2821 | case 'D': | |
2822 | prec = 4; | |
2823 | break; | |
2824 | ||
2825 | case 'x': | |
2826 | case 'X': | |
2827 | prec = 5; | |
2828 | break; | |
2829 | ||
2830 | default: | |
2831 | *sizeP = 0; | |
2832 | return "Bad call to md_atof ()"; | |
2833 | } | |
2834 | t = atof_ieee (input_line_pointer, type, words); | |
2835 | if (t) | |
2836 | input_line_pointer = t; | |
2837 | ||
2838 | *sizeP = prec * sizeof (LITTLENUM_TYPE); | |
3c8df4ba KR |
2839 | /* This loops outputs the LITTLENUMs in REVERSE order; in accord with |
2840 | the bigendian 386. */ | |
355afbcd KR |
2841 | for (wordP = words + prec - 1; prec--;) |
2842 | { | |
ad660eb1 | 2843 | md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE)); |
355afbcd KR |
2844 | litP += sizeof (LITTLENUM_TYPE); |
2845 | } | |
49864cfa | 2846 | return 0; |
fecd2382 RP |
2847 | } |
2848 | \f | |
2849 | char output_invalid_buf[8]; | |
2850 | ||
355afbcd KR |
2851 | static char * |
2852 | output_invalid (c) | |
2853 | char c; | |
fecd2382 | 2854 | { |
355afbcd KR |
2855 | if (isprint (c)) |
2856 | sprintf (output_invalid_buf, "'%c'", c); | |
2857 | else | |
2858 | sprintf (output_invalid_buf, "(0x%x)", (unsigned) c); | |
2859 | return output_invalid_buf; | |
fecd2382 RP |
2860 | } |
2861 | ||
7b23213f | 2862 | /* reg_string starts *before* REGISTER_PREFIX */ |
355afbcd KR |
2863 | static reg_entry * |
2864 | parse_register (reg_string) | |
3c8df4ba | 2865 | char *reg_string; |
fecd2382 | 2866 | { |
355afbcd KR |
2867 | register char *s = reg_string; |
2868 | register char *p; | |
2869 | char reg_name_given[MAX_REG_NAME_SIZE]; | |
2870 | ||
2871 | s++; /* skip REGISTER_PREFIX */ | |
2872 | for (p = reg_name_given; is_register_char (*s); p++, s++) | |
2873 | { | |
58d4951d | 2874 | *p = register_chars[(unsigned char) *s]; |
355afbcd KR |
2875 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) |
2876 | return (reg_entry *) 0; | |
2877 | } | |
2878 | *p = '\0'; | |
2879 | return (reg_entry *) hash_find (reg_hash, reg_name_given); | |
fecd2382 | 2880 | } |
f3d817d8 | 2881 | \f |
ade614d5 | 2882 | #ifdef OBJ_ELF |
3ea36b53 | 2883 | CONST char *md_shortopts = "kmVQ:"; |
ade614d5 KR |
2884 | #else |
2885 | CONST char *md_shortopts = "m"; | |
2886 | #endif | |
f3d817d8 DM |
2887 | struct option md_longopts[] = { |
2888 | {NULL, no_argument, NULL, 0} | |
2889 | }; | |
2890 | size_t md_longopts_size = sizeof(md_longopts); | |
fecd2382 | 2891 | |
f3d817d8 DM |
2892 | int |
2893 | md_parse_option (c, arg) | |
2894 | int c; | |
2895 | char *arg; | |
2896 | { | |
ade614d5 KR |
2897 | switch (c) |
2898 | { | |
2899 | case 'm': | |
2900 | flag_do_long_jump = 1; | |
2901 | break; | |
2902 | ||
590c50d8 | 2903 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
3ea36b53 ILT |
2904 | /* -k: Ignore for FreeBSD compatibility. */ |
2905 | case 'k': | |
2906 | break; | |
2907 | ||
ade614d5 KR |
2908 | /* -V: SVR4 argument to print version ID. */ |
2909 | case 'V': | |
2910 | print_version_id (); | |
2911 | break; | |
2912 | ||
2913 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section | |
2914 | should be emitted or not. FIXME: Not implemented. */ | |
2915 | case 'Q': | |
2916 | break; | |
2917 | #endif | |
2918 | ||
2919 | default: | |
2920 | return 0; | |
2921 | } | |
2922 | return 1; | |
f3d817d8 | 2923 | } |
fecd2382 | 2924 | |
f3d817d8 DM |
2925 | void |
2926 | md_show_usage (stream) | |
2927 | FILE *stream; | |
2928 | { | |
ade614d5 KR |
2929 | fprintf (stream, "\ |
2930 | -m do long jump\n"); | |
f3d817d8 | 2931 | } |
fecd2382 | 2932 | |
590c50d8 ILT |
2933 | #ifdef BFD_ASSEMBLER |
2934 | #ifdef OBJ_MAYBE_ELF | |
2935 | #ifdef OBJ_MAYBE_COFF | |
2936 | ||
2937 | /* Pick the target format to use. */ | |
2938 | ||
2939 | const char * | |
2940 | i386_target_format () | |
2941 | { | |
2942 | switch (OUTPUT_FLAVOR) | |
2943 | { | |
2944 | case bfd_target_coff_flavour: | |
2945 | return "coff-i386"; | |
2946 | case bfd_target_elf_flavour: | |
2947 | return "elf32-i386"; | |
2948 | default: | |
2949 | abort (); | |
2950 | return NULL; | |
2951 | } | |
2952 | } | |
2953 | ||
2954 | #endif /* OBJ_MAYBE_COFF */ | |
2955 | #endif /* OBJ_MAYBE_ELF */ | |
2956 | #endif /* BFD_ASSEMBLER */ | |
2957 | \f | |
fecd2382 RP |
2958 | /* ARGSUSED */ |
2959 | symbolS * | |
355afbcd KR |
2960 | md_undefined_symbol (name) |
2961 | char *name; | |
fecd2382 | 2962 | { |
f0b37b4a KR |
2963 | if (*name == '_' && *(name+1) == 'G' |
2964 | && strcmp(name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
2965 | { | |
2966 | if(!GOT_symbol) | |
2967 | { | |
2968 | if(symbol_find(name)) | |
2969 | as_bad("GOT already in symbol table"); | |
2970 | GOT_symbol = symbol_new (name, undefined_section, | |
2971 | (valueT) 0, &zero_address_frag); | |
2972 | }; | |
2973 | return GOT_symbol; | |
2974 | } | |
355afbcd | 2975 | return 0; |
fecd2382 RP |
2976 | } |
2977 | ||
fecd2382 | 2978 | /* Round up a section size to the appropriate boundary. */ |
3c8df4ba | 2979 | valueT |
355afbcd KR |
2980 | md_section_align (segment, size) |
2981 | segT segment; | |
3c8df4ba | 2982 | valueT size; |
fecd2382 | 2983 | { |
355afbcd | 2984 | return size; /* Byte alignment is fine */ |
fecd2382 RP |
2985 | } |
2986 | ||
7b23213f KR |
2987 | /* Exactly what point is a PC-relative offset relative TO? On the |
2988 | i386, they're relative to the address of the offset, plus its | |
2989 | size. (??? Is this right? FIXME-SOON!) */ | |
fecd2382 | 2990 | long |
355afbcd KR |
2991 | md_pcrel_from (fixP) |
2992 | fixS *fixP; | |
fecd2382 | 2993 | { |
355afbcd | 2994 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; |
fecd2382 RP |
2995 | } |
2996 | ||
49864cfa | 2997 | #ifndef I386COFF |
542e1629 | 2998 | |
49864cfa | 2999 | static void |
ad660eb1 ILT |
3000 | s_bss (ignore) |
3001 | int ignore; | |
542e1629 | 3002 | { |
49864cfa | 3003 | register int temp; |
542e1629 | 3004 | |
49864cfa | 3005 | temp = get_absolute_expression (); |
49864cfa | 3006 | subseg_set (bss_section, (subsegT) temp); |
49864cfa KR |
3007 | demand_empty_rest_of_line (); |
3008 | } | |
542e1629 | 3009 | |
49864cfa | 3010 | #endif |
355afbcd | 3011 | |
542e1629 | 3012 | |
49864cfa | 3013 | #ifdef BFD_ASSEMBLER |
c54c7aac KR |
3014 | |
3015 | void | |
3016 | i386_validate_fix (fixp) | |
3017 | fixS *fixp; | |
3018 | { | |
3019 | if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol) | |
3020 | { | |
3021 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
3022 | fixp->fx_subsy = 0; | |
3023 | } | |
3024 | } | |
3025 | ||
f0b37b4a KR |
3026 | #define F(SZ,PCREL) (((SZ) << 1) + (PCREL)) |
3027 | #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break | |
542e1629 | 3028 | |
49864cfa KR |
3029 | arelent * |
3030 | tc_gen_reloc (section, fixp) | |
3031 | asection *section; | |
3032 | fixS *fixp; | |
542e1629 | 3033 | { |
ad660eb1 | 3034 | arelent *rel; |
49864cfa | 3035 | bfd_reloc_code_real_type code; |
542e1629 | 3036 | |
f0b37b4a | 3037 | switch(fixp->fx_r_type) |
49864cfa | 3038 | { |
f0b37b4a KR |
3039 | case BFD_RELOC_386_PLT32: |
3040 | case BFD_RELOC_386_GOT32: | |
3041 | case BFD_RELOC_386_GOTOFF: | |
3042 | case BFD_RELOC_386_GOTPC: | |
3043 | code = fixp->fx_r_type; | |
3044 | break; | |
3045 | default: | |
3046 | switch (F (fixp->fx_size, fixp->fx_pcrel)) | |
3047 | { | |
f0b37b4a KR |
3048 | MAP (1, 0, BFD_RELOC_8); |
3049 | MAP (2, 0, BFD_RELOC_16); | |
f0b37b4a | 3050 | MAP (4, 0, BFD_RELOC_32); |
f0b37b4a KR |
3051 | MAP (1, 1, BFD_RELOC_8_PCREL); |
3052 | MAP (2, 1, BFD_RELOC_16_PCREL); | |
f0b37b4a KR |
3053 | MAP (4, 1, BFD_RELOC_32_PCREL); |
3054 | default: | |
3055 | as_bad ("Can not do %d byte %srelocation", fixp->fx_size, | |
3ea36b53 | 3056 | fixp->fx_pcrel ? "pc-relative " : ""); |
f0b37b4a | 3057 | } |
49864cfa | 3058 | } |
3c8df4ba KR |
3059 | #undef MAP |
3060 | #undef F | |
542e1629 | 3061 | |
f0b37b4a KR |
3062 | if (code == BFD_RELOC_32 |
3063 | && GOT_symbol | |
3064 | && fixp->fx_addsy == GOT_symbol) | |
3065 | code = BFD_RELOC_386_GOTPC; | |
3066 | ||
590c50d8 | 3067 | rel = (arelent *) xmalloc (sizeof (arelent)); |
ad660eb1 ILT |
3068 | rel->sym_ptr_ptr = &fixp->fx_addsy->bsym; |
3069 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
49864cfa | 3070 | if (fixp->fx_pcrel) |
ad660eb1 | 3071 | rel->addend = fixp->fx_addnumber; |
49864cfa | 3072 | else |
ad660eb1 | 3073 | rel->addend = 0; |
355afbcd | 3074 | |
ad660eb1 | 3075 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
e592f0e6 | 3076 | if (rel->howto == NULL) |
ad660eb1 | 3077 | { |
e592f0e6 ILT |
3078 | as_bad_where (fixp->fx_file, fixp->fx_line, |
3079 | "Cannot represent relocation type %s", | |
3080 | bfd_get_reloc_code_name (code)); | |
3081 | /* Set howto to a garbage value so that we can keep going. */ | |
3082 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
3083 | assert (rel->howto != NULL); | |
ad660eb1 | 3084 | } |
49864cfa | 3085 | |
ad660eb1 | 3086 | return rel; |
49864cfa KR |
3087 | } |
3088 | ||
3089 | #else /* ! BFD_ASSEMBLER */ | |
3090 | ||
3091 | #if (defined(OBJ_AOUT) | defined(OBJ_BOUT)) | |
3092 | void | |
3093 | tc_aout_fix_to_chars (where, fixP, segment_address_in_file) | |
3094 | char *where; | |
3095 | fixS *fixP; | |
3096 | relax_addressT segment_address_in_file; | |
4b77b129 | 3097 | { |
49864cfa KR |
3098 | /* |
3099 | * In: length of relocation (or of address) in chars: 1, 2 or 4. | |
3100 | * Out: GNU LD relocation length code: 0, 1, or 2. | |
3101 | */ | |
4b77b129 | 3102 | |
3c8df4ba | 3103 | static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2}; |
49864cfa KR |
3104 | long r_symbolnum; |
3105 | ||
3106 | know (fixP->fx_addsy != NULL); | |
3107 | ||
3108 | md_number_to_chars (where, | |
ad660eb1 ILT |
3109 | (valueT) (fixP->fx_frag->fr_address |
3110 | + fixP->fx_where - segment_address_in_file), | |
49864cfa KR |
3111 | 4); |
3112 | ||
3113 | r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy) | |
3114 | ? S_GET_TYPE (fixP->fx_addsy) | |
3115 | : fixP->fx_addsy->sy_number); | |
3116 | ||
3117 | where[6] = (r_symbolnum >> 16) & 0x0ff; | |
3118 | where[5] = (r_symbolnum >> 8) & 0x0ff; | |
3119 | where[4] = r_symbolnum & 0x0ff; | |
3120 | where[7] = ((((!S_IS_DEFINED (fixP->fx_addsy)) << 3) & 0x08) | |
3121 | | ((nbytes_r_length[fixP->fx_size] << 1) & 0x06) | |
3122 | | (((fixP->fx_pcrel << 0) & 0x01) & 0x0f)); | |
4b77b129 | 3123 | } |
355afbcd | 3124 | |
49864cfa | 3125 | #endif /* OBJ_AOUT or OBJ_BOUT */ |
4b77b129 | 3126 | |
49864cfa | 3127 | #if defined (I386COFF) |
4b77b129 | 3128 | |
355afbcd KR |
3129 | short |
3130 | tc_coff_fix2rtype (fixP) | |
3131 | fixS *fixP; | |
4b77b129 | 3132 | { |
3ea36b53 ILT |
3133 | if (fixP->fx_r_type == R_IMAGEBASE) |
3134 | return R_IMAGEBASE; | |
3135 | ||
355afbcd KR |
3136 | return (fixP->fx_pcrel ? |
3137 | (fixP->fx_size == 1 ? R_PCRBYTE : | |
3138 | fixP->fx_size == 2 ? R_PCRWORD : | |
3139 | R_PCRLONG) : | |
3140 | (fixP->fx_size == 1 ? R_RELBYTE : | |
3141 | fixP->fx_size == 2 ? R_RELWORD : | |
3142 | R_DIR32)); | |
4b77b129 ILT |
3143 | } |
3144 | ||
49864cfa KR |
3145 | int |
3146 | tc_coff_sizemachdep (frag) | |
3147 | fragS *frag; | |
3148 | { | |
3149 | if (frag->fr_next) | |
3150 | return (frag->fr_next->fr_address - frag->fr_address); | |
3151 | else | |
3152 | return 0; | |
3153 | } | |
3154 | ||
3155 | #endif /* I386COFF */ | |
3156 | ||
3157 | #endif /* BFD_ASSEMBLER? */ | |
3ea36b53 | 3158 | \f |
fecd2382 | 3159 | /* end of tc-i386.c */ |