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b534c6d3 | 1 | /* tc-i386.c -- Assemble code for the Intel 80386 |
82704155 | 2 | Copyright (C) 1989-2019 Free Software Foundation, Inc. |
252b5132 RH |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
19 | 02110-1301, USA. */ | |
252b5132 | 20 | |
47926f60 KH |
21 | /* Intel 80386 machine specific gas. |
22 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 23 | x86_64 support by Jan Hubicka (jh@suse.cz) |
0f10071e | 24 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
47926f60 KH |
25 | Bugs & suggestions are completely welcome. This is free software. |
26 | Please help us make it better. */ | |
252b5132 | 27 | |
252b5132 | 28 | #include "as.h" |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | #include "subsegs.h" |
316e2c05 | 31 | #include "dwarf2dbg.h" |
54cfded0 | 32 | #include "dw2gencfi.h" |
d2b2c203 | 33 | #include "elf/x86-64.h" |
40fb9820 | 34 | #include "opcodes/i386-init.h" |
252b5132 | 35 | |
41fd2579 L |
36 | #ifdef HAVE_LIMITS_H |
37 | #include <limits.h> | |
38 | #else | |
39 | #ifdef HAVE_SYS_PARAM_H | |
40 | #include <sys/param.h> | |
41 | #endif | |
42 | #ifndef INT_MAX | |
43 | #define INT_MAX (int) (((unsigned) (-1)) >> 1) | |
44 | #endif | |
45 | #endif | |
46 | ||
252b5132 RH |
47 | #ifndef REGISTER_WARNINGS |
48 | #define REGISTER_WARNINGS 1 | |
49 | #endif | |
50 | ||
c3332e24 | 51 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 52 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
53 | #endif |
54 | ||
29b0f896 AM |
55 | #ifndef DEFAULT_ARCH |
56 | #define DEFAULT_ARCH "i386" | |
246fcdee | 57 | #endif |
252b5132 | 58 | |
edde18a5 AM |
59 | #ifndef INLINE |
60 | #if __GNUC__ >= 2 | |
61 | #define INLINE __inline__ | |
62 | #else | |
63 | #define INLINE | |
64 | #endif | |
65 | #endif | |
66 | ||
6305a203 L |
67 | /* Prefixes will be emitted in the order defined below. |
68 | WAIT_PREFIX must be the first prefix since FWAIT is really is an | |
69 | instruction, and so must come before any prefixes. | |
70 | The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, | |
42164a71 | 71 | REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */ |
6305a203 L |
72 | #define WAIT_PREFIX 0 |
73 | #define SEG_PREFIX 1 | |
74 | #define ADDR_PREFIX 2 | |
75 | #define DATA_PREFIX 3 | |
c32fa91d | 76 | #define REP_PREFIX 4 |
42164a71 | 77 | #define HLE_PREFIX REP_PREFIX |
7e8b059b | 78 | #define BND_PREFIX REP_PREFIX |
c32fa91d | 79 | #define LOCK_PREFIX 5 |
4e9ac44a L |
80 | #define REX_PREFIX 6 /* must come last. */ |
81 | #define MAX_PREFIXES 7 /* max prefixes per opcode */ | |
6305a203 L |
82 | |
83 | /* we define the syntax here (modulo base,index,scale syntax) */ | |
84 | #define REGISTER_PREFIX '%' | |
85 | #define IMMEDIATE_PREFIX '$' | |
86 | #define ABSOLUTE_PREFIX '*' | |
87 | ||
88 | /* these are the instruction mnemonic suffixes in AT&T syntax or | |
89 | memory operand size in Intel syntax. */ | |
90 | #define WORD_MNEM_SUFFIX 'w' | |
91 | #define BYTE_MNEM_SUFFIX 'b' | |
92 | #define SHORT_MNEM_SUFFIX 's' | |
93 | #define LONG_MNEM_SUFFIX 'l' | |
94 | #define QWORD_MNEM_SUFFIX 'q' | |
6305a203 L |
95 | /* Intel Syntax. Use a non-ascii letter since since it never appears |
96 | in instructions. */ | |
97 | #define LONG_DOUBLE_MNEM_SUFFIX '\1' | |
98 | ||
99 | #define END_OF_INSN '\0' | |
100 | ||
79dec6b7 JB |
101 | /* This matches the C -> StaticRounding alias in the opcode table. */ |
102 | #define commutative staticrounding | |
103 | ||
6305a203 L |
104 | /* |
105 | 'templates' is for grouping together 'template' structures for opcodes | |
106 | of the same name. This is only used for storing the insns in the grand | |
107 | ole hash table of insns. | |
108 | The templates themselves start at START and range up to (but not including) | |
109 | END. | |
110 | */ | |
111 | typedef struct | |
112 | { | |
d3ce72d0 NC |
113 | const insn_template *start; |
114 | const insn_template *end; | |
6305a203 L |
115 | } |
116 | templates; | |
117 | ||
118 | /* 386 operand encoding bytes: see 386 book for details of this. */ | |
119 | typedef struct | |
120 | { | |
121 | unsigned int regmem; /* codes register or memory operand */ | |
122 | unsigned int reg; /* codes register operand (or extended opcode) */ | |
123 | unsigned int mode; /* how to interpret regmem & reg */ | |
124 | } | |
125 | modrm_byte; | |
126 | ||
127 | /* x86-64 extension prefix. */ | |
128 | typedef int rex_byte; | |
129 | ||
6305a203 L |
130 | /* 386 opcode byte to code indirect addressing. */ |
131 | typedef struct | |
132 | { | |
133 | unsigned base; | |
134 | unsigned index; | |
135 | unsigned scale; | |
136 | } | |
137 | sib_byte; | |
138 | ||
6305a203 L |
139 | /* x86 arch names, types and features */ |
140 | typedef struct | |
141 | { | |
142 | const char *name; /* arch name */ | |
8a2c8fef | 143 | unsigned int len; /* arch string length */ |
6305a203 L |
144 | enum processor_type type; /* arch type */ |
145 | i386_cpu_flags flags; /* cpu feature flags */ | |
8a2c8fef | 146 | unsigned int skip; /* show_arch should skip this. */ |
6305a203 L |
147 | } |
148 | arch_entry; | |
149 | ||
293f5f65 L |
150 | /* Used to turn off indicated flags. */ |
151 | typedef struct | |
152 | { | |
153 | const char *name; /* arch name */ | |
154 | unsigned int len; /* arch string length */ | |
155 | i386_cpu_flags flags; /* cpu feature flags */ | |
156 | } | |
157 | noarch_entry; | |
158 | ||
78f12dd3 | 159 | static void update_code_flag (int, int); |
e3bb37b5 L |
160 | static void set_code_flag (int); |
161 | static void set_16bit_gcc_code_flag (int); | |
162 | static void set_intel_syntax (int); | |
1efbbeb4 | 163 | static void set_intel_mnemonic (int); |
db51cc60 | 164 | static void set_allow_index_reg (int); |
7bab8ab5 | 165 | static void set_check (int); |
e3bb37b5 | 166 | static void set_cpu_arch (int); |
6482c264 | 167 | #ifdef TE_PE |
e3bb37b5 | 168 | static void pe_directive_secrel (int); |
6482c264 | 169 | #endif |
e3bb37b5 L |
170 | static void signed_cons (int); |
171 | static char *output_invalid (int c); | |
ee86248c JB |
172 | static int i386_finalize_immediate (segT, expressionS *, i386_operand_type, |
173 | const char *); | |
174 | static int i386_finalize_displacement (segT, expressionS *, i386_operand_type, | |
175 | const char *); | |
a7619375 | 176 | static int i386_att_operand (char *); |
e3bb37b5 | 177 | static int i386_intel_operand (char *, int); |
ee86248c JB |
178 | static int i386_intel_simplify (expressionS *); |
179 | static int i386_intel_parse_name (const char *, expressionS *); | |
e3bb37b5 L |
180 | static const reg_entry *parse_register (char *, char **); |
181 | static char *parse_insn (char *, char *); | |
182 | static char *parse_operands (char *, const char *); | |
183 | static void swap_operands (void); | |
4d456e3d | 184 | static void swap_2_operands (int, int); |
e3bb37b5 L |
185 | static void optimize_imm (void); |
186 | static void optimize_disp (void); | |
83b16ac6 | 187 | static const insn_template *match_template (char); |
e3bb37b5 L |
188 | static int check_string (void); |
189 | static int process_suffix (void); | |
190 | static int check_byte_reg (void); | |
191 | static int check_long_reg (void); | |
192 | static int check_qword_reg (void); | |
193 | static int check_word_reg (void); | |
194 | static int finalize_imm (void); | |
195 | static int process_operands (void); | |
196 | static const seg_entry *build_modrm_byte (void); | |
197 | static void output_insn (void); | |
198 | static void output_imm (fragS *, offsetT); | |
199 | static void output_disp (fragS *, offsetT); | |
29b0f896 | 200 | #ifndef I386COFF |
e3bb37b5 | 201 | static void s_bss (int); |
252b5132 | 202 | #endif |
17d4e2a2 L |
203 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
204 | static void handle_large_common (int small ATTRIBUTE_UNUSED); | |
b4a3a7b4 L |
205 | |
206 | /* GNU_PROPERTY_X86_ISA_1_USED. */ | |
207 | static unsigned int x86_isa_1_used; | |
208 | /* GNU_PROPERTY_X86_FEATURE_2_USED. */ | |
209 | static unsigned int x86_feature_2_used; | |
210 | /* Generate x86 used ISA and feature properties. */ | |
211 | static unsigned int x86_used_note = DEFAULT_X86_USED_NOTE; | |
17d4e2a2 | 212 | #endif |
252b5132 | 213 | |
a847613f | 214 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 215 | |
43234a1e L |
216 | /* This struct describes rounding control and SAE in the instruction. */ |
217 | struct RC_Operation | |
218 | { | |
219 | enum rc_type | |
220 | { | |
221 | rne = 0, | |
222 | rd, | |
223 | ru, | |
224 | rz, | |
225 | saeonly | |
226 | } type; | |
227 | int operand; | |
228 | }; | |
229 | ||
230 | static struct RC_Operation rc_op; | |
231 | ||
232 | /* The struct describes masking, applied to OPERAND in the instruction. | |
233 | MASK is a pointer to the corresponding mask register. ZEROING tells | |
234 | whether merging or zeroing mask is used. */ | |
235 | struct Mask_Operation | |
236 | { | |
237 | const reg_entry *mask; | |
238 | unsigned int zeroing; | |
239 | /* The operand where this operation is associated. */ | |
240 | int operand; | |
241 | }; | |
242 | ||
243 | static struct Mask_Operation mask_op; | |
244 | ||
245 | /* The struct describes broadcasting, applied to OPERAND. FACTOR is | |
246 | broadcast factor. */ | |
247 | struct Broadcast_Operation | |
248 | { | |
8e6e0792 | 249 | /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */ |
43234a1e L |
250 | int type; |
251 | ||
252 | /* Index of broadcasted operand. */ | |
253 | int operand; | |
4a1b91ea L |
254 | |
255 | /* Number of bytes to broadcast. */ | |
256 | int bytes; | |
43234a1e L |
257 | }; |
258 | ||
259 | static struct Broadcast_Operation broadcast_op; | |
260 | ||
c0f3af97 L |
261 | /* VEX prefix. */ |
262 | typedef struct | |
263 | { | |
43234a1e L |
264 | /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */ |
265 | unsigned char bytes[4]; | |
c0f3af97 L |
266 | unsigned int length; |
267 | /* Destination or source register specifier. */ | |
268 | const reg_entry *register_specifier; | |
269 | } vex_prefix; | |
270 | ||
252b5132 | 271 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 272 | i386_insn. */ |
252b5132 | 273 | |
520dc8e8 AM |
274 | union i386_op |
275 | { | |
276 | expressionS *disps; | |
277 | expressionS *imms; | |
278 | const reg_entry *regs; | |
279 | }; | |
280 | ||
a65babc9 L |
281 | enum i386_error |
282 | { | |
86e026a4 | 283 | operand_size_mismatch, |
a65babc9 L |
284 | operand_type_mismatch, |
285 | register_type_mismatch, | |
286 | number_of_operands_mismatch, | |
287 | invalid_instruction_suffix, | |
288 | bad_imm4, | |
a65babc9 L |
289 | unsupported_with_intel_mnemonic, |
290 | unsupported_syntax, | |
6c30d220 L |
291 | unsupported, |
292 | invalid_vsib_address, | |
7bab8ab5 | 293 | invalid_vector_register_set, |
43234a1e L |
294 | unsupported_vector_index_register, |
295 | unsupported_broadcast, | |
43234a1e L |
296 | broadcast_needed, |
297 | unsupported_masking, | |
298 | mask_not_on_destination, | |
299 | no_default_mask, | |
300 | unsupported_rc_sae, | |
301 | rc_sae_operand_not_last_imm, | |
302 | invalid_register_operand, | |
a65babc9 L |
303 | }; |
304 | ||
252b5132 RH |
305 | struct _i386_insn |
306 | { | |
47926f60 | 307 | /* TM holds the template for the insn were currently assembling. */ |
d3ce72d0 | 308 | insn_template tm; |
252b5132 | 309 | |
7d5e4556 L |
310 | /* SUFFIX holds the instruction size suffix for byte, word, dword |
311 | or qword, if given. */ | |
252b5132 RH |
312 | char suffix; |
313 | ||
47926f60 | 314 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
315 | unsigned int operands; |
316 | ||
317 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
318 | of given register, displacement, memory operands and immediate | |
47926f60 | 319 | operands. */ |
252b5132 RH |
320 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
321 | ||
322 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 323 | use OP[i] for the corresponding operand. */ |
40fb9820 | 324 | i386_operand_type types[MAX_OPERANDS]; |
252b5132 | 325 | |
520dc8e8 AM |
326 | /* Displacement expression, immediate expression, or register for each |
327 | operand. */ | |
328 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 329 | |
3e73aa7c JH |
330 | /* Flags for operands. */ |
331 | unsigned int flags[MAX_OPERANDS]; | |
332 | #define Operand_PCrel 1 | |
c48dadc9 | 333 | #define Operand_Mem 2 |
3e73aa7c | 334 | |
252b5132 | 335 | /* Relocation type for operand */ |
f86103b7 | 336 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
252b5132 | 337 | |
252b5132 RH |
338 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
339 | the base index byte below. */ | |
340 | const reg_entry *base_reg; | |
341 | const reg_entry *index_reg; | |
342 | unsigned int log2_scale_factor; | |
343 | ||
344 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 345 | explicit segment overrides are given. */ |
ce8a8b2f | 346 | const seg_entry *seg[2]; |
252b5132 | 347 | |
8325cc63 JB |
348 | /* Copied first memory operand string, for re-checking. */ |
349 | char *memop1_string; | |
350 | ||
252b5132 RH |
351 | /* PREFIX holds all the given prefix opcodes (usually null). |
352 | PREFIXES is the number of prefix opcodes. */ | |
353 | unsigned int prefixes; | |
354 | unsigned char prefix[MAX_PREFIXES]; | |
355 | ||
b4a3a7b4 L |
356 | /* Has MMX register operands. */ |
357 | bfd_boolean has_regmmx; | |
358 | ||
359 | /* Has XMM register operands. */ | |
360 | bfd_boolean has_regxmm; | |
361 | ||
362 | /* Has YMM register operands. */ | |
363 | bfd_boolean has_regymm; | |
364 | ||
365 | /* Has ZMM register operands. */ | |
366 | bfd_boolean has_regzmm; | |
367 | ||
252b5132 | 368 | /* RM and SIB are the modrm byte and the sib byte where the |
c1e679ec | 369 | addressing modes of this insn are encoded. */ |
252b5132 | 370 | modrm_byte rm; |
3e73aa7c | 371 | rex_byte rex; |
43234a1e | 372 | rex_byte vrex; |
252b5132 | 373 | sib_byte sib; |
c0f3af97 | 374 | vex_prefix vex; |
b6169b20 | 375 | |
43234a1e L |
376 | /* Masking attributes. */ |
377 | struct Mask_Operation *mask; | |
378 | ||
379 | /* Rounding control and SAE attributes. */ | |
380 | struct RC_Operation *rounding; | |
381 | ||
382 | /* Broadcasting attributes. */ | |
383 | struct Broadcast_Operation *broadcast; | |
384 | ||
385 | /* Compressed disp8*N attribute. */ | |
386 | unsigned int memshift; | |
387 | ||
86fa6981 L |
388 | /* Prefer load or store in encoding. */ |
389 | enum | |
390 | { | |
391 | dir_encoding_default = 0, | |
392 | dir_encoding_load, | |
64c49ab3 JB |
393 | dir_encoding_store, |
394 | dir_encoding_swap | |
86fa6981 | 395 | } dir_encoding; |
891edac4 | 396 | |
a501d77e L |
397 | /* Prefer 8bit or 32bit displacement in encoding. */ |
398 | enum | |
399 | { | |
400 | disp_encoding_default = 0, | |
401 | disp_encoding_8bit, | |
402 | disp_encoding_32bit | |
403 | } disp_encoding; | |
f8a5c266 | 404 | |
6b6b6807 L |
405 | /* Prefer the REX byte in encoding. */ |
406 | bfd_boolean rex_encoding; | |
407 | ||
b6f8c7c4 L |
408 | /* Disable instruction size optimization. */ |
409 | bfd_boolean no_optimize; | |
410 | ||
86fa6981 L |
411 | /* How to encode vector instructions. */ |
412 | enum | |
413 | { | |
414 | vex_encoding_default = 0, | |
415 | vex_encoding_vex2, | |
416 | vex_encoding_vex3, | |
417 | vex_encoding_evex | |
418 | } vec_encoding; | |
419 | ||
d5de92cf L |
420 | /* REP prefix. */ |
421 | const char *rep_prefix; | |
422 | ||
165de32a L |
423 | /* HLE prefix. */ |
424 | const char *hle_prefix; | |
42164a71 | 425 | |
7e8b059b L |
426 | /* Have BND prefix. */ |
427 | const char *bnd_prefix; | |
428 | ||
04ef582a L |
429 | /* Have NOTRACK prefix. */ |
430 | const char *notrack_prefix; | |
431 | ||
891edac4 | 432 | /* Error message. */ |
a65babc9 | 433 | enum i386_error error; |
252b5132 RH |
434 | }; |
435 | ||
436 | typedef struct _i386_insn i386_insn; | |
437 | ||
43234a1e L |
438 | /* Link RC type with corresponding string, that'll be looked for in |
439 | asm. */ | |
440 | struct RC_name | |
441 | { | |
442 | enum rc_type type; | |
443 | const char *name; | |
444 | unsigned int len; | |
445 | }; | |
446 | ||
447 | static const struct RC_name RC_NamesTable[] = | |
448 | { | |
449 | { rne, STRING_COMMA_LEN ("rn-sae") }, | |
450 | { rd, STRING_COMMA_LEN ("rd-sae") }, | |
451 | { ru, STRING_COMMA_LEN ("ru-sae") }, | |
452 | { rz, STRING_COMMA_LEN ("rz-sae") }, | |
453 | { saeonly, STRING_COMMA_LEN ("sae") }, | |
454 | }; | |
455 | ||
252b5132 RH |
456 | /* List of chars besides those in app.c:symbol_chars that can start an |
457 | operand. Used to prevent the scrubber eating vital white-space. */ | |
86fa6981 | 458 | const char extra_symbol_chars[] = "*%-([{}" |
252b5132 | 459 | #ifdef LEX_AT |
32137342 NC |
460 | "@" |
461 | #endif | |
462 | #ifdef LEX_QM | |
463 | "?" | |
252b5132 | 464 | #endif |
32137342 | 465 | ; |
252b5132 | 466 | |
29b0f896 AM |
467 | #if (defined (TE_I386AIX) \ |
468 | || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ | |
3896cfd5 | 469 | && !defined (TE_GNU) \ |
29b0f896 | 470 | && !defined (TE_LINUX) \ |
8d63c93e | 471 | && !defined (TE_NACL) \ |
29b0f896 | 472 | && !defined (TE_FreeBSD) \ |
5b806d27 | 473 | && !defined (TE_DragonFly) \ |
29b0f896 | 474 | && !defined (TE_NetBSD))) |
252b5132 | 475 | /* This array holds the chars that always start a comment. If the |
b3b91714 AM |
476 | pre-processor is disabled, these aren't very useful. The option |
477 | --divide will remove '/' from this list. */ | |
478 | const char *i386_comment_chars = "#/"; | |
479 | #define SVR4_COMMENT_CHARS 1 | |
252b5132 | 480 | #define PREFIX_SEPARATOR '\\' |
252b5132 | 481 | |
b3b91714 AM |
482 | #else |
483 | const char *i386_comment_chars = "#"; | |
484 | #define PREFIX_SEPARATOR '/' | |
485 | #endif | |
486 | ||
252b5132 RH |
487 | /* This array holds the chars that only start a comment at the beginning of |
488 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
489 | .line and .file directives will appear in the pre-processed output. |
490 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 491 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
492 | #NO_APP at the beginning of its output. |
493 | Also note that comments started like this one will always work if | |
252b5132 | 494 | '/' isn't otherwise defined. */ |
b3b91714 | 495 | const char line_comment_chars[] = "#/"; |
252b5132 | 496 | |
63a0b638 | 497 | const char line_separator_chars[] = ";"; |
252b5132 | 498 | |
ce8a8b2f AM |
499 | /* Chars that can be used to separate mant from exp in floating point |
500 | nums. */ | |
252b5132 RH |
501 | const char EXP_CHARS[] = "eE"; |
502 | ||
ce8a8b2f AM |
503 | /* Chars that mean this number is a floating point constant |
504 | As in 0f12.456 | |
505 | or 0d1.2345e12. */ | |
252b5132 RH |
506 | const char FLT_CHARS[] = "fFdDxX"; |
507 | ||
ce8a8b2f | 508 | /* Tables for lexical analysis. */ |
252b5132 RH |
509 | static char mnemonic_chars[256]; |
510 | static char register_chars[256]; | |
511 | static char operand_chars[256]; | |
512 | static char identifier_chars[256]; | |
513 | static char digit_chars[256]; | |
514 | ||
ce8a8b2f | 515 | /* Lexical macros. */ |
252b5132 RH |
516 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
517 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
518 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
519 | #define is_space_char(x) ((x) == ' ') | |
520 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
521 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
522 | ||
0234cb7c | 523 | /* All non-digit non-letter characters that may occur in an operand. */ |
252b5132 RH |
524 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
525 | ||
526 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
527 | effect this we maintain a stack of saved characters that we've smashed | |
528 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 529 | assembler instruction). */ |
252b5132 | 530 | static char save_stack[32]; |
ce8a8b2f | 531 | static char *save_stack_p; |
252b5132 RH |
532 | #define END_STRING_AND_SAVE(s) \ |
533 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
534 | #define RESTORE_END_STRING(s) \ | |
535 | do { *(s) = *--save_stack_p; } while (0) | |
536 | ||
47926f60 | 537 | /* The instruction we're assembling. */ |
252b5132 RH |
538 | static i386_insn i; |
539 | ||
540 | /* Possible templates for current insn. */ | |
541 | static const templates *current_templates; | |
542 | ||
31b2323c L |
543 | /* Per instruction expressionS buffers: max displacements & immediates. */ |
544 | static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; | |
545 | static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; | |
252b5132 | 546 | |
47926f60 | 547 | /* Current operand we are working on. */ |
ee86248c | 548 | static int this_operand = -1; |
252b5132 | 549 | |
3e73aa7c JH |
550 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
551 | these. */ | |
552 | ||
553 | enum flag_code { | |
554 | CODE_32BIT, | |
555 | CODE_16BIT, | |
556 | CODE_64BIT }; | |
557 | ||
558 | static enum flag_code flag_code; | |
4fa24527 | 559 | static unsigned int object_64bit; |
862be3fb | 560 | static unsigned int disallow_64bit_reloc; |
3e73aa7c JH |
561 | static int use_rela_relocations = 0; |
562 | ||
7af8ed2d NC |
563 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
564 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ | |
565 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) | |
566 | ||
351f65ca L |
567 | /* The ELF ABI to use. */ |
568 | enum x86_elf_abi | |
569 | { | |
570 | I386_ABI, | |
7f56bc95 L |
571 | X86_64_ABI, |
572 | X86_64_X32_ABI | |
351f65ca L |
573 | }; |
574 | ||
575 | static enum x86_elf_abi x86_elf_abi = I386_ABI; | |
7af8ed2d | 576 | #endif |
351f65ca | 577 | |
167ad85b TG |
578 | #if defined (TE_PE) || defined (TE_PEP) |
579 | /* Use big object file format. */ | |
580 | static int use_big_obj = 0; | |
581 | #endif | |
582 | ||
8dcea932 L |
583 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
584 | /* 1 if generating code for a shared library. */ | |
585 | static int shared = 0; | |
586 | #endif | |
587 | ||
47926f60 KH |
588 | /* 1 for intel syntax, |
589 | 0 if att syntax. */ | |
590 | static int intel_syntax = 0; | |
252b5132 | 591 | |
e89c5eaa L |
592 | /* 1 for Intel64 ISA, |
593 | 0 if AMD64 ISA. */ | |
594 | static int intel64; | |
595 | ||
1efbbeb4 L |
596 | /* 1 for intel mnemonic, |
597 | 0 if att mnemonic. */ | |
598 | static int intel_mnemonic = !SYSV386_COMPAT; | |
599 | ||
a60de03c JB |
600 | /* 1 if pseudo registers are permitted. */ |
601 | static int allow_pseudo_reg = 0; | |
602 | ||
47926f60 KH |
603 | /* 1 if register prefix % not required. */ |
604 | static int allow_naked_reg = 0; | |
252b5132 | 605 | |
33eaf5de | 606 | /* 1 if the assembler should add BND prefix for all control-transferring |
7e8b059b L |
607 | instructions supporting it, even if this prefix wasn't specified |
608 | explicitly. */ | |
609 | static int add_bnd_prefix = 0; | |
610 | ||
ba104c83 | 611 | /* 1 if pseudo index register, eiz/riz, is allowed . */ |
db51cc60 L |
612 | static int allow_index_reg = 0; |
613 | ||
d022bddd IT |
614 | /* 1 if the assembler should ignore LOCK prefix, even if it was |
615 | specified explicitly. */ | |
616 | static int omit_lock_prefix = 0; | |
617 | ||
e4e00185 AS |
618 | /* 1 if the assembler should encode lfence, mfence, and sfence as |
619 | "lock addl $0, (%{re}sp)". */ | |
620 | static int avoid_fence = 0; | |
621 | ||
0cb4071e L |
622 | /* 1 if the assembler should generate relax relocations. */ |
623 | ||
624 | static int generate_relax_relocations | |
625 | = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS; | |
626 | ||
7bab8ab5 | 627 | static enum check_kind |
daf50ae7 | 628 | { |
7bab8ab5 JB |
629 | check_none = 0, |
630 | check_warning, | |
631 | check_error | |
daf50ae7 | 632 | } |
7bab8ab5 | 633 | sse_check, operand_check = check_warning; |
daf50ae7 | 634 | |
b6f8c7c4 L |
635 | /* Optimization: |
636 | 1. Clear the REX_W bit with register operand if possible. | |
637 | 2. Above plus use 128bit vector instruction to clear the full vector | |
638 | register. | |
639 | */ | |
640 | static int optimize = 0; | |
641 | ||
642 | /* Optimization: | |
643 | 1. Clear the REX_W bit with register operand if possible. | |
644 | 2. Above plus use 128bit vector instruction to clear the full vector | |
645 | register. | |
646 | 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to | |
647 | "testb $imm7,%r8". | |
648 | */ | |
649 | static int optimize_for_space = 0; | |
650 | ||
2ca3ace5 L |
651 | /* Register prefix used for error message. */ |
652 | static const char *register_prefix = "%"; | |
653 | ||
47926f60 KH |
654 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
655 | leave, push, and pop instructions so that gcc has the same stack | |
656 | frame as in 32 bit mode. */ | |
657 | static char stackop_size = '\0'; | |
eecb386c | 658 | |
12b55ccc L |
659 | /* Non-zero to optimize code alignment. */ |
660 | int optimize_align_code = 1; | |
661 | ||
47926f60 KH |
662 | /* Non-zero to quieten some warnings. */ |
663 | static int quiet_warnings = 0; | |
a38cf1db | 664 | |
47926f60 KH |
665 | /* CPU name. */ |
666 | static const char *cpu_arch_name = NULL; | |
6305a203 | 667 | static char *cpu_sub_arch_name = NULL; |
a38cf1db | 668 | |
47926f60 | 669 | /* CPU feature flags. */ |
40fb9820 L |
670 | static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; |
671 | ||
ccc9c027 L |
672 | /* If we have selected a cpu we are generating instructions for. */ |
673 | static int cpu_arch_tune_set = 0; | |
674 | ||
9103f4f4 | 675 | /* Cpu we are generating instructions for. */ |
fbf3f584 | 676 | enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; |
9103f4f4 L |
677 | |
678 | /* CPU feature flags of cpu we are generating instructions for. */ | |
40fb9820 | 679 | static i386_cpu_flags cpu_arch_tune_flags; |
9103f4f4 | 680 | |
ccc9c027 | 681 | /* CPU instruction set architecture used. */ |
fbf3f584 | 682 | enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; |
ccc9c027 | 683 | |
9103f4f4 | 684 | /* CPU feature flags of instruction set architecture used. */ |
fbf3f584 | 685 | i386_cpu_flags cpu_arch_isa_flags; |
9103f4f4 | 686 | |
fddf5b5b AM |
687 | /* If set, conditional jumps are not automatically promoted to handle |
688 | larger than a byte offset. */ | |
689 | static unsigned int no_cond_jump_promotion = 0; | |
690 | ||
c0f3af97 L |
691 | /* Encode SSE instructions with VEX prefix. */ |
692 | static unsigned int sse2avx; | |
693 | ||
539f890d L |
694 | /* Encode scalar AVX instructions with specific vector length. */ |
695 | static enum | |
696 | { | |
697 | vex128 = 0, | |
698 | vex256 | |
699 | } avxscalar; | |
700 | ||
03751133 L |
701 | /* Encode VEX WIG instructions with specific vex.w. */ |
702 | static enum | |
703 | { | |
704 | vexw0 = 0, | |
705 | vexw1 | |
706 | } vexwig; | |
707 | ||
43234a1e L |
708 | /* Encode scalar EVEX LIG instructions with specific vector length. */ |
709 | static enum | |
710 | { | |
711 | evexl128 = 0, | |
712 | evexl256, | |
713 | evexl512 | |
714 | } evexlig; | |
715 | ||
716 | /* Encode EVEX WIG instructions with specific evex.w. */ | |
717 | static enum | |
718 | { | |
719 | evexw0 = 0, | |
720 | evexw1 | |
721 | } evexwig; | |
722 | ||
d3d3c6db IT |
723 | /* Value to encode in EVEX RC bits, for SAE-only instructions. */ |
724 | static enum rc_type evexrcig = rne; | |
725 | ||
29b0f896 | 726 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
87c245cc | 727 | static symbolS *GOT_symbol; |
29b0f896 | 728 | |
a4447b93 RH |
729 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
730 | unsigned int x86_dwarf2_return_column; | |
731 | ||
732 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
733 | int x86_cie_data_alignment; | |
734 | ||
252b5132 | 735 | /* Interface to relax_segment. |
fddf5b5b AM |
736 | There are 3 major relax states for 386 jump insns because the |
737 | different types of jumps add different sizes to frags when we're | |
738 | figuring out what sort of jump to choose to reach a given label. */ | |
252b5132 | 739 | |
47926f60 | 740 | /* Types. */ |
93c2a809 AM |
741 | #define UNCOND_JUMP 0 |
742 | #define COND_JUMP 1 | |
743 | #define COND_JUMP86 2 | |
fddf5b5b | 744 | |
47926f60 | 745 | /* Sizes. */ |
252b5132 RH |
746 | #define CODE16 1 |
747 | #define SMALL 0 | |
29b0f896 | 748 | #define SMALL16 (SMALL | CODE16) |
252b5132 | 749 | #define BIG 2 |
29b0f896 | 750 | #define BIG16 (BIG | CODE16) |
252b5132 RH |
751 | |
752 | #ifndef INLINE | |
753 | #ifdef __GNUC__ | |
754 | #define INLINE __inline__ | |
755 | #else | |
756 | #define INLINE | |
757 | #endif | |
758 | #endif | |
759 | ||
fddf5b5b AM |
760 | #define ENCODE_RELAX_STATE(type, size) \ |
761 | ((relax_substateT) (((type) << 2) | (size))) | |
762 | #define TYPE_FROM_RELAX_STATE(s) \ | |
763 | ((s) >> 2) | |
764 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
765 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
766 | |
767 | /* This table is used by relax_frag to promote short jumps to long | |
768 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
769 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
770 | don't allow a short jump in a 32 bit code segment to be promoted to | |
771 | a 16 bit offset jump because it's slower (requires data size | |
772 | prefix), and doesn't work, unless the destination is in the bottom | |
773 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
774 | ||
775 | const relax_typeS md_relax_table[] = | |
776 | { | |
24eab124 AM |
777 | /* The fields are: |
778 | 1) most positive reach of this state, | |
779 | 2) most negative reach of this state, | |
93c2a809 | 780 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 781 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 782 | |
fddf5b5b | 783 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
784 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
785 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
786 | /* dword jmp adds 4 bytes to frag: | |
787 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 788 | {0, 0, 4, 0}, |
93c2a809 AM |
789 | /* word jmp adds 2 byte2 to frag: |
790 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
791 | {0, 0, 2, 0}, |
792 | ||
93c2a809 AM |
793 | /* COND_JUMP states. */ |
794 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
795 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
796 | /* dword conditionals adds 5 bytes to frag: | |
797 | 1 extra opcode byte, 4 displacement bytes. */ | |
798 | {0, 0, 5, 0}, | |
fddf5b5b | 799 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
800 | 1 extra opcode byte, 2 displacement bytes. */ |
801 | {0, 0, 3, 0}, | |
802 | ||
803 | /* COND_JUMP86 states. */ | |
804 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
805 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
806 | /* dword conditionals adds 5 bytes to frag: | |
807 | 1 extra opcode byte, 4 displacement bytes. */ | |
808 | {0, 0, 5, 0}, | |
809 | /* word conditionals add 4 bytes to frag: | |
810 | 1 displacement byte and a 3 byte long branch insn. */ | |
811 | {0, 0, 4, 0} | |
252b5132 RH |
812 | }; |
813 | ||
9103f4f4 L |
814 | static const arch_entry cpu_arch[] = |
815 | { | |
89507696 JB |
816 | /* Do not replace the first two entries - i386_target_format() |
817 | relies on them being there in this order. */ | |
8a2c8fef | 818 | { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32, |
293f5f65 | 819 | CPU_GENERIC32_FLAGS, 0 }, |
8a2c8fef | 820 | { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64, |
293f5f65 | 821 | CPU_GENERIC64_FLAGS, 0 }, |
8a2c8fef | 822 | { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN, |
293f5f65 | 823 | CPU_NONE_FLAGS, 0 }, |
8a2c8fef | 824 | { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN, |
293f5f65 | 825 | CPU_I186_FLAGS, 0 }, |
8a2c8fef | 826 | { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN, |
293f5f65 | 827 | CPU_I286_FLAGS, 0 }, |
8a2c8fef | 828 | { STRING_COMMA_LEN ("i386"), PROCESSOR_I386, |
293f5f65 | 829 | CPU_I386_FLAGS, 0 }, |
8a2c8fef | 830 | { STRING_COMMA_LEN ("i486"), PROCESSOR_I486, |
293f5f65 | 831 | CPU_I486_FLAGS, 0 }, |
8a2c8fef | 832 | { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM, |
293f5f65 | 833 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 834 | { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 835 | CPU_I686_FLAGS, 0 }, |
8a2c8fef | 836 | { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM, |
293f5f65 | 837 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 838 | { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 839 | CPU_PENTIUMPRO_FLAGS, 0 }, |
8a2c8fef | 840 | { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 841 | CPU_P2_FLAGS, 0 }, |
8a2c8fef | 842 | { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO, |
293f5f65 | 843 | CPU_P3_FLAGS, 0 }, |
8a2c8fef | 844 | { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4, |
293f5f65 | 845 | CPU_P4_FLAGS, 0 }, |
8a2c8fef | 846 | { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA, |
293f5f65 | 847 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 848 | { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA, |
293f5f65 | 849 | CPU_NOCONA_FLAGS, 0 }, |
8a2c8fef | 850 | { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE, |
293f5f65 | 851 | CPU_CORE_FLAGS, 1 }, |
8a2c8fef | 852 | { STRING_COMMA_LEN ("core"), PROCESSOR_CORE, |
293f5f65 | 853 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 854 | { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2, |
293f5f65 | 855 | CPU_CORE2_FLAGS, 1 }, |
8a2c8fef | 856 | { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2, |
293f5f65 | 857 | CPU_CORE2_FLAGS, 0 }, |
8a2c8fef | 858 | { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7, |
293f5f65 | 859 | CPU_COREI7_FLAGS, 0 }, |
8a2c8fef | 860 | { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM, |
293f5f65 | 861 | CPU_L1OM_FLAGS, 0 }, |
7a9068fe | 862 | { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM, |
293f5f65 | 863 | CPU_K1OM_FLAGS, 0 }, |
81486035 | 864 | { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU, |
293f5f65 | 865 | CPU_IAMCU_FLAGS, 0 }, |
8a2c8fef | 866 | { STRING_COMMA_LEN ("k6"), PROCESSOR_K6, |
293f5f65 | 867 | CPU_K6_FLAGS, 0 }, |
8a2c8fef | 868 | { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6, |
293f5f65 | 869 | CPU_K6_2_FLAGS, 0 }, |
8a2c8fef | 870 | { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON, |
293f5f65 | 871 | CPU_ATHLON_FLAGS, 0 }, |
8a2c8fef | 872 | { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8, |
293f5f65 | 873 | CPU_K8_FLAGS, 1 }, |
8a2c8fef | 874 | { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8, |
293f5f65 | 875 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 876 | { STRING_COMMA_LEN ("k8"), PROCESSOR_K8, |
293f5f65 | 877 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 878 | { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10, |
293f5f65 | 879 | CPU_AMDFAM10_FLAGS, 0 }, |
8aedb9fe | 880 | { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD, |
293f5f65 | 881 | CPU_BDVER1_FLAGS, 0 }, |
8aedb9fe | 882 | { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD, |
293f5f65 | 883 | CPU_BDVER2_FLAGS, 0 }, |
5e5c50d3 | 884 | { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD, |
293f5f65 | 885 | CPU_BDVER3_FLAGS, 0 }, |
c7b0bd56 | 886 | { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD, |
293f5f65 | 887 | CPU_BDVER4_FLAGS, 0 }, |
029f3522 | 888 | { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER, |
293f5f65 | 889 | CPU_ZNVER1_FLAGS, 0 }, |
a9660a6f AP |
890 | { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER, |
891 | CPU_ZNVER2_FLAGS, 0 }, | |
7b458c12 | 892 | { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT, |
293f5f65 | 893 | CPU_BTVER1_FLAGS, 0 }, |
7b458c12 | 894 | { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT, |
293f5f65 | 895 | CPU_BTVER2_FLAGS, 0 }, |
8a2c8fef | 896 | { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN, |
293f5f65 | 897 | CPU_8087_FLAGS, 0 }, |
8a2c8fef | 898 | { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN, |
293f5f65 | 899 | CPU_287_FLAGS, 0 }, |
8a2c8fef | 900 | { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN, |
293f5f65 | 901 | CPU_387_FLAGS, 0 }, |
1848e567 L |
902 | { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN, |
903 | CPU_687_FLAGS, 0 }, | |
d871f3f4 L |
904 | { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN, |
905 | CPU_CMOV_FLAGS, 0 }, | |
906 | { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN, | |
907 | CPU_FXSR_FLAGS, 0 }, | |
8a2c8fef | 908 | { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 909 | CPU_MMX_FLAGS, 0 }, |
8a2c8fef | 910 | { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN, |
293f5f65 | 911 | CPU_SSE_FLAGS, 0 }, |
8a2c8fef | 912 | { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN, |
293f5f65 | 913 | CPU_SSE2_FLAGS, 0 }, |
8a2c8fef | 914 | { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 915 | CPU_SSE3_FLAGS, 0 }, |
8a2c8fef | 916 | { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 917 | CPU_SSSE3_FLAGS, 0 }, |
8a2c8fef | 918 | { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN, |
293f5f65 | 919 | CPU_SSE4_1_FLAGS, 0 }, |
8a2c8fef | 920 | { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN, |
293f5f65 | 921 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 922 | { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN, |
293f5f65 | 923 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 924 | { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN, |
293f5f65 | 925 | CPU_AVX_FLAGS, 0 }, |
6c30d220 | 926 | { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN, |
293f5f65 | 927 | CPU_AVX2_FLAGS, 0 }, |
43234a1e | 928 | { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN, |
293f5f65 | 929 | CPU_AVX512F_FLAGS, 0 }, |
43234a1e | 930 | { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN, |
293f5f65 | 931 | CPU_AVX512CD_FLAGS, 0 }, |
43234a1e | 932 | { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN, |
293f5f65 | 933 | CPU_AVX512ER_FLAGS, 0 }, |
43234a1e | 934 | { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN, |
293f5f65 | 935 | CPU_AVX512PF_FLAGS, 0 }, |
1dfc6506 | 936 | { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN, |
293f5f65 | 937 | CPU_AVX512DQ_FLAGS, 0 }, |
1dfc6506 | 938 | { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN, |
293f5f65 | 939 | CPU_AVX512BW_FLAGS, 0 }, |
1dfc6506 | 940 | { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN, |
293f5f65 | 941 | CPU_AVX512VL_FLAGS, 0 }, |
8a2c8fef | 942 | { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 943 | CPU_VMX_FLAGS, 0 }, |
8729a6f6 | 944 | { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN, |
293f5f65 | 945 | CPU_VMFUNC_FLAGS, 0 }, |
8a2c8fef | 946 | { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN, |
293f5f65 | 947 | CPU_SMX_FLAGS, 0 }, |
8a2c8fef | 948 | { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN, |
293f5f65 | 949 | CPU_XSAVE_FLAGS, 0 }, |
c7b8aa3a | 950 | { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 951 | CPU_XSAVEOPT_FLAGS, 0 }, |
1dfc6506 | 952 | { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN, |
293f5f65 | 953 | CPU_XSAVEC_FLAGS, 0 }, |
1dfc6506 | 954 | { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN, |
293f5f65 | 955 | CPU_XSAVES_FLAGS, 0 }, |
8a2c8fef | 956 | { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN, |
293f5f65 | 957 | CPU_AES_FLAGS, 0 }, |
8a2c8fef | 958 | { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 959 | CPU_PCLMUL_FLAGS, 0 }, |
8a2c8fef | 960 | { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 961 | CPU_PCLMUL_FLAGS, 1 }, |
c7b8aa3a | 962 | { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN, |
293f5f65 | 963 | CPU_FSGSBASE_FLAGS, 0 }, |
c7b8aa3a | 964 | { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN, |
293f5f65 | 965 | CPU_RDRND_FLAGS, 0 }, |
c7b8aa3a | 966 | { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN, |
293f5f65 | 967 | CPU_F16C_FLAGS, 0 }, |
6c30d220 | 968 | { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN, |
293f5f65 | 969 | CPU_BMI2_FLAGS, 0 }, |
8a2c8fef | 970 | { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN, |
293f5f65 | 971 | CPU_FMA_FLAGS, 0 }, |
8a2c8fef | 972 | { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN, |
293f5f65 | 973 | CPU_FMA4_FLAGS, 0 }, |
8a2c8fef | 974 | { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN, |
293f5f65 | 975 | CPU_XOP_FLAGS, 0 }, |
8a2c8fef | 976 | { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN, |
293f5f65 | 977 | CPU_LWP_FLAGS, 0 }, |
8a2c8fef | 978 | { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN, |
293f5f65 | 979 | CPU_MOVBE_FLAGS, 0 }, |
60aa667e | 980 | { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN, |
293f5f65 | 981 | CPU_CX16_FLAGS, 0 }, |
8a2c8fef | 982 | { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN, |
293f5f65 | 983 | CPU_EPT_FLAGS, 0 }, |
6c30d220 | 984 | { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN, |
293f5f65 | 985 | CPU_LZCNT_FLAGS, 0 }, |
42164a71 | 986 | { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN, |
293f5f65 | 987 | CPU_HLE_FLAGS, 0 }, |
42164a71 | 988 | { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN, |
293f5f65 | 989 | CPU_RTM_FLAGS, 0 }, |
6c30d220 | 990 | { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN, |
293f5f65 | 991 | CPU_INVPCID_FLAGS, 0 }, |
8a2c8fef | 992 | { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN, |
293f5f65 | 993 | CPU_CLFLUSH_FLAGS, 0 }, |
22109423 | 994 | { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN, |
293f5f65 | 995 | CPU_NOP_FLAGS, 0 }, |
8a2c8fef | 996 | { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN, |
293f5f65 | 997 | CPU_SYSCALL_FLAGS, 0 }, |
8a2c8fef | 998 | { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN, |
293f5f65 | 999 | CPU_RDTSCP_FLAGS, 0 }, |
8a2c8fef | 1000 | { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN, |
293f5f65 | 1001 | CPU_3DNOW_FLAGS, 0 }, |
8a2c8fef | 1002 | { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN, |
293f5f65 | 1003 | CPU_3DNOWA_FLAGS, 0 }, |
8a2c8fef | 1004 | { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN, |
293f5f65 | 1005 | CPU_PADLOCK_FLAGS, 0 }, |
8a2c8fef | 1006 | { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN, |
293f5f65 | 1007 | CPU_SVME_FLAGS, 1 }, |
8a2c8fef | 1008 | { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN, |
293f5f65 | 1009 | CPU_SVME_FLAGS, 0 }, |
8a2c8fef | 1010 | { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, |
293f5f65 | 1011 | CPU_SSE4A_FLAGS, 0 }, |
8a2c8fef | 1012 | { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN, |
293f5f65 | 1013 | CPU_ABM_FLAGS, 0 }, |
87973e9f | 1014 | { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 1015 | CPU_BMI_FLAGS, 0 }, |
2a2a0f38 | 1016 | { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN, |
293f5f65 | 1017 | CPU_TBM_FLAGS, 0 }, |
e2e1fcde | 1018 | { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1019 | CPU_ADX_FLAGS, 0 }, |
e2e1fcde | 1020 | { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN, |
293f5f65 | 1021 | CPU_RDSEED_FLAGS, 0 }, |
e2e1fcde | 1022 | { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN, |
293f5f65 | 1023 | CPU_PRFCHW_FLAGS, 0 }, |
5c111e37 | 1024 | { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN, |
293f5f65 | 1025 | CPU_SMAP_FLAGS, 0 }, |
7e8b059b | 1026 | { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1027 | CPU_MPX_FLAGS, 0 }, |
a0046408 | 1028 | { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN, |
293f5f65 | 1029 | CPU_SHA_FLAGS, 0 }, |
963f3586 | 1030 | { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 1031 | CPU_CLFLUSHOPT_FLAGS, 0 }, |
dcf893b5 | 1032 | { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN, |
293f5f65 | 1033 | CPU_PREFETCHWT1_FLAGS, 0 }, |
2cf200a4 | 1034 | { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN, |
293f5f65 | 1035 | CPU_SE1_FLAGS, 0 }, |
c5e7287a | 1036 | { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN, |
293f5f65 | 1037 | CPU_CLWB_FLAGS, 0 }, |
2cc1b5aa | 1038 | { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN, |
293f5f65 | 1039 | CPU_AVX512IFMA_FLAGS, 0 }, |
14f195c9 | 1040 | { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 1041 | CPU_AVX512VBMI_FLAGS, 0 }, |
920d2ddc IT |
1042 | { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN, |
1043 | CPU_AVX512_4FMAPS_FLAGS, 0 }, | |
47acf0bd IT |
1044 | { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN, |
1045 | CPU_AVX512_4VNNIW_FLAGS, 0 }, | |
620214f7 IT |
1046 | { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN, |
1047 | CPU_AVX512_VPOPCNTDQ_FLAGS, 0 }, | |
53467f57 IT |
1048 | { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN, |
1049 | CPU_AVX512_VBMI2_FLAGS, 0 }, | |
8cfcb765 IT |
1050 | { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN, |
1051 | CPU_AVX512_VNNI_FLAGS, 0 }, | |
ee6872be IT |
1052 | { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN, |
1053 | CPU_AVX512_BITALG_FLAGS, 0 }, | |
029f3522 | 1054 | { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN, |
293f5f65 | 1055 | CPU_CLZERO_FLAGS, 0 }, |
9916071f | 1056 | { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1057 | CPU_MWAITX_FLAGS, 0 }, |
8eab4136 | 1058 | { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN, |
293f5f65 | 1059 | CPU_OSPKE_FLAGS, 0 }, |
8bc52696 | 1060 | { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN, |
293f5f65 | 1061 | CPU_RDPID_FLAGS, 0 }, |
6b40c462 L |
1062 | { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN, |
1063 | CPU_PTWRITE_FLAGS, 0 }, | |
d777820b IT |
1064 | { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN, |
1065 | CPU_IBT_FLAGS, 0 }, | |
1066 | { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN, | |
1067 | CPU_SHSTK_FLAGS, 0 }, | |
48521003 IT |
1068 | { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN, |
1069 | CPU_GFNI_FLAGS, 0 }, | |
8dcf1fad IT |
1070 | { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN, |
1071 | CPU_VAES_FLAGS, 0 }, | |
ff1982d5 IT |
1072 | { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN, |
1073 | CPU_VPCLMULQDQ_FLAGS, 0 }, | |
3233d7d0 IT |
1074 | { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN, |
1075 | CPU_WBNOINVD_FLAGS, 0 }, | |
be3a8dca IT |
1076 | { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN, |
1077 | CPU_PCONFIG_FLAGS, 0 }, | |
de89d0a3 IT |
1078 | { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN, |
1079 | CPU_WAITPKG_FLAGS, 0 }, | |
c48935d7 IT |
1080 | { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN, |
1081 | CPU_CLDEMOTE_FLAGS, 0 }, | |
c0a30a9f L |
1082 | { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN, |
1083 | CPU_MOVDIRI_FLAGS, 0 }, | |
1084 | { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN, | |
1085 | CPU_MOVDIR64B_FLAGS, 0 }, | |
d6aab7a1 XG |
1086 | { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN, |
1087 | CPU_AVX512_BF16_FLAGS, 0 }, | |
9186c494 L |
1088 | { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN, |
1089 | CPU_AVX512_VP2INTERSECT_FLAGS, 0 }, | |
dd455cf5 L |
1090 | { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN, |
1091 | CPU_ENQCMD_FLAGS, 0 }, | |
142861df JB |
1092 | { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN, |
1093 | CPU_RDPRU_FLAGS, 0 }, | |
1094 | { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN, | |
1095 | CPU_MCOMMIT_FLAGS, 0 }, | |
293f5f65 L |
1096 | }; |
1097 | ||
1098 | static const noarch_entry cpu_noarch[] = | |
1099 | { | |
1100 | { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS }, | |
1848e567 L |
1101 | { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS }, |
1102 | { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS }, | |
1103 | { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS }, | |
d871f3f4 L |
1104 | { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS }, |
1105 | { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS }, | |
293f5f65 L |
1106 | { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS }, |
1107 | { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS }, | |
1848e567 L |
1108 | { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS }, |
1109 | { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS }, | |
1110 | { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS }, | |
1111 | { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS }, | |
1112 | { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS }, | |
1113 | { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS }, | |
293f5f65 | 1114 | { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS }, |
1848e567 | 1115 | { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS }, |
144b71e2 L |
1116 | { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS }, |
1117 | { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS }, | |
1118 | { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS }, | |
1119 | { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS }, | |
1120 | { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS }, | |
1121 | { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS }, | |
1122 | { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS }, | |
1123 | { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS }, | |
1124 | { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS }, | |
920d2ddc | 1125 | { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS }, |
47acf0bd | 1126 | { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS }, |
620214f7 | 1127 | { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS }, |
53467f57 | 1128 | { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS }, |
8cfcb765 | 1129 | { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS }, |
ee6872be | 1130 | { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS }, |
d777820b IT |
1131 | { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS }, |
1132 | { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS }, | |
c0a30a9f L |
1133 | { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS }, |
1134 | { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS }, | |
d6aab7a1 | 1135 | { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS }, |
9186c494 | 1136 | { STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS }, |
dd455cf5 | 1137 | { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS }, |
e413e4e9 AM |
1138 | }; |
1139 | ||
704209c0 | 1140 | #ifdef I386COFF |
a6c24e68 NC |
1141 | /* Like s_lcomm_internal in gas/read.c but the alignment string |
1142 | is allowed to be optional. */ | |
1143 | ||
1144 | static symbolS * | |
1145 | pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size) | |
1146 | { | |
1147 | addressT align = 0; | |
1148 | ||
1149 | SKIP_WHITESPACE (); | |
1150 | ||
7ab9ffdd | 1151 | if (needs_align |
a6c24e68 NC |
1152 | && *input_line_pointer == ',') |
1153 | { | |
1154 | align = parse_align (needs_align - 1); | |
7ab9ffdd | 1155 | |
a6c24e68 NC |
1156 | if (align == (addressT) -1) |
1157 | return NULL; | |
1158 | } | |
1159 | else | |
1160 | { | |
1161 | if (size >= 8) | |
1162 | align = 3; | |
1163 | else if (size >= 4) | |
1164 | align = 2; | |
1165 | else if (size >= 2) | |
1166 | align = 1; | |
1167 | else | |
1168 | align = 0; | |
1169 | } | |
1170 | ||
1171 | bss_alloc (symbolP, size, align); | |
1172 | return symbolP; | |
1173 | } | |
1174 | ||
704209c0 | 1175 | static void |
a6c24e68 NC |
1176 | pe_lcomm (int needs_align) |
1177 | { | |
1178 | s_comm_internal (needs_align * 2, pe_lcomm_internal); | |
1179 | } | |
704209c0 | 1180 | #endif |
a6c24e68 | 1181 | |
29b0f896 AM |
1182 | const pseudo_typeS md_pseudo_table[] = |
1183 | { | |
1184 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) | |
1185 | {"align", s_align_bytes, 0}, | |
1186 | #else | |
1187 | {"align", s_align_ptwo, 0}, | |
1188 | #endif | |
1189 | {"arch", set_cpu_arch, 0}, | |
1190 | #ifndef I386COFF | |
1191 | {"bss", s_bss, 0}, | |
a6c24e68 NC |
1192 | #else |
1193 | {"lcomm", pe_lcomm, 1}, | |
29b0f896 AM |
1194 | #endif |
1195 | {"ffloat", float_cons, 'f'}, | |
1196 | {"dfloat", float_cons, 'd'}, | |
1197 | {"tfloat", float_cons, 'x'}, | |
1198 | {"value", cons, 2}, | |
d182319b | 1199 | {"slong", signed_cons, 4}, |
29b0f896 AM |
1200 | {"noopt", s_ignore, 0}, |
1201 | {"optim", s_ignore, 0}, | |
1202 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, | |
1203 | {"code16", set_code_flag, CODE_16BIT}, | |
1204 | {"code32", set_code_flag, CODE_32BIT}, | |
da5f19a2 | 1205 | #ifdef BFD64 |
29b0f896 | 1206 | {"code64", set_code_flag, CODE_64BIT}, |
da5f19a2 | 1207 | #endif |
29b0f896 AM |
1208 | {"intel_syntax", set_intel_syntax, 1}, |
1209 | {"att_syntax", set_intel_syntax, 0}, | |
1efbbeb4 L |
1210 | {"intel_mnemonic", set_intel_mnemonic, 1}, |
1211 | {"att_mnemonic", set_intel_mnemonic, 0}, | |
db51cc60 L |
1212 | {"allow_index_reg", set_allow_index_reg, 1}, |
1213 | {"disallow_index_reg", set_allow_index_reg, 0}, | |
7bab8ab5 JB |
1214 | {"sse_check", set_check, 0}, |
1215 | {"operand_check", set_check, 1}, | |
3b22753a L |
1216 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
1217 | {"largecomm", handle_large_common, 0}, | |
07a53e5c | 1218 | #else |
68d20676 | 1219 | {"file", dwarf2_directive_file, 0}, |
07a53e5c RH |
1220 | {"loc", dwarf2_directive_loc, 0}, |
1221 | {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, | |
3b22753a | 1222 | #endif |
6482c264 NC |
1223 | #ifdef TE_PE |
1224 | {"secrel32", pe_directive_secrel, 0}, | |
1225 | #endif | |
29b0f896 AM |
1226 | {0, 0, 0} |
1227 | }; | |
1228 | ||
1229 | /* For interface with expression (). */ | |
1230 | extern char *input_line_pointer; | |
1231 | ||
1232 | /* Hash table for instruction mnemonic lookup. */ | |
1233 | static struct hash_control *op_hash; | |
1234 | ||
1235 | /* Hash table for register lookup. */ | |
1236 | static struct hash_control *reg_hash; | |
1237 | \f | |
ce8a8b2f AM |
1238 | /* Various efficient no-op patterns for aligning code labels. |
1239 | Note: Don't try to assemble the instructions in the comments. | |
1240 | 0L and 0w are not legal. */ | |
62a02d25 L |
1241 | static const unsigned char f32_1[] = |
1242 | {0x90}; /* nop */ | |
1243 | static const unsigned char f32_2[] = | |
1244 | {0x66,0x90}; /* xchg %ax,%ax */ | |
1245 | static const unsigned char f32_3[] = | |
1246 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
1247 | static const unsigned char f32_4[] = | |
1248 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
62a02d25 L |
1249 | static const unsigned char f32_6[] = |
1250 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
1251 | static const unsigned char f32_7[] = | |
1252 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
62a02d25 | 1253 | static const unsigned char f16_3[] = |
3ae729d5 | 1254 | {0x8d,0x74,0x00}; /* lea 0(%si),%si */ |
62a02d25 | 1255 | static const unsigned char f16_4[] = |
3ae729d5 L |
1256 | {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */ |
1257 | static const unsigned char jump_disp8[] = | |
1258 | {0xeb}; /* jmp disp8 */ | |
1259 | static const unsigned char jump32_disp32[] = | |
1260 | {0xe9}; /* jmp disp32 */ | |
1261 | static const unsigned char jump16_disp32[] = | |
1262 | {0x66,0xe9}; /* jmp disp32 */ | |
62a02d25 L |
1263 | /* 32-bit NOPs patterns. */ |
1264 | static const unsigned char *const f32_patt[] = { | |
3ae729d5 | 1265 | f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7 |
62a02d25 L |
1266 | }; |
1267 | /* 16-bit NOPs patterns. */ | |
1268 | static const unsigned char *const f16_patt[] = { | |
3ae729d5 | 1269 | f32_1, f32_2, f16_3, f16_4 |
62a02d25 L |
1270 | }; |
1271 | /* nopl (%[re]ax) */ | |
1272 | static const unsigned char alt_3[] = | |
1273 | {0x0f,0x1f,0x00}; | |
1274 | /* nopl 0(%[re]ax) */ | |
1275 | static const unsigned char alt_4[] = | |
1276 | {0x0f,0x1f,0x40,0x00}; | |
1277 | /* nopl 0(%[re]ax,%[re]ax,1) */ | |
1278 | static const unsigned char alt_5[] = | |
1279 | {0x0f,0x1f,0x44,0x00,0x00}; | |
1280 | /* nopw 0(%[re]ax,%[re]ax,1) */ | |
1281 | static const unsigned char alt_6[] = | |
1282 | {0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
1283 | /* nopl 0L(%[re]ax) */ | |
1284 | static const unsigned char alt_7[] = | |
1285 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
1286 | /* nopl 0L(%[re]ax,%[re]ax,1) */ | |
1287 | static const unsigned char alt_8[] = | |
1288 | {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1289 | /* nopw 0L(%[re]ax,%[re]ax,1) */ | |
1290 | static const unsigned char alt_9[] = | |
1291 | {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1292 | /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
1293 | static const unsigned char alt_10[] = | |
1294 | {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
3ae729d5 L |
1295 | /* data16 nopw %cs:0L(%eax,%eax,1) */ |
1296 | static const unsigned char alt_11[] = | |
1297 | {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
62a02d25 L |
1298 | /* 32-bit and 64-bit NOPs patterns. */ |
1299 | static const unsigned char *const alt_patt[] = { | |
1300 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
3ae729d5 | 1301 | alt_9, alt_10, alt_11 |
62a02d25 L |
1302 | }; |
1303 | ||
1304 | /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum | |
1305 | size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */ | |
1306 | ||
1307 | static void | |
1308 | i386_output_nops (char *where, const unsigned char *const *patt, | |
1309 | int count, int max_single_nop_size) | |
1310 | ||
1311 | { | |
3ae729d5 L |
1312 | /* Place the longer NOP first. */ |
1313 | int last; | |
1314 | int offset; | |
3076e594 NC |
1315 | const unsigned char *nops; |
1316 | ||
1317 | if (max_single_nop_size < 1) | |
1318 | { | |
1319 | as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"), | |
1320 | max_single_nop_size); | |
1321 | return; | |
1322 | } | |
1323 | ||
1324 | nops = patt[max_single_nop_size - 1]; | |
3ae729d5 L |
1325 | |
1326 | /* Use the smaller one if the requsted one isn't available. */ | |
1327 | if (nops == NULL) | |
62a02d25 | 1328 | { |
3ae729d5 L |
1329 | max_single_nop_size--; |
1330 | nops = patt[max_single_nop_size - 1]; | |
62a02d25 L |
1331 | } |
1332 | ||
3ae729d5 L |
1333 | last = count % max_single_nop_size; |
1334 | ||
1335 | count -= last; | |
1336 | for (offset = 0; offset < count; offset += max_single_nop_size) | |
1337 | memcpy (where + offset, nops, max_single_nop_size); | |
1338 | ||
1339 | if (last) | |
1340 | { | |
1341 | nops = patt[last - 1]; | |
1342 | if (nops == NULL) | |
1343 | { | |
1344 | /* Use the smaller one plus one-byte NOP if the needed one | |
1345 | isn't available. */ | |
1346 | last--; | |
1347 | nops = patt[last - 1]; | |
1348 | memcpy (where + offset, nops, last); | |
1349 | where[offset + last] = *patt[0]; | |
1350 | } | |
1351 | else | |
1352 | memcpy (where + offset, nops, last); | |
1353 | } | |
62a02d25 L |
1354 | } |
1355 | ||
3ae729d5 L |
1356 | static INLINE int |
1357 | fits_in_imm7 (offsetT num) | |
1358 | { | |
1359 | return (num & 0x7f) == num; | |
1360 | } | |
1361 | ||
1362 | static INLINE int | |
1363 | fits_in_imm31 (offsetT num) | |
1364 | { | |
1365 | return (num & 0x7fffffff) == num; | |
1366 | } | |
62a02d25 L |
1367 | |
1368 | /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a | |
1369 | single NOP instruction LIMIT. */ | |
1370 | ||
1371 | void | |
3ae729d5 | 1372 | i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit) |
62a02d25 | 1373 | { |
3ae729d5 | 1374 | const unsigned char *const *patt = NULL; |
62a02d25 | 1375 | int max_single_nop_size; |
3ae729d5 L |
1376 | /* Maximum number of NOPs before switching to jump over NOPs. */ |
1377 | int max_number_of_nops; | |
62a02d25 | 1378 | |
3ae729d5 | 1379 | switch (fragP->fr_type) |
62a02d25 | 1380 | { |
3ae729d5 L |
1381 | case rs_fill_nop: |
1382 | case rs_align_code: | |
1383 | break; | |
1384 | default: | |
62a02d25 L |
1385 | return; |
1386 | } | |
1387 | ||
ccc9c027 L |
1388 | /* We need to decide which NOP sequence to use for 32bit and |
1389 | 64bit. When -mtune= is used: | |
4eed87de | 1390 | |
76bc74dc L |
1391 | 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and |
1392 | PROCESSOR_GENERIC32, f32_patt will be used. | |
80b8656c L |
1393 | 2. For the rest, alt_patt will be used. |
1394 | ||
1395 | When -mtune= isn't used, alt_patt will be used if | |
22109423 | 1396 | cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will |
76bc74dc | 1397 | be used. |
ccc9c027 L |
1398 | |
1399 | When -march= or .arch is used, we can't use anything beyond | |
1400 | cpu_arch_isa_flags. */ | |
1401 | ||
1402 | if (flag_code == CODE_16BIT) | |
1403 | { | |
3ae729d5 L |
1404 | patt = f16_patt; |
1405 | max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]); | |
1406 | /* Limit number of NOPs to 2 in 16-bit mode. */ | |
1407 | max_number_of_nops = 2; | |
252b5132 | 1408 | } |
33fef721 | 1409 | else |
ccc9c027 | 1410 | { |
fbf3f584 | 1411 | if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN) |
ccc9c027 L |
1412 | { |
1413 | /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ | |
1414 | switch (cpu_arch_tune) | |
1415 | { | |
1416 | case PROCESSOR_UNKNOWN: | |
1417 | /* We use cpu_arch_isa_flags to check if we SHOULD | |
22109423 L |
1418 | optimize with nops. */ |
1419 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1420 | patt = alt_patt; |
ccc9c027 L |
1421 | else |
1422 | patt = f32_patt; | |
1423 | break; | |
ccc9c027 L |
1424 | case PROCESSOR_PENTIUM4: |
1425 | case PROCESSOR_NOCONA: | |
ef05d495 | 1426 | case PROCESSOR_CORE: |
76bc74dc | 1427 | case PROCESSOR_CORE2: |
bd5295b2 | 1428 | case PROCESSOR_COREI7: |
3632d14b | 1429 | case PROCESSOR_L1OM: |
7a9068fe | 1430 | case PROCESSOR_K1OM: |
76bc74dc | 1431 | case PROCESSOR_GENERIC64: |
ccc9c027 L |
1432 | case PROCESSOR_K6: |
1433 | case PROCESSOR_ATHLON: | |
1434 | case PROCESSOR_K8: | |
4eed87de | 1435 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1436 | case PROCESSOR_BD: |
029f3522 | 1437 | case PROCESSOR_ZNVER: |
7b458c12 | 1438 | case PROCESSOR_BT: |
80b8656c | 1439 | patt = alt_patt; |
ccc9c027 | 1440 | break; |
76bc74dc | 1441 | case PROCESSOR_I386: |
ccc9c027 L |
1442 | case PROCESSOR_I486: |
1443 | case PROCESSOR_PENTIUM: | |
2dde1948 | 1444 | case PROCESSOR_PENTIUMPRO: |
81486035 | 1445 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1446 | case PROCESSOR_GENERIC32: |
1447 | patt = f32_patt; | |
1448 | break; | |
4eed87de | 1449 | } |
ccc9c027 L |
1450 | } |
1451 | else | |
1452 | { | |
fbf3f584 | 1453 | switch (fragP->tc_frag_data.tune) |
ccc9c027 L |
1454 | { |
1455 | case PROCESSOR_UNKNOWN: | |
e6a14101 | 1456 | /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be |
ccc9c027 L |
1457 | PROCESSOR_UNKNOWN. */ |
1458 | abort (); | |
1459 | break; | |
1460 | ||
76bc74dc | 1461 | case PROCESSOR_I386: |
ccc9c027 L |
1462 | case PROCESSOR_I486: |
1463 | case PROCESSOR_PENTIUM: | |
81486035 | 1464 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1465 | case PROCESSOR_K6: |
1466 | case PROCESSOR_ATHLON: | |
1467 | case PROCESSOR_K8: | |
4eed87de | 1468 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1469 | case PROCESSOR_BD: |
029f3522 | 1470 | case PROCESSOR_ZNVER: |
7b458c12 | 1471 | case PROCESSOR_BT: |
ccc9c027 L |
1472 | case PROCESSOR_GENERIC32: |
1473 | /* We use cpu_arch_isa_flags to check if we CAN optimize | |
22109423 L |
1474 | with nops. */ |
1475 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1476 | patt = alt_patt; |
ccc9c027 L |
1477 | else |
1478 | patt = f32_patt; | |
1479 | break; | |
76bc74dc L |
1480 | case PROCESSOR_PENTIUMPRO: |
1481 | case PROCESSOR_PENTIUM4: | |
1482 | case PROCESSOR_NOCONA: | |
1483 | case PROCESSOR_CORE: | |
ef05d495 | 1484 | case PROCESSOR_CORE2: |
bd5295b2 | 1485 | case PROCESSOR_COREI7: |
3632d14b | 1486 | case PROCESSOR_L1OM: |
7a9068fe | 1487 | case PROCESSOR_K1OM: |
22109423 | 1488 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) |
80b8656c | 1489 | patt = alt_patt; |
ccc9c027 L |
1490 | else |
1491 | patt = f32_patt; | |
1492 | break; | |
1493 | case PROCESSOR_GENERIC64: | |
80b8656c | 1494 | patt = alt_patt; |
ccc9c027 | 1495 | break; |
4eed87de | 1496 | } |
ccc9c027 L |
1497 | } |
1498 | ||
76bc74dc L |
1499 | if (patt == f32_patt) |
1500 | { | |
3ae729d5 L |
1501 | max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]); |
1502 | /* Limit number of NOPs to 2 for older processors. */ | |
1503 | max_number_of_nops = 2; | |
76bc74dc L |
1504 | } |
1505 | else | |
1506 | { | |
3ae729d5 L |
1507 | max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]); |
1508 | /* Limit number of NOPs to 7 for newer processors. */ | |
1509 | max_number_of_nops = 7; | |
1510 | } | |
1511 | } | |
1512 | ||
1513 | if (limit == 0) | |
1514 | limit = max_single_nop_size; | |
1515 | ||
1516 | if (fragP->fr_type == rs_fill_nop) | |
1517 | { | |
1518 | /* Output NOPs for .nop directive. */ | |
1519 | if (limit > max_single_nop_size) | |
1520 | { | |
1521 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1522 | _("invalid single nop size: %d " | |
1523 | "(expect within [0, %d])"), | |
1524 | limit, max_single_nop_size); | |
1525 | return; | |
1526 | } | |
1527 | } | |
1528 | else | |
1529 | fragP->fr_var = count; | |
1530 | ||
1531 | if ((count / max_single_nop_size) > max_number_of_nops) | |
1532 | { | |
1533 | /* Generate jump over NOPs. */ | |
1534 | offsetT disp = count - 2; | |
1535 | if (fits_in_imm7 (disp)) | |
1536 | { | |
1537 | /* Use "jmp disp8" if possible. */ | |
1538 | count = disp; | |
1539 | where[0] = jump_disp8[0]; | |
1540 | where[1] = count; | |
1541 | where += 2; | |
1542 | } | |
1543 | else | |
1544 | { | |
1545 | unsigned int size_of_jump; | |
1546 | ||
1547 | if (flag_code == CODE_16BIT) | |
1548 | { | |
1549 | where[0] = jump16_disp32[0]; | |
1550 | where[1] = jump16_disp32[1]; | |
1551 | size_of_jump = 2; | |
1552 | } | |
1553 | else | |
1554 | { | |
1555 | where[0] = jump32_disp32[0]; | |
1556 | size_of_jump = 1; | |
1557 | } | |
1558 | ||
1559 | count -= size_of_jump + 4; | |
1560 | if (!fits_in_imm31 (count)) | |
1561 | { | |
1562 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1563 | _("jump over nop padding out of range")); | |
1564 | return; | |
1565 | } | |
1566 | ||
1567 | md_number_to_chars (where + size_of_jump, count, 4); | |
1568 | where += size_of_jump + 4; | |
76bc74dc | 1569 | } |
ccc9c027 | 1570 | } |
3ae729d5 L |
1571 | |
1572 | /* Generate multiple NOPs. */ | |
1573 | i386_output_nops (where, patt, count, limit); | |
252b5132 RH |
1574 | } |
1575 | ||
c6fb90c8 | 1576 | static INLINE int |
0dfbf9d7 | 1577 | operand_type_all_zero (const union i386_operand_type *x) |
40fb9820 | 1578 | { |
0dfbf9d7 | 1579 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1580 | { |
1581 | case 3: | |
0dfbf9d7 | 1582 | if (x->array[2]) |
c6fb90c8 | 1583 | return 0; |
1a0670f3 | 1584 | /* Fall through. */ |
c6fb90c8 | 1585 | case 2: |
0dfbf9d7 | 1586 | if (x->array[1]) |
c6fb90c8 | 1587 | return 0; |
1a0670f3 | 1588 | /* Fall through. */ |
c6fb90c8 | 1589 | case 1: |
0dfbf9d7 | 1590 | return !x->array[0]; |
c6fb90c8 L |
1591 | default: |
1592 | abort (); | |
1593 | } | |
40fb9820 L |
1594 | } |
1595 | ||
c6fb90c8 | 1596 | static INLINE void |
0dfbf9d7 | 1597 | operand_type_set (union i386_operand_type *x, unsigned int v) |
40fb9820 | 1598 | { |
0dfbf9d7 | 1599 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1600 | { |
1601 | case 3: | |
0dfbf9d7 | 1602 | x->array[2] = v; |
1a0670f3 | 1603 | /* Fall through. */ |
c6fb90c8 | 1604 | case 2: |
0dfbf9d7 | 1605 | x->array[1] = v; |
1a0670f3 | 1606 | /* Fall through. */ |
c6fb90c8 | 1607 | case 1: |
0dfbf9d7 | 1608 | x->array[0] = v; |
1a0670f3 | 1609 | /* Fall through. */ |
c6fb90c8 L |
1610 | break; |
1611 | default: | |
1612 | abort (); | |
1613 | } | |
bab6aec1 JB |
1614 | |
1615 | x->bitfield.class = ClassNone; | |
75e5731b | 1616 | x->bitfield.instance = InstanceNone; |
c6fb90c8 | 1617 | } |
40fb9820 | 1618 | |
c6fb90c8 | 1619 | static INLINE int |
0dfbf9d7 L |
1620 | operand_type_equal (const union i386_operand_type *x, |
1621 | const union i386_operand_type *y) | |
c6fb90c8 | 1622 | { |
0dfbf9d7 | 1623 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1624 | { |
1625 | case 3: | |
0dfbf9d7 | 1626 | if (x->array[2] != y->array[2]) |
c6fb90c8 | 1627 | return 0; |
1a0670f3 | 1628 | /* Fall through. */ |
c6fb90c8 | 1629 | case 2: |
0dfbf9d7 | 1630 | if (x->array[1] != y->array[1]) |
c6fb90c8 | 1631 | return 0; |
1a0670f3 | 1632 | /* Fall through. */ |
c6fb90c8 | 1633 | case 1: |
0dfbf9d7 | 1634 | return x->array[0] == y->array[0]; |
c6fb90c8 L |
1635 | break; |
1636 | default: | |
1637 | abort (); | |
1638 | } | |
1639 | } | |
40fb9820 | 1640 | |
0dfbf9d7 L |
1641 | static INLINE int |
1642 | cpu_flags_all_zero (const union i386_cpu_flags *x) | |
1643 | { | |
1644 | switch (ARRAY_SIZE(x->array)) | |
1645 | { | |
53467f57 IT |
1646 | case 4: |
1647 | if (x->array[3]) | |
1648 | return 0; | |
1649 | /* Fall through. */ | |
0dfbf9d7 L |
1650 | case 3: |
1651 | if (x->array[2]) | |
1652 | return 0; | |
1a0670f3 | 1653 | /* Fall through. */ |
0dfbf9d7 L |
1654 | case 2: |
1655 | if (x->array[1]) | |
1656 | return 0; | |
1a0670f3 | 1657 | /* Fall through. */ |
0dfbf9d7 L |
1658 | case 1: |
1659 | return !x->array[0]; | |
1660 | default: | |
1661 | abort (); | |
1662 | } | |
1663 | } | |
1664 | ||
0dfbf9d7 L |
1665 | static INLINE int |
1666 | cpu_flags_equal (const union i386_cpu_flags *x, | |
1667 | const union i386_cpu_flags *y) | |
1668 | { | |
1669 | switch (ARRAY_SIZE(x->array)) | |
1670 | { | |
53467f57 IT |
1671 | case 4: |
1672 | if (x->array[3] != y->array[3]) | |
1673 | return 0; | |
1674 | /* Fall through. */ | |
0dfbf9d7 L |
1675 | case 3: |
1676 | if (x->array[2] != y->array[2]) | |
1677 | return 0; | |
1a0670f3 | 1678 | /* Fall through. */ |
0dfbf9d7 L |
1679 | case 2: |
1680 | if (x->array[1] != y->array[1]) | |
1681 | return 0; | |
1a0670f3 | 1682 | /* Fall through. */ |
0dfbf9d7 L |
1683 | case 1: |
1684 | return x->array[0] == y->array[0]; | |
1685 | break; | |
1686 | default: | |
1687 | abort (); | |
1688 | } | |
1689 | } | |
c6fb90c8 L |
1690 | |
1691 | static INLINE int | |
1692 | cpu_flags_check_cpu64 (i386_cpu_flags f) | |
1693 | { | |
1694 | return !((flag_code == CODE_64BIT && f.bitfield.cpuno64) | |
1695 | || (flag_code != CODE_64BIT && f.bitfield.cpu64)); | |
40fb9820 L |
1696 | } |
1697 | ||
c6fb90c8 L |
1698 | static INLINE i386_cpu_flags |
1699 | cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1700 | { |
c6fb90c8 L |
1701 | switch (ARRAY_SIZE (x.array)) |
1702 | { | |
53467f57 IT |
1703 | case 4: |
1704 | x.array [3] &= y.array [3]; | |
1705 | /* Fall through. */ | |
c6fb90c8 L |
1706 | case 3: |
1707 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1708 | /* Fall through. */ |
c6fb90c8 L |
1709 | case 2: |
1710 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1711 | /* Fall through. */ |
c6fb90c8 L |
1712 | case 1: |
1713 | x.array [0] &= y.array [0]; | |
1714 | break; | |
1715 | default: | |
1716 | abort (); | |
1717 | } | |
1718 | return x; | |
1719 | } | |
40fb9820 | 1720 | |
c6fb90c8 L |
1721 | static INLINE i386_cpu_flags |
1722 | cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1723 | { |
c6fb90c8 | 1724 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1725 | { |
53467f57 IT |
1726 | case 4: |
1727 | x.array [3] |= y.array [3]; | |
1728 | /* Fall through. */ | |
c6fb90c8 L |
1729 | case 3: |
1730 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1731 | /* Fall through. */ |
c6fb90c8 L |
1732 | case 2: |
1733 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1734 | /* Fall through. */ |
c6fb90c8 L |
1735 | case 1: |
1736 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1737 | break; |
1738 | default: | |
1739 | abort (); | |
1740 | } | |
40fb9820 L |
1741 | return x; |
1742 | } | |
1743 | ||
309d3373 JB |
1744 | static INLINE i386_cpu_flags |
1745 | cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y) | |
1746 | { | |
1747 | switch (ARRAY_SIZE (x.array)) | |
1748 | { | |
53467f57 IT |
1749 | case 4: |
1750 | x.array [3] &= ~y.array [3]; | |
1751 | /* Fall through. */ | |
309d3373 JB |
1752 | case 3: |
1753 | x.array [2] &= ~y.array [2]; | |
1a0670f3 | 1754 | /* Fall through. */ |
309d3373 JB |
1755 | case 2: |
1756 | x.array [1] &= ~y.array [1]; | |
1a0670f3 | 1757 | /* Fall through. */ |
309d3373 JB |
1758 | case 1: |
1759 | x.array [0] &= ~y.array [0]; | |
1760 | break; | |
1761 | default: | |
1762 | abort (); | |
1763 | } | |
1764 | return x; | |
1765 | } | |
1766 | ||
c0f3af97 L |
1767 | #define CPU_FLAGS_ARCH_MATCH 0x1 |
1768 | #define CPU_FLAGS_64BIT_MATCH 0x2 | |
1769 | ||
c0f3af97 | 1770 | #define CPU_FLAGS_PERFECT_MATCH \ |
db12e14e | 1771 | (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH) |
c0f3af97 L |
1772 | |
1773 | /* Return CPU flags match bits. */ | |
3629bb00 | 1774 | |
40fb9820 | 1775 | static int |
d3ce72d0 | 1776 | cpu_flags_match (const insn_template *t) |
40fb9820 | 1777 | { |
c0f3af97 L |
1778 | i386_cpu_flags x = t->cpu_flags; |
1779 | int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0; | |
40fb9820 L |
1780 | |
1781 | x.bitfield.cpu64 = 0; | |
1782 | x.bitfield.cpuno64 = 0; | |
1783 | ||
0dfbf9d7 | 1784 | if (cpu_flags_all_zero (&x)) |
c0f3af97 L |
1785 | { |
1786 | /* This instruction is available on all archs. */ | |
db12e14e | 1787 | match |= CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1788 | } |
3629bb00 L |
1789 | else |
1790 | { | |
c0f3af97 | 1791 | /* This instruction is available only on some archs. */ |
3629bb00 L |
1792 | i386_cpu_flags cpu = cpu_arch_flags; |
1793 | ||
ab592e75 JB |
1794 | /* AVX512VL is no standalone feature - match it and then strip it. */ |
1795 | if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl) | |
1796 | return match; | |
1797 | x.bitfield.cpuavx512vl = 0; | |
1798 | ||
3629bb00 | 1799 | cpu = cpu_flags_and (x, cpu); |
c0f3af97 L |
1800 | if (!cpu_flags_all_zero (&cpu)) |
1801 | { | |
a5ff0eb2 L |
1802 | if (x.bitfield.cpuavx) |
1803 | { | |
929f69fa | 1804 | /* We need to check a few extra flags with AVX. */ |
b9d49817 JB |
1805 | if (cpu.bitfield.cpuavx |
1806 | && (!t->opcode_modifier.sse2avx || sse2avx) | |
1807 | && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes) | |
929f69fa | 1808 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) |
b9d49817 JB |
1809 | && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul)) |
1810 | match |= CPU_FLAGS_ARCH_MATCH; | |
a5ff0eb2 | 1811 | } |
929f69fa JB |
1812 | else if (x.bitfield.cpuavx512f) |
1813 | { | |
1814 | /* We need to check a few extra flags with AVX512F. */ | |
1815 | if (cpu.bitfield.cpuavx512f | |
1816 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) | |
1817 | && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes) | |
1818 | && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq)) | |
1819 | match |= CPU_FLAGS_ARCH_MATCH; | |
1820 | } | |
a5ff0eb2 | 1821 | else |
db12e14e | 1822 | match |= CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1823 | } |
3629bb00 | 1824 | } |
c0f3af97 | 1825 | return match; |
40fb9820 L |
1826 | } |
1827 | ||
c6fb90c8 L |
1828 | static INLINE i386_operand_type |
1829 | operand_type_and (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1830 | { |
bab6aec1 JB |
1831 | if (x.bitfield.class != y.bitfield.class) |
1832 | x.bitfield.class = ClassNone; | |
75e5731b JB |
1833 | if (x.bitfield.instance != y.bitfield.instance) |
1834 | x.bitfield.instance = InstanceNone; | |
bab6aec1 | 1835 | |
c6fb90c8 L |
1836 | switch (ARRAY_SIZE (x.array)) |
1837 | { | |
1838 | case 3: | |
1839 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1840 | /* Fall through. */ |
c6fb90c8 L |
1841 | case 2: |
1842 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1843 | /* Fall through. */ |
c6fb90c8 L |
1844 | case 1: |
1845 | x.array [0] &= y.array [0]; | |
1846 | break; | |
1847 | default: | |
1848 | abort (); | |
1849 | } | |
1850 | return x; | |
40fb9820 L |
1851 | } |
1852 | ||
73053c1f JB |
1853 | static INLINE i386_operand_type |
1854 | operand_type_and_not (i386_operand_type x, i386_operand_type y) | |
1855 | { | |
bab6aec1 | 1856 | gas_assert (y.bitfield.class == ClassNone); |
75e5731b | 1857 | gas_assert (y.bitfield.instance == InstanceNone); |
bab6aec1 | 1858 | |
73053c1f JB |
1859 | switch (ARRAY_SIZE (x.array)) |
1860 | { | |
1861 | case 3: | |
1862 | x.array [2] &= ~y.array [2]; | |
1863 | /* Fall through. */ | |
1864 | case 2: | |
1865 | x.array [1] &= ~y.array [1]; | |
1866 | /* Fall through. */ | |
1867 | case 1: | |
1868 | x.array [0] &= ~y.array [0]; | |
1869 | break; | |
1870 | default: | |
1871 | abort (); | |
1872 | } | |
1873 | return x; | |
1874 | } | |
1875 | ||
c6fb90c8 L |
1876 | static INLINE i386_operand_type |
1877 | operand_type_or (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1878 | { |
bab6aec1 JB |
1879 | gas_assert (x.bitfield.class == ClassNone || |
1880 | y.bitfield.class == ClassNone || | |
1881 | x.bitfield.class == y.bitfield.class); | |
75e5731b JB |
1882 | gas_assert (x.bitfield.instance == InstanceNone || |
1883 | y.bitfield.instance == InstanceNone || | |
1884 | x.bitfield.instance == y.bitfield.instance); | |
bab6aec1 | 1885 | |
c6fb90c8 | 1886 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1887 | { |
c6fb90c8 L |
1888 | case 3: |
1889 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1890 | /* Fall through. */ |
c6fb90c8 L |
1891 | case 2: |
1892 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1893 | /* Fall through. */ |
c6fb90c8 L |
1894 | case 1: |
1895 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1896 | break; |
1897 | default: | |
1898 | abort (); | |
1899 | } | |
c6fb90c8 L |
1900 | return x; |
1901 | } | |
40fb9820 | 1902 | |
c6fb90c8 L |
1903 | static INLINE i386_operand_type |
1904 | operand_type_xor (i386_operand_type x, i386_operand_type y) | |
1905 | { | |
bab6aec1 | 1906 | gas_assert (y.bitfield.class == ClassNone); |
75e5731b | 1907 | gas_assert (y.bitfield.instance == InstanceNone); |
bab6aec1 | 1908 | |
c6fb90c8 L |
1909 | switch (ARRAY_SIZE (x.array)) |
1910 | { | |
1911 | case 3: | |
1912 | x.array [2] ^= y.array [2]; | |
1a0670f3 | 1913 | /* Fall through. */ |
c6fb90c8 L |
1914 | case 2: |
1915 | x.array [1] ^= y.array [1]; | |
1a0670f3 | 1916 | /* Fall through. */ |
c6fb90c8 L |
1917 | case 1: |
1918 | x.array [0] ^= y.array [0]; | |
1919 | break; | |
1920 | default: | |
1921 | abort (); | |
1922 | } | |
40fb9820 L |
1923 | return x; |
1924 | } | |
1925 | ||
40fb9820 L |
1926 | static const i386_operand_type disp16 = OPERAND_TYPE_DISP16; |
1927 | static const i386_operand_type disp32 = OPERAND_TYPE_DISP32; | |
1928 | static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S; | |
1929 | static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32; | |
bab6aec1 JB |
1930 | static const i386_operand_type anydisp = OPERAND_TYPE_ANYDISP; |
1931 | static const i386_operand_type anyimm = OPERAND_TYPE_ANYIMM; | |
40fb9820 | 1932 | static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM; |
43234a1e | 1933 | static const i386_operand_type regmask = OPERAND_TYPE_REGMASK; |
40fb9820 L |
1934 | static const i386_operand_type imm8 = OPERAND_TYPE_IMM8; |
1935 | static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S; | |
1936 | static const i386_operand_type imm16 = OPERAND_TYPE_IMM16; | |
1937 | static const i386_operand_type imm32 = OPERAND_TYPE_IMM32; | |
1938 | static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S; | |
1939 | static const i386_operand_type imm64 = OPERAND_TYPE_IMM64; | |
1940 | static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32; | |
1941 | static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S; | |
1942 | static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S; | |
1943 | ||
1944 | enum operand_type | |
1945 | { | |
1946 | reg, | |
40fb9820 L |
1947 | imm, |
1948 | disp, | |
1949 | anymem | |
1950 | }; | |
1951 | ||
c6fb90c8 | 1952 | static INLINE int |
40fb9820 L |
1953 | operand_type_check (i386_operand_type t, enum operand_type c) |
1954 | { | |
1955 | switch (c) | |
1956 | { | |
1957 | case reg: | |
bab6aec1 | 1958 | return t.bitfield.class == Reg; |
40fb9820 | 1959 | |
40fb9820 L |
1960 | case imm: |
1961 | return (t.bitfield.imm8 | |
1962 | || t.bitfield.imm8s | |
1963 | || t.bitfield.imm16 | |
1964 | || t.bitfield.imm32 | |
1965 | || t.bitfield.imm32s | |
1966 | || t.bitfield.imm64); | |
1967 | ||
1968 | case disp: | |
1969 | return (t.bitfield.disp8 | |
1970 | || t.bitfield.disp16 | |
1971 | || t.bitfield.disp32 | |
1972 | || t.bitfield.disp32s | |
1973 | || t.bitfield.disp64); | |
1974 | ||
1975 | case anymem: | |
1976 | return (t.bitfield.disp8 | |
1977 | || t.bitfield.disp16 | |
1978 | || t.bitfield.disp32 | |
1979 | || t.bitfield.disp32s | |
1980 | || t.bitfield.disp64 | |
1981 | || t.bitfield.baseindex); | |
1982 | ||
1983 | default: | |
1984 | abort (); | |
1985 | } | |
2cfe26b6 AM |
1986 | |
1987 | return 0; | |
40fb9820 L |
1988 | } |
1989 | ||
7a54636a L |
1990 | /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size |
1991 | between operand GIVEN and opeand WANTED for instruction template T. */ | |
5c07affc L |
1992 | |
1993 | static INLINE int | |
7a54636a L |
1994 | match_operand_size (const insn_template *t, unsigned int wanted, |
1995 | unsigned int given) | |
5c07affc | 1996 | { |
3ac21baa JB |
1997 | return !((i.types[given].bitfield.byte |
1998 | && !t->operand_types[wanted].bitfield.byte) | |
1999 | || (i.types[given].bitfield.word | |
2000 | && !t->operand_types[wanted].bitfield.word) | |
2001 | || (i.types[given].bitfield.dword | |
2002 | && !t->operand_types[wanted].bitfield.dword) | |
2003 | || (i.types[given].bitfield.qword | |
2004 | && !t->operand_types[wanted].bitfield.qword) | |
2005 | || (i.types[given].bitfield.tbyte | |
2006 | && !t->operand_types[wanted].bitfield.tbyte)); | |
5c07affc L |
2007 | } |
2008 | ||
dd40ce22 L |
2009 | /* Return 1 if there is no conflict in SIMD register between operand |
2010 | GIVEN and opeand WANTED for instruction template T. */ | |
1b54b8d7 JB |
2011 | |
2012 | static INLINE int | |
dd40ce22 L |
2013 | match_simd_size (const insn_template *t, unsigned int wanted, |
2014 | unsigned int given) | |
1b54b8d7 | 2015 | { |
3ac21baa JB |
2016 | return !((i.types[given].bitfield.xmmword |
2017 | && !t->operand_types[wanted].bitfield.xmmword) | |
2018 | || (i.types[given].bitfield.ymmword | |
2019 | && !t->operand_types[wanted].bitfield.ymmword) | |
2020 | || (i.types[given].bitfield.zmmword | |
2021 | && !t->operand_types[wanted].bitfield.zmmword)); | |
1b54b8d7 JB |
2022 | } |
2023 | ||
7a54636a L |
2024 | /* Return 1 if there is no conflict in any size between operand GIVEN |
2025 | and opeand WANTED for instruction template T. */ | |
5c07affc L |
2026 | |
2027 | static INLINE int | |
dd40ce22 L |
2028 | match_mem_size (const insn_template *t, unsigned int wanted, |
2029 | unsigned int given) | |
5c07affc | 2030 | { |
7a54636a | 2031 | return (match_operand_size (t, wanted, given) |
3ac21baa | 2032 | && !((i.types[given].bitfield.unspecified |
af508cb9 | 2033 | && !i.broadcast |
3ac21baa JB |
2034 | && !t->operand_types[wanted].bitfield.unspecified) |
2035 | || (i.types[given].bitfield.fword | |
2036 | && !t->operand_types[wanted].bitfield.fword) | |
1b54b8d7 JB |
2037 | /* For scalar opcode templates to allow register and memory |
2038 | operands at the same time, some special casing is needed | |
d6793fa1 JB |
2039 | here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and |
2040 | down-conversion vpmov*. */ | |
3528c362 | 2041 | || ((t->operand_types[wanted].bitfield.class == RegSIMD |
1b54b8d7 | 2042 | && !t->opcode_modifier.broadcast |
3ac21baa JB |
2043 | && (t->operand_types[wanted].bitfield.byte |
2044 | || t->operand_types[wanted].bitfield.word | |
2045 | || t->operand_types[wanted].bitfield.dword | |
2046 | || t->operand_types[wanted].bitfield.qword)) | |
2047 | ? (i.types[given].bitfield.xmmword | |
2048 | || i.types[given].bitfield.ymmword | |
2049 | || i.types[given].bitfield.zmmword) | |
2050 | : !match_simd_size(t, wanted, given)))); | |
5c07affc L |
2051 | } |
2052 | ||
3ac21baa JB |
2053 | /* Return value has MATCH_STRAIGHT set if there is no size conflict on any |
2054 | operands for instruction template T, and it has MATCH_REVERSE set if there | |
2055 | is no size conflict on any operands for the template with operands reversed | |
2056 | (and the template allows for reversing in the first place). */ | |
5c07affc | 2057 | |
3ac21baa JB |
2058 | #define MATCH_STRAIGHT 1 |
2059 | #define MATCH_REVERSE 2 | |
2060 | ||
2061 | static INLINE unsigned int | |
d3ce72d0 | 2062 | operand_size_match (const insn_template *t) |
5c07affc | 2063 | { |
3ac21baa | 2064 | unsigned int j, match = MATCH_STRAIGHT; |
5c07affc L |
2065 | |
2066 | /* Don't check jump instructions. */ | |
2067 | if (t->opcode_modifier.jump | |
2068 | || t->opcode_modifier.jumpbyte | |
2069 | || t->opcode_modifier.jumpdword | |
2070 | || t->opcode_modifier.jumpintersegment) | |
2071 | return match; | |
2072 | ||
2073 | /* Check memory and accumulator operand size. */ | |
2074 | for (j = 0; j < i.operands; j++) | |
2075 | { | |
3528c362 JB |
2076 | if (i.types[j].bitfield.class != Reg |
2077 | && i.types[j].bitfield.class != RegSIMD | |
1b54b8d7 | 2078 | && t->operand_types[j].bitfield.anysize) |
5c07affc L |
2079 | continue; |
2080 | ||
bab6aec1 | 2081 | if (t->operand_types[j].bitfield.class == Reg |
7a54636a | 2082 | && !match_operand_size (t, j, j)) |
5c07affc L |
2083 | { |
2084 | match = 0; | |
2085 | break; | |
2086 | } | |
2087 | ||
3528c362 | 2088 | if (t->operand_types[j].bitfield.class == RegSIMD |
3ac21baa | 2089 | && !match_simd_size (t, j, j)) |
1b54b8d7 JB |
2090 | { |
2091 | match = 0; | |
2092 | break; | |
2093 | } | |
2094 | ||
75e5731b | 2095 | if (t->operand_types[j].bitfield.instance == Accum |
7a54636a | 2096 | && (!match_operand_size (t, j, j) || !match_simd_size (t, j, j))) |
1b54b8d7 JB |
2097 | { |
2098 | match = 0; | |
2099 | break; | |
2100 | } | |
2101 | ||
c48dadc9 | 2102 | if ((i.flags[j] & Operand_Mem) && !match_mem_size (t, j, j)) |
5c07affc L |
2103 | { |
2104 | match = 0; | |
2105 | break; | |
2106 | } | |
2107 | } | |
2108 | ||
3ac21baa | 2109 | if (!t->opcode_modifier.d) |
891edac4 L |
2110 | { |
2111 | mismatch: | |
3ac21baa JB |
2112 | if (!match) |
2113 | i.error = operand_size_mismatch; | |
2114 | return match; | |
891edac4 | 2115 | } |
5c07affc L |
2116 | |
2117 | /* Check reverse. */ | |
f5eb1d70 | 2118 | gas_assert (i.operands >= 2 && i.operands <= 3); |
5c07affc | 2119 | |
f5eb1d70 | 2120 | for (j = 0; j < i.operands; j++) |
5c07affc | 2121 | { |
f5eb1d70 JB |
2122 | unsigned int given = i.operands - j - 1; |
2123 | ||
bab6aec1 | 2124 | if (t->operand_types[j].bitfield.class == Reg |
f5eb1d70 | 2125 | && !match_operand_size (t, j, given)) |
891edac4 | 2126 | goto mismatch; |
5c07affc | 2127 | |
3528c362 | 2128 | if (t->operand_types[j].bitfield.class == RegSIMD |
f5eb1d70 | 2129 | && !match_simd_size (t, j, given)) |
dbbc8b7e JB |
2130 | goto mismatch; |
2131 | ||
75e5731b | 2132 | if (t->operand_types[j].bitfield.instance == Accum |
f5eb1d70 JB |
2133 | && (!match_operand_size (t, j, given) |
2134 | || !match_simd_size (t, j, given))) | |
dbbc8b7e JB |
2135 | goto mismatch; |
2136 | ||
f5eb1d70 | 2137 | if ((i.flags[given] & Operand_Mem) && !match_mem_size (t, j, given)) |
891edac4 | 2138 | goto mismatch; |
5c07affc L |
2139 | } |
2140 | ||
3ac21baa | 2141 | return match | MATCH_REVERSE; |
5c07affc L |
2142 | } |
2143 | ||
c6fb90c8 | 2144 | static INLINE int |
40fb9820 L |
2145 | operand_type_match (i386_operand_type overlap, |
2146 | i386_operand_type given) | |
2147 | { | |
2148 | i386_operand_type temp = overlap; | |
2149 | ||
2150 | temp.bitfield.jumpabsolute = 0; | |
7d5e4556 | 2151 | temp.bitfield.unspecified = 0; |
5c07affc L |
2152 | temp.bitfield.byte = 0; |
2153 | temp.bitfield.word = 0; | |
2154 | temp.bitfield.dword = 0; | |
2155 | temp.bitfield.fword = 0; | |
2156 | temp.bitfield.qword = 0; | |
2157 | temp.bitfield.tbyte = 0; | |
2158 | temp.bitfield.xmmword = 0; | |
c0f3af97 | 2159 | temp.bitfield.ymmword = 0; |
43234a1e | 2160 | temp.bitfield.zmmword = 0; |
0dfbf9d7 | 2161 | if (operand_type_all_zero (&temp)) |
891edac4 | 2162 | goto mismatch; |
40fb9820 | 2163 | |
891edac4 L |
2164 | if (given.bitfield.baseindex == overlap.bitfield.baseindex |
2165 | && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute) | |
2166 | return 1; | |
2167 | ||
2168 | mismatch: | |
a65babc9 | 2169 | i.error = operand_type_mismatch; |
891edac4 | 2170 | return 0; |
40fb9820 L |
2171 | } |
2172 | ||
7d5e4556 | 2173 | /* If given types g0 and g1 are registers they must be of the same type |
10c17abd JB |
2174 | unless the expected operand type register overlap is null. |
2175 | Memory operand size of certain SIMD instructions is also being checked | |
2176 | here. */ | |
40fb9820 | 2177 | |
c6fb90c8 | 2178 | static INLINE int |
dc821c5f | 2179 | operand_type_register_match (i386_operand_type g0, |
40fb9820 | 2180 | i386_operand_type t0, |
40fb9820 L |
2181 | i386_operand_type g1, |
2182 | i386_operand_type t1) | |
2183 | { | |
bab6aec1 | 2184 | if (g0.bitfield.class != Reg |
3528c362 | 2185 | && g0.bitfield.class != RegSIMD |
10c17abd JB |
2186 | && (!operand_type_check (g0, anymem) |
2187 | || g0.bitfield.unspecified | |
3528c362 | 2188 | || t0.bitfield.class != RegSIMD)) |
40fb9820 L |
2189 | return 1; |
2190 | ||
bab6aec1 | 2191 | if (g1.bitfield.class != Reg |
3528c362 | 2192 | && g1.bitfield.class != RegSIMD |
10c17abd JB |
2193 | && (!operand_type_check (g1, anymem) |
2194 | || g1.bitfield.unspecified | |
3528c362 | 2195 | || t1.bitfield.class != RegSIMD)) |
40fb9820 L |
2196 | return 1; |
2197 | ||
dc821c5f JB |
2198 | if (g0.bitfield.byte == g1.bitfield.byte |
2199 | && g0.bitfield.word == g1.bitfield.word | |
2200 | && g0.bitfield.dword == g1.bitfield.dword | |
10c17abd JB |
2201 | && g0.bitfield.qword == g1.bitfield.qword |
2202 | && g0.bitfield.xmmword == g1.bitfield.xmmword | |
2203 | && g0.bitfield.ymmword == g1.bitfield.ymmword | |
2204 | && g0.bitfield.zmmword == g1.bitfield.zmmword) | |
40fb9820 L |
2205 | return 1; |
2206 | ||
dc821c5f JB |
2207 | if (!(t0.bitfield.byte & t1.bitfield.byte) |
2208 | && !(t0.bitfield.word & t1.bitfield.word) | |
2209 | && !(t0.bitfield.dword & t1.bitfield.dword) | |
10c17abd JB |
2210 | && !(t0.bitfield.qword & t1.bitfield.qword) |
2211 | && !(t0.bitfield.xmmword & t1.bitfield.xmmword) | |
2212 | && !(t0.bitfield.ymmword & t1.bitfield.ymmword) | |
2213 | && !(t0.bitfield.zmmword & t1.bitfield.zmmword)) | |
891edac4 L |
2214 | return 1; |
2215 | ||
a65babc9 | 2216 | i.error = register_type_mismatch; |
891edac4 L |
2217 | |
2218 | return 0; | |
40fb9820 L |
2219 | } |
2220 | ||
4c692bc7 JB |
2221 | static INLINE unsigned int |
2222 | register_number (const reg_entry *r) | |
2223 | { | |
2224 | unsigned int nr = r->reg_num; | |
2225 | ||
2226 | if (r->reg_flags & RegRex) | |
2227 | nr += 8; | |
2228 | ||
200cbe0f L |
2229 | if (r->reg_flags & RegVRex) |
2230 | nr += 16; | |
2231 | ||
4c692bc7 JB |
2232 | return nr; |
2233 | } | |
2234 | ||
252b5132 | 2235 | static INLINE unsigned int |
40fb9820 | 2236 | mode_from_disp_size (i386_operand_type t) |
252b5132 | 2237 | { |
b5014f7a | 2238 | if (t.bitfield.disp8) |
40fb9820 L |
2239 | return 1; |
2240 | else if (t.bitfield.disp16 | |
2241 | || t.bitfield.disp32 | |
2242 | || t.bitfield.disp32s) | |
2243 | return 2; | |
2244 | else | |
2245 | return 0; | |
252b5132 RH |
2246 | } |
2247 | ||
2248 | static INLINE int | |
65879393 | 2249 | fits_in_signed_byte (addressT num) |
252b5132 | 2250 | { |
65879393 | 2251 | return num + 0x80 <= 0xff; |
47926f60 | 2252 | } |
252b5132 RH |
2253 | |
2254 | static INLINE int | |
65879393 | 2255 | fits_in_unsigned_byte (addressT num) |
252b5132 | 2256 | { |
65879393 | 2257 | return num <= 0xff; |
47926f60 | 2258 | } |
252b5132 RH |
2259 | |
2260 | static INLINE int | |
65879393 | 2261 | fits_in_unsigned_word (addressT num) |
252b5132 | 2262 | { |
65879393 | 2263 | return num <= 0xffff; |
47926f60 | 2264 | } |
252b5132 RH |
2265 | |
2266 | static INLINE int | |
65879393 | 2267 | fits_in_signed_word (addressT num) |
252b5132 | 2268 | { |
65879393 | 2269 | return num + 0x8000 <= 0xffff; |
47926f60 | 2270 | } |
2a962e6d | 2271 | |
3e73aa7c | 2272 | static INLINE int |
65879393 | 2273 | fits_in_signed_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2274 | { |
2275 | #ifndef BFD64 | |
2276 | return 1; | |
2277 | #else | |
65879393 | 2278 | return num + 0x80000000 <= 0xffffffff; |
3e73aa7c JH |
2279 | #endif |
2280 | } /* fits_in_signed_long() */ | |
2a962e6d | 2281 | |
3e73aa7c | 2282 | static INLINE int |
65879393 | 2283 | fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2284 | { |
2285 | #ifndef BFD64 | |
2286 | return 1; | |
2287 | #else | |
65879393 | 2288 | return num <= 0xffffffff; |
3e73aa7c JH |
2289 | #endif |
2290 | } /* fits_in_unsigned_long() */ | |
252b5132 | 2291 | |
43234a1e | 2292 | static INLINE int |
b5014f7a | 2293 | fits_in_disp8 (offsetT num) |
43234a1e L |
2294 | { |
2295 | int shift = i.memshift; | |
2296 | unsigned int mask; | |
2297 | ||
2298 | if (shift == -1) | |
2299 | abort (); | |
2300 | ||
2301 | mask = (1 << shift) - 1; | |
2302 | ||
2303 | /* Return 0 if NUM isn't properly aligned. */ | |
2304 | if ((num & mask)) | |
2305 | return 0; | |
2306 | ||
2307 | /* Check if NUM will fit in 8bit after shift. */ | |
2308 | return fits_in_signed_byte (num >> shift); | |
2309 | } | |
2310 | ||
a683cc34 SP |
2311 | static INLINE int |
2312 | fits_in_imm4 (offsetT num) | |
2313 | { | |
2314 | return (num & 0xf) == num; | |
2315 | } | |
2316 | ||
40fb9820 | 2317 | static i386_operand_type |
e3bb37b5 | 2318 | smallest_imm_type (offsetT num) |
252b5132 | 2319 | { |
40fb9820 | 2320 | i386_operand_type t; |
7ab9ffdd | 2321 | |
0dfbf9d7 | 2322 | operand_type_set (&t, 0); |
40fb9820 L |
2323 | t.bitfield.imm64 = 1; |
2324 | ||
2325 | if (cpu_arch_tune != PROCESSOR_I486 && num == 1) | |
e413e4e9 AM |
2326 | { |
2327 | /* This code is disabled on the 486 because all the Imm1 forms | |
2328 | in the opcode table are slower on the i486. They're the | |
2329 | versions with the implicitly specified single-position | |
2330 | displacement, which has another syntax if you really want to | |
2331 | use that form. */ | |
40fb9820 L |
2332 | t.bitfield.imm1 = 1; |
2333 | t.bitfield.imm8 = 1; | |
2334 | t.bitfield.imm8s = 1; | |
2335 | t.bitfield.imm16 = 1; | |
2336 | t.bitfield.imm32 = 1; | |
2337 | t.bitfield.imm32s = 1; | |
2338 | } | |
2339 | else if (fits_in_signed_byte (num)) | |
2340 | { | |
2341 | t.bitfield.imm8 = 1; | |
2342 | t.bitfield.imm8s = 1; | |
2343 | t.bitfield.imm16 = 1; | |
2344 | t.bitfield.imm32 = 1; | |
2345 | t.bitfield.imm32s = 1; | |
2346 | } | |
2347 | else if (fits_in_unsigned_byte (num)) | |
2348 | { | |
2349 | t.bitfield.imm8 = 1; | |
2350 | t.bitfield.imm16 = 1; | |
2351 | t.bitfield.imm32 = 1; | |
2352 | t.bitfield.imm32s = 1; | |
2353 | } | |
2354 | else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
2355 | { | |
2356 | t.bitfield.imm16 = 1; | |
2357 | t.bitfield.imm32 = 1; | |
2358 | t.bitfield.imm32s = 1; | |
2359 | } | |
2360 | else if (fits_in_signed_long (num)) | |
2361 | { | |
2362 | t.bitfield.imm32 = 1; | |
2363 | t.bitfield.imm32s = 1; | |
2364 | } | |
2365 | else if (fits_in_unsigned_long (num)) | |
2366 | t.bitfield.imm32 = 1; | |
2367 | ||
2368 | return t; | |
47926f60 | 2369 | } |
252b5132 | 2370 | |
847f7ad4 | 2371 | static offsetT |
e3bb37b5 | 2372 | offset_in_range (offsetT val, int size) |
847f7ad4 | 2373 | { |
508866be | 2374 | addressT mask; |
ba2adb93 | 2375 | |
847f7ad4 AM |
2376 | switch (size) |
2377 | { | |
508866be L |
2378 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
2379 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 2380 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
3e73aa7c JH |
2381 | #ifdef BFD64 |
2382 | case 8: mask = ((addressT) 2 << 63) - 1; break; | |
2383 | #endif | |
47926f60 | 2384 | default: abort (); |
847f7ad4 AM |
2385 | } |
2386 | ||
9de868bf L |
2387 | #ifdef BFD64 |
2388 | /* If BFD64, sign extend val for 32bit address mode. */ | |
2389 | if (flag_code != CODE_64BIT | |
2390 | || i.prefix[ADDR_PREFIX]) | |
3e73aa7c JH |
2391 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) |
2392 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
fa289fb8 | 2393 | #endif |
ba2adb93 | 2394 | |
47926f60 | 2395 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
847f7ad4 AM |
2396 | { |
2397 | char buf1[40], buf2[40]; | |
2398 | ||
2399 | sprint_value (buf1, val); | |
2400 | sprint_value (buf2, val & mask); | |
2401 | as_warn (_("%s shortened to %s"), buf1, buf2); | |
2402 | } | |
2403 | return val & mask; | |
2404 | } | |
2405 | ||
c32fa91d L |
2406 | enum PREFIX_GROUP |
2407 | { | |
2408 | PREFIX_EXIST = 0, | |
2409 | PREFIX_LOCK, | |
2410 | PREFIX_REP, | |
04ef582a | 2411 | PREFIX_DS, |
c32fa91d L |
2412 | PREFIX_OTHER |
2413 | }; | |
2414 | ||
2415 | /* Returns | |
2416 | a. PREFIX_EXIST if attempting to add a prefix where one from the | |
2417 | same class already exists. | |
2418 | b. PREFIX_LOCK if lock prefix is added. | |
2419 | c. PREFIX_REP if rep/repne prefix is added. | |
04ef582a L |
2420 | d. PREFIX_DS if ds prefix is added. |
2421 | e. PREFIX_OTHER if other prefix is added. | |
c32fa91d L |
2422 | */ |
2423 | ||
2424 | static enum PREFIX_GROUP | |
e3bb37b5 | 2425 | add_prefix (unsigned int prefix) |
252b5132 | 2426 | { |
c32fa91d | 2427 | enum PREFIX_GROUP ret = PREFIX_OTHER; |
b1905489 | 2428 | unsigned int q; |
252b5132 | 2429 | |
29b0f896 AM |
2430 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
2431 | && flag_code == CODE_64BIT) | |
b1905489 | 2432 | { |
161a04f6 | 2433 | if ((i.prefix[REX_PREFIX] & prefix & REX_W) |
44846f29 JB |
2434 | || (i.prefix[REX_PREFIX] & prefix & REX_R) |
2435 | || (i.prefix[REX_PREFIX] & prefix & REX_X) | |
2436 | || (i.prefix[REX_PREFIX] & prefix & REX_B)) | |
c32fa91d | 2437 | ret = PREFIX_EXIST; |
b1905489 JB |
2438 | q = REX_PREFIX; |
2439 | } | |
3e73aa7c | 2440 | else |
b1905489 JB |
2441 | { |
2442 | switch (prefix) | |
2443 | { | |
2444 | default: | |
2445 | abort (); | |
2446 | ||
b1905489 | 2447 | case DS_PREFIX_OPCODE: |
04ef582a L |
2448 | ret = PREFIX_DS; |
2449 | /* Fall through. */ | |
2450 | case CS_PREFIX_OPCODE: | |
b1905489 JB |
2451 | case ES_PREFIX_OPCODE: |
2452 | case FS_PREFIX_OPCODE: | |
2453 | case GS_PREFIX_OPCODE: | |
2454 | case SS_PREFIX_OPCODE: | |
2455 | q = SEG_PREFIX; | |
2456 | break; | |
2457 | ||
2458 | case REPNE_PREFIX_OPCODE: | |
2459 | case REPE_PREFIX_OPCODE: | |
c32fa91d L |
2460 | q = REP_PREFIX; |
2461 | ret = PREFIX_REP; | |
2462 | break; | |
2463 | ||
b1905489 | 2464 | case LOCK_PREFIX_OPCODE: |
c32fa91d L |
2465 | q = LOCK_PREFIX; |
2466 | ret = PREFIX_LOCK; | |
b1905489 JB |
2467 | break; |
2468 | ||
2469 | case FWAIT_OPCODE: | |
2470 | q = WAIT_PREFIX; | |
2471 | break; | |
2472 | ||
2473 | case ADDR_PREFIX_OPCODE: | |
2474 | q = ADDR_PREFIX; | |
2475 | break; | |
2476 | ||
2477 | case DATA_PREFIX_OPCODE: | |
2478 | q = DATA_PREFIX; | |
2479 | break; | |
2480 | } | |
2481 | if (i.prefix[q] != 0) | |
c32fa91d | 2482 | ret = PREFIX_EXIST; |
b1905489 | 2483 | } |
252b5132 | 2484 | |
b1905489 | 2485 | if (ret) |
252b5132 | 2486 | { |
b1905489 JB |
2487 | if (!i.prefix[q]) |
2488 | ++i.prefixes; | |
2489 | i.prefix[q] |= prefix; | |
252b5132 | 2490 | } |
b1905489 JB |
2491 | else |
2492 | as_bad (_("same type of prefix used twice")); | |
252b5132 | 2493 | |
252b5132 RH |
2494 | return ret; |
2495 | } | |
2496 | ||
2497 | static void | |
78f12dd3 | 2498 | update_code_flag (int value, int check) |
eecb386c | 2499 | { |
78f12dd3 L |
2500 | PRINTF_LIKE ((*as_error)); |
2501 | ||
1e9cc1c2 | 2502 | flag_code = (enum flag_code) value; |
40fb9820 L |
2503 | if (flag_code == CODE_64BIT) |
2504 | { | |
2505 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2506 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
40fb9820 L |
2507 | } |
2508 | else | |
2509 | { | |
2510 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2511 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
40fb9820 L |
2512 | } |
2513 | if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm ) | |
3e73aa7c | 2514 | { |
78f12dd3 L |
2515 | if (check) |
2516 | as_error = as_fatal; | |
2517 | else | |
2518 | as_error = as_bad; | |
2519 | (*as_error) (_("64bit mode not supported on `%s'."), | |
2520 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2521 | } |
40fb9820 | 2522 | if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) |
3e73aa7c | 2523 | { |
78f12dd3 L |
2524 | if (check) |
2525 | as_error = as_fatal; | |
2526 | else | |
2527 | as_error = as_bad; | |
2528 | (*as_error) (_("32bit mode not supported on `%s'."), | |
2529 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2530 | } |
eecb386c AM |
2531 | stackop_size = '\0'; |
2532 | } | |
2533 | ||
78f12dd3 L |
2534 | static void |
2535 | set_code_flag (int value) | |
2536 | { | |
2537 | update_code_flag (value, 0); | |
2538 | } | |
2539 | ||
eecb386c | 2540 | static void |
e3bb37b5 | 2541 | set_16bit_gcc_code_flag (int new_code_flag) |
252b5132 | 2542 | { |
1e9cc1c2 | 2543 | flag_code = (enum flag_code) new_code_flag; |
40fb9820 L |
2544 | if (flag_code != CODE_16BIT) |
2545 | abort (); | |
2546 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2547 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
9306ca4a | 2548 | stackop_size = LONG_MNEM_SUFFIX; |
252b5132 RH |
2549 | } |
2550 | ||
2551 | static void | |
e3bb37b5 | 2552 | set_intel_syntax (int syntax_flag) |
252b5132 RH |
2553 | { |
2554 | /* Find out if register prefixing is specified. */ | |
2555 | int ask_naked_reg = 0; | |
2556 | ||
2557 | SKIP_WHITESPACE (); | |
29b0f896 | 2558 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
252b5132 | 2559 | { |
d02603dc NC |
2560 | char *string; |
2561 | int e = get_symbol_name (&string); | |
252b5132 | 2562 | |
47926f60 | 2563 | if (strcmp (string, "prefix") == 0) |
252b5132 | 2564 | ask_naked_reg = 1; |
47926f60 | 2565 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
2566 | ask_naked_reg = -1; |
2567 | else | |
d0b47220 | 2568 | as_bad (_("bad argument to syntax directive.")); |
d02603dc | 2569 | (void) restore_line_pointer (e); |
252b5132 RH |
2570 | } |
2571 | demand_empty_rest_of_line (); | |
c3332e24 | 2572 | |
252b5132 RH |
2573 | intel_syntax = syntax_flag; |
2574 | ||
2575 | if (ask_naked_reg == 0) | |
f86103b7 AM |
2576 | allow_naked_reg = (intel_syntax |
2577 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); | |
252b5132 RH |
2578 | else |
2579 | allow_naked_reg = (ask_naked_reg < 0); | |
9306ca4a | 2580 | |
ee86248c | 2581 | expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0); |
7ab9ffdd | 2582 | |
e4a3b5a4 | 2583 | identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; |
9306ca4a | 2584 | identifier_chars['$'] = intel_syntax ? '$' : 0; |
e4a3b5a4 | 2585 | register_prefix = allow_naked_reg ? "" : "%"; |
252b5132 RH |
2586 | } |
2587 | ||
1efbbeb4 L |
2588 | static void |
2589 | set_intel_mnemonic (int mnemonic_flag) | |
2590 | { | |
e1d4d893 | 2591 | intel_mnemonic = mnemonic_flag; |
1efbbeb4 L |
2592 | } |
2593 | ||
db51cc60 L |
2594 | static void |
2595 | set_allow_index_reg (int flag) | |
2596 | { | |
2597 | allow_index_reg = flag; | |
2598 | } | |
2599 | ||
cb19c032 | 2600 | static void |
7bab8ab5 | 2601 | set_check (int what) |
cb19c032 | 2602 | { |
7bab8ab5 JB |
2603 | enum check_kind *kind; |
2604 | const char *str; | |
2605 | ||
2606 | if (what) | |
2607 | { | |
2608 | kind = &operand_check; | |
2609 | str = "operand"; | |
2610 | } | |
2611 | else | |
2612 | { | |
2613 | kind = &sse_check; | |
2614 | str = "sse"; | |
2615 | } | |
2616 | ||
cb19c032 L |
2617 | SKIP_WHITESPACE (); |
2618 | ||
2619 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
2620 | { | |
d02603dc NC |
2621 | char *string; |
2622 | int e = get_symbol_name (&string); | |
cb19c032 L |
2623 | |
2624 | if (strcmp (string, "none") == 0) | |
7bab8ab5 | 2625 | *kind = check_none; |
cb19c032 | 2626 | else if (strcmp (string, "warning") == 0) |
7bab8ab5 | 2627 | *kind = check_warning; |
cb19c032 | 2628 | else if (strcmp (string, "error") == 0) |
7bab8ab5 | 2629 | *kind = check_error; |
cb19c032 | 2630 | else |
7bab8ab5 | 2631 | as_bad (_("bad argument to %s_check directive."), str); |
d02603dc | 2632 | (void) restore_line_pointer (e); |
cb19c032 L |
2633 | } |
2634 | else | |
7bab8ab5 | 2635 | as_bad (_("missing argument for %s_check directive"), str); |
cb19c032 L |
2636 | |
2637 | demand_empty_rest_of_line (); | |
2638 | } | |
2639 | ||
8a9036a4 L |
2640 | static void |
2641 | check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED, | |
1e9cc1c2 | 2642 | i386_cpu_flags new_flag ATTRIBUTE_UNUSED) |
8a9036a4 L |
2643 | { |
2644 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2645 | static const char *arch; | |
2646 | ||
2647 | /* Intel LIOM is only supported on ELF. */ | |
2648 | if (!IS_ELF) | |
2649 | return; | |
2650 | ||
2651 | if (!arch) | |
2652 | { | |
2653 | /* Use cpu_arch_name if it is set in md_parse_option. Otherwise | |
2654 | use default_arch. */ | |
2655 | arch = cpu_arch_name; | |
2656 | if (!arch) | |
2657 | arch = default_arch; | |
2658 | } | |
2659 | ||
81486035 L |
2660 | /* If we are targeting Intel MCU, we must enable it. */ |
2661 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU | |
2662 | || new_flag.bitfield.cpuiamcu) | |
2663 | return; | |
2664 | ||
3632d14b | 2665 | /* If we are targeting Intel L1OM, we must enable it. */ |
8a9036a4 | 2666 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM |
1e9cc1c2 | 2667 | || new_flag.bitfield.cpul1om) |
8a9036a4 | 2668 | return; |
76ba9986 | 2669 | |
7a9068fe L |
2670 | /* If we are targeting Intel K1OM, we must enable it. */ |
2671 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM | |
2672 | || new_flag.bitfield.cpuk1om) | |
2673 | return; | |
2674 | ||
8a9036a4 L |
2675 | as_bad (_("`%s' is not supported on `%s'"), name, arch); |
2676 | #endif | |
2677 | } | |
2678 | ||
e413e4e9 | 2679 | static void |
e3bb37b5 | 2680 | set_cpu_arch (int dummy ATTRIBUTE_UNUSED) |
e413e4e9 | 2681 | { |
47926f60 | 2682 | SKIP_WHITESPACE (); |
e413e4e9 | 2683 | |
29b0f896 | 2684 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
e413e4e9 | 2685 | { |
d02603dc NC |
2686 | char *string; |
2687 | int e = get_symbol_name (&string); | |
91d6fa6a | 2688 | unsigned int j; |
40fb9820 | 2689 | i386_cpu_flags flags; |
e413e4e9 | 2690 | |
91d6fa6a | 2691 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
e413e4e9 | 2692 | { |
91d6fa6a | 2693 | if (strcmp (string, cpu_arch[j].name) == 0) |
e413e4e9 | 2694 | { |
91d6fa6a | 2695 | check_cpu_arch_compatible (string, cpu_arch[j].flags); |
8a9036a4 | 2696 | |
5c6af06e JB |
2697 | if (*string != '.') |
2698 | { | |
91d6fa6a | 2699 | cpu_arch_name = cpu_arch[j].name; |
5c6af06e | 2700 | cpu_sub_arch_name = NULL; |
91d6fa6a | 2701 | cpu_arch_flags = cpu_arch[j].flags; |
40fb9820 L |
2702 | if (flag_code == CODE_64BIT) |
2703 | { | |
2704 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2705 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
2706 | } | |
2707 | else | |
2708 | { | |
2709 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2710 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
2711 | } | |
91d6fa6a NC |
2712 | cpu_arch_isa = cpu_arch[j].type; |
2713 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
ccc9c027 L |
2714 | if (!cpu_arch_tune_set) |
2715 | { | |
2716 | cpu_arch_tune = cpu_arch_isa; | |
2717 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
2718 | } | |
5c6af06e JB |
2719 | break; |
2720 | } | |
40fb9820 | 2721 | |
293f5f65 L |
2722 | flags = cpu_flags_or (cpu_arch_flags, |
2723 | cpu_arch[j].flags); | |
81486035 | 2724 | |
5b64d091 | 2725 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
5c6af06e | 2726 | { |
6305a203 L |
2727 | if (cpu_sub_arch_name) |
2728 | { | |
2729 | char *name = cpu_sub_arch_name; | |
2730 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 2731 | cpu_arch[j].name, |
1bf57e9f | 2732 | (const char *) NULL); |
6305a203 L |
2733 | free (name); |
2734 | } | |
2735 | else | |
91d6fa6a | 2736 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
40fb9820 | 2737 | cpu_arch_flags = flags; |
a586129e | 2738 | cpu_arch_isa_flags = flags; |
5c6af06e | 2739 | } |
0089dace L |
2740 | else |
2741 | cpu_arch_isa_flags | |
2742 | = cpu_flags_or (cpu_arch_isa_flags, | |
2743 | cpu_arch[j].flags); | |
d02603dc | 2744 | (void) restore_line_pointer (e); |
5c6af06e JB |
2745 | demand_empty_rest_of_line (); |
2746 | return; | |
e413e4e9 AM |
2747 | } |
2748 | } | |
293f5f65 L |
2749 | |
2750 | if (*string == '.' && j >= ARRAY_SIZE (cpu_arch)) | |
2751 | { | |
33eaf5de | 2752 | /* Disable an ISA extension. */ |
293f5f65 L |
2753 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
2754 | if (strcmp (string + 1, cpu_noarch [j].name) == 0) | |
2755 | { | |
2756 | flags = cpu_flags_and_not (cpu_arch_flags, | |
2757 | cpu_noarch[j].flags); | |
2758 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
2759 | { | |
2760 | if (cpu_sub_arch_name) | |
2761 | { | |
2762 | char *name = cpu_sub_arch_name; | |
2763 | cpu_sub_arch_name = concat (name, string, | |
2764 | (const char *) NULL); | |
2765 | free (name); | |
2766 | } | |
2767 | else | |
2768 | cpu_sub_arch_name = xstrdup (string); | |
2769 | cpu_arch_flags = flags; | |
2770 | cpu_arch_isa_flags = flags; | |
2771 | } | |
2772 | (void) restore_line_pointer (e); | |
2773 | demand_empty_rest_of_line (); | |
2774 | return; | |
2775 | } | |
2776 | ||
2777 | j = ARRAY_SIZE (cpu_arch); | |
2778 | } | |
2779 | ||
91d6fa6a | 2780 | if (j >= ARRAY_SIZE (cpu_arch)) |
e413e4e9 AM |
2781 | as_bad (_("no such architecture: `%s'"), string); |
2782 | ||
2783 | *input_line_pointer = e; | |
2784 | } | |
2785 | else | |
2786 | as_bad (_("missing cpu architecture")); | |
2787 | ||
fddf5b5b AM |
2788 | no_cond_jump_promotion = 0; |
2789 | if (*input_line_pointer == ',' | |
29b0f896 | 2790 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
fddf5b5b | 2791 | { |
d02603dc NC |
2792 | char *string; |
2793 | char e; | |
2794 | ||
2795 | ++input_line_pointer; | |
2796 | e = get_symbol_name (&string); | |
fddf5b5b AM |
2797 | |
2798 | if (strcmp (string, "nojumps") == 0) | |
2799 | no_cond_jump_promotion = 1; | |
2800 | else if (strcmp (string, "jumps") == 0) | |
2801 | ; | |
2802 | else | |
2803 | as_bad (_("no such architecture modifier: `%s'"), string); | |
2804 | ||
d02603dc | 2805 | (void) restore_line_pointer (e); |
fddf5b5b AM |
2806 | } |
2807 | ||
e413e4e9 AM |
2808 | demand_empty_rest_of_line (); |
2809 | } | |
2810 | ||
8a9036a4 L |
2811 | enum bfd_architecture |
2812 | i386_arch (void) | |
2813 | { | |
3632d14b | 2814 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 L |
2815 | { |
2816 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2817 | || flag_code != CODE_64BIT) | |
2818 | as_fatal (_("Intel L1OM is 64bit ELF only")); | |
2819 | return bfd_arch_l1om; | |
2820 | } | |
7a9068fe L |
2821 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2822 | { | |
2823 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2824 | || flag_code != CODE_64BIT) | |
2825 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2826 | return bfd_arch_k1om; | |
2827 | } | |
81486035 L |
2828 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
2829 | { | |
2830 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2831 | || flag_code == CODE_64BIT) | |
2832 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2833 | return bfd_arch_iamcu; | |
2834 | } | |
8a9036a4 L |
2835 | else |
2836 | return bfd_arch_i386; | |
2837 | } | |
2838 | ||
b9d79e03 | 2839 | unsigned long |
7016a5d5 | 2840 | i386_mach (void) |
b9d79e03 | 2841 | { |
351f65ca | 2842 | if (!strncmp (default_arch, "x86_64", 6)) |
8a9036a4 | 2843 | { |
3632d14b | 2844 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 2845 | { |
351f65ca L |
2846 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour |
2847 | || default_arch[6] != '\0') | |
8a9036a4 L |
2848 | as_fatal (_("Intel L1OM is 64bit ELF only")); |
2849 | return bfd_mach_l1om; | |
2850 | } | |
7a9068fe L |
2851 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2852 | { | |
2853 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2854 | || default_arch[6] != '\0') | |
2855 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2856 | return bfd_mach_k1om; | |
2857 | } | |
351f65ca | 2858 | else if (default_arch[6] == '\0') |
8a9036a4 | 2859 | return bfd_mach_x86_64; |
351f65ca L |
2860 | else |
2861 | return bfd_mach_x64_32; | |
8a9036a4 | 2862 | } |
5197d474 L |
2863 | else if (!strcmp (default_arch, "i386") |
2864 | || !strcmp (default_arch, "iamcu")) | |
81486035 L |
2865 | { |
2866 | if (cpu_arch_isa == PROCESSOR_IAMCU) | |
2867 | { | |
2868 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
2869 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2870 | return bfd_mach_i386_iamcu; | |
2871 | } | |
2872 | else | |
2873 | return bfd_mach_i386_i386; | |
2874 | } | |
b9d79e03 | 2875 | else |
2b5d6a91 | 2876 | as_fatal (_("unknown architecture")); |
b9d79e03 | 2877 | } |
b9d79e03 | 2878 | \f |
252b5132 | 2879 | void |
7016a5d5 | 2880 | md_begin (void) |
252b5132 RH |
2881 | { |
2882 | const char *hash_err; | |
2883 | ||
86fa6981 L |
2884 | /* Support pseudo prefixes like {disp32}. */ |
2885 | lex_type ['{'] = LEX_BEGIN_NAME; | |
2886 | ||
47926f60 | 2887 | /* Initialize op_hash hash table. */ |
252b5132 RH |
2888 | op_hash = hash_new (); |
2889 | ||
2890 | { | |
d3ce72d0 | 2891 | const insn_template *optab; |
29b0f896 | 2892 | templates *core_optab; |
252b5132 | 2893 | |
47926f60 KH |
2894 | /* Setup for loop. */ |
2895 | optab = i386_optab; | |
add39d23 | 2896 | core_optab = XNEW (templates); |
252b5132 RH |
2897 | core_optab->start = optab; |
2898 | ||
2899 | while (1) | |
2900 | { | |
2901 | ++optab; | |
2902 | if (optab->name == NULL | |
2903 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
2904 | { | |
2905 | /* different name --> ship out current template list; | |
47926f60 | 2906 | add to hash table; & begin anew. */ |
252b5132 RH |
2907 | core_optab->end = optab; |
2908 | hash_err = hash_insert (op_hash, | |
2909 | (optab - 1)->name, | |
5a49b8ac | 2910 | (void *) core_optab); |
252b5132 RH |
2911 | if (hash_err) |
2912 | { | |
b37df7c4 | 2913 | as_fatal (_("can't hash %s: %s"), |
252b5132 RH |
2914 | (optab - 1)->name, |
2915 | hash_err); | |
2916 | } | |
2917 | if (optab->name == NULL) | |
2918 | break; | |
add39d23 | 2919 | core_optab = XNEW (templates); |
252b5132 RH |
2920 | core_optab->start = optab; |
2921 | } | |
2922 | } | |
2923 | } | |
2924 | ||
47926f60 | 2925 | /* Initialize reg_hash hash table. */ |
252b5132 RH |
2926 | reg_hash = hash_new (); |
2927 | { | |
29b0f896 | 2928 | const reg_entry *regtab; |
c3fe08fa | 2929 | unsigned int regtab_size = i386_regtab_size; |
252b5132 | 2930 | |
c3fe08fa | 2931 | for (regtab = i386_regtab; regtab_size--; regtab++) |
252b5132 | 2932 | { |
5a49b8ac | 2933 | hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab); |
252b5132 | 2934 | if (hash_err) |
b37df7c4 | 2935 | as_fatal (_("can't hash %s: %s"), |
3e73aa7c JH |
2936 | regtab->reg_name, |
2937 | hash_err); | |
252b5132 RH |
2938 | } |
2939 | } | |
2940 | ||
47926f60 | 2941 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 | 2942 | { |
29b0f896 AM |
2943 | int c; |
2944 | char *p; | |
252b5132 RH |
2945 | |
2946 | for (c = 0; c < 256; c++) | |
2947 | { | |
3882b010 | 2948 | if (ISDIGIT (c)) |
252b5132 RH |
2949 | { |
2950 | digit_chars[c] = c; | |
2951 | mnemonic_chars[c] = c; | |
2952 | register_chars[c] = c; | |
2953 | operand_chars[c] = c; | |
2954 | } | |
3882b010 | 2955 | else if (ISLOWER (c)) |
252b5132 RH |
2956 | { |
2957 | mnemonic_chars[c] = c; | |
2958 | register_chars[c] = c; | |
2959 | operand_chars[c] = c; | |
2960 | } | |
3882b010 | 2961 | else if (ISUPPER (c)) |
252b5132 | 2962 | { |
3882b010 | 2963 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
2964 | register_chars[c] = mnemonic_chars[c]; |
2965 | operand_chars[c] = c; | |
2966 | } | |
43234a1e | 2967 | else if (c == '{' || c == '}') |
86fa6981 L |
2968 | { |
2969 | mnemonic_chars[c] = c; | |
2970 | operand_chars[c] = c; | |
2971 | } | |
252b5132 | 2972 | |
3882b010 | 2973 | if (ISALPHA (c) || ISDIGIT (c)) |
252b5132 RH |
2974 | identifier_chars[c] = c; |
2975 | else if (c >= 128) | |
2976 | { | |
2977 | identifier_chars[c] = c; | |
2978 | operand_chars[c] = c; | |
2979 | } | |
2980 | } | |
2981 | ||
2982 | #ifdef LEX_AT | |
2983 | identifier_chars['@'] = '@'; | |
32137342 NC |
2984 | #endif |
2985 | #ifdef LEX_QM | |
2986 | identifier_chars['?'] = '?'; | |
2987 | operand_chars['?'] = '?'; | |
252b5132 | 2988 | #endif |
252b5132 | 2989 | digit_chars['-'] = '-'; |
c0f3af97 | 2990 | mnemonic_chars['_'] = '_'; |
791fe849 | 2991 | mnemonic_chars['-'] = '-'; |
0003779b | 2992 | mnemonic_chars['.'] = '.'; |
252b5132 RH |
2993 | identifier_chars['_'] = '_'; |
2994 | identifier_chars['.'] = '.'; | |
2995 | ||
2996 | for (p = operand_special_chars; *p != '\0'; p++) | |
2997 | operand_chars[(unsigned char) *p] = *p; | |
2998 | } | |
2999 | ||
a4447b93 RH |
3000 | if (flag_code == CODE_64BIT) |
3001 | { | |
ca19b261 KT |
3002 | #if defined (OBJ_COFF) && defined (TE_PE) |
3003 | x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour | |
3004 | ? 32 : 16); | |
3005 | #else | |
a4447b93 | 3006 | x86_dwarf2_return_column = 16; |
ca19b261 | 3007 | #endif |
61ff971f | 3008 | x86_cie_data_alignment = -8; |
a4447b93 RH |
3009 | } |
3010 | else | |
3011 | { | |
3012 | x86_dwarf2_return_column = 8; | |
3013 | x86_cie_data_alignment = -4; | |
3014 | } | |
252b5132 RH |
3015 | } |
3016 | ||
3017 | void | |
e3bb37b5 | 3018 | i386_print_statistics (FILE *file) |
252b5132 RH |
3019 | { |
3020 | hash_print_statistics (file, "i386 opcode", op_hash); | |
3021 | hash_print_statistics (file, "i386 register", reg_hash); | |
3022 | } | |
3023 | \f | |
252b5132 RH |
3024 | #ifdef DEBUG386 |
3025 | ||
ce8a8b2f | 3026 | /* Debugging routines for md_assemble. */ |
d3ce72d0 | 3027 | static void pte (insn_template *); |
40fb9820 | 3028 | static void pt (i386_operand_type); |
e3bb37b5 L |
3029 | static void pe (expressionS *); |
3030 | static void ps (symbolS *); | |
252b5132 RH |
3031 | |
3032 | static void | |
2c703856 | 3033 | pi (const char *line, i386_insn *x) |
252b5132 | 3034 | { |
09137c09 | 3035 | unsigned int j; |
252b5132 RH |
3036 | |
3037 | fprintf (stdout, "%s: template ", line); | |
3038 | pte (&x->tm); | |
09f131f2 JH |
3039 | fprintf (stdout, " address: base %s index %s scale %x\n", |
3040 | x->base_reg ? x->base_reg->reg_name : "none", | |
3041 | x->index_reg ? x->index_reg->reg_name : "none", | |
3042 | x->log2_scale_factor); | |
3043 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 3044 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
3045 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
3046 | x->sib.base, x->sib.index, x->sib.scale); | |
3047 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
161a04f6 L |
3048 | (x->rex & REX_W) != 0, |
3049 | (x->rex & REX_R) != 0, | |
3050 | (x->rex & REX_X) != 0, | |
3051 | (x->rex & REX_B) != 0); | |
09137c09 | 3052 | for (j = 0; j < x->operands; j++) |
252b5132 | 3053 | { |
09137c09 SP |
3054 | fprintf (stdout, " #%d: ", j + 1); |
3055 | pt (x->types[j]); | |
252b5132 | 3056 | fprintf (stdout, "\n"); |
bab6aec1 | 3057 | if (x->types[j].bitfield.class == Reg |
3528c362 JB |
3058 | || x->types[j].bitfield.class == RegMMX |
3059 | || x->types[j].bitfield.class == RegSIMD | |
00cee14f | 3060 | || x->types[j].bitfield.class == SReg |
4a5c67ed JB |
3061 | || x->types[j].bitfield.class == RegCR |
3062 | || x->types[j].bitfield.class == RegDR | |
3063 | || x->types[j].bitfield.class == RegTR) | |
09137c09 SP |
3064 | fprintf (stdout, "%s\n", x->op[j].regs->reg_name); |
3065 | if (operand_type_check (x->types[j], imm)) | |
3066 | pe (x->op[j].imms); | |
3067 | if (operand_type_check (x->types[j], disp)) | |
3068 | pe (x->op[j].disps); | |
252b5132 RH |
3069 | } |
3070 | } | |
3071 | ||
3072 | static void | |
d3ce72d0 | 3073 | pte (insn_template *t) |
252b5132 | 3074 | { |
09137c09 | 3075 | unsigned int j; |
252b5132 | 3076 | fprintf (stdout, " %d operands ", t->operands); |
47926f60 | 3077 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
3078 | if (t->extension_opcode != None) |
3079 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
40fb9820 | 3080 | if (t->opcode_modifier.d) |
252b5132 | 3081 | fprintf (stdout, "D"); |
40fb9820 | 3082 | if (t->opcode_modifier.w) |
252b5132 RH |
3083 | fprintf (stdout, "W"); |
3084 | fprintf (stdout, "\n"); | |
09137c09 | 3085 | for (j = 0; j < t->operands; j++) |
252b5132 | 3086 | { |
09137c09 SP |
3087 | fprintf (stdout, " #%d type ", j + 1); |
3088 | pt (t->operand_types[j]); | |
252b5132 RH |
3089 | fprintf (stdout, "\n"); |
3090 | } | |
3091 | } | |
3092 | ||
3093 | static void | |
e3bb37b5 | 3094 | pe (expressionS *e) |
252b5132 | 3095 | { |
24eab124 | 3096 | fprintf (stdout, " operation %d\n", e->X_op); |
b77ad1d4 AM |
3097 | fprintf (stdout, " add_number %ld (%lx)\n", |
3098 | (long) e->X_add_number, (long) e->X_add_number); | |
252b5132 RH |
3099 | if (e->X_add_symbol) |
3100 | { | |
3101 | fprintf (stdout, " add_symbol "); | |
3102 | ps (e->X_add_symbol); | |
3103 | fprintf (stdout, "\n"); | |
3104 | } | |
3105 | if (e->X_op_symbol) | |
3106 | { | |
3107 | fprintf (stdout, " op_symbol "); | |
3108 | ps (e->X_op_symbol); | |
3109 | fprintf (stdout, "\n"); | |
3110 | } | |
3111 | } | |
3112 | ||
3113 | static void | |
e3bb37b5 | 3114 | ps (symbolS *s) |
252b5132 RH |
3115 | { |
3116 | fprintf (stdout, "%s type %s%s", | |
3117 | S_GET_NAME (s), | |
3118 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
3119 | segment_name (S_GET_SEGMENT (s))); | |
3120 | } | |
3121 | ||
7b81dfbb | 3122 | static struct type_name |
252b5132 | 3123 | { |
40fb9820 L |
3124 | i386_operand_type mask; |
3125 | const char *name; | |
252b5132 | 3126 | } |
7b81dfbb | 3127 | const type_names[] = |
252b5132 | 3128 | { |
40fb9820 L |
3129 | { OPERAND_TYPE_REG8, "r8" }, |
3130 | { OPERAND_TYPE_REG16, "r16" }, | |
3131 | { OPERAND_TYPE_REG32, "r32" }, | |
3132 | { OPERAND_TYPE_REG64, "r64" }, | |
2c703856 JB |
3133 | { OPERAND_TYPE_ACC8, "acc8" }, |
3134 | { OPERAND_TYPE_ACC16, "acc16" }, | |
3135 | { OPERAND_TYPE_ACC32, "acc32" }, | |
3136 | { OPERAND_TYPE_ACC64, "acc64" }, | |
40fb9820 L |
3137 | { OPERAND_TYPE_IMM8, "i8" }, |
3138 | { OPERAND_TYPE_IMM8, "i8s" }, | |
3139 | { OPERAND_TYPE_IMM16, "i16" }, | |
3140 | { OPERAND_TYPE_IMM32, "i32" }, | |
3141 | { OPERAND_TYPE_IMM32S, "i32s" }, | |
3142 | { OPERAND_TYPE_IMM64, "i64" }, | |
3143 | { OPERAND_TYPE_IMM1, "i1" }, | |
3144 | { OPERAND_TYPE_BASEINDEX, "BaseIndex" }, | |
3145 | { OPERAND_TYPE_DISP8, "d8" }, | |
3146 | { OPERAND_TYPE_DISP16, "d16" }, | |
3147 | { OPERAND_TYPE_DISP32, "d32" }, | |
3148 | { OPERAND_TYPE_DISP32S, "d32s" }, | |
3149 | { OPERAND_TYPE_DISP64, "d64" }, | |
3150 | { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" }, | |
3151 | { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" }, | |
3152 | { OPERAND_TYPE_CONTROL, "control reg" }, | |
3153 | { OPERAND_TYPE_TEST, "test reg" }, | |
3154 | { OPERAND_TYPE_DEBUG, "debug reg" }, | |
3155 | { OPERAND_TYPE_FLOATREG, "FReg" }, | |
3156 | { OPERAND_TYPE_FLOATACC, "FAcc" }, | |
21df382b | 3157 | { OPERAND_TYPE_SREG, "SReg" }, |
40fb9820 L |
3158 | { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" }, |
3159 | { OPERAND_TYPE_REGMMX, "rMMX" }, | |
3160 | { OPERAND_TYPE_REGXMM, "rXMM" }, | |
0349dc08 | 3161 | { OPERAND_TYPE_REGYMM, "rYMM" }, |
43234a1e L |
3162 | { OPERAND_TYPE_REGZMM, "rZMM" }, |
3163 | { OPERAND_TYPE_REGMASK, "Mask reg" }, | |
40fb9820 | 3164 | { OPERAND_TYPE_ESSEG, "es" }, |
252b5132 RH |
3165 | }; |
3166 | ||
3167 | static void | |
40fb9820 | 3168 | pt (i386_operand_type t) |
252b5132 | 3169 | { |
40fb9820 | 3170 | unsigned int j; |
c6fb90c8 | 3171 | i386_operand_type a; |
252b5132 | 3172 | |
40fb9820 | 3173 | for (j = 0; j < ARRAY_SIZE (type_names); j++) |
c6fb90c8 L |
3174 | { |
3175 | a = operand_type_and (t, type_names[j].mask); | |
2c703856 | 3176 | if (operand_type_equal (&a, &type_names[j].mask)) |
c6fb90c8 L |
3177 | fprintf (stdout, "%s, ", type_names[j].name); |
3178 | } | |
252b5132 RH |
3179 | fflush (stdout); |
3180 | } | |
3181 | ||
3182 | #endif /* DEBUG386 */ | |
3183 | \f | |
252b5132 | 3184 | static bfd_reloc_code_real_type |
3956db08 | 3185 | reloc (unsigned int size, |
64e74474 AM |
3186 | int pcrel, |
3187 | int sign, | |
3188 | bfd_reloc_code_real_type other) | |
252b5132 | 3189 | { |
47926f60 | 3190 | if (other != NO_RELOC) |
3956db08 | 3191 | { |
91d6fa6a | 3192 | reloc_howto_type *rel; |
3956db08 JB |
3193 | |
3194 | if (size == 8) | |
3195 | switch (other) | |
3196 | { | |
64e74474 AM |
3197 | case BFD_RELOC_X86_64_GOT32: |
3198 | return BFD_RELOC_X86_64_GOT64; | |
3199 | break; | |
553d1284 L |
3200 | case BFD_RELOC_X86_64_GOTPLT64: |
3201 | return BFD_RELOC_X86_64_GOTPLT64; | |
3202 | break; | |
64e74474 AM |
3203 | case BFD_RELOC_X86_64_PLTOFF64: |
3204 | return BFD_RELOC_X86_64_PLTOFF64; | |
3205 | break; | |
3206 | case BFD_RELOC_X86_64_GOTPC32: | |
3207 | other = BFD_RELOC_X86_64_GOTPC64; | |
3208 | break; | |
3209 | case BFD_RELOC_X86_64_GOTPCREL: | |
3210 | other = BFD_RELOC_X86_64_GOTPCREL64; | |
3211 | break; | |
3212 | case BFD_RELOC_X86_64_TPOFF32: | |
3213 | other = BFD_RELOC_X86_64_TPOFF64; | |
3214 | break; | |
3215 | case BFD_RELOC_X86_64_DTPOFF32: | |
3216 | other = BFD_RELOC_X86_64_DTPOFF64; | |
3217 | break; | |
3218 | default: | |
3219 | break; | |
3956db08 | 3220 | } |
e05278af | 3221 | |
8ce3d284 | 3222 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
3223 | if (other == BFD_RELOC_SIZE32) |
3224 | { | |
3225 | if (size == 8) | |
1ab668bf | 3226 | other = BFD_RELOC_SIZE64; |
8fd4256d | 3227 | if (pcrel) |
1ab668bf AM |
3228 | { |
3229 | as_bad (_("there are no pc-relative size relocations")); | |
3230 | return NO_RELOC; | |
3231 | } | |
8fd4256d | 3232 | } |
8ce3d284 | 3233 | #endif |
8fd4256d | 3234 | |
e05278af | 3235 | /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ |
f2d8a97c | 3236 | if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc)) |
e05278af JB |
3237 | sign = -1; |
3238 | ||
91d6fa6a NC |
3239 | rel = bfd_reloc_type_lookup (stdoutput, other); |
3240 | if (!rel) | |
3956db08 | 3241 | as_bad (_("unknown relocation (%u)"), other); |
91d6fa6a | 3242 | else if (size != bfd_get_reloc_size (rel)) |
3956db08 | 3243 | as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), |
91d6fa6a | 3244 | bfd_get_reloc_size (rel), |
3956db08 | 3245 | size); |
91d6fa6a | 3246 | else if (pcrel && !rel->pc_relative) |
3956db08 | 3247 | as_bad (_("non-pc-relative relocation for pc-relative field")); |
91d6fa6a | 3248 | else if ((rel->complain_on_overflow == complain_overflow_signed |
3956db08 | 3249 | && !sign) |
91d6fa6a | 3250 | || (rel->complain_on_overflow == complain_overflow_unsigned |
64e74474 | 3251 | && sign > 0)) |
3956db08 JB |
3252 | as_bad (_("relocated field and relocation type differ in signedness")); |
3253 | else | |
3254 | return other; | |
3255 | return NO_RELOC; | |
3256 | } | |
252b5132 RH |
3257 | |
3258 | if (pcrel) | |
3259 | { | |
3e73aa7c | 3260 | if (!sign) |
3956db08 | 3261 | as_bad (_("there are no unsigned pc-relative relocations")); |
252b5132 RH |
3262 | switch (size) |
3263 | { | |
3264 | case 1: return BFD_RELOC_8_PCREL; | |
3265 | case 2: return BFD_RELOC_16_PCREL; | |
d258b828 | 3266 | case 4: return BFD_RELOC_32_PCREL; |
d6ab8113 | 3267 | case 8: return BFD_RELOC_64_PCREL; |
252b5132 | 3268 | } |
3956db08 | 3269 | as_bad (_("cannot do %u byte pc-relative relocation"), size); |
252b5132 RH |
3270 | } |
3271 | else | |
3272 | { | |
3956db08 | 3273 | if (sign > 0) |
e5cb08ac | 3274 | switch (size) |
3e73aa7c JH |
3275 | { |
3276 | case 4: return BFD_RELOC_X86_64_32S; | |
3277 | } | |
3278 | else | |
3279 | switch (size) | |
3280 | { | |
3281 | case 1: return BFD_RELOC_8; | |
3282 | case 2: return BFD_RELOC_16; | |
3283 | case 4: return BFD_RELOC_32; | |
3284 | case 8: return BFD_RELOC_64; | |
3285 | } | |
3956db08 JB |
3286 | as_bad (_("cannot do %s %u byte relocation"), |
3287 | sign > 0 ? "signed" : "unsigned", size); | |
252b5132 RH |
3288 | } |
3289 | ||
0cc9e1d3 | 3290 | return NO_RELOC; |
252b5132 RH |
3291 | } |
3292 | ||
47926f60 KH |
3293 | /* Here we decide which fixups can be adjusted to make them relative to |
3294 | the beginning of the section instead of the symbol. Basically we need | |
3295 | to make sure that the dynamic relocations are done correctly, so in | |
3296 | some cases we force the original symbol to be used. */ | |
3297 | ||
252b5132 | 3298 | int |
e3bb37b5 | 3299 | tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) |
252b5132 | 3300 | { |
6d249963 | 3301 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 3302 | if (!IS_ELF) |
31312f95 AM |
3303 | return 1; |
3304 | ||
a161fe53 AM |
3305 | /* Don't adjust pc-relative references to merge sections in 64-bit |
3306 | mode. */ | |
3307 | if (use_rela_relocations | |
3308 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 | |
3309 | && fixP->fx_pcrel) | |
252b5132 | 3310 | return 0; |
31312f95 | 3311 | |
8d01d9a9 AJ |
3312 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
3313 | and changed later by validate_fix. */ | |
3314 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol | |
3315 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) | |
3316 | return 0; | |
3317 | ||
8fd4256d L |
3318 | /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol |
3319 | for size relocations. */ | |
3320 | if (fixP->fx_r_type == BFD_RELOC_SIZE32 | |
3321 | || fixP->fx_r_type == BFD_RELOC_SIZE64 | |
3322 | || fixP->fx_r_type == BFD_RELOC_386_GOTOFF | |
252b5132 RH |
3323 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 |
3324 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 | |
02a86693 | 3325 | || fixP->fx_r_type == BFD_RELOC_386_GOT32X |
13ae64f3 JJ |
3326 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
3327 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM | |
3328 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 | |
3329 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 | |
37e55690 JJ |
3330 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
3331 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE | |
13ae64f3 JJ |
3332 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
3333 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE | |
67a4f2b7 AO |
3334 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC |
3335 | || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL | |
3e73aa7c JH |
3336 | || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 |
3337 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 | |
80b3ee89 | 3338 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
56ceb5b5 L |
3339 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX |
3340 | || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX | |
bffbf940 JJ |
3341 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
3342 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD | |
3343 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 | |
d6ab8113 | 3344 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 |
bffbf940 JJ |
3345 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF |
3346 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 | |
d6ab8113 JB |
3347 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 |
3348 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 | |
67a4f2b7 AO |
3349 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
3350 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL | |
252b5132 RH |
3351 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
3352 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
3353 | return 0; | |
31312f95 | 3354 | #endif |
252b5132 RH |
3355 | return 1; |
3356 | } | |
252b5132 | 3357 | |
b4cac588 | 3358 | static int |
e3bb37b5 | 3359 | intel_float_operand (const char *mnemonic) |
252b5132 | 3360 | { |
9306ca4a JB |
3361 | /* Note that the value returned is meaningful only for opcodes with (memory) |
3362 | operands, hence the code here is free to improperly handle opcodes that | |
3363 | have no operands (for better performance and smaller code). */ | |
3364 | ||
3365 | if (mnemonic[0] != 'f') | |
3366 | return 0; /* non-math */ | |
3367 | ||
3368 | switch (mnemonic[1]) | |
3369 | { | |
3370 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and | |
3371 | the fs segment override prefix not currently handled because no | |
3372 | call path can make opcodes without operands get here */ | |
3373 | case 'i': | |
3374 | return 2 /* integer op */; | |
3375 | case 'l': | |
3376 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) | |
3377 | return 3; /* fldcw/fldenv */ | |
3378 | break; | |
3379 | case 'n': | |
3380 | if (mnemonic[2] != 'o' /* fnop */) | |
3381 | return 3; /* non-waiting control op */ | |
3382 | break; | |
3383 | case 'r': | |
3384 | if (mnemonic[2] == 's') | |
3385 | return 3; /* frstor/frstpm */ | |
3386 | break; | |
3387 | case 's': | |
3388 | if (mnemonic[2] == 'a') | |
3389 | return 3; /* fsave */ | |
3390 | if (mnemonic[2] == 't') | |
3391 | { | |
3392 | switch (mnemonic[3]) | |
3393 | { | |
3394 | case 'c': /* fstcw */ | |
3395 | case 'd': /* fstdw */ | |
3396 | case 'e': /* fstenv */ | |
3397 | case 's': /* fsts[gw] */ | |
3398 | return 3; | |
3399 | } | |
3400 | } | |
3401 | break; | |
3402 | case 'x': | |
3403 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') | |
3404 | return 0; /* fxsave/fxrstor are not really math ops */ | |
3405 | break; | |
3406 | } | |
252b5132 | 3407 | |
9306ca4a | 3408 | return 1; |
252b5132 RH |
3409 | } |
3410 | ||
c0f3af97 L |
3411 | /* Build the VEX prefix. */ |
3412 | ||
3413 | static void | |
d3ce72d0 | 3414 | build_vex_prefix (const insn_template *t) |
c0f3af97 L |
3415 | { |
3416 | unsigned int register_specifier; | |
3417 | unsigned int implied_prefix; | |
3418 | unsigned int vector_length; | |
03751133 | 3419 | unsigned int w; |
c0f3af97 L |
3420 | |
3421 | /* Check register specifier. */ | |
3422 | if (i.vex.register_specifier) | |
43234a1e L |
3423 | { |
3424 | register_specifier = | |
3425 | ~register_number (i.vex.register_specifier) & 0xf; | |
3426 | gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0); | |
3427 | } | |
c0f3af97 L |
3428 | else |
3429 | register_specifier = 0xf; | |
3430 | ||
79f0fa25 L |
3431 | /* Use 2-byte VEX prefix by swapping destination and source operand |
3432 | if there are more than 1 register operand. */ | |
3433 | if (i.reg_operands > 1 | |
3434 | && i.vec_encoding != vex_encoding_vex3 | |
86fa6981 | 3435 | && i.dir_encoding == dir_encoding_default |
fa99fab2 | 3436 | && i.operands == i.reg_operands |
dbbc8b7e | 3437 | && operand_type_equal (&i.types[0], &i.types[i.operands - 1]) |
7f399153 | 3438 | && i.tm.opcode_modifier.vexopcode == VEX0F |
dbbc8b7e | 3439 | && (i.tm.opcode_modifier.load || i.tm.opcode_modifier.d) |
fa99fab2 L |
3440 | && i.rex == REX_B) |
3441 | { | |
3442 | unsigned int xchg = i.operands - 1; | |
3443 | union i386_op temp_op; | |
3444 | i386_operand_type temp_type; | |
3445 | ||
3446 | temp_type = i.types[xchg]; | |
3447 | i.types[xchg] = i.types[0]; | |
3448 | i.types[0] = temp_type; | |
3449 | temp_op = i.op[xchg]; | |
3450 | i.op[xchg] = i.op[0]; | |
3451 | i.op[0] = temp_op; | |
3452 | ||
9c2799c2 | 3453 | gas_assert (i.rm.mode == 3); |
fa99fab2 L |
3454 | |
3455 | i.rex = REX_R; | |
3456 | xchg = i.rm.regmem; | |
3457 | i.rm.regmem = i.rm.reg; | |
3458 | i.rm.reg = xchg; | |
3459 | ||
dbbc8b7e JB |
3460 | if (i.tm.opcode_modifier.d) |
3461 | i.tm.base_opcode ^= (i.tm.base_opcode & 0xee) != 0x6e | |
3462 | ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD; | |
3463 | else /* Use the next insn. */ | |
3464 | i.tm = t[1]; | |
fa99fab2 L |
3465 | } |
3466 | ||
79dec6b7 JB |
3467 | /* Use 2-byte VEX prefix by swapping commutative source operands if there |
3468 | are no memory operands and at least 3 register ones. */ | |
3469 | if (i.reg_operands >= 3 | |
3470 | && i.vec_encoding != vex_encoding_vex3 | |
3471 | && i.reg_operands == i.operands - i.imm_operands | |
3472 | && i.tm.opcode_modifier.vex | |
3473 | && i.tm.opcode_modifier.commutative | |
3474 | && (i.tm.opcode_modifier.sse2avx || optimize > 1) | |
3475 | && i.rex == REX_B | |
3476 | && i.vex.register_specifier | |
3477 | && !(i.vex.register_specifier->reg_flags & RegRex)) | |
3478 | { | |
3479 | unsigned int xchg = i.operands - i.reg_operands; | |
3480 | union i386_op temp_op; | |
3481 | i386_operand_type temp_type; | |
3482 | ||
3483 | gas_assert (i.tm.opcode_modifier.vexopcode == VEX0F); | |
3484 | gas_assert (!i.tm.opcode_modifier.sae); | |
3485 | gas_assert (operand_type_equal (&i.types[i.operands - 2], | |
3486 | &i.types[i.operands - 3])); | |
3487 | gas_assert (i.rm.mode == 3); | |
3488 | ||
3489 | temp_type = i.types[xchg]; | |
3490 | i.types[xchg] = i.types[xchg + 1]; | |
3491 | i.types[xchg + 1] = temp_type; | |
3492 | temp_op = i.op[xchg]; | |
3493 | i.op[xchg] = i.op[xchg + 1]; | |
3494 | i.op[xchg + 1] = temp_op; | |
3495 | ||
3496 | i.rex = 0; | |
3497 | xchg = i.rm.regmem | 8; | |
3498 | i.rm.regmem = ~register_specifier & 0xf; | |
3499 | gas_assert (!(i.rm.regmem & 8)); | |
3500 | i.vex.register_specifier += xchg - i.rm.regmem; | |
3501 | register_specifier = ~xchg & 0xf; | |
3502 | } | |
3503 | ||
539f890d L |
3504 | if (i.tm.opcode_modifier.vex == VEXScalar) |
3505 | vector_length = avxscalar; | |
10c17abd JB |
3506 | else if (i.tm.opcode_modifier.vex == VEX256) |
3507 | vector_length = 1; | |
539f890d | 3508 | else |
10c17abd | 3509 | { |
56522fc5 | 3510 | unsigned int op; |
10c17abd | 3511 | |
c7213af9 L |
3512 | /* Determine vector length from the last multi-length vector |
3513 | operand. */ | |
10c17abd | 3514 | vector_length = 0; |
56522fc5 | 3515 | for (op = t->operands; op--;) |
10c17abd JB |
3516 | if (t->operand_types[op].bitfield.xmmword |
3517 | && t->operand_types[op].bitfield.ymmword | |
3518 | && i.types[op].bitfield.ymmword) | |
3519 | { | |
3520 | vector_length = 1; | |
3521 | break; | |
3522 | } | |
3523 | } | |
c0f3af97 L |
3524 | |
3525 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
3526 | { | |
3527 | case 0: | |
3528 | implied_prefix = 0; | |
3529 | break; | |
3530 | case DATA_PREFIX_OPCODE: | |
3531 | implied_prefix = 1; | |
3532 | break; | |
3533 | case REPE_PREFIX_OPCODE: | |
3534 | implied_prefix = 2; | |
3535 | break; | |
3536 | case REPNE_PREFIX_OPCODE: | |
3537 | implied_prefix = 3; | |
3538 | break; | |
3539 | default: | |
3540 | abort (); | |
3541 | } | |
3542 | ||
03751133 L |
3543 | /* Check the REX.W bit and VEXW. */ |
3544 | if (i.tm.opcode_modifier.vexw == VEXWIG) | |
3545 | w = (vexwig == vexw1 || (i.rex & REX_W)) ? 1 : 0; | |
3546 | else if (i.tm.opcode_modifier.vexw) | |
3547 | w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0; | |
3548 | else | |
931d03b7 | 3549 | w = (flag_code == CODE_64BIT ? i.rex & REX_W : vexwig == vexw1) ? 1 : 0; |
03751133 | 3550 | |
c0f3af97 | 3551 | /* Use 2-byte VEX prefix if possible. */ |
03751133 L |
3552 | if (w == 0 |
3553 | && i.vec_encoding != vex_encoding_vex3 | |
86fa6981 | 3554 | && i.tm.opcode_modifier.vexopcode == VEX0F |
c0f3af97 L |
3555 | && (i.rex & (REX_W | REX_X | REX_B)) == 0) |
3556 | { | |
3557 | /* 2-byte VEX prefix. */ | |
3558 | unsigned int r; | |
3559 | ||
3560 | i.vex.length = 2; | |
3561 | i.vex.bytes[0] = 0xc5; | |
3562 | ||
3563 | /* Check the REX.R bit. */ | |
3564 | r = (i.rex & REX_R) ? 0 : 1; | |
3565 | i.vex.bytes[1] = (r << 7 | |
3566 | | register_specifier << 3 | |
3567 | | vector_length << 2 | |
3568 | | implied_prefix); | |
3569 | } | |
3570 | else | |
3571 | { | |
3572 | /* 3-byte VEX prefix. */ | |
03751133 | 3573 | unsigned int m; |
c0f3af97 | 3574 | |
f88c9eb0 | 3575 | i.vex.length = 3; |
f88c9eb0 | 3576 | |
7f399153 | 3577 | switch (i.tm.opcode_modifier.vexopcode) |
5dd85c99 | 3578 | { |
7f399153 L |
3579 | case VEX0F: |
3580 | m = 0x1; | |
80de6e00 | 3581 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3582 | break; |
3583 | case VEX0F38: | |
3584 | m = 0x2; | |
80de6e00 | 3585 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3586 | break; |
3587 | case VEX0F3A: | |
3588 | m = 0x3; | |
80de6e00 | 3589 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3590 | break; |
3591 | case XOP08: | |
5dd85c99 SP |
3592 | m = 0x8; |
3593 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3594 | break; |
3595 | case XOP09: | |
f88c9eb0 SP |
3596 | m = 0x9; |
3597 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3598 | break; |
3599 | case XOP0A: | |
f88c9eb0 SP |
3600 | m = 0xa; |
3601 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3602 | break; |
3603 | default: | |
3604 | abort (); | |
f88c9eb0 | 3605 | } |
c0f3af97 | 3606 | |
c0f3af97 L |
3607 | /* The high 3 bits of the second VEX byte are 1's compliment |
3608 | of RXB bits from REX. */ | |
3609 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
3610 | ||
c0f3af97 L |
3611 | i.vex.bytes[2] = (w << 7 |
3612 | | register_specifier << 3 | |
3613 | | vector_length << 2 | |
3614 | | implied_prefix); | |
3615 | } | |
3616 | } | |
3617 | ||
e771e7c9 JB |
3618 | static INLINE bfd_boolean |
3619 | is_evex_encoding (const insn_template *t) | |
3620 | { | |
7091c612 | 3621 | return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift |
e771e7c9 | 3622 | || t->opcode_modifier.broadcast || t->opcode_modifier.masking |
a80195f1 | 3623 | || t->opcode_modifier.sae; |
e771e7c9 JB |
3624 | } |
3625 | ||
7a8655d2 JB |
3626 | static INLINE bfd_boolean |
3627 | is_any_vex_encoding (const insn_template *t) | |
3628 | { | |
3629 | return t->opcode_modifier.vex || t->opcode_modifier.vexopcode | |
3630 | || is_evex_encoding (t); | |
3631 | } | |
3632 | ||
43234a1e L |
3633 | /* Build the EVEX prefix. */ |
3634 | ||
3635 | static void | |
3636 | build_evex_prefix (void) | |
3637 | { | |
3638 | unsigned int register_specifier; | |
3639 | unsigned int implied_prefix; | |
3640 | unsigned int m, w; | |
3641 | rex_byte vrex_used = 0; | |
3642 | ||
3643 | /* Check register specifier. */ | |
3644 | if (i.vex.register_specifier) | |
3645 | { | |
3646 | gas_assert ((i.vrex & REX_X) == 0); | |
3647 | ||
3648 | register_specifier = i.vex.register_specifier->reg_num; | |
3649 | if ((i.vex.register_specifier->reg_flags & RegRex)) | |
3650 | register_specifier += 8; | |
3651 | /* The upper 16 registers are encoded in the fourth byte of the | |
3652 | EVEX prefix. */ | |
3653 | if (!(i.vex.register_specifier->reg_flags & RegVRex)) | |
3654 | i.vex.bytes[3] = 0x8; | |
3655 | register_specifier = ~register_specifier & 0xf; | |
3656 | } | |
3657 | else | |
3658 | { | |
3659 | register_specifier = 0xf; | |
3660 | ||
3661 | /* Encode upper 16 vector index register in the fourth byte of | |
3662 | the EVEX prefix. */ | |
3663 | if (!(i.vrex & REX_X)) | |
3664 | i.vex.bytes[3] = 0x8; | |
3665 | else | |
3666 | vrex_used |= REX_X; | |
3667 | } | |
3668 | ||
3669 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
3670 | { | |
3671 | case 0: | |
3672 | implied_prefix = 0; | |
3673 | break; | |
3674 | case DATA_PREFIX_OPCODE: | |
3675 | implied_prefix = 1; | |
3676 | break; | |
3677 | case REPE_PREFIX_OPCODE: | |
3678 | implied_prefix = 2; | |
3679 | break; | |
3680 | case REPNE_PREFIX_OPCODE: | |
3681 | implied_prefix = 3; | |
3682 | break; | |
3683 | default: | |
3684 | abort (); | |
3685 | } | |
3686 | ||
3687 | /* 4 byte EVEX prefix. */ | |
3688 | i.vex.length = 4; | |
3689 | i.vex.bytes[0] = 0x62; | |
3690 | ||
3691 | /* mmmm bits. */ | |
3692 | switch (i.tm.opcode_modifier.vexopcode) | |
3693 | { | |
3694 | case VEX0F: | |
3695 | m = 1; | |
3696 | break; | |
3697 | case VEX0F38: | |
3698 | m = 2; | |
3699 | break; | |
3700 | case VEX0F3A: | |
3701 | m = 3; | |
3702 | break; | |
3703 | default: | |
3704 | abort (); | |
3705 | break; | |
3706 | } | |
3707 | ||
3708 | /* The high 3 bits of the second EVEX byte are 1's compliment of RXB | |
3709 | bits from REX. */ | |
3710 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
3711 | ||
3712 | /* The fifth bit of the second EVEX byte is 1's compliment of the | |
3713 | REX_R bit in VREX. */ | |
3714 | if (!(i.vrex & REX_R)) | |
3715 | i.vex.bytes[1] |= 0x10; | |
3716 | else | |
3717 | vrex_used |= REX_R; | |
3718 | ||
3719 | if ((i.reg_operands + i.imm_operands) == i.operands) | |
3720 | { | |
3721 | /* When all operands are registers, the REX_X bit in REX is not | |
3722 | used. We reuse it to encode the upper 16 registers, which is | |
3723 | indicated by the REX_B bit in VREX. The REX_X bit is encoded | |
3724 | as 1's compliment. */ | |
3725 | if ((i.vrex & REX_B)) | |
3726 | { | |
3727 | vrex_used |= REX_B; | |
3728 | i.vex.bytes[1] &= ~0x40; | |
3729 | } | |
3730 | } | |
3731 | ||
3732 | /* EVEX instructions shouldn't need the REX prefix. */ | |
3733 | i.vrex &= ~vrex_used; | |
3734 | gas_assert (i.vrex == 0); | |
3735 | ||
6865c043 L |
3736 | /* Check the REX.W bit and VEXW. */ |
3737 | if (i.tm.opcode_modifier.vexw == VEXWIG) | |
3738 | w = (evexwig == evexw1 || (i.rex & REX_W)) ? 1 : 0; | |
3739 | else if (i.tm.opcode_modifier.vexw) | |
3740 | w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0; | |
3741 | else | |
931d03b7 | 3742 | w = (flag_code == CODE_64BIT ? i.rex & REX_W : evexwig == evexw1) ? 1 : 0; |
43234a1e L |
3743 | |
3744 | /* Encode the U bit. */ | |
3745 | implied_prefix |= 0x4; | |
3746 | ||
3747 | /* The third byte of the EVEX prefix. */ | |
3748 | i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix); | |
3749 | ||
3750 | /* The fourth byte of the EVEX prefix. */ | |
3751 | /* The zeroing-masking bit. */ | |
3752 | if (i.mask && i.mask->zeroing) | |
3753 | i.vex.bytes[3] |= 0x80; | |
3754 | ||
3755 | /* Don't always set the broadcast bit if there is no RC. */ | |
3756 | if (!i.rounding) | |
3757 | { | |
3758 | /* Encode the vector length. */ | |
3759 | unsigned int vec_length; | |
3760 | ||
e771e7c9 JB |
3761 | if (!i.tm.opcode_modifier.evex |
3762 | || i.tm.opcode_modifier.evex == EVEXDYN) | |
3763 | { | |
56522fc5 | 3764 | unsigned int op; |
e771e7c9 | 3765 | |
c7213af9 L |
3766 | /* Determine vector length from the last multi-length vector |
3767 | operand. */ | |
e771e7c9 | 3768 | vec_length = 0; |
56522fc5 | 3769 | for (op = i.operands; op--;) |
e771e7c9 JB |
3770 | if (i.tm.operand_types[op].bitfield.xmmword |
3771 | + i.tm.operand_types[op].bitfield.ymmword | |
3772 | + i.tm.operand_types[op].bitfield.zmmword > 1) | |
3773 | { | |
3774 | if (i.types[op].bitfield.zmmword) | |
c7213af9 L |
3775 | { |
3776 | i.tm.opcode_modifier.evex = EVEX512; | |
3777 | break; | |
3778 | } | |
e771e7c9 | 3779 | else if (i.types[op].bitfield.ymmword) |
c7213af9 L |
3780 | { |
3781 | i.tm.opcode_modifier.evex = EVEX256; | |
3782 | break; | |
3783 | } | |
e771e7c9 | 3784 | else if (i.types[op].bitfield.xmmword) |
c7213af9 L |
3785 | { |
3786 | i.tm.opcode_modifier.evex = EVEX128; | |
3787 | break; | |
3788 | } | |
625cbd7a JB |
3789 | else if (i.broadcast && (int) op == i.broadcast->operand) |
3790 | { | |
4a1b91ea | 3791 | switch (i.broadcast->bytes) |
625cbd7a JB |
3792 | { |
3793 | case 64: | |
3794 | i.tm.opcode_modifier.evex = EVEX512; | |
3795 | break; | |
3796 | case 32: | |
3797 | i.tm.opcode_modifier.evex = EVEX256; | |
3798 | break; | |
3799 | case 16: | |
3800 | i.tm.opcode_modifier.evex = EVEX128; | |
3801 | break; | |
3802 | default: | |
c7213af9 | 3803 | abort (); |
625cbd7a | 3804 | } |
c7213af9 | 3805 | break; |
625cbd7a | 3806 | } |
e771e7c9 | 3807 | } |
c7213af9 | 3808 | |
56522fc5 | 3809 | if (op >= MAX_OPERANDS) |
c7213af9 | 3810 | abort (); |
e771e7c9 JB |
3811 | } |
3812 | ||
43234a1e L |
3813 | switch (i.tm.opcode_modifier.evex) |
3814 | { | |
3815 | case EVEXLIG: /* LL' is ignored */ | |
3816 | vec_length = evexlig << 5; | |
3817 | break; | |
3818 | case EVEX128: | |
3819 | vec_length = 0 << 5; | |
3820 | break; | |
3821 | case EVEX256: | |
3822 | vec_length = 1 << 5; | |
3823 | break; | |
3824 | case EVEX512: | |
3825 | vec_length = 2 << 5; | |
3826 | break; | |
3827 | default: | |
3828 | abort (); | |
3829 | break; | |
3830 | } | |
3831 | i.vex.bytes[3] |= vec_length; | |
3832 | /* Encode the broadcast bit. */ | |
3833 | if (i.broadcast) | |
3834 | i.vex.bytes[3] |= 0x10; | |
3835 | } | |
3836 | else | |
3837 | { | |
3838 | if (i.rounding->type != saeonly) | |
3839 | i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5); | |
3840 | else | |
d3d3c6db | 3841 | i.vex.bytes[3] |= 0x10 | (evexrcig << 5); |
43234a1e L |
3842 | } |
3843 | ||
3844 | if (i.mask && i.mask->mask) | |
3845 | i.vex.bytes[3] |= i.mask->mask->reg_num; | |
3846 | } | |
3847 | ||
65da13b5 L |
3848 | static void |
3849 | process_immext (void) | |
3850 | { | |
3851 | expressionS *exp; | |
3852 | ||
c0f3af97 | 3853 | /* These AMD 3DNow! and SSE2 instructions have an opcode suffix |
65da13b5 L |
3854 | which is coded in the same place as an 8-bit immediate field |
3855 | would be. Here we fake an 8-bit immediate operand from the | |
3856 | opcode suffix stored in tm.extension_opcode. | |
3857 | ||
c1e679ec | 3858 | AVX instructions also use this encoding, for some of |
c0f3af97 | 3859 | 3 argument instructions. */ |
65da13b5 | 3860 | |
43234a1e | 3861 | gas_assert (i.imm_operands <= 1 |
7ab9ffdd | 3862 | && (i.operands <= 2 |
7a8655d2 | 3863 | || (is_any_vex_encoding (&i.tm) |
7ab9ffdd | 3864 | && i.operands <= 4))); |
65da13b5 L |
3865 | |
3866 | exp = &im_expressions[i.imm_operands++]; | |
3867 | i.op[i.operands].imms = exp; | |
3868 | i.types[i.operands] = imm8; | |
3869 | i.operands++; | |
3870 | exp->X_op = O_constant; | |
3871 | exp->X_add_number = i.tm.extension_opcode; | |
3872 | i.tm.extension_opcode = None; | |
3873 | } | |
3874 | ||
42164a71 L |
3875 | |
3876 | static int | |
3877 | check_hle (void) | |
3878 | { | |
3879 | switch (i.tm.opcode_modifier.hleprefixok) | |
3880 | { | |
3881 | default: | |
3882 | abort (); | |
82c2def5 | 3883 | case HLEPrefixNone: |
165de32a L |
3884 | as_bad (_("invalid instruction `%s' after `%s'"), |
3885 | i.tm.name, i.hle_prefix); | |
42164a71 | 3886 | return 0; |
82c2def5 | 3887 | case HLEPrefixLock: |
42164a71 L |
3888 | if (i.prefix[LOCK_PREFIX]) |
3889 | return 1; | |
165de32a | 3890 | as_bad (_("missing `lock' with `%s'"), i.hle_prefix); |
42164a71 | 3891 | return 0; |
82c2def5 | 3892 | case HLEPrefixAny: |
42164a71 | 3893 | return 1; |
82c2def5 | 3894 | case HLEPrefixRelease: |
42164a71 L |
3895 | if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE) |
3896 | { | |
3897 | as_bad (_("instruction `%s' after `xacquire' not allowed"), | |
3898 | i.tm.name); | |
3899 | return 0; | |
3900 | } | |
8dc0818e | 3901 | if (i.mem_operands == 0 || !(i.flags[i.operands - 1] & Operand_Mem)) |
42164a71 L |
3902 | { |
3903 | as_bad (_("memory destination needed for instruction `%s'" | |
3904 | " after `xrelease'"), i.tm.name); | |
3905 | return 0; | |
3906 | } | |
3907 | return 1; | |
3908 | } | |
3909 | } | |
3910 | ||
b6f8c7c4 L |
3911 | /* Try the shortest encoding by shortening operand size. */ |
3912 | ||
3913 | static void | |
3914 | optimize_encoding (void) | |
3915 | { | |
a0a1771e | 3916 | unsigned int j; |
b6f8c7c4 L |
3917 | |
3918 | if (optimize_for_space | |
3919 | && i.reg_operands == 1 | |
3920 | && i.imm_operands == 1 | |
3921 | && !i.types[1].bitfield.byte | |
3922 | && i.op[0].imms->X_op == O_constant | |
3923 | && fits_in_imm7 (i.op[0].imms->X_add_number) | |
3924 | && ((i.tm.base_opcode == 0xa8 | |
3925 | && i.tm.extension_opcode == None) | |
3926 | || (i.tm.base_opcode == 0xf6 | |
3927 | && i.tm.extension_opcode == 0x0))) | |
3928 | { | |
3929 | /* Optimize: -Os: | |
3930 | test $imm7, %r64/%r32/%r16 -> test $imm7, %r8 | |
3931 | */ | |
3932 | unsigned int base_regnum = i.op[1].regs->reg_num; | |
3933 | if (flag_code == CODE_64BIT || base_regnum < 4) | |
3934 | { | |
3935 | i.types[1].bitfield.byte = 1; | |
3936 | /* Ignore the suffix. */ | |
3937 | i.suffix = 0; | |
3938 | if (base_regnum >= 4 | |
3939 | && !(i.op[1].regs->reg_flags & RegRex)) | |
3940 | { | |
3941 | /* Handle SP, BP, SI and DI registers. */ | |
3942 | if (i.types[1].bitfield.word) | |
3943 | j = 16; | |
3944 | else if (i.types[1].bitfield.dword) | |
3945 | j = 32; | |
3946 | else | |
3947 | j = 48; | |
3948 | i.op[1].regs -= j; | |
3949 | } | |
3950 | } | |
3951 | } | |
3952 | else if (flag_code == CODE_64BIT | |
d3d50934 L |
3953 | && ((i.types[1].bitfield.qword |
3954 | && i.reg_operands == 1 | |
b6f8c7c4 L |
3955 | && i.imm_operands == 1 |
3956 | && i.op[0].imms->X_op == O_constant | |
507916b8 | 3957 | && ((i.tm.base_opcode == 0xb8 |
b6f8c7c4 L |
3958 | && i.tm.extension_opcode == None |
3959 | && fits_in_unsigned_long (i.op[0].imms->X_add_number)) | |
3960 | || (fits_in_imm31 (i.op[0].imms->X_add_number) | |
3961 | && (((i.tm.base_opcode == 0x24 | |
3962 | || i.tm.base_opcode == 0xa8) | |
3963 | && i.tm.extension_opcode == None) | |
3964 | || (i.tm.base_opcode == 0x80 | |
3965 | && i.tm.extension_opcode == 0x4) | |
3966 | || ((i.tm.base_opcode == 0xf6 | |
507916b8 | 3967 | || (i.tm.base_opcode | 1) == 0xc7) |
b8364fa7 JB |
3968 | && i.tm.extension_opcode == 0x0))) |
3969 | || (fits_in_imm7 (i.op[0].imms->X_add_number) | |
3970 | && i.tm.base_opcode == 0x83 | |
3971 | && i.tm.extension_opcode == 0x4))) | |
d3d50934 L |
3972 | || (i.types[0].bitfield.qword |
3973 | && ((i.reg_operands == 2 | |
3974 | && i.op[0].regs == i.op[1].regs | |
3975 | && ((i.tm.base_opcode == 0x30 | |
3976 | || i.tm.base_opcode == 0x28) | |
3977 | && i.tm.extension_opcode == None)) | |
3978 | || (i.reg_operands == 1 | |
3979 | && i.operands == 1 | |
3980 | && i.tm.base_opcode == 0x30 | |
3981 | && i.tm.extension_opcode == None))))) | |
b6f8c7c4 L |
3982 | { |
3983 | /* Optimize: -O: | |
3984 | andq $imm31, %r64 -> andl $imm31, %r32 | |
b8364fa7 | 3985 | andq $imm7, %r64 -> andl $imm7, %r32 |
b6f8c7c4 L |
3986 | testq $imm31, %r64 -> testl $imm31, %r32 |
3987 | xorq %r64, %r64 -> xorl %r32, %r32 | |
3988 | subq %r64, %r64 -> subl %r32, %r32 | |
3989 | movq $imm31, %r64 -> movl $imm31, %r32 | |
3990 | movq $imm32, %r64 -> movl $imm32, %r32 | |
3991 | */ | |
3992 | i.tm.opcode_modifier.norex64 = 1; | |
507916b8 | 3993 | if (i.tm.base_opcode == 0xb8 || (i.tm.base_opcode | 1) == 0xc7) |
b6f8c7c4 L |
3994 | { |
3995 | /* Handle | |
3996 | movq $imm31, %r64 -> movl $imm31, %r32 | |
3997 | movq $imm32, %r64 -> movl $imm32, %r32 | |
3998 | */ | |
3999 | i.tm.operand_types[0].bitfield.imm32 = 1; | |
4000 | i.tm.operand_types[0].bitfield.imm32s = 0; | |
4001 | i.tm.operand_types[0].bitfield.imm64 = 0; | |
4002 | i.types[0].bitfield.imm32 = 1; | |
4003 | i.types[0].bitfield.imm32s = 0; | |
4004 | i.types[0].bitfield.imm64 = 0; | |
4005 | i.types[1].bitfield.dword = 1; | |
4006 | i.types[1].bitfield.qword = 0; | |
507916b8 | 4007 | if ((i.tm.base_opcode | 1) == 0xc7) |
b6f8c7c4 L |
4008 | { |
4009 | /* Handle | |
4010 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4011 | */ | |
507916b8 | 4012 | i.tm.base_opcode = 0xb8; |
b6f8c7c4 | 4013 | i.tm.extension_opcode = None; |
507916b8 | 4014 | i.tm.opcode_modifier.w = 0; |
b6f8c7c4 L |
4015 | i.tm.opcode_modifier.shortform = 1; |
4016 | i.tm.opcode_modifier.modrm = 0; | |
4017 | } | |
4018 | } | |
4019 | } | |
5641ec01 JB |
4020 | else if (optimize > 1 |
4021 | && !optimize_for_space | |
4022 | && i.reg_operands == 2 | |
4023 | && i.op[0].regs == i.op[1].regs | |
4024 | && ((i.tm.base_opcode & ~(Opcode_D | 1)) == 0x8 | |
4025 | || (i.tm.base_opcode & ~(Opcode_D | 1)) == 0x20) | |
4026 | && (flag_code != CODE_64BIT || !i.types[0].bitfield.dword)) | |
4027 | { | |
4028 | /* Optimize: -O2: | |
4029 | andb %rN, %rN -> testb %rN, %rN | |
4030 | andw %rN, %rN -> testw %rN, %rN | |
4031 | andq %rN, %rN -> testq %rN, %rN | |
4032 | orb %rN, %rN -> testb %rN, %rN | |
4033 | orw %rN, %rN -> testw %rN, %rN | |
4034 | orq %rN, %rN -> testq %rN, %rN | |
4035 | ||
4036 | and outside of 64-bit mode | |
4037 | ||
4038 | andl %rN, %rN -> testl %rN, %rN | |
4039 | orl %rN, %rN -> testl %rN, %rN | |
4040 | */ | |
4041 | i.tm.base_opcode = 0x84 | (i.tm.base_opcode & 1); | |
4042 | } | |
99112332 | 4043 | else if (i.reg_operands == 3 |
b6f8c7c4 L |
4044 | && i.op[0].regs == i.op[1].regs |
4045 | && !i.types[2].bitfield.xmmword | |
4046 | && (i.tm.opcode_modifier.vex | |
7a69eac3 | 4047 | || ((!i.mask || i.mask->zeroing) |
b6f8c7c4 | 4048 | && !i.rounding |
e771e7c9 | 4049 | && is_evex_encoding (&i.tm) |
80c34c38 | 4050 | && (i.vec_encoding != vex_encoding_evex |
dd22218c | 4051 | || cpu_arch_isa_flags.bitfield.cpuavx512vl |
80c34c38 | 4052 | || i.tm.cpu_flags.bitfield.cpuavx512vl |
7091c612 | 4053 | || (i.tm.operand_types[2].bitfield.zmmword |
dd22218c | 4054 | && i.types[2].bitfield.ymmword)))) |
b6f8c7c4 L |
4055 | && ((i.tm.base_opcode == 0x55 |
4056 | || i.tm.base_opcode == 0x6655 | |
4057 | || i.tm.base_opcode == 0x66df | |
4058 | || i.tm.base_opcode == 0x57 | |
4059 | || i.tm.base_opcode == 0x6657 | |
8305403a L |
4060 | || i.tm.base_opcode == 0x66ef |
4061 | || i.tm.base_opcode == 0x66f8 | |
4062 | || i.tm.base_opcode == 0x66f9 | |
4063 | || i.tm.base_opcode == 0x66fa | |
1424ad86 JB |
4064 | || i.tm.base_opcode == 0x66fb |
4065 | || i.tm.base_opcode == 0x42 | |
4066 | || i.tm.base_opcode == 0x6642 | |
4067 | || i.tm.base_opcode == 0x47 | |
4068 | || i.tm.base_opcode == 0x6647) | |
b6f8c7c4 L |
4069 | && i.tm.extension_opcode == None)) |
4070 | { | |
99112332 | 4071 | /* Optimize: -O1: |
8305403a L |
4072 | VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd, |
4073 | vpsubq and vpsubw: | |
b6f8c7c4 L |
4074 | EVEX VOP %zmmM, %zmmM, %zmmN |
4075 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4076 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4077 | EVEX VOP %ymmM, %ymmM, %ymmN |
4078 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4079 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4080 | VEX VOP %ymmM, %ymmM, %ymmN |
4081 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
4082 | VOP, one of vpandn and vpxor: | |
4083 | VEX VOP %ymmM, %ymmM, %ymmN | |
4084 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
4085 | VOP, one of vpandnd and vpandnq: | |
4086 | EVEX VOP %zmmM, %zmmM, %zmmN | |
4087 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4088 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4089 | EVEX VOP %ymmM, %ymmM, %ymmN |
4090 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4091 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4092 | VOP, one of vpxord and vpxorq: |
4093 | EVEX VOP %zmmM, %zmmM, %zmmN | |
4094 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4095 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4096 | EVEX VOP %ymmM, %ymmM, %ymmN |
4097 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4098 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
1424ad86 JB |
4099 | VOP, one of kxord and kxorq: |
4100 | VEX VOP %kM, %kM, %kN | |
4101 | -> VEX kxorw %kM, %kM, %kN | |
4102 | VOP, one of kandnd and kandnq: | |
4103 | VEX VOP %kM, %kM, %kN | |
4104 | -> VEX kandnw %kM, %kM, %kN | |
b6f8c7c4 | 4105 | */ |
e771e7c9 | 4106 | if (is_evex_encoding (&i.tm)) |
b6f8c7c4 | 4107 | { |
7b1d7ca1 | 4108 | if (i.vec_encoding != vex_encoding_evex) |
b6f8c7c4 L |
4109 | { |
4110 | i.tm.opcode_modifier.vex = VEX128; | |
4111 | i.tm.opcode_modifier.vexw = VEXW0; | |
4112 | i.tm.opcode_modifier.evex = 0; | |
4113 | } | |
7b1d7ca1 | 4114 | else if (optimize > 1) |
dd22218c L |
4115 | i.tm.opcode_modifier.evex = EVEX128; |
4116 | else | |
4117 | return; | |
b6f8c7c4 | 4118 | } |
f74a6307 | 4119 | else if (i.tm.operand_types[0].bitfield.class == RegMask) |
1424ad86 JB |
4120 | { |
4121 | i.tm.base_opcode &= 0xff; | |
4122 | i.tm.opcode_modifier.vexw = VEXW0; | |
4123 | } | |
b6f8c7c4 L |
4124 | else |
4125 | i.tm.opcode_modifier.vex = VEX128; | |
4126 | ||
4127 | if (i.tm.opcode_modifier.vex) | |
4128 | for (j = 0; j < 3; j++) | |
4129 | { | |
4130 | i.types[j].bitfield.xmmword = 1; | |
4131 | i.types[j].bitfield.ymmword = 0; | |
4132 | } | |
4133 | } | |
392a5972 | 4134 | else if (i.vec_encoding != vex_encoding_evex |
97ed31ae | 4135 | && !i.types[0].bitfield.zmmword |
392a5972 | 4136 | && !i.types[1].bitfield.zmmword |
97ed31ae | 4137 | && !i.mask |
a0a1771e | 4138 | && !i.broadcast |
97ed31ae | 4139 | && is_evex_encoding (&i.tm) |
392a5972 L |
4140 | && ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0x666f |
4141 | || (i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf36f | |
a0a1771e JB |
4142 | || (i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf26f |
4143 | || (i.tm.base_opcode & ~4) == 0x66db | |
4144 | || (i.tm.base_opcode & ~4) == 0x66eb) | |
97ed31ae L |
4145 | && i.tm.extension_opcode == None) |
4146 | { | |
4147 | /* Optimize: -O1: | |
4148 | VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, | |
4149 | vmovdqu32 and vmovdqu64: | |
4150 | EVEX VOP %xmmM, %xmmN | |
4151 | -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16) | |
4152 | EVEX VOP %ymmM, %ymmN | |
4153 | -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16) | |
4154 | EVEX VOP %xmmM, mem | |
4155 | -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16) | |
4156 | EVEX VOP %ymmM, mem | |
4157 | -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16) | |
4158 | EVEX VOP mem, %xmmN | |
4159 | -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16) | |
4160 | EVEX VOP mem, %ymmN | |
4161 | -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16) | |
a0a1771e JB |
4162 | VOP, one of vpand, vpandn, vpor, vpxor: |
4163 | EVEX VOP{d,q} %xmmL, %xmmM, %xmmN | |
4164 | -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16) | |
4165 | EVEX VOP{d,q} %ymmL, %ymmM, %ymmN | |
4166 | -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16) | |
4167 | EVEX VOP{d,q} mem, %xmmM, %xmmN | |
4168 | -> VEX VOP mem, %xmmM, %xmmN (M and N < 16) | |
4169 | EVEX VOP{d,q} mem, %ymmM, %ymmN | |
4170 | -> VEX VOP mem, %ymmM, %ymmN (M and N < 16) | |
97ed31ae | 4171 | */ |
a0a1771e | 4172 | for (j = 0; j < i.operands; j++) |
392a5972 L |
4173 | if (operand_type_check (i.types[j], disp) |
4174 | && i.op[j].disps->X_op == O_constant) | |
4175 | { | |
4176 | /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix | |
4177 | has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4 | |
4178 | bytes, we choose EVEX Disp8 over VEX Disp32. */ | |
4179 | int evex_disp8, vex_disp8; | |
4180 | unsigned int memshift = i.memshift; | |
4181 | offsetT n = i.op[j].disps->X_add_number; | |
4182 | ||
4183 | evex_disp8 = fits_in_disp8 (n); | |
4184 | i.memshift = 0; | |
4185 | vex_disp8 = fits_in_disp8 (n); | |
4186 | if (evex_disp8 != vex_disp8) | |
4187 | { | |
4188 | i.memshift = memshift; | |
4189 | return; | |
4190 | } | |
4191 | ||
4192 | i.types[j].bitfield.disp8 = vex_disp8; | |
4193 | break; | |
4194 | } | |
4195 | if ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf26f) | |
4196 | i.tm.base_opcode ^= 0xf36f ^ 0xf26f; | |
97ed31ae L |
4197 | i.tm.opcode_modifier.vex |
4198 | = i.types[0].bitfield.ymmword ? VEX256 : VEX128; | |
4199 | i.tm.opcode_modifier.vexw = VEXW0; | |
79dec6b7 JB |
4200 | /* VPAND, VPOR, and VPXOR are commutative. */ |
4201 | if (i.reg_operands == 3 && i.tm.base_opcode != 0x66df) | |
4202 | i.tm.opcode_modifier.commutative = 1; | |
97ed31ae L |
4203 | i.tm.opcode_modifier.evex = 0; |
4204 | i.tm.opcode_modifier.masking = 0; | |
a0a1771e | 4205 | i.tm.opcode_modifier.broadcast = 0; |
97ed31ae L |
4206 | i.tm.opcode_modifier.disp8memshift = 0; |
4207 | i.memshift = 0; | |
a0a1771e JB |
4208 | if (j < i.operands) |
4209 | i.types[j].bitfield.disp8 | |
4210 | = fits_in_disp8 (i.op[j].disps->X_add_number); | |
97ed31ae | 4211 | } |
b6f8c7c4 L |
4212 | } |
4213 | ||
252b5132 RH |
4214 | /* This is the guts of the machine-dependent assembler. LINE points to a |
4215 | machine dependent instruction. This function is supposed to emit | |
4216 | the frags/bytes it assembles to. */ | |
4217 | ||
4218 | void | |
65da13b5 | 4219 | md_assemble (char *line) |
252b5132 | 4220 | { |
40fb9820 | 4221 | unsigned int j; |
83b16ac6 | 4222 | char mnemonic[MAX_MNEM_SIZE], mnem_suffix; |
d3ce72d0 | 4223 | const insn_template *t; |
252b5132 | 4224 | |
47926f60 | 4225 | /* Initialize globals. */ |
252b5132 RH |
4226 | memset (&i, '\0', sizeof (i)); |
4227 | for (j = 0; j < MAX_OPERANDS; j++) | |
1ae12ab7 | 4228 | i.reloc[j] = NO_RELOC; |
252b5132 RH |
4229 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
4230 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 4231 | save_stack_p = save_stack; |
252b5132 RH |
4232 | |
4233 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
4234 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 4235 | start of a (possibly prefixed) mnemonic. */ |
252b5132 | 4236 | |
29b0f896 AM |
4237 | line = parse_insn (line, mnemonic); |
4238 | if (line == NULL) | |
4239 | return; | |
83b16ac6 | 4240 | mnem_suffix = i.suffix; |
252b5132 | 4241 | |
29b0f896 | 4242 | line = parse_operands (line, mnemonic); |
ee86248c | 4243 | this_operand = -1; |
8325cc63 JB |
4244 | xfree (i.memop1_string); |
4245 | i.memop1_string = NULL; | |
29b0f896 AM |
4246 | if (line == NULL) |
4247 | return; | |
252b5132 | 4248 | |
29b0f896 AM |
4249 | /* Now we've parsed the mnemonic into a set of templates, and have the |
4250 | operands at hand. */ | |
4251 | ||
4252 | /* All intel opcodes have reversed operands except for "bound" and | |
4253 | "enter". We also don't reverse intersegment "jmp" and "call" | |
4254 | instructions with 2 immediate operands so that the immediate segment | |
050dfa73 | 4255 | precedes the offset, as it does when in AT&T mode. */ |
4d456e3d L |
4256 | if (intel_syntax |
4257 | && i.operands > 1 | |
29b0f896 | 4258 | && (strcmp (mnemonic, "bound") != 0) |
30123838 | 4259 | && (strcmp (mnemonic, "invlpga") != 0) |
40fb9820 L |
4260 | && !(operand_type_check (i.types[0], imm) |
4261 | && operand_type_check (i.types[1], imm))) | |
29b0f896 AM |
4262 | swap_operands (); |
4263 | ||
ec56d5c0 JB |
4264 | /* The order of the immediates should be reversed |
4265 | for 2 immediates extrq and insertq instructions */ | |
4266 | if (i.imm_operands == 2 | |
4267 | && (strcmp (mnemonic, "extrq") == 0 | |
4268 | || strcmp (mnemonic, "insertq") == 0)) | |
4269 | swap_2_operands (0, 1); | |
4270 | ||
29b0f896 AM |
4271 | if (i.imm_operands) |
4272 | optimize_imm (); | |
4273 | ||
b300c311 L |
4274 | /* Don't optimize displacement for movabs since it only takes 64bit |
4275 | displacement. */ | |
4276 | if (i.disp_operands | |
a501d77e | 4277 | && i.disp_encoding != disp_encoding_32bit |
862be3fb L |
4278 | && (flag_code != CODE_64BIT |
4279 | || strcmp (mnemonic, "movabs") != 0)) | |
4280 | optimize_disp (); | |
29b0f896 AM |
4281 | |
4282 | /* Next, we find a template that matches the given insn, | |
4283 | making sure the overlap of the given operands types is consistent | |
4284 | with the template operand types. */ | |
252b5132 | 4285 | |
83b16ac6 | 4286 | if (!(t = match_template (mnem_suffix))) |
29b0f896 | 4287 | return; |
252b5132 | 4288 | |
7bab8ab5 | 4289 | if (sse_check != check_none |
81f8a913 | 4290 | && !i.tm.opcode_modifier.noavx |
6e3e5c9e | 4291 | && !i.tm.cpu_flags.bitfield.cpuavx |
daf50ae7 L |
4292 | && (i.tm.cpu_flags.bitfield.cpusse |
4293 | || i.tm.cpu_flags.bitfield.cpusse2 | |
4294 | || i.tm.cpu_flags.bitfield.cpusse3 | |
4295 | || i.tm.cpu_flags.bitfield.cpussse3 | |
4296 | || i.tm.cpu_flags.bitfield.cpusse4_1 | |
6e3e5c9e JB |
4297 | || i.tm.cpu_flags.bitfield.cpusse4_2 |
4298 | || i.tm.cpu_flags.bitfield.cpupclmul | |
4299 | || i.tm.cpu_flags.bitfield.cpuaes | |
4300 | || i.tm.cpu_flags.bitfield.cpugfni)) | |
daf50ae7 | 4301 | { |
7bab8ab5 | 4302 | (sse_check == check_warning |
daf50ae7 L |
4303 | ? as_warn |
4304 | : as_bad) (_("SSE instruction `%s' is used"), i.tm.name); | |
4305 | } | |
4306 | ||
321fd21e L |
4307 | /* Zap movzx and movsx suffix. The suffix has been set from |
4308 | "word ptr" or "byte ptr" on the source operand in Intel syntax | |
4309 | or extracted from mnemonic in AT&T syntax. But we'll use | |
4310 | the destination register to choose the suffix for encoding. */ | |
4311 | if ((i.tm.base_opcode & ~9) == 0x0fb6) | |
cd61ebfe | 4312 | { |
321fd21e L |
4313 | /* In Intel syntax, there must be a suffix. In AT&T syntax, if |
4314 | there is no suffix, the default will be byte extension. */ | |
4315 | if (i.reg_operands != 2 | |
4316 | && !i.suffix | |
7ab9ffdd | 4317 | && intel_syntax) |
321fd21e L |
4318 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); |
4319 | ||
4320 | i.suffix = 0; | |
cd61ebfe | 4321 | } |
24eab124 | 4322 | |
40fb9820 | 4323 | if (i.tm.opcode_modifier.fwait) |
29b0f896 AM |
4324 | if (!add_prefix (FWAIT_OPCODE)) |
4325 | return; | |
252b5132 | 4326 | |
d5de92cf L |
4327 | /* Check if REP prefix is OK. */ |
4328 | if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok) | |
4329 | { | |
4330 | as_bad (_("invalid instruction `%s' after `%s'"), | |
4331 | i.tm.name, i.rep_prefix); | |
4332 | return; | |
4333 | } | |
4334 | ||
c1ba0266 L |
4335 | /* Check for lock without a lockable instruction. Destination operand |
4336 | must be memory unless it is xchg (0x86). */ | |
c32fa91d L |
4337 | if (i.prefix[LOCK_PREFIX] |
4338 | && (!i.tm.opcode_modifier.islockable | |
c1ba0266 L |
4339 | || i.mem_operands == 0 |
4340 | || (i.tm.base_opcode != 0x86 | |
8dc0818e | 4341 | && !(i.flags[i.operands - 1] & Operand_Mem)))) |
c32fa91d L |
4342 | { |
4343 | as_bad (_("expecting lockable instruction after `lock'")); | |
4344 | return; | |
4345 | } | |
4346 | ||
7a8655d2 JB |
4347 | /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */ |
4348 | if (i.prefix[DATA_PREFIX] && is_any_vex_encoding (&i.tm)) | |
4349 | { | |
4350 | as_bad (_("data size prefix invalid with `%s'"), i.tm.name); | |
4351 | return; | |
4352 | } | |
4353 | ||
42164a71 | 4354 | /* Check if HLE prefix is OK. */ |
165de32a | 4355 | if (i.hle_prefix && !check_hle ()) |
42164a71 L |
4356 | return; |
4357 | ||
7e8b059b L |
4358 | /* Check BND prefix. */ |
4359 | if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok) | |
4360 | as_bad (_("expecting valid branch instruction after `bnd'")); | |
4361 | ||
04ef582a | 4362 | /* Check NOTRACK prefix. */ |
9fef80d6 L |
4363 | if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok) |
4364 | as_bad (_("expecting indirect branch instruction after `notrack'")); | |
04ef582a | 4365 | |
327e8c42 JB |
4366 | if (i.tm.cpu_flags.bitfield.cpumpx) |
4367 | { | |
4368 | if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX]) | |
4369 | as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions.")); | |
4370 | else if (flag_code != CODE_16BIT | |
4371 | ? i.prefix[ADDR_PREFIX] | |
4372 | : i.mem_operands && !i.prefix[ADDR_PREFIX]) | |
4373 | as_bad (_("16-bit address isn't allowed in MPX instructions")); | |
4374 | } | |
7e8b059b L |
4375 | |
4376 | /* Insert BND prefix. */ | |
76d3a78a JB |
4377 | if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok) |
4378 | { | |
4379 | if (!i.prefix[BND_PREFIX]) | |
4380 | add_prefix (BND_PREFIX_OPCODE); | |
4381 | else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE) | |
4382 | { | |
4383 | as_warn (_("replacing `rep'/`repe' prefix by `bnd'")); | |
4384 | i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE; | |
4385 | } | |
4386 | } | |
7e8b059b | 4387 | |
29b0f896 | 4388 | /* Check string instruction segment overrides. */ |
40fb9820 | 4389 | if (i.tm.opcode_modifier.isstring && i.mem_operands != 0) |
29b0f896 AM |
4390 | { |
4391 | if (!check_string ()) | |
5dd0794d | 4392 | return; |
fc0763e6 | 4393 | i.disp_operands = 0; |
29b0f896 | 4394 | } |
5dd0794d | 4395 | |
b6f8c7c4 L |
4396 | if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize) |
4397 | optimize_encoding (); | |
4398 | ||
29b0f896 AM |
4399 | if (!process_suffix ()) |
4400 | return; | |
e413e4e9 | 4401 | |
bc0844ae L |
4402 | /* Update operand types. */ |
4403 | for (j = 0; j < i.operands; j++) | |
4404 | i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]); | |
4405 | ||
29b0f896 AM |
4406 | /* Make still unresolved immediate matches conform to size of immediate |
4407 | given in i.suffix. */ | |
4408 | if (!finalize_imm ()) | |
4409 | return; | |
252b5132 | 4410 | |
40fb9820 | 4411 | if (i.types[0].bitfield.imm1) |
29b0f896 | 4412 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 | 4413 | |
9afe6eb8 L |
4414 | /* We only need to check those implicit registers for instructions |
4415 | with 3 operands or less. */ | |
4416 | if (i.operands <= 3) | |
4417 | for (j = 0; j < i.operands; j++) | |
75e5731b JB |
4418 | if (i.types[j].bitfield.instance != InstanceNone |
4419 | && !i.types[j].bitfield.xmmword) | |
9afe6eb8 | 4420 | i.reg_operands--; |
40fb9820 | 4421 | |
c0f3af97 L |
4422 | /* ImmExt should be processed after SSE2AVX. */ |
4423 | if (!i.tm.opcode_modifier.sse2avx | |
4424 | && i.tm.opcode_modifier.immext) | |
65da13b5 | 4425 | process_immext (); |
252b5132 | 4426 | |
29b0f896 AM |
4427 | /* For insns with operands there are more diddles to do to the opcode. */ |
4428 | if (i.operands) | |
4429 | { | |
4430 | if (!process_operands ()) | |
4431 | return; | |
4432 | } | |
40fb9820 | 4433 | else if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 AM |
4434 | { |
4435 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ | |
4436 | as_warn (_("translating to `%sp'"), i.tm.name); | |
4437 | } | |
252b5132 | 4438 | |
7a8655d2 | 4439 | if (is_any_vex_encoding (&i.tm)) |
9e5e5283 | 4440 | { |
c1dc7af5 | 4441 | if (!cpu_arch_flags.bitfield.cpui286) |
9e5e5283 | 4442 | { |
c1dc7af5 | 4443 | as_bad (_("instruction `%s' isn't supported outside of protected mode."), |
9e5e5283 L |
4444 | i.tm.name); |
4445 | return; | |
4446 | } | |
c0f3af97 | 4447 | |
9e5e5283 L |
4448 | if (i.tm.opcode_modifier.vex) |
4449 | build_vex_prefix (t); | |
4450 | else | |
4451 | build_evex_prefix (); | |
4452 | } | |
43234a1e | 4453 | |
5dd85c99 SP |
4454 | /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4 |
4455 | instructions may define INT_OPCODE as well, so avoid this corner | |
4456 | case for those instructions that use MODRM. */ | |
4457 | if (i.tm.base_opcode == INT_OPCODE | |
a6461c02 SP |
4458 | && !i.tm.opcode_modifier.modrm |
4459 | && i.op[0].imms->X_add_number == 3) | |
29b0f896 AM |
4460 | { |
4461 | i.tm.base_opcode = INT3_OPCODE; | |
4462 | i.imm_operands = 0; | |
4463 | } | |
252b5132 | 4464 | |
40fb9820 L |
4465 | if ((i.tm.opcode_modifier.jump |
4466 | || i.tm.opcode_modifier.jumpbyte | |
4467 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 AM |
4468 | && i.op[0].disps->X_op == O_constant) |
4469 | { | |
4470 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
4471 | the absolute address given by the constant. Since ix86 jumps and | |
4472 | calls are pc relative, we need to generate a reloc. */ | |
4473 | i.op[0].disps->X_add_symbol = &abs_symbol; | |
4474 | i.op[0].disps->X_op = O_symbol; | |
4475 | } | |
252b5132 | 4476 | |
40fb9820 | 4477 | if (i.tm.opcode_modifier.rex64) |
161a04f6 | 4478 | i.rex |= REX_W; |
252b5132 | 4479 | |
29b0f896 AM |
4480 | /* For 8 bit registers we need an empty rex prefix. Also if the |
4481 | instruction already has a prefix, we need to convert old | |
4482 | registers to new ones. */ | |
773f551c | 4483 | |
bab6aec1 | 4484 | if ((i.types[0].bitfield.class == Reg && i.types[0].bitfield.byte |
29b0f896 | 4485 | && (i.op[0].regs->reg_flags & RegRex64) != 0) |
bab6aec1 | 4486 | || (i.types[1].bitfield.class == Reg && i.types[1].bitfield.byte |
29b0f896 | 4487 | && (i.op[1].regs->reg_flags & RegRex64) != 0) |
bab6aec1 JB |
4488 | || (((i.types[0].bitfield.class == Reg && i.types[0].bitfield.byte) |
4489 | || (i.types[1].bitfield.class == Reg && i.types[1].bitfield.byte)) | |
29b0f896 AM |
4490 | && i.rex != 0)) |
4491 | { | |
4492 | int x; | |
726c5dcd | 4493 | |
29b0f896 AM |
4494 | i.rex |= REX_OPCODE; |
4495 | for (x = 0; x < 2; x++) | |
4496 | { | |
4497 | /* Look for 8 bit operand that uses old registers. */ | |
bab6aec1 | 4498 | if (i.types[x].bitfield.class == Reg && i.types[x].bitfield.byte |
29b0f896 | 4499 | && (i.op[x].regs->reg_flags & RegRex64) == 0) |
773f551c | 4500 | { |
29b0f896 AM |
4501 | /* In case it is "hi" register, give up. */ |
4502 | if (i.op[x].regs->reg_num > 3) | |
a540244d | 4503 | as_bad (_("can't encode register '%s%s' in an " |
4eed87de | 4504 | "instruction requiring REX prefix."), |
a540244d | 4505 | register_prefix, i.op[x].regs->reg_name); |
773f551c | 4506 | |
29b0f896 AM |
4507 | /* Otherwise it is equivalent to the extended register. |
4508 | Since the encoding doesn't change this is merely | |
4509 | cosmetic cleanup for debug output. */ | |
4510 | ||
4511 | i.op[x].regs = i.op[x].regs + 8; | |
773f551c | 4512 | } |
29b0f896 AM |
4513 | } |
4514 | } | |
773f551c | 4515 | |
6b6b6807 L |
4516 | if (i.rex == 0 && i.rex_encoding) |
4517 | { | |
4518 | /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand | |
4519 | that uses legacy register. If it is "hi" register, don't add | |
4520 | the REX_OPCODE byte. */ | |
4521 | int x; | |
4522 | for (x = 0; x < 2; x++) | |
bab6aec1 | 4523 | if (i.types[x].bitfield.class == Reg |
6b6b6807 L |
4524 | && i.types[x].bitfield.byte |
4525 | && (i.op[x].regs->reg_flags & RegRex64) == 0 | |
4526 | && i.op[x].regs->reg_num > 3) | |
4527 | { | |
4528 | i.rex_encoding = FALSE; | |
4529 | break; | |
4530 | } | |
4531 | ||
4532 | if (i.rex_encoding) | |
4533 | i.rex = REX_OPCODE; | |
4534 | } | |
4535 | ||
7ab9ffdd | 4536 | if (i.rex != 0) |
29b0f896 AM |
4537 | add_prefix (REX_OPCODE | i.rex); |
4538 | ||
4539 | /* We are ready to output the insn. */ | |
4540 | output_insn (); | |
4541 | } | |
4542 | ||
4543 | static char * | |
e3bb37b5 | 4544 | parse_insn (char *line, char *mnemonic) |
29b0f896 AM |
4545 | { |
4546 | char *l = line; | |
4547 | char *token_start = l; | |
4548 | char *mnem_p; | |
5c6af06e | 4549 | int supported; |
d3ce72d0 | 4550 | const insn_template *t; |
b6169b20 | 4551 | char *dot_p = NULL; |
29b0f896 | 4552 | |
29b0f896 AM |
4553 | while (1) |
4554 | { | |
4555 | mnem_p = mnemonic; | |
4556 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
4557 | { | |
b6169b20 L |
4558 | if (*mnem_p == '.') |
4559 | dot_p = mnem_p; | |
29b0f896 AM |
4560 | mnem_p++; |
4561 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
45288df1 | 4562 | { |
29b0f896 AM |
4563 | as_bad (_("no such instruction: `%s'"), token_start); |
4564 | return NULL; | |
4565 | } | |
4566 | l++; | |
4567 | } | |
4568 | if (!is_space_char (*l) | |
4569 | && *l != END_OF_INSN | |
e44823cf JB |
4570 | && (intel_syntax |
4571 | || (*l != PREFIX_SEPARATOR | |
4572 | && *l != ','))) | |
29b0f896 AM |
4573 | { |
4574 | as_bad (_("invalid character %s in mnemonic"), | |
4575 | output_invalid (*l)); | |
4576 | return NULL; | |
4577 | } | |
4578 | if (token_start == l) | |
4579 | { | |
e44823cf | 4580 | if (!intel_syntax && *l == PREFIX_SEPARATOR) |
29b0f896 AM |
4581 | as_bad (_("expecting prefix; got nothing")); |
4582 | else | |
4583 | as_bad (_("expecting mnemonic; got nothing")); | |
4584 | return NULL; | |
4585 | } | |
45288df1 | 4586 | |
29b0f896 | 4587 | /* Look up instruction (or prefix) via hash table. */ |
d3ce72d0 | 4588 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
47926f60 | 4589 | |
29b0f896 AM |
4590 | if (*l != END_OF_INSN |
4591 | && (!is_space_char (*l) || l[1] != END_OF_INSN) | |
4592 | && current_templates | |
40fb9820 | 4593 | && current_templates->start->opcode_modifier.isprefix) |
29b0f896 | 4594 | { |
c6fb90c8 | 4595 | if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags)) |
2dd88dca JB |
4596 | { |
4597 | as_bad ((flag_code != CODE_64BIT | |
4598 | ? _("`%s' is only supported in 64-bit mode") | |
4599 | : _("`%s' is not supported in 64-bit mode")), | |
4600 | current_templates->start->name); | |
4601 | return NULL; | |
4602 | } | |
29b0f896 AM |
4603 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
4604 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
673fe0f0 JB |
4605 | if ((current_templates->start->opcode_modifier.size == SIZE16 |
4606 | || current_templates->start->opcode_modifier.size == SIZE32) | |
29b0f896 | 4607 | && flag_code != CODE_64BIT |
673fe0f0 | 4608 | && ((current_templates->start->opcode_modifier.size == SIZE32) |
29b0f896 AM |
4609 | ^ (flag_code == CODE_16BIT))) |
4610 | { | |
4611 | as_bad (_("redundant %s prefix"), | |
4612 | current_templates->start->name); | |
4613 | return NULL; | |
45288df1 | 4614 | } |
86fa6981 | 4615 | if (current_templates->start->opcode_length == 0) |
29b0f896 | 4616 | { |
86fa6981 L |
4617 | /* Handle pseudo prefixes. */ |
4618 | switch (current_templates->start->base_opcode) | |
4619 | { | |
4620 | case 0x0: | |
4621 | /* {disp8} */ | |
4622 | i.disp_encoding = disp_encoding_8bit; | |
4623 | break; | |
4624 | case 0x1: | |
4625 | /* {disp32} */ | |
4626 | i.disp_encoding = disp_encoding_32bit; | |
4627 | break; | |
4628 | case 0x2: | |
4629 | /* {load} */ | |
4630 | i.dir_encoding = dir_encoding_load; | |
4631 | break; | |
4632 | case 0x3: | |
4633 | /* {store} */ | |
4634 | i.dir_encoding = dir_encoding_store; | |
4635 | break; | |
4636 | case 0x4: | |
4637 | /* {vex2} */ | |
4638 | i.vec_encoding = vex_encoding_vex2; | |
4639 | break; | |
4640 | case 0x5: | |
4641 | /* {vex3} */ | |
4642 | i.vec_encoding = vex_encoding_vex3; | |
4643 | break; | |
4644 | case 0x6: | |
4645 | /* {evex} */ | |
4646 | i.vec_encoding = vex_encoding_evex; | |
4647 | break; | |
6b6b6807 L |
4648 | case 0x7: |
4649 | /* {rex} */ | |
4650 | i.rex_encoding = TRUE; | |
4651 | break; | |
b6f8c7c4 L |
4652 | case 0x8: |
4653 | /* {nooptimize} */ | |
4654 | i.no_optimize = TRUE; | |
4655 | break; | |
86fa6981 L |
4656 | default: |
4657 | abort (); | |
4658 | } | |
4659 | } | |
4660 | else | |
4661 | { | |
4662 | /* Add prefix, checking for repeated prefixes. */ | |
4e9ac44a | 4663 | switch (add_prefix (current_templates->start->base_opcode)) |
86fa6981 | 4664 | { |
4e9ac44a L |
4665 | case PREFIX_EXIST: |
4666 | return NULL; | |
4667 | case PREFIX_DS: | |
d777820b | 4668 | if (current_templates->start->cpu_flags.bitfield.cpuibt) |
4e9ac44a L |
4669 | i.notrack_prefix = current_templates->start->name; |
4670 | break; | |
4671 | case PREFIX_REP: | |
4672 | if (current_templates->start->cpu_flags.bitfield.cpuhle) | |
4673 | i.hle_prefix = current_templates->start->name; | |
4674 | else if (current_templates->start->cpu_flags.bitfield.cpumpx) | |
4675 | i.bnd_prefix = current_templates->start->name; | |
4676 | else | |
4677 | i.rep_prefix = current_templates->start->name; | |
4678 | break; | |
4679 | default: | |
4680 | break; | |
86fa6981 | 4681 | } |
29b0f896 AM |
4682 | } |
4683 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
4684 | token_start = ++l; | |
4685 | } | |
4686 | else | |
4687 | break; | |
4688 | } | |
45288df1 | 4689 | |
30a55f88 | 4690 | if (!current_templates) |
b6169b20 | 4691 | { |
07d5e953 JB |
4692 | /* Deprecated functionality (new code should use pseudo-prefixes instead): |
4693 | Check if we should swap operand or force 32bit displacement in | |
f8a5c266 | 4694 | encoding. */ |
30a55f88 | 4695 | if (mnem_p - 2 == dot_p && dot_p[1] == 's') |
64c49ab3 | 4696 | i.dir_encoding = dir_encoding_swap; |
8d63c93e | 4697 | else if (mnem_p - 3 == dot_p |
a501d77e L |
4698 | && dot_p[1] == 'd' |
4699 | && dot_p[2] == '8') | |
4700 | i.disp_encoding = disp_encoding_8bit; | |
8d63c93e | 4701 | else if (mnem_p - 4 == dot_p |
f8a5c266 L |
4702 | && dot_p[1] == 'd' |
4703 | && dot_p[2] == '3' | |
4704 | && dot_p[3] == '2') | |
a501d77e | 4705 | i.disp_encoding = disp_encoding_32bit; |
30a55f88 L |
4706 | else |
4707 | goto check_suffix; | |
4708 | mnem_p = dot_p; | |
4709 | *dot_p = '\0'; | |
d3ce72d0 | 4710 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
b6169b20 L |
4711 | } |
4712 | ||
29b0f896 AM |
4713 | if (!current_templates) |
4714 | { | |
b6169b20 | 4715 | check_suffix: |
1c529385 | 4716 | if (mnem_p > mnemonic) |
29b0f896 | 4717 | { |
1c529385 LH |
4718 | /* See if we can get a match by trimming off a suffix. */ |
4719 | switch (mnem_p[-1]) | |
29b0f896 | 4720 | { |
1c529385 LH |
4721 | case WORD_MNEM_SUFFIX: |
4722 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) | |
29b0f896 AM |
4723 | i.suffix = SHORT_MNEM_SUFFIX; |
4724 | else | |
1c529385 LH |
4725 | /* Fall through. */ |
4726 | case BYTE_MNEM_SUFFIX: | |
4727 | case QWORD_MNEM_SUFFIX: | |
4728 | i.suffix = mnem_p[-1]; | |
29b0f896 | 4729 | mnem_p[-1] = '\0'; |
d3ce72d0 | 4730 | current_templates = (const templates *) hash_find (op_hash, |
1c529385 LH |
4731 | mnemonic); |
4732 | break; | |
4733 | case SHORT_MNEM_SUFFIX: | |
4734 | case LONG_MNEM_SUFFIX: | |
4735 | if (!intel_syntax) | |
4736 | { | |
4737 | i.suffix = mnem_p[-1]; | |
4738 | mnem_p[-1] = '\0'; | |
4739 | current_templates = (const templates *) hash_find (op_hash, | |
4740 | mnemonic); | |
4741 | } | |
4742 | break; | |
4743 | ||
4744 | /* Intel Syntax. */ | |
4745 | case 'd': | |
4746 | if (intel_syntax) | |
4747 | { | |
4748 | if (intel_float_operand (mnemonic) == 1) | |
4749 | i.suffix = SHORT_MNEM_SUFFIX; | |
4750 | else | |
4751 | i.suffix = LONG_MNEM_SUFFIX; | |
4752 | mnem_p[-1] = '\0'; | |
4753 | current_templates = (const templates *) hash_find (op_hash, | |
4754 | mnemonic); | |
4755 | } | |
4756 | break; | |
29b0f896 | 4757 | } |
29b0f896 | 4758 | } |
1c529385 | 4759 | |
29b0f896 AM |
4760 | if (!current_templates) |
4761 | { | |
4762 | as_bad (_("no such instruction: `%s'"), token_start); | |
4763 | return NULL; | |
4764 | } | |
4765 | } | |
252b5132 | 4766 | |
40fb9820 L |
4767 | if (current_templates->start->opcode_modifier.jump |
4768 | || current_templates->start->opcode_modifier.jumpbyte) | |
29b0f896 AM |
4769 | { |
4770 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
4771 | predict taken and predict not taken respectively. | |
4772 | I'm not sure that branch hints actually do anything on loop | |
4773 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
4774 | may work in the future and it doesn't hurt to accept them | |
4775 | now. */ | |
4776 | if (l[0] == ',' && l[1] == 'p') | |
4777 | { | |
4778 | if (l[2] == 't') | |
4779 | { | |
4780 | if (!add_prefix (DS_PREFIX_OPCODE)) | |
4781 | return NULL; | |
4782 | l += 3; | |
4783 | } | |
4784 | else if (l[2] == 'n') | |
4785 | { | |
4786 | if (!add_prefix (CS_PREFIX_OPCODE)) | |
4787 | return NULL; | |
4788 | l += 3; | |
4789 | } | |
4790 | } | |
4791 | } | |
4792 | /* Any other comma loses. */ | |
4793 | if (*l == ',') | |
4794 | { | |
4795 | as_bad (_("invalid character %s in mnemonic"), | |
4796 | output_invalid (*l)); | |
4797 | return NULL; | |
4798 | } | |
252b5132 | 4799 | |
29b0f896 | 4800 | /* Check if instruction is supported on specified architecture. */ |
5c6af06e JB |
4801 | supported = 0; |
4802 | for (t = current_templates->start; t < current_templates->end; ++t) | |
4803 | { | |
c0f3af97 L |
4804 | supported |= cpu_flags_match (t); |
4805 | if (supported == CPU_FLAGS_PERFECT_MATCH) | |
548d0ee6 JB |
4806 | { |
4807 | if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT)) | |
4808 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
3629bb00 | 4809 | |
548d0ee6 JB |
4810 | return l; |
4811 | } | |
29b0f896 | 4812 | } |
3629bb00 | 4813 | |
548d0ee6 JB |
4814 | if (!(supported & CPU_FLAGS_64BIT_MATCH)) |
4815 | as_bad (flag_code == CODE_64BIT | |
4816 | ? _("`%s' is not supported in 64-bit mode") | |
4817 | : _("`%s' is only supported in 64-bit mode"), | |
4818 | current_templates->start->name); | |
4819 | else | |
4820 | as_bad (_("`%s' is not supported on `%s%s'"), | |
4821 | current_templates->start->name, | |
4822 | cpu_arch_name ? cpu_arch_name : default_arch, | |
4823 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); | |
252b5132 | 4824 | |
548d0ee6 | 4825 | return NULL; |
29b0f896 | 4826 | } |
252b5132 | 4827 | |
29b0f896 | 4828 | static char * |
e3bb37b5 | 4829 | parse_operands (char *l, const char *mnemonic) |
29b0f896 AM |
4830 | { |
4831 | char *token_start; | |
3138f287 | 4832 | |
29b0f896 AM |
4833 | /* 1 if operand is pending after ','. */ |
4834 | unsigned int expecting_operand = 0; | |
252b5132 | 4835 | |
29b0f896 AM |
4836 | /* Non-zero if operand parens not balanced. */ |
4837 | unsigned int paren_not_balanced; | |
4838 | ||
4839 | while (*l != END_OF_INSN) | |
4840 | { | |
4841 | /* Skip optional white space before operand. */ | |
4842 | if (is_space_char (*l)) | |
4843 | ++l; | |
d02603dc | 4844 | if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"') |
29b0f896 AM |
4845 | { |
4846 | as_bad (_("invalid character %s before operand %d"), | |
4847 | output_invalid (*l), | |
4848 | i.operands + 1); | |
4849 | return NULL; | |
4850 | } | |
d02603dc | 4851 | token_start = l; /* After white space. */ |
29b0f896 AM |
4852 | paren_not_balanced = 0; |
4853 | while (paren_not_balanced || *l != ',') | |
4854 | { | |
4855 | if (*l == END_OF_INSN) | |
4856 | { | |
4857 | if (paren_not_balanced) | |
4858 | { | |
4859 | if (!intel_syntax) | |
4860 | as_bad (_("unbalanced parenthesis in operand %d."), | |
4861 | i.operands + 1); | |
4862 | else | |
4863 | as_bad (_("unbalanced brackets in operand %d."), | |
4864 | i.operands + 1); | |
4865 | return NULL; | |
4866 | } | |
4867 | else | |
4868 | break; /* we are done */ | |
4869 | } | |
d02603dc | 4870 | else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"') |
29b0f896 AM |
4871 | { |
4872 | as_bad (_("invalid character %s in operand %d"), | |
4873 | output_invalid (*l), | |
4874 | i.operands + 1); | |
4875 | return NULL; | |
4876 | } | |
4877 | if (!intel_syntax) | |
4878 | { | |
4879 | if (*l == '(') | |
4880 | ++paren_not_balanced; | |
4881 | if (*l == ')') | |
4882 | --paren_not_balanced; | |
4883 | } | |
4884 | else | |
4885 | { | |
4886 | if (*l == '[') | |
4887 | ++paren_not_balanced; | |
4888 | if (*l == ']') | |
4889 | --paren_not_balanced; | |
4890 | } | |
4891 | l++; | |
4892 | } | |
4893 | if (l != token_start) | |
4894 | { /* Yes, we've read in another operand. */ | |
4895 | unsigned int operand_ok; | |
4896 | this_operand = i.operands++; | |
4897 | if (i.operands > MAX_OPERANDS) | |
4898 | { | |
4899 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
4900 | MAX_OPERANDS); | |
4901 | return NULL; | |
4902 | } | |
9d46ce34 | 4903 | i.types[this_operand].bitfield.unspecified = 1; |
29b0f896 AM |
4904 | /* Now parse operand adding info to 'i' as we go along. */ |
4905 | END_STRING_AND_SAVE (l); | |
4906 | ||
1286ab78 L |
4907 | if (i.mem_operands > 1) |
4908 | { | |
4909 | as_bad (_("too many memory references for `%s'"), | |
4910 | mnemonic); | |
4911 | return 0; | |
4912 | } | |
4913 | ||
29b0f896 AM |
4914 | if (intel_syntax) |
4915 | operand_ok = | |
4916 | i386_intel_operand (token_start, | |
4917 | intel_float_operand (mnemonic)); | |
4918 | else | |
a7619375 | 4919 | operand_ok = i386_att_operand (token_start); |
29b0f896 AM |
4920 | |
4921 | RESTORE_END_STRING (l); | |
4922 | if (!operand_ok) | |
4923 | return NULL; | |
4924 | } | |
4925 | else | |
4926 | { | |
4927 | if (expecting_operand) | |
4928 | { | |
4929 | expecting_operand_after_comma: | |
4930 | as_bad (_("expecting operand after ','; got nothing")); | |
4931 | return NULL; | |
4932 | } | |
4933 | if (*l == ',') | |
4934 | { | |
4935 | as_bad (_("expecting operand before ','; got nothing")); | |
4936 | return NULL; | |
4937 | } | |
4938 | } | |
7f3f1ea2 | 4939 | |
29b0f896 AM |
4940 | /* Now *l must be either ',' or END_OF_INSN. */ |
4941 | if (*l == ',') | |
4942 | { | |
4943 | if (*++l == END_OF_INSN) | |
4944 | { | |
4945 | /* Just skip it, if it's \n complain. */ | |
4946 | goto expecting_operand_after_comma; | |
4947 | } | |
4948 | expecting_operand = 1; | |
4949 | } | |
4950 | } | |
4951 | return l; | |
4952 | } | |
7f3f1ea2 | 4953 | |
050dfa73 | 4954 | static void |
4d456e3d | 4955 | swap_2_operands (int xchg1, int xchg2) |
050dfa73 MM |
4956 | { |
4957 | union i386_op temp_op; | |
40fb9820 | 4958 | i386_operand_type temp_type; |
c48dadc9 | 4959 | unsigned int temp_flags; |
050dfa73 | 4960 | enum bfd_reloc_code_real temp_reloc; |
4eed87de | 4961 | |
050dfa73 MM |
4962 | temp_type = i.types[xchg2]; |
4963 | i.types[xchg2] = i.types[xchg1]; | |
4964 | i.types[xchg1] = temp_type; | |
c48dadc9 JB |
4965 | |
4966 | temp_flags = i.flags[xchg2]; | |
4967 | i.flags[xchg2] = i.flags[xchg1]; | |
4968 | i.flags[xchg1] = temp_flags; | |
4969 | ||
050dfa73 MM |
4970 | temp_op = i.op[xchg2]; |
4971 | i.op[xchg2] = i.op[xchg1]; | |
4972 | i.op[xchg1] = temp_op; | |
c48dadc9 | 4973 | |
050dfa73 MM |
4974 | temp_reloc = i.reloc[xchg2]; |
4975 | i.reloc[xchg2] = i.reloc[xchg1]; | |
4976 | i.reloc[xchg1] = temp_reloc; | |
43234a1e L |
4977 | |
4978 | if (i.mask) | |
4979 | { | |
4980 | if (i.mask->operand == xchg1) | |
4981 | i.mask->operand = xchg2; | |
4982 | else if (i.mask->operand == xchg2) | |
4983 | i.mask->operand = xchg1; | |
4984 | } | |
4985 | if (i.broadcast) | |
4986 | { | |
4987 | if (i.broadcast->operand == xchg1) | |
4988 | i.broadcast->operand = xchg2; | |
4989 | else if (i.broadcast->operand == xchg2) | |
4990 | i.broadcast->operand = xchg1; | |
4991 | } | |
4992 | if (i.rounding) | |
4993 | { | |
4994 | if (i.rounding->operand == xchg1) | |
4995 | i.rounding->operand = xchg2; | |
4996 | else if (i.rounding->operand == xchg2) | |
4997 | i.rounding->operand = xchg1; | |
4998 | } | |
050dfa73 MM |
4999 | } |
5000 | ||
29b0f896 | 5001 | static void |
e3bb37b5 | 5002 | swap_operands (void) |
29b0f896 | 5003 | { |
b7c61d9a | 5004 | switch (i.operands) |
050dfa73 | 5005 | { |
c0f3af97 | 5006 | case 5: |
b7c61d9a | 5007 | case 4: |
4d456e3d | 5008 | swap_2_operands (1, i.operands - 2); |
1a0670f3 | 5009 | /* Fall through. */ |
b7c61d9a L |
5010 | case 3: |
5011 | case 2: | |
4d456e3d | 5012 | swap_2_operands (0, i.operands - 1); |
b7c61d9a L |
5013 | break; |
5014 | default: | |
5015 | abort (); | |
29b0f896 | 5016 | } |
29b0f896 AM |
5017 | |
5018 | if (i.mem_operands == 2) | |
5019 | { | |
5020 | const seg_entry *temp_seg; | |
5021 | temp_seg = i.seg[0]; | |
5022 | i.seg[0] = i.seg[1]; | |
5023 | i.seg[1] = temp_seg; | |
5024 | } | |
5025 | } | |
252b5132 | 5026 | |
29b0f896 AM |
5027 | /* Try to ensure constant immediates are represented in the smallest |
5028 | opcode possible. */ | |
5029 | static void | |
e3bb37b5 | 5030 | optimize_imm (void) |
29b0f896 AM |
5031 | { |
5032 | char guess_suffix = 0; | |
5033 | int op; | |
252b5132 | 5034 | |
29b0f896 AM |
5035 | if (i.suffix) |
5036 | guess_suffix = i.suffix; | |
5037 | else if (i.reg_operands) | |
5038 | { | |
5039 | /* Figure out a suffix from the last register operand specified. | |
75e5731b JB |
5040 | We can't do this properly yet, i.e. excluding special register |
5041 | instances, but the following works for instructions with | |
5042 | immediates. In any case, we can't set i.suffix yet. */ | |
29b0f896 | 5043 | for (op = i.operands; --op >= 0;) |
bab6aec1 JB |
5044 | if (i.types[op].bitfield.class != Reg) |
5045 | continue; | |
5046 | else if (i.types[op].bitfield.byte) | |
7ab9ffdd | 5047 | { |
40fb9820 L |
5048 | guess_suffix = BYTE_MNEM_SUFFIX; |
5049 | break; | |
5050 | } | |
bab6aec1 | 5051 | else if (i.types[op].bitfield.word) |
252b5132 | 5052 | { |
40fb9820 L |
5053 | guess_suffix = WORD_MNEM_SUFFIX; |
5054 | break; | |
5055 | } | |
bab6aec1 | 5056 | else if (i.types[op].bitfield.dword) |
40fb9820 L |
5057 | { |
5058 | guess_suffix = LONG_MNEM_SUFFIX; | |
5059 | break; | |
5060 | } | |
bab6aec1 | 5061 | else if (i.types[op].bitfield.qword) |
40fb9820 L |
5062 | { |
5063 | guess_suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 | 5064 | break; |
252b5132 | 5065 | } |
29b0f896 AM |
5066 | } |
5067 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) | |
5068 | guess_suffix = WORD_MNEM_SUFFIX; | |
5069 | ||
5070 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 5071 | if (operand_type_check (i.types[op], imm)) |
29b0f896 AM |
5072 | { |
5073 | switch (i.op[op].imms->X_op) | |
252b5132 | 5074 | { |
29b0f896 AM |
5075 | case O_constant: |
5076 | /* If a suffix is given, this operand may be shortened. */ | |
5077 | switch (guess_suffix) | |
252b5132 | 5078 | { |
29b0f896 | 5079 | case LONG_MNEM_SUFFIX: |
40fb9820 L |
5080 | i.types[op].bitfield.imm32 = 1; |
5081 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
5082 | break; |
5083 | case WORD_MNEM_SUFFIX: | |
40fb9820 L |
5084 | i.types[op].bitfield.imm16 = 1; |
5085 | i.types[op].bitfield.imm32 = 1; | |
5086 | i.types[op].bitfield.imm32s = 1; | |
5087 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
5088 | break; |
5089 | case BYTE_MNEM_SUFFIX: | |
40fb9820 L |
5090 | i.types[op].bitfield.imm8 = 1; |
5091 | i.types[op].bitfield.imm8s = 1; | |
5092 | i.types[op].bitfield.imm16 = 1; | |
5093 | i.types[op].bitfield.imm32 = 1; | |
5094 | i.types[op].bitfield.imm32s = 1; | |
5095 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 | 5096 | break; |
252b5132 | 5097 | } |
252b5132 | 5098 | |
29b0f896 AM |
5099 | /* If this operand is at most 16 bits, convert it |
5100 | to a signed 16 bit number before trying to see | |
5101 | whether it will fit in an even smaller size. | |
5102 | This allows a 16-bit operand such as $0xffe0 to | |
5103 | be recognised as within Imm8S range. */ | |
40fb9820 | 5104 | if ((i.types[op].bitfield.imm16) |
29b0f896 | 5105 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) |
252b5132 | 5106 | { |
29b0f896 AM |
5107 | i.op[op].imms->X_add_number = |
5108 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
5109 | } | |
a28def75 L |
5110 | #ifdef BFD64 |
5111 | /* Store 32-bit immediate in 64-bit for 64-bit BFD. */ | |
40fb9820 | 5112 | if ((i.types[op].bitfield.imm32) |
29b0f896 AM |
5113 | && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) |
5114 | == 0)) | |
5115 | { | |
5116 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number | |
5117 | ^ ((offsetT) 1 << 31)) | |
5118 | - ((offsetT) 1 << 31)); | |
5119 | } | |
a28def75 | 5120 | #endif |
40fb9820 | 5121 | i.types[op] |
c6fb90c8 L |
5122 | = operand_type_or (i.types[op], |
5123 | smallest_imm_type (i.op[op].imms->X_add_number)); | |
252b5132 | 5124 | |
29b0f896 AM |
5125 | /* We must avoid matching of Imm32 templates when 64bit |
5126 | only immediate is available. */ | |
5127 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
40fb9820 | 5128 | i.types[op].bitfield.imm32 = 0; |
29b0f896 | 5129 | break; |
252b5132 | 5130 | |
29b0f896 AM |
5131 | case O_absent: |
5132 | case O_register: | |
5133 | abort (); | |
5134 | ||
5135 | /* Symbols and expressions. */ | |
5136 | default: | |
9cd96992 JB |
5137 | /* Convert symbolic operand to proper sizes for matching, but don't |
5138 | prevent matching a set of insns that only supports sizes other | |
5139 | than those matching the insn suffix. */ | |
5140 | { | |
40fb9820 | 5141 | i386_operand_type mask, allowed; |
d3ce72d0 | 5142 | const insn_template *t; |
9cd96992 | 5143 | |
0dfbf9d7 L |
5144 | operand_type_set (&mask, 0); |
5145 | operand_type_set (&allowed, 0); | |
40fb9820 | 5146 | |
4eed87de AM |
5147 | for (t = current_templates->start; |
5148 | t < current_templates->end; | |
5149 | ++t) | |
bab6aec1 JB |
5150 | { |
5151 | allowed = operand_type_or (allowed, t->operand_types[op]); | |
5152 | allowed = operand_type_and (allowed, anyimm); | |
5153 | } | |
9cd96992 JB |
5154 | switch (guess_suffix) |
5155 | { | |
5156 | case QWORD_MNEM_SUFFIX: | |
40fb9820 L |
5157 | mask.bitfield.imm64 = 1; |
5158 | mask.bitfield.imm32s = 1; | |
9cd96992 JB |
5159 | break; |
5160 | case LONG_MNEM_SUFFIX: | |
40fb9820 | 5161 | mask.bitfield.imm32 = 1; |
9cd96992 JB |
5162 | break; |
5163 | case WORD_MNEM_SUFFIX: | |
40fb9820 | 5164 | mask.bitfield.imm16 = 1; |
9cd96992 JB |
5165 | break; |
5166 | case BYTE_MNEM_SUFFIX: | |
40fb9820 | 5167 | mask.bitfield.imm8 = 1; |
9cd96992 JB |
5168 | break; |
5169 | default: | |
9cd96992 JB |
5170 | break; |
5171 | } | |
c6fb90c8 | 5172 | allowed = operand_type_and (mask, allowed); |
0dfbf9d7 | 5173 | if (!operand_type_all_zero (&allowed)) |
c6fb90c8 | 5174 | i.types[op] = operand_type_and (i.types[op], mask); |
9cd96992 | 5175 | } |
29b0f896 | 5176 | break; |
252b5132 | 5177 | } |
29b0f896 AM |
5178 | } |
5179 | } | |
47926f60 | 5180 | |
29b0f896 AM |
5181 | /* Try to use the smallest displacement type too. */ |
5182 | static void | |
e3bb37b5 | 5183 | optimize_disp (void) |
29b0f896 AM |
5184 | { |
5185 | int op; | |
3e73aa7c | 5186 | |
29b0f896 | 5187 | for (op = i.operands; --op >= 0;) |
40fb9820 | 5188 | if (operand_type_check (i.types[op], disp)) |
252b5132 | 5189 | { |
b300c311 | 5190 | if (i.op[op].disps->X_op == O_constant) |
252b5132 | 5191 | { |
91d6fa6a | 5192 | offsetT op_disp = i.op[op].disps->X_add_number; |
29b0f896 | 5193 | |
40fb9820 | 5194 | if (i.types[op].bitfield.disp16 |
91d6fa6a | 5195 | && (op_disp & ~(offsetT) 0xffff) == 0) |
b300c311 L |
5196 | { |
5197 | /* If this operand is at most 16 bits, convert | |
5198 | to a signed 16 bit number and don't use 64bit | |
5199 | displacement. */ | |
91d6fa6a | 5200 | op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000); |
40fb9820 | 5201 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 5202 | } |
a28def75 L |
5203 | #ifdef BFD64 |
5204 | /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */ | |
40fb9820 | 5205 | if (i.types[op].bitfield.disp32 |
91d6fa6a | 5206 | && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0) |
b300c311 L |
5207 | { |
5208 | /* If this operand is at most 32 bits, convert | |
5209 | to a signed 32 bit number and don't use 64bit | |
5210 | displacement. */ | |
91d6fa6a NC |
5211 | op_disp &= (((offsetT) 2 << 31) - 1); |
5212 | op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
40fb9820 | 5213 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 5214 | } |
a28def75 | 5215 | #endif |
91d6fa6a | 5216 | if (!op_disp && i.types[op].bitfield.baseindex) |
b300c311 | 5217 | { |
40fb9820 L |
5218 | i.types[op].bitfield.disp8 = 0; |
5219 | i.types[op].bitfield.disp16 = 0; | |
5220 | i.types[op].bitfield.disp32 = 0; | |
5221 | i.types[op].bitfield.disp32s = 0; | |
5222 | i.types[op].bitfield.disp64 = 0; | |
b300c311 L |
5223 | i.op[op].disps = 0; |
5224 | i.disp_operands--; | |
5225 | } | |
5226 | else if (flag_code == CODE_64BIT) | |
5227 | { | |
91d6fa6a | 5228 | if (fits_in_signed_long (op_disp)) |
28a9d8f5 | 5229 | { |
40fb9820 L |
5230 | i.types[op].bitfield.disp64 = 0; |
5231 | i.types[op].bitfield.disp32s = 1; | |
28a9d8f5 | 5232 | } |
0e1147d9 | 5233 | if (i.prefix[ADDR_PREFIX] |
91d6fa6a | 5234 | && fits_in_unsigned_long (op_disp)) |
40fb9820 | 5235 | i.types[op].bitfield.disp32 = 1; |
b300c311 | 5236 | } |
40fb9820 L |
5237 | if ((i.types[op].bitfield.disp32 |
5238 | || i.types[op].bitfield.disp32s | |
5239 | || i.types[op].bitfield.disp16) | |
b5014f7a | 5240 | && fits_in_disp8 (op_disp)) |
40fb9820 | 5241 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 5242 | } |
67a4f2b7 AO |
5243 | else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
5244 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) | |
5245 | { | |
5246 | fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, | |
5247 | i.op[op].disps, 0, i.reloc[op]); | |
40fb9820 L |
5248 | i.types[op].bitfield.disp8 = 0; |
5249 | i.types[op].bitfield.disp16 = 0; | |
5250 | i.types[op].bitfield.disp32 = 0; | |
5251 | i.types[op].bitfield.disp32s = 0; | |
5252 | i.types[op].bitfield.disp64 = 0; | |
67a4f2b7 AO |
5253 | } |
5254 | else | |
b300c311 | 5255 | /* We only support 64bit displacement on constants. */ |
40fb9820 | 5256 | i.types[op].bitfield.disp64 = 0; |
252b5132 | 5257 | } |
29b0f896 AM |
5258 | } |
5259 | ||
4a1b91ea L |
5260 | /* Return 1 if there is a match in broadcast bytes between operand |
5261 | GIVEN and instruction template T. */ | |
5262 | ||
5263 | static INLINE int | |
5264 | match_broadcast_size (const insn_template *t, unsigned int given) | |
5265 | { | |
5266 | return ((t->opcode_modifier.broadcast == BYTE_BROADCAST | |
5267 | && i.types[given].bitfield.byte) | |
5268 | || (t->opcode_modifier.broadcast == WORD_BROADCAST | |
5269 | && i.types[given].bitfield.word) | |
5270 | || (t->opcode_modifier.broadcast == DWORD_BROADCAST | |
5271 | && i.types[given].bitfield.dword) | |
5272 | || (t->opcode_modifier.broadcast == QWORD_BROADCAST | |
5273 | && i.types[given].bitfield.qword)); | |
5274 | } | |
5275 | ||
6c30d220 L |
5276 | /* Check if operands are valid for the instruction. */ |
5277 | ||
5278 | static int | |
5279 | check_VecOperands (const insn_template *t) | |
5280 | { | |
43234a1e | 5281 | unsigned int op; |
e2195274 JB |
5282 | i386_cpu_flags cpu; |
5283 | static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS; | |
5284 | ||
5285 | /* Templates allowing for ZMMword as well as YMMword and/or XMMword for | |
5286 | any one operand are implicity requiring AVX512VL support if the actual | |
5287 | operand size is YMMword or XMMword. Since this function runs after | |
5288 | template matching, there's no need to check for YMMword/XMMword in | |
5289 | the template. */ | |
5290 | cpu = cpu_flags_and (t->cpu_flags, avx512); | |
5291 | if (!cpu_flags_all_zero (&cpu) | |
5292 | && !t->cpu_flags.bitfield.cpuavx512vl | |
5293 | && !cpu_arch_flags.bitfield.cpuavx512vl) | |
5294 | { | |
5295 | for (op = 0; op < t->operands; ++op) | |
5296 | { | |
5297 | if (t->operand_types[op].bitfield.zmmword | |
5298 | && (i.types[op].bitfield.ymmword | |
5299 | || i.types[op].bitfield.xmmword)) | |
5300 | { | |
5301 | i.error = unsupported; | |
5302 | return 1; | |
5303 | } | |
5304 | } | |
5305 | } | |
43234a1e | 5306 | |
6c30d220 L |
5307 | /* Without VSIB byte, we can't have a vector register for index. */ |
5308 | if (!t->opcode_modifier.vecsib | |
5309 | && i.index_reg | |
1b54b8d7 JB |
5310 | && (i.index_reg->reg_type.bitfield.xmmword |
5311 | || i.index_reg->reg_type.bitfield.ymmword | |
5312 | || i.index_reg->reg_type.bitfield.zmmword)) | |
6c30d220 L |
5313 | { |
5314 | i.error = unsupported_vector_index_register; | |
5315 | return 1; | |
5316 | } | |
5317 | ||
ad8ecc81 MZ |
5318 | /* Check if default mask is allowed. */ |
5319 | if (t->opcode_modifier.nodefmask | |
5320 | && (!i.mask || i.mask->mask->reg_num == 0)) | |
5321 | { | |
5322 | i.error = no_default_mask; | |
5323 | return 1; | |
5324 | } | |
5325 | ||
7bab8ab5 JB |
5326 | /* For VSIB byte, we need a vector register for index, and all vector |
5327 | registers must be distinct. */ | |
5328 | if (t->opcode_modifier.vecsib) | |
5329 | { | |
5330 | if (!i.index_reg | |
6c30d220 | 5331 | || !((t->opcode_modifier.vecsib == VecSIB128 |
1b54b8d7 | 5332 | && i.index_reg->reg_type.bitfield.xmmword) |
6c30d220 | 5333 | || (t->opcode_modifier.vecsib == VecSIB256 |
1b54b8d7 | 5334 | && i.index_reg->reg_type.bitfield.ymmword) |
43234a1e | 5335 | || (t->opcode_modifier.vecsib == VecSIB512 |
1b54b8d7 | 5336 | && i.index_reg->reg_type.bitfield.zmmword))) |
7bab8ab5 JB |
5337 | { |
5338 | i.error = invalid_vsib_address; | |
5339 | return 1; | |
5340 | } | |
5341 | ||
43234a1e L |
5342 | gas_assert (i.reg_operands == 2 || i.mask); |
5343 | if (i.reg_operands == 2 && !i.mask) | |
5344 | { | |
3528c362 | 5345 | gas_assert (i.types[0].bitfield.class == RegSIMD); |
1b54b8d7 JB |
5346 | gas_assert (i.types[0].bitfield.xmmword |
5347 | || i.types[0].bitfield.ymmword); | |
3528c362 | 5348 | gas_assert (i.types[2].bitfield.class == RegSIMD); |
1b54b8d7 JB |
5349 | gas_assert (i.types[2].bitfield.xmmword |
5350 | || i.types[2].bitfield.ymmword); | |
43234a1e L |
5351 | if (operand_check == check_none) |
5352 | return 0; | |
5353 | if (register_number (i.op[0].regs) | |
5354 | != register_number (i.index_reg) | |
5355 | && register_number (i.op[2].regs) | |
5356 | != register_number (i.index_reg) | |
5357 | && register_number (i.op[0].regs) | |
5358 | != register_number (i.op[2].regs)) | |
5359 | return 0; | |
5360 | if (operand_check == check_error) | |
5361 | { | |
5362 | i.error = invalid_vector_register_set; | |
5363 | return 1; | |
5364 | } | |
5365 | as_warn (_("mask, index, and destination registers should be distinct")); | |
5366 | } | |
8444f82a MZ |
5367 | else if (i.reg_operands == 1 && i.mask) |
5368 | { | |
3528c362 | 5369 | if (i.types[1].bitfield.class == RegSIMD |
1b54b8d7 JB |
5370 | && (i.types[1].bitfield.xmmword |
5371 | || i.types[1].bitfield.ymmword | |
5372 | || i.types[1].bitfield.zmmword) | |
8444f82a MZ |
5373 | && (register_number (i.op[1].regs) |
5374 | == register_number (i.index_reg))) | |
5375 | { | |
5376 | if (operand_check == check_error) | |
5377 | { | |
5378 | i.error = invalid_vector_register_set; | |
5379 | return 1; | |
5380 | } | |
5381 | if (operand_check != check_none) | |
5382 | as_warn (_("index and destination registers should be distinct")); | |
5383 | } | |
5384 | } | |
43234a1e | 5385 | } |
7bab8ab5 | 5386 | |
43234a1e L |
5387 | /* Check if broadcast is supported by the instruction and is applied |
5388 | to the memory operand. */ | |
5389 | if (i.broadcast) | |
5390 | { | |
8e6e0792 | 5391 | i386_operand_type type, overlap; |
43234a1e L |
5392 | |
5393 | /* Check if specified broadcast is supported in this instruction, | |
4a1b91ea | 5394 | and its broadcast bytes match the memory operand. */ |
32546502 | 5395 | op = i.broadcast->operand; |
8e6e0792 | 5396 | if (!t->opcode_modifier.broadcast |
c48dadc9 | 5397 | || !(i.flags[op] & Operand_Mem) |
c39e5b26 | 5398 | || (!i.types[op].bitfield.unspecified |
4a1b91ea | 5399 | && !match_broadcast_size (t, op))) |
43234a1e L |
5400 | { |
5401 | bad_broadcast: | |
5402 | i.error = unsupported_broadcast; | |
5403 | return 1; | |
5404 | } | |
8e6e0792 | 5405 | |
4a1b91ea L |
5406 | i.broadcast->bytes = ((1 << (t->opcode_modifier.broadcast - 1)) |
5407 | * i.broadcast->type); | |
8e6e0792 | 5408 | operand_type_set (&type, 0); |
4a1b91ea | 5409 | switch (i.broadcast->bytes) |
8e6e0792 | 5410 | { |
4a1b91ea L |
5411 | case 2: |
5412 | type.bitfield.word = 1; | |
5413 | break; | |
5414 | case 4: | |
5415 | type.bitfield.dword = 1; | |
5416 | break; | |
8e6e0792 JB |
5417 | case 8: |
5418 | type.bitfield.qword = 1; | |
5419 | break; | |
5420 | case 16: | |
5421 | type.bitfield.xmmword = 1; | |
5422 | break; | |
5423 | case 32: | |
5424 | type.bitfield.ymmword = 1; | |
5425 | break; | |
5426 | case 64: | |
5427 | type.bitfield.zmmword = 1; | |
5428 | break; | |
5429 | default: | |
5430 | goto bad_broadcast; | |
5431 | } | |
5432 | ||
5433 | overlap = operand_type_and (type, t->operand_types[op]); | |
5434 | if (operand_type_all_zero (&overlap)) | |
5435 | goto bad_broadcast; | |
5436 | ||
5437 | if (t->opcode_modifier.checkregsize) | |
5438 | { | |
5439 | unsigned int j; | |
5440 | ||
e2195274 | 5441 | type.bitfield.baseindex = 1; |
8e6e0792 JB |
5442 | for (j = 0; j < i.operands; ++j) |
5443 | { | |
5444 | if (j != op | |
5445 | && !operand_type_register_match(i.types[j], | |
5446 | t->operand_types[j], | |
5447 | type, | |
5448 | t->operand_types[op])) | |
5449 | goto bad_broadcast; | |
5450 | } | |
5451 | } | |
43234a1e L |
5452 | } |
5453 | /* If broadcast is supported in this instruction, we need to check if | |
5454 | operand of one-element size isn't specified without broadcast. */ | |
5455 | else if (t->opcode_modifier.broadcast && i.mem_operands) | |
5456 | { | |
5457 | /* Find memory operand. */ | |
5458 | for (op = 0; op < i.operands; op++) | |
8dc0818e | 5459 | if (i.flags[op] & Operand_Mem) |
43234a1e L |
5460 | break; |
5461 | gas_assert (op < i.operands); | |
5462 | /* Check size of the memory operand. */ | |
4a1b91ea | 5463 | if (match_broadcast_size (t, op)) |
43234a1e L |
5464 | { |
5465 | i.error = broadcast_needed; | |
5466 | return 1; | |
5467 | } | |
5468 | } | |
c39e5b26 JB |
5469 | else |
5470 | op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */ | |
43234a1e L |
5471 | |
5472 | /* Check if requested masking is supported. */ | |
ae2387fe | 5473 | if (i.mask) |
43234a1e | 5474 | { |
ae2387fe JB |
5475 | switch (t->opcode_modifier.masking) |
5476 | { | |
5477 | case BOTH_MASKING: | |
5478 | break; | |
5479 | case MERGING_MASKING: | |
5480 | if (i.mask->zeroing) | |
5481 | { | |
5482 | case 0: | |
5483 | i.error = unsupported_masking; | |
5484 | return 1; | |
5485 | } | |
5486 | break; | |
5487 | case DYNAMIC_MASKING: | |
5488 | /* Memory destinations allow only merging masking. */ | |
5489 | if (i.mask->zeroing && i.mem_operands) | |
5490 | { | |
5491 | /* Find memory operand. */ | |
5492 | for (op = 0; op < i.operands; op++) | |
c48dadc9 | 5493 | if (i.flags[op] & Operand_Mem) |
ae2387fe JB |
5494 | break; |
5495 | gas_assert (op < i.operands); | |
5496 | if (op == i.operands - 1) | |
5497 | { | |
5498 | i.error = unsupported_masking; | |
5499 | return 1; | |
5500 | } | |
5501 | } | |
5502 | break; | |
5503 | default: | |
5504 | abort (); | |
5505 | } | |
43234a1e L |
5506 | } |
5507 | ||
5508 | /* Check if masking is applied to dest operand. */ | |
5509 | if (i.mask && (i.mask->operand != (int) (i.operands - 1))) | |
5510 | { | |
5511 | i.error = mask_not_on_destination; | |
5512 | return 1; | |
5513 | } | |
5514 | ||
43234a1e L |
5515 | /* Check RC/SAE. */ |
5516 | if (i.rounding) | |
5517 | { | |
a80195f1 JB |
5518 | if (!t->opcode_modifier.sae |
5519 | || (i.rounding->type != saeonly && !t->opcode_modifier.staticrounding)) | |
43234a1e L |
5520 | { |
5521 | i.error = unsupported_rc_sae; | |
5522 | return 1; | |
5523 | } | |
5524 | /* If the instruction has several immediate operands and one of | |
5525 | them is rounding, the rounding operand should be the last | |
5526 | immediate operand. */ | |
5527 | if (i.imm_operands > 1 | |
5528 | && i.rounding->operand != (int) (i.imm_operands - 1)) | |
7bab8ab5 | 5529 | { |
43234a1e | 5530 | i.error = rc_sae_operand_not_last_imm; |
7bab8ab5 JB |
5531 | return 1; |
5532 | } | |
6c30d220 L |
5533 | } |
5534 | ||
43234a1e | 5535 | /* Check vector Disp8 operand. */ |
b5014f7a JB |
5536 | if (t->opcode_modifier.disp8memshift |
5537 | && i.disp_encoding != disp_encoding_32bit) | |
43234a1e L |
5538 | { |
5539 | if (i.broadcast) | |
4a1b91ea | 5540 | i.memshift = t->opcode_modifier.broadcast - 1; |
7091c612 | 5541 | else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL) |
43234a1e | 5542 | i.memshift = t->opcode_modifier.disp8memshift; |
7091c612 JB |
5543 | else |
5544 | { | |
5545 | const i386_operand_type *type = NULL; | |
5546 | ||
5547 | i.memshift = 0; | |
5548 | for (op = 0; op < i.operands; op++) | |
8dc0818e | 5549 | if (i.flags[op] & Operand_Mem) |
7091c612 | 5550 | { |
4174bfff JB |
5551 | if (t->opcode_modifier.evex == EVEXLIG) |
5552 | i.memshift = 2 + (i.suffix == QWORD_MNEM_SUFFIX); | |
5553 | else if (t->operand_types[op].bitfield.xmmword | |
5554 | + t->operand_types[op].bitfield.ymmword | |
5555 | + t->operand_types[op].bitfield.zmmword <= 1) | |
7091c612 JB |
5556 | type = &t->operand_types[op]; |
5557 | else if (!i.types[op].bitfield.unspecified) | |
5558 | type = &i.types[op]; | |
5559 | } | |
3528c362 | 5560 | else if (i.types[op].bitfield.class == RegSIMD |
4174bfff | 5561 | && t->opcode_modifier.evex != EVEXLIG) |
7091c612 JB |
5562 | { |
5563 | if (i.types[op].bitfield.zmmword) | |
5564 | i.memshift = 6; | |
5565 | else if (i.types[op].bitfield.ymmword && i.memshift < 5) | |
5566 | i.memshift = 5; | |
5567 | else if (i.types[op].bitfield.xmmword && i.memshift < 4) | |
5568 | i.memshift = 4; | |
5569 | } | |
5570 | ||
5571 | if (type) | |
5572 | { | |
5573 | if (type->bitfield.zmmword) | |
5574 | i.memshift = 6; | |
5575 | else if (type->bitfield.ymmword) | |
5576 | i.memshift = 5; | |
5577 | else if (type->bitfield.xmmword) | |
5578 | i.memshift = 4; | |
5579 | } | |
5580 | ||
5581 | /* For the check in fits_in_disp8(). */ | |
5582 | if (i.memshift == 0) | |
5583 | i.memshift = -1; | |
5584 | } | |
43234a1e L |
5585 | |
5586 | for (op = 0; op < i.operands; op++) | |
5587 | if (operand_type_check (i.types[op], disp) | |
5588 | && i.op[op].disps->X_op == O_constant) | |
5589 | { | |
b5014f7a | 5590 | if (fits_in_disp8 (i.op[op].disps->X_add_number)) |
43234a1e | 5591 | { |
b5014f7a JB |
5592 | i.types[op].bitfield.disp8 = 1; |
5593 | return 0; | |
43234a1e | 5594 | } |
b5014f7a | 5595 | i.types[op].bitfield.disp8 = 0; |
43234a1e L |
5596 | } |
5597 | } | |
b5014f7a JB |
5598 | |
5599 | i.memshift = 0; | |
43234a1e | 5600 | |
6c30d220 L |
5601 | return 0; |
5602 | } | |
5603 | ||
43f3e2ee | 5604 | /* Check if operands are valid for the instruction. Update VEX |
a683cc34 SP |
5605 | operand types. */ |
5606 | ||
5607 | static int | |
5608 | VEX_check_operands (const insn_template *t) | |
5609 | { | |
86fa6981 | 5610 | if (i.vec_encoding == vex_encoding_evex) |
43234a1e | 5611 | { |
86fa6981 | 5612 | /* This instruction must be encoded with EVEX prefix. */ |
e771e7c9 | 5613 | if (!is_evex_encoding (t)) |
86fa6981 L |
5614 | { |
5615 | i.error = unsupported; | |
5616 | return 1; | |
5617 | } | |
5618 | return 0; | |
43234a1e L |
5619 | } |
5620 | ||
a683cc34 | 5621 | if (!t->opcode_modifier.vex) |
86fa6981 L |
5622 | { |
5623 | /* This instruction template doesn't have VEX prefix. */ | |
5624 | if (i.vec_encoding != vex_encoding_default) | |
5625 | { | |
5626 | i.error = unsupported; | |
5627 | return 1; | |
5628 | } | |
5629 | return 0; | |
5630 | } | |
a683cc34 | 5631 | |
9d3bf266 JB |
5632 | /* Check the special Imm4 cases; must be the first operand. */ |
5633 | if (t->cpu_flags.bitfield.cpuxop && t->operands == 5) | |
a683cc34 SP |
5634 | { |
5635 | if (i.op[0].imms->X_op != O_constant | |
5636 | || !fits_in_imm4 (i.op[0].imms->X_add_number)) | |
891edac4 | 5637 | { |
a65babc9 | 5638 | i.error = bad_imm4; |
891edac4 L |
5639 | return 1; |
5640 | } | |
a683cc34 | 5641 | |
9d3bf266 JB |
5642 | /* Turn off Imm<N> so that update_imm won't complain. */ |
5643 | operand_type_set (&i.types[0], 0); | |
a683cc34 SP |
5644 | } |
5645 | ||
5646 | return 0; | |
5647 | } | |
5648 | ||
d3ce72d0 | 5649 | static const insn_template * |
83b16ac6 | 5650 | match_template (char mnem_suffix) |
29b0f896 AM |
5651 | { |
5652 | /* Points to template once we've found it. */ | |
d3ce72d0 | 5653 | const insn_template *t; |
40fb9820 | 5654 | i386_operand_type overlap0, overlap1, overlap2, overlap3; |
c0f3af97 | 5655 | i386_operand_type overlap4; |
29b0f896 | 5656 | unsigned int found_reverse_match; |
dc2be329 | 5657 | i386_opcode_modifier suffix_check; |
40fb9820 | 5658 | i386_operand_type operand_types [MAX_OPERANDS]; |
539e75ad | 5659 | int addr_prefix_disp; |
a5c311ca | 5660 | unsigned int j; |
3ac21baa | 5661 | unsigned int found_cpu_match, size_match; |
45664ddb | 5662 | unsigned int check_register; |
5614d22c | 5663 | enum i386_error specific_error = 0; |
29b0f896 | 5664 | |
c0f3af97 L |
5665 | #if MAX_OPERANDS != 5 |
5666 | # error "MAX_OPERANDS must be 5." | |
f48ff2ae L |
5667 | #endif |
5668 | ||
29b0f896 | 5669 | found_reverse_match = 0; |
539e75ad | 5670 | addr_prefix_disp = -1; |
40fb9820 | 5671 | |
dc2be329 | 5672 | /* Prepare for mnemonic suffix check. */ |
40fb9820 | 5673 | memset (&suffix_check, 0, sizeof (suffix_check)); |
dc2be329 L |
5674 | switch (mnem_suffix) |
5675 | { | |
5676 | case BYTE_MNEM_SUFFIX: | |
5677 | suffix_check.no_bsuf = 1; | |
5678 | break; | |
5679 | case WORD_MNEM_SUFFIX: | |
5680 | suffix_check.no_wsuf = 1; | |
5681 | break; | |
5682 | case SHORT_MNEM_SUFFIX: | |
5683 | suffix_check.no_ssuf = 1; | |
5684 | break; | |
5685 | case LONG_MNEM_SUFFIX: | |
5686 | suffix_check.no_lsuf = 1; | |
5687 | break; | |
5688 | case QWORD_MNEM_SUFFIX: | |
5689 | suffix_check.no_qsuf = 1; | |
5690 | break; | |
5691 | default: | |
5692 | /* NB: In Intel syntax, normally we can check for memory operand | |
5693 | size when there is no mnemonic suffix. But jmp and call have | |
5694 | 2 different encodings with Dword memory operand size, one with | |
5695 | No_ldSuf and the other without. i.suffix is set to | |
5696 | LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */ | |
5697 | if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX) | |
5698 | suffix_check.no_ldsuf = 1; | |
83b16ac6 JB |
5699 | } |
5700 | ||
01559ecc L |
5701 | /* Must have right number of operands. */ |
5702 | i.error = number_of_operands_mismatch; | |
5703 | ||
45aa61fe | 5704 | for (t = current_templates->start; t < current_templates->end; t++) |
29b0f896 | 5705 | { |
539e75ad | 5706 | addr_prefix_disp = -1; |
dbbc8b7e | 5707 | found_reverse_match = 0; |
539e75ad | 5708 | |
29b0f896 AM |
5709 | if (i.operands != t->operands) |
5710 | continue; | |
5711 | ||
50aecf8c | 5712 | /* Check processor support. */ |
a65babc9 | 5713 | i.error = unsupported; |
c0f3af97 L |
5714 | found_cpu_match = (cpu_flags_match (t) |
5715 | == CPU_FLAGS_PERFECT_MATCH); | |
50aecf8c L |
5716 | if (!found_cpu_match) |
5717 | continue; | |
5718 | ||
e1d4d893 | 5719 | /* Check AT&T mnemonic. */ |
a65babc9 | 5720 | i.error = unsupported_with_intel_mnemonic; |
e1d4d893 | 5721 | if (intel_mnemonic && t->opcode_modifier.attmnemonic) |
1efbbeb4 L |
5722 | continue; |
5723 | ||
e92bae62 | 5724 | /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */ |
a65babc9 | 5725 | i.error = unsupported_syntax; |
5c07affc | 5726 | if ((intel_syntax && t->opcode_modifier.attsyntax) |
e92bae62 L |
5727 | || (!intel_syntax && t->opcode_modifier.intelsyntax) |
5728 | || (intel64 && t->opcode_modifier.amd64) | |
5729 | || (!intel64 && t->opcode_modifier.intel64)) | |
1efbbeb4 L |
5730 | continue; |
5731 | ||
dc2be329 | 5732 | /* Check the suffix. */ |
a65babc9 | 5733 | i.error = invalid_instruction_suffix; |
dc2be329 L |
5734 | if ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf) |
5735 | || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf) | |
5736 | || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf) | |
5737 | || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf) | |
5738 | || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf) | |
5739 | || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)) | |
83b16ac6 | 5740 | continue; |
29b0f896 | 5741 | |
3ac21baa JB |
5742 | size_match = operand_size_match (t); |
5743 | if (!size_match) | |
7d5e4556 | 5744 | continue; |
539e75ad | 5745 | |
5c07affc L |
5746 | for (j = 0; j < MAX_OPERANDS; j++) |
5747 | operand_types[j] = t->operand_types[j]; | |
5748 | ||
45aa61fe AM |
5749 | /* In general, don't allow 64-bit operands in 32-bit mode. */ |
5750 | if (i.suffix == QWORD_MNEM_SUFFIX | |
5751 | && flag_code != CODE_64BIT | |
5752 | && (intel_syntax | |
40fb9820 | 5753 | ? (!t->opcode_modifier.ignoresize |
625cbd7a | 5754 | && !t->opcode_modifier.broadcast |
45aa61fe AM |
5755 | && !intel_float_operand (t->name)) |
5756 | : intel_float_operand (t->name) != 2) | |
3528c362 JB |
5757 | && ((operand_types[0].bitfield.class != RegMMX |
5758 | && operand_types[0].bitfield.class != RegSIMD) | |
5759 | || (operand_types[t->operands > 1].bitfield.class != RegMMX | |
5760 | && operand_types[t->operands > 1].bitfield.class != RegSIMD)) | |
45aa61fe AM |
5761 | && (t->base_opcode != 0x0fc7 |
5762 | || t->extension_opcode != 1 /* cmpxchg8b */)) | |
5763 | continue; | |
5764 | ||
192dc9c6 JB |
5765 | /* In general, don't allow 32-bit operands on pre-386. */ |
5766 | else if (i.suffix == LONG_MNEM_SUFFIX | |
5767 | && !cpu_arch_flags.bitfield.cpui386 | |
5768 | && (intel_syntax | |
5769 | ? (!t->opcode_modifier.ignoresize | |
5770 | && !intel_float_operand (t->name)) | |
5771 | : intel_float_operand (t->name) != 2) | |
3528c362 JB |
5772 | && ((operand_types[0].bitfield.class != RegMMX |
5773 | && operand_types[0].bitfield.class != RegSIMD) | |
5774 | || (operand_types[t->operands > 1].bitfield.class != RegMMX | |
5775 | && operand_types[t->operands > 1].bitfield.class | |
5776 | != RegSIMD))) | |
192dc9c6 JB |
5777 | continue; |
5778 | ||
29b0f896 | 5779 | /* Do not verify operands when there are none. */ |
50aecf8c | 5780 | else |
29b0f896 | 5781 | { |
c6fb90c8 | 5782 | if (!t->operands) |
2dbab7d5 L |
5783 | /* We've found a match; break out of loop. */ |
5784 | break; | |
29b0f896 | 5785 | } |
252b5132 | 5786 | |
539e75ad L |
5787 | /* Address size prefix will turn Disp64/Disp32/Disp16 operand |
5788 | into Disp32/Disp16/Disp32 operand. */ | |
5789 | if (i.prefix[ADDR_PREFIX] != 0) | |
5790 | { | |
40fb9820 | 5791 | /* There should be only one Disp operand. */ |
539e75ad L |
5792 | switch (flag_code) |
5793 | { | |
5794 | case CODE_16BIT: | |
40fb9820 L |
5795 | for (j = 0; j < MAX_OPERANDS; j++) |
5796 | { | |
5797 | if (operand_types[j].bitfield.disp16) | |
5798 | { | |
5799 | addr_prefix_disp = j; | |
5800 | operand_types[j].bitfield.disp32 = 1; | |
5801 | operand_types[j].bitfield.disp16 = 0; | |
5802 | break; | |
5803 | } | |
5804 | } | |
539e75ad L |
5805 | break; |
5806 | case CODE_32BIT: | |
40fb9820 L |
5807 | for (j = 0; j < MAX_OPERANDS; j++) |
5808 | { | |
5809 | if (operand_types[j].bitfield.disp32) | |
5810 | { | |
5811 | addr_prefix_disp = j; | |
5812 | operand_types[j].bitfield.disp32 = 0; | |
5813 | operand_types[j].bitfield.disp16 = 1; | |
5814 | break; | |
5815 | } | |
5816 | } | |
539e75ad L |
5817 | break; |
5818 | case CODE_64BIT: | |
40fb9820 L |
5819 | for (j = 0; j < MAX_OPERANDS; j++) |
5820 | { | |
5821 | if (operand_types[j].bitfield.disp64) | |
5822 | { | |
5823 | addr_prefix_disp = j; | |
5824 | operand_types[j].bitfield.disp64 = 0; | |
5825 | operand_types[j].bitfield.disp32 = 1; | |
5826 | break; | |
5827 | } | |
5828 | } | |
539e75ad L |
5829 | break; |
5830 | } | |
539e75ad L |
5831 | } |
5832 | ||
02a86693 L |
5833 | /* Force 0x8b encoding for "mov foo@GOT, %eax". */ |
5834 | if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0) | |
5835 | continue; | |
5836 | ||
56ffb741 | 5837 | /* We check register size if needed. */ |
e2195274 JB |
5838 | if (t->opcode_modifier.checkregsize) |
5839 | { | |
5840 | check_register = (1 << t->operands) - 1; | |
5841 | if (i.broadcast) | |
5842 | check_register &= ~(1 << i.broadcast->operand); | |
5843 | } | |
5844 | else | |
5845 | check_register = 0; | |
5846 | ||
c6fb90c8 | 5847 | overlap0 = operand_type_and (i.types[0], operand_types[0]); |
29b0f896 AM |
5848 | switch (t->operands) |
5849 | { | |
5850 | case 1: | |
40fb9820 | 5851 | if (!operand_type_match (overlap0, i.types[0])) |
29b0f896 AM |
5852 | continue; |
5853 | break; | |
5854 | case 2: | |
33eaf5de | 5855 | /* xchg %eax, %eax is a special case. It is an alias for nop |
8b38ad71 L |
5856 | only in 32bit mode and we can use opcode 0x90. In 64bit |
5857 | mode, we can't use 0x90 for xchg %eax, %eax since it should | |
5858 | zero-extend %eax to %rax. */ | |
5859 | if (flag_code == CODE_64BIT | |
5860 | && t->base_opcode == 0x90 | |
75e5731b JB |
5861 | && i.types[0].bitfield.instance == Accum |
5862 | && i.types[0].bitfield.dword | |
5863 | && i.types[1].bitfield.instance == Accum | |
5864 | && i.types[1].bitfield.dword) | |
8b38ad71 | 5865 | continue; |
1212781b JB |
5866 | /* xrelease mov %eax, <disp> is another special case. It must not |
5867 | match the accumulator-only encoding of mov. */ | |
5868 | if (flag_code != CODE_64BIT | |
5869 | && i.hle_prefix | |
5870 | && t->base_opcode == 0xa0 | |
75e5731b | 5871 | && i.types[0].bitfield.instance == Accum |
8dc0818e | 5872 | && (i.flags[1] & Operand_Mem)) |
1212781b | 5873 | continue; |
f5eb1d70 JB |
5874 | /* Fall through. */ |
5875 | ||
5876 | case 3: | |
3ac21baa JB |
5877 | if (!(size_match & MATCH_STRAIGHT)) |
5878 | goto check_reverse; | |
64c49ab3 JB |
5879 | /* Reverse direction of operands if swapping is possible in the first |
5880 | place (operands need to be symmetric) and | |
5881 | - the load form is requested, and the template is a store form, | |
5882 | - the store form is requested, and the template is a load form, | |
5883 | - the non-default (swapped) form is requested. */ | |
5884 | overlap1 = operand_type_and (operand_types[0], operand_types[1]); | |
f5eb1d70 | 5885 | if (t->opcode_modifier.d && i.reg_operands == i.operands |
64c49ab3 JB |
5886 | && !operand_type_all_zero (&overlap1)) |
5887 | switch (i.dir_encoding) | |
5888 | { | |
5889 | case dir_encoding_load: | |
5890 | if (operand_type_check (operand_types[i.operands - 1], anymem) | |
dfd69174 | 5891 | || t->opcode_modifier.regmem) |
64c49ab3 JB |
5892 | goto check_reverse; |
5893 | break; | |
5894 | ||
5895 | case dir_encoding_store: | |
5896 | if (!operand_type_check (operand_types[i.operands - 1], anymem) | |
dfd69174 | 5897 | && !t->opcode_modifier.regmem) |
64c49ab3 JB |
5898 | goto check_reverse; |
5899 | break; | |
5900 | ||
5901 | case dir_encoding_swap: | |
5902 | goto check_reverse; | |
5903 | ||
5904 | case dir_encoding_default: | |
5905 | break; | |
5906 | } | |
86fa6981 | 5907 | /* If we want store form, we skip the current load. */ |
64c49ab3 JB |
5908 | if ((i.dir_encoding == dir_encoding_store |
5909 | || i.dir_encoding == dir_encoding_swap) | |
86fa6981 L |
5910 | && i.mem_operands == 0 |
5911 | && t->opcode_modifier.load) | |
fa99fab2 | 5912 | continue; |
1a0670f3 | 5913 | /* Fall through. */ |
f48ff2ae | 5914 | case 4: |
c0f3af97 | 5915 | case 5: |
c6fb90c8 | 5916 | overlap1 = operand_type_and (i.types[1], operand_types[1]); |
40fb9820 L |
5917 | if (!operand_type_match (overlap0, i.types[0]) |
5918 | || !operand_type_match (overlap1, i.types[1]) | |
e2195274 | 5919 | || ((check_register & 3) == 3 |
dc821c5f | 5920 | && !operand_type_register_match (i.types[0], |
40fb9820 | 5921 | operand_types[0], |
dc821c5f | 5922 | i.types[1], |
40fb9820 | 5923 | operand_types[1]))) |
29b0f896 AM |
5924 | { |
5925 | /* Check if other direction is valid ... */ | |
38e314eb | 5926 | if (!t->opcode_modifier.d) |
29b0f896 AM |
5927 | continue; |
5928 | ||
b6169b20 | 5929 | check_reverse: |
3ac21baa JB |
5930 | if (!(size_match & MATCH_REVERSE)) |
5931 | continue; | |
29b0f896 | 5932 | /* Try reversing direction of operands. */ |
f5eb1d70 JB |
5933 | overlap0 = operand_type_and (i.types[0], operand_types[i.operands - 1]); |
5934 | overlap1 = operand_type_and (i.types[i.operands - 1], operand_types[0]); | |
40fb9820 | 5935 | if (!operand_type_match (overlap0, i.types[0]) |
f5eb1d70 | 5936 | || !operand_type_match (overlap1, i.types[i.operands - 1]) |
45664ddb | 5937 | || (check_register |
dc821c5f | 5938 | && !operand_type_register_match (i.types[0], |
f5eb1d70 JB |
5939 | operand_types[i.operands - 1], |
5940 | i.types[i.operands - 1], | |
45664ddb | 5941 | operand_types[0]))) |
29b0f896 AM |
5942 | { |
5943 | /* Does not match either direction. */ | |
5944 | continue; | |
5945 | } | |
38e314eb | 5946 | /* found_reverse_match holds which of D or FloatR |
29b0f896 | 5947 | we've found. */ |
38e314eb JB |
5948 | if (!t->opcode_modifier.d) |
5949 | found_reverse_match = 0; | |
5950 | else if (operand_types[0].bitfield.tbyte) | |
8a2ed489 | 5951 | found_reverse_match = Opcode_FloatD; |
dbbc8b7e | 5952 | else if (operand_types[0].bitfield.xmmword |
f5eb1d70 | 5953 | || operand_types[i.operands - 1].bitfield.xmmword |
3528c362 JB |
5954 | || operand_types[0].bitfield.class == RegMMX |
5955 | || operand_types[i.operands - 1].bitfield.class == RegMMX | |
dbbc8b7e JB |
5956 | || is_any_vex_encoding(t)) |
5957 | found_reverse_match = (t->base_opcode & 0xee) != 0x6e | |
5958 | ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD; | |
8a2ed489 | 5959 | else |
38e314eb | 5960 | found_reverse_match = Opcode_D; |
40fb9820 | 5961 | if (t->opcode_modifier.floatr) |
8a2ed489 | 5962 | found_reverse_match |= Opcode_FloatR; |
29b0f896 | 5963 | } |
f48ff2ae | 5964 | else |
29b0f896 | 5965 | { |
f48ff2ae | 5966 | /* Found a forward 2 operand match here. */ |
d1cbb4db L |
5967 | switch (t->operands) |
5968 | { | |
c0f3af97 L |
5969 | case 5: |
5970 | overlap4 = operand_type_and (i.types[4], | |
5971 | operand_types[4]); | |
1a0670f3 | 5972 | /* Fall through. */ |
d1cbb4db | 5973 | case 4: |
c6fb90c8 L |
5974 | overlap3 = operand_type_and (i.types[3], |
5975 | operand_types[3]); | |
1a0670f3 | 5976 | /* Fall through. */ |
d1cbb4db | 5977 | case 3: |
c6fb90c8 L |
5978 | overlap2 = operand_type_and (i.types[2], |
5979 | operand_types[2]); | |
d1cbb4db L |
5980 | break; |
5981 | } | |
29b0f896 | 5982 | |
f48ff2ae L |
5983 | switch (t->operands) |
5984 | { | |
c0f3af97 L |
5985 | case 5: |
5986 | if (!operand_type_match (overlap4, i.types[4]) | |
dc821c5f | 5987 | || !operand_type_register_match (i.types[3], |
c0f3af97 | 5988 | operand_types[3], |
c0f3af97 L |
5989 | i.types[4], |
5990 | operand_types[4])) | |
5991 | continue; | |
1a0670f3 | 5992 | /* Fall through. */ |
f48ff2ae | 5993 | case 4: |
40fb9820 | 5994 | if (!operand_type_match (overlap3, i.types[3]) |
e2195274 JB |
5995 | || ((check_register & 0xa) == 0xa |
5996 | && !operand_type_register_match (i.types[1], | |
f7768225 JB |
5997 | operand_types[1], |
5998 | i.types[3], | |
e2195274 JB |
5999 | operand_types[3])) |
6000 | || ((check_register & 0xc) == 0xc | |
6001 | && !operand_type_register_match (i.types[2], | |
6002 | operand_types[2], | |
6003 | i.types[3], | |
6004 | operand_types[3]))) | |
f48ff2ae | 6005 | continue; |
1a0670f3 | 6006 | /* Fall through. */ |
f48ff2ae L |
6007 | case 3: |
6008 | /* Here we make use of the fact that there are no | |
23e42951 | 6009 | reverse match 3 operand instructions. */ |
40fb9820 | 6010 | if (!operand_type_match (overlap2, i.types[2]) |
e2195274 JB |
6011 | || ((check_register & 5) == 5 |
6012 | && !operand_type_register_match (i.types[0], | |
23e42951 JB |
6013 | operand_types[0], |
6014 | i.types[2], | |
e2195274 JB |
6015 | operand_types[2])) |
6016 | || ((check_register & 6) == 6 | |
6017 | && !operand_type_register_match (i.types[1], | |
6018 | operand_types[1], | |
6019 | i.types[2], | |
6020 | operand_types[2]))) | |
f48ff2ae L |
6021 | continue; |
6022 | break; | |
6023 | } | |
29b0f896 | 6024 | } |
f48ff2ae | 6025 | /* Found either forward/reverse 2, 3 or 4 operand match here: |
29b0f896 AM |
6026 | slip through to break. */ |
6027 | } | |
3629bb00 | 6028 | if (!found_cpu_match) |
dbbc8b7e | 6029 | continue; |
c0f3af97 | 6030 | |
5614d22c JB |
6031 | /* Check if vector and VEX operands are valid. */ |
6032 | if (check_VecOperands (t) || VEX_check_operands (t)) | |
6033 | { | |
6034 | specific_error = i.error; | |
6035 | continue; | |
6036 | } | |
a683cc34 | 6037 | |
29b0f896 AM |
6038 | /* We've found a match; break out of loop. */ |
6039 | break; | |
6040 | } | |
6041 | ||
6042 | if (t == current_templates->end) | |
6043 | { | |
6044 | /* We found no match. */ | |
a65babc9 | 6045 | const char *err_msg; |
5614d22c | 6046 | switch (specific_error ? specific_error : i.error) |
a65babc9 L |
6047 | { |
6048 | default: | |
6049 | abort (); | |
86e026a4 | 6050 | case operand_size_mismatch: |
a65babc9 L |
6051 | err_msg = _("operand size mismatch"); |
6052 | break; | |
6053 | case operand_type_mismatch: | |
6054 | err_msg = _("operand type mismatch"); | |
6055 | break; | |
6056 | case register_type_mismatch: | |
6057 | err_msg = _("register type mismatch"); | |
6058 | break; | |
6059 | case number_of_operands_mismatch: | |
6060 | err_msg = _("number of operands mismatch"); | |
6061 | break; | |
6062 | case invalid_instruction_suffix: | |
6063 | err_msg = _("invalid instruction suffix"); | |
6064 | break; | |
6065 | case bad_imm4: | |
4a2608e3 | 6066 | err_msg = _("constant doesn't fit in 4 bits"); |
a65babc9 | 6067 | break; |
a65babc9 L |
6068 | case unsupported_with_intel_mnemonic: |
6069 | err_msg = _("unsupported with Intel mnemonic"); | |
6070 | break; | |
6071 | case unsupported_syntax: | |
6072 | err_msg = _("unsupported syntax"); | |
6073 | break; | |
6074 | case unsupported: | |
35262a23 | 6075 | as_bad (_("unsupported instruction `%s'"), |
10efe3f6 L |
6076 | current_templates->start->name); |
6077 | return NULL; | |
6c30d220 L |
6078 | case invalid_vsib_address: |
6079 | err_msg = _("invalid VSIB address"); | |
6080 | break; | |
7bab8ab5 JB |
6081 | case invalid_vector_register_set: |
6082 | err_msg = _("mask, index, and destination registers must be distinct"); | |
6083 | break; | |
6c30d220 L |
6084 | case unsupported_vector_index_register: |
6085 | err_msg = _("unsupported vector index register"); | |
6086 | break; | |
43234a1e L |
6087 | case unsupported_broadcast: |
6088 | err_msg = _("unsupported broadcast"); | |
6089 | break; | |
43234a1e L |
6090 | case broadcast_needed: |
6091 | err_msg = _("broadcast is needed for operand of such type"); | |
6092 | break; | |
6093 | case unsupported_masking: | |
6094 | err_msg = _("unsupported masking"); | |
6095 | break; | |
6096 | case mask_not_on_destination: | |
6097 | err_msg = _("mask not on destination operand"); | |
6098 | break; | |
6099 | case no_default_mask: | |
6100 | err_msg = _("default mask isn't allowed"); | |
6101 | break; | |
6102 | case unsupported_rc_sae: | |
6103 | err_msg = _("unsupported static rounding/sae"); | |
6104 | break; | |
6105 | case rc_sae_operand_not_last_imm: | |
6106 | if (intel_syntax) | |
6107 | err_msg = _("RC/SAE operand must precede immediate operands"); | |
6108 | else | |
6109 | err_msg = _("RC/SAE operand must follow immediate operands"); | |
6110 | break; | |
6111 | case invalid_register_operand: | |
6112 | err_msg = _("invalid register operand"); | |
6113 | break; | |
a65babc9 L |
6114 | } |
6115 | as_bad (_("%s for `%s'"), err_msg, | |
891edac4 | 6116 | current_templates->start->name); |
fa99fab2 | 6117 | return NULL; |
29b0f896 | 6118 | } |
252b5132 | 6119 | |
29b0f896 AM |
6120 | if (!quiet_warnings) |
6121 | { | |
6122 | if (!intel_syntax | |
40fb9820 L |
6123 | && (i.types[0].bitfield.jumpabsolute |
6124 | != operand_types[0].bitfield.jumpabsolute)) | |
29b0f896 AM |
6125 | { |
6126 | as_warn (_("indirect %s without `*'"), t->name); | |
6127 | } | |
6128 | ||
40fb9820 L |
6129 | if (t->opcode_modifier.isprefix |
6130 | && t->opcode_modifier.ignoresize) | |
29b0f896 AM |
6131 | { |
6132 | /* Warn them that a data or address size prefix doesn't | |
6133 | affect assembly of the next line of code. */ | |
6134 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
6135 | } | |
6136 | } | |
6137 | ||
6138 | /* Copy the template we found. */ | |
6139 | i.tm = *t; | |
539e75ad L |
6140 | |
6141 | if (addr_prefix_disp != -1) | |
6142 | i.tm.operand_types[addr_prefix_disp] | |
6143 | = operand_types[addr_prefix_disp]; | |
6144 | ||
29b0f896 AM |
6145 | if (found_reverse_match) |
6146 | { | |
dfd69174 JB |
6147 | /* If we found a reverse match we must alter the opcode direction |
6148 | bit and clear/flip the regmem modifier one. found_reverse_match | |
6149 | holds bits to change (different for int & float insns). */ | |
29b0f896 AM |
6150 | |
6151 | i.tm.base_opcode ^= found_reverse_match; | |
6152 | ||
f5eb1d70 JB |
6153 | i.tm.operand_types[0] = operand_types[i.operands - 1]; |
6154 | i.tm.operand_types[i.operands - 1] = operand_types[0]; | |
dfd69174 JB |
6155 | |
6156 | /* Certain SIMD insns have their load forms specified in the opcode | |
6157 | table, and hence we need to _set_ RegMem instead of clearing it. | |
6158 | We need to avoid setting the bit though on insns like KMOVW. */ | |
6159 | i.tm.opcode_modifier.regmem | |
6160 | = i.tm.opcode_modifier.modrm && i.tm.opcode_modifier.d | |
6161 | && i.tm.operands > 2U - i.tm.opcode_modifier.sse2avx | |
6162 | && !i.tm.opcode_modifier.regmem; | |
29b0f896 AM |
6163 | } |
6164 | ||
fa99fab2 | 6165 | return t; |
29b0f896 AM |
6166 | } |
6167 | ||
6168 | static int | |
e3bb37b5 | 6169 | check_string (void) |
29b0f896 | 6170 | { |
8dc0818e JB |
6171 | unsigned int mem_op = i.flags[0] & Operand_Mem ? 0 : 1; |
6172 | ||
40fb9820 | 6173 | if (i.tm.operand_types[mem_op].bitfield.esseg) |
29b0f896 AM |
6174 | { |
6175 | if (i.seg[0] != NULL && i.seg[0] != &es) | |
6176 | { | |
a87af027 | 6177 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
29b0f896 | 6178 | i.tm.name, |
d241b910 | 6179 | intel_syntax ? i.tm.operands - mem_op : mem_op + 1, |
a87af027 | 6180 | register_prefix); |
29b0f896 AM |
6181 | return 0; |
6182 | } | |
6183 | /* There's only ever one segment override allowed per instruction. | |
6184 | This instruction possibly has a legal segment override on the | |
6185 | second operand, so copy the segment to where non-string | |
6186 | instructions store it, allowing common code. */ | |
6187 | i.seg[0] = i.seg[1]; | |
6188 | } | |
40fb9820 | 6189 | else if (i.tm.operand_types[mem_op + 1].bitfield.esseg) |
29b0f896 AM |
6190 | { |
6191 | if (i.seg[1] != NULL && i.seg[1] != &es) | |
6192 | { | |
a87af027 | 6193 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
29b0f896 | 6194 | i.tm.name, |
d241b910 | 6195 | intel_syntax ? i.tm.operands - mem_op - 1 : mem_op + 2, |
a87af027 | 6196 | register_prefix); |
29b0f896 AM |
6197 | return 0; |
6198 | } | |
6199 | } | |
6200 | return 1; | |
6201 | } | |
6202 | ||
6203 | static int | |
543613e9 | 6204 | process_suffix (void) |
29b0f896 AM |
6205 | { |
6206 | /* If matched instruction specifies an explicit instruction mnemonic | |
6207 | suffix, use it. */ | |
673fe0f0 | 6208 | if (i.tm.opcode_modifier.size == SIZE16) |
40fb9820 | 6209 | i.suffix = WORD_MNEM_SUFFIX; |
673fe0f0 | 6210 | else if (i.tm.opcode_modifier.size == SIZE32) |
40fb9820 | 6211 | i.suffix = LONG_MNEM_SUFFIX; |
673fe0f0 | 6212 | else if (i.tm.opcode_modifier.size == SIZE64) |
40fb9820 | 6213 | i.suffix = QWORD_MNEM_SUFFIX; |
29b0f896 AM |
6214 | else if (i.reg_operands) |
6215 | { | |
6216 | /* If there's no instruction mnemonic suffix we try to invent one | |
6217 | based on register operands. */ | |
6218 | if (!i.suffix) | |
6219 | { | |
6220 | /* We take i.suffix from the last register operand specified, | |
6221 | Destination register type is more significant than source | |
381d071f L |
6222 | register type. crc32 in SSE4.2 prefers source register |
6223 | type. */ | |
bab6aec1 JB |
6224 | if (i.tm.base_opcode == 0xf20f38f0 |
6225 | && i.types[0].bitfield.class == Reg) | |
381d071f | 6226 | { |
556059dd JB |
6227 | if (i.types[0].bitfield.byte) |
6228 | i.suffix = BYTE_MNEM_SUFFIX; | |
6229 | else if (i.types[0].bitfield.word) | |
40fb9820 | 6230 | i.suffix = WORD_MNEM_SUFFIX; |
556059dd | 6231 | else if (i.types[0].bitfield.dword) |
40fb9820 | 6232 | i.suffix = LONG_MNEM_SUFFIX; |
556059dd | 6233 | else if (i.types[0].bitfield.qword) |
40fb9820 | 6234 | i.suffix = QWORD_MNEM_SUFFIX; |
381d071f L |
6235 | } |
6236 | ||
6237 | if (!i.suffix) | |
6238 | { | |
6239 | int op; | |
6240 | ||
556059dd | 6241 | if (i.tm.base_opcode == 0xf20f38f0) |
20592a94 L |
6242 | { |
6243 | /* We have to know the operand size for crc32. */ | |
6244 | as_bad (_("ambiguous memory operand size for `%s`"), | |
6245 | i.tm.name); | |
6246 | return 0; | |
6247 | } | |
6248 | ||
381d071f | 6249 | for (op = i.operands; --op >= 0;) |
75e5731b JB |
6250 | if (i.tm.operand_types[op].bitfield.instance == InstanceNone |
6251 | || i.tm.operand_types[op].bitfield.instance == Accum) | |
381d071f | 6252 | { |
bab6aec1 | 6253 | if (i.types[op].bitfield.class != Reg) |
8819ada6 JB |
6254 | continue; |
6255 | if (i.types[op].bitfield.byte) | |
6256 | i.suffix = BYTE_MNEM_SUFFIX; | |
6257 | else if (i.types[op].bitfield.word) | |
6258 | i.suffix = WORD_MNEM_SUFFIX; | |
6259 | else if (i.types[op].bitfield.dword) | |
6260 | i.suffix = LONG_MNEM_SUFFIX; | |
6261 | else if (i.types[op].bitfield.qword) | |
6262 | i.suffix = QWORD_MNEM_SUFFIX; | |
6263 | else | |
6264 | continue; | |
6265 | break; | |
381d071f L |
6266 | } |
6267 | } | |
29b0f896 AM |
6268 | } |
6269 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
6270 | { | |
2eb952a4 L |
6271 | if (intel_syntax |
6272 | && i.tm.opcode_modifier.ignoresize | |
6273 | && i.tm.opcode_modifier.no_bsuf) | |
6274 | i.suffix = 0; | |
6275 | else if (!check_byte_reg ()) | |
29b0f896 AM |
6276 | return 0; |
6277 | } | |
6278 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
6279 | { | |
2eb952a4 L |
6280 | if (intel_syntax |
6281 | && i.tm.opcode_modifier.ignoresize | |
9f123b91 JB |
6282 | && i.tm.opcode_modifier.no_lsuf |
6283 | && !i.tm.opcode_modifier.todword | |
6284 | && !i.tm.opcode_modifier.toqword) | |
2eb952a4 L |
6285 | i.suffix = 0; |
6286 | else if (!check_long_reg ()) | |
29b0f896 AM |
6287 | return 0; |
6288 | } | |
6289 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
6290 | { | |
955e1e6a L |
6291 | if (intel_syntax |
6292 | && i.tm.opcode_modifier.ignoresize | |
9f123b91 JB |
6293 | && i.tm.opcode_modifier.no_qsuf |
6294 | && !i.tm.opcode_modifier.todword | |
6295 | && !i.tm.opcode_modifier.toqword) | |
955e1e6a L |
6296 | i.suffix = 0; |
6297 | else if (!check_qword_reg ()) | |
29b0f896 AM |
6298 | return 0; |
6299 | } | |
6300 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
6301 | { | |
2eb952a4 L |
6302 | if (intel_syntax |
6303 | && i.tm.opcode_modifier.ignoresize | |
6304 | && i.tm.opcode_modifier.no_wsuf) | |
6305 | i.suffix = 0; | |
6306 | else if (!check_word_reg ()) | |
29b0f896 AM |
6307 | return 0; |
6308 | } | |
40fb9820 | 6309 | else if (intel_syntax && i.tm.opcode_modifier.ignoresize) |
29b0f896 AM |
6310 | /* Do nothing if the instruction is going to ignore the prefix. */ |
6311 | ; | |
6312 | else | |
6313 | abort (); | |
6314 | } | |
40fb9820 | 6315 | else if (i.tm.opcode_modifier.defaultsize |
9306ca4a JB |
6316 | && !i.suffix |
6317 | /* exclude fldenv/frstor/fsave/fstenv */ | |
40fb9820 | 6318 | && i.tm.opcode_modifier.no_ssuf) |
29b0f896 | 6319 | { |
06f74c5c L |
6320 | if (stackop_size == LONG_MNEM_SUFFIX |
6321 | && i.tm.base_opcode == 0xcf) | |
6322 | { | |
6323 | /* stackop_size is set to LONG_MNEM_SUFFIX for the | |
6324 | .code16gcc directive to support 16-bit mode with | |
6325 | 32-bit address. For IRET without a suffix, generate | |
6326 | 16-bit IRET (opcode 0xcf) to return from an interrupt | |
6327 | handler. */ | |
6328 | i.suffix = WORD_MNEM_SUFFIX; | |
6329 | as_warn (_("generating 16-bit `iret' for .code16gcc directive")); | |
6330 | } | |
6331 | else | |
6332 | i.suffix = stackop_size; | |
29b0f896 | 6333 | } |
9306ca4a JB |
6334 | else if (intel_syntax |
6335 | && !i.suffix | |
40fb9820 L |
6336 | && (i.tm.operand_types[0].bitfield.jumpabsolute |
6337 | || i.tm.opcode_modifier.jumpbyte | |
6338 | || i.tm.opcode_modifier.jumpintersegment | |
64e74474 AM |
6339 | || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */ |
6340 | && i.tm.extension_opcode <= 3))) | |
9306ca4a JB |
6341 | { |
6342 | switch (flag_code) | |
6343 | { | |
6344 | case CODE_64BIT: | |
40fb9820 | 6345 | if (!i.tm.opcode_modifier.no_qsuf) |
9306ca4a JB |
6346 | { |
6347 | i.suffix = QWORD_MNEM_SUFFIX; | |
6348 | break; | |
6349 | } | |
1a0670f3 | 6350 | /* Fall through. */ |
9306ca4a | 6351 | case CODE_32BIT: |
40fb9820 | 6352 | if (!i.tm.opcode_modifier.no_lsuf) |
9306ca4a JB |
6353 | i.suffix = LONG_MNEM_SUFFIX; |
6354 | break; | |
6355 | case CODE_16BIT: | |
40fb9820 | 6356 | if (!i.tm.opcode_modifier.no_wsuf) |
9306ca4a JB |
6357 | i.suffix = WORD_MNEM_SUFFIX; |
6358 | break; | |
6359 | } | |
6360 | } | |
252b5132 | 6361 | |
9306ca4a | 6362 | if (!i.suffix) |
29b0f896 | 6363 | { |
9306ca4a JB |
6364 | if (!intel_syntax) |
6365 | { | |
40fb9820 | 6366 | if (i.tm.opcode_modifier.w) |
9306ca4a | 6367 | { |
4eed87de AM |
6368 | as_bad (_("no instruction mnemonic suffix given and " |
6369 | "no register operands; can't size instruction")); | |
9306ca4a JB |
6370 | return 0; |
6371 | } | |
6372 | } | |
6373 | else | |
6374 | { | |
40fb9820 | 6375 | unsigned int suffixes; |
7ab9ffdd | 6376 | |
40fb9820 L |
6377 | suffixes = !i.tm.opcode_modifier.no_bsuf; |
6378 | if (!i.tm.opcode_modifier.no_wsuf) | |
6379 | suffixes |= 1 << 1; | |
6380 | if (!i.tm.opcode_modifier.no_lsuf) | |
6381 | suffixes |= 1 << 2; | |
fc4adea1 | 6382 | if (!i.tm.opcode_modifier.no_ldsuf) |
40fb9820 L |
6383 | suffixes |= 1 << 3; |
6384 | if (!i.tm.opcode_modifier.no_ssuf) | |
6385 | suffixes |= 1 << 4; | |
c2b9da16 | 6386 | if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf) |
40fb9820 L |
6387 | suffixes |= 1 << 5; |
6388 | ||
6389 | /* There are more than suffix matches. */ | |
6390 | if (i.tm.opcode_modifier.w | |
9306ca4a | 6391 | || ((suffixes & (suffixes - 1)) |
40fb9820 L |
6392 | && !i.tm.opcode_modifier.defaultsize |
6393 | && !i.tm.opcode_modifier.ignoresize)) | |
9306ca4a JB |
6394 | { |
6395 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); | |
6396 | return 0; | |
6397 | } | |
6398 | } | |
29b0f896 | 6399 | } |
252b5132 | 6400 | |
d2224064 JB |
6401 | /* Change the opcode based on the operand size given by i.suffix. */ |
6402 | switch (i.suffix) | |
29b0f896 | 6403 | { |
d2224064 JB |
6404 | /* Size floating point instruction. */ |
6405 | case LONG_MNEM_SUFFIX: | |
6406 | if (i.tm.opcode_modifier.floatmf) | |
6407 | { | |
6408 | i.tm.base_opcode ^= 4; | |
6409 | break; | |
6410 | } | |
6411 | /* fall through */ | |
6412 | case WORD_MNEM_SUFFIX: | |
6413 | case QWORD_MNEM_SUFFIX: | |
29b0f896 | 6414 | /* It's not a byte, select word/dword operation. */ |
40fb9820 | 6415 | if (i.tm.opcode_modifier.w) |
29b0f896 | 6416 | { |
40fb9820 | 6417 | if (i.tm.opcode_modifier.shortform) |
29b0f896 AM |
6418 | i.tm.base_opcode |= 8; |
6419 | else | |
6420 | i.tm.base_opcode |= 1; | |
6421 | } | |
d2224064 JB |
6422 | /* fall through */ |
6423 | case SHORT_MNEM_SUFFIX: | |
29b0f896 AM |
6424 | /* Now select between word & dword operations via the operand |
6425 | size prefix, except for instructions that will ignore this | |
6426 | prefix anyway. */ | |
75c0a438 | 6427 | if (i.reg_operands > 0 |
bab6aec1 | 6428 | && i.types[0].bitfield.class == Reg |
75c0a438 | 6429 | && i.tm.opcode_modifier.addrprefixopreg |
474da251 | 6430 | && (i.tm.operand_types[0].bitfield.instance == Accum |
75c0a438 | 6431 | || i.operands == 1)) |
cb712a9e | 6432 | { |
ca61edf2 L |
6433 | /* The address size override prefix changes the size of the |
6434 | first operand. */ | |
40fb9820 | 6435 | if ((flag_code == CODE_32BIT |
75c0a438 | 6436 | && i.op[0].regs->reg_type.bitfield.word) |
40fb9820 | 6437 | || (flag_code != CODE_32BIT |
75c0a438 | 6438 | && i.op[0].regs->reg_type.bitfield.dword)) |
cb712a9e L |
6439 | if (!add_prefix (ADDR_PREFIX_OPCODE)) |
6440 | return 0; | |
6441 | } | |
6442 | else if (i.suffix != QWORD_MNEM_SUFFIX | |
40fb9820 L |
6443 | && !i.tm.opcode_modifier.ignoresize |
6444 | && !i.tm.opcode_modifier.floatmf | |
a38d7118 | 6445 | && !is_any_vex_encoding (&i.tm) |
cb712a9e L |
6446 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) |
6447 | || (flag_code == CODE_64BIT | |
40fb9820 | 6448 | && i.tm.opcode_modifier.jumpbyte))) |
24eab124 AM |
6449 | { |
6450 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
543613e9 | 6451 | |
40fb9820 | 6452 | if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */ |
29b0f896 | 6453 | prefix = ADDR_PREFIX_OPCODE; |
252b5132 | 6454 | |
29b0f896 AM |
6455 | if (!add_prefix (prefix)) |
6456 | return 0; | |
24eab124 | 6457 | } |
252b5132 | 6458 | |
29b0f896 AM |
6459 | /* Set mode64 for an operand. */ |
6460 | if (i.suffix == QWORD_MNEM_SUFFIX | |
9146926a | 6461 | && flag_code == CODE_64BIT |
d2224064 | 6462 | && !i.tm.opcode_modifier.norex64 |
46e883c5 | 6463 | /* Special case for xchg %rax,%rax. It is NOP and doesn't |
d2224064 JB |
6464 | need rex64. */ |
6465 | && ! (i.operands == 2 | |
6466 | && i.tm.base_opcode == 0x90 | |
6467 | && i.tm.extension_opcode == None | |
75e5731b JB |
6468 | && i.types[0].bitfield.instance == Accum |
6469 | && i.types[0].bitfield.qword | |
6470 | && i.types[1].bitfield.instance == Accum | |
6471 | && i.types[1].bitfield.qword)) | |
d2224064 | 6472 | i.rex |= REX_W; |
3e73aa7c | 6473 | |
d2224064 | 6474 | break; |
29b0f896 | 6475 | } |
7ecd2f8b | 6476 | |
c0a30a9f L |
6477 | if (i.reg_operands != 0 |
6478 | && i.operands > 1 | |
6479 | && i.tm.opcode_modifier.addrprefixopreg | |
474da251 | 6480 | && i.tm.operand_types[0].bitfield.instance != Accum) |
c0a30a9f L |
6481 | { |
6482 | /* Check invalid register operand when the address size override | |
6483 | prefix changes the size of register operands. */ | |
6484 | unsigned int op; | |
6485 | enum { need_word, need_dword, need_qword } need; | |
6486 | ||
6487 | if (flag_code == CODE_32BIT) | |
6488 | need = i.prefix[ADDR_PREFIX] ? need_word : need_dword; | |
6489 | else | |
6490 | { | |
6491 | if (i.prefix[ADDR_PREFIX]) | |
6492 | need = need_dword; | |
6493 | else | |
6494 | need = flag_code == CODE_64BIT ? need_qword : need_word; | |
6495 | } | |
6496 | ||
6497 | for (op = 0; op < i.operands; op++) | |
bab6aec1 | 6498 | if (i.types[op].bitfield.class == Reg |
c0a30a9f L |
6499 | && ((need == need_word |
6500 | && !i.op[op].regs->reg_type.bitfield.word) | |
6501 | || (need == need_dword | |
6502 | && !i.op[op].regs->reg_type.bitfield.dword) | |
6503 | || (need == need_qword | |
6504 | && !i.op[op].regs->reg_type.bitfield.qword))) | |
6505 | { | |
6506 | as_bad (_("invalid register operand size for `%s'"), | |
6507 | i.tm.name); | |
6508 | return 0; | |
6509 | } | |
6510 | } | |
6511 | ||
29b0f896 AM |
6512 | return 1; |
6513 | } | |
3e73aa7c | 6514 | |
29b0f896 | 6515 | static int |
543613e9 | 6516 | check_byte_reg (void) |
29b0f896 AM |
6517 | { |
6518 | int op; | |
543613e9 | 6519 | |
29b0f896 AM |
6520 | for (op = i.operands; --op >= 0;) |
6521 | { | |
dc821c5f | 6522 | /* Skip non-register operands. */ |
bab6aec1 | 6523 | if (i.types[op].bitfield.class != Reg) |
dc821c5f JB |
6524 | continue; |
6525 | ||
29b0f896 AM |
6526 | /* If this is an eight bit register, it's OK. If it's the 16 or |
6527 | 32 bit version of an eight bit register, we will just use the | |
6528 | low portion, and that's OK too. */ | |
dc821c5f | 6529 | if (i.types[op].bitfield.byte) |
29b0f896 AM |
6530 | continue; |
6531 | ||
5a819eb9 | 6532 | /* I/O port address operands are OK too. */ |
75e5731b JB |
6533 | if (i.tm.operand_types[op].bitfield.instance == RegD |
6534 | && i.tm.operand_types[op].bitfield.word) | |
5a819eb9 JB |
6535 | continue; |
6536 | ||
9344ff29 L |
6537 | /* crc32 doesn't generate this warning. */ |
6538 | if (i.tm.base_opcode == 0xf20f38f0) | |
6539 | continue; | |
6540 | ||
dc821c5f JB |
6541 | if ((i.types[op].bitfield.word |
6542 | || i.types[op].bitfield.dword | |
6543 | || i.types[op].bitfield.qword) | |
5a819eb9 JB |
6544 | && i.op[op].regs->reg_num < 4 |
6545 | /* Prohibit these changes in 64bit mode, since the lowering | |
6546 | would be more complicated. */ | |
6547 | && flag_code != CODE_64BIT) | |
29b0f896 | 6548 | { |
29b0f896 | 6549 | #if REGISTER_WARNINGS |
5a819eb9 | 6550 | if (!quiet_warnings) |
a540244d L |
6551 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
6552 | register_prefix, | |
dc821c5f | 6553 | (i.op[op].regs + (i.types[op].bitfield.word |
29b0f896 AM |
6554 | ? REGNAM_AL - REGNAM_AX |
6555 | : REGNAM_AL - REGNAM_EAX))->reg_name, | |
a540244d | 6556 | register_prefix, |
29b0f896 AM |
6557 | i.op[op].regs->reg_name, |
6558 | i.suffix); | |
6559 | #endif | |
6560 | continue; | |
6561 | } | |
6562 | /* Any other register is bad. */ | |
bab6aec1 | 6563 | if (i.types[op].bitfield.class == Reg |
3528c362 JB |
6564 | || i.types[op].bitfield.class == RegMMX |
6565 | || i.types[op].bitfield.class == RegSIMD | |
00cee14f | 6566 | || i.types[op].bitfield.class == SReg |
4a5c67ed JB |
6567 | || i.types[op].bitfield.class == RegCR |
6568 | || i.types[op].bitfield.class == RegDR | |
6569 | || i.types[op].bitfield.class == RegTR) | |
29b0f896 | 6570 | { |
a540244d L |
6571 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6572 | register_prefix, | |
29b0f896 AM |
6573 | i.op[op].regs->reg_name, |
6574 | i.tm.name, | |
6575 | i.suffix); | |
6576 | return 0; | |
6577 | } | |
6578 | } | |
6579 | return 1; | |
6580 | } | |
6581 | ||
6582 | static int | |
e3bb37b5 | 6583 | check_long_reg (void) |
29b0f896 AM |
6584 | { |
6585 | int op; | |
6586 | ||
6587 | for (op = i.operands; --op >= 0;) | |
dc821c5f | 6588 | /* Skip non-register operands. */ |
bab6aec1 | 6589 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 6590 | continue; |
29b0f896 AM |
6591 | /* Reject eight bit registers, except where the template requires |
6592 | them. (eg. movzb) */ | |
dc821c5f | 6593 | else if (i.types[op].bitfield.byte |
bab6aec1 | 6594 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 6595 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f JB |
6596 | && (i.tm.operand_types[op].bitfield.word |
6597 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 6598 | { |
a540244d L |
6599 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6600 | register_prefix, | |
29b0f896 AM |
6601 | i.op[op].regs->reg_name, |
6602 | i.tm.name, | |
6603 | i.suffix); | |
6604 | return 0; | |
6605 | } | |
e4630f71 | 6606 | /* Warn if the e prefix on a general reg is missing. */ |
29b0f896 | 6607 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
dc821c5f | 6608 | && i.types[op].bitfield.word |
bab6aec1 | 6609 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 6610 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 6611 | && i.tm.operand_types[op].bitfield.dword) |
29b0f896 AM |
6612 | { |
6613 | /* Prohibit these changes in the 64bit mode, since the | |
6614 | lowering is more complicated. */ | |
6615 | if (flag_code == CODE_64BIT) | |
252b5132 | 6616 | { |
2b5d6a91 | 6617 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
2ca3ace5 | 6618 | register_prefix, i.op[op].regs->reg_name, |
29b0f896 AM |
6619 | i.suffix); |
6620 | return 0; | |
252b5132 | 6621 | } |
29b0f896 | 6622 | #if REGISTER_WARNINGS |
cecf1424 JB |
6623 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
6624 | register_prefix, | |
6625 | (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name, | |
6626 | register_prefix, i.op[op].regs->reg_name, i.suffix); | |
29b0f896 | 6627 | #endif |
252b5132 | 6628 | } |
e4630f71 | 6629 | /* Warn if the r prefix on a general reg is present. */ |
dc821c5f | 6630 | else if (i.types[op].bitfield.qword |
bab6aec1 | 6631 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 6632 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 6633 | && i.tm.operand_types[op].bitfield.dword) |
252b5132 | 6634 | { |
34828aad | 6635 | if (intel_syntax |
ca61edf2 | 6636 | && i.tm.opcode_modifier.toqword |
3528c362 | 6637 | && i.types[0].bitfield.class != RegSIMD) |
34828aad | 6638 | { |
ca61edf2 | 6639 | /* Convert to QWORD. We want REX byte. */ |
34828aad L |
6640 | i.suffix = QWORD_MNEM_SUFFIX; |
6641 | } | |
6642 | else | |
6643 | { | |
2b5d6a91 | 6644 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
6645 | register_prefix, i.op[op].regs->reg_name, |
6646 | i.suffix); | |
6647 | return 0; | |
6648 | } | |
29b0f896 AM |
6649 | } |
6650 | return 1; | |
6651 | } | |
252b5132 | 6652 | |
29b0f896 | 6653 | static int |
e3bb37b5 | 6654 | check_qword_reg (void) |
29b0f896 AM |
6655 | { |
6656 | int op; | |
252b5132 | 6657 | |
29b0f896 | 6658 | for (op = i.operands; --op >= 0; ) |
dc821c5f | 6659 | /* Skip non-register operands. */ |
bab6aec1 | 6660 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 6661 | continue; |
29b0f896 AM |
6662 | /* Reject eight bit registers, except where the template requires |
6663 | them. (eg. movzb) */ | |
dc821c5f | 6664 | else if (i.types[op].bitfield.byte |
bab6aec1 | 6665 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 6666 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f JB |
6667 | && (i.tm.operand_types[op].bitfield.word |
6668 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 6669 | { |
a540244d L |
6670 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6671 | register_prefix, | |
29b0f896 AM |
6672 | i.op[op].regs->reg_name, |
6673 | i.tm.name, | |
6674 | i.suffix); | |
6675 | return 0; | |
6676 | } | |
e4630f71 | 6677 | /* Warn if the r prefix on a general reg is missing. */ |
dc821c5f JB |
6678 | else if ((i.types[op].bitfield.word |
6679 | || i.types[op].bitfield.dword) | |
bab6aec1 | 6680 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 6681 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 6682 | && i.tm.operand_types[op].bitfield.qword) |
29b0f896 AM |
6683 | { |
6684 | /* Prohibit these changes in the 64bit mode, since the | |
6685 | lowering is more complicated. */ | |
34828aad | 6686 | if (intel_syntax |
ca61edf2 | 6687 | && i.tm.opcode_modifier.todword |
3528c362 | 6688 | && i.types[0].bitfield.class != RegSIMD) |
34828aad | 6689 | { |
ca61edf2 | 6690 | /* Convert to DWORD. We don't want REX byte. */ |
34828aad L |
6691 | i.suffix = LONG_MNEM_SUFFIX; |
6692 | } | |
6693 | else | |
6694 | { | |
2b5d6a91 | 6695 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
6696 | register_prefix, i.op[op].regs->reg_name, |
6697 | i.suffix); | |
6698 | return 0; | |
6699 | } | |
252b5132 | 6700 | } |
29b0f896 AM |
6701 | return 1; |
6702 | } | |
252b5132 | 6703 | |
29b0f896 | 6704 | static int |
e3bb37b5 | 6705 | check_word_reg (void) |
29b0f896 AM |
6706 | { |
6707 | int op; | |
6708 | for (op = i.operands; --op >= 0;) | |
dc821c5f | 6709 | /* Skip non-register operands. */ |
bab6aec1 | 6710 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 6711 | continue; |
29b0f896 AM |
6712 | /* Reject eight bit registers, except where the template requires |
6713 | them. (eg. movzb) */ | |
dc821c5f | 6714 | else if (i.types[op].bitfield.byte |
bab6aec1 | 6715 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 6716 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f JB |
6717 | && (i.tm.operand_types[op].bitfield.word |
6718 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 6719 | { |
a540244d L |
6720 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6721 | register_prefix, | |
29b0f896 AM |
6722 | i.op[op].regs->reg_name, |
6723 | i.tm.name, | |
6724 | i.suffix); | |
6725 | return 0; | |
6726 | } | |
e4630f71 | 6727 | /* Warn if the e or r prefix on a general reg is present. */ |
29b0f896 | 6728 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
dc821c5f JB |
6729 | && (i.types[op].bitfield.dword |
6730 | || i.types[op].bitfield.qword) | |
bab6aec1 | 6731 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 6732 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 6733 | && i.tm.operand_types[op].bitfield.word) |
252b5132 | 6734 | { |
29b0f896 AM |
6735 | /* Prohibit these changes in the 64bit mode, since the |
6736 | lowering is more complicated. */ | |
6737 | if (flag_code == CODE_64BIT) | |
252b5132 | 6738 | { |
2b5d6a91 | 6739 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
2ca3ace5 | 6740 | register_prefix, i.op[op].regs->reg_name, |
29b0f896 AM |
6741 | i.suffix); |
6742 | return 0; | |
252b5132 | 6743 | } |
29b0f896 | 6744 | #if REGISTER_WARNINGS |
cecf1424 JB |
6745 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
6746 | register_prefix, | |
6747 | (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name, | |
6748 | register_prefix, i.op[op].regs->reg_name, i.suffix); | |
29b0f896 AM |
6749 | #endif |
6750 | } | |
6751 | return 1; | |
6752 | } | |
252b5132 | 6753 | |
29b0f896 | 6754 | static int |
40fb9820 | 6755 | update_imm (unsigned int j) |
29b0f896 | 6756 | { |
bc0844ae | 6757 | i386_operand_type overlap = i.types[j]; |
40fb9820 L |
6758 | if ((overlap.bitfield.imm8 |
6759 | || overlap.bitfield.imm8s | |
6760 | || overlap.bitfield.imm16 | |
6761 | || overlap.bitfield.imm32 | |
6762 | || overlap.bitfield.imm32s | |
6763 | || overlap.bitfield.imm64) | |
0dfbf9d7 L |
6764 | && !operand_type_equal (&overlap, &imm8) |
6765 | && !operand_type_equal (&overlap, &imm8s) | |
6766 | && !operand_type_equal (&overlap, &imm16) | |
6767 | && !operand_type_equal (&overlap, &imm32) | |
6768 | && !operand_type_equal (&overlap, &imm32s) | |
6769 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 AM |
6770 | { |
6771 | if (i.suffix) | |
6772 | { | |
40fb9820 L |
6773 | i386_operand_type temp; |
6774 | ||
0dfbf9d7 | 6775 | operand_type_set (&temp, 0); |
7ab9ffdd | 6776 | if (i.suffix == BYTE_MNEM_SUFFIX) |
40fb9820 L |
6777 | { |
6778 | temp.bitfield.imm8 = overlap.bitfield.imm8; | |
6779 | temp.bitfield.imm8s = overlap.bitfield.imm8s; | |
6780 | } | |
6781 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
6782 | temp.bitfield.imm16 = overlap.bitfield.imm16; | |
6783 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
6784 | { | |
6785 | temp.bitfield.imm64 = overlap.bitfield.imm64; | |
6786 | temp.bitfield.imm32s = overlap.bitfield.imm32s; | |
6787 | } | |
6788 | else | |
6789 | temp.bitfield.imm32 = overlap.bitfield.imm32; | |
6790 | overlap = temp; | |
29b0f896 | 6791 | } |
0dfbf9d7 L |
6792 | else if (operand_type_equal (&overlap, &imm16_32_32s) |
6793 | || operand_type_equal (&overlap, &imm16_32) | |
6794 | || operand_type_equal (&overlap, &imm16_32s)) | |
29b0f896 | 6795 | { |
40fb9820 | 6796 | if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
65da13b5 | 6797 | overlap = imm16; |
40fb9820 | 6798 | else |
65da13b5 | 6799 | overlap = imm32s; |
29b0f896 | 6800 | } |
0dfbf9d7 L |
6801 | if (!operand_type_equal (&overlap, &imm8) |
6802 | && !operand_type_equal (&overlap, &imm8s) | |
6803 | && !operand_type_equal (&overlap, &imm16) | |
6804 | && !operand_type_equal (&overlap, &imm32) | |
6805 | && !operand_type_equal (&overlap, &imm32s) | |
6806 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 | 6807 | { |
4eed87de AM |
6808 | as_bad (_("no instruction mnemonic suffix given; " |
6809 | "can't determine immediate size")); | |
29b0f896 AM |
6810 | return 0; |
6811 | } | |
6812 | } | |
40fb9820 | 6813 | i.types[j] = overlap; |
29b0f896 | 6814 | |
40fb9820 L |
6815 | return 1; |
6816 | } | |
6817 | ||
6818 | static int | |
6819 | finalize_imm (void) | |
6820 | { | |
bc0844ae | 6821 | unsigned int j, n; |
29b0f896 | 6822 | |
bc0844ae L |
6823 | /* Update the first 2 immediate operands. */ |
6824 | n = i.operands > 2 ? 2 : i.operands; | |
6825 | if (n) | |
6826 | { | |
6827 | for (j = 0; j < n; j++) | |
6828 | if (update_imm (j) == 0) | |
6829 | return 0; | |
40fb9820 | 6830 | |
bc0844ae L |
6831 | /* The 3rd operand can't be immediate operand. */ |
6832 | gas_assert (operand_type_check (i.types[2], imm) == 0); | |
6833 | } | |
29b0f896 AM |
6834 | |
6835 | return 1; | |
6836 | } | |
6837 | ||
6838 | static int | |
e3bb37b5 | 6839 | process_operands (void) |
29b0f896 AM |
6840 | { |
6841 | /* Default segment register this instruction will use for memory | |
6842 | accesses. 0 means unknown. This is only for optimizing out | |
6843 | unnecessary segment overrides. */ | |
6844 | const seg_entry *default_seg = 0; | |
6845 | ||
2426c15f | 6846 | if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv) |
29b0f896 | 6847 | { |
91d6fa6a NC |
6848 | unsigned int dupl = i.operands; |
6849 | unsigned int dest = dupl - 1; | |
9fcfb3d7 L |
6850 | unsigned int j; |
6851 | ||
c0f3af97 | 6852 | /* The destination must be an xmm register. */ |
9c2799c2 | 6853 | gas_assert (i.reg_operands |
91d6fa6a | 6854 | && MAX_OPERANDS > dupl |
7ab9ffdd | 6855 | && operand_type_equal (&i.types[dest], ®xmm)); |
c0f3af97 | 6856 | |
75e5731b | 6857 | if (i.tm.operand_types[0].bitfield.instance == Accum |
1b54b8d7 | 6858 | && i.tm.operand_types[0].bitfield.xmmword) |
e2ec9d29 | 6859 | { |
8cd7925b | 6860 | if (i.tm.opcode_modifier.vexsources == VEX3SOURCES) |
c0f3af97 L |
6861 | { |
6862 | /* Keep xmm0 for instructions with VEX prefix and 3 | |
6863 | sources. */ | |
75e5731b | 6864 | i.tm.operand_types[0].bitfield.instance = InstanceNone; |
3528c362 | 6865 | i.tm.operand_types[0].bitfield.class = RegSIMD; |
c0f3af97 L |
6866 | goto duplicate; |
6867 | } | |
e2ec9d29 | 6868 | else |
c0f3af97 L |
6869 | { |
6870 | /* We remove the first xmm0 and keep the number of | |
6871 | operands unchanged, which in fact duplicates the | |
6872 | destination. */ | |
6873 | for (j = 1; j < i.operands; j++) | |
6874 | { | |
6875 | i.op[j - 1] = i.op[j]; | |
6876 | i.types[j - 1] = i.types[j]; | |
6877 | i.tm.operand_types[j - 1] = i.tm.operand_types[j]; | |
8dc0818e | 6878 | i.flags[j - 1] = i.flags[j]; |
c0f3af97 L |
6879 | } |
6880 | } | |
6881 | } | |
6882 | else if (i.tm.opcode_modifier.implicit1stxmm0) | |
7ab9ffdd | 6883 | { |
91d6fa6a | 6884 | gas_assert ((MAX_OPERANDS - 1) > dupl |
8cd7925b L |
6885 | && (i.tm.opcode_modifier.vexsources |
6886 | == VEX3SOURCES)); | |
c0f3af97 L |
6887 | |
6888 | /* Add the implicit xmm0 for instructions with VEX prefix | |
6889 | and 3 sources. */ | |
6890 | for (j = i.operands; j > 0; j--) | |
6891 | { | |
6892 | i.op[j] = i.op[j - 1]; | |
6893 | i.types[j] = i.types[j - 1]; | |
6894 | i.tm.operand_types[j] = i.tm.operand_types[j - 1]; | |
8dc0818e | 6895 | i.flags[j] = i.flags[j - 1]; |
c0f3af97 L |
6896 | } |
6897 | i.op[0].regs | |
6898 | = (const reg_entry *) hash_find (reg_hash, "xmm0"); | |
7ab9ffdd | 6899 | i.types[0] = regxmm; |
c0f3af97 L |
6900 | i.tm.operand_types[0] = regxmm; |
6901 | ||
6902 | i.operands += 2; | |
6903 | i.reg_operands += 2; | |
6904 | i.tm.operands += 2; | |
6905 | ||
91d6fa6a | 6906 | dupl++; |
c0f3af97 | 6907 | dest++; |
91d6fa6a NC |
6908 | i.op[dupl] = i.op[dest]; |
6909 | i.types[dupl] = i.types[dest]; | |
6910 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
8dc0818e | 6911 | i.flags[dupl] = i.flags[dest]; |
e2ec9d29 | 6912 | } |
c0f3af97 L |
6913 | else |
6914 | { | |
6915 | duplicate: | |
6916 | i.operands++; | |
6917 | i.reg_operands++; | |
6918 | i.tm.operands++; | |
6919 | ||
91d6fa6a NC |
6920 | i.op[dupl] = i.op[dest]; |
6921 | i.types[dupl] = i.types[dest]; | |
6922 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
8dc0818e | 6923 | i.flags[dupl] = i.flags[dest]; |
c0f3af97 L |
6924 | } |
6925 | ||
6926 | if (i.tm.opcode_modifier.immext) | |
6927 | process_immext (); | |
6928 | } | |
75e5731b | 6929 | else if (i.tm.operand_types[0].bitfield.instance == Accum |
1b54b8d7 | 6930 | && i.tm.operand_types[0].bitfield.xmmword) |
c0f3af97 L |
6931 | { |
6932 | unsigned int j; | |
6933 | ||
9fcfb3d7 L |
6934 | for (j = 1; j < i.operands; j++) |
6935 | { | |
6936 | i.op[j - 1] = i.op[j]; | |
6937 | i.types[j - 1] = i.types[j]; | |
6938 | ||
6939 | /* We need to adjust fields in i.tm since they are used by | |
6940 | build_modrm_byte. */ | |
6941 | i.tm.operand_types [j - 1] = i.tm.operand_types [j]; | |
8dc0818e JB |
6942 | |
6943 | i.flags[j - 1] = i.flags[j]; | |
9fcfb3d7 L |
6944 | } |
6945 | ||
e2ec9d29 L |
6946 | i.operands--; |
6947 | i.reg_operands--; | |
e2ec9d29 L |
6948 | i.tm.operands--; |
6949 | } | |
920d2ddc IT |
6950 | else if (i.tm.opcode_modifier.implicitquadgroup) |
6951 | { | |
a477a8c4 JB |
6952 | unsigned int regnum, first_reg_in_group, last_reg_in_group; |
6953 | ||
920d2ddc | 6954 | /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */ |
3528c362 | 6955 | gas_assert (i.operands >= 2 && i.types[1].bitfield.class == RegSIMD); |
a477a8c4 JB |
6956 | regnum = register_number (i.op[1].regs); |
6957 | first_reg_in_group = regnum & ~3; | |
6958 | last_reg_in_group = first_reg_in_group + 3; | |
6959 | if (regnum != first_reg_in_group) | |
6960 | as_warn (_("source register `%s%s' implicitly denotes" | |
6961 | " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"), | |
6962 | register_prefix, i.op[1].regs->reg_name, | |
6963 | register_prefix, i.op[1].regs->reg_name, first_reg_in_group, | |
6964 | register_prefix, i.op[1].regs->reg_name, last_reg_in_group, | |
6965 | i.tm.name); | |
6966 | } | |
e2ec9d29 L |
6967 | else if (i.tm.opcode_modifier.regkludge) |
6968 | { | |
6969 | /* The imul $imm, %reg instruction is converted into | |
6970 | imul $imm, %reg, %reg, and the clr %reg instruction | |
6971 | is converted into xor %reg, %reg. */ | |
6972 | ||
6973 | unsigned int first_reg_op; | |
6974 | ||
6975 | if (operand_type_check (i.types[0], reg)) | |
6976 | first_reg_op = 0; | |
6977 | else | |
6978 | first_reg_op = 1; | |
6979 | /* Pretend we saw the extra register operand. */ | |
9c2799c2 | 6980 | gas_assert (i.reg_operands == 1 |
7ab9ffdd | 6981 | && i.op[first_reg_op + 1].regs == 0); |
e2ec9d29 L |
6982 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; |
6983 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
6984 | i.operands++; | |
6985 | i.reg_operands++; | |
29b0f896 AM |
6986 | } |
6987 | ||
85b80b0f | 6988 | if (i.tm.opcode_modifier.modrm) |
29b0f896 AM |
6989 | { |
6990 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
52271982 AM |
6991 | must be put into the modrm byte). Now, we make the modrm and |
6992 | index base bytes based on all the info we've collected. */ | |
29b0f896 AM |
6993 | |
6994 | default_seg = build_modrm_byte (); | |
6995 | } | |
00cee14f | 6996 | else if (i.types[0].bitfield.class == SReg) |
85b80b0f JB |
6997 | { |
6998 | if (flag_code != CODE_64BIT | |
6999 | ? i.tm.base_opcode == POP_SEG_SHORT | |
7000 | && i.op[0].regs->reg_num == 1 | |
7001 | : (i.tm.base_opcode | 1) == POP_SEG386_SHORT | |
7002 | && i.op[0].regs->reg_num < 4) | |
7003 | { | |
7004 | as_bad (_("you can't `%s %s%s'"), | |
7005 | i.tm.name, register_prefix, i.op[0].regs->reg_name); | |
7006 | return 0; | |
7007 | } | |
7008 | if ( i.op[0].regs->reg_num > 3 && i.tm.opcode_length == 1 ) | |
7009 | { | |
7010 | i.tm.base_opcode ^= POP_SEG_SHORT ^ POP_SEG386_SHORT; | |
7011 | i.tm.opcode_length = 2; | |
7012 | } | |
7013 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); | |
7014 | } | |
8a2ed489 | 7015 | else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32) |
29b0f896 AM |
7016 | { |
7017 | default_seg = &ds; | |
7018 | } | |
40fb9820 | 7019 | else if (i.tm.opcode_modifier.isstring) |
29b0f896 AM |
7020 | { |
7021 | /* For the string instructions that allow a segment override | |
7022 | on one of their operands, the default segment is ds. */ | |
7023 | default_seg = &ds; | |
7024 | } | |
85b80b0f JB |
7025 | else if (i.tm.opcode_modifier.shortform) |
7026 | { | |
7027 | /* The register or float register operand is in operand | |
7028 | 0 or 1. */ | |
bab6aec1 | 7029 | unsigned int op = i.tm.operand_types[0].bitfield.class != Reg; |
85b80b0f JB |
7030 | |
7031 | /* Register goes in low 3 bits of opcode. */ | |
7032 | i.tm.base_opcode |= i.op[op].regs->reg_num; | |
7033 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
7034 | i.rex |= REX_B; | |
7035 | if (!quiet_warnings && i.tm.opcode_modifier.ugh) | |
7036 | { | |
7037 | /* Warn about some common errors, but press on regardless. | |
7038 | The first case can be generated by gcc (<= 2.8.1). */ | |
7039 | if (i.operands == 2) | |
7040 | { | |
7041 | /* Reversed arguments on faddp, fsubp, etc. */ | |
7042 | as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, | |
7043 | register_prefix, i.op[!intel_syntax].regs->reg_name, | |
7044 | register_prefix, i.op[intel_syntax].regs->reg_name); | |
7045 | } | |
7046 | else | |
7047 | { | |
7048 | /* Extraneous `l' suffix on fp insn. */ | |
7049 | as_warn (_("translating to `%s %s%s'"), i.tm.name, | |
7050 | register_prefix, i.op[0].regs->reg_name); | |
7051 | } | |
7052 | } | |
7053 | } | |
29b0f896 | 7054 | |
75178d9d L |
7055 | if (i.tm.base_opcode == 0x8d /* lea */ |
7056 | && i.seg[0] | |
7057 | && !quiet_warnings) | |
30123838 | 7058 | as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); |
52271982 AM |
7059 | |
7060 | /* If a segment was explicitly specified, and the specified segment | |
7061 | is not the default, use an opcode prefix to select it. If we | |
7062 | never figured out what the default segment is, then default_seg | |
7063 | will be zero at this point, and the specified segment prefix will | |
7064 | always be used. */ | |
29b0f896 AM |
7065 | if ((i.seg[0]) && (i.seg[0] != default_seg)) |
7066 | { | |
7067 | if (!add_prefix (i.seg[0]->seg_prefix)) | |
7068 | return 0; | |
7069 | } | |
7070 | return 1; | |
7071 | } | |
7072 | ||
7073 | static const seg_entry * | |
e3bb37b5 | 7074 | build_modrm_byte (void) |
29b0f896 AM |
7075 | { |
7076 | const seg_entry *default_seg = 0; | |
c0f3af97 | 7077 | unsigned int source, dest; |
8cd7925b | 7078 | int vex_3_sources; |
c0f3af97 | 7079 | |
8cd7925b | 7080 | vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES; |
c0f3af97 L |
7081 | if (vex_3_sources) |
7082 | { | |
91d6fa6a | 7083 | unsigned int nds, reg_slot; |
4c2c6516 | 7084 | expressionS *exp; |
c0f3af97 | 7085 | |
6b8d3588 | 7086 | dest = i.operands - 1; |
c0f3af97 | 7087 | nds = dest - 1; |
922d8de8 | 7088 | |
a683cc34 | 7089 | /* There are 2 kinds of instructions: |
bed3d976 | 7090 | 1. 5 operands: 4 register operands or 3 register operands |
9d3bf266 | 7091 | plus 1 memory operand plus one Imm4 operand, VexXDS, and |
bed3d976 | 7092 | VexW0 or VexW1. The destination must be either XMM, YMM or |
43234a1e | 7093 | ZMM register. |
bed3d976 | 7094 | 2. 4 operands: 4 register operands or 3 register operands |
2f1bada2 | 7095 | plus 1 memory operand, with VexXDS. */ |
922d8de8 | 7096 | gas_assert ((i.reg_operands == 4 |
bed3d976 JB |
7097 | || (i.reg_operands == 3 && i.mem_operands == 1)) |
7098 | && i.tm.opcode_modifier.vexvvvv == VEXXDS | |
dcd7e323 | 7099 | && i.tm.opcode_modifier.vexw |
3528c362 | 7100 | && i.tm.operand_types[dest].bitfield.class == RegSIMD); |
a683cc34 | 7101 | |
48db9223 JB |
7102 | /* If VexW1 is set, the first non-immediate operand is the source and |
7103 | the second non-immediate one is encoded in the immediate operand. */ | |
7104 | if (i.tm.opcode_modifier.vexw == VEXW1) | |
7105 | { | |
7106 | source = i.imm_operands; | |
7107 | reg_slot = i.imm_operands + 1; | |
7108 | } | |
7109 | else | |
7110 | { | |
7111 | source = i.imm_operands + 1; | |
7112 | reg_slot = i.imm_operands; | |
7113 | } | |
7114 | ||
a683cc34 | 7115 | if (i.imm_operands == 0) |
bed3d976 JB |
7116 | { |
7117 | /* When there is no immediate operand, generate an 8bit | |
7118 | immediate operand to encode the first operand. */ | |
7119 | exp = &im_expressions[i.imm_operands++]; | |
7120 | i.op[i.operands].imms = exp; | |
7121 | i.types[i.operands] = imm8; | |
7122 | i.operands++; | |
7123 | ||
3528c362 | 7124 | gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD); |
bed3d976 JB |
7125 | exp->X_op = O_constant; |
7126 | exp->X_add_number = register_number (i.op[reg_slot].regs) << 4; | |
43234a1e L |
7127 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
7128 | } | |
922d8de8 | 7129 | else |
bed3d976 | 7130 | { |
9d3bf266 JB |
7131 | gas_assert (i.imm_operands == 1); |
7132 | gas_assert (fits_in_imm4 (i.op[0].imms->X_add_number)); | |
7133 | gas_assert (!i.tm.opcode_modifier.immext); | |
a683cc34 | 7134 | |
9d3bf266 JB |
7135 | /* Turn on Imm8 again so that output_imm will generate it. */ |
7136 | i.types[0].bitfield.imm8 = 1; | |
bed3d976 | 7137 | |
3528c362 | 7138 | gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD); |
9d3bf266 | 7139 | i.op[0].imms->X_add_number |
bed3d976 | 7140 | |= register_number (i.op[reg_slot].regs) << 4; |
43234a1e | 7141 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
bed3d976 | 7142 | } |
a683cc34 | 7143 | |
3528c362 | 7144 | gas_assert (i.tm.operand_types[nds].bitfield.class == RegSIMD); |
dae39acc | 7145 | i.vex.register_specifier = i.op[nds].regs; |
c0f3af97 L |
7146 | } |
7147 | else | |
7148 | source = dest = 0; | |
29b0f896 AM |
7149 | |
7150 | /* i.reg_operands MUST be the number of real register operands; | |
c0f3af97 L |
7151 | implicit registers do not count. If there are 3 register |
7152 | operands, it must be a instruction with VexNDS. For a | |
7153 | instruction with VexNDD, the destination register is encoded | |
7154 | in VEX prefix. If there are 4 register operands, it must be | |
7155 | a instruction with VEX prefix and 3 sources. */ | |
7ab9ffdd L |
7156 | if (i.mem_operands == 0 |
7157 | && ((i.reg_operands == 2 | |
2426c15f | 7158 | && i.tm.opcode_modifier.vexvvvv <= VEXXDS) |
7ab9ffdd | 7159 | || (i.reg_operands == 3 |
2426c15f | 7160 | && i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd | 7161 | || (i.reg_operands == 4 && vex_3_sources))) |
29b0f896 | 7162 | { |
cab737b9 L |
7163 | switch (i.operands) |
7164 | { | |
7165 | case 2: | |
7166 | source = 0; | |
7167 | break; | |
7168 | case 3: | |
c81128dc L |
7169 | /* When there are 3 operands, one of them may be immediate, |
7170 | which may be the first or the last operand. Otherwise, | |
c0f3af97 L |
7171 | the first operand must be shift count register (cl) or it |
7172 | is an instruction with VexNDS. */ | |
9c2799c2 | 7173 | gas_assert (i.imm_operands == 1 |
7ab9ffdd | 7174 | || (i.imm_operands == 0 |
2426c15f | 7175 | && (i.tm.opcode_modifier.vexvvvv == VEXXDS |
75e5731b JB |
7176 | || (i.types[0].bitfield.instance == RegC |
7177 | && i.types[0].bitfield.byte)))); | |
40fb9820 | 7178 | if (operand_type_check (i.types[0], imm) |
75e5731b JB |
7179 | || (i.types[0].bitfield.instance == RegC |
7180 | && i.types[0].bitfield.byte)) | |
40fb9820 L |
7181 | source = 1; |
7182 | else | |
7183 | source = 0; | |
cab737b9 L |
7184 | break; |
7185 | case 4: | |
368d64cc L |
7186 | /* When there are 4 operands, the first two must be 8bit |
7187 | immediate operands. The source operand will be the 3rd | |
c0f3af97 L |
7188 | one. |
7189 | ||
7190 | For instructions with VexNDS, if the first operand | |
7191 | an imm8, the source operand is the 2nd one. If the last | |
7192 | operand is imm8, the source operand is the first one. */ | |
9c2799c2 | 7193 | gas_assert ((i.imm_operands == 2 |
7ab9ffdd L |
7194 | && i.types[0].bitfield.imm8 |
7195 | && i.types[1].bitfield.imm8) | |
2426c15f | 7196 | || (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd L |
7197 | && i.imm_operands == 1 |
7198 | && (i.types[0].bitfield.imm8 | |
43234a1e L |
7199 | || i.types[i.operands - 1].bitfield.imm8 |
7200 | || i.rounding))); | |
9f2670f2 L |
7201 | if (i.imm_operands == 2) |
7202 | source = 2; | |
7203 | else | |
c0f3af97 L |
7204 | { |
7205 | if (i.types[0].bitfield.imm8) | |
7206 | source = 1; | |
7207 | else | |
7208 | source = 0; | |
7209 | } | |
c0f3af97 L |
7210 | break; |
7211 | case 5: | |
e771e7c9 | 7212 | if (is_evex_encoding (&i.tm)) |
43234a1e L |
7213 | { |
7214 | /* For EVEX instructions, when there are 5 operands, the | |
7215 | first one must be immediate operand. If the second one | |
7216 | is immediate operand, the source operand is the 3th | |
7217 | one. If the last one is immediate operand, the source | |
7218 | operand is the 2nd one. */ | |
7219 | gas_assert (i.imm_operands == 2 | |
7220 | && i.tm.opcode_modifier.sae | |
7221 | && operand_type_check (i.types[0], imm)); | |
7222 | if (operand_type_check (i.types[1], imm)) | |
7223 | source = 2; | |
7224 | else if (operand_type_check (i.types[4], imm)) | |
7225 | source = 1; | |
7226 | else | |
7227 | abort (); | |
7228 | } | |
cab737b9 L |
7229 | break; |
7230 | default: | |
7231 | abort (); | |
7232 | } | |
7233 | ||
c0f3af97 L |
7234 | if (!vex_3_sources) |
7235 | { | |
7236 | dest = source + 1; | |
7237 | ||
43234a1e L |
7238 | /* RC/SAE operand could be between DEST and SRC. That happens |
7239 | when one operand is GPR and the other one is XMM/YMM/ZMM | |
7240 | register. */ | |
7241 | if (i.rounding && i.rounding->operand == (int) dest) | |
7242 | dest++; | |
7243 | ||
2426c15f | 7244 | if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
c0f3af97 | 7245 | { |
43234a1e | 7246 | /* For instructions with VexNDS, the register-only source |
c5d0745b | 7247 | operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask |
dfd69174 | 7248 | register. It is encoded in VEX prefix. */ |
f12dc422 L |
7249 | |
7250 | i386_operand_type op; | |
7251 | unsigned int vvvv; | |
7252 | ||
7253 | /* Check register-only source operand when two source | |
7254 | operands are swapped. */ | |
7255 | if (!i.tm.operand_types[source].bitfield.baseindex | |
7256 | && i.tm.operand_types[dest].bitfield.baseindex) | |
7257 | { | |
7258 | vvvv = source; | |
7259 | source = dest; | |
7260 | } | |
7261 | else | |
7262 | vvvv = dest; | |
7263 | ||
7264 | op = i.tm.operand_types[vvvv]; | |
c0f3af97 | 7265 | if ((dest + 1) >= i.operands |
bab6aec1 | 7266 | || ((op.bitfield.class != Reg |
dc821c5f | 7267 | || (!op.bitfield.dword && !op.bitfield.qword)) |
3528c362 | 7268 | && op.bitfield.class != RegSIMD |
43234a1e | 7269 | && !operand_type_equal (&op, ®mask))) |
c0f3af97 | 7270 | abort (); |
f12dc422 | 7271 | i.vex.register_specifier = i.op[vvvv].regs; |
c0f3af97 L |
7272 | dest++; |
7273 | } | |
7274 | } | |
29b0f896 AM |
7275 | |
7276 | i.rm.mode = 3; | |
dfd69174 JB |
7277 | /* One of the register operands will be encoded in the i.rm.reg |
7278 | field, the other in the combined i.rm.mode and i.rm.regmem | |
29b0f896 AM |
7279 | fields. If no form of this instruction supports a memory |
7280 | destination operand, then we assume the source operand may | |
7281 | sometimes be a memory operand and so we need to store the | |
7282 | destination in the i.rm.reg field. */ | |
dfd69174 | 7283 | if (!i.tm.opcode_modifier.regmem |
40fb9820 | 7284 | && operand_type_check (i.tm.operand_types[dest], anymem) == 0) |
29b0f896 AM |
7285 | { |
7286 | i.rm.reg = i.op[dest].regs->reg_num; | |
7287 | i.rm.regmem = i.op[source].regs->reg_num; | |
3528c362 JB |
7288 | if (i.op[dest].regs->reg_type.bitfield.class == RegMMX |
7289 | || i.op[source].regs->reg_type.bitfield.class == RegMMX) | |
b4a3a7b4 | 7290 | i.has_regmmx = TRUE; |
3528c362 JB |
7291 | else if (i.op[dest].regs->reg_type.bitfield.class == RegSIMD |
7292 | || i.op[source].regs->reg_type.bitfield.class == RegSIMD) | |
b4a3a7b4 L |
7293 | { |
7294 | if (i.types[dest].bitfield.zmmword | |
7295 | || i.types[source].bitfield.zmmword) | |
7296 | i.has_regzmm = TRUE; | |
7297 | else if (i.types[dest].bitfield.ymmword | |
7298 | || i.types[source].bitfield.ymmword) | |
7299 | i.has_regymm = TRUE; | |
7300 | else | |
7301 | i.has_regxmm = TRUE; | |
7302 | } | |
29b0f896 | 7303 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) |
161a04f6 | 7304 | i.rex |= REX_R; |
43234a1e L |
7305 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
7306 | i.vrex |= REX_R; | |
29b0f896 | 7307 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 7308 | i.rex |= REX_B; |
43234a1e L |
7309 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
7310 | i.vrex |= REX_B; | |
29b0f896 AM |
7311 | } |
7312 | else | |
7313 | { | |
7314 | i.rm.reg = i.op[source].regs->reg_num; | |
7315 | i.rm.regmem = i.op[dest].regs->reg_num; | |
7316 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 7317 | i.rex |= REX_B; |
43234a1e L |
7318 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
7319 | i.vrex |= REX_B; | |
29b0f896 | 7320 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 7321 | i.rex |= REX_R; |
43234a1e L |
7322 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
7323 | i.vrex |= REX_R; | |
29b0f896 | 7324 | } |
e0c7f900 | 7325 | if (flag_code != CODE_64BIT && (i.rex & REX_R)) |
c4a530c5 | 7326 | { |
4a5c67ed | 7327 | if (i.types[!i.tm.opcode_modifier.regmem].bitfield.class != RegCR) |
c4a530c5 | 7328 | abort (); |
e0c7f900 | 7329 | i.rex &= ~REX_R; |
c4a530c5 JB |
7330 | add_prefix (LOCK_PREFIX_OPCODE); |
7331 | } | |
29b0f896 AM |
7332 | } |
7333 | else | |
7334 | { /* If it's not 2 reg operands... */ | |
c0f3af97 L |
7335 | unsigned int mem; |
7336 | ||
29b0f896 AM |
7337 | if (i.mem_operands) |
7338 | { | |
7339 | unsigned int fake_zero_displacement = 0; | |
99018f42 | 7340 | unsigned int op; |
4eed87de | 7341 | |
7ab9ffdd | 7342 | for (op = 0; op < i.operands; op++) |
8dc0818e | 7343 | if (i.flags[op] & Operand_Mem) |
7ab9ffdd | 7344 | break; |
7ab9ffdd | 7345 | gas_assert (op < i.operands); |
29b0f896 | 7346 | |
6c30d220 L |
7347 | if (i.tm.opcode_modifier.vecsib) |
7348 | { | |
e968fc9b | 7349 | if (i.index_reg->reg_num == RegIZ) |
6c30d220 L |
7350 | abort (); |
7351 | ||
7352 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
7353 | if (!i.base_reg) | |
7354 | { | |
7355 | i.sib.base = NO_BASE_REGISTER; | |
7356 | i.sib.scale = i.log2_scale_factor; | |
7357 | i.types[op].bitfield.disp8 = 0; | |
7358 | i.types[op].bitfield.disp16 = 0; | |
7359 | i.types[op].bitfield.disp64 = 0; | |
43083a50 | 7360 | if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX]) |
6c30d220 L |
7361 | { |
7362 | /* Must be 32 bit */ | |
7363 | i.types[op].bitfield.disp32 = 1; | |
7364 | i.types[op].bitfield.disp32s = 0; | |
7365 | } | |
7366 | else | |
7367 | { | |
7368 | i.types[op].bitfield.disp32 = 0; | |
7369 | i.types[op].bitfield.disp32s = 1; | |
7370 | } | |
7371 | } | |
7372 | i.sib.index = i.index_reg->reg_num; | |
7373 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
7374 | i.rex |= REX_X; | |
43234a1e L |
7375 | if ((i.index_reg->reg_flags & RegVRex) != 0) |
7376 | i.vrex |= REX_X; | |
6c30d220 L |
7377 | } |
7378 | ||
29b0f896 AM |
7379 | default_seg = &ds; |
7380 | ||
7381 | if (i.base_reg == 0) | |
7382 | { | |
7383 | i.rm.mode = 0; | |
7384 | if (!i.disp_operands) | |
9bb129e8 | 7385 | fake_zero_displacement = 1; |
29b0f896 AM |
7386 | if (i.index_reg == 0) |
7387 | { | |
73053c1f JB |
7388 | i386_operand_type newdisp; |
7389 | ||
6c30d220 | 7390 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 7391 | /* Operand is just <disp> */ |
20f0a1fc | 7392 | if (flag_code == CODE_64BIT) |
29b0f896 AM |
7393 | { |
7394 | /* 64bit mode overwrites the 32bit absolute | |
7395 | addressing by RIP relative addressing and | |
7396 | absolute addressing is encoded by one of the | |
7397 | redundant SIB forms. */ | |
7398 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
7399 | i.sib.base = NO_BASE_REGISTER; | |
7400 | i.sib.index = NO_INDEX_REGISTER; | |
73053c1f | 7401 | newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32); |
20f0a1fc | 7402 | } |
fc225355 L |
7403 | else if ((flag_code == CODE_16BIT) |
7404 | ^ (i.prefix[ADDR_PREFIX] != 0)) | |
20f0a1fc NC |
7405 | { |
7406 | i.rm.regmem = NO_BASE_REGISTER_16; | |
73053c1f | 7407 | newdisp = disp16; |
20f0a1fc NC |
7408 | } |
7409 | else | |
7410 | { | |
7411 | i.rm.regmem = NO_BASE_REGISTER; | |
73053c1f | 7412 | newdisp = disp32; |
29b0f896 | 7413 | } |
73053c1f JB |
7414 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
7415 | i.types[op] = operand_type_or (i.types[op], newdisp); | |
29b0f896 | 7416 | } |
6c30d220 | 7417 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 7418 | { |
6c30d220 | 7419 | /* !i.base_reg && i.index_reg */ |
e968fc9b | 7420 | if (i.index_reg->reg_num == RegIZ) |
db51cc60 L |
7421 | i.sib.index = NO_INDEX_REGISTER; |
7422 | else | |
7423 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
7424 | i.sib.base = NO_BASE_REGISTER; |
7425 | i.sib.scale = i.log2_scale_factor; | |
7426 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
40fb9820 L |
7427 | i.types[op].bitfield.disp8 = 0; |
7428 | i.types[op].bitfield.disp16 = 0; | |
7429 | i.types[op].bitfield.disp64 = 0; | |
43083a50 | 7430 | if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX]) |
40fb9820 L |
7431 | { |
7432 | /* Must be 32 bit */ | |
7433 | i.types[op].bitfield.disp32 = 1; | |
7434 | i.types[op].bitfield.disp32s = 0; | |
7435 | } | |
29b0f896 | 7436 | else |
40fb9820 L |
7437 | { |
7438 | i.types[op].bitfield.disp32 = 0; | |
7439 | i.types[op].bitfield.disp32s = 1; | |
7440 | } | |
29b0f896 | 7441 | if ((i.index_reg->reg_flags & RegRex) != 0) |
161a04f6 | 7442 | i.rex |= REX_X; |
29b0f896 AM |
7443 | } |
7444 | } | |
7445 | /* RIP addressing for 64bit mode. */ | |
e968fc9b | 7446 | else if (i.base_reg->reg_num == RegIP) |
29b0f896 | 7447 | { |
6c30d220 | 7448 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 7449 | i.rm.regmem = NO_BASE_REGISTER; |
40fb9820 L |
7450 | i.types[op].bitfield.disp8 = 0; |
7451 | i.types[op].bitfield.disp16 = 0; | |
7452 | i.types[op].bitfield.disp32 = 0; | |
7453 | i.types[op].bitfield.disp32s = 1; | |
7454 | i.types[op].bitfield.disp64 = 0; | |
71903a11 | 7455 | i.flags[op] |= Operand_PCrel; |
20f0a1fc NC |
7456 | if (! i.disp_operands) |
7457 | fake_zero_displacement = 1; | |
29b0f896 | 7458 | } |
dc821c5f | 7459 | else if (i.base_reg->reg_type.bitfield.word) |
29b0f896 | 7460 | { |
6c30d220 | 7461 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
7462 | switch (i.base_reg->reg_num) |
7463 | { | |
7464 | case 3: /* (%bx) */ | |
7465 | if (i.index_reg == 0) | |
7466 | i.rm.regmem = 7; | |
7467 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
7468 | i.rm.regmem = i.index_reg->reg_num - 6; | |
7469 | break; | |
7470 | case 5: /* (%bp) */ | |
7471 | default_seg = &ss; | |
7472 | if (i.index_reg == 0) | |
7473 | { | |
7474 | i.rm.regmem = 6; | |
40fb9820 | 7475 | if (operand_type_check (i.types[op], disp) == 0) |
29b0f896 AM |
7476 | { |
7477 | /* fake (%bp) into 0(%bp) */ | |
b5014f7a | 7478 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 7479 | fake_zero_displacement = 1; |
29b0f896 AM |
7480 | } |
7481 | } | |
7482 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
7483 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
7484 | break; | |
7485 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
7486 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
7487 | } | |
7488 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
7489 | } | |
7490 | else /* i.base_reg and 32/64 bit mode */ | |
7491 | { | |
7492 | if (flag_code == CODE_64BIT | |
40fb9820 L |
7493 | && operand_type_check (i.types[op], disp)) |
7494 | { | |
73053c1f JB |
7495 | i.types[op].bitfield.disp16 = 0; |
7496 | i.types[op].bitfield.disp64 = 0; | |
40fb9820 | 7497 | if (i.prefix[ADDR_PREFIX] == 0) |
73053c1f JB |
7498 | { |
7499 | i.types[op].bitfield.disp32 = 0; | |
7500 | i.types[op].bitfield.disp32s = 1; | |
7501 | } | |
40fb9820 | 7502 | else |
73053c1f JB |
7503 | { |
7504 | i.types[op].bitfield.disp32 = 1; | |
7505 | i.types[op].bitfield.disp32s = 0; | |
7506 | } | |
40fb9820 | 7507 | } |
20f0a1fc | 7508 | |
6c30d220 L |
7509 | if (!i.tm.opcode_modifier.vecsib) |
7510 | i.rm.regmem = i.base_reg->reg_num; | |
29b0f896 | 7511 | if ((i.base_reg->reg_flags & RegRex) != 0) |
161a04f6 | 7512 | i.rex |= REX_B; |
29b0f896 AM |
7513 | i.sib.base = i.base_reg->reg_num; |
7514 | /* x86-64 ignores REX prefix bit here to avoid decoder | |
7515 | complications. */ | |
848930b2 JB |
7516 | if (!(i.base_reg->reg_flags & RegRex) |
7517 | && (i.base_reg->reg_num == EBP_REG_NUM | |
7518 | || i.base_reg->reg_num == ESP_REG_NUM)) | |
29b0f896 | 7519 | default_seg = &ss; |
848930b2 | 7520 | if (i.base_reg->reg_num == 5 && i.disp_operands == 0) |
29b0f896 | 7521 | { |
848930b2 | 7522 | fake_zero_displacement = 1; |
b5014f7a | 7523 | i.types[op].bitfield.disp8 = 1; |
29b0f896 AM |
7524 | } |
7525 | i.sib.scale = i.log2_scale_factor; | |
7526 | if (i.index_reg == 0) | |
7527 | { | |
6c30d220 | 7528 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
7529 | /* <disp>(%esp) becomes two byte modrm with no index |
7530 | register. We've already stored the code for esp | |
7531 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. | |
7532 | Any base register besides %esp will not use the | |
7533 | extra modrm byte. */ | |
7534 | i.sib.index = NO_INDEX_REGISTER; | |
29b0f896 | 7535 | } |
6c30d220 | 7536 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 7537 | { |
e968fc9b | 7538 | if (i.index_reg->reg_num == RegIZ) |
db51cc60 L |
7539 | i.sib.index = NO_INDEX_REGISTER; |
7540 | else | |
7541 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
7542 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
7543 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
161a04f6 | 7544 | i.rex |= REX_X; |
29b0f896 | 7545 | } |
67a4f2b7 AO |
7546 | |
7547 | if (i.disp_operands | |
7548 | && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL | |
7549 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) | |
7550 | i.rm.mode = 0; | |
7551 | else | |
a501d77e L |
7552 | { |
7553 | if (!fake_zero_displacement | |
7554 | && !i.disp_operands | |
7555 | && i.disp_encoding) | |
7556 | { | |
7557 | fake_zero_displacement = 1; | |
7558 | if (i.disp_encoding == disp_encoding_8bit) | |
7559 | i.types[op].bitfield.disp8 = 1; | |
7560 | else | |
7561 | i.types[op].bitfield.disp32 = 1; | |
7562 | } | |
7563 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
7564 | } | |
29b0f896 | 7565 | } |
252b5132 | 7566 | |
29b0f896 AM |
7567 | if (fake_zero_displacement) |
7568 | { | |
7569 | /* Fakes a zero displacement assuming that i.types[op] | |
7570 | holds the correct displacement size. */ | |
7571 | expressionS *exp; | |
7572 | ||
9c2799c2 | 7573 | gas_assert (i.op[op].disps == 0); |
29b0f896 AM |
7574 | exp = &disp_expressions[i.disp_operands++]; |
7575 | i.op[op].disps = exp; | |
7576 | exp->X_op = O_constant; | |
7577 | exp->X_add_number = 0; | |
7578 | exp->X_add_symbol = (symbolS *) 0; | |
7579 | exp->X_op_symbol = (symbolS *) 0; | |
7580 | } | |
c0f3af97 L |
7581 | |
7582 | mem = op; | |
29b0f896 | 7583 | } |
c0f3af97 L |
7584 | else |
7585 | mem = ~0; | |
252b5132 | 7586 | |
8c43a48b | 7587 | if (i.tm.opcode_modifier.vexsources == XOP2SOURCES) |
5dd85c99 SP |
7588 | { |
7589 | if (operand_type_check (i.types[0], imm)) | |
7590 | i.vex.register_specifier = NULL; | |
7591 | else | |
7592 | { | |
7593 | /* VEX.vvvv encodes one of the sources when the first | |
7594 | operand is not an immediate. */ | |
1ef99a7b | 7595 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
7596 | i.vex.register_specifier = i.op[0].regs; |
7597 | else | |
7598 | i.vex.register_specifier = i.op[1].regs; | |
7599 | } | |
7600 | ||
7601 | /* Destination is a XMM register encoded in the ModRM.reg | |
7602 | and VEX.R bit. */ | |
7603 | i.rm.reg = i.op[2].regs->reg_num; | |
7604 | if ((i.op[2].regs->reg_flags & RegRex) != 0) | |
7605 | i.rex |= REX_R; | |
7606 | ||
7607 | /* ModRM.rm and VEX.B encodes the other source. */ | |
7608 | if (!i.mem_operands) | |
7609 | { | |
7610 | i.rm.mode = 3; | |
7611 | ||
1ef99a7b | 7612 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
7613 | i.rm.regmem = i.op[1].regs->reg_num; |
7614 | else | |
7615 | i.rm.regmem = i.op[0].regs->reg_num; | |
7616 | ||
7617 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
7618 | i.rex |= REX_B; | |
7619 | } | |
7620 | } | |
2426c15f | 7621 | else if (i.tm.opcode_modifier.vexvvvv == VEXLWP) |
f88c9eb0 SP |
7622 | { |
7623 | i.vex.register_specifier = i.op[2].regs; | |
7624 | if (!i.mem_operands) | |
7625 | { | |
7626 | i.rm.mode = 3; | |
7627 | i.rm.regmem = i.op[1].regs->reg_num; | |
7628 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
7629 | i.rex |= REX_B; | |
7630 | } | |
7631 | } | |
29b0f896 AM |
7632 | /* Fill in i.rm.reg or i.rm.regmem field with register operand |
7633 | (if any) based on i.tm.extension_opcode. Again, we must be | |
7634 | careful to make sure that segment/control/debug/test/MMX | |
7635 | registers are coded into the i.rm.reg field. */ | |
f88c9eb0 | 7636 | else if (i.reg_operands) |
29b0f896 | 7637 | { |
99018f42 | 7638 | unsigned int op; |
7ab9ffdd L |
7639 | unsigned int vex_reg = ~0; |
7640 | ||
7641 | for (op = 0; op < i.operands; op++) | |
b4a3a7b4 | 7642 | { |
bab6aec1 | 7643 | if (i.types[op].bitfield.class == Reg |
f74a6307 JB |
7644 | || i.types[op].bitfield.class == RegBND |
7645 | || i.types[op].bitfield.class == RegMask | |
00cee14f | 7646 | || i.types[op].bitfield.class == SReg |
4a5c67ed JB |
7647 | || i.types[op].bitfield.class == RegCR |
7648 | || i.types[op].bitfield.class == RegDR | |
7649 | || i.types[op].bitfield.class == RegTR) | |
b4a3a7b4 | 7650 | break; |
3528c362 | 7651 | if (i.types[op].bitfield.class == RegSIMD) |
b4a3a7b4 L |
7652 | { |
7653 | if (i.types[op].bitfield.zmmword) | |
7654 | i.has_regzmm = TRUE; | |
7655 | else if (i.types[op].bitfield.ymmword) | |
7656 | i.has_regymm = TRUE; | |
7657 | else | |
7658 | i.has_regxmm = TRUE; | |
7659 | break; | |
7660 | } | |
3528c362 | 7661 | if (i.types[op].bitfield.class == RegMMX) |
b4a3a7b4 L |
7662 | { |
7663 | i.has_regmmx = TRUE; | |
7664 | break; | |
7665 | } | |
7666 | } | |
c0209578 | 7667 | |
7ab9ffdd L |
7668 | if (vex_3_sources) |
7669 | op = dest; | |
2426c15f | 7670 | else if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd L |
7671 | { |
7672 | /* For instructions with VexNDS, the register-only | |
7673 | source operand is encoded in VEX prefix. */ | |
7674 | gas_assert (mem != (unsigned int) ~0); | |
c0f3af97 | 7675 | |
7ab9ffdd | 7676 | if (op > mem) |
c0f3af97 | 7677 | { |
7ab9ffdd L |
7678 | vex_reg = op++; |
7679 | gas_assert (op < i.operands); | |
c0f3af97 L |
7680 | } |
7681 | else | |
c0f3af97 | 7682 | { |
f12dc422 L |
7683 | /* Check register-only source operand when two source |
7684 | operands are swapped. */ | |
7685 | if (!i.tm.operand_types[op].bitfield.baseindex | |
7686 | && i.tm.operand_types[op + 1].bitfield.baseindex) | |
7687 | { | |
7688 | vex_reg = op; | |
7689 | op += 2; | |
7690 | gas_assert (mem == (vex_reg + 1) | |
7691 | && op < i.operands); | |
7692 | } | |
7693 | else | |
7694 | { | |
7695 | vex_reg = op + 1; | |
7696 | gas_assert (vex_reg < i.operands); | |
7697 | } | |
c0f3af97 | 7698 | } |
7ab9ffdd | 7699 | } |
2426c15f | 7700 | else if (i.tm.opcode_modifier.vexvvvv == VEXNDD) |
7ab9ffdd | 7701 | { |
f12dc422 | 7702 | /* For instructions with VexNDD, the register destination |
7ab9ffdd | 7703 | is encoded in VEX prefix. */ |
f12dc422 L |
7704 | if (i.mem_operands == 0) |
7705 | { | |
7706 | /* There is no memory operand. */ | |
7707 | gas_assert ((op + 2) == i.operands); | |
7708 | vex_reg = op + 1; | |
7709 | } | |
7710 | else | |
8d63c93e | 7711 | { |
ed438a93 JB |
7712 | /* There are only 2 non-immediate operands. */ |
7713 | gas_assert (op < i.imm_operands + 2 | |
7714 | && i.operands == i.imm_operands + 2); | |
7715 | vex_reg = i.imm_operands + 1; | |
f12dc422 | 7716 | } |
7ab9ffdd L |
7717 | } |
7718 | else | |
7719 | gas_assert (op < i.operands); | |
99018f42 | 7720 | |
7ab9ffdd L |
7721 | if (vex_reg != (unsigned int) ~0) |
7722 | { | |
f12dc422 | 7723 | i386_operand_type *type = &i.tm.operand_types[vex_reg]; |
7ab9ffdd | 7724 | |
bab6aec1 | 7725 | if ((type->bitfield.class != Reg |
dc821c5f | 7726 | || (!type->bitfield.dword && !type->bitfield.qword)) |
3528c362 | 7727 | && type->bitfield.class != RegSIMD |
43234a1e | 7728 | && !operand_type_equal (type, ®mask)) |
7ab9ffdd | 7729 | abort (); |
f88c9eb0 | 7730 | |
7ab9ffdd L |
7731 | i.vex.register_specifier = i.op[vex_reg].regs; |
7732 | } | |
7733 | ||
1b9f0c97 L |
7734 | /* Don't set OP operand twice. */ |
7735 | if (vex_reg != op) | |
7ab9ffdd | 7736 | { |
1b9f0c97 L |
7737 | /* If there is an extension opcode to put here, the |
7738 | register number must be put into the regmem field. */ | |
7739 | if (i.tm.extension_opcode != None) | |
7740 | { | |
7741 | i.rm.regmem = i.op[op].regs->reg_num; | |
7742 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
7743 | i.rex |= REX_B; | |
43234a1e L |
7744 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
7745 | i.vrex |= REX_B; | |
1b9f0c97 L |
7746 | } |
7747 | else | |
7748 | { | |
7749 | i.rm.reg = i.op[op].regs->reg_num; | |
7750 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
7751 | i.rex |= REX_R; | |
43234a1e L |
7752 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
7753 | i.vrex |= REX_R; | |
1b9f0c97 | 7754 | } |
7ab9ffdd | 7755 | } |
252b5132 | 7756 | |
29b0f896 AM |
7757 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we |
7758 | must set it to 3 to indicate this is a register operand | |
7759 | in the regmem field. */ | |
7760 | if (!i.mem_operands) | |
7761 | i.rm.mode = 3; | |
7762 | } | |
252b5132 | 7763 | |
29b0f896 | 7764 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
c1e679ec | 7765 | if (i.tm.extension_opcode != None) |
29b0f896 AM |
7766 | i.rm.reg = i.tm.extension_opcode; |
7767 | } | |
7768 | return default_seg; | |
7769 | } | |
252b5132 | 7770 | |
29b0f896 | 7771 | static void |
e3bb37b5 | 7772 | output_branch (void) |
29b0f896 AM |
7773 | { |
7774 | char *p; | |
f8a5c266 | 7775 | int size; |
29b0f896 AM |
7776 | int code16; |
7777 | int prefix; | |
7778 | relax_substateT subtype; | |
7779 | symbolS *sym; | |
7780 | offsetT off; | |
7781 | ||
f8a5c266 | 7782 | code16 = flag_code == CODE_16BIT ? CODE16 : 0; |
a501d77e | 7783 | size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL; |
29b0f896 AM |
7784 | |
7785 | prefix = 0; | |
7786 | if (i.prefix[DATA_PREFIX] != 0) | |
252b5132 | 7787 | { |
29b0f896 AM |
7788 | prefix = 1; |
7789 | i.prefixes -= 1; | |
7790 | code16 ^= CODE16; | |
252b5132 | 7791 | } |
29b0f896 AM |
7792 | /* Pentium4 branch hints. */ |
7793 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
7794 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2f66722d | 7795 | { |
29b0f896 AM |
7796 | prefix++; |
7797 | i.prefixes--; | |
7798 | } | |
7799 | if (i.prefix[REX_PREFIX] != 0) | |
7800 | { | |
7801 | prefix++; | |
7802 | i.prefixes--; | |
2f66722d AM |
7803 | } |
7804 | ||
7e8b059b L |
7805 | /* BND prefixed jump. */ |
7806 | if (i.prefix[BND_PREFIX] != 0) | |
7807 | { | |
7808 | FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]); | |
7809 | i.prefixes -= 1; | |
7810 | } | |
7811 | ||
29b0f896 AM |
7812 | if (i.prefixes != 0 && !intel_syntax) |
7813 | as_warn (_("skipping prefixes on this instruction")); | |
7814 | ||
7815 | /* It's always a symbol; End frag & setup for relax. | |
7816 | Make sure there is enough room in this frag for the largest | |
7817 | instruction we may generate in md_convert_frag. This is 2 | |
7818 | bytes for the opcode and room for the prefix and largest | |
7819 | displacement. */ | |
7820 | frag_grow (prefix + 2 + 4); | |
7821 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
7822 | p = frag_more (prefix + 1); | |
7823 | if (i.prefix[DATA_PREFIX] != 0) | |
7824 | *p++ = DATA_PREFIX_OPCODE; | |
7825 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE | |
7826 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
7827 | *p++ = i.prefix[SEG_PREFIX]; | |
7828 | if (i.prefix[REX_PREFIX] != 0) | |
7829 | *p++ = i.prefix[REX_PREFIX]; | |
7830 | *p = i.tm.base_opcode; | |
7831 | ||
7832 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
f8a5c266 | 7833 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size); |
40fb9820 | 7834 | else if (cpu_arch_flags.bitfield.cpui386) |
f8a5c266 | 7835 | subtype = ENCODE_RELAX_STATE (COND_JUMP, size); |
29b0f896 | 7836 | else |
f8a5c266 | 7837 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, size); |
29b0f896 | 7838 | subtype |= code16; |
3e73aa7c | 7839 | |
29b0f896 AM |
7840 | sym = i.op[0].disps->X_add_symbol; |
7841 | off = i.op[0].disps->X_add_number; | |
3e73aa7c | 7842 | |
29b0f896 AM |
7843 | if (i.op[0].disps->X_op != O_constant |
7844 | && i.op[0].disps->X_op != O_symbol) | |
3e73aa7c | 7845 | { |
29b0f896 AM |
7846 | /* Handle complex expressions. */ |
7847 | sym = make_expr_symbol (i.op[0].disps); | |
7848 | off = 0; | |
7849 | } | |
3e73aa7c | 7850 | |
29b0f896 AM |
7851 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
7852 | Pass reloc in fr_var. */ | |
d258b828 | 7853 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); |
29b0f896 | 7854 | } |
3e73aa7c | 7855 | |
bd7ab16b L |
7856 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
7857 | /* Return TRUE iff PLT32 relocation should be used for branching to | |
7858 | symbol S. */ | |
7859 | ||
7860 | static bfd_boolean | |
7861 | need_plt32_p (symbolS *s) | |
7862 | { | |
7863 | /* PLT32 relocation is ELF only. */ | |
7864 | if (!IS_ELF) | |
7865 | return FALSE; | |
7866 | ||
a5def729 RO |
7867 | #ifdef TE_SOLARIS |
7868 | /* Don't emit PLT32 relocation on Solaris: neither native linker nor | |
7869 | krtld support it. */ | |
7870 | return FALSE; | |
7871 | #endif | |
7872 | ||
bd7ab16b L |
7873 | /* Since there is no need to prepare for PLT branch on x86-64, we |
7874 | can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can | |
7875 | be used as a marker for 32-bit PC-relative branches. */ | |
7876 | if (!object_64bit) | |
7877 | return FALSE; | |
7878 | ||
7879 | /* Weak or undefined symbol need PLT32 relocation. */ | |
7880 | if (S_IS_WEAK (s) || !S_IS_DEFINED (s)) | |
7881 | return TRUE; | |
7882 | ||
7883 | /* Non-global symbol doesn't need PLT32 relocation. */ | |
7884 | if (! S_IS_EXTERNAL (s)) | |
7885 | return FALSE; | |
7886 | ||
7887 | /* Other global symbols need PLT32 relocation. NB: Symbol with | |
7888 | non-default visibilities are treated as normal global symbol | |
7889 | so that PLT32 relocation can be used as a marker for 32-bit | |
7890 | PC-relative branches. It is useful for linker relaxation. */ | |
7891 | return TRUE; | |
7892 | } | |
7893 | #endif | |
7894 | ||
29b0f896 | 7895 | static void |
e3bb37b5 | 7896 | output_jump (void) |
29b0f896 AM |
7897 | { |
7898 | char *p; | |
7899 | int size; | |
3e02c1cc | 7900 | fixS *fixP; |
bd7ab16b | 7901 | bfd_reloc_code_real_type jump_reloc = i.reloc[0]; |
29b0f896 | 7902 | |
40fb9820 | 7903 | if (i.tm.opcode_modifier.jumpbyte) |
29b0f896 AM |
7904 | { |
7905 | /* This is a loop or jecxz type instruction. */ | |
7906 | size = 1; | |
7907 | if (i.prefix[ADDR_PREFIX] != 0) | |
7908 | { | |
7909 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); | |
7910 | i.prefixes -= 1; | |
7911 | } | |
7912 | /* Pentium4 branch hints. */ | |
7913 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
7914 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
7915 | { | |
7916 | FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); | |
7917 | i.prefixes--; | |
3e73aa7c JH |
7918 | } |
7919 | } | |
29b0f896 AM |
7920 | else |
7921 | { | |
7922 | int code16; | |
3e73aa7c | 7923 | |
29b0f896 AM |
7924 | code16 = 0; |
7925 | if (flag_code == CODE_16BIT) | |
7926 | code16 = CODE16; | |
3e73aa7c | 7927 | |
29b0f896 AM |
7928 | if (i.prefix[DATA_PREFIX] != 0) |
7929 | { | |
7930 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); | |
7931 | i.prefixes -= 1; | |
7932 | code16 ^= CODE16; | |
7933 | } | |
252b5132 | 7934 | |
29b0f896 AM |
7935 | size = 4; |
7936 | if (code16) | |
7937 | size = 2; | |
7938 | } | |
9fcc94b6 | 7939 | |
29b0f896 AM |
7940 | if (i.prefix[REX_PREFIX] != 0) |
7941 | { | |
7942 | FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); | |
7943 | i.prefixes -= 1; | |
7944 | } | |
252b5132 | 7945 | |
7e8b059b L |
7946 | /* BND prefixed jump. */ |
7947 | if (i.prefix[BND_PREFIX] != 0) | |
7948 | { | |
7949 | FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]); | |
7950 | i.prefixes -= 1; | |
7951 | } | |
7952 | ||
29b0f896 AM |
7953 | if (i.prefixes != 0 && !intel_syntax) |
7954 | as_warn (_("skipping prefixes on this instruction")); | |
e0890092 | 7955 | |
42164a71 L |
7956 | p = frag_more (i.tm.opcode_length + size); |
7957 | switch (i.tm.opcode_length) | |
7958 | { | |
7959 | case 2: | |
7960 | *p++ = i.tm.base_opcode >> 8; | |
1a0670f3 | 7961 | /* Fall through. */ |
42164a71 L |
7962 | case 1: |
7963 | *p++ = i.tm.base_opcode; | |
7964 | break; | |
7965 | default: | |
7966 | abort (); | |
7967 | } | |
e0890092 | 7968 | |
bd7ab16b L |
7969 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
7970 | if (size == 4 | |
7971 | && jump_reloc == NO_RELOC | |
7972 | && need_plt32_p (i.op[0].disps->X_add_symbol)) | |
7973 | jump_reloc = BFD_RELOC_X86_64_PLT32; | |
7974 | #endif | |
7975 | ||
7976 | jump_reloc = reloc (size, 1, 1, jump_reloc); | |
7977 | ||
3e02c1cc | 7978 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
bd7ab16b | 7979 | i.op[0].disps, 1, jump_reloc); |
3e02c1cc AM |
7980 | |
7981 | /* All jumps handled here are signed, but don't use a signed limit | |
7982 | check for 32 and 16 bit jumps as we want to allow wrap around at | |
7983 | 4G and 64k respectively. */ | |
7984 | if (size == 1) | |
7985 | fixP->fx_signed = 1; | |
29b0f896 | 7986 | } |
e0890092 | 7987 | |
29b0f896 | 7988 | static void |
e3bb37b5 | 7989 | output_interseg_jump (void) |
29b0f896 AM |
7990 | { |
7991 | char *p; | |
7992 | int size; | |
7993 | int prefix; | |
7994 | int code16; | |
252b5132 | 7995 | |
29b0f896 AM |
7996 | code16 = 0; |
7997 | if (flag_code == CODE_16BIT) | |
7998 | code16 = CODE16; | |
a217f122 | 7999 | |
29b0f896 AM |
8000 | prefix = 0; |
8001 | if (i.prefix[DATA_PREFIX] != 0) | |
8002 | { | |
8003 | prefix = 1; | |
8004 | i.prefixes -= 1; | |
8005 | code16 ^= CODE16; | |
8006 | } | |
8007 | if (i.prefix[REX_PREFIX] != 0) | |
8008 | { | |
8009 | prefix++; | |
8010 | i.prefixes -= 1; | |
8011 | } | |
252b5132 | 8012 | |
29b0f896 AM |
8013 | size = 4; |
8014 | if (code16) | |
8015 | size = 2; | |
252b5132 | 8016 | |
29b0f896 AM |
8017 | if (i.prefixes != 0 && !intel_syntax) |
8018 | as_warn (_("skipping prefixes on this instruction")); | |
252b5132 | 8019 | |
29b0f896 AM |
8020 | /* 1 opcode; 2 segment; offset */ |
8021 | p = frag_more (prefix + 1 + 2 + size); | |
3e73aa7c | 8022 | |
29b0f896 AM |
8023 | if (i.prefix[DATA_PREFIX] != 0) |
8024 | *p++ = DATA_PREFIX_OPCODE; | |
252b5132 | 8025 | |
29b0f896 AM |
8026 | if (i.prefix[REX_PREFIX] != 0) |
8027 | *p++ = i.prefix[REX_PREFIX]; | |
252b5132 | 8028 | |
29b0f896 AM |
8029 | *p++ = i.tm.base_opcode; |
8030 | if (i.op[1].imms->X_op == O_constant) | |
8031 | { | |
8032 | offsetT n = i.op[1].imms->X_add_number; | |
252b5132 | 8033 | |
29b0f896 AM |
8034 | if (size == 2 |
8035 | && !fits_in_unsigned_word (n) | |
8036 | && !fits_in_signed_word (n)) | |
8037 | { | |
8038 | as_bad (_("16-bit jump out of range")); | |
8039 | return; | |
8040 | } | |
8041 | md_number_to_chars (p, n, size); | |
8042 | } | |
8043 | else | |
8044 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
d258b828 | 8045 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); |
29b0f896 AM |
8046 | if (i.op[0].imms->X_op != O_constant) |
8047 | as_bad (_("can't handle non absolute segment in `%s'"), | |
8048 | i.tm.name); | |
8049 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); | |
8050 | } | |
a217f122 | 8051 | |
b4a3a7b4 L |
8052 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8053 | void | |
8054 | x86_cleanup (void) | |
8055 | { | |
8056 | char *p; | |
8057 | asection *seg = now_seg; | |
8058 | subsegT subseg = now_subseg; | |
8059 | asection *sec; | |
8060 | unsigned int alignment, align_size_1; | |
8061 | unsigned int isa_1_descsz, feature_2_descsz, descsz; | |
8062 | unsigned int isa_1_descsz_raw, feature_2_descsz_raw; | |
8063 | unsigned int padding; | |
8064 | ||
8065 | if (!IS_ELF || !x86_used_note) | |
8066 | return; | |
8067 | ||
b4a3a7b4 L |
8068 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X86; |
8069 | ||
8070 | /* The .note.gnu.property section layout: | |
8071 | ||
8072 | Field Length Contents | |
8073 | ---- ---- ---- | |
8074 | n_namsz 4 4 | |
8075 | n_descsz 4 The note descriptor size | |
8076 | n_type 4 NT_GNU_PROPERTY_TYPE_0 | |
8077 | n_name 4 "GNU" | |
8078 | n_desc n_descsz The program property array | |
8079 | .... .... .... | |
8080 | */ | |
8081 | ||
8082 | /* Create the .note.gnu.property section. */ | |
8083 | sec = subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME, 0); | |
fd361982 | 8084 | bfd_set_section_flags (sec, |
b4a3a7b4 L |
8085 | (SEC_ALLOC |
8086 | | SEC_LOAD | |
8087 | | SEC_DATA | |
8088 | | SEC_HAS_CONTENTS | |
8089 | | SEC_READONLY)); | |
8090 | ||
8091 | if (get_elf_backend_data (stdoutput)->s->elfclass == ELFCLASS64) | |
8092 | { | |
8093 | align_size_1 = 7; | |
8094 | alignment = 3; | |
8095 | } | |
8096 | else | |
8097 | { | |
8098 | align_size_1 = 3; | |
8099 | alignment = 2; | |
8100 | } | |
8101 | ||
fd361982 | 8102 | bfd_set_section_alignment (sec, alignment); |
b4a3a7b4 L |
8103 | elf_section_type (sec) = SHT_NOTE; |
8104 | ||
8105 | /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size | |
8106 | + 4-byte data */ | |
8107 | isa_1_descsz_raw = 4 + 4 + 4; | |
8108 | /* Align GNU_PROPERTY_X86_ISA_1_USED. */ | |
8109 | isa_1_descsz = (isa_1_descsz_raw + align_size_1) & ~align_size_1; | |
8110 | ||
8111 | feature_2_descsz_raw = isa_1_descsz; | |
8112 | /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size | |
8113 | + 4-byte data */ | |
8114 | feature_2_descsz_raw += 4 + 4 + 4; | |
8115 | /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */ | |
8116 | feature_2_descsz = ((feature_2_descsz_raw + align_size_1) | |
8117 | & ~align_size_1); | |
8118 | ||
8119 | descsz = feature_2_descsz; | |
8120 | /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */ | |
8121 | p = frag_more (4 + 4 + 4 + 4 + descsz); | |
8122 | ||
8123 | /* Write n_namsz. */ | |
8124 | md_number_to_chars (p, (valueT) 4, 4); | |
8125 | ||
8126 | /* Write n_descsz. */ | |
8127 | md_number_to_chars (p + 4, (valueT) descsz, 4); | |
8128 | ||
8129 | /* Write n_type. */ | |
8130 | md_number_to_chars (p + 4 * 2, (valueT) NT_GNU_PROPERTY_TYPE_0, 4); | |
8131 | ||
8132 | /* Write n_name. */ | |
8133 | memcpy (p + 4 * 3, "GNU", 4); | |
8134 | ||
8135 | /* Write 4-byte type. */ | |
8136 | md_number_to_chars (p + 4 * 4, | |
8137 | (valueT) GNU_PROPERTY_X86_ISA_1_USED, 4); | |
8138 | ||
8139 | /* Write 4-byte data size. */ | |
8140 | md_number_to_chars (p + 4 * 5, (valueT) 4, 4); | |
8141 | ||
8142 | /* Write 4-byte data. */ | |
8143 | md_number_to_chars (p + 4 * 6, (valueT) x86_isa_1_used, 4); | |
8144 | ||
8145 | /* Zero out paddings. */ | |
8146 | padding = isa_1_descsz - isa_1_descsz_raw; | |
8147 | if (padding) | |
8148 | memset (p + 4 * 7, 0, padding); | |
8149 | ||
8150 | /* Write 4-byte type. */ | |
8151 | md_number_to_chars (p + isa_1_descsz + 4 * 4, | |
8152 | (valueT) GNU_PROPERTY_X86_FEATURE_2_USED, 4); | |
8153 | ||
8154 | /* Write 4-byte data size. */ | |
8155 | md_number_to_chars (p + isa_1_descsz + 4 * 5, (valueT) 4, 4); | |
8156 | ||
8157 | /* Write 4-byte data. */ | |
8158 | md_number_to_chars (p + isa_1_descsz + 4 * 6, | |
8159 | (valueT) x86_feature_2_used, 4); | |
8160 | ||
8161 | /* Zero out paddings. */ | |
8162 | padding = feature_2_descsz - feature_2_descsz_raw; | |
8163 | if (padding) | |
8164 | memset (p + isa_1_descsz + 4 * 7, 0, padding); | |
8165 | ||
8166 | /* We probably can't restore the current segment, for there likely | |
8167 | isn't one yet... */ | |
8168 | if (seg && subseg) | |
8169 | subseg_set (seg, subseg); | |
8170 | } | |
8171 | #endif | |
8172 | ||
9c33702b JB |
8173 | static unsigned int |
8174 | encoding_length (const fragS *start_frag, offsetT start_off, | |
8175 | const char *frag_now_ptr) | |
8176 | { | |
8177 | unsigned int len = 0; | |
8178 | ||
8179 | if (start_frag != frag_now) | |
8180 | { | |
8181 | const fragS *fr = start_frag; | |
8182 | ||
8183 | do { | |
8184 | len += fr->fr_fix; | |
8185 | fr = fr->fr_next; | |
8186 | } while (fr && fr != frag_now); | |
8187 | } | |
8188 | ||
8189 | return len - start_off + (frag_now_ptr - frag_now->fr_literal); | |
8190 | } | |
8191 | ||
29b0f896 | 8192 | static void |
e3bb37b5 | 8193 | output_insn (void) |
29b0f896 | 8194 | { |
2bbd9c25 JJ |
8195 | fragS *insn_start_frag; |
8196 | offsetT insn_start_off; | |
8197 | ||
b4a3a7b4 L |
8198 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8199 | if (IS_ELF && x86_used_note) | |
8200 | { | |
8201 | if (i.tm.cpu_flags.bitfield.cpucmov) | |
8202 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_CMOV; | |
8203 | if (i.tm.cpu_flags.bitfield.cpusse) | |
8204 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE; | |
8205 | if (i.tm.cpu_flags.bitfield.cpusse2) | |
8206 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE2; | |
8207 | if (i.tm.cpu_flags.bitfield.cpusse3) | |
8208 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE3; | |
8209 | if (i.tm.cpu_flags.bitfield.cpussse3) | |
8210 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSSE3; | |
8211 | if (i.tm.cpu_flags.bitfield.cpusse4_1) | |
8212 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_1; | |
8213 | if (i.tm.cpu_flags.bitfield.cpusse4_2) | |
8214 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_2; | |
8215 | if (i.tm.cpu_flags.bitfield.cpuavx) | |
8216 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX; | |
8217 | if (i.tm.cpu_flags.bitfield.cpuavx2) | |
8218 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX2; | |
8219 | if (i.tm.cpu_flags.bitfield.cpufma) | |
8220 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_FMA; | |
8221 | if (i.tm.cpu_flags.bitfield.cpuavx512f) | |
8222 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512F; | |
8223 | if (i.tm.cpu_flags.bitfield.cpuavx512cd) | |
8224 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512CD; | |
8225 | if (i.tm.cpu_flags.bitfield.cpuavx512er) | |
8226 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512ER; | |
8227 | if (i.tm.cpu_flags.bitfield.cpuavx512pf) | |
8228 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512PF; | |
8229 | if (i.tm.cpu_flags.bitfield.cpuavx512vl) | |
8230 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512VL; | |
8231 | if (i.tm.cpu_flags.bitfield.cpuavx512dq) | |
8232 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512DQ; | |
8233 | if (i.tm.cpu_flags.bitfield.cpuavx512bw) | |
8234 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512BW; | |
8235 | if (i.tm.cpu_flags.bitfield.cpuavx512_4fmaps) | |
8236 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS; | |
8237 | if (i.tm.cpu_flags.bitfield.cpuavx512_4vnniw) | |
8238 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW; | |
8239 | if (i.tm.cpu_flags.bitfield.cpuavx512_bitalg) | |
8240 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG; | |
8241 | if (i.tm.cpu_flags.bitfield.cpuavx512ifma) | |
8242 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA; | |
8243 | if (i.tm.cpu_flags.bitfield.cpuavx512vbmi) | |
8244 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI; | |
8245 | if (i.tm.cpu_flags.bitfield.cpuavx512_vbmi2) | |
8246 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2; | |
8247 | if (i.tm.cpu_flags.bitfield.cpuavx512_vnni) | |
8248 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI; | |
462cac58 L |
8249 | if (i.tm.cpu_flags.bitfield.cpuavx512_bf16) |
8250 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_BF16; | |
b4a3a7b4 L |
8251 | |
8252 | if (i.tm.cpu_flags.bitfield.cpu8087 | |
8253 | || i.tm.cpu_flags.bitfield.cpu287 | |
8254 | || i.tm.cpu_flags.bitfield.cpu387 | |
8255 | || i.tm.cpu_flags.bitfield.cpu687 | |
8256 | || i.tm.cpu_flags.bitfield.cpufisttp) | |
8257 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X87; | |
8258 | /* Don't set GNU_PROPERTY_X86_FEATURE_2_MMX for prefetchtXXX nor | |
8259 | Xfence instructions. */ | |
8260 | if (i.tm.base_opcode != 0xf18 | |
8261 | && i.tm.base_opcode != 0xf0d | |
c3949f43 | 8262 | && i.tm.base_opcode != 0xfaef8 |
b4a3a7b4 L |
8263 | && (i.has_regmmx |
8264 | || i.tm.cpu_flags.bitfield.cpummx | |
8265 | || i.tm.cpu_flags.bitfield.cpua3dnow | |
8266 | || i.tm.cpu_flags.bitfield.cpua3dnowa)) | |
8267 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MMX; | |
8268 | if (i.has_regxmm) | |
8269 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XMM; | |
8270 | if (i.has_regymm) | |
8271 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_YMM; | |
8272 | if (i.has_regzmm) | |
8273 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_ZMM; | |
8274 | if (i.tm.cpu_flags.bitfield.cpufxsr) | |
8275 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_FXSR; | |
8276 | if (i.tm.cpu_flags.bitfield.cpuxsave) | |
8277 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVE; | |
8278 | if (i.tm.cpu_flags.bitfield.cpuxsaveopt) | |
8279 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT; | |
8280 | if (i.tm.cpu_flags.bitfield.cpuxsavec) | |
8281 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEC; | |
8282 | } | |
8283 | #endif | |
8284 | ||
29b0f896 AM |
8285 | /* Tie dwarf2 debug info to the address at the start of the insn. |
8286 | We can't do this after the insn has been output as the current | |
8287 | frag may have been closed off. eg. by frag_var. */ | |
8288 | dwarf2_emit_insn (0); | |
8289 | ||
2bbd9c25 JJ |
8290 | insn_start_frag = frag_now; |
8291 | insn_start_off = frag_now_fix (); | |
8292 | ||
29b0f896 | 8293 | /* Output jumps. */ |
40fb9820 | 8294 | if (i.tm.opcode_modifier.jump) |
29b0f896 | 8295 | output_branch (); |
40fb9820 L |
8296 | else if (i.tm.opcode_modifier.jumpbyte |
8297 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 | 8298 | output_jump (); |
40fb9820 | 8299 | else if (i.tm.opcode_modifier.jumpintersegment) |
29b0f896 AM |
8300 | output_interseg_jump (); |
8301 | else | |
8302 | { | |
8303 | /* Output normal instructions here. */ | |
8304 | char *p; | |
8305 | unsigned char *q; | |
47465058 | 8306 | unsigned int j; |
331d2d0d | 8307 | unsigned int prefix; |
4dffcebc | 8308 | |
e4e00185 | 8309 | if (avoid_fence |
c3949f43 JB |
8310 | && (i.tm.base_opcode == 0xfaee8 |
8311 | || i.tm.base_opcode == 0xfaef0 | |
8312 | || i.tm.base_opcode == 0xfaef8)) | |
e4e00185 AS |
8313 | { |
8314 | /* Encode lfence, mfence, and sfence as | |
8315 | f0 83 04 24 00 lock addl $0x0, (%{re}sp). */ | |
8316 | offsetT val = 0x240483f0ULL; | |
8317 | p = frag_more (5); | |
8318 | md_number_to_chars (p, val, 5); | |
8319 | return; | |
8320 | } | |
8321 | ||
d022bddd IT |
8322 | /* Some processors fail on LOCK prefix. This options makes |
8323 | assembler ignore LOCK prefix and serves as a workaround. */ | |
8324 | if (omit_lock_prefix) | |
8325 | { | |
8326 | if (i.tm.base_opcode == LOCK_PREFIX_OPCODE) | |
8327 | return; | |
8328 | i.prefix[LOCK_PREFIX] = 0; | |
8329 | } | |
8330 | ||
43234a1e L |
8331 | /* Since the VEX/EVEX prefix contains the implicit prefix, we |
8332 | don't need the explicit prefix. */ | |
8333 | if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex) | |
bc4bd9ab | 8334 | { |
c0f3af97 | 8335 | switch (i.tm.opcode_length) |
bc4bd9ab | 8336 | { |
c0f3af97 L |
8337 | case 3: |
8338 | if (i.tm.base_opcode & 0xff000000) | |
4dffcebc | 8339 | { |
c0f3af97 | 8340 | prefix = (i.tm.base_opcode >> 24) & 0xff; |
c3949f43 JB |
8341 | if (!i.tm.cpu_flags.bitfield.cpupadlock |
8342 | || prefix != REPE_PREFIX_OPCODE | |
8343 | || (i.prefix[REP_PREFIX] != REPE_PREFIX_OPCODE)) | |
8344 | add_prefix (prefix); | |
c0f3af97 L |
8345 | } |
8346 | break; | |
8347 | case 2: | |
8348 | if ((i.tm.base_opcode & 0xff0000) != 0) | |
8349 | { | |
8350 | prefix = (i.tm.base_opcode >> 16) & 0xff; | |
c3949f43 | 8351 | add_prefix (prefix); |
4dffcebc | 8352 | } |
c0f3af97 L |
8353 | break; |
8354 | case 1: | |
8355 | break; | |
390c91cf L |
8356 | case 0: |
8357 | /* Check for pseudo prefixes. */ | |
8358 | as_bad_where (insn_start_frag->fr_file, | |
8359 | insn_start_frag->fr_line, | |
8360 | _("pseudo prefix without instruction")); | |
8361 | return; | |
c0f3af97 L |
8362 | default: |
8363 | abort (); | |
bc4bd9ab | 8364 | } |
c0f3af97 | 8365 | |
6d19a37a | 8366 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
cf61b747 L |
8367 | /* For x32, add a dummy REX_OPCODE prefix for mov/add with |
8368 | R_X86_64_GOTTPOFF relocation so that linker can safely | |
8369 | perform IE->LE optimization. */ | |
8370 | if (x86_elf_abi == X86_64_X32_ABI | |
8371 | && i.operands == 2 | |
8372 | && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF | |
8373 | && i.prefix[REX_PREFIX] == 0) | |
8374 | add_prefix (REX_OPCODE); | |
6d19a37a | 8375 | #endif |
cf61b747 | 8376 | |
c0f3af97 L |
8377 | /* The prefix bytes. */ |
8378 | for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) | |
8379 | if (*q) | |
8380 | FRAG_APPEND_1_CHAR (*q); | |
0f10071e | 8381 | } |
ae5c1c7b | 8382 | else |
c0f3af97 L |
8383 | { |
8384 | for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++) | |
8385 | if (*q) | |
8386 | switch (j) | |
8387 | { | |
8388 | case REX_PREFIX: | |
8389 | /* REX byte is encoded in VEX prefix. */ | |
8390 | break; | |
8391 | case SEG_PREFIX: | |
8392 | case ADDR_PREFIX: | |
8393 | FRAG_APPEND_1_CHAR (*q); | |
8394 | break; | |
8395 | default: | |
8396 | /* There should be no other prefixes for instructions | |
8397 | with VEX prefix. */ | |
8398 | abort (); | |
8399 | } | |
8400 | ||
43234a1e L |
8401 | /* For EVEX instructions i.vrex should become 0 after |
8402 | build_evex_prefix. For VEX instructions upper 16 registers | |
8403 | aren't available, so VREX should be 0. */ | |
8404 | if (i.vrex) | |
8405 | abort (); | |
c0f3af97 L |
8406 | /* Now the VEX prefix. */ |
8407 | p = frag_more (i.vex.length); | |
8408 | for (j = 0; j < i.vex.length; j++) | |
8409 | p[j] = i.vex.bytes[j]; | |
8410 | } | |
252b5132 | 8411 | |
29b0f896 | 8412 | /* Now the opcode; be careful about word order here! */ |
4dffcebc | 8413 | if (i.tm.opcode_length == 1) |
29b0f896 AM |
8414 | { |
8415 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
8416 | } | |
8417 | else | |
8418 | { | |
4dffcebc | 8419 | switch (i.tm.opcode_length) |
331d2d0d | 8420 | { |
43234a1e L |
8421 | case 4: |
8422 | p = frag_more (4); | |
8423 | *p++ = (i.tm.base_opcode >> 24) & 0xff; | |
8424 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
8425 | break; | |
4dffcebc | 8426 | case 3: |
331d2d0d L |
8427 | p = frag_more (3); |
8428 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
4dffcebc L |
8429 | break; |
8430 | case 2: | |
8431 | p = frag_more (2); | |
8432 | break; | |
8433 | default: | |
8434 | abort (); | |
8435 | break; | |
331d2d0d | 8436 | } |
0f10071e | 8437 | |
29b0f896 AM |
8438 | /* Put out high byte first: can't use md_number_to_chars! */ |
8439 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
8440 | *p = i.tm.base_opcode & 0xff; | |
8441 | } | |
3e73aa7c | 8442 | |
29b0f896 | 8443 | /* Now the modrm byte and sib byte (if present). */ |
40fb9820 | 8444 | if (i.tm.opcode_modifier.modrm) |
29b0f896 | 8445 | { |
4a3523fa L |
8446 | FRAG_APPEND_1_CHAR ((i.rm.regmem << 0 |
8447 | | i.rm.reg << 3 | |
8448 | | i.rm.mode << 6)); | |
29b0f896 AM |
8449 | /* If i.rm.regmem == ESP (4) |
8450 | && i.rm.mode != (Register mode) | |
8451 | && not 16 bit | |
8452 | ==> need second modrm byte. */ | |
8453 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
8454 | && i.rm.mode != 3 | |
dc821c5f | 8455 | && !(i.base_reg && i.base_reg->reg_type.bitfield.word)) |
4a3523fa L |
8456 | FRAG_APPEND_1_CHAR ((i.sib.base << 0 |
8457 | | i.sib.index << 3 | |
8458 | | i.sib.scale << 6)); | |
29b0f896 | 8459 | } |
3e73aa7c | 8460 | |
29b0f896 | 8461 | if (i.disp_operands) |
2bbd9c25 | 8462 | output_disp (insn_start_frag, insn_start_off); |
3e73aa7c | 8463 | |
29b0f896 | 8464 | if (i.imm_operands) |
2bbd9c25 | 8465 | output_imm (insn_start_frag, insn_start_off); |
9c33702b JB |
8466 | |
8467 | /* | |
8468 | * frag_now_fix () returning plain abs_section_offset when we're in the | |
8469 | * absolute section, and abs_section_offset not getting updated as data | |
8470 | * gets added to the frag breaks the logic below. | |
8471 | */ | |
8472 | if (now_seg != absolute_section) | |
8473 | { | |
8474 | j = encoding_length (insn_start_frag, insn_start_off, frag_more (0)); | |
8475 | if (j > 15) | |
8476 | as_warn (_("instruction length of %u bytes exceeds the limit of 15"), | |
8477 | j); | |
8478 | } | |
29b0f896 | 8479 | } |
252b5132 | 8480 | |
29b0f896 AM |
8481 | #ifdef DEBUG386 |
8482 | if (flag_debug) | |
8483 | { | |
7b81dfbb | 8484 | pi ("" /*line*/, &i); |
29b0f896 AM |
8485 | } |
8486 | #endif /* DEBUG386 */ | |
8487 | } | |
252b5132 | 8488 | |
e205caa7 L |
8489 | /* Return the size of the displacement operand N. */ |
8490 | ||
8491 | static int | |
8492 | disp_size (unsigned int n) | |
8493 | { | |
8494 | int size = 4; | |
43234a1e | 8495 | |
b5014f7a | 8496 | if (i.types[n].bitfield.disp64) |
40fb9820 L |
8497 | size = 8; |
8498 | else if (i.types[n].bitfield.disp8) | |
8499 | size = 1; | |
8500 | else if (i.types[n].bitfield.disp16) | |
8501 | size = 2; | |
e205caa7 L |
8502 | return size; |
8503 | } | |
8504 | ||
8505 | /* Return the size of the immediate operand N. */ | |
8506 | ||
8507 | static int | |
8508 | imm_size (unsigned int n) | |
8509 | { | |
8510 | int size = 4; | |
40fb9820 L |
8511 | if (i.types[n].bitfield.imm64) |
8512 | size = 8; | |
8513 | else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) | |
8514 | size = 1; | |
8515 | else if (i.types[n].bitfield.imm16) | |
8516 | size = 2; | |
e205caa7 L |
8517 | return size; |
8518 | } | |
8519 | ||
29b0f896 | 8520 | static void |
64e74474 | 8521 | output_disp (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
8522 | { |
8523 | char *p; | |
8524 | unsigned int n; | |
252b5132 | 8525 | |
29b0f896 AM |
8526 | for (n = 0; n < i.operands; n++) |
8527 | { | |
b5014f7a | 8528 | if (operand_type_check (i.types[n], disp)) |
29b0f896 AM |
8529 | { |
8530 | if (i.op[n].disps->X_op == O_constant) | |
8531 | { | |
e205caa7 | 8532 | int size = disp_size (n); |
43234a1e | 8533 | offsetT val = i.op[n].disps->X_add_number; |
252b5132 | 8534 | |
629cfaf1 JB |
8535 | val = offset_in_range (val >> (size == 1 ? i.memshift : 0), |
8536 | size); | |
29b0f896 AM |
8537 | p = frag_more (size); |
8538 | md_number_to_chars (p, val, size); | |
8539 | } | |
8540 | else | |
8541 | { | |
f86103b7 | 8542 | enum bfd_reloc_code_real reloc_type; |
e205caa7 | 8543 | int size = disp_size (n); |
40fb9820 | 8544 | int sign = i.types[n].bitfield.disp32s; |
29b0f896 | 8545 | int pcrel = (i.flags[n] & Operand_PCrel) != 0; |
02a86693 | 8546 | fixS *fixP; |
29b0f896 | 8547 | |
e205caa7 | 8548 | /* We can't have 8 bit displacement here. */ |
9c2799c2 | 8549 | gas_assert (!i.types[n].bitfield.disp8); |
e205caa7 | 8550 | |
29b0f896 AM |
8551 | /* The PC relative address is computed relative |
8552 | to the instruction boundary, so in case immediate | |
8553 | fields follows, we need to adjust the value. */ | |
8554 | if (pcrel && i.imm_operands) | |
8555 | { | |
29b0f896 | 8556 | unsigned int n1; |
e205caa7 | 8557 | int sz = 0; |
252b5132 | 8558 | |
29b0f896 | 8559 | for (n1 = 0; n1 < i.operands; n1++) |
40fb9820 | 8560 | if (operand_type_check (i.types[n1], imm)) |
252b5132 | 8561 | { |
e205caa7 L |
8562 | /* Only one immediate is allowed for PC |
8563 | relative address. */ | |
9c2799c2 | 8564 | gas_assert (sz == 0); |
e205caa7 L |
8565 | sz = imm_size (n1); |
8566 | i.op[n].disps->X_add_number -= sz; | |
252b5132 | 8567 | } |
29b0f896 | 8568 | /* We should find the immediate. */ |
9c2799c2 | 8569 | gas_assert (sz != 0); |
29b0f896 | 8570 | } |
520dc8e8 | 8571 | |
29b0f896 | 8572 | p = frag_more (size); |
d258b828 | 8573 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
d6ab8113 | 8574 | if (GOT_symbol |
2bbd9c25 | 8575 | && GOT_symbol == i.op[n].disps->X_add_symbol |
d6ab8113 | 8576 | && (((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
8577 | || reloc_type == BFD_RELOC_X86_64_32S |
8578 | || (reloc_type == BFD_RELOC_64 | |
8579 | && object_64bit)) | |
d6ab8113 JB |
8580 | && (i.op[n].disps->X_op == O_symbol |
8581 | || (i.op[n].disps->X_op == O_add | |
8582 | && ((symbol_get_value_expression | |
8583 | (i.op[n].disps->X_op_symbol)->X_op) | |
8584 | == O_subtract)))) | |
8585 | || reloc_type == BFD_RELOC_32_PCREL)) | |
2bbd9c25 | 8586 | { |
4fa24527 | 8587 | if (!object_64bit) |
7b81dfbb AJ |
8588 | { |
8589 | reloc_type = BFD_RELOC_386_GOTPC; | |
d583596c JB |
8590 | i.op[n].imms->X_add_number += |
8591 | encoding_length (insn_start_frag, insn_start_off, p); | |
7b81dfbb AJ |
8592 | } |
8593 | else if (reloc_type == BFD_RELOC_64) | |
8594 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
d6ab8113 | 8595 | else |
7b81dfbb AJ |
8596 | /* Don't do the adjustment for x86-64, as there |
8597 | the pcrel addressing is relative to the _next_ | |
8598 | insn, and that is taken care of in other code. */ | |
d6ab8113 | 8599 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
2bbd9c25 | 8600 | } |
02a86693 L |
8601 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, |
8602 | size, i.op[n].disps, pcrel, | |
8603 | reloc_type); | |
8604 | /* Check for "call/jmp *mem", "mov mem, %reg", | |
8605 | "test %reg, mem" and "binop mem, %reg" where binop | |
8606 | is one of adc, add, and, cmp, or, sbb, sub, xor | |
e60f4d3b L |
8607 | instructions without data prefix. Always generate |
8608 | R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */ | |
8609 | if (i.prefix[DATA_PREFIX] == 0 | |
8610 | && (generate_relax_relocations | |
8611 | || (!object_64bit | |
8612 | && i.rm.mode == 0 | |
8613 | && i.rm.regmem == 5)) | |
0cb4071e L |
8614 | && (i.rm.mode == 2 |
8615 | || (i.rm.mode == 0 && i.rm.regmem == 5)) | |
02a86693 L |
8616 | && ((i.operands == 1 |
8617 | && i.tm.base_opcode == 0xff | |
8618 | && (i.rm.reg == 2 || i.rm.reg == 4)) | |
8619 | || (i.operands == 2 | |
8620 | && (i.tm.base_opcode == 0x8b | |
8621 | || i.tm.base_opcode == 0x85 | |
8622 | || (i.tm.base_opcode & 0xc7) == 0x03)))) | |
8623 | { | |
8624 | if (object_64bit) | |
8625 | { | |
8626 | fixP->fx_tcbit = i.rex != 0; | |
8627 | if (i.base_reg | |
e968fc9b | 8628 | && (i.base_reg->reg_num == RegIP)) |
02a86693 L |
8629 | fixP->fx_tcbit2 = 1; |
8630 | } | |
8631 | else | |
8632 | fixP->fx_tcbit2 = 1; | |
8633 | } | |
29b0f896 AM |
8634 | } |
8635 | } | |
8636 | } | |
8637 | } | |
252b5132 | 8638 | |
29b0f896 | 8639 | static void |
64e74474 | 8640 | output_imm (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
8641 | { |
8642 | char *p; | |
8643 | unsigned int n; | |
252b5132 | 8644 | |
29b0f896 AM |
8645 | for (n = 0; n < i.operands; n++) |
8646 | { | |
43234a1e L |
8647 | /* Skip SAE/RC Imm operand in EVEX. They are already handled. */ |
8648 | if (i.rounding && (int) n == i.rounding->operand) | |
8649 | continue; | |
8650 | ||
40fb9820 | 8651 | if (operand_type_check (i.types[n], imm)) |
29b0f896 AM |
8652 | { |
8653 | if (i.op[n].imms->X_op == O_constant) | |
8654 | { | |
e205caa7 | 8655 | int size = imm_size (n); |
29b0f896 | 8656 | offsetT val; |
b4cac588 | 8657 | |
29b0f896 AM |
8658 | val = offset_in_range (i.op[n].imms->X_add_number, |
8659 | size); | |
8660 | p = frag_more (size); | |
8661 | md_number_to_chars (p, val, size); | |
8662 | } | |
8663 | else | |
8664 | { | |
8665 | /* Not absolute_section. | |
8666 | Need a 32-bit fixup (don't support 8bit | |
8667 | non-absolute imms). Try to support other | |
8668 | sizes ... */ | |
f86103b7 | 8669 | enum bfd_reloc_code_real reloc_type; |
e205caa7 L |
8670 | int size = imm_size (n); |
8671 | int sign; | |
29b0f896 | 8672 | |
40fb9820 | 8673 | if (i.types[n].bitfield.imm32s |
a7d61044 | 8674 | && (i.suffix == QWORD_MNEM_SUFFIX |
40fb9820 | 8675 | || (!i.suffix && i.tm.opcode_modifier.no_lsuf))) |
29b0f896 | 8676 | sign = 1; |
e205caa7 L |
8677 | else |
8678 | sign = 0; | |
520dc8e8 | 8679 | |
29b0f896 | 8680 | p = frag_more (size); |
d258b828 | 8681 | reloc_type = reloc (size, 0, sign, i.reloc[n]); |
f86103b7 | 8682 | |
2bbd9c25 JJ |
8683 | /* This is tough to explain. We end up with this one if we |
8684 | * have operands that look like | |
8685 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to | |
8686 | * obtain the absolute address of the GOT, and it is strongly | |
8687 | * preferable from a performance point of view to avoid using | |
8688 | * a runtime relocation for this. The actual sequence of | |
8689 | * instructions often look something like: | |
8690 | * | |
8691 | * call .L66 | |
8692 | * .L66: | |
8693 | * popl %ebx | |
8694 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
8695 | * | |
8696 | * The call and pop essentially return the absolute address | |
8697 | * of the label .L66 and store it in %ebx. The linker itself | |
8698 | * will ultimately change the first operand of the addl so | |
8699 | * that %ebx points to the GOT, but to keep things simple, the | |
8700 | * .o file must have this operand set so that it generates not | |
8701 | * the absolute address of .L66, but the absolute address of | |
8702 | * itself. This allows the linker itself simply treat a GOTPC | |
8703 | * relocation as asking for a pcrel offset to the GOT to be | |
8704 | * added in, and the addend of the relocation is stored in the | |
8705 | * operand field for the instruction itself. | |
8706 | * | |
8707 | * Our job here is to fix the operand so that it would add | |
8708 | * the correct offset so that %ebx would point to itself. The | |
8709 | * thing that is tricky is that .-.L66 will point to the | |
8710 | * beginning of the instruction, so we need to further modify | |
8711 | * the operand so that it will point to itself. There are | |
8712 | * other cases where you have something like: | |
8713 | * | |
8714 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
8715 | * | |
8716 | * and here no correction would be required. Internally in | |
8717 | * the assembler we treat operands of this form as not being | |
8718 | * pcrel since the '.' is explicitly mentioned, and I wonder | |
8719 | * whether it would simplify matters to do it this way. Who | |
8720 | * knows. In earlier versions of the PIC patches, the | |
8721 | * pcrel_adjust field was used to store the correction, but | |
8722 | * since the expression is not pcrel, I felt it would be | |
8723 | * confusing to do it this way. */ | |
8724 | ||
d6ab8113 | 8725 | if ((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
8726 | || reloc_type == BFD_RELOC_X86_64_32S |
8727 | || reloc_type == BFD_RELOC_64) | |
29b0f896 AM |
8728 | && GOT_symbol |
8729 | && GOT_symbol == i.op[n].imms->X_add_symbol | |
8730 | && (i.op[n].imms->X_op == O_symbol | |
8731 | || (i.op[n].imms->X_op == O_add | |
8732 | && ((symbol_get_value_expression | |
8733 | (i.op[n].imms->X_op_symbol)->X_op) | |
8734 | == O_subtract)))) | |
8735 | { | |
4fa24527 | 8736 | if (!object_64bit) |
d6ab8113 | 8737 | reloc_type = BFD_RELOC_386_GOTPC; |
7b81dfbb | 8738 | else if (size == 4) |
d6ab8113 | 8739 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
7b81dfbb AJ |
8740 | else if (size == 8) |
8741 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
d583596c JB |
8742 | i.op[n].imms->X_add_number += |
8743 | encoding_length (insn_start_frag, insn_start_off, p); | |
29b0f896 | 8744 | } |
29b0f896 AM |
8745 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
8746 | i.op[n].imms, 0, reloc_type); | |
8747 | } | |
8748 | } | |
8749 | } | |
252b5132 RH |
8750 | } |
8751 | \f | |
d182319b JB |
8752 | /* x86_cons_fix_new is called via the expression parsing code when a |
8753 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
d182319b JB |
8754 | static int cons_sign = -1; |
8755 | ||
8756 | void | |
e3bb37b5 | 8757 | x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, |
62ebcb5c | 8758 | expressionS *exp, bfd_reloc_code_real_type r) |
d182319b | 8759 | { |
d258b828 | 8760 | r = reloc (len, 0, cons_sign, r); |
d182319b JB |
8761 | |
8762 | #ifdef TE_PE | |
8763 | if (exp->X_op == O_secrel) | |
8764 | { | |
8765 | exp->X_op = O_symbol; | |
8766 | r = BFD_RELOC_32_SECREL; | |
8767 | } | |
8768 | #endif | |
8769 | ||
8770 | fix_new_exp (frag, off, len, exp, 0, r); | |
8771 | } | |
8772 | ||
357d1bd8 L |
8773 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
8774 | purpose of the `.dc.a' internal pseudo-op. */ | |
8775 | ||
8776 | int | |
8777 | x86_address_bytes (void) | |
8778 | { | |
8779 | if ((stdoutput->arch_info->mach & bfd_mach_x64_32)) | |
8780 | return 4; | |
8781 | return stdoutput->arch_info->bits_per_address / 8; | |
8782 | } | |
8783 | ||
d382c579 TG |
8784 | #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \ |
8785 | || defined (LEX_AT) | |
d258b828 | 8786 | # define lex_got(reloc, adjust, types) NULL |
718ddfc0 | 8787 | #else |
f3c180ae AM |
8788 | /* Parse operands of the form |
8789 | <symbol>@GOTOFF+<nnn> | |
8790 | and similar .plt or .got references. | |
8791 | ||
8792 | If we find one, set up the correct relocation in RELOC and copy the | |
8793 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
8794 | parsing by the calling routine. Return this buffer, and if ADJUST | |
8795 | is non-null set it to the length of the string we removed from the | |
8796 | input line. Otherwise return NULL. */ | |
8797 | static char * | |
91d6fa6a | 8798 | lex_got (enum bfd_reloc_code_real *rel, |
64e74474 | 8799 | int *adjust, |
d258b828 | 8800 | i386_operand_type *types) |
f3c180ae | 8801 | { |
7b81dfbb AJ |
8802 | /* Some of the relocations depend on the size of what field is to |
8803 | be relocated. But in our callers i386_immediate and i386_displacement | |
8804 | we don't yet know the operand size (this will be set by insn | |
8805 | matching). Hence we record the word32 relocation here, | |
8806 | and adjust the reloc according to the real size in reloc(). */ | |
f3c180ae AM |
8807 | static const struct { |
8808 | const char *str; | |
cff8d58a | 8809 | int len; |
4fa24527 | 8810 | const enum bfd_reloc_code_real rel[2]; |
40fb9820 | 8811 | const i386_operand_type types64; |
f3c180ae | 8812 | } gotrel[] = { |
8ce3d284 | 8813 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
8814 | { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32, |
8815 | BFD_RELOC_SIZE32 }, | |
8816 | OPERAND_TYPE_IMM32_64 }, | |
8ce3d284 | 8817 | #endif |
cff8d58a L |
8818 | { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real, |
8819 | BFD_RELOC_X86_64_PLTOFF64 }, | |
40fb9820 | 8820 | OPERAND_TYPE_IMM64 }, |
cff8d58a L |
8821 | { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32, |
8822 | BFD_RELOC_X86_64_PLT32 }, | |
40fb9820 | 8823 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8824 | { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real, |
8825 | BFD_RELOC_X86_64_GOTPLT64 }, | |
40fb9820 | 8826 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
8827 | { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF, |
8828 | BFD_RELOC_X86_64_GOTOFF64 }, | |
40fb9820 | 8829 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
8830 | { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real, |
8831 | BFD_RELOC_X86_64_GOTPCREL }, | |
40fb9820 | 8832 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8833 | { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD, |
8834 | BFD_RELOC_X86_64_TLSGD }, | |
40fb9820 | 8835 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8836 | { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM, |
8837 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 8838 | OPERAND_TYPE_NONE }, |
cff8d58a L |
8839 | { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real, |
8840 | BFD_RELOC_X86_64_TLSLD }, | |
40fb9820 | 8841 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8842 | { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32, |
8843 | BFD_RELOC_X86_64_GOTTPOFF }, | |
40fb9820 | 8844 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8845 | { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32, |
8846 | BFD_RELOC_X86_64_TPOFF32 }, | |
40fb9820 | 8847 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
8848 | { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE, |
8849 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 8850 | OPERAND_TYPE_NONE }, |
cff8d58a L |
8851 | { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32, |
8852 | BFD_RELOC_X86_64_DTPOFF32 }, | |
40fb9820 | 8853 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
8854 | { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE, |
8855 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 8856 | OPERAND_TYPE_NONE }, |
cff8d58a L |
8857 | { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE, |
8858 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 8859 | OPERAND_TYPE_NONE }, |
cff8d58a L |
8860 | { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32, |
8861 | BFD_RELOC_X86_64_GOT32 }, | |
40fb9820 | 8862 | OPERAND_TYPE_IMM32_32S_64_DISP32 }, |
cff8d58a L |
8863 | { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC, |
8864 | BFD_RELOC_X86_64_GOTPC32_TLSDESC }, | |
40fb9820 | 8865 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8866 | { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL, |
8867 | BFD_RELOC_X86_64_TLSDESC_CALL }, | |
40fb9820 | 8868 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
f3c180ae AM |
8869 | }; |
8870 | char *cp; | |
8871 | unsigned int j; | |
8872 | ||
d382c579 | 8873 | #if defined (OBJ_MAYBE_ELF) |
718ddfc0 JB |
8874 | if (!IS_ELF) |
8875 | return NULL; | |
d382c579 | 8876 | #endif |
718ddfc0 | 8877 | |
f3c180ae | 8878 | for (cp = input_line_pointer; *cp != '@'; cp++) |
67c11a9b | 8879 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') |
f3c180ae AM |
8880 | return NULL; |
8881 | ||
47465058 | 8882 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) |
f3c180ae | 8883 | { |
cff8d58a | 8884 | int len = gotrel[j].len; |
28f81592 | 8885 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae | 8886 | { |
4fa24527 | 8887 | if (gotrel[j].rel[object_64bit] != 0) |
f3c180ae | 8888 | { |
28f81592 AM |
8889 | int first, second; |
8890 | char *tmpbuf, *past_reloc; | |
f3c180ae | 8891 | |
91d6fa6a | 8892 | *rel = gotrel[j].rel[object_64bit]; |
f3c180ae | 8893 | |
3956db08 JB |
8894 | if (types) |
8895 | { | |
8896 | if (flag_code != CODE_64BIT) | |
40fb9820 L |
8897 | { |
8898 | types->bitfield.imm32 = 1; | |
8899 | types->bitfield.disp32 = 1; | |
8900 | } | |
3956db08 JB |
8901 | else |
8902 | *types = gotrel[j].types64; | |
8903 | } | |
8904 | ||
8fd4256d | 8905 | if (j != 0 && GOT_symbol == NULL) |
f3c180ae AM |
8906 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); |
8907 | ||
28f81592 | 8908 | /* The length of the first part of our input line. */ |
f3c180ae | 8909 | first = cp - input_line_pointer; |
28f81592 AM |
8910 | |
8911 | /* The second part goes from after the reloc token until | |
67c11a9b | 8912 | (and including) an end_of_line char or comma. */ |
28f81592 | 8913 | past_reloc = cp + 1 + len; |
67c11a9b AM |
8914 | cp = past_reloc; |
8915 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
8916 | ++cp; | |
8917 | second = cp + 1 - past_reloc; | |
28f81592 AM |
8918 | |
8919 | /* Allocate and copy string. The trailing NUL shouldn't | |
8920 | be necessary, but be safe. */ | |
add39d23 | 8921 | tmpbuf = XNEWVEC (char, first + second + 2); |
f3c180ae | 8922 | memcpy (tmpbuf, input_line_pointer, first); |
0787a12d AM |
8923 | if (second != 0 && *past_reloc != ' ') |
8924 | /* Replace the relocation token with ' ', so that | |
8925 | errors like foo@GOTOFF1 will be detected. */ | |
8926 | tmpbuf[first++] = ' '; | |
af89796a L |
8927 | else |
8928 | /* Increment length by 1 if the relocation token is | |
8929 | removed. */ | |
8930 | len++; | |
8931 | if (adjust) | |
8932 | *adjust = len; | |
0787a12d AM |
8933 | memcpy (tmpbuf + first, past_reloc, second); |
8934 | tmpbuf[first + second] = '\0'; | |
f3c180ae AM |
8935 | return tmpbuf; |
8936 | } | |
8937 | ||
4fa24527 JB |
8938 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
8939 | gotrel[j].str, 1 << (5 + object_64bit)); | |
f3c180ae AM |
8940 | return NULL; |
8941 | } | |
8942 | } | |
8943 | ||
8944 | /* Might be a symbol version string. Don't as_bad here. */ | |
8945 | return NULL; | |
8946 | } | |
4e4f7c87 | 8947 | #endif |
f3c180ae | 8948 | |
a988325c NC |
8949 | #ifdef TE_PE |
8950 | #ifdef lex_got | |
8951 | #undef lex_got | |
8952 | #endif | |
8953 | /* Parse operands of the form | |
8954 | <symbol>@SECREL32+<nnn> | |
8955 | ||
8956 | If we find one, set up the correct relocation in RELOC and copy the | |
8957 | input string, minus the `@SECREL32' into a malloc'd buffer for | |
8958 | parsing by the calling routine. Return this buffer, and if ADJUST | |
8959 | is non-null set it to the length of the string we removed from the | |
34bca508 L |
8960 | input line. Otherwise return NULL. |
8961 | ||
a988325c NC |
8962 | This function is copied from the ELF version above adjusted for PE targets. */ |
8963 | ||
8964 | static char * | |
8965 | lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED, | |
8966 | int *adjust ATTRIBUTE_UNUSED, | |
d258b828 | 8967 | i386_operand_type *types) |
a988325c NC |
8968 | { |
8969 | static const struct | |
8970 | { | |
8971 | const char *str; | |
8972 | int len; | |
8973 | const enum bfd_reloc_code_real rel[2]; | |
8974 | const i386_operand_type types64; | |
8975 | } | |
8976 | gotrel[] = | |
8977 | { | |
8978 | { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL, | |
8979 | BFD_RELOC_32_SECREL }, | |
8980 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, | |
8981 | }; | |
8982 | ||
8983 | char *cp; | |
8984 | unsigned j; | |
8985 | ||
8986 | for (cp = input_line_pointer; *cp != '@'; cp++) | |
8987 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') | |
8988 | return NULL; | |
8989 | ||
8990 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) | |
8991 | { | |
8992 | int len = gotrel[j].len; | |
8993 | ||
8994 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) | |
8995 | { | |
8996 | if (gotrel[j].rel[object_64bit] != 0) | |
8997 | { | |
8998 | int first, second; | |
8999 | char *tmpbuf, *past_reloc; | |
9000 | ||
9001 | *rel = gotrel[j].rel[object_64bit]; | |
9002 | if (adjust) | |
9003 | *adjust = len; | |
9004 | ||
9005 | if (types) | |
9006 | { | |
9007 | if (flag_code != CODE_64BIT) | |
9008 | { | |
9009 | types->bitfield.imm32 = 1; | |
9010 | types->bitfield.disp32 = 1; | |
9011 | } | |
9012 | else | |
9013 | *types = gotrel[j].types64; | |
9014 | } | |
9015 | ||
9016 | /* The length of the first part of our input line. */ | |
9017 | first = cp - input_line_pointer; | |
9018 | ||
9019 | /* The second part goes from after the reloc token until | |
9020 | (and including) an end_of_line char or comma. */ | |
9021 | past_reloc = cp + 1 + len; | |
9022 | cp = past_reloc; | |
9023 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
9024 | ++cp; | |
9025 | second = cp + 1 - past_reloc; | |
9026 | ||
9027 | /* Allocate and copy string. The trailing NUL shouldn't | |
9028 | be necessary, but be safe. */ | |
add39d23 | 9029 | tmpbuf = XNEWVEC (char, first + second + 2); |
a988325c NC |
9030 | memcpy (tmpbuf, input_line_pointer, first); |
9031 | if (second != 0 && *past_reloc != ' ') | |
9032 | /* Replace the relocation token with ' ', so that | |
9033 | errors like foo@SECLREL321 will be detected. */ | |
9034 | tmpbuf[first++] = ' '; | |
9035 | memcpy (tmpbuf + first, past_reloc, second); | |
9036 | tmpbuf[first + second] = '\0'; | |
9037 | return tmpbuf; | |
9038 | } | |
9039 | ||
9040 | as_bad (_("@%s reloc is not supported with %d-bit output format"), | |
9041 | gotrel[j].str, 1 << (5 + object_64bit)); | |
9042 | return NULL; | |
9043 | } | |
9044 | } | |
9045 | ||
9046 | /* Might be a symbol version string. Don't as_bad here. */ | |
9047 | return NULL; | |
9048 | } | |
9049 | ||
9050 | #endif /* TE_PE */ | |
9051 | ||
62ebcb5c | 9052 | bfd_reloc_code_real_type |
e3bb37b5 | 9053 | x86_cons (expressionS *exp, int size) |
f3c180ae | 9054 | { |
62ebcb5c AM |
9055 | bfd_reloc_code_real_type got_reloc = NO_RELOC; |
9056 | ||
ee86248c JB |
9057 | intel_syntax = -intel_syntax; |
9058 | ||
3c7b9c2c | 9059 | exp->X_md = 0; |
4fa24527 | 9060 | if (size == 4 || (object_64bit && size == 8)) |
f3c180ae AM |
9061 | { |
9062 | /* Handle @GOTOFF and the like in an expression. */ | |
9063 | char *save; | |
9064 | char *gotfree_input_line; | |
4a57f2cf | 9065 | int adjust = 0; |
f3c180ae AM |
9066 | |
9067 | save = input_line_pointer; | |
d258b828 | 9068 | gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); |
f3c180ae AM |
9069 | if (gotfree_input_line) |
9070 | input_line_pointer = gotfree_input_line; | |
9071 | ||
9072 | expression (exp); | |
9073 | ||
9074 | if (gotfree_input_line) | |
9075 | { | |
9076 | /* expression () has merrily parsed up to the end of line, | |
9077 | or a comma - in the wrong buffer. Transfer how far | |
9078 | input_line_pointer has moved to the right buffer. */ | |
9079 | input_line_pointer = (save | |
9080 | + (input_line_pointer - gotfree_input_line) | |
9081 | + adjust); | |
9082 | free (gotfree_input_line); | |
3992d3b7 AM |
9083 | if (exp->X_op == O_constant |
9084 | || exp->X_op == O_absent | |
9085 | || exp->X_op == O_illegal | |
0398aac5 | 9086 | || exp->X_op == O_register |
3992d3b7 AM |
9087 | || exp->X_op == O_big) |
9088 | { | |
9089 | char c = *input_line_pointer; | |
9090 | *input_line_pointer = 0; | |
9091 | as_bad (_("missing or invalid expression `%s'"), save); | |
9092 | *input_line_pointer = c; | |
9093 | } | |
b9519cfe L |
9094 | else if ((got_reloc == BFD_RELOC_386_PLT32 |
9095 | || got_reloc == BFD_RELOC_X86_64_PLT32) | |
9096 | && exp->X_op != O_symbol) | |
9097 | { | |
9098 | char c = *input_line_pointer; | |
9099 | *input_line_pointer = 0; | |
9100 | as_bad (_("invalid PLT expression `%s'"), save); | |
9101 | *input_line_pointer = c; | |
9102 | } | |
f3c180ae AM |
9103 | } |
9104 | } | |
9105 | else | |
9106 | expression (exp); | |
ee86248c JB |
9107 | |
9108 | intel_syntax = -intel_syntax; | |
9109 | ||
9110 | if (intel_syntax) | |
9111 | i386_intel_simplify (exp); | |
62ebcb5c AM |
9112 | |
9113 | return got_reloc; | |
f3c180ae | 9114 | } |
f3c180ae | 9115 | |
9f32dd5b L |
9116 | static void |
9117 | signed_cons (int size) | |
6482c264 | 9118 | { |
d182319b JB |
9119 | if (flag_code == CODE_64BIT) |
9120 | cons_sign = 1; | |
9121 | cons (size); | |
9122 | cons_sign = -1; | |
6482c264 NC |
9123 | } |
9124 | ||
d182319b | 9125 | #ifdef TE_PE |
6482c264 | 9126 | static void |
7016a5d5 | 9127 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
6482c264 NC |
9128 | { |
9129 | expressionS exp; | |
9130 | ||
9131 | do | |
9132 | { | |
9133 | expression (&exp); | |
9134 | if (exp.X_op == O_symbol) | |
9135 | exp.X_op = O_secrel; | |
9136 | ||
9137 | emit_expr (&exp, 4); | |
9138 | } | |
9139 | while (*input_line_pointer++ == ','); | |
9140 | ||
9141 | input_line_pointer--; | |
9142 | demand_empty_rest_of_line (); | |
9143 | } | |
6482c264 NC |
9144 | #endif |
9145 | ||
43234a1e L |
9146 | /* Handle Vector operations. */ |
9147 | ||
9148 | static char * | |
9149 | check_VecOperations (char *op_string, char *op_end) | |
9150 | { | |
9151 | const reg_entry *mask; | |
9152 | const char *saved; | |
9153 | char *end_op; | |
9154 | ||
9155 | while (*op_string | |
9156 | && (op_end == NULL || op_string < op_end)) | |
9157 | { | |
9158 | saved = op_string; | |
9159 | if (*op_string == '{') | |
9160 | { | |
9161 | op_string++; | |
9162 | ||
9163 | /* Check broadcasts. */ | |
9164 | if (strncmp (op_string, "1to", 3) == 0) | |
9165 | { | |
9166 | int bcst_type; | |
9167 | ||
9168 | if (i.broadcast) | |
9169 | goto duplicated_vec_op; | |
9170 | ||
9171 | op_string += 3; | |
9172 | if (*op_string == '8') | |
8e6e0792 | 9173 | bcst_type = 8; |
b28d1bda | 9174 | else if (*op_string == '4') |
8e6e0792 | 9175 | bcst_type = 4; |
b28d1bda | 9176 | else if (*op_string == '2') |
8e6e0792 | 9177 | bcst_type = 2; |
43234a1e L |
9178 | else if (*op_string == '1' |
9179 | && *(op_string+1) == '6') | |
9180 | { | |
8e6e0792 | 9181 | bcst_type = 16; |
43234a1e L |
9182 | op_string++; |
9183 | } | |
9184 | else | |
9185 | { | |
9186 | as_bad (_("Unsupported broadcast: `%s'"), saved); | |
9187 | return NULL; | |
9188 | } | |
9189 | op_string++; | |
9190 | ||
9191 | broadcast_op.type = bcst_type; | |
9192 | broadcast_op.operand = this_operand; | |
1f75763a | 9193 | broadcast_op.bytes = 0; |
43234a1e L |
9194 | i.broadcast = &broadcast_op; |
9195 | } | |
9196 | /* Check masking operation. */ | |
9197 | else if ((mask = parse_register (op_string, &end_op)) != NULL) | |
9198 | { | |
9199 | /* k0 can't be used for write mask. */ | |
f74a6307 | 9200 | if (mask->reg_type.bitfield.class != RegMask || !mask->reg_num) |
43234a1e | 9201 | { |
6d2cd6b2 JB |
9202 | as_bad (_("`%s%s' can't be used for write mask"), |
9203 | register_prefix, mask->reg_name); | |
43234a1e L |
9204 | return NULL; |
9205 | } | |
9206 | ||
9207 | if (!i.mask) | |
9208 | { | |
9209 | mask_op.mask = mask; | |
9210 | mask_op.zeroing = 0; | |
9211 | mask_op.operand = this_operand; | |
9212 | i.mask = &mask_op; | |
9213 | } | |
9214 | else | |
9215 | { | |
9216 | if (i.mask->mask) | |
9217 | goto duplicated_vec_op; | |
9218 | ||
9219 | i.mask->mask = mask; | |
9220 | ||
9221 | /* Only "{z}" is allowed here. No need to check | |
9222 | zeroing mask explicitly. */ | |
9223 | if (i.mask->operand != this_operand) | |
9224 | { | |
9225 | as_bad (_("invalid write mask `%s'"), saved); | |
9226 | return NULL; | |
9227 | } | |
9228 | } | |
9229 | ||
9230 | op_string = end_op; | |
9231 | } | |
9232 | /* Check zeroing-flag for masking operation. */ | |
9233 | else if (*op_string == 'z') | |
9234 | { | |
9235 | if (!i.mask) | |
9236 | { | |
9237 | mask_op.mask = NULL; | |
9238 | mask_op.zeroing = 1; | |
9239 | mask_op.operand = this_operand; | |
9240 | i.mask = &mask_op; | |
9241 | } | |
9242 | else | |
9243 | { | |
9244 | if (i.mask->zeroing) | |
9245 | { | |
9246 | duplicated_vec_op: | |
9247 | as_bad (_("duplicated `%s'"), saved); | |
9248 | return NULL; | |
9249 | } | |
9250 | ||
9251 | i.mask->zeroing = 1; | |
9252 | ||
9253 | /* Only "{%k}" is allowed here. No need to check mask | |
9254 | register explicitly. */ | |
9255 | if (i.mask->operand != this_operand) | |
9256 | { | |
9257 | as_bad (_("invalid zeroing-masking `%s'"), | |
9258 | saved); | |
9259 | return NULL; | |
9260 | } | |
9261 | } | |
9262 | ||
9263 | op_string++; | |
9264 | } | |
9265 | else | |
9266 | goto unknown_vec_op; | |
9267 | ||
9268 | if (*op_string != '}') | |
9269 | { | |
9270 | as_bad (_("missing `}' in `%s'"), saved); | |
9271 | return NULL; | |
9272 | } | |
9273 | op_string++; | |
0ba3a731 L |
9274 | |
9275 | /* Strip whitespace since the addition of pseudo prefixes | |
9276 | changed how the scrubber treats '{'. */ | |
9277 | if (is_space_char (*op_string)) | |
9278 | ++op_string; | |
9279 | ||
43234a1e L |
9280 | continue; |
9281 | } | |
9282 | unknown_vec_op: | |
9283 | /* We don't know this one. */ | |
9284 | as_bad (_("unknown vector operation: `%s'"), saved); | |
9285 | return NULL; | |
9286 | } | |
9287 | ||
6d2cd6b2 JB |
9288 | if (i.mask && i.mask->zeroing && !i.mask->mask) |
9289 | { | |
9290 | as_bad (_("zeroing-masking only allowed with write mask")); | |
9291 | return NULL; | |
9292 | } | |
9293 | ||
43234a1e L |
9294 | return op_string; |
9295 | } | |
9296 | ||
252b5132 | 9297 | static int |
70e41ade | 9298 | i386_immediate (char *imm_start) |
252b5132 RH |
9299 | { |
9300 | char *save_input_line_pointer; | |
f3c180ae | 9301 | char *gotfree_input_line; |
252b5132 | 9302 | segT exp_seg = 0; |
47926f60 | 9303 | expressionS *exp; |
40fb9820 L |
9304 | i386_operand_type types; |
9305 | ||
0dfbf9d7 | 9306 | operand_type_set (&types, ~0); |
252b5132 RH |
9307 | |
9308 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
9309 | { | |
31b2323c L |
9310 | as_bad (_("at most %d immediate operands are allowed"), |
9311 | MAX_IMMEDIATE_OPERANDS); | |
252b5132 RH |
9312 | return 0; |
9313 | } | |
9314 | ||
9315 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 9316 | i.op[this_operand].imms = exp; |
252b5132 RH |
9317 | |
9318 | if (is_space_char (*imm_start)) | |
9319 | ++imm_start; | |
9320 | ||
9321 | save_input_line_pointer = input_line_pointer; | |
9322 | input_line_pointer = imm_start; | |
9323 | ||
d258b828 | 9324 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
9325 | if (gotfree_input_line) |
9326 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
9327 | |
9328 | exp_seg = expression (exp); | |
9329 | ||
83183c0c | 9330 | SKIP_WHITESPACE (); |
43234a1e L |
9331 | |
9332 | /* Handle vector operations. */ | |
9333 | if (*input_line_pointer == '{') | |
9334 | { | |
9335 | input_line_pointer = check_VecOperations (input_line_pointer, | |
9336 | NULL); | |
9337 | if (input_line_pointer == NULL) | |
9338 | return 0; | |
9339 | } | |
9340 | ||
252b5132 | 9341 | if (*input_line_pointer) |
f3c180ae | 9342 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
9343 | |
9344 | input_line_pointer = save_input_line_pointer; | |
f3c180ae | 9345 | if (gotfree_input_line) |
ee86248c JB |
9346 | { |
9347 | free (gotfree_input_line); | |
9348 | ||
9349 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
9350 | exp->X_op = O_illegal; | |
9351 | } | |
9352 | ||
9353 | return i386_finalize_immediate (exp_seg, exp, types, imm_start); | |
9354 | } | |
252b5132 | 9355 | |
ee86248c JB |
9356 | static int |
9357 | i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
9358 | i386_operand_type types, const char *imm_start) | |
9359 | { | |
9360 | if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big) | |
252b5132 | 9361 | { |
313c53d1 L |
9362 | if (imm_start) |
9363 | as_bad (_("missing or invalid immediate expression `%s'"), | |
9364 | imm_start); | |
3992d3b7 | 9365 | return 0; |
252b5132 | 9366 | } |
3e73aa7c | 9367 | else if (exp->X_op == O_constant) |
252b5132 | 9368 | { |
47926f60 | 9369 | /* Size it properly later. */ |
40fb9820 | 9370 | i.types[this_operand].bitfield.imm64 = 1; |
13f864ae L |
9371 | /* If not 64bit, sign extend val. */ |
9372 | if (flag_code != CODE_64BIT | |
4eed87de AM |
9373 | && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) |
9374 | exp->X_add_number | |
9375 | = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
252b5132 | 9376 | } |
4c63da97 | 9377 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
f86103b7 | 9378 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 9379 | && exp_seg != absolute_section |
47926f60 | 9380 | && exp_seg != text_section |
24eab124 AM |
9381 | && exp_seg != data_section |
9382 | && exp_seg != bss_section | |
9383 | && exp_seg != undefined_section | |
f86103b7 | 9384 | && !bfd_is_com_section (exp_seg)) |
252b5132 | 9385 | { |
d0b47220 | 9386 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
252b5132 RH |
9387 | return 0; |
9388 | } | |
9389 | #endif | |
a841bdf5 | 9390 | else if (!intel_syntax && exp_seg == reg_section) |
bb8f5920 | 9391 | { |
313c53d1 L |
9392 | if (imm_start) |
9393 | as_bad (_("illegal immediate register operand %s"), imm_start); | |
bb8f5920 L |
9394 | return 0; |
9395 | } | |
252b5132 RH |
9396 | else |
9397 | { | |
9398 | /* This is an address. The size of the address will be | |
24eab124 | 9399 | determined later, depending on destination register, |
3e73aa7c | 9400 | suffix, or the default for the section. */ |
40fb9820 L |
9401 | i.types[this_operand].bitfield.imm8 = 1; |
9402 | i.types[this_operand].bitfield.imm16 = 1; | |
9403 | i.types[this_operand].bitfield.imm32 = 1; | |
9404 | i.types[this_operand].bitfield.imm32s = 1; | |
9405 | i.types[this_operand].bitfield.imm64 = 1; | |
c6fb90c8 L |
9406 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
9407 | types); | |
252b5132 RH |
9408 | } |
9409 | ||
9410 | return 1; | |
9411 | } | |
9412 | ||
551c1ca1 | 9413 | static char * |
e3bb37b5 | 9414 | i386_scale (char *scale) |
252b5132 | 9415 | { |
551c1ca1 AM |
9416 | offsetT val; |
9417 | char *save = input_line_pointer; | |
252b5132 | 9418 | |
551c1ca1 AM |
9419 | input_line_pointer = scale; |
9420 | val = get_absolute_expression (); | |
9421 | ||
9422 | switch (val) | |
252b5132 | 9423 | { |
551c1ca1 | 9424 | case 1: |
252b5132 RH |
9425 | i.log2_scale_factor = 0; |
9426 | break; | |
551c1ca1 | 9427 | case 2: |
252b5132 RH |
9428 | i.log2_scale_factor = 1; |
9429 | break; | |
551c1ca1 | 9430 | case 4: |
252b5132 RH |
9431 | i.log2_scale_factor = 2; |
9432 | break; | |
551c1ca1 | 9433 | case 8: |
252b5132 RH |
9434 | i.log2_scale_factor = 3; |
9435 | break; | |
9436 | default: | |
a724f0f4 JB |
9437 | { |
9438 | char sep = *input_line_pointer; | |
9439 | ||
9440 | *input_line_pointer = '\0'; | |
9441 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
9442 | scale); | |
9443 | *input_line_pointer = sep; | |
9444 | input_line_pointer = save; | |
9445 | return NULL; | |
9446 | } | |
252b5132 | 9447 | } |
29b0f896 | 9448 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
252b5132 RH |
9449 | { |
9450 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 9451 | 1 << i.log2_scale_factor); |
252b5132 | 9452 | i.log2_scale_factor = 0; |
252b5132 | 9453 | } |
551c1ca1 AM |
9454 | scale = input_line_pointer; |
9455 | input_line_pointer = save; | |
9456 | return scale; | |
252b5132 RH |
9457 | } |
9458 | ||
252b5132 | 9459 | static int |
e3bb37b5 | 9460 | i386_displacement (char *disp_start, char *disp_end) |
252b5132 | 9461 | { |
29b0f896 | 9462 | expressionS *exp; |
252b5132 RH |
9463 | segT exp_seg = 0; |
9464 | char *save_input_line_pointer; | |
f3c180ae | 9465 | char *gotfree_input_line; |
40fb9820 L |
9466 | int override; |
9467 | i386_operand_type bigdisp, types = anydisp; | |
3992d3b7 | 9468 | int ret; |
252b5132 | 9469 | |
31b2323c L |
9470 | if (i.disp_operands == MAX_MEMORY_OPERANDS) |
9471 | { | |
9472 | as_bad (_("at most %d displacement operands are allowed"), | |
9473 | MAX_MEMORY_OPERANDS); | |
9474 | return 0; | |
9475 | } | |
9476 | ||
0dfbf9d7 | 9477 | operand_type_set (&bigdisp, 0); |
40fb9820 L |
9478 | if ((i.types[this_operand].bitfield.jumpabsolute) |
9479 | || (!current_templates->start->opcode_modifier.jump | |
9480 | && !current_templates->start->opcode_modifier.jumpdword)) | |
e05278af | 9481 | { |
40fb9820 | 9482 | bigdisp.bitfield.disp32 = 1; |
e05278af | 9483 | override = (i.prefix[ADDR_PREFIX] != 0); |
40fb9820 L |
9484 | if (flag_code == CODE_64BIT) |
9485 | { | |
9486 | if (!override) | |
9487 | { | |
9488 | bigdisp.bitfield.disp32s = 1; | |
9489 | bigdisp.bitfield.disp64 = 1; | |
9490 | } | |
9491 | } | |
9492 | else if ((flag_code == CODE_16BIT) ^ override) | |
9493 | { | |
9494 | bigdisp.bitfield.disp32 = 0; | |
9495 | bigdisp.bitfield.disp16 = 1; | |
9496 | } | |
e05278af JB |
9497 | } |
9498 | else | |
9499 | { | |
9500 | /* For PC-relative branches, the width of the displacement | |
9501 | is dependent upon data size, not address size. */ | |
e05278af | 9502 | override = (i.prefix[DATA_PREFIX] != 0); |
40fb9820 L |
9503 | if (flag_code == CODE_64BIT) |
9504 | { | |
9505 | if (override || i.suffix == WORD_MNEM_SUFFIX) | |
9506 | bigdisp.bitfield.disp16 = 1; | |
9507 | else | |
9508 | { | |
9509 | bigdisp.bitfield.disp32 = 1; | |
9510 | bigdisp.bitfield.disp32s = 1; | |
9511 | } | |
9512 | } | |
9513 | else | |
e05278af JB |
9514 | { |
9515 | if (!override) | |
9516 | override = (i.suffix == (flag_code != CODE_16BIT | |
9517 | ? WORD_MNEM_SUFFIX | |
9518 | : LONG_MNEM_SUFFIX)); | |
40fb9820 L |
9519 | bigdisp.bitfield.disp32 = 1; |
9520 | if ((flag_code == CODE_16BIT) ^ override) | |
9521 | { | |
9522 | bigdisp.bitfield.disp32 = 0; | |
9523 | bigdisp.bitfield.disp16 = 1; | |
9524 | } | |
e05278af | 9525 | } |
e05278af | 9526 | } |
c6fb90c8 L |
9527 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
9528 | bigdisp); | |
252b5132 RH |
9529 | |
9530 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 9531 | i.op[this_operand].disps = exp; |
252b5132 RH |
9532 | i.disp_operands++; |
9533 | save_input_line_pointer = input_line_pointer; | |
9534 | input_line_pointer = disp_start; | |
9535 | END_STRING_AND_SAVE (disp_end); | |
9536 | ||
9537 | #ifndef GCC_ASM_O_HACK | |
9538 | #define GCC_ASM_O_HACK 0 | |
9539 | #endif | |
9540 | #if GCC_ASM_O_HACK | |
9541 | END_STRING_AND_SAVE (disp_end + 1); | |
40fb9820 | 9542 | if (i.types[this_operand].bitfield.baseIndex |
24eab124 | 9543 | && displacement_string_end[-1] == '+') |
252b5132 RH |
9544 | { |
9545 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
9546 | constraint within gcc asm statements. |
9547 | For instance: | |
9548 | ||
9549 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
9550 | __asm__ __volatile__ ( \ | |
9551 | "movw %w2,%0\n\t" \ | |
9552 | "movw %w1,2+%0\n\t" \ | |
9553 | "rorl $16,%1\n\t" \ | |
9554 | "movb %b1,4+%0\n\t" \ | |
9555 | "movb %4,5+%0\n\t" \ | |
9556 | "movb $0,6+%0\n\t" \ | |
9557 | "movb %h1,7+%0\n\t" \ | |
9558 | "rorl $16,%1" \ | |
9559 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
9560 | ||
9561 | This works great except that the output assembler ends | |
9562 | up looking a bit weird if it turns out that there is | |
9563 | no offset. You end up producing code that looks like: | |
9564 | ||
9565 | #APP | |
9566 | movw $235,(%eax) | |
9567 | movw %dx,2+(%eax) | |
9568 | rorl $16,%edx | |
9569 | movb %dl,4+(%eax) | |
9570 | movb $137,5+(%eax) | |
9571 | movb $0,6+(%eax) | |
9572 | movb %dh,7+(%eax) | |
9573 | rorl $16,%edx | |
9574 | #NO_APP | |
9575 | ||
47926f60 | 9576 | So here we provide the missing zero. */ |
24eab124 AM |
9577 | |
9578 | *displacement_string_end = '0'; | |
252b5132 RH |
9579 | } |
9580 | #endif | |
d258b828 | 9581 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
9582 | if (gotfree_input_line) |
9583 | input_line_pointer = gotfree_input_line; | |
252b5132 | 9584 | |
24eab124 | 9585 | exp_seg = expression (exp); |
252b5132 | 9586 | |
636c26b0 AM |
9587 | SKIP_WHITESPACE (); |
9588 | if (*input_line_pointer) | |
9589 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
9590 | #if GCC_ASM_O_HACK | |
9591 | RESTORE_END_STRING (disp_end + 1); | |
9592 | #endif | |
636c26b0 | 9593 | input_line_pointer = save_input_line_pointer; |
636c26b0 | 9594 | if (gotfree_input_line) |
ee86248c JB |
9595 | { |
9596 | free (gotfree_input_line); | |
9597 | ||
9598 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
9599 | exp->X_op = O_illegal; | |
9600 | } | |
9601 | ||
9602 | ret = i386_finalize_displacement (exp_seg, exp, types, disp_start); | |
9603 | ||
9604 | RESTORE_END_STRING (disp_end); | |
9605 | ||
9606 | return ret; | |
9607 | } | |
9608 | ||
9609 | static int | |
9610 | i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
9611 | i386_operand_type types, const char *disp_start) | |
9612 | { | |
9613 | i386_operand_type bigdisp; | |
9614 | int ret = 1; | |
636c26b0 | 9615 | |
24eab124 AM |
9616 | /* We do this to make sure that the section symbol is in |
9617 | the symbol table. We will ultimately change the relocation | |
47926f60 | 9618 | to be relative to the beginning of the section. */ |
1ae12ab7 | 9619 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
d6ab8113 JB |
9620 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
9621 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) | |
24eab124 | 9622 | { |
636c26b0 | 9623 | if (exp->X_op != O_symbol) |
3992d3b7 | 9624 | goto inv_disp; |
636c26b0 | 9625 | |
e5cb08ac | 9626 | if (S_IS_LOCAL (exp->X_add_symbol) |
c64efb4b L |
9627 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section |
9628 | && S_GET_SEGMENT (exp->X_add_symbol) != expr_section) | |
24eab124 | 9629 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); |
24eab124 AM |
9630 | exp->X_op = O_subtract; |
9631 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 | 9632 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
29b0f896 | 9633 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
d6ab8113 JB |
9634 | else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
9635 | i.reloc[this_operand] = BFD_RELOC_64; | |
23df1078 | 9636 | else |
29b0f896 | 9637 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 9638 | } |
252b5132 | 9639 | |
3992d3b7 AM |
9640 | else if (exp->X_op == O_absent |
9641 | || exp->X_op == O_illegal | |
ee86248c | 9642 | || exp->X_op == O_big) |
2daf4fd8 | 9643 | { |
3992d3b7 AM |
9644 | inv_disp: |
9645 | as_bad (_("missing or invalid displacement expression `%s'"), | |
2daf4fd8 | 9646 | disp_start); |
3992d3b7 | 9647 | ret = 0; |
2daf4fd8 AM |
9648 | } |
9649 | ||
0e1147d9 L |
9650 | else if (flag_code == CODE_64BIT |
9651 | && !i.prefix[ADDR_PREFIX] | |
9652 | && exp->X_op == O_constant) | |
9653 | { | |
9654 | /* Since displacement is signed extended to 64bit, don't allow | |
9655 | disp32 and turn off disp32s if they are out of range. */ | |
9656 | i.types[this_operand].bitfield.disp32 = 0; | |
9657 | if (!fits_in_signed_long (exp->X_add_number)) | |
9658 | { | |
9659 | i.types[this_operand].bitfield.disp32s = 0; | |
9660 | if (i.types[this_operand].bitfield.baseindex) | |
9661 | { | |
9662 | as_bad (_("0x%lx out range of signed 32bit displacement"), | |
9663 | (long) exp->X_add_number); | |
9664 | ret = 0; | |
9665 | } | |
9666 | } | |
9667 | } | |
9668 | ||
4c63da97 | 9669 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
3992d3b7 AM |
9670 | else if (exp->X_op != O_constant |
9671 | && OUTPUT_FLAVOR == bfd_target_aout_flavour | |
9672 | && exp_seg != absolute_section | |
9673 | && exp_seg != text_section | |
9674 | && exp_seg != data_section | |
9675 | && exp_seg != bss_section | |
9676 | && exp_seg != undefined_section | |
9677 | && !bfd_is_com_section (exp_seg)) | |
24eab124 | 9678 | { |
d0b47220 | 9679 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
3992d3b7 | 9680 | ret = 0; |
24eab124 | 9681 | } |
252b5132 | 9682 | #endif |
3956db08 | 9683 | |
40fb9820 L |
9684 | /* Check if this is a displacement only operand. */ |
9685 | bigdisp = i.types[this_operand]; | |
9686 | bigdisp.bitfield.disp8 = 0; | |
9687 | bigdisp.bitfield.disp16 = 0; | |
9688 | bigdisp.bitfield.disp32 = 0; | |
9689 | bigdisp.bitfield.disp32s = 0; | |
9690 | bigdisp.bitfield.disp64 = 0; | |
0dfbf9d7 | 9691 | if (operand_type_all_zero (&bigdisp)) |
c6fb90c8 L |
9692 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
9693 | types); | |
3956db08 | 9694 | |
3992d3b7 | 9695 | return ret; |
252b5132 RH |
9696 | } |
9697 | ||
2abc2bec JB |
9698 | /* Return the active addressing mode, taking address override and |
9699 | registers forming the address into consideration. Update the | |
9700 | address override prefix if necessary. */ | |
47926f60 | 9701 | |
2abc2bec JB |
9702 | static enum flag_code |
9703 | i386_addressing_mode (void) | |
252b5132 | 9704 | { |
be05d201 L |
9705 | enum flag_code addr_mode; |
9706 | ||
9707 | if (i.prefix[ADDR_PREFIX]) | |
9708 | addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT; | |
9709 | else | |
9710 | { | |
9711 | addr_mode = flag_code; | |
9712 | ||
24eab124 | 9713 | #if INFER_ADDR_PREFIX |
be05d201 L |
9714 | if (i.mem_operands == 0) |
9715 | { | |
9716 | /* Infer address prefix from the first memory operand. */ | |
9717 | const reg_entry *addr_reg = i.base_reg; | |
9718 | ||
9719 | if (addr_reg == NULL) | |
9720 | addr_reg = i.index_reg; | |
eecb386c | 9721 | |
be05d201 L |
9722 | if (addr_reg) |
9723 | { | |
e968fc9b | 9724 | if (addr_reg->reg_type.bitfield.dword) |
be05d201 L |
9725 | addr_mode = CODE_32BIT; |
9726 | else if (flag_code != CODE_64BIT | |
dc821c5f | 9727 | && addr_reg->reg_type.bitfield.word) |
be05d201 L |
9728 | addr_mode = CODE_16BIT; |
9729 | ||
9730 | if (addr_mode != flag_code) | |
9731 | { | |
9732 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
9733 | i.prefixes += 1; | |
9734 | /* Change the size of any displacement too. At most one | |
9735 | of Disp16 or Disp32 is set. | |
9736 | FIXME. There doesn't seem to be any real need for | |
9737 | separate Disp16 and Disp32 flags. The same goes for | |
9738 | Imm16 and Imm32. Removing them would probably clean | |
9739 | up the code quite a lot. */ | |
9740 | if (flag_code != CODE_64BIT | |
9741 | && (i.types[this_operand].bitfield.disp16 | |
9742 | || i.types[this_operand].bitfield.disp32)) | |
9743 | i.types[this_operand] | |
9744 | = operand_type_xor (i.types[this_operand], disp16_32); | |
9745 | } | |
9746 | } | |
9747 | } | |
24eab124 | 9748 | #endif |
be05d201 L |
9749 | } |
9750 | ||
2abc2bec JB |
9751 | return addr_mode; |
9752 | } | |
9753 | ||
9754 | /* Make sure the memory operand we've been dealt is valid. | |
9755 | Return 1 on success, 0 on a failure. */ | |
9756 | ||
9757 | static int | |
9758 | i386_index_check (const char *operand_string) | |
9759 | { | |
9760 | const char *kind = "base/index"; | |
9761 | enum flag_code addr_mode = i386_addressing_mode (); | |
9762 | ||
fc0763e6 | 9763 | if (current_templates->start->opcode_modifier.isstring |
c3949f43 | 9764 | && !current_templates->start->cpu_flags.bitfield.cpupadlock |
fc0763e6 JB |
9765 | && (current_templates->end[-1].opcode_modifier.isstring |
9766 | || i.mem_operands)) | |
9767 | { | |
9768 | /* Memory operands of string insns are special in that they only allow | |
9769 | a single register (rDI, rSI, or rBX) as their memory address. */ | |
be05d201 L |
9770 | const reg_entry *expected_reg; |
9771 | static const char *di_si[][2] = | |
9772 | { | |
9773 | { "esi", "edi" }, | |
9774 | { "si", "di" }, | |
9775 | { "rsi", "rdi" } | |
9776 | }; | |
9777 | static const char *bx[] = { "ebx", "bx", "rbx" }; | |
fc0763e6 JB |
9778 | |
9779 | kind = "string address"; | |
9780 | ||
8325cc63 | 9781 | if (current_templates->start->opcode_modifier.repprefixok) |
fc0763e6 JB |
9782 | { |
9783 | i386_operand_type type = current_templates->end[-1].operand_types[0]; | |
9784 | ||
9785 | if (!type.bitfield.baseindex | |
9786 | || ((!i.mem_operands != !intel_syntax) | |
9787 | && current_templates->end[-1].operand_types[1] | |
9788 | .bitfield.baseindex)) | |
9789 | type = current_templates->end[-1].operand_types[1]; | |
be05d201 L |
9790 | expected_reg = hash_find (reg_hash, |
9791 | di_si[addr_mode][type.bitfield.esseg]); | |
9792 | ||
fc0763e6 JB |
9793 | } |
9794 | else | |
be05d201 | 9795 | expected_reg = hash_find (reg_hash, bx[addr_mode]); |
fc0763e6 | 9796 | |
be05d201 L |
9797 | if (i.base_reg != expected_reg |
9798 | || i.index_reg | |
fc0763e6 | 9799 | || operand_type_check (i.types[this_operand], disp)) |
fc0763e6 | 9800 | { |
be05d201 L |
9801 | /* The second memory operand must have the same size as |
9802 | the first one. */ | |
9803 | if (i.mem_operands | |
9804 | && i.base_reg | |
9805 | && !((addr_mode == CODE_64BIT | |
dc821c5f | 9806 | && i.base_reg->reg_type.bitfield.qword) |
be05d201 | 9807 | || (addr_mode == CODE_32BIT |
dc821c5f JB |
9808 | ? i.base_reg->reg_type.bitfield.dword |
9809 | : i.base_reg->reg_type.bitfield.word))) | |
be05d201 L |
9810 | goto bad_address; |
9811 | ||
fc0763e6 JB |
9812 | as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"), |
9813 | operand_string, | |
9814 | intel_syntax ? '[' : '(', | |
9815 | register_prefix, | |
be05d201 | 9816 | expected_reg->reg_name, |
fc0763e6 | 9817 | intel_syntax ? ']' : ')'); |
be05d201 | 9818 | return 1; |
fc0763e6 | 9819 | } |
be05d201 L |
9820 | else |
9821 | return 1; | |
9822 | ||
9823 | bad_address: | |
9824 | as_bad (_("`%s' is not a valid %s expression"), | |
9825 | operand_string, kind); | |
9826 | return 0; | |
3e73aa7c JH |
9827 | } |
9828 | else | |
9829 | { | |
be05d201 L |
9830 | if (addr_mode != CODE_16BIT) |
9831 | { | |
9832 | /* 32-bit/64-bit checks. */ | |
9833 | if ((i.base_reg | |
e968fc9b JB |
9834 | && ((addr_mode == CODE_64BIT |
9835 | ? !i.base_reg->reg_type.bitfield.qword | |
9836 | : !i.base_reg->reg_type.bitfield.dword) | |
9837 | || (i.index_reg && i.base_reg->reg_num == RegIP) | |
9838 | || i.base_reg->reg_num == RegIZ)) | |
be05d201 | 9839 | || (i.index_reg |
1b54b8d7 JB |
9840 | && !i.index_reg->reg_type.bitfield.xmmword |
9841 | && !i.index_reg->reg_type.bitfield.ymmword | |
9842 | && !i.index_reg->reg_type.bitfield.zmmword | |
be05d201 | 9843 | && ((addr_mode == CODE_64BIT |
e968fc9b JB |
9844 | ? !i.index_reg->reg_type.bitfield.qword |
9845 | : !i.index_reg->reg_type.bitfield.dword) | |
be05d201 L |
9846 | || !i.index_reg->reg_type.bitfield.baseindex))) |
9847 | goto bad_address; | |
8178be5b JB |
9848 | |
9849 | /* bndmk, bndldx, and bndstx have special restrictions. */ | |
9850 | if (current_templates->start->base_opcode == 0xf30f1b | |
9851 | || (current_templates->start->base_opcode & ~1) == 0x0f1a) | |
9852 | { | |
9853 | /* They cannot use RIP-relative addressing. */ | |
e968fc9b | 9854 | if (i.base_reg && i.base_reg->reg_num == RegIP) |
8178be5b JB |
9855 | { |
9856 | as_bad (_("`%s' cannot be used here"), operand_string); | |
9857 | return 0; | |
9858 | } | |
9859 | ||
9860 | /* bndldx and bndstx ignore their scale factor. */ | |
9861 | if (current_templates->start->base_opcode != 0xf30f1b | |
9862 | && i.log2_scale_factor) | |
9863 | as_warn (_("register scaling is being ignored here")); | |
9864 | } | |
be05d201 L |
9865 | } |
9866 | else | |
3e73aa7c | 9867 | { |
be05d201 | 9868 | /* 16-bit checks. */ |
3e73aa7c | 9869 | if ((i.base_reg |
dc821c5f | 9870 | && (!i.base_reg->reg_type.bitfield.word |
40fb9820 | 9871 | || !i.base_reg->reg_type.bitfield.baseindex)) |
3e73aa7c | 9872 | || (i.index_reg |
dc821c5f | 9873 | && (!i.index_reg->reg_type.bitfield.word |
40fb9820 | 9874 | || !i.index_reg->reg_type.bitfield.baseindex |
29b0f896 AM |
9875 | || !(i.base_reg |
9876 | && i.base_reg->reg_num < 6 | |
9877 | && i.index_reg->reg_num >= 6 | |
9878 | && i.log2_scale_factor == 0)))) | |
be05d201 | 9879 | goto bad_address; |
3e73aa7c JH |
9880 | } |
9881 | } | |
be05d201 | 9882 | return 1; |
24eab124 | 9883 | } |
252b5132 | 9884 | |
43234a1e L |
9885 | /* Handle vector immediates. */ |
9886 | ||
9887 | static int | |
9888 | RC_SAE_immediate (const char *imm_start) | |
9889 | { | |
9890 | unsigned int match_found, j; | |
9891 | const char *pstr = imm_start; | |
9892 | expressionS *exp; | |
9893 | ||
9894 | if (*pstr != '{') | |
9895 | return 0; | |
9896 | ||
9897 | pstr++; | |
9898 | match_found = 0; | |
9899 | for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++) | |
9900 | { | |
9901 | if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len)) | |
9902 | { | |
9903 | if (!i.rounding) | |
9904 | { | |
9905 | rc_op.type = RC_NamesTable[j].type; | |
9906 | rc_op.operand = this_operand; | |
9907 | i.rounding = &rc_op; | |
9908 | } | |
9909 | else | |
9910 | { | |
9911 | as_bad (_("duplicated `%s'"), imm_start); | |
9912 | return 0; | |
9913 | } | |
9914 | pstr += RC_NamesTable[j].len; | |
9915 | match_found = 1; | |
9916 | break; | |
9917 | } | |
9918 | } | |
9919 | if (!match_found) | |
9920 | return 0; | |
9921 | ||
9922 | if (*pstr++ != '}') | |
9923 | { | |
9924 | as_bad (_("Missing '}': '%s'"), imm_start); | |
9925 | return 0; | |
9926 | } | |
9927 | /* RC/SAE immediate string should contain nothing more. */; | |
9928 | if (*pstr != 0) | |
9929 | { | |
9930 | as_bad (_("Junk after '}': '%s'"), imm_start); | |
9931 | return 0; | |
9932 | } | |
9933 | ||
9934 | exp = &im_expressions[i.imm_operands++]; | |
9935 | i.op[this_operand].imms = exp; | |
9936 | ||
9937 | exp->X_op = O_constant; | |
9938 | exp->X_add_number = 0; | |
9939 | exp->X_add_symbol = (symbolS *) 0; | |
9940 | exp->X_op_symbol = (symbolS *) 0; | |
9941 | ||
9942 | i.types[this_operand].bitfield.imm8 = 1; | |
9943 | return 1; | |
9944 | } | |
9945 | ||
8325cc63 JB |
9946 | /* Only string instructions can have a second memory operand, so |
9947 | reduce current_templates to just those if it contains any. */ | |
9948 | static int | |
9949 | maybe_adjust_templates (void) | |
9950 | { | |
9951 | const insn_template *t; | |
9952 | ||
9953 | gas_assert (i.mem_operands == 1); | |
9954 | ||
9955 | for (t = current_templates->start; t < current_templates->end; ++t) | |
9956 | if (t->opcode_modifier.isstring) | |
9957 | break; | |
9958 | ||
9959 | if (t < current_templates->end) | |
9960 | { | |
9961 | static templates aux_templates; | |
9962 | bfd_boolean recheck; | |
9963 | ||
9964 | aux_templates.start = t; | |
9965 | for (; t < current_templates->end; ++t) | |
9966 | if (!t->opcode_modifier.isstring) | |
9967 | break; | |
9968 | aux_templates.end = t; | |
9969 | ||
9970 | /* Determine whether to re-check the first memory operand. */ | |
9971 | recheck = (aux_templates.start != current_templates->start | |
9972 | || t != current_templates->end); | |
9973 | ||
9974 | current_templates = &aux_templates; | |
9975 | ||
9976 | if (recheck) | |
9977 | { | |
9978 | i.mem_operands = 0; | |
9979 | if (i.memop1_string != NULL | |
9980 | && i386_index_check (i.memop1_string) == 0) | |
9981 | return 0; | |
9982 | i.mem_operands = 1; | |
9983 | } | |
9984 | } | |
9985 | ||
9986 | return 1; | |
9987 | } | |
9988 | ||
fc0763e6 | 9989 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero |
47926f60 | 9990 | on error. */ |
252b5132 | 9991 | |
252b5132 | 9992 | static int |
a7619375 | 9993 | i386_att_operand (char *operand_string) |
252b5132 | 9994 | { |
af6bdddf AM |
9995 | const reg_entry *r; |
9996 | char *end_op; | |
24eab124 | 9997 | char *op_string = operand_string; |
252b5132 | 9998 | |
24eab124 | 9999 | if (is_space_char (*op_string)) |
252b5132 RH |
10000 | ++op_string; |
10001 | ||
24eab124 | 10002 | /* We check for an absolute prefix (differentiating, |
47926f60 | 10003 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
10004 | if (*op_string == ABSOLUTE_PREFIX) |
10005 | { | |
10006 | ++op_string; | |
10007 | if (is_space_char (*op_string)) | |
10008 | ++op_string; | |
40fb9820 | 10009 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 | 10010 | } |
252b5132 | 10011 | |
47926f60 | 10012 | /* Check if operand is a register. */ |
4d1bb795 | 10013 | if ((r = parse_register (op_string, &end_op)) != NULL) |
24eab124 | 10014 | { |
40fb9820 L |
10015 | i386_operand_type temp; |
10016 | ||
24eab124 AM |
10017 | /* Check for a segment override by searching for ':' after a |
10018 | segment register. */ | |
10019 | op_string = end_op; | |
10020 | if (is_space_char (*op_string)) | |
10021 | ++op_string; | |
00cee14f | 10022 | if (*op_string == ':' && r->reg_type.bitfield.class == SReg) |
24eab124 AM |
10023 | { |
10024 | switch (r->reg_num) | |
10025 | { | |
10026 | case 0: | |
10027 | i.seg[i.mem_operands] = &es; | |
10028 | break; | |
10029 | case 1: | |
10030 | i.seg[i.mem_operands] = &cs; | |
10031 | break; | |
10032 | case 2: | |
10033 | i.seg[i.mem_operands] = &ss; | |
10034 | break; | |
10035 | case 3: | |
10036 | i.seg[i.mem_operands] = &ds; | |
10037 | break; | |
10038 | case 4: | |
10039 | i.seg[i.mem_operands] = &fs; | |
10040 | break; | |
10041 | case 5: | |
10042 | i.seg[i.mem_operands] = &gs; | |
10043 | break; | |
10044 | } | |
252b5132 | 10045 | |
24eab124 | 10046 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
10047 | ++op_string; |
10048 | if (is_space_char (*op_string)) | |
24eab124 | 10049 | ++op_string; |
252b5132 | 10050 | |
24eab124 AM |
10051 | if (!is_digit_char (*op_string) |
10052 | && !is_identifier_char (*op_string) | |
10053 | && *op_string != '(' | |
10054 | && *op_string != ABSOLUTE_PREFIX) | |
10055 | { | |
10056 | as_bad (_("bad memory operand `%s'"), op_string); | |
10057 | return 0; | |
10058 | } | |
47926f60 | 10059 | /* Handle case of %es:*foo. */ |
24eab124 AM |
10060 | if (*op_string == ABSOLUTE_PREFIX) |
10061 | { | |
10062 | ++op_string; | |
10063 | if (is_space_char (*op_string)) | |
10064 | ++op_string; | |
40fb9820 | 10065 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 AM |
10066 | } |
10067 | goto do_memory_reference; | |
10068 | } | |
43234a1e L |
10069 | |
10070 | /* Handle vector operations. */ | |
10071 | if (*op_string == '{') | |
10072 | { | |
10073 | op_string = check_VecOperations (op_string, NULL); | |
10074 | if (op_string == NULL) | |
10075 | return 0; | |
10076 | } | |
10077 | ||
24eab124 AM |
10078 | if (*op_string) |
10079 | { | |
d0b47220 | 10080 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
10081 | return 0; |
10082 | } | |
40fb9820 L |
10083 | temp = r->reg_type; |
10084 | temp.bitfield.baseindex = 0; | |
c6fb90c8 L |
10085 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
10086 | temp); | |
7d5e4556 | 10087 | i.types[this_operand].bitfield.unspecified = 0; |
520dc8e8 | 10088 | i.op[this_operand].regs = r; |
24eab124 AM |
10089 | i.reg_operands++; |
10090 | } | |
af6bdddf AM |
10091 | else if (*op_string == REGISTER_PREFIX) |
10092 | { | |
10093 | as_bad (_("bad register name `%s'"), op_string); | |
10094 | return 0; | |
10095 | } | |
24eab124 | 10096 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 10097 | { |
24eab124 | 10098 | ++op_string; |
40fb9820 | 10099 | if (i.types[this_operand].bitfield.jumpabsolute) |
24eab124 | 10100 | { |
d0b47220 | 10101 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
10102 | return 0; |
10103 | } | |
10104 | if (!i386_immediate (op_string)) | |
10105 | return 0; | |
10106 | } | |
43234a1e L |
10107 | else if (RC_SAE_immediate (operand_string)) |
10108 | { | |
10109 | /* If it is a RC or SAE immediate, do nothing. */ | |
10110 | ; | |
10111 | } | |
24eab124 AM |
10112 | else if (is_digit_char (*op_string) |
10113 | || is_identifier_char (*op_string) | |
d02603dc | 10114 | || *op_string == '"' |
e5cb08ac | 10115 | || *op_string == '(') |
24eab124 | 10116 | { |
47926f60 | 10117 | /* This is a memory reference of some sort. */ |
af6bdddf | 10118 | char *base_string; |
252b5132 | 10119 | |
47926f60 | 10120 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
10121 | char *displacement_string_start; |
10122 | char *displacement_string_end; | |
43234a1e | 10123 | char *vop_start; |
252b5132 | 10124 | |
24eab124 | 10125 | do_memory_reference: |
8325cc63 JB |
10126 | if (i.mem_operands == 1 && !maybe_adjust_templates ()) |
10127 | return 0; | |
24eab124 | 10128 | if ((i.mem_operands == 1 |
40fb9820 | 10129 | && !current_templates->start->opcode_modifier.isstring) |
24eab124 AM |
10130 | || i.mem_operands == 2) |
10131 | { | |
10132 | as_bad (_("too many memory references for `%s'"), | |
10133 | current_templates->start->name); | |
10134 | return 0; | |
10135 | } | |
252b5132 | 10136 | |
24eab124 AM |
10137 | /* Check for base index form. We detect the base index form by |
10138 | looking for an ')' at the end of the operand, searching | |
10139 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
10140 | after the '('. */ | |
af6bdddf | 10141 | base_string = op_string + strlen (op_string); |
c3332e24 | 10142 | |
43234a1e L |
10143 | /* Handle vector operations. */ |
10144 | vop_start = strchr (op_string, '{'); | |
10145 | if (vop_start && vop_start < base_string) | |
10146 | { | |
10147 | if (check_VecOperations (vop_start, base_string) == NULL) | |
10148 | return 0; | |
10149 | base_string = vop_start; | |
10150 | } | |
10151 | ||
af6bdddf AM |
10152 | --base_string; |
10153 | if (is_space_char (*base_string)) | |
10154 | --base_string; | |
252b5132 | 10155 | |
47926f60 | 10156 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
10157 | displacement_string_start = op_string; |
10158 | displacement_string_end = base_string + 1; | |
252b5132 | 10159 | |
24eab124 AM |
10160 | if (*base_string == ')') |
10161 | { | |
af6bdddf | 10162 | char *temp_string; |
24eab124 AM |
10163 | unsigned int parens_balanced = 1; |
10164 | /* We've already checked that the number of left & right ()'s are | |
47926f60 | 10165 | equal, so this loop will not be infinite. */ |
24eab124 AM |
10166 | do |
10167 | { | |
10168 | base_string--; | |
10169 | if (*base_string == ')') | |
10170 | parens_balanced++; | |
10171 | if (*base_string == '(') | |
10172 | parens_balanced--; | |
10173 | } | |
10174 | while (parens_balanced); | |
c3332e24 | 10175 | |
af6bdddf | 10176 | temp_string = base_string; |
c3332e24 | 10177 | |
24eab124 | 10178 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
10179 | ++base_string; |
10180 | if (is_space_char (*base_string)) | |
24eab124 | 10181 | ++base_string; |
252b5132 | 10182 | |
af6bdddf | 10183 | if (*base_string == ',' |
4eed87de AM |
10184 | || ((i.base_reg = parse_register (base_string, &end_op)) |
10185 | != NULL)) | |
252b5132 | 10186 | { |
af6bdddf | 10187 | displacement_string_end = temp_string; |
252b5132 | 10188 | |
40fb9820 | 10189 | i.types[this_operand].bitfield.baseindex = 1; |
252b5132 | 10190 | |
af6bdddf | 10191 | if (i.base_reg) |
24eab124 | 10192 | { |
24eab124 AM |
10193 | base_string = end_op; |
10194 | if (is_space_char (*base_string)) | |
10195 | ++base_string; | |
af6bdddf AM |
10196 | } |
10197 | ||
10198 | /* There may be an index reg or scale factor here. */ | |
10199 | if (*base_string == ',') | |
10200 | { | |
10201 | ++base_string; | |
10202 | if (is_space_char (*base_string)) | |
10203 | ++base_string; | |
10204 | ||
4eed87de AM |
10205 | if ((i.index_reg = parse_register (base_string, &end_op)) |
10206 | != NULL) | |
24eab124 | 10207 | { |
af6bdddf | 10208 | base_string = end_op; |
24eab124 AM |
10209 | if (is_space_char (*base_string)) |
10210 | ++base_string; | |
af6bdddf AM |
10211 | if (*base_string == ',') |
10212 | { | |
10213 | ++base_string; | |
10214 | if (is_space_char (*base_string)) | |
10215 | ++base_string; | |
10216 | } | |
e5cb08ac | 10217 | else if (*base_string != ')') |
af6bdddf | 10218 | { |
4eed87de AM |
10219 | as_bad (_("expecting `,' or `)' " |
10220 | "after index register in `%s'"), | |
af6bdddf AM |
10221 | operand_string); |
10222 | return 0; | |
10223 | } | |
24eab124 | 10224 | } |
af6bdddf | 10225 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 10226 | { |
f76bf5e0 L |
10227 | end_op = strchr (base_string, ','); |
10228 | if (end_op) | |
10229 | *end_op = '\0'; | |
af6bdddf | 10230 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
10231 | return 0; |
10232 | } | |
252b5132 | 10233 | |
47926f60 | 10234 | /* Check for scale factor. */ |
551c1ca1 | 10235 | if (*base_string != ')') |
af6bdddf | 10236 | { |
551c1ca1 AM |
10237 | char *end_scale = i386_scale (base_string); |
10238 | ||
10239 | if (!end_scale) | |
af6bdddf | 10240 | return 0; |
24eab124 | 10241 | |
551c1ca1 | 10242 | base_string = end_scale; |
af6bdddf AM |
10243 | if (is_space_char (*base_string)) |
10244 | ++base_string; | |
10245 | if (*base_string != ')') | |
10246 | { | |
4eed87de AM |
10247 | as_bad (_("expecting `)' " |
10248 | "after scale factor in `%s'"), | |
af6bdddf AM |
10249 | operand_string); |
10250 | return 0; | |
10251 | } | |
10252 | } | |
10253 | else if (!i.index_reg) | |
24eab124 | 10254 | { |
4eed87de AM |
10255 | as_bad (_("expecting index register or scale factor " |
10256 | "after `,'; got '%c'"), | |
af6bdddf | 10257 | *base_string); |
24eab124 AM |
10258 | return 0; |
10259 | } | |
10260 | } | |
af6bdddf | 10261 | else if (*base_string != ')') |
24eab124 | 10262 | { |
4eed87de AM |
10263 | as_bad (_("expecting `,' or `)' " |
10264 | "after base register in `%s'"), | |
af6bdddf | 10265 | operand_string); |
24eab124 AM |
10266 | return 0; |
10267 | } | |
c3332e24 | 10268 | } |
af6bdddf | 10269 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 10270 | { |
f76bf5e0 L |
10271 | end_op = strchr (base_string, ','); |
10272 | if (end_op) | |
10273 | *end_op = '\0'; | |
af6bdddf | 10274 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 10275 | return 0; |
c3332e24 | 10276 | } |
24eab124 AM |
10277 | } |
10278 | ||
10279 | /* If there's an expression beginning the operand, parse it, | |
10280 | assuming displacement_string_start and | |
10281 | displacement_string_end are meaningful. */ | |
10282 | if (displacement_string_start != displacement_string_end) | |
10283 | { | |
10284 | if (!i386_displacement (displacement_string_start, | |
10285 | displacement_string_end)) | |
10286 | return 0; | |
10287 | } | |
10288 | ||
10289 | /* Special case for (%dx) while doing input/output op. */ | |
10290 | if (i.base_reg | |
75e5731b JB |
10291 | && i.base_reg->reg_type.bitfield.instance == RegD |
10292 | && i.base_reg->reg_type.bitfield.word | |
24eab124 AM |
10293 | && i.index_reg == 0 |
10294 | && i.log2_scale_factor == 0 | |
10295 | && i.seg[i.mem_operands] == 0 | |
40fb9820 | 10296 | && !operand_type_check (i.types[this_operand], disp)) |
24eab124 | 10297 | { |
2fb5be8d | 10298 | i.types[this_operand] = i.base_reg->reg_type; |
24eab124 AM |
10299 | return 1; |
10300 | } | |
10301 | ||
eecb386c AM |
10302 | if (i386_index_check (operand_string) == 0) |
10303 | return 0; | |
c48dadc9 | 10304 | i.flags[this_operand] |= Operand_Mem; |
8325cc63 JB |
10305 | if (i.mem_operands == 0) |
10306 | i.memop1_string = xstrdup (operand_string); | |
24eab124 AM |
10307 | i.mem_operands++; |
10308 | } | |
10309 | else | |
ce8a8b2f AM |
10310 | { |
10311 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
10312 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
10313 | output_invalid (*op_string), | |
10314 | this_operand + 1, | |
10315 | op_string); | |
10316 | return 0; | |
10317 | } | |
47926f60 | 10318 | return 1; /* Normal return. */ |
252b5132 RH |
10319 | } |
10320 | \f | |
fa94de6b RM |
10321 | /* Calculate the maximum variable size (i.e., excluding fr_fix) |
10322 | that an rs_machine_dependent frag may reach. */ | |
10323 | ||
10324 | unsigned int | |
10325 | i386_frag_max_var (fragS *frag) | |
10326 | { | |
10327 | /* The only relaxable frags are for jumps. | |
10328 | Unconditional jumps can grow by 4 bytes and others by 5 bytes. */ | |
10329 | gas_assert (frag->fr_type == rs_machine_dependent); | |
10330 | return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5; | |
10331 | } | |
10332 | ||
b084df0b L |
10333 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
10334 | static int | |
8dcea932 | 10335 | elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var) |
b084df0b L |
10336 | { |
10337 | /* STT_GNU_IFUNC symbol must go through PLT. */ | |
10338 | if ((symbol_get_bfdsym (fr_symbol)->flags | |
10339 | & BSF_GNU_INDIRECT_FUNCTION) != 0) | |
10340 | return 0; | |
10341 | ||
10342 | if (!S_IS_EXTERNAL (fr_symbol)) | |
10343 | /* Symbol may be weak or local. */ | |
10344 | return !S_IS_WEAK (fr_symbol); | |
10345 | ||
8dcea932 L |
10346 | /* Global symbols with non-default visibility can't be preempted. */ |
10347 | if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT) | |
10348 | return 1; | |
10349 | ||
10350 | if (fr_var != NO_RELOC) | |
10351 | switch ((enum bfd_reloc_code_real) fr_var) | |
10352 | { | |
10353 | case BFD_RELOC_386_PLT32: | |
10354 | case BFD_RELOC_X86_64_PLT32: | |
33eaf5de | 10355 | /* Symbol with PLT relocation may be preempted. */ |
8dcea932 L |
10356 | return 0; |
10357 | default: | |
10358 | abort (); | |
10359 | } | |
10360 | ||
b084df0b L |
10361 | /* Global symbols with default visibility in a shared library may be |
10362 | preempted by another definition. */ | |
8dcea932 | 10363 | return !shared; |
b084df0b L |
10364 | } |
10365 | #endif | |
10366 | ||
ee7fcc42 AM |
10367 | /* md_estimate_size_before_relax() |
10368 | ||
10369 | Called just before relax() for rs_machine_dependent frags. The x86 | |
10370 | assembler uses these frags to handle variable size jump | |
10371 | instructions. | |
10372 | ||
10373 | Any symbol that is now undefined will not become defined. | |
10374 | Return the correct fr_subtype in the frag. | |
10375 | Return the initial "guess for variable size of frag" to caller. | |
10376 | The guess is actually the growth beyond the fixed part. Whatever | |
10377 | we do to grow the fixed or variable part contributes to our | |
10378 | returned value. */ | |
10379 | ||
252b5132 | 10380 | int |
7016a5d5 | 10381 | md_estimate_size_before_relax (fragS *fragP, segT segment) |
252b5132 | 10382 | { |
252b5132 | 10383 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
10384 | check for un-relaxable symbols. On an ELF system, we can't relax |
10385 | an externally visible symbol, because it may be overridden by a | |
10386 | shared library. */ | |
10387 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 10388 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 10389 | || (IS_ELF |
8dcea932 L |
10390 | && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol, |
10391 | fragP->fr_var)) | |
fbeb56a4 DK |
10392 | #endif |
10393 | #if defined (OBJ_COFF) && defined (TE_PE) | |
7ab9ffdd | 10394 | || (OUTPUT_FLAVOR == bfd_target_coff_flavour |
fbeb56a4 | 10395 | && S_IS_WEAK (fragP->fr_symbol)) |
b98ef147 AM |
10396 | #endif |
10397 | ) | |
252b5132 | 10398 | { |
b98ef147 AM |
10399 | /* Symbol is undefined in this segment, or we need to keep a |
10400 | reloc so that weak symbols can be overridden. */ | |
10401 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f86103b7 | 10402 | enum bfd_reloc_code_real reloc_type; |
ee7fcc42 AM |
10403 | unsigned char *opcode; |
10404 | int old_fr_fix; | |
f6af82bd | 10405 | |
ee7fcc42 | 10406 | if (fragP->fr_var != NO_RELOC) |
1e9cc1c2 | 10407 | reloc_type = (enum bfd_reloc_code_real) fragP->fr_var; |
b98ef147 | 10408 | else if (size == 2) |
f6af82bd | 10409 | reloc_type = BFD_RELOC_16_PCREL; |
bd7ab16b L |
10410 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
10411 | else if (need_plt32_p (fragP->fr_symbol)) | |
10412 | reloc_type = BFD_RELOC_X86_64_PLT32; | |
10413 | #endif | |
f6af82bd AM |
10414 | else |
10415 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 10416 | |
ee7fcc42 AM |
10417 | old_fr_fix = fragP->fr_fix; |
10418 | opcode = (unsigned char *) fragP->fr_opcode; | |
10419 | ||
fddf5b5b | 10420 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 10421 | { |
fddf5b5b AM |
10422 | case UNCOND_JUMP: |
10423 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 10424 | opcode[0] = 0xe9; |
252b5132 | 10425 | fragP->fr_fix += size; |
062cd5e7 AS |
10426 | fix_new (fragP, old_fr_fix, size, |
10427 | fragP->fr_symbol, | |
10428 | fragP->fr_offset, 1, | |
10429 | reloc_type); | |
252b5132 RH |
10430 | break; |
10431 | ||
fddf5b5b | 10432 | case COND_JUMP86: |
412167cb AM |
10433 | if (size == 2 |
10434 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) | |
fddf5b5b AM |
10435 | { |
10436 | /* Negate the condition, and branch past an | |
10437 | unconditional jump. */ | |
10438 | opcode[0] ^= 1; | |
10439 | opcode[1] = 3; | |
10440 | /* Insert an unconditional jump. */ | |
10441 | opcode[2] = 0xe9; | |
10442 | /* We added two extra opcode bytes, and have a two byte | |
10443 | offset. */ | |
10444 | fragP->fr_fix += 2 + 2; | |
062cd5e7 AS |
10445 | fix_new (fragP, old_fr_fix + 2, 2, |
10446 | fragP->fr_symbol, | |
10447 | fragP->fr_offset, 1, | |
10448 | reloc_type); | |
fddf5b5b AM |
10449 | break; |
10450 | } | |
10451 | /* Fall through. */ | |
10452 | ||
10453 | case COND_JUMP: | |
412167cb AM |
10454 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
10455 | { | |
3e02c1cc AM |
10456 | fixS *fixP; |
10457 | ||
412167cb | 10458 | fragP->fr_fix += 1; |
3e02c1cc AM |
10459 | fixP = fix_new (fragP, old_fr_fix, 1, |
10460 | fragP->fr_symbol, | |
10461 | fragP->fr_offset, 1, | |
10462 | BFD_RELOC_8_PCREL); | |
10463 | fixP->fx_signed = 1; | |
412167cb AM |
10464 | break; |
10465 | } | |
93c2a809 | 10466 | |
24eab124 | 10467 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 10468 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 10469 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 10470 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
10471 | /* We've added an opcode byte. */ |
10472 | fragP->fr_fix += 1 + size; | |
062cd5e7 AS |
10473 | fix_new (fragP, old_fr_fix + 1, size, |
10474 | fragP->fr_symbol, | |
10475 | fragP->fr_offset, 1, | |
10476 | reloc_type); | |
252b5132 | 10477 | break; |
fddf5b5b AM |
10478 | |
10479 | default: | |
10480 | BAD_CASE (fragP->fr_subtype); | |
10481 | break; | |
252b5132 RH |
10482 | } |
10483 | frag_wane (fragP); | |
ee7fcc42 | 10484 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 10485 | } |
93c2a809 | 10486 | |
93c2a809 AM |
10487 | /* Guess size depending on current relax state. Initially the relax |
10488 | state will correspond to a short jump and we return 1, because | |
10489 | the variable part of the frag (the branch offset) is one byte | |
10490 | long. However, we can relax a section more than once and in that | |
10491 | case we must either set fr_subtype back to the unrelaxed state, | |
10492 | or return the value for the appropriate branch. */ | |
10493 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
10494 | } |
10495 | ||
47926f60 KH |
10496 | /* Called after relax() is finished. |
10497 | ||
10498 | In: Address of frag. | |
10499 | fr_type == rs_machine_dependent. | |
10500 | fr_subtype is what the address relaxed to. | |
10501 | ||
10502 | Out: Any fixSs and constants are set up. | |
10503 | Caller will turn frag into a ".space 0". */ | |
10504 | ||
252b5132 | 10505 | void |
7016a5d5 TG |
10506 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, |
10507 | fragS *fragP) | |
252b5132 | 10508 | { |
29b0f896 | 10509 | unsigned char *opcode; |
252b5132 | 10510 | unsigned char *where_to_put_displacement = NULL; |
847f7ad4 AM |
10511 | offsetT target_address; |
10512 | offsetT opcode_address; | |
252b5132 | 10513 | unsigned int extension = 0; |
847f7ad4 | 10514 | offsetT displacement_from_opcode_start; |
252b5132 RH |
10515 | |
10516 | opcode = (unsigned char *) fragP->fr_opcode; | |
10517 | ||
47926f60 | 10518 | /* Address we want to reach in file space. */ |
252b5132 | 10519 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 10520 | |
47926f60 | 10521 | /* Address opcode resides at in file space. */ |
252b5132 RH |
10522 | opcode_address = fragP->fr_address + fragP->fr_fix; |
10523 | ||
47926f60 | 10524 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
10525 | displacement_from_opcode_start = target_address - opcode_address; |
10526 | ||
fddf5b5b | 10527 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 10528 | { |
47926f60 KH |
10529 | /* Don't have to change opcode. */ |
10530 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 10531 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
10532 | } |
10533 | else | |
10534 | { | |
10535 | if (no_cond_jump_promotion | |
10536 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4eed87de AM |
10537 | as_warn_where (fragP->fr_file, fragP->fr_line, |
10538 | _("long jump required")); | |
252b5132 | 10539 | |
fddf5b5b AM |
10540 | switch (fragP->fr_subtype) |
10541 | { | |
10542 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
10543 | extension = 4; /* 1 opcode + 4 displacement */ | |
10544 | opcode[0] = 0xe9; | |
10545 | where_to_put_displacement = &opcode[1]; | |
10546 | break; | |
252b5132 | 10547 | |
fddf5b5b AM |
10548 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
10549 | extension = 2; /* 1 opcode + 2 displacement */ | |
10550 | opcode[0] = 0xe9; | |
10551 | where_to_put_displacement = &opcode[1]; | |
10552 | break; | |
252b5132 | 10553 | |
fddf5b5b AM |
10554 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
10555 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
10556 | extension = 5; /* 2 opcode + 4 displacement */ | |
10557 | opcode[1] = opcode[0] + 0x10; | |
10558 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
10559 | where_to_put_displacement = &opcode[2]; | |
10560 | break; | |
252b5132 | 10561 | |
fddf5b5b AM |
10562 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
10563 | extension = 3; /* 2 opcode + 2 displacement */ | |
10564 | opcode[1] = opcode[0] + 0x10; | |
10565 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
10566 | where_to_put_displacement = &opcode[2]; | |
10567 | break; | |
252b5132 | 10568 | |
fddf5b5b AM |
10569 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
10570 | extension = 4; | |
10571 | opcode[0] ^= 1; | |
10572 | opcode[1] = 3; | |
10573 | opcode[2] = 0xe9; | |
10574 | where_to_put_displacement = &opcode[3]; | |
10575 | break; | |
10576 | ||
10577 | default: | |
10578 | BAD_CASE (fragP->fr_subtype); | |
10579 | break; | |
10580 | } | |
252b5132 | 10581 | } |
fddf5b5b | 10582 | |
7b81dfbb AJ |
10583 | /* If size if less then four we are sure that the operand fits, |
10584 | but if it's 4, then it could be that the displacement is larger | |
10585 | then -/+ 2GB. */ | |
10586 | if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 | |
10587 | && object_64bit | |
10588 | && ((addressT) (displacement_from_opcode_start - extension | |
4eed87de AM |
10589 | + ((addressT) 1 << 31)) |
10590 | > (((addressT) 2 << 31) - 1))) | |
7b81dfbb AJ |
10591 | { |
10592 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
10593 | _("jump target out of range")); | |
10594 | /* Make us emit 0. */ | |
10595 | displacement_from_opcode_start = extension; | |
10596 | } | |
47926f60 | 10597 | /* Now put displacement after opcode. */ |
252b5132 RH |
10598 | md_number_to_chars ((char *) where_to_put_displacement, |
10599 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 10600 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
10601 | fragP->fr_fix += extension; |
10602 | } | |
10603 | \f | |
7016a5d5 | 10604 | /* Apply a fixup (fixP) to segment data, once it has been determined |
252b5132 RH |
10605 | by our caller that we have all the info we need to fix it up. |
10606 | ||
7016a5d5 TG |
10607 | Parameter valP is the pointer to the value of the bits. |
10608 | ||
252b5132 RH |
10609 | On the 386, immediates, displacements, and data pointers are all in |
10610 | the same (little-endian) format, so we don't need to care about which | |
10611 | we are handling. */ | |
10612 | ||
94f592af | 10613 | void |
7016a5d5 | 10614 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 10615 | { |
94f592af | 10616 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
c6682705 | 10617 | valueT value = *valP; |
252b5132 | 10618 | |
f86103b7 | 10619 | #if !defined (TE_Mach) |
93382f6d AM |
10620 | if (fixP->fx_pcrel) |
10621 | { | |
10622 | switch (fixP->fx_r_type) | |
10623 | { | |
5865bb77 ILT |
10624 | default: |
10625 | break; | |
10626 | ||
d6ab8113 JB |
10627 | case BFD_RELOC_64: |
10628 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
10629 | break; | |
93382f6d | 10630 | case BFD_RELOC_32: |
ae8887b5 | 10631 | case BFD_RELOC_X86_64_32S: |
93382f6d AM |
10632 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
10633 | break; | |
10634 | case BFD_RELOC_16: | |
10635 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
10636 | break; | |
10637 | case BFD_RELOC_8: | |
10638 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
10639 | break; | |
10640 | } | |
10641 | } | |
252b5132 | 10642 | |
a161fe53 | 10643 | if (fixP->fx_addsy != NULL |
31312f95 | 10644 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
d6ab8113 | 10645 | || fixP->fx_r_type == BFD_RELOC_64_PCREL |
31312f95 | 10646 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
d258b828 | 10647 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) |
31312f95 | 10648 | && !use_rela_relocations) |
252b5132 | 10649 | { |
31312f95 AM |
10650 | /* This is a hack. There should be a better way to handle this. |
10651 | This covers for the fact that bfd_install_relocation will | |
10652 | subtract the current location (for partial_inplace, PC relative | |
10653 | relocations); see more below. */ | |
252b5132 | 10654 | #ifndef OBJ_AOUT |
718ddfc0 | 10655 | if (IS_ELF |
252b5132 RH |
10656 | #ifdef TE_PE |
10657 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
10658 | #endif | |
10659 | ) | |
10660 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
10661 | #endif | |
10662 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 10663 | if (IS_ELF) |
252b5132 | 10664 | { |
6539b54b | 10665 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
2f66722d | 10666 | |
6539b54b | 10667 | if ((sym_seg == seg |
2f66722d | 10668 | || (symbol_section_p (fixP->fx_addsy) |
6539b54b | 10669 | && sym_seg != absolute_section)) |
af65af87 | 10670 | && !generic_force_reloc (fixP)) |
2f66722d AM |
10671 | { |
10672 | /* Yes, we add the values in twice. This is because | |
6539b54b AM |
10673 | bfd_install_relocation subtracts them out again. I think |
10674 | bfd_install_relocation is broken, but I don't dare change | |
2f66722d AM |
10675 | it. FIXME. */ |
10676 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
10677 | } | |
252b5132 RH |
10678 | } |
10679 | #endif | |
10680 | #if defined (OBJ_COFF) && defined (TE_PE) | |
977cdf5a NC |
10681 | /* For some reason, the PE format does not store a |
10682 | section address offset for a PC relative symbol. */ | |
10683 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg | |
7be1c489 | 10684 | || S_IS_WEAK (fixP->fx_addsy)) |
252b5132 RH |
10685 | value += md_pcrel_from (fixP); |
10686 | #endif | |
10687 | } | |
fbeb56a4 | 10688 | #if defined (OBJ_COFF) && defined (TE_PE) |
f01c1a09 NC |
10689 | if (fixP->fx_addsy != NULL |
10690 | && S_IS_WEAK (fixP->fx_addsy) | |
10691 | /* PR 16858: Do not modify weak function references. */ | |
10692 | && ! fixP->fx_pcrel) | |
fbeb56a4 | 10693 | { |
296a8689 NC |
10694 | #if !defined (TE_PEP) |
10695 | /* For x86 PE weak function symbols are neither PC-relative | |
10696 | nor do they set S_IS_FUNCTION. So the only reliable way | |
10697 | to detect them is to check the flags of their containing | |
10698 | section. */ | |
10699 | if (S_GET_SEGMENT (fixP->fx_addsy) != NULL | |
10700 | && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE) | |
10701 | ; | |
10702 | else | |
10703 | #endif | |
fbeb56a4 DK |
10704 | value -= S_GET_VALUE (fixP->fx_addsy); |
10705 | } | |
10706 | #endif | |
252b5132 RH |
10707 | |
10708 | /* Fix a few things - the dynamic linker expects certain values here, | |
0234cb7c | 10709 | and we must not disappoint it. */ |
252b5132 | 10710 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 10711 | if (IS_ELF && fixP->fx_addsy) |
47926f60 KH |
10712 | switch (fixP->fx_r_type) |
10713 | { | |
10714 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 10715 | case BFD_RELOC_X86_64_PLT32: |
b9519cfe L |
10716 | /* Make the jump instruction point to the address of the operand. |
10717 | At runtime we merely add the offset to the actual PLT entry. | |
10718 | NB: Subtract the offset size only for jump instructions. */ | |
10719 | if (fixP->fx_pcrel) | |
10720 | value = -4; | |
47926f60 | 10721 | break; |
31312f95 | 10722 | |
13ae64f3 JJ |
10723 | case BFD_RELOC_386_TLS_GD: |
10724 | case BFD_RELOC_386_TLS_LDM: | |
13ae64f3 | 10725 | case BFD_RELOC_386_TLS_IE_32: |
37e55690 JJ |
10726 | case BFD_RELOC_386_TLS_IE: |
10727 | case BFD_RELOC_386_TLS_GOTIE: | |
67a4f2b7 | 10728 | case BFD_RELOC_386_TLS_GOTDESC: |
bffbf940 JJ |
10729 | case BFD_RELOC_X86_64_TLSGD: |
10730 | case BFD_RELOC_X86_64_TLSLD: | |
10731 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 | 10732 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
00f7efb6 JJ |
10733 | value = 0; /* Fully resolved at runtime. No addend. */ |
10734 | /* Fallthrough */ | |
10735 | case BFD_RELOC_386_TLS_LE: | |
10736 | case BFD_RELOC_386_TLS_LDO_32: | |
10737 | case BFD_RELOC_386_TLS_LE_32: | |
10738 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 10739 | case BFD_RELOC_X86_64_DTPOFF64: |
00f7efb6 | 10740 | case BFD_RELOC_X86_64_TPOFF32: |
d6ab8113 | 10741 | case BFD_RELOC_X86_64_TPOFF64: |
00f7efb6 JJ |
10742 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
10743 | break; | |
10744 | ||
67a4f2b7 AO |
10745 | case BFD_RELOC_386_TLS_DESC_CALL: |
10746 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
10747 | value = 0; /* Fully resolved at runtime. No addend. */ | |
10748 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
10749 | fixP->fx_done = 0; | |
10750 | return; | |
10751 | ||
47926f60 KH |
10752 | case BFD_RELOC_VTABLE_INHERIT: |
10753 | case BFD_RELOC_VTABLE_ENTRY: | |
10754 | fixP->fx_done = 0; | |
94f592af | 10755 | return; |
47926f60 KH |
10756 | |
10757 | default: | |
10758 | break; | |
10759 | } | |
10760 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
c6682705 | 10761 | *valP = value; |
f86103b7 | 10762 | #endif /* !defined (TE_Mach) */ |
3e73aa7c | 10763 | |
3e73aa7c | 10764 | /* Are we finished with this relocation now? */ |
c6682705 | 10765 | if (fixP->fx_addsy == NULL) |
3e73aa7c | 10766 | fixP->fx_done = 1; |
fbeb56a4 DK |
10767 | #if defined (OBJ_COFF) && defined (TE_PE) |
10768 | else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) | |
10769 | { | |
10770 | fixP->fx_done = 0; | |
10771 | /* Remember value for tc_gen_reloc. */ | |
10772 | fixP->fx_addnumber = value; | |
10773 | /* Clear out the frag for now. */ | |
10774 | value = 0; | |
10775 | } | |
10776 | #endif | |
3e73aa7c JH |
10777 | else if (use_rela_relocations) |
10778 | { | |
10779 | fixP->fx_no_overflow = 1; | |
062cd5e7 AS |
10780 | /* Remember value for tc_gen_reloc. */ |
10781 | fixP->fx_addnumber = value; | |
3e73aa7c JH |
10782 | value = 0; |
10783 | } | |
f86103b7 | 10784 | |
94f592af | 10785 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 10786 | } |
252b5132 | 10787 | \f |
6d4af3c2 | 10788 | const char * |
499ac353 | 10789 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 10790 | { |
499ac353 NC |
10791 | /* This outputs the LITTLENUMs in REVERSE order; |
10792 | in accord with the bigendian 386. */ | |
10793 | return ieee_md_atof (type, litP, sizeP, FALSE); | |
252b5132 RH |
10794 | } |
10795 | \f | |
2d545b82 | 10796 | static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; |
252b5132 | 10797 | |
252b5132 | 10798 | static char * |
e3bb37b5 | 10799 | output_invalid (int c) |
252b5132 | 10800 | { |
3882b010 | 10801 | if (ISPRINT (c)) |
f9f21a03 L |
10802 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
10803 | "'%c'", c); | |
252b5132 | 10804 | else |
f9f21a03 | 10805 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
2d545b82 | 10806 | "(0x%x)", (unsigned char) c); |
252b5132 RH |
10807 | return output_invalid_buf; |
10808 | } | |
10809 | ||
af6bdddf | 10810 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
10811 | |
10812 | static const reg_entry * | |
4d1bb795 | 10813 | parse_real_register (char *reg_string, char **end_op) |
252b5132 | 10814 | { |
af6bdddf AM |
10815 | char *s = reg_string; |
10816 | char *p; | |
252b5132 RH |
10817 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
10818 | const reg_entry *r; | |
10819 | ||
10820 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
10821 | if (*s == REGISTER_PREFIX) | |
10822 | ++s; | |
10823 | ||
10824 | if (is_space_char (*s)) | |
10825 | ++s; | |
10826 | ||
10827 | p = reg_name_given; | |
af6bdddf | 10828 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
10829 | { |
10830 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
10831 | return (const reg_entry *) NULL; |
10832 | s++; | |
252b5132 RH |
10833 | } |
10834 | ||
6588847e DN |
10835 | /* For naked regs, make sure that we are not dealing with an identifier. |
10836 | This prevents confusing an identifier like `eax_var' with register | |
10837 | `eax'. */ | |
10838 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
10839 | return (const reg_entry *) NULL; | |
10840 | ||
af6bdddf | 10841 | *end_op = s; |
252b5132 RH |
10842 | |
10843 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
10844 | ||
5f47d35b | 10845 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
47926f60 | 10846 | if (r == i386_regtab /* %st is first entry of table */) |
5f47d35b | 10847 | { |
0e0eea78 JB |
10848 | if (!cpu_arch_flags.bitfield.cpu8087 |
10849 | && !cpu_arch_flags.bitfield.cpu287 | |
10850 | && !cpu_arch_flags.bitfield.cpu387) | |
10851 | return (const reg_entry *) NULL; | |
10852 | ||
5f47d35b AM |
10853 | if (is_space_char (*s)) |
10854 | ++s; | |
10855 | if (*s == '(') | |
10856 | { | |
af6bdddf | 10857 | ++s; |
5f47d35b AM |
10858 | if (is_space_char (*s)) |
10859 | ++s; | |
10860 | if (*s >= '0' && *s <= '7') | |
10861 | { | |
db557034 | 10862 | int fpr = *s - '0'; |
af6bdddf | 10863 | ++s; |
5f47d35b AM |
10864 | if (is_space_char (*s)) |
10865 | ++s; | |
10866 | if (*s == ')') | |
10867 | { | |
10868 | *end_op = s + 1; | |
1e9cc1c2 | 10869 | r = (const reg_entry *) hash_find (reg_hash, "st(0)"); |
db557034 AM |
10870 | know (r); |
10871 | return r + fpr; | |
5f47d35b | 10872 | } |
5f47d35b | 10873 | } |
47926f60 | 10874 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
10875 | return (const reg_entry *) NULL; |
10876 | } | |
10877 | } | |
10878 | ||
a60de03c JB |
10879 | if (r == NULL || allow_pseudo_reg) |
10880 | return r; | |
10881 | ||
0dfbf9d7 | 10882 | if (operand_type_all_zero (&r->reg_type)) |
a60de03c JB |
10883 | return (const reg_entry *) NULL; |
10884 | ||
dc821c5f | 10885 | if ((r->reg_type.bitfield.dword |
00cee14f | 10886 | || (r->reg_type.bitfield.class == SReg && r->reg_num > 3) |
4a5c67ed JB |
10887 | || r->reg_type.bitfield.class == RegCR |
10888 | || r->reg_type.bitfield.class == RegDR | |
10889 | || r->reg_type.bitfield.class == RegTR) | |
192dc9c6 JB |
10890 | && !cpu_arch_flags.bitfield.cpui386) |
10891 | return (const reg_entry *) NULL; | |
10892 | ||
3528c362 | 10893 | if (r->reg_type.bitfield.class == RegMMX && !cpu_arch_flags.bitfield.cpummx) |
192dc9c6 JB |
10894 | return (const reg_entry *) NULL; |
10895 | ||
6e041cf4 JB |
10896 | if (!cpu_arch_flags.bitfield.cpuavx512f) |
10897 | { | |
f74a6307 JB |
10898 | if (r->reg_type.bitfield.zmmword |
10899 | || r->reg_type.bitfield.class == RegMask) | |
6e041cf4 | 10900 | return (const reg_entry *) NULL; |
40f12533 | 10901 | |
6e041cf4 JB |
10902 | if (!cpu_arch_flags.bitfield.cpuavx) |
10903 | { | |
10904 | if (r->reg_type.bitfield.ymmword) | |
10905 | return (const reg_entry *) NULL; | |
1848e567 | 10906 | |
6e041cf4 JB |
10907 | if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword) |
10908 | return (const reg_entry *) NULL; | |
10909 | } | |
10910 | } | |
43234a1e | 10911 | |
f74a6307 | 10912 | if (r->reg_type.bitfield.class == RegBND && !cpu_arch_flags.bitfield.cpumpx) |
1adf7f56 JB |
10913 | return (const reg_entry *) NULL; |
10914 | ||
db51cc60 | 10915 | /* Don't allow fake index register unless allow_index_reg isn't 0. */ |
e968fc9b | 10916 | if (!allow_index_reg && r->reg_num == RegIZ) |
db51cc60 L |
10917 | return (const reg_entry *) NULL; |
10918 | ||
1d3f8286 JB |
10919 | /* Upper 16 vector registers are only available with VREX in 64bit |
10920 | mode, and require EVEX encoding. */ | |
10921 | if (r->reg_flags & RegVRex) | |
43234a1e | 10922 | { |
e951d5ca | 10923 | if (!cpu_arch_flags.bitfield.cpuavx512f |
43234a1e L |
10924 | || flag_code != CODE_64BIT) |
10925 | return (const reg_entry *) NULL; | |
1d3f8286 JB |
10926 | |
10927 | i.vec_encoding = vex_encoding_evex; | |
43234a1e L |
10928 | } |
10929 | ||
4787f4a5 | 10930 | if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword) |
4a5c67ed | 10931 | && (!cpu_arch_flags.bitfield.cpulm || r->reg_type.bitfield.class != RegCR) |
1ae00879 | 10932 | && flag_code != CODE_64BIT) |
20f0a1fc | 10933 | return (const reg_entry *) NULL; |
1ae00879 | 10934 | |
00cee14f JB |
10935 | if (r->reg_type.bitfield.class == SReg && r->reg_num == RegFlat |
10936 | && !intel_syntax) | |
b7240065 JB |
10937 | return (const reg_entry *) NULL; |
10938 | ||
252b5132 RH |
10939 | return r; |
10940 | } | |
4d1bb795 JB |
10941 | |
10942 | /* REG_STRING starts *before* REGISTER_PREFIX. */ | |
10943 | ||
10944 | static const reg_entry * | |
10945 | parse_register (char *reg_string, char **end_op) | |
10946 | { | |
10947 | const reg_entry *r; | |
10948 | ||
10949 | if (*reg_string == REGISTER_PREFIX || allow_naked_reg) | |
10950 | r = parse_real_register (reg_string, end_op); | |
10951 | else | |
10952 | r = NULL; | |
10953 | if (!r) | |
10954 | { | |
10955 | char *save = input_line_pointer; | |
10956 | char c; | |
10957 | symbolS *symbolP; | |
10958 | ||
10959 | input_line_pointer = reg_string; | |
d02603dc | 10960 | c = get_symbol_name (®_string); |
4d1bb795 JB |
10961 | symbolP = symbol_find (reg_string); |
10962 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) | |
10963 | { | |
10964 | const expressionS *e = symbol_get_value_expression (symbolP); | |
10965 | ||
0398aac5 | 10966 | know (e->X_op == O_register); |
4eed87de | 10967 | know (e->X_add_number >= 0 |
c3fe08fa | 10968 | && (valueT) e->X_add_number < i386_regtab_size); |
4d1bb795 | 10969 | r = i386_regtab + e->X_add_number; |
d3bb6b49 | 10970 | if ((r->reg_flags & RegVRex)) |
86fa6981 | 10971 | i.vec_encoding = vex_encoding_evex; |
4d1bb795 JB |
10972 | *end_op = input_line_pointer; |
10973 | } | |
10974 | *input_line_pointer = c; | |
10975 | input_line_pointer = save; | |
10976 | } | |
10977 | return r; | |
10978 | } | |
10979 | ||
10980 | int | |
10981 | i386_parse_name (char *name, expressionS *e, char *nextcharP) | |
10982 | { | |
10983 | const reg_entry *r; | |
10984 | char *end = input_line_pointer; | |
10985 | ||
10986 | *end = *nextcharP; | |
10987 | r = parse_register (name, &input_line_pointer); | |
10988 | if (r && end <= input_line_pointer) | |
10989 | { | |
10990 | *nextcharP = *input_line_pointer; | |
10991 | *input_line_pointer = 0; | |
10992 | e->X_op = O_register; | |
10993 | e->X_add_number = r - i386_regtab; | |
10994 | return 1; | |
10995 | } | |
10996 | input_line_pointer = end; | |
10997 | *end = 0; | |
ee86248c | 10998 | return intel_syntax ? i386_intel_parse_name (name, e) : 0; |
4d1bb795 JB |
10999 | } |
11000 | ||
11001 | void | |
11002 | md_operand (expressionS *e) | |
11003 | { | |
ee86248c JB |
11004 | char *end; |
11005 | const reg_entry *r; | |
4d1bb795 | 11006 | |
ee86248c JB |
11007 | switch (*input_line_pointer) |
11008 | { | |
11009 | case REGISTER_PREFIX: | |
11010 | r = parse_real_register (input_line_pointer, &end); | |
4d1bb795 JB |
11011 | if (r) |
11012 | { | |
11013 | e->X_op = O_register; | |
11014 | e->X_add_number = r - i386_regtab; | |
11015 | input_line_pointer = end; | |
11016 | } | |
ee86248c JB |
11017 | break; |
11018 | ||
11019 | case '[': | |
9c2799c2 | 11020 | gas_assert (intel_syntax); |
ee86248c JB |
11021 | end = input_line_pointer++; |
11022 | expression (e); | |
11023 | if (*input_line_pointer == ']') | |
11024 | { | |
11025 | ++input_line_pointer; | |
11026 | e->X_op_symbol = make_expr_symbol (e); | |
11027 | e->X_add_symbol = NULL; | |
11028 | e->X_add_number = 0; | |
11029 | e->X_op = O_index; | |
11030 | } | |
11031 | else | |
11032 | { | |
11033 | e->X_op = O_absent; | |
11034 | input_line_pointer = end; | |
11035 | } | |
11036 | break; | |
4d1bb795 JB |
11037 | } |
11038 | } | |
11039 | ||
252b5132 | 11040 | \f |
4cc782b5 | 11041 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
b6f8c7c4 | 11042 | const char *md_shortopts = "kVQ:sqnO::"; |
252b5132 | 11043 | #else |
b6f8c7c4 | 11044 | const char *md_shortopts = "qnO::"; |
252b5132 | 11045 | #endif |
6e0b89ee | 11046 | |
3e73aa7c | 11047 | #define OPTION_32 (OPTION_MD_BASE + 0) |
b3b91714 AM |
11048 | #define OPTION_64 (OPTION_MD_BASE + 1) |
11049 | #define OPTION_DIVIDE (OPTION_MD_BASE + 2) | |
9103f4f4 L |
11050 | #define OPTION_MARCH (OPTION_MD_BASE + 3) |
11051 | #define OPTION_MTUNE (OPTION_MD_BASE + 4) | |
1efbbeb4 L |
11052 | #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) |
11053 | #define OPTION_MSYNTAX (OPTION_MD_BASE + 6) | |
11054 | #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) | |
11055 | #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) | |
bd5dea88 | 11056 | #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9) |
c0f3af97 | 11057 | #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10) |
daf50ae7 | 11058 | #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11) |
7bab8ab5 JB |
11059 | #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12) |
11060 | #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13) | |
11061 | #define OPTION_X32 (OPTION_MD_BASE + 14) | |
7e8b059b | 11062 | #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15) |
43234a1e L |
11063 | #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16) |
11064 | #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17) | |
167ad85b | 11065 | #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18) |
d1982f93 | 11066 | #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19) |
d3d3c6db | 11067 | #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20) |
8dcea932 | 11068 | #define OPTION_MSHARED (OPTION_MD_BASE + 21) |
5db04b09 L |
11069 | #define OPTION_MAMD64 (OPTION_MD_BASE + 22) |
11070 | #define OPTION_MINTEL64 (OPTION_MD_BASE + 23) | |
e4e00185 | 11071 | #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24) |
b4a3a7b4 | 11072 | #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25) |
03751133 | 11073 | #define OPTION_MVEXWIG (OPTION_MD_BASE + 26) |
b3b91714 | 11074 | |
99ad8390 NC |
11075 | struct option md_longopts[] = |
11076 | { | |
3e73aa7c | 11077 | {"32", no_argument, NULL, OPTION_32}, |
321098a5 | 11078 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 11079 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c | 11080 | {"64", no_argument, NULL, OPTION_64}, |
351f65ca L |
11081 | #endif |
11082 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
570561f7 | 11083 | {"x32", no_argument, NULL, OPTION_X32}, |
8dcea932 | 11084 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
b4a3a7b4 | 11085 | {"mx86-used-note", required_argument, NULL, OPTION_X86_USED_NOTE}, |
6e0b89ee | 11086 | #endif |
b3b91714 | 11087 | {"divide", no_argument, NULL, OPTION_DIVIDE}, |
9103f4f4 L |
11088 | {"march", required_argument, NULL, OPTION_MARCH}, |
11089 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1efbbeb4 L |
11090 | {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, |
11091 | {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, | |
11092 | {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, | |
11093 | {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, | |
c0f3af97 | 11094 | {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX}, |
daf50ae7 | 11095 | {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK}, |
7bab8ab5 | 11096 | {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK}, |
539f890d | 11097 | {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR}, |
03751133 | 11098 | {"mvexwig", required_argument, NULL, OPTION_MVEXWIG}, |
7e8b059b | 11099 | {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX}, |
43234a1e L |
11100 | {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG}, |
11101 | {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG}, | |
167ad85b TG |
11102 | # if defined (TE_PE) || defined (TE_PEP) |
11103 | {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ}, | |
11104 | #endif | |
d1982f93 | 11105 | {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX}, |
e4e00185 | 11106 | {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD}, |
0cb4071e | 11107 | {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS}, |
d3d3c6db | 11108 | {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG}, |
5db04b09 L |
11109 | {"mamd64", no_argument, NULL, OPTION_MAMD64}, |
11110 | {"mintel64", no_argument, NULL, OPTION_MINTEL64}, | |
252b5132 RH |
11111 | {NULL, no_argument, NULL, 0} |
11112 | }; | |
11113 | size_t md_longopts_size = sizeof (md_longopts); | |
11114 | ||
11115 | int | |
17b9d67d | 11116 | md_parse_option (int c, const char *arg) |
252b5132 | 11117 | { |
91d6fa6a | 11118 | unsigned int j; |
293f5f65 | 11119 | char *arch, *next, *saved; |
9103f4f4 | 11120 | |
252b5132 RH |
11121 | switch (c) |
11122 | { | |
12b55ccc L |
11123 | case 'n': |
11124 | optimize_align_code = 0; | |
11125 | break; | |
11126 | ||
a38cf1db AM |
11127 | case 'q': |
11128 | quiet_warnings = 1; | |
252b5132 RH |
11129 | break; |
11130 | ||
11131 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
11132 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
11133 | should be emitted or not. FIXME: Not implemented. */ | |
11134 | case 'Q': | |
d4693039 JB |
11135 | if ((arg[0] != 'y' && arg[0] != 'n') || arg[1]) |
11136 | return 0; | |
252b5132 RH |
11137 | break; |
11138 | ||
11139 | /* -V: SVR4 argument to print version ID. */ | |
11140 | case 'V': | |
11141 | print_version_id (); | |
11142 | break; | |
11143 | ||
a38cf1db AM |
11144 | /* -k: Ignore for FreeBSD compatibility. */ |
11145 | case 'k': | |
252b5132 | 11146 | break; |
4cc782b5 ILT |
11147 | |
11148 | case 's': | |
11149 | /* -s: On i386 Solaris, this tells the native assembler to use | |
29b0f896 | 11150 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
4cc782b5 | 11151 | break; |
8dcea932 L |
11152 | |
11153 | case OPTION_MSHARED: | |
11154 | shared = 1; | |
11155 | break; | |
b4a3a7b4 L |
11156 | |
11157 | case OPTION_X86_USED_NOTE: | |
11158 | if (strcasecmp (arg, "yes") == 0) | |
11159 | x86_used_note = 1; | |
11160 | else if (strcasecmp (arg, "no") == 0) | |
11161 | x86_used_note = 0; | |
11162 | else | |
11163 | as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg); | |
11164 | break; | |
11165 | ||
11166 | ||
99ad8390 | 11167 | #endif |
321098a5 | 11168 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 11169 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c JH |
11170 | case OPTION_64: |
11171 | { | |
11172 | const char **list, **l; | |
11173 | ||
3e73aa7c JH |
11174 | list = bfd_target_list (); |
11175 | for (l = list; *l != NULL; l++) | |
8620418b | 11176 | if (CONST_STRNEQ (*l, "elf64-x86-64") |
99ad8390 NC |
11177 | || strcmp (*l, "coff-x86-64") == 0 |
11178 | || strcmp (*l, "pe-x86-64") == 0 | |
d382c579 TG |
11179 | || strcmp (*l, "pei-x86-64") == 0 |
11180 | || strcmp (*l, "mach-o-x86-64") == 0) | |
6e0b89ee AM |
11181 | { |
11182 | default_arch = "x86_64"; | |
11183 | break; | |
11184 | } | |
3e73aa7c | 11185 | if (*l == NULL) |
2b5d6a91 | 11186 | as_fatal (_("no compiled in support for x86_64")); |
3e73aa7c JH |
11187 | free (list); |
11188 | } | |
11189 | break; | |
11190 | #endif | |
252b5132 | 11191 | |
351f65ca | 11192 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
570561f7 | 11193 | case OPTION_X32: |
351f65ca L |
11194 | if (IS_ELF) |
11195 | { | |
11196 | const char **list, **l; | |
11197 | ||
11198 | list = bfd_target_list (); | |
11199 | for (l = list; *l != NULL; l++) | |
11200 | if (CONST_STRNEQ (*l, "elf32-x86-64")) | |
11201 | { | |
11202 | default_arch = "x86_64:32"; | |
11203 | break; | |
11204 | } | |
11205 | if (*l == NULL) | |
2b5d6a91 | 11206 | as_fatal (_("no compiled in support for 32bit x86_64")); |
351f65ca L |
11207 | free (list); |
11208 | } | |
11209 | else | |
11210 | as_fatal (_("32bit x86_64 is only supported for ELF")); | |
11211 | break; | |
11212 | #endif | |
11213 | ||
6e0b89ee AM |
11214 | case OPTION_32: |
11215 | default_arch = "i386"; | |
11216 | break; | |
11217 | ||
b3b91714 AM |
11218 | case OPTION_DIVIDE: |
11219 | #ifdef SVR4_COMMENT_CHARS | |
11220 | { | |
11221 | char *n, *t; | |
11222 | const char *s; | |
11223 | ||
add39d23 | 11224 | n = XNEWVEC (char, strlen (i386_comment_chars) + 1); |
b3b91714 AM |
11225 | t = n; |
11226 | for (s = i386_comment_chars; *s != '\0'; s++) | |
11227 | if (*s != '/') | |
11228 | *t++ = *s; | |
11229 | *t = '\0'; | |
11230 | i386_comment_chars = n; | |
11231 | } | |
11232 | #endif | |
11233 | break; | |
11234 | ||
9103f4f4 | 11235 | case OPTION_MARCH: |
293f5f65 L |
11236 | saved = xstrdup (arg); |
11237 | arch = saved; | |
11238 | /* Allow -march=+nosse. */ | |
11239 | if (*arch == '+') | |
11240 | arch++; | |
6305a203 | 11241 | do |
9103f4f4 | 11242 | { |
6305a203 | 11243 | if (*arch == '.') |
2b5d6a91 | 11244 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
11245 | next = strchr (arch, '+'); |
11246 | if (next) | |
11247 | *next++ = '\0'; | |
91d6fa6a | 11248 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 11249 | { |
91d6fa6a | 11250 | if (strcmp (arch, cpu_arch [j].name) == 0) |
ccc9c027 | 11251 | { |
6305a203 | 11252 | /* Processor. */ |
1ded5609 JB |
11253 | if (! cpu_arch[j].flags.bitfield.cpui386) |
11254 | continue; | |
11255 | ||
91d6fa6a | 11256 | cpu_arch_name = cpu_arch[j].name; |
6305a203 | 11257 | cpu_sub_arch_name = NULL; |
91d6fa6a NC |
11258 | cpu_arch_flags = cpu_arch[j].flags; |
11259 | cpu_arch_isa = cpu_arch[j].type; | |
11260 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
6305a203 L |
11261 | if (!cpu_arch_tune_set) |
11262 | { | |
11263 | cpu_arch_tune = cpu_arch_isa; | |
11264 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
11265 | } | |
11266 | break; | |
11267 | } | |
91d6fa6a NC |
11268 | else if (*cpu_arch [j].name == '.' |
11269 | && strcmp (arch, cpu_arch [j].name + 1) == 0) | |
6305a203 | 11270 | { |
33eaf5de | 11271 | /* ISA extension. */ |
6305a203 | 11272 | i386_cpu_flags flags; |
309d3373 | 11273 | |
293f5f65 L |
11274 | flags = cpu_flags_or (cpu_arch_flags, |
11275 | cpu_arch[j].flags); | |
81486035 | 11276 | |
5b64d091 | 11277 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
6305a203 L |
11278 | { |
11279 | if (cpu_sub_arch_name) | |
11280 | { | |
11281 | char *name = cpu_sub_arch_name; | |
11282 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 11283 | cpu_arch[j].name, |
1bf57e9f | 11284 | (const char *) NULL); |
6305a203 L |
11285 | free (name); |
11286 | } | |
11287 | else | |
91d6fa6a | 11288 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
6305a203 | 11289 | cpu_arch_flags = flags; |
a586129e | 11290 | cpu_arch_isa_flags = flags; |
6305a203 | 11291 | } |
0089dace L |
11292 | else |
11293 | cpu_arch_isa_flags | |
11294 | = cpu_flags_or (cpu_arch_isa_flags, | |
11295 | cpu_arch[j].flags); | |
6305a203 | 11296 | break; |
ccc9c027 | 11297 | } |
9103f4f4 | 11298 | } |
6305a203 | 11299 | |
293f5f65 L |
11300 | if (j >= ARRAY_SIZE (cpu_arch)) |
11301 | { | |
33eaf5de | 11302 | /* Disable an ISA extension. */ |
293f5f65 L |
11303 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
11304 | if (strcmp (arch, cpu_noarch [j].name) == 0) | |
11305 | { | |
11306 | i386_cpu_flags flags; | |
11307 | ||
11308 | flags = cpu_flags_and_not (cpu_arch_flags, | |
11309 | cpu_noarch[j].flags); | |
11310 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
11311 | { | |
11312 | if (cpu_sub_arch_name) | |
11313 | { | |
11314 | char *name = cpu_sub_arch_name; | |
11315 | cpu_sub_arch_name = concat (arch, | |
11316 | (const char *) NULL); | |
11317 | free (name); | |
11318 | } | |
11319 | else | |
11320 | cpu_sub_arch_name = xstrdup (arch); | |
11321 | cpu_arch_flags = flags; | |
11322 | cpu_arch_isa_flags = flags; | |
11323 | } | |
11324 | break; | |
11325 | } | |
11326 | ||
11327 | if (j >= ARRAY_SIZE (cpu_noarch)) | |
11328 | j = ARRAY_SIZE (cpu_arch); | |
11329 | } | |
11330 | ||
91d6fa6a | 11331 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 11332 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
11333 | |
11334 | arch = next; | |
9103f4f4 | 11335 | } |
293f5f65 L |
11336 | while (next != NULL); |
11337 | free (saved); | |
9103f4f4 L |
11338 | break; |
11339 | ||
11340 | case OPTION_MTUNE: | |
11341 | if (*arg == '.') | |
2b5d6a91 | 11342 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
91d6fa6a | 11343 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 11344 | { |
91d6fa6a | 11345 | if (strcmp (arg, cpu_arch [j].name) == 0) |
9103f4f4 | 11346 | { |
ccc9c027 | 11347 | cpu_arch_tune_set = 1; |
91d6fa6a NC |
11348 | cpu_arch_tune = cpu_arch [j].type; |
11349 | cpu_arch_tune_flags = cpu_arch[j].flags; | |
9103f4f4 L |
11350 | break; |
11351 | } | |
11352 | } | |
91d6fa6a | 11353 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 11354 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
9103f4f4 L |
11355 | break; |
11356 | ||
1efbbeb4 L |
11357 | case OPTION_MMNEMONIC: |
11358 | if (strcasecmp (arg, "att") == 0) | |
11359 | intel_mnemonic = 0; | |
11360 | else if (strcasecmp (arg, "intel") == 0) | |
11361 | intel_mnemonic = 1; | |
11362 | else | |
2b5d6a91 | 11363 | as_fatal (_("invalid -mmnemonic= option: `%s'"), arg); |
1efbbeb4 L |
11364 | break; |
11365 | ||
11366 | case OPTION_MSYNTAX: | |
11367 | if (strcasecmp (arg, "att") == 0) | |
11368 | intel_syntax = 0; | |
11369 | else if (strcasecmp (arg, "intel") == 0) | |
11370 | intel_syntax = 1; | |
11371 | else | |
2b5d6a91 | 11372 | as_fatal (_("invalid -msyntax= option: `%s'"), arg); |
1efbbeb4 L |
11373 | break; |
11374 | ||
11375 | case OPTION_MINDEX_REG: | |
11376 | allow_index_reg = 1; | |
11377 | break; | |
11378 | ||
11379 | case OPTION_MNAKED_REG: | |
11380 | allow_naked_reg = 1; | |
11381 | break; | |
11382 | ||
c0f3af97 L |
11383 | case OPTION_MSSE2AVX: |
11384 | sse2avx = 1; | |
11385 | break; | |
11386 | ||
daf50ae7 L |
11387 | case OPTION_MSSE_CHECK: |
11388 | if (strcasecmp (arg, "error") == 0) | |
7bab8ab5 | 11389 | sse_check = check_error; |
daf50ae7 | 11390 | else if (strcasecmp (arg, "warning") == 0) |
7bab8ab5 | 11391 | sse_check = check_warning; |
daf50ae7 | 11392 | else if (strcasecmp (arg, "none") == 0) |
7bab8ab5 | 11393 | sse_check = check_none; |
daf50ae7 | 11394 | else |
2b5d6a91 | 11395 | as_fatal (_("invalid -msse-check= option: `%s'"), arg); |
daf50ae7 L |
11396 | break; |
11397 | ||
7bab8ab5 JB |
11398 | case OPTION_MOPERAND_CHECK: |
11399 | if (strcasecmp (arg, "error") == 0) | |
11400 | operand_check = check_error; | |
11401 | else if (strcasecmp (arg, "warning") == 0) | |
11402 | operand_check = check_warning; | |
11403 | else if (strcasecmp (arg, "none") == 0) | |
11404 | operand_check = check_none; | |
11405 | else | |
11406 | as_fatal (_("invalid -moperand-check= option: `%s'"), arg); | |
11407 | break; | |
11408 | ||
539f890d L |
11409 | case OPTION_MAVXSCALAR: |
11410 | if (strcasecmp (arg, "128") == 0) | |
11411 | avxscalar = vex128; | |
11412 | else if (strcasecmp (arg, "256") == 0) | |
11413 | avxscalar = vex256; | |
11414 | else | |
2b5d6a91 | 11415 | as_fatal (_("invalid -mavxscalar= option: `%s'"), arg); |
539f890d L |
11416 | break; |
11417 | ||
03751133 L |
11418 | case OPTION_MVEXWIG: |
11419 | if (strcmp (arg, "0") == 0) | |
40c9c8de | 11420 | vexwig = vexw0; |
03751133 | 11421 | else if (strcmp (arg, "1") == 0) |
40c9c8de | 11422 | vexwig = vexw1; |
03751133 L |
11423 | else |
11424 | as_fatal (_("invalid -mvexwig= option: `%s'"), arg); | |
11425 | break; | |
11426 | ||
7e8b059b L |
11427 | case OPTION_MADD_BND_PREFIX: |
11428 | add_bnd_prefix = 1; | |
11429 | break; | |
11430 | ||
43234a1e L |
11431 | case OPTION_MEVEXLIG: |
11432 | if (strcmp (arg, "128") == 0) | |
11433 | evexlig = evexl128; | |
11434 | else if (strcmp (arg, "256") == 0) | |
11435 | evexlig = evexl256; | |
11436 | else if (strcmp (arg, "512") == 0) | |
11437 | evexlig = evexl512; | |
11438 | else | |
11439 | as_fatal (_("invalid -mevexlig= option: `%s'"), arg); | |
11440 | break; | |
11441 | ||
d3d3c6db IT |
11442 | case OPTION_MEVEXRCIG: |
11443 | if (strcmp (arg, "rne") == 0) | |
11444 | evexrcig = rne; | |
11445 | else if (strcmp (arg, "rd") == 0) | |
11446 | evexrcig = rd; | |
11447 | else if (strcmp (arg, "ru") == 0) | |
11448 | evexrcig = ru; | |
11449 | else if (strcmp (arg, "rz") == 0) | |
11450 | evexrcig = rz; | |
11451 | else | |
11452 | as_fatal (_("invalid -mevexrcig= option: `%s'"), arg); | |
11453 | break; | |
11454 | ||
43234a1e L |
11455 | case OPTION_MEVEXWIG: |
11456 | if (strcmp (arg, "0") == 0) | |
11457 | evexwig = evexw0; | |
11458 | else if (strcmp (arg, "1") == 0) | |
11459 | evexwig = evexw1; | |
11460 | else | |
11461 | as_fatal (_("invalid -mevexwig= option: `%s'"), arg); | |
11462 | break; | |
11463 | ||
167ad85b TG |
11464 | # if defined (TE_PE) || defined (TE_PEP) |
11465 | case OPTION_MBIG_OBJ: | |
11466 | use_big_obj = 1; | |
11467 | break; | |
11468 | #endif | |
11469 | ||
d1982f93 | 11470 | case OPTION_MOMIT_LOCK_PREFIX: |
d022bddd IT |
11471 | if (strcasecmp (arg, "yes") == 0) |
11472 | omit_lock_prefix = 1; | |
11473 | else if (strcasecmp (arg, "no") == 0) | |
11474 | omit_lock_prefix = 0; | |
11475 | else | |
11476 | as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg); | |
11477 | break; | |
11478 | ||
e4e00185 AS |
11479 | case OPTION_MFENCE_AS_LOCK_ADD: |
11480 | if (strcasecmp (arg, "yes") == 0) | |
11481 | avoid_fence = 1; | |
11482 | else if (strcasecmp (arg, "no") == 0) | |
11483 | avoid_fence = 0; | |
11484 | else | |
11485 | as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg); | |
11486 | break; | |
11487 | ||
0cb4071e L |
11488 | case OPTION_MRELAX_RELOCATIONS: |
11489 | if (strcasecmp (arg, "yes") == 0) | |
11490 | generate_relax_relocations = 1; | |
11491 | else if (strcasecmp (arg, "no") == 0) | |
11492 | generate_relax_relocations = 0; | |
11493 | else | |
11494 | as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg); | |
11495 | break; | |
11496 | ||
5db04b09 | 11497 | case OPTION_MAMD64: |
e89c5eaa | 11498 | intel64 = 0; |
5db04b09 L |
11499 | break; |
11500 | ||
11501 | case OPTION_MINTEL64: | |
e89c5eaa | 11502 | intel64 = 1; |
5db04b09 L |
11503 | break; |
11504 | ||
b6f8c7c4 L |
11505 | case 'O': |
11506 | if (arg == NULL) | |
11507 | { | |
11508 | optimize = 1; | |
11509 | /* Turn off -Os. */ | |
11510 | optimize_for_space = 0; | |
11511 | } | |
11512 | else if (*arg == 's') | |
11513 | { | |
11514 | optimize_for_space = 1; | |
11515 | /* Turn on all encoding optimizations. */ | |
41fd2579 | 11516 | optimize = INT_MAX; |
b6f8c7c4 L |
11517 | } |
11518 | else | |
11519 | { | |
11520 | optimize = atoi (arg); | |
11521 | /* Turn off -Os. */ | |
11522 | optimize_for_space = 0; | |
11523 | } | |
11524 | break; | |
11525 | ||
252b5132 RH |
11526 | default: |
11527 | return 0; | |
11528 | } | |
11529 | return 1; | |
11530 | } | |
11531 | ||
8a2c8fef L |
11532 | #define MESSAGE_TEMPLATE \ |
11533 | " " | |
11534 | ||
293f5f65 L |
11535 | static char * |
11536 | output_message (FILE *stream, char *p, char *message, char *start, | |
11537 | int *left_p, const char *name, int len) | |
11538 | { | |
11539 | int size = sizeof (MESSAGE_TEMPLATE); | |
11540 | int left = *left_p; | |
11541 | ||
11542 | /* Reserve 2 spaces for ", " or ",\0" */ | |
11543 | left -= len + 2; | |
11544 | ||
11545 | /* Check if there is any room. */ | |
11546 | if (left >= 0) | |
11547 | { | |
11548 | if (p != start) | |
11549 | { | |
11550 | *p++ = ','; | |
11551 | *p++ = ' '; | |
11552 | } | |
11553 | p = mempcpy (p, name, len); | |
11554 | } | |
11555 | else | |
11556 | { | |
11557 | /* Output the current message now and start a new one. */ | |
11558 | *p++ = ','; | |
11559 | *p = '\0'; | |
11560 | fprintf (stream, "%s\n", message); | |
11561 | p = start; | |
11562 | left = size - (start - message) - len - 2; | |
11563 | ||
11564 | gas_assert (left >= 0); | |
11565 | ||
11566 | p = mempcpy (p, name, len); | |
11567 | } | |
11568 | ||
11569 | *left_p = left; | |
11570 | return p; | |
11571 | } | |
11572 | ||
8a2c8fef | 11573 | static void |
1ded5609 | 11574 | show_arch (FILE *stream, int ext, int check) |
8a2c8fef L |
11575 | { |
11576 | static char message[] = MESSAGE_TEMPLATE; | |
11577 | char *start = message + 27; | |
11578 | char *p; | |
11579 | int size = sizeof (MESSAGE_TEMPLATE); | |
11580 | int left; | |
11581 | const char *name; | |
11582 | int len; | |
11583 | unsigned int j; | |
11584 | ||
11585 | p = start; | |
11586 | left = size - (start - message); | |
11587 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) | |
11588 | { | |
11589 | /* Should it be skipped? */ | |
11590 | if (cpu_arch [j].skip) | |
11591 | continue; | |
11592 | ||
11593 | name = cpu_arch [j].name; | |
11594 | len = cpu_arch [j].len; | |
11595 | if (*name == '.') | |
11596 | { | |
11597 | /* It is an extension. Skip if we aren't asked to show it. */ | |
11598 | if (ext) | |
11599 | { | |
11600 | name++; | |
11601 | len--; | |
11602 | } | |
11603 | else | |
11604 | continue; | |
11605 | } | |
11606 | else if (ext) | |
11607 | { | |
11608 | /* It is an processor. Skip if we show only extension. */ | |
11609 | continue; | |
11610 | } | |
1ded5609 JB |
11611 | else if (check && ! cpu_arch[j].flags.bitfield.cpui386) |
11612 | { | |
11613 | /* It is an impossible processor - skip. */ | |
11614 | continue; | |
11615 | } | |
8a2c8fef | 11616 | |
293f5f65 | 11617 | p = output_message (stream, p, message, start, &left, name, len); |
8a2c8fef L |
11618 | } |
11619 | ||
293f5f65 L |
11620 | /* Display disabled extensions. */ |
11621 | if (ext) | |
11622 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) | |
11623 | { | |
11624 | name = cpu_noarch [j].name; | |
11625 | len = cpu_noarch [j].len; | |
11626 | p = output_message (stream, p, message, start, &left, name, | |
11627 | len); | |
11628 | } | |
11629 | ||
8a2c8fef L |
11630 | *p = '\0'; |
11631 | fprintf (stream, "%s\n", message); | |
11632 | } | |
11633 | ||
252b5132 | 11634 | void |
8a2c8fef | 11635 | md_show_usage (FILE *stream) |
252b5132 | 11636 | { |
4cc782b5 ILT |
11637 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
11638 | fprintf (stream, _("\ | |
d4693039 | 11639 | -Qy, -Qn ignored\n\ |
a38cf1db | 11640 | -V print assembler version number\n\ |
b3b91714 AM |
11641 | -k ignored\n")); |
11642 | #endif | |
11643 | fprintf (stream, _("\ | |
12b55ccc | 11644 | -n Do not optimize code alignment\n\ |
b3b91714 AM |
11645 | -q quieten some warnings\n")); |
11646 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
11647 | fprintf (stream, _("\ | |
a38cf1db | 11648 | -s ignored\n")); |
b3b91714 | 11649 | #endif |
d7f449c0 L |
11650 | #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
11651 | || defined (TE_PE) || defined (TE_PEP)) | |
751d281c | 11652 | fprintf (stream, _("\ |
570561f7 | 11653 | --32/--64/--x32 generate 32bit/64bit/x32 code\n")); |
751d281c | 11654 | #endif |
b3b91714 AM |
11655 | #ifdef SVR4_COMMENT_CHARS |
11656 | fprintf (stream, _("\ | |
11657 | --divide do not treat `/' as a comment character\n")); | |
a38cf1db AM |
11658 | #else |
11659 | fprintf (stream, _("\ | |
b3b91714 | 11660 | --divide ignored\n")); |
4cc782b5 | 11661 | #endif |
9103f4f4 | 11662 | fprintf (stream, _("\ |
6305a203 | 11663 | -march=CPU[,+EXTENSION...]\n\ |
8a2c8fef | 11664 | generate code for CPU and EXTENSION, CPU is one of:\n")); |
1ded5609 | 11665 | show_arch (stream, 0, 1); |
8a2c8fef L |
11666 | fprintf (stream, _("\ |
11667 | EXTENSION is combination of:\n")); | |
1ded5609 | 11668 | show_arch (stream, 1, 0); |
6305a203 | 11669 | fprintf (stream, _("\ |
8a2c8fef | 11670 | -mtune=CPU optimize for CPU, CPU is one of:\n")); |
1ded5609 | 11671 | show_arch (stream, 0, 0); |
ba104c83 | 11672 | fprintf (stream, _("\ |
c0f3af97 L |
11673 | -msse2avx encode SSE instructions with VEX prefix\n")); |
11674 | fprintf (stream, _("\ | |
7c5c05ef | 11675 | -msse-check=[none|error|warning] (default: warning)\n\ |
daf50ae7 L |
11676 | check SSE instructions\n")); |
11677 | fprintf (stream, _("\ | |
7c5c05ef | 11678 | -moperand-check=[none|error|warning] (default: warning)\n\ |
7bab8ab5 JB |
11679 | check operand combinations for validity\n")); |
11680 | fprintf (stream, _("\ | |
7c5c05ef L |
11681 | -mavxscalar=[128|256] (default: 128)\n\ |
11682 | encode scalar AVX instructions with specific vector\n\ | |
539f890d L |
11683 | length\n")); |
11684 | fprintf (stream, _("\ | |
03751133 L |
11685 | -mvexwig=[0|1] (default: 0)\n\ |
11686 | encode VEX instructions with specific VEX.W value\n\ | |
11687 | for VEX.W bit ignored instructions\n")); | |
11688 | fprintf (stream, _("\ | |
7c5c05ef L |
11689 | -mevexlig=[128|256|512] (default: 128)\n\ |
11690 | encode scalar EVEX instructions with specific vector\n\ | |
43234a1e L |
11691 | length\n")); |
11692 | fprintf (stream, _("\ | |
7c5c05ef L |
11693 | -mevexwig=[0|1] (default: 0)\n\ |
11694 | encode EVEX instructions with specific EVEX.W value\n\ | |
43234a1e L |
11695 | for EVEX.W bit ignored instructions\n")); |
11696 | fprintf (stream, _("\ | |
7c5c05ef | 11697 | -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\ |
d3d3c6db IT |
11698 | encode EVEX instructions with specific EVEX.RC value\n\ |
11699 | for SAE-only ignored instructions\n")); | |
11700 | fprintf (stream, _("\ | |
7c5c05ef L |
11701 | -mmnemonic=[att|intel] ")); |
11702 | if (SYSV386_COMPAT) | |
11703 | fprintf (stream, _("(default: att)\n")); | |
11704 | else | |
11705 | fprintf (stream, _("(default: intel)\n")); | |
11706 | fprintf (stream, _("\ | |
11707 | use AT&T/Intel mnemonic\n")); | |
ba104c83 | 11708 | fprintf (stream, _("\ |
7c5c05ef L |
11709 | -msyntax=[att|intel] (default: att)\n\ |
11710 | use AT&T/Intel syntax\n")); | |
ba104c83 L |
11711 | fprintf (stream, _("\ |
11712 | -mindex-reg support pseudo index registers\n")); | |
11713 | fprintf (stream, _("\ | |
11714 | -mnaked-reg don't require `%%' prefix for registers\n")); | |
11715 | fprintf (stream, _("\ | |
7e8b059b | 11716 | -madd-bnd-prefix add BND prefix for all valid branches\n")); |
b4a3a7b4 | 11717 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8dcea932 L |
11718 | fprintf (stream, _("\ |
11719 | -mshared disable branch optimization for shared code\n")); | |
b4a3a7b4 L |
11720 | fprintf (stream, _("\ |
11721 | -mx86-used-note=[no|yes] ")); | |
11722 | if (DEFAULT_X86_USED_NOTE) | |
11723 | fprintf (stream, _("(default: yes)\n")); | |
11724 | else | |
11725 | fprintf (stream, _("(default: no)\n")); | |
11726 | fprintf (stream, _("\ | |
11727 | generate x86 used ISA and feature properties\n")); | |
11728 | #endif | |
11729 | #if defined (TE_PE) || defined (TE_PEP) | |
167ad85b TG |
11730 | fprintf (stream, _("\ |
11731 | -mbig-obj generate big object files\n")); | |
11732 | #endif | |
d022bddd | 11733 | fprintf (stream, _("\ |
7c5c05ef | 11734 | -momit-lock-prefix=[no|yes] (default: no)\n\ |
d022bddd | 11735 | strip all lock prefixes\n")); |
5db04b09 | 11736 | fprintf (stream, _("\ |
7c5c05ef | 11737 | -mfence-as-lock-add=[no|yes] (default: no)\n\ |
e4e00185 AS |
11738 | encode lfence, mfence and sfence as\n\ |
11739 | lock addl $0x0, (%%{re}sp)\n")); | |
11740 | fprintf (stream, _("\ | |
7c5c05ef L |
11741 | -mrelax-relocations=[no|yes] ")); |
11742 | if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS) | |
11743 | fprintf (stream, _("(default: yes)\n")); | |
11744 | else | |
11745 | fprintf (stream, _("(default: no)\n")); | |
11746 | fprintf (stream, _("\ | |
0cb4071e L |
11747 | generate relax relocations\n")); |
11748 | fprintf (stream, _("\ | |
7c5c05ef | 11749 | -mamd64 accept only AMD64 ISA [default]\n")); |
5db04b09 L |
11750 | fprintf (stream, _("\ |
11751 | -mintel64 accept only Intel64 ISA\n")); | |
252b5132 RH |
11752 | } |
11753 | ||
3e73aa7c | 11754 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
321098a5 | 11755 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
e57f8c65 | 11756 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
252b5132 RH |
11757 | |
11758 | /* Pick the target format to use. */ | |
11759 | ||
47926f60 | 11760 | const char * |
e3bb37b5 | 11761 | i386_target_format (void) |
252b5132 | 11762 | { |
351f65ca L |
11763 | if (!strncmp (default_arch, "x86_64", 6)) |
11764 | { | |
11765 | update_code_flag (CODE_64BIT, 1); | |
11766 | if (default_arch[6] == '\0') | |
7f56bc95 | 11767 | x86_elf_abi = X86_64_ABI; |
351f65ca | 11768 | else |
7f56bc95 | 11769 | x86_elf_abi = X86_64_X32_ABI; |
351f65ca | 11770 | } |
3e73aa7c | 11771 | else if (!strcmp (default_arch, "i386")) |
78f12dd3 | 11772 | update_code_flag (CODE_32BIT, 1); |
5197d474 L |
11773 | else if (!strcmp (default_arch, "iamcu")) |
11774 | { | |
11775 | update_code_flag (CODE_32BIT, 1); | |
11776 | if (cpu_arch_isa == PROCESSOR_UNKNOWN) | |
11777 | { | |
11778 | static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS; | |
11779 | cpu_arch_name = "iamcu"; | |
11780 | cpu_sub_arch_name = NULL; | |
11781 | cpu_arch_flags = iamcu_flags; | |
11782 | cpu_arch_isa = PROCESSOR_IAMCU; | |
11783 | cpu_arch_isa_flags = iamcu_flags; | |
11784 | if (!cpu_arch_tune_set) | |
11785 | { | |
11786 | cpu_arch_tune = cpu_arch_isa; | |
11787 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
11788 | } | |
11789 | } | |
8d471ec1 | 11790 | else if (cpu_arch_isa != PROCESSOR_IAMCU) |
5197d474 L |
11791 | as_fatal (_("Intel MCU doesn't support `%s' architecture"), |
11792 | cpu_arch_name); | |
11793 | } | |
3e73aa7c | 11794 | else |
2b5d6a91 | 11795 | as_fatal (_("unknown architecture")); |
89507696 JB |
11796 | |
11797 | if (cpu_flags_all_zero (&cpu_arch_isa_flags)) | |
11798 | cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
11799 | if (cpu_flags_all_zero (&cpu_arch_tune_flags)) | |
11800 | cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
11801 | ||
252b5132 RH |
11802 | switch (OUTPUT_FLAVOR) |
11803 | { | |
9384f2ff | 11804 | #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT) |
4c63da97 | 11805 | case bfd_target_aout_flavour: |
47926f60 | 11806 | return AOUT_TARGET_FORMAT; |
4c63da97 | 11807 | #endif |
9384f2ff AM |
11808 | #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF) |
11809 | # if defined (TE_PE) || defined (TE_PEP) | |
11810 | case bfd_target_coff_flavour: | |
167ad85b TG |
11811 | if (flag_code == CODE_64BIT) |
11812 | return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64"; | |
11813 | else | |
11814 | return "pe-i386"; | |
9384f2ff | 11815 | # elif defined (TE_GO32) |
0561d57c JK |
11816 | case bfd_target_coff_flavour: |
11817 | return "coff-go32"; | |
9384f2ff | 11818 | # else |
252b5132 RH |
11819 | case bfd_target_coff_flavour: |
11820 | return "coff-i386"; | |
9384f2ff | 11821 | # endif |
4c63da97 | 11822 | #endif |
3e73aa7c | 11823 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 11824 | case bfd_target_elf_flavour: |
3e73aa7c | 11825 | { |
351f65ca L |
11826 | const char *format; |
11827 | ||
11828 | switch (x86_elf_abi) | |
4fa24527 | 11829 | { |
351f65ca L |
11830 | default: |
11831 | format = ELF_TARGET_FORMAT; | |
11832 | break; | |
7f56bc95 | 11833 | case X86_64_ABI: |
351f65ca | 11834 | use_rela_relocations = 1; |
4fa24527 | 11835 | object_64bit = 1; |
351f65ca L |
11836 | format = ELF_TARGET_FORMAT64; |
11837 | break; | |
7f56bc95 | 11838 | case X86_64_X32_ABI: |
4fa24527 | 11839 | use_rela_relocations = 1; |
351f65ca | 11840 | object_64bit = 1; |
862be3fb | 11841 | disallow_64bit_reloc = 1; |
351f65ca L |
11842 | format = ELF_TARGET_FORMAT32; |
11843 | break; | |
4fa24527 | 11844 | } |
3632d14b | 11845 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 11846 | { |
7f56bc95 | 11847 | if (x86_elf_abi != X86_64_ABI) |
8a9036a4 L |
11848 | as_fatal (_("Intel L1OM is 64bit only")); |
11849 | return ELF_TARGET_L1OM_FORMAT; | |
11850 | } | |
b49f93f6 | 11851 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
7a9068fe L |
11852 | { |
11853 | if (x86_elf_abi != X86_64_ABI) | |
11854 | as_fatal (_("Intel K1OM is 64bit only")); | |
11855 | return ELF_TARGET_K1OM_FORMAT; | |
11856 | } | |
81486035 L |
11857 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
11858 | { | |
11859 | if (x86_elf_abi != I386_ABI) | |
11860 | as_fatal (_("Intel MCU is 32bit only")); | |
11861 | return ELF_TARGET_IAMCU_FORMAT; | |
11862 | } | |
8a9036a4 | 11863 | else |
351f65ca | 11864 | return format; |
3e73aa7c | 11865 | } |
e57f8c65 TG |
11866 | #endif |
11867 | #if defined (OBJ_MACH_O) | |
11868 | case bfd_target_mach_o_flavour: | |
d382c579 TG |
11869 | if (flag_code == CODE_64BIT) |
11870 | { | |
11871 | use_rela_relocations = 1; | |
11872 | object_64bit = 1; | |
11873 | return "mach-o-x86-64"; | |
11874 | } | |
11875 | else | |
11876 | return "mach-o-i386"; | |
4c63da97 | 11877 | #endif |
252b5132 RH |
11878 | default: |
11879 | abort (); | |
11880 | return NULL; | |
11881 | } | |
11882 | } | |
11883 | ||
47926f60 | 11884 | #endif /* OBJ_MAYBE_ more than one */ |
252b5132 | 11885 | \f |
252b5132 | 11886 | symbolS * |
7016a5d5 | 11887 | md_undefined_symbol (char *name) |
252b5132 | 11888 | { |
18dc2407 ILT |
11889 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
11890 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
11891 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
11892 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
11893 | { |
11894 | if (!GOT_symbol) | |
11895 | { | |
11896 | if (symbol_find (name)) | |
11897 | as_bad (_("GOT already in symbol table")); | |
11898 | GOT_symbol = symbol_new (name, undefined_section, | |
11899 | (valueT) 0, &zero_address_frag); | |
11900 | }; | |
11901 | return GOT_symbol; | |
11902 | } | |
252b5132 RH |
11903 | return 0; |
11904 | } | |
11905 | ||
11906 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 11907 | |
252b5132 | 11908 | valueT |
7016a5d5 | 11909 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
252b5132 | 11910 | { |
4c63da97 AM |
11911 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
11912 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
11913 | { | |
11914 | /* For a.out, force the section size to be aligned. If we don't do | |
11915 | this, BFD will align it for us, but it will not write out the | |
11916 | final bytes of the section. This may be a bug in BFD, but it is | |
11917 | easier to fix it here since that is how the other a.out targets | |
11918 | work. */ | |
11919 | int align; | |
11920 | ||
fd361982 | 11921 | align = bfd_section_alignment (segment); |
8d3842cd | 11922 | size = ((size + (1 << align) - 1) & (-((valueT) 1 << align))); |
4c63da97 | 11923 | } |
252b5132 RH |
11924 | #endif |
11925 | ||
11926 | return size; | |
11927 | } | |
11928 | ||
11929 | /* On the i386, PC-relative offsets are relative to the start of the | |
11930 | next instruction. That is, the address of the offset, plus its | |
11931 | size, since the offset is always the last part of the insn. */ | |
11932 | ||
11933 | long | |
e3bb37b5 | 11934 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
11935 | { |
11936 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
11937 | } | |
11938 | ||
11939 | #ifndef I386COFF | |
11940 | ||
11941 | static void | |
e3bb37b5 | 11942 | s_bss (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 11943 | { |
29b0f896 | 11944 | int temp; |
252b5132 | 11945 | |
8a75718c JB |
11946 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
11947 | if (IS_ELF) | |
11948 | obj_elf_section_change_hook (); | |
11949 | #endif | |
252b5132 RH |
11950 | temp = get_absolute_expression (); |
11951 | subseg_set (bss_section, (subsegT) temp); | |
11952 | demand_empty_rest_of_line (); | |
11953 | } | |
11954 | ||
11955 | #endif | |
11956 | ||
252b5132 | 11957 | void |
e3bb37b5 | 11958 | i386_validate_fix (fixS *fixp) |
252b5132 | 11959 | { |
02a86693 | 11960 | if (fixp->fx_subsy) |
252b5132 | 11961 | { |
02a86693 | 11962 | if (fixp->fx_subsy == GOT_symbol) |
23df1078 | 11963 | { |
02a86693 L |
11964 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
11965 | { | |
11966 | if (!object_64bit) | |
11967 | abort (); | |
11968 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
11969 | if (fixp->fx_tcbit2) | |
56ceb5b5 L |
11970 | fixp->fx_r_type = (fixp->fx_tcbit |
11971 | ? BFD_RELOC_X86_64_REX_GOTPCRELX | |
11972 | : BFD_RELOC_X86_64_GOTPCRELX); | |
02a86693 L |
11973 | else |
11974 | #endif | |
11975 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
11976 | } | |
d6ab8113 | 11977 | else |
02a86693 L |
11978 | { |
11979 | if (!object_64bit) | |
11980 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
11981 | else | |
11982 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; | |
11983 | } | |
11984 | fixp->fx_subsy = 0; | |
23df1078 | 11985 | } |
252b5132 | 11986 | } |
02a86693 L |
11987 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
11988 | else if (!object_64bit) | |
11989 | { | |
11990 | if (fixp->fx_r_type == BFD_RELOC_386_GOT32 | |
11991 | && fixp->fx_tcbit2) | |
11992 | fixp->fx_r_type = BFD_RELOC_386_GOT32X; | |
11993 | } | |
11994 | #endif | |
252b5132 RH |
11995 | } |
11996 | ||
252b5132 | 11997 | arelent * |
7016a5d5 | 11998 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
11999 | { |
12000 | arelent *rel; | |
12001 | bfd_reloc_code_real_type code; | |
12002 | ||
12003 | switch (fixp->fx_r_type) | |
12004 | { | |
8ce3d284 | 12005 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
12006 | case BFD_RELOC_SIZE32: |
12007 | case BFD_RELOC_SIZE64: | |
12008 | if (S_IS_DEFINED (fixp->fx_addsy) | |
12009 | && !S_IS_EXTERNAL (fixp->fx_addsy)) | |
12010 | { | |
12011 | /* Resolve size relocation against local symbol to size of | |
12012 | the symbol plus addend. */ | |
12013 | valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset; | |
12014 | if (fixp->fx_r_type == BFD_RELOC_SIZE32 | |
12015 | && !fits_in_unsigned_long (value)) | |
12016 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
12017 | _("symbol size computation overflow")); | |
12018 | fixp->fx_addsy = NULL; | |
12019 | fixp->fx_subsy = NULL; | |
12020 | md_apply_fix (fixp, (valueT *) &value, NULL); | |
12021 | return NULL; | |
12022 | } | |
8ce3d284 | 12023 | #endif |
1a0670f3 | 12024 | /* Fall through. */ |
8fd4256d | 12025 | |
3e73aa7c JH |
12026 | case BFD_RELOC_X86_64_PLT32: |
12027 | case BFD_RELOC_X86_64_GOT32: | |
12028 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
12029 | case BFD_RELOC_X86_64_GOTPCRELX: |
12030 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
252b5132 RH |
12031 | case BFD_RELOC_386_PLT32: |
12032 | case BFD_RELOC_386_GOT32: | |
02a86693 | 12033 | case BFD_RELOC_386_GOT32X: |
252b5132 RH |
12034 | case BFD_RELOC_386_GOTOFF: |
12035 | case BFD_RELOC_386_GOTPC: | |
13ae64f3 JJ |
12036 | case BFD_RELOC_386_TLS_GD: |
12037 | case BFD_RELOC_386_TLS_LDM: | |
12038 | case BFD_RELOC_386_TLS_LDO_32: | |
12039 | case BFD_RELOC_386_TLS_IE_32: | |
37e55690 JJ |
12040 | case BFD_RELOC_386_TLS_IE: |
12041 | case BFD_RELOC_386_TLS_GOTIE: | |
13ae64f3 JJ |
12042 | case BFD_RELOC_386_TLS_LE_32: |
12043 | case BFD_RELOC_386_TLS_LE: | |
67a4f2b7 AO |
12044 | case BFD_RELOC_386_TLS_GOTDESC: |
12045 | case BFD_RELOC_386_TLS_DESC_CALL: | |
bffbf940 JJ |
12046 | case BFD_RELOC_X86_64_TLSGD: |
12047 | case BFD_RELOC_X86_64_TLSLD: | |
12048 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 12049 | case BFD_RELOC_X86_64_DTPOFF64: |
bffbf940 JJ |
12050 | case BFD_RELOC_X86_64_GOTTPOFF: |
12051 | case BFD_RELOC_X86_64_TPOFF32: | |
d6ab8113 JB |
12052 | case BFD_RELOC_X86_64_TPOFF64: |
12053 | case BFD_RELOC_X86_64_GOTOFF64: | |
12054 | case BFD_RELOC_X86_64_GOTPC32: | |
7b81dfbb AJ |
12055 | case BFD_RELOC_X86_64_GOT64: |
12056 | case BFD_RELOC_X86_64_GOTPCREL64: | |
12057 | case BFD_RELOC_X86_64_GOTPC64: | |
12058 | case BFD_RELOC_X86_64_GOTPLT64: | |
12059 | case BFD_RELOC_X86_64_PLTOFF64: | |
67a4f2b7 AO |
12060 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
12061 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
252b5132 RH |
12062 | case BFD_RELOC_RVA: |
12063 | case BFD_RELOC_VTABLE_ENTRY: | |
12064 | case BFD_RELOC_VTABLE_INHERIT: | |
6482c264 NC |
12065 | #ifdef TE_PE |
12066 | case BFD_RELOC_32_SECREL: | |
12067 | #endif | |
252b5132 RH |
12068 | code = fixp->fx_r_type; |
12069 | break; | |
dbbaec26 L |
12070 | case BFD_RELOC_X86_64_32S: |
12071 | if (!fixp->fx_pcrel) | |
12072 | { | |
12073 | /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ | |
12074 | code = fixp->fx_r_type; | |
12075 | break; | |
12076 | } | |
1a0670f3 | 12077 | /* Fall through. */ |
252b5132 | 12078 | default: |
93382f6d | 12079 | if (fixp->fx_pcrel) |
252b5132 | 12080 | { |
93382f6d AM |
12081 | switch (fixp->fx_size) |
12082 | { | |
12083 | default: | |
b091f402 AM |
12084 | as_bad_where (fixp->fx_file, fixp->fx_line, |
12085 | _("can not do %d byte pc-relative relocation"), | |
12086 | fixp->fx_size); | |
93382f6d AM |
12087 | code = BFD_RELOC_32_PCREL; |
12088 | break; | |
12089 | case 1: code = BFD_RELOC_8_PCREL; break; | |
12090 | case 2: code = BFD_RELOC_16_PCREL; break; | |
d258b828 | 12091 | case 4: code = BFD_RELOC_32_PCREL; break; |
d6ab8113 JB |
12092 | #ifdef BFD64 |
12093 | case 8: code = BFD_RELOC_64_PCREL; break; | |
12094 | #endif | |
93382f6d AM |
12095 | } |
12096 | } | |
12097 | else | |
12098 | { | |
12099 | switch (fixp->fx_size) | |
12100 | { | |
12101 | default: | |
b091f402 AM |
12102 | as_bad_where (fixp->fx_file, fixp->fx_line, |
12103 | _("can not do %d byte relocation"), | |
12104 | fixp->fx_size); | |
93382f6d AM |
12105 | code = BFD_RELOC_32; |
12106 | break; | |
12107 | case 1: code = BFD_RELOC_8; break; | |
12108 | case 2: code = BFD_RELOC_16; break; | |
12109 | case 4: code = BFD_RELOC_32; break; | |
937149dd | 12110 | #ifdef BFD64 |
3e73aa7c | 12111 | case 8: code = BFD_RELOC_64; break; |
937149dd | 12112 | #endif |
93382f6d | 12113 | } |
252b5132 RH |
12114 | } |
12115 | break; | |
12116 | } | |
252b5132 | 12117 | |
d182319b JB |
12118 | if ((code == BFD_RELOC_32 |
12119 | || code == BFD_RELOC_32_PCREL | |
12120 | || code == BFD_RELOC_X86_64_32S) | |
252b5132 RH |
12121 | && GOT_symbol |
12122 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c | 12123 | { |
4fa24527 | 12124 | if (!object_64bit) |
d6ab8113 JB |
12125 | code = BFD_RELOC_386_GOTPC; |
12126 | else | |
12127 | code = BFD_RELOC_X86_64_GOTPC32; | |
3e73aa7c | 12128 | } |
7b81dfbb AJ |
12129 | if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) |
12130 | && GOT_symbol | |
12131 | && fixp->fx_addsy == GOT_symbol) | |
12132 | { | |
12133 | code = BFD_RELOC_X86_64_GOTPC64; | |
12134 | } | |
252b5132 | 12135 | |
add39d23 TS |
12136 | rel = XNEW (arelent); |
12137 | rel->sym_ptr_ptr = XNEW (asymbol *); | |
49309057 | 12138 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
12139 | |
12140 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
c87db184 | 12141 | |
3e73aa7c JH |
12142 | if (!use_rela_relocations) |
12143 | { | |
12144 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
12145 | vtable entry to be used in the relocation's section offset. */ | |
12146 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
12147 | rel->address = fixp->fx_offset; | |
fbeb56a4 DK |
12148 | #if defined (OBJ_COFF) && defined (TE_PE) |
12149 | else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy)) | |
12150 | rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2); | |
12151 | else | |
12152 | #endif | |
c6682705 | 12153 | rel->addend = 0; |
3e73aa7c JH |
12154 | } |
12155 | /* Use the rela in 64bit mode. */ | |
252b5132 | 12156 | else |
3e73aa7c | 12157 | { |
862be3fb L |
12158 | if (disallow_64bit_reloc) |
12159 | switch (code) | |
12160 | { | |
862be3fb L |
12161 | case BFD_RELOC_X86_64_DTPOFF64: |
12162 | case BFD_RELOC_X86_64_TPOFF64: | |
12163 | case BFD_RELOC_64_PCREL: | |
12164 | case BFD_RELOC_X86_64_GOTOFF64: | |
12165 | case BFD_RELOC_X86_64_GOT64: | |
12166 | case BFD_RELOC_X86_64_GOTPCREL64: | |
12167 | case BFD_RELOC_X86_64_GOTPC64: | |
12168 | case BFD_RELOC_X86_64_GOTPLT64: | |
12169 | case BFD_RELOC_X86_64_PLTOFF64: | |
12170 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
12171 | _("cannot represent relocation type %s in x32 mode"), | |
12172 | bfd_get_reloc_code_name (code)); | |
12173 | break; | |
12174 | default: | |
12175 | break; | |
12176 | } | |
12177 | ||
062cd5e7 AS |
12178 | if (!fixp->fx_pcrel) |
12179 | rel->addend = fixp->fx_offset; | |
12180 | else | |
12181 | switch (code) | |
12182 | { | |
12183 | case BFD_RELOC_X86_64_PLT32: | |
12184 | case BFD_RELOC_X86_64_GOT32: | |
12185 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
12186 | case BFD_RELOC_X86_64_GOTPCRELX: |
12187 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
bffbf940 JJ |
12188 | case BFD_RELOC_X86_64_TLSGD: |
12189 | case BFD_RELOC_X86_64_TLSLD: | |
12190 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 AO |
12191 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
12192 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
062cd5e7 AS |
12193 | rel->addend = fixp->fx_offset - fixp->fx_size; |
12194 | break; | |
12195 | default: | |
12196 | rel->addend = (section->vma | |
12197 | - fixp->fx_size | |
12198 | + fixp->fx_addnumber | |
12199 | + md_pcrel_from (fixp)); | |
12200 | break; | |
12201 | } | |
3e73aa7c JH |
12202 | } |
12203 | ||
252b5132 RH |
12204 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
12205 | if (rel->howto == NULL) | |
12206 | { | |
12207 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 12208 | _("cannot represent relocation type %s"), |
252b5132 RH |
12209 | bfd_get_reloc_code_name (code)); |
12210 | /* Set howto to a garbage value so that we can keep going. */ | |
12211 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
9c2799c2 | 12212 | gas_assert (rel->howto != NULL); |
252b5132 RH |
12213 | } |
12214 | ||
12215 | return rel; | |
12216 | } | |
12217 | ||
ee86248c | 12218 | #include "tc-i386-intel.c" |
54cfded0 | 12219 | |
a60de03c JB |
12220 | void |
12221 | tc_x86_parse_to_dw2regnum (expressionS *exp) | |
54cfded0 | 12222 | { |
a60de03c JB |
12223 | int saved_naked_reg; |
12224 | char saved_register_dot; | |
54cfded0 | 12225 | |
a60de03c JB |
12226 | saved_naked_reg = allow_naked_reg; |
12227 | allow_naked_reg = 1; | |
12228 | saved_register_dot = register_chars['.']; | |
12229 | register_chars['.'] = '.'; | |
12230 | allow_pseudo_reg = 1; | |
12231 | expression_and_evaluate (exp); | |
12232 | allow_pseudo_reg = 0; | |
12233 | register_chars['.'] = saved_register_dot; | |
12234 | allow_naked_reg = saved_naked_reg; | |
12235 | ||
e96d56a1 | 12236 | if (exp->X_op == O_register && exp->X_add_number >= 0) |
54cfded0 | 12237 | { |
a60de03c JB |
12238 | if ((addressT) exp->X_add_number < i386_regtab_size) |
12239 | { | |
12240 | exp->X_op = O_constant; | |
12241 | exp->X_add_number = i386_regtab[exp->X_add_number] | |
12242 | .dw2_regnum[flag_code >> 1]; | |
12243 | } | |
12244 | else | |
12245 | exp->X_op = O_illegal; | |
54cfded0 | 12246 | } |
54cfded0 AM |
12247 | } |
12248 | ||
12249 | void | |
12250 | tc_x86_frame_initial_instructions (void) | |
12251 | { | |
a60de03c JB |
12252 | static unsigned int sp_regno[2]; |
12253 | ||
12254 | if (!sp_regno[flag_code >> 1]) | |
12255 | { | |
12256 | char *saved_input = input_line_pointer; | |
12257 | char sp[][4] = {"esp", "rsp"}; | |
12258 | expressionS exp; | |
a4447b93 | 12259 | |
a60de03c JB |
12260 | input_line_pointer = sp[flag_code >> 1]; |
12261 | tc_x86_parse_to_dw2regnum (&exp); | |
9c2799c2 | 12262 | gas_assert (exp.X_op == O_constant); |
a60de03c JB |
12263 | sp_regno[flag_code >> 1] = exp.X_add_number; |
12264 | input_line_pointer = saved_input; | |
12265 | } | |
a4447b93 | 12266 | |
61ff971f L |
12267 | cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment); |
12268 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); | |
54cfded0 | 12269 | } |
d2b2c203 | 12270 | |
d7921315 L |
12271 | int |
12272 | x86_dwarf2_addr_size (void) | |
12273 | { | |
12274 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) | |
12275 | if (x86_elf_abi == X86_64_X32_ABI) | |
12276 | return 4; | |
12277 | #endif | |
12278 | return bfd_arch_bits_per_address (stdoutput) / 8; | |
12279 | } | |
12280 | ||
d2b2c203 DJ |
12281 | int |
12282 | i386_elf_section_type (const char *str, size_t len) | |
12283 | { | |
12284 | if (flag_code == CODE_64BIT | |
12285 | && len == sizeof ("unwind") - 1 | |
12286 | && strncmp (str, "unwind", 6) == 0) | |
12287 | return SHT_X86_64_UNWIND; | |
12288 | ||
12289 | return -1; | |
12290 | } | |
bb41ade5 | 12291 | |
ad5fec3b EB |
12292 | #ifdef TE_SOLARIS |
12293 | void | |
12294 | i386_solaris_fix_up_eh_frame (segT sec) | |
12295 | { | |
12296 | if (flag_code == CODE_64BIT) | |
12297 | elf_section_type (sec) = SHT_X86_64_UNWIND; | |
12298 | } | |
12299 | #endif | |
12300 | ||
bb41ade5 AM |
12301 | #ifdef TE_PE |
12302 | void | |
12303 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) | |
12304 | { | |
91d6fa6a | 12305 | expressionS exp; |
bb41ade5 | 12306 | |
91d6fa6a NC |
12307 | exp.X_op = O_secrel; |
12308 | exp.X_add_symbol = symbol; | |
12309 | exp.X_add_number = 0; | |
12310 | emit_expr (&exp, size); | |
bb41ade5 AM |
12311 | } |
12312 | #endif | |
3b22753a L |
12313 | |
12314 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
12315 | /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ | |
12316 | ||
01e1a5bc | 12317 | bfd_vma |
6d4af3c2 | 12318 | x86_64_section_letter (int letter, const char **ptr_msg) |
3b22753a L |
12319 | { |
12320 | if (flag_code == CODE_64BIT) | |
12321 | { | |
12322 | if (letter == 'l') | |
12323 | return SHF_X86_64_LARGE; | |
12324 | ||
8f3bae45 | 12325 | *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string"); |
64e74474 | 12326 | } |
3b22753a | 12327 | else |
8f3bae45 | 12328 | *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string"); |
3b22753a L |
12329 | return -1; |
12330 | } | |
12331 | ||
01e1a5bc | 12332 | bfd_vma |
3b22753a L |
12333 | x86_64_section_word (char *str, size_t len) |
12334 | { | |
8620418b | 12335 | if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large")) |
3b22753a L |
12336 | return SHF_X86_64_LARGE; |
12337 | ||
12338 | return -1; | |
12339 | } | |
12340 | ||
12341 | static void | |
12342 | handle_large_common (int small ATTRIBUTE_UNUSED) | |
12343 | { | |
12344 | if (flag_code != CODE_64BIT) | |
12345 | { | |
12346 | s_comm_internal (0, elf_common_parse); | |
12347 | as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); | |
12348 | } | |
12349 | else | |
12350 | { | |
12351 | static segT lbss_section; | |
12352 | asection *saved_com_section_ptr = elf_com_section_ptr; | |
12353 | asection *saved_bss_section = bss_section; | |
12354 | ||
12355 | if (lbss_section == NULL) | |
12356 | { | |
12357 | flagword applicable; | |
12358 | segT seg = now_seg; | |
12359 | subsegT subseg = now_subseg; | |
12360 | ||
12361 | /* The .lbss section is for local .largecomm symbols. */ | |
12362 | lbss_section = subseg_new (".lbss", 0); | |
12363 | applicable = bfd_applicable_section_flags (stdoutput); | |
fd361982 | 12364 | bfd_set_section_flags (lbss_section, applicable & SEC_ALLOC); |
3b22753a L |
12365 | seg_info (lbss_section)->bss = 1; |
12366 | ||
12367 | subseg_set (seg, subseg); | |
12368 | } | |
12369 | ||
12370 | elf_com_section_ptr = &_bfd_elf_large_com_section; | |
12371 | bss_section = lbss_section; | |
12372 | ||
12373 | s_comm_internal (0, elf_common_parse); | |
12374 | ||
12375 | elf_com_section_ptr = saved_com_section_ptr; | |
12376 | bss_section = saved_bss_section; | |
12377 | } | |
12378 | } | |
12379 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |