Commit | Line | Data |
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fecd2382 | 1 | /* i386.c -- Assemble code for the Intel 80386 |
dddc8a82 ILT |
2 | Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 1998 |
3 | Free Software Foundation. | |
355afbcd | 4 | |
a39116f1 | 5 | This file is part of GAS, the GNU Assembler. |
355afbcd | 6 | |
a39116f1 RP |
7 | GAS is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
355afbcd | 11 | |
a39116f1 RP |
12 | GAS is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
355afbcd | 16 | |
a39116f1 | 17 | You should have received a copy of the GNU General Public License |
e592f0e6 ILT |
18 | along with GAS; see the file COPYING. If not, write to the Free |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
20 | 02111-1307, USA. */ | |
fecd2382 | 21 | |
fecd2382 RP |
22 | /* |
23 | Intel 80386 machine specific gas. | |
24 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
25 | Bugs & suggestions are completely welcome. This is free software. | |
26 | Please help us make it better. | |
a39116f1 | 27 | */ |
fecd2382 | 28 | |
4b77b129 ILT |
29 | #include <ctype.h> |
30 | ||
fecd2382 | 31 | #include "as.h" |
0877841d | 32 | #include "subsegs.h" |
fecd2382 RP |
33 | |
34 | #include "obstack.h" | |
a39116f1 | 35 | #include "opcode/i386.h" |
fecd2382 | 36 | |
f0b37b4a KR |
37 | #ifndef TC_RELOC |
38 | #define TC_RELOC(X,Y) (Y) | |
39 | #endif | |
40 | ||
f59fb6ca ILT |
41 | static unsigned long mode_from_disp_size PARAMS ((unsigned long)); |
42 | static int fits_in_signed_byte PARAMS ((long)); | |
43 | static int fits_in_unsigned_byte PARAMS ((long)); | |
44 | static int fits_in_unsigned_word PARAMS ((long)); | |
45 | static int fits_in_signed_word PARAMS ((long)); | |
46 | static int smallest_imm_type PARAMS ((long)); | |
4498e3d6 | 47 | static int check_prefix PARAMS ((int)); |
f59fb6ca ILT |
48 | static void set_16bit_code_flag PARAMS ((int)); |
49 | #ifdef BFD_ASSEMBLER | |
50 | static bfd_reloc_code_real_type reloc | |
51 | PARAMS ((int, int, bfd_reloc_code_real_type)); | |
52 | #endif | |
53 | ||
fecd2382 RP |
54 | /* 'md_assemble ()' gathers together information and puts it into a |
55 | i386_insn. */ | |
56 | ||
3c8df4ba | 57 | struct _i386_insn |
355afbcd KR |
58 | { |
59 | /* TM holds the template for the insn were currently assembling. */ | |
60 | template tm; | |
61 | /* SUFFIX holds the opcode suffix (e.g. 'l' for 'movl') if given. */ | |
62 | char suffix; | |
63 | /* Operands are coded with OPERANDS, TYPES, DISPS, IMMS, and REGS. */ | |
64 | ||
65 | /* OPERANDS gives the number of given operands. */ | |
66 | unsigned int operands; | |
67 | ||
49864cfa KR |
68 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number |
69 | of given register, displacement, memory operands and immediate | |
70 | operands. */ | |
355afbcd KR |
71 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
72 | ||
73 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
49864cfa KR |
74 | search through DISPS [i] & IMMS [i] & REGS [i] for the required |
75 | operand. */ | |
355afbcd KR |
76 | unsigned int types[MAX_OPERANDS]; |
77 | ||
78 | /* Displacements (if given) for each operand. */ | |
79 | expressionS *disps[MAX_OPERANDS]; | |
80 | ||
f0b37b4a KR |
81 | /* Relocation type for operand */ |
82 | #ifdef BFD_ASSEMBLER | |
83 | enum bfd_reloc_code_real disp_reloc[MAX_OPERANDS]; | |
84 | #else | |
85 | int disp_reloc[MAX_OPERANDS]; | |
86 | #endif | |
87 | ||
355afbcd KR |
88 | /* Immediate operands (if given) for each operand. */ |
89 | expressionS *imms[MAX_OPERANDS]; | |
90 | ||
91 | /* Register operands (if given) for each operand. */ | |
92 | reg_entry *regs[MAX_OPERANDS]; | |
93 | ||
94 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode | |
49864cfa | 95 | the base index byte below. */ |
355afbcd KR |
96 | reg_entry *base_reg; |
97 | reg_entry *index_reg; | |
98 | unsigned int log2_scale_factor; | |
99 | ||
4498e3d6 ILT |
100 | /* SEG gives the seg_entries of this insn. They are zero unless |
101 | explicit segment overrides are given. */ | |
102 | const seg_entry *seg[2]; /* segments for memory operands (if given) */ | |
355afbcd KR |
103 | |
104 | /* PREFIX holds all the given prefix opcodes (usually null). | |
49864cfa | 105 | PREFIXES is the size of PREFIX. */ |
355afbcd KR |
106 | /* richfix: really unsigned? */ |
107 | unsigned char prefix[MAX_PREFIXES]; | |
108 | unsigned int prefixes; | |
109 | ||
4498e3d6 ILT |
110 | /* Wait prefix needs to come before any other prefixes, so handle |
111 | it specially. wait_prefix will hold the opcode modifier flag | |
112 | FWait if a wait prefix is given. */ | |
113 | int wait_prefix; | |
114 | ||
115 | /* RM and BI are the modrm byte and the base index byte where the | |
49864cfa | 116 | addressing modes of this insn are encoded. */ |
355afbcd KR |
117 | |
118 | modrm_byte rm; | |
119 | base_index_byte bi; | |
3c8df4ba | 120 | }; |
355afbcd | 121 | |
3c8df4ba | 122 | typedef struct _i386_insn i386_insn; |
fecd2382 | 123 | |
a39116f1 RP |
124 | /* This array holds the chars that always start a comment. If the |
125 | pre-processor is disabled, these aren't very useful */ | |
590c50d8 | 126 | #if defined (TE_I386AIX) || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
49864cfa KR |
127 | const char comment_chars[] = "#/"; |
128 | #else | |
a39116f1 | 129 | const char comment_chars[] = "#"; |
49864cfa | 130 | #endif |
fecd2382 | 131 | |
a39116f1 RP |
132 | /* This array holds the chars that only start a comment at the beginning of |
133 | a line. If the line seems to have the form '# 123 filename' | |
134 | .line and .file directives will appear in the pre-processed output */ | |
135 | /* Note that input_file.c hand checks for '#' at the beginning of the | |
136 | first line of the input file. This is because the compiler outputs | |
137 | #NO_APP at the beginning of its output. */ | |
138 | /* Also note that comments started like this one will always work if | |
f3d817d8 | 139 | '/' isn't otherwise defined. */ |
590c50d8 | 140 | #if defined (TE_I386AIX) || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
ad660eb1 | 141 | const char line_comment_chars[] = ""; |
7b23213f KR |
142 | #else |
143 | const char line_comment_chars[] = "/"; | |
144 | #endif | |
355afbcd | 145 | const char line_separator_chars[] = ""; |
fecd2382 | 146 | |
a39116f1 RP |
147 | /* Chars that can be used to separate mant from exp in floating point nums */ |
148 | const char EXP_CHARS[] = "eE"; | |
fecd2382 | 149 | |
a39116f1 RP |
150 | /* Chars that mean this number is a floating point constant */ |
151 | /* As in 0f12.456 */ | |
152 | /* or 0d1.2345e12 */ | |
153 | const char FLT_CHARS[] = "fFdDxX"; | |
fecd2382 RP |
154 | |
155 | /* tables for lexical analysis */ | |
156 | static char opcode_chars[256]; | |
157 | static char register_chars[256]; | |
158 | static char operand_chars[256]; | |
159 | static char space_chars[256]; | |
160 | static char identifier_chars[256]; | |
161 | static char digit_chars[256]; | |
162 | ||
163 | /* lexical macros */ | |
164 | #define is_opcode_char(x) (opcode_chars[(unsigned char) x]) | |
165 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
166 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
167 | #define is_space_char(x) (space_chars[(unsigned char) x]) | |
168 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
169 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
170 | ||
171 | /* put here all non-digit non-letter charcters that may occur in an operand */ | |
f0b37b4a | 172 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
fecd2382 | 173 | |
fecd2382 RP |
174 | /* md_assemble() always leaves the strings it's passed unaltered. To |
175 | effect this we maintain a stack of saved characters that we've smashed | |
176 | with '\0's (indicating end of strings for various sub-fields of the | |
177 | assembler instruction). */ | |
178 | static char save_stack[32]; | |
179 | static char *save_stack_p; /* stack pointer */ | |
180 | #define END_STRING_AND_SAVE(s) *save_stack_p++ = *s; *s = '\0' | |
181 | #define RESTORE_END_STRING(s) *s = *--save_stack_p | |
355afbcd KR |
182 | |
183 | /* The instruction we're assembling. */ | |
184 | static i386_insn i; | |
fecd2382 | 185 | |
4498e3d6 ILT |
186 | /* Possible templates for current insn. */ |
187 | static templates *current_templates; | |
188 | ||
fecd2382 RP |
189 | /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */ |
190 | static expressionS disp_expressions[2], im_expressions[2]; | |
191 | ||
4498e3d6 | 192 | /* Pointers to ebp & esp entries in reg_hash hash table. */ |
fecd2382 RP |
193 | static reg_entry *ebp, *esp; |
194 | ||
195 | static int this_operand; /* current operand we are working on */ | |
196 | ||
ade614d5 KR |
197 | static int flag_do_long_jump; /* FIXME what does this do? */ |
198 | ||
c54c7aac KR |
199 | static int flag_16bit_code; /* 1 if we're writing 16-bit code, 0 if 32-bit */ |
200 | ||
3c8df4ba KR |
201 | /* Interface to relax_segment. |
202 | There are 2 relax states for 386 jump insns: one for conditional & | |
203 | one for unconditional jumps. This is because the these two types | |
204 | of jumps add different sizes to frags when we're figuring out what | |
205 | sort of jump to choose to reach a given label. */ | |
fecd2382 RP |
206 | |
207 | /* types */ | |
208 | #define COND_JUMP 1 /* conditional jump */ | |
209 | #define UNCOND_JUMP 2 /* unconditional jump */ | |
210 | /* sizes */ | |
211 | #define BYTE 0 | |
212 | #define WORD 1 | |
213 | #define DWORD 2 | |
214 | #define UNKNOWN_SIZE 3 | |
215 | ||
3c8df4ba KR |
216 | #ifndef INLINE |
217 | #ifdef __GNUC__ | |
218 | #define INLINE __inline__ | |
219 | #else | |
220 | #define INLINE | |
221 | #endif | |
222 | #endif | |
223 | ||
ad660eb1 ILT |
224 | #define ENCODE_RELAX_STATE(type,size) \ |
225 | ((relax_substateT)((type<<2) | (size))) | |
fecd2382 | 226 | #define SIZE_FROM_RELAX_STATE(s) \ |
a39116f1 | 227 | ( (((s) & 0x3) == BYTE ? 1 : (((s) & 0x3) == WORD ? 2 : 4)) ) |
fecd2382 | 228 | |
355afbcd KR |
229 | const relax_typeS md_relax_table[] = |
230 | { | |
49864cfa KR |
231 | /* The fields are: |
232 | 1) most positive reach of this state, | |
233 | 2) most negative reach of this state, | |
234 | 3) how many bytes this mode will add to the size of the current frag | |
235 | 4) which index into the table to try if we can't fit into this one. | |
236 | */ | |
355afbcd KR |
237 | {1, 1, 0, 0}, |
238 | {1, 1, 0, 0}, | |
239 | {1, 1, 0, 0}, | |
240 | {1, 1, 0, 0}, | |
241 | ||
4498e3d6 ILT |
242 | /* For now we don't use word displacement jumps; they will not work |
243 | for destination addresses > 0xFFFF, since they clear the upper 16 | |
244 | bits of %eip. */ | |
355afbcd | 245 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, DWORD)}, |
3c8df4ba KR |
246 | /* word conditionals add 3 bytes to frag: |
247 | 2 opcode prefix; 1 displacement bytes */ | |
355afbcd | 248 | {32767 + 2, -32768 + 2, 3, ENCODE_RELAX_STATE (COND_JUMP, DWORD)}, |
3c8df4ba KR |
249 | /* dword conditionals adds 4 bytes to frag: |
250 | 1 opcode prefix; 3 displacement bytes */ | |
355afbcd KR |
251 | {0, 0, 4, 0}, |
252 | {1, 1, 0, 0}, | |
253 | ||
254 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, DWORD)}, | |
3c8df4ba KR |
255 | /* word jmp adds 2 bytes to frag: |
256 | 1 opcode prefix; 1 displacement bytes */ | |
355afbcd | 257 | {32767 + 2, -32768 + 2, 2, ENCODE_RELAX_STATE (UNCOND_JUMP, DWORD)}, |
3c8df4ba KR |
258 | /* dword jmp adds 3 bytes to frag: |
259 | 0 opcode prefix; 3 displacement bytes */ | |
355afbcd KR |
260 | {0, 0, 3, 0}, |
261 | {1, 1, 0, 0}, | |
262 | ||
fecd2382 RP |
263 | }; |
264 | ||
3ea36b53 ILT |
265 | |
266 | void | |
267 | i386_align_code (fragP, count) | |
268 | fragS *fragP; | |
269 | int count; | |
270 | { | |
271 | /* Various efficient no-op patterns for aligning code labels. */ | |
fb50cd4e ILT |
272 | /* Note: Don't try to assemble the instructions in the comments. */ |
273 | /* 0L and 0w are not legal */ | |
274 | static const char f32_1[] = | |
275 | {0x90}; /* nop */ | |
276 | static const char f32_2[] = | |
277 | {0x89,0xf6}; /* movl %esi,%esi */ | |
278 | static const char f32_3[] = | |
279 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
280 | static const char f32_4[] = | |
281 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
282 | static const char f32_5[] = | |
283 | {0x90, /* nop */ | |
284 | 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
285 | static const char f32_6[] = | |
286 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
287 | static const char f32_7[] = | |
288 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
289 | static const char f32_8[] = | |
290 | {0x90, /* nop */ | |
291 | 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
292 | static const char f32_9[] = | |
293 | {0x89,0xf6, /* movl %esi,%esi */ | |
294 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
295 | static const char f32_10[] = | |
296 | {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ | |
297 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
298 | static const char f32_11[] = | |
299 | {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ | |
300 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
301 | static const char f32_12[] = | |
302 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
303 | 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ | |
304 | static const char f32_13[] = | |
305 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
306 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
307 | static const char f32_14[] = | |
308 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ | |
309 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
310 | static const char f32_15[] = | |
311 | {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */ | |
312 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; | |
313 | static const char f16_4[] = | |
388fa5c6 | 314 | {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ |
fb50cd4e ILT |
315 | static const char f16_5[] = |
316 | {0x90, /* nop */ | |
388fa5c6 | 317 | 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ |
fb50cd4e ILT |
318 | static const char f16_6[] = |
319 | {0x89,0xf6, /* mov %si,%si */ | |
320 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
321 | static const char f16_7[] = | |
388fa5c6 | 322 | {0x8d,0x74,0x00, /* lea 0(%si),%si */ |
fb50cd4e ILT |
323 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ |
324 | static const char f16_8[] = | |
388fa5c6 | 325 | {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ |
fb50cd4e | 326 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ |
3ea36b53 ILT |
327 | static const char *const f32_patt[] = { |
328 | f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, | |
329 | f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15 | |
330 | }; | |
331 | static const char *const f16_patt[] = { | |
332 | f32_1, f32_2, f32_3, f16_4, f16_5, f16_6, f16_7, f16_8, | |
333 | f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15 | |
334 | }; | |
335 | ||
336 | if (count > 0 && count <= 15) | |
337 | { | |
338 | if (flag_16bit_code) | |
339 | { | |
340 | memcpy(fragP->fr_literal + fragP->fr_fix, | |
341 | f16_patt[count - 1], count); | |
342 | if (count > 8) /* adjust jump offset */ | |
343 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; | |
344 | } | |
345 | else | |
346 | memcpy(fragP->fr_literal + fragP->fr_fix, | |
347 | f32_patt[count - 1], count); | |
348 | fragP->fr_var = count; | |
349 | } | |
350 | } | |
351 | ||
49864cfa KR |
352 | static char *output_invalid PARAMS ((int c)); |
353 | static int i386_operand PARAMS ((char *operand_string)); | |
354 | static reg_entry *parse_register PARAMS ((char *reg_string)); | |
355 | #ifndef I386COFF | |
ad660eb1 | 356 | static void s_bss PARAMS ((int)); |
49864cfa | 357 | #endif |
fecd2382 | 358 | |
4498e3d6 | 359 | symbolS *GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */ |
f0b37b4a | 360 | |
3c8df4ba | 361 | static INLINE unsigned long |
49864cfa KR |
362 | mode_from_disp_size (t) |
363 | unsigned long t; | |
364 | { | |
3c8df4ba KR |
365 | return (t & Disp8) ? 1 : (t & Disp32) ? 2 : 0; |
366 | } | |
49864cfa | 367 | |
ad660eb1 ILT |
368 | #if 0 |
369 | /* Not used. */ | |
3c8df4ba | 370 | /* convert opcode suffix ('b' 'w' 'l' typically) into type specifier */ |
49864cfa | 371 | |
3c8df4ba | 372 | static INLINE unsigned long |
49864cfa KR |
373 | opcode_suffix_to_type (s) |
374 | unsigned long s; | |
375 | { | |
376 | return (s == BYTE_OPCODE_SUFFIX | |
377 | ? Byte : (s == WORD_OPCODE_SUFFIX | |
378 | ? Word : DWord)); | |
379 | } /* opcode_suffix_to_type() */ | |
ad660eb1 | 380 | #endif |
49864cfa | 381 | |
3c8df4ba | 382 | static INLINE int |
49864cfa KR |
383 | fits_in_signed_byte (num) |
384 | long num; | |
385 | { | |
3c8df4ba | 386 | return (num >= -128) && (num <= 127); |
49864cfa KR |
387 | } /* fits_in_signed_byte() */ |
388 | ||
3c8df4ba | 389 | static INLINE int |
49864cfa KR |
390 | fits_in_unsigned_byte (num) |
391 | long num; | |
392 | { | |
3c8df4ba | 393 | return (num & 0xff) == num; |
49864cfa KR |
394 | } /* fits_in_unsigned_byte() */ |
395 | ||
3c8df4ba | 396 | static INLINE int |
49864cfa KR |
397 | fits_in_unsigned_word (num) |
398 | long num; | |
399 | { | |
3c8df4ba | 400 | return (num & 0xffff) == num; |
49864cfa KR |
401 | } /* fits_in_unsigned_word() */ |
402 | ||
3c8df4ba | 403 | static INLINE int |
49864cfa KR |
404 | fits_in_signed_word (num) |
405 | long num; | |
406 | { | |
3c8df4ba | 407 | return (-32768 <= num) && (num <= 32767); |
49864cfa KR |
408 | } /* fits_in_signed_word() */ |
409 | ||
410 | static int | |
411 | smallest_imm_type (num) | |
412 | long num; | |
413 | { | |
f3d817d8 DM |
414 | #if 0 |
415 | /* This code is disabled because all the Imm1 forms in the opcode table | |
416 | are slower on the i486, and they're the versions with the implicitly | |
417 | specified single-position displacement, which has another syntax if | |
418 | you really want to use that form. If you really prefer to have the | |
419 | one-byte-shorter Imm1 form despite these problems, re-enable this | |
420 | code. */ | |
421 | if (num == 1) | |
422 | return Imm1 | Imm8 | Imm8S | Imm16 | Imm32; | |
423 | #endif | |
424 | return (fits_in_signed_byte (num) | |
3c8df4ba KR |
425 | ? (Imm8S | Imm8 | Imm16 | Imm32) |
426 | : fits_in_unsigned_byte (num) | |
427 | ? (Imm8 | Imm16 | Imm32) | |
428 | : (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
429 | ? (Imm16 | Imm32) | |
430 | : (Imm32)); | |
49864cfa | 431 | } /* smallest_imm_type() */ |
fecd2382 | 432 | |
4498e3d6 ILT |
433 | static int |
434 | check_prefix (prefix) | |
435 | int prefix; | |
436 | { | |
437 | int q; | |
438 | ||
439 | for (q = 0; q < i.prefixes; q++) | |
440 | { | |
441 | switch (prefix) | |
442 | { | |
443 | case CS_PREFIX_OPCODE: | |
444 | case DS_PREFIX_OPCODE: | |
445 | case ES_PREFIX_OPCODE: | |
446 | case FS_PREFIX_OPCODE: | |
447 | case GS_PREFIX_OPCODE: | |
448 | case SS_PREFIX_OPCODE: | |
449 | switch (i.prefix[q]) | |
450 | { | |
451 | case CS_PREFIX_OPCODE: | |
452 | case DS_PREFIX_OPCODE: | |
453 | case ES_PREFIX_OPCODE: | |
454 | case FS_PREFIX_OPCODE: | |
455 | case GS_PREFIX_OPCODE: | |
456 | case SS_PREFIX_OPCODE: | |
457 | as_bad ("same type of prefix used twice"); | |
458 | return 0; | |
459 | } | |
460 | break; | |
461 | ||
462 | case REPNE: | |
463 | case REPE: | |
464 | switch (i.prefix[q]) | |
465 | { | |
466 | case REPNE: | |
467 | case REPE: | |
468 | as_bad ("same type of prefix used twice"); | |
469 | return 0; | |
470 | } | |
471 | break; | |
472 | ||
473 | case FWAIT_OPCODE: | |
474 | if (i.wait_prefix != 0) | |
475 | { | |
476 | as_bad ("same type of prefix used twice"); | |
477 | return 0; | |
478 | } | |
479 | break; | |
480 | ||
481 | default: | |
482 | if (i.prefix[q] == prefix) | |
483 | { | |
484 | as_bad ("same type of prefix used twice"); | |
485 | return 0; | |
486 | } | |
487 | } | |
488 | } | |
489 | ||
490 | if (i.prefixes == MAX_PREFIXES && prefix != FWAIT_OPCODE) | |
491 | { | |
492 | char *p = "another"; /* paranoia */ | |
493 | ||
494 | for (q = 0; | |
495 | q < sizeof (i386_prefixtab) / sizeof (i386_prefixtab[0]); | |
496 | q++) | |
497 | if (i386_prefixtab[q].prefix_code == prefix) | |
498 | p = i386_prefixtab[q].prefix_name; | |
499 | ||
500 | as_bad ("%d prefixes given and `%%%s' prefix gives too many", | |
501 | MAX_PREFIXES, p); | |
502 | return 0; | |
503 | } | |
504 | ||
505 | return 1; | |
506 | } | |
507 | ||
f59fb6ca ILT |
508 | static void |
509 | set_16bit_code_flag (new_16bit_code_flag) | |
c54c7aac KR |
510 | int new_16bit_code_flag; |
511 | { | |
512 | flag_16bit_code = new_16bit_code_flag; | |
513 | } | |
514 | ||
355afbcd KR |
515 | const pseudo_typeS md_pseudo_table[] = |
516 | { | |
49864cfa | 517 | #ifndef I386COFF |
355afbcd | 518 | {"bss", s_bss, 0}, |
49864cfa | 519 | #endif |
02bdbd8b | 520 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) |
355afbcd | 521 | {"align", s_align_bytes, 0}, |
49864cfa KR |
522 | #else |
523 | {"align", s_align_ptwo, 0}, | |
524 | #endif | |
355afbcd KR |
525 | {"ffloat", float_cons, 'f'}, |
526 | {"dfloat", float_cons, 'd'}, | |
527 | {"tfloat", float_cons, 'x'}, | |
528 | {"value", cons, 2}, | |
49864cfa KR |
529 | {"noopt", s_ignore, 0}, |
530 | {"optim", s_ignore, 0}, | |
c54c7aac KR |
531 | {"code16", set_16bit_code_flag, 1}, |
532 | {"code32", set_16bit_code_flag, 0}, | |
355afbcd | 533 | {0, 0, 0} |
fecd2382 RP |
534 | }; |
535 | ||
536 | /* for interface with expression () */ | |
355afbcd | 537 | extern char *input_line_pointer; |
fecd2382 RP |
538 | |
539 | /* obstack for constructing various things in md_begin */ | |
540 | struct obstack o; | |
541 | ||
542 | /* hash table for opcode lookup */ | |
f3d817d8 | 543 | static struct hash_control *op_hash; |
fecd2382 | 544 | /* hash table for register lookup */ |
f3d817d8 | 545 | static struct hash_control *reg_hash; |
fecd2382 | 546 | /* hash table for prefix lookup */ |
f3d817d8 | 547 | static struct hash_control *prefix_hash; |
fecd2382 | 548 | \f |
355afbcd KR |
549 | |
550 | void | |
551 | md_begin () | |
fecd2382 | 552 | { |
ad660eb1 | 553 | const char *hash_err; |
355afbcd KR |
554 | |
555 | obstack_begin (&o, 4096); | |
556 | ||
557 | /* initialize op_hash hash table */ | |
f3d817d8 | 558 | op_hash = hash_new (); |
355afbcd KR |
559 | |
560 | { | |
561 | register const template *optab; | |
562 | register templates *core_optab; | |
563 | char *prev_name; | |
564 | ||
565 | optab = i386_optab; /* setup for loop */ | |
566 | prev_name = optab->name; | |
567 | obstack_grow (&o, optab, sizeof (template)); | |
568 | core_optab = (templates *) xmalloc (sizeof (templates)); | |
569 | ||
570 | for (optab++; optab < i386_optab_end; optab++) | |
571 | { | |
572 | if (!strcmp (optab->name, prev_name)) | |
573 | { | |
574 | /* same name as before --> append to current template list */ | |
575 | obstack_grow (&o, optab, sizeof (template)); | |
576 | } | |
577 | else | |
578 | { | |
579 | /* different name --> ship out current template list; | |
49864cfa KR |
580 | add to hash table; & begin anew */ |
581 | /* Note: end must be set before start! since obstack_next_free | |
582 | changes upon opstack_finish */ | |
355afbcd KR |
583 | core_optab->end = (template *) obstack_next_free (&o); |
584 | core_optab->start = (template *) obstack_finish (&o); | |
585 | hash_err = hash_insert (op_hash, prev_name, (char *) core_optab); | |
ad660eb1 | 586 | if (hash_err) |
355afbcd KR |
587 | { |
588 | hash_error: | |
48401fcf | 589 | as_fatal (_("Internal Error: Can't hash %s: %s"), prev_name, |
3c8df4ba | 590 | hash_err); |
355afbcd KR |
591 | } |
592 | prev_name = optab->name; | |
593 | core_optab = (templates *) xmalloc (sizeof (templates)); | |
594 | obstack_grow (&o, optab, sizeof (template)); | |
595 | } | |
596 | } | |
597 | } | |
598 | ||
599 | /* initialize reg_hash hash table */ | |
600 | reg_hash = hash_new (); | |
601 | { | |
602 | register const reg_entry *regtab; | |
603 | ||
604 | for (regtab = i386_regtab; regtab < i386_regtab_end; regtab++) | |
605 | { | |
ad660eb1 ILT |
606 | hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab); |
607 | if (hash_err) | |
355afbcd KR |
608 | goto hash_error; |
609 | } | |
610 | } | |
611 | ||
612 | esp = (reg_entry *) hash_find (reg_hash, "esp"); | |
613 | ebp = (reg_entry *) hash_find (reg_hash, "ebp"); | |
614 | ||
615 | /* initialize reg_hash hash table */ | |
616 | prefix_hash = hash_new (); | |
617 | { | |
618 | register const prefix_entry *prefixtab; | |
619 | ||
620 | for (prefixtab = i386_prefixtab; | |
621 | prefixtab < i386_prefixtab_end; prefixtab++) | |
622 | { | |
ad660eb1 ILT |
623 | hash_err = hash_insert (prefix_hash, prefixtab->prefix_name, |
624 | (PTR) prefixtab); | |
625 | if (hash_err) | |
355afbcd KR |
626 | goto hash_error; |
627 | } | |
628 | } | |
629 | ||
630 | /* fill in lexical tables: opcode_chars, operand_chars, space_chars */ | |
631 | { | |
ad660eb1 ILT |
632 | register int c; |
633 | register char *p; | |
355afbcd KR |
634 | |
635 | for (c = 0; c < 256; c++) | |
636 | { | |
637 | if (islower (c) || isdigit (c)) | |
638 | { | |
639 | opcode_chars[c] = c; | |
640 | register_chars[c] = c; | |
641 | } | |
642 | else if (isupper (c)) | |
643 | { | |
644 | opcode_chars[c] = tolower (c); | |
645 | register_chars[c] = opcode_chars[c]; | |
646 | } | |
647 | else if (c == PREFIX_SEPERATOR) | |
648 | { | |
649 | opcode_chars[c] = c; | |
650 | } | |
651 | else if (c == ')' || c == '(') | |
652 | { | |
653 | register_chars[c] = c; | |
654 | } | |
655 | ||
656 | if (isupper (c) || islower (c) || isdigit (c)) | |
657 | operand_chars[c] = c; | |
355afbcd KR |
658 | |
659 | if (isdigit (c) || c == '-') | |
660 | digit_chars[c] = c; | |
661 | ||
662 | if (isalpha (c) || c == '_' || c == '.' || isdigit (c)) | |
663 | identifier_chars[c] = c; | |
664 | ||
30355216 SC |
665 | #ifdef LEX_AT |
666 | identifier_chars['@'] = '@'; | |
667 | #endif | |
668 | ||
355afbcd KR |
669 | if (c == ' ' || c == '\t') |
670 | space_chars[c] = c; | |
671 | } | |
ad660eb1 ILT |
672 | |
673 | for (p = operand_special_chars; *p != '\0'; p++) | |
674 | operand_chars[(unsigned char) *p] = *p; | |
355afbcd | 675 | } |
ad660eb1 | 676 | |
590c50d8 ILT |
677 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
678 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
679 | { | |
680 | record_alignment (text_section, 2); | |
681 | record_alignment (data_section, 2); | |
682 | record_alignment (bss_section, 2); | |
683 | } | |
ad660eb1 | 684 | #endif |
fecd2382 | 685 | } |
3ea36b53 ILT |
686 | |
687 | void | |
688 | i386_print_statistics (file) | |
689 | FILE *file; | |
690 | { | |
691 | hash_print_statistics (file, "i386 opcode", op_hash); | |
692 | hash_print_statistics (file, "i386 register", reg_hash); | |
693 | hash_print_statistics (file, "i386 prefix", prefix_hash); | |
694 | } | |
fecd2382 | 695 | \f |
355afbcd | 696 | |
fecd2382 RP |
697 | #ifdef DEBUG386 |
698 | ||
699 | /* debugging routines for md_assemble */ | |
ad660eb1 ILT |
700 | static void pi PARAMS ((char *, i386_insn *)); |
701 | static void pte PARAMS ((template *)); | |
702 | static void pt PARAMS ((unsigned int)); | |
703 | static void pe PARAMS ((expressionS *)); | |
704 | static void ps PARAMS ((symbolS *)); | |
fecd2382 | 705 | |
355afbcd KR |
706 | static void |
707 | pi (line, x) | |
708 | char *line; | |
709 | i386_insn *x; | |
fecd2382 | 710 | { |
355afbcd KR |
711 | register template *p; |
712 | int i; | |
713 | ||
714 | fprintf (stdout, "%s: template ", line); | |
715 | pte (&x->tm); | |
716 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x", | |
717 | x->rm.mode, x->rm.reg, x->rm.regmem); | |
718 | fprintf (stdout, " base %x index %x scale %x\n", | |
719 | x->bi.base, x->bi.index, x->bi.scale); | |
720 | for (i = 0; i < x->operands; i++) | |
721 | { | |
722 | fprintf (stdout, " #%d: ", i + 1); | |
723 | pt (x->types[i]); | |
724 | fprintf (stdout, "\n"); | |
a52f90a4 ILT |
725 | if (x->types[i] |
726 | & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX)) | |
355afbcd KR |
727 | fprintf (stdout, "%s\n", x->regs[i]->reg_name); |
728 | if (x->types[i] & Imm) | |
729 | pe (x->imms[i]); | |
730 | if (x->types[i] & (Disp | Abs)) | |
731 | pe (x->disps[i]); | |
732 | } | |
fecd2382 RP |
733 | } |
734 | ||
355afbcd KR |
735 | static void |
736 | pte (t) | |
737 | template *t; | |
fecd2382 | 738 | { |
355afbcd KR |
739 | int i; |
740 | fprintf (stdout, " %d operands ", t->operands); | |
741 | fprintf (stdout, "opcode %x ", | |
742 | t->base_opcode); | |
743 | if (t->extension_opcode != None) | |
744 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
745 | if (t->opcode_modifier & D) | |
746 | fprintf (stdout, "D"); | |
747 | if (t->opcode_modifier & W) | |
748 | fprintf (stdout, "W"); | |
749 | fprintf (stdout, "\n"); | |
750 | for (i = 0; i < t->operands; i++) | |
751 | { | |
752 | fprintf (stdout, " #%d type ", i + 1); | |
753 | pt (t->operand_types[i]); | |
754 | fprintf (stdout, "\n"); | |
755 | } | |
fecd2382 RP |
756 | } |
757 | ||
355afbcd KR |
758 | static void |
759 | pe (e) | |
760 | expressionS *e; | |
fecd2382 | 761 | { |
5ac34ac3 | 762 | fprintf (stdout, " operation %d\n", e->X_op); |
355afbcd KR |
763 | fprintf (stdout, " add_number %d (%x)\n", |
764 | e->X_add_number, e->X_add_number); | |
765 | if (e->X_add_symbol) | |
766 | { | |
767 | fprintf (stdout, " add_symbol "); | |
768 | ps (e->X_add_symbol); | |
769 | fprintf (stdout, "\n"); | |
770 | } | |
5ac34ac3 | 771 | if (e->X_op_symbol) |
355afbcd | 772 | { |
5ac34ac3 ILT |
773 | fprintf (stdout, " op_symbol "); |
774 | ps (e->X_op_symbol); | |
355afbcd KR |
775 | fprintf (stdout, "\n"); |
776 | } | |
fecd2382 RP |
777 | } |
778 | ||
355afbcd KR |
779 | static void |
780 | ps (s) | |
781 | symbolS *s; | |
fecd2382 | 782 | { |
355afbcd KR |
783 | fprintf (stdout, "%s type %s%s", |
784 | S_GET_NAME (s), | |
785 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
786 | segment_name (S_GET_SEGMENT (s))); | |
fecd2382 RP |
787 | } |
788 | ||
355afbcd KR |
789 | struct type_name |
790 | { | |
791 | unsigned int mask; | |
792 | char *tname; | |
793 | } | |
794 | ||
795 | type_names[] = | |
796 | { | |
797 | { Reg8, "r8" }, | |
798 | { Reg16, "r16" }, | |
799 | { Reg32, "r32" }, | |
800 | { Imm8, "i8" }, | |
801 | { Imm8S, "i8s" }, | |
802 | { Imm16, "i16" }, | |
803 | { Imm32, "i32" }, | |
804 | { Mem8, "Mem8" }, | |
805 | { Mem16, "Mem16" }, | |
806 | { Mem32, "Mem32" }, | |
807 | { BaseIndex, "BaseIndex" }, | |
808 | { Abs8, "Abs8" }, | |
809 | { Abs16, "Abs16" }, | |
810 | { Abs32, "Abs32" }, | |
811 | { Disp8, "d8" }, | |
812 | { Disp16, "d16" }, | |
813 | { Disp32, "d32" }, | |
814 | { SReg2, "SReg2" }, | |
815 | { SReg3, "SReg3" }, | |
816 | { Acc, "Acc" }, | |
817 | { InOutPortReg, "InOutPortReg" }, | |
818 | { ShiftCount, "ShiftCount" }, | |
819 | { Imm1, "i1" }, | |
820 | { Control, "control reg" }, | |
821 | { Test, "test reg" }, | |
4498e3d6 | 822 | { Debug, "debug reg" }, |
355afbcd KR |
823 | { FloatReg, "FReg" }, |
824 | { FloatAcc, "FAcc" }, | |
825 | { JumpAbsolute, "Jump Absolute" }, | |
454b0ccd | 826 | { RegMMX, "rMMX" }, |
4498e3d6 | 827 | { EsSeg, "es" }, |
355afbcd | 828 | { 0, "" } |
fecd2382 RP |
829 | }; |
830 | ||
355afbcd KR |
831 | static void |
832 | pt (t) | |
833 | unsigned int t; | |
fecd2382 | 834 | { |
355afbcd KR |
835 | register struct type_name *ty; |
836 | ||
837 | if (t == Unknown) | |
838 | { | |
48401fcf | 839 | fprintf (stdout, _("Unknown")); |
355afbcd KR |
840 | } |
841 | else | |
842 | { | |
843 | for (ty = type_names; ty->mask; ty++) | |
844 | if (t & ty->mask) | |
845 | fprintf (stdout, "%s, ", ty->tname); | |
846 | } | |
847 | fflush (stdout); | |
fecd2382 RP |
848 | } |
849 | ||
850 | #endif /* DEBUG386 */ | |
851 | \f | |
49864cfa KR |
852 | #ifdef BFD_ASSEMBLER |
853 | static bfd_reloc_code_real_type | |
f0b37b4a | 854 | reloc (size, pcrel, other) |
49864cfa KR |
855 | int size; |
856 | int pcrel; | |
f0b37b4a | 857 | bfd_reloc_code_real_type other; |
49864cfa | 858 | { |
f0b37b4a KR |
859 | if (other != NO_RELOC) return other; |
860 | ||
49864cfa KR |
861 | if (pcrel) |
862 | switch (size) | |
863 | { | |
864 | case 1: return BFD_RELOC_8_PCREL; | |
865 | case 2: return BFD_RELOC_16_PCREL; | |
866 | case 4: return BFD_RELOC_32_PCREL; | |
867 | } | |
868 | else | |
869 | switch (size) | |
870 | { | |
871 | case 1: return BFD_RELOC_8; | |
872 | case 2: return BFD_RELOC_16; | |
873 | case 4: return BFD_RELOC_32; | |
874 | } | |
ad660eb1 | 875 | |
48401fcf TT |
876 | if (pcrel) |
877 | as_bad (_("Can not do %d byte pc-relative relocation"), size); | |
878 | else | |
879 | as_bad (_("Can not do %d byte relocation"), size); | |
880 | ||
ad660eb1 | 881 | return BFD_RELOC_NONE; |
49864cfa | 882 | } |
49864cfa | 883 | |
f0b37b4a KR |
884 | /* |
885 | * Here we decide which fixups can be adjusted to make them relative to | |
886 | * the beginning of the section instead of the symbol. Basically we need | |
887 | * to make sure that the dynamic relocations are done correctly, so in | |
888 | * some cases we force the original symbol to be used. | |
889 | */ | |
0877841d | 890 | int |
f0b37b4a KR |
891 | tc_i386_fix_adjustable(fixP) |
892 | fixS * fixP; | |
893 | { | |
76fb6d2f | 894 | #ifdef OBJ_ELF |
c54c7aac | 895 | /* Prevent all adjustments to global symbols. */ |
0877841d | 896 | if (S_IS_EXTERN (fixP->fx_addsy)) |
c54c7aac | 897 | return 0; |
0b476c53 ILT |
898 | if (S_IS_WEAK (fixP->fx_addsy)) |
899 | return 0; | |
0b476c53 | 900 | #endif /* ! defined (OBJ_AOUT) */ |
c54c7aac | 901 | /* adjust_reloc_syms doesn't know about the GOT */ |
0877841d ILT |
902 | if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF |
903 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 | |
904 | || fixP->fx_r_type == BFD_RELOC_386_GOT32) | |
c54c7aac | 905 | return 0; |
c54c7aac | 906 | return 1; |
f0b37b4a | 907 | } |
454b0ccd ILT |
908 | #else |
909 | #define reloc(SIZE,PCREL,OTHER) 0 | |
910 | #define BFD_RELOC_32 0 | |
911 | #define BFD_RELOC_32_PCREL 0 | |
912 | #define BFD_RELOC_386_PLT32 0 | |
913 | #define BFD_RELOC_386_GOT32 0 | |
914 | #define BFD_RELOC_386_GOTOFF 0 | |
915 | #endif | |
f0b37b4a | 916 | |
49864cfa | 917 | /* This is the guts of the machine-dependent assembler. LINE points to a |
3c8df4ba | 918 | machine dependent instruction. This function is supposed to emit |
49864cfa | 919 | the frags/bytes it assembles to. */ |
f0b37b4a | 920 | |
355afbcd KR |
921 | void |
922 | md_assemble (line) | |
923 | char *line; | |
fecd2382 | 924 | { |
227b6b55 ILT |
925 | /* Points to template once we've found it. */ |
926 | const template *t; | |
355afbcd | 927 | |
ad660eb1 ILT |
928 | /* Count the size of the instruction generated. */ |
929 | int insn_size = 0; | |
930 | ||
f0b37b4a KR |
931 | int j; |
932 | ||
355afbcd KR |
933 | /* Initialize globals. */ |
934 | memset (&i, '\0', sizeof (i)); | |
f0b37b4a KR |
935 | for (j = 0; j < MAX_OPERANDS; j++) |
936 | i.disp_reloc[j] = NO_RELOC; | |
355afbcd KR |
937 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
938 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
939 | save_stack_p = save_stack; /* reset stack pointer */ | |
940 | ||
227b6b55 | 941 | /* First parse an opcode & call i386_operand for the operands. |
49864cfa KR |
942 | We assume that the scrubber has arranged it so that line[0] is the valid |
943 | start of a (possibly prefixed) opcode. */ | |
355afbcd | 944 | { |
f3d817d8 | 945 | char *l = line; |
355afbcd KR |
946 | |
947 | /* 1 if operand is pending after ','. */ | |
948 | unsigned int expecting_operand = 0; | |
4498e3d6 ILT |
949 | /* Non-zero if we found a prefix only acceptable with string insns. */ |
950 | const char *expecting_string_instruction = NULL; | |
0b476c53 ILT |
951 | /* Non-zero if operand parens not balanced. */ |
952 | unsigned int paren_not_balanced; | |
355afbcd KR |
953 | char *token_start = l; |
954 | ||
955 | while (!is_space_char (*l) && *l != END_OF_INSN) | |
956 | { | |
957 | if (!is_opcode_char (*l)) | |
958 | { | |
48401fcf | 959 | as_bad (_("invalid character %s in opcode"), output_invalid (*l)); |
355afbcd KR |
960 | return; |
961 | } | |
962 | else if (*l != PREFIX_SEPERATOR) | |
963 | { | |
964 | *l = opcode_chars[(unsigned char) *l]; /* fold case of opcodes */ | |
965 | l++; | |
966 | } | |
967 | else | |
f3d817d8 DM |
968 | { |
969 | /* This opcode's got a prefix. */ | |
970 | unsigned int q; | |
971 | prefix_entry *prefix; | |
355afbcd KR |
972 | |
973 | if (l == token_start) | |
974 | { | |
48401fcf | 975 | as_bad (_("expecting prefix; got nothing")); |
355afbcd KR |
976 | return; |
977 | } | |
978 | END_STRING_AND_SAVE (l); | |
979 | prefix = (prefix_entry *) hash_find (prefix_hash, token_start); | |
980 | if (!prefix) | |
981 | { | |
48401fcf | 982 | as_bad (_("no such opcode prefix `%s'"), token_start); |
4498e3d6 | 983 | RESTORE_END_STRING (l); |
355afbcd KR |
984 | return; |
985 | } | |
986 | RESTORE_END_STRING (l); | |
987 | /* check for repeated prefix */ | |
4498e3d6 ILT |
988 | if (! check_prefix (prefix->prefix_code)) |
989 | return; | |
990 | if (prefix->prefix_code == FWAIT_OPCODE) | |
355afbcd | 991 | { |
4498e3d6 ILT |
992 | i.wait_prefix = FWait; |
993 | } | |
994 | else | |
995 | { | |
996 | i.prefix[i.prefixes++] = prefix->prefix_code; | |
997 | if (prefix->prefix_code == REPE | |
998 | || prefix->prefix_code == REPNE) | |
999 | expecting_string_instruction = prefix->prefix_name; | |
355afbcd | 1000 | } |
4498e3d6 | 1001 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ |
355afbcd KR |
1002 | token_start = ++l; |
1003 | } | |
1004 | } | |
1005 | END_STRING_AND_SAVE (l); | |
1006 | if (token_start == l) | |
1007 | { | |
48401fcf | 1008 | as_bad (_("expecting opcode; got nothing")); |
4498e3d6 | 1009 | RESTORE_END_STRING (l); |
355afbcd KR |
1010 | return; |
1011 | } | |
1012 | ||
1013 | /* Lookup insn in hash; try intel & att naming conventions if appropriate; | |
49864cfa | 1014 | that is: we only use the opcode suffix 'b' 'w' or 'l' if we need to. */ |
355afbcd KR |
1015 | current_templates = (templates *) hash_find (op_hash, token_start); |
1016 | if (!current_templates) | |
1017 | { | |
1018 | int last_index = strlen (token_start) - 1; | |
1019 | char last_char = token_start[last_index]; | |
1020 | switch (last_char) | |
1021 | { | |
1022 | case DWORD_OPCODE_SUFFIX: | |
1023 | case WORD_OPCODE_SUFFIX: | |
1024 | case BYTE_OPCODE_SUFFIX: | |
1025 | token_start[last_index] = '\0'; | |
1026 | current_templates = (templates *) hash_find (op_hash, token_start); | |
1027 | token_start[last_index] = last_char; | |
1028 | i.suffix = last_char; | |
1029 | } | |
1030 | if (!current_templates) | |
1031 | { | |
48401fcf | 1032 | as_bad (_("no such 386 instruction: `%s'"), token_start); |
4498e3d6 | 1033 | RESTORE_END_STRING (l); |
355afbcd KR |
1034 | return; |
1035 | } | |
1036 | } | |
1037 | RESTORE_END_STRING (l); | |
1038 | ||
1039 | /* check for rep/repne without a string instruction */ | |
1040 | if (expecting_string_instruction && | |
4498e3d6 | 1041 | !(current_templates->start->opcode_modifier & IsString)) |
355afbcd | 1042 | { |
48401fcf | 1043 | as_bad (_("expecting string instruction after `%s'"), |
4498e3d6 | 1044 | expecting_string_instruction); |
355afbcd KR |
1045 | return; |
1046 | } | |
1047 | ||
1048 | /* There may be operands to parse. */ | |
4498e3d6 | 1049 | if (*l != END_OF_INSN) |
355afbcd KR |
1050 | { |
1051 | /* parse operands */ | |
1052 | do | |
1053 | { | |
1054 | /* skip optional white space before operand */ | |
1055 | while (!is_operand_char (*l) && *l != END_OF_INSN) | |
1056 | { | |
1057 | if (!is_space_char (*l)) | |
1058 | { | |
48401fcf TT |
1059 | as_bad (_("invalid character %s before operand %d"), |
1060 | output_invalid (*l), i.operands); | |
355afbcd KR |
1061 | return; |
1062 | } | |
1063 | l++; | |
1064 | } | |
1065 | token_start = l; /* after white space */ | |
0b476c53 ILT |
1066 | paren_not_balanced = 0; |
1067 | while (paren_not_balanced || *l != ',') | |
355afbcd KR |
1068 | { |
1069 | if (*l == END_OF_INSN) | |
1070 | { | |
0b476c53 | 1071 | if (paren_not_balanced) |
355afbcd | 1072 | { |
48401fcf TT |
1073 | as_bad (_("unbalanced parenthesis in operand %d."), |
1074 | i.operands); | |
355afbcd KR |
1075 | return; |
1076 | } | |
1077 | else | |
1078 | break; /* we are done */ | |
1079 | } | |
ad660eb1 | 1080 | else if (!is_operand_char (*l) && !is_space_char (*l)) |
355afbcd | 1081 | { |
48401fcf TT |
1082 | as_bad (_("invalid character %s in operand %d"), |
1083 | output_invalid (*l), i.operands); | |
355afbcd KR |
1084 | return; |
1085 | } | |
1086 | if (*l == '(') | |
0b476c53 | 1087 | ++paren_not_balanced; |
355afbcd | 1088 | if (*l == ')') |
0b476c53 | 1089 | --paren_not_balanced; |
355afbcd KR |
1090 | l++; |
1091 | } | |
1092 | if (l != token_start) | |
1093 | { /* yes, we've read in another operand */ | |
1094 | unsigned int operand_ok; | |
1095 | this_operand = i.operands++; | |
1096 | if (i.operands > MAX_OPERANDS) | |
1097 | { | |
48401fcf | 1098 | as_bad (_("spurious operands; (%d operands/instruction max)"), |
355afbcd KR |
1099 | MAX_OPERANDS); |
1100 | return; | |
1101 | } | |
1102 | /* now parse operand adding info to 'i' as we go along */ | |
1103 | END_STRING_AND_SAVE (l); | |
1104 | operand_ok = i386_operand (token_start); | |
1105 | RESTORE_END_STRING (l); /* restore old contents */ | |
1106 | if (!operand_ok) | |
1107 | return; | |
1108 | } | |
1109 | else | |
1110 | { | |
1111 | if (expecting_operand) | |
1112 | { | |
1113 | expecting_operand_after_comma: | |
48401fcf | 1114 | as_bad (_("expecting operand after ','; got nothing")); |
355afbcd KR |
1115 | return; |
1116 | } | |
1117 | if (*l == ',') | |
1118 | { | |
48401fcf | 1119 | as_bad (_("expecting operand before ','; got nothing")); |
355afbcd KR |
1120 | return; |
1121 | } | |
1122 | } | |
1123 | ||
1124 | /* now *l must be either ',' or END_OF_INSN */ | |
1125 | if (*l == ',') | |
1126 | { | |
1127 | if (*++l == END_OF_INSN) | |
1128 | { /* just skip it, if it's \n complain */ | |
1129 | goto expecting_operand_after_comma; | |
1130 | } | |
1131 | expecting_operand = 1; | |
1132 | } | |
1133 | } | |
1134 | while (*l != END_OF_INSN); /* until we get end of insn */ | |
1135 | } | |
1136 | } | |
1137 | ||
1138 | /* Now we've parsed the opcode into a set of templates, and have the | |
c5dd66a1 KR |
1139 | operands at hand. |
1140 | ||
1141 | Next, we find a template that matches the given insn, | |
1142 | making sure the overlap of the given operands types is consistent | |
1143 | with the template operand types. */ | |
355afbcd | 1144 | |
fecd2382 | 1145 | #define MATCH(overlap,given_type) \ |
a39116f1 | 1146 | (overlap && \ |
49864cfa KR |
1147 | (((overlap & (JumpAbsolute|BaseIndex|Mem8)) \ |
1148 | == (given_type & (JumpAbsolute|BaseIndex|Mem8))) \ | |
1149 | || (overlap == InOutPortReg))) | |
1150 | ||
355afbcd KR |
1151 | |
1152 | /* If m0 and m1 are register matches they must be consistent | |
c5dd66a1 KR |
1153 | with the expected operand types t0 and t1. |
1154 | That is, if both m0 & m1 are register matches | |
1155 | i.e. ( ((m0 & (Reg)) && (m1 & (Reg)) ) ? | |
1156 | then, either 1. or 2. must be true: | |
1157 | 1. the expected operand type register overlap is null: | |
1158 | (t0 & t1 & Reg) == 0 | |
1159 | AND | |
1160 | the given register overlap is null: | |
1161 | (m0 & m1 & Reg) == 0 | |
1162 | 2. the expected operand type register overlap == the given | |
1163 | operand type overlap: (t0 & t1 & m0 & m1 & Reg). | |
1164 | */ | |
a39116f1 RP |
1165 | #define CONSISTENT_REGISTER_MATCH(m0, m1, t0, t1) \ |
1166 | ( ((m0 & (Reg)) && (m1 & (Reg))) ? \ | |
1167 | ( ((t0 & t1 & (Reg)) == 0 && (m0 & m1 & (Reg)) == 0) || \ | |
1168 | ((t0 & t1) & (m0 & m1) & (Reg)) \ | |
1169 | ) : 1) | |
355afbcd KR |
1170 | { |
1171 | register unsigned int overlap0, overlap1; | |
1172 | expressionS *exp; | |
1173 | unsigned int overlap2; | |
1174 | unsigned int found_reverse_match; | |
1175 | ||
1176 | overlap0 = overlap1 = overlap2 = found_reverse_match = 0; | |
1177 | for (t = current_templates->start; | |
1178 | t < current_templates->end; | |
1179 | t++) | |
1180 | { | |
355afbcd KR |
1181 | /* must have right number of operands */ |
1182 | if (i.operands != t->operands) | |
1183 | continue; | |
1184 | else if (!t->operands) | |
1185 | break; /* 0 operands always matches */ | |
1186 | ||
1187 | overlap0 = i.types[0] & t->operand_types[0]; | |
1188 | switch (t->operands) | |
1189 | { | |
1190 | case 1: | |
1191 | if (!MATCH (overlap0, i.types[0])) | |
1192 | continue; | |
1193 | break; | |
1194 | case 2: | |
1195 | case 3: | |
1196 | overlap1 = i.types[1] & t->operand_types[1]; | |
1197 | if (!MATCH (overlap0, i.types[0]) || | |
1198 | !MATCH (overlap1, i.types[1]) || | |
1199 | !CONSISTENT_REGISTER_MATCH (overlap0, overlap1, | |
1200 | t->operand_types[0], | |
1201 | t->operand_types[1])) | |
542e1629 | 1202 | { |
355afbcd KR |
1203 | |
1204 | /* check if other direction is valid ... */ | |
1205 | if (!(t->opcode_modifier & COMES_IN_BOTH_DIRECTIONS)) | |
1206 | continue; | |
1207 | ||
1208 | /* try reversing direction of operands */ | |
1209 | overlap0 = i.types[0] & t->operand_types[1]; | |
1210 | overlap1 = i.types[1] & t->operand_types[0]; | |
1211 | if (!MATCH (overlap0, i.types[0]) || | |
1212 | !MATCH (overlap1, i.types[1]) || | |
1213 | !CONSISTENT_REGISTER_MATCH (overlap0, overlap1, | |
227b6b55 ILT |
1214 | t->operand_types[1], |
1215 | t->operand_types[0])) | |
355afbcd KR |
1216 | { |
1217 | /* does not match either direction */ | |
1218 | continue; | |
1219 | } | |
1220 | /* found a reverse match here -- slip through */ | |
1221 | /* found_reverse_match holds which of D or FloatD we've found */ | |
1222 | found_reverse_match = t->opcode_modifier & COMES_IN_BOTH_DIRECTIONS; | |
1223 | } /* endif: not forward match */ | |
1224 | /* found either forward/reverse 2 operand match here */ | |
1225 | if (t->operands == 3) | |
1226 | { | |
1227 | overlap2 = i.types[2] & t->operand_types[2]; | |
1228 | if (!MATCH (overlap2, i.types[2]) || | |
1229 | !CONSISTENT_REGISTER_MATCH (overlap0, overlap2, | |
1230 | t->operand_types[0], | |
1231 | t->operand_types[2]) || | |
1232 | !CONSISTENT_REGISTER_MATCH (overlap1, overlap2, | |
1233 | t->operand_types[1], | |
1234 | t->operand_types[2])) | |
1235 | continue; | |
1236 | } | |
1237 | /* found either forward/reverse 2 or 3 operand match here: | |
c5dd66a1 | 1238 | slip through to break */ |
355afbcd KR |
1239 | } |
1240 | break; /* we've found a match; break out of loop */ | |
1241 | } /* for (t = ... */ | |
1242 | if (t == current_templates->end) | |
1243 | { /* we found no match */ | |
48401fcf | 1244 | as_bad (_("suffix or operands invalid for `%s'"), |
4498e3d6 | 1245 | current_templates->start->name); |
355afbcd KR |
1246 | return; |
1247 | } | |
1248 | ||
4498e3d6 | 1249 | /* Copy the template we found. */ |
f3d817d8 | 1250 | i.tm = *t; |
4498e3d6 | 1251 | i.tm.opcode_modifier |= i.wait_prefix; |
227b6b55 ILT |
1252 | |
1253 | if (found_reverse_match) | |
1254 | { | |
1255 | i.tm.operand_types[0] = t->operand_types[1]; | |
1256 | i.tm.operand_types[1] = t->operand_types[0]; | |
1257 | } | |
355afbcd | 1258 | |
4498e3d6 ILT |
1259 | /* Check string instruction segment overrides */ |
1260 | if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0) | |
1261 | { | |
1262 | int mem_op = (i.types[0] & Mem) ? 0 : 1; | |
1263 | if ((i.tm.operand_types[mem_op+0] & EsSeg) != 0) | |
1264 | { | |
1265 | if (i.seg[0] != (seg_entry *) 0 && i.seg[0] != (seg_entry *) &es) | |
1266 | { | |
1267 | as_bad ("`%s' %s operand must use `%%es' segment", | |
1268 | i.tm.name, | |
1269 | ordinal_names[mem_op+0]); | |
1270 | return; | |
1271 | } | |
1272 | /* There's only ever one segment override allowed per instruction. | |
1273 | This instruction possibly has a legal segment override on the | |
1274 | second operand, so copy the segment to where non-string | |
1275 | instructions store it, allowing common code. */ | |
1276 | i.seg[0] = i.seg[1]; | |
1277 | } | |
1278 | else if ((i.tm.operand_types[mem_op+1] & EsSeg) != 0) | |
1279 | { | |
1280 | if (i.seg[1] != (seg_entry *) 0 && i.seg[1] != (seg_entry *) &es) | |
1281 | { | |
1282 | as_bad ("`%s' %s operand must use `%%es' segment", | |
1283 | i.tm.name, | |
1284 | ordinal_names[mem_op+1]); | |
1285 | return; | |
1286 | } | |
1287 | } | |
1288 | } | |
1289 | ||
c54c7aac KR |
1290 | /* If the matched instruction specifies an explicit opcode suffix, |
1291 | use it - and make sure none has already been specified. */ | |
227b6b55 | 1292 | if (i.tm.opcode_modifier & (Data16|Data32)) |
c54c7aac KR |
1293 | { |
1294 | if (i.suffix) | |
1295 | { | |
48401fcf | 1296 | as_bad (_("extraneous opcode suffix given")); |
c54c7aac KR |
1297 | return; |
1298 | } | |
227b6b55 | 1299 | if (i.tm.opcode_modifier & Data16) |
c54c7aac KR |
1300 | i.suffix = WORD_OPCODE_SUFFIX; |
1301 | else | |
1302 | i.suffix = DWORD_OPCODE_SUFFIX; | |
1303 | } | |
1304 | ||
355afbcd | 1305 | /* If there's no opcode suffix we try to invent one based on register |
c5dd66a1 | 1306 | operands. */ |
355afbcd KR |
1307 | if (!i.suffix && i.reg_operands) |
1308 | { | |
1309 | /* We take i.suffix from the LAST register operand specified. This | |
c5dd66a1 KR |
1310 | assumes that the last register operands is the destination register |
1311 | operand. */ | |
ad660eb1 ILT |
1312 | int op; |
1313 | for (op = 0; op < MAX_OPERANDS; op++) | |
1314 | if (i.types[op] & Reg) | |
355afbcd | 1315 | { |
e592f0e6 ILT |
1316 | i.suffix = ((i.types[op] & Reg8) ? BYTE_OPCODE_SUFFIX : |
1317 | (i.types[op] & Reg16) ? WORD_OPCODE_SUFFIX : | |
ad660eb1 | 1318 | DWORD_OPCODE_SUFFIX); |
355afbcd KR |
1319 | } |
1320 | } | |
3ea36b53 ILT |
1321 | else if (i.suffix != 0 |
1322 | && i.reg_operands != 0 | |
1323 | && (i.types[i.operands - 1] & Reg) != 0) | |
1324 | { | |
e592f0e6 | 1325 | int bad; |
3ea36b53 ILT |
1326 | |
1327 | /* If the last operand is a register, make sure it is | |
1328 | compatible with the suffix. */ | |
1329 | ||
e592f0e6 | 1330 | bad = 0; |
3ea36b53 ILT |
1331 | switch (i.suffix) |
1332 | { | |
1333 | default: | |
1334 | abort (); | |
1335 | case BYTE_OPCODE_SUFFIX: | |
e592f0e6 ILT |
1336 | /* If this is an eight bit register, it's OK. If it's the |
1337 | 16 or 32 bit version of an eight bit register, we will | |
1338 | just use the low portion, and that's OK too. */ | |
1339 | if ((i.types[i.operands - 1] & Reg8) == 0 | |
1340 | && i.regs[i.operands - 1]->reg_num >= 4) | |
1341 | bad = 1; | |
3ea36b53 ILT |
1342 | break; |
1343 | case WORD_OPCODE_SUFFIX: | |
3ea36b53 | 1344 | case DWORD_OPCODE_SUFFIX: |
e592f0e6 ILT |
1345 | /* We don't insist on the presence or absence of the e |
1346 | prefix on the register, but we reject eight bit | |
1347 | registers. */ | |
1348 | if ((i.types[i.operands - 1] & Reg8) != 0) | |
1349 | bad = 1; | |
3ea36b53 | 1350 | } |
e592f0e6 | 1351 | if (bad) |
48401fcf | 1352 | as_bad (_("register does not match opcode suffix")); |
3ea36b53 | 1353 | } |
355afbcd KR |
1354 | |
1355 | /* Make still unresolved immediate matches conform to size of immediate | |
c5dd66a1 KR |
1356 | given in i.suffix. Note: overlap2 cannot be an immediate! |
1357 | We assume this. */ | |
355afbcd KR |
1358 | if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32)) |
1359 | && overlap0 != Imm8 && overlap0 != Imm8S | |
1360 | && overlap0 != Imm16 && overlap0 != Imm32) | |
1361 | { | |
1362 | if (!i.suffix) | |
1363 | { | |
48401fcf | 1364 | as_bad (_("no opcode suffix given; can't determine immediate size")); |
355afbcd KR |
1365 | return; |
1366 | } | |
1367 | overlap0 &= (i.suffix == BYTE_OPCODE_SUFFIX ? (Imm8 | Imm8S) : | |
1368 | (i.suffix == WORD_OPCODE_SUFFIX ? Imm16 : Imm32)); | |
1369 | } | |
1370 | if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32)) | |
1371 | && overlap1 != Imm8 && overlap1 != Imm8S | |
1372 | && overlap1 != Imm16 && overlap1 != Imm32) | |
1373 | { | |
1374 | if (!i.suffix) | |
1375 | { | |
48401fcf | 1376 | as_bad (_("no opcode suffix given; can't determine immediate size")); |
355afbcd KR |
1377 | return; |
1378 | } | |
1379 | overlap1 &= (i.suffix == BYTE_OPCODE_SUFFIX ? (Imm8 | Imm8S) : | |
1380 | (i.suffix == WORD_OPCODE_SUFFIX ? Imm16 : Imm32)); | |
1381 | } | |
1382 | ||
1383 | i.types[0] = overlap0; | |
1384 | i.types[1] = overlap1; | |
1385 | i.types[2] = overlap2; | |
1386 | ||
1387 | if (overlap0 & ImplicitRegister) | |
1388 | i.reg_operands--; | |
1389 | if (overlap1 & ImplicitRegister) | |
1390 | i.reg_operands--; | |
1391 | if (overlap2 & ImplicitRegister) | |
1392 | i.reg_operands--; | |
1393 | if (overlap0 & Imm1) | |
1394 | i.imm_operands = 0; /* kludge for shift insns */ | |
1395 | ||
355afbcd | 1396 | /* Finalize opcode. First, we change the opcode based on the operand |
c5dd66a1 KR |
1397 | size given by i.suffix: we never have to change things for byte insns, |
1398 | or when no opcode suffix is need to size the operands. */ | |
355afbcd | 1399 | |
227b6b55 | 1400 | if (!i.suffix && (i.tm.opcode_modifier & W)) |
355afbcd | 1401 | { |
48401fcf | 1402 | as_bad (_("no opcode suffix given and no register operands; can't size instruction")); |
355afbcd KR |
1403 | return; |
1404 | } | |
1405 | ||
1406 | if (i.suffix && i.suffix != BYTE_OPCODE_SUFFIX) | |
1407 | { | |
1408 | /* Select between byte and word/dword operations. */ | |
227b6b55 ILT |
1409 | if (i.tm.opcode_modifier & W) |
1410 | i.tm.base_opcode |= W; | |
355afbcd | 1411 | /* Now select between word & dword operations via the |
a39116f1 | 1412 | operand size prefix. */ |
c54c7aac | 1413 | if ((i.suffix == WORD_OPCODE_SUFFIX) ^ flag_16bit_code) |
355afbcd | 1414 | { |
4498e3d6 ILT |
1415 | if (! check_prefix (WORD_PREFIX_OPCODE)) |
1416 | return; | |
355afbcd KR |
1417 | i.prefix[i.prefixes++] = WORD_PREFIX_OPCODE; |
1418 | } | |
1419 | } | |
1420 | ||
1421 | /* For insns with operands there are more diddles to do to the opcode. */ | |
1422 | if (i.operands) | |
1423 | { | |
c54c7aac KR |
1424 | /* Default segment register this instruction will use |
1425 | for memory accesses. 0 means unknown. | |
1426 | This is only for optimizing out unnecessary segment overrides. */ | |
1427 | const seg_entry *default_seg = 0; | |
1428 | ||
1429 | /* True if this instruction uses a memory addressing mode, | |
1430 | and therefore may need an address-size prefix. */ | |
1431 | int uses_mem_addrmode = 0; | |
1432 | ||
1433 | ||
355afbcd | 1434 | /* If we found a reverse match we must alter the opcode direction bit |
c5dd66a1 KR |
1435 | found_reverse_match holds bit to set (different for int & |
1436 | float insns). */ | |
355afbcd | 1437 | |
4498e3d6 | 1438 | i.tm.base_opcode ^= found_reverse_match; |
355afbcd | 1439 | |
c5dd66a1 | 1440 | /* The imul $imm, %reg instruction is converted into |
4498e3d6 ILT |
1441 | imul $imm, %reg, %reg, and the clr %reg instruction |
1442 | is converted into xor %reg, %reg. */ | |
1443 | if (i.tm.opcode_modifier & regKludge) | |
2fb44892 | 1444 | { |
4498e3d6 ILT |
1445 | unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1; |
1446 | /* Pretend we saw the extra register operand. */ | |
1447 | i.regs[first_reg_op+1] = i.regs[first_reg_op]; | |
2fb44892 ILT |
1448 | i.reg_operands = 2; |
1449 | } | |
1450 | ||
227b6b55 | 1451 | if (i.tm.opcode_modifier & ShortForm) |
355afbcd KR |
1452 | { |
1453 | /* The register or float register operand is in operand 0 or 1. */ | |
ad660eb1 | 1454 | unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1; |
355afbcd | 1455 | /* Register goes in low 3 bits of opcode. */ |
227b6b55 | 1456 | i.tm.base_opcode |= i.regs[op]->reg_num; |
355afbcd | 1457 | } |
227b6b55 | 1458 | else if (i.tm.opcode_modifier & ShortFormW) |
355afbcd KR |
1459 | { |
1460 | /* Short form with 0x8 width bit. Register is always dest. operand */ | |
227b6b55 | 1461 | i.tm.base_opcode |= i.regs[1]->reg_num; |
355afbcd KR |
1462 | if (i.suffix == WORD_OPCODE_SUFFIX || |
1463 | i.suffix == DWORD_OPCODE_SUFFIX) | |
227b6b55 | 1464 | i.tm.base_opcode |= 0x8; |
355afbcd | 1465 | } |
227b6b55 | 1466 | else if (i.tm.opcode_modifier & Modrm) |
355afbcd | 1467 | { |
227b6b55 ILT |
1468 | /* The opcode is completed (modulo i.tm.extension_opcode which |
1469 | must be put into the modrm byte). | |
1470 | Now, we make the modrm & index base bytes based on all the | |
1471 | info we've collected. */ | |
355afbcd KR |
1472 | |
1473 | /* i.reg_operands MUST be the number of real register operands; | |
c5dd66a1 | 1474 | implicit registers do not count. */ |
355afbcd KR |
1475 | if (i.reg_operands == 2) |
1476 | { | |
1477 | unsigned int source, dest; | |
454b0ccd ILT |
1478 | source = ((i.types[0] |
1479 | & (Reg | |
1480 | | SReg2 | |
1481 | | SReg3 | |
1482 | | Control | |
1483 | | Debug | |
1484 | | Test | |
1485 | | RegMMX)) | |
1486 | ? 0 : 1); | |
355afbcd | 1487 | dest = source + 1; |
4498e3d6 ILT |
1488 | |
1489 | /* Certain instructions expect the destination to be | |
1490 | in the i.rm.reg field. This is by far the | |
1491 | exceptional case. For these instructions, if the | |
1492 | source operand is a register, we must reverse the | |
1493 | i.rm.reg and i.rm.regmem fields. We accomplish | |
1494 | this by pretending that the two register operands | |
1495 | were given in the reverse order. */ | |
1496 | if (i.tm.opcode_modifier & ReverseRegRegmem) | |
1497 | { | |
1498 | reg_entry *tmp = i.regs[source]; | |
1499 | i.regs[source] = i.regs[dest]; | |
1500 | i.regs[dest] = tmp; | |
1501 | } | |
1502 | ||
355afbcd | 1503 | i.rm.mode = 3; |
c5dd66a1 | 1504 | /* We must be careful to make sure that all |
454b0ccd | 1505 | segment/control/test/debug/MMX registers go into |
4498e3d6 | 1506 | the i.rm.reg field (despite whether they are |
454b0ccd ILT |
1507 | source or destination operands). */ |
1508 | if (i.regs[dest]->reg_type | |
1509 | & (SReg2 | SReg3 | Control | Debug | Test | RegMMX)) | |
355afbcd KR |
1510 | { |
1511 | i.rm.reg = i.regs[dest]->reg_num; | |
1512 | i.rm.regmem = i.regs[source]->reg_num; | |
1513 | } | |
1514 | else | |
1515 | { | |
1516 | i.rm.reg = i.regs[source]->reg_num; | |
1517 | i.rm.regmem = i.regs[dest]->reg_num; | |
1518 | } | |
1519 | } | |
1520 | else | |
1521 | { /* if it's not 2 reg operands... */ | |
1522 | if (i.mem_operands) | |
1523 | { | |
1524 | unsigned int fake_zero_displacement = 0; | |
4498e3d6 ILT |
1525 | unsigned int op = ((i.types[0] & Mem) |
1526 | ? 0 | |
1527 | : (i.types[1] & Mem) ? 1 : 2); | |
355afbcd | 1528 | |
49864cfa KR |
1529 | /* Encode memory operand into modrm byte and base index |
1530 | byte. */ | |
355afbcd KR |
1531 | |
1532 | if (i.base_reg == esp && !i.index_reg) | |
1533 | { | |
49864cfa KR |
1534 | /* <disp>(%esp) becomes two byte modrm with no index |
1535 | register. */ | |
355afbcd | 1536 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
ad660eb1 | 1537 | i.rm.mode = mode_from_disp_size (i.types[op]); |
355afbcd KR |
1538 | i.bi.base = ESP_REG_NUM; |
1539 | i.bi.index = NO_INDEX_REGISTER; | |
1540 | i.bi.scale = 0; /* Must be zero! */ | |
1541 | } | |
1542 | else if (i.base_reg == ebp && !i.index_reg) | |
1543 | { | |
ad660eb1 | 1544 | if (!(i.types[op] & Disp)) |
355afbcd | 1545 | { |
49864cfa KR |
1546 | /* Must fake a zero byte displacement. There is |
1547 | no direct way to code '(%ebp)' directly. */ | |
355afbcd KR |
1548 | fake_zero_displacement = 1; |
1549 | /* fake_zero_displacement code does not set this. */ | |
ad660eb1 | 1550 | i.types[op] |= Disp8; |
355afbcd | 1551 | } |
ad660eb1 | 1552 | i.rm.mode = mode_from_disp_size (i.types[op]); |
355afbcd KR |
1553 | i.rm.regmem = EBP_REG_NUM; |
1554 | } | |
ad660eb1 | 1555 | else if (!i.base_reg && (i.types[op] & BaseIndex)) |
355afbcd KR |
1556 | { |
1557 | /* There are three cases here. | |
c5dd66a1 KR |
1558 | Case 1: '<32bit disp>(,1)' -- indirect absolute. |
1559 | (Same as cases 2 & 3 with NO index register) | |
1560 | Case 2: <32bit disp> (,<index>) -- no base register with disp | |
1561 | Case 3: (, <index>) --- no base register; | |
1562 | no disp (must add 32bit 0 disp). */ | |
355afbcd KR |
1563 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
1564 | i.rm.mode = 0; /* 32bit mode */ | |
1565 | i.bi.base = NO_BASE_REGISTER; | |
ad660eb1 ILT |
1566 | i.types[op] &= ~Disp; |
1567 | i.types[op] |= Disp32; /* Must be 32bit! */ | |
355afbcd KR |
1568 | if (i.index_reg) |
1569 | { /* case 2 or case 3 */ | |
1570 | i.bi.index = i.index_reg->reg_num; | |
1571 | i.bi.scale = i.log2_scale_factor; | |
1572 | if (i.disp_operands == 0) | |
1573 | fake_zero_displacement = 1; /* case 3 */ | |
1574 | } | |
1575 | else | |
1576 | { | |
1577 | i.bi.index = NO_INDEX_REGISTER; | |
1578 | i.bi.scale = 0; | |
1579 | } | |
1580 | } | |
1581 | else if (i.disp_operands && !i.base_reg && !i.index_reg) | |
1582 | { | |
1583 | /* Operand is just <32bit disp> */ | |
1584 | i.rm.regmem = EBP_REG_NUM; | |
1585 | i.rm.mode = 0; | |
ad660eb1 ILT |
1586 | i.types[op] &= ~Disp; |
1587 | i.types[op] |= Disp32; | |
355afbcd KR |
1588 | } |
1589 | else | |
1590 | { | |
1591 | /* It's not a special case; rev'em up. */ | |
1592 | i.rm.regmem = i.base_reg->reg_num; | |
ad660eb1 | 1593 | i.rm.mode = mode_from_disp_size (i.types[op]); |
355afbcd KR |
1594 | if (i.index_reg) |
1595 | { | |
1596 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
1597 | i.bi.base = i.base_reg->reg_num; | |
1598 | i.bi.index = i.index_reg->reg_num; | |
1599 | i.bi.scale = i.log2_scale_factor; | |
1600 | if (i.base_reg == ebp && i.disp_operands == 0) | |
1601 | { /* pace */ | |
1602 | fake_zero_displacement = 1; | |
ad660eb1 ILT |
1603 | i.types[op] |= Disp8; |
1604 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
355afbcd KR |
1605 | } |
1606 | } | |
1607 | } | |
1608 | if (fake_zero_displacement) | |
1609 | { | |
ad660eb1 | 1610 | /* Fakes a zero displacement assuming that i.types[op] |
c5dd66a1 | 1611 | holds the correct displacement size. */ |
355afbcd | 1612 | exp = &disp_expressions[i.disp_operands++]; |
ad660eb1 | 1613 | i.disps[op] = exp; |
5ac34ac3 | 1614 | exp->X_op = O_constant; |
355afbcd KR |
1615 | exp->X_add_number = 0; |
1616 | exp->X_add_symbol = (symbolS *) 0; | |
5ac34ac3 | 1617 | exp->X_op_symbol = (symbolS *) 0; |
355afbcd KR |
1618 | } |
1619 | ||
4498e3d6 ILT |
1620 | /* Find the default segment for the memory operand. |
1621 | Used to optimize out explicit segment specifications. */ | |
1622 | if (i.seg[0]) | |
355afbcd KR |
1623 | { |
1624 | unsigned int seg_index; | |
355afbcd KR |
1625 | |
1626 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING) | |
1627 | { | |
1628 | seg_index = (i.rm.mode << 3) | i.bi.base; | |
1629 | default_seg = two_byte_segment_defaults[seg_index]; | |
1630 | } | |
1631 | else | |
1632 | { | |
1633 | seg_index = (i.rm.mode << 3) | i.rm.regmem; | |
1634 | default_seg = one_byte_segment_defaults[seg_index]; | |
1635 | } | |
355afbcd KR |
1636 | } |
1637 | } | |
1638 | ||
454b0ccd | 1639 | /* Fill in i.rm.reg or i.rm.regmem field with register |
227b6b55 ILT |
1640 | operand (if any) based on i.tm.extension_opcode. |
1641 | Again, we must be careful to make sure that | |
1642 | segment/control/debug/test/MMX registers are coded | |
1643 | into the i.rm.reg field. */ | |
355afbcd KR |
1644 | if (i.reg_operands) |
1645 | { | |
ad660eb1 | 1646 | unsigned int op = |
454b0ccd ILT |
1647 | ((i.types[0] |
1648 | & (Reg | SReg2 | SReg3 | Control | Debug | |
1649 | | Test | RegMMX)) | |
1650 | ? 0 | |
1651 | : ((i.types[1] | |
1652 | & (Reg | SReg2 | SReg3 | Control | Debug | |
1653 | | Test | RegMMX)) | |
1654 | ? 1 | |
1655 | : 2)); | |
c5dd66a1 KR |
1656 | /* If there is an extension opcode to put here, the |
1657 | register number must be put into the regmem field. */ | |
227b6b55 | 1658 | if (i.tm.extension_opcode != None) |
ad660eb1 | 1659 | i.rm.regmem = i.regs[op]->reg_num; |
355afbcd | 1660 | else |
ad660eb1 | 1661 | i.rm.reg = i.regs[op]->reg_num; |
355afbcd KR |
1662 | |
1663 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 | |
c5dd66a1 | 1664 | we must set it to 3 to indicate this is a register |
4498e3d6 | 1665 | operand in the regmem field. */ |
355afbcd KR |
1666 | if (!i.mem_operands) |
1667 | i.rm.mode = 3; | |
1668 | } | |
1669 | ||
1670 | /* Fill in i.rm.reg field with extension opcode (if any). */ | |
227b6b55 ILT |
1671 | if (i.tm.extension_opcode != None) |
1672 | i.rm.reg = i.tm.extension_opcode; | |
355afbcd | 1673 | } |
c54c7aac KR |
1674 | |
1675 | if (i.rm.mode != 3) | |
1676 | uses_mem_addrmode = 1; | |
1677 | } | |
4498e3d6 ILT |
1678 | else if (i.tm.opcode_modifier & Seg2ShortForm) |
1679 | { | |
1680 | if (i.tm.base_opcode == POP_SEG_SHORT && i.regs[0]->reg_num == 1) | |
1681 | { | |
1682 | as_bad ("you can't `pop %%cs' on the 386."); | |
1683 | return; | |
1684 | } | |
1685 | i.tm.base_opcode |= (i.regs[0]->reg_num << 3); | |
1686 | } | |
1687 | else if (i.tm.opcode_modifier & Seg3ShortForm) | |
1688 | { | |
1689 | /* 'push %fs' is 0x0fa0; 'pop %fs' is 0x0fa1. | |
1690 | 'push %gs' is 0x0fa8; 'pop %fs' is 0x0fa9. | |
1691 | So, only if i.regs[0]->reg_num == 5 (%gs) do we need | |
1692 | to change the opcode. */ | |
1693 | if (i.regs[0]->reg_num == 5) | |
1694 | i.tm.base_opcode |= 0x08; | |
1695 | } | |
1696 | else if ((i.tm.base_opcode & ~DW) == MOV_AX_DISP32) | |
1697 | { | |
1698 | /* This is a special non-modrm instruction | |
1699 | that addresses memory with a 32-bit displacement mode anyway, | |
1700 | and thus requires an address-size prefix if in 16-bit mode. */ | |
1701 | uses_mem_addrmode = 1; | |
1702 | default_seg = &ds; | |
1703 | } | |
1704 | else if ((i.tm.opcode_modifier & IsString) != 0) | |
1705 | { | |
1706 | /* For the string instructions that allow a segment override | |
1707 | on one of their operands, the default segment is ds. */ | |
1708 | default_seg = &ds; | |
1709 | } | |
c54c7aac KR |
1710 | |
1711 | /* GAS currently doesn't support 16-bit memory addressing modes at all, | |
1712 | so if we're writing 16-bit code and using a memory addressing mode, | |
1713 | always spew out an address size prefix. */ | |
1714 | if (uses_mem_addrmode && flag_16bit_code) | |
1715 | { | |
4498e3d6 ILT |
1716 | if (! check_prefix (ADDR_PREFIX_OPCODE)) |
1717 | return; | |
c54c7aac KR |
1718 | i.prefix[i.prefixes++] = ADDR_PREFIX_OPCODE; |
1719 | } | |
1720 | ||
1721 | /* If a segment was explicitly specified, | |
1722 | and the specified segment is not the default, | |
1723 | use an opcode prefix to select it. | |
1724 | If we never figured out what the default segment is, | |
1725 | then default_seg will be zero at this point, | |
1726 | and the specified segment prefix will always be used. */ | |
4498e3d6 | 1727 | if ((i.seg[0]) && (i.seg[0] != default_seg)) |
c54c7aac | 1728 | { |
4498e3d6 ILT |
1729 | if (! check_prefix (i.seg[0]->seg_prefix)) |
1730 | return; | |
1731 | i.prefix[i.prefixes++] = i.seg[0]->seg_prefix; | |
355afbcd KR |
1732 | } |
1733 | } | |
1734 | } | |
1735 | ||
1736 | /* Handle conversion of 'int $3' --> special int3 insn. */ | |
227b6b55 | 1737 | if (i.tm.base_opcode == INT_OPCODE && i.imms[0]->X_add_number == 3) |
355afbcd | 1738 | { |
227b6b55 | 1739 | i.tm.base_opcode = INT3_OPCODE; |
355afbcd KR |
1740 | i.imm_operands = 0; |
1741 | } | |
1742 | ||
1743 | /* We are ready to output the insn. */ | |
1744 | { | |
1745 | register char *p; | |
1746 | ||
1747 | /* Output jumps. */ | |
227b6b55 | 1748 | if (i.tm.opcode_modifier & Jump) |
355afbcd | 1749 | { |
ad660eb1 | 1750 | unsigned long n = i.disps[0]->X_add_number; |
355afbcd | 1751 | |
4498e3d6 ILT |
1752 | if (i.prefixes != 0) |
1753 | as_warn ("skipping prefixes on this instruction"); | |
1754 | ||
5ac34ac3 | 1755 | if (i.disps[0]->X_op == O_constant) |
355afbcd | 1756 | { |
355afbcd KR |
1757 | if (fits_in_signed_byte (n)) |
1758 | { | |
1759 | p = frag_more (2); | |
ad660eb1 | 1760 | insn_size += 2; |
227b6b55 | 1761 | p[0] = i.tm.base_opcode; |
355afbcd | 1762 | p[1] = n; |
355afbcd | 1763 | } |
355afbcd | 1764 | else |
c54c7aac KR |
1765 | { /* It's an absolute word/dword displacement. */ |
1766 | ||
4498e3d6 | 1767 | /* Use 16-bit jumps only for 16-bit code, |
c54c7aac | 1768 | because text segments are limited to 64K anyway; |
4498e3d6 ILT |
1769 | Use 32-bit jumps for 32-bit code, because they're faster, |
1770 | and a 16-bit jump will clear the top 16 bits of %eip. */ | |
c54c7aac KR |
1771 | int jmp_size = flag_16bit_code ? 2 : 4; |
1772 | if (flag_16bit_code && !fits_in_signed_word (n)) | |
1773 | { | |
48401fcf | 1774 | as_bad (_("16-bit jump out of range")); |
c54c7aac KR |
1775 | return; |
1776 | } | |
1777 | ||
227b6b55 | 1778 | if (i.tm.base_opcode == JUMP_PC_RELATIVE) |
355afbcd KR |
1779 | { /* pace */ |
1780 | /* unconditional jump */ | |
c54c7aac KR |
1781 | p = frag_more (1 + jmp_size); |
1782 | insn_size += 1 + jmp_size; | |
7b23213f | 1783 | p[0] = (char) 0xe9; |
c54c7aac | 1784 | md_number_to_chars (&p[1], (valueT) n, jmp_size); |
355afbcd KR |
1785 | } |
1786 | else | |
1787 | { | |
1788 | /* conditional jump */ | |
c54c7aac KR |
1789 | p = frag_more (2 + jmp_size); |
1790 | insn_size += 2 + jmp_size; | |
355afbcd | 1791 | p[0] = TWO_BYTE_OPCODE_ESCAPE; |
227b6b55 | 1792 | p[1] = i.tm.base_opcode + 0x10; |
c54c7aac | 1793 | md_number_to_chars (&p[2], (valueT) n, jmp_size); |
355afbcd KR |
1794 | } |
1795 | } | |
49864cfa KR |
1796 | } |
1797 | else | |
1798 | { | |
c54c7aac KR |
1799 | if (flag_16bit_code) |
1800 | { | |
1801 | FRAG_APPEND_1_CHAR (WORD_PREFIX_OPCODE); | |
1802 | insn_size += 1; | |
1803 | } | |
1804 | ||
355afbcd | 1805 | /* It's a symbol; end frag & setup for relax. |
49864cfa KR |
1806 | Make sure there are more than 6 chars left in the current frag; |
1807 | if not we'll have to start a new one. */ | |
3ea36b53 | 1808 | frag_grow (7); |
355afbcd | 1809 | p = frag_more (1); |
ad660eb1 | 1810 | insn_size += 1; |
227b6b55 | 1811 | p[0] = i.tm.base_opcode; |
355afbcd KR |
1812 | frag_var (rs_machine_dependent, |
1813 | 6, /* 2 opcode/prefix + 4 displacement */ | |
1814 | 1, | |
1815 | ((unsigned char) *p == JUMP_PC_RELATIVE | |
1816 | ? ENCODE_RELAX_STATE (UNCOND_JUMP, BYTE) | |
1817 | : ENCODE_RELAX_STATE (COND_JUMP, BYTE)), | |
1818 | i.disps[0]->X_add_symbol, | |
f59fb6ca | 1819 | (offsetT) n, p); |
355afbcd KR |
1820 | } |
1821 | } | |
227b6b55 | 1822 | else if (i.tm.opcode_modifier & (JumpByte | JumpDword)) |
355afbcd | 1823 | { |
227b6b55 | 1824 | int size = (i.tm.opcode_modifier & JumpByte) ? 1 : 4; |
ad660eb1 | 1825 | unsigned long n = i.disps[0]->X_add_number; |
c54c7aac KR |
1826 | unsigned char *q; |
1827 | ||
1828 | /* The jcx/jecx instruction might need a data size prefix. */ | |
1829 | for (q = i.prefix; q < i.prefix + i.prefixes; q++) | |
1830 | { | |
1831 | if (*q == WORD_PREFIX_OPCODE) | |
1832 | { | |
02bdbd8b ILT |
1833 | /* The jcxz/jecxz instructions are marked with Data16 |
1834 | and Data32, which means that they may get | |
1835 | WORD_PREFIX_OPCODE added to the list of prefixes. | |
1836 | However, the are correctly distinguished using | |
1837 | ADDR_PREFIX_OPCODE. Here we look for | |
1838 | WORD_PREFIX_OPCODE, and actually emit | |
1839 | ADDR_PREFIX_OPCODE. This is a hack, but, then, so | |
1840 | is the instruction itself. | |
1841 | ||
625ea5db ILT |
1842 | If an explicit suffix is used for the loop |
1843 | instruction, that actually controls whether we use | |
1844 | cx vs. ecx. This is also controlled by | |
1845 | ADDR_PREFIX_OPCODE. | |
1846 | ||
02bdbd8b ILT |
1847 | I don't know if there is any valid case in which we |
1848 | want to emit WORD_PREFIX_OPCODE, but I am keeping | |
1849 | the old behaviour for safety. */ | |
1850 | ||
227b6b55 ILT |
1851 | if (IS_JUMP_ON_CX_ZERO (i.tm.base_opcode) |
1852 | || IS_LOOP_ECX_TIMES (i.tm.base_opcode)) | |
02bdbd8b ILT |
1853 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); |
1854 | else | |
1855 | FRAG_APPEND_1_CHAR (WORD_PREFIX_OPCODE); | |
c54c7aac KR |
1856 | insn_size += 1; |
1857 | break; | |
1858 | } | |
1859 | } | |
1860 | ||
1861 | if ((size == 4) && (flag_16bit_code)) | |
1862 | { | |
1863 | FRAG_APPEND_1_CHAR (WORD_PREFIX_OPCODE); | |
1864 | insn_size += 1; | |
1865 | } | |
355afbcd | 1866 | |
227b6b55 | 1867 | if (fits_in_unsigned_byte (i.tm.base_opcode)) |
355afbcd | 1868 | { |
227b6b55 | 1869 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); |
ad660eb1 | 1870 | insn_size += 1; |
355afbcd KR |
1871 | } |
1872 | else | |
1873 | { | |
1874 | p = frag_more (2); /* opcode can be at most two bytes */ | |
ad660eb1 | 1875 | insn_size += 2; |
355afbcd | 1876 | /* put out high byte first: can't use md_number_to_chars! */ |
227b6b55 ILT |
1877 | *p++ = (i.tm.base_opcode >> 8) & 0xff; |
1878 | *p = i.tm.base_opcode & 0xff; | |
355afbcd KR |
1879 | } |
1880 | ||
1881 | p = frag_more (size); | |
ad660eb1 | 1882 | insn_size += size; |
5ac34ac3 | 1883 | if (i.disps[0]->X_op == O_constant) |
355afbcd | 1884 | { |
ad660eb1 | 1885 | md_number_to_chars (p, (valueT) n, size); |
355afbcd KR |
1886 | if (size == 1 && !fits_in_signed_byte (n)) |
1887 | { | |
48401fcf | 1888 | as_bad (_("loop/jecx only takes byte displacement; %lu shortened to %d"), |
355afbcd KR |
1889 | n, *p); |
1890 | } | |
49864cfa KR |
1891 | } |
1892 | else | |
1893 | { | |
5ac34ac3 | 1894 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
f0b37b4a KR |
1895 | i.disps[0], 1, reloc (size, 1, i.disp_reloc[0])); |
1896 | ||
355afbcd KR |
1897 | } |
1898 | } | |
227b6b55 | 1899 | else if (i.tm.opcode_modifier & JumpInterSegment) |
355afbcd | 1900 | { |
4498e3d6 ILT |
1901 | if (i.prefixes != 0) |
1902 | as_warn ("skipping prefixes on this instruction"); | |
1903 | ||
c54c7aac KR |
1904 | if (flag_16bit_code) |
1905 | { | |
1906 | FRAG_APPEND_1_CHAR (WORD_PREFIX_OPCODE); | |
1907 | insn_size += 1; | |
1908 | } | |
1909 | ||
355afbcd | 1910 | p = frag_more (1 + 2 + 4); /* 1 opcode; 2 segment; 4 offset */ |
ad660eb1 | 1911 | insn_size += 1 + 2 + 4; |
227b6b55 | 1912 | p[0] = i.tm.base_opcode; |
5ac34ac3 | 1913 | if (i.imms[1]->X_op == O_constant) |
ad660eb1 | 1914 | md_number_to_chars (p + 1, (valueT) i.imms[1]->X_add_number, 4); |
355afbcd | 1915 | else |
5ac34ac3 | 1916 | fix_new_exp (frag_now, p + 1 - frag_now->fr_literal, 4, |
7b23213f | 1917 | i.imms[1], 0, BFD_RELOC_32); |
5ac34ac3 | 1918 | if (i.imms[0]->X_op != O_constant) |
48401fcf | 1919 | as_bad (_("can't handle non absolute segment in long call/jmp")); |
ad660eb1 | 1920 | md_number_to_chars (p + 5, (valueT) i.imms[0]->X_add_number, 2); |
355afbcd KR |
1921 | } |
1922 | else | |
1923 | { | |
1924 | /* Output normal instructions here. */ | |
1925 | unsigned char *q; | |
1926 | ||
4498e3d6 ILT |
1927 | /* Hack for fwait. It must come before any prefixes, as it |
1928 | really is an instruction rather than a prefix. */ | |
1929 | if ((i.tm.opcode_modifier & FWait) != 0) | |
1930 | { | |
1931 | p = frag_more (1); | |
1932 | insn_size += 1; | |
1933 | md_number_to_chars (p, (valueT) FWAIT_OPCODE, 1); | |
1934 | } | |
1935 | ||
1936 | /* The prefix bytes. */ | |
355afbcd KR |
1937 | for (q = i.prefix; q < i.prefix + i.prefixes; q++) |
1938 | { | |
1939 | p = frag_more (1); | |
ad660eb1 ILT |
1940 | insn_size += 1; |
1941 | md_number_to_chars (p, (valueT) *q, 1); | |
355afbcd KR |
1942 | } |
1943 | ||
1944 | /* Now the opcode; be careful about word order here! */ | |
227b6b55 | 1945 | if (fits_in_unsigned_byte (i.tm.base_opcode)) |
355afbcd | 1946 | { |
227b6b55 | 1947 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); |
ad660eb1 | 1948 | insn_size += 1; |
355afbcd | 1949 | } |
227b6b55 | 1950 | else if (fits_in_unsigned_word (i.tm.base_opcode)) |
355afbcd KR |
1951 | { |
1952 | p = frag_more (2); | |
ad660eb1 | 1953 | insn_size += 2; |
355afbcd | 1954 | /* put out high byte first: can't use md_number_to_chars! */ |
227b6b55 ILT |
1955 | *p++ = (i.tm.base_opcode >> 8) & 0xff; |
1956 | *p = i.tm.base_opcode & 0xff; | |
355afbcd KR |
1957 | } |
1958 | else | |
1959 | { /* opcode is either 3 or 4 bytes */ | |
227b6b55 | 1960 | if (i.tm.base_opcode & 0xff000000) |
355afbcd KR |
1961 | { |
1962 | p = frag_more (4); | |
ad660eb1 | 1963 | insn_size += 4; |
227b6b55 | 1964 | *p++ = (i.tm.base_opcode >> 24) & 0xff; |
355afbcd KR |
1965 | } |
1966 | else | |
ad660eb1 ILT |
1967 | { |
1968 | p = frag_more (3); | |
1969 | insn_size += 3; | |
1970 | } | |
227b6b55 ILT |
1971 | *p++ = (i.tm.base_opcode >> 16) & 0xff; |
1972 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
1973 | *p = (i.tm.base_opcode) & 0xff; | |
355afbcd KR |
1974 | } |
1975 | ||
1976 | /* Now the modrm byte and base index byte (if present). */ | |
227b6b55 | 1977 | if (i.tm.opcode_modifier & Modrm) |
355afbcd KR |
1978 | { |
1979 | p = frag_more (1); | |
ad660eb1 | 1980 | insn_size += 1; |
355afbcd | 1981 | /* md_number_to_chars (p, i.rm, 1); */ |
ad660eb1 ILT |
1982 | md_number_to_chars (p, |
1983 | (valueT) (i.rm.regmem << 0 | |
1984 | | i.rm.reg << 3 | |
1985 | | i.rm.mode << 6), | |
1986 | 1); | |
355afbcd | 1987 | /* If i.rm.regmem == ESP (4) && i.rm.mode != Mode 3 (Register mode) |
a39116f1 | 1988 | ==> need second modrm byte. */ |
355afbcd KR |
1989 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING && i.rm.mode != 3) |
1990 | { | |
1991 | p = frag_more (1); | |
ad660eb1 | 1992 | insn_size += 1; |
355afbcd | 1993 | /* md_number_to_chars (p, i.bi, 1); */ |
ad660eb1 ILT |
1994 | md_number_to_chars (p, (valueT) (i.bi.base << 0 |
1995 | | i.bi.index << 3 | |
1996 | | i.bi.scale << 6), | |
1997 | 1); | |
355afbcd KR |
1998 | } |
1999 | } | |
2000 | ||
2001 | if (i.disp_operands) | |
2002 | { | |
2003 | register unsigned int n; | |
2004 | ||
2005 | for (n = 0; n < i.operands; n++) | |
2006 | { | |
2007 | if (i.disps[n]) | |
2008 | { | |
5ac34ac3 | 2009 | if (i.disps[n]->X_op == O_constant) |
355afbcd KR |
2010 | { |
2011 | if (i.types[n] & (Disp8 | Abs8)) | |
2012 | { | |
2013 | p = frag_more (1); | |
ad660eb1 ILT |
2014 | insn_size += 1; |
2015 | md_number_to_chars (p, | |
2016 | (valueT) i.disps[n]->X_add_number, | |
2017 | 1); | |
355afbcd KR |
2018 | } |
2019 | else if (i.types[n] & (Disp16 | Abs16)) | |
2020 | { | |
2021 | p = frag_more (2); | |
ad660eb1 ILT |
2022 | insn_size += 2; |
2023 | md_number_to_chars (p, | |
2024 | (valueT) i.disps[n]->X_add_number, | |
2025 | 2); | |
355afbcd KR |
2026 | } |
2027 | else | |
2028 | { /* Disp32|Abs32 */ | |
2029 | p = frag_more (4); | |
ad660eb1 ILT |
2030 | insn_size += 4; |
2031 | md_number_to_chars (p, | |
2032 | (valueT) i.disps[n]->X_add_number, | |
2033 | 4); | |
355afbcd KR |
2034 | } |
2035 | } | |
2036 | else | |
49864cfa | 2037 | { /* not absolute_section */ |
355afbcd KR |
2038 | /* need a 32-bit fixup (don't support 8bit non-absolute disps) */ |
2039 | p = frag_more (4); | |
ad660eb1 | 2040 | insn_size += 4; |
5ac34ac3 | 2041 | fix_new_exp (frag_now, p - frag_now->fr_literal, 4, |
f0b37b4a KR |
2042 | i.disps[n], 0, |
2043 | TC_RELOC(i.disp_reloc[n], BFD_RELOC_32)); | |
355afbcd KR |
2044 | } |
2045 | } | |
2046 | } | |
2047 | } /* end displacement output */ | |
2048 | ||
2049 | /* output immediate */ | |
2050 | if (i.imm_operands) | |
2051 | { | |
2052 | register unsigned int n; | |
2053 | ||
2054 | for (n = 0; n < i.operands; n++) | |
2055 | { | |
2056 | if (i.imms[n]) | |
2057 | { | |
5ac34ac3 | 2058 | if (i.imms[n]->X_op == O_constant) |
355afbcd KR |
2059 | { |
2060 | if (i.types[n] & (Imm8 | Imm8S)) | |
2061 | { | |
2062 | p = frag_more (1); | |
ad660eb1 ILT |
2063 | insn_size += 1; |
2064 | md_number_to_chars (p, | |
2065 | (valueT) i.imms[n]->X_add_number, | |
2066 | 1); | |
355afbcd KR |
2067 | } |
2068 | else if (i.types[n] & Imm16) | |
2069 | { | |
2070 | p = frag_more (2); | |
ad660eb1 ILT |
2071 | insn_size += 2; |
2072 | md_number_to_chars (p, | |
2073 | (valueT) i.imms[n]->X_add_number, | |
2074 | 2); | |
355afbcd KR |
2075 | } |
2076 | else | |
2077 | { | |
2078 | p = frag_more (4); | |
ad660eb1 ILT |
2079 | insn_size += 4; |
2080 | md_number_to_chars (p, | |
2081 | (valueT) i.imms[n]->X_add_number, | |
2082 | 4); | |
355afbcd KR |
2083 | } |
2084 | } | |
2085 | else | |
49864cfa | 2086 | { /* not absolute_section */ |
f0b37b4a KR |
2087 | /* Need a 32-bit fixup (don't support 8bit |
2088 | non-absolute ims). Try to support other | |
2089 | sizes ... */ | |
2090 | int r_type; | |
355afbcd | 2091 | int size; |
f0b37b4a KR |
2092 | int pcrel = 0; |
2093 | ||
355afbcd KR |
2094 | if (i.types[n] & (Imm8 | Imm8S)) |
2095 | size = 1; | |
2096 | else if (i.types[n] & Imm16) | |
2097 | size = 2; | |
2098 | else | |
2099 | size = 4; | |
f0b37b4a | 2100 | r_type = reloc (size, 0, i.disp_reloc[0]); |
355afbcd | 2101 | p = frag_more (size); |
ad660eb1 | 2102 | insn_size += size; |
f0b37b4a | 2103 | #ifdef BFD_ASSEMBLER |
c54c7aac | 2104 | if (r_type == BFD_RELOC_32 |
f0b37b4a | 2105 | && GOT_symbol |
0877841d ILT |
2106 | && GOT_symbol == i.imms[n]->X_add_symbol |
2107 | && (i.imms[n]->X_op == O_symbol | |
2108 | || (i.imms[n]->X_op == O_add | |
2109 | && (i.imms[n]->X_op_symbol->sy_value.X_op | |
2110 | == O_subtract)))) | |
f0b37b4a KR |
2111 | { |
2112 | r_type = BFD_RELOC_386_GOTPC; | |
2113 | i.imms[n]->X_add_number += 3; | |
2114 | } | |
2115 | #endif | |
5ac34ac3 | 2116 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
f0b37b4a | 2117 | i.imms[n], pcrel, r_type); |
355afbcd KR |
2118 | } |
2119 | } | |
2120 | } | |
2121 | } /* end immediate output */ | |
2122 | } | |
2123 | ||
fecd2382 | 2124 | #ifdef DEBUG386 |
ade614d5 | 2125 | if (flag_debug) |
355afbcd KR |
2126 | { |
2127 | pi (line, &i); | |
2128 | } | |
fecd2382 | 2129 | #endif /* DEBUG386 */ |
355afbcd | 2130 | } |
fecd2382 RP |
2131 | } |
2132 | \f | |
2133 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero | |
2134 | on error. */ | |
2135 | ||
355afbcd KR |
2136 | static int |
2137 | i386_operand (operand_string) | |
2138 | char *operand_string; | |
fecd2382 | 2139 | { |
355afbcd KR |
2140 | register char *op_string = operand_string; |
2141 | ||
2142 | /* Address of '\0' at end of operand_string. */ | |
2143 | char *end_of_operand_string = operand_string + strlen (operand_string); | |
2144 | ||
2145 | /* Start and end of displacement string expression (if found). */ | |
2146 | char *displacement_string_start = NULL; | |
2147 | char *displacement_string_end = NULL; | |
2148 | ||
2149 | /* We check for an absolute prefix (differentiating, | |
3c8df4ba | 2150 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
355afbcd KR |
2151 | if (*op_string == ABSOLUTE_PREFIX) |
2152 | { | |
2153 | op_string++; | |
2154 | i.types[this_operand] |= JumpAbsolute; | |
2155 | } | |
2156 | ||
2157 | /* Check if operand is a register. */ | |
2158 | if (*op_string == REGISTER_PREFIX) | |
2159 | { | |
2160 | register reg_entry *r; | |
2161 | if (!(r = parse_register (op_string))) | |
2162 | { | |
48401fcf | 2163 | as_bad (_("bad register name `%s'"), op_string); |
355afbcd | 2164 | return 0; |
fecd2382 | 2165 | } |
355afbcd | 2166 | /* Check for segment override, rather than segment register by |
3c8df4ba | 2167 | searching for ':' after %<x>s where <x> = s, c, d, e, f, g. */ |
355afbcd KR |
2168 | if ((r->reg_type & (SReg2 | SReg3)) && op_string[3] == ':') |
2169 | { | |
2170 | switch (r->reg_num) | |
2171 | { | |
2172 | case 0: | |
4498e3d6 | 2173 | i.seg[i.mem_operands] = (seg_entry *) & es; |
355afbcd KR |
2174 | break; |
2175 | case 1: | |
4498e3d6 | 2176 | i.seg[i.mem_operands] = (seg_entry *) & cs; |
355afbcd KR |
2177 | break; |
2178 | case 2: | |
4498e3d6 | 2179 | i.seg[i.mem_operands] = (seg_entry *) & ss; |
355afbcd KR |
2180 | break; |
2181 | case 3: | |
4498e3d6 | 2182 | i.seg[i.mem_operands] = (seg_entry *) & ds; |
355afbcd KR |
2183 | break; |
2184 | case 4: | |
4498e3d6 | 2185 | i.seg[i.mem_operands] = (seg_entry *) & fs; |
355afbcd KR |
2186 | break; |
2187 | case 5: | |
4498e3d6 | 2188 | i.seg[i.mem_operands] = (seg_entry *) & gs; |
355afbcd KR |
2189 | break; |
2190 | } | |
2191 | op_string += 4; /* skip % <x> s : */ | |
2192 | operand_string = op_string; /* Pretend given string starts here. */ | |
2193 | if (!is_digit_char (*op_string) && !is_identifier_char (*op_string) | |
2194 | && *op_string != '(' && *op_string != ABSOLUTE_PREFIX) | |
2195 | { | |
48401fcf | 2196 | as_bad (_("bad memory operand `%s'"), op_string); |
355afbcd KR |
2197 | return 0; |
2198 | } | |
2199 | /* Handle case of %es:*foo. */ | |
2200 | if (*op_string == ABSOLUTE_PREFIX) | |
2201 | { | |
2202 | op_string++; | |
2203 | i.types[this_operand] |= JumpAbsolute; | |
2204 | } | |
2205 | goto do_memory_reference; | |
2206 | } | |
2207 | i.types[this_operand] |= r->reg_type; | |
2208 | i.regs[this_operand] = r; | |
2209 | i.reg_operands++; | |
2210 | } | |
2211 | else if (*op_string == IMMEDIATE_PREFIX) | |
2212 | { /* ... or an immediate */ | |
2213 | char *save_input_line_pointer; | |
49864cfa | 2214 | segT exp_seg = 0; |
355afbcd KR |
2215 | expressionS *exp; |
2216 | ||
2217 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
2218 | { | |
48401fcf | 2219 | as_bad (_("only 1 or 2 immediate operands are allowed")); |
355afbcd KR |
2220 | return 0; |
2221 | } | |
542e1629 | 2222 | |
355afbcd KR |
2223 | exp = &im_expressions[i.imm_operands++]; |
2224 | i.imms[this_operand] = exp; | |
2225 | save_input_line_pointer = input_line_pointer; | |
2226 | input_line_pointer = ++op_string; /* must advance op_string! */ | |
ad660eb1 | 2227 | SKIP_WHITESPACE (); |
355afbcd | 2228 | exp_seg = expression (exp); |
388fa5c6 | 2229 | if (*input_line_pointer != '\0') |
dddc8a82 ILT |
2230 | { |
2231 | /* This should be as_bad, but some versions of gcc, up to | |
2232 | about 2.8 and egcs 1.01, generate a bogus @GOTOFF(%ebx) | |
2233 | in certain cases. Oddly, the code in question turns out | |
2234 | to work correctly anyhow, so we make this just a warning | |
2235 | until those versions of gcc are obsolete. */ | |
48401fcf | 2236 | as_warn (_("unrecognized characters `%s' in expression"), |
dddc8a82 ILT |
2237 | input_line_pointer); |
2238 | } | |
355afbcd KR |
2239 | input_line_pointer = save_input_line_pointer; |
2240 | ||
7b23213f | 2241 | if (exp->X_op == O_absent) |
355afbcd | 2242 | { |
49864cfa | 2243 | /* missing or bad expr becomes absolute 0 */ |
48401fcf | 2244 | as_bad (_("missing or invalid immediate expression `%s' taken as 0"), |
355afbcd | 2245 | operand_string); |
5ac34ac3 | 2246 | exp->X_op = O_constant; |
355afbcd KR |
2247 | exp->X_add_number = 0; |
2248 | exp->X_add_symbol = (symbolS *) 0; | |
5ac34ac3 | 2249 | exp->X_op_symbol = (symbolS *) 0; |
355afbcd | 2250 | i.types[this_operand] |= Imm; |
49864cfa | 2251 | } |
7b23213f | 2252 | else if (exp->X_op == O_constant) |
49864cfa | 2253 | { |
ad660eb1 ILT |
2254 | i.types[this_operand] |= |
2255 | smallest_imm_type ((unsigned long) exp->X_add_number); | |
49864cfa | 2256 | } |
7b23213f | 2257 | #ifdef OBJ_AOUT |
49864cfa KR |
2258 | else if (exp_seg != text_section |
2259 | && exp_seg != data_section | |
2260 | && exp_seg != bss_section | |
2261 | && exp_seg != undefined_section | |
2262 | #ifdef BFD_ASSEMBLER | |
2263 | && ! bfd_is_com_section (exp_seg) | |
2264 | #endif | |
2265 | ) | |
2266 | { | |
355afbcd | 2267 | seg_unimplemented: |
48401fcf | 2268 | as_bad (_("Unimplemented segment type %d in parse_operand"), exp_seg); |
355afbcd KR |
2269 | return 0; |
2270 | } | |
49864cfa KR |
2271 | #endif |
2272 | else | |
2273 | { | |
2274 | /* this is an address ==> 32bit */ | |
2275 | i.types[this_operand] |= Imm32; | |
2276 | } | |
355afbcd | 2277 | /* shorten this type of this operand if the instruction wants |
49864cfa KR |
2278 | * fewer bits than are present in the immediate. The bit field |
2279 | * code can put out 'andb $0xffffff, %al', for example. pace | |
2280 | * also 'movw $foo,(%eax)' | |
2281 | */ | |
355afbcd KR |
2282 | switch (i.suffix) |
2283 | { | |
2284 | case WORD_OPCODE_SUFFIX: | |
2285 | i.types[this_operand] |= Imm16; | |
2286 | break; | |
2287 | case BYTE_OPCODE_SUFFIX: | |
2288 | i.types[this_operand] |= Imm16 | Imm8 | Imm8S; | |
2289 | break; | |
2290 | } | |
2291 | } | |
2292 | else if (is_digit_char (*op_string) || is_identifier_char (*op_string) | |
2293 | || *op_string == '(') | |
2294 | { | |
2295 | /* This is a memory reference of some sort. */ | |
2296 | register char *base_string; | |
2297 | unsigned int found_base_index_form; | |
2298 | ||
2299 | do_memory_reference: | |
4498e3d6 ILT |
2300 | if ((i.mem_operands == 1 |
2301 | && (current_templates->start->opcode_modifier & IsString) == 0) | |
2302 | || i.mem_operands == 2) | |
355afbcd | 2303 | { |
48401fcf | 2304 | as_bad (_("too many memory references for `%s'"), |
4498e3d6 | 2305 | current_templates->start->name); |
355afbcd KR |
2306 | return 0; |
2307 | } | |
2308 | i.mem_operands++; | |
2309 | ||
2310 | /* Determine type of memory operand from opcode_suffix; | |
227b6b55 | 2311 | no opcode suffix implies general memory references. */ |
355afbcd KR |
2312 | switch (i.suffix) |
2313 | { | |
2314 | case BYTE_OPCODE_SUFFIX: | |
2315 | i.types[this_operand] |= Mem8; | |
2316 | break; | |
2317 | case WORD_OPCODE_SUFFIX: | |
2318 | i.types[this_operand] |= Mem16; | |
2319 | break; | |
2320 | case DWORD_OPCODE_SUFFIX: | |
2321 | default: | |
2322 | i.types[this_operand] |= Mem32; | |
2323 | } | |
2324 | ||
49864cfa KR |
2325 | /* Check for base index form. We detect the base index form by |
2326 | looking for an ')' at the end of the operand, searching | |
2327 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
2328 | after it. */ | |
355afbcd KR |
2329 | base_string = end_of_operand_string - 1; |
2330 | found_base_index_form = 0; | |
2331 | if (*base_string == ')') | |
2332 | { | |
0b476c53 | 2333 | unsigned int parens_balanced = 1; |
49864cfa KR |
2334 | /* We've already checked that the number of left & right ()'s are |
2335 | equal, so this loop will not be infinite. */ | |
355afbcd KR |
2336 | do |
2337 | { | |
2338 | base_string--; | |
2339 | if (*base_string == ')') | |
0b476c53 | 2340 | parens_balanced++; |
355afbcd | 2341 | if (*base_string == '(') |
0b476c53 | 2342 | parens_balanced--; |
355afbcd | 2343 | } |
0b476c53 | 2344 | while (parens_balanced); |
355afbcd KR |
2345 | base_string++; /* Skip past '('. */ |
2346 | if (*base_string == REGISTER_PREFIX || *base_string == ',') | |
2347 | found_base_index_form = 1; | |
2348 | } | |
2349 | ||
2350 | /* If we can't parse a base index register expression, we've found | |
49864cfa KR |
2351 | a pure displacement expression. We set up displacement_string_start |
2352 | and displacement_string_end for the code below. */ | |
355afbcd KR |
2353 | if (!found_base_index_form) |
2354 | { | |
2355 | displacement_string_start = op_string; | |
2356 | displacement_string_end = end_of_operand_string; | |
2357 | } | |
2358 | else | |
2359 | { | |
2360 | char *base_reg_name, *index_reg_name, *num_string; | |
2361 | int num; | |
2362 | ||
2363 | i.types[this_operand] |= BaseIndex; | |
2364 | ||
2365 | /* If there is a displacement set-up for it to be parsed later. */ | |
2366 | if (base_string != op_string + 1) | |
2367 | { | |
2368 | displacement_string_start = op_string; | |
2369 | displacement_string_end = base_string - 1; | |
2370 | } | |
2371 | ||
2372 | /* Find base register (if any). */ | |
2373 | if (*base_string != ',') | |
2374 | { | |
2375 | base_reg_name = base_string++; | |
2376 | /* skip past register name & parse it */ | |
2377 | while (isalpha (*base_string)) | |
2378 | base_string++; | |
2379 | if (base_string == base_reg_name + 1) | |
2380 | { | |
48401fcf | 2381 | as_bad (_("can't find base register name after `(%c'"), |
355afbcd KR |
2382 | REGISTER_PREFIX); |
2383 | return 0; | |
2384 | } | |
2385 | END_STRING_AND_SAVE (base_string); | |
2386 | if (!(i.base_reg = parse_register (base_reg_name))) | |
2387 | { | |
48401fcf | 2388 | as_bad (_("bad base register name `%s'"), base_reg_name); |
4498e3d6 | 2389 | RESTORE_END_STRING (base_string); |
355afbcd KR |
2390 | return 0; |
2391 | } | |
2392 | RESTORE_END_STRING (base_string); | |
2393 | } | |
2394 | ||
2395 | /* Now check seperator; must be ',' ==> index reg | |
a39116f1 RP |
2396 | OR num ==> no index reg. just scale factor |
2397 | OR ')' ==> end. (scale factor = 1) */ | |
355afbcd KR |
2398 | if (*base_string != ',' && *base_string != ')') |
2399 | { | |
48401fcf | 2400 | as_bad (_("expecting `,' or `)' after base register in `%s'"), |
355afbcd KR |
2401 | operand_string); |
2402 | return 0; | |
2403 | } | |
2404 | ||
2405 | /* There may index reg here; and there may be a scale factor. */ | |
2406 | if (*base_string == ',' && *(base_string + 1) == REGISTER_PREFIX) | |
2407 | { | |
2408 | index_reg_name = ++base_string; | |
2409 | while (isalpha (*++base_string)); | |
2410 | END_STRING_AND_SAVE (base_string); | |
2411 | if (!(i.index_reg = parse_register (index_reg_name))) | |
2412 | { | |
48401fcf | 2413 | as_bad (_("bad index register name `%s'"), index_reg_name); |
4498e3d6 | 2414 | RESTORE_END_STRING (base_string); |
355afbcd | 2415 | return 0; |
a39116f1 | 2416 | } |
355afbcd KR |
2417 | RESTORE_END_STRING (base_string); |
2418 | } | |
2419 | ||
2420 | /* Check for scale factor. */ | |
2421 | if (*base_string == ',' && isdigit (*(base_string + 1))) | |
2422 | { | |
2423 | num_string = ++base_string; | |
2424 | while (is_digit_char (*base_string)) | |
2425 | base_string++; | |
2426 | if (base_string == num_string) | |
2427 | { | |
48401fcf | 2428 | as_bad (_("can't find a scale factor after `,'")); |
355afbcd | 2429 | return 0; |
a39116f1 | 2430 | } |
355afbcd KR |
2431 | END_STRING_AND_SAVE (base_string); |
2432 | /* We've got a scale factor. */ | |
2433 | if (!sscanf (num_string, "%d", &num)) | |
2434 | { | |
48401fcf | 2435 | as_bad (_("can't parse scale factor from `%s'"), num_string); |
4498e3d6 | 2436 | RESTORE_END_STRING (base_string); |
355afbcd | 2437 | return 0; |
a39116f1 | 2438 | } |
355afbcd KR |
2439 | RESTORE_END_STRING (base_string); |
2440 | switch (num) | |
2441 | { /* must be 1 digit scale */ | |
2442 | case 1: | |
2443 | i.log2_scale_factor = 0; | |
2444 | break; | |
2445 | case 2: | |
2446 | i.log2_scale_factor = 1; | |
2447 | break; | |
2448 | case 4: | |
2449 | i.log2_scale_factor = 2; | |
2450 | break; | |
2451 | case 8: | |
2452 | i.log2_scale_factor = 3; | |
2453 | break; | |
2454 | default: | |
48401fcf | 2455 | as_bad (_("expecting scale factor of 1, 2, 4, 8; got %d"), num); |
355afbcd | 2456 | return 0; |
a39116f1 | 2457 | } |
355afbcd KR |
2458 | } |
2459 | else | |
2460 | { | |
2461 | if (!i.index_reg && *base_string == ',') | |
2462 | { | |
48401fcf | 2463 | as_bad (_("expecting index register or scale factor after `,'; got '%c'"), |
355afbcd KR |
2464 | *(base_string + 1)); |
2465 | return 0; | |
a39116f1 | 2466 | } |
355afbcd KR |
2467 | } |
2468 | } | |
2469 | ||
2470 | /* If there's an expression begining the operand, parse it, | |
49864cfa KR |
2471 | assuming displacement_string_start and displacement_string_end |
2472 | are meaningful. */ | |
355afbcd KR |
2473 | if (displacement_string_start) |
2474 | { | |
2475 | register expressionS *exp; | |
49864cfa | 2476 | segT exp_seg = 0; |
355afbcd KR |
2477 | char *save_input_line_pointer; |
2478 | exp = &disp_expressions[i.disp_operands]; | |
2479 | i.disps[this_operand] = exp; | |
f0b37b4a | 2480 | i.disp_reloc[this_operand] = NO_RELOC; |
355afbcd KR |
2481 | i.disp_operands++; |
2482 | save_input_line_pointer = input_line_pointer; | |
2483 | input_line_pointer = displacement_string_start; | |
2484 | END_STRING_AND_SAVE (displacement_string_end); | |
a52f90a4 | 2485 | |
30355216 | 2486 | #ifndef LEX_AT |
f0b37b4a KR |
2487 | { |
2488 | /* | |
2489 | * We can have operands of the form | |
2490 | * <symbol>@GOTOFF+<nnn> | |
2491 | * Take the easy way out here and copy everything | |
2492 | * into a temporary buffer... | |
2493 | */ | |
2494 | register char *cp; | |
a52f90a4 ILT |
2495 | |
2496 | cp = strchr (input_line_pointer, '@'); | |
2497 | if (cp != NULL) | |
2498 | { | |
2499 | char *tmpbuf; | |
2500 | ||
2501 | if (GOT_symbol == NULL) | |
2502 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); | |
2503 | ||
2504 | tmpbuf = (char *) alloca ((cp - input_line_pointer) + 20); | |
2505 | ||
2506 | if (strncmp (cp + 1, "PLT", 3) == 0) | |
2507 | { | |
2508 | i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32; | |
2509 | *cp = '\0'; | |
2510 | strcpy (tmpbuf, input_line_pointer); | |
2511 | strcat (tmpbuf, cp + 1 + 3); | |
2512 | *cp = '@'; | |
2513 | } | |
2514 | else if (strncmp (cp + 1, "GOTOFF", 6) == 0) | |
2515 | { | |
2516 | i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF; | |
2517 | *cp = '\0'; | |
2518 | strcpy (tmpbuf, input_line_pointer); | |
2519 | strcat (tmpbuf, cp + 1 + 6); | |
2520 | *cp = '@'; | |
2521 | } | |
2522 | else if (strncmp (cp + 1, "GOT", 3) == 0) | |
2523 | { | |
2524 | i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32; | |
2525 | *cp = '\0'; | |
2526 | strcpy (tmpbuf, input_line_pointer); | |
2527 | strcat (tmpbuf, cp + 1 + 3); | |
2528 | *cp = '@'; | |
2529 | } | |
2530 | else | |
48401fcf | 2531 | as_bad (_("Bad reloc specifier `%s' in expression"), cp + 1); |
a52f90a4 ILT |
2532 | |
2533 | input_line_pointer = tmpbuf; | |
2534 | } | |
f0b37b4a | 2535 | } |
30355216 | 2536 | #endif |
a52f90a4 | 2537 | |
355afbcd | 2538 | exp_seg = expression (exp); |
f0b37b4a KR |
2539 | |
2540 | #ifdef BFD_ASSEMBLER | |
2541 | /* We do this to make sure that the section symbol is in | |
2542 | the symbol table. We will ultimately change the relocation | |
2543 | to be relative to the beginning of the section */ | |
c54c7aac KR |
2544 | if (i.disp_reloc[this_operand] == BFD_RELOC_386_GOTOFF) |
2545 | { | |
2546 | if (S_IS_LOCAL(exp->X_add_symbol) | |
2547 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section) | |
2548 | section_symbol(exp->X_add_symbol->bsym->section); | |
2549 | assert (exp->X_op == O_symbol); | |
2550 | exp->X_op = O_subtract; | |
2551 | exp->X_op_symbol = GOT_symbol; | |
2552 | i.disp_reloc[this_operand] = BFD_RELOC_32; | |
2553 | } | |
f0b37b4a KR |
2554 | #endif |
2555 | ||
355afbcd | 2556 | if (*input_line_pointer) |
48401fcf TT |
2557 | as_bad (_("Ignoring junk `%s' after expression"), |
2558 | input_line_pointer); | |
355afbcd KR |
2559 | RESTORE_END_STRING (displacement_string_end); |
2560 | input_line_pointer = save_input_line_pointer; | |
7b23213f | 2561 | if (exp->X_op == O_absent) |
355afbcd | 2562 | { |
355afbcd | 2563 | /* missing expr becomes absolute 0 */ |
48401fcf | 2564 | as_bad (_("missing or invalid displacement `%s' taken as 0"), |
355afbcd KR |
2565 | operand_string); |
2566 | i.types[this_operand] |= (Disp | Abs); | |
5ac34ac3 | 2567 | exp->X_op = O_constant; |
355afbcd KR |
2568 | exp->X_add_number = 0; |
2569 | exp->X_add_symbol = (symbolS *) 0; | |
5ac34ac3 | 2570 | exp->X_op_symbol = (symbolS *) 0; |
49864cfa | 2571 | } |
7b23213f | 2572 | else if (exp->X_op == O_constant) |
49864cfa | 2573 | { |
355afbcd | 2574 | i.types[this_operand] |= SMALLEST_DISP_TYPE (exp->X_add_number); |
49864cfa KR |
2575 | } |
2576 | else if (exp_seg == text_section | |
2577 | || exp_seg == data_section | |
2578 | || exp_seg == bss_section | |
2579 | || exp_seg == undefined_section) | |
2580 | { | |
355afbcd | 2581 | i.types[this_operand] |= Disp32; |
49864cfa KR |
2582 | } |
2583 | else | |
2584 | { | |
7b23213f | 2585 | #ifndef OBJ_AOUT |
49864cfa KR |
2586 | i.types[this_operand] |= Disp32; |
2587 | #else | |
355afbcd | 2588 | goto seg_unimplemented; |
49864cfa | 2589 | #endif |
355afbcd KR |
2590 | } |
2591 | } | |
2592 | ||
2593 | /* Make sure the memory operand we've been dealt is valid. */ | |
2594 | if (i.base_reg && i.index_reg && | |
2595 | !(i.base_reg->reg_type & i.index_reg->reg_type & Reg)) | |
2596 | { | |
48401fcf | 2597 | as_bad (_("register size mismatch in (base,index,scale) expression")); |
355afbcd KR |
2598 | return 0; |
2599 | } | |
2600 | /* | |
49864cfa KR |
2601 | * special case for (%dx) while doing input/output op |
2602 | */ | |
355afbcd KR |
2603 | if ((i.base_reg && |
2604 | (i.base_reg->reg_type == (Reg16 | InOutPortReg)) && | |
2605 | (i.index_reg == 0))) | |
49864cfa KR |
2606 | { |
2607 | i.types[this_operand] |= InOutPortReg; | |
2608 | return 1; | |
2609 | } | |
355afbcd KR |
2610 | if ((i.base_reg && (i.base_reg->reg_type & Reg32) == 0) || |
2611 | (i.index_reg && (i.index_reg->reg_type & Reg32) == 0)) | |
2612 | { | |
48401fcf | 2613 | as_bad (_("base/index register must be 32 bit register")); |
355afbcd KR |
2614 | return 0; |
2615 | } | |
2616 | if (i.index_reg && i.index_reg == esp) | |
2617 | { | |
48401fcf TT |
2618 | as_bad (_("`%%s' may not be used as an index register"), |
2619 | esp->reg_name); | |
355afbcd | 2620 | return 0; |
fecd2382 | 2621 | } |
355afbcd KR |
2622 | } |
2623 | else | |
2624 | { /* it's not a memory operand; argh! */ | |
48401fcf | 2625 | as_bad (_("invalid char %s begining %s operand `%s'"), |
355afbcd KR |
2626 | output_invalid (*op_string), ordinal_names[this_operand], |
2627 | op_string); | |
2628 | return 0; | |
2629 | } | |
2630 | return 1; /* normal return */ | |
fecd2382 RP |
2631 | } |
2632 | \f | |
2633 | /* | |
2634 | * md_estimate_size_before_relax() | |
2635 | * | |
2636 | * Called just before relax(). | |
2637 | * Any symbol that is now undefined will not become defined. | |
2638 | * Return the correct fr_subtype in the frag. | |
2639 | * Return the initial "guess for fr_var" to caller. | |
2640 | * The guess for fr_var is ACTUALLY the growth beyond fr_fix. | |
2641 | * Whatever we do to grow fr_fix or fr_var contributes to our returned value. | |
2642 | * Although it may not be explicit in the frag, pretend fr_var starts with a | |
2643 | * 0 value. | |
2644 | */ | |
2645 | int | |
355afbcd KR |
2646 | md_estimate_size_before_relax (fragP, segment) |
2647 | register fragS *fragP; | |
2648 | register segT segment; | |
fecd2382 | 2649 | { |
355afbcd KR |
2650 | register unsigned char *opcode; |
2651 | register int old_fr_fix; | |
2652 | ||
2653 | old_fr_fix = fragP->fr_fix; | |
2654 | opcode = (unsigned char *) fragP->fr_opcode; | |
2655 | /* We've already got fragP->fr_subtype right; all we have to do is check | |
a39116f1 | 2656 | for un-relaxable symbols. */ |
355afbcd KR |
2657 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment) |
2658 | { | |
2659 | /* symbol is undefined in this segment */ | |
2660 | switch (opcode[0]) | |
2661 | { | |
2662 | case JUMP_PC_RELATIVE: /* make jmp (0xeb) a dword displacement jump */ | |
2663 | opcode[0] = 0xe9; /* dword disp jmp */ | |
2664 | fragP->fr_fix += 4; | |
2665 | fix_new (fragP, old_fr_fix, 4, | |
f0b37b4a KR |
2666 | fragP->fr_symbol, |
2667 | fragP->fr_offset, 1, | |
2668 | (GOT_symbol && /* Not quite right - we should switch on | |
2669 | presence of @PLT, but I cannot see how | |
2670 | to get to that from here. We should have | |
2671 | done this in md_assemble to really | |
2672 | get it right all of the time, but I | |
2673 | think it does not matter that much, as | |
2674 | this will be right most of the time. ERY*/ | |
2675 | S_GET_SEGMENT(fragP->fr_symbol) == undefined_section)? | |
2676 | BFD_RELOC_386_PLT32 : BFD_RELOC_32_PCREL); | |
355afbcd KR |
2677 | break; |
2678 | ||
2679 | default: | |
2680 | /* This changes the byte-displacement jump 0x7N --> | |
a39116f1 | 2681 | the dword-displacement jump 0x0f8N */ |
355afbcd KR |
2682 | opcode[1] = opcode[0] + 0x10; |
2683 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; /* two-byte escape */ | |
2684 | fragP->fr_fix += 1 + 4; /* we've added an opcode byte */ | |
2685 | fix_new (fragP, old_fr_fix + 1, 4, | |
2686 | fragP->fr_symbol, | |
f0b37b4a KR |
2687 | fragP->fr_offset, 1, |
2688 | (GOT_symbol && /* Not quite right - we should switch on | |
2689 | presence of @PLT, but I cannot see how | |
2690 | to get to that from here. ERY */ | |
2691 | S_GET_SEGMENT(fragP->fr_symbol) == undefined_section)? | |
2692 | BFD_RELOC_386_PLT32 : BFD_RELOC_32_PCREL); | |
355afbcd | 2693 | break; |
a39116f1 | 2694 | } |
355afbcd KR |
2695 | frag_wane (fragP); |
2696 | } | |
2697 | return (fragP->fr_var + fragP->fr_fix - old_fr_fix); | |
fecd2382 RP |
2698 | } /* md_estimate_size_before_relax() */ |
2699 | \f | |
2700 | /* | |
2701 | * md_convert_frag(); | |
2702 | * | |
2703 | * Called after relax() is finished. | |
2704 | * In: Address of frag. | |
2705 | * fr_type == rs_machine_dependent. | |
2706 | * fr_subtype is what the address relaxed to. | |
2707 | * | |
2708 | * Out: Any fixSs and constants are set up. | |
2709 | * Caller will turn frag into a ".space 0". | |
2710 | */ | |
49864cfa | 2711 | #ifndef BFD_ASSEMBLER |
fecd2382 | 2712 | void |
3ea36b53 | 2713 | md_convert_frag (headers, sec, fragP) |
355afbcd | 2714 | object_headers *headers; |
3ea36b53 | 2715 | segT sec; |
355afbcd | 2716 | register fragS *fragP; |
49864cfa KR |
2717 | #else |
2718 | void | |
2719 | md_convert_frag (abfd, sec, fragP) | |
2720 | bfd *abfd; | |
2721 | segT sec; | |
2722 | register fragS *fragP; | |
2723 | #endif | |
fecd2382 | 2724 | { |
355afbcd KR |
2725 | register unsigned char *opcode; |
2726 | unsigned char *where_to_put_displacement = NULL; | |
2727 | unsigned int target_address; | |
2728 | unsigned int opcode_address; | |
2729 | unsigned int extension = 0; | |
2730 | int displacement_from_opcode_start; | |
2731 | ||
2732 | opcode = (unsigned char *) fragP->fr_opcode; | |
2733 | ||
2734 | /* Address we want to reach in file space. */ | |
2735 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; | |
7b23213f KR |
2736 | #ifdef BFD_ASSEMBLER /* not needed otherwise? */ |
2737 | target_address += fragP->fr_symbol->sy_frag->fr_address; | |
2738 | #endif | |
355afbcd KR |
2739 | |
2740 | /* Address opcode resides at in file space. */ | |
2741 | opcode_address = fragP->fr_address + fragP->fr_fix; | |
2742 | ||
2743 | /* Displacement from opcode start to fill into instruction. */ | |
2744 | displacement_from_opcode_start = target_address - opcode_address; | |
2745 | ||
2746 | switch (fragP->fr_subtype) | |
2747 | { | |
2748 | case ENCODE_RELAX_STATE (COND_JUMP, BYTE): | |
a39116f1 | 2749 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BYTE): |
355afbcd KR |
2750 | /* don't have to change opcode */ |
2751 | extension = 1; /* 1 opcode + 1 displacement */ | |
2752 | where_to_put_displacement = &opcode[1]; | |
2753 | break; | |
2754 | ||
2755 | case ENCODE_RELAX_STATE (COND_JUMP, WORD): | |
2756 | opcode[1] = TWO_BYTE_OPCODE_ESCAPE; | |
2757 | opcode[2] = opcode[0] + 0x10; | |
2758 | opcode[0] = WORD_PREFIX_OPCODE; | |
2759 | extension = 4; /* 3 opcode + 2 displacement */ | |
2760 | where_to_put_displacement = &opcode[3]; | |
2761 | break; | |
2762 | ||
2763 | case ENCODE_RELAX_STATE (UNCOND_JUMP, WORD): | |
2764 | opcode[1] = 0xe9; | |
2765 | opcode[0] = WORD_PREFIX_OPCODE; | |
2766 | extension = 3; /* 2 opcode + 2 displacement */ | |
2767 | where_to_put_displacement = &opcode[2]; | |
2768 | break; | |
2769 | ||
2770 | case ENCODE_RELAX_STATE (COND_JUMP, DWORD): | |
2771 | opcode[1] = opcode[0] + 0x10; | |
2772 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
2773 | extension = 5; /* 2 opcode + 4 displacement */ | |
2774 | where_to_put_displacement = &opcode[2]; | |
2775 | break; | |
2776 | ||
2777 | case ENCODE_RELAX_STATE (UNCOND_JUMP, DWORD): | |
2778 | opcode[0] = 0xe9; | |
2779 | extension = 4; /* 1 opcode + 4 displacement */ | |
2780 | where_to_put_displacement = &opcode[1]; | |
2781 | break; | |
2782 | ||
2783 | default: | |
2784 | BAD_CASE (fragP->fr_subtype); | |
2785 | break; | |
2786 | } | |
2787 | /* now put displacement after opcode */ | |
2788 | md_number_to_chars ((char *) where_to_put_displacement, | |
ad660eb1 | 2789 | (valueT) (displacement_from_opcode_start - extension), |
355afbcd KR |
2790 | SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
2791 | fragP->fr_fix += extension; | |
fecd2382 | 2792 | } |
fecd2382 | 2793 | \f |
355afbcd | 2794 | |
fecd2382 | 2795 | int md_short_jump_size = 2; /* size of byte displacement jmp */ |
355afbcd | 2796 | int md_long_jump_size = 5; /* size of dword displacement jmp */ |
49864cfa | 2797 | const int md_reloc_size = 8; /* Size of relocation record */ |
fecd2382 | 2798 | |
355afbcd KR |
2799 | void |
2800 | md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol) | |
2801 | char *ptr; | |
025b0302 | 2802 | addressT from_addr, to_addr; |
355afbcd KR |
2803 | fragS *frag; |
2804 | symbolS *to_symbol; | |
fecd2382 | 2805 | { |
355afbcd KR |
2806 | long offset; |
2807 | ||
2808 | offset = to_addr - (from_addr + 2); | |
ad660eb1 ILT |
2809 | md_number_to_chars (ptr, (valueT) 0xeb, 1); /* opcode for byte-disp jump */ |
2810 | md_number_to_chars (ptr + 1, (valueT) offset, 1); | |
fecd2382 RP |
2811 | } |
2812 | ||
355afbcd KR |
2813 | void |
2814 | md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol) | |
2815 | char *ptr; | |
025b0302 | 2816 | addressT from_addr, to_addr; |
355afbcd KR |
2817 | fragS *frag; |
2818 | symbolS *to_symbol; | |
fecd2382 | 2819 | { |
355afbcd KR |
2820 | long offset; |
2821 | ||
ade614d5 | 2822 | if (flag_do_long_jump) |
355afbcd KR |
2823 | { |
2824 | offset = to_addr - S_GET_VALUE (to_symbol); | |
ad660eb1 ILT |
2825 | md_number_to_chars (ptr, (valueT) 0xe9, 1);/* opcode for long jmp */ |
2826 | md_number_to_chars (ptr + 1, (valueT) offset, 4); | |
355afbcd | 2827 | fix_new (frag, (ptr + 1) - frag->fr_literal, 4, |
7b23213f | 2828 | to_symbol, (offsetT) 0, 0, BFD_RELOC_32); |
355afbcd KR |
2829 | } |
2830 | else | |
2831 | { | |
2832 | offset = to_addr - (from_addr + 5); | |
ad660eb1 ILT |
2833 | md_number_to_chars (ptr, (valueT) 0xe9, 1); |
2834 | md_number_to_chars (ptr + 1, (valueT) offset, 4); | |
355afbcd | 2835 | } |
fecd2382 RP |
2836 | } |
2837 | \f | |
fecd2382 | 2838 | /* Apply a fixup (fixS) to segment data, once it has been determined |
355afbcd KR |
2839 | by our caller that we have all the info we need to fix it up. |
2840 | ||
fecd2382 RP |
2841 | On the 386, immediates, displacements, and data pointers are all in |
2842 | the same (little-endian) format, so we don't need to care about which | |
2843 | we are handling. */ | |
2844 | ||
3ea36b53 ILT |
2845 | int |
2846 | md_apply_fix3 (fixP, valp, seg) | |
2847 | fixS *fixP; /* The fix we're to put in. */ | |
2848 | valueT *valp; /* Pointer to the value of the bits. */ | |
2849 | segT seg; /* Segment fix is from. */ | |
fecd2382 | 2850 | { |
355afbcd | 2851 | register char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
3ea36b53 | 2852 | valueT value = *valp; |
355afbcd | 2853 | |
388fa5c6 ILT |
2854 | if (fixP->fx_r_type == BFD_RELOC_32 && fixP->fx_pcrel) |
2855 | fixP->fx_r_type = BFD_RELOC_32_PCREL; | |
2856 | ||
f3d817d8 | 2857 | #if defined (BFD_ASSEMBLER) && !defined (TE_Mach) |
7b23213f KR |
2858 | /* |
2859 | * This is a hack. There should be a better way to | |
2860 | * handle this. | |
2861 | */ | |
2862 | if (fixP->fx_r_type == BFD_RELOC_32_PCREL && fixP->fx_addsy) | |
2863 | { | |
0b476c53 | 2864 | #ifndef OBJ_AOUT |
76fb6d2f ILT |
2865 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour |
2866 | || OUTPUT_FLAVOR == bfd_target_coff_flavour) | |
590c50d8 | 2867 | value += fixP->fx_where + fixP->fx_frag->fr_address; |
0b476c53 | 2868 | #endif |
590c50d8 ILT |
2869 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
2870 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
2871 | && (S_GET_SEGMENT (fixP->fx_addsy) == seg | |
2872 | || (fixP->fx_addsy->bsym->flags & BSF_SECTION_SYM) != 0)) | |
f3d817d8 DM |
2873 | { |
2874 | /* Yes, we add the values in twice. This is because | |
2875 | bfd_perform_relocation subtracts them out again. I think | |
2876 | bfd_perform_relocation is broken, but I don't dare change | |
2877 | it. FIXME. */ | |
2878 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
2879 | } | |
76fb6d2f ILT |
2880 | #endif |
2881 | #if defined (OBJ_COFF) && defined (TE_PE) | |
2882 | /* For some reason, the PE format does not store a section | |
2883 | address offset for a PC relative symbol. */ | |
2884 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg) | |
2885 | value += md_pcrel_from (fixP); | |
7b23213f | 2886 | #endif |
355afbcd | 2887 | } |
f0b37b4a KR |
2888 | |
2889 | /* Fix a few things - the dynamic linker expects certain values here, | |
2890 | and we must not dissappoint it. */ | |
590c50d8 ILT |
2891 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
2892 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
2893 | && fixP->fx_addsy) | |
f0b37b4a KR |
2894 | switch(fixP->fx_r_type) { |
2895 | case BFD_RELOC_386_PLT32: | |
2896 | /* Make the jump instruction point to the address of the operand. At | |
2897 | runtime we merely add the offset to the actual PLT entry. */ | |
2898 | value = 0xfffffffc; | |
2899 | break; | |
2900 | case BFD_RELOC_386_GOTPC: | |
2901 | /* | |
2902 | * This is tough to explain. We end up with this one if we have | |
2903 | * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal | |
2904 | * here is to obtain the absolute address of the GOT, and it is strongly | |
2905 | * preferable from a performance point of view to avoid using a runtime | |
2906 | * relocation for this. The actual sequence of instructions often look | |
2907 | * something like: | |
2908 | * | |
2909 | * call .L66 | |
2910 | * .L66: | |
2911 | * popl %ebx | |
2912 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
2913 | * | |
2914 | * The call and pop essentially return the absolute address of | |
2915 | * the label .L66 and store it in %ebx. The linker itself will | |
2916 | * ultimately change the first operand of the addl so that %ebx points to | |
2917 | * the GOT, but to keep things simple, the .o file must have this operand | |
2918 | * set so that it generates not the absolute address of .L66, but the | |
2919 | * absolute address of itself. This allows the linker itself simply | |
2920 | * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be | |
2921 | * added in, and the addend of the relocation is stored in the operand | |
2922 | * field for the instruction itself. | |
2923 | * | |
2924 | * Our job here is to fix the operand so that it would add the correct | |
2925 | * offset so that %ebx would point to itself. The thing that is tricky is | |
2926 | * that .-.L66 will point to the beginning of the instruction, so we need | |
2927 | * to further modify the operand so that it will point to itself. | |
2928 | * There are other cases where you have something like: | |
2929 | * | |
2930 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
2931 | * | |
2932 | * and here no correction would be required. Internally in the assembler | |
2933 | * we treat operands of this form as not being pcrel since the '.' is | |
2934 | * explicitly mentioned, and I wonder whether it would simplify matters | |
2935 | * to do it this way. Who knows. In earlier versions of the PIC patches, | |
2936 | * the pcrel_adjust field was used to store the correction, but since the | |
2937 | * expression is not pcrel, I felt it would be confusing to do it this way. | |
2938 | */ | |
c54c7aac | 2939 | value -= 1; |
f0b37b4a KR |
2940 | break; |
2941 | case BFD_RELOC_386_GOT32: | |
2942 | value = 0; /* Fully resolved at runtime. No addend. */ | |
c54c7aac | 2943 | break; |
f0b37b4a | 2944 | case BFD_RELOC_386_GOTOFF: |
c54c7aac KR |
2945 | break; |
2946 | ||
f0b37b4a KR |
2947 | default: |
2948 | break; | |
2949 | } | |
2950 | #endif | |
2951 | ||
f3d817d8 DM |
2952 | #endif |
2953 | md_number_to_chars (p, value, fixP->fx_size); | |
fecd2382 | 2954 | |
49864cfa KR |
2955 | return 1; |
2956 | } | |
49864cfa | 2957 | |
ad660eb1 ILT |
2958 | #if 0 |
2959 | /* This is never used. */ | |
355afbcd KR |
2960 | long /* Knows about the byte order in a word. */ |
2961 | md_chars_to_number (con, nbytes) | |
2962 | unsigned char con[]; /* Low order byte 1st. */ | |
2963 | int nbytes; /* Number of bytes in the input. */ | |
fecd2382 | 2964 | { |
355afbcd KR |
2965 | long retval; |
2966 | for (retval = 0, con += nbytes - 1; nbytes--; con--) | |
2967 | { | |
2968 | retval <<= BITS_PER_CHAR; | |
2969 | retval |= *con; | |
2970 | } | |
2971 | return retval; | |
fecd2382 | 2972 | } |
ad660eb1 | 2973 | #endif /* 0 */ |
fecd2382 | 2974 | \f |
355afbcd | 2975 | |
fecd2382 RP |
2976 | #define MAX_LITTLENUMS 6 |
2977 | ||
2978 | /* Turn the string pointed to by litP into a floating point constant of type | |
2979 | type, and emit the appropriate bytes. The number of LITTLENUMS emitted | |
3c8df4ba | 2980 | is stored in *sizeP . An error message is returned, or NULL on OK. */ |
fecd2382 | 2981 | char * |
355afbcd KR |
2982 | md_atof (type, litP, sizeP) |
2983 | char type; | |
2984 | char *litP; | |
2985 | int *sizeP; | |
fecd2382 | 2986 | { |
355afbcd KR |
2987 | int prec; |
2988 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
2989 | LITTLENUM_TYPE *wordP; | |
2990 | char *t; | |
2991 | ||
2992 | switch (type) | |
2993 | { | |
2994 | case 'f': | |
2995 | case 'F': | |
2996 | prec = 2; | |
2997 | break; | |
2998 | ||
2999 | case 'd': | |
3000 | case 'D': | |
3001 | prec = 4; | |
3002 | break; | |
3003 | ||
3004 | case 'x': | |
3005 | case 'X': | |
3006 | prec = 5; | |
3007 | break; | |
3008 | ||
3009 | default: | |
3010 | *sizeP = 0; | |
48401fcf | 3011 | return _("Bad call to md_atof ()"); |
355afbcd KR |
3012 | } |
3013 | t = atof_ieee (input_line_pointer, type, words); | |
3014 | if (t) | |
3015 | input_line_pointer = t; | |
3016 | ||
3017 | *sizeP = prec * sizeof (LITTLENUM_TYPE); | |
3c8df4ba KR |
3018 | /* This loops outputs the LITTLENUMs in REVERSE order; in accord with |
3019 | the bigendian 386. */ | |
355afbcd KR |
3020 | for (wordP = words + prec - 1; prec--;) |
3021 | { | |
ad660eb1 | 3022 | md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE)); |
355afbcd KR |
3023 | litP += sizeof (LITTLENUM_TYPE); |
3024 | } | |
49864cfa | 3025 | return 0; |
fecd2382 RP |
3026 | } |
3027 | \f | |
3028 | char output_invalid_buf[8]; | |
3029 | ||
355afbcd KR |
3030 | static char * |
3031 | output_invalid (c) | |
3032 | char c; | |
fecd2382 | 3033 | { |
355afbcd KR |
3034 | if (isprint (c)) |
3035 | sprintf (output_invalid_buf, "'%c'", c); | |
3036 | else | |
3037 | sprintf (output_invalid_buf, "(0x%x)", (unsigned) c); | |
3038 | return output_invalid_buf; | |
fecd2382 RP |
3039 | } |
3040 | ||
7b23213f | 3041 | /* reg_string starts *before* REGISTER_PREFIX */ |
355afbcd KR |
3042 | static reg_entry * |
3043 | parse_register (reg_string) | |
3c8df4ba | 3044 | char *reg_string; |
fecd2382 | 3045 | { |
355afbcd KR |
3046 | register char *s = reg_string; |
3047 | register char *p; | |
3048 | char reg_name_given[MAX_REG_NAME_SIZE]; | |
3049 | ||
3050 | s++; /* skip REGISTER_PREFIX */ | |
3051 | for (p = reg_name_given; is_register_char (*s); p++, s++) | |
3052 | { | |
58d4951d | 3053 | *p = register_chars[(unsigned char) *s]; |
355afbcd KR |
3054 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) |
3055 | return (reg_entry *) 0; | |
3056 | } | |
3057 | *p = '\0'; | |
3058 | return (reg_entry *) hash_find (reg_hash, reg_name_given); | |
fecd2382 | 3059 | } |
f3d817d8 | 3060 | \f |
ade614d5 | 3061 | #ifdef OBJ_ELF |
3ea36b53 | 3062 | CONST char *md_shortopts = "kmVQ:"; |
ade614d5 KR |
3063 | #else |
3064 | CONST char *md_shortopts = "m"; | |
3065 | #endif | |
f3d817d8 DM |
3066 | struct option md_longopts[] = { |
3067 | {NULL, no_argument, NULL, 0} | |
3068 | }; | |
3069 | size_t md_longopts_size = sizeof(md_longopts); | |
fecd2382 | 3070 | |
f3d817d8 DM |
3071 | int |
3072 | md_parse_option (c, arg) | |
3073 | int c; | |
3074 | char *arg; | |
3075 | { | |
ade614d5 KR |
3076 | switch (c) |
3077 | { | |
3078 | case 'm': | |
3079 | flag_do_long_jump = 1; | |
3080 | break; | |
3081 | ||
590c50d8 | 3082 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
3ea36b53 ILT |
3083 | /* -k: Ignore for FreeBSD compatibility. */ |
3084 | case 'k': | |
3085 | break; | |
3086 | ||
ade614d5 KR |
3087 | /* -V: SVR4 argument to print version ID. */ |
3088 | case 'V': | |
3089 | print_version_id (); | |
3090 | break; | |
3091 | ||
3092 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section | |
3093 | should be emitted or not. FIXME: Not implemented. */ | |
3094 | case 'Q': | |
3095 | break; | |
3096 | #endif | |
3097 | ||
3098 | default: | |
3099 | return 0; | |
3100 | } | |
3101 | return 1; | |
f3d817d8 | 3102 | } |
fecd2382 | 3103 | |
f3d817d8 DM |
3104 | void |
3105 | md_show_usage (stream) | |
3106 | FILE *stream; | |
3107 | { | |
48401fcf TT |
3108 | fprintf (stream, _("\ |
3109 | -m do long jump\n")); | |
f3d817d8 | 3110 | } |
fecd2382 | 3111 | |
590c50d8 ILT |
3112 | #ifdef BFD_ASSEMBLER |
3113 | #ifdef OBJ_MAYBE_ELF | |
3114 | #ifdef OBJ_MAYBE_COFF | |
3115 | ||
3116 | /* Pick the target format to use. */ | |
3117 | ||
3118 | const char * | |
3119 | i386_target_format () | |
3120 | { | |
3121 | switch (OUTPUT_FLAVOR) | |
3122 | { | |
3123 | case bfd_target_coff_flavour: | |
3124 | return "coff-i386"; | |
3125 | case bfd_target_elf_flavour: | |
3126 | return "elf32-i386"; | |
3127 | default: | |
3128 | abort (); | |
3129 | return NULL; | |
3130 | } | |
3131 | } | |
3132 | ||
3133 | #endif /* OBJ_MAYBE_COFF */ | |
3134 | #endif /* OBJ_MAYBE_ELF */ | |
3135 | #endif /* BFD_ASSEMBLER */ | |
3136 | \f | |
fecd2382 RP |
3137 | /* ARGSUSED */ |
3138 | symbolS * | |
355afbcd KR |
3139 | md_undefined_symbol (name) |
3140 | char *name; | |
fecd2382 | 3141 | { |
f0b37b4a KR |
3142 | if (*name == '_' && *(name+1) == 'G' |
3143 | && strcmp(name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
3144 | { | |
3145 | if(!GOT_symbol) | |
3146 | { | |
3147 | if(symbol_find(name)) | |
48401fcf | 3148 | as_bad(_("GOT already in symbol table")); |
f0b37b4a KR |
3149 | GOT_symbol = symbol_new (name, undefined_section, |
3150 | (valueT) 0, &zero_address_frag); | |
3151 | }; | |
3152 | return GOT_symbol; | |
3153 | } | |
355afbcd | 3154 | return 0; |
fecd2382 RP |
3155 | } |
3156 | ||
fecd2382 | 3157 | /* Round up a section size to the appropriate boundary. */ |
3c8df4ba | 3158 | valueT |
355afbcd KR |
3159 | md_section_align (segment, size) |
3160 | segT segment; | |
3c8df4ba | 3161 | valueT size; |
fecd2382 | 3162 | { |
91951af6 ILT |
3163 | #ifdef OBJ_AOUT |
3164 | #ifdef BFD_ASSEMBLER | |
3165 | /* For a.out, force the section size to be aligned. If we don't do | |
3166 | this, BFD will align it for us, but it will not write out the | |
3167 | final bytes of the section. This may be a bug in BFD, but it is | |
3168 | easier to fix it here since that is how the other a.out targets | |
3169 | work. */ | |
3170 | int align; | |
3171 | ||
3172 | align = bfd_get_section_alignment (stdoutput, segment); | |
3173 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); | |
3174 | #endif | |
3175 | #endif | |
3176 | ||
3177 | return size; | |
fecd2382 RP |
3178 | } |
3179 | ||
7b23213f KR |
3180 | /* Exactly what point is a PC-relative offset relative TO? On the |
3181 | i386, they're relative to the address of the offset, plus its | |
3182 | size. (??? Is this right? FIXME-SOON!) */ | |
fecd2382 | 3183 | long |
355afbcd KR |
3184 | md_pcrel_from (fixP) |
3185 | fixS *fixP; | |
fecd2382 | 3186 | { |
355afbcd | 3187 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; |
fecd2382 RP |
3188 | } |
3189 | ||
49864cfa | 3190 | #ifndef I386COFF |
542e1629 | 3191 | |
49864cfa | 3192 | static void |
ad660eb1 ILT |
3193 | s_bss (ignore) |
3194 | int ignore; | |
542e1629 | 3195 | { |
49864cfa | 3196 | register int temp; |
542e1629 | 3197 | |
49864cfa | 3198 | temp = get_absolute_expression (); |
49864cfa | 3199 | subseg_set (bss_section, (subsegT) temp); |
49864cfa KR |
3200 | demand_empty_rest_of_line (); |
3201 | } | |
542e1629 | 3202 | |
49864cfa | 3203 | #endif |
355afbcd | 3204 | |
542e1629 | 3205 | |
49864cfa | 3206 | #ifdef BFD_ASSEMBLER |
c54c7aac KR |
3207 | |
3208 | void | |
3209 | i386_validate_fix (fixp) | |
3210 | fixS *fixp; | |
3211 | { | |
3212 | if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol) | |
3213 | { | |
3214 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
3215 | fixp->fx_subsy = 0; | |
3216 | } | |
3217 | } | |
3218 | ||
f0b37b4a KR |
3219 | #define F(SZ,PCREL) (((SZ) << 1) + (PCREL)) |
3220 | #define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break | |
542e1629 | 3221 | |
49864cfa KR |
3222 | arelent * |
3223 | tc_gen_reloc (section, fixp) | |
3224 | asection *section; | |
3225 | fixS *fixp; | |
542e1629 | 3226 | { |
ad660eb1 | 3227 | arelent *rel; |
49864cfa | 3228 | bfd_reloc_code_real_type code; |
542e1629 | 3229 | |
f0b37b4a | 3230 | switch(fixp->fx_r_type) |
49864cfa | 3231 | { |
f0b37b4a KR |
3232 | case BFD_RELOC_386_PLT32: |
3233 | case BFD_RELOC_386_GOT32: | |
3234 | case BFD_RELOC_386_GOTOFF: | |
3235 | case BFD_RELOC_386_GOTPC: | |
a52f90a4 | 3236 | case BFD_RELOC_RVA: |
f0b37b4a KR |
3237 | code = fixp->fx_r_type; |
3238 | break; | |
3239 | default: | |
3240 | switch (F (fixp->fx_size, fixp->fx_pcrel)) | |
3241 | { | |
f0b37b4a KR |
3242 | MAP (1, 0, BFD_RELOC_8); |
3243 | MAP (2, 0, BFD_RELOC_16); | |
f0b37b4a | 3244 | MAP (4, 0, BFD_RELOC_32); |
f0b37b4a KR |
3245 | MAP (1, 1, BFD_RELOC_8_PCREL); |
3246 | MAP (2, 1, BFD_RELOC_16_PCREL); | |
f0b37b4a KR |
3247 | MAP (4, 1, BFD_RELOC_32_PCREL); |
3248 | default: | |
48401fcf TT |
3249 | if (fixp->fx_pcrel) |
3250 | as_bad (_("Can not do %d byte pc-relative relocation"), | |
3251 | fixp->fx_size); | |
3252 | else | |
3253 | as_bad (_("Can not do %d byte relocation"), fixp->fx_size); | |
f0b37b4a | 3254 | } |
49864cfa | 3255 | } |
3c8df4ba KR |
3256 | #undef MAP |
3257 | #undef F | |
542e1629 | 3258 | |
f0b37b4a KR |
3259 | if (code == BFD_RELOC_32 |
3260 | && GOT_symbol | |
3261 | && fixp->fx_addsy == GOT_symbol) | |
3262 | code = BFD_RELOC_386_GOTPC; | |
3263 | ||
590c50d8 | 3264 | rel = (arelent *) xmalloc (sizeof (arelent)); |
ad660eb1 ILT |
3265 | rel->sym_ptr_ptr = &fixp->fx_addsy->bsym; |
3266 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
49864cfa | 3267 | if (fixp->fx_pcrel) |
ad660eb1 | 3268 | rel->addend = fixp->fx_addnumber; |
49864cfa | 3269 | else |
ad660eb1 | 3270 | rel->addend = 0; |
355afbcd | 3271 | |
ad660eb1 | 3272 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
e592f0e6 | 3273 | if (rel->howto == NULL) |
ad660eb1 | 3274 | { |
e592f0e6 | 3275 | as_bad_where (fixp->fx_file, fixp->fx_line, |
48401fcf | 3276 | _("Cannot represent relocation type %s"), |
e592f0e6 ILT |
3277 | bfd_get_reloc_code_name (code)); |
3278 | /* Set howto to a garbage value so that we can keep going. */ | |
3279 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
3280 | assert (rel->howto != NULL); | |
ad660eb1 | 3281 | } |
49864cfa | 3282 | |
ad660eb1 | 3283 | return rel; |
49864cfa KR |
3284 | } |
3285 | ||
3286 | #else /* ! BFD_ASSEMBLER */ | |
3287 | ||
3288 | #if (defined(OBJ_AOUT) | defined(OBJ_BOUT)) | |
3289 | void | |
3290 | tc_aout_fix_to_chars (where, fixP, segment_address_in_file) | |
3291 | char *where; | |
3292 | fixS *fixP; | |
3293 | relax_addressT segment_address_in_file; | |
4b77b129 | 3294 | { |
49864cfa KR |
3295 | /* |
3296 | * In: length of relocation (or of address) in chars: 1, 2 or 4. | |
3297 | * Out: GNU LD relocation length code: 0, 1, or 2. | |
3298 | */ | |
4b77b129 | 3299 | |
3c8df4ba | 3300 | static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2}; |
49864cfa KR |
3301 | long r_symbolnum; |
3302 | ||
3303 | know (fixP->fx_addsy != NULL); | |
3304 | ||
3305 | md_number_to_chars (where, | |
ad660eb1 ILT |
3306 | (valueT) (fixP->fx_frag->fr_address |
3307 | + fixP->fx_where - segment_address_in_file), | |
49864cfa KR |
3308 | 4); |
3309 | ||
3310 | r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy) | |
3311 | ? S_GET_TYPE (fixP->fx_addsy) | |
3312 | : fixP->fx_addsy->sy_number); | |
3313 | ||
3314 | where[6] = (r_symbolnum >> 16) & 0x0ff; | |
3315 | where[5] = (r_symbolnum >> 8) & 0x0ff; | |
3316 | where[4] = r_symbolnum & 0x0ff; | |
3317 | where[7] = ((((!S_IS_DEFINED (fixP->fx_addsy)) << 3) & 0x08) | |
3318 | | ((nbytes_r_length[fixP->fx_size] << 1) & 0x06) | |
3319 | | (((fixP->fx_pcrel << 0) & 0x01) & 0x0f)); | |
4b77b129 | 3320 | } |
355afbcd | 3321 | |
49864cfa | 3322 | #endif /* OBJ_AOUT or OBJ_BOUT */ |
4b77b129 | 3323 | |
49864cfa | 3324 | #if defined (I386COFF) |
4b77b129 | 3325 | |
355afbcd KR |
3326 | short |
3327 | tc_coff_fix2rtype (fixP) | |
3328 | fixS *fixP; | |
4b77b129 | 3329 | { |
3ea36b53 ILT |
3330 | if (fixP->fx_r_type == R_IMAGEBASE) |
3331 | return R_IMAGEBASE; | |
3332 | ||
355afbcd KR |
3333 | return (fixP->fx_pcrel ? |
3334 | (fixP->fx_size == 1 ? R_PCRBYTE : | |
3335 | fixP->fx_size == 2 ? R_PCRWORD : | |
3336 | R_PCRLONG) : | |
3337 | (fixP->fx_size == 1 ? R_RELBYTE : | |
3338 | fixP->fx_size == 2 ? R_RELWORD : | |
3339 | R_DIR32)); | |
4b77b129 ILT |
3340 | } |
3341 | ||
49864cfa KR |
3342 | int |
3343 | tc_coff_sizemachdep (frag) | |
3344 | fragS *frag; | |
3345 | { | |
3346 | if (frag->fr_next) | |
3347 | return (frag->fr_next->fr_address - frag->fr_address); | |
3348 | else | |
3349 | return 0; | |
3350 | } | |
3351 | ||
3352 | #endif /* I386COFF */ | |
3353 | ||
3354 | #endif /* BFD_ASSEMBLER? */ | |
3ea36b53 | 3355 | \f |
fecd2382 | 3356 | /* end of tc-i386.c */ |