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Remove duplicate definitions of the md_atof() function
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
4dc85607 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
e3bb37b5
L		 58static void set_code_flag (int);
59static void set_16bit_gcc_code_flag (int);
60static void set_intel_syntax (int);
db51cc60 61static void set_allow_index_reg (int);
e3bb37b5 62static void set_cpu_arch (int);
6482c264 63#ifdef TE_PE
e3bb37b5 64static void pe_directive_secrel (int);
6482c264 65#endif
e3bb37b5
L		 66static void signed_cons (int);
67static char *output_invalid (int c);
68static int i386_operand (char *);
69static int i386_intel_operand (char *, int);
70static const reg_entry *parse_register (char *, char **);
71static char *parse_insn (char *, char *);
72static char *parse_operands (char *, const char *);
73static void swap_operands (void);
4d456e3d 74static void swap_2_operands (int, int);
e3bb37b5
L		 75static void optimize_imm (void);
76static void optimize_disp (void);
77static int match_template (void);
78static int check_string (void);
79static int process_suffix (void);
80static int check_byte_reg (void);
81static int check_long_reg (void);
82static int check_qword_reg (void);
83static int check_word_reg (void);
84static int finalize_imm (void);
85f10a01 85static void process_drex (void);
e3bb37b5
L		 86static int process_operands (void);
87static const seg_entry *build_modrm_byte (void);
88static void output_insn (void);
89static void output_imm (fragS *, offsetT);
90static void output_disp (fragS *, offsetT);
29b0f896 91#ifndef I386COFF
e3bb37b5 92static void s_bss (int);
252b5132 93#endif
17d4e2a2
L		 94#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
95static void handle_large_common (int small ATTRIBUTE_UNUSED);
96#endif
252b5132 97
a847613f 98static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 99
252b5132 100/* 'md_assemble ()' gathers together information and puts it into a
47926f60 101 i386_insn. */
252b5132 102
520dc8e8
AM		 103union i386_op
104 {
105 expressionS *disps;
106 expressionS *imms;
107 const reg_entry *regs;
108 };
109
252b5132
RH		 110struct _i386_insn
111 {
47926f60 112 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 113 template tm;
114
115 /* SUFFIX holds the instruction mnemonic suffix if given.
116 (e.g. 'l' for 'movl') */
117 char suffix;
118
47926f60 119 /* OPERANDS gives the number of given operands. */
252b5132
RH		 120 unsigned int operands;
121
122 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
123 of given register, displacement, memory operands and immediate
47926f60 124 operands. */
252b5132
RH		 125 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
126
127 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 128 use OP[i] for the corresponding operand. */
40fb9820 129 i386_operand_type types[MAX_OPERANDS];
252b5132 130
520dc8e8
AM		 131 /* Displacement expression, immediate expression, or register for each
132 operand. */
133 union i386_op op[MAX_OPERANDS];
252b5132 134
3e73aa7c
JH		 135 /* Flags for operands. */
136 unsigned int flags[MAX_OPERANDS];
137#define Operand_PCrel 1
138
252b5132 139 /* Relocation type for operand */
f86103b7 140 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 141
252b5132
RH		 142 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
143 the base index byte below. */
144 const reg_entry *base_reg;
145 const reg_entry *index_reg;
146 unsigned int log2_scale_factor;
147
148 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 149 explicit segment overrides are given. */
ce8a8b2f 150 const seg_entry *seg[2];
252b5132
RH		 151
152 /* PREFIX holds all the given prefix opcodes (usually null).
153 PREFIXES is the number of prefix opcodes. */
154 unsigned int prefixes;
155 unsigned char prefix[MAX_PREFIXES];
156
157 /* RM and SIB are the modrm byte and the sib byte where the
85f10a01
MM		 158 addressing modes of this insn are encoded. DREX is the byte
159 added by the SSE5 instructions. */
252b5132
RH		 160
161 modrm_byte rm;
3e73aa7c 162 rex_byte rex;
252b5132 163 sib_byte sib;
85f10a01 164 drex_byte drex;
252b5132
RH		 165 };
166
167typedef struct _i386_insn i386_insn;
168
169/* List of chars besides those in app.c:symbol_chars that can start an
170 operand. Used to prevent the scrubber eating vital white-space. */
32137342 171const char extra_symbol_chars[] = "*%-(["
252b5132 172#ifdef LEX_AT
32137342
NC		 173 "@"
174#endif
175#ifdef LEX_QM
176 "?"
252b5132 177#endif
32137342 178 ;
252b5132 179
29b0f896
AM		 180#if (defined (TE_I386AIX) \
181 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 182 && !defined (TE_GNU) \
29b0f896 183 && !defined (TE_LINUX) \
32137342 184 && !defined (TE_NETWARE) \
29b0f896
AM		 185 && !defined (TE_FreeBSD) \
186 && !defined (TE_NetBSD)))
252b5132 187/* This array holds the chars that always start a comment. If the
b3b91714
AM		 188 pre-processor is disabled, these aren't very useful. The option
189 --divide will remove '/' from this list. */
190const char *i386_comment_chars = "#/";
191#define SVR4_COMMENT_CHARS 1
252b5132 192#define PREFIX_SEPARATOR '\\'
252b5132 193
b3b91714
AM		 194#else
195const char *i386_comment_chars = "#";
196#define PREFIX_SEPARATOR '/'
197#endif
198
252b5132
RH		 199/* This array holds the chars that only start a comment at the beginning of
200 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 201 .line and .file directives will appear in the pre-processed output.
202 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 203 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 204 #NO_APP at the beginning of its output.
205 Also note that comments started like this one will always work if
252b5132 206 '/' isn't otherwise defined. */
b3b91714 207const char line_comment_chars[] = "#/";
252b5132 208
63a0b638 209const char line_separator_chars[] = ";";
252b5132 210
ce8a8b2f
AM		 211/* Chars that can be used to separate mant from exp in floating point
212 nums. */
252b5132
RH		 213const char EXP_CHARS[] = "eE";
214
ce8a8b2f
AM		 215/* Chars that mean this number is a floating point constant
216 As in 0f12.456
217 or 0d1.2345e12. */
252b5132
RH		 218const char FLT_CHARS[] = "fFdDxX";
219
ce8a8b2f 220/* Tables for lexical analysis. */
252b5132
RH		 221static char mnemonic_chars[256];
222static char register_chars[256];
223static char operand_chars[256];
224static char identifier_chars[256];
225static char digit_chars[256];
226
ce8a8b2f 227/* Lexical macros. */
252b5132
RH		 228#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
229#define is_operand_char(x) (operand_chars[(unsigned char) x])
230#define is_register_char(x) (register_chars[(unsigned char) x])
231#define is_space_char(x) ((x) == ' ')
232#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
233#define is_digit_char(x) (digit_chars[(unsigned char) x])
234
0234cb7c 235/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 236static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
237
238/* md_assemble() always leaves the strings it's passed unaltered. To
239 effect this we maintain a stack of saved characters that we've smashed
240 with '\0's (indicating end of strings for various sub-fields of the
47926f60 241 assembler instruction). */
252b5132 242static char save_stack[32];
ce8a8b2f 243static char *save_stack_p;
252b5132
RH		 244#define END_STRING_AND_SAVE(s) \
245 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
246#define RESTORE_END_STRING(s) \
247 do { *(s) = *--save_stack_p; } while (0)
248
47926f60 249/* The instruction we're assembling. */
252b5132
RH		 250static i386_insn i;
251
252/* Possible templates for current insn. */
253static const templates *current_templates;
254
31b2323c
L		 255/* Per instruction expressionS buffers: max displacements & immediates. */
256static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
257static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 258
47926f60
KH		 259/* Current operand we are working on. */
260static int this_operand;
252b5132 261
3e73aa7c
JH		 262/* We support four different modes. FLAG_CODE variable is used to distinguish
263 these. */
264
265enum flag_code {
266 CODE_32BIT,
267 CODE_16BIT,
268 CODE_64BIT };
269
270static enum flag_code flag_code;
4fa24527 271static unsigned int object_64bit;
3e73aa7c
JH		 272static int use_rela_relocations = 0;
273
274/* The names used to print error messages. */
b77a7acd 275static const char *flag_code_names[] =
3e73aa7c
JH		 276 {
277 "32",
278 "16",
279 "64"
280 };
252b5132 281
47926f60
KH		 282/* 1 for intel syntax,
283 0 if att syntax. */
284static int intel_syntax = 0;
252b5132 285
47926f60
KH		 286/* 1 if register prefix % not required. */
287static int allow_naked_reg = 0;
252b5132 288
db51cc60
L		 289/* 1 if fake index register, eiz/riz, is allowed . */
290static int allow_index_reg = 0;
291
2ca3ace5
L		 292/* Register prefix used for error message. */
293static const char *register_prefix = "%";
294
47926f60
KH		 295/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
296 leave, push, and pop instructions so that gcc has the same stack
297 frame as in 32 bit mode. */
298static char stackop_size = '\0';
eecb386c 299
12b55ccc
L		 300/* Non-zero to optimize code alignment. */
301int optimize_align_code = 1;
302
47926f60
KH		 303/* Non-zero to quieten some warnings. */
304static int quiet_warnings = 0;
a38cf1db 305
47926f60
KH		 306/* CPU name. */
307static const char *cpu_arch_name = NULL;
5c6af06e 308static const char *cpu_sub_arch_name = NULL;
a38cf1db 309
47926f60 310/* CPU feature flags. */
40fb9820
L		 311static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
312
313/* Bitwise NOT of cpu_arch_flags. */
314static i386_cpu_flags cpu_arch_flags_not;
a38cf1db 315
ccc9c027
L		 316/* If we have selected a cpu we are generating instructions for. */
317static int cpu_arch_tune_set = 0;
318
9103f4f4
L		 319/* Cpu we are generating instructions for. */
320static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
321
322/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 323static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 324
ccc9c027
L		 325/* CPU instruction set architecture used. */
326static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
327
9103f4f4 328/* CPU feature flags of instruction set architecture used. */
40fb9820 329static i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 330
fddf5b5b
AM		 331/* If set, conditional jumps are not automatically promoted to handle
332 larger than a byte offset. */
333static unsigned int no_cond_jump_promotion = 0;
334
29b0f896 335/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 336static symbolS *GOT_symbol;
29b0f896 337
a4447b93
RH		 338/* The dwarf2 return column, adjusted for 32 or 64 bit. */
339unsigned int x86_dwarf2_return_column;
340
341/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
342int x86_cie_data_alignment;
343
252b5132 344/* Interface to relax_segment.
fddf5b5b
AM		 345 There are 3 major relax states for 386 jump insns because the
346 different types of jumps add different sizes to frags when we're
347 figuring out what sort of jump to choose to reach a given label. */
252b5132 348
47926f60 349/* Types. */
93c2a809
AM		 350#define UNCOND_JUMP 0
351#define COND_JUMP 1
352#define COND_JUMP86 2
fddf5b5b 353
47926f60 354/* Sizes. */
252b5132
RH		 355#define CODE16 1
356#define SMALL 0
29b0f896 357#define SMALL16 (SMALL | CODE16)
252b5132 358#define BIG 2
29b0f896 359#define BIG16 (BIG | CODE16)
252b5132
RH		 360
361#ifndef INLINE
362#ifdef __GNUC__
363#define INLINE __inline__
364#else
365#define INLINE
366#endif
367#endif
368
fddf5b5b
AM		 369#define ENCODE_RELAX_STATE(type, size) \
370 ((relax_substateT) (((type) << 2) | (size)))
371#define TYPE_FROM_RELAX_STATE(s) \
372 ((s) >> 2)
373#define DISP_SIZE_FROM_RELAX_STATE(s) \
374 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 375
376/* This table is used by relax_frag to promote short jumps to long
377 ones where necessary. SMALL (short) jumps may be promoted to BIG
378 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
379 don't allow a short jump in a 32 bit code segment to be promoted to
380 a 16 bit offset jump because it's slower (requires data size
381 prefix), and doesn't work, unless the destination is in the bottom
382 64k of the code segment (The top 16 bits of eip are zeroed). */
383
384const relax_typeS md_relax_table[] =
385{
24eab124
AM		 386 /* The fields are:
387 1) most positive reach of this state,
388 2) most negative reach of this state,
93c2a809 389 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 390 4) which index into the table to try if we can't fit into this one. */
252b5132 391
fddf5b5b 392 /* UNCOND_JUMP states. */
93c2a809
AM		 393 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
394 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
395 /* dword jmp adds 4 bytes to frag:
396 0 extra opcode bytes, 4 displacement bytes. */
252b5132 397 {0, 0, 4, 0},
93c2a809
AM		 398 /* word jmp adds 2 byte2 to frag:
399 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 400 {0, 0, 2, 0},
401
93c2a809
AM		 402 /* COND_JUMP states. */
403 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
404 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
405 /* dword conditionals adds 5 bytes to frag:
406 1 extra opcode byte, 4 displacement bytes. */
407 {0, 0, 5, 0},
fddf5b5b 408 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 409 1 extra opcode byte, 2 displacement bytes. */
410 {0, 0, 3, 0},
411
412 /* COND_JUMP86 states. */
413 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
414 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
415 /* dword conditionals adds 5 bytes to frag:
416 1 extra opcode byte, 4 displacement bytes. */
417 {0, 0, 5, 0},
418 /* word conditionals add 4 bytes to frag:
419 1 displacement byte and a 3 byte long branch insn. */
420 {0, 0, 4, 0}
252b5132
RH		 421};
422
9103f4f4
L		 423static const arch_entry cpu_arch[] =
424{
425 {"generic32", PROCESSOR_GENERIC32,
40fb9820 426 CPU_GENERIC32_FLAGS },
9103f4f4 427 {"generic64", PROCESSOR_GENERIC64,
40fb9820 428 CPU_GENERIC64_FLAGS },
9103f4f4 429 {"i8086", PROCESSOR_UNKNOWN,
40fb9820 430 CPU_NONE_FLAGS },
9103f4f4 431 {"i186", PROCESSOR_UNKNOWN,
40fb9820 432 CPU_I186_FLAGS },
9103f4f4 433 {"i286", PROCESSOR_UNKNOWN,
40fb9820 434 CPU_I286_FLAGS },
76bc74dc 435 {"i386", PROCESSOR_I386,
40fb9820 436 CPU_I386_FLAGS },
9103f4f4 437 {"i486", PROCESSOR_I486,
40fb9820 438 CPU_I486_FLAGS },
9103f4f4 439 {"i586", PROCESSOR_PENTIUM,
40fb9820 440 CPU_I586_FLAGS },
9103f4f4 441 {"i686", PROCESSOR_PENTIUMPRO,
40fb9820 442 CPU_I686_FLAGS },
9103f4f4 443 {"pentium", PROCESSOR_PENTIUM,
40fb9820 444 CPU_I586_FLAGS },
9103f4f4 445 {"pentiumpro",PROCESSOR_PENTIUMPRO,
40fb9820 446 CPU_I686_FLAGS },
9103f4f4 447 {"pentiumii", PROCESSOR_PENTIUMPRO,
40fb9820 448 CPU_P2_FLAGS },
9103f4f4 449 {"pentiumiii",PROCESSOR_PENTIUMPRO,
40fb9820 450 CPU_P3_FLAGS },
9103f4f4 451 {"pentium4", PROCESSOR_PENTIUM4,
40fb9820 452 CPU_P4_FLAGS },
9103f4f4 453 {"prescott", PROCESSOR_NOCONA,
40fb9820 454 CPU_CORE_FLAGS },
9103f4f4 455 {"nocona", PROCESSOR_NOCONA,
40fb9820 456 CPU_NOCONA_FLAGS },
ef05d495 457 {"yonah", PROCESSOR_CORE,
40fb9820 458 CPU_CORE_FLAGS },
ef05d495 459 {"core", PROCESSOR_CORE,
40fb9820 460 CPU_CORE_FLAGS },
ef05d495 461 {"merom", PROCESSOR_CORE2,
40fb9820 462 CPU_CORE2_FLAGS },
ef05d495 463 {"core2", PROCESSOR_CORE2,
40fb9820 464 CPU_CORE2_FLAGS },
9103f4f4 465 {"k6", PROCESSOR_K6,
40fb9820 466 CPU_K6_FLAGS },
9103f4f4 467 {"k6_2", PROCESSOR_K6,
40fb9820 468 CPU_K6_2_FLAGS },
9103f4f4 469 {"athlon", PROCESSOR_ATHLON,
40fb9820 470 CPU_ATHLON_FLAGS },
9103f4f4 471 {"sledgehammer", PROCESSOR_K8,
40fb9820 472 CPU_K8_FLAGS },
9103f4f4 473 {"opteron", PROCESSOR_K8,
40fb9820 474 CPU_K8_FLAGS },
9103f4f4 475 {"k8", PROCESSOR_K8,
40fb9820 476 CPU_K8_FLAGS },
050dfa73 477 {"amdfam10", PROCESSOR_AMDFAM10,
40fb9820 478 CPU_AMDFAM10_FLAGS },
9103f4f4 479 {".mmx", PROCESSOR_UNKNOWN,
40fb9820 480 CPU_MMX_FLAGS },
9103f4f4 481 {".sse", PROCESSOR_UNKNOWN,
40fb9820 482 CPU_SSE_FLAGS },
9103f4f4 483 {".sse2", PROCESSOR_UNKNOWN,
40fb9820 484 CPU_SSE2_FLAGS },
9103f4f4 485 {".sse3", PROCESSOR_UNKNOWN,
40fb9820 486 CPU_SSE3_FLAGS },
ef05d495 487 {".ssse3", PROCESSOR_UNKNOWN,
40fb9820 488 CPU_SSSE3_FLAGS },
42903f7f 489 {".sse4.1", PROCESSOR_UNKNOWN,
40fb9820 490 CPU_SSE4_1_FLAGS },
381d071f 491 {".sse4.2", PROCESSOR_UNKNOWN,
40fb9820 492 CPU_SSE4_2_FLAGS },
381d071f 493 {".sse4", PROCESSOR_UNKNOWN,
40fb9820 494 CPU_SSE4_2_FLAGS },
9103f4f4 495 {".3dnow", PROCESSOR_UNKNOWN,
40fb9820 496 CPU_3DNOW_FLAGS },
9103f4f4 497 {".3dnowa", PROCESSOR_UNKNOWN,
40fb9820 498 CPU_3DNOWA_FLAGS },
9103f4f4 499 {".padlock", PROCESSOR_UNKNOWN,
40fb9820 500 CPU_PADLOCK_FLAGS },
9103f4f4 501 {".pacifica", PROCESSOR_UNKNOWN,
40fb9820 502 CPU_SVME_FLAGS },
9103f4f4 503 {".svme", PROCESSOR_UNKNOWN,
40fb9820 504 CPU_SVME_FLAGS },
050dfa73 505 {".sse4a", PROCESSOR_UNKNOWN,
40fb9820 506 CPU_SSE4A_FLAGS },
050dfa73 507 {".abm", PROCESSOR_UNKNOWN,
40fb9820 508 CPU_ABM_FLAGS },
85f10a01
MM		 509 {".sse5", PROCESSOR_UNKNOWN,
510 CPU_SSE5_FLAGS },
e413e4e9
AM		 511};
512
29b0f896
AM		 513const pseudo_typeS md_pseudo_table[] =
514{
515#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
516 {"align", s_align_bytes, 0},
517#else
518 {"align", s_align_ptwo, 0},
519#endif
520 {"arch", set_cpu_arch, 0},
521#ifndef I386COFF
522 {"bss", s_bss, 0},
523#endif
524 {"ffloat", float_cons, 'f'},
525 {"dfloat", float_cons, 'd'},
526 {"tfloat", float_cons, 'x'},
527 {"value", cons, 2},
d182319b 528 {"slong", signed_cons, 4},
29b0f896
AM		 529 {"noopt", s_ignore, 0},
530 {"optim", s_ignore, 0},
531 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
532 {"code16", set_code_flag, CODE_16BIT},
533 {"code32", set_code_flag, CODE_32BIT},
534 {"code64", set_code_flag, CODE_64BIT},
535 {"intel_syntax", set_intel_syntax, 1},
536 {"att_syntax", set_intel_syntax, 0},
db51cc60
L		 537 {"allow_index_reg", set_allow_index_reg, 1},
538 {"disallow_index_reg", set_allow_index_reg, 0},
3b22753a
L		 539#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
540 {"largecomm", handle_large_common, 0},
07a53e5c 541#else
e3bb37b5 542 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 543 {"loc", dwarf2_directive_loc, 0},
544 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 545#endif
6482c264
NC		 546#ifdef TE_PE
547 {"secrel32", pe_directive_secrel, 0},
548#endif
29b0f896
AM		 549 {0, 0, 0}
550};
551
552/* For interface with expression (). */
553extern char *input_line_pointer;
554
555/* Hash table for instruction mnemonic lookup. */
556static struct hash_control *op_hash;
557
558/* Hash table for register lookup. */
559static struct hash_control *reg_hash;
560\f
252b5132 561void
e3bb37b5 562i386_align_code (fragS *fragP, int count)
252b5132 563{
ce8a8b2f
AM		 564 /* Various efficient no-op patterns for aligning code labels.
565 Note: Don't try to assemble the instructions in the comments.
566 0L and 0w are not legal. */
252b5132
RH		 567 static const char f32_1[] =
568 {0x90}; /* nop */
569 static const char f32_2[] =
ccc9c027 570 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 571 static const char f32_3[] =
572 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
573 static const char f32_4[] =
574 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
575 static const char f32_5[] =
576 {0x90, /* nop */
577 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
578 static const char f32_6[] =
579 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
580 static const char f32_7[] =
581 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
582 static const char f32_8[] =
583 {0x90, /* nop */
584 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
585 static const char f32_9[] =
586 {0x89,0xf6, /* movl %esi,%esi */
587 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
588 static const char f32_10[] =
589 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
590 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
591 static const char f32_11[] =
592 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
593 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
594 static const char f32_12[] =
595 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
596 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
597 static const char f32_13[] =
598 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
599 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
600 static const char f32_14[] =
601 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
602 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 603 static const char f16_3[] =
604 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 605 static const char f16_4[] =
606 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
607 static const char f16_5[] =
608 {0x90, /* nop */
609 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
610 static const char f16_6[] =
611 {0x89,0xf6, /* mov %si,%si */
612 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
613 static const char f16_7[] =
614 {0x8d,0x74,0x00, /* lea 0(%si),%si */
615 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
616 static const char f16_8[] =
617 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
618 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 619 static const char jump_31[] =
620 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
621 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
622 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
623 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 624 static const char *const f32_patt[] = {
625 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 626 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 627 };
628 static const char *const f16_patt[] = {
76bc74dc 629 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 630 };
ccc9c027
L		 631 /* nopl (%[re]ax) */
632 static const char alt_3[] =
633 {0x0f,0x1f,0x00};
634 /* nopl 0(%[re]ax) */
635 static const char alt_4[] =
636 {0x0f,0x1f,0x40,0x00};
637 /* nopl 0(%[re]ax,%[re]ax,1) */
638 static const char alt_5[] =
639 {0x0f,0x1f,0x44,0x00,0x00};
640 /* nopw 0(%[re]ax,%[re]ax,1) */
641 static const char alt_6[] =
642 {0x66,0x0f,0x1f,0x44,0x00,0x00};
643 /* nopl 0L(%[re]ax) */
644 static const char alt_7[] =
645 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
646 /* nopl 0L(%[re]ax,%[re]ax,1) */
647 static const char alt_8[] =
648 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
649 /* nopw 0L(%[re]ax,%[re]ax,1) */
650 static const char alt_9[] =
651 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
652 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
653 static const char alt_10[] =
654 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
655 /* data16
656 nopw %cs:0L(%[re]ax,%[re]ax,1) */
657 static const char alt_long_11[] =
658 {0x66,
659 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
660 /* data16
661 data16
662 nopw %cs:0L(%[re]ax,%[re]ax,1) */
663 static const char alt_long_12[] =
664 {0x66,
665 0x66,
666 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
667 /* data16
668 data16
669 data16
670 nopw %cs:0L(%[re]ax,%[re]ax,1) */
671 static const char alt_long_13[] =
672 {0x66,
673 0x66,
674 0x66,
675 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
676 /* data16
677 data16
678 data16
679 data16
680 nopw %cs:0L(%[re]ax,%[re]ax,1) */
681 static const char alt_long_14[] =
682 {0x66,
683 0x66,
684 0x66,
685 0x66,
686 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
687 /* data16
688 data16
689 data16
690 data16
691 data16
692 nopw %cs:0L(%[re]ax,%[re]ax,1) */
693 static const char alt_long_15[] =
694 {0x66,
695 0x66,
696 0x66,
697 0x66,
698 0x66,
699 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
700 /* nopl 0(%[re]ax,%[re]ax,1)
701 nopw 0(%[re]ax,%[re]ax,1) */
702 static const char alt_short_11[] =
703 {0x0f,0x1f,0x44,0x00,0x00,
704 0x66,0x0f,0x1f,0x44,0x00,0x00};
705 /* nopw 0(%[re]ax,%[re]ax,1)
706 nopw 0(%[re]ax,%[re]ax,1) */
707 static const char alt_short_12[] =
708 {0x66,0x0f,0x1f,0x44,0x00,0x00,
709 0x66,0x0f,0x1f,0x44,0x00,0x00};
710 /* nopw 0(%[re]ax,%[re]ax,1)
711 nopl 0L(%[re]ax) */
712 static const char alt_short_13[] =
713 {0x66,0x0f,0x1f,0x44,0x00,0x00,
714 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
715 /* nopl 0L(%[re]ax)
716 nopl 0L(%[re]ax) */
717 static const char alt_short_14[] =
718 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
719 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
720 /* nopl 0L(%[re]ax)
721 nopl 0L(%[re]ax,%[re]ax,1) */
722 static const char alt_short_15[] =
723 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
724 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
725 static const char *const alt_short_patt[] = {
726 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
727 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
728 alt_short_14, alt_short_15
729 };
730 static const char *const alt_long_patt[] = {
731 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
732 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
733 alt_long_14, alt_long_15
734 };
252b5132 735
76bc74dc
L		 736 /* Only align for at least a positive non-zero boundary. */
737 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 738 return;
3e73aa7c 739
ccc9c027
L		 740 /* We need to decide which NOP sequence to use for 32bit and
741 64bit. When -mtune= is used:
4eed87de 742
76bc74dc
L		 743 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
744 PROCESSOR_GENERIC32, f32_patt will be used.
745 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
746 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
747 alt_long_patt will be used.
748 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
749 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 750
76bc74dc
L		 751 When -mtune= isn't used, alt_long_patt will be used if
752 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
753 be used.
ccc9c027
L		 754
755 When -march= or .arch is used, we can't use anything beyond
756 cpu_arch_isa_flags. */
757
758 if (flag_code == CODE_16BIT)
759 {
ccc9c027 760 if (count > 8)
33fef721 761 {
76bc74dc
L		 762 memcpy (fragP->fr_literal + fragP->fr_fix,
763 jump_31, count);
764 /* Adjust jump offset. */
765 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 766 }
76bc74dc
L		 767 else
768 memcpy (fragP->fr_literal + fragP->fr_fix,
769 f16_patt[count - 1], count);
252b5132 770 }
33fef721 771 else
ccc9c027
L		 772 {
773 const char *const *patt = NULL;
774
775 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
776 {
777 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
778 switch (cpu_arch_tune)
779 {
780 case PROCESSOR_UNKNOWN:
781 /* We use cpu_arch_isa_flags to check if we SHOULD
782 optimize for Cpu686. */
40fb9820 783 if (cpu_arch_isa_flags.bitfield.cpui686)
76bc74dc 784 patt = alt_long_patt;
ccc9c027
L		 785 else
786 patt = f32_patt;
787 break;
ccc9c027
L		 788 case PROCESSOR_PENTIUMPRO:
789 case PROCESSOR_PENTIUM4:
790 case PROCESSOR_NOCONA:
ef05d495 791 case PROCESSOR_CORE:
76bc74dc
L		 792 case PROCESSOR_CORE2:
793 case PROCESSOR_GENERIC64:
794 patt = alt_long_patt;
795 break;
ccc9c027
L		 796 case PROCESSOR_K6:
797 case PROCESSOR_ATHLON:
798 case PROCESSOR_K8:
4eed87de 799 case PROCESSOR_AMDFAM10:
ccc9c027
L		 800 patt = alt_short_patt;
801 break;
76bc74dc 802 case PROCESSOR_I386:
ccc9c027
L		 803 case PROCESSOR_I486:
804 case PROCESSOR_PENTIUM:
805 case PROCESSOR_GENERIC32:
806 patt = f32_patt;
807 break;
4eed87de 808 }
ccc9c027
L		 809 }
810 else
811 {
812 switch (cpu_arch_tune)
813 {
814 case PROCESSOR_UNKNOWN:
815 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
816 PROCESSOR_UNKNOWN. */
817 abort ();
818 break;
819
76bc74dc 820 case PROCESSOR_I386:
ccc9c027
L		 821 case PROCESSOR_I486:
822 case PROCESSOR_PENTIUM:
ccc9c027
L		 823 case PROCESSOR_K6:
824 case PROCESSOR_ATHLON:
825 case PROCESSOR_K8:
4eed87de 826 case PROCESSOR_AMDFAM10:
ccc9c027
L		 827 case PROCESSOR_GENERIC32:
828 /* We use cpu_arch_isa_flags to check if we CAN optimize
829 for Cpu686. */
40fb9820 830 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 831 patt = alt_short_patt;
832 else
833 patt = f32_patt;
834 break;
76bc74dc
L		 835 case PROCESSOR_PENTIUMPRO:
836 case PROCESSOR_PENTIUM4:
837 case PROCESSOR_NOCONA:
838 case PROCESSOR_CORE:
ef05d495 839 case PROCESSOR_CORE2:
40fb9820 840 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 841 patt = alt_long_patt;
842 else
843 patt = f32_patt;
844 break;
845 case PROCESSOR_GENERIC64:
76bc74dc 846 patt = alt_long_patt;
ccc9c027 847 break;
4eed87de 848 }
ccc9c027
L		 849 }
850
76bc74dc
L		 851 if (patt == f32_patt)
852 {
853 /* If the padding is less than 15 bytes, we use the normal
854 ones. Otherwise, we use a jump instruction and adjust
855 its offset. */
856 if (count < 15)
857 memcpy (fragP->fr_literal + fragP->fr_fix,
858 patt[count - 1], count);
859 else
860 {
861 memcpy (fragP->fr_literal + fragP->fr_fix,
862 jump_31, count);
863 /* Adjust jump offset. */
864 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
865 }
866 }
867 else
868 {
869 /* Maximum length of an instruction is 15 byte. If the
870 padding is greater than 15 bytes and we don't use jump,
871 we have to break it into smaller pieces. */
872 int padding = count;
873 while (padding > 15)
874 {
875 padding -= 15;
876 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
877 patt [14], 15);
878 }
879
880 if (padding)
881 memcpy (fragP->fr_literal + fragP->fr_fix,
882 patt [padding - 1], padding);
883 }
ccc9c027 884 }
33fef721 885 fragP->fr_var = count;
252b5132
RH		 886}
887
c6fb90c8
L		 888static INLINE int
889uints_all_zero (const unsigned int *x, unsigned int size)
40fb9820 890{
c6fb90c8
L		 891 switch (size)
892 {
893 case 3:
894 if (x[2])
895 return 0;
896 case 2:
897 if (x[1])
898 return 0;
899 case 1:
900 return !x[0];
901 default:
902 abort ();
903 }
40fb9820
L		 904}
905
c6fb90c8
L		 906static INLINE void
907uints_set (unsigned int *x, unsigned int v, unsigned int size)
40fb9820 908{
c6fb90c8
L		 909 switch (size)
910 {
911 case 3:
912 x[2] = v;
913 case 2:
914 x[1] = v;
915 case 1:
916 x[0] = v;
917 break;
918 default:
919 abort ();
920 }
921}
40fb9820 922
c6fb90c8
L		 923static INLINE int
924uints_equal (const unsigned int *x, const unsigned int *y,
925 unsigned int size)
926{
927 switch (size)
928 {
929 case 3:
930 if (x[2] != y [2])
931 return 0;
932 case 2:
933 if (x[1] != y [1])
934 return 0;
935 case 1:
936 return x[0] == y [0];
937 break;
938 default:
939 abort ();
940 }
941}
40fb9820 942
c6fb90c8
L		 943#define UINTS_ALL_ZERO(x) \
944 uints_all_zero ((x).array, ARRAY_SIZE ((x).array))
945#define UINTS_SET(x, v) \
946 uints_set ((x).array, v, ARRAY_SIZE ((x).array))
947#define UINTS_CLEAR(x) \
948 uints_set ((x).array, 0, ARRAY_SIZE ((x).array))
949#define UINTS_EQUAL(x, y) \
950 uints_equal ((x).array, (y).array, ARRAY_SIZE ((x).array))
951
952static INLINE int
953cpu_flags_check_cpu64 (i386_cpu_flags f)
954{
955 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
956 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 957}
958
c6fb90c8 959static INLINE i386_cpu_flags
40fb9820
L		 960cpu_flags_not (i386_cpu_flags x)
961{
c6fb90c8
L		 962 switch (ARRAY_SIZE (x.array))
963 {
964 case 3:
965 x.array [2] = ~x.array [2];
966 case 2:
967 x.array [1] = ~x.array [1];
968 case 1:
969 x.array [0] = ~x.array [0];
970 break;
971 default:
972 abort ();
973 }
40fb9820
L		 974
975#ifdef CpuUnused
976 x.bitfield.unused = 0;
977#endif
978
979 return x;
980}
981
c6fb90c8
L		 982static INLINE i386_cpu_flags
983cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 984{
c6fb90c8
L		 985 switch (ARRAY_SIZE (x.array))
986 {
987 case 3:
988 x.array [2] &= y.array [2];
989 case 2:
990 x.array [1] &= y.array [1];
991 case 1:
992 x.array [0] &= y.array [0];
993 break;
994 default:
995 abort ();
996 }
997 return x;
998}
40fb9820 999
c6fb90c8
L		 1000static INLINE i386_cpu_flags
1001cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1002{
c6fb90c8 1003 switch (ARRAY_SIZE (x.array))
40fb9820 1004 {
c6fb90c8
L		 1005 case 3:
1006 x.array [2] |= y.array [2];
1007 case 2:
1008 x.array [1] |= y.array [1];
1009 case 1:
1010 x.array [0] |= y.array [0];
40fb9820
L		 1011 break;
1012 default:
1013 abort ();
1014 }
40fb9820
L		 1015 return x;
1016}
1017
1018static int
1019cpu_flags_match (i386_cpu_flags x)
1020{
1021 i386_cpu_flags not = cpu_arch_flags_not;
1022
1023 not.bitfield.cpu64 = 1;
1024 not.bitfield.cpuno64 = 1;
1025
1026 x.bitfield.cpu64 = 0;
1027 x.bitfield.cpuno64 = 0;
1028
c6fb90c8
L		 1029 not = cpu_flags_and (x, not);
1030 return UINTS_ALL_ZERO (not);
40fb9820
L		 1031}
1032
c6fb90c8
L		 1033static INLINE i386_operand_type
1034operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1035{
c6fb90c8
L		 1036 switch (ARRAY_SIZE (x.array))
1037 {
1038 case 3:
1039 x.array [2] &= y.array [2];
1040 case 2:
1041 x.array [1] &= y.array [1];
1042 case 1:
1043 x.array [0] &= y.array [0];
1044 break;
1045 default:
1046 abort ();
1047 }
1048 return x;
40fb9820
L		 1049}
1050
c6fb90c8
L		 1051static INLINE i386_operand_type
1052operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1053{
c6fb90c8 1054 switch (ARRAY_SIZE (x.array))
40fb9820 1055 {
c6fb90c8
L		 1056 case 3:
1057 x.array [2] |= y.array [2];
1058 case 2:
1059 x.array [1] |= y.array [1];
1060 case 1:
1061 x.array [0] |= y.array [0];
40fb9820
L		 1062 break;
1063 default:
1064 abort ();
1065 }
c6fb90c8
L		 1066 return x;
1067}
40fb9820 1068
c6fb90c8
L		 1069static INLINE i386_operand_type
1070operand_type_xor (i386_operand_type x, i386_operand_type y)
1071{
1072 switch (ARRAY_SIZE (x.array))
1073 {
1074 case 3:
1075 x.array [2] ^= y.array [2];
1076 case 2:
1077 x.array [1] ^= y.array [1];
1078 case 1:
1079 x.array [0] ^= y.array [0];
1080 break;
1081 default:
1082 abort ();
1083 }
40fb9820
L		 1084 return x;
1085}
1086
1087static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1088static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1089static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1090static const i386_operand_type reg16_inoutportreg
1091 = OPERAND_TYPE_REG16_INOUTPORTREG;
1092static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1093static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1094static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1095static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1096static const i386_operand_type anydisp
1097 = OPERAND_TYPE_ANYDISP;
40fb9820
L		 1098static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1099static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1100static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1101static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1102static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1103static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1104static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1105static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1106static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1107static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1108
1109enum operand_type
1110{
1111 reg,
40fb9820
L		 1112 imm,
1113 disp,
1114 anymem
1115};
1116
c6fb90c8 1117static INLINE int
40fb9820
L		 1118operand_type_check (i386_operand_type t, enum operand_type c)
1119{
1120 switch (c)
1121 {
1122 case reg:
1123 return (t.bitfield.reg8
1124 || t.bitfield.reg16
1125 || t.bitfield.reg32
1126 || t.bitfield.reg64);
1127
40fb9820
L		 1128 case imm:
1129 return (t.bitfield.imm8
1130 || t.bitfield.imm8s
1131 || t.bitfield.imm16
1132 || t.bitfield.imm32
1133 || t.bitfield.imm32s
1134 || t.bitfield.imm64);
1135
1136 case disp:
1137 return (t.bitfield.disp8
1138 || t.bitfield.disp16
1139 || t.bitfield.disp32
1140 || t.bitfield.disp32s
1141 || t.bitfield.disp64);
1142
1143 case anymem:
1144 return (t.bitfield.disp8
1145 || t.bitfield.disp16
1146 || t.bitfield.disp32
1147 || t.bitfield.disp32s
1148 || t.bitfield.disp64
1149 || t.bitfield.baseindex);
1150
1151 default:
1152 abort ();
1153 }
1154}
1155
c6fb90c8 1156static INLINE int
40fb9820
L		 1157operand_type_match (i386_operand_type overlap,
1158 i386_operand_type given)
1159{
1160 i386_operand_type temp = overlap;
1161
1162 temp.bitfield.jumpabsolute = 0;
c6fb90c8 1163 if (UINTS_ALL_ZERO (temp))
40fb9820
L		 1164 return 0;
1165
1166 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1167 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1168}
1169
1170/* If given types r0 and r1 are registers they must be of the same type
1171 unless the expected operand type register overlap is null.
1172 Note that Acc in a template matches every size of reg. */
1173
c6fb90c8 1174static INLINE int
40fb9820
L		 1175operand_type_register_match (i386_operand_type m0,
1176 i386_operand_type g0,
1177 i386_operand_type t0,
1178 i386_operand_type m1,
1179 i386_operand_type g1,
1180 i386_operand_type t1)
1181{
1182 if (!operand_type_check (g0, reg))
1183 return 1;
1184
1185 if (!operand_type_check (g1, reg))
1186 return 1;
1187
1188 if (g0.bitfield.reg8 == g1.bitfield.reg8
1189 && g0.bitfield.reg16 == g1.bitfield.reg16
1190 && g0.bitfield.reg32 == g1.bitfield.reg32
1191 && g0.bitfield.reg64 == g1.bitfield.reg64)
1192 return 1;
1193
1194 if (m0.bitfield.acc)
1195 {
1196 t0.bitfield.reg8 = 1;
1197 t0.bitfield.reg16 = 1;
1198 t0.bitfield.reg32 = 1;
1199 t0.bitfield.reg64 = 1;
1200 }
1201
1202 if (m1.bitfield.acc)
1203 {
1204 t1.bitfield.reg8 = 1;
1205 t1.bitfield.reg16 = 1;
1206 t1.bitfield.reg32 = 1;
1207 t1.bitfield.reg64 = 1;
1208 }
1209
1210 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1211 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1212 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1213 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1214}
1215
252b5132 1216static INLINE unsigned int
40fb9820 1217mode_from_disp_size (i386_operand_type t)
252b5132 1218{
40fb9820
L		 1219 if (t.bitfield.disp8)
1220 return 1;
1221 else if (t.bitfield.disp16
1222 || t.bitfield.disp32
1223 || t.bitfield.disp32s)
1224 return 2;
1225 else
1226 return 0;
252b5132
RH		 1227}
1228
1229static INLINE int
e3bb37b5 1230fits_in_signed_byte (offsetT num)
252b5132
RH		 1231{
1232 return (num >= -128) && (num <= 127);
47926f60 1233}
252b5132
RH		 1234
1235static INLINE int
e3bb37b5 1236fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1237{
1238 return (num & 0xff) == num;
47926f60 1239}
252b5132
RH		 1240
1241static INLINE int
e3bb37b5 1242fits_in_unsigned_word (offsetT num)
252b5132
RH		 1243{
1244 return (num & 0xffff) == num;
47926f60 1245}
252b5132
RH		 1246
1247static INLINE int
e3bb37b5 1248fits_in_signed_word (offsetT num)
252b5132
RH		 1249{
1250 return (-32768 <= num) && (num <= 32767);
47926f60 1251}
2a962e6d 1252
3e73aa7c 1253static INLINE int
e3bb37b5 1254fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1255{
1256#ifndef BFD64
1257 return 1;
1258#else
1259 return (!(((offsetT) -1 << 31) & num)
1260 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1261#endif
1262} /* fits_in_signed_long() */
2a962e6d 1263
3e73aa7c 1264static INLINE int
e3bb37b5 1265fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1266{
1267#ifndef BFD64
1268 return 1;
1269#else
1270 return (num & (((offsetT) 2 << 31) - 1)) == num;
1271#endif
1272} /* fits_in_unsigned_long() */
252b5132 1273
40fb9820 1274static i386_operand_type
e3bb37b5 1275smallest_imm_type (offsetT num)
252b5132 1276{
40fb9820
L		 1277 i386_operand_type t;
1278
c6fb90c8 1279 UINTS_CLEAR (t);
40fb9820
L		 1280 t.bitfield.imm64 = 1;
1281
1282 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1283 {
1284 /* This code is disabled on the 486 because all the Imm1 forms
1285 in the opcode table are slower on the i486. They're the
1286 versions with the implicitly specified single-position
1287 displacement, which has another syntax if you really want to
1288 use that form. */
40fb9820
L		 1289 t.bitfield.imm1 = 1;
1290 t.bitfield.imm8 = 1;
1291 t.bitfield.imm8s = 1;
1292 t.bitfield.imm16 = 1;
1293 t.bitfield.imm32 = 1;
1294 t.bitfield.imm32s = 1;
1295 }
1296 else if (fits_in_signed_byte (num))
1297 {
1298 t.bitfield.imm8 = 1;
1299 t.bitfield.imm8s = 1;
1300 t.bitfield.imm16 = 1;
1301 t.bitfield.imm32 = 1;
1302 t.bitfield.imm32s = 1;
1303 }
1304 else if (fits_in_unsigned_byte (num))
1305 {
1306 t.bitfield.imm8 = 1;
1307 t.bitfield.imm16 = 1;
1308 t.bitfield.imm32 = 1;
1309 t.bitfield.imm32s = 1;
1310 }
1311 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1312 {
1313 t.bitfield.imm16 = 1;
1314 t.bitfield.imm32 = 1;
1315 t.bitfield.imm32s = 1;
1316 }
1317 else if (fits_in_signed_long (num))
1318 {
1319 t.bitfield.imm32 = 1;
1320 t.bitfield.imm32s = 1;
1321 }
1322 else if (fits_in_unsigned_long (num))
1323 t.bitfield.imm32 = 1;
1324
1325 return t;
47926f60 1326}
252b5132 1327
847f7ad4 1328static offsetT
e3bb37b5 1329offset_in_range (offsetT val, int size)
847f7ad4 1330{
508866be 1331 addressT mask;
ba2adb93 1332
847f7ad4
AM		 1333 switch (size)
1334 {
508866be
L		 1335 case 1: mask = ((addressT) 1 << 8) - 1; break;
1336 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1337 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1338#ifdef BFD64
1339 case 8: mask = ((addressT) 2 << 63) - 1; break;
1340#endif
47926f60 1341 default: abort ();
847f7ad4
AM		 1342 }
1343
ba2adb93 1344 /* If BFD64, sign extend val. */
3e73aa7c
JH		 1345 if (!use_rela_relocations)
1346 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1347 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 1348
47926f60 1349 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1350 {
1351 char buf1[40], buf2[40];
1352
1353 sprint_value (buf1, val);
1354 sprint_value (buf2, val & mask);
1355 as_warn (_("%s shortened to %s"), buf1, buf2);
1356 }
1357 return val & mask;
1358}
1359
252b5132
RH		 1360/* Returns 0 if attempting to add a prefix where one from the same
1361 class already exists, 1 if non rep/repne added, 2 if rep/repne
1362 added. */
1363static int
e3bb37b5 1364add_prefix (unsigned int prefix)
252b5132
RH		 1365{
1366 int ret = 1;
b1905489 1367 unsigned int q;
252b5132 1368
29b0f896
AM		 1369 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1370 && flag_code == CODE_64BIT)
b1905489 1371 {
161a04f6
L		 1372 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1373 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1374 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 1375 ret = 0;
1376 q = REX_PREFIX;
1377 }
3e73aa7c 1378 else
b1905489
JB		 1379 {
1380 switch (prefix)
1381 {
1382 default:
1383 abort ();
1384
1385 case CS_PREFIX_OPCODE:
1386 case DS_PREFIX_OPCODE:
1387 case ES_PREFIX_OPCODE:
1388 case FS_PREFIX_OPCODE:
1389 case GS_PREFIX_OPCODE:
1390 case SS_PREFIX_OPCODE:
1391 q = SEG_PREFIX;
1392 break;
1393
1394 case REPNE_PREFIX_OPCODE:
1395 case REPE_PREFIX_OPCODE:
1396 ret = 2;
1397 /* fall thru */
1398 case LOCK_PREFIX_OPCODE:
1399 q = LOCKREP_PREFIX;
1400 break;
1401
1402 case FWAIT_OPCODE:
1403 q = WAIT_PREFIX;
1404 break;
1405
1406 case ADDR_PREFIX_OPCODE:
1407 q = ADDR_PREFIX;
1408 break;
1409
1410 case DATA_PREFIX_OPCODE:
1411 q = DATA_PREFIX;
1412 break;
1413 }
1414 if (i.prefix[q] != 0)
1415 ret = 0;
1416 }
252b5132 1417
b1905489 1418 if (ret)
252b5132 1419 {
b1905489
JB		 1420 if (!i.prefix[q])
1421 ++i.prefixes;
1422 i.prefix[q] |= prefix;
252b5132 1423 }
b1905489
JB		 1424 else
1425 as_bad (_("same type of prefix used twice"));
252b5132 1426
252b5132
RH		 1427 return ret;
1428}
1429
1430static void
e3bb37b5 1431set_code_flag (int value)
eecb386c 1432{
3e73aa7c 1433 flag_code = value;
40fb9820
L		 1434 if (flag_code == CODE_64BIT)
1435 {
1436 cpu_arch_flags.bitfield.cpu64 = 1;
1437 cpu_arch_flags.bitfield.cpuno64 = 0;
1438 cpu_arch_flags_not.bitfield.cpu64 = 0;
1439 cpu_arch_flags_not.bitfield.cpuno64 = 1;
1440 }
1441 else
1442 {
1443 cpu_arch_flags.bitfield.cpu64 = 0;
1444 cpu_arch_flags.bitfield.cpuno64 = 1;
1445 cpu_arch_flags_not.bitfield.cpu64 = 1;
1446 cpu_arch_flags_not.bitfield.cpuno64 = 0;
1447 }
1448 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1449 {
1450 as_bad (_("64bit mode not supported on this CPU."));
1451 }
40fb9820 1452 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1453 {
1454 as_bad (_("32bit mode not supported on this CPU."));
1455 }
eecb386c
AM		 1456 stackop_size = '\0';
1457}
1458
1459static void
e3bb37b5 1460set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1461{
3e73aa7c 1462 flag_code = new_code_flag;
40fb9820
L		 1463 if (flag_code != CODE_16BIT)
1464 abort ();
1465 cpu_arch_flags.bitfield.cpu64 = 0;
1466 cpu_arch_flags.bitfield.cpuno64 = 1;
1467 cpu_arch_flags_not.bitfield.cpu64 = 1;
1468 cpu_arch_flags_not.bitfield.cpuno64 = 0;
9306ca4a 1469 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1470}
1471
1472static void
e3bb37b5 1473set_intel_syntax (int syntax_flag)
252b5132
RH		 1474{
1475 /* Find out if register prefixing is specified. */
1476 int ask_naked_reg = 0;
1477
1478 SKIP_WHITESPACE ();
29b0f896 1479 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1480 {
1481 char *string = input_line_pointer;
1482 int e = get_symbol_end ();
1483
47926f60 1484 if (strcmp (string, "prefix") == 0)
252b5132 1485 ask_naked_reg = 1;
47926f60 1486 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1487 ask_naked_reg = -1;
1488 else
d0b47220 1489 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1490 *input_line_pointer = e;
1491 }
1492 demand_empty_rest_of_line ();
c3332e24 1493
252b5132
RH		 1494 intel_syntax = syntax_flag;
1495
1496 if (ask_naked_reg == 0)
f86103b7
AM		 1497 allow_naked_reg = (intel_syntax
1498 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1499 else
1500 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1501
e4a3b5a4 1502 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1503 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1504 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1505}
1506
db51cc60
L		 1507static void
1508set_allow_index_reg (int flag)
1509{
1510 allow_index_reg = flag;
1511}
1512
e413e4e9 1513static void
e3bb37b5 1514set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1515{
47926f60 1516 SKIP_WHITESPACE ();
e413e4e9 1517
29b0f896 1518 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1519 {
1520 char *string = input_line_pointer;
1521 int e = get_symbol_end ();
9103f4f4 1522 unsigned int i;
40fb9820 1523 i386_cpu_flags flags;
e413e4e9 1524
9103f4f4 1525 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1526 {
1527 if (strcmp (string, cpu_arch[i].name) == 0)
1528 {
5c6af06e
JB		 1529 if (*string != '.')
1530 {
1531 cpu_arch_name = cpu_arch[i].name;
1532 cpu_sub_arch_name = NULL;
40fb9820
L		 1533 cpu_arch_flags = cpu_arch[i].flags;
1534 if (flag_code == CODE_64BIT)
1535 {
1536 cpu_arch_flags.bitfield.cpu64 = 1;
1537 cpu_arch_flags.bitfield.cpuno64 = 0;
1538 }
1539 else
1540 {
1541 cpu_arch_flags.bitfield.cpu64 = 0;
1542 cpu_arch_flags.bitfield.cpuno64 = 1;
1543 }
1544 cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
ccc9c027 1545 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1546 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1547 if (!cpu_arch_tune_set)
1548 {
1549 cpu_arch_tune = cpu_arch_isa;
1550 cpu_arch_tune_flags = cpu_arch_isa_flags;
1551 }
5c6af06e
JB		 1552 break;
1553 }
40fb9820 1554
c6fb90c8
L		 1555 flags = cpu_flags_or (cpu_arch_flags,
1556 cpu_arch[i].flags);
1557 if (!UINTS_EQUAL (flags, cpu_arch_flags))
5c6af06e
JB		 1558 {
1559 cpu_sub_arch_name = cpu_arch[i].name;
40fb9820
L		 1560 cpu_arch_flags = flags;
1561 cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
5c6af06e
JB		 1562 }
1563 *input_line_pointer = e;
1564 demand_empty_rest_of_line ();
1565 return;
e413e4e9
AM		 1566 }
1567 }
9103f4f4 1568 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1569 as_bad (_("no such architecture: `%s'"), string);
1570
1571 *input_line_pointer = e;
1572 }
1573 else
1574 as_bad (_("missing cpu architecture"));
1575
fddf5b5b
AM		 1576 no_cond_jump_promotion = 0;
1577 if (*input_line_pointer == ','
29b0f896 1578 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1579 {
1580 char *string = ++input_line_pointer;
1581 int e = get_symbol_end ();
1582
1583 if (strcmp (string, "nojumps") == 0)
1584 no_cond_jump_promotion = 1;
1585 else if (strcmp (string, "jumps") == 0)
1586 ;
1587 else
1588 as_bad (_("no such architecture modifier: `%s'"), string);
1589
1590 *input_line_pointer = e;
1591 }
1592
e413e4e9
AM		 1593 demand_empty_rest_of_line ();
1594}
1595
b9d79e03
JH		 1596unsigned long
1597i386_mach ()
1598{
1599 if (!strcmp (default_arch, "x86_64"))
1600 return bfd_mach_x86_64;
1601 else if (!strcmp (default_arch, "i386"))
1602 return bfd_mach_i386_i386;
1603 else
1604 as_fatal (_("Unknown architecture"));
1605}
b9d79e03 1606\f
252b5132
RH		 1607void
1608md_begin ()
1609{
1610 const char *hash_err;
1611
40fb9820
L		 1612 cpu_arch_flags_not = cpu_flags_not (cpu_arch_flags);
1613
47926f60 1614 /* Initialize op_hash hash table. */
252b5132
RH		 1615 op_hash = hash_new ();
1616
1617 {
29b0f896
AM		 1618 const template *optab;
1619 templates *core_optab;
252b5132 1620
47926f60
KH		 1621 /* Setup for loop. */
1622 optab = i386_optab;
252b5132
RH		 1623 core_optab = (templates *) xmalloc (sizeof (templates));
1624 core_optab->start = optab;
1625
1626 while (1)
1627 {
1628 ++optab;
1629 if (optab->name == NULL
1630 || strcmp (optab->name, (optab - 1)->name) != 0)
1631 {
1632 /* different name --> ship out current template list;
47926f60 1633 add to hash table; & begin anew. */
252b5132
RH		 1634 core_optab->end = optab;
1635 hash_err = hash_insert (op_hash,
1636 (optab - 1)->name,
1637 (PTR) core_optab);
1638 if (hash_err)
1639 {
252b5132
RH		 1640 as_fatal (_("Internal Error: Can't hash %s: %s"),
1641 (optab - 1)->name,
1642 hash_err);
1643 }
1644 if (optab->name == NULL)
1645 break;
1646 core_optab = (templates *) xmalloc (sizeof (templates));
1647 core_optab->start = optab;
1648 }
1649 }
1650 }
1651
47926f60 1652 /* Initialize reg_hash hash table. */
252b5132
RH		 1653 reg_hash = hash_new ();
1654 {
29b0f896 1655 const reg_entry *regtab;
c3fe08fa 1656 unsigned int regtab_size = i386_regtab_size;
252b5132 1657
c3fe08fa 1658 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132
RH		 1659 {
1660 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1661 if (hash_err)
3e73aa7c
JH		 1662 as_fatal (_("Internal Error: Can't hash %s: %s"),
1663 regtab->reg_name,
1664 hash_err);
252b5132
RH		 1665 }
1666 }
1667
47926f60 1668 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 1669 {
29b0f896
AM		 1670 int c;
1671 char *p;
252b5132
RH		 1672
1673 for (c = 0; c < 256; c++)
1674 {
3882b010 1675 if (ISDIGIT (c))
252b5132
RH		 1676 {
1677 digit_chars[c] = c;
1678 mnemonic_chars[c] = c;
1679 register_chars[c] = c;
1680 operand_chars[c] = c;
1681 }
3882b010 1682 else if (ISLOWER (c))
252b5132
RH		 1683 {
1684 mnemonic_chars[c] = c;
1685 register_chars[c] = c;
1686 operand_chars[c] = c;
1687 }
3882b010 1688 else if (ISUPPER (c))
252b5132 1689 {
3882b010 1690 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1691 register_chars[c] = mnemonic_chars[c];
1692 operand_chars[c] = c;
1693 }
1694
3882b010 1695 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1696 identifier_chars[c] = c;
1697 else if (c >= 128)
1698 {
1699 identifier_chars[c] = c;
1700 operand_chars[c] = c;
1701 }
1702 }
1703
1704#ifdef LEX_AT
1705 identifier_chars['@'] = '@';
32137342
NC		 1706#endif
1707#ifdef LEX_QM
1708 identifier_chars['?'] = '?';
1709 operand_chars['?'] = '?';
252b5132 1710#endif
252b5132 1711 digit_chars['-'] = '-';
791fe849 1712 mnemonic_chars['-'] = '-';
0003779b 1713 mnemonic_chars['.'] = '.';
252b5132
RH		 1714 identifier_chars['_'] = '_';
1715 identifier_chars['.'] = '.';
1716
1717 for (p = operand_special_chars; *p != '\0'; p++)
1718 operand_chars[(unsigned char) *p] = *p;
1719 }
1720
1721#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1722 if (IS_ELF)
252b5132
RH		 1723 {
1724 record_alignment (text_section, 2);
1725 record_alignment (data_section, 2);
1726 record_alignment (bss_section, 2);
1727 }
1728#endif
a4447b93
RH		 1729
1730 if (flag_code == CODE_64BIT)
1731 {
1732 x86_dwarf2_return_column = 16;
1733 x86_cie_data_alignment = -8;
1734 }
1735 else
1736 {
1737 x86_dwarf2_return_column = 8;
1738 x86_cie_data_alignment = -4;
1739 }
252b5132
RH		 1740}
1741
1742void
e3bb37b5 1743i386_print_statistics (FILE *file)
252b5132
RH		 1744{
1745 hash_print_statistics (file, "i386 opcode", op_hash);
1746 hash_print_statistics (file, "i386 register", reg_hash);
1747}
1748\f
252b5132
RH		 1749#ifdef DEBUG386
1750
ce8a8b2f 1751/* Debugging routines for md_assemble. */
e3bb37b5 1752static void pte (template *);
40fb9820 1753static void pt (i386_operand_type);
e3bb37b5
L		 1754static void pe (expressionS *);
1755static void ps (symbolS *);
252b5132
RH		 1756
1757static void
e3bb37b5 1758pi (char *line, i386_insn *x)
252b5132 1759{
09f131f2 1760 unsigned int i;
252b5132
RH		 1761
1762 fprintf (stdout, "%s: template ", line);
1763 pte (&x->tm);
09f131f2
JH		 1764 fprintf (stdout, " address: base %s index %s scale %x\n",
1765 x->base_reg ? x->base_reg->reg_name : "none",
1766 x->index_reg ? x->index_reg->reg_name : "none",
1767 x->log2_scale_factor);
1768 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1769 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1770 fprintf (stdout, " sib: base %x index %x scale %x\n",
1771 x->sib.base, x->sib.index, x->sib.scale);
1772 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 1773 (x->rex & REX_W) != 0,
1774 (x->rex & REX_R) != 0,
1775 (x->rex & REX_X) != 0,
1776 (x->rex & REX_B) != 0);
85f10a01
MM		 1777 fprintf (stdout, " drex: reg %d rex 0x%x\n",
1778 x->drex.reg, x->drex.rex);
252b5132
RH		 1779 for (i = 0; i < x->operands; i++)
1780 {
1781 fprintf (stdout, " #%d: ", i + 1);
1782 pt (x->types[i]);
1783 fprintf (stdout, "\n");
40fb9820
L		 1784 if (x->types[i].bitfield.reg8
1785 || x->types[i].bitfield.reg16
1786 || x->types[i].bitfield.reg32
1787 || x->types[i].bitfield.reg64
1788 || x->types[i].bitfield.regmmx
1789 || x->types[i].bitfield.regxmm
1790 || x->types[i].bitfield.sreg2
1791 || x->types[i].bitfield.sreg3
1792 || x->types[i].bitfield.control
1793 || x->types[i].bitfield.debug
1794 || x->types[i].bitfield.test)
520dc8e8 1795 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 1796 if (operand_type_check (x->types[i], imm))
520dc8e8 1797 pe (x->op[i].imms);
40fb9820 1798 if (operand_type_check (x->types[i], disp))
520dc8e8 1799 pe (x->op[i].disps);
252b5132
RH		 1800 }
1801}
1802
1803static void
e3bb37b5 1804pte (template *t)
252b5132 1805{
09f131f2 1806 unsigned int i;
252b5132 1807 fprintf (stdout, " %d operands ", t->operands);
47926f60 1808 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1809 if (t->extension_opcode != None)
1810 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 1811 if (t->opcode_modifier.d)
252b5132 1812 fprintf (stdout, "D");
40fb9820 1813 if (t->opcode_modifier.w)
252b5132
RH		 1814 fprintf (stdout, "W");
1815 fprintf (stdout, "\n");
1816 for (i = 0; i < t->operands; i++)
1817 {
1818 fprintf (stdout, " #%d type ", i + 1);
1819 pt (t->operand_types[i]);
1820 fprintf (stdout, "\n");
1821 }
1822}
1823
1824static void
e3bb37b5 1825pe (expressionS *e)
252b5132 1826{
24eab124 1827 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1828 fprintf (stdout, " add_number %ld (%lx)\n",
1829 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1830 if (e->X_add_symbol)
1831 {
1832 fprintf (stdout, " add_symbol ");
1833 ps (e->X_add_symbol);
1834 fprintf (stdout, "\n");
1835 }
1836 if (e->X_op_symbol)
1837 {
1838 fprintf (stdout, " op_symbol ");
1839 ps (e->X_op_symbol);
1840 fprintf (stdout, "\n");
1841 }
1842}
1843
1844static void
e3bb37b5 1845ps (symbolS *s)
252b5132
RH		 1846{
1847 fprintf (stdout, "%s type %s%s",
1848 S_GET_NAME (s),
1849 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1850 segment_name (S_GET_SEGMENT (s)));
1851}
1852
7b81dfbb 1853static struct type_name
252b5132 1854 {
40fb9820
L		 1855 i386_operand_type mask;
1856 const char *name;
252b5132 1857 }
7b81dfbb 1858const type_names[] =
252b5132 1859{
40fb9820
L		 1860 { OPERAND_TYPE_REG8, "r8" },
1861 { OPERAND_TYPE_REG16, "r16" },
1862 { OPERAND_TYPE_REG32, "r32" },
1863 { OPERAND_TYPE_REG64, "r64" },
1864 { OPERAND_TYPE_IMM8, "i8" },
1865 { OPERAND_TYPE_IMM8, "i8s" },
1866 { OPERAND_TYPE_IMM16, "i16" },
1867 { OPERAND_TYPE_IMM32, "i32" },
1868 { OPERAND_TYPE_IMM32S, "i32s" },
1869 { OPERAND_TYPE_IMM64, "i64" },
1870 { OPERAND_TYPE_IMM1, "i1" },
1871 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
1872 { OPERAND_TYPE_DISP8, "d8" },
1873 { OPERAND_TYPE_DISP16, "d16" },
1874 { OPERAND_TYPE_DISP32, "d32" },
1875 { OPERAND_TYPE_DISP32S, "d32s" },
1876 { OPERAND_TYPE_DISP64, "d64" },
1877 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
1878 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
1879 { OPERAND_TYPE_CONTROL, "control reg" },
1880 { OPERAND_TYPE_TEST, "test reg" },
1881 { OPERAND_TYPE_DEBUG, "debug reg" },
1882 { OPERAND_TYPE_FLOATREG, "FReg" },
1883 { OPERAND_TYPE_FLOATACC, "FAcc" },
1884 { OPERAND_TYPE_SREG2, "SReg2" },
1885 { OPERAND_TYPE_SREG3, "SReg3" },
1886 { OPERAND_TYPE_ACC, "Acc" },
1887 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
1888 { OPERAND_TYPE_REGMMX, "rMMX" },
1889 { OPERAND_TYPE_REGXMM, "rXMM" },
1890 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 1891};
1892
1893static void
40fb9820 1894pt (i386_operand_type t)
252b5132 1895{
40fb9820 1896 unsigned int j;
c6fb90c8 1897 i386_operand_type a;
252b5132 1898
40fb9820 1899 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 1900 {
1901 a = operand_type_and (t, type_names[j].mask);
1902 if (!UINTS_ALL_ZERO (a))
1903 fprintf (stdout, "%s, ", type_names[j].name);
1904 }
252b5132
RH		 1905 fflush (stdout);
1906}
1907
1908#endif /* DEBUG386 */
1909\f
252b5132 1910static bfd_reloc_code_real_type
3956db08 1911reloc (unsigned int size,
64e74474
AM		 1912 int pcrel,
1913 int sign,
1914 bfd_reloc_code_real_type other)
252b5132 1915{
47926f60 1916 if (other != NO_RELOC)
3956db08
JB		 1917 {
1918 reloc_howto_type *reloc;
1919
1920 if (size == 8)
1921 switch (other)
1922 {
64e74474
AM		 1923 case BFD_RELOC_X86_64_GOT32:
1924 return BFD_RELOC_X86_64_GOT64;
1925 break;
1926 case BFD_RELOC_X86_64_PLTOFF64:
1927 return BFD_RELOC_X86_64_PLTOFF64;
1928 break;
1929 case BFD_RELOC_X86_64_GOTPC32:
1930 other = BFD_RELOC_X86_64_GOTPC64;
1931 break;
1932 case BFD_RELOC_X86_64_GOTPCREL:
1933 other = BFD_RELOC_X86_64_GOTPCREL64;
1934 break;
1935 case BFD_RELOC_X86_64_TPOFF32:
1936 other = BFD_RELOC_X86_64_TPOFF64;
1937 break;
1938 case BFD_RELOC_X86_64_DTPOFF32:
1939 other = BFD_RELOC_X86_64_DTPOFF64;
1940 break;
1941 default:
1942 break;
3956db08 1943 }
e05278af
JB		 1944
1945 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1946 if (size == 4 && flag_code != CODE_64BIT)
1947 sign = -1;
1948
3956db08
JB		 1949 reloc = bfd_reloc_type_lookup (stdoutput, other);
1950 if (!reloc)
1951 as_bad (_("unknown relocation (%u)"), other);
1952 else if (size != bfd_get_reloc_size (reloc))
1953 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1954 bfd_get_reloc_size (reloc),
1955 size);
1956 else if (pcrel && !reloc->pc_relative)
1957 as_bad (_("non-pc-relative relocation for pc-relative field"));
1958 else if ((reloc->complain_on_overflow == complain_overflow_signed
1959 && !sign)
1960 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 1961 && sign > 0))
3956db08
JB		 1962 as_bad (_("relocated field and relocation type differ in signedness"));
1963 else
1964 return other;
1965 return NO_RELOC;
1966 }
252b5132
RH		 1967
1968 if (pcrel)
1969 {
3e73aa7c 1970 if (!sign)
3956db08 1971 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1972 switch (size)
1973 {
1974 case 1: return BFD_RELOC_8_PCREL;
1975 case 2: return BFD_RELOC_16_PCREL;
1976 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1977 case 8: return BFD_RELOC_64_PCREL;
252b5132 1978 }
3956db08 1979 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1980 }
1981 else
1982 {
3956db08 1983 if (sign > 0)
e5cb08ac 1984 switch (size)
3e73aa7c
JH		 1985 {
1986 case 4: return BFD_RELOC_X86_64_32S;
1987 }
1988 else
1989 switch (size)
1990 {
1991 case 1: return BFD_RELOC_8;
1992 case 2: return BFD_RELOC_16;
1993 case 4: return BFD_RELOC_32;
1994 case 8: return BFD_RELOC_64;
1995 }
3956db08
JB		 1996 as_bad (_("cannot do %s %u byte relocation"),
1997 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1998 }
1999
bfb32b52 2000 abort ();
252b5132
RH		 2001 return BFD_RELOC_NONE;
2002}
2003
47926f60
KH		 2004/* Here we decide which fixups can be adjusted to make them relative to
2005 the beginning of the section instead of the symbol. Basically we need
2006 to make sure that the dynamic relocations are done correctly, so in
2007 some cases we force the original symbol to be used. */
2008
252b5132 2009int
e3bb37b5 2010tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2011{
6d249963 2012#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2013 if (!IS_ELF)
31312f95
AM		 2014 return 1;
2015
a161fe53
AM		 2016 /* Don't adjust pc-relative references to merge sections in 64-bit
2017 mode. */
2018 if (use_rela_relocations
2019 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2020 && fixP->fx_pcrel)
252b5132 2021 return 0;
31312f95 2022
8d01d9a9
AJ		 2023 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2024 and changed later by validate_fix. */
2025 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2026 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2027 return 0;
2028
ce8a8b2f 2029 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2030 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2031 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2032 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2033 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2034 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2035 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2036 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2037 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2038 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2039 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2040 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2041 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2042 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2043 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2044 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2045 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2046 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2047 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2048 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2049 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2050 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2051 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2052 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2053 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2054 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2055 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2056 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2057 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2058 return 0;
31312f95 2059#endif
252b5132
RH		 2060 return 1;
2061}
252b5132 2062
b4cac588 2063static int
e3bb37b5 2064intel_float_operand (const char *mnemonic)
252b5132 2065{
9306ca4a
JB		 2066 /* Note that the value returned is meaningful only for opcodes with (memory)
2067 operands, hence the code here is free to improperly handle opcodes that
2068 have no operands (for better performance and smaller code). */
2069
2070 if (mnemonic[0] != 'f')
2071 return 0; /* non-math */
2072
2073 switch (mnemonic[1])
2074 {
2075 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2076 the fs segment override prefix not currently handled because no
2077 call path can make opcodes without operands get here */
2078 case 'i':
2079 return 2 /* integer op */;
2080 case 'l':
2081 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2082 return 3; /* fldcw/fldenv */
2083 break;
2084 case 'n':
2085 if (mnemonic[2] != 'o' /* fnop */)
2086 return 3; /* non-waiting control op */
2087 break;
2088 case 'r':
2089 if (mnemonic[2] == 's')
2090 return 3; /* frstor/frstpm */
2091 break;
2092 case 's':
2093 if (mnemonic[2] == 'a')
2094 return 3; /* fsave */
2095 if (mnemonic[2] == 't')
2096 {
2097 switch (mnemonic[3])
2098 {
2099 case 'c': /* fstcw */
2100 case 'd': /* fstdw */
2101 case 'e': /* fstenv */
2102 case 's': /* fsts[gw] */
2103 return 3;
2104 }
2105 }
2106 break;
2107 case 'x':
2108 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2109 return 0; /* fxsave/fxrstor are not really math ops */
2110 break;
2111 }
252b5132 2112
9306ca4a 2113 return 1;
252b5132
RH		 2114}
2115
2116/* This is the guts of the machine-dependent assembler. LINE points to a
2117 machine dependent instruction. This function is supposed to emit
2118 the frags/bytes it assembles to. */
2119
2120void
2121md_assemble (line)
2122 char *line;
2123{
40fb9820 2124 unsigned int j;
252b5132
RH		 2125 char mnemonic[MAX_MNEM_SIZE];
2126
47926f60 2127 /* Initialize globals. */
252b5132
RH		 2128 memset (&i, '\0', sizeof (i));
2129 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2130 i.reloc[j] = NO_RELOC;
252b5132
RH		 2131 memset (disp_expressions, '\0', sizeof (disp_expressions));
2132 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2133 save_stack_p = save_stack;
252b5132
RH		 2134
2135 /* First parse an instruction mnemonic & call i386_operand for the operands.
2136 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2137 start of a (possibly prefixed) mnemonic. */
252b5132 2138
29b0f896
AM		 2139 line = parse_insn (line, mnemonic);
2140 if (line == NULL)
2141 return;
252b5132 2142
29b0f896
AM		 2143 line = parse_operands (line, mnemonic);
2144 if (line == NULL)
2145 return;
252b5132 2146
29b0f896
AM		 2147 /* Now we've parsed the mnemonic into a set of templates, and have the
2148 operands at hand. */
2149
2150 /* All intel opcodes have reversed operands except for "bound" and
2151 "enter". We also don't reverse intersegment "jmp" and "call"
2152 instructions with 2 immediate operands so that the immediate segment
050dfa73 2153 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2154 if (intel_syntax
2155 && i.operands > 1
29b0f896 2156 && (strcmp (mnemonic, "bound") != 0)
30123838 2157 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2158 && !(operand_type_check (i.types[0], imm)
2159 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2160 swap_operands ();
2161
ec56d5c0
JB		 2162 /* The order of the immediates should be reversed
2163 for 2 immediates extrq and insertq instructions */
2164 if (i.imm_operands == 2
2165 && (strcmp (mnemonic, "extrq") == 0
2166 || strcmp (mnemonic, "insertq") == 0))
2167 swap_2_operands (0, 1);
2168
29b0f896
AM		 2169 if (i.imm_operands)
2170 optimize_imm ();
2171
b300c311
L		 2172 /* Don't optimize displacement for movabs since it only takes 64bit
2173 displacement. */
2174 if (i.disp_operands
2175 && (flag_code != CODE_64BIT
2176 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2177 optimize_disp ();
2178
2179 /* Next, we find a template that matches the given insn,
2180 making sure the overlap of the given operands types is consistent
2181 with the template operand types. */
252b5132 2182
29b0f896
AM		 2183 if (!match_template ())
2184 return;
252b5132 2185
cd61ebfe
AM		 2186 if (intel_syntax)
2187 {
2188 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
2189 if (SYSV386_COMPAT
2190 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
8a2ed489 2191 i.tm.base_opcode ^= Opcode_FloatR;
cd61ebfe
AM		 2192
2193 /* Zap movzx and movsx suffix. The suffix may have been set from
2194 "word ptr" or "byte ptr" on the source operand, but we'll use
2195 the suffix later to choose the destination register. */
2196 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 2197 {
2198 if (i.reg_operands < 2
2199 && !i.suffix
40fb9820
L		 2200 && (!i.tm.opcode_modifier.no_bsuf
2201 || !i.tm.opcode_modifier.no_wsuf
2202 || !i.tm.opcode_modifier.no_lsuf
2203 || !i.tm.opcode_modifier.no_ssuf
2204 || !i.tm.opcode_modifier.no_xsuf
2205 || !i.tm.opcode_modifier.no_qsuf))
9306ca4a
JB		 2206 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2207
2208 i.suffix = 0;
2209 }
cd61ebfe 2210 }
24eab124 2211
40fb9820 2212 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2213 if (!add_prefix (FWAIT_OPCODE))
2214 return;
252b5132 2215
29b0f896 2216 /* Check string instruction segment overrides. */
40fb9820 2217 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 2218 {
2219 if (!check_string ())
5dd0794d 2220 return;
29b0f896 2221 }
5dd0794d 2222
29b0f896
AM		 2223 if (!process_suffix ())
2224 return;
e413e4e9 2225
29b0f896
AM		 2226 /* Make still unresolved immediate matches conform to size of immediate
2227 given in i.suffix. */
2228 if (!finalize_imm ())
2229 return;
252b5132 2230
40fb9820 2231 if (i.types[0].bitfield.imm1)
29b0f896 2232 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 2233
40fb9820 2234 for (j = 0; j < 3; j++)
c6fb90c8
L		 2235 if (i.types[j].bitfield.inoutportreg
2236 || i.types[j].bitfield.shiftcount
2237 || i.types[j].bitfield.acc
2238 || i.types[j].bitfield.floatacc)
40fb9820
L		 2239 i.reg_operands--;
2240
2241 if (i.tm.opcode_modifier.immext)
29b0f896 2242 {
02fc3089
L		 2243 expressionS *exp;
2244
40fb9820 2245 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
ca164297 2246 {
b7d9ef37 2247 /* Streaming SIMD extensions 3 Instructions have the fixed
ca164297
L		 2248 operands with an opcode suffix which is coded in the same
2249 place as an 8-bit immediate field would be. Here we check
2250 those operands and remove them afterwards. */
2251 unsigned int x;
2252
a4622f40 2253 for (x = 0; x < i.operands; x++)
ca164297 2254 if (i.op[x].regs->reg_num != x)
a540244d
L		 2255 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2256 register_prefix,
2257 i.op[x].regs->reg_name,
2258 x + 1,
2259 i.tm.name);
ca164297
L		 2260 i.operands = 0;
2261 }
2262
29b0f896
AM		 2263 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2264 opcode suffix which is coded in the same place as an 8-bit
2265 immediate field would be. Here we fake an 8-bit immediate
85f10a01
MM		 2266 operand from the opcode suffix stored in tm.extension_opcode.
2267 SSE5 also uses this encoding, for some of its 3 argument
2268 instructions. */
252b5132 2269
85f10a01
MM		 2270 assert (i.imm_operands == 0
2271 && (i.operands <= 2
2272 || (i.tm.cpu_flags.bitfield.cpusse5
2273 && i.operands <= 3)));
252b5132 2274
29b0f896
AM		 2275 exp = &im_expressions[i.imm_operands++];
2276 i.op[i.operands].imms = exp;
c6fb90c8 2277 UINTS_CLEAR (i.types[i.operands]);
40fb9820
L		 2278 i.types[i.operands].bitfield.imm8 = 1;
2279 i.operands++;
29b0f896
AM		 2280 exp->X_op = O_constant;
2281 exp->X_add_number = i.tm.extension_opcode;
2282 i.tm.extension_opcode = None;
2283 }
252b5132 2284
29b0f896
AM		 2285 /* For insns with operands there are more diddles to do to the opcode. */
2286 if (i.operands)
2287 {
2288 if (!process_operands ())
2289 return;
2290 }
40fb9820 2291 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 2292 {
2293 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2294 as_warn (_("translating to `%sp'"), i.tm.name);
2295 }
252b5132 2296
29b0f896
AM		 2297 /* Handle conversion of 'int $3' --> special int3 insn. */
2298 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2299 {
2300 i.tm.base_opcode = INT3_OPCODE;
2301 i.imm_operands = 0;
2302 }
252b5132 2303
40fb9820
L		 2304 if ((i.tm.opcode_modifier.jump
2305 || i.tm.opcode_modifier.jumpbyte
2306 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 2307 && i.op[0].disps->X_op == O_constant)
2308 {
2309 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2310 the absolute address given by the constant. Since ix86 jumps and
2311 calls are pc relative, we need to generate a reloc. */
2312 i.op[0].disps->X_add_symbol = &abs_symbol;
2313 i.op[0].disps->X_op = O_symbol;
2314 }
252b5132 2315
40fb9820 2316 if (i.tm.opcode_modifier.rex64)
161a04f6 2317 i.rex |= REX_W;
252b5132 2318
29b0f896
AM		 2319 /* For 8 bit registers we need an empty rex prefix. Also if the
2320 instruction already has a prefix, we need to convert old
2321 registers to new ones. */
773f551c 2322
40fb9820 2323 if ((i.types[0].bitfield.reg8
29b0f896 2324 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 2325 || (i.types[1].bitfield.reg8
29b0f896 2326 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 2327 || ((i.types[0].bitfield.reg8
2328 || i.types[1].bitfield.reg8)
29b0f896
AM		 2329 && i.rex != 0))
2330 {
2331 int x;
726c5dcd 2332
29b0f896
AM		 2333 i.rex |= REX_OPCODE;
2334 for (x = 0; x < 2; x++)
2335 {
2336 /* Look for 8 bit operand that uses old registers. */
40fb9820 2337 if (i.types[x].bitfield.reg8
29b0f896 2338 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 2339 {
29b0f896
AM		 2340 /* In case it is "hi" register, give up. */
2341 if (i.op[x].regs->reg_num > 3)
a540244d 2342 as_bad (_("can't encode register '%s%s' in an "
4eed87de 2343 "instruction requiring REX prefix."),
a540244d 2344 register_prefix, i.op[x].regs->reg_name);
773f551c 2345
29b0f896
AM		 2346 /* Otherwise it is equivalent to the extended register.
2347 Since the encoding doesn't change this is merely
2348 cosmetic cleanup for debug output. */
2349
2350 i.op[x].regs = i.op[x].regs + 8;
773f551c 2351 }
29b0f896
AM		 2352 }
2353 }
773f551c 2354
85f10a01
MM		 2355 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2356 REX prefix. */
2357 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
2358 {
2359 i.drex.rex = i.rex;
2360 i.rex = 0;
2361 }
2362 else if (i.rex != 0)
29b0f896
AM		 2363 add_prefix (REX_OPCODE | i.rex);
2364
2365 /* We are ready to output the insn. */
2366 output_insn ();
2367}
2368
2369static char *
e3bb37b5 2370parse_insn (char *line, char *mnemonic)
29b0f896
AM		 2371{
2372 char *l = line;
2373 char *token_start = l;
2374 char *mnem_p;
5c6af06e
JB		 2375 int supported;
2376 const template *t;
29b0f896
AM		 2377
2378 /* Non-zero if we found a prefix only acceptable with string insns. */
2379 const char *expecting_string_instruction = NULL;
45288df1 2380
29b0f896
AM		 2381 while (1)
2382 {
2383 mnem_p = mnemonic;
2384 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2385 {
2386 mnem_p++;
2387 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 2388 {
29b0f896
AM		 2389 as_bad (_("no such instruction: `%s'"), token_start);
2390 return NULL;
2391 }
2392 l++;
2393 }
2394 if (!is_space_char (*l)
2395 && *l != END_OF_INSN
e44823cf
JB		 2396 && (intel_syntax
2397 || (*l != PREFIX_SEPARATOR
2398 && *l != ',')))
29b0f896
AM		 2399 {
2400 as_bad (_("invalid character %s in mnemonic"),
2401 output_invalid (*l));
2402 return NULL;
2403 }
2404 if (token_start == l)
2405 {
e44823cf 2406 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 2407 as_bad (_("expecting prefix; got nothing"));
2408 else
2409 as_bad (_("expecting mnemonic; got nothing"));
2410 return NULL;
2411 }
45288df1 2412
29b0f896
AM		 2413 /* Look up instruction (or prefix) via hash table. */
2414 current_templates = hash_find (op_hash, mnemonic);
47926f60 2415
29b0f896
AM		 2416 if (*l != END_OF_INSN
2417 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2418 && current_templates
40fb9820 2419 && current_templates->start->opcode_modifier.isprefix)
29b0f896 2420 {
c6fb90c8 2421 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 2422 {
2423 as_bad ((flag_code != CODE_64BIT
2424 ? _("`%s' is only supported in 64-bit mode")
2425 : _("`%s' is not supported in 64-bit mode")),
2426 current_templates->start->name);
2427 return NULL;
2428 }
29b0f896
AM		 2429 /* If we are in 16-bit mode, do not allow addr16 or data16.
2430 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 2431 if ((current_templates->start->opcode_modifier.size16
2432 || current_templates->start->opcode_modifier.size32)
29b0f896 2433 && flag_code != CODE_64BIT
40fb9820 2434 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 2435 ^ (flag_code == CODE_16BIT)))
2436 {
2437 as_bad (_("redundant %s prefix"),
2438 current_templates->start->name);
2439 return NULL;
45288df1 2440 }
29b0f896
AM		 2441 /* Add prefix, checking for repeated prefixes. */
2442 switch (add_prefix (current_templates->start->base_opcode))
2443 {
2444 case 0:
2445 return NULL;
2446 case 2:
2447 expecting_string_instruction = current_templates->start->name;
2448 break;
2449 }
2450 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2451 token_start = ++l;
2452 }
2453 else
2454 break;
2455 }
45288df1 2456
29b0f896
AM		 2457 if (!current_templates)
2458 {
2459 /* See if we can get a match by trimming off a suffix. */
2460 switch (mnem_p[-1])
2461 {
2462 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2463 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2464 i.suffix = SHORT_MNEM_SUFFIX;
2465 else
29b0f896
AM		 2466 case BYTE_MNEM_SUFFIX:
2467 case QWORD_MNEM_SUFFIX:
2468 i.suffix = mnem_p[-1];
2469 mnem_p[-1] = '\0';
2470 current_templates = hash_find (op_hash, mnemonic);
2471 break;
2472 case SHORT_MNEM_SUFFIX:
2473 case LONG_MNEM_SUFFIX:
2474 if (!intel_syntax)
2475 {
2476 i.suffix = mnem_p[-1];
2477 mnem_p[-1] = '\0';
2478 current_templates = hash_find (op_hash, mnemonic);
2479 }
2480 break;
252b5132 2481
29b0f896
AM		 2482 /* Intel Syntax. */
2483 case 'd':
2484 if (intel_syntax)
2485 {
9306ca4a 2486 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2487 i.suffix = SHORT_MNEM_SUFFIX;
2488 else
2489 i.suffix = LONG_MNEM_SUFFIX;
2490 mnem_p[-1] = '\0';
2491 current_templates = hash_find (op_hash, mnemonic);
2492 }
2493 break;
2494 }
2495 if (!current_templates)
2496 {
2497 as_bad (_("no such instruction: `%s'"), token_start);
2498 return NULL;
2499 }
2500 }
252b5132 2501
40fb9820
L		 2502 if (current_templates->start->opcode_modifier.jump
2503 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 2504 {
2505 /* Check for a branch hint. We allow ",pt" and ",pn" for
2506 predict taken and predict not taken respectively.
2507 I'm not sure that branch hints actually do anything on loop
2508 and jcxz insns (JumpByte) for current Pentium4 chips. They
2509 may work in the future and it doesn't hurt to accept them
2510 now. */
2511 if (l[0] == ',' && l[1] == 'p')
2512 {
2513 if (l[2] == 't')
2514 {
2515 if (!add_prefix (DS_PREFIX_OPCODE))
2516 return NULL;
2517 l += 3;
2518 }
2519 else if (l[2] == 'n')
2520 {
2521 if (!add_prefix (CS_PREFIX_OPCODE))
2522 return NULL;
2523 l += 3;
2524 }
2525 }
2526 }
2527 /* Any other comma loses. */
2528 if (*l == ',')
2529 {
2530 as_bad (_("invalid character %s in mnemonic"),
2531 output_invalid (*l));
2532 return NULL;
2533 }
252b5132 2534
29b0f896 2535 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 2536 supported = 0;
2537 for (t = current_templates->start; t < current_templates->end; ++t)
2538 {
40fb9820 2539 if (cpu_flags_match (t->cpu_flags))
64e74474 2540 supported |= 1;
c6fb90c8 2541 if (cpu_flags_check_cpu64 (t->cpu_flags))
64e74474 2542 supported |= 2;
5c6af06e
JB		 2543 }
2544 if (!(supported & 2))
2545 {
2546 as_bad (flag_code == CODE_64BIT
2547 ? _("`%s' is not supported in 64-bit mode")
2548 : _("`%s' is only supported in 64-bit mode"),
2549 current_templates->start->name);
2550 return NULL;
2551 }
2552 if (!(supported & 1))
29b0f896 2553 {
5c6af06e
JB		 2554 as_warn (_("`%s' is not supported on `%s%s'"),
2555 current_templates->start->name,
2556 cpu_arch_name,
2557 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896 2558 }
40fb9820
L		 2559 else if (!cpu_arch_flags.bitfield.cpui386
2560 && (flag_code != CODE_16BIT))
29b0f896
AM		 2561 {
2562 as_warn (_("use .code16 to ensure correct addressing mode"));
2563 }
252b5132 2564
29b0f896 2565 /* Check for rep/repne without a string instruction. */
f41bbced 2566 if (expecting_string_instruction)
29b0f896 2567 {
f41bbced
JB		 2568 static templates override;
2569
2570 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 2571 if (t->opcode_modifier.isstring)
f41bbced
JB		 2572 break;
2573 if (t >= current_templates->end)
2574 {
2575 as_bad (_("expecting string instruction after `%s'"),
64e74474 2576 expecting_string_instruction);
f41bbced
JB		 2577 return NULL;
2578 }
2579 for (override.start = t; t < current_templates->end; ++t)
40fb9820 2580 if (!t->opcode_modifier.isstring)
f41bbced
JB		 2581 break;
2582 override.end = t;
2583 current_templates = &override;
29b0f896 2584 }
252b5132 2585
29b0f896
AM		 2586 return l;
2587}
252b5132 2588
29b0f896 2589static char *
e3bb37b5 2590parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 2591{
2592 char *token_start;
3138f287 2593
29b0f896
AM		 2594 /* 1 if operand is pending after ','. */
2595 unsigned int expecting_operand = 0;
252b5132 2596
29b0f896
AM		 2597 /* Non-zero if operand parens not balanced. */
2598 unsigned int paren_not_balanced;
2599
2600 while (*l != END_OF_INSN)
2601 {
2602 /* Skip optional white space before operand. */
2603 if (is_space_char (*l))
2604 ++l;
2605 if (!is_operand_char (*l) && *l != END_OF_INSN)
2606 {
2607 as_bad (_("invalid character %s before operand %d"),
2608 output_invalid (*l),
2609 i.operands + 1);
2610 return NULL;
2611 }
2612 token_start = l; /* after white space */
2613 paren_not_balanced = 0;
2614 while (paren_not_balanced || *l != ',')
2615 {
2616 if (*l == END_OF_INSN)
2617 {
2618 if (paren_not_balanced)
2619 {
2620 if (!intel_syntax)
2621 as_bad (_("unbalanced parenthesis in operand %d."),
2622 i.operands + 1);
2623 else
2624 as_bad (_("unbalanced brackets in operand %d."),
2625 i.operands + 1);
2626 return NULL;
2627 }
2628 else
2629 break; /* we are done */
2630 }
2631 else if (!is_operand_char (*l) && !is_space_char (*l))
2632 {
2633 as_bad (_("invalid character %s in operand %d"),
2634 output_invalid (*l),
2635 i.operands + 1);
2636 return NULL;
2637 }
2638 if (!intel_syntax)
2639 {
2640 if (*l == '(')
2641 ++paren_not_balanced;
2642 if (*l == ')')
2643 --paren_not_balanced;
2644 }
2645 else
2646 {
2647 if (*l == '[')
2648 ++paren_not_balanced;
2649 if (*l == ']')
2650 --paren_not_balanced;
2651 }
2652 l++;
2653 }
2654 if (l != token_start)
2655 { /* Yes, we've read in another operand. */
2656 unsigned int operand_ok;
2657 this_operand = i.operands++;
2658 if (i.operands > MAX_OPERANDS)
2659 {
2660 as_bad (_("spurious operands; (%d operands/instruction max)"),
2661 MAX_OPERANDS);
2662 return NULL;
2663 }
2664 /* Now parse operand adding info to 'i' as we go along. */
2665 END_STRING_AND_SAVE (l);
2666
2667 if (intel_syntax)
2668 operand_ok =
2669 i386_intel_operand (token_start,
2670 intel_float_operand (mnemonic));
2671 else
2672 operand_ok = i386_operand (token_start);
2673
2674 RESTORE_END_STRING (l);
2675 if (!operand_ok)
2676 return NULL;
2677 }
2678 else
2679 {
2680 if (expecting_operand)
2681 {
2682 expecting_operand_after_comma:
2683 as_bad (_("expecting operand after ','; got nothing"));
2684 return NULL;
2685 }
2686 if (*l == ',')
2687 {
2688 as_bad (_("expecting operand before ','; got nothing"));
2689 return NULL;
2690 }
2691 }
7f3f1ea2 2692
29b0f896
AM		 2693 /* Now *l must be either ',' or END_OF_INSN. */
2694 if (*l == ',')
2695 {
2696 if (*++l == END_OF_INSN)
2697 {
2698 /* Just skip it, if it's \n complain. */
2699 goto expecting_operand_after_comma;
2700 }
2701 expecting_operand = 1;
2702 }
2703 }
2704 return l;
2705}
7f3f1ea2 2706
050dfa73 2707static void
4d456e3d 2708swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 2709{
2710 union i386_op temp_op;
40fb9820 2711 i386_operand_type temp_type;
050dfa73 2712 enum bfd_reloc_code_real temp_reloc;
4eed87de 2713
050dfa73
MM		 2714 temp_type = i.types[xchg2];
2715 i.types[xchg2] = i.types[xchg1];
2716 i.types[xchg1] = temp_type;
2717 temp_op = i.op[xchg2];
2718 i.op[xchg2] = i.op[xchg1];
2719 i.op[xchg1] = temp_op;
2720 temp_reloc = i.reloc[xchg2];
2721 i.reloc[xchg2] = i.reloc[xchg1];
2722 i.reloc[xchg1] = temp_reloc;
2723}
2724
29b0f896 2725static void
e3bb37b5 2726swap_operands (void)
29b0f896 2727{
b7c61d9a 2728 switch (i.operands)
050dfa73 2729 {
b7c61d9a 2730 case 4:
4d456e3d 2731 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 2732 case 3:
2733 case 2:
4d456e3d 2734 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 2735 break;
2736 default:
2737 abort ();
29b0f896 2738 }
29b0f896
AM		 2739
2740 if (i.mem_operands == 2)
2741 {
2742 const seg_entry *temp_seg;
2743 temp_seg = i.seg[0];
2744 i.seg[0] = i.seg[1];
2745 i.seg[1] = temp_seg;
2746 }
2747}
252b5132 2748
29b0f896
AM		 2749/* Try to ensure constant immediates are represented in the smallest
2750 opcode possible. */
2751static void
e3bb37b5 2752optimize_imm (void)
29b0f896
AM		 2753{
2754 char guess_suffix = 0;
2755 int op;
252b5132 2756
29b0f896
AM		 2757 if (i.suffix)
2758 guess_suffix = i.suffix;
2759 else if (i.reg_operands)
2760 {
2761 /* Figure out a suffix from the last register operand specified.
2762 We can't do this properly yet, ie. excluding InOutPortReg,
2763 but the following works for instructions with immediates.
2764 In any case, we can't set i.suffix yet. */
2765 for (op = i.operands; --op >= 0;)
40fb9820
L		 2766 if (i.types[op].bitfield.reg8)
2767 {
2768 guess_suffix = BYTE_MNEM_SUFFIX;
2769 break;
2770 }
2771 else if (i.types[op].bitfield.reg16)
252b5132 2772 {
40fb9820
L		 2773 guess_suffix = WORD_MNEM_SUFFIX;
2774 break;
2775 }
2776 else if (i.types[op].bitfield.reg32)
2777 {
2778 guess_suffix = LONG_MNEM_SUFFIX;
2779 break;
2780 }
2781 else if (i.types[op].bitfield.reg64)
2782 {
2783 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 2784 break;
252b5132 2785 }
29b0f896
AM		 2786 }
2787 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2788 guess_suffix = WORD_MNEM_SUFFIX;
2789
2790 for (op = i.operands; --op >= 0;)
40fb9820 2791 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 2792 {
2793 switch (i.op[op].imms->X_op)
252b5132 2794 {
29b0f896
AM		 2795 case O_constant:
2796 /* If a suffix is given, this operand may be shortened. */
2797 switch (guess_suffix)
252b5132 2798 {
29b0f896 2799 case LONG_MNEM_SUFFIX:
40fb9820
L		 2800 i.types[op].bitfield.imm32 = 1;
2801 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 2802 break;
2803 case WORD_MNEM_SUFFIX:
40fb9820
L		 2804 i.types[op].bitfield.imm16 = 1;
2805 i.types[op].bitfield.imm32 = 1;
2806 i.types[op].bitfield.imm32s = 1;
2807 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 2808 break;
2809 case BYTE_MNEM_SUFFIX:
40fb9820
L		 2810 i.types[op].bitfield.imm8 = 1;
2811 i.types[op].bitfield.imm8s = 1;
2812 i.types[op].bitfield.imm16 = 1;
2813 i.types[op].bitfield.imm32 = 1;
2814 i.types[op].bitfield.imm32s = 1;
2815 i.types[op].bitfield.imm64 = 1;
29b0f896 2816 break;
252b5132 2817 }
252b5132 2818
29b0f896
AM		 2819 /* If this operand is at most 16 bits, convert it
2820 to a signed 16 bit number before trying to see
2821 whether it will fit in an even smaller size.
2822 This allows a 16-bit operand such as $0xffe0 to
2823 be recognised as within Imm8S range. */
40fb9820 2824 if ((i.types[op].bitfield.imm16)
29b0f896 2825 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2826 {
29b0f896
AM		 2827 i.op[op].imms->X_add_number =
2828 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2829 }
40fb9820 2830 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 2831 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2832 == 0))
2833 {
2834 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2835 ^ ((offsetT) 1 << 31))
2836 - ((offsetT) 1 << 31));
2837 }
40fb9820 2838 i.types[op]
c6fb90c8
L		 2839 = operand_type_or (i.types[op],
2840 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 2841
29b0f896
AM		 2842 /* We must avoid matching of Imm32 templates when 64bit
2843 only immediate is available. */
2844 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 2845 i.types[op].bitfield.imm32 = 0;
29b0f896 2846 break;
252b5132 2847
29b0f896
AM		 2848 case O_absent:
2849 case O_register:
2850 abort ();
2851
2852 /* Symbols and expressions. */
2853 default:
9cd96992
JB		 2854 /* Convert symbolic operand to proper sizes for matching, but don't
2855 prevent matching a set of insns that only supports sizes other
2856 than those matching the insn suffix. */
2857 {
40fb9820 2858 i386_operand_type mask, allowed;
9cd96992
JB		 2859 const template *t;
2860
c6fb90c8
L		 2861 UINTS_CLEAR (mask);
2862 UINTS_CLEAR (allowed);
40fb9820 2863
4eed87de
AM		 2864 for (t = current_templates->start;
2865 t < current_templates->end;
2866 ++t)
c6fb90c8
L		 2867 allowed = operand_type_or (allowed,
2868 t->operand_types[op]);
9cd96992
JB		 2869 switch (guess_suffix)
2870 {
2871 case QWORD_MNEM_SUFFIX:
40fb9820
L		 2872 mask.bitfield.imm64 = 1;
2873 mask.bitfield.imm32s = 1;
9cd96992
JB		 2874 break;
2875 case LONG_MNEM_SUFFIX:
40fb9820 2876 mask.bitfield.imm32 = 1;
9cd96992
JB		 2877 break;
2878 case WORD_MNEM_SUFFIX:
40fb9820 2879 mask.bitfield.imm16 = 1;
9cd96992
JB		 2880 break;
2881 case BYTE_MNEM_SUFFIX:
40fb9820 2882 mask.bitfield.imm8 = 1;
9cd96992
JB		 2883 break;
2884 default:
9cd96992
JB		 2885 break;
2886 }
c6fb90c8
L		 2887 allowed = operand_type_and (mask, allowed);
2888 if (!UINTS_ALL_ZERO (allowed))
2889 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 2890 }
29b0f896 2891 break;
252b5132 2892 }
29b0f896
AM		 2893 }
2894}
47926f60 2895
29b0f896
AM		 2896/* Try to use the smallest displacement type too. */
2897static void
e3bb37b5 2898optimize_disp (void)
29b0f896
AM		 2899{
2900 int op;
3e73aa7c 2901
29b0f896 2902 for (op = i.operands; --op >= 0;)
40fb9820 2903 if (operand_type_check (i.types[op], disp))
252b5132 2904 {
b300c311 2905 if (i.op[op].disps->X_op == O_constant)
252b5132 2906 {
b300c311 2907 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2908
40fb9820 2909 if (i.types[op].bitfield.disp16
b300c311
L		 2910 && (disp & ~(offsetT) 0xffff) == 0)
2911 {
2912 /* If this operand is at most 16 bits, convert
2913 to a signed 16 bit number and don't use 64bit
2914 displacement. */
2915 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 2916 i.types[op].bitfield.disp64 = 0;
b300c311 2917 }
40fb9820 2918 if (i.types[op].bitfield.disp32
b300c311
L		 2919 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2920 {
2921 /* If this operand is at most 32 bits, convert
2922 to a signed 32 bit number and don't use 64bit
2923 displacement. */
2924 disp &= (((offsetT) 2 << 31) - 1);
2925 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 2926 i.types[op].bitfield.disp64 = 0;
b300c311 2927 }
40fb9820 2928 if (!disp && i.types[op].bitfield.baseindex)
b300c311 2929 {
40fb9820
L		 2930 i.types[op].bitfield.disp8 = 0;
2931 i.types[op].bitfield.disp16 = 0;
2932 i.types[op].bitfield.disp32 = 0;
2933 i.types[op].bitfield.disp32s = 0;
2934 i.types[op].bitfield.disp64 = 0;
b300c311
L		 2935 i.op[op].disps = 0;
2936 i.disp_operands--;
2937 }
2938 else if (flag_code == CODE_64BIT)
2939 {
2940 if (fits_in_signed_long (disp))
28a9d8f5 2941 {
40fb9820
L		 2942 i.types[op].bitfield.disp64 = 0;
2943 i.types[op].bitfield.disp32s = 1;
28a9d8f5 2944 }
b300c311 2945 if (fits_in_unsigned_long (disp))
40fb9820 2946 i.types[op].bitfield.disp32 = 1;
b300c311 2947 }
40fb9820
L		 2948 if ((i.types[op].bitfield.disp32
2949 || i.types[op].bitfield.disp32s
2950 || i.types[op].bitfield.disp16)
b300c311 2951 && fits_in_signed_byte (disp))
40fb9820 2952 i.types[op].bitfield.disp8 = 1;
252b5132 2953 }
67a4f2b7
AO		 2954 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2955 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2956 {
2957 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2958 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 2959 i.types[op].bitfield.disp8 = 0;
2960 i.types[op].bitfield.disp16 = 0;
2961 i.types[op].bitfield.disp32 = 0;
2962 i.types[op].bitfield.disp32s = 0;
2963 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 2964 }
2965 else
b300c311 2966 /* We only support 64bit displacement on constants. */
40fb9820 2967 i.types[op].bitfield.disp64 = 0;
252b5132 2968 }
29b0f896
AM		 2969}
2970
2971static int
e3bb37b5 2972match_template (void)
29b0f896
AM		 2973{
2974 /* Points to template once we've found it. */
2975 const template *t;
40fb9820 2976 i386_operand_type overlap0, overlap1, overlap2, overlap3;
29b0f896 2977 unsigned int found_reverse_match;
40fb9820
L		 2978 i386_opcode_modifier suffix_check;
2979 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 2980 int addr_prefix_disp;
a5c311ca 2981 unsigned int j;
c6fb90c8 2982 i386_cpu_flags overlap;
29b0f896 2983
f48ff2ae
L		 2984#if MAX_OPERANDS != 4
2985# error "MAX_OPERANDS must be 4."
2986#endif
2987
29b0f896 2988 found_reverse_match = 0;
539e75ad 2989 addr_prefix_disp = -1;
40fb9820
L		 2990
2991 memset (&suffix_check, 0, sizeof (suffix_check));
2992 if (i.suffix == BYTE_MNEM_SUFFIX)
2993 suffix_check.no_bsuf = 1;
2994 else if (i.suffix == WORD_MNEM_SUFFIX)
2995 suffix_check.no_wsuf = 1;
2996 else if (i.suffix == SHORT_MNEM_SUFFIX)
2997 suffix_check.no_ssuf = 1;
2998 else if (i.suffix == LONG_MNEM_SUFFIX)
2999 suffix_check.no_lsuf = 1;
3000 else if (i.suffix == QWORD_MNEM_SUFFIX)
3001 suffix_check.no_qsuf = 1;
3002 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
3003 suffix_check.no_xsuf = 1;
29b0f896 3004
45aa61fe 3005 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3006 {
539e75ad
L		 3007 addr_prefix_disp = -1;
3008
29b0f896
AM		 3009 /* Must have right number of operands. */
3010 if (i.operands != t->operands)
3011 continue;
3012
20592a94 3013 /* Check the suffix, except for some instructions in intel mode. */
40fb9820
L		 3014 if (((t->opcode_modifier.no_bsuf & suffix_check.no_bsuf)
3015 || (t->opcode_modifier.no_wsuf & suffix_check.no_wsuf)
3016 || (t->opcode_modifier.no_lsuf & suffix_check.no_lsuf)
3017 || (t->opcode_modifier.no_ssuf & suffix_check.no_ssuf)
3018 || (t->opcode_modifier.no_qsuf & suffix_check.no_qsuf)
3019 || (t->opcode_modifier.no_xsuf & suffix_check.no_xsuf))
3020 && !(intel_syntax && t->opcode_modifier.ignoresize))
29b0f896
AM		 3021 continue;
3022
a5c311ca
L		 3023 for (j = 0; j < MAX_OPERANDS; j++)
3024 operand_types [j] = t->operand_types [j];
539e75ad 3025
45aa61fe
AM		 3026 /* In general, don't allow 64-bit operands in 32-bit mode. */
3027 if (i.suffix == QWORD_MNEM_SUFFIX
3028 && flag_code != CODE_64BIT
3029 && (intel_syntax
40fb9820 3030 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3031 && !intel_float_operand (t->name))
3032 : intel_float_operand (t->name) != 2)
40fb9820
L		 3033 && ((!operand_types[0].bitfield.regmmx
3034 && !operand_types[0].bitfield.regxmm)
3035 || (!operand_types[t->operands > 1].bitfield.regmmx
3036 && !!operand_types[t->operands > 1].bitfield.regxmm))
45aa61fe
AM		 3037 && (t->base_opcode != 0x0fc7
3038 || t->extension_opcode != 1 /* cmpxchg8b */))
3039 continue;
3040
29b0f896 3041 /* Do not verify operands when there are none. */
c6fb90c8 3042 else
29b0f896 3043 {
c6fb90c8
L		 3044 overlap = cpu_flags_and (t->cpu_flags, cpu_arch_flags_not);
3045 if (!t->operands)
3046 {
3047 if (!UINTS_ALL_ZERO (overlap))
3048 continue;
3049 /* We've found a match; break out of loop. */
3050 break;
3051 }
29b0f896 3052 }
252b5132 3053
539e75ad
L		 3054 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3055 into Disp32/Disp16/Disp32 operand. */
3056 if (i.prefix[ADDR_PREFIX] != 0)
3057 {
40fb9820 3058 /* There should be only one Disp operand. */
539e75ad
L		 3059 switch (flag_code)
3060 {
3061 case CODE_16BIT:
40fb9820
L		 3062 for (j = 0; j < MAX_OPERANDS; j++)
3063 {
3064 if (operand_types[j].bitfield.disp16)
3065 {
3066 addr_prefix_disp = j;
3067 operand_types[j].bitfield.disp32 = 1;
3068 operand_types[j].bitfield.disp16 = 0;
3069 break;
3070 }
3071 }
539e75ad
L		 3072 break;
3073 case CODE_32BIT:
40fb9820
L		 3074 for (j = 0; j < MAX_OPERANDS; j++)
3075 {
3076 if (operand_types[j].bitfield.disp32)
3077 {
3078 addr_prefix_disp = j;
3079 operand_types[j].bitfield.disp32 = 0;
3080 operand_types[j].bitfield.disp16 = 1;
3081 break;
3082 }
3083 }
539e75ad
L		 3084 break;
3085 case CODE_64BIT:
40fb9820
L		 3086 for (j = 0; j < MAX_OPERANDS; j++)
3087 {
3088 if (operand_types[j].bitfield.disp64)
3089 {
3090 addr_prefix_disp = j;
3091 operand_types[j].bitfield.disp64 = 0;
3092 operand_types[j].bitfield.disp32 = 1;
3093 break;
3094 }
3095 }
539e75ad
L		 3096 break;
3097 }
539e75ad
L		 3098 }
3099
c6fb90c8 3100 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3101 switch (t->operands)
3102 {
3103 case 1:
40fb9820 3104 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3105 continue;
3106 break;
3107 case 2:
8b38ad71
L		 3108 /* xchg %eax, %eax is a special case. It is an aliase for nop
3109 only in 32bit mode and we can use opcode 0x90. In 64bit
3110 mode, we can't use 0x90 for xchg %eax, %eax since it should
3111 zero-extend %eax to %rax. */
3112 if (flag_code == CODE_64BIT
3113 && t->base_opcode == 0x90
c6fb90c8
L		 3114 && UINTS_EQUAL (i.types [0], acc32)
3115 && UINTS_EQUAL (i.types [1], acc32))
8b38ad71 3116 continue;
29b0f896 3117 case 3:
f48ff2ae 3118 case 4:
c6fb90c8 3119 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 3120 if (!operand_type_match (overlap0, i.types[0])
3121 || !operand_type_match (overlap1, i.types[1])
cb712a9e 3122 /* monitor in SSE3 is a very special case. The first
708587a4 3123 register and the second register may have different
26186d74
L		 3124 sizes. The same applies to crc32 in SSE4.2. It is
3125 also true for invlpga, vmload, vmrun and vmsave in
3126 SVME. */
cb712a9e 3127 || !((t->base_opcode == 0x0f01
26186d74
L		 3128 && (t->extension_opcode == 0xc8
3129 || t->extension_opcode == 0xd8
3130 || t->extension_opcode == 0xda
3131 || t->extension_opcode == 0xdb
3132 || t->extension_opcode == 0xdf))
381d071f 3133 || t->base_opcode == 0xf20f38f1
40fb9820
L		 3134 || operand_type_register_match (overlap0, i.types[0],
3135 operand_types[0],
3136 overlap1, i.types[1],
3137 operand_types[1])))
29b0f896
AM		 3138 {
3139 /* Check if other direction is valid ... */
40fb9820 3140 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 3141 continue;
3142
3143 /* Try reversing direction of operands. */
c6fb90c8
L		 3144 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3145 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 3146 if (!operand_type_match (overlap0, i.types[0])
3147 || !operand_type_match (overlap1, i.types[1])
3148 || !operand_type_register_match (overlap0, i.types[0],
3149 operand_types[1],
3150 overlap1, i.types[1],
3151 operand_types[0]))
29b0f896
AM		 3152 {
3153 /* Does not match either direction. */
3154 continue;
3155 }
3156 /* found_reverse_match holds which of D or FloatDR
3157 we've found. */
40fb9820 3158 if (t->opcode_modifier.d)
8a2ed489 3159 found_reverse_match = Opcode_D;
40fb9820 3160 else if (t->opcode_modifier.floatd)
8a2ed489
L		 3161 found_reverse_match = Opcode_FloatD;
3162 else
3163 found_reverse_match = 0;
40fb9820 3164 if (t->opcode_modifier.floatr)
8a2ed489 3165 found_reverse_match |= Opcode_FloatR;
29b0f896 3166 }
f48ff2ae 3167 else
29b0f896 3168 {
f48ff2ae 3169 /* Found a forward 2 operand match here. */
d1cbb4db
L		 3170 switch (t->operands)
3171 {
3172 case 4:
c6fb90c8
L		 3173 overlap3 = operand_type_and (i.types[3],
3174 operand_types[3]);
d1cbb4db 3175 case 3:
c6fb90c8
L		 3176 overlap2 = operand_type_and (i.types[2],
3177 operand_types[2]);
d1cbb4db
L		 3178 break;
3179 }
29b0f896 3180
f48ff2ae
L		 3181 switch (t->operands)
3182 {
3183 case 4:
40fb9820
L		 3184 if (!operand_type_match (overlap3, i.types[3])
3185 || !operand_type_register_match (overlap2,
3186 i.types[2],
3187 operand_types[2],
3188 overlap3,
3189 i.types[3],
3190 operand_types[3]))
f48ff2ae
L		 3191 continue;
3192 case 3:
3193 /* Here we make use of the fact that there are no
3194 reverse match 3 operand instructions, and all 3
3195 operand instructions only need to be checked for
3196 register consistency between operands 2 and 3. */
40fb9820
L		 3197 if (!operand_type_match (overlap2, i.types[2])
3198 || !operand_type_register_match (overlap1,
3199 i.types[1],
3200 operand_types[1],
3201 overlap2,
3202 i.types[2],
3203 operand_types[2]))
f48ff2ae
L		 3204 continue;
3205 break;
3206 }
29b0f896 3207 }
f48ff2ae 3208 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 3209 slip through to break. */
3210 }
c6fb90c8 3211 if (!UINTS_ALL_ZERO (overlap))
29b0f896
AM		 3212 {
3213 found_reverse_match = 0;
3214 continue;
3215 }
3216 /* We've found a match; break out of loop. */
3217 break;
3218 }
3219
3220 if (t == current_templates->end)
3221 {
3222 /* We found no match. */
3223 as_bad (_("suffix or operands invalid for `%s'"),
3224 current_templates->start->name);
3225 return 0;
3226 }
252b5132 3227
29b0f896
AM		 3228 if (!quiet_warnings)
3229 {
3230 if (!intel_syntax
40fb9820
L		 3231 && (i.types[0].bitfield.jumpabsolute
3232 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 3233 {
3234 as_warn (_("indirect %s without `*'"), t->name);
3235 }
3236
40fb9820
L		 3237 if (t->opcode_modifier.isprefix
3238 && t->opcode_modifier.ignoresize)
29b0f896
AM		 3239 {
3240 /* Warn them that a data or address size prefix doesn't
3241 affect assembly of the next line of code. */
3242 as_warn (_("stand-alone `%s' prefix"), t->name);
3243 }
3244 }
3245
3246 /* Copy the template we found. */
3247 i.tm = *t;
539e75ad
L		 3248
3249 if (addr_prefix_disp != -1)
3250 i.tm.operand_types[addr_prefix_disp]
3251 = operand_types[addr_prefix_disp];
3252
29b0f896
AM		 3253 if (found_reverse_match)
3254 {
3255 /* If we found a reverse match we must alter the opcode
3256 direction bit. found_reverse_match holds bits to change
3257 (different for int & float insns). */
3258
3259 i.tm.base_opcode ^= found_reverse_match;
3260
539e75ad
L		 3261 i.tm.operand_types[0] = operand_types[1];
3262 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 3263 }
3264
3265 return 1;
3266}
3267
3268static int
e3bb37b5 3269check_string (void)
29b0f896 3270{
40fb9820
L		 3271 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3272 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 3273 {
3274 if (i.seg[0] != NULL && i.seg[0] != &es)
3275 {
3276 as_bad (_("`%s' operand %d must use `%%es' segment"),
3277 i.tm.name,
3278 mem_op + 1);
3279 return 0;
3280 }
3281 /* There's only ever one segment override allowed per instruction.
3282 This instruction possibly has a legal segment override on the
3283 second operand, so copy the segment to where non-string
3284 instructions store it, allowing common code. */
3285 i.seg[0] = i.seg[1];
3286 }
40fb9820 3287 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 3288 {
3289 if (i.seg[1] != NULL && i.seg[1] != &es)
3290 {
3291 as_bad (_("`%s' operand %d must use `%%es' segment"),
3292 i.tm.name,
3293 mem_op + 2);
3294 return 0;
3295 }
3296 }
3297 return 1;
3298}
3299
3300static int
543613e9 3301process_suffix (void)
29b0f896
AM		 3302{
3303 /* If matched instruction specifies an explicit instruction mnemonic
3304 suffix, use it. */
40fb9820
L		 3305 if (i.tm.opcode_modifier.size16)
3306 i.suffix = WORD_MNEM_SUFFIX;
3307 else if (i.tm.opcode_modifier.size32)
3308 i.suffix = LONG_MNEM_SUFFIX;
3309 else if (i.tm.opcode_modifier.size64)
3310 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 3311 else if (i.reg_operands)
3312 {
3313 /* If there's no instruction mnemonic suffix we try to invent one
3314 based on register operands. */
3315 if (!i.suffix)
3316 {
3317 /* We take i.suffix from the last register operand specified,
3318 Destination register type is more significant than source
381d071f
L		 3319 register type. crc32 in SSE4.2 prefers source register
3320 type. */
3321 if (i.tm.base_opcode == 0xf20f38f1)
3322 {
40fb9820
L		 3323 if (i.types[0].bitfield.reg16)
3324 i.suffix = WORD_MNEM_SUFFIX;
3325 else if (i.types[0].bitfield.reg32)
3326 i.suffix = LONG_MNEM_SUFFIX;
3327 else if (i.types[0].bitfield.reg64)
3328 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 3329 }
9344ff29 3330 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 3331 {
40fb9820 3332 if (i.types[0].bitfield.reg8)
20592a94
L		 3333 i.suffix = BYTE_MNEM_SUFFIX;
3334 }
381d071f
L		 3335
3336 if (!i.suffix)
3337 {
3338 int op;
3339
20592a94
L		 3340 if (i.tm.base_opcode == 0xf20f38f1
3341 || i.tm.base_opcode == 0xf20f38f0)
3342 {
3343 /* We have to know the operand size for crc32. */
3344 as_bad (_("ambiguous memory operand size for `%s`"),
3345 i.tm.name);
3346 return 0;
3347 }
3348
381d071f 3349 for (op = i.operands; --op >= 0;)
40fb9820 3350 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 3351 {
40fb9820
L		 3352 if (i.types[op].bitfield.reg8)
3353 {
3354 i.suffix = BYTE_MNEM_SUFFIX;
3355 break;
3356 }
3357 else if (i.types[op].bitfield.reg16)
3358 {
3359 i.suffix = WORD_MNEM_SUFFIX;
3360 break;
3361 }
3362 else if (i.types[op].bitfield.reg32)
3363 {
3364 i.suffix = LONG_MNEM_SUFFIX;
3365 break;
3366 }
3367 else if (i.types[op].bitfield.reg64)
3368 {
3369 i.suffix = QWORD_MNEM_SUFFIX;
3370 break;
3371 }
381d071f
L		 3372 }
3373 }
29b0f896
AM		 3374 }
3375 else if (i.suffix == BYTE_MNEM_SUFFIX)
3376 {
3377 if (!check_byte_reg ())
3378 return 0;
3379 }
3380 else if (i.suffix == LONG_MNEM_SUFFIX)
3381 {
3382 if (!check_long_reg ())
3383 return 0;
3384 }
3385 else if (i.suffix == QWORD_MNEM_SUFFIX)
3386 {
955e1e6a
L		 3387 if (intel_syntax
3388 && i.tm.opcode_modifier.ignoresize
3389 && i.tm.opcode_modifier.no_qsuf)
3390 i.suffix = 0;
3391 else if (!check_qword_reg ())
29b0f896
AM		 3392 return 0;
3393 }
3394 else if (i.suffix == WORD_MNEM_SUFFIX)
3395 {
3396 if (!check_word_reg ())
3397 return 0;
3398 }
40fb9820 3399 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 3400 /* Do nothing if the instruction is going to ignore the prefix. */
3401 ;
3402 else
3403 abort ();
3404 }
40fb9820 3405 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 3406 && !i.suffix
3407 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 3408 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 3409 {
3410 i.suffix = stackop_size;
3411 }
9306ca4a
JB		 3412 else if (intel_syntax
3413 && !i.suffix
40fb9820
L		 3414 && (i.tm.operand_types[0].bitfield.jumpabsolute
3415 || i.tm.opcode_modifier.jumpbyte
3416 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 3417 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
3418 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 3419 {
3420 switch (flag_code)
3421 {
3422 case CODE_64BIT:
40fb9820 3423 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 3424 {
3425 i.suffix = QWORD_MNEM_SUFFIX;
3426 break;
3427 }
3428 case CODE_32BIT:
40fb9820 3429 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 3430 i.suffix = LONG_MNEM_SUFFIX;
3431 break;
3432 case CODE_16BIT:
40fb9820 3433 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 3434 i.suffix = WORD_MNEM_SUFFIX;
3435 break;
3436 }
3437 }
252b5132 3438
9306ca4a 3439 if (!i.suffix)
29b0f896 3440 {
9306ca4a
JB		 3441 if (!intel_syntax)
3442 {
40fb9820 3443 if (i.tm.opcode_modifier.w)
9306ca4a 3444 {
4eed87de
AM		 3445 as_bad (_("no instruction mnemonic suffix given and "
3446 "no register operands; can't size instruction"));
9306ca4a
JB		 3447 return 0;
3448 }
3449 }
3450 else
3451 {
40fb9820
L		 3452 unsigned int suffixes;
3453
3454 suffixes = !i.tm.opcode_modifier.no_bsuf;
3455 if (!i.tm.opcode_modifier.no_wsuf)
3456 suffixes |= 1 << 1;
3457 if (!i.tm.opcode_modifier.no_lsuf)
3458 suffixes |= 1 << 2;
3459 if (!i.tm.opcode_modifier.no_lsuf)
3460 suffixes |= 1 << 3;
3461 if (!i.tm.opcode_modifier.no_ssuf)
3462 suffixes |= 1 << 4;
3463 if (!i.tm.opcode_modifier.no_qsuf)
3464 suffixes |= 1 << 5;
3465
3466 /* There are more than suffix matches. */
3467 if (i.tm.opcode_modifier.w
9306ca4a 3468 || ((suffixes & (suffixes - 1))
40fb9820
L		 3469 && !i.tm.opcode_modifier.defaultsize
3470 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 3471 {
3472 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3473 return 0;
3474 }
3475 }
29b0f896 3476 }
252b5132 3477
9306ca4a
JB		 3478 /* Change the opcode based on the operand size given by i.suffix;
3479 We don't need to change things for byte insns. */
3480
29b0f896
AM		 3481 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
3482 {
3483 /* It's not a byte, select word/dword operation. */
40fb9820 3484 if (i.tm.opcode_modifier.w)
29b0f896 3485 {
40fb9820 3486 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 3487 i.tm.base_opcode |= 8;
3488 else
3489 i.tm.base_opcode |= 1;
3490 }
0f3f3d8b 3491
29b0f896
AM		 3492 /* Now select between word & dword operations via the operand
3493 size prefix, except for instructions that will ignore this
3494 prefix anyway. */
26186d74
L		 3495 if (i.tm.base_opcode == 0x0f01
3496 && (i.tm.extension_opcode == 0xc8
3497 || i.tm.extension_opcode == 0xd8
3498 || i.tm.extension_opcode == 0xda
3499 || i.tm.extension_opcode == 0xdb
3500 || i.tm.extension_opcode == 0xdf))
cb712a9e
L		 3501 {
3502 /* monitor in SSE3 is a very special case. The default size
3503 of AX is the size of mode. The address size override
26186d74
L		 3504 prefix will change the size of AX. It is also true for
3505 invlpga, vmload, vmrun and vmsave in SVME. */
40fb9820
L		 3506 if ((flag_code == CODE_32BIT
3507 && i.op->regs[0].reg_type.bitfield.reg16)
3508 || (flag_code != CODE_32BIT
3509 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 3510 if (!add_prefix (ADDR_PREFIX_OPCODE))
3511 return 0;
3512 }
3513 else if (i.suffix != QWORD_MNEM_SUFFIX
3514 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 3515 && !i.tm.opcode_modifier.ignoresize
3516 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 3517 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3518 || (flag_code == CODE_64BIT
40fb9820 3519 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 3520 {
3521 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 3522
40fb9820 3523 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 3524 prefix = ADDR_PREFIX_OPCODE;
252b5132 3525
29b0f896
AM		 3526 if (!add_prefix (prefix))
3527 return 0;
24eab124 3528 }
252b5132 3529
29b0f896
AM		 3530 /* Set mode64 for an operand. */
3531 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 3532 && flag_code == CODE_64BIT
40fb9820 3533 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 3534 {
3535 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 3536 need rex64. cmpxchg8b is also a special case. */
3537 if (! (i.operands == 2
3538 && i.tm.base_opcode == 0x90
3539 && i.tm.extension_opcode == None
c6fb90c8
L		 3540 && UINTS_EQUAL (i.types [0], acc64)
3541 && UINTS_EQUAL (i.types [1], acc64))
d9a5e5e5
L		 3542 && ! (i.operands == 1
3543 && i.tm.base_opcode == 0xfc7
3544 && i.tm.extension_opcode == 1
40fb9820
L		 3545 && !operand_type_check (i.types [0], reg)
3546 && operand_type_check (i.types [0], anymem)))
f6bee062 3547 i.rex |= REX_W;
46e883c5 3548 }
3e73aa7c 3549
29b0f896
AM		 3550 /* Size floating point instruction. */
3551 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 3552 if (i.tm.opcode_modifier.floatmf)
543613e9 3553 i.tm.base_opcode ^= 4;
29b0f896 3554 }
7ecd2f8b 3555
29b0f896
AM		 3556 return 1;
3557}
3e73aa7c 3558
29b0f896 3559static int
543613e9 3560check_byte_reg (void)
29b0f896
AM		 3561{
3562 int op;
543613e9 3563
29b0f896
AM		 3564 for (op = i.operands; --op >= 0;)
3565 {
3566 /* If this is an eight bit register, it's OK. If it's the 16 or
3567 32 bit version of an eight bit register, we will just use the
3568 low portion, and that's OK too. */
40fb9820 3569 if (i.types[op].bitfield.reg8)
29b0f896
AM		 3570 continue;
3571
c3ad16c0
L		 3572 /* movzx, movsx, pextrb and pinsrb should not generate this
3573 warning. */
29b0f896
AM		 3574 if (intel_syntax
3575 && (i.tm.base_opcode == 0xfb7
3576 || i.tm.base_opcode == 0xfb6
3577 || i.tm.base_opcode == 0x63
3578 || i.tm.base_opcode == 0xfbe
c3ad16c0
L		 3579 || i.tm.base_opcode == 0xfbf
3580 || i.tm.base_opcode == 0x660f3a14
3581 || i.tm.base_opcode == 0x660f3a20))
29b0f896
AM		 3582 continue;
3583
9344ff29
L		 3584 /* crc32 doesn't generate this warning. */
3585 if (i.tm.base_opcode == 0xf20f38f0)
3586 continue;
3587
40fb9820
L		 3588 if ((i.types[op].bitfield.reg16
3589 || i.types[op].bitfield.reg32
3590 || i.types[op].bitfield.reg64)
3591 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 3592 {
3593 /* Prohibit these changes in the 64bit mode, since the
3594 lowering is more complicated. */
3595 if (flag_code == CODE_64BIT
40fb9820 3596 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 3597 {
2ca3ace5
L		 3598 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3599 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3600 i.suffix);
3601 return 0;
3602 }
3603#if REGISTER_WARNINGS
3604 if (!quiet_warnings
40fb9820 3605 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 3606 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3607 register_prefix,
40fb9820 3608 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 3609 ? REGNAM_AL - REGNAM_AX
3610 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 3611 register_prefix,
29b0f896
AM		 3612 i.op[op].regs->reg_name,
3613 i.suffix);
3614#endif
3615 continue;
3616 }
3617 /* Any other register is bad. */
40fb9820
L		 3618 if (i.types[op].bitfield.reg16
3619 || i.types[op].bitfield.reg32
3620 || i.types[op].bitfield.reg64
3621 || i.types[op].bitfield.regmmx
3622 || i.types[op].bitfield.regxmm
3623 || i.types[op].bitfield.sreg2
3624 || i.types[op].bitfield.sreg3
3625 || i.types[op].bitfield.control
3626 || i.types[op].bitfield.debug
3627 || i.types[op].bitfield.test
3628 || i.types[op].bitfield.floatreg
3629 || i.types[op].bitfield.floatacc)
29b0f896 3630 {
a540244d
L		 3631 as_bad (_("`%s%s' not allowed with `%s%c'"),
3632 register_prefix,
29b0f896
AM		 3633 i.op[op].regs->reg_name,
3634 i.tm.name,
3635 i.suffix);
3636 return 0;
3637 }
3638 }
3639 return 1;
3640}
3641
3642static int
e3bb37b5 3643check_long_reg (void)
29b0f896
AM		 3644{
3645 int op;
3646
3647 for (op = i.operands; --op >= 0;)
3648 /* Reject eight bit registers, except where the template requires
3649 them. (eg. movzb) */
40fb9820
L		 3650 if (i.types[op].bitfield.reg8
3651 && (i.tm.operand_types[op].bitfield.reg16
3652 || i.tm.operand_types[op].bitfield.reg32
3653 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3654 {
a540244d
L		 3655 as_bad (_("`%s%s' not allowed with `%s%c'"),
3656 register_prefix,
29b0f896
AM		 3657 i.op[op].regs->reg_name,
3658 i.tm.name,
3659 i.suffix);
3660 return 0;
3661 }
3662 /* Warn if the e prefix on a general reg is missing. */
3663 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 3664 && i.types[op].bitfield.reg16
3665 && (i.tm.operand_types[op].bitfield.reg32
3666 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 3667 {
3668 /* Prohibit these changes in the 64bit mode, since the
3669 lowering is more complicated. */
3670 if (flag_code == CODE_64BIT)
252b5132 3671 {
2ca3ace5
L		 3672 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3673 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3674 i.suffix);
3675 return 0;
252b5132 3676 }
29b0f896
AM		 3677#if REGISTER_WARNINGS
3678 else
a540244d
L		 3679 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3680 register_prefix,
29b0f896 3681 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 3682 register_prefix,
29b0f896
AM		 3683 i.op[op].regs->reg_name,
3684 i.suffix);
3685#endif
252b5132 3686 }
29b0f896 3687 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 3688 else if (i.types[op].bitfield.reg64
3689 && (i.tm.operand_types[op].bitfield.reg32
3690 || i.tm.operand_types[op].bitfield.acc))
252b5132 3691 {
34828aad 3692 if (intel_syntax
07e8d93c
L		 3693 && (i.tm.base_opcode == 0xf30f2d
3694 || i.tm.base_opcode == 0xf30f2c)
40fb9820 3695 && !i.types[0].bitfield.regxmm)
34828aad 3696 {
07e8d93c
L		 3697 /* cvtss2si/cvttss2si convert DWORD memory to Reg64. We
3698 want REX byte. */
34828aad
L		 3699 i.suffix = QWORD_MNEM_SUFFIX;
3700 }
3701 else
3702 {
3703 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3704 register_prefix, i.op[op].regs->reg_name,
3705 i.suffix);
3706 return 0;
3707 }
29b0f896
AM		 3708 }
3709 return 1;
3710}
252b5132 3711
29b0f896 3712static int
e3bb37b5 3713check_qword_reg (void)
29b0f896
AM		 3714{
3715 int op;
252b5132 3716
29b0f896
AM		 3717 for (op = i.operands; --op >= 0; )
3718 /* Reject eight bit registers, except where the template requires
3719 them. (eg. movzb) */
40fb9820
L		 3720 if (i.types[op].bitfield.reg8
3721 && (i.tm.operand_types[op].bitfield.reg16
3722 || i.tm.operand_types[op].bitfield.reg32
3723 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3724 {
a540244d
L		 3725 as_bad (_("`%s%s' not allowed with `%s%c'"),
3726 register_prefix,
29b0f896
AM		 3727 i.op[op].regs->reg_name,
3728 i.tm.name,
3729 i.suffix);
3730 return 0;
3731 }
3732 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 3733 else if ((i.types[op].bitfield.reg16
3734 || i.types[op].bitfield.reg32)
3735 && (i.tm.operand_types[op].bitfield.reg32
3736 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 3737 {
3738 /* Prohibit these changes in the 64bit mode, since the
3739 lowering is more complicated. */
34828aad 3740 if (intel_syntax
07e8d93c
L		 3741 && (i.tm.base_opcode == 0xf20f2d
3742 || i.tm.base_opcode == 0xf20f2c)
40fb9820 3743 && !i.types[0].bitfield.regxmm)
34828aad 3744 {
07e8d93c
L		 3745 /* cvtsd2si/cvttsd2si convert QWORD memory to Reg32. We
3746 don't want REX byte. */
34828aad
L		 3747 i.suffix = LONG_MNEM_SUFFIX;
3748 }
3749 else
3750 {
3751 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3752 register_prefix, i.op[op].regs->reg_name,
3753 i.suffix);
3754 return 0;
3755 }
252b5132 3756 }
29b0f896
AM		 3757 return 1;
3758}
252b5132 3759
29b0f896 3760static int
e3bb37b5 3761check_word_reg (void)
29b0f896
AM		 3762{
3763 int op;
3764 for (op = i.operands; --op >= 0;)
3765 /* Reject eight bit registers, except where the template requires
3766 them. (eg. movzb) */
40fb9820
L		 3767 if (i.types[op].bitfield.reg8
3768 && (i.tm.operand_types[op].bitfield.reg16
3769 || i.tm.operand_types[op].bitfield.reg32
3770 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3771 {
a540244d
L		 3772 as_bad (_("`%s%s' not allowed with `%s%c'"),
3773 register_prefix,
29b0f896
AM		 3774 i.op[op].regs->reg_name,
3775 i.tm.name,
3776 i.suffix);
3777 return 0;
3778 }
3779 /* Warn if the e prefix on a general reg is present. */
3780 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 3781 && i.types[op].bitfield.reg32
3782 && (i.tm.operand_types[op].bitfield.reg16
3783 || i.tm.operand_types[op].bitfield.acc))
252b5132 3784 {
29b0f896
AM		 3785 /* Prohibit these changes in the 64bit mode, since the
3786 lowering is more complicated. */
3787 if (flag_code == CODE_64BIT)
252b5132 3788 {
2ca3ace5
L		 3789 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3790 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3791 i.suffix);
3792 return 0;
252b5132 3793 }
29b0f896
AM		 3794 else
3795#if REGISTER_WARNINGS
a540244d
L		 3796 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3797 register_prefix,
29b0f896 3798 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 3799 register_prefix,
29b0f896
AM		 3800 i.op[op].regs->reg_name,
3801 i.suffix);
3802#endif
3803 }
3804 return 1;
3805}
252b5132 3806
29b0f896 3807static int
40fb9820 3808update_imm (unsigned int j)
29b0f896 3809{
40fb9820
L		 3810 i386_operand_type overlap;
3811
c6fb90c8 3812 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
40fb9820
L		 3813 if ((overlap.bitfield.imm8
3814 || overlap.bitfield.imm8s
3815 || overlap.bitfield.imm16
3816 || overlap.bitfield.imm32
3817 || overlap.bitfield.imm32s
3818 || overlap.bitfield.imm64)
c6fb90c8
L		 3819 && !UINTS_EQUAL (overlap, imm8)
3820 && !UINTS_EQUAL (overlap, imm8s)
3821 && !UINTS_EQUAL (overlap, imm16)
3822 && !UINTS_EQUAL (overlap, imm32)
3823 && !UINTS_EQUAL (overlap, imm32s)
3824 && !UINTS_EQUAL (overlap, imm64))
29b0f896
AM		 3825 {
3826 if (i.suffix)
3827 {
40fb9820
L		 3828 i386_operand_type temp;
3829
c6fb90c8 3830 UINTS_CLEAR (temp);
40fb9820
L		 3831 if (i.suffix == BYTE_MNEM_SUFFIX)
3832 {
3833 temp.bitfield.imm8 = overlap.bitfield.imm8;
3834 temp.bitfield.imm8s = overlap.bitfield.imm8s;
3835 }
3836 else if (i.suffix == WORD_MNEM_SUFFIX)
3837 temp.bitfield.imm16 = overlap.bitfield.imm16;
3838 else if (i.suffix == QWORD_MNEM_SUFFIX)
3839 {
3840 temp.bitfield.imm64 = overlap.bitfield.imm64;
3841 temp.bitfield.imm32s = overlap.bitfield.imm32s;
3842 }
3843 else
3844 temp.bitfield.imm32 = overlap.bitfield.imm32;
3845 overlap = temp;
29b0f896 3846 }
c6fb90c8
L		 3847 else if (UINTS_EQUAL (overlap, imm16_32_32s)
3848 || UINTS_EQUAL (overlap, imm16_32)
3849 || UINTS_EQUAL (overlap, imm16_32s))
29b0f896 3850 {
c6fb90c8 3851 UINTS_CLEAR (overlap);
40fb9820
L		 3852 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3853 overlap.bitfield.imm16 = 1;
3854 else
3855 overlap.bitfield.imm32s = 1;
29b0f896 3856 }
c6fb90c8
L		 3857 if (!UINTS_EQUAL (overlap, imm8)
3858 && !UINTS_EQUAL (overlap, imm8s)
3859 && !UINTS_EQUAL (overlap, imm16)
3860 && !UINTS_EQUAL (overlap, imm32)
3861 && !UINTS_EQUAL (overlap, imm32s)
3862 && !UINTS_EQUAL (overlap, imm64))
29b0f896 3863 {
4eed87de
AM		 3864 as_bad (_("no instruction mnemonic suffix given; "
3865 "can't determine immediate size"));
29b0f896
AM		 3866 return 0;
3867 }
3868 }
40fb9820 3869 i.types[j] = overlap;
29b0f896 3870
40fb9820
L		 3871 return 1;
3872}
3873
3874static int
3875finalize_imm (void)
3876{
3877 unsigned int j;
29b0f896 3878
40fb9820
L		 3879 for (j = 0; j < 2; j++)
3880 if (update_imm (j) == 0)
3881 return 0;
3882
c6fb90c8 3883 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
40fb9820 3884 assert (operand_type_check (i.types[2], imm) == 0);
29b0f896
AM		 3885
3886 return 1;
3887}
3888
85f10a01
MM		 3889static void
3890process_drex (void)
3891{
3892 i.drex.modrm_reg = None;
3893 i.drex.modrm_regmem = None;
3894
3895 /* SSE5 4 operand instructions must have the destination the same as
3896 one of the inputs. Figure out the destination register and cache
3897 it away in the drex field, and remember which fields to use for
3898 the modrm byte. */
3899 if (i.tm.opcode_modifier.drex
3900 && i.tm.opcode_modifier.drexv
3901 && i.operands == 4)
3902 {
3903 i.tm.extension_opcode = None;
3904
3905 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
3906 if (i.types[0].bitfield.regxmm != 0
3907 && i.types[1].bitfield.regxmm != 0
3908 && i.types[2].bitfield.regxmm != 0
3909 && i.types[3].bitfield.regxmm != 0
3910 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3911 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3912 {
3913 /* Clear the arguments that are stored in drex. */
3914 UINTS_CLEAR (i.types[0]);
3915 UINTS_CLEAR (i.types[3]);
3916 i.reg_operands -= 2;
3917
3918 /* There are two different ways to encode a 4 operand
3919 instruction with all registers that uses OC1 set to
3920 0 or 1. Favor setting OC1 to 0 since this mimics the
3921 actions of other SSE5 assemblers. Use modrm encoding 2
3922 for register/register. Include the high order bit that
3923 is normally stored in the REX byte in the register
3924 field. */
3925 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
3926 i.drex.modrm_reg = 2;
3927 i.drex.modrm_regmem = 1;
3928 i.drex.reg = (i.op[3].regs->reg_num
3929 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3930 }
3931
3932 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
3933 else if (i.types[0].bitfield.regxmm != 0
3934 && i.types[1].bitfield.regxmm != 0
3935 && (i.types[2].bitfield.regxmm
3936 || operand_type_check (i.types[2], anymem))
3937 && i.types[3].bitfield.regxmm != 0
3938 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3939 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3940 {
3941 /* clear the arguments that are stored in drex */
3942 UINTS_CLEAR (i.types[0]);
3943 UINTS_CLEAR (i.types[3]);
3944 i.reg_operands -= 2;
3945
3946 /* Specify the modrm encoding for memory addressing. Include
3947 the high order bit that is normally stored in the REX byte
3948 in the register field. */
3949 i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
3950 i.drex.modrm_reg = 1;
3951 i.drex.modrm_regmem = 2;
3952 i.drex.reg = (i.op[3].regs->reg_num
3953 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3954 }
3955
3956 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
3957 else if (i.types[0].bitfield.regxmm != 0
3958 && operand_type_check (i.types[1], anymem) != 0
3959 && i.types[2].bitfield.regxmm != 0
3960 && i.types[3].bitfield.regxmm != 0
3961 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
3962 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
3963 {
3964 /* Clear the arguments that are stored in drex. */
3965 UINTS_CLEAR (i.types[0]);
3966 UINTS_CLEAR (i.types[3]);
3967 i.reg_operands -= 2;
3968
3969 /* Specify the modrm encoding for memory addressing. Include
3970 the high order bit that is normally stored in the REX byte
3971 in the register field. */
3972 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
3973 i.drex.modrm_reg = 2;
3974 i.drex.modrm_regmem = 1;
3975 i.drex.reg = (i.op[3].regs->reg_num
3976 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
3977 }
3978
3979 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
3980 else if (i.types[0].bitfield.regxmm != 0
3981 && i.types[1].bitfield.regxmm != 0
3982 && i.types[2].bitfield.regxmm != 0
3983 && i.types[3].bitfield.regxmm != 0
3984 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
3985 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
3986 {
3987 /* clear the arguments that are stored in drex */
3988 UINTS_CLEAR (i.types[2]);
3989 UINTS_CLEAR (i.types[3]);
3990 i.reg_operands -= 2;
3991
3992 /* There are two different ways to encode a 4 operand
3993 instruction with all registers that uses OC1 set to
3994 0 or 1. Favor setting OC1 to 0 since this mimics the
3995 actions of other SSE5 assemblers. Use modrm encoding
3996 2 for register/register. Include the high order bit that
3997 is normally stored in the REX byte in the register
3998 field. */
3999 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4000 i.drex.modrm_reg = 1;
4001 i.drex.modrm_regmem = 0;
4002
4003 /* Remember the register, including the upper bits */
4004 i.drex.reg = (i.op[3].regs->reg_num
4005 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4006 }
4007
4008 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4009 else if (i.types[0].bitfield.regxmm != 0
4010 && (i.types[1].bitfield.regxmm
4011 || operand_type_check (i.types[1], anymem))
4012 && i.types[2].bitfield.regxmm != 0
4013 && i.types[3].bitfield.regxmm != 0
4014 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4015 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4016 {
4017 /* Clear the arguments that are stored in drex. */
4018 UINTS_CLEAR (i.types[2]);
4019 UINTS_CLEAR (i.types[3]);
4020 i.reg_operands -= 2;
4021
4022 /* Specify the modrm encoding and remember the register
4023 including the bits normally stored in the REX byte. */
4024 i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
4025 i.drex.modrm_reg = 0;
4026 i.drex.modrm_regmem = 1;
4027 i.drex.reg = (i.op[3].regs->reg_num
4028 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4029 }
4030
4031 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4032 else if (operand_type_check (i.types[0], anymem) != 0
4033 && i.types[1].bitfield.regxmm != 0
4034 && i.types[2].bitfield.regxmm != 0
4035 && i.types[3].bitfield.regxmm != 0
4036 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4037 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4038 {
4039 /* clear the arguments that are stored in drex */
4040 UINTS_CLEAR (i.types[2]);
4041 UINTS_CLEAR (i.types[3]);
4042 i.reg_operands -= 2;
4043
4044 /* Specify the modrm encoding and remember the register
4045 including the bits normally stored in the REX byte. */
4046 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4047 i.drex.modrm_reg = 1;
4048 i.drex.modrm_regmem = 0;
4049 i.drex.reg = (i.op[3].regs->reg_num
4050 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4051 }
4052
4053 else
4054 as_bad (_("Incorrect operands for the '%s' instruction"),
4055 i.tm.name);
4056 }
4057
4058 /* SSE5 instructions with the DREX byte where the only memory operand
4059 is in the 2nd argument, and the first and last xmm register must
4060 match, and is encoded in the DREX byte. */
4061 else if (i.tm.opcode_modifier.drex
4062 && !i.tm.opcode_modifier.drexv
4063 && i.operands == 4)
4064 {
4065 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4066 if (i.types[0].bitfield.regxmm != 0
4067 && (i.types[1].bitfield.regxmm
4068 || operand_type_check(i.types[1], anymem))
4069 && i.types[2].bitfield.regxmm != 0
4070 && i.types[3].bitfield.regxmm != 0
4071 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4072 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4073 {
4074 /* clear the arguments that are stored in drex */
4075 UINTS_CLEAR (i.types[0]);
4076 UINTS_CLEAR (i.types[3]);
4077 i.reg_operands -= 2;
4078
4079 /* Specify the modrm encoding and remember the register
4080 including the high bit normally stored in the REX
4081 byte. */
4082 i.drex.modrm_reg = 2;
4083 i.drex.modrm_regmem = 1;
4084 i.drex.reg = (i.op[3].regs->reg_num
4085 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4086 }
4087
4088 else
4089 as_bad (_("Incorrect operands for the '%s' instruction"),
4090 i.tm.name);
4091 }
4092
4093 /* SSE5 3 operand instructions that the result is a register, being
4094 either operand can be a memory operand, using OC0 to note which
4095 one is the memory. */
4096 else if (i.tm.opcode_modifier.drex
4097 && i.tm.opcode_modifier.drexv
4098 && i.operands == 3)
4099 {
4100 i.tm.extension_opcode = None;
4101
4102 /* Case 1: 3 operand insn, src1 = register. */
4103 if (i.types[0].bitfield.regxmm != 0
4104 && i.types[1].bitfield.regxmm != 0
4105 && i.types[2].bitfield.regxmm != 0)
4106 {
4107 /* Clear the arguments that are stored in drex. */
4108 UINTS_CLEAR (i.types[2]);
4109 i.reg_operands--;
4110
4111 /* Specify the modrm encoding and remember the register
4112 including the high bit normally stored in the REX byte. */
4113 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4114 i.drex.modrm_reg = 1;
4115 i.drex.modrm_regmem = 0;
4116 i.drex.reg = (i.op[2].regs->reg_num
4117 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4118 }
4119
4120 /* Case 2: 3 operand insn, src1 = memory. */
4121 else if (operand_type_check (i.types[0], anymem) != 0
4122 && i.types[1].bitfield.regxmm != 0
4123 && i.types[2].bitfield.regxmm != 0)
4124 {
4125 /* Clear the arguments that are stored in drex. */
4126 UINTS_CLEAR (i.types[2]);
4127 i.reg_operands--;
4128
4129 /* Specify the modrm encoding and remember the register
4130 including the high bit normally stored in the REX
4131 byte. */
4132 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4133 i.drex.modrm_reg = 1;
4134 i.drex.modrm_regmem = 0;
4135 i.drex.reg = (i.op[2].regs->reg_num
4136 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4137 }
4138
4139 /* Case 3: 3 operand insn, src2 = memory. */
4140 else if (i.types[0].bitfield.regxmm != 0
4141 && operand_type_check (i.types[1], anymem) != 0
4142 && i.types[2].bitfield.regxmm != 0)
4143 {
4144 /* Clear the arguments that are stored in drex. */
4145 UINTS_CLEAR (i.types[2]);
4146 i.reg_operands--;
4147
4148 /* Specify the modrm encoding and remember the register
4149 including the high bit normally stored in the REX byte. */
4150 i.tm.extension_opcode = DREX_X1_XMEM_X2;
4151 i.drex.modrm_reg = 0;
4152 i.drex.modrm_regmem = 1;
4153 i.drex.reg = (i.op[2].regs->reg_num
4154 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4155 }
4156
4157 else
4158 as_bad (_("Incorrect operands for the '%s' instruction"),
4159 i.tm.name);
4160 }
4161
4162 /* SSE5 4 operand instructions that are the comparison instructions
4163 where the first operand is the immediate value of the comparison
4164 to be done. */
4165 else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
4166 {
4167 /* Case 1: 4 operand insn, src1 = reg/memory. */
4168 if (operand_type_check (i.types[0], imm) != 0
4169 && (i.types[1].bitfield.regxmm
4170 || operand_type_check (i.types[1], anymem))
4171 && i.types[2].bitfield.regxmm != 0
4172 && i.types[3].bitfield.regxmm != 0)
4173 {
4174 /* clear the arguments that are stored in drex */
4175 UINTS_CLEAR (i.types[3]);
4176 i.reg_operands--;
4177
4178 /* Specify the modrm encoding and remember the register
4179 including the high bit normally stored in the REX byte. */
4180 i.drex.modrm_reg = 2;
4181 i.drex.modrm_regmem = 1;
4182 i.drex.reg = (i.op[3].regs->reg_num
4183 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4184 }
4185
4186 /* Case 2: 3 operand insn with ImmExt that places the
4187 opcode_extension as an immediate argument. This is used for
4188 all of the varients of comparison that supplies the appropriate
4189 value as part of the instruction. */
4190 else if ((i.types[0].bitfield.regxmm
4191 || operand_type_check (i.types[0], anymem))
4192 && i.types[1].bitfield.regxmm != 0
4193 && i.types[2].bitfield.regxmm != 0
4194 && operand_type_check (i.types[3], imm) != 0)
4195 {
4196 /* clear the arguments that are stored in drex */
4197 UINTS_CLEAR (i.types[2]);
4198 i.reg_operands--;
4199
4200 /* Specify the modrm encoding and remember the register
4201 including the high bit normally stored in the REX byte. */
4202 i.drex.modrm_reg = 1;
4203 i.drex.modrm_regmem = 0;
4204 i.drex.reg = (i.op[2].regs->reg_num
4205 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4206 }
4207
4208 else
4209 as_bad (_("Incorrect operands for the '%s' instruction"),
4210 i.tm.name);
4211 }
4212
4213 else if (i.tm.opcode_modifier.drex
4214 || i.tm.opcode_modifier.drexv
4215 || i.tm.opcode_modifier.drexc)
4216 as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
4217}
4218
29b0f896 4219static int
e3bb37b5 4220process_operands (void)
29b0f896
AM		 4221{
4222 /* Default segment register this instruction will use for memory
4223 accesses. 0 means unknown. This is only for optimizing out
4224 unnecessary segment overrides. */
4225 const seg_entry *default_seg = 0;
4226
85f10a01
MM		 4227 /* Handle all of the DREX munging that SSE5 needs. */
4228 if (i.tm.opcode_modifier.drex
4229 || i.tm.opcode_modifier.drexv
4230 || i.tm.opcode_modifier.drexc)
4231 process_drex ();
4232
e2ec9d29 4233 if (i.tm.opcode_modifier.firstxmm0)
29b0f896 4234 {
9fcfb3d7
L		 4235 unsigned int j;
4236
e2ec9d29
L		 4237 /* The first operand is implicit and must be xmm0. */
4238 assert (i.reg_operands && UINTS_EQUAL (i.types[0], regxmm));
4239 if (i.op[0].regs->reg_num != 0)
4240 {
4241 if (intel_syntax)
4242 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
4243 i.tm.name, register_prefix);
4244 else
4245 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
4246 i.tm.name, register_prefix);
4247 return 0;
4248 }
9fcfb3d7
L		 4249
4250 for (j = 1; j < i.operands; j++)
4251 {
4252 i.op[j - 1] = i.op[j];
4253 i.types[j - 1] = i.types[j];
4254
4255 /* We need to adjust fields in i.tm since they are used by
4256 build_modrm_byte. */
4257 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4258 }
4259
e2ec9d29
L		 4260 i.operands--;
4261 i.reg_operands--;
e2ec9d29
L		 4262 i.tm.operands--;
4263 }
4264 else if (i.tm.opcode_modifier.regkludge)
4265 {
4266 /* The imul $imm, %reg instruction is converted into
4267 imul $imm, %reg, %reg, and the clr %reg instruction
4268 is converted into xor %reg, %reg. */
4269
4270 unsigned int first_reg_op;
4271
4272 if (operand_type_check (i.types[0], reg))
4273 first_reg_op = 0;
4274 else
4275 first_reg_op = 1;
4276 /* Pretend we saw the extra register operand. */
4277 assert (i.reg_operands == 1
4278 && i.op[first_reg_op + 1].regs == 0);
4279 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4280 i.types[first_reg_op + 1] = i.types[first_reg_op];
4281 i.operands++;
4282 i.reg_operands++;
29b0f896
AM		 4283 }
4284
40fb9820 4285 if (i.tm.opcode_modifier.shortform)
29b0f896 4286 {
40fb9820
L		 4287 if (i.types[0].bitfield.sreg2
4288 || i.types[0].bitfield.sreg3)
29b0f896 4289 {
4eed87de
AM		 4290 if (i.tm.base_opcode == POP_SEG_SHORT
4291 && i.op[0].regs->reg_num == 1)
29b0f896 4292 {
4eed87de
AM		 4293 as_bad (_("you can't `pop %%cs'"));
4294 return 0;
29b0f896 4295 }
4eed87de
AM		 4296 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4297 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 4298 i.rex |= REX_B;
4eed87de
AM		 4299 }
4300 else
4301 {
85f10a01
MM		 4302 /* The register or float register operand is in operand
4303 0 or 1. */
40fb9820
L		 4304 unsigned int op;
4305
4306 if (i.types[0].bitfield.floatreg
4307 || operand_type_check (i.types[0], reg))
4308 op = 0;
4309 else
4310 op = 1;
4eed87de
AM		 4311 /* Register goes in low 3 bits of opcode. */
4312 i.tm.base_opcode |= i.op[op].regs->reg_num;
4313 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 4314 i.rex |= REX_B;
40fb9820 4315 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 4316 {
4eed87de
AM		 4317 /* Warn about some common errors, but press on regardless.
4318 The first case can be generated by gcc (<= 2.8.1). */
4319 if (i.operands == 2)
4320 {
4321 /* Reversed arguments on faddp, fsubp, etc. */
a540244d
L		 4322 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
4323 register_prefix, i.op[1].regs->reg_name,
4324 register_prefix, i.op[0].regs->reg_name);
4eed87de
AM		 4325 }
4326 else
4327 {
4328 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 4329 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4330 register_prefix, i.op[0].regs->reg_name);
4eed87de 4331 }
29b0f896
AM		 4332 }
4333 }
4334 }
40fb9820 4335 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 4336 {
4337 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 4338 must be put into the modrm byte). Now, we make the modrm and
4339 index base bytes based on all the info we've collected. */
29b0f896
AM		 4340
4341 default_seg = build_modrm_byte ();
4342 }
8a2ed489 4343 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 4344 {
4345 default_seg = &ds;
4346 }
40fb9820 4347 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 4348 {
4349 /* For the string instructions that allow a segment override
4350 on one of their operands, the default segment is ds. */
4351 default_seg = &ds;
4352 }
4353
75178d9d
L		 4354 if (i.tm.base_opcode == 0x8d /* lea */
4355 && i.seg[0]
4356 && !quiet_warnings)
30123838 4357 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 4358
4359 /* If a segment was explicitly specified, and the specified segment
4360 is not the default, use an opcode prefix to select it. If we
4361 never figured out what the default segment is, then default_seg
4362 will be zero at this point, and the specified segment prefix will
4363 always be used. */
29b0f896
AM		 4364 if ((i.seg[0]) && (i.seg[0] != default_seg))
4365 {
4366 if (!add_prefix (i.seg[0]->seg_prefix))
4367 return 0;
4368 }
4369 return 1;
4370}
4371
4372static const seg_entry *
e3bb37b5 4373build_modrm_byte (void)
29b0f896
AM		 4374{
4375 const seg_entry *default_seg = 0;
4376
85f10a01
MM		 4377 /* SSE5 4 operand instructions are encoded in such a way that one of
4378 the inputs must match the destination register. Process_drex hides
4379 the 3rd argument in the drex field, so that by the time we get
4380 here, it looks to GAS as if this is a 2 operand instruction. */
4381 if ((i.tm.opcode_modifier.drex
4382 || i.tm.opcode_modifier.drexv
b5016f89 4383 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4384 && i.reg_operands == 2)
4385 {
4386 const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
4387 const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
4388
4389 i.rm.reg = reg->reg_num;
4390 i.rm.regmem = regmem->reg_num;
4391 i.rm.mode = 3;
4392 if ((reg->reg_flags & RegRex) != 0)
4393 i.rex |= REX_R;
4394 if ((regmem->reg_flags & RegRex) != 0)
4395 i.rex |= REX_B;
4396 }
4397
29b0f896
AM		 4398 /* i.reg_operands MUST be the number of real register operands;
4399 implicit registers do not count. */
85f10a01 4400 else if (i.reg_operands == 2)
29b0f896
AM		 4401 {
4402 unsigned int source, dest;
cab737b9
L		 4403
4404 switch (i.operands)
4405 {
4406 case 2:
4407 source = 0;
4408 break;
4409 case 3:
c81128dc
L		 4410 /* When there are 3 operands, one of them may be immediate,
4411 which may be the first or the last operand. Otherwise,
4412 the first operand must be shift count register (cl). */
4413 assert (i.imm_operands == 1
4414 || (i.imm_operands == 0
40fb9820
L		 4415 && i.types[0].bitfield.shiftcount));
4416 if (operand_type_check (i.types[0], imm)
4417 || i.types[0].bitfield.shiftcount)
4418 source = 1;
4419 else
4420 source = 0;
cab737b9
L		 4421 break;
4422 case 4:
368d64cc
L		 4423 /* When there are 4 operands, the first two must be 8bit
4424 immediate operands. The source operand will be the 3rd
4425 one. */
cab737b9 4426 assert (i.imm_operands == 2
368d64cc
L		 4427 && i.types[0].bitfield.imm8
4428 && i.types[1].bitfield.imm8);
cab737b9
L		 4429 source = 2;
4430 break;
4431 default:
4432 abort ();
4433 }
4434
29b0f896
AM		 4435 dest = source + 1;
4436
4437 i.rm.mode = 3;
4438 /* One of the register operands will be encoded in the i.tm.reg
4439 field, the other in the combined i.tm.mode and i.tm.regmem
4440 fields. If no form of this instruction supports a memory
4441 destination operand, then we assume the source operand may
4442 sometimes be a memory operand and so we need to store the
4443 destination in the i.rm.reg field. */
40fb9820
L		 4444 if (!i.tm.operand_types[dest].bitfield.regmem
4445 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 4446 {
4447 i.rm.reg = i.op[dest].regs->reg_num;
4448 i.rm.regmem = i.op[source].regs->reg_num;
4449 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4450 i.rex |= REX_R;
29b0f896 4451 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4452 i.rex |= REX_B;
29b0f896
AM		 4453 }
4454 else
4455 {
4456 i.rm.reg = i.op[source].regs->reg_num;
4457 i.rm.regmem = i.op[dest].regs->reg_num;
4458 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4459 i.rex |= REX_B;
29b0f896 4460 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4461 i.rex |= REX_R;
29b0f896 4462 }
161a04f6 4463 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 4464 {
40fb9820
L		 4465 if (!i.types[0].bitfield.control
4466 && !i.types[1].bitfield.control)
c4a530c5 4467 abort ();
161a04f6 4468 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 4469 add_prefix (LOCK_PREFIX_OPCODE);
4470 }
29b0f896
AM		 4471 }
4472 else
4473 { /* If it's not 2 reg operands... */
4474 if (i.mem_operands)
4475 {
4476 unsigned int fake_zero_displacement = 0;
99018f42 4477 unsigned int op;
4eed87de 4478
85f10a01
MM		 4479 /* This has been precalculated for SSE5 instructions
4480 that have a DREX field earlier in process_drex. */
b5016f89
L		 4481 if (i.tm.opcode_modifier.drex
4482 || i.tm.opcode_modifier.drexv
4483 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4484 op = i.drex.modrm_regmem;
4485 else
4486 {
c0209578
L		 4487 for (op = 0; op < i.operands; op++)
4488 if (operand_type_check (i.types[op], anymem))
4489 break;
4490 assert (op < i.operands);
85f10a01 4491 }
29b0f896
AM		 4492
4493 default_seg = &ds;
4494
4495 if (i.base_reg == 0)
4496 {
4497 i.rm.mode = 0;
4498 if (!i.disp_operands)
4499 fake_zero_displacement = 1;
4500 if (i.index_reg == 0)
4501 {
4502 /* Operand is just <disp> */
20f0a1fc 4503 if (flag_code == CODE_64BIT)
29b0f896
AM		 4504 {
4505 /* 64bit mode overwrites the 32bit absolute
4506 addressing by RIP relative addressing and
4507 absolute addressing is encoded by one of the
4508 redundant SIB forms. */
4509 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4510 i.sib.base = NO_BASE_REGISTER;
4511 i.sib.index = NO_INDEX_REGISTER;
fc225355 4512 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 4513 ? disp32s : disp32);
20f0a1fc 4514 }
fc225355
L		 4515 else if ((flag_code == CODE_16BIT)
4516 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 4517 {
4518 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 4519 i.types[op] = disp16;
20f0a1fc
NC		 4520 }
4521 else
4522 {
4523 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 4524 i.types[op] = disp32;
29b0f896
AM		 4525 }
4526 }
4527 else /* !i.base_reg && i.index_reg */
4528 {
db51cc60
L		 4529 if (i.index_reg->reg_num == RegEiz
4530 || i.index_reg->reg_num == RegRiz)
4531 i.sib.index = NO_INDEX_REGISTER;
4532 else
4533 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 4534 i.sib.base = NO_BASE_REGISTER;
4535 i.sib.scale = i.log2_scale_factor;
4536 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 4537 i.types[op].bitfield.disp8 = 0;
4538 i.types[op].bitfield.disp16 = 0;
4539 i.types[op].bitfield.disp64 = 0;
29b0f896 4540 if (flag_code != CODE_64BIT)
40fb9820
L		 4541 {
4542 /* Must be 32 bit */
4543 i.types[op].bitfield.disp32 = 1;
4544 i.types[op].bitfield.disp32s = 0;
4545 }
29b0f896 4546 else
40fb9820
L		 4547 {
4548 i.types[op].bitfield.disp32 = 0;
4549 i.types[op].bitfield.disp32s = 1;
4550 }
29b0f896 4551 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 4552 i.rex |= REX_X;
29b0f896
AM		 4553 }
4554 }
4555 /* RIP addressing for 64bit mode. */
9a04903e
JB		 4556 else if (i.base_reg->reg_num == RegRip ||
4557 i.base_reg->reg_num == RegEip)
29b0f896
AM		 4558 {
4559 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 4560 i.types[op].bitfield.disp8 = 0;
4561 i.types[op].bitfield.disp16 = 0;
4562 i.types[op].bitfield.disp32 = 0;
4563 i.types[op].bitfield.disp32s = 1;
4564 i.types[op].bitfield.disp64 = 0;
71903a11 4565 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 4566 if (! i.disp_operands)
4567 fake_zero_displacement = 1;
29b0f896 4568 }
40fb9820 4569 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 4570 {
4571 switch (i.base_reg->reg_num)
4572 {
4573 case 3: /* (%bx) */
4574 if (i.index_reg == 0)
4575 i.rm.regmem = 7;
4576 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
4577 i.rm.regmem = i.index_reg->reg_num - 6;
4578 break;
4579 case 5: /* (%bp) */
4580 default_seg = &ss;
4581 if (i.index_reg == 0)
4582 {
4583 i.rm.regmem = 6;
40fb9820 4584 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 4585 {
4586 /* fake (%bp) into 0(%bp) */
40fb9820 4587 i.types[op].bitfield.disp8 = 1;
252b5132 4588 fake_zero_displacement = 1;
29b0f896
AM		 4589 }
4590 }
4591 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
4592 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
4593 break;
4594 default: /* (%si) -> 4 or (%di) -> 5 */
4595 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
4596 }
4597 i.rm.mode = mode_from_disp_size (i.types[op]);
4598 }
4599 else /* i.base_reg and 32/64 bit mode */
4600 {
4601 if (flag_code == CODE_64BIT
40fb9820
L		 4602 && operand_type_check (i.types[op], disp))
4603 {
4604 i386_operand_type temp;
c6fb90c8 4605 UINTS_CLEAR (temp);
40fb9820
L		 4606 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
4607 i.types[op] = temp;
4608 if (i.prefix[ADDR_PREFIX] == 0)
4609 i.types[op].bitfield.disp32s = 1;
4610 else
4611 i.types[op].bitfield.disp32 = 1;
4612 }
20f0a1fc 4613
29b0f896
AM		 4614 i.rm.regmem = i.base_reg->reg_num;
4615 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 4616 i.rex |= REX_B;
29b0f896
AM		 4617 i.sib.base = i.base_reg->reg_num;
4618 /* x86-64 ignores REX prefix bit here to avoid decoder
4619 complications. */
4620 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
4621 {
4622 default_seg = &ss;
4623 if (i.disp_operands == 0)
4624 {
4625 fake_zero_displacement = 1;
40fb9820 4626 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 4627 }
4628 }
4629 else if (i.base_reg->reg_num == ESP_REG_NUM)
4630 {
4631 default_seg = &ss;
4632 }
4633 i.sib.scale = i.log2_scale_factor;
4634 if (i.index_reg == 0)
4635 {
4636 /* <disp>(%esp) becomes two byte modrm with no index
4637 register. We've already stored the code for esp
4638 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
4639 Any base register besides %esp will not use the
4640 extra modrm byte. */
4641 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 4642 }
4643 else
4644 {
db51cc60
L		 4645 if (i.index_reg->reg_num == RegEiz
4646 || i.index_reg->reg_num == RegRiz)
4647 i.sib.index = NO_INDEX_REGISTER;
4648 else
4649 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 4650 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4651 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 4652 i.rex |= REX_X;
29b0f896 4653 }
67a4f2b7
AO		 4654
4655 if (i.disp_operands
4656 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4657 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
4658 i.rm.mode = 0;
4659 else
4660 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 4661 }
252b5132 4662
29b0f896
AM		 4663 if (fake_zero_displacement)
4664 {
4665 /* Fakes a zero displacement assuming that i.types[op]
4666 holds the correct displacement size. */
4667 expressionS *exp;
4668
4669 assert (i.op[op].disps == 0);
4670 exp = &disp_expressions[i.disp_operands++];
4671 i.op[op].disps = exp;
4672 exp->X_op = O_constant;
4673 exp->X_add_number = 0;
4674 exp->X_add_symbol = (symbolS *) 0;
4675 exp->X_op_symbol = (symbolS *) 0;
4676 }
4677 }
252b5132 4678
29b0f896
AM		 4679 /* Fill in i.rm.reg or i.rm.regmem field with register operand
4680 (if any) based on i.tm.extension_opcode. Again, we must be
4681 careful to make sure that segment/control/debug/test/MMX
4682 registers are coded into the i.rm.reg field. */
4683 if (i.reg_operands)
4684 {
99018f42
L		 4685 unsigned int op;
4686
85f10a01
MM		 4687 /* This has been precalculated for SSE5 instructions
4688 that have a DREX field earlier in process_drex. */
b5016f89
L		 4689 if (i.tm.opcode_modifier.drex
4690 || i.tm.opcode_modifier.drexv
4691 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4692 {
4693 op = i.drex.modrm_reg;
4694 i.rm.reg = i.op[op].regs->reg_num;
4695 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4696 i.rex |= REX_R;
4697 }
4698 else
4699 {
c0209578
L		 4700 for (op = 0; op < i.operands; op++)
4701 if (i.types[op].bitfield.reg8
4702 || i.types[op].bitfield.reg16
4703 || i.types[op].bitfield.reg32
4704 || i.types[op].bitfield.reg64
4705 || i.types[op].bitfield.regmmx
4706 || i.types[op].bitfield.regxmm
4707 || i.types[op].bitfield.sreg2
4708 || i.types[op].bitfield.sreg3
4709 || i.types[op].bitfield.control
4710 || i.types[op].bitfield.debug
4711 || i.types[op].bitfield.test)
4712 break;
4713
4714 assert (op < i.operands);
99018f42 4715
85f10a01
MM		 4716 /* If there is an extension opcode to put here, the
4717 register number must be put into the regmem field. */
c0209578
L		 4718 if (i.tm.extension_opcode != None)
4719 {
4720 i.rm.regmem = i.op[op].regs->reg_num;
4721 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4722 i.rex |= REX_B;
4723 }
4724 else
4725 {
4726 i.rm.reg = i.op[op].regs->reg_num;
4727 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4728 i.rex |= REX_R;
4729 }
85f10a01 4730 }
252b5132 4731
29b0f896
AM		 4732 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
4733 must set it to 3 to indicate this is a register operand
4734 in the regmem field. */
4735 if (!i.mem_operands)
4736 i.rm.mode = 3;
4737 }
252b5132 4738
29b0f896 4739 /* Fill in i.rm.reg field with extension opcode (if any). */
85f10a01
MM		 4740 if (i.tm.extension_opcode != None
4741 && !(i.tm.opcode_modifier.drex
4742 || i.tm.opcode_modifier.drexv
4743 || i.tm.opcode_modifier.drexc))
29b0f896
AM		 4744 i.rm.reg = i.tm.extension_opcode;
4745 }
4746 return default_seg;
4747}
252b5132 4748
29b0f896 4749static void
e3bb37b5 4750output_branch (void)
29b0f896
AM		 4751{
4752 char *p;
4753 int code16;
4754 int prefix;
4755 relax_substateT subtype;
4756 symbolS *sym;
4757 offsetT off;
4758
4759 code16 = 0;
4760 if (flag_code == CODE_16BIT)
4761 code16 = CODE16;
4762
4763 prefix = 0;
4764 if (i.prefix[DATA_PREFIX] != 0)
252b5132 4765 {
29b0f896
AM		 4766 prefix = 1;
4767 i.prefixes -= 1;
4768 code16 ^= CODE16;
252b5132 4769 }
29b0f896
AM		 4770 /* Pentium4 branch hints. */
4771 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4772 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 4773 {
29b0f896
AM		 4774 prefix++;
4775 i.prefixes--;
4776 }
4777 if (i.prefix[REX_PREFIX] != 0)
4778 {
4779 prefix++;
4780 i.prefixes--;
2f66722d
AM		 4781 }
4782
29b0f896
AM		 4783 if (i.prefixes != 0 && !intel_syntax)
4784 as_warn (_("skipping prefixes on this instruction"));
4785
4786 /* It's always a symbol; End frag & setup for relax.
4787 Make sure there is enough room in this frag for the largest
4788 instruction we may generate in md_convert_frag. This is 2
4789 bytes for the opcode and room for the prefix and largest
4790 displacement. */
4791 frag_grow (prefix + 2 + 4);
4792 /* Prefix and 1 opcode byte go in fr_fix. */
4793 p = frag_more (prefix + 1);
4794 if (i.prefix[DATA_PREFIX] != 0)
4795 *p++ = DATA_PREFIX_OPCODE;
4796 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
4797 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
4798 *p++ = i.prefix[SEG_PREFIX];
4799 if (i.prefix[REX_PREFIX] != 0)
4800 *p++ = i.prefix[REX_PREFIX];
4801 *p = i.tm.base_opcode;
4802
4803 if ((unsigned char) *p == JUMP_PC_RELATIVE)
4804 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 4805 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 4806 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
4807 else
4808 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
4809 subtype |= code16;
3e73aa7c 4810
29b0f896
AM		 4811 sym = i.op[0].disps->X_add_symbol;
4812 off = i.op[0].disps->X_add_number;
3e73aa7c 4813
29b0f896
AM		 4814 if (i.op[0].disps->X_op != O_constant
4815 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 4816 {
29b0f896
AM		 4817 /* Handle complex expressions. */
4818 sym = make_expr_symbol (i.op[0].disps);
4819 off = 0;
4820 }
3e73aa7c 4821
29b0f896
AM		 4822 /* 1 possible extra opcode + 4 byte displacement go in var part.
4823 Pass reloc in fr_var. */
4824 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
4825}
3e73aa7c 4826
29b0f896 4827static void
e3bb37b5 4828output_jump (void)
29b0f896
AM		 4829{
4830 char *p;
4831 int size;
3e02c1cc 4832 fixS *fixP;
29b0f896 4833
40fb9820 4834 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 4835 {
4836 /* This is a loop or jecxz type instruction. */
4837 size = 1;
4838 if (i.prefix[ADDR_PREFIX] != 0)
4839 {
4840 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
4841 i.prefixes -= 1;
4842 }
4843 /* Pentium4 branch hints. */
4844 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4845 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
4846 {
4847 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
4848 i.prefixes--;
3e73aa7c
JH		 4849 }
4850 }
29b0f896
AM		 4851 else
4852 {
4853 int code16;
3e73aa7c 4854
29b0f896
AM		 4855 code16 = 0;
4856 if (flag_code == CODE_16BIT)
4857 code16 = CODE16;
3e73aa7c 4858
29b0f896
AM		 4859 if (i.prefix[DATA_PREFIX] != 0)
4860 {
4861 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
4862 i.prefixes -= 1;
4863 code16 ^= CODE16;
4864 }
252b5132 4865
29b0f896
AM		 4866 size = 4;
4867 if (code16)
4868 size = 2;
4869 }
9fcc94b6 4870
29b0f896
AM		 4871 if (i.prefix[REX_PREFIX] != 0)
4872 {
4873 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
4874 i.prefixes -= 1;
4875 }
252b5132 4876
29b0f896
AM		 4877 if (i.prefixes != 0 && !intel_syntax)
4878 as_warn (_("skipping prefixes on this instruction"));
e0890092 4879
29b0f896
AM		 4880 p = frag_more (1 + size);
4881 *p++ = i.tm.base_opcode;
e0890092 4882
3e02c1cc
AM		 4883 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4884 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
4885
4886 /* All jumps handled here are signed, but don't use a signed limit
4887 check for 32 and 16 bit jumps as we want to allow wrap around at
4888 4G and 64k respectively. */
4889 if (size == 1)
4890 fixP->fx_signed = 1;
29b0f896 4891}
e0890092 4892
29b0f896 4893static void
e3bb37b5 4894output_interseg_jump (void)
29b0f896
AM		 4895{
4896 char *p;
4897 int size;
4898 int prefix;
4899 int code16;
252b5132 4900
29b0f896
AM		 4901 code16 = 0;
4902 if (flag_code == CODE_16BIT)
4903 code16 = CODE16;
a217f122 4904
29b0f896
AM		 4905 prefix = 0;
4906 if (i.prefix[DATA_PREFIX] != 0)
4907 {
4908 prefix = 1;
4909 i.prefixes -= 1;
4910 code16 ^= CODE16;
4911 }
4912 if (i.prefix[REX_PREFIX] != 0)
4913 {
4914 prefix++;
4915 i.prefixes -= 1;
4916 }
252b5132 4917
29b0f896
AM		 4918 size = 4;
4919 if (code16)
4920 size = 2;
252b5132 4921
29b0f896
AM		 4922 if (i.prefixes != 0 && !intel_syntax)
4923 as_warn (_("skipping prefixes on this instruction"));
252b5132 4924
29b0f896
AM		 4925 /* 1 opcode; 2 segment; offset */
4926 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 4927
29b0f896
AM		 4928 if (i.prefix[DATA_PREFIX] != 0)
4929 *p++ = DATA_PREFIX_OPCODE;
252b5132 4930
29b0f896
AM		 4931 if (i.prefix[REX_PREFIX] != 0)
4932 *p++ = i.prefix[REX_PREFIX];
252b5132 4933
29b0f896
AM		 4934 *p++ = i.tm.base_opcode;
4935 if (i.op[1].imms->X_op == O_constant)
4936 {
4937 offsetT n = i.op[1].imms->X_add_number;
252b5132 4938
29b0f896
AM		 4939 if (size == 2
4940 && !fits_in_unsigned_word (n)
4941 && !fits_in_signed_word (n))
4942 {
4943 as_bad (_("16-bit jump out of range"));
4944 return;
4945 }
4946 md_number_to_chars (p, n, size);
4947 }
4948 else
4949 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4950 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
4951 if (i.op[0].imms->X_op != O_constant)
4952 as_bad (_("can't handle non absolute segment in `%s'"),
4953 i.tm.name);
4954 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
4955}
a217f122 4956
29b0f896 4957static void
e3bb37b5 4958output_insn (void)
29b0f896 4959{
2bbd9c25
JJ		 4960 fragS *insn_start_frag;
4961 offsetT insn_start_off;
4962
29b0f896
AM		 4963 /* Tie dwarf2 debug info to the address at the start of the insn.
4964 We can't do this after the insn has been output as the current
4965 frag may have been closed off. eg. by frag_var. */
4966 dwarf2_emit_insn (0);
4967
2bbd9c25
JJ		 4968 insn_start_frag = frag_now;
4969 insn_start_off = frag_now_fix ();
4970
29b0f896 4971 /* Output jumps. */
40fb9820 4972 if (i.tm.opcode_modifier.jump)
29b0f896 4973 output_branch ();
40fb9820
L		 4974 else if (i.tm.opcode_modifier.jumpbyte
4975 || i.tm.opcode_modifier.jumpdword)
29b0f896 4976 output_jump ();
40fb9820 4977 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 4978 output_interseg_jump ();
4979 else
4980 {
4981 /* Output normal instructions here. */
4982 char *p;
4983 unsigned char *q;
331d2d0d 4984 unsigned int prefix;
4dffcebc
L		 4985
4986 switch (i.tm.opcode_length)
bc4bd9ab 4987 {
4dffcebc 4988 case 3:
331d2d0d
L		 4989 if (i.tm.base_opcode & 0xff000000)
4990 {
4991 prefix = (i.tm.base_opcode >> 24) & 0xff;
4992 goto check_prefix;
4993 }
4dffcebc
L		 4994 break;
4995 case 2:
4996 if ((i.tm.base_opcode & 0xff0000) != 0)
bc4bd9ab 4997 {
4dffcebc
L		 4998 prefix = (i.tm.base_opcode >> 16) & 0xff;
4999 if (i.tm.cpu_flags.bitfield.cpupadlock)
5000 {
5001check_prefix:
5002 if (prefix != REPE_PREFIX_OPCODE
5003 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
5004 add_prefix (prefix);
5005 }
5006 else
bc4bd9ab
MK		 5007 add_prefix (prefix);
5008 }
4dffcebc
L		 5009 break;
5010 case 1:
5011 break;
5012 default:
5013 abort ();
0f10071e 5014 }
252b5132 5015
29b0f896
AM		 5016 /* The prefix bytes. */
5017 for (q = i.prefix;
5018 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
5019 q++)
5020 {
5021 if (*q)
5022 {
5023 p = frag_more (1);
5024 md_number_to_chars (p, (valueT) *q, 1);
5025 }
5026 }
252b5132 5027
29b0f896 5028 /* Now the opcode; be careful about word order here! */
4dffcebc 5029 if (i.tm.opcode_length == 1)
29b0f896
AM		 5030 {
5031 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5032 }
5033 else
5034 {
4dffcebc 5035 switch (i.tm.opcode_length)
331d2d0d 5036 {
4dffcebc 5037 case 3:
331d2d0d
L		 5038 p = frag_more (3);
5039 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 5040 break;
5041 case 2:
5042 p = frag_more (2);
5043 break;
5044 default:
5045 abort ();
5046 break;
331d2d0d 5047 }
0f10071e 5048
29b0f896
AM		 5049 /* Put out high byte first: can't use md_number_to_chars! */
5050 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5051 *p = i.tm.base_opcode & 0xff;
85f10a01
MM		 5052
5053 /* On SSE5, encode the OC1 bit in the DREX field if this
5054 encoding has multiple formats. */
5055 if (i.tm.opcode_modifier.drex
5056 && i.tm.opcode_modifier.drexv
5057 && DREX_OC1 (i.tm.extension_opcode))
5058 *p |= DREX_OC1_MASK;
29b0f896 5059 }
3e73aa7c 5060
29b0f896 5061 /* Now the modrm byte and sib byte (if present). */
40fb9820 5062 if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5063 {
5064 p = frag_more (1);
5065 md_number_to_chars (p,
5066 (valueT) (i.rm.regmem << 0
5067 | i.rm.reg << 3
5068 | i.rm.mode << 6),
5069 1);
5070 /* If i.rm.regmem == ESP (4)
5071 && i.rm.mode != (Register mode)
5072 && not 16 bit
5073 ==> need second modrm byte. */
5074 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5075 && i.rm.mode != 3
40fb9820 5076 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
29b0f896
AM		 5077 {
5078 p = frag_more (1);
5079 md_number_to_chars (p,
5080 (valueT) (i.sib.base << 0
5081 | i.sib.index << 3
5082 | i.sib.scale << 6),
5083 1);
5084 }
5085 }
3e73aa7c 5086
85f10a01
MM		 5087 /* Write the DREX byte if needed. */
5088 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
5089 {
5090 p = frag_more (1);
5091 *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
5092
5093 /* Encode the OC0 bit if this encoding has multiple
5094 formats. */
5095 if ((i.tm.opcode_modifier.drex
5096 || i.tm.opcode_modifier.drexv)
5097 && DREX_OC0 (i.tm.extension_opcode))
5098 *p |= DREX_OC0_MASK;
5099 }
5100
29b0f896 5101 if (i.disp_operands)
2bbd9c25 5102 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 5103
29b0f896 5104 if (i.imm_operands)
2bbd9c25 5105 output_imm (insn_start_frag, insn_start_off);
29b0f896 5106 }
252b5132 5107
29b0f896
AM		 5108#ifdef DEBUG386
5109 if (flag_debug)
5110 {
7b81dfbb 5111 pi ("" /*line*/, &i);
29b0f896
AM		 5112 }
5113#endif /* DEBUG386 */
5114}
252b5132 5115
e205caa7
L		 5116/* Return the size of the displacement operand N. */
5117
5118static int
5119disp_size (unsigned int n)
5120{
5121 int size = 4;
40fb9820
L		 5122 if (i.types[n].bitfield.disp64)
5123 size = 8;
5124 else if (i.types[n].bitfield.disp8)
5125 size = 1;
5126 else if (i.types[n].bitfield.disp16)
5127 size = 2;
e205caa7
L		 5128 return size;
5129}
5130
5131/* Return the size of the immediate operand N. */
5132
5133static int
5134imm_size (unsigned int n)
5135{
5136 int size = 4;
40fb9820
L		 5137 if (i.types[n].bitfield.imm64)
5138 size = 8;
5139 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5140 size = 1;
5141 else if (i.types[n].bitfield.imm16)
5142 size = 2;
e205caa7
L		 5143 return size;
5144}
5145
29b0f896 5146static void
64e74474 5147output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5148{
5149 char *p;
5150 unsigned int n;
252b5132 5151
29b0f896
AM		 5152 for (n = 0; n < i.operands; n++)
5153 {
40fb9820 5154 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 5155 {
5156 if (i.op[n].disps->X_op == O_constant)
5157 {
e205caa7 5158 int size = disp_size (n);
29b0f896 5159 offsetT val;
252b5132 5160
29b0f896
AM		 5161 val = offset_in_range (i.op[n].disps->X_add_number,
5162 size);
5163 p = frag_more (size);
5164 md_number_to_chars (p, val, size);
5165 }
5166 else
5167 {
f86103b7 5168 enum bfd_reloc_code_real reloc_type;
e205caa7 5169 int size = disp_size (n);
40fb9820 5170 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 5171 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5172
e205caa7 5173 /* We can't have 8 bit displacement here. */
40fb9820 5174 assert (!i.types[n].bitfield.disp8);
e205caa7 5175
29b0f896
AM		 5176 /* The PC relative address is computed relative
5177 to the instruction boundary, so in case immediate
5178 fields follows, we need to adjust the value. */
5179 if (pcrel && i.imm_operands)
5180 {
29b0f896 5181 unsigned int n1;
e205caa7 5182 int sz = 0;
252b5132 5183
29b0f896 5184 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 5185 if (operand_type_check (i.types[n1], imm))
252b5132 5186 {
e205caa7
L		 5187 /* Only one immediate is allowed for PC
5188 relative address. */
5189 assert (sz == 0);
5190 sz = imm_size (n1);
5191 i.op[n].disps->X_add_number -= sz;
252b5132 5192 }
29b0f896 5193 /* We should find the immediate. */
e205caa7 5194 assert (sz != 0);
29b0f896 5195 }
520dc8e8 5196
29b0f896 5197 p = frag_more (size);
2bbd9c25 5198 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 5199 if (GOT_symbol
2bbd9c25 5200 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 5201 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5202 || reloc_type == BFD_RELOC_X86_64_32S
5203 || (reloc_type == BFD_RELOC_64
5204 && object_64bit))
d6ab8113
JB		 5205 && (i.op[n].disps->X_op == O_symbol
5206 || (i.op[n].disps->X_op == O_add
5207 && ((symbol_get_value_expression
5208 (i.op[n].disps->X_op_symbol)->X_op)
5209 == O_subtract))))
5210 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 5211 {
5212 offsetT add;
5213
5214 if (insn_start_frag == frag_now)
5215 add = (p - frag_now->fr_literal) - insn_start_off;
5216 else
5217 {
5218 fragS *fr;
5219
5220 add = insn_start_frag->fr_fix - insn_start_off;
5221 for (fr = insn_start_frag->fr_next;
5222 fr && fr != frag_now; fr = fr->fr_next)
5223 add += fr->fr_fix;
5224 add += p - frag_now->fr_literal;
5225 }
5226
4fa24527 5227 if (!object_64bit)
7b81dfbb
AJ		 5228 {
5229 reloc_type = BFD_RELOC_386_GOTPC;
5230 i.op[n].imms->X_add_number += add;
5231 }
5232 else if (reloc_type == BFD_RELOC_64)
5233 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 5234 else
7b81dfbb
AJ		 5235 /* Don't do the adjustment for x86-64, as there
5236 the pcrel addressing is relative to the _next_
5237 insn, and that is taken care of in other code. */
d6ab8113 5238 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 5239 }
062cd5e7 5240 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 5241 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 5242 }
5243 }
5244 }
5245}
252b5132 5246
29b0f896 5247static void
64e74474 5248output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5249{
5250 char *p;
5251 unsigned int n;
252b5132 5252
29b0f896
AM		 5253 for (n = 0; n < i.operands; n++)
5254 {
40fb9820 5255 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 5256 {
5257 if (i.op[n].imms->X_op == O_constant)
5258 {
e205caa7 5259 int size = imm_size (n);
29b0f896 5260 offsetT val;
b4cac588 5261
29b0f896
AM		 5262 val = offset_in_range (i.op[n].imms->X_add_number,
5263 size);
5264 p = frag_more (size);
5265 md_number_to_chars (p, val, size);
5266 }
5267 else
5268 {
5269 /* Not absolute_section.
5270 Need a 32-bit fixup (don't support 8bit
5271 non-absolute imms). Try to support other
5272 sizes ... */
f86103b7 5273 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 5274 int size = imm_size (n);
5275 int sign;
29b0f896 5276
40fb9820 5277 if (i.types[n].bitfield.imm32s
a7d61044 5278 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 5279 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 5280 sign = 1;
e205caa7
L		 5281 else
5282 sign = 0;
520dc8e8 5283
29b0f896
AM		 5284 p = frag_more (size);
5285 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 5286
2bbd9c25
JJ		 5287 /* This is tough to explain. We end up with this one if we
5288 * have operands that look like
5289 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5290 * obtain the absolute address of the GOT, and it is strongly
5291 * preferable from a performance point of view to avoid using
5292 * a runtime relocation for this. The actual sequence of
5293 * instructions often look something like:
5294 *
5295 * call .L66
5296 * .L66:
5297 * popl %ebx
5298 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5299 *
5300 * The call and pop essentially return the absolute address
5301 * of the label .L66 and store it in %ebx. The linker itself
5302 * will ultimately change the first operand of the addl so
5303 * that %ebx points to the GOT, but to keep things simple, the
5304 * .o file must have this operand set so that it generates not
5305 * the absolute address of .L66, but the absolute address of
5306 * itself. This allows the linker itself simply treat a GOTPC
5307 * relocation as asking for a pcrel offset to the GOT to be
5308 * added in, and the addend of the relocation is stored in the
5309 * operand field for the instruction itself.
5310 *
5311 * Our job here is to fix the operand so that it would add
5312 * the correct offset so that %ebx would point to itself. The
5313 * thing that is tricky is that .-.L66 will point to the
5314 * beginning of the instruction, so we need to further modify
5315 * the operand so that it will point to itself. There are
5316 * other cases where you have something like:
5317 *
5318 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5319 *
5320 * and here no correction would be required. Internally in
5321 * the assembler we treat operands of this form as not being
5322 * pcrel since the '.' is explicitly mentioned, and I wonder
5323 * whether it would simplify matters to do it this way. Who
5324 * knows. In earlier versions of the PIC patches, the
5325 * pcrel_adjust field was used to store the correction, but
5326 * since the expression is not pcrel, I felt it would be
5327 * confusing to do it this way. */
5328
d6ab8113 5329 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5330 || reloc_type == BFD_RELOC_X86_64_32S
5331 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 5332 && GOT_symbol
5333 && GOT_symbol == i.op[n].imms->X_add_symbol
5334 && (i.op[n].imms->X_op == O_symbol
5335 || (i.op[n].imms->X_op == O_add
5336 && ((symbol_get_value_expression
5337 (i.op[n].imms->X_op_symbol)->X_op)
5338 == O_subtract))))
5339 {
2bbd9c25
JJ		 5340 offsetT add;
5341
5342 if (insn_start_frag == frag_now)
5343 add = (p - frag_now->fr_literal) - insn_start_off;
5344 else
5345 {
5346 fragS *fr;
5347
5348 add = insn_start_frag->fr_fix - insn_start_off;
5349 for (fr = insn_start_frag->fr_next;
5350 fr && fr != frag_now; fr = fr->fr_next)
5351 add += fr->fr_fix;
5352 add += p - frag_now->fr_literal;
5353 }
5354
4fa24527 5355 if (!object_64bit)
d6ab8113 5356 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 5357 else if (size == 4)
d6ab8113 5358 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 5359 else if (size == 8)
5360 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 5361 i.op[n].imms->X_add_number += add;
29b0f896 5362 }
29b0f896
AM		 5363 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5364 i.op[n].imms, 0, reloc_type);
5365 }
5366 }
5367 }
252b5132
RH		 5368}
5369\f
d182319b
JB		 5370/* x86_cons_fix_new is called via the expression parsing code when a
5371 reloc is needed. We use this hook to get the correct .got reloc. */
5372static enum bfd_reloc_code_real got_reloc = NO_RELOC;
5373static int cons_sign = -1;
5374
5375void
e3bb37b5 5376x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 5377 expressionS *exp)
d182319b
JB		 5378{
5379 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
5380
5381 got_reloc = NO_RELOC;
5382
5383#ifdef TE_PE
5384 if (exp->X_op == O_secrel)
5385 {
5386 exp->X_op = O_symbol;
5387 r = BFD_RELOC_32_SECREL;
5388 }
5389#endif
5390
5391 fix_new_exp (frag, off, len, exp, 0, r);
5392}
5393
718ddfc0
JB		 5394#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5395# define lex_got(reloc, adjust, types) NULL
5396#else
f3c180ae
AM		 5397/* Parse operands of the form
5398 <symbol>@GOTOFF+<nnn>
5399 and similar .plt or .got references.
5400
5401 If we find one, set up the correct relocation in RELOC and copy the
5402 input string, minus the `@GOTOFF' into a malloc'd buffer for
5403 parsing by the calling routine. Return this buffer, and if ADJUST
5404 is non-null set it to the length of the string we removed from the
5405 input line. Otherwise return NULL. */
5406static char *
3956db08 5407lex_got (enum bfd_reloc_code_real *reloc,
64e74474 5408 int *adjust,
40fb9820 5409 i386_operand_type *types)
f3c180ae 5410{
7b81dfbb
AJ		 5411 /* Some of the relocations depend on the size of what field is to
5412 be relocated. But in our callers i386_immediate and i386_displacement
5413 we don't yet know the operand size (this will be set by insn
5414 matching). Hence we record the word32 relocation here,
5415 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 5416 static const struct {
5417 const char *str;
4fa24527 5418 const enum bfd_reloc_code_real rel[2];
40fb9820 5419 const i386_operand_type types64;
f3c180ae 5420 } gotrel[] = {
4eed87de
AM		 5421 { "PLTOFF", { 0,
5422 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 5423 OPERAND_TYPE_IMM64 },
4eed87de
AM		 5424 { "PLT", { BFD_RELOC_386_PLT32,
5425 BFD_RELOC_X86_64_PLT32 },
40fb9820 5426 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5427 { "GOTPLT", { 0,
5428 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 5429 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 5430 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
5431 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 5432 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 5433 { "GOTPCREL", { 0,
5434 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 5435 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5436 { "TLSGD", { BFD_RELOC_386_TLS_GD,
5437 BFD_RELOC_X86_64_TLSGD },
40fb9820 5438 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5439 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
5440 0 },
40fb9820 5441 OPERAND_TYPE_NONE },
4eed87de
AM		 5442 { "TLSLD", { 0,
5443 BFD_RELOC_X86_64_TLSLD },
40fb9820 5444 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5445 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
5446 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 5447 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5448 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
5449 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 5450 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 5451 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
5452 0 },
40fb9820 5453 OPERAND_TYPE_NONE },
4eed87de
AM		 5454 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
5455 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820
L		 5456
5457 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 5458 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
5459 0 },
40fb9820 5460 OPERAND_TYPE_NONE },
4eed87de
AM		 5461 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
5462 0 },
40fb9820 5463 OPERAND_TYPE_NONE },
4eed87de
AM		 5464 { "GOT", { BFD_RELOC_386_GOT32,
5465 BFD_RELOC_X86_64_GOT32 },
40fb9820 5466 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM		 5467 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
5468 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 5469 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5470 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
5471 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 5472 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 5473 };
5474 char *cp;
5475 unsigned int j;
5476
718ddfc0
JB		 5477 if (!IS_ELF)
5478 return NULL;
5479
f3c180ae 5480 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 5481 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 5482 return NULL;
5483
5484 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
5485 {
5486 int len;
5487
5488 len = strlen (gotrel[j].str);
28f81592 5489 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 5490 {
4fa24527 5491 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 5492 {
28f81592
AM		 5493 int first, second;
5494 char *tmpbuf, *past_reloc;
f3c180ae 5495
4fa24527 5496 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 5497 if (adjust)
5498 *adjust = len;
f3c180ae 5499
3956db08
JB		 5500 if (types)
5501 {
5502 if (flag_code != CODE_64BIT)
40fb9820
L		 5503 {
5504 types->bitfield.imm32 = 1;
5505 types->bitfield.disp32 = 1;
5506 }
3956db08
JB		 5507 else
5508 *types = gotrel[j].types64;
5509 }
5510
f3c180ae
AM		 5511 if (GOT_symbol == NULL)
5512 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
5513
28f81592 5514 /* The length of the first part of our input line. */
f3c180ae 5515 first = cp - input_line_pointer;
28f81592
AM		 5516
5517 /* The second part goes from after the reloc token until
67c11a9b 5518 (and including) an end_of_line char or comma. */
28f81592 5519 past_reloc = cp + 1 + len;
67c11a9b
AM		 5520 cp = past_reloc;
5521 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
5522 ++cp;
5523 second = cp + 1 - past_reloc;
28f81592
AM		 5524
5525 /* Allocate and copy string. The trailing NUL shouldn't
5526 be necessary, but be safe. */
5527 tmpbuf = xmalloc (first + second + 2);
f3c180ae 5528 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 5529 if (second != 0 && *past_reloc != ' ')
5530 /* Replace the relocation token with ' ', so that
5531 errors like foo@GOTOFF1 will be detected. */
5532 tmpbuf[first++] = ' ';
5533 memcpy (tmpbuf + first, past_reloc, second);
5534 tmpbuf[first + second] = '\0';
f3c180ae
AM		 5535 return tmpbuf;
5536 }
5537
4fa24527
JB		 5538 as_bad (_("@%s reloc is not supported with %d-bit output format"),
5539 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 5540 return NULL;
5541 }
5542 }
5543
5544 /* Might be a symbol version string. Don't as_bad here. */
5545 return NULL;
5546}
5547
f3c180ae 5548void
e3bb37b5 5549x86_cons (expressionS *exp, int size)
f3c180ae 5550{
4fa24527 5551 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 5552 {
5553 /* Handle @GOTOFF and the like in an expression. */
5554 char *save;
5555 char *gotfree_input_line;
5556 int adjust;
5557
5558 save = input_line_pointer;
3956db08 5559 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 5560 if (gotfree_input_line)
5561 input_line_pointer = gotfree_input_line;
5562
5563 expression (exp);
5564
5565 if (gotfree_input_line)
5566 {
5567 /* expression () has merrily parsed up to the end of line,
5568 or a comma - in the wrong buffer. Transfer how far
5569 input_line_pointer has moved to the right buffer. */
5570 input_line_pointer = (save
5571 + (input_line_pointer - gotfree_input_line)
5572 + adjust);
5573 free (gotfree_input_line);
3992d3b7
AM		 5574 if (exp->X_op == O_constant
5575 || exp->X_op == O_absent
5576 || exp->X_op == O_illegal
5577 || exp->X_op == O_register
5578 || exp->X_op == O_big)
5579 {
5580 char c = *input_line_pointer;
5581 *input_line_pointer = 0;
5582 as_bad (_("missing or invalid expression `%s'"), save);
5583 *input_line_pointer = c;
5584 }
f3c180ae
AM		 5585 }
5586 }
5587 else
5588 expression (exp);
5589}
5590#endif
5591
d182319b 5592static void signed_cons (int size)
6482c264 5593{
d182319b
JB		 5594 if (flag_code == CODE_64BIT)
5595 cons_sign = 1;
5596 cons (size);
5597 cons_sign = -1;
6482c264
NC		 5598}
5599
d182319b 5600#ifdef TE_PE
6482c264
NC		 5601static void
5602pe_directive_secrel (dummy)
5603 int dummy ATTRIBUTE_UNUSED;
5604{
5605 expressionS exp;
5606
5607 do
5608 {
5609 expression (&exp);
5610 if (exp.X_op == O_symbol)
5611 exp.X_op = O_secrel;
5612
5613 emit_expr (&exp, 4);
5614 }
5615 while (*input_line_pointer++ == ',');
5616
5617 input_line_pointer--;
5618 demand_empty_rest_of_line ();
5619}
6482c264
NC		 5620#endif
5621
252b5132 5622static int
70e41ade 5623i386_immediate (char *imm_start)
252b5132
RH		 5624{
5625 char *save_input_line_pointer;
f3c180ae 5626 char *gotfree_input_line;
252b5132 5627 segT exp_seg = 0;
47926f60 5628 expressionS *exp;
40fb9820
L		 5629 i386_operand_type types;
5630
c6fb90c8 5631 UINTS_SET (types, ~0);
252b5132
RH		 5632
5633 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
5634 {
31b2323c
L		 5635 as_bad (_("at most %d immediate operands are allowed"),
5636 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 5637 return 0;
5638 }
5639
5640 exp = &im_expressions[i.imm_operands++];
520dc8e8 5641 i.op[this_operand].imms = exp;
252b5132
RH		 5642
5643 if (is_space_char (*imm_start))
5644 ++imm_start;
5645
5646 save_input_line_pointer = input_line_pointer;
5647 input_line_pointer = imm_start;
5648
3956db08 5649 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 5650 if (gotfree_input_line)
5651 input_line_pointer = gotfree_input_line;
252b5132
RH		 5652
5653 exp_seg = expression (exp);
5654
83183c0c 5655 SKIP_WHITESPACE ();
252b5132 5656 if (*input_line_pointer)
f3c180ae 5657 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 5658
5659 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 5660 if (gotfree_input_line)
5661 free (gotfree_input_line);
252b5132 5662
3992d3b7
AM		 5663 if (exp->X_op == O_absent
5664 || exp->X_op == O_illegal
5665 || exp->X_op == O_big
5666 || (gotfree_input_line
5667 && (exp->X_op == O_constant
5668 || exp->X_op == O_register)))
252b5132 5669 {
3992d3b7 5670 as_bad (_("missing or invalid immediate expression `%s'"),
24eab124 5671 imm_start);
3992d3b7 5672 return 0;
252b5132 5673 }
3e73aa7c 5674 else if (exp->X_op == O_constant)
252b5132 5675 {
47926f60 5676 /* Size it properly later. */
40fb9820 5677 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 5678 /* If BFD64, sign extend val. */
4eed87de
AM		 5679 if (!use_rela_relocations
5680 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
5681 exp->X_add_number
5682 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 5683 }
4c63da97 5684#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 5685 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 5686 && exp_seg != absolute_section
47926f60 5687 && exp_seg != text_section
24eab124
AM		 5688 && exp_seg != data_section
5689 && exp_seg != bss_section
5690 && exp_seg != undefined_section
f86103b7 5691 && !bfd_is_com_section (exp_seg))
252b5132 5692 {
d0b47220 5693 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 5694 return 0;
5695 }
5696#endif
bb8f5920
L		 5697 else if (!intel_syntax && exp->X_op == O_register)
5698 {
5699 as_bad (_("illegal immediate register operand %s"), imm_start);
5700 return 0;
5701 }
252b5132
RH		 5702 else
5703 {
5704 /* This is an address. The size of the address will be
24eab124 5705 determined later, depending on destination register,
3e73aa7c 5706 suffix, or the default for the section. */
40fb9820
L		 5707 i.types[this_operand].bitfield.imm8 = 1;
5708 i.types[this_operand].bitfield.imm16 = 1;
5709 i.types[this_operand].bitfield.imm32 = 1;
5710 i.types[this_operand].bitfield.imm32s = 1;
5711 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 5712 i.types[this_operand] = operand_type_and (i.types[this_operand],
5713 types);
252b5132
RH		 5714 }
5715
5716 return 1;
5717}
5718
551c1ca1 5719static char *
e3bb37b5 5720i386_scale (char *scale)
252b5132 5721{
551c1ca1
AM		 5722 offsetT val;
5723 char *save = input_line_pointer;
252b5132 5724
551c1ca1
AM		 5725 input_line_pointer = scale;
5726 val = get_absolute_expression ();
5727
5728 switch (val)
252b5132 5729 {
551c1ca1 5730 case 1:
252b5132
RH		 5731 i.log2_scale_factor = 0;
5732 break;
551c1ca1 5733 case 2:
252b5132
RH		 5734 i.log2_scale_factor = 1;
5735 break;
551c1ca1 5736 case 4:
252b5132
RH		 5737 i.log2_scale_factor = 2;
5738 break;
551c1ca1 5739 case 8:
252b5132
RH		 5740 i.log2_scale_factor = 3;
5741 break;
5742 default:
a724f0f4
JB		 5743 {
5744 char sep = *input_line_pointer;
5745
5746 *input_line_pointer = '\0';
5747 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5748 scale);
5749 *input_line_pointer = sep;
5750 input_line_pointer = save;
5751 return NULL;
5752 }
252b5132 5753 }
29b0f896 5754 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 5755 {
5756 as_warn (_("scale factor of %d without an index register"),
24eab124 5757 1 << i.log2_scale_factor);
252b5132 5758 i.log2_scale_factor = 0;
252b5132 5759 }
551c1ca1
AM		 5760 scale = input_line_pointer;
5761 input_line_pointer = save;
5762 return scale;
252b5132
RH		 5763}
5764
252b5132 5765static int
e3bb37b5 5766i386_displacement (char *disp_start, char *disp_end)
252b5132 5767{
29b0f896 5768 expressionS *exp;
252b5132
RH		 5769 segT exp_seg = 0;
5770 char *save_input_line_pointer;
f3c180ae 5771 char *gotfree_input_line;
40fb9820
L		 5772 int override;
5773 i386_operand_type bigdisp, types = anydisp;
3992d3b7 5774 int ret;
252b5132 5775
31b2323c
L		 5776 if (i.disp_operands == MAX_MEMORY_OPERANDS)
5777 {
5778 as_bad (_("at most %d displacement operands are allowed"),
5779 MAX_MEMORY_OPERANDS);
5780 return 0;
5781 }
5782
c6fb90c8 5783 UINTS_CLEAR (bigdisp);
40fb9820
L		 5784 if ((i.types[this_operand].bitfield.jumpabsolute)
5785 || (!current_templates->start->opcode_modifier.jump
5786 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 5787 {
40fb9820 5788 bigdisp.bitfield.disp32 = 1;
e05278af 5789 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 5790 if (flag_code == CODE_64BIT)
5791 {
5792 if (!override)
5793 {
5794 bigdisp.bitfield.disp32s = 1;
5795 bigdisp.bitfield.disp64 = 1;
5796 }
5797 }
5798 else if ((flag_code == CODE_16BIT) ^ override)
5799 {
5800 bigdisp.bitfield.disp32 = 0;
5801 bigdisp.bitfield.disp16 = 1;
5802 }
e05278af
JB		 5803 }
5804 else
5805 {
5806 /* For PC-relative branches, the width of the displacement
5807 is dependent upon data size, not address size. */
e05278af 5808 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 5809 if (flag_code == CODE_64BIT)
5810 {
5811 if (override || i.suffix == WORD_MNEM_SUFFIX)
5812 bigdisp.bitfield.disp16 = 1;
5813 else
5814 {
5815 bigdisp.bitfield.disp32 = 1;
5816 bigdisp.bitfield.disp32s = 1;
5817 }
5818 }
5819 else
e05278af
JB		 5820 {
5821 if (!override)
5822 override = (i.suffix == (flag_code != CODE_16BIT
5823 ? WORD_MNEM_SUFFIX
5824 : LONG_MNEM_SUFFIX));
40fb9820
L		 5825 bigdisp.bitfield.disp32 = 1;
5826 if ((flag_code == CODE_16BIT) ^ override)
5827 {
5828 bigdisp.bitfield.disp32 = 0;
5829 bigdisp.bitfield.disp16 = 1;
5830 }
e05278af 5831 }
e05278af 5832 }
c6fb90c8
L		 5833 i.types[this_operand] = operand_type_or (i.types[this_operand],
5834 bigdisp);
252b5132
RH		 5835
5836 exp = &disp_expressions[i.disp_operands];
520dc8e8 5837 i.op[this_operand].disps = exp;
252b5132
RH		 5838 i.disp_operands++;
5839 save_input_line_pointer = input_line_pointer;
5840 input_line_pointer = disp_start;
5841 END_STRING_AND_SAVE (disp_end);
5842
5843#ifndef GCC_ASM_O_HACK
5844#define GCC_ASM_O_HACK 0
5845#endif
5846#if GCC_ASM_O_HACK
5847 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 5848 if (i.types[this_operand].bitfield.baseIndex
24eab124 5849 && displacement_string_end[-1] == '+')
252b5132
RH		 5850 {
5851 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 5852 constraint within gcc asm statements.
5853 For instance:
5854
5855 #define _set_tssldt_desc(n,addr,limit,type) \
5856 __asm__ __volatile__ ( \
5857 "movw %w2,%0\n\t" \
5858 "movw %w1,2+%0\n\t" \
5859 "rorl $16,%1\n\t" \
5860 "movb %b1,4+%0\n\t" \
5861 "movb %4,5+%0\n\t" \
5862 "movb $0,6+%0\n\t" \
5863 "movb %h1,7+%0\n\t" \
5864 "rorl $16,%1" \
5865 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
5866
5867 This works great except that the output assembler ends
5868 up looking a bit weird if it turns out that there is
5869 no offset. You end up producing code that looks like:
5870
5871 #APP
5872 movw $235,(%eax)
5873 movw %dx,2+(%eax)
5874 rorl $16,%edx
5875 movb %dl,4+(%eax)
5876 movb $137,5+(%eax)
5877 movb $0,6+(%eax)
5878 movb %dh,7+(%eax)
5879 rorl $16,%edx
5880 #NO_APP
5881
47926f60 5882 So here we provide the missing zero. */
24eab124
AM		 5883
5884 *displacement_string_end = '0';
252b5132
RH		 5885 }
5886#endif
3956db08 5887 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 5888 if (gotfree_input_line)
5889 input_line_pointer = gotfree_input_line;
252b5132 5890
24eab124 5891 exp_seg = expression (exp);
252b5132 5892
636c26b0
AM		 5893 SKIP_WHITESPACE ();
5894 if (*input_line_pointer)
5895 as_bad (_("junk `%s' after expression"), input_line_pointer);
5896#if GCC_ASM_O_HACK
5897 RESTORE_END_STRING (disp_end + 1);
5898#endif
636c26b0 5899 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 5900 if (gotfree_input_line)
5901 free (gotfree_input_line);
3992d3b7 5902 ret = 1;
636c26b0 5903
24eab124
AM		 5904 /* We do this to make sure that the section symbol is in
5905 the symbol table. We will ultimately change the relocation
47926f60 5906 to be relative to the beginning of the section. */
1ae12ab7 5907 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 5908 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
5909 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 5910 {
636c26b0 5911 if (exp->X_op != O_symbol)
3992d3b7 5912 goto inv_disp;
636c26b0 5913
e5cb08ac 5914 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 5915 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
5916 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 5917 exp->X_op = O_subtract;
5918 exp->X_op_symbol = GOT_symbol;
1ae12ab7 5919 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 5920 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 5921 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
5922 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 5923 else
29b0f896 5924 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 5925 }
252b5132 5926
3992d3b7
AM		 5927 else if (exp->X_op == O_absent
5928 || exp->X_op == O_illegal
5929 || exp->X_op == O_big
5930 || (gotfree_input_line
5931 && (exp->X_op == O_constant
5932 || exp->X_op == O_register)))
2daf4fd8 5933 {
3992d3b7
AM		 5934 inv_disp:
5935 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 5936 disp_start);
3992d3b7 5937 ret = 0;
2daf4fd8
AM		 5938 }
5939
4c63da97 5940#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 5941 else if (exp->X_op != O_constant
5942 && OUTPUT_FLAVOR == bfd_target_aout_flavour
5943 && exp_seg != absolute_section
5944 && exp_seg != text_section
5945 && exp_seg != data_section
5946 && exp_seg != bss_section
5947 && exp_seg != undefined_section
5948 && !bfd_is_com_section (exp_seg))
24eab124 5949 {
d0b47220 5950 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 5951 ret = 0;
24eab124 5952 }
252b5132 5953#endif
3956db08 5954
3992d3b7
AM		 5955 RESTORE_END_STRING (disp_end);
5956
40fb9820
L		 5957 /* Check if this is a displacement only operand. */
5958 bigdisp = i.types[this_operand];
5959 bigdisp.bitfield.disp8 = 0;
5960 bigdisp.bitfield.disp16 = 0;
5961 bigdisp.bitfield.disp32 = 0;
5962 bigdisp.bitfield.disp32s = 0;
5963 bigdisp.bitfield.disp64 = 0;
c6fb90c8
L		 5964 if (UINTS_ALL_ZERO (bigdisp))
5965 i.types[this_operand] = operand_type_and (i.types[this_operand],
5966 types);
3956db08 5967
3992d3b7 5968 return ret;
252b5132
RH		 5969}
5970
eecb386c 5971/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 5972 Return 1 on success, 0 on a failure. */
5973
252b5132 5974static int
e3bb37b5 5975i386_index_check (const char *operand_string)
252b5132 5976{
3e73aa7c 5977 int ok;
24eab124 5978#if INFER_ADDR_PREFIX
eecb386c
AM		 5979 int fudged = 0;
5980
24eab124
AM		 5981 tryprefix:
5982#endif
3e73aa7c 5983 ok = 1;
75178d9d 5984 if (flag_code == CODE_64BIT)
64e74474 5985 {
64e74474 5986 if ((i.base_reg
40fb9820
L		 5987 && ((i.prefix[ADDR_PREFIX] == 0
5988 && !i.base_reg->reg_type.bitfield.reg64)
5989 || (i.prefix[ADDR_PREFIX]
5990 && !i.base_reg->reg_type.bitfield.reg32))
5991 && (i.index_reg
9a04903e
JB		 5992 || i.base_reg->reg_num !=
5993 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 5994 || (i.index_reg
40fb9820
L		 5995 && (!i.index_reg->reg_type.bitfield.baseindex
5996 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 5997 && i.index_reg->reg_num != RegRiz
5998 && !i.index_reg->reg_type.bitfield.reg64
5999 )
40fb9820 6000 || (i.prefix[ADDR_PREFIX]
db51cc60 6001 && i.index_reg->reg_num != RegEiz
40fb9820 6002 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 6003 ok = 0;
3e73aa7c
JH		 6004 }
6005 else
6006 {
6007 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6008 {
6009 /* 16bit checks. */
6010 if ((i.base_reg
40fb9820
L		 6011 && (!i.base_reg->reg_type.bitfield.reg16
6012 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 6013 || (i.index_reg
40fb9820
L		 6014 && (!i.index_reg->reg_type.bitfield.reg16
6015 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 6016 || !(i.base_reg
6017 && i.base_reg->reg_num < 6
6018 && i.index_reg->reg_num >= 6
6019 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 6020 ok = 0;
6021 }
6022 else
e5cb08ac 6023 {
3e73aa7c
JH		 6024 /* 32bit checks. */
6025 if ((i.base_reg
40fb9820 6026 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 6027 || (i.index_reg
db51cc60
L		 6028 && ((!i.index_reg->reg_type.bitfield.reg32
6029 && i.index_reg->reg_num != RegEiz)
40fb9820 6030 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 6031 ok = 0;
3e73aa7c
JH		 6032 }
6033 }
6034 if (!ok)
24eab124
AM		 6035 {
6036#if INFER_ADDR_PREFIX
20f0a1fc 6037 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 6038 {
6039 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6040 i.prefixes += 1;
b23bac36
AM		 6041 /* Change the size of any displacement too. At most one of
6042 Disp16 or Disp32 is set.
6043 FIXME. There doesn't seem to be any real need for separate
6044 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 6045 Removing them would probably clean up the code quite a lot. */
4eed87de 6046 if (flag_code != CODE_64BIT
40fb9820
L		 6047 && (i.types[this_operand].bitfield.disp16
6048 || i.types[this_operand].bitfield.disp32))
6049 i.types[this_operand]
c6fb90c8 6050 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 6051 fudged = 1;
24eab124
AM		 6052 goto tryprefix;
6053 }
eecb386c
AM		 6054 if (fudged)
6055 as_bad (_("`%s' is not a valid base/index expression"),
6056 operand_string);
6057 else
c388dee8 6058#endif
eecb386c
AM		 6059 as_bad (_("`%s' is not a valid %s bit base/index expression"),
6060 operand_string,
3e73aa7c 6061 flag_code_names[flag_code]);
24eab124 6062 }
20f0a1fc 6063 return ok;
24eab124 6064}
252b5132 6065
252b5132 6066/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 6067 on error. */
252b5132 6068
252b5132 6069static int
e3bb37b5 6070i386_operand (char *operand_string)
252b5132 6071{
af6bdddf
AM		 6072 const reg_entry *r;
6073 char *end_op;
24eab124 6074 char *op_string = operand_string;
252b5132 6075
24eab124 6076 if (is_space_char (*op_string))
252b5132
RH		 6077 ++op_string;
6078
24eab124 6079 /* We check for an absolute prefix (differentiating,
47926f60 6080 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 6081 if (*op_string == ABSOLUTE_PREFIX)
6082 {
6083 ++op_string;
6084 if (is_space_char (*op_string))
6085 ++op_string;
40fb9820 6086 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 6087 }
252b5132 6088
47926f60 6089 /* Check if operand is a register. */
4d1bb795 6090 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 6091 {
40fb9820
L		 6092 i386_operand_type temp;
6093
24eab124
AM		 6094 /* Check for a segment override by searching for ':' after a
6095 segment register. */
6096 op_string = end_op;
6097 if (is_space_char (*op_string))
6098 ++op_string;
40fb9820
L		 6099 if (*op_string == ':'
6100 && (r->reg_type.bitfield.sreg2
6101 || r->reg_type.bitfield.sreg3))
24eab124
AM		 6102 {
6103 switch (r->reg_num)
6104 {
6105 case 0:
6106 i.seg[i.mem_operands] = &es;
6107 break;
6108 case 1:
6109 i.seg[i.mem_operands] = &cs;
6110 break;
6111 case 2:
6112 i.seg[i.mem_operands] = &ss;
6113 break;
6114 case 3:
6115 i.seg[i.mem_operands] = &ds;
6116 break;
6117 case 4:
6118 i.seg[i.mem_operands] = &fs;
6119 break;
6120 case 5:
6121 i.seg[i.mem_operands] = &gs;
6122 break;
6123 }
252b5132 6124
24eab124 6125 /* Skip the ':' and whitespace. */
252b5132
RH		 6126 ++op_string;
6127 if (is_space_char (*op_string))
24eab124 6128 ++op_string;
252b5132 6129
24eab124
AM		 6130 if (!is_digit_char (*op_string)
6131 && !is_identifier_char (*op_string)
6132 && *op_string != '('
6133 && *op_string != ABSOLUTE_PREFIX)
6134 {
6135 as_bad (_("bad memory operand `%s'"), op_string);
6136 return 0;
6137 }
47926f60 6138 /* Handle case of %es:*foo. */
24eab124
AM		 6139 if (*op_string == ABSOLUTE_PREFIX)
6140 {
6141 ++op_string;
6142 if (is_space_char (*op_string))
6143 ++op_string;
40fb9820 6144 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 6145 }
6146 goto do_memory_reference;
6147 }
6148 if (*op_string)
6149 {
d0b47220 6150 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 6151 return 0;
6152 }
40fb9820
L		 6153 temp = r->reg_type;
6154 temp.bitfield.baseindex = 0;
c6fb90c8
L		 6155 i.types[this_operand] = operand_type_or (i.types[this_operand],
6156 temp);
520dc8e8 6157 i.op[this_operand].regs = r;
24eab124
AM		 6158 i.reg_operands++;
6159 }
af6bdddf
AM		 6160 else if (*op_string == REGISTER_PREFIX)
6161 {
6162 as_bad (_("bad register name `%s'"), op_string);
6163 return 0;
6164 }
24eab124 6165 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 6166 {
24eab124 6167 ++op_string;
40fb9820 6168 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 6169 {
d0b47220 6170 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 6171 return 0;
6172 }
6173 if (!i386_immediate (op_string))
6174 return 0;
6175 }
6176 else if (is_digit_char (*op_string)
6177 || is_identifier_char (*op_string)
e5cb08ac 6178 || *op_string == '(')
24eab124 6179 {
47926f60 6180 /* This is a memory reference of some sort. */
af6bdddf 6181 char *base_string;
252b5132 6182
47926f60 6183 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 6184 char *displacement_string_start;
6185 char *displacement_string_end;
252b5132 6186
24eab124 6187 do_memory_reference:
24eab124 6188 if ((i.mem_operands == 1
40fb9820 6189 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 6190 || i.mem_operands == 2)
6191 {
6192 as_bad (_("too many memory references for `%s'"),
6193 current_templates->start->name);
6194 return 0;
6195 }
252b5132 6196
24eab124
AM		 6197 /* Check for base index form. We detect the base index form by
6198 looking for an ')' at the end of the operand, searching
6199 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6200 after the '('. */
af6bdddf 6201 base_string = op_string + strlen (op_string);
c3332e24 6202
af6bdddf
AM		 6203 --base_string;
6204 if (is_space_char (*base_string))
6205 --base_string;
252b5132 6206
47926f60 6207 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 6208 displacement_string_start = op_string;
6209 displacement_string_end = base_string + 1;
252b5132 6210
24eab124
AM		 6211 if (*base_string == ')')
6212 {
af6bdddf 6213 char *temp_string;
24eab124
AM		 6214 unsigned int parens_balanced = 1;
6215 /* We've already checked that the number of left & right ()'s are
47926f60 6216 equal, so this loop will not be infinite. */
24eab124
AM		 6217 do
6218 {
6219 base_string--;
6220 if (*base_string == ')')
6221 parens_balanced++;
6222 if (*base_string == '(')
6223 parens_balanced--;
6224 }
6225 while (parens_balanced);
c3332e24 6226
af6bdddf 6227 temp_string = base_string;
c3332e24 6228
24eab124 6229 /* Skip past '(' and whitespace. */
252b5132
RH		 6230 ++base_string;
6231 if (is_space_char (*base_string))
24eab124 6232 ++base_string;
252b5132 6233
af6bdddf 6234 if (*base_string == ','
4eed87de
AM		 6235 || ((i.base_reg = parse_register (base_string, &end_op))
6236 != NULL))
252b5132 6237 {
af6bdddf 6238 displacement_string_end = temp_string;
252b5132 6239
40fb9820 6240 i.types[this_operand].bitfield.baseindex = 1;
252b5132 6241
af6bdddf 6242 if (i.base_reg)
24eab124 6243 {
24eab124
AM		 6244 base_string = end_op;
6245 if (is_space_char (*base_string))
6246 ++base_string;
af6bdddf
AM		 6247 }
6248
6249 /* There may be an index reg or scale factor here. */
6250 if (*base_string == ',')
6251 {
6252 ++base_string;
6253 if (is_space_char (*base_string))
6254 ++base_string;
6255
4eed87de
AM		 6256 if ((i.index_reg = parse_register (base_string, &end_op))
6257 != NULL)
24eab124 6258 {
af6bdddf 6259 base_string = end_op;
24eab124
AM		 6260 if (is_space_char (*base_string))
6261 ++base_string;
af6bdddf
AM		 6262 if (*base_string == ',')
6263 {
6264 ++base_string;
6265 if (is_space_char (*base_string))
6266 ++base_string;
6267 }
e5cb08ac 6268 else if (*base_string != ')')
af6bdddf 6269 {
4eed87de
AM		 6270 as_bad (_("expecting `,' or `)' "
6271 "after index register in `%s'"),
af6bdddf
AM		 6272 operand_string);
6273 return 0;
6274 }
24eab124 6275 }
af6bdddf 6276 else if (*base_string == REGISTER_PREFIX)
24eab124 6277 {
af6bdddf 6278 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 6279 return 0;
6280 }
252b5132 6281
47926f60 6282 /* Check for scale factor. */
551c1ca1 6283 if (*base_string != ')')
af6bdddf 6284 {
551c1ca1
AM		 6285 char *end_scale = i386_scale (base_string);
6286
6287 if (!end_scale)
af6bdddf 6288 return 0;
24eab124 6289
551c1ca1 6290 base_string = end_scale;
af6bdddf
AM		 6291 if (is_space_char (*base_string))
6292 ++base_string;
6293 if (*base_string != ')')
6294 {
4eed87de
AM		 6295 as_bad (_("expecting `)' "
6296 "after scale factor in `%s'"),
af6bdddf
AM		 6297 operand_string);
6298 return 0;
6299 }
6300 }
6301 else if (!i.index_reg)
24eab124 6302 {
4eed87de
AM		 6303 as_bad (_("expecting index register or scale factor "
6304 "after `,'; got '%c'"),
af6bdddf 6305 *base_string);
24eab124
AM		 6306 return 0;
6307 }
6308 }
af6bdddf 6309 else if (*base_string != ')')
24eab124 6310 {
4eed87de
AM		 6311 as_bad (_("expecting `,' or `)' "
6312 "after base register in `%s'"),
af6bdddf 6313 operand_string);
24eab124
AM		 6314 return 0;
6315 }
c3332e24 6316 }
af6bdddf 6317 else if (*base_string == REGISTER_PREFIX)
c3332e24 6318 {
af6bdddf 6319 as_bad (_("bad register name `%s'"), base_string);
24eab124 6320 return 0;
c3332e24 6321 }
24eab124
AM		 6322 }
6323
6324 /* If there's an expression beginning the operand, parse it,
6325 assuming displacement_string_start and
6326 displacement_string_end are meaningful. */
6327 if (displacement_string_start != displacement_string_end)
6328 {
6329 if (!i386_displacement (displacement_string_start,
6330 displacement_string_end))
6331 return 0;
6332 }
6333
6334 /* Special case for (%dx) while doing input/output op. */
6335 if (i.base_reg
c6fb90c8 6336 && UINTS_EQUAL (i.base_reg->reg_type, reg16_inoutportreg)
24eab124
AM		 6337 && i.index_reg == 0
6338 && i.log2_scale_factor == 0
6339 && i.seg[i.mem_operands] == 0
40fb9820 6340 && !operand_type_check (i.types[this_operand], disp))
24eab124 6341 {
c6fb90c8 6342 UINTS_CLEAR (i.types[this_operand]);
40fb9820 6343 i.types[this_operand].bitfield.inoutportreg = 1;
24eab124
AM		 6344 return 1;
6345 }
6346
eecb386c
AM		 6347 if (i386_index_check (operand_string) == 0)
6348 return 0;
24eab124
AM		 6349 i.mem_operands++;
6350 }
6351 else
ce8a8b2f
AM		 6352 {
6353 /* It's not a memory operand; argh! */
24eab124
AM		 6354 as_bad (_("invalid char %s beginning operand %d `%s'"),
6355 output_invalid (*op_string),
6356 this_operand + 1,
6357 op_string);
6358 return 0;
6359 }
47926f60 6360 return 1; /* Normal return. */
252b5132
RH		 6361}
6362\f
ee7fcc42
AM		 6363/* md_estimate_size_before_relax()
6364
6365 Called just before relax() for rs_machine_dependent frags. The x86
6366 assembler uses these frags to handle variable size jump
6367 instructions.
6368
6369 Any symbol that is now undefined will not become defined.
6370 Return the correct fr_subtype in the frag.
6371 Return the initial "guess for variable size of frag" to caller.
6372 The guess is actually the growth beyond the fixed part. Whatever
6373 we do to grow the fixed or variable part contributes to our
6374 returned value. */
6375
252b5132
RH		 6376int
6377md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 6378 fragS *fragP;
6379 segT segment;
252b5132 6380{
252b5132 6381 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 6382 check for un-relaxable symbols. On an ELF system, we can't relax
6383 an externally visible symbol, because it may be overridden by a
6384 shared library. */
6385 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 6386#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6387 || (IS_ELF
31312f95
AM		 6388 && (S_IS_EXTERNAL (fragP->fr_symbol)
6389 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 6390#endif
6391 )
252b5132 6392 {
b98ef147
AM		 6393 /* Symbol is undefined in this segment, or we need to keep a
6394 reloc so that weak symbols can be overridden. */
6395 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 6396 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 6397 unsigned char *opcode;
6398 int old_fr_fix;
f6af82bd 6399
ee7fcc42
AM		 6400 if (fragP->fr_var != NO_RELOC)
6401 reloc_type = fragP->fr_var;
b98ef147 6402 else if (size == 2)
f6af82bd
AM		 6403 reloc_type = BFD_RELOC_16_PCREL;
6404 else
6405 reloc_type = BFD_RELOC_32_PCREL;
252b5132 6406
ee7fcc42
AM		 6407 old_fr_fix = fragP->fr_fix;
6408 opcode = (unsigned char *) fragP->fr_opcode;
6409
fddf5b5b 6410 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 6411 {
fddf5b5b
AM		 6412 case UNCOND_JUMP:
6413 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 6414 opcode[0] = 0xe9;
252b5132 6415 fragP->fr_fix += size;
062cd5e7
AS		 6416 fix_new (fragP, old_fr_fix, size,
6417 fragP->fr_symbol,
6418 fragP->fr_offset, 1,
6419 reloc_type);
252b5132
RH		 6420 break;
6421
fddf5b5b 6422 case COND_JUMP86:
412167cb
AM		 6423 if (size == 2
6424 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 6425 {
6426 /* Negate the condition, and branch past an
6427 unconditional jump. */
6428 opcode[0] ^= 1;
6429 opcode[1] = 3;
6430 /* Insert an unconditional jump. */
6431 opcode[2] = 0xe9;
6432 /* We added two extra opcode bytes, and have a two byte
6433 offset. */
6434 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 6435 fix_new (fragP, old_fr_fix + 2, 2,
6436 fragP->fr_symbol,
6437 fragP->fr_offset, 1,
6438 reloc_type);
fddf5b5b
AM		 6439 break;
6440 }
6441 /* Fall through. */
6442
6443 case COND_JUMP:
412167cb
AM		 6444 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
6445 {
3e02c1cc
AM		 6446 fixS *fixP;
6447
412167cb 6448 fragP->fr_fix += 1;
3e02c1cc
AM		 6449 fixP = fix_new (fragP, old_fr_fix, 1,
6450 fragP->fr_symbol,
6451 fragP->fr_offset, 1,
6452 BFD_RELOC_8_PCREL);
6453 fixP->fx_signed = 1;
412167cb
AM		 6454 break;
6455 }
93c2a809 6456
24eab124 6457 /* This changes the byte-displacement jump 0x7N
fddf5b5b 6458 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 6459 opcode[1] = opcode[0] + 0x10;
f6af82bd 6460 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 6461 /* We've added an opcode byte. */
6462 fragP->fr_fix += 1 + size;
062cd5e7
AS		 6463 fix_new (fragP, old_fr_fix + 1, size,
6464 fragP->fr_symbol,
6465 fragP->fr_offset, 1,
6466 reloc_type);
252b5132 6467 break;
fddf5b5b
AM		 6468
6469 default:
6470 BAD_CASE (fragP->fr_subtype);
6471 break;
252b5132
RH		 6472 }
6473 frag_wane (fragP);
ee7fcc42 6474 return fragP->fr_fix - old_fr_fix;
252b5132 6475 }
93c2a809 6476
93c2a809
AM		 6477 /* Guess size depending on current relax state. Initially the relax
6478 state will correspond to a short jump and we return 1, because
6479 the variable part of the frag (the branch offset) is one byte
6480 long. However, we can relax a section more than once and in that
6481 case we must either set fr_subtype back to the unrelaxed state,
6482 or return the value for the appropriate branch. */
6483 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 6484}
6485
47926f60
KH		 6486/* Called after relax() is finished.
6487
6488 In: Address of frag.
6489 fr_type == rs_machine_dependent.
6490 fr_subtype is what the address relaxed to.
6491
6492 Out: Any fixSs and constants are set up.
6493 Caller will turn frag into a ".space 0". */
6494
252b5132
RH		 6495void
6496md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 6497 bfd *abfd ATTRIBUTE_UNUSED;
6498 segT sec ATTRIBUTE_UNUSED;
29b0f896 6499 fragS *fragP;
252b5132 6500{
29b0f896 6501 unsigned char *opcode;
252b5132 6502 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 6503 offsetT target_address;
6504 offsetT opcode_address;
252b5132 6505 unsigned int extension = 0;
847f7ad4 6506 offsetT displacement_from_opcode_start;
252b5132
RH		 6507
6508 opcode = (unsigned char *) fragP->fr_opcode;
6509
47926f60 6510 /* Address we want to reach in file space. */
252b5132 6511 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 6512
47926f60 6513 /* Address opcode resides at in file space. */
252b5132
RH		 6514 opcode_address = fragP->fr_address + fragP->fr_fix;
6515
47926f60 6516 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 6517 displacement_from_opcode_start = target_address - opcode_address;
6518
fddf5b5b 6519 if ((fragP->fr_subtype & BIG) == 0)
252b5132 6520 {
47926f60
KH		 6521 /* Don't have to change opcode. */
6522 extension = 1; /* 1 opcode + 1 displacement */
252b5132 6523 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 6524 }
6525 else
6526 {
6527 if (no_cond_jump_promotion
6528 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 6529 as_warn_where (fragP->fr_file, fragP->fr_line,
6530 _("long jump required"));
252b5132 6531
fddf5b5b
AM		 6532 switch (fragP->fr_subtype)
6533 {
6534 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
6535 extension = 4; /* 1 opcode + 4 displacement */
6536 opcode[0] = 0xe9;
6537 where_to_put_displacement = &opcode[1];
6538 break;
252b5132 6539
fddf5b5b
AM		 6540 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
6541 extension = 2; /* 1 opcode + 2 displacement */
6542 opcode[0] = 0xe9;
6543 where_to_put_displacement = &opcode[1];
6544 break;
252b5132 6545
fddf5b5b
AM		 6546 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
6547 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
6548 extension = 5; /* 2 opcode + 4 displacement */
6549 opcode[1] = opcode[0] + 0x10;
6550 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6551 where_to_put_displacement = &opcode[2];
6552 break;
252b5132 6553
fddf5b5b
AM		 6554 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
6555 extension = 3; /* 2 opcode + 2 displacement */
6556 opcode[1] = opcode[0] + 0x10;
6557 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6558 where_to_put_displacement = &opcode[2];
6559 break;
252b5132 6560
fddf5b5b
AM		 6561 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
6562 extension = 4;
6563 opcode[0] ^= 1;
6564 opcode[1] = 3;
6565 opcode[2] = 0xe9;
6566 where_to_put_displacement = &opcode[3];
6567 break;
6568
6569 default:
6570 BAD_CASE (fragP->fr_subtype);
6571 break;
6572 }
252b5132 6573 }
fddf5b5b 6574
7b81dfbb
AJ		 6575 /* If size if less then four we are sure that the operand fits,
6576 but if it's 4, then it could be that the displacement is larger
6577 then -/+ 2GB. */
6578 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
6579 && object_64bit
6580 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 6581 + ((addressT) 1 << 31))
6582 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 6583 {
6584 as_bad_where (fragP->fr_file, fragP->fr_line,
6585 _("jump target out of range"));
6586 /* Make us emit 0. */
6587 displacement_from_opcode_start = extension;
6588 }
47926f60 6589 /* Now put displacement after opcode. */
252b5132
RH		 6590 md_number_to_chars ((char *) where_to_put_displacement,
6591 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 6592 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 6593 fragP->fr_fix += extension;
6594}
6595\f
47926f60
KH		 6596/* Size of byte displacement jmp. */
6597int md_short_jump_size = 2;
6598
6599/* Size of dword displacement jmp. */
6600int md_long_jump_size = 5;
252b5132 6601
252b5132
RH		 6602void
6603md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
6604 char *ptr;
6605 addressT from_addr, to_addr;
ab9da554
ILT		 6606 fragS *frag ATTRIBUTE_UNUSED;
6607 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 6608{
847f7ad4 6609 offsetT offset;
252b5132
RH		 6610
6611 offset = to_addr - (from_addr + 2);
47926f60
KH		 6612 /* Opcode for byte-disp jump. */
6613 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 6614 md_number_to_chars (ptr + 1, (valueT) offset, 1);
6615}
6616
6617void
6618md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
6619 char *ptr;
6620 addressT from_addr, to_addr;
a38cf1db
AM		 6621 fragS *frag ATTRIBUTE_UNUSED;
6622 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 6623{
847f7ad4 6624 offsetT offset;
252b5132 6625
a38cf1db
AM		 6626 offset = to_addr - (from_addr + 5);
6627 md_number_to_chars (ptr, (valueT) 0xe9, 1);
6628 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 6629}
6630\f
6631/* Apply a fixup (fixS) to segment data, once it has been determined
6632 by our caller that we have all the info we need to fix it up.
6633
6634 On the 386, immediates, displacements, and data pointers are all in
6635 the same (little-endian) format, so we don't need to care about which
6636 we are handling. */
6637
94f592af 6638void
55cf6793 6639md_apply_fix (fixP, valP, seg)
47926f60
KH		 6640 /* The fix we're to put in. */
6641 fixS *fixP;
47926f60 6642 /* Pointer to the value of the bits. */
c6682705 6643 valueT *valP;
47926f60
KH		 6644 /* Segment fix is from. */
6645 segT seg ATTRIBUTE_UNUSED;
252b5132 6646{
94f592af 6647 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 6648 valueT value = *valP;
252b5132 6649
f86103b7 6650#if !defined (TE_Mach)
93382f6d
AM		 6651 if (fixP->fx_pcrel)
6652 {
6653 switch (fixP->fx_r_type)
6654 {
5865bb77
ILT		 6655 default:
6656 break;
6657
d6ab8113
JB		 6658 case BFD_RELOC_64:
6659 fixP->fx_r_type = BFD_RELOC_64_PCREL;
6660 break;
93382f6d 6661 case BFD_RELOC_32:
ae8887b5 6662 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 6663 fixP->fx_r_type = BFD_RELOC_32_PCREL;
6664 break;
6665 case BFD_RELOC_16:
6666 fixP->fx_r_type = BFD_RELOC_16_PCREL;
6667 break;
6668 case BFD_RELOC_8:
6669 fixP->fx_r_type = BFD_RELOC_8_PCREL;
6670 break;
6671 }
6672 }
252b5132 6673
a161fe53 6674 if (fixP->fx_addsy != NULL
31312f95 6675 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 6676 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 6677 || fixP->fx_r_type == BFD_RELOC_16_PCREL
6678 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
6679 && !use_rela_relocations)
252b5132 6680 {
31312f95
AM		 6681 /* This is a hack. There should be a better way to handle this.
6682 This covers for the fact that bfd_install_relocation will
6683 subtract the current location (for partial_inplace, PC relative
6684 relocations); see more below. */
252b5132 6685#ifndef OBJ_AOUT
718ddfc0 6686 if (IS_ELF
252b5132
RH		 6687#ifdef TE_PE
6688 || OUTPUT_FLAVOR == bfd_target_coff_flavour
6689#endif
6690 )
6691 value += fixP->fx_where + fixP->fx_frag->fr_address;
6692#endif
6693#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6694 if (IS_ELF)
252b5132 6695 {
6539b54b 6696 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 6697
6539b54b 6698 if ((sym_seg == seg
2f66722d 6699 || (symbol_section_p (fixP->fx_addsy)
6539b54b 6700 && sym_seg != absolute_section))
ae6063d4 6701 && !generic_force_reloc (fixP))
2f66722d
AM		 6702 {
6703 /* Yes, we add the values in twice. This is because
6539b54b
AM		 6704 bfd_install_relocation subtracts them out again. I think
6705 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 6706 it. FIXME. */
6707 value += fixP->fx_where + fixP->fx_frag->fr_address;
6708 }
252b5132
RH		 6709 }
6710#endif
6711#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 6712 /* For some reason, the PE format does not store a
6713 section address offset for a PC relative symbol. */
6714 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 6715 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 6716 value += md_pcrel_from (fixP);
6717#endif
6718 }
6719
6720 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 6721 and we must not disappoint it. */
252b5132 6722#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6723 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 6724 switch (fixP->fx_r_type)
6725 {
6726 case BFD_RELOC_386_PLT32:
3e73aa7c 6727 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 6728 /* Make the jump instruction point to the address of the operand. At
6729 runtime we merely add the offset to the actual PLT entry. */
6730 value = -4;
6731 break;
31312f95 6732
13ae64f3
JJ		 6733 case BFD_RELOC_386_TLS_GD:
6734 case BFD_RELOC_386_TLS_LDM:
13ae64f3 6735 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 6736 case BFD_RELOC_386_TLS_IE:
6737 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 6738 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 6739 case BFD_RELOC_X86_64_TLSGD:
6740 case BFD_RELOC_X86_64_TLSLD:
6741 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 6742 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 6743 value = 0; /* Fully resolved at runtime. No addend. */
6744 /* Fallthrough */
6745 case BFD_RELOC_386_TLS_LE:
6746 case BFD_RELOC_386_TLS_LDO_32:
6747 case BFD_RELOC_386_TLS_LE_32:
6748 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 6749 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 6750 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 6751 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 6752 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6753 break;
6754
67a4f2b7
AO		 6755 case BFD_RELOC_386_TLS_DESC_CALL:
6756 case BFD_RELOC_X86_64_TLSDESC_CALL:
6757 value = 0; /* Fully resolved at runtime. No addend. */
6758 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6759 fixP->fx_done = 0;
6760 return;
6761
00f7efb6
JJ		 6762 case BFD_RELOC_386_GOT32:
6763 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 6764 value = 0; /* Fully resolved at runtime. No addend. */
6765 break;
47926f60
KH		 6766
6767 case BFD_RELOC_VTABLE_INHERIT:
6768 case BFD_RELOC_VTABLE_ENTRY:
6769 fixP->fx_done = 0;
94f592af 6770 return;
47926f60
KH		 6771
6772 default:
6773 break;
6774 }
6775#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 6776 *valP = value;
f86103b7 6777#endif /* !defined (TE_Mach) */
3e73aa7c 6778
3e73aa7c 6779 /* Are we finished with this relocation now? */
c6682705 6780 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 6781 fixP->fx_done = 1;
6782 else if (use_rela_relocations)
6783 {
6784 fixP->fx_no_overflow = 1;
062cd5e7
AS		 6785 /* Remember value for tc_gen_reloc. */
6786 fixP->fx_addnumber = value;
3e73aa7c
JH		 6787 value = 0;
6788 }
f86103b7 6789
94f592af 6790 md_number_to_chars (p, value, fixP->fx_size);
252b5132 6791}
252b5132 6792\f
252b5132 6793char *
499ac353 6794md_atof (int type, char *litP, int *sizeP)
252b5132 6795{
499ac353
NC		 6796 /* This outputs the LITTLENUMs in REVERSE order;
6797 in accord with the bigendian 386. */
6798 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 6799}
6800\f
2d545b82 6801static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 6802
252b5132 6803static char *
e3bb37b5 6804output_invalid (int c)
252b5132 6805{
3882b010 6806 if (ISPRINT (c))
f9f21a03
L		 6807 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
6808 "'%c'", c);
252b5132 6809 else
f9f21a03 6810 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 6811 "(0x%x)", (unsigned char) c);
252b5132
RH		 6812 return output_invalid_buf;
6813}
6814
af6bdddf 6815/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 6816
6817static const reg_entry *
4d1bb795 6818parse_real_register (char *reg_string, char **end_op)
252b5132 6819{
af6bdddf
AM		 6820 char *s = reg_string;
6821 char *p;
252b5132
RH		 6822 char reg_name_given[MAX_REG_NAME_SIZE + 1];
6823 const reg_entry *r;
6824
6825 /* Skip possible REGISTER_PREFIX and possible whitespace. */
6826 if (*s == REGISTER_PREFIX)
6827 ++s;
6828
6829 if (is_space_char (*s))
6830 ++s;
6831
6832 p = reg_name_given;
af6bdddf 6833 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 6834 {
6835 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 6836 return (const reg_entry *) NULL;
6837 s++;
252b5132
RH		 6838 }
6839
6588847e
DN		 6840 /* For naked regs, make sure that we are not dealing with an identifier.
6841 This prevents confusing an identifier like `eax_var' with register
6842 `eax'. */
6843 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
6844 return (const reg_entry *) NULL;
6845
af6bdddf 6846 *end_op = s;
252b5132
RH		 6847
6848 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
6849
5f47d35b 6850 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 6851 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 6852 {
5f47d35b
AM		 6853 if (is_space_char (*s))
6854 ++s;
6855 if (*s == '(')
6856 {
af6bdddf 6857 ++s;
5f47d35b
AM		 6858 if (is_space_char (*s))
6859 ++s;
6860 if (*s >= '0' && *s <= '7')
6861 {
db557034 6862 int fpr = *s - '0';
af6bdddf 6863 ++s;
5f47d35b
AM		 6864 if (is_space_char (*s))
6865 ++s;
6866 if (*s == ')')
6867 {
6868 *end_op = s + 1;
db557034
AM		 6869 r = hash_find (reg_hash, "st(0)");
6870 know (r);
6871 return r + fpr;
5f47d35b 6872 }
5f47d35b 6873 }
47926f60 6874 /* We have "%st(" then garbage. */
5f47d35b
AM		 6875 return (const reg_entry *) NULL;
6876 }
6877 }
6878
db51cc60
L		 6879 /* Don't allow fake index register unless allow_index_reg isn't 0. */
6880 if (r != NULL
6881 && !allow_index_reg
6882 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
6883 return (const reg_entry *) NULL;
6884
1ae00879 6885 if (r != NULL
d946b91f 6886 && ((r->reg_flags & (RegRex64 | RegRex))
40fb9820
L		 6887 || r->reg_type.bitfield.reg64)
6888 && (!cpu_arch_flags.bitfield.cpulm
c6fb90c8 6889 || !UINTS_EQUAL (r->reg_type, control))
1ae00879 6890 && flag_code != CODE_64BIT)
20f0a1fc 6891 return (const reg_entry *) NULL;
1ae00879 6892
252b5132
RH		 6893 return r;
6894}
4d1bb795
JB		 6895
6896/* REG_STRING starts *before* REGISTER_PREFIX. */
6897
6898static const reg_entry *
6899parse_register (char *reg_string, char **end_op)
6900{
6901 const reg_entry *r;
6902
6903 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
6904 r = parse_real_register (reg_string, end_op);
6905 else
6906 r = NULL;
6907 if (!r)
6908 {
6909 char *save = input_line_pointer;
6910 char c;
6911 symbolS *symbolP;
6912
6913 input_line_pointer = reg_string;
6914 c = get_symbol_end ();
6915 symbolP = symbol_find (reg_string);
6916 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
6917 {
6918 const expressionS *e = symbol_get_value_expression (symbolP);
6919
6920 know (e->X_op == O_register);
4eed87de 6921 know (e->X_add_number >= 0
c3fe08fa 6922 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 6923 r = i386_regtab + e->X_add_number;
6924 *end_op = input_line_pointer;
6925 }
6926 *input_line_pointer = c;
6927 input_line_pointer = save;
6928 }
6929 return r;
6930}
6931
6932int
6933i386_parse_name (char *name, expressionS *e, char *nextcharP)
6934{
6935 const reg_entry *r;
6936 char *end = input_line_pointer;
6937
6938 *end = *nextcharP;
6939 r = parse_register (name, &input_line_pointer);
6940 if (r && end <= input_line_pointer)
6941 {
6942 *nextcharP = *input_line_pointer;
6943 *input_line_pointer = 0;
6944 e->X_op = O_register;
6945 e->X_add_number = r - i386_regtab;
6946 return 1;
6947 }
6948 input_line_pointer = end;
6949 *end = 0;
6950 return 0;
6951}
6952
6953void
6954md_operand (expressionS *e)
6955{
6956 if (*input_line_pointer == REGISTER_PREFIX)
6957 {
6958 char *end;
6959 const reg_entry *r = parse_real_register (input_line_pointer, &end);
6960
6961 if (r)
6962 {
6963 e->X_op = O_register;
6964 e->X_add_number = r - i386_regtab;
6965 input_line_pointer = end;
6966 }
6967 }
6968}
6969
252b5132 6970\f
4cc782b5 6971#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 6972const char *md_shortopts = "kVQ:sqn";
252b5132 6973#else
12b55ccc 6974const char *md_shortopts = "qn";
252b5132 6975#endif
6e0b89ee 6976
3e73aa7c 6977#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 6978#define OPTION_64 (OPTION_MD_BASE + 1)
6979#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 6980#define OPTION_MARCH (OPTION_MD_BASE + 3)
6981#define OPTION_MTUNE (OPTION_MD_BASE + 4)
b3b91714 6982
99ad8390
NC		 6983struct option md_longopts[] =
6984{
3e73aa7c 6985 {"32", no_argument, NULL, OPTION_32},
99ad8390 6986#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 6987 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 6988#endif
b3b91714 6989 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 6990 {"march", required_argument, NULL, OPTION_MARCH},
6991 {"mtune", required_argument, NULL, OPTION_MTUNE},
252b5132
RH		 6992 {NULL, no_argument, NULL, 0}
6993};
6994size_t md_longopts_size = sizeof (md_longopts);
6995
6996int
9103f4f4 6997md_parse_option (int c, char *arg)
252b5132 6998{
9103f4f4
L		 6999 unsigned int i;
7000
252b5132
RH		 7001 switch (c)
7002 {
12b55ccc
L		 7003 case 'n':
7004 optimize_align_code = 0;
7005 break;
7006
a38cf1db
AM		 7007 case 'q':
7008 quiet_warnings = 1;
252b5132
RH		 7009 break;
7010
7011#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 7012 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7013 should be emitted or not. FIXME: Not implemented. */
7014 case 'Q':
252b5132
RH		 7015 break;
7016
7017 /* -V: SVR4 argument to print version ID. */
7018 case 'V':
7019 print_version_id ();
7020 break;
7021
a38cf1db
AM		 7022 /* -k: Ignore for FreeBSD compatibility. */
7023 case 'k':
252b5132 7024 break;
4cc782b5
ILT		 7025
7026 case 's':
7027 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 7028 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 7029 break;
99ad8390
NC		 7030#endif
7031#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 7032 case OPTION_64:
7033 {
7034 const char **list, **l;
7035
3e73aa7c
JH		 7036 list = bfd_target_list ();
7037 for (l = list; *l != NULL; l++)
8620418b 7038 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 7039 || strcmp (*l, "coff-x86-64") == 0
7040 || strcmp (*l, "pe-x86-64") == 0
7041 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 7042 {
7043 default_arch = "x86_64";
7044 break;
7045 }
3e73aa7c 7046 if (*l == NULL)
6e0b89ee 7047 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 7048 free (list);
7049 }
7050 break;
7051#endif
252b5132 7052
6e0b89ee
AM		 7053 case OPTION_32:
7054 default_arch = "i386";
7055 break;
7056
b3b91714
AM		 7057 case OPTION_DIVIDE:
7058#ifdef SVR4_COMMENT_CHARS
7059 {
7060 char *n, *t;
7061 const char *s;
7062
7063 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7064 t = n;
7065 for (s = i386_comment_chars; *s != '\0'; s++)
7066 if (*s != '/')
7067 *t++ = *s;
7068 *t = '\0';
7069 i386_comment_chars = n;
7070 }
7071#endif
7072 break;
7073
9103f4f4
L		 7074 case OPTION_MARCH:
7075 if (*arg == '.')
7076 as_fatal (_("Invalid -march= option: `%s'"), arg);
7077 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7078 {
7079 if (strcmp (arg, cpu_arch [i].name) == 0)
7080 {
ccc9c027 7081 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 7082 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 7083 if (!cpu_arch_tune_set)
7084 {
7085 cpu_arch_tune = cpu_arch_isa;
7086 cpu_arch_tune_flags = cpu_arch_isa_flags;
7087 }
9103f4f4
L		 7088 break;
7089 }
7090 }
7091 if (i >= ARRAY_SIZE (cpu_arch))
7092 as_fatal (_("Invalid -march= option: `%s'"), arg);
7093 break;
7094
7095 case OPTION_MTUNE:
7096 if (*arg == '.')
7097 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7098 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7099 {
7100 if (strcmp (arg, cpu_arch [i].name) == 0)
7101 {
ccc9c027 7102 cpu_arch_tune_set = 1;
9103f4f4
L		 7103 cpu_arch_tune = cpu_arch [i].type;
7104 cpu_arch_tune_flags = cpu_arch[i].flags;
7105 break;
7106 }
7107 }
7108 if (i >= ARRAY_SIZE (cpu_arch))
7109 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7110 break;
7111
252b5132
RH		 7112 default:
7113 return 0;
7114 }
7115 return 1;
7116}
7117
7118void
7119md_show_usage (stream)
7120 FILE *stream;
7121{
4cc782b5
ILT		 7122#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7123 fprintf (stream, _("\
a38cf1db
AM		 7124 -Q ignored\n\
7125 -V print assembler version number\n\
b3b91714
AM		 7126 -k ignored\n"));
7127#endif
7128 fprintf (stream, _("\
12b55ccc 7129 -n Do not optimize code alignment\n\
b3b91714
AM		 7130 -q quieten some warnings\n"));
7131#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7132 fprintf (stream, _("\
a38cf1db 7133 -s ignored\n"));
b3b91714 7134#endif
751d281c
L		 7135#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7136 fprintf (stream, _("\
7137 --32/--64 generate 32bit/64bit code\n"));
7138#endif
b3b91714
AM		 7139#ifdef SVR4_COMMENT_CHARS
7140 fprintf (stream, _("\
7141 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 7142#else
7143 fprintf (stream, _("\
b3b91714 7144 --divide ignored\n"));
4cc782b5 7145#endif
9103f4f4
L		 7146 fprintf (stream, _("\
7147 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
7148 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
4eed87de 7149 core, core2, k6, athlon, k8, generic32, generic64\n"));
9103f4f4 7150
252b5132
RH		 7151}
7152
3e73aa7c 7153#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
872ce6ff 7154 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
252b5132
RH		 7155
7156/* Pick the target format to use. */
7157
47926f60 7158const char *
e3bb37b5 7159i386_target_format (void)
252b5132 7160{
3e73aa7c 7161 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 7162 {
7163 set_code_flag (CODE_64BIT);
c6fb90c8 7164 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
40fb9820
L		 7165 {
7166 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7167 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7168 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7169 cpu_arch_isa_flags.bitfield.cpui486 = 1;
7170 cpu_arch_isa_flags.bitfield.cpui586 = 1;
7171 cpu_arch_isa_flags.bitfield.cpui686 = 1;
7172 cpu_arch_isa_flags.bitfield.cpup4 = 1;
7173 cpu_arch_isa_flags.bitfield.cpummx= 1;
7174 cpu_arch_isa_flags.bitfield.cpummx2 = 1;
7175 cpu_arch_isa_flags.bitfield.cpusse = 1;
7176 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
7177 }
c6fb90c8 7178 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
40fb9820
L		 7179 {
7180 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7181 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7182 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7183 cpu_arch_tune_flags.bitfield.cpui486 = 1;
7184 cpu_arch_tune_flags.bitfield.cpui586 = 1;
7185 cpu_arch_tune_flags.bitfield.cpui686 = 1;
7186 cpu_arch_tune_flags.bitfield.cpup4 = 1;
7187 cpu_arch_tune_flags.bitfield.cpummx= 1;
7188 cpu_arch_tune_flags.bitfield.cpummx2 = 1;
7189 cpu_arch_tune_flags.bitfield.cpusse = 1;
7190 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
7191 }
9103f4f4 7192 }
3e73aa7c 7193 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 7194 {
7195 set_code_flag (CODE_32BIT);
c6fb90c8 7196 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
40fb9820
L		 7197 {
7198 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7199 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7200 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7201 }
c6fb90c8 7202 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
40fb9820
L		 7203 {
7204 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7205 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7206 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7207 }
9103f4f4 7208 }
3e73aa7c
JH		 7209 else
7210 as_fatal (_("Unknown architecture"));
252b5132
RH		 7211 switch (OUTPUT_FLAVOR)
7212 {
872ce6ff
L		 7213#ifdef TE_PEP
7214 case bfd_target_coff_flavour:
7215 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386";
7216 break;
7217#endif
4c63da97
AM		 7218#ifdef OBJ_MAYBE_AOUT
7219 case bfd_target_aout_flavour:
47926f60 7220 return AOUT_TARGET_FORMAT;
4c63da97
AM		 7221#endif
7222#ifdef OBJ_MAYBE_COFF
252b5132
RH		 7223 case bfd_target_coff_flavour:
7224 return "coff-i386";
4c63da97 7225#endif
3e73aa7c 7226#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 7227 case bfd_target_elf_flavour:
3e73aa7c 7228 {
e5cb08ac 7229 if (flag_code == CODE_64BIT)
4fa24527
JB		 7230 {
7231 object_64bit = 1;
7232 use_rela_relocations = 1;
7233 }
9d7cbccd 7234 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 7235 }
4c63da97 7236#endif
252b5132
RH		 7237 default:
7238 abort ();
7239 return NULL;
7240 }
7241}
7242
47926f60 7243#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 7244
7245#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 7246void
7247i386_elf_emit_arch_note (void)
a847613f 7248{
718ddfc0 7249 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 7250 {
7251 char *p;
7252 asection *seg = now_seg;
7253 subsegT subseg = now_subseg;
7254 Elf_Internal_Note i_note;
7255 Elf_External_Note e_note;
7256 asection *note_secp;
7257 int len;
7258
7259 /* Create the .note section. */
7260 note_secp = subseg_new (".note", 0);
7261 bfd_set_section_flags (stdoutput,
7262 note_secp,
7263 SEC_HAS_CONTENTS | SEC_READONLY);
7264
7265 /* Process the arch string. */
7266 len = strlen (cpu_arch_name);
7267
7268 i_note.namesz = len + 1;
7269 i_note.descsz = 0;
7270 i_note.type = NT_ARCH;
7271 p = frag_more (sizeof (e_note.namesz));
7272 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
7273 p = frag_more (sizeof (e_note.descsz));
7274 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
7275 p = frag_more (sizeof (e_note.type));
7276 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
7277 p = frag_more (len + 1);
7278 strcpy (p, cpu_arch_name);
7279
7280 frag_align (2, 0, 0);
7281
7282 subseg_set (seg, subseg);
7283 }
7284}
7285#endif
252b5132 7286\f
252b5132
RH		 7287symbolS *
7288md_undefined_symbol (name)
7289 char *name;
7290{
18dc2407
ILT		 7291 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
7292 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
7293 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
7294 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 7295 {
7296 if (!GOT_symbol)
7297 {
7298 if (symbol_find (name))
7299 as_bad (_("GOT already in symbol table"));
7300 GOT_symbol = symbol_new (name, undefined_section,
7301 (valueT) 0, &zero_address_frag);
7302 };
7303 return GOT_symbol;
7304 }
252b5132
RH		 7305 return 0;
7306}
7307
7308/* Round up a section size to the appropriate boundary. */
47926f60 7309
252b5132
RH		 7310valueT
7311md_section_align (segment, size)
ab9da554 7312 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 7313 valueT size;
7314{
4c63da97
AM		 7315#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7316 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
7317 {
7318 /* For a.out, force the section size to be aligned. If we don't do
7319 this, BFD will align it for us, but it will not write out the
7320 final bytes of the section. This may be a bug in BFD, but it is
7321 easier to fix it here since that is how the other a.out targets
7322 work. */
7323 int align;
7324
7325 align = bfd_get_section_alignment (stdoutput, segment);
7326 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7327 }
252b5132
RH		 7328#endif
7329
7330 return size;
7331}
7332
7333/* On the i386, PC-relative offsets are relative to the start of the
7334 next instruction. That is, the address of the offset, plus its
7335 size, since the offset is always the last part of the insn. */
7336
7337long
e3bb37b5 7338md_pcrel_from (fixS *fixP)
252b5132
RH		 7339{
7340 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
7341}
7342
7343#ifndef I386COFF
7344
7345static void
e3bb37b5 7346s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 7347{
29b0f896 7348 int temp;
252b5132 7349
8a75718c
JB		 7350#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7351 if (IS_ELF)
7352 obj_elf_section_change_hook ();
7353#endif
252b5132
RH		 7354 temp = get_absolute_expression ();
7355 subseg_set (bss_section, (subsegT) temp);
7356 demand_empty_rest_of_line ();
7357}
7358
7359#endif
7360
252b5132 7361void
e3bb37b5 7362i386_validate_fix (fixS *fixp)
252b5132
RH		 7363{
7364 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
7365 {
23df1078
JH		 7366 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
7367 {
4fa24527 7368 if (!object_64bit)
23df1078
JH		 7369 abort ();
7370 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
7371 }
7372 else
7373 {
4fa24527 7374 if (!object_64bit)
d6ab8113
JB		 7375 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
7376 else
7377 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 7378 }
252b5132
RH		 7379 fixp->fx_subsy = 0;
7380 }
7381}
7382
252b5132
RH		 7383arelent *
7384tc_gen_reloc (section, fixp)
ab9da554 7385 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 7386 fixS *fixp;
7387{
7388 arelent *rel;
7389 bfd_reloc_code_real_type code;
7390
7391 switch (fixp->fx_r_type)
7392 {
3e73aa7c
JH		 7393 case BFD_RELOC_X86_64_PLT32:
7394 case BFD_RELOC_X86_64_GOT32:
7395 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 7396 case BFD_RELOC_386_PLT32:
7397 case BFD_RELOC_386_GOT32:
7398 case BFD_RELOC_386_GOTOFF:
7399 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 7400 case BFD_RELOC_386_TLS_GD:
7401 case BFD_RELOC_386_TLS_LDM:
7402 case BFD_RELOC_386_TLS_LDO_32:
7403 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7404 case BFD_RELOC_386_TLS_IE:
7405 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 7406 case BFD_RELOC_386_TLS_LE_32:
7407 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 7408 case BFD_RELOC_386_TLS_GOTDESC:
7409 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 7410 case BFD_RELOC_X86_64_TLSGD:
7411 case BFD_RELOC_X86_64_TLSLD:
7412 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7413 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 7414 case BFD_RELOC_X86_64_GOTTPOFF:
7415 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 7416 case BFD_RELOC_X86_64_TPOFF64:
7417 case BFD_RELOC_X86_64_GOTOFF64:
7418 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 7419 case BFD_RELOC_X86_64_GOT64:
7420 case BFD_RELOC_X86_64_GOTPCREL64:
7421 case BFD_RELOC_X86_64_GOTPC64:
7422 case BFD_RELOC_X86_64_GOTPLT64:
7423 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 7424 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7425 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 7426 case BFD_RELOC_RVA:
7427 case BFD_RELOC_VTABLE_ENTRY:
7428 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 7429#ifdef TE_PE
7430 case BFD_RELOC_32_SECREL:
7431#endif
252b5132
RH		 7432 code = fixp->fx_r_type;
7433 break;
dbbaec26
L		 7434 case BFD_RELOC_X86_64_32S:
7435 if (!fixp->fx_pcrel)
7436 {
7437 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
7438 code = fixp->fx_r_type;
7439 break;
7440 }
252b5132 7441 default:
93382f6d 7442 if (fixp->fx_pcrel)
252b5132 7443 {
93382f6d
AM		 7444 switch (fixp->fx_size)
7445 {
7446 default:
b091f402
AM		 7447 as_bad_where (fixp->fx_file, fixp->fx_line,
7448 _("can not do %d byte pc-relative relocation"),
7449 fixp->fx_size);
93382f6d
AM		 7450 code = BFD_RELOC_32_PCREL;
7451 break;
7452 case 1: code = BFD_RELOC_8_PCREL; break;
7453 case 2: code = BFD_RELOC_16_PCREL; break;
7454 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 7455#ifdef BFD64
7456 case 8: code = BFD_RELOC_64_PCREL; break;
7457#endif
93382f6d
AM		 7458 }
7459 }
7460 else
7461 {
7462 switch (fixp->fx_size)
7463 {
7464 default:
b091f402
AM		 7465 as_bad_where (fixp->fx_file, fixp->fx_line,
7466 _("can not do %d byte relocation"),
7467 fixp->fx_size);
93382f6d
AM		 7468 code = BFD_RELOC_32;
7469 break;
7470 case 1: code = BFD_RELOC_8; break;
7471 case 2: code = BFD_RELOC_16; break;
7472 case 4: code = BFD_RELOC_32; break;
937149dd 7473#ifdef BFD64
3e73aa7c 7474 case 8: code = BFD_RELOC_64; break;
937149dd 7475#endif
93382f6d 7476 }
252b5132
RH		 7477 }
7478 break;
7479 }
252b5132 7480
d182319b
JB		 7481 if ((code == BFD_RELOC_32
7482 || code == BFD_RELOC_32_PCREL
7483 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 7484 && GOT_symbol
7485 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 7486 {
4fa24527 7487 if (!object_64bit)
d6ab8113
JB		 7488 code = BFD_RELOC_386_GOTPC;
7489 else
7490 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 7491 }
7b81dfbb
AJ		 7492 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
7493 && GOT_symbol
7494 && fixp->fx_addsy == GOT_symbol)
7495 {
7496 code = BFD_RELOC_X86_64_GOTPC64;
7497 }
252b5132
RH		 7498
7499 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 7500 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
7501 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 7502
7503 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 7504
3e73aa7c
JH		 7505 if (!use_rela_relocations)
7506 {
7507 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
7508 vtable entry to be used in the relocation's section offset. */
7509 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7510 rel->address = fixp->fx_offset;
252b5132 7511
c6682705 7512 rel->addend = 0;
3e73aa7c
JH		 7513 }
7514 /* Use the rela in 64bit mode. */
252b5132 7515 else
3e73aa7c 7516 {
062cd5e7
AS		 7517 if (!fixp->fx_pcrel)
7518 rel->addend = fixp->fx_offset;
7519 else
7520 switch (code)
7521 {
7522 case BFD_RELOC_X86_64_PLT32:
7523 case BFD_RELOC_X86_64_GOT32:
7524 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 7525 case BFD_RELOC_X86_64_TLSGD:
7526 case BFD_RELOC_X86_64_TLSLD:
7527 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 7528 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7529 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 7530 rel->addend = fixp->fx_offset - fixp->fx_size;
7531 break;
7532 default:
7533 rel->addend = (section->vma
7534 - fixp->fx_size
7535 + fixp->fx_addnumber
7536 + md_pcrel_from (fixp));
7537 break;
7538 }
3e73aa7c
JH		 7539 }
7540
252b5132
RH		 7541 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
7542 if (rel->howto == NULL)
7543 {
7544 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 7545 _("cannot represent relocation type %s"),
252b5132
RH		 7546 bfd_get_reloc_code_name (code));
7547 /* Set howto to a garbage value so that we can keep going. */
7548 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
7549 assert (rel->howto != NULL);
7550 }
7551
7552 return rel;
7553}
7554
64a0c779
DN		 7555\f
7556/* Parse operands using Intel syntax. This implements a recursive descent
7557 parser based on the BNF grammar published in Appendix B of the MASM 6.1
7558 Programmer's Guide.
7559
7560 FIXME: We do not recognize the full operand grammar defined in the MASM
7561 documentation. In particular, all the structure/union and
7562 high-level macro operands are missing.
7563
7564 Uppercase words are terminals, lower case words are non-terminals.
7565 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
7566 bars '|' denote choices. Most grammar productions are implemented in
7567 functions called 'intel_<production>'.
7568
7569 Initial production is 'expr'.
7570
9306ca4a 7571 addOp + | -
64a0c779
DN		 7572
7573 alpha [a-zA-Z]
7574
9306ca4a
JB		 7575 binOp & | AND | \| | OR | ^ | XOR
7576
64a0c779
DN		 7577 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
7578
7579 constant digits [[ radixOverride ]]
7580
9306ca4a 7581 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 7582
7583 digits decdigit
b77a7acd
AJ		 7584 | digits decdigit
7585 | digits hexdigit
64a0c779
DN		 7586
7587 decdigit [0-9]
7588
9306ca4a
JB		 7589 e04 e04 addOp e05
7590 | e05
7591
7592 e05 e05 binOp e06
b77a7acd 7593 | e06
64a0c779
DN		 7594
7595 e06 e06 mulOp e09
b77a7acd 7596 | e09
64a0c779
DN		 7597
7598 e09 OFFSET e10
a724f0f4
JB		 7599 | SHORT e10
7600 | + e10
7601 | - e10
9306ca4a
JB		 7602 | ~ e10
7603 | NOT e10
64a0c779
DN		 7604 | e09 PTR e10
7605 | e09 : e10
7606 | e10
7607
7608 e10 e10 [ expr ]
b77a7acd 7609 | e11
64a0c779
DN		 7610
7611 e11 ( expr )
b77a7acd 7612 | [ expr ]
64a0c779
DN		 7613 | constant
7614 | dataType
7615 | id
7616 | $
7617 | register
7618
a724f0f4 7619 => expr expr cmpOp e04
9306ca4a 7620 | e04
64a0c779
DN		 7621
7622 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 7623 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 7624
7625 hexdigit a | b | c | d | e | f
b77a7acd 7626 | A | B | C | D | E | F
64a0c779
DN		 7627
7628 id alpha
b77a7acd 7629 | id alpha
64a0c779
DN		 7630 | id decdigit
7631
9306ca4a 7632 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 7633
7634 quote " | '
7635
7636 register specialRegister
b77a7acd 7637 | gpRegister
64a0c779
DN		 7638 | byteRegister
7639
7640 segmentRegister CS | DS | ES | FS | GS | SS
7641
9306ca4a 7642 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 7643 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 7644 | TR3 | TR4 | TR5 | TR6 | TR7
7645
64a0c779
DN		 7646 We simplify the grammar in obvious places (e.g., register parsing is
7647 done by calling parse_register) and eliminate immediate left recursion
7648 to implement a recursive-descent parser.
7649
a724f0f4
JB		 7650 expr e04 expr'
7651
7652 expr' cmpOp e04 expr'
7653 | Empty
9306ca4a
JB		 7654
7655 e04 e05 e04'
7656
7657 e04' addOp e05 e04'
7658 | Empty
64a0c779
DN		 7659
7660 e05 e06 e05'
7661
9306ca4a 7662 e05' binOp e06 e05'
b77a7acd 7663 | Empty
64a0c779
DN		 7664
7665 e06 e09 e06'
7666
7667 e06' mulOp e09 e06'
b77a7acd 7668 | Empty
64a0c779
DN		 7669
7670 e09 OFFSET e10 e09'
a724f0f4
JB		 7671 | SHORT e10'
7672 | + e10'
7673 | - e10'
7674 | ~ e10'
7675 | NOT e10'
b77a7acd 7676 | e10 e09'
64a0c779
DN		 7677
7678 e09' PTR e10 e09'
b77a7acd 7679 | : e10 e09'
64a0c779
DN		 7680 | Empty
7681
7682 e10 e11 e10'
7683
7684 e10' [ expr ] e10'
b77a7acd 7685 | Empty
64a0c779
DN		 7686
7687 e11 ( expr )
b77a7acd 7688 | [ expr ]
64a0c779
DN		 7689 | BYTE
7690 | WORD
7691 | DWORD
9306ca4a 7692 | FWORD
64a0c779 7693 | QWORD
9306ca4a
JB		 7694 | TBYTE
7695 | OWORD
7696 | XMMWORD
64a0c779
DN		 7697 | .
7698 | $
7699 | register
7700 | id
7701 | constant */
7702
7703/* Parsing structure for the intel syntax parser. Used to implement the
7704 semantic actions for the operand grammar. */
7705struct intel_parser_s
7706 {
7707 char *op_string; /* The string being parsed. */
7708 int got_a_float; /* Whether the operand is a float. */
4a1805b1 7709 int op_modifier; /* Operand modifier. */
64a0c779 7710 int is_mem; /* 1 if operand is memory reference. */
4eed87de
AM		 7711 int in_offset; /* >=1 if parsing operand of offset. */
7712 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 7713 const reg_entry *reg; /* Last register reference found. */
7714 char *disp; /* Displacement string being built. */
a724f0f4 7715 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 7716 };
7717
7718static struct intel_parser_s intel_parser;
7719
7720/* Token structure for parsing intel syntax. */
7721struct intel_token
7722 {
7723 int code; /* Token code. */
7724 const reg_entry *reg; /* Register entry for register tokens. */
7725 char *str; /* String representation. */
7726 };
7727
7728static struct intel_token cur_token, prev_token;
7729
50705ef4
AM		 7730/* Token codes for the intel parser. Since T_SHORT is already used
7731 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 7732#define T_NIL -1
7733#define T_CONST 1
7734#define T_REG 2
7735#define T_BYTE 3
7736#define T_WORD 4
9306ca4a
JB		 7737#define T_DWORD 5
7738#define T_FWORD 6
7739#define T_QWORD 7
7740#define T_TBYTE 8
7741#define T_XMMWORD 9
50705ef4 7742#undef T_SHORT
9306ca4a
JB		 7743#define T_SHORT 10
7744#define T_OFFSET 11
7745#define T_PTR 12
7746#define T_ID 13
7747#define T_SHL 14
7748#define T_SHR 15
64a0c779
DN		 7749
7750/* Prototypes for intel parser functions. */
e3bb37b5
L		 7751static int intel_match_token (int);
7752static void intel_putback_token (void);
7753static void intel_get_token (void);
7754static int intel_expr (void);
7755static int intel_e04 (void);
7756static int intel_e05 (void);
7757static int intel_e06 (void);
7758static int intel_e09 (void);
7759static int intel_e10 (void);
7760static int intel_e11 (void);
64a0c779 7761
64a0c779 7762static int
e3bb37b5 7763i386_intel_operand (char *operand_string, int got_a_float)
64a0c779
DN		 7764{
7765 int ret;
7766 char *p;
7767
a724f0f4
JB		 7768 p = intel_parser.op_string = xstrdup (operand_string);
7769 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
7770
7771 for (;;)
64a0c779 7772 {
a724f0f4
JB		 7773 /* Initialize token holders. */
7774 cur_token.code = prev_token.code = T_NIL;
7775 cur_token.reg = prev_token.reg = NULL;
7776 cur_token.str = prev_token.str = NULL;
7777
7778 /* Initialize parser structure. */
7779 intel_parser.got_a_float = got_a_float;
7780 intel_parser.op_modifier = 0;
7781 intel_parser.is_mem = 0;
7782 intel_parser.in_offset = 0;
7783 intel_parser.in_bracket = 0;
7784 intel_parser.reg = NULL;
7785 intel_parser.disp[0] = '\0';
7786 intel_parser.next_operand = NULL;
7787
7788 /* Read the first token and start the parser. */
7789 intel_get_token ();
7790 ret = intel_expr ();
7791
7792 if (!ret)
7793 break;
7794
9306ca4a
JB		 7795 if (cur_token.code != T_NIL)
7796 {
7797 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
7798 current_templates->start->name, cur_token.str);
7799 ret = 0;
7800 }
64a0c779
DN		 7801 /* If we found a memory reference, hand it over to i386_displacement
7802 to fill in the rest of the operand fields. */
9306ca4a 7803 else if (intel_parser.is_mem)
64a0c779
DN		 7804 {
7805 if ((i.mem_operands == 1
40fb9820 7806 && !current_templates->start->opcode_modifier.isstring)
64a0c779
DN		 7807 || i.mem_operands == 2)
7808 {
7809 as_bad (_("too many memory references for '%s'"),
7810 current_templates->start->name);
7811 ret = 0;
7812 }
7813 else
7814 {
7815 char *s = intel_parser.disp;
7816 i.mem_operands++;
7817
a724f0f4
JB		 7818 if (!quiet_warnings && intel_parser.is_mem < 0)
7819 /* See the comments in intel_bracket_expr. */
7820 as_warn (_("Treating `%s' as memory reference"), operand_string);
7821
64a0c779
DN		 7822 /* Add the displacement expression. */
7823 if (*s != '\0')
a4622f40
AM		 7824 ret = i386_displacement (s, s + strlen (s));
7825 if (ret)
a724f0f4
JB		 7826 {
7827 /* Swap base and index in 16-bit memory operands like
7828 [si+bx]. Since i386_index_check is also used in AT&T
7829 mode we have to do that here. */
7830 if (i.base_reg
7831 && i.index_reg
40fb9820
L		 7832 && i.base_reg->reg_type.bitfield.reg16
7833 && i.index_reg->reg_type.bitfield.reg16
a724f0f4
JB		 7834 && i.base_reg->reg_num >= 6
7835 && i.index_reg->reg_num < 6)
7836 {
7837 const reg_entry *base = i.index_reg;
7838
7839 i.index_reg = i.base_reg;
7840 i.base_reg = base;
7841 }
7842 ret = i386_index_check (operand_string);
7843 }
64a0c779
DN		 7844 }
7845 }
7846
7847 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 7848 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 7849 || intel_parser.reg == NULL)
7850 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 7851
7852 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
4eed87de 7853 ret = 0;
a724f0f4
JB		 7854 if (!ret || !intel_parser.next_operand)
7855 break;
7856 intel_parser.op_string = intel_parser.next_operand;
7857 this_operand = i.operands++;
64a0c779
DN		 7858 }
7859
7860 free (p);
7861 free (intel_parser.disp);
7862
7863 return ret;
7864}
7865
a724f0f4
JB		 7866#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
7867
7868/* expr e04 expr'
7869
7870 expr' cmpOp e04 expr'
7871 | Empty */
64a0c779 7872static int
e3bb37b5 7873intel_expr (void)
64a0c779 7874{
a724f0f4
JB		 7875 /* XXX Implement the comparison operators. */
7876 return intel_e04 ();
9306ca4a
JB		 7877}
7878
a724f0f4 7879/* e04 e05 e04'
9306ca4a 7880
a724f0f4 7881 e04' addOp e05 e04'
9306ca4a
JB		 7882 | Empty */
7883static int
e3bb37b5 7884intel_e04 (void)
9306ca4a 7885{
a724f0f4 7886 int nregs = -1;
9306ca4a 7887
a724f0f4 7888 for (;;)
9306ca4a 7889 {
a724f0f4
JB		 7890 if (!intel_e05())
7891 return 0;
9306ca4a 7892
a724f0f4
JB		 7893 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7894 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 7895
a724f0f4
JB		 7896 if (cur_token.code == '+')
7897 nregs = -1;
7898 else if (cur_token.code == '-')
7899 nregs = NUM_ADDRESS_REGS;
7900 else
7901 return 1;
64a0c779 7902
a724f0f4
JB		 7903 strcat (intel_parser.disp, cur_token.str);
7904 intel_match_token (cur_token.code);
7905 }
64a0c779
DN		 7906}
7907
64a0c779
DN		 7908/* e05 e06 e05'
7909
9306ca4a 7910 e05' binOp e06 e05'
64a0c779
DN		 7911 | Empty */
7912static int
e3bb37b5 7913intel_e05 (void)
64a0c779 7914{
a724f0f4 7915 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 7916
a724f0f4 7917 for (;;)
64a0c779 7918 {
a724f0f4
JB		 7919 if (!intel_e06())
7920 return 0;
7921
4eed87de
AM		 7922 if (cur_token.code == '&'
7923 || cur_token.code == '|'
7924 || cur_token.code == '^')
a724f0f4
JB		 7925 {
7926 char str[2];
7927
7928 str[0] = cur_token.code;
7929 str[1] = 0;
7930 strcat (intel_parser.disp, str);
7931 }
7932 else
7933 break;
9306ca4a 7934
64a0c779
DN		 7935 intel_match_token (cur_token.code);
7936
a724f0f4
JB		 7937 if (nregs < 0)
7938 nregs = ~nregs;
64a0c779 7939 }
a724f0f4
JB		 7940 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7941 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
7942 return 1;
4a1805b1 7943}
64a0c779
DN		 7944
7945/* e06 e09 e06'
7946
7947 e06' mulOp e09 e06'
b77a7acd 7948 | Empty */
64a0c779 7949static int
e3bb37b5 7950intel_e06 (void)
64a0c779 7951{
a724f0f4 7952 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 7953
a724f0f4 7954 for (;;)
64a0c779 7955 {
a724f0f4
JB		 7956 if (!intel_e09())
7957 return 0;
9306ca4a 7958
4eed87de
AM		 7959 if (cur_token.code == '*'
7960 || cur_token.code == '/'
7961 || cur_token.code == '%')
a724f0f4
JB		 7962 {
7963 char str[2];
9306ca4a 7964
a724f0f4
JB		 7965 str[0] = cur_token.code;
7966 str[1] = 0;
7967 strcat (intel_parser.disp, str);
7968 }
7969 else if (cur_token.code == T_SHL)
7970 strcat (intel_parser.disp, "<<");
7971 else if (cur_token.code == T_SHR)
7972 strcat (intel_parser.disp, ">>");
7973 else
7974 break;
9306ca4a 7975
64e74474 7976 intel_match_token (cur_token.code);
64a0c779 7977
a724f0f4
JB		 7978 if (nregs < 0)
7979 nregs = ~nregs;
64a0c779 7980 }
a724f0f4
JB		 7981 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7982 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
7983 return 1;
64a0c779
DN		 7984}
7985
a724f0f4
JB		 7986/* e09 OFFSET e09
7987 | SHORT e09
7988 | + e09
7989 | - e09
7990 | ~ e09
7991 | NOT e09
9306ca4a
JB		 7992 | e10 e09'
7993
64a0c779 7994 e09' PTR e10 e09'
b77a7acd 7995 | : e10 e09'
64a0c779
DN		 7996 | Empty */
7997static int
e3bb37b5 7998intel_e09 (void)
64a0c779 7999{
a724f0f4
JB		 8000 int nregs = ~NUM_ADDRESS_REGS;
8001 int in_offset = 0;
8002
8003 for (;;)
64a0c779 8004 {
a724f0f4
JB		 8005 /* Don't consume constants here. */
8006 if (cur_token.code == '+' || cur_token.code == '-')
8007 {
8008 /* Need to look one token ahead - if the next token
8009 is a constant, the current token is its sign. */
8010 int next_code;
8011
8012 intel_match_token (cur_token.code);
8013 next_code = cur_token.code;
8014 intel_putback_token ();
8015 if (next_code == T_CONST)
8016 break;
8017 }
8018
8019 /* e09 OFFSET e09 */
8020 if (cur_token.code == T_OFFSET)
8021 {
8022 if (!in_offset++)
8023 ++intel_parser.in_offset;
8024 }
8025
8026 /* e09 SHORT e09 */
8027 else if (cur_token.code == T_SHORT)
8028 intel_parser.op_modifier |= 1 << T_SHORT;
8029
8030 /* e09 + e09 */
8031 else if (cur_token.code == '+')
8032 strcat (intel_parser.disp, "+");
8033
8034 /* e09 - e09
8035 | ~ e09
8036 | NOT e09 */
8037 else if (cur_token.code == '-' || cur_token.code == '~')
8038 {
8039 char str[2];
64a0c779 8040
a724f0f4
JB		 8041 if (nregs < 0)
8042 nregs = ~nregs;
8043 str[0] = cur_token.code;
8044 str[1] = 0;
8045 strcat (intel_parser.disp, str);
8046 }
8047
8048 /* e09 e10 e09' */
8049 else
8050 break;
8051
8052 intel_match_token (cur_token.code);
64a0c779
DN		 8053 }
8054
a724f0f4 8055 for (;;)
9306ca4a 8056 {
a724f0f4
JB		 8057 if (!intel_e10 ())
8058 return 0;
9306ca4a 8059
a724f0f4
JB		 8060 /* e09' PTR e10 e09' */
8061 if (cur_token.code == T_PTR)
8062 {
8063 char suffix;
9306ca4a 8064
a724f0f4
JB		 8065 if (prev_token.code == T_BYTE)
8066 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 8067
a724f0f4
JB		 8068 else if (prev_token.code == T_WORD)
8069 {
8070 if (current_templates->start->name[0] == 'l'
8071 && current_templates->start->name[2] == 's'
8072 && current_templates->start->name[3] == 0)
8073 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8074 else if (intel_parser.got_a_float == 2) /* "fi..." */
8075 suffix = SHORT_MNEM_SUFFIX;
8076 else
8077 suffix = WORD_MNEM_SUFFIX;
8078 }
64a0c779 8079
a724f0f4
JB		 8080 else if (prev_token.code == T_DWORD)
8081 {
8082 if (current_templates->start->name[0] == 'l'
8083 && current_templates->start->name[2] == 's'
8084 && current_templates->start->name[3] == 0)
8085 suffix = WORD_MNEM_SUFFIX;
8086 else if (flag_code == CODE_16BIT
40fb9820
L		 8087 && (current_templates->start->opcode_modifier.jump
8088 || current_templates->start->opcode_modifier.jumpdword))
a724f0f4
JB		 8089 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8090 else if (intel_parser.got_a_float == 1) /* "f..." */
8091 suffix = SHORT_MNEM_SUFFIX;
8092 else
8093 suffix = LONG_MNEM_SUFFIX;
8094 }
9306ca4a 8095
a724f0f4
JB		 8096 else if (prev_token.code == T_FWORD)
8097 {
8098 if (current_templates->start->name[0] == 'l'
8099 && current_templates->start->name[2] == 's'
8100 && current_templates->start->name[3] == 0)
8101 suffix = LONG_MNEM_SUFFIX;
8102 else if (!intel_parser.got_a_float)
8103 {
8104 if (flag_code == CODE_16BIT)
8105 add_prefix (DATA_PREFIX_OPCODE);
8106 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8107 }
8108 else
8109 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8110 }
64a0c779 8111
a724f0f4
JB		 8112 else if (prev_token.code == T_QWORD)
8113 {
8114 if (intel_parser.got_a_float == 1) /* "f..." */
8115 suffix = LONG_MNEM_SUFFIX;
8116 else
8117 suffix = QWORD_MNEM_SUFFIX;
8118 }
64a0c779 8119
a724f0f4
JB		 8120 else if (prev_token.code == T_TBYTE)
8121 {
8122 if (intel_parser.got_a_float == 1)
8123 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8124 else
8125 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8126 }
9306ca4a 8127
a724f0f4 8128 else if (prev_token.code == T_XMMWORD)
9306ca4a 8129 {
a724f0f4
JB		 8130 /* XXX ignored for now, but accepted since gcc uses it */
8131 suffix = 0;
9306ca4a 8132 }
64a0c779 8133
f16b83df 8134 else
a724f0f4
JB		 8135 {
8136 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
8137 return 0;
8138 }
8139
435acd52
JB		 8140 /* Operands for jump/call using 'ptr' notation denote absolute
8141 addresses. */
40fb9820
L		 8142 if (current_templates->start->opcode_modifier.jump
8143 || current_templates->start->opcode_modifier.jumpdword)
8144 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 8145
a724f0f4
JB		 8146 if (current_templates->start->base_opcode == 0x8d /* lea */)
8147 ;
8148 else if (!i.suffix)
8149 i.suffix = suffix;
8150 else if (i.suffix != suffix)
8151 {
8152 as_bad (_("Conflicting operand modifiers"));
8153 return 0;
8154 }
64a0c779 8155
9306ca4a
JB		 8156 }
8157
a724f0f4
JB		 8158 /* e09' : e10 e09' */
8159 else if (cur_token.code == ':')
9306ca4a 8160 {
a724f0f4
JB		 8161 if (prev_token.code != T_REG)
8162 {
8163 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
8164 segment/group identifier (which we don't have), using comma
8165 as the operand separator there is even less consistent, since
8166 there all branches only have a single operand. */
8167 if (this_operand != 0
8168 || intel_parser.in_offset
8169 || intel_parser.in_bracket
40fb9820
L		 8170 || (!current_templates->start->opcode_modifier.jump
8171 && !current_templates->start->opcode_modifier.jumpdword
8172 && !current_templates->start->opcode_modifier.jumpintersegment
8173 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
a724f0f4
JB		 8174 return intel_match_token (T_NIL);
8175 /* Remember the start of the 2nd operand and terminate 1st
8176 operand here.
8177 XXX This isn't right, yet (when SSSS:OOOO is right operand of
8178 another expression), but it gets at least the simplest case
8179 (a plain number or symbol on the left side) right. */
8180 intel_parser.next_operand = intel_parser.op_string;
8181 *--intel_parser.op_string = '\0';
8182 return intel_match_token (':');
8183 }
9306ca4a 8184 }
64a0c779 8185
a724f0f4 8186 /* e09' Empty */
64a0c779 8187 else
a724f0f4 8188 break;
64a0c779 8189
a724f0f4
JB		 8190 intel_match_token (cur_token.code);
8191
8192 }
8193
8194 if (in_offset)
8195 {
8196 --intel_parser.in_offset;
8197 if (nregs < 0)
8198 nregs = ~nregs;
8199 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 8200 {
a724f0f4 8201 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 8202 return 0;
8203 }
a724f0f4
JB		 8204 intel_parser.op_modifier |= 1 << T_OFFSET;
8205 }
9306ca4a 8206
a724f0f4
JB		 8207 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8208 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
8209 return 1;
8210}
64a0c779 8211
a724f0f4 8212static int
e3bb37b5 8213intel_bracket_expr (void)
a724f0f4
JB		 8214{
8215 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
8216 const char *start = intel_parser.op_string;
8217 int len;
8218
8219 if (i.op[this_operand].regs)
8220 return intel_match_token (T_NIL);
8221
8222 intel_match_token ('[');
8223
8224 /* Mark as a memory operand only if it's not already known to be an
8225 offset expression. If it's an offset expression, we need to keep
8226 the brace in. */
8227 if (!intel_parser.in_offset)
8228 {
8229 ++intel_parser.in_bracket;
435acd52
JB		 8230
8231 /* Operands for jump/call inside brackets denote absolute addresses. */
40fb9820
L		 8232 if (current_templates->start->opcode_modifier.jump
8233 || current_templates->start->opcode_modifier.jumpdword)
8234 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 8235
a724f0f4
JB		 8236 /* Unfortunately gas always diverged from MASM in a respect that can't
8237 be easily fixed without risking to break code sequences likely to be
8238 encountered (the testsuite even check for this): MASM doesn't consider
8239 an expression inside brackets unconditionally as a memory reference.
8240 When that is e.g. a constant, an offset expression, or the sum of the
8241 two, this is still taken as a constant load. gas, however, always
8242 treated these as memory references. As a compromise, we'll try to make
8243 offset expressions inside brackets work the MASM way (since that's
8244 less likely to be found in real world code), but make constants alone
8245 continue to work the traditional gas way. In either case, issue a
8246 warning. */
8247 intel_parser.op_modifier &= ~was_offset;
64a0c779 8248 }
a724f0f4 8249 else
64e74474 8250 strcat (intel_parser.disp, "[");
a724f0f4
JB		 8251
8252 /* Add a '+' to the displacement string if necessary. */
8253 if (*intel_parser.disp != '\0'
8254 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
8255 strcat (intel_parser.disp, "+");
64a0c779 8256
a724f0f4
JB		 8257 if (intel_expr ()
8258 && (len = intel_parser.op_string - start - 1,
8259 intel_match_token (']')))
64a0c779 8260 {
a724f0f4
JB		 8261 /* Preserve brackets when the operand is an offset expression. */
8262 if (intel_parser.in_offset)
8263 strcat (intel_parser.disp, "]");
8264 else
8265 {
8266 --intel_parser.in_bracket;
8267 if (i.base_reg || i.index_reg)
8268 intel_parser.is_mem = 1;
8269 if (!intel_parser.is_mem)
8270 {
8271 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8272 /* Defer the warning until all of the operand was parsed. */
8273 intel_parser.is_mem = -1;
8274 else if (!quiet_warnings)
4eed87de
AM		 8275 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
8276 len, start, len, start);
a724f0f4
JB		 8277 }
8278 }
8279 intel_parser.op_modifier |= was_offset;
64a0c779 8280
a724f0f4 8281 return 1;
64a0c779 8282 }
a724f0f4 8283 return 0;
64a0c779
DN		 8284}
8285
8286/* e10 e11 e10'
8287
8288 e10' [ expr ] e10'
b77a7acd 8289 | Empty */
64a0c779 8290static int
e3bb37b5 8291intel_e10 (void)
64a0c779 8292{
a724f0f4
JB		 8293 if (!intel_e11 ())
8294 return 0;
64a0c779 8295
a724f0f4 8296 while (cur_token.code == '[')
64a0c779 8297 {
a724f0f4 8298 if (!intel_bracket_expr ())
21d6c4af 8299 return 0;
64a0c779
DN		 8300 }
8301
a724f0f4 8302 return 1;
64a0c779
DN		 8303}
8304
64a0c779 8305/* e11 ( expr )
b77a7acd 8306 | [ expr ]
64a0c779
DN		 8307 | BYTE
8308 | WORD
8309 | DWORD
9306ca4a 8310 | FWORD
64a0c779 8311 | QWORD
9306ca4a
JB		 8312 | TBYTE
8313 | OWORD
8314 | XMMWORD
4a1805b1 8315 | $
64a0c779
DN		 8316 | .
8317 | register
8318 | id
8319 | constant */
8320static int
e3bb37b5 8321intel_e11 (void)
64a0c779 8322{
a724f0f4 8323 switch (cur_token.code)
64a0c779 8324 {
a724f0f4
JB		 8325 /* e11 ( expr ) */
8326 case '(':
64a0c779
DN		 8327 intel_match_token ('(');
8328 strcat (intel_parser.disp, "(");
8329
8330 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 8331 {
8332 strcat (intel_parser.disp, ")");
8333 return 1;
8334 }
a724f0f4 8335 return 0;
4a1805b1 8336
a724f0f4
JB		 8337 /* e11 [ expr ] */
8338 case '[':
a724f0f4 8339 return intel_bracket_expr ();
64a0c779 8340
a724f0f4
JB		 8341 /* e11 $
8342 | . */
8343 case '.':
64a0c779
DN		 8344 strcat (intel_parser.disp, cur_token.str);
8345 intel_match_token (cur_token.code);
21d6c4af
DN		 8346
8347 /* Mark as a memory operand only if it's not already known to be an
8348 offset expression. */
a724f0f4 8349 if (!intel_parser.in_offset)
21d6c4af 8350 intel_parser.is_mem = 1;
64a0c779
DN		 8351
8352 return 1;
64a0c779 8353
a724f0f4
JB		 8354 /* e11 register */
8355 case T_REG:
8356 {
8357 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 8358
a724f0f4 8359 intel_match_token (T_REG);
64a0c779 8360
a724f0f4
JB		 8361 /* Check for segment change. */
8362 if (cur_token.code == ':')
8363 {
40fb9820
L		 8364 if (!reg->reg_type.bitfield.sreg2
8365 && !reg->reg_type.bitfield.sreg3)
a724f0f4 8366 {
4eed87de
AM		 8367 as_bad (_("`%s' is not a valid segment register"),
8368 reg->reg_name);
a724f0f4
JB		 8369 return 0;
8370 }
8371 else if (i.seg[i.mem_operands])
8372 as_warn (_("Extra segment override ignored"));
8373 else
8374 {
8375 if (!intel_parser.in_offset)
8376 intel_parser.is_mem = 1;
8377 switch (reg->reg_num)
8378 {
8379 case 0:
8380 i.seg[i.mem_operands] = &es;
8381 break;
8382 case 1:
8383 i.seg[i.mem_operands] = &cs;
8384 break;
8385 case 2:
8386 i.seg[i.mem_operands] = &ss;
8387 break;
8388 case 3:
8389 i.seg[i.mem_operands] = &ds;
8390 break;
8391 case 4:
8392 i.seg[i.mem_operands] = &fs;
8393 break;
8394 case 5:
8395 i.seg[i.mem_operands] = &gs;
8396 break;
8397 }
8398 }
8399 }
64a0c779 8400
a724f0f4
JB		 8401 /* Not a segment register. Check for register scaling. */
8402 else if (cur_token.code == '*')
8403 {
8404 if (!intel_parser.in_bracket)
8405 {
8406 as_bad (_("Register scaling only allowed in memory operands"));
8407 return 0;
8408 }
64a0c779 8409
40fb9820 8410 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
a724f0f4
JB		 8411 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
8412 else if (i.index_reg)
8413 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 8414
a724f0f4
JB		 8415 /* What follows must be a valid scale. */
8416 intel_match_token ('*');
8417 i.index_reg = reg;
40fb9820 8418 i.types[this_operand].bitfield.baseindex = 1;
64a0c779 8419
a724f0f4
JB		 8420 /* Set the scale after setting the register (otherwise,
8421 i386_scale will complain) */
8422 if (cur_token.code == '+' || cur_token.code == '-')
8423 {
8424 char *str, sign = cur_token.code;
8425 intel_match_token (cur_token.code);
8426 if (cur_token.code != T_CONST)
8427 {
8428 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8429 cur_token.str);
8430 return 0;
8431 }
8432 str = (char *) xmalloc (strlen (cur_token.str) + 2);
8433 strcpy (str + 1, cur_token.str);
8434 *str = sign;
8435 if (!i386_scale (str))
8436 return 0;
8437 free (str);
8438 }
8439 else if (!i386_scale (cur_token.str))
64a0c779 8440 return 0;
a724f0f4
JB		 8441 intel_match_token (cur_token.code);
8442 }
64a0c779 8443
a724f0f4
JB		 8444 /* No scaling. If this is a memory operand, the register is either a
8445 base register (first occurrence) or an index register (second
8446 occurrence). */
7b0441f6 8447 else if (intel_parser.in_bracket)
a724f0f4 8448 {
64a0c779 8449
a724f0f4
JB		 8450 if (!i.base_reg)
8451 i.base_reg = reg;
8452 else if (!i.index_reg)
8453 i.index_reg = reg;
8454 else
8455 {
8456 as_bad (_("Too many register references in memory operand"));
8457 return 0;
8458 }
64a0c779 8459
40fb9820 8460 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4 8461 }
4a1805b1 8462
4d1bb795
JB		 8463 /* It's neither base nor index. */
8464 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4 8465 {
40fb9820
L		 8466 i386_operand_type temp = reg->reg_type;
8467 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8468 i.types[this_operand] = operand_type_or (i.types[this_operand],
8469 temp);
a724f0f4
JB		 8470 i.op[this_operand].regs = reg;
8471 i.reg_operands++;
8472 }
8473 else
8474 {
8475 as_bad (_("Invalid use of register"));
8476 return 0;
8477 }
64a0c779 8478
a724f0f4
JB		 8479 /* Since registers are not part of the displacement string (except
8480 when we're parsing offset operands), we may need to remove any
8481 preceding '+' from the displacement string. */
8482 if (*intel_parser.disp != '\0'
8483 && !intel_parser.in_offset)
8484 {
8485 char *s = intel_parser.disp;
8486 s += strlen (s) - 1;
8487 if (*s == '+')
8488 *s = '\0';
8489 }
4a1805b1 8490
a724f0f4
JB		 8491 return 1;
8492 }
8493
8494 /* e11 BYTE
8495 | WORD
8496 | DWORD
8497 | FWORD
8498 | QWORD
8499 | TBYTE
8500 | OWORD
8501 | XMMWORD */
8502 case T_BYTE:
8503 case T_WORD:
8504 case T_DWORD:
8505 case T_FWORD:
8506 case T_QWORD:
8507 case T_TBYTE:
8508 case T_XMMWORD:
8509 intel_match_token (cur_token.code);
64a0c779 8510
a724f0f4
JB		 8511 if (cur_token.code == T_PTR)
8512 return 1;
8513
8514 /* It must have been an identifier. */
8515 intel_putback_token ();
8516 cur_token.code = T_ID;
8517 /* FALLTHRU */
8518
8519 /* e11 id
8520 | constant */
8521 case T_ID:
8522 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 8523 {
8524 symbolS *symbolP;
8525
a724f0f4
JB		 8526 /* The identifier represents a memory reference only if it's not
8527 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 8528 symbolP = symbol_find(cur_token.str);
8529 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
8530 intel_parser.is_mem = 1;
8531 }
a724f0f4 8532 /* FALLTHRU */
64a0c779 8533
a724f0f4
JB		 8534 case T_CONST:
8535 case '-':
8536 case '+':
8537 {
8538 char *save_str, sign = 0;
64a0c779 8539
a724f0f4
JB		 8540 /* Allow constants that start with `+' or `-'. */
8541 if (cur_token.code == '-' || cur_token.code == '+')
8542 {
8543 sign = cur_token.code;
8544 intel_match_token (cur_token.code);
8545 if (cur_token.code != T_CONST)
8546 {
8547 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8548 cur_token.str);
8549 return 0;
8550 }
8551 }
64a0c779 8552
a724f0f4
JB		 8553 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
8554 strcpy (save_str + !!sign, cur_token.str);
8555 if (sign)
8556 *save_str = sign;
64a0c779 8557
a724f0f4
JB		 8558 /* Get the next token to check for register scaling. */
8559 intel_match_token (cur_token.code);
64a0c779 8560
4eed87de
AM		 8561 /* Check if this constant is a scaling factor for an
8562 index register. */
a724f0f4
JB		 8563 if (cur_token.code == '*')
8564 {
8565 if (intel_match_token ('*') && cur_token.code == T_REG)
8566 {
8567 const reg_entry *reg = cur_token.reg;
8568
8569 if (!intel_parser.in_bracket)
8570 {
4eed87de
AM		 8571 as_bad (_("Register scaling only allowed "
8572 "in memory operands"));
a724f0f4
JB		 8573 return 0;
8574 }
8575
4eed87de
AM		 8576 /* Disallow things like [1*si].
8577 sp and esp are invalid as index. */
40fb9820 8578 if (reg->reg_type.bitfield.reg16)
4eed87de 8579 reg = i386_regtab + REGNAM_AX + 4;
a724f0f4 8580 else if (i.index_reg)
4eed87de 8581 reg = i386_regtab + REGNAM_EAX + 4;
a724f0f4
JB		 8582
8583 /* The constant is followed by `* reg', so it must be
8584 a valid scale. */
8585 i.index_reg = reg;
40fb9820 8586 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4
JB		 8587
8588 /* Set the scale after setting the register (otherwise,
8589 i386_scale will complain) */
8590 if (!i386_scale (save_str))
64a0c779 8591 return 0;
a724f0f4
JB		 8592 intel_match_token (T_REG);
8593
8594 /* Since registers are not part of the displacement
8595 string, we may need to remove any preceding '+' from
8596 the displacement string. */
8597 if (*intel_parser.disp != '\0')
8598 {
8599 char *s = intel_parser.disp;
8600 s += strlen (s) - 1;
8601 if (*s == '+')
8602 *s = '\0';
8603 }
8604
8605 free (save_str);
8606
8607 return 1;
8608 }
64a0c779 8609
a724f0f4
JB		 8610 /* The constant was not used for register scaling. Since we have
8611 already consumed the token following `*' we now need to put it
8612 back in the stream. */
64a0c779 8613 intel_putback_token ();
a724f0f4 8614 }
64a0c779 8615
a724f0f4
JB		 8616 /* Add the constant to the displacement string. */
8617 strcat (intel_parser.disp, save_str);
8618 free (save_str);
64a0c779 8619
a724f0f4
JB		 8620 return 1;
8621 }
64a0c779
DN		 8622 }
8623
64a0c779
DN		 8624 as_bad (_("Unrecognized token '%s'"), cur_token.str);
8625 return 0;
8626}
8627
64a0c779
DN		 8628/* Match the given token against cur_token. If they match, read the next
8629 token from the operand string. */
8630static int
e3bb37b5 8631intel_match_token (int code)
64a0c779
DN		 8632{
8633 if (cur_token.code == code)
8634 {
8635 intel_get_token ();
8636 return 1;
8637 }
8638 else
8639 {
0477af35 8640 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 8641 return 0;
8642 }
8643}
8644
64a0c779
DN		 8645/* Read a new token from intel_parser.op_string and store it in cur_token. */
8646static void
e3bb37b5 8647intel_get_token (void)
64a0c779
DN		 8648{
8649 char *end_op;
8650 const reg_entry *reg;
8651 struct intel_token new_token;
8652
8653 new_token.code = T_NIL;
8654 new_token.reg = NULL;
8655 new_token.str = NULL;
8656
4a1805b1 8657 /* Free the memory allocated to the previous token and move
64a0c779
DN		 8658 cur_token to prev_token. */
8659 if (prev_token.str)
8660 free (prev_token.str);
8661
8662 prev_token = cur_token;
8663
8664 /* Skip whitespace. */
8665 while (is_space_char (*intel_parser.op_string))
8666 intel_parser.op_string++;
8667
8668 /* Return an empty token if we find nothing else on the line. */
8669 if (*intel_parser.op_string == '\0')
8670 {
8671 cur_token = new_token;
8672 return;
8673 }
8674
8675 /* The new token cannot be larger than the remainder of the operand
8676 string. */
a724f0f4 8677 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 8678 new_token.str[0] = '\0';
8679
8680 if (strchr ("0123456789", *intel_parser.op_string))
8681 {
8682 char *p = new_token.str;
8683 char *q = intel_parser.op_string;
8684 new_token.code = T_CONST;
8685
8686 /* Allow any kind of identifier char to encompass floating point and
8687 hexadecimal numbers. */
8688 while (is_identifier_char (*q))
8689 *p++ = *q++;
8690 *p = '\0';
8691
8692 /* Recognize special symbol names [0-9][bf]. */
8693 if (strlen (intel_parser.op_string) == 2
4a1805b1 8694 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 8695 || intel_parser.op_string[1] == 'f'))
8696 new_token.code = T_ID;
8697 }
8698
4d1bb795 8699 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 8700 {
4d1bb795
JB		 8701 size_t len = end_op - intel_parser.op_string;
8702
64a0c779
DN		 8703 new_token.code = T_REG;
8704 new_token.reg = reg;
8705
4d1bb795
JB		 8706 memcpy (new_token.str, intel_parser.op_string, len);
8707 new_token.str[len] = '\0';
64a0c779
DN		 8708 }
8709
8710 else if (is_identifier_char (*intel_parser.op_string))
8711 {
8712 char *p = new_token.str;
8713 char *q = intel_parser.op_string;
8714
8715 /* A '.' or '$' followed by an identifier char is an identifier.
8716 Otherwise, it's operator '.' followed by an expression. */
8717 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
8718 {
9306ca4a
JB		 8719 new_token.code = '.';
8720 new_token.str[0] = '.';
64a0c779
DN		 8721 new_token.str[1] = '\0';
8722 }
8723 else
8724 {
8725 while (is_identifier_char (*q) || *q == '@')
8726 *p++ = *q++;
8727 *p = '\0';
8728
9306ca4a
JB		 8729 if (strcasecmp (new_token.str, "NOT") == 0)
8730 new_token.code = '~';
8731
8732 else if (strcasecmp (new_token.str, "MOD") == 0)
8733 new_token.code = '%';
8734
8735 else if (strcasecmp (new_token.str, "AND") == 0)
8736 new_token.code = '&';
8737
8738 else if (strcasecmp (new_token.str, "OR") == 0)
8739 new_token.code = '|';
8740
8741 else if (strcasecmp (new_token.str, "XOR") == 0)
8742 new_token.code = '^';
8743
8744 else if (strcasecmp (new_token.str, "SHL") == 0)
8745 new_token.code = T_SHL;
8746
8747 else if (strcasecmp (new_token.str, "SHR") == 0)
8748 new_token.code = T_SHR;
8749
8750 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 8751 new_token.code = T_BYTE;
8752
8753 else if (strcasecmp (new_token.str, "WORD") == 0)
8754 new_token.code = T_WORD;
8755
8756 else if (strcasecmp (new_token.str, "DWORD") == 0)
8757 new_token.code = T_DWORD;
8758
9306ca4a
JB		 8759 else if (strcasecmp (new_token.str, "FWORD") == 0)
8760 new_token.code = T_FWORD;
8761
64a0c779
DN		 8762 else if (strcasecmp (new_token.str, "QWORD") == 0)
8763 new_token.code = T_QWORD;
8764
9306ca4a
JB		 8765 else if (strcasecmp (new_token.str, "TBYTE") == 0
8766 /* XXX remove (gcc still uses it) */
8767 || strcasecmp (new_token.str, "XWORD") == 0)
8768 new_token.code = T_TBYTE;
8769
8770 else if (strcasecmp (new_token.str, "XMMWORD") == 0
8771 || strcasecmp (new_token.str, "OWORD") == 0)
8772 new_token.code = T_XMMWORD;
64a0c779
DN		 8773
8774 else if (strcasecmp (new_token.str, "PTR") == 0)
8775 new_token.code = T_PTR;
8776
8777 else if (strcasecmp (new_token.str, "SHORT") == 0)
8778 new_token.code = T_SHORT;
8779
8780 else if (strcasecmp (new_token.str, "OFFSET") == 0)
8781 {
8782 new_token.code = T_OFFSET;
8783
8784 /* ??? This is not mentioned in the MASM grammar but gcc
8785 makes use of it with -mintel-syntax. OFFSET may be
8786 followed by FLAT: */
8787 if (strncasecmp (q, " FLAT:", 6) == 0)
8788 strcat (new_token.str, " FLAT:");
8789 }
8790
8791 /* ??? This is not mentioned in the MASM grammar. */
8792 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 8793 {
8794 new_token.code = T_OFFSET;
8795 if (*q == ':')
8796 strcat (new_token.str, ":");
8797 else
8798 as_bad (_("`:' expected"));
8799 }
64a0c779
DN		 8800
8801 else
8802 new_token.code = T_ID;
8803 }
8804 }
8805
9306ca4a
JB		 8806 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
8807 {
8808 new_token.code = *intel_parser.op_string;
8809 new_token.str[0] = *intel_parser.op_string;
8810 new_token.str[1] = '\0';
8811 }
8812
8813 else if (strchr ("<>", *intel_parser.op_string)
8814 && *intel_parser.op_string == *(intel_parser.op_string + 1))
8815 {
8816 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
8817 new_token.str[0] = *intel_parser.op_string;
8818 new_token.str[1] = *intel_parser.op_string;
8819 new_token.str[2] = '\0';
8820 }
8821
64a0c779 8822 else
0477af35 8823 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 8824
8825 intel_parser.op_string += strlen (new_token.str);
8826 cur_token = new_token;
8827}
8828
64a0c779
DN		 8829/* Put cur_token back into the token stream and make cur_token point to
8830 prev_token. */
8831static void
e3bb37b5 8832intel_putback_token (void)
64a0c779 8833{
a724f0f4
JB		 8834 if (cur_token.code != T_NIL)
8835 {
8836 intel_parser.op_string -= strlen (cur_token.str);
8837 free (cur_token.str);
8838 }
64a0c779 8839 cur_token = prev_token;
4a1805b1 8840
64a0c779
DN		 8841 /* Forget prev_token. */
8842 prev_token.code = T_NIL;
8843 prev_token.reg = NULL;
8844 prev_token.str = NULL;
8845}
54cfded0 8846
a4447b93 8847int
1df69f4f 8848tc_x86_regname_to_dw2regnum (char *regname)
54cfded0
AM		 8849{
8850 unsigned int regnum;
8851 unsigned int regnames_count;
089dfecd 8852 static const char *const regnames_32[] =
54cfded0 8853 {
a4447b93
RH		 8854 "eax", "ecx", "edx", "ebx",
8855 "esp", "ebp", "esi", "edi",
089dfecd
JB		 8856 "eip", "eflags", NULL,
8857 "st0", "st1", "st2", "st3",
8858 "st4", "st5", "st6", "st7",
8859 NULL, NULL,
8860 "xmm0", "xmm1", "xmm2", "xmm3",
8861 "xmm4", "xmm5", "xmm6", "xmm7",
8862 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 8863 "mm4", "mm5", "mm6", "mm7",
8864 "fcw", "fsw", "mxcsr",
8865 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8866 "tr", "ldtr"
54cfded0 8867 };
089dfecd 8868 static const char *const regnames_64[] =
54cfded0 8869 {
089dfecd
JB		 8870 "rax", "rdx", "rcx", "rbx",
8871 "rsi", "rdi", "rbp", "rsp",
8872 "r8", "r9", "r10", "r11",
54cfded0 8873 "r12", "r13", "r14", "r15",
089dfecd
JB		 8874 "rip",
8875 "xmm0", "xmm1", "xmm2", "xmm3",
8876 "xmm4", "xmm5", "xmm6", "xmm7",
8877 "xmm8", "xmm9", "xmm10", "xmm11",
8878 "xmm12", "xmm13", "xmm14", "xmm15",
8879 "st0", "st1", "st2", "st3",
8880 "st4", "st5", "st6", "st7",
8881 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 8882 "mm4", "mm5", "mm6", "mm7",
8883 "rflags",
8884 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8885 "fs.base", "gs.base", NULL, NULL,
8886 "tr", "ldtr",
8887 "mxcsr", "fcw", "fsw"
54cfded0 8888 };
089dfecd 8889 const char *const *regnames;
54cfded0
AM		 8890
8891 if (flag_code == CODE_64BIT)
8892 {
8893 regnames = regnames_64;
0cea6190 8894 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 8895 }
8896 else
8897 {
8898 regnames = regnames_32;
0cea6190 8899 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 8900 }
8901
8902 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 8903 if (regnames[regnum] != NULL
8904 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 8905 return regnum;
8906
54cfded0
AM		 8907 return -1;
8908}
8909
8910void
8911tc_x86_frame_initial_instructions (void)
8912{
a4447b93
RH		 8913 static unsigned int sp_regno;
8914
8915 if (!sp_regno)
8916 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
8917 ? "rsp" : "esp");
8918
8919 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
8920 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 8921}
d2b2c203
DJ		 8922
8923int
8924i386_elf_section_type (const char *str, size_t len)
8925{
8926 if (flag_code == CODE_64BIT
8927 && len == sizeof ("unwind") - 1
8928 && strncmp (str, "unwind", 6) == 0)
8929 return SHT_X86_64_UNWIND;
8930
8931 return -1;
8932}
bb41ade5
AM		 8933
8934#ifdef TE_PE
8935void
8936tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8937{
8938 expressionS expr;
8939
8940 expr.X_op = O_secrel;
8941 expr.X_add_symbol = symbol;
8942 expr.X_add_number = 0;
8943 emit_expr (&expr, size);
8944}
8945#endif
3b22753a
L		 8946
8947#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8948/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8949
8950int
8951x86_64_section_letter (int letter, char **ptr_msg)
8952{
8953 if (flag_code == CODE_64BIT)
8954 {
8955 if (letter == 'l')
8956 return SHF_X86_64_LARGE;
8957
8958 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 8959 }
3b22753a 8960 else
64e74474 8961 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 8962 return -1;
8963}
8964
8965int
8966x86_64_section_word (char *str, size_t len)
8967{
8620418b 8968 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 8969 return SHF_X86_64_LARGE;
8970
8971 return -1;
8972}
8973
8974static void
8975handle_large_common (int small ATTRIBUTE_UNUSED)
8976{
8977 if (flag_code != CODE_64BIT)
8978 {
8979 s_comm_internal (0, elf_common_parse);
8980 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8981 }
8982 else
8983 {
8984 static segT lbss_section;
8985 asection *saved_com_section_ptr = elf_com_section_ptr;
8986 asection *saved_bss_section = bss_section;
8987
8988 if (lbss_section == NULL)
8989 {
8990 flagword applicable;
8991 segT seg = now_seg;
8992 subsegT subseg = now_subseg;
8993
8994 /* The .lbss section is for local .largecomm symbols. */
8995 lbss_section = subseg_new (".lbss", 0);
8996 applicable = bfd_applicable_section_flags (stdoutput);
8997 bfd_set_section_flags (stdoutput, lbss_section,
8998 applicable & SEC_ALLOC);
8999 seg_info (lbss_section)->bss = 1;
9000
9001 subseg_set (seg, subseg);
9002 }
9003
9004 elf_com_section_ptr = &_bfd_elf_large_com_section;
9005 bss_section = lbss_section;
9006
9007 s_comm_internal (0, elf_common_parse);
9008
9009 elf_com_section_ptr = saved_com_section_ptr;
9010 bss_section = saved_bss_section;
9011 }
9012}
9013#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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