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b534c6d3 | 1 | /* tc-i386.c -- Assemble code for the Intel 80386 |
250d07de | 2 | Copyright (C) 1989-2021 Free Software Foundation, Inc. |
252b5132 RH |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
19 | 02110-1301, USA. */ | |
252b5132 | 20 | |
47926f60 KH |
21 | /* Intel 80386 machine specific gas. |
22 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 23 | x86_64 support by Jan Hubicka (jh@suse.cz) |
0f10071e | 24 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
47926f60 KH |
25 | Bugs & suggestions are completely welcome. This is free software. |
26 | Please help us make it better. */ | |
252b5132 | 27 | |
252b5132 | 28 | #include "as.h" |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | #include "subsegs.h" |
316e2c05 | 31 | #include "dwarf2dbg.h" |
54cfded0 | 32 | #include "dw2gencfi.h" |
d2b2c203 | 33 | #include "elf/x86-64.h" |
40fb9820 | 34 | #include "opcodes/i386-init.h" |
41fd2579 | 35 | #include <limits.h> |
41fd2579 | 36 | |
c3332e24 | 37 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 38 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
39 | #endif |
40 | ||
29b0f896 AM |
41 | #ifndef DEFAULT_ARCH |
42 | #define DEFAULT_ARCH "i386" | |
246fcdee | 43 | #endif |
252b5132 | 44 | |
edde18a5 AM |
45 | #ifndef INLINE |
46 | #if __GNUC__ >= 2 | |
47 | #define INLINE __inline__ | |
48 | #else | |
49 | #define INLINE | |
50 | #endif | |
51 | #endif | |
52 | ||
6305a203 L |
53 | /* Prefixes will be emitted in the order defined below. |
54 | WAIT_PREFIX must be the first prefix since FWAIT is really is an | |
55 | instruction, and so must come before any prefixes. | |
56 | The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, | |
42164a71 | 57 | REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */ |
6305a203 L |
58 | #define WAIT_PREFIX 0 |
59 | #define SEG_PREFIX 1 | |
60 | #define ADDR_PREFIX 2 | |
61 | #define DATA_PREFIX 3 | |
c32fa91d | 62 | #define REP_PREFIX 4 |
42164a71 | 63 | #define HLE_PREFIX REP_PREFIX |
7e8b059b | 64 | #define BND_PREFIX REP_PREFIX |
c32fa91d | 65 | #define LOCK_PREFIX 5 |
4e9ac44a L |
66 | #define REX_PREFIX 6 /* must come last. */ |
67 | #define MAX_PREFIXES 7 /* max prefixes per opcode */ | |
6305a203 L |
68 | |
69 | /* we define the syntax here (modulo base,index,scale syntax) */ | |
70 | #define REGISTER_PREFIX '%' | |
71 | #define IMMEDIATE_PREFIX '$' | |
72 | #define ABSOLUTE_PREFIX '*' | |
73 | ||
74 | /* these are the instruction mnemonic suffixes in AT&T syntax or | |
75 | memory operand size in Intel syntax. */ | |
76 | #define WORD_MNEM_SUFFIX 'w' | |
77 | #define BYTE_MNEM_SUFFIX 'b' | |
78 | #define SHORT_MNEM_SUFFIX 's' | |
79 | #define LONG_MNEM_SUFFIX 'l' | |
80 | #define QWORD_MNEM_SUFFIX 'q' | |
6305a203 L |
81 | /* Intel Syntax. Use a non-ascii letter since since it never appears |
82 | in instructions. */ | |
83 | #define LONG_DOUBLE_MNEM_SUFFIX '\1' | |
84 | ||
85 | #define END_OF_INSN '\0' | |
86 | ||
79dec6b7 JB |
87 | /* This matches the C -> StaticRounding alias in the opcode table. */ |
88 | #define commutative staticrounding | |
89 | ||
6305a203 L |
90 | /* |
91 | 'templates' is for grouping together 'template' structures for opcodes | |
92 | of the same name. This is only used for storing the insns in the grand | |
93 | ole hash table of insns. | |
94 | The templates themselves start at START and range up to (but not including) | |
95 | END. | |
96 | */ | |
97 | typedef struct | |
98 | { | |
d3ce72d0 NC |
99 | const insn_template *start; |
100 | const insn_template *end; | |
6305a203 L |
101 | } |
102 | templates; | |
103 | ||
104 | /* 386 operand encoding bytes: see 386 book for details of this. */ | |
105 | typedef struct | |
106 | { | |
107 | unsigned int regmem; /* codes register or memory operand */ | |
108 | unsigned int reg; /* codes register operand (or extended opcode) */ | |
109 | unsigned int mode; /* how to interpret regmem & reg */ | |
110 | } | |
111 | modrm_byte; | |
112 | ||
113 | /* x86-64 extension prefix. */ | |
114 | typedef int rex_byte; | |
115 | ||
6305a203 L |
116 | /* 386 opcode byte to code indirect addressing. */ |
117 | typedef struct | |
118 | { | |
119 | unsigned base; | |
120 | unsigned index; | |
121 | unsigned scale; | |
122 | } | |
123 | sib_byte; | |
124 | ||
6305a203 L |
125 | /* x86 arch names, types and features */ |
126 | typedef struct | |
127 | { | |
128 | const char *name; /* arch name */ | |
8a2c8fef | 129 | unsigned int len; /* arch string length */ |
6305a203 L |
130 | enum processor_type type; /* arch type */ |
131 | i386_cpu_flags flags; /* cpu feature flags */ | |
8a2c8fef | 132 | unsigned int skip; /* show_arch should skip this. */ |
6305a203 L |
133 | } |
134 | arch_entry; | |
135 | ||
293f5f65 L |
136 | /* Used to turn off indicated flags. */ |
137 | typedef struct | |
138 | { | |
139 | const char *name; /* arch name */ | |
140 | unsigned int len; /* arch string length */ | |
141 | i386_cpu_flags flags; /* cpu feature flags */ | |
142 | } | |
143 | noarch_entry; | |
144 | ||
78f12dd3 | 145 | static void update_code_flag (int, int); |
e3bb37b5 L |
146 | static void set_code_flag (int); |
147 | static void set_16bit_gcc_code_flag (int); | |
148 | static void set_intel_syntax (int); | |
1efbbeb4 | 149 | static void set_intel_mnemonic (int); |
db51cc60 | 150 | static void set_allow_index_reg (int); |
7bab8ab5 | 151 | static void set_check (int); |
e3bb37b5 | 152 | static void set_cpu_arch (int); |
6482c264 | 153 | #ifdef TE_PE |
e3bb37b5 | 154 | static void pe_directive_secrel (int); |
6482c264 | 155 | #endif |
e3bb37b5 L |
156 | static void signed_cons (int); |
157 | static char *output_invalid (int c); | |
ee86248c JB |
158 | static int i386_finalize_immediate (segT, expressionS *, i386_operand_type, |
159 | const char *); | |
160 | static int i386_finalize_displacement (segT, expressionS *, i386_operand_type, | |
161 | const char *); | |
a7619375 | 162 | static int i386_att_operand (char *); |
e3bb37b5 | 163 | static int i386_intel_operand (char *, int); |
ee86248c JB |
164 | static int i386_intel_simplify (expressionS *); |
165 | static int i386_intel_parse_name (const char *, expressionS *); | |
e3bb37b5 L |
166 | static const reg_entry *parse_register (char *, char **); |
167 | static char *parse_insn (char *, char *); | |
168 | static char *parse_operands (char *, const char *); | |
169 | static void swap_operands (void); | |
783c187b | 170 | static void swap_2_operands (unsigned int, unsigned int); |
48bcea9f | 171 | static enum flag_code i386_addressing_mode (void); |
e3bb37b5 L |
172 | static void optimize_imm (void); |
173 | static void optimize_disp (void); | |
83b16ac6 | 174 | static const insn_template *match_template (char); |
e3bb37b5 L |
175 | static int check_string (void); |
176 | static int process_suffix (void); | |
177 | static int check_byte_reg (void); | |
178 | static int check_long_reg (void); | |
179 | static int check_qword_reg (void); | |
180 | static int check_word_reg (void); | |
181 | static int finalize_imm (void); | |
182 | static int process_operands (void); | |
5e042380 | 183 | static const reg_entry *build_modrm_byte (void); |
e3bb37b5 L |
184 | static void output_insn (void); |
185 | static void output_imm (fragS *, offsetT); | |
186 | static void output_disp (fragS *, offsetT); | |
29b0f896 | 187 | #ifndef I386COFF |
e3bb37b5 | 188 | static void s_bss (int); |
252b5132 | 189 | #endif |
17d4e2a2 L |
190 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
191 | static void handle_large_common (int small ATTRIBUTE_UNUSED); | |
b4a3a7b4 L |
192 | |
193 | /* GNU_PROPERTY_X86_ISA_1_USED. */ | |
194 | static unsigned int x86_isa_1_used; | |
195 | /* GNU_PROPERTY_X86_FEATURE_2_USED. */ | |
196 | static unsigned int x86_feature_2_used; | |
197 | /* Generate x86 used ISA and feature properties. */ | |
198 | static unsigned int x86_used_note = DEFAULT_X86_USED_NOTE; | |
17d4e2a2 | 199 | #endif |
252b5132 | 200 | |
a847613f | 201 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 202 | |
8a6fb3f9 JB |
203 | /* parse_register() returns this when a register alias cannot be used. */ |
204 | static const reg_entry bad_reg = { "<bad>", OPERAND_TYPE_NONE, 0, 0, | |
205 | { Dw2Inval, Dw2Inval } }; | |
206 | ||
34684862 | 207 | static const reg_entry *reg_eax; |
5e042380 JB |
208 | static const reg_entry *reg_ds; |
209 | static const reg_entry *reg_es; | |
210 | static const reg_entry *reg_ss; | |
6288d05f | 211 | static const reg_entry *reg_st0; |
6225c532 JB |
212 | static const reg_entry *reg_k0; |
213 | ||
c0f3af97 L |
214 | /* VEX prefix. */ |
215 | typedef struct | |
216 | { | |
43234a1e L |
217 | /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */ |
218 | unsigned char bytes[4]; | |
c0f3af97 L |
219 | unsigned int length; |
220 | /* Destination or source register specifier. */ | |
221 | const reg_entry *register_specifier; | |
222 | } vex_prefix; | |
223 | ||
252b5132 | 224 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 225 | i386_insn. */ |
252b5132 | 226 | |
520dc8e8 AM |
227 | union i386_op |
228 | { | |
229 | expressionS *disps; | |
230 | expressionS *imms; | |
231 | const reg_entry *regs; | |
232 | }; | |
233 | ||
a65babc9 L |
234 | enum i386_error |
235 | { | |
86e026a4 | 236 | operand_size_mismatch, |
a65babc9 L |
237 | operand_type_mismatch, |
238 | register_type_mismatch, | |
239 | number_of_operands_mismatch, | |
240 | invalid_instruction_suffix, | |
241 | bad_imm4, | |
a65babc9 L |
242 | unsupported_with_intel_mnemonic, |
243 | unsupported_syntax, | |
6c30d220 | 244 | unsupported, |
260cd341 | 245 | invalid_sib_address, |
6c30d220 | 246 | invalid_vsib_address, |
7bab8ab5 | 247 | invalid_vector_register_set, |
260cd341 | 248 | invalid_tmm_register_set, |
43234a1e L |
249 | unsupported_vector_index_register, |
250 | unsupported_broadcast, | |
43234a1e L |
251 | broadcast_needed, |
252 | unsupported_masking, | |
253 | mask_not_on_destination, | |
254 | no_default_mask, | |
255 | unsupported_rc_sae, | |
256 | rc_sae_operand_not_last_imm, | |
257 | invalid_register_operand, | |
a65babc9 L |
258 | }; |
259 | ||
252b5132 RH |
260 | struct _i386_insn |
261 | { | |
47926f60 | 262 | /* TM holds the template for the insn were currently assembling. */ |
d3ce72d0 | 263 | insn_template tm; |
252b5132 | 264 | |
7d5e4556 L |
265 | /* SUFFIX holds the instruction size suffix for byte, word, dword |
266 | or qword, if given. */ | |
252b5132 RH |
267 | char suffix; |
268 | ||
9a182d04 JB |
269 | /* OPCODE_LENGTH holds the number of base opcode bytes. */ |
270 | unsigned char opcode_length; | |
271 | ||
47926f60 | 272 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
273 | unsigned int operands; |
274 | ||
275 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
276 | of given register, displacement, memory operands and immediate | |
47926f60 | 277 | operands. */ |
252b5132 RH |
278 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
279 | ||
280 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 281 | use OP[i] for the corresponding operand. */ |
40fb9820 | 282 | i386_operand_type types[MAX_OPERANDS]; |
252b5132 | 283 | |
520dc8e8 AM |
284 | /* Displacement expression, immediate expression, or register for each |
285 | operand. */ | |
286 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 287 | |
3e73aa7c JH |
288 | /* Flags for operands. */ |
289 | unsigned int flags[MAX_OPERANDS]; | |
290 | #define Operand_PCrel 1 | |
c48dadc9 | 291 | #define Operand_Mem 2 |
3e73aa7c | 292 | |
252b5132 | 293 | /* Relocation type for operand */ |
f86103b7 | 294 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
252b5132 | 295 | |
252b5132 RH |
296 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
297 | the base index byte below. */ | |
298 | const reg_entry *base_reg; | |
299 | const reg_entry *index_reg; | |
300 | unsigned int log2_scale_factor; | |
301 | ||
302 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 303 | explicit segment overrides are given. */ |
5e042380 | 304 | const reg_entry *seg[2]; |
252b5132 | 305 | |
8325cc63 JB |
306 | /* Copied first memory operand string, for re-checking. */ |
307 | char *memop1_string; | |
308 | ||
252b5132 RH |
309 | /* PREFIX holds all the given prefix opcodes (usually null). |
310 | PREFIXES is the number of prefix opcodes. */ | |
311 | unsigned int prefixes; | |
312 | unsigned char prefix[MAX_PREFIXES]; | |
313 | ||
50128d0c | 314 | /* Register is in low 3 bits of opcode. */ |
5b7c81bd | 315 | bool short_form; |
50128d0c | 316 | |
6f2f06be | 317 | /* The operand to a branch insn indicates an absolute branch. */ |
5b7c81bd | 318 | bool jumpabsolute; |
6f2f06be | 319 | |
921eafea L |
320 | /* Extended states. */ |
321 | enum | |
322 | { | |
323 | /* Use MMX state. */ | |
324 | xstate_mmx = 1 << 0, | |
325 | /* Use XMM state. */ | |
326 | xstate_xmm = 1 << 1, | |
327 | /* Use YMM state. */ | |
328 | xstate_ymm = 1 << 2 | xstate_xmm, | |
329 | /* Use ZMM state. */ | |
330 | xstate_zmm = 1 << 3 | xstate_ymm, | |
331 | /* Use TMM state. */ | |
32930e4e L |
332 | xstate_tmm = 1 << 4, |
333 | /* Use MASK state. */ | |
334 | xstate_mask = 1 << 5 | |
921eafea | 335 | } xstate; |
260cd341 | 336 | |
e379e5f3 | 337 | /* Has GOTPC or TLS relocation. */ |
5b7c81bd | 338 | bool has_gotpc_tls_reloc; |
e379e5f3 | 339 | |
252b5132 | 340 | /* RM and SIB are the modrm byte and the sib byte where the |
c1e679ec | 341 | addressing modes of this insn are encoded. */ |
252b5132 | 342 | modrm_byte rm; |
3e73aa7c | 343 | rex_byte rex; |
43234a1e | 344 | rex_byte vrex; |
252b5132 | 345 | sib_byte sib; |
c0f3af97 | 346 | vex_prefix vex; |
b6169b20 | 347 | |
6225c532 JB |
348 | /* Masking attributes. |
349 | ||
350 | The struct describes masking, applied to OPERAND in the instruction. | |
351 | REG is a pointer to the corresponding mask register. ZEROING tells | |
352 | whether merging or zeroing mask is used. */ | |
353 | struct Mask_Operation | |
354 | { | |
355 | const reg_entry *reg; | |
356 | unsigned int zeroing; | |
357 | /* The operand where this operation is associated. */ | |
358 | unsigned int operand; | |
359 | } mask; | |
43234a1e L |
360 | |
361 | /* Rounding control and SAE attributes. */ | |
ca5312a2 JB |
362 | struct RC_Operation |
363 | { | |
364 | enum rc_type | |
365 | { | |
366 | rc_none = -1, | |
367 | rne, | |
368 | rd, | |
369 | ru, | |
370 | rz, | |
371 | saeonly | |
372 | } type; | |
373 | ||
374 | unsigned int operand; | |
375 | } rounding; | |
43234a1e | 376 | |
5273a3cd JB |
377 | /* Broadcasting attributes. |
378 | ||
379 | The struct describes broadcasting, applied to OPERAND. TYPE is | |
380 | expresses the broadcast factor. */ | |
381 | struct Broadcast_Operation | |
382 | { | |
383 | /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */ | |
384 | unsigned int type; | |
385 | ||
386 | /* Index of broadcasted operand. */ | |
387 | unsigned int operand; | |
388 | ||
389 | /* Number of bytes to broadcast. */ | |
390 | unsigned int bytes; | |
391 | } broadcast; | |
43234a1e L |
392 | |
393 | /* Compressed disp8*N attribute. */ | |
394 | unsigned int memshift; | |
395 | ||
86fa6981 L |
396 | /* Prefer load or store in encoding. */ |
397 | enum | |
398 | { | |
399 | dir_encoding_default = 0, | |
400 | dir_encoding_load, | |
64c49ab3 JB |
401 | dir_encoding_store, |
402 | dir_encoding_swap | |
86fa6981 | 403 | } dir_encoding; |
891edac4 | 404 | |
41eb8e88 | 405 | /* Prefer 8bit, 16bit, 32bit displacement in encoding. */ |
a501d77e L |
406 | enum |
407 | { | |
408 | disp_encoding_default = 0, | |
409 | disp_encoding_8bit, | |
41eb8e88 | 410 | disp_encoding_16bit, |
a501d77e L |
411 | disp_encoding_32bit |
412 | } disp_encoding; | |
f8a5c266 | 413 | |
6b6b6807 | 414 | /* Prefer the REX byte in encoding. */ |
5b7c81bd | 415 | bool rex_encoding; |
6b6b6807 | 416 | |
b6f8c7c4 | 417 | /* Disable instruction size optimization. */ |
5b7c81bd | 418 | bool no_optimize; |
b6f8c7c4 | 419 | |
86fa6981 L |
420 | /* How to encode vector instructions. */ |
421 | enum | |
422 | { | |
423 | vex_encoding_default = 0, | |
42e04b36 | 424 | vex_encoding_vex, |
86fa6981 | 425 | vex_encoding_vex3, |
da4977e0 JB |
426 | vex_encoding_evex, |
427 | vex_encoding_error | |
86fa6981 L |
428 | } vec_encoding; |
429 | ||
d5de92cf L |
430 | /* REP prefix. */ |
431 | const char *rep_prefix; | |
432 | ||
165de32a L |
433 | /* HLE prefix. */ |
434 | const char *hle_prefix; | |
42164a71 | 435 | |
7e8b059b L |
436 | /* Have BND prefix. */ |
437 | const char *bnd_prefix; | |
438 | ||
04ef582a L |
439 | /* Have NOTRACK prefix. */ |
440 | const char *notrack_prefix; | |
441 | ||
891edac4 | 442 | /* Error message. */ |
a65babc9 | 443 | enum i386_error error; |
252b5132 RH |
444 | }; |
445 | ||
446 | typedef struct _i386_insn i386_insn; | |
447 | ||
43234a1e L |
448 | /* Link RC type with corresponding string, that'll be looked for in |
449 | asm. */ | |
450 | struct RC_name | |
451 | { | |
452 | enum rc_type type; | |
453 | const char *name; | |
454 | unsigned int len; | |
455 | }; | |
456 | ||
457 | static const struct RC_name RC_NamesTable[] = | |
458 | { | |
459 | { rne, STRING_COMMA_LEN ("rn-sae") }, | |
460 | { rd, STRING_COMMA_LEN ("rd-sae") }, | |
461 | { ru, STRING_COMMA_LEN ("ru-sae") }, | |
462 | { rz, STRING_COMMA_LEN ("rz-sae") }, | |
463 | { saeonly, STRING_COMMA_LEN ("sae") }, | |
464 | }; | |
465 | ||
252b5132 RH |
466 | /* List of chars besides those in app.c:symbol_chars that can start an |
467 | operand. Used to prevent the scrubber eating vital white-space. */ | |
86fa6981 | 468 | const char extra_symbol_chars[] = "*%-([{}" |
252b5132 | 469 | #ifdef LEX_AT |
32137342 NC |
470 | "@" |
471 | #endif | |
472 | #ifdef LEX_QM | |
473 | "?" | |
252b5132 | 474 | #endif |
32137342 | 475 | ; |
252b5132 | 476 | |
b3983e5f JB |
477 | #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ |
478 | && !defined (TE_GNU) \ | |
479 | && !defined (TE_LINUX) \ | |
480 | && !defined (TE_FreeBSD) \ | |
481 | && !defined (TE_DragonFly) \ | |
482 | && !defined (TE_NetBSD)) | |
252b5132 | 483 | /* This array holds the chars that always start a comment. If the |
b3b91714 AM |
484 | pre-processor is disabled, these aren't very useful. The option |
485 | --divide will remove '/' from this list. */ | |
486 | const char *i386_comment_chars = "#/"; | |
487 | #define SVR4_COMMENT_CHARS 1 | |
252b5132 | 488 | #define PREFIX_SEPARATOR '\\' |
252b5132 | 489 | |
b3b91714 AM |
490 | #else |
491 | const char *i386_comment_chars = "#"; | |
492 | #define PREFIX_SEPARATOR '/' | |
493 | #endif | |
494 | ||
252b5132 RH |
495 | /* This array holds the chars that only start a comment at the beginning of |
496 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
497 | .line and .file directives will appear in the pre-processed output. |
498 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 499 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
500 | #NO_APP at the beginning of its output. |
501 | Also note that comments started like this one will always work if | |
252b5132 | 502 | '/' isn't otherwise defined. */ |
b3b91714 | 503 | const char line_comment_chars[] = "#/"; |
252b5132 | 504 | |
63a0b638 | 505 | const char line_separator_chars[] = ";"; |
252b5132 | 506 | |
ce8a8b2f AM |
507 | /* Chars that can be used to separate mant from exp in floating point |
508 | nums. */ | |
252b5132 RH |
509 | const char EXP_CHARS[] = "eE"; |
510 | ||
ce8a8b2f AM |
511 | /* Chars that mean this number is a floating point constant |
512 | As in 0f12.456 | |
513 | or 0d1.2345e12. */ | |
252b5132 RH |
514 | const char FLT_CHARS[] = "fFdDxX"; |
515 | ||
ce8a8b2f | 516 | /* Tables for lexical analysis. */ |
252b5132 RH |
517 | static char mnemonic_chars[256]; |
518 | static char register_chars[256]; | |
519 | static char operand_chars[256]; | |
520 | static char identifier_chars[256]; | |
521 | static char digit_chars[256]; | |
522 | ||
ce8a8b2f | 523 | /* Lexical macros. */ |
252b5132 RH |
524 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
525 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
526 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
527 | #define is_space_char(x) ((x) == ' ') | |
528 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
529 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
530 | ||
0234cb7c | 531 | /* All non-digit non-letter characters that may occur in an operand. */ |
252b5132 RH |
532 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
533 | ||
534 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
535 | effect this we maintain a stack of saved characters that we've smashed | |
536 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 537 | assembler instruction). */ |
252b5132 | 538 | static char save_stack[32]; |
ce8a8b2f | 539 | static char *save_stack_p; |
252b5132 RH |
540 | #define END_STRING_AND_SAVE(s) \ |
541 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
542 | #define RESTORE_END_STRING(s) \ | |
543 | do { *(s) = *--save_stack_p; } while (0) | |
544 | ||
47926f60 | 545 | /* The instruction we're assembling. */ |
252b5132 RH |
546 | static i386_insn i; |
547 | ||
548 | /* Possible templates for current insn. */ | |
549 | static const templates *current_templates; | |
550 | ||
31b2323c L |
551 | /* Per instruction expressionS buffers: max displacements & immediates. */ |
552 | static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; | |
553 | static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; | |
252b5132 | 554 | |
47926f60 | 555 | /* Current operand we are working on. */ |
ee86248c | 556 | static int this_operand = -1; |
252b5132 | 557 | |
3e73aa7c JH |
558 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
559 | these. */ | |
560 | ||
561 | enum flag_code { | |
562 | CODE_32BIT, | |
563 | CODE_16BIT, | |
564 | CODE_64BIT }; | |
565 | ||
566 | static enum flag_code flag_code; | |
4fa24527 | 567 | static unsigned int object_64bit; |
862be3fb | 568 | static unsigned int disallow_64bit_reloc; |
3e73aa7c | 569 | static int use_rela_relocations = 0; |
e379e5f3 L |
570 | /* __tls_get_addr/___tls_get_addr symbol for TLS. */ |
571 | static const char *tls_get_addr; | |
3e73aa7c | 572 | |
7af8ed2d NC |
573 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
574 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ | |
575 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) | |
576 | ||
351f65ca L |
577 | /* The ELF ABI to use. */ |
578 | enum x86_elf_abi | |
579 | { | |
580 | I386_ABI, | |
7f56bc95 L |
581 | X86_64_ABI, |
582 | X86_64_X32_ABI | |
351f65ca L |
583 | }; |
584 | ||
585 | static enum x86_elf_abi x86_elf_abi = I386_ABI; | |
7af8ed2d | 586 | #endif |
351f65ca | 587 | |
167ad85b TG |
588 | #if defined (TE_PE) || defined (TE_PEP) |
589 | /* Use big object file format. */ | |
590 | static int use_big_obj = 0; | |
591 | #endif | |
592 | ||
8dcea932 L |
593 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
594 | /* 1 if generating code for a shared library. */ | |
595 | static int shared = 0; | |
596 | #endif | |
597 | ||
47926f60 KH |
598 | /* 1 for intel syntax, |
599 | 0 if att syntax. */ | |
600 | static int intel_syntax = 0; | |
252b5132 | 601 | |
4b5aaf5f L |
602 | static enum x86_64_isa |
603 | { | |
604 | amd64 = 1, /* AMD64 ISA. */ | |
605 | intel64 /* Intel64 ISA. */ | |
606 | } isa64; | |
e89c5eaa | 607 | |
1efbbeb4 L |
608 | /* 1 for intel mnemonic, |
609 | 0 if att mnemonic. */ | |
610 | static int intel_mnemonic = !SYSV386_COMPAT; | |
611 | ||
a60de03c JB |
612 | /* 1 if pseudo registers are permitted. */ |
613 | static int allow_pseudo_reg = 0; | |
614 | ||
47926f60 KH |
615 | /* 1 if register prefix % not required. */ |
616 | static int allow_naked_reg = 0; | |
252b5132 | 617 | |
33eaf5de | 618 | /* 1 if the assembler should add BND prefix for all control-transferring |
7e8b059b L |
619 | instructions supporting it, even if this prefix wasn't specified |
620 | explicitly. */ | |
621 | static int add_bnd_prefix = 0; | |
622 | ||
ba104c83 | 623 | /* 1 if pseudo index register, eiz/riz, is allowed . */ |
db51cc60 L |
624 | static int allow_index_reg = 0; |
625 | ||
d022bddd IT |
626 | /* 1 if the assembler should ignore LOCK prefix, even if it was |
627 | specified explicitly. */ | |
628 | static int omit_lock_prefix = 0; | |
629 | ||
e4e00185 AS |
630 | /* 1 if the assembler should encode lfence, mfence, and sfence as |
631 | "lock addl $0, (%{re}sp)". */ | |
632 | static int avoid_fence = 0; | |
633 | ||
ae531041 L |
634 | /* 1 if lfence should be inserted after every load. */ |
635 | static int lfence_after_load = 0; | |
636 | ||
637 | /* Non-zero if lfence should be inserted before indirect branch. */ | |
638 | static enum lfence_before_indirect_branch_kind | |
639 | { | |
640 | lfence_branch_none = 0, | |
641 | lfence_branch_register, | |
642 | lfence_branch_memory, | |
643 | lfence_branch_all | |
644 | } | |
645 | lfence_before_indirect_branch; | |
646 | ||
647 | /* Non-zero if lfence should be inserted before ret. */ | |
648 | static enum lfence_before_ret_kind | |
649 | { | |
650 | lfence_before_ret_none = 0, | |
651 | lfence_before_ret_not, | |
a09f656b | 652 | lfence_before_ret_or, |
653 | lfence_before_ret_shl | |
ae531041 L |
654 | } |
655 | lfence_before_ret; | |
656 | ||
657 | /* Types of previous instruction is .byte or prefix. */ | |
e379e5f3 L |
658 | static struct |
659 | { | |
660 | segT seg; | |
661 | const char *file; | |
662 | const char *name; | |
663 | unsigned int line; | |
664 | enum last_insn_kind | |
665 | { | |
666 | last_insn_other = 0, | |
667 | last_insn_directive, | |
668 | last_insn_prefix | |
669 | } kind; | |
670 | } last_insn; | |
671 | ||
0cb4071e L |
672 | /* 1 if the assembler should generate relax relocations. */ |
673 | ||
674 | static int generate_relax_relocations | |
675 | = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS; | |
676 | ||
7bab8ab5 | 677 | static enum check_kind |
daf50ae7 | 678 | { |
7bab8ab5 JB |
679 | check_none = 0, |
680 | check_warning, | |
681 | check_error | |
daf50ae7 | 682 | } |
7bab8ab5 | 683 | sse_check, operand_check = check_warning; |
daf50ae7 | 684 | |
e379e5f3 L |
685 | /* Non-zero if branches should be aligned within power of 2 boundary. */ |
686 | static int align_branch_power = 0; | |
687 | ||
688 | /* Types of branches to align. */ | |
689 | enum align_branch_kind | |
690 | { | |
691 | align_branch_none = 0, | |
692 | align_branch_jcc = 1, | |
693 | align_branch_fused = 2, | |
694 | align_branch_jmp = 3, | |
695 | align_branch_call = 4, | |
696 | align_branch_indirect = 5, | |
697 | align_branch_ret = 6 | |
698 | }; | |
699 | ||
700 | /* Type bits of branches to align. */ | |
701 | enum align_branch_bit | |
702 | { | |
703 | align_branch_jcc_bit = 1 << align_branch_jcc, | |
704 | align_branch_fused_bit = 1 << align_branch_fused, | |
705 | align_branch_jmp_bit = 1 << align_branch_jmp, | |
706 | align_branch_call_bit = 1 << align_branch_call, | |
707 | align_branch_indirect_bit = 1 << align_branch_indirect, | |
708 | align_branch_ret_bit = 1 << align_branch_ret | |
709 | }; | |
710 | ||
711 | static unsigned int align_branch = (align_branch_jcc_bit | |
712 | | align_branch_fused_bit | |
713 | | align_branch_jmp_bit); | |
714 | ||
79d72f45 HL |
715 | /* Types of condition jump used by macro-fusion. */ |
716 | enum mf_jcc_kind | |
717 | { | |
718 | mf_jcc_jo = 0, /* base opcode 0x70 */ | |
719 | mf_jcc_jc, /* base opcode 0x72 */ | |
720 | mf_jcc_je, /* base opcode 0x74 */ | |
721 | mf_jcc_jna, /* base opcode 0x76 */ | |
722 | mf_jcc_js, /* base opcode 0x78 */ | |
723 | mf_jcc_jp, /* base opcode 0x7a */ | |
724 | mf_jcc_jl, /* base opcode 0x7c */ | |
725 | mf_jcc_jle, /* base opcode 0x7e */ | |
726 | }; | |
727 | ||
728 | /* Types of compare flag-modifying insntructions used by macro-fusion. */ | |
729 | enum mf_cmp_kind | |
730 | { | |
731 | mf_cmp_test_and, /* test/cmp */ | |
732 | mf_cmp_alu_cmp, /* add/sub/cmp */ | |
733 | mf_cmp_incdec /* inc/dec */ | |
734 | }; | |
735 | ||
e379e5f3 L |
736 | /* The maximum padding size for fused jcc. CMP like instruction can |
737 | be 9 bytes and jcc can be 6 bytes. Leave room just in case for | |
738 | prefixes. */ | |
739 | #define MAX_FUSED_JCC_PADDING_SIZE 20 | |
740 | ||
741 | /* The maximum number of prefixes added for an instruction. */ | |
742 | static unsigned int align_branch_prefix_size = 5; | |
743 | ||
b6f8c7c4 L |
744 | /* Optimization: |
745 | 1. Clear the REX_W bit with register operand if possible. | |
746 | 2. Above plus use 128bit vector instruction to clear the full vector | |
747 | register. | |
748 | */ | |
749 | static int optimize = 0; | |
750 | ||
751 | /* Optimization: | |
752 | 1. Clear the REX_W bit with register operand if possible. | |
753 | 2. Above plus use 128bit vector instruction to clear the full vector | |
754 | register. | |
755 | 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to | |
756 | "testb $imm7,%r8". | |
757 | */ | |
758 | static int optimize_for_space = 0; | |
759 | ||
2ca3ace5 L |
760 | /* Register prefix used for error message. */ |
761 | static const char *register_prefix = "%"; | |
762 | ||
47926f60 KH |
763 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
764 | leave, push, and pop instructions so that gcc has the same stack | |
765 | frame as in 32 bit mode. */ | |
766 | static char stackop_size = '\0'; | |
eecb386c | 767 | |
12b55ccc L |
768 | /* Non-zero to optimize code alignment. */ |
769 | int optimize_align_code = 1; | |
770 | ||
47926f60 KH |
771 | /* Non-zero to quieten some warnings. */ |
772 | static int quiet_warnings = 0; | |
a38cf1db | 773 | |
47926f60 KH |
774 | /* CPU name. */ |
775 | static const char *cpu_arch_name = NULL; | |
6305a203 | 776 | static char *cpu_sub_arch_name = NULL; |
a38cf1db | 777 | |
47926f60 | 778 | /* CPU feature flags. */ |
40fb9820 L |
779 | static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; |
780 | ||
ccc9c027 L |
781 | /* If we have selected a cpu we are generating instructions for. */ |
782 | static int cpu_arch_tune_set = 0; | |
783 | ||
9103f4f4 | 784 | /* Cpu we are generating instructions for. */ |
fbf3f584 | 785 | enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; |
9103f4f4 L |
786 | |
787 | /* CPU feature flags of cpu we are generating instructions for. */ | |
40fb9820 | 788 | static i386_cpu_flags cpu_arch_tune_flags; |
9103f4f4 | 789 | |
ccc9c027 | 790 | /* CPU instruction set architecture used. */ |
fbf3f584 | 791 | enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; |
ccc9c027 | 792 | |
9103f4f4 | 793 | /* CPU feature flags of instruction set architecture used. */ |
fbf3f584 | 794 | i386_cpu_flags cpu_arch_isa_flags; |
9103f4f4 | 795 | |
fddf5b5b AM |
796 | /* If set, conditional jumps are not automatically promoted to handle |
797 | larger than a byte offset. */ | |
798 | static unsigned int no_cond_jump_promotion = 0; | |
799 | ||
c0f3af97 L |
800 | /* Encode SSE instructions with VEX prefix. */ |
801 | static unsigned int sse2avx; | |
802 | ||
539f890d L |
803 | /* Encode scalar AVX instructions with specific vector length. */ |
804 | static enum | |
805 | { | |
806 | vex128 = 0, | |
807 | vex256 | |
808 | } avxscalar; | |
809 | ||
03751133 L |
810 | /* Encode VEX WIG instructions with specific vex.w. */ |
811 | static enum | |
812 | { | |
813 | vexw0 = 0, | |
814 | vexw1 | |
815 | } vexwig; | |
816 | ||
43234a1e L |
817 | /* Encode scalar EVEX LIG instructions with specific vector length. */ |
818 | static enum | |
819 | { | |
820 | evexl128 = 0, | |
821 | evexl256, | |
822 | evexl512 | |
823 | } evexlig; | |
824 | ||
825 | /* Encode EVEX WIG instructions with specific evex.w. */ | |
826 | static enum | |
827 | { | |
828 | evexw0 = 0, | |
829 | evexw1 | |
830 | } evexwig; | |
831 | ||
d3d3c6db IT |
832 | /* Value to encode in EVEX RC bits, for SAE-only instructions. */ |
833 | static enum rc_type evexrcig = rne; | |
834 | ||
29b0f896 | 835 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
87c245cc | 836 | static symbolS *GOT_symbol; |
29b0f896 | 837 | |
a4447b93 RH |
838 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
839 | unsigned int x86_dwarf2_return_column; | |
840 | ||
841 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
842 | int x86_cie_data_alignment; | |
843 | ||
252b5132 | 844 | /* Interface to relax_segment. |
fddf5b5b AM |
845 | There are 3 major relax states for 386 jump insns because the |
846 | different types of jumps add different sizes to frags when we're | |
e379e5f3 L |
847 | figuring out what sort of jump to choose to reach a given label. |
848 | ||
849 | BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align | |
850 | branches which are handled by md_estimate_size_before_relax() and | |
851 | i386_generic_table_relax_frag(). */ | |
252b5132 | 852 | |
47926f60 | 853 | /* Types. */ |
93c2a809 AM |
854 | #define UNCOND_JUMP 0 |
855 | #define COND_JUMP 1 | |
856 | #define COND_JUMP86 2 | |
e379e5f3 L |
857 | #define BRANCH_PADDING 3 |
858 | #define BRANCH_PREFIX 4 | |
859 | #define FUSED_JCC_PADDING 5 | |
fddf5b5b | 860 | |
47926f60 | 861 | /* Sizes. */ |
252b5132 RH |
862 | #define CODE16 1 |
863 | #define SMALL 0 | |
29b0f896 | 864 | #define SMALL16 (SMALL | CODE16) |
252b5132 | 865 | #define BIG 2 |
29b0f896 | 866 | #define BIG16 (BIG | CODE16) |
252b5132 RH |
867 | |
868 | #ifndef INLINE | |
869 | #ifdef __GNUC__ | |
870 | #define INLINE __inline__ | |
871 | #else | |
872 | #define INLINE | |
873 | #endif | |
874 | #endif | |
875 | ||
fddf5b5b AM |
876 | #define ENCODE_RELAX_STATE(type, size) \ |
877 | ((relax_substateT) (((type) << 2) | (size))) | |
878 | #define TYPE_FROM_RELAX_STATE(s) \ | |
879 | ((s) >> 2) | |
880 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
881 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
882 | |
883 | /* This table is used by relax_frag to promote short jumps to long | |
884 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
885 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
886 | don't allow a short jump in a 32 bit code segment to be promoted to | |
887 | a 16 bit offset jump because it's slower (requires data size | |
888 | prefix), and doesn't work, unless the destination is in the bottom | |
889 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
890 | ||
891 | const relax_typeS md_relax_table[] = | |
892 | { | |
24eab124 AM |
893 | /* The fields are: |
894 | 1) most positive reach of this state, | |
895 | 2) most negative reach of this state, | |
93c2a809 | 896 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 897 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 898 | |
fddf5b5b | 899 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
900 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
901 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
902 | /* dword jmp adds 4 bytes to frag: | |
903 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 904 | {0, 0, 4, 0}, |
93c2a809 AM |
905 | /* word jmp adds 2 byte2 to frag: |
906 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
907 | {0, 0, 2, 0}, |
908 | ||
93c2a809 AM |
909 | /* COND_JUMP states. */ |
910 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
911 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
912 | /* dword conditionals adds 5 bytes to frag: | |
913 | 1 extra opcode byte, 4 displacement bytes. */ | |
914 | {0, 0, 5, 0}, | |
fddf5b5b | 915 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
916 | 1 extra opcode byte, 2 displacement bytes. */ |
917 | {0, 0, 3, 0}, | |
918 | ||
919 | /* COND_JUMP86 states. */ | |
920 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
921 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
922 | /* dword conditionals adds 5 bytes to frag: | |
923 | 1 extra opcode byte, 4 displacement bytes. */ | |
924 | {0, 0, 5, 0}, | |
925 | /* word conditionals add 4 bytes to frag: | |
926 | 1 displacement byte and a 3 byte long branch insn. */ | |
927 | {0, 0, 4, 0} | |
252b5132 RH |
928 | }; |
929 | ||
9103f4f4 L |
930 | static const arch_entry cpu_arch[] = |
931 | { | |
89507696 JB |
932 | /* Do not replace the first two entries - i386_target_format() |
933 | relies on them being there in this order. */ | |
8a2c8fef | 934 | { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32, |
293f5f65 | 935 | CPU_GENERIC32_FLAGS, 0 }, |
8a2c8fef | 936 | { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64, |
293f5f65 | 937 | CPU_GENERIC64_FLAGS, 0 }, |
8a2c8fef | 938 | { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN, |
293f5f65 | 939 | CPU_NONE_FLAGS, 0 }, |
8a2c8fef | 940 | { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN, |
293f5f65 | 941 | CPU_I186_FLAGS, 0 }, |
8a2c8fef | 942 | { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN, |
293f5f65 | 943 | CPU_I286_FLAGS, 0 }, |
8a2c8fef | 944 | { STRING_COMMA_LEN ("i386"), PROCESSOR_I386, |
293f5f65 | 945 | CPU_I386_FLAGS, 0 }, |
8a2c8fef | 946 | { STRING_COMMA_LEN ("i486"), PROCESSOR_I486, |
293f5f65 | 947 | CPU_I486_FLAGS, 0 }, |
8a2c8fef | 948 | { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM, |
293f5f65 | 949 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 950 | { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 951 | CPU_I686_FLAGS, 0 }, |
8a2c8fef | 952 | { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM, |
293f5f65 | 953 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 954 | { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 955 | CPU_PENTIUMPRO_FLAGS, 0 }, |
8a2c8fef | 956 | { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 957 | CPU_P2_FLAGS, 0 }, |
8a2c8fef | 958 | { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO, |
293f5f65 | 959 | CPU_P3_FLAGS, 0 }, |
8a2c8fef | 960 | { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4, |
293f5f65 | 961 | CPU_P4_FLAGS, 0 }, |
8a2c8fef | 962 | { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA, |
293f5f65 | 963 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 964 | { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA, |
293f5f65 | 965 | CPU_NOCONA_FLAGS, 0 }, |
8a2c8fef | 966 | { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE, |
293f5f65 | 967 | CPU_CORE_FLAGS, 1 }, |
8a2c8fef | 968 | { STRING_COMMA_LEN ("core"), PROCESSOR_CORE, |
293f5f65 | 969 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 970 | { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2, |
293f5f65 | 971 | CPU_CORE2_FLAGS, 1 }, |
8a2c8fef | 972 | { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2, |
293f5f65 | 973 | CPU_CORE2_FLAGS, 0 }, |
8a2c8fef | 974 | { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7, |
293f5f65 | 975 | CPU_COREI7_FLAGS, 0 }, |
8a2c8fef | 976 | { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM, |
293f5f65 | 977 | CPU_L1OM_FLAGS, 0 }, |
7a9068fe | 978 | { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM, |
293f5f65 | 979 | CPU_K1OM_FLAGS, 0 }, |
81486035 | 980 | { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU, |
293f5f65 | 981 | CPU_IAMCU_FLAGS, 0 }, |
8a2c8fef | 982 | { STRING_COMMA_LEN ("k6"), PROCESSOR_K6, |
293f5f65 | 983 | CPU_K6_FLAGS, 0 }, |
8a2c8fef | 984 | { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6, |
293f5f65 | 985 | CPU_K6_2_FLAGS, 0 }, |
8a2c8fef | 986 | { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON, |
293f5f65 | 987 | CPU_ATHLON_FLAGS, 0 }, |
8a2c8fef | 988 | { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8, |
293f5f65 | 989 | CPU_K8_FLAGS, 1 }, |
8a2c8fef | 990 | { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8, |
293f5f65 | 991 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 992 | { STRING_COMMA_LEN ("k8"), PROCESSOR_K8, |
293f5f65 | 993 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 994 | { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10, |
293f5f65 | 995 | CPU_AMDFAM10_FLAGS, 0 }, |
8aedb9fe | 996 | { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD, |
293f5f65 | 997 | CPU_BDVER1_FLAGS, 0 }, |
8aedb9fe | 998 | { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD, |
293f5f65 | 999 | CPU_BDVER2_FLAGS, 0 }, |
5e5c50d3 | 1000 | { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD, |
293f5f65 | 1001 | CPU_BDVER3_FLAGS, 0 }, |
c7b0bd56 | 1002 | { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD, |
293f5f65 | 1003 | CPU_BDVER4_FLAGS, 0 }, |
029f3522 | 1004 | { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER, |
293f5f65 | 1005 | CPU_ZNVER1_FLAGS, 0 }, |
a9660a6f AP |
1006 | { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER, |
1007 | CPU_ZNVER2_FLAGS, 0 }, | |
646cc3e0 GG |
1008 | { STRING_COMMA_LEN ("znver3"), PROCESSOR_ZNVER, |
1009 | CPU_ZNVER3_FLAGS, 0 }, | |
7b458c12 | 1010 | { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT, |
293f5f65 | 1011 | CPU_BTVER1_FLAGS, 0 }, |
7b458c12 | 1012 | { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT, |
293f5f65 | 1013 | CPU_BTVER2_FLAGS, 0 }, |
8a2c8fef | 1014 | { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN, |
293f5f65 | 1015 | CPU_8087_FLAGS, 0 }, |
8a2c8fef | 1016 | { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN, |
293f5f65 | 1017 | CPU_287_FLAGS, 0 }, |
8a2c8fef | 1018 | { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN, |
293f5f65 | 1019 | CPU_387_FLAGS, 0 }, |
1848e567 L |
1020 | { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN, |
1021 | CPU_687_FLAGS, 0 }, | |
d871f3f4 L |
1022 | { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN, |
1023 | CPU_CMOV_FLAGS, 0 }, | |
1024 | { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN, | |
1025 | CPU_FXSR_FLAGS, 0 }, | |
8a2c8fef | 1026 | { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1027 | CPU_MMX_FLAGS, 0 }, |
8a2c8fef | 1028 | { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN, |
293f5f65 | 1029 | CPU_SSE_FLAGS, 0 }, |
8a2c8fef | 1030 | { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN, |
293f5f65 | 1031 | CPU_SSE2_FLAGS, 0 }, |
8a2c8fef | 1032 | { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 1033 | CPU_SSE3_FLAGS, 0 }, |
af5c13b0 L |
1034 | { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, |
1035 | CPU_SSE4A_FLAGS, 0 }, | |
8a2c8fef | 1036 | { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 1037 | CPU_SSSE3_FLAGS, 0 }, |
8a2c8fef | 1038 | { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN, |
293f5f65 | 1039 | CPU_SSE4_1_FLAGS, 0 }, |
8a2c8fef | 1040 | { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN, |
293f5f65 | 1041 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 1042 | { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN, |
293f5f65 | 1043 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 1044 | { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1045 | CPU_AVX_FLAGS, 0 }, |
6c30d220 | 1046 | { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN, |
293f5f65 | 1047 | CPU_AVX2_FLAGS, 0 }, |
43234a1e | 1048 | { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN, |
293f5f65 | 1049 | CPU_AVX512F_FLAGS, 0 }, |
43234a1e | 1050 | { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN, |
293f5f65 | 1051 | CPU_AVX512CD_FLAGS, 0 }, |
43234a1e | 1052 | { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN, |
293f5f65 | 1053 | CPU_AVX512ER_FLAGS, 0 }, |
43234a1e | 1054 | { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN, |
293f5f65 | 1055 | CPU_AVX512PF_FLAGS, 0 }, |
1dfc6506 | 1056 | { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN, |
293f5f65 | 1057 | CPU_AVX512DQ_FLAGS, 0 }, |
1dfc6506 | 1058 | { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN, |
293f5f65 | 1059 | CPU_AVX512BW_FLAGS, 0 }, |
1dfc6506 | 1060 | { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN, |
293f5f65 | 1061 | CPU_AVX512VL_FLAGS, 0 }, |
8a2c8fef | 1062 | { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1063 | CPU_VMX_FLAGS, 0 }, |
8729a6f6 | 1064 | { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN, |
293f5f65 | 1065 | CPU_VMFUNC_FLAGS, 0 }, |
8a2c8fef | 1066 | { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1067 | CPU_SMX_FLAGS, 0 }, |
8a2c8fef | 1068 | { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN, |
293f5f65 | 1069 | CPU_XSAVE_FLAGS, 0 }, |
c7b8aa3a | 1070 | { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 1071 | CPU_XSAVEOPT_FLAGS, 0 }, |
1dfc6506 | 1072 | { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN, |
293f5f65 | 1073 | CPU_XSAVEC_FLAGS, 0 }, |
1dfc6506 | 1074 | { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN, |
293f5f65 | 1075 | CPU_XSAVES_FLAGS, 0 }, |
8a2c8fef | 1076 | { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN, |
293f5f65 | 1077 | CPU_AES_FLAGS, 0 }, |
8a2c8fef | 1078 | { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 1079 | CPU_PCLMUL_FLAGS, 0 }, |
8a2c8fef | 1080 | { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 1081 | CPU_PCLMUL_FLAGS, 1 }, |
c7b8aa3a | 1082 | { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN, |
293f5f65 | 1083 | CPU_FSGSBASE_FLAGS, 0 }, |
c7b8aa3a | 1084 | { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN, |
293f5f65 | 1085 | CPU_RDRND_FLAGS, 0 }, |
c7b8aa3a | 1086 | { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN, |
293f5f65 | 1087 | CPU_F16C_FLAGS, 0 }, |
6c30d220 | 1088 | { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN, |
293f5f65 | 1089 | CPU_BMI2_FLAGS, 0 }, |
8a2c8fef | 1090 | { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN, |
293f5f65 | 1091 | CPU_FMA_FLAGS, 0 }, |
8a2c8fef | 1092 | { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN, |
293f5f65 | 1093 | CPU_FMA4_FLAGS, 0 }, |
8a2c8fef | 1094 | { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN, |
293f5f65 | 1095 | CPU_XOP_FLAGS, 0 }, |
8a2c8fef | 1096 | { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN, |
293f5f65 | 1097 | CPU_LWP_FLAGS, 0 }, |
8a2c8fef | 1098 | { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN, |
293f5f65 | 1099 | CPU_MOVBE_FLAGS, 0 }, |
60aa667e | 1100 | { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN, |
293f5f65 | 1101 | CPU_CX16_FLAGS, 0 }, |
8a2c8fef | 1102 | { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN, |
293f5f65 | 1103 | CPU_EPT_FLAGS, 0 }, |
6c30d220 | 1104 | { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN, |
293f5f65 | 1105 | CPU_LZCNT_FLAGS, 0 }, |
272a84b1 L |
1106 | { STRING_COMMA_LEN (".popcnt"), PROCESSOR_UNKNOWN, |
1107 | CPU_POPCNT_FLAGS, 0 }, | |
42164a71 | 1108 | { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN, |
293f5f65 | 1109 | CPU_HLE_FLAGS, 0 }, |
42164a71 | 1110 | { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN, |
293f5f65 | 1111 | CPU_RTM_FLAGS, 0 }, |
6c30d220 | 1112 | { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN, |
293f5f65 | 1113 | CPU_INVPCID_FLAGS, 0 }, |
8a2c8fef | 1114 | { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN, |
293f5f65 | 1115 | CPU_CLFLUSH_FLAGS, 0 }, |
22109423 | 1116 | { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN, |
293f5f65 | 1117 | CPU_NOP_FLAGS, 0 }, |
8a2c8fef | 1118 | { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN, |
293f5f65 | 1119 | CPU_SYSCALL_FLAGS, 0 }, |
8a2c8fef | 1120 | { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN, |
293f5f65 | 1121 | CPU_RDTSCP_FLAGS, 0 }, |
8a2c8fef | 1122 | { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN, |
293f5f65 | 1123 | CPU_3DNOW_FLAGS, 0 }, |
8a2c8fef | 1124 | { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN, |
293f5f65 | 1125 | CPU_3DNOWA_FLAGS, 0 }, |
8a2c8fef | 1126 | { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN, |
293f5f65 | 1127 | CPU_PADLOCK_FLAGS, 0 }, |
8a2c8fef | 1128 | { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN, |
293f5f65 | 1129 | CPU_SVME_FLAGS, 1 }, |
8a2c8fef | 1130 | { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN, |
293f5f65 | 1131 | CPU_SVME_FLAGS, 0 }, |
8a2c8fef | 1132 | { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, |
293f5f65 | 1133 | CPU_SSE4A_FLAGS, 0 }, |
8a2c8fef | 1134 | { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN, |
293f5f65 | 1135 | CPU_ABM_FLAGS, 0 }, |
87973e9f | 1136 | { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 1137 | CPU_BMI_FLAGS, 0 }, |
2a2a0f38 | 1138 | { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN, |
293f5f65 | 1139 | CPU_TBM_FLAGS, 0 }, |
e2e1fcde | 1140 | { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1141 | CPU_ADX_FLAGS, 0 }, |
e2e1fcde | 1142 | { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN, |
293f5f65 | 1143 | CPU_RDSEED_FLAGS, 0 }, |
e2e1fcde | 1144 | { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN, |
293f5f65 | 1145 | CPU_PRFCHW_FLAGS, 0 }, |
5c111e37 | 1146 | { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN, |
293f5f65 | 1147 | CPU_SMAP_FLAGS, 0 }, |
7e8b059b | 1148 | { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1149 | CPU_MPX_FLAGS, 0 }, |
a0046408 | 1150 | { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN, |
293f5f65 | 1151 | CPU_SHA_FLAGS, 0 }, |
963f3586 | 1152 | { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 1153 | CPU_CLFLUSHOPT_FLAGS, 0 }, |
dcf893b5 | 1154 | { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN, |
293f5f65 | 1155 | CPU_PREFETCHWT1_FLAGS, 0 }, |
2cf200a4 | 1156 | { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN, |
293f5f65 | 1157 | CPU_SE1_FLAGS, 0 }, |
c5e7287a | 1158 | { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN, |
293f5f65 | 1159 | CPU_CLWB_FLAGS, 0 }, |
2cc1b5aa | 1160 | { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN, |
293f5f65 | 1161 | CPU_AVX512IFMA_FLAGS, 0 }, |
14f195c9 | 1162 | { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 1163 | CPU_AVX512VBMI_FLAGS, 0 }, |
920d2ddc IT |
1164 | { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN, |
1165 | CPU_AVX512_4FMAPS_FLAGS, 0 }, | |
47acf0bd IT |
1166 | { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN, |
1167 | CPU_AVX512_4VNNIW_FLAGS, 0 }, | |
620214f7 IT |
1168 | { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN, |
1169 | CPU_AVX512_VPOPCNTDQ_FLAGS, 0 }, | |
53467f57 IT |
1170 | { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN, |
1171 | CPU_AVX512_VBMI2_FLAGS, 0 }, | |
8cfcb765 IT |
1172 | { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN, |
1173 | CPU_AVX512_VNNI_FLAGS, 0 }, | |
ee6872be IT |
1174 | { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN, |
1175 | CPU_AVX512_BITALG_FLAGS, 0 }, | |
58bf9b6a L |
1176 | { STRING_COMMA_LEN (".avx_vnni"), PROCESSOR_UNKNOWN, |
1177 | CPU_AVX_VNNI_FLAGS, 0 }, | |
029f3522 | 1178 | { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN, |
293f5f65 | 1179 | CPU_CLZERO_FLAGS, 0 }, |
9916071f | 1180 | { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1181 | CPU_MWAITX_FLAGS, 0 }, |
8eab4136 | 1182 | { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN, |
293f5f65 | 1183 | CPU_OSPKE_FLAGS, 0 }, |
8bc52696 | 1184 | { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN, |
293f5f65 | 1185 | CPU_RDPID_FLAGS, 0 }, |
6b40c462 L |
1186 | { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN, |
1187 | CPU_PTWRITE_FLAGS, 0 }, | |
d777820b IT |
1188 | { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN, |
1189 | CPU_IBT_FLAGS, 0 }, | |
1190 | { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN, | |
1191 | CPU_SHSTK_FLAGS, 0 }, | |
48521003 IT |
1192 | { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN, |
1193 | CPU_GFNI_FLAGS, 0 }, | |
8dcf1fad IT |
1194 | { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN, |
1195 | CPU_VAES_FLAGS, 0 }, | |
ff1982d5 IT |
1196 | { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN, |
1197 | CPU_VPCLMULQDQ_FLAGS, 0 }, | |
3233d7d0 IT |
1198 | { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN, |
1199 | CPU_WBNOINVD_FLAGS, 0 }, | |
be3a8dca IT |
1200 | { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN, |
1201 | CPU_PCONFIG_FLAGS, 0 }, | |
de89d0a3 IT |
1202 | { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN, |
1203 | CPU_WAITPKG_FLAGS, 0 }, | |
c48935d7 IT |
1204 | { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN, |
1205 | CPU_CLDEMOTE_FLAGS, 0 }, | |
260cd341 LC |
1206 | { STRING_COMMA_LEN (".amx_int8"), PROCESSOR_UNKNOWN, |
1207 | CPU_AMX_INT8_FLAGS, 0 }, | |
1208 | { STRING_COMMA_LEN (".amx_bf16"), PROCESSOR_UNKNOWN, | |
1209 | CPU_AMX_BF16_FLAGS, 0 }, | |
1210 | { STRING_COMMA_LEN (".amx_tile"), PROCESSOR_UNKNOWN, | |
1211 | CPU_AMX_TILE_FLAGS, 0 }, | |
c0a30a9f L |
1212 | { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN, |
1213 | CPU_MOVDIRI_FLAGS, 0 }, | |
1214 | { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN, | |
1215 | CPU_MOVDIR64B_FLAGS, 0 }, | |
d6aab7a1 XG |
1216 | { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN, |
1217 | CPU_AVX512_BF16_FLAGS, 0 }, | |
9186c494 L |
1218 | { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN, |
1219 | CPU_AVX512_VP2INTERSECT_FLAGS, 0 }, | |
81d54bb7 CL |
1220 | { STRING_COMMA_LEN (".tdx"), PROCESSOR_UNKNOWN, |
1221 | CPU_TDX_FLAGS, 0 }, | |
dd455cf5 L |
1222 | { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN, |
1223 | CPU_ENQCMD_FLAGS, 0 }, | |
4b27d27c L |
1224 | { STRING_COMMA_LEN (".serialize"), PROCESSOR_UNKNOWN, |
1225 | CPU_SERIALIZE_FLAGS, 0 }, | |
142861df JB |
1226 | { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN, |
1227 | CPU_RDPRU_FLAGS, 0 }, | |
1228 | { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN, | |
1229 | CPU_MCOMMIT_FLAGS, 0 }, | |
a847e322 JB |
1230 | { STRING_COMMA_LEN (".sev_es"), PROCESSOR_UNKNOWN, |
1231 | CPU_SEV_ES_FLAGS, 0 }, | |
bb651e8b CL |
1232 | { STRING_COMMA_LEN (".tsxldtrk"), PROCESSOR_UNKNOWN, |
1233 | CPU_TSXLDTRK_FLAGS, 0 }, | |
c4694f17 TG |
1234 | { STRING_COMMA_LEN (".kl"), PROCESSOR_UNKNOWN, |
1235 | CPU_KL_FLAGS, 0 }, | |
1236 | { STRING_COMMA_LEN (".widekl"), PROCESSOR_UNKNOWN, | |
1237 | CPU_WIDEKL_FLAGS, 0 }, | |
f64c42a9 LC |
1238 | { STRING_COMMA_LEN (".uintr"), PROCESSOR_UNKNOWN, |
1239 | CPU_UINTR_FLAGS, 0 }, | |
c1fa250a LC |
1240 | { STRING_COMMA_LEN (".hreset"), PROCESSOR_UNKNOWN, |
1241 | CPU_HRESET_FLAGS, 0 }, | |
293f5f65 L |
1242 | }; |
1243 | ||
1244 | static const noarch_entry cpu_noarch[] = | |
1245 | { | |
1246 | { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS }, | |
1848e567 L |
1247 | { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS }, |
1248 | { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS }, | |
1249 | { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS }, | |
d871f3f4 L |
1250 | { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS }, |
1251 | { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS }, | |
293f5f65 L |
1252 | { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS }, |
1253 | { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS }, | |
1848e567 L |
1254 | { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS }, |
1255 | { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS }, | |
af5c13b0 | 1256 | { STRING_COMMA_LEN ("nosse4a"), CPU_ANY_SSE4A_FLAGS }, |
1848e567 L |
1257 | { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS }, |
1258 | { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS }, | |
1259 | { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS }, | |
af5c13b0 | 1260 | { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS }, |
293f5f65 | 1261 | { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS }, |
1848e567 | 1262 | { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS }, |
144b71e2 L |
1263 | { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS }, |
1264 | { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS }, | |
1265 | { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS }, | |
1266 | { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS }, | |
1267 | { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS }, | |
1268 | { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS }, | |
1269 | { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS }, | |
1270 | { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS }, | |
1271 | { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS }, | |
920d2ddc | 1272 | { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS }, |
47acf0bd | 1273 | { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS }, |
620214f7 | 1274 | { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS }, |
53467f57 | 1275 | { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS }, |
8cfcb765 | 1276 | { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS }, |
ee6872be | 1277 | { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS }, |
58bf9b6a | 1278 | { STRING_COMMA_LEN ("noavx_vnni"), CPU_ANY_AVX_VNNI_FLAGS }, |
d777820b IT |
1279 | { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS }, |
1280 | { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS }, | |
260cd341 LC |
1281 | { STRING_COMMA_LEN ("noamx_int8"), CPU_ANY_AMX_INT8_FLAGS }, |
1282 | { STRING_COMMA_LEN ("noamx_bf16"), CPU_ANY_AMX_BF16_FLAGS }, | |
1283 | { STRING_COMMA_LEN ("noamx_tile"), CPU_ANY_AMX_TILE_FLAGS }, | |
c0a30a9f L |
1284 | { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS }, |
1285 | { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS }, | |
d6aab7a1 | 1286 | { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS }, |
708a2fff CL |
1287 | { STRING_COMMA_LEN ("noavx512_vp2intersect"), |
1288 | CPU_ANY_AVX512_VP2INTERSECT_FLAGS }, | |
81d54bb7 | 1289 | { STRING_COMMA_LEN ("notdx"), CPU_ANY_TDX_FLAGS }, |
dd455cf5 | 1290 | { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS }, |
4b27d27c | 1291 | { STRING_COMMA_LEN ("noserialize"), CPU_ANY_SERIALIZE_FLAGS }, |
bb651e8b | 1292 | { STRING_COMMA_LEN ("notsxldtrk"), CPU_ANY_TSXLDTRK_FLAGS }, |
c4694f17 TG |
1293 | { STRING_COMMA_LEN ("nokl"), CPU_ANY_KL_FLAGS }, |
1294 | { STRING_COMMA_LEN ("nowidekl"), CPU_ANY_WIDEKL_FLAGS }, | |
f64c42a9 | 1295 | { STRING_COMMA_LEN ("nouintr"), CPU_ANY_UINTR_FLAGS }, |
c1fa250a | 1296 | { STRING_COMMA_LEN ("nohreset"), CPU_ANY_HRESET_FLAGS }, |
e413e4e9 AM |
1297 | }; |
1298 | ||
704209c0 | 1299 | #ifdef I386COFF |
a6c24e68 NC |
1300 | /* Like s_lcomm_internal in gas/read.c but the alignment string |
1301 | is allowed to be optional. */ | |
1302 | ||
1303 | static symbolS * | |
1304 | pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size) | |
1305 | { | |
1306 | addressT align = 0; | |
1307 | ||
1308 | SKIP_WHITESPACE (); | |
1309 | ||
7ab9ffdd | 1310 | if (needs_align |
a6c24e68 NC |
1311 | && *input_line_pointer == ',') |
1312 | { | |
1313 | align = parse_align (needs_align - 1); | |
7ab9ffdd | 1314 | |
a6c24e68 NC |
1315 | if (align == (addressT) -1) |
1316 | return NULL; | |
1317 | } | |
1318 | else | |
1319 | { | |
1320 | if (size >= 8) | |
1321 | align = 3; | |
1322 | else if (size >= 4) | |
1323 | align = 2; | |
1324 | else if (size >= 2) | |
1325 | align = 1; | |
1326 | else | |
1327 | align = 0; | |
1328 | } | |
1329 | ||
1330 | bss_alloc (symbolP, size, align); | |
1331 | return symbolP; | |
1332 | } | |
1333 | ||
704209c0 | 1334 | static void |
a6c24e68 NC |
1335 | pe_lcomm (int needs_align) |
1336 | { | |
1337 | s_comm_internal (needs_align * 2, pe_lcomm_internal); | |
1338 | } | |
704209c0 | 1339 | #endif |
a6c24e68 | 1340 | |
29b0f896 AM |
1341 | const pseudo_typeS md_pseudo_table[] = |
1342 | { | |
1343 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) | |
1344 | {"align", s_align_bytes, 0}, | |
1345 | #else | |
1346 | {"align", s_align_ptwo, 0}, | |
1347 | #endif | |
1348 | {"arch", set_cpu_arch, 0}, | |
1349 | #ifndef I386COFF | |
1350 | {"bss", s_bss, 0}, | |
a6c24e68 NC |
1351 | #else |
1352 | {"lcomm", pe_lcomm, 1}, | |
29b0f896 AM |
1353 | #endif |
1354 | {"ffloat", float_cons, 'f'}, | |
1355 | {"dfloat", float_cons, 'd'}, | |
1356 | {"tfloat", float_cons, 'x'}, | |
1357 | {"value", cons, 2}, | |
d182319b | 1358 | {"slong", signed_cons, 4}, |
29b0f896 AM |
1359 | {"noopt", s_ignore, 0}, |
1360 | {"optim", s_ignore, 0}, | |
1361 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, | |
1362 | {"code16", set_code_flag, CODE_16BIT}, | |
1363 | {"code32", set_code_flag, CODE_32BIT}, | |
da5f19a2 | 1364 | #ifdef BFD64 |
29b0f896 | 1365 | {"code64", set_code_flag, CODE_64BIT}, |
da5f19a2 | 1366 | #endif |
29b0f896 AM |
1367 | {"intel_syntax", set_intel_syntax, 1}, |
1368 | {"att_syntax", set_intel_syntax, 0}, | |
1efbbeb4 L |
1369 | {"intel_mnemonic", set_intel_mnemonic, 1}, |
1370 | {"att_mnemonic", set_intel_mnemonic, 0}, | |
db51cc60 L |
1371 | {"allow_index_reg", set_allow_index_reg, 1}, |
1372 | {"disallow_index_reg", set_allow_index_reg, 0}, | |
7bab8ab5 JB |
1373 | {"sse_check", set_check, 0}, |
1374 | {"operand_check", set_check, 1}, | |
3b22753a L |
1375 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
1376 | {"largecomm", handle_large_common, 0}, | |
07a53e5c | 1377 | #else |
68d20676 | 1378 | {"file", dwarf2_directive_file, 0}, |
07a53e5c RH |
1379 | {"loc", dwarf2_directive_loc, 0}, |
1380 | {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, | |
3b22753a | 1381 | #endif |
6482c264 NC |
1382 | #ifdef TE_PE |
1383 | {"secrel32", pe_directive_secrel, 0}, | |
1384 | #endif | |
29b0f896 AM |
1385 | {0, 0, 0} |
1386 | }; | |
1387 | ||
1388 | /* For interface with expression (). */ | |
1389 | extern char *input_line_pointer; | |
1390 | ||
1391 | /* Hash table for instruction mnemonic lookup. */ | |
629310ab | 1392 | static htab_t op_hash; |
29b0f896 AM |
1393 | |
1394 | /* Hash table for register lookup. */ | |
629310ab | 1395 | static htab_t reg_hash; |
29b0f896 | 1396 | \f |
ce8a8b2f AM |
1397 | /* Various efficient no-op patterns for aligning code labels. |
1398 | Note: Don't try to assemble the instructions in the comments. | |
1399 | 0L and 0w are not legal. */ | |
62a02d25 L |
1400 | static const unsigned char f32_1[] = |
1401 | {0x90}; /* nop */ | |
1402 | static const unsigned char f32_2[] = | |
1403 | {0x66,0x90}; /* xchg %ax,%ax */ | |
1404 | static const unsigned char f32_3[] = | |
1405 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
1406 | static const unsigned char f32_4[] = | |
1407 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
62a02d25 L |
1408 | static const unsigned char f32_6[] = |
1409 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
1410 | static const unsigned char f32_7[] = | |
1411 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
62a02d25 | 1412 | static const unsigned char f16_3[] = |
3ae729d5 | 1413 | {0x8d,0x74,0x00}; /* lea 0(%si),%si */ |
62a02d25 | 1414 | static const unsigned char f16_4[] = |
3ae729d5 L |
1415 | {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */ |
1416 | static const unsigned char jump_disp8[] = | |
1417 | {0xeb}; /* jmp disp8 */ | |
1418 | static const unsigned char jump32_disp32[] = | |
1419 | {0xe9}; /* jmp disp32 */ | |
1420 | static const unsigned char jump16_disp32[] = | |
1421 | {0x66,0xe9}; /* jmp disp32 */ | |
62a02d25 L |
1422 | /* 32-bit NOPs patterns. */ |
1423 | static const unsigned char *const f32_patt[] = { | |
3ae729d5 | 1424 | f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7 |
62a02d25 L |
1425 | }; |
1426 | /* 16-bit NOPs patterns. */ | |
1427 | static const unsigned char *const f16_patt[] = { | |
3ae729d5 | 1428 | f32_1, f32_2, f16_3, f16_4 |
62a02d25 L |
1429 | }; |
1430 | /* nopl (%[re]ax) */ | |
1431 | static const unsigned char alt_3[] = | |
1432 | {0x0f,0x1f,0x00}; | |
1433 | /* nopl 0(%[re]ax) */ | |
1434 | static const unsigned char alt_4[] = | |
1435 | {0x0f,0x1f,0x40,0x00}; | |
1436 | /* nopl 0(%[re]ax,%[re]ax,1) */ | |
1437 | static const unsigned char alt_5[] = | |
1438 | {0x0f,0x1f,0x44,0x00,0x00}; | |
1439 | /* nopw 0(%[re]ax,%[re]ax,1) */ | |
1440 | static const unsigned char alt_6[] = | |
1441 | {0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
1442 | /* nopl 0L(%[re]ax) */ | |
1443 | static const unsigned char alt_7[] = | |
1444 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
1445 | /* nopl 0L(%[re]ax,%[re]ax,1) */ | |
1446 | static const unsigned char alt_8[] = | |
1447 | {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1448 | /* nopw 0L(%[re]ax,%[re]ax,1) */ | |
1449 | static const unsigned char alt_9[] = | |
1450 | {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1451 | /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
1452 | static const unsigned char alt_10[] = | |
1453 | {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
3ae729d5 L |
1454 | /* data16 nopw %cs:0L(%eax,%eax,1) */ |
1455 | static const unsigned char alt_11[] = | |
1456 | {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
62a02d25 L |
1457 | /* 32-bit and 64-bit NOPs patterns. */ |
1458 | static const unsigned char *const alt_patt[] = { | |
1459 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
3ae729d5 | 1460 | alt_9, alt_10, alt_11 |
62a02d25 L |
1461 | }; |
1462 | ||
1463 | /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum | |
1464 | size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */ | |
1465 | ||
1466 | static void | |
1467 | i386_output_nops (char *where, const unsigned char *const *patt, | |
1468 | int count, int max_single_nop_size) | |
1469 | ||
1470 | { | |
3ae729d5 L |
1471 | /* Place the longer NOP first. */ |
1472 | int last; | |
1473 | int offset; | |
3076e594 NC |
1474 | const unsigned char *nops; |
1475 | ||
1476 | if (max_single_nop_size < 1) | |
1477 | { | |
1478 | as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"), | |
1479 | max_single_nop_size); | |
1480 | return; | |
1481 | } | |
1482 | ||
1483 | nops = patt[max_single_nop_size - 1]; | |
3ae729d5 L |
1484 | |
1485 | /* Use the smaller one if the requsted one isn't available. */ | |
1486 | if (nops == NULL) | |
62a02d25 | 1487 | { |
3ae729d5 L |
1488 | max_single_nop_size--; |
1489 | nops = patt[max_single_nop_size - 1]; | |
62a02d25 L |
1490 | } |
1491 | ||
3ae729d5 L |
1492 | last = count % max_single_nop_size; |
1493 | ||
1494 | count -= last; | |
1495 | for (offset = 0; offset < count; offset += max_single_nop_size) | |
1496 | memcpy (where + offset, nops, max_single_nop_size); | |
1497 | ||
1498 | if (last) | |
1499 | { | |
1500 | nops = patt[last - 1]; | |
1501 | if (nops == NULL) | |
1502 | { | |
1503 | /* Use the smaller one plus one-byte NOP if the needed one | |
1504 | isn't available. */ | |
1505 | last--; | |
1506 | nops = patt[last - 1]; | |
1507 | memcpy (where + offset, nops, last); | |
1508 | where[offset + last] = *patt[0]; | |
1509 | } | |
1510 | else | |
1511 | memcpy (where + offset, nops, last); | |
1512 | } | |
62a02d25 L |
1513 | } |
1514 | ||
3ae729d5 L |
1515 | static INLINE int |
1516 | fits_in_imm7 (offsetT num) | |
1517 | { | |
1518 | return (num & 0x7f) == num; | |
1519 | } | |
1520 | ||
1521 | static INLINE int | |
1522 | fits_in_imm31 (offsetT num) | |
1523 | { | |
1524 | return (num & 0x7fffffff) == num; | |
1525 | } | |
62a02d25 L |
1526 | |
1527 | /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a | |
1528 | single NOP instruction LIMIT. */ | |
1529 | ||
1530 | void | |
3ae729d5 | 1531 | i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit) |
62a02d25 | 1532 | { |
3ae729d5 | 1533 | const unsigned char *const *patt = NULL; |
62a02d25 | 1534 | int max_single_nop_size; |
3ae729d5 L |
1535 | /* Maximum number of NOPs before switching to jump over NOPs. */ |
1536 | int max_number_of_nops; | |
62a02d25 | 1537 | |
3ae729d5 | 1538 | switch (fragP->fr_type) |
62a02d25 | 1539 | { |
3ae729d5 L |
1540 | case rs_fill_nop: |
1541 | case rs_align_code: | |
1542 | break; | |
e379e5f3 L |
1543 | case rs_machine_dependent: |
1544 | /* Allow NOP padding for jumps and calls. */ | |
1545 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING | |
1546 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
1547 | break; | |
1548 | /* Fall through. */ | |
3ae729d5 | 1549 | default: |
62a02d25 L |
1550 | return; |
1551 | } | |
1552 | ||
ccc9c027 L |
1553 | /* We need to decide which NOP sequence to use for 32bit and |
1554 | 64bit. When -mtune= is used: | |
4eed87de | 1555 | |
76bc74dc L |
1556 | 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and |
1557 | PROCESSOR_GENERIC32, f32_patt will be used. | |
80b8656c L |
1558 | 2. For the rest, alt_patt will be used. |
1559 | ||
1560 | When -mtune= isn't used, alt_patt will be used if | |
22109423 | 1561 | cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will |
76bc74dc | 1562 | be used. |
ccc9c027 L |
1563 | |
1564 | When -march= or .arch is used, we can't use anything beyond | |
1565 | cpu_arch_isa_flags. */ | |
1566 | ||
1567 | if (flag_code == CODE_16BIT) | |
1568 | { | |
3ae729d5 L |
1569 | patt = f16_patt; |
1570 | max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]); | |
1571 | /* Limit number of NOPs to 2 in 16-bit mode. */ | |
1572 | max_number_of_nops = 2; | |
252b5132 | 1573 | } |
33fef721 | 1574 | else |
ccc9c027 | 1575 | { |
fbf3f584 | 1576 | if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN) |
ccc9c027 L |
1577 | { |
1578 | /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ | |
1579 | switch (cpu_arch_tune) | |
1580 | { | |
1581 | case PROCESSOR_UNKNOWN: | |
1582 | /* We use cpu_arch_isa_flags to check if we SHOULD | |
22109423 L |
1583 | optimize with nops. */ |
1584 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1585 | patt = alt_patt; |
ccc9c027 L |
1586 | else |
1587 | patt = f32_patt; | |
1588 | break; | |
ccc9c027 L |
1589 | case PROCESSOR_PENTIUM4: |
1590 | case PROCESSOR_NOCONA: | |
ef05d495 | 1591 | case PROCESSOR_CORE: |
76bc74dc | 1592 | case PROCESSOR_CORE2: |
bd5295b2 | 1593 | case PROCESSOR_COREI7: |
3632d14b | 1594 | case PROCESSOR_L1OM: |
7a9068fe | 1595 | case PROCESSOR_K1OM: |
76bc74dc | 1596 | case PROCESSOR_GENERIC64: |
ccc9c027 L |
1597 | case PROCESSOR_K6: |
1598 | case PROCESSOR_ATHLON: | |
1599 | case PROCESSOR_K8: | |
4eed87de | 1600 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1601 | case PROCESSOR_BD: |
029f3522 | 1602 | case PROCESSOR_ZNVER: |
7b458c12 | 1603 | case PROCESSOR_BT: |
80b8656c | 1604 | patt = alt_patt; |
ccc9c027 | 1605 | break; |
76bc74dc | 1606 | case PROCESSOR_I386: |
ccc9c027 L |
1607 | case PROCESSOR_I486: |
1608 | case PROCESSOR_PENTIUM: | |
2dde1948 | 1609 | case PROCESSOR_PENTIUMPRO: |
81486035 | 1610 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1611 | case PROCESSOR_GENERIC32: |
1612 | patt = f32_patt; | |
1613 | break; | |
4eed87de | 1614 | } |
ccc9c027 L |
1615 | } |
1616 | else | |
1617 | { | |
fbf3f584 | 1618 | switch (fragP->tc_frag_data.tune) |
ccc9c027 L |
1619 | { |
1620 | case PROCESSOR_UNKNOWN: | |
e6a14101 | 1621 | /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be |
ccc9c027 L |
1622 | PROCESSOR_UNKNOWN. */ |
1623 | abort (); | |
1624 | break; | |
1625 | ||
76bc74dc | 1626 | case PROCESSOR_I386: |
ccc9c027 L |
1627 | case PROCESSOR_I486: |
1628 | case PROCESSOR_PENTIUM: | |
81486035 | 1629 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1630 | case PROCESSOR_K6: |
1631 | case PROCESSOR_ATHLON: | |
1632 | case PROCESSOR_K8: | |
4eed87de | 1633 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1634 | case PROCESSOR_BD: |
029f3522 | 1635 | case PROCESSOR_ZNVER: |
7b458c12 | 1636 | case PROCESSOR_BT: |
ccc9c027 L |
1637 | case PROCESSOR_GENERIC32: |
1638 | /* We use cpu_arch_isa_flags to check if we CAN optimize | |
22109423 L |
1639 | with nops. */ |
1640 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1641 | patt = alt_patt; |
ccc9c027 L |
1642 | else |
1643 | patt = f32_patt; | |
1644 | break; | |
76bc74dc L |
1645 | case PROCESSOR_PENTIUMPRO: |
1646 | case PROCESSOR_PENTIUM4: | |
1647 | case PROCESSOR_NOCONA: | |
1648 | case PROCESSOR_CORE: | |
ef05d495 | 1649 | case PROCESSOR_CORE2: |
bd5295b2 | 1650 | case PROCESSOR_COREI7: |
3632d14b | 1651 | case PROCESSOR_L1OM: |
7a9068fe | 1652 | case PROCESSOR_K1OM: |
22109423 | 1653 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) |
80b8656c | 1654 | patt = alt_patt; |
ccc9c027 L |
1655 | else |
1656 | patt = f32_patt; | |
1657 | break; | |
1658 | case PROCESSOR_GENERIC64: | |
80b8656c | 1659 | patt = alt_patt; |
ccc9c027 | 1660 | break; |
4eed87de | 1661 | } |
ccc9c027 L |
1662 | } |
1663 | ||
76bc74dc L |
1664 | if (patt == f32_patt) |
1665 | { | |
3ae729d5 L |
1666 | max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]); |
1667 | /* Limit number of NOPs to 2 for older processors. */ | |
1668 | max_number_of_nops = 2; | |
76bc74dc L |
1669 | } |
1670 | else | |
1671 | { | |
3ae729d5 L |
1672 | max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]); |
1673 | /* Limit number of NOPs to 7 for newer processors. */ | |
1674 | max_number_of_nops = 7; | |
1675 | } | |
1676 | } | |
1677 | ||
1678 | if (limit == 0) | |
1679 | limit = max_single_nop_size; | |
1680 | ||
1681 | if (fragP->fr_type == rs_fill_nop) | |
1682 | { | |
1683 | /* Output NOPs for .nop directive. */ | |
1684 | if (limit > max_single_nop_size) | |
1685 | { | |
1686 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1687 | _("invalid single nop size: %d " | |
1688 | "(expect within [0, %d])"), | |
1689 | limit, max_single_nop_size); | |
1690 | return; | |
1691 | } | |
1692 | } | |
e379e5f3 | 1693 | else if (fragP->fr_type != rs_machine_dependent) |
3ae729d5 L |
1694 | fragP->fr_var = count; |
1695 | ||
1696 | if ((count / max_single_nop_size) > max_number_of_nops) | |
1697 | { | |
1698 | /* Generate jump over NOPs. */ | |
1699 | offsetT disp = count - 2; | |
1700 | if (fits_in_imm7 (disp)) | |
1701 | { | |
1702 | /* Use "jmp disp8" if possible. */ | |
1703 | count = disp; | |
1704 | where[0] = jump_disp8[0]; | |
1705 | where[1] = count; | |
1706 | where += 2; | |
1707 | } | |
1708 | else | |
1709 | { | |
1710 | unsigned int size_of_jump; | |
1711 | ||
1712 | if (flag_code == CODE_16BIT) | |
1713 | { | |
1714 | where[0] = jump16_disp32[0]; | |
1715 | where[1] = jump16_disp32[1]; | |
1716 | size_of_jump = 2; | |
1717 | } | |
1718 | else | |
1719 | { | |
1720 | where[0] = jump32_disp32[0]; | |
1721 | size_of_jump = 1; | |
1722 | } | |
1723 | ||
1724 | count -= size_of_jump + 4; | |
1725 | if (!fits_in_imm31 (count)) | |
1726 | { | |
1727 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1728 | _("jump over nop padding out of range")); | |
1729 | return; | |
1730 | } | |
1731 | ||
1732 | md_number_to_chars (where + size_of_jump, count, 4); | |
1733 | where += size_of_jump + 4; | |
76bc74dc | 1734 | } |
ccc9c027 | 1735 | } |
3ae729d5 L |
1736 | |
1737 | /* Generate multiple NOPs. */ | |
1738 | i386_output_nops (where, patt, count, limit); | |
252b5132 RH |
1739 | } |
1740 | ||
c6fb90c8 | 1741 | static INLINE int |
0dfbf9d7 | 1742 | operand_type_all_zero (const union i386_operand_type *x) |
40fb9820 | 1743 | { |
0dfbf9d7 | 1744 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1745 | { |
1746 | case 3: | |
0dfbf9d7 | 1747 | if (x->array[2]) |
c6fb90c8 | 1748 | return 0; |
1a0670f3 | 1749 | /* Fall through. */ |
c6fb90c8 | 1750 | case 2: |
0dfbf9d7 | 1751 | if (x->array[1]) |
c6fb90c8 | 1752 | return 0; |
1a0670f3 | 1753 | /* Fall through. */ |
c6fb90c8 | 1754 | case 1: |
0dfbf9d7 | 1755 | return !x->array[0]; |
c6fb90c8 L |
1756 | default: |
1757 | abort (); | |
1758 | } | |
40fb9820 L |
1759 | } |
1760 | ||
c6fb90c8 | 1761 | static INLINE void |
0dfbf9d7 | 1762 | operand_type_set (union i386_operand_type *x, unsigned int v) |
40fb9820 | 1763 | { |
0dfbf9d7 | 1764 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1765 | { |
1766 | case 3: | |
0dfbf9d7 | 1767 | x->array[2] = v; |
1a0670f3 | 1768 | /* Fall through. */ |
c6fb90c8 | 1769 | case 2: |
0dfbf9d7 | 1770 | x->array[1] = v; |
1a0670f3 | 1771 | /* Fall through. */ |
c6fb90c8 | 1772 | case 1: |
0dfbf9d7 | 1773 | x->array[0] = v; |
1a0670f3 | 1774 | /* Fall through. */ |
c6fb90c8 L |
1775 | break; |
1776 | default: | |
1777 | abort (); | |
1778 | } | |
bab6aec1 JB |
1779 | |
1780 | x->bitfield.class = ClassNone; | |
75e5731b | 1781 | x->bitfield.instance = InstanceNone; |
c6fb90c8 | 1782 | } |
40fb9820 | 1783 | |
c6fb90c8 | 1784 | static INLINE int |
0dfbf9d7 L |
1785 | operand_type_equal (const union i386_operand_type *x, |
1786 | const union i386_operand_type *y) | |
c6fb90c8 | 1787 | { |
0dfbf9d7 | 1788 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1789 | { |
1790 | case 3: | |
0dfbf9d7 | 1791 | if (x->array[2] != y->array[2]) |
c6fb90c8 | 1792 | return 0; |
1a0670f3 | 1793 | /* Fall through. */ |
c6fb90c8 | 1794 | case 2: |
0dfbf9d7 | 1795 | if (x->array[1] != y->array[1]) |
c6fb90c8 | 1796 | return 0; |
1a0670f3 | 1797 | /* Fall through. */ |
c6fb90c8 | 1798 | case 1: |
0dfbf9d7 | 1799 | return x->array[0] == y->array[0]; |
c6fb90c8 L |
1800 | break; |
1801 | default: | |
1802 | abort (); | |
1803 | } | |
1804 | } | |
40fb9820 | 1805 | |
0dfbf9d7 L |
1806 | static INLINE int |
1807 | cpu_flags_all_zero (const union i386_cpu_flags *x) | |
1808 | { | |
1809 | switch (ARRAY_SIZE(x->array)) | |
1810 | { | |
53467f57 IT |
1811 | case 4: |
1812 | if (x->array[3]) | |
1813 | return 0; | |
1814 | /* Fall through. */ | |
0dfbf9d7 L |
1815 | case 3: |
1816 | if (x->array[2]) | |
1817 | return 0; | |
1a0670f3 | 1818 | /* Fall through. */ |
0dfbf9d7 L |
1819 | case 2: |
1820 | if (x->array[1]) | |
1821 | return 0; | |
1a0670f3 | 1822 | /* Fall through. */ |
0dfbf9d7 L |
1823 | case 1: |
1824 | return !x->array[0]; | |
1825 | default: | |
1826 | abort (); | |
1827 | } | |
1828 | } | |
1829 | ||
0dfbf9d7 L |
1830 | static INLINE int |
1831 | cpu_flags_equal (const union i386_cpu_flags *x, | |
1832 | const union i386_cpu_flags *y) | |
1833 | { | |
1834 | switch (ARRAY_SIZE(x->array)) | |
1835 | { | |
53467f57 IT |
1836 | case 4: |
1837 | if (x->array[3] != y->array[3]) | |
1838 | return 0; | |
1839 | /* Fall through. */ | |
0dfbf9d7 L |
1840 | case 3: |
1841 | if (x->array[2] != y->array[2]) | |
1842 | return 0; | |
1a0670f3 | 1843 | /* Fall through. */ |
0dfbf9d7 L |
1844 | case 2: |
1845 | if (x->array[1] != y->array[1]) | |
1846 | return 0; | |
1a0670f3 | 1847 | /* Fall through. */ |
0dfbf9d7 L |
1848 | case 1: |
1849 | return x->array[0] == y->array[0]; | |
1850 | break; | |
1851 | default: | |
1852 | abort (); | |
1853 | } | |
1854 | } | |
c6fb90c8 L |
1855 | |
1856 | static INLINE int | |
1857 | cpu_flags_check_cpu64 (i386_cpu_flags f) | |
1858 | { | |
1859 | return !((flag_code == CODE_64BIT && f.bitfield.cpuno64) | |
1860 | || (flag_code != CODE_64BIT && f.bitfield.cpu64)); | |
40fb9820 L |
1861 | } |
1862 | ||
c6fb90c8 L |
1863 | static INLINE i386_cpu_flags |
1864 | cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1865 | { |
c6fb90c8 L |
1866 | switch (ARRAY_SIZE (x.array)) |
1867 | { | |
53467f57 IT |
1868 | case 4: |
1869 | x.array [3] &= y.array [3]; | |
1870 | /* Fall through. */ | |
c6fb90c8 L |
1871 | case 3: |
1872 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1873 | /* Fall through. */ |
c6fb90c8 L |
1874 | case 2: |
1875 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1876 | /* Fall through. */ |
c6fb90c8 L |
1877 | case 1: |
1878 | x.array [0] &= y.array [0]; | |
1879 | break; | |
1880 | default: | |
1881 | abort (); | |
1882 | } | |
1883 | return x; | |
1884 | } | |
40fb9820 | 1885 | |
c6fb90c8 L |
1886 | static INLINE i386_cpu_flags |
1887 | cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1888 | { |
c6fb90c8 | 1889 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1890 | { |
53467f57 IT |
1891 | case 4: |
1892 | x.array [3] |= y.array [3]; | |
1893 | /* Fall through. */ | |
c6fb90c8 L |
1894 | case 3: |
1895 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1896 | /* Fall through. */ |
c6fb90c8 L |
1897 | case 2: |
1898 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1899 | /* Fall through. */ |
c6fb90c8 L |
1900 | case 1: |
1901 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1902 | break; |
1903 | default: | |
1904 | abort (); | |
1905 | } | |
40fb9820 L |
1906 | return x; |
1907 | } | |
1908 | ||
309d3373 JB |
1909 | static INLINE i386_cpu_flags |
1910 | cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y) | |
1911 | { | |
1912 | switch (ARRAY_SIZE (x.array)) | |
1913 | { | |
53467f57 IT |
1914 | case 4: |
1915 | x.array [3] &= ~y.array [3]; | |
1916 | /* Fall through. */ | |
309d3373 JB |
1917 | case 3: |
1918 | x.array [2] &= ~y.array [2]; | |
1a0670f3 | 1919 | /* Fall through. */ |
309d3373 JB |
1920 | case 2: |
1921 | x.array [1] &= ~y.array [1]; | |
1a0670f3 | 1922 | /* Fall through. */ |
309d3373 JB |
1923 | case 1: |
1924 | x.array [0] &= ~y.array [0]; | |
1925 | break; | |
1926 | default: | |
1927 | abort (); | |
1928 | } | |
1929 | return x; | |
1930 | } | |
1931 | ||
6c0946d0 JB |
1932 | static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS; |
1933 | ||
c0f3af97 L |
1934 | #define CPU_FLAGS_ARCH_MATCH 0x1 |
1935 | #define CPU_FLAGS_64BIT_MATCH 0x2 | |
1936 | ||
c0f3af97 | 1937 | #define CPU_FLAGS_PERFECT_MATCH \ |
db12e14e | 1938 | (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH) |
c0f3af97 L |
1939 | |
1940 | /* Return CPU flags match bits. */ | |
3629bb00 | 1941 | |
40fb9820 | 1942 | static int |
d3ce72d0 | 1943 | cpu_flags_match (const insn_template *t) |
40fb9820 | 1944 | { |
c0f3af97 L |
1945 | i386_cpu_flags x = t->cpu_flags; |
1946 | int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0; | |
40fb9820 L |
1947 | |
1948 | x.bitfield.cpu64 = 0; | |
1949 | x.bitfield.cpuno64 = 0; | |
1950 | ||
0dfbf9d7 | 1951 | if (cpu_flags_all_zero (&x)) |
c0f3af97 L |
1952 | { |
1953 | /* This instruction is available on all archs. */ | |
db12e14e | 1954 | match |= CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1955 | } |
3629bb00 L |
1956 | else |
1957 | { | |
c0f3af97 | 1958 | /* This instruction is available only on some archs. */ |
3629bb00 L |
1959 | i386_cpu_flags cpu = cpu_arch_flags; |
1960 | ||
ab592e75 JB |
1961 | /* AVX512VL is no standalone feature - match it and then strip it. */ |
1962 | if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl) | |
1963 | return match; | |
1964 | x.bitfield.cpuavx512vl = 0; | |
1965 | ||
3629bb00 | 1966 | cpu = cpu_flags_and (x, cpu); |
c0f3af97 L |
1967 | if (!cpu_flags_all_zero (&cpu)) |
1968 | { | |
57392598 | 1969 | if (x.bitfield.cpuavx) |
a5ff0eb2 | 1970 | { |
929f69fa | 1971 | /* We need to check a few extra flags with AVX. */ |
b9d49817 | 1972 | if (cpu.bitfield.cpuavx |
40d231b4 JB |
1973 | && (!t->opcode_modifier.sse2avx |
1974 | || (sse2avx && !i.prefix[DATA_PREFIX])) | |
b9d49817 | 1975 | && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes) |
929f69fa | 1976 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) |
b9d49817 JB |
1977 | && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul)) |
1978 | match |= CPU_FLAGS_ARCH_MATCH; | |
a5ff0eb2 | 1979 | } |
929f69fa JB |
1980 | else if (x.bitfield.cpuavx512f) |
1981 | { | |
1982 | /* We need to check a few extra flags with AVX512F. */ | |
1983 | if (cpu.bitfield.cpuavx512f | |
1984 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) | |
1985 | && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes) | |
1986 | && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq)) | |
1987 | match |= CPU_FLAGS_ARCH_MATCH; | |
1988 | } | |
a5ff0eb2 | 1989 | else |
db12e14e | 1990 | match |= CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1991 | } |
3629bb00 | 1992 | } |
c0f3af97 | 1993 | return match; |
40fb9820 L |
1994 | } |
1995 | ||
c6fb90c8 L |
1996 | static INLINE i386_operand_type |
1997 | operand_type_and (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1998 | { |
bab6aec1 JB |
1999 | if (x.bitfield.class != y.bitfield.class) |
2000 | x.bitfield.class = ClassNone; | |
75e5731b JB |
2001 | if (x.bitfield.instance != y.bitfield.instance) |
2002 | x.bitfield.instance = InstanceNone; | |
bab6aec1 | 2003 | |
c6fb90c8 L |
2004 | switch (ARRAY_SIZE (x.array)) |
2005 | { | |
2006 | case 3: | |
2007 | x.array [2] &= y.array [2]; | |
1a0670f3 | 2008 | /* Fall through. */ |
c6fb90c8 L |
2009 | case 2: |
2010 | x.array [1] &= y.array [1]; | |
1a0670f3 | 2011 | /* Fall through. */ |
c6fb90c8 L |
2012 | case 1: |
2013 | x.array [0] &= y.array [0]; | |
2014 | break; | |
2015 | default: | |
2016 | abort (); | |
2017 | } | |
2018 | return x; | |
40fb9820 L |
2019 | } |
2020 | ||
73053c1f JB |
2021 | static INLINE i386_operand_type |
2022 | operand_type_and_not (i386_operand_type x, i386_operand_type y) | |
2023 | { | |
bab6aec1 | 2024 | gas_assert (y.bitfield.class == ClassNone); |
75e5731b | 2025 | gas_assert (y.bitfield.instance == InstanceNone); |
bab6aec1 | 2026 | |
73053c1f JB |
2027 | switch (ARRAY_SIZE (x.array)) |
2028 | { | |
2029 | case 3: | |
2030 | x.array [2] &= ~y.array [2]; | |
2031 | /* Fall through. */ | |
2032 | case 2: | |
2033 | x.array [1] &= ~y.array [1]; | |
2034 | /* Fall through. */ | |
2035 | case 1: | |
2036 | x.array [0] &= ~y.array [0]; | |
2037 | break; | |
2038 | default: | |
2039 | abort (); | |
2040 | } | |
2041 | return x; | |
2042 | } | |
2043 | ||
c6fb90c8 L |
2044 | static INLINE i386_operand_type |
2045 | operand_type_or (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 2046 | { |
bab6aec1 JB |
2047 | gas_assert (x.bitfield.class == ClassNone || |
2048 | y.bitfield.class == ClassNone || | |
2049 | x.bitfield.class == y.bitfield.class); | |
75e5731b JB |
2050 | gas_assert (x.bitfield.instance == InstanceNone || |
2051 | y.bitfield.instance == InstanceNone || | |
2052 | x.bitfield.instance == y.bitfield.instance); | |
bab6aec1 | 2053 | |
c6fb90c8 | 2054 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 2055 | { |
c6fb90c8 L |
2056 | case 3: |
2057 | x.array [2] |= y.array [2]; | |
1a0670f3 | 2058 | /* Fall through. */ |
c6fb90c8 L |
2059 | case 2: |
2060 | x.array [1] |= y.array [1]; | |
1a0670f3 | 2061 | /* Fall through. */ |
c6fb90c8 L |
2062 | case 1: |
2063 | x.array [0] |= y.array [0]; | |
40fb9820 L |
2064 | break; |
2065 | default: | |
2066 | abort (); | |
2067 | } | |
c6fb90c8 L |
2068 | return x; |
2069 | } | |
40fb9820 | 2070 | |
c6fb90c8 L |
2071 | static INLINE i386_operand_type |
2072 | operand_type_xor (i386_operand_type x, i386_operand_type y) | |
2073 | { | |
bab6aec1 | 2074 | gas_assert (y.bitfield.class == ClassNone); |
75e5731b | 2075 | gas_assert (y.bitfield.instance == InstanceNone); |
bab6aec1 | 2076 | |
c6fb90c8 L |
2077 | switch (ARRAY_SIZE (x.array)) |
2078 | { | |
2079 | case 3: | |
2080 | x.array [2] ^= y.array [2]; | |
1a0670f3 | 2081 | /* Fall through. */ |
c6fb90c8 L |
2082 | case 2: |
2083 | x.array [1] ^= y.array [1]; | |
1a0670f3 | 2084 | /* Fall through. */ |
c6fb90c8 L |
2085 | case 1: |
2086 | x.array [0] ^= y.array [0]; | |
2087 | break; | |
2088 | default: | |
2089 | abort (); | |
2090 | } | |
40fb9820 L |
2091 | return x; |
2092 | } | |
2093 | ||
40fb9820 L |
2094 | static const i386_operand_type disp16 = OPERAND_TYPE_DISP16; |
2095 | static const i386_operand_type disp32 = OPERAND_TYPE_DISP32; | |
2096 | static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S; | |
2097 | static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32; | |
bab6aec1 JB |
2098 | static const i386_operand_type anydisp = OPERAND_TYPE_ANYDISP; |
2099 | static const i386_operand_type anyimm = OPERAND_TYPE_ANYIMM; | |
40fb9820 | 2100 | static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM; |
43234a1e | 2101 | static const i386_operand_type regmask = OPERAND_TYPE_REGMASK; |
40fb9820 L |
2102 | static const i386_operand_type imm8 = OPERAND_TYPE_IMM8; |
2103 | static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S; | |
2104 | static const i386_operand_type imm16 = OPERAND_TYPE_IMM16; | |
2105 | static const i386_operand_type imm32 = OPERAND_TYPE_IMM32; | |
2106 | static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S; | |
2107 | static const i386_operand_type imm64 = OPERAND_TYPE_IMM64; | |
2108 | static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32; | |
2109 | static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S; | |
2110 | static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S; | |
2111 | ||
2112 | enum operand_type | |
2113 | { | |
2114 | reg, | |
40fb9820 L |
2115 | imm, |
2116 | disp, | |
2117 | anymem | |
2118 | }; | |
2119 | ||
c6fb90c8 | 2120 | static INLINE int |
40fb9820 L |
2121 | operand_type_check (i386_operand_type t, enum operand_type c) |
2122 | { | |
2123 | switch (c) | |
2124 | { | |
2125 | case reg: | |
bab6aec1 | 2126 | return t.bitfield.class == Reg; |
40fb9820 | 2127 | |
40fb9820 L |
2128 | case imm: |
2129 | return (t.bitfield.imm8 | |
2130 | || t.bitfield.imm8s | |
2131 | || t.bitfield.imm16 | |
2132 | || t.bitfield.imm32 | |
2133 | || t.bitfield.imm32s | |
2134 | || t.bitfield.imm64); | |
2135 | ||
2136 | case disp: | |
2137 | return (t.bitfield.disp8 | |
2138 | || t.bitfield.disp16 | |
2139 | || t.bitfield.disp32 | |
2140 | || t.bitfield.disp32s | |
2141 | || t.bitfield.disp64); | |
2142 | ||
2143 | case anymem: | |
2144 | return (t.bitfield.disp8 | |
2145 | || t.bitfield.disp16 | |
2146 | || t.bitfield.disp32 | |
2147 | || t.bitfield.disp32s | |
2148 | || t.bitfield.disp64 | |
2149 | || t.bitfield.baseindex); | |
2150 | ||
2151 | default: | |
2152 | abort (); | |
2153 | } | |
2cfe26b6 AM |
2154 | |
2155 | return 0; | |
40fb9820 L |
2156 | } |
2157 | ||
7a54636a L |
2158 | /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size |
2159 | between operand GIVEN and opeand WANTED for instruction template T. */ | |
5c07affc L |
2160 | |
2161 | static INLINE int | |
7a54636a L |
2162 | match_operand_size (const insn_template *t, unsigned int wanted, |
2163 | unsigned int given) | |
5c07affc | 2164 | { |
3ac21baa JB |
2165 | return !((i.types[given].bitfield.byte |
2166 | && !t->operand_types[wanted].bitfield.byte) | |
2167 | || (i.types[given].bitfield.word | |
2168 | && !t->operand_types[wanted].bitfield.word) | |
2169 | || (i.types[given].bitfield.dword | |
2170 | && !t->operand_types[wanted].bitfield.dword) | |
2171 | || (i.types[given].bitfield.qword | |
2172 | && !t->operand_types[wanted].bitfield.qword) | |
2173 | || (i.types[given].bitfield.tbyte | |
2174 | && !t->operand_types[wanted].bitfield.tbyte)); | |
5c07affc L |
2175 | } |
2176 | ||
dd40ce22 L |
2177 | /* Return 1 if there is no conflict in SIMD register between operand |
2178 | GIVEN and opeand WANTED for instruction template T. */ | |
1b54b8d7 JB |
2179 | |
2180 | static INLINE int | |
dd40ce22 L |
2181 | match_simd_size (const insn_template *t, unsigned int wanted, |
2182 | unsigned int given) | |
1b54b8d7 | 2183 | { |
3ac21baa JB |
2184 | return !((i.types[given].bitfield.xmmword |
2185 | && !t->operand_types[wanted].bitfield.xmmword) | |
2186 | || (i.types[given].bitfield.ymmword | |
2187 | && !t->operand_types[wanted].bitfield.ymmword) | |
2188 | || (i.types[given].bitfield.zmmword | |
260cd341 LC |
2189 | && !t->operand_types[wanted].bitfield.zmmword) |
2190 | || (i.types[given].bitfield.tmmword | |
2191 | && !t->operand_types[wanted].bitfield.tmmword)); | |
1b54b8d7 JB |
2192 | } |
2193 | ||
7a54636a L |
2194 | /* Return 1 if there is no conflict in any size between operand GIVEN |
2195 | and opeand WANTED for instruction template T. */ | |
5c07affc L |
2196 | |
2197 | static INLINE int | |
dd40ce22 L |
2198 | match_mem_size (const insn_template *t, unsigned int wanted, |
2199 | unsigned int given) | |
5c07affc | 2200 | { |
7a54636a | 2201 | return (match_operand_size (t, wanted, given) |
3ac21baa | 2202 | && !((i.types[given].bitfield.unspecified |
5273a3cd | 2203 | && !i.broadcast.type |
3ac21baa JB |
2204 | && !t->operand_types[wanted].bitfield.unspecified) |
2205 | || (i.types[given].bitfield.fword | |
2206 | && !t->operand_types[wanted].bitfield.fword) | |
1b54b8d7 JB |
2207 | /* For scalar opcode templates to allow register and memory |
2208 | operands at the same time, some special casing is needed | |
d6793fa1 JB |
2209 | here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and |
2210 | down-conversion vpmov*. */ | |
3528c362 | 2211 | || ((t->operand_types[wanted].bitfield.class == RegSIMD |
bc49bfd8 JB |
2212 | && t->operand_types[wanted].bitfield.byte |
2213 | + t->operand_types[wanted].bitfield.word | |
2214 | + t->operand_types[wanted].bitfield.dword | |
2215 | + t->operand_types[wanted].bitfield.qword | |
2216 | > !!t->opcode_modifier.broadcast) | |
3ac21baa JB |
2217 | ? (i.types[given].bitfield.xmmword |
2218 | || i.types[given].bitfield.ymmword | |
2219 | || i.types[given].bitfield.zmmword) | |
2220 | : !match_simd_size(t, wanted, given)))); | |
5c07affc L |
2221 | } |
2222 | ||
3ac21baa JB |
2223 | /* Return value has MATCH_STRAIGHT set if there is no size conflict on any |
2224 | operands for instruction template T, and it has MATCH_REVERSE set if there | |
2225 | is no size conflict on any operands for the template with operands reversed | |
2226 | (and the template allows for reversing in the first place). */ | |
5c07affc | 2227 | |
3ac21baa JB |
2228 | #define MATCH_STRAIGHT 1 |
2229 | #define MATCH_REVERSE 2 | |
2230 | ||
2231 | static INLINE unsigned int | |
d3ce72d0 | 2232 | operand_size_match (const insn_template *t) |
5c07affc | 2233 | { |
3ac21baa | 2234 | unsigned int j, match = MATCH_STRAIGHT; |
5c07affc | 2235 | |
0cfa3eb3 | 2236 | /* Don't check non-absolute jump instructions. */ |
5c07affc | 2237 | if (t->opcode_modifier.jump |
0cfa3eb3 | 2238 | && t->opcode_modifier.jump != JUMP_ABSOLUTE) |
5c07affc L |
2239 | return match; |
2240 | ||
2241 | /* Check memory and accumulator operand size. */ | |
2242 | for (j = 0; j < i.operands; j++) | |
2243 | { | |
3528c362 JB |
2244 | if (i.types[j].bitfield.class != Reg |
2245 | && i.types[j].bitfield.class != RegSIMD | |
601e8564 | 2246 | && t->opcode_modifier.anysize) |
5c07affc L |
2247 | continue; |
2248 | ||
bab6aec1 | 2249 | if (t->operand_types[j].bitfield.class == Reg |
7a54636a | 2250 | && !match_operand_size (t, j, j)) |
5c07affc L |
2251 | { |
2252 | match = 0; | |
2253 | break; | |
2254 | } | |
2255 | ||
3528c362 | 2256 | if (t->operand_types[j].bitfield.class == RegSIMD |
3ac21baa | 2257 | && !match_simd_size (t, j, j)) |
1b54b8d7 JB |
2258 | { |
2259 | match = 0; | |
2260 | break; | |
2261 | } | |
2262 | ||
75e5731b | 2263 | if (t->operand_types[j].bitfield.instance == Accum |
7a54636a | 2264 | && (!match_operand_size (t, j, j) || !match_simd_size (t, j, j))) |
1b54b8d7 JB |
2265 | { |
2266 | match = 0; | |
2267 | break; | |
2268 | } | |
2269 | ||
c48dadc9 | 2270 | if ((i.flags[j] & Operand_Mem) && !match_mem_size (t, j, j)) |
5c07affc L |
2271 | { |
2272 | match = 0; | |
2273 | break; | |
2274 | } | |
2275 | } | |
2276 | ||
3ac21baa | 2277 | if (!t->opcode_modifier.d) |
891edac4 | 2278 | { |
dc1e8a47 | 2279 | mismatch: |
3ac21baa JB |
2280 | if (!match) |
2281 | i.error = operand_size_mismatch; | |
2282 | return match; | |
891edac4 | 2283 | } |
5c07affc L |
2284 | |
2285 | /* Check reverse. */ | |
f5eb1d70 | 2286 | gas_assert (i.operands >= 2 && i.operands <= 3); |
5c07affc | 2287 | |
f5eb1d70 | 2288 | for (j = 0; j < i.operands; j++) |
5c07affc | 2289 | { |
f5eb1d70 JB |
2290 | unsigned int given = i.operands - j - 1; |
2291 | ||
bab6aec1 | 2292 | if (t->operand_types[j].bitfield.class == Reg |
f5eb1d70 | 2293 | && !match_operand_size (t, j, given)) |
891edac4 | 2294 | goto mismatch; |
5c07affc | 2295 | |
3528c362 | 2296 | if (t->operand_types[j].bitfield.class == RegSIMD |
f5eb1d70 | 2297 | && !match_simd_size (t, j, given)) |
dbbc8b7e JB |
2298 | goto mismatch; |
2299 | ||
75e5731b | 2300 | if (t->operand_types[j].bitfield.instance == Accum |
f5eb1d70 JB |
2301 | && (!match_operand_size (t, j, given) |
2302 | || !match_simd_size (t, j, given))) | |
dbbc8b7e JB |
2303 | goto mismatch; |
2304 | ||
f5eb1d70 | 2305 | if ((i.flags[given] & Operand_Mem) && !match_mem_size (t, j, given)) |
891edac4 | 2306 | goto mismatch; |
5c07affc L |
2307 | } |
2308 | ||
3ac21baa | 2309 | return match | MATCH_REVERSE; |
5c07affc L |
2310 | } |
2311 | ||
c6fb90c8 | 2312 | static INLINE int |
40fb9820 L |
2313 | operand_type_match (i386_operand_type overlap, |
2314 | i386_operand_type given) | |
2315 | { | |
2316 | i386_operand_type temp = overlap; | |
2317 | ||
7d5e4556 | 2318 | temp.bitfield.unspecified = 0; |
5c07affc L |
2319 | temp.bitfield.byte = 0; |
2320 | temp.bitfield.word = 0; | |
2321 | temp.bitfield.dword = 0; | |
2322 | temp.bitfield.fword = 0; | |
2323 | temp.bitfield.qword = 0; | |
2324 | temp.bitfield.tbyte = 0; | |
2325 | temp.bitfield.xmmword = 0; | |
c0f3af97 | 2326 | temp.bitfield.ymmword = 0; |
43234a1e | 2327 | temp.bitfield.zmmword = 0; |
260cd341 | 2328 | temp.bitfield.tmmword = 0; |
0dfbf9d7 | 2329 | if (operand_type_all_zero (&temp)) |
891edac4 | 2330 | goto mismatch; |
40fb9820 | 2331 | |
6f2f06be | 2332 | if (given.bitfield.baseindex == overlap.bitfield.baseindex) |
891edac4 L |
2333 | return 1; |
2334 | ||
dc1e8a47 | 2335 | mismatch: |
a65babc9 | 2336 | i.error = operand_type_mismatch; |
891edac4 | 2337 | return 0; |
40fb9820 L |
2338 | } |
2339 | ||
7d5e4556 | 2340 | /* If given types g0 and g1 are registers they must be of the same type |
10c17abd | 2341 | unless the expected operand type register overlap is null. |
5de4d9ef | 2342 | Some Intel syntax memory operand size checking also happens here. */ |
40fb9820 | 2343 | |
c6fb90c8 | 2344 | static INLINE int |
dc821c5f | 2345 | operand_type_register_match (i386_operand_type g0, |
40fb9820 | 2346 | i386_operand_type t0, |
40fb9820 L |
2347 | i386_operand_type g1, |
2348 | i386_operand_type t1) | |
2349 | { | |
bab6aec1 | 2350 | if (g0.bitfield.class != Reg |
3528c362 | 2351 | && g0.bitfield.class != RegSIMD |
10c17abd JB |
2352 | && (!operand_type_check (g0, anymem) |
2353 | || g0.bitfield.unspecified | |
5de4d9ef JB |
2354 | || (t0.bitfield.class != Reg |
2355 | && t0.bitfield.class != RegSIMD))) | |
40fb9820 L |
2356 | return 1; |
2357 | ||
bab6aec1 | 2358 | if (g1.bitfield.class != Reg |
3528c362 | 2359 | && g1.bitfield.class != RegSIMD |
10c17abd JB |
2360 | && (!operand_type_check (g1, anymem) |
2361 | || g1.bitfield.unspecified | |
5de4d9ef JB |
2362 | || (t1.bitfield.class != Reg |
2363 | && t1.bitfield.class != RegSIMD))) | |
40fb9820 L |
2364 | return 1; |
2365 | ||
dc821c5f JB |
2366 | if (g0.bitfield.byte == g1.bitfield.byte |
2367 | && g0.bitfield.word == g1.bitfield.word | |
2368 | && g0.bitfield.dword == g1.bitfield.dword | |
10c17abd JB |
2369 | && g0.bitfield.qword == g1.bitfield.qword |
2370 | && g0.bitfield.xmmword == g1.bitfield.xmmword | |
2371 | && g0.bitfield.ymmword == g1.bitfield.ymmword | |
2372 | && g0.bitfield.zmmword == g1.bitfield.zmmword) | |
40fb9820 L |
2373 | return 1; |
2374 | ||
dc821c5f JB |
2375 | if (!(t0.bitfield.byte & t1.bitfield.byte) |
2376 | && !(t0.bitfield.word & t1.bitfield.word) | |
2377 | && !(t0.bitfield.dword & t1.bitfield.dword) | |
10c17abd JB |
2378 | && !(t0.bitfield.qword & t1.bitfield.qword) |
2379 | && !(t0.bitfield.xmmword & t1.bitfield.xmmword) | |
2380 | && !(t0.bitfield.ymmword & t1.bitfield.ymmword) | |
2381 | && !(t0.bitfield.zmmword & t1.bitfield.zmmword)) | |
891edac4 L |
2382 | return 1; |
2383 | ||
a65babc9 | 2384 | i.error = register_type_mismatch; |
891edac4 L |
2385 | |
2386 | return 0; | |
40fb9820 L |
2387 | } |
2388 | ||
4c692bc7 JB |
2389 | static INLINE unsigned int |
2390 | register_number (const reg_entry *r) | |
2391 | { | |
2392 | unsigned int nr = r->reg_num; | |
2393 | ||
2394 | if (r->reg_flags & RegRex) | |
2395 | nr += 8; | |
2396 | ||
200cbe0f L |
2397 | if (r->reg_flags & RegVRex) |
2398 | nr += 16; | |
2399 | ||
4c692bc7 JB |
2400 | return nr; |
2401 | } | |
2402 | ||
252b5132 | 2403 | static INLINE unsigned int |
40fb9820 | 2404 | mode_from_disp_size (i386_operand_type t) |
252b5132 | 2405 | { |
b5014f7a | 2406 | if (t.bitfield.disp8) |
40fb9820 L |
2407 | return 1; |
2408 | else if (t.bitfield.disp16 | |
2409 | || t.bitfield.disp32 | |
2410 | || t.bitfield.disp32s) | |
2411 | return 2; | |
2412 | else | |
2413 | return 0; | |
252b5132 RH |
2414 | } |
2415 | ||
2416 | static INLINE int | |
65879393 | 2417 | fits_in_signed_byte (addressT num) |
252b5132 | 2418 | { |
65879393 | 2419 | return num + 0x80 <= 0xff; |
47926f60 | 2420 | } |
252b5132 RH |
2421 | |
2422 | static INLINE int | |
65879393 | 2423 | fits_in_unsigned_byte (addressT num) |
252b5132 | 2424 | { |
65879393 | 2425 | return num <= 0xff; |
47926f60 | 2426 | } |
252b5132 RH |
2427 | |
2428 | static INLINE int | |
65879393 | 2429 | fits_in_unsigned_word (addressT num) |
252b5132 | 2430 | { |
65879393 | 2431 | return num <= 0xffff; |
47926f60 | 2432 | } |
252b5132 RH |
2433 | |
2434 | static INLINE int | |
65879393 | 2435 | fits_in_signed_word (addressT num) |
252b5132 | 2436 | { |
65879393 | 2437 | return num + 0x8000 <= 0xffff; |
47926f60 | 2438 | } |
2a962e6d | 2439 | |
3e73aa7c | 2440 | static INLINE int |
65879393 | 2441 | fits_in_signed_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2442 | { |
2443 | #ifndef BFD64 | |
2444 | return 1; | |
2445 | #else | |
65879393 | 2446 | return num + 0x80000000 <= 0xffffffff; |
3e73aa7c JH |
2447 | #endif |
2448 | } /* fits_in_signed_long() */ | |
2a962e6d | 2449 | |
3e73aa7c | 2450 | static INLINE int |
65879393 | 2451 | fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2452 | { |
2453 | #ifndef BFD64 | |
2454 | return 1; | |
2455 | #else | |
65879393 | 2456 | return num <= 0xffffffff; |
3e73aa7c JH |
2457 | #endif |
2458 | } /* fits_in_unsigned_long() */ | |
252b5132 | 2459 | |
a442cac5 JB |
2460 | static INLINE valueT extend_to_32bit_address (addressT num) |
2461 | { | |
2462 | #ifdef BFD64 | |
2463 | if (fits_in_unsigned_long(num)) | |
2464 | return (num ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
2465 | ||
2466 | if (!fits_in_signed_long (num)) | |
2467 | return num & 0xffffffff; | |
2468 | #endif | |
2469 | ||
2470 | return num; | |
2471 | } | |
2472 | ||
43234a1e | 2473 | static INLINE int |
b5014f7a | 2474 | fits_in_disp8 (offsetT num) |
43234a1e L |
2475 | { |
2476 | int shift = i.memshift; | |
2477 | unsigned int mask; | |
2478 | ||
2479 | if (shift == -1) | |
2480 | abort (); | |
2481 | ||
2482 | mask = (1 << shift) - 1; | |
2483 | ||
2484 | /* Return 0 if NUM isn't properly aligned. */ | |
2485 | if ((num & mask)) | |
2486 | return 0; | |
2487 | ||
2488 | /* Check if NUM will fit in 8bit after shift. */ | |
2489 | return fits_in_signed_byte (num >> shift); | |
2490 | } | |
2491 | ||
a683cc34 SP |
2492 | static INLINE int |
2493 | fits_in_imm4 (offsetT num) | |
2494 | { | |
2495 | return (num & 0xf) == num; | |
2496 | } | |
2497 | ||
40fb9820 | 2498 | static i386_operand_type |
e3bb37b5 | 2499 | smallest_imm_type (offsetT num) |
252b5132 | 2500 | { |
40fb9820 | 2501 | i386_operand_type t; |
7ab9ffdd | 2502 | |
0dfbf9d7 | 2503 | operand_type_set (&t, 0); |
40fb9820 L |
2504 | t.bitfield.imm64 = 1; |
2505 | ||
2506 | if (cpu_arch_tune != PROCESSOR_I486 && num == 1) | |
e413e4e9 AM |
2507 | { |
2508 | /* This code is disabled on the 486 because all the Imm1 forms | |
2509 | in the opcode table are slower on the i486. They're the | |
2510 | versions with the implicitly specified single-position | |
2511 | displacement, which has another syntax if you really want to | |
2512 | use that form. */ | |
40fb9820 L |
2513 | t.bitfield.imm1 = 1; |
2514 | t.bitfield.imm8 = 1; | |
2515 | t.bitfield.imm8s = 1; | |
2516 | t.bitfield.imm16 = 1; | |
2517 | t.bitfield.imm32 = 1; | |
2518 | t.bitfield.imm32s = 1; | |
2519 | } | |
2520 | else if (fits_in_signed_byte (num)) | |
2521 | { | |
2522 | t.bitfield.imm8 = 1; | |
2523 | t.bitfield.imm8s = 1; | |
2524 | t.bitfield.imm16 = 1; | |
2525 | t.bitfield.imm32 = 1; | |
2526 | t.bitfield.imm32s = 1; | |
2527 | } | |
2528 | else if (fits_in_unsigned_byte (num)) | |
2529 | { | |
2530 | t.bitfield.imm8 = 1; | |
2531 | t.bitfield.imm16 = 1; | |
2532 | t.bitfield.imm32 = 1; | |
2533 | t.bitfield.imm32s = 1; | |
2534 | } | |
2535 | else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
2536 | { | |
2537 | t.bitfield.imm16 = 1; | |
2538 | t.bitfield.imm32 = 1; | |
2539 | t.bitfield.imm32s = 1; | |
2540 | } | |
2541 | else if (fits_in_signed_long (num)) | |
2542 | { | |
2543 | t.bitfield.imm32 = 1; | |
2544 | t.bitfield.imm32s = 1; | |
2545 | } | |
2546 | else if (fits_in_unsigned_long (num)) | |
2547 | t.bitfield.imm32 = 1; | |
2548 | ||
2549 | return t; | |
47926f60 | 2550 | } |
252b5132 | 2551 | |
847f7ad4 | 2552 | static offsetT |
e3bb37b5 | 2553 | offset_in_range (offsetT val, int size) |
847f7ad4 | 2554 | { |
508866be | 2555 | addressT mask; |
ba2adb93 | 2556 | |
847f7ad4 AM |
2557 | switch (size) |
2558 | { | |
508866be L |
2559 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
2560 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 2561 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
3e73aa7c JH |
2562 | #ifdef BFD64 |
2563 | case 8: mask = ((addressT) 2 << 63) - 1; break; | |
2564 | #endif | |
47926f60 | 2565 | default: abort (); |
847f7ad4 AM |
2566 | } |
2567 | ||
47926f60 | 2568 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
847f7ad4 AM |
2569 | { |
2570 | char buf1[40], buf2[40]; | |
2571 | ||
9a8041fd JB |
2572 | bfd_sprintf_vma (stdoutput, buf1, val); |
2573 | bfd_sprintf_vma (stdoutput, buf2, val & mask); | |
847f7ad4 AM |
2574 | as_warn (_("%s shortened to %s"), buf1, buf2); |
2575 | } | |
2576 | return val & mask; | |
2577 | } | |
2578 | ||
c32fa91d L |
2579 | enum PREFIX_GROUP |
2580 | { | |
2581 | PREFIX_EXIST = 0, | |
2582 | PREFIX_LOCK, | |
2583 | PREFIX_REP, | |
04ef582a | 2584 | PREFIX_DS, |
c32fa91d L |
2585 | PREFIX_OTHER |
2586 | }; | |
2587 | ||
2588 | /* Returns | |
2589 | a. PREFIX_EXIST if attempting to add a prefix where one from the | |
2590 | same class already exists. | |
2591 | b. PREFIX_LOCK if lock prefix is added. | |
2592 | c. PREFIX_REP if rep/repne prefix is added. | |
04ef582a L |
2593 | d. PREFIX_DS if ds prefix is added. |
2594 | e. PREFIX_OTHER if other prefix is added. | |
c32fa91d L |
2595 | */ |
2596 | ||
2597 | static enum PREFIX_GROUP | |
e3bb37b5 | 2598 | add_prefix (unsigned int prefix) |
252b5132 | 2599 | { |
c32fa91d | 2600 | enum PREFIX_GROUP ret = PREFIX_OTHER; |
b1905489 | 2601 | unsigned int q; |
252b5132 | 2602 | |
29b0f896 AM |
2603 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
2604 | && flag_code == CODE_64BIT) | |
b1905489 | 2605 | { |
161a04f6 | 2606 | if ((i.prefix[REX_PREFIX] & prefix & REX_W) |
44846f29 JB |
2607 | || (i.prefix[REX_PREFIX] & prefix & REX_R) |
2608 | || (i.prefix[REX_PREFIX] & prefix & REX_X) | |
2609 | || (i.prefix[REX_PREFIX] & prefix & REX_B)) | |
c32fa91d | 2610 | ret = PREFIX_EXIST; |
b1905489 JB |
2611 | q = REX_PREFIX; |
2612 | } | |
3e73aa7c | 2613 | else |
b1905489 JB |
2614 | { |
2615 | switch (prefix) | |
2616 | { | |
2617 | default: | |
2618 | abort (); | |
2619 | ||
b1905489 | 2620 | case DS_PREFIX_OPCODE: |
04ef582a L |
2621 | ret = PREFIX_DS; |
2622 | /* Fall through. */ | |
2623 | case CS_PREFIX_OPCODE: | |
b1905489 JB |
2624 | case ES_PREFIX_OPCODE: |
2625 | case FS_PREFIX_OPCODE: | |
2626 | case GS_PREFIX_OPCODE: | |
2627 | case SS_PREFIX_OPCODE: | |
2628 | q = SEG_PREFIX; | |
2629 | break; | |
2630 | ||
2631 | case REPNE_PREFIX_OPCODE: | |
2632 | case REPE_PREFIX_OPCODE: | |
c32fa91d L |
2633 | q = REP_PREFIX; |
2634 | ret = PREFIX_REP; | |
2635 | break; | |
2636 | ||
b1905489 | 2637 | case LOCK_PREFIX_OPCODE: |
c32fa91d L |
2638 | q = LOCK_PREFIX; |
2639 | ret = PREFIX_LOCK; | |
b1905489 JB |
2640 | break; |
2641 | ||
2642 | case FWAIT_OPCODE: | |
2643 | q = WAIT_PREFIX; | |
2644 | break; | |
2645 | ||
2646 | case ADDR_PREFIX_OPCODE: | |
2647 | q = ADDR_PREFIX; | |
2648 | break; | |
2649 | ||
2650 | case DATA_PREFIX_OPCODE: | |
2651 | q = DATA_PREFIX; | |
2652 | break; | |
2653 | } | |
2654 | if (i.prefix[q] != 0) | |
c32fa91d | 2655 | ret = PREFIX_EXIST; |
b1905489 | 2656 | } |
252b5132 | 2657 | |
b1905489 | 2658 | if (ret) |
252b5132 | 2659 | { |
b1905489 JB |
2660 | if (!i.prefix[q]) |
2661 | ++i.prefixes; | |
2662 | i.prefix[q] |= prefix; | |
252b5132 | 2663 | } |
b1905489 JB |
2664 | else |
2665 | as_bad (_("same type of prefix used twice")); | |
252b5132 | 2666 | |
252b5132 RH |
2667 | return ret; |
2668 | } | |
2669 | ||
2670 | static void | |
78f12dd3 | 2671 | update_code_flag (int value, int check) |
eecb386c | 2672 | { |
78f12dd3 L |
2673 | PRINTF_LIKE ((*as_error)); |
2674 | ||
1e9cc1c2 | 2675 | flag_code = (enum flag_code) value; |
40fb9820 L |
2676 | if (flag_code == CODE_64BIT) |
2677 | { | |
2678 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2679 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
40fb9820 L |
2680 | } |
2681 | else | |
2682 | { | |
2683 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2684 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
40fb9820 L |
2685 | } |
2686 | if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm ) | |
3e73aa7c | 2687 | { |
78f12dd3 L |
2688 | if (check) |
2689 | as_error = as_fatal; | |
2690 | else | |
2691 | as_error = as_bad; | |
2692 | (*as_error) (_("64bit mode not supported on `%s'."), | |
2693 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2694 | } |
40fb9820 | 2695 | if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) |
3e73aa7c | 2696 | { |
78f12dd3 L |
2697 | if (check) |
2698 | as_error = as_fatal; | |
2699 | else | |
2700 | as_error = as_bad; | |
2701 | (*as_error) (_("32bit mode not supported on `%s'."), | |
2702 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2703 | } |
eecb386c AM |
2704 | stackop_size = '\0'; |
2705 | } | |
2706 | ||
78f12dd3 L |
2707 | static void |
2708 | set_code_flag (int value) | |
2709 | { | |
2710 | update_code_flag (value, 0); | |
2711 | } | |
2712 | ||
eecb386c | 2713 | static void |
e3bb37b5 | 2714 | set_16bit_gcc_code_flag (int new_code_flag) |
252b5132 | 2715 | { |
1e9cc1c2 | 2716 | flag_code = (enum flag_code) new_code_flag; |
40fb9820 L |
2717 | if (flag_code != CODE_16BIT) |
2718 | abort (); | |
2719 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2720 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
9306ca4a | 2721 | stackop_size = LONG_MNEM_SUFFIX; |
252b5132 RH |
2722 | } |
2723 | ||
2724 | static void | |
e3bb37b5 | 2725 | set_intel_syntax (int syntax_flag) |
252b5132 RH |
2726 | { |
2727 | /* Find out if register prefixing is specified. */ | |
2728 | int ask_naked_reg = 0; | |
2729 | ||
2730 | SKIP_WHITESPACE (); | |
29b0f896 | 2731 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
252b5132 | 2732 | { |
d02603dc NC |
2733 | char *string; |
2734 | int e = get_symbol_name (&string); | |
252b5132 | 2735 | |
47926f60 | 2736 | if (strcmp (string, "prefix") == 0) |
252b5132 | 2737 | ask_naked_reg = 1; |
47926f60 | 2738 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
2739 | ask_naked_reg = -1; |
2740 | else | |
d0b47220 | 2741 | as_bad (_("bad argument to syntax directive.")); |
d02603dc | 2742 | (void) restore_line_pointer (e); |
252b5132 RH |
2743 | } |
2744 | demand_empty_rest_of_line (); | |
c3332e24 | 2745 | |
252b5132 RH |
2746 | intel_syntax = syntax_flag; |
2747 | ||
2748 | if (ask_naked_reg == 0) | |
f86103b7 AM |
2749 | allow_naked_reg = (intel_syntax |
2750 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); | |
252b5132 RH |
2751 | else |
2752 | allow_naked_reg = (ask_naked_reg < 0); | |
9306ca4a | 2753 | |
ee86248c | 2754 | expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0); |
7ab9ffdd | 2755 | |
e4a3b5a4 | 2756 | identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; |
9306ca4a | 2757 | identifier_chars['$'] = intel_syntax ? '$' : 0; |
e4a3b5a4 | 2758 | register_prefix = allow_naked_reg ? "" : "%"; |
252b5132 RH |
2759 | } |
2760 | ||
1efbbeb4 L |
2761 | static void |
2762 | set_intel_mnemonic (int mnemonic_flag) | |
2763 | { | |
e1d4d893 | 2764 | intel_mnemonic = mnemonic_flag; |
1efbbeb4 L |
2765 | } |
2766 | ||
db51cc60 L |
2767 | static void |
2768 | set_allow_index_reg (int flag) | |
2769 | { | |
2770 | allow_index_reg = flag; | |
2771 | } | |
2772 | ||
cb19c032 | 2773 | static void |
7bab8ab5 | 2774 | set_check (int what) |
cb19c032 | 2775 | { |
7bab8ab5 JB |
2776 | enum check_kind *kind; |
2777 | const char *str; | |
2778 | ||
2779 | if (what) | |
2780 | { | |
2781 | kind = &operand_check; | |
2782 | str = "operand"; | |
2783 | } | |
2784 | else | |
2785 | { | |
2786 | kind = &sse_check; | |
2787 | str = "sse"; | |
2788 | } | |
2789 | ||
cb19c032 L |
2790 | SKIP_WHITESPACE (); |
2791 | ||
2792 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
2793 | { | |
d02603dc NC |
2794 | char *string; |
2795 | int e = get_symbol_name (&string); | |
cb19c032 L |
2796 | |
2797 | if (strcmp (string, "none") == 0) | |
7bab8ab5 | 2798 | *kind = check_none; |
cb19c032 | 2799 | else if (strcmp (string, "warning") == 0) |
7bab8ab5 | 2800 | *kind = check_warning; |
cb19c032 | 2801 | else if (strcmp (string, "error") == 0) |
7bab8ab5 | 2802 | *kind = check_error; |
cb19c032 | 2803 | else |
7bab8ab5 | 2804 | as_bad (_("bad argument to %s_check directive."), str); |
d02603dc | 2805 | (void) restore_line_pointer (e); |
cb19c032 L |
2806 | } |
2807 | else | |
7bab8ab5 | 2808 | as_bad (_("missing argument for %s_check directive"), str); |
cb19c032 L |
2809 | |
2810 | demand_empty_rest_of_line (); | |
2811 | } | |
2812 | ||
8a9036a4 L |
2813 | static void |
2814 | check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED, | |
1e9cc1c2 | 2815 | i386_cpu_flags new_flag ATTRIBUTE_UNUSED) |
8a9036a4 L |
2816 | { |
2817 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2818 | static const char *arch; | |
2819 | ||
2820 | /* Intel LIOM is only supported on ELF. */ | |
2821 | if (!IS_ELF) | |
2822 | return; | |
2823 | ||
2824 | if (!arch) | |
2825 | { | |
2826 | /* Use cpu_arch_name if it is set in md_parse_option. Otherwise | |
2827 | use default_arch. */ | |
2828 | arch = cpu_arch_name; | |
2829 | if (!arch) | |
2830 | arch = default_arch; | |
2831 | } | |
2832 | ||
81486035 L |
2833 | /* If we are targeting Intel MCU, we must enable it. */ |
2834 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU | |
2835 | || new_flag.bitfield.cpuiamcu) | |
2836 | return; | |
2837 | ||
3632d14b | 2838 | /* If we are targeting Intel L1OM, we must enable it. */ |
8a9036a4 | 2839 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM |
1e9cc1c2 | 2840 | || new_flag.bitfield.cpul1om) |
8a9036a4 | 2841 | return; |
76ba9986 | 2842 | |
7a9068fe L |
2843 | /* If we are targeting Intel K1OM, we must enable it. */ |
2844 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM | |
2845 | || new_flag.bitfield.cpuk1om) | |
2846 | return; | |
2847 | ||
8a9036a4 L |
2848 | as_bad (_("`%s' is not supported on `%s'"), name, arch); |
2849 | #endif | |
2850 | } | |
2851 | ||
e413e4e9 | 2852 | static void |
e3bb37b5 | 2853 | set_cpu_arch (int dummy ATTRIBUTE_UNUSED) |
e413e4e9 | 2854 | { |
47926f60 | 2855 | SKIP_WHITESPACE (); |
e413e4e9 | 2856 | |
29b0f896 | 2857 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
e413e4e9 | 2858 | { |
d02603dc NC |
2859 | char *string; |
2860 | int e = get_symbol_name (&string); | |
91d6fa6a | 2861 | unsigned int j; |
40fb9820 | 2862 | i386_cpu_flags flags; |
e413e4e9 | 2863 | |
91d6fa6a | 2864 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
e413e4e9 | 2865 | { |
91d6fa6a | 2866 | if (strcmp (string, cpu_arch[j].name) == 0) |
e413e4e9 | 2867 | { |
91d6fa6a | 2868 | check_cpu_arch_compatible (string, cpu_arch[j].flags); |
8a9036a4 | 2869 | |
5c6af06e JB |
2870 | if (*string != '.') |
2871 | { | |
91d6fa6a | 2872 | cpu_arch_name = cpu_arch[j].name; |
5c6af06e | 2873 | cpu_sub_arch_name = NULL; |
91d6fa6a | 2874 | cpu_arch_flags = cpu_arch[j].flags; |
40fb9820 L |
2875 | if (flag_code == CODE_64BIT) |
2876 | { | |
2877 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2878 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
2879 | } | |
2880 | else | |
2881 | { | |
2882 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2883 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
2884 | } | |
91d6fa6a NC |
2885 | cpu_arch_isa = cpu_arch[j].type; |
2886 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
ccc9c027 L |
2887 | if (!cpu_arch_tune_set) |
2888 | { | |
2889 | cpu_arch_tune = cpu_arch_isa; | |
2890 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
2891 | } | |
5c6af06e JB |
2892 | break; |
2893 | } | |
40fb9820 | 2894 | |
293f5f65 L |
2895 | flags = cpu_flags_or (cpu_arch_flags, |
2896 | cpu_arch[j].flags); | |
81486035 | 2897 | |
5b64d091 | 2898 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
5c6af06e | 2899 | { |
6305a203 L |
2900 | if (cpu_sub_arch_name) |
2901 | { | |
2902 | char *name = cpu_sub_arch_name; | |
2903 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 2904 | cpu_arch[j].name, |
1bf57e9f | 2905 | (const char *) NULL); |
6305a203 L |
2906 | free (name); |
2907 | } | |
2908 | else | |
91d6fa6a | 2909 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
40fb9820 | 2910 | cpu_arch_flags = flags; |
a586129e | 2911 | cpu_arch_isa_flags = flags; |
5c6af06e | 2912 | } |
0089dace L |
2913 | else |
2914 | cpu_arch_isa_flags | |
2915 | = cpu_flags_or (cpu_arch_isa_flags, | |
2916 | cpu_arch[j].flags); | |
d02603dc | 2917 | (void) restore_line_pointer (e); |
5c6af06e JB |
2918 | demand_empty_rest_of_line (); |
2919 | return; | |
e413e4e9 AM |
2920 | } |
2921 | } | |
293f5f65 L |
2922 | |
2923 | if (*string == '.' && j >= ARRAY_SIZE (cpu_arch)) | |
2924 | { | |
33eaf5de | 2925 | /* Disable an ISA extension. */ |
293f5f65 L |
2926 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
2927 | if (strcmp (string + 1, cpu_noarch [j].name) == 0) | |
2928 | { | |
2929 | flags = cpu_flags_and_not (cpu_arch_flags, | |
2930 | cpu_noarch[j].flags); | |
2931 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
2932 | { | |
2933 | if (cpu_sub_arch_name) | |
2934 | { | |
2935 | char *name = cpu_sub_arch_name; | |
2936 | cpu_sub_arch_name = concat (name, string, | |
2937 | (const char *) NULL); | |
2938 | free (name); | |
2939 | } | |
2940 | else | |
2941 | cpu_sub_arch_name = xstrdup (string); | |
2942 | cpu_arch_flags = flags; | |
2943 | cpu_arch_isa_flags = flags; | |
2944 | } | |
2945 | (void) restore_line_pointer (e); | |
2946 | demand_empty_rest_of_line (); | |
2947 | return; | |
2948 | } | |
2949 | ||
2950 | j = ARRAY_SIZE (cpu_arch); | |
2951 | } | |
2952 | ||
91d6fa6a | 2953 | if (j >= ARRAY_SIZE (cpu_arch)) |
e413e4e9 AM |
2954 | as_bad (_("no such architecture: `%s'"), string); |
2955 | ||
2956 | *input_line_pointer = e; | |
2957 | } | |
2958 | else | |
2959 | as_bad (_("missing cpu architecture")); | |
2960 | ||
fddf5b5b AM |
2961 | no_cond_jump_promotion = 0; |
2962 | if (*input_line_pointer == ',' | |
29b0f896 | 2963 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
fddf5b5b | 2964 | { |
d02603dc NC |
2965 | char *string; |
2966 | char e; | |
2967 | ||
2968 | ++input_line_pointer; | |
2969 | e = get_symbol_name (&string); | |
fddf5b5b AM |
2970 | |
2971 | if (strcmp (string, "nojumps") == 0) | |
2972 | no_cond_jump_promotion = 1; | |
2973 | else if (strcmp (string, "jumps") == 0) | |
2974 | ; | |
2975 | else | |
2976 | as_bad (_("no such architecture modifier: `%s'"), string); | |
2977 | ||
d02603dc | 2978 | (void) restore_line_pointer (e); |
fddf5b5b AM |
2979 | } |
2980 | ||
e413e4e9 AM |
2981 | demand_empty_rest_of_line (); |
2982 | } | |
2983 | ||
8a9036a4 L |
2984 | enum bfd_architecture |
2985 | i386_arch (void) | |
2986 | { | |
3632d14b | 2987 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 L |
2988 | { |
2989 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2990 | || flag_code != CODE_64BIT) | |
2991 | as_fatal (_("Intel L1OM is 64bit ELF only")); | |
2992 | return bfd_arch_l1om; | |
2993 | } | |
7a9068fe L |
2994 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2995 | { | |
2996 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2997 | || flag_code != CODE_64BIT) | |
2998 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2999 | return bfd_arch_k1om; | |
3000 | } | |
81486035 L |
3001 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
3002 | { | |
3003 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
3004 | || flag_code == CODE_64BIT) | |
3005 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
3006 | return bfd_arch_iamcu; | |
3007 | } | |
8a9036a4 L |
3008 | else |
3009 | return bfd_arch_i386; | |
3010 | } | |
3011 | ||
b9d79e03 | 3012 | unsigned long |
7016a5d5 | 3013 | i386_mach (void) |
b9d79e03 | 3014 | { |
d34049e8 | 3015 | if (startswith (default_arch, "x86_64")) |
8a9036a4 | 3016 | { |
3632d14b | 3017 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 3018 | { |
351f65ca L |
3019 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour |
3020 | || default_arch[6] != '\0') | |
8a9036a4 L |
3021 | as_fatal (_("Intel L1OM is 64bit ELF only")); |
3022 | return bfd_mach_l1om; | |
3023 | } | |
7a9068fe L |
3024 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
3025 | { | |
3026 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
3027 | || default_arch[6] != '\0') | |
3028 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
3029 | return bfd_mach_k1om; | |
3030 | } | |
351f65ca | 3031 | else if (default_arch[6] == '\0') |
8a9036a4 | 3032 | return bfd_mach_x86_64; |
351f65ca L |
3033 | else |
3034 | return bfd_mach_x64_32; | |
8a9036a4 | 3035 | } |
5197d474 L |
3036 | else if (!strcmp (default_arch, "i386") |
3037 | || !strcmp (default_arch, "iamcu")) | |
81486035 L |
3038 | { |
3039 | if (cpu_arch_isa == PROCESSOR_IAMCU) | |
3040 | { | |
3041 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
3042 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
3043 | return bfd_mach_i386_iamcu; | |
3044 | } | |
3045 | else | |
3046 | return bfd_mach_i386_i386; | |
3047 | } | |
b9d79e03 | 3048 | else |
2b5d6a91 | 3049 | as_fatal (_("unknown architecture")); |
b9d79e03 | 3050 | } |
b9d79e03 | 3051 | \f |
252b5132 | 3052 | void |
7016a5d5 | 3053 | md_begin (void) |
252b5132 | 3054 | { |
86fa6981 L |
3055 | /* Support pseudo prefixes like {disp32}. */ |
3056 | lex_type ['{'] = LEX_BEGIN_NAME; | |
3057 | ||
47926f60 | 3058 | /* Initialize op_hash hash table. */ |
629310ab | 3059 | op_hash = str_htab_create (); |
252b5132 RH |
3060 | |
3061 | { | |
d3ce72d0 | 3062 | const insn_template *optab; |
29b0f896 | 3063 | templates *core_optab; |
252b5132 | 3064 | |
47926f60 KH |
3065 | /* Setup for loop. */ |
3066 | optab = i386_optab; | |
add39d23 | 3067 | core_optab = XNEW (templates); |
252b5132 RH |
3068 | core_optab->start = optab; |
3069 | ||
3070 | while (1) | |
3071 | { | |
3072 | ++optab; | |
3073 | if (optab->name == NULL | |
3074 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
3075 | { | |
3076 | /* different name --> ship out current template list; | |
47926f60 | 3077 | add to hash table; & begin anew. */ |
252b5132 | 3078 | core_optab->end = optab; |
fe0e921f AM |
3079 | if (str_hash_insert (op_hash, (optab - 1)->name, core_optab, 0)) |
3080 | as_fatal (_("duplicate %s"), (optab - 1)->name); | |
3081 | ||
252b5132 RH |
3082 | if (optab->name == NULL) |
3083 | break; | |
add39d23 | 3084 | core_optab = XNEW (templates); |
252b5132 RH |
3085 | core_optab->start = optab; |
3086 | } | |
3087 | } | |
3088 | } | |
3089 | ||
47926f60 | 3090 | /* Initialize reg_hash hash table. */ |
629310ab | 3091 | reg_hash = str_htab_create (); |
252b5132 | 3092 | { |
29b0f896 | 3093 | const reg_entry *regtab; |
c3fe08fa | 3094 | unsigned int regtab_size = i386_regtab_size; |
252b5132 | 3095 | |
c3fe08fa | 3096 | for (regtab = i386_regtab; regtab_size--; regtab++) |
6225c532 | 3097 | { |
6288d05f JB |
3098 | switch (regtab->reg_type.bitfield.class) |
3099 | { | |
3100 | case Reg: | |
34684862 JB |
3101 | if (regtab->reg_type.bitfield.dword) |
3102 | { | |
3103 | if (regtab->reg_type.bitfield.instance == Accum) | |
3104 | reg_eax = regtab; | |
3105 | } | |
3106 | else if (regtab->reg_type.bitfield.tbyte) | |
6288d05f JB |
3107 | { |
3108 | /* There's no point inserting st(<N>) in the hash table, as | |
3109 | parentheses aren't included in register_chars[] anyway. */ | |
3110 | if (regtab->reg_type.bitfield.instance != Accum) | |
3111 | continue; | |
3112 | reg_st0 = regtab; | |
3113 | } | |
3114 | break; | |
3115 | ||
5e042380 JB |
3116 | case SReg: |
3117 | switch (regtab->reg_num) | |
3118 | { | |
3119 | case 0: reg_es = regtab; break; | |
3120 | case 2: reg_ss = regtab; break; | |
3121 | case 3: reg_ds = regtab; break; | |
3122 | } | |
3123 | break; | |
3124 | ||
6288d05f JB |
3125 | case RegMask: |
3126 | if (!regtab->reg_num) | |
3127 | reg_k0 = regtab; | |
3128 | break; | |
3129 | } | |
3130 | ||
6225c532 JB |
3131 | if (str_hash_insert (reg_hash, regtab->reg_name, regtab, 0) != NULL) |
3132 | as_fatal (_("duplicate %s"), regtab->reg_name); | |
6225c532 | 3133 | } |
252b5132 RH |
3134 | } |
3135 | ||
47926f60 | 3136 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 | 3137 | { |
29b0f896 AM |
3138 | int c; |
3139 | char *p; | |
252b5132 RH |
3140 | |
3141 | for (c = 0; c < 256; c++) | |
3142 | { | |
3882b010 | 3143 | if (ISDIGIT (c)) |
252b5132 RH |
3144 | { |
3145 | digit_chars[c] = c; | |
3146 | mnemonic_chars[c] = c; | |
3147 | register_chars[c] = c; | |
3148 | operand_chars[c] = c; | |
3149 | } | |
3882b010 | 3150 | else if (ISLOWER (c)) |
252b5132 RH |
3151 | { |
3152 | mnemonic_chars[c] = c; | |
3153 | register_chars[c] = c; | |
3154 | operand_chars[c] = c; | |
3155 | } | |
3882b010 | 3156 | else if (ISUPPER (c)) |
252b5132 | 3157 | { |
3882b010 | 3158 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
3159 | register_chars[c] = mnemonic_chars[c]; |
3160 | operand_chars[c] = c; | |
3161 | } | |
43234a1e | 3162 | else if (c == '{' || c == '}') |
86fa6981 L |
3163 | { |
3164 | mnemonic_chars[c] = c; | |
3165 | operand_chars[c] = c; | |
3166 | } | |
b3983e5f JB |
3167 | #ifdef SVR4_COMMENT_CHARS |
3168 | else if (c == '\\' && strchr (i386_comment_chars, '/')) | |
3169 | operand_chars[c] = c; | |
3170 | #endif | |
252b5132 | 3171 | |
3882b010 | 3172 | if (ISALPHA (c) || ISDIGIT (c)) |
252b5132 RH |
3173 | identifier_chars[c] = c; |
3174 | else if (c >= 128) | |
3175 | { | |
3176 | identifier_chars[c] = c; | |
3177 | operand_chars[c] = c; | |
3178 | } | |
3179 | } | |
3180 | ||
3181 | #ifdef LEX_AT | |
3182 | identifier_chars['@'] = '@'; | |
32137342 NC |
3183 | #endif |
3184 | #ifdef LEX_QM | |
3185 | identifier_chars['?'] = '?'; | |
3186 | operand_chars['?'] = '?'; | |
252b5132 | 3187 | #endif |
252b5132 | 3188 | digit_chars['-'] = '-'; |
c0f3af97 | 3189 | mnemonic_chars['_'] = '_'; |
791fe849 | 3190 | mnemonic_chars['-'] = '-'; |
0003779b | 3191 | mnemonic_chars['.'] = '.'; |
252b5132 RH |
3192 | identifier_chars['_'] = '_'; |
3193 | identifier_chars['.'] = '.'; | |
3194 | ||
3195 | for (p = operand_special_chars; *p != '\0'; p++) | |
3196 | operand_chars[(unsigned char) *p] = *p; | |
3197 | } | |
3198 | ||
a4447b93 RH |
3199 | if (flag_code == CODE_64BIT) |
3200 | { | |
ca19b261 KT |
3201 | #if defined (OBJ_COFF) && defined (TE_PE) |
3202 | x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour | |
3203 | ? 32 : 16); | |
3204 | #else | |
a4447b93 | 3205 | x86_dwarf2_return_column = 16; |
ca19b261 | 3206 | #endif |
61ff971f | 3207 | x86_cie_data_alignment = -8; |
a4447b93 RH |
3208 | } |
3209 | else | |
3210 | { | |
3211 | x86_dwarf2_return_column = 8; | |
3212 | x86_cie_data_alignment = -4; | |
3213 | } | |
e379e5f3 L |
3214 | |
3215 | /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it | |
3216 | can be turned into BRANCH_PREFIX frag. */ | |
3217 | if (align_branch_prefix_size > MAX_FUSED_JCC_PADDING_SIZE) | |
3218 | abort (); | |
252b5132 RH |
3219 | } |
3220 | ||
3221 | void | |
e3bb37b5 | 3222 | i386_print_statistics (FILE *file) |
252b5132 | 3223 | { |
629310ab ML |
3224 | htab_print_statistics (file, "i386 opcode", op_hash); |
3225 | htab_print_statistics (file, "i386 register", reg_hash); | |
252b5132 RH |
3226 | } |
3227 | \f | |
252b5132 RH |
3228 | #ifdef DEBUG386 |
3229 | ||
ce8a8b2f | 3230 | /* Debugging routines for md_assemble. */ |
d3ce72d0 | 3231 | static void pte (insn_template *); |
40fb9820 | 3232 | static void pt (i386_operand_type); |
e3bb37b5 L |
3233 | static void pe (expressionS *); |
3234 | static void ps (symbolS *); | |
252b5132 RH |
3235 | |
3236 | static void | |
2c703856 | 3237 | pi (const char *line, i386_insn *x) |
252b5132 | 3238 | { |
09137c09 | 3239 | unsigned int j; |
252b5132 RH |
3240 | |
3241 | fprintf (stdout, "%s: template ", line); | |
3242 | pte (&x->tm); | |
09f131f2 JH |
3243 | fprintf (stdout, " address: base %s index %s scale %x\n", |
3244 | x->base_reg ? x->base_reg->reg_name : "none", | |
3245 | x->index_reg ? x->index_reg->reg_name : "none", | |
3246 | x->log2_scale_factor); | |
3247 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 3248 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
3249 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
3250 | x->sib.base, x->sib.index, x->sib.scale); | |
3251 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
161a04f6 L |
3252 | (x->rex & REX_W) != 0, |
3253 | (x->rex & REX_R) != 0, | |
3254 | (x->rex & REX_X) != 0, | |
3255 | (x->rex & REX_B) != 0); | |
09137c09 | 3256 | for (j = 0; j < x->operands; j++) |
252b5132 | 3257 | { |
09137c09 SP |
3258 | fprintf (stdout, " #%d: ", j + 1); |
3259 | pt (x->types[j]); | |
252b5132 | 3260 | fprintf (stdout, "\n"); |
bab6aec1 | 3261 | if (x->types[j].bitfield.class == Reg |
3528c362 JB |
3262 | || x->types[j].bitfield.class == RegMMX |
3263 | || x->types[j].bitfield.class == RegSIMD | |
dd6b8a0b | 3264 | || x->types[j].bitfield.class == RegMask |
00cee14f | 3265 | || x->types[j].bitfield.class == SReg |
4a5c67ed JB |
3266 | || x->types[j].bitfield.class == RegCR |
3267 | || x->types[j].bitfield.class == RegDR | |
dd6b8a0b JB |
3268 | || x->types[j].bitfield.class == RegTR |
3269 | || x->types[j].bitfield.class == RegBND) | |
09137c09 SP |
3270 | fprintf (stdout, "%s\n", x->op[j].regs->reg_name); |
3271 | if (operand_type_check (x->types[j], imm)) | |
3272 | pe (x->op[j].imms); | |
3273 | if (operand_type_check (x->types[j], disp)) | |
3274 | pe (x->op[j].disps); | |
252b5132 RH |
3275 | } |
3276 | } | |
3277 | ||
3278 | static void | |
d3ce72d0 | 3279 | pte (insn_template *t) |
252b5132 | 3280 | { |
b933fa4b | 3281 | static const unsigned char opc_pfx[] = { 0, 0x66, 0xf3, 0xf2 }; |
441f6aca JB |
3282 | static const char *const opc_spc[] = { |
3283 | NULL, "0f", "0f38", "0f3a", NULL, NULL, NULL, NULL, | |
3284 | "XOP08", "XOP09", "XOP0A", | |
3285 | }; | |
09137c09 | 3286 | unsigned int j; |
441f6aca | 3287 | |
252b5132 | 3288 | fprintf (stdout, " %d operands ", t->operands); |
441f6aca JB |
3289 | if (opc_pfx[t->opcode_modifier.opcodeprefix]) |
3290 | fprintf (stdout, "pfx %x ", opc_pfx[t->opcode_modifier.opcodeprefix]); | |
3291 | if (opc_spc[t->opcode_modifier.opcodespace]) | |
3292 | fprintf (stdout, "space %s ", opc_spc[t->opcode_modifier.opcodespace]); | |
47926f60 | 3293 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
3294 | if (t->extension_opcode != None) |
3295 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
40fb9820 | 3296 | if (t->opcode_modifier.d) |
252b5132 | 3297 | fprintf (stdout, "D"); |
40fb9820 | 3298 | if (t->opcode_modifier.w) |
252b5132 RH |
3299 | fprintf (stdout, "W"); |
3300 | fprintf (stdout, "\n"); | |
09137c09 | 3301 | for (j = 0; j < t->operands; j++) |
252b5132 | 3302 | { |
09137c09 SP |
3303 | fprintf (stdout, " #%d type ", j + 1); |
3304 | pt (t->operand_types[j]); | |
252b5132 RH |
3305 | fprintf (stdout, "\n"); |
3306 | } | |
3307 | } | |
3308 | ||
3309 | static void | |
e3bb37b5 | 3310 | pe (expressionS *e) |
252b5132 | 3311 | { |
24eab124 | 3312 | fprintf (stdout, " operation %d\n", e->X_op); |
7b025ee8 JB |
3313 | fprintf (stdout, " add_number %" BFD_VMA_FMT "d (%" BFD_VMA_FMT "x)\n", |
3314 | e->X_add_number, e->X_add_number); | |
252b5132 RH |
3315 | if (e->X_add_symbol) |
3316 | { | |
3317 | fprintf (stdout, " add_symbol "); | |
3318 | ps (e->X_add_symbol); | |
3319 | fprintf (stdout, "\n"); | |
3320 | } | |
3321 | if (e->X_op_symbol) | |
3322 | { | |
3323 | fprintf (stdout, " op_symbol "); | |
3324 | ps (e->X_op_symbol); | |
3325 | fprintf (stdout, "\n"); | |
3326 | } | |
3327 | } | |
3328 | ||
3329 | static void | |
e3bb37b5 | 3330 | ps (symbolS *s) |
252b5132 RH |
3331 | { |
3332 | fprintf (stdout, "%s type %s%s", | |
3333 | S_GET_NAME (s), | |
3334 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
3335 | segment_name (S_GET_SEGMENT (s))); | |
3336 | } | |
3337 | ||
7b81dfbb | 3338 | static struct type_name |
252b5132 | 3339 | { |
40fb9820 L |
3340 | i386_operand_type mask; |
3341 | const char *name; | |
252b5132 | 3342 | } |
7b81dfbb | 3343 | const type_names[] = |
252b5132 | 3344 | { |
40fb9820 L |
3345 | { OPERAND_TYPE_REG8, "r8" }, |
3346 | { OPERAND_TYPE_REG16, "r16" }, | |
3347 | { OPERAND_TYPE_REG32, "r32" }, | |
3348 | { OPERAND_TYPE_REG64, "r64" }, | |
2c703856 JB |
3349 | { OPERAND_TYPE_ACC8, "acc8" }, |
3350 | { OPERAND_TYPE_ACC16, "acc16" }, | |
3351 | { OPERAND_TYPE_ACC32, "acc32" }, | |
3352 | { OPERAND_TYPE_ACC64, "acc64" }, | |
40fb9820 L |
3353 | { OPERAND_TYPE_IMM8, "i8" }, |
3354 | { OPERAND_TYPE_IMM8, "i8s" }, | |
3355 | { OPERAND_TYPE_IMM16, "i16" }, | |
3356 | { OPERAND_TYPE_IMM32, "i32" }, | |
3357 | { OPERAND_TYPE_IMM32S, "i32s" }, | |
3358 | { OPERAND_TYPE_IMM64, "i64" }, | |
3359 | { OPERAND_TYPE_IMM1, "i1" }, | |
3360 | { OPERAND_TYPE_BASEINDEX, "BaseIndex" }, | |
3361 | { OPERAND_TYPE_DISP8, "d8" }, | |
3362 | { OPERAND_TYPE_DISP16, "d16" }, | |
3363 | { OPERAND_TYPE_DISP32, "d32" }, | |
3364 | { OPERAND_TYPE_DISP32S, "d32s" }, | |
3365 | { OPERAND_TYPE_DISP64, "d64" }, | |
3366 | { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" }, | |
3367 | { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" }, | |
3368 | { OPERAND_TYPE_CONTROL, "control reg" }, | |
3369 | { OPERAND_TYPE_TEST, "test reg" }, | |
3370 | { OPERAND_TYPE_DEBUG, "debug reg" }, | |
3371 | { OPERAND_TYPE_FLOATREG, "FReg" }, | |
3372 | { OPERAND_TYPE_FLOATACC, "FAcc" }, | |
21df382b | 3373 | { OPERAND_TYPE_SREG, "SReg" }, |
40fb9820 L |
3374 | { OPERAND_TYPE_REGMMX, "rMMX" }, |
3375 | { OPERAND_TYPE_REGXMM, "rXMM" }, | |
0349dc08 | 3376 | { OPERAND_TYPE_REGYMM, "rYMM" }, |
43234a1e | 3377 | { OPERAND_TYPE_REGZMM, "rZMM" }, |
260cd341 | 3378 | { OPERAND_TYPE_REGTMM, "rTMM" }, |
43234a1e | 3379 | { OPERAND_TYPE_REGMASK, "Mask reg" }, |
252b5132 RH |
3380 | }; |
3381 | ||
3382 | static void | |
40fb9820 | 3383 | pt (i386_operand_type t) |
252b5132 | 3384 | { |
40fb9820 | 3385 | unsigned int j; |
c6fb90c8 | 3386 | i386_operand_type a; |
252b5132 | 3387 | |
40fb9820 | 3388 | for (j = 0; j < ARRAY_SIZE (type_names); j++) |
c6fb90c8 L |
3389 | { |
3390 | a = operand_type_and (t, type_names[j].mask); | |
2c703856 | 3391 | if (operand_type_equal (&a, &type_names[j].mask)) |
c6fb90c8 L |
3392 | fprintf (stdout, "%s, ", type_names[j].name); |
3393 | } | |
252b5132 RH |
3394 | fflush (stdout); |
3395 | } | |
3396 | ||
3397 | #endif /* DEBUG386 */ | |
3398 | \f | |
252b5132 | 3399 | static bfd_reloc_code_real_type |
3956db08 | 3400 | reloc (unsigned int size, |
64e74474 AM |
3401 | int pcrel, |
3402 | int sign, | |
3403 | bfd_reloc_code_real_type other) | |
252b5132 | 3404 | { |
47926f60 | 3405 | if (other != NO_RELOC) |
3956db08 | 3406 | { |
91d6fa6a | 3407 | reloc_howto_type *rel; |
3956db08 JB |
3408 | |
3409 | if (size == 8) | |
3410 | switch (other) | |
3411 | { | |
64e74474 AM |
3412 | case BFD_RELOC_X86_64_GOT32: |
3413 | return BFD_RELOC_X86_64_GOT64; | |
3414 | break; | |
553d1284 L |
3415 | case BFD_RELOC_X86_64_GOTPLT64: |
3416 | return BFD_RELOC_X86_64_GOTPLT64; | |
3417 | break; | |
64e74474 AM |
3418 | case BFD_RELOC_X86_64_PLTOFF64: |
3419 | return BFD_RELOC_X86_64_PLTOFF64; | |
3420 | break; | |
3421 | case BFD_RELOC_X86_64_GOTPC32: | |
3422 | other = BFD_RELOC_X86_64_GOTPC64; | |
3423 | break; | |
3424 | case BFD_RELOC_X86_64_GOTPCREL: | |
3425 | other = BFD_RELOC_X86_64_GOTPCREL64; | |
3426 | break; | |
3427 | case BFD_RELOC_X86_64_TPOFF32: | |
3428 | other = BFD_RELOC_X86_64_TPOFF64; | |
3429 | break; | |
3430 | case BFD_RELOC_X86_64_DTPOFF32: | |
3431 | other = BFD_RELOC_X86_64_DTPOFF64; | |
3432 | break; | |
3433 | default: | |
3434 | break; | |
3956db08 | 3435 | } |
e05278af | 3436 | |
8ce3d284 | 3437 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
3438 | if (other == BFD_RELOC_SIZE32) |
3439 | { | |
3440 | if (size == 8) | |
1ab668bf | 3441 | other = BFD_RELOC_SIZE64; |
8fd4256d | 3442 | if (pcrel) |
1ab668bf AM |
3443 | { |
3444 | as_bad (_("there are no pc-relative size relocations")); | |
3445 | return NO_RELOC; | |
3446 | } | |
8fd4256d | 3447 | } |
8ce3d284 | 3448 | #endif |
8fd4256d | 3449 | |
e05278af | 3450 | /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ |
f2d8a97c | 3451 | if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc)) |
e05278af JB |
3452 | sign = -1; |
3453 | ||
91d6fa6a NC |
3454 | rel = bfd_reloc_type_lookup (stdoutput, other); |
3455 | if (!rel) | |
3956db08 | 3456 | as_bad (_("unknown relocation (%u)"), other); |
91d6fa6a | 3457 | else if (size != bfd_get_reloc_size (rel)) |
3956db08 | 3458 | as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), |
91d6fa6a | 3459 | bfd_get_reloc_size (rel), |
3956db08 | 3460 | size); |
91d6fa6a | 3461 | else if (pcrel && !rel->pc_relative) |
3956db08 | 3462 | as_bad (_("non-pc-relative relocation for pc-relative field")); |
91d6fa6a | 3463 | else if ((rel->complain_on_overflow == complain_overflow_signed |
3956db08 | 3464 | && !sign) |
91d6fa6a | 3465 | || (rel->complain_on_overflow == complain_overflow_unsigned |
64e74474 | 3466 | && sign > 0)) |
3956db08 JB |
3467 | as_bad (_("relocated field and relocation type differ in signedness")); |
3468 | else | |
3469 | return other; | |
3470 | return NO_RELOC; | |
3471 | } | |
252b5132 RH |
3472 | |
3473 | if (pcrel) | |
3474 | { | |
3e73aa7c | 3475 | if (!sign) |
3956db08 | 3476 | as_bad (_("there are no unsigned pc-relative relocations")); |
252b5132 RH |
3477 | switch (size) |
3478 | { | |
3479 | case 1: return BFD_RELOC_8_PCREL; | |
3480 | case 2: return BFD_RELOC_16_PCREL; | |
d258b828 | 3481 | case 4: return BFD_RELOC_32_PCREL; |
d6ab8113 | 3482 | case 8: return BFD_RELOC_64_PCREL; |
252b5132 | 3483 | } |
3956db08 | 3484 | as_bad (_("cannot do %u byte pc-relative relocation"), size); |
252b5132 RH |
3485 | } |
3486 | else | |
3487 | { | |
3956db08 | 3488 | if (sign > 0) |
e5cb08ac | 3489 | switch (size) |
3e73aa7c JH |
3490 | { |
3491 | case 4: return BFD_RELOC_X86_64_32S; | |
3492 | } | |
3493 | else | |
3494 | switch (size) | |
3495 | { | |
3496 | case 1: return BFD_RELOC_8; | |
3497 | case 2: return BFD_RELOC_16; | |
3498 | case 4: return BFD_RELOC_32; | |
3499 | case 8: return BFD_RELOC_64; | |
3500 | } | |
3956db08 JB |
3501 | as_bad (_("cannot do %s %u byte relocation"), |
3502 | sign > 0 ? "signed" : "unsigned", size); | |
252b5132 RH |
3503 | } |
3504 | ||
0cc9e1d3 | 3505 | return NO_RELOC; |
252b5132 RH |
3506 | } |
3507 | ||
47926f60 KH |
3508 | /* Here we decide which fixups can be adjusted to make them relative to |
3509 | the beginning of the section instead of the symbol. Basically we need | |
3510 | to make sure that the dynamic relocations are done correctly, so in | |
3511 | some cases we force the original symbol to be used. */ | |
3512 | ||
252b5132 | 3513 | int |
e3bb37b5 | 3514 | tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) |
252b5132 | 3515 | { |
6d249963 | 3516 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 3517 | if (!IS_ELF) |
31312f95 AM |
3518 | return 1; |
3519 | ||
a161fe53 AM |
3520 | /* Don't adjust pc-relative references to merge sections in 64-bit |
3521 | mode. */ | |
3522 | if (use_rela_relocations | |
3523 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 | |
3524 | && fixP->fx_pcrel) | |
252b5132 | 3525 | return 0; |
31312f95 | 3526 | |
8d01d9a9 AJ |
3527 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
3528 | and changed later by validate_fix. */ | |
3529 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol | |
3530 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) | |
3531 | return 0; | |
3532 | ||
8fd4256d L |
3533 | /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol |
3534 | for size relocations. */ | |
3535 | if (fixP->fx_r_type == BFD_RELOC_SIZE32 | |
3536 | || fixP->fx_r_type == BFD_RELOC_SIZE64 | |
3537 | || fixP->fx_r_type == BFD_RELOC_386_GOTOFF | |
252b5132 | 3538 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 |
02a86693 | 3539 | || fixP->fx_r_type == BFD_RELOC_386_GOT32X |
13ae64f3 JJ |
3540 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
3541 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM | |
3542 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 | |
3543 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 | |
37e55690 JJ |
3544 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
3545 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE | |
13ae64f3 JJ |
3546 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
3547 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE | |
67a4f2b7 AO |
3548 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC |
3549 | || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL | |
3e73aa7c | 3550 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 |
80b3ee89 | 3551 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
56ceb5b5 L |
3552 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX |
3553 | || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX | |
bffbf940 JJ |
3554 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
3555 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD | |
3556 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 | |
d6ab8113 | 3557 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 |
bffbf940 JJ |
3558 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF |
3559 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 | |
d6ab8113 JB |
3560 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 |
3561 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 | |
67a4f2b7 AO |
3562 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
3563 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL | |
252b5132 RH |
3564 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
3565 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
3566 | return 0; | |
31312f95 | 3567 | #endif |
252b5132 RH |
3568 | return 1; |
3569 | } | |
252b5132 | 3570 | |
a9aabc23 JB |
3571 | static INLINE bool |
3572 | want_disp32 (const insn_template *t) | |
3573 | { | |
3574 | return flag_code != CODE_64BIT | |
3575 | || i.prefix[ADDR_PREFIX] | |
3576 | || (t->base_opcode == 0x8d | |
3577 | && t->opcode_modifier.opcodespace == SPACE_BASE | |
fe134c65 JB |
3578 | && (!i.types[1].bitfield.qword |
3579 | || t->opcode_modifier.size == SIZE32)); | |
a9aabc23 JB |
3580 | } |
3581 | ||
b4cac588 | 3582 | static int |
e3bb37b5 | 3583 | intel_float_operand (const char *mnemonic) |
252b5132 | 3584 | { |
9306ca4a JB |
3585 | /* Note that the value returned is meaningful only for opcodes with (memory) |
3586 | operands, hence the code here is free to improperly handle opcodes that | |
3587 | have no operands (for better performance and smaller code). */ | |
3588 | ||
3589 | if (mnemonic[0] != 'f') | |
3590 | return 0; /* non-math */ | |
3591 | ||
3592 | switch (mnemonic[1]) | |
3593 | { | |
3594 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and | |
3595 | the fs segment override prefix not currently handled because no | |
3596 | call path can make opcodes without operands get here */ | |
3597 | case 'i': | |
3598 | return 2 /* integer op */; | |
3599 | case 'l': | |
3600 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) | |
3601 | return 3; /* fldcw/fldenv */ | |
3602 | break; | |
3603 | case 'n': | |
3604 | if (mnemonic[2] != 'o' /* fnop */) | |
3605 | return 3; /* non-waiting control op */ | |
3606 | break; | |
3607 | case 'r': | |
3608 | if (mnemonic[2] == 's') | |
3609 | return 3; /* frstor/frstpm */ | |
3610 | break; | |
3611 | case 's': | |
3612 | if (mnemonic[2] == 'a') | |
3613 | return 3; /* fsave */ | |
3614 | if (mnemonic[2] == 't') | |
3615 | { | |
3616 | switch (mnemonic[3]) | |
3617 | { | |
3618 | case 'c': /* fstcw */ | |
3619 | case 'd': /* fstdw */ | |
3620 | case 'e': /* fstenv */ | |
3621 | case 's': /* fsts[gw] */ | |
3622 | return 3; | |
3623 | } | |
3624 | } | |
3625 | break; | |
3626 | case 'x': | |
3627 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') | |
3628 | return 0; /* fxsave/fxrstor are not really math ops */ | |
3629 | break; | |
3630 | } | |
252b5132 | 3631 | |
9306ca4a | 3632 | return 1; |
252b5132 RH |
3633 | } |
3634 | ||
9a182d04 JB |
3635 | static INLINE void |
3636 | install_template (const insn_template *t) | |
3637 | { | |
3638 | unsigned int l; | |
3639 | ||
3640 | i.tm = *t; | |
3641 | ||
3642 | /* Note that for pseudo prefixes this produces a length of 1. But for them | |
3643 | the length isn't interesting at all. */ | |
3644 | for (l = 1; l < 4; ++l) | |
3645 | if (!(t->base_opcode >> (8 * l))) | |
3646 | break; | |
3647 | ||
3648 | i.opcode_length = l; | |
3649 | } | |
3650 | ||
c0f3af97 L |
3651 | /* Build the VEX prefix. */ |
3652 | ||
3653 | static void | |
d3ce72d0 | 3654 | build_vex_prefix (const insn_template *t) |
c0f3af97 L |
3655 | { |
3656 | unsigned int register_specifier; | |
c0f3af97 | 3657 | unsigned int vector_length; |
03751133 | 3658 | unsigned int w; |
c0f3af97 L |
3659 | |
3660 | /* Check register specifier. */ | |
3661 | if (i.vex.register_specifier) | |
43234a1e L |
3662 | { |
3663 | register_specifier = | |
3664 | ~register_number (i.vex.register_specifier) & 0xf; | |
3665 | gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0); | |
3666 | } | |
c0f3af97 L |
3667 | else |
3668 | register_specifier = 0xf; | |
3669 | ||
79f0fa25 L |
3670 | /* Use 2-byte VEX prefix by swapping destination and source operand |
3671 | if there are more than 1 register operand. */ | |
3672 | if (i.reg_operands > 1 | |
3673 | && i.vec_encoding != vex_encoding_vex3 | |
86fa6981 | 3674 | && i.dir_encoding == dir_encoding_default |
fa99fab2 | 3675 | && i.operands == i.reg_operands |
dbbc8b7e | 3676 | && operand_type_equal (&i.types[0], &i.types[i.operands - 1]) |
441f6aca | 3677 | && i.tm.opcode_modifier.opcodespace == SPACE_0F |
dbbc8b7e | 3678 | && (i.tm.opcode_modifier.load || i.tm.opcode_modifier.d) |
fa99fab2 L |
3679 | && i.rex == REX_B) |
3680 | { | |
3681 | unsigned int xchg = i.operands - 1; | |
3682 | union i386_op temp_op; | |
3683 | i386_operand_type temp_type; | |
3684 | ||
3685 | temp_type = i.types[xchg]; | |
3686 | i.types[xchg] = i.types[0]; | |
3687 | i.types[0] = temp_type; | |
3688 | temp_op = i.op[xchg]; | |
3689 | i.op[xchg] = i.op[0]; | |
3690 | i.op[0] = temp_op; | |
3691 | ||
9c2799c2 | 3692 | gas_assert (i.rm.mode == 3); |
fa99fab2 L |
3693 | |
3694 | i.rex = REX_R; | |
3695 | xchg = i.rm.regmem; | |
3696 | i.rm.regmem = i.rm.reg; | |
3697 | i.rm.reg = xchg; | |
3698 | ||
dbbc8b7e JB |
3699 | if (i.tm.opcode_modifier.d) |
3700 | i.tm.base_opcode ^= (i.tm.base_opcode & 0xee) != 0x6e | |
3701 | ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD; | |
3702 | else /* Use the next insn. */ | |
9a182d04 | 3703 | install_template (&t[1]); |
fa99fab2 L |
3704 | } |
3705 | ||
79dec6b7 JB |
3706 | /* Use 2-byte VEX prefix by swapping commutative source operands if there |
3707 | are no memory operands and at least 3 register ones. */ | |
3708 | if (i.reg_operands >= 3 | |
3709 | && i.vec_encoding != vex_encoding_vex3 | |
3710 | && i.reg_operands == i.operands - i.imm_operands | |
3711 | && i.tm.opcode_modifier.vex | |
3712 | && i.tm.opcode_modifier.commutative | |
3713 | && (i.tm.opcode_modifier.sse2avx || optimize > 1) | |
3714 | && i.rex == REX_B | |
3715 | && i.vex.register_specifier | |
3716 | && !(i.vex.register_specifier->reg_flags & RegRex)) | |
3717 | { | |
3718 | unsigned int xchg = i.operands - i.reg_operands; | |
3719 | union i386_op temp_op; | |
3720 | i386_operand_type temp_type; | |
3721 | ||
441f6aca | 3722 | gas_assert (i.tm.opcode_modifier.opcodespace == SPACE_0F); |
79dec6b7 JB |
3723 | gas_assert (!i.tm.opcode_modifier.sae); |
3724 | gas_assert (operand_type_equal (&i.types[i.operands - 2], | |
3725 | &i.types[i.operands - 3])); | |
3726 | gas_assert (i.rm.mode == 3); | |
3727 | ||
3728 | temp_type = i.types[xchg]; | |
3729 | i.types[xchg] = i.types[xchg + 1]; | |
3730 | i.types[xchg + 1] = temp_type; | |
3731 | temp_op = i.op[xchg]; | |
3732 | i.op[xchg] = i.op[xchg + 1]; | |
3733 | i.op[xchg + 1] = temp_op; | |
3734 | ||
3735 | i.rex = 0; | |
3736 | xchg = i.rm.regmem | 8; | |
3737 | i.rm.regmem = ~register_specifier & 0xf; | |
3738 | gas_assert (!(i.rm.regmem & 8)); | |
3739 | i.vex.register_specifier += xchg - i.rm.regmem; | |
3740 | register_specifier = ~xchg & 0xf; | |
3741 | } | |
3742 | ||
539f890d L |
3743 | if (i.tm.opcode_modifier.vex == VEXScalar) |
3744 | vector_length = avxscalar; | |
10c17abd JB |
3745 | else if (i.tm.opcode_modifier.vex == VEX256) |
3746 | vector_length = 1; | |
539f890d | 3747 | else |
10c17abd | 3748 | { |
56522fc5 | 3749 | unsigned int op; |
10c17abd | 3750 | |
c7213af9 L |
3751 | /* Determine vector length from the last multi-length vector |
3752 | operand. */ | |
10c17abd | 3753 | vector_length = 0; |
56522fc5 | 3754 | for (op = t->operands; op--;) |
10c17abd JB |
3755 | if (t->operand_types[op].bitfield.xmmword |
3756 | && t->operand_types[op].bitfield.ymmword | |
3757 | && i.types[op].bitfield.ymmword) | |
3758 | { | |
3759 | vector_length = 1; | |
3760 | break; | |
3761 | } | |
3762 | } | |
c0f3af97 | 3763 | |
03751133 L |
3764 | /* Check the REX.W bit and VEXW. */ |
3765 | if (i.tm.opcode_modifier.vexw == VEXWIG) | |
3766 | w = (vexwig == vexw1 || (i.rex & REX_W)) ? 1 : 0; | |
3767 | else if (i.tm.opcode_modifier.vexw) | |
3768 | w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0; | |
3769 | else | |
931d03b7 | 3770 | w = (flag_code == CODE_64BIT ? i.rex & REX_W : vexwig == vexw1) ? 1 : 0; |
03751133 | 3771 | |
c0f3af97 | 3772 | /* Use 2-byte VEX prefix if possible. */ |
03751133 L |
3773 | if (w == 0 |
3774 | && i.vec_encoding != vex_encoding_vex3 | |
441f6aca | 3775 | && i.tm.opcode_modifier.opcodespace == SPACE_0F |
c0f3af97 L |
3776 | && (i.rex & (REX_W | REX_X | REX_B)) == 0) |
3777 | { | |
3778 | /* 2-byte VEX prefix. */ | |
3779 | unsigned int r; | |
3780 | ||
3781 | i.vex.length = 2; | |
3782 | i.vex.bytes[0] = 0xc5; | |
3783 | ||
3784 | /* Check the REX.R bit. */ | |
3785 | r = (i.rex & REX_R) ? 0 : 1; | |
3786 | i.vex.bytes[1] = (r << 7 | |
3787 | | register_specifier << 3 | |
3788 | | vector_length << 2 | |
35648716 | 3789 | | i.tm.opcode_modifier.opcodeprefix); |
c0f3af97 L |
3790 | } |
3791 | else | |
3792 | { | |
3793 | /* 3-byte VEX prefix. */ | |
f88c9eb0 | 3794 | i.vex.length = 3; |
f88c9eb0 | 3795 | |
441f6aca | 3796 | switch (i.tm.opcode_modifier.opcodespace) |
5dd85c99 | 3797 | { |
441f6aca JB |
3798 | case SPACE_0F: |
3799 | case SPACE_0F38: | |
3800 | case SPACE_0F3A: | |
80de6e00 | 3801 | i.vex.bytes[0] = 0xc4; |
7f399153 | 3802 | break; |
441f6aca JB |
3803 | case SPACE_XOP08: |
3804 | case SPACE_XOP09: | |
3805 | case SPACE_XOP0A: | |
f88c9eb0 | 3806 | i.vex.bytes[0] = 0x8f; |
7f399153 L |
3807 | break; |
3808 | default: | |
3809 | abort (); | |
f88c9eb0 | 3810 | } |
c0f3af97 | 3811 | |
c0f3af97 L |
3812 | /* The high 3 bits of the second VEX byte are 1's compliment |
3813 | of RXB bits from REX. */ | |
441f6aca | 3814 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | i.tm.opcode_modifier.opcodespace; |
c0f3af97 | 3815 | |
c0f3af97 L |
3816 | i.vex.bytes[2] = (w << 7 |
3817 | | register_specifier << 3 | |
3818 | | vector_length << 2 | |
35648716 | 3819 | | i.tm.opcode_modifier.opcodeprefix); |
c0f3af97 L |
3820 | } |
3821 | } | |
3822 | ||
5b7c81bd | 3823 | static INLINE bool |
e771e7c9 JB |
3824 | is_evex_encoding (const insn_template *t) |
3825 | { | |
7091c612 | 3826 | return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift |
e771e7c9 | 3827 | || t->opcode_modifier.broadcast || t->opcode_modifier.masking |
a80195f1 | 3828 | || t->opcode_modifier.sae; |
e771e7c9 JB |
3829 | } |
3830 | ||
5b7c81bd | 3831 | static INLINE bool |
7a8655d2 JB |
3832 | is_any_vex_encoding (const insn_template *t) |
3833 | { | |
7b47a312 | 3834 | return t->opcode_modifier.vex || is_evex_encoding (t); |
7a8655d2 JB |
3835 | } |
3836 | ||
43234a1e L |
3837 | /* Build the EVEX prefix. */ |
3838 | ||
3839 | static void | |
3840 | build_evex_prefix (void) | |
3841 | { | |
35648716 | 3842 | unsigned int register_specifier, w; |
43234a1e L |
3843 | rex_byte vrex_used = 0; |
3844 | ||
3845 | /* Check register specifier. */ | |
3846 | if (i.vex.register_specifier) | |
3847 | { | |
3848 | gas_assert ((i.vrex & REX_X) == 0); | |
3849 | ||
3850 | register_specifier = i.vex.register_specifier->reg_num; | |
3851 | if ((i.vex.register_specifier->reg_flags & RegRex)) | |
3852 | register_specifier += 8; | |
3853 | /* The upper 16 registers are encoded in the fourth byte of the | |
3854 | EVEX prefix. */ | |
3855 | if (!(i.vex.register_specifier->reg_flags & RegVRex)) | |
3856 | i.vex.bytes[3] = 0x8; | |
3857 | register_specifier = ~register_specifier & 0xf; | |
3858 | } | |
3859 | else | |
3860 | { | |
3861 | register_specifier = 0xf; | |
3862 | ||
3863 | /* Encode upper 16 vector index register in the fourth byte of | |
3864 | the EVEX prefix. */ | |
3865 | if (!(i.vrex & REX_X)) | |
3866 | i.vex.bytes[3] = 0x8; | |
3867 | else | |
3868 | vrex_used |= REX_X; | |
3869 | } | |
3870 | ||
43234a1e L |
3871 | /* 4 byte EVEX prefix. */ |
3872 | i.vex.length = 4; | |
3873 | i.vex.bytes[0] = 0x62; | |
3874 | ||
43234a1e L |
3875 | /* The high 3 bits of the second EVEX byte are 1's compliment of RXB |
3876 | bits from REX. */ | |
441f6aca JB |
3877 | gas_assert (i.tm.opcode_modifier.opcodespace >= SPACE_0F); |
3878 | gas_assert (i.tm.opcode_modifier.opcodespace <= SPACE_0F3A); | |
3879 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | i.tm.opcode_modifier.opcodespace; | |
43234a1e L |
3880 | |
3881 | /* The fifth bit of the second EVEX byte is 1's compliment of the | |
3882 | REX_R bit in VREX. */ | |
3883 | if (!(i.vrex & REX_R)) | |
3884 | i.vex.bytes[1] |= 0x10; | |
3885 | else | |
3886 | vrex_used |= REX_R; | |
3887 | ||
3888 | if ((i.reg_operands + i.imm_operands) == i.operands) | |
3889 | { | |
3890 | /* When all operands are registers, the REX_X bit in REX is not | |
3891 | used. We reuse it to encode the upper 16 registers, which is | |
3892 | indicated by the REX_B bit in VREX. The REX_X bit is encoded | |
3893 | as 1's compliment. */ | |
3894 | if ((i.vrex & REX_B)) | |
3895 | { | |
3896 | vrex_used |= REX_B; | |
3897 | i.vex.bytes[1] &= ~0x40; | |
3898 | } | |
3899 | } | |
3900 | ||
3901 | /* EVEX instructions shouldn't need the REX prefix. */ | |
3902 | i.vrex &= ~vrex_used; | |
3903 | gas_assert (i.vrex == 0); | |
3904 | ||
6865c043 L |
3905 | /* Check the REX.W bit and VEXW. */ |
3906 | if (i.tm.opcode_modifier.vexw == VEXWIG) | |
3907 | w = (evexwig == evexw1 || (i.rex & REX_W)) ? 1 : 0; | |
3908 | else if (i.tm.opcode_modifier.vexw) | |
3909 | w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0; | |
3910 | else | |
931d03b7 | 3911 | w = (flag_code == CODE_64BIT ? i.rex & REX_W : evexwig == evexw1) ? 1 : 0; |
43234a1e | 3912 | |
43234a1e | 3913 | /* The third byte of the EVEX prefix. */ |
35648716 JB |
3914 | i.vex.bytes[2] = ((w << 7) |
3915 | | (register_specifier << 3) | |
3916 | | 4 /* Encode the U bit. */ | |
3917 | | i.tm.opcode_modifier.opcodeprefix); | |
43234a1e L |
3918 | |
3919 | /* The fourth byte of the EVEX prefix. */ | |
3920 | /* The zeroing-masking bit. */ | |
6225c532 | 3921 | if (i.mask.reg && i.mask.zeroing) |
43234a1e L |
3922 | i.vex.bytes[3] |= 0x80; |
3923 | ||
3924 | /* Don't always set the broadcast bit if there is no RC. */ | |
ca5312a2 | 3925 | if (i.rounding.type == rc_none) |
43234a1e L |
3926 | { |
3927 | /* Encode the vector length. */ | |
3928 | unsigned int vec_length; | |
3929 | ||
e771e7c9 JB |
3930 | if (!i.tm.opcode_modifier.evex |
3931 | || i.tm.opcode_modifier.evex == EVEXDYN) | |
3932 | { | |
56522fc5 | 3933 | unsigned int op; |
e771e7c9 | 3934 | |
c7213af9 L |
3935 | /* Determine vector length from the last multi-length vector |
3936 | operand. */ | |
56522fc5 | 3937 | for (op = i.operands; op--;) |
e771e7c9 JB |
3938 | if (i.tm.operand_types[op].bitfield.xmmword |
3939 | + i.tm.operand_types[op].bitfield.ymmword | |
3940 | + i.tm.operand_types[op].bitfield.zmmword > 1) | |
3941 | { | |
3942 | if (i.types[op].bitfield.zmmword) | |
c7213af9 L |
3943 | { |
3944 | i.tm.opcode_modifier.evex = EVEX512; | |
3945 | break; | |
3946 | } | |
e771e7c9 | 3947 | else if (i.types[op].bitfield.ymmword) |
c7213af9 L |
3948 | { |
3949 | i.tm.opcode_modifier.evex = EVEX256; | |
3950 | break; | |
3951 | } | |
e771e7c9 | 3952 | else if (i.types[op].bitfield.xmmword) |
c7213af9 L |
3953 | { |
3954 | i.tm.opcode_modifier.evex = EVEX128; | |
3955 | break; | |
3956 | } | |
5273a3cd | 3957 | else if (i.broadcast.type && op == i.broadcast.operand) |
625cbd7a | 3958 | { |
5273a3cd | 3959 | switch (i.broadcast.bytes) |
625cbd7a JB |
3960 | { |
3961 | case 64: | |
3962 | i.tm.opcode_modifier.evex = EVEX512; | |
3963 | break; | |
3964 | case 32: | |
3965 | i.tm.opcode_modifier.evex = EVEX256; | |
3966 | break; | |
3967 | case 16: | |
3968 | i.tm.opcode_modifier.evex = EVEX128; | |
3969 | break; | |
3970 | default: | |
c7213af9 | 3971 | abort (); |
625cbd7a | 3972 | } |
c7213af9 | 3973 | break; |
625cbd7a | 3974 | } |
e771e7c9 | 3975 | } |
c7213af9 | 3976 | |
56522fc5 | 3977 | if (op >= MAX_OPERANDS) |
c7213af9 | 3978 | abort (); |
e771e7c9 JB |
3979 | } |
3980 | ||
43234a1e L |
3981 | switch (i.tm.opcode_modifier.evex) |
3982 | { | |
3983 | case EVEXLIG: /* LL' is ignored */ | |
3984 | vec_length = evexlig << 5; | |
3985 | break; | |
3986 | case EVEX128: | |
3987 | vec_length = 0 << 5; | |
3988 | break; | |
3989 | case EVEX256: | |
3990 | vec_length = 1 << 5; | |
3991 | break; | |
3992 | case EVEX512: | |
3993 | vec_length = 2 << 5; | |
3994 | break; | |
3995 | default: | |
3996 | abort (); | |
3997 | break; | |
3998 | } | |
3999 | i.vex.bytes[3] |= vec_length; | |
4000 | /* Encode the broadcast bit. */ | |
5273a3cd | 4001 | if (i.broadcast.type) |
43234a1e L |
4002 | i.vex.bytes[3] |= 0x10; |
4003 | } | |
ca5312a2 JB |
4004 | else if (i.rounding.type != saeonly) |
4005 | i.vex.bytes[3] |= 0x10 | (i.rounding.type << 5); | |
43234a1e | 4006 | else |
ca5312a2 | 4007 | i.vex.bytes[3] |= 0x10 | (evexrcig << 5); |
43234a1e | 4008 | |
6225c532 JB |
4009 | if (i.mask.reg) |
4010 | i.vex.bytes[3] |= i.mask.reg->reg_num; | |
43234a1e L |
4011 | } |
4012 | ||
65da13b5 L |
4013 | static void |
4014 | process_immext (void) | |
4015 | { | |
4016 | expressionS *exp; | |
4017 | ||
c0f3af97 | 4018 | /* These AMD 3DNow! and SSE2 instructions have an opcode suffix |
65da13b5 L |
4019 | which is coded in the same place as an 8-bit immediate field |
4020 | would be. Here we fake an 8-bit immediate operand from the | |
4021 | opcode suffix stored in tm.extension_opcode. | |
4022 | ||
c1e679ec | 4023 | AVX instructions also use this encoding, for some of |
c0f3af97 | 4024 | 3 argument instructions. */ |
65da13b5 | 4025 | |
43234a1e | 4026 | gas_assert (i.imm_operands <= 1 |
7ab9ffdd | 4027 | && (i.operands <= 2 |
7a8655d2 | 4028 | || (is_any_vex_encoding (&i.tm) |
7ab9ffdd | 4029 | && i.operands <= 4))); |
65da13b5 L |
4030 | |
4031 | exp = &im_expressions[i.imm_operands++]; | |
4032 | i.op[i.operands].imms = exp; | |
4033 | i.types[i.operands] = imm8; | |
4034 | i.operands++; | |
4035 | exp->X_op = O_constant; | |
4036 | exp->X_add_number = i.tm.extension_opcode; | |
4037 | i.tm.extension_opcode = None; | |
4038 | } | |
4039 | ||
42164a71 L |
4040 | |
4041 | static int | |
4042 | check_hle (void) | |
4043 | { | |
742732c7 | 4044 | switch (i.tm.opcode_modifier.prefixok) |
42164a71 L |
4045 | { |
4046 | default: | |
4047 | abort (); | |
742732c7 JB |
4048 | case PrefixLock: |
4049 | case PrefixNone: | |
4050 | case PrefixNoTrack: | |
4051 | case PrefixRep: | |
165de32a L |
4052 | as_bad (_("invalid instruction `%s' after `%s'"), |
4053 | i.tm.name, i.hle_prefix); | |
42164a71 | 4054 | return 0; |
742732c7 | 4055 | case PrefixHLELock: |
42164a71 L |
4056 | if (i.prefix[LOCK_PREFIX]) |
4057 | return 1; | |
165de32a | 4058 | as_bad (_("missing `lock' with `%s'"), i.hle_prefix); |
42164a71 | 4059 | return 0; |
742732c7 | 4060 | case PrefixHLEAny: |
42164a71 | 4061 | return 1; |
742732c7 | 4062 | case PrefixHLERelease: |
42164a71 L |
4063 | if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE) |
4064 | { | |
4065 | as_bad (_("instruction `%s' after `xacquire' not allowed"), | |
4066 | i.tm.name); | |
4067 | return 0; | |
4068 | } | |
8dc0818e | 4069 | if (i.mem_operands == 0 || !(i.flags[i.operands - 1] & Operand_Mem)) |
42164a71 L |
4070 | { |
4071 | as_bad (_("memory destination needed for instruction `%s'" | |
4072 | " after `xrelease'"), i.tm.name); | |
4073 | return 0; | |
4074 | } | |
4075 | return 1; | |
4076 | } | |
4077 | } | |
4078 | ||
b6f8c7c4 L |
4079 | /* Try the shortest encoding by shortening operand size. */ |
4080 | ||
4081 | static void | |
4082 | optimize_encoding (void) | |
4083 | { | |
a0a1771e | 4084 | unsigned int j; |
b6f8c7c4 | 4085 | |
fe134c65 JB |
4086 | if (i.tm.opcode_modifier.opcodespace == SPACE_BASE |
4087 | && i.tm.base_opcode == 0x8d) | |
4088 | { | |
4089 | /* Optimize: -O: | |
4090 | lea symbol, %rN -> mov $symbol, %rN | |
4091 | lea (%rM), %rN -> mov %rM, %rN | |
4092 | lea (,%rM,1), %rN -> mov %rM, %rN | |
4093 | ||
4094 | and in 32-bit mode for 16-bit addressing | |
4095 | ||
4096 | lea (%rM), %rN -> movzx %rM, %rN | |
4097 | ||
4098 | and in 64-bit mode zap 32-bit addressing in favor of using a | |
4099 | 32-bit (or less) destination. | |
4100 | */ | |
4101 | if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX]) | |
4102 | { | |
4103 | if (!i.op[1].regs->reg_type.bitfield.word) | |
4104 | i.tm.opcode_modifier.size = SIZE32; | |
4105 | i.prefix[ADDR_PREFIX] = 0; | |
4106 | } | |
4107 | ||
4108 | if (!i.index_reg && !i.base_reg) | |
4109 | { | |
4110 | /* Handle: | |
4111 | lea symbol, %rN -> mov $symbol, %rN | |
4112 | */ | |
4113 | if (flag_code == CODE_64BIT) | |
4114 | { | |
4115 | /* Don't transform a relocation to a 16-bit one. */ | |
4116 | if (i.op[0].disps | |
4117 | && i.op[0].disps->X_op != O_constant | |
4118 | && i.op[1].regs->reg_type.bitfield.word) | |
4119 | return; | |
4120 | ||
4121 | if (!i.op[1].regs->reg_type.bitfield.qword | |
4122 | || i.tm.opcode_modifier.size == SIZE32) | |
4123 | { | |
4124 | i.tm.base_opcode = 0xb8; | |
4125 | i.tm.opcode_modifier.modrm = 0; | |
4126 | if (!i.op[1].regs->reg_type.bitfield.word) | |
4127 | i.types[0].bitfield.imm32 = 1; | |
4128 | else | |
4129 | { | |
4130 | i.tm.opcode_modifier.size = SIZE16; | |
4131 | i.types[0].bitfield.imm16 = 1; | |
4132 | } | |
4133 | } | |
4134 | else | |
4135 | { | |
4136 | /* Subject to further optimization below. */ | |
4137 | i.tm.base_opcode = 0xc7; | |
4138 | i.tm.extension_opcode = 0; | |
4139 | i.types[0].bitfield.imm32s = 1; | |
4140 | i.types[0].bitfield.baseindex = 0; | |
4141 | } | |
4142 | } | |
4143 | /* Outside of 64-bit mode address and operand sizes have to match if | |
4144 | a relocation is involved, as otherwise we wouldn't (currently) or | |
4145 | even couldn't express the relocation correctly. */ | |
4146 | else if (i.op[0].disps | |
4147 | && i.op[0].disps->X_op != O_constant | |
4148 | && ((!i.prefix[ADDR_PREFIX]) | |
4149 | != (flag_code == CODE_32BIT | |
4150 | ? i.op[1].regs->reg_type.bitfield.dword | |
4151 | : i.op[1].regs->reg_type.bitfield.word))) | |
4152 | return; | |
4153 | else | |
4154 | { | |
4155 | i.tm.base_opcode = 0xb8; | |
4156 | i.tm.opcode_modifier.modrm = 0; | |
4157 | if (i.op[1].regs->reg_type.bitfield.dword) | |
4158 | i.types[0].bitfield.imm32 = 1; | |
4159 | else | |
4160 | i.types[0].bitfield.imm16 = 1; | |
4161 | ||
4162 | if (i.op[0].disps | |
4163 | && i.op[0].disps->X_op == O_constant | |
4164 | && i.op[1].regs->reg_type.bitfield.dword | |
60cfa10c L |
4165 | /* NB: Add () to !i.prefix[ADDR_PREFIX] to silence |
4166 | GCC 5. */ | |
4167 | && (!i.prefix[ADDR_PREFIX]) != (flag_code == CODE_32BIT)) | |
fe134c65 JB |
4168 | i.op[0].disps->X_add_number &= 0xffff; |
4169 | } | |
4170 | ||
4171 | i.tm.operand_types[0] = i.types[0]; | |
4172 | i.imm_operands = 1; | |
4173 | if (!i.op[0].imms) | |
4174 | { | |
4175 | i.op[0].imms = &im_expressions[0]; | |
4176 | i.op[0].imms->X_op = O_absent; | |
4177 | } | |
4178 | } | |
4179 | else if (i.op[0].disps | |
4180 | && (i.op[0].disps->X_op != O_constant | |
4181 | || i.op[0].disps->X_add_number)) | |
4182 | return; | |
4183 | else | |
4184 | { | |
4185 | /* Handle: | |
4186 | lea (%rM), %rN -> mov %rM, %rN | |
4187 | lea (,%rM,1), %rN -> mov %rM, %rN | |
4188 | lea (%rM), %rN -> movzx %rM, %rN | |
4189 | */ | |
4190 | const reg_entry *addr_reg; | |
4191 | ||
4192 | if (!i.index_reg && i.base_reg->reg_num != RegIP) | |
4193 | addr_reg = i.base_reg; | |
4194 | else if (!i.base_reg | |
4195 | && i.index_reg->reg_num != RegIZ | |
4196 | && !i.log2_scale_factor) | |
4197 | addr_reg = i.index_reg; | |
4198 | else | |
4199 | return; | |
4200 | ||
4201 | if (addr_reg->reg_type.bitfield.word | |
4202 | && i.op[1].regs->reg_type.bitfield.dword) | |
4203 | { | |
4204 | if (flag_code != CODE_32BIT) | |
4205 | return; | |
4206 | i.tm.opcode_modifier.opcodespace = SPACE_0F; | |
4207 | i.tm.base_opcode = 0xb7; | |
4208 | } | |
4209 | else | |
4210 | i.tm.base_opcode = 0x8b; | |
4211 | ||
4212 | if (addr_reg->reg_type.bitfield.dword | |
4213 | && i.op[1].regs->reg_type.bitfield.qword) | |
4214 | i.tm.opcode_modifier.size = SIZE32; | |
4215 | ||
4216 | i.op[0].regs = addr_reg; | |
4217 | i.reg_operands = 2; | |
4218 | } | |
4219 | ||
4220 | i.mem_operands = 0; | |
4221 | i.disp_operands = 0; | |
4222 | i.prefix[ADDR_PREFIX] = 0; | |
4223 | i.prefix[SEG_PREFIX] = 0; | |
4224 | i.seg[0] = NULL; | |
4225 | } | |
4226 | ||
b6f8c7c4 | 4227 | if (optimize_for_space |
389d00a5 | 4228 | && i.tm.opcode_modifier.opcodespace == SPACE_BASE |
b6f8c7c4 L |
4229 | && i.reg_operands == 1 |
4230 | && i.imm_operands == 1 | |
4231 | && !i.types[1].bitfield.byte | |
4232 | && i.op[0].imms->X_op == O_constant | |
4233 | && fits_in_imm7 (i.op[0].imms->X_add_number) | |
72aea328 | 4234 | && (i.tm.base_opcode == 0xa8 |
b6f8c7c4 L |
4235 | || (i.tm.base_opcode == 0xf6 |
4236 | && i.tm.extension_opcode == 0x0))) | |
4237 | { | |
4238 | /* Optimize: -Os: | |
4239 | test $imm7, %r64/%r32/%r16 -> test $imm7, %r8 | |
4240 | */ | |
4241 | unsigned int base_regnum = i.op[1].regs->reg_num; | |
4242 | if (flag_code == CODE_64BIT || base_regnum < 4) | |
4243 | { | |
4244 | i.types[1].bitfield.byte = 1; | |
4245 | /* Ignore the suffix. */ | |
4246 | i.suffix = 0; | |
7697afb6 JB |
4247 | /* Convert to byte registers. */ |
4248 | if (i.types[1].bitfield.word) | |
4249 | j = 16; | |
4250 | else if (i.types[1].bitfield.dword) | |
4251 | j = 32; | |
4252 | else | |
4253 | j = 48; | |
4254 | if (!(i.op[1].regs->reg_flags & RegRex) && base_regnum < 4) | |
4255 | j += 8; | |
4256 | i.op[1].regs -= j; | |
b6f8c7c4 L |
4257 | } |
4258 | } | |
4259 | else if (flag_code == CODE_64BIT | |
389d00a5 | 4260 | && i.tm.opcode_modifier.opcodespace == SPACE_BASE |
d3d50934 L |
4261 | && ((i.types[1].bitfield.qword |
4262 | && i.reg_operands == 1 | |
b6f8c7c4 L |
4263 | && i.imm_operands == 1 |
4264 | && i.op[0].imms->X_op == O_constant | |
507916b8 | 4265 | && ((i.tm.base_opcode == 0xb8 |
b6f8c7c4 L |
4266 | && i.tm.extension_opcode == None |
4267 | && fits_in_unsigned_long (i.op[0].imms->X_add_number)) | |
4268 | || (fits_in_imm31 (i.op[0].imms->X_add_number) | |
72aea328 JB |
4269 | && ((i.tm.base_opcode == 0x24 |
4270 | || i.tm.base_opcode == 0xa8) | |
b6f8c7c4 L |
4271 | || (i.tm.base_opcode == 0x80 |
4272 | && i.tm.extension_opcode == 0x4) | |
4273 | || ((i.tm.base_opcode == 0xf6 | |
507916b8 | 4274 | || (i.tm.base_opcode | 1) == 0xc7) |
b8364fa7 JB |
4275 | && i.tm.extension_opcode == 0x0))) |
4276 | || (fits_in_imm7 (i.op[0].imms->X_add_number) | |
4277 | && i.tm.base_opcode == 0x83 | |
4278 | && i.tm.extension_opcode == 0x4))) | |
d3d50934 L |
4279 | || (i.types[0].bitfield.qword |
4280 | && ((i.reg_operands == 2 | |
4281 | && i.op[0].regs == i.op[1].regs | |
72aea328 JB |
4282 | && (i.tm.base_opcode == 0x30 |
4283 | || i.tm.base_opcode == 0x28)) | |
d3d50934 L |
4284 | || (i.reg_operands == 1 |
4285 | && i.operands == 1 | |
72aea328 | 4286 | && i.tm.base_opcode == 0x30))))) |
b6f8c7c4 L |
4287 | { |
4288 | /* Optimize: -O: | |
4289 | andq $imm31, %r64 -> andl $imm31, %r32 | |
b8364fa7 | 4290 | andq $imm7, %r64 -> andl $imm7, %r32 |
b6f8c7c4 L |
4291 | testq $imm31, %r64 -> testl $imm31, %r32 |
4292 | xorq %r64, %r64 -> xorl %r32, %r32 | |
4293 | subq %r64, %r64 -> subl %r32, %r32 | |
4294 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4295 | movq $imm32, %r64 -> movl $imm32, %r32 | |
4296 | */ | |
4297 | i.tm.opcode_modifier.norex64 = 1; | |
507916b8 | 4298 | if (i.tm.base_opcode == 0xb8 || (i.tm.base_opcode | 1) == 0xc7) |
b6f8c7c4 L |
4299 | { |
4300 | /* Handle | |
4301 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4302 | movq $imm32, %r64 -> movl $imm32, %r32 | |
4303 | */ | |
4304 | i.tm.operand_types[0].bitfield.imm32 = 1; | |
4305 | i.tm.operand_types[0].bitfield.imm32s = 0; | |
4306 | i.tm.operand_types[0].bitfield.imm64 = 0; | |
4307 | i.types[0].bitfield.imm32 = 1; | |
4308 | i.types[0].bitfield.imm32s = 0; | |
4309 | i.types[0].bitfield.imm64 = 0; | |
4310 | i.types[1].bitfield.dword = 1; | |
4311 | i.types[1].bitfield.qword = 0; | |
507916b8 | 4312 | if ((i.tm.base_opcode | 1) == 0xc7) |
b6f8c7c4 L |
4313 | { |
4314 | /* Handle | |
4315 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4316 | */ | |
507916b8 | 4317 | i.tm.base_opcode = 0xb8; |
b6f8c7c4 | 4318 | i.tm.extension_opcode = None; |
507916b8 | 4319 | i.tm.opcode_modifier.w = 0; |
b6f8c7c4 L |
4320 | i.tm.opcode_modifier.modrm = 0; |
4321 | } | |
4322 | } | |
4323 | } | |
5641ec01 JB |
4324 | else if (optimize > 1 |
4325 | && !optimize_for_space | |
389d00a5 | 4326 | && i.tm.opcode_modifier.opcodespace == SPACE_BASE |
5641ec01 JB |
4327 | && i.reg_operands == 2 |
4328 | && i.op[0].regs == i.op[1].regs | |
4329 | && ((i.tm.base_opcode & ~(Opcode_D | 1)) == 0x8 | |
4330 | || (i.tm.base_opcode & ~(Opcode_D | 1)) == 0x20) | |
4331 | && (flag_code != CODE_64BIT || !i.types[0].bitfield.dword)) | |
4332 | { | |
4333 | /* Optimize: -O2: | |
4334 | andb %rN, %rN -> testb %rN, %rN | |
4335 | andw %rN, %rN -> testw %rN, %rN | |
4336 | andq %rN, %rN -> testq %rN, %rN | |
4337 | orb %rN, %rN -> testb %rN, %rN | |
4338 | orw %rN, %rN -> testw %rN, %rN | |
4339 | orq %rN, %rN -> testq %rN, %rN | |
4340 | ||
4341 | and outside of 64-bit mode | |
4342 | ||
4343 | andl %rN, %rN -> testl %rN, %rN | |
4344 | orl %rN, %rN -> testl %rN, %rN | |
4345 | */ | |
4346 | i.tm.base_opcode = 0x84 | (i.tm.base_opcode & 1); | |
4347 | } | |
99112332 | 4348 | else if (i.reg_operands == 3 |
b6f8c7c4 L |
4349 | && i.op[0].regs == i.op[1].regs |
4350 | && !i.types[2].bitfield.xmmword | |
4351 | && (i.tm.opcode_modifier.vex | |
6225c532 | 4352 | || ((!i.mask.reg || i.mask.zeroing) |
ca5312a2 | 4353 | && i.rounding.type == rc_none |
e771e7c9 | 4354 | && is_evex_encoding (&i.tm) |
80c34c38 | 4355 | && (i.vec_encoding != vex_encoding_evex |
dd22218c | 4356 | || cpu_arch_isa_flags.bitfield.cpuavx512vl |
80c34c38 | 4357 | || i.tm.cpu_flags.bitfield.cpuavx512vl |
7091c612 | 4358 | || (i.tm.operand_types[2].bitfield.zmmword |
dd22218c | 4359 | && i.types[2].bitfield.ymmword)))) |
b6f8c7c4 | 4360 | && ((i.tm.base_opcode == 0x55 |
b6f8c7c4 | 4361 | || i.tm.base_opcode == 0x57 |
35648716 JB |
4362 | || i.tm.base_opcode == 0xdf |
4363 | || i.tm.base_opcode == 0xef | |
4364 | || i.tm.base_opcode == 0xf8 | |
4365 | || i.tm.base_opcode == 0xf9 | |
4366 | || i.tm.base_opcode == 0xfa | |
4367 | || i.tm.base_opcode == 0xfb | |
1424ad86 | 4368 | || i.tm.base_opcode == 0x42 |
35648716 | 4369 | || i.tm.base_opcode == 0x47) |
b6f8c7c4 L |
4370 | && i.tm.extension_opcode == None)) |
4371 | { | |
99112332 | 4372 | /* Optimize: -O1: |
8305403a L |
4373 | VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd, |
4374 | vpsubq and vpsubw: | |
b6f8c7c4 L |
4375 | EVEX VOP %zmmM, %zmmM, %zmmN |
4376 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4377 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4378 | EVEX VOP %ymmM, %ymmM, %ymmN |
4379 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4380 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4381 | VEX VOP %ymmM, %ymmM, %ymmN |
4382 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
4383 | VOP, one of vpandn and vpxor: | |
4384 | VEX VOP %ymmM, %ymmM, %ymmN | |
4385 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
4386 | VOP, one of vpandnd and vpandnq: | |
4387 | EVEX VOP %zmmM, %zmmM, %zmmN | |
4388 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4389 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4390 | EVEX VOP %ymmM, %ymmM, %ymmN |
4391 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4392 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4393 | VOP, one of vpxord and vpxorq: |
4394 | EVEX VOP %zmmM, %zmmM, %zmmN | |
4395 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4396 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4397 | EVEX VOP %ymmM, %ymmM, %ymmN |
4398 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4399 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
1424ad86 JB |
4400 | VOP, one of kxord and kxorq: |
4401 | VEX VOP %kM, %kM, %kN | |
4402 | -> VEX kxorw %kM, %kM, %kN | |
4403 | VOP, one of kandnd and kandnq: | |
4404 | VEX VOP %kM, %kM, %kN | |
4405 | -> VEX kandnw %kM, %kM, %kN | |
b6f8c7c4 | 4406 | */ |
e771e7c9 | 4407 | if (is_evex_encoding (&i.tm)) |
b6f8c7c4 | 4408 | { |
7b1d7ca1 | 4409 | if (i.vec_encoding != vex_encoding_evex) |
b6f8c7c4 L |
4410 | { |
4411 | i.tm.opcode_modifier.vex = VEX128; | |
4412 | i.tm.opcode_modifier.vexw = VEXW0; | |
4413 | i.tm.opcode_modifier.evex = 0; | |
4414 | } | |
7b1d7ca1 | 4415 | else if (optimize > 1) |
dd22218c L |
4416 | i.tm.opcode_modifier.evex = EVEX128; |
4417 | else | |
4418 | return; | |
b6f8c7c4 | 4419 | } |
f74a6307 | 4420 | else if (i.tm.operand_types[0].bitfield.class == RegMask) |
1424ad86 | 4421 | { |
35648716 | 4422 | i.tm.opcode_modifier.opcodeprefix = PREFIX_NONE; |
1424ad86 JB |
4423 | i.tm.opcode_modifier.vexw = VEXW0; |
4424 | } | |
b6f8c7c4 L |
4425 | else |
4426 | i.tm.opcode_modifier.vex = VEX128; | |
4427 | ||
4428 | if (i.tm.opcode_modifier.vex) | |
4429 | for (j = 0; j < 3; j++) | |
4430 | { | |
4431 | i.types[j].bitfield.xmmword = 1; | |
4432 | i.types[j].bitfield.ymmword = 0; | |
4433 | } | |
4434 | } | |
392a5972 | 4435 | else if (i.vec_encoding != vex_encoding_evex |
97ed31ae | 4436 | && !i.types[0].bitfield.zmmword |
392a5972 | 4437 | && !i.types[1].bitfield.zmmword |
6225c532 | 4438 | && !i.mask.reg |
5273a3cd | 4439 | && !i.broadcast.type |
97ed31ae | 4440 | && is_evex_encoding (&i.tm) |
35648716 JB |
4441 | && ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0x6f |
4442 | || (i.tm.base_opcode & ~4) == 0xdb | |
4443 | || (i.tm.base_opcode & ~4) == 0xeb) | |
97ed31ae L |
4444 | && i.tm.extension_opcode == None) |
4445 | { | |
4446 | /* Optimize: -O1: | |
4447 | VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, | |
4448 | vmovdqu32 and vmovdqu64: | |
4449 | EVEX VOP %xmmM, %xmmN | |
4450 | -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16) | |
4451 | EVEX VOP %ymmM, %ymmN | |
4452 | -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16) | |
4453 | EVEX VOP %xmmM, mem | |
4454 | -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16) | |
4455 | EVEX VOP %ymmM, mem | |
4456 | -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16) | |
4457 | EVEX VOP mem, %xmmN | |
4458 | -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16) | |
4459 | EVEX VOP mem, %ymmN | |
4460 | -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16) | |
a0a1771e JB |
4461 | VOP, one of vpand, vpandn, vpor, vpxor: |
4462 | EVEX VOP{d,q} %xmmL, %xmmM, %xmmN | |
4463 | -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16) | |
4464 | EVEX VOP{d,q} %ymmL, %ymmM, %ymmN | |
4465 | -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16) | |
4466 | EVEX VOP{d,q} mem, %xmmM, %xmmN | |
4467 | -> VEX VOP mem, %xmmM, %xmmN (M and N < 16) | |
4468 | EVEX VOP{d,q} mem, %ymmM, %ymmN | |
4469 | -> VEX VOP mem, %ymmM, %ymmN (M and N < 16) | |
97ed31ae | 4470 | */ |
a0a1771e | 4471 | for (j = 0; j < i.operands; j++) |
392a5972 L |
4472 | if (operand_type_check (i.types[j], disp) |
4473 | && i.op[j].disps->X_op == O_constant) | |
4474 | { | |
4475 | /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix | |
4476 | has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4 | |
4477 | bytes, we choose EVEX Disp8 over VEX Disp32. */ | |
4478 | int evex_disp8, vex_disp8; | |
4479 | unsigned int memshift = i.memshift; | |
4480 | offsetT n = i.op[j].disps->X_add_number; | |
4481 | ||
4482 | evex_disp8 = fits_in_disp8 (n); | |
4483 | i.memshift = 0; | |
4484 | vex_disp8 = fits_in_disp8 (n); | |
4485 | if (evex_disp8 != vex_disp8) | |
4486 | { | |
4487 | i.memshift = memshift; | |
4488 | return; | |
4489 | } | |
4490 | ||
4491 | i.types[j].bitfield.disp8 = vex_disp8; | |
4492 | break; | |
4493 | } | |
35648716 JB |
4494 | if ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0x6f |
4495 | && i.tm.opcode_modifier.opcodeprefix == PREFIX_0XF2) | |
4496 | i.tm.opcode_modifier.opcodeprefix = PREFIX_0XF3; | |
97ed31ae L |
4497 | i.tm.opcode_modifier.vex |
4498 | = i.types[0].bitfield.ymmword ? VEX256 : VEX128; | |
4499 | i.tm.opcode_modifier.vexw = VEXW0; | |
79dec6b7 | 4500 | /* VPAND, VPOR, and VPXOR are commutative. */ |
35648716 | 4501 | if (i.reg_operands == 3 && i.tm.base_opcode != 0xdf) |
79dec6b7 | 4502 | i.tm.opcode_modifier.commutative = 1; |
97ed31ae L |
4503 | i.tm.opcode_modifier.evex = 0; |
4504 | i.tm.opcode_modifier.masking = 0; | |
a0a1771e | 4505 | i.tm.opcode_modifier.broadcast = 0; |
97ed31ae L |
4506 | i.tm.opcode_modifier.disp8memshift = 0; |
4507 | i.memshift = 0; | |
a0a1771e JB |
4508 | if (j < i.operands) |
4509 | i.types[j].bitfield.disp8 | |
4510 | = fits_in_disp8 (i.op[j].disps->X_add_number); | |
97ed31ae | 4511 | } |
b6f8c7c4 L |
4512 | } |
4513 | ||
ae531041 L |
4514 | /* Return non-zero for load instruction. */ |
4515 | ||
4516 | static int | |
4517 | load_insn_p (void) | |
4518 | { | |
4519 | unsigned int dest; | |
4520 | int any_vex_p = is_any_vex_encoding (&i.tm); | |
4521 | unsigned int base_opcode = i.tm.base_opcode | 1; | |
4522 | ||
4523 | if (!any_vex_p) | |
4524 | { | |
a09f656b | 4525 | /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0, |
4526 | prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn, | |
4527 | bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */ | |
4528 | if (i.tm.opcode_modifier.anysize) | |
ae531041 L |
4529 | return 0; |
4530 | ||
389d00a5 JB |
4531 | /* pop. */ |
4532 | if (strcmp (i.tm.name, "pop") == 0) | |
4533 | return 1; | |
4534 | } | |
4535 | ||
4536 | if (i.tm.opcode_modifier.opcodespace == SPACE_BASE) | |
4537 | { | |
4538 | /* popf, popa. */ | |
4539 | if (i.tm.base_opcode == 0x9d | |
a09f656b | 4540 | || i.tm.base_opcode == 0x61) |
ae531041 L |
4541 | return 1; |
4542 | ||
4543 | /* movs, cmps, lods, scas. */ | |
4544 | if ((i.tm.base_opcode | 0xb) == 0xaf) | |
4545 | return 1; | |
4546 | ||
a09f656b | 4547 | /* outs, xlatb. */ |
4548 | if (base_opcode == 0x6f | |
4549 | || i.tm.base_opcode == 0xd7) | |
ae531041 | 4550 | return 1; |
a09f656b | 4551 | /* NB: For AMD-specific insns with implicit memory operands, |
4552 | they're intentionally not covered. */ | |
ae531041 L |
4553 | } |
4554 | ||
4555 | /* No memory operand. */ | |
4556 | if (!i.mem_operands) | |
4557 | return 0; | |
4558 | ||
4559 | if (any_vex_p) | |
4560 | { | |
4561 | /* vldmxcsr. */ | |
4562 | if (i.tm.base_opcode == 0xae | |
4563 | && i.tm.opcode_modifier.vex | |
441f6aca | 4564 | && i.tm.opcode_modifier.opcodespace == SPACE_0F |
35648716 | 4565 | && i.tm.opcode_modifier.opcodeprefix == PREFIX_NONE |
ae531041 L |
4566 | && i.tm.extension_opcode == 2) |
4567 | return 1; | |
4568 | } | |
389d00a5 | 4569 | else if (i.tm.opcode_modifier.opcodespace == SPACE_BASE) |
ae531041 L |
4570 | { |
4571 | /* test, not, neg, mul, imul, div, idiv. */ | |
4572 | if ((i.tm.base_opcode == 0xf6 || i.tm.base_opcode == 0xf7) | |
4573 | && i.tm.extension_opcode != 1) | |
4574 | return 1; | |
4575 | ||
4576 | /* inc, dec. */ | |
4577 | if (base_opcode == 0xff && i.tm.extension_opcode <= 1) | |
4578 | return 1; | |
4579 | ||
4580 | /* add, or, adc, sbb, and, sub, xor, cmp. */ | |
4581 | if (i.tm.base_opcode >= 0x80 && i.tm.base_opcode <= 0x83) | |
4582 | return 1; | |
4583 | ||
ae531041 L |
4584 | /* rol, ror, rcl, rcr, shl/sal, shr, sar. */ |
4585 | if ((base_opcode == 0xc1 | |
4586 | || (i.tm.base_opcode >= 0xd0 && i.tm.base_opcode <= 0xd3)) | |
4587 | && i.tm.extension_opcode != 6) | |
4588 | return 1; | |
4589 | ||
ae531041 | 4590 | /* Check for x87 instructions. */ |
389d00a5 | 4591 | if (base_opcode >= 0xd8 && base_opcode <= 0xdf) |
ae531041 L |
4592 | { |
4593 | /* Skip fst, fstp, fstenv, fstcw. */ | |
4594 | if (i.tm.base_opcode == 0xd9 | |
4595 | && (i.tm.extension_opcode == 2 | |
4596 | || i.tm.extension_opcode == 3 | |
4597 | || i.tm.extension_opcode == 6 | |
4598 | || i.tm.extension_opcode == 7)) | |
4599 | return 0; | |
4600 | ||
4601 | /* Skip fisttp, fist, fistp, fstp. */ | |
4602 | if (i.tm.base_opcode == 0xdb | |
4603 | && (i.tm.extension_opcode == 1 | |
4604 | || i.tm.extension_opcode == 2 | |
4605 | || i.tm.extension_opcode == 3 | |
4606 | || i.tm.extension_opcode == 7)) | |
4607 | return 0; | |
4608 | ||
4609 | /* Skip fisttp, fst, fstp, fsave, fstsw. */ | |
4610 | if (i.tm.base_opcode == 0xdd | |
4611 | && (i.tm.extension_opcode == 1 | |
4612 | || i.tm.extension_opcode == 2 | |
4613 | || i.tm.extension_opcode == 3 | |
4614 | || i.tm.extension_opcode == 6 | |
4615 | || i.tm.extension_opcode == 7)) | |
4616 | return 0; | |
4617 | ||
4618 | /* Skip fisttp, fist, fistp, fbstp, fistp. */ | |
4619 | if (i.tm.base_opcode == 0xdf | |
4620 | && (i.tm.extension_opcode == 1 | |
4621 | || i.tm.extension_opcode == 2 | |
4622 | || i.tm.extension_opcode == 3 | |
4623 | || i.tm.extension_opcode == 6 | |
4624 | || i.tm.extension_opcode == 7)) | |
4625 | return 0; | |
4626 | ||
4627 | return 1; | |
4628 | } | |
4629 | } | |
389d00a5 JB |
4630 | else if (i.tm.opcode_modifier.opcodespace == SPACE_0F) |
4631 | { | |
4632 | /* bt, bts, btr, btc. */ | |
4633 | if (i.tm.base_opcode == 0xba | |
4634 | && (i.tm.extension_opcode >= 4 && i.tm.extension_opcode <= 7)) | |
4635 | return 1; | |
4636 | ||
4637 | /* cmpxchg8b, cmpxchg16b, xrstors, vmptrld. */ | |
4638 | if (i.tm.base_opcode == 0xc7 | |
4639 | && i.tm.opcode_modifier.opcodeprefix == PREFIX_NONE | |
4640 | && (i.tm.extension_opcode == 1 || i.tm.extension_opcode == 3 | |
4641 | || i.tm.extension_opcode == 6)) | |
4642 | return 1; | |
4643 | ||
4644 | /* fxrstor, ldmxcsr, xrstor. */ | |
4645 | if (i.tm.base_opcode == 0xae | |
4646 | && (i.tm.extension_opcode == 1 | |
4647 | || i.tm.extension_opcode == 2 | |
4648 | || i.tm.extension_opcode == 5)) | |
4649 | return 1; | |
4650 | ||
4651 | /* lgdt, lidt, lmsw. */ | |
4652 | if (i.tm.base_opcode == 0x01 | |
4653 | && (i.tm.extension_opcode == 2 | |
4654 | || i.tm.extension_opcode == 3 | |
4655 | || i.tm.extension_opcode == 6)) | |
4656 | return 1; | |
4657 | } | |
ae531041 L |
4658 | |
4659 | dest = i.operands - 1; | |
4660 | ||
4661 | /* Check fake imm8 operand and 3 source operands. */ | |
4662 | if ((i.tm.opcode_modifier.immext | |
4663 | || i.tm.opcode_modifier.vexsources == VEX3SOURCES) | |
4664 | && i.types[dest].bitfield.imm8) | |
4665 | dest--; | |
4666 | ||
389d00a5 JB |
4667 | /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg. */ |
4668 | if (i.tm.opcode_modifier.opcodespace == SPACE_BASE | |
ae531041 L |
4669 | && (base_opcode == 0x1 |
4670 | || base_opcode == 0x9 | |
4671 | || base_opcode == 0x11 | |
4672 | || base_opcode == 0x19 | |
4673 | || base_opcode == 0x21 | |
4674 | || base_opcode == 0x29 | |
4675 | || base_opcode == 0x31 | |
4676 | || base_opcode == 0x39 | |
389d00a5 JB |
4677 | || (base_opcode | 2) == 0x87)) |
4678 | return 1; | |
4679 | ||
4680 | /* xadd. */ | |
4681 | if (i.tm.opcode_modifier.opcodespace == SPACE_0F | |
4682 | && base_opcode == 0xc1) | |
ae531041 L |
4683 | return 1; |
4684 | ||
4685 | /* Check for load instruction. */ | |
4686 | return (i.types[dest].bitfield.class != ClassNone | |
4687 | || i.types[dest].bitfield.instance == Accum); | |
4688 | } | |
4689 | ||
4690 | /* Output lfence, 0xfaee8, after instruction. */ | |
4691 | ||
4692 | static void | |
4693 | insert_lfence_after (void) | |
4694 | { | |
4695 | if (lfence_after_load && load_insn_p ()) | |
4696 | { | |
a09f656b | 4697 | /* There are also two REP string instructions that require |
4698 | special treatment. Specifically, the compare string (CMPS) | |
4699 | and scan string (SCAS) instructions set EFLAGS in a manner | |
4700 | that depends on the data being compared/scanned. When used | |
4701 | with a REP prefix, the number of iterations may therefore | |
4702 | vary depending on this data. If the data is a program secret | |
4703 | chosen by the adversary using an LVI method, | |
4704 | then this data-dependent behavior may leak some aspect | |
4705 | of the secret. */ | |
4706 | if (((i.tm.base_opcode | 0x1) == 0xa7 | |
4707 | || (i.tm.base_opcode | 0x1) == 0xaf) | |
4708 | && i.prefix[REP_PREFIX]) | |
4709 | { | |
4710 | as_warn (_("`%s` changes flags which would affect control flow behavior"), | |
4711 | i.tm.name); | |
4712 | } | |
ae531041 L |
4713 | char *p = frag_more (3); |
4714 | *p++ = 0xf; | |
4715 | *p++ = 0xae; | |
4716 | *p = 0xe8; | |
4717 | } | |
4718 | } | |
4719 | ||
4720 | /* Output lfence, 0xfaee8, before instruction. */ | |
4721 | ||
4722 | static void | |
4723 | insert_lfence_before (void) | |
4724 | { | |
4725 | char *p; | |
4726 | ||
389d00a5 | 4727 | if (i.tm.opcode_modifier.opcodespace != SPACE_BASE) |
ae531041 L |
4728 | return; |
4729 | ||
4730 | if (i.tm.base_opcode == 0xff | |
4731 | && (i.tm.extension_opcode == 2 || i.tm.extension_opcode == 4)) | |
4732 | { | |
4733 | /* Insert lfence before indirect branch if needed. */ | |
4734 | ||
4735 | if (lfence_before_indirect_branch == lfence_branch_none) | |
4736 | return; | |
4737 | ||
4738 | if (i.operands != 1) | |
4739 | abort (); | |
4740 | ||
4741 | if (i.reg_operands == 1) | |
4742 | { | |
4743 | /* Indirect branch via register. Don't insert lfence with | |
4744 | -mlfence-after-load=yes. */ | |
4745 | if (lfence_after_load | |
4746 | || lfence_before_indirect_branch == lfence_branch_memory) | |
4747 | return; | |
4748 | } | |
4749 | else if (i.mem_operands == 1 | |
4750 | && lfence_before_indirect_branch != lfence_branch_register) | |
4751 | { | |
4752 | as_warn (_("indirect `%s` with memory operand should be avoided"), | |
4753 | i.tm.name); | |
4754 | return; | |
4755 | } | |
4756 | else | |
4757 | return; | |
4758 | ||
4759 | if (last_insn.kind != last_insn_other | |
4760 | && last_insn.seg == now_seg) | |
4761 | { | |
4762 | as_warn_where (last_insn.file, last_insn.line, | |
4763 | _("`%s` skips -mlfence-before-indirect-branch on `%s`"), | |
4764 | last_insn.name, i.tm.name); | |
4765 | return; | |
4766 | } | |
4767 | ||
4768 | p = frag_more (3); | |
4769 | *p++ = 0xf; | |
4770 | *p++ = 0xae; | |
4771 | *p = 0xe8; | |
4772 | return; | |
4773 | } | |
4774 | ||
503648e4 | 4775 | /* Output or/not/shl and lfence before near ret. */ |
ae531041 L |
4776 | if (lfence_before_ret != lfence_before_ret_none |
4777 | && (i.tm.base_opcode == 0xc2 | |
503648e4 | 4778 | || i.tm.base_opcode == 0xc3)) |
ae531041 L |
4779 | { |
4780 | if (last_insn.kind != last_insn_other | |
4781 | && last_insn.seg == now_seg) | |
4782 | { | |
4783 | as_warn_where (last_insn.file, last_insn.line, | |
4784 | _("`%s` skips -mlfence-before-ret on `%s`"), | |
4785 | last_insn.name, i.tm.name); | |
4786 | return; | |
4787 | } | |
a09f656b | 4788 | |
a09f656b | 4789 | /* Near ret ingore operand size override under CPU64. */ |
503648e4 | 4790 | char prefix = flag_code == CODE_64BIT |
4791 | ? 0x48 | |
4792 | : i.prefix[DATA_PREFIX] ? 0x66 : 0x0; | |
a09f656b | 4793 | |
4794 | if (lfence_before_ret == lfence_before_ret_not) | |
4795 | { | |
4796 | /* not: 0xf71424, may add prefix | |
4797 | for operand size override or 64-bit code. */ | |
4798 | p = frag_more ((prefix ? 2 : 0) + 6 + 3); | |
4799 | if (prefix) | |
4800 | *p++ = prefix; | |
ae531041 L |
4801 | *p++ = 0xf7; |
4802 | *p++ = 0x14; | |
4803 | *p++ = 0x24; | |
a09f656b | 4804 | if (prefix) |
4805 | *p++ = prefix; | |
ae531041 L |
4806 | *p++ = 0xf7; |
4807 | *p++ = 0x14; | |
4808 | *p++ = 0x24; | |
4809 | } | |
a09f656b | 4810 | else |
4811 | { | |
4812 | p = frag_more ((prefix ? 1 : 0) + 4 + 3); | |
4813 | if (prefix) | |
4814 | *p++ = prefix; | |
4815 | if (lfence_before_ret == lfence_before_ret_or) | |
4816 | { | |
4817 | /* or: 0x830c2400, may add prefix | |
4818 | for operand size override or 64-bit code. */ | |
4819 | *p++ = 0x83; | |
4820 | *p++ = 0x0c; | |
4821 | } | |
4822 | else | |
4823 | { | |
4824 | /* shl: 0xc1242400, may add prefix | |
4825 | for operand size override or 64-bit code. */ | |
4826 | *p++ = 0xc1; | |
4827 | *p++ = 0x24; | |
4828 | } | |
4829 | ||
4830 | *p++ = 0x24; | |
4831 | *p++ = 0x0; | |
4832 | } | |
4833 | ||
ae531041 L |
4834 | *p++ = 0xf; |
4835 | *p++ = 0xae; | |
4836 | *p = 0xe8; | |
4837 | } | |
4838 | } | |
4839 | ||
252b5132 RH |
4840 | /* This is the guts of the machine-dependent assembler. LINE points to a |
4841 | machine dependent instruction. This function is supposed to emit | |
4842 | the frags/bytes it assembles to. */ | |
4843 | ||
4844 | void | |
65da13b5 | 4845 | md_assemble (char *line) |
252b5132 | 4846 | { |
40fb9820 | 4847 | unsigned int j; |
83b16ac6 | 4848 | char mnemonic[MAX_MNEM_SIZE], mnem_suffix; |
d3ce72d0 | 4849 | const insn_template *t; |
252b5132 | 4850 | |
47926f60 | 4851 | /* Initialize globals. */ |
252b5132 | 4852 | memset (&i, '\0', sizeof (i)); |
ca5312a2 | 4853 | i.rounding.type = rc_none; |
252b5132 | 4854 | for (j = 0; j < MAX_OPERANDS; j++) |
1ae12ab7 | 4855 | i.reloc[j] = NO_RELOC; |
252b5132 RH |
4856 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
4857 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 4858 | save_stack_p = save_stack; |
252b5132 RH |
4859 | |
4860 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
4861 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 4862 | start of a (possibly prefixed) mnemonic. */ |
252b5132 | 4863 | |
29b0f896 AM |
4864 | line = parse_insn (line, mnemonic); |
4865 | if (line == NULL) | |
4866 | return; | |
83b16ac6 | 4867 | mnem_suffix = i.suffix; |
252b5132 | 4868 | |
29b0f896 | 4869 | line = parse_operands (line, mnemonic); |
ee86248c | 4870 | this_operand = -1; |
8325cc63 JB |
4871 | xfree (i.memop1_string); |
4872 | i.memop1_string = NULL; | |
29b0f896 AM |
4873 | if (line == NULL) |
4874 | return; | |
252b5132 | 4875 | |
29b0f896 AM |
4876 | /* Now we've parsed the mnemonic into a set of templates, and have the |
4877 | operands at hand. */ | |
4878 | ||
b630c145 | 4879 | /* All Intel opcodes have reversed operands except for "bound", "enter", |
c0e54661 JB |
4880 | "invlpg*", "monitor*", "mwait*", "tpause", "umwait", "pvalidate", |
4881 | "rmpadjust", and "rmpupdate". We also don't reverse intersegment "jmp" | |
4882 | and "call" instructions with 2 immediate operands so that the immediate | |
4883 | segment precedes the offset consistently in Intel and AT&T modes. */ | |
4d456e3d L |
4884 | if (intel_syntax |
4885 | && i.operands > 1 | |
29b0f896 | 4886 | && (strcmp (mnemonic, "bound") != 0) |
c0e54661 | 4887 | && (strncmp (mnemonic, "invlpg", 6) != 0) |
d34049e8 ML |
4888 | && !startswith (mnemonic, "monitor") |
4889 | && !startswith (mnemonic, "mwait") | |
c0e54661 | 4890 | && (strcmp (mnemonic, "pvalidate") != 0) |
d34049e8 | 4891 | && !startswith (mnemonic, "rmp") |
b630c145 JB |
4892 | && (strcmp (mnemonic, "tpause") != 0) |
4893 | && (strcmp (mnemonic, "umwait") != 0) | |
40fb9820 L |
4894 | && !(operand_type_check (i.types[0], imm) |
4895 | && operand_type_check (i.types[1], imm))) | |
29b0f896 AM |
4896 | swap_operands (); |
4897 | ||
ec56d5c0 JB |
4898 | /* The order of the immediates should be reversed |
4899 | for 2 immediates extrq and insertq instructions */ | |
4900 | if (i.imm_operands == 2 | |
4901 | && (strcmp (mnemonic, "extrq") == 0 | |
4902 | || strcmp (mnemonic, "insertq") == 0)) | |
4903 | swap_2_operands (0, 1); | |
4904 | ||
29b0f896 AM |
4905 | if (i.imm_operands) |
4906 | optimize_imm (); | |
4907 | ||
a9aabc23 | 4908 | if (i.disp_operands && !want_disp32 (current_templates->start)) |
cce08655 JB |
4909 | { |
4910 | for (j = 0; j < i.operands; ++j) | |
4911 | { | |
4912 | const expressionS *exp = i.op[j].disps; | |
4913 | ||
4914 | if (!operand_type_check (i.types[j], disp)) | |
4915 | continue; | |
4916 | ||
4917 | if (exp->X_op != O_constant) | |
4918 | continue; | |
4919 | ||
4920 | /* Since displacement is signed extended to 64bit, don't allow | |
4921 | disp32 and turn off disp32s if they are out of range. */ | |
4922 | i.types[j].bitfield.disp32 = 0; | |
4923 | if (fits_in_signed_long (exp->X_add_number)) | |
4924 | continue; | |
4925 | ||
4926 | i.types[j].bitfield.disp32s = 0; | |
4927 | if (i.types[j].bitfield.baseindex) | |
4928 | { | |
4929 | as_bad (_("0x%" BFD_VMA_FMT "x out of range of signed 32bit displacement"), | |
4930 | exp->X_add_number); | |
4931 | return; | |
4932 | } | |
4933 | } | |
4934 | } | |
4935 | ||
b300c311 L |
4936 | /* Don't optimize displacement for movabs since it only takes 64bit |
4937 | displacement. */ | |
4938 | if (i.disp_operands | |
a501d77e | 4939 | && i.disp_encoding != disp_encoding_32bit |
862be3fb L |
4940 | && (flag_code != CODE_64BIT |
4941 | || strcmp (mnemonic, "movabs") != 0)) | |
4942 | optimize_disp (); | |
29b0f896 AM |
4943 | |
4944 | /* Next, we find a template that matches the given insn, | |
4945 | making sure the overlap of the given operands types is consistent | |
4946 | with the template operand types. */ | |
252b5132 | 4947 | |
83b16ac6 | 4948 | if (!(t = match_template (mnem_suffix))) |
29b0f896 | 4949 | return; |
252b5132 | 4950 | |
7bab8ab5 | 4951 | if (sse_check != check_none |
81f8a913 | 4952 | && !i.tm.opcode_modifier.noavx |
6e3e5c9e | 4953 | && !i.tm.cpu_flags.bitfield.cpuavx |
569d50f1 | 4954 | && !i.tm.cpu_flags.bitfield.cpuavx512f |
daf50ae7 L |
4955 | && (i.tm.cpu_flags.bitfield.cpusse |
4956 | || i.tm.cpu_flags.bitfield.cpusse2 | |
4957 | || i.tm.cpu_flags.bitfield.cpusse3 | |
4958 | || i.tm.cpu_flags.bitfield.cpussse3 | |
4959 | || i.tm.cpu_flags.bitfield.cpusse4_1 | |
6e3e5c9e JB |
4960 | || i.tm.cpu_flags.bitfield.cpusse4_2 |
4961 | || i.tm.cpu_flags.bitfield.cpupclmul | |
4962 | || i.tm.cpu_flags.bitfield.cpuaes | |
569d50f1 | 4963 | || i.tm.cpu_flags.bitfield.cpusha |
6e3e5c9e | 4964 | || i.tm.cpu_flags.bitfield.cpugfni)) |
daf50ae7 | 4965 | { |
7bab8ab5 | 4966 | (sse_check == check_warning |
daf50ae7 L |
4967 | ? as_warn |
4968 | : as_bad) (_("SSE instruction `%s' is used"), i.tm.name); | |
4969 | } | |
4970 | ||
40fb9820 | 4971 | if (i.tm.opcode_modifier.fwait) |
29b0f896 AM |
4972 | if (!add_prefix (FWAIT_OPCODE)) |
4973 | return; | |
252b5132 | 4974 | |
d5de92cf | 4975 | /* Check if REP prefix is OK. */ |
742732c7 | 4976 | if (i.rep_prefix && i.tm.opcode_modifier.prefixok != PrefixRep) |
d5de92cf L |
4977 | { |
4978 | as_bad (_("invalid instruction `%s' after `%s'"), | |
4979 | i.tm.name, i.rep_prefix); | |
4980 | return; | |
4981 | } | |
4982 | ||
c1ba0266 L |
4983 | /* Check for lock without a lockable instruction. Destination operand |
4984 | must be memory unless it is xchg (0x86). */ | |
c32fa91d | 4985 | if (i.prefix[LOCK_PREFIX] |
742732c7 | 4986 | && (i.tm.opcode_modifier.prefixok < PrefixLock |
c1ba0266 L |
4987 | || i.mem_operands == 0 |
4988 | || (i.tm.base_opcode != 0x86 | |
8dc0818e | 4989 | && !(i.flags[i.operands - 1] & Operand_Mem)))) |
c32fa91d L |
4990 | { |
4991 | as_bad (_("expecting lockable instruction after `lock'")); | |
4992 | return; | |
4993 | } | |
4994 | ||
40d231b4 JB |
4995 | /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */ |
4996 | if (i.prefix[DATA_PREFIX] | |
4997 | && (is_any_vex_encoding (&i.tm) | |
4998 | || i.tm.operand_types[i.imm_operands].bitfield.class >= RegMMX | |
4999 | || i.tm.operand_types[i.imm_operands + 1].bitfield.class >= RegMMX)) | |
7a8655d2 JB |
5000 | { |
5001 | as_bad (_("data size prefix invalid with `%s'"), i.tm.name); | |
5002 | return; | |
5003 | } | |
5004 | ||
42164a71 | 5005 | /* Check if HLE prefix is OK. */ |
165de32a | 5006 | if (i.hle_prefix && !check_hle ()) |
42164a71 L |
5007 | return; |
5008 | ||
7e8b059b L |
5009 | /* Check BND prefix. */ |
5010 | if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok) | |
5011 | as_bad (_("expecting valid branch instruction after `bnd'")); | |
5012 | ||
04ef582a | 5013 | /* Check NOTRACK prefix. */ |
742732c7 | 5014 | if (i.notrack_prefix && i.tm.opcode_modifier.prefixok != PrefixNoTrack) |
9fef80d6 | 5015 | as_bad (_("expecting indirect branch instruction after `notrack'")); |
04ef582a | 5016 | |
327e8c42 JB |
5017 | if (i.tm.cpu_flags.bitfield.cpumpx) |
5018 | { | |
5019 | if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX]) | |
5020 | as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions.")); | |
5021 | else if (flag_code != CODE_16BIT | |
5022 | ? i.prefix[ADDR_PREFIX] | |
5023 | : i.mem_operands && !i.prefix[ADDR_PREFIX]) | |
5024 | as_bad (_("16-bit address isn't allowed in MPX instructions")); | |
5025 | } | |
7e8b059b L |
5026 | |
5027 | /* Insert BND prefix. */ | |
76d3a78a JB |
5028 | if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok) |
5029 | { | |
5030 | if (!i.prefix[BND_PREFIX]) | |
5031 | add_prefix (BND_PREFIX_OPCODE); | |
5032 | else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE) | |
5033 | { | |
5034 | as_warn (_("replacing `rep'/`repe' prefix by `bnd'")); | |
5035 | i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE; | |
5036 | } | |
5037 | } | |
7e8b059b | 5038 | |
29b0f896 | 5039 | /* Check string instruction segment overrides. */ |
51c8edf6 | 5040 | if (i.tm.opcode_modifier.isstring >= IS_STRING_ES_OP0) |
29b0f896 | 5041 | { |
51c8edf6 | 5042 | gas_assert (i.mem_operands); |
29b0f896 | 5043 | if (!check_string ()) |
5dd0794d | 5044 | return; |
fc0763e6 | 5045 | i.disp_operands = 0; |
29b0f896 | 5046 | } |
5dd0794d | 5047 | |
b6f8c7c4 L |
5048 | if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize) |
5049 | optimize_encoding (); | |
5050 | ||
29b0f896 AM |
5051 | if (!process_suffix ()) |
5052 | return; | |
e413e4e9 | 5053 | |
921eafea | 5054 | /* Update operand types and check extended states. */ |
bc0844ae | 5055 | for (j = 0; j < i.operands; j++) |
921eafea L |
5056 | { |
5057 | i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]); | |
3d70986f | 5058 | switch (i.tm.operand_types[j].bitfield.class) |
921eafea L |
5059 | { |
5060 | default: | |
5061 | break; | |
5062 | case RegMMX: | |
5063 | i.xstate |= xstate_mmx; | |
5064 | break; | |
5065 | case RegMask: | |
32930e4e | 5066 | i.xstate |= xstate_mask; |
921eafea L |
5067 | break; |
5068 | case RegSIMD: | |
3d70986f | 5069 | if (i.tm.operand_types[j].bitfield.tmmword) |
921eafea | 5070 | i.xstate |= xstate_tmm; |
3d70986f | 5071 | else if (i.tm.operand_types[j].bitfield.zmmword) |
921eafea | 5072 | i.xstate |= xstate_zmm; |
3d70986f | 5073 | else if (i.tm.operand_types[j].bitfield.ymmword) |
921eafea | 5074 | i.xstate |= xstate_ymm; |
3d70986f | 5075 | else if (i.tm.operand_types[j].bitfield.xmmword) |
921eafea L |
5076 | i.xstate |= xstate_xmm; |
5077 | break; | |
5078 | } | |
5079 | } | |
bc0844ae | 5080 | |
29b0f896 AM |
5081 | /* Make still unresolved immediate matches conform to size of immediate |
5082 | given in i.suffix. */ | |
5083 | if (!finalize_imm ()) | |
5084 | return; | |
252b5132 | 5085 | |
40fb9820 | 5086 | if (i.types[0].bitfield.imm1) |
29b0f896 | 5087 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 | 5088 | |
9afe6eb8 L |
5089 | /* We only need to check those implicit registers for instructions |
5090 | with 3 operands or less. */ | |
5091 | if (i.operands <= 3) | |
5092 | for (j = 0; j < i.operands; j++) | |
75e5731b JB |
5093 | if (i.types[j].bitfield.instance != InstanceNone |
5094 | && !i.types[j].bitfield.xmmword) | |
9afe6eb8 | 5095 | i.reg_operands--; |
40fb9820 | 5096 | |
29b0f896 AM |
5097 | /* For insns with operands there are more diddles to do to the opcode. */ |
5098 | if (i.operands) | |
5099 | { | |
5100 | if (!process_operands ()) | |
5101 | return; | |
5102 | } | |
8c190ce0 | 5103 | else if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 AM |
5104 | { |
5105 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ | |
5106 | as_warn (_("translating to `%sp'"), i.tm.name); | |
5107 | } | |
252b5132 | 5108 | |
7a8655d2 | 5109 | if (is_any_vex_encoding (&i.tm)) |
9e5e5283 | 5110 | { |
c1dc7af5 | 5111 | if (!cpu_arch_flags.bitfield.cpui286) |
9e5e5283 | 5112 | { |
c1dc7af5 | 5113 | as_bad (_("instruction `%s' isn't supported outside of protected mode."), |
9e5e5283 L |
5114 | i.tm.name); |
5115 | return; | |
5116 | } | |
c0f3af97 | 5117 | |
0b9404fd JB |
5118 | /* Check for explicit REX prefix. */ |
5119 | if (i.prefix[REX_PREFIX] || i.rex_encoding) | |
5120 | { | |
5121 | as_bad (_("REX prefix invalid with `%s'"), i.tm.name); | |
5122 | return; | |
5123 | } | |
5124 | ||
9e5e5283 L |
5125 | if (i.tm.opcode_modifier.vex) |
5126 | build_vex_prefix (t); | |
5127 | else | |
5128 | build_evex_prefix (); | |
0b9404fd JB |
5129 | |
5130 | /* The individual REX.RXBW bits got consumed. */ | |
5131 | i.rex &= REX_OPCODE; | |
9e5e5283 | 5132 | } |
43234a1e | 5133 | |
5dd85c99 SP |
5134 | /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4 |
5135 | instructions may define INT_OPCODE as well, so avoid this corner | |
5136 | case for those instructions that use MODRM. */ | |
389d00a5 JB |
5137 | if (i.tm.opcode_modifier.opcodespace == SPACE_BASE |
5138 | && i.tm.base_opcode == INT_OPCODE | |
a6461c02 SP |
5139 | && !i.tm.opcode_modifier.modrm |
5140 | && i.op[0].imms->X_add_number == 3) | |
29b0f896 AM |
5141 | { |
5142 | i.tm.base_opcode = INT3_OPCODE; | |
5143 | i.imm_operands = 0; | |
5144 | } | |
252b5132 | 5145 | |
0cfa3eb3 JB |
5146 | if ((i.tm.opcode_modifier.jump == JUMP |
5147 | || i.tm.opcode_modifier.jump == JUMP_BYTE | |
5148 | || i.tm.opcode_modifier.jump == JUMP_DWORD) | |
29b0f896 AM |
5149 | && i.op[0].disps->X_op == O_constant) |
5150 | { | |
5151 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
5152 | the absolute address given by the constant. Since ix86 jumps and | |
5153 | calls are pc relative, we need to generate a reloc. */ | |
5154 | i.op[0].disps->X_add_symbol = &abs_symbol; | |
5155 | i.op[0].disps->X_op = O_symbol; | |
5156 | } | |
252b5132 | 5157 | |
29b0f896 AM |
5158 | /* For 8 bit registers we need an empty rex prefix. Also if the |
5159 | instruction already has a prefix, we need to convert old | |
5160 | registers to new ones. */ | |
773f551c | 5161 | |
bab6aec1 | 5162 | if ((i.types[0].bitfield.class == Reg && i.types[0].bitfield.byte |
29b0f896 | 5163 | && (i.op[0].regs->reg_flags & RegRex64) != 0) |
bab6aec1 | 5164 | || (i.types[1].bitfield.class == Reg && i.types[1].bitfield.byte |
29b0f896 | 5165 | && (i.op[1].regs->reg_flags & RegRex64) != 0) |
bab6aec1 JB |
5166 | || (((i.types[0].bitfield.class == Reg && i.types[0].bitfield.byte) |
5167 | || (i.types[1].bitfield.class == Reg && i.types[1].bitfield.byte)) | |
29b0f896 AM |
5168 | && i.rex != 0)) |
5169 | { | |
5170 | int x; | |
726c5dcd | 5171 | |
29b0f896 AM |
5172 | i.rex |= REX_OPCODE; |
5173 | for (x = 0; x < 2; x++) | |
5174 | { | |
5175 | /* Look for 8 bit operand that uses old registers. */ | |
bab6aec1 | 5176 | if (i.types[x].bitfield.class == Reg && i.types[x].bitfield.byte |
29b0f896 | 5177 | && (i.op[x].regs->reg_flags & RegRex64) == 0) |
773f551c | 5178 | { |
3f93af61 | 5179 | gas_assert (!(i.op[x].regs->reg_flags & RegRex)); |
29b0f896 AM |
5180 | /* In case it is "hi" register, give up. */ |
5181 | if (i.op[x].regs->reg_num > 3) | |
a540244d | 5182 | as_bad (_("can't encode register '%s%s' in an " |
4eed87de | 5183 | "instruction requiring REX prefix."), |
a540244d | 5184 | register_prefix, i.op[x].regs->reg_name); |
773f551c | 5185 | |
29b0f896 AM |
5186 | /* Otherwise it is equivalent to the extended register. |
5187 | Since the encoding doesn't change this is merely | |
5188 | cosmetic cleanup for debug output. */ | |
5189 | ||
5190 | i.op[x].regs = i.op[x].regs + 8; | |
773f551c | 5191 | } |
29b0f896 AM |
5192 | } |
5193 | } | |
773f551c | 5194 | |
6b6b6807 L |
5195 | if (i.rex == 0 && i.rex_encoding) |
5196 | { | |
5197 | /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand | |
3f93af61 | 5198 | that uses legacy register. If it is "hi" register, don't add |
6b6b6807 L |
5199 | the REX_OPCODE byte. */ |
5200 | int x; | |
5201 | for (x = 0; x < 2; x++) | |
bab6aec1 | 5202 | if (i.types[x].bitfield.class == Reg |
6b6b6807 L |
5203 | && i.types[x].bitfield.byte |
5204 | && (i.op[x].regs->reg_flags & RegRex64) == 0 | |
5205 | && i.op[x].regs->reg_num > 3) | |
5206 | { | |
3f93af61 | 5207 | gas_assert (!(i.op[x].regs->reg_flags & RegRex)); |
5b7c81bd | 5208 | i.rex_encoding = false; |
6b6b6807 L |
5209 | break; |
5210 | } | |
5211 | ||
5212 | if (i.rex_encoding) | |
5213 | i.rex = REX_OPCODE; | |
5214 | } | |
5215 | ||
7ab9ffdd | 5216 | if (i.rex != 0) |
29b0f896 AM |
5217 | add_prefix (REX_OPCODE | i.rex); |
5218 | ||
ae531041 L |
5219 | insert_lfence_before (); |
5220 | ||
29b0f896 AM |
5221 | /* We are ready to output the insn. */ |
5222 | output_insn (); | |
e379e5f3 | 5223 | |
ae531041 L |
5224 | insert_lfence_after (); |
5225 | ||
e379e5f3 L |
5226 | last_insn.seg = now_seg; |
5227 | ||
5228 | if (i.tm.opcode_modifier.isprefix) | |
5229 | { | |
5230 | last_insn.kind = last_insn_prefix; | |
5231 | last_insn.name = i.tm.name; | |
5232 | last_insn.file = as_where (&last_insn.line); | |
5233 | } | |
5234 | else | |
5235 | last_insn.kind = last_insn_other; | |
29b0f896 AM |
5236 | } |
5237 | ||
5238 | static char * | |
e3bb37b5 | 5239 | parse_insn (char *line, char *mnemonic) |
29b0f896 AM |
5240 | { |
5241 | char *l = line; | |
5242 | char *token_start = l; | |
5243 | char *mnem_p; | |
5c6af06e | 5244 | int supported; |
d3ce72d0 | 5245 | const insn_template *t; |
b6169b20 | 5246 | char *dot_p = NULL; |
29b0f896 | 5247 | |
29b0f896 AM |
5248 | while (1) |
5249 | { | |
5250 | mnem_p = mnemonic; | |
5251 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
5252 | { | |
b6169b20 L |
5253 | if (*mnem_p == '.') |
5254 | dot_p = mnem_p; | |
29b0f896 AM |
5255 | mnem_p++; |
5256 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
45288df1 | 5257 | { |
29b0f896 AM |
5258 | as_bad (_("no such instruction: `%s'"), token_start); |
5259 | return NULL; | |
5260 | } | |
5261 | l++; | |
5262 | } | |
5263 | if (!is_space_char (*l) | |
5264 | && *l != END_OF_INSN | |
e44823cf JB |
5265 | && (intel_syntax |
5266 | || (*l != PREFIX_SEPARATOR | |
5267 | && *l != ','))) | |
29b0f896 AM |
5268 | { |
5269 | as_bad (_("invalid character %s in mnemonic"), | |
5270 | output_invalid (*l)); | |
5271 | return NULL; | |
5272 | } | |
5273 | if (token_start == l) | |
5274 | { | |
e44823cf | 5275 | if (!intel_syntax && *l == PREFIX_SEPARATOR) |
29b0f896 AM |
5276 | as_bad (_("expecting prefix; got nothing")); |
5277 | else | |
5278 | as_bad (_("expecting mnemonic; got nothing")); | |
5279 | return NULL; | |
5280 | } | |
45288df1 | 5281 | |
29b0f896 | 5282 | /* Look up instruction (or prefix) via hash table. */ |
629310ab | 5283 | current_templates = (const templates *) str_hash_find (op_hash, mnemonic); |
47926f60 | 5284 | |
29b0f896 AM |
5285 | if (*l != END_OF_INSN |
5286 | && (!is_space_char (*l) || l[1] != END_OF_INSN) | |
5287 | && current_templates | |
40fb9820 | 5288 | && current_templates->start->opcode_modifier.isprefix) |
29b0f896 | 5289 | { |
c6fb90c8 | 5290 | if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags)) |
2dd88dca JB |
5291 | { |
5292 | as_bad ((flag_code != CODE_64BIT | |
5293 | ? _("`%s' is only supported in 64-bit mode") | |
5294 | : _("`%s' is not supported in 64-bit mode")), | |
5295 | current_templates->start->name); | |
5296 | return NULL; | |
5297 | } | |
29b0f896 AM |
5298 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
5299 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
673fe0f0 JB |
5300 | if ((current_templates->start->opcode_modifier.size == SIZE16 |
5301 | || current_templates->start->opcode_modifier.size == SIZE32) | |
29b0f896 | 5302 | && flag_code != CODE_64BIT |
673fe0f0 | 5303 | && ((current_templates->start->opcode_modifier.size == SIZE32) |
29b0f896 AM |
5304 | ^ (flag_code == CODE_16BIT))) |
5305 | { | |
5306 | as_bad (_("redundant %s prefix"), | |
5307 | current_templates->start->name); | |
5308 | return NULL; | |
45288df1 | 5309 | } |
31184569 JB |
5310 | |
5311 | if (current_templates->start->base_opcode == PSEUDO_PREFIX) | |
29b0f896 | 5312 | { |
86fa6981 | 5313 | /* Handle pseudo prefixes. */ |
31184569 | 5314 | switch (current_templates->start->extension_opcode) |
86fa6981 | 5315 | { |
41eb8e88 | 5316 | case Prefix_Disp8: |
86fa6981 L |
5317 | /* {disp8} */ |
5318 | i.disp_encoding = disp_encoding_8bit; | |
5319 | break; | |
41eb8e88 L |
5320 | case Prefix_Disp16: |
5321 | /* {disp16} */ | |
5322 | i.disp_encoding = disp_encoding_16bit; | |
5323 | break; | |
5324 | case Prefix_Disp32: | |
86fa6981 L |
5325 | /* {disp32} */ |
5326 | i.disp_encoding = disp_encoding_32bit; | |
5327 | break; | |
41eb8e88 | 5328 | case Prefix_Load: |
86fa6981 L |
5329 | /* {load} */ |
5330 | i.dir_encoding = dir_encoding_load; | |
5331 | break; | |
41eb8e88 | 5332 | case Prefix_Store: |
86fa6981 L |
5333 | /* {store} */ |
5334 | i.dir_encoding = dir_encoding_store; | |
5335 | break; | |
41eb8e88 | 5336 | case Prefix_VEX: |
42e04b36 L |
5337 | /* {vex} */ |
5338 | i.vec_encoding = vex_encoding_vex; | |
86fa6981 | 5339 | break; |
41eb8e88 | 5340 | case Prefix_VEX3: |
86fa6981 L |
5341 | /* {vex3} */ |
5342 | i.vec_encoding = vex_encoding_vex3; | |
5343 | break; | |
41eb8e88 | 5344 | case Prefix_EVEX: |
86fa6981 L |
5345 | /* {evex} */ |
5346 | i.vec_encoding = vex_encoding_evex; | |
5347 | break; | |
41eb8e88 | 5348 | case Prefix_REX: |
6b6b6807 | 5349 | /* {rex} */ |
5b7c81bd | 5350 | i.rex_encoding = true; |
6b6b6807 | 5351 | break; |
41eb8e88 | 5352 | case Prefix_NoOptimize: |
b6f8c7c4 | 5353 | /* {nooptimize} */ |
5b7c81bd | 5354 | i.no_optimize = true; |
b6f8c7c4 | 5355 | break; |
86fa6981 L |
5356 | default: |
5357 | abort (); | |
5358 | } | |
5359 | } | |
5360 | else | |
5361 | { | |
5362 | /* Add prefix, checking for repeated prefixes. */ | |
4e9ac44a | 5363 | switch (add_prefix (current_templates->start->base_opcode)) |
86fa6981 | 5364 | { |
4e9ac44a L |
5365 | case PREFIX_EXIST: |
5366 | return NULL; | |
5367 | case PREFIX_DS: | |
d777820b | 5368 | if (current_templates->start->cpu_flags.bitfield.cpuibt) |
4e9ac44a L |
5369 | i.notrack_prefix = current_templates->start->name; |
5370 | break; | |
5371 | case PREFIX_REP: | |
5372 | if (current_templates->start->cpu_flags.bitfield.cpuhle) | |
5373 | i.hle_prefix = current_templates->start->name; | |
5374 | else if (current_templates->start->cpu_flags.bitfield.cpumpx) | |
5375 | i.bnd_prefix = current_templates->start->name; | |
5376 | else | |
5377 | i.rep_prefix = current_templates->start->name; | |
5378 | break; | |
5379 | default: | |
5380 | break; | |
86fa6981 | 5381 | } |
29b0f896 AM |
5382 | } |
5383 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
5384 | token_start = ++l; | |
5385 | } | |
5386 | else | |
5387 | break; | |
5388 | } | |
45288df1 | 5389 | |
30a55f88 | 5390 | if (!current_templates) |
b6169b20 | 5391 | { |
07d5e953 JB |
5392 | /* Deprecated functionality (new code should use pseudo-prefixes instead): |
5393 | Check if we should swap operand or force 32bit displacement in | |
f8a5c266 | 5394 | encoding. */ |
30a55f88 | 5395 | if (mnem_p - 2 == dot_p && dot_p[1] == 's') |
64c49ab3 | 5396 | i.dir_encoding = dir_encoding_swap; |
8d63c93e | 5397 | else if (mnem_p - 3 == dot_p |
a501d77e L |
5398 | && dot_p[1] == 'd' |
5399 | && dot_p[2] == '8') | |
5400 | i.disp_encoding = disp_encoding_8bit; | |
8d63c93e | 5401 | else if (mnem_p - 4 == dot_p |
f8a5c266 L |
5402 | && dot_p[1] == 'd' |
5403 | && dot_p[2] == '3' | |
5404 | && dot_p[3] == '2') | |
a501d77e | 5405 | i.disp_encoding = disp_encoding_32bit; |
30a55f88 L |
5406 | else |
5407 | goto check_suffix; | |
5408 | mnem_p = dot_p; | |
5409 | *dot_p = '\0'; | |
629310ab | 5410 | current_templates = (const templates *) str_hash_find (op_hash, mnemonic); |
b6169b20 L |
5411 | } |
5412 | ||
29b0f896 AM |
5413 | if (!current_templates) |
5414 | { | |
dc1e8a47 | 5415 | check_suffix: |
1c529385 | 5416 | if (mnem_p > mnemonic) |
29b0f896 | 5417 | { |
1c529385 LH |
5418 | /* See if we can get a match by trimming off a suffix. */ |
5419 | switch (mnem_p[-1]) | |
29b0f896 | 5420 | { |
1c529385 LH |
5421 | case WORD_MNEM_SUFFIX: |
5422 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) | |
29b0f896 AM |
5423 | i.suffix = SHORT_MNEM_SUFFIX; |
5424 | else | |
1c529385 LH |
5425 | /* Fall through. */ |
5426 | case BYTE_MNEM_SUFFIX: | |
5427 | case QWORD_MNEM_SUFFIX: | |
5428 | i.suffix = mnem_p[-1]; | |
29b0f896 | 5429 | mnem_p[-1] = '\0'; |
fe0e921f AM |
5430 | current_templates |
5431 | = (const templates *) str_hash_find (op_hash, mnemonic); | |
1c529385 LH |
5432 | break; |
5433 | case SHORT_MNEM_SUFFIX: | |
5434 | case LONG_MNEM_SUFFIX: | |
5435 | if (!intel_syntax) | |
5436 | { | |
5437 | i.suffix = mnem_p[-1]; | |
5438 | mnem_p[-1] = '\0'; | |
fe0e921f AM |
5439 | current_templates |
5440 | = (const templates *) str_hash_find (op_hash, mnemonic); | |
1c529385 LH |
5441 | } |
5442 | break; | |
5443 | ||
5444 | /* Intel Syntax. */ | |
5445 | case 'd': | |
5446 | if (intel_syntax) | |
5447 | { | |
5448 | if (intel_float_operand (mnemonic) == 1) | |
5449 | i.suffix = SHORT_MNEM_SUFFIX; | |
5450 | else | |
5451 | i.suffix = LONG_MNEM_SUFFIX; | |
5452 | mnem_p[-1] = '\0'; | |
fe0e921f AM |
5453 | current_templates |
5454 | = (const templates *) str_hash_find (op_hash, mnemonic); | |
1c529385 LH |
5455 | } |
5456 | break; | |
29b0f896 | 5457 | } |
29b0f896 | 5458 | } |
1c529385 | 5459 | |
29b0f896 AM |
5460 | if (!current_templates) |
5461 | { | |
5462 | as_bad (_("no such instruction: `%s'"), token_start); | |
5463 | return NULL; | |
5464 | } | |
5465 | } | |
252b5132 | 5466 | |
0cfa3eb3 JB |
5467 | if (current_templates->start->opcode_modifier.jump == JUMP |
5468 | || current_templates->start->opcode_modifier.jump == JUMP_BYTE) | |
29b0f896 AM |
5469 | { |
5470 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
5471 | predict taken and predict not taken respectively. | |
5472 | I'm not sure that branch hints actually do anything on loop | |
5473 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
5474 | may work in the future and it doesn't hurt to accept them | |
5475 | now. */ | |
5476 | if (l[0] == ',' && l[1] == 'p') | |
5477 | { | |
5478 | if (l[2] == 't') | |
5479 | { | |
5480 | if (!add_prefix (DS_PREFIX_OPCODE)) | |
5481 | return NULL; | |
5482 | l += 3; | |
5483 | } | |
5484 | else if (l[2] == 'n') | |
5485 | { | |
5486 | if (!add_prefix (CS_PREFIX_OPCODE)) | |
5487 | return NULL; | |
5488 | l += 3; | |
5489 | } | |
5490 | } | |
5491 | } | |
5492 | /* Any other comma loses. */ | |
5493 | if (*l == ',') | |
5494 | { | |
5495 | as_bad (_("invalid character %s in mnemonic"), | |
5496 | output_invalid (*l)); | |
5497 | return NULL; | |
5498 | } | |
252b5132 | 5499 | |
29b0f896 | 5500 | /* Check if instruction is supported on specified architecture. */ |
5c6af06e JB |
5501 | supported = 0; |
5502 | for (t = current_templates->start; t < current_templates->end; ++t) | |
5503 | { | |
c0f3af97 L |
5504 | supported |= cpu_flags_match (t); |
5505 | if (supported == CPU_FLAGS_PERFECT_MATCH) | |
548d0ee6 JB |
5506 | { |
5507 | if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT)) | |
5508 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
3629bb00 | 5509 | |
548d0ee6 JB |
5510 | return l; |
5511 | } | |
29b0f896 | 5512 | } |
3629bb00 | 5513 | |
548d0ee6 JB |
5514 | if (!(supported & CPU_FLAGS_64BIT_MATCH)) |
5515 | as_bad (flag_code == CODE_64BIT | |
5516 | ? _("`%s' is not supported in 64-bit mode") | |
5517 | : _("`%s' is only supported in 64-bit mode"), | |
5518 | current_templates->start->name); | |
5519 | else | |
5520 | as_bad (_("`%s' is not supported on `%s%s'"), | |
5521 | current_templates->start->name, | |
5522 | cpu_arch_name ? cpu_arch_name : default_arch, | |
5523 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); | |
252b5132 | 5524 | |
548d0ee6 | 5525 | return NULL; |
29b0f896 | 5526 | } |
252b5132 | 5527 | |
29b0f896 | 5528 | static char * |
e3bb37b5 | 5529 | parse_operands (char *l, const char *mnemonic) |
29b0f896 AM |
5530 | { |
5531 | char *token_start; | |
3138f287 | 5532 | |
29b0f896 AM |
5533 | /* 1 if operand is pending after ','. */ |
5534 | unsigned int expecting_operand = 0; | |
252b5132 | 5535 | |
29b0f896 AM |
5536 | /* Non-zero if operand parens not balanced. */ |
5537 | unsigned int paren_not_balanced; | |
5538 | ||
5539 | while (*l != END_OF_INSN) | |
5540 | { | |
5541 | /* Skip optional white space before operand. */ | |
5542 | if (is_space_char (*l)) | |
5543 | ++l; | |
d02603dc | 5544 | if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"') |
29b0f896 AM |
5545 | { |
5546 | as_bad (_("invalid character %s before operand %d"), | |
5547 | output_invalid (*l), | |
5548 | i.operands + 1); | |
5549 | return NULL; | |
5550 | } | |
d02603dc | 5551 | token_start = l; /* After white space. */ |
29b0f896 AM |
5552 | paren_not_balanced = 0; |
5553 | while (paren_not_balanced || *l != ',') | |
5554 | { | |
5555 | if (*l == END_OF_INSN) | |
5556 | { | |
5557 | if (paren_not_balanced) | |
5558 | { | |
5559 | if (!intel_syntax) | |
5560 | as_bad (_("unbalanced parenthesis in operand %d."), | |
5561 | i.operands + 1); | |
5562 | else | |
5563 | as_bad (_("unbalanced brackets in operand %d."), | |
5564 | i.operands + 1); | |
5565 | return NULL; | |
5566 | } | |
5567 | else | |
5568 | break; /* we are done */ | |
5569 | } | |
d02603dc | 5570 | else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"') |
29b0f896 AM |
5571 | { |
5572 | as_bad (_("invalid character %s in operand %d"), | |
5573 | output_invalid (*l), | |
5574 | i.operands + 1); | |
5575 | return NULL; | |
5576 | } | |
5577 | if (!intel_syntax) | |
5578 | { | |
5579 | if (*l == '(') | |
5580 | ++paren_not_balanced; | |
5581 | if (*l == ')') | |
5582 | --paren_not_balanced; | |
5583 | } | |
5584 | else | |
5585 | { | |
5586 | if (*l == '[') | |
5587 | ++paren_not_balanced; | |
5588 | if (*l == ']') | |
5589 | --paren_not_balanced; | |
5590 | } | |
5591 | l++; | |
5592 | } | |
5593 | if (l != token_start) | |
5594 | { /* Yes, we've read in another operand. */ | |
5595 | unsigned int operand_ok; | |
5596 | this_operand = i.operands++; | |
5597 | if (i.operands > MAX_OPERANDS) | |
5598 | { | |
5599 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
5600 | MAX_OPERANDS); | |
5601 | return NULL; | |
5602 | } | |
9d46ce34 | 5603 | i.types[this_operand].bitfield.unspecified = 1; |
29b0f896 AM |
5604 | /* Now parse operand adding info to 'i' as we go along. */ |
5605 | END_STRING_AND_SAVE (l); | |
5606 | ||
1286ab78 L |
5607 | if (i.mem_operands > 1) |
5608 | { | |
5609 | as_bad (_("too many memory references for `%s'"), | |
5610 | mnemonic); | |
5611 | return 0; | |
5612 | } | |
5613 | ||
29b0f896 AM |
5614 | if (intel_syntax) |
5615 | operand_ok = | |
5616 | i386_intel_operand (token_start, | |
5617 | intel_float_operand (mnemonic)); | |
5618 | else | |
a7619375 | 5619 | operand_ok = i386_att_operand (token_start); |
29b0f896 AM |
5620 | |
5621 | RESTORE_END_STRING (l); | |
5622 | if (!operand_ok) | |
5623 | return NULL; | |
5624 | } | |
5625 | else | |
5626 | { | |
5627 | if (expecting_operand) | |
5628 | { | |
5629 | expecting_operand_after_comma: | |
5630 | as_bad (_("expecting operand after ','; got nothing")); | |
5631 | return NULL; | |
5632 | } | |
5633 | if (*l == ',') | |
5634 | { | |
5635 | as_bad (_("expecting operand before ','; got nothing")); | |
5636 | return NULL; | |
5637 | } | |
5638 | } | |
7f3f1ea2 | 5639 | |
29b0f896 AM |
5640 | /* Now *l must be either ',' or END_OF_INSN. */ |
5641 | if (*l == ',') | |
5642 | { | |
5643 | if (*++l == END_OF_INSN) | |
5644 | { | |
5645 | /* Just skip it, if it's \n complain. */ | |
5646 | goto expecting_operand_after_comma; | |
5647 | } | |
5648 | expecting_operand = 1; | |
5649 | } | |
5650 | } | |
5651 | return l; | |
5652 | } | |
7f3f1ea2 | 5653 | |
050dfa73 | 5654 | static void |
783c187b | 5655 | swap_2_operands (unsigned int xchg1, unsigned int xchg2) |
050dfa73 MM |
5656 | { |
5657 | union i386_op temp_op; | |
40fb9820 | 5658 | i386_operand_type temp_type; |
c48dadc9 | 5659 | unsigned int temp_flags; |
050dfa73 | 5660 | enum bfd_reloc_code_real temp_reloc; |
4eed87de | 5661 | |
050dfa73 MM |
5662 | temp_type = i.types[xchg2]; |
5663 | i.types[xchg2] = i.types[xchg1]; | |
5664 | i.types[xchg1] = temp_type; | |
c48dadc9 JB |
5665 | |
5666 | temp_flags = i.flags[xchg2]; | |
5667 | i.flags[xchg2] = i.flags[xchg1]; | |
5668 | i.flags[xchg1] = temp_flags; | |
5669 | ||
050dfa73 MM |
5670 | temp_op = i.op[xchg2]; |
5671 | i.op[xchg2] = i.op[xchg1]; | |
5672 | i.op[xchg1] = temp_op; | |
c48dadc9 | 5673 | |
050dfa73 MM |
5674 | temp_reloc = i.reloc[xchg2]; |
5675 | i.reloc[xchg2] = i.reloc[xchg1]; | |
5676 | i.reloc[xchg1] = temp_reloc; | |
43234a1e | 5677 | |
6225c532 | 5678 | if (i.mask.reg) |
43234a1e | 5679 | { |
6225c532 JB |
5680 | if (i.mask.operand == xchg1) |
5681 | i.mask.operand = xchg2; | |
5682 | else if (i.mask.operand == xchg2) | |
5683 | i.mask.operand = xchg1; | |
43234a1e | 5684 | } |
5273a3cd | 5685 | if (i.broadcast.type) |
43234a1e | 5686 | { |
5273a3cd JB |
5687 | if (i.broadcast.operand == xchg1) |
5688 | i.broadcast.operand = xchg2; | |
5689 | else if (i.broadcast.operand == xchg2) | |
5690 | i.broadcast.operand = xchg1; | |
43234a1e | 5691 | } |
ca5312a2 | 5692 | if (i.rounding.type != rc_none) |
43234a1e | 5693 | { |
ca5312a2 JB |
5694 | if (i.rounding.operand == xchg1) |
5695 | i.rounding.operand = xchg2; | |
5696 | else if (i.rounding.operand == xchg2) | |
5697 | i.rounding.operand = xchg1; | |
43234a1e | 5698 | } |
050dfa73 MM |
5699 | } |
5700 | ||
29b0f896 | 5701 | static void |
e3bb37b5 | 5702 | swap_operands (void) |
29b0f896 | 5703 | { |
b7c61d9a | 5704 | switch (i.operands) |
050dfa73 | 5705 | { |
c0f3af97 | 5706 | case 5: |
b7c61d9a | 5707 | case 4: |
4d456e3d | 5708 | swap_2_operands (1, i.operands - 2); |
1a0670f3 | 5709 | /* Fall through. */ |
b7c61d9a L |
5710 | case 3: |
5711 | case 2: | |
4d456e3d | 5712 | swap_2_operands (0, i.operands - 1); |
b7c61d9a L |
5713 | break; |
5714 | default: | |
5715 | abort (); | |
29b0f896 | 5716 | } |
29b0f896 AM |
5717 | |
5718 | if (i.mem_operands == 2) | |
5719 | { | |
5e042380 | 5720 | const reg_entry *temp_seg; |
29b0f896 AM |
5721 | temp_seg = i.seg[0]; |
5722 | i.seg[0] = i.seg[1]; | |
5723 | i.seg[1] = temp_seg; | |
5724 | } | |
5725 | } | |
252b5132 | 5726 | |
29b0f896 AM |
5727 | /* Try to ensure constant immediates are represented in the smallest |
5728 | opcode possible. */ | |
5729 | static void | |
e3bb37b5 | 5730 | optimize_imm (void) |
29b0f896 AM |
5731 | { |
5732 | char guess_suffix = 0; | |
5733 | int op; | |
252b5132 | 5734 | |
29b0f896 AM |
5735 | if (i.suffix) |
5736 | guess_suffix = i.suffix; | |
5737 | else if (i.reg_operands) | |
5738 | { | |
5739 | /* Figure out a suffix from the last register operand specified. | |
75e5731b JB |
5740 | We can't do this properly yet, i.e. excluding special register |
5741 | instances, but the following works for instructions with | |
5742 | immediates. In any case, we can't set i.suffix yet. */ | |
29b0f896 | 5743 | for (op = i.operands; --op >= 0;) |
bab6aec1 JB |
5744 | if (i.types[op].bitfield.class != Reg) |
5745 | continue; | |
5746 | else if (i.types[op].bitfield.byte) | |
7ab9ffdd | 5747 | { |
40fb9820 L |
5748 | guess_suffix = BYTE_MNEM_SUFFIX; |
5749 | break; | |
5750 | } | |
bab6aec1 | 5751 | else if (i.types[op].bitfield.word) |
252b5132 | 5752 | { |
40fb9820 L |
5753 | guess_suffix = WORD_MNEM_SUFFIX; |
5754 | break; | |
5755 | } | |
bab6aec1 | 5756 | else if (i.types[op].bitfield.dword) |
40fb9820 L |
5757 | { |
5758 | guess_suffix = LONG_MNEM_SUFFIX; | |
5759 | break; | |
5760 | } | |
bab6aec1 | 5761 | else if (i.types[op].bitfield.qword) |
40fb9820 L |
5762 | { |
5763 | guess_suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 | 5764 | break; |
252b5132 | 5765 | } |
29b0f896 AM |
5766 | } |
5767 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) | |
5768 | guess_suffix = WORD_MNEM_SUFFIX; | |
5769 | ||
5770 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 5771 | if (operand_type_check (i.types[op], imm)) |
29b0f896 AM |
5772 | { |
5773 | switch (i.op[op].imms->X_op) | |
252b5132 | 5774 | { |
29b0f896 AM |
5775 | case O_constant: |
5776 | /* If a suffix is given, this operand may be shortened. */ | |
5777 | switch (guess_suffix) | |
252b5132 | 5778 | { |
29b0f896 | 5779 | case LONG_MNEM_SUFFIX: |
40fb9820 L |
5780 | i.types[op].bitfield.imm32 = 1; |
5781 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
5782 | break; |
5783 | case WORD_MNEM_SUFFIX: | |
40fb9820 L |
5784 | i.types[op].bitfield.imm16 = 1; |
5785 | i.types[op].bitfield.imm32 = 1; | |
5786 | i.types[op].bitfield.imm32s = 1; | |
5787 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
5788 | break; |
5789 | case BYTE_MNEM_SUFFIX: | |
40fb9820 L |
5790 | i.types[op].bitfield.imm8 = 1; |
5791 | i.types[op].bitfield.imm8s = 1; | |
5792 | i.types[op].bitfield.imm16 = 1; | |
5793 | i.types[op].bitfield.imm32 = 1; | |
5794 | i.types[op].bitfield.imm32s = 1; | |
5795 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 | 5796 | break; |
252b5132 | 5797 | } |
252b5132 | 5798 | |
29b0f896 AM |
5799 | /* If this operand is at most 16 bits, convert it |
5800 | to a signed 16 bit number before trying to see | |
5801 | whether it will fit in an even smaller size. | |
5802 | This allows a 16-bit operand such as $0xffe0 to | |
5803 | be recognised as within Imm8S range. */ | |
40fb9820 | 5804 | if ((i.types[op].bitfield.imm16) |
29b0f896 | 5805 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) |
252b5132 | 5806 | { |
87ed972d JB |
5807 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number |
5808 | ^ 0x8000) - 0x8000); | |
29b0f896 | 5809 | } |
a28def75 L |
5810 | #ifdef BFD64 |
5811 | /* Store 32-bit immediate in 64-bit for 64-bit BFD. */ | |
40fb9820 | 5812 | if ((i.types[op].bitfield.imm32) |
29b0f896 AM |
5813 | && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) |
5814 | == 0)) | |
5815 | { | |
5816 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number | |
5817 | ^ ((offsetT) 1 << 31)) | |
5818 | - ((offsetT) 1 << 31)); | |
5819 | } | |
a28def75 | 5820 | #endif |
40fb9820 | 5821 | i.types[op] |
c6fb90c8 L |
5822 | = operand_type_or (i.types[op], |
5823 | smallest_imm_type (i.op[op].imms->X_add_number)); | |
252b5132 | 5824 | |
29b0f896 AM |
5825 | /* We must avoid matching of Imm32 templates when 64bit |
5826 | only immediate is available. */ | |
5827 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
40fb9820 | 5828 | i.types[op].bitfield.imm32 = 0; |
29b0f896 | 5829 | break; |
252b5132 | 5830 | |
29b0f896 AM |
5831 | case O_absent: |
5832 | case O_register: | |
5833 | abort (); | |
5834 | ||
5835 | /* Symbols and expressions. */ | |
5836 | default: | |
9cd96992 JB |
5837 | /* Convert symbolic operand to proper sizes for matching, but don't |
5838 | prevent matching a set of insns that only supports sizes other | |
5839 | than those matching the insn suffix. */ | |
5840 | { | |
40fb9820 | 5841 | i386_operand_type mask, allowed; |
87ed972d | 5842 | const insn_template *t = current_templates->start; |
9cd96992 | 5843 | |
0dfbf9d7 | 5844 | operand_type_set (&mask, 0); |
87ed972d | 5845 | allowed = t->operand_types[op]; |
40fb9820 | 5846 | |
87ed972d | 5847 | while (++t < current_templates->end) |
bab6aec1 | 5848 | { |
bab6aec1 | 5849 | allowed = operand_type_and (allowed, anyimm); |
87ed972d | 5850 | allowed = operand_type_or (allowed, t->operand_types[op]); |
bab6aec1 | 5851 | } |
9cd96992 JB |
5852 | switch (guess_suffix) |
5853 | { | |
5854 | case QWORD_MNEM_SUFFIX: | |
40fb9820 L |
5855 | mask.bitfield.imm64 = 1; |
5856 | mask.bitfield.imm32s = 1; | |
9cd96992 JB |
5857 | break; |
5858 | case LONG_MNEM_SUFFIX: | |
40fb9820 | 5859 | mask.bitfield.imm32 = 1; |
9cd96992 JB |
5860 | break; |
5861 | case WORD_MNEM_SUFFIX: | |
40fb9820 | 5862 | mask.bitfield.imm16 = 1; |
9cd96992 JB |
5863 | break; |
5864 | case BYTE_MNEM_SUFFIX: | |
40fb9820 | 5865 | mask.bitfield.imm8 = 1; |
9cd96992 JB |
5866 | break; |
5867 | default: | |
9cd96992 JB |
5868 | break; |
5869 | } | |
c6fb90c8 | 5870 | allowed = operand_type_and (mask, allowed); |
0dfbf9d7 | 5871 | if (!operand_type_all_zero (&allowed)) |
c6fb90c8 | 5872 | i.types[op] = operand_type_and (i.types[op], mask); |
9cd96992 | 5873 | } |
29b0f896 | 5874 | break; |
252b5132 | 5875 | } |
29b0f896 AM |
5876 | } |
5877 | } | |
47926f60 | 5878 | |
29b0f896 AM |
5879 | /* Try to use the smallest displacement type too. */ |
5880 | static void | |
e3bb37b5 | 5881 | optimize_disp (void) |
29b0f896 AM |
5882 | { |
5883 | int op; | |
3e73aa7c | 5884 | |
29b0f896 | 5885 | for (op = i.operands; --op >= 0;) |
40fb9820 | 5886 | if (operand_type_check (i.types[op], disp)) |
252b5132 | 5887 | { |
b300c311 | 5888 | if (i.op[op].disps->X_op == O_constant) |
252b5132 | 5889 | { |
91d6fa6a | 5890 | offsetT op_disp = i.op[op].disps->X_add_number; |
29b0f896 | 5891 | |
40fb9820 | 5892 | if (i.types[op].bitfield.disp16 |
91d6fa6a | 5893 | && (op_disp & ~(offsetT) 0xffff) == 0) |
b300c311 L |
5894 | { |
5895 | /* If this operand is at most 16 bits, convert | |
5896 | to a signed 16 bit number and don't use 64bit | |
5897 | displacement. */ | |
91d6fa6a | 5898 | op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000); |
40fb9820 | 5899 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 5900 | } |
91d6fa6a | 5901 | if (!op_disp && i.types[op].bitfield.baseindex) |
b300c311 | 5902 | { |
40fb9820 L |
5903 | i.types[op].bitfield.disp8 = 0; |
5904 | i.types[op].bitfield.disp16 = 0; | |
5905 | i.types[op].bitfield.disp32 = 0; | |
5906 | i.types[op].bitfield.disp32s = 0; | |
5907 | i.types[op].bitfield.disp64 = 0; | |
b300c311 L |
5908 | i.op[op].disps = 0; |
5909 | i.disp_operands--; | |
5910 | } | |
28a167a4 | 5911 | #ifdef BFD64 |
b300c311 L |
5912 | else if (flag_code == CODE_64BIT) |
5913 | { | |
a9aabc23 | 5914 | if (want_disp32 (current_templates->start) |
28a167a4 JB |
5915 | && fits_in_unsigned_long (op_disp)) |
5916 | i.types[op].bitfield.disp32 = 1; | |
5917 | ||
5918 | /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */ | |
5919 | if (i.types[op].bitfield.disp32 | |
5920 | && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0) | |
5921 | { | |
5922 | /* If this operand is at most 32 bits, convert | |
5923 | to a signed 32 bit number and don't use 64bit | |
5924 | displacement. */ | |
5925 | op_disp &= (((offsetT) 2 << 31) - 1); | |
5926 | op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
5927 | i.types[op].bitfield.disp64 = 0; | |
5928 | } | |
5929 | ||
91d6fa6a | 5930 | if (fits_in_signed_long (op_disp)) |
28a9d8f5 | 5931 | { |
40fb9820 L |
5932 | i.types[op].bitfield.disp64 = 0; |
5933 | i.types[op].bitfield.disp32s = 1; | |
28a9d8f5 | 5934 | } |
b300c311 | 5935 | } |
28a167a4 | 5936 | #endif |
40fb9820 L |
5937 | if ((i.types[op].bitfield.disp32 |
5938 | || i.types[op].bitfield.disp32s | |
5939 | || i.types[op].bitfield.disp16) | |
b5014f7a | 5940 | && fits_in_disp8 (op_disp)) |
40fb9820 | 5941 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 5942 | } |
67a4f2b7 AO |
5943 | else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
5944 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) | |
5945 | { | |
5946 | fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, | |
5947 | i.op[op].disps, 0, i.reloc[op]); | |
40fb9820 L |
5948 | i.types[op].bitfield.disp8 = 0; |
5949 | i.types[op].bitfield.disp16 = 0; | |
5950 | i.types[op].bitfield.disp32 = 0; | |
5951 | i.types[op].bitfield.disp32s = 0; | |
5952 | i.types[op].bitfield.disp64 = 0; | |
67a4f2b7 AO |
5953 | } |
5954 | else | |
b300c311 | 5955 | /* We only support 64bit displacement on constants. */ |
40fb9820 | 5956 | i.types[op].bitfield.disp64 = 0; |
252b5132 | 5957 | } |
29b0f896 AM |
5958 | } |
5959 | ||
4a1b91ea L |
5960 | /* Return 1 if there is a match in broadcast bytes between operand |
5961 | GIVEN and instruction template T. */ | |
5962 | ||
5963 | static INLINE int | |
5964 | match_broadcast_size (const insn_template *t, unsigned int given) | |
5965 | { | |
5966 | return ((t->opcode_modifier.broadcast == BYTE_BROADCAST | |
5967 | && i.types[given].bitfield.byte) | |
5968 | || (t->opcode_modifier.broadcast == WORD_BROADCAST | |
5969 | && i.types[given].bitfield.word) | |
5970 | || (t->opcode_modifier.broadcast == DWORD_BROADCAST | |
5971 | && i.types[given].bitfield.dword) | |
5972 | || (t->opcode_modifier.broadcast == QWORD_BROADCAST | |
5973 | && i.types[given].bitfield.qword)); | |
5974 | } | |
5975 | ||
6c30d220 L |
5976 | /* Check if operands are valid for the instruction. */ |
5977 | ||
5978 | static int | |
5979 | check_VecOperands (const insn_template *t) | |
5980 | { | |
43234a1e | 5981 | unsigned int op; |
e2195274 | 5982 | i386_cpu_flags cpu; |
e2195274 JB |
5983 | |
5984 | /* Templates allowing for ZMMword as well as YMMword and/or XMMword for | |
5985 | any one operand are implicity requiring AVX512VL support if the actual | |
5986 | operand size is YMMword or XMMword. Since this function runs after | |
5987 | template matching, there's no need to check for YMMword/XMMword in | |
5988 | the template. */ | |
5989 | cpu = cpu_flags_and (t->cpu_flags, avx512); | |
5990 | if (!cpu_flags_all_zero (&cpu) | |
5991 | && !t->cpu_flags.bitfield.cpuavx512vl | |
5992 | && !cpu_arch_flags.bitfield.cpuavx512vl) | |
5993 | { | |
5994 | for (op = 0; op < t->operands; ++op) | |
5995 | { | |
5996 | if (t->operand_types[op].bitfield.zmmword | |
5997 | && (i.types[op].bitfield.ymmword | |
5998 | || i.types[op].bitfield.xmmword)) | |
5999 | { | |
6000 | i.error = unsupported; | |
6001 | return 1; | |
6002 | } | |
6003 | } | |
6004 | } | |
43234a1e | 6005 | |
6c30d220 | 6006 | /* Without VSIB byte, we can't have a vector register for index. */ |
63112cd6 | 6007 | if (!t->opcode_modifier.sib |
6c30d220 | 6008 | && i.index_reg |
1b54b8d7 JB |
6009 | && (i.index_reg->reg_type.bitfield.xmmword |
6010 | || i.index_reg->reg_type.bitfield.ymmword | |
6011 | || i.index_reg->reg_type.bitfield.zmmword)) | |
6c30d220 L |
6012 | { |
6013 | i.error = unsupported_vector_index_register; | |
6014 | return 1; | |
6015 | } | |
6016 | ||
ad8ecc81 MZ |
6017 | /* Check if default mask is allowed. */ |
6018 | if (t->opcode_modifier.nodefmask | |
6225c532 | 6019 | && (!i.mask.reg || i.mask.reg->reg_num == 0)) |
ad8ecc81 MZ |
6020 | { |
6021 | i.error = no_default_mask; | |
6022 | return 1; | |
6023 | } | |
6024 | ||
7bab8ab5 JB |
6025 | /* For VSIB byte, we need a vector register for index, and all vector |
6026 | registers must be distinct. */ | |
260cd341 | 6027 | if (t->opcode_modifier.sib && t->opcode_modifier.sib != SIBMEM) |
7bab8ab5 JB |
6028 | { |
6029 | if (!i.index_reg | |
63112cd6 | 6030 | || !((t->opcode_modifier.sib == VECSIB128 |
1b54b8d7 | 6031 | && i.index_reg->reg_type.bitfield.xmmword) |
63112cd6 | 6032 | || (t->opcode_modifier.sib == VECSIB256 |
1b54b8d7 | 6033 | && i.index_reg->reg_type.bitfield.ymmword) |
63112cd6 | 6034 | || (t->opcode_modifier.sib == VECSIB512 |
1b54b8d7 | 6035 | && i.index_reg->reg_type.bitfield.zmmword))) |
7bab8ab5 JB |
6036 | { |
6037 | i.error = invalid_vsib_address; | |
6038 | return 1; | |
6039 | } | |
6040 | ||
6225c532 JB |
6041 | gas_assert (i.reg_operands == 2 || i.mask.reg); |
6042 | if (i.reg_operands == 2 && !i.mask.reg) | |
43234a1e | 6043 | { |
3528c362 | 6044 | gas_assert (i.types[0].bitfield.class == RegSIMD); |
1b54b8d7 JB |
6045 | gas_assert (i.types[0].bitfield.xmmword |
6046 | || i.types[0].bitfield.ymmword); | |
3528c362 | 6047 | gas_assert (i.types[2].bitfield.class == RegSIMD); |
1b54b8d7 JB |
6048 | gas_assert (i.types[2].bitfield.xmmword |
6049 | || i.types[2].bitfield.ymmword); | |
43234a1e L |
6050 | if (operand_check == check_none) |
6051 | return 0; | |
6052 | if (register_number (i.op[0].regs) | |
6053 | != register_number (i.index_reg) | |
6054 | && register_number (i.op[2].regs) | |
6055 | != register_number (i.index_reg) | |
6056 | && register_number (i.op[0].regs) | |
6057 | != register_number (i.op[2].regs)) | |
6058 | return 0; | |
6059 | if (operand_check == check_error) | |
6060 | { | |
6061 | i.error = invalid_vector_register_set; | |
6062 | return 1; | |
6063 | } | |
6064 | as_warn (_("mask, index, and destination registers should be distinct")); | |
6065 | } | |
6225c532 | 6066 | else if (i.reg_operands == 1 && i.mask.reg) |
8444f82a | 6067 | { |
3528c362 | 6068 | if (i.types[1].bitfield.class == RegSIMD |
1b54b8d7 JB |
6069 | && (i.types[1].bitfield.xmmword |
6070 | || i.types[1].bitfield.ymmword | |
6071 | || i.types[1].bitfield.zmmword) | |
8444f82a MZ |
6072 | && (register_number (i.op[1].regs) |
6073 | == register_number (i.index_reg))) | |
6074 | { | |
6075 | if (operand_check == check_error) | |
6076 | { | |
6077 | i.error = invalid_vector_register_set; | |
6078 | return 1; | |
6079 | } | |
6080 | if (operand_check != check_none) | |
6081 | as_warn (_("index and destination registers should be distinct")); | |
6082 | } | |
6083 | } | |
43234a1e | 6084 | } |
7bab8ab5 | 6085 | |
260cd341 LC |
6086 | /* For AMX instructions with three tmmword operands, all tmmword operand must be |
6087 | distinct */ | |
6088 | if (t->operand_types[0].bitfield.tmmword | |
6089 | && i.reg_operands == 3) | |
6090 | { | |
6091 | if (register_number (i.op[0].regs) | |
6092 | == register_number (i.op[1].regs) | |
6093 | || register_number (i.op[0].regs) | |
6094 | == register_number (i.op[2].regs) | |
6095 | || register_number (i.op[1].regs) | |
6096 | == register_number (i.op[2].regs)) | |
6097 | { | |
6098 | i.error = invalid_tmm_register_set; | |
6099 | return 1; | |
6100 | } | |
6101 | } | |
6102 | ||
43234a1e L |
6103 | /* Check if broadcast is supported by the instruction and is applied |
6104 | to the memory operand. */ | |
5273a3cd | 6105 | if (i.broadcast.type) |
43234a1e | 6106 | { |
8e6e0792 | 6107 | i386_operand_type type, overlap; |
43234a1e L |
6108 | |
6109 | /* Check if specified broadcast is supported in this instruction, | |
4a1b91ea | 6110 | and its broadcast bytes match the memory operand. */ |
5273a3cd | 6111 | op = i.broadcast.operand; |
8e6e0792 | 6112 | if (!t->opcode_modifier.broadcast |
c48dadc9 | 6113 | || !(i.flags[op] & Operand_Mem) |
c39e5b26 | 6114 | || (!i.types[op].bitfield.unspecified |
4a1b91ea | 6115 | && !match_broadcast_size (t, op))) |
43234a1e L |
6116 | { |
6117 | bad_broadcast: | |
6118 | i.error = unsupported_broadcast; | |
6119 | return 1; | |
6120 | } | |
8e6e0792 | 6121 | |
5273a3cd JB |
6122 | i.broadcast.bytes = ((1 << (t->opcode_modifier.broadcast - 1)) |
6123 | * i.broadcast.type); | |
8e6e0792 | 6124 | operand_type_set (&type, 0); |
5273a3cd | 6125 | switch (i.broadcast.bytes) |
8e6e0792 | 6126 | { |
4a1b91ea L |
6127 | case 2: |
6128 | type.bitfield.word = 1; | |
6129 | break; | |
6130 | case 4: | |
6131 | type.bitfield.dword = 1; | |
6132 | break; | |
8e6e0792 JB |
6133 | case 8: |
6134 | type.bitfield.qword = 1; | |
6135 | break; | |
6136 | case 16: | |
6137 | type.bitfield.xmmword = 1; | |
6138 | break; | |
6139 | case 32: | |
6140 | type.bitfield.ymmword = 1; | |
6141 | break; | |
6142 | case 64: | |
6143 | type.bitfield.zmmword = 1; | |
6144 | break; | |
6145 | default: | |
6146 | goto bad_broadcast; | |
6147 | } | |
6148 | ||
6149 | overlap = operand_type_and (type, t->operand_types[op]); | |
bc49bfd8 JB |
6150 | if (t->operand_types[op].bitfield.class == RegSIMD |
6151 | && t->operand_types[op].bitfield.byte | |
6152 | + t->operand_types[op].bitfield.word | |
6153 | + t->operand_types[op].bitfield.dword | |
6154 | + t->operand_types[op].bitfield.qword > 1) | |
6155 | { | |
6156 | overlap.bitfield.xmmword = 0; | |
6157 | overlap.bitfield.ymmword = 0; | |
6158 | overlap.bitfield.zmmword = 0; | |
6159 | } | |
8e6e0792 JB |
6160 | if (operand_type_all_zero (&overlap)) |
6161 | goto bad_broadcast; | |
6162 | ||
6163 | if (t->opcode_modifier.checkregsize) | |
6164 | { | |
6165 | unsigned int j; | |
6166 | ||
e2195274 | 6167 | type.bitfield.baseindex = 1; |
8e6e0792 JB |
6168 | for (j = 0; j < i.operands; ++j) |
6169 | { | |
6170 | if (j != op | |
6171 | && !operand_type_register_match(i.types[j], | |
6172 | t->operand_types[j], | |
6173 | type, | |
6174 | t->operand_types[op])) | |
6175 | goto bad_broadcast; | |
6176 | } | |
6177 | } | |
43234a1e L |
6178 | } |
6179 | /* If broadcast is supported in this instruction, we need to check if | |
6180 | operand of one-element size isn't specified without broadcast. */ | |
6181 | else if (t->opcode_modifier.broadcast && i.mem_operands) | |
6182 | { | |
6183 | /* Find memory operand. */ | |
6184 | for (op = 0; op < i.operands; op++) | |
8dc0818e | 6185 | if (i.flags[op] & Operand_Mem) |
43234a1e L |
6186 | break; |
6187 | gas_assert (op < i.operands); | |
6188 | /* Check size of the memory operand. */ | |
4a1b91ea | 6189 | if (match_broadcast_size (t, op)) |
43234a1e L |
6190 | { |
6191 | i.error = broadcast_needed; | |
6192 | return 1; | |
6193 | } | |
6194 | } | |
c39e5b26 JB |
6195 | else |
6196 | op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */ | |
43234a1e L |
6197 | |
6198 | /* Check if requested masking is supported. */ | |
6225c532 | 6199 | if (i.mask.reg) |
43234a1e | 6200 | { |
ae2387fe JB |
6201 | switch (t->opcode_modifier.masking) |
6202 | { | |
6203 | case BOTH_MASKING: | |
6204 | break; | |
6205 | case MERGING_MASKING: | |
6225c532 | 6206 | if (i.mask.zeroing) |
ae2387fe JB |
6207 | { |
6208 | case 0: | |
6209 | i.error = unsupported_masking; | |
6210 | return 1; | |
6211 | } | |
6212 | break; | |
6213 | case DYNAMIC_MASKING: | |
6214 | /* Memory destinations allow only merging masking. */ | |
6225c532 | 6215 | if (i.mask.zeroing && i.mem_operands) |
ae2387fe JB |
6216 | { |
6217 | /* Find memory operand. */ | |
6218 | for (op = 0; op < i.operands; op++) | |
c48dadc9 | 6219 | if (i.flags[op] & Operand_Mem) |
ae2387fe JB |
6220 | break; |
6221 | gas_assert (op < i.operands); | |
6222 | if (op == i.operands - 1) | |
6223 | { | |
6224 | i.error = unsupported_masking; | |
6225 | return 1; | |
6226 | } | |
6227 | } | |
6228 | break; | |
6229 | default: | |
6230 | abort (); | |
6231 | } | |
43234a1e L |
6232 | } |
6233 | ||
6234 | /* Check if masking is applied to dest operand. */ | |
6225c532 | 6235 | if (i.mask.reg && (i.mask.operand != i.operands - 1)) |
43234a1e L |
6236 | { |
6237 | i.error = mask_not_on_destination; | |
6238 | return 1; | |
6239 | } | |
6240 | ||
43234a1e | 6241 | /* Check RC/SAE. */ |
ca5312a2 | 6242 | if (i.rounding.type != rc_none) |
43234a1e | 6243 | { |
a80195f1 | 6244 | if (!t->opcode_modifier.sae |
ca5312a2 | 6245 | || (i.rounding.type != saeonly && !t->opcode_modifier.staticrounding)) |
43234a1e L |
6246 | { |
6247 | i.error = unsupported_rc_sae; | |
6248 | return 1; | |
6249 | } | |
6250 | /* If the instruction has several immediate operands and one of | |
6251 | them is rounding, the rounding operand should be the last | |
6252 | immediate operand. */ | |
6253 | if (i.imm_operands > 1 | |
ca5312a2 | 6254 | && i.rounding.operand != i.imm_operands - 1) |
7bab8ab5 | 6255 | { |
43234a1e | 6256 | i.error = rc_sae_operand_not_last_imm; |
7bab8ab5 JB |
6257 | return 1; |
6258 | } | |
6c30d220 L |
6259 | } |
6260 | ||
da4977e0 JB |
6261 | /* Check the special Imm4 cases; must be the first operand. */ |
6262 | if (t->cpu_flags.bitfield.cpuxop && t->operands == 5) | |
6263 | { | |
6264 | if (i.op[0].imms->X_op != O_constant | |
6265 | || !fits_in_imm4 (i.op[0].imms->X_add_number)) | |
6266 | { | |
6267 | i.error = bad_imm4; | |
6268 | return 1; | |
6269 | } | |
6270 | ||
6271 | /* Turn off Imm<N> so that update_imm won't complain. */ | |
6272 | operand_type_set (&i.types[0], 0); | |
6273 | } | |
6274 | ||
43234a1e | 6275 | /* Check vector Disp8 operand. */ |
b5014f7a JB |
6276 | if (t->opcode_modifier.disp8memshift |
6277 | && i.disp_encoding != disp_encoding_32bit) | |
43234a1e | 6278 | { |
5273a3cd | 6279 | if (i.broadcast.type) |
4a1b91ea | 6280 | i.memshift = t->opcode_modifier.broadcast - 1; |
7091c612 | 6281 | else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL) |
43234a1e | 6282 | i.memshift = t->opcode_modifier.disp8memshift; |
7091c612 JB |
6283 | else |
6284 | { | |
6285 | const i386_operand_type *type = NULL; | |
6286 | ||
6287 | i.memshift = 0; | |
6288 | for (op = 0; op < i.operands; op++) | |
8dc0818e | 6289 | if (i.flags[op] & Operand_Mem) |
7091c612 | 6290 | { |
4174bfff JB |
6291 | if (t->opcode_modifier.evex == EVEXLIG) |
6292 | i.memshift = 2 + (i.suffix == QWORD_MNEM_SUFFIX); | |
6293 | else if (t->operand_types[op].bitfield.xmmword | |
6294 | + t->operand_types[op].bitfield.ymmword | |
6295 | + t->operand_types[op].bitfield.zmmword <= 1) | |
7091c612 JB |
6296 | type = &t->operand_types[op]; |
6297 | else if (!i.types[op].bitfield.unspecified) | |
6298 | type = &i.types[op]; | |
6299 | } | |
3528c362 | 6300 | else if (i.types[op].bitfield.class == RegSIMD |
4174bfff | 6301 | && t->opcode_modifier.evex != EVEXLIG) |
7091c612 JB |
6302 | { |
6303 | if (i.types[op].bitfield.zmmword) | |
6304 | i.memshift = 6; | |
6305 | else if (i.types[op].bitfield.ymmword && i.memshift < 5) | |
6306 | i.memshift = 5; | |
6307 | else if (i.types[op].bitfield.xmmword && i.memshift < 4) | |
6308 | i.memshift = 4; | |
6309 | } | |
6310 | ||
6311 | if (type) | |
6312 | { | |
6313 | if (type->bitfield.zmmword) | |
6314 | i.memshift = 6; | |
6315 | else if (type->bitfield.ymmword) | |
6316 | i.memshift = 5; | |
6317 | else if (type->bitfield.xmmword) | |
6318 | i.memshift = 4; | |
6319 | } | |
6320 | ||
6321 | /* For the check in fits_in_disp8(). */ | |
6322 | if (i.memshift == 0) | |
6323 | i.memshift = -1; | |
6324 | } | |
43234a1e L |
6325 | |
6326 | for (op = 0; op < i.operands; op++) | |
6327 | if (operand_type_check (i.types[op], disp) | |
6328 | && i.op[op].disps->X_op == O_constant) | |
6329 | { | |
b5014f7a | 6330 | if (fits_in_disp8 (i.op[op].disps->X_add_number)) |
43234a1e | 6331 | { |
b5014f7a JB |
6332 | i.types[op].bitfield.disp8 = 1; |
6333 | return 0; | |
43234a1e | 6334 | } |
b5014f7a | 6335 | i.types[op].bitfield.disp8 = 0; |
43234a1e L |
6336 | } |
6337 | } | |
b5014f7a JB |
6338 | |
6339 | i.memshift = 0; | |
43234a1e | 6340 | |
6c30d220 L |
6341 | return 0; |
6342 | } | |
6343 | ||
da4977e0 | 6344 | /* Check if encoding requirements are met by the instruction. */ |
a683cc34 SP |
6345 | |
6346 | static int | |
da4977e0 | 6347 | VEX_check_encoding (const insn_template *t) |
a683cc34 | 6348 | { |
da4977e0 JB |
6349 | if (i.vec_encoding == vex_encoding_error) |
6350 | { | |
6351 | i.error = unsupported; | |
6352 | return 1; | |
6353 | } | |
6354 | ||
86fa6981 | 6355 | if (i.vec_encoding == vex_encoding_evex) |
43234a1e | 6356 | { |
86fa6981 | 6357 | /* This instruction must be encoded with EVEX prefix. */ |
e771e7c9 | 6358 | if (!is_evex_encoding (t)) |
86fa6981 L |
6359 | { |
6360 | i.error = unsupported; | |
6361 | return 1; | |
6362 | } | |
6363 | return 0; | |
43234a1e L |
6364 | } |
6365 | ||
a683cc34 | 6366 | if (!t->opcode_modifier.vex) |
86fa6981 L |
6367 | { |
6368 | /* This instruction template doesn't have VEX prefix. */ | |
6369 | if (i.vec_encoding != vex_encoding_default) | |
6370 | { | |
6371 | i.error = unsupported; | |
6372 | return 1; | |
6373 | } | |
6374 | return 0; | |
6375 | } | |
a683cc34 | 6376 | |
a683cc34 SP |
6377 | return 0; |
6378 | } | |
6379 | ||
d3ce72d0 | 6380 | static const insn_template * |
83b16ac6 | 6381 | match_template (char mnem_suffix) |
29b0f896 AM |
6382 | { |
6383 | /* Points to template once we've found it. */ | |
d3ce72d0 | 6384 | const insn_template *t; |
40fb9820 | 6385 | i386_operand_type overlap0, overlap1, overlap2, overlap3; |
c0f3af97 | 6386 | i386_operand_type overlap4; |
29b0f896 | 6387 | unsigned int found_reverse_match; |
dc2be329 | 6388 | i386_opcode_modifier suffix_check; |
40fb9820 | 6389 | i386_operand_type operand_types [MAX_OPERANDS]; |
539e75ad | 6390 | int addr_prefix_disp; |
45a4bb20 | 6391 | unsigned int j, size_match, check_register; |
5614d22c | 6392 | enum i386_error specific_error = 0; |
29b0f896 | 6393 | |
c0f3af97 L |
6394 | #if MAX_OPERANDS != 5 |
6395 | # error "MAX_OPERANDS must be 5." | |
f48ff2ae L |
6396 | #endif |
6397 | ||
29b0f896 | 6398 | found_reverse_match = 0; |
539e75ad | 6399 | addr_prefix_disp = -1; |
40fb9820 | 6400 | |
dc2be329 | 6401 | /* Prepare for mnemonic suffix check. */ |
40fb9820 | 6402 | memset (&suffix_check, 0, sizeof (suffix_check)); |
dc2be329 L |
6403 | switch (mnem_suffix) |
6404 | { | |
6405 | case BYTE_MNEM_SUFFIX: | |
6406 | suffix_check.no_bsuf = 1; | |
6407 | break; | |
6408 | case WORD_MNEM_SUFFIX: | |
6409 | suffix_check.no_wsuf = 1; | |
6410 | break; | |
6411 | case SHORT_MNEM_SUFFIX: | |
6412 | suffix_check.no_ssuf = 1; | |
6413 | break; | |
6414 | case LONG_MNEM_SUFFIX: | |
6415 | suffix_check.no_lsuf = 1; | |
6416 | break; | |
6417 | case QWORD_MNEM_SUFFIX: | |
6418 | suffix_check.no_qsuf = 1; | |
6419 | break; | |
6420 | default: | |
6421 | /* NB: In Intel syntax, normally we can check for memory operand | |
6422 | size when there is no mnemonic suffix. But jmp and call have | |
6423 | 2 different encodings with Dword memory operand size, one with | |
6424 | No_ldSuf and the other without. i.suffix is set to | |
6425 | LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */ | |
6426 | if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX) | |
6427 | suffix_check.no_ldsuf = 1; | |
83b16ac6 JB |
6428 | } |
6429 | ||
01559ecc L |
6430 | /* Must have right number of operands. */ |
6431 | i.error = number_of_operands_mismatch; | |
6432 | ||
45aa61fe | 6433 | for (t = current_templates->start; t < current_templates->end; t++) |
29b0f896 | 6434 | { |
539e75ad | 6435 | addr_prefix_disp = -1; |
dbbc8b7e | 6436 | found_reverse_match = 0; |
539e75ad | 6437 | |
29b0f896 AM |
6438 | if (i.operands != t->operands) |
6439 | continue; | |
6440 | ||
50aecf8c | 6441 | /* Check processor support. */ |
a65babc9 | 6442 | i.error = unsupported; |
45a4bb20 | 6443 | if (cpu_flags_match (t) != CPU_FLAGS_PERFECT_MATCH) |
50aecf8c L |
6444 | continue; |
6445 | ||
57392598 CL |
6446 | /* Check Pseudo Prefix. */ |
6447 | i.error = unsupported; | |
6448 | if (t->opcode_modifier.pseudovexprefix | |
6449 | && !(i.vec_encoding == vex_encoding_vex | |
6450 | || i.vec_encoding == vex_encoding_vex3)) | |
6451 | continue; | |
6452 | ||
e1d4d893 | 6453 | /* Check AT&T mnemonic. */ |
a65babc9 | 6454 | i.error = unsupported_with_intel_mnemonic; |
e1d4d893 | 6455 | if (intel_mnemonic && t->opcode_modifier.attmnemonic) |
1efbbeb4 L |
6456 | continue; |
6457 | ||
4b5aaf5f | 6458 | /* Check AT&T/Intel syntax. */ |
a65babc9 | 6459 | i.error = unsupported_syntax; |
5c07affc | 6460 | if ((intel_syntax && t->opcode_modifier.attsyntax) |
4b5aaf5f | 6461 | || (!intel_syntax && t->opcode_modifier.intelsyntax)) |
1efbbeb4 L |
6462 | continue; |
6463 | ||
4b5aaf5f L |
6464 | /* Check Intel64/AMD64 ISA. */ |
6465 | switch (isa64) | |
6466 | { | |
6467 | default: | |
6468 | /* Default: Don't accept Intel64. */ | |
6469 | if (t->opcode_modifier.isa64 == INTEL64) | |
6470 | continue; | |
6471 | break; | |
6472 | case amd64: | |
6473 | /* -mamd64: Don't accept Intel64 and Intel64 only. */ | |
6474 | if (t->opcode_modifier.isa64 >= INTEL64) | |
6475 | continue; | |
6476 | break; | |
6477 | case intel64: | |
6478 | /* -mintel64: Don't accept AMD64. */ | |
5990e377 | 6479 | if (t->opcode_modifier.isa64 == AMD64 && flag_code == CODE_64BIT) |
4b5aaf5f L |
6480 | continue; |
6481 | break; | |
6482 | } | |
6483 | ||
dc2be329 | 6484 | /* Check the suffix. */ |
a65babc9 | 6485 | i.error = invalid_instruction_suffix; |
dc2be329 L |
6486 | if ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf) |
6487 | || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf) | |
6488 | || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf) | |
6489 | || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf) | |
6490 | || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf) | |
6491 | || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)) | |
83b16ac6 | 6492 | continue; |
29b0f896 | 6493 | |
3ac21baa JB |
6494 | size_match = operand_size_match (t); |
6495 | if (!size_match) | |
7d5e4556 | 6496 | continue; |
539e75ad | 6497 | |
6f2f06be JB |
6498 | /* This is intentionally not |
6499 | ||
0cfa3eb3 | 6500 | if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE)) |
6f2f06be JB |
6501 | |
6502 | as the case of a missing * on the operand is accepted (perhaps with | |
6503 | a warning, issued further down). */ | |
0cfa3eb3 | 6504 | if (i.jumpabsolute && t->opcode_modifier.jump != JUMP_ABSOLUTE) |
6f2f06be JB |
6505 | { |
6506 | i.error = operand_type_mismatch; | |
6507 | continue; | |
6508 | } | |
6509 | ||
5c07affc L |
6510 | for (j = 0; j < MAX_OPERANDS; j++) |
6511 | operand_types[j] = t->operand_types[j]; | |
6512 | ||
e365e234 JB |
6513 | /* In general, don't allow |
6514 | - 64-bit operands outside of 64-bit mode, | |
6515 | - 32-bit operands on pre-386. */ | |
4873e243 | 6516 | j = i.imm_operands + (t->operands > i.imm_operands + 1); |
e365e234 JB |
6517 | if (((i.suffix == QWORD_MNEM_SUFFIX |
6518 | && flag_code != CODE_64BIT | |
389d00a5 JB |
6519 | && !(t->opcode_modifier.opcodespace == SPACE_0F |
6520 | && t->base_opcode == 0xc7 | |
5e74b495 | 6521 | && t->opcode_modifier.opcodeprefix == PREFIX_NONE |
8b65b895 | 6522 | && t->extension_opcode == 1) /* cmpxchg8b */) |
e365e234 JB |
6523 | || (i.suffix == LONG_MNEM_SUFFIX |
6524 | && !cpu_arch_flags.bitfield.cpui386)) | |
45aa61fe | 6525 | && (intel_syntax |
3cd7f3e3 | 6526 | ? (t->opcode_modifier.mnemonicsize != IGNORESIZE |
45aa61fe AM |
6527 | && !intel_float_operand (t->name)) |
6528 | : intel_float_operand (t->name) != 2) | |
4873e243 JB |
6529 | && (t->operands == i.imm_operands |
6530 | || (operand_types[i.imm_operands].bitfield.class != RegMMX | |
6531 | && operand_types[i.imm_operands].bitfield.class != RegSIMD | |
6532 | && operand_types[i.imm_operands].bitfield.class != RegMask) | |
6533 | || (operand_types[j].bitfield.class != RegMMX | |
6534 | && operand_types[j].bitfield.class != RegSIMD | |
6535 | && operand_types[j].bitfield.class != RegMask)) | |
63112cd6 | 6536 | && !t->opcode_modifier.sib) |
192dc9c6 JB |
6537 | continue; |
6538 | ||
29b0f896 | 6539 | /* Do not verify operands when there are none. */ |
e365e234 | 6540 | if (!t->operands) |
da4977e0 JB |
6541 | { |
6542 | if (VEX_check_encoding (t)) | |
6543 | { | |
6544 | specific_error = i.error; | |
6545 | continue; | |
6546 | } | |
6547 | ||
6548 | /* We've found a match; break out of loop. */ | |
6549 | break; | |
6550 | } | |
252b5132 | 6551 | |
48bcea9f JB |
6552 | if (!t->opcode_modifier.jump |
6553 | || t->opcode_modifier.jump == JUMP_ABSOLUTE) | |
6554 | { | |
6555 | /* There should be only one Disp operand. */ | |
6556 | for (j = 0; j < MAX_OPERANDS; j++) | |
6557 | if (operand_type_check (operand_types[j], disp)) | |
539e75ad | 6558 | break; |
48bcea9f JB |
6559 | if (j < MAX_OPERANDS) |
6560 | { | |
5b7c81bd | 6561 | bool override = (i.prefix[ADDR_PREFIX] != 0); |
48bcea9f JB |
6562 | |
6563 | addr_prefix_disp = j; | |
6564 | ||
6565 | /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16 | |
6566 | operand into Disp32/Disp32/Disp16/Disp32 operand. */ | |
6567 | switch (flag_code) | |
40fb9820 | 6568 | { |
48bcea9f JB |
6569 | case CODE_16BIT: |
6570 | override = !override; | |
6571 | /* Fall through. */ | |
6572 | case CODE_32BIT: | |
6573 | if (operand_types[j].bitfield.disp32 | |
6574 | && operand_types[j].bitfield.disp16) | |
40fb9820 | 6575 | { |
48bcea9f JB |
6576 | operand_types[j].bitfield.disp16 = override; |
6577 | operand_types[j].bitfield.disp32 = !override; | |
40fb9820 | 6578 | } |
48bcea9f JB |
6579 | operand_types[j].bitfield.disp32s = 0; |
6580 | operand_types[j].bitfield.disp64 = 0; | |
6581 | break; | |
6582 | ||
6583 | case CODE_64BIT: | |
6584 | if (operand_types[j].bitfield.disp32s | |
6585 | || operand_types[j].bitfield.disp64) | |
40fb9820 | 6586 | { |
48bcea9f JB |
6587 | operand_types[j].bitfield.disp64 &= !override; |
6588 | operand_types[j].bitfield.disp32s &= !override; | |
6589 | operand_types[j].bitfield.disp32 = override; | |
40fb9820 | 6590 | } |
48bcea9f JB |
6591 | operand_types[j].bitfield.disp16 = 0; |
6592 | break; | |
40fb9820 | 6593 | } |
539e75ad | 6594 | } |
48bcea9f | 6595 | } |
539e75ad | 6596 | |
02a86693 | 6597 | /* Force 0x8b encoding for "mov foo@GOT, %eax". */ |
35648716 JB |
6598 | if (i.reloc[0] == BFD_RELOC_386_GOT32 |
6599 | && t->base_opcode == 0xa0 | |
6600 | && t->opcode_modifier.opcodespace == SPACE_BASE) | |
02a86693 L |
6601 | continue; |
6602 | ||
56ffb741 | 6603 | /* We check register size if needed. */ |
e2195274 JB |
6604 | if (t->opcode_modifier.checkregsize) |
6605 | { | |
6606 | check_register = (1 << t->operands) - 1; | |
5273a3cd JB |
6607 | if (i.broadcast.type) |
6608 | check_register &= ~(1 << i.broadcast.operand); | |
e2195274 JB |
6609 | } |
6610 | else | |
6611 | check_register = 0; | |
6612 | ||
c6fb90c8 | 6613 | overlap0 = operand_type_and (i.types[0], operand_types[0]); |
29b0f896 AM |
6614 | switch (t->operands) |
6615 | { | |
6616 | case 1: | |
40fb9820 | 6617 | if (!operand_type_match (overlap0, i.types[0])) |
29b0f896 AM |
6618 | continue; |
6619 | break; | |
6620 | case 2: | |
33eaf5de | 6621 | /* xchg %eax, %eax is a special case. It is an alias for nop |
8b38ad71 L |
6622 | only in 32bit mode and we can use opcode 0x90. In 64bit |
6623 | mode, we can't use 0x90 for xchg %eax, %eax since it should | |
6624 | zero-extend %eax to %rax. */ | |
6625 | if (flag_code == CODE_64BIT | |
6626 | && t->base_opcode == 0x90 | |
35648716 | 6627 | && t->opcode_modifier.opcodespace == SPACE_BASE |
75e5731b JB |
6628 | && i.types[0].bitfield.instance == Accum |
6629 | && i.types[0].bitfield.dword | |
6630 | && i.types[1].bitfield.instance == Accum | |
6631 | && i.types[1].bitfield.dword) | |
8b38ad71 | 6632 | continue; |
1212781b JB |
6633 | /* xrelease mov %eax, <disp> is another special case. It must not |
6634 | match the accumulator-only encoding of mov. */ | |
6635 | if (flag_code != CODE_64BIT | |
6636 | && i.hle_prefix | |
6637 | && t->base_opcode == 0xa0 | |
35648716 | 6638 | && t->opcode_modifier.opcodespace == SPACE_BASE |
75e5731b | 6639 | && i.types[0].bitfield.instance == Accum |
8dc0818e | 6640 | && (i.flags[1] & Operand_Mem)) |
1212781b | 6641 | continue; |
f5eb1d70 JB |
6642 | /* Fall through. */ |
6643 | ||
6644 | case 3: | |
3ac21baa JB |
6645 | if (!(size_match & MATCH_STRAIGHT)) |
6646 | goto check_reverse; | |
64c49ab3 JB |
6647 | /* Reverse direction of operands if swapping is possible in the first |
6648 | place (operands need to be symmetric) and | |
6649 | - the load form is requested, and the template is a store form, | |
6650 | - the store form is requested, and the template is a load form, | |
6651 | - the non-default (swapped) form is requested. */ | |
6652 | overlap1 = operand_type_and (operand_types[0], operand_types[1]); | |
f5eb1d70 | 6653 | if (t->opcode_modifier.d && i.reg_operands == i.operands |
64c49ab3 JB |
6654 | && !operand_type_all_zero (&overlap1)) |
6655 | switch (i.dir_encoding) | |
6656 | { | |
6657 | case dir_encoding_load: | |
6658 | if (operand_type_check (operand_types[i.operands - 1], anymem) | |
dfd69174 | 6659 | || t->opcode_modifier.regmem) |
64c49ab3 JB |
6660 | goto check_reverse; |
6661 | break; | |
6662 | ||
6663 | case dir_encoding_store: | |
6664 | if (!operand_type_check (operand_types[i.operands - 1], anymem) | |
dfd69174 | 6665 | && !t->opcode_modifier.regmem) |
64c49ab3 JB |
6666 | goto check_reverse; |
6667 | break; | |
6668 | ||
6669 | case dir_encoding_swap: | |
6670 | goto check_reverse; | |
6671 | ||
6672 | case dir_encoding_default: | |
6673 | break; | |
6674 | } | |
86fa6981 | 6675 | /* If we want store form, we skip the current load. */ |
64c49ab3 JB |
6676 | if ((i.dir_encoding == dir_encoding_store |
6677 | || i.dir_encoding == dir_encoding_swap) | |
86fa6981 L |
6678 | && i.mem_operands == 0 |
6679 | && t->opcode_modifier.load) | |
fa99fab2 | 6680 | continue; |
1a0670f3 | 6681 | /* Fall through. */ |
f48ff2ae | 6682 | case 4: |
c0f3af97 | 6683 | case 5: |
c6fb90c8 | 6684 | overlap1 = operand_type_and (i.types[1], operand_types[1]); |
40fb9820 L |
6685 | if (!operand_type_match (overlap0, i.types[0]) |
6686 | || !operand_type_match (overlap1, i.types[1]) | |
e2195274 | 6687 | || ((check_register & 3) == 3 |
dc821c5f | 6688 | && !operand_type_register_match (i.types[0], |
40fb9820 | 6689 | operand_types[0], |
dc821c5f | 6690 | i.types[1], |
40fb9820 | 6691 | operand_types[1]))) |
29b0f896 AM |
6692 | { |
6693 | /* Check if other direction is valid ... */ | |
38e314eb | 6694 | if (!t->opcode_modifier.d) |
29b0f896 AM |
6695 | continue; |
6696 | ||
dc1e8a47 | 6697 | check_reverse: |
3ac21baa JB |
6698 | if (!(size_match & MATCH_REVERSE)) |
6699 | continue; | |
29b0f896 | 6700 | /* Try reversing direction of operands. */ |
f5eb1d70 JB |
6701 | overlap0 = operand_type_and (i.types[0], operand_types[i.operands - 1]); |
6702 | overlap1 = operand_type_and (i.types[i.operands - 1], operand_types[0]); | |
40fb9820 | 6703 | if (!operand_type_match (overlap0, i.types[0]) |
f5eb1d70 | 6704 | || !operand_type_match (overlap1, i.types[i.operands - 1]) |
45664ddb | 6705 | || (check_register |
dc821c5f | 6706 | && !operand_type_register_match (i.types[0], |
f5eb1d70 JB |
6707 | operand_types[i.operands - 1], |
6708 | i.types[i.operands - 1], | |
45664ddb | 6709 | operand_types[0]))) |
29b0f896 AM |
6710 | { |
6711 | /* Does not match either direction. */ | |
6712 | continue; | |
6713 | } | |
38e314eb | 6714 | /* found_reverse_match holds which of D or FloatR |
29b0f896 | 6715 | we've found. */ |
38e314eb JB |
6716 | if (!t->opcode_modifier.d) |
6717 | found_reverse_match = 0; | |
6718 | else if (operand_types[0].bitfield.tbyte) | |
8a2ed489 | 6719 | found_reverse_match = Opcode_FloatD; |
dbbc8b7e | 6720 | else if (operand_types[0].bitfield.xmmword |
f5eb1d70 | 6721 | || operand_types[i.operands - 1].bitfield.xmmword |
3528c362 JB |
6722 | || operand_types[0].bitfield.class == RegMMX |
6723 | || operand_types[i.operands - 1].bitfield.class == RegMMX | |
dbbc8b7e JB |
6724 | || is_any_vex_encoding(t)) |
6725 | found_reverse_match = (t->base_opcode & 0xee) != 0x6e | |
6726 | ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD; | |
8a2ed489 | 6727 | else |
38e314eb | 6728 | found_reverse_match = Opcode_D; |
40fb9820 | 6729 | if (t->opcode_modifier.floatr) |
8a2ed489 | 6730 | found_reverse_match |= Opcode_FloatR; |
29b0f896 | 6731 | } |
f48ff2ae | 6732 | else |
29b0f896 | 6733 | { |
f48ff2ae | 6734 | /* Found a forward 2 operand match here. */ |
d1cbb4db L |
6735 | switch (t->operands) |
6736 | { | |
c0f3af97 L |
6737 | case 5: |
6738 | overlap4 = operand_type_and (i.types[4], | |
6739 | operand_types[4]); | |
1a0670f3 | 6740 | /* Fall through. */ |
d1cbb4db | 6741 | case 4: |
c6fb90c8 L |
6742 | overlap3 = operand_type_and (i.types[3], |
6743 | operand_types[3]); | |
1a0670f3 | 6744 | /* Fall through. */ |
d1cbb4db | 6745 | case 3: |
c6fb90c8 L |
6746 | overlap2 = operand_type_and (i.types[2], |
6747 | operand_types[2]); | |
d1cbb4db L |
6748 | break; |
6749 | } | |
29b0f896 | 6750 | |
f48ff2ae L |
6751 | switch (t->operands) |
6752 | { | |
c0f3af97 L |
6753 | case 5: |
6754 | if (!operand_type_match (overlap4, i.types[4]) | |
dc821c5f | 6755 | || !operand_type_register_match (i.types[3], |
c0f3af97 | 6756 | operand_types[3], |
c0f3af97 L |
6757 | i.types[4], |
6758 | operand_types[4])) | |
6759 | continue; | |
1a0670f3 | 6760 | /* Fall through. */ |
f48ff2ae | 6761 | case 4: |
40fb9820 | 6762 | if (!operand_type_match (overlap3, i.types[3]) |
e2195274 JB |
6763 | || ((check_register & 0xa) == 0xa |
6764 | && !operand_type_register_match (i.types[1], | |
f7768225 JB |
6765 | operand_types[1], |
6766 | i.types[3], | |
e2195274 JB |
6767 | operand_types[3])) |
6768 | || ((check_register & 0xc) == 0xc | |
6769 | && !operand_type_register_match (i.types[2], | |
6770 | operand_types[2], | |
6771 | i.types[3], | |
6772 | operand_types[3]))) | |
f48ff2ae | 6773 | continue; |
1a0670f3 | 6774 | /* Fall through. */ |
f48ff2ae L |
6775 | case 3: |
6776 | /* Here we make use of the fact that there are no | |
23e42951 | 6777 | reverse match 3 operand instructions. */ |
40fb9820 | 6778 | if (!operand_type_match (overlap2, i.types[2]) |
e2195274 JB |
6779 | || ((check_register & 5) == 5 |
6780 | && !operand_type_register_match (i.types[0], | |
23e42951 JB |
6781 | operand_types[0], |
6782 | i.types[2], | |
e2195274 JB |
6783 | operand_types[2])) |
6784 | || ((check_register & 6) == 6 | |
6785 | && !operand_type_register_match (i.types[1], | |
6786 | operand_types[1], | |
6787 | i.types[2], | |
6788 | operand_types[2]))) | |
f48ff2ae L |
6789 | continue; |
6790 | break; | |
6791 | } | |
29b0f896 | 6792 | } |
f48ff2ae | 6793 | /* Found either forward/reverse 2, 3 or 4 operand match here: |
29b0f896 AM |
6794 | slip through to break. */ |
6795 | } | |
c0f3af97 | 6796 | |
da4977e0 JB |
6797 | /* Check if vector operands are valid. */ |
6798 | if (check_VecOperands (t)) | |
6799 | { | |
6800 | specific_error = i.error; | |
6801 | continue; | |
6802 | } | |
6803 | ||
6804 | /* Check if VEX/EVEX encoding requirements can be satisfied. */ | |
6805 | if (VEX_check_encoding (t)) | |
5614d22c JB |
6806 | { |
6807 | specific_error = i.error; | |
6808 | continue; | |
6809 | } | |
a683cc34 | 6810 | |
29b0f896 AM |
6811 | /* We've found a match; break out of loop. */ |
6812 | break; | |
6813 | } | |
6814 | ||
6815 | if (t == current_templates->end) | |
6816 | { | |
6817 | /* We found no match. */ | |
a65babc9 | 6818 | const char *err_msg; |
5614d22c | 6819 | switch (specific_error ? specific_error : i.error) |
a65babc9 L |
6820 | { |
6821 | default: | |
6822 | abort (); | |
86e026a4 | 6823 | case operand_size_mismatch: |
a65babc9 L |
6824 | err_msg = _("operand size mismatch"); |
6825 | break; | |
6826 | case operand_type_mismatch: | |
6827 | err_msg = _("operand type mismatch"); | |
6828 | break; | |
6829 | case register_type_mismatch: | |
6830 | err_msg = _("register type mismatch"); | |
6831 | break; | |
6832 | case number_of_operands_mismatch: | |
6833 | err_msg = _("number of operands mismatch"); | |
6834 | break; | |
6835 | case invalid_instruction_suffix: | |
6836 | err_msg = _("invalid instruction suffix"); | |
6837 | break; | |
6838 | case bad_imm4: | |
4a2608e3 | 6839 | err_msg = _("constant doesn't fit in 4 bits"); |
a65babc9 | 6840 | break; |
a65babc9 L |
6841 | case unsupported_with_intel_mnemonic: |
6842 | err_msg = _("unsupported with Intel mnemonic"); | |
6843 | break; | |
6844 | case unsupported_syntax: | |
6845 | err_msg = _("unsupported syntax"); | |
6846 | break; | |
6847 | case unsupported: | |
35262a23 | 6848 | as_bad (_("unsupported instruction `%s'"), |
10efe3f6 L |
6849 | current_templates->start->name); |
6850 | return NULL; | |
260cd341 LC |
6851 | case invalid_sib_address: |
6852 | err_msg = _("invalid SIB address"); | |
6853 | break; | |
6c30d220 L |
6854 | case invalid_vsib_address: |
6855 | err_msg = _("invalid VSIB address"); | |
6856 | break; | |
7bab8ab5 JB |
6857 | case invalid_vector_register_set: |
6858 | err_msg = _("mask, index, and destination registers must be distinct"); | |
6859 | break; | |
260cd341 LC |
6860 | case invalid_tmm_register_set: |
6861 | err_msg = _("all tmm registers must be distinct"); | |
6862 | break; | |
6c30d220 L |
6863 | case unsupported_vector_index_register: |
6864 | err_msg = _("unsupported vector index register"); | |
6865 | break; | |
43234a1e L |
6866 | case unsupported_broadcast: |
6867 | err_msg = _("unsupported broadcast"); | |
6868 | break; | |
43234a1e L |
6869 | case broadcast_needed: |
6870 | err_msg = _("broadcast is needed for operand of such type"); | |
6871 | break; | |
6872 | case unsupported_masking: | |
6873 | err_msg = _("unsupported masking"); | |
6874 | break; | |
6875 | case mask_not_on_destination: | |
6876 | err_msg = _("mask not on destination operand"); | |
6877 | break; | |
6878 | case no_default_mask: | |
6879 | err_msg = _("default mask isn't allowed"); | |
6880 | break; | |
6881 | case unsupported_rc_sae: | |
6882 | err_msg = _("unsupported static rounding/sae"); | |
6883 | break; | |
6884 | case rc_sae_operand_not_last_imm: | |
6885 | if (intel_syntax) | |
6886 | err_msg = _("RC/SAE operand must precede immediate operands"); | |
6887 | else | |
6888 | err_msg = _("RC/SAE operand must follow immediate operands"); | |
6889 | break; | |
6890 | case invalid_register_operand: | |
6891 | err_msg = _("invalid register operand"); | |
6892 | break; | |
a65babc9 L |
6893 | } |
6894 | as_bad (_("%s for `%s'"), err_msg, | |
891edac4 | 6895 | current_templates->start->name); |
fa99fab2 | 6896 | return NULL; |
29b0f896 | 6897 | } |
252b5132 | 6898 | |
29b0f896 AM |
6899 | if (!quiet_warnings) |
6900 | { | |
6901 | if (!intel_syntax | |
0cfa3eb3 | 6902 | && (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))) |
6f2f06be | 6903 | as_warn (_("indirect %s without `*'"), t->name); |
29b0f896 | 6904 | |
40fb9820 | 6905 | if (t->opcode_modifier.isprefix |
3cd7f3e3 | 6906 | && t->opcode_modifier.mnemonicsize == IGNORESIZE) |
29b0f896 AM |
6907 | { |
6908 | /* Warn them that a data or address size prefix doesn't | |
6909 | affect assembly of the next line of code. */ | |
6910 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
6911 | } | |
6912 | } | |
6913 | ||
6914 | /* Copy the template we found. */ | |
9a182d04 | 6915 | install_template (t); |
539e75ad L |
6916 | |
6917 | if (addr_prefix_disp != -1) | |
6918 | i.tm.operand_types[addr_prefix_disp] | |
6919 | = operand_types[addr_prefix_disp]; | |
6920 | ||
29b0f896 AM |
6921 | if (found_reverse_match) |
6922 | { | |
dfd69174 JB |
6923 | /* If we found a reverse match we must alter the opcode direction |
6924 | bit and clear/flip the regmem modifier one. found_reverse_match | |
6925 | holds bits to change (different for int & float insns). */ | |
29b0f896 AM |
6926 | |
6927 | i.tm.base_opcode ^= found_reverse_match; | |
6928 | ||
f5eb1d70 JB |
6929 | i.tm.operand_types[0] = operand_types[i.operands - 1]; |
6930 | i.tm.operand_types[i.operands - 1] = operand_types[0]; | |
dfd69174 JB |
6931 | |
6932 | /* Certain SIMD insns have their load forms specified in the opcode | |
6933 | table, and hence we need to _set_ RegMem instead of clearing it. | |
6934 | We need to avoid setting the bit though on insns like KMOVW. */ | |
6935 | i.tm.opcode_modifier.regmem | |
6936 | = i.tm.opcode_modifier.modrm && i.tm.opcode_modifier.d | |
6937 | && i.tm.operands > 2U - i.tm.opcode_modifier.sse2avx | |
6938 | && !i.tm.opcode_modifier.regmem; | |
29b0f896 AM |
6939 | } |
6940 | ||
fa99fab2 | 6941 | return t; |
29b0f896 AM |
6942 | } |
6943 | ||
6944 | static int | |
e3bb37b5 | 6945 | check_string (void) |
29b0f896 | 6946 | { |
51c8edf6 JB |
6947 | unsigned int es_op = i.tm.opcode_modifier.isstring - IS_STRING_ES_OP0; |
6948 | unsigned int op = i.tm.operand_types[0].bitfield.baseindex ? es_op : 0; | |
8dc0818e | 6949 | |
5e042380 | 6950 | if (i.seg[op] != NULL && i.seg[op] != reg_es) |
29b0f896 | 6951 | { |
51c8edf6 JB |
6952 | as_bad (_("`%s' operand %u must use `%ses' segment"), |
6953 | i.tm.name, | |
6954 | intel_syntax ? i.tm.operands - es_op : es_op + 1, | |
6955 | register_prefix); | |
6956 | return 0; | |
29b0f896 | 6957 | } |
51c8edf6 JB |
6958 | |
6959 | /* There's only ever one segment override allowed per instruction. | |
6960 | This instruction possibly has a legal segment override on the | |
6961 | second operand, so copy the segment to where non-string | |
6962 | instructions store it, allowing common code. */ | |
6963 | i.seg[op] = i.seg[1]; | |
6964 | ||
29b0f896 AM |
6965 | return 1; |
6966 | } | |
6967 | ||
6968 | static int | |
543613e9 | 6969 | process_suffix (void) |
29b0f896 | 6970 | { |
5b7c81bd | 6971 | bool is_crc32 = false, is_movx = false; |
8b65b895 | 6972 | |
29b0f896 AM |
6973 | /* If matched instruction specifies an explicit instruction mnemonic |
6974 | suffix, use it. */ | |
673fe0f0 | 6975 | if (i.tm.opcode_modifier.size == SIZE16) |
40fb9820 | 6976 | i.suffix = WORD_MNEM_SUFFIX; |
673fe0f0 | 6977 | else if (i.tm.opcode_modifier.size == SIZE32) |
40fb9820 | 6978 | i.suffix = LONG_MNEM_SUFFIX; |
673fe0f0 | 6979 | else if (i.tm.opcode_modifier.size == SIZE64) |
40fb9820 | 6980 | i.suffix = QWORD_MNEM_SUFFIX; |
13e600d0 | 6981 | else if (i.reg_operands |
c8f8eebc JB |
6982 | && (i.operands > 1 || i.types[0].bitfield.class == Reg) |
6983 | && !i.tm.opcode_modifier.addrprefixopreg) | |
29b0f896 | 6984 | { |
65fca059 | 6985 | unsigned int numop = i.operands; |
389d00a5 JB |
6986 | |
6987 | /* MOVSX/MOVZX */ | |
6988 | is_movx = (i.tm.opcode_modifier.opcodespace == SPACE_0F | |
6989 | && (i.tm.base_opcode | 8) == 0xbe) | |
6990 | || (i.tm.opcode_modifier.opcodespace == SPACE_BASE | |
6991 | && i.tm.base_opcode == 0x63 | |
6992 | && i.tm.cpu_flags.bitfield.cpu64); | |
6993 | ||
8b65b895 | 6994 | /* CRC32 */ |
389d00a5 JB |
6995 | is_crc32 = (i.tm.base_opcode == 0xf0 |
6996 | && i.tm.opcode_modifier.opcodespace == SPACE_0F38 | |
8b65b895 | 6997 | && i.tm.opcode_modifier.opcodeprefix == PREFIX_0XF2); |
65fca059 JB |
6998 | |
6999 | /* movsx/movzx want only their source operand considered here, for the | |
7000 | ambiguity checking below. The suffix will be replaced afterwards | |
7001 | to represent the destination (register). */ | |
389d00a5 | 7002 | if (is_movx && (i.tm.opcode_modifier.w || i.tm.base_opcode == 0x63)) |
65fca059 JB |
7003 | --i.operands; |
7004 | ||
643bb870 | 7005 | /* crc32 needs REX.W set regardless of suffix / source operand size. */ |
8b65b895 | 7006 | if (is_crc32 && i.tm.operand_types[1].bitfield.qword) |
643bb870 JB |
7007 | i.rex |= REX_W; |
7008 | ||
29b0f896 | 7009 | /* If there's no instruction mnemonic suffix we try to invent one |
13e600d0 | 7010 | based on GPR operands. */ |
29b0f896 AM |
7011 | if (!i.suffix) |
7012 | { | |
7013 | /* We take i.suffix from the last register operand specified, | |
7014 | Destination register type is more significant than source | |
381d071f L |
7015 | register type. crc32 in SSE4.2 prefers source register |
7016 | type. */ | |
8b65b895 | 7017 | unsigned int op = is_crc32 ? 1 : i.operands; |
20592a94 | 7018 | |
1a035124 JB |
7019 | while (op--) |
7020 | if (i.tm.operand_types[op].bitfield.instance == InstanceNone | |
7021 | || i.tm.operand_types[op].bitfield.instance == Accum) | |
7022 | { | |
7023 | if (i.types[op].bitfield.class != Reg) | |
7024 | continue; | |
7025 | if (i.types[op].bitfield.byte) | |
7026 | i.suffix = BYTE_MNEM_SUFFIX; | |
7027 | else if (i.types[op].bitfield.word) | |
7028 | i.suffix = WORD_MNEM_SUFFIX; | |
7029 | else if (i.types[op].bitfield.dword) | |
7030 | i.suffix = LONG_MNEM_SUFFIX; | |
7031 | else if (i.types[op].bitfield.qword) | |
7032 | i.suffix = QWORD_MNEM_SUFFIX; | |
7033 | else | |
7034 | continue; | |
7035 | break; | |
7036 | } | |
65fca059 JB |
7037 | |
7038 | /* As an exception, movsx/movzx silently default to a byte source | |
7039 | in AT&T mode. */ | |
389d00a5 | 7040 | if (is_movx && i.tm.opcode_modifier.w && !i.suffix && !intel_syntax) |
65fca059 | 7041 | i.suffix = BYTE_MNEM_SUFFIX; |
29b0f896 AM |
7042 | } |
7043 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
7044 | { | |
2eb952a4 | 7045 | if (intel_syntax |
3cd7f3e3 | 7046 | && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE |
2eb952a4 L |
7047 | && i.tm.opcode_modifier.no_bsuf) |
7048 | i.suffix = 0; | |
7049 | else if (!check_byte_reg ()) | |
29b0f896 AM |
7050 | return 0; |
7051 | } | |
7052 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
7053 | { | |
2eb952a4 | 7054 | if (intel_syntax |
3cd7f3e3 | 7055 | && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE |
9f123b91 JB |
7056 | && i.tm.opcode_modifier.no_lsuf |
7057 | && !i.tm.opcode_modifier.todword | |
7058 | && !i.tm.opcode_modifier.toqword) | |
2eb952a4 L |
7059 | i.suffix = 0; |
7060 | else if (!check_long_reg ()) | |
29b0f896 AM |
7061 | return 0; |
7062 | } | |
7063 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
7064 | { | |
955e1e6a | 7065 | if (intel_syntax |
3cd7f3e3 | 7066 | && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE |
9f123b91 JB |
7067 | && i.tm.opcode_modifier.no_qsuf |
7068 | && !i.tm.opcode_modifier.todword | |
7069 | && !i.tm.opcode_modifier.toqword) | |
955e1e6a L |
7070 | i.suffix = 0; |
7071 | else if (!check_qword_reg ()) | |
29b0f896 AM |
7072 | return 0; |
7073 | } | |
7074 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
7075 | { | |
2eb952a4 | 7076 | if (intel_syntax |
3cd7f3e3 | 7077 | && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE |
2eb952a4 L |
7078 | && i.tm.opcode_modifier.no_wsuf) |
7079 | i.suffix = 0; | |
7080 | else if (!check_word_reg ()) | |
29b0f896 AM |
7081 | return 0; |
7082 | } | |
3cd7f3e3 L |
7083 | else if (intel_syntax |
7084 | && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE) | |
29b0f896 AM |
7085 | /* Do nothing if the instruction is going to ignore the prefix. */ |
7086 | ; | |
7087 | else | |
7088 | abort (); | |
65fca059 JB |
7089 | |
7090 | /* Undo the movsx/movzx change done above. */ | |
7091 | i.operands = numop; | |
29b0f896 | 7092 | } |
3cd7f3e3 L |
7093 | else if (i.tm.opcode_modifier.mnemonicsize == DEFAULTSIZE |
7094 | && !i.suffix) | |
29b0f896 | 7095 | { |
13e600d0 JB |
7096 | i.suffix = stackop_size; |
7097 | if (stackop_size == LONG_MNEM_SUFFIX) | |
06f74c5c L |
7098 | { |
7099 | /* stackop_size is set to LONG_MNEM_SUFFIX for the | |
7100 | .code16gcc directive to support 16-bit mode with | |
7101 | 32-bit address. For IRET without a suffix, generate | |
7102 | 16-bit IRET (opcode 0xcf) to return from an interrupt | |
7103 | handler. */ | |
13e600d0 JB |
7104 | if (i.tm.base_opcode == 0xcf) |
7105 | { | |
7106 | i.suffix = WORD_MNEM_SUFFIX; | |
7107 | as_warn (_("generating 16-bit `iret' for .code16gcc directive")); | |
7108 | } | |
7109 | /* Warn about changed behavior for segment register push/pop. */ | |
7110 | else if ((i.tm.base_opcode | 1) == 0x07) | |
7111 | as_warn (_("generating 32-bit `%s', unlike earlier gas versions"), | |
7112 | i.tm.name); | |
06f74c5c | 7113 | } |
29b0f896 | 7114 | } |
c006a730 | 7115 | else if (!i.suffix |
0cfa3eb3 JB |
7116 | && (i.tm.opcode_modifier.jump == JUMP_ABSOLUTE |
7117 | || i.tm.opcode_modifier.jump == JUMP_BYTE | |
7118 | || i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT | |
389d00a5 JB |
7119 | || (i.tm.opcode_modifier.opcodespace == SPACE_0F |
7120 | && i.tm.base_opcode == 0x01 /* [ls][gi]dt */ | |
64e74474 | 7121 | && i.tm.extension_opcode <= 3))) |
9306ca4a JB |
7122 | { |
7123 | switch (flag_code) | |
7124 | { | |
7125 | case CODE_64BIT: | |
40fb9820 | 7126 | if (!i.tm.opcode_modifier.no_qsuf) |
9306ca4a | 7127 | { |
828c2a25 JB |
7128 | if (i.tm.opcode_modifier.jump == JUMP_BYTE |
7129 | || i.tm.opcode_modifier.no_lsuf) | |
7130 | i.suffix = QWORD_MNEM_SUFFIX; | |
9306ca4a JB |
7131 | break; |
7132 | } | |
1a0670f3 | 7133 | /* Fall through. */ |
9306ca4a | 7134 | case CODE_32BIT: |
40fb9820 | 7135 | if (!i.tm.opcode_modifier.no_lsuf) |
9306ca4a JB |
7136 | i.suffix = LONG_MNEM_SUFFIX; |
7137 | break; | |
7138 | case CODE_16BIT: | |
40fb9820 | 7139 | if (!i.tm.opcode_modifier.no_wsuf) |
9306ca4a JB |
7140 | i.suffix = WORD_MNEM_SUFFIX; |
7141 | break; | |
7142 | } | |
7143 | } | |
252b5132 | 7144 | |
c006a730 | 7145 | if (!i.suffix |
3cd7f3e3 | 7146 | && (i.tm.opcode_modifier.mnemonicsize != DEFAULTSIZE |
873494c8 JB |
7147 | /* Also cover lret/retf/iret in 64-bit mode. */ |
7148 | || (flag_code == CODE_64BIT | |
7149 | && !i.tm.opcode_modifier.no_lsuf | |
7150 | && !i.tm.opcode_modifier.no_qsuf)) | |
3cd7f3e3 | 7151 | && i.tm.opcode_modifier.mnemonicsize != IGNORESIZE |
8bbb3ad8 JB |
7152 | /* Explicit sizing prefixes are assumed to disambiguate insns. */ |
7153 | && !i.prefix[DATA_PREFIX] && !(i.prefix[REX_PREFIX] & REX_W) | |
62b3f548 JB |
7154 | /* Accept FLDENV et al without suffix. */ |
7155 | && (i.tm.opcode_modifier.no_ssuf || i.tm.opcode_modifier.floatmf)) | |
29b0f896 | 7156 | { |
6c0946d0 | 7157 | unsigned int suffixes, evex = 0; |
c006a730 JB |
7158 | |
7159 | suffixes = !i.tm.opcode_modifier.no_bsuf; | |
7160 | if (!i.tm.opcode_modifier.no_wsuf) | |
7161 | suffixes |= 1 << 1; | |
7162 | if (!i.tm.opcode_modifier.no_lsuf) | |
7163 | suffixes |= 1 << 2; | |
7164 | if (!i.tm.opcode_modifier.no_ldsuf) | |
7165 | suffixes |= 1 << 3; | |
7166 | if (!i.tm.opcode_modifier.no_ssuf) | |
7167 | suffixes |= 1 << 4; | |
7168 | if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf) | |
7169 | suffixes |= 1 << 5; | |
7170 | ||
6c0946d0 JB |
7171 | /* For [XYZ]MMWORD operands inspect operand sizes. While generally |
7172 | also suitable for AT&T syntax mode, it was requested that this be | |
7173 | restricted to just Intel syntax. */ | |
5273a3cd | 7174 | if (intel_syntax && is_any_vex_encoding (&i.tm) && !i.broadcast.type) |
6c0946d0 | 7175 | { |
b9915cbc | 7176 | unsigned int op; |
6c0946d0 | 7177 | |
b9915cbc | 7178 | for (op = 0; op < i.tm.operands; ++op) |
6c0946d0 | 7179 | { |
b9915cbc JB |
7180 | if (is_evex_encoding (&i.tm) |
7181 | && !cpu_arch_flags.bitfield.cpuavx512vl) | |
6c0946d0 | 7182 | { |
b9915cbc JB |
7183 | if (i.tm.operand_types[op].bitfield.ymmword) |
7184 | i.tm.operand_types[op].bitfield.xmmword = 0; | |
7185 | if (i.tm.operand_types[op].bitfield.zmmword) | |
7186 | i.tm.operand_types[op].bitfield.ymmword = 0; | |
7187 | if (!i.tm.opcode_modifier.evex | |
7188 | || i.tm.opcode_modifier.evex == EVEXDYN) | |
7189 | i.tm.opcode_modifier.evex = EVEX512; | |
7190 | } | |
6c0946d0 | 7191 | |
b9915cbc JB |
7192 | if (i.tm.operand_types[op].bitfield.xmmword |
7193 | + i.tm.operand_types[op].bitfield.ymmword | |
7194 | + i.tm.operand_types[op].bitfield.zmmword < 2) | |
7195 | continue; | |
6c0946d0 | 7196 | |
b9915cbc JB |
7197 | /* Any properly sized operand disambiguates the insn. */ |
7198 | if (i.types[op].bitfield.xmmword | |
7199 | || i.types[op].bitfield.ymmword | |
7200 | || i.types[op].bitfield.zmmword) | |
7201 | { | |
7202 | suffixes &= ~(7 << 6); | |
7203 | evex = 0; | |
7204 | break; | |
7205 | } | |
6c0946d0 | 7206 | |
b9915cbc JB |
7207 | if ((i.flags[op] & Operand_Mem) |
7208 | && i.tm.operand_types[op].bitfield.unspecified) | |
7209 | { | |
7210 | if (i.tm.operand_types[op].bitfield.xmmword) | |
7211 | suffixes |= 1 << 6; | |
7212 | if (i.tm.operand_types[op].bitfield.ymmword) | |
7213 | suffixes |= 1 << 7; | |
7214 | if (i.tm.operand_types[op].bitfield.zmmword) | |
7215 | suffixes |= 1 << 8; | |
7216 | if (is_evex_encoding (&i.tm)) | |
7217 | evex = EVEX512; | |
6c0946d0 JB |
7218 | } |
7219 | } | |
7220 | } | |
7221 | ||
7222 | /* Are multiple suffixes / operand sizes allowed? */ | |
c006a730 | 7223 | if (suffixes & (suffixes - 1)) |
9306ca4a | 7224 | { |
873494c8 | 7225 | if (intel_syntax |
3cd7f3e3 | 7226 | && (i.tm.opcode_modifier.mnemonicsize != DEFAULTSIZE |
873494c8 | 7227 | || operand_check == check_error)) |
9306ca4a | 7228 | { |
c006a730 | 7229 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); |
9306ca4a JB |
7230 | return 0; |
7231 | } | |
c006a730 | 7232 | if (operand_check == check_error) |
9306ca4a | 7233 | { |
c006a730 JB |
7234 | as_bad (_("no instruction mnemonic suffix given and " |
7235 | "no register operands; can't size `%s'"), i.tm.name); | |
9306ca4a JB |
7236 | return 0; |
7237 | } | |
c006a730 | 7238 | if (operand_check == check_warning) |
873494c8 JB |
7239 | as_warn (_("%s; using default for `%s'"), |
7240 | intel_syntax | |
7241 | ? _("ambiguous operand size") | |
7242 | : _("no instruction mnemonic suffix given and " | |
7243 | "no register operands"), | |
7244 | i.tm.name); | |
c006a730 JB |
7245 | |
7246 | if (i.tm.opcode_modifier.floatmf) | |
7247 | i.suffix = SHORT_MNEM_SUFFIX; | |
389d00a5 | 7248 | else if (is_movx) |
65fca059 | 7249 | /* handled below */; |
6c0946d0 JB |
7250 | else if (evex) |
7251 | i.tm.opcode_modifier.evex = evex; | |
c006a730 JB |
7252 | else if (flag_code == CODE_16BIT) |
7253 | i.suffix = WORD_MNEM_SUFFIX; | |
1a035124 | 7254 | else if (!i.tm.opcode_modifier.no_lsuf) |
c006a730 | 7255 | i.suffix = LONG_MNEM_SUFFIX; |
1a035124 JB |
7256 | else |
7257 | i.suffix = QWORD_MNEM_SUFFIX; | |
9306ca4a | 7258 | } |
29b0f896 | 7259 | } |
252b5132 | 7260 | |
389d00a5 | 7261 | if (is_movx) |
65fca059 JB |
7262 | { |
7263 | /* In Intel syntax, movsx/movzx must have a "suffix" (checked above). | |
7264 | In AT&T syntax, if there is no suffix (warned about above), the default | |
7265 | will be byte extension. */ | |
7266 | if (i.tm.opcode_modifier.w && i.suffix && i.suffix != BYTE_MNEM_SUFFIX) | |
7267 | i.tm.base_opcode |= 1; | |
7268 | ||
7269 | /* For further processing, the suffix should represent the destination | |
7270 | (register). This is already the case when one was used with | |
7271 | mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was | |
7272 | no suffix to begin with. */ | |
7273 | if (i.tm.opcode_modifier.w || i.tm.base_opcode == 0x63 || !i.suffix) | |
7274 | { | |
7275 | if (i.types[1].bitfield.word) | |
7276 | i.suffix = WORD_MNEM_SUFFIX; | |
7277 | else if (i.types[1].bitfield.qword) | |
7278 | i.suffix = QWORD_MNEM_SUFFIX; | |
7279 | else | |
7280 | i.suffix = LONG_MNEM_SUFFIX; | |
7281 | ||
7282 | i.tm.opcode_modifier.w = 0; | |
7283 | } | |
7284 | } | |
7285 | ||
50128d0c JB |
7286 | if (!i.tm.opcode_modifier.modrm && i.reg_operands && i.tm.operands < 3) |
7287 | i.short_form = (i.tm.operand_types[0].bitfield.class == Reg) | |
7288 | != (i.tm.operand_types[1].bitfield.class == Reg); | |
7289 | ||
d2224064 JB |
7290 | /* Change the opcode based on the operand size given by i.suffix. */ |
7291 | switch (i.suffix) | |
29b0f896 | 7292 | { |
d2224064 JB |
7293 | /* Size floating point instruction. */ |
7294 | case LONG_MNEM_SUFFIX: | |
7295 | if (i.tm.opcode_modifier.floatmf) | |
7296 | { | |
7297 | i.tm.base_opcode ^= 4; | |
7298 | break; | |
7299 | } | |
7300 | /* fall through */ | |
7301 | case WORD_MNEM_SUFFIX: | |
7302 | case QWORD_MNEM_SUFFIX: | |
29b0f896 | 7303 | /* It's not a byte, select word/dword operation. */ |
40fb9820 | 7304 | if (i.tm.opcode_modifier.w) |
29b0f896 | 7305 | { |
50128d0c | 7306 | if (i.short_form) |
29b0f896 AM |
7307 | i.tm.base_opcode |= 8; |
7308 | else | |
7309 | i.tm.base_opcode |= 1; | |
7310 | } | |
d2224064 JB |
7311 | /* fall through */ |
7312 | case SHORT_MNEM_SUFFIX: | |
29b0f896 AM |
7313 | /* Now select between word & dword operations via the operand |
7314 | size prefix, except for instructions that will ignore this | |
7315 | prefix anyway. */ | |
c8f8eebc | 7316 | if (i.suffix != QWORD_MNEM_SUFFIX |
3cd7f3e3 | 7317 | && i.tm.opcode_modifier.mnemonicsize != IGNORESIZE |
c8f8eebc JB |
7318 | && !i.tm.opcode_modifier.floatmf |
7319 | && !is_any_vex_encoding (&i.tm) | |
7320 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) | |
7321 | || (flag_code == CODE_64BIT | |
7322 | && i.tm.opcode_modifier.jump == JUMP_BYTE))) | |
24eab124 AM |
7323 | { |
7324 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
543613e9 | 7325 | |
0cfa3eb3 | 7326 | if (i.tm.opcode_modifier.jump == JUMP_BYTE) /* jcxz, loop */ |
29b0f896 | 7327 | prefix = ADDR_PREFIX_OPCODE; |
252b5132 | 7328 | |
29b0f896 AM |
7329 | if (!add_prefix (prefix)) |
7330 | return 0; | |
24eab124 | 7331 | } |
252b5132 | 7332 | |
29b0f896 AM |
7333 | /* Set mode64 for an operand. */ |
7334 | if (i.suffix == QWORD_MNEM_SUFFIX | |
9146926a | 7335 | && flag_code == CODE_64BIT |
d2224064 | 7336 | && !i.tm.opcode_modifier.norex64 |
4ed21b58 | 7337 | && !i.tm.opcode_modifier.vexw |
46e883c5 | 7338 | /* Special case for xchg %rax,%rax. It is NOP and doesn't |
d2224064 JB |
7339 | need rex64. */ |
7340 | && ! (i.operands == 2 | |
7341 | && i.tm.base_opcode == 0x90 | |
7342 | && i.tm.extension_opcode == None | |
75e5731b JB |
7343 | && i.types[0].bitfield.instance == Accum |
7344 | && i.types[0].bitfield.qword | |
7345 | && i.types[1].bitfield.instance == Accum | |
7346 | && i.types[1].bitfield.qword)) | |
d2224064 | 7347 | i.rex |= REX_W; |
3e73aa7c | 7348 | |
d2224064 | 7349 | break; |
8bbb3ad8 JB |
7350 | |
7351 | case 0: | |
f9a6a8f0 | 7352 | /* Select word/dword/qword operation with explicit data sizing prefix |
8bbb3ad8 JB |
7353 | when there are no suitable register operands. */ |
7354 | if (i.tm.opcode_modifier.w | |
7355 | && (i.prefix[DATA_PREFIX] || (i.prefix[REX_PREFIX] & REX_W)) | |
7356 | && (!i.reg_operands | |
7357 | || (i.reg_operands == 1 | |
7358 | /* ShiftCount */ | |
7359 | && (i.tm.operand_types[0].bitfield.instance == RegC | |
7360 | /* InOutPortReg */ | |
7361 | || i.tm.operand_types[0].bitfield.instance == RegD | |
7362 | || i.tm.operand_types[1].bitfield.instance == RegD | |
7363 | /* CRC32 */ | |
8b65b895 | 7364 | || is_crc32)))) |
8bbb3ad8 JB |
7365 | i.tm.base_opcode |= 1; |
7366 | break; | |
29b0f896 | 7367 | } |
7ecd2f8b | 7368 | |
c8f8eebc | 7369 | if (i.tm.opcode_modifier.addrprefixopreg) |
c0a30a9f | 7370 | { |
c8f8eebc JB |
7371 | gas_assert (!i.suffix); |
7372 | gas_assert (i.reg_operands); | |
c0a30a9f | 7373 | |
c8f8eebc JB |
7374 | if (i.tm.operand_types[0].bitfield.instance == Accum |
7375 | || i.operands == 1) | |
7376 | { | |
7377 | /* The address size override prefix changes the size of the | |
7378 | first operand. */ | |
7379 | if (flag_code == CODE_64BIT | |
7380 | && i.op[0].regs->reg_type.bitfield.word) | |
7381 | { | |
7382 | as_bad (_("16-bit addressing unavailable for `%s'"), | |
7383 | i.tm.name); | |
7384 | return 0; | |
7385 | } | |
7386 | ||
7387 | if ((flag_code == CODE_32BIT | |
7388 | ? i.op[0].regs->reg_type.bitfield.word | |
7389 | : i.op[0].regs->reg_type.bitfield.dword) | |
7390 | && !add_prefix (ADDR_PREFIX_OPCODE)) | |
7391 | return 0; | |
7392 | } | |
c0a30a9f L |
7393 | else |
7394 | { | |
c8f8eebc JB |
7395 | /* Check invalid register operand when the address size override |
7396 | prefix changes the size of register operands. */ | |
7397 | unsigned int op; | |
7398 | enum { need_word, need_dword, need_qword } need; | |
7399 | ||
27f13469 | 7400 | /* Check the register operand for the address size prefix if |
b3a3496f | 7401 | the memory operand has no real registers, like symbol, DISP |
829f3fe1 | 7402 | or bogus (x32-only) symbol(%rip) when symbol(%eip) is meant. */ |
27f13469 L |
7403 | if (i.mem_operands == 1 |
7404 | && i.reg_operands == 1 | |
7405 | && i.operands == 2 | |
27f13469 | 7406 | && i.types[1].bitfield.class == Reg |
b3a3496f L |
7407 | && (flag_code == CODE_32BIT |
7408 | ? i.op[1].regs->reg_type.bitfield.word | |
7409 | : i.op[1].regs->reg_type.bitfield.dword) | |
7410 | && ((i.base_reg == NULL && i.index_reg == NULL) | |
829f3fe1 JB |
7411 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
7412 | || (x86_elf_abi == X86_64_X32_ABI | |
7413 | && i.base_reg | |
b3a3496f L |
7414 | && i.base_reg->reg_num == RegIP |
7415 | && i.base_reg->reg_type.bitfield.qword)) | |
829f3fe1 JB |
7416 | #else |
7417 | || 0) | |
7418 | #endif | |
27f13469 L |
7419 | && !add_prefix (ADDR_PREFIX_OPCODE)) |
7420 | return 0; | |
7421 | ||
c8f8eebc JB |
7422 | if (flag_code == CODE_32BIT) |
7423 | need = i.prefix[ADDR_PREFIX] ? need_word : need_dword; | |
7424 | else if (i.prefix[ADDR_PREFIX]) | |
c0a30a9f L |
7425 | need = need_dword; |
7426 | else | |
7427 | need = flag_code == CODE_64BIT ? need_qword : need_word; | |
c0a30a9f | 7428 | |
c8f8eebc JB |
7429 | for (op = 0; op < i.operands; op++) |
7430 | { | |
7431 | if (i.types[op].bitfield.class != Reg) | |
7432 | continue; | |
7433 | ||
7434 | switch (need) | |
7435 | { | |
7436 | case need_word: | |
7437 | if (i.op[op].regs->reg_type.bitfield.word) | |
7438 | continue; | |
7439 | break; | |
7440 | case need_dword: | |
7441 | if (i.op[op].regs->reg_type.bitfield.dword) | |
7442 | continue; | |
7443 | break; | |
7444 | case need_qword: | |
7445 | if (i.op[op].regs->reg_type.bitfield.qword) | |
7446 | continue; | |
7447 | break; | |
7448 | } | |
7449 | ||
7450 | as_bad (_("invalid register operand size for `%s'"), | |
7451 | i.tm.name); | |
7452 | return 0; | |
7453 | } | |
7454 | } | |
c0a30a9f L |
7455 | } |
7456 | ||
29b0f896 AM |
7457 | return 1; |
7458 | } | |
3e73aa7c | 7459 | |
29b0f896 | 7460 | static int |
543613e9 | 7461 | check_byte_reg (void) |
29b0f896 AM |
7462 | { |
7463 | int op; | |
543613e9 | 7464 | |
29b0f896 AM |
7465 | for (op = i.operands; --op >= 0;) |
7466 | { | |
dc821c5f | 7467 | /* Skip non-register operands. */ |
bab6aec1 | 7468 | if (i.types[op].bitfield.class != Reg) |
dc821c5f JB |
7469 | continue; |
7470 | ||
29b0f896 AM |
7471 | /* If this is an eight bit register, it's OK. If it's the 16 or |
7472 | 32 bit version of an eight bit register, we will just use the | |
7473 | low portion, and that's OK too. */ | |
dc821c5f | 7474 | if (i.types[op].bitfield.byte) |
29b0f896 AM |
7475 | continue; |
7476 | ||
5a819eb9 | 7477 | /* I/O port address operands are OK too. */ |
75e5731b JB |
7478 | if (i.tm.operand_types[op].bitfield.instance == RegD |
7479 | && i.tm.operand_types[op].bitfield.word) | |
5a819eb9 JB |
7480 | continue; |
7481 | ||
9706160a | 7482 | /* crc32 only wants its source operand checked here. */ |
389d00a5 JB |
7483 | if (i.tm.base_opcode == 0xf0 |
7484 | && i.tm.opcode_modifier.opcodespace == SPACE_0F38 | |
8b65b895 L |
7485 | && i.tm.opcode_modifier.opcodeprefix == PREFIX_0XF2 |
7486 | && op != 0) | |
9344ff29 L |
7487 | continue; |
7488 | ||
29b0f896 | 7489 | /* Any other register is bad. */ |
73c76375 JB |
7490 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
7491 | register_prefix, i.op[op].regs->reg_name, | |
7492 | i.tm.name, i.suffix); | |
7493 | return 0; | |
29b0f896 AM |
7494 | } |
7495 | return 1; | |
7496 | } | |
7497 | ||
7498 | static int | |
e3bb37b5 | 7499 | check_long_reg (void) |
29b0f896 AM |
7500 | { |
7501 | int op; | |
7502 | ||
7503 | for (op = i.operands; --op >= 0;) | |
dc821c5f | 7504 | /* Skip non-register operands. */ |
bab6aec1 | 7505 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 7506 | continue; |
29b0f896 AM |
7507 | /* Reject eight bit registers, except where the template requires |
7508 | them. (eg. movzb) */ | |
dc821c5f | 7509 | else if (i.types[op].bitfield.byte |
bab6aec1 | 7510 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 7511 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f JB |
7512 | && (i.tm.operand_types[op].bitfield.word |
7513 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 7514 | { |
a540244d L |
7515 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
7516 | register_prefix, | |
29b0f896 AM |
7517 | i.op[op].regs->reg_name, |
7518 | i.tm.name, | |
7519 | i.suffix); | |
7520 | return 0; | |
7521 | } | |
be4c5e58 L |
7522 | /* Error if the e prefix on a general reg is missing. */ |
7523 | else if (i.types[op].bitfield.word | |
bab6aec1 | 7524 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 7525 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 7526 | && i.tm.operand_types[op].bitfield.dword) |
29b0f896 | 7527 | { |
be4c5e58 L |
7528 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
7529 | register_prefix, i.op[op].regs->reg_name, | |
7530 | i.suffix); | |
7531 | return 0; | |
252b5132 | 7532 | } |
e4630f71 | 7533 | /* Warn if the r prefix on a general reg is present. */ |
dc821c5f | 7534 | else if (i.types[op].bitfield.qword |
bab6aec1 | 7535 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 7536 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 7537 | && i.tm.operand_types[op].bitfield.dword) |
252b5132 | 7538 | { |
34828aad | 7539 | if (intel_syntax |
65fca059 | 7540 | && i.tm.opcode_modifier.toqword |
3528c362 | 7541 | && i.types[0].bitfield.class != RegSIMD) |
34828aad | 7542 | { |
ca61edf2 | 7543 | /* Convert to QWORD. We want REX byte. */ |
34828aad L |
7544 | i.suffix = QWORD_MNEM_SUFFIX; |
7545 | } | |
7546 | else | |
7547 | { | |
2b5d6a91 | 7548 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
7549 | register_prefix, i.op[op].regs->reg_name, |
7550 | i.suffix); | |
7551 | return 0; | |
7552 | } | |
29b0f896 AM |
7553 | } |
7554 | return 1; | |
7555 | } | |
252b5132 | 7556 | |
29b0f896 | 7557 | static int |
e3bb37b5 | 7558 | check_qword_reg (void) |
29b0f896 AM |
7559 | { |
7560 | int op; | |
252b5132 | 7561 | |
29b0f896 | 7562 | for (op = i.operands; --op >= 0; ) |
dc821c5f | 7563 | /* Skip non-register operands. */ |
bab6aec1 | 7564 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 7565 | continue; |
29b0f896 AM |
7566 | /* Reject eight bit registers, except where the template requires |
7567 | them. (eg. movzb) */ | |
dc821c5f | 7568 | else if (i.types[op].bitfield.byte |
bab6aec1 | 7569 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 7570 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f JB |
7571 | && (i.tm.operand_types[op].bitfield.word |
7572 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 7573 | { |
a540244d L |
7574 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
7575 | register_prefix, | |
29b0f896 AM |
7576 | i.op[op].regs->reg_name, |
7577 | i.tm.name, | |
7578 | i.suffix); | |
7579 | return 0; | |
7580 | } | |
e4630f71 | 7581 | /* Warn if the r prefix on a general reg is missing. */ |
dc821c5f JB |
7582 | else if ((i.types[op].bitfield.word |
7583 | || i.types[op].bitfield.dword) | |
bab6aec1 | 7584 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 7585 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 7586 | && i.tm.operand_types[op].bitfield.qword) |
29b0f896 AM |
7587 | { |
7588 | /* Prohibit these changes in the 64bit mode, since the | |
7589 | lowering is more complicated. */ | |
34828aad | 7590 | if (intel_syntax |
ca61edf2 | 7591 | && i.tm.opcode_modifier.todword |
3528c362 | 7592 | && i.types[0].bitfield.class != RegSIMD) |
34828aad | 7593 | { |
ca61edf2 | 7594 | /* Convert to DWORD. We don't want REX byte. */ |
34828aad L |
7595 | i.suffix = LONG_MNEM_SUFFIX; |
7596 | } | |
7597 | else | |
7598 | { | |
2b5d6a91 | 7599 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
7600 | register_prefix, i.op[op].regs->reg_name, |
7601 | i.suffix); | |
7602 | return 0; | |
7603 | } | |
252b5132 | 7604 | } |
29b0f896 AM |
7605 | return 1; |
7606 | } | |
252b5132 | 7607 | |
29b0f896 | 7608 | static int |
e3bb37b5 | 7609 | check_word_reg (void) |
29b0f896 AM |
7610 | { |
7611 | int op; | |
7612 | for (op = i.operands; --op >= 0;) | |
dc821c5f | 7613 | /* Skip non-register operands. */ |
bab6aec1 | 7614 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 7615 | continue; |
29b0f896 AM |
7616 | /* Reject eight bit registers, except where the template requires |
7617 | them. (eg. movzb) */ | |
dc821c5f | 7618 | else if (i.types[op].bitfield.byte |
bab6aec1 | 7619 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 7620 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f JB |
7621 | && (i.tm.operand_types[op].bitfield.word |
7622 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 7623 | { |
a540244d L |
7624 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
7625 | register_prefix, | |
29b0f896 AM |
7626 | i.op[op].regs->reg_name, |
7627 | i.tm.name, | |
7628 | i.suffix); | |
7629 | return 0; | |
7630 | } | |
9706160a JB |
7631 | /* Error if the e or r prefix on a general reg is present. */ |
7632 | else if ((i.types[op].bitfield.dword | |
dc821c5f | 7633 | || i.types[op].bitfield.qword) |
bab6aec1 | 7634 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 7635 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 7636 | && i.tm.operand_types[op].bitfield.word) |
252b5132 | 7637 | { |
9706160a JB |
7638 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
7639 | register_prefix, i.op[op].regs->reg_name, | |
7640 | i.suffix); | |
7641 | return 0; | |
29b0f896 AM |
7642 | } |
7643 | return 1; | |
7644 | } | |
252b5132 | 7645 | |
29b0f896 | 7646 | static int |
40fb9820 | 7647 | update_imm (unsigned int j) |
29b0f896 | 7648 | { |
bc0844ae | 7649 | i386_operand_type overlap = i.types[j]; |
40fb9820 L |
7650 | if ((overlap.bitfield.imm8 |
7651 | || overlap.bitfield.imm8s | |
7652 | || overlap.bitfield.imm16 | |
7653 | || overlap.bitfield.imm32 | |
7654 | || overlap.bitfield.imm32s | |
7655 | || overlap.bitfield.imm64) | |
0dfbf9d7 L |
7656 | && !operand_type_equal (&overlap, &imm8) |
7657 | && !operand_type_equal (&overlap, &imm8s) | |
7658 | && !operand_type_equal (&overlap, &imm16) | |
7659 | && !operand_type_equal (&overlap, &imm32) | |
7660 | && !operand_type_equal (&overlap, &imm32s) | |
7661 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 AM |
7662 | { |
7663 | if (i.suffix) | |
7664 | { | |
40fb9820 L |
7665 | i386_operand_type temp; |
7666 | ||
0dfbf9d7 | 7667 | operand_type_set (&temp, 0); |
7ab9ffdd | 7668 | if (i.suffix == BYTE_MNEM_SUFFIX) |
40fb9820 L |
7669 | { |
7670 | temp.bitfield.imm8 = overlap.bitfield.imm8; | |
7671 | temp.bitfield.imm8s = overlap.bitfield.imm8s; | |
7672 | } | |
7673 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
7674 | temp.bitfield.imm16 = overlap.bitfield.imm16; | |
7675 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
7676 | { | |
7677 | temp.bitfield.imm64 = overlap.bitfield.imm64; | |
7678 | temp.bitfield.imm32s = overlap.bitfield.imm32s; | |
7679 | } | |
7680 | else | |
7681 | temp.bitfield.imm32 = overlap.bitfield.imm32; | |
7682 | overlap = temp; | |
29b0f896 | 7683 | } |
0dfbf9d7 L |
7684 | else if (operand_type_equal (&overlap, &imm16_32_32s) |
7685 | || operand_type_equal (&overlap, &imm16_32) | |
7686 | || operand_type_equal (&overlap, &imm16_32s)) | |
29b0f896 | 7687 | { |
40fb9820 | 7688 | if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
65da13b5 | 7689 | overlap = imm16; |
40fb9820 | 7690 | else |
65da13b5 | 7691 | overlap = imm32s; |
29b0f896 | 7692 | } |
8bbb3ad8 JB |
7693 | else if (i.prefix[REX_PREFIX] & REX_W) |
7694 | overlap = operand_type_and (overlap, imm32s); | |
7695 | else if (i.prefix[DATA_PREFIX]) | |
7696 | overlap = operand_type_and (overlap, | |
7697 | flag_code != CODE_16BIT ? imm16 : imm32); | |
0dfbf9d7 L |
7698 | if (!operand_type_equal (&overlap, &imm8) |
7699 | && !operand_type_equal (&overlap, &imm8s) | |
7700 | && !operand_type_equal (&overlap, &imm16) | |
7701 | && !operand_type_equal (&overlap, &imm32) | |
7702 | && !operand_type_equal (&overlap, &imm32s) | |
7703 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 | 7704 | { |
4eed87de AM |
7705 | as_bad (_("no instruction mnemonic suffix given; " |
7706 | "can't determine immediate size")); | |
29b0f896 AM |
7707 | return 0; |
7708 | } | |
7709 | } | |
40fb9820 | 7710 | i.types[j] = overlap; |
29b0f896 | 7711 | |
40fb9820 L |
7712 | return 1; |
7713 | } | |
7714 | ||
7715 | static int | |
7716 | finalize_imm (void) | |
7717 | { | |
bc0844ae | 7718 | unsigned int j, n; |
29b0f896 | 7719 | |
bc0844ae L |
7720 | /* Update the first 2 immediate operands. */ |
7721 | n = i.operands > 2 ? 2 : i.operands; | |
7722 | if (n) | |
7723 | { | |
7724 | for (j = 0; j < n; j++) | |
7725 | if (update_imm (j) == 0) | |
7726 | return 0; | |
40fb9820 | 7727 | |
bc0844ae L |
7728 | /* The 3rd operand can't be immediate operand. */ |
7729 | gas_assert (operand_type_check (i.types[2], imm) == 0); | |
7730 | } | |
29b0f896 AM |
7731 | |
7732 | return 1; | |
7733 | } | |
7734 | ||
7735 | static int | |
e3bb37b5 | 7736 | process_operands (void) |
29b0f896 AM |
7737 | { |
7738 | /* Default segment register this instruction will use for memory | |
7739 | accesses. 0 means unknown. This is only for optimizing out | |
7740 | unnecessary segment overrides. */ | |
5e042380 | 7741 | const reg_entry *default_seg = NULL; |
29b0f896 | 7742 | |
a5aeccd9 JB |
7743 | if (i.tm.opcode_modifier.sse2avx) |
7744 | { | |
7745 | /* Legacy encoded insns allow explicit REX prefixes, so these prefixes | |
7746 | need converting. */ | |
7747 | i.rex |= i.prefix[REX_PREFIX] & (REX_W | REX_R | REX_X | REX_B); | |
7748 | i.prefix[REX_PREFIX] = 0; | |
7749 | i.rex_encoding = 0; | |
7750 | } | |
c423d21a JB |
7751 | /* ImmExt should be processed after SSE2AVX. */ |
7752 | else if (i.tm.opcode_modifier.immext) | |
7753 | process_immext (); | |
a5aeccd9 | 7754 | |
2426c15f | 7755 | if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv) |
29b0f896 | 7756 | { |
91d6fa6a NC |
7757 | unsigned int dupl = i.operands; |
7758 | unsigned int dest = dupl - 1; | |
9fcfb3d7 L |
7759 | unsigned int j; |
7760 | ||
c0f3af97 | 7761 | /* The destination must be an xmm register. */ |
9c2799c2 | 7762 | gas_assert (i.reg_operands |
91d6fa6a | 7763 | && MAX_OPERANDS > dupl |
7ab9ffdd | 7764 | && operand_type_equal (&i.types[dest], ®xmm)); |
c0f3af97 | 7765 | |
75e5731b | 7766 | if (i.tm.operand_types[0].bitfield.instance == Accum |
1b54b8d7 | 7767 | && i.tm.operand_types[0].bitfield.xmmword) |
e2ec9d29 | 7768 | { |
8cd7925b | 7769 | if (i.tm.opcode_modifier.vexsources == VEX3SOURCES) |
c0f3af97 L |
7770 | { |
7771 | /* Keep xmm0 for instructions with VEX prefix and 3 | |
7772 | sources. */ | |
75e5731b | 7773 | i.tm.operand_types[0].bitfield.instance = InstanceNone; |
3528c362 | 7774 | i.tm.operand_types[0].bitfield.class = RegSIMD; |
c0f3af97 L |
7775 | goto duplicate; |
7776 | } | |
e2ec9d29 | 7777 | else |
c0f3af97 L |
7778 | { |
7779 | /* We remove the first xmm0 and keep the number of | |
7780 | operands unchanged, which in fact duplicates the | |
7781 | destination. */ | |
7782 | for (j = 1; j < i.operands; j++) | |
7783 | { | |
7784 | i.op[j - 1] = i.op[j]; | |
7785 | i.types[j - 1] = i.types[j]; | |
7786 | i.tm.operand_types[j - 1] = i.tm.operand_types[j]; | |
8dc0818e | 7787 | i.flags[j - 1] = i.flags[j]; |
c0f3af97 L |
7788 | } |
7789 | } | |
7790 | } | |
7791 | else if (i.tm.opcode_modifier.implicit1stxmm0) | |
7ab9ffdd | 7792 | { |
91d6fa6a | 7793 | gas_assert ((MAX_OPERANDS - 1) > dupl |
8cd7925b L |
7794 | && (i.tm.opcode_modifier.vexsources |
7795 | == VEX3SOURCES)); | |
c0f3af97 L |
7796 | |
7797 | /* Add the implicit xmm0 for instructions with VEX prefix | |
7798 | and 3 sources. */ | |
7799 | for (j = i.operands; j > 0; j--) | |
7800 | { | |
7801 | i.op[j] = i.op[j - 1]; | |
7802 | i.types[j] = i.types[j - 1]; | |
7803 | i.tm.operand_types[j] = i.tm.operand_types[j - 1]; | |
8dc0818e | 7804 | i.flags[j] = i.flags[j - 1]; |
c0f3af97 L |
7805 | } |
7806 | i.op[0].regs | |
629310ab | 7807 | = (const reg_entry *) str_hash_find (reg_hash, "xmm0"); |
7ab9ffdd | 7808 | i.types[0] = regxmm; |
c0f3af97 L |
7809 | i.tm.operand_types[0] = regxmm; |
7810 | ||
7811 | i.operands += 2; | |
7812 | i.reg_operands += 2; | |
7813 | i.tm.operands += 2; | |
7814 | ||
91d6fa6a | 7815 | dupl++; |
c0f3af97 | 7816 | dest++; |
91d6fa6a NC |
7817 | i.op[dupl] = i.op[dest]; |
7818 | i.types[dupl] = i.types[dest]; | |
7819 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
8dc0818e | 7820 | i.flags[dupl] = i.flags[dest]; |
e2ec9d29 | 7821 | } |
c0f3af97 L |
7822 | else |
7823 | { | |
dc1e8a47 | 7824 | duplicate: |
c0f3af97 L |
7825 | i.operands++; |
7826 | i.reg_operands++; | |
7827 | i.tm.operands++; | |
7828 | ||
91d6fa6a NC |
7829 | i.op[dupl] = i.op[dest]; |
7830 | i.types[dupl] = i.types[dest]; | |
7831 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
8dc0818e | 7832 | i.flags[dupl] = i.flags[dest]; |
c0f3af97 L |
7833 | } |
7834 | ||
7835 | if (i.tm.opcode_modifier.immext) | |
7836 | process_immext (); | |
7837 | } | |
75e5731b | 7838 | else if (i.tm.operand_types[0].bitfield.instance == Accum |
1b54b8d7 | 7839 | && i.tm.operand_types[0].bitfield.xmmword) |
c0f3af97 L |
7840 | { |
7841 | unsigned int j; | |
7842 | ||
9fcfb3d7 L |
7843 | for (j = 1; j < i.operands; j++) |
7844 | { | |
7845 | i.op[j - 1] = i.op[j]; | |
7846 | i.types[j - 1] = i.types[j]; | |
7847 | ||
7848 | /* We need to adjust fields in i.tm since they are used by | |
7849 | build_modrm_byte. */ | |
7850 | i.tm.operand_types [j - 1] = i.tm.operand_types [j]; | |
8dc0818e JB |
7851 | |
7852 | i.flags[j - 1] = i.flags[j]; | |
9fcfb3d7 L |
7853 | } |
7854 | ||
e2ec9d29 L |
7855 | i.operands--; |
7856 | i.reg_operands--; | |
e2ec9d29 L |
7857 | i.tm.operands--; |
7858 | } | |
920d2ddc IT |
7859 | else if (i.tm.opcode_modifier.implicitquadgroup) |
7860 | { | |
a477a8c4 JB |
7861 | unsigned int regnum, first_reg_in_group, last_reg_in_group; |
7862 | ||
920d2ddc | 7863 | /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */ |
3528c362 | 7864 | gas_assert (i.operands >= 2 && i.types[1].bitfield.class == RegSIMD); |
a477a8c4 JB |
7865 | regnum = register_number (i.op[1].regs); |
7866 | first_reg_in_group = regnum & ~3; | |
7867 | last_reg_in_group = first_reg_in_group + 3; | |
7868 | if (regnum != first_reg_in_group) | |
7869 | as_warn (_("source register `%s%s' implicitly denotes" | |
7870 | " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"), | |
7871 | register_prefix, i.op[1].regs->reg_name, | |
7872 | register_prefix, i.op[1].regs->reg_name, first_reg_in_group, | |
7873 | register_prefix, i.op[1].regs->reg_name, last_reg_in_group, | |
7874 | i.tm.name); | |
7875 | } | |
e2ec9d29 L |
7876 | else if (i.tm.opcode_modifier.regkludge) |
7877 | { | |
7878 | /* The imul $imm, %reg instruction is converted into | |
7879 | imul $imm, %reg, %reg, and the clr %reg instruction | |
7880 | is converted into xor %reg, %reg. */ | |
7881 | ||
7882 | unsigned int first_reg_op; | |
7883 | ||
7884 | if (operand_type_check (i.types[0], reg)) | |
7885 | first_reg_op = 0; | |
7886 | else | |
7887 | first_reg_op = 1; | |
7888 | /* Pretend we saw the extra register operand. */ | |
9c2799c2 | 7889 | gas_assert (i.reg_operands == 1 |
7ab9ffdd | 7890 | && i.op[first_reg_op + 1].regs == 0); |
e2ec9d29 L |
7891 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; |
7892 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
7893 | i.operands++; | |
7894 | i.reg_operands++; | |
29b0f896 AM |
7895 | } |
7896 | ||
85b80b0f | 7897 | if (i.tm.opcode_modifier.modrm) |
29b0f896 AM |
7898 | { |
7899 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
52271982 AM |
7900 | must be put into the modrm byte). Now, we make the modrm and |
7901 | index base bytes based on all the info we've collected. */ | |
29b0f896 AM |
7902 | |
7903 | default_seg = build_modrm_byte (); | |
7904 | } | |
00cee14f | 7905 | else if (i.types[0].bitfield.class == SReg) |
85b80b0f JB |
7906 | { |
7907 | if (flag_code != CODE_64BIT | |
7908 | ? i.tm.base_opcode == POP_SEG_SHORT | |
7909 | && i.op[0].regs->reg_num == 1 | |
389d00a5 | 7910 | : (i.tm.base_opcode | 1) == (POP_SEG386_SHORT & 0xff) |
85b80b0f JB |
7911 | && i.op[0].regs->reg_num < 4) |
7912 | { | |
7913 | as_bad (_("you can't `%s %s%s'"), | |
7914 | i.tm.name, register_prefix, i.op[0].regs->reg_name); | |
7915 | return 0; | |
7916 | } | |
389d00a5 JB |
7917 | if (i.op[0].regs->reg_num > 3 |
7918 | && i.tm.opcode_modifier.opcodespace == SPACE_BASE ) | |
85b80b0f | 7919 | { |
389d00a5 JB |
7920 | i.tm.base_opcode ^= (POP_SEG_SHORT ^ POP_SEG386_SHORT) & 0xff; |
7921 | i.tm.opcode_modifier.opcodespace = SPACE_0F; | |
85b80b0f JB |
7922 | } |
7923 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); | |
7924 | } | |
389d00a5 JB |
7925 | else if (i.tm.opcode_modifier.opcodespace == SPACE_BASE |
7926 | && (i.tm.base_opcode & ~3) == MOV_AX_DISP32) | |
29b0f896 | 7927 | { |
5e042380 | 7928 | default_seg = reg_ds; |
29b0f896 | 7929 | } |
40fb9820 | 7930 | else if (i.tm.opcode_modifier.isstring) |
29b0f896 AM |
7931 | { |
7932 | /* For the string instructions that allow a segment override | |
7933 | on one of their operands, the default segment is ds. */ | |
5e042380 | 7934 | default_seg = reg_ds; |
29b0f896 | 7935 | } |
50128d0c | 7936 | else if (i.short_form) |
85b80b0f JB |
7937 | { |
7938 | /* The register or float register operand is in operand | |
7939 | 0 or 1. */ | |
bab6aec1 | 7940 | unsigned int op = i.tm.operand_types[0].bitfield.class != Reg; |
85b80b0f JB |
7941 | |
7942 | /* Register goes in low 3 bits of opcode. */ | |
7943 | i.tm.base_opcode |= i.op[op].regs->reg_num; | |
7944 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
7945 | i.rex |= REX_B; | |
7946 | if (!quiet_warnings && i.tm.opcode_modifier.ugh) | |
7947 | { | |
7948 | /* Warn about some common errors, but press on regardless. | |
7949 | The first case can be generated by gcc (<= 2.8.1). */ | |
7950 | if (i.operands == 2) | |
7951 | { | |
7952 | /* Reversed arguments on faddp, fsubp, etc. */ | |
7953 | as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, | |
7954 | register_prefix, i.op[!intel_syntax].regs->reg_name, | |
7955 | register_prefix, i.op[intel_syntax].regs->reg_name); | |
7956 | } | |
7957 | else | |
7958 | { | |
7959 | /* Extraneous `l' suffix on fp insn. */ | |
7960 | as_warn (_("translating to `%s %s%s'"), i.tm.name, | |
7961 | register_prefix, i.op[0].regs->reg_name); | |
7962 | } | |
7963 | } | |
7964 | } | |
29b0f896 | 7965 | |
514a8bb0 | 7966 | if ((i.seg[0] || i.prefix[SEG_PREFIX]) |
514a8bb0 | 7967 | && i.tm.base_opcode == 0x8d /* lea */ |
35648716 | 7968 | && i.tm.opcode_modifier.opcodespace == SPACE_BASE |
514a8bb0 | 7969 | && !is_any_vex_encoding(&i.tm)) |
92334ad2 JB |
7970 | { |
7971 | if (!quiet_warnings) | |
7972 | as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); | |
7973 | if (optimize) | |
7974 | { | |
7975 | i.seg[0] = NULL; | |
7976 | i.prefix[SEG_PREFIX] = 0; | |
7977 | } | |
7978 | } | |
52271982 AM |
7979 | |
7980 | /* If a segment was explicitly specified, and the specified segment | |
b6773884 JB |
7981 | is neither the default nor the one already recorded from a prefix, |
7982 | use an opcode prefix to select it. If we never figured out what | |
7983 | the default segment is, then default_seg will be zero at this | |
7984 | point, and the specified segment prefix will always be used. */ | |
7985 | if (i.seg[0] | |
7986 | && i.seg[0] != default_seg | |
5e042380 | 7987 | && i386_seg_prefixes[i.seg[0]->reg_num] != i.prefix[SEG_PREFIX]) |
29b0f896 | 7988 | { |
5e042380 | 7989 | if (!add_prefix (i386_seg_prefixes[i.seg[0]->reg_num])) |
29b0f896 AM |
7990 | return 0; |
7991 | } | |
7992 | return 1; | |
7993 | } | |
7994 | ||
a5aeccd9 | 7995 | static INLINE void set_rex_vrex (const reg_entry *r, unsigned int rex_bit, |
5b7c81bd | 7996 | bool do_sse2avx) |
a5aeccd9 JB |
7997 | { |
7998 | if (r->reg_flags & RegRex) | |
7999 | { | |
8000 | if (i.rex & rex_bit) | |
8001 | as_bad (_("same type of prefix used twice")); | |
8002 | i.rex |= rex_bit; | |
8003 | } | |
8004 | else if (do_sse2avx && (i.rex & rex_bit) && i.vex.register_specifier) | |
8005 | { | |
8006 | gas_assert (i.vex.register_specifier == r); | |
8007 | i.vex.register_specifier += 8; | |
8008 | } | |
8009 | ||
8010 | if (r->reg_flags & RegVRex) | |
8011 | i.vrex |= rex_bit; | |
8012 | } | |
8013 | ||
5e042380 | 8014 | static const reg_entry * |
e3bb37b5 | 8015 | build_modrm_byte (void) |
29b0f896 | 8016 | { |
5e042380 | 8017 | const reg_entry *default_seg = NULL; |
c0f3af97 | 8018 | unsigned int source, dest; |
8cd7925b | 8019 | int vex_3_sources; |
c0f3af97 | 8020 | |
8cd7925b | 8021 | vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES; |
c0f3af97 L |
8022 | if (vex_3_sources) |
8023 | { | |
91d6fa6a | 8024 | unsigned int nds, reg_slot; |
4c2c6516 | 8025 | expressionS *exp; |
c0f3af97 | 8026 | |
6b8d3588 | 8027 | dest = i.operands - 1; |
c0f3af97 | 8028 | nds = dest - 1; |
922d8de8 | 8029 | |
a683cc34 | 8030 | /* There are 2 kinds of instructions: |
bed3d976 | 8031 | 1. 5 operands: 4 register operands or 3 register operands |
9d3bf266 | 8032 | plus 1 memory operand plus one Imm4 operand, VexXDS, and |
bed3d976 | 8033 | VexW0 or VexW1. The destination must be either XMM, YMM or |
43234a1e | 8034 | ZMM register. |
bed3d976 | 8035 | 2. 4 operands: 4 register operands or 3 register operands |
2f1bada2 | 8036 | plus 1 memory operand, with VexXDS. */ |
922d8de8 | 8037 | gas_assert ((i.reg_operands == 4 |
bed3d976 JB |
8038 | || (i.reg_operands == 3 && i.mem_operands == 1)) |
8039 | && i.tm.opcode_modifier.vexvvvv == VEXXDS | |
dcd7e323 | 8040 | && i.tm.opcode_modifier.vexw |
3528c362 | 8041 | && i.tm.operand_types[dest].bitfield.class == RegSIMD); |
a683cc34 | 8042 | |
48db9223 JB |
8043 | /* If VexW1 is set, the first non-immediate operand is the source and |
8044 | the second non-immediate one is encoded in the immediate operand. */ | |
8045 | if (i.tm.opcode_modifier.vexw == VEXW1) | |
8046 | { | |
8047 | source = i.imm_operands; | |
8048 | reg_slot = i.imm_operands + 1; | |
8049 | } | |
8050 | else | |
8051 | { | |
8052 | source = i.imm_operands + 1; | |
8053 | reg_slot = i.imm_operands; | |
8054 | } | |
8055 | ||
a683cc34 | 8056 | if (i.imm_operands == 0) |
bed3d976 JB |
8057 | { |
8058 | /* When there is no immediate operand, generate an 8bit | |
8059 | immediate operand to encode the first operand. */ | |
8060 | exp = &im_expressions[i.imm_operands++]; | |
8061 | i.op[i.operands].imms = exp; | |
8062 | i.types[i.operands] = imm8; | |
8063 | i.operands++; | |
8064 | ||
3528c362 | 8065 | gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD); |
bed3d976 JB |
8066 | exp->X_op = O_constant; |
8067 | exp->X_add_number = register_number (i.op[reg_slot].regs) << 4; | |
43234a1e L |
8068 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
8069 | } | |
922d8de8 | 8070 | else |
bed3d976 | 8071 | { |
9d3bf266 JB |
8072 | gas_assert (i.imm_operands == 1); |
8073 | gas_assert (fits_in_imm4 (i.op[0].imms->X_add_number)); | |
8074 | gas_assert (!i.tm.opcode_modifier.immext); | |
a683cc34 | 8075 | |
9d3bf266 JB |
8076 | /* Turn on Imm8 again so that output_imm will generate it. */ |
8077 | i.types[0].bitfield.imm8 = 1; | |
bed3d976 | 8078 | |
3528c362 | 8079 | gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD); |
9d3bf266 | 8080 | i.op[0].imms->X_add_number |
bed3d976 | 8081 | |= register_number (i.op[reg_slot].regs) << 4; |
43234a1e | 8082 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
bed3d976 | 8083 | } |
a683cc34 | 8084 | |
3528c362 | 8085 | gas_assert (i.tm.operand_types[nds].bitfield.class == RegSIMD); |
dae39acc | 8086 | i.vex.register_specifier = i.op[nds].regs; |
c0f3af97 L |
8087 | } |
8088 | else | |
8089 | source = dest = 0; | |
29b0f896 AM |
8090 | |
8091 | /* i.reg_operands MUST be the number of real register operands; | |
c0f3af97 L |
8092 | implicit registers do not count. If there are 3 register |
8093 | operands, it must be a instruction with VexNDS. For a | |
8094 | instruction with VexNDD, the destination register is encoded | |
8095 | in VEX prefix. If there are 4 register operands, it must be | |
8096 | a instruction with VEX prefix and 3 sources. */ | |
7ab9ffdd L |
8097 | if (i.mem_operands == 0 |
8098 | && ((i.reg_operands == 2 | |
2426c15f | 8099 | && i.tm.opcode_modifier.vexvvvv <= VEXXDS) |
7ab9ffdd | 8100 | || (i.reg_operands == 3 |
2426c15f | 8101 | && i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd | 8102 | || (i.reg_operands == 4 && vex_3_sources))) |
29b0f896 | 8103 | { |
cab737b9 L |
8104 | switch (i.operands) |
8105 | { | |
8106 | case 2: | |
8107 | source = 0; | |
8108 | break; | |
8109 | case 3: | |
c81128dc L |
8110 | /* When there are 3 operands, one of them may be immediate, |
8111 | which may be the first or the last operand. Otherwise, | |
c0f3af97 L |
8112 | the first operand must be shift count register (cl) or it |
8113 | is an instruction with VexNDS. */ | |
9c2799c2 | 8114 | gas_assert (i.imm_operands == 1 |
7ab9ffdd | 8115 | || (i.imm_operands == 0 |
2426c15f | 8116 | && (i.tm.opcode_modifier.vexvvvv == VEXXDS |
75e5731b JB |
8117 | || (i.types[0].bitfield.instance == RegC |
8118 | && i.types[0].bitfield.byte)))); | |
40fb9820 | 8119 | if (operand_type_check (i.types[0], imm) |
75e5731b JB |
8120 | || (i.types[0].bitfield.instance == RegC |
8121 | && i.types[0].bitfield.byte)) | |
40fb9820 L |
8122 | source = 1; |
8123 | else | |
8124 | source = 0; | |
cab737b9 L |
8125 | break; |
8126 | case 4: | |
368d64cc L |
8127 | /* When there are 4 operands, the first two must be 8bit |
8128 | immediate operands. The source operand will be the 3rd | |
c0f3af97 L |
8129 | one. |
8130 | ||
8131 | For instructions with VexNDS, if the first operand | |
8132 | an imm8, the source operand is the 2nd one. If the last | |
8133 | operand is imm8, the source operand is the first one. */ | |
9c2799c2 | 8134 | gas_assert ((i.imm_operands == 2 |
7ab9ffdd L |
8135 | && i.types[0].bitfield.imm8 |
8136 | && i.types[1].bitfield.imm8) | |
2426c15f | 8137 | || (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd L |
8138 | && i.imm_operands == 1 |
8139 | && (i.types[0].bitfield.imm8 | |
43234a1e | 8140 | || i.types[i.operands - 1].bitfield.imm8 |
ca5312a2 | 8141 | || i.rounding.type != rc_none))); |
9f2670f2 L |
8142 | if (i.imm_operands == 2) |
8143 | source = 2; | |
8144 | else | |
c0f3af97 L |
8145 | { |
8146 | if (i.types[0].bitfield.imm8) | |
8147 | source = 1; | |
8148 | else | |
8149 | source = 0; | |
8150 | } | |
c0f3af97 L |
8151 | break; |
8152 | case 5: | |
e771e7c9 | 8153 | if (is_evex_encoding (&i.tm)) |
43234a1e L |
8154 | { |
8155 | /* For EVEX instructions, when there are 5 operands, the | |
8156 | first one must be immediate operand. If the second one | |
8157 | is immediate operand, the source operand is the 3th | |
8158 | one. If the last one is immediate operand, the source | |
8159 | operand is the 2nd one. */ | |
8160 | gas_assert (i.imm_operands == 2 | |
8161 | && i.tm.opcode_modifier.sae | |
8162 | && operand_type_check (i.types[0], imm)); | |
8163 | if (operand_type_check (i.types[1], imm)) | |
8164 | source = 2; | |
8165 | else if (operand_type_check (i.types[4], imm)) | |
8166 | source = 1; | |
8167 | else | |
8168 | abort (); | |
8169 | } | |
cab737b9 L |
8170 | break; |
8171 | default: | |
8172 | abort (); | |
8173 | } | |
8174 | ||
c0f3af97 L |
8175 | if (!vex_3_sources) |
8176 | { | |
8177 | dest = source + 1; | |
8178 | ||
43234a1e L |
8179 | /* RC/SAE operand could be between DEST and SRC. That happens |
8180 | when one operand is GPR and the other one is XMM/YMM/ZMM | |
8181 | register. */ | |
ca5312a2 | 8182 | if (i.rounding.type != rc_none && i.rounding.operand == dest) |
43234a1e L |
8183 | dest++; |
8184 | ||
2426c15f | 8185 | if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
c0f3af97 | 8186 | { |
43234a1e | 8187 | /* For instructions with VexNDS, the register-only source |
c5d0745b | 8188 | operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask |
dfd69174 | 8189 | register. It is encoded in VEX prefix. */ |
f12dc422 L |
8190 | |
8191 | i386_operand_type op; | |
8192 | unsigned int vvvv; | |
8193 | ||
c2ecccb3 L |
8194 | /* Swap two source operands if needed. */ |
8195 | if (i.tm.opcode_modifier.swapsources) | |
f12dc422 L |
8196 | { |
8197 | vvvv = source; | |
8198 | source = dest; | |
8199 | } | |
8200 | else | |
8201 | vvvv = dest; | |
8202 | ||
8203 | op = i.tm.operand_types[vvvv]; | |
c0f3af97 | 8204 | if ((dest + 1) >= i.operands |
bab6aec1 | 8205 | || ((op.bitfield.class != Reg |
dc821c5f | 8206 | || (!op.bitfield.dword && !op.bitfield.qword)) |
3528c362 | 8207 | && op.bitfield.class != RegSIMD |
43234a1e | 8208 | && !operand_type_equal (&op, ®mask))) |
c0f3af97 | 8209 | abort (); |
f12dc422 | 8210 | i.vex.register_specifier = i.op[vvvv].regs; |
c0f3af97 L |
8211 | dest++; |
8212 | } | |
8213 | } | |
29b0f896 AM |
8214 | |
8215 | i.rm.mode = 3; | |
dfd69174 JB |
8216 | /* One of the register operands will be encoded in the i.rm.reg |
8217 | field, the other in the combined i.rm.mode and i.rm.regmem | |
29b0f896 AM |
8218 | fields. If no form of this instruction supports a memory |
8219 | destination operand, then we assume the source operand may | |
8220 | sometimes be a memory operand and so we need to store the | |
8221 | destination in the i.rm.reg field. */ | |
dfd69174 | 8222 | if (!i.tm.opcode_modifier.regmem |
40fb9820 | 8223 | && operand_type_check (i.tm.operand_types[dest], anymem) == 0) |
29b0f896 AM |
8224 | { |
8225 | i.rm.reg = i.op[dest].regs->reg_num; | |
8226 | i.rm.regmem = i.op[source].regs->reg_num; | |
a5aeccd9 | 8227 | set_rex_vrex (i.op[dest].regs, REX_R, i.tm.opcode_modifier.sse2avx); |
5b7c81bd | 8228 | set_rex_vrex (i.op[source].regs, REX_B, false); |
29b0f896 AM |
8229 | } |
8230 | else | |
8231 | { | |
8232 | i.rm.reg = i.op[source].regs->reg_num; | |
8233 | i.rm.regmem = i.op[dest].regs->reg_num; | |
a5aeccd9 | 8234 | set_rex_vrex (i.op[dest].regs, REX_B, i.tm.opcode_modifier.sse2avx); |
5b7c81bd | 8235 | set_rex_vrex (i.op[source].regs, REX_R, false); |
29b0f896 | 8236 | } |
e0c7f900 | 8237 | if (flag_code != CODE_64BIT && (i.rex & REX_R)) |
c4a530c5 | 8238 | { |
4a5c67ed | 8239 | if (i.types[!i.tm.opcode_modifier.regmem].bitfield.class != RegCR) |
c4a530c5 | 8240 | abort (); |
e0c7f900 | 8241 | i.rex &= ~REX_R; |
c4a530c5 JB |
8242 | add_prefix (LOCK_PREFIX_OPCODE); |
8243 | } | |
29b0f896 AM |
8244 | } |
8245 | else | |
8246 | { /* If it's not 2 reg operands... */ | |
c0f3af97 L |
8247 | unsigned int mem; |
8248 | ||
29b0f896 AM |
8249 | if (i.mem_operands) |
8250 | { | |
8251 | unsigned int fake_zero_displacement = 0; | |
99018f42 | 8252 | unsigned int op; |
4eed87de | 8253 | |
7ab9ffdd | 8254 | for (op = 0; op < i.operands; op++) |
8dc0818e | 8255 | if (i.flags[op] & Operand_Mem) |
7ab9ffdd | 8256 | break; |
7ab9ffdd | 8257 | gas_assert (op < i.operands); |
29b0f896 | 8258 | |
63112cd6 | 8259 | if (i.tm.opcode_modifier.sib) |
6c30d220 | 8260 | { |
260cd341 LC |
8261 | /* The index register of VSIB shouldn't be RegIZ. */ |
8262 | if (i.tm.opcode_modifier.sib != SIBMEM | |
8263 | && i.index_reg->reg_num == RegIZ) | |
6c30d220 L |
8264 | abort (); |
8265 | ||
8266 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
8267 | if (!i.base_reg) | |
8268 | { | |
8269 | i.sib.base = NO_BASE_REGISTER; | |
8270 | i.sib.scale = i.log2_scale_factor; | |
8271 | i.types[op].bitfield.disp8 = 0; | |
8272 | i.types[op].bitfield.disp16 = 0; | |
8273 | i.types[op].bitfield.disp64 = 0; | |
a9aabc23 | 8274 | if (want_disp32 (&i.tm)) |
6c30d220 L |
8275 | { |
8276 | /* Must be 32 bit */ | |
8277 | i.types[op].bitfield.disp32 = 1; | |
8278 | i.types[op].bitfield.disp32s = 0; | |
8279 | } | |
8280 | else | |
8281 | { | |
8282 | i.types[op].bitfield.disp32 = 0; | |
8283 | i.types[op].bitfield.disp32s = 1; | |
8284 | } | |
8285 | } | |
260cd341 LC |
8286 | |
8287 | /* Since the mandatory SIB always has index register, so | |
8288 | the code logic remains unchanged. The non-mandatory SIB | |
8289 | without index register is allowed and will be handled | |
8290 | later. */ | |
8291 | if (i.index_reg) | |
8292 | { | |
8293 | if (i.index_reg->reg_num == RegIZ) | |
8294 | i.sib.index = NO_INDEX_REGISTER; | |
8295 | else | |
8296 | i.sib.index = i.index_reg->reg_num; | |
5b7c81bd | 8297 | set_rex_vrex (i.index_reg, REX_X, false); |
260cd341 | 8298 | } |
6c30d220 L |
8299 | } |
8300 | ||
5e042380 | 8301 | default_seg = reg_ds; |
29b0f896 AM |
8302 | |
8303 | if (i.base_reg == 0) | |
8304 | { | |
8305 | i.rm.mode = 0; | |
8306 | if (!i.disp_operands) | |
9bb129e8 | 8307 | fake_zero_displacement = 1; |
29b0f896 AM |
8308 | if (i.index_reg == 0) |
8309 | { | |
73053c1f JB |
8310 | i386_operand_type newdisp; |
8311 | ||
260cd341 LC |
8312 | /* Both check for VSIB and mandatory non-vector SIB. */ |
8313 | gas_assert (!i.tm.opcode_modifier.sib | |
8314 | || i.tm.opcode_modifier.sib == SIBMEM); | |
29b0f896 | 8315 | /* Operand is just <disp> */ |
20f0a1fc | 8316 | if (flag_code == CODE_64BIT) |
29b0f896 AM |
8317 | { |
8318 | /* 64bit mode overwrites the 32bit absolute | |
8319 | addressing by RIP relative addressing and | |
8320 | absolute addressing is encoded by one of the | |
8321 | redundant SIB forms. */ | |
8322 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
8323 | i.sib.base = NO_BASE_REGISTER; | |
8324 | i.sib.index = NO_INDEX_REGISTER; | |
a9aabc23 | 8325 | newdisp = (want_disp32(&i.tm) ? disp32 : disp32s); |
20f0a1fc | 8326 | } |
fc225355 L |
8327 | else if ((flag_code == CODE_16BIT) |
8328 | ^ (i.prefix[ADDR_PREFIX] != 0)) | |
20f0a1fc NC |
8329 | { |
8330 | i.rm.regmem = NO_BASE_REGISTER_16; | |
73053c1f | 8331 | newdisp = disp16; |
20f0a1fc NC |
8332 | } |
8333 | else | |
8334 | { | |
8335 | i.rm.regmem = NO_BASE_REGISTER; | |
73053c1f | 8336 | newdisp = disp32; |
29b0f896 | 8337 | } |
73053c1f JB |
8338 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
8339 | i.types[op] = operand_type_or (i.types[op], newdisp); | |
29b0f896 | 8340 | } |
63112cd6 | 8341 | else if (!i.tm.opcode_modifier.sib) |
29b0f896 | 8342 | { |
6c30d220 | 8343 | /* !i.base_reg && i.index_reg */ |
e968fc9b | 8344 | if (i.index_reg->reg_num == RegIZ) |
db51cc60 L |
8345 | i.sib.index = NO_INDEX_REGISTER; |
8346 | else | |
8347 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
8348 | i.sib.base = NO_BASE_REGISTER; |
8349 | i.sib.scale = i.log2_scale_factor; | |
8350 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
40fb9820 L |
8351 | i.types[op].bitfield.disp8 = 0; |
8352 | i.types[op].bitfield.disp16 = 0; | |
8353 | i.types[op].bitfield.disp64 = 0; | |
a9aabc23 | 8354 | if (want_disp32 (&i.tm)) |
40fb9820 L |
8355 | { |
8356 | /* Must be 32 bit */ | |
8357 | i.types[op].bitfield.disp32 = 1; | |
8358 | i.types[op].bitfield.disp32s = 0; | |
8359 | } | |
29b0f896 | 8360 | else |
40fb9820 L |
8361 | { |
8362 | i.types[op].bitfield.disp32 = 0; | |
8363 | i.types[op].bitfield.disp32s = 1; | |
8364 | } | |
29b0f896 | 8365 | if ((i.index_reg->reg_flags & RegRex) != 0) |
161a04f6 | 8366 | i.rex |= REX_X; |
29b0f896 AM |
8367 | } |
8368 | } | |
8369 | /* RIP addressing for 64bit mode. */ | |
e968fc9b | 8370 | else if (i.base_reg->reg_num == RegIP) |
29b0f896 | 8371 | { |
63112cd6 | 8372 | gas_assert (!i.tm.opcode_modifier.sib); |
29b0f896 | 8373 | i.rm.regmem = NO_BASE_REGISTER; |
40fb9820 L |
8374 | i.types[op].bitfield.disp8 = 0; |
8375 | i.types[op].bitfield.disp16 = 0; | |
8376 | i.types[op].bitfield.disp32 = 0; | |
8377 | i.types[op].bitfield.disp32s = 1; | |
8378 | i.types[op].bitfield.disp64 = 0; | |
71903a11 | 8379 | i.flags[op] |= Operand_PCrel; |
20f0a1fc NC |
8380 | if (! i.disp_operands) |
8381 | fake_zero_displacement = 1; | |
29b0f896 | 8382 | } |
dc821c5f | 8383 | else if (i.base_reg->reg_type.bitfield.word) |
29b0f896 | 8384 | { |
63112cd6 | 8385 | gas_assert (!i.tm.opcode_modifier.sib); |
29b0f896 AM |
8386 | switch (i.base_reg->reg_num) |
8387 | { | |
8388 | case 3: /* (%bx) */ | |
8389 | if (i.index_reg == 0) | |
8390 | i.rm.regmem = 7; | |
8391 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
8392 | i.rm.regmem = i.index_reg->reg_num - 6; | |
8393 | break; | |
8394 | case 5: /* (%bp) */ | |
5e042380 | 8395 | default_seg = reg_ss; |
29b0f896 AM |
8396 | if (i.index_reg == 0) |
8397 | { | |
8398 | i.rm.regmem = 6; | |
40fb9820 | 8399 | if (operand_type_check (i.types[op], disp) == 0) |
29b0f896 AM |
8400 | { |
8401 | /* fake (%bp) into 0(%bp) */ | |
41eb8e88 | 8402 | if (i.disp_encoding == disp_encoding_16bit) |
1a02d6b0 L |
8403 | i.types[op].bitfield.disp16 = 1; |
8404 | else | |
8405 | i.types[op].bitfield.disp8 = 1; | |
252b5132 | 8406 | fake_zero_displacement = 1; |
29b0f896 AM |
8407 | } |
8408 | } | |
8409 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
8410 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
8411 | break; | |
8412 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
8413 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
8414 | } | |
41eb8e88 L |
8415 | if (!fake_zero_displacement |
8416 | && !i.disp_operands | |
8417 | && i.disp_encoding) | |
8418 | { | |
8419 | fake_zero_displacement = 1; | |
8420 | if (i.disp_encoding == disp_encoding_8bit) | |
8421 | i.types[op].bitfield.disp8 = 1; | |
8422 | else | |
8423 | i.types[op].bitfield.disp16 = 1; | |
8424 | } | |
29b0f896 AM |
8425 | i.rm.mode = mode_from_disp_size (i.types[op]); |
8426 | } | |
8427 | else /* i.base_reg and 32/64 bit mode */ | |
8428 | { | |
a9aabc23 | 8429 | if (operand_type_check (i.types[op], disp)) |
40fb9820 | 8430 | { |
73053c1f JB |
8431 | i.types[op].bitfield.disp16 = 0; |
8432 | i.types[op].bitfield.disp64 = 0; | |
a9aabc23 | 8433 | if (!want_disp32 (&i.tm)) |
73053c1f JB |
8434 | { |
8435 | i.types[op].bitfield.disp32 = 0; | |
8436 | i.types[op].bitfield.disp32s = 1; | |
8437 | } | |
40fb9820 | 8438 | else |
73053c1f JB |
8439 | { |
8440 | i.types[op].bitfield.disp32 = 1; | |
8441 | i.types[op].bitfield.disp32s = 0; | |
8442 | } | |
40fb9820 | 8443 | } |
20f0a1fc | 8444 | |
63112cd6 | 8445 | if (!i.tm.opcode_modifier.sib) |
6c30d220 | 8446 | i.rm.regmem = i.base_reg->reg_num; |
29b0f896 | 8447 | if ((i.base_reg->reg_flags & RegRex) != 0) |
161a04f6 | 8448 | i.rex |= REX_B; |
29b0f896 AM |
8449 | i.sib.base = i.base_reg->reg_num; |
8450 | /* x86-64 ignores REX prefix bit here to avoid decoder | |
8451 | complications. */ | |
848930b2 JB |
8452 | if (!(i.base_reg->reg_flags & RegRex) |
8453 | && (i.base_reg->reg_num == EBP_REG_NUM | |
8454 | || i.base_reg->reg_num == ESP_REG_NUM)) | |
5e042380 | 8455 | default_seg = reg_ss; |
848930b2 | 8456 | if (i.base_reg->reg_num == 5 && i.disp_operands == 0) |
29b0f896 | 8457 | { |
848930b2 | 8458 | fake_zero_displacement = 1; |
1a02d6b0 L |
8459 | if (i.disp_encoding == disp_encoding_32bit) |
8460 | i.types[op].bitfield.disp32 = 1; | |
8461 | else | |
8462 | i.types[op].bitfield.disp8 = 1; | |
29b0f896 AM |
8463 | } |
8464 | i.sib.scale = i.log2_scale_factor; | |
8465 | if (i.index_reg == 0) | |
8466 | { | |
260cd341 LC |
8467 | /* Only check for VSIB. */ |
8468 | gas_assert (i.tm.opcode_modifier.sib != VECSIB128 | |
8469 | && i.tm.opcode_modifier.sib != VECSIB256 | |
8470 | && i.tm.opcode_modifier.sib != VECSIB512); | |
8471 | ||
29b0f896 AM |
8472 | /* <disp>(%esp) becomes two byte modrm with no index |
8473 | register. We've already stored the code for esp | |
8474 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. | |
8475 | Any base register besides %esp will not use the | |
8476 | extra modrm byte. */ | |
8477 | i.sib.index = NO_INDEX_REGISTER; | |
29b0f896 | 8478 | } |
63112cd6 | 8479 | else if (!i.tm.opcode_modifier.sib) |
29b0f896 | 8480 | { |
e968fc9b | 8481 | if (i.index_reg->reg_num == RegIZ) |
db51cc60 L |
8482 | i.sib.index = NO_INDEX_REGISTER; |
8483 | else | |
8484 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
8485 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
8486 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
161a04f6 | 8487 | i.rex |= REX_X; |
29b0f896 | 8488 | } |
67a4f2b7 AO |
8489 | |
8490 | if (i.disp_operands | |
8491 | && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL | |
8492 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) | |
8493 | i.rm.mode = 0; | |
8494 | else | |
a501d77e L |
8495 | { |
8496 | if (!fake_zero_displacement | |
8497 | && !i.disp_operands | |
8498 | && i.disp_encoding) | |
8499 | { | |
8500 | fake_zero_displacement = 1; | |
8501 | if (i.disp_encoding == disp_encoding_8bit) | |
8502 | i.types[op].bitfield.disp8 = 1; | |
8503 | else | |
8504 | i.types[op].bitfield.disp32 = 1; | |
8505 | } | |
8506 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
8507 | } | |
29b0f896 | 8508 | } |
252b5132 | 8509 | |
29b0f896 AM |
8510 | if (fake_zero_displacement) |
8511 | { | |
8512 | /* Fakes a zero displacement assuming that i.types[op] | |
8513 | holds the correct displacement size. */ | |
8514 | expressionS *exp; | |
8515 | ||
9c2799c2 | 8516 | gas_assert (i.op[op].disps == 0); |
29b0f896 AM |
8517 | exp = &disp_expressions[i.disp_operands++]; |
8518 | i.op[op].disps = exp; | |
8519 | exp->X_op = O_constant; | |
8520 | exp->X_add_number = 0; | |
8521 | exp->X_add_symbol = (symbolS *) 0; | |
8522 | exp->X_op_symbol = (symbolS *) 0; | |
8523 | } | |
c0f3af97 L |
8524 | |
8525 | mem = op; | |
29b0f896 | 8526 | } |
c0f3af97 L |
8527 | else |
8528 | mem = ~0; | |
252b5132 | 8529 | |
8c43a48b | 8530 | if (i.tm.opcode_modifier.vexsources == XOP2SOURCES) |
5dd85c99 SP |
8531 | { |
8532 | if (operand_type_check (i.types[0], imm)) | |
8533 | i.vex.register_specifier = NULL; | |
8534 | else | |
8535 | { | |
8536 | /* VEX.vvvv encodes one of the sources when the first | |
8537 | operand is not an immediate. */ | |
1ef99a7b | 8538 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
8539 | i.vex.register_specifier = i.op[0].regs; |
8540 | else | |
8541 | i.vex.register_specifier = i.op[1].regs; | |
8542 | } | |
8543 | ||
8544 | /* Destination is a XMM register encoded in the ModRM.reg | |
8545 | and VEX.R bit. */ | |
8546 | i.rm.reg = i.op[2].regs->reg_num; | |
8547 | if ((i.op[2].regs->reg_flags & RegRex) != 0) | |
8548 | i.rex |= REX_R; | |
8549 | ||
8550 | /* ModRM.rm and VEX.B encodes the other source. */ | |
8551 | if (!i.mem_operands) | |
8552 | { | |
8553 | i.rm.mode = 3; | |
8554 | ||
1ef99a7b | 8555 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
8556 | i.rm.regmem = i.op[1].regs->reg_num; |
8557 | else | |
8558 | i.rm.regmem = i.op[0].regs->reg_num; | |
8559 | ||
8560 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
8561 | i.rex |= REX_B; | |
8562 | } | |
8563 | } | |
2426c15f | 8564 | else if (i.tm.opcode_modifier.vexvvvv == VEXLWP) |
f88c9eb0 SP |
8565 | { |
8566 | i.vex.register_specifier = i.op[2].regs; | |
8567 | if (!i.mem_operands) | |
8568 | { | |
8569 | i.rm.mode = 3; | |
8570 | i.rm.regmem = i.op[1].regs->reg_num; | |
8571 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
8572 | i.rex |= REX_B; | |
8573 | } | |
8574 | } | |
29b0f896 AM |
8575 | /* Fill in i.rm.reg or i.rm.regmem field with register operand |
8576 | (if any) based on i.tm.extension_opcode. Again, we must be | |
8577 | careful to make sure that segment/control/debug/test/MMX | |
8578 | registers are coded into the i.rm.reg field. */ | |
f88c9eb0 | 8579 | else if (i.reg_operands) |
29b0f896 | 8580 | { |
99018f42 | 8581 | unsigned int op; |
7ab9ffdd L |
8582 | unsigned int vex_reg = ~0; |
8583 | ||
8584 | for (op = 0; op < i.operands; op++) | |
921eafea L |
8585 | if (i.types[op].bitfield.class == Reg |
8586 | || i.types[op].bitfield.class == RegBND | |
8587 | || i.types[op].bitfield.class == RegMask | |
8588 | || i.types[op].bitfield.class == SReg | |
8589 | || i.types[op].bitfield.class == RegCR | |
8590 | || i.types[op].bitfield.class == RegDR | |
8591 | || i.types[op].bitfield.class == RegTR | |
8592 | || i.types[op].bitfield.class == RegSIMD | |
8593 | || i.types[op].bitfield.class == RegMMX) | |
8594 | break; | |
c0209578 | 8595 | |
7ab9ffdd L |
8596 | if (vex_3_sources) |
8597 | op = dest; | |
2426c15f | 8598 | else if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd L |
8599 | { |
8600 | /* For instructions with VexNDS, the register-only | |
8601 | source operand is encoded in VEX prefix. */ | |
8602 | gas_assert (mem != (unsigned int) ~0); | |
c0f3af97 | 8603 | |
7ab9ffdd | 8604 | if (op > mem) |
c0f3af97 | 8605 | { |
7ab9ffdd L |
8606 | vex_reg = op++; |
8607 | gas_assert (op < i.operands); | |
c0f3af97 L |
8608 | } |
8609 | else | |
c0f3af97 | 8610 | { |
f12dc422 L |
8611 | /* Check register-only source operand when two source |
8612 | operands are swapped. */ | |
8613 | if (!i.tm.operand_types[op].bitfield.baseindex | |
8614 | && i.tm.operand_types[op + 1].bitfield.baseindex) | |
8615 | { | |
8616 | vex_reg = op; | |
8617 | op += 2; | |
8618 | gas_assert (mem == (vex_reg + 1) | |
8619 | && op < i.operands); | |
8620 | } | |
8621 | else | |
8622 | { | |
8623 | vex_reg = op + 1; | |
8624 | gas_assert (vex_reg < i.operands); | |
8625 | } | |
c0f3af97 | 8626 | } |
7ab9ffdd | 8627 | } |
2426c15f | 8628 | else if (i.tm.opcode_modifier.vexvvvv == VEXNDD) |
7ab9ffdd | 8629 | { |
f12dc422 | 8630 | /* For instructions with VexNDD, the register destination |
7ab9ffdd | 8631 | is encoded in VEX prefix. */ |
f12dc422 L |
8632 | if (i.mem_operands == 0) |
8633 | { | |
8634 | /* There is no memory operand. */ | |
8635 | gas_assert ((op + 2) == i.operands); | |
8636 | vex_reg = op + 1; | |
8637 | } | |
8638 | else | |
8d63c93e | 8639 | { |
ed438a93 JB |
8640 | /* There are only 2 non-immediate operands. */ |
8641 | gas_assert (op < i.imm_operands + 2 | |
8642 | && i.operands == i.imm_operands + 2); | |
8643 | vex_reg = i.imm_operands + 1; | |
f12dc422 | 8644 | } |
7ab9ffdd L |
8645 | } |
8646 | else | |
8647 | gas_assert (op < i.operands); | |
99018f42 | 8648 | |
7ab9ffdd L |
8649 | if (vex_reg != (unsigned int) ~0) |
8650 | { | |
f12dc422 | 8651 | i386_operand_type *type = &i.tm.operand_types[vex_reg]; |
7ab9ffdd | 8652 | |
bab6aec1 | 8653 | if ((type->bitfield.class != Reg |
dc821c5f | 8654 | || (!type->bitfield.dword && !type->bitfield.qword)) |
3528c362 | 8655 | && type->bitfield.class != RegSIMD |
43234a1e | 8656 | && !operand_type_equal (type, ®mask)) |
7ab9ffdd | 8657 | abort (); |
f88c9eb0 | 8658 | |
7ab9ffdd L |
8659 | i.vex.register_specifier = i.op[vex_reg].regs; |
8660 | } | |
8661 | ||
1b9f0c97 L |
8662 | /* Don't set OP operand twice. */ |
8663 | if (vex_reg != op) | |
7ab9ffdd | 8664 | { |
1b9f0c97 L |
8665 | /* If there is an extension opcode to put here, the |
8666 | register number must be put into the regmem field. */ | |
8667 | if (i.tm.extension_opcode != None) | |
8668 | { | |
8669 | i.rm.regmem = i.op[op].regs->reg_num; | |
a5aeccd9 JB |
8670 | set_rex_vrex (i.op[op].regs, REX_B, |
8671 | i.tm.opcode_modifier.sse2avx); | |
1b9f0c97 L |
8672 | } |
8673 | else | |
8674 | { | |
8675 | i.rm.reg = i.op[op].regs->reg_num; | |
a5aeccd9 JB |
8676 | set_rex_vrex (i.op[op].regs, REX_R, |
8677 | i.tm.opcode_modifier.sse2avx); | |
1b9f0c97 | 8678 | } |
7ab9ffdd | 8679 | } |
252b5132 | 8680 | |
29b0f896 AM |
8681 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we |
8682 | must set it to 3 to indicate this is a register operand | |
8683 | in the regmem field. */ | |
8684 | if (!i.mem_operands) | |
8685 | i.rm.mode = 3; | |
8686 | } | |
252b5132 | 8687 | |
29b0f896 | 8688 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
c1e679ec | 8689 | if (i.tm.extension_opcode != None) |
29b0f896 AM |
8690 | i.rm.reg = i.tm.extension_opcode; |
8691 | } | |
8692 | return default_seg; | |
8693 | } | |
252b5132 | 8694 | |
48ef937e JB |
8695 | static INLINE void |
8696 | frag_opcode_byte (unsigned char byte) | |
8697 | { | |
8698 | if (now_seg != absolute_section) | |
8699 | FRAG_APPEND_1_CHAR (byte); | |
8700 | else | |
8701 | ++abs_section_offset; | |
8702 | } | |
8703 | ||
376cd056 JB |
8704 | static unsigned int |
8705 | flip_code16 (unsigned int code16) | |
8706 | { | |
8707 | gas_assert (i.tm.operands == 1); | |
8708 | ||
8709 | return !(i.prefix[REX_PREFIX] & REX_W) | |
8710 | && (code16 ? i.tm.operand_types[0].bitfield.disp32 | |
8711 | || i.tm.operand_types[0].bitfield.disp32s | |
8712 | : i.tm.operand_types[0].bitfield.disp16) | |
8713 | ? CODE16 : 0; | |
8714 | } | |
8715 | ||
29b0f896 | 8716 | static void |
e3bb37b5 | 8717 | output_branch (void) |
29b0f896 AM |
8718 | { |
8719 | char *p; | |
f8a5c266 | 8720 | int size; |
29b0f896 AM |
8721 | int code16; |
8722 | int prefix; | |
8723 | relax_substateT subtype; | |
8724 | symbolS *sym; | |
8725 | offsetT off; | |
8726 | ||
48ef937e JB |
8727 | if (now_seg == absolute_section) |
8728 | { | |
8729 | as_bad (_("relaxable branches not supported in absolute section")); | |
8730 | return; | |
8731 | } | |
8732 | ||
f8a5c266 | 8733 | code16 = flag_code == CODE_16BIT ? CODE16 : 0; |
a501d77e | 8734 | size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL; |
29b0f896 AM |
8735 | |
8736 | prefix = 0; | |
8737 | if (i.prefix[DATA_PREFIX] != 0) | |
252b5132 | 8738 | { |
29b0f896 AM |
8739 | prefix = 1; |
8740 | i.prefixes -= 1; | |
376cd056 | 8741 | code16 ^= flip_code16(code16); |
252b5132 | 8742 | } |
29b0f896 AM |
8743 | /* Pentium4 branch hints. */ |
8744 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
8745 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2f66722d | 8746 | { |
29b0f896 AM |
8747 | prefix++; |
8748 | i.prefixes--; | |
8749 | } | |
8750 | if (i.prefix[REX_PREFIX] != 0) | |
8751 | { | |
8752 | prefix++; | |
8753 | i.prefixes--; | |
2f66722d AM |
8754 | } |
8755 | ||
7e8b059b L |
8756 | /* BND prefixed jump. */ |
8757 | if (i.prefix[BND_PREFIX] != 0) | |
8758 | { | |
6cb0a70e JB |
8759 | prefix++; |
8760 | i.prefixes--; | |
7e8b059b L |
8761 | } |
8762 | ||
f2810fe0 JB |
8763 | if (i.prefixes != 0) |
8764 | as_warn (_("skipping prefixes on `%s'"), i.tm.name); | |
29b0f896 AM |
8765 | |
8766 | /* It's always a symbol; End frag & setup for relax. | |
8767 | Make sure there is enough room in this frag for the largest | |
8768 | instruction we may generate in md_convert_frag. This is 2 | |
8769 | bytes for the opcode and room for the prefix and largest | |
8770 | displacement. */ | |
8771 | frag_grow (prefix + 2 + 4); | |
8772 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
8773 | p = frag_more (prefix + 1); | |
8774 | if (i.prefix[DATA_PREFIX] != 0) | |
8775 | *p++ = DATA_PREFIX_OPCODE; | |
8776 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE | |
8777 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
8778 | *p++ = i.prefix[SEG_PREFIX]; | |
6cb0a70e JB |
8779 | if (i.prefix[BND_PREFIX] != 0) |
8780 | *p++ = BND_PREFIX_OPCODE; | |
29b0f896 AM |
8781 | if (i.prefix[REX_PREFIX] != 0) |
8782 | *p++ = i.prefix[REX_PREFIX]; | |
8783 | *p = i.tm.base_opcode; | |
8784 | ||
8785 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
f8a5c266 | 8786 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size); |
40fb9820 | 8787 | else if (cpu_arch_flags.bitfield.cpui386) |
f8a5c266 | 8788 | subtype = ENCODE_RELAX_STATE (COND_JUMP, size); |
29b0f896 | 8789 | else |
f8a5c266 | 8790 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, size); |
29b0f896 | 8791 | subtype |= code16; |
3e73aa7c | 8792 | |
29b0f896 AM |
8793 | sym = i.op[0].disps->X_add_symbol; |
8794 | off = i.op[0].disps->X_add_number; | |
3e73aa7c | 8795 | |
29b0f896 AM |
8796 | if (i.op[0].disps->X_op != O_constant |
8797 | && i.op[0].disps->X_op != O_symbol) | |
3e73aa7c | 8798 | { |
29b0f896 AM |
8799 | /* Handle complex expressions. */ |
8800 | sym = make_expr_symbol (i.op[0].disps); | |
8801 | off = 0; | |
8802 | } | |
3e73aa7c | 8803 | |
29b0f896 AM |
8804 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
8805 | Pass reloc in fr_var. */ | |
d258b828 | 8806 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); |
29b0f896 | 8807 | } |
3e73aa7c | 8808 | |
bd7ab16b L |
8809 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8810 | /* Return TRUE iff PLT32 relocation should be used for branching to | |
8811 | symbol S. */ | |
8812 | ||
5b7c81bd | 8813 | static bool |
bd7ab16b L |
8814 | need_plt32_p (symbolS *s) |
8815 | { | |
8816 | /* PLT32 relocation is ELF only. */ | |
8817 | if (!IS_ELF) | |
5b7c81bd | 8818 | return false; |
bd7ab16b | 8819 | |
a5def729 RO |
8820 | #ifdef TE_SOLARIS |
8821 | /* Don't emit PLT32 relocation on Solaris: neither native linker nor | |
8822 | krtld support it. */ | |
5b7c81bd | 8823 | return false; |
a5def729 RO |
8824 | #endif |
8825 | ||
bd7ab16b L |
8826 | /* Since there is no need to prepare for PLT branch on x86-64, we |
8827 | can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can | |
8828 | be used as a marker for 32-bit PC-relative branches. */ | |
8829 | if (!object_64bit) | |
5b7c81bd | 8830 | return false; |
bd7ab16b | 8831 | |
44365e88 | 8832 | if (s == NULL) |
5b7c81bd | 8833 | return false; |
44365e88 | 8834 | |
bd7ab16b L |
8835 | /* Weak or undefined symbol need PLT32 relocation. */ |
8836 | if (S_IS_WEAK (s) || !S_IS_DEFINED (s)) | |
5b7c81bd | 8837 | return true; |
bd7ab16b L |
8838 | |
8839 | /* Non-global symbol doesn't need PLT32 relocation. */ | |
8840 | if (! S_IS_EXTERNAL (s)) | |
5b7c81bd | 8841 | return false; |
bd7ab16b L |
8842 | |
8843 | /* Other global symbols need PLT32 relocation. NB: Symbol with | |
8844 | non-default visibilities are treated as normal global symbol | |
8845 | so that PLT32 relocation can be used as a marker for 32-bit | |
8846 | PC-relative branches. It is useful for linker relaxation. */ | |
5b7c81bd | 8847 | return true; |
bd7ab16b L |
8848 | } |
8849 | #endif | |
8850 | ||
29b0f896 | 8851 | static void |
e3bb37b5 | 8852 | output_jump (void) |
29b0f896 AM |
8853 | { |
8854 | char *p; | |
8855 | int size; | |
3e02c1cc | 8856 | fixS *fixP; |
bd7ab16b | 8857 | bfd_reloc_code_real_type jump_reloc = i.reloc[0]; |
29b0f896 | 8858 | |
0cfa3eb3 | 8859 | if (i.tm.opcode_modifier.jump == JUMP_BYTE) |
29b0f896 AM |
8860 | { |
8861 | /* This is a loop or jecxz type instruction. */ | |
8862 | size = 1; | |
8863 | if (i.prefix[ADDR_PREFIX] != 0) | |
8864 | { | |
48ef937e | 8865 | frag_opcode_byte (ADDR_PREFIX_OPCODE); |
29b0f896 AM |
8866 | i.prefixes -= 1; |
8867 | } | |
8868 | /* Pentium4 branch hints. */ | |
8869 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
8870 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
8871 | { | |
48ef937e | 8872 | frag_opcode_byte (i.prefix[SEG_PREFIX]); |
29b0f896 | 8873 | i.prefixes--; |
3e73aa7c JH |
8874 | } |
8875 | } | |
29b0f896 AM |
8876 | else |
8877 | { | |
8878 | int code16; | |
3e73aa7c | 8879 | |
29b0f896 AM |
8880 | code16 = 0; |
8881 | if (flag_code == CODE_16BIT) | |
8882 | code16 = CODE16; | |
3e73aa7c | 8883 | |
29b0f896 AM |
8884 | if (i.prefix[DATA_PREFIX] != 0) |
8885 | { | |
48ef937e | 8886 | frag_opcode_byte (DATA_PREFIX_OPCODE); |
29b0f896 | 8887 | i.prefixes -= 1; |
376cd056 | 8888 | code16 ^= flip_code16(code16); |
29b0f896 | 8889 | } |
252b5132 | 8890 | |
29b0f896 AM |
8891 | size = 4; |
8892 | if (code16) | |
8893 | size = 2; | |
8894 | } | |
9fcc94b6 | 8895 | |
6cb0a70e JB |
8896 | /* BND prefixed jump. */ |
8897 | if (i.prefix[BND_PREFIX] != 0) | |
29b0f896 | 8898 | { |
48ef937e | 8899 | frag_opcode_byte (i.prefix[BND_PREFIX]); |
29b0f896 AM |
8900 | i.prefixes -= 1; |
8901 | } | |
252b5132 | 8902 | |
6cb0a70e | 8903 | if (i.prefix[REX_PREFIX] != 0) |
7e8b059b | 8904 | { |
48ef937e | 8905 | frag_opcode_byte (i.prefix[REX_PREFIX]); |
7e8b059b L |
8906 | i.prefixes -= 1; |
8907 | } | |
8908 | ||
f2810fe0 JB |
8909 | if (i.prefixes != 0) |
8910 | as_warn (_("skipping prefixes on `%s'"), i.tm.name); | |
e0890092 | 8911 | |
48ef937e JB |
8912 | if (now_seg == absolute_section) |
8913 | { | |
9a182d04 | 8914 | abs_section_offset += i.opcode_length + size; |
48ef937e JB |
8915 | return; |
8916 | } | |
8917 | ||
9a182d04 JB |
8918 | p = frag_more (i.opcode_length + size); |
8919 | switch (i.opcode_length) | |
42164a71 L |
8920 | { |
8921 | case 2: | |
8922 | *p++ = i.tm.base_opcode >> 8; | |
1a0670f3 | 8923 | /* Fall through. */ |
42164a71 L |
8924 | case 1: |
8925 | *p++ = i.tm.base_opcode; | |
8926 | break; | |
8927 | default: | |
8928 | abort (); | |
8929 | } | |
e0890092 | 8930 | |
bd7ab16b L |
8931 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8932 | if (size == 4 | |
8933 | && jump_reloc == NO_RELOC | |
8934 | && need_plt32_p (i.op[0].disps->X_add_symbol)) | |
8935 | jump_reloc = BFD_RELOC_X86_64_PLT32; | |
8936 | #endif | |
8937 | ||
8938 | jump_reloc = reloc (size, 1, 1, jump_reloc); | |
8939 | ||
3e02c1cc | 8940 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
bd7ab16b | 8941 | i.op[0].disps, 1, jump_reloc); |
3e02c1cc | 8942 | |
eb19308f JB |
8943 | /* All jumps handled here are signed, but don't unconditionally use a |
8944 | signed limit check for 32 and 16 bit jumps as we want to allow wrap | |
8945 | around at 4G (outside of 64-bit mode) and 64k (except for XBEGIN) | |
8946 | respectively. */ | |
8947 | switch (size) | |
8948 | { | |
8949 | case 1: | |
8950 | fixP->fx_signed = 1; | |
8951 | break; | |
8952 | ||
8953 | case 2: | |
8954 | if (i.tm.base_opcode == 0xc7f8) | |
8955 | fixP->fx_signed = 1; | |
8956 | break; | |
8957 | ||
8958 | case 4: | |
8959 | if (flag_code == CODE_64BIT) | |
8960 | fixP->fx_signed = 1; | |
8961 | break; | |
8962 | } | |
29b0f896 | 8963 | } |
e0890092 | 8964 | |
29b0f896 | 8965 | static void |
e3bb37b5 | 8966 | output_interseg_jump (void) |
29b0f896 AM |
8967 | { |
8968 | char *p; | |
8969 | int size; | |
8970 | int prefix; | |
8971 | int code16; | |
252b5132 | 8972 | |
29b0f896 AM |
8973 | code16 = 0; |
8974 | if (flag_code == CODE_16BIT) | |
8975 | code16 = CODE16; | |
a217f122 | 8976 | |
29b0f896 AM |
8977 | prefix = 0; |
8978 | if (i.prefix[DATA_PREFIX] != 0) | |
8979 | { | |
8980 | prefix = 1; | |
8981 | i.prefixes -= 1; | |
8982 | code16 ^= CODE16; | |
8983 | } | |
6cb0a70e JB |
8984 | |
8985 | gas_assert (!i.prefix[REX_PREFIX]); | |
252b5132 | 8986 | |
29b0f896 AM |
8987 | size = 4; |
8988 | if (code16) | |
8989 | size = 2; | |
252b5132 | 8990 | |
f2810fe0 JB |
8991 | if (i.prefixes != 0) |
8992 | as_warn (_("skipping prefixes on `%s'"), i.tm.name); | |
252b5132 | 8993 | |
48ef937e JB |
8994 | if (now_seg == absolute_section) |
8995 | { | |
8996 | abs_section_offset += prefix + 1 + 2 + size; | |
8997 | return; | |
8998 | } | |
8999 | ||
29b0f896 AM |
9000 | /* 1 opcode; 2 segment; offset */ |
9001 | p = frag_more (prefix + 1 + 2 + size); | |
3e73aa7c | 9002 | |
29b0f896 AM |
9003 | if (i.prefix[DATA_PREFIX] != 0) |
9004 | *p++ = DATA_PREFIX_OPCODE; | |
252b5132 | 9005 | |
29b0f896 AM |
9006 | if (i.prefix[REX_PREFIX] != 0) |
9007 | *p++ = i.prefix[REX_PREFIX]; | |
252b5132 | 9008 | |
29b0f896 AM |
9009 | *p++ = i.tm.base_opcode; |
9010 | if (i.op[1].imms->X_op == O_constant) | |
9011 | { | |
9012 | offsetT n = i.op[1].imms->X_add_number; | |
252b5132 | 9013 | |
29b0f896 AM |
9014 | if (size == 2 |
9015 | && !fits_in_unsigned_word (n) | |
9016 | && !fits_in_signed_word (n)) | |
9017 | { | |
9018 | as_bad (_("16-bit jump out of range")); | |
9019 | return; | |
9020 | } | |
9021 | md_number_to_chars (p, n, size); | |
9022 | } | |
9023 | else | |
9024 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
d258b828 | 9025 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); |
6d96a594 C |
9026 | |
9027 | p += size; | |
9028 | if (i.op[0].imms->X_op == O_constant) | |
9029 | md_number_to_chars (p, (valueT) i.op[0].imms->X_add_number, 2); | |
9030 | else | |
9031 | fix_new_exp (frag_now, p - frag_now->fr_literal, 2, | |
9032 | i.op[0].imms, 0, reloc (2, 0, 0, i.reloc[0])); | |
29b0f896 | 9033 | } |
a217f122 | 9034 | |
b4a3a7b4 L |
9035 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
9036 | void | |
9037 | x86_cleanup (void) | |
9038 | { | |
9039 | char *p; | |
9040 | asection *seg = now_seg; | |
9041 | subsegT subseg = now_subseg; | |
9042 | asection *sec; | |
9043 | unsigned int alignment, align_size_1; | |
9044 | unsigned int isa_1_descsz, feature_2_descsz, descsz; | |
9045 | unsigned int isa_1_descsz_raw, feature_2_descsz_raw; | |
9046 | unsigned int padding; | |
9047 | ||
1273b2f8 | 9048 | if (!IS_ELF || !x86_used_note) |
b4a3a7b4 L |
9049 | return; |
9050 | ||
b4a3a7b4 L |
9051 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X86; |
9052 | ||
9053 | /* The .note.gnu.property section layout: | |
9054 | ||
9055 | Field Length Contents | |
9056 | ---- ---- ---- | |
9057 | n_namsz 4 4 | |
9058 | n_descsz 4 The note descriptor size | |
9059 | n_type 4 NT_GNU_PROPERTY_TYPE_0 | |
9060 | n_name 4 "GNU" | |
9061 | n_desc n_descsz The program property array | |
9062 | .... .... .... | |
9063 | */ | |
9064 | ||
9065 | /* Create the .note.gnu.property section. */ | |
9066 | sec = subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME, 0); | |
fd361982 | 9067 | bfd_set_section_flags (sec, |
b4a3a7b4 L |
9068 | (SEC_ALLOC |
9069 | | SEC_LOAD | |
9070 | | SEC_DATA | |
9071 | | SEC_HAS_CONTENTS | |
9072 | | SEC_READONLY)); | |
9073 | ||
9074 | if (get_elf_backend_data (stdoutput)->s->elfclass == ELFCLASS64) | |
9075 | { | |
9076 | align_size_1 = 7; | |
9077 | alignment = 3; | |
9078 | } | |
9079 | else | |
9080 | { | |
9081 | align_size_1 = 3; | |
9082 | alignment = 2; | |
9083 | } | |
9084 | ||
fd361982 | 9085 | bfd_set_section_alignment (sec, alignment); |
b4a3a7b4 L |
9086 | elf_section_type (sec) = SHT_NOTE; |
9087 | ||
1273b2f8 L |
9088 | /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size |
9089 | + 4-byte data */ | |
9090 | isa_1_descsz_raw = 4 + 4 + 4; | |
9091 | /* Align GNU_PROPERTY_X86_ISA_1_USED. */ | |
9092 | isa_1_descsz = (isa_1_descsz_raw + align_size_1) & ~align_size_1; | |
b4a3a7b4 L |
9093 | |
9094 | feature_2_descsz_raw = isa_1_descsz; | |
9095 | /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size | |
1273b2f8 | 9096 | + 4-byte data */ |
b4a3a7b4 L |
9097 | feature_2_descsz_raw += 4 + 4 + 4; |
9098 | /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */ | |
9099 | feature_2_descsz = ((feature_2_descsz_raw + align_size_1) | |
9100 | & ~align_size_1); | |
9101 | ||
9102 | descsz = feature_2_descsz; | |
9103 | /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */ | |
9104 | p = frag_more (4 + 4 + 4 + 4 + descsz); | |
9105 | ||
9106 | /* Write n_namsz. */ | |
9107 | md_number_to_chars (p, (valueT) 4, 4); | |
9108 | ||
9109 | /* Write n_descsz. */ | |
9110 | md_number_to_chars (p + 4, (valueT) descsz, 4); | |
9111 | ||
9112 | /* Write n_type. */ | |
9113 | md_number_to_chars (p + 4 * 2, (valueT) NT_GNU_PROPERTY_TYPE_0, 4); | |
9114 | ||
9115 | /* Write n_name. */ | |
9116 | memcpy (p + 4 * 3, "GNU", 4); | |
9117 | ||
1273b2f8 L |
9118 | /* Write 4-byte type. */ |
9119 | md_number_to_chars (p + 4 * 4, | |
9120 | (valueT) GNU_PROPERTY_X86_ISA_1_USED, 4); | |
b4a3a7b4 | 9121 | |
1273b2f8 L |
9122 | /* Write 4-byte data size. */ |
9123 | md_number_to_chars (p + 4 * 5, (valueT) 4, 4); | |
b4a3a7b4 | 9124 | |
1273b2f8 L |
9125 | /* Write 4-byte data. */ |
9126 | md_number_to_chars (p + 4 * 6, (valueT) x86_isa_1_used, 4); | |
b4a3a7b4 | 9127 | |
1273b2f8 L |
9128 | /* Zero out paddings. */ |
9129 | padding = isa_1_descsz - isa_1_descsz_raw; | |
9130 | if (padding) | |
9131 | memset (p + 4 * 7, 0, padding); | |
b4a3a7b4 L |
9132 | |
9133 | /* Write 4-byte type. */ | |
9134 | md_number_to_chars (p + isa_1_descsz + 4 * 4, | |
9135 | (valueT) GNU_PROPERTY_X86_FEATURE_2_USED, 4); | |
9136 | ||
9137 | /* Write 4-byte data size. */ | |
9138 | md_number_to_chars (p + isa_1_descsz + 4 * 5, (valueT) 4, 4); | |
9139 | ||
9140 | /* Write 4-byte data. */ | |
9141 | md_number_to_chars (p + isa_1_descsz + 4 * 6, | |
9142 | (valueT) x86_feature_2_used, 4); | |
9143 | ||
9144 | /* Zero out paddings. */ | |
9145 | padding = feature_2_descsz - feature_2_descsz_raw; | |
9146 | if (padding) | |
9147 | memset (p + isa_1_descsz + 4 * 7, 0, padding); | |
9148 | ||
9149 | /* We probably can't restore the current segment, for there likely | |
9150 | isn't one yet... */ | |
9151 | if (seg && subseg) | |
9152 | subseg_set (seg, subseg); | |
9153 | } | |
9154 | #endif | |
9155 | ||
9c33702b JB |
9156 | static unsigned int |
9157 | encoding_length (const fragS *start_frag, offsetT start_off, | |
9158 | const char *frag_now_ptr) | |
9159 | { | |
9160 | unsigned int len = 0; | |
9161 | ||
9162 | if (start_frag != frag_now) | |
9163 | { | |
9164 | const fragS *fr = start_frag; | |
9165 | ||
9166 | do { | |
9167 | len += fr->fr_fix; | |
9168 | fr = fr->fr_next; | |
9169 | } while (fr && fr != frag_now); | |
9170 | } | |
9171 | ||
9172 | return len - start_off + (frag_now_ptr - frag_now->fr_literal); | |
9173 | } | |
9174 | ||
e379e5f3 | 9175 | /* Return 1 for test, and, cmp, add, sub, inc and dec which may |
79d72f45 HL |
9176 | be macro-fused with conditional jumps. |
9177 | NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address, | |
9178 | or is one of the following format: | |
9179 | ||
9180 | cmp m, imm | |
9181 | add m, imm | |
9182 | sub m, imm | |
9183 | test m, imm | |
9184 | and m, imm | |
9185 | inc m | |
9186 | dec m | |
9187 | ||
9188 | it is unfusible. */ | |
e379e5f3 L |
9189 | |
9190 | static int | |
79d72f45 | 9191 | maybe_fused_with_jcc_p (enum mf_cmp_kind* mf_cmp_p) |
e379e5f3 L |
9192 | { |
9193 | /* No RIP address. */ | |
9194 | if (i.base_reg && i.base_reg->reg_num == RegIP) | |
9195 | return 0; | |
9196 | ||
389d00a5 JB |
9197 | /* No opcodes outside of base encoding space. */ |
9198 | if (i.tm.opcode_modifier.opcodespace != SPACE_BASE) | |
e379e5f3 L |
9199 | return 0; |
9200 | ||
79d72f45 HL |
9201 | /* add, sub without add/sub m, imm. */ |
9202 | if (i.tm.base_opcode <= 5 | |
e379e5f3 L |
9203 | || (i.tm.base_opcode >= 0x28 && i.tm.base_opcode <= 0x2d) |
9204 | || ((i.tm.base_opcode | 3) == 0x83 | |
79d72f45 | 9205 | && (i.tm.extension_opcode == 0x5 |
e379e5f3 | 9206 | || i.tm.extension_opcode == 0x0))) |
79d72f45 HL |
9207 | { |
9208 | *mf_cmp_p = mf_cmp_alu_cmp; | |
9209 | return !(i.mem_operands && i.imm_operands); | |
9210 | } | |
e379e5f3 | 9211 | |
79d72f45 HL |
9212 | /* and without and m, imm. */ |
9213 | if ((i.tm.base_opcode >= 0x20 && i.tm.base_opcode <= 0x25) | |
9214 | || ((i.tm.base_opcode | 3) == 0x83 | |
9215 | && i.tm.extension_opcode == 0x4)) | |
9216 | { | |
9217 | *mf_cmp_p = mf_cmp_test_and; | |
9218 | return !(i.mem_operands && i.imm_operands); | |
9219 | } | |
9220 | ||
9221 | /* test without test m imm. */ | |
e379e5f3 L |
9222 | if ((i.tm.base_opcode | 1) == 0x85 |
9223 | || (i.tm.base_opcode | 1) == 0xa9 | |
9224 | || ((i.tm.base_opcode | 1) == 0xf7 | |
79d72f45 HL |
9225 | && i.tm.extension_opcode == 0)) |
9226 | { | |
9227 | *mf_cmp_p = mf_cmp_test_and; | |
9228 | return !(i.mem_operands && i.imm_operands); | |
9229 | } | |
9230 | ||
9231 | /* cmp without cmp m, imm. */ | |
9232 | if ((i.tm.base_opcode >= 0x38 && i.tm.base_opcode <= 0x3d) | |
e379e5f3 L |
9233 | || ((i.tm.base_opcode | 3) == 0x83 |
9234 | && (i.tm.extension_opcode == 0x7))) | |
79d72f45 HL |
9235 | { |
9236 | *mf_cmp_p = mf_cmp_alu_cmp; | |
9237 | return !(i.mem_operands && i.imm_operands); | |
9238 | } | |
e379e5f3 | 9239 | |
79d72f45 | 9240 | /* inc, dec without inc/dec m. */ |
e379e5f3 L |
9241 | if ((i.tm.cpu_flags.bitfield.cpuno64 |
9242 | && (i.tm.base_opcode | 0xf) == 0x4f) | |
9243 | || ((i.tm.base_opcode | 1) == 0xff | |
9244 | && i.tm.extension_opcode <= 0x1)) | |
79d72f45 HL |
9245 | { |
9246 | *mf_cmp_p = mf_cmp_incdec; | |
9247 | return !i.mem_operands; | |
9248 | } | |
e379e5f3 L |
9249 | |
9250 | return 0; | |
9251 | } | |
9252 | ||
9253 | /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */ | |
9254 | ||
9255 | static int | |
79d72f45 | 9256 | add_fused_jcc_padding_frag_p (enum mf_cmp_kind* mf_cmp_p) |
e379e5f3 L |
9257 | { |
9258 | /* NB: Don't work with COND_JUMP86 without i386. */ | |
9259 | if (!align_branch_power | |
9260 | || now_seg == absolute_section | |
9261 | || !cpu_arch_flags.bitfield.cpui386 | |
9262 | || !(align_branch & align_branch_fused_bit)) | |
9263 | return 0; | |
9264 | ||
79d72f45 | 9265 | if (maybe_fused_with_jcc_p (mf_cmp_p)) |
e379e5f3 L |
9266 | { |
9267 | if (last_insn.kind == last_insn_other | |
9268 | || last_insn.seg != now_seg) | |
9269 | return 1; | |
9270 | if (flag_debug) | |
9271 | as_warn_where (last_insn.file, last_insn.line, | |
9272 | _("`%s` skips -malign-branch-boundary on `%s`"), | |
9273 | last_insn.name, i.tm.name); | |
9274 | } | |
9275 | ||
9276 | return 0; | |
9277 | } | |
9278 | ||
9279 | /* Return 1 if a BRANCH_PREFIX frag should be generated. */ | |
9280 | ||
9281 | static int | |
9282 | add_branch_prefix_frag_p (void) | |
9283 | { | |
9284 | /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix | |
9285 | to PadLock instructions since they include prefixes in opcode. */ | |
9286 | if (!align_branch_power | |
9287 | || !align_branch_prefix_size | |
9288 | || now_seg == absolute_section | |
9289 | || i.tm.cpu_flags.bitfield.cpupadlock | |
9290 | || !cpu_arch_flags.bitfield.cpui386) | |
9291 | return 0; | |
9292 | ||
9293 | /* Don't add prefix if it is a prefix or there is no operand in case | |
9294 | that segment prefix is special. */ | |
9295 | if (!i.operands || i.tm.opcode_modifier.isprefix) | |
9296 | return 0; | |
9297 | ||
9298 | if (last_insn.kind == last_insn_other | |
9299 | || last_insn.seg != now_seg) | |
9300 | return 1; | |
9301 | ||
9302 | if (flag_debug) | |
9303 | as_warn_where (last_insn.file, last_insn.line, | |
9304 | _("`%s` skips -malign-branch-boundary on `%s`"), | |
9305 | last_insn.name, i.tm.name); | |
9306 | ||
9307 | return 0; | |
9308 | } | |
9309 | ||
9310 | /* Return 1 if a BRANCH_PADDING frag should be generated. */ | |
9311 | ||
9312 | static int | |
79d72f45 HL |
9313 | add_branch_padding_frag_p (enum align_branch_kind *branch_p, |
9314 | enum mf_jcc_kind *mf_jcc_p) | |
e379e5f3 L |
9315 | { |
9316 | int add_padding; | |
9317 | ||
9318 | /* NB: Don't work with COND_JUMP86 without i386. */ | |
9319 | if (!align_branch_power | |
9320 | || now_seg == absolute_section | |
389d00a5 JB |
9321 | || !cpu_arch_flags.bitfield.cpui386 |
9322 | || i.tm.opcode_modifier.opcodespace != SPACE_BASE) | |
e379e5f3 L |
9323 | return 0; |
9324 | ||
9325 | add_padding = 0; | |
9326 | ||
9327 | /* Check for jcc and direct jmp. */ | |
9328 | if (i.tm.opcode_modifier.jump == JUMP) | |
9329 | { | |
9330 | if (i.tm.base_opcode == JUMP_PC_RELATIVE) | |
9331 | { | |
9332 | *branch_p = align_branch_jmp; | |
9333 | add_padding = align_branch & align_branch_jmp_bit; | |
9334 | } | |
9335 | else | |
9336 | { | |
79d72f45 HL |
9337 | /* Because J<cc> and JN<cc> share same group in macro-fusible table, |
9338 | igore the lowest bit. */ | |
9339 | *mf_jcc_p = (i.tm.base_opcode & 0x0e) >> 1; | |
e379e5f3 L |
9340 | *branch_p = align_branch_jcc; |
9341 | if ((align_branch & align_branch_jcc_bit)) | |
9342 | add_padding = 1; | |
9343 | } | |
9344 | } | |
e379e5f3 L |
9345 | else if ((i.tm.base_opcode | 1) == 0xc3) |
9346 | { | |
9347 | /* Near ret. */ | |
9348 | *branch_p = align_branch_ret; | |
9349 | if ((align_branch & align_branch_ret_bit)) | |
9350 | add_padding = 1; | |
9351 | } | |
9352 | else | |
9353 | { | |
9354 | /* Check for indirect jmp, direct and indirect calls. */ | |
9355 | if (i.tm.base_opcode == 0xe8) | |
9356 | { | |
9357 | /* Direct call. */ | |
9358 | *branch_p = align_branch_call; | |
9359 | if ((align_branch & align_branch_call_bit)) | |
9360 | add_padding = 1; | |
9361 | } | |
9362 | else if (i.tm.base_opcode == 0xff | |
9363 | && (i.tm.extension_opcode == 2 | |
9364 | || i.tm.extension_opcode == 4)) | |
9365 | { | |
9366 | /* Indirect call and jmp. */ | |
9367 | *branch_p = align_branch_indirect; | |
9368 | if ((align_branch & align_branch_indirect_bit)) | |
9369 | add_padding = 1; | |
9370 | } | |
9371 | ||
9372 | if (add_padding | |
9373 | && i.disp_operands | |
9374 | && tls_get_addr | |
9375 | && (i.op[0].disps->X_op == O_symbol | |
9376 | || (i.op[0].disps->X_op == O_subtract | |
9377 | && i.op[0].disps->X_op_symbol == GOT_symbol))) | |
9378 | { | |
9379 | symbolS *s = i.op[0].disps->X_add_symbol; | |
9380 | /* No padding to call to global or undefined tls_get_addr. */ | |
9381 | if ((S_IS_EXTERNAL (s) || !S_IS_DEFINED (s)) | |
9382 | && strcmp (S_GET_NAME (s), tls_get_addr) == 0) | |
9383 | return 0; | |
9384 | } | |
9385 | } | |
9386 | ||
9387 | if (add_padding | |
9388 | && last_insn.kind != last_insn_other | |
9389 | && last_insn.seg == now_seg) | |
9390 | { | |
9391 | if (flag_debug) | |
9392 | as_warn_where (last_insn.file, last_insn.line, | |
9393 | _("`%s` skips -malign-branch-boundary on `%s`"), | |
9394 | last_insn.name, i.tm.name); | |
9395 | return 0; | |
9396 | } | |
9397 | ||
9398 | return add_padding; | |
9399 | } | |
9400 | ||
29b0f896 | 9401 | static void |
e3bb37b5 | 9402 | output_insn (void) |
29b0f896 | 9403 | { |
2bbd9c25 JJ |
9404 | fragS *insn_start_frag; |
9405 | offsetT insn_start_off; | |
e379e5f3 L |
9406 | fragS *fragP = NULL; |
9407 | enum align_branch_kind branch = align_branch_none; | |
79d72f45 HL |
9408 | /* The initializer is arbitrary just to avoid uninitialized error. |
9409 | it's actually either assigned in add_branch_padding_frag_p | |
9410 | or never be used. */ | |
9411 | enum mf_jcc_kind mf_jcc = mf_jcc_jo; | |
2bbd9c25 | 9412 | |
b4a3a7b4 | 9413 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
48ef937e | 9414 | if (IS_ELF && x86_used_note && now_seg != absolute_section) |
b4a3a7b4 | 9415 | { |
32930e4e L |
9416 | if ((i.xstate & xstate_tmm) == xstate_tmm |
9417 | || i.tm.cpu_flags.bitfield.cpuamx_tile) | |
9418 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_TMM; | |
9419 | ||
b4a3a7b4 L |
9420 | if (i.tm.cpu_flags.bitfield.cpu8087 |
9421 | || i.tm.cpu_flags.bitfield.cpu287 | |
9422 | || i.tm.cpu_flags.bitfield.cpu387 | |
9423 | || i.tm.cpu_flags.bitfield.cpu687 | |
9424 | || i.tm.cpu_flags.bitfield.cpufisttp) | |
9425 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X87; | |
014d61ea | 9426 | |
921eafea | 9427 | if ((i.xstate & xstate_mmx) |
389d00a5 JB |
9428 | || (i.tm.opcode_modifier.opcodespace == SPACE_0F |
9429 | && !is_any_vex_encoding (&i.tm) | |
9430 | && (i.tm.base_opcode == 0x77 /* emms */ | |
9431 | || i.tm.base_opcode == 0x0e /* femms */))) | |
b4a3a7b4 | 9432 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MMX; |
014d61ea | 9433 | |
32930e4e L |
9434 | if (i.index_reg) |
9435 | { | |
9436 | if (i.index_reg->reg_type.bitfield.zmmword) | |
9437 | i.xstate |= xstate_zmm; | |
9438 | else if (i.index_reg->reg_type.bitfield.ymmword) | |
9439 | i.xstate |= xstate_ymm; | |
9440 | else if (i.index_reg->reg_type.bitfield.xmmword) | |
9441 | i.xstate |= xstate_xmm; | |
9442 | } | |
014d61ea JB |
9443 | |
9444 | /* vzeroall / vzeroupper */ | |
9445 | if (i.tm.base_opcode == 0x77 && i.tm.cpu_flags.bitfield.cpuavx) | |
9446 | i.xstate |= xstate_ymm; | |
9447 | ||
c4694f17 | 9448 | if ((i.xstate & xstate_xmm) |
389d00a5 JB |
9449 | /* ldmxcsr / stmxcsr / vldmxcsr / vstmxcsr */ |
9450 | || (i.tm.base_opcode == 0xae | |
9451 | && (i.tm.cpu_flags.bitfield.cpusse | |
9452 | || i.tm.cpu_flags.bitfield.cpuavx)) | |
c4694f17 TG |
9453 | || i.tm.cpu_flags.bitfield.cpuwidekl |
9454 | || i.tm.cpu_flags.bitfield.cpukl) | |
b4a3a7b4 | 9455 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XMM; |
014d61ea | 9456 | |
921eafea | 9457 | if ((i.xstate & xstate_ymm) == xstate_ymm) |
b4a3a7b4 | 9458 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_YMM; |
921eafea | 9459 | if ((i.xstate & xstate_zmm) == xstate_zmm) |
b4a3a7b4 | 9460 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_ZMM; |
6225c532 | 9461 | if (i.mask.reg || (i.xstate & xstate_mask) == xstate_mask) |
32930e4e | 9462 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MASK; |
b4a3a7b4 L |
9463 | if (i.tm.cpu_flags.bitfield.cpufxsr) |
9464 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_FXSR; | |
9465 | if (i.tm.cpu_flags.bitfield.cpuxsave) | |
9466 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVE; | |
9467 | if (i.tm.cpu_flags.bitfield.cpuxsaveopt) | |
9468 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT; | |
9469 | if (i.tm.cpu_flags.bitfield.cpuxsavec) | |
9470 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEC; | |
b0ab0693 L |
9471 | |
9472 | if (x86_feature_2_used | |
9473 | || i.tm.cpu_flags.bitfield.cpucmov | |
9474 | || i.tm.cpu_flags.bitfield.cpusyscall | |
389d00a5 JB |
9475 | || (i.tm.opcode_modifier.opcodespace == SPACE_0F |
9476 | && i.tm.base_opcode == 0xc7 | |
70e95837 | 9477 | && i.tm.opcode_modifier.opcodeprefix == PREFIX_NONE |
b0ab0693 L |
9478 | && i.tm.extension_opcode == 1) /* cmpxchg8b */) |
9479 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_BASELINE; | |
9480 | if (i.tm.cpu_flags.bitfield.cpusse3 | |
9481 | || i.tm.cpu_flags.bitfield.cpussse3 | |
9482 | || i.tm.cpu_flags.bitfield.cpusse4_1 | |
9483 | || i.tm.cpu_flags.bitfield.cpusse4_2 | |
9484 | || i.tm.cpu_flags.bitfield.cpucx16 | |
9485 | || i.tm.cpu_flags.bitfield.cpupopcnt | |
9486 | /* LAHF-SAHF insns in 64-bit mode. */ | |
9487 | || (flag_code == CODE_64BIT | |
35648716 JB |
9488 | && (i.tm.base_opcode | 1) == 0x9f |
9489 | && i.tm.opcode_modifier.opcodespace == SPACE_BASE)) | |
b0ab0693 L |
9490 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_V2; |
9491 | if (i.tm.cpu_flags.bitfield.cpuavx | |
9492 | || i.tm.cpu_flags.bitfield.cpuavx2 | |
9493 | /* Any VEX encoded insns execpt for CpuAVX512F, CpuAVX512BW, | |
9494 | CpuAVX512DQ, LPW, TBM and AMX. */ | |
9495 | || (i.tm.opcode_modifier.vex | |
9496 | && !i.tm.cpu_flags.bitfield.cpuavx512f | |
9497 | && !i.tm.cpu_flags.bitfield.cpuavx512bw | |
9498 | && !i.tm.cpu_flags.bitfield.cpuavx512dq | |
9499 | && !i.tm.cpu_flags.bitfield.cpulwp | |
9500 | && !i.tm.cpu_flags.bitfield.cputbm | |
9501 | && !(x86_feature_2_used & GNU_PROPERTY_X86_FEATURE_2_TMM)) | |
9502 | || i.tm.cpu_flags.bitfield.cpuf16c | |
9503 | || i.tm.cpu_flags.bitfield.cpufma | |
9504 | || i.tm.cpu_flags.bitfield.cpulzcnt | |
9505 | || i.tm.cpu_flags.bitfield.cpumovbe | |
9506 | || i.tm.cpu_flags.bitfield.cpuxsaves | |
9507 | || (x86_feature_2_used | |
9508 | & (GNU_PROPERTY_X86_FEATURE_2_XSAVE | |
9509 | | GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT | |
9510 | | GNU_PROPERTY_X86_FEATURE_2_XSAVEC)) != 0) | |
9511 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_V3; | |
9512 | if (i.tm.cpu_flags.bitfield.cpuavx512f | |
9513 | || i.tm.cpu_flags.bitfield.cpuavx512bw | |
9514 | || i.tm.cpu_flags.bitfield.cpuavx512dq | |
9515 | || i.tm.cpu_flags.bitfield.cpuavx512vl | |
9516 | /* Any EVEX encoded insns except for AVX512ER, AVX512PF and | |
9517 | VNNIW. */ | |
9518 | || (i.tm.opcode_modifier.evex | |
9519 | && !i.tm.cpu_flags.bitfield.cpuavx512er | |
9520 | && !i.tm.cpu_flags.bitfield.cpuavx512pf | |
9521 | && !i.tm.cpu_flags.bitfield.cpuavx512_4vnniw)) | |
9522 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_V4; | |
b4a3a7b4 L |
9523 | } |
9524 | #endif | |
9525 | ||
29b0f896 AM |
9526 | /* Tie dwarf2 debug info to the address at the start of the insn. |
9527 | We can't do this after the insn has been output as the current | |
9528 | frag may have been closed off. eg. by frag_var. */ | |
9529 | dwarf2_emit_insn (0); | |
9530 | ||
2bbd9c25 JJ |
9531 | insn_start_frag = frag_now; |
9532 | insn_start_off = frag_now_fix (); | |
9533 | ||
79d72f45 | 9534 | if (add_branch_padding_frag_p (&branch, &mf_jcc)) |
e379e5f3 L |
9535 | { |
9536 | char *p; | |
9537 | /* Branch can be 8 bytes. Leave some room for prefixes. */ | |
9538 | unsigned int max_branch_padding_size = 14; | |
9539 | ||
9540 | /* Align section to boundary. */ | |
9541 | record_alignment (now_seg, align_branch_power); | |
9542 | ||
9543 | /* Make room for padding. */ | |
9544 | frag_grow (max_branch_padding_size); | |
9545 | ||
9546 | /* Start of the padding. */ | |
9547 | p = frag_more (0); | |
9548 | ||
9549 | fragP = frag_now; | |
9550 | ||
9551 | frag_var (rs_machine_dependent, max_branch_padding_size, 0, | |
9552 | ENCODE_RELAX_STATE (BRANCH_PADDING, 0), | |
9553 | NULL, 0, p); | |
9554 | ||
79d72f45 | 9555 | fragP->tc_frag_data.mf_type = mf_jcc; |
e379e5f3 L |
9556 | fragP->tc_frag_data.branch_type = branch; |
9557 | fragP->tc_frag_data.max_bytes = max_branch_padding_size; | |
9558 | } | |
9559 | ||
29b0f896 | 9560 | /* Output jumps. */ |
0cfa3eb3 | 9561 | if (i.tm.opcode_modifier.jump == JUMP) |
29b0f896 | 9562 | output_branch (); |
0cfa3eb3 JB |
9563 | else if (i.tm.opcode_modifier.jump == JUMP_BYTE |
9564 | || i.tm.opcode_modifier.jump == JUMP_DWORD) | |
29b0f896 | 9565 | output_jump (); |
0cfa3eb3 | 9566 | else if (i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT) |
29b0f896 AM |
9567 | output_interseg_jump (); |
9568 | else | |
9569 | { | |
9570 | /* Output normal instructions here. */ | |
9571 | char *p; | |
9572 | unsigned char *q; | |
47465058 | 9573 | unsigned int j; |
79d72f45 | 9574 | enum mf_cmp_kind mf_cmp; |
4dffcebc | 9575 | |
e4e00185 | 9576 | if (avoid_fence |
389d00a5 JB |
9577 | && (i.tm.base_opcode == 0xaee8 |
9578 | || i.tm.base_opcode == 0xaef0 | |
9579 | || i.tm.base_opcode == 0xaef8)) | |
48ef937e JB |
9580 | { |
9581 | /* Encode lfence, mfence, and sfence as | |
9582 | f0 83 04 24 00 lock addl $0x0, (%{re}sp). */ | |
9583 | if (now_seg != absolute_section) | |
9584 | { | |
9585 | offsetT val = 0x240483f0ULL; | |
9586 | ||
9587 | p = frag_more (5); | |
9588 | md_number_to_chars (p, val, 5); | |
9589 | } | |
9590 | else | |
9591 | abs_section_offset += 5; | |
9592 | return; | |
9593 | } | |
e4e00185 | 9594 | |
d022bddd IT |
9595 | /* Some processors fail on LOCK prefix. This options makes |
9596 | assembler ignore LOCK prefix and serves as a workaround. */ | |
9597 | if (omit_lock_prefix) | |
9598 | { | |
35648716 JB |
9599 | if (i.tm.base_opcode == LOCK_PREFIX_OPCODE |
9600 | && i.tm.opcode_modifier.isprefix) | |
d022bddd IT |
9601 | return; |
9602 | i.prefix[LOCK_PREFIX] = 0; | |
9603 | } | |
9604 | ||
e379e5f3 L |
9605 | if (branch) |
9606 | /* Skip if this is a branch. */ | |
9607 | ; | |
79d72f45 | 9608 | else if (add_fused_jcc_padding_frag_p (&mf_cmp)) |
e379e5f3 L |
9609 | { |
9610 | /* Make room for padding. */ | |
9611 | frag_grow (MAX_FUSED_JCC_PADDING_SIZE); | |
9612 | p = frag_more (0); | |
9613 | ||
9614 | fragP = frag_now; | |
9615 | ||
9616 | frag_var (rs_machine_dependent, MAX_FUSED_JCC_PADDING_SIZE, 0, | |
9617 | ENCODE_RELAX_STATE (FUSED_JCC_PADDING, 0), | |
9618 | NULL, 0, p); | |
9619 | ||
79d72f45 | 9620 | fragP->tc_frag_data.mf_type = mf_cmp; |
e379e5f3 L |
9621 | fragP->tc_frag_data.branch_type = align_branch_fused; |
9622 | fragP->tc_frag_data.max_bytes = MAX_FUSED_JCC_PADDING_SIZE; | |
9623 | } | |
9624 | else if (add_branch_prefix_frag_p ()) | |
9625 | { | |
9626 | unsigned int max_prefix_size = align_branch_prefix_size; | |
9627 | ||
9628 | /* Make room for padding. */ | |
9629 | frag_grow (max_prefix_size); | |
9630 | p = frag_more (0); | |
9631 | ||
9632 | fragP = frag_now; | |
9633 | ||
9634 | frag_var (rs_machine_dependent, max_prefix_size, 0, | |
9635 | ENCODE_RELAX_STATE (BRANCH_PREFIX, 0), | |
9636 | NULL, 0, p); | |
9637 | ||
9638 | fragP->tc_frag_data.max_bytes = max_prefix_size; | |
9639 | } | |
9640 | ||
43234a1e L |
9641 | /* Since the VEX/EVEX prefix contains the implicit prefix, we |
9642 | don't need the explicit prefix. */ | |
9643 | if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex) | |
bc4bd9ab | 9644 | { |
7b47a312 | 9645 | switch (i.tm.opcode_modifier.opcodeprefix) |
bc4bd9ab | 9646 | { |
7b47a312 L |
9647 | case PREFIX_0X66: |
9648 | add_prefix (0x66); | |
9649 | break; | |
9650 | case PREFIX_0XF2: | |
9651 | add_prefix (0xf2); | |
9652 | break; | |
9653 | case PREFIX_0XF3: | |
8b65b895 L |
9654 | if (!i.tm.cpu_flags.bitfield.cpupadlock |
9655 | || (i.prefix[REP_PREFIX] != 0xf3)) | |
9656 | add_prefix (0xf3); | |
c0f3af97 | 9657 | break; |
7b47a312 | 9658 | case PREFIX_NONE: |
9a182d04 | 9659 | switch (i.opcode_length) |
c0f3af97 | 9660 | { |
7b47a312 | 9661 | case 2: |
7b47a312 | 9662 | break; |
9a182d04 | 9663 | case 1: |
7b47a312 | 9664 | /* Check for pseudo prefixes. */ |
9a182d04 JB |
9665 | if (!i.tm.opcode_modifier.isprefix || i.tm.base_opcode) |
9666 | break; | |
7b47a312 L |
9667 | as_bad_where (insn_start_frag->fr_file, |
9668 | insn_start_frag->fr_line, | |
9669 | _("pseudo prefix without instruction")); | |
9670 | return; | |
9671 | default: | |
9672 | abort (); | |
4dffcebc | 9673 | } |
c0f3af97 | 9674 | break; |
c0f3af97 L |
9675 | default: |
9676 | abort (); | |
bc4bd9ab | 9677 | } |
c0f3af97 | 9678 | |
6d19a37a | 9679 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
cf61b747 L |
9680 | /* For x32, add a dummy REX_OPCODE prefix for mov/add with |
9681 | R_X86_64_GOTTPOFF relocation so that linker can safely | |
14470f07 L |
9682 | perform IE->LE optimization. A dummy REX_OPCODE prefix |
9683 | is also needed for lea with R_X86_64_GOTPC32_TLSDESC | |
9684 | relocation for GDesc -> IE/LE optimization. */ | |
cf61b747 L |
9685 | if (x86_elf_abi == X86_64_X32_ABI |
9686 | && i.operands == 2 | |
14470f07 L |
9687 | && (i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF |
9688 | || i.reloc[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC) | |
cf61b747 L |
9689 | && i.prefix[REX_PREFIX] == 0) |
9690 | add_prefix (REX_OPCODE); | |
6d19a37a | 9691 | #endif |
cf61b747 | 9692 | |
c0f3af97 L |
9693 | /* The prefix bytes. */ |
9694 | for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) | |
9695 | if (*q) | |
48ef937e | 9696 | frag_opcode_byte (*q); |
0f10071e | 9697 | } |
ae5c1c7b | 9698 | else |
c0f3af97 L |
9699 | { |
9700 | for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++) | |
9701 | if (*q) | |
9702 | switch (j) | |
9703 | { | |
c0f3af97 L |
9704 | case SEG_PREFIX: |
9705 | case ADDR_PREFIX: | |
48ef937e | 9706 | frag_opcode_byte (*q); |
c0f3af97 L |
9707 | break; |
9708 | default: | |
9709 | /* There should be no other prefixes for instructions | |
9710 | with VEX prefix. */ | |
9711 | abort (); | |
9712 | } | |
9713 | ||
43234a1e L |
9714 | /* For EVEX instructions i.vrex should become 0 after |
9715 | build_evex_prefix. For VEX instructions upper 16 registers | |
9716 | aren't available, so VREX should be 0. */ | |
9717 | if (i.vrex) | |
9718 | abort (); | |
c0f3af97 | 9719 | /* Now the VEX prefix. */ |
48ef937e JB |
9720 | if (now_seg != absolute_section) |
9721 | { | |
9722 | p = frag_more (i.vex.length); | |
9723 | for (j = 0; j < i.vex.length; j++) | |
9724 | p[j] = i.vex.bytes[j]; | |
9725 | } | |
9726 | else | |
9727 | abs_section_offset += i.vex.length; | |
c0f3af97 | 9728 | } |
252b5132 | 9729 | |
29b0f896 | 9730 | /* Now the opcode; be careful about word order here! */ |
389d00a5 JB |
9731 | j = i.opcode_length; |
9732 | if (!i.vex.length) | |
9733 | switch (i.tm.opcode_modifier.opcodespace) | |
9734 | { | |
9735 | case SPACE_BASE: | |
9736 | break; | |
9737 | case SPACE_0F: | |
9738 | ++j; | |
9739 | break; | |
9740 | case SPACE_0F38: | |
9741 | case SPACE_0F3A: | |
9742 | j += 2; | |
9743 | break; | |
9744 | default: | |
9745 | abort (); | |
9746 | } | |
9747 | ||
48ef937e | 9748 | if (now_seg == absolute_section) |
389d00a5 JB |
9749 | abs_section_offset += j; |
9750 | else if (j == 1) | |
29b0f896 AM |
9751 | { |
9752 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
9753 | } | |
9754 | else | |
9755 | { | |
389d00a5 JB |
9756 | p = frag_more (j); |
9757 | if (!i.vex.length | |
9758 | && i.tm.opcode_modifier.opcodespace != SPACE_BASE) | |
9759 | { | |
9760 | *p++ = 0x0f; | |
9761 | if (i.tm.opcode_modifier.opcodespace != SPACE_0F) | |
9762 | *p++ = i.tm.opcode_modifier.opcodespace == SPACE_0F38 | |
9763 | ? 0x38 : 0x3a; | |
9764 | } | |
9765 | ||
9a182d04 | 9766 | switch (i.opcode_length) |
331d2d0d | 9767 | { |
4dffcebc | 9768 | case 2: |
389d00a5 JB |
9769 | /* Put out high byte first: can't use md_number_to_chars! */ |
9770 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
9771 | /* Fall through. */ | |
9772 | case 1: | |
9773 | *p = i.tm.base_opcode & 0xff; | |
4dffcebc L |
9774 | break; |
9775 | default: | |
9776 | abort (); | |
9777 | break; | |
331d2d0d | 9778 | } |
0f10071e | 9779 | |
29b0f896 | 9780 | } |
3e73aa7c | 9781 | |
29b0f896 | 9782 | /* Now the modrm byte and sib byte (if present). */ |
40fb9820 | 9783 | if (i.tm.opcode_modifier.modrm) |
29b0f896 | 9784 | { |
48ef937e JB |
9785 | frag_opcode_byte ((i.rm.regmem << 0) |
9786 | | (i.rm.reg << 3) | |
9787 | | (i.rm.mode << 6)); | |
29b0f896 AM |
9788 | /* If i.rm.regmem == ESP (4) |
9789 | && i.rm.mode != (Register mode) | |
9790 | && not 16 bit | |
9791 | ==> need second modrm byte. */ | |
9792 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
9793 | && i.rm.mode != 3 | |
dc821c5f | 9794 | && !(i.base_reg && i.base_reg->reg_type.bitfield.word)) |
48ef937e JB |
9795 | frag_opcode_byte ((i.sib.base << 0) |
9796 | | (i.sib.index << 3) | |
9797 | | (i.sib.scale << 6)); | |
29b0f896 | 9798 | } |
3e73aa7c | 9799 | |
29b0f896 | 9800 | if (i.disp_operands) |
2bbd9c25 | 9801 | output_disp (insn_start_frag, insn_start_off); |
3e73aa7c | 9802 | |
29b0f896 | 9803 | if (i.imm_operands) |
2bbd9c25 | 9804 | output_imm (insn_start_frag, insn_start_off); |
9c33702b JB |
9805 | |
9806 | /* | |
9807 | * frag_now_fix () returning plain abs_section_offset when we're in the | |
9808 | * absolute section, and abs_section_offset not getting updated as data | |
9809 | * gets added to the frag breaks the logic below. | |
9810 | */ | |
9811 | if (now_seg != absolute_section) | |
9812 | { | |
9813 | j = encoding_length (insn_start_frag, insn_start_off, frag_more (0)); | |
9814 | if (j > 15) | |
9815 | as_warn (_("instruction length of %u bytes exceeds the limit of 15"), | |
9816 | j); | |
e379e5f3 L |
9817 | else if (fragP) |
9818 | { | |
9819 | /* NB: Don't add prefix with GOTPC relocation since | |
9820 | output_disp() above depends on the fixed encoding | |
9821 | length. Can't add prefix with TLS relocation since | |
9822 | it breaks TLS linker optimization. */ | |
9823 | unsigned int max = i.has_gotpc_tls_reloc ? 0 : 15 - j; | |
9824 | /* Prefix count on the current instruction. */ | |
9825 | unsigned int count = i.vex.length; | |
9826 | unsigned int k; | |
9827 | for (k = 0; k < ARRAY_SIZE (i.prefix); k++) | |
9828 | /* REX byte is encoded in VEX/EVEX prefix. */ | |
9829 | if (i.prefix[k] && (k != REX_PREFIX || !i.vex.length)) | |
9830 | count++; | |
9831 | ||
9832 | /* Count prefixes for extended opcode maps. */ | |
9833 | if (!i.vex.length) | |
389d00a5 | 9834 | switch (i.tm.opcode_modifier.opcodespace) |
e379e5f3 | 9835 | { |
389d00a5 | 9836 | case SPACE_BASE: |
e379e5f3 | 9837 | break; |
389d00a5 JB |
9838 | case SPACE_0F: |
9839 | count++; | |
e379e5f3 | 9840 | break; |
389d00a5 JB |
9841 | case SPACE_0F38: |
9842 | case SPACE_0F3A: | |
9843 | count += 2; | |
e379e5f3 L |
9844 | break; |
9845 | default: | |
9846 | abort (); | |
9847 | } | |
9848 | ||
9849 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
9850 | == BRANCH_PREFIX) | |
9851 | { | |
9852 | /* Set the maximum prefix size in BRANCH_PREFIX | |
9853 | frag. */ | |
9854 | if (fragP->tc_frag_data.max_bytes > max) | |
9855 | fragP->tc_frag_data.max_bytes = max; | |
9856 | if (fragP->tc_frag_data.max_bytes > count) | |
9857 | fragP->tc_frag_data.max_bytes -= count; | |
9858 | else | |
9859 | fragP->tc_frag_data.max_bytes = 0; | |
9860 | } | |
9861 | else | |
9862 | { | |
9863 | /* Remember the maximum prefix size in FUSED_JCC_PADDING | |
9864 | frag. */ | |
9865 | unsigned int max_prefix_size; | |
9866 | if (align_branch_prefix_size > max) | |
9867 | max_prefix_size = max; | |
9868 | else | |
9869 | max_prefix_size = align_branch_prefix_size; | |
9870 | if (max_prefix_size > count) | |
9871 | fragP->tc_frag_data.max_prefix_length | |
9872 | = max_prefix_size - count; | |
9873 | } | |
9874 | ||
9875 | /* Use existing segment prefix if possible. Use CS | |
9876 | segment prefix in 64-bit mode. In 32-bit mode, use SS | |
9877 | segment prefix with ESP/EBP base register and use DS | |
9878 | segment prefix without ESP/EBP base register. */ | |
9879 | if (i.prefix[SEG_PREFIX]) | |
9880 | fragP->tc_frag_data.default_prefix = i.prefix[SEG_PREFIX]; | |
9881 | else if (flag_code == CODE_64BIT) | |
9882 | fragP->tc_frag_data.default_prefix = CS_PREFIX_OPCODE; | |
9883 | else if (i.base_reg | |
9884 | && (i.base_reg->reg_num == 4 | |
9885 | || i.base_reg->reg_num == 5)) | |
9886 | fragP->tc_frag_data.default_prefix = SS_PREFIX_OPCODE; | |
9887 | else | |
9888 | fragP->tc_frag_data.default_prefix = DS_PREFIX_OPCODE; | |
9889 | } | |
9c33702b | 9890 | } |
29b0f896 | 9891 | } |
252b5132 | 9892 | |
e379e5f3 L |
9893 | /* NB: Don't work with COND_JUMP86 without i386. */ |
9894 | if (align_branch_power | |
9895 | && now_seg != absolute_section | |
9896 | && cpu_arch_flags.bitfield.cpui386) | |
9897 | { | |
9898 | /* Terminate each frag so that we can add prefix and check for | |
9899 | fused jcc. */ | |
9900 | frag_wane (frag_now); | |
9901 | frag_new (0); | |
9902 | } | |
9903 | ||
29b0f896 AM |
9904 | #ifdef DEBUG386 |
9905 | if (flag_debug) | |
9906 | { | |
7b81dfbb | 9907 | pi ("" /*line*/, &i); |
29b0f896 AM |
9908 | } |
9909 | #endif /* DEBUG386 */ | |
9910 | } | |
252b5132 | 9911 | |
e205caa7 L |
9912 | /* Return the size of the displacement operand N. */ |
9913 | ||
9914 | static int | |
9915 | disp_size (unsigned int n) | |
9916 | { | |
9917 | int size = 4; | |
43234a1e | 9918 | |
b5014f7a | 9919 | if (i.types[n].bitfield.disp64) |
40fb9820 L |
9920 | size = 8; |
9921 | else if (i.types[n].bitfield.disp8) | |
9922 | size = 1; | |
9923 | else if (i.types[n].bitfield.disp16) | |
9924 | size = 2; | |
e205caa7 L |
9925 | return size; |
9926 | } | |
9927 | ||
9928 | /* Return the size of the immediate operand N. */ | |
9929 | ||
9930 | static int | |
9931 | imm_size (unsigned int n) | |
9932 | { | |
9933 | int size = 4; | |
40fb9820 L |
9934 | if (i.types[n].bitfield.imm64) |
9935 | size = 8; | |
9936 | else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) | |
9937 | size = 1; | |
9938 | else if (i.types[n].bitfield.imm16) | |
9939 | size = 2; | |
e205caa7 L |
9940 | return size; |
9941 | } | |
9942 | ||
29b0f896 | 9943 | static void |
64e74474 | 9944 | output_disp (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
9945 | { |
9946 | char *p; | |
9947 | unsigned int n; | |
252b5132 | 9948 | |
29b0f896 AM |
9949 | for (n = 0; n < i.operands; n++) |
9950 | { | |
b5014f7a | 9951 | if (operand_type_check (i.types[n], disp)) |
29b0f896 | 9952 | { |
48ef937e JB |
9953 | int size = disp_size (n); |
9954 | ||
9955 | if (now_seg == absolute_section) | |
9956 | abs_section_offset += size; | |
9957 | else if (i.op[n].disps->X_op == O_constant) | |
29b0f896 | 9958 | { |
43234a1e | 9959 | offsetT val = i.op[n].disps->X_add_number; |
252b5132 | 9960 | |
629cfaf1 JB |
9961 | val = offset_in_range (val >> (size == 1 ? i.memshift : 0), |
9962 | size); | |
29b0f896 AM |
9963 | p = frag_more (size); |
9964 | md_number_to_chars (p, val, size); | |
9965 | } | |
9966 | else | |
9967 | { | |
f86103b7 | 9968 | enum bfd_reloc_code_real reloc_type; |
40fb9820 | 9969 | int sign = i.types[n].bitfield.disp32s; |
29b0f896 | 9970 | int pcrel = (i.flags[n] & Operand_PCrel) != 0; |
02a86693 | 9971 | fixS *fixP; |
29b0f896 | 9972 | |
e205caa7 | 9973 | /* We can't have 8 bit displacement here. */ |
9c2799c2 | 9974 | gas_assert (!i.types[n].bitfield.disp8); |
e205caa7 | 9975 | |
29b0f896 AM |
9976 | /* The PC relative address is computed relative |
9977 | to the instruction boundary, so in case immediate | |
9978 | fields follows, we need to adjust the value. */ | |
9979 | if (pcrel && i.imm_operands) | |
9980 | { | |
29b0f896 | 9981 | unsigned int n1; |
e205caa7 | 9982 | int sz = 0; |
252b5132 | 9983 | |
29b0f896 | 9984 | for (n1 = 0; n1 < i.operands; n1++) |
40fb9820 | 9985 | if (operand_type_check (i.types[n1], imm)) |
252b5132 | 9986 | { |
e205caa7 L |
9987 | /* Only one immediate is allowed for PC |
9988 | relative address. */ | |
9c2799c2 | 9989 | gas_assert (sz == 0); |
e205caa7 L |
9990 | sz = imm_size (n1); |
9991 | i.op[n].disps->X_add_number -= sz; | |
252b5132 | 9992 | } |
29b0f896 | 9993 | /* We should find the immediate. */ |
9c2799c2 | 9994 | gas_assert (sz != 0); |
29b0f896 | 9995 | } |
520dc8e8 | 9996 | |
29b0f896 | 9997 | p = frag_more (size); |
d258b828 | 9998 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
d6ab8113 | 9999 | if (GOT_symbol |
2bbd9c25 | 10000 | && GOT_symbol == i.op[n].disps->X_add_symbol |
d6ab8113 | 10001 | && (((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
10002 | || reloc_type == BFD_RELOC_X86_64_32S |
10003 | || (reloc_type == BFD_RELOC_64 | |
10004 | && object_64bit)) | |
d6ab8113 JB |
10005 | && (i.op[n].disps->X_op == O_symbol |
10006 | || (i.op[n].disps->X_op == O_add | |
10007 | && ((symbol_get_value_expression | |
10008 | (i.op[n].disps->X_op_symbol)->X_op) | |
10009 | == O_subtract)))) | |
10010 | || reloc_type == BFD_RELOC_32_PCREL)) | |
2bbd9c25 | 10011 | { |
4fa24527 | 10012 | if (!object_64bit) |
7b81dfbb AJ |
10013 | { |
10014 | reloc_type = BFD_RELOC_386_GOTPC; | |
5b7c81bd | 10015 | i.has_gotpc_tls_reloc = true; |
98da05bf | 10016 | i.op[n].disps->X_add_number += |
d583596c | 10017 | encoding_length (insn_start_frag, insn_start_off, p); |
7b81dfbb AJ |
10018 | } |
10019 | else if (reloc_type == BFD_RELOC_64) | |
10020 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
d6ab8113 | 10021 | else |
7b81dfbb AJ |
10022 | /* Don't do the adjustment for x86-64, as there |
10023 | the pcrel addressing is relative to the _next_ | |
10024 | insn, and that is taken care of in other code. */ | |
d6ab8113 | 10025 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
2bbd9c25 | 10026 | } |
e379e5f3 L |
10027 | else if (align_branch_power) |
10028 | { | |
10029 | switch (reloc_type) | |
10030 | { | |
10031 | case BFD_RELOC_386_TLS_GD: | |
10032 | case BFD_RELOC_386_TLS_LDM: | |
10033 | case BFD_RELOC_386_TLS_IE: | |
10034 | case BFD_RELOC_386_TLS_IE_32: | |
10035 | case BFD_RELOC_386_TLS_GOTIE: | |
10036 | case BFD_RELOC_386_TLS_GOTDESC: | |
10037 | case BFD_RELOC_386_TLS_DESC_CALL: | |
10038 | case BFD_RELOC_X86_64_TLSGD: | |
10039 | case BFD_RELOC_X86_64_TLSLD: | |
10040 | case BFD_RELOC_X86_64_GOTTPOFF: | |
10041 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: | |
10042 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
5b7c81bd | 10043 | i.has_gotpc_tls_reloc = true; |
e379e5f3 L |
10044 | default: |
10045 | break; | |
10046 | } | |
10047 | } | |
02a86693 L |
10048 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, |
10049 | size, i.op[n].disps, pcrel, | |
10050 | reloc_type); | |
eb19308f JB |
10051 | |
10052 | if (flag_code == CODE_64BIT && size == 4 && pcrel | |
10053 | && !i.prefix[ADDR_PREFIX]) | |
10054 | fixP->fx_signed = 1; | |
10055 | ||
02a86693 L |
10056 | /* Check for "call/jmp *mem", "mov mem, %reg", |
10057 | "test %reg, mem" and "binop mem, %reg" where binop | |
10058 | is one of adc, add, and, cmp, or, sbb, sub, xor | |
e60f4d3b L |
10059 | instructions without data prefix. Always generate |
10060 | R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */ | |
10061 | if (i.prefix[DATA_PREFIX] == 0 | |
10062 | && (generate_relax_relocations | |
10063 | || (!object_64bit | |
10064 | && i.rm.mode == 0 | |
10065 | && i.rm.regmem == 5)) | |
0cb4071e L |
10066 | && (i.rm.mode == 2 |
10067 | || (i.rm.mode == 0 && i.rm.regmem == 5)) | |
389d00a5 | 10068 | && i.tm.opcode_modifier.opcodespace == SPACE_BASE |
02a86693 L |
10069 | && ((i.operands == 1 |
10070 | && i.tm.base_opcode == 0xff | |
10071 | && (i.rm.reg == 2 || i.rm.reg == 4)) | |
10072 | || (i.operands == 2 | |
10073 | && (i.tm.base_opcode == 0x8b | |
10074 | || i.tm.base_opcode == 0x85 | |
2ae4c703 | 10075 | || (i.tm.base_opcode & ~0x38) == 0x03)))) |
02a86693 L |
10076 | { |
10077 | if (object_64bit) | |
10078 | { | |
10079 | fixP->fx_tcbit = i.rex != 0; | |
10080 | if (i.base_reg | |
e968fc9b | 10081 | && (i.base_reg->reg_num == RegIP)) |
02a86693 L |
10082 | fixP->fx_tcbit2 = 1; |
10083 | } | |
10084 | else | |
10085 | fixP->fx_tcbit2 = 1; | |
10086 | } | |
29b0f896 AM |
10087 | } |
10088 | } | |
10089 | } | |
10090 | } | |
252b5132 | 10091 | |
29b0f896 | 10092 | static void |
64e74474 | 10093 | output_imm (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
10094 | { |
10095 | char *p; | |
10096 | unsigned int n; | |
252b5132 | 10097 | |
29b0f896 AM |
10098 | for (n = 0; n < i.operands; n++) |
10099 | { | |
43234a1e | 10100 | /* Skip SAE/RC Imm operand in EVEX. They are already handled. */ |
ca5312a2 | 10101 | if (i.rounding.type != rc_none && n == i.rounding.operand) |
43234a1e L |
10102 | continue; |
10103 | ||
40fb9820 | 10104 | if (operand_type_check (i.types[n], imm)) |
29b0f896 | 10105 | { |
48ef937e JB |
10106 | int size = imm_size (n); |
10107 | ||
10108 | if (now_seg == absolute_section) | |
10109 | abs_section_offset += size; | |
10110 | else if (i.op[n].imms->X_op == O_constant) | |
29b0f896 | 10111 | { |
29b0f896 | 10112 | offsetT val; |
b4cac588 | 10113 | |
29b0f896 AM |
10114 | val = offset_in_range (i.op[n].imms->X_add_number, |
10115 | size); | |
10116 | p = frag_more (size); | |
10117 | md_number_to_chars (p, val, size); | |
10118 | } | |
10119 | else | |
10120 | { | |
10121 | /* Not absolute_section. | |
10122 | Need a 32-bit fixup (don't support 8bit | |
10123 | non-absolute imms). Try to support other | |
10124 | sizes ... */ | |
f86103b7 | 10125 | enum bfd_reloc_code_real reloc_type; |
e205caa7 | 10126 | int sign; |
29b0f896 | 10127 | |
40fb9820 | 10128 | if (i.types[n].bitfield.imm32s |
a7d61044 | 10129 | && (i.suffix == QWORD_MNEM_SUFFIX |
40fb9820 | 10130 | || (!i.suffix && i.tm.opcode_modifier.no_lsuf))) |
29b0f896 | 10131 | sign = 1; |
e205caa7 L |
10132 | else |
10133 | sign = 0; | |
520dc8e8 | 10134 | |
29b0f896 | 10135 | p = frag_more (size); |
d258b828 | 10136 | reloc_type = reloc (size, 0, sign, i.reloc[n]); |
f86103b7 | 10137 | |
2bbd9c25 JJ |
10138 | /* This is tough to explain. We end up with this one if we |
10139 | * have operands that look like | |
10140 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to | |
10141 | * obtain the absolute address of the GOT, and it is strongly | |
10142 | * preferable from a performance point of view to avoid using | |
10143 | * a runtime relocation for this. The actual sequence of | |
10144 | * instructions often look something like: | |
10145 | * | |
10146 | * call .L66 | |
10147 | * .L66: | |
10148 | * popl %ebx | |
10149 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
10150 | * | |
10151 | * The call and pop essentially return the absolute address | |
10152 | * of the label .L66 and store it in %ebx. The linker itself | |
10153 | * will ultimately change the first operand of the addl so | |
10154 | * that %ebx points to the GOT, but to keep things simple, the | |
10155 | * .o file must have this operand set so that it generates not | |
10156 | * the absolute address of .L66, but the absolute address of | |
10157 | * itself. This allows the linker itself simply treat a GOTPC | |
10158 | * relocation as asking for a pcrel offset to the GOT to be | |
10159 | * added in, and the addend of the relocation is stored in the | |
10160 | * operand field for the instruction itself. | |
10161 | * | |
10162 | * Our job here is to fix the operand so that it would add | |
10163 | * the correct offset so that %ebx would point to itself. The | |
10164 | * thing that is tricky is that .-.L66 will point to the | |
10165 | * beginning of the instruction, so we need to further modify | |
10166 | * the operand so that it will point to itself. There are | |
10167 | * other cases where you have something like: | |
10168 | * | |
10169 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
10170 | * | |
10171 | * and here no correction would be required. Internally in | |
10172 | * the assembler we treat operands of this form as not being | |
10173 | * pcrel since the '.' is explicitly mentioned, and I wonder | |
10174 | * whether it would simplify matters to do it this way. Who | |
10175 | * knows. In earlier versions of the PIC patches, the | |
10176 | * pcrel_adjust field was used to store the correction, but | |
10177 | * since the expression is not pcrel, I felt it would be | |
10178 | * confusing to do it this way. */ | |
10179 | ||
d6ab8113 | 10180 | if ((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
10181 | || reloc_type == BFD_RELOC_X86_64_32S |
10182 | || reloc_type == BFD_RELOC_64) | |
29b0f896 AM |
10183 | && GOT_symbol |
10184 | && GOT_symbol == i.op[n].imms->X_add_symbol | |
10185 | && (i.op[n].imms->X_op == O_symbol | |
10186 | || (i.op[n].imms->X_op == O_add | |
10187 | && ((symbol_get_value_expression | |
10188 | (i.op[n].imms->X_op_symbol)->X_op) | |
10189 | == O_subtract)))) | |
10190 | { | |
4fa24527 | 10191 | if (!object_64bit) |
d6ab8113 | 10192 | reloc_type = BFD_RELOC_386_GOTPC; |
7b81dfbb | 10193 | else if (size == 4) |
d6ab8113 | 10194 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
7b81dfbb AJ |
10195 | else if (size == 8) |
10196 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
5b7c81bd | 10197 | i.has_gotpc_tls_reloc = true; |
d583596c JB |
10198 | i.op[n].imms->X_add_number += |
10199 | encoding_length (insn_start_frag, insn_start_off, p); | |
29b0f896 | 10200 | } |
29b0f896 AM |
10201 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
10202 | i.op[n].imms, 0, reloc_type); | |
10203 | } | |
10204 | } | |
10205 | } | |
252b5132 RH |
10206 | } |
10207 | \f | |
d182319b JB |
10208 | /* x86_cons_fix_new is called via the expression parsing code when a |
10209 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
d182319b JB |
10210 | static int cons_sign = -1; |
10211 | ||
10212 | void | |
e3bb37b5 | 10213 | x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, |
62ebcb5c | 10214 | expressionS *exp, bfd_reloc_code_real_type r) |
d182319b | 10215 | { |
d258b828 | 10216 | r = reloc (len, 0, cons_sign, r); |
d182319b JB |
10217 | |
10218 | #ifdef TE_PE | |
10219 | if (exp->X_op == O_secrel) | |
10220 | { | |
10221 | exp->X_op = O_symbol; | |
10222 | r = BFD_RELOC_32_SECREL; | |
10223 | } | |
10224 | #endif | |
10225 | ||
10226 | fix_new_exp (frag, off, len, exp, 0, r); | |
10227 | } | |
10228 | ||
357d1bd8 L |
10229 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
10230 | purpose of the `.dc.a' internal pseudo-op. */ | |
10231 | ||
10232 | int | |
10233 | x86_address_bytes (void) | |
10234 | { | |
10235 | if ((stdoutput->arch_info->mach & bfd_mach_x64_32)) | |
10236 | return 4; | |
10237 | return stdoutput->arch_info->bits_per_address / 8; | |
10238 | } | |
10239 | ||
deea4973 JB |
10240 | #if (!(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \ |
10241 | || defined (LEX_AT)) && !defined (TE_PE) | |
d258b828 | 10242 | # define lex_got(reloc, adjust, types) NULL |
718ddfc0 | 10243 | #else |
f3c180ae AM |
10244 | /* Parse operands of the form |
10245 | <symbol>@GOTOFF+<nnn> | |
10246 | and similar .plt or .got references. | |
10247 | ||
10248 | If we find one, set up the correct relocation in RELOC and copy the | |
10249 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
10250 | parsing by the calling routine. Return this buffer, and if ADJUST | |
10251 | is non-null set it to the length of the string we removed from the | |
10252 | input line. Otherwise return NULL. */ | |
10253 | static char * | |
91d6fa6a | 10254 | lex_got (enum bfd_reloc_code_real *rel, |
64e74474 | 10255 | int *adjust, |
d258b828 | 10256 | i386_operand_type *types) |
f3c180ae | 10257 | { |
7b81dfbb AJ |
10258 | /* Some of the relocations depend on the size of what field is to |
10259 | be relocated. But in our callers i386_immediate and i386_displacement | |
10260 | we don't yet know the operand size (this will be set by insn | |
10261 | matching). Hence we record the word32 relocation here, | |
10262 | and adjust the reloc according to the real size in reloc(). */ | |
f3c180ae AM |
10263 | static const struct { |
10264 | const char *str; | |
cff8d58a | 10265 | int len; |
4fa24527 | 10266 | const enum bfd_reloc_code_real rel[2]; |
40fb9820 | 10267 | const i386_operand_type types64; |
5b7c81bd | 10268 | bool need_GOT_symbol; |
f3c180ae | 10269 | } gotrel[] = { |
deea4973 | 10270 | #ifndef TE_PE |
8ce3d284 | 10271 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
10272 | { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32, |
10273 | BFD_RELOC_SIZE32 }, | |
5b7c81bd | 10274 | OPERAND_TYPE_IMM32_64, false }, |
8ce3d284 | 10275 | #endif |
cff8d58a L |
10276 | { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real, |
10277 | BFD_RELOC_X86_64_PLTOFF64 }, | |
5b7c81bd | 10278 | OPERAND_TYPE_IMM64, true }, |
cff8d58a L |
10279 | { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32, |
10280 | BFD_RELOC_X86_64_PLT32 }, | |
5b7c81bd | 10281 | OPERAND_TYPE_IMM32_32S_DISP32, false }, |
cff8d58a L |
10282 | { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real, |
10283 | BFD_RELOC_X86_64_GOTPLT64 }, | |
5b7c81bd | 10284 | OPERAND_TYPE_IMM64_DISP64, true }, |
cff8d58a L |
10285 | { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF, |
10286 | BFD_RELOC_X86_64_GOTOFF64 }, | |
5b7c81bd | 10287 | OPERAND_TYPE_IMM64_DISP64, true }, |
cff8d58a L |
10288 | { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real, |
10289 | BFD_RELOC_X86_64_GOTPCREL }, | |
5b7c81bd | 10290 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
cff8d58a L |
10291 | { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD, |
10292 | BFD_RELOC_X86_64_TLSGD }, | |
5b7c81bd | 10293 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
cff8d58a L |
10294 | { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM, |
10295 | _dummy_first_bfd_reloc_code_real }, | |
5b7c81bd | 10296 | OPERAND_TYPE_NONE, true }, |
cff8d58a L |
10297 | { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real, |
10298 | BFD_RELOC_X86_64_TLSLD }, | |
5b7c81bd | 10299 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
cff8d58a L |
10300 | { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32, |
10301 | BFD_RELOC_X86_64_GOTTPOFF }, | |
5b7c81bd | 10302 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
cff8d58a L |
10303 | { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32, |
10304 | BFD_RELOC_X86_64_TPOFF32 }, | |
5b7c81bd | 10305 | OPERAND_TYPE_IMM32_32S_64_DISP32_64, true }, |
cff8d58a L |
10306 | { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE, |
10307 | _dummy_first_bfd_reloc_code_real }, | |
5b7c81bd | 10308 | OPERAND_TYPE_NONE, true }, |
cff8d58a L |
10309 | { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32, |
10310 | BFD_RELOC_X86_64_DTPOFF32 }, | |
5b7c81bd | 10311 | OPERAND_TYPE_IMM32_32S_64_DISP32_64, true }, |
cff8d58a L |
10312 | { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE, |
10313 | _dummy_first_bfd_reloc_code_real }, | |
5b7c81bd | 10314 | OPERAND_TYPE_NONE, true }, |
cff8d58a L |
10315 | { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE, |
10316 | _dummy_first_bfd_reloc_code_real }, | |
5b7c81bd | 10317 | OPERAND_TYPE_NONE, true }, |
cff8d58a L |
10318 | { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32, |
10319 | BFD_RELOC_X86_64_GOT32 }, | |
5b7c81bd | 10320 | OPERAND_TYPE_IMM32_32S_64_DISP32, true }, |
cff8d58a L |
10321 | { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC, |
10322 | BFD_RELOC_X86_64_GOTPC32_TLSDESC }, | |
5b7c81bd | 10323 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
cff8d58a L |
10324 | { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL, |
10325 | BFD_RELOC_X86_64_TLSDESC_CALL }, | |
5b7c81bd | 10326 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
deea4973 JB |
10327 | #else /* TE_PE */ |
10328 | { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL, | |
10329 | BFD_RELOC_32_SECREL }, | |
10330 | OPERAND_TYPE_IMM32_32S_64_DISP32_64, false }, | |
10331 | #endif | |
f3c180ae AM |
10332 | }; |
10333 | char *cp; | |
10334 | unsigned int j; | |
10335 | ||
deea4973 | 10336 | #if defined (OBJ_MAYBE_ELF) && !defined (TE_PE) |
718ddfc0 JB |
10337 | if (!IS_ELF) |
10338 | return NULL; | |
d382c579 | 10339 | #endif |
718ddfc0 | 10340 | |
f3c180ae | 10341 | for (cp = input_line_pointer; *cp != '@'; cp++) |
67c11a9b | 10342 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') |
f3c180ae AM |
10343 | return NULL; |
10344 | ||
47465058 | 10345 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) |
f3c180ae | 10346 | { |
cff8d58a | 10347 | int len = gotrel[j].len; |
28f81592 | 10348 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae | 10349 | { |
4fa24527 | 10350 | if (gotrel[j].rel[object_64bit] != 0) |
f3c180ae | 10351 | { |
28f81592 AM |
10352 | int first, second; |
10353 | char *tmpbuf, *past_reloc; | |
f3c180ae | 10354 | |
91d6fa6a | 10355 | *rel = gotrel[j].rel[object_64bit]; |
f3c180ae | 10356 | |
3956db08 JB |
10357 | if (types) |
10358 | { | |
10359 | if (flag_code != CODE_64BIT) | |
40fb9820 L |
10360 | { |
10361 | types->bitfield.imm32 = 1; | |
10362 | types->bitfield.disp32 = 1; | |
10363 | } | |
3956db08 JB |
10364 | else |
10365 | *types = gotrel[j].types64; | |
10366 | } | |
10367 | ||
844bf810 | 10368 | if (gotrel[j].need_GOT_symbol && GOT_symbol == NULL) |
f3c180ae AM |
10369 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); |
10370 | ||
28f81592 | 10371 | /* The length of the first part of our input line. */ |
f3c180ae | 10372 | first = cp - input_line_pointer; |
28f81592 AM |
10373 | |
10374 | /* The second part goes from after the reloc token until | |
67c11a9b | 10375 | (and including) an end_of_line char or comma. */ |
28f81592 | 10376 | past_reloc = cp + 1 + len; |
67c11a9b AM |
10377 | cp = past_reloc; |
10378 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
10379 | ++cp; | |
10380 | second = cp + 1 - past_reloc; | |
28f81592 AM |
10381 | |
10382 | /* Allocate and copy string. The trailing NUL shouldn't | |
10383 | be necessary, but be safe. */ | |
add39d23 | 10384 | tmpbuf = XNEWVEC (char, first + second + 2); |
f3c180ae | 10385 | memcpy (tmpbuf, input_line_pointer, first); |
0787a12d AM |
10386 | if (second != 0 && *past_reloc != ' ') |
10387 | /* Replace the relocation token with ' ', so that | |
10388 | errors like foo@GOTOFF1 will be detected. */ | |
10389 | tmpbuf[first++] = ' '; | |
af89796a L |
10390 | else |
10391 | /* Increment length by 1 if the relocation token is | |
10392 | removed. */ | |
10393 | len++; | |
10394 | if (adjust) | |
10395 | *adjust = len; | |
0787a12d AM |
10396 | memcpy (tmpbuf + first, past_reloc, second); |
10397 | tmpbuf[first + second] = '\0'; | |
f3c180ae AM |
10398 | return tmpbuf; |
10399 | } | |
10400 | ||
4fa24527 JB |
10401 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
10402 | gotrel[j].str, 1 << (5 + object_64bit)); | |
f3c180ae AM |
10403 | return NULL; |
10404 | } | |
10405 | } | |
10406 | ||
10407 | /* Might be a symbol version string. Don't as_bad here. */ | |
10408 | return NULL; | |
10409 | } | |
4e4f7c87 | 10410 | #endif |
f3c180ae | 10411 | |
62ebcb5c | 10412 | bfd_reloc_code_real_type |
e3bb37b5 | 10413 | x86_cons (expressionS *exp, int size) |
f3c180ae | 10414 | { |
62ebcb5c AM |
10415 | bfd_reloc_code_real_type got_reloc = NO_RELOC; |
10416 | ||
ee86248c JB |
10417 | intel_syntax = -intel_syntax; |
10418 | ||
3c7b9c2c | 10419 | exp->X_md = 0; |
4fa24527 | 10420 | if (size == 4 || (object_64bit && size == 8)) |
f3c180ae AM |
10421 | { |
10422 | /* Handle @GOTOFF and the like in an expression. */ | |
10423 | char *save; | |
10424 | char *gotfree_input_line; | |
4a57f2cf | 10425 | int adjust = 0; |
f3c180ae AM |
10426 | |
10427 | save = input_line_pointer; | |
d258b828 | 10428 | gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); |
f3c180ae AM |
10429 | if (gotfree_input_line) |
10430 | input_line_pointer = gotfree_input_line; | |
10431 | ||
10432 | expression (exp); | |
10433 | ||
10434 | if (gotfree_input_line) | |
10435 | { | |
10436 | /* expression () has merrily parsed up to the end of line, | |
10437 | or a comma - in the wrong buffer. Transfer how far | |
10438 | input_line_pointer has moved to the right buffer. */ | |
10439 | input_line_pointer = (save | |
10440 | + (input_line_pointer - gotfree_input_line) | |
10441 | + adjust); | |
10442 | free (gotfree_input_line); | |
3992d3b7 AM |
10443 | if (exp->X_op == O_constant |
10444 | || exp->X_op == O_absent | |
10445 | || exp->X_op == O_illegal | |
0398aac5 | 10446 | || exp->X_op == O_register |
3992d3b7 AM |
10447 | || exp->X_op == O_big) |
10448 | { | |
10449 | char c = *input_line_pointer; | |
10450 | *input_line_pointer = 0; | |
10451 | as_bad (_("missing or invalid expression `%s'"), save); | |
10452 | *input_line_pointer = c; | |
10453 | } | |
b9519cfe L |
10454 | else if ((got_reloc == BFD_RELOC_386_PLT32 |
10455 | || got_reloc == BFD_RELOC_X86_64_PLT32) | |
10456 | && exp->X_op != O_symbol) | |
10457 | { | |
10458 | char c = *input_line_pointer; | |
10459 | *input_line_pointer = 0; | |
10460 | as_bad (_("invalid PLT expression `%s'"), save); | |
10461 | *input_line_pointer = c; | |
10462 | } | |
f3c180ae AM |
10463 | } |
10464 | } | |
10465 | else | |
10466 | expression (exp); | |
ee86248c JB |
10467 | |
10468 | intel_syntax = -intel_syntax; | |
10469 | ||
10470 | if (intel_syntax) | |
10471 | i386_intel_simplify (exp); | |
62ebcb5c | 10472 | |
a442cac5 JB |
10473 | /* If not 64bit, massage value, to account for wraparound when !BFD64. */ |
10474 | if (size == 4 && exp->X_op == O_constant && !object_64bit) | |
10475 | exp->X_add_number = extend_to_32bit_address (exp->X_add_number); | |
10476 | ||
62ebcb5c | 10477 | return got_reloc; |
f3c180ae | 10478 | } |
f3c180ae | 10479 | |
9f32dd5b L |
10480 | static void |
10481 | signed_cons (int size) | |
6482c264 | 10482 | { |
a442cac5 | 10483 | if (object_64bit) |
d182319b JB |
10484 | cons_sign = 1; |
10485 | cons (size); | |
10486 | cons_sign = -1; | |
6482c264 NC |
10487 | } |
10488 | ||
d182319b | 10489 | #ifdef TE_PE |
6482c264 | 10490 | static void |
7016a5d5 | 10491 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
6482c264 NC |
10492 | { |
10493 | expressionS exp; | |
10494 | ||
10495 | do | |
10496 | { | |
10497 | expression (&exp); | |
10498 | if (exp.X_op == O_symbol) | |
10499 | exp.X_op = O_secrel; | |
10500 | ||
10501 | emit_expr (&exp, 4); | |
10502 | } | |
10503 | while (*input_line_pointer++ == ','); | |
10504 | ||
10505 | input_line_pointer--; | |
10506 | demand_empty_rest_of_line (); | |
10507 | } | |
6482c264 NC |
10508 | #endif |
10509 | ||
43234a1e L |
10510 | /* Handle Vector operations. */ |
10511 | ||
10512 | static char * | |
10513 | check_VecOperations (char *op_string, char *op_end) | |
10514 | { | |
10515 | const reg_entry *mask; | |
10516 | const char *saved; | |
10517 | char *end_op; | |
10518 | ||
10519 | while (*op_string | |
10520 | && (op_end == NULL || op_string < op_end)) | |
10521 | { | |
10522 | saved = op_string; | |
10523 | if (*op_string == '{') | |
10524 | { | |
10525 | op_string++; | |
10526 | ||
10527 | /* Check broadcasts. */ | |
d34049e8 | 10528 | if (startswith (op_string, "1to")) |
43234a1e | 10529 | { |
5273a3cd | 10530 | unsigned int bcst_type; |
43234a1e | 10531 | |
5273a3cd | 10532 | if (i.broadcast.type) |
43234a1e L |
10533 | goto duplicated_vec_op; |
10534 | ||
10535 | op_string += 3; | |
10536 | if (*op_string == '8') | |
8e6e0792 | 10537 | bcst_type = 8; |
b28d1bda | 10538 | else if (*op_string == '4') |
8e6e0792 | 10539 | bcst_type = 4; |
b28d1bda | 10540 | else if (*op_string == '2') |
8e6e0792 | 10541 | bcst_type = 2; |
43234a1e L |
10542 | else if (*op_string == '1' |
10543 | && *(op_string+1) == '6') | |
10544 | { | |
8e6e0792 | 10545 | bcst_type = 16; |
43234a1e L |
10546 | op_string++; |
10547 | } | |
10548 | else | |
10549 | { | |
10550 | as_bad (_("Unsupported broadcast: `%s'"), saved); | |
10551 | return NULL; | |
10552 | } | |
10553 | op_string++; | |
10554 | ||
5273a3cd JB |
10555 | i.broadcast.type = bcst_type; |
10556 | i.broadcast.operand = this_operand; | |
43234a1e L |
10557 | } |
10558 | /* Check masking operation. */ | |
10559 | else if ((mask = parse_register (op_string, &end_op)) != NULL) | |
10560 | { | |
8a6fb3f9 JB |
10561 | if (mask == &bad_reg) |
10562 | return NULL; | |
10563 | ||
43234a1e | 10564 | /* k0 can't be used for write mask. */ |
f74a6307 | 10565 | if (mask->reg_type.bitfield.class != RegMask || !mask->reg_num) |
43234a1e | 10566 | { |
6d2cd6b2 JB |
10567 | as_bad (_("`%s%s' can't be used for write mask"), |
10568 | register_prefix, mask->reg_name); | |
43234a1e L |
10569 | return NULL; |
10570 | } | |
10571 | ||
6225c532 | 10572 | if (!i.mask.reg) |
43234a1e | 10573 | { |
6225c532 JB |
10574 | i.mask.reg = mask; |
10575 | i.mask.operand = this_operand; | |
43234a1e | 10576 | } |
6225c532 JB |
10577 | else if (i.mask.reg->reg_num) |
10578 | goto duplicated_vec_op; | |
43234a1e L |
10579 | else |
10580 | { | |
6225c532 | 10581 | i.mask.reg = mask; |
43234a1e L |
10582 | |
10583 | /* Only "{z}" is allowed here. No need to check | |
10584 | zeroing mask explicitly. */ | |
6225c532 | 10585 | if (i.mask.operand != (unsigned int) this_operand) |
43234a1e L |
10586 | { |
10587 | as_bad (_("invalid write mask `%s'"), saved); | |
10588 | return NULL; | |
10589 | } | |
10590 | } | |
10591 | ||
10592 | op_string = end_op; | |
10593 | } | |
10594 | /* Check zeroing-flag for masking operation. */ | |
10595 | else if (*op_string == 'z') | |
10596 | { | |
6225c532 | 10597 | if (!i.mask.reg) |
43234a1e | 10598 | { |
6225c532 JB |
10599 | i.mask.reg = reg_k0; |
10600 | i.mask.zeroing = 1; | |
10601 | i.mask.operand = this_operand; | |
43234a1e L |
10602 | } |
10603 | else | |
10604 | { | |
6225c532 | 10605 | if (i.mask.zeroing) |
43234a1e L |
10606 | { |
10607 | duplicated_vec_op: | |
10608 | as_bad (_("duplicated `%s'"), saved); | |
10609 | return NULL; | |
10610 | } | |
10611 | ||
6225c532 | 10612 | i.mask.zeroing = 1; |
43234a1e L |
10613 | |
10614 | /* Only "{%k}" is allowed here. No need to check mask | |
10615 | register explicitly. */ | |
6225c532 | 10616 | if (i.mask.operand != (unsigned int) this_operand) |
43234a1e L |
10617 | { |
10618 | as_bad (_("invalid zeroing-masking `%s'"), | |
10619 | saved); | |
10620 | return NULL; | |
10621 | } | |
10622 | } | |
10623 | ||
10624 | op_string++; | |
10625 | } | |
10626 | else | |
10627 | goto unknown_vec_op; | |
10628 | ||
10629 | if (*op_string != '}') | |
10630 | { | |
10631 | as_bad (_("missing `}' in `%s'"), saved); | |
10632 | return NULL; | |
10633 | } | |
10634 | op_string++; | |
0ba3a731 L |
10635 | |
10636 | /* Strip whitespace since the addition of pseudo prefixes | |
10637 | changed how the scrubber treats '{'. */ | |
10638 | if (is_space_char (*op_string)) | |
10639 | ++op_string; | |
10640 | ||
43234a1e L |
10641 | continue; |
10642 | } | |
10643 | unknown_vec_op: | |
10644 | /* We don't know this one. */ | |
10645 | as_bad (_("unknown vector operation: `%s'"), saved); | |
10646 | return NULL; | |
10647 | } | |
10648 | ||
6225c532 | 10649 | if (i.mask.reg && i.mask.zeroing && !i.mask.reg->reg_num) |
6d2cd6b2 JB |
10650 | { |
10651 | as_bad (_("zeroing-masking only allowed with write mask")); | |
10652 | return NULL; | |
10653 | } | |
10654 | ||
43234a1e L |
10655 | return op_string; |
10656 | } | |
10657 | ||
252b5132 | 10658 | static int |
70e41ade | 10659 | i386_immediate (char *imm_start) |
252b5132 RH |
10660 | { |
10661 | char *save_input_line_pointer; | |
f3c180ae | 10662 | char *gotfree_input_line; |
252b5132 | 10663 | segT exp_seg = 0; |
47926f60 | 10664 | expressionS *exp; |
40fb9820 L |
10665 | i386_operand_type types; |
10666 | ||
0dfbf9d7 | 10667 | operand_type_set (&types, ~0); |
252b5132 RH |
10668 | |
10669 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
10670 | { | |
31b2323c L |
10671 | as_bad (_("at most %d immediate operands are allowed"), |
10672 | MAX_IMMEDIATE_OPERANDS); | |
252b5132 RH |
10673 | return 0; |
10674 | } | |
10675 | ||
10676 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 10677 | i.op[this_operand].imms = exp; |
252b5132 RH |
10678 | |
10679 | if (is_space_char (*imm_start)) | |
10680 | ++imm_start; | |
10681 | ||
10682 | save_input_line_pointer = input_line_pointer; | |
10683 | input_line_pointer = imm_start; | |
10684 | ||
d258b828 | 10685 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
10686 | if (gotfree_input_line) |
10687 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
10688 | |
10689 | exp_seg = expression (exp); | |
10690 | ||
83183c0c | 10691 | SKIP_WHITESPACE (); |
252b5132 | 10692 | if (*input_line_pointer) |
f3c180ae | 10693 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
10694 | |
10695 | input_line_pointer = save_input_line_pointer; | |
f3c180ae | 10696 | if (gotfree_input_line) |
ee86248c JB |
10697 | { |
10698 | free (gotfree_input_line); | |
10699 | ||
9aac24b1 | 10700 | if (exp->X_op == O_constant) |
ee86248c JB |
10701 | exp->X_op = O_illegal; |
10702 | } | |
10703 | ||
9aac24b1 JB |
10704 | if (exp_seg == reg_section) |
10705 | { | |
10706 | as_bad (_("illegal immediate register operand %s"), imm_start); | |
10707 | return 0; | |
10708 | } | |
10709 | ||
ee86248c JB |
10710 | return i386_finalize_immediate (exp_seg, exp, types, imm_start); |
10711 | } | |
252b5132 | 10712 | |
ee86248c JB |
10713 | static int |
10714 | i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
10715 | i386_operand_type types, const char *imm_start) | |
10716 | { | |
10717 | if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big) | |
252b5132 | 10718 | { |
313c53d1 L |
10719 | if (imm_start) |
10720 | as_bad (_("missing or invalid immediate expression `%s'"), | |
10721 | imm_start); | |
3992d3b7 | 10722 | return 0; |
252b5132 | 10723 | } |
3e73aa7c | 10724 | else if (exp->X_op == O_constant) |
252b5132 | 10725 | { |
47926f60 | 10726 | /* Size it properly later. */ |
40fb9820 | 10727 | i.types[this_operand].bitfield.imm64 = 1; |
a442cac5 JB |
10728 | |
10729 | /* If not 64bit, sign/zero extend val, to account for wraparound | |
10730 | when !BFD64. */ | |
10731 | if (flag_code != CODE_64BIT) | |
10732 | exp->X_add_number = extend_to_32bit_address (exp->X_add_number); | |
252b5132 | 10733 | } |
4c63da97 | 10734 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
f86103b7 | 10735 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 10736 | && exp_seg != absolute_section |
47926f60 | 10737 | && exp_seg != text_section |
24eab124 AM |
10738 | && exp_seg != data_section |
10739 | && exp_seg != bss_section | |
10740 | && exp_seg != undefined_section | |
f86103b7 | 10741 | && !bfd_is_com_section (exp_seg)) |
252b5132 | 10742 | { |
d0b47220 | 10743 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
252b5132 RH |
10744 | return 0; |
10745 | } | |
10746 | #endif | |
10747 | else | |
10748 | { | |
10749 | /* This is an address. The size of the address will be | |
24eab124 | 10750 | determined later, depending on destination register, |
3e73aa7c | 10751 | suffix, or the default for the section. */ |
40fb9820 L |
10752 | i.types[this_operand].bitfield.imm8 = 1; |
10753 | i.types[this_operand].bitfield.imm16 = 1; | |
10754 | i.types[this_operand].bitfield.imm32 = 1; | |
10755 | i.types[this_operand].bitfield.imm32s = 1; | |
10756 | i.types[this_operand].bitfield.imm64 = 1; | |
c6fb90c8 L |
10757 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
10758 | types); | |
252b5132 RH |
10759 | } |
10760 | ||
10761 | return 1; | |
10762 | } | |
10763 | ||
551c1ca1 | 10764 | static char * |
e3bb37b5 | 10765 | i386_scale (char *scale) |
252b5132 | 10766 | { |
551c1ca1 AM |
10767 | offsetT val; |
10768 | char *save = input_line_pointer; | |
252b5132 | 10769 | |
551c1ca1 AM |
10770 | input_line_pointer = scale; |
10771 | val = get_absolute_expression (); | |
10772 | ||
10773 | switch (val) | |
252b5132 | 10774 | { |
551c1ca1 | 10775 | case 1: |
252b5132 RH |
10776 | i.log2_scale_factor = 0; |
10777 | break; | |
551c1ca1 | 10778 | case 2: |
252b5132 RH |
10779 | i.log2_scale_factor = 1; |
10780 | break; | |
551c1ca1 | 10781 | case 4: |
252b5132 RH |
10782 | i.log2_scale_factor = 2; |
10783 | break; | |
551c1ca1 | 10784 | case 8: |
252b5132 RH |
10785 | i.log2_scale_factor = 3; |
10786 | break; | |
10787 | default: | |
a724f0f4 JB |
10788 | { |
10789 | char sep = *input_line_pointer; | |
10790 | ||
10791 | *input_line_pointer = '\0'; | |
10792 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
10793 | scale); | |
10794 | *input_line_pointer = sep; | |
10795 | input_line_pointer = save; | |
10796 | return NULL; | |
10797 | } | |
252b5132 | 10798 | } |
29b0f896 | 10799 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
252b5132 RH |
10800 | { |
10801 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 10802 | 1 << i.log2_scale_factor); |
252b5132 | 10803 | i.log2_scale_factor = 0; |
252b5132 | 10804 | } |
551c1ca1 AM |
10805 | scale = input_line_pointer; |
10806 | input_line_pointer = save; | |
10807 | return scale; | |
252b5132 RH |
10808 | } |
10809 | ||
252b5132 | 10810 | static int |
e3bb37b5 | 10811 | i386_displacement (char *disp_start, char *disp_end) |
252b5132 | 10812 | { |
29b0f896 | 10813 | expressionS *exp; |
252b5132 RH |
10814 | segT exp_seg = 0; |
10815 | char *save_input_line_pointer; | |
f3c180ae | 10816 | char *gotfree_input_line; |
40fb9820 L |
10817 | int override; |
10818 | i386_operand_type bigdisp, types = anydisp; | |
3992d3b7 | 10819 | int ret; |
252b5132 | 10820 | |
31b2323c L |
10821 | if (i.disp_operands == MAX_MEMORY_OPERANDS) |
10822 | { | |
10823 | as_bad (_("at most %d displacement operands are allowed"), | |
10824 | MAX_MEMORY_OPERANDS); | |
10825 | return 0; | |
10826 | } | |
10827 | ||
0dfbf9d7 | 10828 | operand_type_set (&bigdisp, 0); |
6f2f06be | 10829 | if (i.jumpabsolute |
48bcea9f | 10830 | || i.types[this_operand].bitfield.baseindex |
0cfa3eb3 JB |
10831 | || (current_templates->start->opcode_modifier.jump != JUMP |
10832 | && current_templates->start->opcode_modifier.jump != JUMP_DWORD)) | |
e05278af | 10833 | { |
48bcea9f | 10834 | i386_addressing_mode (); |
e05278af | 10835 | override = (i.prefix[ADDR_PREFIX] != 0); |
40fb9820 L |
10836 | if (flag_code == CODE_64BIT) |
10837 | { | |
10838 | if (!override) | |
10839 | { | |
10840 | bigdisp.bitfield.disp32s = 1; | |
10841 | bigdisp.bitfield.disp64 = 1; | |
10842 | } | |
48bcea9f JB |
10843 | else |
10844 | bigdisp.bitfield.disp32 = 1; | |
40fb9820 L |
10845 | } |
10846 | else if ((flag_code == CODE_16BIT) ^ override) | |
40fb9820 | 10847 | bigdisp.bitfield.disp16 = 1; |
48bcea9f JB |
10848 | else |
10849 | bigdisp.bitfield.disp32 = 1; | |
e05278af JB |
10850 | } |
10851 | else | |
10852 | { | |
376cd056 JB |
10853 | /* For PC-relative branches, the width of the displacement may be |
10854 | dependent upon data size, but is never dependent upon address size. | |
10855 | Also make sure to not unintentionally match against a non-PC-relative | |
10856 | branch template. */ | |
10857 | static templates aux_templates; | |
10858 | const insn_template *t = current_templates->start; | |
5b7c81bd | 10859 | bool has_intel64 = false; |
376cd056 JB |
10860 | |
10861 | aux_templates.start = t; | |
10862 | while (++t < current_templates->end) | |
10863 | { | |
10864 | if (t->opcode_modifier.jump | |
10865 | != current_templates->start->opcode_modifier.jump) | |
10866 | break; | |
4b5aaf5f | 10867 | if ((t->opcode_modifier.isa64 >= INTEL64)) |
5b7c81bd | 10868 | has_intel64 = true; |
376cd056 JB |
10869 | } |
10870 | if (t < current_templates->end) | |
10871 | { | |
10872 | aux_templates.end = t; | |
10873 | current_templates = &aux_templates; | |
10874 | } | |
10875 | ||
e05278af | 10876 | override = (i.prefix[DATA_PREFIX] != 0); |
40fb9820 L |
10877 | if (flag_code == CODE_64BIT) |
10878 | { | |
376cd056 JB |
10879 | if ((override || i.suffix == WORD_MNEM_SUFFIX) |
10880 | && (!intel64 || !has_intel64)) | |
40fb9820 L |
10881 | bigdisp.bitfield.disp16 = 1; |
10882 | else | |
48bcea9f | 10883 | bigdisp.bitfield.disp32s = 1; |
40fb9820 L |
10884 | } |
10885 | else | |
e05278af JB |
10886 | { |
10887 | if (!override) | |
10888 | override = (i.suffix == (flag_code != CODE_16BIT | |
10889 | ? WORD_MNEM_SUFFIX | |
10890 | : LONG_MNEM_SUFFIX)); | |
40fb9820 L |
10891 | bigdisp.bitfield.disp32 = 1; |
10892 | if ((flag_code == CODE_16BIT) ^ override) | |
10893 | { | |
10894 | bigdisp.bitfield.disp32 = 0; | |
10895 | bigdisp.bitfield.disp16 = 1; | |
10896 | } | |
e05278af | 10897 | } |
e05278af | 10898 | } |
c6fb90c8 L |
10899 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
10900 | bigdisp); | |
252b5132 RH |
10901 | |
10902 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 10903 | i.op[this_operand].disps = exp; |
252b5132 RH |
10904 | i.disp_operands++; |
10905 | save_input_line_pointer = input_line_pointer; | |
10906 | input_line_pointer = disp_start; | |
10907 | END_STRING_AND_SAVE (disp_end); | |
10908 | ||
10909 | #ifndef GCC_ASM_O_HACK | |
10910 | #define GCC_ASM_O_HACK 0 | |
10911 | #endif | |
10912 | #if GCC_ASM_O_HACK | |
10913 | END_STRING_AND_SAVE (disp_end + 1); | |
40fb9820 | 10914 | if (i.types[this_operand].bitfield.baseIndex |
24eab124 | 10915 | && displacement_string_end[-1] == '+') |
252b5132 RH |
10916 | { |
10917 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
10918 | constraint within gcc asm statements. |
10919 | For instance: | |
10920 | ||
10921 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
10922 | __asm__ __volatile__ ( \ | |
10923 | "movw %w2,%0\n\t" \ | |
10924 | "movw %w1,2+%0\n\t" \ | |
10925 | "rorl $16,%1\n\t" \ | |
10926 | "movb %b1,4+%0\n\t" \ | |
10927 | "movb %4,5+%0\n\t" \ | |
10928 | "movb $0,6+%0\n\t" \ | |
10929 | "movb %h1,7+%0\n\t" \ | |
10930 | "rorl $16,%1" \ | |
10931 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
10932 | ||
10933 | This works great except that the output assembler ends | |
10934 | up looking a bit weird if it turns out that there is | |
10935 | no offset. You end up producing code that looks like: | |
10936 | ||
10937 | #APP | |
10938 | movw $235,(%eax) | |
10939 | movw %dx,2+(%eax) | |
10940 | rorl $16,%edx | |
10941 | movb %dl,4+(%eax) | |
10942 | movb $137,5+(%eax) | |
10943 | movb $0,6+(%eax) | |
10944 | movb %dh,7+(%eax) | |
10945 | rorl $16,%edx | |
10946 | #NO_APP | |
10947 | ||
47926f60 | 10948 | So here we provide the missing zero. */ |
24eab124 AM |
10949 | |
10950 | *displacement_string_end = '0'; | |
252b5132 RH |
10951 | } |
10952 | #endif | |
d258b828 | 10953 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
10954 | if (gotfree_input_line) |
10955 | input_line_pointer = gotfree_input_line; | |
252b5132 | 10956 | |
24eab124 | 10957 | exp_seg = expression (exp); |
252b5132 | 10958 | |
636c26b0 AM |
10959 | SKIP_WHITESPACE (); |
10960 | if (*input_line_pointer) | |
10961 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
10962 | #if GCC_ASM_O_HACK | |
10963 | RESTORE_END_STRING (disp_end + 1); | |
10964 | #endif | |
636c26b0 | 10965 | input_line_pointer = save_input_line_pointer; |
636c26b0 | 10966 | if (gotfree_input_line) |
ee86248c JB |
10967 | { |
10968 | free (gotfree_input_line); | |
10969 | ||
10970 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
10971 | exp->X_op = O_illegal; | |
10972 | } | |
10973 | ||
10974 | ret = i386_finalize_displacement (exp_seg, exp, types, disp_start); | |
10975 | ||
10976 | RESTORE_END_STRING (disp_end); | |
10977 | ||
10978 | return ret; | |
10979 | } | |
10980 | ||
10981 | static int | |
10982 | i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
10983 | i386_operand_type types, const char *disp_start) | |
10984 | { | |
10985 | i386_operand_type bigdisp; | |
10986 | int ret = 1; | |
636c26b0 | 10987 | |
24eab124 AM |
10988 | /* We do this to make sure that the section symbol is in |
10989 | the symbol table. We will ultimately change the relocation | |
47926f60 | 10990 | to be relative to the beginning of the section. */ |
1ae12ab7 | 10991 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
d6ab8113 JB |
10992 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
10993 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) | |
24eab124 | 10994 | { |
636c26b0 | 10995 | if (exp->X_op != O_symbol) |
3992d3b7 | 10996 | goto inv_disp; |
636c26b0 | 10997 | |
e5cb08ac | 10998 | if (S_IS_LOCAL (exp->X_add_symbol) |
c64efb4b L |
10999 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section |
11000 | && S_GET_SEGMENT (exp->X_add_symbol) != expr_section) | |
24eab124 | 11001 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); |
24eab124 AM |
11002 | exp->X_op = O_subtract; |
11003 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 | 11004 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
29b0f896 | 11005 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
d6ab8113 JB |
11006 | else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
11007 | i.reloc[this_operand] = BFD_RELOC_64; | |
23df1078 | 11008 | else |
29b0f896 | 11009 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 11010 | } |
252b5132 | 11011 | |
3992d3b7 AM |
11012 | else if (exp->X_op == O_absent |
11013 | || exp->X_op == O_illegal | |
ee86248c | 11014 | || exp->X_op == O_big) |
2daf4fd8 | 11015 | { |
3992d3b7 AM |
11016 | inv_disp: |
11017 | as_bad (_("missing or invalid displacement expression `%s'"), | |
2daf4fd8 | 11018 | disp_start); |
3992d3b7 | 11019 | ret = 0; |
2daf4fd8 AM |
11020 | } |
11021 | ||
4c63da97 | 11022 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
3992d3b7 AM |
11023 | else if (exp->X_op != O_constant |
11024 | && OUTPUT_FLAVOR == bfd_target_aout_flavour | |
11025 | && exp_seg != absolute_section | |
11026 | && exp_seg != text_section | |
11027 | && exp_seg != data_section | |
11028 | && exp_seg != bss_section | |
11029 | && exp_seg != undefined_section | |
11030 | && !bfd_is_com_section (exp_seg)) | |
24eab124 | 11031 | { |
d0b47220 | 11032 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
3992d3b7 | 11033 | ret = 0; |
24eab124 | 11034 | } |
252b5132 | 11035 | #endif |
3956db08 | 11036 | |
48bcea9f JB |
11037 | if (current_templates->start->opcode_modifier.jump == JUMP_BYTE |
11038 | /* Constants get taken care of by optimize_disp(). */ | |
11039 | && exp->X_op != O_constant) | |
11040 | i.types[this_operand].bitfield.disp8 = 1; | |
11041 | ||
40fb9820 L |
11042 | /* Check if this is a displacement only operand. */ |
11043 | bigdisp = i.types[this_operand]; | |
11044 | bigdisp.bitfield.disp8 = 0; | |
11045 | bigdisp.bitfield.disp16 = 0; | |
11046 | bigdisp.bitfield.disp32 = 0; | |
11047 | bigdisp.bitfield.disp32s = 0; | |
11048 | bigdisp.bitfield.disp64 = 0; | |
0dfbf9d7 | 11049 | if (operand_type_all_zero (&bigdisp)) |
c6fb90c8 L |
11050 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
11051 | types); | |
3956db08 | 11052 | |
3992d3b7 | 11053 | return ret; |
252b5132 RH |
11054 | } |
11055 | ||
2abc2bec JB |
11056 | /* Return the active addressing mode, taking address override and |
11057 | registers forming the address into consideration. Update the | |
11058 | address override prefix if necessary. */ | |
47926f60 | 11059 | |
2abc2bec JB |
11060 | static enum flag_code |
11061 | i386_addressing_mode (void) | |
252b5132 | 11062 | { |
be05d201 L |
11063 | enum flag_code addr_mode; |
11064 | ||
11065 | if (i.prefix[ADDR_PREFIX]) | |
11066 | addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT; | |
a23b33b3 JB |
11067 | else if (flag_code == CODE_16BIT |
11068 | && current_templates->start->cpu_flags.bitfield.cpumpx | |
11069 | /* Avoid replacing the "16-bit addressing not allowed" diagnostic | |
11070 | from md_assemble() by "is not a valid base/index expression" | |
11071 | when there is a base and/or index. */ | |
11072 | && !i.types[this_operand].bitfield.baseindex) | |
11073 | { | |
11074 | /* MPX insn memory operands with neither base nor index must be forced | |
11075 | to use 32-bit addressing in 16-bit mode. */ | |
11076 | addr_mode = CODE_32BIT; | |
11077 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
11078 | ++i.prefixes; | |
11079 | gas_assert (!i.types[this_operand].bitfield.disp16); | |
11080 | gas_assert (!i.types[this_operand].bitfield.disp32); | |
11081 | } | |
be05d201 L |
11082 | else |
11083 | { | |
11084 | addr_mode = flag_code; | |
11085 | ||
24eab124 | 11086 | #if INFER_ADDR_PREFIX |
be05d201 L |
11087 | if (i.mem_operands == 0) |
11088 | { | |
11089 | /* Infer address prefix from the first memory operand. */ | |
11090 | const reg_entry *addr_reg = i.base_reg; | |
11091 | ||
11092 | if (addr_reg == NULL) | |
11093 | addr_reg = i.index_reg; | |
eecb386c | 11094 | |
be05d201 L |
11095 | if (addr_reg) |
11096 | { | |
e968fc9b | 11097 | if (addr_reg->reg_type.bitfield.dword) |
be05d201 L |
11098 | addr_mode = CODE_32BIT; |
11099 | else if (flag_code != CODE_64BIT | |
dc821c5f | 11100 | && addr_reg->reg_type.bitfield.word) |
be05d201 L |
11101 | addr_mode = CODE_16BIT; |
11102 | ||
11103 | if (addr_mode != flag_code) | |
11104 | { | |
11105 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
11106 | i.prefixes += 1; | |
11107 | /* Change the size of any displacement too. At most one | |
11108 | of Disp16 or Disp32 is set. | |
11109 | FIXME. There doesn't seem to be any real need for | |
11110 | separate Disp16 and Disp32 flags. The same goes for | |
11111 | Imm16 and Imm32. Removing them would probably clean | |
11112 | up the code quite a lot. */ | |
11113 | if (flag_code != CODE_64BIT | |
11114 | && (i.types[this_operand].bitfield.disp16 | |
11115 | || i.types[this_operand].bitfield.disp32)) | |
11116 | i.types[this_operand] | |
11117 | = operand_type_xor (i.types[this_operand], disp16_32); | |
11118 | } | |
11119 | } | |
11120 | } | |
24eab124 | 11121 | #endif |
be05d201 L |
11122 | } |
11123 | ||
2abc2bec JB |
11124 | return addr_mode; |
11125 | } | |
11126 | ||
11127 | /* Make sure the memory operand we've been dealt is valid. | |
11128 | Return 1 on success, 0 on a failure. */ | |
11129 | ||
11130 | static int | |
11131 | i386_index_check (const char *operand_string) | |
11132 | { | |
11133 | const char *kind = "base/index"; | |
11134 | enum flag_code addr_mode = i386_addressing_mode (); | |
a152332d | 11135 | const insn_template *t = current_templates->start; |
2abc2bec | 11136 | |
a152332d JB |
11137 | if (t->opcode_modifier.isstring |
11138 | && !t->cpu_flags.bitfield.cpupadlock | |
fc0763e6 JB |
11139 | && (current_templates->end[-1].opcode_modifier.isstring |
11140 | || i.mem_operands)) | |
11141 | { | |
11142 | /* Memory operands of string insns are special in that they only allow | |
11143 | a single register (rDI, rSI, or rBX) as their memory address. */ | |
be05d201 L |
11144 | const reg_entry *expected_reg; |
11145 | static const char *di_si[][2] = | |
11146 | { | |
11147 | { "esi", "edi" }, | |
11148 | { "si", "di" }, | |
11149 | { "rsi", "rdi" } | |
11150 | }; | |
11151 | static const char *bx[] = { "ebx", "bx", "rbx" }; | |
fc0763e6 JB |
11152 | |
11153 | kind = "string address"; | |
11154 | ||
a152332d | 11155 | if (t->opcode_modifier.prefixok == PrefixRep) |
fc0763e6 | 11156 | { |
51c8edf6 JB |
11157 | int es_op = current_templates->end[-1].opcode_modifier.isstring |
11158 | - IS_STRING_ES_OP0; | |
11159 | int op = 0; | |
fc0763e6 | 11160 | |
51c8edf6 | 11161 | if (!current_templates->end[-1].operand_types[0].bitfield.baseindex |
fc0763e6 JB |
11162 | || ((!i.mem_operands != !intel_syntax) |
11163 | && current_templates->end[-1].operand_types[1] | |
11164 | .bitfield.baseindex)) | |
51c8edf6 | 11165 | op = 1; |
fe0e921f AM |
11166 | expected_reg |
11167 | = (const reg_entry *) str_hash_find (reg_hash, | |
11168 | di_si[addr_mode][op == es_op]); | |
fc0763e6 JB |
11169 | } |
11170 | else | |
fe0e921f AM |
11171 | expected_reg |
11172 | = (const reg_entry *)str_hash_find (reg_hash, bx[addr_mode]); | |
fc0763e6 | 11173 | |
be05d201 L |
11174 | if (i.base_reg != expected_reg |
11175 | || i.index_reg | |
fc0763e6 | 11176 | || operand_type_check (i.types[this_operand], disp)) |
fc0763e6 | 11177 | { |
be05d201 L |
11178 | /* The second memory operand must have the same size as |
11179 | the first one. */ | |
11180 | if (i.mem_operands | |
11181 | && i.base_reg | |
11182 | && !((addr_mode == CODE_64BIT | |
dc821c5f | 11183 | && i.base_reg->reg_type.bitfield.qword) |
be05d201 | 11184 | || (addr_mode == CODE_32BIT |
dc821c5f JB |
11185 | ? i.base_reg->reg_type.bitfield.dword |
11186 | : i.base_reg->reg_type.bitfield.word))) | |
be05d201 L |
11187 | goto bad_address; |
11188 | ||
fc0763e6 JB |
11189 | as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"), |
11190 | operand_string, | |
11191 | intel_syntax ? '[' : '(', | |
11192 | register_prefix, | |
be05d201 | 11193 | expected_reg->reg_name, |
fc0763e6 | 11194 | intel_syntax ? ']' : ')'); |
be05d201 | 11195 | return 1; |
fc0763e6 | 11196 | } |
be05d201 L |
11197 | else |
11198 | return 1; | |
11199 | ||
dc1e8a47 | 11200 | bad_address: |
be05d201 L |
11201 | as_bad (_("`%s' is not a valid %s expression"), |
11202 | operand_string, kind); | |
11203 | return 0; | |
3e73aa7c JH |
11204 | } |
11205 | else | |
11206 | { | |
be05d201 L |
11207 | if (addr_mode != CODE_16BIT) |
11208 | { | |
11209 | /* 32-bit/64-bit checks. */ | |
41eb8e88 L |
11210 | if (i.disp_encoding == disp_encoding_16bit) |
11211 | { | |
11212 | bad_disp: | |
11213 | as_bad (_("invalid `%s' prefix"), | |
11214 | addr_mode == CODE_16BIT ? "{disp32}" : "{disp16}"); | |
11215 | return 0; | |
11216 | } | |
11217 | ||
be05d201 | 11218 | if ((i.base_reg |
e968fc9b JB |
11219 | && ((addr_mode == CODE_64BIT |
11220 | ? !i.base_reg->reg_type.bitfield.qword | |
11221 | : !i.base_reg->reg_type.bitfield.dword) | |
11222 | || (i.index_reg && i.base_reg->reg_num == RegIP) | |
11223 | || i.base_reg->reg_num == RegIZ)) | |
be05d201 | 11224 | || (i.index_reg |
1b54b8d7 JB |
11225 | && !i.index_reg->reg_type.bitfield.xmmword |
11226 | && !i.index_reg->reg_type.bitfield.ymmword | |
11227 | && !i.index_reg->reg_type.bitfield.zmmword | |
be05d201 | 11228 | && ((addr_mode == CODE_64BIT |
e968fc9b JB |
11229 | ? !i.index_reg->reg_type.bitfield.qword |
11230 | : !i.index_reg->reg_type.bitfield.dword) | |
be05d201 L |
11231 | || !i.index_reg->reg_type.bitfield.baseindex))) |
11232 | goto bad_address; | |
8178be5b | 11233 | |
260cd341 | 11234 | /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */ |
a152332d | 11235 | if ((t->opcode_modifier.opcodeprefix == PREFIX_0XF3 |
389d00a5 JB |
11236 | && t->opcode_modifier.opcodespace == SPACE_0F |
11237 | && t->base_opcode == 0x1b) | |
a152332d | 11238 | || (t->opcode_modifier.opcodeprefix == PREFIX_NONE |
389d00a5 JB |
11239 | && t->opcode_modifier.opcodespace == SPACE_0F |
11240 | && (t->base_opcode & ~1) == 0x1a) | |
a152332d | 11241 | || t->opcode_modifier.sib == SIBMEM) |
8178be5b JB |
11242 | { |
11243 | /* They cannot use RIP-relative addressing. */ | |
e968fc9b | 11244 | if (i.base_reg && i.base_reg->reg_num == RegIP) |
8178be5b JB |
11245 | { |
11246 | as_bad (_("`%s' cannot be used here"), operand_string); | |
11247 | return 0; | |
11248 | } | |
11249 | ||
11250 | /* bndldx and bndstx ignore their scale factor. */ | |
a152332d | 11251 | if (t->opcode_modifier.opcodeprefix == PREFIX_NONE |
389d00a5 JB |
11252 | && t->opcode_modifier.opcodespace == SPACE_0F |
11253 | && (t->base_opcode & ~1) == 0x1a | |
8178be5b JB |
11254 | && i.log2_scale_factor) |
11255 | as_warn (_("register scaling is being ignored here")); | |
11256 | } | |
be05d201 L |
11257 | } |
11258 | else | |
3e73aa7c | 11259 | { |
be05d201 | 11260 | /* 16-bit checks. */ |
41eb8e88 L |
11261 | if (i.disp_encoding == disp_encoding_32bit) |
11262 | goto bad_disp; | |
11263 | ||
3e73aa7c | 11264 | if ((i.base_reg |
dc821c5f | 11265 | && (!i.base_reg->reg_type.bitfield.word |
40fb9820 | 11266 | || !i.base_reg->reg_type.bitfield.baseindex)) |
3e73aa7c | 11267 | || (i.index_reg |
dc821c5f | 11268 | && (!i.index_reg->reg_type.bitfield.word |
40fb9820 | 11269 | || !i.index_reg->reg_type.bitfield.baseindex |
29b0f896 AM |
11270 | || !(i.base_reg |
11271 | && i.base_reg->reg_num < 6 | |
11272 | && i.index_reg->reg_num >= 6 | |
11273 | && i.log2_scale_factor == 0)))) | |
be05d201 | 11274 | goto bad_address; |
3e73aa7c JH |
11275 | } |
11276 | } | |
be05d201 | 11277 | return 1; |
24eab124 | 11278 | } |
252b5132 | 11279 | |
43234a1e L |
11280 | /* Handle vector immediates. */ |
11281 | ||
11282 | static int | |
11283 | RC_SAE_immediate (const char *imm_start) | |
11284 | { | |
11285 | unsigned int match_found, j; | |
11286 | const char *pstr = imm_start; | |
11287 | expressionS *exp; | |
11288 | ||
11289 | if (*pstr != '{') | |
11290 | return 0; | |
11291 | ||
11292 | pstr++; | |
11293 | match_found = 0; | |
11294 | for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++) | |
11295 | { | |
11296 | if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len)) | |
11297 | { | |
ca5312a2 | 11298 | if (i.rounding.type != rc_none) |
43234a1e L |
11299 | { |
11300 | as_bad (_("duplicated `%s'"), imm_start); | |
11301 | return 0; | |
11302 | } | |
ca5312a2 JB |
11303 | |
11304 | i.rounding.type = RC_NamesTable[j].type; | |
11305 | i.rounding.operand = this_operand; | |
11306 | ||
43234a1e L |
11307 | pstr += RC_NamesTable[j].len; |
11308 | match_found = 1; | |
11309 | break; | |
11310 | } | |
11311 | } | |
11312 | if (!match_found) | |
11313 | return 0; | |
11314 | ||
11315 | if (*pstr++ != '}') | |
11316 | { | |
11317 | as_bad (_("Missing '}': '%s'"), imm_start); | |
11318 | return 0; | |
11319 | } | |
11320 | /* RC/SAE immediate string should contain nothing more. */; | |
11321 | if (*pstr != 0) | |
11322 | { | |
11323 | as_bad (_("Junk after '}': '%s'"), imm_start); | |
11324 | return 0; | |
11325 | } | |
11326 | ||
11327 | exp = &im_expressions[i.imm_operands++]; | |
11328 | i.op[this_operand].imms = exp; | |
11329 | ||
11330 | exp->X_op = O_constant; | |
11331 | exp->X_add_number = 0; | |
11332 | exp->X_add_symbol = (symbolS *) 0; | |
11333 | exp->X_op_symbol = (symbolS *) 0; | |
11334 | ||
11335 | i.types[this_operand].bitfield.imm8 = 1; | |
11336 | return 1; | |
11337 | } | |
11338 | ||
8325cc63 JB |
11339 | /* Only string instructions can have a second memory operand, so |
11340 | reduce current_templates to just those if it contains any. */ | |
11341 | static int | |
11342 | maybe_adjust_templates (void) | |
11343 | { | |
11344 | const insn_template *t; | |
11345 | ||
11346 | gas_assert (i.mem_operands == 1); | |
11347 | ||
11348 | for (t = current_templates->start; t < current_templates->end; ++t) | |
11349 | if (t->opcode_modifier.isstring) | |
11350 | break; | |
11351 | ||
11352 | if (t < current_templates->end) | |
11353 | { | |
11354 | static templates aux_templates; | |
5b7c81bd | 11355 | bool recheck; |
8325cc63 JB |
11356 | |
11357 | aux_templates.start = t; | |
11358 | for (; t < current_templates->end; ++t) | |
11359 | if (!t->opcode_modifier.isstring) | |
11360 | break; | |
11361 | aux_templates.end = t; | |
11362 | ||
11363 | /* Determine whether to re-check the first memory operand. */ | |
11364 | recheck = (aux_templates.start != current_templates->start | |
11365 | || t != current_templates->end); | |
11366 | ||
11367 | current_templates = &aux_templates; | |
11368 | ||
11369 | if (recheck) | |
11370 | { | |
11371 | i.mem_operands = 0; | |
11372 | if (i.memop1_string != NULL | |
11373 | && i386_index_check (i.memop1_string) == 0) | |
11374 | return 0; | |
11375 | i.mem_operands = 1; | |
11376 | } | |
11377 | } | |
11378 | ||
11379 | return 1; | |
11380 | } | |
11381 | ||
fc0763e6 | 11382 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero |
47926f60 | 11383 | on error. */ |
252b5132 | 11384 | |
252b5132 | 11385 | static int |
a7619375 | 11386 | i386_att_operand (char *operand_string) |
252b5132 | 11387 | { |
af6bdddf AM |
11388 | const reg_entry *r; |
11389 | char *end_op; | |
24eab124 | 11390 | char *op_string = operand_string; |
252b5132 | 11391 | |
24eab124 | 11392 | if (is_space_char (*op_string)) |
252b5132 RH |
11393 | ++op_string; |
11394 | ||
24eab124 | 11395 | /* We check for an absolute prefix (differentiating, |
47926f60 | 11396 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
11397 | if (*op_string == ABSOLUTE_PREFIX) |
11398 | { | |
11399 | ++op_string; | |
11400 | if (is_space_char (*op_string)) | |
11401 | ++op_string; | |
5b7c81bd | 11402 | i.jumpabsolute = true; |
24eab124 | 11403 | } |
252b5132 | 11404 | |
47926f60 | 11405 | /* Check if operand is a register. */ |
4d1bb795 | 11406 | if ((r = parse_register (op_string, &end_op)) != NULL) |
24eab124 | 11407 | { |
40fb9820 L |
11408 | i386_operand_type temp; |
11409 | ||
8a6fb3f9 JB |
11410 | if (r == &bad_reg) |
11411 | return 0; | |
11412 | ||
24eab124 AM |
11413 | /* Check for a segment override by searching for ':' after a |
11414 | segment register. */ | |
11415 | op_string = end_op; | |
11416 | if (is_space_char (*op_string)) | |
11417 | ++op_string; | |
00cee14f | 11418 | if (*op_string == ':' && r->reg_type.bitfield.class == SReg) |
24eab124 | 11419 | { |
5e042380 | 11420 | i.seg[i.mem_operands] = r; |
252b5132 | 11421 | |
24eab124 | 11422 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
11423 | ++op_string; |
11424 | if (is_space_char (*op_string)) | |
24eab124 | 11425 | ++op_string; |
252b5132 | 11426 | |
24eab124 AM |
11427 | if (!is_digit_char (*op_string) |
11428 | && !is_identifier_char (*op_string) | |
11429 | && *op_string != '(' | |
11430 | && *op_string != ABSOLUTE_PREFIX) | |
11431 | { | |
11432 | as_bad (_("bad memory operand `%s'"), op_string); | |
11433 | return 0; | |
11434 | } | |
47926f60 | 11435 | /* Handle case of %es:*foo. */ |
24eab124 AM |
11436 | if (*op_string == ABSOLUTE_PREFIX) |
11437 | { | |
11438 | ++op_string; | |
11439 | if (is_space_char (*op_string)) | |
11440 | ++op_string; | |
5b7c81bd | 11441 | i.jumpabsolute = true; |
24eab124 AM |
11442 | } |
11443 | goto do_memory_reference; | |
11444 | } | |
43234a1e L |
11445 | |
11446 | /* Handle vector operations. */ | |
11447 | if (*op_string == '{') | |
11448 | { | |
11449 | op_string = check_VecOperations (op_string, NULL); | |
11450 | if (op_string == NULL) | |
11451 | return 0; | |
11452 | } | |
11453 | ||
24eab124 AM |
11454 | if (*op_string) |
11455 | { | |
d0b47220 | 11456 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
11457 | return 0; |
11458 | } | |
40fb9820 L |
11459 | temp = r->reg_type; |
11460 | temp.bitfield.baseindex = 0; | |
c6fb90c8 L |
11461 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
11462 | temp); | |
7d5e4556 | 11463 | i.types[this_operand].bitfield.unspecified = 0; |
520dc8e8 | 11464 | i.op[this_operand].regs = r; |
24eab124 AM |
11465 | i.reg_operands++; |
11466 | } | |
af6bdddf AM |
11467 | else if (*op_string == REGISTER_PREFIX) |
11468 | { | |
11469 | as_bad (_("bad register name `%s'"), op_string); | |
11470 | return 0; | |
11471 | } | |
24eab124 | 11472 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 11473 | { |
24eab124 | 11474 | ++op_string; |
6f2f06be | 11475 | if (i.jumpabsolute) |
24eab124 | 11476 | { |
d0b47220 | 11477 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
11478 | return 0; |
11479 | } | |
11480 | if (!i386_immediate (op_string)) | |
11481 | return 0; | |
11482 | } | |
43234a1e L |
11483 | else if (RC_SAE_immediate (operand_string)) |
11484 | { | |
11485 | /* If it is a RC or SAE immediate, do nothing. */ | |
11486 | ; | |
11487 | } | |
24eab124 AM |
11488 | else if (is_digit_char (*op_string) |
11489 | || is_identifier_char (*op_string) | |
d02603dc | 11490 | || *op_string == '"' |
e5cb08ac | 11491 | || *op_string == '(') |
24eab124 | 11492 | { |
47926f60 | 11493 | /* This is a memory reference of some sort. */ |
af6bdddf | 11494 | char *base_string; |
252b5132 | 11495 | |
47926f60 | 11496 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
11497 | char *displacement_string_start; |
11498 | char *displacement_string_end; | |
43234a1e | 11499 | char *vop_start; |
252b5132 | 11500 | |
24eab124 | 11501 | do_memory_reference: |
8325cc63 JB |
11502 | if (i.mem_operands == 1 && !maybe_adjust_templates ()) |
11503 | return 0; | |
24eab124 | 11504 | if ((i.mem_operands == 1 |
40fb9820 | 11505 | && !current_templates->start->opcode_modifier.isstring) |
24eab124 AM |
11506 | || i.mem_operands == 2) |
11507 | { | |
11508 | as_bad (_("too many memory references for `%s'"), | |
11509 | current_templates->start->name); | |
11510 | return 0; | |
11511 | } | |
252b5132 | 11512 | |
24eab124 AM |
11513 | /* Check for base index form. We detect the base index form by |
11514 | looking for an ')' at the end of the operand, searching | |
11515 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
11516 | after the '('. */ | |
af6bdddf | 11517 | base_string = op_string + strlen (op_string); |
c3332e24 | 11518 | |
43234a1e L |
11519 | /* Handle vector operations. */ |
11520 | vop_start = strchr (op_string, '{'); | |
11521 | if (vop_start && vop_start < base_string) | |
11522 | { | |
11523 | if (check_VecOperations (vop_start, base_string) == NULL) | |
11524 | return 0; | |
11525 | base_string = vop_start; | |
11526 | } | |
11527 | ||
af6bdddf AM |
11528 | --base_string; |
11529 | if (is_space_char (*base_string)) | |
11530 | --base_string; | |
252b5132 | 11531 | |
47926f60 | 11532 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
11533 | displacement_string_start = op_string; |
11534 | displacement_string_end = base_string + 1; | |
252b5132 | 11535 | |
24eab124 AM |
11536 | if (*base_string == ')') |
11537 | { | |
af6bdddf | 11538 | char *temp_string; |
24eab124 AM |
11539 | unsigned int parens_balanced = 1; |
11540 | /* We've already checked that the number of left & right ()'s are | |
47926f60 | 11541 | equal, so this loop will not be infinite. */ |
24eab124 AM |
11542 | do |
11543 | { | |
11544 | base_string--; | |
11545 | if (*base_string == ')') | |
11546 | parens_balanced++; | |
11547 | if (*base_string == '(') | |
11548 | parens_balanced--; | |
11549 | } | |
11550 | while (parens_balanced); | |
c3332e24 | 11551 | |
af6bdddf | 11552 | temp_string = base_string; |
c3332e24 | 11553 | |
24eab124 | 11554 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
11555 | ++base_string; |
11556 | if (is_space_char (*base_string)) | |
24eab124 | 11557 | ++base_string; |
252b5132 | 11558 | |
af6bdddf | 11559 | if (*base_string == ',' |
4eed87de AM |
11560 | || ((i.base_reg = parse_register (base_string, &end_op)) |
11561 | != NULL)) | |
252b5132 | 11562 | { |
af6bdddf | 11563 | displacement_string_end = temp_string; |
252b5132 | 11564 | |
40fb9820 | 11565 | i.types[this_operand].bitfield.baseindex = 1; |
252b5132 | 11566 | |
af6bdddf | 11567 | if (i.base_reg) |
24eab124 | 11568 | { |
8a6fb3f9 JB |
11569 | if (i.base_reg == &bad_reg) |
11570 | return 0; | |
24eab124 AM |
11571 | base_string = end_op; |
11572 | if (is_space_char (*base_string)) | |
11573 | ++base_string; | |
af6bdddf AM |
11574 | } |
11575 | ||
11576 | /* There may be an index reg or scale factor here. */ | |
11577 | if (*base_string == ',') | |
11578 | { | |
11579 | ++base_string; | |
11580 | if (is_space_char (*base_string)) | |
11581 | ++base_string; | |
11582 | ||
4eed87de AM |
11583 | if ((i.index_reg = parse_register (base_string, &end_op)) |
11584 | != NULL) | |
24eab124 | 11585 | { |
8a6fb3f9 JB |
11586 | if (i.index_reg == &bad_reg) |
11587 | return 0; | |
af6bdddf | 11588 | base_string = end_op; |
24eab124 AM |
11589 | if (is_space_char (*base_string)) |
11590 | ++base_string; | |
af6bdddf AM |
11591 | if (*base_string == ',') |
11592 | { | |
11593 | ++base_string; | |
11594 | if (is_space_char (*base_string)) | |
11595 | ++base_string; | |
11596 | } | |
e5cb08ac | 11597 | else if (*base_string != ')') |
af6bdddf | 11598 | { |
4eed87de AM |
11599 | as_bad (_("expecting `,' or `)' " |
11600 | "after index register in `%s'"), | |
af6bdddf AM |
11601 | operand_string); |
11602 | return 0; | |
11603 | } | |
24eab124 | 11604 | } |
af6bdddf | 11605 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 11606 | { |
f76bf5e0 L |
11607 | end_op = strchr (base_string, ','); |
11608 | if (end_op) | |
11609 | *end_op = '\0'; | |
af6bdddf | 11610 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
11611 | return 0; |
11612 | } | |
252b5132 | 11613 | |
47926f60 | 11614 | /* Check for scale factor. */ |
551c1ca1 | 11615 | if (*base_string != ')') |
af6bdddf | 11616 | { |
551c1ca1 AM |
11617 | char *end_scale = i386_scale (base_string); |
11618 | ||
11619 | if (!end_scale) | |
af6bdddf | 11620 | return 0; |
24eab124 | 11621 | |
551c1ca1 | 11622 | base_string = end_scale; |
af6bdddf AM |
11623 | if (is_space_char (*base_string)) |
11624 | ++base_string; | |
11625 | if (*base_string != ')') | |
11626 | { | |
4eed87de AM |
11627 | as_bad (_("expecting `)' " |
11628 | "after scale factor in `%s'"), | |
af6bdddf AM |
11629 | operand_string); |
11630 | return 0; | |
11631 | } | |
11632 | } | |
11633 | else if (!i.index_reg) | |
24eab124 | 11634 | { |
4eed87de AM |
11635 | as_bad (_("expecting index register or scale factor " |
11636 | "after `,'; got '%c'"), | |
af6bdddf | 11637 | *base_string); |
24eab124 AM |
11638 | return 0; |
11639 | } | |
11640 | } | |
af6bdddf | 11641 | else if (*base_string != ')') |
24eab124 | 11642 | { |
4eed87de AM |
11643 | as_bad (_("expecting `,' or `)' " |
11644 | "after base register in `%s'"), | |
af6bdddf | 11645 | operand_string); |
24eab124 AM |
11646 | return 0; |
11647 | } | |
c3332e24 | 11648 | } |
af6bdddf | 11649 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 11650 | { |
f76bf5e0 L |
11651 | end_op = strchr (base_string, ','); |
11652 | if (end_op) | |
11653 | *end_op = '\0'; | |
af6bdddf | 11654 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 11655 | return 0; |
c3332e24 | 11656 | } |
24eab124 AM |
11657 | } |
11658 | ||
11659 | /* If there's an expression beginning the operand, parse it, | |
11660 | assuming displacement_string_start and | |
11661 | displacement_string_end are meaningful. */ | |
11662 | if (displacement_string_start != displacement_string_end) | |
11663 | { | |
11664 | if (!i386_displacement (displacement_string_start, | |
11665 | displacement_string_end)) | |
11666 | return 0; | |
11667 | } | |
11668 | ||
11669 | /* Special case for (%dx) while doing input/output op. */ | |
11670 | if (i.base_reg | |
75e5731b JB |
11671 | && i.base_reg->reg_type.bitfield.instance == RegD |
11672 | && i.base_reg->reg_type.bitfield.word | |
24eab124 AM |
11673 | && i.index_reg == 0 |
11674 | && i.log2_scale_factor == 0 | |
11675 | && i.seg[i.mem_operands] == 0 | |
40fb9820 | 11676 | && !operand_type_check (i.types[this_operand], disp)) |
24eab124 | 11677 | { |
2fb5be8d | 11678 | i.types[this_operand] = i.base_reg->reg_type; |
24eab124 AM |
11679 | return 1; |
11680 | } | |
11681 | ||
eecb386c AM |
11682 | if (i386_index_check (operand_string) == 0) |
11683 | return 0; | |
c48dadc9 | 11684 | i.flags[this_operand] |= Operand_Mem; |
8325cc63 JB |
11685 | if (i.mem_operands == 0) |
11686 | i.memop1_string = xstrdup (operand_string); | |
24eab124 AM |
11687 | i.mem_operands++; |
11688 | } | |
11689 | else | |
ce8a8b2f AM |
11690 | { |
11691 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
11692 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
11693 | output_invalid (*op_string), | |
11694 | this_operand + 1, | |
11695 | op_string); | |
11696 | return 0; | |
11697 | } | |
47926f60 | 11698 | return 1; /* Normal return. */ |
252b5132 RH |
11699 | } |
11700 | \f | |
fa94de6b RM |
11701 | /* Calculate the maximum variable size (i.e., excluding fr_fix) |
11702 | that an rs_machine_dependent frag may reach. */ | |
11703 | ||
11704 | unsigned int | |
11705 | i386_frag_max_var (fragS *frag) | |
11706 | { | |
11707 | /* The only relaxable frags are for jumps. | |
11708 | Unconditional jumps can grow by 4 bytes and others by 5 bytes. */ | |
11709 | gas_assert (frag->fr_type == rs_machine_dependent); | |
11710 | return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5; | |
11711 | } | |
11712 | ||
b084df0b L |
11713 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
11714 | static int | |
8dcea932 | 11715 | elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var) |
b084df0b L |
11716 | { |
11717 | /* STT_GNU_IFUNC symbol must go through PLT. */ | |
11718 | if ((symbol_get_bfdsym (fr_symbol)->flags | |
11719 | & BSF_GNU_INDIRECT_FUNCTION) != 0) | |
11720 | return 0; | |
11721 | ||
11722 | if (!S_IS_EXTERNAL (fr_symbol)) | |
11723 | /* Symbol may be weak or local. */ | |
11724 | return !S_IS_WEAK (fr_symbol); | |
11725 | ||
8dcea932 L |
11726 | /* Global symbols with non-default visibility can't be preempted. */ |
11727 | if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT) | |
11728 | return 1; | |
11729 | ||
11730 | if (fr_var != NO_RELOC) | |
11731 | switch ((enum bfd_reloc_code_real) fr_var) | |
11732 | { | |
11733 | case BFD_RELOC_386_PLT32: | |
11734 | case BFD_RELOC_X86_64_PLT32: | |
33eaf5de | 11735 | /* Symbol with PLT relocation may be preempted. */ |
8dcea932 L |
11736 | return 0; |
11737 | default: | |
11738 | abort (); | |
11739 | } | |
11740 | ||
b084df0b L |
11741 | /* Global symbols with default visibility in a shared library may be |
11742 | preempted by another definition. */ | |
8dcea932 | 11743 | return !shared; |
b084df0b L |
11744 | } |
11745 | #endif | |
11746 | ||
79d72f45 HL |
11747 | /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture |
11748 | Note also work for Skylake and Cascadelake. | |
11749 | --------------------------------------------------------------------- | |
11750 | | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND | | |
11751 | | ------ | ----------- | ------- | -------- | | |
11752 | | Jo | N | N | Y | | |
11753 | | Jno | N | N | Y | | |
11754 | | Jc/Jb | Y | N | Y | | |
11755 | | Jae/Jnb | Y | N | Y | | |
11756 | | Je/Jz | Y | Y | Y | | |
11757 | | Jne/Jnz | Y | Y | Y | | |
11758 | | Jna/Jbe | Y | N | Y | | |
11759 | | Ja/Jnbe | Y | N | Y | | |
11760 | | Js | N | N | Y | | |
11761 | | Jns | N | N | Y | | |
11762 | | Jp/Jpe | N | N | Y | | |
11763 | | Jnp/Jpo | N | N | Y | | |
11764 | | Jl/Jnge | Y | Y | Y | | |
11765 | | Jge/Jnl | Y | Y | Y | | |
11766 | | Jle/Jng | Y | Y | Y | | |
11767 | | Jg/Jnle | Y | Y | Y | | |
11768 | --------------------------------------------------------------------- */ | |
11769 | static int | |
11770 | i386_macro_fusible_p (enum mf_cmp_kind mf_cmp, enum mf_jcc_kind mf_jcc) | |
11771 | { | |
11772 | if (mf_cmp == mf_cmp_alu_cmp) | |
11773 | return ((mf_jcc >= mf_jcc_jc && mf_jcc <= mf_jcc_jna) | |
11774 | || mf_jcc == mf_jcc_jl || mf_jcc == mf_jcc_jle); | |
11775 | if (mf_cmp == mf_cmp_incdec) | |
11776 | return (mf_jcc == mf_jcc_je || mf_jcc == mf_jcc_jl | |
11777 | || mf_jcc == mf_jcc_jle); | |
11778 | if (mf_cmp == mf_cmp_test_and) | |
11779 | return 1; | |
11780 | return 0; | |
11781 | } | |
11782 | ||
e379e5f3 L |
11783 | /* Return the next non-empty frag. */ |
11784 | ||
11785 | static fragS * | |
11786 | i386_next_non_empty_frag (fragS *fragP) | |
11787 | { | |
11788 | /* There may be a frag with a ".fill 0" when there is no room in | |
11789 | the current frag for frag_grow in output_insn. */ | |
11790 | for (fragP = fragP->fr_next; | |
11791 | (fragP != NULL | |
11792 | && fragP->fr_type == rs_fill | |
11793 | && fragP->fr_fix == 0); | |
11794 | fragP = fragP->fr_next) | |
11795 | ; | |
11796 | return fragP; | |
11797 | } | |
11798 | ||
11799 | /* Return the next jcc frag after BRANCH_PADDING. */ | |
11800 | ||
11801 | static fragS * | |
79d72f45 | 11802 | i386_next_fusible_jcc_frag (fragS *maybe_cmp_fragP, fragS *pad_fragP) |
e379e5f3 | 11803 | { |
79d72f45 HL |
11804 | fragS *branch_fragP; |
11805 | if (!pad_fragP) | |
e379e5f3 L |
11806 | return NULL; |
11807 | ||
79d72f45 HL |
11808 | if (pad_fragP->fr_type == rs_machine_dependent |
11809 | && (TYPE_FROM_RELAX_STATE (pad_fragP->fr_subtype) | |
e379e5f3 L |
11810 | == BRANCH_PADDING)) |
11811 | { | |
79d72f45 HL |
11812 | branch_fragP = i386_next_non_empty_frag (pad_fragP); |
11813 | if (branch_fragP->fr_type != rs_machine_dependent) | |
e379e5f3 | 11814 | return NULL; |
79d72f45 HL |
11815 | if (TYPE_FROM_RELAX_STATE (branch_fragP->fr_subtype) == COND_JUMP |
11816 | && i386_macro_fusible_p (maybe_cmp_fragP->tc_frag_data.mf_type, | |
11817 | pad_fragP->tc_frag_data.mf_type)) | |
11818 | return branch_fragP; | |
e379e5f3 L |
11819 | } |
11820 | ||
11821 | return NULL; | |
11822 | } | |
11823 | ||
11824 | /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */ | |
11825 | ||
11826 | static void | |
11827 | i386_classify_machine_dependent_frag (fragS *fragP) | |
11828 | { | |
11829 | fragS *cmp_fragP; | |
11830 | fragS *pad_fragP; | |
11831 | fragS *branch_fragP; | |
11832 | fragS *next_fragP; | |
11833 | unsigned int max_prefix_length; | |
11834 | ||
11835 | if (fragP->tc_frag_data.classified) | |
11836 | return; | |
11837 | ||
11838 | /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert | |
11839 | FUSED_JCC_PADDING and merge BRANCH_PADDING. */ | |
11840 | for (next_fragP = fragP; | |
11841 | next_fragP != NULL; | |
11842 | next_fragP = next_fragP->fr_next) | |
11843 | { | |
11844 | next_fragP->tc_frag_data.classified = 1; | |
11845 | if (next_fragP->fr_type == rs_machine_dependent) | |
11846 | switch (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)) | |
11847 | { | |
11848 | case BRANCH_PADDING: | |
11849 | /* The BRANCH_PADDING frag must be followed by a branch | |
11850 | frag. */ | |
11851 | branch_fragP = i386_next_non_empty_frag (next_fragP); | |
11852 | next_fragP->tc_frag_data.u.branch_fragP = branch_fragP; | |
11853 | break; | |
11854 | case FUSED_JCC_PADDING: | |
11855 | /* Check if this is a fused jcc: | |
11856 | FUSED_JCC_PADDING | |
11857 | CMP like instruction | |
11858 | BRANCH_PADDING | |
11859 | COND_JUMP | |
11860 | */ | |
11861 | cmp_fragP = i386_next_non_empty_frag (next_fragP); | |
11862 | pad_fragP = i386_next_non_empty_frag (cmp_fragP); | |
79d72f45 | 11863 | branch_fragP = i386_next_fusible_jcc_frag (next_fragP, pad_fragP); |
e379e5f3 L |
11864 | if (branch_fragP) |
11865 | { | |
11866 | /* The BRANCH_PADDING frag is merged with the | |
11867 | FUSED_JCC_PADDING frag. */ | |
11868 | next_fragP->tc_frag_data.u.branch_fragP = branch_fragP; | |
11869 | /* CMP like instruction size. */ | |
11870 | next_fragP->tc_frag_data.cmp_size = cmp_fragP->fr_fix; | |
11871 | frag_wane (pad_fragP); | |
11872 | /* Skip to branch_fragP. */ | |
11873 | next_fragP = branch_fragP; | |
11874 | } | |
11875 | else if (next_fragP->tc_frag_data.max_prefix_length) | |
11876 | { | |
11877 | /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't | |
11878 | a fused jcc. */ | |
11879 | next_fragP->fr_subtype | |
11880 | = ENCODE_RELAX_STATE (BRANCH_PREFIX, 0); | |
11881 | next_fragP->tc_frag_data.max_bytes | |
11882 | = next_fragP->tc_frag_data.max_prefix_length; | |
11883 | /* This will be updated in the BRANCH_PREFIX scan. */ | |
11884 | next_fragP->tc_frag_data.max_prefix_length = 0; | |
11885 | } | |
11886 | else | |
11887 | frag_wane (next_fragP); | |
11888 | break; | |
11889 | } | |
11890 | } | |
11891 | ||
11892 | /* Stop if there is no BRANCH_PREFIX. */ | |
11893 | if (!align_branch_prefix_size) | |
11894 | return; | |
11895 | ||
11896 | /* Scan for BRANCH_PREFIX. */ | |
11897 | for (; fragP != NULL; fragP = fragP->fr_next) | |
11898 | { | |
11899 | if (fragP->fr_type != rs_machine_dependent | |
11900 | || (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
11901 | != BRANCH_PREFIX)) | |
11902 | continue; | |
11903 | ||
11904 | /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and | |
11905 | COND_JUMP_PREFIX. */ | |
11906 | max_prefix_length = 0; | |
11907 | for (next_fragP = fragP; | |
11908 | next_fragP != NULL; | |
11909 | next_fragP = next_fragP->fr_next) | |
11910 | { | |
11911 | if (next_fragP->fr_type == rs_fill) | |
11912 | /* Skip rs_fill frags. */ | |
11913 | continue; | |
11914 | else if (next_fragP->fr_type != rs_machine_dependent) | |
11915 | /* Stop for all other frags. */ | |
11916 | break; | |
11917 | ||
11918 | /* rs_machine_dependent frags. */ | |
11919 | if (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
11920 | == BRANCH_PREFIX) | |
11921 | { | |
11922 | /* Count BRANCH_PREFIX frags. */ | |
11923 | if (max_prefix_length >= MAX_FUSED_JCC_PADDING_SIZE) | |
11924 | { | |
11925 | max_prefix_length = MAX_FUSED_JCC_PADDING_SIZE; | |
11926 | frag_wane (next_fragP); | |
11927 | } | |
11928 | else | |
11929 | max_prefix_length | |
11930 | += next_fragP->tc_frag_data.max_bytes; | |
11931 | } | |
11932 | else if ((TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
11933 | == BRANCH_PADDING) | |
11934 | || (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
11935 | == FUSED_JCC_PADDING)) | |
11936 | { | |
11937 | /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */ | |
11938 | fragP->tc_frag_data.u.padding_fragP = next_fragP; | |
11939 | break; | |
11940 | } | |
11941 | else | |
11942 | /* Stop for other rs_machine_dependent frags. */ | |
11943 | break; | |
11944 | } | |
11945 | ||
11946 | fragP->tc_frag_data.max_prefix_length = max_prefix_length; | |
11947 | ||
11948 | /* Skip to the next frag. */ | |
11949 | fragP = next_fragP; | |
11950 | } | |
11951 | } | |
11952 | ||
11953 | /* Compute padding size for | |
11954 | ||
11955 | FUSED_JCC_PADDING | |
11956 | CMP like instruction | |
11957 | BRANCH_PADDING | |
11958 | COND_JUMP/UNCOND_JUMP | |
11959 | ||
11960 | or | |
11961 | ||
11962 | BRANCH_PADDING | |
11963 | COND_JUMP/UNCOND_JUMP | |
11964 | */ | |
11965 | ||
11966 | static int | |
11967 | i386_branch_padding_size (fragS *fragP, offsetT address) | |
11968 | { | |
11969 | unsigned int offset, size, padding_size; | |
11970 | fragS *branch_fragP = fragP->tc_frag_data.u.branch_fragP; | |
11971 | ||
11972 | /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */ | |
11973 | if (!address) | |
11974 | address = fragP->fr_address; | |
11975 | address += fragP->fr_fix; | |
11976 | ||
11977 | /* CMP like instrunction size. */ | |
11978 | size = fragP->tc_frag_data.cmp_size; | |
11979 | ||
11980 | /* The base size of the branch frag. */ | |
11981 | size += branch_fragP->fr_fix; | |
11982 | ||
11983 | /* Add opcode and displacement bytes for the rs_machine_dependent | |
11984 | branch frag. */ | |
11985 | if (branch_fragP->fr_type == rs_machine_dependent) | |
11986 | size += md_relax_table[branch_fragP->fr_subtype].rlx_length; | |
11987 | ||
11988 | /* Check if branch is within boundary and doesn't end at the last | |
11989 | byte. */ | |
11990 | offset = address & ((1U << align_branch_power) - 1); | |
11991 | if ((offset + size) >= (1U << align_branch_power)) | |
11992 | /* Padding needed to avoid crossing boundary. */ | |
11993 | padding_size = (1U << align_branch_power) - offset; | |
11994 | else | |
11995 | /* No padding needed. */ | |
11996 | padding_size = 0; | |
11997 | ||
11998 | /* The return value may be saved in tc_frag_data.length which is | |
11999 | unsigned byte. */ | |
12000 | if (!fits_in_unsigned_byte (padding_size)) | |
12001 | abort (); | |
12002 | ||
12003 | return padding_size; | |
12004 | } | |
12005 | ||
12006 | /* i386_generic_table_relax_frag() | |
12007 | ||
12008 | Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to | |
12009 | grow/shrink padding to align branch frags. Hand others to | |
12010 | relax_frag(). */ | |
12011 | ||
12012 | long | |
12013 | i386_generic_table_relax_frag (segT segment, fragS *fragP, long stretch) | |
12014 | { | |
12015 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING | |
12016 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
12017 | { | |
12018 | long padding_size = i386_branch_padding_size (fragP, 0); | |
12019 | long grow = padding_size - fragP->tc_frag_data.length; | |
12020 | ||
12021 | /* When the BRANCH_PREFIX frag is used, the computed address | |
12022 | must match the actual address and there should be no padding. */ | |
12023 | if (fragP->tc_frag_data.padding_address | |
12024 | && (fragP->tc_frag_data.padding_address != fragP->fr_address | |
12025 | || padding_size)) | |
12026 | abort (); | |
12027 | ||
12028 | /* Update the padding size. */ | |
12029 | if (grow) | |
12030 | fragP->tc_frag_data.length = padding_size; | |
12031 | ||
12032 | return grow; | |
12033 | } | |
12034 | else if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
12035 | { | |
12036 | fragS *padding_fragP, *next_fragP; | |
12037 | long padding_size, left_size, last_size; | |
12038 | ||
12039 | padding_fragP = fragP->tc_frag_data.u.padding_fragP; | |
12040 | if (!padding_fragP) | |
12041 | /* Use the padding set by the leading BRANCH_PREFIX frag. */ | |
12042 | return (fragP->tc_frag_data.length | |
12043 | - fragP->tc_frag_data.last_length); | |
12044 | ||
12045 | /* Compute the relative address of the padding frag in the very | |
12046 | first time where the BRANCH_PREFIX frag sizes are zero. */ | |
12047 | if (!fragP->tc_frag_data.padding_address) | |
12048 | fragP->tc_frag_data.padding_address | |
12049 | = padding_fragP->fr_address - (fragP->fr_address - stretch); | |
12050 | ||
12051 | /* First update the last length from the previous interation. */ | |
12052 | left_size = fragP->tc_frag_data.prefix_length; | |
12053 | for (next_fragP = fragP; | |
12054 | next_fragP != padding_fragP; | |
12055 | next_fragP = next_fragP->fr_next) | |
12056 | if (next_fragP->fr_type == rs_machine_dependent | |
12057 | && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
12058 | == BRANCH_PREFIX)) | |
12059 | { | |
12060 | if (left_size) | |
12061 | { | |
12062 | int max = next_fragP->tc_frag_data.max_bytes; | |
12063 | if (max) | |
12064 | { | |
12065 | int size; | |
12066 | if (max > left_size) | |
12067 | size = left_size; | |
12068 | else | |
12069 | size = max; | |
12070 | left_size -= size; | |
12071 | next_fragP->tc_frag_data.last_length = size; | |
12072 | } | |
12073 | } | |
12074 | else | |
12075 | next_fragP->tc_frag_data.last_length = 0; | |
12076 | } | |
12077 | ||
12078 | /* Check the padding size for the padding frag. */ | |
12079 | padding_size = i386_branch_padding_size | |
12080 | (padding_fragP, (fragP->fr_address | |
12081 | + fragP->tc_frag_data.padding_address)); | |
12082 | ||
12083 | last_size = fragP->tc_frag_data.prefix_length; | |
12084 | /* Check if there is change from the last interation. */ | |
12085 | if (padding_size == last_size) | |
12086 | { | |
12087 | /* Update the expected address of the padding frag. */ | |
12088 | padding_fragP->tc_frag_data.padding_address | |
12089 | = (fragP->fr_address + padding_size | |
12090 | + fragP->tc_frag_data.padding_address); | |
12091 | return 0; | |
12092 | } | |
12093 | ||
12094 | if (padding_size > fragP->tc_frag_data.max_prefix_length) | |
12095 | { | |
12096 | /* No padding if there is no sufficient room. Clear the | |
12097 | expected address of the padding frag. */ | |
12098 | padding_fragP->tc_frag_data.padding_address = 0; | |
12099 | padding_size = 0; | |
12100 | } | |
12101 | else | |
12102 | /* Store the expected address of the padding frag. */ | |
12103 | padding_fragP->tc_frag_data.padding_address | |
12104 | = (fragP->fr_address + padding_size | |
12105 | + fragP->tc_frag_data.padding_address); | |
12106 | ||
12107 | fragP->tc_frag_data.prefix_length = padding_size; | |
12108 | ||
12109 | /* Update the length for the current interation. */ | |
12110 | left_size = padding_size; | |
12111 | for (next_fragP = fragP; | |
12112 | next_fragP != padding_fragP; | |
12113 | next_fragP = next_fragP->fr_next) | |
12114 | if (next_fragP->fr_type == rs_machine_dependent | |
12115 | && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
12116 | == BRANCH_PREFIX)) | |
12117 | { | |
12118 | if (left_size) | |
12119 | { | |
12120 | int max = next_fragP->tc_frag_data.max_bytes; | |
12121 | if (max) | |
12122 | { | |
12123 | int size; | |
12124 | if (max > left_size) | |
12125 | size = left_size; | |
12126 | else | |
12127 | size = max; | |
12128 | left_size -= size; | |
12129 | next_fragP->tc_frag_data.length = size; | |
12130 | } | |
12131 | } | |
12132 | else | |
12133 | next_fragP->tc_frag_data.length = 0; | |
12134 | } | |
12135 | ||
12136 | return (fragP->tc_frag_data.length | |
12137 | - fragP->tc_frag_data.last_length); | |
12138 | } | |
12139 | return relax_frag (segment, fragP, stretch); | |
12140 | } | |
12141 | ||
ee7fcc42 AM |
12142 | /* md_estimate_size_before_relax() |
12143 | ||
12144 | Called just before relax() for rs_machine_dependent frags. The x86 | |
12145 | assembler uses these frags to handle variable size jump | |
12146 | instructions. | |
12147 | ||
12148 | Any symbol that is now undefined will not become defined. | |
12149 | Return the correct fr_subtype in the frag. | |
12150 | Return the initial "guess for variable size of frag" to caller. | |
12151 | The guess is actually the growth beyond the fixed part. Whatever | |
12152 | we do to grow the fixed or variable part contributes to our | |
12153 | returned value. */ | |
12154 | ||
252b5132 | 12155 | int |
7016a5d5 | 12156 | md_estimate_size_before_relax (fragS *fragP, segT segment) |
252b5132 | 12157 | { |
e379e5f3 L |
12158 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING |
12159 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX | |
12160 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
12161 | { | |
12162 | i386_classify_machine_dependent_frag (fragP); | |
12163 | return fragP->tc_frag_data.length; | |
12164 | } | |
12165 | ||
252b5132 | 12166 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
12167 | check for un-relaxable symbols. On an ELF system, we can't relax |
12168 | an externally visible symbol, because it may be overridden by a | |
12169 | shared library. */ | |
12170 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 12171 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 12172 | || (IS_ELF |
8dcea932 L |
12173 | && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol, |
12174 | fragP->fr_var)) | |
fbeb56a4 DK |
12175 | #endif |
12176 | #if defined (OBJ_COFF) && defined (TE_PE) | |
7ab9ffdd | 12177 | || (OUTPUT_FLAVOR == bfd_target_coff_flavour |
fbeb56a4 | 12178 | && S_IS_WEAK (fragP->fr_symbol)) |
b98ef147 AM |
12179 | #endif |
12180 | ) | |
252b5132 | 12181 | { |
b98ef147 AM |
12182 | /* Symbol is undefined in this segment, or we need to keep a |
12183 | reloc so that weak symbols can be overridden. */ | |
12184 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f86103b7 | 12185 | enum bfd_reloc_code_real reloc_type; |
ee7fcc42 AM |
12186 | unsigned char *opcode; |
12187 | int old_fr_fix; | |
eb19308f | 12188 | fixS *fixP = NULL; |
f6af82bd | 12189 | |
ee7fcc42 | 12190 | if (fragP->fr_var != NO_RELOC) |
1e9cc1c2 | 12191 | reloc_type = (enum bfd_reloc_code_real) fragP->fr_var; |
b98ef147 | 12192 | else if (size == 2) |
f6af82bd | 12193 | reloc_type = BFD_RELOC_16_PCREL; |
bd7ab16b L |
12194 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
12195 | else if (need_plt32_p (fragP->fr_symbol)) | |
12196 | reloc_type = BFD_RELOC_X86_64_PLT32; | |
12197 | #endif | |
f6af82bd AM |
12198 | else |
12199 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 12200 | |
ee7fcc42 AM |
12201 | old_fr_fix = fragP->fr_fix; |
12202 | opcode = (unsigned char *) fragP->fr_opcode; | |
12203 | ||
fddf5b5b | 12204 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 12205 | { |
fddf5b5b AM |
12206 | case UNCOND_JUMP: |
12207 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 12208 | opcode[0] = 0xe9; |
252b5132 | 12209 | fragP->fr_fix += size; |
eb19308f JB |
12210 | fixP = fix_new (fragP, old_fr_fix, size, |
12211 | fragP->fr_symbol, | |
12212 | fragP->fr_offset, 1, | |
12213 | reloc_type); | |
252b5132 RH |
12214 | break; |
12215 | ||
fddf5b5b | 12216 | case COND_JUMP86: |
412167cb AM |
12217 | if (size == 2 |
12218 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) | |
fddf5b5b AM |
12219 | { |
12220 | /* Negate the condition, and branch past an | |
12221 | unconditional jump. */ | |
12222 | opcode[0] ^= 1; | |
12223 | opcode[1] = 3; | |
12224 | /* Insert an unconditional jump. */ | |
12225 | opcode[2] = 0xe9; | |
12226 | /* We added two extra opcode bytes, and have a two byte | |
12227 | offset. */ | |
12228 | fragP->fr_fix += 2 + 2; | |
062cd5e7 AS |
12229 | fix_new (fragP, old_fr_fix + 2, 2, |
12230 | fragP->fr_symbol, | |
12231 | fragP->fr_offset, 1, | |
12232 | reloc_type); | |
fddf5b5b AM |
12233 | break; |
12234 | } | |
12235 | /* Fall through. */ | |
12236 | ||
12237 | case COND_JUMP: | |
412167cb AM |
12238 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
12239 | { | |
12240 | fragP->fr_fix += 1; | |
3e02c1cc AM |
12241 | fixP = fix_new (fragP, old_fr_fix, 1, |
12242 | fragP->fr_symbol, | |
12243 | fragP->fr_offset, 1, | |
12244 | BFD_RELOC_8_PCREL); | |
12245 | fixP->fx_signed = 1; | |
412167cb AM |
12246 | break; |
12247 | } | |
93c2a809 | 12248 | |
24eab124 | 12249 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 12250 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 12251 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 12252 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
12253 | /* We've added an opcode byte. */ |
12254 | fragP->fr_fix += 1 + size; | |
eb19308f JB |
12255 | fixP = fix_new (fragP, old_fr_fix + 1, size, |
12256 | fragP->fr_symbol, | |
12257 | fragP->fr_offset, 1, | |
12258 | reloc_type); | |
252b5132 | 12259 | break; |
fddf5b5b AM |
12260 | |
12261 | default: | |
12262 | BAD_CASE (fragP->fr_subtype); | |
12263 | break; | |
252b5132 | 12264 | } |
eb19308f JB |
12265 | |
12266 | /* All jumps handled here are signed, but don't unconditionally use a | |
12267 | signed limit check for 32 and 16 bit jumps as we want to allow wrap | |
12268 | around at 4G (outside of 64-bit mode) and 64k. */ | |
12269 | if (size == 4 && flag_code == CODE_64BIT) | |
12270 | fixP->fx_signed = 1; | |
12271 | ||
252b5132 | 12272 | frag_wane (fragP); |
ee7fcc42 | 12273 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 12274 | } |
93c2a809 | 12275 | |
93c2a809 AM |
12276 | /* Guess size depending on current relax state. Initially the relax |
12277 | state will correspond to a short jump and we return 1, because | |
12278 | the variable part of the frag (the branch offset) is one byte | |
12279 | long. However, we can relax a section more than once and in that | |
12280 | case we must either set fr_subtype back to the unrelaxed state, | |
12281 | or return the value for the appropriate branch. */ | |
12282 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
12283 | } |
12284 | ||
47926f60 KH |
12285 | /* Called after relax() is finished. |
12286 | ||
12287 | In: Address of frag. | |
12288 | fr_type == rs_machine_dependent. | |
12289 | fr_subtype is what the address relaxed to. | |
12290 | ||
12291 | Out: Any fixSs and constants are set up. | |
12292 | Caller will turn frag into a ".space 0". */ | |
12293 | ||
252b5132 | 12294 | void |
7016a5d5 TG |
12295 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, |
12296 | fragS *fragP) | |
252b5132 | 12297 | { |
29b0f896 | 12298 | unsigned char *opcode; |
252b5132 | 12299 | unsigned char *where_to_put_displacement = NULL; |
847f7ad4 AM |
12300 | offsetT target_address; |
12301 | offsetT opcode_address; | |
252b5132 | 12302 | unsigned int extension = 0; |
847f7ad4 | 12303 | offsetT displacement_from_opcode_start; |
252b5132 | 12304 | |
e379e5f3 L |
12305 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING |
12306 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING | |
12307 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
12308 | { | |
12309 | /* Generate nop padding. */ | |
12310 | unsigned int size = fragP->tc_frag_data.length; | |
12311 | if (size) | |
12312 | { | |
12313 | if (size > fragP->tc_frag_data.max_bytes) | |
12314 | abort (); | |
12315 | ||
12316 | if (flag_debug) | |
12317 | { | |
12318 | const char *msg; | |
12319 | const char *branch = "branch"; | |
12320 | const char *prefix = ""; | |
12321 | fragS *padding_fragP; | |
12322 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
12323 | == BRANCH_PREFIX) | |
12324 | { | |
12325 | padding_fragP = fragP->tc_frag_data.u.padding_fragP; | |
12326 | switch (fragP->tc_frag_data.default_prefix) | |
12327 | { | |
12328 | default: | |
12329 | abort (); | |
12330 | break; | |
12331 | case CS_PREFIX_OPCODE: | |
12332 | prefix = " cs"; | |
12333 | break; | |
12334 | case DS_PREFIX_OPCODE: | |
12335 | prefix = " ds"; | |
12336 | break; | |
12337 | case ES_PREFIX_OPCODE: | |
12338 | prefix = " es"; | |
12339 | break; | |
12340 | case FS_PREFIX_OPCODE: | |
12341 | prefix = " fs"; | |
12342 | break; | |
12343 | case GS_PREFIX_OPCODE: | |
12344 | prefix = " gs"; | |
12345 | break; | |
12346 | case SS_PREFIX_OPCODE: | |
12347 | prefix = " ss"; | |
12348 | break; | |
12349 | } | |
12350 | if (padding_fragP) | |
12351 | msg = _("%s:%u: add %d%s at 0x%llx to align " | |
12352 | "%s within %d-byte boundary\n"); | |
12353 | else | |
12354 | msg = _("%s:%u: add additional %d%s at 0x%llx to " | |
12355 | "align %s within %d-byte boundary\n"); | |
12356 | } | |
12357 | else | |
12358 | { | |
12359 | padding_fragP = fragP; | |
12360 | msg = _("%s:%u: add %d%s-byte nop at 0x%llx to align " | |
12361 | "%s within %d-byte boundary\n"); | |
12362 | } | |
12363 | ||
12364 | if (padding_fragP) | |
12365 | switch (padding_fragP->tc_frag_data.branch_type) | |
12366 | { | |
12367 | case align_branch_jcc: | |
12368 | branch = "jcc"; | |
12369 | break; | |
12370 | case align_branch_fused: | |
12371 | branch = "fused jcc"; | |
12372 | break; | |
12373 | case align_branch_jmp: | |
12374 | branch = "jmp"; | |
12375 | break; | |
12376 | case align_branch_call: | |
12377 | branch = "call"; | |
12378 | break; | |
12379 | case align_branch_indirect: | |
12380 | branch = "indiret branch"; | |
12381 | break; | |
12382 | case align_branch_ret: | |
12383 | branch = "ret"; | |
12384 | break; | |
12385 | default: | |
12386 | break; | |
12387 | } | |
12388 | ||
12389 | fprintf (stdout, msg, | |
12390 | fragP->fr_file, fragP->fr_line, size, prefix, | |
12391 | (long long) fragP->fr_address, branch, | |
12392 | 1 << align_branch_power); | |
12393 | } | |
12394 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
12395 | memset (fragP->fr_opcode, | |
12396 | fragP->tc_frag_data.default_prefix, size); | |
12397 | else | |
12398 | i386_generate_nops (fragP, (char *) fragP->fr_opcode, | |
12399 | size, 0); | |
12400 | fragP->fr_fix += size; | |
12401 | } | |
12402 | return; | |
12403 | } | |
12404 | ||
252b5132 RH |
12405 | opcode = (unsigned char *) fragP->fr_opcode; |
12406 | ||
47926f60 | 12407 | /* Address we want to reach in file space. */ |
252b5132 | 12408 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 12409 | |
47926f60 | 12410 | /* Address opcode resides at in file space. */ |
252b5132 RH |
12411 | opcode_address = fragP->fr_address + fragP->fr_fix; |
12412 | ||
47926f60 | 12413 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
12414 | displacement_from_opcode_start = target_address - opcode_address; |
12415 | ||
fddf5b5b | 12416 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 12417 | { |
47926f60 KH |
12418 | /* Don't have to change opcode. */ |
12419 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 12420 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
12421 | } |
12422 | else | |
12423 | { | |
12424 | if (no_cond_jump_promotion | |
12425 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4eed87de AM |
12426 | as_warn_where (fragP->fr_file, fragP->fr_line, |
12427 | _("long jump required")); | |
252b5132 | 12428 | |
fddf5b5b AM |
12429 | switch (fragP->fr_subtype) |
12430 | { | |
12431 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
12432 | extension = 4; /* 1 opcode + 4 displacement */ | |
12433 | opcode[0] = 0xe9; | |
12434 | where_to_put_displacement = &opcode[1]; | |
12435 | break; | |
252b5132 | 12436 | |
fddf5b5b AM |
12437 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
12438 | extension = 2; /* 1 opcode + 2 displacement */ | |
12439 | opcode[0] = 0xe9; | |
12440 | where_to_put_displacement = &opcode[1]; | |
12441 | break; | |
252b5132 | 12442 | |
fddf5b5b AM |
12443 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
12444 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
12445 | extension = 5; /* 2 opcode + 4 displacement */ | |
12446 | opcode[1] = opcode[0] + 0x10; | |
12447 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
12448 | where_to_put_displacement = &opcode[2]; | |
12449 | break; | |
252b5132 | 12450 | |
fddf5b5b AM |
12451 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
12452 | extension = 3; /* 2 opcode + 2 displacement */ | |
12453 | opcode[1] = opcode[0] + 0x10; | |
12454 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
12455 | where_to_put_displacement = &opcode[2]; | |
12456 | break; | |
252b5132 | 12457 | |
fddf5b5b AM |
12458 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
12459 | extension = 4; | |
12460 | opcode[0] ^= 1; | |
12461 | opcode[1] = 3; | |
12462 | opcode[2] = 0xe9; | |
12463 | where_to_put_displacement = &opcode[3]; | |
12464 | break; | |
12465 | ||
12466 | default: | |
12467 | BAD_CASE (fragP->fr_subtype); | |
12468 | break; | |
12469 | } | |
252b5132 | 12470 | } |
fddf5b5b | 12471 | |
7b81dfbb AJ |
12472 | /* If size if less then four we are sure that the operand fits, |
12473 | but if it's 4, then it could be that the displacement is larger | |
12474 | then -/+ 2GB. */ | |
12475 | if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 | |
12476 | && object_64bit | |
12477 | && ((addressT) (displacement_from_opcode_start - extension | |
4eed87de AM |
12478 | + ((addressT) 1 << 31)) |
12479 | > (((addressT) 2 << 31) - 1))) | |
7b81dfbb AJ |
12480 | { |
12481 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
12482 | _("jump target out of range")); | |
12483 | /* Make us emit 0. */ | |
12484 | displacement_from_opcode_start = extension; | |
12485 | } | |
47926f60 | 12486 | /* Now put displacement after opcode. */ |
252b5132 RH |
12487 | md_number_to_chars ((char *) where_to_put_displacement, |
12488 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 12489 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
12490 | fragP->fr_fix += extension; |
12491 | } | |
12492 | \f | |
7016a5d5 | 12493 | /* Apply a fixup (fixP) to segment data, once it has been determined |
252b5132 RH |
12494 | by our caller that we have all the info we need to fix it up. |
12495 | ||
7016a5d5 TG |
12496 | Parameter valP is the pointer to the value of the bits. |
12497 | ||
252b5132 RH |
12498 | On the 386, immediates, displacements, and data pointers are all in |
12499 | the same (little-endian) format, so we don't need to care about which | |
12500 | we are handling. */ | |
12501 | ||
94f592af | 12502 | void |
7016a5d5 | 12503 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 12504 | { |
94f592af | 12505 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
c6682705 | 12506 | valueT value = *valP; |
252b5132 | 12507 | |
f86103b7 | 12508 | #if !defined (TE_Mach) |
93382f6d AM |
12509 | if (fixP->fx_pcrel) |
12510 | { | |
12511 | switch (fixP->fx_r_type) | |
12512 | { | |
5865bb77 ILT |
12513 | default: |
12514 | break; | |
12515 | ||
d6ab8113 JB |
12516 | case BFD_RELOC_64: |
12517 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
12518 | break; | |
93382f6d | 12519 | case BFD_RELOC_32: |
ae8887b5 | 12520 | case BFD_RELOC_X86_64_32S: |
93382f6d AM |
12521 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
12522 | break; | |
12523 | case BFD_RELOC_16: | |
12524 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
12525 | break; | |
12526 | case BFD_RELOC_8: | |
12527 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
12528 | break; | |
12529 | } | |
12530 | } | |
252b5132 | 12531 | |
a161fe53 | 12532 | if (fixP->fx_addsy != NULL |
31312f95 | 12533 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
d6ab8113 | 12534 | || fixP->fx_r_type == BFD_RELOC_64_PCREL |
31312f95 | 12535 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
d258b828 | 12536 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) |
31312f95 | 12537 | && !use_rela_relocations) |
252b5132 | 12538 | { |
31312f95 AM |
12539 | /* This is a hack. There should be a better way to handle this. |
12540 | This covers for the fact that bfd_install_relocation will | |
12541 | subtract the current location (for partial_inplace, PC relative | |
12542 | relocations); see more below. */ | |
252b5132 | 12543 | #ifndef OBJ_AOUT |
718ddfc0 | 12544 | if (IS_ELF |
252b5132 RH |
12545 | #ifdef TE_PE |
12546 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
12547 | #endif | |
12548 | ) | |
12549 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
12550 | #endif | |
12551 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 12552 | if (IS_ELF) |
252b5132 | 12553 | { |
6539b54b | 12554 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
2f66722d | 12555 | |
6539b54b | 12556 | if ((sym_seg == seg |
2f66722d | 12557 | || (symbol_section_p (fixP->fx_addsy) |
6539b54b | 12558 | && sym_seg != absolute_section)) |
af65af87 | 12559 | && !generic_force_reloc (fixP)) |
2f66722d AM |
12560 | { |
12561 | /* Yes, we add the values in twice. This is because | |
6539b54b AM |
12562 | bfd_install_relocation subtracts them out again. I think |
12563 | bfd_install_relocation is broken, but I don't dare change | |
2f66722d AM |
12564 | it. FIXME. */ |
12565 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
12566 | } | |
252b5132 RH |
12567 | } |
12568 | #endif | |
12569 | #if defined (OBJ_COFF) && defined (TE_PE) | |
977cdf5a NC |
12570 | /* For some reason, the PE format does not store a |
12571 | section address offset for a PC relative symbol. */ | |
12572 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg | |
7be1c489 | 12573 | || S_IS_WEAK (fixP->fx_addsy)) |
252b5132 RH |
12574 | value += md_pcrel_from (fixP); |
12575 | #endif | |
12576 | } | |
fbeb56a4 | 12577 | #if defined (OBJ_COFF) && defined (TE_PE) |
f01c1a09 NC |
12578 | if (fixP->fx_addsy != NULL |
12579 | && S_IS_WEAK (fixP->fx_addsy) | |
12580 | /* PR 16858: Do not modify weak function references. */ | |
12581 | && ! fixP->fx_pcrel) | |
fbeb56a4 | 12582 | { |
296a8689 NC |
12583 | #if !defined (TE_PEP) |
12584 | /* For x86 PE weak function symbols are neither PC-relative | |
12585 | nor do they set S_IS_FUNCTION. So the only reliable way | |
12586 | to detect them is to check the flags of their containing | |
12587 | section. */ | |
12588 | if (S_GET_SEGMENT (fixP->fx_addsy) != NULL | |
12589 | && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE) | |
12590 | ; | |
12591 | else | |
12592 | #endif | |
fbeb56a4 DK |
12593 | value -= S_GET_VALUE (fixP->fx_addsy); |
12594 | } | |
12595 | #endif | |
252b5132 RH |
12596 | |
12597 | /* Fix a few things - the dynamic linker expects certain values here, | |
0234cb7c | 12598 | and we must not disappoint it. */ |
252b5132 | 12599 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 12600 | if (IS_ELF && fixP->fx_addsy) |
47926f60 KH |
12601 | switch (fixP->fx_r_type) |
12602 | { | |
12603 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 12604 | case BFD_RELOC_X86_64_PLT32: |
b9519cfe L |
12605 | /* Make the jump instruction point to the address of the operand. |
12606 | At runtime we merely add the offset to the actual PLT entry. | |
12607 | NB: Subtract the offset size only for jump instructions. */ | |
12608 | if (fixP->fx_pcrel) | |
12609 | value = -4; | |
47926f60 | 12610 | break; |
31312f95 | 12611 | |
13ae64f3 JJ |
12612 | case BFD_RELOC_386_TLS_GD: |
12613 | case BFD_RELOC_386_TLS_LDM: | |
13ae64f3 | 12614 | case BFD_RELOC_386_TLS_IE_32: |
37e55690 JJ |
12615 | case BFD_RELOC_386_TLS_IE: |
12616 | case BFD_RELOC_386_TLS_GOTIE: | |
67a4f2b7 | 12617 | case BFD_RELOC_386_TLS_GOTDESC: |
bffbf940 JJ |
12618 | case BFD_RELOC_X86_64_TLSGD: |
12619 | case BFD_RELOC_X86_64_TLSLD: | |
12620 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 | 12621 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
00f7efb6 JJ |
12622 | value = 0; /* Fully resolved at runtime. No addend. */ |
12623 | /* Fallthrough */ | |
12624 | case BFD_RELOC_386_TLS_LE: | |
12625 | case BFD_RELOC_386_TLS_LDO_32: | |
12626 | case BFD_RELOC_386_TLS_LE_32: | |
12627 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 12628 | case BFD_RELOC_X86_64_DTPOFF64: |
00f7efb6 | 12629 | case BFD_RELOC_X86_64_TPOFF32: |
d6ab8113 | 12630 | case BFD_RELOC_X86_64_TPOFF64: |
00f7efb6 JJ |
12631 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
12632 | break; | |
12633 | ||
67a4f2b7 AO |
12634 | case BFD_RELOC_386_TLS_DESC_CALL: |
12635 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
12636 | value = 0; /* Fully resolved at runtime. No addend. */ | |
12637 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
12638 | fixP->fx_done = 0; | |
12639 | return; | |
12640 | ||
47926f60 KH |
12641 | case BFD_RELOC_VTABLE_INHERIT: |
12642 | case BFD_RELOC_VTABLE_ENTRY: | |
12643 | fixP->fx_done = 0; | |
94f592af | 12644 | return; |
47926f60 KH |
12645 | |
12646 | default: | |
12647 | break; | |
12648 | } | |
12649 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
a442cac5 JB |
12650 | |
12651 | /* If not 64bit, massage value, to account for wraparound when !BFD64. */ | |
12652 | if (!object_64bit) | |
12653 | value = extend_to_32bit_address (value); | |
12654 | ||
c6682705 | 12655 | *valP = value; |
f86103b7 | 12656 | #endif /* !defined (TE_Mach) */ |
3e73aa7c | 12657 | |
3e73aa7c | 12658 | /* Are we finished with this relocation now? */ |
c6682705 | 12659 | if (fixP->fx_addsy == NULL) |
b8188555 JB |
12660 | { |
12661 | fixP->fx_done = 1; | |
12662 | switch (fixP->fx_r_type) | |
12663 | { | |
12664 | case BFD_RELOC_X86_64_32S: | |
12665 | fixP->fx_signed = 1; | |
12666 | break; | |
12667 | ||
12668 | default: | |
12669 | break; | |
12670 | } | |
12671 | } | |
fbeb56a4 DK |
12672 | #if defined (OBJ_COFF) && defined (TE_PE) |
12673 | else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) | |
12674 | { | |
12675 | fixP->fx_done = 0; | |
12676 | /* Remember value for tc_gen_reloc. */ | |
12677 | fixP->fx_addnumber = value; | |
12678 | /* Clear out the frag for now. */ | |
12679 | value = 0; | |
12680 | } | |
12681 | #endif | |
3e73aa7c JH |
12682 | else if (use_rela_relocations) |
12683 | { | |
12684 | fixP->fx_no_overflow = 1; | |
062cd5e7 AS |
12685 | /* Remember value for tc_gen_reloc. */ |
12686 | fixP->fx_addnumber = value; | |
3e73aa7c JH |
12687 | value = 0; |
12688 | } | |
f86103b7 | 12689 | |
94f592af | 12690 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 12691 | } |
252b5132 | 12692 | \f |
6d4af3c2 | 12693 | const char * |
499ac353 | 12694 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 12695 | { |
499ac353 NC |
12696 | /* This outputs the LITTLENUMs in REVERSE order; |
12697 | in accord with the bigendian 386. */ | |
5b7c81bd | 12698 | return ieee_md_atof (type, litP, sizeP, false); |
252b5132 RH |
12699 | } |
12700 | \f | |
2d545b82 | 12701 | static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; |
252b5132 | 12702 | |
252b5132 | 12703 | static char * |
e3bb37b5 | 12704 | output_invalid (int c) |
252b5132 | 12705 | { |
3882b010 | 12706 | if (ISPRINT (c)) |
f9f21a03 L |
12707 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
12708 | "'%c'", c); | |
252b5132 | 12709 | else |
f9f21a03 | 12710 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
2d545b82 | 12711 | "(0x%x)", (unsigned char) c); |
252b5132 RH |
12712 | return output_invalid_buf; |
12713 | } | |
12714 | ||
8a6fb3f9 JB |
12715 | /* Verify that @r can be used in the current context. */ |
12716 | ||
5b7c81bd | 12717 | static bool check_register (const reg_entry *r) |
8a6fb3f9 JB |
12718 | { |
12719 | if (allow_pseudo_reg) | |
5b7c81bd | 12720 | return true; |
8a6fb3f9 JB |
12721 | |
12722 | if (operand_type_all_zero (&r->reg_type)) | |
5b7c81bd | 12723 | return false; |
8a6fb3f9 JB |
12724 | |
12725 | if ((r->reg_type.bitfield.dword | |
12726 | || (r->reg_type.bitfield.class == SReg && r->reg_num > 3) | |
12727 | || r->reg_type.bitfield.class == RegCR | |
22e00a3f | 12728 | || r->reg_type.bitfield.class == RegDR) |
8a6fb3f9 | 12729 | && !cpu_arch_flags.bitfield.cpui386) |
5b7c81bd | 12730 | return false; |
8a6fb3f9 | 12731 | |
22e00a3f JB |
12732 | if (r->reg_type.bitfield.class == RegTR |
12733 | && (flag_code == CODE_64BIT | |
12734 | || !cpu_arch_flags.bitfield.cpui386 | |
12735 | || cpu_arch_isa_flags.bitfield.cpui586 | |
12736 | || cpu_arch_isa_flags.bitfield.cpui686)) | |
5b7c81bd | 12737 | return false; |
22e00a3f | 12738 | |
8a6fb3f9 | 12739 | if (r->reg_type.bitfield.class == RegMMX && !cpu_arch_flags.bitfield.cpummx) |
5b7c81bd | 12740 | return false; |
8a6fb3f9 JB |
12741 | |
12742 | if (!cpu_arch_flags.bitfield.cpuavx512f) | |
12743 | { | |
12744 | if (r->reg_type.bitfield.zmmword | |
12745 | || r->reg_type.bitfield.class == RegMask) | |
5b7c81bd | 12746 | return false; |
8a6fb3f9 JB |
12747 | |
12748 | if (!cpu_arch_flags.bitfield.cpuavx) | |
12749 | { | |
12750 | if (r->reg_type.bitfield.ymmword) | |
5b7c81bd | 12751 | return false; |
8a6fb3f9 JB |
12752 | |
12753 | if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword) | |
5b7c81bd | 12754 | return false; |
8a6fb3f9 JB |
12755 | } |
12756 | } | |
12757 | ||
260cd341 LC |
12758 | if (r->reg_type.bitfield.tmmword |
12759 | && (!cpu_arch_flags.bitfield.cpuamx_tile | |
12760 | || flag_code != CODE_64BIT)) | |
5b7c81bd | 12761 | return false; |
260cd341 | 12762 | |
8a6fb3f9 | 12763 | if (r->reg_type.bitfield.class == RegBND && !cpu_arch_flags.bitfield.cpumpx) |
5b7c81bd | 12764 | return false; |
8a6fb3f9 JB |
12765 | |
12766 | /* Don't allow fake index register unless allow_index_reg isn't 0. */ | |
12767 | if (!allow_index_reg && r->reg_num == RegIZ) | |
5b7c81bd | 12768 | return false; |
8a6fb3f9 JB |
12769 | |
12770 | /* Upper 16 vector registers are only available with VREX in 64bit | |
12771 | mode, and require EVEX encoding. */ | |
12772 | if (r->reg_flags & RegVRex) | |
12773 | { | |
12774 | if (!cpu_arch_flags.bitfield.cpuavx512f | |
12775 | || flag_code != CODE_64BIT) | |
5b7c81bd | 12776 | return false; |
8a6fb3f9 | 12777 | |
da4977e0 JB |
12778 | if (i.vec_encoding == vex_encoding_default) |
12779 | i.vec_encoding = vex_encoding_evex; | |
12780 | else if (i.vec_encoding != vex_encoding_evex) | |
12781 | i.vec_encoding = vex_encoding_error; | |
8a6fb3f9 JB |
12782 | } |
12783 | ||
12784 | if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword) | |
12785 | && (!cpu_arch_flags.bitfield.cpulm || r->reg_type.bitfield.class != RegCR) | |
12786 | && flag_code != CODE_64BIT) | |
5b7c81bd | 12787 | return false; |
8a6fb3f9 JB |
12788 | |
12789 | if (r->reg_type.bitfield.class == SReg && r->reg_num == RegFlat | |
12790 | && !intel_syntax) | |
5b7c81bd | 12791 | return false; |
8a6fb3f9 | 12792 | |
5b7c81bd | 12793 | return true; |
8a6fb3f9 JB |
12794 | } |
12795 | ||
af6bdddf | 12796 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
12797 | |
12798 | static const reg_entry * | |
4d1bb795 | 12799 | parse_real_register (char *reg_string, char **end_op) |
252b5132 | 12800 | { |
af6bdddf AM |
12801 | char *s = reg_string; |
12802 | char *p; | |
252b5132 RH |
12803 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
12804 | const reg_entry *r; | |
12805 | ||
12806 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
12807 | if (*s == REGISTER_PREFIX) | |
12808 | ++s; | |
12809 | ||
12810 | if (is_space_char (*s)) | |
12811 | ++s; | |
12812 | ||
12813 | p = reg_name_given; | |
af6bdddf | 12814 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
12815 | { |
12816 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
12817 | return (const reg_entry *) NULL; |
12818 | s++; | |
252b5132 RH |
12819 | } |
12820 | ||
6588847e DN |
12821 | /* For naked regs, make sure that we are not dealing with an identifier. |
12822 | This prevents confusing an identifier like `eax_var' with register | |
12823 | `eax'. */ | |
12824 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
12825 | return (const reg_entry *) NULL; | |
12826 | ||
af6bdddf | 12827 | *end_op = s; |
252b5132 | 12828 | |
629310ab | 12829 | r = (const reg_entry *) str_hash_find (reg_hash, reg_name_given); |
252b5132 | 12830 | |
5f47d35b | 12831 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
6288d05f | 12832 | if (r == reg_st0) |
5f47d35b | 12833 | { |
0e0eea78 JB |
12834 | if (!cpu_arch_flags.bitfield.cpu8087 |
12835 | && !cpu_arch_flags.bitfield.cpu287 | |
af32b722 JB |
12836 | && !cpu_arch_flags.bitfield.cpu387 |
12837 | && !allow_pseudo_reg) | |
0e0eea78 JB |
12838 | return (const reg_entry *) NULL; |
12839 | ||
5f47d35b AM |
12840 | if (is_space_char (*s)) |
12841 | ++s; | |
12842 | if (*s == '(') | |
12843 | { | |
af6bdddf | 12844 | ++s; |
5f47d35b AM |
12845 | if (is_space_char (*s)) |
12846 | ++s; | |
12847 | if (*s >= '0' && *s <= '7') | |
12848 | { | |
db557034 | 12849 | int fpr = *s - '0'; |
af6bdddf | 12850 | ++s; |
5f47d35b AM |
12851 | if (is_space_char (*s)) |
12852 | ++s; | |
12853 | if (*s == ')') | |
12854 | { | |
12855 | *end_op = s + 1; | |
6288d05f | 12856 | know (r[fpr].reg_num == fpr); |
db557034 | 12857 | return r + fpr; |
5f47d35b | 12858 | } |
5f47d35b | 12859 | } |
47926f60 | 12860 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
12861 | return (const reg_entry *) NULL; |
12862 | } | |
12863 | } | |
12864 | ||
8a6fb3f9 | 12865 | return r && check_register (r) ? r : NULL; |
252b5132 | 12866 | } |
4d1bb795 JB |
12867 | |
12868 | /* REG_STRING starts *before* REGISTER_PREFIX. */ | |
12869 | ||
12870 | static const reg_entry * | |
12871 | parse_register (char *reg_string, char **end_op) | |
12872 | { | |
12873 | const reg_entry *r; | |
12874 | ||
12875 | if (*reg_string == REGISTER_PREFIX || allow_naked_reg) | |
12876 | r = parse_real_register (reg_string, end_op); | |
12877 | else | |
12878 | r = NULL; | |
12879 | if (!r) | |
12880 | { | |
12881 | char *save = input_line_pointer; | |
12882 | char c; | |
12883 | symbolS *symbolP; | |
12884 | ||
12885 | input_line_pointer = reg_string; | |
d02603dc | 12886 | c = get_symbol_name (®_string); |
4d1bb795 JB |
12887 | symbolP = symbol_find (reg_string); |
12888 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) | |
12889 | { | |
12890 | const expressionS *e = symbol_get_value_expression (symbolP); | |
12891 | ||
0398aac5 | 12892 | know (e->X_op == O_register); |
4eed87de | 12893 | know (e->X_add_number >= 0 |
c3fe08fa | 12894 | && (valueT) e->X_add_number < i386_regtab_size); |
4d1bb795 | 12895 | r = i386_regtab + e->X_add_number; |
8a6fb3f9 JB |
12896 | if (!check_register (r)) |
12897 | { | |
12898 | as_bad (_("register '%s%s' cannot be used here"), | |
12899 | register_prefix, r->reg_name); | |
12900 | r = &bad_reg; | |
12901 | } | |
4d1bb795 JB |
12902 | *end_op = input_line_pointer; |
12903 | } | |
12904 | *input_line_pointer = c; | |
12905 | input_line_pointer = save; | |
12906 | } | |
12907 | return r; | |
12908 | } | |
12909 | ||
12910 | int | |
12911 | i386_parse_name (char *name, expressionS *e, char *nextcharP) | |
12912 | { | |
12913 | const reg_entry *r; | |
12914 | char *end = input_line_pointer; | |
12915 | ||
12916 | *end = *nextcharP; | |
12917 | r = parse_register (name, &input_line_pointer); | |
12918 | if (r && end <= input_line_pointer) | |
12919 | { | |
12920 | *nextcharP = *input_line_pointer; | |
12921 | *input_line_pointer = 0; | |
8a6fb3f9 JB |
12922 | if (r != &bad_reg) |
12923 | { | |
12924 | e->X_op = O_register; | |
12925 | e->X_add_number = r - i386_regtab; | |
12926 | } | |
12927 | else | |
12928 | e->X_op = O_illegal; | |
4d1bb795 JB |
12929 | return 1; |
12930 | } | |
12931 | input_line_pointer = end; | |
12932 | *end = 0; | |
ee86248c | 12933 | return intel_syntax ? i386_intel_parse_name (name, e) : 0; |
4d1bb795 JB |
12934 | } |
12935 | ||
12936 | void | |
12937 | md_operand (expressionS *e) | |
12938 | { | |
ee86248c JB |
12939 | char *end; |
12940 | const reg_entry *r; | |
4d1bb795 | 12941 | |
ee86248c JB |
12942 | switch (*input_line_pointer) |
12943 | { | |
12944 | case REGISTER_PREFIX: | |
12945 | r = parse_real_register (input_line_pointer, &end); | |
4d1bb795 JB |
12946 | if (r) |
12947 | { | |
12948 | e->X_op = O_register; | |
12949 | e->X_add_number = r - i386_regtab; | |
12950 | input_line_pointer = end; | |
12951 | } | |
ee86248c JB |
12952 | break; |
12953 | ||
12954 | case '[': | |
9c2799c2 | 12955 | gas_assert (intel_syntax); |
ee86248c JB |
12956 | end = input_line_pointer++; |
12957 | expression (e); | |
12958 | if (*input_line_pointer == ']') | |
12959 | { | |
12960 | ++input_line_pointer; | |
12961 | e->X_op_symbol = make_expr_symbol (e); | |
12962 | e->X_add_symbol = NULL; | |
12963 | e->X_add_number = 0; | |
12964 | e->X_op = O_index; | |
12965 | } | |
12966 | else | |
12967 | { | |
12968 | e->X_op = O_absent; | |
12969 | input_line_pointer = end; | |
12970 | } | |
12971 | break; | |
4d1bb795 JB |
12972 | } |
12973 | } | |
12974 | ||
252b5132 | 12975 | \f |
4cc782b5 | 12976 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
b6f8c7c4 | 12977 | const char *md_shortopts = "kVQ:sqnO::"; |
252b5132 | 12978 | #else |
b6f8c7c4 | 12979 | const char *md_shortopts = "qnO::"; |
252b5132 | 12980 | #endif |
6e0b89ee | 12981 | |
3e73aa7c | 12982 | #define OPTION_32 (OPTION_MD_BASE + 0) |
b3b91714 AM |
12983 | #define OPTION_64 (OPTION_MD_BASE + 1) |
12984 | #define OPTION_DIVIDE (OPTION_MD_BASE + 2) | |
9103f4f4 L |
12985 | #define OPTION_MARCH (OPTION_MD_BASE + 3) |
12986 | #define OPTION_MTUNE (OPTION_MD_BASE + 4) | |
1efbbeb4 L |
12987 | #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) |
12988 | #define OPTION_MSYNTAX (OPTION_MD_BASE + 6) | |
12989 | #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) | |
12990 | #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) | |
bd5dea88 | 12991 | #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9) |
c0f3af97 | 12992 | #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10) |
daf50ae7 | 12993 | #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11) |
7bab8ab5 JB |
12994 | #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12) |
12995 | #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13) | |
12996 | #define OPTION_X32 (OPTION_MD_BASE + 14) | |
7e8b059b | 12997 | #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15) |
43234a1e L |
12998 | #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16) |
12999 | #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17) | |
167ad85b | 13000 | #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18) |
d1982f93 | 13001 | #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19) |
d3d3c6db | 13002 | #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20) |
8dcea932 | 13003 | #define OPTION_MSHARED (OPTION_MD_BASE + 21) |
5db04b09 L |
13004 | #define OPTION_MAMD64 (OPTION_MD_BASE + 22) |
13005 | #define OPTION_MINTEL64 (OPTION_MD_BASE + 23) | |
e4e00185 | 13006 | #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24) |
b4a3a7b4 | 13007 | #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25) |
03751133 | 13008 | #define OPTION_MVEXWIG (OPTION_MD_BASE + 26) |
e379e5f3 L |
13009 | #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27) |
13010 | #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28) | |
13011 | #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29) | |
76cf450b | 13012 | #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30) |
ae531041 L |
13013 | #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31) |
13014 | #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32) | |
13015 | #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33) | |
b3b91714 | 13016 | |
99ad8390 NC |
13017 | struct option md_longopts[] = |
13018 | { | |
3e73aa7c | 13019 | {"32", no_argument, NULL, OPTION_32}, |
321098a5 | 13020 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 13021 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c | 13022 | {"64", no_argument, NULL, OPTION_64}, |
351f65ca L |
13023 | #endif |
13024 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
570561f7 | 13025 | {"x32", no_argument, NULL, OPTION_X32}, |
8dcea932 | 13026 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
b4a3a7b4 | 13027 | {"mx86-used-note", required_argument, NULL, OPTION_X86_USED_NOTE}, |
6e0b89ee | 13028 | #endif |
b3b91714 | 13029 | {"divide", no_argument, NULL, OPTION_DIVIDE}, |
9103f4f4 L |
13030 | {"march", required_argument, NULL, OPTION_MARCH}, |
13031 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1efbbeb4 L |
13032 | {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, |
13033 | {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, | |
13034 | {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, | |
13035 | {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, | |
c0f3af97 | 13036 | {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX}, |
daf50ae7 | 13037 | {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK}, |
7bab8ab5 | 13038 | {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK}, |
539f890d | 13039 | {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR}, |
03751133 | 13040 | {"mvexwig", required_argument, NULL, OPTION_MVEXWIG}, |
7e8b059b | 13041 | {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX}, |
43234a1e L |
13042 | {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG}, |
13043 | {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG}, | |
167ad85b TG |
13044 | # if defined (TE_PE) || defined (TE_PEP) |
13045 | {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ}, | |
13046 | #endif | |
d1982f93 | 13047 | {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX}, |
e4e00185 | 13048 | {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD}, |
0cb4071e | 13049 | {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS}, |
d3d3c6db | 13050 | {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG}, |
e379e5f3 L |
13051 | {"malign-branch-boundary", required_argument, NULL, OPTION_MALIGN_BRANCH_BOUNDARY}, |
13052 | {"malign-branch-prefix-size", required_argument, NULL, OPTION_MALIGN_BRANCH_PREFIX_SIZE}, | |
13053 | {"malign-branch", required_argument, NULL, OPTION_MALIGN_BRANCH}, | |
76cf450b | 13054 | {"mbranches-within-32B-boundaries", no_argument, NULL, OPTION_MBRANCHES_WITH_32B_BOUNDARIES}, |
ae531041 L |
13055 | {"mlfence-after-load", required_argument, NULL, OPTION_MLFENCE_AFTER_LOAD}, |
13056 | {"mlfence-before-indirect-branch", required_argument, NULL, | |
13057 | OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH}, | |
13058 | {"mlfence-before-ret", required_argument, NULL, OPTION_MLFENCE_BEFORE_RET}, | |
5db04b09 L |
13059 | {"mamd64", no_argument, NULL, OPTION_MAMD64}, |
13060 | {"mintel64", no_argument, NULL, OPTION_MINTEL64}, | |
252b5132 RH |
13061 | {NULL, no_argument, NULL, 0} |
13062 | }; | |
13063 | size_t md_longopts_size = sizeof (md_longopts); | |
13064 | ||
13065 | int | |
17b9d67d | 13066 | md_parse_option (int c, const char *arg) |
252b5132 | 13067 | { |
91d6fa6a | 13068 | unsigned int j; |
e379e5f3 | 13069 | char *arch, *next, *saved, *type; |
9103f4f4 | 13070 | |
252b5132 RH |
13071 | switch (c) |
13072 | { | |
12b55ccc L |
13073 | case 'n': |
13074 | optimize_align_code = 0; | |
13075 | break; | |
13076 | ||
a38cf1db AM |
13077 | case 'q': |
13078 | quiet_warnings = 1; | |
252b5132 RH |
13079 | break; |
13080 | ||
13081 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
13082 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
13083 | should be emitted or not. FIXME: Not implemented. */ | |
13084 | case 'Q': | |
d4693039 JB |
13085 | if ((arg[0] != 'y' && arg[0] != 'n') || arg[1]) |
13086 | return 0; | |
252b5132 RH |
13087 | break; |
13088 | ||
13089 | /* -V: SVR4 argument to print version ID. */ | |
13090 | case 'V': | |
13091 | print_version_id (); | |
13092 | break; | |
13093 | ||
a38cf1db AM |
13094 | /* -k: Ignore for FreeBSD compatibility. */ |
13095 | case 'k': | |
252b5132 | 13096 | break; |
4cc782b5 ILT |
13097 | |
13098 | case 's': | |
13099 | /* -s: On i386 Solaris, this tells the native assembler to use | |
29b0f896 | 13100 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
4cc782b5 | 13101 | break; |
8dcea932 L |
13102 | |
13103 | case OPTION_MSHARED: | |
13104 | shared = 1; | |
13105 | break; | |
b4a3a7b4 L |
13106 | |
13107 | case OPTION_X86_USED_NOTE: | |
13108 | if (strcasecmp (arg, "yes") == 0) | |
13109 | x86_used_note = 1; | |
13110 | else if (strcasecmp (arg, "no") == 0) | |
13111 | x86_used_note = 0; | |
13112 | else | |
13113 | as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg); | |
13114 | break; | |
13115 | ||
13116 | ||
99ad8390 | 13117 | #endif |
321098a5 | 13118 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 13119 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c JH |
13120 | case OPTION_64: |
13121 | { | |
13122 | const char **list, **l; | |
13123 | ||
3e73aa7c JH |
13124 | list = bfd_target_list (); |
13125 | for (l = list; *l != NULL; l++) | |
08dedd66 | 13126 | if (startswith (*l, "elf64-x86-64") |
99ad8390 NC |
13127 | || strcmp (*l, "coff-x86-64") == 0 |
13128 | || strcmp (*l, "pe-x86-64") == 0 | |
d382c579 TG |
13129 | || strcmp (*l, "pei-x86-64") == 0 |
13130 | || strcmp (*l, "mach-o-x86-64") == 0) | |
6e0b89ee AM |
13131 | { |
13132 | default_arch = "x86_64"; | |
13133 | break; | |
13134 | } | |
3e73aa7c | 13135 | if (*l == NULL) |
2b5d6a91 | 13136 | as_fatal (_("no compiled in support for x86_64")); |
3e73aa7c JH |
13137 | free (list); |
13138 | } | |
13139 | break; | |
13140 | #endif | |
252b5132 | 13141 | |
351f65ca | 13142 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
570561f7 | 13143 | case OPTION_X32: |
351f65ca L |
13144 | if (IS_ELF) |
13145 | { | |
13146 | const char **list, **l; | |
13147 | ||
13148 | list = bfd_target_list (); | |
13149 | for (l = list; *l != NULL; l++) | |
08dedd66 | 13150 | if (startswith (*l, "elf32-x86-64")) |
351f65ca L |
13151 | { |
13152 | default_arch = "x86_64:32"; | |
13153 | break; | |
13154 | } | |
13155 | if (*l == NULL) | |
2b5d6a91 | 13156 | as_fatal (_("no compiled in support for 32bit x86_64")); |
351f65ca L |
13157 | free (list); |
13158 | } | |
13159 | else | |
13160 | as_fatal (_("32bit x86_64 is only supported for ELF")); | |
13161 | break; | |
13162 | #endif | |
13163 | ||
6e0b89ee AM |
13164 | case OPTION_32: |
13165 | default_arch = "i386"; | |
13166 | break; | |
13167 | ||
b3b91714 AM |
13168 | case OPTION_DIVIDE: |
13169 | #ifdef SVR4_COMMENT_CHARS | |
13170 | { | |
13171 | char *n, *t; | |
13172 | const char *s; | |
13173 | ||
add39d23 | 13174 | n = XNEWVEC (char, strlen (i386_comment_chars) + 1); |
b3b91714 AM |
13175 | t = n; |
13176 | for (s = i386_comment_chars; *s != '\0'; s++) | |
13177 | if (*s != '/') | |
13178 | *t++ = *s; | |
13179 | *t = '\0'; | |
13180 | i386_comment_chars = n; | |
13181 | } | |
13182 | #endif | |
13183 | break; | |
13184 | ||
9103f4f4 | 13185 | case OPTION_MARCH: |
293f5f65 L |
13186 | saved = xstrdup (arg); |
13187 | arch = saved; | |
13188 | /* Allow -march=+nosse. */ | |
13189 | if (*arch == '+') | |
13190 | arch++; | |
6305a203 | 13191 | do |
9103f4f4 | 13192 | { |
6305a203 | 13193 | if (*arch == '.') |
2b5d6a91 | 13194 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
13195 | next = strchr (arch, '+'); |
13196 | if (next) | |
13197 | *next++ = '\0'; | |
91d6fa6a | 13198 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 13199 | { |
91d6fa6a | 13200 | if (strcmp (arch, cpu_arch [j].name) == 0) |
ccc9c027 | 13201 | { |
6305a203 | 13202 | /* Processor. */ |
1ded5609 JB |
13203 | if (! cpu_arch[j].flags.bitfield.cpui386) |
13204 | continue; | |
13205 | ||
91d6fa6a | 13206 | cpu_arch_name = cpu_arch[j].name; |
6305a203 | 13207 | cpu_sub_arch_name = NULL; |
91d6fa6a NC |
13208 | cpu_arch_flags = cpu_arch[j].flags; |
13209 | cpu_arch_isa = cpu_arch[j].type; | |
13210 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
6305a203 L |
13211 | if (!cpu_arch_tune_set) |
13212 | { | |
13213 | cpu_arch_tune = cpu_arch_isa; | |
13214 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
13215 | } | |
13216 | break; | |
13217 | } | |
91d6fa6a NC |
13218 | else if (*cpu_arch [j].name == '.' |
13219 | && strcmp (arch, cpu_arch [j].name + 1) == 0) | |
6305a203 | 13220 | { |
33eaf5de | 13221 | /* ISA extension. */ |
6305a203 | 13222 | i386_cpu_flags flags; |
309d3373 | 13223 | |
293f5f65 L |
13224 | flags = cpu_flags_or (cpu_arch_flags, |
13225 | cpu_arch[j].flags); | |
81486035 | 13226 | |
5b64d091 | 13227 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
6305a203 L |
13228 | { |
13229 | if (cpu_sub_arch_name) | |
13230 | { | |
13231 | char *name = cpu_sub_arch_name; | |
13232 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 13233 | cpu_arch[j].name, |
1bf57e9f | 13234 | (const char *) NULL); |
6305a203 L |
13235 | free (name); |
13236 | } | |
13237 | else | |
91d6fa6a | 13238 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
6305a203 | 13239 | cpu_arch_flags = flags; |
a586129e | 13240 | cpu_arch_isa_flags = flags; |
6305a203 | 13241 | } |
0089dace L |
13242 | else |
13243 | cpu_arch_isa_flags | |
13244 | = cpu_flags_or (cpu_arch_isa_flags, | |
13245 | cpu_arch[j].flags); | |
6305a203 | 13246 | break; |
ccc9c027 | 13247 | } |
9103f4f4 | 13248 | } |
6305a203 | 13249 | |
293f5f65 L |
13250 | if (j >= ARRAY_SIZE (cpu_arch)) |
13251 | { | |
33eaf5de | 13252 | /* Disable an ISA extension. */ |
293f5f65 L |
13253 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
13254 | if (strcmp (arch, cpu_noarch [j].name) == 0) | |
13255 | { | |
13256 | i386_cpu_flags flags; | |
13257 | ||
13258 | flags = cpu_flags_and_not (cpu_arch_flags, | |
13259 | cpu_noarch[j].flags); | |
13260 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
13261 | { | |
13262 | if (cpu_sub_arch_name) | |
13263 | { | |
13264 | char *name = cpu_sub_arch_name; | |
13265 | cpu_sub_arch_name = concat (arch, | |
13266 | (const char *) NULL); | |
13267 | free (name); | |
13268 | } | |
13269 | else | |
13270 | cpu_sub_arch_name = xstrdup (arch); | |
13271 | cpu_arch_flags = flags; | |
13272 | cpu_arch_isa_flags = flags; | |
13273 | } | |
13274 | break; | |
13275 | } | |
13276 | ||
13277 | if (j >= ARRAY_SIZE (cpu_noarch)) | |
13278 | j = ARRAY_SIZE (cpu_arch); | |
13279 | } | |
13280 | ||
91d6fa6a | 13281 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 13282 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
13283 | |
13284 | arch = next; | |
9103f4f4 | 13285 | } |
293f5f65 L |
13286 | while (next != NULL); |
13287 | free (saved); | |
9103f4f4 L |
13288 | break; |
13289 | ||
13290 | case OPTION_MTUNE: | |
13291 | if (*arg == '.') | |
2b5d6a91 | 13292 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
91d6fa6a | 13293 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 13294 | { |
91d6fa6a | 13295 | if (strcmp (arg, cpu_arch [j].name) == 0) |
9103f4f4 | 13296 | { |
ccc9c027 | 13297 | cpu_arch_tune_set = 1; |
91d6fa6a NC |
13298 | cpu_arch_tune = cpu_arch [j].type; |
13299 | cpu_arch_tune_flags = cpu_arch[j].flags; | |
9103f4f4 L |
13300 | break; |
13301 | } | |
13302 | } | |
91d6fa6a | 13303 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 13304 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
9103f4f4 L |
13305 | break; |
13306 | ||
1efbbeb4 L |
13307 | case OPTION_MMNEMONIC: |
13308 | if (strcasecmp (arg, "att") == 0) | |
13309 | intel_mnemonic = 0; | |
13310 | else if (strcasecmp (arg, "intel") == 0) | |
13311 | intel_mnemonic = 1; | |
13312 | else | |
2b5d6a91 | 13313 | as_fatal (_("invalid -mmnemonic= option: `%s'"), arg); |
1efbbeb4 L |
13314 | break; |
13315 | ||
13316 | case OPTION_MSYNTAX: | |
13317 | if (strcasecmp (arg, "att") == 0) | |
13318 | intel_syntax = 0; | |
13319 | else if (strcasecmp (arg, "intel") == 0) | |
13320 | intel_syntax = 1; | |
13321 | else | |
2b5d6a91 | 13322 | as_fatal (_("invalid -msyntax= option: `%s'"), arg); |
1efbbeb4 L |
13323 | break; |
13324 | ||
13325 | case OPTION_MINDEX_REG: | |
13326 | allow_index_reg = 1; | |
13327 | break; | |
13328 | ||
13329 | case OPTION_MNAKED_REG: | |
13330 | allow_naked_reg = 1; | |
13331 | break; | |
13332 | ||
c0f3af97 L |
13333 | case OPTION_MSSE2AVX: |
13334 | sse2avx = 1; | |
13335 | break; | |
13336 | ||
daf50ae7 L |
13337 | case OPTION_MSSE_CHECK: |
13338 | if (strcasecmp (arg, "error") == 0) | |
7bab8ab5 | 13339 | sse_check = check_error; |
daf50ae7 | 13340 | else if (strcasecmp (arg, "warning") == 0) |
7bab8ab5 | 13341 | sse_check = check_warning; |
daf50ae7 | 13342 | else if (strcasecmp (arg, "none") == 0) |
7bab8ab5 | 13343 | sse_check = check_none; |
daf50ae7 | 13344 | else |
2b5d6a91 | 13345 | as_fatal (_("invalid -msse-check= option: `%s'"), arg); |
daf50ae7 L |
13346 | break; |
13347 | ||
7bab8ab5 JB |
13348 | case OPTION_MOPERAND_CHECK: |
13349 | if (strcasecmp (arg, "error") == 0) | |
13350 | operand_check = check_error; | |
13351 | else if (strcasecmp (arg, "warning") == 0) | |
13352 | operand_check = check_warning; | |
13353 | else if (strcasecmp (arg, "none") == 0) | |
13354 | operand_check = check_none; | |
13355 | else | |
13356 | as_fatal (_("invalid -moperand-check= option: `%s'"), arg); | |
13357 | break; | |
13358 | ||
539f890d L |
13359 | case OPTION_MAVXSCALAR: |
13360 | if (strcasecmp (arg, "128") == 0) | |
13361 | avxscalar = vex128; | |
13362 | else if (strcasecmp (arg, "256") == 0) | |
13363 | avxscalar = vex256; | |
13364 | else | |
2b5d6a91 | 13365 | as_fatal (_("invalid -mavxscalar= option: `%s'"), arg); |
539f890d L |
13366 | break; |
13367 | ||
03751133 L |
13368 | case OPTION_MVEXWIG: |
13369 | if (strcmp (arg, "0") == 0) | |
40c9c8de | 13370 | vexwig = vexw0; |
03751133 | 13371 | else if (strcmp (arg, "1") == 0) |
40c9c8de | 13372 | vexwig = vexw1; |
03751133 L |
13373 | else |
13374 | as_fatal (_("invalid -mvexwig= option: `%s'"), arg); | |
13375 | break; | |
13376 | ||
7e8b059b L |
13377 | case OPTION_MADD_BND_PREFIX: |
13378 | add_bnd_prefix = 1; | |
13379 | break; | |
13380 | ||
43234a1e L |
13381 | case OPTION_MEVEXLIG: |
13382 | if (strcmp (arg, "128") == 0) | |
13383 | evexlig = evexl128; | |
13384 | else if (strcmp (arg, "256") == 0) | |
13385 | evexlig = evexl256; | |
13386 | else if (strcmp (arg, "512") == 0) | |
13387 | evexlig = evexl512; | |
13388 | else | |
13389 | as_fatal (_("invalid -mevexlig= option: `%s'"), arg); | |
13390 | break; | |
13391 | ||
d3d3c6db IT |
13392 | case OPTION_MEVEXRCIG: |
13393 | if (strcmp (arg, "rne") == 0) | |
13394 | evexrcig = rne; | |
13395 | else if (strcmp (arg, "rd") == 0) | |
13396 | evexrcig = rd; | |
13397 | else if (strcmp (arg, "ru") == 0) | |
13398 | evexrcig = ru; | |
13399 | else if (strcmp (arg, "rz") == 0) | |
13400 | evexrcig = rz; | |
13401 | else | |
13402 | as_fatal (_("invalid -mevexrcig= option: `%s'"), arg); | |
13403 | break; | |
13404 | ||
43234a1e L |
13405 | case OPTION_MEVEXWIG: |
13406 | if (strcmp (arg, "0") == 0) | |
13407 | evexwig = evexw0; | |
13408 | else if (strcmp (arg, "1") == 0) | |
13409 | evexwig = evexw1; | |
13410 | else | |
13411 | as_fatal (_("invalid -mevexwig= option: `%s'"), arg); | |
13412 | break; | |
13413 | ||
167ad85b TG |
13414 | # if defined (TE_PE) || defined (TE_PEP) |
13415 | case OPTION_MBIG_OBJ: | |
13416 | use_big_obj = 1; | |
13417 | break; | |
13418 | #endif | |
13419 | ||
d1982f93 | 13420 | case OPTION_MOMIT_LOCK_PREFIX: |
d022bddd IT |
13421 | if (strcasecmp (arg, "yes") == 0) |
13422 | omit_lock_prefix = 1; | |
13423 | else if (strcasecmp (arg, "no") == 0) | |
13424 | omit_lock_prefix = 0; | |
13425 | else | |
13426 | as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg); | |
13427 | break; | |
13428 | ||
e4e00185 AS |
13429 | case OPTION_MFENCE_AS_LOCK_ADD: |
13430 | if (strcasecmp (arg, "yes") == 0) | |
13431 | avoid_fence = 1; | |
13432 | else if (strcasecmp (arg, "no") == 0) | |
13433 | avoid_fence = 0; | |
13434 | else | |
13435 | as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg); | |
13436 | break; | |
13437 | ||
ae531041 L |
13438 | case OPTION_MLFENCE_AFTER_LOAD: |
13439 | if (strcasecmp (arg, "yes") == 0) | |
13440 | lfence_after_load = 1; | |
13441 | else if (strcasecmp (arg, "no") == 0) | |
13442 | lfence_after_load = 0; | |
13443 | else | |
13444 | as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg); | |
13445 | break; | |
13446 | ||
13447 | case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH: | |
13448 | if (strcasecmp (arg, "all") == 0) | |
a09f656b | 13449 | { |
13450 | lfence_before_indirect_branch = lfence_branch_all; | |
13451 | if (lfence_before_ret == lfence_before_ret_none) | |
13452 | lfence_before_ret = lfence_before_ret_shl; | |
13453 | } | |
ae531041 L |
13454 | else if (strcasecmp (arg, "memory") == 0) |
13455 | lfence_before_indirect_branch = lfence_branch_memory; | |
13456 | else if (strcasecmp (arg, "register") == 0) | |
13457 | lfence_before_indirect_branch = lfence_branch_register; | |
13458 | else if (strcasecmp (arg, "none") == 0) | |
13459 | lfence_before_indirect_branch = lfence_branch_none; | |
13460 | else | |
13461 | as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"), | |
13462 | arg); | |
13463 | break; | |
13464 | ||
13465 | case OPTION_MLFENCE_BEFORE_RET: | |
13466 | if (strcasecmp (arg, "or") == 0) | |
13467 | lfence_before_ret = lfence_before_ret_or; | |
13468 | else if (strcasecmp (arg, "not") == 0) | |
13469 | lfence_before_ret = lfence_before_ret_not; | |
a09f656b | 13470 | else if (strcasecmp (arg, "shl") == 0 || strcasecmp (arg, "yes") == 0) |
13471 | lfence_before_ret = lfence_before_ret_shl; | |
ae531041 L |
13472 | else if (strcasecmp (arg, "none") == 0) |
13473 | lfence_before_ret = lfence_before_ret_none; | |
13474 | else | |
13475 | as_fatal (_("invalid -mlfence-before-ret= option: `%s'"), | |
13476 | arg); | |
13477 | break; | |
13478 | ||
0cb4071e L |
13479 | case OPTION_MRELAX_RELOCATIONS: |
13480 | if (strcasecmp (arg, "yes") == 0) | |
13481 | generate_relax_relocations = 1; | |
13482 | else if (strcasecmp (arg, "no") == 0) | |
13483 | generate_relax_relocations = 0; | |
13484 | else | |
13485 | as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg); | |
13486 | break; | |
13487 | ||
e379e5f3 L |
13488 | case OPTION_MALIGN_BRANCH_BOUNDARY: |
13489 | { | |
13490 | char *end; | |
13491 | long int align = strtoul (arg, &end, 0); | |
13492 | if (*end == '\0') | |
13493 | { | |
13494 | if (align == 0) | |
13495 | { | |
13496 | align_branch_power = 0; | |
13497 | break; | |
13498 | } | |
13499 | else if (align >= 16) | |
13500 | { | |
13501 | int align_power; | |
13502 | for (align_power = 0; | |
13503 | (align & 1) == 0; | |
13504 | align >>= 1, align_power++) | |
13505 | continue; | |
13506 | /* Limit alignment power to 31. */ | |
13507 | if (align == 1 && align_power < 32) | |
13508 | { | |
13509 | align_branch_power = align_power; | |
13510 | break; | |
13511 | } | |
13512 | } | |
13513 | } | |
13514 | as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg); | |
13515 | } | |
13516 | break; | |
13517 | ||
13518 | case OPTION_MALIGN_BRANCH_PREFIX_SIZE: | |
13519 | { | |
13520 | char *end; | |
13521 | int align = strtoul (arg, &end, 0); | |
13522 | /* Some processors only support 5 prefixes. */ | |
13523 | if (*end == '\0' && align >= 0 && align < 6) | |
13524 | { | |
13525 | align_branch_prefix_size = align; | |
13526 | break; | |
13527 | } | |
13528 | as_fatal (_("invalid -malign-branch-prefix-size= value: %s"), | |
13529 | arg); | |
13530 | } | |
13531 | break; | |
13532 | ||
13533 | case OPTION_MALIGN_BRANCH: | |
13534 | align_branch = 0; | |
13535 | saved = xstrdup (arg); | |
13536 | type = saved; | |
13537 | do | |
13538 | { | |
13539 | next = strchr (type, '+'); | |
13540 | if (next) | |
13541 | *next++ = '\0'; | |
13542 | if (strcasecmp (type, "jcc") == 0) | |
13543 | align_branch |= align_branch_jcc_bit; | |
13544 | else if (strcasecmp (type, "fused") == 0) | |
13545 | align_branch |= align_branch_fused_bit; | |
13546 | else if (strcasecmp (type, "jmp") == 0) | |
13547 | align_branch |= align_branch_jmp_bit; | |
13548 | else if (strcasecmp (type, "call") == 0) | |
13549 | align_branch |= align_branch_call_bit; | |
13550 | else if (strcasecmp (type, "ret") == 0) | |
13551 | align_branch |= align_branch_ret_bit; | |
13552 | else if (strcasecmp (type, "indirect") == 0) | |
13553 | align_branch |= align_branch_indirect_bit; | |
13554 | else | |
13555 | as_fatal (_("invalid -malign-branch= option: `%s'"), arg); | |
13556 | type = next; | |
13557 | } | |
13558 | while (next != NULL); | |
13559 | free (saved); | |
13560 | break; | |
13561 | ||
76cf450b L |
13562 | case OPTION_MBRANCHES_WITH_32B_BOUNDARIES: |
13563 | align_branch_power = 5; | |
13564 | align_branch_prefix_size = 5; | |
13565 | align_branch = (align_branch_jcc_bit | |
13566 | | align_branch_fused_bit | |
13567 | | align_branch_jmp_bit); | |
13568 | break; | |
13569 | ||
5db04b09 | 13570 | case OPTION_MAMD64: |
4b5aaf5f | 13571 | isa64 = amd64; |
5db04b09 L |
13572 | break; |
13573 | ||
13574 | case OPTION_MINTEL64: | |
4b5aaf5f | 13575 | isa64 = intel64; |
5db04b09 L |
13576 | break; |
13577 | ||
b6f8c7c4 L |
13578 | case 'O': |
13579 | if (arg == NULL) | |
13580 | { | |
13581 | optimize = 1; | |
13582 | /* Turn off -Os. */ | |
13583 | optimize_for_space = 0; | |
13584 | } | |
13585 | else if (*arg == 's') | |
13586 | { | |
13587 | optimize_for_space = 1; | |
13588 | /* Turn on all encoding optimizations. */ | |
41fd2579 | 13589 | optimize = INT_MAX; |
b6f8c7c4 L |
13590 | } |
13591 | else | |
13592 | { | |
13593 | optimize = atoi (arg); | |
13594 | /* Turn off -Os. */ | |
13595 | optimize_for_space = 0; | |
13596 | } | |
13597 | break; | |
13598 | ||
252b5132 RH |
13599 | default: |
13600 | return 0; | |
13601 | } | |
13602 | return 1; | |
13603 | } | |
13604 | ||
8a2c8fef L |
13605 | #define MESSAGE_TEMPLATE \ |
13606 | " " | |
13607 | ||
293f5f65 L |
13608 | static char * |
13609 | output_message (FILE *stream, char *p, char *message, char *start, | |
13610 | int *left_p, const char *name, int len) | |
13611 | { | |
13612 | int size = sizeof (MESSAGE_TEMPLATE); | |
13613 | int left = *left_p; | |
13614 | ||
13615 | /* Reserve 2 spaces for ", " or ",\0" */ | |
13616 | left -= len + 2; | |
13617 | ||
13618 | /* Check if there is any room. */ | |
13619 | if (left >= 0) | |
13620 | { | |
13621 | if (p != start) | |
13622 | { | |
13623 | *p++ = ','; | |
13624 | *p++ = ' '; | |
13625 | } | |
13626 | p = mempcpy (p, name, len); | |
13627 | } | |
13628 | else | |
13629 | { | |
13630 | /* Output the current message now and start a new one. */ | |
13631 | *p++ = ','; | |
13632 | *p = '\0'; | |
13633 | fprintf (stream, "%s\n", message); | |
13634 | p = start; | |
13635 | left = size - (start - message) - len - 2; | |
13636 | ||
13637 | gas_assert (left >= 0); | |
13638 | ||
13639 | p = mempcpy (p, name, len); | |
13640 | } | |
13641 | ||
13642 | *left_p = left; | |
13643 | return p; | |
13644 | } | |
13645 | ||
8a2c8fef | 13646 | static void |
1ded5609 | 13647 | show_arch (FILE *stream, int ext, int check) |
8a2c8fef L |
13648 | { |
13649 | static char message[] = MESSAGE_TEMPLATE; | |
13650 | char *start = message + 27; | |
13651 | char *p; | |
13652 | int size = sizeof (MESSAGE_TEMPLATE); | |
13653 | int left; | |
13654 | const char *name; | |
13655 | int len; | |
13656 | unsigned int j; | |
13657 | ||
13658 | p = start; | |
13659 | left = size - (start - message); | |
13660 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) | |
13661 | { | |
13662 | /* Should it be skipped? */ | |
13663 | if (cpu_arch [j].skip) | |
13664 | continue; | |
13665 | ||
13666 | name = cpu_arch [j].name; | |
13667 | len = cpu_arch [j].len; | |
13668 | if (*name == '.') | |
13669 | { | |
13670 | /* It is an extension. Skip if we aren't asked to show it. */ | |
13671 | if (ext) | |
13672 | { | |
13673 | name++; | |
13674 | len--; | |
13675 | } | |
13676 | else | |
13677 | continue; | |
13678 | } | |
13679 | else if (ext) | |
13680 | { | |
13681 | /* It is an processor. Skip if we show only extension. */ | |
13682 | continue; | |
13683 | } | |
1ded5609 JB |
13684 | else if (check && ! cpu_arch[j].flags.bitfield.cpui386) |
13685 | { | |
13686 | /* It is an impossible processor - skip. */ | |
13687 | continue; | |
13688 | } | |
8a2c8fef | 13689 | |
293f5f65 | 13690 | p = output_message (stream, p, message, start, &left, name, len); |
8a2c8fef L |
13691 | } |
13692 | ||
293f5f65 L |
13693 | /* Display disabled extensions. */ |
13694 | if (ext) | |
13695 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) | |
13696 | { | |
13697 | name = cpu_noarch [j].name; | |
13698 | len = cpu_noarch [j].len; | |
13699 | p = output_message (stream, p, message, start, &left, name, | |
13700 | len); | |
13701 | } | |
13702 | ||
8a2c8fef L |
13703 | *p = '\0'; |
13704 | fprintf (stream, "%s\n", message); | |
13705 | } | |
13706 | ||
252b5132 | 13707 | void |
8a2c8fef | 13708 | md_show_usage (FILE *stream) |
252b5132 | 13709 | { |
4cc782b5 ILT |
13710 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
13711 | fprintf (stream, _("\ | |
d4693039 | 13712 | -Qy, -Qn ignored\n\ |
a38cf1db | 13713 | -V print assembler version number\n\ |
b3b91714 AM |
13714 | -k ignored\n")); |
13715 | #endif | |
13716 | fprintf (stream, _("\ | |
12b55ccc | 13717 | -n Do not optimize code alignment\n\ |
b3b91714 AM |
13718 | -q quieten some warnings\n")); |
13719 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
13720 | fprintf (stream, _("\ | |
a38cf1db | 13721 | -s ignored\n")); |
b3b91714 | 13722 | #endif |
d7f449c0 L |
13723 | #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
13724 | || defined (TE_PE) || defined (TE_PEP)) | |
751d281c | 13725 | fprintf (stream, _("\ |
570561f7 | 13726 | --32/--64/--x32 generate 32bit/64bit/x32 code\n")); |
751d281c | 13727 | #endif |
b3b91714 AM |
13728 | #ifdef SVR4_COMMENT_CHARS |
13729 | fprintf (stream, _("\ | |
13730 | --divide do not treat `/' as a comment character\n")); | |
a38cf1db AM |
13731 | #else |
13732 | fprintf (stream, _("\ | |
b3b91714 | 13733 | --divide ignored\n")); |
4cc782b5 | 13734 | #endif |
9103f4f4 | 13735 | fprintf (stream, _("\ |
6305a203 | 13736 | -march=CPU[,+EXTENSION...]\n\ |
8a2c8fef | 13737 | generate code for CPU and EXTENSION, CPU is one of:\n")); |
1ded5609 | 13738 | show_arch (stream, 0, 1); |
8a2c8fef L |
13739 | fprintf (stream, _("\ |
13740 | EXTENSION is combination of:\n")); | |
1ded5609 | 13741 | show_arch (stream, 1, 0); |
6305a203 | 13742 | fprintf (stream, _("\ |
8a2c8fef | 13743 | -mtune=CPU optimize for CPU, CPU is one of:\n")); |
1ded5609 | 13744 | show_arch (stream, 0, 0); |
ba104c83 | 13745 | fprintf (stream, _("\ |
c0f3af97 L |
13746 | -msse2avx encode SSE instructions with VEX prefix\n")); |
13747 | fprintf (stream, _("\ | |
7c5c05ef | 13748 | -msse-check=[none|error|warning] (default: warning)\n\ |
daf50ae7 L |
13749 | check SSE instructions\n")); |
13750 | fprintf (stream, _("\ | |
7c5c05ef | 13751 | -moperand-check=[none|error|warning] (default: warning)\n\ |
7bab8ab5 JB |
13752 | check operand combinations for validity\n")); |
13753 | fprintf (stream, _("\ | |
7c5c05ef L |
13754 | -mavxscalar=[128|256] (default: 128)\n\ |
13755 | encode scalar AVX instructions with specific vector\n\ | |
539f890d L |
13756 | length\n")); |
13757 | fprintf (stream, _("\ | |
03751133 L |
13758 | -mvexwig=[0|1] (default: 0)\n\ |
13759 | encode VEX instructions with specific VEX.W value\n\ | |
13760 | for VEX.W bit ignored instructions\n")); | |
13761 | fprintf (stream, _("\ | |
7c5c05ef L |
13762 | -mevexlig=[128|256|512] (default: 128)\n\ |
13763 | encode scalar EVEX instructions with specific vector\n\ | |
43234a1e L |
13764 | length\n")); |
13765 | fprintf (stream, _("\ | |
7c5c05ef L |
13766 | -mevexwig=[0|1] (default: 0)\n\ |
13767 | encode EVEX instructions with specific EVEX.W value\n\ | |
43234a1e L |
13768 | for EVEX.W bit ignored instructions\n")); |
13769 | fprintf (stream, _("\ | |
7c5c05ef | 13770 | -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\ |
d3d3c6db IT |
13771 | encode EVEX instructions with specific EVEX.RC value\n\ |
13772 | for SAE-only ignored instructions\n")); | |
13773 | fprintf (stream, _("\ | |
7c5c05ef L |
13774 | -mmnemonic=[att|intel] ")); |
13775 | if (SYSV386_COMPAT) | |
13776 | fprintf (stream, _("(default: att)\n")); | |
13777 | else | |
13778 | fprintf (stream, _("(default: intel)\n")); | |
13779 | fprintf (stream, _("\ | |
13780 | use AT&T/Intel mnemonic\n")); | |
ba104c83 | 13781 | fprintf (stream, _("\ |
7c5c05ef L |
13782 | -msyntax=[att|intel] (default: att)\n\ |
13783 | use AT&T/Intel syntax\n")); | |
ba104c83 L |
13784 | fprintf (stream, _("\ |
13785 | -mindex-reg support pseudo index registers\n")); | |
13786 | fprintf (stream, _("\ | |
13787 | -mnaked-reg don't require `%%' prefix for registers\n")); | |
13788 | fprintf (stream, _("\ | |
7e8b059b | 13789 | -madd-bnd-prefix add BND prefix for all valid branches\n")); |
b4a3a7b4 | 13790 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8dcea932 L |
13791 | fprintf (stream, _("\ |
13792 | -mshared disable branch optimization for shared code\n")); | |
b4a3a7b4 L |
13793 | fprintf (stream, _("\ |
13794 | -mx86-used-note=[no|yes] ")); | |
13795 | if (DEFAULT_X86_USED_NOTE) | |
13796 | fprintf (stream, _("(default: yes)\n")); | |
13797 | else | |
13798 | fprintf (stream, _("(default: no)\n")); | |
13799 | fprintf (stream, _("\ | |
13800 | generate x86 used ISA and feature properties\n")); | |
13801 | #endif | |
13802 | #if defined (TE_PE) || defined (TE_PEP) | |
167ad85b TG |
13803 | fprintf (stream, _("\ |
13804 | -mbig-obj generate big object files\n")); | |
13805 | #endif | |
d022bddd | 13806 | fprintf (stream, _("\ |
7c5c05ef | 13807 | -momit-lock-prefix=[no|yes] (default: no)\n\ |
d022bddd | 13808 | strip all lock prefixes\n")); |
5db04b09 | 13809 | fprintf (stream, _("\ |
7c5c05ef | 13810 | -mfence-as-lock-add=[no|yes] (default: no)\n\ |
e4e00185 AS |
13811 | encode lfence, mfence and sfence as\n\ |
13812 | lock addl $0x0, (%%{re}sp)\n")); | |
13813 | fprintf (stream, _("\ | |
7c5c05ef L |
13814 | -mrelax-relocations=[no|yes] ")); |
13815 | if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS) | |
13816 | fprintf (stream, _("(default: yes)\n")); | |
13817 | else | |
13818 | fprintf (stream, _("(default: no)\n")); | |
13819 | fprintf (stream, _("\ | |
0cb4071e L |
13820 | generate relax relocations\n")); |
13821 | fprintf (stream, _("\ | |
e379e5f3 L |
13822 | -malign-branch-boundary=NUM (default: 0)\n\ |
13823 | align branches within NUM byte boundary\n")); | |
13824 | fprintf (stream, _("\ | |
13825 | -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\ | |
13826 | TYPE is combination of jcc, fused, jmp, call, ret,\n\ | |
13827 | indirect\n\ | |
13828 | specify types of branches to align\n")); | |
13829 | fprintf (stream, _("\ | |
13830 | -malign-branch-prefix-size=NUM (default: 5)\n\ | |
13831 | align branches with NUM prefixes per instruction\n")); | |
13832 | fprintf (stream, _("\ | |
76cf450b L |
13833 | -mbranches-within-32B-boundaries\n\ |
13834 | align branches within 32 byte boundary\n")); | |
13835 | fprintf (stream, _("\ | |
ae531041 L |
13836 | -mlfence-after-load=[no|yes] (default: no)\n\ |
13837 | generate lfence after load\n")); | |
13838 | fprintf (stream, _("\ | |
13839 | -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\ | |
13840 | generate lfence before indirect near branch\n")); | |
13841 | fprintf (stream, _("\ | |
a09f656b | 13842 | -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\ |
ae531041 L |
13843 | generate lfence before ret\n")); |
13844 | fprintf (stream, _("\ | |
7c5c05ef | 13845 | -mamd64 accept only AMD64 ISA [default]\n")); |
5db04b09 L |
13846 | fprintf (stream, _("\ |
13847 | -mintel64 accept only Intel64 ISA\n")); | |
252b5132 RH |
13848 | } |
13849 | ||
3e73aa7c | 13850 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
321098a5 | 13851 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
e57f8c65 | 13852 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
252b5132 RH |
13853 | |
13854 | /* Pick the target format to use. */ | |
13855 | ||
47926f60 | 13856 | const char * |
e3bb37b5 | 13857 | i386_target_format (void) |
252b5132 | 13858 | { |
d34049e8 | 13859 | if (startswith (default_arch, "x86_64")) |
351f65ca L |
13860 | { |
13861 | update_code_flag (CODE_64BIT, 1); | |
13862 | if (default_arch[6] == '\0') | |
7f56bc95 | 13863 | x86_elf_abi = X86_64_ABI; |
351f65ca | 13864 | else |
7f56bc95 | 13865 | x86_elf_abi = X86_64_X32_ABI; |
351f65ca | 13866 | } |
3e73aa7c | 13867 | else if (!strcmp (default_arch, "i386")) |
78f12dd3 | 13868 | update_code_flag (CODE_32BIT, 1); |
5197d474 L |
13869 | else if (!strcmp (default_arch, "iamcu")) |
13870 | { | |
13871 | update_code_flag (CODE_32BIT, 1); | |
13872 | if (cpu_arch_isa == PROCESSOR_UNKNOWN) | |
13873 | { | |
13874 | static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS; | |
13875 | cpu_arch_name = "iamcu"; | |
13876 | cpu_sub_arch_name = NULL; | |
13877 | cpu_arch_flags = iamcu_flags; | |
13878 | cpu_arch_isa = PROCESSOR_IAMCU; | |
13879 | cpu_arch_isa_flags = iamcu_flags; | |
13880 | if (!cpu_arch_tune_set) | |
13881 | { | |
13882 | cpu_arch_tune = cpu_arch_isa; | |
13883 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
13884 | } | |
13885 | } | |
8d471ec1 | 13886 | else if (cpu_arch_isa != PROCESSOR_IAMCU) |
5197d474 L |
13887 | as_fatal (_("Intel MCU doesn't support `%s' architecture"), |
13888 | cpu_arch_name); | |
13889 | } | |
3e73aa7c | 13890 | else |
2b5d6a91 | 13891 | as_fatal (_("unknown architecture")); |
89507696 JB |
13892 | |
13893 | if (cpu_flags_all_zero (&cpu_arch_isa_flags)) | |
13894 | cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
13895 | if (cpu_flags_all_zero (&cpu_arch_tune_flags)) | |
13896 | cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
13897 | ||
252b5132 RH |
13898 | switch (OUTPUT_FLAVOR) |
13899 | { | |
9384f2ff | 13900 | #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT) |
4c63da97 | 13901 | case bfd_target_aout_flavour: |
47926f60 | 13902 | return AOUT_TARGET_FORMAT; |
4c63da97 | 13903 | #endif |
9384f2ff AM |
13904 | #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF) |
13905 | # if defined (TE_PE) || defined (TE_PEP) | |
13906 | case bfd_target_coff_flavour: | |
167ad85b | 13907 | if (flag_code == CODE_64BIT) |
eb19308f JB |
13908 | { |
13909 | object_64bit = 1; | |
13910 | return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64"; | |
13911 | } | |
13912 | return use_big_obj ? "pe-bigobj-i386" : "pe-i386"; | |
9384f2ff | 13913 | # elif defined (TE_GO32) |
0561d57c JK |
13914 | case bfd_target_coff_flavour: |
13915 | return "coff-go32"; | |
9384f2ff | 13916 | # else |
252b5132 RH |
13917 | case bfd_target_coff_flavour: |
13918 | return "coff-i386"; | |
9384f2ff | 13919 | # endif |
4c63da97 | 13920 | #endif |
3e73aa7c | 13921 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 13922 | case bfd_target_elf_flavour: |
3e73aa7c | 13923 | { |
351f65ca L |
13924 | const char *format; |
13925 | ||
13926 | switch (x86_elf_abi) | |
4fa24527 | 13927 | { |
351f65ca L |
13928 | default: |
13929 | format = ELF_TARGET_FORMAT; | |
e379e5f3 L |
13930 | #ifndef TE_SOLARIS |
13931 | tls_get_addr = "___tls_get_addr"; | |
13932 | #endif | |
351f65ca | 13933 | break; |
7f56bc95 | 13934 | case X86_64_ABI: |
351f65ca | 13935 | use_rela_relocations = 1; |
4fa24527 | 13936 | object_64bit = 1; |
e379e5f3 L |
13937 | #ifndef TE_SOLARIS |
13938 | tls_get_addr = "__tls_get_addr"; | |
13939 | #endif | |
351f65ca L |
13940 | format = ELF_TARGET_FORMAT64; |
13941 | break; | |
7f56bc95 | 13942 | case X86_64_X32_ABI: |
4fa24527 | 13943 | use_rela_relocations = 1; |
351f65ca | 13944 | object_64bit = 1; |
e379e5f3 L |
13945 | #ifndef TE_SOLARIS |
13946 | tls_get_addr = "__tls_get_addr"; | |
13947 | #endif | |
862be3fb | 13948 | disallow_64bit_reloc = 1; |
351f65ca L |
13949 | format = ELF_TARGET_FORMAT32; |
13950 | break; | |
4fa24527 | 13951 | } |
3632d14b | 13952 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 13953 | { |
7f56bc95 | 13954 | if (x86_elf_abi != X86_64_ABI) |
8a9036a4 L |
13955 | as_fatal (_("Intel L1OM is 64bit only")); |
13956 | return ELF_TARGET_L1OM_FORMAT; | |
13957 | } | |
b49f93f6 | 13958 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
7a9068fe L |
13959 | { |
13960 | if (x86_elf_abi != X86_64_ABI) | |
13961 | as_fatal (_("Intel K1OM is 64bit only")); | |
13962 | return ELF_TARGET_K1OM_FORMAT; | |
13963 | } | |
81486035 L |
13964 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
13965 | { | |
13966 | if (x86_elf_abi != I386_ABI) | |
13967 | as_fatal (_("Intel MCU is 32bit only")); | |
13968 | return ELF_TARGET_IAMCU_FORMAT; | |
13969 | } | |
8a9036a4 | 13970 | else |
351f65ca | 13971 | return format; |
3e73aa7c | 13972 | } |
e57f8c65 TG |
13973 | #endif |
13974 | #if defined (OBJ_MACH_O) | |
13975 | case bfd_target_mach_o_flavour: | |
d382c579 TG |
13976 | if (flag_code == CODE_64BIT) |
13977 | { | |
13978 | use_rela_relocations = 1; | |
13979 | object_64bit = 1; | |
13980 | return "mach-o-x86-64"; | |
13981 | } | |
13982 | else | |
13983 | return "mach-o-i386"; | |
4c63da97 | 13984 | #endif |
252b5132 RH |
13985 | default: |
13986 | abort (); | |
13987 | return NULL; | |
13988 | } | |
13989 | } | |
13990 | ||
47926f60 | 13991 | #endif /* OBJ_MAYBE_ more than one */ |
252b5132 | 13992 | \f |
252b5132 | 13993 | symbolS * |
7016a5d5 | 13994 | md_undefined_symbol (char *name) |
252b5132 | 13995 | { |
18dc2407 ILT |
13996 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
13997 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
13998 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
13999 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
14000 | { |
14001 | if (!GOT_symbol) | |
14002 | { | |
14003 | if (symbol_find (name)) | |
14004 | as_bad (_("GOT already in symbol table")); | |
14005 | GOT_symbol = symbol_new (name, undefined_section, | |
e01e1cee | 14006 | &zero_address_frag, 0); |
24eab124 AM |
14007 | }; |
14008 | return GOT_symbol; | |
14009 | } | |
252b5132 RH |
14010 | return 0; |
14011 | } | |
14012 | ||
14013 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 14014 | |
252b5132 | 14015 | valueT |
7016a5d5 | 14016 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
252b5132 | 14017 | { |
4c63da97 AM |
14018 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
14019 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
14020 | { | |
14021 | /* For a.out, force the section size to be aligned. If we don't do | |
14022 | this, BFD will align it for us, but it will not write out the | |
14023 | final bytes of the section. This may be a bug in BFD, but it is | |
14024 | easier to fix it here since that is how the other a.out targets | |
14025 | work. */ | |
14026 | int align; | |
14027 | ||
fd361982 | 14028 | align = bfd_section_alignment (segment); |
8d3842cd | 14029 | size = ((size + (1 << align) - 1) & (-((valueT) 1 << align))); |
4c63da97 | 14030 | } |
252b5132 RH |
14031 | #endif |
14032 | ||
14033 | return size; | |
14034 | } | |
14035 | ||
14036 | /* On the i386, PC-relative offsets are relative to the start of the | |
14037 | next instruction. That is, the address of the offset, plus its | |
14038 | size, since the offset is always the last part of the insn. */ | |
14039 | ||
14040 | long | |
e3bb37b5 | 14041 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
14042 | { |
14043 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
14044 | } | |
14045 | ||
14046 | #ifndef I386COFF | |
14047 | ||
14048 | static void | |
e3bb37b5 | 14049 | s_bss (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 14050 | { |
29b0f896 | 14051 | int temp; |
252b5132 | 14052 | |
8a75718c JB |
14053 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
14054 | if (IS_ELF) | |
14055 | obj_elf_section_change_hook (); | |
14056 | #endif | |
252b5132 RH |
14057 | temp = get_absolute_expression (); |
14058 | subseg_set (bss_section, (subsegT) temp); | |
14059 | demand_empty_rest_of_line (); | |
14060 | } | |
14061 | ||
14062 | #endif | |
14063 | ||
e379e5f3 L |
14064 | /* Remember constant directive. */ |
14065 | ||
14066 | void | |
14067 | i386_cons_align (int ignore ATTRIBUTE_UNUSED) | |
14068 | { | |
14069 | if (last_insn.kind != last_insn_directive | |
14070 | && (bfd_section_flags (now_seg) & SEC_CODE)) | |
14071 | { | |
14072 | last_insn.seg = now_seg; | |
14073 | last_insn.kind = last_insn_directive; | |
14074 | last_insn.name = "constant directive"; | |
14075 | last_insn.file = as_where (&last_insn.line); | |
ae531041 L |
14076 | if (lfence_before_ret != lfence_before_ret_none) |
14077 | { | |
14078 | if (lfence_before_indirect_branch != lfence_branch_none) | |
14079 | as_warn (_("constant directive skips -mlfence-before-ret " | |
14080 | "and -mlfence-before-indirect-branch")); | |
14081 | else | |
14082 | as_warn (_("constant directive skips -mlfence-before-ret")); | |
14083 | } | |
14084 | else if (lfence_before_indirect_branch != lfence_branch_none) | |
14085 | as_warn (_("constant directive skips -mlfence-before-indirect-branch")); | |
e379e5f3 L |
14086 | } |
14087 | } | |
14088 | ||
3abbafc2 | 14089 | int |
e3bb37b5 | 14090 | i386_validate_fix (fixS *fixp) |
252b5132 | 14091 | { |
3abbafc2 JB |
14092 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
14093 | if (fixp->fx_r_type == BFD_RELOC_SIZE32 | |
14094 | || fixp->fx_r_type == BFD_RELOC_SIZE64) | |
14095 | return IS_ELF && fixp->fx_addsy | |
14096 | && (!S_IS_DEFINED (fixp->fx_addsy) | |
14097 | || S_IS_EXTERNAL (fixp->fx_addsy)); | |
14098 | #endif | |
14099 | ||
02a86693 | 14100 | if (fixp->fx_subsy) |
252b5132 | 14101 | { |
02a86693 | 14102 | if (fixp->fx_subsy == GOT_symbol) |
23df1078 | 14103 | { |
02a86693 L |
14104 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
14105 | { | |
14106 | if (!object_64bit) | |
14107 | abort (); | |
14108 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
14109 | if (fixp->fx_tcbit2) | |
56ceb5b5 L |
14110 | fixp->fx_r_type = (fixp->fx_tcbit |
14111 | ? BFD_RELOC_X86_64_REX_GOTPCRELX | |
14112 | : BFD_RELOC_X86_64_GOTPCRELX); | |
02a86693 L |
14113 | else |
14114 | #endif | |
14115 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
14116 | } | |
d6ab8113 | 14117 | else |
02a86693 L |
14118 | { |
14119 | if (!object_64bit) | |
14120 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
14121 | else | |
14122 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; | |
14123 | } | |
14124 | fixp->fx_subsy = 0; | |
23df1078 | 14125 | } |
252b5132 | 14126 | } |
02a86693 | 14127 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
2585b7a5 | 14128 | else |
02a86693 | 14129 | { |
2585b7a5 L |
14130 | /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol |
14131 | to section. Since PLT32 relocation must be against symbols, | |
14132 | turn such PLT32 relocation into PC32 relocation. */ | |
14133 | if (fixp->fx_addsy | |
14134 | && (fixp->fx_r_type == BFD_RELOC_386_PLT32 | |
14135 | || fixp->fx_r_type == BFD_RELOC_X86_64_PLT32) | |
14136 | && symbol_section_p (fixp->fx_addsy)) | |
14137 | fixp->fx_r_type = BFD_RELOC_32_PCREL; | |
14138 | if (!object_64bit) | |
14139 | { | |
14140 | if (fixp->fx_r_type == BFD_RELOC_386_GOT32 | |
14141 | && fixp->fx_tcbit2) | |
14142 | fixp->fx_r_type = BFD_RELOC_386_GOT32X; | |
14143 | } | |
02a86693 L |
14144 | } |
14145 | #endif | |
3abbafc2 JB |
14146 | |
14147 | return 1; | |
252b5132 RH |
14148 | } |
14149 | ||
252b5132 | 14150 | arelent * |
7016a5d5 | 14151 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
14152 | { |
14153 | arelent *rel; | |
14154 | bfd_reloc_code_real_type code; | |
14155 | ||
14156 | switch (fixp->fx_r_type) | |
14157 | { | |
8ce3d284 | 14158 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
3abbafc2 JB |
14159 | symbolS *sym; |
14160 | ||
8fd4256d L |
14161 | case BFD_RELOC_SIZE32: |
14162 | case BFD_RELOC_SIZE64: | |
3abbafc2 JB |
14163 | if (fixp->fx_addsy |
14164 | && !bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_addsy)) | |
14165 | && (!fixp->fx_subsy | |
14166 | || bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_subsy)))) | |
14167 | sym = fixp->fx_addsy; | |
14168 | else if (fixp->fx_subsy | |
14169 | && !bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_subsy)) | |
14170 | && (!fixp->fx_addsy | |
14171 | || bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_addsy)))) | |
14172 | sym = fixp->fx_subsy; | |
14173 | else | |
14174 | sym = NULL; | |
14175 | if (IS_ELF && sym && S_IS_DEFINED (sym) && !S_IS_EXTERNAL (sym)) | |
8fd4256d L |
14176 | { |
14177 | /* Resolve size relocation against local symbol to size of | |
14178 | the symbol plus addend. */ | |
3abbafc2 | 14179 | valueT value = S_GET_SIZE (sym); |
44f87162 | 14180 | |
3abbafc2 JB |
14181 | if (symbol_get_bfdsym (sym)->flags & BSF_SECTION_SYM) |
14182 | value = bfd_section_size (S_GET_SEGMENT (sym)); | |
14183 | if (sym == fixp->fx_subsy) | |
14184 | { | |
14185 | value = -value; | |
14186 | if (fixp->fx_addsy) | |
14187 | value += S_GET_VALUE (fixp->fx_addsy); | |
14188 | } | |
14189 | else if (fixp->fx_subsy) | |
14190 | value -= S_GET_VALUE (fixp->fx_subsy); | |
44f87162 | 14191 | value += fixp->fx_offset; |
8fd4256d | 14192 | if (fixp->fx_r_type == BFD_RELOC_SIZE32 |
d965814f | 14193 | && object_64bit |
8fd4256d L |
14194 | && !fits_in_unsigned_long (value)) |
14195 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
14196 | _("symbol size computation overflow")); | |
14197 | fixp->fx_addsy = NULL; | |
14198 | fixp->fx_subsy = NULL; | |
14199 | md_apply_fix (fixp, (valueT *) &value, NULL); | |
14200 | return NULL; | |
14201 | } | |
3abbafc2 JB |
14202 | if (!fixp->fx_addsy || fixp->fx_subsy) |
14203 | { | |
14204 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
14205 | "unsupported expression involving @size"); | |
14206 | return NULL; | |
14207 | } | |
8ce3d284 | 14208 | #endif |
1a0670f3 | 14209 | /* Fall through. */ |
8fd4256d | 14210 | |
3e73aa7c JH |
14211 | case BFD_RELOC_X86_64_PLT32: |
14212 | case BFD_RELOC_X86_64_GOT32: | |
14213 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
14214 | case BFD_RELOC_X86_64_GOTPCRELX: |
14215 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
252b5132 RH |
14216 | case BFD_RELOC_386_PLT32: |
14217 | case BFD_RELOC_386_GOT32: | |
02a86693 | 14218 | case BFD_RELOC_386_GOT32X: |
252b5132 RH |
14219 | case BFD_RELOC_386_GOTOFF: |
14220 | case BFD_RELOC_386_GOTPC: | |
13ae64f3 JJ |
14221 | case BFD_RELOC_386_TLS_GD: |
14222 | case BFD_RELOC_386_TLS_LDM: | |
14223 | case BFD_RELOC_386_TLS_LDO_32: | |
14224 | case BFD_RELOC_386_TLS_IE_32: | |
37e55690 JJ |
14225 | case BFD_RELOC_386_TLS_IE: |
14226 | case BFD_RELOC_386_TLS_GOTIE: | |
13ae64f3 JJ |
14227 | case BFD_RELOC_386_TLS_LE_32: |
14228 | case BFD_RELOC_386_TLS_LE: | |
67a4f2b7 AO |
14229 | case BFD_RELOC_386_TLS_GOTDESC: |
14230 | case BFD_RELOC_386_TLS_DESC_CALL: | |
bffbf940 JJ |
14231 | case BFD_RELOC_X86_64_TLSGD: |
14232 | case BFD_RELOC_X86_64_TLSLD: | |
14233 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 14234 | case BFD_RELOC_X86_64_DTPOFF64: |
bffbf940 JJ |
14235 | case BFD_RELOC_X86_64_GOTTPOFF: |
14236 | case BFD_RELOC_X86_64_TPOFF32: | |
d6ab8113 JB |
14237 | case BFD_RELOC_X86_64_TPOFF64: |
14238 | case BFD_RELOC_X86_64_GOTOFF64: | |
14239 | case BFD_RELOC_X86_64_GOTPC32: | |
7b81dfbb AJ |
14240 | case BFD_RELOC_X86_64_GOT64: |
14241 | case BFD_RELOC_X86_64_GOTPCREL64: | |
14242 | case BFD_RELOC_X86_64_GOTPC64: | |
14243 | case BFD_RELOC_X86_64_GOTPLT64: | |
14244 | case BFD_RELOC_X86_64_PLTOFF64: | |
67a4f2b7 AO |
14245 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
14246 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
252b5132 RH |
14247 | case BFD_RELOC_RVA: |
14248 | case BFD_RELOC_VTABLE_ENTRY: | |
14249 | case BFD_RELOC_VTABLE_INHERIT: | |
6482c264 NC |
14250 | #ifdef TE_PE |
14251 | case BFD_RELOC_32_SECREL: | |
14252 | #endif | |
252b5132 RH |
14253 | code = fixp->fx_r_type; |
14254 | break; | |
dbbaec26 L |
14255 | case BFD_RELOC_X86_64_32S: |
14256 | if (!fixp->fx_pcrel) | |
14257 | { | |
14258 | /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ | |
14259 | code = fixp->fx_r_type; | |
14260 | break; | |
14261 | } | |
1a0670f3 | 14262 | /* Fall through. */ |
252b5132 | 14263 | default: |
93382f6d | 14264 | if (fixp->fx_pcrel) |
252b5132 | 14265 | { |
93382f6d AM |
14266 | switch (fixp->fx_size) |
14267 | { | |
14268 | default: | |
b091f402 AM |
14269 | as_bad_where (fixp->fx_file, fixp->fx_line, |
14270 | _("can not do %d byte pc-relative relocation"), | |
14271 | fixp->fx_size); | |
93382f6d AM |
14272 | code = BFD_RELOC_32_PCREL; |
14273 | break; | |
14274 | case 1: code = BFD_RELOC_8_PCREL; break; | |
14275 | case 2: code = BFD_RELOC_16_PCREL; break; | |
d258b828 | 14276 | case 4: code = BFD_RELOC_32_PCREL; break; |
d6ab8113 JB |
14277 | #ifdef BFD64 |
14278 | case 8: code = BFD_RELOC_64_PCREL; break; | |
14279 | #endif | |
93382f6d AM |
14280 | } |
14281 | } | |
14282 | else | |
14283 | { | |
14284 | switch (fixp->fx_size) | |
14285 | { | |
14286 | default: | |
b091f402 AM |
14287 | as_bad_where (fixp->fx_file, fixp->fx_line, |
14288 | _("can not do %d byte relocation"), | |
14289 | fixp->fx_size); | |
93382f6d AM |
14290 | code = BFD_RELOC_32; |
14291 | break; | |
14292 | case 1: code = BFD_RELOC_8; break; | |
14293 | case 2: code = BFD_RELOC_16; break; | |
14294 | case 4: code = BFD_RELOC_32; break; | |
937149dd | 14295 | #ifdef BFD64 |
3e73aa7c | 14296 | case 8: code = BFD_RELOC_64; break; |
937149dd | 14297 | #endif |
93382f6d | 14298 | } |
252b5132 RH |
14299 | } |
14300 | break; | |
14301 | } | |
252b5132 | 14302 | |
d182319b JB |
14303 | if ((code == BFD_RELOC_32 |
14304 | || code == BFD_RELOC_32_PCREL | |
14305 | || code == BFD_RELOC_X86_64_32S) | |
252b5132 RH |
14306 | && GOT_symbol |
14307 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c | 14308 | { |
4fa24527 | 14309 | if (!object_64bit) |
d6ab8113 JB |
14310 | code = BFD_RELOC_386_GOTPC; |
14311 | else | |
14312 | code = BFD_RELOC_X86_64_GOTPC32; | |
3e73aa7c | 14313 | } |
7b81dfbb AJ |
14314 | if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) |
14315 | && GOT_symbol | |
14316 | && fixp->fx_addsy == GOT_symbol) | |
14317 | { | |
14318 | code = BFD_RELOC_X86_64_GOTPC64; | |
14319 | } | |
252b5132 | 14320 | |
add39d23 TS |
14321 | rel = XNEW (arelent); |
14322 | rel->sym_ptr_ptr = XNEW (asymbol *); | |
49309057 | 14323 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
14324 | |
14325 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
c87db184 | 14326 | |
3e73aa7c JH |
14327 | if (!use_rela_relocations) |
14328 | { | |
14329 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
14330 | vtable entry to be used in the relocation's section offset. */ | |
14331 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
14332 | rel->address = fixp->fx_offset; | |
fbeb56a4 DK |
14333 | #if defined (OBJ_COFF) && defined (TE_PE) |
14334 | else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy)) | |
14335 | rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2); | |
14336 | else | |
14337 | #endif | |
c6682705 | 14338 | rel->addend = 0; |
3e73aa7c JH |
14339 | } |
14340 | /* Use the rela in 64bit mode. */ | |
252b5132 | 14341 | else |
3e73aa7c | 14342 | { |
862be3fb L |
14343 | if (disallow_64bit_reloc) |
14344 | switch (code) | |
14345 | { | |
862be3fb L |
14346 | case BFD_RELOC_X86_64_DTPOFF64: |
14347 | case BFD_RELOC_X86_64_TPOFF64: | |
14348 | case BFD_RELOC_64_PCREL: | |
14349 | case BFD_RELOC_X86_64_GOTOFF64: | |
14350 | case BFD_RELOC_X86_64_GOT64: | |
14351 | case BFD_RELOC_X86_64_GOTPCREL64: | |
14352 | case BFD_RELOC_X86_64_GOTPC64: | |
14353 | case BFD_RELOC_X86_64_GOTPLT64: | |
14354 | case BFD_RELOC_X86_64_PLTOFF64: | |
14355 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
14356 | _("cannot represent relocation type %s in x32 mode"), | |
14357 | bfd_get_reloc_code_name (code)); | |
14358 | break; | |
14359 | default: | |
14360 | break; | |
14361 | } | |
14362 | ||
062cd5e7 AS |
14363 | if (!fixp->fx_pcrel) |
14364 | rel->addend = fixp->fx_offset; | |
14365 | else | |
14366 | switch (code) | |
14367 | { | |
14368 | case BFD_RELOC_X86_64_PLT32: | |
14369 | case BFD_RELOC_X86_64_GOT32: | |
14370 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
14371 | case BFD_RELOC_X86_64_GOTPCRELX: |
14372 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
bffbf940 JJ |
14373 | case BFD_RELOC_X86_64_TLSGD: |
14374 | case BFD_RELOC_X86_64_TLSLD: | |
14375 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 AO |
14376 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
14377 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
062cd5e7 AS |
14378 | rel->addend = fixp->fx_offset - fixp->fx_size; |
14379 | break; | |
14380 | default: | |
14381 | rel->addend = (section->vma | |
14382 | - fixp->fx_size | |
14383 | + fixp->fx_addnumber | |
14384 | + md_pcrel_from (fixp)); | |
14385 | break; | |
14386 | } | |
3e73aa7c JH |
14387 | } |
14388 | ||
252b5132 RH |
14389 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
14390 | if (rel->howto == NULL) | |
14391 | { | |
14392 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 14393 | _("cannot represent relocation type %s"), |
252b5132 RH |
14394 | bfd_get_reloc_code_name (code)); |
14395 | /* Set howto to a garbage value so that we can keep going. */ | |
14396 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
9c2799c2 | 14397 | gas_assert (rel->howto != NULL); |
252b5132 RH |
14398 | } |
14399 | ||
14400 | return rel; | |
14401 | } | |
14402 | ||
ee86248c | 14403 | #include "tc-i386-intel.c" |
54cfded0 | 14404 | |
a60de03c JB |
14405 | void |
14406 | tc_x86_parse_to_dw2regnum (expressionS *exp) | |
54cfded0 | 14407 | { |
a60de03c JB |
14408 | int saved_naked_reg; |
14409 | char saved_register_dot; | |
54cfded0 | 14410 | |
a60de03c JB |
14411 | saved_naked_reg = allow_naked_reg; |
14412 | allow_naked_reg = 1; | |
14413 | saved_register_dot = register_chars['.']; | |
14414 | register_chars['.'] = '.'; | |
14415 | allow_pseudo_reg = 1; | |
14416 | expression_and_evaluate (exp); | |
14417 | allow_pseudo_reg = 0; | |
14418 | register_chars['.'] = saved_register_dot; | |
14419 | allow_naked_reg = saved_naked_reg; | |
14420 | ||
e96d56a1 | 14421 | if (exp->X_op == O_register && exp->X_add_number >= 0) |
54cfded0 | 14422 | { |
a60de03c JB |
14423 | if ((addressT) exp->X_add_number < i386_regtab_size) |
14424 | { | |
14425 | exp->X_op = O_constant; | |
14426 | exp->X_add_number = i386_regtab[exp->X_add_number] | |
14427 | .dw2_regnum[flag_code >> 1]; | |
14428 | } | |
14429 | else | |
14430 | exp->X_op = O_illegal; | |
54cfded0 | 14431 | } |
54cfded0 AM |
14432 | } |
14433 | ||
14434 | void | |
14435 | tc_x86_frame_initial_instructions (void) | |
14436 | { | |
a60de03c JB |
14437 | static unsigned int sp_regno[2]; |
14438 | ||
14439 | if (!sp_regno[flag_code >> 1]) | |
14440 | { | |
14441 | char *saved_input = input_line_pointer; | |
14442 | char sp[][4] = {"esp", "rsp"}; | |
14443 | expressionS exp; | |
a4447b93 | 14444 | |
a60de03c JB |
14445 | input_line_pointer = sp[flag_code >> 1]; |
14446 | tc_x86_parse_to_dw2regnum (&exp); | |
9c2799c2 | 14447 | gas_assert (exp.X_op == O_constant); |
a60de03c JB |
14448 | sp_regno[flag_code >> 1] = exp.X_add_number; |
14449 | input_line_pointer = saved_input; | |
14450 | } | |
a4447b93 | 14451 | |
61ff971f L |
14452 | cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment); |
14453 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); | |
54cfded0 | 14454 | } |
d2b2c203 | 14455 | |
d7921315 L |
14456 | int |
14457 | x86_dwarf2_addr_size (void) | |
14458 | { | |
14459 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) | |
14460 | if (x86_elf_abi == X86_64_X32_ABI) | |
14461 | return 4; | |
14462 | #endif | |
14463 | return bfd_arch_bits_per_address (stdoutput) / 8; | |
14464 | } | |
14465 | ||
d2b2c203 DJ |
14466 | int |
14467 | i386_elf_section_type (const char *str, size_t len) | |
14468 | { | |
14469 | if (flag_code == CODE_64BIT | |
14470 | && len == sizeof ("unwind") - 1 | |
d34049e8 | 14471 | && startswith (str, "unwind")) |
d2b2c203 DJ |
14472 | return SHT_X86_64_UNWIND; |
14473 | ||
14474 | return -1; | |
14475 | } | |
bb41ade5 | 14476 | |
ad5fec3b EB |
14477 | #ifdef TE_SOLARIS |
14478 | void | |
14479 | i386_solaris_fix_up_eh_frame (segT sec) | |
14480 | { | |
14481 | if (flag_code == CODE_64BIT) | |
14482 | elf_section_type (sec) = SHT_X86_64_UNWIND; | |
14483 | } | |
14484 | #endif | |
14485 | ||
bb41ade5 AM |
14486 | #ifdef TE_PE |
14487 | void | |
14488 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) | |
14489 | { | |
91d6fa6a | 14490 | expressionS exp; |
bb41ade5 | 14491 | |
91d6fa6a NC |
14492 | exp.X_op = O_secrel; |
14493 | exp.X_add_symbol = symbol; | |
14494 | exp.X_add_number = 0; | |
14495 | emit_expr (&exp, size); | |
bb41ade5 AM |
14496 | } |
14497 | #endif | |
3b22753a L |
14498 | |
14499 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
14500 | /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ | |
14501 | ||
01e1a5bc | 14502 | bfd_vma |
6d4af3c2 | 14503 | x86_64_section_letter (int letter, const char **ptr_msg) |
3b22753a L |
14504 | { |
14505 | if (flag_code == CODE_64BIT) | |
14506 | { | |
14507 | if (letter == 'l') | |
14508 | return SHF_X86_64_LARGE; | |
14509 | ||
8f3bae45 | 14510 | *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string"); |
64e74474 | 14511 | } |
3b22753a | 14512 | else |
8f3bae45 | 14513 | *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string"); |
3b22753a L |
14514 | return -1; |
14515 | } | |
14516 | ||
01e1a5bc | 14517 | bfd_vma |
3b22753a L |
14518 | x86_64_section_word (char *str, size_t len) |
14519 | { | |
08dedd66 | 14520 | if (len == 5 && flag_code == CODE_64BIT && startswith (str, "large")) |
3b22753a L |
14521 | return SHF_X86_64_LARGE; |
14522 | ||
14523 | return -1; | |
14524 | } | |
14525 | ||
14526 | static void | |
14527 | handle_large_common (int small ATTRIBUTE_UNUSED) | |
14528 | { | |
14529 | if (flag_code != CODE_64BIT) | |
14530 | { | |
14531 | s_comm_internal (0, elf_common_parse); | |
14532 | as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); | |
14533 | } | |
14534 | else | |
14535 | { | |
14536 | static segT lbss_section; | |
14537 | asection *saved_com_section_ptr = elf_com_section_ptr; | |
14538 | asection *saved_bss_section = bss_section; | |
14539 | ||
14540 | if (lbss_section == NULL) | |
14541 | { | |
14542 | flagword applicable; | |
14543 | segT seg = now_seg; | |
14544 | subsegT subseg = now_subseg; | |
14545 | ||
14546 | /* The .lbss section is for local .largecomm symbols. */ | |
14547 | lbss_section = subseg_new (".lbss", 0); | |
14548 | applicable = bfd_applicable_section_flags (stdoutput); | |
fd361982 | 14549 | bfd_set_section_flags (lbss_section, applicable & SEC_ALLOC); |
3b22753a L |
14550 | seg_info (lbss_section)->bss = 1; |
14551 | ||
14552 | subseg_set (seg, subseg); | |
14553 | } | |
14554 | ||
14555 | elf_com_section_ptr = &_bfd_elf_large_com_section; | |
14556 | bss_section = lbss_section; | |
14557 | ||
14558 | s_comm_internal (0, elf_common_parse); | |
14559 | ||
14560 | elf_com_section_ptr = saved_com_section_ptr; | |
14561 | bss_section = saved_bss_section; | |
14562 | } | |
14563 | } | |
14564 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |