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Fix gdb.opt/inline-cmds.exp regressions
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
2571583a 2 Copyright (C) 1989-2017 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d 68#define LOCK_PREFIX 5
4e9ac44a
L		 69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 86#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 87/* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89#define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91#define END_OF_INSN '\0'
92
93/*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100typedef struct
101{
d3ce72d0
NC		 102 const insn_template *start;
103 const insn_template *end;
6305a203
L		 104}
105templates;
106
107/* 386 operand encoding bytes: see 386 book for details of this. */
108typedef struct
109{
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113}
114modrm_byte;
115
116/* x86-64 extension prefix. */
117typedef int rex_byte;
118
6305a203
L		 119/* 386 opcode byte to code indirect addressing. */
120typedef struct
121{
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125}
126sib_byte;
127
6305a203
L		 128/* x86 arch names, types and features */
129typedef struct
130{
131 const char *name; /* arch name */
8a2c8fef 132 unsigned int len; /* arch string length */
6305a203
L		 133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 135 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 136}
137arch_entry;
138
293f5f65
L		 139/* Used to turn off indicated flags. */
140typedef struct
141{
142 const char *name; /* arch name */
143 unsigned int len; /* arch string length */
144 i386_cpu_flags flags; /* cpu feature flags */
145}
146noarch_entry;
147
78f12dd3 148static void update_code_flag (int, int);
e3bb37b5
L		 149static void set_code_flag (int);
150static void set_16bit_gcc_code_flag (int);
151static void set_intel_syntax (int);
1efbbeb4 152static void set_intel_mnemonic (int);
db51cc60 153static void set_allow_index_reg (int);
7bab8ab5 154static void set_check (int);
e3bb37b5 155static void set_cpu_arch (int);
6482c264 156#ifdef TE_PE
e3bb37b5 157static void pe_directive_secrel (int);
6482c264 158#endif
e3bb37b5
L		 159static void signed_cons (int);
160static char *output_invalid (int c);
ee86248c
JB		 161static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
162 const char *);
163static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
164 const char *);
a7619375 165static int i386_att_operand (char *);
e3bb37b5 166static int i386_intel_operand (char *, int);
ee86248c
JB		 167static int i386_intel_simplify (expressionS *);
168static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 169static const reg_entry *parse_register (char *, char **);
170static char *parse_insn (char *, char *);
171static char *parse_operands (char *, const char *);
172static void swap_operands (void);
4d456e3d 173static void swap_2_operands (int, int);
e3bb37b5
L		 174static void optimize_imm (void);
175static void optimize_disp (void);
83b16ac6 176static const insn_template *match_template (char);
e3bb37b5
L		 177static int check_string (void);
178static int process_suffix (void);
179static int check_byte_reg (void);
180static int check_long_reg (void);
181static int check_qword_reg (void);
182static int check_word_reg (void);
183static int finalize_imm (void);
184static int process_operands (void);
185static const seg_entry *build_modrm_byte (void);
186static void output_insn (void);
187static void output_imm (fragS *, offsetT);
188static void output_disp (fragS *, offsetT);
29b0f896 189#ifndef I386COFF
e3bb37b5 190static void s_bss (int);
252b5132 191#endif
17d4e2a2
L		 192#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193static void handle_large_common (int small ATTRIBUTE_UNUSED);
194#endif
252b5132 195
a847613f 196static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 197
43234a1e
L		 198/* This struct describes rounding control and SAE in the instruction. */
199struct RC_Operation
200{
201 enum rc_type
202 {
203 rne = 0,
204 rd,
205 ru,
206 rz,
207 saeonly
208 } type;
209 int operand;
210};
211
212static struct RC_Operation rc_op;
213
214/* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217struct Mask_Operation
218{
219 const reg_entry *mask;
220 unsigned int zeroing;
221 /* The operand where this operation is associated. */
222 int operand;
223};
224
225static struct Mask_Operation mask_op;
226
227/* The struct describes broadcasting, applied to OPERAND. FACTOR is
228 broadcast factor. */
229struct Broadcast_Operation
230{
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
232 int type;
233
234 /* Index of broadcasted operand. */
235 int operand;
236};
237
238static struct Broadcast_Operation broadcast_op;
239
c0f3af97
L		 240/* VEX prefix. */
241typedef struct
242{
43234a1e
L		 243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes[4];
c0f3af97
L		 245 unsigned int length;
246 /* Destination or source register specifier. */
247 const reg_entry *register_specifier;
248} vex_prefix;
249
252b5132 250/* 'md_assemble ()' gathers together information and puts it into a
47926f60 251 i386_insn. */
252b5132 252
520dc8e8
AM		 253union i386_op
254 {
255 expressionS *disps;
256 expressionS *imms;
257 const reg_entry *regs;
258 };
259
a65babc9
L		 260enum i386_error
261 {
86e026a4 262 operand_size_mismatch,
a65babc9
L		 263 operand_type_mismatch,
264 register_type_mismatch,
265 number_of_operands_mismatch,
266 invalid_instruction_suffix,
267 bad_imm4,
268 old_gcc_only,
269 unsupported_with_intel_mnemonic,
270 unsupported_syntax,
6c30d220
L		 271 unsupported,
272 invalid_vsib_address,
7bab8ab5 273 invalid_vector_register_set,
43234a1e
L		 274 unsupported_vector_index_register,
275 unsupported_broadcast,
276 broadcast_not_on_src_operand,
277 broadcast_needed,
278 unsupported_masking,
279 mask_not_on_destination,
280 no_default_mask,
281 unsupported_rc_sae,
282 rc_sae_operand_not_last_imm,
283 invalid_register_operand,
284 try_vector_disp8
a65babc9
L		 285 };
286
252b5132
RH		 287struct _i386_insn
288 {
47926f60 289 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 290 insn_template tm;
252b5132 291
7d5e4556
L		 292 /* SUFFIX holds the instruction size suffix for byte, word, dword
293 or qword, if given. */
252b5132
RH		 294 char suffix;
295
47926f60 296 /* OPERANDS gives the number of given operands. */
252b5132
RH		 297 unsigned int operands;
298
299 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
300 of given register, displacement, memory operands and immediate
47926f60 301 operands. */
252b5132
RH		 302 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
303
304 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 305 use OP[i] for the corresponding operand. */
40fb9820 306 i386_operand_type types[MAX_OPERANDS];
252b5132 307
520dc8e8
AM		 308 /* Displacement expression, immediate expression, or register for each
309 operand. */
310 union i386_op op[MAX_OPERANDS];
252b5132 311
3e73aa7c
JH		 312 /* Flags for operands. */
313 unsigned int flags[MAX_OPERANDS];
314#define Operand_PCrel 1
315
252b5132 316 /* Relocation type for operand */
f86103b7 317 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 318
252b5132
RH		 319 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
320 the base index byte below. */
321 const reg_entry *base_reg;
322 const reg_entry *index_reg;
323 unsigned int log2_scale_factor;
324
325 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 326 explicit segment overrides are given. */
ce8a8b2f 327 const seg_entry *seg[2];
252b5132 328
8325cc63
JB		 329 /* Copied first memory operand string, for re-checking. */
330 char *memop1_string;
331
252b5132
RH		 332 /* PREFIX holds all the given prefix opcodes (usually null).
333 PREFIXES is the number of prefix opcodes. */
334 unsigned int prefixes;
335 unsigned char prefix[MAX_PREFIXES];
336
337 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 338 addressing modes of this insn are encoded. */
252b5132 339 modrm_byte rm;
3e73aa7c 340 rex_byte rex;
43234a1e 341 rex_byte vrex;
252b5132 342 sib_byte sib;
c0f3af97 343 vex_prefix vex;
b6169b20 344
43234a1e
L		 345 /* Masking attributes. */
346 struct Mask_Operation *mask;
347
348 /* Rounding control and SAE attributes. */
349 struct RC_Operation *rounding;
350
351 /* Broadcasting attributes. */
352 struct Broadcast_Operation *broadcast;
353
354 /* Compressed disp8*N attribute. */
355 unsigned int memshift;
356
86fa6981
L		 357 /* Prefer load or store in encoding. */
358 enum
359 {
360 dir_encoding_default = 0,
361 dir_encoding_load,
362 dir_encoding_store
363 } dir_encoding;
891edac4 364
a501d77e
L		 365 /* Prefer 8bit or 32bit displacement in encoding. */
366 enum
367 {
368 disp_encoding_default = 0,
369 disp_encoding_8bit,
370 disp_encoding_32bit
371 } disp_encoding;
f8a5c266 372
86fa6981
L		 373 /* How to encode vector instructions. */
374 enum
375 {
376 vex_encoding_default = 0,
377 vex_encoding_vex2,
378 vex_encoding_vex3,
379 vex_encoding_evex
380 } vec_encoding;
381
d5de92cf
L		 382 /* REP prefix. */
383 const char *rep_prefix;
384
165de32a
L		 385 /* HLE prefix. */
386 const char *hle_prefix;
42164a71 387
7e8b059b
L		 388 /* Have BND prefix. */
389 const char *bnd_prefix;
390
04ef582a
L		 391 /* Have NOTRACK prefix. */
392 const char *notrack_prefix;
393
891edac4 394 /* Error message. */
a65babc9 395 enum i386_error error;
252b5132
RH		 396 };
397
398typedef struct _i386_insn i386_insn;
399
43234a1e
L		 400/* Link RC type with corresponding string, that'll be looked for in
401 asm. */
402struct RC_name
403{
404 enum rc_type type;
405 const char *name;
406 unsigned int len;
407};
408
409static const struct RC_name RC_NamesTable[] =
410{
411 { rne, STRING_COMMA_LEN ("rn-sae") },
412 { rd, STRING_COMMA_LEN ("rd-sae") },
413 { ru, STRING_COMMA_LEN ("ru-sae") },
414 { rz, STRING_COMMA_LEN ("rz-sae") },
415 { saeonly, STRING_COMMA_LEN ("sae") },
416};
417
252b5132
RH		 418/* List of chars besides those in app.c:symbol_chars that can start an
419 operand. Used to prevent the scrubber eating vital white-space. */
86fa6981 420const char extra_symbol_chars[] = "*%-([{}"
252b5132 421#ifdef LEX_AT
32137342
NC		 422 "@"
423#endif
424#ifdef LEX_QM
425 "?"
252b5132 426#endif
32137342 427 ;
252b5132 428
29b0f896
AM		 429#if (defined (TE_I386AIX) \
430 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 431 && !defined (TE_GNU) \
29b0f896 432 && !defined (TE_LINUX) \
8d63c93e
RM		 433 && !defined (TE_NACL) \
434 && !defined (TE_NETWARE) \
29b0f896 435 && !defined (TE_FreeBSD) \
5b806d27 436 && !defined (TE_DragonFly) \
29b0f896 437 && !defined (TE_NetBSD)))
252b5132 438/* This array holds the chars that always start a comment. If the
b3b91714
AM		 439 pre-processor is disabled, these aren't very useful. The option
440 --divide will remove '/' from this list. */
441const char *i386_comment_chars = "#/";
442#define SVR4_COMMENT_CHARS 1
252b5132 443#define PREFIX_SEPARATOR '\\'
252b5132 444
b3b91714
AM		 445#else
446const char *i386_comment_chars = "#";
447#define PREFIX_SEPARATOR '/'
448#endif
449
252b5132
RH		 450/* This array holds the chars that only start a comment at the beginning of
451 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 452 .line and .file directives will appear in the pre-processed output.
453 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 454 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 455 #NO_APP at the beginning of its output.
456 Also note that comments started like this one will always work if
252b5132 457 '/' isn't otherwise defined. */
b3b91714 458const char line_comment_chars[] = "#/";
252b5132 459
63a0b638 460const char line_separator_chars[] = ";";
252b5132 461
ce8a8b2f
AM		 462/* Chars that can be used to separate mant from exp in floating point
463 nums. */
252b5132
RH		 464const char EXP_CHARS[] = "eE";
465
ce8a8b2f
AM		 466/* Chars that mean this number is a floating point constant
467 As in 0f12.456
468 or 0d1.2345e12. */
252b5132
RH		 469const char FLT_CHARS[] = "fFdDxX";
470
ce8a8b2f 471/* Tables for lexical analysis. */
252b5132
RH		 472static char mnemonic_chars[256];
473static char register_chars[256];
474static char operand_chars[256];
475static char identifier_chars[256];
476static char digit_chars[256];
477
ce8a8b2f 478/* Lexical macros. */
252b5132
RH		 479#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
480#define is_operand_char(x) (operand_chars[(unsigned char) x])
481#define is_register_char(x) (register_chars[(unsigned char) x])
482#define is_space_char(x) ((x) == ' ')
483#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
484#define is_digit_char(x) (digit_chars[(unsigned char) x])
485
0234cb7c 486/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 487static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
488
489/* md_assemble() always leaves the strings it's passed unaltered. To
490 effect this we maintain a stack of saved characters that we've smashed
491 with '\0's (indicating end of strings for various sub-fields of the
47926f60 492 assembler instruction). */
252b5132 493static char save_stack[32];
ce8a8b2f 494static char *save_stack_p;
252b5132
RH		 495#define END_STRING_AND_SAVE(s) \
496 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
497#define RESTORE_END_STRING(s) \
498 do { *(s) = *--save_stack_p; } while (0)
499
47926f60 500/* The instruction we're assembling. */
252b5132
RH		 501static i386_insn i;
502
503/* Possible templates for current insn. */
504static const templates *current_templates;
505
31b2323c
L		 506/* Per instruction expressionS buffers: max displacements & immediates. */
507static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
508static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 509
47926f60 510/* Current operand we are working on. */
ee86248c 511static int this_operand = -1;
252b5132 512
3e73aa7c
JH		 513/* We support four different modes. FLAG_CODE variable is used to distinguish
514 these. */
515
516enum flag_code {
517 CODE_32BIT,
518 CODE_16BIT,
519 CODE_64BIT };
520
521static enum flag_code flag_code;
4fa24527 522static unsigned int object_64bit;
862be3fb 523static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 524static int use_rela_relocations = 0;
525
7af8ed2d
NC		 526#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
527 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
528 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
529
351f65ca
L		 530/* The ELF ABI to use. */
531enum x86_elf_abi
532{
533 I386_ABI,
7f56bc95
L		 534 X86_64_ABI,
535 X86_64_X32_ABI
351f65ca
L		 536};
537
538static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 539#endif
351f65ca 540
167ad85b
TG		 541#if defined (TE_PE) || defined (TE_PEP)
542/* Use big object file format. */
543static int use_big_obj = 0;
544#endif
545
8dcea932
L		 546#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547/* 1 if generating code for a shared library. */
548static int shared = 0;
549#endif
550
47926f60
KH		 551/* 1 for intel syntax,
552 0 if att syntax. */
553static int intel_syntax = 0;
252b5132 554
e89c5eaa
L		 555/* 1 for Intel64 ISA,
556 0 if AMD64 ISA. */
557static int intel64;
558
1efbbeb4
L		 559/* 1 for intel mnemonic,
560 0 if att mnemonic. */
561static int intel_mnemonic = !SYSV386_COMPAT;
562
5209009a 563/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 564static int old_gcc = OLDGCC_COMPAT;
565
a60de03c
JB		 566/* 1 if pseudo registers are permitted. */
567static int allow_pseudo_reg = 0;
568
47926f60
KH		 569/* 1 if register prefix % not required. */
570static int allow_naked_reg = 0;
252b5132 571
33eaf5de 572/* 1 if the assembler should add BND prefix for all control-transferring
7e8b059b
L		 573 instructions supporting it, even if this prefix wasn't specified
574 explicitly. */
575static int add_bnd_prefix = 0;
576
ba104c83 577/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 578static int allow_index_reg = 0;
579
d022bddd
IT		 580/* 1 if the assembler should ignore LOCK prefix, even if it was
581 specified explicitly. */
582static int omit_lock_prefix = 0;
583
e4e00185
AS		 584/* 1 if the assembler should encode lfence, mfence, and sfence as
585 "lock addl $0, (%{re}sp)". */
586static int avoid_fence = 0;
587
0cb4071e
L		 588/* 1 if the assembler should generate relax relocations. */
589
590static int generate_relax_relocations
591 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
592
7bab8ab5 593static enum check_kind
daf50ae7 594 {
7bab8ab5
JB		 595 check_none = 0,
596 check_warning,
597 check_error
daf50ae7 598 }
7bab8ab5 599sse_check, operand_check = check_warning;
daf50ae7 600
2ca3ace5
L		 601/* Register prefix used for error message. */
602static const char *register_prefix = "%";
603
47926f60
KH		 604/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
605 leave, push, and pop instructions so that gcc has the same stack
606 frame as in 32 bit mode. */
607static char stackop_size = '\0';
eecb386c 608
12b55ccc
L		 609/* Non-zero to optimize code alignment. */
610int optimize_align_code = 1;
611
47926f60
KH		 612/* Non-zero to quieten some warnings. */
613static int quiet_warnings = 0;
a38cf1db 614
47926f60
KH		 615/* CPU name. */
616static const char *cpu_arch_name = NULL;
6305a203 617static char *cpu_sub_arch_name = NULL;
a38cf1db 618
47926f60 619/* CPU feature flags. */
40fb9820
L		 620static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
621
ccc9c027
L		 622/* If we have selected a cpu we are generating instructions for. */
623static int cpu_arch_tune_set = 0;
624
9103f4f4 625/* Cpu we are generating instructions for. */
fbf3f584 626enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 627
628/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 629static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 630
ccc9c027 631/* CPU instruction set architecture used. */
fbf3f584 632enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 633
9103f4f4 634/* CPU feature flags of instruction set architecture used. */
fbf3f584 635i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 636
fddf5b5b
AM		 637/* If set, conditional jumps are not automatically promoted to handle
638 larger than a byte offset. */
639static unsigned int no_cond_jump_promotion = 0;
640
c0f3af97
L		 641/* Encode SSE instructions with VEX prefix. */
642static unsigned int sse2avx;
643
539f890d
L		 644/* Encode scalar AVX instructions with specific vector length. */
645static enum
646 {
647 vex128 = 0,
648 vex256
649 } avxscalar;
650
43234a1e
L		 651/* Encode scalar EVEX LIG instructions with specific vector length. */
652static enum
653 {
654 evexl128 = 0,
655 evexl256,
656 evexl512
657 } evexlig;
658
659/* Encode EVEX WIG instructions with specific evex.w. */
660static enum
661 {
662 evexw0 = 0,
663 evexw1
664 } evexwig;
665
d3d3c6db
IT		 666/* Value to encode in EVEX RC bits, for SAE-only instructions. */
667static enum rc_type evexrcig = rne;
668
29b0f896 669/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 670static symbolS *GOT_symbol;
29b0f896 671
a4447b93
RH		 672/* The dwarf2 return column, adjusted for 32 or 64 bit. */
673unsigned int x86_dwarf2_return_column;
674
675/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
676int x86_cie_data_alignment;
677
252b5132 678/* Interface to relax_segment.
fddf5b5b
AM		 679 There are 3 major relax states for 386 jump insns because the
680 different types of jumps add different sizes to frags when we're
681 figuring out what sort of jump to choose to reach a given label. */
252b5132 682
47926f60 683/* Types. */
93c2a809
AM		 684#define UNCOND_JUMP 0
685#define COND_JUMP 1
686#define COND_JUMP86 2
fddf5b5b 687
47926f60 688/* Sizes. */
252b5132
RH		 689#define CODE16 1
690#define SMALL 0
29b0f896 691#define SMALL16 (SMALL | CODE16)
252b5132 692#define BIG 2
29b0f896 693#define BIG16 (BIG | CODE16)
252b5132
RH		 694
695#ifndef INLINE
696#ifdef __GNUC__
697#define INLINE __inline__
698#else
699#define INLINE
700#endif
701#endif
702
fddf5b5b
AM		 703#define ENCODE_RELAX_STATE(type, size) \
704 ((relax_substateT) (((type) << 2) | (size)))
705#define TYPE_FROM_RELAX_STATE(s) \
706 ((s) >> 2)
707#define DISP_SIZE_FROM_RELAX_STATE(s) \
708 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 709
710/* This table is used by relax_frag to promote short jumps to long
711 ones where necessary. SMALL (short) jumps may be promoted to BIG
712 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
713 don't allow a short jump in a 32 bit code segment to be promoted to
714 a 16 bit offset jump because it's slower (requires data size
715 prefix), and doesn't work, unless the destination is in the bottom
716 64k of the code segment (The top 16 bits of eip are zeroed). */
717
718const relax_typeS md_relax_table[] =
719{
24eab124
AM		 720 /* The fields are:
721 1) most positive reach of this state,
722 2) most negative reach of this state,
93c2a809 723 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 724 4) which index into the table to try if we can't fit into this one. */
252b5132 725
fddf5b5b 726 /* UNCOND_JUMP states. */
93c2a809
AM		 727 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
728 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
729 /* dword jmp adds 4 bytes to frag:
730 0 extra opcode bytes, 4 displacement bytes. */
252b5132 731 {0, 0, 4, 0},
93c2a809
AM		 732 /* word jmp adds 2 byte2 to frag:
733 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 734 {0, 0, 2, 0},
735
93c2a809
AM		 736 /* COND_JUMP states. */
737 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
738 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
739 /* dword conditionals adds 5 bytes to frag:
740 1 extra opcode byte, 4 displacement bytes. */
741 {0, 0, 5, 0},
fddf5b5b 742 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 743 1 extra opcode byte, 2 displacement bytes. */
744 {0, 0, 3, 0},
745
746 /* COND_JUMP86 states. */
747 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
748 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
749 /* dword conditionals adds 5 bytes to frag:
750 1 extra opcode byte, 4 displacement bytes. */
751 {0, 0, 5, 0},
752 /* word conditionals add 4 bytes to frag:
753 1 displacement byte and a 3 byte long branch insn. */
754 {0, 0, 4, 0}
252b5132
RH		 755};
756
9103f4f4
L		 757static const arch_entry cpu_arch[] =
758{
89507696
JB		 759 /* Do not replace the first two entries - i386_target_format()
760 relies on them being there in this order. */
8a2c8fef 761 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
293f5f65 762 CPU_GENERIC32_FLAGS, 0 },
8a2c8fef 763 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
293f5f65 764 CPU_GENERIC64_FLAGS, 0 },
8a2c8fef 765 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
293f5f65 766 CPU_NONE_FLAGS, 0 },
8a2c8fef 767 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
293f5f65 768 CPU_I186_FLAGS, 0 },
8a2c8fef 769 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
293f5f65 770 CPU_I286_FLAGS, 0 },
8a2c8fef 771 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
293f5f65 772 CPU_I386_FLAGS, 0 },
8a2c8fef 773 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
293f5f65 774 CPU_I486_FLAGS, 0 },
8a2c8fef 775 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
293f5f65 776 CPU_I586_FLAGS, 0 },
8a2c8fef 777 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
293f5f65 778 CPU_I686_FLAGS, 0 },
8a2c8fef 779 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
293f5f65 780 CPU_I586_FLAGS, 0 },
8a2c8fef 781 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
293f5f65 782 CPU_PENTIUMPRO_FLAGS, 0 },
8a2c8fef 783 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
293f5f65 784 CPU_P2_FLAGS, 0 },
8a2c8fef 785 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
293f5f65 786 CPU_P3_FLAGS, 0 },
8a2c8fef 787 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
293f5f65 788 CPU_P4_FLAGS, 0 },
8a2c8fef 789 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
293f5f65 790 CPU_CORE_FLAGS, 0 },
8a2c8fef 791 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
293f5f65 792 CPU_NOCONA_FLAGS, 0 },
8a2c8fef 793 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
293f5f65 794 CPU_CORE_FLAGS, 1 },
8a2c8fef 795 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
293f5f65 796 CPU_CORE_FLAGS, 0 },
8a2c8fef 797 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
293f5f65 798 CPU_CORE2_FLAGS, 1 },
8a2c8fef 799 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
293f5f65 800 CPU_CORE2_FLAGS, 0 },
8a2c8fef 801 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
293f5f65 802 CPU_COREI7_FLAGS, 0 },
8a2c8fef 803 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
293f5f65 804 CPU_L1OM_FLAGS, 0 },
7a9068fe 805 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
293f5f65 806 CPU_K1OM_FLAGS, 0 },
81486035 807 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
293f5f65 808 CPU_IAMCU_FLAGS, 0 },
8a2c8fef 809 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
293f5f65 810 CPU_K6_FLAGS, 0 },
8a2c8fef 811 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
293f5f65 812 CPU_K6_2_FLAGS, 0 },
8a2c8fef 813 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
293f5f65 814 CPU_ATHLON_FLAGS, 0 },
8a2c8fef 815 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
293f5f65 816 CPU_K8_FLAGS, 1 },
8a2c8fef 817 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
293f5f65 818 CPU_K8_FLAGS, 0 },
8a2c8fef 819 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
293f5f65 820 CPU_K8_FLAGS, 0 },
8a2c8fef 821 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
293f5f65 822 CPU_AMDFAM10_FLAGS, 0 },
8aedb9fe 823 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
293f5f65 824 CPU_BDVER1_FLAGS, 0 },
8aedb9fe 825 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
293f5f65 826 CPU_BDVER2_FLAGS, 0 },
5e5c50d3 827 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
293f5f65 828 CPU_BDVER3_FLAGS, 0 },
c7b0bd56 829 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
293f5f65 830 CPU_BDVER4_FLAGS, 0 },
029f3522 831 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
293f5f65 832 CPU_ZNVER1_FLAGS, 0 },
7b458c12 833 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
293f5f65 834 CPU_BTVER1_FLAGS, 0 },
7b458c12 835 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
293f5f65 836 CPU_BTVER2_FLAGS, 0 },
8a2c8fef 837 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
293f5f65 838 CPU_8087_FLAGS, 0 },
8a2c8fef 839 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
293f5f65 840 CPU_287_FLAGS, 0 },
8a2c8fef 841 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
293f5f65 842 CPU_387_FLAGS, 0 },
1848e567
L		 843 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
844 CPU_687_FLAGS, 0 },
8a2c8fef 845 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
293f5f65 846 CPU_MMX_FLAGS, 0 },
8a2c8fef 847 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
293f5f65 848 CPU_SSE_FLAGS, 0 },
8a2c8fef 849 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
293f5f65 850 CPU_SSE2_FLAGS, 0 },
8a2c8fef 851 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
293f5f65 852 CPU_SSE3_FLAGS, 0 },
8a2c8fef 853 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
293f5f65 854 CPU_SSSE3_FLAGS, 0 },
8a2c8fef 855 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
293f5f65 856 CPU_SSE4_1_FLAGS, 0 },
8a2c8fef 857 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
293f5f65 858 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 859 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
293f5f65 860 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 861 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
293f5f65 862 CPU_AVX_FLAGS, 0 },
6c30d220 863 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
293f5f65 864 CPU_AVX2_FLAGS, 0 },
43234a1e 865 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
293f5f65 866 CPU_AVX512F_FLAGS, 0 },
43234a1e 867 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
293f5f65 868 CPU_AVX512CD_FLAGS, 0 },
43234a1e 869 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
293f5f65 870 CPU_AVX512ER_FLAGS, 0 },
43234a1e 871 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
293f5f65 872 CPU_AVX512PF_FLAGS, 0 },
1dfc6506 873 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
293f5f65 874 CPU_AVX512DQ_FLAGS, 0 },
1dfc6506 875 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
293f5f65 876 CPU_AVX512BW_FLAGS, 0 },
1dfc6506 877 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
293f5f65 878 CPU_AVX512VL_FLAGS, 0 },
8a2c8fef 879 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
293f5f65 880 CPU_VMX_FLAGS, 0 },
8729a6f6 881 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
293f5f65 882 CPU_VMFUNC_FLAGS, 0 },
8a2c8fef 883 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
293f5f65 884 CPU_SMX_FLAGS, 0 },
8a2c8fef 885 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
293f5f65 886 CPU_XSAVE_FLAGS, 0 },
c7b8aa3a 887 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
293f5f65 888 CPU_XSAVEOPT_FLAGS, 0 },
1dfc6506 889 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
293f5f65 890 CPU_XSAVEC_FLAGS, 0 },
1dfc6506 891 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
293f5f65 892 CPU_XSAVES_FLAGS, 0 },
8a2c8fef 893 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
293f5f65 894 CPU_AES_FLAGS, 0 },
8a2c8fef 895 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
293f5f65 896 CPU_PCLMUL_FLAGS, 0 },
8a2c8fef 897 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
293f5f65 898 CPU_PCLMUL_FLAGS, 1 },
c7b8aa3a 899 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
293f5f65 900 CPU_FSGSBASE_FLAGS, 0 },
c7b8aa3a 901 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
293f5f65 902 CPU_RDRND_FLAGS, 0 },
c7b8aa3a 903 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
293f5f65 904 CPU_F16C_FLAGS, 0 },
6c30d220 905 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
293f5f65 906 CPU_BMI2_FLAGS, 0 },
8a2c8fef 907 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
293f5f65 908 CPU_FMA_FLAGS, 0 },
8a2c8fef 909 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
293f5f65 910 CPU_FMA4_FLAGS, 0 },
8a2c8fef 911 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
293f5f65 912 CPU_XOP_FLAGS, 0 },
8a2c8fef 913 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
293f5f65 914 CPU_LWP_FLAGS, 0 },
8a2c8fef 915 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
293f5f65 916 CPU_MOVBE_FLAGS, 0 },
60aa667e 917 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
293f5f65 918 CPU_CX16_FLAGS, 0 },
8a2c8fef 919 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
293f5f65 920 CPU_EPT_FLAGS, 0 },
6c30d220 921 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
293f5f65 922 CPU_LZCNT_FLAGS, 0 },
42164a71 923 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
293f5f65 924 CPU_HLE_FLAGS, 0 },
42164a71 925 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
293f5f65 926 CPU_RTM_FLAGS, 0 },
6c30d220 927 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
293f5f65 928 CPU_INVPCID_FLAGS, 0 },
8a2c8fef 929 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
293f5f65 930 CPU_CLFLUSH_FLAGS, 0 },
22109423 931 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
293f5f65 932 CPU_NOP_FLAGS, 0 },
8a2c8fef 933 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
293f5f65 934 CPU_SYSCALL_FLAGS, 0 },
8a2c8fef 935 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
293f5f65 936 CPU_RDTSCP_FLAGS, 0 },
8a2c8fef 937 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
293f5f65 938 CPU_3DNOW_FLAGS, 0 },
8a2c8fef 939 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
293f5f65 940 CPU_3DNOWA_FLAGS, 0 },
8a2c8fef 941 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
293f5f65 942 CPU_PADLOCK_FLAGS, 0 },
8a2c8fef 943 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
293f5f65 944 CPU_SVME_FLAGS, 1 },
8a2c8fef 945 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
293f5f65 946 CPU_SVME_FLAGS, 0 },
8a2c8fef 947 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
293f5f65 948 CPU_SSE4A_FLAGS, 0 },
8a2c8fef 949 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
293f5f65 950 CPU_ABM_FLAGS, 0 },
87973e9f 951 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
293f5f65 952 CPU_BMI_FLAGS, 0 },
2a2a0f38 953 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
293f5f65 954 CPU_TBM_FLAGS, 0 },
e2e1fcde 955 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
293f5f65 956 CPU_ADX_FLAGS, 0 },
e2e1fcde 957 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
293f5f65 958 CPU_RDSEED_FLAGS, 0 },
e2e1fcde 959 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
293f5f65 960 CPU_PRFCHW_FLAGS, 0 },
5c111e37 961 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
293f5f65 962 CPU_SMAP_FLAGS, 0 },
7e8b059b 963 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
293f5f65 964 CPU_MPX_FLAGS, 0 },
a0046408 965 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
293f5f65 966 CPU_SHA_FLAGS, 0 },
963f3586 967 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
293f5f65 968 CPU_CLFLUSHOPT_FLAGS, 0 },
dcf893b5 969 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
293f5f65 970 CPU_PREFETCHWT1_FLAGS, 0 },
2cf200a4 971 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
293f5f65 972 CPU_SE1_FLAGS, 0 },
c5e7287a 973 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
293f5f65 974 CPU_CLWB_FLAGS, 0 },
2cc1b5aa 975 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
293f5f65 976 CPU_AVX512IFMA_FLAGS, 0 },
14f195c9 977 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
293f5f65 978 CPU_AVX512VBMI_FLAGS, 0 },
920d2ddc
IT		 979 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
980 CPU_AVX512_4FMAPS_FLAGS, 0 },
47acf0bd
IT		 981 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
982 CPU_AVX512_4VNNIW_FLAGS, 0 },
620214f7
IT		 983 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
984 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
53467f57
IT		 985 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
986 CPU_AVX512_VBMI2_FLAGS, 0 },
8cfcb765
IT		 987 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
988 CPU_AVX512_VNNI_FLAGS, 0 },
ee6872be
IT		 989 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
990 CPU_AVX512_BITALG_FLAGS, 0 },
029f3522 991 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
293f5f65 992 CPU_CLZERO_FLAGS, 0 },
9916071f 993 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
293f5f65 994 CPU_MWAITX_FLAGS, 0 },
8eab4136 995 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
293f5f65 996 CPU_OSPKE_FLAGS, 0 },
8bc52696 997 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
293f5f65 998 CPU_RDPID_FLAGS, 0 },
6b40c462
L		 999 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1000 CPU_PTWRITE_FLAGS, 0 },
603555e5
L		 1001 { STRING_COMMA_LEN (".cet"), PROCESSOR_UNKNOWN,
1002 CPU_CET_FLAGS, 0 },
48521003
IT		 1003 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1004 CPU_GFNI_FLAGS, 0 },
8dcf1fad
IT		 1005 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1006 CPU_VAES_FLAGS, 0 },
ff1982d5
IT		 1007 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1008 CPU_VPCLMULQDQ_FLAGS, 0 },
293f5f65
L		 1009};
1010
1011static const noarch_entry cpu_noarch[] =
1012{
1013 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1848e567
L		 1014 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1015 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1016 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
293f5f65
L		 1017 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1018 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1848e567
L		 1019 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1020 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1021 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1022 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1023 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1024 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
293f5f65 1025 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1848e567 1026 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
144b71e2
L		 1027 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1028 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1029 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1030 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1031 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1032 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1033 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1034 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1035 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
920d2ddc 1036 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
47acf0bd 1037 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
620214f7 1038 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
53467f57 1039 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
8cfcb765 1040 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
ee6872be 1041 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
e413e4e9
AM		 1042};
1043
704209c0 1044#ifdef I386COFF
a6c24e68
NC		 1045/* Like s_lcomm_internal in gas/read.c but the alignment string
1046 is allowed to be optional. */
1047
1048static symbolS *
1049pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1050{
1051 addressT align = 0;
1052
1053 SKIP_WHITESPACE ();
1054
7ab9ffdd 1055 if (needs_align
a6c24e68
NC		 1056 && *input_line_pointer == ',')
1057 {
1058 align = parse_align (needs_align - 1);
7ab9ffdd 1059
a6c24e68
NC		 1060 if (align == (addressT) -1)
1061 return NULL;
1062 }
1063 else
1064 {
1065 if (size >= 8)
1066 align = 3;
1067 else if (size >= 4)
1068 align = 2;
1069 else if (size >= 2)
1070 align = 1;
1071 else
1072 align = 0;
1073 }
1074
1075 bss_alloc (symbolP, size, align);
1076 return symbolP;
1077}
1078
704209c0 1079static void
a6c24e68
NC		 1080pe_lcomm (int needs_align)
1081{
1082 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1083}
704209c0 1084#endif
a6c24e68 1085
29b0f896
AM		 1086const pseudo_typeS md_pseudo_table[] =
1087{
1088#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1089 {"align", s_align_bytes, 0},
1090#else
1091 {"align", s_align_ptwo, 0},
1092#endif
1093 {"arch", set_cpu_arch, 0},
1094#ifndef I386COFF
1095 {"bss", s_bss, 0},
a6c24e68
NC		 1096#else
1097 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1098#endif
1099 {"ffloat", float_cons, 'f'},
1100 {"dfloat", float_cons, 'd'},
1101 {"tfloat", float_cons, 'x'},
1102 {"value", cons, 2},
d182319b 1103 {"slong", signed_cons, 4},
29b0f896
AM		 1104 {"noopt", s_ignore, 0},
1105 {"optim", s_ignore, 0},
1106 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1107 {"code16", set_code_flag, CODE_16BIT},
1108 {"code32", set_code_flag, CODE_32BIT},
1109 {"code64", set_code_flag, CODE_64BIT},
1110 {"intel_syntax", set_intel_syntax, 1},
1111 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1112 {"intel_mnemonic", set_intel_mnemonic, 1},
1113 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1114 {"allow_index_reg", set_allow_index_reg, 1},
1115 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1116 {"sse_check", set_check, 0},
1117 {"operand_check", set_check, 1},
3b22753a
L		 1118#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1119 {"largecomm", handle_large_common, 0},
07a53e5c 1120#else
e3bb37b5 1121 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 1122 {"loc", dwarf2_directive_loc, 0},
1123 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1124#endif
6482c264
NC		 1125#ifdef TE_PE
1126 {"secrel32", pe_directive_secrel, 0},
1127#endif
29b0f896
AM		 1128 {0, 0, 0}
1129};
1130
1131/* For interface with expression (). */
1132extern char *input_line_pointer;
1133
1134/* Hash table for instruction mnemonic lookup. */
1135static struct hash_control *op_hash;
1136
1137/* Hash table for register lookup. */
1138static struct hash_control *reg_hash;
1139\f
252b5132 1140void
e3bb37b5 1141i386_align_code (fragS *fragP, int count)
252b5132 1142{
ce8a8b2f
AM		 1143 /* Various efficient no-op patterns for aligning code labels.
1144 Note: Don't try to assemble the instructions in the comments.
1145 0L and 0w are not legal. */
bad6e36d 1146 static const unsigned char f32_1[] =
252b5132 1147 {0x90}; /* nop */
bad6e36d 1148 static const unsigned char f32_2[] =
ccc9c027 1149 {0x66,0x90}; /* xchg %ax,%ax */
bad6e36d 1150 static const unsigned char f32_3[] =
252b5132 1151 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
bad6e36d 1152 static const unsigned char f32_4[] =
252b5132 1153 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
bad6e36d 1154 static const unsigned char f32_5[] =
252b5132
RH		 1155 {0x90, /* nop */
1156 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
bad6e36d 1157 static const unsigned char f32_6[] =
252b5132 1158 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
bad6e36d 1159 static const unsigned char f32_7[] =
252b5132 1160 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
bad6e36d 1161 static const unsigned char f32_8[] =
252b5132
RH		 1162 {0x90, /* nop */
1163 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
bad6e36d 1164 static const unsigned char f32_9[] =
252b5132
RH		 1165 {0x89,0xf6, /* movl %esi,%esi */
1166 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1167 static const unsigned char f32_10[] =
252b5132
RH		 1168 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1169 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1170 static const unsigned char f32_11[] =
252b5132
RH		 1171 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1172 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1173 static const unsigned char f32_12[] =
252b5132
RH		 1174 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1175 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
bad6e36d 1176 static const unsigned char f32_13[] =
252b5132
RH		 1177 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1178 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1179 static const unsigned char f32_14[] =
252b5132
RH		 1180 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1181 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1182 static const unsigned char f16_3[] =
c3332e24 1183 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
bad6e36d 1184 static const unsigned char f16_4[] =
252b5132 1185 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
bad6e36d 1186 static const unsigned char f16_5[] =
252b5132
RH		 1187 {0x90, /* nop */
1188 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
bad6e36d 1189 static const unsigned char f16_6[] =
252b5132
RH		 1190 {0x89,0xf6, /* mov %si,%si */
1191 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1192 static const unsigned char f16_7[] =
252b5132
RH		 1193 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1194 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1195 static const unsigned char f16_8[] =
252b5132
RH		 1196 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1197 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1198 static const unsigned char jump_31[] =
76bc74dc
L		 1199 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1200 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1201 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1202 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
bad6e36d 1203 static const unsigned char *const f32_patt[] = {
252b5132 1204 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1205 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132 1206 };
bad6e36d 1207 static const unsigned char *const f16_patt[] = {
76bc74dc 1208 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1209 };
ccc9c027 1210 /* nopl (%[re]ax) */
bad6e36d 1211 static const unsigned char alt_3[] =
ccc9c027
L		 1212 {0x0f,0x1f,0x00};
1213 /* nopl 0(%[re]ax) */
bad6e36d 1214 static const unsigned char alt_4[] =
ccc9c027
L		 1215 {0x0f,0x1f,0x40,0x00};
1216 /* nopl 0(%[re]ax,%[re]ax,1) */
bad6e36d 1217 static const unsigned char alt_5[] =
ccc9c027
L		 1218 {0x0f,0x1f,0x44,0x00,0x00};
1219 /* nopw 0(%[re]ax,%[re]ax,1) */
bad6e36d 1220 static const unsigned char alt_6[] =
ccc9c027
L		 1221 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1222 /* nopl 0L(%[re]ax) */
bad6e36d 1223 static const unsigned char alt_7[] =
ccc9c027
L		 1224 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1225 /* nopl 0L(%[re]ax,%[re]ax,1) */
bad6e36d 1226 static const unsigned char alt_8[] =
ccc9c027
L		 1227 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1228 /* nopw 0L(%[re]ax,%[re]ax,1) */
bad6e36d 1229 static const unsigned char alt_9[] =
ccc9c027
L		 1230 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1231 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
bad6e36d 1232 static const unsigned char alt_10[] =
ccc9c027 1233 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
bad6e36d 1234 static const unsigned char *const alt_patt[] = {
ccc9c027 1235 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
80b8656c 1236 alt_9, alt_10
ccc9c027 1237 };
252b5132 1238
76bc74dc
L		 1239 /* Only align for at least a positive non-zero boundary. */
1240 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1241 return;
3e73aa7c 1242
ccc9c027
L		 1243 /* We need to decide which NOP sequence to use for 32bit and
1244 64bit. When -mtune= is used:
4eed87de 1245
76bc74dc
L		 1246 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1247 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1248 2. For the rest, alt_patt will be used.
1249
1250 When -mtune= isn't used, alt_patt will be used if
22109423 1251 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1252 be used.
ccc9c027
L		 1253
1254 When -march= or .arch is used, we can't use anything beyond
1255 cpu_arch_isa_flags. */
1256
1257 if (flag_code == CODE_16BIT)
1258 {
ccc9c027 1259 if (count > 8)
33fef721 1260 {
76bc74dc
L		 1261 memcpy (fragP->fr_literal + fragP->fr_fix,
1262 jump_31, count);
1263 /* Adjust jump offset. */
1264 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1265 }
76bc74dc
L		 1266 else
1267 memcpy (fragP->fr_literal + fragP->fr_fix,
1268 f16_patt[count - 1], count);
252b5132 1269 }
33fef721 1270 else
ccc9c027 1271 {
bad6e36d 1272 const unsigned char *const *patt = NULL;
ccc9c027 1273
fbf3f584 1274 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1275 {
1276 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1277 switch (cpu_arch_tune)
1278 {
1279 case PROCESSOR_UNKNOWN:
1280 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1281 optimize with nops. */
1282 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1283 patt = alt_patt;
ccc9c027
L		 1284 else
1285 patt = f32_patt;
1286 break;
ccc9c027
L		 1287 case PROCESSOR_PENTIUM4:
1288 case PROCESSOR_NOCONA:
ef05d495 1289 case PROCESSOR_CORE:
76bc74dc 1290 case PROCESSOR_CORE2:
bd5295b2 1291 case PROCESSOR_COREI7:
3632d14b 1292 case PROCESSOR_L1OM:
7a9068fe 1293 case PROCESSOR_K1OM:
76bc74dc 1294 case PROCESSOR_GENERIC64:
ccc9c027
L		 1295 case PROCESSOR_K6:
1296 case PROCESSOR_ATHLON:
1297 case PROCESSOR_K8:
4eed87de 1298 case PROCESSOR_AMDFAM10:
8aedb9fe 1299 case PROCESSOR_BD:
029f3522 1300 case PROCESSOR_ZNVER:
7b458c12 1301 case PROCESSOR_BT:
80b8656c 1302 patt = alt_patt;
ccc9c027 1303 break;
76bc74dc 1304 case PROCESSOR_I386:
ccc9c027
L		 1305 case PROCESSOR_I486:
1306 case PROCESSOR_PENTIUM:
2dde1948 1307 case PROCESSOR_PENTIUMPRO:
81486035 1308 case PROCESSOR_IAMCU:
ccc9c027
L		 1309 case PROCESSOR_GENERIC32:
1310 patt = f32_patt;
1311 break;
4eed87de 1312 }
ccc9c027
L		 1313 }
1314 else
1315 {
fbf3f584 1316 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1317 {
1318 case PROCESSOR_UNKNOWN:
e6a14101 1319 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1320 PROCESSOR_UNKNOWN. */
1321 abort ();
1322 break;
1323
76bc74dc 1324 case PROCESSOR_I386:
ccc9c027
L		 1325 case PROCESSOR_I486:
1326 case PROCESSOR_PENTIUM:
81486035 1327 case PROCESSOR_IAMCU:
ccc9c027
L		 1328 case PROCESSOR_K6:
1329 case PROCESSOR_ATHLON:
1330 case PROCESSOR_K8:
4eed87de 1331 case PROCESSOR_AMDFAM10:
8aedb9fe 1332 case PROCESSOR_BD:
029f3522 1333 case PROCESSOR_ZNVER:
7b458c12 1334 case PROCESSOR_BT:
ccc9c027
L		 1335 case PROCESSOR_GENERIC32:
1336 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1337 with nops. */
1338 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1339 patt = alt_patt;
ccc9c027
L		 1340 else
1341 patt = f32_patt;
1342 break;
76bc74dc
L		 1343 case PROCESSOR_PENTIUMPRO:
1344 case PROCESSOR_PENTIUM4:
1345 case PROCESSOR_NOCONA:
1346 case PROCESSOR_CORE:
ef05d495 1347 case PROCESSOR_CORE2:
bd5295b2 1348 case PROCESSOR_COREI7:
3632d14b 1349 case PROCESSOR_L1OM:
7a9068fe 1350 case PROCESSOR_K1OM:
22109423 1351 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1352 patt = alt_patt;
ccc9c027
L		 1353 else
1354 patt = f32_patt;
1355 break;
1356 case PROCESSOR_GENERIC64:
80b8656c 1357 patt = alt_patt;
ccc9c027 1358 break;
4eed87de 1359 }
ccc9c027
L		 1360 }
1361
76bc74dc
L		 1362 if (patt == f32_patt)
1363 {
1364 /* If the padding is less than 15 bytes, we use the normal
1365 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1366 its offset. */
1367 int limit;
76ba9986 1368
711eedef
L		 1369 /* For 64bit, the limit is 3 bytes. */
1370 if (flag_code == CODE_64BIT
1371 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1372 limit = 3;
1373 else
1374 limit = 15;
1375 if (count < limit)
76bc74dc
L		 1376 memcpy (fragP->fr_literal + fragP->fr_fix,
1377 patt[count - 1], count);
1378 else
1379 {
1380 memcpy (fragP->fr_literal + fragP->fr_fix,
1381 jump_31, count);
1382 /* Adjust jump offset. */
1383 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1384 }
1385 }
1386 else
1387 {
80b8656c
L		 1388 /* Maximum length of an instruction is 10 byte. If the
1389 padding is greater than 10 bytes and we don't use jump,
76bc74dc
L		 1390 we have to break it into smaller pieces. */
1391 int padding = count;
80b8656c 1392 while (padding > 10)
76bc74dc 1393 {
80b8656c 1394 padding -= 10;
76bc74dc 1395 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
80b8656c 1396 patt [9], 10);
76bc74dc
L		 1397 }
1398
1399 if (padding)
1400 memcpy (fragP->fr_literal + fragP->fr_fix,
1401 patt [padding - 1], padding);
1402 }
ccc9c027 1403 }
33fef721 1404 fragP->fr_var = count;
252b5132
RH		 1405}
1406
c6fb90c8 1407static INLINE int
0dfbf9d7 1408operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1409{
0dfbf9d7 1410 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1411 {
1412 case 3:
0dfbf9d7 1413 if (x->array[2])
c6fb90c8 1414 return 0;
1a0670f3 1415 /* Fall through. */
c6fb90c8 1416 case 2:
0dfbf9d7 1417 if (x->array[1])
c6fb90c8 1418 return 0;
1a0670f3 1419 /* Fall through. */
c6fb90c8 1420 case 1:
0dfbf9d7 1421 return !x->array[0];
c6fb90c8
L		 1422 default:
1423 abort ();
1424 }
40fb9820
L		 1425}
1426
c6fb90c8 1427static INLINE void
0dfbf9d7 1428operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1429{
0dfbf9d7 1430 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1431 {
1432 case 3:
0dfbf9d7 1433 x->array[2] = v;
1a0670f3 1434 /* Fall through. */
c6fb90c8 1435 case 2:
0dfbf9d7 1436 x->array[1] = v;
1a0670f3 1437 /* Fall through. */
c6fb90c8 1438 case 1:
0dfbf9d7 1439 x->array[0] = v;
1a0670f3 1440 /* Fall through. */
c6fb90c8
L		 1441 break;
1442 default:
1443 abort ();
1444 }
1445}
40fb9820 1446
c6fb90c8 1447static INLINE int
0dfbf9d7
L		 1448operand_type_equal (const union i386_operand_type *x,
1449 const union i386_operand_type *y)
c6fb90c8 1450{
0dfbf9d7 1451 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1452 {
1453 case 3:
0dfbf9d7 1454 if (x->array[2] != y->array[2])
c6fb90c8 1455 return 0;
1a0670f3 1456 /* Fall through. */
c6fb90c8 1457 case 2:
0dfbf9d7 1458 if (x->array[1] != y->array[1])
c6fb90c8 1459 return 0;
1a0670f3 1460 /* Fall through. */
c6fb90c8 1461 case 1:
0dfbf9d7 1462 return x->array[0] == y->array[0];
c6fb90c8
L		 1463 break;
1464 default:
1465 abort ();
1466 }
1467}
40fb9820 1468
0dfbf9d7
L		 1469static INLINE int
1470cpu_flags_all_zero (const union i386_cpu_flags *x)
1471{
1472 switch (ARRAY_SIZE(x->array))
1473 {
53467f57
IT		 1474 case 4:
1475 if (x->array[3])
1476 return 0;
1477 /* Fall through. */
0dfbf9d7
L		 1478 case 3:
1479 if (x->array[2])
1480 return 0;
1a0670f3 1481 /* Fall through. */
0dfbf9d7
L		 1482 case 2:
1483 if (x->array[1])
1484 return 0;
1a0670f3 1485 /* Fall through. */
0dfbf9d7
L		 1486 case 1:
1487 return !x->array[0];
1488 default:
1489 abort ();
1490 }
1491}
1492
0dfbf9d7
L		 1493static INLINE int
1494cpu_flags_equal (const union i386_cpu_flags *x,
1495 const union i386_cpu_flags *y)
1496{
1497 switch (ARRAY_SIZE(x->array))
1498 {
53467f57
IT		 1499 case 4:
1500 if (x->array[3] != y->array[3])
1501 return 0;
1502 /* Fall through. */
0dfbf9d7
L		 1503 case 3:
1504 if (x->array[2] != y->array[2])
1505 return 0;
1a0670f3 1506 /* Fall through. */
0dfbf9d7
L		 1507 case 2:
1508 if (x->array[1] != y->array[1])
1509 return 0;
1a0670f3 1510 /* Fall through. */
0dfbf9d7
L		 1511 case 1:
1512 return x->array[0] == y->array[0];
1513 break;
1514 default:
1515 abort ();
1516 }
1517}
c6fb90c8
L		 1518
1519static INLINE int
1520cpu_flags_check_cpu64 (i386_cpu_flags f)
1521{
1522 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1523 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1524}
1525
c6fb90c8
L		 1526static INLINE i386_cpu_flags
1527cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1528{
c6fb90c8
L		 1529 switch (ARRAY_SIZE (x.array))
1530 {
53467f57
IT		 1531 case 4:
1532 x.array [3] &= y.array [3];
1533 /* Fall through. */
c6fb90c8
L		 1534 case 3:
1535 x.array [2] &= y.array [2];
1a0670f3 1536 /* Fall through. */
c6fb90c8
L		 1537 case 2:
1538 x.array [1] &= y.array [1];
1a0670f3 1539 /* Fall through. */
c6fb90c8
L		 1540 case 1:
1541 x.array [0] &= y.array [0];
1542 break;
1543 default:
1544 abort ();
1545 }
1546 return x;
1547}
40fb9820 1548
c6fb90c8
L		 1549static INLINE i386_cpu_flags
1550cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1551{
c6fb90c8 1552 switch (ARRAY_SIZE (x.array))
40fb9820 1553 {
53467f57
IT		 1554 case 4:
1555 x.array [3] |= y.array [3];
1556 /* Fall through. */
c6fb90c8
L		 1557 case 3:
1558 x.array [2] |= y.array [2];
1a0670f3 1559 /* Fall through. */
c6fb90c8
L		 1560 case 2:
1561 x.array [1] |= y.array [1];
1a0670f3 1562 /* Fall through. */
c6fb90c8
L		 1563 case 1:
1564 x.array [0] |= y.array [0];
40fb9820
L		 1565 break;
1566 default:
1567 abort ();
1568 }
40fb9820
L		 1569 return x;
1570}
1571
309d3373
JB		 1572static INLINE i386_cpu_flags
1573cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1574{
1575 switch (ARRAY_SIZE (x.array))
1576 {
53467f57
IT		 1577 case 4:
1578 x.array [3] &= ~y.array [3];
1579 /* Fall through. */
309d3373
JB		 1580 case 3:
1581 x.array [2] &= ~y.array [2];
1a0670f3 1582 /* Fall through. */
309d3373
JB		 1583 case 2:
1584 x.array [1] &= ~y.array [1];
1a0670f3 1585 /* Fall through. */
309d3373
JB		 1586 case 1:
1587 x.array [0] &= ~y.array [0];
1588 break;
1589 default:
1590 abort ();
1591 }
1592 return x;
1593}
1594
c0f3af97
L		 1595#define CPU_FLAGS_ARCH_MATCH 0x1
1596#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1597#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1598#define CPU_FLAGS_PCLMUL_MATCH 0x8
1599#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1600
a5ff0eb2 1601#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1602 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1603 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1604#define CPU_FLAGS_PERFECT_MATCH \
1605 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1606
1607/* Return CPU flags match bits. */
3629bb00 1608
40fb9820 1609static int
d3ce72d0 1610cpu_flags_match (const insn_template *t)
40fb9820 1611{
c0f3af97
L		 1612 i386_cpu_flags x = t->cpu_flags;
1613 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1614
1615 x.bitfield.cpu64 = 0;
1616 x.bitfield.cpuno64 = 0;
1617
0dfbf9d7 1618 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1619 {
1620 /* This instruction is available on all archs. */
1621 match |= CPU_FLAGS_32BIT_MATCH;
1622 }
3629bb00
L		 1623 else
1624 {
c0f3af97 1625 /* This instruction is available only on some archs. */
3629bb00
L		 1626 i386_cpu_flags cpu = cpu_arch_flags;
1627
3629bb00 1628 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1629 if (!cpu_flags_all_zero (&cpu))
1630 {
a5ff0eb2
L		 1631 if (x.bitfield.cpuavx)
1632 {
ce2f5b3c 1633 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1634 if (cpu.bitfield.cpuavx)
1635 {
1636 /* Check SSE2AVX. */
1637 if (!t->opcode_modifier.sse2avx|| sse2avx)
1638 {
1639 match |= (CPU_FLAGS_ARCH_MATCH
1640 | CPU_FLAGS_AVX_MATCH);
1641 /* Check AES. */
1642 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1643 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1644 /* Check PCLMUL. */
1645 if (!x.bitfield.cpupclmul
1646 || cpu.bitfield.cpupclmul)
1647 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1648 }
1649 }
1650 else
1651 match |= CPU_FLAGS_ARCH_MATCH;
1652 }
73b090a9
L		 1653 else if (x.bitfield.cpuavx512vl)
1654 {
1655 /* Match AVX512VL. */
1656 if (cpu.bitfield.cpuavx512vl)
1657 {
1658 /* Need another match. */
1659 cpu.bitfield.cpuavx512vl = 0;
1660 if (!cpu_flags_all_zero (&cpu))
1661 match |= CPU_FLAGS_32BIT_MATCH;
1662 else
1663 match |= CPU_FLAGS_ARCH_MATCH;
1664 }
1665 else
1666 match |= CPU_FLAGS_ARCH_MATCH;
1667 }
a5ff0eb2 1668 else
c0f3af97
L		 1669 match |= CPU_FLAGS_32BIT_MATCH;
1670 }
3629bb00 1671 }
c0f3af97 1672 return match;
40fb9820
L		 1673}
1674
c6fb90c8
L		 1675static INLINE i386_operand_type
1676operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1677{
c6fb90c8
L		 1678 switch (ARRAY_SIZE (x.array))
1679 {
1680 case 3:
1681 x.array [2] &= y.array [2];
1a0670f3 1682 /* Fall through. */
c6fb90c8
L		 1683 case 2:
1684 x.array [1] &= y.array [1];
1a0670f3 1685 /* Fall through. */
c6fb90c8
L		 1686 case 1:
1687 x.array [0] &= y.array [0];
1688 break;
1689 default:
1690 abort ();
1691 }
1692 return x;
40fb9820
L		 1693}
1694
c6fb90c8
L		 1695static INLINE i386_operand_type
1696operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1697{
c6fb90c8 1698 switch (ARRAY_SIZE (x.array))
40fb9820 1699 {
c6fb90c8
L		 1700 case 3:
1701 x.array [2] |= y.array [2];
1a0670f3 1702 /* Fall through. */
c6fb90c8
L		 1703 case 2:
1704 x.array [1] |= y.array [1];
1a0670f3 1705 /* Fall through. */
c6fb90c8
L		 1706 case 1:
1707 x.array [0] |= y.array [0];
40fb9820
L		 1708 break;
1709 default:
1710 abort ();
1711 }
c6fb90c8
L		 1712 return x;
1713}
40fb9820 1714
c6fb90c8
L		 1715static INLINE i386_operand_type
1716operand_type_xor (i386_operand_type x, i386_operand_type y)
1717{
1718 switch (ARRAY_SIZE (x.array))
1719 {
1720 case 3:
1721 x.array [2] ^= y.array [2];
1a0670f3 1722 /* Fall through. */
c6fb90c8
L		 1723 case 2:
1724 x.array [1] ^= y.array [1];
1a0670f3 1725 /* Fall through. */
c6fb90c8
L		 1726 case 1:
1727 x.array [0] ^= y.array [0];
1728 break;
1729 default:
1730 abort ();
1731 }
40fb9820
L		 1732 return x;
1733}
1734
1735static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1736static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1737static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1738static const i386_operand_type inoutportreg
1739 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1740static const i386_operand_type reg16_inoutportreg
1741 = OPERAND_TYPE_REG16_INOUTPORTREG;
1742static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1743static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1744static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1745static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1746static const i386_operand_type anydisp
1747 = OPERAND_TYPE_ANYDISP;
40fb9820 1748static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1749static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1750static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1751static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1752static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1753static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1754static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1755static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1756static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1757static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1758static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1759static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1760static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1761static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1762
1763enum operand_type
1764{
1765 reg,
40fb9820
L		 1766 imm,
1767 disp,
1768 anymem
1769};
1770
c6fb90c8 1771static INLINE int
40fb9820
L		 1772operand_type_check (i386_operand_type t, enum operand_type c)
1773{
1774 switch (c)
1775 {
1776 case reg:
1777 return (t.bitfield.reg8
1778 || t.bitfield.reg16
1779 || t.bitfield.reg32
1780 || t.bitfield.reg64);
1781
40fb9820
L		 1782 case imm:
1783 return (t.bitfield.imm8
1784 || t.bitfield.imm8s
1785 || t.bitfield.imm16
1786 || t.bitfield.imm32
1787 || t.bitfield.imm32s
1788 || t.bitfield.imm64);
1789
1790 case disp:
1791 return (t.bitfield.disp8
1792 || t.bitfield.disp16
1793 || t.bitfield.disp32
1794 || t.bitfield.disp32s
1795 || t.bitfield.disp64);
1796
1797 case anymem:
1798 return (t.bitfield.disp8
1799 || t.bitfield.disp16
1800 || t.bitfield.disp32
1801 || t.bitfield.disp32s
1802 || t.bitfield.disp64
1803 || t.bitfield.baseindex);
1804
1805 default:
1806 abort ();
1807 }
2cfe26b6
AM		 1808
1809 return 0;
40fb9820
L		 1810}
1811
5c07affc
L		 1812/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1813 operand J for instruction template T. */
1814
1815static INLINE int
d3ce72d0 1816match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1817{
1818 return !((i.types[j].bitfield.byte
1819 && !t->operand_types[j].bitfield.byte)
1820 || (i.types[j].bitfield.word
1821 && !t->operand_types[j].bitfield.word)
1822 || (i.types[j].bitfield.dword
1823 && !t->operand_types[j].bitfield.dword)
1824 || (i.types[j].bitfield.qword
1825 && !t->operand_types[j].bitfield.qword));
1826}
1827
1828/* Return 1 if there is no conflict in any size on operand J for
1829 instruction template T. */
1830
1831static INLINE int
d3ce72d0 1832match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1833{
1834 return (match_reg_size (t, j)
1835 && !((i.types[j].bitfield.unspecified
af508cb9 1836 && !i.broadcast
5c07affc
L		 1837 && !t->operand_types[j].bitfield.unspecified)
1838 || (i.types[j].bitfield.fword
1839 && !t->operand_types[j].bitfield.fword)
1840 || (i.types[j].bitfield.tbyte
1841 && !t->operand_types[j].bitfield.tbyte)
1842 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1843 && !t->operand_types[j].bitfield.xmmword)
1844 || (i.types[j].bitfield.ymmword
43234a1e
L		 1845 && !t->operand_types[j].bitfield.ymmword)
1846 || (i.types[j].bitfield.zmmword
1847 && !t->operand_types[j].bitfield.zmmword)));
5c07affc
L		 1848}
1849
1850/* Return 1 if there is no size conflict on any operands for
1851 instruction template T. */
1852
1853static INLINE int
d3ce72d0 1854operand_size_match (const insn_template *t)
5c07affc
L		 1855{
1856 unsigned int j;
1857 int match = 1;
1858
1859 /* Don't check jump instructions. */
1860 if (t->opcode_modifier.jump
1861 || t->opcode_modifier.jumpbyte
1862 || t->opcode_modifier.jumpdword
1863 || t->opcode_modifier.jumpintersegment)
1864 return match;
1865
1866 /* Check memory and accumulator operand size. */
1867 for (j = 0; j < i.operands; j++)
1868 {
1869 if (t->operand_types[j].bitfield.anysize)
1870 continue;
1871
1872 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1873 {
1874 match = 0;
1875 break;
1876 }
1877
1878 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1879 {
1880 match = 0;
1881 break;
1882 }
1883 }
1884
891edac4 1885 if (match)
5c07affc 1886 return match;
891edac4
L		 1887 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1888 {
1889mismatch:
86e026a4 1890 i.error = operand_size_mismatch;
891edac4
L		 1891 return 0;
1892 }
5c07affc
L		 1893
1894 /* Check reverse. */
9c2799c2 1895 gas_assert (i.operands == 2);
5c07affc
L		 1896
1897 match = 1;
1898 for (j = 0; j < 2; j++)
1899 {
1900 if (t->operand_types[j].bitfield.acc
1901 && !match_reg_size (t, j ? 0 : 1))
891edac4 1902 goto mismatch;
5c07affc
L		 1903
1904 if (i.types[j].bitfield.mem
1905 && !match_mem_size (t, j ? 0 : 1))
891edac4 1906 goto mismatch;
5c07affc
L		 1907 }
1908
1909 return match;
1910}
1911
c6fb90c8 1912static INLINE int
40fb9820
L		 1913operand_type_match (i386_operand_type overlap,
1914 i386_operand_type given)
1915{
1916 i386_operand_type temp = overlap;
1917
1918 temp.bitfield.jumpabsolute = 0;
7d5e4556 1919 temp.bitfield.unspecified = 0;
5c07affc
L		 1920 temp.bitfield.byte = 0;
1921 temp.bitfield.word = 0;
1922 temp.bitfield.dword = 0;
1923 temp.bitfield.fword = 0;
1924 temp.bitfield.qword = 0;
1925 temp.bitfield.tbyte = 0;
1926 temp.bitfield.xmmword = 0;
c0f3af97 1927 temp.bitfield.ymmword = 0;
43234a1e 1928 temp.bitfield.zmmword = 0;
0dfbf9d7 1929 if (operand_type_all_zero (&temp))
891edac4 1930 goto mismatch;
40fb9820 1931
891edac4
L		 1932 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1933 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1934 return 1;
1935
1936mismatch:
a65babc9 1937 i.error = operand_type_mismatch;
891edac4 1938 return 0;
40fb9820
L		 1939}
1940
7d5e4556 1941/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1942 unless the expected operand type register overlap is null.
1943 Note that Acc in a template matches every size of reg. */
1944
c6fb90c8 1945static INLINE int
40fb9820
L		 1946operand_type_register_match (i386_operand_type m0,
1947 i386_operand_type g0,
1948 i386_operand_type t0,
1949 i386_operand_type m1,
1950 i386_operand_type g1,
1951 i386_operand_type t1)
1952{
1953 if (!operand_type_check (g0, reg))
1954 return 1;
1955
1956 if (!operand_type_check (g1, reg))
1957 return 1;
1958
1959 if (g0.bitfield.reg8 == g1.bitfield.reg8
1960 && g0.bitfield.reg16 == g1.bitfield.reg16
1961 && g0.bitfield.reg32 == g1.bitfield.reg32
1962 && g0.bitfield.reg64 == g1.bitfield.reg64)
1963 return 1;
1964
1965 if (m0.bitfield.acc)
1966 {
1967 t0.bitfield.reg8 = 1;
1968 t0.bitfield.reg16 = 1;
1969 t0.bitfield.reg32 = 1;
1970 t0.bitfield.reg64 = 1;
1971 }
1972
1973 if (m1.bitfield.acc)
1974 {
1975 t1.bitfield.reg8 = 1;
1976 t1.bitfield.reg16 = 1;
1977 t1.bitfield.reg32 = 1;
1978 t1.bitfield.reg64 = 1;
1979 }
1980
891edac4
L		 1981 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1982 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1983 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1984 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1985 return 1;
1986
a65babc9 1987 i.error = register_type_mismatch;
891edac4
L		 1988
1989 return 0;
40fb9820
L		 1990}
1991
4c692bc7
JB		 1992static INLINE unsigned int
1993register_number (const reg_entry *r)
1994{
1995 unsigned int nr = r->reg_num;
1996
1997 if (r->reg_flags & RegRex)
1998 nr += 8;
1999
200cbe0f
L		 2000 if (r->reg_flags & RegVRex)
2001 nr += 16;
2002
4c692bc7
JB		 2003 return nr;
2004}
2005
252b5132 2006static INLINE unsigned int
40fb9820 2007mode_from_disp_size (i386_operand_type t)
252b5132 2008{
43234a1e 2009 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
40fb9820
L		 2010 return 1;
2011 else if (t.bitfield.disp16
2012 || t.bitfield.disp32
2013 || t.bitfield.disp32s)
2014 return 2;
2015 else
2016 return 0;
252b5132
RH		 2017}
2018
2019static INLINE int
65879393 2020fits_in_signed_byte (addressT num)
252b5132 2021{
65879393 2022 return num + 0x80 <= 0xff;
47926f60 2023}
252b5132
RH		 2024
2025static INLINE int
65879393 2026fits_in_unsigned_byte (addressT num)
252b5132 2027{
65879393 2028 return num <= 0xff;
47926f60 2029}
252b5132
RH		 2030
2031static INLINE int
65879393 2032fits_in_unsigned_word (addressT num)
252b5132 2033{
65879393 2034 return num <= 0xffff;
47926f60 2035}
252b5132
RH		 2036
2037static INLINE int
65879393 2038fits_in_signed_word (addressT num)
252b5132 2039{
65879393 2040 return num + 0x8000 <= 0xffff;
47926f60 2041}
2a962e6d 2042
3e73aa7c 2043static INLINE int
65879393 2044fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2045{
2046#ifndef BFD64
2047 return 1;
2048#else
65879393 2049 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 2050#endif
2051} /* fits_in_signed_long() */
2a962e6d 2052
3e73aa7c 2053static INLINE int
65879393 2054fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2055{
2056#ifndef BFD64
2057 return 1;
2058#else
65879393 2059 return num <= 0xffffffff;
3e73aa7c
JH		 2060#endif
2061} /* fits_in_unsigned_long() */
252b5132 2062
43234a1e
L		 2063static INLINE int
2064fits_in_vec_disp8 (offsetT num)
2065{
2066 int shift = i.memshift;
2067 unsigned int mask;
2068
2069 if (shift == -1)
2070 abort ();
2071
2072 mask = (1 << shift) - 1;
2073
2074 /* Return 0 if NUM isn't properly aligned. */
2075 if ((num & mask))
2076 return 0;
2077
2078 /* Check if NUM will fit in 8bit after shift. */
2079 return fits_in_signed_byte (num >> shift);
2080}
2081
a683cc34
SP		 2082static INLINE int
2083fits_in_imm4 (offsetT num)
2084{
2085 return (num & 0xf) == num;
2086}
2087
40fb9820 2088static i386_operand_type
e3bb37b5 2089smallest_imm_type (offsetT num)
252b5132 2090{
40fb9820 2091 i386_operand_type t;
7ab9ffdd 2092
0dfbf9d7 2093 operand_type_set (&t, 0);
40fb9820
L		 2094 t.bitfield.imm64 = 1;
2095
2096 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2097 {
2098 /* This code is disabled on the 486 because all the Imm1 forms
2099 in the opcode table are slower on the i486. They're the
2100 versions with the implicitly specified single-position
2101 displacement, which has another syntax if you really want to
2102 use that form. */
40fb9820
L		 2103 t.bitfield.imm1 = 1;
2104 t.bitfield.imm8 = 1;
2105 t.bitfield.imm8s = 1;
2106 t.bitfield.imm16 = 1;
2107 t.bitfield.imm32 = 1;
2108 t.bitfield.imm32s = 1;
2109 }
2110 else if (fits_in_signed_byte (num))
2111 {
2112 t.bitfield.imm8 = 1;
2113 t.bitfield.imm8s = 1;
2114 t.bitfield.imm16 = 1;
2115 t.bitfield.imm32 = 1;
2116 t.bitfield.imm32s = 1;
2117 }
2118 else if (fits_in_unsigned_byte (num))
2119 {
2120 t.bitfield.imm8 = 1;
2121 t.bitfield.imm16 = 1;
2122 t.bitfield.imm32 = 1;
2123 t.bitfield.imm32s = 1;
2124 }
2125 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2126 {
2127 t.bitfield.imm16 = 1;
2128 t.bitfield.imm32 = 1;
2129 t.bitfield.imm32s = 1;
2130 }
2131 else if (fits_in_signed_long (num))
2132 {
2133 t.bitfield.imm32 = 1;
2134 t.bitfield.imm32s = 1;
2135 }
2136 else if (fits_in_unsigned_long (num))
2137 t.bitfield.imm32 = 1;
2138
2139 return t;
47926f60 2140}
252b5132 2141
847f7ad4 2142static offsetT
e3bb37b5 2143offset_in_range (offsetT val, int size)
847f7ad4 2144{
508866be 2145 addressT mask;
ba2adb93 2146
847f7ad4
AM		 2147 switch (size)
2148 {
508866be
L		 2149 case 1: mask = ((addressT) 1 << 8) - 1; break;
2150 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2151 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2152#ifdef BFD64
2153 case 8: mask = ((addressT) 2 << 63) - 1; break;
2154#endif
47926f60 2155 default: abort ();
847f7ad4
AM		 2156 }
2157
9de868bf
L		 2158#ifdef BFD64
2159 /* If BFD64, sign extend val for 32bit address mode. */
2160 if (flag_code != CODE_64BIT
2161 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2162 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2163 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2164#endif
ba2adb93 2165
47926f60 2166 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2167 {
2168 char buf1[40], buf2[40];
2169
2170 sprint_value (buf1, val);
2171 sprint_value (buf2, val & mask);
2172 as_warn (_("%s shortened to %s"), buf1, buf2);
2173 }
2174 return val & mask;
2175}
2176
c32fa91d
L		 2177enum PREFIX_GROUP
2178{
2179 PREFIX_EXIST = 0,
2180 PREFIX_LOCK,
2181 PREFIX_REP,
04ef582a 2182 PREFIX_DS,
c32fa91d
L		 2183 PREFIX_OTHER
2184};
2185
2186/* Returns
2187 a. PREFIX_EXIST if attempting to add a prefix where one from the
2188 same class already exists.
2189 b. PREFIX_LOCK if lock prefix is added.
2190 c. PREFIX_REP if rep/repne prefix is added.
04ef582a
L		 2191 d. PREFIX_DS if ds prefix is added.
2192 e. PREFIX_OTHER if other prefix is added.
c32fa91d
L		 2193 */
2194
2195static enum PREFIX_GROUP
e3bb37b5 2196add_prefix (unsigned int prefix)
252b5132 2197{
c32fa91d 2198 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2199 unsigned int q;
252b5132 2200
29b0f896
AM		 2201 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2202 && flag_code == CODE_64BIT)
b1905489 2203 {
161a04f6
L		 2204 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2205 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2206 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2207 ret = PREFIX_EXIST;
b1905489
JB		 2208 q = REX_PREFIX;
2209 }
3e73aa7c 2210 else
b1905489
JB		 2211 {
2212 switch (prefix)
2213 {
2214 default:
2215 abort ();
2216
b1905489 2217 case DS_PREFIX_OPCODE:
04ef582a
L		 2218 ret = PREFIX_DS;
2219 /* Fall through. */
2220 case CS_PREFIX_OPCODE:
b1905489
JB		 2221 case ES_PREFIX_OPCODE:
2222 case FS_PREFIX_OPCODE:
2223 case GS_PREFIX_OPCODE:
2224 case SS_PREFIX_OPCODE:
2225 q = SEG_PREFIX;
2226 break;
2227
2228 case REPNE_PREFIX_OPCODE:
2229 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2230 q = REP_PREFIX;
2231 ret = PREFIX_REP;
2232 break;
2233
b1905489 2234 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2235 q = LOCK_PREFIX;
2236 ret = PREFIX_LOCK;
b1905489
JB		 2237 break;
2238
2239 case FWAIT_OPCODE:
2240 q = WAIT_PREFIX;
2241 break;
2242
2243 case ADDR_PREFIX_OPCODE:
2244 q = ADDR_PREFIX;
2245 break;
2246
2247 case DATA_PREFIX_OPCODE:
2248 q = DATA_PREFIX;
2249 break;
2250 }
2251 if (i.prefix[q] != 0)
c32fa91d 2252 ret = PREFIX_EXIST;
b1905489 2253 }
252b5132 2254
b1905489 2255 if (ret)
252b5132 2256 {
b1905489
JB		 2257 if (!i.prefix[q])
2258 ++i.prefixes;
2259 i.prefix[q] |= prefix;
252b5132 2260 }
b1905489
JB		 2261 else
2262 as_bad (_("same type of prefix used twice"));
252b5132 2263
252b5132
RH		 2264 return ret;
2265}
2266
2267static void
78f12dd3 2268update_code_flag (int value, int check)
eecb386c 2269{
78f12dd3
L		 2270 PRINTF_LIKE ((*as_error));
2271
1e9cc1c2 2272 flag_code = (enum flag_code) value;
40fb9820
L		 2273 if (flag_code == CODE_64BIT)
2274 {
2275 cpu_arch_flags.bitfield.cpu64 = 1;
2276 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2277 }
2278 else
2279 {
2280 cpu_arch_flags.bitfield.cpu64 = 0;
2281 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2282 }
2283 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2284 {
78f12dd3
L		 2285 if (check)
2286 as_error = as_fatal;
2287 else
2288 as_error = as_bad;
2289 (*as_error) (_("64bit mode not supported on `%s'."),
2290 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2291 }
40fb9820 2292 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2293 {
78f12dd3
L		 2294 if (check)
2295 as_error = as_fatal;
2296 else
2297 as_error = as_bad;
2298 (*as_error) (_("32bit mode not supported on `%s'."),
2299 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2300 }
eecb386c
AM		 2301 stackop_size = '\0';
2302}
2303
78f12dd3
L		 2304static void
2305set_code_flag (int value)
2306{
2307 update_code_flag (value, 0);
2308}
2309
eecb386c 2310static void
e3bb37b5 2311set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2312{
1e9cc1c2 2313 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2314 if (flag_code != CODE_16BIT)
2315 abort ();
2316 cpu_arch_flags.bitfield.cpu64 = 0;
2317 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2318 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2319}
2320
2321static void
e3bb37b5 2322set_intel_syntax (int syntax_flag)
252b5132
RH		 2323{
2324 /* Find out if register prefixing is specified. */
2325 int ask_naked_reg = 0;
2326
2327 SKIP_WHITESPACE ();
29b0f896 2328 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132 2329 {
d02603dc
NC		 2330 char *string;
2331 int e = get_symbol_name (&string);
252b5132 2332
47926f60 2333 if (strcmp (string, "prefix") == 0)
252b5132 2334 ask_naked_reg = 1;
47926f60 2335 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2336 ask_naked_reg = -1;
2337 else
d0b47220 2338 as_bad (_("bad argument to syntax directive."));
d02603dc 2339 (void) restore_line_pointer (e);
252b5132
RH		 2340 }
2341 demand_empty_rest_of_line ();
c3332e24 2342
252b5132
RH		 2343 intel_syntax = syntax_flag;
2344
2345 if (ask_naked_reg == 0)
f86103b7
AM		 2346 allow_naked_reg = (intel_syntax
2347 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2348 else
2349 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2350
ee86248c 2351 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2352
e4a3b5a4 2353 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2354 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2355 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2356}
2357
1efbbeb4
L		 2358static void
2359set_intel_mnemonic (int mnemonic_flag)
2360{
e1d4d893 2361 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2362}
2363
db51cc60
L		 2364static void
2365set_allow_index_reg (int flag)
2366{
2367 allow_index_reg = flag;
2368}
2369
cb19c032 2370static void
7bab8ab5 2371set_check (int what)
cb19c032 2372{
7bab8ab5
JB		 2373 enum check_kind *kind;
2374 const char *str;
2375
2376 if (what)
2377 {
2378 kind = &operand_check;
2379 str = "operand";
2380 }
2381 else
2382 {
2383 kind = &sse_check;
2384 str = "sse";
2385 }
2386
cb19c032
L		 2387 SKIP_WHITESPACE ();
2388
2389 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2390 {
d02603dc
NC		 2391 char *string;
2392 int e = get_symbol_name (&string);
cb19c032
L		 2393
2394 if (strcmp (string, "none") == 0)
7bab8ab5 2395 *kind = check_none;
cb19c032 2396 else if (strcmp (string, "warning") == 0)
7bab8ab5 2397 *kind = check_warning;
cb19c032 2398 else if (strcmp (string, "error") == 0)
7bab8ab5 2399 *kind = check_error;
cb19c032 2400 else
7bab8ab5 2401 as_bad (_("bad argument to %s_check directive."), str);
d02603dc 2402 (void) restore_line_pointer (e);
cb19c032
L		 2403 }
2404 else
7bab8ab5 2405 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2406
2407 demand_empty_rest_of_line ();
2408}
2409
8a9036a4
L		 2410static void
2411check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2412 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2413{
2414#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2415 static const char *arch;
2416
2417 /* Intel LIOM is only supported on ELF. */
2418 if (!IS_ELF)
2419 return;
2420
2421 if (!arch)
2422 {
2423 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2424 use default_arch. */
2425 arch = cpu_arch_name;
2426 if (!arch)
2427 arch = default_arch;
2428 }
2429
81486035
L		 2430 /* If we are targeting Intel MCU, we must enable it. */
2431 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2432 || new_flag.bitfield.cpuiamcu)
2433 return;
2434
3632d14b 2435 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2436 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2437 || new_flag.bitfield.cpul1om)
8a9036a4 2438 return;
76ba9986 2439
7a9068fe
L		 2440 /* If we are targeting Intel K1OM, we must enable it. */
2441 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2442 || new_flag.bitfield.cpuk1om)
2443 return;
2444
8a9036a4
L		 2445 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2446#endif
2447}
2448
e413e4e9 2449static void
e3bb37b5 2450set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2451{
47926f60 2452 SKIP_WHITESPACE ();
e413e4e9 2453
29b0f896 2454 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9 2455 {
d02603dc
NC		 2456 char *string;
2457 int e = get_symbol_name (&string);
91d6fa6a 2458 unsigned int j;
40fb9820 2459 i386_cpu_flags flags;
e413e4e9 2460
91d6fa6a 2461 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2462 {
91d6fa6a 2463 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2464 {
91d6fa6a 2465 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2466
5c6af06e
JB		 2467 if (*string != '.')
2468 {
91d6fa6a 2469 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2470 cpu_sub_arch_name = NULL;
91d6fa6a 2471 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2472 if (flag_code == CODE_64BIT)
2473 {
2474 cpu_arch_flags.bitfield.cpu64 = 1;
2475 cpu_arch_flags.bitfield.cpuno64 = 0;
2476 }
2477 else
2478 {
2479 cpu_arch_flags.bitfield.cpu64 = 0;
2480 cpu_arch_flags.bitfield.cpuno64 = 1;
2481 }
91d6fa6a
NC		 2482 cpu_arch_isa = cpu_arch[j].type;
2483 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2484 if (!cpu_arch_tune_set)
2485 {
2486 cpu_arch_tune = cpu_arch_isa;
2487 cpu_arch_tune_flags = cpu_arch_isa_flags;
2488 }
5c6af06e
JB		 2489 break;
2490 }
40fb9820 2491
293f5f65
L		 2492 flags = cpu_flags_or (cpu_arch_flags,
2493 cpu_arch[j].flags);
81486035 2494
5b64d091 2495 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2496 {
6305a203
L		 2497 if (cpu_sub_arch_name)
2498 {
2499 char *name = cpu_sub_arch_name;
2500 cpu_sub_arch_name = concat (name,
91d6fa6a 2501 cpu_arch[j].name,
1bf57e9f 2502 (const char *) NULL);
6305a203
L		 2503 free (name);
2504 }
2505 else
91d6fa6a 2506 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2507 cpu_arch_flags = flags;
a586129e 2508 cpu_arch_isa_flags = flags;
5c6af06e 2509 }
d02603dc 2510 (void) restore_line_pointer (e);
5c6af06e
JB		 2511 demand_empty_rest_of_line ();
2512 return;
e413e4e9
AM		 2513 }
2514 }
293f5f65
L		 2515
2516 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2517 {
33eaf5de 2518 /* Disable an ISA extension. */
293f5f65
L		 2519 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2520 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2521 {
2522 flags = cpu_flags_and_not (cpu_arch_flags,
2523 cpu_noarch[j].flags);
2524 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2525 {
2526 if (cpu_sub_arch_name)
2527 {
2528 char *name = cpu_sub_arch_name;
2529 cpu_sub_arch_name = concat (name, string,
2530 (const char *) NULL);
2531 free (name);
2532 }
2533 else
2534 cpu_sub_arch_name = xstrdup (string);
2535 cpu_arch_flags = flags;
2536 cpu_arch_isa_flags = flags;
2537 }
2538 (void) restore_line_pointer (e);
2539 demand_empty_rest_of_line ();
2540 return;
2541 }
2542
2543 j = ARRAY_SIZE (cpu_arch);
2544 }
2545
91d6fa6a 2546 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2547 as_bad (_("no such architecture: `%s'"), string);
2548
2549 *input_line_pointer = e;
2550 }
2551 else
2552 as_bad (_("missing cpu architecture"));
2553
fddf5b5b
AM		 2554 no_cond_jump_promotion = 0;
2555 if (*input_line_pointer == ','
29b0f896 2556 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b 2557 {
d02603dc
NC		 2558 char *string;
2559 char e;
2560
2561 ++input_line_pointer;
2562 e = get_symbol_name (&string);
fddf5b5b
AM		 2563
2564 if (strcmp (string, "nojumps") == 0)
2565 no_cond_jump_promotion = 1;
2566 else if (strcmp (string, "jumps") == 0)
2567 ;
2568 else
2569 as_bad (_("no such architecture modifier: `%s'"), string);
2570
d02603dc 2571 (void) restore_line_pointer (e);
fddf5b5b
AM		 2572 }
2573
e413e4e9
AM		 2574 demand_empty_rest_of_line ();
2575}
2576
8a9036a4
L		 2577enum bfd_architecture
2578i386_arch (void)
2579{
3632d14b 2580 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2581 {
2582 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2583 || flag_code != CODE_64BIT)
2584 as_fatal (_("Intel L1OM is 64bit ELF only"));
2585 return bfd_arch_l1om;
2586 }
7a9068fe
L		 2587 else if (cpu_arch_isa == PROCESSOR_K1OM)
2588 {
2589 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2590 || flag_code != CODE_64BIT)
2591 as_fatal (_("Intel K1OM is 64bit ELF only"));
2592 return bfd_arch_k1om;
2593 }
81486035
L		 2594 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2595 {
2596 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2597 || flag_code == CODE_64BIT)
2598 as_fatal (_("Intel MCU is 32bit ELF only"));
2599 return bfd_arch_iamcu;
2600 }
8a9036a4
L		 2601 else
2602 return bfd_arch_i386;
2603}
2604
b9d79e03 2605unsigned long
7016a5d5 2606i386_mach (void)
b9d79e03 2607{
351f65ca 2608 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2609 {
3632d14b 2610 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2611 {
351f65ca
L		 2612 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2613 || default_arch[6] != '\0')
8a9036a4
L		 2614 as_fatal (_("Intel L1OM is 64bit ELF only"));
2615 return bfd_mach_l1om;
2616 }
7a9068fe
L		 2617 else if (cpu_arch_isa == PROCESSOR_K1OM)
2618 {
2619 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2620 || default_arch[6] != '\0')
2621 as_fatal (_("Intel K1OM is 64bit ELF only"));
2622 return bfd_mach_k1om;
2623 }
351f65ca 2624 else if (default_arch[6] == '\0')
8a9036a4 2625 return bfd_mach_x86_64;
351f65ca
L		 2626 else
2627 return bfd_mach_x64_32;
8a9036a4 2628 }
5197d474
L		 2629 else if (!strcmp (default_arch, "i386")
2630 || !strcmp (default_arch, "iamcu"))
81486035
L		 2631 {
2632 if (cpu_arch_isa == PROCESSOR_IAMCU)
2633 {
2634 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2635 as_fatal (_("Intel MCU is 32bit ELF only"));
2636 return bfd_mach_i386_iamcu;
2637 }
2638 else
2639 return bfd_mach_i386_i386;
2640 }
b9d79e03 2641 else
2b5d6a91 2642 as_fatal (_("unknown architecture"));
b9d79e03 2643}
b9d79e03 2644\f
252b5132 2645void
7016a5d5 2646md_begin (void)
252b5132
RH		 2647{
2648 const char *hash_err;
2649
86fa6981
L		 2650 /* Support pseudo prefixes like {disp32}. */
2651 lex_type ['{'] = LEX_BEGIN_NAME;
2652
47926f60 2653 /* Initialize op_hash hash table. */
252b5132
RH		 2654 op_hash = hash_new ();
2655
2656 {
d3ce72d0 2657 const insn_template *optab;
29b0f896 2658 templates *core_optab;
252b5132 2659
47926f60
KH		 2660 /* Setup for loop. */
2661 optab = i386_optab;
add39d23 2662 core_optab = XNEW (templates);
252b5132
RH		 2663 core_optab->start = optab;
2664
2665 while (1)
2666 {
2667 ++optab;
2668 if (optab->name == NULL
2669 || strcmp (optab->name, (optab - 1)->name) != 0)
2670 {
2671 /* different name --> ship out current template list;
47926f60 2672 add to hash table; & begin anew. */
252b5132
RH		 2673 core_optab->end = optab;
2674 hash_err = hash_insert (op_hash,
2675 (optab - 1)->name,
5a49b8ac 2676 (void *) core_optab);
252b5132
RH		 2677 if (hash_err)
2678 {
b37df7c4 2679 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2680 (optab - 1)->name,
2681 hash_err);
2682 }
2683 if (optab->name == NULL)
2684 break;
add39d23 2685 core_optab = XNEW (templates);
252b5132
RH		 2686 core_optab->start = optab;
2687 }
2688 }
2689 }
2690
47926f60 2691 /* Initialize reg_hash hash table. */
252b5132
RH		 2692 reg_hash = hash_new ();
2693 {
29b0f896 2694 const reg_entry *regtab;
c3fe08fa 2695 unsigned int regtab_size = i386_regtab_size;
252b5132 2696
c3fe08fa 2697 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2698 {
5a49b8ac 2699 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2700 if (hash_err)
b37df7c4 2701 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2702 regtab->reg_name,
2703 hash_err);
252b5132
RH		 2704 }
2705 }
2706
47926f60 2707 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2708 {
29b0f896
AM		 2709 int c;
2710 char *p;
252b5132
RH		 2711
2712 for (c = 0; c < 256; c++)
2713 {
3882b010 2714 if (ISDIGIT (c))
252b5132
RH		 2715 {
2716 digit_chars[c] = c;
2717 mnemonic_chars[c] = c;
2718 register_chars[c] = c;
2719 operand_chars[c] = c;
2720 }
3882b010 2721 else if (ISLOWER (c))
252b5132
RH		 2722 {
2723 mnemonic_chars[c] = c;
2724 register_chars[c] = c;
2725 operand_chars[c] = c;
2726 }
3882b010 2727 else if (ISUPPER (c))
252b5132 2728 {
3882b010 2729 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2730 register_chars[c] = mnemonic_chars[c];
2731 operand_chars[c] = c;
2732 }
43234a1e 2733 else if (c == '{' || c == '}')
86fa6981
L		 2734 {
2735 mnemonic_chars[c] = c;
2736 operand_chars[c] = c;
2737 }
252b5132 2738
3882b010 2739 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2740 identifier_chars[c] = c;
2741 else if (c >= 128)
2742 {
2743 identifier_chars[c] = c;
2744 operand_chars[c] = c;
2745 }
2746 }
2747
2748#ifdef LEX_AT
2749 identifier_chars['@'] = '@';
32137342
NC		 2750#endif
2751#ifdef LEX_QM
2752 identifier_chars['?'] = '?';
2753 operand_chars['?'] = '?';
252b5132 2754#endif
252b5132 2755 digit_chars['-'] = '-';
c0f3af97 2756 mnemonic_chars['_'] = '_';
791fe849 2757 mnemonic_chars['-'] = '-';
0003779b 2758 mnemonic_chars['.'] = '.';
252b5132
RH		 2759 identifier_chars['_'] = '_';
2760 identifier_chars['.'] = '.';
2761
2762 for (p = operand_special_chars; *p != '\0'; p++)
2763 operand_chars[(unsigned char) *p] = *p;
2764 }
2765
a4447b93
RH		 2766 if (flag_code == CODE_64BIT)
2767 {
ca19b261
KT		 2768#if defined (OBJ_COFF) && defined (TE_PE)
2769 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2770 ? 32 : 16);
2771#else
a4447b93 2772 x86_dwarf2_return_column = 16;
ca19b261 2773#endif
61ff971f 2774 x86_cie_data_alignment = -8;
a4447b93
RH		 2775 }
2776 else
2777 {
2778 x86_dwarf2_return_column = 8;
2779 x86_cie_data_alignment = -4;
2780 }
252b5132
RH		 2781}
2782
2783void
e3bb37b5 2784i386_print_statistics (FILE *file)
252b5132
RH		 2785{
2786 hash_print_statistics (file, "i386 opcode", op_hash);
2787 hash_print_statistics (file, "i386 register", reg_hash);
2788}
2789\f
252b5132
RH		 2790#ifdef DEBUG386
2791
ce8a8b2f 2792/* Debugging routines for md_assemble. */
d3ce72d0 2793static void pte (insn_template *);
40fb9820 2794static void pt (i386_operand_type);
e3bb37b5
L		 2795static void pe (expressionS *);
2796static void ps (symbolS *);
252b5132
RH		 2797
2798static void
e3bb37b5 2799pi (char *line, i386_insn *x)
252b5132 2800{
09137c09 2801 unsigned int j;
252b5132
RH		 2802
2803 fprintf (stdout, "%s: template ", line);
2804 pte (&x->tm);
09f131f2
JH		 2805 fprintf (stdout, " address: base %s index %s scale %x\n",
2806 x->base_reg ? x->base_reg->reg_name : "none",
2807 x->index_reg ? x->index_reg->reg_name : "none",
2808 x->log2_scale_factor);
2809 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2810 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2811 fprintf (stdout, " sib: base %x index %x scale %x\n",
2812 x->sib.base, x->sib.index, x->sib.scale);
2813 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2814 (x->rex & REX_W) != 0,
2815 (x->rex & REX_R) != 0,
2816 (x->rex & REX_X) != 0,
2817 (x->rex & REX_B) != 0);
09137c09 2818 for (j = 0; j < x->operands; j++)
252b5132 2819 {
09137c09
SP		 2820 fprintf (stdout, " #%d: ", j + 1);
2821 pt (x->types[j]);
252b5132 2822 fprintf (stdout, "\n");
09137c09
SP		 2823 if (x->types[j].bitfield.reg8
2824 || x->types[j].bitfield.reg16
2825 || x->types[j].bitfield.reg32
2826 || x->types[j].bitfield.reg64
2827 || x->types[j].bitfield.regmmx
2828 || x->types[j].bitfield.regxmm
2829 || x->types[j].bitfield.regymm
43234a1e 2830 || x->types[j].bitfield.regzmm
09137c09
SP		 2831 || x->types[j].bitfield.sreg2
2832 || x->types[j].bitfield.sreg3
2833 || x->types[j].bitfield.control
2834 || x->types[j].bitfield.debug
2835 || x->types[j].bitfield.test)
2836 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2837 if (operand_type_check (x->types[j], imm))
2838 pe (x->op[j].imms);
2839 if (operand_type_check (x->types[j], disp))
2840 pe (x->op[j].disps);
252b5132
RH		 2841 }
2842}
2843
2844static void
d3ce72d0 2845pte (insn_template *t)
252b5132 2846{
09137c09 2847 unsigned int j;
252b5132 2848 fprintf (stdout, " %d operands ", t->operands);
47926f60 2849 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2850 if (t->extension_opcode != None)
2851 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2852 if (t->opcode_modifier.d)
252b5132 2853 fprintf (stdout, "D");
40fb9820 2854 if (t->opcode_modifier.w)
252b5132
RH		 2855 fprintf (stdout, "W");
2856 fprintf (stdout, "\n");
09137c09 2857 for (j = 0; j < t->operands; j++)
252b5132 2858 {
09137c09
SP		 2859 fprintf (stdout, " #%d type ", j + 1);
2860 pt (t->operand_types[j]);
252b5132
RH		 2861 fprintf (stdout, "\n");
2862 }
2863}
2864
2865static void
e3bb37b5 2866pe (expressionS *e)
252b5132 2867{
24eab124 2868 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2869 fprintf (stdout, " add_number %ld (%lx)\n",
2870 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2871 if (e->X_add_symbol)
2872 {
2873 fprintf (stdout, " add_symbol ");
2874 ps (e->X_add_symbol);
2875 fprintf (stdout, "\n");
2876 }
2877 if (e->X_op_symbol)
2878 {
2879 fprintf (stdout, " op_symbol ");
2880 ps (e->X_op_symbol);
2881 fprintf (stdout, "\n");
2882 }
2883}
2884
2885static void
e3bb37b5 2886ps (symbolS *s)
252b5132
RH		 2887{
2888 fprintf (stdout, "%s type %s%s",
2889 S_GET_NAME (s),
2890 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2891 segment_name (S_GET_SEGMENT (s)));
2892}
2893
7b81dfbb 2894static struct type_name
252b5132 2895 {
40fb9820
L		 2896 i386_operand_type mask;
2897 const char *name;
252b5132 2898 }
7b81dfbb 2899const type_names[] =
252b5132 2900{
40fb9820
L		 2901 { OPERAND_TYPE_REG8, "r8" },
2902 { OPERAND_TYPE_REG16, "r16" },
2903 { OPERAND_TYPE_REG32, "r32" },
2904 { OPERAND_TYPE_REG64, "r64" },
2905 { OPERAND_TYPE_IMM8, "i8" },
2906 { OPERAND_TYPE_IMM8, "i8s" },
2907 { OPERAND_TYPE_IMM16, "i16" },
2908 { OPERAND_TYPE_IMM32, "i32" },
2909 { OPERAND_TYPE_IMM32S, "i32s" },
2910 { OPERAND_TYPE_IMM64, "i64" },
2911 { OPERAND_TYPE_IMM1, "i1" },
2912 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2913 { OPERAND_TYPE_DISP8, "d8" },
2914 { OPERAND_TYPE_DISP16, "d16" },
2915 { OPERAND_TYPE_DISP32, "d32" },
2916 { OPERAND_TYPE_DISP32S, "d32s" },
2917 { OPERAND_TYPE_DISP64, "d64" },
43234a1e 2918 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
40fb9820
L		 2919 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2920 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2921 { OPERAND_TYPE_CONTROL, "control reg" },
2922 { OPERAND_TYPE_TEST, "test reg" },
2923 { OPERAND_TYPE_DEBUG, "debug reg" },
2924 { OPERAND_TYPE_FLOATREG, "FReg" },
2925 { OPERAND_TYPE_FLOATACC, "FAcc" },
2926 { OPERAND_TYPE_SREG2, "SReg2" },
2927 { OPERAND_TYPE_SREG3, "SReg3" },
2928 { OPERAND_TYPE_ACC, "Acc" },
2929 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2930 { OPERAND_TYPE_REGMMX, "rMMX" },
2931 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2932 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2933 { OPERAND_TYPE_REGZMM, "rZMM" },
2934 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2935 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2936};
2937
2938static void
40fb9820 2939pt (i386_operand_type t)
252b5132 2940{
40fb9820 2941 unsigned int j;
c6fb90c8 2942 i386_operand_type a;
252b5132 2943
40fb9820 2944 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2945 {
2946 a = operand_type_and (t, type_names[j].mask);
0349dc08 2947 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2948 fprintf (stdout, "%s, ", type_names[j].name);
2949 }
252b5132
RH		 2950 fflush (stdout);
2951}
2952
2953#endif /* DEBUG386 */
2954\f
252b5132 2955static bfd_reloc_code_real_type
3956db08 2956reloc (unsigned int size,
64e74474
AM		 2957 int pcrel,
2958 int sign,
2959 bfd_reloc_code_real_type other)
252b5132 2960{
47926f60 2961 if (other != NO_RELOC)
3956db08 2962 {
91d6fa6a 2963 reloc_howto_type *rel;
3956db08
JB		 2964
2965 if (size == 8)
2966 switch (other)
2967 {
64e74474
AM		 2968 case BFD_RELOC_X86_64_GOT32:
2969 return BFD_RELOC_X86_64_GOT64;
2970 break;
553d1284
L		 2971 case BFD_RELOC_X86_64_GOTPLT64:
2972 return BFD_RELOC_X86_64_GOTPLT64;
2973 break;
64e74474
AM		 2974 case BFD_RELOC_X86_64_PLTOFF64:
2975 return BFD_RELOC_X86_64_PLTOFF64;
2976 break;
2977 case BFD_RELOC_X86_64_GOTPC32:
2978 other = BFD_RELOC_X86_64_GOTPC64;
2979 break;
2980 case BFD_RELOC_X86_64_GOTPCREL:
2981 other = BFD_RELOC_X86_64_GOTPCREL64;
2982 break;
2983 case BFD_RELOC_X86_64_TPOFF32:
2984 other = BFD_RELOC_X86_64_TPOFF64;
2985 break;
2986 case BFD_RELOC_X86_64_DTPOFF32:
2987 other = BFD_RELOC_X86_64_DTPOFF64;
2988 break;
2989 default:
2990 break;
3956db08 2991 }
e05278af 2992
8ce3d284 2993#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2994 if (other == BFD_RELOC_SIZE32)
2995 {
2996 if (size == 8)
1ab668bf 2997 other = BFD_RELOC_SIZE64;
8fd4256d 2998 if (pcrel)
1ab668bf
AM		 2999 {
3000 as_bad (_("there are no pc-relative size relocations"));
3001 return NO_RELOC;
3002 }
8fd4256d 3003 }
8ce3d284 3004#endif
8fd4256d 3005
e05278af 3006 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 3007 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 3008 sign = -1;
3009
91d6fa6a
NC		 3010 rel = bfd_reloc_type_lookup (stdoutput, other);
3011 if (!rel)
3956db08 3012 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 3013 else if (size != bfd_get_reloc_size (rel))
3956db08 3014 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 3015 bfd_get_reloc_size (rel),
3956db08 3016 size);
91d6fa6a 3017 else if (pcrel && !rel->pc_relative)
3956db08 3018 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 3019 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 3020 && !sign)
91d6fa6a 3021 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 3022 && sign > 0))
3956db08
JB		 3023 as_bad (_("relocated field and relocation type differ in signedness"));
3024 else
3025 return other;
3026 return NO_RELOC;
3027 }
252b5132
RH		 3028
3029 if (pcrel)
3030 {
3e73aa7c 3031 if (!sign)
3956db08 3032 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 3033 switch (size)
3034 {
3035 case 1: return BFD_RELOC_8_PCREL;
3036 case 2: return BFD_RELOC_16_PCREL;
d258b828 3037 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 3038 case 8: return BFD_RELOC_64_PCREL;
252b5132 3039 }
3956db08 3040 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 3041 }
3042 else
3043 {
3956db08 3044 if (sign > 0)
e5cb08ac 3045 switch (size)
3e73aa7c
JH		 3046 {
3047 case 4: return BFD_RELOC_X86_64_32S;
3048 }
3049 else
3050 switch (size)
3051 {
3052 case 1: return BFD_RELOC_8;
3053 case 2: return BFD_RELOC_16;
3054 case 4: return BFD_RELOC_32;
3055 case 8: return BFD_RELOC_64;
3056 }
3956db08
JB		 3057 as_bad (_("cannot do %s %u byte relocation"),
3058 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 3059 }
3060
0cc9e1d3 3061 return NO_RELOC;
252b5132
RH		 3062}
3063
47926f60
KH		 3064/* Here we decide which fixups can be adjusted to make them relative to
3065 the beginning of the section instead of the symbol. Basically we need
3066 to make sure that the dynamic relocations are done correctly, so in
3067 some cases we force the original symbol to be used. */
3068
252b5132 3069int
e3bb37b5 3070tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 3071{
6d249963 3072#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 3073 if (!IS_ELF)
31312f95
AM		 3074 return 1;
3075
a161fe53
AM		 3076 /* Don't adjust pc-relative references to merge sections in 64-bit
3077 mode. */
3078 if (use_rela_relocations
3079 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3080 && fixP->fx_pcrel)
252b5132 3081 return 0;
31312f95 3082
8d01d9a9
AJ		 3083 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3084 and changed later by validate_fix. */
3085 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3086 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3087 return 0;
3088
8fd4256d
L		 3089 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3090 for size relocations. */
3091 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3092 || fixP->fx_r_type == BFD_RELOC_SIZE64
3093 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 3094 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3095 || fixP->fx_r_type == BFD_RELOC_386_GOT32
02a86693 3096 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
13ae64f3
JJ		 3097 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3098 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3099 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3100 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 3101 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3102 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 3103 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3104 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 3105 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3106 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 3107 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3108 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 3109 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
56ceb5b5
L		 3110 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3111 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
bffbf940
JJ		 3112 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3113 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3114 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 3115 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 3116 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3117 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 3118 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3119 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 3120 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3121 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 3122 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3123 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3124 return 0;
31312f95 3125#endif
252b5132
RH		 3126 return 1;
3127}
252b5132 3128
b4cac588 3129static int
e3bb37b5 3130intel_float_operand (const char *mnemonic)
252b5132 3131{
9306ca4a
JB		 3132 /* Note that the value returned is meaningful only for opcodes with (memory)
3133 operands, hence the code here is free to improperly handle opcodes that
3134 have no operands (for better performance and smaller code). */
3135
3136 if (mnemonic[0] != 'f')
3137 return 0; /* non-math */
3138
3139 switch (mnemonic[1])
3140 {
3141 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3142 the fs segment override prefix not currently handled because no
3143 call path can make opcodes without operands get here */
3144 case 'i':
3145 return 2 /* integer op */;
3146 case 'l':
3147 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3148 return 3; /* fldcw/fldenv */
3149 break;
3150 case 'n':
3151 if (mnemonic[2] != 'o' /* fnop */)
3152 return 3; /* non-waiting control op */
3153 break;
3154 case 'r':
3155 if (mnemonic[2] == 's')
3156 return 3; /* frstor/frstpm */
3157 break;
3158 case 's':
3159 if (mnemonic[2] == 'a')
3160 return 3; /* fsave */
3161 if (mnemonic[2] == 't')
3162 {
3163 switch (mnemonic[3])
3164 {
3165 case 'c': /* fstcw */
3166 case 'd': /* fstdw */
3167 case 'e': /* fstenv */
3168 case 's': /* fsts[gw] */
3169 return 3;
3170 }
3171 }
3172 break;
3173 case 'x':
3174 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3175 return 0; /* fxsave/fxrstor are not really math ops */
3176 break;
3177 }
252b5132 3178
9306ca4a 3179 return 1;
252b5132
RH		 3180}
3181
c0f3af97
L		 3182/* Build the VEX prefix. */
3183
3184static void
d3ce72d0 3185build_vex_prefix (const insn_template *t)
c0f3af97
L		 3186{
3187 unsigned int register_specifier;
3188 unsigned int implied_prefix;
3189 unsigned int vector_length;
3190
3191 /* Check register specifier. */
3192 if (i.vex.register_specifier)
43234a1e
L		 3193 {
3194 register_specifier =
3195 ~register_number (i.vex.register_specifier) & 0xf;
3196 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3197 }
c0f3af97
L		 3198 else
3199 register_specifier = 0xf;
3200
33eaf5de 3201 /* Use 2-byte VEX prefix by swapping destination and source
fa99fab2 3202 operand. */
86fa6981
L		 3203 if (i.vec_encoding != vex_encoding_vex3
3204 && i.dir_encoding == dir_encoding_default
fa99fab2 3205 && i.operands == i.reg_operands
7f399153 3206 && i.tm.opcode_modifier.vexopcode == VEX0F
86fa6981 3207 && i.tm.opcode_modifier.load
fa99fab2
L		 3208 && i.rex == REX_B)
3209 {
3210 unsigned int xchg = i.operands - 1;
3211 union i386_op temp_op;
3212 i386_operand_type temp_type;
3213
3214 temp_type = i.types[xchg];
3215 i.types[xchg] = i.types[0];
3216 i.types[0] = temp_type;
3217 temp_op = i.op[xchg];
3218 i.op[xchg] = i.op[0];
3219 i.op[0] = temp_op;
3220
9c2799c2 3221 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3222
3223 i.rex = REX_R;
3224 xchg = i.rm.regmem;
3225 i.rm.regmem = i.rm.reg;
3226 i.rm.reg = xchg;
3227
3228 /* Use the next insn. */
3229 i.tm = t[1];
3230 }
3231
539f890d
L		 3232 if (i.tm.opcode_modifier.vex == VEXScalar)
3233 vector_length = avxscalar;
3234 else
3235 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3236
3237 switch ((i.tm.base_opcode >> 8) & 0xff)
3238 {
3239 case 0:
3240 implied_prefix = 0;
3241 break;
3242 case DATA_PREFIX_OPCODE:
3243 implied_prefix = 1;
3244 break;
3245 case REPE_PREFIX_OPCODE:
3246 implied_prefix = 2;
3247 break;
3248 case REPNE_PREFIX_OPCODE:
3249 implied_prefix = 3;
3250 break;
3251 default:
3252 abort ();
3253 }
3254
3255 /* Use 2-byte VEX prefix if possible. */
86fa6981
L		 3256 if (i.vec_encoding != vex_encoding_vex3
3257 && i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3258 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3259 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3260 {
3261 /* 2-byte VEX prefix. */
3262 unsigned int r;
3263
3264 i.vex.length = 2;
3265 i.vex.bytes[0] = 0xc5;
3266
3267 /* Check the REX.R bit. */
3268 r = (i.rex & REX_R) ? 0 : 1;
3269 i.vex.bytes[1] = (r << 7
3270 | register_specifier << 3
3271 | vector_length << 2
3272 | implied_prefix);
3273 }
3274 else
3275 {
3276 /* 3-byte VEX prefix. */
3277 unsigned int m, w;
3278
f88c9eb0 3279 i.vex.length = 3;
f88c9eb0 3280
7f399153 3281 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3282 {
7f399153
L		 3283 case VEX0F:
3284 m = 0x1;
80de6e00 3285 i.vex.bytes[0] = 0xc4;
7f399153
L		 3286 break;
3287 case VEX0F38:
3288 m = 0x2;
80de6e00 3289 i.vex.bytes[0] = 0xc4;
7f399153
L		 3290 break;
3291 case VEX0F3A:
3292 m = 0x3;
80de6e00 3293 i.vex.bytes[0] = 0xc4;
7f399153
L		 3294 break;
3295 case XOP08:
5dd85c99
SP		 3296 m = 0x8;
3297 i.vex.bytes[0] = 0x8f;
7f399153
L		 3298 break;
3299 case XOP09:
f88c9eb0
SP		 3300 m = 0x9;
3301 i.vex.bytes[0] = 0x8f;
7f399153
L		 3302 break;
3303 case XOP0A:
f88c9eb0
SP		 3304 m = 0xa;
3305 i.vex.bytes[0] = 0x8f;
7f399153
L		 3306 break;
3307 default:
3308 abort ();
f88c9eb0 3309 }
c0f3af97 3310
c0f3af97
L		 3311 /* The high 3 bits of the second VEX byte are 1's compliment
3312 of RXB bits from REX. */
3313 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3314
3315 /* Check the REX.W bit. */
3316 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3317 if (i.tm.opcode_modifier.vexw == VEXW1)
3318 w = 1;
c0f3af97
L		 3319
3320 i.vex.bytes[2] = (w << 7
3321 | register_specifier << 3
3322 | vector_length << 2
3323 | implied_prefix);
3324 }
3325}
3326
43234a1e
L		 3327/* Build the EVEX prefix. */
3328
3329static void
3330build_evex_prefix (void)
3331{
3332 unsigned int register_specifier;
3333 unsigned int implied_prefix;
3334 unsigned int m, w;
3335 rex_byte vrex_used = 0;
3336
3337 /* Check register specifier. */
3338 if (i.vex.register_specifier)
3339 {
3340 gas_assert ((i.vrex & REX_X) == 0);
3341
3342 register_specifier = i.vex.register_specifier->reg_num;
3343 if ((i.vex.register_specifier->reg_flags & RegRex))
3344 register_specifier += 8;
3345 /* The upper 16 registers are encoded in the fourth byte of the
3346 EVEX prefix. */
3347 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3348 i.vex.bytes[3] = 0x8;
3349 register_specifier = ~register_specifier & 0xf;
3350 }
3351 else
3352 {
3353 register_specifier = 0xf;
3354
3355 /* Encode upper 16 vector index register in the fourth byte of
3356 the EVEX prefix. */
3357 if (!(i.vrex & REX_X))
3358 i.vex.bytes[3] = 0x8;
3359 else
3360 vrex_used |= REX_X;
3361 }
3362
3363 switch ((i.tm.base_opcode >> 8) & 0xff)
3364 {
3365 case 0:
3366 implied_prefix = 0;
3367 break;
3368 case DATA_PREFIX_OPCODE:
3369 implied_prefix = 1;
3370 break;
3371 case REPE_PREFIX_OPCODE:
3372 implied_prefix = 2;
3373 break;
3374 case REPNE_PREFIX_OPCODE:
3375 implied_prefix = 3;
3376 break;
3377 default:
3378 abort ();
3379 }
3380
3381 /* 4 byte EVEX prefix. */
3382 i.vex.length = 4;
3383 i.vex.bytes[0] = 0x62;
3384
3385 /* mmmm bits. */
3386 switch (i.tm.opcode_modifier.vexopcode)
3387 {
3388 case VEX0F:
3389 m = 1;
3390 break;
3391 case VEX0F38:
3392 m = 2;
3393 break;
3394 case VEX0F3A:
3395 m = 3;
3396 break;
3397 default:
3398 abort ();
3399 break;
3400 }
3401
3402 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3403 bits from REX. */
3404 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3405
3406 /* The fifth bit of the second EVEX byte is 1's compliment of the
3407 REX_R bit in VREX. */
3408 if (!(i.vrex & REX_R))
3409 i.vex.bytes[1] |= 0x10;
3410 else
3411 vrex_used |= REX_R;
3412
3413 if ((i.reg_operands + i.imm_operands) == i.operands)
3414 {
3415 /* When all operands are registers, the REX_X bit in REX is not
3416 used. We reuse it to encode the upper 16 registers, which is
3417 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3418 as 1's compliment. */
3419 if ((i.vrex & REX_B))
3420 {
3421 vrex_used |= REX_B;
3422 i.vex.bytes[1] &= ~0x40;
3423 }
3424 }
3425
3426 /* EVEX instructions shouldn't need the REX prefix. */
3427 i.vrex &= ~vrex_used;
3428 gas_assert (i.vrex == 0);
3429
3430 /* Check the REX.W bit. */
3431 w = (i.rex & REX_W) ? 1 : 0;
3432 if (i.tm.opcode_modifier.vexw)
3433 {
3434 if (i.tm.opcode_modifier.vexw == VEXW1)
3435 w = 1;
3436 }
3437 /* If w is not set it means we are dealing with WIG instruction. */
3438 else if (!w)
3439 {
3440 if (evexwig == evexw1)
3441 w = 1;
3442 }
3443
3444 /* Encode the U bit. */
3445 implied_prefix |= 0x4;
3446
3447 /* The third byte of the EVEX prefix. */
3448 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3449
3450 /* The fourth byte of the EVEX prefix. */
3451 /* The zeroing-masking bit. */
3452 if (i.mask && i.mask->zeroing)
3453 i.vex.bytes[3] |= 0x80;
3454
3455 /* Don't always set the broadcast bit if there is no RC. */
3456 if (!i.rounding)
3457 {
3458 /* Encode the vector length. */
3459 unsigned int vec_length;
3460
3461 switch (i.tm.opcode_modifier.evex)
3462 {
3463 case EVEXLIG: /* LL' is ignored */
3464 vec_length = evexlig << 5;
3465 break;
3466 case EVEX128:
3467 vec_length = 0 << 5;
3468 break;
3469 case EVEX256:
3470 vec_length = 1 << 5;
3471 break;
3472 case EVEX512:
3473 vec_length = 2 << 5;
3474 break;
3475 default:
3476 abort ();
3477 break;
3478 }
3479 i.vex.bytes[3] |= vec_length;
3480 /* Encode the broadcast bit. */
3481 if (i.broadcast)
3482 i.vex.bytes[3] |= 0x10;
3483 }
3484 else
3485 {
3486 if (i.rounding->type != saeonly)
3487 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3488 else
d3d3c6db 3489 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3490 }
3491
3492 if (i.mask && i.mask->mask)
3493 i.vex.bytes[3] |= i.mask->mask->reg_num;
3494}
3495
65da13b5
L		 3496static void
3497process_immext (void)
3498{
3499 expressionS *exp;
3500
4c692bc7
JB		 3501 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3502 && i.operands > 0)
65da13b5 3503 {
4c692bc7
JB		 3504 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3505 with an opcode suffix which is coded in the same place as an
3506 8-bit immediate field would be.
3507 Here we check those operands and remove them afterwards. */
65da13b5
L		 3508 unsigned int x;
3509
3510 for (x = 0; x < i.operands; x++)
4c692bc7 3511 if (register_number (i.op[x].regs) != x)
65da13b5 3512 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3513 register_prefix, i.op[x].regs->reg_name, x + 1,
3514 i.tm.name);
3515
3516 i.operands = 0;
65da13b5
L		 3517 }
3518
9916071f
AP		 3519 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3520 {
3521 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3522 suffix which is coded in the same place as an 8-bit immediate
3523 field would be.
3524 Here we check those operands and remove them afterwards. */
3525 unsigned int x;
3526
3527 if (i.operands != 3)
3528 abort();
3529
3530 for (x = 0; x < 2; x++)
3531 if (register_number (i.op[x].regs) != x)
3532 goto bad_register_operand;
3533
3534 /* Check for third operand for mwaitx/monitorx insn. */
3535 if (register_number (i.op[x].regs)
3536 != (x + (i.tm.extension_opcode == 0xfb)))
3537 {
3538bad_register_operand:
3539 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3540 register_prefix, i.op[x].regs->reg_name, x+1,
3541 i.tm.name);
3542 }
3543
3544 i.operands = 0;
3545 }
3546
c0f3af97 3547 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3548 which is coded in the same place as an 8-bit immediate field
3549 would be. Here we fake an 8-bit immediate operand from the
3550 opcode suffix stored in tm.extension_opcode.
3551
c1e679ec 3552 AVX instructions also use this encoding, for some of
c0f3af97 3553 3 argument instructions. */
65da13b5 3554
43234a1e 3555 gas_assert (i.imm_operands <= 1
7ab9ffdd 3556 && (i.operands <= 2
43234a1e
L		 3557 || ((i.tm.opcode_modifier.vex
3558 || i.tm.opcode_modifier.evex)
7ab9ffdd 3559 && i.operands <= 4)));
65da13b5
L		 3560
3561 exp = &im_expressions[i.imm_operands++];
3562 i.op[i.operands].imms = exp;
3563 i.types[i.operands] = imm8;
3564 i.operands++;
3565 exp->X_op = O_constant;
3566 exp->X_add_number = i.tm.extension_opcode;
3567 i.tm.extension_opcode = None;
3568}
3569
42164a71
L		 3570
3571static int
3572check_hle (void)
3573{
3574 switch (i.tm.opcode_modifier.hleprefixok)
3575 {
3576 default:
3577 abort ();
82c2def5 3578 case HLEPrefixNone:
165de32a
L		 3579 as_bad (_("invalid instruction `%s' after `%s'"),
3580 i.tm.name, i.hle_prefix);
42164a71 3581 return 0;
82c2def5 3582 case HLEPrefixLock:
42164a71
L		 3583 if (i.prefix[LOCK_PREFIX])
3584 return 1;
165de32a 3585 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3586 return 0;
82c2def5 3587 case HLEPrefixAny:
42164a71 3588 return 1;
82c2def5 3589 case HLEPrefixRelease:
42164a71
L		 3590 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3591 {
3592 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3593 i.tm.name);
3594 return 0;
3595 }
3596 if (i.mem_operands == 0
3597 || !operand_type_check (i.types[i.operands - 1], anymem))
3598 {
3599 as_bad (_("memory destination needed for instruction `%s'"
3600 " after `xrelease'"), i.tm.name);
3601 return 0;
3602 }
3603 return 1;
3604 }
3605}
3606
252b5132
RH		 3607/* This is the guts of the machine-dependent assembler. LINE points to a
3608 machine dependent instruction. This function is supposed to emit
3609 the frags/bytes it assembles to. */
3610
3611void
65da13b5 3612md_assemble (char *line)
252b5132 3613{
40fb9820 3614 unsigned int j;
83b16ac6 3615 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
d3ce72d0 3616 const insn_template *t;
252b5132 3617
47926f60 3618 /* Initialize globals. */
252b5132
RH		 3619 memset (&i, '\0', sizeof (i));
3620 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3621 i.reloc[j] = NO_RELOC;
252b5132
RH		 3622 memset (disp_expressions, '\0', sizeof (disp_expressions));
3623 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3624 save_stack_p = save_stack;
252b5132
RH		 3625
3626 /* First parse an instruction mnemonic & call i386_operand for the operands.
3627 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3628 start of a (possibly prefixed) mnemonic. */
252b5132 3629
29b0f896
AM		 3630 line = parse_insn (line, mnemonic);
3631 if (line == NULL)
3632 return;
83b16ac6 3633 mnem_suffix = i.suffix;
252b5132 3634
29b0f896 3635 line = parse_operands (line, mnemonic);
ee86248c 3636 this_operand = -1;
8325cc63
JB		 3637 xfree (i.memop1_string);
3638 i.memop1_string = NULL;
29b0f896
AM		 3639 if (line == NULL)
3640 return;
252b5132 3641
29b0f896
AM		 3642 /* Now we've parsed the mnemonic into a set of templates, and have the
3643 operands at hand. */
3644
3645 /* All intel opcodes have reversed operands except for "bound" and
3646 "enter". We also don't reverse intersegment "jmp" and "call"
3647 instructions with 2 immediate operands so that the immediate segment
050dfa73 3648 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3649 if (intel_syntax
3650 && i.operands > 1
29b0f896 3651 && (strcmp (mnemonic, "bound") != 0)
30123838 3652 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3653 && !(operand_type_check (i.types[0], imm)
3654 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3655 swap_operands ();
3656
ec56d5c0
JB		 3657 /* The order of the immediates should be reversed
3658 for 2 immediates extrq and insertq instructions */
3659 if (i.imm_operands == 2
3660 && (strcmp (mnemonic, "extrq") == 0
3661 || strcmp (mnemonic, "insertq") == 0))
3662 swap_2_operands (0, 1);
3663
29b0f896
AM		 3664 if (i.imm_operands)
3665 optimize_imm ();
3666
b300c311
L		 3667 /* Don't optimize displacement for movabs since it only takes 64bit
3668 displacement. */
3669 if (i.disp_operands
a501d77e 3670 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3671 && (flag_code != CODE_64BIT
3672 || strcmp (mnemonic, "movabs") != 0))
3673 optimize_disp ();
29b0f896
AM		 3674
3675 /* Next, we find a template that matches the given insn,
3676 making sure the overlap of the given operands types is consistent
3677 with the template operand types. */
252b5132 3678
83b16ac6 3679 if (!(t = match_template (mnem_suffix)))
29b0f896 3680 return;
252b5132 3681
7bab8ab5 3682 if (sse_check != check_none
81f8a913 3683 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3684 && (i.tm.cpu_flags.bitfield.cpusse
3685 || i.tm.cpu_flags.bitfield.cpusse2
3686 || i.tm.cpu_flags.bitfield.cpusse3
3687 || i.tm.cpu_flags.bitfield.cpussse3
3688 || i.tm.cpu_flags.bitfield.cpusse4_1
3689 || i.tm.cpu_flags.bitfield.cpusse4_2))
3690 {
7bab8ab5 3691 (sse_check == check_warning
daf50ae7
L		 3692 ? as_warn
3693 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3694 }
3695
321fd21e
L		 3696 /* Zap movzx and movsx suffix. The suffix has been set from
3697 "word ptr" or "byte ptr" on the source operand in Intel syntax
3698 or extracted from mnemonic in AT&T syntax. But we'll use
3699 the destination register to choose the suffix for encoding. */
3700 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3701 {
321fd21e
L		 3702 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3703 there is no suffix, the default will be byte extension. */
3704 if (i.reg_operands != 2
3705 && !i.suffix
7ab9ffdd 3706 && intel_syntax)
321fd21e
L		 3707 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3708
3709 i.suffix = 0;
cd61ebfe 3710 }
24eab124 3711
40fb9820 3712 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3713 if (!add_prefix (FWAIT_OPCODE))
3714 return;
252b5132 3715
d5de92cf
L		 3716 /* Check if REP prefix is OK. */
3717 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3718 {
3719 as_bad (_("invalid instruction `%s' after `%s'"),
3720 i.tm.name, i.rep_prefix);
3721 return;
3722 }
3723
c1ba0266
L		 3724 /* Check for lock without a lockable instruction. Destination operand
3725 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3726 if (i.prefix[LOCK_PREFIX]
3727 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3728 || i.mem_operands == 0
3729 || (i.tm.base_opcode != 0x86
3730 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3731 {
3732 as_bad (_("expecting lockable instruction after `lock'"));
3733 return;
3734 }
3735
42164a71 3736 /* Check if HLE prefix is OK. */
165de32a 3737 if (i.hle_prefix && !check_hle ())
42164a71
L		 3738 return;
3739
7e8b059b
L		 3740 /* Check BND prefix. */
3741 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3742 as_bad (_("expecting valid branch instruction after `bnd'"));
3743
04ef582a 3744 /* Check NOTRACK prefix. */
9fef80d6
L		 3745 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
3746 as_bad (_("expecting indirect branch instruction after `notrack'"));
04ef582a 3747
327e8c42
JB		 3748 if (i.tm.cpu_flags.bitfield.cpumpx)
3749 {
3750 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
3751 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3752 else if (flag_code != CODE_16BIT
3753 ? i.prefix[ADDR_PREFIX]
3754 : i.mem_operands && !i.prefix[ADDR_PREFIX])
3755 as_bad (_("16-bit address isn't allowed in MPX instructions"));
3756 }
7e8b059b
L		 3757
3758 /* Insert BND prefix. */
3759 if (add_bnd_prefix
3760 && i.tm.opcode_modifier.bndprefixok
3761 && !i.prefix[BND_PREFIX])
3762 add_prefix (BND_PREFIX_OPCODE);
3763
29b0f896 3764 /* Check string instruction segment overrides. */
40fb9820 3765 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3766 {
3767 if (!check_string ())
5dd0794d 3768 return;
fc0763e6 3769 i.disp_operands = 0;
29b0f896 3770 }
5dd0794d 3771
29b0f896
AM		 3772 if (!process_suffix ())
3773 return;
e413e4e9 3774
bc0844ae
L		 3775 /* Update operand types. */
3776 for (j = 0; j < i.operands; j++)
3777 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3778
29b0f896
AM		 3779 /* Make still unresolved immediate matches conform to size of immediate
3780 given in i.suffix. */
3781 if (!finalize_imm ())
3782 return;
252b5132 3783
40fb9820 3784 if (i.types[0].bitfield.imm1)
29b0f896 3785 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3786
9afe6eb8
L		 3787 /* We only need to check those implicit registers for instructions
3788 with 3 operands or less. */
3789 if (i.operands <= 3)
3790 for (j = 0; j < i.operands; j++)
3791 if (i.types[j].bitfield.inoutportreg
3792 || i.types[j].bitfield.shiftcount
3793 || i.types[j].bitfield.acc
3794 || i.types[j].bitfield.floatacc)
3795 i.reg_operands--;
40fb9820 3796
c0f3af97
L		 3797 /* ImmExt should be processed after SSE2AVX. */
3798 if (!i.tm.opcode_modifier.sse2avx
3799 && i.tm.opcode_modifier.immext)
65da13b5 3800 process_immext ();
252b5132 3801
29b0f896
AM		 3802 /* For insns with operands there are more diddles to do to the opcode. */
3803 if (i.operands)
3804 {
3805 if (!process_operands ())
3806 return;
3807 }
40fb9820 3808 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3809 {
3810 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3811 as_warn (_("translating to `%sp'"), i.tm.name);
3812 }
252b5132 3813
9e5e5283
L		 3814 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3815 {
3816 if (flag_code == CODE_16BIT)
3817 {
3818 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3819 i.tm.name);
3820 return;
3821 }
c0f3af97 3822
9e5e5283
L		 3823 if (i.tm.opcode_modifier.vex)
3824 build_vex_prefix (t);
3825 else
3826 build_evex_prefix ();
3827 }
43234a1e 3828
5dd85c99
SP		 3829 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3830 instructions may define INT_OPCODE as well, so avoid this corner
3831 case for those instructions that use MODRM. */
3832 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3833 && !i.tm.opcode_modifier.modrm
3834 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3835 {
3836 i.tm.base_opcode = INT3_OPCODE;
3837 i.imm_operands = 0;
3838 }
252b5132 3839
40fb9820
L		 3840 if ((i.tm.opcode_modifier.jump
3841 || i.tm.opcode_modifier.jumpbyte
3842 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3843 && i.op[0].disps->X_op == O_constant)
3844 {
3845 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3846 the absolute address given by the constant. Since ix86 jumps and
3847 calls are pc relative, we need to generate a reloc. */
3848 i.op[0].disps->X_add_symbol = &abs_symbol;
3849 i.op[0].disps->X_op = O_symbol;
3850 }
252b5132 3851
40fb9820 3852 if (i.tm.opcode_modifier.rex64)
161a04f6 3853 i.rex |= REX_W;
252b5132 3854
29b0f896
AM		 3855 /* For 8 bit registers we need an empty rex prefix. Also if the
3856 instruction already has a prefix, we need to convert old
3857 registers to new ones. */
773f551c 3858
40fb9820 3859 if ((i.types[0].bitfield.reg8
29b0f896 3860 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3861 || (i.types[1].bitfield.reg8
29b0f896 3862 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3863 || ((i.types[0].bitfield.reg8
3864 || i.types[1].bitfield.reg8)
29b0f896
AM		 3865 && i.rex != 0))
3866 {
3867 int x;
726c5dcd 3868
29b0f896
AM		 3869 i.rex |= REX_OPCODE;
3870 for (x = 0; x < 2; x++)
3871 {
3872 /* Look for 8 bit operand that uses old registers. */
40fb9820 3873 if (i.types[x].bitfield.reg8
29b0f896 3874 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3875 {
29b0f896
AM		 3876 /* In case it is "hi" register, give up. */
3877 if (i.op[x].regs->reg_num > 3)
a540244d 3878 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3879 "instruction requiring REX prefix."),
a540244d 3880 register_prefix, i.op[x].regs->reg_name);
773f551c 3881
29b0f896
AM		 3882 /* Otherwise it is equivalent to the extended register.
3883 Since the encoding doesn't change this is merely
3884 cosmetic cleanup for debug output. */
3885
3886 i.op[x].regs = i.op[x].regs + 8;
773f551c 3887 }
29b0f896
AM		 3888 }
3889 }
773f551c 3890
7ab9ffdd 3891 if (i.rex != 0)
29b0f896
AM		 3892 add_prefix (REX_OPCODE | i.rex);
3893
3894 /* We are ready to output the insn. */
3895 output_insn ();
3896}
3897
3898static char *
e3bb37b5 3899parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3900{
3901 char *l = line;
3902 char *token_start = l;
3903 char *mnem_p;
5c6af06e 3904 int supported;
d3ce72d0 3905 const insn_template *t;
b6169b20 3906 char *dot_p = NULL;
29b0f896 3907
29b0f896
AM		 3908 while (1)
3909 {
3910 mnem_p = mnemonic;
3911 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3912 {
b6169b20
L		 3913 if (*mnem_p == '.')
3914 dot_p = mnem_p;
29b0f896
AM		 3915 mnem_p++;
3916 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3917 {
29b0f896
AM		 3918 as_bad (_("no such instruction: `%s'"), token_start);
3919 return NULL;
3920 }
3921 l++;
3922 }
3923 if (!is_space_char (*l)
3924 && *l != END_OF_INSN
e44823cf
JB		 3925 && (intel_syntax
3926 || (*l != PREFIX_SEPARATOR
3927 && *l != ',')))
29b0f896
AM		 3928 {
3929 as_bad (_("invalid character %s in mnemonic"),
3930 output_invalid (*l));
3931 return NULL;
3932 }
3933 if (token_start == l)
3934 {
e44823cf 3935 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3936 as_bad (_("expecting prefix; got nothing"));
3937 else
3938 as_bad (_("expecting mnemonic; got nothing"));
3939 return NULL;
3940 }
45288df1 3941
29b0f896 3942 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3943 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3944
29b0f896
AM		 3945 if (*l != END_OF_INSN
3946 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3947 && current_templates
40fb9820 3948 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3949 {
c6fb90c8 3950 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3951 {
3952 as_bad ((flag_code != CODE_64BIT
3953 ? _("`%s' is only supported in 64-bit mode")
3954 : _("`%s' is not supported in 64-bit mode")),
3955 current_templates->start->name);
3956 return NULL;
3957 }
29b0f896
AM		 3958 /* If we are in 16-bit mode, do not allow addr16 or data16.
3959 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3960 if ((current_templates->start->opcode_modifier.size16
3961 || current_templates->start->opcode_modifier.size32)
29b0f896 3962 && flag_code != CODE_64BIT
40fb9820 3963 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3964 ^ (flag_code == CODE_16BIT)))
3965 {
3966 as_bad (_("redundant %s prefix"),
3967 current_templates->start->name);
3968 return NULL;
45288df1 3969 }
86fa6981 3970 if (current_templates->start->opcode_length == 0)
29b0f896 3971 {
86fa6981
L		 3972 /* Handle pseudo prefixes. */
3973 switch (current_templates->start->base_opcode)
3974 {
3975 case 0x0:
3976 /* {disp8} */
3977 i.disp_encoding = disp_encoding_8bit;
3978 break;
3979 case 0x1:
3980 /* {disp32} */
3981 i.disp_encoding = disp_encoding_32bit;
3982 break;
3983 case 0x2:
3984 /* {load} */
3985 i.dir_encoding = dir_encoding_load;
3986 break;
3987 case 0x3:
3988 /* {store} */
3989 i.dir_encoding = dir_encoding_store;
3990 break;
3991 case 0x4:
3992 /* {vex2} */
3993 i.vec_encoding = vex_encoding_vex2;
3994 break;
3995 case 0x5:
3996 /* {vex3} */
3997 i.vec_encoding = vex_encoding_vex3;
3998 break;
3999 case 0x6:
4000 /* {evex} */
4001 i.vec_encoding = vex_encoding_evex;
4002 break;
4003 default:
4004 abort ();
4005 }
4006 }
4007 else
4008 {
4009 /* Add prefix, checking for repeated prefixes. */
4e9ac44a 4010 switch (add_prefix (current_templates->start->base_opcode))
86fa6981 4011 {
4e9ac44a
L		 4012 case PREFIX_EXIST:
4013 return NULL;
4014 case PREFIX_DS:
4015 if (current_templates->start->cpu_flags.bitfield.cpucet)
4016 i.notrack_prefix = current_templates->start->name;
4017 break;
4018 case PREFIX_REP:
4019 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4020 i.hle_prefix = current_templates->start->name;
4021 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4022 i.bnd_prefix = current_templates->start->name;
4023 else
4024 i.rep_prefix = current_templates->start->name;
4025 break;
4026 default:
4027 break;
86fa6981 4028 }
29b0f896
AM		 4029 }
4030 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4031 token_start = ++l;
4032 }
4033 else
4034 break;
4035 }
45288df1 4036
30a55f88 4037 if (!current_templates)
b6169b20 4038 {
f8a5c266
L		 4039 /* Check if we should swap operand or force 32bit displacement in
4040 encoding. */
30a55f88 4041 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
86fa6981 4042 i.dir_encoding = dir_encoding_store;
8d63c93e 4043 else if (mnem_p - 3 == dot_p
a501d77e
L		 4044 && dot_p[1] == 'd'
4045 && dot_p[2] == '8')
4046 i.disp_encoding = disp_encoding_8bit;
8d63c93e 4047 else if (mnem_p - 4 == dot_p
f8a5c266
L		 4048 && dot_p[1] == 'd'
4049 && dot_p[2] == '3'
4050 && dot_p[3] == '2')
a501d77e 4051 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 4052 else
4053 goto check_suffix;
4054 mnem_p = dot_p;
4055 *dot_p = '\0';
d3ce72d0 4056 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 4057 }
4058
29b0f896
AM		 4059 if (!current_templates)
4060 {
b6169b20 4061check_suffix:
29b0f896
AM		 4062 /* See if we can get a match by trimming off a suffix. */
4063 switch (mnem_p[-1])
4064 {
4065 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 4066 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4067 i.suffix = SHORT_MNEM_SUFFIX;
4068 else
1a0670f3 4069 /* Fall through. */
29b0f896
AM		 4070 case BYTE_MNEM_SUFFIX:
4071 case QWORD_MNEM_SUFFIX:
4072 i.suffix = mnem_p[-1];
4073 mnem_p[-1] = '\0';
d3ce72d0
NC		 4074 current_templates = (const templates *) hash_find (op_hash,
4075 mnemonic);
29b0f896
AM		 4076 break;
4077 case SHORT_MNEM_SUFFIX:
4078 case LONG_MNEM_SUFFIX:
4079 if (!intel_syntax)
4080 {
4081 i.suffix = mnem_p[-1];
4082 mnem_p[-1] = '\0';
d3ce72d0
NC		 4083 current_templates = (const templates *) hash_find (op_hash,
4084 mnemonic);
29b0f896
AM		 4085 }
4086 break;
252b5132 4087
29b0f896
AM		 4088 /* Intel Syntax. */
4089 case 'd':
4090 if (intel_syntax)
4091 {
9306ca4a 4092 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 4093 i.suffix = SHORT_MNEM_SUFFIX;
4094 else
4095 i.suffix = LONG_MNEM_SUFFIX;
4096 mnem_p[-1] = '\0';
d3ce72d0
NC		 4097 current_templates = (const templates *) hash_find (op_hash,
4098 mnemonic);
29b0f896
AM		 4099 }
4100 break;
4101 }
4102 if (!current_templates)
4103 {
4104 as_bad (_("no such instruction: `%s'"), token_start);
4105 return NULL;
4106 }
4107 }
252b5132 4108
40fb9820
L		 4109 if (current_templates->start->opcode_modifier.jump
4110 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 4111 {
4112 /* Check for a branch hint. We allow ",pt" and ",pn" for
4113 predict taken and predict not taken respectively.
4114 I'm not sure that branch hints actually do anything on loop
4115 and jcxz insns (JumpByte) for current Pentium4 chips. They
4116 may work in the future and it doesn't hurt to accept them
4117 now. */
4118 if (l[0] == ',' && l[1] == 'p')
4119 {
4120 if (l[2] == 't')
4121 {
4122 if (!add_prefix (DS_PREFIX_OPCODE))
4123 return NULL;
4124 l += 3;
4125 }
4126 else if (l[2] == 'n')
4127 {
4128 if (!add_prefix (CS_PREFIX_OPCODE))
4129 return NULL;
4130 l += 3;
4131 }
4132 }
4133 }
4134 /* Any other comma loses. */
4135 if (*l == ',')
4136 {
4137 as_bad (_("invalid character %s in mnemonic"),
4138 output_invalid (*l));
4139 return NULL;
4140 }
252b5132 4141
29b0f896 4142 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 4143 supported = 0;
4144 for (t = current_templates->start; t < current_templates->end; ++t)
4145 {
c0f3af97
L		 4146 supported |= cpu_flags_match (t);
4147 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 4148 goto skip;
5c6af06e 4149 }
3629bb00 4150
c0f3af97 4151 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 4152 {
4153 as_bad (flag_code == CODE_64BIT
4154 ? _("`%s' is not supported in 64-bit mode")
4155 : _("`%s' is only supported in 64-bit mode"),
4156 current_templates->start->name);
4157 return NULL;
4158 }
c0f3af97 4159 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 4160 {
3629bb00 4161 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 4162 current_templates->start->name,
41aacd83 4163 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 4164 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4165 return NULL;
29b0f896 4166 }
3629bb00
L		 4167
4168skip:
4169 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 4170 && (flag_code != CODE_16BIT))
29b0f896
AM		 4171 {
4172 as_warn (_("use .code16 to ensure correct addressing mode"));
4173 }
252b5132 4174
29b0f896
AM		 4175 return l;
4176}
252b5132 4177
29b0f896 4178static char *
e3bb37b5 4179parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 4180{
4181 char *token_start;
3138f287 4182
29b0f896
AM		 4183 /* 1 if operand is pending after ','. */
4184 unsigned int expecting_operand = 0;
252b5132 4185
29b0f896
AM		 4186 /* Non-zero if operand parens not balanced. */
4187 unsigned int paren_not_balanced;
4188
4189 while (*l != END_OF_INSN)
4190 {
4191 /* Skip optional white space before operand. */
4192 if (is_space_char (*l))
4193 ++l;
d02603dc 4194 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
29b0f896
AM		 4195 {
4196 as_bad (_("invalid character %s before operand %d"),
4197 output_invalid (*l),
4198 i.operands + 1);
4199 return NULL;
4200 }
d02603dc 4201 token_start = l; /* After white space. */
29b0f896
AM		 4202 paren_not_balanced = 0;
4203 while (paren_not_balanced || *l != ',')
4204 {
4205 if (*l == END_OF_INSN)
4206 {
4207 if (paren_not_balanced)
4208 {
4209 if (!intel_syntax)
4210 as_bad (_("unbalanced parenthesis in operand %d."),
4211 i.operands + 1);
4212 else
4213 as_bad (_("unbalanced brackets in operand %d."),
4214 i.operands + 1);
4215 return NULL;
4216 }
4217 else
4218 break; /* we are done */
4219 }
d02603dc 4220 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
29b0f896
AM		 4221 {
4222 as_bad (_("invalid character %s in operand %d"),
4223 output_invalid (*l),
4224 i.operands + 1);
4225 return NULL;
4226 }
4227 if (!intel_syntax)
4228 {
4229 if (*l == '(')
4230 ++paren_not_balanced;
4231 if (*l == ')')
4232 --paren_not_balanced;
4233 }
4234 else
4235 {
4236 if (*l == '[')
4237 ++paren_not_balanced;
4238 if (*l == ']')
4239 --paren_not_balanced;
4240 }
4241 l++;
4242 }
4243 if (l != token_start)
4244 { /* Yes, we've read in another operand. */
4245 unsigned int operand_ok;
4246 this_operand = i.operands++;
4247 if (i.operands > MAX_OPERANDS)
4248 {
4249 as_bad (_("spurious operands; (%d operands/instruction max)"),
4250 MAX_OPERANDS);
4251 return NULL;
4252 }
9d46ce34 4253 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4254 /* Now parse operand adding info to 'i' as we go along. */
4255 END_STRING_AND_SAVE (l);
4256
4257 if (intel_syntax)
4258 operand_ok =
4259 i386_intel_operand (token_start,
4260 intel_float_operand (mnemonic));
4261 else
a7619375 4262 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4263
4264 RESTORE_END_STRING (l);
4265 if (!operand_ok)
4266 return NULL;
4267 }
4268 else
4269 {
4270 if (expecting_operand)
4271 {
4272 expecting_operand_after_comma:
4273 as_bad (_("expecting operand after ','; got nothing"));
4274 return NULL;
4275 }
4276 if (*l == ',')
4277 {
4278 as_bad (_("expecting operand before ','; got nothing"));
4279 return NULL;
4280 }
4281 }
7f3f1ea2 4282
29b0f896
AM		 4283 /* Now *l must be either ',' or END_OF_INSN. */
4284 if (*l == ',')
4285 {
4286 if (*++l == END_OF_INSN)
4287 {
4288 /* Just skip it, if it's \n complain. */
4289 goto expecting_operand_after_comma;
4290 }
4291 expecting_operand = 1;
4292 }
4293 }
4294 return l;
4295}
7f3f1ea2 4296
050dfa73 4297static void
4d456e3d 4298swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4299{
4300 union i386_op temp_op;
40fb9820 4301 i386_operand_type temp_type;
050dfa73 4302 enum bfd_reloc_code_real temp_reloc;
4eed87de 4303
050dfa73
MM		 4304 temp_type = i.types[xchg2];
4305 i.types[xchg2] = i.types[xchg1];
4306 i.types[xchg1] = temp_type;
4307 temp_op = i.op[xchg2];
4308 i.op[xchg2] = i.op[xchg1];
4309 i.op[xchg1] = temp_op;
4310 temp_reloc = i.reloc[xchg2];
4311 i.reloc[xchg2] = i.reloc[xchg1];
4312 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4313
4314 if (i.mask)
4315 {
4316 if (i.mask->operand == xchg1)
4317 i.mask->operand = xchg2;
4318 else if (i.mask->operand == xchg2)
4319 i.mask->operand = xchg1;
4320 }
4321 if (i.broadcast)
4322 {
4323 if (i.broadcast->operand == xchg1)
4324 i.broadcast->operand = xchg2;
4325 else if (i.broadcast->operand == xchg2)
4326 i.broadcast->operand = xchg1;
4327 }
4328 if (i.rounding)
4329 {
4330 if (i.rounding->operand == xchg1)
4331 i.rounding->operand = xchg2;
4332 else if (i.rounding->operand == xchg2)
4333 i.rounding->operand = xchg1;
4334 }
050dfa73
MM		 4335}
4336
29b0f896 4337static void
e3bb37b5 4338swap_operands (void)
29b0f896 4339{
b7c61d9a 4340 switch (i.operands)
050dfa73 4341 {
c0f3af97 4342 case 5:
b7c61d9a 4343 case 4:
4d456e3d 4344 swap_2_operands (1, i.operands - 2);
1a0670f3 4345 /* Fall through. */
b7c61d9a
L		 4346 case 3:
4347 case 2:
4d456e3d 4348 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4349 break;
4350 default:
4351 abort ();
29b0f896 4352 }
29b0f896
AM		 4353
4354 if (i.mem_operands == 2)
4355 {
4356 const seg_entry *temp_seg;
4357 temp_seg = i.seg[0];
4358 i.seg[0] = i.seg[1];
4359 i.seg[1] = temp_seg;
4360 }
4361}
252b5132 4362
29b0f896
AM		 4363/* Try to ensure constant immediates are represented in the smallest
4364 opcode possible. */
4365static void
e3bb37b5 4366optimize_imm (void)
29b0f896
AM		 4367{
4368 char guess_suffix = 0;
4369 int op;
252b5132 4370
29b0f896
AM		 4371 if (i.suffix)
4372 guess_suffix = i.suffix;
4373 else if (i.reg_operands)
4374 {
4375 /* Figure out a suffix from the last register operand specified.
4376 We can't do this properly yet, ie. excluding InOutPortReg,
4377 but the following works for instructions with immediates.
4378 In any case, we can't set i.suffix yet. */
4379 for (op = i.operands; --op >= 0;)
40fb9820 4380 if (i.types[op].bitfield.reg8)
7ab9ffdd 4381 {
40fb9820
L		 4382 guess_suffix = BYTE_MNEM_SUFFIX;
4383 break;
4384 }
4385 else if (i.types[op].bitfield.reg16)
252b5132 4386 {
40fb9820
L		 4387 guess_suffix = WORD_MNEM_SUFFIX;
4388 break;
4389 }
4390 else if (i.types[op].bitfield.reg32)
4391 {
4392 guess_suffix = LONG_MNEM_SUFFIX;
4393 break;
4394 }
4395 else if (i.types[op].bitfield.reg64)
4396 {
4397 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4398 break;
252b5132 4399 }
29b0f896
AM		 4400 }
4401 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4402 guess_suffix = WORD_MNEM_SUFFIX;
4403
4404 for (op = i.operands; --op >= 0;)
40fb9820 4405 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4406 {
4407 switch (i.op[op].imms->X_op)
252b5132 4408 {
29b0f896
AM		 4409 case O_constant:
4410 /* If a suffix is given, this operand may be shortened. */
4411 switch (guess_suffix)
252b5132 4412 {
29b0f896 4413 case LONG_MNEM_SUFFIX:
40fb9820
L		 4414 i.types[op].bitfield.imm32 = 1;
4415 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4416 break;
4417 case WORD_MNEM_SUFFIX:
40fb9820
L		 4418 i.types[op].bitfield.imm16 = 1;
4419 i.types[op].bitfield.imm32 = 1;
4420 i.types[op].bitfield.imm32s = 1;
4421 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4422 break;
4423 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4424 i.types[op].bitfield.imm8 = 1;
4425 i.types[op].bitfield.imm8s = 1;
4426 i.types[op].bitfield.imm16 = 1;
4427 i.types[op].bitfield.imm32 = 1;
4428 i.types[op].bitfield.imm32s = 1;
4429 i.types[op].bitfield.imm64 = 1;
29b0f896 4430 break;
252b5132 4431 }
252b5132 4432
29b0f896
AM		 4433 /* If this operand is at most 16 bits, convert it
4434 to a signed 16 bit number before trying to see
4435 whether it will fit in an even smaller size.
4436 This allows a 16-bit operand such as $0xffe0 to
4437 be recognised as within Imm8S range. */
40fb9820 4438 if ((i.types[op].bitfield.imm16)
29b0f896 4439 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4440 {
29b0f896
AM		 4441 i.op[op].imms->X_add_number =
4442 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4443 }
a28def75
L		 4444#ifdef BFD64
4445 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
40fb9820 4446 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4447 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4448 == 0))
4449 {
4450 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4451 ^ ((offsetT) 1 << 31))
4452 - ((offsetT) 1 << 31));
4453 }
a28def75 4454#endif
40fb9820 4455 i.types[op]
c6fb90c8
L		 4456 = operand_type_or (i.types[op],
4457 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4458
29b0f896
AM		 4459 /* We must avoid matching of Imm32 templates when 64bit
4460 only immediate is available. */
4461 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4462 i.types[op].bitfield.imm32 = 0;
29b0f896 4463 break;
252b5132 4464
29b0f896
AM		 4465 case O_absent:
4466 case O_register:
4467 abort ();
4468
4469 /* Symbols and expressions. */
4470 default:
9cd96992
JB		 4471 /* Convert symbolic operand to proper sizes for matching, but don't
4472 prevent matching a set of insns that only supports sizes other
4473 than those matching the insn suffix. */
4474 {
40fb9820 4475 i386_operand_type mask, allowed;
d3ce72d0 4476 const insn_template *t;
9cd96992 4477
0dfbf9d7
L		 4478 operand_type_set (&mask, 0);
4479 operand_type_set (&allowed, 0);
40fb9820 4480
4eed87de
AM		 4481 for (t = current_templates->start;
4482 t < current_templates->end;
4483 ++t)
c6fb90c8
L		 4484 allowed = operand_type_or (allowed,
4485 t->operand_types[op]);
9cd96992
JB		 4486 switch (guess_suffix)
4487 {
4488 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4489 mask.bitfield.imm64 = 1;
4490 mask.bitfield.imm32s = 1;
9cd96992
JB		 4491 break;
4492 case LONG_MNEM_SUFFIX:
40fb9820 4493 mask.bitfield.imm32 = 1;
9cd96992
JB		 4494 break;
4495 case WORD_MNEM_SUFFIX:
40fb9820 4496 mask.bitfield.imm16 = 1;
9cd96992
JB		 4497 break;
4498 case BYTE_MNEM_SUFFIX:
40fb9820 4499 mask.bitfield.imm8 = 1;
9cd96992
JB		 4500 break;
4501 default:
9cd96992
JB		 4502 break;
4503 }
c6fb90c8 4504 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4505 if (!operand_type_all_zero (&allowed))
c6fb90c8 4506 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4507 }
29b0f896 4508 break;
252b5132 4509 }
29b0f896
AM		 4510 }
4511}
47926f60 4512
29b0f896
AM		 4513/* Try to use the smallest displacement type too. */
4514static void
e3bb37b5 4515optimize_disp (void)
29b0f896
AM		 4516{
4517 int op;
3e73aa7c 4518
29b0f896 4519 for (op = i.operands; --op >= 0;)
40fb9820 4520 if (operand_type_check (i.types[op], disp))
252b5132 4521 {
b300c311 4522 if (i.op[op].disps->X_op == O_constant)
252b5132 4523 {
91d6fa6a 4524 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4525
40fb9820 4526 if (i.types[op].bitfield.disp16
91d6fa6a 4527 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4528 {
4529 /* If this operand is at most 16 bits, convert
4530 to a signed 16 bit number and don't use 64bit
4531 displacement. */
91d6fa6a 4532 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4533 i.types[op].bitfield.disp64 = 0;
b300c311 4534 }
a28def75
L		 4535#ifdef BFD64
4536 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
40fb9820 4537 if (i.types[op].bitfield.disp32
91d6fa6a 4538 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4539 {
4540 /* If this operand is at most 32 bits, convert
4541 to a signed 32 bit number and don't use 64bit
4542 displacement. */
91d6fa6a
NC		 4543 op_disp &= (((offsetT) 2 << 31) - 1);
4544 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4545 i.types[op].bitfield.disp64 = 0;
b300c311 4546 }
a28def75 4547#endif
91d6fa6a 4548 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4549 {
40fb9820
L		 4550 i.types[op].bitfield.disp8 = 0;
4551 i.types[op].bitfield.disp16 = 0;
4552 i.types[op].bitfield.disp32 = 0;
4553 i.types[op].bitfield.disp32s = 0;
4554 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4555 i.op[op].disps = 0;
4556 i.disp_operands--;
4557 }
4558 else if (flag_code == CODE_64BIT)
4559 {
91d6fa6a 4560 if (fits_in_signed_long (op_disp))
28a9d8f5 4561 {
40fb9820
L		 4562 i.types[op].bitfield.disp64 = 0;
4563 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4564 }
0e1147d9 4565 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4566 && fits_in_unsigned_long (op_disp))
40fb9820 4567 i.types[op].bitfield.disp32 = 1;
b300c311 4568 }
40fb9820
L		 4569 if ((i.types[op].bitfield.disp32
4570 || i.types[op].bitfield.disp32s
4571 || i.types[op].bitfield.disp16)
91d6fa6a 4572 && fits_in_signed_byte (op_disp))
40fb9820 4573 i.types[op].bitfield.disp8 = 1;
252b5132 4574 }
67a4f2b7
AO		 4575 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4576 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4577 {
4578 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4579 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4580 i.types[op].bitfield.disp8 = 0;
4581 i.types[op].bitfield.disp16 = 0;
4582 i.types[op].bitfield.disp32 = 0;
4583 i.types[op].bitfield.disp32s = 0;
4584 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4585 }
4586 else
b300c311 4587 /* We only support 64bit displacement on constants. */
40fb9820 4588 i.types[op].bitfield.disp64 = 0;
252b5132 4589 }
29b0f896
AM		 4590}
4591
6c30d220
L		 4592/* Check if operands are valid for the instruction. */
4593
4594static int
4595check_VecOperands (const insn_template *t)
4596{
43234a1e
L		 4597 unsigned int op;
4598
6c30d220
L		 4599 /* Without VSIB byte, we can't have a vector register for index. */
4600 if (!t->opcode_modifier.vecsib
4601 && i.index_reg
4602 && (i.index_reg->reg_type.bitfield.regxmm
43234a1e
L		 4603 || i.index_reg->reg_type.bitfield.regymm
4604 || i.index_reg->reg_type.bitfield.regzmm))
6c30d220
L		 4605 {
4606 i.error = unsupported_vector_index_register;
4607 return 1;
4608 }
4609
ad8ecc81
MZ		 4610 /* Check if default mask is allowed. */
4611 if (t->opcode_modifier.nodefmask
4612 && (!i.mask || i.mask->mask->reg_num == 0))
4613 {
4614 i.error = no_default_mask;
4615 return 1;
4616 }
4617
7bab8ab5
JB		 4618 /* For VSIB byte, we need a vector register for index, and all vector
4619 registers must be distinct. */
4620 if (t->opcode_modifier.vecsib)
4621 {
4622 if (!i.index_reg
6c30d220
L		 4623 || !((t->opcode_modifier.vecsib == VecSIB128
4624 && i.index_reg->reg_type.bitfield.regxmm)
4625 || (t->opcode_modifier.vecsib == VecSIB256
43234a1e
L		 4626 && i.index_reg->reg_type.bitfield.regymm)
4627 || (t->opcode_modifier.vecsib == VecSIB512
4628 && i.index_reg->reg_type.bitfield.regzmm)))
7bab8ab5
JB		 4629 {
4630 i.error = invalid_vsib_address;
4631 return 1;
4632 }
4633
43234a1e
L		 4634 gas_assert (i.reg_operands == 2 || i.mask);
4635 if (i.reg_operands == 2 && !i.mask)
4636 {
4637 gas_assert (i.types[0].bitfield.regxmm
7c84a0ca 4638 || i.types[0].bitfield.regymm);
43234a1e 4639 gas_assert (i.types[2].bitfield.regxmm
7c84a0ca 4640 || i.types[2].bitfield.regymm);
43234a1e
L		 4641 if (operand_check == check_none)
4642 return 0;
4643 if (register_number (i.op[0].regs)
4644 != register_number (i.index_reg)
4645 && register_number (i.op[2].regs)
4646 != register_number (i.index_reg)
4647 && register_number (i.op[0].regs)
4648 != register_number (i.op[2].regs))
4649 return 0;
4650 if (operand_check == check_error)
4651 {
4652 i.error = invalid_vector_register_set;
4653 return 1;
4654 }
4655 as_warn (_("mask, index, and destination registers should be distinct"));
4656 }
8444f82a
MZ		 4657 else if (i.reg_operands == 1 && i.mask)
4658 {
4659 if ((i.types[1].bitfield.regymm
4660 || i.types[1].bitfield.regzmm)
4661 && (register_number (i.op[1].regs)
4662 == register_number (i.index_reg)))
4663 {
4664 if (operand_check == check_error)
4665 {
4666 i.error = invalid_vector_register_set;
4667 return 1;
4668 }
4669 if (operand_check != check_none)
4670 as_warn (_("index and destination registers should be distinct"));
4671 }
4672 }
43234a1e 4673 }
7bab8ab5 4674
43234a1e
L		 4675 /* Check if broadcast is supported by the instruction and is applied
4676 to the memory operand. */
4677 if (i.broadcast)
4678 {
4679 int broadcasted_opnd_size;
4680
4681 /* Check if specified broadcast is supported in this instruction,
4682 and it's applied to memory operand of DWORD or QWORD type,
4683 depending on VecESize. */
4684 if (i.broadcast->type != t->opcode_modifier.broadcast
4685 || !i.types[i.broadcast->operand].bitfield.mem
4686 || (t->opcode_modifier.vecesize == 0
4687 && !i.types[i.broadcast->operand].bitfield.dword
4688 && !i.types[i.broadcast->operand].bitfield.unspecified)
4689 || (t->opcode_modifier.vecesize == 1
4690 && !i.types[i.broadcast->operand].bitfield.qword
4691 && !i.types[i.broadcast->operand].bitfield.unspecified))
4692 goto bad_broadcast;
4693
4694 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4695 if (i.broadcast->type == BROADCAST_1TO16)
4696 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4697 else if (i.broadcast->type == BROADCAST_1TO8)
4698 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
b28d1bda
IT		 4699 else if (i.broadcast->type == BROADCAST_1TO4)
4700 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4701 else if (i.broadcast->type == BROADCAST_1TO2)
4702 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
43234a1e
L		 4703 else
4704 goto bad_broadcast;
4705
4706 if ((broadcasted_opnd_size == 256
4707 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4708 || (broadcasted_opnd_size == 512
4709 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4710 {
4711 bad_broadcast:
4712 i.error = unsupported_broadcast;
4713 return 1;
4714 }
4715 }
4716 /* If broadcast is supported in this instruction, we need to check if
4717 operand of one-element size isn't specified without broadcast. */
4718 else if (t->opcode_modifier.broadcast && i.mem_operands)
4719 {
4720 /* Find memory operand. */
4721 for (op = 0; op < i.operands; op++)
4722 if (operand_type_check (i.types[op], anymem))
4723 break;
4724 gas_assert (op < i.operands);
4725 /* Check size of the memory operand. */
4726 if ((t->opcode_modifier.vecesize == 0
4727 && i.types[op].bitfield.dword)
4728 || (t->opcode_modifier.vecesize == 1
4729 && i.types[op].bitfield.qword))
4730 {
4731 i.error = broadcast_needed;
4732 return 1;
4733 }
4734 }
4735
4736 /* Check if requested masking is supported. */
4737 if (i.mask
4738 && (!t->opcode_modifier.masking
4739 || (i.mask->zeroing
4740 && t->opcode_modifier.masking == MERGING_MASKING)))
4741 {
4742 i.error = unsupported_masking;
4743 return 1;
4744 }
4745
4746 /* Check if masking is applied to dest operand. */
4747 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4748 {
4749 i.error = mask_not_on_destination;
4750 return 1;
4751 }
4752
43234a1e
L		 4753 /* Check RC/SAE. */
4754 if (i.rounding)
4755 {
4756 if ((i.rounding->type != saeonly
4757 && !t->opcode_modifier.staticrounding)
4758 || (i.rounding->type == saeonly
4759 && (t->opcode_modifier.staticrounding
4760 || !t->opcode_modifier.sae)))
4761 {
4762 i.error = unsupported_rc_sae;
4763 return 1;
4764 }
4765 /* If the instruction has several immediate operands and one of
4766 them is rounding, the rounding operand should be the last
4767 immediate operand. */
4768 if (i.imm_operands > 1
4769 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4770 {
43234a1e 4771 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4772 return 1;
4773 }
6c30d220
L		 4774 }
4775
43234a1e
L		 4776 /* Check vector Disp8 operand. */
4777 if (t->opcode_modifier.disp8memshift)
4778 {
4779 if (i.broadcast)
4780 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4781 else
4782 i.memshift = t->opcode_modifier.disp8memshift;
4783
4784 for (op = 0; op < i.operands; op++)
4785 if (operand_type_check (i.types[op], disp)
4786 && i.op[op].disps->X_op == O_constant)
4787 {
4788 offsetT value = i.op[op].disps->X_add_number;
5be33403
L		 4789 int vec_disp8_ok
4790 = (i.disp_encoding != disp_encoding_32bit
4791 && fits_in_vec_disp8 (value));
43234a1e
L		 4792 if (t->operand_types [op].bitfield.vec_disp8)
4793 {
4794 if (vec_disp8_ok)
4795 i.types[op].bitfield.vec_disp8 = 1;
4796 else
4797 {
4798 /* Vector insn can only have Vec_Disp8/Disp32 in
4799 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4800 mode. */
4801 i.types[op].bitfield.disp8 = 0;
4802 if (flag_code != CODE_16BIT)
4803 i.types[op].bitfield.disp16 = 0;
4804 }
4805 }
4806 else if (flag_code != CODE_16BIT)
4807 {
4808 /* One form of this instruction supports vector Disp8.
4809 Try vector Disp8 if we need to use Disp32. */
4810 if (vec_disp8_ok && !fits_in_signed_byte (value))
4811 {
4812 i.error = try_vector_disp8;
4813 return 1;
4814 }
4815 }
4816 }
4817 }
4818 else
4819 i.memshift = -1;
4820
6c30d220
L		 4821 return 0;
4822}
4823
43f3e2ee 4824/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4825 operand types. */
4826
4827static int
4828VEX_check_operands (const insn_template *t)
4829{
86fa6981 4830 if (i.vec_encoding == vex_encoding_evex)
43234a1e 4831 {
86fa6981
L		 4832 /* This instruction must be encoded with EVEX prefix. */
4833 if (!t->opcode_modifier.evex)
4834 {
4835 i.error = unsupported;
4836 return 1;
4837 }
4838 return 0;
43234a1e
L		 4839 }
4840
a683cc34 4841 if (!t->opcode_modifier.vex)
86fa6981
L		 4842 {
4843 /* This instruction template doesn't have VEX prefix. */
4844 if (i.vec_encoding != vex_encoding_default)
4845 {
4846 i.error = unsupported;
4847 return 1;
4848 }
4849 return 0;
4850 }
a683cc34
SP		 4851
4852 /* Only check VEX_Imm4, which must be the first operand. */
4853 if (t->operand_types[0].bitfield.vec_imm4)
4854 {
4855 if (i.op[0].imms->X_op != O_constant
4856 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4857 {
a65babc9 4858 i.error = bad_imm4;
891edac4
L		 4859 return 1;
4860 }
a683cc34
SP		 4861
4862 /* Turn off Imm8 so that update_imm won't complain. */
4863 i.types[0] = vec_imm4;
4864 }
4865
4866 return 0;
4867}
4868
d3ce72d0 4869static const insn_template *
83b16ac6 4870match_template (char mnem_suffix)
29b0f896
AM		 4871{
4872 /* Points to template once we've found it. */
d3ce72d0 4873 const insn_template *t;
40fb9820 4874 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4875 i386_operand_type overlap4;
29b0f896 4876 unsigned int found_reverse_match;
83b16ac6 4877 i386_opcode_modifier suffix_check, mnemsuf_check;
40fb9820 4878 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4879 int addr_prefix_disp;
a5c311ca 4880 unsigned int j;
3629bb00 4881 unsigned int found_cpu_match;
45664ddb 4882 unsigned int check_register;
5614d22c 4883 enum i386_error specific_error = 0;
29b0f896 4884
c0f3af97
L		 4885#if MAX_OPERANDS != 5
4886# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4887#endif
4888
29b0f896 4889 found_reverse_match = 0;
539e75ad 4890 addr_prefix_disp = -1;
40fb9820
L		 4891
4892 memset (&suffix_check, 0, sizeof (suffix_check));
4893 if (i.suffix == BYTE_MNEM_SUFFIX)
4894 suffix_check.no_bsuf = 1;
4895 else if (i.suffix == WORD_MNEM_SUFFIX)
4896 suffix_check.no_wsuf = 1;
4897 else if (i.suffix == SHORT_MNEM_SUFFIX)
4898 suffix_check.no_ssuf = 1;
4899 else if (i.suffix == LONG_MNEM_SUFFIX)
4900 suffix_check.no_lsuf = 1;
4901 else if (i.suffix == QWORD_MNEM_SUFFIX)
4902 suffix_check.no_qsuf = 1;
4903 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4904 suffix_check.no_ldsuf = 1;
29b0f896 4905
83b16ac6
JB		 4906 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
4907 if (intel_syntax)
4908 {
4909 switch (mnem_suffix)
4910 {
4911 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
4912 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
4913 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
4914 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
4915 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
4916 }
4917 }
4918
01559ecc
L		 4919 /* Must have right number of operands. */
4920 i.error = number_of_operands_mismatch;
4921
45aa61fe 4922 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4923 {
539e75ad
L		 4924 addr_prefix_disp = -1;
4925
29b0f896
AM		 4926 if (i.operands != t->operands)
4927 continue;
4928
50aecf8c 4929 /* Check processor support. */
a65babc9 4930 i.error = unsupported;
c0f3af97
L		 4931 found_cpu_match = (cpu_flags_match (t)
4932 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4933 if (!found_cpu_match)
4934 continue;
4935
e1d4d893 4936 /* Check old gcc support. */
a65babc9 4937 i.error = old_gcc_only;
e1d4d893
L		 4938 if (!old_gcc && t->opcode_modifier.oldgcc)
4939 continue;
4940
4941 /* Check AT&T mnemonic. */
a65babc9 4942 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4943 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4944 continue;
4945
e92bae62 4946 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
a65babc9 4947 i.error = unsupported_syntax;
5c07affc 4948 if ((intel_syntax && t->opcode_modifier.attsyntax)
e92bae62
L		 4949 || (!intel_syntax && t->opcode_modifier.intelsyntax)
4950 || (intel64 && t->opcode_modifier.amd64)
4951 || (!intel64 && t->opcode_modifier.intel64))
1efbbeb4
L		 4952 continue;
4953
20592a94 4954 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4955 i.error = invalid_instruction_suffix;
567e4e96
L		 4956 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4957 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4958 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4959 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4960 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4961 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4962 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896 4963 continue;
83b16ac6
JB		 4964 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
4965 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
4966 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
4967 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
4968 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
4969 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
4970 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
4971 continue;
29b0f896 4972
5c07affc 4973 if (!operand_size_match (t))
7d5e4556 4974 continue;
539e75ad 4975
5c07affc
L		 4976 for (j = 0; j < MAX_OPERANDS; j++)
4977 operand_types[j] = t->operand_types[j];
4978
45aa61fe
AM		 4979 /* In general, don't allow 64-bit operands in 32-bit mode. */
4980 if (i.suffix == QWORD_MNEM_SUFFIX
4981 && flag_code != CODE_64BIT
4982 && (intel_syntax
40fb9820 4983 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4984 && !intel_float_operand (t->name))
4985 : intel_float_operand (t->name) != 2)
40fb9820 4986 && ((!operand_types[0].bitfield.regmmx
c0f3af97 4987 && !operand_types[0].bitfield.regxmm
43234a1e
L		 4988 && !operand_types[0].bitfield.regymm
4989 && !operand_types[0].bitfield.regzmm)
40fb9820 4990 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736
AM		 4991 && operand_types[t->operands > 1].bitfield.regxmm
4992 && operand_types[t->operands > 1].bitfield.regymm
4993 && operand_types[t->operands > 1].bitfield.regzmm))
45aa61fe
AM		 4994 && (t->base_opcode != 0x0fc7
4995 || t->extension_opcode != 1 /* cmpxchg8b */))
4996 continue;
4997
192dc9c6
JB		 4998 /* In general, don't allow 32-bit operands on pre-386. */
4999 else if (i.suffix == LONG_MNEM_SUFFIX
5000 && !cpu_arch_flags.bitfield.cpui386
5001 && (intel_syntax
5002 ? (!t->opcode_modifier.ignoresize
5003 && !intel_float_operand (t->name))
5004 : intel_float_operand (t->name) != 2)
5005 && ((!operand_types[0].bitfield.regmmx
5006 && !operand_types[0].bitfield.regxmm)
5007 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736 5008 && operand_types[t->operands > 1].bitfield.regxmm)))
192dc9c6
JB		 5009 continue;
5010
29b0f896 5011 /* Do not verify operands when there are none. */
50aecf8c 5012 else
29b0f896 5013 {
c6fb90c8 5014 if (!t->operands)
2dbab7d5
L		 5015 /* We've found a match; break out of loop. */
5016 break;
29b0f896 5017 }
252b5132 5018
539e75ad
L		 5019 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5020 into Disp32/Disp16/Disp32 operand. */
5021 if (i.prefix[ADDR_PREFIX] != 0)
5022 {
40fb9820 5023 /* There should be only one Disp operand. */
539e75ad
L		 5024 switch (flag_code)
5025 {
5026 case CODE_16BIT:
40fb9820
L		 5027 for (j = 0; j < MAX_OPERANDS; j++)
5028 {
5029 if (operand_types[j].bitfield.disp16)
5030 {
5031 addr_prefix_disp = j;
5032 operand_types[j].bitfield.disp32 = 1;
5033 operand_types[j].bitfield.disp16 = 0;
5034 break;
5035 }
5036 }
539e75ad
L		 5037 break;
5038 case CODE_32BIT:
40fb9820
L		 5039 for (j = 0; j < MAX_OPERANDS; j++)
5040 {
5041 if (operand_types[j].bitfield.disp32)
5042 {
5043 addr_prefix_disp = j;
5044 operand_types[j].bitfield.disp32 = 0;
5045 operand_types[j].bitfield.disp16 = 1;
5046 break;
5047 }
5048 }
539e75ad
L		 5049 break;
5050 case CODE_64BIT:
40fb9820
L		 5051 for (j = 0; j < MAX_OPERANDS; j++)
5052 {
5053 if (operand_types[j].bitfield.disp64)
5054 {
5055 addr_prefix_disp = j;
5056 operand_types[j].bitfield.disp64 = 0;
5057 operand_types[j].bitfield.disp32 = 1;
5058 break;
5059 }
5060 }
539e75ad
L		 5061 break;
5062 }
539e75ad
L		 5063 }
5064
02a86693
L		 5065 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5066 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5067 continue;
5068
56ffb741
L		 5069 /* We check register size if needed. */
5070 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 5071 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 5072 switch (t->operands)
5073 {
5074 case 1:
40fb9820 5075 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 5076 continue;
5077 break;
5078 case 2:
33eaf5de 5079 /* xchg %eax, %eax is a special case. It is an alias for nop
8b38ad71
L		 5080 only in 32bit mode and we can use opcode 0x90. In 64bit
5081 mode, we can't use 0x90 for xchg %eax, %eax since it should
5082 zero-extend %eax to %rax. */
5083 if (flag_code == CODE_64BIT
5084 && t->base_opcode == 0x90
0dfbf9d7
L		 5085 && operand_type_equal (&i.types [0], &acc32)
5086 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 5087 continue;
86fa6981
L		 5088 /* If we want store form, we reverse direction of operands. */
5089 if (i.dir_encoding == dir_encoding_store
5090 && t->opcode_modifier.d)
5091 goto check_reverse;
1a0670f3 5092 /* Fall through. */
b6169b20 5093
29b0f896 5094 case 3:
86fa6981
L		 5095 /* If we want store form, we skip the current load. */
5096 if (i.dir_encoding == dir_encoding_store
5097 && i.mem_operands == 0
5098 && t->opcode_modifier.load)
fa99fab2 5099 continue;
1a0670f3 5100 /* Fall through. */
f48ff2ae 5101 case 4:
c0f3af97 5102 case 5:
c6fb90c8 5103 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 5104 if (!operand_type_match (overlap0, i.types[0])
5105 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 5106 || (check_register
5107 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 5108 operand_types[0],
5109 overlap1, i.types[1],
5110 operand_types[1])))
29b0f896
AM		 5111 {
5112 /* Check if other direction is valid ... */
40fb9820 5113 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 5114 continue;
5115
b6169b20 5116check_reverse:
29b0f896 5117 /* Try reversing direction of operands. */
c6fb90c8
L		 5118 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5119 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 5120 if (!operand_type_match (overlap0, i.types[0])
5121 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 5122 || (check_register
5123 && !operand_type_register_match (overlap0,
5124 i.types[0],
5125 operand_types[1],
5126 overlap1,
5127 i.types[1],
5128 operand_types[0])))
29b0f896
AM		 5129 {
5130 /* Does not match either direction. */
5131 continue;
5132 }
5133 /* found_reverse_match holds which of D or FloatDR
5134 we've found. */
40fb9820 5135 if (t->opcode_modifier.d)
8a2ed489 5136 found_reverse_match = Opcode_D;
40fb9820 5137 else if (t->opcode_modifier.floatd)
8a2ed489
L		 5138 found_reverse_match = Opcode_FloatD;
5139 else
5140 found_reverse_match = 0;
40fb9820 5141 if (t->opcode_modifier.floatr)
8a2ed489 5142 found_reverse_match |= Opcode_FloatR;
29b0f896 5143 }
f48ff2ae 5144 else
29b0f896 5145 {
f48ff2ae 5146 /* Found a forward 2 operand match here. */
d1cbb4db
L		 5147 switch (t->operands)
5148 {
c0f3af97
L		 5149 case 5:
5150 overlap4 = operand_type_and (i.types[4],
5151 operand_types[4]);
1a0670f3 5152 /* Fall through. */
d1cbb4db 5153 case 4:
c6fb90c8
L		 5154 overlap3 = operand_type_and (i.types[3],
5155 operand_types[3]);
1a0670f3 5156 /* Fall through. */
d1cbb4db 5157 case 3:
c6fb90c8
L		 5158 overlap2 = operand_type_and (i.types[2],
5159 operand_types[2]);
d1cbb4db
L		 5160 break;
5161 }
29b0f896 5162
f48ff2ae
L		 5163 switch (t->operands)
5164 {
c0f3af97
L		 5165 case 5:
5166 if (!operand_type_match (overlap4, i.types[4])
5167 || !operand_type_register_match (overlap3,
5168 i.types[3],
5169 operand_types[3],
5170 overlap4,
5171 i.types[4],
5172 operand_types[4]))
5173 continue;
1a0670f3 5174 /* Fall through. */
f48ff2ae 5175 case 4:
40fb9820 5176 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 5177 || (check_register
5178 && !operand_type_register_match (overlap2,
5179 i.types[2],
5180 operand_types[2],
5181 overlap3,
5182 i.types[3],
5183 operand_types[3])))
f48ff2ae 5184 continue;
1a0670f3 5185 /* Fall through. */
f48ff2ae
L		 5186 case 3:
5187 /* Here we make use of the fact that there are no
5188 reverse match 3 operand instructions, and all 3
5189 operand instructions only need to be checked for
5190 register consistency between operands 2 and 3. */
40fb9820 5191 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 5192 || (check_register
5193 && !operand_type_register_match (overlap1,
5194 i.types[1],
5195 operand_types[1],
5196 overlap2,
5197 i.types[2],
5198 operand_types[2])))
f48ff2ae
L		 5199 continue;
5200 break;
5201 }
29b0f896 5202 }
f48ff2ae 5203 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 5204 slip through to break. */
5205 }
3629bb00 5206 if (!found_cpu_match)
29b0f896
AM		 5207 {
5208 found_reverse_match = 0;
5209 continue;
5210 }
c0f3af97 5211
5614d22c
JB		 5212 /* Check if vector and VEX operands are valid. */
5213 if (check_VecOperands (t) || VEX_check_operands (t))
5214 {
5215 specific_error = i.error;
5216 continue;
5217 }
a683cc34 5218
29b0f896
AM		 5219 /* We've found a match; break out of loop. */
5220 break;
5221 }
5222
5223 if (t == current_templates->end)
5224 {
5225 /* We found no match. */
a65babc9 5226 const char *err_msg;
5614d22c 5227 switch (specific_error ? specific_error : i.error)
a65babc9
L		 5228 {
5229 default:
5230 abort ();
86e026a4 5231 case operand_size_mismatch:
a65babc9
L		 5232 err_msg = _("operand size mismatch");
5233 break;
5234 case operand_type_mismatch:
5235 err_msg = _("operand type mismatch");
5236 break;
5237 case register_type_mismatch:
5238 err_msg = _("register type mismatch");
5239 break;
5240 case number_of_operands_mismatch:
5241 err_msg = _("number of operands mismatch");
5242 break;
5243 case invalid_instruction_suffix:
5244 err_msg = _("invalid instruction suffix");
5245 break;
5246 case bad_imm4:
4a2608e3 5247 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 5248 break;
5249 case old_gcc_only:
5250 err_msg = _("only supported with old gcc");
5251 break;
5252 case unsupported_with_intel_mnemonic:
5253 err_msg = _("unsupported with Intel mnemonic");
5254 break;
5255 case unsupported_syntax:
5256 err_msg = _("unsupported syntax");
5257 break;
5258 case unsupported:
35262a23 5259 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 5260 current_templates->start->name);
5261 return NULL;
6c30d220
L		 5262 case invalid_vsib_address:
5263 err_msg = _("invalid VSIB address");
5264 break;
7bab8ab5
JB		 5265 case invalid_vector_register_set:
5266 err_msg = _("mask, index, and destination registers must be distinct");
5267 break;
6c30d220
L		 5268 case unsupported_vector_index_register:
5269 err_msg = _("unsupported vector index register");
5270 break;
43234a1e
L		 5271 case unsupported_broadcast:
5272 err_msg = _("unsupported broadcast");
5273 break;
5274 case broadcast_not_on_src_operand:
5275 err_msg = _("broadcast not on source memory operand");
5276 break;
5277 case broadcast_needed:
5278 err_msg = _("broadcast is needed for operand of such type");
5279 break;
5280 case unsupported_masking:
5281 err_msg = _("unsupported masking");
5282 break;
5283 case mask_not_on_destination:
5284 err_msg = _("mask not on destination operand");
5285 break;
5286 case no_default_mask:
5287 err_msg = _("default mask isn't allowed");
5288 break;
5289 case unsupported_rc_sae:
5290 err_msg = _("unsupported static rounding/sae");
5291 break;
5292 case rc_sae_operand_not_last_imm:
5293 if (intel_syntax)
5294 err_msg = _("RC/SAE operand must precede immediate operands");
5295 else
5296 err_msg = _("RC/SAE operand must follow immediate operands");
5297 break;
5298 case invalid_register_operand:
5299 err_msg = _("invalid register operand");
5300 break;
a65babc9
L		 5301 }
5302 as_bad (_("%s for `%s'"), err_msg,
891edac4 5303 current_templates->start->name);
fa99fab2 5304 return NULL;
29b0f896 5305 }
252b5132 5306
29b0f896
AM		 5307 if (!quiet_warnings)
5308 {
5309 if (!intel_syntax
40fb9820
L		 5310 && (i.types[0].bitfield.jumpabsolute
5311 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5312 {
5313 as_warn (_("indirect %s without `*'"), t->name);
5314 }
5315
40fb9820
L		 5316 if (t->opcode_modifier.isprefix
5317 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5318 {
5319 /* Warn them that a data or address size prefix doesn't
5320 affect assembly of the next line of code. */
5321 as_warn (_("stand-alone `%s' prefix"), t->name);
5322 }
5323 }
5324
5325 /* Copy the template we found. */
5326 i.tm = *t;
539e75ad
L		 5327
5328 if (addr_prefix_disp != -1)
5329 i.tm.operand_types[addr_prefix_disp]
5330 = operand_types[addr_prefix_disp];
5331
29b0f896
AM		 5332 if (found_reverse_match)
5333 {
5334 /* If we found a reverse match we must alter the opcode
5335 direction bit. found_reverse_match holds bits to change
5336 (different for int & float insns). */
5337
5338 i.tm.base_opcode ^= found_reverse_match;
5339
539e75ad
L		 5340 i.tm.operand_types[0] = operand_types[1];
5341 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5342 }
5343
fa99fab2 5344 return t;
29b0f896
AM		 5345}
5346
5347static int
e3bb37b5 5348check_string (void)
29b0f896 5349{
40fb9820
L		 5350 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5351 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5352 {
5353 if (i.seg[0] != NULL && i.seg[0] != &es)
5354 {
a87af027 5355 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5356 i.tm.name,
a87af027
JB		 5357 mem_op + 1,
5358 register_prefix);
29b0f896
AM		 5359 return 0;
5360 }
5361 /* There's only ever one segment override allowed per instruction.
5362 This instruction possibly has a legal segment override on the
5363 second operand, so copy the segment to where non-string
5364 instructions store it, allowing common code. */
5365 i.seg[0] = i.seg[1];
5366 }
40fb9820 5367 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5368 {
5369 if (i.seg[1] != NULL && i.seg[1] != &es)
5370 {
a87af027 5371 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5372 i.tm.name,
a87af027
JB		 5373 mem_op + 2,
5374 register_prefix);
29b0f896
AM		 5375 return 0;
5376 }
5377 }
5378 return 1;
5379}
5380
5381static int
543613e9 5382process_suffix (void)
29b0f896
AM		 5383{
5384 /* If matched instruction specifies an explicit instruction mnemonic
5385 suffix, use it. */
40fb9820
L		 5386 if (i.tm.opcode_modifier.size16)
5387 i.suffix = WORD_MNEM_SUFFIX;
5388 else if (i.tm.opcode_modifier.size32)
5389 i.suffix = LONG_MNEM_SUFFIX;
5390 else if (i.tm.opcode_modifier.size64)
5391 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5392 else if (i.reg_operands)
5393 {
5394 /* If there's no instruction mnemonic suffix we try to invent one
5395 based on register operands. */
5396 if (!i.suffix)
5397 {
5398 /* We take i.suffix from the last register operand specified,
5399 Destination register type is more significant than source
381d071f
L		 5400 register type. crc32 in SSE4.2 prefers source register
5401 type. */
5402 if (i.tm.base_opcode == 0xf20f38f1)
5403 {
40fb9820
L		 5404 if (i.types[0].bitfield.reg16)
5405 i.suffix = WORD_MNEM_SUFFIX;
5406 else if (i.types[0].bitfield.reg32)
5407 i.suffix = LONG_MNEM_SUFFIX;
5408 else if (i.types[0].bitfield.reg64)
5409 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5410 }
9344ff29 5411 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5412 {
40fb9820 5413 if (i.types[0].bitfield.reg8)
20592a94
L		 5414 i.suffix = BYTE_MNEM_SUFFIX;
5415 }
381d071f
L		 5416
5417 if (!i.suffix)
5418 {
5419 int op;
5420
20592a94
L		 5421 if (i.tm.base_opcode == 0xf20f38f1
5422 || i.tm.base_opcode == 0xf20f38f0)
5423 {
5424 /* We have to know the operand size for crc32. */
5425 as_bad (_("ambiguous memory operand size for `%s`"),
5426 i.tm.name);
5427 return 0;
5428 }
5429
381d071f 5430 for (op = i.operands; --op >= 0;)
40fb9820 5431 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 5432 {
40fb9820
L		 5433 if (i.types[op].bitfield.reg8)
5434 {
5435 i.suffix = BYTE_MNEM_SUFFIX;
5436 break;
5437 }
5438 else if (i.types[op].bitfield.reg16)
5439 {
5440 i.suffix = WORD_MNEM_SUFFIX;
5441 break;
5442 }
5443 else if (i.types[op].bitfield.reg32)
5444 {
5445 i.suffix = LONG_MNEM_SUFFIX;
5446 break;
5447 }
5448 else if (i.types[op].bitfield.reg64)
5449 {
5450 i.suffix = QWORD_MNEM_SUFFIX;
5451 break;
5452 }
381d071f
L		 5453 }
5454 }
29b0f896
AM		 5455 }
5456 else if (i.suffix == BYTE_MNEM_SUFFIX)
5457 {
2eb952a4
L		 5458 if (intel_syntax
5459 && i.tm.opcode_modifier.ignoresize
5460 && i.tm.opcode_modifier.no_bsuf)
5461 i.suffix = 0;
5462 else if (!check_byte_reg ())
29b0f896
AM		 5463 return 0;
5464 }
5465 else if (i.suffix == LONG_MNEM_SUFFIX)
5466 {
2eb952a4
L		 5467 if (intel_syntax
5468 && i.tm.opcode_modifier.ignoresize
5469 && i.tm.opcode_modifier.no_lsuf)
5470 i.suffix = 0;
5471 else if (!check_long_reg ())
29b0f896
AM		 5472 return 0;
5473 }
5474 else if (i.suffix == QWORD_MNEM_SUFFIX)
5475 {
955e1e6a
L		 5476 if (intel_syntax
5477 && i.tm.opcode_modifier.ignoresize
5478 && i.tm.opcode_modifier.no_qsuf)
5479 i.suffix = 0;
5480 else if (!check_qword_reg ())
29b0f896
AM		 5481 return 0;
5482 }
5483 else if (i.suffix == WORD_MNEM_SUFFIX)
5484 {
2eb952a4
L		 5485 if (intel_syntax
5486 && i.tm.opcode_modifier.ignoresize
5487 && i.tm.opcode_modifier.no_wsuf)
5488 i.suffix = 0;
5489 else if (!check_word_reg ())
29b0f896
AM		 5490 return 0;
5491 }
c0f3af97 5492 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5493 || i.suffix == YMMWORD_MNEM_SUFFIX
5494 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5495 {
43234a1e 5496 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5497 should check if it is a valid suffix. */
5498 }
40fb9820 5499 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5500 /* Do nothing if the instruction is going to ignore the prefix. */
5501 ;
5502 else
5503 abort ();
5504 }
40fb9820 5505 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5506 && !i.suffix
5507 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5508 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5509 {
5510 i.suffix = stackop_size;
5511 }
9306ca4a
JB		 5512 else if (intel_syntax
5513 && !i.suffix
40fb9820
L		 5514 && (i.tm.operand_types[0].bitfield.jumpabsolute
5515 || i.tm.opcode_modifier.jumpbyte
5516 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5517 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5518 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5519 {
5520 switch (flag_code)
5521 {
5522 case CODE_64BIT:
40fb9820 5523 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5524 {
5525 i.suffix = QWORD_MNEM_SUFFIX;
5526 break;
5527 }
1a0670f3 5528 /* Fall through. */
9306ca4a 5529 case CODE_32BIT:
40fb9820 5530 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5531 i.suffix = LONG_MNEM_SUFFIX;
5532 break;
5533 case CODE_16BIT:
40fb9820 5534 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5535 i.suffix = WORD_MNEM_SUFFIX;
5536 break;
5537 }
5538 }
252b5132 5539
9306ca4a 5540 if (!i.suffix)
29b0f896 5541 {
9306ca4a
JB		 5542 if (!intel_syntax)
5543 {
40fb9820 5544 if (i.tm.opcode_modifier.w)
9306ca4a 5545 {
4eed87de
AM		 5546 as_bad (_("no instruction mnemonic suffix given and "
5547 "no register operands; can't size instruction"));
9306ca4a
JB		 5548 return 0;
5549 }
5550 }
5551 else
5552 {
40fb9820 5553 unsigned int suffixes;
7ab9ffdd 5554
40fb9820
L		 5555 suffixes = !i.tm.opcode_modifier.no_bsuf;
5556 if (!i.tm.opcode_modifier.no_wsuf)
5557 suffixes |= 1 << 1;
5558 if (!i.tm.opcode_modifier.no_lsuf)
5559 suffixes |= 1 << 2;
fc4adea1 5560 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5561 suffixes |= 1 << 3;
5562 if (!i.tm.opcode_modifier.no_ssuf)
5563 suffixes |= 1 << 4;
5564 if (!i.tm.opcode_modifier.no_qsuf)
5565 suffixes |= 1 << 5;
5566
5567 /* There are more than suffix matches. */
5568 if (i.tm.opcode_modifier.w
9306ca4a 5569 || ((suffixes & (suffixes - 1))
40fb9820
L		 5570 && !i.tm.opcode_modifier.defaultsize
5571 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5572 {
5573 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5574 return 0;
5575 }
5576 }
29b0f896 5577 }
252b5132 5578
9306ca4a
JB		 5579 /* Change the opcode based on the operand size given by i.suffix;
5580 We don't need to change things for byte insns. */
5581
582d5edd
L		 5582 if (i.suffix
5583 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5584 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5585 && i.suffix != YMMWORD_MNEM_SUFFIX
5586 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5587 {
5588 /* It's not a byte, select word/dword operation. */
40fb9820 5589 if (i.tm.opcode_modifier.w)
29b0f896 5590 {
40fb9820 5591 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5592 i.tm.base_opcode |= 8;
5593 else
5594 i.tm.base_opcode |= 1;
5595 }
0f3f3d8b 5596
29b0f896
AM		 5597 /* Now select between word & dword operations via the operand
5598 size prefix, except for instructions that will ignore this
5599 prefix anyway. */
ca61edf2 5600 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5601 {
ca61edf2
L		 5602 /* The address size override prefix changes the size of the
5603 first operand. */
40fb9820
L		 5604 if ((flag_code == CODE_32BIT
5605 && i.op->regs[0].reg_type.bitfield.reg16)
5606 || (flag_code != CODE_32BIT
5607 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 5608 if (!add_prefix (ADDR_PREFIX_OPCODE))
5609 return 0;
5610 }
5611 else if (i.suffix != QWORD_MNEM_SUFFIX
5612 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5613 && !i.tm.opcode_modifier.ignoresize
5614 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5615 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5616 || (flag_code == CODE_64BIT
40fb9820 5617 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5618 {
5619 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5620
40fb9820 5621 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5622 prefix = ADDR_PREFIX_OPCODE;
252b5132 5623
29b0f896
AM		 5624 if (!add_prefix (prefix))
5625 return 0;
24eab124 5626 }
252b5132 5627
29b0f896
AM		 5628 /* Set mode64 for an operand. */
5629 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5630 && flag_code == CODE_64BIT
40fb9820 5631 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5632 {
5633 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5634 need rex64. cmpxchg8b is also a special case. */
5635 if (! (i.operands == 2
5636 && i.tm.base_opcode == 0x90
5637 && i.tm.extension_opcode == None
0dfbf9d7
L		 5638 && operand_type_equal (&i.types [0], &acc64)
5639 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5640 && ! (i.operands == 1
5641 && i.tm.base_opcode == 0xfc7
5642 && i.tm.extension_opcode == 1
40fb9820
L		 5643 && !operand_type_check (i.types [0], reg)
5644 && operand_type_check (i.types [0], anymem)))
f6bee062 5645 i.rex |= REX_W;
46e883c5 5646 }
3e73aa7c 5647
29b0f896
AM		 5648 /* Size floating point instruction. */
5649 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5650 if (i.tm.opcode_modifier.floatmf)
543613e9 5651 i.tm.base_opcode ^= 4;
29b0f896 5652 }
7ecd2f8b 5653
29b0f896
AM		 5654 return 1;
5655}
3e73aa7c 5656
29b0f896 5657static int
543613e9 5658check_byte_reg (void)
29b0f896
AM		 5659{
5660 int op;
543613e9 5661
29b0f896
AM		 5662 for (op = i.operands; --op >= 0;)
5663 {
5664 /* If this is an eight bit register, it's OK. If it's the 16 or
5665 32 bit version of an eight bit register, we will just use the
5666 low portion, and that's OK too. */
40fb9820 5667 if (i.types[op].bitfield.reg8)
29b0f896
AM		 5668 continue;
5669
5a819eb9
JB		 5670 /* I/O port address operands are OK too. */
5671 if (i.tm.operand_types[op].bitfield.inoutportreg)
5672 continue;
5673
9344ff29
L		 5674 /* crc32 doesn't generate this warning. */
5675 if (i.tm.base_opcode == 0xf20f38f0)
5676 continue;
5677
40fb9820
L		 5678 if ((i.types[op].bitfield.reg16
5679 || i.types[op].bitfield.reg32
5680 || i.types[op].bitfield.reg64)
5a819eb9
JB		 5681 && i.op[op].regs->reg_num < 4
5682 /* Prohibit these changes in 64bit mode, since the lowering
5683 would be more complicated. */
5684 && flag_code != CODE_64BIT)
29b0f896 5685 {
29b0f896 5686#if REGISTER_WARNINGS
5a819eb9 5687 if (!quiet_warnings)
a540244d
L		 5688 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5689 register_prefix,
40fb9820 5690 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 5691 ? REGNAM_AL - REGNAM_AX
5692 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5693 register_prefix,
29b0f896
AM		 5694 i.op[op].regs->reg_name,
5695 i.suffix);
5696#endif
5697 continue;
5698 }
5699 /* Any other register is bad. */
40fb9820
L		 5700 if (i.types[op].bitfield.reg16
5701 || i.types[op].bitfield.reg32
5702 || i.types[op].bitfield.reg64
5703 || i.types[op].bitfield.regmmx
5704 || i.types[op].bitfield.regxmm
c0f3af97 5705 || i.types[op].bitfield.regymm
43234a1e 5706 || i.types[op].bitfield.regzmm
40fb9820
L		 5707 || i.types[op].bitfield.sreg2
5708 || i.types[op].bitfield.sreg3
5709 || i.types[op].bitfield.control
5710 || i.types[op].bitfield.debug
5711 || i.types[op].bitfield.test
5712 || i.types[op].bitfield.floatreg
5713 || i.types[op].bitfield.floatacc)
29b0f896 5714 {
a540244d
L		 5715 as_bad (_("`%s%s' not allowed with `%s%c'"),
5716 register_prefix,
29b0f896
AM		 5717 i.op[op].regs->reg_name,
5718 i.tm.name,
5719 i.suffix);
5720 return 0;
5721 }
5722 }
5723 return 1;
5724}
5725
5726static int
e3bb37b5 5727check_long_reg (void)
29b0f896
AM		 5728{
5729 int op;
5730
5731 for (op = i.operands; --op >= 0;)
5732 /* Reject eight bit registers, except where the template requires
5733 them. (eg. movzb) */
40fb9820
L		 5734 if (i.types[op].bitfield.reg8
5735 && (i.tm.operand_types[op].bitfield.reg16
5736 || i.tm.operand_types[op].bitfield.reg32
5737 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5738 {
a540244d
L		 5739 as_bad (_("`%s%s' not allowed with `%s%c'"),
5740 register_prefix,
29b0f896
AM		 5741 i.op[op].regs->reg_name,
5742 i.tm.name,
5743 i.suffix);
5744 return 0;
5745 }
e4630f71 5746 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5747 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5748 && i.types[op].bitfield.reg16
5749 && (i.tm.operand_types[op].bitfield.reg32
5750 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5751 {
5752 /* Prohibit these changes in the 64bit mode, since the
5753 lowering is more complicated. */
5754 if (flag_code == CODE_64BIT)
252b5132 5755 {
2b5d6a91 5756 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5757 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5758 i.suffix);
5759 return 0;
252b5132 5760 }
29b0f896 5761#if REGISTER_WARNINGS
cecf1424
JB		 5762 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5763 register_prefix,
5764 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5765 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5766#endif
252b5132 5767 }
e4630f71 5768 /* Warn if the r prefix on a general reg is present. */
40fb9820
L		 5769 else if (i.types[op].bitfield.reg64
5770 && (i.tm.operand_types[op].bitfield.reg32
5771 || i.tm.operand_types[op].bitfield.acc))
252b5132 5772 {
34828aad 5773 if (intel_syntax
ca61edf2 5774 && i.tm.opcode_modifier.toqword
40fb9820 5775 && !i.types[0].bitfield.regxmm)
34828aad 5776 {
ca61edf2 5777 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5778 i.suffix = QWORD_MNEM_SUFFIX;
5779 }
5780 else
5781 {
2b5d6a91 5782 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5783 register_prefix, i.op[op].regs->reg_name,
5784 i.suffix);
5785 return 0;
5786 }
29b0f896
AM		 5787 }
5788 return 1;
5789}
252b5132 5790
29b0f896 5791static int
e3bb37b5 5792check_qword_reg (void)
29b0f896
AM		 5793{
5794 int op;
252b5132 5795
29b0f896
AM		 5796 for (op = i.operands; --op >= 0; )
5797 /* Reject eight bit registers, except where the template requires
5798 them. (eg. movzb) */
40fb9820
L		 5799 if (i.types[op].bitfield.reg8
5800 && (i.tm.operand_types[op].bitfield.reg16
5801 || i.tm.operand_types[op].bitfield.reg32
5802 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5803 {
a540244d
L		 5804 as_bad (_("`%s%s' not allowed with `%s%c'"),
5805 register_prefix,
29b0f896
AM		 5806 i.op[op].regs->reg_name,
5807 i.tm.name,
5808 i.suffix);
5809 return 0;
5810 }
e4630f71 5811 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 5812 else if ((i.types[op].bitfield.reg16
5813 || i.types[op].bitfield.reg32)
33d0ab95 5814 && (i.tm.operand_types[op].bitfield.reg64
40fb9820 5815 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5816 {
5817 /* Prohibit these changes in the 64bit mode, since the
5818 lowering is more complicated. */
34828aad 5819 if (intel_syntax
ca61edf2 5820 && i.tm.opcode_modifier.todword
40fb9820 5821 && !i.types[0].bitfield.regxmm)
34828aad 5822 {
ca61edf2 5823 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5824 i.suffix = LONG_MNEM_SUFFIX;
5825 }
5826 else
5827 {
2b5d6a91 5828 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5829 register_prefix, i.op[op].regs->reg_name,
5830 i.suffix);
5831 return 0;
5832 }
252b5132 5833 }
29b0f896
AM		 5834 return 1;
5835}
252b5132 5836
29b0f896 5837static int
e3bb37b5 5838check_word_reg (void)
29b0f896
AM		 5839{
5840 int op;
5841 for (op = i.operands; --op >= 0;)
5842 /* Reject eight bit registers, except where the template requires
5843 them. (eg. movzb) */
40fb9820
L		 5844 if (i.types[op].bitfield.reg8
5845 && (i.tm.operand_types[op].bitfield.reg16
5846 || i.tm.operand_types[op].bitfield.reg32
5847 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5848 {
a540244d
L		 5849 as_bad (_("`%s%s' not allowed with `%s%c'"),
5850 register_prefix,
29b0f896
AM		 5851 i.op[op].regs->reg_name,
5852 i.tm.name,
5853 i.suffix);
5854 return 0;
5855 }
e4630f71 5856 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5857 else if ((!quiet_warnings || flag_code == CODE_64BIT)
e4630f71
JB		 5858 && (i.types[op].bitfield.reg32
5859 || i.types[op].bitfield.reg64)
40fb9820
L		 5860 && (i.tm.operand_types[op].bitfield.reg16
5861 || i.tm.operand_types[op].bitfield.acc))
252b5132 5862 {
29b0f896
AM		 5863 /* Prohibit these changes in the 64bit mode, since the
5864 lowering is more complicated. */
5865 if (flag_code == CODE_64BIT)
252b5132 5866 {
2b5d6a91 5867 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5868 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5869 i.suffix);
5870 return 0;
252b5132 5871 }
29b0f896 5872#if REGISTER_WARNINGS
cecf1424
JB		 5873 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5874 register_prefix,
5875 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5876 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5877#endif
5878 }
5879 return 1;
5880}
252b5132 5881
29b0f896 5882static int
40fb9820 5883update_imm (unsigned int j)
29b0f896 5884{
bc0844ae 5885 i386_operand_type overlap = i.types[j];
40fb9820
L		 5886 if ((overlap.bitfield.imm8
5887 || overlap.bitfield.imm8s
5888 || overlap.bitfield.imm16
5889 || overlap.bitfield.imm32
5890 || overlap.bitfield.imm32s
5891 || overlap.bitfield.imm64)
0dfbf9d7
L		 5892 && !operand_type_equal (&overlap, &imm8)
5893 && !operand_type_equal (&overlap, &imm8s)
5894 && !operand_type_equal (&overlap, &imm16)
5895 && !operand_type_equal (&overlap, &imm32)
5896 && !operand_type_equal (&overlap, &imm32s)
5897 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5898 {
5899 if (i.suffix)
5900 {
40fb9820
L		 5901 i386_operand_type temp;
5902
0dfbf9d7 5903 operand_type_set (&temp, 0);
7ab9ffdd 5904 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5905 {
5906 temp.bitfield.imm8 = overlap.bitfield.imm8;
5907 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5908 }
5909 else if (i.suffix == WORD_MNEM_SUFFIX)
5910 temp.bitfield.imm16 = overlap.bitfield.imm16;
5911 else if (i.suffix == QWORD_MNEM_SUFFIX)
5912 {
5913 temp.bitfield.imm64 = overlap.bitfield.imm64;
5914 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5915 }
5916 else
5917 temp.bitfield.imm32 = overlap.bitfield.imm32;
5918 overlap = temp;
29b0f896 5919 }
0dfbf9d7
L		 5920 else if (operand_type_equal (&overlap, &imm16_32_32s)
5921 || operand_type_equal (&overlap, &imm16_32)
5922 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5923 {
40fb9820 5924 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5925 overlap = imm16;
40fb9820 5926 else
65da13b5 5927 overlap = imm32s;
29b0f896 5928 }
0dfbf9d7
L		 5929 if (!operand_type_equal (&overlap, &imm8)
5930 && !operand_type_equal (&overlap, &imm8s)
5931 && !operand_type_equal (&overlap, &imm16)
5932 && !operand_type_equal (&overlap, &imm32)
5933 && !operand_type_equal (&overlap, &imm32s)
5934 && !operand_type_equal (&overlap, &imm64))
29b0f896 5935 {
4eed87de
AM		 5936 as_bad (_("no instruction mnemonic suffix given; "
5937 "can't determine immediate size"));
29b0f896
AM		 5938 return 0;
5939 }
5940 }
40fb9820 5941 i.types[j] = overlap;
29b0f896 5942
40fb9820
L		 5943 return 1;
5944}
5945
5946static int
5947finalize_imm (void)
5948{
bc0844ae 5949 unsigned int j, n;
29b0f896 5950
bc0844ae
L		 5951 /* Update the first 2 immediate operands. */
5952 n = i.operands > 2 ? 2 : i.operands;
5953 if (n)
5954 {
5955 for (j = 0; j < n; j++)
5956 if (update_imm (j) == 0)
5957 return 0;
40fb9820 5958
bc0844ae
L		 5959 /* The 3rd operand can't be immediate operand. */
5960 gas_assert (operand_type_check (i.types[2], imm) == 0);
5961 }
29b0f896
AM		 5962
5963 return 1;
5964}
5965
c0f3af97
L		 5966static int
5967bad_implicit_operand (int xmm)
5968{
91d6fa6a
NC		 5969 const char *ireg = xmm ? "xmm0" : "ymm0";
5970
c0f3af97
L		 5971 if (intel_syntax)
5972 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5973 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5974 else
5975 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5976 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5977 return 0;
5978}
5979
29b0f896 5980static int
e3bb37b5 5981process_operands (void)
29b0f896
AM		 5982{
5983 /* Default segment register this instruction will use for memory
5984 accesses. 0 means unknown. This is only for optimizing out
5985 unnecessary segment overrides. */
5986 const seg_entry *default_seg = 0;
5987
2426c15f 5988 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5989 {
91d6fa6a
NC		 5990 unsigned int dupl = i.operands;
5991 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5992 unsigned int j;
5993
c0f3af97 5994 /* The destination must be an xmm register. */
9c2799c2 5995 gas_assert (i.reg_operands
91d6fa6a 5996 && MAX_OPERANDS > dupl
7ab9ffdd 5997 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5998
5999 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 6000 {
c0f3af97 6001 /* The first operand is implicit and must be xmm0. */
9c2799c2 6002 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 6003 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 6004 return bad_implicit_operand (1);
6005
8cd7925b 6006 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 6007 {
6008 /* Keep xmm0 for instructions with VEX prefix and 3
6009 sources. */
6010 goto duplicate;
6011 }
e2ec9d29 6012 else
c0f3af97
L		 6013 {
6014 /* We remove the first xmm0 and keep the number of
6015 operands unchanged, which in fact duplicates the
6016 destination. */
6017 for (j = 1; j < i.operands; j++)
6018 {
6019 i.op[j - 1] = i.op[j];
6020 i.types[j - 1] = i.types[j];
6021 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6022 }
6023 }
6024 }
6025 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 6026 {
91d6fa6a 6027 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 6028 && (i.tm.opcode_modifier.vexsources
6029 == VEX3SOURCES));
c0f3af97
L		 6030
6031 /* Add the implicit xmm0 for instructions with VEX prefix
6032 and 3 sources. */
6033 for (j = i.operands; j > 0; j--)
6034 {
6035 i.op[j] = i.op[j - 1];
6036 i.types[j] = i.types[j - 1];
6037 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6038 }
6039 i.op[0].regs
6040 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 6041 i.types[0] = regxmm;
c0f3af97
L		 6042 i.tm.operand_types[0] = regxmm;
6043
6044 i.operands += 2;
6045 i.reg_operands += 2;
6046 i.tm.operands += 2;
6047
91d6fa6a 6048 dupl++;
c0f3af97 6049 dest++;
91d6fa6a
NC		 6050 i.op[dupl] = i.op[dest];
6051 i.types[dupl] = i.types[dest];
6052 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 6053 }
c0f3af97
L		 6054 else
6055 {
6056duplicate:
6057 i.operands++;
6058 i.reg_operands++;
6059 i.tm.operands++;
6060
91d6fa6a
NC		 6061 i.op[dupl] = i.op[dest];
6062 i.types[dupl] = i.types[dest];
6063 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 6064 }
6065
6066 if (i.tm.opcode_modifier.immext)
6067 process_immext ();
6068 }
6069 else if (i.tm.opcode_modifier.firstxmm0)
6070 {
6071 unsigned int j;
6072
43234a1e 6073 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
9c2799c2 6074 gas_assert (i.reg_operands
7ab9ffdd 6075 && (operand_type_equal (&i.types[0], &regxmm)
43234a1e
L		 6076 || operand_type_equal (&i.types[0], &regymm)
6077 || operand_type_equal (&i.types[0], &regzmm)));
4c692bc7 6078 if (register_number (i.op[0].regs) != 0)
c0f3af97 6079 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 6080
6081 for (j = 1; j < i.operands; j++)
6082 {
6083 i.op[j - 1] = i.op[j];
6084 i.types[j - 1] = i.types[j];
6085
6086 /* We need to adjust fields in i.tm since they are used by
6087 build_modrm_byte. */
6088 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6089 }
6090
e2ec9d29
L		 6091 i.operands--;
6092 i.reg_operands--;
e2ec9d29
L		 6093 i.tm.operands--;
6094 }
920d2ddc
IT		 6095 else if (i.tm.opcode_modifier.implicitquadgroup)
6096 {
6097 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6098 gas_assert (i.operands >= 2
6099 && (operand_type_equal (&i.types[1], &regxmm)
6100 || operand_type_equal (&i.types[1], &regymm)
6101 || operand_type_equal (&i.types[1], &regzmm)));
6102 unsigned int regnum = register_number (i.op[1].regs);
6103 unsigned int first_reg_in_group = regnum & ~3;
6104 unsigned int last_reg_in_group = first_reg_in_group + 3;
6105 if (regnum != first_reg_in_group) {
6106 as_warn (_("the second source register `%s%s' implicitly denotes"
6107 " `%s%.3s%d' to `%s%.3s%d' source group in `%s'"),
6108 register_prefix, i.op[1].regs->reg_name,
6109 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6110 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6111 i.tm.name);
6112 }
6113 }
e2ec9d29
L		 6114 else if (i.tm.opcode_modifier.regkludge)
6115 {
6116 /* The imul $imm, %reg instruction is converted into
6117 imul $imm, %reg, %reg, and the clr %reg instruction
6118 is converted into xor %reg, %reg. */
6119
6120 unsigned int first_reg_op;
6121
6122 if (operand_type_check (i.types[0], reg))
6123 first_reg_op = 0;
6124 else
6125 first_reg_op = 1;
6126 /* Pretend we saw the extra register operand. */
9c2799c2 6127 gas_assert (i.reg_operands == 1
7ab9ffdd 6128 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 6129 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6130 i.types[first_reg_op + 1] = i.types[first_reg_op];
6131 i.operands++;
6132 i.reg_operands++;
29b0f896
AM		 6133 }
6134
40fb9820 6135 if (i.tm.opcode_modifier.shortform)
29b0f896 6136 {
40fb9820
L		 6137 if (i.types[0].bitfield.sreg2
6138 || i.types[0].bitfield.sreg3)
29b0f896 6139 {
4eed87de
AM		 6140 if (i.tm.base_opcode == POP_SEG_SHORT
6141 && i.op[0].regs->reg_num == 1)
29b0f896 6142 {
a87af027 6143 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 6144 return 0;
29b0f896 6145 }
4eed87de
AM		 6146 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6147 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 6148 i.rex |= REX_B;
4eed87de
AM		 6149 }
6150 else
6151 {
7ab9ffdd 6152 /* The register or float register operand is in operand
85f10a01 6153 0 or 1. */
40fb9820 6154 unsigned int op;
7ab9ffdd
L		 6155
6156 if (i.types[0].bitfield.floatreg
6157 || operand_type_check (i.types[0], reg))
6158 op = 0;
6159 else
6160 op = 1;
4eed87de
AM		 6161 /* Register goes in low 3 bits of opcode. */
6162 i.tm.base_opcode |= i.op[op].regs->reg_num;
6163 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 6164 i.rex |= REX_B;
40fb9820 6165 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 6166 {
4eed87de
AM		 6167 /* Warn about some common errors, but press on regardless.
6168 The first case can be generated by gcc (<= 2.8.1). */
6169 if (i.operands == 2)
6170 {
6171 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 6172 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 6173 register_prefix, i.op[!intel_syntax].regs->reg_name,
6174 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 6175 }
6176 else
6177 {
6178 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 6179 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6180 register_prefix, i.op[0].regs->reg_name);
4eed87de 6181 }
29b0f896
AM		 6182 }
6183 }
6184 }
40fb9820 6185 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 6186 {
6187 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 6188 must be put into the modrm byte). Now, we make the modrm and
6189 index base bytes based on all the info we've collected. */
29b0f896
AM		 6190
6191 default_seg = build_modrm_byte ();
6192 }
8a2ed489 6193 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 6194 {
6195 default_seg = &ds;
6196 }
40fb9820 6197 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 6198 {
6199 /* For the string instructions that allow a segment override
6200 on one of their operands, the default segment is ds. */
6201 default_seg = &ds;
6202 }
6203
75178d9d
L		 6204 if (i.tm.base_opcode == 0x8d /* lea */
6205 && i.seg[0]
6206 && !quiet_warnings)
30123838 6207 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 6208
6209 /* If a segment was explicitly specified, and the specified segment
6210 is not the default, use an opcode prefix to select it. If we
6211 never figured out what the default segment is, then default_seg
6212 will be zero at this point, and the specified segment prefix will
6213 always be used. */
29b0f896
AM		 6214 if ((i.seg[0]) && (i.seg[0] != default_seg))
6215 {
6216 if (!add_prefix (i.seg[0]->seg_prefix))
6217 return 0;
6218 }
6219 return 1;
6220}
6221
6222static const seg_entry *
e3bb37b5 6223build_modrm_byte (void)
29b0f896
AM		 6224{
6225 const seg_entry *default_seg = 0;
c0f3af97 6226 unsigned int source, dest;
8cd7925b 6227 int vex_3_sources;
c0f3af97
L		 6228
6229 /* The first operand of instructions with VEX prefix and 3 sources
6230 must be VEX_Imm4. */
8cd7925b 6231 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 6232 if (vex_3_sources)
6233 {
91d6fa6a 6234 unsigned int nds, reg_slot;
4c2c6516 6235 expressionS *exp;
c0f3af97 6236
922d8de8 6237 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 6238 && i.tm.opcode_modifier.immext)
6239 {
6240 dest = i.operands - 2;
6241 gas_assert (dest == 3);
6242 }
922d8de8 6243 else
a683cc34 6244 dest = i.operands - 1;
c0f3af97 6245 nds = dest - 1;
922d8de8 6246
a683cc34
SP		 6247 /* There are 2 kinds of instructions:
6248 1. 5 operands: 4 register operands or 3 register operands
6249 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 6250 VexW0 or VexW1. The destination must be either XMM, YMM or
6251 ZMM register.
a683cc34
SP		 6252 2. 4 operands: 4 register operands or 3 register operands
6253 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 6254 gas_assert ((i.reg_operands == 4
a683cc34
SP		 6255 || (i.reg_operands == 3 && i.mem_operands == 1))
6256 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6257 && (i.tm.opcode_modifier.veximmext
6258 || (i.imm_operands == 1
6259 && i.types[0].bitfield.vec_imm4
6260 && (i.tm.opcode_modifier.vexw == VEXW0
6261 || i.tm.opcode_modifier.vexw == VEXW1)
6262 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 6263 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
6264 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 6265
6266 if (i.imm_operands == 0)
6267 {
6268 /* When there is no immediate operand, generate an 8bit
6269 immediate operand to encode the first operand. */
6270 exp = &im_expressions[i.imm_operands++];
6271 i.op[i.operands].imms = exp;
6272 i.types[i.operands] = imm8;
6273 i.operands++;
6274 /* If VexW1 is set, the first operand is the source and
6275 the second operand is encoded in the immediate operand. */
6276 if (i.tm.opcode_modifier.vexw == VEXW1)
6277 {
6278 source = 0;
6279 reg_slot = 1;
6280 }
6281 else
6282 {
6283 source = 1;
6284 reg_slot = 0;
6285 }
6286
6287 /* FMA swaps REG and NDS. */
6288 if (i.tm.cpu_flags.bitfield.cpufma)
6289 {
6290 unsigned int tmp;
6291 tmp = reg_slot;
6292 reg_slot = nds;
6293 nds = tmp;
6294 }
6295
24981e7b
L		 6296 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6297 &regxmm)
a683cc34 6298 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6299 &regymm)
6300 || operand_type_equal (&i.tm.operand_types[reg_slot],
6301 &regzmm));
a683cc34 6302 exp->X_op = O_constant;
4c692bc7 6303 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6304 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6305 }
922d8de8 6306 else
a683cc34
SP		 6307 {
6308 unsigned int imm_slot;
6309
6310 if (i.tm.opcode_modifier.vexw == VEXW0)
6311 {
6312 /* If VexW0 is set, the third operand is the source and
6313 the second operand is encoded in the immediate
6314 operand. */
6315 source = 2;
6316 reg_slot = 1;
6317 }
6318 else
6319 {
6320 /* VexW1 is set, the second operand is the source and
6321 the third operand is encoded in the immediate
6322 operand. */
6323 source = 1;
6324 reg_slot = 2;
6325 }
6326
6327 if (i.tm.opcode_modifier.immext)
6328 {
33eaf5de 6329 /* When ImmExt is set, the immediate byte is the last
a683cc34
SP		 6330 operand. */
6331 imm_slot = i.operands - 1;
6332 source--;
6333 reg_slot--;
6334 }
6335 else
6336 {
6337 imm_slot = 0;
6338
6339 /* Turn on Imm8 so that output_imm will generate it. */
6340 i.types[imm_slot].bitfield.imm8 = 1;
6341 }
6342
24981e7b
L		 6343 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6344 &regxmm)
6345 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6346 &regymm)
6347 || operand_type_equal (&i.tm.operand_types[reg_slot],
6348 &regzmm));
a683cc34 6349 i.op[imm_slot].imms->X_add_number
4c692bc7 6350 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6351 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6352 }
6353
6354 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6355 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 6356 &regymm)
6357 || operand_type_equal (&i.tm.operand_types[nds],
6358 &regzmm));
dae39acc 6359 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6360 }
6361 else
6362 source = dest = 0;
29b0f896
AM		 6363
6364 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6365 implicit registers do not count. If there are 3 register
6366 operands, it must be a instruction with VexNDS. For a
6367 instruction with VexNDD, the destination register is encoded
6368 in VEX prefix. If there are 4 register operands, it must be
6369 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6370 if (i.mem_operands == 0
6371 && ((i.reg_operands == 2
2426c15f 6372 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6373 || (i.reg_operands == 3
2426c15f 6374 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6375 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6376 {
cab737b9
L		 6377 switch (i.operands)
6378 {
6379 case 2:
6380 source = 0;
6381 break;
6382 case 3:
c81128dc
L		 6383 /* When there are 3 operands, one of them may be immediate,
6384 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6385 the first operand must be shift count register (cl) or it
6386 is an instruction with VexNDS. */
9c2799c2 6387 gas_assert (i.imm_operands == 1
7ab9ffdd 6388 || (i.imm_operands == 0
2426c15f 6389 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6390 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6391 if (operand_type_check (i.types[0], imm)
6392 || i.types[0].bitfield.shiftcount)
6393 source = 1;
6394 else
6395 source = 0;
cab737b9
L		 6396 break;
6397 case 4:
368d64cc
L		 6398 /* When there are 4 operands, the first two must be 8bit
6399 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6400 one.
6401
6402 For instructions with VexNDS, if the first operand
6403 an imm8, the source operand is the 2nd one. If the last
6404 operand is imm8, the source operand is the first one. */
9c2799c2 6405 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6406 && i.types[0].bitfield.imm8
6407 && i.types[1].bitfield.imm8)
2426c15f 6408 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6409 && i.imm_operands == 1
6410 && (i.types[0].bitfield.imm8
43234a1e
L		 6411 || i.types[i.operands - 1].bitfield.imm8
6412 || i.rounding)));
9f2670f2
L		 6413 if (i.imm_operands == 2)
6414 source = 2;
6415 else
c0f3af97
L		 6416 {
6417 if (i.types[0].bitfield.imm8)
6418 source = 1;
6419 else
6420 source = 0;
6421 }
c0f3af97
L		 6422 break;
6423 case 5:
43234a1e
L		 6424 if (i.tm.opcode_modifier.evex)
6425 {
6426 /* For EVEX instructions, when there are 5 operands, the
6427 first one must be immediate operand. If the second one
6428 is immediate operand, the source operand is the 3th
6429 one. If the last one is immediate operand, the source
6430 operand is the 2nd one. */
6431 gas_assert (i.imm_operands == 2
6432 && i.tm.opcode_modifier.sae
6433 && operand_type_check (i.types[0], imm));
6434 if (operand_type_check (i.types[1], imm))
6435 source = 2;
6436 else if (operand_type_check (i.types[4], imm))
6437 source = 1;
6438 else
6439 abort ();
6440 }
cab737b9
L		 6441 break;
6442 default:
6443 abort ();
6444 }
6445
c0f3af97
L		 6446 if (!vex_3_sources)
6447 {
6448 dest = source + 1;
6449
43234a1e
L		 6450 /* RC/SAE operand could be between DEST and SRC. That happens
6451 when one operand is GPR and the other one is XMM/YMM/ZMM
6452 register. */
6453 if (i.rounding && i.rounding->operand == (int) dest)
6454 dest++;
6455
2426c15f 6456 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6457 {
43234a1e
L		 6458 /* For instructions with VexNDS, the register-only source
6459 operand must be 32/64bit integer, XMM, YMM or ZMM
6460 register. It is encoded in VEX prefix. We need to
6461 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6462
6463 i386_operand_type op;
6464 unsigned int vvvv;
6465
6466 /* Check register-only source operand when two source
6467 operands are swapped. */
6468 if (!i.tm.operand_types[source].bitfield.baseindex
6469 && i.tm.operand_types[dest].bitfield.baseindex)
6470 {
6471 vvvv = source;
6472 source = dest;
6473 }
6474 else
6475 vvvv = dest;
6476
6477 op = i.tm.operand_types[vvvv];
fa99fab2 6478 op.bitfield.regmem = 0;
c0f3af97 6479 if ((dest + 1) >= i.operands
ac4eb736
AM		 6480 || (!op.bitfield.reg32
6481 && op.bitfield.reg64
f12dc422 6482 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6483 && !operand_type_equal (&op, &regymm)
6484 && !operand_type_equal (&op, &regzmm)
6485 && !operand_type_equal (&op, &regmask)))
c0f3af97 6486 abort ();
f12dc422 6487 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6488 dest++;
6489 }
6490 }
29b0f896
AM		 6491
6492 i.rm.mode = 3;
6493 /* One of the register operands will be encoded in the i.tm.reg
6494 field, the other in the combined i.tm.mode and i.tm.regmem
6495 fields. If no form of this instruction supports a memory
6496 destination operand, then we assume the source operand may
6497 sometimes be a memory operand and so we need to store the
6498 destination in the i.rm.reg field. */
40fb9820
L		 6499 if (!i.tm.operand_types[dest].bitfield.regmem
6500 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6501 {
6502 i.rm.reg = i.op[dest].regs->reg_num;
6503 i.rm.regmem = i.op[source].regs->reg_num;
6504 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6505 i.rex |= REX_R;
43234a1e
L		 6506 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6507 i.vrex |= REX_R;
29b0f896 6508 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6509 i.rex |= REX_B;
43234a1e
L		 6510 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6511 i.vrex |= REX_B;
29b0f896
AM		 6512 }
6513 else
6514 {
6515 i.rm.reg = i.op[source].regs->reg_num;
6516 i.rm.regmem = i.op[dest].regs->reg_num;
6517 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6518 i.rex |= REX_B;
43234a1e
L		 6519 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6520 i.vrex |= REX_B;
29b0f896 6521 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6522 i.rex |= REX_R;
43234a1e
L		 6523 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6524 i.vrex |= REX_R;
29b0f896 6525 }
161a04f6 6526 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6527 {
40fb9820
L		 6528 if (!i.types[0].bitfield.control
6529 && !i.types[1].bitfield.control)
c4a530c5 6530 abort ();
161a04f6 6531 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6532 add_prefix (LOCK_PREFIX_OPCODE);
6533 }
29b0f896
AM		 6534 }
6535 else
6536 { /* If it's not 2 reg operands... */
c0f3af97
L		 6537 unsigned int mem;
6538
29b0f896
AM		 6539 if (i.mem_operands)
6540 {
6541 unsigned int fake_zero_displacement = 0;
99018f42 6542 unsigned int op;
4eed87de 6543
7ab9ffdd
L		 6544 for (op = 0; op < i.operands; op++)
6545 if (operand_type_check (i.types[op], anymem))
6546 break;
7ab9ffdd 6547 gas_assert (op < i.operands);
29b0f896 6548
6c30d220
L		 6549 if (i.tm.opcode_modifier.vecsib)
6550 {
6551 if (i.index_reg->reg_num == RegEiz
6552 || i.index_reg->reg_num == RegRiz)
6553 abort ();
6554
6555 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6556 if (!i.base_reg)
6557 {
6558 i.sib.base = NO_BASE_REGISTER;
6559 i.sib.scale = i.log2_scale_factor;
43234a1e
L		 6560 /* No Vec_Disp8 if there is no base. */
6561 i.types[op].bitfield.vec_disp8 = 0;
6c30d220
L		 6562 i.types[op].bitfield.disp8 = 0;
6563 i.types[op].bitfield.disp16 = 0;
6564 i.types[op].bitfield.disp64 = 0;
6565 if (flag_code != CODE_64BIT)
6566 {
6567 /* Must be 32 bit */
6568 i.types[op].bitfield.disp32 = 1;
6569 i.types[op].bitfield.disp32s = 0;
6570 }
6571 else
6572 {
6573 i.types[op].bitfield.disp32 = 0;
6574 i.types[op].bitfield.disp32s = 1;
6575 }
6576 }
6577 i.sib.index = i.index_reg->reg_num;
6578 if ((i.index_reg->reg_flags & RegRex) != 0)
6579 i.rex |= REX_X;
43234a1e
L		 6580 if ((i.index_reg->reg_flags & RegVRex) != 0)
6581 i.vrex |= REX_X;
6c30d220
L		 6582 }
6583
29b0f896
AM		 6584 default_seg = &ds;
6585
6586 if (i.base_reg == 0)
6587 {
6588 i.rm.mode = 0;
6589 if (!i.disp_operands)
6c30d220
L		 6590 {
6591 fake_zero_displacement = 1;
6592 /* Instructions with VSIB byte need 32bit displacement
6593 if there is no base register. */
6594 if (i.tm.opcode_modifier.vecsib)
6595 i.types[op].bitfield.disp32 = 1;
6596 }
29b0f896
AM		 6597 if (i.index_reg == 0)
6598 {
6c30d220 6599 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6600 /* Operand is just <disp> */
20f0a1fc 6601 if (flag_code == CODE_64BIT)
29b0f896
AM		 6602 {
6603 /* 64bit mode overwrites the 32bit absolute
6604 addressing by RIP relative addressing and
6605 absolute addressing is encoded by one of the
6606 redundant SIB forms. */
6607 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6608 i.sib.base = NO_BASE_REGISTER;
6609 i.sib.index = NO_INDEX_REGISTER;
fc225355 6610 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6611 ? disp32s : disp32);
20f0a1fc 6612 }
fc225355
L		 6613 else if ((flag_code == CODE_16BIT)
6614 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6615 {
6616 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6617 i.types[op] = disp16;
20f0a1fc
NC		 6618 }
6619 else
6620 {
6621 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6622 i.types[op] = disp32;
29b0f896
AM		 6623 }
6624 }
6c30d220 6625 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6626 {
6c30d220 6627 /* !i.base_reg && i.index_reg */
db51cc60
L		 6628 if (i.index_reg->reg_num == RegEiz
6629 || i.index_reg->reg_num == RegRiz)
6630 i.sib.index = NO_INDEX_REGISTER;
6631 else
6632 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6633 i.sib.base = NO_BASE_REGISTER;
6634 i.sib.scale = i.log2_scale_factor;
6635 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
43234a1e
L		 6636 /* No Vec_Disp8 if there is no base. */
6637 i.types[op].bitfield.vec_disp8 = 0;
40fb9820
L		 6638 i.types[op].bitfield.disp8 = 0;
6639 i.types[op].bitfield.disp16 = 0;
6640 i.types[op].bitfield.disp64 = 0;
29b0f896 6641 if (flag_code != CODE_64BIT)
40fb9820
L		 6642 {
6643 /* Must be 32 bit */
6644 i.types[op].bitfield.disp32 = 1;
6645 i.types[op].bitfield.disp32s = 0;
6646 }
29b0f896 6647 else
40fb9820
L		 6648 {
6649 i.types[op].bitfield.disp32 = 0;
6650 i.types[op].bitfield.disp32s = 1;
6651 }
29b0f896 6652 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6653 i.rex |= REX_X;
29b0f896
AM		 6654 }
6655 }
6656 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6657 else if (i.base_reg->reg_num == RegRip ||
6658 i.base_reg->reg_num == RegEip)
29b0f896 6659 {
6c30d220 6660 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6661 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6662 i.types[op].bitfield.disp8 = 0;
6663 i.types[op].bitfield.disp16 = 0;
6664 i.types[op].bitfield.disp32 = 0;
6665 i.types[op].bitfield.disp32s = 1;
6666 i.types[op].bitfield.disp64 = 0;
43234a1e 6667 i.types[op].bitfield.vec_disp8 = 0;
71903a11 6668 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6669 if (! i.disp_operands)
6670 fake_zero_displacement = 1;
29b0f896 6671 }
40fb9820 6672 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 6673 {
6c30d220 6674 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6675 switch (i.base_reg->reg_num)
6676 {
6677 case 3: /* (%bx) */
6678 if (i.index_reg == 0)
6679 i.rm.regmem = 7;
6680 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6681 i.rm.regmem = i.index_reg->reg_num - 6;
6682 break;
6683 case 5: /* (%bp) */
6684 default_seg = &ss;
6685 if (i.index_reg == 0)
6686 {
6687 i.rm.regmem = 6;
40fb9820 6688 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6689 {
6690 /* fake (%bp) into 0(%bp) */
43234a1e
L		 6691 if (i.tm.operand_types[op].bitfield.vec_disp8)
6692 i.types[op].bitfield.vec_disp8 = 1;
6693 else
6694 i.types[op].bitfield.disp8 = 1;
252b5132 6695 fake_zero_displacement = 1;
29b0f896
AM		 6696 }
6697 }
6698 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6699 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6700 break;
6701 default: /* (%si) -> 4 or (%di) -> 5 */
6702 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6703 }
6704 i.rm.mode = mode_from_disp_size (i.types[op]);
6705 }
6706 else /* i.base_reg and 32/64 bit mode */
6707 {
6708 if (flag_code == CODE_64BIT
40fb9820
L		 6709 && operand_type_check (i.types[op], disp))
6710 {
6711 i386_operand_type temp;
0dfbf9d7 6712 operand_type_set (&temp, 0);
40fb9820 6713 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
43234a1e
L		 6714 temp.bitfield.vec_disp8
6715 = i.types[op].bitfield.vec_disp8;
40fb9820
L		 6716 i.types[op] = temp;
6717 if (i.prefix[ADDR_PREFIX] == 0)
6718 i.types[op].bitfield.disp32s = 1;
6719 else
6720 i.types[op].bitfield.disp32 = 1;
6721 }
20f0a1fc 6722
6c30d220
L		 6723 if (!i.tm.opcode_modifier.vecsib)
6724 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6725 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6726 i.rex |= REX_B;
29b0f896
AM		 6727 i.sib.base = i.base_reg->reg_num;
6728 /* x86-64 ignores REX prefix bit here to avoid decoder
6729 complications. */
848930b2
JB		 6730 if (!(i.base_reg->reg_flags & RegRex)
6731 && (i.base_reg->reg_num == EBP_REG_NUM
6732 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6733 default_seg = &ss;
848930b2 6734 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6735 {
848930b2 6736 fake_zero_displacement = 1;
43234a1e
L		 6737 if (i.tm.operand_types [op].bitfield.vec_disp8)
6738 i.types[op].bitfield.vec_disp8 = 1;
6739 else
6740 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6741 }
6742 i.sib.scale = i.log2_scale_factor;
6743 if (i.index_reg == 0)
6744 {
6c30d220 6745 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6746 /* <disp>(%esp) becomes two byte modrm with no index
6747 register. We've already stored the code for esp
6748 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6749 Any base register besides %esp will not use the
6750 extra modrm byte. */
6751 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6752 }
6c30d220 6753 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6754 {
db51cc60
L		 6755 if (i.index_reg->reg_num == RegEiz
6756 || i.index_reg->reg_num == RegRiz)
6757 i.sib.index = NO_INDEX_REGISTER;
6758 else
6759 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6760 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6761 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6762 i.rex |= REX_X;
29b0f896 6763 }
67a4f2b7
AO		 6764
6765 if (i.disp_operands
6766 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6767 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6768 i.rm.mode = 0;
6769 else
a501d77e
L		 6770 {
6771 if (!fake_zero_displacement
6772 && !i.disp_operands
6773 && i.disp_encoding)
6774 {
6775 fake_zero_displacement = 1;
6776 if (i.disp_encoding == disp_encoding_8bit)
6777 i.types[op].bitfield.disp8 = 1;
6778 else
6779 i.types[op].bitfield.disp32 = 1;
6780 }
6781 i.rm.mode = mode_from_disp_size (i.types[op]);
6782 }
29b0f896 6783 }
252b5132 6784
29b0f896
AM		 6785 if (fake_zero_displacement)
6786 {
6787 /* Fakes a zero displacement assuming that i.types[op]
6788 holds the correct displacement size. */
6789 expressionS *exp;
6790
9c2799c2 6791 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6792 exp = &disp_expressions[i.disp_operands++];
6793 i.op[op].disps = exp;
6794 exp->X_op = O_constant;
6795 exp->X_add_number = 0;
6796 exp->X_add_symbol = (symbolS *) 0;
6797 exp->X_op_symbol = (symbolS *) 0;
6798 }
c0f3af97
L		 6799
6800 mem = op;
29b0f896 6801 }
c0f3af97
L		 6802 else
6803 mem = ~0;
252b5132 6804
8c43a48b 6805 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6806 {
6807 if (operand_type_check (i.types[0], imm))
6808 i.vex.register_specifier = NULL;
6809 else
6810 {
6811 /* VEX.vvvv encodes one of the sources when the first
6812 operand is not an immediate. */
1ef99a7b 6813 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6814 i.vex.register_specifier = i.op[0].regs;
6815 else
6816 i.vex.register_specifier = i.op[1].regs;
6817 }
6818
6819 /* Destination is a XMM register encoded in the ModRM.reg
6820 and VEX.R bit. */
6821 i.rm.reg = i.op[2].regs->reg_num;
6822 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6823 i.rex |= REX_R;
6824
6825 /* ModRM.rm and VEX.B encodes the other source. */
6826 if (!i.mem_operands)
6827 {
6828 i.rm.mode = 3;
6829
1ef99a7b 6830 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6831 i.rm.regmem = i.op[1].regs->reg_num;
6832 else
6833 i.rm.regmem = i.op[0].regs->reg_num;
6834
6835 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6836 i.rex |= REX_B;
6837 }
6838 }
2426c15f 6839 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6840 {
6841 i.vex.register_specifier = i.op[2].regs;
6842 if (!i.mem_operands)
6843 {
6844 i.rm.mode = 3;
6845 i.rm.regmem = i.op[1].regs->reg_num;
6846 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6847 i.rex |= REX_B;
6848 }
6849 }
29b0f896
AM		 6850 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6851 (if any) based on i.tm.extension_opcode. Again, we must be
6852 careful to make sure that segment/control/debug/test/MMX
6853 registers are coded into the i.rm.reg field. */
f88c9eb0 6854 else if (i.reg_operands)
29b0f896 6855 {
99018f42 6856 unsigned int op;
7ab9ffdd
L		 6857 unsigned int vex_reg = ~0;
6858
6859 for (op = 0; op < i.operands; op++)
6860 if (i.types[op].bitfield.reg8
6861 || i.types[op].bitfield.reg16
6862 || i.types[op].bitfield.reg32
6863 || i.types[op].bitfield.reg64
6864 || i.types[op].bitfield.regmmx
6865 || i.types[op].bitfield.regxmm
6866 || i.types[op].bitfield.regymm
7e8b059b 6867 || i.types[op].bitfield.regbnd
43234a1e
L		 6868 || i.types[op].bitfield.regzmm
6869 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6870 || i.types[op].bitfield.sreg2
6871 || i.types[op].bitfield.sreg3
6872 || i.types[op].bitfield.control
6873 || i.types[op].bitfield.debug
6874 || i.types[op].bitfield.test)
6875 break;
c0209578 6876
7ab9ffdd
L		 6877 if (vex_3_sources)
6878 op = dest;
2426c15f 6879 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6880 {
6881 /* For instructions with VexNDS, the register-only
6882 source operand is encoded in VEX prefix. */
6883 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6884
7ab9ffdd 6885 if (op > mem)
c0f3af97 6886 {
7ab9ffdd
L		 6887 vex_reg = op++;
6888 gas_assert (op < i.operands);
c0f3af97
L		 6889 }
6890 else
c0f3af97 6891 {
f12dc422
L		 6892 /* Check register-only source operand when two source
6893 operands are swapped. */
6894 if (!i.tm.operand_types[op].bitfield.baseindex
6895 && i.tm.operand_types[op + 1].bitfield.baseindex)
6896 {
6897 vex_reg = op;
6898 op += 2;
6899 gas_assert (mem == (vex_reg + 1)
6900 && op < i.operands);
6901 }
6902 else
6903 {
6904 vex_reg = op + 1;
6905 gas_assert (vex_reg < i.operands);
6906 }
c0f3af97 6907 }
7ab9ffdd 6908 }
2426c15f 6909 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6910 {
f12dc422 6911 /* For instructions with VexNDD, the register destination
7ab9ffdd 6912 is encoded in VEX prefix. */
f12dc422
L		 6913 if (i.mem_operands == 0)
6914 {
6915 /* There is no memory operand. */
6916 gas_assert ((op + 2) == i.operands);
6917 vex_reg = op + 1;
6918 }
6919 else
8d63c93e 6920 {
f12dc422
L		 6921 /* There are only 2 operands. */
6922 gas_assert (op < 2 && i.operands == 2);
6923 vex_reg = 1;
6924 }
7ab9ffdd
L		 6925 }
6926 else
6927 gas_assert (op < i.operands);
99018f42 6928
7ab9ffdd
L		 6929 if (vex_reg != (unsigned int) ~0)
6930 {
f12dc422 6931 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6932
f12dc422
L		 6933 if (type->bitfield.reg32 != 1
6934 && type->bitfield.reg64 != 1
6935 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6936 && !operand_type_equal (type, &regymm)
6937 && !operand_type_equal (type, &regzmm)
6938 && !operand_type_equal (type, &regmask))
7ab9ffdd 6939 abort ();
f88c9eb0 6940
7ab9ffdd
L		 6941 i.vex.register_specifier = i.op[vex_reg].regs;
6942 }
6943
1b9f0c97
L		 6944 /* Don't set OP operand twice. */
6945 if (vex_reg != op)
7ab9ffdd 6946 {
1b9f0c97
L		 6947 /* If there is an extension opcode to put here, the
6948 register number must be put into the regmem field. */
6949 if (i.tm.extension_opcode != None)
6950 {
6951 i.rm.regmem = i.op[op].regs->reg_num;
6952 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6953 i.rex |= REX_B;
43234a1e
L		 6954 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6955 i.vrex |= REX_B;
1b9f0c97
L		 6956 }
6957 else
6958 {
6959 i.rm.reg = i.op[op].regs->reg_num;
6960 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6961 i.rex |= REX_R;
43234a1e
L		 6962 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6963 i.vrex |= REX_R;
1b9f0c97 6964 }
7ab9ffdd 6965 }
252b5132 6966
29b0f896
AM		 6967 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6968 must set it to 3 to indicate this is a register operand
6969 in the regmem field. */
6970 if (!i.mem_operands)
6971 i.rm.mode = 3;
6972 }
252b5132 6973
29b0f896 6974 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6975 if (i.tm.extension_opcode != None)
29b0f896
AM		 6976 i.rm.reg = i.tm.extension_opcode;
6977 }
6978 return default_seg;
6979}
252b5132 6980
29b0f896 6981static void
e3bb37b5 6982output_branch (void)
29b0f896
AM		 6983{
6984 char *p;
f8a5c266 6985 int size;
29b0f896
AM		 6986 int code16;
6987 int prefix;
6988 relax_substateT subtype;
6989 symbolS *sym;
6990 offsetT off;
6991
f8a5c266 6992 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6993 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6994
6995 prefix = 0;
6996 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6997 {
29b0f896
AM		 6998 prefix = 1;
6999 i.prefixes -= 1;
7000 code16 ^= CODE16;
252b5132 7001 }
29b0f896
AM		 7002 /* Pentium4 branch hints. */
7003 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7004 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 7005 {
29b0f896
AM		 7006 prefix++;
7007 i.prefixes--;
7008 }
7009 if (i.prefix[REX_PREFIX] != 0)
7010 {
7011 prefix++;
7012 i.prefixes--;
2f66722d
AM		 7013 }
7014
7e8b059b
L		 7015 /* BND prefixed jump. */
7016 if (i.prefix[BND_PREFIX] != 0)
7017 {
7018 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7019 i.prefixes -= 1;
7020 }
7021
29b0f896
AM		 7022 if (i.prefixes != 0 && !intel_syntax)
7023 as_warn (_("skipping prefixes on this instruction"));
7024
7025 /* It's always a symbol; End frag & setup for relax.
7026 Make sure there is enough room in this frag for the largest
7027 instruction we may generate in md_convert_frag. This is 2
7028 bytes for the opcode and room for the prefix and largest
7029 displacement. */
7030 frag_grow (prefix + 2 + 4);
7031 /* Prefix and 1 opcode byte go in fr_fix. */
7032 p = frag_more (prefix + 1);
7033 if (i.prefix[DATA_PREFIX] != 0)
7034 *p++ = DATA_PREFIX_OPCODE;
7035 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7036 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7037 *p++ = i.prefix[SEG_PREFIX];
7038 if (i.prefix[REX_PREFIX] != 0)
7039 *p++ = i.prefix[REX_PREFIX];
7040 *p = i.tm.base_opcode;
7041
7042 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 7043 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 7044 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 7045 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 7046 else
f8a5c266 7047 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 7048 subtype |= code16;
3e73aa7c 7049
29b0f896
AM		 7050 sym = i.op[0].disps->X_add_symbol;
7051 off = i.op[0].disps->X_add_number;
3e73aa7c 7052
29b0f896
AM		 7053 if (i.op[0].disps->X_op != O_constant
7054 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 7055 {
29b0f896
AM		 7056 /* Handle complex expressions. */
7057 sym = make_expr_symbol (i.op[0].disps);
7058 off = 0;
7059 }
3e73aa7c 7060
29b0f896
AM		 7061 /* 1 possible extra opcode + 4 byte displacement go in var part.
7062 Pass reloc in fr_var. */
d258b828 7063 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 7064}
3e73aa7c 7065
29b0f896 7066static void
e3bb37b5 7067output_jump (void)
29b0f896
AM		 7068{
7069 char *p;
7070 int size;
3e02c1cc 7071 fixS *fixP;
29b0f896 7072
40fb9820 7073 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 7074 {
7075 /* This is a loop or jecxz type instruction. */
7076 size = 1;
7077 if (i.prefix[ADDR_PREFIX] != 0)
7078 {
7079 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7080 i.prefixes -= 1;
7081 }
7082 /* Pentium4 branch hints. */
7083 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7084 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7085 {
7086 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7087 i.prefixes--;
3e73aa7c
JH		 7088 }
7089 }
29b0f896
AM		 7090 else
7091 {
7092 int code16;
3e73aa7c 7093
29b0f896
AM		 7094 code16 = 0;
7095 if (flag_code == CODE_16BIT)
7096 code16 = CODE16;
3e73aa7c 7097
29b0f896
AM		 7098 if (i.prefix[DATA_PREFIX] != 0)
7099 {
7100 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7101 i.prefixes -= 1;
7102 code16 ^= CODE16;
7103 }
252b5132 7104
29b0f896
AM		 7105 size = 4;
7106 if (code16)
7107 size = 2;
7108 }
9fcc94b6 7109
29b0f896
AM		 7110 if (i.prefix[REX_PREFIX] != 0)
7111 {
7112 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7113 i.prefixes -= 1;
7114 }
252b5132 7115
7e8b059b
L		 7116 /* BND prefixed jump. */
7117 if (i.prefix[BND_PREFIX] != 0)
7118 {
7119 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7120 i.prefixes -= 1;
7121 }
7122
29b0f896
AM		 7123 if (i.prefixes != 0 && !intel_syntax)
7124 as_warn (_("skipping prefixes on this instruction"));
e0890092 7125
42164a71
L		 7126 p = frag_more (i.tm.opcode_length + size);
7127 switch (i.tm.opcode_length)
7128 {
7129 case 2:
7130 *p++ = i.tm.base_opcode >> 8;
1a0670f3 7131 /* Fall through. */
42164a71
L		 7132 case 1:
7133 *p++ = i.tm.base_opcode;
7134 break;
7135 default:
7136 abort ();
7137 }
e0890092 7138
3e02c1cc 7139 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 7140 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3e02c1cc
AM		 7141
7142 /* All jumps handled here are signed, but don't use a signed limit
7143 check for 32 and 16 bit jumps as we want to allow wrap around at
7144 4G and 64k respectively. */
7145 if (size == 1)
7146 fixP->fx_signed = 1;
29b0f896 7147}
e0890092 7148
29b0f896 7149static void
e3bb37b5 7150output_interseg_jump (void)
29b0f896
AM		 7151{
7152 char *p;
7153 int size;
7154 int prefix;
7155 int code16;
252b5132 7156
29b0f896
AM		 7157 code16 = 0;
7158 if (flag_code == CODE_16BIT)
7159 code16 = CODE16;
a217f122 7160
29b0f896
AM		 7161 prefix = 0;
7162 if (i.prefix[DATA_PREFIX] != 0)
7163 {
7164 prefix = 1;
7165 i.prefixes -= 1;
7166 code16 ^= CODE16;
7167 }
7168 if (i.prefix[REX_PREFIX] != 0)
7169 {
7170 prefix++;
7171 i.prefixes -= 1;
7172 }
252b5132 7173
29b0f896
AM		 7174 size = 4;
7175 if (code16)
7176 size = 2;
252b5132 7177
29b0f896
AM		 7178 if (i.prefixes != 0 && !intel_syntax)
7179 as_warn (_("skipping prefixes on this instruction"));
252b5132 7180
29b0f896
AM		 7181 /* 1 opcode; 2 segment; offset */
7182 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 7183
29b0f896
AM		 7184 if (i.prefix[DATA_PREFIX] != 0)
7185 *p++ = DATA_PREFIX_OPCODE;
252b5132 7186
29b0f896
AM		 7187 if (i.prefix[REX_PREFIX] != 0)
7188 *p++ = i.prefix[REX_PREFIX];
252b5132 7189
29b0f896
AM		 7190 *p++ = i.tm.base_opcode;
7191 if (i.op[1].imms->X_op == O_constant)
7192 {
7193 offsetT n = i.op[1].imms->X_add_number;
252b5132 7194
29b0f896
AM		 7195 if (size == 2
7196 && !fits_in_unsigned_word (n)
7197 && !fits_in_signed_word (n))
7198 {
7199 as_bad (_("16-bit jump out of range"));
7200 return;
7201 }
7202 md_number_to_chars (p, n, size);
7203 }
7204 else
7205 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 7206 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 7207 if (i.op[0].imms->X_op != O_constant)
7208 as_bad (_("can't handle non absolute segment in `%s'"),
7209 i.tm.name);
7210 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7211}
a217f122 7212
29b0f896 7213static void
e3bb37b5 7214output_insn (void)
29b0f896 7215{
2bbd9c25
JJ		 7216 fragS *insn_start_frag;
7217 offsetT insn_start_off;
7218
29b0f896
AM		 7219 /* Tie dwarf2 debug info to the address at the start of the insn.
7220 We can't do this after the insn has been output as the current
7221 frag may have been closed off. eg. by frag_var. */
7222 dwarf2_emit_insn (0);
7223
2bbd9c25
JJ		 7224 insn_start_frag = frag_now;
7225 insn_start_off = frag_now_fix ();
7226
29b0f896 7227 /* Output jumps. */
40fb9820 7228 if (i.tm.opcode_modifier.jump)
29b0f896 7229 output_branch ();
40fb9820
L		 7230 else if (i.tm.opcode_modifier.jumpbyte
7231 || i.tm.opcode_modifier.jumpdword)
29b0f896 7232 output_jump ();
40fb9820 7233 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 7234 output_interseg_jump ();
7235 else
7236 {
7237 /* Output normal instructions here. */
7238 char *p;
7239 unsigned char *q;
47465058 7240 unsigned int j;
331d2d0d 7241 unsigned int prefix;
4dffcebc 7242
e4e00185
AS		 7243 if (avoid_fence
7244 && i.tm.base_opcode == 0xfae
7245 && i.operands == 1
7246 && i.imm_operands == 1
7247 && (i.op[0].imms->X_add_number == 0xe8
7248 || i.op[0].imms->X_add_number == 0xf0
7249 || i.op[0].imms->X_add_number == 0xf8))
7250 {
7251 /* Encode lfence, mfence, and sfence as
7252 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7253 offsetT val = 0x240483f0ULL;
7254 p = frag_more (5);
7255 md_number_to_chars (p, val, 5);
7256 return;
7257 }
7258
d022bddd
IT		 7259 /* Some processors fail on LOCK prefix. This options makes
7260 assembler ignore LOCK prefix and serves as a workaround. */
7261 if (omit_lock_prefix)
7262 {
7263 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7264 return;
7265 i.prefix[LOCK_PREFIX] = 0;
7266 }
7267
43234a1e
L		 7268 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7269 don't need the explicit prefix. */
7270 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 7271 {
c0f3af97 7272 switch (i.tm.opcode_length)
bc4bd9ab 7273 {
c0f3af97
L		 7274 case 3:
7275 if (i.tm.base_opcode & 0xff000000)
4dffcebc 7276 {
c0f3af97
L		 7277 prefix = (i.tm.base_opcode >> 24) & 0xff;
7278 goto check_prefix;
7279 }
7280 break;
7281 case 2:
7282 if ((i.tm.base_opcode & 0xff0000) != 0)
7283 {
7284 prefix = (i.tm.base_opcode >> 16) & 0xff;
7285 if (i.tm.cpu_flags.bitfield.cpupadlock)
7286 {
4dffcebc 7287check_prefix:
c0f3af97 7288 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 7289 || (i.prefix[REP_PREFIX]
c0f3af97
L		 7290 != REPE_PREFIX_OPCODE))
7291 add_prefix (prefix);
7292 }
7293 else
4dffcebc
L		 7294 add_prefix (prefix);
7295 }
c0f3af97
L		 7296 break;
7297 case 1:
7298 break;
7299 default:
7300 abort ();
bc4bd9ab 7301 }
c0f3af97 7302
6d19a37a 7303#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 7304 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7305 R_X86_64_GOTTPOFF relocation so that linker can safely
7306 perform IE->LE optimization. */
7307 if (x86_elf_abi == X86_64_X32_ABI
7308 && i.operands == 2
7309 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7310 && i.prefix[REX_PREFIX] == 0)
7311 add_prefix (REX_OPCODE);
6d19a37a 7312#endif
cf61b747 7313
c0f3af97
L		 7314 /* The prefix bytes. */
7315 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7316 if (*q)
7317 FRAG_APPEND_1_CHAR (*q);
0f10071e 7318 }
ae5c1c7b 7319 else
c0f3af97
L		 7320 {
7321 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7322 if (*q)
7323 switch (j)
7324 {
7325 case REX_PREFIX:
7326 /* REX byte is encoded in VEX prefix. */
7327 break;
7328 case SEG_PREFIX:
7329 case ADDR_PREFIX:
7330 FRAG_APPEND_1_CHAR (*q);
7331 break;
7332 default:
7333 /* There should be no other prefixes for instructions
7334 with VEX prefix. */
7335 abort ();
7336 }
7337
43234a1e
L		 7338 /* For EVEX instructions i.vrex should become 0 after
7339 build_evex_prefix. For VEX instructions upper 16 registers
7340 aren't available, so VREX should be 0. */
7341 if (i.vrex)
7342 abort ();
c0f3af97
L		 7343 /* Now the VEX prefix. */
7344 p = frag_more (i.vex.length);
7345 for (j = 0; j < i.vex.length; j++)
7346 p[j] = i.vex.bytes[j];
7347 }
252b5132 7348
29b0f896 7349 /* Now the opcode; be careful about word order here! */
4dffcebc 7350 if (i.tm.opcode_length == 1)
29b0f896
AM		 7351 {
7352 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7353 }
7354 else
7355 {
4dffcebc 7356 switch (i.tm.opcode_length)
331d2d0d 7357 {
43234a1e
L		 7358 case 4:
7359 p = frag_more (4);
7360 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7361 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7362 break;
4dffcebc 7363 case 3:
331d2d0d
L		 7364 p = frag_more (3);
7365 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7366 break;
7367 case 2:
7368 p = frag_more (2);
7369 break;
7370 default:
7371 abort ();
7372 break;
331d2d0d 7373 }
0f10071e 7374
29b0f896
AM		 7375 /* Put out high byte first: can't use md_number_to_chars! */
7376 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7377 *p = i.tm.base_opcode & 0xff;
7378 }
3e73aa7c 7379
29b0f896 7380 /* Now the modrm byte and sib byte (if present). */
40fb9820 7381 if (i.tm.opcode_modifier.modrm)
29b0f896 7382 {
4a3523fa
L		 7383 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7384 | i.rm.reg << 3
7385 | i.rm.mode << 6));
29b0f896
AM		 7386 /* If i.rm.regmem == ESP (4)
7387 && i.rm.mode != (Register mode)
7388 && not 16 bit
7389 ==> need second modrm byte. */
7390 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7391 && i.rm.mode != 3
40fb9820 7392 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 7393 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7394 | i.sib.index << 3
7395 | i.sib.scale << 6));
29b0f896 7396 }
3e73aa7c 7397
29b0f896 7398 if (i.disp_operands)
2bbd9c25 7399 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7400
29b0f896 7401 if (i.imm_operands)
2bbd9c25 7402 output_imm (insn_start_frag, insn_start_off);
29b0f896 7403 }
252b5132 7404
29b0f896
AM		 7405#ifdef DEBUG386
7406 if (flag_debug)
7407 {
7b81dfbb 7408 pi ("" /*line*/, &i);
29b0f896
AM		 7409 }
7410#endif /* DEBUG386 */
7411}
252b5132 7412
e205caa7
L		 7413/* Return the size of the displacement operand N. */
7414
7415static int
7416disp_size (unsigned int n)
7417{
7418 int size = 4;
43234a1e
L		 7419
7420 /* Vec_Disp8 has to be 8bit. */
7421 if (i.types[n].bitfield.vec_disp8)
7422 size = 1;
7423 else if (i.types[n].bitfield.disp64)
40fb9820
L		 7424 size = 8;
7425 else if (i.types[n].bitfield.disp8)
7426 size = 1;
7427 else if (i.types[n].bitfield.disp16)
7428 size = 2;
e205caa7
L		 7429 return size;
7430}
7431
7432/* Return the size of the immediate operand N. */
7433
7434static int
7435imm_size (unsigned int n)
7436{
7437 int size = 4;
40fb9820
L		 7438 if (i.types[n].bitfield.imm64)
7439 size = 8;
7440 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7441 size = 1;
7442 else if (i.types[n].bitfield.imm16)
7443 size = 2;
e205caa7
L		 7444 return size;
7445}
7446
29b0f896 7447static void
64e74474 7448output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7449{
7450 char *p;
7451 unsigned int n;
252b5132 7452
29b0f896
AM		 7453 for (n = 0; n < i.operands; n++)
7454 {
43234a1e
L		 7455 if (i.types[n].bitfield.vec_disp8
7456 || operand_type_check (i.types[n], disp))
29b0f896
AM		 7457 {
7458 if (i.op[n].disps->X_op == O_constant)
7459 {
e205caa7 7460 int size = disp_size (n);
43234a1e 7461 offsetT val = i.op[n].disps->X_add_number;
252b5132 7462
43234a1e
L		 7463 if (i.types[n].bitfield.vec_disp8)
7464 val >>= i.memshift;
7465 val = offset_in_range (val, size);
29b0f896
AM		 7466 p = frag_more (size);
7467 md_number_to_chars (p, val, size);
7468 }
7469 else
7470 {
f86103b7 7471 enum bfd_reloc_code_real reloc_type;
e205caa7 7472 int size = disp_size (n);
40fb9820 7473 int sign = i.types[n].bitfield.disp32s;
29b0f896 7474 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
02a86693 7475 fixS *fixP;
29b0f896 7476
e205caa7 7477 /* We can't have 8 bit displacement here. */
9c2799c2 7478 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7479
29b0f896
AM		 7480 /* The PC relative address is computed relative
7481 to the instruction boundary, so in case immediate
7482 fields follows, we need to adjust the value. */
7483 if (pcrel && i.imm_operands)
7484 {
29b0f896 7485 unsigned int n1;
e205caa7 7486 int sz = 0;
252b5132 7487
29b0f896 7488 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7489 if (operand_type_check (i.types[n1], imm))
252b5132 7490 {
e205caa7
L		 7491 /* Only one immediate is allowed for PC
7492 relative address. */
9c2799c2 7493 gas_assert (sz == 0);
e205caa7
L		 7494 sz = imm_size (n1);
7495 i.op[n].disps->X_add_number -= sz;
252b5132 7496 }
29b0f896 7497 /* We should find the immediate. */
9c2799c2 7498 gas_assert (sz != 0);
29b0f896 7499 }
520dc8e8 7500
29b0f896 7501 p = frag_more (size);
d258b828 7502 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7503 if (GOT_symbol
2bbd9c25 7504 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7505 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7506 || reloc_type == BFD_RELOC_X86_64_32S
7507 || (reloc_type == BFD_RELOC_64
7508 && object_64bit))
d6ab8113
JB		 7509 && (i.op[n].disps->X_op == O_symbol
7510 || (i.op[n].disps->X_op == O_add
7511 && ((symbol_get_value_expression
7512 (i.op[n].disps->X_op_symbol)->X_op)
7513 == O_subtract))))
7514 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7515 {
7516 offsetT add;
7517
7518 if (insn_start_frag == frag_now)
7519 add = (p - frag_now->fr_literal) - insn_start_off;
7520 else
7521 {
7522 fragS *fr;
7523
7524 add = insn_start_frag->fr_fix - insn_start_off;
7525 for (fr = insn_start_frag->fr_next;
7526 fr && fr != frag_now; fr = fr->fr_next)
7527 add += fr->fr_fix;
7528 add += p - frag_now->fr_literal;
7529 }
7530
4fa24527 7531 if (!object_64bit)
7b81dfbb
AJ		 7532 {
7533 reloc_type = BFD_RELOC_386_GOTPC;
7534 i.op[n].imms->X_add_number += add;
7535 }
7536 else if (reloc_type == BFD_RELOC_64)
7537 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7538 else
7b81dfbb
AJ		 7539 /* Don't do the adjustment for x86-64, as there
7540 the pcrel addressing is relative to the _next_
7541 insn, and that is taken care of in other code. */
d6ab8113 7542 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7543 }
02a86693
L		 7544 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7545 size, i.op[n].disps, pcrel,
7546 reloc_type);
7547 /* Check for "call/jmp *mem", "mov mem, %reg",
7548 "test %reg, mem" and "binop mem, %reg" where binop
7549 is one of adc, add, and, cmp, or, sbb, sub, xor
0cb4071e
L		 7550 instructions. Always generate R_386_GOT32X for
7551 "sym*GOT" operand in 32-bit mode. */
7552 if ((generate_relax_relocations
7553 || (!object_64bit
7554 && i.rm.mode == 0
7555 && i.rm.regmem == 5))
7556 && (i.rm.mode == 2
7557 || (i.rm.mode == 0 && i.rm.regmem == 5))
02a86693
L		 7558 && ((i.operands == 1
7559 && i.tm.base_opcode == 0xff
7560 && (i.rm.reg == 2 || i.rm.reg == 4))
7561 || (i.operands == 2
7562 && (i.tm.base_opcode == 0x8b
7563 || i.tm.base_opcode == 0x85
7564 || (i.tm.base_opcode & 0xc7) == 0x03))))
7565 {
7566 if (object_64bit)
7567 {
7568 fixP->fx_tcbit = i.rex != 0;
7569 if (i.base_reg
7570 && (i.base_reg->reg_num == RegRip
7571 || i.base_reg->reg_num == RegEip))
7572 fixP->fx_tcbit2 = 1;
7573 }
7574 else
7575 fixP->fx_tcbit2 = 1;
7576 }
29b0f896
AM		 7577 }
7578 }
7579 }
7580}
252b5132 7581
29b0f896 7582static void
64e74474 7583output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7584{
7585 char *p;
7586 unsigned int n;
252b5132 7587
29b0f896
AM		 7588 for (n = 0; n < i.operands; n++)
7589 {
43234a1e
L		 7590 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7591 if (i.rounding && (int) n == i.rounding->operand)
7592 continue;
7593
40fb9820 7594 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7595 {
7596 if (i.op[n].imms->X_op == O_constant)
7597 {
e205caa7 7598 int size = imm_size (n);
29b0f896 7599 offsetT val;
b4cac588 7600
29b0f896
AM		 7601 val = offset_in_range (i.op[n].imms->X_add_number,
7602 size);
7603 p = frag_more (size);
7604 md_number_to_chars (p, val, size);
7605 }
7606 else
7607 {
7608 /* Not absolute_section.
7609 Need a 32-bit fixup (don't support 8bit
7610 non-absolute imms). Try to support other
7611 sizes ... */
f86103b7 7612 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7613 int size = imm_size (n);
7614 int sign;
29b0f896 7615
40fb9820 7616 if (i.types[n].bitfield.imm32s
a7d61044 7617 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7618 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7619 sign = 1;
e205caa7
L		 7620 else
7621 sign = 0;
520dc8e8 7622
29b0f896 7623 p = frag_more (size);
d258b828 7624 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 7625
2bbd9c25
JJ		 7626 /* This is tough to explain. We end up with this one if we
7627 * have operands that look like
7628 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7629 * obtain the absolute address of the GOT, and it is strongly
7630 * preferable from a performance point of view to avoid using
7631 * a runtime relocation for this. The actual sequence of
7632 * instructions often look something like:
7633 *
7634 * call .L66
7635 * .L66:
7636 * popl %ebx
7637 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7638 *
7639 * The call and pop essentially return the absolute address
7640 * of the label .L66 and store it in %ebx. The linker itself
7641 * will ultimately change the first operand of the addl so
7642 * that %ebx points to the GOT, but to keep things simple, the
7643 * .o file must have this operand set so that it generates not
7644 * the absolute address of .L66, but the absolute address of
7645 * itself. This allows the linker itself simply treat a GOTPC
7646 * relocation as asking for a pcrel offset to the GOT to be
7647 * added in, and the addend of the relocation is stored in the
7648 * operand field for the instruction itself.
7649 *
7650 * Our job here is to fix the operand so that it would add
7651 * the correct offset so that %ebx would point to itself. The
7652 * thing that is tricky is that .-.L66 will point to the
7653 * beginning of the instruction, so we need to further modify
7654 * the operand so that it will point to itself. There are
7655 * other cases where you have something like:
7656 *
7657 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7658 *
7659 * and here no correction would be required. Internally in
7660 * the assembler we treat operands of this form as not being
7661 * pcrel since the '.' is explicitly mentioned, and I wonder
7662 * whether it would simplify matters to do it this way. Who
7663 * knows. In earlier versions of the PIC patches, the
7664 * pcrel_adjust field was used to store the correction, but
7665 * since the expression is not pcrel, I felt it would be
7666 * confusing to do it this way. */
7667
d6ab8113 7668 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7669 || reloc_type == BFD_RELOC_X86_64_32S
7670 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7671 && GOT_symbol
7672 && GOT_symbol == i.op[n].imms->X_add_symbol
7673 && (i.op[n].imms->X_op == O_symbol
7674 || (i.op[n].imms->X_op == O_add
7675 && ((symbol_get_value_expression
7676 (i.op[n].imms->X_op_symbol)->X_op)
7677 == O_subtract))))
7678 {
2bbd9c25
JJ		 7679 offsetT add;
7680
7681 if (insn_start_frag == frag_now)
7682 add = (p - frag_now->fr_literal) - insn_start_off;
7683 else
7684 {
7685 fragS *fr;
7686
7687 add = insn_start_frag->fr_fix - insn_start_off;
7688 for (fr = insn_start_frag->fr_next;
7689 fr && fr != frag_now; fr = fr->fr_next)
7690 add += fr->fr_fix;
7691 add += p - frag_now->fr_literal;
7692 }
7693
4fa24527 7694 if (!object_64bit)
d6ab8113 7695 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7696 else if (size == 4)
d6ab8113 7697 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7698 else if (size == 8)
7699 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7700 i.op[n].imms->X_add_number += add;
29b0f896 7701 }
29b0f896
AM		 7702 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7703 i.op[n].imms, 0, reloc_type);
7704 }
7705 }
7706 }
252b5132
RH		 7707}
7708\f
d182319b
JB		 7709/* x86_cons_fix_new is called via the expression parsing code when a
7710 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 7711static int cons_sign = -1;
7712
7713void
e3bb37b5 7714x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 7715 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 7716{
d258b828 7717 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 7718
7719#ifdef TE_PE
7720 if (exp->X_op == O_secrel)
7721 {
7722 exp->X_op = O_symbol;
7723 r = BFD_RELOC_32_SECREL;
7724 }
7725#endif
7726
7727 fix_new_exp (frag, off, len, exp, 0, r);
7728}
7729
357d1bd8
L		 7730/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7731 purpose of the `.dc.a' internal pseudo-op. */
7732
7733int
7734x86_address_bytes (void)
7735{
7736 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7737 return 4;
7738 return stdoutput->arch_info->bits_per_address / 8;
7739}
7740
d382c579
TG		 7741#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7742 || defined (LEX_AT)
d258b828 7743# define lex_got(reloc, adjust, types) NULL
718ddfc0 7744#else
f3c180ae
AM		 7745/* Parse operands of the form
7746 <symbol>@GOTOFF+<nnn>
7747 and similar .plt or .got references.
7748
7749 If we find one, set up the correct relocation in RELOC and copy the
7750 input string, minus the `@GOTOFF' into a malloc'd buffer for
7751 parsing by the calling routine. Return this buffer, and if ADJUST
7752 is non-null set it to the length of the string we removed from the
7753 input line. Otherwise return NULL. */
7754static char *
91d6fa6a 7755lex_got (enum bfd_reloc_code_real *rel,
64e74474 7756 int *adjust,
d258b828 7757 i386_operand_type *types)
f3c180ae 7758{
7b81dfbb
AJ		 7759 /* Some of the relocations depend on the size of what field is to
7760 be relocated. But in our callers i386_immediate and i386_displacement
7761 we don't yet know the operand size (this will be set by insn
7762 matching). Hence we record the word32 relocation here,
7763 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7764 static const struct {
7765 const char *str;
cff8d58a 7766 int len;
4fa24527 7767 const enum bfd_reloc_code_real rel[2];
40fb9820 7768 const i386_operand_type types64;
f3c180ae 7769 } gotrel[] = {
8ce3d284 7770#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7771 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7772 BFD_RELOC_SIZE32 },
7773 OPERAND_TYPE_IMM32_64 },
8ce3d284 7774#endif
cff8d58a
L		 7775 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7776 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7777 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7778 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7779 BFD_RELOC_X86_64_PLT32 },
40fb9820 7780 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7781 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7782 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7783 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7784 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7785 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7786 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7787 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7788 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7789 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7790 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7791 BFD_RELOC_X86_64_TLSGD },
40fb9820 7792 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7793 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7794 _dummy_first_bfd_reloc_code_real },
40fb9820 7795 OPERAND_TYPE_NONE },
cff8d58a
L		 7796 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7797 BFD_RELOC_X86_64_TLSLD },
40fb9820 7798 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7799 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7800 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7801 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7802 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7803 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7804 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7805 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7806 _dummy_first_bfd_reloc_code_real },
40fb9820 7807 OPERAND_TYPE_NONE },
cff8d58a
L		 7808 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7809 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7810 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7811 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7812 _dummy_first_bfd_reloc_code_real },
40fb9820 7813 OPERAND_TYPE_NONE },
cff8d58a
L		 7814 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7815 _dummy_first_bfd_reloc_code_real },
40fb9820 7816 OPERAND_TYPE_NONE },
cff8d58a
L		 7817 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7818 BFD_RELOC_X86_64_GOT32 },
40fb9820 7819 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7820 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7821 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7822 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7823 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7824 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7825 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7826 };
7827 char *cp;
7828 unsigned int j;
7829
d382c579 7830#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7831 if (!IS_ELF)
7832 return NULL;
d382c579 7833#endif
718ddfc0 7834
f3c180ae 7835 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7836 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7837 return NULL;
7838
47465058 7839 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7840 {
cff8d58a 7841 int len = gotrel[j].len;
28f81592 7842 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7843 {
4fa24527 7844 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7845 {
28f81592
AM		 7846 int first, second;
7847 char *tmpbuf, *past_reloc;
f3c180ae 7848
91d6fa6a 7849 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7850
3956db08
JB		 7851 if (types)
7852 {
7853 if (flag_code != CODE_64BIT)
40fb9820
L		 7854 {
7855 types->bitfield.imm32 = 1;
7856 types->bitfield.disp32 = 1;
7857 }
3956db08
JB		 7858 else
7859 *types = gotrel[j].types64;
7860 }
7861
8fd4256d 7862 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7863 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7864
28f81592 7865 /* The length of the first part of our input line. */
f3c180ae 7866 first = cp - input_line_pointer;
28f81592
AM		 7867
7868 /* The second part goes from after the reloc token until
67c11a9b 7869 (and including) an end_of_line char or comma. */
28f81592 7870 past_reloc = cp + 1 + len;
67c11a9b
AM		 7871 cp = past_reloc;
7872 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7873 ++cp;
7874 second = cp + 1 - past_reloc;
28f81592
AM		 7875
7876 /* Allocate and copy string. The trailing NUL shouldn't
7877 be necessary, but be safe. */
add39d23 7878 tmpbuf = XNEWVEC (char, first + second + 2);
f3c180ae 7879 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7880 if (second != 0 && *past_reloc != ' ')
7881 /* Replace the relocation token with ' ', so that
7882 errors like foo@GOTOFF1 will be detected. */
7883 tmpbuf[first++] = ' ';
af89796a
L		 7884 else
7885 /* Increment length by 1 if the relocation token is
7886 removed. */
7887 len++;
7888 if (adjust)
7889 *adjust = len;
0787a12d
AM		 7890 memcpy (tmpbuf + first, past_reloc, second);
7891 tmpbuf[first + second] = '\0';
f3c180ae
AM		 7892 return tmpbuf;
7893 }
7894
4fa24527
JB		 7895 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7896 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7897 return NULL;
7898 }
7899 }
7900
7901 /* Might be a symbol version string. Don't as_bad here. */
7902 return NULL;
7903}
4e4f7c87 7904#endif
f3c180ae 7905
a988325c
NC		 7906#ifdef TE_PE
7907#ifdef lex_got
7908#undef lex_got
7909#endif
7910/* Parse operands of the form
7911 <symbol>@SECREL32+<nnn>
7912
7913 If we find one, set up the correct relocation in RELOC and copy the
7914 input string, minus the `@SECREL32' into a malloc'd buffer for
7915 parsing by the calling routine. Return this buffer, and if ADJUST
7916 is non-null set it to the length of the string we removed from the
34bca508
L		 7917 input line. Otherwise return NULL.
7918
a988325c
NC		 7919 This function is copied from the ELF version above adjusted for PE targets. */
7920
7921static char *
7922lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7923 int *adjust ATTRIBUTE_UNUSED,
d258b828 7924 i386_operand_type *types)
a988325c
NC		 7925{
7926 static const struct
7927 {
7928 const char *str;
7929 int len;
7930 const enum bfd_reloc_code_real rel[2];
7931 const i386_operand_type types64;
7932 }
7933 gotrel[] =
7934 {
7935 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7936 BFD_RELOC_32_SECREL },
7937 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7938 };
7939
7940 char *cp;
7941 unsigned j;
7942
7943 for (cp = input_line_pointer; *cp != '@'; cp++)
7944 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7945 return NULL;
7946
7947 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7948 {
7949 int len = gotrel[j].len;
7950
7951 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7952 {
7953 if (gotrel[j].rel[object_64bit] != 0)
7954 {
7955 int first, second;
7956 char *tmpbuf, *past_reloc;
7957
7958 *rel = gotrel[j].rel[object_64bit];
7959 if (adjust)
7960 *adjust = len;
7961
7962 if (types)
7963 {
7964 if (flag_code != CODE_64BIT)
7965 {
7966 types->bitfield.imm32 = 1;
7967 types->bitfield.disp32 = 1;
7968 }
7969 else
7970 *types = gotrel[j].types64;
7971 }
7972
7973 /* The length of the first part of our input line. */
7974 first = cp - input_line_pointer;
7975
7976 /* The second part goes from after the reloc token until
7977 (and including) an end_of_line char or comma. */
7978 past_reloc = cp + 1 + len;
7979 cp = past_reloc;
7980 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7981 ++cp;
7982 second = cp + 1 - past_reloc;
7983
7984 /* Allocate and copy string. The trailing NUL shouldn't
7985 be necessary, but be safe. */
add39d23 7986 tmpbuf = XNEWVEC (char, first + second + 2);
a988325c
NC		 7987 memcpy (tmpbuf, input_line_pointer, first);
7988 if (second != 0 && *past_reloc != ' ')
7989 /* Replace the relocation token with ' ', so that
7990 errors like foo@SECLREL321 will be detected. */
7991 tmpbuf[first++] = ' ';
7992 memcpy (tmpbuf + first, past_reloc, second);
7993 tmpbuf[first + second] = '\0';
7994 return tmpbuf;
7995 }
7996
7997 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7998 gotrel[j].str, 1 << (5 + object_64bit));
7999 return NULL;
8000 }
8001 }
8002
8003 /* Might be a symbol version string. Don't as_bad here. */
8004 return NULL;
8005}
8006
8007#endif /* TE_PE */
8008
62ebcb5c 8009bfd_reloc_code_real_type
e3bb37b5 8010x86_cons (expressionS *exp, int size)
f3c180ae 8011{
62ebcb5c
AM		 8012 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8013
ee86248c
JB		 8014 intel_syntax = -intel_syntax;
8015
3c7b9c2c 8016 exp->X_md = 0;
4fa24527 8017 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 8018 {
8019 /* Handle @GOTOFF and the like in an expression. */
8020 char *save;
8021 char *gotfree_input_line;
4a57f2cf 8022 int adjust = 0;
f3c180ae
AM		 8023
8024 save = input_line_pointer;
d258b828 8025 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 8026 if (gotfree_input_line)
8027 input_line_pointer = gotfree_input_line;
8028
8029 expression (exp);
8030
8031 if (gotfree_input_line)
8032 {
8033 /* expression () has merrily parsed up to the end of line,
8034 or a comma - in the wrong buffer. Transfer how far
8035 input_line_pointer has moved to the right buffer. */
8036 input_line_pointer = (save
8037 + (input_line_pointer - gotfree_input_line)
8038 + adjust);
8039 free (gotfree_input_line);
3992d3b7
AM		 8040 if (exp->X_op == O_constant
8041 || exp->X_op == O_absent
8042 || exp->X_op == O_illegal
0398aac5 8043 || exp->X_op == O_register
3992d3b7
AM		 8044 || exp->X_op == O_big)
8045 {
8046 char c = *input_line_pointer;
8047 *input_line_pointer = 0;
8048 as_bad (_("missing or invalid expression `%s'"), save);
8049 *input_line_pointer = c;
8050 }
f3c180ae
AM		 8051 }
8052 }
8053 else
8054 expression (exp);
ee86248c
JB		 8055
8056 intel_syntax = -intel_syntax;
8057
8058 if (intel_syntax)
8059 i386_intel_simplify (exp);
62ebcb5c
AM		 8060
8061 return got_reloc;
f3c180ae 8062}
f3c180ae 8063
9f32dd5b
L		 8064static void
8065signed_cons (int size)
6482c264 8066{
d182319b
JB		 8067 if (flag_code == CODE_64BIT)
8068 cons_sign = 1;
8069 cons (size);
8070 cons_sign = -1;
6482c264
NC		 8071}
8072
d182319b 8073#ifdef TE_PE
6482c264 8074static void
7016a5d5 8075pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 8076{
8077 expressionS exp;
8078
8079 do
8080 {
8081 expression (&exp);
8082 if (exp.X_op == O_symbol)
8083 exp.X_op = O_secrel;
8084
8085 emit_expr (&exp, 4);
8086 }
8087 while (*input_line_pointer++ == ',');
8088
8089 input_line_pointer--;
8090 demand_empty_rest_of_line ();
8091}
6482c264
NC		 8092#endif
8093
43234a1e
L		 8094/* Handle Vector operations. */
8095
8096static char *
8097check_VecOperations (char *op_string, char *op_end)
8098{
8099 const reg_entry *mask;
8100 const char *saved;
8101 char *end_op;
8102
8103 while (*op_string
8104 && (op_end == NULL || op_string < op_end))
8105 {
8106 saved = op_string;
8107 if (*op_string == '{')
8108 {
8109 op_string++;
8110
8111 /* Check broadcasts. */
8112 if (strncmp (op_string, "1to", 3) == 0)
8113 {
8114 int bcst_type;
8115
8116 if (i.broadcast)
8117 goto duplicated_vec_op;
8118
8119 op_string += 3;
8120 if (*op_string == '8')
8121 bcst_type = BROADCAST_1TO8;
b28d1bda
IT		 8122 else if (*op_string == '4')
8123 bcst_type = BROADCAST_1TO4;
8124 else if (*op_string == '2')
8125 bcst_type = BROADCAST_1TO2;
43234a1e
L		 8126 else if (*op_string == '1'
8127 && *(op_string+1) == '6')
8128 {
8129 bcst_type = BROADCAST_1TO16;
8130 op_string++;
8131 }
8132 else
8133 {
8134 as_bad (_("Unsupported broadcast: `%s'"), saved);
8135 return NULL;
8136 }
8137 op_string++;
8138
8139 broadcast_op.type = bcst_type;
8140 broadcast_op.operand = this_operand;
8141 i.broadcast = &broadcast_op;
8142 }
8143 /* Check masking operation. */
8144 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8145 {
8146 /* k0 can't be used for write mask. */
8147 if (mask->reg_num == 0)
8148 {
8149 as_bad (_("`%s' can't be used for write mask"),
8150 op_string);
8151 return NULL;
8152 }
8153
8154 if (!i.mask)
8155 {
8156 mask_op.mask = mask;
8157 mask_op.zeroing = 0;
8158 mask_op.operand = this_operand;
8159 i.mask = &mask_op;
8160 }
8161 else
8162 {
8163 if (i.mask->mask)
8164 goto duplicated_vec_op;
8165
8166 i.mask->mask = mask;
8167
8168 /* Only "{z}" is allowed here. No need to check
8169 zeroing mask explicitly. */
8170 if (i.mask->operand != this_operand)
8171 {
8172 as_bad (_("invalid write mask `%s'"), saved);
8173 return NULL;
8174 }
8175 }
8176
8177 op_string = end_op;
8178 }
8179 /* Check zeroing-flag for masking operation. */
8180 else if (*op_string == 'z')
8181 {
8182 if (!i.mask)
8183 {
8184 mask_op.mask = NULL;
8185 mask_op.zeroing = 1;
8186 mask_op.operand = this_operand;
8187 i.mask = &mask_op;
8188 }
8189 else
8190 {
8191 if (i.mask->zeroing)
8192 {
8193 duplicated_vec_op:
8194 as_bad (_("duplicated `%s'"), saved);
8195 return NULL;
8196 }
8197
8198 i.mask->zeroing = 1;
8199
8200 /* Only "{%k}" is allowed here. No need to check mask
8201 register explicitly. */
8202 if (i.mask->operand != this_operand)
8203 {
8204 as_bad (_("invalid zeroing-masking `%s'"),
8205 saved);
8206 return NULL;
8207 }
8208 }
8209
8210 op_string++;
8211 }
8212 else
8213 goto unknown_vec_op;
8214
8215 if (*op_string != '}')
8216 {
8217 as_bad (_("missing `}' in `%s'"), saved);
8218 return NULL;
8219 }
8220 op_string++;
8221 continue;
8222 }
8223 unknown_vec_op:
8224 /* We don't know this one. */
8225 as_bad (_("unknown vector operation: `%s'"), saved);
8226 return NULL;
8227 }
8228
8229 return op_string;
8230}
8231
252b5132 8232static int
70e41ade 8233i386_immediate (char *imm_start)
252b5132
RH		 8234{
8235 char *save_input_line_pointer;
f3c180ae 8236 char *gotfree_input_line;
252b5132 8237 segT exp_seg = 0;
47926f60 8238 expressionS *exp;
40fb9820
L		 8239 i386_operand_type types;
8240
0dfbf9d7 8241 operand_type_set (&types, ~0);
252b5132
RH		 8242
8243 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8244 {
31b2323c
L		 8245 as_bad (_("at most %d immediate operands are allowed"),
8246 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 8247 return 0;
8248 }
8249
8250 exp = &im_expressions[i.imm_operands++];
520dc8e8 8251 i.op[this_operand].imms = exp;
252b5132
RH		 8252
8253 if (is_space_char (*imm_start))
8254 ++imm_start;
8255
8256 save_input_line_pointer = input_line_pointer;
8257 input_line_pointer = imm_start;
8258
d258b828 8259 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8260 if (gotfree_input_line)
8261 input_line_pointer = gotfree_input_line;
252b5132
RH		 8262
8263 exp_seg = expression (exp);
8264
83183c0c 8265 SKIP_WHITESPACE ();
43234a1e
L		 8266
8267 /* Handle vector operations. */
8268 if (*input_line_pointer == '{')
8269 {
8270 input_line_pointer = check_VecOperations (input_line_pointer,
8271 NULL);
8272 if (input_line_pointer == NULL)
8273 return 0;
8274 }
8275
252b5132 8276 if (*input_line_pointer)
f3c180ae 8277 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 8278
8279 input_line_pointer = save_input_line_pointer;
f3c180ae 8280 if (gotfree_input_line)
ee86248c
JB		 8281 {
8282 free (gotfree_input_line);
8283
8284 if (exp->X_op == O_constant || exp->X_op == O_register)
8285 exp->X_op = O_illegal;
8286 }
8287
8288 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8289}
252b5132 8290
ee86248c
JB		 8291static int
8292i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8293 i386_operand_type types, const char *imm_start)
8294{
8295 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 8296 {
313c53d1
L		 8297 if (imm_start)
8298 as_bad (_("missing or invalid immediate expression `%s'"),
8299 imm_start);
3992d3b7 8300 return 0;
252b5132 8301 }
3e73aa7c 8302 else if (exp->X_op == O_constant)
252b5132 8303 {
47926f60 8304 /* Size it properly later. */
40fb9820 8305 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 8306 /* If not 64bit, sign extend val. */
8307 if (flag_code != CODE_64BIT
4eed87de
AM		 8308 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8309 exp->X_add_number
8310 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 8311 }
4c63da97 8312#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 8313 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 8314 && exp_seg != absolute_section
47926f60 8315 && exp_seg != text_section
24eab124
AM		 8316 && exp_seg != data_section
8317 && exp_seg != bss_section
8318 && exp_seg != undefined_section
f86103b7 8319 && !bfd_is_com_section (exp_seg))
252b5132 8320 {
d0b47220 8321 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 8322 return 0;
8323 }
8324#endif
a841bdf5 8325 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 8326 {
313c53d1
L		 8327 if (imm_start)
8328 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 8329 return 0;
8330 }
252b5132
RH		 8331 else
8332 {
8333 /* This is an address. The size of the address will be
24eab124 8334 determined later, depending on destination register,
3e73aa7c 8335 suffix, or the default for the section. */
40fb9820
L		 8336 i.types[this_operand].bitfield.imm8 = 1;
8337 i.types[this_operand].bitfield.imm16 = 1;
8338 i.types[this_operand].bitfield.imm32 = 1;
8339 i.types[this_operand].bitfield.imm32s = 1;
8340 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8341 i.types[this_operand] = operand_type_and (i.types[this_operand],
8342 types);
252b5132
RH		 8343 }
8344
8345 return 1;
8346}
8347
551c1ca1 8348static char *
e3bb37b5 8349i386_scale (char *scale)
252b5132 8350{
551c1ca1
AM		 8351 offsetT val;
8352 char *save = input_line_pointer;
252b5132 8353
551c1ca1
AM		 8354 input_line_pointer = scale;
8355 val = get_absolute_expression ();
8356
8357 switch (val)
252b5132 8358 {
551c1ca1 8359 case 1:
252b5132
RH		 8360 i.log2_scale_factor = 0;
8361 break;
551c1ca1 8362 case 2:
252b5132
RH		 8363 i.log2_scale_factor = 1;
8364 break;
551c1ca1 8365 case 4:
252b5132
RH		 8366 i.log2_scale_factor = 2;
8367 break;
551c1ca1 8368 case 8:
252b5132
RH		 8369 i.log2_scale_factor = 3;
8370 break;
8371 default:
a724f0f4
JB		 8372 {
8373 char sep = *input_line_pointer;
8374
8375 *input_line_pointer = '\0';
8376 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8377 scale);
8378 *input_line_pointer = sep;
8379 input_line_pointer = save;
8380 return NULL;
8381 }
252b5132 8382 }
29b0f896 8383 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8384 {
8385 as_warn (_("scale factor of %d without an index register"),
24eab124 8386 1 << i.log2_scale_factor);
252b5132 8387 i.log2_scale_factor = 0;
252b5132 8388 }
551c1ca1
AM		 8389 scale = input_line_pointer;
8390 input_line_pointer = save;
8391 return scale;
252b5132
RH		 8392}
8393
252b5132 8394static int
e3bb37b5 8395i386_displacement (char *disp_start, char *disp_end)
252b5132 8396{
29b0f896 8397 expressionS *exp;
252b5132
RH		 8398 segT exp_seg = 0;
8399 char *save_input_line_pointer;
f3c180ae 8400 char *gotfree_input_line;
40fb9820
L		 8401 int override;
8402 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8403 int ret;
252b5132 8404
31b2323c
L		 8405 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8406 {
8407 as_bad (_("at most %d displacement operands are allowed"),
8408 MAX_MEMORY_OPERANDS);
8409 return 0;
8410 }
8411
0dfbf9d7 8412 operand_type_set (&bigdisp, 0);
40fb9820
L		 8413 if ((i.types[this_operand].bitfield.jumpabsolute)
8414 || (!current_templates->start->opcode_modifier.jump
8415 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8416 {
40fb9820 8417 bigdisp.bitfield.disp32 = 1;
e05278af 8418 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8419 if (flag_code == CODE_64BIT)
8420 {
8421 if (!override)
8422 {
8423 bigdisp.bitfield.disp32s = 1;
8424 bigdisp.bitfield.disp64 = 1;
8425 }
8426 }
8427 else if ((flag_code == CODE_16BIT) ^ override)
8428 {
8429 bigdisp.bitfield.disp32 = 0;
8430 bigdisp.bitfield.disp16 = 1;
8431 }
e05278af
JB		 8432 }
8433 else
8434 {
8435 /* For PC-relative branches, the width of the displacement
8436 is dependent upon data size, not address size. */
e05278af 8437 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8438 if (flag_code == CODE_64BIT)
8439 {
8440 if (override || i.suffix == WORD_MNEM_SUFFIX)
8441 bigdisp.bitfield.disp16 = 1;
8442 else
8443 {
8444 bigdisp.bitfield.disp32 = 1;
8445 bigdisp.bitfield.disp32s = 1;
8446 }
8447 }
8448 else
e05278af
JB		 8449 {
8450 if (!override)
8451 override = (i.suffix == (flag_code != CODE_16BIT
8452 ? WORD_MNEM_SUFFIX
8453 : LONG_MNEM_SUFFIX));
40fb9820
L		 8454 bigdisp.bitfield.disp32 = 1;
8455 if ((flag_code == CODE_16BIT) ^ override)
8456 {
8457 bigdisp.bitfield.disp32 = 0;
8458 bigdisp.bitfield.disp16 = 1;
8459 }
e05278af 8460 }
e05278af 8461 }
c6fb90c8
L		 8462 i.types[this_operand] = operand_type_or (i.types[this_operand],
8463 bigdisp);
252b5132
RH		 8464
8465 exp = &disp_expressions[i.disp_operands];
520dc8e8 8466 i.op[this_operand].disps = exp;
252b5132
RH		 8467 i.disp_operands++;
8468 save_input_line_pointer = input_line_pointer;
8469 input_line_pointer = disp_start;
8470 END_STRING_AND_SAVE (disp_end);
8471
8472#ifndef GCC_ASM_O_HACK
8473#define GCC_ASM_O_HACK 0
8474#endif
8475#if GCC_ASM_O_HACK
8476 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8477 if (i.types[this_operand].bitfield.baseIndex
24eab124 8478 && displacement_string_end[-1] == '+')
252b5132
RH		 8479 {
8480 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8481 constraint within gcc asm statements.
8482 For instance:
8483
8484 #define _set_tssldt_desc(n,addr,limit,type) \
8485 __asm__ __volatile__ ( \
8486 "movw %w2,%0\n\t" \
8487 "movw %w1,2+%0\n\t" \
8488 "rorl $16,%1\n\t" \
8489 "movb %b1,4+%0\n\t" \
8490 "movb %4,5+%0\n\t" \
8491 "movb $0,6+%0\n\t" \
8492 "movb %h1,7+%0\n\t" \
8493 "rorl $16,%1" \
8494 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8495
8496 This works great except that the output assembler ends
8497 up looking a bit weird if it turns out that there is
8498 no offset. You end up producing code that looks like:
8499
8500 #APP
8501 movw $235,(%eax)
8502 movw %dx,2+(%eax)
8503 rorl $16,%edx
8504 movb %dl,4+(%eax)
8505 movb $137,5+(%eax)
8506 movb $0,6+(%eax)
8507 movb %dh,7+(%eax)
8508 rorl $16,%edx
8509 #NO_APP
8510
47926f60 8511 So here we provide the missing zero. */
24eab124
AM		 8512
8513 *displacement_string_end = '0';
252b5132
RH		 8514 }
8515#endif
d258b828 8516 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8517 if (gotfree_input_line)
8518 input_line_pointer = gotfree_input_line;
252b5132 8519
24eab124 8520 exp_seg = expression (exp);
252b5132 8521
636c26b0
AM		 8522 SKIP_WHITESPACE ();
8523 if (*input_line_pointer)
8524 as_bad (_("junk `%s' after expression"), input_line_pointer);
8525#if GCC_ASM_O_HACK
8526 RESTORE_END_STRING (disp_end + 1);
8527#endif
636c26b0 8528 input_line_pointer = save_input_line_pointer;
636c26b0 8529 if (gotfree_input_line)
ee86248c
JB		 8530 {
8531 free (gotfree_input_line);
8532
8533 if (exp->X_op == O_constant || exp->X_op == O_register)
8534 exp->X_op = O_illegal;
8535 }
8536
8537 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8538
8539 RESTORE_END_STRING (disp_end);
8540
8541 return ret;
8542}
8543
8544static int
8545i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8546 i386_operand_type types, const char *disp_start)
8547{
8548 i386_operand_type bigdisp;
8549 int ret = 1;
636c26b0 8550
24eab124
AM		 8551 /* We do this to make sure that the section symbol is in
8552 the symbol table. We will ultimately change the relocation
47926f60 8553 to be relative to the beginning of the section. */
1ae12ab7 8554 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8555 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8556 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8557 {
636c26b0 8558 if (exp->X_op != O_symbol)
3992d3b7 8559 goto inv_disp;
636c26b0 8560
e5cb08ac 8561 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8562 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8563 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8564 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8565 exp->X_op = O_subtract;
8566 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8567 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8568 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8569 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8570 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8571 else
29b0f896 8572 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8573 }
252b5132 8574
3992d3b7
AM		 8575 else if (exp->X_op == O_absent
8576 || exp->X_op == O_illegal
ee86248c 8577 || exp->X_op == O_big)
2daf4fd8 8578 {
3992d3b7
AM		 8579 inv_disp:
8580 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8581 disp_start);
3992d3b7 8582 ret = 0;
2daf4fd8
AM		 8583 }
8584
0e1147d9
L		 8585 else if (flag_code == CODE_64BIT
8586 && !i.prefix[ADDR_PREFIX]
8587 && exp->X_op == O_constant)
8588 {
8589 /* Since displacement is signed extended to 64bit, don't allow
8590 disp32 and turn off disp32s if they are out of range. */
8591 i.types[this_operand].bitfield.disp32 = 0;
8592 if (!fits_in_signed_long (exp->X_add_number))
8593 {
8594 i.types[this_operand].bitfield.disp32s = 0;
8595 if (i.types[this_operand].bitfield.baseindex)
8596 {
8597 as_bad (_("0x%lx out range of signed 32bit displacement"),
8598 (long) exp->X_add_number);
8599 ret = 0;
8600 }
8601 }
8602 }
8603
4c63da97 8604#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8605 else if (exp->X_op != O_constant
8606 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8607 && exp_seg != absolute_section
8608 && exp_seg != text_section
8609 && exp_seg != data_section
8610 && exp_seg != bss_section
8611 && exp_seg != undefined_section
8612 && !bfd_is_com_section (exp_seg))
24eab124 8613 {
d0b47220 8614 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8615 ret = 0;
24eab124 8616 }
252b5132 8617#endif
3956db08 8618
40fb9820
L		 8619 /* Check if this is a displacement only operand. */
8620 bigdisp = i.types[this_operand];
8621 bigdisp.bitfield.disp8 = 0;
8622 bigdisp.bitfield.disp16 = 0;
8623 bigdisp.bitfield.disp32 = 0;
8624 bigdisp.bitfield.disp32s = 0;
8625 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8626 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8627 i.types[this_operand] = operand_type_and (i.types[this_operand],
8628 types);
3956db08 8629
3992d3b7 8630 return ret;
252b5132
RH		 8631}
8632
eecb386c 8633/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 8634 Return 1 on success, 0 on a failure. */
8635
252b5132 8636static int
e3bb37b5 8637i386_index_check (const char *operand_string)
252b5132 8638{
fc0763e6 8639 const char *kind = "base/index";
be05d201
L		 8640 enum flag_code addr_mode;
8641
8642 if (i.prefix[ADDR_PREFIX])
8643 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8644 else
8645 {
8646 addr_mode = flag_code;
8647
24eab124 8648#if INFER_ADDR_PREFIX
be05d201
L		 8649 if (i.mem_operands == 0)
8650 {
8651 /* Infer address prefix from the first memory operand. */
8652 const reg_entry *addr_reg = i.base_reg;
8653
8654 if (addr_reg == NULL)
8655 addr_reg = i.index_reg;
eecb386c 8656
be05d201
L		 8657 if (addr_reg)
8658 {
8659 if (addr_reg->reg_num == RegEip
8660 || addr_reg->reg_num == RegEiz
8661 || addr_reg->reg_type.bitfield.reg32)
8662 addr_mode = CODE_32BIT;
8663 else if (flag_code != CODE_64BIT
8664 && addr_reg->reg_type.bitfield.reg16)
8665 addr_mode = CODE_16BIT;
8666
8667 if (addr_mode != flag_code)
8668 {
8669 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8670 i.prefixes += 1;
8671 /* Change the size of any displacement too. At most one
8672 of Disp16 or Disp32 is set.
8673 FIXME. There doesn't seem to be any real need for
8674 separate Disp16 and Disp32 flags. The same goes for
8675 Imm16 and Imm32. Removing them would probably clean
8676 up the code quite a lot. */
8677 if (flag_code != CODE_64BIT
8678 && (i.types[this_operand].bitfield.disp16
8679 || i.types[this_operand].bitfield.disp32))
8680 i.types[this_operand]
8681 = operand_type_xor (i.types[this_operand], disp16_32);
8682 }
8683 }
8684 }
24eab124 8685#endif
be05d201
L		 8686 }
8687
fc0763e6
JB		 8688 if (current_templates->start->opcode_modifier.isstring
8689 && !current_templates->start->opcode_modifier.immext
8690 && (current_templates->end[-1].opcode_modifier.isstring
8691 || i.mem_operands))
8692 {
8693 /* Memory operands of string insns are special in that they only allow
8694 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8695 const reg_entry *expected_reg;
8696 static const char *di_si[][2] =
8697 {
8698 { "esi", "edi" },
8699 { "si", "di" },
8700 { "rsi", "rdi" }
8701 };
8702 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8703
8704 kind = "string address";
8705
8325cc63 8706 if (current_templates->start->opcode_modifier.repprefixok)
fc0763e6
JB		 8707 {
8708 i386_operand_type type = current_templates->end[-1].operand_types[0];
8709
8710 if (!type.bitfield.baseindex
8711 || ((!i.mem_operands != !intel_syntax)
8712 && current_templates->end[-1].operand_types[1]
8713 .bitfield.baseindex))
8714 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8715 expected_reg = hash_find (reg_hash,
8716 di_si[addr_mode][type.bitfield.esseg]);
8717
fc0763e6
JB		 8718 }
8719 else
be05d201 8720 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8721
be05d201
L		 8722 if (i.base_reg != expected_reg
8723 || i.index_reg
fc0763e6 8724 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8725 {
be05d201
L		 8726 /* The second memory operand must have the same size as
8727 the first one. */
8728 if (i.mem_operands
8729 && i.base_reg
8730 && !((addr_mode == CODE_64BIT
8731 && i.base_reg->reg_type.bitfield.reg64)
8732 || (addr_mode == CODE_32BIT
8733 ? i.base_reg->reg_type.bitfield.reg32
8734 : i.base_reg->reg_type.bitfield.reg16)))
8735 goto bad_address;
8736
fc0763e6
JB		 8737 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8738 operand_string,
8739 intel_syntax ? '[' : '(',
8740 register_prefix,
be05d201 8741 expected_reg->reg_name,
fc0763e6 8742 intel_syntax ? ']' : ')');
be05d201 8743 return 1;
fc0763e6 8744 }
be05d201
L		 8745 else
8746 return 1;
8747
8748bad_address:
8749 as_bad (_("`%s' is not a valid %s expression"),
8750 operand_string, kind);
8751 return 0;
3e73aa7c
JH		 8752 }
8753 else
8754 {
be05d201
L		 8755 if (addr_mode != CODE_16BIT)
8756 {
8757 /* 32-bit/64-bit checks. */
8758 if ((i.base_reg
8759 && (addr_mode == CODE_64BIT
8760 ? !i.base_reg->reg_type.bitfield.reg64
8761 : !i.base_reg->reg_type.bitfield.reg32)
8762 && (i.index_reg
8763 || (i.base_reg->reg_num
8764 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8765 || (i.index_reg
8766 && !i.index_reg->reg_type.bitfield.regxmm
8767 && !i.index_reg->reg_type.bitfield.regymm
43234a1e 8768 && !i.index_reg->reg_type.bitfield.regzmm
be05d201
L		 8769 && ((addr_mode == CODE_64BIT
8770 ? !(i.index_reg->reg_type.bitfield.reg64
8771 || i.index_reg->reg_num == RegRiz)
8772 : !(i.index_reg->reg_type.bitfield.reg32
8773 || i.index_reg->reg_num == RegEiz))
8774 || !i.index_reg->reg_type.bitfield.baseindex)))
8775 goto bad_address;
8178be5b
JB		 8776
8777 /* bndmk, bndldx, and bndstx have special restrictions. */
8778 if (current_templates->start->base_opcode == 0xf30f1b
8779 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
8780 {
8781 /* They cannot use RIP-relative addressing. */
8782 if (i.base_reg && i.base_reg->reg_num == RegRip)
8783 {
8784 as_bad (_("`%s' cannot be used here"), operand_string);
8785 return 0;
8786 }
8787
8788 /* bndldx and bndstx ignore their scale factor. */
8789 if (current_templates->start->base_opcode != 0xf30f1b
8790 && i.log2_scale_factor)
8791 as_warn (_("register scaling is being ignored here"));
8792 }
be05d201
L		 8793 }
8794 else
3e73aa7c 8795 {
be05d201 8796 /* 16-bit checks. */
3e73aa7c 8797 if ((i.base_reg
40fb9820
L		 8798 && (!i.base_reg->reg_type.bitfield.reg16
8799 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8800 || (i.index_reg
40fb9820
L		 8801 && (!i.index_reg->reg_type.bitfield.reg16
8802 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8803 || !(i.base_reg
8804 && i.base_reg->reg_num < 6
8805 && i.index_reg->reg_num >= 6
8806 && i.log2_scale_factor == 0))))
be05d201 8807 goto bad_address;
3e73aa7c
JH		 8808 }
8809 }
be05d201 8810 return 1;
24eab124 8811}
252b5132 8812
43234a1e
L		 8813/* Handle vector immediates. */
8814
8815static int
8816RC_SAE_immediate (const char *imm_start)
8817{
8818 unsigned int match_found, j;
8819 const char *pstr = imm_start;
8820 expressionS *exp;
8821
8822 if (*pstr != '{')
8823 return 0;
8824
8825 pstr++;
8826 match_found = 0;
8827 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8828 {
8829 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8830 {
8831 if (!i.rounding)
8832 {
8833 rc_op.type = RC_NamesTable[j].type;
8834 rc_op.operand = this_operand;
8835 i.rounding = &rc_op;
8836 }
8837 else
8838 {
8839 as_bad (_("duplicated `%s'"), imm_start);
8840 return 0;
8841 }
8842 pstr += RC_NamesTable[j].len;
8843 match_found = 1;
8844 break;
8845 }
8846 }
8847 if (!match_found)
8848 return 0;
8849
8850 if (*pstr++ != '}')
8851 {
8852 as_bad (_("Missing '}': '%s'"), imm_start);
8853 return 0;
8854 }
8855 /* RC/SAE immediate string should contain nothing more. */;
8856 if (*pstr != 0)
8857 {
8858 as_bad (_("Junk after '}': '%s'"), imm_start);
8859 return 0;
8860 }
8861
8862 exp = &im_expressions[i.imm_operands++];
8863 i.op[this_operand].imms = exp;
8864
8865 exp->X_op = O_constant;
8866 exp->X_add_number = 0;
8867 exp->X_add_symbol = (symbolS *) 0;
8868 exp->X_op_symbol = (symbolS *) 0;
8869
8870 i.types[this_operand].bitfield.imm8 = 1;
8871 return 1;
8872}
8873
8325cc63
JB		 8874/* Only string instructions can have a second memory operand, so
8875 reduce current_templates to just those if it contains any. */
8876static int
8877maybe_adjust_templates (void)
8878{
8879 const insn_template *t;
8880
8881 gas_assert (i.mem_operands == 1);
8882
8883 for (t = current_templates->start; t < current_templates->end; ++t)
8884 if (t->opcode_modifier.isstring)
8885 break;
8886
8887 if (t < current_templates->end)
8888 {
8889 static templates aux_templates;
8890 bfd_boolean recheck;
8891
8892 aux_templates.start = t;
8893 for (; t < current_templates->end; ++t)
8894 if (!t->opcode_modifier.isstring)
8895 break;
8896 aux_templates.end = t;
8897
8898 /* Determine whether to re-check the first memory operand. */
8899 recheck = (aux_templates.start != current_templates->start
8900 || t != current_templates->end);
8901
8902 current_templates = &aux_templates;
8903
8904 if (recheck)
8905 {
8906 i.mem_operands = 0;
8907 if (i.memop1_string != NULL
8908 && i386_index_check (i.memop1_string) == 0)
8909 return 0;
8910 i.mem_operands = 1;
8911 }
8912 }
8913
8914 return 1;
8915}
8916
fc0763e6 8917/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8918 on error. */
252b5132 8919
252b5132 8920static int
a7619375 8921i386_att_operand (char *operand_string)
252b5132 8922{
af6bdddf
AM		 8923 const reg_entry *r;
8924 char *end_op;
24eab124 8925 char *op_string = operand_string;
252b5132 8926
24eab124 8927 if (is_space_char (*op_string))
252b5132
RH		 8928 ++op_string;
8929
24eab124 8930 /* We check for an absolute prefix (differentiating,
47926f60 8931 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8932 if (*op_string == ABSOLUTE_PREFIX)
8933 {
8934 ++op_string;
8935 if (is_space_char (*op_string))
8936 ++op_string;
40fb9820 8937 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8938 }
252b5132 8939
47926f60 8940 /* Check if operand is a register. */
4d1bb795 8941 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8942 {
40fb9820
L		 8943 i386_operand_type temp;
8944
24eab124
AM		 8945 /* Check for a segment override by searching for ':' after a
8946 segment register. */
8947 op_string = end_op;
8948 if (is_space_char (*op_string))
8949 ++op_string;
40fb9820
L		 8950 if (*op_string == ':'
8951 && (r->reg_type.bitfield.sreg2
8952 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8953 {
8954 switch (r->reg_num)
8955 {
8956 case 0:
8957 i.seg[i.mem_operands] = &es;
8958 break;
8959 case 1:
8960 i.seg[i.mem_operands] = &cs;
8961 break;
8962 case 2:
8963 i.seg[i.mem_operands] = &ss;
8964 break;
8965 case 3:
8966 i.seg[i.mem_operands] = &ds;
8967 break;
8968 case 4:
8969 i.seg[i.mem_operands] = &fs;
8970 break;
8971 case 5:
8972 i.seg[i.mem_operands] = &gs;
8973 break;
8974 }
252b5132 8975
24eab124 8976 /* Skip the ':' and whitespace. */
252b5132
RH		 8977 ++op_string;
8978 if (is_space_char (*op_string))
24eab124 8979 ++op_string;
252b5132 8980
24eab124
AM		 8981 if (!is_digit_char (*op_string)
8982 && !is_identifier_char (*op_string)
8983 && *op_string != '('
8984 && *op_string != ABSOLUTE_PREFIX)
8985 {
8986 as_bad (_("bad memory operand `%s'"), op_string);
8987 return 0;
8988 }
47926f60 8989 /* Handle case of %es:*foo. */
24eab124
AM		 8990 if (*op_string == ABSOLUTE_PREFIX)
8991 {
8992 ++op_string;
8993 if (is_space_char (*op_string))
8994 ++op_string;
40fb9820 8995 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8996 }
8997 goto do_memory_reference;
8998 }
43234a1e
L		 8999
9000 /* Handle vector operations. */
9001 if (*op_string == '{')
9002 {
9003 op_string = check_VecOperations (op_string, NULL);
9004 if (op_string == NULL)
9005 return 0;
9006 }
9007
24eab124
AM		 9008 if (*op_string)
9009 {
d0b47220 9010 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 9011 return 0;
9012 }
40fb9820
L		 9013 temp = r->reg_type;
9014 temp.bitfield.baseindex = 0;
c6fb90c8
L		 9015 i.types[this_operand] = operand_type_or (i.types[this_operand],
9016 temp);
7d5e4556 9017 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 9018 i.op[this_operand].regs = r;
24eab124
AM		 9019 i.reg_operands++;
9020 }
af6bdddf
AM		 9021 else if (*op_string == REGISTER_PREFIX)
9022 {
9023 as_bad (_("bad register name `%s'"), op_string);
9024 return 0;
9025 }
24eab124 9026 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 9027 {
24eab124 9028 ++op_string;
40fb9820 9029 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 9030 {
d0b47220 9031 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 9032 return 0;
9033 }
9034 if (!i386_immediate (op_string))
9035 return 0;
9036 }
43234a1e
L		 9037 else if (RC_SAE_immediate (operand_string))
9038 {
9039 /* If it is a RC or SAE immediate, do nothing. */
9040 ;
9041 }
24eab124
AM		 9042 else if (is_digit_char (*op_string)
9043 || is_identifier_char (*op_string)
d02603dc 9044 || *op_string == '"'
e5cb08ac 9045 || *op_string == '(')
24eab124 9046 {
47926f60 9047 /* This is a memory reference of some sort. */
af6bdddf 9048 char *base_string;
252b5132 9049
47926f60 9050 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 9051 char *displacement_string_start;
9052 char *displacement_string_end;
43234a1e 9053 char *vop_start;
252b5132 9054
24eab124 9055 do_memory_reference:
8325cc63
JB		 9056 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9057 return 0;
24eab124 9058 if ((i.mem_operands == 1
40fb9820 9059 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 9060 || i.mem_operands == 2)
9061 {
9062 as_bad (_("too many memory references for `%s'"),
9063 current_templates->start->name);
9064 return 0;
9065 }
252b5132 9066
24eab124
AM		 9067 /* Check for base index form. We detect the base index form by
9068 looking for an ')' at the end of the operand, searching
9069 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9070 after the '('. */
af6bdddf 9071 base_string = op_string + strlen (op_string);
c3332e24 9072
43234a1e
L		 9073 /* Handle vector operations. */
9074 vop_start = strchr (op_string, '{');
9075 if (vop_start && vop_start < base_string)
9076 {
9077 if (check_VecOperations (vop_start, base_string) == NULL)
9078 return 0;
9079 base_string = vop_start;
9080 }
9081
af6bdddf
AM		 9082 --base_string;
9083 if (is_space_char (*base_string))
9084 --base_string;
252b5132 9085
47926f60 9086 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 9087 displacement_string_start = op_string;
9088 displacement_string_end = base_string + 1;
252b5132 9089
24eab124
AM		 9090 if (*base_string == ')')
9091 {
af6bdddf 9092 char *temp_string;
24eab124
AM		 9093 unsigned int parens_balanced = 1;
9094 /* We've already checked that the number of left & right ()'s are
47926f60 9095 equal, so this loop will not be infinite. */
24eab124
AM		 9096 do
9097 {
9098 base_string--;
9099 if (*base_string == ')')
9100 parens_balanced++;
9101 if (*base_string == '(')
9102 parens_balanced--;
9103 }
9104 while (parens_balanced);
c3332e24 9105
af6bdddf 9106 temp_string = base_string;
c3332e24 9107
24eab124 9108 /* Skip past '(' and whitespace. */
252b5132
RH		 9109 ++base_string;
9110 if (is_space_char (*base_string))
24eab124 9111 ++base_string;
252b5132 9112
af6bdddf 9113 if (*base_string == ','
4eed87de
AM		 9114 || ((i.base_reg = parse_register (base_string, &end_op))
9115 != NULL))
252b5132 9116 {
af6bdddf 9117 displacement_string_end = temp_string;
252b5132 9118
40fb9820 9119 i.types[this_operand].bitfield.baseindex = 1;
252b5132 9120
af6bdddf 9121 if (i.base_reg)
24eab124 9122 {
24eab124
AM		 9123 base_string = end_op;
9124 if (is_space_char (*base_string))
9125 ++base_string;
af6bdddf
AM		 9126 }
9127
9128 /* There may be an index reg or scale factor here. */
9129 if (*base_string == ',')
9130 {
9131 ++base_string;
9132 if (is_space_char (*base_string))
9133 ++base_string;
9134
4eed87de
AM		 9135 if ((i.index_reg = parse_register (base_string, &end_op))
9136 != NULL)
24eab124 9137 {
af6bdddf 9138 base_string = end_op;
24eab124
AM		 9139 if (is_space_char (*base_string))
9140 ++base_string;
af6bdddf
AM		 9141 if (*base_string == ',')
9142 {
9143 ++base_string;
9144 if (is_space_char (*base_string))
9145 ++base_string;
9146 }
e5cb08ac 9147 else if (*base_string != ')')
af6bdddf 9148 {
4eed87de
AM		 9149 as_bad (_("expecting `,' or `)' "
9150 "after index register in `%s'"),
af6bdddf
AM		 9151 operand_string);
9152 return 0;
9153 }
24eab124 9154 }
af6bdddf 9155 else if (*base_string == REGISTER_PREFIX)
24eab124 9156 {
f76bf5e0
L		 9157 end_op = strchr (base_string, ',');
9158 if (end_op)
9159 *end_op = '\0';
af6bdddf 9160 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 9161 return 0;
9162 }
252b5132 9163
47926f60 9164 /* Check for scale factor. */
551c1ca1 9165 if (*base_string != ')')
af6bdddf 9166 {
551c1ca1
AM		 9167 char *end_scale = i386_scale (base_string);
9168
9169 if (!end_scale)
af6bdddf 9170 return 0;
24eab124 9171
551c1ca1 9172 base_string = end_scale;
af6bdddf
AM		 9173 if (is_space_char (*base_string))
9174 ++base_string;
9175 if (*base_string != ')')
9176 {
4eed87de
AM		 9177 as_bad (_("expecting `)' "
9178 "after scale factor in `%s'"),
af6bdddf
AM		 9179 operand_string);
9180 return 0;
9181 }
9182 }
9183 else if (!i.index_reg)
24eab124 9184 {
4eed87de
AM		 9185 as_bad (_("expecting index register or scale factor "
9186 "after `,'; got '%c'"),
af6bdddf 9187 *base_string);
24eab124
AM		 9188 return 0;
9189 }
9190 }
af6bdddf 9191 else if (*base_string != ')')
24eab124 9192 {
4eed87de
AM		 9193 as_bad (_("expecting `,' or `)' "
9194 "after base register in `%s'"),
af6bdddf 9195 operand_string);
24eab124
AM		 9196 return 0;
9197 }
c3332e24 9198 }
af6bdddf 9199 else if (*base_string == REGISTER_PREFIX)
c3332e24 9200 {
f76bf5e0
L		 9201 end_op = strchr (base_string, ',');
9202 if (end_op)
9203 *end_op = '\0';
af6bdddf 9204 as_bad (_("bad register name `%s'"), base_string);
24eab124 9205 return 0;
c3332e24 9206 }
24eab124
AM		 9207 }
9208
9209 /* If there's an expression beginning the operand, parse it,
9210 assuming displacement_string_start and
9211 displacement_string_end are meaningful. */
9212 if (displacement_string_start != displacement_string_end)
9213 {
9214 if (!i386_displacement (displacement_string_start,
9215 displacement_string_end))
9216 return 0;
9217 }
9218
9219 /* Special case for (%dx) while doing input/output op. */
9220 if (i.base_reg
0dfbf9d7
L		 9221 && operand_type_equal (&i.base_reg->reg_type,
9222 &reg16_inoutportreg)
24eab124
AM		 9223 && i.index_reg == 0
9224 && i.log2_scale_factor == 0
9225 && i.seg[i.mem_operands] == 0
40fb9820 9226 && !operand_type_check (i.types[this_operand], disp))
24eab124 9227 {
65da13b5 9228 i.types[this_operand] = inoutportreg;
24eab124
AM		 9229 return 1;
9230 }
9231
eecb386c
AM		 9232 if (i386_index_check (operand_string) == 0)
9233 return 0;
5c07affc 9234 i.types[this_operand].bitfield.mem = 1;
8325cc63
JB		 9235 if (i.mem_operands == 0)
9236 i.memop1_string = xstrdup (operand_string);
24eab124
AM		 9237 i.mem_operands++;
9238 }
9239 else
ce8a8b2f
AM		 9240 {
9241 /* It's not a memory operand; argh! */
24eab124
AM		 9242 as_bad (_("invalid char %s beginning operand %d `%s'"),
9243 output_invalid (*op_string),
9244 this_operand + 1,
9245 op_string);
9246 return 0;
9247 }
47926f60 9248 return 1; /* Normal return. */
252b5132
RH		 9249}
9250\f
fa94de6b
RM		 9251/* Calculate the maximum variable size (i.e., excluding fr_fix)
9252 that an rs_machine_dependent frag may reach. */
9253
9254unsigned int
9255i386_frag_max_var (fragS *frag)
9256{
9257 /* The only relaxable frags are for jumps.
9258 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9259 gas_assert (frag->fr_type == rs_machine_dependent);
9260 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9261}
9262
b084df0b
L		 9263#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9264static int
8dcea932 9265elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
b084df0b
L		 9266{
9267 /* STT_GNU_IFUNC symbol must go through PLT. */
9268 if ((symbol_get_bfdsym (fr_symbol)->flags
9269 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9270 return 0;
9271
9272 if (!S_IS_EXTERNAL (fr_symbol))
9273 /* Symbol may be weak or local. */
9274 return !S_IS_WEAK (fr_symbol);
9275
8dcea932
L		 9276 /* Global symbols with non-default visibility can't be preempted. */
9277 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9278 return 1;
9279
9280 if (fr_var != NO_RELOC)
9281 switch ((enum bfd_reloc_code_real) fr_var)
9282 {
9283 case BFD_RELOC_386_PLT32:
9284 case BFD_RELOC_X86_64_PLT32:
33eaf5de 9285 /* Symbol with PLT relocation may be preempted. */
8dcea932
L		 9286 return 0;
9287 default:
9288 abort ();
9289 }
9290
b084df0b
L		 9291 /* Global symbols with default visibility in a shared library may be
9292 preempted by another definition. */
8dcea932 9293 return !shared;
b084df0b
L		 9294}
9295#endif
9296
ee7fcc42
AM		 9297/* md_estimate_size_before_relax()
9298
9299 Called just before relax() for rs_machine_dependent frags. The x86
9300 assembler uses these frags to handle variable size jump
9301 instructions.
9302
9303 Any symbol that is now undefined will not become defined.
9304 Return the correct fr_subtype in the frag.
9305 Return the initial "guess for variable size of frag" to caller.
9306 The guess is actually the growth beyond the fixed part. Whatever
9307 we do to grow the fixed or variable part contributes to our
9308 returned value. */
9309
252b5132 9310int
7016a5d5 9311md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 9312{
252b5132 9313 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 9314 check for un-relaxable symbols. On an ELF system, we can't relax
9315 an externally visible symbol, because it may be overridden by a
9316 shared library. */
9317 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 9318#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9319 || (IS_ELF
8dcea932
L		 9320 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9321 fragP->fr_var))
fbeb56a4
DK		 9322#endif
9323#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 9324 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 9325 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 9326#endif
9327 )
252b5132 9328 {
b98ef147
AM		 9329 /* Symbol is undefined in this segment, or we need to keep a
9330 reloc so that weak symbols can be overridden. */
9331 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 9332 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 9333 unsigned char *opcode;
9334 int old_fr_fix;
f6af82bd 9335
ee7fcc42 9336 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 9337 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 9338 else if (size == 2)
f6af82bd
AM		 9339 reloc_type = BFD_RELOC_16_PCREL;
9340 else
9341 reloc_type = BFD_RELOC_32_PCREL;
252b5132 9342
ee7fcc42
AM		 9343 old_fr_fix = fragP->fr_fix;
9344 opcode = (unsigned char *) fragP->fr_opcode;
9345
fddf5b5b 9346 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 9347 {
fddf5b5b
AM		 9348 case UNCOND_JUMP:
9349 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 9350 opcode[0] = 0xe9;
252b5132 9351 fragP->fr_fix += size;
062cd5e7
AS		 9352 fix_new (fragP, old_fr_fix, size,
9353 fragP->fr_symbol,
9354 fragP->fr_offset, 1,
9355 reloc_type);
252b5132
RH		 9356 break;
9357
fddf5b5b 9358 case COND_JUMP86:
412167cb
AM		 9359 if (size == 2
9360 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 9361 {
9362 /* Negate the condition, and branch past an
9363 unconditional jump. */
9364 opcode[0] ^= 1;
9365 opcode[1] = 3;
9366 /* Insert an unconditional jump. */
9367 opcode[2] = 0xe9;
9368 /* We added two extra opcode bytes, and have a two byte
9369 offset. */
9370 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 9371 fix_new (fragP, old_fr_fix + 2, 2,
9372 fragP->fr_symbol,
9373 fragP->fr_offset, 1,
9374 reloc_type);
fddf5b5b
AM		 9375 break;
9376 }
9377 /* Fall through. */
9378
9379 case COND_JUMP:
412167cb
AM		 9380 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9381 {
3e02c1cc
AM		 9382 fixS *fixP;
9383
412167cb 9384 fragP->fr_fix += 1;
3e02c1cc
AM		 9385 fixP = fix_new (fragP, old_fr_fix, 1,
9386 fragP->fr_symbol,
9387 fragP->fr_offset, 1,
9388 BFD_RELOC_8_PCREL);
9389 fixP->fx_signed = 1;
412167cb
AM		 9390 break;
9391 }
93c2a809 9392
24eab124 9393 /* This changes the byte-displacement jump 0x7N
fddf5b5b 9394 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 9395 opcode[1] = opcode[0] + 0x10;
f6af82bd 9396 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 9397 /* We've added an opcode byte. */
9398 fragP->fr_fix += 1 + size;
062cd5e7
AS		 9399 fix_new (fragP, old_fr_fix + 1, size,
9400 fragP->fr_symbol,
9401 fragP->fr_offset, 1,
9402 reloc_type);
252b5132 9403 break;
fddf5b5b
AM		 9404
9405 default:
9406 BAD_CASE (fragP->fr_subtype);
9407 break;
252b5132
RH		 9408 }
9409 frag_wane (fragP);
ee7fcc42 9410 return fragP->fr_fix - old_fr_fix;
252b5132 9411 }
93c2a809 9412
93c2a809
AM		 9413 /* Guess size depending on current relax state. Initially the relax
9414 state will correspond to a short jump and we return 1, because
9415 the variable part of the frag (the branch offset) is one byte
9416 long. However, we can relax a section more than once and in that
9417 case we must either set fr_subtype back to the unrelaxed state,
9418 or return the value for the appropriate branch. */
9419 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 9420}
9421
47926f60
KH		 9422/* Called after relax() is finished.
9423
9424 In: Address of frag.
9425 fr_type == rs_machine_dependent.
9426 fr_subtype is what the address relaxed to.
9427
9428 Out: Any fixSs and constants are set up.
9429 Caller will turn frag into a ".space 0". */
9430
252b5132 9431void
7016a5d5
TG		 9432md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9433 fragS *fragP)
252b5132 9434{
29b0f896 9435 unsigned char *opcode;
252b5132 9436 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9437 offsetT target_address;
9438 offsetT opcode_address;
252b5132 9439 unsigned int extension = 0;
847f7ad4 9440 offsetT displacement_from_opcode_start;
252b5132
RH		 9441
9442 opcode = (unsigned char *) fragP->fr_opcode;
9443
47926f60 9444 /* Address we want to reach in file space. */
252b5132 9445 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9446
47926f60 9447 /* Address opcode resides at in file space. */
252b5132
RH		 9448 opcode_address = fragP->fr_address + fragP->fr_fix;
9449
47926f60 9450 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9451 displacement_from_opcode_start = target_address - opcode_address;
9452
fddf5b5b 9453 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9454 {
47926f60
KH		 9455 /* Don't have to change opcode. */
9456 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9457 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9458 }
9459 else
9460 {
9461 if (no_cond_jump_promotion
9462 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9463 as_warn_where (fragP->fr_file, fragP->fr_line,
9464 _("long jump required"));
252b5132 9465
fddf5b5b
AM		 9466 switch (fragP->fr_subtype)
9467 {
9468 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9469 extension = 4; /* 1 opcode + 4 displacement */
9470 opcode[0] = 0xe9;
9471 where_to_put_displacement = &opcode[1];
9472 break;
252b5132 9473
fddf5b5b
AM		 9474 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9475 extension = 2; /* 1 opcode + 2 displacement */
9476 opcode[0] = 0xe9;
9477 where_to_put_displacement = &opcode[1];
9478 break;
252b5132 9479
fddf5b5b
AM		 9480 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9481 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9482 extension = 5; /* 2 opcode + 4 displacement */
9483 opcode[1] = opcode[0] + 0x10;
9484 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9485 where_to_put_displacement = &opcode[2];
9486 break;
252b5132 9487
fddf5b5b
AM		 9488 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9489 extension = 3; /* 2 opcode + 2 displacement */
9490 opcode[1] = opcode[0] + 0x10;
9491 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9492 where_to_put_displacement = &opcode[2];
9493 break;
252b5132 9494
fddf5b5b
AM		 9495 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9496 extension = 4;
9497 opcode[0] ^= 1;
9498 opcode[1] = 3;
9499 opcode[2] = 0xe9;
9500 where_to_put_displacement = &opcode[3];
9501 break;
9502
9503 default:
9504 BAD_CASE (fragP->fr_subtype);
9505 break;
9506 }
252b5132 9507 }
fddf5b5b 9508
7b81dfbb
AJ		 9509 /* If size if less then four we are sure that the operand fits,
9510 but if it's 4, then it could be that the displacement is larger
9511 then -/+ 2GB. */
9512 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9513 && object_64bit
9514 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9515 + ((addressT) 1 << 31))
9516 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9517 {
9518 as_bad_where (fragP->fr_file, fragP->fr_line,
9519 _("jump target out of range"));
9520 /* Make us emit 0. */
9521 displacement_from_opcode_start = extension;
9522 }
47926f60 9523 /* Now put displacement after opcode. */
252b5132
RH		 9524 md_number_to_chars ((char *) where_to_put_displacement,
9525 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9526 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9527 fragP->fr_fix += extension;
9528}
9529\f
7016a5d5 9530/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9531 by our caller that we have all the info we need to fix it up.
9532
7016a5d5
TG		 9533 Parameter valP is the pointer to the value of the bits.
9534
252b5132
RH		 9535 On the 386, immediates, displacements, and data pointers are all in
9536 the same (little-endian) format, so we don't need to care about which
9537 we are handling. */
9538
94f592af 9539void
7016a5d5 9540md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9541{
94f592af 9542 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9543 valueT value = *valP;
252b5132 9544
f86103b7 9545#if !defined (TE_Mach)
93382f6d
AM		 9546 if (fixP->fx_pcrel)
9547 {
9548 switch (fixP->fx_r_type)
9549 {
5865bb77
ILT		 9550 default:
9551 break;
9552
d6ab8113
JB		 9553 case BFD_RELOC_64:
9554 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9555 break;
93382f6d 9556 case BFD_RELOC_32:
ae8887b5 9557 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9558 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9559 break;
9560 case BFD_RELOC_16:
9561 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9562 break;
9563 case BFD_RELOC_8:
9564 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9565 break;
9566 }
9567 }
252b5132 9568
a161fe53 9569 if (fixP->fx_addsy != NULL
31312f95 9570 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9571 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9572 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 9573 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 9574 && !use_rela_relocations)
252b5132 9575 {
31312f95
AM		 9576 /* This is a hack. There should be a better way to handle this.
9577 This covers for the fact that bfd_install_relocation will
9578 subtract the current location (for partial_inplace, PC relative
9579 relocations); see more below. */
252b5132 9580#ifndef OBJ_AOUT
718ddfc0 9581 if (IS_ELF
252b5132
RH		 9582#ifdef TE_PE
9583 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9584#endif
9585 )
9586 value += fixP->fx_where + fixP->fx_frag->fr_address;
9587#endif
9588#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9589 if (IS_ELF)
252b5132 9590 {
6539b54b 9591 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9592
6539b54b 9593 if ((sym_seg == seg
2f66722d 9594 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9595 && sym_seg != absolute_section))
af65af87 9596 && !generic_force_reloc (fixP))
2f66722d
AM		 9597 {
9598 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9599 bfd_install_relocation subtracts them out again. I think
9600 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9601 it. FIXME. */
9602 value += fixP->fx_where + fixP->fx_frag->fr_address;
9603 }
252b5132
RH		 9604 }
9605#endif
9606#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9607 /* For some reason, the PE format does not store a
9608 section address offset for a PC relative symbol. */
9609 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9610 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9611 value += md_pcrel_from (fixP);
9612#endif
9613 }
fbeb56a4 9614#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9615 if (fixP->fx_addsy != NULL
9616 && S_IS_WEAK (fixP->fx_addsy)
9617 /* PR 16858: Do not modify weak function references. */
9618 && ! fixP->fx_pcrel)
fbeb56a4 9619 {
296a8689
NC		 9620#if !defined (TE_PEP)
9621 /* For x86 PE weak function symbols are neither PC-relative
9622 nor do they set S_IS_FUNCTION. So the only reliable way
9623 to detect them is to check the flags of their containing
9624 section. */
9625 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9626 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9627 ;
9628 else
9629#endif
fbeb56a4
DK		 9630 value -= S_GET_VALUE (fixP->fx_addsy);
9631 }
9632#endif
252b5132
RH		 9633
9634 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9635 and we must not disappoint it. */
252b5132 9636#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9637 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9638 switch (fixP->fx_r_type)
9639 {
9640 case BFD_RELOC_386_PLT32:
3e73aa7c 9641 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 9642 /* Make the jump instruction point to the address of the operand. At
9643 runtime we merely add the offset to the actual PLT entry. */
9644 value = -4;
9645 break;
31312f95 9646
13ae64f3
JJ		 9647 case BFD_RELOC_386_TLS_GD:
9648 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9649 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9650 case BFD_RELOC_386_TLS_IE:
9651 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9652 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9653 case BFD_RELOC_X86_64_TLSGD:
9654 case BFD_RELOC_X86_64_TLSLD:
9655 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9656 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9657 value = 0; /* Fully resolved at runtime. No addend. */
9658 /* Fallthrough */
9659 case BFD_RELOC_386_TLS_LE:
9660 case BFD_RELOC_386_TLS_LDO_32:
9661 case BFD_RELOC_386_TLS_LE_32:
9662 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9663 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9664 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9665 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9666 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9667 break;
9668
67a4f2b7
AO		 9669 case BFD_RELOC_386_TLS_DESC_CALL:
9670 case BFD_RELOC_X86_64_TLSDESC_CALL:
9671 value = 0; /* Fully resolved at runtime. No addend. */
9672 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9673 fixP->fx_done = 0;
9674 return;
9675
47926f60
KH		 9676 case BFD_RELOC_VTABLE_INHERIT:
9677 case BFD_RELOC_VTABLE_ENTRY:
9678 fixP->fx_done = 0;
94f592af 9679 return;
47926f60
KH		 9680
9681 default:
9682 break;
9683 }
9684#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9685 *valP = value;
f86103b7 9686#endif /* !defined (TE_Mach) */
3e73aa7c 9687
3e73aa7c 9688 /* Are we finished with this relocation now? */
c6682705 9689 if (fixP->fx_addsy == NULL)
3e73aa7c 9690 fixP->fx_done = 1;
fbeb56a4
DK		 9691#if defined (OBJ_COFF) && defined (TE_PE)
9692 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9693 {
9694 fixP->fx_done = 0;
9695 /* Remember value for tc_gen_reloc. */
9696 fixP->fx_addnumber = value;
9697 /* Clear out the frag for now. */
9698 value = 0;
9699 }
9700#endif
3e73aa7c
JH		 9701 else if (use_rela_relocations)
9702 {
9703 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9704 /* Remember value for tc_gen_reloc. */
9705 fixP->fx_addnumber = value;
3e73aa7c
JH		 9706 value = 0;
9707 }
f86103b7 9708
94f592af 9709 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9710}
252b5132 9711\f
6d4af3c2 9712const char *
499ac353 9713md_atof (int type, char *litP, int *sizeP)
252b5132 9714{
499ac353
NC		 9715 /* This outputs the LITTLENUMs in REVERSE order;
9716 in accord with the bigendian 386. */
9717 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9718}
9719\f
2d545b82 9720static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9721
252b5132 9722static char *
e3bb37b5 9723output_invalid (int c)
252b5132 9724{
3882b010 9725 if (ISPRINT (c))
f9f21a03
L		 9726 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9727 "'%c'", c);
252b5132 9728 else
f9f21a03 9729 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9730 "(0x%x)", (unsigned char) c);
252b5132
RH		 9731 return output_invalid_buf;
9732}
9733
af6bdddf 9734/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9735
9736static const reg_entry *
4d1bb795 9737parse_real_register (char *reg_string, char **end_op)
252b5132 9738{
af6bdddf
AM		 9739 char *s = reg_string;
9740 char *p;
252b5132
RH		 9741 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9742 const reg_entry *r;
9743
9744 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9745 if (*s == REGISTER_PREFIX)
9746 ++s;
9747
9748 if (is_space_char (*s))
9749 ++s;
9750
9751 p = reg_name_given;
af6bdddf 9752 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9753 {
9754 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9755 return (const reg_entry *) NULL;
9756 s++;
252b5132
RH		 9757 }
9758
6588847e
DN		 9759 /* For naked regs, make sure that we are not dealing with an identifier.
9760 This prevents confusing an identifier like `eax_var' with register
9761 `eax'. */
9762 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9763 return (const reg_entry *) NULL;
9764
af6bdddf 9765 *end_op = s;
252b5132
RH		 9766
9767 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9768
5f47d35b 9769 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9770 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9771 {
5f47d35b
AM		 9772 if (is_space_char (*s))
9773 ++s;
9774 if (*s == '(')
9775 {
af6bdddf 9776 ++s;
5f47d35b
AM		 9777 if (is_space_char (*s))
9778 ++s;
9779 if (*s >= '0' && *s <= '7')
9780 {
db557034 9781 int fpr = *s - '0';
af6bdddf 9782 ++s;
5f47d35b
AM		 9783 if (is_space_char (*s))
9784 ++s;
9785 if (*s == ')')
9786 {
9787 *end_op = s + 1;
1e9cc1c2 9788 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9789 know (r);
9790 return r + fpr;
5f47d35b 9791 }
5f47d35b 9792 }
47926f60 9793 /* We have "%st(" then garbage. */
5f47d35b
AM		 9794 return (const reg_entry *) NULL;
9795 }
9796 }
9797
a60de03c
JB		 9798 if (r == NULL || allow_pseudo_reg)
9799 return r;
9800
0dfbf9d7 9801 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9802 return (const reg_entry *) NULL;
9803
192dc9c6
JB		 9804 if ((r->reg_type.bitfield.reg32
9805 || r->reg_type.bitfield.sreg3
9806 || r->reg_type.bitfield.control
9807 || r->reg_type.bitfield.debug
9808 || r->reg_type.bitfield.test)
9809 && !cpu_arch_flags.bitfield.cpui386)
9810 return (const reg_entry *) NULL;
9811
309d3373
JB		 9812 if (r->reg_type.bitfield.floatreg
9813 && !cpu_arch_flags.bitfield.cpu8087
9814 && !cpu_arch_flags.bitfield.cpu287
9815 && !cpu_arch_flags.bitfield.cpu387)
9816 return (const reg_entry *) NULL;
9817
1848e567 9818 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
192dc9c6
JB		 9819 return (const reg_entry *) NULL;
9820
1848e567 9821 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpuregxmm)
192dc9c6
JB		 9822 return (const reg_entry *) NULL;
9823
1848e567 9824 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuregymm)
40f12533
L		 9825 return (const reg_entry *) NULL;
9826
1848e567
L		 9827 if (r->reg_type.bitfield.regzmm && !cpu_arch_flags.bitfield.cpuregzmm)
9828 return (const reg_entry *) NULL;
9829
9830 if (r->reg_type.bitfield.regmask
9831 && !cpu_arch_flags.bitfield.cpuregmask)
43234a1e
L		 9832 return (const reg_entry *) NULL;
9833
db51cc60 9834 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9835 if (!allow_index_reg
db51cc60
L		 9836 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9837 return (const reg_entry *) NULL;
9838
43234a1e
L		 9839 /* Upper 16 vector register is only available with VREX in 64bit
9840 mode. */
9841 if ((r->reg_flags & RegVRex))
9842 {
86fa6981
L		 9843 if (i.vec_encoding == vex_encoding_default)
9844 i.vec_encoding = vex_encoding_evex;
9845
43234a1e 9846 if (!cpu_arch_flags.bitfield.cpuvrex
86fa6981 9847 || i.vec_encoding != vex_encoding_evex
43234a1e
L		 9848 || flag_code != CODE_64BIT)
9849 return (const reg_entry *) NULL;
43234a1e
L		 9850 }
9851
a60de03c
JB		 9852 if (((r->reg_flags & (RegRex64 | RegRex))
9853 || r->reg_type.bitfield.reg64)
40fb9820 9854 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9855 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9856 && flag_code != CODE_64BIT)
20f0a1fc 9857 return (const reg_entry *) NULL;
1ae00879 9858
b7240065
JB		 9859 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9860 return (const reg_entry *) NULL;
9861
252b5132
RH		 9862 return r;
9863}
4d1bb795
JB		 9864
9865/* REG_STRING starts *before* REGISTER_PREFIX. */
9866
9867static const reg_entry *
9868parse_register (char *reg_string, char **end_op)
9869{
9870 const reg_entry *r;
9871
9872 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9873 r = parse_real_register (reg_string, end_op);
9874 else
9875 r = NULL;
9876 if (!r)
9877 {
9878 char *save = input_line_pointer;
9879 char c;
9880 symbolS *symbolP;
9881
9882 input_line_pointer = reg_string;
d02603dc 9883 c = get_symbol_name (&reg_string);
4d1bb795
JB		 9884 symbolP = symbol_find (reg_string);
9885 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9886 {
9887 const expressionS *e = symbol_get_value_expression (symbolP);
9888
0398aac5 9889 know (e->X_op == O_register);
4eed87de 9890 know (e->X_add_number >= 0
c3fe08fa 9891 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 9892 r = i386_regtab + e->X_add_number;
d3bb6b49 9893 if ((r->reg_flags & RegVRex))
86fa6981 9894 i.vec_encoding = vex_encoding_evex;
4d1bb795
JB		 9895 *end_op = input_line_pointer;
9896 }
9897 *input_line_pointer = c;
9898 input_line_pointer = save;
9899 }
9900 return r;
9901}
9902
9903int
9904i386_parse_name (char *name, expressionS *e, char *nextcharP)
9905{
9906 const reg_entry *r;
9907 char *end = input_line_pointer;
9908
9909 *end = *nextcharP;
9910 r = parse_register (name, &input_line_pointer);
9911 if (r && end <= input_line_pointer)
9912 {
9913 *nextcharP = *input_line_pointer;
9914 *input_line_pointer = 0;
9915 e->X_op = O_register;
9916 e->X_add_number = r - i386_regtab;
9917 return 1;
9918 }
9919 input_line_pointer = end;
9920 *end = 0;
ee86248c 9921 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9922}
9923
9924void
9925md_operand (expressionS *e)
9926{
ee86248c
JB		 9927 char *end;
9928 const reg_entry *r;
4d1bb795 9929
ee86248c
JB		 9930 switch (*input_line_pointer)
9931 {
9932 case REGISTER_PREFIX:
9933 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9934 if (r)
9935 {
9936 e->X_op = O_register;
9937 e->X_add_number = r - i386_regtab;
9938 input_line_pointer = end;
9939 }
ee86248c
JB		 9940 break;
9941
9942 case '[':
9c2799c2 9943 gas_assert (intel_syntax);
ee86248c
JB		 9944 end = input_line_pointer++;
9945 expression (e);
9946 if (*input_line_pointer == ']')
9947 {
9948 ++input_line_pointer;
9949 e->X_op_symbol = make_expr_symbol (e);
9950 e->X_add_symbol = NULL;
9951 e->X_add_number = 0;
9952 e->X_op = O_index;
9953 }
9954 else
9955 {
9956 e->X_op = O_absent;
9957 input_line_pointer = end;
9958 }
9959 break;
4d1bb795
JB		 9960 }
9961}
9962
252b5132 9963\f
4cc782b5 9964#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9965const char *md_shortopts = "kVQ:sqn";
252b5132 9966#else
12b55ccc 9967const char *md_shortopts = "qn";
252b5132 9968#endif
6e0b89ee 9969
3e73aa7c 9970#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9971#define OPTION_64 (OPTION_MD_BASE + 1)
9972#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9973#define OPTION_MARCH (OPTION_MD_BASE + 3)
9974#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9975#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9976#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9977#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9978#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9979#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9980#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9981#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9982#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9983#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9984#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9985#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9986#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9987#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 9988#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
d1982f93 9989#define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 9990#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
8dcea932 9991#define OPTION_MSHARED (OPTION_MD_BASE + 21)
5db04b09
L		 9992#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9993#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
e4e00185 9994#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
0cb4071e 9995#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
b3b91714 9996
99ad8390
NC		 9997struct option md_longopts[] =
9998{
3e73aa7c 9999 {"32", no_argument, NULL, OPTION_32},
321098a5 10000#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 10001 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 10002 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 10003#endif
10004#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 10005 {"x32", no_argument, NULL, OPTION_X32},
8dcea932 10006 {"mshared", no_argument, NULL, OPTION_MSHARED},
6e0b89ee 10007#endif
b3b91714 10008 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 10009 {"march", required_argument, NULL, OPTION_MARCH},
10010 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 10011 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10012 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10013 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10014 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
10015 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 10016 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 10017 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 10018 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 10019 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 10020 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 10021 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10022 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 10023# if defined (TE_PE) || defined (TE_PEP)
10024 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10025#endif
d1982f93 10026 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
e4e00185 10027 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
0cb4071e 10028 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
d3d3c6db 10029 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
5db04b09
L		 10030 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10031 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
252b5132
RH		 10032 {NULL, no_argument, NULL, 0}
10033};
10034size_t md_longopts_size = sizeof (md_longopts);
10035
10036int
17b9d67d 10037md_parse_option (int c, const char *arg)
252b5132 10038{
91d6fa6a 10039 unsigned int j;
293f5f65 10040 char *arch, *next, *saved;
9103f4f4 10041
252b5132
RH		 10042 switch (c)
10043 {
12b55ccc
L		 10044 case 'n':
10045 optimize_align_code = 0;
10046 break;
10047
a38cf1db
AM		 10048 case 'q':
10049 quiet_warnings = 1;
252b5132
RH		 10050 break;
10051
10052#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 10053 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10054 should be emitted or not. FIXME: Not implemented. */
10055 case 'Q':
252b5132
RH		 10056 break;
10057
10058 /* -V: SVR4 argument to print version ID. */
10059 case 'V':
10060 print_version_id ();
10061 break;
10062
a38cf1db
AM		 10063 /* -k: Ignore for FreeBSD compatibility. */
10064 case 'k':
252b5132 10065 break;
4cc782b5
ILT		 10066
10067 case 's':
10068 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 10069 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 10070 break;
8dcea932
L		 10071
10072 case OPTION_MSHARED:
10073 shared = 1;
10074 break;
99ad8390 10075#endif
321098a5 10076#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 10077 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 10078 case OPTION_64:
10079 {
10080 const char **list, **l;
10081
3e73aa7c
JH		 10082 list = bfd_target_list ();
10083 for (l = list; *l != NULL; l++)
8620418b 10084 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 10085 || strcmp (*l, "coff-x86-64") == 0
10086 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 10087 || strcmp (*l, "pei-x86-64") == 0
10088 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 10089 {
10090 default_arch = "x86_64";
10091 break;
10092 }
3e73aa7c 10093 if (*l == NULL)
2b5d6a91 10094 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 10095 free (list);
10096 }
10097 break;
10098#endif
252b5132 10099
351f65ca 10100#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 10101 case OPTION_X32:
351f65ca
L		 10102 if (IS_ELF)
10103 {
10104 const char **list, **l;
10105
10106 list = bfd_target_list ();
10107 for (l = list; *l != NULL; l++)
10108 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10109 {
10110 default_arch = "x86_64:32";
10111 break;
10112 }
10113 if (*l == NULL)
2b5d6a91 10114 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 10115 free (list);
10116 }
10117 else
10118 as_fatal (_("32bit x86_64 is only supported for ELF"));
10119 break;
10120#endif
10121
6e0b89ee
AM		 10122 case OPTION_32:
10123 default_arch = "i386";
10124 break;
10125
b3b91714
AM		 10126 case OPTION_DIVIDE:
10127#ifdef SVR4_COMMENT_CHARS
10128 {
10129 char *n, *t;
10130 const char *s;
10131
add39d23 10132 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
b3b91714
AM		 10133 t = n;
10134 for (s = i386_comment_chars; *s != '\0'; s++)
10135 if (*s != '/')
10136 *t++ = *s;
10137 *t = '\0';
10138 i386_comment_chars = n;
10139 }
10140#endif
10141 break;
10142
9103f4f4 10143 case OPTION_MARCH:
293f5f65
L		 10144 saved = xstrdup (arg);
10145 arch = saved;
10146 /* Allow -march=+nosse. */
10147 if (*arch == '+')
10148 arch++;
6305a203 10149 do
9103f4f4 10150 {
6305a203 10151 if (*arch == '.')
2b5d6a91 10152 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10153 next = strchr (arch, '+');
10154 if (next)
10155 *next++ = '\0';
91d6fa6a 10156 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10157 {
91d6fa6a 10158 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 10159 {
6305a203 10160 /* Processor. */
1ded5609
JB		 10161 if (! cpu_arch[j].flags.bitfield.cpui386)
10162 continue;
10163
91d6fa6a 10164 cpu_arch_name = cpu_arch[j].name;
6305a203 10165 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 10166 cpu_arch_flags = cpu_arch[j].flags;
10167 cpu_arch_isa = cpu_arch[j].type;
10168 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 10169 if (!cpu_arch_tune_set)
10170 {
10171 cpu_arch_tune = cpu_arch_isa;
10172 cpu_arch_tune_flags = cpu_arch_isa_flags;
10173 }
10174 break;
10175 }
91d6fa6a
NC		 10176 else if (*cpu_arch [j].name == '.'
10177 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203 10178 {
33eaf5de 10179 /* ISA extension. */
6305a203 10180 i386_cpu_flags flags;
309d3373 10181
293f5f65
L		 10182 flags = cpu_flags_or (cpu_arch_flags,
10183 cpu_arch[j].flags);
81486035 10184
5b64d091 10185 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 10186 {
10187 if (cpu_sub_arch_name)
10188 {
10189 char *name = cpu_sub_arch_name;
10190 cpu_sub_arch_name = concat (name,
91d6fa6a 10191 cpu_arch[j].name,
1bf57e9f 10192 (const char *) NULL);
6305a203
L		 10193 free (name);
10194 }
10195 else
91d6fa6a 10196 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 10197 cpu_arch_flags = flags;
a586129e 10198 cpu_arch_isa_flags = flags;
6305a203
L		 10199 }
10200 break;
ccc9c027 10201 }
9103f4f4 10202 }
6305a203 10203
293f5f65
L		 10204 if (j >= ARRAY_SIZE (cpu_arch))
10205 {
33eaf5de 10206 /* Disable an ISA extension. */
293f5f65
L		 10207 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10208 if (strcmp (arch, cpu_noarch [j].name) == 0)
10209 {
10210 i386_cpu_flags flags;
10211
10212 flags = cpu_flags_and_not (cpu_arch_flags,
10213 cpu_noarch[j].flags);
10214 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10215 {
10216 if (cpu_sub_arch_name)
10217 {
10218 char *name = cpu_sub_arch_name;
10219 cpu_sub_arch_name = concat (arch,
10220 (const char *) NULL);
10221 free (name);
10222 }
10223 else
10224 cpu_sub_arch_name = xstrdup (arch);
10225 cpu_arch_flags = flags;
10226 cpu_arch_isa_flags = flags;
10227 }
10228 break;
10229 }
10230
10231 if (j >= ARRAY_SIZE (cpu_noarch))
10232 j = ARRAY_SIZE (cpu_arch);
10233 }
10234
91d6fa6a 10235 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10236 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10237
10238 arch = next;
9103f4f4 10239 }
293f5f65
L		 10240 while (next != NULL);
10241 free (saved);
9103f4f4
L		 10242 break;
10243
10244 case OPTION_MTUNE:
10245 if (*arg == '.')
2b5d6a91 10246 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 10247 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10248 {
91d6fa6a 10249 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 10250 {
ccc9c027 10251 cpu_arch_tune_set = 1;
91d6fa6a
NC		 10252 cpu_arch_tune = cpu_arch [j].type;
10253 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 10254 break;
10255 }
10256 }
91d6fa6a 10257 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10258 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 10259 break;
10260
1efbbeb4
L		 10261 case OPTION_MMNEMONIC:
10262 if (strcasecmp (arg, "att") == 0)
10263 intel_mnemonic = 0;
10264 else if (strcasecmp (arg, "intel") == 0)
10265 intel_mnemonic = 1;
10266 else
2b5d6a91 10267 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 10268 break;
10269
10270 case OPTION_MSYNTAX:
10271 if (strcasecmp (arg, "att") == 0)
10272 intel_syntax = 0;
10273 else if (strcasecmp (arg, "intel") == 0)
10274 intel_syntax = 1;
10275 else
2b5d6a91 10276 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 10277 break;
10278
10279 case OPTION_MINDEX_REG:
10280 allow_index_reg = 1;
10281 break;
10282
10283 case OPTION_MNAKED_REG:
10284 allow_naked_reg = 1;
10285 break;
10286
10287 case OPTION_MOLD_GCC:
10288 old_gcc = 1;
1efbbeb4
L		 10289 break;
10290
c0f3af97
L		 10291 case OPTION_MSSE2AVX:
10292 sse2avx = 1;
10293 break;
10294
daf50ae7
L		 10295 case OPTION_MSSE_CHECK:
10296 if (strcasecmp (arg, "error") == 0)
7bab8ab5 10297 sse_check = check_error;
daf50ae7 10298 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 10299 sse_check = check_warning;
daf50ae7 10300 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 10301 sse_check = check_none;
daf50ae7 10302 else
2b5d6a91 10303 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 10304 break;
10305
7bab8ab5
JB		 10306 case OPTION_MOPERAND_CHECK:
10307 if (strcasecmp (arg, "error") == 0)
10308 operand_check = check_error;
10309 else if (strcasecmp (arg, "warning") == 0)
10310 operand_check = check_warning;
10311 else if (strcasecmp (arg, "none") == 0)
10312 operand_check = check_none;
10313 else
10314 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10315 break;
10316
539f890d
L		 10317 case OPTION_MAVXSCALAR:
10318 if (strcasecmp (arg, "128") == 0)
10319 avxscalar = vex128;
10320 else if (strcasecmp (arg, "256") == 0)
10321 avxscalar = vex256;
10322 else
2b5d6a91 10323 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 10324 break;
10325
7e8b059b
L		 10326 case OPTION_MADD_BND_PREFIX:
10327 add_bnd_prefix = 1;
10328 break;
10329
43234a1e
L		 10330 case OPTION_MEVEXLIG:
10331 if (strcmp (arg, "128") == 0)
10332 evexlig = evexl128;
10333 else if (strcmp (arg, "256") == 0)
10334 evexlig = evexl256;
10335 else if (strcmp (arg, "512") == 0)
10336 evexlig = evexl512;
10337 else
10338 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10339 break;
10340
d3d3c6db
IT		 10341 case OPTION_MEVEXRCIG:
10342 if (strcmp (arg, "rne") == 0)
10343 evexrcig = rne;
10344 else if (strcmp (arg, "rd") == 0)
10345 evexrcig = rd;
10346 else if (strcmp (arg, "ru") == 0)
10347 evexrcig = ru;
10348 else if (strcmp (arg, "rz") == 0)
10349 evexrcig = rz;
10350 else
10351 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10352 break;
10353
43234a1e
L		 10354 case OPTION_MEVEXWIG:
10355 if (strcmp (arg, "0") == 0)
10356 evexwig = evexw0;
10357 else if (strcmp (arg, "1") == 0)
10358 evexwig = evexw1;
10359 else
10360 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10361 break;
10362
167ad85b
TG		 10363# if defined (TE_PE) || defined (TE_PEP)
10364 case OPTION_MBIG_OBJ:
10365 use_big_obj = 1;
10366 break;
10367#endif
10368
d1982f93 10369 case OPTION_MOMIT_LOCK_PREFIX:
d022bddd
IT		 10370 if (strcasecmp (arg, "yes") == 0)
10371 omit_lock_prefix = 1;
10372 else if (strcasecmp (arg, "no") == 0)
10373 omit_lock_prefix = 0;
10374 else
10375 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10376 break;
10377
e4e00185
AS		 10378 case OPTION_MFENCE_AS_LOCK_ADD:
10379 if (strcasecmp (arg, "yes") == 0)
10380 avoid_fence = 1;
10381 else if (strcasecmp (arg, "no") == 0)
10382 avoid_fence = 0;
10383 else
10384 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10385 break;
10386
0cb4071e
L		 10387 case OPTION_MRELAX_RELOCATIONS:
10388 if (strcasecmp (arg, "yes") == 0)
10389 generate_relax_relocations = 1;
10390 else if (strcasecmp (arg, "no") == 0)
10391 generate_relax_relocations = 0;
10392 else
10393 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10394 break;
10395
5db04b09 10396 case OPTION_MAMD64:
e89c5eaa 10397 intel64 = 0;
5db04b09
L		 10398 break;
10399
10400 case OPTION_MINTEL64:
e89c5eaa 10401 intel64 = 1;
5db04b09
L		 10402 break;
10403
252b5132
RH		 10404 default:
10405 return 0;
10406 }
10407 return 1;
10408}
10409
8a2c8fef
L		 10410#define MESSAGE_TEMPLATE \
10411" "
10412
293f5f65
L		 10413static char *
10414output_message (FILE *stream, char *p, char *message, char *start,
10415 int *left_p, const char *name, int len)
10416{
10417 int size = sizeof (MESSAGE_TEMPLATE);
10418 int left = *left_p;
10419
10420 /* Reserve 2 spaces for ", " or ",\0" */
10421 left -= len + 2;
10422
10423 /* Check if there is any room. */
10424 if (left >= 0)
10425 {
10426 if (p != start)
10427 {
10428 *p++ = ',';
10429 *p++ = ' ';
10430 }
10431 p = mempcpy (p, name, len);
10432 }
10433 else
10434 {
10435 /* Output the current message now and start a new one. */
10436 *p++ = ',';
10437 *p = '\0';
10438 fprintf (stream, "%s\n", message);
10439 p = start;
10440 left = size - (start - message) - len - 2;
10441
10442 gas_assert (left >= 0);
10443
10444 p = mempcpy (p, name, len);
10445 }
10446
10447 *left_p = left;
10448 return p;
10449}
10450
8a2c8fef 10451static void
1ded5609 10452show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 10453{
10454 static char message[] = MESSAGE_TEMPLATE;
10455 char *start = message + 27;
10456 char *p;
10457 int size = sizeof (MESSAGE_TEMPLATE);
10458 int left;
10459 const char *name;
10460 int len;
10461 unsigned int j;
10462
10463 p = start;
10464 left = size - (start - message);
10465 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10466 {
10467 /* Should it be skipped? */
10468 if (cpu_arch [j].skip)
10469 continue;
10470
10471 name = cpu_arch [j].name;
10472 len = cpu_arch [j].len;
10473 if (*name == '.')
10474 {
10475 /* It is an extension. Skip if we aren't asked to show it. */
10476 if (ext)
10477 {
10478 name++;
10479 len--;
10480 }
10481 else
10482 continue;
10483 }
10484 else if (ext)
10485 {
10486 /* It is an processor. Skip if we show only extension. */
10487 continue;
10488 }
1ded5609
JB		 10489 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10490 {
10491 /* It is an impossible processor - skip. */
10492 continue;
10493 }
8a2c8fef 10494
293f5f65 10495 p = output_message (stream, p, message, start, &left, name, len);
8a2c8fef
L		 10496 }
10497
293f5f65
L		 10498 /* Display disabled extensions. */
10499 if (ext)
10500 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10501 {
10502 name = cpu_noarch [j].name;
10503 len = cpu_noarch [j].len;
10504 p = output_message (stream, p, message, start, &left, name,
10505 len);
10506 }
10507
8a2c8fef
L		 10508 *p = '\0';
10509 fprintf (stream, "%s\n", message);
10510}
10511
252b5132 10512void
8a2c8fef 10513md_show_usage (FILE *stream)
252b5132 10514{
4cc782b5
ILT		 10515#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10516 fprintf (stream, _("\
a38cf1db
AM		 10517 -Q ignored\n\
10518 -V print assembler version number\n\
b3b91714
AM		 10519 -k ignored\n"));
10520#endif
10521 fprintf (stream, _("\
12b55ccc 10522 -n Do not optimize code alignment\n\
b3b91714
AM		 10523 -q quieten some warnings\n"));
10524#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10525 fprintf (stream, _("\
a38cf1db 10526 -s ignored\n"));
b3b91714 10527#endif
321098a5
L		 10528#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10529 || defined (TE_PE) || defined (TE_PEP))
751d281c 10530 fprintf (stream, _("\
570561f7 10531 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10532#endif
b3b91714
AM		 10533#ifdef SVR4_COMMENT_CHARS
10534 fprintf (stream, _("\
10535 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10536#else
10537 fprintf (stream, _("\
b3b91714 10538 --divide ignored\n"));
4cc782b5 10539#endif
9103f4f4 10540 fprintf (stream, _("\
6305a203 10541 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10542 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10543 show_arch (stream, 0, 1);
8a2c8fef
L		 10544 fprintf (stream, _("\
10545 EXTENSION is combination of:\n"));
1ded5609 10546 show_arch (stream, 1, 0);
6305a203 10547 fprintf (stream, _("\
8a2c8fef 10548 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10549 show_arch (stream, 0, 0);
ba104c83 10550 fprintf (stream, _("\
c0f3af97
L		 10551 -msse2avx encode SSE instructions with VEX prefix\n"));
10552 fprintf (stream, _("\
daf50ae7
L		 10553 -msse-check=[none|error|warning]\n\
10554 check SSE instructions\n"));
10555 fprintf (stream, _("\
7bab8ab5
JB		 10556 -moperand-check=[none|error|warning]\n\
10557 check operand combinations for validity\n"));
10558 fprintf (stream, _("\
539f890d
L		 10559 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10560 length\n"));
10561 fprintf (stream, _("\
43234a1e
L		 10562 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10563 length\n"));
10564 fprintf (stream, _("\
10565 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10566 for EVEX.W bit ignored instructions\n"));
10567 fprintf (stream, _("\
d3d3c6db
IT		 10568 -mevexrcig=[rne|rd|ru|rz]\n\
10569 encode EVEX instructions with specific EVEX.RC value\n\
10570 for SAE-only ignored instructions\n"));
10571 fprintf (stream, _("\
ba104c83
L		 10572 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10573 fprintf (stream, _("\
10574 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10575 fprintf (stream, _("\
10576 -mindex-reg support pseudo index registers\n"));
10577 fprintf (stream, _("\
10578 -mnaked-reg don't require `%%' prefix for registers\n"));
10579 fprintf (stream, _("\
10580 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 10581 fprintf (stream, _("\
10582 -madd-bnd-prefix add BND prefix for all valid branches\n"));
8dcea932
L		 10583 fprintf (stream, _("\
10584 -mshared disable branch optimization for shared code\n"));
167ad85b
TG		 10585# if defined (TE_PE) || defined (TE_PEP)
10586 fprintf (stream, _("\
10587 -mbig-obj generate big object files\n"));
10588#endif
d022bddd
IT		 10589 fprintf (stream, _("\
10590 -momit-lock-prefix=[no|yes]\n\
10591 strip all lock prefixes\n"));
5db04b09 10592 fprintf (stream, _("\
e4e00185
AS		 10593 -mfence-as-lock-add=[no|yes]\n\
10594 encode lfence, mfence and sfence as\n\
10595 lock addl $0x0, (%%{re}sp)\n"));
10596 fprintf (stream, _("\
0cb4071e
L		 10597 -mrelax-relocations=[no|yes]\n\
10598 generate relax relocations\n"));
10599 fprintf (stream, _("\
5db04b09
L		 10600 -mamd64 accept only AMD64 ISA\n"));
10601 fprintf (stream, _("\
10602 -mintel64 accept only Intel64 ISA\n"));
252b5132
RH		 10603}
10604
3e73aa7c 10605#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 10606 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 10607 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 10608
10609/* Pick the target format to use. */
10610
47926f60 10611const char *
e3bb37b5 10612i386_target_format (void)
252b5132 10613{
351f65ca
L		 10614 if (!strncmp (default_arch, "x86_64", 6))
10615 {
10616 update_code_flag (CODE_64BIT, 1);
10617 if (default_arch[6] == '\0')
7f56bc95 10618 x86_elf_abi = X86_64_ABI;
351f65ca 10619 else
7f56bc95 10620 x86_elf_abi = X86_64_X32_ABI;
351f65ca 10621 }
3e73aa7c 10622 else if (!strcmp (default_arch, "i386"))
78f12dd3 10623 update_code_flag (CODE_32BIT, 1);
5197d474
L		 10624 else if (!strcmp (default_arch, "iamcu"))
10625 {
10626 update_code_flag (CODE_32BIT, 1);
10627 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10628 {
10629 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10630 cpu_arch_name = "iamcu";
10631 cpu_sub_arch_name = NULL;
10632 cpu_arch_flags = iamcu_flags;
10633 cpu_arch_isa = PROCESSOR_IAMCU;
10634 cpu_arch_isa_flags = iamcu_flags;
10635 if (!cpu_arch_tune_set)
10636 {
10637 cpu_arch_tune = cpu_arch_isa;
10638 cpu_arch_tune_flags = cpu_arch_isa_flags;
10639 }
10640 }
8d471ec1 10641 else if (cpu_arch_isa != PROCESSOR_IAMCU)
5197d474
L		 10642 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10643 cpu_arch_name);
10644 }
3e73aa7c 10645 else
2b5d6a91 10646 as_fatal (_("unknown architecture"));
89507696
JB		 10647
10648 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10649 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10650 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10651 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10652
252b5132
RH		 10653 switch (OUTPUT_FLAVOR)
10654 {
9384f2ff 10655#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 10656 case bfd_target_aout_flavour:
47926f60 10657 return AOUT_TARGET_FORMAT;
4c63da97 10658#endif
9384f2ff
AM		 10659#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10660# if defined (TE_PE) || defined (TE_PEP)
10661 case bfd_target_coff_flavour:
167ad85b
TG		 10662 if (flag_code == CODE_64BIT)
10663 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10664 else
10665 return "pe-i386";
9384f2ff 10666# elif defined (TE_GO32)
0561d57c
JK		 10667 case bfd_target_coff_flavour:
10668 return "coff-go32";
9384f2ff 10669# else
252b5132
RH		 10670 case bfd_target_coff_flavour:
10671 return "coff-i386";
9384f2ff 10672# endif
4c63da97 10673#endif
3e73aa7c 10674#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 10675 case bfd_target_elf_flavour:
3e73aa7c 10676 {
351f65ca
L		 10677 const char *format;
10678
10679 switch (x86_elf_abi)
4fa24527 10680 {
351f65ca
L		 10681 default:
10682 format = ELF_TARGET_FORMAT;
10683 break;
7f56bc95 10684 case X86_64_ABI:
351f65ca 10685 use_rela_relocations = 1;
4fa24527 10686 object_64bit = 1;
351f65ca
L		 10687 format = ELF_TARGET_FORMAT64;
10688 break;
7f56bc95 10689 case X86_64_X32_ABI:
4fa24527 10690 use_rela_relocations = 1;
351f65ca 10691 object_64bit = 1;
862be3fb 10692 disallow_64bit_reloc = 1;
351f65ca
L		 10693 format = ELF_TARGET_FORMAT32;
10694 break;
4fa24527 10695 }
3632d14b 10696 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10697 {
7f56bc95 10698 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10699 as_fatal (_("Intel L1OM is 64bit only"));
10700 return ELF_TARGET_L1OM_FORMAT;
10701 }
b49f93f6 10702 else if (cpu_arch_isa == PROCESSOR_K1OM)
7a9068fe
L		 10703 {
10704 if (x86_elf_abi != X86_64_ABI)
10705 as_fatal (_("Intel K1OM is 64bit only"));
10706 return ELF_TARGET_K1OM_FORMAT;
10707 }
81486035
L		 10708 else if (cpu_arch_isa == PROCESSOR_IAMCU)
10709 {
10710 if (x86_elf_abi != I386_ABI)
10711 as_fatal (_("Intel MCU is 32bit only"));
10712 return ELF_TARGET_IAMCU_FORMAT;
10713 }
8a9036a4 10714 else
351f65ca 10715 return format;
3e73aa7c 10716 }
e57f8c65
TG		 10717#endif
10718#if defined (OBJ_MACH_O)
10719 case bfd_target_mach_o_flavour:
d382c579
TG		 10720 if (flag_code == CODE_64BIT)
10721 {
10722 use_rela_relocations = 1;
10723 object_64bit = 1;
10724 return "mach-o-x86-64";
10725 }
10726 else
10727 return "mach-o-i386";
4c63da97 10728#endif
252b5132
RH		 10729 default:
10730 abort ();
10731 return NULL;
10732 }
10733}
10734
47926f60 10735#endif /* OBJ_MAYBE_ more than one */
252b5132 10736\f
252b5132 10737symbolS *
7016a5d5 10738md_undefined_symbol (char *name)
252b5132 10739{
18dc2407
ILT		 10740 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10741 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10742 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10743 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10744 {
10745 if (!GOT_symbol)
10746 {
10747 if (symbol_find (name))
10748 as_bad (_("GOT already in symbol table"));
10749 GOT_symbol = symbol_new (name, undefined_section,
10750 (valueT) 0, &zero_address_frag);
10751 };
10752 return GOT_symbol;
10753 }
252b5132
RH		 10754 return 0;
10755}
10756
10757/* Round up a section size to the appropriate boundary. */
47926f60 10758
252b5132 10759valueT
7016a5d5 10760md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10761{
4c63da97
AM		 10762#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10763 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10764 {
10765 /* For a.out, force the section size to be aligned. If we don't do
10766 this, BFD will align it for us, but it will not write out the
10767 final bytes of the section. This may be a bug in BFD, but it is
10768 easier to fix it here since that is how the other a.out targets
10769 work. */
10770 int align;
10771
10772 align = bfd_get_section_alignment (stdoutput, segment);
8d3842cd 10773 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
4c63da97 10774 }
252b5132
RH		 10775#endif
10776
10777 return size;
10778}
10779
10780/* On the i386, PC-relative offsets are relative to the start of the
10781 next instruction. That is, the address of the offset, plus its
10782 size, since the offset is always the last part of the insn. */
10783
10784long
e3bb37b5 10785md_pcrel_from (fixS *fixP)
252b5132
RH		 10786{
10787 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10788}
10789
10790#ifndef I386COFF
10791
10792static void
e3bb37b5 10793s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10794{
29b0f896 10795 int temp;
252b5132 10796
8a75718c
JB		 10797#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10798 if (IS_ELF)
10799 obj_elf_section_change_hook ();
10800#endif
252b5132
RH		 10801 temp = get_absolute_expression ();
10802 subseg_set (bss_section, (subsegT) temp);
10803 demand_empty_rest_of_line ();
10804}
10805
10806#endif
10807
252b5132 10808void
e3bb37b5 10809i386_validate_fix (fixS *fixp)
252b5132 10810{
02a86693 10811 if (fixp->fx_subsy)
252b5132 10812 {
02a86693 10813 if (fixp->fx_subsy == GOT_symbol)
23df1078 10814 {
02a86693
L		 10815 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10816 {
10817 if (!object_64bit)
10818 abort ();
10819#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10820 if (fixp->fx_tcbit2)
56ceb5b5
L		 10821 fixp->fx_r_type = (fixp->fx_tcbit
10822 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10823 : BFD_RELOC_X86_64_GOTPCRELX);
02a86693
L		 10824 else
10825#endif
10826 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10827 }
d6ab8113 10828 else
02a86693
L		 10829 {
10830 if (!object_64bit)
10831 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10832 else
10833 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
10834 }
10835 fixp->fx_subsy = 0;
23df1078 10836 }
252b5132 10837 }
02a86693
L		 10838#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10839 else if (!object_64bit)
10840 {
10841 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
10842 && fixp->fx_tcbit2)
10843 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
10844 }
10845#endif
252b5132
RH		 10846}
10847
252b5132 10848arelent *
7016a5d5 10849tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10850{
10851 arelent *rel;
10852 bfd_reloc_code_real_type code;
10853
10854 switch (fixp->fx_r_type)
10855 {
8ce3d284 10856#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10857 case BFD_RELOC_SIZE32:
10858 case BFD_RELOC_SIZE64:
10859 if (S_IS_DEFINED (fixp->fx_addsy)
10860 && !S_IS_EXTERNAL (fixp->fx_addsy))
10861 {
10862 /* Resolve size relocation against local symbol to size of
10863 the symbol plus addend. */
10864 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10865 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10866 && !fits_in_unsigned_long (value))
10867 as_bad_where (fixp->fx_file, fixp->fx_line,
10868 _("symbol size computation overflow"));
10869 fixp->fx_addsy = NULL;
10870 fixp->fx_subsy = NULL;
10871 md_apply_fix (fixp, (valueT *) &value, NULL);
10872 return NULL;
10873 }
8ce3d284 10874#endif
1a0670f3 10875 /* Fall through. */
8fd4256d 10876
3e73aa7c
JH		 10877 case BFD_RELOC_X86_64_PLT32:
10878 case BFD_RELOC_X86_64_GOT32:
10879 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 10880 case BFD_RELOC_X86_64_GOTPCRELX:
10881 case BFD_RELOC_X86_64_REX_GOTPCRELX:
252b5132
RH		 10882 case BFD_RELOC_386_PLT32:
10883 case BFD_RELOC_386_GOT32:
02a86693 10884 case BFD_RELOC_386_GOT32X:
252b5132
RH		 10885 case BFD_RELOC_386_GOTOFF:
10886 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10887 case BFD_RELOC_386_TLS_GD:
10888 case BFD_RELOC_386_TLS_LDM:
10889 case BFD_RELOC_386_TLS_LDO_32:
10890 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10891 case BFD_RELOC_386_TLS_IE:
10892 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10893 case BFD_RELOC_386_TLS_LE_32:
10894 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10895 case BFD_RELOC_386_TLS_GOTDESC:
10896 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10897 case BFD_RELOC_X86_64_TLSGD:
10898 case BFD_RELOC_X86_64_TLSLD:
10899 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10900 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10901 case BFD_RELOC_X86_64_GOTTPOFF:
10902 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10903 case BFD_RELOC_X86_64_TPOFF64:
10904 case BFD_RELOC_X86_64_GOTOFF64:
10905 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10906 case BFD_RELOC_X86_64_GOT64:
10907 case BFD_RELOC_X86_64_GOTPCREL64:
10908 case BFD_RELOC_X86_64_GOTPC64:
10909 case BFD_RELOC_X86_64_GOTPLT64:
10910 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10911 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10912 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10913 case BFD_RELOC_RVA:
10914 case BFD_RELOC_VTABLE_ENTRY:
10915 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10916#ifdef TE_PE
10917 case BFD_RELOC_32_SECREL:
10918#endif
252b5132
RH		 10919 code = fixp->fx_r_type;
10920 break;
dbbaec26
L		 10921 case BFD_RELOC_X86_64_32S:
10922 if (!fixp->fx_pcrel)
10923 {
10924 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10925 code = fixp->fx_r_type;
10926 break;
10927 }
1a0670f3 10928 /* Fall through. */
252b5132 10929 default:
93382f6d 10930 if (fixp->fx_pcrel)
252b5132 10931 {
93382f6d
AM		 10932 switch (fixp->fx_size)
10933 {
10934 default:
b091f402
AM		 10935 as_bad_where (fixp->fx_file, fixp->fx_line,
10936 _("can not do %d byte pc-relative relocation"),
10937 fixp->fx_size);
93382f6d
AM		 10938 code = BFD_RELOC_32_PCREL;
10939 break;
10940 case 1: code = BFD_RELOC_8_PCREL; break;
10941 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 10942 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 10943#ifdef BFD64
10944 case 8: code = BFD_RELOC_64_PCREL; break;
10945#endif
93382f6d
AM		 10946 }
10947 }
10948 else
10949 {
10950 switch (fixp->fx_size)
10951 {
10952 default:
b091f402
AM		 10953 as_bad_where (fixp->fx_file, fixp->fx_line,
10954 _("can not do %d byte relocation"),
10955 fixp->fx_size);
93382f6d
AM		 10956 code = BFD_RELOC_32;
10957 break;
10958 case 1: code = BFD_RELOC_8; break;
10959 case 2: code = BFD_RELOC_16; break;
10960 case 4: code = BFD_RELOC_32; break;
937149dd 10961#ifdef BFD64
3e73aa7c 10962 case 8: code = BFD_RELOC_64; break;
937149dd 10963#endif
93382f6d 10964 }
252b5132
RH		 10965 }
10966 break;
10967 }
252b5132 10968
d182319b
JB		 10969 if ((code == BFD_RELOC_32
10970 || code == BFD_RELOC_32_PCREL
10971 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10972 && GOT_symbol
10973 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10974 {
4fa24527 10975 if (!object_64bit)
d6ab8113
JB		 10976 code = BFD_RELOC_386_GOTPC;
10977 else
10978 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10979 }
7b81dfbb
AJ		 10980 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10981 && GOT_symbol
10982 && fixp->fx_addsy == GOT_symbol)
10983 {
10984 code = BFD_RELOC_X86_64_GOTPC64;
10985 }
252b5132 10986
add39d23
TS		 10987 rel = XNEW (arelent);
10988 rel->sym_ptr_ptr = XNEW (asymbol *);
49309057 10989 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10990
10991 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10992
3e73aa7c
JH		 10993 if (!use_rela_relocations)
10994 {
10995 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10996 vtable entry to be used in the relocation's section offset. */
10997 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10998 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10999#if defined (OBJ_COFF) && defined (TE_PE)
11000 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11001 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11002 else
11003#endif
c6682705 11004 rel->addend = 0;
3e73aa7c
JH		 11005 }
11006 /* Use the rela in 64bit mode. */
252b5132 11007 else
3e73aa7c 11008 {
862be3fb
L		 11009 if (disallow_64bit_reloc)
11010 switch (code)
11011 {
862be3fb
L		 11012 case BFD_RELOC_X86_64_DTPOFF64:
11013 case BFD_RELOC_X86_64_TPOFF64:
11014 case BFD_RELOC_64_PCREL:
11015 case BFD_RELOC_X86_64_GOTOFF64:
11016 case BFD_RELOC_X86_64_GOT64:
11017 case BFD_RELOC_X86_64_GOTPCREL64:
11018 case BFD_RELOC_X86_64_GOTPC64:
11019 case BFD_RELOC_X86_64_GOTPLT64:
11020 case BFD_RELOC_X86_64_PLTOFF64:
11021 as_bad_where (fixp->fx_file, fixp->fx_line,
11022 _("cannot represent relocation type %s in x32 mode"),
11023 bfd_get_reloc_code_name (code));
11024 break;
11025 default:
11026 break;
11027 }
11028
062cd5e7
AS		 11029 if (!fixp->fx_pcrel)
11030 rel->addend = fixp->fx_offset;
11031 else
11032 switch (code)
11033 {
11034 case BFD_RELOC_X86_64_PLT32:
11035 case BFD_RELOC_X86_64_GOT32:
11036 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 11037 case BFD_RELOC_X86_64_GOTPCRELX:
11038 case BFD_RELOC_X86_64_REX_GOTPCRELX:
bffbf940
JJ		 11039 case BFD_RELOC_X86_64_TLSGD:
11040 case BFD_RELOC_X86_64_TLSLD:
11041 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 11042 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11043 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 11044 rel->addend = fixp->fx_offset - fixp->fx_size;
11045 break;
11046 default:
11047 rel->addend = (section->vma
11048 - fixp->fx_size
11049 + fixp->fx_addnumber
11050 + md_pcrel_from (fixp));
11051 break;
11052 }
3e73aa7c
JH		 11053 }
11054
252b5132
RH		 11055 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11056 if (rel->howto == NULL)
11057 {
11058 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 11059 _("cannot represent relocation type %s"),
252b5132
RH		 11060 bfd_get_reloc_code_name (code));
11061 /* Set howto to a garbage value so that we can keep going. */
11062 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 11063 gas_assert (rel->howto != NULL);
252b5132
RH		 11064 }
11065
11066 return rel;
11067}
11068
ee86248c 11069#include "tc-i386-intel.c"
54cfded0 11070
a60de03c
JB		 11071void
11072tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 11073{
a60de03c
JB		 11074 int saved_naked_reg;
11075 char saved_register_dot;
54cfded0 11076
a60de03c
JB		 11077 saved_naked_reg = allow_naked_reg;
11078 allow_naked_reg = 1;
11079 saved_register_dot = register_chars['.'];
11080 register_chars['.'] = '.';
11081 allow_pseudo_reg = 1;
11082 expression_and_evaluate (exp);
11083 allow_pseudo_reg = 0;
11084 register_chars['.'] = saved_register_dot;
11085 allow_naked_reg = saved_naked_reg;
11086
e96d56a1 11087 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 11088 {
a60de03c
JB		 11089 if ((addressT) exp->X_add_number < i386_regtab_size)
11090 {
11091 exp->X_op = O_constant;
11092 exp->X_add_number = i386_regtab[exp->X_add_number]
11093 .dw2_regnum[flag_code >> 1];
11094 }
11095 else
11096 exp->X_op = O_illegal;
54cfded0 11097 }
54cfded0
AM		 11098}
11099
11100void
11101tc_x86_frame_initial_instructions (void)
11102{
a60de03c
JB		 11103 static unsigned int sp_regno[2];
11104
11105 if (!sp_regno[flag_code >> 1])
11106 {
11107 char *saved_input = input_line_pointer;
11108 char sp[][4] = {"esp", "rsp"};
11109 expressionS exp;
a4447b93 11110
a60de03c
JB		 11111 input_line_pointer = sp[flag_code >> 1];
11112 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 11113 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 11114 sp_regno[flag_code >> 1] = exp.X_add_number;
11115 input_line_pointer = saved_input;
11116 }
a4447b93 11117
61ff971f
L		 11118 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11119 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 11120}
d2b2c203 11121
d7921315
L		 11122int
11123x86_dwarf2_addr_size (void)
11124{
11125#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11126 if (x86_elf_abi == X86_64_X32_ABI)
11127 return 4;
11128#endif
11129 return bfd_arch_bits_per_address (stdoutput) / 8;
11130}
11131
d2b2c203
DJ		 11132int
11133i386_elf_section_type (const char *str, size_t len)
11134{
11135 if (flag_code == CODE_64BIT
11136 && len == sizeof ("unwind") - 1
11137 && strncmp (str, "unwind", 6) == 0)
11138 return SHT_X86_64_UNWIND;
11139
11140 return -1;
11141}
bb41ade5 11142
ad5fec3b
EB		 11143#ifdef TE_SOLARIS
11144void
11145i386_solaris_fix_up_eh_frame (segT sec)
11146{
11147 if (flag_code == CODE_64BIT)
11148 elf_section_type (sec) = SHT_X86_64_UNWIND;
11149}
11150#endif
11151
bb41ade5
AM		 11152#ifdef TE_PE
11153void
11154tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11155{
91d6fa6a 11156 expressionS exp;
bb41ade5 11157
91d6fa6a
NC		 11158 exp.X_op = O_secrel;
11159 exp.X_add_symbol = symbol;
11160 exp.X_add_number = 0;
11161 emit_expr (&exp, size);
bb41ade5
AM		 11162}
11163#endif
3b22753a
L		 11164
11165#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11166/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11167
01e1a5bc 11168bfd_vma
6d4af3c2 11169x86_64_section_letter (int letter, const char **ptr_msg)
3b22753a
L		 11170{
11171 if (flag_code == CODE_64BIT)
11172 {
11173 if (letter == 'l')
11174 return SHF_X86_64_LARGE;
11175
8f3bae45 11176 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 11177 }
3b22753a 11178 else
8f3bae45 11179 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 11180 return -1;
11181}
11182
01e1a5bc 11183bfd_vma
3b22753a
L		 11184x86_64_section_word (char *str, size_t len)
11185{
8620418b 11186 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 11187 return SHF_X86_64_LARGE;
11188
11189 return -1;
11190}
11191
11192static void
11193handle_large_common (int small ATTRIBUTE_UNUSED)
11194{
11195 if (flag_code != CODE_64BIT)
11196 {
11197 s_comm_internal (0, elf_common_parse);
11198 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11199 }
11200 else
11201 {
11202 static segT lbss_section;
11203 asection *saved_com_section_ptr = elf_com_section_ptr;
11204 asection *saved_bss_section = bss_section;
11205
11206 if (lbss_section == NULL)
11207 {
11208 flagword applicable;
11209 segT seg = now_seg;
11210 subsegT subseg = now_subseg;
11211
11212 /* The .lbss section is for local .largecomm symbols. */
11213 lbss_section = subseg_new (".lbss", 0);
11214 applicable = bfd_applicable_section_flags (stdoutput);
11215 bfd_set_section_flags (stdoutput, lbss_section,
11216 applicable & SEC_ALLOC);
11217 seg_info (lbss_section)->bss = 1;
11218
11219 subseg_set (seg, subseg);
11220 }
11221
11222 elf_com_section_ptr = &_bfd_elf_large_com_section;
11223 bss_section = lbss_section;
11224
11225 s_comm_internal (0, elf_common_parse);
11226
11227 elf_com_section_ptr = saved_com_section_ptr;
11228 bss_section = saved_bss_section;
11229 }
11230}
11231#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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