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* config/tc-i386.c (process_operands): Warn about "lea" segment
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
252b5132 1/* i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
5db1645b 3 2000, 2001, 2002
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
47926f60
KH		 26 Bugs & suggestions are completely welcome. This is free software.
27 Please help us make it better. */
252b5132 28
252b5132 29#include "as.h"
3882b010 30#include "safe-ctype.h"
252b5132 31#include "subsegs.h"
316e2c05 32#include "dwarf2dbg.h"
252b5132
RH		 33#include "opcode/i386.h"
34
252b5132
RH		 35#ifndef REGISTER_WARNINGS
36#define REGISTER_WARNINGS 1
37#endif
38
c3332e24 39#ifndef INFER_ADDR_PREFIX
eecb386c 40#define INFER_ADDR_PREFIX 1
c3332e24
AM		 41#endif
42
252b5132
RH		 43#ifndef SCALE1_WHEN_NO_INDEX
44/* Specifying a scale factor besides 1 when there is no index is
45 futile. eg. `mov (%ebx,2),%al' does exactly the same as
46 `mov (%ebx),%al'. To slavishly follow what the programmer
47 specified, set SCALE1_WHEN_NO_INDEX to 0. */
48#define SCALE1_WHEN_NO_INDEX 1
49#endif
50
29b0f896
AM		 51#ifdef BFD_ASSEMBLER
52#define RELOC_ENUM enum bfd_reloc_code_real
53#else
54#define RELOC_ENUM int
246fcdee 55#endif
29b0f896
AM		 56
57#ifndef DEFAULT_ARCH
58#define DEFAULT_ARCH "i386"
246fcdee 59#endif
252b5132 60
edde18a5
AM		 61#ifndef INLINE
62#if __GNUC__ >= 2
63#define INLINE __inline__
64#else
65#define INLINE
66#endif
67#endif
68
29b0f896
AM		 69static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
70static INLINE int fits_in_signed_byte PARAMS ((offsetT));
71static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
72static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
73static INLINE int fits_in_signed_word PARAMS ((offsetT));
74static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
75static INLINE int fits_in_signed_long PARAMS ((offsetT));
847f7ad4
AM		 76static int smallest_imm_type PARAMS ((offsetT));
77static offsetT offset_in_range PARAMS ((offsetT, int));
252b5132 78static int add_prefix PARAMS ((unsigned int));
3e73aa7c 79static void set_code_flag PARAMS ((int));
47926f60 80static void set_16bit_gcc_code_flag PARAMS ((int));
252b5132 81static void set_intel_syntax PARAMS ((int));
e413e4e9 82static void set_cpu_arch PARAMS ((int));
29b0f896
AM		 83static char *output_invalid PARAMS ((int c));
84static int i386_operand PARAMS ((char *operand_string));
85static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
86static const reg_entry *parse_register PARAMS ((char *reg_string,
87 char **end_op));
88static char *parse_insn PARAMS ((char *, char *));
89static char *parse_operands PARAMS ((char *, const char *));
90static void swap_operands PARAMS ((void));
91static void optimize_imm PARAMS ((void));
92static void optimize_disp PARAMS ((void));
93static int match_template PARAMS ((void));
94static int check_string PARAMS ((void));
95static int process_suffix PARAMS ((void));
96static int check_byte_reg PARAMS ((void));
97static int check_long_reg PARAMS ((void));
98static int check_qword_reg PARAMS ((void));
99static int check_word_reg PARAMS ((void));
100static int finalize_imm PARAMS ((void));
101static int process_operands PARAMS ((void));
102static const seg_entry *build_modrm_byte PARAMS ((void));
103static void output_insn PARAMS ((void));
104static void output_branch PARAMS ((void));
105static void output_jump PARAMS ((void));
106static void output_interseg_jump PARAMS ((void));
2bbd9c25
JJ		 107static void output_imm PARAMS ((fragS *insn_start_frag,
108 offsetT insn_start_off));
109static void output_disp PARAMS ((fragS *insn_start_frag,
110 offsetT insn_start_off));
29b0f896
AM		 111#ifndef I386COFF
112static void s_bss PARAMS ((int));
252b5132
RH		 113#endif
114
a847613f 115static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 116
252b5132 117/* 'md_assemble ()' gathers together information and puts it into a
47926f60 118 i386_insn. */
252b5132 119
520dc8e8
AM		 120union i386_op
121 {
122 expressionS *disps;
123 expressionS *imms;
124 const reg_entry *regs;
125 };
126
252b5132
RH		 127struct _i386_insn
128 {
47926f60 129 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 130 template tm;
131
132 /* SUFFIX holds the instruction mnemonic suffix if given.
133 (e.g. 'l' for 'movl') */
134 char suffix;
135
47926f60 136 /* OPERANDS gives the number of given operands. */
252b5132
RH		 137 unsigned int operands;
138
139 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
140 of given register, displacement, memory operands and immediate
47926f60 141 operands. */
252b5132
RH		 142 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
143
144 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 145 use OP[i] for the corresponding operand. */
252b5132
RH		 146 unsigned int types[MAX_OPERANDS];
147
520dc8e8
AM		 148 /* Displacement expression, immediate expression, or register for each
149 operand. */
150 union i386_op op[MAX_OPERANDS];
252b5132 151
3e73aa7c
JH		 152 /* Flags for operands. */
153 unsigned int flags[MAX_OPERANDS];
154#define Operand_PCrel 1
155
252b5132 156 /* Relocation type for operand */
f3c180ae 157 RELOC_ENUM reloc[MAX_OPERANDS];
252b5132 158
252b5132
RH		 159 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
160 the base index byte below. */
161 const reg_entry *base_reg;
162 const reg_entry *index_reg;
163 unsigned int log2_scale_factor;
164
165 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 166 explicit segment overrides are given. */
ce8a8b2f 167 const seg_entry *seg[2];
252b5132
RH		 168
169 /* PREFIX holds all the given prefix opcodes (usually null).
170 PREFIXES is the number of prefix opcodes. */
171 unsigned int prefixes;
172 unsigned char prefix[MAX_PREFIXES];
173
174 /* RM and SIB are the modrm byte and the sib byte where the
175 addressing modes of this insn are encoded. */
176
177 modrm_byte rm;
3e73aa7c 178 rex_byte rex;
252b5132
RH		 179 sib_byte sib;
180 };
181
182typedef struct _i386_insn i386_insn;
183
184/* List of chars besides those in app.c:symbol_chars that can start an
185 operand. Used to prevent the scrubber eating vital white-space. */
186#ifdef LEX_AT
200dbde8 187const char extra_symbol_chars[] = "*%-(@[";
252b5132 188#else
200dbde8 189const char extra_symbol_chars[] = "*%-([";
252b5132
RH		 190#endif
191
29b0f896
AM		 192#if (defined (TE_I386AIX) \
193 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
194 && !defined (TE_LINUX) \
195 && !defined (TE_FreeBSD) \
196 && !defined (TE_NetBSD)))
252b5132 197/* This array holds the chars that always start a comment. If the
ce8a8b2f 198 pre-processor is disabled, these aren't very useful. */
252b5132
RH		 199const char comment_chars[] = "#/";
200#define PREFIX_SEPARATOR '\\'
252b5132
RH		 201
202/* This array holds the chars that only start a comment at the beginning of
203 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 204 .line and .file directives will appear in the pre-processed output.
205 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 206 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 207 #NO_APP at the beginning of its output.
208 Also note that comments started like this one will always work if
252b5132 209 '/' isn't otherwise defined. */
252b5132 210const char line_comment_chars[] = "";
29b0f896 211
252b5132 212#else
29b0f896
AM		 213/* Putting '/' here makes it impossible to use the divide operator.
214 However, we need it for compatibility with SVR4 systems. */
215const char comment_chars[] = "#";
216#define PREFIX_SEPARATOR '/'
217
252b5132
RH		 218const char line_comment_chars[] = "/";
219#endif
220
63a0b638 221const char line_separator_chars[] = ";";
252b5132 222
ce8a8b2f
AM		 223/* Chars that can be used to separate mant from exp in floating point
224 nums. */
252b5132
RH		 225const char EXP_CHARS[] = "eE";
226
ce8a8b2f
AM		 227/* Chars that mean this number is a floating point constant
228 As in 0f12.456
229 or 0d1.2345e12. */
252b5132
RH		 230const char FLT_CHARS[] = "fFdDxX";
231
ce8a8b2f 232/* Tables for lexical analysis. */
252b5132
RH		 233static char mnemonic_chars[256];
234static char register_chars[256];
235static char operand_chars[256];
236static char identifier_chars[256];
237static char digit_chars[256];
238
ce8a8b2f 239/* Lexical macros. */
252b5132
RH		 240#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
241#define is_operand_char(x) (operand_chars[(unsigned char) x])
242#define is_register_char(x) (register_chars[(unsigned char) x])
243#define is_space_char(x) ((x) == ' ')
244#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
245#define is_digit_char(x) (digit_chars[(unsigned char) x])
246
ce8a8b2f 247/* All non-digit non-letter charcters that may occur in an operand. */
252b5132
RH		 248static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
249
250/* md_assemble() always leaves the strings it's passed unaltered. To
251 effect this we maintain a stack of saved characters that we've smashed
252 with '\0's (indicating end of strings for various sub-fields of the
47926f60 253 assembler instruction). */
252b5132 254static char save_stack[32];
ce8a8b2f 255static char *save_stack_p;
252b5132
RH		 256#define END_STRING_AND_SAVE(s) \
257 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
258#define RESTORE_END_STRING(s) \
259 do { *(s) = *--save_stack_p; } while (0)
260
47926f60 261/* The instruction we're assembling. */
252b5132
RH		 262static i386_insn i;
263
264/* Possible templates for current insn. */
265static const templates *current_templates;
266
47926f60 267/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
252b5132
RH		 268static expressionS disp_expressions[2], im_expressions[2];
269
47926f60
KH		 270/* Current operand we are working on. */
271static int this_operand;
252b5132 272
3e73aa7c
JH		 273/* We support four different modes. FLAG_CODE variable is used to distinguish
274 these. */
275
276enum flag_code {
277 CODE_32BIT,
278 CODE_16BIT,
279 CODE_64BIT };
f3c180ae 280#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 281
282static enum flag_code flag_code;
283static int use_rela_relocations = 0;
284
285/* The names used to print error messages. */
b77a7acd 286static const char *flag_code_names[] =
3e73aa7c
JH		 287 {
288 "32",
289 "16",
290 "64"
291 };
252b5132 292
47926f60
KH		 293/* 1 for intel syntax,
294 0 if att syntax. */
295static int intel_syntax = 0;
252b5132 296
47926f60
KH		 297/* 1 if register prefix % not required. */
298static int allow_naked_reg = 0;
252b5132 299
47926f60
KH		 300/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
301 leave, push, and pop instructions so that gcc has the same stack
302 frame as in 32 bit mode. */
303static char stackop_size = '\0';
eecb386c 304
47926f60
KH		 305/* Non-zero to quieten some warnings. */
306static int quiet_warnings = 0;
a38cf1db 307
47926f60
KH		 308/* CPU name. */
309static const char *cpu_arch_name = NULL;
a38cf1db 310
47926f60 311/* CPU feature flags. */
29b0f896 312static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 313
fddf5b5b
AM		 314/* If set, conditional jumps are not automatically promoted to handle
315 larger than a byte offset. */
316static unsigned int no_cond_jump_promotion = 0;
317
29b0f896
AM		 318/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
319symbolS *GOT_symbol;
320
252b5132 321/* Interface to relax_segment.
fddf5b5b
AM		 322 There are 3 major relax states for 386 jump insns because the
323 different types of jumps add different sizes to frags when we're
324 figuring out what sort of jump to choose to reach a given label. */
252b5132 325
47926f60 326/* Types. */
93c2a809
AM		 327#define UNCOND_JUMP 0
328#define COND_JUMP 1
329#define COND_JUMP86 2
fddf5b5b 330
47926f60 331/* Sizes. */
252b5132
RH		 332#define CODE16 1
333#define SMALL 0
29b0f896 334#define SMALL16 (SMALL | CODE16)
252b5132 335#define BIG 2
29b0f896 336#define BIG16 (BIG | CODE16)
252b5132
RH		 337
338#ifndef INLINE
339#ifdef __GNUC__
340#define INLINE __inline__
341#else
342#define INLINE
343#endif
344#endif
345
fddf5b5b
AM		 346#define ENCODE_RELAX_STATE(type, size) \
347 ((relax_substateT) (((type) << 2) | (size)))
348#define TYPE_FROM_RELAX_STATE(s) \
349 ((s) >> 2)
350#define DISP_SIZE_FROM_RELAX_STATE(s) \
351 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 352
353/* This table is used by relax_frag to promote short jumps to long
354 ones where necessary. SMALL (short) jumps may be promoted to BIG
355 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
356 don't allow a short jump in a 32 bit code segment to be promoted to
357 a 16 bit offset jump because it's slower (requires data size
358 prefix), and doesn't work, unless the destination is in the bottom
359 64k of the code segment (The top 16 bits of eip are zeroed). */
360
361const relax_typeS md_relax_table[] =
362{
24eab124
AM		 363 /* The fields are:
364 1) most positive reach of this state,
365 2) most negative reach of this state,
93c2a809 366 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 367 4) which index into the table to try if we can't fit into this one. */
252b5132 368
fddf5b5b 369 /* UNCOND_JUMP states. */
93c2a809
AM		 370 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
371 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
372 /* dword jmp adds 4 bytes to frag:
373 0 extra opcode bytes, 4 displacement bytes. */
252b5132 374 {0, 0, 4, 0},
93c2a809
AM		 375 /* word jmp adds 2 byte2 to frag:
376 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 377 {0, 0, 2, 0},
378
93c2a809
AM		 379 /* COND_JUMP states. */
380 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
381 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
382 /* dword conditionals adds 5 bytes to frag:
383 1 extra opcode byte, 4 displacement bytes. */
384 {0, 0, 5, 0},
fddf5b5b 385 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 386 1 extra opcode byte, 2 displacement bytes. */
387 {0, 0, 3, 0},
388
389 /* COND_JUMP86 states. */
390 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
391 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
392 /* dword conditionals adds 5 bytes to frag:
393 1 extra opcode byte, 4 displacement bytes. */
394 {0, 0, 5, 0},
395 /* word conditionals add 4 bytes to frag:
396 1 displacement byte and a 3 byte long branch insn. */
397 {0, 0, 4, 0}
252b5132
RH		 398};
399
e413e4e9
AM		 400static const arch_entry cpu_arch[] = {
401 {"i8086", Cpu086 },
402 {"i186", Cpu086|Cpu186 },
403 {"i286", Cpu086|Cpu186|Cpu286 },
404 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
405 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
406 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
407 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
408 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
409 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
a167610d 410 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2 },
3e73aa7c
JH		 411 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
412 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|Cpu3dnow },
a167610d 413 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|Cpu3dnow|CpuSSE|CpuSSE2 },
e413e4e9
AM		 414 {NULL, 0 }
415};
416
29b0f896
AM		 417const pseudo_typeS md_pseudo_table[] =
418{
419#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
420 {"align", s_align_bytes, 0},
421#else
422 {"align", s_align_ptwo, 0},
423#endif
424 {"arch", set_cpu_arch, 0},
425#ifndef I386COFF
426 {"bss", s_bss, 0},
427#endif
428 {"ffloat", float_cons, 'f'},
429 {"dfloat", float_cons, 'd'},
430 {"tfloat", float_cons, 'x'},
431 {"value", cons, 2},
432 {"noopt", s_ignore, 0},
433 {"optim", s_ignore, 0},
434 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
435 {"code16", set_code_flag, CODE_16BIT},
436 {"code32", set_code_flag, CODE_32BIT},
437 {"code64", set_code_flag, CODE_64BIT},
438 {"intel_syntax", set_intel_syntax, 1},
439 {"att_syntax", set_intel_syntax, 0},
c6682705 440 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
29b0f896
AM		 441 {"loc", dwarf2_directive_loc, 0},
442 {0, 0, 0}
443};
444
445/* For interface with expression (). */
446extern char *input_line_pointer;
447
448/* Hash table for instruction mnemonic lookup. */
449static struct hash_control *op_hash;
450
451/* Hash table for register lookup. */
452static struct hash_control *reg_hash;
453\f
252b5132
RH		 454void
455i386_align_code (fragP, count)
456 fragS *fragP;
457 int count;
458{
ce8a8b2f
AM		 459 /* Various efficient no-op patterns for aligning code labels.
460 Note: Don't try to assemble the instructions in the comments.
461 0L and 0w are not legal. */
252b5132
RH		 462 static const char f32_1[] =
463 {0x90}; /* nop */
464 static const char f32_2[] =
465 {0x89,0xf6}; /* movl %esi,%esi */
466 static const char f32_3[] =
467 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
468 static const char f32_4[] =
469 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
470 static const char f32_5[] =
471 {0x90, /* nop */
472 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
473 static const char f32_6[] =
474 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
475 static const char f32_7[] =
476 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
477 static const char f32_8[] =
478 {0x90, /* nop */
479 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
480 static const char f32_9[] =
481 {0x89,0xf6, /* movl %esi,%esi */
482 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
483 static const char f32_10[] =
484 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
485 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
486 static const char f32_11[] =
487 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
488 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
489 static const char f32_12[] =
490 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
491 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
492 static const char f32_13[] =
493 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
494 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
495 static const char f32_14[] =
496 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
497 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
498 static const char f32_15[] =
499 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
500 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 501 static const char f16_3[] =
502 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 503 static const char f16_4[] =
504 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
505 static const char f16_5[] =
506 {0x90, /* nop */
507 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
508 static const char f16_6[] =
509 {0x89,0xf6, /* mov %si,%si */
510 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
511 static const char f16_7[] =
512 {0x8d,0x74,0x00, /* lea 0(%si),%si */
513 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
514 static const char f16_8[] =
515 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
516 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
517 static const char *const f32_patt[] = {
518 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
519 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
520 };
521 static const char *const f16_patt[] = {
c3332e24 522 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 523 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
524 };
525
33fef721
JH		 526 if (count <= 0 || count > 15)
527 return;
3e73aa7c 528
33fef721
JH		 529 /* The recommended way to pad 64bit code is to use NOPs preceded by
530 maximally four 0x66 prefixes. Balance the size of nops. */
531 if (flag_code == CODE_64BIT)
252b5132 532 {
33fef721
JH		 533 int i;
534 int nnops = (count + 3) / 4;
535 int len = count / nnops;
536 int remains = count - nnops * len;
537 int pos = 0;
538
539 for (i = 0; i < remains; i++)
252b5132 540 {
33fef721
JH		 541 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
542 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
543 pos += len + 1;
544 }
545 for (; i < nnops; i++)
546 {
547 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
548 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
549 pos += len;
252b5132 550 }
252b5132 551 }
33fef721
JH		 552 else
553 if (flag_code == CODE_16BIT)
554 {
555 memcpy (fragP->fr_literal + fragP->fr_fix,
556 f16_patt[count - 1], count);
557 if (count > 8)
558 /* Adjust jump offset. */
559 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
560 }
561 else
562 memcpy (fragP->fr_literal + fragP->fr_fix,
563 f32_patt[count - 1], count);
564 fragP->fr_var = count;
252b5132
RH		 565}
566
252b5132
RH		 567static INLINE unsigned int
568mode_from_disp_size (t)
569 unsigned int t;
570{
3e73aa7c 571 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 572}
573
574static INLINE int
575fits_in_signed_byte (num)
847f7ad4 576 offsetT num;
252b5132
RH		 577{
578 return (num >= -128) && (num <= 127);
47926f60 579}
252b5132
RH		 580
581static INLINE int
582fits_in_unsigned_byte (num)
847f7ad4 583 offsetT num;
252b5132
RH		 584{
585 return (num & 0xff) == num;
47926f60 586}
252b5132
RH		 587
588static INLINE int
589fits_in_unsigned_word (num)
847f7ad4 590 offsetT num;
252b5132
RH		 591{
592 return (num & 0xffff) == num;
47926f60 593}
252b5132
RH		 594
595static INLINE int
596fits_in_signed_word (num)
847f7ad4 597 offsetT num;
252b5132
RH		 598{
599 return (-32768 <= num) && (num <= 32767);
47926f60 600}
3e73aa7c
JH		 601static INLINE int
602fits_in_signed_long (num)
603 offsetT num ATTRIBUTE_UNUSED;
604{
605#ifndef BFD64
606 return 1;
607#else
608 return (!(((offsetT) -1 << 31) & num)
609 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
610#endif
611} /* fits_in_signed_long() */
612static INLINE int
613fits_in_unsigned_long (num)
614 offsetT num ATTRIBUTE_UNUSED;
615{
616#ifndef BFD64
617 return 1;
618#else
619 return (num & (((offsetT) 2 << 31) - 1)) == num;
620#endif
621} /* fits_in_unsigned_long() */
252b5132
RH		 622
623static int
624smallest_imm_type (num)
847f7ad4 625 offsetT num;
252b5132 626{
a847613f 627 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 628 {
629 /* This code is disabled on the 486 because all the Imm1 forms
630 in the opcode table are slower on the i486. They're the
631 versions with the implicitly specified single-position
632 displacement, which has another syntax if you really want to
633 use that form. */
634 if (num == 1)
3e73aa7c 635 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 636 }
252b5132 637 return (fits_in_signed_byte (num)
3e73aa7c 638 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 639 : fits_in_unsigned_byte (num)
3e73aa7c 640 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 641 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 642 ? (Imm16 | Imm32 | Imm32S | Imm64)
643 : fits_in_signed_long (num)
644 ? (Imm32 | Imm32S | Imm64)
645 : fits_in_unsigned_long (num)
646 ? (Imm32 | Imm64)
647 : Imm64);
47926f60 648}
252b5132 649
847f7ad4
AM		 650static offsetT
651offset_in_range (val, size)
652 offsetT val;
653 int size;
654{
508866be 655 addressT mask;
ba2adb93 656
847f7ad4
AM		 657 switch (size)
658 {
508866be
L		 659 case 1: mask = ((addressT) 1 << 8) - 1; break;
660 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 661 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 662#ifdef BFD64
663 case 8: mask = ((addressT) 2 << 63) - 1; break;
664#endif
47926f60 665 default: abort ();
847f7ad4
AM		 666 }
667
ba2adb93 668 /* If BFD64, sign extend val. */
3e73aa7c
JH		 669 if (!use_rela_relocations)
670 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
671 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 672
47926f60 673 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 674 {
675 char buf1[40], buf2[40];
676
677 sprint_value (buf1, val);
678 sprint_value (buf2, val & mask);
679 as_warn (_("%s shortened to %s"), buf1, buf2);
680 }
681 return val & mask;
682}
683
252b5132
RH		 684/* Returns 0 if attempting to add a prefix where one from the same
685 class already exists, 1 if non rep/repne added, 2 if rep/repne
686 added. */
687static int
688add_prefix (prefix)
689 unsigned int prefix;
690{
691 int ret = 1;
692 int q;
693
29b0f896
AM		 694 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
695 && flag_code == CODE_64BIT)
3e73aa7c
JH		 696 q = REX_PREFIX;
697 else
698 switch (prefix)
699 {
700 default:
701 abort ();
702
703 case CS_PREFIX_OPCODE:
704 case DS_PREFIX_OPCODE:
705 case ES_PREFIX_OPCODE:
706 case FS_PREFIX_OPCODE:
707 case GS_PREFIX_OPCODE:
708 case SS_PREFIX_OPCODE:
709 q = SEG_PREFIX;
710 break;
252b5132 711
3e73aa7c
JH		 712 case REPNE_PREFIX_OPCODE:
713 case REPE_PREFIX_OPCODE:
714 ret = 2;
715 /* fall thru */
716 case LOCK_PREFIX_OPCODE:
717 q = LOCKREP_PREFIX;
718 break;
252b5132 719
3e73aa7c
JH		 720 case FWAIT_OPCODE:
721 q = WAIT_PREFIX;
722 break;
252b5132 723
3e73aa7c
JH		 724 case ADDR_PREFIX_OPCODE:
725 q = ADDR_PREFIX;
726 break;
252b5132 727
3e73aa7c
JH		 728 case DATA_PREFIX_OPCODE:
729 q = DATA_PREFIX;
730 break;
731 }
252b5132 732
29b0f896 733 if (i.prefix[q] != 0)
252b5132
RH		 734 {
735 as_bad (_("same type of prefix used twice"));
736 return 0;
737 }
738
739 i.prefixes += 1;
740 i.prefix[q] = prefix;
741 return ret;
742}
743
744static void
3e73aa7c 745set_code_flag (value)
e5cb08ac 746 int value;
eecb386c 747{
3e73aa7c
JH		 748 flag_code = value;
749 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
750 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
751 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
752 {
753 as_bad (_("64bit mode not supported on this CPU."));
754 }
755 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
756 {
757 as_bad (_("32bit mode not supported on this CPU."));
758 }
eecb386c
AM		 759 stackop_size = '\0';
760}
761
762static void
3e73aa7c
JH		 763set_16bit_gcc_code_flag (new_code_flag)
764 int new_code_flag;
252b5132 765{
3e73aa7c
JH		 766 flag_code = new_code_flag;
767 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
768 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
769 stackop_size = 'l';
252b5132
RH		 770}
771
772static void
773set_intel_syntax (syntax_flag)
eecb386c 774 int syntax_flag;
252b5132
RH		 775{
776 /* Find out if register prefixing is specified. */
777 int ask_naked_reg = 0;
778
779 SKIP_WHITESPACE ();
29b0f896 780 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 781 {
782 char *string = input_line_pointer;
783 int e = get_symbol_end ();
784
47926f60 785 if (strcmp (string, "prefix") == 0)
252b5132 786 ask_naked_reg = 1;
47926f60 787 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 788 ask_naked_reg = -1;
789 else
d0b47220 790 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 791 *input_line_pointer = e;
792 }
793 demand_empty_rest_of_line ();
c3332e24 794
252b5132
RH		 795 intel_syntax = syntax_flag;
796
797 if (ask_naked_reg == 0)
798 {
799#ifdef BFD_ASSEMBLER
800 allow_naked_reg = (intel_syntax
24eab124 801 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132 802#else
47926f60
KH		 803 /* Conservative default. */
804 allow_naked_reg = 0;
252b5132
RH		 805#endif
806 }
807 else
808 allow_naked_reg = (ask_naked_reg < 0);
809}
810
e413e4e9
AM		 811static void
812set_cpu_arch (dummy)
47926f60 813 int dummy ATTRIBUTE_UNUSED;
e413e4e9 814{
47926f60 815 SKIP_WHITESPACE ();
e413e4e9 816
29b0f896 817 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 818 {
819 char *string = input_line_pointer;
820 int e = get_symbol_end ();
821 int i;
822
823 for (i = 0; cpu_arch[i].name; i++)
824 {
825 if (strcmp (string, cpu_arch[i].name) == 0)
826 {
827 cpu_arch_name = cpu_arch[i].name;
fddf5b5b
AM		 828 cpu_arch_flags = (cpu_arch[i].flags
829 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
e413e4e9
AM		 830 break;
831 }
832 }
833 if (!cpu_arch[i].name)
834 as_bad (_("no such architecture: `%s'"), string);
835
836 *input_line_pointer = e;
837 }
838 else
839 as_bad (_("missing cpu architecture"));
840
fddf5b5b
AM		 841 no_cond_jump_promotion = 0;
842 if (*input_line_pointer == ','
29b0f896 843 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 844 {
845 char *string = ++input_line_pointer;
846 int e = get_symbol_end ();
847
848 if (strcmp (string, "nojumps") == 0)
849 no_cond_jump_promotion = 1;
850 else if (strcmp (string, "jumps") == 0)
851 ;
852 else
853 as_bad (_("no such architecture modifier: `%s'"), string);
854
855 *input_line_pointer = e;
856 }
857
e413e4e9
AM		 858 demand_empty_rest_of_line ();
859}
860
b9d79e03
JH		 861#ifdef BFD_ASSEMBLER
862unsigned long
863i386_mach ()
864{
865 if (!strcmp (default_arch, "x86_64"))
866 return bfd_mach_x86_64;
867 else if (!strcmp (default_arch, "i386"))
868 return bfd_mach_i386_i386;
869 else
870 as_fatal (_("Unknown architecture"));
871}
872#endif
873\f
252b5132
RH		 874void
875md_begin ()
876{
877 const char *hash_err;
878
47926f60 879 /* Initialize op_hash hash table. */
252b5132
RH		 880 op_hash = hash_new ();
881
882 {
29b0f896
AM		 883 const template *optab;
884 templates *core_optab;
252b5132 885
47926f60
KH		 886 /* Setup for loop. */
887 optab = i386_optab;
252b5132
RH		 888 core_optab = (templates *) xmalloc (sizeof (templates));
889 core_optab->start = optab;
890
891 while (1)
892 {
893 ++optab;
894 if (optab->name == NULL
895 || strcmp (optab->name, (optab - 1)->name) != 0)
896 {
897 /* different name --> ship out current template list;
47926f60 898 add to hash table; & begin anew. */
252b5132
RH		 899 core_optab->end = optab;
900 hash_err = hash_insert (op_hash,
901 (optab - 1)->name,
902 (PTR) core_optab);
903 if (hash_err)
904 {
252b5132
RH		 905 as_fatal (_("Internal Error: Can't hash %s: %s"),
906 (optab - 1)->name,
907 hash_err);
908 }
909 if (optab->name == NULL)
910 break;
911 core_optab = (templates *) xmalloc (sizeof (templates));
912 core_optab->start = optab;
913 }
914 }
915 }
916
47926f60 917 /* Initialize reg_hash hash table. */
252b5132
RH		 918 reg_hash = hash_new ();
919 {
29b0f896 920 const reg_entry *regtab;
252b5132
RH		 921
922 for (regtab = i386_regtab;
923 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
924 regtab++)
925 {
926 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
927 if (hash_err)
3e73aa7c
JH		 928 as_fatal (_("Internal Error: Can't hash %s: %s"),
929 regtab->reg_name,
930 hash_err);
252b5132
RH		 931 }
932 }
933
47926f60 934 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 935 {
29b0f896
AM		 936 int c;
937 char *p;
252b5132
RH		 938
939 for (c = 0; c < 256; c++)
940 {
3882b010 941 if (ISDIGIT (c))
252b5132
RH		 942 {
943 digit_chars[c] = c;
944 mnemonic_chars[c] = c;
945 register_chars[c] = c;
946 operand_chars[c] = c;
947 }
3882b010 948 else if (ISLOWER (c))
252b5132
RH		 949 {
950 mnemonic_chars[c] = c;
951 register_chars[c] = c;
952 operand_chars[c] = c;
953 }
3882b010 954 else if (ISUPPER (c))
252b5132 955 {
3882b010 956 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 957 register_chars[c] = mnemonic_chars[c];
958 operand_chars[c] = c;
959 }
960
3882b010 961 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 962 identifier_chars[c] = c;
963 else if (c >= 128)
964 {
965 identifier_chars[c] = c;
966 operand_chars[c] = c;
967 }
968 }
969
970#ifdef LEX_AT
971 identifier_chars['@'] = '@';
972#endif
252b5132
RH		 973 digit_chars['-'] = '-';
974 identifier_chars['_'] = '_';
975 identifier_chars['.'] = '.';
976
977 for (p = operand_special_chars; *p != '\0'; p++)
978 operand_chars[(unsigned char) *p] = *p;
979 }
980
981#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
982 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
983 {
984 record_alignment (text_section, 2);
985 record_alignment (data_section, 2);
986 record_alignment (bss_section, 2);
987 }
988#endif
989}
990
991void
992i386_print_statistics (file)
993 FILE *file;
994{
995 hash_print_statistics (file, "i386 opcode", op_hash);
996 hash_print_statistics (file, "i386 register", reg_hash);
997}
998\f
252b5132
RH		 999#ifdef DEBUG386
1000
ce8a8b2f 1001/* Debugging routines for md_assemble. */
252b5132
RH		 1002static void pi PARAMS ((char *, i386_insn *));
1003static void pte PARAMS ((template *));
1004static void pt PARAMS ((unsigned int));
1005static void pe PARAMS ((expressionS *));
1006static void ps PARAMS ((symbolS *));
1007
1008static void
1009pi (line, x)
1010 char *line;
1011 i386_insn *x;
1012{
09f131f2 1013 unsigned int i;
252b5132
RH		 1014
1015 fprintf (stdout, "%s: template ", line);
1016 pte (&x->tm);
09f131f2
JH		 1017 fprintf (stdout, " address: base %s index %s scale %x\n",
1018 x->base_reg ? x->base_reg->reg_name : "none",
1019 x->index_reg ? x->index_reg->reg_name : "none",
1020 x->log2_scale_factor);
1021 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1022 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1023 fprintf (stdout, " sib: base %x index %x scale %x\n",
1024 x->sib.base, x->sib.index, x->sib.scale);
1025 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
29b0f896
AM		 1026 (x->rex & REX_MODE64) != 0,
1027 (x->rex & REX_EXTX) != 0,
1028 (x->rex & REX_EXTY) != 0,
1029 (x->rex & REX_EXTZ) != 0);
252b5132
RH		 1030 for (i = 0; i < x->operands; i++)
1031 {
1032 fprintf (stdout, " #%d: ", i + 1);
1033 pt (x->types[i]);
1034 fprintf (stdout, "\n");
1035 if (x->types[i]
3f4438ab 1036 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1037 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1038 if (x->types[i] & Imm)
520dc8e8 1039 pe (x->op[i].imms);
252b5132 1040 if (x->types[i] & Disp)
520dc8e8 1041 pe (x->op[i].disps);
252b5132
RH		 1042 }
1043}
1044
1045static void
1046pte (t)
1047 template *t;
1048{
09f131f2 1049 unsigned int i;
252b5132 1050 fprintf (stdout, " %d operands ", t->operands);
47926f60 1051 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1052 if (t->extension_opcode != None)
1053 fprintf (stdout, "ext %x ", t->extension_opcode);
1054 if (t->opcode_modifier & D)
1055 fprintf (stdout, "D");
1056 if (t->opcode_modifier & W)
1057 fprintf (stdout, "W");
1058 fprintf (stdout, "\n");
1059 for (i = 0; i < t->operands; i++)
1060 {
1061 fprintf (stdout, " #%d type ", i + 1);
1062 pt (t->operand_types[i]);
1063 fprintf (stdout, "\n");
1064 }
1065}
1066
1067static void
1068pe (e)
1069 expressionS *e;
1070{
24eab124 1071 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1072 fprintf (stdout, " add_number %ld (%lx)\n",
1073 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1074 if (e->X_add_symbol)
1075 {
1076 fprintf (stdout, " add_symbol ");
1077 ps (e->X_add_symbol);
1078 fprintf (stdout, "\n");
1079 }
1080 if (e->X_op_symbol)
1081 {
1082 fprintf (stdout, " op_symbol ");
1083 ps (e->X_op_symbol);
1084 fprintf (stdout, "\n");
1085 }
1086}
1087
1088static void
1089ps (s)
1090 symbolS *s;
1091{
1092 fprintf (stdout, "%s type %s%s",
1093 S_GET_NAME (s),
1094 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1095 segment_name (S_GET_SEGMENT (s)));
1096}
1097
1098struct type_name
1099 {
1100 unsigned int mask;
1101 char *tname;
1102 }
1103
29b0f896 1104static const type_names[] =
252b5132
RH		 1105{
1106 { Reg8, "r8" },
1107 { Reg16, "r16" },
1108 { Reg32, "r32" },
09f131f2 1109 { Reg64, "r64" },
252b5132
RH		 1110 { Imm8, "i8" },
1111 { Imm8S, "i8s" },
1112 { Imm16, "i16" },
1113 { Imm32, "i32" },
09f131f2
JH		 1114 { Imm32S, "i32s" },
1115 { Imm64, "i64" },
252b5132
RH		 1116 { Imm1, "i1" },
1117 { BaseIndex, "BaseIndex" },
1118 { Disp8, "d8" },
1119 { Disp16, "d16" },
1120 { Disp32, "d32" },
09f131f2
JH		 1121 { Disp32S, "d32s" },
1122 { Disp64, "d64" },
252b5132
RH		 1123 { InOutPortReg, "InOutPortReg" },
1124 { ShiftCount, "ShiftCount" },
1125 { Control, "control reg" },
1126 { Test, "test reg" },
1127 { Debug, "debug reg" },
1128 { FloatReg, "FReg" },
1129 { FloatAcc, "FAcc" },
1130 { SReg2, "SReg2" },
1131 { SReg3, "SReg3" },
1132 { Acc, "Acc" },
1133 { JumpAbsolute, "Jump Absolute" },
1134 { RegMMX, "rMMX" },
3f4438ab 1135 { RegXMM, "rXMM" },
252b5132
RH		 1136 { EsSeg, "es" },
1137 { 0, "" }
1138};
1139
1140static void
1141pt (t)
1142 unsigned int t;
1143{
29b0f896 1144 const struct type_name *ty;
252b5132 1145
09f131f2
JH		 1146 for (ty = type_names; ty->mask; ty++)
1147 if (t & ty->mask)
1148 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1149 fflush (stdout);
1150}
1151
1152#endif /* DEBUG386 */
1153\f
252b5132 1154#ifdef BFD_ASSEMBLER
29b0f896
AM		 1155static bfd_reloc_code_real_type reloc
1156 PARAMS ((int, int, int, bfd_reloc_code_real_type));
252b5132
RH		 1157
1158static bfd_reloc_code_real_type
3e73aa7c 1159reloc (size, pcrel, sign, other)
252b5132
RH		 1160 int size;
1161 int pcrel;
3e73aa7c 1162 int sign;
252b5132
RH		 1163 bfd_reloc_code_real_type other;
1164{
47926f60
KH		 1165 if (other != NO_RELOC)
1166 return other;
252b5132
RH		 1167
1168 if (pcrel)
1169 {
3e73aa7c 1170 if (!sign)
e5cb08ac 1171 as_bad (_("There are no unsigned pc-relative relocations"));
252b5132
RH		 1172 switch (size)
1173 {
1174 case 1: return BFD_RELOC_8_PCREL;
1175 case 2: return BFD_RELOC_16_PCREL;
1176 case 4: return BFD_RELOC_32_PCREL;
1177 }
d0b47220 1178 as_bad (_("can not do %d byte pc-relative relocation"), size);
252b5132
RH		 1179 }
1180 else
1181 {
3e73aa7c 1182 if (sign)
e5cb08ac 1183 switch (size)
3e73aa7c
JH		 1184 {
1185 case 4: return BFD_RELOC_X86_64_32S;
1186 }
1187 else
1188 switch (size)
1189 {
1190 case 1: return BFD_RELOC_8;
1191 case 2: return BFD_RELOC_16;
1192 case 4: return BFD_RELOC_32;
1193 case 8: return BFD_RELOC_64;
1194 }
1195 as_bad (_("can not do %s %d byte relocation"),
1196 sign ? "signed" : "unsigned", size);
252b5132
RH		 1197 }
1198
bfb32b52 1199 abort ();
252b5132
RH		 1200 return BFD_RELOC_NONE;
1201}
1202
47926f60
KH		 1203/* Here we decide which fixups can be adjusted to make them relative to
1204 the beginning of the section instead of the symbol. Basically we need
1205 to make sure that the dynamic relocations are done correctly, so in
1206 some cases we force the original symbol to be used. */
1207
252b5132 1208int
c0c949c7 1209tc_i386_fix_adjustable (fixP)
31312f95 1210 fixS *fixP ATTRIBUTE_UNUSED;
252b5132 1211{
6d249963 1212#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
31312f95
AM		 1213 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
1214 return 1;
1215
a161fe53
AM		 1216 /* Don't adjust pc-relative references to merge sections in 64-bit
1217 mode. */
1218 if (use_rela_relocations
1219 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1220 && fixP->fx_pcrel)
252b5132 1221 return 0;
31312f95 1222
ce8a8b2f 1223 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1224 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1225 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1226 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1227 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1228 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1229 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1230 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1231 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1232 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1233 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1234 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3e73aa7c
JH		 1235 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1236 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1237 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
252b5132
RH		 1238 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1239 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1240 return 0;
31312f95 1241#endif
252b5132
RH		 1242 return 1;
1243}
1244#else
ec56dfb4 1245#define reloc(SIZE,PCREL,SIGN,OTHER) 0
c6682705 1246#define BFD_RELOC_8 0
ec56dfb4
L		 1247#define BFD_RELOC_16 0
1248#define BFD_RELOC_32 0
c6682705 1249#define BFD_RELOC_8_PCREL 0
ec56dfb4
L		 1250#define BFD_RELOC_16_PCREL 0
1251#define BFD_RELOC_32_PCREL 0
1252#define BFD_RELOC_386_PLT32 0
1253#define BFD_RELOC_386_GOT32 0
1254#define BFD_RELOC_386_GOTOFF 0
13ae64f3
JJ		 1255#define BFD_RELOC_386_TLS_GD 0
1256#define BFD_RELOC_386_TLS_LDM 0
1257#define BFD_RELOC_386_TLS_LDO_32 0
1258#define BFD_RELOC_386_TLS_IE_32 0
37e55690
JJ		 1259#define BFD_RELOC_386_TLS_IE 0
1260#define BFD_RELOC_386_TLS_GOTIE 0
13ae64f3
JJ		 1261#define BFD_RELOC_386_TLS_LE_32 0
1262#define BFD_RELOC_386_TLS_LE 0
ec56dfb4
L		 1263#define BFD_RELOC_X86_64_PLT32 0
1264#define BFD_RELOC_X86_64_GOT32 0
1265#define BFD_RELOC_X86_64_GOTPCREL 0
252b5132
RH		 1266#endif
1267
29b0f896 1268static int intel_float_operand PARAMS ((const char *mnemonic));
b4cac588
AM		 1269
1270static int
252b5132 1271intel_float_operand (mnemonic)
29b0f896 1272 const char *mnemonic;
252b5132 1273{
47926f60 1274 if (mnemonic[0] == 'f' && mnemonic[1] == 'i')
cc5ca5ce 1275 return 2;
252b5132
RH		 1276
1277 if (mnemonic[0] == 'f')
1278 return 1;
1279
1280 return 0;
1281}
1282
1283/* This is the guts of the machine-dependent assembler. LINE points to a
1284 machine dependent instruction. This function is supposed to emit
1285 the frags/bytes it assembles to. */
1286
1287void
1288md_assemble (line)
1289 char *line;
1290{
252b5132 1291 int j;
252b5132
RH		 1292 char mnemonic[MAX_MNEM_SIZE];
1293
47926f60 1294 /* Initialize globals. */
252b5132
RH		 1295 memset (&i, '\0', sizeof (i));
1296 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1297 i.reloc[j] = NO_RELOC;
252b5132
RH		 1298 memset (disp_expressions, '\0', sizeof (disp_expressions));
1299 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1300 save_stack_p = save_stack;
252b5132
RH		 1301
1302 /* First parse an instruction mnemonic & call i386_operand for the operands.
1303 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1304 start of a (possibly prefixed) mnemonic. */
252b5132 1305
29b0f896
AM		 1306 line = parse_insn (line, mnemonic);
1307 if (line == NULL)
1308 return;
252b5132 1309
29b0f896
AM		 1310 line = parse_operands (line, mnemonic);
1311 if (line == NULL)
1312 return;
252b5132 1313
29b0f896
AM		 1314 /* Now we've parsed the mnemonic into a set of templates, and have the
1315 operands at hand. */
1316
1317 /* All intel opcodes have reversed operands except for "bound" and
1318 "enter". We also don't reverse intersegment "jmp" and "call"
1319 instructions with 2 immediate operands so that the immediate segment
1320 precedes the offset, as it does when in AT&T mode. "enter" and the
1321 intersegment "jmp" and "call" instructions are the only ones that
1322 have two immediate operands. */
1323 if (intel_syntax && i.operands > 1
1324 && (strcmp (mnemonic, "bound") != 0)
1325 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1326 swap_operands ();
1327
1328 if (i.imm_operands)
1329 optimize_imm ();
1330
1331 if (i.disp_operands)
1332 optimize_disp ();
1333
1334 /* Next, we find a template that matches the given insn,
1335 making sure the overlap of the given operands types is consistent
1336 with the template operand types. */
252b5132 1337
29b0f896
AM		 1338 if (!match_template ())
1339 return;
252b5132 1340
cd61ebfe
AM		 1341 if (intel_syntax)
1342 {
1343 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1344 if (SYSV386_COMPAT
1345 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1346 i.tm.base_opcode ^= FloatR;
1347
1348 /* Zap movzx and movsx suffix. The suffix may have been set from
1349 "word ptr" or "byte ptr" on the source operand, but we'll use
1350 the suffix later to choose the destination register. */
1351 if ((i.tm.base_opcode & ~9) == 0x0fb6)
1352 i.suffix = 0;
1353 }
24eab124 1354
29b0f896
AM		 1355 if (i.tm.opcode_modifier & FWait)
1356 if (!add_prefix (FWAIT_OPCODE))
1357 return;
252b5132 1358
29b0f896
AM		 1359 /* Check string instruction segment overrides. */
1360 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1361 {
1362 if (!check_string ())
5dd0794d 1363 return;
29b0f896 1364 }
5dd0794d 1365
29b0f896
AM		 1366 if (!process_suffix ())
1367 return;
e413e4e9 1368
29b0f896
AM		 1369 /* Make still unresolved immediate matches conform to size of immediate
1370 given in i.suffix. */
1371 if (!finalize_imm ())
1372 return;
252b5132 1373
29b0f896
AM		 1374 if (i.types[0] & Imm1)
1375 i.imm_operands = 0; /* kludge for shift insns. */
1376 if (i.types[0] & ImplicitRegister)
1377 i.reg_operands--;
1378 if (i.types[1] & ImplicitRegister)
1379 i.reg_operands--;
1380 if (i.types[2] & ImplicitRegister)
1381 i.reg_operands--;
252b5132 1382
29b0f896
AM		 1383 if (i.tm.opcode_modifier & ImmExt)
1384 {
1385 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1386 opcode suffix which is coded in the same place as an 8-bit
1387 immediate field would be. Here we fake an 8-bit immediate
1388 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1389
29b0f896 1390 expressionS *exp;
252b5132 1391
29b0f896 1392 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1393
29b0f896
AM		 1394 exp = &im_expressions[i.imm_operands++];
1395 i.op[i.operands].imms = exp;
1396 i.types[i.operands++] = Imm8;
1397 exp->X_op = O_constant;
1398 exp->X_add_number = i.tm.extension_opcode;
1399 i.tm.extension_opcode = None;
1400 }
252b5132 1401
29b0f896
AM		 1402 /* For insns with operands there are more diddles to do to the opcode. */
1403 if (i.operands)
1404 {
1405 if (!process_operands ())
1406 return;
1407 }
1408 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1409 {
1410 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1411 as_warn (_("translating to `%sp'"), i.tm.name);
1412 }
252b5132 1413
29b0f896
AM		 1414 /* Handle conversion of 'int $3' --> special int3 insn. */
1415 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1416 {
1417 i.tm.base_opcode = INT3_OPCODE;
1418 i.imm_operands = 0;
1419 }
252b5132 1420
29b0f896
AM		 1421 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1422 && i.op[0].disps->X_op == O_constant)
1423 {
1424 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1425 the absolute address given by the constant. Since ix86 jumps and
1426 calls are pc relative, we need to generate a reloc. */
1427 i.op[0].disps->X_add_symbol = &abs_symbol;
1428 i.op[0].disps->X_op = O_symbol;
1429 }
252b5132 1430
29b0f896
AM		 1431 if ((i.tm.opcode_modifier & Rex64) != 0)
1432 i.rex |= REX_MODE64;
252b5132 1433
29b0f896
AM		 1434 /* For 8 bit registers we need an empty rex prefix. Also if the
1435 instruction already has a prefix, we need to convert old
1436 registers to new ones. */
773f551c 1437
29b0f896
AM		 1438 if (((i.types[0] & Reg8) != 0
1439 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1440 || ((i.types[1] & Reg8) != 0
1441 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1442 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1443 && i.rex != 0))
1444 {
1445 int x;
726c5dcd 1446
29b0f896
AM		 1447 i.rex |= REX_OPCODE;
1448 for (x = 0; x < 2; x++)
1449 {
1450 /* Look for 8 bit operand that uses old registers. */
1451 if ((i.types[x] & Reg8) != 0
1452 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1453 {
29b0f896
AM		 1454 /* In case it is "hi" register, give up. */
1455 if (i.op[x].regs->reg_num > 3)
1456 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix.\n"),
1457 i.op[x].regs->reg_name);
773f551c 1458
29b0f896
AM		 1459 /* Otherwise it is equivalent to the extended register.
1460 Since the encoding doesn't change this is merely
1461 cosmetic cleanup for debug output. */
1462
1463 i.op[x].regs = i.op[x].regs + 8;
773f551c 1464 }
29b0f896
AM		 1465 }
1466 }
773f551c 1467
29b0f896
AM		 1468 if (i.rex != 0)
1469 add_prefix (REX_OPCODE | i.rex);
1470
1471 /* We are ready to output the insn. */
1472 output_insn ();
1473}
1474
1475static char *
1476parse_insn (line, mnemonic)
1477 char *line;
1478 char *mnemonic;
1479{
1480 char *l = line;
1481 char *token_start = l;
1482 char *mnem_p;
1483
1484 /* Non-zero if we found a prefix only acceptable with string insns. */
1485 const char *expecting_string_instruction = NULL;
45288df1 1486
29b0f896
AM		 1487 while (1)
1488 {
1489 mnem_p = mnemonic;
1490 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1491 {
1492 mnem_p++;
1493 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1494 {
29b0f896
AM		 1495 as_bad (_("no such instruction: `%s'"), token_start);
1496 return NULL;
1497 }
1498 l++;
1499 }
1500 if (!is_space_char (*l)
1501 && *l != END_OF_INSN
1502 && *l != PREFIX_SEPARATOR
1503 && *l != ',')
1504 {
1505 as_bad (_("invalid character %s in mnemonic"),
1506 output_invalid (*l));
1507 return NULL;
1508 }
1509 if (token_start == l)
1510 {
1511 if (*l == PREFIX_SEPARATOR)
1512 as_bad (_("expecting prefix; got nothing"));
1513 else
1514 as_bad (_("expecting mnemonic; got nothing"));
1515 return NULL;
1516 }
45288df1 1517
29b0f896
AM		 1518 /* Look up instruction (or prefix) via hash table. */
1519 current_templates = hash_find (op_hash, mnemonic);
47926f60 1520
29b0f896
AM		 1521 if (*l != END_OF_INSN
1522 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1523 && current_templates
1524 && (current_templates->start->opcode_modifier & IsPrefix))
1525 {
1526 /* If we are in 16-bit mode, do not allow addr16 or data16.
1527 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1528 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1529 && flag_code != CODE_64BIT
1530 && (((current_templates->start->opcode_modifier & Size32) != 0)
1531 ^ (flag_code == CODE_16BIT)))
1532 {
1533 as_bad (_("redundant %s prefix"),
1534 current_templates->start->name);
1535 return NULL;
45288df1 1536 }
29b0f896
AM		 1537 /* Add prefix, checking for repeated prefixes. */
1538 switch (add_prefix (current_templates->start->base_opcode))
1539 {
1540 case 0:
1541 return NULL;
1542 case 2:
1543 expecting_string_instruction = current_templates->start->name;
1544 break;
1545 }
1546 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1547 token_start = ++l;
1548 }
1549 else
1550 break;
1551 }
45288df1 1552
29b0f896
AM		 1553 if (!current_templates)
1554 {
1555 /* See if we can get a match by trimming off a suffix. */
1556 switch (mnem_p[-1])
1557 {
1558 case WORD_MNEM_SUFFIX:
1559 case BYTE_MNEM_SUFFIX:
1560 case QWORD_MNEM_SUFFIX:
1561 i.suffix = mnem_p[-1];
1562 mnem_p[-1] = '\0';
1563 current_templates = hash_find (op_hash, mnemonic);
1564 break;
1565 case SHORT_MNEM_SUFFIX:
1566 case LONG_MNEM_SUFFIX:
1567 if (!intel_syntax)
1568 {
1569 i.suffix = mnem_p[-1];
1570 mnem_p[-1] = '\0';
1571 current_templates = hash_find (op_hash, mnemonic);
1572 }
1573 break;
252b5132 1574
29b0f896
AM		 1575 /* Intel Syntax. */
1576 case 'd':
1577 if (intel_syntax)
1578 {
1579 if (intel_float_operand (mnemonic))
1580 i.suffix = SHORT_MNEM_SUFFIX;
1581 else
1582 i.suffix = LONG_MNEM_SUFFIX;
1583 mnem_p[-1] = '\0';
1584 current_templates = hash_find (op_hash, mnemonic);
1585 }
1586 break;
1587 }
1588 if (!current_templates)
1589 {
1590 as_bad (_("no such instruction: `%s'"), token_start);
1591 return NULL;
1592 }
1593 }
252b5132 1594
29b0f896
AM		 1595 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
1596 {
1597 /* Check for a branch hint. We allow ",pt" and ",pn" for
1598 predict taken and predict not taken respectively.
1599 I'm not sure that branch hints actually do anything on loop
1600 and jcxz insns (JumpByte) for current Pentium4 chips. They
1601 may work in the future and it doesn't hurt to accept them
1602 now. */
1603 if (l[0] == ',' && l[1] == 'p')
1604 {
1605 if (l[2] == 't')
1606 {
1607 if (!add_prefix (DS_PREFIX_OPCODE))
1608 return NULL;
1609 l += 3;
1610 }
1611 else if (l[2] == 'n')
1612 {
1613 if (!add_prefix (CS_PREFIX_OPCODE))
1614 return NULL;
1615 l += 3;
1616 }
1617 }
1618 }
1619 /* Any other comma loses. */
1620 if (*l == ',')
1621 {
1622 as_bad (_("invalid character %s in mnemonic"),
1623 output_invalid (*l));
1624 return NULL;
1625 }
252b5132 1626
29b0f896
AM		 1627 /* Check if instruction is supported on specified architecture. */
1628 if ((current_templates->start->cpu_flags & ~(Cpu64 | CpuNo64))
1629 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64)))
1630 {
1631 as_warn (_("`%s' is not supported on `%s'"),
1632 current_templates->start->name, cpu_arch_name);
1633 }
1634 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
1635 {
1636 as_warn (_("use .code16 to ensure correct addressing mode"));
1637 }
252b5132 1638
29b0f896
AM		 1639 /* Check for rep/repne without a string instruction. */
1640 if (expecting_string_instruction
1641 && !(current_templates->start->opcode_modifier & IsString))
1642 {
1643 as_bad (_("expecting string instruction after `%s'"),
1644 expecting_string_instruction);
1645 return NULL;
1646 }
252b5132 1647
29b0f896
AM		 1648 return l;
1649}
252b5132 1650
29b0f896
AM		 1651static char *
1652parse_operands (l, mnemonic)
1653 char *l;
1654 const char *mnemonic;
1655{
1656 char *token_start;
3138f287 1657
29b0f896
AM		 1658 /* 1 if operand is pending after ','. */
1659 unsigned int expecting_operand = 0;
252b5132 1660
29b0f896
AM		 1661 /* Non-zero if operand parens not balanced. */
1662 unsigned int paren_not_balanced;
1663
1664 while (*l != END_OF_INSN)
1665 {
1666 /* Skip optional white space before operand. */
1667 if (is_space_char (*l))
1668 ++l;
1669 if (!is_operand_char (*l) && *l != END_OF_INSN)
1670 {
1671 as_bad (_("invalid character %s before operand %d"),
1672 output_invalid (*l),
1673 i.operands + 1);
1674 return NULL;
1675 }
1676 token_start = l; /* after white space */
1677 paren_not_balanced = 0;
1678 while (paren_not_balanced || *l != ',')
1679 {
1680 if (*l == END_OF_INSN)
1681 {
1682 if (paren_not_balanced)
1683 {
1684 if (!intel_syntax)
1685 as_bad (_("unbalanced parenthesis in operand %d."),
1686 i.operands + 1);
1687 else
1688 as_bad (_("unbalanced brackets in operand %d."),
1689 i.operands + 1);
1690 return NULL;
1691 }
1692 else
1693 break; /* we are done */
1694 }
1695 else if (!is_operand_char (*l) && !is_space_char (*l))
1696 {
1697 as_bad (_("invalid character %s in operand %d"),
1698 output_invalid (*l),
1699 i.operands + 1);
1700 return NULL;
1701 }
1702 if (!intel_syntax)
1703 {
1704 if (*l == '(')
1705 ++paren_not_balanced;
1706 if (*l == ')')
1707 --paren_not_balanced;
1708 }
1709 else
1710 {
1711 if (*l == '[')
1712 ++paren_not_balanced;
1713 if (*l == ']')
1714 --paren_not_balanced;
1715 }
1716 l++;
1717 }
1718 if (l != token_start)
1719 { /* Yes, we've read in another operand. */
1720 unsigned int operand_ok;
1721 this_operand = i.operands++;
1722 if (i.operands > MAX_OPERANDS)
1723 {
1724 as_bad (_("spurious operands; (%d operands/instruction max)"),
1725 MAX_OPERANDS);
1726 return NULL;
1727 }
1728 /* Now parse operand adding info to 'i' as we go along. */
1729 END_STRING_AND_SAVE (l);
1730
1731 if (intel_syntax)
1732 operand_ok =
1733 i386_intel_operand (token_start,
1734 intel_float_operand (mnemonic));
1735 else
1736 operand_ok = i386_operand (token_start);
1737
1738 RESTORE_END_STRING (l);
1739 if (!operand_ok)
1740 return NULL;
1741 }
1742 else
1743 {
1744 if (expecting_operand)
1745 {
1746 expecting_operand_after_comma:
1747 as_bad (_("expecting operand after ','; got nothing"));
1748 return NULL;
1749 }
1750 if (*l == ',')
1751 {
1752 as_bad (_("expecting operand before ','; got nothing"));
1753 return NULL;
1754 }
1755 }
7f3f1ea2 1756
29b0f896
AM		 1757 /* Now *l must be either ',' or END_OF_INSN. */
1758 if (*l == ',')
1759 {
1760 if (*++l == END_OF_INSN)
1761 {
1762 /* Just skip it, if it's \n complain. */
1763 goto expecting_operand_after_comma;
1764 }
1765 expecting_operand = 1;
1766 }
1767 }
1768 return l;
1769}
7f3f1ea2 1770
29b0f896
AM		 1771static void
1772swap_operands ()
1773{
1774 union i386_op temp_op;
1775 unsigned int temp_type;
1776 RELOC_ENUM temp_reloc;
1777 int xchg1 = 0;
1778 int xchg2 = 0;
252b5132 1779
29b0f896
AM		 1780 if (i.operands == 2)
1781 {
1782 xchg1 = 0;
1783 xchg2 = 1;
1784 }
1785 else if (i.operands == 3)
1786 {
1787 xchg1 = 0;
1788 xchg2 = 2;
1789 }
1790 temp_type = i.types[xchg2];
1791 i.types[xchg2] = i.types[xchg1];
1792 i.types[xchg1] = temp_type;
1793 temp_op = i.op[xchg2];
1794 i.op[xchg2] = i.op[xchg1];
1795 i.op[xchg1] = temp_op;
1796 temp_reloc = i.reloc[xchg2];
1797 i.reloc[xchg2] = i.reloc[xchg1];
1798 i.reloc[xchg1] = temp_reloc;
1799
1800 if (i.mem_operands == 2)
1801 {
1802 const seg_entry *temp_seg;
1803 temp_seg = i.seg[0];
1804 i.seg[0] = i.seg[1];
1805 i.seg[1] = temp_seg;
1806 }
1807}
252b5132 1808
29b0f896
AM		 1809/* Try to ensure constant immediates are represented in the smallest
1810 opcode possible. */
1811static void
1812optimize_imm ()
1813{
1814 char guess_suffix = 0;
1815 int op;
252b5132 1816
29b0f896
AM		 1817 if (i.suffix)
1818 guess_suffix = i.suffix;
1819 else if (i.reg_operands)
1820 {
1821 /* Figure out a suffix from the last register operand specified.
1822 We can't do this properly yet, ie. excluding InOutPortReg,
1823 but the following works for instructions with immediates.
1824 In any case, we can't set i.suffix yet. */
1825 for (op = i.operands; --op >= 0;)
1826 if (i.types[op] & Reg)
252b5132 1827 {
29b0f896
AM		 1828 if (i.types[op] & Reg8)
1829 guess_suffix = BYTE_MNEM_SUFFIX;
1830 else if (i.types[op] & Reg16)
1831 guess_suffix = WORD_MNEM_SUFFIX;
1832 else if (i.types[op] & Reg32)
1833 guess_suffix = LONG_MNEM_SUFFIX;
1834 else if (i.types[op] & Reg64)
1835 guess_suffix = QWORD_MNEM_SUFFIX;
1836 break;
252b5132 1837 }
29b0f896
AM		 1838 }
1839 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
1840 guess_suffix = WORD_MNEM_SUFFIX;
1841
1842 for (op = i.operands; --op >= 0;)
1843 if (i.types[op] & Imm)
1844 {
1845 switch (i.op[op].imms->X_op)
252b5132 1846 {
29b0f896
AM		 1847 case O_constant:
1848 /* If a suffix is given, this operand may be shortened. */
1849 switch (guess_suffix)
252b5132 1850 {
29b0f896
AM		 1851 case LONG_MNEM_SUFFIX:
1852 i.types[op] |= Imm32 | Imm64;
1853 break;
1854 case WORD_MNEM_SUFFIX:
1855 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
1856 break;
1857 case BYTE_MNEM_SUFFIX:
1858 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
1859 break;
252b5132 1860 }
252b5132 1861
29b0f896
AM		 1862 /* If this operand is at most 16 bits, convert it
1863 to a signed 16 bit number before trying to see
1864 whether it will fit in an even smaller size.
1865 This allows a 16-bit operand such as $0xffe0 to
1866 be recognised as within Imm8S range. */
1867 if ((i.types[op] & Imm16)
1868 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 1869 {
29b0f896
AM		 1870 i.op[op].imms->X_add_number =
1871 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
1872 }
1873 if ((i.types[op] & Imm32)
1874 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
1875 == 0))
1876 {
1877 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
1878 ^ ((offsetT) 1 << 31))
1879 - ((offsetT) 1 << 31));
1880 }
1881 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 1882
29b0f896
AM		 1883 /* We must avoid matching of Imm32 templates when 64bit
1884 only immediate is available. */
1885 if (guess_suffix == QWORD_MNEM_SUFFIX)
1886 i.types[op] &= ~Imm32;
1887 break;
252b5132 1888
29b0f896
AM		 1889 case O_absent:
1890 case O_register:
1891 abort ();
1892
1893 /* Symbols and expressions. */
1894 default:
1895 /* Convert symbolic operand to proper sizes for matching. */
1896 switch (guess_suffix)
1897 {
1898 case QWORD_MNEM_SUFFIX:
1899 i.types[op] = Imm64 | Imm32S;
1900 break;
1901 case LONG_MNEM_SUFFIX:
1902 i.types[op] = Imm32 | Imm64;
1903 break;
1904 case WORD_MNEM_SUFFIX:
1905 i.types[op] = Imm16 | Imm32 | Imm64;
1906 break;
1907 break;
1908 case BYTE_MNEM_SUFFIX:
1909 i.types[op] = Imm8 | Imm8S | Imm16 | Imm32S | Imm32;
1910 break;
1911 break;
252b5132 1912 }
29b0f896 1913 break;
252b5132 1914 }
29b0f896
AM		 1915 }
1916}
47926f60 1917
29b0f896
AM		 1918/* Try to use the smallest displacement type too. */
1919static void
1920optimize_disp ()
1921{
1922 int op;
3e73aa7c 1923
29b0f896
AM		 1924 for (op = i.operands; --op >= 0;)
1925 if ((i.types[op] & Disp) && i.op[op].disps->X_op == O_constant)
252b5132 1926 {
29b0f896
AM		 1927 offsetT disp = i.op[op].disps->X_add_number;
1928
1929 if (i.types[op] & Disp16)
252b5132 1930 {
29b0f896
AM		 1931 /* We know this operand is at most 16 bits, so
1932 convert to a signed 16 bit number before trying
1933 to see whether it will fit in an even smaller
1934 size. */
1935
1936 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
252b5132 1937 }
29b0f896 1938 else if (i.types[op] & Disp32)
252b5132 1939 {
29b0f896
AM		 1940 /* We know this operand is at most 32 bits, so convert to a
1941 signed 32 bit number before trying to see whether it will
1942 fit in an even smaller size. */
1943 disp &= (((offsetT) 2 << 31) - 1);
1944 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 1945 }
29b0f896 1946 if (flag_code == CODE_64BIT)
252b5132 1947 {
29b0f896
AM		 1948 if (fits_in_signed_long (disp))
1949 i.types[op] |= Disp32S;
1950 if (fits_in_unsigned_long (disp))
1951 i.types[op] |= Disp32;
252b5132 1952 }
29b0f896
AM		 1953 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
1954 && fits_in_signed_byte (disp))
1955 i.types[op] |= Disp8;
252b5132 1956 }
29b0f896
AM		 1957}
1958
1959static int
1960match_template ()
1961{
1962 /* Points to template once we've found it. */
1963 const template *t;
1964 unsigned int overlap0, overlap1, overlap2;
1965 unsigned int found_reverse_match;
1966 int suffix_check;
1967
1968#define MATCH(overlap, given, template) \
1969 ((overlap & ~JumpAbsolute) \
1970 && (((given) & (BaseIndex | JumpAbsolute)) \
1971 == ((overlap) & (BaseIndex | JumpAbsolute))))
1972
1973 /* If given types r0 and r1 are registers they must be of the same type
1974 unless the expected operand type register overlap is null.
1975 Note that Acc in a template matches every size of reg. */
1976#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1977 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
1978 || ((g0) & Reg) == ((g1) & Reg) \
1979 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1980
1981 overlap0 = 0;
1982 overlap1 = 0;
1983 overlap2 = 0;
1984 found_reverse_match = 0;
1985 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
1986 ? No_bSuf
1987 : (i.suffix == WORD_MNEM_SUFFIX
1988 ? No_wSuf
1989 : (i.suffix == SHORT_MNEM_SUFFIX
1990 ? No_sSuf
1991 : (i.suffix == LONG_MNEM_SUFFIX
1992 ? No_lSuf
1993 : (i.suffix == QWORD_MNEM_SUFFIX
1994 ? No_qSuf
1995 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
1996 ? No_xSuf : 0))))));
1997
1998 for (t = current_templates->start;
1999 t < current_templates->end;
2000 t++)
2001 {
2002 /* Must have right number of operands. */
2003 if (i.operands != t->operands)
2004 continue;
2005
2006 /* Check the suffix, except for some instructions in intel mode. */
2007 if ((t->opcode_modifier & suffix_check)
2008 && !(intel_syntax
2009 && (t->opcode_modifier & IgnoreSize))
2010 && !(intel_syntax
2011 && t->base_opcode == 0xd9
2012 && (t->extension_opcode == 5 /* 0xd9,5 "fldcw" */
2013 || t->extension_opcode == 7))) /* 0xd9,7 "f{n}stcw" */
2014 continue;
2015
2016 /* Do not verify operands when there are none. */
2017 else if (!t->operands)
2018 {
2019 if (t->cpu_flags & ~cpu_arch_flags)
2020 continue;
2021 /* We've found a match; break out of loop. */
2022 break;
2023 }
252b5132 2024
29b0f896
AM		 2025 overlap0 = i.types[0] & t->operand_types[0];
2026 switch (t->operands)
2027 {
2028 case 1:
2029 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
2030 continue;
2031 break;
2032 case 2:
2033 case 3:
2034 overlap1 = i.types[1] & t->operand_types[1];
2035 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
2036 || !MATCH (overlap1, i.types[1], t->operand_types[1])
2037 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2038 t->operand_types[0],
2039 overlap1, i.types[1],
2040 t->operand_types[1]))
2041 {
2042 /* Check if other direction is valid ... */
2043 if ((t->opcode_modifier & (D | FloatD)) == 0)
2044 continue;
2045
2046 /* Try reversing direction of operands. */
2047 overlap0 = i.types[0] & t->operand_types[1];
2048 overlap1 = i.types[1] & t->operand_types[0];
2049 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
2050 || !MATCH (overlap1, i.types[1], t->operand_types[0])
2051 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2052 t->operand_types[1],
2053 overlap1, i.types[1],
2054 t->operand_types[0]))
2055 {
2056 /* Does not match either direction. */
2057 continue;
2058 }
2059 /* found_reverse_match holds which of D or FloatDR
2060 we've found. */
2061 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2062 }
2063 /* Found a forward 2 operand match here. */
2064 else if (t->operands == 3)
2065 {
2066 /* Here we make use of the fact that there are no
2067 reverse match 3 operand instructions, and all 3
2068 operand instructions only need to be checked for
2069 register consistency between operands 2 and 3. */
2070 overlap2 = i.types[2] & t->operand_types[2];
2071 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
2072 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2073 t->operand_types[1],
2074 overlap2, i.types[2],
2075 t->operand_types[2]))
2076
2077 continue;
2078 }
2079 /* Found either forward/reverse 2 or 3 operand match here:
2080 slip through to break. */
2081 }
2082 if (t->cpu_flags & ~cpu_arch_flags)
2083 {
2084 found_reverse_match = 0;
2085 continue;
2086 }
2087 /* We've found a match; break out of loop. */
2088 break;
2089 }
2090
2091 if (t == current_templates->end)
2092 {
2093 /* We found no match. */
2094 as_bad (_("suffix or operands invalid for `%s'"),
2095 current_templates->start->name);
2096 return 0;
2097 }
252b5132 2098
29b0f896
AM		 2099 if (!quiet_warnings)
2100 {
2101 if (!intel_syntax
2102 && ((i.types[0] & JumpAbsolute)
2103 != (t->operand_types[0] & JumpAbsolute)))
2104 {
2105 as_warn (_("indirect %s without `*'"), t->name);
2106 }
2107
2108 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2109 == (IsPrefix | IgnoreSize))
2110 {
2111 /* Warn them that a data or address size prefix doesn't
2112 affect assembly of the next line of code. */
2113 as_warn (_("stand-alone `%s' prefix"), t->name);
2114 }
2115 }
2116
2117 /* Copy the template we found. */
2118 i.tm = *t;
2119 if (found_reverse_match)
2120 {
2121 /* If we found a reverse match we must alter the opcode
2122 direction bit. found_reverse_match holds bits to change
2123 (different for int & float insns). */
2124
2125 i.tm.base_opcode ^= found_reverse_match;
2126
2127 i.tm.operand_types[0] = t->operand_types[1];
2128 i.tm.operand_types[1] = t->operand_types[0];
2129 }
2130
2131 return 1;
2132}
2133
2134static int
2135check_string ()
2136{
2137 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2138 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2139 {
2140 if (i.seg[0] != NULL && i.seg[0] != &es)
2141 {
2142 as_bad (_("`%s' operand %d must use `%%es' segment"),
2143 i.tm.name,
2144 mem_op + 1);
2145 return 0;
2146 }
2147 /* There's only ever one segment override allowed per instruction.
2148 This instruction possibly has a legal segment override on the
2149 second operand, so copy the segment to where non-string
2150 instructions store it, allowing common code. */
2151 i.seg[0] = i.seg[1];
2152 }
2153 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2154 {
2155 if (i.seg[1] != NULL && i.seg[1] != &es)
2156 {
2157 as_bad (_("`%s' operand %d must use `%%es' segment"),
2158 i.tm.name,
2159 mem_op + 2);
2160 return 0;
2161 }
2162 }
2163 return 1;
2164}
2165
2166static int
2167process_suffix ()
2168{
2169 /* If matched instruction specifies an explicit instruction mnemonic
2170 suffix, use it. */
2171 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2172 {
2173 if (i.tm.opcode_modifier & Size16)
2174 i.suffix = WORD_MNEM_SUFFIX;
2175 else if (i.tm.opcode_modifier & Size64)
2176 i.suffix = QWORD_MNEM_SUFFIX;
2177 else
2178 i.suffix = LONG_MNEM_SUFFIX;
2179 }
2180 else if (i.reg_operands)
2181 {
2182 /* If there's no instruction mnemonic suffix we try to invent one
2183 based on register operands. */
2184 if (!i.suffix)
2185 {
2186 /* We take i.suffix from the last register operand specified,
2187 Destination register type is more significant than source
2188 register type. */
2189 int op;
2190 for (op = i.operands; --op >= 0;)
2191 if ((i.types[op] & Reg)
2192 && !(i.tm.operand_types[op] & InOutPortReg))
2193 {
2194 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2195 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2196 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2197 LONG_MNEM_SUFFIX);
2198 break;
2199 }
2200 }
2201 else if (i.suffix == BYTE_MNEM_SUFFIX)
2202 {
2203 if (!check_byte_reg ())
2204 return 0;
2205 }
2206 else if (i.suffix == LONG_MNEM_SUFFIX)
2207 {
2208 if (!check_long_reg ())
2209 return 0;
2210 }
2211 else if (i.suffix == QWORD_MNEM_SUFFIX)
2212 {
2213 if (!check_qword_reg ())
2214 return 0;
2215 }
2216 else if (i.suffix == WORD_MNEM_SUFFIX)
2217 {
2218 if (!check_word_reg ())
2219 return 0;
2220 }
2221 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2222 /* Do nothing if the instruction is going to ignore the prefix. */
2223 ;
2224 else
2225 abort ();
2226 }
2227 else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix)
2228 {
2229 i.suffix = stackop_size;
2230 }
252b5132 2231
29b0f896
AM		 2232 /* Change the opcode based on the operand size given by i.suffix;
2233 We need not change things for byte insns. */
252b5132 2234
29b0f896
AM		 2235 if (!i.suffix && (i.tm.opcode_modifier & W))
2236 {
2237 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2238 return 0;
2239 }
252b5132 2240
29b0f896
AM		 2241 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2242 {
2243 /* It's not a byte, select word/dword operation. */
2244 if (i.tm.opcode_modifier & W)
2245 {
2246 if (i.tm.opcode_modifier & ShortForm)
2247 i.tm.base_opcode |= 8;
2248 else
2249 i.tm.base_opcode |= 1;
2250 }
0f3f3d8b 2251
29b0f896
AM		 2252 /* Now select between word & dword operations via the operand
2253 size prefix, except for instructions that will ignore this
2254 prefix anyway. */
2255 if (i.suffix != QWORD_MNEM_SUFFIX
9146926a
AM		 2256 && !(i.tm.opcode_modifier & IgnoreSize)
2257 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2258 || (flag_code == CODE_64BIT
2259 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 2260 {
2261 unsigned int prefix = DATA_PREFIX_OPCODE;
29b0f896
AM		 2262 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2263 prefix = ADDR_PREFIX_OPCODE;
252b5132 2264
29b0f896
AM		 2265 if (!add_prefix (prefix))
2266 return 0;
24eab124 2267 }
252b5132 2268
29b0f896
AM		 2269 /* Set mode64 for an operand. */
2270 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 2271 && flag_code == CODE_64BIT
29b0f896 2272 && (i.tm.opcode_modifier & NoRex64) == 0)
9146926a 2273 i.rex |= REX_MODE64;
3e73aa7c 2274
29b0f896
AM		 2275 /* Size floating point instruction. */
2276 if (i.suffix == LONG_MNEM_SUFFIX)
2277 {
2278 if (i.tm.opcode_modifier & FloatMF)
2279 i.tm.base_opcode ^= 4;
2280 }
2281 }
7ecd2f8b 2282
29b0f896
AM		 2283 return 1;
2284}
3e73aa7c 2285
29b0f896
AM		 2286static int
2287check_byte_reg ()
2288{
2289 int op;
2290 for (op = i.operands; --op >= 0;)
2291 {
2292 /* If this is an eight bit register, it's OK. If it's the 16 or
2293 32 bit version of an eight bit register, we will just use the
2294 low portion, and that's OK too. */
2295 if (i.types[op] & Reg8)
2296 continue;
2297
2298 /* movzx and movsx should not generate this warning. */
2299 if (intel_syntax
2300 && (i.tm.base_opcode == 0xfb7
2301 || i.tm.base_opcode == 0xfb6
2302 || i.tm.base_opcode == 0x63
2303 || i.tm.base_opcode == 0xfbe
2304 || i.tm.base_opcode == 0xfbf))
2305 continue;
2306
2307 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4
2308#if 0
2309 /* Check that the template allows eight bit regs. This
2310 kills insns such as `orb $1,%edx', which maybe should be
2311 allowed. */
2312 && (i.tm.operand_types[op] & (Reg8 | InOutPortReg))
2313#endif
2314 )
2315 {
2316 /* Prohibit these changes in the 64bit mode, since the
2317 lowering is more complicated. */
2318 if (flag_code == CODE_64BIT
2319 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2320 {
0f3f3d8b 2321 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2322 i.op[op].regs->reg_name,
2323 i.suffix);
2324 return 0;
2325 }
2326#if REGISTER_WARNINGS
2327 if (!quiet_warnings
2328 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2329 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2330 (i.op[op].regs + (i.types[op] & Reg16
2331 ? REGNAM_AL - REGNAM_AX
2332 : REGNAM_AL - REGNAM_EAX))->reg_name,
2333 i.op[op].regs->reg_name,
2334 i.suffix);
2335#endif
2336 continue;
2337 }
2338 /* Any other register is bad. */
2339 if (i.types[op] & (Reg | RegMMX | RegXMM
2340 | SReg2 | SReg3
2341 | Control | Debug | Test
2342 | FloatReg | FloatAcc))
2343 {
2344 as_bad (_("`%%%s' not allowed with `%s%c'"),
2345 i.op[op].regs->reg_name,
2346 i.tm.name,
2347 i.suffix);
2348 return 0;
2349 }
2350 }
2351 return 1;
2352}
2353
2354static int
2355check_long_reg ()
2356{
2357 int op;
2358
2359 for (op = i.operands; --op >= 0;)
2360 /* Reject eight bit registers, except where the template requires
2361 them. (eg. movzb) */
2362 if ((i.types[op] & Reg8) != 0
2363 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2364 {
2365 as_bad (_("`%%%s' not allowed with `%s%c'"),
2366 i.op[op].regs->reg_name,
2367 i.tm.name,
2368 i.suffix);
2369 return 0;
2370 }
2371 /* Warn if the e prefix on a general reg is missing. */
2372 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2373 && (i.types[op] & Reg16) != 0
2374 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2375 {
2376 /* Prohibit these changes in the 64bit mode, since the
2377 lowering is more complicated. */
2378 if (flag_code == CODE_64BIT)
252b5132 2379 {
0f3f3d8b 2380 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2381 i.op[op].regs->reg_name,
2382 i.suffix);
2383 return 0;
252b5132 2384 }
29b0f896
AM		 2385#if REGISTER_WARNINGS
2386 else
2387 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2388 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
2389 i.op[op].regs->reg_name,
2390 i.suffix);
2391#endif
252b5132 2392 }
29b0f896
AM		 2393 /* Warn if the r prefix on a general reg is missing. */
2394 else if ((i.types[op] & Reg64) != 0
2395 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 2396 {
0f3f3d8b 2397 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2398 i.op[op].regs->reg_name,
2399 i.suffix);
2400 return 0;
2401 }
2402 return 1;
2403}
252b5132 2404
29b0f896
AM		 2405static int
2406check_qword_reg ()
2407{
2408 int op;
252b5132 2409
29b0f896
AM		 2410 for (op = i.operands; --op >= 0; )
2411 /* Reject eight bit registers, except where the template requires
2412 them. (eg. movzb) */
2413 if ((i.types[op] & Reg8) != 0
2414 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2415 {
2416 as_bad (_("`%%%s' not allowed with `%s%c'"),
2417 i.op[op].regs->reg_name,
2418 i.tm.name,
2419 i.suffix);
2420 return 0;
2421 }
2422 /* Warn if the e prefix on a general reg is missing. */
2423 else if (((i.types[op] & Reg16) != 0
2424 || (i.types[op] & Reg32) != 0)
2425 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2426 {
2427 /* Prohibit these changes in the 64bit mode, since the
2428 lowering is more complicated. */
0f3f3d8b 2429 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2430 i.op[op].regs->reg_name,
2431 i.suffix);
2432 return 0;
252b5132 2433 }
29b0f896
AM		 2434 return 1;
2435}
252b5132 2436
29b0f896
AM		 2437static int
2438check_word_reg ()
2439{
2440 int op;
2441 for (op = i.operands; --op >= 0;)
2442 /* Reject eight bit registers, except where the template requires
2443 them. (eg. movzb) */
2444 if ((i.types[op] & Reg8) != 0
2445 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2446 {
2447 as_bad (_("`%%%s' not allowed with `%s%c'"),
2448 i.op[op].regs->reg_name,
2449 i.tm.name,
2450 i.suffix);
2451 return 0;
2452 }
2453 /* Warn if the e prefix on a general reg is present. */
2454 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2455 && (i.types[op] & Reg32) != 0
2456 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 2457 {
29b0f896
AM		 2458 /* Prohibit these changes in the 64bit mode, since the
2459 lowering is more complicated. */
2460 if (flag_code == CODE_64BIT)
252b5132 2461 {
0f3f3d8b 2462 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2463 i.op[op].regs->reg_name,
2464 i.suffix);
2465 return 0;
252b5132 2466 }
29b0f896
AM		 2467 else
2468#if REGISTER_WARNINGS
2469 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2470 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
2471 i.op[op].regs->reg_name,
2472 i.suffix);
2473#endif
2474 }
2475 return 1;
2476}
252b5132 2477
29b0f896
AM		 2478static int
2479finalize_imm ()
2480{
2481 unsigned int overlap0, overlap1, overlap2;
2482
2483 overlap0 = i.types[0] & i.tm.operand_types[0];
2484 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S))
2485 && overlap0 != Imm8 && overlap0 != Imm8S
2486 && overlap0 != Imm16 && overlap0 != Imm32S
2487 && overlap0 != Imm32 && overlap0 != Imm64)
2488 {
2489 if (i.suffix)
2490 {
2491 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
2492 ? Imm8 | Imm8S
2493 : (i.suffix == WORD_MNEM_SUFFIX
2494 ? Imm16
2495 : (i.suffix == QWORD_MNEM_SUFFIX
2496 ? Imm64 | Imm32S
2497 : Imm32)));
2498 }
2499 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2500 || overlap0 == (Imm16 | Imm32)
2501 || overlap0 == (Imm16 | Imm32S))
2502 {
2503 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2504 ? Imm16 : Imm32S);
2505 }
2506 if (overlap0 != Imm8 && overlap0 != Imm8S
2507 && overlap0 != Imm16 && overlap0 != Imm32S
2508 && overlap0 != Imm32 && overlap0 != Imm64)
2509 {
2510 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2511 return 0;
2512 }
2513 }
2514 i.types[0] = overlap0;
2515
2516 overlap1 = i.types[1] & i.tm.operand_types[1];
2517 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32))
2518 && overlap1 != Imm8 && overlap1 != Imm8S
2519 && overlap1 != Imm16 && overlap1 != Imm32S
2520 && overlap1 != Imm32 && overlap1 != Imm64)
2521 {
2522 if (i.suffix)
2523 {
2524 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
2525 ? Imm8 | Imm8S
2526 : (i.suffix == WORD_MNEM_SUFFIX
2527 ? Imm16
2528 : (i.suffix == QWORD_MNEM_SUFFIX
2529 ? Imm64 | Imm32S
2530 : Imm32)));
2531 }
2532 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2533 || overlap1 == (Imm16 | Imm32)
2534 || overlap1 == (Imm16 | Imm32S))
2535 {
2536 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2537 ? Imm16 : Imm32S);
2538 }
2539 if (overlap1 != Imm8 && overlap1 != Imm8S
2540 && overlap1 != Imm16 && overlap1 != Imm32S
2541 && overlap1 != Imm32 && overlap1 != Imm64)
2542 {
2543 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
2544 return 0;
2545 }
2546 }
2547 i.types[1] = overlap1;
2548
2549 overlap2 = i.types[2] & i.tm.operand_types[2];
2550 assert ((overlap2 & Imm) == 0);
2551 i.types[2] = overlap2;
2552
2553 return 1;
2554}
2555
2556static int
2557process_operands ()
2558{
2559 /* Default segment register this instruction will use for memory
2560 accesses. 0 means unknown. This is only for optimizing out
2561 unnecessary segment overrides. */
2562 const seg_entry *default_seg = 0;
2563
2564 /* The imul $imm, %reg instruction is converted into
2565 imul $imm, %reg, %reg, and the clr %reg instruction
2566 is converted into xor %reg, %reg. */
2567 if (i.tm.opcode_modifier & regKludge)
2568 {
2569 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
2570 /* Pretend we saw the extra register operand. */
2571 assert (i.op[first_reg_op + 1].regs == 0);
2572 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2573 i.types[first_reg_op + 1] = i.types[first_reg_op];
2574 i.reg_operands = 2;
2575 }
2576
2577 if (i.tm.opcode_modifier & ShortForm)
2578 {
2579 /* The register or float register operand is in operand 0 or 1. */
2580 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2581 /* Register goes in low 3 bits of opcode. */
2582 i.tm.base_opcode |= i.op[op].regs->reg_num;
2583 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2584 i.rex |= REX_EXTZ;
2585 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2586 {
2587 /* Warn about some common errors, but press on regardless.
2588 The first case can be generated by gcc (<= 2.8.1). */
2589 if (i.operands == 2)
2590 {
2591 /* Reversed arguments on faddp, fsubp, etc. */
2592 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
2593 i.op[1].regs->reg_name,
2594 i.op[0].regs->reg_name);
2595 }
2596 else
2597 {
2598 /* Extraneous `l' suffix on fp insn. */
2599 as_warn (_("translating to `%s %%%s'"), i.tm.name,
2600 i.op[0].regs->reg_name);
2601 }
2602 }
2603 }
2604 else if (i.tm.opcode_modifier & Modrm)
2605 {
2606 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 2607 must be put into the modrm byte). Now, we make the modrm and
2608 index base bytes based on all the info we've collected. */
29b0f896
AM		 2609
2610 default_seg = build_modrm_byte ();
2611 }
2612 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2613 {
2614 if (i.tm.base_opcode == POP_SEG_SHORT
2615 && i.op[0].regs->reg_num == 1)
2616 {
2617 as_bad (_("you can't `pop %%cs'"));
2618 return 0;
2619 }
2620 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2621 if ((i.op[0].regs->reg_flags & RegRex) != 0)
2622 i.rex |= REX_EXTZ;
2623 }
2624 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
2625 {
2626 default_seg = &ds;
2627 }
2628 else if ((i.tm.opcode_modifier & IsString) != 0)
2629 {
2630 /* For the string instructions that allow a segment override
2631 on one of their operands, the default segment is ds. */
2632 default_seg = &ds;
2633 }
2634
52271982
AM		 2635 if (i.tm.base_opcode == 0x8d /* lea */ && i.seg[0] && !quiet_warnings)
2636 as_warn (_("segment override on `lea' is ineffectual"));
2637
2638 /* If a segment was explicitly specified, and the specified segment
2639 is not the default, use an opcode prefix to select it. If we
2640 never figured out what the default segment is, then default_seg
2641 will be zero at this point, and the specified segment prefix will
2642 always be used. */
29b0f896
AM		 2643 if ((i.seg[0]) && (i.seg[0] != default_seg))
2644 {
2645 if (!add_prefix (i.seg[0]->seg_prefix))
2646 return 0;
2647 }
2648 return 1;
2649}
2650
2651static const seg_entry *
2652build_modrm_byte ()
2653{
2654 const seg_entry *default_seg = 0;
2655
2656 /* i.reg_operands MUST be the number of real register operands;
2657 implicit registers do not count. */
2658 if (i.reg_operands == 2)
2659 {
2660 unsigned int source, dest;
2661 source = ((i.types[0]
2662 & (Reg | RegMMX | RegXMM
2663 | SReg2 | SReg3
2664 | Control | Debug | Test))
2665 ? 0 : 1);
2666 dest = source + 1;
2667
2668 i.rm.mode = 3;
2669 /* One of the register operands will be encoded in the i.tm.reg
2670 field, the other in the combined i.tm.mode and i.tm.regmem
2671 fields. If no form of this instruction supports a memory
2672 destination operand, then we assume the source operand may
2673 sometimes be a memory operand and so we need to store the
2674 destination in the i.rm.reg field. */
2675 if ((i.tm.operand_types[dest] & AnyMem) == 0)
2676 {
2677 i.rm.reg = i.op[dest].regs->reg_num;
2678 i.rm.regmem = i.op[source].regs->reg_num;
2679 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2680 i.rex |= REX_EXTX;
2681 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2682 i.rex |= REX_EXTZ;
2683 }
2684 else
2685 {
2686 i.rm.reg = i.op[source].regs->reg_num;
2687 i.rm.regmem = i.op[dest].regs->reg_num;
2688 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2689 i.rex |= REX_EXTZ;
2690 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2691 i.rex |= REX_EXTX;
2692 }
2693 }
2694 else
2695 { /* If it's not 2 reg operands... */
2696 if (i.mem_operands)
2697 {
2698 unsigned int fake_zero_displacement = 0;
2699 unsigned int op = ((i.types[0] & AnyMem)
2700 ? 0
2701 : (i.types[1] & AnyMem) ? 1 : 2);
2702
2703 default_seg = &ds;
2704
2705 if (i.base_reg == 0)
2706 {
2707 i.rm.mode = 0;
2708 if (!i.disp_operands)
2709 fake_zero_displacement = 1;
2710 if (i.index_reg == 0)
2711 {
2712 /* Operand is just <disp> */
2713 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
2714 && (flag_code != CODE_64BIT))
2715 {
2716 i.rm.regmem = NO_BASE_REGISTER_16;
2717 i.types[op] &= ~Disp;
2718 i.types[op] |= Disp16;
2719 }
2720 else if (flag_code != CODE_64BIT
2721 || (i.prefix[ADDR_PREFIX] != 0))
2722 {
2723 i.rm.regmem = NO_BASE_REGISTER;
2724 i.types[op] &= ~Disp;
2725 i.types[op] |= Disp32;
2726 }
2727 else
2728 {
2729 /* 64bit mode overwrites the 32bit absolute
2730 addressing by RIP relative addressing and
2731 absolute addressing is encoded by one of the
2732 redundant SIB forms. */
2733 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2734 i.sib.base = NO_BASE_REGISTER;
2735 i.sib.index = NO_INDEX_REGISTER;
2736 i.types[op] &= ~Disp;
2737 i.types[op] |= Disp32S;
2738 }
2739 }
2740 else /* !i.base_reg && i.index_reg */
2741 {
2742 i.sib.index = i.index_reg->reg_num;
2743 i.sib.base = NO_BASE_REGISTER;
2744 i.sib.scale = i.log2_scale_factor;
2745 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2746 i.types[op] &= ~Disp;
2747 if (flag_code != CODE_64BIT)
2748 i.types[op] |= Disp32; /* Must be 32 bit */
2749 else
2750 i.types[op] |= Disp32S;
2751 if ((i.index_reg->reg_flags & RegRex) != 0)
2752 i.rex |= REX_EXTY;
2753 }
2754 }
2755 /* RIP addressing for 64bit mode. */
2756 else if (i.base_reg->reg_type == BaseIndex)
2757 {
2758 i.rm.regmem = NO_BASE_REGISTER;
2759 i.types[op] &= ~Disp;
2760 i.types[op] |= Disp32S;
2761 i.flags[op] = Operand_PCrel;
2762 }
2763 else if (i.base_reg->reg_type & Reg16)
2764 {
2765 switch (i.base_reg->reg_num)
2766 {
2767 case 3: /* (%bx) */
2768 if (i.index_reg == 0)
2769 i.rm.regmem = 7;
2770 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2771 i.rm.regmem = i.index_reg->reg_num - 6;
2772 break;
2773 case 5: /* (%bp) */
2774 default_seg = &ss;
2775 if (i.index_reg == 0)
2776 {
2777 i.rm.regmem = 6;
2778 if ((i.types[op] & Disp) == 0)
2779 {
2780 /* fake (%bp) into 0(%bp) */
2781 i.types[op] |= Disp8;
252b5132 2782 fake_zero_displacement = 1;
29b0f896
AM		 2783 }
2784 }
2785 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2786 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
2787 break;
2788 default: /* (%si) -> 4 or (%di) -> 5 */
2789 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
2790 }
2791 i.rm.mode = mode_from_disp_size (i.types[op]);
2792 }
2793 else /* i.base_reg and 32/64 bit mode */
2794 {
2795 if (flag_code == CODE_64BIT
2796 && (i.types[op] & Disp))
2797 {
2798 if (i.types[op] & Disp8)
2799 i.types[op] = Disp8 | Disp32S;
2800 else
2801 i.types[op] = Disp32S;
2802 }
2803 i.rm.regmem = i.base_reg->reg_num;
2804 if ((i.base_reg->reg_flags & RegRex) != 0)
2805 i.rex |= REX_EXTZ;
2806 i.sib.base = i.base_reg->reg_num;
2807 /* x86-64 ignores REX prefix bit here to avoid decoder
2808 complications. */
2809 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
2810 {
2811 default_seg = &ss;
2812 if (i.disp_operands == 0)
2813 {
2814 fake_zero_displacement = 1;
2815 i.types[op] |= Disp8;
2816 }
2817 }
2818 else if (i.base_reg->reg_num == ESP_REG_NUM)
2819 {
2820 default_seg = &ss;
2821 }
2822 i.sib.scale = i.log2_scale_factor;
2823 if (i.index_reg == 0)
2824 {
2825 /* <disp>(%esp) becomes two byte modrm with no index
2826 register. We've already stored the code for esp
2827 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
2828 Any base register besides %esp will not use the
2829 extra modrm byte. */
2830 i.sib.index = NO_INDEX_REGISTER;
2831#if !SCALE1_WHEN_NO_INDEX
2832 /* Another case where we force the second modrm byte. */
2833 if (i.log2_scale_factor)
2834 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 2835#endif
29b0f896
AM		 2836 }
2837 else
2838 {
2839 i.sib.index = i.index_reg->reg_num;
2840 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2841 if ((i.index_reg->reg_flags & RegRex) != 0)
2842 i.rex |= REX_EXTY;
2843 }
2844 i.rm.mode = mode_from_disp_size (i.types[op]);
2845 }
252b5132 2846
29b0f896
AM		 2847 if (fake_zero_displacement)
2848 {
2849 /* Fakes a zero displacement assuming that i.types[op]
2850 holds the correct displacement size. */
2851 expressionS *exp;
2852
2853 assert (i.op[op].disps == 0);
2854 exp = &disp_expressions[i.disp_operands++];
2855 i.op[op].disps = exp;
2856 exp->X_op = O_constant;
2857 exp->X_add_number = 0;
2858 exp->X_add_symbol = (symbolS *) 0;
2859 exp->X_op_symbol = (symbolS *) 0;
2860 }
2861 }
252b5132 2862
29b0f896
AM		 2863 /* Fill in i.rm.reg or i.rm.regmem field with register operand
2864 (if any) based on i.tm.extension_opcode. Again, we must be
2865 careful to make sure that segment/control/debug/test/MMX
2866 registers are coded into the i.rm.reg field. */
2867 if (i.reg_operands)
2868 {
2869 unsigned int op =
2870 ((i.types[0]
2871 & (Reg | RegMMX | RegXMM
2872 | SReg2 | SReg3
2873 | Control | Debug | Test))
2874 ? 0
2875 : ((i.types[1]
2876 & (Reg | RegMMX | RegXMM
2877 | SReg2 | SReg3
2878 | Control | Debug | Test))
2879 ? 1
2880 : 2));
2881 /* If there is an extension opcode to put here, the register
2882 number must be put into the regmem field. */
2883 if (i.tm.extension_opcode != None)
2884 {
2885 i.rm.regmem = i.op[op].regs->reg_num;
2886 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2887 i.rex |= REX_EXTZ;
2888 }
2889 else
2890 {
2891 i.rm.reg = i.op[op].regs->reg_num;
2892 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2893 i.rex |= REX_EXTX;
2894 }
252b5132 2895
29b0f896
AM		 2896 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
2897 must set it to 3 to indicate this is a register operand
2898 in the regmem field. */
2899 if (!i.mem_operands)
2900 i.rm.mode = 3;
2901 }
252b5132 2902
29b0f896
AM		 2903 /* Fill in i.rm.reg field with extension opcode (if any). */
2904 if (i.tm.extension_opcode != None)
2905 i.rm.reg = i.tm.extension_opcode;
2906 }
2907 return default_seg;
2908}
252b5132 2909
29b0f896
AM		 2910static void
2911output_branch ()
2912{
2913 char *p;
2914 int code16;
2915 int prefix;
2916 relax_substateT subtype;
2917 symbolS *sym;
2918 offsetT off;
2919
2920 code16 = 0;
2921 if (flag_code == CODE_16BIT)
2922 code16 = CODE16;
2923
2924 prefix = 0;
2925 if (i.prefix[DATA_PREFIX] != 0)
252b5132 2926 {
29b0f896
AM		 2927 prefix = 1;
2928 i.prefixes -= 1;
2929 code16 ^= CODE16;
252b5132 2930 }
29b0f896
AM		 2931 /* Pentium4 branch hints. */
2932 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
2933 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 2934 {
29b0f896
AM		 2935 prefix++;
2936 i.prefixes--;
2937 }
2938 if (i.prefix[REX_PREFIX] != 0)
2939 {
2940 prefix++;
2941 i.prefixes--;
2f66722d
AM		 2942 }
2943
29b0f896
AM		 2944 if (i.prefixes != 0 && !intel_syntax)
2945 as_warn (_("skipping prefixes on this instruction"));
2946
2947 /* It's always a symbol; End frag & setup for relax.
2948 Make sure there is enough room in this frag for the largest
2949 instruction we may generate in md_convert_frag. This is 2
2950 bytes for the opcode and room for the prefix and largest
2951 displacement. */
2952 frag_grow (prefix + 2 + 4);
2953 /* Prefix and 1 opcode byte go in fr_fix. */
2954 p = frag_more (prefix + 1);
2955 if (i.prefix[DATA_PREFIX] != 0)
2956 *p++ = DATA_PREFIX_OPCODE;
2957 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
2958 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
2959 *p++ = i.prefix[SEG_PREFIX];
2960 if (i.prefix[REX_PREFIX] != 0)
2961 *p++ = i.prefix[REX_PREFIX];
2962 *p = i.tm.base_opcode;
2963
2964 if ((unsigned char) *p == JUMP_PC_RELATIVE)
2965 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
2966 else if ((cpu_arch_flags & Cpu386) != 0)
2967 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
2968 else
2969 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
2970 subtype |= code16;
3e73aa7c 2971
29b0f896
AM		 2972 sym = i.op[0].disps->X_add_symbol;
2973 off = i.op[0].disps->X_add_number;
3e73aa7c 2974
29b0f896
AM		 2975 if (i.op[0].disps->X_op != O_constant
2976 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 2977 {
29b0f896
AM		 2978 /* Handle complex expressions. */
2979 sym = make_expr_symbol (i.op[0].disps);
2980 off = 0;
2981 }
3e73aa7c 2982
29b0f896
AM		 2983 /* 1 possible extra opcode + 4 byte displacement go in var part.
2984 Pass reloc in fr_var. */
2985 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
2986}
3e73aa7c 2987
29b0f896
AM		 2988static void
2989output_jump ()
2990{
2991 char *p;
2992 int size;
2993
2994 if (i.tm.opcode_modifier & JumpByte)
2995 {
2996 /* This is a loop or jecxz type instruction. */
2997 size = 1;
2998 if (i.prefix[ADDR_PREFIX] != 0)
2999 {
3000 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3001 i.prefixes -= 1;
3002 }
3003 /* Pentium4 branch hints. */
3004 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3005 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3006 {
3007 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3008 i.prefixes--;
3e73aa7c
JH		 3009 }
3010 }
29b0f896
AM		 3011 else
3012 {
3013 int code16;
3e73aa7c 3014
29b0f896
AM		 3015 code16 = 0;
3016 if (flag_code == CODE_16BIT)
3017 code16 = CODE16;
3e73aa7c 3018
29b0f896
AM		 3019 if (i.prefix[DATA_PREFIX] != 0)
3020 {
3021 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3022 i.prefixes -= 1;
3023 code16 ^= CODE16;
3024 }
252b5132 3025
29b0f896
AM		 3026 size = 4;
3027 if (code16)
3028 size = 2;
3029 }
9fcc94b6 3030
29b0f896
AM		 3031 if (i.prefix[REX_PREFIX] != 0)
3032 {
3033 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3034 i.prefixes -= 1;
3035 }
252b5132 3036
29b0f896
AM		 3037 if (i.prefixes != 0 && !intel_syntax)
3038 as_warn (_("skipping prefixes on this instruction"));
e0890092 3039
29b0f896
AM		 3040 p = frag_more (1 + size);
3041 *p++ = i.tm.base_opcode;
e0890092 3042
062cd5e7
AS		 3043 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3044 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
29b0f896 3045}
e0890092 3046
29b0f896
AM		 3047static void
3048output_interseg_jump ()
3049{
3050 char *p;
3051 int size;
3052 int prefix;
3053 int code16;
252b5132 3054
29b0f896
AM		 3055 code16 = 0;
3056 if (flag_code == CODE_16BIT)
3057 code16 = CODE16;
a217f122 3058
29b0f896
AM		 3059 prefix = 0;
3060 if (i.prefix[DATA_PREFIX] != 0)
3061 {
3062 prefix = 1;
3063 i.prefixes -= 1;
3064 code16 ^= CODE16;
3065 }
3066 if (i.prefix[REX_PREFIX] != 0)
3067 {
3068 prefix++;
3069 i.prefixes -= 1;
3070 }
252b5132 3071
29b0f896
AM		 3072 size = 4;
3073 if (code16)
3074 size = 2;
252b5132 3075
29b0f896
AM		 3076 if (i.prefixes != 0 && !intel_syntax)
3077 as_warn (_("skipping prefixes on this instruction"));
252b5132 3078
29b0f896
AM		 3079 /* 1 opcode; 2 segment; offset */
3080 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3081
29b0f896
AM		 3082 if (i.prefix[DATA_PREFIX] != 0)
3083 *p++ = DATA_PREFIX_OPCODE;
252b5132 3084
29b0f896
AM		 3085 if (i.prefix[REX_PREFIX] != 0)
3086 *p++ = i.prefix[REX_PREFIX];
252b5132 3087
29b0f896
AM		 3088 *p++ = i.tm.base_opcode;
3089 if (i.op[1].imms->X_op == O_constant)
3090 {
3091 offsetT n = i.op[1].imms->X_add_number;
252b5132 3092
29b0f896
AM		 3093 if (size == 2
3094 && !fits_in_unsigned_word (n)
3095 && !fits_in_signed_word (n))
3096 {
3097 as_bad (_("16-bit jump out of range"));
3098 return;
3099 }
3100 md_number_to_chars (p, n, size);
3101 }
3102 else
3103 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3104 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3105 if (i.op[0].imms->X_op != O_constant)
3106 as_bad (_("can't handle non absolute segment in `%s'"),
3107 i.tm.name);
3108 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3109}
a217f122 3110
2bbd9c25 3111
29b0f896
AM		 3112static void
3113output_insn ()
3114{
2bbd9c25
JJ		 3115 fragS *insn_start_frag;
3116 offsetT insn_start_off;
3117
29b0f896
AM		 3118 /* Tie dwarf2 debug info to the address at the start of the insn.
3119 We can't do this after the insn has been output as the current
3120 frag may have been closed off. eg. by frag_var. */
3121 dwarf2_emit_insn (0);
3122
2bbd9c25
JJ		 3123 insn_start_frag = frag_now;
3124 insn_start_off = frag_now_fix ();
3125
29b0f896
AM		 3126 /* Output jumps. */
3127 if (i.tm.opcode_modifier & Jump)
3128 output_branch ();
3129 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3130 output_jump ();
3131 else if (i.tm.opcode_modifier & JumpInterSegment)
3132 output_interseg_jump ();
3133 else
3134 {
3135 /* Output normal instructions here. */
3136 char *p;
3137 unsigned char *q;
252b5132 3138
29b0f896
AM		 3139 /* All opcodes on i386 have either 1 or 2 bytes. We may use third
3140 byte for the SSE instructions to specify a prefix they require. */
3141 if (i.tm.base_opcode & 0xff0000)
3142 add_prefix ((i.tm.base_opcode >> 16) & 0xff);
252b5132 3143
29b0f896
AM		 3144 /* The prefix bytes. */
3145 for (q = i.prefix;
3146 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3147 q++)
3148 {
3149 if (*q)
3150 {
3151 p = frag_more (1);
3152 md_number_to_chars (p, (valueT) *q, 1);
3153 }
3154 }
252b5132 3155
29b0f896
AM		 3156 /* Now the opcode; be careful about word order here! */
3157 if (fits_in_unsigned_byte (i.tm.base_opcode))
3158 {
3159 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3160 }
3161 else
3162 {
3163 p = frag_more (2);
3164 /* Put out high byte first: can't use md_number_to_chars! */
3165 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3166 *p = i.tm.base_opcode & 0xff;
3167 }
3e73aa7c 3168
29b0f896
AM		 3169 /* Now the modrm byte and sib byte (if present). */
3170 if (i.tm.opcode_modifier & Modrm)
3171 {
3172 p = frag_more (1);
3173 md_number_to_chars (p,
3174 (valueT) (i.rm.regmem << 0
3175 | i.rm.reg << 3
3176 | i.rm.mode << 6),
3177 1);
3178 /* If i.rm.regmem == ESP (4)
3179 && i.rm.mode != (Register mode)
3180 && not 16 bit
3181 ==> need second modrm byte. */
3182 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3183 && i.rm.mode != 3
3184 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3185 {
3186 p = frag_more (1);
3187 md_number_to_chars (p,
3188 (valueT) (i.sib.base << 0
3189 | i.sib.index << 3
3190 | i.sib.scale << 6),
3191 1);
3192 }
3193 }
3e73aa7c 3194
29b0f896 3195 if (i.disp_operands)
2bbd9c25 3196 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 3197
29b0f896 3198 if (i.imm_operands)
2bbd9c25 3199 output_imm (insn_start_frag, insn_start_off);
29b0f896 3200 }
252b5132 3201
29b0f896
AM		 3202#ifdef DEBUG386
3203 if (flag_debug)
3204 {
3205 pi (line, &i);
3206 }
3207#endif /* DEBUG386 */
3208}
252b5132 3209
29b0f896 3210static void
2bbd9c25
JJ		 3211output_disp (insn_start_frag, insn_start_off)
3212 fragS *insn_start_frag;
3213 offsetT insn_start_off;
29b0f896
AM		 3214{
3215 char *p;
3216 unsigned int n;
252b5132 3217
29b0f896
AM		 3218 for (n = 0; n < i.operands; n++)
3219 {
3220 if (i.types[n] & Disp)
3221 {
3222 if (i.op[n].disps->X_op == O_constant)
3223 {
3224 int size;
3225 offsetT val;
252b5132 3226
29b0f896
AM		 3227 size = 4;
3228 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3229 {
3230 size = 2;
3231 if (i.types[n] & Disp8)
3232 size = 1;
3233 if (i.types[n] & Disp64)
3234 size = 8;
3235 }
3236 val = offset_in_range (i.op[n].disps->X_add_number,
3237 size);
3238 p = frag_more (size);
3239 md_number_to_chars (p, val, size);
3240 }
3241 else
3242 {
2bbd9c25 3243 RELOC_ENUM reloc_type;
29b0f896
AM		 3244 int size = 4;
3245 int sign = 0;
3246 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
3247
3248 /* The PC relative address is computed relative
3249 to the instruction boundary, so in case immediate
3250 fields follows, we need to adjust the value. */
3251 if (pcrel && i.imm_operands)
3252 {
3253 int imm_size = 4;
3254 unsigned int n1;
252b5132 3255
29b0f896
AM		 3256 for (n1 = 0; n1 < i.operands; n1++)
3257 if (i.types[n1] & Imm)
252b5132 3258 {
29b0f896 3259 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 3260 {
29b0f896
AM		 3261 imm_size = 2;
3262 if (i.types[n1] & (Imm8 | Imm8S))
3263 imm_size = 1;
3264 if (i.types[n1] & Imm64)
3265 imm_size = 8;
252b5132 3266 }
29b0f896 3267 break;
252b5132 3268 }
29b0f896
AM		 3269 /* We should find the immediate. */
3270 if (n1 == i.operands)
3271 abort ();
3272 i.op[n].disps->X_add_number -= imm_size;
3273 }
520dc8e8 3274
29b0f896
AM		 3275 if (i.types[n] & Disp32S)
3276 sign = 1;
3e73aa7c 3277
29b0f896
AM		 3278 if (i.types[n] & (Disp16 | Disp64))
3279 {
3280 size = 2;
3281 if (i.types[n] & Disp64)
3282 size = 8;
3283 }
520dc8e8 3284
29b0f896 3285 p = frag_more (size);
2bbd9c25
JJ		 3286 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
3287#ifdef BFD_ASSEMBLER
3288 if (reloc_type == BFD_RELOC_32
3289 && GOT_symbol
3290 && GOT_symbol == i.op[n].disps->X_add_symbol
3291 && (i.op[n].disps->X_op == O_symbol
3292 || (i.op[n].disps->X_op == O_add
3293 && ((symbol_get_value_expression
3294 (i.op[n].disps->X_op_symbol)->X_op)
3295 == O_subtract))))
3296 {
3297 offsetT add;
3298
3299 if (insn_start_frag == frag_now)
3300 add = (p - frag_now->fr_literal) - insn_start_off;
3301 else
3302 {
3303 fragS *fr;
3304
3305 add = insn_start_frag->fr_fix - insn_start_off;
3306 for (fr = insn_start_frag->fr_next;
3307 fr && fr != frag_now; fr = fr->fr_next)
3308 add += fr->fr_fix;
3309 add += p - frag_now->fr_literal;
3310 }
3311
3312 /* We don't support dynamic linking on x86-64 yet. */
3313 if (flag_code == CODE_64BIT)
3314 abort ();
3315 reloc_type = BFD_RELOC_386_GOTPC;
3316 i.op[n].disps->X_add_number += add;
3317 }
3318#endif
062cd5e7 3319 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 3320 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 3321 }
3322 }
3323 }
3324}
252b5132 3325
29b0f896 3326static void
2bbd9c25
JJ		 3327output_imm (insn_start_frag, insn_start_off)
3328 fragS *insn_start_frag;
3329 offsetT insn_start_off;
29b0f896
AM		 3330{
3331 char *p;
3332 unsigned int n;
252b5132 3333
29b0f896
AM		 3334 for (n = 0; n < i.operands; n++)
3335 {
3336 if (i.types[n] & Imm)
3337 {
3338 if (i.op[n].imms->X_op == O_constant)
3339 {
3340 int size;
3341 offsetT val;
b4cac588 3342
29b0f896
AM		 3343 size = 4;
3344 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3345 {
3346 size = 2;
3347 if (i.types[n] & (Imm8 | Imm8S))
3348 size = 1;
3349 else if (i.types[n] & Imm64)
3350 size = 8;
3351 }
3352 val = offset_in_range (i.op[n].imms->X_add_number,
3353 size);
3354 p = frag_more (size);
3355 md_number_to_chars (p, val, size);
3356 }
3357 else
3358 {
3359 /* Not absolute_section.
3360 Need a 32-bit fixup (don't support 8bit
3361 non-absolute imms). Try to support other
3362 sizes ... */
3363 RELOC_ENUM reloc_type;
3364 int size = 4;
3365 int sign = 0;
3366
3367 if ((i.types[n] & (Imm32S))
3368 && i.suffix == QWORD_MNEM_SUFFIX)
3369 sign = 1;
3370 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3371 {
3372 size = 2;
3373 if (i.types[n] & (Imm8 | Imm8S))
3374 size = 1;
3375 if (i.types[n] & Imm64)
3376 size = 8;
3377 }
520dc8e8 3378
29b0f896
AM		 3379 p = frag_more (size);
3380 reloc_type = reloc (size, 0, sign, i.reloc[n]);
252b5132 3381#ifdef BFD_ASSEMBLER
2bbd9c25
JJ		 3382 /* This is tough to explain. We end up with this one if we
3383 * have operands that look like
3384 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3385 * obtain the absolute address of the GOT, and it is strongly
3386 * preferable from a performance point of view to avoid using
3387 * a runtime relocation for this. The actual sequence of
3388 * instructions often look something like:
3389 *
3390 * call .L66
3391 * .L66:
3392 * popl %ebx
3393 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3394 *
3395 * The call and pop essentially return the absolute address
3396 * of the label .L66 and store it in %ebx. The linker itself
3397 * will ultimately change the first operand of the addl so
3398 * that %ebx points to the GOT, but to keep things simple, the
3399 * .o file must have this operand set so that it generates not
3400 * the absolute address of .L66, but the absolute address of
3401 * itself. This allows the linker itself simply treat a GOTPC
3402 * relocation as asking for a pcrel offset to the GOT to be
3403 * added in, and the addend of the relocation is stored in the
3404 * operand field for the instruction itself.
3405 *
3406 * Our job here is to fix the operand so that it would add
3407 * the correct offset so that %ebx would point to itself. The
3408 * thing that is tricky is that .-.L66 will point to the
3409 * beginning of the instruction, so we need to further modify
3410 * the operand so that it will point to itself. There are
3411 * other cases where you have something like:
3412 *
3413 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3414 *
3415 * and here no correction would be required. Internally in
3416 * the assembler we treat operands of this form as not being
3417 * pcrel since the '.' is explicitly mentioned, and I wonder
3418 * whether it would simplify matters to do it this way. Who
3419 * knows. In earlier versions of the PIC patches, the
3420 * pcrel_adjust field was used to store the correction, but
3421 * since the expression is not pcrel, I felt it would be
3422 * confusing to do it this way. */
3423
29b0f896
AM		 3424 if (reloc_type == BFD_RELOC_32
3425 && GOT_symbol
3426 && GOT_symbol == i.op[n].imms->X_add_symbol
3427 && (i.op[n].imms->X_op == O_symbol
3428 || (i.op[n].imms->X_op == O_add
3429 && ((symbol_get_value_expression
3430 (i.op[n].imms->X_op_symbol)->X_op)
3431 == O_subtract))))
3432 {
2bbd9c25
JJ		 3433 offsetT add;
3434
3435 if (insn_start_frag == frag_now)
3436 add = (p - frag_now->fr_literal) - insn_start_off;
3437 else
3438 {
3439 fragS *fr;
3440
3441 add = insn_start_frag->fr_fix - insn_start_off;
3442 for (fr = insn_start_frag->fr_next;
3443 fr && fr != frag_now; fr = fr->fr_next)
3444 add += fr->fr_fix;
3445 add += p - frag_now->fr_literal;
3446 }
3447
29b0f896
AM		 3448 /* We don't support dynamic linking on x86-64 yet. */
3449 if (flag_code == CODE_64BIT)
3450 abort ();
3451 reloc_type = BFD_RELOC_386_GOTPC;
2bbd9c25 3452 i.op[n].imms->X_add_number += add;
29b0f896 3453 }
252b5132 3454#endif
29b0f896
AM		 3455 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3456 i.op[n].imms, 0, reloc_type);
3457 }
3458 }
3459 }
252b5132
RH		 3460}
3461\f
f3c180ae
AM		 3462#ifndef LEX_AT
3463static char *lex_got PARAMS ((RELOC_ENUM *, int *));
3464
3465/* Parse operands of the form
3466 <symbol>@GOTOFF+<nnn>
3467 and similar .plt or .got references.
3468
3469 If we find one, set up the correct relocation in RELOC and copy the
3470 input string, minus the `@GOTOFF' into a malloc'd buffer for
3471 parsing by the calling routine. Return this buffer, and if ADJUST
3472 is non-null set it to the length of the string we removed from the
3473 input line. Otherwise return NULL. */
3474static char *
3475lex_got (reloc, adjust)
3476 RELOC_ENUM *reloc;
3477 int *adjust;
3478{
3479 static const char * const mode_name[NUM_FLAG_CODE] = { "32", "16", "64" };
3480 static const struct {
3481 const char *str;
3482 const RELOC_ENUM rel[NUM_FLAG_CODE];
3483 } gotrel[] = {
13ae64f3
JJ		 3484 { "PLT", { BFD_RELOC_386_PLT32, 0, BFD_RELOC_X86_64_PLT32 } },
3485 { "GOTOFF", { BFD_RELOC_386_GOTOFF, 0, 0 } },
3486 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL } },
3487 { "TLSGD", { BFD_RELOC_386_TLS_GD, 0, 0 } },
3488 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0, 0 } },
3489 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, 0, 0 } },
3490 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, 0, 0 } },
3491 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0, 0 } },
3492 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, 0, 0 } },
37e55690
JJ		 3493 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0, 0 } },
3494 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0, 0 } },
13ae64f3 3495 { "GOT", { BFD_RELOC_386_GOT32, 0, BFD_RELOC_X86_64_GOT32 } }
f3c180ae
AM		 3496 };
3497 char *cp;
3498 unsigned int j;
3499
3500 for (cp = input_line_pointer; *cp != '@'; cp++)
3501 if (is_end_of_line[(unsigned char) *cp])
3502 return NULL;
3503
3504 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
3505 {
3506 int len;
3507
3508 len = strlen (gotrel[j].str);
28f81592 3509 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae
AM		 3510 {
3511 if (gotrel[j].rel[(unsigned int) flag_code] != 0)
3512 {
28f81592
AM		 3513 int first, second;
3514 char *tmpbuf, *past_reloc;
f3c180ae
AM		 3515
3516 *reloc = gotrel[j].rel[(unsigned int) flag_code];
28f81592
AM		 3517 if (adjust)
3518 *adjust = len;
f3c180ae
AM		 3519
3520 if (GOT_symbol == NULL)
3521 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3522
3523 /* Replace the relocation token with ' ', so that
3524 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 3525
3526 /* The length of the first part of our input line. */
f3c180ae 3527 first = cp - input_line_pointer;
28f81592
AM		 3528
3529 /* The second part goes from after the reloc token until
3530 (and including) an end_of_line char. Don't use strlen
3531 here as the end_of_line char may not be a NUL. */
3532 past_reloc = cp + 1 + len;
3533 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
3534 ;
3535 second = cp - past_reloc;
3536
3537 /* Allocate and copy string. The trailing NUL shouldn't
3538 be necessary, but be safe. */
3539 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 3540 memcpy (tmpbuf, input_line_pointer, first);
3541 tmpbuf[first] = ' ';
28f81592
AM		 3542 memcpy (tmpbuf + first + 1, past_reloc, second);
3543 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 3544 return tmpbuf;
3545 }
3546
3547 as_bad (_("@%s reloc is not supported in %s bit mode"),
3548 gotrel[j].str, mode_name[(unsigned int) flag_code]);
3549 return NULL;
3550 }
3551 }
3552
3553 /* Might be a symbol version string. Don't as_bad here. */
3554 return NULL;
3555}
3556
3557/* x86_cons_fix_new is called via the expression parsing code when a
3558 reloc is needed. We use this hook to get the correct .got reloc. */
3559static RELOC_ENUM got_reloc = NO_RELOC;
3560
3561void
3562x86_cons_fix_new (frag, off, len, exp)
3563 fragS *frag;
3564 unsigned int off;
3565 unsigned int len;
3566 expressionS *exp;
3567{
3568 RELOC_ENUM r = reloc (len, 0, 0, got_reloc);
3569 got_reloc = NO_RELOC;
3570 fix_new_exp (frag, off, len, exp, 0, r);
3571}
3572
3573void
3574x86_cons (exp, size)
3575 expressionS *exp;
3576 int size;
3577{
3578 if (size == 4)
3579 {
3580 /* Handle @GOTOFF and the like in an expression. */
3581 char *save;
3582 char *gotfree_input_line;
3583 int adjust;
3584
3585 save = input_line_pointer;
3586 gotfree_input_line = lex_got (&got_reloc, &adjust);
3587 if (gotfree_input_line)
3588 input_line_pointer = gotfree_input_line;
3589
3590 expression (exp);
3591
3592 if (gotfree_input_line)
3593 {
3594 /* expression () has merrily parsed up to the end of line,
3595 or a comma - in the wrong buffer. Transfer how far
3596 input_line_pointer has moved to the right buffer. */
3597 input_line_pointer = (save
3598 + (input_line_pointer - gotfree_input_line)
3599 + adjust);
3600 free (gotfree_input_line);
3601 }
3602 }
3603 else
3604 expression (exp);
3605}
3606#endif
3607
252b5132
RH		 3608static int i386_immediate PARAMS ((char *));
3609
3610static int
3611i386_immediate (imm_start)
3612 char *imm_start;
3613{
3614 char *save_input_line_pointer;
f3c180ae
AM		 3615#ifndef LEX_AT
3616 char *gotfree_input_line;
3617#endif
252b5132 3618 segT exp_seg = 0;
47926f60 3619 expressionS *exp;
252b5132
RH		 3620
3621 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
3622 {
d0b47220 3623 as_bad (_("only 1 or 2 immediate operands are allowed"));
252b5132
RH		 3624 return 0;
3625 }
3626
3627 exp = &im_expressions[i.imm_operands++];
520dc8e8 3628 i.op[this_operand].imms = exp;
252b5132
RH		 3629
3630 if (is_space_char (*imm_start))
3631 ++imm_start;
3632
3633 save_input_line_pointer = input_line_pointer;
3634 input_line_pointer = imm_start;
3635
3636#ifndef LEX_AT
f3c180ae
AM		 3637 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3638 if (gotfree_input_line)
3639 input_line_pointer = gotfree_input_line;
252b5132
RH		 3640#endif
3641
3642 exp_seg = expression (exp);
3643
83183c0c 3644 SKIP_WHITESPACE ();
252b5132 3645 if (*input_line_pointer)
f3c180ae 3646 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 3647
3648 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 3649#ifndef LEX_AT
3650 if (gotfree_input_line)
3651 free (gotfree_input_line);
3652#endif
252b5132 3653
2daf4fd8 3654 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 3655 {
47926f60 3656 /* Missing or bad expr becomes absolute 0. */
d0b47220 3657 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 3658 imm_start);
252b5132
RH		 3659 exp->X_op = O_constant;
3660 exp->X_add_number = 0;
3661 exp->X_add_symbol = (symbolS *) 0;
3662 exp->X_op_symbol = (symbolS *) 0;
252b5132 3663 }
3e73aa7c 3664 else if (exp->X_op == O_constant)
252b5132 3665 {
47926f60 3666 /* Size it properly later. */
3e73aa7c
JH		 3667 i.types[this_operand] |= Imm64;
3668 /* If BFD64, sign extend val. */
3669 if (!use_rela_relocations)
3670 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
3671 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 3672 }
4c63da97 3673#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
47926f60 3674 else if (1
4c63da97 3675#ifdef BFD_ASSEMBLER
47926f60 3676 && OUTPUT_FLAVOR == bfd_target_aout_flavour
4c63da97 3677#endif
31312f95 3678 && exp_seg != absolute_section
47926f60 3679 && exp_seg != text_section
24eab124
AM		 3680 && exp_seg != data_section
3681 && exp_seg != bss_section
3682 && exp_seg != undefined_section
252b5132 3683#ifdef BFD_ASSEMBLER
24eab124 3684 && !bfd_is_com_section (exp_seg)
252b5132 3685#endif
24eab124 3686 )
252b5132 3687 {
4c63da97 3688#ifdef BFD_ASSEMBLER
d0b47220 3689 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4c63da97 3690#else
d0b47220 3691 as_bad (_("unimplemented segment type %d in operand"), exp_seg);
4c63da97 3692#endif
252b5132
RH		 3693 return 0;
3694 }
3695#endif
3696 else
3697 {
3698 /* This is an address. The size of the address will be
24eab124 3699 determined later, depending on destination register,
3e73aa7c
JH		 3700 suffix, or the default for the section. */
3701 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
252b5132
RH		 3702 }
3703
3704 return 1;
3705}
3706
551c1ca1 3707static char *i386_scale PARAMS ((char *));
252b5132 3708
551c1ca1 3709static char *
252b5132
RH		 3710i386_scale (scale)
3711 char *scale;
3712{
551c1ca1
AM		 3713 offsetT val;
3714 char *save = input_line_pointer;
252b5132 3715
551c1ca1
AM		 3716 input_line_pointer = scale;
3717 val = get_absolute_expression ();
3718
3719 switch (val)
252b5132 3720 {
551c1ca1
AM		 3721 case 0:
3722 case 1:
252b5132
RH		 3723 i.log2_scale_factor = 0;
3724 break;
551c1ca1 3725 case 2:
252b5132
RH		 3726 i.log2_scale_factor = 1;
3727 break;
551c1ca1 3728 case 4:
252b5132
RH		 3729 i.log2_scale_factor = 2;
3730 break;
551c1ca1 3731 case 8:
252b5132
RH		 3732 i.log2_scale_factor = 3;
3733 break;
3734 default:
252b5132 3735 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
24eab124 3736 scale);
551c1ca1
AM		 3737 input_line_pointer = save;
3738 return NULL;
252b5132 3739 }
29b0f896 3740 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 3741 {
3742 as_warn (_("scale factor of %d without an index register"),
24eab124 3743 1 << i.log2_scale_factor);
252b5132
RH		 3744#if SCALE1_WHEN_NO_INDEX
3745 i.log2_scale_factor = 0;
3746#endif
3747 }
551c1ca1
AM		 3748 scale = input_line_pointer;
3749 input_line_pointer = save;
3750 return scale;
252b5132
RH		 3751}
3752
3753static int i386_displacement PARAMS ((char *, char *));
3754
3755static int
3756i386_displacement (disp_start, disp_end)
3757 char *disp_start;
3758 char *disp_end;
3759{
29b0f896 3760 expressionS *exp;
252b5132
RH		 3761 segT exp_seg = 0;
3762 char *save_input_line_pointer;
f3c180ae
AM		 3763#ifndef LEX_AT
3764 char *gotfree_input_line;
3765#endif
252b5132
RH		 3766 int bigdisp = Disp32;
3767
3e73aa7c 3768 if (flag_code == CODE_64BIT)
7ecd2f8b 3769 {
29b0f896
AM		 3770 if (i.prefix[ADDR_PREFIX] == 0)
3771 bigdisp = Disp64;
7ecd2f8b
JH		 3772 }
3773 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3774 bigdisp = Disp16;
252b5132
RH		 3775 i.types[this_operand] |= bigdisp;
3776
3777 exp = &disp_expressions[i.disp_operands];
520dc8e8 3778 i.op[this_operand].disps = exp;
252b5132
RH		 3779 i.disp_operands++;
3780 save_input_line_pointer = input_line_pointer;
3781 input_line_pointer = disp_start;
3782 END_STRING_AND_SAVE (disp_end);
3783
3784#ifndef GCC_ASM_O_HACK
3785#define GCC_ASM_O_HACK 0
3786#endif
3787#if GCC_ASM_O_HACK
3788 END_STRING_AND_SAVE (disp_end + 1);
3789 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 3790 && displacement_string_end[-1] == '+')
252b5132
RH		 3791 {
3792 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 3793 constraint within gcc asm statements.
3794 For instance:
3795
3796 #define _set_tssldt_desc(n,addr,limit,type) \
3797 __asm__ __volatile__ ( \
3798 "movw %w2,%0\n\t" \
3799 "movw %w1,2+%0\n\t" \
3800 "rorl $16,%1\n\t" \
3801 "movb %b1,4+%0\n\t" \
3802 "movb %4,5+%0\n\t" \
3803 "movb $0,6+%0\n\t" \
3804 "movb %h1,7+%0\n\t" \
3805 "rorl $16,%1" \
3806 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3807
3808 This works great except that the output assembler ends
3809 up looking a bit weird if it turns out that there is
3810 no offset. You end up producing code that looks like:
3811
3812 #APP
3813 movw $235,(%eax)
3814 movw %dx,2+(%eax)
3815 rorl $16,%edx
3816 movb %dl,4+(%eax)
3817 movb $137,5+(%eax)
3818 movb $0,6+(%eax)
3819 movb %dh,7+(%eax)
3820 rorl $16,%edx
3821 #NO_APP
3822
47926f60 3823 So here we provide the missing zero. */
24eab124
AM		 3824
3825 *displacement_string_end = '0';
252b5132
RH		 3826 }
3827#endif
3828#ifndef LEX_AT
f3c180ae
AM		 3829 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3830 if (gotfree_input_line)
3831 input_line_pointer = gotfree_input_line;
252b5132
RH		 3832#endif
3833
24eab124 3834 exp_seg = expression (exp);
252b5132 3835
636c26b0
AM		 3836 SKIP_WHITESPACE ();
3837 if (*input_line_pointer)
3838 as_bad (_("junk `%s' after expression"), input_line_pointer);
3839#if GCC_ASM_O_HACK
3840 RESTORE_END_STRING (disp_end + 1);
3841#endif
3842 RESTORE_END_STRING (disp_end);
3843 input_line_pointer = save_input_line_pointer;
3844#ifndef LEX_AT
3845 if (gotfree_input_line)
3846 free (gotfree_input_line);
3847#endif
3848
252b5132 3849#ifdef BFD_ASSEMBLER
24eab124
AM		 3850 /* We do this to make sure that the section symbol is in
3851 the symbol table. We will ultimately change the relocation
47926f60 3852 to be relative to the beginning of the section. */
1ae12ab7
AM		 3853 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
3854 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
24eab124 3855 {
636c26b0
AM		 3856 if (exp->X_op != O_symbol)
3857 {
3858 as_bad (_("bad expression used with @%s"),
3859 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
3860 ? "GOTPCREL"
3861 : "GOTOFF"));
3862 return 0;
3863 }
3864
e5cb08ac 3865 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 3866 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
3867 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 3868 exp->X_op = O_subtract;
3869 exp->X_op_symbol = GOT_symbol;
1ae12ab7 3870 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 3871 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
23df1078 3872 else
29b0f896 3873 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 3874 }
252b5132
RH		 3875#endif
3876
2daf4fd8
AM		 3877 if (exp->X_op == O_absent || exp->X_op == O_big)
3878 {
47926f60 3879 /* Missing or bad expr becomes absolute 0. */
d0b47220 3880 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 3881 disp_start);
3882 exp->X_op = O_constant;
3883 exp->X_add_number = 0;
3884 exp->X_add_symbol = (symbolS *) 0;
3885 exp->X_op_symbol = (symbolS *) 0;
3886 }
3887
4c63da97 3888#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 3889 if (exp->X_op != O_constant
4c63da97 3890#ifdef BFD_ASSEMBLER
45288df1 3891 && OUTPUT_FLAVOR == bfd_target_aout_flavour
4c63da97 3892#endif
31312f95 3893 && exp_seg != absolute_section
45288df1
AM		 3894 && exp_seg != text_section
3895 && exp_seg != data_section
3896 && exp_seg != bss_section
31312f95
AM		 3897 && exp_seg != undefined_section
3898#ifdef BFD_ASSEMBLER
3899 && !bfd_is_com_section (exp_seg)
3900#endif
3901 )
24eab124 3902 {
4c63da97 3903#ifdef BFD_ASSEMBLER
d0b47220 3904 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4c63da97 3905#else
d0b47220 3906 as_bad (_("unimplemented segment type %d in operand"), exp_seg);
4c63da97 3907#endif
24eab124
AM		 3908 return 0;
3909 }
252b5132 3910#endif
3e73aa7c
JH		 3911 else if (flag_code == CODE_64BIT)
3912 i.types[this_operand] |= Disp32S | Disp32;
252b5132
RH		 3913 return 1;
3914}
3915
e5cb08ac 3916static int i386_index_check PARAMS ((const char *));
252b5132 3917
eecb386c 3918/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 3919 Return 1 on success, 0 on a failure. */
3920
252b5132 3921static int
eecb386c
AM		 3922i386_index_check (operand_string)
3923 const char *operand_string;
252b5132 3924{
3e73aa7c 3925 int ok;
24eab124 3926#if INFER_ADDR_PREFIX
eecb386c
AM		 3927 int fudged = 0;
3928
24eab124
AM		 3929 tryprefix:
3930#endif
3e73aa7c
JH		 3931 ok = 1;
3932 if (flag_code == CODE_64BIT)
3933 {
7ecd2f8b
JH		 3934 if (i.prefix[ADDR_PREFIX] == 0)
3935 {
3936 /* 64bit checks. */
3937 if ((i.base_reg
3938 && ((i.base_reg->reg_type & Reg64) == 0)
3939 && (i.base_reg->reg_type != BaseIndex
3940 || i.index_reg))
3941 || (i.index_reg
29b0f896
AM		 3942 && ((i.index_reg->reg_type & (Reg64 | BaseIndex))
3943 != (Reg64 | BaseIndex))))
7ecd2f8b
JH		 3944 ok = 0;
3945 }
3946 else
3947 {
3948 /* 32bit checks. */
3949 if ((i.base_reg
3950 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
3951 || (i.index_reg
29b0f896
AM		 3952 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
3953 != (Reg32 | BaseIndex))))
7ecd2f8b
JH		 3954 ok = 0;
3955 }
3e73aa7c
JH		 3956 }
3957 else
3958 {
3959 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3960 {
3961 /* 16bit checks. */
3962 if ((i.base_reg
29b0f896
AM		 3963 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
3964 != (Reg16 | BaseIndex)))
3e73aa7c 3965 || (i.index_reg
29b0f896
AM		 3966 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
3967 != (Reg16 | BaseIndex))
3968 || !(i.base_reg
3969 && i.base_reg->reg_num < 6
3970 && i.index_reg->reg_num >= 6
3971 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 3972 ok = 0;
3973 }
3974 else
e5cb08ac 3975 {
3e73aa7c
JH		 3976 /* 32bit checks. */
3977 if ((i.base_reg
3978 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
3979 || (i.index_reg
29b0f896
AM		 3980 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
3981 != (Reg32 | BaseIndex))))
e5cb08ac 3982 ok = 0;
3e73aa7c
JH		 3983 }
3984 }
3985 if (!ok)
24eab124
AM		 3986 {
3987#if INFER_ADDR_PREFIX
3e73aa7c
JH		 3988 if (flag_code != CODE_64BIT
3989 && i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0')
24eab124
AM		 3990 {
3991 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
3992 i.prefixes += 1;
b23bac36
AM		 3993 /* Change the size of any displacement too. At most one of
3994 Disp16 or Disp32 is set.
3995 FIXME. There doesn't seem to be any real need for separate
3996 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 3997 Removing them would probably clean up the code quite a lot. */
29b0f896
AM		 3998 if (i.types[this_operand] & (Disp16 | Disp32))
3999 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 4000 fudged = 1;
24eab124
AM		 4001 goto tryprefix;
4002 }
eecb386c
AM		 4003 if (fudged)
4004 as_bad (_("`%s' is not a valid base/index expression"),
4005 operand_string);
4006 else
c388dee8 4007#endif
eecb386c
AM		 4008 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4009 operand_string,
3e73aa7c 4010 flag_code_names[flag_code]);
eecb386c 4011 return 0;
24eab124
AM		 4012 }
4013 return 1;
4014}
252b5132 4015
252b5132 4016/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 4017 on error. */
252b5132 4018
252b5132
RH		 4019static int
4020i386_operand (operand_string)
4021 char *operand_string;
4022{
af6bdddf
AM		 4023 const reg_entry *r;
4024 char *end_op;
24eab124 4025 char *op_string = operand_string;
252b5132 4026
24eab124 4027 if (is_space_char (*op_string))
252b5132
RH		 4028 ++op_string;
4029
24eab124 4030 /* We check for an absolute prefix (differentiating,
47926f60 4031 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 4032 if (*op_string == ABSOLUTE_PREFIX)
4033 {
4034 ++op_string;
4035 if (is_space_char (*op_string))
4036 ++op_string;
4037 i.types[this_operand] |= JumpAbsolute;
4038 }
252b5132 4039
47926f60 4040 /* Check if operand is a register. */
af6bdddf
AM		 4041 if ((*op_string == REGISTER_PREFIX || allow_naked_reg)
4042 && (r = parse_register (op_string, &end_op)) != NULL)
24eab124 4043 {
24eab124
AM		 4044 /* Check for a segment override by searching for ':' after a
4045 segment register. */
4046 op_string = end_op;
4047 if (is_space_char (*op_string))
4048 ++op_string;
4049 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4050 {
4051 switch (r->reg_num)
4052 {
4053 case 0:
4054 i.seg[i.mem_operands] = &es;
4055 break;
4056 case 1:
4057 i.seg[i.mem_operands] = &cs;
4058 break;
4059 case 2:
4060 i.seg[i.mem_operands] = &ss;
4061 break;
4062 case 3:
4063 i.seg[i.mem_operands] = &ds;
4064 break;
4065 case 4:
4066 i.seg[i.mem_operands] = &fs;
4067 break;
4068 case 5:
4069 i.seg[i.mem_operands] = &gs;
4070 break;
4071 }
252b5132 4072
24eab124 4073 /* Skip the ':' and whitespace. */
252b5132
RH		 4074 ++op_string;
4075 if (is_space_char (*op_string))
24eab124 4076 ++op_string;
252b5132 4077
24eab124
AM		 4078 if (!is_digit_char (*op_string)
4079 && !is_identifier_char (*op_string)
4080 && *op_string != '('
4081 && *op_string != ABSOLUTE_PREFIX)
4082 {
4083 as_bad (_("bad memory operand `%s'"), op_string);
4084 return 0;
4085 }
47926f60 4086 /* Handle case of %es:*foo. */
24eab124
AM		 4087 if (*op_string == ABSOLUTE_PREFIX)
4088 {
4089 ++op_string;
4090 if (is_space_char (*op_string))
4091 ++op_string;
4092 i.types[this_operand] |= JumpAbsolute;
4093 }
4094 goto do_memory_reference;
4095 }
4096 if (*op_string)
4097 {
d0b47220 4098 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 4099 return 0;
4100 }
4101 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 4102 i.op[this_operand].regs = r;
24eab124
AM		 4103 i.reg_operands++;
4104 }
af6bdddf
AM		 4105 else if (*op_string == REGISTER_PREFIX)
4106 {
4107 as_bad (_("bad register name `%s'"), op_string);
4108 return 0;
4109 }
24eab124 4110 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 4111 {
24eab124
AM		 4112 ++op_string;
4113 if (i.types[this_operand] & JumpAbsolute)
4114 {
d0b47220 4115 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 4116 return 0;
4117 }
4118 if (!i386_immediate (op_string))
4119 return 0;
4120 }
4121 else if (is_digit_char (*op_string)
4122 || is_identifier_char (*op_string)
e5cb08ac 4123 || *op_string == '(')
24eab124 4124 {
47926f60 4125 /* This is a memory reference of some sort. */
af6bdddf 4126 char *base_string;
252b5132 4127
47926f60 4128 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 4129 char *displacement_string_start;
4130 char *displacement_string_end;
252b5132 4131
24eab124 4132 do_memory_reference:
24eab124
AM		 4133 if ((i.mem_operands == 1
4134 && (current_templates->start->opcode_modifier & IsString) == 0)
4135 || i.mem_operands == 2)
4136 {
4137 as_bad (_("too many memory references for `%s'"),
4138 current_templates->start->name);
4139 return 0;
4140 }
252b5132 4141
24eab124
AM		 4142 /* Check for base index form. We detect the base index form by
4143 looking for an ')' at the end of the operand, searching
4144 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4145 after the '('. */
af6bdddf 4146 base_string = op_string + strlen (op_string);
c3332e24 4147
af6bdddf
AM		 4148 --base_string;
4149 if (is_space_char (*base_string))
4150 --base_string;
252b5132 4151
47926f60 4152 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 4153 displacement_string_start = op_string;
4154 displacement_string_end = base_string + 1;
252b5132 4155
24eab124
AM		 4156 if (*base_string == ')')
4157 {
af6bdddf 4158 char *temp_string;
24eab124
AM		 4159 unsigned int parens_balanced = 1;
4160 /* We've already checked that the number of left & right ()'s are
47926f60 4161 equal, so this loop will not be infinite. */
24eab124
AM		 4162 do
4163 {
4164 base_string--;
4165 if (*base_string == ')')
4166 parens_balanced++;
4167 if (*base_string == '(')
4168 parens_balanced--;
4169 }
4170 while (parens_balanced);
c3332e24 4171
af6bdddf 4172 temp_string = base_string;
c3332e24 4173
24eab124 4174 /* Skip past '(' and whitespace. */
252b5132
RH		 4175 ++base_string;
4176 if (is_space_char (*base_string))
24eab124 4177 ++base_string;
252b5132 4178
af6bdddf
AM		 4179 if (*base_string == ','
4180 || ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4181 && (i.base_reg = parse_register (base_string, &end_op)) != NULL))
252b5132 4182 {
af6bdddf 4183 displacement_string_end = temp_string;
252b5132 4184
af6bdddf 4185 i.types[this_operand] |= BaseIndex;
252b5132 4186
af6bdddf 4187 if (i.base_reg)
24eab124 4188 {
24eab124
AM		 4189 base_string = end_op;
4190 if (is_space_char (*base_string))
4191 ++base_string;
af6bdddf
AM		 4192 }
4193
4194 /* There may be an index reg or scale factor here. */
4195 if (*base_string == ',')
4196 {
4197 ++base_string;
4198 if (is_space_char (*base_string))
4199 ++base_string;
4200
4201 if ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4202 && (i.index_reg = parse_register (base_string, &end_op)) != NULL)
24eab124 4203 {
af6bdddf 4204 base_string = end_op;
24eab124
AM		 4205 if (is_space_char (*base_string))
4206 ++base_string;
af6bdddf
AM		 4207 if (*base_string == ',')
4208 {
4209 ++base_string;
4210 if (is_space_char (*base_string))
4211 ++base_string;
4212 }
e5cb08ac 4213 else if (*base_string != ')')
af6bdddf
AM		 4214 {
4215 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4216 operand_string);
4217 return 0;
4218 }
24eab124 4219 }
af6bdddf 4220 else if (*base_string == REGISTER_PREFIX)
24eab124 4221 {
af6bdddf 4222 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 4223 return 0;
4224 }
252b5132 4225
47926f60 4226 /* Check for scale factor. */
551c1ca1 4227 if (*base_string != ')')
af6bdddf 4228 {
551c1ca1
AM		 4229 char *end_scale = i386_scale (base_string);
4230
4231 if (!end_scale)
af6bdddf 4232 return 0;
24eab124 4233
551c1ca1 4234 base_string = end_scale;
af6bdddf
AM		 4235 if (is_space_char (*base_string))
4236 ++base_string;
4237 if (*base_string != ')')
4238 {
4239 as_bad (_("expecting `)' after scale factor in `%s'"),
4240 operand_string);
4241 return 0;
4242 }
4243 }
4244 else if (!i.index_reg)
24eab124 4245 {
af6bdddf
AM		 4246 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4247 *base_string);
24eab124
AM		 4248 return 0;
4249 }
4250 }
af6bdddf 4251 else if (*base_string != ')')
24eab124 4252 {
af6bdddf
AM		 4253 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4254 operand_string);
24eab124
AM		 4255 return 0;
4256 }
c3332e24 4257 }
af6bdddf 4258 else if (*base_string == REGISTER_PREFIX)
c3332e24 4259 {
af6bdddf 4260 as_bad (_("bad register name `%s'"), base_string);
24eab124 4261 return 0;
c3332e24 4262 }
24eab124
AM		 4263 }
4264
4265 /* If there's an expression beginning the operand, parse it,
4266 assuming displacement_string_start and
4267 displacement_string_end are meaningful. */
4268 if (displacement_string_start != displacement_string_end)
4269 {
4270 if (!i386_displacement (displacement_string_start,
4271 displacement_string_end))
4272 return 0;
4273 }
4274
4275 /* Special case for (%dx) while doing input/output op. */
4276 if (i.base_reg
4277 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
4278 && i.index_reg == 0
4279 && i.log2_scale_factor == 0
4280 && i.seg[i.mem_operands] == 0
4281 && (i.types[this_operand] & Disp) == 0)
4282 {
4283 i.types[this_operand] = InOutPortReg;
4284 return 1;
4285 }
4286
eecb386c
AM		 4287 if (i386_index_check (operand_string) == 0)
4288 return 0;
24eab124
AM		 4289 i.mem_operands++;
4290 }
4291 else
ce8a8b2f
AM		 4292 {
4293 /* It's not a memory operand; argh! */
24eab124
AM		 4294 as_bad (_("invalid char %s beginning operand %d `%s'"),
4295 output_invalid (*op_string),
4296 this_operand + 1,
4297 op_string);
4298 return 0;
4299 }
47926f60 4300 return 1; /* Normal return. */
252b5132
RH		 4301}
4302\f
ee7fcc42
AM		 4303/* md_estimate_size_before_relax()
4304
4305 Called just before relax() for rs_machine_dependent frags. The x86
4306 assembler uses these frags to handle variable size jump
4307 instructions.
4308
4309 Any symbol that is now undefined will not become defined.
4310 Return the correct fr_subtype in the frag.
4311 Return the initial "guess for variable size of frag" to caller.
4312 The guess is actually the growth beyond the fixed part. Whatever
4313 we do to grow the fixed or variable part contributes to our
4314 returned value. */
4315
252b5132
RH		 4316int
4317md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 4318 fragS *fragP;
4319 segT segment;
252b5132 4320{
252b5132 4321 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 4322 check for un-relaxable symbols. On an ELF system, we can't relax
4323 an externally visible symbol, because it may be overridden by a
4324 shared library. */
4325 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 4326#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
31312f95
AM		 4327 || (OUTPUT_FLAVOR == bfd_target_elf_flavour
4328 && (S_IS_EXTERNAL (fragP->fr_symbol)
4329 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 4330#endif
4331 )
252b5132 4332 {
b98ef147
AM		 4333 /* Symbol is undefined in this segment, or we need to keep a
4334 reloc so that weak symbols can be overridden. */
4335 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f3c180ae 4336 RELOC_ENUM reloc_type;
ee7fcc42
AM		 4337 unsigned char *opcode;
4338 int old_fr_fix;
f6af82bd 4339
ee7fcc42
AM		 4340 if (fragP->fr_var != NO_RELOC)
4341 reloc_type = fragP->fr_var;
b98ef147 4342 else if (size == 2)
f6af82bd
AM		 4343 reloc_type = BFD_RELOC_16_PCREL;
4344 else
4345 reloc_type = BFD_RELOC_32_PCREL;
252b5132 4346
ee7fcc42
AM		 4347 old_fr_fix = fragP->fr_fix;
4348 opcode = (unsigned char *) fragP->fr_opcode;
4349
fddf5b5b 4350 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 4351 {
fddf5b5b
AM		 4352 case UNCOND_JUMP:
4353 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 4354 opcode[0] = 0xe9;
252b5132 4355 fragP->fr_fix += size;
062cd5e7
AS		 4356 fix_new (fragP, old_fr_fix, size,
4357 fragP->fr_symbol,
4358 fragP->fr_offset, 1,
4359 reloc_type);
252b5132
RH		 4360 break;
4361
fddf5b5b 4362 case COND_JUMP86:
412167cb
AM		 4363 if (size == 2
4364 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 4365 {
4366 /* Negate the condition, and branch past an
4367 unconditional jump. */
4368 opcode[0] ^= 1;
4369 opcode[1] = 3;
4370 /* Insert an unconditional jump. */
4371 opcode[2] = 0xe9;
4372 /* We added two extra opcode bytes, and have a two byte
4373 offset. */
4374 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 4375 fix_new (fragP, old_fr_fix + 2, 2,
4376 fragP->fr_symbol,
4377 fragP->fr_offset, 1,
4378 reloc_type);
fddf5b5b
AM		 4379 break;
4380 }
4381 /* Fall through. */
4382
4383 case COND_JUMP:
412167cb
AM		 4384 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
4385 {
4386 fragP->fr_fix += 1;
4387 fix_new (fragP, old_fr_fix, 1,
4388 fragP->fr_symbol,
4389 fragP->fr_offset, 1,
4390 BFD_RELOC_8_PCREL);
4391 break;
4392 }
93c2a809 4393
24eab124 4394 /* This changes the byte-displacement jump 0x7N
fddf5b5b 4395 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 4396 opcode[1] = opcode[0] + 0x10;
f6af82bd 4397 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 4398 /* We've added an opcode byte. */
4399 fragP->fr_fix += 1 + size;
062cd5e7
AS		 4400 fix_new (fragP, old_fr_fix + 1, size,
4401 fragP->fr_symbol,
4402 fragP->fr_offset, 1,
4403 reloc_type);
252b5132 4404 break;
fddf5b5b
AM		 4405
4406 default:
4407 BAD_CASE (fragP->fr_subtype);
4408 break;
252b5132
RH		 4409 }
4410 frag_wane (fragP);
ee7fcc42 4411 return fragP->fr_fix - old_fr_fix;
252b5132 4412 }
93c2a809 4413
93c2a809
AM		 4414 /* Guess size depending on current relax state. Initially the relax
4415 state will correspond to a short jump and we return 1, because
4416 the variable part of the frag (the branch offset) is one byte
4417 long. However, we can relax a section more than once and in that
4418 case we must either set fr_subtype back to the unrelaxed state,
4419 or return the value for the appropriate branch. */
4420 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 4421}
4422
47926f60
KH		 4423/* Called after relax() is finished.
4424
4425 In: Address of frag.
4426 fr_type == rs_machine_dependent.
4427 fr_subtype is what the address relaxed to.
4428
4429 Out: Any fixSs and constants are set up.
4430 Caller will turn frag into a ".space 0". */
4431
252b5132
RH		 4432#ifndef BFD_ASSEMBLER
4433void
4434md_convert_frag (headers, sec, fragP)
a04b544b
ILT		 4435 object_headers *headers ATTRIBUTE_UNUSED;
4436 segT sec ATTRIBUTE_UNUSED;
29b0f896 4437 fragS *fragP;
252b5132
RH		 4438#else
4439void
4440md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 4441 bfd *abfd ATTRIBUTE_UNUSED;
4442 segT sec ATTRIBUTE_UNUSED;
29b0f896 4443 fragS *fragP;
252b5132
RH		 4444#endif
4445{
29b0f896 4446 unsigned char *opcode;
252b5132 4447 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 4448 offsetT target_address;
4449 offsetT opcode_address;
252b5132 4450 unsigned int extension = 0;
847f7ad4 4451 offsetT displacement_from_opcode_start;
252b5132
RH		 4452
4453 opcode = (unsigned char *) fragP->fr_opcode;
4454
47926f60 4455 /* Address we want to reach in file space. */
252b5132 4456 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 4457
47926f60 4458 /* Address opcode resides at in file space. */
252b5132
RH		 4459 opcode_address = fragP->fr_address + fragP->fr_fix;
4460
47926f60 4461 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 4462 displacement_from_opcode_start = target_address - opcode_address;
4463
fddf5b5b 4464 if ((fragP->fr_subtype & BIG) == 0)
252b5132 4465 {
47926f60
KH		 4466 /* Don't have to change opcode. */
4467 extension = 1; /* 1 opcode + 1 displacement */
252b5132 4468 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 4469 }
4470 else
4471 {
4472 if (no_cond_jump_promotion
4473 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4474 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
252b5132 4475
fddf5b5b
AM		 4476 switch (fragP->fr_subtype)
4477 {
4478 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
4479 extension = 4; /* 1 opcode + 4 displacement */
4480 opcode[0] = 0xe9;
4481 where_to_put_displacement = &opcode[1];
4482 break;
252b5132 4483
fddf5b5b
AM		 4484 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
4485 extension = 2; /* 1 opcode + 2 displacement */
4486 opcode[0] = 0xe9;
4487 where_to_put_displacement = &opcode[1];
4488 break;
252b5132 4489
fddf5b5b
AM		 4490 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
4491 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
4492 extension = 5; /* 2 opcode + 4 displacement */
4493 opcode[1] = opcode[0] + 0x10;
4494 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4495 where_to_put_displacement = &opcode[2];
4496 break;
252b5132 4497
fddf5b5b
AM		 4498 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
4499 extension = 3; /* 2 opcode + 2 displacement */
4500 opcode[1] = opcode[0] + 0x10;
4501 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4502 where_to_put_displacement = &opcode[2];
4503 break;
252b5132 4504
fddf5b5b
AM		 4505 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
4506 extension = 4;
4507 opcode[0] ^= 1;
4508 opcode[1] = 3;
4509 opcode[2] = 0xe9;
4510 where_to_put_displacement = &opcode[3];
4511 break;
4512
4513 default:
4514 BAD_CASE (fragP->fr_subtype);
4515 break;
4516 }
252b5132 4517 }
fddf5b5b 4518
47926f60 4519 /* Now put displacement after opcode. */
252b5132
RH		 4520 md_number_to_chars ((char *) where_to_put_displacement,
4521 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 4522 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 4523 fragP->fr_fix += extension;
4524}
4525\f
47926f60
KH		 4526/* Size of byte displacement jmp. */
4527int md_short_jump_size = 2;
4528
4529/* Size of dword displacement jmp. */
4530int md_long_jump_size = 5;
252b5132 4531
47926f60
KH		 4532/* Size of relocation record. */
4533const int md_reloc_size = 8;
252b5132
RH		 4534
4535void
4536md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4537 char *ptr;
4538 addressT from_addr, to_addr;
ab9da554
ILT		 4539 fragS *frag ATTRIBUTE_UNUSED;
4540 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4541{
847f7ad4 4542 offsetT offset;
252b5132
RH		 4543
4544 offset = to_addr - (from_addr + 2);
47926f60
KH		 4545 /* Opcode for byte-disp jump. */
4546 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 4547 md_number_to_chars (ptr + 1, (valueT) offset, 1);
4548}
4549
4550void
4551md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4552 char *ptr;
4553 addressT from_addr, to_addr;
a38cf1db
AM		 4554 fragS *frag ATTRIBUTE_UNUSED;
4555 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4556{
847f7ad4 4557 offsetT offset;
252b5132 4558
a38cf1db
AM		 4559 offset = to_addr - (from_addr + 5);
4560 md_number_to_chars (ptr, (valueT) 0xe9, 1);
4561 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 4562}
4563\f
4564/* Apply a fixup (fixS) to segment data, once it has been determined
4565 by our caller that we have all the info we need to fix it up.
4566
4567 On the 386, immediates, displacements, and data pointers are all in
4568 the same (little-endian) format, so we don't need to care about which
4569 we are handling. */
4570
94f592af
NC		 4571void
4572md_apply_fix3 (fixP, valP, seg)
47926f60
KH		 4573 /* The fix we're to put in. */
4574 fixS *fixP;
47926f60 4575 /* Pointer to the value of the bits. */
c6682705 4576 valueT *valP;
47926f60
KH		 4577 /* Segment fix is from. */
4578 segT seg ATTRIBUTE_UNUSED;
252b5132 4579{
94f592af 4580 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 4581 valueT value = *valP;
252b5132 4582
e1b283bb 4583#if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
93382f6d
AM		 4584 if (fixP->fx_pcrel)
4585 {
4586 switch (fixP->fx_r_type)
4587 {
5865bb77
ILT		 4588 default:
4589 break;
4590
93382f6d
AM		 4591 case BFD_RELOC_32:
4592 fixP->fx_r_type = BFD_RELOC_32_PCREL;
4593 break;
4594 case BFD_RELOC_16:
4595 fixP->fx_r_type = BFD_RELOC_16_PCREL;
4596 break;
4597 case BFD_RELOC_8:
4598 fixP->fx_r_type = BFD_RELOC_8_PCREL;
4599 break;
4600 }
4601 }
252b5132 4602
a161fe53 4603 if (fixP->fx_addsy != NULL
31312f95
AM		 4604 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
4605 || fixP->fx_r_type == BFD_RELOC_16_PCREL
4606 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4607 && !use_rela_relocations)
252b5132 4608 {
31312f95
AM		 4609 /* This is a hack. There should be a better way to handle this.
4610 This covers for the fact that bfd_install_relocation will
4611 subtract the current location (for partial_inplace, PC relative
4612 relocations); see more below. */
252b5132
RH		 4613#ifndef OBJ_AOUT
4614 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4615#ifdef TE_PE
4616 || OUTPUT_FLAVOR == bfd_target_coff_flavour
4617#endif
4618 )
4619 value += fixP->fx_where + fixP->fx_frag->fr_address;
4620#endif
4621#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2f66722d 4622 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
252b5132 4623 {
6539b54b 4624 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 4625
6539b54b 4626 if ((sym_seg == seg
2f66722d 4627 || (symbol_section_p (fixP->fx_addsy)
6539b54b
AM		 4628 && sym_seg != absolute_section))
4629 && !S_FORCE_RELOC (fixP->fx_addsy))
2f66722d
AM		 4630 {
4631 /* Yes, we add the values in twice. This is because
6539b54b
AM		 4632 bfd_install_relocation subtracts them out again. I think
4633 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 4634 it. FIXME. */
4635 value += fixP->fx_where + fixP->fx_frag->fr_address;
4636 }
252b5132
RH		 4637 }
4638#endif
4639#if defined (OBJ_COFF) && defined (TE_PE)
4640 /* For some reason, the PE format does not store a section
24eab124 4641 address offset for a PC relative symbol. */
252b5132
RH		 4642 if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
4643 value += md_pcrel_from (fixP);
4644#endif
4645 }
4646
4647 /* Fix a few things - the dynamic linker expects certain values here,
47926f60 4648 and we must not dissappoint it. */
252b5132
RH		 4649#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4650 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4651 && fixP->fx_addsy)
47926f60
KH		 4652 switch (fixP->fx_r_type)
4653 {
4654 case BFD_RELOC_386_PLT32:
3e73aa7c 4655 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 4656 /* Make the jump instruction point to the address of the operand. At
4657 runtime we merely add the offset to the actual PLT entry. */
4658 value = -4;
4659 break;
31312f95 4660
47926f60 4661 case BFD_RELOC_386_GOT32:
13ae64f3
JJ		 4662 case BFD_RELOC_386_TLS_GD:
4663 case BFD_RELOC_386_TLS_LDM:
13ae64f3 4664 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 4665 case BFD_RELOC_386_TLS_IE:
4666 case BFD_RELOC_386_TLS_GOTIE:
3e73aa7c 4667 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 4668 value = 0; /* Fully resolved at runtime. No addend. */
4669 break;
47926f60
KH		 4670
4671 case BFD_RELOC_VTABLE_INHERIT:
4672 case BFD_RELOC_VTABLE_ENTRY:
4673 fixP->fx_done = 0;
94f592af 4674 return;
47926f60
KH		 4675
4676 default:
4677 break;
4678 }
4679#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 4680 *valP = value;
47926f60 4681#endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
3e73aa7c 4682
3e73aa7c 4683 /* Are we finished with this relocation now? */
c6682705 4684 if (fixP->fx_addsy == NULL)
3e73aa7c 4685 fixP->fx_done = 1;
94f592af 4686#ifdef BFD_ASSEMBLER
3e73aa7c
JH		 4687 else if (use_rela_relocations)
4688 {
4689 fixP->fx_no_overflow = 1;
062cd5e7
AS		 4690 /* Remember value for tc_gen_reloc. */
4691 fixP->fx_addnumber = value;
3e73aa7c
JH		 4692 value = 0;
4693 }
3e73aa7c 4694#endif
94f592af 4695 md_number_to_chars (p, value, fixP->fx_size);
252b5132 4696}
252b5132 4697\f
252b5132
RH		 4698#define MAX_LITTLENUMS 6
4699
47926f60
KH		 4700/* Turn the string pointed to by litP into a floating point constant
4701 of type TYPE, and emit the appropriate bytes. The number of
4702 LITTLENUMS emitted is stored in *SIZEP. An error message is
4703 returned, or NULL on OK. */
4704
252b5132
RH		 4705char *
4706md_atof (type, litP, sizeP)
2ab9b79e 4707 int type;
252b5132
RH		 4708 char *litP;
4709 int *sizeP;
4710{
4711 int prec;
4712 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4713 LITTLENUM_TYPE *wordP;
4714 char *t;
4715
4716 switch (type)
4717 {
4718 case 'f':
4719 case 'F':
4720 prec = 2;
4721 break;
4722
4723 case 'd':
4724 case 'D':
4725 prec = 4;
4726 break;
4727
4728 case 'x':
4729 case 'X':
4730 prec = 5;
4731 break;
4732
4733 default:
4734 *sizeP = 0;
4735 return _("Bad call to md_atof ()");
4736 }
4737 t = atof_ieee (input_line_pointer, type, words);
4738 if (t)
4739 input_line_pointer = t;
4740
4741 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4742 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4743 the bigendian 386. */
4744 for (wordP = words + prec - 1; prec--;)
4745 {
4746 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
4747 litP += sizeof (LITTLENUM_TYPE);
4748 }
4749 return 0;
4750}
4751\f
4752char output_invalid_buf[8];
4753
252b5132
RH		 4754static char *
4755output_invalid (c)
4756 int c;
4757{
3882b010 4758 if (ISPRINT (c))
252b5132
RH		 4759 sprintf (output_invalid_buf, "'%c'", c);
4760 else
4761 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
4762 return output_invalid_buf;
4763}
4764
af6bdddf 4765/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 4766
4767static const reg_entry *
4768parse_register (reg_string, end_op)
4769 char *reg_string;
4770 char **end_op;
4771{
af6bdddf
AM		 4772 char *s = reg_string;
4773 char *p;
252b5132
RH		 4774 char reg_name_given[MAX_REG_NAME_SIZE + 1];
4775 const reg_entry *r;
4776
4777 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4778 if (*s == REGISTER_PREFIX)
4779 ++s;
4780
4781 if (is_space_char (*s))
4782 ++s;
4783
4784 p = reg_name_given;
af6bdddf 4785 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 4786 {
4787 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 4788 return (const reg_entry *) NULL;
4789 s++;
252b5132
RH		 4790 }
4791
6588847e
DN		 4792 /* For naked regs, make sure that we are not dealing with an identifier.
4793 This prevents confusing an identifier like `eax_var' with register
4794 `eax'. */
4795 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
4796 return (const reg_entry *) NULL;
4797
af6bdddf 4798 *end_op = s;
252b5132
RH		 4799
4800 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
4801
5f47d35b 4802 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 4803 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 4804 {
5f47d35b
AM		 4805 if (is_space_char (*s))
4806 ++s;
4807 if (*s == '(')
4808 {
af6bdddf 4809 ++s;
5f47d35b
AM		 4810 if (is_space_char (*s))
4811 ++s;
4812 if (*s >= '0' && *s <= '7')
4813 {
4814 r = &i386_float_regtab[*s - '0'];
af6bdddf 4815 ++s;
5f47d35b
AM		 4816 if (is_space_char (*s))
4817 ++s;
4818 if (*s == ')')
4819 {
4820 *end_op = s + 1;
4821 return r;
4822 }
5f47d35b 4823 }
47926f60 4824 /* We have "%st(" then garbage. */
5f47d35b
AM		 4825 return (const reg_entry *) NULL;
4826 }
4827 }
4828
1ae00879 4829 if (r != NULL
29b0f896 4830 && (r->reg_flags & (RegRex64 | RegRex)) != 0
1ae00879
AM		 4831 && flag_code != CODE_64BIT)
4832 {
4833 return (const reg_entry *) NULL;
4834 }
4835
252b5132
RH		 4836 return r;
4837}
4838\f
4cc782b5 4839#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
65172ab8 4840const char *md_shortopts = "kVQ:sq";
252b5132 4841#else
65172ab8 4842const char *md_shortopts = "q";
252b5132 4843#endif
6e0b89ee 4844
252b5132 4845struct option md_longopts[] = {
3e73aa7c
JH		 4846#define OPTION_32 (OPTION_MD_BASE + 0)
4847 {"32", no_argument, NULL, OPTION_32},
6e0b89ee 4848#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3e73aa7c
JH		 4849#define OPTION_64 (OPTION_MD_BASE + 1)
4850 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 4851#endif
252b5132
RH		 4852 {NULL, no_argument, NULL, 0}
4853};
4854size_t md_longopts_size = sizeof (md_longopts);
4855
4856int
4857md_parse_option (c, arg)
4858 int c;
ab9da554 4859 char *arg ATTRIBUTE_UNUSED;
252b5132
RH		 4860{
4861 switch (c)
4862 {
a38cf1db
AM		 4863 case 'q':
4864 quiet_warnings = 1;
252b5132
RH		 4865 break;
4866
4867#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 4868 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4869 should be emitted or not. FIXME: Not implemented. */
4870 case 'Q':
252b5132
RH		 4871 break;
4872
4873 /* -V: SVR4 argument to print version ID. */
4874 case 'V':
4875 print_version_id ();
4876 break;
4877
a38cf1db
AM		 4878 /* -k: Ignore for FreeBSD compatibility. */
4879 case 'k':
252b5132 4880 break;
4cc782b5
ILT		 4881
4882 case 's':
4883 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 4884 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 4885 break;
6e0b89ee 4886
3e73aa7c
JH		 4887 case OPTION_64:
4888 {
4889 const char **list, **l;
4890
3e73aa7c
JH		 4891 list = bfd_target_list ();
4892 for (l = list; *l != NULL; l++)
6e0b89ee
AM		 4893 if (strcmp (*l, "elf64-x86-64") == 0)
4894 {
4895 default_arch = "x86_64";
4896 break;
4897 }
3e73aa7c 4898 if (*l == NULL)
6e0b89ee 4899 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 4900 free (list);
4901 }
4902 break;
4903#endif
252b5132 4904
6e0b89ee
AM		 4905 case OPTION_32:
4906 default_arch = "i386";
4907 break;
4908
252b5132
RH		 4909 default:
4910 return 0;
4911 }
4912 return 1;
4913}
4914
4915void
4916md_show_usage (stream)
4917 FILE *stream;
4918{
4cc782b5
ILT		 4919#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4920 fprintf (stream, _("\
a38cf1db
AM		 4921 -Q ignored\n\
4922 -V print assembler version number\n\
4923 -k ignored\n\
4924 -q quieten some warnings\n\
4925 -s ignored\n"));
4926#else
4927 fprintf (stream, _("\
4928 -q quieten some warnings\n"));
4cc782b5 4929#endif
252b5132
RH		 4930}
4931
4932#ifdef BFD_ASSEMBLER
3e73aa7c
JH		 4933#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4934 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 4935
4936/* Pick the target format to use. */
4937
47926f60 4938const char *
252b5132
RH		 4939i386_target_format ()
4940{
3e73aa7c
JH		 4941 if (!strcmp (default_arch, "x86_64"))
4942 set_code_flag (CODE_64BIT);
4943 else if (!strcmp (default_arch, "i386"))
4944 set_code_flag (CODE_32BIT);
4945 else
4946 as_fatal (_("Unknown architecture"));
252b5132
RH		 4947 switch (OUTPUT_FLAVOR)
4948 {
4c63da97
AM		 4949#ifdef OBJ_MAYBE_AOUT
4950 case bfd_target_aout_flavour:
47926f60 4951 return AOUT_TARGET_FORMAT;
4c63da97
AM		 4952#endif
4953#ifdef OBJ_MAYBE_COFF
252b5132
RH		 4954 case bfd_target_coff_flavour:
4955 return "coff-i386";
4c63da97 4956#endif
3e73aa7c 4957#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 4958 case bfd_target_elf_flavour:
3e73aa7c 4959 {
e5cb08ac
KH		 4960 if (flag_code == CODE_64BIT)
4961 use_rela_relocations = 1;
4ada7262 4962 return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT;
3e73aa7c 4963 }
4c63da97 4964#endif
252b5132
RH		 4965 default:
4966 abort ();
4967 return NULL;
4968 }
4969}
4970
47926f60 4971#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 4972
4973#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4974void i386_elf_emit_arch_note ()
4975{
4976 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4977 && cpu_arch_name != NULL)
4978 {
4979 char *p;
4980 asection *seg = now_seg;
4981 subsegT subseg = now_subseg;
4982 Elf_Internal_Note i_note;
4983 Elf_External_Note e_note;
4984 asection *note_secp;
4985 int len;
4986
4987 /* Create the .note section. */
4988 note_secp = subseg_new (".note", 0);
4989 bfd_set_section_flags (stdoutput,
4990 note_secp,
4991 SEC_HAS_CONTENTS | SEC_READONLY);
4992
4993 /* Process the arch string. */
4994 len = strlen (cpu_arch_name);
4995
4996 i_note.namesz = len + 1;
4997 i_note.descsz = 0;
4998 i_note.type = NT_ARCH;
4999 p = frag_more (sizeof (e_note.namesz));
5000 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
5001 p = frag_more (sizeof (e_note.descsz));
5002 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
5003 p = frag_more (sizeof (e_note.type));
5004 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
5005 p = frag_more (len + 1);
5006 strcpy (p, cpu_arch_name);
5007
5008 frag_align (2, 0, 0);
5009
5010 subseg_set (seg, subseg);
5011 }
5012}
5013#endif
47926f60 5014#endif /* BFD_ASSEMBLER */
252b5132 5015\f
252b5132
RH		 5016symbolS *
5017md_undefined_symbol (name)
5018 char *name;
5019{
18dc2407
ILT		 5020 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
5021 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
5022 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
5023 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 5024 {
5025 if (!GOT_symbol)
5026 {
5027 if (symbol_find (name))
5028 as_bad (_("GOT already in symbol table"));
5029 GOT_symbol = symbol_new (name, undefined_section,
5030 (valueT) 0, &zero_address_frag);
5031 };
5032 return GOT_symbol;
5033 }
252b5132
RH		 5034 return 0;
5035}
5036
5037/* Round up a section size to the appropriate boundary. */
47926f60 5038
252b5132
RH		 5039valueT
5040md_section_align (segment, size)
ab9da554 5041 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 5042 valueT size;
5043{
252b5132 5044#ifdef BFD_ASSEMBLER
4c63da97
AM		 5045#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5046 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
5047 {
5048 /* For a.out, force the section size to be aligned. If we don't do
5049 this, BFD will align it for us, but it will not write out the
5050 final bytes of the section. This may be a bug in BFD, but it is
5051 easier to fix it here since that is how the other a.out targets
5052 work. */
5053 int align;
5054
5055 align = bfd_get_section_alignment (stdoutput, segment);
5056 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
5057 }
252b5132
RH		 5058#endif
5059#endif
5060
5061 return size;
5062}
5063
5064/* On the i386, PC-relative offsets are relative to the start of the
5065 next instruction. That is, the address of the offset, plus its
5066 size, since the offset is always the last part of the insn. */
5067
5068long
5069md_pcrel_from (fixP)
5070 fixS *fixP;
5071{
5072 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
5073}
5074
5075#ifndef I386COFF
5076
5077static void
5078s_bss (ignore)
ab9da554 5079 int ignore ATTRIBUTE_UNUSED;
252b5132 5080{
29b0f896 5081 int temp;
252b5132
RH		 5082
5083 temp = get_absolute_expression ();
5084 subseg_set (bss_section, (subsegT) temp);
5085 demand_empty_rest_of_line ();
5086}
5087
5088#endif
5089
252b5132
RH		 5090#ifdef BFD_ASSEMBLER
5091
5092void
5093i386_validate_fix (fixp)
5094 fixS *fixp;
5095{
5096 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
5097 {
3e73aa7c 5098 /* GOTOFF relocation are nonsense in 64bit mode. */
23df1078
JH		 5099 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
5100 {
5101 if (flag_code != CODE_64BIT)
5102 abort ();
5103 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
5104 }
5105 else
5106 {
5107 if (flag_code == CODE_64BIT)
5108 abort ();
5109 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
5110 }
252b5132
RH		 5111 fixp->fx_subsy = 0;
5112 }
5113}
5114
a161fe53
AM		 5115boolean
5116i386_force_relocation (fixp)
5117 fixS *fixp;
5118{
5119 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
5120 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5121 return 1;
5122
5123 return S_FORCE_RELOC (fixp->fx_addsy);
5124}
5125
252b5132
RH		 5126arelent *
5127tc_gen_reloc (section, fixp)
ab9da554 5128 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 5129 fixS *fixp;
5130{
5131 arelent *rel;
5132 bfd_reloc_code_real_type code;
5133
5134 switch (fixp->fx_r_type)
5135 {
3e73aa7c
JH		 5136 case BFD_RELOC_X86_64_PLT32:
5137 case BFD_RELOC_X86_64_GOT32:
5138 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 5139 case BFD_RELOC_386_PLT32:
5140 case BFD_RELOC_386_GOT32:
5141 case BFD_RELOC_386_GOTOFF:
5142 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 5143 case BFD_RELOC_386_TLS_GD:
5144 case BFD_RELOC_386_TLS_LDM:
5145 case BFD_RELOC_386_TLS_LDO_32:
5146 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5147 case BFD_RELOC_386_TLS_IE:
5148 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 5149 case BFD_RELOC_386_TLS_LE_32:
5150 case BFD_RELOC_386_TLS_LE:
3e73aa7c 5151 case BFD_RELOC_X86_64_32S:
252b5132
RH		 5152 case BFD_RELOC_RVA:
5153 case BFD_RELOC_VTABLE_ENTRY:
5154 case BFD_RELOC_VTABLE_INHERIT:
5155 code = fixp->fx_r_type;
5156 break;
5157 default:
93382f6d 5158 if (fixp->fx_pcrel)
252b5132 5159 {
93382f6d
AM		 5160 switch (fixp->fx_size)
5161 {
5162 default:
b091f402
AM		 5163 as_bad_where (fixp->fx_file, fixp->fx_line,
5164 _("can not do %d byte pc-relative relocation"),
5165 fixp->fx_size);
93382f6d
AM		 5166 code = BFD_RELOC_32_PCREL;
5167 break;
5168 case 1: code = BFD_RELOC_8_PCREL; break;
5169 case 2: code = BFD_RELOC_16_PCREL; break;
5170 case 4: code = BFD_RELOC_32_PCREL; break;
5171 }
5172 }
5173 else
5174 {
5175 switch (fixp->fx_size)
5176 {
5177 default:
b091f402
AM		 5178 as_bad_where (fixp->fx_file, fixp->fx_line,
5179 _("can not do %d byte relocation"),
5180 fixp->fx_size);
93382f6d
AM		 5181 code = BFD_RELOC_32;
5182 break;
5183 case 1: code = BFD_RELOC_8; break;
5184 case 2: code = BFD_RELOC_16; break;
5185 case 4: code = BFD_RELOC_32; break;
937149dd 5186#ifdef BFD64
3e73aa7c 5187 case 8: code = BFD_RELOC_64; break;
937149dd 5188#endif
93382f6d 5189 }
252b5132
RH		 5190 }
5191 break;
5192 }
252b5132
RH		 5193
5194 if (code == BFD_RELOC_32
5195 && GOT_symbol
5196 && fixp->fx_addsy == GOT_symbol)
3e73aa7c
JH		 5197 {
5198 /* We don't support GOTPC on 64bit targets. */
5199 if (flag_code == CODE_64BIT)
bfb32b52 5200 abort ();
3e73aa7c
JH		 5201 code = BFD_RELOC_386_GOTPC;
5202 }
252b5132
RH		 5203
5204 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 5205 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5206 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 5207
5208 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
3e73aa7c
JH		 5209 if (!use_rela_relocations)
5210 {
5211 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5212 vtable entry to be used in the relocation's section offset. */
5213 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5214 rel->address = fixp->fx_offset;
252b5132 5215
c6682705 5216 rel->addend = 0;
3e73aa7c
JH		 5217 }
5218 /* Use the rela in 64bit mode. */
252b5132 5219 else
3e73aa7c 5220 {
062cd5e7
AS		 5221 if (!fixp->fx_pcrel)
5222 rel->addend = fixp->fx_offset;
5223 else
5224 switch (code)
5225 {
5226 case BFD_RELOC_X86_64_PLT32:
5227 case BFD_RELOC_X86_64_GOT32:
5228 case BFD_RELOC_X86_64_GOTPCREL:
5229 rel->addend = fixp->fx_offset - fixp->fx_size;
5230 break;
5231 default:
5232 rel->addend = (section->vma
5233 - fixp->fx_size
5234 + fixp->fx_addnumber
5235 + md_pcrel_from (fixp));
5236 break;
5237 }
3e73aa7c
JH		 5238 }
5239
252b5132
RH		 5240 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
5241 if (rel->howto == NULL)
5242 {
5243 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 5244 _("cannot represent relocation type %s"),
252b5132
RH		 5245 bfd_get_reloc_code_name (code));
5246 /* Set howto to a garbage value so that we can keep going. */
5247 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
5248 assert (rel->howto != NULL);
5249 }
5250
5251 return rel;
5252}
5253
29b0f896 5254#else /* !BFD_ASSEMBLER */
252b5132
RH		 5255
5256#if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
5257void
5258tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
5259 char *where;
5260 fixS *fixP;
5261 relax_addressT segment_address_in_file;
5262{
47926f60
KH		 5263 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
5264 Out: GNU LD relocation length code: 0, 1, or 2. */
252b5132 5265
47926f60 5266 static const unsigned char nbytes_r_length[] = { 42, 0, 1, 42, 2 };
252b5132
RH		 5267 long r_symbolnum;
5268
5269 know (fixP->fx_addsy != NULL);
5270
5271 md_number_to_chars (where,
5272 (valueT) (fixP->fx_frag->fr_address
5273 + fixP->fx_where - segment_address_in_file),
5274 4);
5275
5276 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
5277 ? S_GET_TYPE (fixP->fx_addsy)
5278 : fixP->fx_addsy->sy_number);
5279
5280 where[6] = (r_symbolnum >> 16) & 0x0ff;
5281 where[5] = (r_symbolnum >> 8) & 0x0ff;
5282 where[4] = r_symbolnum & 0x0ff;
5283 where[7] = ((((!S_IS_DEFINED (fixP->fx_addsy)) << 3) & 0x08)
5284 | ((nbytes_r_length[fixP->fx_size] << 1) & 0x06)
5285 | (((fixP->fx_pcrel << 0) & 0x01) & 0x0f));
5286}
5287
47926f60 5288#endif /* OBJ_AOUT or OBJ_BOUT. */
252b5132
RH		 5289
5290#if defined (I386COFF)
5291
5292short
5293tc_coff_fix2rtype (fixP)
5294 fixS *fixP;
5295{
5296 if (fixP->fx_r_type == R_IMAGEBASE)
5297 return R_IMAGEBASE;
5298
5299 return (fixP->fx_pcrel ?
5300 (fixP->fx_size == 1 ? R_PCRBYTE :
5301 fixP->fx_size == 2 ? R_PCRWORD :
5302 R_PCRLONG) :
5303 (fixP->fx_size == 1 ? R_RELBYTE :
5304 fixP->fx_size == 2 ? R_RELWORD :
5305 R_DIR32));
5306}
5307
5308int
5309tc_coff_sizemachdep (frag)
5310 fragS *frag;
5311{
5312 if (frag->fr_next)
5313 return (frag->fr_next->fr_address - frag->fr_address);
5314 else
5315 return 0;
5316}
5317
47926f60 5318#endif /* I386COFF */
252b5132 5319
29b0f896 5320#endif /* !BFD_ASSEMBLER */
64a0c779
DN		 5321\f
5322/* Parse operands using Intel syntax. This implements a recursive descent
5323 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5324 Programmer's Guide.
5325
5326 FIXME: We do not recognize the full operand grammar defined in the MASM
5327 documentation. In particular, all the structure/union and
5328 high-level macro operands are missing.
5329
5330 Uppercase words are terminals, lower case words are non-terminals.
5331 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5332 bars '|' denote choices. Most grammar productions are implemented in
5333 functions called 'intel_<production>'.
5334
5335 Initial production is 'expr'.
5336
64a0c779
DN		 5337 addOp + | -
5338
5339 alpha [a-zA-Z]
5340
5341 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5342
5343 constant digits [[ radixOverride ]]
5344
5345 dataType BYTE | WORD | DWORD | QWORD | XWORD
5346
5347 digits decdigit
b77a7acd
AJ		 5348 | digits decdigit
5349 | digits hexdigit
64a0c779
DN		 5350
5351 decdigit [0-9]
5352
5353 e05 e05 addOp e06
b77a7acd 5354 | e06
64a0c779
DN		 5355
5356 e06 e06 mulOp e09
b77a7acd 5357 | e09
64a0c779
DN		 5358
5359 e09 OFFSET e10
5360 | e09 PTR e10
5361 | e09 : e10
5362 | e10
5363
5364 e10 e10 [ expr ]
b77a7acd 5365 | e11
64a0c779
DN		 5366
5367 e11 ( expr )
b77a7acd 5368 | [ expr ]
64a0c779
DN		 5369 | constant
5370 | dataType
5371 | id
5372 | $
5373 | register
5374
5375 => expr SHORT e05
b77a7acd 5376 | e05
64a0c779
DN		 5377
5378 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 5379 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 5380
5381 hexdigit a | b | c | d | e | f
b77a7acd 5382 | A | B | C | D | E | F
64a0c779
DN		 5383
5384 id alpha
b77a7acd 5385 | id alpha
64a0c779
DN		 5386 | id decdigit
5387
5388 mulOp * | / | MOD
5389
5390 quote " | '
5391
5392 register specialRegister
b77a7acd 5393 | gpRegister
64a0c779
DN		 5394 | byteRegister
5395
5396 segmentRegister CS | DS | ES | FS | GS | SS
5397
5398 specialRegister CR0 | CR2 | CR3
b77a7acd 5399 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 5400 | TR3 | TR4 | TR5 | TR6 | TR7
5401
64a0c779
DN		 5402 We simplify the grammar in obvious places (e.g., register parsing is
5403 done by calling parse_register) and eliminate immediate left recursion
5404 to implement a recursive-descent parser.
5405
5406 expr SHORT e05
b77a7acd 5407 | e05
64a0c779
DN		 5408
5409 e05 e06 e05'
5410
5411 e05' addOp e06 e05'
b77a7acd 5412 | Empty
64a0c779
DN		 5413
5414 e06 e09 e06'
5415
5416 e06' mulOp e09 e06'
b77a7acd 5417 | Empty
64a0c779
DN		 5418
5419 e09 OFFSET e10 e09'
b77a7acd 5420 | e10 e09'
64a0c779
DN		 5421
5422 e09' PTR e10 e09'
b77a7acd 5423 | : e10 e09'
64a0c779
DN		 5424 | Empty
5425
5426 e10 e11 e10'
5427
5428 e10' [ expr ] e10'
b77a7acd 5429 | Empty
64a0c779
DN		 5430
5431 e11 ( expr )
b77a7acd 5432 | [ expr ]
64a0c779
DN		 5433 | BYTE
5434 | WORD
5435 | DWORD
5436 | QWORD
5437 | XWORD
5438 | .
5439 | $
5440 | register
5441 | id
5442 | constant */
5443
5444/* Parsing structure for the intel syntax parser. Used to implement the
5445 semantic actions for the operand grammar. */
5446struct intel_parser_s
5447 {
5448 char *op_string; /* The string being parsed. */
5449 int got_a_float; /* Whether the operand is a float. */
4a1805b1 5450 int op_modifier; /* Operand modifier. */
64a0c779
DN		 5451 int is_mem; /* 1 if operand is memory reference. */
5452 const reg_entry *reg; /* Last register reference found. */
5453 char *disp; /* Displacement string being built. */
5454 };
5455
5456static struct intel_parser_s intel_parser;
5457
5458/* Token structure for parsing intel syntax. */
5459struct intel_token
5460 {
5461 int code; /* Token code. */
5462 const reg_entry *reg; /* Register entry for register tokens. */
5463 char *str; /* String representation. */
5464 };
5465
5466static struct intel_token cur_token, prev_token;
5467
50705ef4
AM		 5468/* Token codes for the intel parser. Since T_SHORT is already used
5469 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 5470#define T_NIL -1
5471#define T_CONST 1
5472#define T_REG 2
5473#define T_BYTE 3
5474#define T_WORD 4
5475#define T_DWORD 5
5476#define T_QWORD 6
5477#define T_XWORD 7
50705ef4 5478#undef T_SHORT
64a0c779
DN		 5479#define T_SHORT 8
5480#define T_OFFSET 9
5481#define T_PTR 10
5482#define T_ID 11
5483
5484/* Prototypes for intel parser functions. */
5485static int intel_match_token PARAMS ((int code));
cce0cbdc
DN		 5486static void intel_get_token PARAMS ((void));
5487static void intel_putback_token PARAMS ((void));
5488static int intel_expr PARAMS ((void));
5489static int intel_e05 PARAMS ((void));
5490static int intel_e05_1 PARAMS ((void));
5491static int intel_e06 PARAMS ((void));
5492static int intel_e06_1 PARAMS ((void));
5493static int intel_e09 PARAMS ((void));
5494static int intel_e09_1 PARAMS ((void));
5495static int intel_e10 PARAMS ((void));
5496static int intel_e10_1 PARAMS ((void));
5497static int intel_e11 PARAMS ((void));
64a0c779 5498
64a0c779
DN		 5499static int
5500i386_intel_operand (operand_string, got_a_float)
5501 char *operand_string;
5502 int got_a_float;
5503{
5504 int ret;
5505 char *p;
5506
5507 /* Initialize token holders. */
5508 cur_token.code = prev_token.code = T_NIL;
5509 cur_token.reg = prev_token.reg = NULL;
5510 cur_token.str = prev_token.str = NULL;
5511
5512 /* Initialize parser structure. */
e5cb08ac 5513 p = intel_parser.op_string = (char *) malloc (strlen (operand_string) + 1);
64a0c779
DN		 5514 if (p == NULL)
5515 abort ();
5516 strcpy (intel_parser.op_string, operand_string);
5517 intel_parser.got_a_float = got_a_float;
5518 intel_parser.op_modifier = -1;
5519 intel_parser.is_mem = 0;
5520 intel_parser.reg = NULL;
e5cb08ac 5521 intel_parser.disp = (char *) malloc (strlen (operand_string) + 1);
64a0c779
DN		 5522 if (intel_parser.disp == NULL)
5523 abort ();
5524 intel_parser.disp[0] = '\0';
5525
5526 /* Read the first token and start the parser. */
5527 intel_get_token ();
5528 ret = intel_expr ();
5529
5530 if (ret)
5531 {
5532 /* If we found a memory reference, hand it over to i386_displacement
5533 to fill in the rest of the operand fields. */
5534 if (intel_parser.is_mem)
5535 {
5536 if ((i.mem_operands == 1
5537 && (current_templates->start->opcode_modifier & IsString) == 0)
5538 || i.mem_operands == 2)
5539 {
5540 as_bad (_("too many memory references for '%s'"),
5541 current_templates->start->name);
5542 ret = 0;
5543 }
5544 else
5545 {
5546 char *s = intel_parser.disp;
5547 i.mem_operands++;
5548
5549 /* Add the displacement expression. */
5550 if (*s != '\0')
5551 ret = i386_displacement (s, s + strlen (s))
5552 && i386_index_check (s);
5553 }
5554 }
5555
5556 /* Constant and OFFSET expressions are handled by i386_immediate. */
5557 else if (intel_parser.op_modifier == OFFSET_FLAT
5558 || intel_parser.reg == NULL)
5559 ret = i386_immediate (intel_parser.disp);
5560 }
5561
5562 free (p);
5563 free (intel_parser.disp);
5564
5565 return ret;
5566}
5567
64a0c779 5568/* expr SHORT e05
b77a7acd 5569 | e05 */
64a0c779
DN		 5570static int
5571intel_expr ()
5572{
5573 /* expr SHORT e05 */
5574 if (cur_token.code == T_SHORT)
5575 {
5576 intel_parser.op_modifier = SHORT;
5577 intel_match_token (T_SHORT);
5578
5579 return (intel_e05 ());
5580 }
5581
5582 /* expr e05 */
5583 else
5584 return intel_e05 ();
5585}
5586
64a0c779
DN		 5587/* e05 e06 e05'
5588
4a1805b1 5589 e05' addOp e06 e05'
64a0c779
DN		 5590 | Empty */
5591static int
5592intel_e05 ()
5593{
5594 return (intel_e06 () && intel_e05_1 ());
5595}
5596
5597static int
5598intel_e05_1 ()
5599{
5600 /* e05' addOp e06 e05' */
5601 if (cur_token.code == '+' || cur_token.code == '-')
5602 {
5603 strcat (intel_parser.disp, cur_token.str);
5604 intel_match_token (cur_token.code);
5605
5606 return (intel_e06 () && intel_e05_1 ());
5607 }
5608
5609 /* e05' Empty */
5610 else
5611 return 1;
4a1805b1 5612}
64a0c779
DN		 5613
5614/* e06 e09 e06'
5615
5616 e06' mulOp e09 e06'
b77a7acd 5617 | Empty */
64a0c779
DN		 5618static int
5619intel_e06 ()
5620{
5621 return (intel_e09 () && intel_e06_1 ());
5622}
5623
5624static int
5625intel_e06_1 ()
5626{
5627 /* e06' mulOp e09 e06' */
5628 if (cur_token.code == '*' || cur_token.code == '/')
5629 {
5630 strcat (intel_parser.disp, cur_token.str);
5631 intel_match_token (cur_token.code);
5632
5633 return (intel_e09 () && intel_e06_1 ());
5634 }
4a1805b1 5635
64a0c779 5636 /* e06' Empty */
4a1805b1 5637 else
64a0c779
DN		 5638 return 1;
5639}
5640
64a0c779 5641/* e09 OFFSET e10 e09'
b77a7acd 5642 | e10 e09'
64a0c779
DN		 5643
5644 e09' PTR e10 e09'
b77a7acd 5645 | : e10 e09'
64a0c779
DN		 5646 | Empty */
5647static int
5648intel_e09 ()
5649{
5650 /* e09 OFFSET e10 e09' */
5651 if (cur_token.code == T_OFFSET)
5652 {
5653 intel_parser.is_mem = 0;
5654 intel_parser.op_modifier = OFFSET_FLAT;
5655 intel_match_token (T_OFFSET);
5656
5657 return (intel_e10 () && intel_e09_1 ());
5658 }
5659
5660 /* e09 e10 e09' */
5661 else
5662 return (intel_e10 () && intel_e09_1 ());
5663}
5664
5665static int
5666intel_e09_1 ()
5667{
5668 /* e09' PTR e10 e09' */
5669 if (cur_token.code == T_PTR)
5670 {
5671 if (prev_token.code == T_BYTE)
5672 i.suffix = BYTE_MNEM_SUFFIX;
5673
5674 else if (prev_token.code == T_WORD)
5675 {
5676 if (intel_parser.got_a_float == 2) /* "fi..." */
5677 i.suffix = SHORT_MNEM_SUFFIX;
5678 else
5679 i.suffix = WORD_MNEM_SUFFIX;
5680 }
5681
5682 else if (prev_token.code == T_DWORD)
5683 {
5684 if (intel_parser.got_a_float == 1) /* "f..." */
5685 i.suffix = SHORT_MNEM_SUFFIX;
5686 else
5687 i.suffix = LONG_MNEM_SUFFIX;
5688 }
5689
5690 else if (prev_token.code == T_QWORD)
f16b83df
JH		 5691 {
5692 if (intel_parser.got_a_float == 1) /* "f..." */
5693 i.suffix = LONG_MNEM_SUFFIX;
5694 else
3e73aa7c 5695 i.suffix = QWORD_MNEM_SUFFIX;
f16b83df 5696 }
64a0c779
DN		 5697
5698 else if (prev_token.code == T_XWORD)
5699 i.suffix = LONG_DOUBLE_MNEM_SUFFIX;
5700
5701 else
5702 {
5703 as_bad (_("Unknown operand modifier `%s'\n"), prev_token.str);
5704 return 0;
5705 }
5706
5707 intel_match_token (T_PTR);
5708
5709 return (intel_e10 () && intel_e09_1 ());
5710 }
5711
5712 /* e09 : e10 e09' */
5713 else if (cur_token.code == ':')
5714 {
21d6c4af
DN		 5715 /* Mark as a memory operand only if it's not already known to be an
5716 offset expression. */
5717 if (intel_parser.op_modifier != OFFSET_FLAT)
5718 intel_parser.is_mem = 1;
64a0c779
DN		 5719
5720 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5721 }
5722
5723 /* e09' Empty */
5724 else
5725 return 1;
5726}
5727
5728/* e10 e11 e10'
5729
5730 e10' [ expr ] e10'
b77a7acd 5731 | Empty */
64a0c779
DN		 5732static int
5733intel_e10 ()
5734{
5735 return (intel_e11 () && intel_e10_1 ());
5736}
5737
5738static int
5739intel_e10_1 ()
5740{
5741 /* e10' [ expr ] e10' */
5742 if (cur_token.code == '[')
5743 {
5744 intel_match_token ('[');
21d6c4af
DN		 5745
5746 /* Mark as a memory operand only if it's not already known to be an
5747 offset expression. If it's an offset expression, we need to keep
5748 the brace in. */
5749 if (intel_parser.op_modifier != OFFSET_FLAT)
5750 intel_parser.is_mem = 1;
5751 else
5752 strcat (intel_parser.disp, "[");
4a1805b1 5753
64a0c779 5754 /* Add a '+' to the displacement string if necessary. */
21d6c4af
DN		 5755 if (*intel_parser.disp != '\0'
5756 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
64a0c779
DN		 5757 strcat (intel_parser.disp, "+");
5758
21d6c4af
DN		 5759 if (intel_expr () && intel_match_token (']'))
5760 {
5761 /* Preserve brackets when the operand is an offset expression. */
5762 if (intel_parser.op_modifier == OFFSET_FLAT)
5763 strcat (intel_parser.disp, "]");
5764
5765 return intel_e10_1 ();
5766 }
5767 else
5768 return 0;
64a0c779
DN		 5769 }
5770
5771 /* e10' Empty */
5772 else
5773 return 1;
5774}
5775
64a0c779 5776/* e11 ( expr )
b77a7acd 5777 | [ expr ]
64a0c779
DN		 5778 | BYTE
5779 | WORD
5780 | DWORD
5781 | QWORD
5782 | XWORD
4a1805b1 5783 | $
64a0c779
DN		 5784 | .
5785 | register
5786 | id
5787 | constant */
5788static int
5789intel_e11 ()
5790{
5791 /* e11 ( expr ) */
5792 if (cur_token.code == '(')
5793 {
5794 intel_match_token ('(');
5795 strcat (intel_parser.disp, "(");
5796
5797 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 5798 {
5799 strcat (intel_parser.disp, ")");
5800 return 1;
5801 }
64a0c779
DN		 5802 else
5803 return 0;
5804 }
5805
5806 /* e11 [ expr ] */
5807 else if (cur_token.code == '[')
5808 {
5809 intel_match_token ('[');
21d6c4af
DN		 5810
5811 /* Mark as a memory operand only if it's not already known to be an
5812 offset expression. If it's an offset expression, we need to keep
5813 the brace in. */
5814 if (intel_parser.op_modifier != OFFSET_FLAT)
5815 intel_parser.is_mem = 1;
5816 else
5817 strcat (intel_parser.disp, "[");
4a1805b1 5818
64a0c779
DN		 5819 /* Operands for jump/call inside brackets denote absolute addresses. */
5820 if (current_templates->start->opcode_modifier & Jump
5821 || current_templates->start->opcode_modifier & JumpDword
5822 || current_templates->start->opcode_modifier & JumpByte
5823 || current_templates->start->opcode_modifier & JumpInterSegment)
5824 i.types[this_operand] |= JumpAbsolute;
5825
5826 /* Add a '+' to the displacement string if necessary. */
21d6c4af
DN		 5827 if (*intel_parser.disp != '\0'
5828 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
64a0c779
DN		 5829 strcat (intel_parser.disp, "+");
5830
21d6c4af
DN		 5831 if (intel_expr () && intel_match_token (']'))
5832 {
5833 /* Preserve brackets when the operand is an offset expression. */
5834 if (intel_parser.op_modifier == OFFSET_FLAT)
5835 strcat (intel_parser.disp, "]");
5836
5837 return 1;
5838 }
5839 else
5840 return 0;
64a0c779
DN		 5841 }
5842
4a1805b1 5843 /* e11 BYTE
64a0c779
DN		 5844 | WORD
5845 | DWORD
5846 | QWORD
5847 | XWORD */
5848 else if (cur_token.code == T_BYTE
5849 || cur_token.code == T_WORD
5850 || cur_token.code == T_DWORD
5851 || cur_token.code == T_QWORD
5852 || cur_token.code == T_XWORD)
5853 {
5854 intel_match_token (cur_token.code);
5855
5856 return 1;
5857 }
5858
5859 /* e11 $
5860 | . */
5861 else if (cur_token.code == '$' || cur_token.code == '.')
5862 {
5863 strcat (intel_parser.disp, cur_token.str);
5864 intel_match_token (cur_token.code);
21d6c4af
DN		 5865
5866 /* Mark as a memory operand only if it's not already known to be an
5867 offset expression. */
5868 if (intel_parser.op_modifier != OFFSET_FLAT)
5869 intel_parser.is_mem = 1;
64a0c779
DN		 5870
5871 return 1;
5872 }
5873
5874 /* e11 register */
5875 else if (cur_token.code == T_REG)
5876 {
5877 const reg_entry *reg = intel_parser.reg = cur_token.reg;
5878
5879 intel_match_token (T_REG);
5880
5881 /* Check for segment change. */
5882 if (cur_token.code == ':')
5883 {
5884 if (reg->reg_type & (SReg2 | SReg3))
5885 {
5886 switch (reg->reg_num)
5887 {
5888 case 0:
5889 i.seg[i.mem_operands] = &es;
5890 break;
5891 case 1:
5892 i.seg[i.mem_operands] = &cs;
5893 break;
5894 case 2:
5895 i.seg[i.mem_operands] = &ss;
5896 break;
5897 case 3:
5898 i.seg[i.mem_operands] = &ds;
5899 break;
5900 case 4:
5901 i.seg[i.mem_operands] = &fs;
5902 break;
5903 case 5:
5904 i.seg[i.mem_operands] = &gs;
5905 break;
5906 }
5907 }
5908 else
5909 {
5910 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
5911 return 0;
5912 }
5913 }
5914
5915 /* Not a segment register. Check for register scaling. */
5916 else if (cur_token.code == '*')
5917 {
5918 if (!intel_parser.is_mem)
5919 {
5920 as_bad (_("Register scaling only allowed in memory operands."));
5921 return 0;
5922 }
5923
4a1805b1 5924 /* What follows must be a valid scale. */
64a0c779
DN		 5925 if (intel_match_token ('*')
5926 && strchr ("01248", *cur_token.str))
5927 {
5928 i.index_reg = reg;
5929 i.types[this_operand] |= BaseIndex;
5930
5931 /* Set the scale after setting the register (otherwise,
5932 i386_scale will complain) */
5933 i386_scale (cur_token.str);
5934 intel_match_token (T_CONST);
5935 }
5936 else
5937 {
5938 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5939 cur_token.str);
5940 return 0;
5941 }
5942 }
5943
5944 /* No scaling. If this is a memory operand, the register is either a
5945 base register (first occurrence) or an index register (second
5946 occurrence). */
5947 else if (intel_parser.is_mem && !(reg->reg_type & (SReg2 | SReg3)))
5948 {
5949 if (i.base_reg && i.index_reg)
5950 {
5951 as_bad (_("Too many register references in memory operand.\n"));
5952 return 0;
5953 }
5954
5955 if (i.base_reg == NULL)
5956 i.base_reg = reg;
5957 else
5958 i.index_reg = reg;
5959
5960 i.types[this_operand] |= BaseIndex;
5961 }
5962
5963 /* Offset modifier. Add the register to the displacement string to be
5964 parsed as an immediate expression after we're done. */
5965 else if (intel_parser.op_modifier == OFFSET_FLAT)
5966 strcat (intel_parser.disp, reg->reg_name);
4a1805b1 5967
64a0c779
DN		 5968 /* It's neither base nor index nor offset. */
5969 else
5970 {
5971 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
5972 i.op[this_operand].regs = reg;
5973 i.reg_operands++;
5974 }
5975
5976 /* Since registers are not part of the displacement string (except
5977 when we're parsing offset operands), we may need to remove any
5978 preceding '+' from the displacement string. */
5979 if (*intel_parser.disp != '\0'
5980 && intel_parser.op_modifier != OFFSET_FLAT)
5981 {
5982 char *s = intel_parser.disp;
5983 s += strlen (s) - 1;
5984 if (*s == '+')
5985 *s = '\0';
5986 }
5987
5988 return 1;
5989 }
4a1805b1 5990
64a0c779
DN		 5991 /* e11 id */
5992 else if (cur_token.code == T_ID)
5993 {
5994 /* Add the identifier to the displacement string. */
5995 strcat (intel_parser.disp, cur_token.str);
5996 intel_match_token (T_ID);
5997
5998 /* The identifier represents a memory reference only if it's not
5999 preceded by an offset modifier. */
21d6c4af 6000 if (intel_parser.op_modifier != OFFSET_FLAT)
64a0c779
DN		 6001 intel_parser.is_mem = 1;
6002
6003 return 1;
6004 }
6005
6006 /* e11 constant */
6007 else if (cur_token.code == T_CONST
e5cb08ac 6008 || cur_token.code == '-'
64a0c779
DN		 6009 || cur_token.code == '+')
6010 {
6011 char *save_str;
6012
6013 /* Allow constants that start with `+' or `-'. */
6014 if (cur_token.code == '-' || cur_token.code == '+')
6015 {
6016 strcat (intel_parser.disp, cur_token.str);
6017 intel_match_token (cur_token.code);
6018 if (cur_token.code != T_CONST)
6019 {
6020 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
6021 cur_token.str);
6022 return 0;
6023 }
6024 }
6025
e5cb08ac 6026 save_str = (char *) malloc (strlen (cur_token.str) + 1);
64a0c779 6027 if (save_str == NULL)
bc805888 6028 abort ();
64a0c779
DN		 6029 strcpy (save_str, cur_token.str);
6030
6031 /* Get the next token to check for register scaling. */
6032 intel_match_token (cur_token.code);
6033
6034 /* Check if this constant is a scaling factor for an index register. */
6035 if (cur_token.code == '*')
6036 {
6037 if (intel_match_token ('*') && cur_token.code == T_REG)
6038 {
6039 if (!intel_parser.is_mem)
6040 {
6041 as_bad (_("Register scaling only allowed in memory operands."));
6042 return 0;
6043 }
6044
4a1805b1 6045 /* The constant is followed by `* reg', so it must be
64a0c779
DN		 6046 a valid scale. */
6047 if (strchr ("01248", *save_str))
6048 {
6049 i.index_reg = cur_token.reg;
6050 i.types[this_operand] |= BaseIndex;
6051
6052 /* Set the scale after setting the register (otherwise,
6053 i386_scale will complain) */
6054 i386_scale (save_str);
6055 intel_match_token (T_REG);
6056
6057 /* Since registers are not part of the displacement
6058 string, we may need to remove any preceding '+' from
6059 the displacement string. */
6060 if (*intel_parser.disp != '\0')
6061 {
6062 char *s = intel_parser.disp;
6063 s += strlen (s) - 1;
6064 if (*s == '+')
6065 *s = '\0';
6066 }
6067
6068 free (save_str);
6069
6070 return 1;
6071 }
6072 else
6073 return 0;
6074 }
6075
6076 /* The constant was not used for register scaling. Since we have
6077 already consumed the token following `*' we now need to put it
6078 back in the stream. */
6079 else
6080 intel_putback_token ();
6081 }
6082
6083 /* Add the constant to the displacement string. */
6084 strcat (intel_parser.disp, save_str);
6085 free (save_str);
6086
6087 return 1;
6088 }
6089
64a0c779
DN		 6090 as_bad (_("Unrecognized token '%s'"), cur_token.str);
6091 return 0;
6092}
6093
64a0c779
DN		 6094/* Match the given token against cur_token. If they match, read the next
6095 token from the operand string. */
6096static int
6097intel_match_token (code)
e5cb08ac 6098 int code;
64a0c779
DN		 6099{
6100 if (cur_token.code == code)
6101 {
6102 intel_get_token ();
6103 return 1;
6104 }
6105 else
6106 {
6107 as_bad (_("Unexpected token `%s'\n"), cur_token.str);
6108 return 0;
6109 }
6110}
6111
64a0c779
DN		 6112/* Read a new token from intel_parser.op_string and store it in cur_token. */
6113static void
6114intel_get_token ()
6115{
6116 char *end_op;
6117 const reg_entry *reg;
6118 struct intel_token new_token;
6119
6120 new_token.code = T_NIL;
6121 new_token.reg = NULL;
6122 new_token.str = NULL;
6123
4a1805b1 6124 /* Free the memory allocated to the previous token and move
64a0c779
DN		 6125 cur_token to prev_token. */
6126 if (prev_token.str)
6127 free (prev_token.str);
6128
6129 prev_token = cur_token;
6130
6131 /* Skip whitespace. */
6132 while (is_space_char (*intel_parser.op_string))
6133 intel_parser.op_string++;
6134
6135 /* Return an empty token if we find nothing else on the line. */
6136 if (*intel_parser.op_string == '\0')
6137 {
6138 cur_token = new_token;
6139 return;
6140 }
6141
6142 /* The new token cannot be larger than the remainder of the operand
6143 string. */
e5cb08ac 6144 new_token.str = (char *) malloc (strlen (intel_parser.op_string) + 1);
64a0c779 6145 if (new_token.str == NULL)
bc805888 6146 abort ();
64a0c779
DN		 6147 new_token.str[0] = '\0';
6148
6149 if (strchr ("0123456789", *intel_parser.op_string))
6150 {
6151 char *p = new_token.str;
6152 char *q = intel_parser.op_string;
6153 new_token.code = T_CONST;
6154
6155 /* Allow any kind of identifier char to encompass floating point and
6156 hexadecimal numbers. */
6157 while (is_identifier_char (*q))
6158 *p++ = *q++;
6159 *p = '\0';
6160
6161 /* Recognize special symbol names [0-9][bf]. */
6162 if (strlen (intel_parser.op_string) == 2
4a1805b1 6163 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 6164 || intel_parser.op_string[1] == 'f'))
6165 new_token.code = T_ID;
6166 }
6167
6168 else if (strchr ("+-/*:[]()", *intel_parser.op_string))
6169 {
6170 new_token.code = *intel_parser.op_string;
6171 new_token.str[0] = *intel_parser.op_string;
6172 new_token.str[1] = '\0';
6173 }
6174
6175 else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg)
6176 && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL))
6177 {
6178 new_token.code = T_REG;
6179 new_token.reg = reg;
6180
6181 if (*intel_parser.op_string == REGISTER_PREFIX)
6182 {
6183 new_token.str[0] = REGISTER_PREFIX;
6184 new_token.str[1] = '\0';
6185 }
6186
6187 strcat (new_token.str, reg->reg_name);
6188 }
6189
6190 else if (is_identifier_char (*intel_parser.op_string))
6191 {
6192 char *p = new_token.str;
6193 char *q = intel_parser.op_string;
6194
6195 /* A '.' or '$' followed by an identifier char is an identifier.
6196 Otherwise, it's operator '.' followed by an expression. */
6197 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
6198 {
6199 new_token.code = *q;
6200 new_token.str[0] = *q;
6201 new_token.str[1] = '\0';
6202 }
6203 else
6204 {
6205 while (is_identifier_char (*q) || *q == '@')
6206 *p++ = *q++;
6207 *p = '\0';
6208
6209 if (strcasecmp (new_token.str, "BYTE") == 0)
6210 new_token.code = T_BYTE;
6211
6212 else if (strcasecmp (new_token.str, "WORD") == 0)
6213 new_token.code = T_WORD;
6214
6215 else if (strcasecmp (new_token.str, "DWORD") == 0)
6216 new_token.code = T_DWORD;
6217
6218 else if (strcasecmp (new_token.str, "QWORD") == 0)
6219 new_token.code = T_QWORD;
6220
6221 else if (strcasecmp (new_token.str, "XWORD") == 0)
6222 new_token.code = T_XWORD;
6223
6224 else if (strcasecmp (new_token.str, "PTR") == 0)
6225 new_token.code = T_PTR;
6226
6227 else if (strcasecmp (new_token.str, "SHORT") == 0)
6228 new_token.code = T_SHORT;
6229
6230 else if (strcasecmp (new_token.str, "OFFSET") == 0)
6231 {
6232 new_token.code = T_OFFSET;
6233
6234 /* ??? This is not mentioned in the MASM grammar but gcc
6235 makes use of it with -mintel-syntax. OFFSET may be
6236 followed by FLAT: */
6237 if (strncasecmp (q, " FLAT:", 6) == 0)
6238 strcat (new_token.str, " FLAT:");
6239 }
6240
6241 /* ??? This is not mentioned in the MASM grammar. */
6242 else if (strcasecmp (new_token.str, "FLAT") == 0)
6243 new_token.code = T_OFFSET;
6244
6245 else
6246 new_token.code = T_ID;
6247 }
6248 }
6249
6250 else
6251 as_bad (_("Unrecognized token `%s'\n"), intel_parser.op_string);
6252
6253 intel_parser.op_string += strlen (new_token.str);
6254 cur_token = new_token;
6255}
6256
64a0c779
DN		 6257/* Put cur_token back into the token stream and make cur_token point to
6258 prev_token. */
6259static void
6260intel_putback_token ()
6261{
6262 intel_parser.op_string -= strlen (cur_token.str);
6263 free (cur_token.str);
6264 cur_token = prev_token;
4a1805b1 6265
64a0c779
DN		 6266 /* Forget prev_token. */
6267 prev_token.code = T_NIL;
6268 prev_token.reg = NULL;
6269 prev_token.str = NULL;
6270}
GDB Binutils - Deliverables
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