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* elf32-ppc.c (ppc_elf_relocate_section): Allow ".sbss.*" and
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
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252b5132 1/* i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
5db1645b 3 2000, 2001, 2002
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
47926f60
KH		 26 Bugs & suggestions are completely welcome. This is free software.
27 Please help us make it better. */
252b5132 28
252b5132 29#include "as.h"
3882b010 30#include "safe-ctype.h"
252b5132 31#include "subsegs.h"
316e2c05 32#include "dwarf2dbg.h"
252b5132
RH		 33#include "opcode/i386.h"
34
252b5132
RH		 35#ifndef REGISTER_WARNINGS
36#define REGISTER_WARNINGS 1
37#endif
38
c3332e24 39#ifndef INFER_ADDR_PREFIX
eecb386c 40#define INFER_ADDR_PREFIX 1
c3332e24
AM		 41#endif
42
252b5132
RH		 43#ifndef SCALE1_WHEN_NO_INDEX
44/* Specifying a scale factor besides 1 when there is no index is
45 futile. eg. `mov (%ebx,2),%al' does exactly the same as
46 `mov (%ebx),%al'. To slavishly follow what the programmer
47 specified, set SCALE1_WHEN_NO_INDEX to 0. */
48#define SCALE1_WHEN_NO_INDEX 1
49#endif
50
29b0f896
AM		 51#ifdef BFD_ASSEMBLER
52#define RELOC_ENUM enum bfd_reloc_code_real
53#else
54#define RELOC_ENUM int
246fcdee 55#endif
29b0f896
AM		 56
57#ifndef DEFAULT_ARCH
58#define DEFAULT_ARCH "i386"
246fcdee 59#endif
252b5132 60
edde18a5
AM		 61#ifndef INLINE
62#if __GNUC__ >= 2
63#define INLINE __inline__
64#else
65#define INLINE
66#endif
67#endif
68
29b0f896
AM		 69static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
70static INLINE int fits_in_signed_byte PARAMS ((offsetT));
71static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
72static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
73static INLINE int fits_in_signed_word PARAMS ((offsetT));
74static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
75static INLINE int fits_in_signed_long PARAMS ((offsetT));
847f7ad4
AM		 76static int smallest_imm_type PARAMS ((offsetT));
77static offsetT offset_in_range PARAMS ((offsetT, int));
252b5132 78static int add_prefix PARAMS ((unsigned int));
3e73aa7c 79static void set_code_flag PARAMS ((int));
47926f60 80static void set_16bit_gcc_code_flag PARAMS ((int));
252b5132 81static void set_intel_syntax PARAMS ((int));
e413e4e9 82static void set_cpu_arch PARAMS ((int));
29b0f896
AM		 83static char *output_invalid PARAMS ((int c));
84static int i386_operand PARAMS ((char *operand_string));
85static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
86static const reg_entry *parse_register PARAMS ((char *reg_string,
87 char **end_op));
88static char *parse_insn PARAMS ((char *, char *));
89static char *parse_operands PARAMS ((char *, const char *));
90static void swap_operands PARAMS ((void));
91static void optimize_imm PARAMS ((void));
92static void optimize_disp PARAMS ((void));
93static int match_template PARAMS ((void));
94static int check_string PARAMS ((void));
95static int process_suffix PARAMS ((void));
96static int check_byte_reg PARAMS ((void));
97static int check_long_reg PARAMS ((void));
98static int check_qword_reg PARAMS ((void));
99static int check_word_reg PARAMS ((void));
100static int finalize_imm PARAMS ((void));
101static int process_operands PARAMS ((void));
102static const seg_entry *build_modrm_byte PARAMS ((void));
103static void output_insn PARAMS ((void));
104static void output_branch PARAMS ((void));
105static void output_jump PARAMS ((void));
106static void output_interseg_jump PARAMS ((void));
2bbd9c25
JJ		 107static void output_imm PARAMS ((fragS *insn_start_frag,
108 offsetT insn_start_off));
109static void output_disp PARAMS ((fragS *insn_start_frag,
110 offsetT insn_start_off));
29b0f896
AM		 111#ifndef I386COFF
112static void s_bss PARAMS ((int));
252b5132
RH		 113#endif
114
a847613f 115static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 116
252b5132 117/* 'md_assemble ()' gathers together information and puts it into a
47926f60 118 i386_insn. */
252b5132 119
520dc8e8
AM		 120union i386_op
121 {
122 expressionS *disps;
123 expressionS *imms;
124 const reg_entry *regs;
125 };
126
252b5132
RH		 127struct _i386_insn
128 {
47926f60 129 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 130 template tm;
131
132 /* SUFFIX holds the instruction mnemonic suffix if given.
133 (e.g. 'l' for 'movl') */
134 char suffix;
135
47926f60 136 /* OPERANDS gives the number of given operands. */
252b5132
RH		 137 unsigned int operands;
138
139 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
140 of given register, displacement, memory operands and immediate
47926f60 141 operands. */
252b5132
RH		 142 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
143
144 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 145 use OP[i] for the corresponding operand. */
252b5132
RH		 146 unsigned int types[MAX_OPERANDS];
147
520dc8e8
AM		 148 /* Displacement expression, immediate expression, or register for each
149 operand. */
150 union i386_op op[MAX_OPERANDS];
252b5132 151
3e73aa7c
JH		 152 /* Flags for operands. */
153 unsigned int flags[MAX_OPERANDS];
154#define Operand_PCrel 1
155
252b5132 156 /* Relocation type for operand */
f3c180ae 157 RELOC_ENUM reloc[MAX_OPERANDS];
252b5132 158
252b5132
RH		 159 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
160 the base index byte below. */
161 const reg_entry *base_reg;
162 const reg_entry *index_reg;
163 unsigned int log2_scale_factor;
164
165 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 166 explicit segment overrides are given. */
ce8a8b2f 167 const seg_entry *seg[2];
252b5132
RH		 168
169 /* PREFIX holds all the given prefix opcodes (usually null).
170 PREFIXES is the number of prefix opcodes. */
171 unsigned int prefixes;
172 unsigned char prefix[MAX_PREFIXES];
173
174 /* RM and SIB are the modrm byte and the sib byte where the
175 addressing modes of this insn are encoded. */
176
177 modrm_byte rm;
3e73aa7c 178 rex_byte rex;
252b5132
RH		 179 sib_byte sib;
180 };
181
182typedef struct _i386_insn i386_insn;
183
184/* List of chars besides those in app.c:symbol_chars that can start an
185 operand. Used to prevent the scrubber eating vital white-space. */
186#ifdef LEX_AT
200dbde8 187const char extra_symbol_chars[] = "*%-(@[";
252b5132 188#else
200dbde8 189const char extra_symbol_chars[] = "*%-([";
252b5132
RH		 190#endif
191
29b0f896
AM		 192#if (defined (TE_I386AIX) \
193 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
194 && !defined (TE_LINUX) \
195 && !defined (TE_FreeBSD) \
196 && !defined (TE_NetBSD)))
252b5132 197/* This array holds the chars that always start a comment. If the
ce8a8b2f 198 pre-processor is disabled, these aren't very useful. */
252b5132
RH		 199const char comment_chars[] = "#/";
200#define PREFIX_SEPARATOR '\\'
252b5132
RH		 201
202/* This array holds the chars that only start a comment at the beginning of
203 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 204 .line and .file directives will appear in the pre-processed output.
205 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 206 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 207 #NO_APP at the beginning of its output.
208 Also note that comments started like this one will always work if
252b5132 209 '/' isn't otherwise defined. */
252b5132 210const char line_comment_chars[] = "";
29b0f896 211
252b5132 212#else
29b0f896
AM		 213/* Putting '/' here makes it impossible to use the divide operator.
214 However, we need it for compatibility with SVR4 systems. */
215const char comment_chars[] = "#";
216#define PREFIX_SEPARATOR '/'
217
252b5132
RH		 218const char line_comment_chars[] = "/";
219#endif
220
63a0b638 221const char line_separator_chars[] = ";";
252b5132 222
ce8a8b2f
AM		 223/* Chars that can be used to separate mant from exp in floating point
224 nums. */
252b5132
RH		 225const char EXP_CHARS[] = "eE";
226
ce8a8b2f
AM		 227/* Chars that mean this number is a floating point constant
228 As in 0f12.456
229 or 0d1.2345e12. */
252b5132
RH		 230const char FLT_CHARS[] = "fFdDxX";
231
ce8a8b2f 232/* Tables for lexical analysis. */
252b5132
RH		 233static char mnemonic_chars[256];
234static char register_chars[256];
235static char operand_chars[256];
236static char identifier_chars[256];
237static char digit_chars[256];
238
ce8a8b2f 239/* Lexical macros. */
252b5132
RH		 240#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
241#define is_operand_char(x) (operand_chars[(unsigned char) x])
242#define is_register_char(x) (register_chars[(unsigned char) x])
243#define is_space_char(x) ((x) == ' ')
244#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
245#define is_digit_char(x) (digit_chars[(unsigned char) x])
246
ce8a8b2f 247/* All non-digit non-letter charcters that may occur in an operand. */
252b5132
RH		 248static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
249
250/* md_assemble() always leaves the strings it's passed unaltered. To
251 effect this we maintain a stack of saved characters that we've smashed
252 with '\0's (indicating end of strings for various sub-fields of the
47926f60 253 assembler instruction). */
252b5132 254static char save_stack[32];
ce8a8b2f 255static char *save_stack_p;
252b5132
RH		 256#define END_STRING_AND_SAVE(s) \
257 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
258#define RESTORE_END_STRING(s) \
259 do { *(s) = *--save_stack_p; } while (0)
260
47926f60 261/* The instruction we're assembling. */
252b5132
RH		 262static i386_insn i;
263
264/* Possible templates for current insn. */
265static const templates *current_templates;
266
47926f60 267/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
252b5132
RH		 268static expressionS disp_expressions[2], im_expressions[2];
269
47926f60
KH		 270/* Current operand we are working on. */
271static int this_operand;
252b5132 272
3e73aa7c
JH		 273/* We support four different modes. FLAG_CODE variable is used to distinguish
274 these. */
275
276enum flag_code {
277 CODE_32BIT,
278 CODE_16BIT,
279 CODE_64BIT };
f3c180ae 280#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 281
282static enum flag_code flag_code;
283static int use_rela_relocations = 0;
284
285/* The names used to print error messages. */
b77a7acd 286static const char *flag_code_names[] =
3e73aa7c
JH		 287 {
288 "32",
289 "16",
290 "64"
291 };
252b5132 292
47926f60
KH		 293/* 1 for intel syntax,
294 0 if att syntax. */
295static int intel_syntax = 0;
252b5132 296
47926f60
KH		 297/* 1 if register prefix % not required. */
298static int allow_naked_reg = 0;
252b5132 299
47926f60
KH		 300/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
301 leave, push, and pop instructions so that gcc has the same stack
302 frame as in 32 bit mode. */
303static char stackop_size = '\0';
eecb386c 304
47926f60
KH		 305/* Non-zero to quieten some warnings. */
306static int quiet_warnings = 0;
a38cf1db 307
47926f60
KH		 308/* CPU name. */
309static const char *cpu_arch_name = NULL;
a38cf1db 310
47926f60 311/* CPU feature flags. */
29b0f896 312static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 313
fddf5b5b
AM		 314/* If set, conditional jumps are not automatically promoted to handle
315 larger than a byte offset. */
316static unsigned int no_cond_jump_promotion = 0;
317
29b0f896
AM		 318/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
319symbolS *GOT_symbol;
320
252b5132 321/* Interface to relax_segment.
fddf5b5b
AM		 322 There are 3 major relax states for 386 jump insns because the
323 different types of jumps add different sizes to frags when we're
324 figuring out what sort of jump to choose to reach a given label. */
252b5132 325
47926f60 326/* Types. */
93c2a809
AM		 327#define UNCOND_JUMP 0
328#define COND_JUMP 1
329#define COND_JUMP86 2
fddf5b5b 330
47926f60 331/* Sizes. */
252b5132
RH		 332#define CODE16 1
333#define SMALL 0
29b0f896 334#define SMALL16 (SMALL | CODE16)
252b5132 335#define BIG 2
29b0f896 336#define BIG16 (BIG | CODE16)
252b5132
RH		 337
338#ifndef INLINE
339#ifdef __GNUC__
340#define INLINE __inline__
341#else
342#define INLINE
343#endif
344#endif
345
fddf5b5b
AM		 346#define ENCODE_RELAX_STATE(type, size) \
347 ((relax_substateT) (((type) << 2) | (size)))
348#define TYPE_FROM_RELAX_STATE(s) \
349 ((s) >> 2)
350#define DISP_SIZE_FROM_RELAX_STATE(s) \
351 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 352
353/* This table is used by relax_frag to promote short jumps to long
354 ones where necessary. SMALL (short) jumps may be promoted to BIG
355 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
356 don't allow a short jump in a 32 bit code segment to be promoted to
357 a 16 bit offset jump because it's slower (requires data size
358 prefix), and doesn't work, unless the destination is in the bottom
359 64k of the code segment (The top 16 bits of eip are zeroed). */
360
361const relax_typeS md_relax_table[] =
362{
24eab124
AM		 363 /* The fields are:
364 1) most positive reach of this state,
365 2) most negative reach of this state,
93c2a809 366 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 367 4) which index into the table to try if we can't fit into this one. */
252b5132 368
fddf5b5b 369 /* UNCOND_JUMP states. */
93c2a809
AM		 370 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
371 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
372 /* dword jmp adds 4 bytes to frag:
373 0 extra opcode bytes, 4 displacement bytes. */
252b5132 374 {0, 0, 4, 0},
93c2a809
AM		 375 /* word jmp adds 2 byte2 to frag:
376 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 377 {0, 0, 2, 0},
378
93c2a809
AM		 379 /* COND_JUMP states. */
380 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
381 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
382 /* dword conditionals adds 5 bytes to frag:
383 1 extra opcode byte, 4 displacement bytes. */
384 {0, 0, 5, 0},
fddf5b5b 385 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 386 1 extra opcode byte, 2 displacement bytes. */
387 {0, 0, 3, 0},
388
389 /* COND_JUMP86 states. */
390 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
391 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
392 /* dword conditionals adds 5 bytes to frag:
393 1 extra opcode byte, 4 displacement bytes. */
394 {0, 0, 5, 0},
395 /* word conditionals add 4 bytes to frag:
396 1 displacement byte and a 3 byte long branch insn. */
397 {0, 0, 4, 0}
252b5132
RH		 398};
399
e413e4e9
AM		 400static const arch_entry cpu_arch[] = {
401 {"i8086", Cpu086 },
402 {"i186", Cpu086|Cpu186 },
403 {"i286", Cpu086|Cpu186|Cpu286 },
404 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
405 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
406 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
407 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
408 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
409 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
a167610d 410 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2 },
3e73aa7c
JH		 411 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
412 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|Cpu3dnow },
a167610d 413 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|Cpu3dnow|CpuSSE|CpuSSE2 },
e413e4e9
AM		 414 {NULL, 0 }
415};
416
29b0f896
AM		 417const pseudo_typeS md_pseudo_table[] =
418{
419#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
420 {"align", s_align_bytes, 0},
421#else
422 {"align", s_align_ptwo, 0},
423#endif
424 {"arch", set_cpu_arch, 0},
425#ifndef I386COFF
426 {"bss", s_bss, 0},
427#endif
428 {"ffloat", float_cons, 'f'},
429 {"dfloat", float_cons, 'd'},
430 {"tfloat", float_cons, 'x'},
431 {"value", cons, 2},
432 {"noopt", s_ignore, 0},
433 {"optim", s_ignore, 0},
434 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
435 {"code16", set_code_flag, CODE_16BIT},
436 {"code32", set_code_flag, CODE_32BIT},
437 {"code64", set_code_flag, CODE_64BIT},
438 {"intel_syntax", set_intel_syntax, 1},
439 {"att_syntax", set_intel_syntax, 0},
c6682705 440 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
29b0f896
AM		 441 {"loc", dwarf2_directive_loc, 0},
442 {0, 0, 0}
443};
444
445/* For interface with expression (). */
446extern char *input_line_pointer;
447
448/* Hash table for instruction mnemonic lookup. */
449static struct hash_control *op_hash;
450
451/* Hash table for register lookup. */
452static struct hash_control *reg_hash;
453\f
252b5132
RH		 454void
455i386_align_code (fragP, count)
456 fragS *fragP;
457 int count;
458{
ce8a8b2f
AM		 459 /* Various efficient no-op patterns for aligning code labels.
460 Note: Don't try to assemble the instructions in the comments.
461 0L and 0w are not legal. */
252b5132
RH		 462 static const char f32_1[] =
463 {0x90}; /* nop */
464 static const char f32_2[] =
465 {0x89,0xf6}; /* movl %esi,%esi */
466 static const char f32_3[] =
467 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
468 static const char f32_4[] =
469 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
470 static const char f32_5[] =
471 {0x90, /* nop */
472 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
473 static const char f32_6[] =
474 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
475 static const char f32_7[] =
476 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
477 static const char f32_8[] =
478 {0x90, /* nop */
479 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
480 static const char f32_9[] =
481 {0x89,0xf6, /* movl %esi,%esi */
482 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
483 static const char f32_10[] =
484 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
485 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
486 static const char f32_11[] =
487 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
488 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
489 static const char f32_12[] =
490 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
491 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
492 static const char f32_13[] =
493 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
494 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
495 static const char f32_14[] =
496 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
497 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
498 static const char f32_15[] =
499 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
500 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 501 static const char f16_3[] =
502 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 503 static const char f16_4[] =
504 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
505 static const char f16_5[] =
506 {0x90, /* nop */
507 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
508 static const char f16_6[] =
509 {0x89,0xf6, /* mov %si,%si */
510 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
511 static const char f16_7[] =
512 {0x8d,0x74,0x00, /* lea 0(%si),%si */
513 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
514 static const char f16_8[] =
515 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
516 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
517 static const char *const f32_patt[] = {
518 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
519 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
520 };
521 static const char *const f16_patt[] = {
c3332e24 522 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 523 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
524 };
525
33fef721
JH		 526 if (count <= 0 || count > 15)
527 return;
3e73aa7c 528
33fef721
JH		 529 /* The recommended way to pad 64bit code is to use NOPs preceded by
530 maximally four 0x66 prefixes. Balance the size of nops. */
531 if (flag_code == CODE_64BIT)
252b5132 532 {
33fef721
JH		 533 int i;
534 int nnops = (count + 3) / 4;
535 int len = count / nnops;
536 int remains = count - nnops * len;
537 int pos = 0;
538
539 for (i = 0; i < remains; i++)
252b5132 540 {
33fef721
JH		 541 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
542 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
543 pos += len + 1;
544 }
545 for (; i < nnops; i++)
546 {
547 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
548 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
549 pos += len;
252b5132 550 }
252b5132 551 }
33fef721
JH		 552 else
553 if (flag_code == CODE_16BIT)
554 {
555 memcpy (fragP->fr_literal + fragP->fr_fix,
556 f16_patt[count - 1], count);
557 if (count > 8)
558 /* Adjust jump offset. */
559 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
560 }
561 else
562 memcpy (fragP->fr_literal + fragP->fr_fix,
563 f32_patt[count - 1], count);
564 fragP->fr_var = count;
252b5132
RH		 565}
566
252b5132
RH		 567static INLINE unsigned int
568mode_from_disp_size (t)
569 unsigned int t;
570{
3e73aa7c 571 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 572}
573
574static INLINE int
575fits_in_signed_byte (num)
847f7ad4 576 offsetT num;
252b5132
RH		 577{
578 return (num >= -128) && (num <= 127);
47926f60 579}
252b5132
RH		 580
581static INLINE int
582fits_in_unsigned_byte (num)
847f7ad4 583 offsetT num;
252b5132
RH		 584{
585 return (num & 0xff) == num;
47926f60 586}
252b5132
RH		 587
588static INLINE int
589fits_in_unsigned_word (num)
847f7ad4 590 offsetT num;
252b5132
RH		 591{
592 return (num & 0xffff) == num;
47926f60 593}
252b5132
RH		 594
595static INLINE int
596fits_in_signed_word (num)
847f7ad4 597 offsetT num;
252b5132
RH		 598{
599 return (-32768 <= num) && (num <= 32767);
47926f60 600}
3e73aa7c
JH		 601static INLINE int
602fits_in_signed_long (num)
603 offsetT num ATTRIBUTE_UNUSED;
604{
605#ifndef BFD64
606 return 1;
607#else
608 return (!(((offsetT) -1 << 31) & num)
609 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
610#endif
611} /* fits_in_signed_long() */
612static INLINE int
613fits_in_unsigned_long (num)
614 offsetT num ATTRIBUTE_UNUSED;
615{
616#ifndef BFD64
617 return 1;
618#else
619 return (num & (((offsetT) 2 << 31) - 1)) == num;
620#endif
621} /* fits_in_unsigned_long() */
252b5132
RH		 622
623static int
624smallest_imm_type (num)
847f7ad4 625 offsetT num;
252b5132 626{
a847613f 627 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 628 {
629 /* This code is disabled on the 486 because all the Imm1 forms
630 in the opcode table are slower on the i486. They're the
631 versions with the implicitly specified single-position
632 displacement, which has another syntax if you really want to
633 use that form. */
634 if (num == 1)
3e73aa7c 635 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 636 }
252b5132 637 return (fits_in_signed_byte (num)
3e73aa7c 638 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 639 : fits_in_unsigned_byte (num)
3e73aa7c 640 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 641 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 642 ? (Imm16 | Imm32 | Imm32S | Imm64)
643 : fits_in_signed_long (num)
644 ? (Imm32 | Imm32S | Imm64)
645 : fits_in_unsigned_long (num)
646 ? (Imm32 | Imm64)
647 : Imm64);
47926f60 648}
252b5132 649
847f7ad4
AM		 650static offsetT
651offset_in_range (val, size)
652 offsetT val;
653 int size;
654{
508866be 655 addressT mask;
ba2adb93 656
847f7ad4
AM		 657 switch (size)
658 {
508866be
L		 659 case 1: mask = ((addressT) 1 << 8) - 1; break;
660 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 661 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 662#ifdef BFD64
663 case 8: mask = ((addressT) 2 << 63) - 1; break;
664#endif
47926f60 665 default: abort ();
847f7ad4
AM		 666 }
667
ba2adb93 668 /* If BFD64, sign extend val. */
3e73aa7c
JH		 669 if (!use_rela_relocations)
670 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
671 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 672
47926f60 673 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 674 {
675 char buf1[40], buf2[40];
676
677 sprint_value (buf1, val);
678 sprint_value (buf2, val & mask);
679 as_warn (_("%s shortened to %s"), buf1, buf2);
680 }
681 return val & mask;
682}
683
252b5132
RH		 684/* Returns 0 if attempting to add a prefix where one from the same
685 class already exists, 1 if non rep/repne added, 2 if rep/repne
686 added. */
687static int
688add_prefix (prefix)
689 unsigned int prefix;
690{
691 int ret = 1;
692 int q;
693
29b0f896
AM		 694 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
695 && flag_code == CODE_64BIT)
3e73aa7c
JH		 696 q = REX_PREFIX;
697 else
698 switch (prefix)
699 {
700 default:
701 abort ();
702
703 case CS_PREFIX_OPCODE:
704 case DS_PREFIX_OPCODE:
705 case ES_PREFIX_OPCODE:
706 case FS_PREFIX_OPCODE:
707 case GS_PREFIX_OPCODE:
708 case SS_PREFIX_OPCODE:
709 q = SEG_PREFIX;
710 break;
252b5132 711
3e73aa7c
JH		 712 case REPNE_PREFIX_OPCODE:
713 case REPE_PREFIX_OPCODE:
714 ret = 2;
715 /* fall thru */
716 case LOCK_PREFIX_OPCODE:
717 q = LOCKREP_PREFIX;
718 break;
252b5132 719
3e73aa7c
JH		 720 case FWAIT_OPCODE:
721 q = WAIT_PREFIX;
722 break;
252b5132 723
3e73aa7c
JH		 724 case ADDR_PREFIX_OPCODE:
725 q = ADDR_PREFIX;
726 break;
252b5132 727
3e73aa7c
JH		 728 case DATA_PREFIX_OPCODE:
729 q = DATA_PREFIX;
730 break;
731 }
252b5132 732
29b0f896 733 if (i.prefix[q] != 0)
252b5132
RH		 734 {
735 as_bad (_("same type of prefix used twice"));
736 return 0;
737 }
738
739 i.prefixes += 1;
740 i.prefix[q] = prefix;
741 return ret;
742}
743
744static void
3e73aa7c 745set_code_flag (value)
e5cb08ac 746 int value;
eecb386c 747{
3e73aa7c
JH		 748 flag_code = value;
749 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
750 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
751 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
752 {
753 as_bad (_("64bit mode not supported on this CPU."));
754 }
755 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
756 {
757 as_bad (_("32bit mode not supported on this CPU."));
758 }
eecb386c
AM		 759 stackop_size = '\0';
760}
761
762static void
3e73aa7c
JH		 763set_16bit_gcc_code_flag (new_code_flag)
764 int new_code_flag;
252b5132 765{
3e73aa7c
JH		 766 flag_code = new_code_flag;
767 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
768 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
769 stackop_size = 'l';
252b5132
RH		 770}
771
772static void
773set_intel_syntax (syntax_flag)
eecb386c 774 int syntax_flag;
252b5132
RH		 775{
776 /* Find out if register prefixing is specified. */
777 int ask_naked_reg = 0;
778
779 SKIP_WHITESPACE ();
29b0f896 780 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 781 {
782 char *string = input_line_pointer;
783 int e = get_symbol_end ();
784
47926f60 785 if (strcmp (string, "prefix") == 0)
252b5132 786 ask_naked_reg = 1;
47926f60 787 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 788 ask_naked_reg = -1;
789 else
d0b47220 790 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 791 *input_line_pointer = e;
792 }
793 demand_empty_rest_of_line ();
c3332e24 794
252b5132
RH		 795 intel_syntax = syntax_flag;
796
797 if (ask_naked_reg == 0)
798 {
799#ifdef BFD_ASSEMBLER
800 allow_naked_reg = (intel_syntax
24eab124 801 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132 802#else
47926f60
KH		 803 /* Conservative default. */
804 allow_naked_reg = 0;
252b5132
RH		 805#endif
806 }
807 else
808 allow_naked_reg = (ask_naked_reg < 0);
809}
810
e413e4e9
AM		 811static void
812set_cpu_arch (dummy)
47926f60 813 int dummy ATTRIBUTE_UNUSED;
e413e4e9 814{
47926f60 815 SKIP_WHITESPACE ();
e413e4e9 816
29b0f896 817 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 818 {
819 char *string = input_line_pointer;
820 int e = get_symbol_end ();
821 int i;
822
823 for (i = 0; cpu_arch[i].name; i++)
824 {
825 if (strcmp (string, cpu_arch[i].name) == 0)
826 {
827 cpu_arch_name = cpu_arch[i].name;
fddf5b5b
AM		 828 cpu_arch_flags = (cpu_arch[i].flags
829 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
e413e4e9
AM		 830 break;
831 }
832 }
833 if (!cpu_arch[i].name)
834 as_bad (_("no such architecture: `%s'"), string);
835
836 *input_line_pointer = e;
837 }
838 else
839 as_bad (_("missing cpu architecture"));
840
fddf5b5b
AM		 841 no_cond_jump_promotion = 0;
842 if (*input_line_pointer == ','
29b0f896 843 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 844 {
845 char *string = ++input_line_pointer;
846 int e = get_symbol_end ();
847
848 if (strcmp (string, "nojumps") == 0)
849 no_cond_jump_promotion = 1;
850 else if (strcmp (string, "jumps") == 0)
851 ;
852 else
853 as_bad (_("no such architecture modifier: `%s'"), string);
854
855 *input_line_pointer = e;
856 }
857
e413e4e9
AM		 858 demand_empty_rest_of_line ();
859}
860
b9d79e03
JH		 861#ifdef BFD_ASSEMBLER
862unsigned long
863i386_mach ()
864{
865 if (!strcmp (default_arch, "x86_64"))
866 return bfd_mach_x86_64;
867 else if (!strcmp (default_arch, "i386"))
868 return bfd_mach_i386_i386;
869 else
870 as_fatal (_("Unknown architecture"));
871}
872#endif
873\f
252b5132
RH		 874void
875md_begin ()
876{
877 const char *hash_err;
878
47926f60 879 /* Initialize op_hash hash table. */
252b5132
RH		 880 op_hash = hash_new ();
881
882 {
29b0f896
AM		 883 const template *optab;
884 templates *core_optab;
252b5132 885
47926f60
KH		 886 /* Setup for loop. */
887 optab = i386_optab;
252b5132
RH		 888 core_optab = (templates *) xmalloc (sizeof (templates));
889 core_optab->start = optab;
890
891 while (1)
892 {
893 ++optab;
894 if (optab->name == NULL
895 || strcmp (optab->name, (optab - 1)->name) != 0)
896 {
897 /* different name --> ship out current template list;
47926f60 898 add to hash table; & begin anew. */
252b5132
RH		 899 core_optab->end = optab;
900 hash_err = hash_insert (op_hash,
901 (optab - 1)->name,
902 (PTR) core_optab);
903 if (hash_err)
904 {
252b5132
RH		 905 as_fatal (_("Internal Error: Can't hash %s: %s"),
906 (optab - 1)->name,
907 hash_err);
908 }
909 if (optab->name == NULL)
910 break;
911 core_optab = (templates *) xmalloc (sizeof (templates));
912 core_optab->start = optab;
913 }
914 }
915 }
916
47926f60 917 /* Initialize reg_hash hash table. */
252b5132
RH		 918 reg_hash = hash_new ();
919 {
29b0f896 920 const reg_entry *regtab;
252b5132
RH		 921
922 for (regtab = i386_regtab;
923 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
924 regtab++)
925 {
926 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
927 if (hash_err)
3e73aa7c
JH		 928 as_fatal (_("Internal Error: Can't hash %s: %s"),
929 regtab->reg_name,
930 hash_err);
252b5132
RH		 931 }
932 }
933
47926f60 934 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 935 {
29b0f896
AM		 936 int c;
937 char *p;
252b5132
RH		 938
939 for (c = 0; c < 256; c++)
940 {
3882b010 941 if (ISDIGIT (c))
252b5132
RH		 942 {
943 digit_chars[c] = c;
944 mnemonic_chars[c] = c;
945 register_chars[c] = c;
946 operand_chars[c] = c;
947 }
3882b010 948 else if (ISLOWER (c))
252b5132
RH		 949 {
950 mnemonic_chars[c] = c;
951 register_chars[c] = c;
952 operand_chars[c] = c;
953 }
3882b010 954 else if (ISUPPER (c))
252b5132 955 {
3882b010 956 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 957 register_chars[c] = mnemonic_chars[c];
958 operand_chars[c] = c;
959 }
960
3882b010 961 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 962 identifier_chars[c] = c;
963 else if (c >= 128)
964 {
965 identifier_chars[c] = c;
966 operand_chars[c] = c;
967 }
968 }
969
970#ifdef LEX_AT
971 identifier_chars['@'] = '@';
972#endif
252b5132
RH		 973 digit_chars['-'] = '-';
974 identifier_chars['_'] = '_';
975 identifier_chars['.'] = '.';
976
977 for (p = operand_special_chars; *p != '\0'; p++)
978 operand_chars[(unsigned char) *p] = *p;
979 }
980
981#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
982 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
983 {
984 record_alignment (text_section, 2);
985 record_alignment (data_section, 2);
986 record_alignment (bss_section, 2);
987 }
988#endif
989}
990
991void
992i386_print_statistics (file)
993 FILE *file;
994{
995 hash_print_statistics (file, "i386 opcode", op_hash);
996 hash_print_statistics (file, "i386 register", reg_hash);
997}
998\f
252b5132
RH		 999#ifdef DEBUG386
1000
ce8a8b2f 1001/* Debugging routines for md_assemble. */
252b5132
RH		 1002static void pi PARAMS ((char *, i386_insn *));
1003static void pte PARAMS ((template *));
1004static void pt PARAMS ((unsigned int));
1005static void pe PARAMS ((expressionS *));
1006static void ps PARAMS ((symbolS *));
1007
1008static void
1009pi (line, x)
1010 char *line;
1011 i386_insn *x;
1012{
09f131f2 1013 unsigned int i;
252b5132
RH		 1014
1015 fprintf (stdout, "%s: template ", line);
1016 pte (&x->tm);
09f131f2
JH		 1017 fprintf (stdout, " address: base %s index %s scale %x\n",
1018 x->base_reg ? x->base_reg->reg_name : "none",
1019 x->index_reg ? x->index_reg->reg_name : "none",
1020 x->log2_scale_factor);
1021 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1022 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1023 fprintf (stdout, " sib: base %x index %x scale %x\n",
1024 x->sib.base, x->sib.index, x->sib.scale);
1025 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
29b0f896
AM		 1026 (x->rex & REX_MODE64) != 0,
1027 (x->rex & REX_EXTX) != 0,
1028 (x->rex & REX_EXTY) != 0,
1029 (x->rex & REX_EXTZ) != 0);
252b5132
RH		 1030 for (i = 0; i < x->operands; i++)
1031 {
1032 fprintf (stdout, " #%d: ", i + 1);
1033 pt (x->types[i]);
1034 fprintf (stdout, "\n");
1035 if (x->types[i]
3f4438ab 1036 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1037 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1038 if (x->types[i] & Imm)
520dc8e8 1039 pe (x->op[i].imms);
252b5132 1040 if (x->types[i] & Disp)
520dc8e8 1041 pe (x->op[i].disps);
252b5132
RH		 1042 }
1043}
1044
1045static void
1046pte (t)
1047 template *t;
1048{
09f131f2 1049 unsigned int i;
252b5132 1050 fprintf (stdout, " %d operands ", t->operands);
47926f60 1051 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1052 if (t->extension_opcode != None)
1053 fprintf (stdout, "ext %x ", t->extension_opcode);
1054 if (t->opcode_modifier & D)
1055 fprintf (stdout, "D");
1056 if (t->opcode_modifier & W)
1057 fprintf (stdout, "W");
1058 fprintf (stdout, "\n");
1059 for (i = 0; i < t->operands; i++)
1060 {
1061 fprintf (stdout, " #%d type ", i + 1);
1062 pt (t->operand_types[i]);
1063 fprintf (stdout, "\n");
1064 }
1065}
1066
1067static void
1068pe (e)
1069 expressionS *e;
1070{
24eab124 1071 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1072 fprintf (stdout, " add_number %ld (%lx)\n",
1073 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1074 if (e->X_add_symbol)
1075 {
1076 fprintf (stdout, " add_symbol ");
1077 ps (e->X_add_symbol);
1078 fprintf (stdout, "\n");
1079 }
1080 if (e->X_op_symbol)
1081 {
1082 fprintf (stdout, " op_symbol ");
1083 ps (e->X_op_symbol);
1084 fprintf (stdout, "\n");
1085 }
1086}
1087
1088static void
1089ps (s)
1090 symbolS *s;
1091{
1092 fprintf (stdout, "%s type %s%s",
1093 S_GET_NAME (s),
1094 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1095 segment_name (S_GET_SEGMENT (s)));
1096}
1097
1098struct type_name
1099 {
1100 unsigned int mask;
1101 char *tname;
1102 }
1103
29b0f896 1104static const type_names[] =
252b5132
RH		 1105{
1106 { Reg8, "r8" },
1107 { Reg16, "r16" },
1108 { Reg32, "r32" },
09f131f2 1109 { Reg64, "r64" },
252b5132
RH		 1110 { Imm8, "i8" },
1111 { Imm8S, "i8s" },
1112 { Imm16, "i16" },
1113 { Imm32, "i32" },
09f131f2
JH		 1114 { Imm32S, "i32s" },
1115 { Imm64, "i64" },
252b5132
RH		 1116 { Imm1, "i1" },
1117 { BaseIndex, "BaseIndex" },
1118 { Disp8, "d8" },
1119 { Disp16, "d16" },
1120 { Disp32, "d32" },
09f131f2
JH		 1121 { Disp32S, "d32s" },
1122 { Disp64, "d64" },
252b5132
RH		 1123 { InOutPortReg, "InOutPortReg" },
1124 { ShiftCount, "ShiftCount" },
1125 { Control, "control reg" },
1126 { Test, "test reg" },
1127 { Debug, "debug reg" },
1128 { FloatReg, "FReg" },
1129 { FloatAcc, "FAcc" },
1130 { SReg2, "SReg2" },
1131 { SReg3, "SReg3" },
1132 { Acc, "Acc" },
1133 { JumpAbsolute, "Jump Absolute" },
1134 { RegMMX, "rMMX" },
3f4438ab 1135 { RegXMM, "rXMM" },
252b5132
RH		 1136 { EsSeg, "es" },
1137 { 0, "" }
1138};
1139
1140static void
1141pt (t)
1142 unsigned int t;
1143{
29b0f896 1144 const struct type_name *ty;
252b5132 1145
09f131f2
JH		 1146 for (ty = type_names; ty->mask; ty++)
1147 if (t & ty->mask)
1148 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1149 fflush (stdout);
1150}
1151
1152#endif /* DEBUG386 */
1153\f
252b5132 1154#ifdef BFD_ASSEMBLER
29b0f896
AM		 1155static bfd_reloc_code_real_type reloc
1156 PARAMS ((int, int, int, bfd_reloc_code_real_type));
252b5132
RH		 1157
1158static bfd_reloc_code_real_type
3e73aa7c 1159reloc (size, pcrel, sign, other)
252b5132
RH		 1160 int size;
1161 int pcrel;
3e73aa7c 1162 int sign;
252b5132
RH		 1163 bfd_reloc_code_real_type other;
1164{
47926f60
KH		 1165 if (other != NO_RELOC)
1166 return other;
252b5132
RH		 1167
1168 if (pcrel)
1169 {
3e73aa7c 1170 if (!sign)
e5cb08ac 1171 as_bad (_("There are no unsigned pc-relative relocations"));
252b5132
RH		 1172 switch (size)
1173 {
1174 case 1: return BFD_RELOC_8_PCREL;
1175 case 2: return BFD_RELOC_16_PCREL;
1176 case 4: return BFD_RELOC_32_PCREL;
1177 }
d0b47220 1178 as_bad (_("can not do %d byte pc-relative relocation"), size);
252b5132
RH		 1179 }
1180 else
1181 {
3e73aa7c 1182 if (sign)
e5cb08ac 1183 switch (size)
3e73aa7c
JH		 1184 {
1185 case 4: return BFD_RELOC_X86_64_32S;
1186 }
1187 else
1188 switch (size)
1189 {
1190 case 1: return BFD_RELOC_8;
1191 case 2: return BFD_RELOC_16;
1192 case 4: return BFD_RELOC_32;
1193 case 8: return BFD_RELOC_64;
1194 }
1195 as_bad (_("can not do %s %d byte relocation"),
1196 sign ? "signed" : "unsigned", size);
252b5132
RH		 1197 }
1198
bfb32b52 1199 abort ();
252b5132
RH		 1200 return BFD_RELOC_NONE;
1201}
1202
47926f60
KH		 1203/* Here we decide which fixups can be adjusted to make them relative to
1204 the beginning of the section instead of the symbol. Basically we need
1205 to make sure that the dynamic relocations are done correctly, so in
1206 some cases we force the original symbol to be used. */
1207
252b5132 1208int
c0c949c7 1209tc_i386_fix_adjustable (fixP)
31312f95 1210 fixS *fixP ATTRIBUTE_UNUSED;
252b5132 1211{
6d249963 1212#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
31312f95
AM		 1213 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
1214 return 1;
1215
a161fe53
AM		 1216 /* Don't adjust pc-relative references to merge sections in 64-bit
1217 mode. */
1218 if (use_rela_relocations
1219 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1220 && fixP->fx_pcrel)
252b5132 1221 return 0;
31312f95 1222
ce8a8b2f 1223 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1224 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1225 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1226 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1227 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1228 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1229 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1230 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1231 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1232 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1233 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1234 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3e73aa7c
JH		 1235 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1236 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1237 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
252b5132
RH		 1238 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1239 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1240 return 0;
31312f95 1241#endif
252b5132
RH		 1242 return 1;
1243}
1244#else
ec56dfb4 1245#define reloc(SIZE,PCREL,SIGN,OTHER) 0
c6682705 1246#define BFD_RELOC_8 0
ec56dfb4
L		 1247#define BFD_RELOC_16 0
1248#define BFD_RELOC_32 0
c6682705 1249#define BFD_RELOC_8_PCREL 0
ec56dfb4
L		 1250#define BFD_RELOC_16_PCREL 0
1251#define BFD_RELOC_32_PCREL 0
1252#define BFD_RELOC_386_PLT32 0
1253#define BFD_RELOC_386_GOT32 0
1254#define BFD_RELOC_386_GOTOFF 0
13ae64f3
JJ		 1255#define BFD_RELOC_386_TLS_GD 0
1256#define BFD_RELOC_386_TLS_LDM 0
1257#define BFD_RELOC_386_TLS_LDO_32 0
1258#define BFD_RELOC_386_TLS_IE_32 0
37e55690
JJ		 1259#define BFD_RELOC_386_TLS_IE 0
1260#define BFD_RELOC_386_TLS_GOTIE 0
13ae64f3
JJ		 1261#define BFD_RELOC_386_TLS_LE_32 0
1262#define BFD_RELOC_386_TLS_LE 0
ec56dfb4
L		 1263#define BFD_RELOC_X86_64_PLT32 0
1264#define BFD_RELOC_X86_64_GOT32 0
1265#define BFD_RELOC_X86_64_GOTPCREL 0
252b5132
RH		 1266#endif
1267
29b0f896 1268static int intel_float_operand PARAMS ((const char *mnemonic));
b4cac588
AM		 1269
1270static int
252b5132 1271intel_float_operand (mnemonic)
29b0f896 1272 const char *mnemonic;
252b5132 1273{
47926f60 1274 if (mnemonic[0] == 'f' && mnemonic[1] == 'i')
cc5ca5ce 1275 return 2;
252b5132
RH		 1276
1277 if (mnemonic[0] == 'f')
1278 return 1;
1279
1280 return 0;
1281}
1282
1283/* This is the guts of the machine-dependent assembler. LINE points to a
1284 machine dependent instruction. This function is supposed to emit
1285 the frags/bytes it assembles to. */
1286
1287void
1288md_assemble (line)
1289 char *line;
1290{
252b5132 1291 int j;
252b5132
RH		 1292 char mnemonic[MAX_MNEM_SIZE];
1293
47926f60 1294 /* Initialize globals. */
252b5132
RH		 1295 memset (&i, '\0', sizeof (i));
1296 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1297 i.reloc[j] = NO_RELOC;
252b5132
RH		 1298 memset (disp_expressions, '\0', sizeof (disp_expressions));
1299 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1300 save_stack_p = save_stack;
252b5132
RH		 1301
1302 /* First parse an instruction mnemonic & call i386_operand for the operands.
1303 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1304 start of a (possibly prefixed) mnemonic. */
252b5132 1305
29b0f896
AM		 1306 line = parse_insn (line, mnemonic);
1307 if (line == NULL)
1308 return;
252b5132 1309
29b0f896
AM		 1310 line = parse_operands (line, mnemonic);
1311 if (line == NULL)
1312 return;
252b5132 1313
29b0f896
AM		 1314 /* Now we've parsed the mnemonic into a set of templates, and have the
1315 operands at hand. */
1316
1317 /* All intel opcodes have reversed operands except for "bound" and
1318 "enter". We also don't reverse intersegment "jmp" and "call"
1319 instructions with 2 immediate operands so that the immediate segment
1320 precedes the offset, as it does when in AT&T mode. "enter" and the
1321 intersegment "jmp" and "call" instructions are the only ones that
1322 have two immediate operands. */
1323 if (intel_syntax && i.operands > 1
1324 && (strcmp (mnemonic, "bound") != 0)
1325 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1326 swap_operands ();
1327
1328 if (i.imm_operands)
1329 optimize_imm ();
1330
1331 if (i.disp_operands)
1332 optimize_disp ();
1333
1334 /* Next, we find a template that matches the given insn,
1335 making sure the overlap of the given operands types is consistent
1336 with the template operand types. */
252b5132 1337
29b0f896
AM		 1338 if (!match_template ())
1339 return;
252b5132 1340
cd61ebfe
AM		 1341 if (intel_syntax)
1342 {
1343 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1344 if (SYSV386_COMPAT
1345 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1346 i.tm.base_opcode ^= FloatR;
1347
1348 /* Zap movzx and movsx suffix. The suffix may have been set from
1349 "word ptr" or "byte ptr" on the source operand, but we'll use
1350 the suffix later to choose the destination register. */
1351 if ((i.tm.base_opcode & ~9) == 0x0fb6)
1352 i.suffix = 0;
1353 }
24eab124 1354
29b0f896
AM		 1355 if (i.tm.opcode_modifier & FWait)
1356 if (!add_prefix (FWAIT_OPCODE))
1357 return;
252b5132 1358
29b0f896
AM		 1359 /* Check string instruction segment overrides. */
1360 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1361 {
1362 if (!check_string ())
5dd0794d 1363 return;
29b0f896 1364 }
5dd0794d 1365
29b0f896
AM		 1366 if (!process_suffix ())
1367 return;
e413e4e9 1368
29b0f896
AM		 1369 /* Make still unresolved immediate matches conform to size of immediate
1370 given in i.suffix. */
1371 if (!finalize_imm ())
1372 return;
252b5132 1373
29b0f896
AM		 1374 if (i.types[0] & Imm1)
1375 i.imm_operands = 0; /* kludge for shift insns. */
1376 if (i.types[0] & ImplicitRegister)
1377 i.reg_operands--;
1378 if (i.types[1] & ImplicitRegister)
1379 i.reg_operands--;
1380 if (i.types[2] & ImplicitRegister)
1381 i.reg_operands--;
252b5132 1382
29b0f896
AM		 1383 if (i.tm.opcode_modifier & ImmExt)
1384 {
1385 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1386 opcode suffix which is coded in the same place as an 8-bit
1387 immediate field would be. Here we fake an 8-bit immediate
1388 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1389
29b0f896 1390 expressionS *exp;
252b5132 1391
29b0f896 1392 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1393
29b0f896
AM		 1394 exp = &im_expressions[i.imm_operands++];
1395 i.op[i.operands].imms = exp;
1396 i.types[i.operands++] = Imm8;
1397 exp->X_op = O_constant;
1398 exp->X_add_number = i.tm.extension_opcode;
1399 i.tm.extension_opcode = None;
1400 }
252b5132 1401
29b0f896
AM		 1402 /* For insns with operands there are more diddles to do to the opcode. */
1403 if (i.operands)
1404 {
1405 if (!process_operands ())
1406 return;
1407 }
1408 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1409 {
1410 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1411 as_warn (_("translating to `%sp'"), i.tm.name);
1412 }
252b5132 1413
29b0f896
AM		 1414 /* Handle conversion of 'int $3' --> special int3 insn. */
1415 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1416 {
1417 i.tm.base_opcode = INT3_OPCODE;
1418 i.imm_operands = 0;
1419 }
252b5132 1420
29b0f896
AM		 1421 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1422 && i.op[0].disps->X_op == O_constant)
1423 {
1424 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1425 the absolute address given by the constant. Since ix86 jumps and
1426 calls are pc relative, we need to generate a reloc. */
1427 i.op[0].disps->X_add_symbol = &abs_symbol;
1428 i.op[0].disps->X_op = O_symbol;
1429 }
252b5132 1430
29b0f896
AM		 1431 if ((i.tm.opcode_modifier & Rex64) != 0)
1432 i.rex |= REX_MODE64;
252b5132 1433
29b0f896
AM		 1434 /* For 8 bit registers we need an empty rex prefix. Also if the
1435 instruction already has a prefix, we need to convert old
1436 registers to new ones. */
773f551c 1437
29b0f896
AM		 1438 if (((i.types[0] & Reg8) != 0
1439 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1440 || ((i.types[1] & Reg8) != 0
1441 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1442 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1443 && i.rex != 0))
1444 {
1445 int x;
726c5dcd 1446
29b0f896
AM		 1447 i.rex |= REX_OPCODE;
1448 for (x = 0; x < 2; x++)
1449 {
1450 /* Look for 8 bit operand that uses old registers. */
1451 if ((i.types[x] & Reg8) != 0
1452 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1453 {
29b0f896
AM		 1454 /* In case it is "hi" register, give up. */
1455 if (i.op[x].regs->reg_num > 3)
1456 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix.\n"),
1457 i.op[x].regs->reg_name);
773f551c 1458
29b0f896
AM		 1459 /* Otherwise it is equivalent to the extended register.
1460 Since the encoding doesn't change this is merely
1461 cosmetic cleanup for debug output. */
1462
1463 i.op[x].regs = i.op[x].regs + 8;
773f551c 1464 }
29b0f896
AM		 1465 }
1466 }
773f551c 1467
29b0f896
AM		 1468 if (i.rex != 0)
1469 add_prefix (REX_OPCODE | i.rex);
1470
1471 /* We are ready to output the insn. */
1472 output_insn ();
1473}
1474
1475static char *
1476parse_insn (line, mnemonic)
1477 char *line;
1478 char *mnemonic;
1479{
1480 char *l = line;
1481 char *token_start = l;
1482 char *mnem_p;
1483
1484 /* Non-zero if we found a prefix only acceptable with string insns. */
1485 const char *expecting_string_instruction = NULL;
45288df1 1486
29b0f896
AM		 1487 while (1)
1488 {
1489 mnem_p = mnemonic;
1490 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1491 {
1492 mnem_p++;
1493 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1494 {
29b0f896
AM		 1495 as_bad (_("no such instruction: `%s'"), token_start);
1496 return NULL;
1497 }
1498 l++;
1499 }
1500 if (!is_space_char (*l)
1501 && *l != END_OF_INSN
1502 && *l != PREFIX_SEPARATOR
1503 && *l != ',')
1504 {
1505 as_bad (_("invalid character %s in mnemonic"),
1506 output_invalid (*l));
1507 return NULL;
1508 }
1509 if (token_start == l)
1510 {
1511 if (*l == PREFIX_SEPARATOR)
1512 as_bad (_("expecting prefix; got nothing"));
1513 else
1514 as_bad (_("expecting mnemonic; got nothing"));
1515 return NULL;
1516 }
45288df1 1517
29b0f896
AM		 1518 /* Look up instruction (or prefix) via hash table. */
1519 current_templates = hash_find (op_hash, mnemonic);
47926f60 1520
29b0f896
AM		 1521 if (*l != END_OF_INSN
1522 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1523 && current_templates
1524 && (current_templates->start->opcode_modifier & IsPrefix))
1525 {
1526 /* If we are in 16-bit mode, do not allow addr16 or data16.
1527 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1528 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1529 && flag_code != CODE_64BIT
1530 && (((current_templates->start->opcode_modifier & Size32) != 0)
1531 ^ (flag_code == CODE_16BIT)))
1532 {
1533 as_bad (_("redundant %s prefix"),
1534 current_templates->start->name);
1535 return NULL;
45288df1 1536 }
29b0f896
AM		 1537 /* Add prefix, checking for repeated prefixes. */
1538 switch (add_prefix (current_templates->start->base_opcode))
1539 {
1540 case 0:
1541 return NULL;
1542 case 2:
1543 expecting_string_instruction = current_templates->start->name;
1544 break;
1545 }
1546 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1547 token_start = ++l;
1548 }
1549 else
1550 break;
1551 }
45288df1 1552
29b0f896
AM		 1553 if (!current_templates)
1554 {
1555 /* See if we can get a match by trimming off a suffix. */
1556 switch (mnem_p[-1])
1557 {
1558 case WORD_MNEM_SUFFIX:
1559 case BYTE_MNEM_SUFFIX:
1560 case QWORD_MNEM_SUFFIX:
1561 i.suffix = mnem_p[-1];
1562 mnem_p[-1] = '\0';
1563 current_templates = hash_find (op_hash, mnemonic);
1564 break;
1565 case SHORT_MNEM_SUFFIX:
1566 case LONG_MNEM_SUFFIX:
1567 if (!intel_syntax)
1568 {
1569 i.suffix = mnem_p[-1];
1570 mnem_p[-1] = '\0';
1571 current_templates = hash_find (op_hash, mnemonic);
1572 }
1573 break;
252b5132 1574
29b0f896
AM		 1575 /* Intel Syntax. */
1576 case 'd':
1577 if (intel_syntax)
1578 {
1579 if (intel_float_operand (mnemonic))
1580 i.suffix = SHORT_MNEM_SUFFIX;
1581 else
1582 i.suffix = LONG_MNEM_SUFFIX;
1583 mnem_p[-1] = '\0';
1584 current_templates = hash_find (op_hash, mnemonic);
1585 }
1586 break;
1587 }
1588 if (!current_templates)
1589 {
1590 as_bad (_("no such instruction: `%s'"), token_start);
1591 return NULL;
1592 }
1593 }
252b5132 1594
29b0f896
AM		 1595 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
1596 {
1597 /* Check for a branch hint. We allow ",pt" and ",pn" for
1598 predict taken and predict not taken respectively.
1599 I'm not sure that branch hints actually do anything on loop
1600 and jcxz insns (JumpByte) for current Pentium4 chips. They
1601 may work in the future and it doesn't hurt to accept them
1602 now. */
1603 if (l[0] == ',' && l[1] == 'p')
1604 {
1605 if (l[2] == 't')
1606 {
1607 if (!add_prefix (DS_PREFIX_OPCODE))
1608 return NULL;
1609 l += 3;
1610 }
1611 else if (l[2] == 'n')
1612 {
1613 if (!add_prefix (CS_PREFIX_OPCODE))
1614 return NULL;
1615 l += 3;
1616 }
1617 }
1618 }
1619 /* Any other comma loses. */
1620 if (*l == ',')
1621 {
1622 as_bad (_("invalid character %s in mnemonic"),
1623 output_invalid (*l));
1624 return NULL;
1625 }
252b5132 1626
29b0f896
AM		 1627 /* Check if instruction is supported on specified architecture. */
1628 if ((current_templates->start->cpu_flags & ~(Cpu64 | CpuNo64))
1629 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64)))
1630 {
1631 as_warn (_("`%s' is not supported on `%s'"),
1632 current_templates->start->name, cpu_arch_name);
1633 }
1634 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
1635 {
1636 as_warn (_("use .code16 to ensure correct addressing mode"));
1637 }
252b5132 1638
29b0f896
AM		 1639 /* Check for rep/repne without a string instruction. */
1640 if (expecting_string_instruction
1641 && !(current_templates->start->opcode_modifier & IsString))
1642 {
1643 as_bad (_("expecting string instruction after `%s'"),
1644 expecting_string_instruction);
1645 return NULL;
1646 }
252b5132 1647
29b0f896
AM		 1648 return l;
1649}
252b5132 1650
29b0f896
AM		 1651static char *
1652parse_operands (l, mnemonic)
1653 char *l;
1654 const char *mnemonic;
1655{
1656 char *token_start;
3138f287 1657
29b0f896
AM		 1658 /* 1 if operand is pending after ','. */
1659 unsigned int expecting_operand = 0;
252b5132 1660
29b0f896
AM		 1661 /* Non-zero if operand parens not balanced. */
1662 unsigned int paren_not_balanced;
1663
1664 while (*l != END_OF_INSN)
1665 {
1666 /* Skip optional white space before operand. */
1667 if (is_space_char (*l))
1668 ++l;
1669 if (!is_operand_char (*l) && *l != END_OF_INSN)
1670 {
1671 as_bad (_("invalid character %s before operand %d"),
1672 output_invalid (*l),
1673 i.operands + 1);
1674 return NULL;
1675 }
1676 token_start = l; /* after white space */
1677 paren_not_balanced = 0;
1678 while (paren_not_balanced || *l != ',')
1679 {
1680 if (*l == END_OF_INSN)
1681 {
1682 if (paren_not_balanced)
1683 {
1684 if (!intel_syntax)
1685 as_bad (_("unbalanced parenthesis in operand %d."),
1686 i.operands + 1);
1687 else
1688 as_bad (_("unbalanced brackets in operand %d."),
1689 i.operands + 1);
1690 return NULL;
1691 }
1692 else
1693 break; /* we are done */
1694 }
1695 else if (!is_operand_char (*l) && !is_space_char (*l))
1696 {
1697 as_bad (_("invalid character %s in operand %d"),
1698 output_invalid (*l),
1699 i.operands + 1);
1700 return NULL;
1701 }
1702 if (!intel_syntax)
1703 {
1704 if (*l == '(')
1705 ++paren_not_balanced;
1706 if (*l == ')')
1707 --paren_not_balanced;
1708 }
1709 else
1710 {
1711 if (*l == '[')
1712 ++paren_not_balanced;
1713 if (*l == ']')
1714 --paren_not_balanced;
1715 }
1716 l++;
1717 }
1718 if (l != token_start)
1719 { /* Yes, we've read in another operand. */
1720 unsigned int operand_ok;
1721 this_operand = i.operands++;
1722 if (i.operands > MAX_OPERANDS)
1723 {
1724 as_bad (_("spurious operands; (%d operands/instruction max)"),
1725 MAX_OPERANDS);
1726 return NULL;
1727 }
1728 /* Now parse operand adding info to 'i' as we go along. */
1729 END_STRING_AND_SAVE (l);
1730
1731 if (intel_syntax)
1732 operand_ok =
1733 i386_intel_operand (token_start,
1734 intel_float_operand (mnemonic));
1735 else
1736 operand_ok = i386_operand (token_start);
1737
1738 RESTORE_END_STRING (l);
1739 if (!operand_ok)
1740 return NULL;
1741 }
1742 else
1743 {
1744 if (expecting_operand)
1745 {
1746 expecting_operand_after_comma:
1747 as_bad (_("expecting operand after ','; got nothing"));
1748 return NULL;
1749 }
1750 if (*l == ',')
1751 {
1752 as_bad (_("expecting operand before ','; got nothing"));
1753 return NULL;
1754 }
1755 }
7f3f1ea2 1756
29b0f896
AM		 1757 /* Now *l must be either ',' or END_OF_INSN. */
1758 if (*l == ',')
1759 {
1760 if (*++l == END_OF_INSN)
1761 {
1762 /* Just skip it, if it's \n complain. */
1763 goto expecting_operand_after_comma;
1764 }
1765 expecting_operand = 1;
1766 }
1767 }
1768 return l;
1769}
7f3f1ea2 1770
29b0f896
AM		 1771static void
1772swap_operands ()
1773{
1774 union i386_op temp_op;
1775 unsigned int temp_type;
1776 RELOC_ENUM temp_reloc;
1777 int xchg1 = 0;
1778 int xchg2 = 0;
252b5132 1779
29b0f896
AM		 1780 if (i.operands == 2)
1781 {
1782 xchg1 = 0;
1783 xchg2 = 1;
1784 }
1785 else if (i.operands == 3)
1786 {
1787 xchg1 = 0;
1788 xchg2 = 2;
1789 }
1790 temp_type = i.types[xchg2];
1791 i.types[xchg2] = i.types[xchg1];
1792 i.types[xchg1] = temp_type;
1793 temp_op = i.op[xchg2];
1794 i.op[xchg2] = i.op[xchg1];
1795 i.op[xchg1] = temp_op;
1796 temp_reloc = i.reloc[xchg2];
1797 i.reloc[xchg2] = i.reloc[xchg1];
1798 i.reloc[xchg1] = temp_reloc;
1799
1800 if (i.mem_operands == 2)
1801 {
1802 const seg_entry *temp_seg;
1803 temp_seg = i.seg[0];
1804 i.seg[0] = i.seg[1];
1805 i.seg[1] = temp_seg;
1806 }
1807}
252b5132 1808
29b0f896
AM		 1809/* Try to ensure constant immediates are represented in the smallest
1810 opcode possible. */
1811static void
1812optimize_imm ()
1813{
1814 char guess_suffix = 0;
1815 int op;
252b5132 1816
29b0f896
AM		 1817 if (i.suffix)
1818 guess_suffix = i.suffix;
1819 else if (i.reg_operands)
1820 {
1821 /* Figure out a suffix from the last register operand specified.
1822 We can't do this properly yet, ie. excluding InOutPortReg,
1823 but the following works for instructions with immediates.
1824 In any case, we can't set i.suffix yet. */
1825 for (op = i.operands; --op >= 0;)
1826 if (i.types[op] & Reg)
252b5132 1827 {
29b0f896
AM		 1828 if (i.types[op] & Reg8)
1829 guess_suffix = BYTE_MNEM_SUFFIX;
1830 else if (i.types[op] & Reg16)
1831 guess_suffix = WORD_MNEM_SUFFIX;
1832 else if (i.types[op] & Reg32)
1833 guess_suffix = LONG_MNEM_SUFFIX;
1834 else if (i.types[op] & Reg64)
1835 guess_suffix = QWORD_MNEM_SUFFIX;
1836 break;
252b5132 1837 }
29b0f896
AM		 1838 }
1839 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
1840 guess_suffix = WORD_MNEM_SUFFIX;
1841
1842 for (op = i.operands; --op >= 0;)
1843 if (i.types[op] & Imm)
1844 {
1845 switch (i.op[op].imms->X_op)
252b5132 1846 {
29b0f896
AM		 1847 case O_constant:
1848 /* If a suffix is given, this operand may be shortened. */
1849 switch (guess_suffix)
252b5132 1850 {
29b0f896
AM		 1851 case LONG_MNEM_SUFFIX:
1852 i.types[op] |= Imm32 | Imm64;
1853 break;
1854 case WORD_MNEM_SUFFIX:
1855 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
1856 break;
1857 case BYTE_MNEM_SUFFIX:
1858 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
1859 break;
252b5132 1860 }
252b5132 1861
29b0f896
AM		 1862 /* If this operand is at most 16 bits, convert it
1863 to a signed 16 bit number before trying to see
1864 whether it will fit in an even smaller size.
1865 This allows a 16-bit operand such as $0xffe0 to
1866 be recognised as within Imm8S range. */
1867 if ((i.types[op] & Imm16)
1868 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 1869 {
29b0f896
AM		 1870 i.op[op].imms->X_add_number =
1871 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
1872 }
1873 if ((i.types[op] & Imm32)
1874 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
1875 == 0))
1876 {
1877 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
1878 ^ ((offsetT) 1 << 31))
1879 - ((offsetT) 1 << 31));
1880 }
1881 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 1882
29b0f896
AM		 1883 /* We must avoid matching of Imm32 templates when 64bit
1884 only immediate is available. */
1885 if (guess_suffix == QWORD_MNEM_SUFFIX)
1886 i.types[op] &= ~Imm32;
1887 break;
252b5132 1888
29b0f896
AM		 1889 case O_absent:
1890 case O_register:
1891 abort ();
1892
1893 /* Symbols and expressions. */
1894 default:
1895 /* Convert symbolic operand to proper sizes for matching. */
1896 switch (guess_suffix)
1897 {
1898 case QWORD_MNEM_SUFFIX:
1899 i.types[op] = Imm64 | Imm32S;
1900 break;
1901 case LONG_MNEM_SUFFIX:
1902 i.types[op] = Imm32 | Imm64;
1903 break;
1904 case WORD_MNEM_SUFFIX:
1905 i.types[op] = Imm16 | Imm32 | Imm64;
1906 break;
1907 break;
1908 case BYTE_MNEM_SUFFIX:
1909 i.types[op] = Imm8 | Imm8S | Imm16 | Imm32S | Imm32;
1910 break;
1911 break;
252b5132 1912 }
29b0f896 1913 break;
252b5132 1914 }
29b0f896
AM		 1915 }
1916}
47926f60 1917
29b0f896
AM		 1918/* Try to use the smallest displacement type too. */
1919static void
1920optimize_disp ()
1921{
1922 int op;
3e73aa7c 1923
29b0f896
AM		 1924 for (op = i.operands; --op >= 0;)
1925 if ((i.types[op] & Disp) && i.op[op].disps->X_op == O_constant)
252b5132 1926 {
29b0f896
AM		 1927 offsetT disp = i.op[op].disps->X_add_number;
1928
1929 if (i.types[op] & Disp16)
252b5132 1930 {
29b0f896
AM		 1931 /* We know this operand is at most 16 bits, so
1932 convert to a signed 16 bit number before trying
1933 to see whether it will fit in an even smaller
1934 size. */
1935
1936 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
252b5132 1937 }
29b0f896 1938 else if (i.types[op] & Disp32)
252b5132 1939 {
29b0f896
AM		 1940 /* We know this operand is at most 32 bits, so convert to a
1941 signed 32 bit number before trying to see whether it will
1942 fit in an even smaller size. */
1943 disp &= (((offsetT) 2 << 31) - 1);
1944 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 1945 }
29b0f896 1946 if (flag_code == CODE_64BIT)
252b5132 1947 {
29b0f896
AM		 1948 if (fits_in_signed_long (disp))
1949 i.types[op] |= Disp32S;
1950 if (fits_in_unsigned_long (disp))
1951 i.types[op] |= Disp32;
252b5132 1952 }
29b0f896
AM		 1953 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
1954 && fits_in_signed_byte (disp))
1955 i.types[op] |= Disp8;
252b5132 1956 }
29b0f896
AM		 1957}
1958
1959static int
1960match_template ()
1961{
1962 /* Points to template once we've found it. */
1963 const template *t;
1964 unsigned int overlap0, overlap1, overlap2;
1965 unsigned int found_reverse_match;
1966 int suffix_check;
1967
1968#define MATCH(overlap, given, template) \
1969 ((overlap & ~JumpAbsolute) \
1970 && (((given) & (BaseIndex | JumpAbsolute)) \
1971 == ((overlap) & (BaseIndex | JumpAbsolute))))
1972
1973 /* If given types r0 and r1 are registers they must be of the same type
1974 unless the expected operand type register overlap is null.
1975 Note that Acc in a template matches every size of reg. */
1976#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1977 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
1978 || ((g0) & Reg) == ((g1) & Reg) \
1979 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1980
1981 overlap0 = 0;
1982 overlap1 = 0;
1983 overlap2 = 0;
1984 found_reverse_match = 0;
1985 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
1986 ? No_bSuf
1987 : (i.suffix == WORD_MNEM_SUFFIX
1988 ? No_wSuf
1989 : (i.suffix == SHORT_MNEM_SUFFIX
1990 ? No_sSuf
1991 : (i.suffix == LONG_MNEM_SUFFIX
1992 ? No_lSuf
1993 : (i.suffix == QWORD_MNEM_SUFFIX
1994 ? No_qSuf
1995 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
1996 ? No_xSuf : 0))))));
1997
1998 for (t = current_templates->start;
1999 t < current_templates->end;
2000 t++)
2001 {
2002 /* Must have right number of operands. */
2003 if (i.operands != t->operands)
2004 continue;
2005
2006 /* Check the suffix, except for some instructions in intel mode. */
2007 if ((t->opcode_modifier & suffix_check)
2008 && !(intel_syntax
2009 && (t->opcode_modifier & IgnoreSize))
2010 && !(intel_syntax
2011 && t->base_opcode == 0xd9
2012 && (t->extension_opcode == 5 /* 0xd9,5 "fldcw" */
2013 || t->extension_opcode == 7))) /* 0xd9,7 "f{n}stcw" */
2014 continue;
2015
2016 /* Do not verify operands when there are none. */
2017 else if (!t->operands)
2018 {
2019 if (t->cpu_flags & ~cpu_arch_flags)
2020 continue;
2021 /* We've found a match; break out of loop. */
2022 break;
2023 }
252b5132 2024
29b0f896
AM		 2025 overlap0 = i.types[0] & t->operand_types[0];
2026 switch (t->operands)
2027 {
2028 case 1:
2029 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
2030 continue;
2031 break;
2032 case 2:
2033 case 3:
2034 overlap1 = i.types[1] & t->operand_types[1];
2035 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
2036 || !MATCH (overlap1, i.types[1], t->operand_types[1])
2037 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2038 t->operand_types[0],
2039 overlap1, i.types[1],
2040 t->operand_types[1]))
2041 {
2042 /* Check if other direction is valid ... */
2043 if ((t->opcode_modifier & (D | FloatD)) == 0)
2044 continue;
2045
2046 /* Try reversing direction of operands. */
2047 overlap0 = i.types[0] & t->operand_types[1];
2048 overlap1 = i.types[1] & t->operand_types[0];
2049 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
2050 || !MATCH (overlap1, i.types[1], t->operand_types[0])
2051 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2052 t->operand_types[1],
2053 overlap1, i.types[1],
2054 t->operand_types[0]))
2055 {
2056 /* Does not match either direction. */
2057 continue;
2058 }
2059 /* found_reverse_match holds which of D or FloatDR
2060 we've found. */
2061 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2062 }
2063 /* Found a forward 2 operand match here. */
2064 else if (t->operands == 3)
2065 {
2066 /* Here we make use of the fact that there are no
2067 reverse match 3 operand instructions, and all 3
2068 operand instructions only need to be checked for
2069 register consistency between operands 2 and 3. */
2070 overlap2 = i.types[2] & t->operand_types[2];
2071 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
2072 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2073 t->operand_types[1],
2074 overlap2, i.types[2],
2075 t->operand_types[2]))
2076
2077 continue;
2078 }
2079 /* Found either forward/reverse 2 or 3 operand match here:
2080 slip through to break. */
2081 }
2082 if (t->cpu_flags & ~cpu_arch_flags)
2083 {
2084 found_reverse_match = 0;
2085 continue;
2086 }
2087 /* We've found a match; break out of loop. */
2088 break;
2089 }
2090
2091 if (t == current_templates->end)
2092 {
2093 /* We found no match. */
2094 as_bad (_("suffix or operands invalid for `%s'"),
2095 current_templates->start->name);
2096 return 0;
2097 }
252b5132 2098
29b0f896
AM		 2099 if (!quiet_warnings)
2100 {
2101 if (!intel_syntax
2102 && ((i.types[0] & JumpAbsolute)
2103 != (t->operand_types[0] & JumpAbsolute)))
2104 {
2105 as_warn (_("indirect %s without `*'"), t->name);
2106 }
2107
2108 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2109 == (IsPrefix | IgnoreSize))
2110 {
2111 /* Warn them that a data or address size prefix doesn't
2112 affect assembly of the next line of code. */
2113 as_warn (_("stand-alone `%s' prefix"), t->name);
2114 }
2115 }
2116
2117 /* Copy the template we found. */
2118 i.tm = *t;
2119 if (found_reverse_match)
2120 {
2121 /* If we found a reverse match we must alter the opcode
2122 direction bit. found_reverse_match holds bits to change
2123 (different for int & float insns). */
2124
2125 i.tm.base_opcode ^= found_reverse_match;
2126
2127 i.tm.operand_types[0] = t->operand_types[1];
2128 i.tm.operand_types[1] = t->operand_types[0];
2129 }
2130
2131 return 1;
2132}
2133
2134static int
2135check_string ()
2136{
2137 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2138 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2139 {
2140 if (i.seg[0] != NULL && i.seg[0] != &es)
2141 {
2142 as_bad (_("`%s' operand %d must use `%%es' segment"),
2143 i.tm.name,
2144 mem_op + 1);
2145 return 0;
2146 }
2147 /* There's only ever one segment override allowed per instruction.
2148 This instruction possibly has a legal segment override on the
2149 second operand, so copy the segment to where non-string
2150 instructions store it, allowing common code. */
2151 i.seg[0] = i.seg[1];
2152 }
2153 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2154 {
2155 if (i.seg[1] != NULL && i.seg[1] != &es)
2156 {
2157 as_bad (_("`%s' operand %d must use `%%es' segment"),
2158 i.tm.name,
2159 mem_op + 2);
2160 return 0;
2161 }
2162 }
2163 return 1;
2164}
2165
2166static int
2167process_suffix ()
2168{
2169 /* If matched instruction specifies an explicit instruction mnemonic
2170 suffix, use it. */
2171 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2172 {
2173 if (i.tm.opcode_modifier & Size16)
2174 i.suffix = WORD_MNEM_SUFFIX;
2175 else if (i.tm.opcode_modifier & Size64)
2176 i.suffix = QWORD_MNEM_SUFFIX;
2177 else
2178 i.suffix = LONG_MNEM_SUFFIX;
2179 }
2180 else if (i.reg_operands)
2181 {
2182 /* If there's no instruction mnemonic suffix we try to invent one
2183 based on register operands. */
2184 if (!i.suffix)
2185 {
2186 /* We take i.suffix from the last register operand specified,
2187 Destination register type is more significant than source
2188 register type. */
2189 int op;
2190 for (op = i.operands; --op >= 0;)
2191 if ((i.types[op] & Reg)
2192 && !(i.tm.operand_types[op] & InOutPortReg))
2193 {
2194 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2195 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2196 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2197 LONG_MNEM_SUFFIX);
2198 break;
2199 }
2200 }
2201 else if (i.suffix == BYTE_MNEM_SUFFIX)
2202 {
2203 if (!check_byte_reg ())
2204 return 0;
2205 }
2206 else if (i.suffix == LONG_MNEM_SUFFIX)
2207 {
2208 if (!check_long_reg ())
2209 return 0;
2210 }
2211 else if (i.suffix == QWORD_MNEM_SUFFIX)
2212 {
2213 if (!check_qword_reg ())
2214 return 0;
2215 }
2216 else if (i.suffix == WORD_MNEM_SUFFIX)
2217 {
2218 if (!check_word_reg ())
2219 return 0;
2220 }
2221 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2222 /* Do nothing if the instruction is going to ignore the prefix. */
2223 ;
2224 else
2225 abort ();
2226 }
2227 else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix)
2228 {
2229 i.suffix = stackop_size;
2230 }
252b5132 2231
29b0f896
AM		 2232 /* Change the opcode based on the operand size given by i.suffix;
2233 We need not change things for byte insns. */
252b5132 2234
29b0f896
AM		 2235 if (!i.suffix && (i.tm.opcode_modifier & W))
2236 {
2237 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2238 return 0;
2239 }
252b5132 2240
29b0f896
AM		 2241 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2242 {
2243 /* It's not a byte, select word/dword operation. */
2244 if (i.tm.opcode_modifier & W)
2245 {
2246 if (i.tm.opcode_modifier & ShortForm)
2247 i.tm.base_opcode |= 8;
2248 else
2249 i.tm.base_opcode |= 1;
2250 }
0f3f3d8b 2251
29b0f896
AM		 2252 /* Now select between word & dword operations via the operand
2253 size prefix, except for instructions that will ignore this
2254 prefix anyway. */
2255 if (i.suffix != QWORD_MNEM_SUFFIX
9146926a
AM		 2256 && !(i.tm.opcode_modifier & IgnoreSize)
2257 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2258 || (flag_code == CODE_64BIT
2259 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 2260 {
2261 unsigned int prefix = DATA_PREFIX_OPCODE;
29b0f896
AM		 2262 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2263 prefix = ADDR_PREFIX_OPCODE;
252b5132 2264
29b0f896
AM		 2265 if (!add_prefix (prefix))
2266 return 0;
24eab124 2267 }
252b5132 2268
29b0f896
AM		 2269 /* Set mode64 for an operand. */
2270 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 2271 && flag_code == CODE_64BIT
29b0f896 2272 && (i.tm.opcode_modifier & NoRex64) == 0)
9146926a 2273 i.rex |= REX_MODE64;
3e73aa7c 2274
29b0f896
AM		 2275 /* Size floating point instruction. */
2276 if (i.suffix == LONG_MNEM_SUFFIX)
2277 {
2278 if (i.tm.opcode_modifier & FloatMF)
2279 i.tm.base_opcode ^= 4;
2280 }
2281 }
7ecd2f8b 2282
29b0f896
AM		 2283 return 1;
2284}
3e73aa7c 2285
29b0f896
AM		 2286static int
2287check_byte_reg ()
2288{
2289 int op;
2290 for (op = i.operands; --op >= 0;)
2291 {
2292 /* If this is an eight bit register, it's OK. If it's the 16 or
2293 32 bit version of an eight bit register, we will just use the
2294 low portion, and that's OK too. */
2295 if (i.types[op] & Reg8)
2296 continue;
2297
2298 /* movzx and movsx should not generate this warning. */
2299 if (intel_syntax
2300 && (i.tm.base_opcode == 0xfb7
2301 || i.tm.base_opcode == 0xfb6
2302 || i.tm.base_opcode == 0x63
2303 || i.tm.base_opcode == 0xfbe
2304 || i.tm.base_opcode == 0xfbf))
2305 continue;
2306
2307 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4
2308#if 0
2309 /* Check that the template allows eight bit regs. This
2310 kills insns such as `orb $1,%edx', which maybe should be
2311 allowed. */
2312 && (i.tm.operand_types[op] & (Reg8 | InOutPortReg))
2313#endif
2314 )
2315 {
2316 /* Prohibit these changes in the 64bit mode, since the
2317 lowering is more complicated. */
2318 if (flag_code == CODE_64BIT
2319 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2320 {
0f3f3d8b 2321 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2322 i.op[op].regs->reg_name,
2323 i.suffix);
2324 return 0;
2325 }
2326#if REGISTER_WARNINGS
2327 if (!quiet_warnings
2328 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2329 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2330 (i.op[op].regs + (i.types[op] & Reg16
2331 ? REGNAM_AL - REGNAM_AX
2332 : REGNAM_AL - REGNAM_EAX))->reg_name,
2333 i.op[op].regs->reg_name,
2334 i.suffix);
2335#endif
2336 continue;
2337 }
2338 /* Any other register is bad. */
2339 if (i.types[op] & (Reg | RegMMX | RegXMM
2340 | SReg2 | SReg3
2341 | Control | Debug | Test
2342 | FloatReg | FloatAcc))
2343 {
2344 as_bad (_("`%%%s' not allowed with `%s%c'"),
2345 i.op[op].regs->reg_name,
2346 i.tm.name,
2347 i.suffix);
2348 return 0;
2349 }
2350 }
2351 return 1;
2352}
2353
2354static int
2355check_long_reg ()
2356{
2357 int op;
2358
2359 for (op = i.operands; --op >= 0;)
2360 /* Reject eight bit registers, except where the template requires
2361 them. (eg. movzb) */
2362 if ((i.types[op] & Reg8) != 0
2363 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2364 {
2365 as_bad (_("`%%%s' not allowed with `%s%c'"),
2366 i.op[op].regs->reg_name,
2367 i.tm.name,
2368 i.suffix);
2369 return 0;
2370 }
2371 /* Warn if the e prefix on a general reg is missing. */
2372 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2373 && (i.types[op] & Reg16) != 0
2374 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2375 {
2376 /* Prohibit these changes in the 64bit mode, since the
2377 lowering is more complicated. */
2378 if (flag_code == CODE_64BIT)
252b5132 2379 {
0f3f3d8b 2380 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2381 i.op[op].regs->reg_name,
2382 i.suffix);
2383 return 0;
252b5132 2384 }
29b0f896
AM		 2385#if REGISTER_WARNINGS
2386 else
2387 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2388 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
2389 i.op[op].regs->reg_name,
2390 i.suffix);
2391#endif
252b5132 2392 }
29b0f896
AM		 2393 /* Warn if the r prefix on a general reg is missing. */
2394 else if ((i.types[op] & Reg64) != 0
2395 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 2396 {
0f3f3d8b 2397 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2398 i.op[op].regs->reg_name,
2399 i.suffix);
2400 return 0;
2401 }
2402 return 1;
2403}
252b5132 2404
29b0f896
AM		 2405static int
2406check_qword_reg ()
2407{
2408 int op;
252b5132 2409
29b0f896
AM		 2410 for (op = i.operands; --op >= 0; )
2411 /* Reject eight bit registers, except where the template requires
2412 them. (eg. movzb) */
2413 if ((i.types[op] & Reg8) != 0
2414 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2415 {
2416 as_bad (_("`%%%s' not allowed with `%s%c'"),
2417 i.op[op].regs->reg_name,
2418 i.tm.name,
2419 i.suffix);
2420 return 0;
2421 }
2422 /* Warn if the e prefix on a general reg is missing. */
2423 else if (((i.types[op] & Reg16) != 0
2424 || (i.types[op] & Reg32) != 0)
2425 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2426 {
2427 /* Prohibit these changes in the 64bit mode, since the
2428 lowering is more complicated. */
0f3f3d8b 2429 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2430 i.op[op].regs->reg_name,
2431 i.suffix);
2432 return 0;
252b5132 2433 }
29b0f896
AM		 2434 return 1;
2435}
252b5132 2436
29b0f896
AM		 2437static int
2438check_word_reg ()
2439{
2440 int op;
2441 for (op = i.operands; --op >= 0;)
2442 /* Reject eight bit registers, except where the template requires
2443 them. (eg. movzb) */
2444 if ((i.types[op] & Reg8) != 0
2445 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2446 {
2447 as_bad (_("`%%%s' not allowed with `%s%c'"),
2448 i.op[op].regs->reg_name,
2449 i.tm.name,
2450 i.suffix);
2451 return 0;
2452 }
2453 /* Warn if the e prefix on a general reg is present. */
2454 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2455 && (i.types[op] & Reg32) != 0
2456 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 2457 {
29b0f896
AM		 2458 /* Prohibit these changes in the 64bit mode, since the
2459 lowering is more complicated. */
2460 if (flag_code == CODE_64BIT)
252b5132 2461 {
0f3f3d8b 2462 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2463 i.op[op].regs->reg_name,
2464 i.suffix);
2465 return 0;
252b5132 2466 }
29b0f896
AM		 2467 else
2468#if REGISTER_WARNINGS
2469 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2470 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
2471 i.op[op].regs->reg_name,
2472 i.suffix);
2473#endif
2474 }
2475 return 1;
2476}
252b5132 2477
29b0f896
AM		 2478static int
2479finalize_imm ()
2480{
2481 unsigned int overlap0, overlap1, overlap2;
2482
2483 overlap0 = i.types[0] & i.tm.operand_types[0];
2484 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S))
2485 && overlap0 != Imm8 && overlap0 != Imm8S
2486 && overlap0 != Imm16 && overlap0 != Imm32S
2487 && overlap0 != Imm32 && overlap0 != Imm64)
2488 {
2489 if (i.suffix)
2490 {
2491 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
2492 ? Imm8 | Imm8S
2493 : (i.suffix == WORD_MNEM_SUFFIX
2494 ? Imm16
2495 : (i.suffix == QWORD_MNEM_SUFFIX
2496 ? Imm64 | Imm32S
2497 : Imm32)));
2498 }
2499 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2500 || overlap0 == (Imm16 | Imm32)
2501 || overlap0 == (Imm16 | Imm32S))
2502 {
2503 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2504 ? Imm16 : Imm32S);
2505 }
2506 if (overlap0 != Imm8 && overlap0 != Imm8S
2507 && overlap0 != Imm16 && overlap0 != Imm32S
2508 && overlap0 != Imm32 && overlap0 != Imm64)
2509 {
2510 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2511 return 0;
2512 }
2513 }
2514 i.types[0] = overlap0;
2515
2516 overlap1 = i.types[1] & i.tm.operand_types[1];
2517 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32))
2518 && overlap1 != Imm8 && overlap1 != Imm8S
2519 && overlap1 != Imm16 && overlap1 != Imm32S
2520 && overlap1 != Imm32 && overlap1 != Imm64)
2521 {
2522 if (i.suffix)
2523 {
2524 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
2525 ? Imm8 | Imm8S
2526 : (i.suffix == WORD_MNEM_SUFFIX
2527 ? Imm16
2528 : (i.suffix == QWORD_MNEM_SUFFIX
2529 ? Imm64 | Imm32S
2530 : Imm32)));
2531 }
2532 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2533 || overlap1 == (Imm16 | Imm32)
2534 || overlap1 == (Imm16 | Imm32S))
2535 {
2536 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2537 ? Imm16 : Imm32S);
2538 }
2539 if (overlap1 != Imm8 && overlap1 != Imm8S
2540 && overlap1 != Imm16 && overlap1 != Imm32S
2541 && overlap1 != Imm32 && overlap1 != Imm64)
2542 {
2543 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
2544 return 0;
2545 }
2546 }
2547 i.types[1] = overlap1;
2548
2549 overlap2 = i.types[2] & i.tm.operand_types[2];
2550 assert ((overlap2 & Imm) == 0);
2551 i.types[2] = overlap2;
2552
2553 return 1;
2554}
2555
2556static int
2557process_operands ()
2558{
2559 /* Default segment register this instruction will use for memory
2560 accesses. 0 means unknown. This is only for optimizing out
2561 unnecessary segment overrides. */
2562 const seg_entry *default_seg = 0;
2563
2564 /* The imul $imm, %reg instruction is converted into
2565 imul $imm, %reg, %reg, and the clr %reg instruction
2566 is converted into xor %reg, %reg. */
2567 if (i.tm.opcode_modifier & regKludge)
2568 {
2569 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
2570 /* Pretend we saw the extra register operand. */
2571 assert (i.op[first_reg_op + 1].regs == 0);
2572 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2573 i.types[first_reg_op + 1] = i.types[first_reg_op];
2574 i.reg_operands = 2;
2575 }
2576
2577 if (i.tm.opcode_modifier & ShortForm)
2578 {
2579 /* The register or float register operand is in operand 0 or 1. */
2580 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2581 /* Register goes in low 3 bits of opcode. */
2582 i.tm.base_opcode |= i.op[op].regs->reg_num;
2583 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2584 i.rex |= REX_EXTZ;
2585 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2586 {
2587 /* Warn about some common errors, but press on regardless.
2588 The first case can be generated by gcc (<= 2.8.1). */
2589 if (i.operands == 2)
2590 {
2591 /* Reversed arguments on faddp, fsubp, etc. */
2592 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
2593 i.op[1].regs->reg_name,
2594 i.op[0].regs->reg_name);
2595 }
2596 else
2597 {
2598 /* Extraneous `l' suffix on fp insn. */
2599 as_warn (_("translating to `%s %%%s'"), i.tm.name,
2600 i.op[0].regs->reg_name);
2601 }
2602 }
2603 }
2604 else if (i.tm.opcode_modifier & Modrm)
2605 {
2606 /* The opcode is completed (modulo i.tm.extension_opcode which
2607 must be put into the modrm byte).
2608 Now, we make the modrm & index base bytes based on all the
2609 info we've collected. */
2610
2611 default_seg = build_modrm_byte ();
2612 }
2613 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2614 {
2615 if (i.tm.base_opcode == POP_SEG_SHORT
2616 && i.op[0].regs->reg_num == 1)
2617 {
2618 as_bad (_("you can't `pop %%cs'"));
2619 return 0;
2620 }
2621 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2622 if ((i.op[0].regs->reg_flags & RegRex) != 0)
2623 i.rex |= REX_EXTZ;
2624 }
2625 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
2626 {
2627 default_seg = &ds;
2628 }
2629 else if ((i.tm.opcode_modifier & IsString) != 0)
2630 {
2631 /* For the string instructions that allow a segment override
2632 on one of their operands, the default segment is ds. */
2633 default_seg = &ds;
2634 }
2635
2636 /* If a segment was explicitly specified,
2637 and the specified segment is not the default,
2638 use an opcode prefix to select it.
2639 If we never figured out what the default segment is,
2640 then default_seg will be zero at this point,
2641 and the specified segment prefix will always be used. */
2642 if ((i.seg[0]) && (i.seg[0] != default_seg))
2643 {
2644 if (!add_prefix (i.seg[0]->seg_prefix))
2645 return 0;
2646 }
2647 return 1;
2648}
2649
2650static const seg_entry *
2651build_modrm_byte ()
2652{
2653 const seg_entry *default_seg = 0;
2654
2655 /* i.reg_operands MUST be the number of real register operands;
2656 implicit registers do not count. */
2657 if (i.reg_operands == 2)
2658 {
2659 unsigned int source, dest;
2660 source = ((i.types[0]
2661 & (Reg | RegMMX | RegXMM
2662 | SReg2 | SReg3
2663 | Control | Debug | Test))
2664 ? 0 : 1);
2665 dest = source + 1;
2666
2667 i.rm.mode = 3;
2668 /* One of the register operands will be encoded in the i.tm.reg
2669 field, the other in the combined i.tm.mode and i.tm.regmem
2670 fields. If no form of this instruction supports a memory
2671 destination operand, then we assume the source operand may
2672 sometimes be a memory operand and so we need to store the
2673 destination in the i.rm.reg field. */
2674 if ((i.tm.operand_types[dest] & AnyMem) == 0)
2675 {
2676 i.rm.reg = i.op[dest].regs->reg_num;
2677 i.rm.regmem = i.op[source].regs->reg_num;
2678 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2679 i.rex |= REX_EXTX;
2680 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2681 i.rex |= REX_EXTZ;
2682 }
2683 else
2684 {
2685 i.rm.reg = i.op[source].regs->reg_num;
2686 i.rm.regmem = i.op[dest].regs->reg_num;
2687 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2688 i.rex |= REX_EXTZ;
2689 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2690 i.rex |= REX_EXTX;
2691 }
2692 }
2693 else
2694 { /* If it's not 2 reg operands... */
2695 if (i.mem_operands)
2696 {
2697 unsigned int fake_zero_displacement = 0;
2698 unsigned int op = ((i.types[0] & AnyMem)
2699 ? 0
2700 : (i.types[1] & AnyMem) ? 1 : 2);
2701
2702 default_seg = &ds;
2703
2704 if (i.base_reg == 0)
2705 {
2706 i.rm.mode = 0;
2707 if (!i.disp_operands)
2708 fake_zero_displacement = 1;
2709 if (i.index_reg == 0)
2710 {
2711 /* Operand is just <disp> */
2712 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
2713 && (flag_code != CODE_64BIT))
2714 {
2715 i.rm.regmem = NO_BASE_REGISTER_16;
2716 i.types[op] &= ~Disp;
2717 i.types[op] |= Disp16;
2718 }
2719 else if (flag_code != CODE_64BIT
2720 || (i.prefix[ADDR_PREFIX] != 0))
2721 {
2722 i.rm.regmem = NO_BASE_REGISTER;
2723 i.types[op] &= ~Disp;
2724 i.types[op] |= Disp32;
2725 }
2726 else
2727 {
2728 /* 64bit mode overwrites the 32bit absolute
2729 addressing by RIP relative addressing and
2730 absolute addressing is encoded by one of the
2731 redundant SIB forms. */
2732 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2733 i.sib.base = NO_BASE_REGISTER;
2734 i.sib.index = NO_INDEX_REGISTER;
2735 i.types[op] &= ~Disp;
2736 i.types[op] |= Disp32S;
2737 }
2738 }
2739 else /* !i.base_reg && i.index_reg */
2740 {
2741 i.sib.index = i.index_reg->reg_num;
2742 i.sib.base = NO_BASE_REGISTER;
2743 i.sib.scale = i.log2_scale_factor;
2744 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2745 i.types[op] &= ~Disp;
2746 if (flag_code != CODE_64BIT)
2747 i.types[op] |= Disp32; /* Must be 32 bit */
2748 else
2749 i.types[op] |= Disp32S;
2750 if ((i.index_reg->reg_flags & RegRex) != 0)
2751 i.rex |= REX_EXTY;
2752 }
2753 }
2754 /* RIP addressing for 64bit mode. */
2755 else if (i.base_reg->reg_type == BaseIndex)
2756 {
2757 i.rm.regmem = NO_BASE_REGISTER;
2758 i.types[op] &= ~Disp;
2759 i.types[op] |= Disp32S;
2760 i.flags[op] = Operand_PCrel;
2761 }
2762 else if (i.base_reg->reg_type & Reg16)
2763 {
2764 switch (i.base_reg->reg_num)
2765 {
2766 case 3: /* (%bx) */
2767 if (i.index_reg == 0)
2768 i.rm.regmem = 7;
2769 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2770 i.rm.regmem = i.index_reg->reg_num - 6;
2771 break;
2772 case 5: /* (%bp) */
2773 default_seg = &ss;
2774 if (i.index_reg == 0)
2775 {
2776 i.rm.regmem = 6;
2777 if ((i.types[op] & Disp) == 0)
2778 {
2779 /* fake (%bp) into 0(%bp) */
2780 i.types[op] |= Disp8;
252b5132 2781 fake_zero_displacement = 1;
29b0f896
AM		 2782 }
2783 }
2784 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2785 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
2786 break;
2787 default: /* (%si) -> 4 or (%di) -> 5 */
2788 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
2789 }
2790 i.rm.mode = mode_from_disp_size (i.types[op]);
2791 }
2792 else /* i.base_reg and 32/64 bit mode */
2793 {
2794 if (flag_code == CODE_64BIT
2795 && (i.types[op] & Disp))
2796 {
2797 if (i.types[op] & Disp8)
2798 i.types[op] = Disp8 | Disp32S;
2799 else
2800 i.types[op] = Disp32S;
2801 }
2802 i.rm.regmem = i.base_reg->reg_num;
2803 if ((i.base_reg->reg_flags & RegRex) != 0)
2804 i.rex |= REX_EXTZ;
2805 i.sib.base = i.base_reg->reg_num;
2806 /* x86-64 ignores REX prefix bit here to avoid decoder
2807 complications. */
2808 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
2809 {
2810 default_seg = &ss;
2811 if (i.disp_operands == 0)
2812 {
2813 fake_zero_displacement = 1;
2814 i.types[op] |= Disp8;
2815 }
2816 }
2817 else if (i.base_reg->reg_num == ESP_REG_NUM)
2818 {
2819 default_seg = &ss;
2820 }
2821 i.sib.scale = i.log2_scale_factor;
2822 if (i.index_reg == 0)
2823 {
2824 /* <disp>(%esp) becomes two byte modrm with no index
2825 register. We've already stored the code for esp
2826 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
2827 Any base register besides %esp will not use the
2828 extra modrm byte. */
2829 i.sib.index = NO_INDEX_REGISTER;
2830#if !SCALE1_WHEN_NO_INDEX
2831 /* Another case where we force the second modrm byte. */
2832 if (i.log2_scale_factor)
2833 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 2834#endif
29b0f896
AM		 2835 }
2836 else
2837 {
2838 i.sib.index = i.index_reg->reg_num;
2839 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2840 if ((i.index_reg->reg_flags & RegRex) != 0)
2841 i.rex |= REX_EXTY;
2842 }
2843 i.rm.mode = mode_from_disp_size (i.types[op]);
2844 }
252b5132 2845
29b0f896
AM		 2846 if (fake_zero_displacement)
2847 {
2848 /* Fakes a zero displacement assuming that i.types[op]
2849 holds the correct displacement size. */
2850 expressionS *exp;
2851
2852 assert (i.op[op].disps == 0);
2853 exp = &disp_expressions[i.disp_operands++];
2854 i.op[op].disps = exp;
2855 exp->X_op = O_constant;
2856 exp->X_add_number = 0;
2857 exp->X_add_symbol = (symbolS *) 0;
2858 exp->X_op_symbol = (symbolS *) 0;
2859 }
2860 }
252b5132 2861
29b0f896
AM		 2862 /* Fill in i.rm.reg or i.rm.regmem field with register operand
2863 (if any) based on i.tm.extension_opcode. Again, we must be
2864 careful to make sure that segment/control/debug/test/MMX
2865 registers are coded into the i.rm.reg field. */
2866 if (i.reg_operands)
2867 {
2868 unsigned int op =
2869 ((i.types[0]
2870 & (Reg | RegMMX | RegXMM
2871 | SReg2 | SReg3
2872 | Control | Debug | Test))
2873 ? 0
2874 : ((i.types[1]
2875 & (Reg | RegMMX | RegXMM
2876 | SReg2 | SReg3
2877 | Control | Debug | Test))
2878 ? 1
2879 : 2));
2880 /* If there is an extension opcode to put here, the register
2881 number must be put into the regmem field. */
2882 if (i.tm.extension_opcode != None)
2883 {
2884 i.rm.regmem = i.op[op].regs->reg_num;
2885 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2886 i.rex |= REX_EXTZ;
2887 }
2888 else
2889 {
2890 i.rm.reg = i.op[op].regs->reg_num;
2891 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2892 i.rex |= REX_EXTX;
2893 }
252b5132 2894
29b0f896
AM		 2895 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
2896 must set it to 3 to indicate this is a register operand
2897 in the regmem field. */
2898 if (!i.mem_operands)
2899 i.rm.mode = 3;
2900 }
252b5132 2901
29b0f896
AM		 2902 /* Fill in i.rm.reg field with extension opcode (if any). */
2903 if (i.tm.extension_opcode != None)
2904 i.rm.reg = i.tm.extension_opcode;
2905 }
2906 return default_seg;
2907}
252b5132 2908
29b0f896
AM		 2909static void
2910output_branch ()
2911{
2912 char *p;
2913 int code16;
2914 int prefix;
2915 relax_substateT subtype;
2916 symbolS *sym;
2917 offsetT off;
2918
2919 code16 = 0;
2920 if (flag_code == CODE_16BIT)
2921 code16 = CODE16;
2922
2923 prefix = 0;
2924 if (i.prefix[DATA_PREFIX] != 0)
252b5132 2925 {
29b0f896
AM		 2926 prefix = 1;
2927 i.prefixes -= 1;
2928 code16 ^= CODE16;
252b5132 2929 }
29b0f896
AM		 2930 /* Pentium4 branch hints. */
2931 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
2932 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 2933 {
29b0f896
AM		 2934 prefix++;
2935 i.prefixes--;
2936 }
2937 if (i.prefix[REX_PREFIX] != 0)
2938 {
2939 prefix++;
2940 i.prefixes--;
2f66722d
AM		 2941 }
2942
29b0f896
AM		 2943 if (i.prefixes != 0 && !intel_syntax)
2944 as_warn (_("skipping prefixes on this instruction"));
2945
2946 /* It's always a symbol; End frag & setup for relax.
2947 Make sure there is enough room in this frag for the largest
2948 instruction we may generate in md_convert_frag. This is 2
2949 bytes for the opcode and room for the prefix and largest
2950 displacement. */
2951 frag_grow (prefix + 2 + 4);
2952 /* Prefix and 1 opcode byte go in fr_fix. */
2953 p = frag_more (prefix + 1);
2954 if (i.prefix[DATA_PREFIX] != 0)
2955 *p++ = DATA_PREFIX_OPCODE;
2956 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
2957 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
2958 *p++ = i.prefix[SEG_PREFIX];
2959 if (i.prefix[REX_PREFIX] != 0)
2960 *p++ = i.prefix[REX_PREFIX];
2961 *p = i.tm.base_opcode;
2962
2963 if ((unsigned char) *p == JUMP_PC_RELATIVE)
2964 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
2965 else if ((cpu_arch_flags & Cpu386) != 0)
2966 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
2967 else
2968 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
2969 subtype |= code16;
3e73aa7c 2970
29b0f896
AM		 2971 sym = i.op[0].disps->X_add_symbol;
2972 off = i.op[0].disps->X_add_number;
3e73aa7c 2973
29b0f896
AM		 2974 if (i.op[0].disps->X_op != O_constant
2975 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 2976 {
29b0f896
AM		 2977 /* Handle complex expressions. */
2978 sym = make_expr_symbol (i.op[0].disps);
2979 off = 0;
2980 }
3e73aa7c 2981
29b0f896
AM		 2982 /* 1 possible extra opcode + 4 byte displacement go in var part.
2983 Pass reloc in fr_var. */
2984 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
2985}
3e73aa7c 2986
29b0f896
AM		 2987static void
2988output_jump ()
2989{
2990 char *p;
2991 int size;
2992
2993 if (i.tm.opcode_modifier & JumpByte)
2994 {
2995 /* This is a loop or jecxz type instruction. */
2996 size = 1;
2997 if (i.prefix[ADDR_PREFIX] != 0)
2998 {
2999 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3000 i.prefixes -= 1;
3001 }
3002 /* Pentium4 branch hints. */
3003 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3004 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3005 {
3006 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3007 i.prefixes--;
3e73aa7c
JH		 3008 }
3009 }
29b0f896
AM		 3010 else
3011 {
3012 int code16;
3e73aa7c 3013
29b0f896
AM		 3014 code16 = 0;
3015 if (flag_code == CODE_16BIT)
3016 code16 = CODE16;
3e73aa7c 3017
29b0f896
AM		 3018 if (i.prefix[DATA_PREFIX] != 0)
3019 {
3020 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3021 i.prefixes -= 1;
3022 code16 ^= CODE16;
3023 }
252b5132 3024
29b0f896
AM		 3025 size = 4;
3026 if (code16)
3027 size = 2;
3028 }
9fcc94b6 3029
29b0f896
AM		 3030 if (i.prefix[REX_PREFIX] != 0)
3031 {
3032 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3033 i.prefixes -= 1;
3034 }
252b5132 3035
29b0f896
AM		 3036 if (i.prefixes != 0 && !intel_syntax)
3037 as_warn (_("skipping prefixes on this instruction"));
e0890092 3038
29b0f896
AM		 3039 p = frag_more (1 + size);
3040 *p++ = i.tm.base_opcode;
e0890092 3041
062cd5e7
AS		 3042 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3043 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
29b0f896 3044}
e0890092 3045
29b0f896
AM		 3046static void
3047output_interseg_jump ()
3048{
3049 char *p;
3050 int size;
3051 int prefix;
3052 int code16;
252b5132 3053
29b0f896
AM		 3054 code16 = 0;
3055 if (flag_code == CODE_16BIT)
3056 code16 = CODE16;
a217f122 3057
29b0f896
AM		 3058 prefix = 0;
3059 if (i.prefix[DATA_PREFIX] != 0)
3060 {
3061 prefix = 1;
3062 i.prefixes -= 1;
3063 code16 ^= CODE16;
3064 }
3065 if (i.prefix[REX_PREFIX] != 0)
3066 {
3067 prefix++;
3068 i.prefixes -= 1;
3069 }
252b5132 3070
29b0f896
AM		 3071 size = 4;
3072 if (code16)
3073 size = 2;
252b5132 3074
29b0f896
AM		 3075 if (i.prefixes != 0 && !intel_syntax)
3076 as_warn (_("skipping prefixes on this instruction"));
252b5132 3077
29b0f896
AM		 3078 /* 1 opcode; 2 segment; offset */
3079 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3080
29b0f896
AM		 3081 if (i.prefix[DATA_PREFIX] != 0)
3082 *p++ = DATA_PREFIX_OPCODE;
252b5132 3083
29b0f896
AM		 3084 if (i.prefix[REX_PREFIX] != 0)
3085 *p++ = i.prefix[REX_PREFIX];
252b5132 3086
29b0f896
AM		 3087 *p++ = i.tm.base_opcode;
3088 if (i.op[1].imms->X_op == O_constant)
3089 {
3090 offsetT n = i.op[1].imms->X_add_number;
252b5132 3091
29b0f896
AM		 3092 if (size == 2
3093 && !fits_in_unsigned_word (n)
3094 && !fits_in_signed_word (n))
3095 {
3096 as_bad (_("16-bit jump out of range"));
3097 return;
3098 }
3099 md_number_to_chars (p, n, size);
3100 }
3101 else
3102 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3103 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3104 if (i.op[0].imms->X_op != O_constant)
3105 as_bad (_("can't handle non absolute segment in `%s'"),
3106 i.tm.name);
3107 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3108}
a217f122 3109
2bbd9c25 3110
29b0f896
AM		 3111static void
3112output_insn ()
3113{
2bbd9c25
JJ		 3114 fragS *insn_start_frag;
3115 offsetT insn_start_off;
3116
29b0f896
AM		 3117 /* Tie dwarf2 debug info to the address at the start of the insn.
3118 We can't do this after the insn has been output as the current
3119 frag may have been closed off. eg. by frag_var. */
3120 dwarf2_emit_insn (0);
3121
2bbd9c25
JJ		 3122 insn_start_frag = frag_now;
3123 insn_start_off = frag_now_fix ();
3124
29b0f896
AM		 3125 /* Output jumps. */
3126 if (i.tm.opcode_modifier & Jump)
3127 output_branch ();
3128 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3129 output_jump ();
3130 else if (i.tm.opcode_modifier & JumpInterSegment)
3131 output_interseg_jump ();
3132 else
3133 {
3134 /* Output normal instructions here. */
3135 char *p;
3136 unsigned char *q;
252b5132 3137
29b0f896
AM		 3138 /* All opcodes on i386 have either 1 or 2 bytes. We may use third
3139 byte for the SSE instructions to specify a prefix they require. */
3140 if (i.tm.base_opcode & 0xff0000)
3141 add_prefix ((i.tm.base_opcode >> 16) & 0xff);
252b5132 3142
29b0f896
AM		 3143 /* The prefix bytes. */
3144 for (q = i.prefix;
3145 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3146 q++)
3147 {
3148 if (*q)
3149 {
3150 p = frag_more (1);
3151 md_number_to_chars (p, (valueT) *q, 1);
3152 }
3153 }
252b5132 3154
29b0f896
AM		 3155 /* Now the opcode; be careful about word order here! */
3156 if (fits_in_unsigned_byte (i.tm.base_opcode))
3157 {
3158 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3159 }
3160 else
3161 {
3162 p = frag_more (2);
3163 /* Put out high byte first: can't use md_number_to_chars! */
3164 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3165 *p = i.tm.base_opcode & 0xff;
3166 }
3e73aa7c 3167
29b0f896
AM		 3168 /* Now the modrm byte and sib byte (if present). */
3169 if (i.tm.opcode_modifier & Modrm)
3170 {
3171 p = frag_more (1);
3172 md_number_to_chars (p,
3173 (valueT) (i.rm.regmem << 0
3174 | i.rm.reg << 3
3175 | i.rm.mode << 6),
3176 1);
3177 /* If i.rm.regmem == ESP (4)
3178 && i.rm.mode != (Register mode)
3179 && not 16 bit
3180 ==> need second modrm byte. */
3181 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3182 && i.rm.mode != 3
3183 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3184 {
3185 p = frag_more (1);
3186 md_number_to_chars (p,
3187 (valueT) (i.sib.base << 0
3188 | i.sib.index << 3
3189 | i.sib.scale << 6),
3190 1);
3191 }
3192 }
3e73aa7c 3193
29b0f896 3194 if (i.disp_operands)
2bbd9c25 3195 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 3196
29b0f896 3197 if (i.imm_operands)
2bbd9c25 3198 output_imm (insn_start_frag, insn_start_off);
29b0f896 3199 }
252b5132 3200
29b0f896
AM		 3201#ifdef DEBUG386
3202 if (flag_debug)
3203 {
3204 pi (line, &i);
3205 }
3206#endif /* DEBUG386 */
3207}
252b5132 3208
29b0f896 3209static void
2bbd9c25
JJ		 3210output_disp (insn_start_frag, insn_start_off)
3211 fragS *insn_start_frag;
3212 offsetT insn_start_off;
29b0f896
AM		 3213{
3214 char *p;
3215 unsigned int n;
252b5132 3216
29b0f896
AM		 3217 for (n = 0; n < i.operands; n++)
3218 {
3219 if (i.types[n] & Disp)
3220 {
3221 if (i.op[n].disps->X_op == O_constant)
3222 {
3223 int size;
3224 offsetT val;
252b5132 3225
29b0f896
AM		 3226 size = 4;
3227 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3228 {
3229 size = 2;
3230 if (i.types[n] & Disp8)
3231 size = 1;
3232 if (i.types[n] & Disp64)
3233 size = 8;
3234 }
3235 val = offset_in_range (i.op[n].disps->X_add_number,
3236 size);
3237 p = frag_more (size);
3238 md_number_to_chars (p, val, size);
3239 }
3240 else
3241 {
2bbd9c25 3242 RELOC_ENUM reloc_type;
29b0f896
AM		 3243 int size = 4;
3244 int sign = 0;
3245 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
3246
3247 /* The PC relative address is computed relative
3248 to the instruction boundary, so in case immediate
3249 fields follows, we need to adjust the value. */
3250 if (pcrel && i.imm_operands)
3251 {
3252 int imm_size = 4;
3253 unsigned int n1;
252b5132 3254
29b0f896
AM		 3255 for (n1 = 0; n1 < i.operands; n1++)
3256 if (i.types[n1] & Imm)
252b5132 3257 {
29b0f896 3258 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 3259 {
29b0f896
AM		 3260 imm_size = 2;
3261 if (i.types[n1] & (Imm8 | Imm8S))
3262 imm_size = 1;
3263 if (i.types[n1] & Imm64)
3264 imm_size = 8;
252b5132 3265 }
29b0f896 3266 break;
252b5132 3267 }
29b0f896
AM		 3268 /* We should find the immediate. */
3269 if (n1 == i.operands)
3270 abort ();
3271 i.op[n].disps->X_add_number -= imm_size;
3272 }
520dc8e8 3273
29b0f896
AM		 3274 if (i.types[n] & Disp32S)
3275 sign = 1;
3e73aa7c 3276
29b0f896
AM		 3277 if (i.types[n] & (Disp16 | Disp64))
3278 {
3279 size = 2;
3280 if (i.types[n] & Disp64)
3281 size = 8;
3282 }
520dc8e8 3283
29b0f896 3284 p = frag_more (size);
2bbd9c25
JJ		 3285 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
3286#ifdef BFD_ASSEMBLER
3287 if (reloc_type == BFD_RELOC_32
3288 && GOT_symbol
3289 && GOT_symbol == i.op[n].disps->X_add_symbol
3290 && (i.op[n].disps->X_op == O_symbol
3291 || (i.op[n].disps->X_op == O_add
3292 && ((symbol_get_value_expression
3293 (i.op[n].disps->X_op_symbol)->X_op)
3294 == O_subtract))))
3295 {
3296 offsetT add;
3297
3298 if (insn_start_frag == frag_now)
3299 add = (p - frag_now->fr_literal) - insn_start_off;
3300 else
3301 {
3302 fragS *fr;
3303
3304 add = insn_start_frag->fr_fix - insn_start_off;
3305 for (fr = insn_start_frag->fr_next;
3306 fr && fr != frag_now; fr = fr->fr_next)
3307 add += fr->fr_fix;
3308 add += p - frag_now->fr_literal;
3309 }
3310
3311 /* We don't support dynamic linking on x86-64 yet. */
3312 if (flag_code == CODE_64BIT)
3313 abort ();
3314 reloc_type = BFD_RELOC_386_GOTPC;
3315 i.op[n].disps->X_add_number += add;
3316 }
3317#endif
062cd5e7 3318 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 3319 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 3320 }
3321 }
3322 }
3323}
252b5132 3324
29b0f896 3325static void
2bbd9c25
JJ		 3326output_imm (insn_start_frag, insn_start_off)
3327 fragS *insn_start_frag;
3328 offsetT insn_start_off;
29b0f896
AM		 3329{
3330 char *p;
3331 unsigned int n;
252b5132 3332
29b0f896
AM		 3333 for (n = 0; n < i.operands; n++)
3334 {
3335 if (i.types[n] & Imm)
3336 {
3337 if (i.op[n].imms->X_op == O_constant)
3338 {
3339 int size;
3340 offsetT val;
b4cac588 3341
29b0f896
AM		 3342 size = 4;
3343 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3344 {
3345 size = 2;
3346 if (i.types[n] & (Imm8 | Imm8S))
3347 size = 1;
3348 else if (i.types[n] & Imm64)
3349 size = 8;
3350 }
3351 val = offset_in_range (i.op[n].imms->X_add_number,
3352 size);
3353 p = frag_more (size);
3354 md_number_to_chars (p, val, size);
3355 }
3356 else
3357 {
3358 /* Not absolute_section.
3359 Need a 32-bit fixup (don't support 8bit
3360 non-absolute imms). Try to support other
3361 sizes ... */
3362 RELOC_ENUM reloc_type;
3363 int size = 4;
3364 int sign = 0;
3365
3366 if ((i.types[n] & (Imm32S))
3367 && i.suffix == QWORD_MNEM_SUFFIX)
3368 sign = 1;
3369 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3370 {
3371 size = 2;
3372 if (i.types[n] & (Imm8 | Imm8S))
3373 size = 1;
3374 if (i.types[n] & Imm64)
3375 size = 8;
3376 }
520dc8e8 3377
29b0f896
AM		 3378 p = frag_more (size);
3379 reloc_type = reloc (size, 0, sign, i.reloc[n]);
252b5132 3380#ifdef BFD_ASSEMBLER
2bbd9c25
JJ		 3381 /* This is tough to explain. We end up with this one if we
3382 * have operands that look like
3383 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3384 * obtain the absolute address of the GOT, and it is strongly
3385 * preferable from a performance point of view to avoid using
3386 * a runtime relocation for this. The actual sequence of
3387 * instructions often look something like:
3388 *
3389 * call .L66
3390 * .L66:
3391 * popl %ebx
3392 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3393 *
3394 * The call and pop essentially return the absolute address
3395 * of the label .L66 and store it in %ebx. The linker itself
3396 * will ultimately change the first operand of the addl so
3397 * that %ebx points to the GOT, but to keep things simple, the
3398 * .o file must have this operand set so that it generates not
3399 * the absolute address of .L66, but the absolute address of
3400 * itself. This allows the linker itself simply treat a GOTPC
3401 * relocation as asking for a pcrel offset to the GOT to be
3402 * added in, and the addend of the relocation is stored in the
3403 * operand field for the instruction itself.
3404 *
3405 * Our job here is to fix the operand so that it would add
3406 * the correct offset so that %ebx would point to itself. The
3407 * thing that is tricky is that .-.L66 will point to the
3408 * beginning of the instruction, so we need to further modify
3409 * the operand so that it will point to itself. There are
3410 * other cases where you have something like:
3411 *
3412 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3413 *
3414 * and here no correction would be required. Internally in
3415 * the assembler we treat operands of this form as not being
3416 * pcrel since the '.' is explicitly mentioned, and I wonder
3417 * whether it would simplify matters to do it this way. Who
3418 * knows. In earlier versions of the PIC patches, the
3419 * pcrel_adjust field was used to store the correction, but
3420 * since the expression is not pcrel, I felt it would be
3421 * confusing to do it this way. */
3422
29b0f896
AM		 3423 if (reloc_type == BFD_RELOC_32
3424 && GOT_symbol
3425 && GOT_symbol == i.op[n].imms->X_add_symbol
3426 && (i.op[n].imms->X_op == O_symbol
3427 || (i.op[n].imms->X_op == O_add
3428 && ((symbol_get_value_expression
3429 (i.op[n].imms->X_op_symbol)->X_op)
3430 == O_subtract))))
3431 {
2bbd9c25
JJ		 3432 offsetT add;
3433
3434 if (insn_start_frag == frag_now)
3435 add = (p - frag_now->fr_literal) - insn_start_off;
3436 else
3437 {
3438 fragS *fr;
3439
3440 add = insn_start_frag->fr_fix - insn_start_off;
3441 for (fr = insn_start_frag->fr_next;
3442 fr && fr != frag_now; fr = fr->fr_next)
3443 add += fr->fr_fix;
3444 add += p - frag_now->fr_literal;
3445 }
3446
29b0f896
AM		 3447 /* We don't support dynamic linking on x86-64 yet. */
3448 if (flag_code == CODE_64BIT)
3449 abort ();
3450 reloc_type = BFD_RELOC_386_GOTPC;
2bbd9c25 3451 i.op[n].imms->X_add_number += add;
29b0f896 3452 }
252b5132 3453#endif
29b0f896
AM		 3454 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3455 i.op[n].imms, 0, reloc_type);
3456 }
3457 }
3458 }
252b5132
RH		 3459}
3460\f
f3c180ae
AM		 3461#ifndef LEX_AT
3462static char *lex_got PARAMS ((RELOC_ENUM *, int *));
3463
3464/* Parse operands of the form
3465 <symbol>@GOTOFF+<nnn>
3466 and similar .plt or .got references.
3467
3468 If we find one, set up the correct relocation in RELOC and copy the
3469 input string, minus the `@GOTOFF' into a malloc'd buffer for
3470 parsing by the calling routine. Return this buffer, and if ADJUST
3471 is non-null set it to the length of the string we removed from the
3472 input line. Otherwise return NULL. */
3473static char *
3474lex_got (reloc, adjust)
3475 RELOC_ENUM *reloc;
3476 int *adjust;
3477{
3478 static const char * const mode_name[NUM_FLAG_CODE] = { "32", "16", "64" };
3479 static const struct {
3480 const char *str;
3481 const RELOC_ENUM rel[NUM_FLAG_CODE];
3482 } gotrel[] = {
13ae64f3
JJ		 3483 { "PLT", { BFD_RELOC_386_PLT32, 0, BFD_RELOC_X86_64_PLT32 } },
3484 { "GOTOFF", { BFD_RELOC_386_GOTOFF, 0, 0 } },
3485 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL } },
3486 { "TLSGD", { BFD_RELOC_386_TLS_GD, 0, 0 } },
3487 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0, 0 } },
3488 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, 0, 0 } },
3489 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, 0, 0 } },
3490 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0, 0 } },
3491 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, 0, 0 } },
37e55690
JJ		 3492 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0, 0 } },
3493 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0, 0 } },
13ae64f3 3494 { "GOT", { BFD_RELOC_386_GOT32, 0, BFD_RELOC_X86_64_GOT32 } }
f3c180ae
AM		 3495 };
3496 char *cp;
3497 unsigned int j;
3498
3499 for (cp = input_line_pointer; *cp != '@'; cp++)
3500 if (is_end_of_line[(unsigned char) *cp])
3501 return NULL;
3502
3503 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
3504 {
3505 int len;
3506
3507 len = strlen (gotrel[j].str);
28f81592 3508 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae
AM		 3509 {
3510 if (gotrel[j].rel[(unsigned int) flag_code] != 0)
3511 {
28f81592
AM		 3512 int first, second;
3513 char *tmpbuf, *past_reloc;
f3c180ae
AM		 3514
3515 *reloc = gotrel[j].rel[(unsigned int) flag_code];
28f81592
AM		 3516 if (adjust)
3517 *adjust = len;
f3c180ae
AM		 3518
3519 if (GOT_symbol == NULL)
3520 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3521
3522 /* Replace the relocation token with ' ', so that
3523 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 3524
3525 /* The length of the first part of our input line. */
f3c180ae 3526 first = cp - input_line_pointer;
28f81592
AM		 3527
3528 /* The second part goes from after the reloc token until
3529 (and including) an end_of_line char. Don't use strlen
3530 here as the end_of_line char may not be a NUL. */
3531 past_reloc = cp + 1 + len;
3532 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
3533 ;
3534 second = cp - past_reloc;
3535
3536 /* Allocate and copy string. The trailing NUL shouldn't
3537 be necessary, but be safe. */
3538 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 3539 memcpy (tmpbuf, input_line_pointer, first);
3540 tmpbuf[first] = ' ';
28f81592
AM		 3541 memcpy (tmpbuf + first + 1, past_reloc, second);
3542 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 3543 return tmpbuf;
3544 }
3545
3546 as_bad (_("@%s reloc is not supported in %s bit mode"),
3547 gotrel[j].str, mode_name[(unsigned int) flag_code]);
3548 return NULL;
3549 }
3550 }
3551
3552 /* Might be a symbol version string. Don't as_bad here. */
3553 return NULL;
3554}
3555
3556/* x86_cons_fix_new is called via the expression parsing code when a
3557 reloc is needed. We use this hook to get the correct .got reloc. */
3558static RELOC_ENUM got_reloc = NO_RELOC;
3559
3560void
3561x86_cons_fix_new (frag, off, len, exp)
3562 fragS *frag;
3563 unsigned int off;
3564 unsigned int len;
3565 expressionS *exp;
3566{
3567 RELOC_ENUM r = reloc (len, 0, 0, got_reloc);
3568 got_reloc = NO_RELOC;
3569 fix_new_exp (frag, off, len, exp, 0, r);
3570}
3571
3572void
3573x86_cons (exp, size)
3574 expressionS *exp;
3575 int size;
3576{
3577 if (size == 4)
3578 {
3579 /* Handle @GOTOFF and the like in an expression. */
3580 char *save;
3581 char *gotfree_input_line;
3582 int adjust;
3583
3584 save = input_line_pointer;
3585 gotfree_input_line = lex_got (&got_reloc, &adjust);
3586 if (gotfree_input_line)
3587 input_line_pointer = gotfree_input_line;
3588
3589 expression (exp);
3590
3591 if (gotfree_input_line)
3592 {
3593 /* expression () has merrily parsed up to the end of line,
3594 or a comma - in the wrong buffer. Transfer how far
3595 input_line_pointer has moved to the right buffer. */
3596 input_line_pointer = (save
3597 + (input_line_pointer - gotfree_input_line)
3598 + adjust);
3599 free (gotfree_input_line);
3600 }
3601 }
3602 else
3603 expression (exp);
3604}
3605#endif
3606
252b5132
RH		 3607static int i386_immediate PARAMS ((char *));
3608
3609static int
3610i386_immediate (imm_start)
3611 char *imm_start;
3612{
3613 char *save_input_line_pointer;
f3c180ae
AM		 3614#ifndef LEX_AT
3615 char *gotfree_input_line;
3616#endif
252b5132 3617 segT exp_seg = 0;
47926f60 3618 expressionS *exp;
252b5132
RH		 3619
3620 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
3621 {
d0b47220 3622 as_bad (_("only 1 or 2 immediate operands are allowed"));
252b5132
RH		 3623 return 0;
3624 }
3625
3626 exp = &im_expressions[i.imm_operands++];
520dc8e8 3627 i.op[this_operand].imms = exp;
252b5132
RH		 3628
3629 if (is_space_char (*imm_start))
3630 ++imm_start;
3631
3632 save_input_line_pointer = input_line_pointer;
3633 input_line_pointer = imm_start;
3634
3635#ifndef LEX_AT
f3c180ae
AM		 3636 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3637 if (gotfree_input_line)
3638 input_line_pointer = gotfree_input_line;
252b5132
RH		 3639#endif
3640
3641 exp_seg = expression (exp);
3642
83183c0c 3643 SKIP_WHITESPACE ();
252b5132 3644 if (*input_line_pointer)
f3c180ae 3645 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 3646
3647 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 3648#ifndef LEX_AT
3649 if (gotfree_input_line)
3650 free (gotfree_input_line);
3651#endif
252b5132 3652
2daf4fd8 3653 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 3654 {
47926f60 3655 /* Missing or bad expr becomes absolute 0. */
d0b47220 3656 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 3657 imm_start);
252b5132
RH		 3658 exp->X_op = O_constant;
3659 exp->X_add_number = 0;
3660 exp->X_add_symbol = (symbolS *) 0;
3661 exp->X_op_symbol = (symbolS *) 0;
252b5132 3662 }
3e73aa7c 3663 else if (exp->X_op == O_constant)
252b5132 3664 {
47926f60 3665 /* Size it properly later. */
3e73aa7c
JH		 3666 i.types[this_operand] |= Imm64;
3667 /* If BFD64, sign extend val. */
3668 if (!use_rela_relocations)
3669 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
3670 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 3671 }
4c63da97 3672#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
47926f60 3673 else if (1
4c63da97 3674#ifdef BFD_ASSEMBLER
47926f60 3675 && OUTPUT_FLAVOR == bfd_target_aout_flavour
4c63da97 3676#endif
31312f95 3677 && exp_seg != absolute_section
47926f60 3678 && exp_seg != text_section
24eab124
AM		 3679 && exp_seg != data_section
3680 && exp_seg != bss_section
3681 && exp_seg != undefined_section
252b5132 3682#ifdef BFD_ASSEMBLER
24eab124 3683 && !bfd_is_com_section (exp_seg)
252b5132 3684#endif
24eab124 3685 )
252b5132 3686 {
4c63da97 3687#ifdef BFD_ASSEMBLER
d0b47220 3688 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4c63da97 3689#else
d0b47220 3690 as_bad (_("unimplemented segment type %d in operand"), exp_seg);
4c63da97 3691#endif
252b5132
RH		 3692 return 0;
3693 }
3694#endif
3695 else
3696 {
3697 /* This is an address. The size of the address will be
24eab124 3698 determined later, depending on destination register,
3e73aa7c
JH		 3699 suffix, or the default for the section. */
3700 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
252b5132
RH		 3701 }
3702
3703 return 1;
3704}
3705
551c1ca1 3706static char *i386_scale PARAMS ((char *));
252b5132 3707
551c1ca1 3708static char *
252b5132
RH		 3709i386_scale (scale)
3710 char *scale;
3711{
551c1ca1
AM		 3712 offsetT val;
3713 char *save = input_line_pointer;
252b5132 3714
551c1ca1
AM		 3715 input_line_pointer = scale;
3716 val = get_absolute_expression ();
3717
3718 switch (val)
252b5132 3719 {
551c1ca1
AM		 3720 case 0:
3721 case 1:
252b5132
RH		 3722 i.log2_scale_factor = 0;
3723 break;
551c1ca1 3724 case 2:
252b5132
RH		 3725 i.log2_scale_factor = 1;
3726 break;
551c1ca1 3727 case 4:
252b5132
RH		 3728 i.log2_scale_factor = 2;
3729 break;
551c1ca1 3730 case 8:
252b5132
RH		 3731 i.log2_scale_factor = 3;
3732 break;
3733 default:
252b5132 3734 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
24eab124 3735 scale);
551c1ca1
AM		 3736 input_line_pointer = save;
3737 return NULL;
252b5132 3738 }
29b0f896 3739 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 3740 {
3741 as_warn (_("scale factor of %d without an index register"),
24eab124 3742 1 << i.log2_scale_factor);
252b5132
RH		 3743#if SCALE1_WHEN_NO_INDEX
3744 i.log2_scale_factor = 0;
3745#endif
3746 }
551c1ca1
AM		 3747 scale = input_line_pointer;
3748 input_line_pointer = save;
3749 return scale;
252b5132
RH		 3750}
3751
3752static int i386_displacement PARAMS ((char *, char *));
3753
3754static int
3755i386_displacement (disp_start, disp_end)
3756 char *disp_start;
3757 char *disp_end;
3758{
29b0f896 3759 expressionS *exp;
252b5132
RH		 3760 segT exp_seg = 0;
3761 char *save_input_line_pointer;
f3c180ae
AM		 3762#ifndef LEX_AT
3763 char *gotfree_input_line;
3764#endif
252b5132
RH		 3765 int bigdisp = Disp32;
3766
3e73aa7c 3767 if (flag_code == CODE_64BIT)
7ecd2f8b 3768 {
29b0f896
AM		 3769 if (i.prefix[ADDR_PREFIX] == 0)
3770 bigdisp = Disp64;
7ecd2f8b
JH		 3771 }
3772 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3773 bigdisp = Disp16;
252b5132
RH		 3774 i.types[this_operand] |= bigdisp;
3775
3776 exp = &disp_expressions[i.disp_operands];
520dc8e8 3777 i.op[this_operand].disps = exp;
252b5132
RH		 3778 i.disp_operands++;
3779 save_input_line_pointer = input_line_pointer;
3780 input_line_pointer = disp_start;
3781 END_STRING_AND_SAVE (disp_end);
3782
3783#ifndef GCC_ASM_O_HACK
3784#define GCC_ASM_O_HACK 0
3785#endif
3786#if GCC_ASM_O_HACK
3787 END_STRING_AND_SAVE (disp_end + 1);
3788 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 3789 && displacement_string_end[-1] == '+')
252b5132
RH		 3790 {
3791 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 3792 constraint within gcc asm statements.
3793 For instance:
3794
3795 #define _set_tssldt_desc(n,addr,limit,type) \
3796 __asm__ __volatile__ ( \
3797 "movw %w2,%0\n\t" \
3798 "movw %w1,2+%0\n\t" \
3799 "rorl $16,%1\n\t" \
3800 "movb %b1,4+%0\n\t" \
3801 "movb %4,5+%0\n\t" \
3802 "movb $0,6+%0\n\t" \
3803 "movb %h1,7+%0\n\t" \
3804 "rorl $16,%1" \
3805 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3806
3807 This works great except that the output assembler ends
3808 up looking a bit weird if it turns out that there is
3809 no offset. You end up producing code that looks like:
3810
3811 #APP
3812 movw $235,(%eax)
3813 movw %dx,2+(%eax)
3814 rorl $16,%edx
3815 movb %dl,4+(%eax)
3816 movb $137,5+(%eax)
3817 movb $0,6+(%eax)
3818 movb %dh,7+(%eax)
3819 rorl $16,%edx
3820 #NO_APP
3821
47926f60 3822 So here we provide the missing zero. */
24eab124
AM		 3823
3824 *displacement_string_end = '0';
252b5132
RH		 3825 }
3826#endif
3827#ifndef LEX_AT
f3c180ae
AM		 3828 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3829 if (gotfree_input_line)
3830 input_line_pointer = gotfree_input_line;
252b5132
RH		 3831#endif
3832
24eab124 3833 exp_seg = expression (exp);
252b5132 3834
636c26b0
AM		 3835 SKIP_WHITESPACE ();
3836 if (*input_line_pointer)
3837 as_bad (_("junk `%s' after expression"), input_line_pointer);
3838#if GCC_ASM_O_HACK
3839 RESTORE_END_STRING (disp_end + 1);
3840#endif
3841 RESTORE_END_STRING (disp_end);
3842 input_line_pointer = save_input_line_pointer;
3843#ifndef LEX_AT
3844 if (gotfree_input_line)
3845 free (gotfree_input_line);
3846#endif
3847
252b5132 3848#ifdef BFD_ASSEMBLER
24eab124
AM		 3849 /* We do this to make sure that the section symbol is in
3850 the symbol table. We will ultimately change the relocation
47926f60 3851 to be relative to the beginning of the section. */
1ae12ab7
AM		 3852 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
3853 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
24eab124 3854 {
636c26b0
AM		 3855 if (exp->X_op != O_symbol)
3856 {
3857 as_bad (_("bad expression used with @%s"),
3858 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
3859 ? "GOTPCREL"
3860 : "GOTOFF"));
3861 return 0;
3862 }
3863
e5cb08ac 3864 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 3865 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
3866 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 3867 exp->X_op = O_subtract;
3868 exp->X_op_symbol = GOT_symbol;
1ae12ab7 3869 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 3870 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
23df1078 3871 else
29b0f896 3872 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 3873 }
252b5132
RH		 3874#endif
3875
2daf4fd8
AM		 3876 if (exp->X_op == O_absent || exp->X_op == O_big)
3877 {
47926f60 3878 /* Missing or bad expr becomes absolute 0. */
d0b47220 3879 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 3880 disp_start);
3881 exp->X_op = O_constant;
3882 exp->X_add_number = 0;
3883 exp->X_add_symbol = (symbolS *) 0;
3884 exp->X_op_symbol = (symbolS *) 0;
3885 }
3886
4c63da97 3887#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 3888 if (exp->X_op != O_constant
4c63da97 3889#ifdef BFD_ASSEMBLER
45288df1 3890 && OUTPUT_FLAVOR == bfd_target_aout_flavour
4c63da97 3891#endif
31312f95 3892 && exp_seg != absolute_section
45288df1
AM		 3893 && exp_seg != text_section
3894 && exp_seg != data_section
3895 && exp_seg != bss_section
31312f95
AM		 3896 && exp_seg != undefined_section
3897#ifdef BFD_ASSEMBLER
3898 && !bfd_is_com_section (exp_seg)
3899#endif
3900 )
24eab124 3901 {
4c63da97 3902#ifdef BFD_ASSEMBLER
d0b47220 3903 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4c63da97 3904#else
d0b47220 3905 as_bad (_("unimplemented segment type %d in operand"), exp_seg);
4c63da97 3906#endif
24eab124
AM		 3907 return 0;
3908 }
252b5132 3909#endif
3e73aa7c
JH		 3910 else if (flag_code == CODE_64BIT)
3911 i.types[this_operand] |= Disp32S | Disp32;
252b5132
RH		 3912 return 1;
3913}
3914
e5cb08ac 3915static int i386_index_check PARAMS ((const char *));
252b5132 3916
eecb386c 3917/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 3918 Return 1 on success, 0 on a failure. */
3919
252b5132 3920static int
eecb386c
AM		 3921i386_index_check (operand_string)
3922 const char *operand_string;
252b5132 3923{
3e73aa7c 3924 int ok;
24eab124 3925#if INFER_ADDR_PREFIX
eecb386c
AM		 3926 int fudged = 0;
3927
24eab124
AM		 3928 tryprefix:
3929#endif
3e73aa7c
JH		 3930 ok = 1;
3931 if (flag_code == CODE_64BIT)
3932 {
7ecd2f8b
JH		 3933 if (i.prefix[ADDR_PREFIX] == 0)
3934 {
3935 /* 64bit checks. */
3936 if ((i.base_reg
3937 && ((i.base_reg->reg_type & Reg64) == 0)
3938 && (i.base_reg->reg_type != BaseIndex
3939 || i.index_reg))
3940 || (i.index_reg
29b0f896
AM		 3941 && ((i.index_reg->reg_type & (Reg64 | BaseIndex))
3942 != (Reg64 | BaseIndex))))
7ecd2f8b
JH		 3943 ok = 0;
3944 }
3945 else
3946 {
3947 /* 32bit checks. */
3948 if ((i.base_reg
3949 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
3950 || (i.index_reg
29b0f896
AM		 3951 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
3952 != (Reg32 | BaseIndex))))
7ecd2f8b
JH		 3953 ok = 0;
3954 }
3e73aa7c
JH		 3955 }
3956 else
3957 {
3958 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3959 {
3960 /* 16bit checks. */
3961 if ((i.base_reg
29b0f896
AM		 3962 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
3963 != (Reg16 | BaseIndex)))
3e73aa7c 3964 || (i.index_reg
29b0f896
AM		 3965 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
3966 != (Reg16 | BaseIndex))
3967 || !(i.base_reg
3968 && i.base_reg->reg_num < 6
3969 && i.index_reg->reg_num >= 6
3970 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 3971 ok = 0;
3972 }
3973 else
e5cb08ac 3974 {
3e73aa7c
JH		 3975 /* 32bit checks. */
3976 if ((i.base_reg
3977 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
3978 || (i.index_reg
29b0f896
AM		 3979 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
3980 != (Reg32 | BaseIndex))))
e5cb08ac 3981 ok = 0;
3e73aa7c
JH		 3982 }
3983 }
3984 if (!ok)
24eab124
AM		 3985 {
3986#if INFER_ADDR_PREFIX
3e73aa7c
JH		 3987 if (flag_code != CODE_64BIT
3988 && i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0')
24eab124
AM		 3989 {
3990 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
3991 i.prefixes += 1;
b23bac36
AM		 3992 /* Change the size of any displacement too. At most one of
3993 Disp16 or Disp32 is set.
3994 FIXME. There doesn't seem to be any real need for separate
3995 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 3996 Removing them would probably clean up the code quite a lot. */
29b0f896
AM		 3997 if (i.types[this_operand] & (Disp16 | Disp32))
3998 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 3999 fudged = 1;
24eab124
AM		 4000 goto tryprefix;
4001 }
eecb386c
AM		 4002 if (fudged)
4003 as_bad (_("`%s' is not a valid base/index expression"),
4004 operand_string);
4005 else
c388dee8 4006#endif
eecb386c
AM		 4007 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4008 operand_string,
3e73aa7c 4009 flag_code_names[flag_code]);
eecb386c 4010 return 0;
24eab124
AM		 4011 }
4012 return 1;
4013}
252b5132 4014
252b5132 4015/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 4016 on error. */
252b5132 4017
252b5132
RH		 4018static int
4019i386_operand (operand_string)
4020 char *operand_string;
4021{
af6bdddf
AM		 4022 const reg_entry *r;
4023 char *end_op;
24eab124 4024 char *op_string = operand_string;
252b5132 4025
24eab124 4026 if (is_space_char (*op_string))
252b5132
RH		 4027 ++op_string;
4028
24eab124 4029 /* We check for an absolute prefix (differentiating,
47926f60 4030 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 4031 if (*op_string == ABSOLUTE_PREFIX)
4032 {
4033 ++op_string;
4034 if (is_space_char (*op_string))
4035 ++op_string;
4036 i.types[this_operand] |= JumpAbsolute;
4037 }
252b5132 4038
47926f60 4039 /* Check if operand is a register. */
af6bdddf
AM		 4040 if ((*op_string == REGISTER_PREFIX || allow_naked_reg)
4041 && (r = parse_register (op_string, &end_op)) != NULL)
24eab124 4042 {
24eab124
AM		 4043 /* Check for a segment override by searching for ':' after a
4044 segment register. */
4045 op_string = end_op;
4046 if (is_space_char (*op_string))
4047 ++op_string;
4048 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4049 {
4050 switch (r->reg_num)
4051 {
4052 case 0:
4053 i.seg[i.mem_operands] = &es;
4054 break;
4055 case 1:
4056 i.seg[i.mem_operands] = &cs;
4057 break;
4058 case 2:
4059 i.seg[i.mem_operands] = &ss;
4060 break;
4061 case 3:
4062 i.seg[i.mem_operands] = &ds;
4063 break;
4064 case 4:
4065 i.seg[i.mem_operands] = &fs;
4066 break;
4067 case 5:
4068 i.seg[i.mem_operands] = &gs;
4069 break;
4070 }
252b5132 4071
24eab124 4072 /* Skip the ':' and whitespace. */
252b5132
RH		 4073 ++op_string;
4074 if (is_space_char (*op_string))
24eab124 4075 ++op_string;
252b5132 4076
24eab124
AM		 4077 if (!is_digit_char (*op_string)
4078 && !is_identifier_char (*op_string)
4079 && *op_string != '('
4080 && *op_string != ABSOLUTE_PREFIX)
4081 {
4082 as_bad (_("bad memory operand `%s'"), op_string);
4083 return 0;
4084 }
47926f60 4085 /* Handle case of %es:*foo. */
24eab124
AM		 4086 if (*op_string == ABSOLUTE_PREFIX)
4087 {
4088 ++op_string;
4089 if (is_space_char (*op_string))
4090 ++op_string;
4091 i.types[this_operand] |= JumpAbsolute;
4092 }
4093 goto do_memory_reference;
4094 }
4095 if (*op_string)
4096 {
d0b47220 4097 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 4098 return 0;
4099 }
4100 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 4101 i.op[this_operand].regs = r;
24eab124
AM		 4102 i.reg_operands++;
4103 }
af6bdddf
AM		 4104 else if (*op_string == REGISTER_PREFIX)
4105 {
4106 as_bad (_("bad register name `%s'"), op_string);
4107 return 0;
4108 }
24eab124 4109 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 4110 {
24eab124
AM		 4111 ++op_string;
4112 if (i.types[this_operand] & JumpAbsolute)
4113 {
d0b47220 4114 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 4115 return 0;
4116 }
4117 if (!i386_immediate (op_string))
4118 return 0;
4119 }
4120 else if (is_digit_char (*op_string)
4121 || is_identifier_char (*op_string)
e5cb08ac 4122 || *op_string == '(')
24eab124 4123 {
47926f60 4124 /* This is a memory reference of some sort. */
af6bdddf 4125 char *base_string;
252b5132 4126
47926f60 4127 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 4128 char *displacement_string_start;
4129 char *displacement_string_end;
252b5132 4130
24eab124 4131 do_memory_reference:
24eab124
AM		 4132 if ((i.mem_operands == 1
4133 && (current_templates->start->opcode_modifier & IsString) == 0)
4134 || i.mem_operands == 2)
4135 {
4136 as_bad (_("too many memory references for `%s'"),
4137 current_templates->start->name);
4138 return 0;
4139 }
252b5132 4140
24eab124
AM		 4141 /* Check for base index form. We detect the base index form by
4142 looking for an ')' at the end of the operand, searching
4143 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4144 after the '('. */
af6bdddf 4145 base_string = op_string + strlen (op_string);
c3332e24 4146
af6bdddf
AM		 4147 --base_string;
4148 if (is_space_char (*base_string))
4149 --base_string;
252b5132 4150
47926f60 4151 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 4152 displacement_string_start = op_string;
4153 displacement_string_end = base_string + 1;
252b5132 4154
24eab124
AM		 4155 if (*base_string == ')')
4156 {
af6bdddf 4157 char *temp_string;
24eab124
AM		 4158 unsigned int parens_balanced = 1;
4159 /* We've already checked that the number of left & right ()'s are
47926f60 4160 equal, so this loop will not be infinite. */
24eab124
AM		 4161 do
4162 {
4163 base_string--;
4164 if (*base_string == ')')
4165 parens_balanced++;
4166 if (*base_string == '(')
4167 parens_balanced--;
4168 }
4169 while (parens_balanced);
c3332e24 4170
af6bdddf 4171 temp_string = base_string;
c3332e24 4172
24eab124 4173 /* Skip past '(' and whitespace. */
252b5132
RH		 4174 ++base_string;
4175 if (is_space_char (*base_string))
24eab124 4176 ++base_string;
252b5132 4177
af6bdddf
AM		 4178 if (*base_string == ','
4179 || ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4180 && (i.base_reg = parse_register (base_string, &end_op)) != NULL))
252b5132 4181 {
af6bdddf 4182 displacement_string_end = temp_string;
252b5132 4183
af6bdddf 4184 i.types[this_operand] |= BaseIndex;
252b5132 4185
af6bdddf 4186 if (i.base_reg)
24eab124 4187 {
24eab124
AM		 4188 base_string = end_op;
4189 if (is_space_char (*base_string))
4190 ++base_string;
af6bdddf
AM		 4191 }
4192
4193 /* There may be an index reg or scale factor here. */
4194 if (*base_string == ',')
4195 {
4196 ++base_string;
4197 if (is_space_char (*base_string))
4198 ++base_string;
4199
4200 if ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4201 && (i.index_reg = parse_register (base_string, &end_op)) != NULL)
24eab124 4202 {
af6bdddf 4203 base_string = end_op;
24eab124
AM		 4204 if (is_space_char (*base_string))
4205 ++base_string;
af6bdddf
AM		 4206 if (*base_string == ',')
4207 {
4208 ++base_string;
4209 if (is_space_char (*base_string))
4210 ++base_string;
4211 }
e5cb08ac 4212 else if (*base_string != ')')
af6bdddf
AM		 4213 {
4214 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4215 operand_string);
4216 return 0;
4217 }
24eab124 4218 }
af6bdddf 4219 else if (*base_string == REGISTER_PREFIX)
24eab124 4220 {
af6bdddf 4221 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 4222 return 0;
4223 }
252b5132 4224
47926f60 4225 /* Check for scale factor. */
551c1ca1 4226 if (*base_string != ')')
af6bdddf 4227 {
551c1ca1
AM		 4228 char *end_scale = i386_scale (base_string);
4229
4230 if (!end_scale)
af6bdddf 4231 return 0;
24eab124 4232
551c1ca1 4233 base_string = end_scale;
af6bdddf
AM		 4234 if (is_space_char (*base_string))
4235 ++base_string;
4236 if (*base_string != ')')
4237 {
4238 as_bad (_("expecting `)' after scale factor in `%s'"),
4239 operand_string);
4240 return 0;
4241 }
4242 }
4243 else if (!i.index_reg)
24eab124 4244 {
af6bdddf
AM		 4245 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4246 *base_string);
24eab124
AM		 4247 return 0;
4248 }
4249 }
af6bdddf 4250 else if (*base_string != ')')
24eab124 4251 {
af6bdddf
AM		 4252 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4253 operand_string);
24eab124
AM		 4254 return 0;
4255 }
c3332e24 4256 }
af6bdddf 4257 else if (*base_string == REGISTER_PREFIX)
c3332e24 4258 {
af6bdddf 4259 as_bad (_("bad register name `%s'"), base_string);
24eab124 4260 return 0;
c3332e24 4261 }
24eab124
AM		 4262 }
4263
4264 /* If there's an expression beginning the operand, parse it,
4265 assuming displacement_string_start and
4266 displacement_string_end are meaningful. */
4267 if (displacement_string_start != displacement_string_end)
4268 {
4269 if (!i386_displacement (displacement_string_start,
4270 displacement_string_end))
4271 return 0;
4272 }
4273
4274 /* Special case for (%dx) while doing input/output op. */
4275 if (i.base_reg
4276 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
4277 && i.index_reg == 0
4278 && i.log2_scale_factor == 0
4279 && i.seg[i.mem_operands] == 0
4280 && (i.types[this_operand] & Disp) == 0)
4281 {
4282 i.types[this_operand] = InOutPortReg;
4283 return 1;
4284 }
4285
eecb386c
AM		 4286 if (i386_index_check (operand_string) == 0)
4287 return 0;
24eab124
AM		 4288 i.mem_operands++;
4289 }
4290 else
ce8a8b2f
AM		 4291 {
4292 /* It's not a memory operand; argh! */
24eab124
AM		 4293 as_bad (_("invalid char %s beginning operand %d `%s'"),
4294 output_invalid (*op_string),
4295 this_operand + 1,
4296 op_string);
4297 return 0;
4298 }
47926f60 4299 return 1; /* Normal return. */
252b5132
RH		 4300}
4301\f
ee7fcc42
AM		 4302/* md_estimate_size_before_relax()
4303
4304 Called just before relax() for rs_machine_dependent frags. The x86
4305 assembler uses these frags to handle variable size jump
4306 instructions.
4307
4308 Any symbol that is now undefined will not become defined.
4309 Return the correct fr_subtype in the frag.
4310 Return the initial "guess for variable size of frag" to caller.
4311 The guess is actually the growth beyond the fixed part. Whatever
4312 we do to grow the fixed or variable part contributes to our
4313 returned value. */
4314
252b5132
RH		 4315int
4316md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 4317 fragS *fragP;
4318 segT segment;
252b5132 4319{
252b5132 4320 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 4321 check for un-relaxable symbols. On an ELF system, we can't relax
4322 an externally visible symbol, because it may be overridden by a
4323 shared library. */
4324 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 4325#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
31312f95
AM		 4326 || (OUTPUT_FLAVOR == bfd_target_elf_flavour
4327 && (S_IS_EXTERNAL (fragP->fr_symbol)
4328 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 4329#endif
4330 )
252b5132 4331 {
b98ef147
AM		 4332 /* Symbol is undefined in this segment, or we need to keep a
4333 reloc so that weak symbols can be overridden. */
4334 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f3c180ae 4335 RELOC_ENUM reloc_type;
ee7fcc42
AM		 4336 unsigned char *opcode;
4337 int old_fr_fix;
f6af82bd 4338
ee7fcc42
AM		 4339 if (fragP->fr_var != NO_RELOC)
4340 reloc_type = fragP->fr_var;
b98ef147 4341 else if (size == 2)
f6af82bd
AM		 4342 reloc_type = BFD_RELOC_16_PCREL;
4343 else
4344 reloc_type = BFD_RELOC_32_PCREL;
252b5132 4345
ee7fcc42
AM		 4346 old_fr_fix = fragP->fr_fix;
4347 opcode = (unsigned char *) fragP->fr_opcode;
4348
fddf5b5b 4349 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 4350 {
fddf5b5b
AM		 4351 case UNCOND_JUMP:
4352 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 4353 opcode[0] = 0xe9;
252b5132 4354 fragP->fr_fix += size;
062cd5e7
AS		 4355 fix_new (fragP, old_fr_fix, size,
4356 fragP->fr_symbol,
4357 fragP->fr_offset, 1,
4358 reloc_type);
252b5132
RH		 4359 break;
4360
fddf5b5b 4361 case COND_JUMP86:
412167cb
AM		 4362 if (size == 2
4363 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 4364 {
4365 /* Negate the condition, and branch past an
4366 unconditional jump. */
4367 opcode[0] ^= 1;
4368 opcode[1] = 3;
4369 /* Insert an unconditional jump. */
4370 opcode[2] = 0xe9;
4371 /* We added two extra opcode bytes, and have a two byte
4372 offset. */
4373 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 4374 fix_new (fragP, old_fr_fix + 2, 2,
4375 fragP->fr_symbol,
4376 fragP->fr_offset, 1,
4377 reloc_type);
fddf5b5b
AM		 4378 break;
4379 }
4380 /* Fall through. */
4381
4382 case COND_JUMP:
412167cb
AM		 4383 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
4384 {
4385 fragP->fr_fix += 1;
4386 fix_new (fragP, old_fr_fix, 1,
4387 fragP->fr_symbol,
4388 fragP->fr_offset, 1,
4389 BFD_RELOC_8_PCREL);
4390 break;
4391 }
93c2a809 4392
24eab124 4393 /* This changes the byte-displacement jump 0x7N
fddf5b5b 4394 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 4395 opcode[1] = opcode[0] + 0x10;
f6af82bd 4396 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 4397 /* We've added an opcode byte. */
4398 fragP->fr_fix += 1 + size;
062cd5e7
AS		 4399 fix_new (fragP, old_fr_fix + 1, size,
4400 fragP->fr_symbol,
4401 fragP->fr_offset, 1,
4402 reloc_type);
252b5132 4403 break;
fddf5b5b
AM		 4404
4405 default:
4406 BAD_CASE (fragP->fr_subtype);
4407 break;
252b5132
RH		 4408 }
4409 frag_wane (fragP);
ee7fcc42 4410 return fragP->fr_fix - old_fr_fix;
252b5132 4411 }
93c2a809 4412
93c2a809
AM		 4413 /* Guess size depending on current relax state. Initially the relax
4414 state will correspond to a short jump and we return 1, because
4415 the variable part of the frag (the branch offset) is one byte
4416 long. However, we can relax a section more than once and in that
4417 case we must either set fr_subtype back to the unrelaxed state,
4418 or return the value for the appropriate branch. */
4419 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 4420}
4421
47926f60
KH		 4422/* Called after relax() is finished.
4423
4424 In: Address of frag.
4425 fr_type == rs_machine_dependent.
4426 fr_subtype is what the address relaxed to.
4427
4428 Out: Any fixSs and constants are set up.
4429 Caller will turn frag into a ".space 0". */
4430
252b5132
RH		 4431#ifndef BFD_ASSEMBLER
4432void
4433md_convert_frag (headers, sec, fragP)
a04b544b
ILT		 4434 object_headers *headers ATTRIBUTE_UNUSED;
4435 segT sec ATTRIBUTE_UNUSED;
29b0f896 4436 fragS *fragP;
252b5132
RH		 4437#else
4438void
4439md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 4440 bfd *abfd ATTRIBUTE_UNUSED;
4441 segT sec ATTRIBUTE_UNUSED;
29b0f896 4442 fragS *fragP;
252b5132
RH		 4443#endif
4444{
29b0f896 4445 unsigned char *opcode;
252b5132 4446 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 4447 offsetT target_address;
4448 offsetT opcode_address;
252b5132 4449 unsigned int extension = 0;
847f7ad4 4450 offsetT displacement_from_opcode_start;
252b5132
RH		 4451
4452 opcode = (unsigned char *) fragP->fr_opcode;
4453
47926f60 4454 /* Address we want to reach in file space. */
252b5132 4455 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 4456
47926f60 4457 /* Address opcode resides at in file space. */
252b5132
RH		 4458 opcode_address = fragP->fr_address + fragP->fr_fix;
4459
47926f60 4460 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 4461 displacement_from_opcode_start = target_address - opcode_address;
4462
fddf5b5b 4463 if ((fragP->fr_subtype & BIG) == 0)
252b5132 4464 {
47926f60
KH		 4465 /* Don't have to change opcode. */
4466 extension = 1; /* 1 opcode + 1 displacement */
252b5132 4467 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 4468 }
4469 else
4470 {
4471 if (no_cond_jump_promotion
4472 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4473 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
252b5132 4474
fddf5b5b
AM		 4475 switch (fragP->fr_subtype)
4476 {
4477 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
4478 extension = 4; /* 1 opcode + 4 displacement */
4479 opcode[0] = 0xe9;
4480 where_to_put_displacement = &opcode[1];
4481 break;
252b5132 4482
fddf5b5b
AM		 4483 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
4484 extension = 2; /* 1 opcode + 2 displacement */
4485 opcode[0] = 0xe9;
4486 where_to_put_displacement = &opcode[1];
4487 break;
252b5132 4488
fddf5b5b
AM		 4489 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
4490 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
4491 extension = 5; /* 2 opcode + 4 displacement */
4492 opcode[1] = opcode[0] + 0x10;
4493 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4494 where_to_put_displacement = &opcode[2];
4495 break;
252b5132 4496
fddf5b5b
AM		 4497 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
4498 extension = 3; /* 2 opcode + 2 displacement */
4499 opcode[1] = opcode[0] + 0x10;
4500 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4501 where_to_put_displacement = &opcode[2];
4502 break;
252b5132 4503
fddf5b5b
AM		 4504 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
4505 extension = 4;
4506 opcode[0] ^= 1;
4507 opcode[1] = 3;
4508 opcode[2] = 0xe9;
4509 where_to_put_displacement = &opcode[3];
4510 break;
4511
4512 default:
4513 BAD_CASE (fragP->fr_subtype);
4514 break;
4515 }
252b5132 4516 }
fddf5b5b 4517
47926f60 4518 /* Now put displacement after opcode. */
252b5132
RH		 4519 md_number_to_chars ((char *) where_to_put_displacement,
4520 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 4521 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 4522 fragP->fr_fix += extension;
4523}
4524\f
47926f60
KH		 4525/* Size of byte displacement jmp. */
4526int md_short_jump_size = 2;
4527
4528/* Size of dword displacement jmp. */
4529int md_long_jump_size = 5;
252b5132 4530
47926f60
KH		 4531/* Size of relocation record. */
4532const int md_reloc_size = 8;
252b5132
RH		 4533
4534void
4535md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4536 char *ptr;
4537 addressT from_addr, to_addr;
ab9da554
ILT		 4538 fragS *frag ATTRIBUTE_UNUSED;
4539 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4540{
847f7ad4 4541 offsetT offset;
252b5132
RH		 4542
4543 offset = to_addr - (from_addr + 2);
47926f60
KH		 4544 /* Opcode for byte-disp jump. */
4545 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 4546 md_number_to_chars (ptr + 1, (valueT) offset, 1);
4547}
4548
4549void
4550md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4551 char *ptr;
4552 addressT from_addr, to_addr;
a38cf1db
AM		 4553 fragS *frag ATTRIBUTE_UNUSED;
4554 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4555{
847f7ad4 4556 offsetT offset;
252b5132 4557
a38cf1db
AM		 4558 offset = to_addr - (from_addr + 5);
4559 md_number_to_chars (ptr, (valueT) 0xe9, 1);
4560 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 4561}
4562\f
4563/* Apply a fixup (fixS) to segment data, once it has been determined
4564 by our caller that we have all the info we need to fix it up.
4565
4566 On the 386, immediates, displacements, and data pointers are all in
4567 the same (little-endian) format, so we don't need to care about which
4568 we are handling. */
4569
94f592af
NC		 4570void
4571md_apply_fix3 (fixP, valP, seg)
47926f60
KH		 4572 /* The fix we're to put in. */
4573 fixS *fixP;
47926f60 4574 /* Pointer to the value of the bits. */
c6682705 4575 valueT *valP;
47926f60
KH		 4576 /* Segment fix is from. */
4577 segT seg ATTRIBUTE_UNUSED;
252b5132 4578{
94f592af 4579 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 4580 valueT value = *valP;
252b5132 4581
e1b283bb 4582#if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
93382f6d
AM		 4583 if (fixP->fx_pcrel)
4584 {
4585 switch (fixP->fx_r_type)
4586 {
5865bb77
ILT		 4587 default:
4588 break;
4589
93382f6d
AM		 4590 case BFD_RELOC_32:
4591 fixP->fx_r_type = BFD_RELOC_32_PCREL;
4592 break;
4593 case BFD_RELOC_16:
4594 fixP->fx_r_type = BFD_RELOC_16_PCREL;
4595 break;
4596 case BFD_RELOC_8:
4597 fixP->fx_r_type = BFD_RELOC_8_PCREL;
4598 break;
4599 }
4600 }
252b5132 4601
a161fe53 4602 if (fixP->fx_addsy != NULL
31312f95
AM		 4603 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
4604 || fixP->fx_r_type == BFD_RELOC_16_PCREL
4605 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4606 && !use_rela_relocations)
252b5132 4607 {
31312f95
AM		 4608 /* This is a hack. There should be a better way to handle this.
4609 This covers for the fact that bfd_install_relocation will
4610 subtract the current location (for partial_inplace, PC relative
4611 relocations); see more below. */
252b5132
RH		 4612#ifndef OBJ_AOUT
4613 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4614#ifdef TE_PE
4615 || OUTPUT_FLAVOR == bfd_target_coff_flavour
4616#endif
4617 )
4618 value += fixP->fx_where + fixP->fx_frag->fr_address;
4619#endif
4620#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2f66722d 4621 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
252b5132 4622 {
2f66722d
AM		 4623 segT fseg = S_GET_SEGMENT (fixP->fx_addsy);
4624
4625 if ((fseg == seg
4626 || (symbol_section_p (fixP->fx_addsy)
4627 && fseg != absolute_section))
29b0f896
AM		 4628 && !S_IS_EXTERNAL (fixP->fx_addsy)
4629 && !S_IS_WEAK (fixP->fx_addsy)
2f66722d 4630 && S_IS_DEFINED (fixP->fx_addsy)
29b0f896 4631 && !S_IS_COMMON (fixP->fx_addsy))
2f66722d
AM		 4632 {
4633 /* Yes, we add the values in twice. This is because
4634 bfd_perform_relocation subtracts them out again. I think
4635 bfd_perform_relocation is broken, but I don't dare change
4636 it. FIXME. */
4637 value += fixP->fx_where + fixP->fx_frag->fr_address;
4638 }
252b5132
RH		 4639 }
4640#endif
4641#if defined (OBJ_COFF) && defined (TE_PE)
4642 /* For some reason, the PE format does not store a section
24eab124 4643 address offset for a PC relative symbol. */
252b5132
RH		 4644 if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
4645 value += md_pcrel_from (fixP);
4646#endif
4647 }
4648
4649 /* Fix a few things - the dynamic linker expects certain values here,
47926f60 4650 and we must not dissappoint it. */
252b5132
RH		 4651#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4652 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4653 && fixP->fx_addsy)
47926f60
KH		 4654 switch (fixP->fx_r_type)
4655 {
4656 case BFD_RELOC_386_PLT32:
3e73aa7c 4657 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 4658 /* Make the jump instruction point to the address of the operand. At
4659 runtime we merely add the offset to the actual PLT entry. */
4660 value = -4;
4661 break;
31312f95 4662
47926f60 4663 case BFD_RELOC_386_GOT32:
13ae64f3
JJ		 4664 case BFD_RELOC_386_TLS_GD:
4665 case BFD_RELOC_386_TLS_LDM:
13ae64f3 4666 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 4667 case BFD_RELOC_386_TLS_IE:
4668 case BFD_RELOC_386_TLS_GOTIE:
3e73aa7c 4669 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 4670 value = 0; /* Fully resolved at runtime. No addend. */
4671 break;
47926f60
KH		 4672
4673 case BFD_RELOC_VTABLE_INHERIT:
4674 case BFD_RELOC_VTABLE_ENTRY:
4675 fixP->fx_done = 0;
94f592af 4676 return;
47926f60
KH		 4677
4678 default:
4679 break;
4680 }
4681#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 4682 *valP = value;
47926f60 4683#endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
3e73aa7c 4684
3e73aa7c 4685 /* Are we finished with this relocation now? */
c6682705 4686 if (fixP->fx_addsy == NULL)
3e73aa7c 4687 fixP->fx_done = 1;
94f592af 4688#ifdef BFD_ASSEMBLER
3e73aa7c
JH		 4689 else if (use_rela_relocations)
4690 {
4691 fixP->fx_no_overflow = 1;
062cd5e7
AS		 4692 /* Remember value for tc_gen_reloc. */
4693 fixP->fx_addnumber = value;
3e73aa7c
JH		 4694 value = 0;
4695 }
3e73aa7c 4696#endif
94f592af 4697 md_number_to_chars (p, value, fixP->fx_size);
252b5132 4698}
252b5132 4699\f
252b5132
RH		 4700#define MAX_LITTLENUMS 6
4701
47926f60
KH		 4702/* Turn the string pointed to by litP into a floating point constant
4703 of type TYPE, and emit the appropriate bytes. The number of
4704 LITTLENUMS emitted is stored in *SIZEP. An error message is
4705 returned, or NULL on OK. */
4706
252b5132
RH		 4707char *
4708md_atof (type, litP, sizeP)
2ab9b79e 4709 int type;
252b5132
RH		 4710 char *litP;
4711 int *sizeP;
4712{
4713 int prec;
4714 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4715 LITTLENUM_TYPE *wordP;
4716 char *t;
4717
4718 switch (type)
4719 {
4720 case 'f':
4721 case 'F':
4722 prec = 2;
4723 break;
4724
4725 case 'd':
4726 case 'D':
4727 prec = 4;
4728 break;
4729
4730 case 'x':
4731 case 'X':
4732 prec = 5;
4733 break;
4734
4735 default:
4736 *sizeP = 0;
4737 return _("Bad call to md_atof ()");
4738 }
4739 t = atof_ieee (input_line_pointer, type, words);
4740 if (t)
4741 input_line_pointer = t;
4742
4743 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4744 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4745 the bigendian 386. */
4746 for (wordP = words + prec - 1; prec--;)
4747 {
4748 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
4749 litP += sizeof (LITTLENUM_TYPE);
4750 }
4751 return 0;
4752}
4753\f
4754char output_invalid_buf[8];
4755
252b5132
RH		 4756static char *
4757output_invalid (c)
4758 int c;
4759{
3882b010 4760 if (ISPRINT (c))
252b5132
RH		 4761 sprintf (output_invalid_buf, "'%c'", c);
4762 else
4763 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
4764 return output_invalid_buf;
4765}
4766
af6bdddf 4767/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 4768
4769static const reg_entry *
4770parse_register (reg_string, end_op)
4771 char *reg_string;
4772 char **end_op;
4773{
af6bdddf
AM		 4774 char *s = reg_string;
4775 char *p;
252b5132
RH		 4776 char reg_name_given[MAX_REG_NAME_SIZE + 1];
4777 const reg_entry *r;
4778
4779 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4780 if (*s == REGISTER_PREFIX)
4781 ++s;
4782
4783 if (is_space_char (*s))
4784 ++s;
4785
4786 p = reg_name_given;
af6bdddf 4787 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 4788 {
4789 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 4790 return (const reg_entry *) NULL;
4791 s++;
252b5132
RH		 4792 }
4793
6588847e
DN		 4794 /* For naked regs, make sure that we are not dealing with an identifier.
4795 This prevents confusing an identifier like `eax_var' with register
4796 `eax'. */
4797 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
4798 return (const reg_entry *) NULL;
4799
af6bdddf 4800 *end_op = s;
252b5132
RH		 4801
4802 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
4803
5f47d35b 4804 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 4805 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 4806 {
5f47d35b
AM		 4807 if (is_space_char (*s))
4808 ++s;
4809 if (*s == '(')
4810 {
af6bdddf 4811 ++s;
5f47d35b
AM		 4812 if (is_space_char (*s))
4813 ++s;
4814 if (*s >= '0' && *s <= '7')
4815 {
4816 r = &i386_float_regtab[*s - '0'];
af6bdddf 4817 ++s;
5f47d35b
AM		 4818 if (is_space_char (*s))
4819 ++s;
4820 if (*s == ')')
4821 {
4822 *end_op = s + 1;
4823 return r;
4824 }
5f47d35b 4825 }
47926f60 4826 /* We have "%st(" then garbage. */
5f47d35b
AM		 4827 return (const reg_entry *) NULL;
4828 }
4829 }
4830
1ae00879 4831 if (r != NULL
29b0f896 4832 && (r->reg_flags & (RegRex64 | RegRex)) != 0
1ae00879
AM		 4833 && flag_code != CODE_64BIT)
4834 {
4835 return (const reg_entry *) NULL;
4836 }
4837
252b5132
RH		 4838 return r;
4839}
4840\f
4cc782b5 4841#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
65172ab8 4842const char *md_shortopts = "kVQ:sq";
252b5132 4843#else
65172ab8 4844const char *md_shortopts = "q";
252b5132 4845#endif
6e0b89ee 4846
252b5132 4847struct option md_longopts[] = {
3e73aa7c
JH		 4848#define OPTION_32 (OPTION_MD_BASE + 0)
4849 {"32", no_argument, NULL, OPTION_32},
6e0b89ee 4850#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3e73aa7c
JH		 4851#define OPTION_64 (OPTION_MD_BASE + 1)
4852 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 4853#endif
252b5132
RH		 4854 {NULL, no_argument, NULL, 0}
4855};
4856size_t md_longopts_size = sizeof (md_longopts);
4857
4858int
4859md_parse_option (c, arg)
4860 int c;
ab9da554 4861 char *arg ATTRIBUTE_UNUSED;
252b5132
RH		 4862{
4863 switch (c)
4864 {
a38cf1db
AM		 4865 case 'q':
4866 quiet_warnings = 1;
252b5132
RH		 4867 break;
4868
4869#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 4870 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4871 should be emitted or not. FIXME: Not implemented. */
4872 case 'Q':
252b5132
RH		 4873 break;
4874
4875 /* -V: SVR4 argument to print version ID. */
4876 case 'V':
4877 print_version_id ();
4878 break;
4879
a38cf1db
AM		 4880 /* -k: Ignore for FreeBSD compatibility. */
4881 case 'k':
252b5132 4882 break;
4cc782b5
ILT		 4883
4884 case 's':
4885 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 4886 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 4887 break;
6e0b89ee 4888
3e73aa7c
JH		 4889 case OPTION_64:
4890 {
4891 const char **list, **l;
4892
3e73aa7c
JH		 4893 list = bfd_target_list ();
4894 for (l = list; *l != NULL; l++)
6e0b89ee
AM		 4895 if (strcmp (*l, "elf64-x86-64") == 0)
4896 {
4897 default_arch = "x86_64";
4898 break;
4899 }
3e73aa7c 4900 if (*l == NULL)
6e0b89ee 4901 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 4902 free (list);
4903 }
4904 break;
4905#endif
252b5132 4906
6e0b89ee
AM		 4907 case OPTION_32:
4908 default_arch = "i386";
4909 break;
4910
252b5132
RH		 4911 default:
4912 return 0;
4913 }
4914 return 1;
4915}
4916
4917void
4918md_show_usage (stream)
4919 FILE *stream;
4920{
4cc782b5
ILT		 4921#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4922 fprintf (stream, _("\
a38cf1db
AM		 4923 -Q ignored\n\
4924 -V print assembler version number\n\
4925 -k ignored\n\
4926 -q quieten some warnings\n\
4927 -s ignored\n"));
4928#else
4929 fprintf (stream, _("\
4930 -q quieten some warnings\n"));
4cc782b5 4931#endif
252b5132
RH		 4932}
4933
4934#ifdef BFD_ASSEMBLER
3e73aa7c
JH		 4935#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4936 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 4937
4938/* Pick the target format to use. */
4939
47926f60 4940const char *
252b5132
RH		 4941i386_target_format ()
4942{
3e73aa7c
JH		 4943 if (!strcmp (default_arch, "x86_64"))
4944 set_code_flag (CODE_64BIT);
4945 else if (!strcmp (default_arch, "i386"))
4946 set_code_flag (CODE_32BIT);
4947 else
4948 as_fatal (_("Unknown architecture"));
252b5132
RH		 4949 switch (OUTPUT_FLAVOR)
4950 {
4c63da97
AM		 4951#ifdef OBJ_MAYBE_AOUT
4952 case bfd_target_aout_flavour:
47926f60 4953 return AOUT_TARGET_FORMAT;
4c63da97
AM		 4954#endif
4955#ifdef OBJ_MAYBE_COFF
252b5132
RH		 4956 case bfd_target_coff_flavour:
4957 return "coff-i386";
4c63da97 4958#endif
3e73aa7c 4959#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 4960 case bfd_target_elf_flavour:
3e73aa7c 4961 {
e5cb08ac
KH		 4962 if (flag_code == CODE_64BIT)
4963 use_rela_relocations = 1;
4ada7262 4964 return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT;
3e73aa7c 4965 }
4c63da97 4966#endif
252b5132
RH		 4967 default:
4968 abort ();
4969 return NULL;
4970 }
4971}
4972
47926f60 4973#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 4974
4975#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4976void i386_elf_emit_arch_note ()
4977{
4978 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4979 && cpu_arch_name != NULL)
4980 {
4981 char *p;
4982 asection *seg = now_seg;
4983 subsegT subseg = now_subseg;
4984 Elf_Internal_Note i_note;
4985 Elf_External_Note e_note;
4986 asection *note_secp;
4987 int len;
4988
4989 /* Create the .note section. */
4990 note_secp = subseg_new (".note", 0);
4991 bfd_set_section_flags (stdoutput,
4992 note_secp,
4993 SEC_HAS_CONTENTS | SEC_READONLY);
4994
4995 /* Process the arch string. */
4996 len = strlen (cpu_arch_name);
4997
4998 i_note.namesz = len + 1;
4999 i_note.descsz = 0;
5000 i_note.type = NT_ARCH;
5001 p = frag_more (sizeof (e_note.namesz));
5002 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
5003 p = frag_more (sizeof (e_note.descsz));
5004 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
5005 p = frag_more (sizeof (e_note.type));
5006 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
5007 p = frag_more (len + 1);
5008 strcpy (p, cpu_arch_name);
5009
5010 frag_align (2, 0, 0);
5011
5012 subseg_set (seg, subseg);
5013 }
5014}
5015#endif
47926f60 5016#endif /* BFD_ASSEMBLER */
252b5132 5017\f
252b5132
RH		 5018symbolS *
5019md_undefined_symbol (name)
5020 char *name;
5021{
18dc2407
ILT		 5022 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
5023 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
5024 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
5025 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 5026 {
5027 if (!GOT_symbol)
5028 {
5029 if (symbol_find (name))
5030 as_bad (_("GOT already in symbol table"));
5031 GOT_symbol = symbol_new (name, undefined_section,
5032 (valueT) 0, &zero_address_frag);
5033 };
5034 return GOT_symbol;
5035 }
252b5132
RH		 5036 return 0;
5037}
5038
5039/* Round up a section size to the appropriate boundary. */
47926f60 5040
252b5132
RH		 5041valueT
5042md_section_align (segment, size)
ab9da554 5043 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 5044 valueT size;
5045{
252b5132 5046#ifdef BFD_ASSEMBLER
4c63da97
AM		 5047#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5048 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
5049 {
5050 /* For a.out, force the section size to be aligned. If we don't do
5051 this, BFD will align it for us, but it will not write out the
5052 final bytes of the section. This may be a bug in BFD, but it is
5053 easier to fix it here since that is how the other a.out targets
5054 work. */
5055 int align;
5056
5057 align = bfd_get_section_alignment (stdoutput, segment);
5058 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
5059 }
252b5132
RH		 5060#endif
5061#endif
5062
5063 return size;
5064}
5065
5066/* On the i386, PC-relative offsets are relative to the start of the
5067 next instruction. That is, the address of the offset, plus its
5068 size, since the offset is always the last part of the insn. */
5069
5070long
5071md_pcrel_from (fixP)
5072 fixS *fixP;
5073{
5074 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
5075}
5076
5077#ifndef I386COFF
5078
5079static void
5080s_bss (ignore)
ab9da554 5081 int ignore ATTRIBUTE_UNUSED;
252b5132 5082{
29b0f896 5083 int temp;
252b5132
RH		 5084
5085 temp = get_absolute_expression ();
5086 subseg_set (bss_section, (subsegT) temp);
5087 demand_empty_rest_of_line ();
5088}
5089
5090#endif
5091
252b5132
RH		 5092#ifdef BFD_ASSEMBLER
5093
5094void
5095i386_validate_fix (fixp)
5096 fixS *fixp;
5097{
5098 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
5099 {
3e73aa7c 5100 /* GOTOFF relocation are nonsense in 64bit mode. */
23df1078
JH		 5101 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
5102 {
5103 if (flag_code != CODE_64BIT)
5104 abort ();
5105 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
5106 }
5107 else
5108 {
5109 if (flag_code == CODE_64BIT)
5110 abort ();
5111 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
5112 }
252b5132
RH		 5113 fixp->fx_subsy = 0;
5114 }
5115}
5116
a161fe53
AM		 5117boolean
5118i386_force_relocation (fixp)
5119 fixS *fixp;
5120{
5121 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
5122 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5123 return 1;
5124
5125 return S_FORCE_RELOC (fixp->fx_addsy);
5126}
5127
252b5132
RH		 5128arelent *
5129tc_gen_reloc (section, fixp)
ab9da554 5130 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 5131 fixS *fixp;
5132{
5133 arelent *rel;
5134 bfd_reloc_code_real_type code;
5135
5136 switch (fixp->fx_r_type)
5137 {
3e73aa7c
JH		 5138 case BFD_RELOC_X86_64_PLT32:
5139 case BFD_RELOC_X86_64_GOT32:
5140 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 5141 case BFD_RELOC_386_PLT32:
5142 case BFD_RELOC_386_GOT32:
5143 case BFD_RELOC_386_GOTOFF:
5144 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 5145 case BFD_RELOC_386_TLS_GD:
5146 case BFD_RELOC_386_TLS_LDM:
5147 case BFD_RELOC_386_TLS_LDO_32:
5148 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5149 case BFD_RELOC_386_TLS_IE:
5150 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 5151 case BFD_RELOC_386_TLS_LE_32:
5152 case BFD_RELOC_386_TLS_LE:
3e73aa7c 5153 case BFD_RELOC_X86_64_32S:
252b5132
RH		 5154 case BFD_RELOC_RVA:
5155 case BFD_RELOC_VTABLE_ENTRY:
5156 case BFD_RELOC_VTABLE_INHERIT:
5157 code = fixp->fx_r_type;
5158 break;
5159 default:
93382f6d 5160 if (fixp->fx_pcrel)
252b5132 5161 {
93382f6d
AM		 5162 switch (fixp->fx_size)
5163 {
5164 default:
b091f402
AM		 5165 as_bad_where (fixp->fx_file, fixp->fx_line,
5166 _("can not do %d byte pc-relative relocation"),
5167 fixp->fx_size);
93382f6d
AM		 5168 code = BFD_RELOC_32_PCREL;
5169 break;
5170 case 1: code = BFD_RELOC_8_PCREL; break;
5171 case 2: code = BFD_RELOC_16_PCREL; break;
5172 case 4: code = BFD_RELOC_32_PCREL; break;
5173 }
5174 }
5175 else
5176 {
5177 switch (fixp->fx_size)
5178 {
5179 default:
b091f402
AM		 5180 as_bad_where (fixp->fx_file, fixp->fx_line,
5181 _("can not do %d byte relocation"),
5182 fixp->fx_size);
93382f6d
AM		 5183 code = BFD_RELOC_32;
5184 break;
5185 case 1: code = BFD_RELOC_8; break;
5186 case 2: code = BFD_RELOC_16; break;
5187 case 4: code = BFD_RELOC_32; break;
937149dd 5188#ifdef BFD64
3e73aa7c 5189 case 8: code = BFD_RELOC_64; break;
937149dd 5190#endif
93382f6d 5191 }
252b5132
RH		 5192 }
5193 break;
5194 }
252b5132
RH		 5195
5196 if (code == BFD_RELOC_32
5197 && GOT_symbol
5198 && fixp->fx_addsy == GOT_symbol)
3e73aa7c
JH		 5199 {
5200 /* We don't support GOTPC on 64bit targets. */
5201 if (flag_code == CODE_64BIT)
bfb32b52 5202 abort ();
3e73aa7c
JH		 5203 code = BFD_RELOC_386_GOTPC;
5204 }
252b5132
RH		 5205
5206 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 5207 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5208 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 5209
5210 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
3e73aa7c
JH		 5211 if (!use_rela_relocations)
5212 {
5213 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5214 vtable entry to be used in the relocation's section offset. */
5215 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5216 rel->address = fixp->fx_offset;
252b5132 5217
c6682705 5218 rel->addend = 0;
3e73aa7c
JH		 5219 }
5220 /* Use the rela in 64bit mode. */
252b5132 5221 else
3e73aa7c 5222 {
062cd5e7
AS		 5223 if (!fixp->fx_pcrel)
5224 rel->addend = fixp->fx_offset;
5225 else
5226 switch (code)
5227 {
5228 case BFD_RELOC_X86_64_PLT32:
5229 case BFD_RELOC_X86_64_GOT32:
5230 case BFD_RELOC_X86_64_GOTPCREL:
5231 rel->addend = fixp->fx_offset - fixp->fx_size;
5232 break;
5233 default:
5234 rel->addend = (section->vma
5235 - fixp->fx_size
5236 + fixp->fx_addnumber
5237 + md_pcrel_from (fixp));
5238 break;
5239 }
3e73aa7c
JH		 5240 }
5241
252b5132
RH		 5242 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
5243 if (rel->howto == NULL)
5244 {
5245 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 5246 _("cannot represent relocation type %s"),
252b5132
RH		 5247 bfd_get_reloc_code_name (code));
5248 /* Set howto to a garbage value so that we can keep going. */
5249 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
5250 assert (rel->howto != NULL);
5251 }
5252
5253 return rel;
5254}
5255
29b0f896 5256#else /* !BFD_ASSEMBLER */
252b5132
RH		 5257
5258#if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
5259void
5260tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
5261 char *where;
5262 fixS *fixP;
5263 relax_addressT segment_address_in_file;
5264{
47926f60
KH		 5265 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
5266 Out: GNU LD relocation length code: 0, 1, or 2. */
252b5132 5267
47926f60 5268 static const unsigned char nbytes_r_length[] = { 42, 0, 1, 42, 2 };
252b5132
RH		 5269 long r_symbolnum;
5270
5271 know (fixP->fx_addsy != NULL);
5272
5273 md_number_to_chars (where,
5274 (valueT) (fixP->fx_frag->fr_address
5275 + fixP->fx_where - segment_address_in_file),
5276 4);
5277
5278 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
5279 ? S_GET_TYPE (fixP->fx_addsy)
5280 : fixP->fx_addsy->sy_number);
5281
5282 where[6] = (r_symbolnum >> 16) & 0x0ff;
5283 where[5] = (r_symbolnum >> 8) & 0x0ff;
5284 where[4] = r_symbolnum & 0x0ff;
5285 where[7] = ((((!S_IS_DEFINED (fixP->fx_addsy)) << 3) & 0x08)
5286 | ((nbytes_r_length[fixP->fx_size] << 1) & 0x06)
5287 | (((fixP->fx_pcrel << 0) & 0x01) & 0x0f));
5288}
5289
47926f60 5290#endif /* OBJ_AOUT or OBJ_BOUT. */
252b5132
RH		 5291
5292#if defined (I386COFF)
5293
5294short
5295tc_coff_fix2rtype (fixP)
5296 fixS *fixP;
5297{
5298 if (fixP->fx_r_type == R_IMAGEBASE)
5299 return R_IMAGEBASE;
5300
5301 return (fixP->fx_pcrel ?
5302 (fixP->fx_size == 1 ? R_PCRBYTE :
5303 fixP->fx_size == 2 ? R_PCRWORD :
5304 R_PCRLONG) :
5305 (fixP->fx_size == 1 ? R_RELBYTE :
5306 fixP->fx_size == 2 ? R_RELWORD :
5307 R_DIR32));
5308}
5309
5310int
5311tc_coff_sizemachdep (frag)
5312 fragS *frag;
5313{
5314 if (frag->fr_next)
5315 return (frag->fr_next->fr_address - frag->fr_address);
5316 else
5317 return 0;
5318}
5319
47926f60 5320#endif /* I386COFF */
252b5132 5321
29b0f896 5322#endif /* !BFD_ASSEMBLER */
64a0c779
DN		 5323\f
5324/* Parse operands using Intel syntax. This implements a recursive descent
5325 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5326 Programmer's Guide.
5327
5328 FIXME: We do not recognize the full operand grammar defined in the MASM
5329 documentation. In particular, all the structure/union and
5330 high-level macro operands are missing.
5331
5332 Uppercase words are terminals, lower case words are non-terminals.
5333 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5334 bars '|' denote choices. Most grammar productions are implemented in
5335 functions called 'intel_<production>'.
5336
5337 Initial production is 'expr'.
5338
64a0c779
DN		 5339 addOp + | -
5340
5341 alpha [a-zA-Z]
5342
5343 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5344
5345 constant digits [[ radixOverride ]]
5346
5347 dataType BYTE | WORD | DWORD | QWORD | XWORD
5348
5349 digits decdigit
b77a7acd
AJ		 5350 | digits decdigit
5351 | digits hexdigit
64a0c779
DN		 5352
5353 decdigit [0-9]
5354
5355 e05 e05 addOp e06
b77a7acd 5356 | e06
64a0c779
DN		 5357
5358 e06 e06 mulOp e09
b77a7acd 5359 | e09
64a0c779
DN		 5360
5361 e09 OFFSET e10
5362 | e09 PTR e10
5363 | e09 : e10
5364 | e10
5365
5366 e10 e10 [ expr ]
b77a7acd 5367 | e11
64a0c779
DN		 5368
5369 e11 ( expr )
b77a7acd 5370 | [ expr ]
64a0c779
DN		 5371 | constant
5372 | dataType
5373 | id
5374 | $
5375 | register
5376
5377 => expr SHORT e05
b77a7acd 5378 | e05
64a0c779
DN		 5379
5380 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 5381 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 5382
5383 hexdigit a | b | c | d | e | f
b77a7acd 5384 | A | B | C | D | E | F
64a0c779
DN		 5385
5386 id alpha
b77a7acd 5387 | id alpha
64a0c779
DN		 5388 | id decdigit
5389
5390 mulOp * | / | MOD
5391
5392 quote " | '
5393
5394 register specialRegister
b77a7acd 5395 | gpRegister
64a0c779
DN		 5396 | byteRegister
5397
5398 segmentRegister CS | DS | ES | FS | GS | SS
5399
5400 specialRegister CR0 | CR2 | CR3
b77a7acd 5401 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 5402 | TR3 | TR4 | TR5 | TR6 | TR7
5403
64a0c779
DN		 5404 We simplify the grammar in obvious places (e.g., register parsing is
5405 done by calling parse_register) and eliminate immediate left recursion
5406 to implement a recursive-descent parser.
5407
5408 expr SHORT e05
b77a7acd 5409 | e05
64a0c779
DN		 5410
5411 e05 e06 e05'
5412
5413 e05' addOp e06 e05'
b77a7acd 5414 | Empty
64a0c779
DN		 5415
5416 e06 e09 e06'
5417
5418 e06' mulOp e09 e06'
b77a7acd 5419 | Empty
64a0c779
DN		 5420
5421 e09 OFFSET e10 e09'
b77a7acd 5422 | e10 e09'
64a0c779
DN		 5423
5424 e09' PTR e10 e09'
b77a7acd 5425 | : e10 e09'
64a0c779
DN		 5426 | Empty
5427
5428 e10 e11 e10'
5429
5430 e10' [ expr ] e10'
b77a7acd 5431 | Empty
64a0c779
DN		 5432
5433 e11 ( expr )
b77a7acd 5434 | [ expr ]
64a0c779
DN		 5435 | BYTE
5436 | WORD
5437 | DWORD
5438 | QWORD
5439 | XWORD
5440 | .
5441 | $
5442 | register
5443 | id
5444 | constant */
5445
5446/* Parsing structure for the intel syntax parser. Used to implement the
5447 semantic actions for the operand grammar. */
5448struct intel_parser_s
5449 {
5450 char *op_string; /* The string being parsed. */
5451 int got_a_float; /* Whether the operand is a float. */
4a1805b1 5452 int op_modifier; /* Operand modifier. */
64a0c779
DN		 5453 int is_mem; /* 1 if operand is memory reference. */
5454 const reg_entry *reg; /* Last register reference found. */
5455 char *disp; /* Displacement string being built. */
5456 };
5457
5458static struct intel_parser_s intel_parser;
5459
5460/* Token structure for parsing intel syntax. */
5461struct intel_token
5462 {
5463 int code; /* Token code. */
5464 const reg_entry *reg; /* Register entry for register tokens. */
5465 char *str; /* String representation. */
5466 };
5467
5468static struct intel_token cur_token, prev_token;
5469
50705ef4
AM		 5470/* Token codes for the intel parser. Since T_SHORT is already used
5471 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 5472#define T_NIL -1
5473#define T_CONST 1
5474#define T_REG 2
5475#define T_BYTE 3
5476#define T_WORD 4
5477#define T_DWORD 5
5478#define T_QWORD 6
5479#define T_XWORD 7
50705ef4 5480#undef T_SHORT
64a0c779
DN		 5481#define T_SHORT 8
5482#define T_OFFSET 9
5483#define T_PTR 10
5484#define T_ID 11
5485
5486/* Prototypes for intel parser functions. */
5487static int intel_match_token PARAMS ((int code));
cce0cbdc
DN		 5488static void intel_get_token PARAMS ((void));
5489static void intel_putback_token PARAMS ((void));
5490static int intel_expr PARAMS ((void));
5491static int intel_e05 PARAMS ((void));
5492static int intel_e05_1 PARAMS ((void));
5493static int intel_e06 PARAMS ((void));
5494static int intel_e06_1 PARAMS ((void));
5495static int intel_e09 PARAMS ((void));
5496static int intel_e09_1 PARAMS ((void));
5497static int intel_e10 PARAMS ((void));
5498static int intel_e10_1 PARAMS ((void));
5499static int intel_e11 PARAMS ((void));
64a0c779 5500
64a0c779
DN		 5501static int
5502i386_intel_operand (operand_string, got_a_float)
5503 char *operand_string;
5504 int got_a_float;
5505{
5506 int ret;
5507 char *p;
5508
5509 /* Initialize token holders. */
5510 cur_token.code = prev_token.code = T_NIL;
5511 cur_token.reg = prev_token.reg = NULL;
5512 cur_token.str = prev_token.str = NULL;
5513
5514 /* Initialize parser structure. */
e5cb08ac 5515 p = intel_parser.op_string = (char *) malloc (strlen (operand_string) + 1);
64a0c779
DN		 5516 if (p == NULL)
5517 abort ();
5518 strcpy (intel_parser.op_string, operand_string);
5519 intel_parser.got_a_float = got_a_float;
5520 intel_parser.op_modifier = -1;
5521 intel_parser.is_mem = 0;
5522 intel_parser.reg = NULL;
e5cb08ac 5523 intel_parser.disp = (char *) malloc (strlen (operand_string) + 1);
64a0c779
DN		 5524 if (intel_parser.disp == NULL)
5525 abort ();
5526 intel_parser.disp[0] = '\0';
5527
5528 /* Read the first token and start the parser. */
5529 intel_get_token ();
5530 ret = intel_expr ();
5531
5532 if (ret)
5533 {
5534 /* If we found a memory reference, hand it over to i386_displacement
5535 to fill in the rest of the operand fields. */
5536 if (intel_parser.is_mem)
5537 {
5538 if ((i.mem_operands == 1
5539 && (current_templates->start->opcode_modifier & IsString) == 0)
5540 || i.mem_operands == 2)
5541 {
5542 as_bad (_("too many memory references for '%s'"),
5543 current_templates->start->name);
5544 ret = 0;
5545 }
5546 else
5547 {
5548 char *s = intel_parser.disp;
5549 i.mem_operands++;
5550
5551 /* Add the displacement expression. */
5552 if (*s != '\0')
5553 ret = i386_displacement (s, s + strlen (s))
5554 && i386_index_check (s);
5555 }
5556 }
5557
5558 /* Constant and OFFSET expressions are handled by i386_immediate. */
5559 else if (intel_parser.op_modifier == OFFSET_FLAT
5560 || intel_parser.reg == NULL)
5561 ret = i386_immediate (intel_parser.disp);
5562 }
5563
5564 free (p);
5565 free (intel_parser.disp);
5566
5567 return ret;
5568}
5569
64a0c779 5570/* expr SHORT e05
b77a7acd 5571 | e05 */
64a0c779
DN		 5572static int
5573intel_expr ()
5574{
5575 /* expr SHORT e05 */
5576 if (cur_token.code == T_SHORT)
5577 {
5578 intel_parser.op_modifier = SHORT;
5579 intel_match_token (T_SHORT);
5580
5581 return (intel_e05 ());
5582 }
5583
5584 /* expr e05 */
5585 else
5586 return intel_e05 ();
5587}
5588
64a0c779
DN		 5589/* e05 e06 e05'
5590
4a1805b1 5591 e05' addOp e06 e05'
64a0c779
DN		 5592 | Empty */
5593static int
5594intel_e05 ()
5595{
5596 return (intel_e06 () && intel_e05_1 ());
5597}
5598
5599static int
5600intel_e05_1 ()
5601{
5602 /* e05' addOp e06 e05' */
5603 if (cur_token.code == '+' || cur_token.code == '-')
5604 {
5605 strcat (intel_parser.disp, cur_token.str);
5606 intel_match_token (cur_token.code);
5607
5608 return (intel_e06 () && intel_e05_1 ());
5609 }
5610
5611 /* e05' Empty */
5612 else
5613 return 1;
4a1805b1 5614}
64a0c779
DN		 5615
5616/* e06 e09 e06'
5617
5618 e06' mulOp e09 e06'
b77a7acd 5619 | Empty */
64a0c779
DN		 5620static int
5621intel_e06 ()
5622{
5623 return (intel_e09 () && intel_e06_1 ());
5624}
5625
5626static int
5627intel_e06_1 ()
5628{
5629 /* e06' mulOp e09 e06' */
5630 if (cur_token.code == '*' || cur_token.code == '/')
5631 {
5632 strcat (intel_parser.disp, cur_token.str);
5633 intel_match_token (cur_token.code);
5634
5635 return (intel_e09 () && intel_e06_1 ());
5636 }
4a1805b1 5637
64a0c779 5638 /* e06' Empty */
4a1805b1 5639 else
64a0c779
DN		 5640 return 1;
5641}
5642
64a0c779 5643/* e09 OFFSET e10 e09'
b77a7acd 5644 | e10 e09'
64a0c779
DN		 5645
5646 e09' PTR e10 e09'
b77a7acd 5647 | : e10 e09'
64a0c779
DN		 5648 | Empty */
5649static int
5650intel_e09 ()
5651{
5652 /* e09 OFFSET e10 e09' */
5653 if (cur_token.code == T_OFFSET)
5654 {
5655 intel_parser.is_mem = 0;
5656 intel_parser.op_modifier = OFFSET_FLAT;
5657 intel_match_token (T_OFFSET);
5658
5659 return (intel_e10 () && intel_e09_1 ());
5660 }
5661
5662 /* e09 e10 e09' */
5663 else
5664 return (intel_e10 () && intel_e09_1 ());
5665}
5666
5667static int
5668intel_e09_1 ()
5669{
5670 /* e09' PTR e10 e09' */
5671 if (cur_token.code == T_PTR)
5672 {
5673 if (prev_token.code == T_BYTE)
5674 i.suffix = BYTE_MNEM_SUFFIX;
5675
5676 else if (prev_token.code == T_WORD)
5677 {
5678 if (intel_parser.got_a_float == 2) /* "fi..." */
5679 i.suffix = SHORT_MNEM_SUFFIX;
5680 else
5681 i.suffix = WORD_MNEM_SUFFIX;
5682 }
5683
5684 else if (prev_token.code == T_DWORD)
5685 {
5686 if (intel_parser.got_a_float == 1) /* "f..." */
5687 i.suffix = SHORT_MNEM_SUFFIX;
5688 else
5689 i.suffix = LONG_MNEM_SUFFIX;
5690 }
5691
5692 else if (prev_token.code == T_QWORD)
f16b83df
JH		 5693 {
5694 if (intel_parser.got_a_float == 1) /* "f..." */
5695 i.suffix = LONG_MNEM_SUFFIX;
5696 else
3e73aa7c 5697 i.suffix = QWORD_MNEM_SUFFIX;
f16b83df 5698 }
64a0c779
DN		 5699
5700 else if (prev_token.code == T_XWORD)
5701 i.suffix = LONG_DOUBLE_MNEM_SUFFIX;
5702
5703 else
5704 {
5705 as_bad (_("Unknown operand modifier `%s'\n"), prev_token.str);
5706 return 0;
5707 }
5708
5709 intel_match_token (T_PTR);
5710
5711 return (intel_e10 () && intel_e09_1 ());
5712 }
5713
5714 /* e09 : e10 e09' */
5715 else if (cur_token.code == ':')
5716 {
21d6c4af
DN		 5717 /* Mark as a memory operand only if it's not already known to be an
5718 offset expression. */
5719 if (intel_parser.op_modifier != OFFSET_FLAT)
5720 intel_parser.is_mem = 1;
64a0c779
DN		 5721
5722 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5723 }
5724
5725 /* e09' Empty */
5726 else
5727 return 1;
5728}
5729
5730/* e10 e11 e10'
5731
5732 e10' [ expr ] e10'
b77a7acd 5733 | Empty */
64a0c779
DN		 5734static int
5735intel_e10 ()
5736{
5737 return (intel_e11 () && intel_e10_1 ());
5738}
5739
5740static int
5741intel_e10_1 ()
5742{
5743 /* e10' [ expr ] e10' */
5744 if (cur_token.code == '[')
5745 {
5746 intel_match_token ('[');
21d6c4af
DN		 5747
5748 /* Mark as a memory operand only if it's not already known to be an
5749 offset expression. If it's an offset expression, we need to keep
5750 the brace in. */
5751 if (intel_parser.op_modifier != OFFSET_FLAT)
5752 intel_parser.is_mem = 1;
5753 else
5754 strcat (intel_parser.disp, "[");
4a1805b1 5755
64a0c779 5756 /* Add a '+' to the displacement string if necessary. */
21d6c4af
DN		 5757 if (*intel_parser.disp != '\0'
5758 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
64a0c779
DN		 5759 strcat (intel_parser.disp, "+");
5760
21d6c4af
DN		 5761 if (intel_expr () && intel_match_token (']'))
5762 {
5763 /* Preserve brackets when the operand is an offset expression. */
5764 if (intel_parser.op_modifier == OFFSET_FLAT)
5765 strcat (intel_parser.disp, "]");
5766
5767 return intel_e10_1 ();
5768 }
5769 else
5770 return 0;
64a0c779
DN		 5771 }
5772
5773 /* e10' Empty */
5774 else
5775 return 1;
5776}
5777
64a0c779 5778/* e11 ( expr )
b77a7acd 5779 | [ expr ]
64a0c779
DN		 5780 | BYTE
5781 | WORD
5782 | DWORD
5783 | QWORD
5784 | XWORD
4a1805b1 5785 | $
64a0c779
DN		 5786 | .
5787 | register
5788 | id
5789 | constant */
5790static int
5791intel_e11 ()
5792{
5793 /* e11 ( expr ) */
5794 if (cur_token.code == '(')
5795 {
5796 intel_match_token ('(');
5797 strcat (intel_parser.disp, "(");
5798
5799 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 5800 {
5801 strcat (intel_parser.disp, ")");
5802 return 1;
5803 }
64a0c779
DN		 5804 else
5805 return 0;
5806 }
5807
5808 /* e11 [ expr ] */
5809 else if (cur_token.code == '[')
5810 {
5811 intel_match_token ('[');
21d6c4af
DN		 5812
5813 /* Mark as a memory operand only if it's not already known to be an
5814 offset expression. If it's an offset expression, we need to keep
5815 the brace in. */
5816 if (intel_parser.op_modifier != OFFSET_FLAT)
5817 intel_parser.is_mem = 1;
5818 else
5819 strcat (intel_parser.disp, "[");
4a1805b1 5820
64a0c779
DN		 5821 /* Operands for jump/call inside brackets denote absolute addresses. */
5822 if (current_templates->start->opcode_modifier & Jump
5823 || current_templates->start->opcode_modifier & JumpDword
5824 || current_templates->start->opcode_modifier & JumpByte
5825 || current_templates->start->opcode_modifier & JumpInterSegment)
5826 i.types[this_operand] |= JumpAbsolute;
5827
5828 /* Add a '+' to the displacement string if necessary. */
21d6c4af
DN		 5829 if (*intel_parser.disp != '\0'
5830 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
64a0c779
DN		 5831 strcat (intel_parser.disp, "+");
5832
21d6c4af
DN		 5833 if (intel_expr () && intel_match_token (']'))
5834 {
5835 /* Preserve brackets when the operand is an offset expression. */
5836 if (intel_parser.op_modifier == OFFSET_FLAT)
5837 strcat (intel_parser.disp, "]");
5838
5839 return 1;
5840 }
5841 else
5842 return 0;
64a0c779
DN		 5843 }
5844
4a1805b1 5845 /* e11 BYTE
64a0c779
DN		 5846 | WORD
5847 | DWORD
5848 | QWORD
5849 | XWORD */
5850 else if (cur_token.code == T_BYTE
5851 || cur_token.code == T_WORD
5852 || cur_token.code == T_DWORD
5853 || cur_token.code == T_QWORD
5854 || cur_token.code == T_XWORD)
5855 {
5856 intel_match_token (cur_token.code);
5857
5858 return 1;
5859 }
5860
5861 /* e11 $
5862 | . */
5863 else if (cur_token.code == '$' || cur_token.code == '.')
5864 {
5865 strcat (intel_parser.disp, cur_token.str);
5866 intel_match_token (cur_token.code);
21d6c4af
DN		 5867
5868 /* Mark as a memory operand only if it's not already known to be an
5869 offset expression. */
5870 if (intel_parser.op_modifier != OFFSET_FLAT)
5871 intel_parser.is_mem = 1;
64a0c779
DN		 5872
5873 return 1;
5874 }
5875
5876 /* e11 register */
5877 else if (cur_token.code == T_REG)
5878 {
5879 const reg_entry *reg = intel_parser.reg = cur_token.reg;
5880
5881 intel_match_token (T_REG);
5882
5883 /* Check for segment change. */
5884 if (cur_token.code == ':')
5885 {
5886 if (reg->reg_type & (SReg2 | SReg3))
5887 {
5888 switch (reg->reg_num)
5889 {
5890 case 0:
5891 i.seg[i.mem_operands] = &es;
5892 break;
5893 case 1:
5894 i.seg[i.mem_operands] = &cs;
5895 break;
5896 case 2:
5897 i.seg[i.mem_operands] = &ss;
5898 break;
5899 case 3:
5900 i.seg[i.mem_operands] = &ds;
5901 break;
5902 case 4:
5903 i.seg[i.mem_operands] = &fs;
5904 break;
5905 case 5:
5906 i.seg[i.mem_operands] = &gs;
5907 break;
5908 }
5909 }
5910 else
5911 {
5912 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
5913 return 0;
5914 }
5915 }
5916
5917 /* Not a segment register. Check for register scaling. */
5918 else if (cur_token.code == '*')
5919 {
5920 if (!intel_parser.is_mem)
5921 {
5922 as_bad (_("Register scaling only allowed in memory operands."));
5923 return 0;
5924 }
5925
4a1805b1 5926 /* What follows must be a valid scale. */
64a0c779
DN		 5927 if (intel_match_token ('*')
5928 && strchr ("01248", *cur_token.str))
5929 {
5930 i.index_reg = reg;
5931 i.types[this_operand] |= BaseIndex;
5932
5933 /* Set the scale after setting the register (otherwise,
5934 i386_scale will complain) */
5935 i386_scale (cur_token.str);
5936 intel_match_token (T_CONST);
5937 }
5938 else
5939 {
5940 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5941 cur_token.str);
5942 return 0;
5943 }
5944 }
5945
5946 /* No scaling. If this is a memory operand, the register is either a
5947 base register (first occurrence) or an index register (second
5948 occurrence). */
5949 else if (intel_parser.is_mem && !(reg->reg_type & (SReg2 | SReg3)))
5950 {
5951 if (i.base_reg && i.index_reg)
5952 {
5953 as_bad (_("Too many register references in memory operand.\n"));
5954 return 0;
5955 }
5956
5957 if (i.base_reg == NULL)
5958 i.base_reg = reg;
5959 else
5960 i.index_reg = reg;
5961
5962 i.types[this_operand] |= BaseIndex;
5963 }
5964
5965 /* Offset modifier. Add the register to the displacement string to be
5966 parsed as an immediate expression after we're done. */
5967 else if (intel_parser.op_modifier == OFFSET_FLAT)
5968 strcat (intel_parser.disp, reg->reg_name);
4a1805b1 5969
64a0c779
DN		 5970 /* It's neither base nor index nor offset. */
5971 else
5972 {
5973 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
5974 i.op[this_operand].regs = reg;
5975 i.reg_operands++;
5976 }
5977
5978 /* Since registers are not part of the displacement string (except
5979 when we're parsing offset operands), we may need to remove any
5980 preceding '+' from the displacement string. */
5981 if (*intel_parser.disp != '\0'
5982 && intel_parser.op_modifier != OFFSET_FLAT)
5983 {
5984 char *s = intel_parser.disp;
5985 s += strlen (s) - 1;
5986 if (*s == '+')
5987 *s = '\0';
5988 }
5989
5990 return 1;
5991 }
4a1805b1 5992
64a0c779
DN		 5993 /* e11 id */
5994 else if (cur_token.code == T_ID)
5995 {
5996 /* Add the identifier to the displacement string. */
5997 strcat (intel_parser.disp, cur_token.str);
5998 intel_match_token (T_ID);
5999
6000 /* The identifier represents a memory reference only if it's not
6001 preceded by an offset modifier. */
21d6c4af 6002 if (intel_parser.op_modifier != OFFSET_FLAT)
64a0c779
DN		 6003 intel_parser.is_mem = 1;
6004
6005 return 1;
6006 }
6007
6008 /* e11 constant */
6009 else if (cur_token.code == T_CONST
e5cb08ac 6010 || cur_token.code == '-'
64a0c779
DN		 6011 || cur_token.code == '+')
6012 {
6013 char *save_str;
6014
6015 /* Allow constants that start with `+' or `-'. */
6016 if (cur_token.code == '-' || cur_token.code == '+')
6017 {
6018 strcat (intel_parser.disp, cur_token.str);
6019 intel_match_token (cur_token.code);
6020 if (cur_token.code != T_CONST)
6021 {
6022 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
6023 cur_token.str);
6024 return 0;
6025 }
6026 }
6027
e5cb08ac 6028 save_str = (char *) malloc (strlen (cur_token.str) + 1);
64a0c779 6029 if (save_str == NULL)
bc805888 6030 abort ();
64a0c779
DN		 6031 strcpy (save_str, cur_token.str);
6032
6033 /* Get the next token to check for register scaling. */
6034 intel_match_token (cur_token.code);
6035
6036 /* Check if this constant is a scaling factor for an index register. */
6037 if (cur_token.code == '*')
6038 {
6039 if (intel_match_token ('*') && cur_token.code == T_REG)
6040 {
6041 if (!intel_parser.is_mem)
6042 {
6043 as_bad (_("Register scaling only allowed in memory operands."));
6044 return 0;
6045 }
6046
4a1805b1 6047 /* The constant is followed by `* reg', so it must be
64a0c779
DN		 6048 a valid scale. */
6049 if (strchr ("01248", *save_str))
6050 {
6051 i.index_reg = cur_token.reg;
6052 i.types[this_operand] |= BaseIndex;
6053
6054 /* Set the scale after setting the register (otherwise,
6055 i386_scale will complain) */
6056 i386_scale (save_str);
6057 intel_match_token (T_REG);
6058
6059 /* Since registers are not part of the displacement
6060 string, we may need to remove any preceding '+' from
6061 the displacement string. */
6062 if (*intel_parser.disp != '\0')
6063 {
6064 char *s = intel_parser.disp;
6065 s += strlen (s) - 1;
6066 if (*s == '+')
6067 *s = '\0';
6068 }
6069
6070 free (save_str);
6071
6072 return 1;
6073 }
6074 else
6075 return 0;
6076 }
6077
6078 /* The constant was not used for register scaling. Since we have
6079 already consumed the token following `*' we now need to put it
6080 back in the stream. */
6081 else
6082 intel_putback_token ();
6083 }
6084
6085 /* Add the constant to the displacement string. */
6086 strcat (intel_parser.disp, save_str);
6087 free (save_str);
6088
6089 return 1;
6090 }
6091
64a0c779
DN		 6092 as_bad (_("Unrecognized token '%s'"), cur_token.str);
6093 return 0;
6094}
6095
64a0c779
DN		 6096/* Match the given token against cur_token. If they match, read the next
6097 token from the operand string. */
6098static int
6099intel_match_token (code)
e5cb08ac 6100 int code;
64a0c779
DN		 6101{
6102 if (cur_token.code == code)
6103 {
6104 intel_get_token ();
6105 return 1;
6106 }
6107 else
6108 {
6109 as_bad (_("Unexpected token `%s'\n"), cur_token.str);
6110 return 0;
6111 }
6112}
6113
64a0c779
DN		 6114/* Read a new token from intel_parser.op_string and store it in cur_token. */
6115static void
6116intel_get_token ()
6117{
6118 char *end_op;
6119 const reg_entry *reg;
6120 struct intel_token new_token;
6121
6122 new_token.code = T_NIL;
6123 new_token.reg = NULL;
6124 new_token.str = NULL;
6125
4a1805b1 6126 /* Free the memory allocated to the previous token and move
64a0c779
DN		 6127 cur_token to prev_token. */
6128 if (prev_token.str)
6129 free (prev_token.str);
6130
6131 prev_token = cur_token;
6132
6133 /* Skip whitespace. */
6134 while (is_space_char (*intel_parser.op_string))
6135 intel_parser.op_string++;
6136
6137 /* Return an empty token if we find nothing else on the line. */
6138 if (*intel_parser.op_string == '\0')
6139 {
6140 cur_token = new_token;
6141 return;
6142 }
6143
6144 /* The new token cannot be larger than the remainder of the operand
6145 string. */
e5cb08ac 6146 new_token.str = (char *) malloc (strlen (intel_parser.op_string) + 1);
64a0c779 6147 if (new_token.str == NULL)
bc805888 6148 abort ();
64a0c779
DN		 6149 new_token.str[0] = '\0';
6150
6151 if (strchr ("0123456789", *intel_parser.op_string))
6152 {
6153 char *p = new_token.str;
6154 char *q = intel_parser.op_string;
6155 new_token.code = T_CONST;
6156
6157 /* Allow any kind of identifier char to encompass floating point and
6158 hexadecimal numbers. */
6159 while (is_identifier_char (*q))
6160 *p++ = *q++;
6161 *p = '\0';
6162
6163 /* Recognize special symbol names [0-9][bf]. */
6164 if (strlen (intel_parser.op_string) == 2
4a1805b1 6165 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 6166 || intel_parser.op_string[1] == 'f'))
6167 new_token.code = T_ID;
6168 }
6169
6170 else if (strchr ("+-/*:[]()", *intel_parser.op_string))
6171 {
6172 new_token.code = *intel_parser.op_string;
6173 new_token.str[0] = *intel_parser.op_string;
6174 new_token.str[1] = '\0';
6175 }
6176
6177 else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg)
6178 && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL))
6179 {
6180 new_token.code = T_REG;
6181 new_token.reg = reg;
6182
6183 if (*intel_parser.op_string == REGISTER_PREFIX)
6184 {
6185 new_token.str[0] = REGISTER_PREFIX;
6186 new_token.str[1] = '\0';
6187 }
6188
6189 strcat (new_token.str, reg->reg_name);
6190 }
6191
6192 else if (is_identifier_char (*intel_parser.op_string))
6193 {
6194 char *p = new_token.str;
6195 char *q = intel_parser.op_string;
6196
6197 /* A '.' or '$' followed by an identifier char is an identifier.
6198 Otherwise, it's operator '.' followed by an expression. */
6199 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
6200 {
6201 new_token.code = *q;
6202 new_token.str[0] = *q;
6203 new_token.str[1] = '\0';
6204 }
6205 else
6206 {
6207 while (is_identifier_char (*q) || *q == '@')
6208 *p++ = *q++;
6209 *p = '\0';
6210
6211 if (strcasecmp (new_token.str, "BYTE") == 0)
6212 new_token.code = T_BYTE;
6213
6214 else if (strcasecmp (new_token.str, "WORD") == 0)
6215 new_token.code = T_WORD;
6216
6217 else if (strcasecmp (new_token.str, "DWORD") == 0)
6218 new_token.code = T_DWORD;
6219
6220 else if (strcasecmp (new_token.str, "QWORD") == 0)
6221 new_token.code = T_QWORD;
6222
6223 else if (strcasecmp (new_token.str, "XWORD") == 0)
6224 new_token.code = T_XWORD;
6225
6226 else if (strcasecmp (new_token.str, "PTR") == 0)
6227 new_token.code = T_PTR;
6228
6229 else if (strcasecmp (new_token.str, "SHORT") == 0)
6230 new_token.code = T_SHORT;
6231
6232 else if (strcasecmp (new_token.str, "OFFSET") == 0)
6233 {
6234 new_token.code = T_OFFSET;
6235
6236 /* ??? This is not mentioned in the MASM grammar but gcc
6237 makes use of it with -mintel-syntax. OFFSET may be
6238 followed by FLAT: */
6239 if (strncasecmp (q, " FLAT:", 6) == 0)
6240 strcat (new_token.str, " FLAT:");
6241 }
6242
6243 /* ??? This is not mentioned in the MASM grammar. */
6244 else if (strcasecmp (new_token.str, "FLAT") == 0)
6245 new_token.code = T_OFFSET;
6246
6247 else
6248 new_token.code = T_ID;
6249 }
6250 }
6251
6252 else
6253 as_bad (_("Unrecognized token `%s'\n"), intel_parser.op_string);
6254
6255 intel_parser.op_string += strlen (new_token.str);
6256 cur_token = new_token;
6257}
6258
64a0c779
DN		 6259/* Put cur_token back into the token stream and make cur_token point to
6260 prev_token. */
6261static void
6262intel_putback_token ()
6263{
6264 intel_parser.op_string -= strlen (cur_token.str);
6265 free (cur_token.str);
6266 cur_token = prev_token;
4a1805b1 6267
64a0c779
DN		 6268 /* Forget prev_token. */
6269 prev_token.code = T_NIL;
6270 prev_token.reg = NULL;
6271 prev_token.str = NULL;
6272}
GDB Binutils - Deliverables
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