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x86: fold VFPCLASSP{D,S} templates
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
219d1afa 2 Copyright (C) 1989-2018 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d 68#define LOCK_PREFIX 5
4e9ac44a
L		 69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
6305a203
L		 84/* Intel Syntax. Use a non-ascii letter since since it never appears
85 in instructions. */
86#define LONG_DOUBLE_MNEM_SUFFIX '\1'
87
88#define END_OF_INSN '\0'
89
90/*
91 'templates' is for grouping together 'template' structures for opcodes
92 of the same name. This is only used for storing the insns in the grand
93 ole hash table of insns.
94 The templates themselves start at START and range up to (but not including)
95 END.
96 */
97typedef struct
98{
d3ce72d0
NC		 99 const insn_template *start;
100 const insn_template *end;
6305a203
L		 101}
102templates;
103
104/* 386 operand encoding bytes: see 386 book for details of this. */
105typedef struct
106{
107 unsigned int regmem; /* codes register or memory operand */
108 unsigned int reg; /* codes register operand (or extended opcode) */
109 unsigned int mode; /* how to interpret regmem & reg */
110}
111modrm_byte;
112
113/* x86-64 extension prefix. */
114typedef int rex_byte;
115
6305a203
L		 116/* 386 opcode byte to code indirect addressing. */
117typedef struct
118{
119 unsigned base;
120 unsigned index;
121 unsigned scale;
122}
123sib_byte;
124
6305a203
L		 125/* x86 arch names, types and features */
126typedef struct
127{
128 const char *name; /* arch name */
8a2c8fef 129 unsigned int len; /* arch string length */
6305a203
L		 130 enum processor_type type; /* arch type */
131 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 132 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 133}
134arch_entry;
135
293f5f65
L		 136/* Used to turn off indicated flags. */
137typedef struct
138{
139 const char *name; /* arch name */
140 unsigned int len; /* arch string length */
141 i386_cpu_flags flags; /* cpu feature flags */
142}
143noarch_entry;
144
78f12dd3 145static void update_code_flag (int, int);
e3bb37b5
L		 146static void set_code_flag (int);
147static void set_16bit_gcc_code_flag (int);
148static void set_intel_syntax (int);
1efbbeb4 149static void set_intel_mnemonic (int);
db51cc60 150static void set_allow_index_reg (int);
7bab8ab5 151static void set_check (int);
e3bb37b5 152static void set_cpu_arch (int);
6482c264 153#ifdef TE_PE
e3bb37b5 154static void pe_directive_secrel (int);
6482c264 155#endif
e3bb37b5
L		 156static void signed_cons (int);
157static char *output_invalid (int c);
ee86248c
JB		 158static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
159 const char *);
160static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
161 const char *);
a7619375 162static int i386_att_operand (char *);
e3bb37b5 163static int i386_intel_operand (char *, int);
ee86248c
JB		 164static int i386_intel_simplify (expressionS *);
165static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 166static const reg_entry *parse_register (char *, char **);
167static char *parse_insn (char *, char *);
168static char *parse_operands (char *, const char *);
169static void swap_operands (void);
4d456e3d 170static void swap_2_operands (int, int);
e3bb37b5
L		 171static void optimize_imm (void);
172static void optimize_disp (void);
83b16ac6 173static const insn_template *match_template (char);
e3bb37b5
L		 174static int check_string (void);
175static int process_suffix (void);
176static int check_byte_reg (void);
177static int check_long_reg (void);
178static int check_qword_reg (void);
179static int check_word_reg (void);
180static int finalize_imm (void);
181static int process_operands (void);
182static const seg_entry *build_modrm_byte (void);
183static void output_insn (void);
184static void output_imm (fragS *, offsetT);
185static void output_disp (fragS *, offsetT);
29b0f896 186#ifndef I386COFF
e3bb37b5 187static void s_bss (int);
252b5132 188#endif
17d4e2a2
L		 189#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
190static void handle_large_common (int small ATTRIBUTE_UNUSED);
191#endif
252b5132 192
a847613f 193static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 194
43234a1e
L		 195/* This struct describes rounding control and SAE in the instruction. */
196struct RC_Operation
197{
198 enum rc_type
199 {
200 rne = 0,
201 rd,
202 ru,
203 rz,
204 saeonly
205 } type;
206 int operand;
207};
208
209static struct RC_Operation rc_op;
210
211/* The struct describes masking, applied to OPERAND in the instruction.
212 MASK is a pointer to the corresponding mask register. ZEROING tells
213 whether merging or zeroing mask is used. */
214struct Mask_Operation
215{
216 const reg_entry *mask;
217 unsigned int zeroing;
218 /* The operand where this operation is associated. */
219 int operand;
220};
221
222static struct Mask_Operation mask_op;
223
224/* The struct describes broadcasting, applied to OPERAND. FACTOR is
225 broadcast factor. */
226struct Broadcast_Operation
227{
8e6e0792 228 /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */
43234a1e
L		 229 int type;
230
231 /* Index of broadcasted operand. */
232 int operand;
233};
234
235static struct Broadcast_Operation broadcast_op;
236
c0f3af97
L		 237/* VEX prefix. */
238typedef struct
239{
43234a1e
L		 240 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
241 unsigned char bytes[4];
c0f3af97
L		 242 unsigned int length;
243 /* Destination or source register specifier. */
244 const reg_entry *register_specifier;
245} vex_prefix;
246
252b5132 247/* 'md_assemble ()' gathers together information and puts it into a
47926f60 248 i386_insn. */
252b5132 249
520dc8e8
AM		 250union i386_op
251 {
252 expressionS *disps;
253 expressionS *imms;
254 const reg_entry *regs;
255 };
256
a65babc9
L		 257enum i386_error
258 {
86e026a4 259 operand_size_mismatch,
a65babc9
L		 260 operand_type_mismatch,
261 register_type_mismatch,
262 number_of_operands_mismatch,
263 invalid_instruction_suffix,
264 bad_imm4,
a65babc9
L		 265 unsupported_with_intel_mnemonic,
266 unsupported_syntax,
6c30d220
L		 267 unsupported,
268 invalid_vsib_address,
7bab8ab5 269 invalid_vector_register_set,
43234a1e
L		 270 unsupported_vector_index_register,
271 unsupported_broadcast,
272 broadcast_not_on_src_operand,
273 broadcast_needed,
274 unsupported_masking,
275 mask_not_on_destination,
276 no_default_mask,
277 unsupported_rc_sae,
278 rc_sae_operand_not_last_imm,
279 invalid_register_operand,
a65babc9
L		 280 };
281
252b5132
RH		 282struct _i386_insn
283 {
47926f60 284 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 285 insn_template tm;
252b5132 286
7d5e4556
L		 287 /* SUFFIX holds the instruction size suffix for byte, word, dword
288 or qword, if given. */
252b5132
RH		 289 char suffix;
290
47926f60 291 /* OPERANDS gives the number of given operands. */
252b5132
RH		 292 unsigned int operands;
293
294 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
295 of given register, displacement, memory operands and immediate
47926f60 296 operands. */
252b5132
RH		 297 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
298
299 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 300 use OP[i] for the corresponding operand. */
40fb9820 301 i386_operand_type types[MAX_OPERANDS];
252b5132 302
520dc8e8
AM		 303 /* Displacement expression, immediate expression, or register for each
304 operand. */
305 union i386_op op[MAX_OPERANDS];
252b5132 306
3e73aa7c
JH		 307 /* Flags for operands. */
308 unsigned int flags[MAX_OPERANDS];
309#define Operand_PCrel 1
310
252b5132 311 /* Relocation type for operand */
f86103b7 312 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 313
252b5132
RH		 314 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
315 the base index byte below. */
316 const reg_entry *base_reg;
317 const reg_entry *index_reg;
318 unsigned int log2_scale_factor;
319
320 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 321 explicit segment overrides are given. */
ce8a8b2f 322 const seg_entry *seg[2];
252b5132 323
8325cc63
JB		 324 /* Copied first memory operand string, for re-checking. */
325 char *memop1_string;
326
252b5132
RH		 327 /* PREFIX holds all the given prefix opcodes (usually null).
328 PREFIXES is the number of prefix opcodes. */
329 unsigned int prefixes;
330 unsigned char prefix[MAX_PREFIXES];
331
332 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 333 addressing modes of this insn are encoded. */
252b5132 334 modrm_byte rm;
3e73aa7c 335 rex_byte rex;
43234a1e 336 rex_byte vrex;
252b5132 337 sib_byte sib;
c0f3af97 338 vex_prefix vex;
b6169b20 339
43234a1e
L		 340 /* Masking attributes. */
341 struct Mask_Operation *mask;
342
343 /* Rounding control and SAE attributes. */
344 struct RC_Operation *rounding;
345
346 /* Broadcasting attributes. */
347 struct Broadcast_Operation *broadcast;
348
349 /* Compressed disp8*N attribute. */
350 unsigned int memshift;
351
86fa6981
L		 352 /* Prefer load or store in encoding. */
353 enum
354 {
355 dir_encoding_default = 0,
356 dir_encoding_load,
357 dir_encoding_store
358 } dir_encoding;
891edac4 359
a501d77e
L		 360 /* Prefer 8bit or 32bit displacement in encoding. */
361 enum
362 {
363 disp_encoding_default = 0,
364 disp_encoding_8bit,
365 disp_encoding_32bit
366 } disp_encoding;
f8a5c266 367
6b6b6807
L		 368 /* Prefer the REX byte in encoding. */
369 bfd_boolean rex_encoding;
370
b6f8c7c4
L		 371 /* Disable instruction size optimization. */
372 bfd_boolean no_optimize;
373
86fa6981
L		 374 /* How to encode vector instructions. */
375 enum
376 {
377 vex_encoding_default = 0,
378 vex_encoding_vex2,
379 vex_encoding_vex3,
380 vex_encoding_evex
381 } vec_encoding;
382
d5de92cf
L		 383 /* REP prefix. */
384 const char *rep_prefix;
385
165de32a
L		 386 /* HLE prefix. */
387 const char *hle_prefix;
42164a71 388
7e8b059b
L		 389 /* Have BND prefix. */
390 const char *bnd_prefix;
391
04ef582a
L		 392 /* Have NOTRACK prefix. */
393 const char *notrack_prefix;
394
891edac4 395 /* Error message. */
a65babc9 396 enum i386_error error;
252b5132
RH		 397 };
398
399typedef struct _i386_insn i386_insn;
400
43234a1e
L		 401/* Link RC type with corresponding string, that'll be looked for in
402 asm. */
403struct RC_name
404{
405 enum rc_type type;
406 const char *name;
407 unsigned int len;
408};
409
410static const struct RC_name RC_NamesTable[] =
411{
412 { rne, STRING_COMMA_LEN ("rn-sae") },
413 { rd, STRING_COMMA_LEN ("rd-sae") },
414 { ru, STRING_COMMA_LEN ("ru-sae") },
415 { rz, STRING_COMMA_LEN ("rz-sae") },
416 { saeonly, STRING_COMMA_LEN ("sae") },
417};
418
252b5132
RH		 419/* List of chars besides those in app.c:symbol_chars that can start an
420 operand. Used to prevent the scrubber eating vital white-space. */
86fa6981 421const char extra_symbol_chars[] = "*%-([{}"
252b5132 422#ifdef LEX_AT
32137342
NC		 423 "@"
424#endif
425#ifdef LEX_QM
426 "?"
252b5132 427#endif
32137342 428 ;
252b5132 429
29b0f896
AM		 430#if (defined (TE_I386AIX) \
431 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 432 && !defined (TE_GNU) \
29b0f896 433 && !defined (TE_LINUX) \
8d63c93e 434 && !defined (TE_NACL) \
29b0f896 435 && !defined (TE_FreeBSD) \
5b806d27 436 && !defined (TE_DragonFly) \
29b0f896 437 && !defined (TE_NetBSD)))
252b5132 438/* This array holds the chars that always start a comment. If the
b3b91714
AM		 439 pre-processor is disabled, these aren't very useful. The option
440 --divide will remove '/' from this list. */
441const char *i386_comment_chars = "#/";
442#define SVR4_COMMENT_CHARS 1
252b5132 443#define PREFIX_SEPARATOR '\\'
252b5132 444
b3b91714
AM		 445#else
446const char *i386_comment_chars = "#";
447#define PREFIX_SEPARATOR '/'
448#endif
449
252b5132
RH		 450/* This array holds the chars that only start a comment at the beginning of
451 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 452 .line and .file directives will appear in the pre-processed output.
453 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 454 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 455 #NO_APP at the beginning of its output.
456 Also note that comments started like this one will always work if
252b5132 457 '/' isn't otherwise defined. */
b3b91714 458const char line_comment_chars[] = "#/";
252b5132 459
63a0b638 460const char line_separator_chars[] = ";";
252b5132 461
ce8a8b2f
AM		 462/* Chars that can be used to separate mant from exp in floating point
463 nums. */
252b5132
RH		 464const char EXP_CHARS[] = "eE";
465
ce8a8b2f
AM		 466/* Chars that mean this number is a floating point constant
467 As in 0f12.456
468 or 0d1.2345e12. */
252b5132
RH		 469const char FLT_CHARS[] = "fFdDxX";
470
ce8a8b2f 471/* Tables for lexical analysis. */
252b5132
RH		 472static char mnemonic_chars[256];
473static char register_chars[256];
474static char operand_chars[256];
475static char identifier_chars[256];
476static char digit_chars[256];
477
ce8a8b2f 478/* Lexical macros. */
252b5132
RH		 479#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
480#define is_operand_char(x) (operand_chars[(unsigned char) x])
481#define is_register_char(x) (register_chars[(unsigned char) x])
482#define is_space_char(x) ((x) == ' ')
483#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
484#define is_digit_char(x) (digit_chars[(unsigned char) x])
485
0234cb7c 486/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 487static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
488
489/* md_assemble() always leaves the strings it's passed unaltered. To
490 effect this we maintain a stack of saved characters that we've smashed
491 with '\0's (indicating end of strings for various sub-fields of the
47926f60 492 assembler instruction). */
252b5132 493static char save_stack[32];
ce8a8b2f 494static char *save_stack_p;
252b5132
RH		 495#define END_STRING_AND_SAVE(s) \
496 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
497#define RESTORE_END_STRING(s) \
498 do { *(s) = *--save_stack_p; } while (0)
499
47926f60 500/* The instruction we're assembling. */
252b5132
RH		 501static i386_insn i;
502
503/* Possible templates for current insn. */
504static const templates *current_templates;
505
31b2323c
L		 506/* Per instruction expressionS buffers: max displacements & immediates. */
507static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
508static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 509
47926f60 510/* Current operand we are working on. */
ee86248c 511static int this_operand = -1;
252b5132 512
3e73aa7c
JH		 513/* We support four different modes. FLAG_CODE variable is used to distinguish
514 these. */
515
516enum flag_code {
517 CODE_32BIT,
518 CODE_16BIT,
519 CODE_64BIT };
520
521static enum flag_code flag_code;
4fa24527 522static unsigned int object_64bit;
862be3fb 523static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 524static int use_rela_relocations = 0;
525
7af8ed2d
NC		 526#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
527 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
528 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
529
351f65ca
L		 530/* The ELF ABI to use. */
531enum x86_elf_abi
532{
533 I386_ABI,
7f56bc95
L		 534 X86_64_ABI,
535 X86_64_X32_ABI
351f65ca
L		 536};
537
538static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 539#endif
351f65ca 540
167ad85b
TG		 541#if defined (TE_PE) || defined (TE_PEP)
542/* Use big object file format. */
543static int use_big_obj = 0;
544#endif
545
8dcea932
L		 546#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547/* 1 if generating code for a shared library. */
548static int shared = 0;
549#endif
550
47926f60
KH		 551/* 1 for intel syntax,
552 0 if att syntax. */
553static int intel_syntax = 0;
252b5132 554
e89c5eaa
L		 555/* 1 for Intel64 ISA,
556 0 if AMD64 ISA. */
557static int intel64;
558
1efbbeb4
L		 559/* 1 for intel mnemonic,
560 0 if att mnemonic. */
561static int intel_mnemonic = !SYSV386_COMPAT;
562
a60de03c
JB		 563/* 1 if pseudo registers are permitted. */
564static int allow_pseudo_reg = 0;
565
47926f60
KH		 566/* 1 if register prefix % not required. */
567static int allow_naked_reg = 0;
252b5132 568
33eaf5de 569/* 1 if the assembler should add BND prefix for all control-transferring
7e8b059b
L		 570 instructions supporting it, even if this prefix wasn't specified
571 explicitly. */
572static int add_bnd_prefix = 0;
573
ba104c83 574/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 575static int allow_index_reg = 0;
576
d022bddd
IT		 577/* 1 if the assembler should ignore LOCK prefix, even if it was
578 specified explicitly. */
579static int omit_lock_prefix = 0;
580
e4e00185
AS		 581/* 1 if the assembler should encode lfence, mfence, and sfence as
582 "lock addl $0, (%{re}sp)". */
583static int avoid_fence = 0;
584
0cb4071e
L		 585/* 1 if the assembler should generate relax relocations. */
586
587static int generate_relax_relocations
588 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
589
7bab8ab5 590static enum check_kind
daf50ae7 591 {
7bab8ab5
JB		 592 check_none = 0,
593 check_warning,
594 check_error
daf50ae7 595 }
7bab8ab5 596sse_check, operand_check = check_warning;
daf50ae7 597
b6f8c7c4
L		 598/* Optimization:
599 1. Clear the REX_W bit with register operand if possible.
600 2. Above plus use 128bit vector instruction to clear the full vector
601 register.
602 */
603static int optimize = 0;
604
605/* Optimization:
606 1. Clear the REX_W bit with register operand if possible.
607 2. Above plus use 128bit vector instruction to clear the full vector
608 register.
609 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
610 "testb $imm7,%r8".
611 */
612static int optimize_for_space = 0;
613
2ca3ace5
L		 614/* Register prefix used for error message. */
615static const char *register_prefix = "%";
616
47926f60
KH		 617/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
618 leave, push, and pop instructions so that gcc has the same stack
619 frame as in 32 bit mode. */
620static char stackop_size = '\0';
eecb386c 621
12b55ccc
L		 622/* Non-zero to optimize code alignment. */
623int optimize_align_code = 1;
624
47926f60
KH		 625/* Non-zero to quieten some warnings. */
626static int quiet_warnings = 0;
a38cf1db 627
47926f60
KH		 628/* CPU name. */
629static const char *cpu_arch_name = NULL;
6305a203 630static char *cpu_sub_arch_name = NULL;
a38cf1db 631
47926f60 632/* CPU feature flags. */
40fb9820
L		 633static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
634
ccc9c027
L		 635/* If we have selected a cpu we are generating instructions for. */
636static int cpu_arch_tune_set = 0;
637
9103f4f4 638/* Cpu we are generating instructions for. */
fbf3f584 639enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 640
641/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 642static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 643
ccc9c027 644/* CPU instruction set architecture used. */
fbf3f584 645enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 646
9103f4f4 647/* CPU feature flags of instruction set architecture used. */
fbf3f584 648i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 649
fddf5b5b
AM		 650/* If set, conditional jumps are not automatically promoted to handle
651 larger than a byte offset. */
652static unsigned int no_cond_jump_promotion = 0;
653
c0f3af97
L		 654/* Encode SSE instructions with VEX prefix. */
655static unsigned int sse2avx;
656
539f890d
L		 657/* Encode scalar AVX instructions with specific vector length. */
658static enum
659 {
660 vex128 = 0,
661 vex256
662 } avxscalar;
663
43234a1e
L		 664/* Encode scalar EVEX LIG instructions with specific vector length. */
665static enum
666 {
667 evexl128 = 0,
668 evexl256,
669 evexl512
670 } evexlig;
671
672/* Encode EVEX WIG instructions with specific evex.w. */
673static enum
674 {
675 evexw0 = 0,
676 evexw1
677 } evexwig;
678
d3d3c6db
IT		 679/* Value to encode in EVEX RC bits, for SAE-only instructions. */
680static enum rc_type evexrcig = rne;
681
29b0f896 682/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 683static symbolS *GOT_symbol;
29b0f896 684
a4447b93
RH		 685/* The dwarf2 return column, adjusted for 32 or 64 bit. */
686unsigned int x86_dwarf2_return_column;
687
688/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
689int x86_cie_data_alignment;
690
252b5132 691/* Interface to relax_segment.
fddf5b5b
AM		 692 There are 3 major relax states for 386 jump insns because the
693 different types of jumps add different sizes to frags when we're
694 figuring out what sort of jump to choose to reach a given label. */
252b5132 695
47926f60 696/* Types. */
93c2a809
AM		 697#define UNCOND_JUMP 0
698#define COND_JUMP 1
699#define COND_JUMP86 2
fddf5b5b 700
47926f60 701/* Sizes. */
252b5132
RH		 702#define CODE16 1
703#define SMALL 0
29b0f896 704#define SMALL16 (SMALL | CODE16)
252b5132 705#define BIG 2
29b0f896 706#define BIG16 (BIG | CODE16)
252b5132
RH		 707
708#ifndef INLINE
709#ifdef __GNUC__
710#define INLINE __inline__
711#else
712#define INLINE
713#endif
714#endif
715
fddf5b5b
AM		 716#define ENCODE_RELAX_STATE(type, size) \
717 ((relax_substateT) (((type) << 2) | (size)))
718#define TYPE_FROM_RELAX_STATE(s) \
719 ((s) >> 2)
720#define DISP_SIZE_FROM_RELAX_STATE(s) \
721 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 722
723/* This table is used by relax_frag to promote short jumps to long
724 ones where necessary. SMALL (short) jumps may be promoted to BIG
725 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
726 don't allow a short jump in a 32 bit code segment to be promoted to
727 a 16 bit offset jump because it's slower (requires data size
728 prefix), and doesn't work, unless the destination is in the bottom
729 64k of the code segment (The top 16 bits of eip are zeroed). */
730
731const relax_typeS md_relax_table[] =
732{
24eab124
AM		 733 /* The fields are:
734 1) most positive reach of this state,
735 2) most negative reach of this state,
93c2a809 736 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 737 4) which index into the table to try if we can't fit into this one. */
252b5132 738
fddf5b5b 739 /* UNCOND_JUMP states. */
93c2a809
AM		 740 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
741 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
742 /* dword jmp adds 4 bytes to frag:
743 0 extra opcode bytes, 4 displacement bytes. */
252b5132 744 {0, 0, 4, 0},
93c2a809
AM		 745 /* word jmp adds 2 byte2 to frag:
746 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 747 {0, 0, 2, 0},
748
93c2a809
AM		 749 /* COND_JUMP states. */
750 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
751 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
752 /* dword conditionals adds 5 bytes to frag:
753 1 extra opcode byte, 4 displacement bytes. */
754 {0, 0, 5, 0},
fddf5b5b 755 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 756 1 extra opcode byte, 2 displacement bytes. */
757 {0, 0, 3, 0},
758
759 /* COND_JUMP86 states. */
760 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
761 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
762 /* dword conditionals adds 5 bytes to frag:
763 1 extra opcode byte, 4 displacement bytes. */
764 {0, 0, 5, 0},
765 /* word conditionals add 4 bytes to frag:
766 1 displacement byte and a 3 byte long branch insn. */
767 {0, 0, 4, 0}
252b5132
RH		 768};
769
9103f4f4
L		 770static const arch_entry cpu_arch[] =
771{
89507696
JB		 772 /* Do not replace the first two entries - i386_target_format()
773 relies on them being there in this order. */
8a2c8fef 774 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
293f5f65 775 CPU_GENERIC32_FLAGS, 0 },
8a2c8fef 776 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
293f5f65 777 CPU_GENERIC64_FLAGS, 0 },
8a2c8fef 778 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
293f5f65 779 CPU_NONE_FLAGS, 0 },
8a2c8fef 780 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
293f5f65 781 CPU_I186_FLAGS, 0 },
8a2c8fef 782 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
293f5f65 783 CPU_I286_FLAGS, 0 },
8a2c8fef 784 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
293f5f65 785 CPU_I386_FLAGS, 0 },
8a2c8fef 786 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
293f5f65 787 CPU_I486_FLAGS, 0 },
8a2c8fef 788 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
293f5f65 789 CPU_I586_FLAGS, 0 },
8a2c8fef 790 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
293f5f65 791 CPU_I686_FLAGS, 0 },
8a2c8fef 792 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
293f5f65 793 CPU_I586_FLAGS, 0 },
8a2c8fef 794 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
293f5f65 795 CPU_PENTIUMPRO_FLAGS, 0 },
8a2c8fef 796 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
293f5f65 797 CPU_P2_FLAGS, 0 },
8a2c8fef 798 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
293f5f65 799 CPU_P3_FLAGS, 0 },
8a2c8fef 800 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
293f5f65 801 CPU_P4_FLAGS, 0 },
8a2c8fef 802 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
293f5f65 803 CPU_CORE_FLAGS, 0 },
8a2c8fef 804 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
293f5f65 805 CPU_NOCONA_FLAGS, 0 },
8a2c8fef 806 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
293f5f65 807 CPU_CORE_FLAGS, 1 },
8a2c8fef 808 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
293f5f65 809 CPU_CORE_FLAGS, 0 },
8a2c8fef 810 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
293f5f65 811 CPU_CORE2_FLAGS, 1 },
8a2c8fef 812 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
293f5f65 813 CPU_CORE2_FLAGS, 0 },
8a2c8fef 814 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
293f5f65 815 CPU_COREI7_FLAGS, 0 },
8a2c8fef 816 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
293f5f65 817 CPU_L1OM_FLAGS, 0 },
7a9068fe 818 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
293f5f65 819 CPU_K1OM_FLAGS, 0 },
81486035 820 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
293f5f65 821 CPU_IAMCU_FLAGS, 0 },
8a2c8fef 822 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
293f5f65 823 CPU_K6_FLAGS, 0 },
8a2c8fef 824 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
293f5f65 825 CPU_K6_2_FLAGS, 0 },
8a2c8fef 826 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
293f5f65 827 CPU_ATHLON_FLAGS, 0 },
8a2c8fef 828 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
293f5f65 829 CPU_K8_FLAGS, 1 },
8a2c8fef 830 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
293f5f65 831 CPU_K8_FLAGS, 0 },
8a2c8fef 832 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
293f5f65 833 CPU_K8_FLAGS, 0 },
8a2c8fef 834 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
293f5f65 835 CPU_AMDFAM10_FLAGS, 0 },
8aedb9fe 836 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
293f5f65 837 CPU_BDVER1_FLAGS, 0 },
8aedb9fe 838 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
293f5f65 839 CPU_BDVER2_FLAGS, 0 },
5e5c50d3 840 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
293f5f65 841 CPU_BDVER3_FLAGS, 0 },
c7b0bd56 842 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
293f5f65 843 CPU_BDVER4_FLAGS, 0 },
029f3522 844 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
293f5f65 845 CPU_ZNVER1_FLAGS, 0 },
a9660a6f
AP		 846 { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER,
847 CPU_ZNVER2_FLAGS, 0 },
7b458c12 848 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
293f5f65 849 CPU_BTVER1_FLAGS, 0 },
7b458c12 850 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
293f5f65 851 CPU_BTVER2_FLAGS, 0 },
8a2c8fef 852 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
293f5f65 853 CPU_8087_FLAGS, 0 },
8a2c8fef 854 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
293f5f65 855 CPU_287_FLAGS, 0 },
8a2c8fef 856 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
293f5f65 857 CPU_387_FLAGS, 0 },
1848e567
L		 858 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
859 CPU_687_FLAGS, 0 },
8a2c8fef 860 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
293f5f65 861 CPU_MMX_FLAGS, 0 },
8a2c8fef 862 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
293f5f65 863 CPU_SSE_FLAGS, 0 },
8a2c8fef 864 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
293f5f65 865 CPU_SSE2_FLAGS, 0 },
8a2c8fef 866 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
293f5f65 867 CPU_SSE3_FLAGS, 0 },
8a2c8fef 868 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
293f5f65 869 CPU_SSSE3_FLAGS, 0 },
8a2c8fef 870 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
293f5f65 871 CPU_SSE4_1_FLAGS, 0 },
8a2c8fef 872 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
293f5f65 873 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 874 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
293f5f65 875 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 876 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
293f5f65 877 CPU_AVX_FLAGS, 0 },
6c30d220 878 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
293f5f65 879 CPU_AVX2_FLAGS, 0 },
43234a1e 880 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
293f5f65 881 CPU_AVX512F_FLAGS, 0 },
43234a1e 882 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
293f5f65 883 CPU_AVX512CD_FLAGS, 0 },
43234a1e 884 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
293f5f65 885 CPU_AVX512ER_FLAGS, 0 },
43234a1e 886 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
293f5f65 887 CPU_AVX512PF_FLAGS, 0 },
1dfc6506 888 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
293f5f65 889 CPU_AVX512DQ_FLAGS, 0 },
1dfc6506 890 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
293f5f65 891 CPU_AVX512BW_FLAGS, 0 },
1dfc6506 892 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
293f5f65 893 CPU_AVX512VL_FLAGS, 0 },
8a2c8fef 894 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
293f5f65 895 CPU_VMX_FLAGS, 0 },
8729a6f6 896 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
293f5f65 897 CPU_VMFUNC_FLAGS, 0 },
8a2c8fef 898 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
293f5f65 899 CPU_SMX_FLAGS, 0 },
8a2c8fef 900 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
293f5f65 901 CPU_XSAVE_FLAGS, 0 },
c7b8aa3a 902 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
293f5f65 903 CPU_XSAVEOPT_FLAGS, 0 },
1dfc6506 904 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
293f5f65 905 CPU_XSAVEC_FLAGS, 0 },
1dfc6506 906 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
293f5f65 907 CPU_XSAVES_FLAGS, 0 },
8a2c8fef 908 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
293f5f65 909 CPU_AES_FLAGS, 0 },
8a2c8fef 910 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
293f5f65 911 CPU_PCLMUL_FLAGS, 0 },
8a2c8fef 912 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
293f5f65 913 CPU_PCLMUL_FLAGS, 1 },
c7b8aa3a 914 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
293f5f65 915 CPU_FSGSBASE_FLAGS, 0 },
c7b8aa3a 916 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
293f5f65 917 CPU_RDRND_FLAGS, 0 },
c7b8aa3a 918 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
293f5f65 919 CPU_F16C_FLAGS, 0 },
6c30d220 920 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
293f5f65 921 CPU_BMI2_FLAGS, 0 },
8a2c8fef 922 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
293f5f65 923 CPU_FMA_FLAGS, 0 },
8a2c8fef 924 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
293f5f65 925 CPU_FMA4_FLAGS, 0 },
8a2c8fef 926 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
293f5f65 927 CPU_XOP_FLAGS, 0 },
8a2c8fef 928 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
293f5f65 929 CPU_LWP_FLAGS, 0 },
8a2c8fef 930 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
293f5f65 931 CPU_MOVBE_FLAGS, 0 },
60aa667e 932 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
293f5f65 933 CPU_CX16_FLAGS, 0 },
8a2c8fef 934 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
293f5f65 935 CPU_EPT_FLAGS, 0 },
6c30d220 936 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
293f5f65 937 CPU_LZCNT_FLAGS, 0 },
42164a71 938 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
293f5f65 939 CPU_HLE_FLAGS, 0 },
42164a71 940 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
293f5f65 941 CPU_RTM_FLAGS, 0 },
6c30d220 942 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
293f5f65 943 CPU_INVPCID_FLAGS, 0 },
8a2c8fef 944 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
293f5f65 945 CPU_CLFLUSH_FLAGS, 0 },
22109423 946 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
293f5f65 947 CPU_NOP_FLAGS, 0 },
8a2c8fef 948 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
293f5f65 949 CPU_SYSCALL_FLAGS, 0 },
8a2c8fef 950 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
293f5f65 951 CPU_RDTSCP_FLAGS, 0 },
8a2c8fef 952 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
293f5f65 953 CPU_3DNOW_FLAGS, 0 },
8a2c8fef 954 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
293f5f65 955 CPU_3DNOWA_FLAGS, 0 },
8a2c8fef 956 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
293f5f65 957 CPU_PADLOCK_FLAGS, 0 },
8a2c8fef 958 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
293f5f65 959 CPU_SVME_FLAGS, 1 },
8a2c8fef 960 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
293f5f65 961 CPU_SVME_FLAGS, 0 },
8a2c8fef 962 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
293f5f65 963 CPU_SSE4A_FLAGS, 0 },
8a2c8fef 964 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
293f5f65 965 CPU_ABM_FLAGS, 0 },
87973e9f 966 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
293f5f65 967 CPU_BMI_FLAGS, 0 },
2a2a0f38 968 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
293f5f65 969 CPU_TBM_FLAGS, 0 },
e2e1fcde 970 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
293f5f65 971 CPU_ADX_FLAGS, 0 },
e2e1fcde 972 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
293f5f65 973 CPU_RDSEED_FLAGS, 0 },
e2e1fcde 974 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
293f5f65 975 CPU_PRFCHW_FLAGS, 0 },
5c111e37 976 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
293f5f65 977 CPU_SMAP_FLAGS, 0 },
7e8b059b 978 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
293f5f65 979 CPU_MPX_FLAGS, 0 },
a0046408 980 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
293f5f65 981 CPU_SHA_FLAGS, 0 },
963f3586 982 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
293f5f65 983 CPU_CLFLUSHOPT_FLAGS, 0 },
dcf893b5 984 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
293f5f65 985 CPU_PREFETCHWT1_FLAGS, 0 },
2cf200a4 986 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
293f5f65 987 CPU_SE1_FLAGS, 0 },
c5e7287a 988 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
293f5f65 989 CPU_CLWB_FLAGS, 0 },
2cc1b5aa 990 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
293f5f65 991 CPU_AVX512IFMA_FLAGS, 0 },
14f195c9 992 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
293f5f65 993 CPU_AVX512VBMI_FLAGS, 0 },
920d2ddc
IT		 994 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
995 CPU_AVX512_4FMAPS_FLAGS, 0 },
47acf0bd
IT		 996 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
997 CPU_AVX512_4VNNIW_FLAGS, 0 },
620214f7
IT		 998 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
999 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
53467f57
IT		 1000 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
1001 CPU_AVX512_VBMI2_FLAGS, 0 },
8cfcb765
IT		 1002 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
1003 CPU_AVX512_VNNI_FLAGS, 0 },
ee6872be
IT		 1004 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
1005 CPU_AVX512_BITALG_FLAGS, 0 },
029f3522 1006 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
293f5f65 1007 CPU_CLZERO_FLAGS, 0 },
9916071f 1008 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
293f5f65 1009 CPU_MWAITX_FLAGS, 0 },
8eab4136 1010 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
293f5f65 1011 CPU_OSPKE_FLAGS, 0 },
8bc52696 1012 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
293f5f65 1013 CPU_RDPID_FLAGS, 0 },
6b40c462
L		 1014 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
1015 CPU_PTWRITE_FLAGS, 0 },
d777820b
IT		 1016 { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN,
1017 CPU_IBT_FLAGS, 0 },
1018 { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN,
1019 CPU_SHSTK_FLAGS, 0 },
48521003
IT		 1020 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1021 CPU_GFNI_FLAGS, 0 },
8dcf1fad
IT		 1022 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1023 CPU_VAES_FLAGS, 0 },
ff1982d5
IT		 1024 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1025 CPU_VPCLMULQDQ_FLAGS, 0 },
3233d7d0
IT		 1026 { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN,
1027 CPU_WBNOINVD_FLAGS, 0 },
be3a8dca
IT		 1028 { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN,
1029 CPU_PCONFIG_FLAGS, 0 },
de89d0a3
IT		 1030 { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN,
1031 CPU_WAITPKG_FLAGS, 0 },
c48935d7
IT		 1032 { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN,
1033 CPU_CLDEMOTE_FLAGS, 0 },
c0a30a9f
L		 1034 { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN,
1035 CPU_MOVDIRI_FLAGS, 0 },
1036 { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN,
1037 CPU_MOVDIR64B_FLAGS, 0 },
293f5f65
L		 1038};
1039
1040static const noarch_entry cpu_noarch[] =
1041{
1042 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1848e567
L		 1043 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1044 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1045 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
293f5f65
L		 1046 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1047 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1848e567
L		 1048 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1049 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1050 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1051 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1052 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1053 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
293f5f65 1054 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1848e567 1055 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
144b71e2
L		 1056 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1057 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1058 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1059 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1060 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1061 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1062 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1063 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1064 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
920d2ddc 1065 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
47acf0bd 1066 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
620214f7 1067 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
53467f57 1068 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
8cfcb765 1069 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
ee6872be 1070 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
d777820b
IT		 1071 { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS },
1072 { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS },
c0a30a9f
L		 1073 { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS },
1074 { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS },
e413e4e9
AM		 1075};
1076
704209c0 1077#ifdef I386COFF
a6c24e68
NC		 1078/* Like s_lcomm_internal in gas/read.c but the alignment string
1079 is allowed to be optional. */
1080
1081static symbolS *
1082pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1083{
1084 addressT align = 0;
1085
1086 SKIP_WHITESPACE ();
1087
7ab9ffdd 1088 if (needs_align
a6c24e68
NC		 1089 && *input_line_pointer == ',')
1090 {
1091 align = parse_align (needs_align - 1);
7ab9ffdd 1092
a6c24e68
NC		 1093 if (align == (addressT) -1)
1094 return NULL;
1095 }
1096 else
1097 {
1098 if (size >= 8)
1099 align = 3;
1100 else if (size >= 4)
1101 align = 2;
1102 else if (size >= 2)
1103 align = 1;
1104 else
1105 align = 0;
1106 }
1107
1108 bss_alloc (symbolP, size, align);
1109 return symbolP;
1110}
1111
704209c0 1112static void
a6c24e68
NC		 1113pe_lcomm (int needs_align)
1114{
1115 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1116}
704209c0 1117#endif
a6c24e68 1118
29b0f896
AM		 1119const pseudo_typeS md_pseudo_table[] =
1120{
1121#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1122 {"align", s_align_bytes, 0},
1123#else
1124 {"align", s_align_ptwo, 0},
1125#endif
1126 {"arch", set_cpu_arch, 0},
1127#ifndef I386COFF
1128 {"bss", s_bss, 0},
a6c24e68
NC		 1129#else
1130 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1131#endif
1132 {"ffloat", float_cons, 'f'},
1133 {"dfloat", float_cons, 'd'},
1134 {"tfloat", float_cons, 'x'},
1135 {"value", cons, 2},
d182319b 1136 {"slong", signed_cons, 4},
29b0f896
AM		 1137 {"noopt", s_ignore, 0},
1138 {"optim", s_ignore, 0},
1139 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1140 {"code16", set_code_flag, CODE_16BIT},
1141 {"code32", set_code_flag, CODE_32BIT},
da5f19a2 1142#ifdef BFD64
29b0f896 1143 {"code64", set_code_flag, CODE_64BIT},
da5f19a2 1144#endif
29b0f896
AM		 1145 {"intel_syntax", set_intel_syntax, 1},
1146 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1147 {"intel_mnemonic", set_intel_mnemonic, 1},
1148 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1149 {"allow_index_reg", set_allow_index_reg, 1},
1150 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1151 {"sse_check", set_check, 0},
1152 {"operand_check", set_check, 1},
3b22753a
L		 1153#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1154 {"largecomm", handle_large_common, 0},
07a53e5c 1155#else
68d20676 1156 {"file", dwarf2_directive_file, 0},
07a53e5c
RH		 1157 {"loc", dwarf2_directive_loc, 0},
1158 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1159#endif
6482c264
NC		 1160#ifdef TE_PE
1161 {"secrel32", pe_directive_secrel, 0},
1162#endif
29b0f896
AM		 1163 {0, 0, 0}
1164};
1165
1166/* For interface with expression (). */
1167extern char *input_line_pointer;
1168
1169/* Hash table for instruction mnemonic lookup. */
1170static struct hash_control *op_hash;
1171
1172/* Hash table for register lookup. */
1173static struct hash_control *reg_hash;
1174\f
ce8a8b2f
AM		 1175 /* Various efficient no-op patterns for aligning code labels.
1176 Note: Don't try to assemble the instructions in the comments.
1177 0L and 0w are not legal. */
62a02d25
L		 1178static const unsigned char f32_1[] =
1179 {0x90}; /* nop */
1180static const unsigned char f32_2[] =
1181 {0x66,0x90}; /* xchg %ax,%ax */
1182static const unsigned char f32_3[] =
1183 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1184static const unsigned char f32_4[] =
1185 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
62a02d25
L		 1186static const unsigned char f32_6[] =
1187 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1188static const unsigned char f32_7[] =
1189 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
62a02d25 1190static const unsigned char f16_3[] =
3ae729d5 1191 {0x8d,0x74,0x00}; /* lea 0(%si),%si */
62a02d25 1192static const unsigned char f16_4[] =
3ae729d5
L		 1193 {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */
1194static const unsigned char jump_disp8[] =
1195 {0xeb}; /* jmp disp8 */
1196static const unsigned char jump32_disp32[] =
1197 {0xe9}; /* jmp disp32 */
1198static const unsigned char jump16_disp32[] =
1199 {0x66,0xe9}; /* jmp disp32 */
62a02d25
L		 1200/* 32-bit NOPs patterns. */
1201static const unsigned char *const f32_patt[] = {
3ae729d5 1202 f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7
62a02d25
L		 1203};
1204/* 16-bit NOPs patterns. */
1205static const unsigned char *const f16_patt[] = {
3ae729d5 1206 f32_1, f32_2, f16_3, f16_4
62a02d25
L		 1207};
1208/* nopl (%[re]ax) */
1209static const unsigned char alt_3[] =
1210 {0x0f,0x1f,0x00};
1211/* nopl 0(%[re]ax) */
1212static const unsigned char alt_4[] =
1213 {0x0f,0x1f,0x40,0x00};
1214/* nopl 0(%[re]ax,%[re]ax,1) */
1215static const unsigned char alt_5[] =
1216 {0x0f,0x1f,0x44,0x00,0x00};
1217/* nopw 0(%[re]ax,%[re]ax,1) */
1218static const unsigned char alt_6[] =
1219 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1220/* nopl 0L(%[re]ax) */
1221static const unsigned char alt_7[] =
1222 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1223/* nopl 0L(%[re]ax,%[re]ax,1) */
1224static const unsigned char alt_8[] =
1225 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1226/* nopw 0L(%[re]ax,%[re]ax,1) */
1227static const unsigned char alt_9[] =
1228 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1229/* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1230static const unsigned char alt_10[] =
1231 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
3ae729d5
L		 1232/* data16 nopw %cs:0L(%eax,%eax,1) */
1233static const unsigned char alt_11[] =
1234 {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
62a02d25
L		 1235/* 32-bit and 64-bit NOPs patterns. */
1236static const unsigned char *const alt_patt[] = {
1237 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
3ae729d5 1238 alt_9, alt_10, alt_11
62a02d25
L		 1239};
1240
1241/* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1242 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1243
1244static void
1245i386_output_nops (char *where, const unsigned char *const *patt,
1246 int count, int max_single_nop_size)
1247
1248{
3ae729d5
L		 1249 /* Place the longer NOP first. */
1250 int last;
1251 int offset;
1252 const unsigned char *nops = patt[max_single_nop_size - 1];
1253
1254 /* Use the smaller one if the requsted one isn't available. */
1255 if (nops == NULL)
62a02d25 1256 {
3ae729d5
L		 1257 max_single_nop_size--;
1258 nops = patt[max_single_nop_size - 1];
62a02d25
L		 1259 }
1260
3ae729d5
L		 1261 last = count % max_single_nop_size;
1262
1263 count -= last;
1264 for (offset = 0; offset < count; offset += max_single_nop_size)
1265 memcpy (where + offset, nops, max_single_nop_size);
1266
1267 if (last)
1268 {
1269 nops = patt[last - 1];
1270 if (nops == NULL)
1271 {
1272 /* Use the smaller one plus one-byte NOP if the needed one
1273 isn't available. */
1274 last--;
1275 nops = patt[last - 1];
1276 memcpy (where + offset, nops, last);
1277 where[offset + last] = *patt[0];
1278 }
1279 else
1280 memcpy (where + offset, nops, last);
1281 }
62a02d25
L		 1282}
1283
3ae729d5
L		 1284static INLINE int
1285fits_in_imm7 (offsetT num)
1286{
1287 return (num & 0x7f) == num;
1288}
1289
1290static INLINE int
1291fits_in_imm31 (offsetT num)
1292{
1293 return (num & 0x7fffffff) == num;
1294}
62a02d25
L		 1295
1296/* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1297 single NOP instruction LIMIT. */
1298
1299void
3ae729d5 1300i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit)
62a02d25 1301{
3ae729d5 1302 const unsigned char *const *patt = NULL;
62a02d25 1303 int max_single_nop_size;
3ae729d5
L		 1304 /* Maximum number of NOPs before switching to jump over NOPs. */
1305 int max_number_of_nops;
62a02d25 1306
3ae729d5 1307 switch (fragP->fr_type)
62a02d25 1308 {
3ae729d5
L		 1309 case rs_fill_nop:
1310 case rs_align_code:
1311 break;
1312 default:
62a02d25
L		 1313 return;
1314 }
1315
ccc9c027
L		 1316 /* We need to decide which NOP sequence to use for 32bit and
1317 64bit. When -mtune= is used:
4eed87de 1318
76bc74dc
L		 1319 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1320 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1321 2. For the rest, alt_patt will be used.
1322
1323 When -mtune= isn't used, alt_patt will be used if
22109423 1324 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1325 be used.
ccc9c027
L		 1326
1327 When -march= or .arch is used, we can't use anything beyond
1328 cpu_arch_isa_flags. */
1329
1330 if (flag_code == CODE_16BIT)
1331 {
3ae729d5
L		 1332 patt = f16_patt;
1333 max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]);
1334 /* Limit number of NOPs to 2 in 16-bit mode. */
1335 max_number_of_nops = 2;
252b5132 1336 }
33fef721 1337 else
ccc9c027 1338 {
fbf3f584 1339 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1340 {
1341 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1342 switch (cpu_arch_tune)
1343 {
1344 case PROCESSOR_UNKNOWN:
1345 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1346 optimize with nops. */
1347 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1348 patt = alt_patt;
ccc9c027
L		 1349 else
1350 patt = f32_patt;
1351 break;
ccc9c027
L		 1352 case PROCESSOR_PENTIUM4:
1353 case PROCESSOR_NOCONA:
ef05d495 1354 case PROCESSOR_CORE:
76bc74dc 1355 case PROCESSOR_CORE2:
bd5295b2 1356 case PROCESSOR_COREI7:
3632d14b 1357 case PROCESSOR_L1OM:
7a9068fe 1358 case PROCESSOR_K1OM:
76bc74dc 1359 case PROCESSOR_GENERIC64:
ccc9c027
L		 1360 case PROCESSOR_K6:
1361 case PROCESSOR_ATHLON:
1362 case PROCESSOR_K8:
4eed87de 1363 case PROCESSOR_AMDFAM10:
8aedb9fe 1364 case PROCESSOR_BD:
029f3522 1365 case PROCESSOR_ZNVER:
7b458c12 1366 case PROCESSOR_BT:
80b8656c 1367 patt = alt_patt;
ccc9c027 1368 break;
76bc74dc 1369 case PROCESSOR_I386:
ccc9c027
L		 1370 case PROCESSOR_I486:
1371 case PROCESSOR_PENTIUM:
2dde1948 1372 case PROCESSOR_PENTIUMPRO:
81486035 1373 case PROCESSOR_IAMCU:
ccc9c027
L		 1374 case PROCESSOR_GENERIC32:
1375 patt = f32_patt;
1376 break;
4eed87de 1377 }
ccc9c027
L		 1378 }
1379 else
1380 {
fbf3f584 1381 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1382 {
1383 case PROCESSOR_UNKNOWN:
e6a14101 1384 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1385 PROCESSOR_UNKNOWN. */
1386 abort ();
1387 break;
1388
76bc74dc 1389 case PROCESSOR_I386:
ccc9c027
L		 1390 case PROCESSOR_I486:
1391 case PROCESSOR_PENTIUM:
81486035 1392 case PROCESSOR_IAMCU:
ccc9c027
L		 1393 case PROCESSOR_K6:
1394 case PROCESSOR_ATHLON:
1395 case PROCESSOR_K8:
4eed87de 1396 case PROCESSOR_AMDFAM10:
8aedb9fe 1397 case PROCESSOR_BD:
029f3522 1398 case PROCESSOR_ZNVER:
7b458c12 1399 case PROCESSOR_BT:
ccc9c027
L		 1400 case PROCESSOR_GENERIC32:
1401 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1402 with nops. */
1403 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1404 patt = alt_patt;
ccc9c027
L		 1405 else
1406 patt = f32_patt;
1407 break;
76bc74dc
L		 1408 case PROCESSOR_PENTIUMPRO:
1409 case PROCESSOR_PENTIUM4:
1410 case PROCESSOR_NOCONA:
1411 case PROCESSOR_CORE:
ef05d495 1412 case PROCESSOR_CORE2:
bd5295b2 1413 case PROCESSOR_COREI7:
3632d14b 1414 case PROCESSOR_L1OM:
7a9068fe 1415 case PROCESSOR_K1OM:
22109423 1416 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1417 patt = alt_patt;
ccc9c027
L		 1418 else
1419 patt = f32_patt;
1420 break;
1421 case PROCESSOR_GENERIC64:
80b8656c 1422 patt = alt_patt;
ccc9c027 1423 break;
4eed87de 1424 }
ccc9c027
L		 1425 }
1426
76bc74dc
L		 1427 if (patt == f32_patt)
1428 {
3ae729d5
L		 1429 max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]);
1430 /* Limit number of NOPs to 2 for older processors. */
1431 max_number_of_nops = 2;
76bc74dc
L		 1432 }
1433 else
1434 {
3ae729d5
L		 1435 max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]);
1436 /* Limit number of NOPs to 7 for newer processors. */
1437 max_number_of_nops = 7;
1438 }
1439 }
1440
1441 if (limit == 0)
1442 limit = max_single_nop_size;
1443
1444 if (fragP->fr_type == rs_fill_nop)
1445 {
1446 /* Output NOPs for .nop directive. */
1447 if (limit > max_single_nop_size)
1448 {
1449 as_bad_where (fragP->fr_file, fragP->fr_line,
1450 _("invalid single nop size: %d "
1451 "(expect within [0, %d])"),
1452 limit, max_single_nop_size);
1453 return;
1454 }
1455 }
1456 else
1457 fragP->fr_var = count;
1458
1459 if ((count / max_single_nop_size) > max_number_of_nops)
1460 {
1461 /* Generate jump over NOPs. */
1462 offsetT disp = count - 2;
1463 if (fits_in_imm7 (disp))
1464 {
1465 /* Use "jmp disp8" if possible. */
1466 count = disp;
1467 where[0] = jump_disp8[0];
1468 where[1] = count;
1469 where += 2;
1470 }
1471 else
1472 {
1473 unsigned int size_of_jump;
1474
1475 if (flag_code == CODE_16BIT)
1476 {
1477 where[0] = jump16_disp32[0];
1478 where[1] = jump16_disp32[1];
1479 size_of_jump = 2;
1480 }
1481 else
1482 {
1483 where[0] = jump32_disp32[0];
1484 size_of_jump = 1;
1485 }
1486
1487 count -= size_of_jump + 4;
1488 if (!fits_in_imm31 (count))
1489 {
1490 as_bad_where (fragP->fr_file, fragP->fr_line,
1491 _("jump over nop padding out of range"));
1492 return;
1493 }
1494
1495 md_number_to_chars (where + size_of_jump, count, 4);
1496 where += size_of_jump + 4;
76bc74dc 1497 }
ccc9c027 1498 }
3ae729d5
L		 1499
1500 /* Generate multiple NOPs. */
1501 i386_output_nops (where, patt, count, limit);
252b5132
RH		 1502}
1503
c6fb90c8 1504static INLINE int
0dfbf9d7 1505operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1506{
0dfbf9d7 1507 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1508 {
1509 case 3:
0dfbf9d7 1510 if (x->array[2])
c6fb90c8 1511 return 0;
1a0670f3 1512 /* Fall through. */
c6fb90c8 1513 case 2:
0dfbf9d7 1514 if (x->array[1])
c6fb90c8 1515 return 0;
1a0670f3 1516 /* Fall through. */
c6fb90c8 1517 case 1:
0dfbf9d7 1518 return !x->array[0];
c6fb90c8
L		 1519 default:
1520 abort ();
1521 }
40fb9820
L		 1522}
1523
c6fb90c8 1524static INLINE void
0dfbf9d7 1525operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1526{
0dfbf9d7 1527 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1528 {
1529 case 3:
0dfbf9d7 1530 x->array[2] = v;
1a0670f3 1531 /* Fall through. */
c6fb90c8 1532 case 2:
0dfbf9d7 1533 x->array[1] = v;
1a0670f3 1534 /* Fall through. */
c6fb90c8 1535 case 1:
0dfbf9d7 1536 x->array[0] = v;
1a0670f3 1537 /* Fall through. */
c6fb90c8
L		 1538 break;
1539 default:
1540 abort ();
1541 }
1542}
40fb9820 1543
c6fb90c8 1544static INLINE int
0dfbf9d7
L		 1545operand_type_equal (const union i386_operand_type *x,
1546 const union i386_operand_type *y)
c6fb90c8 1547{
0dfbf9d7 1548 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1549 {
1550 case 3:
0dfbf9d7 1551 if (x->array[2] != y->array[2])
c6fb90c8 1552 return 0;
1a0670f3 1553 /* Fall through. */
c6fb90c8 1554 case 2:
0dfbf9d7 1555 if (x->array[1] != y->array[1])
c6fb90c8 1556 return 0;
1a0670f3 1557 /* Fall through. */
c6fb90c8 1558 case 1:
0dfbf9d7 1559 return x->array[0] == y->array[0];
c6fb90c8
L		 1560 break;
1561 default:
1562 abort ();
1563 }
1564}
40fb9820 1565
0dfbf9d7
L		 1566static INLINE int
1567cpu_flags_all_zero (const union i386_cpu_flags *x)
1568{
1569 switch (ARRAY_SIZE(x->array))
1570 {
53467f57
IT		 1571 case 4:
1572 if (x->array[3])
1573 return 0;
1574 /* Fall through. */
0dfbf9d7
L		 1575 case 3:
1576 if (x->array[2])
1577 return 0;
1a0670f3 1578 /* Fall through. */
0dfbf9d7
L		 1579 case 2:
1580 if (x->array[1])
1581 return 0;
1a0670f3 1582 /* Fall through. */
0dfbf9d7
L		 1583 case 1:
1584 return !x->array[0];
1585 default:
1586 abort ();
1587 }
1588}
1589
0dfbf9d7
L		 1590static INLINE int
1591cpu_flags_equal (const union i386_cpu_flags *x,
1592 const union i386_cpu_flags *y)
1593{
1594 switch (ARRAY_SIZE(x->array))
1595 {
53467f57
IT		 1596 case 4:
1597 if (x->array[3] != y->array[3])
1598 return 0;
1599 /* Fall through. */
0dfbf9d7
L		 1600 case 3:
1601 if (x->array[2] != y->array[2])
1602 return 0;
1a0670f3 1603 /* Fall through. */
0dfbf9d7
L		 1604 case 2:
1605 if (x->array[1] != y->array[1])
1606 return 0;
1a0670f3 1607 /* Fall through. */
0dfbf9d7
L		 1608 case 1:
1609 return x->array[0] == y->array[0];
1610 break;
1611 default:
1612 abort ();
1613 }
1614}
c6fb90c8
L		 1615
1616static INLINE int
1617cpu_flags_check_cpu64 (i386_cpu_flags f)
1618{
1619 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1620 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1621}
1622
c6fb90c8
L		 1623static INLINE i386_cpu_flags
1624cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1625{
c6fb90c8
L		 1626 switch (ARRAY_SIZE (x.array))
1627 {
53467f57
IT		 1628 case 4:
1629 x.array [3] &= y.array [3];
1630 /* Fall through. */
c6fb90c8
L		 1631 case 3:
1632 x.array [2] &= y.array [2];
1a0670f3 1633 /* Fall through. */
c6fb90c8
L		 1634 case 2:
1635 x.array [1] &= y.array [1];
1a0670f3 1636 /* Fall through. */
c6fb90c8
L		 1637 case 1:
1638 x.array [0] &= y.array [0];
1639 break;
1640 default:
1641 abort ();
1642 }
1643 return x;
1644}
40fb9820 1645
c6fb90c8
L		 1646static INLINE i386_cpu_flags
1647cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1648{
c6fb90c8 1649 switch (ARRAY_SIZE (x.array))
40fb9820 1650 {
53467f57
IT		 1651 case 4:
1652 x.array [3] |= y.array [3];
1653 /* Fall through. */
c6fb90c8
L		 1654 case 3:
1655 x.array [2] |= y.array [2];
1a0670f3 1656 /* Fall through. */
c6fb90c8
L		 1657 case 2:
1658 x.array [1] |= y.array [1];
1a0670f3 1659 /* Fall through. */
c6fb90c8
L		 1660 case 1:
1661 x.array [0] |= y.array [0];
40fb9820
L		 1662 break;
1663 default:
1664 abort ();
1665 }
40fb9820
L		 1666 return x;
1667}
1668
309d3373
JB		 1669static INLINE i386_cpu_flags
1670cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1671{
1672 switch (ARRAY_SIZE (x.array))
1673 {
53467f57
IT		 1674 case 4:
1675 x.array [3] &= ~y.array [3];
1676 /* Fall through. */
309d3373
JB		 1677 case 3:
1678 x.array [2] &= ~y.array [2];
1a0670f3 1679 /* Fall through. */
309d3373
JB		 1680 case 2:
1681 x.array [1] &= ~y.array [1];
1a0670f3 1682 /* Fall through. */
309d3373
JB		 1683 case 1:
1684 x.array [0] &= ~y.array [0];
1685 break;
1686 default:
1687 abort ();
1688 }
1689 return x;
1690}
1691
c0f3af97
L		 1692#define CPU_FLAGS_ARCH_MATCH 0x1
1693#define CPU_FLAGS_64BIT_MATCH 0x2
1694
c0f3af97 1695#define CPU_FLAGS_PERFECT_MATCH \
db12e14e 1696 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
c0f3af97
L		 1697
1698/* Return CPU flags match bits. */
3629bb00 1699
40fb9820 1700static int
d3ce72d0 1701cpu_flags_match (const insn_template *t)
40fb9820 1702{
c0f3af97
L		 1703 i386_cpu_flags x = t->cpu_flags;
1704 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1705
1706 x.bitfield.cpu64 = 0;
1707 x.bitfield.cpuno64 = 0;
1708
0dfbf9d7 1709 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1710 {
1711 /* This instruction is available on all archs. */
db12e14e 1712 match |= CPU_FLAGS_ARCH_MATCH;
c0f3af97 1713 }
3629bb00
L		 1714 else
1715 {
c0f3af97 1716 /* This instruction is available only on some archs. */
3629bb00
L		 1717 i386_cpu_flags cpu = cpu_arch_flags;
1718
ab592e75
JB		 1719 /* AVX512VL is no standalone feature - match it and then strip it. */
1720 if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl)
1721 return match;
1722 x.bitfield.cpuavx512vl = 0;
1723
3629bb00 1724 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1725 if (!cpu_flags_all_zero (&cpu))
1726 {
a5ff0eb2
L		 1727 if (x.bitfield.cpuavx)
1728 {
929f69fa 1729 /* We need to check a few extra flags with AVX. */
b9d49817
JB		 1730 if (cpu.bitfield.cpuavx
1731 && (!t->opcode_modifier.sse2avx || sse2avx)
1732 && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
929f69fa 1733 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
b9d49817
JB		 1734 && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul))
1735 match |= CPU_FLAGS_ARCH_MATCH;
a5ff0eb2 1736 }
929f69fa
JB		 1737 else if (x.bitfield.cpuavx512f)
1738 {
1739 /* We need to check a few extra flags with AVX512F. */
1740 if (cpu.bitfield.cpuavx512f
1741 && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni)
1742 && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes)
1743 && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq))
1744 match |= CPU_FLAGS_ARCH_MATCH;
1745 }
a5ff0eb2 1746 else
db12e14e 1747 match |= CPU_FLAGS_ARCH_MATCH;
c0f3af97 1748 }
3629bb00 1749 }
c0f3af97 1750 return match;
40fb9820
L		 1751}
1752
c6fb90c8
L		 1753static INLINE i386_operand_type
1754operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1755{
c6fb90c8
L		 1756 switch (ARRAY_SIZE (x.array))
1757 {
1758 case 3:
1759 x.array [2] &= y.array [2];
1a0670f3 1760 /* Fall through. */
c6fb90c8
L		 1761 case 2:
1762 x.array [1] &= y.array [1];
1a0670f3 1763 /* Fall through. */
c6fb90c8
L		 1764 case 1:
1765 x.array [0] &= y.array [0];
1766 break;
1767 default:
1768 abort ();
1769 }
1770 return x;
40fb9820
L		 1771}
1772
73053c1f
JB		 1773static INLINE i386_operand_type
1774operand_type_and_not (i386_operand_type x, i386_operand_type y)
1775{
1776 switch (ARRAY_SIZE (x.array))
1777 {
1778 case 3:
1779 x.array [2] &= ~y.array [2];
1780 /* Fall through. */
1781 case 2:
1782 x.array [1] &= ~y.array [1];
1783 /* Fall through. */
1784 case 1:
1785 x.array [0] &= ~y.array [0];
1786 break;
1787 default:
1788 abort ();
1789 }
1790 return x;
1791}
1792
c6fb90c8
L		 1793static INLINE i386_operand_type
1794operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1795{
c6fb90c8 1796 switch (ARRAY_SIZE (x.array))
40fb9820 1797 {
c6fb90c8
L		 1798 case 3:
1799 x.array [2] |= y.array [2];
1a0670f3 1800 /* Fall through. */
c6fb90c8
L		 1801 case 2:
1802 x.array [1] |= y.array [1];
1a0670f3 1803 /* Fall through. */
c6fb90c8
L		 1804 case 1:
1805 x.array [0] |= y.array [0];
40fb9820
L		 1806 break;
1807 default:
1808 abort ();
1809 }
c6fb90c8
L		 1810 return x;
1811}
40fb9820 1812
c6fb90c8
L		 1813static INLINE i386_operand_type
1814operand_type_xor (i386_operand_type x, i386_operand_type y)
1815{
1816 switch (ARRAY_SIZE (x.array))
1817 {
1818 case 3:
1819 x.array [2] ^= y.array [2];
1a0670f3 1820 /* Fall through. */
c6fb90c8
L		 1821 case 2:
1822 x.array [1] ^= y.array [1];
1a0670f3 1823 /* Fall through. */
c6fb90c8
L		 1824 case 1:
1825 x.array [0] ^= y.array [0];
1826 break;
1827 default:
1828 abort ();
1829 }
40fb9820
L		 1830 return x;
1831}
1832
1833static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1834static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
40fb9820
L		 1835static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1836static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1837static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1838static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1839static const i386_operand_type anydisp
1840 = OPERAND_TYPE_ANYDISP;
40fb9820 1841static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
43234a1e 1842static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1843static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1844static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1845static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1846static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1847static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1848static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1849static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1850static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1851static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1852static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1853
1854enum operand_type
1855{
1856 reg,
40fb9820
L		 1857 imm,
1858 disp,
1859 anymem
1860};
1861
c6fb90c8 1862static INLINE int
40fb9820
L		 1863operand_type_check (i386_operand_type t, enum operand_type c)
1864{
1865 switch (c)
1866 {
1867 case reg:
dc821c5f 1868 return t.bitfield.reg;
40fb9820 1869
40fb9820
L		 1870 case imm:
1871 return (t.bitfield.imm8
1872 || t.bitfield.imm8s
1873 || t.bitfield.imm16
1874 || t.bitfield.imm32
1875 || t.bitfield.imm32s
1876 || t.bitfield.imm64);
1877
1878 case disp:
1879 return (t.bitfield.disp8
1880 || t.bitfield.disp16
1881 || t.bitfield.disp32
1882 || t.bitfield.disp32s
1883 || t.bitfield.disp64);
1884
1885 case anymem:
1886 return (t.bitfield.disp8
1887 || t.bitfield.disp16
1888 || t.bitfield.disp32
1889 || t.bitfield.disp32s
1890 || t.bitfield.disp64
1891 || t.bitfield.baseindex);
1892
1893 default:
1894 abort ();
1895 }
2cfe26b6
AM		 1896
1897 return 0;
40fb9820
L		 1898}
1899
ca0d63fe 1900/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
5c07affc
L		 1901 operand J for instruction template T. */
1902
1903static INLINE int
3ac21baa 1904match_reg_size (const insn_template *t, unsigned int wanted, unsigned int given)
5c07affc 1905{
3ac21baa
JB		 1906 return !((i.types[given].bitfield.byte
1907 && !t->operand_types[wanted].bitfield.byte)
1908 || (i.types[given].bitfield.word
1909 && !t->operand_types[wanted].bitfield.word)
1910 || (i.types[given].bitfield.dword
1911 && !t->operand_types[wanted].bitfield.dword)
1912 || (i.types[given].bitfield.qword
1913 && !t->operand_types[wanted].bitfield.qword)
1914 || (i.types[given].bitfield.tbyte
1915 && !t->operand_types[wanted].bitfield.tbyte));
5c07affc
L		 1916}
1917
1b54b8d7
JB		 1918/* Return 1 if there is no conflict in SIMD register on
1919 operand J for instruction template T. */
1920
1921static INLINE int
3ac21baa 1922match_simd_size (const insn_template *t, unsigned int wanted, unsigned int given)
1b54b8d7 1923{
3ac21baa
JB		 1924 return !((i.types[given].bitfield.xmmword
1925 && !t->operand_types[wanted].bitfield.xmmword)
1926 || (i.types[given].bitfield.ymmword
1927 && !t->operand_types[wanted].bitfield.ymmword)
1928 || (i.types[given].bitfield.zmmword
1929 && !t->operand_types[wanted].bitfield.zmmword));
1b54b8d7
JB		 1930}
1931
5c07affc
L		 1932/* Return 1 if there is no conflict in any size on operand J for
1933 instruction template T. */
1934
1935static INLINE int
3ac21baa 1936match_mem_size (const insn_template *t, unsigned int wanted, unsigned int given)
5c07affc 1937{
3ac21baa
JB		 1938 return (match_reg_size (t, wanted, given)
1939 && !((i.types[given].bitfield.unspecified
af508cb9 1940 && !i.broadcast
3ac21baa
JB		 1941 && !t->operand_types[wanted].bitfield.unspecified)
1942 || (i.types[given].bitfield.fword
1943 && !t->operand_types[wanted].bitfield.fword)
1b54b8d7
JB		 1944 /* For scalar opcode templates to allow register and memory
1945 operands at the same time, some special casing is needed
d6793fa1
JB		 1946 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
1947 down-conversion vpmov*. */
3ac21baa 1948 || ((t->operand_types[wanted].bitfield.regsimd
1b54b8d7 1949 && !t->opcode_modifier.broadcast
3ac21baa
JB		 1950 && (t->operand_types[wanted].bitfield.byte
1951 || t->operand_types[wanted].bitfield.word
1952 || t->operand_types[wanted].bitfield.dword
1953 || t->operand_types[wanted].bitfield.qword))
1954 ? (i.types[given].bitfield.xmmword
1955 || i.types[given].bitfield.ymmword
1956 || i.types[given].bitfield.zmmword)
1957 : !match_simd_size(t, wanted, given))));
5c07affc
L		 1958}
1959
3ac21baa
JB		 1960/* Return value has MATCH_STRAIGHT set if there is no size conflict on any
1961 operands for instruction template T, and it has MATCH_REVERSE set if there
1962 is no size conflict on any operands for the template with operands reversed
1963 (and the template allows for reversing in the first place). */
5c07affc 1964
3ac21baa
JB		 1965#define MATCH_STRAIGHT 1
1966#define MATCH_REVERSE 2
1967
1968static INLINE unsigned int
d3ce72d0 1969operand_size_match (const insn_template *t)
5c07affc 1970{
3ac21baa 1971 unsigned int j, match = MATCH_STRAIGHT;
5c07affc
L		 1972
1973 /* Don't check jump instructions. */
1974 if (t->opcode_modifier.jump
1975 || t->opcode_modifier.jumpbyte
1976 || t->opcode_modifier.jumpdword
1977 || t->opcode_modifier.jumpintersegment)
1978 return match;
1979
1980 /* Check memory and accumulator operand size. */
1981 for (j = 0; j < i.operands; j++)
1982 {
1b54b8d7
JB		 1983 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
1984 && t->operand_types[j].bitfield.anysize)
5c07affc
L		 1985 continue;
1986
1b54b8d7 1987 if (t->operand_types[j].bitfield.reg
3ac21baa 1988 && !match_reg_size (t, j, j))
5c07affc
L		 1989 {
1990 match = 0;
1991 break;
1992 }
1993
1b54b8d7 1994 if (t->operand_types[j].bitfield.regsimd
3ac21baa 1995 && !match_simd_size (t, j, j))
1b54b8d7
JB		 1996 {
1997 match = 0;
1998 break;
1999 }
2000
2001 if (t->operand_types[j].bitfield.acc
3ac21baa 2002 && (!match_reg_size (t, j, j) || !match_simd_size (t, j, j)))
1b54b8d7
JB		 2003 {
2004 match = 0;
2005 break;
2006 }
2007
3ac21baa 2008 if (i.types[j].bitfield.mem && !match_mem_size (t, j, j))
5c07affc
L		 2009 {
2010 match = 0;
2011 break;
2012 }
2013 }
2014
3ac21baa 2015 if (!t->opcode_modifier.d)
891edac4
L		 2016 {
2017mismatch:
3ac21baa
JB		 2018 if (!match)
2019 i.error = operand_size_mismatch;
2020 return match;
891edac4 2021 }
5c07affc
L		 2022
2023 /* Check reverse. */
9c2799c2 2024 gas_assert (i.operands == 2);
5c07affc 2025
5c07affc
L		 2026 for (j = 0; j < 2; j++)
2027 {
dc821c5f
JB		 2028 if ((t->operand_types[j].bitfield.reg
2029 || t->operand_types[j].bitfield.acc)
3ac21baa 2030 && !match_reg_size (t, j, !j))
891edac4 2031 goto mismatch;
5c07affc 2032
3ac21baa
JB		 2033 if (i.types[!j].bitfield.mem
2034 && !match_mem_size (t, j, !j))
891edac4 2035 goto mismatch;
5c07affc
L		 2036 }
2037
3ac21baa 2038 return match | MATCH_REVERSE;
5c07affc
L		 2039}
2040
c6fb90c8 2041static INLINE int
40fb9820
L		 2042operand_type_match (i386_operand_type overlap,
2043 i386_operand_type given)
2044{
2045 i386_operand_type temp = overlap;
2046
2047 temp.bitfield.jumpabsolute = 0;
7d5e4556 2048 temp.bitfield.unspecified = 0;
5c07affc
L		 2049 temp.bitfield.byte = 0;
2050 temp.bitfield.word = 0;
2051 temp.bitfield.dword = 0;
2052 temp.bitfield.fword = 0;
2053 temp.bitfield.qword = 0;
2054 temp.bitfield.tbyte = 0;
2055 temp.bitfield.xmmword = 0;
c0f3af97 2056 temp.bitfield.ymmword = 0;
43234a1e 2057 temp.bitfield.zmmword = 0;
0dfbf9d7 2058 if (operand_type_all_zero (&temp))
891edac4 2059 goto mismatch;
40fb9820 2060
891edac4
L		 2061 if (given.bitfield.baseindex == overlap.bitfield.baseindex
2062 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
2063 return 1;
2064
2065mismatch:
a65babc9 2066 i.error = operand_type_mismatch;
891edac4 2067 return 0;
40fb9820
L		 2068}
2069
7d5e4556 2070/* If given types g0 and g1 are registers they must be of the same type
10c17abd
JB		 2071 unless the expected operand type register overlap is null.
2072 Memory operand size of certain SIMD instructions is also being checked
2073 here. */
40fb9820 2074
c6fb90c8 2075static INLINE int
dc821c5f 2076operand_type_register_match (i386_operand_type g0,
40fb9820 2077 i386_operand_type t0,
40fb9820
L		 2078 i386_operand_type g1,
2079 i386_operand_type t1)
2080{
10c17abd
JB		 2081 if (!g0.bitfield.reg
2082 && !g0.bitfield.regsimd
2083 && (!operand_type_check (g0, anymem)
2084 || g0.bitfield.unspecified
2085 || !t0.bitfield.regsimd))
40fb9820
L		 2086 return 1;
2087
10c17abd
JB		 2088 if (!g1.bitfield.reg
2089 && !g1.bitfield.regsimd
2090 && (!operand_type_check (g1, anymem)
2091 || g1.bitfield.unspecified
2092 || !t1.bitfield.regsimd))
40fb9820
L		 2093 return 1;
2094
dc821c5f
JB		 2095 if (g0.bitfield.byte == g1.bitfield.byte
2096 && g0.bitfield.word == g1.bitfield.word
2097 && g0.bitfield.dword == g1.bitfield.dword
10c17abd
JB		 2098 && g0.bitfield.qword == g1.bitfield.qword
2099 && g0.bitfield.xmmword == g1.bitfield.xmmword
2100 && g0.bitfield.ymmword == g1.bitfield.ymmword
2101 && g0.bitfield.zmmword == g1.bitfield.zmmword)
40fb9820
L		 2102 return 1;
2103
dc821c5f
JB		 2104 if (!(t0.bitfield.byte & t1.bitfield.byte)
2105 && !(t0.bitfield.word & t1.bitfield.word)
2106 && !(t0.bitfield.dword & t1.bitfield.dword)
10c17abd
JB		 2107 && !(t0.bitfield.qword & t1.bitfield.qword)
2108 && !(t0.bitfield.xmmword & t1.bitfield.xmmword)
2109 && !(t0.bitfield.ymmword & t1.bitfield.ymmword)
2110 && !(t0.bitfield.zmmword & t1.bitfield.zmmword))
891edac4
L		 2111 return 1;
2112
a65babc9 2113 i.error = register_type_mismatch;
891edac4
L		 2114
2115 return 0;
40fb9820
L		 2116}
2117
4c692bc7
JB		 2118static INLINE unsigned int
2119register_number (const reg_entry *r)
2120{
2121 unsigned int nr = r->reg_num;
2122
2123 if (r->reg_flags & RegRex)
2124 nr += 8;
2125
200cbe0f
L		 2126 if (r->reg_flags & RegVRex)
2127 nr += 16;
2128
4c692bc7
JB		 2129 return nr;
2130}
2131
252b5132 2132static INLINE unsigned int
40fb9820 2133mode_from_disp_size (i386_operand_type t)
252b5132 2134{
b5014f7a 2135 if (t.bitfield.disp8)
40fb9820
L		 2136 return 1;
2137 else if (t.bitfield.disp16
2138 || t.bitfield.disp32
2139 || t.bitfield.disp32s)
2140 return 2;
2141 else
2142 return 0;
252b5132
RH		 2143}
2144
2145static INLINE int
65879393 2146fits_in_signed_byte (addressT num)
252b5132 2147{
65879393 2148 return num + 0x80 <= 0xff;
47926f60 2149}
252b5132
RH		 2150
2151static INLINE int
65879393 2152fits_in_unsigned_byte (addressT num)
252b5132 2153{
65879393 2154 return num <= 0xff;
47926f60 2155}
252b5132
RH		 2156
2157static INLINE int
65879393 2158fits_in_unsigned_word (addressT num)
252b5132 2159{
65879393 2160 return num <= 0xffff;
47926f60 2161}
252b5132
RH		 2162
2163static INLINE int
65879393 2164fits_in_signed_word (addressT num)
252b5132 2165{
65879393 2166 return num + 0x8000 <= 0xffff;
47926f60 2167}
2a962e6d 2168
3e73aa7c 2169static INLINE int
65879393 2170fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2171{
2172#ifndef BFD64
2173 return 1;
2174#else
65879393 2175 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 2176#endif
2177} /* fits_in_signed_long() */
2a962e6d 2178
3e73aa7c 2179static INLINE int
65879393 2180fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2181{
2182#ifndef BFD64
2183 return 1;
2184#else
65879393 2185 return num <= 0xffffffff;
3e73aa7c
JH		 2186#endif
2187} /* fits_in_unsigned_long() */
252b5132 2188
43234a1e 2189static INLINE int
b5014f7a 2190fits_in_disp8 (offsetT num)
43234a1e
L		 2191{
2192 int shift = i.memshift;
2193 unsigned int mask;
2194
2195 if (shift == -1)
2196 abort ();
2197
2198 mask = (1 << shift) - 1;
2199
2200 /* Return 0 if NUM isn't properly aligned. */
2201 if ((num & mask))
2202 return 0;
2203
2204 /* Check if NUM will fit in 8bit after shift. */
2205 return fits_in_signed_byte (num >> shift);
2206}
2207
a683cc34
SP		 2208static INLINE int
2209fits_in_imm4 (offsetT num)
2210{
2211 return (num & 0xf) == num;
2212}
2213
40fb9820 2214static i386_operand_type
e3bb37b5 2215smallest_imm_type (offsetT num)
252b5132 2216{
40fb9820 2217 i386_operand_type t;
7ab9ffdd 2218
0dfbf9d7 2219 operand_type_set (&t, 0);
40fb9820
L		 2220 t.bitfield.imm64 = 1;
2221
2222 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2223 {
2224 /* This code is disabled on the 486 because all the Imm1 forms
2225 in the opcode table are slower on the i486. They're the
2226 versions with the implicitly specified single-position
2227 displacement, which has another syntax if you really want to
2228 use that form. */
40fb9820
L		 2229 t.bitfield.imm1 = 1;
2230 t.bitfield.imm8 = 1;
2231 t.bitfield.imm8s = 1;
2232 t.bitfield.imm16 = 1;
2233 t.bitfield.imm32 = 1;
2234 t.bitfield.imm32s = 1;
2235 }
2236 else if (fits_in_signed_byte (num))
2237 {
2238 t.bitfield.imm8 = 1;
2239 t.bitfield.imm8s = 1;
2240 t.bitfield.imm16 = 1;
2241 t.bitfield.imm32 = 1;
2242 t.bitfield.imm32s = 1;
2243 }
2244 else if (fits_in_unsigned_byte (num))
2245 {
2246 t.bitfield.imm8 = 1;
2247 t.bitfield.imm16 = 1;
2248 t.bitfield.imm32 = 1;
2249 t.bitfield.imm32s = 1;
2250 }
2251 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2252 {
2253 t.bitfield.imm16 = 1;
2254 t.bitfield.imm32 = 1;
2255 t.bitfield.imm32s = 1;
2256 }
2257 else if (fits_in_signed_long (num))
2258 {
2259 t.bitfield.imm32 = 1;
2260 t.bitfield.imm32s = 1;
2261 }
2262 else if (fits_in_unsigned_long (num))
2263 t.bitfield.imm32 = 1;
2264
2265 return t;
47926f60 2266}
252b5132 2267
847f7ad4 2268static offsetT
e3bb37b5 2269offset_in_range (offsetT val, int size)
847f7ad4 2270{
508866be 2271 addressT mask;
ba2adb93 2272
847f7ad4
AM		 2273 switch (size)
2274 {
508866be
L		 2275 case 1: mask = ((addressT) 1 << 8) - 1; break;
2276 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2277 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2278#ifdef BFD64
2279 case 8: mask = ((addressT) 2 << 63) - 1; break;
2280#endif
47926f60 2281 default: abort ();
847f7ad4
AM		 2282 }
2283
9de868bf
L		 2284#ifdef BFD64
2285 /* If BFD64, sign extend val for 32bit address mode. */
2286 if (flag_code != CODE_64BIT
2287 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2288 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2289 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2290#endif
ba2adb93 2291
47926f60 2292 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2293 {
2294 char buf1[40], buf2[40];
2295
2296 sprint_value (buf1, val);
2297 sprint_value (buf2, val & mask);
2298 as_warn (_("%s shortened to %s"), buf1, buf2);
2299 }
2300 return val & mask;
2301}
2302
c32fa91d
L		 2303enum PREFIX_GROUP
2304{
2305 PREFIX_EXIST = 0,
2306 PREFIX_LOCK,
2307 PREFIX_REP,
04ef582a 2308 PREFIX_DS,
c32fa91d
L		 2309 PREFIX_OTHER
2310};
2311
2312/* Returns
2313 a. PREFIX_EXIST if attempting to add a prefix where one from the
2314 same class already exists.
2315 b. PREFIX_LOCK if lock prefix is added.
2316 c. PREFIX_REP if rep/repne prefix is added.
04ef582a
L		 2317 d. PREFIX_DS if ds prefix is added.
2318 e. PREFIX_OTHER if other prefix is added.
c32fa91d
L		 2319 */
2320
2321static enum PREFIX_GROUP
e3bb37b5 2322add_prefix (unsigned int prefix)
252b5132 2323{
c32fa91d 2324 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2325 unsigned int q;
252b5132 2326
29b0f896
AM		 2327 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2328 && flag_code == CODE_64BIT)
b1905489 2329 {
161a04f6 2330 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
44846f29
JB		 2331 || (i.prefix[REX_PREFIX] & prefix & REX_R)
2332 || (i.prefix[REX_PREFIX] & prefix & REX_X)
2333 || (i.prefix[REX_PREFIX] & prefix & REX_B))
c32fa91d 2334 ret = PREFIX_EXIST;
b1905489
JB		 2335 q = REX_PREFIX;
2336 }
3e73aa7c 2337 else
b1905489
JB		 2338 {
2339 switch (prefix)
2340 {
2341 default:
2342 abort ();
2343
b1905489 2344 case DS_PREFIX_OPCODE:
04ef582a
L		 2345 ret = PREFIX_DS;
2346 /* Fall through. */
2347 case CS_PREFIX_OPCODE:
b1905489
JB		 2348 case ES_PREFIX_OPCODE:
2349 case FS_PREFIX_OPCODE:
2350 case GS_PREFIX_OPCODE:
2351 case SS_PREFIX_OPCODE:
2352 q = SEG_PREFIX;
2353 break;
2354
2355 case REPNE_PREFIX_OPCODE:
2356 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2357 q = REP_PREFIX;
2358 ret = PREFIX_REP;
2359 break;
2360
b1905489 2361 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2362 q = LOCK_PREFIX;
2363 ret = PREFIX_LOCK;
b1905489
JB		 2364 break;
2365
2366 case FWAIT_OPCODE:
2367 q = WAIT_PREFIX;
2368 break;
2369
2370 case ADDR_PREFIX_OPCODE:
2371 q = ADDR_PREFIX;
2372 break;
2373
2374 case DATA_PREFIX_OPCODE:
2375 q = DATA_PREFIX;
2376 break;
2377 }
2378 if (i.prefix[q] != 0)
c32fa91d 2379 ret = PREFIX_EXIST;
b1905489 2380 }
252b5132 2381
b1905489 2382 if (ret)
252b5132 2383 {
b1905489
JB		 2384 if (!i.prefix[q])
2385 ++i.prefixes;
2386 i.prefix[q] |= prefix;
252b5132 2387 }
b1905489
JB		 2388 else
2389 as_bad (_("same type of prefix used twice"));
252b5132 2390
252b5132
RH		 2391 return ret;
2392}
2393
2394static void
78f12dd3 2395update_code_flag (int value, int check)
eecb386c 2396{
78f12dd3
L		 2397 PRINTF_LIKE ((*as_error));
2398
1e9cc1c2 2399 flag_code = (enum flag_code) value;
40fb9820
L		 2400 if (flag_code == CODE_64BIT)
2401 {
2402 cpu_arch_flags.bitfield.cpu64 = 1;
2403 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2404 }
2405 else
2406 {
2407 cpu_arch_flags.bitfield.cpu64 = 0;
2408 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2409 }
2410 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2411 {
78f12dd3
L		 2412 if (check)
2413 as_error = as_fatal;
2414 else
2415 as_error = as_bad;
2416 (*as_error) (_("64bit mode not supported on `%s'."),
2417 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2418 }
40fb9820 2419 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2420 {
78f12dd3
L		 2421 if (check)
2422 as_error = as_fatal;
2423 else
2424 as_error = as_bad;
2425 (*as_error) (_("32bit mode not supported on `%s'."),
2426 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2427 }
eecb386c
AM		 2428 stackop_size = '\0';
2429}
2430
78f12dd3
L		 2431static void
2432set_code_flag (int value)
2433{
2434 update_code_flag (value, 0);
2435}
2436
eecb386c 2437static void
e3bb37b5 2438set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2439{
1e9cc1c2 2440 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2441 if (flag_code != CODE_16BIT)
2442 abort ();
2443 cpu_arch_flags.bitfield.cpu64 = 0;
2444 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2445 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2446}
2447
2448static void
e3bb37b5 2449set_intel_syntax (int syntax_flag)
252b5132
RH		 2450{
2451 /* Find out if register prefixing is specified. */
2452 int ask_naked_reg = 0;
2453
2454 SKIP_WHITESPACE ();
29b0f896 2455 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132 2456 {
d02603dc
NC		 2457 char *string;
2458 int e = get_symbol_name (&string);
252b5132 2459
47926f60 2460 if (strcmp (string, "prefix") == 0)
252b5132 2461 ask_naked_reg = 1;
47926f60 2462 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2463 ask_naked_reg = -1;
2464 else
d0b47220 2465 as_bad (_("bad argument to syntax directive."));
d02603dc 2466 (void) restore_line_pointer (e);
252b5132
RH		 2467 }
2468 demand_empty_rest_of_line ();
c3332e24 2469
252b5132
RH		 2470 intel_syntax = syntax_flag;
2471
2472 if (ask_naked_reg == 0)
f86103b7
AM		 2473 allow_naked_reg = (intel_syntax
2474 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2475 else
2476 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2477
ee86248c 2478 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2479
e4a3b5a4 2480 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2481 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2482 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2483}
2484
1efbbeb4
L		 2485static void
2486set_intel_mnemonic (int mnemonic_flag)
2487{
e1d4d893 2488 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2489}
2490
db51cc60
L		 2491static void
2492set_allow_index_reg (int flag)
2493{
2494 allow_index_reg = flag;
2495}
2496
cb19c032 2497static void
7bab8ab5 2498set_check (int what)
cb19c032 2499{
7bab8ab5
JB		 2500 enum check_kind *kind;
2501 const char *str;
2502
2503 if (what)
2504 {
2505 kind = &operand_check;
2506 str = "operand";
2507 }
2508 else
2509 {
2510 kind = &sse_check;
2511 str = "sse";
2512 }
2513
cb19c032
L		 2514 SKIP_WHITESPACE ();
2515
2516 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2517 {
d02603dc
NC		 2518 char *string;
2519 int e = get_symbol_name (&string);
cb19c032
L		 2520
2521 if (strcmp (string, "none") == 0)
7bab8ab5 2522 *kind = check_none;
cb19c032 2523 else if (strcmp (string, "warning") == 0)
7bab8ab5 2524 *kind = check_warning;
cb19c032 2525 else if (strcmp (string, "error") == 0)
7bab8ab5 2526 *kind = check_error;
cb19c032 2527 else
7bab8ab5 2528 as_bad (_("bad argument to %s_check directive."), str);
d02603dc 2529 (void) restore_line_pointer (e);
cb19c032
L		 2530 }
2531 else
7bab8ab5 2532 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2533
2534 demand_empty_rest_of_line ();
2535}
2536
8a9036a4
L		 2537static void
2538check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2539 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2540{
2541#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2542 static const char *arch;
2543
2544 /* Intel LIOM is only supported on ELF. */
2545 if (!IS_ELF)
2546 return;
2547
2548 if (!arch)
2549 {
2550 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2551 use default_arch. */
2552 arch = cpu_arch_name;
2553 if (!arch)
2554 arch = default_arch;
2555 }
2556
81486035
L		 2557 /* If we are targeting Intel MCU, we must enable it. */
2558 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2559 || new_flag.bitfield.cpuiamcu)
2560 return;
2561
3632d14b 2562 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2563 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2564 || new_flag.bitfield.cpul1om)
8a9036a4 2565 return;
76ba9986 2566
7a9068fe
L		 2567 /* If we are targeting Intel K1OM, we must enable it. */
2568 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2569 || new_flag.bitfield.cpuk1om)
2570 return;
2571
8a9036a4
L		 2572 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2573#endif
2574}
2575
e413e4e9 2576static void
e3bb37b5 2577set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2578{
47926f60 2579 SKIP_WHITESPACE ();
e413e4e9 2580
29b0f896 2581 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9 2582 {
d02603dc
NC		 2583 char *string;
2584 int e = get_symbol_name (&string);
91d6fa6a 2585 unsigned int j;
40fb9820 2586 i386_cpu_flags flags;
e413e4e9 2587
91d6fa6a 2588 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2589 {
91d6fa6a 2590 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2591 {
91d6fa6a 2592 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2593
5c6af06e
JB		 2594 if (*string != '.')
2595 {
91d6fa6a 2596 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2597 cpu_sub_arch_name = NULL;
91d6fa6a 2598 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2599 if (flag_code == CODE_64BIT)
2600 {
2601 cpu_arch_flags.bitfield.cpu64 = 1;
2602 cpu_arch_flags.bitfield.cpuno64 = 0;
2603 }
2604 else
2605 {
2606 cpu_arch_flags.bitfield.cpu64 = 0;
2607 cpu_arch_flags.bitfield.cpuno64 = 1;
2608 }
91d6fa6a
NC		 2609 cpu_arch_isa = cpu_arch[j].type;
2610 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2611 if (!cpu_arch_tune_set)
2612 {
2613 cpu_arch_tune = cpu_arch_isa;
2614 cpu_arch_tune_flags = cpu_arch_isa_flags;
2615 }
5c6af06e
JB		 2616 break;
2617 }
40fb9820 2618
293f5f65
L		 2619 flags = cpu_flags_or (cpu_arch_flags,
2620 cpu_arch[j].flags);
81486035 2621
5b64d091 2622 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2623 {
6305a203
L		 2624 if (cpu_sub_arch_name)
2625 {
2626 char *name = cpu_sub_arch_name;
2627 cpu_sub_arch_name = concat (name,
91d6fa6a 2628 cpu_arch[j].name,
1bf57e9f 2629 (const char *) NULL);
6305a203
L		 2630 free (name);
2631 }
2632 else
91d6fa6a 2633 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2634 cpu_arch_flags = flags;
a586129e 2635 cpu_arch_isa_flags = flags;
5c6af06e 2636 }
0089dace
L		 2637 else
2638 cpu_arch_isa_flags
2639 = cpu_flags_or (cpu_arch_isa_flags,
2640 cpu_arch[j].flags);
d02603dc 2641 (void) restore_line_pointer (e);
5c6af06e
JB		 2642 demand_empty_rest_of_line ();
2643 return;
e413e4e9
AM		 2644 }
2645 }
293f5f65
L		 2646
2647 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2648 {
33eaf5de 2649 /* Disable an ISA extension. */
293f5f65
L		 2650 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2651 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2652 {
2653 flags = cpu_flags_and_not (cpu_arch_flags,
2654 cpu_noarch[j].flags);
2655 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2656 {
2657 if (cpu_sub_arch_name)
2658 {
2659 char *name = cpu_sub_arch_name;
2660 cpu_sub_arch_name = concat (name, string,
2661 (const char *) NULL);
2662 free (name);
2663 }
2664 else
2665 cpu_sub_arch_name = xstrdup (string);
2666 cpu_arch_flags = flags;
2667 cpu_arch_isa_flags = flags;
2668 }
2669 (void) restore_line_pointer (e);
2670 demand_empty_rest_of_line ();
2671 return;
2672 }
2673
2674 j = ARRAY_SIZE (cpu_arch);
2675 }
2676
91d6fa6a 2677 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2678 as_bad (_("no such architecture: `%s'"), string);
2679
2680 *input_line_pointer = e;
2681 }
2682 else
2683 as_bad (_("missing cpu architecture"));
2684
fddf5b5b
AM		 2685 no_cond_jump_promotion = 0;
2686 if (*input_line_pointer == ','
29b0f896 2687 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b 2688 {
d02603dc
NC		 2689 char *string;
2690 char e;
2691
2692 ++input_line_pointer;
2693 e = get_symbol_name (&string);
fddf5b5b
AM		 2694
2695 if (strcmp (string, "nojumps") == 0)
2696 no_cond_jump_promotion = 1;
2697 else if (strcmp (string, "jumps") == 0)
2698 ;
2699 else
2700 as_bad (_("no such architecture modifier: `%s'"), string);
2701
d02603dc 2702 (void) restore_line_pointer (e);
fddf5b5b
AM		 2703 }
2704
e413e4e9
AM		 2705 demand_empty_rest_of_line ();
2706}
2707
8a9036a4
L		 2708enum bfd_architecture
2709i386_arch (void)
2710{
3632d14b 2711 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2712 {
2713 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2714 || flag_code != CODE_64BIT)
2715 as_fatal (_("Intel L1OM is 64bit ELF only"));
2716 return bfd_arch_l1om;
2717 }
7a9068fe
L		 2718 else if (cpu_arch_isa == PROCESSOR_K1OM)
2719 {
2720 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2721 || flag_code != CODE_64BIT)
2722 as_fatal (_("Intel K1OM is 64bit ELF only"));
2723 return bfd_arch_k1om;
2724 }
81486035
L		 2725 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2726 {
2727 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2728 || flag_code == CODE_64BIT)
2729 as_fatal (_("Intel MCU is 32bit ELF only"));
2730 return bfd_arch_iamcu;
2731 }
8a9036a4
L		 2732 else
2733 return bfd_arch_i386;
2734}
2735
b9d79e03 2736unsigned long
7016a5d5 2737i386_mach (void)
b9d79e03 2738{
351f65ca 2739 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2740 {
3632d14b 2741 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2742 {
351f65ca
L		 2743 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2744 || default_arch[6] != '\0')
8a9036a4
L		 2745 as_fatal (_("Intel L1OM is 64bit ELF only"));
2746 return bfd_mach_l1om;
2747 }
7a9068fe
L		 2748 else if (cpu_arch_isa == PROCESSOR_K1OM)
2749 {
2750 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2751 || default_arch[6] != '\0')
2752 as_fatal (_("Intel K1OM is 64bit ELF only"));
2753 return bfd_mach_k1om;
2754 }
351f65ca 2755 else if (default_arch[6] == '\0')
8a9036a4 2756 return bfd_mach_x86_64;
351f65ca
L		 2757 else
2758 return bfd_mach_x64_32;
8a9036a4 2759 }
5197d474
L		 2760 else if (!strcmp (default_arch, "i386")
2761 || !strcmp (default_arch, "iamcu"))
81486035
L		 2762 {
2763 if (cpu_arch_isa == PROCESSOR_IAMCU)
2764 {
2765 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2766 as_fatal (_("Intel MCU is 32bit ELF only"));
2767 return bfd_mach_i386_iamcu;
2768 }
2769 else
2770 return bfd_mach_i386_i386;
2771 }
b9d79e03 2772 else
2b5d6a91 2773 as_fatal (_("unknown architecture"));
b9d79e03 2774}
b9d79e03 2775\f
252b5132 2776void
7016a5d5 2777md_begin (void)
252b5132
RH		 2778{
2779 const char *hash_err;
2780
86fa6981
L		 2781 /* Support pseudo prefixes like {disp32}. */
2782 lex_type ['{'] = LEX_BEGIN_NAME;
2783
47926f60 2784 /* Initialize op_hash hash table. */
252b5132
RH		 2785 op_hash = hash_new ();
2786
2787 {
d3ce72d0 2788 const insn_template *optab;
29b0f896 2789 templates *core_optab;
252b5132 2790
47926f60
KH		 2791 /* Setup for loop. */
2792 optab = i386_optab;
add39d23 2793 core_optab = XNEW (templates);
252b5132
RH		 2794 core_optab->start = optab;
2795
2796 while (1)
2797 {
2798 ++optab;
2799 if (optab->name == NULL
2800 || strcmp (optab->name, (optab - 1)->name) != 0)
2801 {
2802 /* different name --> ship out current template list;
47926f60 2803 add to hash table; & begin anew. */
252b5132
RH		 2804 core_optab->end = optab;
2805 hash_err = hash_insert (op_hash,
2806 (optab - 1)->name,
5a49b8ac 2807 (void *) core_optab);
252b5132
RH		 2808 if (hash_err)
2809 {
b37df7c4 2810 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2811 (optab - 1)->name,
2812 hash_err);
2813 }
2814 if (optab->name == NULL)
2815 break;
add39d23 2816 core_optab = XNEW (templates);
252b5132
RH		 2817 core_optab->start = optab;
2818 }
2819 }
2820 }
2821
47926f60 2822 /* Initialize reg_hash hash table. */
252b5132
RH		 2823 reg_hash = hash_new ();
2824 {
29b0f896 2825 const reg_entry *regtab;
c3fe08fa 2826 unsigned int regtab_size = i386_regtab_size;
252b5132 2827
c3fe08fa 2828 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2829 {
5a49b8ac 2830 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2831 if (hash_err)
b37df7c4 2832 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2833 regtab->reg_name,
2834 hash_err);
252b5132
RH		 2835 }
2836 }
2837
47926f60 2838 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2839 {
29b0f896
AM		 2840 int c;
2841 char *p;
252b5132
RH		 2842
2843 for (c = 0; c < 256; c++)
2844 {
3882b010 2845 if (ISDIGIT (c))
252b5132
RH		 2846 {
2847 digit_chars[c] = c;
2848 mnemonic_chars[c] = c;
2849 register_chars[c] = c;
2850 operand_chars[c] = c;
2851 }
3882b010 2852 else if (ISLOWER (c))
252b5132
RH		 2853 {
2854 mnemonic_chars[c] = c;
2855 register_chars[c] = c;
2856 operand_chars[c] = c;
2857 }
3882b010 2858 else if (ISUPPER (c))
252b5132 2859 {
3882b010 2860 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2861 register_chars[c] = mnemonic_chars[c];
2862 operand_chars[c] = c;
2863 }
43234a1e 2864 else if (c == '{' || c == '}')
86fa6981
L		 2865 {
2866 mnemonic_chars[c] = c;
2867 operand_chars[c] = c;
2868 }
252b5132 2869
3882b010 2870 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2871 identifier_chars[c] = c;
2872 else if (c >= 128)
2873 {
2874 identifier_chars[c] = c;
2875 operand_chars[c] = c;
2876 }
2877 }
2878
2879#ifdef LEX_AT
2880 identifier_chars['@'] = '@';
32137342
NC		 2881#endif
2882#ifdef LEX_QM
2883 identifier_chars['?'] = '?';
2884 operand_chars['?'] = '?';
252b5132 2885#endif
252b5132 2886 digit_chars['-'] = '-';
c0f3af97 2887 mnemonic_chars['_'] = '_';
791fe849 2888 mnemonic_chars['-'] = '-';
0003779b 2889 mnemonic_chars['.'] = '.';
252b5132
RH		 2890 identifier_chars['_'] = '_';
2891 identifier_chars['.'] = '.';
2892
2893 for (p = operand_special_chars; *p != '\0'; p++)
2894 operand_chars[(unsigned char) *p] = *p;
2895 }
2896
a4447b93
RH		 2897 if (flag_code == CODE_64BIT)
2898 {
ca19b261
KT		 2899#if defined (OBJ_COFF) && defined (TE_PE)
2900 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2901 ? 32 : 16);
2902#else
a4447b93 2903 x86_dwarf2_return_column = 16;
ca19b261 2904#endif
61ff971f 2905 x86_cie_data_alignment = -8;
a4447b93
RH		 2906 }
2907 else
2908 {
2909 x86_dwarf2_return_column = 8;
2910 x86_cie_data_alignment = -4;
2911 }
252b5132
RH		 2912}
2913
2914void
e3bb37b5 2915i386_print_statistics (FILE *file)
252b5132
RH		 2916{
2917 hash_print_statistics (file, "i386 opcode", op_hash);
2918 hash_print_statistics (file, "i386 register", reg_hash);
2919}
2920\f
252b5132
RH		 2921#ifdef DEBUG386
2922
ce8a8b2f 2923/* Debugging routines for md_assemble. */
d3ce72d0 2924static void pte (insn_template *);
40fb9820 2925static void pt (i386_operand_type);
e3bb37b5
L		 2926static void pe (expressionS *);
2927static void ps (symbolS *);
252b5132
RH		 2928
2929static void
e3bb37b5 2930pi (char *line, i386_insn *x)
252b5132 2931{
09137c09 2932 unsigned int j;
252b5132
RH		 2933
2934 fprintf (stdout, "%s: template ", line);
2935 pte (&x->tm);
09f131f2
JH		 2936 fprintf (stdout, " address: base %s index %s scale %x\n",
2937 x->base_reg ? x->base_reg->reg_name : "none",
2938 x->index_reg ? x->index_reg->reg_name : "none",
2939 x->log2_scale_factor);
2940 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2941 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2942 fprintf (stdout, " sib: base %x index %x scale %x\n",
2943 x->sib.base, x->sib.index, x->sib.scale);
2944 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2945 (x->rex & REX_W) != 0,
2946 (x->rex & REX_R) != 0,
2947 (x->rex & REX_X) != 0,
2948 (x->rex & REX_B) != 0);
09137c09 2949 for (j = 0; j < x->operands; j++)
252b5132 2950 {
09137c09
SP		 2951 fprintf (stdout, " #%d: ", j + 1);
2952 pt (x->types[j]);
252b5132 2953 fprintf (stdout, "\n");
dc821c5f 2954 if (x->types[j].bitfield.reg
09137c09 2955 || x->types[j].bitfield.regmmx
1b54b8d7 2956 || x->types[j].bitfield.regsimd
09137c09
SP		 2957 || x->types[j].bitfield.sreg2
2958 || x->types[j].bitfield.sreg3
2959 || x->types[j].bitfield.control
2960 || x->types[j].bitfield.debug
2961 || x->types[j].bitfield.test)
2962 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2963 if (operand_type_check (x->types[j], imm))
2964 pe (x->op[j].imms);
2965 if (operand_type_check (x->types[j], disp))
2966 pe (x->op[j].disps);
252b5132
RH		 2967 }
2968}
2969
2970static void
d3ce72d0 2971pte (insn_template *t)
252b5132 2972{
09137c09 2973 unsigned int j;
252b5132 2974 fprintf (stdout, " %d operands ", t->operands);
47926f60 2975 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2976 if (t->extension_opcode != None)
2977 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2978 if (t->opcode_modifier.d)
252b5132 2979 fprintf (stdout, "D");
40fb9820 2980 if (t->opcode_modifier.w)
252b5132
RH		 2981 fprintf (stdout, "W");
2982 fprintf (stdout, "\n");
09137c09 2983 for (j = 0; j < t->operands; j++)
252b5132 2984 {
09137c09
SP		 2985 fprintf (stdout, " #%d type ", j + 1);
2986 pt (t->operand_types[j]);
252b5132
RH		 2987 fprintf (stdout, "\n");
2988 }
2989}
2990
2991static void
e3bb37b5 2992pe (expressionS *e)
252b5132 2993{
24eab124 2994 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2995 fprintf (stdout, " add_number %ld (%lx)\n",
2996 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2997 if (e->X_add_symbol)
2998 {
2999 fprintf (stdout, " add_symbol ");
3000 ps (e->X_add_symbol);
3001 fprintf (stdout, "\n");
3002 }
3003 if (e->X_op_symbol)
3004 {
3005 fprintf (stdout, " op_symbol ");
3006 ps (e->X_op_symbol);
3007 fprintf (stdout, "\n");
3008 }
3009}
3010
3011static void
e3bb37b5 3012ps (symbolS *s)
252b5132
RH		 3013{
3014 fprintf (stdout, "%s type %s%s",
3015 S_GET_NAME (s),
3016 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
3017 segment_name (S_GET_SEGMENT (s)));
3018}
3019
7b81dfbb 3020static struct type_name
252b5132 3021 {
40fb9820
L		 3022 i386_operand_type mask;
3023 const char *name;
252b5132 3024 }
7b81dfbb 3025const type_names[] =
252b5132 3026{
40fb9820
L		 3027 { OPERAND_TYPE_REG8, "r8" },
3028 { OPERAND_TYPE_REG16, "r16" },
3029 { OPERAND_TYPE_REG32, "r32" },
3030 { OPERAND_TYPE_REG64, "r64" },
3031 { OPERAND_TYPE_IMM8, "i8" },
3032 { OPERAND_TYPE_IMM8, "i8s" },
3033 { OPERAND_TYPE_IMM16, "i16" },
3034 { OPERAND_TYPE_IMM32, "i32" },
3035 { OPERAND_TYPE_IMM32S, "i32s" },
3036 { OPERAND_TYPE_IMM64, "i64" },
3037 { OPERAND_TYPE_IMM1, "i1" },
3038 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
3039 { OPERAND_TYPE_DISP8, "d8" },
3040 { OPERAND_TYPE_DISP16, "d16" },
3041 { OPERAND_TYPE_DISP32, "d32" },
3042 { OPERAND_TYPE_DISP32S, "d32s" },
3043 { OPERAND_TYPE_DISP64, "d64" },
3044 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
3045 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
3046 { OPERAND_TYPE_CONTROL, "control reg" },
3047 { OPERAND_TYPE_TEST, "test reg" },
3048 { OPERAND_TYPE_DEBUG, "debug reg" },
3049 { OPERAND_TYPE_FLOATREG, "FReg" },
3050 { OPERAND_TYPE_FLOATACC, "FAcc" },
3051 { OPERAND_TYPE_SREG2, "SReg2" },
3052 { OPERAND_TYPE_SREG3, "SReg3" },
3053 { OPERAND_TYPE_ACC, "Acc" },
3054 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
3055 { OPERAND_TYPE_REGMMX, "rMMX" },
3056 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 3057 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 3058 { OPERAND_TYPE_REGZMM, "rZMM" },
3059 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 3060 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 3061};
3062
3063static void
40fb9820 3064pt (i386_operand_type t)
252b5132 3065{
40fb9820 3066 unsigned int j;
c6fb90c8 3067 i386_operand_type a;
252b5132 3068
40fb9820 3069 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 3070 {
3071 a = operand_type_and (t, type_names[j].mask);
0349dc08 3072 if (!operand_type_all_zero (&a))
c6fb90c8
L		 3073 fprintf (stdout, "%s, ", type_names[j].name);
3074 }
252b5132
RH		 3075 fflush (stdout);
3076}
3077
3078#endif /* DEBUG386 */
3079\f
252b5132 3080static bfd_reloc_code_real_type
3956db08 3081reloc (unsigned int size,
64e74474
AM		 3082 int pcrel,
3083 int sign,
3084 bfd_reloc_code_real_type other)
252b5132 3085{
47926f60 3086 if (other != NO_RELOC)
3956db08 3087 {
91d6fa6a 3088 reloc_howto_type *rel;
3956db08
JB		 3089
3090 if (size == 8)
3091 switch (other)
3092 {
64e74474
AM		 3093 case BFD_RELOC_X86_64_GOT32:
3094 return BFD_RELOC_X86_64_GOT64;
3095 break;
553d1284
L		 3096 case BFD_RELOC_X86_64_GOTPLT64:
3097 return BFD_RELOC_X86_64_GOTPLT64;
3098 break;
64e74474
AM		 3099 case BFD_RELOC_X86_64_PLTOFF64:
3100 return BFD_RELOC_X86_64_PLTOFF64;
3101 break;
3102 case BFD_RELOC_X86_64_GOTPC32:
3103 other = BFD_RELOC_X86_64_GOTPC64;
3104 break;
3105 case BFD_RELOC_X86_64_GOTPCREL:
3106 other = BFD_RELOC_X86_64_GOTPCREL64;
3107 break;
3108 case BFD_RELOC_X86_64_TPOFF32:
3109 other = BFD_RELOC_X86_64_TPOFF64;
3110 break;
3111 case BFD_RELOC_X86_64_DTPOFF32:
3112 other = BFD_RELOC_X86_64_DTPOFF64;
3113 break;
3114 default:
3115 break;
3956db08 3116 }
e05278af 3117
8ce3d284 3118#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 3119 if (other == BFD_RELOC_SIZE32)
3120 {
3121 if (size == 8)
1ab668bf 3122 other = BFD_RELOC_SIZE64;
8fd4256d 3123 if (pcrel)
1ab668bf
AM		 3124 {
3125 as_bad (_("there are no pc-relative size relocations"));
3126 return NO_RELOC;
3127 }
8fd4256d 3128 }
8ce3d284 3129#endif
8fd4256d 3130
e05278af 3131 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 3132 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 3133 sign = -1;
3134
91d6fa6a
NC		 3135 rel = bfd_reloc_type_lookup (stdoutput, other);
3136 if (!rel)
3956db08 3137 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 3138 else if (size != bfd_get_reloc_size (rel))
3956db08 3139 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 3140 bfd_get_reloc_size (rel),
3956db08 3141 size);
91d6fa6a 3142 else if (pcrel && !rel->pc_relative)
3956db08 3143 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 3144 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 3145 && !sign)
91d6fa6a 3146 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 3147 && sign > 0))
3956db08
JB		 3148 as_bad (_("relocated field and relocation type differ in signedness"));
3149 else
3150 return other;
3151 return NO_RELOC;
3152 }
252b5132
RH		 3153
3154 if (pcrel)
3155 {
3e73aa7c 3156 if (!sign)
3956db08 3157 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 3158 switch (size)
3159 {
3160 case 1: return BFD_RELOC_8_PCREL;
3161 case 2: return BFD_RELOC_16_PCREL;
d258b828 3162 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 3163 case 8: return BFD_RELOC_64_PCREL;
252b5132 3164 }
3956db08 3165 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 3166 }
3167 else
3168 {
3956db08 3169 if (sign > 0)
e5cb08ac 3170 switch (size)
3e73aa7c
JH		 3171 {
3172 case 4: return BFD_RELOC_X86_64_32S;
3173 }
3174 else
3175 switch (size)
3176 {
3177 case 1: return BFD_RELOC_8;
3178 case 2: return BFD_RELOC_16;
3179 case 4: return BFD_RELOC_32;
3180 case 8: return BFD_RELOC_64;
3181 }
3956db08
JB		 3182 as_bad (_("cannot do %s %u byte relocation"),
3183 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 3184 }
3185
0cc9e1d3 3186 return NO_RELOC;
252b5132
RH		 3187}
3188
47926f60
KH		 3189/* Here we decide which fixups can be adjusted to make them relative to
3190 the beginning of the section instead of the symbol. Basically we need
3191 to make sure that the dynamic relocations are done correctly, so in
3192 some cases we force the original symbol to be used. */
3193
252b5132 3194int
e3bb37b5 3195tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 3196{
6d249963 3197#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 3198 if (!IS_ELF)
31312f95
AM		 3199 return 1;
3200
a161fe53
AM		 3201 /* Don't adjust pc-relative references to merge sections in 64-bit
3202 mode. */
3203 if (use_rela_relocations
3204 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3205 && fixP->fx_pcrel)
252b5132 3206 return 0;
31312f95 3207
8d01d9a9
AJ		 3208 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3209 and changed later by validate_fix. */
3210 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3211 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3212 return 0;
3213
8fd4256d
L		 3214 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3215 for size relocations. */
3216 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3217 || fixP->fx_r_type == BFD_RELOC_SIZE64
3218 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 3219 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3220 || fixP->fx_r_type == BFD_RELOC_386_GOT32
02a86693 3221 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
13ae64f3
JJ		 3222 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3223 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3224 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3225 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 3226 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3227 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 3228 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3229 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 3230 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3231 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 3232 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3233 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 3234 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
56ceb5b5
L		 3235 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3236 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
bffbf940
JJ		 3237 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3238 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3239 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 3240 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 3241 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3242 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 3243 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3244 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 3245 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3246 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 3247 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3248 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3249 return 0;
31312f95 3250#endif
252b5132
RH		 3251 return 1;
3252}
252b5132 3253
b4cac588 3254static int
e3bb37b5 3255intel_float_operand (const char *mnemonic)
252b5132 3256{
9306ca4a
JB		 3257 /* Note that the value returned is meaningful only for opcodes with (memory)
3258 operands, hence the code here is free to improperly handle opcodes that
3259 have no operands (for better performance and smaller code). */
3260
3261 if (mnemonic[0] != 'f')
3262 return 0; /* non-math */
3263
3264 switch (mnemonic[1])
3265 {
3266 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3267 the fs segment override prefix not currently handled because no
3268 call path can make opcodes without operands get here */
3269 case 'i':
3270 return 2 /* integer op */;
3271 case 'l':
3272 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3273 return 3; /* fldcw/fldenv */
3274 break;
3275 case 'n':
3276 if (mnemonic[2] != 'o' /* fnop */)
3277 return 3; /* non-waiting control op */
3278 break;
3279 case 'r':
3280 if (mnemonic[2] == 's')
3281 return 3; /* frstor/frstpm */
3282 break;
3283 case 's':
3284 if (mnemonic[2] == 'a')
3285 return 3; /* fsave */
3286 if (mnemonic[2] == 't')
3287 {
3288 switch (mnemonic[3])
3289 {
3290 case 'c': /* fstcw */
3291 case 'd': /* fstdw */
3292 case 'e': /* fstenv */
3293 case 's': /* fsts[gw] */
3294 return 3;
3295 }
3296 }
3297 break;
3298 case 'x':
3299 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3300 return 0; /* fxsave/fxrstor are not really math ops */
3301 break;
3302 }
252b5132 3303
9306ca4a 3304 return 1;
252b5132
RH		 3305}
3306
c0f3af97
L		 3307/* Build the VEX prefix. */
3308
3309static void
d3ce72d0 3310build_vex_prefix (const insn_template *t)
c0f3af97
L		 3311{
3312 unsigned int register_specifier;
3313 unsigned int implied_prefix;
3314 unsigned int vector_length;
3315
3316 /* Check register specifier. */
3317 if (i.vex.register_specifier)
43234a1e
L		 3318 {
3319 register_specifier =
3320 ~register_number (i.vex.register_specifier) & 0xf;
3321 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3322 }
c0f3af97
L		 3323 else
3324 register_specifier = 0xf;
3325
33eaf5de 3326 /* Use 2-byte VEX prefix by swapping destination and source
fa99fab2 3327 operand. */
86fa6981
L		 3328 if (i.vec_encoding != vex_encoding_vex3
3329 && i.dir_encoding == dir_encoding_default
fa99fab2 3330 && i.operands == i.reg_operands
7f399153 3331 && i.tm.opcode_modifier.vexopcode == VEX0F
86fa6981 3332 && i.tm.opcode_modifier.load
fa99fab2
L		 3333 && i.rex == REX_B)
3334 {
3335 unsigned int xchg = i.operands - 1;
3336 union i386_op temp_op;
3337 i386_operand_type temp_type;
3338
3339 temp_type = i.types[xchg];
3340 i.types[xchg] = i.types[0];
3341 i.types[0] = temp_type;
3342 temp_op = i.op[xchg];
3343 i.op[xchg] = i.op[0];
3344 i.op[0] = temp_op;
3345
9c2799c2 3346 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3347
3348 i.rex = REX_R;
3349 xchg = i.rm.regmem;
3350 i.rm.regmem = i.rm.reg;
3351 i.rm.reg = xchg;
3352
3353 /* Use the next insn. */
3354 i.tm = t[1];
3355 }
3356
539f890d
L		 3357 if (i.tm.opcode_modifier.vex == VEXScalar)
3358 vector_length = avxscalar;
10c17abd
JB		 3359 else if (i.tm.opcode_modifier.vex == VEX256)
3360 vector_length = 1;
539f890d 3361 else
10c17abd
JB		 3362 {
3363 unsigned int op;
3364
3365 vector_length = 0;
3366 for (op = 0; op < t->operands; ++op)
3367 if (t->operand_types[op].bitfield.xmmword
3368 && t->operand_types[op].bitfield.ymmword
3369 && i.types[op].bitfield.ymmword)
3370 {
3371 vector_length = 1;
3372 break;
3373 }
3374 }
c0f3af97
L		 3375
3376 switch ((i.tm.base_opcode >> 8) & 0xff)
3377 {
3378 case 0:
3379 implied_prefix = 0;
3380 break;
3381 case DATA_PREFIX_OPCODE:
3382 implied_prefix = 1;
3383 break;
3384 case REPE_PREFIX_OPCODE:
3385 implied_prefix = 2;
3386 break;
3387 case REPNE_PREFIX_OPCODE:
3388 implied_prefix = 3;
3389 break;
3390 default:
3391 abort ();
3392 }
3393
3394 /* Use 2-byte VEX prefix if possible. */
86fa6981
L		 3395 if (i.vec_encoding != vex_encoding_vex3
3396 && i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3397 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3398 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3399 {
3400 /* 2-byte VEX prefix. */
3401 unsigned int r;
3402
3403 i.vex.length = 2;
3404 i.vex.bytes[0] = 0xc5;
3405
3406 /* Check the REX.R bit. */
3407 r = (i.rex & REX_R) ? 0 : 1;
3408 i.vex.bytes[1] = (r << 7
3409 | register_specifier << 3
3410 | vector_length << 2
3411 | implied_prefix);
3412 }
3413 else
3414 {
3415 /* 3-byte VEX prefix. */
3416 unsigned int m, w;
3417
f88c9eb0 3418 i.vex.length = 3;
f88c9eb0 3419
7f399153 3420 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3421 {
7f399153
L		 3422 case VEX0F:
3423 m = 0x1;
80de6e00 3424 i.vex.bytes[0] = 0xc4;
7f399153
L		 3425 break;
3426 case VEX0F38:
3427 m = 0x2;
80de6e00 3428 i.vex.bytes[0] = 0xc4;
7f399153
L		 3429 break;
3430 case VEX0F3A:
3431 m = 0x3;
80de6e00 3432 i.vex.bytes[0] = 0xc4;
7f399153
L		 3433 break;
3434 case XOP08:
5dd85c99
SP		 3435 m = 0x8;
3436 i.vex.bytes[0] = 0x8f;
7f399153
L		 3437 break;
3438 case XOP09:
f88c9eb0
SP		 3439 m = 0x9;
3440 i.vex.bytes[0] = 0x8f;
7f399153
L		 3441 break;
3442 case XOP0A:
f88c9eb0
SP		 3443 m = 0xa;
3444 i.vex.bytes[0] = 0x8f;
7f399153
L		 3445 break;
3446 default:
3447 abort ();
f88c9eb0 3448 }
c0f3af97 3449
c0f3af97
L		 3450 /* The high 3 bits of the second VEX byte are 1's compliment
3451 of RXB bits from REX. */
3452 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3453
3454 /* Check the REX.W bit. */
3455 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3456 if (i.tm.opcode_modifier.vexw == VEXW1)
3457 w = 1;
c0f3af97
L		 3458
3459 i.vex.bytes[2] = (w << 7
3460 | register_specifier << 3
3461 | vector_length << 2
3462 | implied_prefix);
3463 }
3464}
3465
e771e7c9
JB		 3466static INLINE bfd_boolean
3467is_evex_encoding (const insn_template *t)
3468{
7091c612 3469 return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift
e771e7c9
JB		 3470 || t->opcode_modifier.broadcast || t->opcode_modifier.masking
3471 || t->opcode_modifier.staticrounding || t->opcode_modifier.sae;
3472}
3473
43234a1e
L		 3474/* Build the EVEX prefix. */
3475
3476static void
3477build_evex_prefix (void)
3478{
3479 unsigned int register_specifier;
3480 unsigned int implied_prefix;
3481 unsigned int m, w;
3482 rex_byte vrex_used = 0;
3483
3484 /* Check register specifier. */
3485 if (i.vex.register_specifier)
3486 {
3487 gas_assert ((i.vrex & REX_X) == 0);
3488
3489 register_specifier = i.vex.register_specifier->reg_num;
3490 if ((i.vex.register_specifier->reg_flags & RegRex))
3491 register_specifier += 8;
3492 /* The upper 16 registers are encoded in the fourth byte of the
3493 EVEX prefix. */
3494 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3495 i.vex.bytes[3] = 0x8;
3496 register_specifier = ~register_specifier & 0xf;
3497 }
3498 else
3499 {
3500 register_specifier = 0xf;
3501
3502 /* Encode upper 16 vector index register in the fourth byte of
3503 the EVEX prefix. */
3504 if (!(i.vrex & REX_X))
3505 i.vex.bytes[3] = 0x8;
3506 else
3507 vrex_used |= REX_X;
3508 }
3509
3510 switch ((i.tm.base_opcode >> 8) & 0xff)
3511 {
3512 case 0:
3513 implied_prefix = 0;
3514 break;
3515 case DATA_PREFIX_OPCODE:
3516 implied_prefix = 1;
3517 break;
3518 case REPE_PREFIX_OPCODE:
3519 implied_prefix = 2;
3520 break;
3521 case REPNE_PREFIX_OPCODE:
3522 implied_prefix = 3;
3523 break;
3524 default:
3525 abort ();
3526 }
3527
3528 /* 4 byte EVEX prefix. */
3529 i.vex.length = 4;
3530 i.vex.bytes[0] = 0x62;
3531
3532 /* mmmm bits. */
3533 switch (i.tm.opcode_modifier.vexopcode)
3534 {
3535 case VEX0F:
3536 m = 1;
3537 break;
3538 case VEX0F38:
3539 m = 2;
3540 break;
3541 case VEX0F3A:
3542 m = 3;
3543 break;
3544 default:
3545 abort ();
3546 break;
3547 }
3548
3549 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3550 bits from REX. */
3551 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3552
3553 /* The fifth bit of the second EVEX byte is 1's compliment of the
3554 REX_R bit in VREX. */
3555 if (!(i.vrex & REX_R))
3556 i.vex.bytes[1] |= 0x10;
3557 else
3558 vrex_used |= REX_R;
3559
3560 if ((i.reg_operands + i.imm_operands) == i.operands)
3561 {
3562 /* When all operands are registers, the REX_X bit in REX is not
3563 used. We reuse it to encode the upper 16 registers, which is
3564 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3565 as 1's compliment. */
3566 if ((i.vrex & REX_B))
3567 {
3568 vrex_used |= REX_B;
3569 i.vex.bytes[1] &= ~0x40;
3570 }
3571 }
3572
3573 /* EVEX instructions shouldn't need the REX prefix. */
3574 i.vrex &= ~vrex_used;
3575 gas_assert (i.vrex == 0);
3576
3577 /* Check the REX.W bit. */
3578 w = (i.rex & REX_W) ? 1 : 0;
3579 if (i.tm.opcode_modifier.vexw)
3580 {
3581 if (i.tm.opcode_modifier.vexw == VEXW1)
3582 w = 1;
3583 }
3584 /* If w is not set it means we are dealing with WIG instruction. */
3585 else if (!w)
3586 {
3587 if (evexwig == evexw1)
3588 w = 1;
3589 }
3590
3591 /* Encode the U bit. */
3592 implied_prefix |= 0x4;
3593
3594 /* The third byte of the EVEX prefix. */
3595 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3596
3597 /* The fourth byte of the EVEX prefix. */
3598 /* The zeroing-masking bit. */
3599 if (i.mask && i.mask->zeroing)
3600 i.vex.bytes[3] |= 0x80;
3601
3602 /* Don't always set the broadcast bit if there is no RC. */
3603 if (!i.rounding)
3604 {
3605 /* Encode the vector length. */
3606 unsigned int vec_length;
3607
e771e7c9
JB		 3608 if (!i.tm.opcode_modifier.evex
3609 || i.tm.opcode_modifier.evex == EVEXDYN)
3610 {
3611 unsigned int op;
3612
3613 vec_length = 0;
3614 for (op = 0; op < i.tm.operands; ++op)
3615 if (i.tm.operand_types[op].bitfield.xmmword
3616 + i.tm.operand_types[op].bitfield.ymmword
3617 + i.tm.operand_types[op].bitfield.zmmword > 1)
3618 {
3619 if (i.types[op].bitfield.zmmword)
3620 i.tm.opcode_modifier.evex = EVEX512;
3621 else if (i.types[op].bitfield.ymmword)
3622 i.tm.opcode_modifier.evex = EVEX256;
3623 else if (i.types[op].bitfield.xmmword)
3624 i.tm.opcode_modifier.evex = EVEX128;
625cbd7a
JB		 3625 else if (i.broadcast && (int) op == i.broadcast->operand)
3626 {
3627 switch ((i.tm.operand_types[op].bitfield.dword ? 4 : 8)
3628 * i.broadcast->type)
3629 {
3630 case 64:
3631 i.tm.opcode_modifier.evex = EVEX512;
3632 break;
3633 case 32:
3634 i.tm.opcode_modifier.evex = EVEX256;
3635 break;
3636 case 16:
3637 i.tm.opcode_modifier.evex = EVEX128;
3638 break;
3639 default:
3640 continue;
3641 }
3642 }
e771e7c9
JB		 3643 continue;
3644 break;
3645 }
3646 }
3647
43234a1e
L		 3648 switch (i.tm.opcode_modifier.evex)
3649 {
3650 case EVEXLIG: /* LL' is ignored */
3651 vec_length = evexlig << 5;
3652 break;
3653 case EVEX128:
3654 vec_length = 0 << 5;
3655 break;
3656 case EVEX256:
3657 vec_length = 1 << 5;
3658 break;
3659 case EVEX512:
3660 vec_length = 2 << 5;
3661 break;
3662 default:
3663 abort ();
3664 break;
3665 }
3666 i.vex.bytes[3] |= vec_length;
3667 /* Encode the broadcast bit. */
3668 if (i.broadcast)
3669 i.vex.bytes[3] |= 0x10;
3670 }
3671 else
3672 {
3673 if (i.rounding->type != saeonly)
3674 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3675 else
d3d3c6db 3676 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3677 }
3678
3679 if (i.mask && i.mask->mask)
3680 i.vex.bytes[3] |= i.mask->mask->reg_num;
3681}
3682
65da13b5
L		 3683static void
3684process_immext (void)
3685{
3686 expressionS *exp;
3687
4c692bc7
JB		 3688 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3689 && i.operands > 0)
65da13b5 3690 {
4c692bc7
JB		 3691 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3692 with an opcode suffix which is coded in the same place as an
3693 8-bit immediate field would be.
3694 Here we check those operands and remove them afterwards. */
65da13b5
L		 3695 unsigned int x;
3696
3697 for (x = 0; x < i.operands; x++)
4c692bc7 3698 if (register_number (i.op[x].regs) != x)
65da13b5 3699 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3700 register_prefix, i.op[x].regs->reg_name, x + 1,
3701 i.tm.name);
3702
3703 i.operands = 0;
65da13b5
L		 3704 }
3705
9916071f
AP		 3706 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3707 {
3708 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3709 suffix which is coded in the same place as an 8-bit immediate
3710 field would be.
3711 Here we check those operands and remove them afterwards. */
3712 unsigned int x;
3713
3714 if (i.operands != 3)
3715 abort();
3716
3717 for (x = 0; x < 2; x++)
3718 if (register_number (i.op[x].regs) != x)
3719 goto bad_register_operand;
3720
3721 /* Check for third operand for mwaitx/monitorx insn. */
3722 if (register_number (i.op[x].regs)
3723 != (x + (i.tm.extension_opcode == 0xfb)))
3724 {
3725bad_register_operand:
3726 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3727 register_prefix, i.op[x].regs->reg_name, x+1,
3728 i.tm.name);
3729 }
3730
3731 i.operands = 0;
3732 }
3733
c0f3af97 3734 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3735 which is coded in the same place as an 8-bit immediate field
3736 would be. Here we fake an 8-bit immediate operand from the
3737 opcode suffix stored in tm.extension_opcode.
3738
c1e679ec 3739 AVX instructions also use this encoding, for some of
c0f3af97 3740 3 argument instructions. */
65da13b5 3741
43234a1e 3742 gas_assert (i.imm_operands <= 1
7ab9ffdd 3743 && (i.operands <= 2
43234a1e 3744 || ((i.tm.opcode_modifier.vex
e771e7c9
JB		 3745 || i.tm.opcode_modifier.vexopcode
3746 || is_evex_encoding (&i.tm))
7ab9ffdd 3747 && i.operands <= 4)));
65da13b5
L		 3748
3749 exp = &im_expressions[i.imm_operands++];
3750 i.op[i.operands].imms = exp;
3751 i.types[i.operands] = imm8;
3752 i.operands++;
3753 exp->X_op = O_constant;
3754 exp->X_add_number = i.tm.extension_opcode;
3755 i.tm.extension_opcode = None;
3756}
3757
42164a71
L		 3758
3759static int
3760check_hle (void)
3761{
3762 switch (i.tm.opcode_modifier.hleprefixok)
3763 {
3764 default:
3765 abort ();
82c2def5 3766 case HLEPrefixNone:
165de32a
L		 3767 as_bad (_("invalid instruction `%s' after `%s'"),
3768 i.tm.name, i.hle_prefix);
42164a71 3769 return 0;
82c2def5 3770 case HLEPrefixLock:
42164a71
L		 3771 if (i.prefix[LOCK_PREFIX])
3772 return 1;
165de32a 3773 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3774 return 0;
82c2def5 3775 case HLEPrefixAny:
42164a71 3776 return 1;
82c2def5 3777 case HLEPrefixRelease:
42164a71
L		 3778 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3779 {
3780 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3781 i.tm.name);
3782 return 0;
3783 }
3784 if (i.mem_operands == 0
3785 || !operand_type_check (i.types[i.operands - 1], anymem))
3786 {
3787 as_bad (_("memory destination needed for instruction `%s'"
3788 " after `xrelease'"), i.tm.name);
3789 return 0;
3790 }
3791 return 1;
3792 }
3793}
3794
b6f8c7c4
L		 3795/* Try the shortest encoding by shortening operand size. */
3796
3797static void
3798optimize_encoding (void)
3799{
3800 int j;
3801
3802 if (optimize_for_space
3803 && i.reg_operands == 1
3804 && i.imm_operands == 1
3805 && !i.types[1].bitfield.byte
3806 && i.op[0].imms->X_op == O_constant
3807 && fits_in_imm7 (i.op[0].imms->X_add_number)
3808 && ((i.tm.base_opcode == 0xa8
3809 && i.tm.extension_opcode == None)
3810 || (i.tm.base_opcode == 0xf6
3811 && i.tm.extension_opcode == 0x0)))
3812 {
3813 /* Optimize: -Os:
3814 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
3815 */
3816 unsigned int base_regnum = i.op[1].regs->reg_num;
3817 if (flag_code == CODE_64BIT || base_regnum < 4)
3818 {
3819 i.types[1].bitfield.byte = 1;
3820 /* Ignore the suffix. */
3821 i.suffix = 0;
3822 if (base_regnum >= 4
3823 && !(i.op[1].regs->reg_flags & RegRex))
3824 {
3825 /* Handle SP, BP, SI and DI registers. */
3826 if (i.types[1].bitfield.word)
3827 j = 16;
3828 else if (i.types[1].bitfield.dword)
3829 j = 32;
3830 else
3831 j = 48;
3832 i.op[1].regs -= j;
3833 }
3834 }
3835 }
3836 else if (flag_code == CODE_64BIT
d3d50934
L		 3837 && ((i.types[1].bitfield.qword
3838 && i.reg_operands == 1
b6f8c7c4
L		 3839 && i.imm_operands == 1
3840 && i.op[0].imms->X_op == O_constant
3841 && ((i.tm.base_opcode == 0xb0
3842 && i.tm.extension_opcode == None
3843 && fits_in_unsigned_long (i.op[0].imms->X_add_number))
3844 || (fits_in_imm31 (i.op[0].imms->X_add_number)
3845 && (((i.tm.base_opcode == 0x24
3846 || i.tm.base_opcode == 0xa8)
3847 && i.tm.extension_opcode == None)
3848 || (i.tm.base_opcode == 0x80
3849 && i.tm.extension_opcode == 0x4)
3850 || ((i.tm.base_opcode == 0xf6
3851 || i.tm.base_opcode == 0xc6)
3852 && i.tm.extension_opcode == 0x0)))))
d3d50934
L		 3853 || (i.types[0].bitfield.qword
3854 && ((i.reg_operands == 2
3855 && i.op[0].regs == i.op[1].regs
3856 && ((i.tm.base_opcode == 0x30
3857 || i.tm.base_opcode == 0x28)
3858 && i.tm.extension_opcode == None))
3859 || (i.reg_operands == 1
3860 && i.operands == 1
3861 && i.tm.base_opcode == 0x30
3862 && i.tm.extension_opcode == None)))))
b6f8c7c4
L		 3863 {
3864 /* Optimize: -O:
3865 andq $imm31, %r64 -> andl $imm31, %r32
3866 testq $imm31, %r64 -> testl $imm31, %r32
3867 xorq %r64, %r64 -> xorl %r32, %r32
3868 subq %r64, %r64 -> subl %r32, %r32
3869 movq $imm31, %r64 -> movl $imm31, %r32
3870 movq $imm32, %r64 -> movl $imm32, %r32
3871 */
3872 i.tm.opcode_modifier.norex64 = 1;
3873 if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6)
3874 {
3875 /* Handle
3876 movq $imm31, %r64 -> movl $imm31, %r32
3877 movq $imm32, %r64 -> movl $imm32, %r32
3878 */
3879 i.tm.operand_types[0].bitfield.imm32 = 1;
3880 i.tm.operand_types[0].bitfield.imm32s = 0;
3881 i.tm.operand_types[0].bitfield.imm64 = 0;
3882 i.types[0].bitfield.imm32 = 1;
3883 i.types[0].bitfield.imm32s = 0;
3884 i.types[0].bitfield.imm64 = 0;
3885 i.types[1].bitfield.dword = 1;
3886 i.types[1].bitfield.qword = 0;
3887 if (i.tm.base_opcode == 0xc6)
3888 {
3889 /* Handle
3890 movq $imm31, %r64 -> movl $imm31, %r32
3891 */
3892 i.tm.base_opcode = 0xb0;
3893 i.tm.extension_opcode = None;
3894 i.tm.opcode_modifier.shortform = 1;
3895 i.tm.opcode_modifier.modrm = 0;
3896 }
3897 }
3898 }
3899 else if (optimize > 1
3900 && i.reg_operands == 3
3901 && i.op[0].regs == i.op[1].regs
3902 && !i.types[2].bitfield.xmmword
3903 && (i.tm.opcode_modifier.vex
7a69eac3 3904 || ((!i.mask || i.mask->zeroing)
b6f8c7c4 3905 && !i.rounding
e771e7c9 3906 && is_evex_encoding (&i.tm)
80c34c38
L		 3907 && (i.vec_encoding != vex_encoding_evex
3908 || i.tm.cpu_flags.bitfield.cpuavx512vl
7091c612
JB		 3909 || (i.tm.operand_types[2].bitfield.zmmword
3910 && i.types[2].bitfield.ymmword)
0089dace 3911 || cpu_arch_isa_flags.bitfield.cpuavx512vl)))
b6f8c7c4
L		 3912 && ((i.tm.base_opcode == 0x55
3913 || i.tm.base_opcode == 0x6655
3914 || i.tm.base_opcode == 0x66df
3915 || i.tm.base_opcode == 0x57
3916 || i.tm.base_opcode == 0x6657
8305403a
L		 3917 || i.tm.base_opcode == 0x66ef
3918 || i.tm.base_opcode == 0x66f8
3919 || i.tm.base_opcode == 0x66f9
3920 || i.tm.base_opcode == 0x66fa
3921 || i.tm.base_opcode == 0x66fb)
b6f8c7c4
L		 3922 && i.tm.extension_opcode == None))
3923 {
3924 /* Optimize: -O2:
8305403a
L		 3925 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
3926 vpsubq and vpsubw:
b6f8c7c4
L		 3927 EVEX VOP %zmmM, %zmmM, %zmmN
3928 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3929 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3930 EVEX VOP %ymmM, %ymmM, %ymmN
3931 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
3932 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3933 VEX VOP %ymmM, %ymmM, %ymmN
3934 -> VEX VOP %xmmM, %xmmM, %xmmN
3935 VOP, one of vpandn and vpxor:
3936 VEX VOP %ymmM, %ymmM, %ymmN
3937 -> VEX VOP %xmmM, %xmmM, %xmmN
3938 VOP, one of vpandnd and vpandnq:
3939 EVEX VOP %zmmM, %zmmM, %zmmN
3940 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3941 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3942 EVEX VOP %ymmM, %ymmM, %ymmN
3943 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
3944 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3945 VOP, one of vpxord and vpxorq:
3946 EVEX VOP %zmmM, %zmmM, %zmmN
3947 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3948 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3949 EVEX VOP %ymmM, %ymmM, %ymmN
3950 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
3951 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
3952 */
e771e7c9 3953 if (is_evex_encoding (&i.tm))
b6f8c7c4 3954 {
0089dace 3955 if (i.vec_encoding == vex_encoding_evex)
b6f8c7c4
L		 3956 i.tm.opcode_modifier.evex = EVEX128;
3957 else
3958 {
3959 i.tm.opcode_modifier.vex = VEX128;
3960 i.tm.opcode_modifier.vexw = VEXW0;
3961 i.tm.opcode_modifier.evex = 0;
3962 }
3963 }
3964 else
3965 i.tm.opcode_modifier.vex = VEX128;
3966
3967 if (i.tm.opcode_modifier.vex)
3968 for (j = 0; j < 3; j++)
3969 {
3970 i.types[j].bitfield.xmmword = 1;
3971 i.types[j].bitfield.ymmword = 0;
3972 }
3973 }
3974}
3975
252b5132
RH		 3976/* This is the guts of the machine-dependent assembler. LINE points to a
3977 machine dependent instruction. This function is supposed to emit
3978 the frags/bytes it assembles to. */
3979
3980void
65da13b5 3981md_assemble (char *line)
252b5132 3982{
40fb9820 3983 unsigned int j;
83b16ac6 3984 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
d3ce72d0 3985 const insn_template *t;
252b5132 3986
47926f60 3987 /* Initialize globals. */
252b5132
RH		 3988 memset (&i, '\0', sizeof (i));
3989 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3990 i.reloc[j] = NO_RELOC;
252b5132
RH		 3991 memset (disp_expressions, '\0', sizeof (disp_expressions));
3992 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3993 save_stack_p = save_stack;
252b5132
RH		 3994
3995 /* First parse an instruction mnemonic & call i386_operand for the operands.
3996 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3997 start of a (possibly prefixed) mnemonic. */
252b5132 3998
29b0f896
AM		 3999 line = parse_insn (line, mnemonic);
4000 if (line == NULL)
4001 return;
83b16ac6 4002 mnem_suffix = i.suffix;
252b5132 4003
29b0f896 4004 line = parse_operands (line, mnemonic);
ee86248c 4005 this_operand = -1;
8325cc63
JB		 4006 xfree (i.memop1_string);
4007 i.memop1_string = NULL;
29b0f896
AM		 4008 if (line == NULL)
4009 return;
252b5132 4010
29b0f896
AM		 4011 /* Now we've parsed the mnemonic into a set of templates, and have the
4012 operands at hand. */
4013
4014 /* All intel opcodes have reversed operands except for "bound" and
4015 "enter". We also don't reverse intersegment "jmp" and "call"
4016 instructions with 2 immediate operands so that the immediate segment
050dfa73 4017 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 4018 if (intel_syntax
4019 && i.operands > 1
29b0f896 4020 && (strcmp (mnemonic, "bound") != 0)
30123838 4021 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 4022 && !(operand_type_check (i.types[0], imm)
4023 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 4024 swap_operands ();
4025
ec56d5c0
JB		 4026 /* The order of the immediates should be reversed
4027 for 2 immediates extrq and insertq instructions */
4028 if (i.imm_operands == 2
4029 && (strcmp (mnemonic, "extrq") == 0
4030 || strcmp (mnemonic, "insertq") == 0))
4031 swap_2_operands (0, 1);
4032
29b0f896
AM		 4033 if (i.imm_operands)
4034 optimize_imm ();
4035
b300c311
L		 4036 /* Don't optimize displacement for movabs since it only takes 64bit
4037 displacement. */
4038 if (i.disp_operands
a501d77e 4039 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 4040 && (flag_code != CODE_64BIT
4041 || strcmp (mnemonic, "movabs") != 0))
4042 optimize_disp ();
29b0f896
AM		 4043
4044 /* Next, we find a template that matches the given insn,
4045 making sure the overlap of the given operands types is consistent
4046 with the template operand types. */
252b5132 4047
83b16ac6 4048 if (!(t = match_template (mnem_suffix)))
29b0f896 4049 return;
252b5132 4050
7bab8ab5 4051 if (sse_check != check_none
81f8a913 4052 && !i.tm.opcode_modifier.noavx
6e3e5c9e 4053 && !i.tm.cpu_flags.bitfield.cpuavx
daf50ae7
L		 4054 && (i.tm.cpu_flags.bitfield.cpusse
4055 || i.tm.cpu_flags.bitfield.cpusse2
4056 || i.tm.cpu_flags.bitfield.cpusse3
4057 || i.tm.cpu_flags.bitfield.cpussse3
4058 || i.tm.cpu_flags.bitfield.cpusse4_1
6e3e5c9e
JB		 4059 || i.tm.cpu_flags.bitfield.cpusse4_2
4060 || i.tm.cpu_flags.bitfield.cpupclmul
4061 || i.tm.cpu_flags.bitfield.cpuaes
4062 || i.tm.cpu_flags.bitfield.cpugfni))
daf50ae7 4063 {
7bab8ab5 4064 (sse_check == check_warning
daf50ae7
L		 4065 ? as_warn
4066 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
4067 }
4068
321fd21e
L		 4069 /* Zap movzx and movsx suffix. The suffix has been set from
4070 "word ptr" or "byte ptr" on the source operand in Intel syntax
4071 or extracted from mnemonic in AT&T syntax. But we'll use
4072 the destination register to choose the suffix for encoding. */
4073 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 4074 {
321fd21e
L		 4075 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
4076 there is no suffix, the default will be byte extension. */
4077 if (i.reg_operands != 2
4078 && !i.suffix
7ab9ffdd 4079 && intel_syntax)
321fd21e
L		 4080 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4081
4082 i.suffix = 0;
cd61ebfe 4083 }
24eab124 4084
40fb9820 4085 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 4086 if (!add_prefix (FWAIT_OPCODE))
4087 return;
252b5132 4088
d5de92cf
L		 4089 /* Check if REP prefix is OK. */
4090 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
4091 {
4092 as_bad (_("invalid instruction `%s' after `%s'"),
4093 i.tm.name, i.rep_prefix);
4094 return;
4095 }
4096
c1ba0266
L		 4097 /* Check for lock without a lockable instruction. Destination operand
4098 must be memory unless it is xchg (0x86). */
c32fa91d
L		 4099 if (i.prefix[LOCK_PREFIX]
4100 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 4101 || i.mem_operands == 0
4102 || (i.tm.base_opcode != 0x86
4103 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 4104 {
4105 as_bad (_("expecting lockable instruction after `lock'"));
4106 return;
4107 }
4108
42164a71 4109 /* Check if HLE prefix is OK. */
165de32a 4110 if (i.hle_prefix && !check_hle ())
42164a71
L		 4111 return;
4112
7e8b059b
L		 4113 /* Check BND prefix. */
4114 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
4115 as_bad (_("expecting valid branch instruction after `bnd'"));
4116
04ef582a 4117 /* Check NOTRACK prefix. */
9fef80d6
L		 4118 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
4119 as_bad (_("expecting indirect branch instruction after `notrack'"));
04ef582a 4120
327e8c42
JB		 4121 if (i.tm.cpu_flags.bitfield.cpumpx)
4122 {
4123 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
4124 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
4125 else if (flag_code != CODE_16BIT
4126 ? i.prefix[ADDR_PREFIX]
4127 : i.mem_operands && !i.prefix[ADDR_PREFIX])
4128 as_bad (_("16-bit address isn't allowed in MPX instructions"));
4129 }
7e8b059b
L		 4130
4131 /* Insert BND prefix. */
76d3a78a
JB		 4132 if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok)
4133 {
4134 if (!i.prefix[BND_PREFIX])
4135 add_prefix (BND_PREFIX_OPCODE);
4136 else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE)
4137 {
4138 as_warn (_("replacing `rep'/`repe' prefix by `bnd'"));
4139 i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE;
4140 }
4141 }
7e8b059b 4142
29b0f896 4143 /* Check string instruction segment overrides. */
40fb9820 4144 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 4145 {
4146 if (!check_string ())
5dd0794d 4147 return;
fc0763e6 4148 i.disp_operands = 0;
29b0f896 4149 }
5dd0794d 4150
b6f8c7c4
L		 4151 if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize)
4152 optimize_encoding ();
4153
29b0f896
AM		 4154 if (!process_suffix ())
4155 return;
e413e4e9 4156
bc0844ae
L		 4157 /* Update operand types. */
4158 for (j = 0; j < i.operands; j++)
4159 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
4160
29b0f896
AM		 4161 /* Make still unresolved immediate matches conform to size of immediate
4162 given in i.suffix. */
4163 if (!finalize_imm ())
4164 return;
252b5132 4165
40fb9820 4166 if (i.types[0].bitfield.imm1)
29b0f896 4167 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 4168
9afe6eb8
L		 4169 /* We only need to check those implicit registers for instructions
4170 with 3 operands or less. */
4171 if (i.operands <= 3)
4172 for (j = 0; j < i.operands; j++)
4173 if (i.types[j].bitfield.inoutportreg
4174 || i.types[j].bitfield.shiftcount
1b54b8d7 4175 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
9afe6eb8 4176 i.reg_operands--;
40fb9820 4177
c0f3af97
L		 4178 /* ImmExt should be processed after SSE2AVX. */
4179 if (!i.tm.opcode_modifier.sse2avx
4180 && i.tm.opcode_modifier.immext)
65da13b5 4181 process_immext ();
252b5132 4182
29b0f896
AM		 4183 /* For insns with operands there are more diddles to do to the opcode. */
4184 if (i.operands)
4185 {
4186 if (!process_operands ())
4187 return;
4188 }
40fb9820 4189 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 4190 {
4191 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
4192 as_warn (_("translating to `%sp'"), i.tm.name);
4193 }
252b5132 4194
e771e7c9
JB		 4195 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.vexopcode
4196 || is_evex_encoding (&i.tm))
9e5e5283
L		 4197 {
4198 if (flag_code == CODE_16BIT)
4199 {
4200 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
4201 i.tm.name);
4202 return;
4203 }
c0f3af97 4204
9e5e5283
L		 4205 if (i.tm.opcode_modifier.vex)
4206 build_vex_prefix (t);
4207 else
4208 build_evex_prefix ();
4209 }
43234a1e 4210
5dd85c99
SP		 4211 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
4212 instructions may define INT_OPCODE as well, so avoid this corner
4213 case for those instructions that use MODRM. */
4214 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 4215 && !i.tm.opcode_modifier.modrm
4216 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 4217 {
4218 i.tm.base_opcode = INT3_OPCODE;
4219 i.imm_operands = 0;
4220 }
252b5132 4221
40fb9820
L		 4222 if ((i.tm.opcode_modifier.jump
4223 || i.tm.opcode_modifier.jumpbyte
4224 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 4225 && i.op[0].disps->X_op == O_constant)
4226 {
4227 /* Convert "jmp constant" (and "call constant") to a jump (call) to
4228 the absolute address given by the constant. Since ix86 jumps and
4229 calls are pc relative, we need to generate a reloc. */
4230 i.op[0].disps->X_add_symbol = &abs_symbol;
4231 i.op[0].disps->X_op = O_symbol;
4232 }
252b5132 4233
40fb9820 4234 if (i.tm.opcode_modifier.rex64)
161a04f6 4235 i.rex |= REX_W;
252b5132 4236
29b0f896
AM		 4237 /* For 8 bit registers we need an empty rex prefix. Also if the
4238 instruction already has a prefix, we need to convert old
4239 registers to new ones. */
773f551c 4240
dc821c5f 4241 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
29b0f896 4242 && (i.op[0].regs->reg_flags & RegRex64) != 0)
dc821c5f 4243 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
29b0f896 4244 && (i.op[1].regs->reg_flags & RegRex64) != 0)
dc821c5f
JB		 4245 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
4246 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
29b0f896
AM		 4247 && i.rex != 0))
4248 {
4249 int x;
726c5dcd 4250
29b0f896
AM		 4251 i.rex |= REX_OPCODE;
4252 for (x = 0; x < 2; x++)
4253 {
4254 /* Look for 8 bit operand that uses old registers. */
dc821c5f 4255 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
29b0f896 4256 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 4257 {
29b0f896
AM		 4258 /* In case it is "hi" register, give up. */
4259 if (i.op[x].regs->reg_num > 3)
a540244d 4260 as_bad (_("can't encode register '%s%s' in an "
4eed87de 4261 "instruction requiring REX prefix."),
a540244d 4262 register_prefix, i.op[x].regs->reg_name);
773f551c 4263
29b0f896
AM		 4264 /* Otherwise it is equivalent to the extended register.
4265 Since the encoding doesn't change this is merely
4266 cosmetic cleanup for debug output. */
4267
4268 i.op[x].regs = i.op[x].regs + 8;
773f551c 4269 }
29b0f896
AM		 4270 }
4271 }
773f551c 4272
6b6b6807
L		 4273 if (i.rex == 0 && i.rex_encoding)
4274 {
4275 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4276 that uses legacy register. If it is "hi" register, don't add
4277 the REX_OPCODE byte. */
4278 int x;
4279 for (x = 0; x < 2; x++)
4280 if (i.types[x].bitfield.reg
4281 && i.types[x].bitfield.byte
4282 && (i.op[x].regs->reg_flags & RegRex64) == 0
4283 && i.op[x].regs->reg_num > 3)
4284 {
4285 i.rex_encoding = FALSE;
4286 break;
4287 }
4288
4289 if (i.rex_encoding)
4290 i.rex = REX_OPCODE;
4291 }
4292
7ab9ffdd 4293 if (i.rex != 0)
29b0f896
AM		 4294 add_prefix (REX_OPCODE | i.rex);
4295
4296 /* We are ready to output the insn. */
4297 output_insn ();
4298}
4299
4300static char *
e3bb37b5 4301parse_insn (char *line, char *mnemonic)
29b0f896
AM		 4302{
4303 char *l = line;
4304 char *token_start = l;
4305 char *mnem_p;
5c6af06e 4306 int supported;
d3ce72d0 4307 const insn_template *t;
b6169b20 4308 char *dot_p = NULL;
29b0f896 4309
29b0f896
AM		 4310 while (1)
4311 {
4312 mnem_p = mnemonic;
4313 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
4314 {
b6169b20
L		 4315 if (*mnem_p == '.')
4316 dot_p = mnem_p;
29b0f896
AM		 4317 mnem_p++;
4318 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 4319 {
29b0f896
AM		 4320 as_bad (_("no such instruction: `%s'"), token_start);
4321 return NULL;
4322 }
4323 l++;
4324 }
4325 if (!is_space_char (*l)
4326 && *l != END_OF_INSN
e44823cf
JB		 4327 && (intel_syntax
4328 || (*l != PREFIX_SEPARATOR
4329 && *l != ',')))
29b0f896
AM		 4330 {
4331 as_bad (_("invalid character %s in mnemonic"),
4332 output_invalid (*l));
4333 return NULL;
4334 }
4335 if (token_start == l)
4336 {
e44823cf 4337 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 4338 as_bad (_("expecting prefix; got nothing"));
4339 else
4340 as_bad (_("expecting mnemonic; got nothing"));
4341 return NULL;
4342 }
45288df1 4343
29b0f896 4344 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 4345 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 4346
29b0f896
AM		 4347 if (*l != END_OF_INSN
4348 && (!is_space_char (*l) || l[1] != END_OF_INSN)
4349 && current_templates
40fb9820 4350 && current_templates->start->opcode_modifier.isprefix)
29b0f896 4351 {
c6fb90c8 4352 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 4353 {
4354 as_bad ((flag_code != CODE_64BIT
4355 ? _("`%s' is only supported in 64-bit mode")
4356 : _("`%s' is not supported in 64-bit mode")),
4357 current_templates->start->name);
4358 return NULL;
4359 }
29b0f896
AM		 4360 /* If we are in 16-bit mode, do not allow addr16 or data16.
4361 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 4362 if ((current_templates->start->opcode_modifier.size16
4363 || current_templates->start->opcode_modifier.size32)
29b0f896 4364 && flag_code != CODE_64BIT
40fb9820 4365 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 4366 ^ (flag_code == CODE_16BIT)))
4367 {
4368 as_bad (_("redundant %s prefix"),
4369 current_templates->start->name);
4370 return NULL;
45288df1 4371 }
86fa6981 4372 if (current_templates->start->opcode_length == 0)
29b0f896 4373 {
86fa6981
L		 4374 /* Handle pseudo prefixes. */
4375 switch (current_templates->start->base_opcode)
4376 {
4377 case 0x0:
4378 /* {disp8} */
4379 i.disp_encoding = disp_encoding_8bit;
4380 break;
4381 case 0x1:
4382 /* {disp32} */
4383 i.disp_encoding = disp_encoding_32bit;
4384 break;
4385 case 0x2:
4386 /* {load} */
4387 i.dir_encoding = dir_encoding_load;
4388 break;
4389 case 0x3:
4390 /* {store} */
4391 i.dir_encoding = dir_encoding_store;
4392 break;
4393 case 0x4:
4394 /* {vex2} */
4395 i.vec_encoding = vex_encoding_vex2;
4396 break;
4397 case 0x5:
4398 /* {vex3} */
4399 i.vec_encoding = vex_encoding_vex3;
4400 break;
4401 case 0x6:
4402 /* {evex} */
4403 i.vec_encoding = vex_encoding_evex;
4404 break;
6b6b6807
L		 4405 case 0x7:
4406 /* {rex} */
4407 i.rex_encoding = TRUE;
4408 break;
b6f8c7c4
L		 4409 case 0x8:
4410 /* {nooptimize} */
4411 i.no_optimize = TRUE;
4412 break;
86fa6981
L		 4413 default:
4414 abort ();
4415 }
4416 }
4417 else
4418 {
4419 /* Add prefix, checking for repeated prefixes. */
4e9ac44a 4420 switch (add_prefix (current_templates->start->base_opcode))
86fa6981 4421 {
4e9ac44a
L		 4422 case PREFIX_EXIST:
4423 return NULL;
4424 case PREFIX_DS:
d777820b 4425 if (current_templates->start->cpu_flags.bitfield.cpuibt)
4e9ac44a
L		 4426 i.notrack_prefix = current_templates->start->name;
4427 break;
4428 case PREFIX_REP:
4429 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4430 i.hle_prefix = current_templates->start->name;
4431 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4432 i.bnd_prefix = current_templates->start->name;
4433 else
4434 i.rep_prefix = current_templates->start->name;
4435 break;
4436 default:
4437 break;
86fa6981 4438 }
29b0f896
AM		 4439 }
4440 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4441 token_start = ++l;
4442 }
4443 else
4444 break;
4445 }
45288df1 4446
30a55f88 4447 if (!current_templates)
b6169b20 4448 {
f8a5c266
L		 4449 /* Check if we should swap operand or force 32bit displacement in
4450 encoding. */
30a55f88 4451 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
86fa6981 4452 i.dir_encoding = dir_encoding_store;
8d63c93e 4453 else if (mnem_p - 3 == dot_p
a501d77e
L		 4454 && dot_p[1] == 'd'
4455 && dot_p[2] == '8')
4456 i.disp_encoding = disp_encoding_8bit;
8d63c93e 4457 else if (mnem_p - 4 == dot_p
f8a5c266
L		 4458 && dot_p[1] == 'd'
4459 && dot_p[2] == '3'
4460 && dot_p[3] == '2')
a501d77e 4461 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 4462 else
4463 goto check_suffix;
4464 mnem_p = dot_p;
4465 *dot_p = '\0';
d3ce72d0 4466 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 4467 }
4468
29b0f896
AM		 4469 if (!current_templates)
4470 {
b6169b20 4471check_suffix:
29b0f896
AM		 4472 /* See if we can get a match by trimming off a suffix. */
4473 switch (mnem_p[-1])
4474 {
4475 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 4476 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4477 i.suffix = SHORT_MNEM_SUFFIX;
4478 else
1a0670f3 4479 /* Fall through. */
29b0f896
AM		 4480 case BYTE_MNEM_SUFFIX:
4481 case QWORD_MNEM_SUFFIX:
4482 i.suffix = mnem_p[-1];
4483 mnem_p[-1] = '\0';
d3ce72d0
NC		 4484 current_templates = (const templates *) hash_find (op_hash,
4485 mnemonic);
29b0f896
AM		 4486 break;
4487 case SHORT_MNEM_SUFFIX:
4488 case LONG_MNEM_SUFFIX:
4489 if (!intel_syntax)
4490 {
4491 i.suffix = mnem_p[-1];
4492 mnem_p[-1] = '\0';
d3ce72d0
NC		 4493 current_templates = (const templates *) hash_find (op_hash,
4494 mnemonic);
29b0f896
AM		 4495 }
4496 break;
252b5132 4497
29b0f896
AM		 4498 /* Intel Syntax. */
4499 case 'd':
4500 if (intel_syntax)
4501 {
9306ca4a 4502 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 4503 i.suffix = SHORT_MNEM_SUFFIX;
4504 else
4505 i.suffix = LONG_MNEM_SUFFIX;
4506 mnem_p[-1] = '\0';
d3ce72d0
NC		 4507 current_templates = (const templates *) hash_find (op_hash,
4508 mnemonic);
29b0f896
AM		 4509 }
4510 break;
4511 }
4512 if (!current_templates)
4513 {
4514 as_bad (_("no such instruction: `%s'"), token_start);
4515 return NULL;
4516 }
4517 }
252b5132 4518
40fb9820
L		 4519 if (current_templates->start->opcode_modifier.jump
4520 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 4521 {
4522 /* Check for a branch hint. We allow ",pt" and ",pn" for
4523 predict taken and predict not taken respectively.
4524 I'm not sure that branch hints actually do anything on loop
4525 and jcxz insns (JumpByte) for current Pentium4 chips. They
4526 may work in the future and it doesn't hurt to accept them
4527 now. */
4528 if (l[0] == ',' && l[1] == 'p')
4529 {
4530 if (l[2] == 't')
4531 {
4532 if (!add_prefix (DS_PREFIX_OPCODE))
4533 return NULL;
4534 l += 3;
4535 }
4536 else if (l[2] == 'n')
4537 {
4538 if (!add_prefix (CS_PREFIX_OPCODE))
4539 return NULL;
4540 l += 3;
4541 }
4542 }
4543 }
4544 /* Any other comma loses. */
4545 if (*l == ',')
4546 {
4547 as_bad (_("invalid character %s in mnemonic"),
4548 output_invalid (*l));
4549 return NULL;
4550 }
252b5132 4551
29b0f896 4552 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 4553 supported = 0;
4554 for (t = current_templates->start; t < current_templates->end; ++t)
4555 {
c0f3af97
L		 4556 supported |= cpu_flags_match (t);
4557 if (supported == CPU_FLAGS_PERFECT_MATCH)
548d0ee6
JB		 4558 {
4559 if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT))
4560 as_warn (_("use .code16 to ensure correct addressing mode"));
3629bb00 4561
548d0ee6
JB		 4562 return l;
4563 }
29b0f896 4564 }
3629bb00 4565
548d0ee6
JB		 4566 if (!(supported & CPU_FLAGS_64BIT_MATCH))
4567 as_bad (flag_code == CODE_64BIT
4568 ? _("`%s' is not supported in 64-bit mode")
4569 : _("`%s' is only supported in 64-bit mode"),
4570 current_templates->start->name);
4571 else
4572 as_bad (_("`%s' is not supported on `%s%s'"),
4573 current_templates->start->name,
4574 cpu_arch_name ? cpu_arch_name : default_arch,
4575 cpu_sub_arch_name ? cpu_sub_arch_name : "");
252b5132 4576
548d0ee6 4577 return NULL;
29b0f896 4578}
252b5132 4579
29b0f896 4580static char *
e3bb37b5 4581parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 4582{
4583 char *token_start;
3138f287 4584
29b0f896
AM		 4585 /* 1 if operand is pending after ','. */
4586 unsigned int expecting_operand = 0;
252b5132 4587
29b0f896
AM		 4588 /* Non-zero if operand parens not balanced. */
4589 unsigned int paren_not_balanced;
4590
4591 while (*l != END_OF_INSN)
4592 {
4593 /* Skip optional white space before operand. */
4594 if (is_space_char (*l))
4595 ++l;
d02603dc 4596 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
29b0f896
AM		 4597 {
4598 as_bad (_("invalid character %s before operand %d"),
4599 output_invalid (*l),
4600 i.operands + 1);
4601 return NULL;
4602 }
d02603dc 4603 token_start = l; /* After white space. */
29b0f896
AM		 4604 paren_not_balanced = 0;
4605 while (paren_not_balanced || *l != ',')
4606 {
4607 if (*l == END_OF_INSN)
4608 {
4609 if (paren_not_balanced)
4610 {
4611 if (!intel_syntax)
4612 as_bad (_("unbalanced parenthesis in operand %d."),
4613 i.operands + 1);
4614 else
4615 as_bad (_("unbalanced brackets in operand %d."),
4616 i.operands + 1);
4617 return NULL;
4618 }
4619 else
4620 break; /* we are done */
4621 }
d02603dc 4622 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
29b0f896
AM		 4623 {
4624 as_bad (_("invalid character %s in operand %d"),
4625 output_invalid (*l),
4626 i.operands + 1);
4627 return NULL;
4628 }
4629 if (!intel_syntax)
4630 {
4631 if (*l == '(')
4632 ++paren_not_balanced;
4633 if (*l == ')')
4634 --paren_not_balanced;
4635 }
4636 else
4637 {
4638 if (*l == '[')
4639 ++paren_not_balanced;
4640 if (*l == ']')
4641 --paren_not_balanced;
4642 }
4643 l++;
4644 }
4645 if (l != token_start)
4646 { /* Yes, we've read in another operand. */
4647 unsigned int operand_ok;
4648 this_operand = i.operands++;
4649 if (i.operands > MAX_OPERANDS)
4650 {
4651 as_bad (_("spurious operands; (%d operands/instruction max)"),
4652 MAX_OPERANDS);
4653 return NULL;
4654 }
9d46ce34 4655 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4656 /* Now parse operand adding info to 'i' as we go along. */
4657 END_STRING_AND_SAVE (l);
4658
4659 if (intel_syntax)
4660 operand_ok =
4661 i386_intel_operand (token_start,
4662 intel_float_operand (mnemonic));
4663 else
a7619375 4664 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4665
4666 RESTORE_END_STRING (l);
4667 if (!operand_ok)
4668 return NULL;
4669 }
4670 else
4671 {
4672 if (expecting_operand)
4673 {
4674 expecting_operand_after_comma:
4675 as_bad (_("expecting operand after ','; got nothing"));
4676 return NULL;
4677 }
4678 if (*l == ',')
4679 {
4680 as_bad (_("expecting operand before ','; got nothing"));
4681 return NULL;
4682 }
4683 }
7f3f1ea2 4684
29b0f896
AM		 4685 /* Now *l must be either ',' or END_OF_INSN. */
4686 if (*l == ',')
4687 {
4688 if (*++l == END_OF_INSN)
4689 {
4690 /* Just skip it, if it's \n complain. */
4691 goto expecting_operand_after_comma;
4692 }
4693 expecting_operand = 1;
4694 }
4695 }
4696 return l;
4697}
7f3f1ea2 4698
050dfa73 4699static void
4d456e3d 4700swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4701{
4702 union i386_op temp_op;
40fb9820 4703 i386_operand_type temp_type;
050dfa73 4704 enum bfd_reloc_code_real temp_reloc;
4eed87de 4705
050dfa73
MM		 4706 temp_type = i.types[xchg2];
4707 i.types[xchg2] = i.types[xchg1];
4708 i.types[xchg1] = temp_type;
4709 temp_op = i.op[xchg2];
4710 i.op[xchg2] = i.op[xchg1];
4711 i.op[xchg1] = temp_op;
4712 temp_reloc = i.reloc[xchg2];
4713 i.reloc[xchg2] = i.reloc[xchg1];
4714 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4715
4716 if (i.mask)
4717 {
4718 if (i.mask->operand == xchg1)
4719 i.mask->operand = xchg2;
4720 else if (i.mask->operand == xchg2)
4721 i.mask->operand = xchg1;
4722 }
4723 if (i.broadcast)
4724 {
4725 if (i.broadcast->operand == xchg1)
4726 i.broadcast->operand = xchg2;
4727 else if (i.broadcast->operand == xchg2)
4728 i.broadcast->operand = xchg1;
4729 }
4730 if (i.rounding)
4731 {
4732 if (i.rounding->operand == xchg1)
4733 i.rounding->operand = xchg2;
4734 else if (i.rounding->operand == xchg2)
4735 i.rounding->operand = xchg1;
4736 }
050dfa73
MM		 4737}
4738
29b0f896 4739static void
e3bb37b5 4740swap_operands (void)
29b0f896 4741{
b7c61d9a 4742 switch (i.operands)
050dfa73 4743 {
c0f3af97 4744 case 5:
b7c61d9a 4745 case 4:
4d456e3d 4746 swap_2_operands (1, i.operands - 2);
1a0670f3 4747 /* Fall through. */
b7c61d9a
L		 4748 case 3:
4749 case 2:
4d456e3d 4750 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4751 break;
4752 default:
4753 abort ();
29b0f896 4754 }
29b0f896
AM		 4755
4756 if (i.mem_operands == 2)
4757 {
4758 const seg_entry *temp_seg;
4759 temp_seg = i.seg[0];
4760 i.seg[0] = i.seg[1];
4761 i.seg[1] = temp_seg;
4762 }
4763}
252b5132 4764
29b0f896
AM		 4765/* Try to ensure constant immediates are represented in the smallest
4766 opcode possible. */
4767static void
e3bb37b5 4768optimize_imm (void)
29b0f896
AM		 4769{
4770 char guess_suffix = 0;
4771 int op;
252b5132 4772
29b0f896
AM		 4773 if (i.suffix)
4774 guess_suffix = i.suffix;
4775 else if (i.reg_operands)
4776 {
4777 /* Figure out a suffix from the last register operand specified.
4778 We can't do this properly yet, ie. excluding InOutPortReg,
4779 but the following works for instructions with immediates.
4780 In any case, we can't set i.suffix yet. */
4781 for (op = i.operands; --op >= 0;)
dc821c5f 4782 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
7ab9ffdd 4783 {
40fb9820
L		 4784 guess_suffix = BYTE_MNEM_SUFFIX;
4785 break;
4786 }
dc821c5f 4787 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
252b5132 4788 {
40fb9820
L		 4789 guess_suffix = WORD_MNEM_SUFFIX;
4790 break;
4791 }
dc821c5f 4792 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
40fb9820
L		 4793 {
4794 guess_suffix = LONG_MNEM_SUFFIX;
4795 break;
4796 }
dc821c5f 4797 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
40fb9820
L		 4798 {
4799 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4800 break;
252b5132 4801 }
29b0f896
AM		 4802 }
4803 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4804 guess_suffix = WORD_MNEM_SUFFIX;
4805
4806 for (op = i.operands; --op >= 0;)
40fb9820 4807 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4808 {
4809 switch (i.op[op].imms->X_op)
252b5132 4810 {
29b0f896
AM		 4811 case O_constant:
4812 /* If a suffix is given, this operand may be shortened. */
4813 switch (guess_suffix)
252b5132 4814 {
29b0f896 4815 case LONG_MNEM_SUFFIX:
40fb9820
L		 4816 i.types[op].bitfield.imm32 = 1;
4817 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4818 break;
4819 case WORD_MNEM_SUFFIX:
40fb9820
L		 4820 i.types[op].bitfield.imm16 = 1;
4821 i.types[op].bitfield.imm32 = 1;
4822 i.types[op].bitfield.imm32s = 1;
4823 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4824 break;
4825 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4826 i.types[op].bitfield.imm8 = 1;
4827 i.types[op].bitfield.imm8s = 1;
4828 i.types[op].bitfield.imm16 = 1;
4829 i.types[op].bitfield.imm32 = 1;
4830 i.types[op].bitfield.imm32s = 1;
4831 i.types[op].bitfield.imm64 = 1;
29b0f896 4832 break;
252b5132 4833 }
252b5132 4834
29b0f896
AM		 4835 /* If this operand is at most 16 bits, convert it
4836 to a signed 16 bit number before trying to see
4837 whether it will fit in an even smaller size.
4838 This allows a 16-bit operand such as $0xffe0 to
4839 be recognised as within Imm8S range. */
40fb9820 4840 if ((i.types[op].bitfield.imm16)
29b0f896 4841 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4842 {
29b0f896
AM		 4843 i.op[op].imms->X_add_number =
4844 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4845 }
a28def75
L		 4846#ifdef BFD64
4847 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
40fb9820 4848 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4849 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4850 == 0))
4851 {
4852 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4853 ^ ((offsetT) 1 << 31))
4854 - ((offsetT) 1 << 31));
4855 }
a28def75 4856#endif
40fb9820 4857 i.types[op]
c6fb90c8
L		 4858 = operand_type_or (i.types[op],
4859 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4860
29b0f896
AM		 4861 /* We must avoid matching of Imm32 templates when 64bit
4862 only immediate is available. */
4863 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4864 i.types[op].bitfield.imm32 = 0;
29b0f896 4865 break;
252b5132 4866
29b0f896
AM		 4867 case O_absent:
4868 case O_register:
4869 abort ();
4870
4871 /* Symbols and expressions. */
4872 default:
9cd96992
JB		 4873 /* Convert symbolic operand to proper sizes for matching, but don't
4874 prevent matching a set of insns that only supports sizes other
4875 than those matching the insn suffix. */
4876 {
40fb9820 4877 i386_operand_type mask, allowed;
d3ce72d0 4878 const insn_template *t;
9cd96992 4879
0dfbf9d7
L		 4880 operand_type_set (&mask, 0);
4881 operand_type_set (&allowed, 0);
40fb9820 4882
4eed87de
AM		 4883 for (t = current_templates->start;
4884 t < current_templates->end;
4885 ++t)
c6fb90c8
L		 4886 allowed = operand_type_or (allowed,
4887 t->operand_types[op]);
9cd96992
JB		 4888 switch (guess_suffix)
4889 {
4890 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4891 mask.bitfield.imm64 = 1;
4892 mask.bitfield.imm32s = 1;
9cd96992
JB		 4893 break;
4894 case LONG_MNEM_SUFFIX:
40fb9820 4895 mask.bitfield.imm32 = 1;
9cd96992
JB		 4896 break;
4897 case WORD_MNEM_SUFFIX:
40fb9820 4898 mask.bitfield.imm16 = 1;
9cd96992
JB		 4899 break;
4900 case BYTE_MNEM_SUFFIX:
40fb9820 4901 mask.bitfield.imm8 = 1;
9cd96992
JB		 4902 break;
4903 default:
9cd96992
JB		 4904 break;
4905 }
c6fb90c8 4906 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4907 if (!operand_type_all_zero (&allowed))
c6fb90c8 4908 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4909 }
29b0f896 4910 break;
252b5132 4911 }
29b0f896
AM		 4912 }
4913}
47926f60 4914
29b0f896
AM		 4915/* Try to use the smallest displacement type too. */
4916static void
e3bb37b5 4917optimize_disp (void)
29b0f896
AM		 4918{
4919 int op;
3e73aa7c 4920
29b0f896 4921 for (op = i.operands; --op >= 0;)
40fb9820 4922 if (operand_type_check (i.types[op], disp))
252b5132 4923 {
b300c311 4924 if (i.op[op].disps->X_op == O_constant)
252b5132 4925 {
91d6fa6a 4926 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4927
40fb9820 4928 if (i.types[op].bitfield.disp16
91d6fa6a 4929 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4930 {
4931 /* If this operand is at most 16 bits, convert
4932 to a signed 16 bit number and don't use 64bit
4933 displacement. */
91d6fa6a 4934 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4935 i.types[op].bitfield.disp64 = 0;
b300c311 4936 }
a28def75
L		 4937#ifdef BFD64
4938 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
40fb9820 4939 if (i.types[op].bitfield.disp32
91d6fa6a 4940 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4941 {
4942 /* If this operand is at most 32 bits, convert
4943 to a signed 32 bit number and don't use 64bit
4944 displacement. */
91d6fa6a
NC		 4945 op_disp &= (((offsetT) 2 << 31) - 1);
4946 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4947 i.types[op].bitfield.disp64 = 0;
b300c311 4948 }
a28def75 4949#endif
91d6fa6a 4950 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4951 {
40fb9820
L		 4952 i.types[op].bitfield.disp8 = 0;
4953 i.types[op].bitfield.disp16 = 0;
4954 i.types[op].bitfield.disp32 = 0;
4955 i.types[op].bitfield.disp32s = 0;
4956 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4957 i.op[op].disps = 0;
4958 i.disp_operands--;
4959 }
4960 else if (flag_code == CODE_64BIT)
4961 {
91d6fa6a 4962 if (fits_in_signed_long (op_disp))
28a9d8f5 4963 {
40fb9820
L		 4964 i.types[op].bitfield.disp64 = 0;
4965 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4966 }
0e1147d9 4967 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4968 && fits_in_unsigned_long (op_disp))
40fb9820 4969 i.types[op].bitfield.disp32 = 1;
b300c311 4970 }
40fb9820
L		 4971 if ((i.types[op].bitfield.disp32
4972 || i.types[op].bitfield.disp32s
4973 || i.types[op].bitfield.disp16)
b5014f7a 4974 && fits_in_disp8 (op_disp))
40fb9820 4975 i.types[op].bitfield.disp8 = 1;
252b5132 4976 }
67a4f2b7
AO		 4977 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4978 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4979 {
4980 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4981 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4982 i.types[op].bitfield.disp8 = 0;
4983 i.types[op].bitfield.disp16 = 0;
4984 i.types[op].bitfield.disp32 = 0;
4985 i.types[op].bitfield.disp32s = 0;
4986 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4987 }
4988 else
b300c311 4989 /* We only support 64bit displacement on constants. */
40fb9820 4990 i.types[op].bitfield.disp64 = 0;
252b5132 4991 }
29b0f896
AM		 4992}
4993
6c30d220
L		 4994/* Check if operands are valid for the instruction. */
4995
4996static int
4997check_VecOperands (const insn_template *t)
4998{
43234a1e 4999 unsigned int op;
e2195274
JB		 5000 i386_cpu_flags cpu;
5001 static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS;
5002
5003 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
5004 any one operand are implicity requiring AVX512VL support if the actual
5005 operand size is YMMword or XMMword. Since this function runs after
5006 template matching, there's no need to check for YMMword/XMMword in
5007 the template. */
5008 cpu = cpu_flags_and (t->cpu_flags, avx512);
5009 if (!cpu_flags_all_zero (&cpu)
5010 && !t->cpu_flags.bitfield.cpuavx512vl
5011 && !cpu_arch_flags.bitfield.cpuavx512vl)
5012 {
5013 for (op = 0; op < t->operands; ++op)
5014 {
5015 if (t->operand_types[op].bitfield.zmmword
5016 && (i.types[op].bitfield.ymmword
5017 || i.types[op].bitfield.xmmword))
5018 {
5019 i.error = unsupported;
5020 return 1;
5021 }
5022 }
5023 }
43234a1e 5024
6c30d220
L		 5025 /* Without VSIB byte, we can't have a vector register for index. */
5026 if (!t->opcode_modifier.vecsib
5027 && i.index_reg
1b54b8d7
JB		 5028 && (i.index_reg->reg_type.bitfield.xmmword
5029 || i.index_reg->reg_type.bitfield.ymmword
5030 || i.index_reg->reg_type.bitfield.zmmword))
6c30d220
L		 5031 {
5032 i.error = unsupported_vector_index_register;
5033 return 1;
5034 }
5035
ad8ecc81
MZ		 5036 /* Check if default mask is allowed. */
5037 if (t->opcode_modifier.nodefmask
5038 && (!i.mask || i.mask->mask->reg_num == 0))
5039 {
5040 i.error = no_default_mask;
5041 return 1;
5042 }
5043
7bab8ab5
JB		 5044 /* For VSIB byte, we need a vector register for index, and all vector
5045 registers must be distinct. */
5046 if (t->opcode_modifier.vecsib)
5047 {
5048 if (!i.index_reg
6c30d220 5049 || !((t->opcode_modifier.vecsib == VecSIB128
1b54b8d7 5050 && i.index_reg->reg_type.bitfield.xmmword)
6c30d220 5051 || (t->opcode_modifier.vecsib == VecSIB256
1b54b8d7 5052 && i.index_reg->reg_type.bitfield.ymmword)
43234a1e 5053 || (t->opcode_modifier.vecsib == VecSIB512
1b54b8d7 5054 && i.index_reg->reg_type.bitfield.zmmword)))
7bab8ab5
JB		 5055 {
5056 i.error = invalid_vsib_address;
5057 return 1;
5058 }
5059
43234a1e
L		 5060 gas_assert (i.reg_operands == 2 || i.mask);
5061 if (i.reg_operands == 2 && !i.mask)
5062 {
1b54b8d7
JB		 5063 gas_assert (i.types[0].bitfield.regsimd);
5064 gas_assert (i.types[0].bitfield.xmmword
5065 || i.types[0].bitfield.ymmword);
5066 gas_assert (i.types[2].bitfield.regsimd);
5067 gas_assert (i.types[2].bitfield.xmmword
5068 || i.types[2].bitfield.ymmword);
43234a1e
L		 5069 if (operand_check == check_none)
5070 return 0;
5071 if (register_number (i.op[0].regs)
5072 != register_number (i.index_reg)
5073 && register_number (i.op[2].regs)
5074 != register_number (i.index_reg)
5075 && register_number (i.op[0].regs)
5076 != register_number (i.op[2].regs))
5077 return 0;
5078 if (operand_check == check_error)
5079 {
5080 i.error = invalid_vector_register_set;
5081 return 1;
5082 }
5083 as_warn (_("mask, index, and destination registers should be distinct"));
5084 }
8444f82a
MZ		 5085 else if (i.reg_operands == 1 && i.mask)
5086 {
1b54b8d7
JB		 5087 if (i.types[1].bitfield.regsimd
5088 && (i.types[1].bitfield.xmmword
5089 || i.types[1].bitfield.ymmword
5090 || i.types[1].bitfield.zmmword)
8444f82a
MZ		 5091 && (register_number (i.op[1].regs)
5092 == register_number (i.index_reg)))
5093 {
5094 if (operand_check == check_error)
5095 {
5096 i.error = invalid_vector_register_set;
5097 return 1;
5098 }
5099 if (operand_check != check_none)
5100 as_warn (_("index and destination registers should be distinct"));
5101 }
5102 }
43234a1e 5103 }
7bab8ab5 5104
43234a1e
L		 5105 /* Check if broadcast is supported by the instruction and is applied
5106 to the memory operand. */
5107 if (i.broadcast)
5108 {
8e6e0792 5109 i386_operand_type type, overlap;
43234a1e
L		 5110
5111 /* Check if specified broadcast is supported in this instruction,
c39e5b26 5112 and it's applied to memory operand of DWORD or QWORD type. */
32546502 5113 op = i.broadcast->operand;
8e6e0792 5114 if (!t->opcode_modifier.broadcast
32546502 5115 || !i.types[op].bitfield.mem
c39e5b26
JB		 5116 || (!i.types[op].bitfield.unspecified
5117 && (t->operand_types[op].bitfield.dword
5118 ? !i.types[op].bitfield.dword
5119 : !i.types[op].bitfield.qword)))
43234a1e
L		 5120 {
5121 bad_broadcast:
5122 i.error = unsupported_broadcast;
5123 return 1;
5124 }
8e6e0792
JB		 5125
5126 operand_type_set (&type, 0);
c39e5b26 5127 switch ((t->operand_types[op].bitfield.dword ? 4 : 8) * i.broadcast->type)
8e6e0792
JB		 5128 {
5129 case 8:
5130 type.bitfield.qword = 1;
5131 break;
5132 case 16:
5133 type.bitfield.xmmword = 1;
5134 break;
5135 case 32:
5136 type.bitfield.ymmword = 1;
5137 break;
5138 case 64:
5139 type.bitfield.zmmword = 1;
5140 break;
5141 default:
5142 goto bad_broadcast;
5143 }
5144
5145 overlap = operand_type_and (type, t->operand_types[op]);
5146 if (operand_type_all_zero (&overlap))
5147 goto bad_broadcast;
5148
5149 if (t->opcode_modifier.checkregsize)
5150 {
5151 unsigned int j;
5152
e2195274 5153 type.bitfield.baseindex = 1;
8e6e0792
JB		 5154 for (j = 0; j < i.operands; ++j)
5155 {
5156 if (j != op
5157 && !operand_type_register_match(i.types[j],
5158 t->operand_types[j],
5159 type,
5160 t->operand_types[op]))
5161 goto bad_broadcast;
5162 }
5163 }
43234a1e
L		 5164 }
5165 /* If broadcast is supported in this instruction, we need to check if
5166 operand of one-element size isn't specified without broadcast. */
5167 else if (t->opcode_modifier.broadcast && i.mem_operands)
5168 {
5169 /* Find memory operand. */
5170 for (op = 0; op < i.operands; op++)
5171 if (operand_type_check (i.types[op], anymem))
5172 break;
5173 gas_assert (op < i.operands);
5174 /* Check size of the memory operand. */
c39e5b26
JB		 5175 if (t->operand_types[op].bitfield.dword
5176 ? i.types[op].bitfield.dword
5177 : i.types[op].bitfield.qword)
43234a1e
L		 5178 {
5179 i.error = broadcast_needed;
5180 return 1;
5181 }
5182 }
c39e5b26
JB		 5183 else
5184 op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */
43234a1e
L		 5185
5186 /* Check if requested masking is supported. */
5187 if (i.mask
5188 && (!t->opcode_modifier.masking
5189 || (i.mask->zeroing
5190 && t->opcode_modifier.masking == MERGING_MASKING)))
5191 {
5192 i.error = unsupported_masking;
5193 return 1;
5194 }
5195
5196 /* Check if masking is applied to dest operand. */
5197 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
5198 {
5199 i.error = mask_not_on_destination;
5200 return 1;
5201 }
5202
43234a1e
L		 5203 /* Check RC/SAE. */
5204 if (i.rounding)
5205 {
5206 if ((i.rounding->type != saeonly
5207 && !t->opcode_modifier.staticrounding)
5208 || (i.rounding->type == saeonly
5209 && (t->opcode_modifier.staticrounding
5210 || !t->opcode_modifier.sae)))
5211 {
5212 i.error = unsupported_rc_sae;
5213 return 1;
5214 }
5215 /* If the instruction has several immediate operands and one of
5216 them is rounding, the rounding operand should be the last
5217 immediate operand. */
5218 if (i.imm_operands > 1
5219 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 5220 {
43234a1e 5221 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 5222 return 1;
5223 }
6c30d220
L		 5224 }
5225
43234a1e 5226 /* Check vector Disp8 operand. */
b5014f7a
JB		 5227 if (t->opcode_modifier.disp8memshift
5228 && i.disp_encoding != disp_encoding_32bit)
43234a1e
L		 5229 {
5230 if (i.broadcast)
c39e5b26 5231 i.memshift = t->operand_types[op].bitfield.dword ? 2 : 3;
7091c612 5232 else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL)
43234a1e 5233 i.memshift = t->opcode_modifier.disp8memshift;
7091c612
JB		 5234 else
5235 {
5236 const i386_operand_type *type = NULL;
5237
5238 i.memshift = 0;
5239 for (op = 0; op < i.operands; op++)
5240 if (operand_type_check (i.types[op], anymem))
5241 {
5242 if (t->operand_types[op].bitfield.xmmword
5243 + t->operand_types[op].bitfield.ymmword
5244 + t->operand_types[op].bitfield.zmmword <= 1)
5245 type = &t->operand_types[op];
5246 else if (!i.types[op].bitfield.unspecified)
5247 type = &i.types[op];
5248 }
5249 else if (i.types[op].bitfield.regsimd)
5250 {
5251 if (i.types[op].bitfield.zmmword)
5252 i.memshift = 6;
5253 else if (i.types[op].bitfield.ymmword && i.memshift < 5)
5254 i.memshift = 5;
5255 else if (i.types[op].bitfield.xmmword && i.memshift < 4)
5256 i.memshift = 4;
5257 }
5258
5259 if (type)
5260 {
5261 if (type->bitfield.zmmword)
5262 i.memshift = 6;
5263 else if (type->bitfield.ymmword)
5264 i.memshift = 5;
5265 else if (type->bitfield.xmmword)
5266 i.memshift = 4;
5267 }
5268
5269 /* For the check in fits_in_disp8(). */
5270 if (i.memshift == 0)
5271 i.memshift = -1;
5272 }
43234a1e
L		 5273
5274 for (op = 0; op < i.operands; op++)
5275 if (operand_type_check (i.types[op], disp)
5276 && i.op[op].disps->X_op == O_constant)
5277 {
b5014f7a 5278 if (fits_in_disp8 (i.op[op].disps->X_add_number))
43234a1e 5279 {
b5014f7a
JB		 5280 i.types[op].bitfield.disp8 = 1;
5281 return 0;
43234a1e 5282 }
b5014f7a 5283 i.types[op].bitfield.disp8 = 0;
43234a1e
L		 5284 }
5285 }
b5014f7a
JB		 5286
5287 i.memshift = 0;
43234a1e 5288
6c30d220
L		 5289 return 0;
5290}
5291
43f3e2ee 5292/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 5293 operand types. */
5294
5295static int
5296VEX_check_operands (const insn_template *t)
5297{
86fa6981 5298 if (i.vec_encoding == vex_encoding_evex)
43234a1e 5299 {
86fa6981 5300 /* This instruction must be encoded with EVEX prefix. */
e771e7c9 5301 if (!is_evex_encoding (t))
86fa6981
L		 5302 {
5303 i.error = unsupported;
5304 return 1;
5305 }
5306 return 0;
43234a1e
L		 5307 }
5308
a683cc34 5309 if (!t->opcode_modifier.vex)
86fa6981
L		 5310 {
5311 /* This instruction template doesn't have VEX prefix. */
5312 if (i.vec_encoding != vex_encoding_default)
5313 {
5314 i.error = unsupported;
5315 return 1;
5316 }
5317 return 0;
5318 }
a683cc34
SP		 5319
5320 /* Only check VEX_Imm4, which must be the first operand. */
5321 if (t->operand_types[0].bitfield.vec_imm4)
5322 {
5323 if (i.op[0].imms->X_op != O_constant
5324 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 5325 {
a65babc9 5326 i.error = bad_imm4;
891edac4
L		 5327 return 1;
5328 }
a683cc34
SP		 5329
5330 /* Turn off Imm8 so that update_imm won't complain. */
5331 i.types[0] = vec_imm4;
5332 }
5333
5334 return 0;
5335}
5336
d3ce72d0 5337static const insn_template *
83b16ac6 5338match_template (char mnem_suffix)
29b0f896
AM		 5339{
5340 /* Points to template once we've found it. */
d3ce72d0 5341 const insn_template *t;
40fb9820 5342 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 5343 i386_operand_type overlap4;
29b0f896 5344 unsigned int found_reverse_match;
83b16ac6 5345 i386_opcode_modifier suffix_check, mnemsuf_check;
40fb9820 5346 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 5347 int addr_prefix_disp;
a5c311ca 5348 unsigned int j;
3ac21baa 5349 unsigned int found_cpu_match, size_match;
45664ddb 5350 unsigned int check_register;
5614d22c 5351 enum i386_error specific_error = 0;
29b0f896 5352
c0f3af97
L		 5353#if MAX_OPERANDS != 5
5354# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 5355#endif
5356
29b0f896 5357 found_reverse_match = 0;
539e75ad 5358 addr_prefix_disp = -1;
40fb9820
L		 5359
5360 memset (&suffix_check, 0, sizeof (suffix_check));
e2195274
JB		 5361 if (intel_syntax && i.broadcast)
5362 /* nothing */;
5363 else if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5364 suffix_check.no_bsuf = 1;
5365 else if (i.suffix == WORD_MNEM_SUFFIX)
5366 suffix_check.no_wsuf = 1;
5367 else if (i.suffix == SHORT_MNEM_SUFFIX)
5368 suffix_check.no_ssuf = 1;
5369 else if (i.suffix == LONG_MNEM_SUFFIX)
5370 suffix_check.no_lsuf = 1;
5371 else if (i.suffix == QWORD_MNEM_SUFFIX)
5372 suffix_check.no_qsuf = 1;
5373 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 5374 suffix_check.no_ldsuf = 1;
29b0f896 5375
83b16ac6
JB		 5376 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
5377 if (intel_syntax)
5378 {
5379 switch (mnem_suffix)
5380 {
5381 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
5382 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
5383 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
5384 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
5385 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
5386 }
5387 }
5388
01559ecc
L		 5389 /* Must have right number of operands. */
5390 i.error = number_of_operands_mismatch;
5391
45aa61fe 5392 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 5393 {
539e75ad
L		 5394 addr_prefix_disp = -1;
5395
29b0f896
AM		 5396 if (i.operands != t->operands)
5397 continue;
5398
50aecf8c 5399 /* Check processor support. */
a65babc9 5400 i.error = unsupported;
c0f3af97
L		 5401 found_cpu_match = (cpu_flags_match (t)
5402 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 5403 if (!found_cpu_match)
5404 continue;
5405
e1d4d893 5406 /* Check AT&T mnemonic. */
a65babc9 5407 i.error = unsupported_with_intel_mnemonic;
e1d4d893 5408 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 5409 continue;
5410
e92bae62 5411 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
a65babc9 5412 i.error = unsupported_syntax;
5c07affc 5413 if ((intel_syntax && t->opcode_modifier.attsyntax)
e92bae62
L		 5414 || (!intel_syntax && t->opcode_modifier.intelsyntax)
5415 || (intel64 && t->opcode_modifier.amd64)
5416 || (!intel64 && t->opcode_modifier.intel64))
1efbbeb4
L		 5417 continue;
5418
20592a94 5419 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 5420 i.error = invalid_instruction_suffix;
567e4e96
L		 5421 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
5422 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
5423 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
5424 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
5425 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
5426 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
5427 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896 5428 continue;
83b16ac6
JB		 5429 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
5430 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
5431 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
5432 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
5433 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
5434 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
5435 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
5436 continue;
29b0f896 5437
3ac21baa
JB		 5438 size_match = operand_size_match (t);
5439 if (!size_match)
7d5e4556 5440 continue;
539e75ad 5441
5c07affc
L		 5442 for (j = 0; j < MAX_OPERANDS; j++)
5443 operand_types[j] = t->operand_types[j];
5444
45aa61fe
AM		 5445 /* In general, don't allow 64-bit operands in 32-bit mode. */
5446 if (i.suffix == QWORD_MNEM_SUFFIX
5447 && flag_code != CODE_64BIT
5448 && (intel_syntax
40fb9820 5449 ? (!t->opcode_modifier.ignoresize
625cbd7a 5450 && !t->opcode_modifier.broadcast
45aa61fe
AM		 5451 && !intel_float_operand (t->name))
5452 : intel_float_operand (t->name) != 2)
40fb9820 5453 && ((!operand_types[0].bitfield.regmmx
1b54b8d7 5454 && !operand_types[0].bitfield.regsimd)
40fb9820 5455 || (!operand_types[t->operands > 1].bitfield.regmmx
1b54b8d7 5456 && !operand_types[t->operands > 1].bitfield.regsimd))
45aa61fe
AM		 5457 && (t->base_opcode != 0x0fc7
5458 || t->extension_opcode != 1 /* cmpxchg8b */))
5459 continue;
5460
192dc9c6
JB		 5461 /* In general, don't allow 32-bit operands on pre-386. */
5462 else if (i.suffix == LONG_MNEM_SUFFIX
5463 && !cpu_arch_flags.bitfield.cpui386
5464 && (intel_syntax
5465 ? (!t->opcode_modifier.ignoresize
5466 && !intel_float_operand (t->name))
5467 : intel_float_operand (t->name) != 2)
5468 && ((!operand_types[0].bitfield.regmmx
1b54b8d7 5469 && !operand_types[0].bitfield.regsimd)
192dc9c6 5470 || (!operand_types[t->operands > 1].bitfield.regmmx
1b54b8d7 5471 && !operand_types[t->operands > 1].bitfield.regsimd)))
192dc9c6
JB		 5472 continue;
5473
29b0f896 5474 /* Do not verify operands when there are none. */
50aecf8c 5475 else
29b0f896 5476 {
c6fb90c8 5477 if (!t->operands)
2dbab7d5
L		 5478 /* We've found a match; break out of loop. */
5479 break;
29b0f896 5480 }
252b5132 5481
539e75ad
L		 5482 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5483 into Disp32/Disp16/Disp32 operand. */
5484 if (i.prefix[ADDR_PREFIX] != 0)
5485 {
40fb9820 5486 /* There should be only one Disp operand. */
539e75ad
L		 5487 switch (flag_code)
5488 {
5489 case CODE_16BIT:
40fb9820
L		 5490 for (j = 0; j < MAX_OPERANDS; j++)
5491 {
5492 if (operand_types[j].bitfield.disp16)
5493 {
5494 addr_prefix_disp = j;
5495 operand_types[j].bitfield.disp32 = 1;
5496 operand_types[j].bitfield.disp16 = 0;
5497 break;
5498 }
5499 }
539e75ad
L		 5500 break;
5501 case CODE_32BIT:
40fb9820
L		 5502 for (j = 0; j < MAX_OPERANDS; j++)
5503 {
5504 if (operand_types[j].bitfield.disp32)
5505 {
5506 addr_prefix_disp = j;
5507 operand_types[j].bitfield.disp32 = 0;
5508 operand_types[j].bitfield.disp16 = 1;
5509 break;
5510 }
5511 }
539e75ad
L		 5512 break;
5513 case CODE_64BIT:
40fb9820
L		 5514 for (j = 0; j < MAX_OPERANDS; j++)
5515 {
5516 if (operand_types[j].bitfield.disp64)
5517 {
5518 addr_prefix_disp = j;
5519 operand_types[j].bitfield.disp64 = 0;
5520 operand_types[j].bitfield.disp32 = 1;
5521 break;
5522 }
5523 }
539e75ad
L		 5524 break;
5525 }
539e75ad
L		 5526 }
5527
02a86693
L		 5528 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5529 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5530 continue;
5531
56ffb741 5532 /* We check register size if needed. */
e2195274
JB		 5533 if (t->opcode_modifier.checkregsize)
5534 {
5535 check_register = (1 << t->operands) - 1;
5536 if (i.broadcast)
5537 check_register &= ~(1 << i.broadcast->operand);
5538 }
5539 else
5540 check_register = 0;
5541
c6fb90c8 5542 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 5543 switch (t->operands)
5544 {
5545 case 1:
40fb9820 5546 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 5547 continue;
5548 break;
5549 case 2:
33eaf5de 5550 /* xchg %eax, %eax is a special case. It is an alias for nop
8b38ad71
L		 5551 only in 32bit mode and we can use opcode 0x90. In 64bit
5552 mode, we can't use 0x90 for xchg %eax, %eax since it should
5553 zero-extend %eax to %rax. */
5554 if (flag_code == CODE_64BIT
5555 && t->base_opcode == 0x90
0dfbf9d7
L		 5556 && operand_type_equal (&i.types [0], &acc32)
5557 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 5558 continue;
1212781b
JB		 5559 /* xrelease mov %eax, <disp> is another special case. It must not
5560 match the accumulator-only encoding of mov. */
5561 if (flag_code != CODE_64BIT
5562 && i.hle_prefix
5563 && t->base_opcode == 0xa0
5564 && i.types[0].bitfield.acc
5565 && operand_type_check (i.types[1], anymem))
5566 continue;
3ac21baa
JB		 5567 if (!(size_match & MATCH_STRAIGHT))
5568 goto check_reverse;
86fa6981
L		 5569 /* If we want store form, we reverse direction of operands. */
5570 if (i.dir_encoding == dir_encoding_store
5571 && t->opcode_modifier.d)
5572 goto check_reverse;
1a0670f3 5573 /* Fall through. */
b6169b20 5574
29b0f896 5575 case 3:
86fa6981
L		 5576 /* If we want store form, we skip the current load. */
5577 if (i.dir_encoding == dir_encoding_store
5578 && i.mem_operands == 0
5579 && t->opcode_modifier.load)
fa99fab2 5580 continue;
1a0670f3 5581 /* Fall through. */
f48ff2ae 5582 case 4:
c0f3af97 5583 case 5:
c6fb90c8 5584 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 5585 if (!operand_type_match (overlap0, i.types[0])
5586 || !operand_type_match (overlap1, i.types[1])
e2195274 5587 || ((check_register & 3) == 3
dc821c5f 5588 && !operand_type_register_match (i.types[0],
40fb9820 5589 operand_types[0],
dc821c5f 5590 i.types[1],
40fb9820 5591 operand_types[1])))
29b0f896
AM		 5592 {
5593 /* Check if other direction is valid ... */
38e314eb 5594 if (!t->opcode_modifier.d)
29b0f896
AM		 5595 continue;
5596
b6169b20 5597check_reverse:
3ac21baa
JB		 5598 if (!(size_match & MATCH_REVERSE))
5599 continue;
29b0f896 5600 /* Try reversing direction of operands. */
c6fb90c8
L		 5601 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5602 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 5603 if (!operand_type_match (overlap0, i.types[0])
5604 || !operand_type_match (overlap1, i.types[1])
45664ddb 5605 || (check_register
dc821c5f 5606 && !operand_type_register_match (i.types[0],
45664ddb 5607 operand_types[1],
45664ddb
L		 5608 i.types[1],
5609 operand_types[0])))
29b0f896
AM		 5610 {
5611 /* Does not match either direction. */
5612 continue;
5613 }
38e314eb 5614 /* found_reverse_match holds which of D or FloatR
29b0f896 5615 we've found. */
38e314eb
JB		 5616 if (!t->opcode_modifier.d)
5617 found_reverse_match = 0;
5618 else if (operand_types[0].bitfield.tbyte)
8a2ed489
L		 5619 found_reverse_match = Opcode_FloatD;
5620 else
38e314eb 5621 found_reverse_match = Opcode_D;
40fb9820 5622 if (t->opcode_modifier.floatr)
8a2ed489 5623 found_reverse_match |= Opcode_FloatR;
29b0f896 5624 }
f48ff2ae 5625 else
29b0f896 5626 {
f48ff2ae 5627 /* Found a forward 2 operand match here. */
d1cbb4db
L		 5628 switch (t->operands)
5629 {
c0f3af97
L		 5630 case 5:
5631 overlap4 = operand_type_and (i.types[4],
5632 operand_types[4]);
1a0670f3 5633 /* Fall through. */
d1cbb4db 5634 case 4:
c6fb90c8
L		 5635 overlap3 = operand_type_and (i.types[3],
5636 operand_types[3]);
1a0670f3 5637 /* Fall through. */
d1cbb4db 5638 case 3:
c6fb90c8
L		 5639 overlap2 = operand_type_and (i.types[2],
5640 operand_types[2]);
d1cbb4db
L		 5641 break;
5642 }
29b0f896 5643
f48ff2ae
L		 5644 switch (t->operands)
5645 {
c0f3af97
L		 5646 case 5:
5647 if (!operand_type_match (overlap4, i.types[4])
dc821c5f 5648 || !operand_type_register_match (i.types[3],
c0f3af97 5649 operand_types[3],
c0f3af97
L		 5650 i.types[4],
5651 operand_types[4]))
5652 continue;
1a0670f3 5653 /* Fall through. */
f48ff2ae 5654 case 4:
40fb9820 5655 if (!operand_type_match (overlap3, i.types[3])
e2195274
JB		 5656 || ((check_register & 0xa) == 0xa
5657 && !operand_type_register_match (i.types[1],
f7768225
JB		 5658 operand_types[1],
5659 i.types[3],
e2195274
JB		 5660 operand_types[3]))
5661 || ((check_register & 0xc) == 0xc
5662 && !operand_type_register_match (i.types[2],
5663 operand_types[2],
5664 i.types[3],
5665 operand_types[3])))
f48ff2ae 5666 continue;
1a0670f3 5667 /* Fall through. */
f48ff2ae
L		 5668 case 3:
5669 /* Here we make use of the fact that there are no
23e42951 5670 reverse match 3 operand instructions. */
40fb9820 5671 if (!operand_type_match (overlap2, i.types[2])
e2195274
JB		 5672 || ((check_register & 5) == 5
5673 && !operand_type_register_match (i.types[0],
23e42951
JB		 5674 operand_types[0],
5675 i.types[2],
e2195274
JB		 5676 operand_types[2]))
5677 || ((check_register & 6) == 6
5678 && !operand_type_register_match (i.types[1],
5679 operand_types[1],
5680 i.types[2],
5681 operand_types[2])))
f48ff2ae
L		 5682 continue;
5683 break;
5684 }
29b0f896 5685 }
f48ff2ae 5686 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 5687 slip through to break. */
5688 }
3629bb00 5689 if (!found_cpu_match)
29b0f896
AM		 5690 {
5691 found_reverse_match = 0;
5692 continue;
5693 }
c0f3af97 5694
5614d22c
JB		 5695 /* Check if vector and VEX operands are valid. */
5696 if (check_VecOperands (t) || VEX_check_operands (t))
5697 {
5698 specific_error = i.error;
5699 continue;
5700 }
a683cc34 5701
29b0f896
AM		 5702 /* We've found a match; break out of loop. */
5703 break;
5704 }
5705
5706 if (t == current_templates->end)
5707 {
5708 /* We found no match. */
a65babc9 5709 const char *err_msg;
5614d22c 5710 switch (specific_error ? specific_error : i.error)
a65babc9
L		 5711 {
5712 default:
5713 abort ();
86e026a4 5714 case operand_size_mismatch:
a65babc9
L		 5715 err_msg = _("operand size mismatch");
5716 break;
5717 case operand_type_mismatch:
5718 err_msg = _("operand type mismatch");
5719 break;
5720 case register_type_mismatch:
5721 err_msg = _("register type mismatch");
5722 break;
5723 case number_of_operands_mismatch:
5724 err_msg = _("number of operands mismatch");
5725 break;
5726 case invalid_instruction_suffix:
5727 err_msg = _("invalid instruction suffix");
5728 break;
5729 case bad_imm4:
4a2608e3 5730 err_msg = _("constant doesn't fit in 4 bits");
a65babc9 5731 break;
a65babc9
L		 5732 case unsupported_with_intel_mnemonic:
5733 err_msg = _("unsupported with Intel mnemonic");
5734 break;
5735 case unsupported_syntax:
5736 err_msg = _("unsupported syntax");
5737 break;
5738 case unsupported:
35262a23 5739 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 5740 current_templates->start->name);
5741 return NULL;
6c30d220
L		 5742 case invalid_vsib_address:
5743 err_msg = _("invalid VSIB address");
5744 break;
7bab8ab5
JB		 5745 case invalid_vector_register_set:
5746 err_msg = _("mask, index, and destination registers must be distinct");
5747 break;
6c30d220
L		 5748 case unsupported_vector_index_register:
5749 err_msg = _("unsupported vector index register");
5750 break;
43234a1e
L		 5751 case unsupported_broadcast:
5752 err_msg = _("unsupported broadcast");
5753 break;
5754 case broadcast_not_on_src_operand:
5755 err_msg = _("broadcast not on source memory operand");
5756 break;
5757 case broadcast_needed:
5758 err_msg = _("broadcast is needed for operand of such type");
5759 break;
5760 case unsupported_masking:
5761 err_msg = _("unsupported masking");
5762 break;
5763 case mask_not_on_destination:
5764 err_msg = _("mask not on destination operand");
5765 break;
5766 case no_default_mask:
5767 err_msg = _("default mask isn't allowed");
5768 break;
5769 case unsupported_rc_sae:
5770 err_msg = _("unsupported static rounding/sae");
5771 break;
5772 case rc_sae_operand_not_last_imm:
5773 if (intel_syntax)
5774 err_msg = _("RC/SAE operand must precede immediate operands");
5775 else
5776 err_msg = _("RC/SAE operand must follow immediate operands");
5777 break;
5778 case invalid_register_operand:
5779 err_msg = _("invalid register operand");
5780 break;
a65babc9
L		 5781 }
5782 as_bad (_("%s for `%s'"), err_msg,
891edac4 5783 current_templates->start->name);
fa99fab2 5784 return NULL;
29b0f896 5785 }
252b5132 5786
29b0f896
AM		 5787 if (!quiet_warnings)
5788 {
5789 if (!intel_syntax
40fb9820
L		 5790 && (i.types[0].bitfield.jumpabsolute
5791 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5792 {
5793 as_warn (_("indirect %s without `*'"), t->name);
5794 }
5795
40fb9820
L		 5796 if (t->opcode_modifier.isprefix
5797 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5798 {
5799 /* Warn them that a data or address size prefix doesn't
5800 affect assembly of the next line of code. */
5801 as_warn (_("stand-alone `%s' prefix"), t->name);
5802 }
5803 }
5804
5805 /* Copy the template we found. */
5806 i.tm = *t;
539e75ad
L		 5807
5808 if (addr_prefix_disp != -1)
5809 i.tm.operand_types[addr_prefix_disp]
5810 = operand_types[addr_prefix_disp];
5811
29b0f896
AM		 5812 if (found_reverse_match)
5813 {
5814 /* If we found a reverse match we must alter the opcode
5815 direction bit. found_reverse_match holds bits to change
5816 (different for int & float insns). */
5817
5818 i.tm.base_opcode ^= found_reverse_match;
5819
539e75ad
L		 5820 i.tm.operand_types[0] = operand_types[1];
5821 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5822 }
5823
fa99fab2 5824 return t;
29b0f896
AM		 5825}
5826
5827static int
e3bb37b5 5828check_string (void)
29b0f896 5829{
40fb9820
L		 5830 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5831 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5832 {
5833 if (i.seg[0] != NULL && i.seg[0] != &es)
5834 {
a87af027 5835 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5836 i.tm.name,
a87af027
JB		 5837 mem_op + 1,
5838 register_prefix);
29b0f896
AM		 5839 return 0;
5840 }
5841 /* There's only ever one segment override allowed per instruction.
5842 This instruction possibly has a legal segment override on the
5843 second operand, so copy the segment to where non-string
5844 instructions store it, allowing common code. */
5845 i.seg[0] = i.seg[1];
5846 }
40fb9820 5847 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5848 {
5849 if (i.seg[1] != NULL && i.seg[1] != &es)
5850 {
a87af027 5851 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5852 i.tm.name,
a87af027
JB		 5853 mem_op + 2,
5854 register_prefix);
29b0f896
AM		 5855 return 0;
5856 }
5857 }
5858 return 1;
5859}
5860
5861static int
543613e9 5862process_suffix (void)
29b0f896
AM		 5863{
5864 /* If matched instruction specifies an explicit instruction mnemonic
5865 suffix, use it. */
40fb9820
L		 5866 if (i.tm.opcode_modifier.size16)
5867 i.suffix = WORD_MNEM_SUFFIX;
5868 else if (i.tm.opcode_modifier.size32)
5869 i.suffix = LONG_MNEM_SUFFIX;
5870 else if (i.tm.opcode_modifier.size64)
5871 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5872 else if (i.reg_operands)
5873 {
5874 /* If there's no instruction mnemonic suffix we try to invent one
5875 based on register operands. */
5876 if (!i.suffix)
5877 {
5878 /* We take i.suffix from the last register operand specified,
5879 Destination register type is more significant than source
381d071f
L		 5880 register type. crc32 in SSE4.2 prefers source register
5881 type. */
5882 if (i.tm.base_opcode == 0xf20f38f1)
5883 {
dc821c5f 5884 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
40fb9820 5885 i.suffix = WORD_MNEM_SUFFIX;
dc821c5f 5886 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
40fb9820 5887 i.suffix = LONG_MNEM_SUFFIX;
dc821c5f 5888 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
40fb9820 5889 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5890 }
9344ff29 5891 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5892 {
dc821c5f 5893 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
20592a94
L		 5894 i.suffix = BYTE_MNEM_SUFFIX;
5895 }
381d071f
L		 5896
5897 if (!i.suffix)
5898 {
5899 int op;
5900
20592a94
L		 5901 if (i.tm.base_opcode == 0xf20f38f1
5902 || i.tm.base_opcode == 0xf20f38f0)
5903 {
5904 /* We have to know the operand size for crc32. */
5905 as_bad (_("ambiguous memory operand size for `%s`"),
5906 i.tm.name);
5907 return 0;
5908 }
5909
381d071f 5910 for (op = i.operands; --op >= 0;)
b76bc5d5
JB		 5911 if (!i.tm.operand_types[op].bitfield.inoutportreg
5912 && !i.tm.operand_types[op].bitfield.shiftcount)
381d071f 5913 {
8819ada6
JB		 5914 if (!i.types[op].bitfield.reg)
5915 continue;
5916 if (i.types[op].bitfield.byte)
5917 i.suffix = BYTE_MNEM_SUFFIX;
5918 else if (i.types[op].bitfield.word)
5919 i.suffix = WORD_MNEM_SUFFIX;
5920 else if (i.types[op].bitfield.dword)
5921 i.suffix = LONG_MNEM_SUFFIX;
5922 else if (i.types[op].bitfield.qword)
5923 i.suffix = QWORD_MNEM_SUFFIX;
5924 else
5925 continue;
5926 break;
381d071f
L		 5927 }
5928 }
29b0f896
AM		 5929 }
5930 else if (i.suffix == BYTE_MNEM_SUFFIX)
5931 {
2eb952a4
L		 5932 if (intel_syntax
5933 && i.tm.opcode_modifier.ignoresize
5934 && i.tm.opcode_modifier.no_bsuf)
5935 i.suffix = 0;
5936 else if (!check_byte_reg ())
29b0f896
AM		 5937 return 0;
5938 }
5939 else if (i.suffix == LONG_MNEM_SUFFIX)
5940 {
2eb952a4
L		 5941 if (intel_syntax
5942 && i.tm.opcode_modifier.ignoresize
9f123b91
JB		 5943 && i.tm.opcode_modifier.no_lsuf
5944 && !i.tm.opcode_modifier.todword
5945 && !i.tm.opcode_modifier.toqword)
2eb952a4
L		 5946 i.suffix = 0;
5947 else if (!check_long_reg ())
29b0f896
AM		 5948 return 0;
5949 }
5950 else if (i.suffix == QWORD_MNEM_SUFFIX)
5951 {
955e1e6a
L		 5952 if (intel_syntax
5953 && i.tm.opcode_modifier.ignoresize
9f123b91
JB		 5954 && i.tm.opcode_modifier.no_qsuf
5955 && !i.tm.opcode_modifier.todword
5956 && !i.tm.opcode_modifier.toqword)
955e1e6a
L		 5957 i.suffix = 0;
5958 else if (!check_qword_reg ())
29b0f896
AM		 5959 return 0;
5960 }
5961 else if (i.suffix == WORD_MNEM_SUFFIX)
5962 {
2eb952a4
L		 5963 if (intel_syntax
5964 && i.tm.opcode_modifier.ignoresize
5965 && i.tm.opcode_modifier.no_wsuf)
5966 i.suffix = 0;
5967 else if (!check_word_reg ())
29b0f896
AM		 5968 return 0;
5969 }
40fb9820 5970 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5971 /* Do nothing if the instruction is going to ignore the prefix. */
5972 ;
5973 else
5974 abort ();
5975 }
40fb9820 5976 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5977 && !i.suffix
5978 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5979 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5980 {
5981 i.suffix = stackop_size;
5982 }
9306ca4a
JB		 5983 else if (intel_syntax
5984 && !i.suffix
40fb9820
L		 5985 && (i.tm.operand_types[0].bitfield.jumpabsolute
5986 || i.tm.opcode_modifier.jumpbyte
5987 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5988 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5989 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5990 {
5991 switch (flag_code)
5992 {
5993 case CODE_64BIT:
40fb9820 5994 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5995 {
5996 i.suffix = QWORD_MNEM_SUFFIX;
5997 break;
5998 }
1a0670f3 5999 /* Fall through. */
9306ca4a 6000 case CODE_32BIT:
40fb9820 6001 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 6002 i.suffix = LONG_MNEM_SUFFIX;
6003 break;
6004 case CODE_16BIT:
40fb9820 6005 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 6006 i.suffix = WORD_MNEM_SUFFIX;
6007 break;
6008 }
6009 }
252b5132 6010
9306ca4a 6011 if (!i.suffix)
29b0f896 6012 {
9306ca4a
JB		 6013 if (!intel_syntax)
6014 {
40fb9820 6015 if (i.tm.opcode_modifier.w)
9306ca4a 6016 {
4eed87de
AM		 6017 as_bad (_("no instruction mnemonic suffix given and "
6018 "no register operands; can't size instruction"));
9306ca4a
JB		 6019 return 0;
6020 }
6021 }
6022 else
6023 {
40fb9820 6024 unsigned int suffixes;
7ab9ffdd 6025
40fb9820
L		 6026 suffixes = !i.tm.opcode_modifier.no_bsuf;
6027 if (!i.tm.opcode_modifier.no_wsuf)
6028 suffixes |= 1 << 1;
6029 if (!i.tm.opcode_modifier.no_lsuf)
6030 suffixes |= 1 << 2;
fc4adea1 6031 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 6032 suffixes |= 1 << 3;
6033 if (!i.tm.opcode_modifier.no_ssuf)
6034 suffixes |= 1 << 4;
c2b9da16 6035 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
40fb9820
L		 6036 suffixes |= 1 << 5;
6037
6038 /* There are more than suffix matches. */
6039 if (i.tm.opcode_modifier.w
9306ca4a 6040 || ((suffixes & (suffixes - 1))
40fb9820
L		 6041 && !i.tm.opcode_modifier.defaultsize
6042 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 6043 {
6044 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
6045 return 0;
6046 }
6047 }
29b0f896 6048 }
252b5132 6049
d2224064
JB		 6050 /* Change the opcode based on the operand size given by i.suffix. */
6051 switch (i.suffix)
29b0f896 6052 {
d2224064
JB		 6053 /* Size floating point instruction. */
6054 case LONG_MNEM_SUFFIX:
6055 if (i.tm.opcode_modifier.floatmf)
6056 {
6057 i.tm.base_opcode ^= 4;
6058 break;
6059 }
6060 /* fall through */
6061 case WORD_MNEM_SUFFIX:
6062 case QWORD_MNEM_SUFFIX:
29b0f896 6063 /* It's not a byte, select word/dword operation. */
40fb9820 6064 if (i.tm.opcode_modifier.w)
29b0f896 6065 {
40fb9820 6066 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 6067 i.tm.base_opcode |= 8;
6068 else
6069 i.tm.base_opcode |= 1;
6070 }
d2224064
JB		 6071 /* fall through */
6072 case SHORT_MNEM_SUFFIX:
29b0f896
AM		 6073 /* Now select between word & dword operations via the operand
6074 size prefix, except for instructions that will ignore this
6075 prefix anyway. */
75c0a438
L		 6076 if (i.reg_operands > 0
6077 && i.types[0].bitfield.reg
6078 && i.tm.opcode_modifier.addrprefixopreg
6079 && (i.tm.opcode_modifier.immext
6080 || i.operands == 1))
cb712a9e 6081 {
ca61edf2
L		 6082 /* The address size override prefix changes the size of the
6083 first operand. */
40fb9820 6084 if ((flag_code == CODE_32BIT
75c0a438 6085 && i.op[0].regs->reg_type.bitfield.word)
40fb9820 6086 || (flag_code != CODE_32BIT
75c0a438 6087 && i.op[0].regs->reg_type.bitfield.dword))
cb712a9e
L		 6088 if (!add_prefix (ADDR_PREFIX_OPCODE))
6089 return 0;
6090 }
6091 else if (i.suffix != QWORD_MNEM_SUFFIX
40fb9820
L		 6092 && !i.tm.opcode_modifier.ignoresize
6093 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 6094 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
6095 || (flag_code == CODE_64BIT
40fb9820 6096 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 6097 {
6098 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 6099
40fb9820 6100 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 6101 prefix = ADDR_PREFIX_OPCODE;
252b5132 6102
29b0f896
AM		 6103 if (!add_prefix (prefix))
6104 return 0;
24eab124 6105 }
252b5132 6106
29b0f896
AM		 6107 /* Set mode64 for an operand. */
6108 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 6109 && flag_code == CODE_64BIT
d2224064 6110 && !i.tm.opcode_modifier.norex64
46e883c5 6111 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d2224064
JB		 6112 need rex64. */
6113 && ! (i.operands == 2
6114 && i.tm.base_opcode == 0x90
6115 && i.tm.extension_opcode == None
6116 && operand_type_equal (&i.types [0], &acc64)
6117 && operand_type_equal (&i.types [1], &acc64)))
6118 i.rex |= REX_W;
3e73aa7c 6119
d2224064 6120 break;
29b0f896 6121 }
7ecd2f8b 6122
c0a30a9f
L		 6123 if (i.reg_operands != 0
6124 && i.operands > 1
6125 && i.tm.opcode_modifier.addrprefixopreg
6126 && !i.tm.opcode_modifier.immext)
6127 {
6128 /* Check invalid register operand when the address size override
6129 prefix changes the size of register operands. */
6130 unsigned int op;
6131 enum { need_word, need_dword, need_qword } need;
6132
6133 if (flag_code == CODE_32BIT)
6134 need = i.prefix[ADDR_PREFIX] ? need_word : need_dword;
6135 else
6136 {
6137 if (i.prefix[ADDR_PREFIX])
6138 need = need_dword;
6139 else
6140 need = flag_code == CODE_64BIT ? need_qword : need_word;
6141 }
6142
6143 for (op = 0; op < i.operands; op++)
6144 if (i.types[op].bitfield.reg
6145 && ((need == need_word
6146 && !i.op[op].regs->reg_type.bitfield.word)
6147 || (need == need_dword
6148 && !i.op[op].regs->reg_type.bitfield.dword)
6149 || (need == need_qword
6150 && !i.op[op].regs->reg_type.bitfield.qword)))
6151 {
6152 as_bad (_("invalid register operand size for `%s'"),
6153 i.tm.name);
6154 return 0;
6155 }
6156 }
6157
29b0f896
AM		 6158 return 1;
6159}
3e73aa7c 6160
29b0f896 6161static int
543613e9 6162check_byte_reg (void)
29b0f896
AM		 6163{
6164 int op;
543613e9 6165
29b0f896
AM		 6166 for (op = i.operands; --op >= 0;)
6167 {
dc821c5f
JB		 6168 /* Skip non-register operands. */
6169 if (!i.types[op].bitfield.reg)
6170 continue;
6171
29b0f896
AM		 6172 /* If this is an eight bit register, it's OK. If it's the 16 or
6173 32 bit version of an eight bit register, we will just use the
6174 low portion, and that's OK too. */
dc821c5f 6175 if (i.types[op].bitfield.byte)
29b0f896
AM		 6176 continue;
6177
5a819eb9
JB		 6178 /* I/O port address operands are OK too. */
6179 if (i.tm.operand_types[op].bitfield.inoutportreg)
6180 continue;
6181
9344ff29
L		 6182 /* crc32 doesn't generate this warning. */
6183 if (i.tm.base_opcode == 0xf20f38f0)
6184 continue;
6185
dc821c5f
JB		 6186 if ((i.types[op].bitfield.word
6187 || i.types[op].bitfield.dword
6188 || i.types[op].bitfield.qword)
5a819eb9
JB		 6189 && i.op[op].regs->reg_num < 4
6190 /* Prohibit these changes in 64bit mode, since the lowering
6191 would be more complicated. */
6192 && flag_code != CODE_64BIT)
29b0f896 6193 {
29b0f896 6194#if REGISTER_WARNINGS
5a819eb9 6195 if (!quiet_warnings)
a540244d
L		 6196 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6197 register_prefix,
dc821c5f 6198 (i.op[op].regs + (i.types[op].bitfield.word
29b0f896
AM		 6199 ? REGNAM_AL - REGNAM_AX
6200 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 6201 register_prefix,
29b0f896
AM		 6202 i.op[op].regs->reg_name,
6203 i.suffix);
6204#endif
6205 continue;
6206 }
6207 /* Any other register is bad. */
dc821c5f 6208 if (i.types[op].bitfield.reg
40fb9820 6209 || i.types[op].bitfield.regmmx
1b54b8d7 6210 || i.types[op].bitfield.regsimd
40fb9820
L		 6211 || i.types[op].bitfield.sreg2
6212 || i.types[op].bitfield.sreg3
6213 || i.types[op].bitfield.control
6214 || i.types[op].bitfield.debug
ca0d63fe 6215 || i.types[op].bitfield.test)
29b0f896 6216 {
a540244d
L		 6217 as_bad (_("`%s%s' not allowed with `%s%c'"),
6218 register_prefix,
29b0f896
AM		 6219 i.op[op].regs->reg_name,
6220 i.tm.name,
6221 i.suffix);
6222 return 0;
6223 }
6224 }
6225 return 1;
6226}
6227
6228static int
e3bb37b5 6229check_long_reg (void)
29b0f896
AM		 6230{
6231 int op;
6232
6233 for (op = i.operands; --op >= 0;)
dc821c5f
JB		 6234 /* Skip non-register operands. */
6235 if (!i.types[op].bitfield.reg)
6236 continue;
29b0f896
AM		 6237 /* Reject eight bit registers, except where the template requires
6238 them. (eg. movzb) */
dc821c5f
JB		 6239 else if (i.types[op].bitfield.byte
6240 && (i.tm.operand_types[op].bitfield.reg
6241 || i.tm.operand_types[op].bitfield.acc)
6242 && (i.tm.operand_types[op].bitfield.word
6243 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6244 {
a540244d
L		 6245 as_bad (_("`%s%s' not allowed with `%s%c'"),
6246 register_prefix,
29b0f896
AM		 6247 i.op[op].regs->reg_name,
6248 i.tm.name,
6249 i.suffix);
6250 return 0;
6251 }
e4630f71 6252 /* Warn if the e prefix on a general reg is missing. */
29b0f896 6253 else if ((!quiet_warnings || flag_code == CODE_64BIT)
dc821c5f
JB		 6254 && i.types[op].bitfield.word
6255 && (i.tm.operand_types[op].bitfield.reg
6256 || i.tm.operand_types[op].bitfield.acc)
6257 && i.tm.operand_types[op].bitfield.dword)
29b0f896
AM		 6258 {
6259 /* Prohibit these changes in the 64bit mode, since the
6260 lowering is more complicated. */
6261 if (flag_code == CODE_64BIT)
252b5132 6262 {
2b5d6a91 6263 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 6264 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 6265 i.suffix);
6266 return 0;
252b5132 6267 }
29b0f896 6268#if REGISTER_WARNINGS
cecf1424
JB		 6269 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6270 register_prefix,
6271 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
6272 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 6273#endif
252b5132 6274 }
e4630f71 6275 /* Warn if the r prefix on a general reg is present. */
dc821c5f
JB		 6276 else if (i.types[op].bitfield.qword
6277 && (i.tm.operand_types[op].bitfield.reg
6278 || i.tm.operand_types[op].bitfield.acc)
6279 && i.tm.operand_types[op].bitfield.dword)
252b5132 6280 {
34828aad 6281 if (intel_syntax
ca61edf2 6282 && i.tm.opcode_modifier.toqword
1b54b8d7 6283 && !i.types[0].bitfield.regsimd)
34828aad 6284 {
ca61edf2 6285 /* Convert to QWORD. We want REX byte. */
34828aad
L		 6286 i.suffix = QWORD_MNEM_SUFFIX;
6287 }
6288 else
6289 {
2b5d6a91 6290 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 6291 register_prefix, i.op[op].regs->reg_name,
6292 i.suffix);
6293 return 0;
6294 }
29b0f896
AM		 6295 }
6296 return 1;
6297}
252b5132 6298
29b0f896 6299static int
e3bb37b5 6300check_qword_reg (void)
29b0f896
AM		 6301{
6302 int op;
252b5132 6303
29b0f896 6304 for (op = i.operands; --op >= 0; )
dc821c5f
JB		 6305 /* Skip non-register operands. */
6306 if (!i.types[op].bitfield.reg)
6307 continue;
29b0f896
AM		 6308 /* Reject eight bit registers, except where the template requires
6309 them. (eg. movzb) */
dc821c5f
JB		 6310 else if (i.types[op].bitfield.byte
6311 && (i.tm.operand_types[op].bitfield.reg
6312 || i.tm.operand_types[op].bitfield.acc)
6313 && (i.tm.operand_types[op].bitfield.word
6314 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6315 {
a540244d
L		 6316 as_bad (_("`%s%s' not allowed with `%s%c'"),
6317 register_prefix,
29b0f896
AM		 6318 i.op[op].regs->reg_name,
6319 i.tm.name,
6320 i.suffix);
6321 return 0;
6322 }
e4630f71 6323 /* Warn if the r prefix on a general reg is missing. */
dc821c5f
JB		 6324 else if ((i.types[op].bitfield.word
6325 || i.types[op].bitfield.dword)
6326 && (i.tm.operand_types[op].bitfield.reg
6327 || i.tm.operand_types[op].bitfield.acc)
6328 && i.tm.operand_types[op].bitfield.qword)
29b0f896
AM		 6329 {
6330 /* Prohibit these changes in the 64bit mode, since the
6331 lowering is more complicated. */
34828aad 6332 if (intel_syntax
ca61edf2 6333 && i.tm.opcode_modifier.todword
1b54b8d7 6334 && !i.types[0].bitfield.regsimd)
34828aad 6335 {
ca61edf2 6336 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 6337 i.suffix = LONG_MNEM_SUFFIX;
6338 }
6339 else
6340 {
2b5d6a91 6341 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 6342 register_prefix, i.op[op].regs->reg_name,
6343 i.suffix);
6344 return 0;
6345 }
252b5132 6346 }
29b0f896
AM		 6347 return 1;
6348}
252b5132 6349
29b0f896 6350static int
e3bb37b5 6351check_word_reg (void)
29b0f896
AM		 6352{
6353 int op;
6354 for (op = i.operands; --op >= 0;)
dc821c5f
JB		 6355 /* Skip non-register operands. */
6356 if (!i.types[op].bitfield.reg)
6357 continue;
29b0f896
AM		 6358 /* Reject eight bit registers, except where the template requires
6359 them. (eg. movzb) */
dc821c5f
JB		 6360 else if (i.types[op].bitfield.byte
6361 && (i.tm.operand_types[op].bitfield.reg
6362 || i.tm.operand_types[op].bitfield.acc)
6363 && (i.tm.operand_types[op].bitfield.word
6364 || i.tm.operand_types[op].bitfield.dword))
29b0f896 6365 {
a540244d
L		 6366 as_bad (_("`%s%s' not allowed with `%s%c'"),
6367 register_prefix,
29b0f896
AM		 6368 i.op[op].regs->reg_name,
6369 i.tm.name,
6370 i.suffix);
6371 return 0;
6372 }
e4630f71 6373 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 6374 else if ((!quiet_warnings || flag_code == CODE_64BIT)
dc821c5f
JB		 6375 && (i.types[op].bitfield.dword
6376 || i.types[op].bitfield.qword)
6377 && (i.tm.operand_types[op].bitfield.reg
6378 || i.tm.operand_types[op].bitfield.acc)
6379 && i.tm.operand_types[op].bitfield.word)
252b5132 6380 {
29b0f896
AM		 6381 /* Prohibit these changes in the 64bit mode, since the
6382 lowering is more complicated. */
6383 if (flag_code == CODE_64BIT)
252b5132 6384 {
2b5d6a91 6385 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 6386 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 6387 i.suffix);
6388 return 0;
252b5132 6389 }
29b0f896 6390#if REGISTER_WARNINGS
cecf1424
JB		 6391 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
6392 register_prefix,
6393 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
6394 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 6395#endif
6396 }
6397 return 1;
6398}
252b5132 6399
29b0f896 6400static int
40fb9820 6401update_imm (unsigned int j)
29b0f896 6402{
bc0844ae 6403 i386_operand_type overlap = i.types[j];
40fb9820
L		 6404 if ((overlap.bitfield.imm8
6405 || overlap.bitfield.imm8s
6406 || overlap.bitfield.imm16
6407 || overlap.bitfield.imm32
6408 || overlap.bitfield.imm32s
6409 || overlap.bitfield.imm64)
0dfbf9d7
L		 6410 && !operand_type_equal (&overlap, &imm8)
6411 && !operand_type_equal (&overlap, &imm8s)
6412 && !operand_type_equal (&overlap, &imm16)
6413 && !operand_type_equal (&overlap, &imm32)
6414 && !operand_type_equal (&overlap, &imm32s)
6415 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 6416 {
6417 if (i.suffix)
6418 {
40fb9820
L		 6419 i386_operand_type temp;
6420
0dfbf9d7 6421 operand_type_set (&temp, 0);
7ab9ffdd 6422 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 6423 {
6424 temp.bitfield.imm8 = overlap.bitfield.imm8;
6425 temp.bitfield.imm8s = overlap.bitfield.imm8s;
6426 }
6427 else if (i.suffix == WORD_MNEM_SUFFIX)
6428 temp.bitfield.imm16 = overlap.bitfield.imm16;
6429 else if (i.suffix == QWORD_MNEM_SUFFIX)
6430 {
6431 temp.bitfield.imm64 = overlap.bitfield.imm64;
6432 temp.bitfield.imm32s = overlap.bitfield.imm32s;
6433 }
6434 else
6435 temp.bitfield.imm32 = overlap.bitfield.imm32;
6436 overlap = temp;
29b0f896 6437 }
0dfbf9d7
L		 6438 else if (operand_type_equal (&overlap, &imm16_32_32s)
6439 || operand_type_equal (&overlap, &imm16_32)
6440 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 6441 {
40fb9820 6442 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 6443 overlap = imm16;
40fb9820 6444 else
65da13b5 6445 overlap = imm32s;
29b0f896 6446 }
0dfbf9d7
L		 6447 if (!operand_type_equal (&overlap, &imm8)
6448 && !operand_type_equal (&overlap, &imm8s)
6449 && !operand_type_equal (&overlap, &imm16)
6450 && !operand_type_equal (&overlap, &imm32)
6451 && !operand_type_equal (&overlap, &imm32s)
6452 && !operand_type_equal (&overlap, &imm64))
29b0f896 6453 {
4eed87de
AM		 6454 as_bad (_("no instruction mnemonic suffix given; "
6455 "can't determine immediate size"));
29b0f896
AM		 6456 return 0;
6457 }
6458 }
40fb9820 6459 i.types[j] = overlap;
29b0f896 6460
40fb9820
L		 6461 return 1;
6462}
6463
6464static int
6465finalize_imm (void)
6466{
bc0844ae 6467 unsigned int j, n;
29b0f896 6468
bc0844ae
L		 6469 /* Update the first 2 immediate operands. */
6470 n = i.operands > 2 ? 2 : i.operands;
6471 if (n)
6472 {
6473 for (j = 0; j < n; j++)
6474 if (update_imm (j) == 0)
6475 return 0;
40fb9820 6476
bc0844ae
L		 6477 /* The 3rd operand can't be immediate operand. */
6478 gas_assert (operand_type_check (i.types[2], imm) == 0);
6479 }
29b0f896
AM		 6480
6481 return 1;
6482}
6483
6484static int
e3bb37b5 6485process_operands (void)
29b0f896
AM		 6486{
6487 /* Default segment register this instruction will use for memory
6488 accesses. 0 means unknown. This is only for optimizing out
6489 unnecessary segment overrides. */
6490 const seg_entry *default_seg = 0;
6491
2426c15f 6492 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 6493 {
91d6fa6a
NC		 6494 unsigned int dupl = i.operands;
6495 unsigned int dest = dupl - 1;
9fcfb3d7
L		 6496 unsigned int j;
6497
c0f3af97 6498 /* The destination must be an xmm register. */
9c2799c2 6499 gas_assert (i.reg_operands
91d6fa6a 6500 && MAX_OPERANDS > dupl
7ab9ffdd 6501 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97 6502
1b54b8d7
JB		 6503 if (i.tm.operand_types[0].bitfield.acc
6504 && i.tm.operand_types[0].bitfield.xmmword)
e2ec9d29 6505 {
8cd7925b 6506 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 6507 {
6508 /* Keep xmm0 for instructions with VEX prefix and 3
6509 sources. */
1b54b8d7
JB		 6510 i.tm.operand_types[0].bitfield.acc = 0;
6511 i.tm.operand_types[0].bitfield.regsimd = 1;
c0f3af97
L		 6512 goto duplicate;
6513 }
e2ec9d29 6514 else
c0f3af97
L		 6515 {
6516 /* We remove the first xmm0 and keep the number of
6517 operands unchanged, which in fact duplicates the
6518 destination. */
6519 for (j = 1; j < i.operands; j++)
6520 {
6521 i.op[j - 1] = i.op[j];
6522 i.types[j - 1] = i.types[j];
6523 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6524 }
6525 }
6526 }
6527 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 6528 {
91d6fa6a 6529 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 6530 && (i.tm.opcode_modifier.vexsources
6531 == VEX3SOURCES));
c0f3af97
L		 6532
6533 /* Add the implicit xmm0 for instructions with VEX prefix
6534 and 3 sources. */
6535 for (j = i.operands; j > 0; j--)
6536 {
6537 i.op[j] = i.op[j - 1];
6538 i.types[j] = i.types[j - 1];
6539 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6540 }
6541 i.op[0].regs
6542 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 6543 i.types[0] = regxmm;
c0f3af97
L		 6544 i.tm.operand_types[0] = regxmm;
6545
6546 i.operands += 2;
6547 i.reg_operands += 2;
6548 i.tm.operands += 2;
6549
91d6fa6a 6550 dupl++;
c0f3af97 6551 dest++;
91d6fa6a
NC		 6552 i.op[dupl] = i.op[dest];
6553 i.types[dupl] = i.types[dest];
6554 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 6555 }
c0f3af97
L		 6556 else
6557 {
6558duplicate:
6559 i.operands++;
6560 i.reg_operands++;
6561 i.tm.operands++;
6562
91d6fa6a
NC		 6563 i.op[dupl] = i.op[dest];
6564 i.types[dupl] = i.types[dest];
6565 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 6566 }
6567
6568 if (i.tm.opcode_modifier.immext)
6569 process_immext ();
6570 }
1b54b8d7
JB		 6571 else if (i.tm.operand_types[0].bitfield.acc
6572 && i.tm.operand_types[0].bitfield.xmmword)
c0f3af97
L		 6573 {
6574 unsigned int j;
6575
9fcfb3d7
L		 6576 for (j = 1; j < i.operands; j++)
6577 {
6578 i.op[j - 1] = i.op[j];
6579 i.types[j - 1] = i.types[j];
6580
6581 /* We need to adjust fields in i.tm since they are used by
6582 build_modrm_byte. */
6583 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6584 }
6585
e2ec9d29
L		 6586 i.operands--;
6587 i.reg_operands--;
e2ec9d29
L		 6588 i.tm.operands--;
6589 }
920d2ddc
IT		 6590 else if (i.tm.opcode_modifier.implicitquadgroup)
6591 {
a477a8c4
JB		 6592 unsigned int regnum, first_reg_in_group, last_reg_in_group;
6593
920d2ddc 6594 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
10c17abd 6595 gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd);
a477a8c4
JB		 6596 regnum = register_number (i.op[1].regs);
6597 first_reg_in_group = regnum & ~3;
6598 last_reg_in_group = first_reg_in_group + 3;
6599 if (regnum != first_reg_in_group)
6600 as_warn (_("source register `%s%s' implicitly denotes"
6601 " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"),
6602 register_prefix, i.op[1].regs->reg_name,
6603 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6604 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6605 i.tm.name);
6606 }
e2ec9d29
L		 6607 else if (i.tm.opcode_modifier.regkludge)
6608 {
6609 /* The imul $imm, %reg instruction is converted into
6610 imul $imm, %reg, %reg, and the clr %reg instruction
6611 is converted into xor %reg, %reg. */
6612
6613 unsigned int first_reg_op;
6614
6615 if (operand_type_check (i.types[0], reg))
6616 first_reg_op = 0;
6617 else
6618 first_reg_op = 1;
6619 /* Pretend we saw the extra register operand. */
9c2799c2 6620 gas_assert (i.reg_operands == 1
7ab9ffdd 6621 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 6622 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6623 i.types[first_reg_op + 1] = i.types[first_reg_op];
6624 i.operands++;
6625 i.reg_operands++;
29b0f896
AM		 6626 }
6627
40fb9820 6628 if (i.tm.opcode_modifier.shortform)
29b0f896 6629 {
40fb9820
L		 6630 if (i.types[0].bitfield.sreg2
6631 || i.types[0].bitfield.sreg3)
29b0f896 6632 {
4eed87de
AM		 6633 if (i.tm.base_opcode == POP_SEG_SHORT
6634 && i.op[0].regs->reg_num == 1)
29b0f896 6635 {
a87af027 6636 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 6637 return 0;
29b0f896 6638 }
4eed87de
AM		 6639 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6640 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 6641 i.rex |= REX_B;
4eed87de
AM		 6642 }
6643 else
6644 {
7ab9ffdd 6645 /* The register or float register operand is in operand
85f10a01 6646 0 or 1. */
40fb9820 6647 unsigned int op;
7ab9ffdd 6648
ca0d63fe 6649 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
7ab9ffdd
L		 6650 || operand_type_check (i.types[0], reg))
6651 op = 0;
6652 else
6653 op = 1;
4eed87de
AM		 6654 /* Register goes in low 3 bits of opcode. */
6655 i.tm.base_opcode |= i.op[op].regs->reg_num;
6656 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 6657 i.rex |= REX_B;
40fb9820 6658 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 6659 {
4eed87de
AM		 6660 /* Warn about some common errors, but press on regardless.
6661 The first case can be generated by gcc (<= 2.8.1). */
6662 if (i.operands == 2)
6663 {
6664 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 6665 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 6666 register_prefix, i.op[!intel_syntax].regs->reg_name,
6667 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 6668 }
6669 else
6670 {
6671 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 6672 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6673 register_prefix, i.op[0].regs->reg_name);
4eed87de 6674 }
29b0f896
AM		 6675 }
6676 }
6677 }
40fb9820 6678 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 6679 {
6680 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 6681 must be put into the modrm byte). Now, we make the modrm and
6682 index base bytes based on all the info we've collected. */
29b0f896
AM		 6683
6684 default_seg = build_modrm_byte ();
6685 }
8a2ed489 6686 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 6687 {
6688 default_seg = &ds;
6689 }
40fb9820 6690 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 6691 {
6692 /* For the string instructions that allow a segment override
6693 on one of their operands, the default segment is ds. */
6694 default_seg = &ds;
6695 }
6696
75178d9d
L		 6697 if (i.tm.base_opcode == 0x8d /* lea */
6698 && i.seg[0]
6699 && !quiet_warnings)
30123838 6700 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 6701
6702 /* If a segment was explicitly specified, and the specified segment
6703 is not the default, use an opcode prefix to select it. If we
6704 never figured out what the default segment is, then default_seg
6705 will be zero at this point, and the specified segment prefix will
6706 always be used. */
29b0f896
AM		 6707 if ((i.seg[0]) && (i.seg[0] != default_seg))
6708 {
6709 if (!add_prefix (i.seg[0]->seg_prefix))
6710 return 0;
6711 }
6712 return 1;
6713}
6714
6715static const seg_entry *
e3bb37b5 6716build_modrm_byte (void)
29b0f896
AM		 6717{
6718 const seg_entry *default_seg = 0;
c0f3af97 6719 unsigned int source, dest;
8cd7925b 6720 int vex_3_sources;
c0f3af97 6721
8cd7925b 6722 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 6723 if (vex_3_sources)
6724 {
91d6fa6a 6725 unsigned int nds, reg_slot;
4c2c6516 6726 expressionS *exp;
c0f3af97 6727
6b8d3588 6728 dest = i.operands - 1;
c0f3af97 6729 nds = dest - 1;
922d8de8 6730
a683cc34 6731 /* There are 2 kinds of instructions:
bed3d976
JB		 6732 1. 5 operands: 4 register operands or 3 register operands
6733 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
6734 VexW0 or VexW1. The destination must be either XMM, YMM or
43234a1e 6735 ZMM register.
bed3d976 6736 2. 4 operands: 4 register operands or 3 register operands
2f1bada2 6737 plus 1 memory operand, with VexXDS. */
922d8de8 6738 gas_assert ((i.reg_operands == 4
bed3d976
JB		 6739 || (i.reg_operands == 3 && i.mem_operands == 1))
6740 && i.tm.opcode_modifier.vexvvvv == VEXXDS
dcd7e323
JB		 6741 && i.tm.opcode_modifier.vexw
6742 && i.tm.operand_types[dest].bitfield.regsimd);
a683cc34 6743
48db9223
JB		 6744 /* If VexW1 is set, the first non-immediate operand is the source and
6745 the second non-immediate one is encoded in the immediate operand. */
6746 if (i.tm.opcode_modifier.vexw == VEXW1)
6747 {
6748 source = i.imm_operands;
6749 reg_slot = i.imm_operands + 1;
6750 }
6751 else
6752 {
6753 source = i.imm_operands + 1;
6754 reg_slot = i.imm_operands;
6755 }
6756
a683cc34 6757 if (i.imm_operands == 0)
bed3d976
JB		 6758 {
6759 /* When there is no immediate operand, generate an 8bit
6760 immediate operand to encode the first operand. */
6761 exp = &im_expressions[i.imm_operands++];
6762 i.op[i.operands].imms = exp;
6763 i.types[i.operands] = imm8;
6764 i.operands++;
6765
6766 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6767 exp->X_op = O_constant;
6768 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6769 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6770 }
922d8de8 6771 else
bed3d976
JB		 6772 {
6773 unsigned int imm_slot;
a683cc34 6774
2f1bada2
JB		 6775 gas_assert (i.imm_operands == 1 && i.types[0].bitfield.vec_imm4);
6776
bed3d976
JB		 6777 if (i.tm.opcode_modifier.immext)
6778 {
6779 /* When ImmExt is set, the immediate byte is the last
6780 operand. */
6781 imm_slot = i.operands - 1;
6782 source--;
6783 reg_slot--;
6784 }
6785 else
6786 {
6787 imm_slot = 0;
6788
6789 /* Turn on Imm8 so that output_imm will generate it. */
6790 i.types[imm_slot].bitfield.imm8 = 1;
6791 }
6792
6793 gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd);
6794 i.op[imm_slot].imms->X_add_number
6795 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6796 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
bed3d976 6797 }
a683cc34 6798
10c17abd 6799 gas_assert (i.tm.operand_types[nds].bitfield.regsimd);
dae39acc 6800 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6801 }
6802 else
6803 source = dest = 0;
29b0f896
AM		 6804
6805 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6806 implicit registers do not count. If there are 3 register
6807 operands, it must be a instruction with VexNDS. For a
6808 instruction with VexNDD, the destination register is encoded
6809 in VEX prefix. If there are 4 register operands, it must be
6810 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6811 if (i.mem_operands == 0
6812 && ((i.reg_operands == 2
2426c15f 6813 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6814 || (i.reg_operands == 3
2426c15f 6815 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6816 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6817 {
cab737b9
L		 6818 switch (i.operands)
6819 {
6820 case 2:
6821 source = 0;
6822 break;
6823 case 3:
c81128dc
L		 6824 /* When there are 3 operands, one of them may be immediate,
6825 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6826 the first operand must be shift count register (cl) or it
6827 is an instruction with VexNDS. */
9c2799c2 6828 gas_assert (i.imm_operands == 1
7ab9ffdd 6829 || (i.imm_operands == 0
2426c15f 6830 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6831 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6832 if (operand_type_check (i.types[0], imm)
6833 || i.types[0].bitfield.shiftcount)
6834 source = 1;
6835 else
6836 source = 0;
cab737b9
L		 6837 break;
6838 case 4:
368d64cc
L		 6839 /* When there are 4 operands, the first two must be 8bit
6840 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6841 one.
6842
6843 For instructions with VexNDS, if the first operand
6844 an imm8, the source operand is the 2nd one. If the last
6845 operand is imm8, the source operand is the first one. */
9c2799c2 6846 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6847 && i.types[0].bitfield.imm8
6848 && i.types[1].bitfield.imm8)
2426c15f 6849 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6850 && i.imm_operands == 1
6851 && (i.types[0].bitfield.imm8
43234a1e
L		 6852 || i.types[i.operands - 1].bitfield.imm8
6853 || i.rounding)));
9f2670f2
L		 6854 if (i.imm_operands == 2)
6855 source = 2;
6856 else
c0f3af97
L		 6857 {
6858 if (i.types[0].bitfield.imm8)
6859 source = 1;
6860 else
6861 source = 0;
6862 }
c0f3af97
L		 6863 break;
6864 case 5:
e771e7c9 6865 if (is_evex_encoding (&i.tm))
43234a1e
L		 6866 {
6867 /* For EVEX instructions, when there are 5 operands, the
6868 first one must be immediate operand. If the second one
6869 is immediate operand, the source operand is the 3th
6870 one. If the last one is immediate operand, the source
6871 operand is the 2nd one. */
6872 gas_assert (i.imm_operands == 2
6873 && i.tm.opcode_modifier.sae
6874 && operand_type_check (i.types[0], imm));
6875 if (operand_type_check (i.types[1], imm))
6876 source = 2;
6877 else if (operand_type_check (i.types[4], imm))
6878 source = 1;
6879 else
6880 abort ();
6881 }
cab737b9
L		 6882 break;
6883 default:
6884 abort ();
6885 }
6886
c0f3af97
L		 6887 if (!vex_3_sources)
6888 {
6889 dest = source + 1;
6890
43234a1e
L		 6891 /* RC/SAE operand could be between DEST and SRC. That happens
6892 when one operand is GPR and the other one is XMM/YMM/ZMM
6893 register. */
6894 if (i.rounding && i.rounding->operand == (int) dest)
6895 dest++;
6896
2426c15f 6897 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6898 {
43234a1e 6899 /* For instructions with VexNDS, the register-only source
c5d0745b 6900 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
43234a1e
L		 6901 register. It is encoded in VEX prefix. We need to
6902 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6903
6904 i386_operand_type op;
6905 unsigned int vvvv;
6906
6907 /* Check register-only source operand when two source
6908 operands are swapped. */
6909 if (!i.tm.operand_types[source].bitfield.baseindex
6910 && i.tm.operand_types[dest].bitfield.baseindex)
6911 {
6912 vvvv = source;
6913 source = dest;
6914 }
6915 else
6916 vvvv = dest;
6917
6918 op = i.tm.operand_types[vvvv];
fa99fab2 6919 op.bitfield.regmem = 0;
c0f3af97 6920 if ((dest + 1) >= i.operands
dc821c5f
JB		 6921 || ((!op.bitfield.reg
6922 || (!op.bitfield.dword && !op.bitfield.qword))
10c17abd 6923 && !op.bitfield.regsimd
43234a1e 6924 && !operand_type_equal (&op, &regmask)))
c0f3af97 6925 abort ();
f12dc422 6926 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6927 dest++;
6928 }
6929 }
29b0f896
AM		 6930
6931 i.rm.mode = 3;
6932 /* One of the register operands will be encoded in the i.tm.reg
6933 field, the other in the combined i.tm.mode and i.tm.regmem
6934 fields. If no form of this instruction supports a memory
6935 destination operand, then we assume the source operand may
6936 sometimes be a memory operand and so we need to store the
6937 destination in the i.rm.reg field. */
40fb9820
L		 6938 if (!i.tm.operand_types[dest].bitfield.regmem
6939 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6940 {
6941 i.rm.reg = i.op[dest].regs->reg_num;
6942 i.rm.regmem = i.op[source].regs->reg_num;
6943 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6944 i.rex |= REX_R;
43234a1e
L		 6945 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6946 i.vrex |= REX_R;
29b0f896 6947 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6948 i.rex |= REX_B;
43234a1e
L		 6949 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6950 i.vrex |= REX_B;
29b0f896
AM		 6951 }
6952 else
6953 {
6954 i.rm.reg = i.op[source].regs->reg_num;
6955 i.rm.regmem = i.op[dest].regs->reg_num;
6956 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6957 i.rex |= REX_B;
43234a1e
L		 6958 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6959 i.vrex |= REX_B;
29b0f896 6960 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6961 i.rex |= REX_R;
43234a1e
L		 6962 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6963 i.vrex |= REX_R;
29b0f896 6964 }
e0c7f900 6965 if (flag_code != CODE_64BIT && (i.rex & REX_R))
c4a530c5 6966 {
e0c7f900 6967 if (!i.types[i.tm.operand_types[0].bitfield.regmem].bitfield.control)
c4a530c5 6968 abort ();
e0c7f900 6969 i.rex &= ~REX_R;
c4a530c5
JB		 6970 add_prefix (LOCK_PREFIX_OPCODE);
6971 }
29b0f896
AM		 6972 }
6973 else
6974 { /* If it's not 2 reg operands... */
c0f3af97
L		 6975 unsigned int mem;
6976
29b0f896
AM		 6977 if (i.mem_operands)
6978 {
6979 unsigned int fake_zero_displacement = 0;
99018f42 6980 unsigned int op;
4eed87de 6981
7ab9ffdd
L		 6982 for (op = 0; op < i.operands; op++)
6983 if (operand_type_check (i.types[op], anymem))
6984 break;
7ab9ffdd 6985 gas_assert (op < i.operands);
29b0f896 6986
6c30d220
L		 6987 if (i.tm.opcode_modifier.vecsib)
6988 {
6989 if (i.index_reg->reg_num == RegEiz
6990 || i.index_reg->reg_num == RegRiz)
6991 abort ();
6992
6993 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6994 if (!i.base_reg)
6995 {
6996 i.sib.base = NO_BASE_REGISTER;
6997 i.sib.scale = i.log2_scale_factor;
6998 i.types[op].bitfield.disp8 = 0;
6999 i.types[op].bitfield.disp16 = 0;
7000 i.types[op].bitfield.disp64 = 0;
43083a50 7001 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6c30d220
L		 7002 {
7003 /* Must be 32 bit */
7004 i.types[op].bitfield.disp32 = 1;
7005 i.types[op].bitfield.disp32s = 0;
7006 }
7007 else
7008 {
7009 i.types[op].bitfield.disp32 = 0;
7010 i.types[op].bitfield.disp32s = 1;
7011 }
7012 }
7013 i.sib.index = i.index_reg->reg_num;
7014 if ((i.index_reg->reg_flags & RegRex) != 0)
7015 i.rex |= REX_X;
43234a1e
L		 7016 if ((i.index_reg->reg_flags & RegVRex) != 0)
7017 i.vrex |= REX_X;
6c30d220
L		 7018 }
7019
29b0f896
AM		 7020 default_seg = &ds;
7021
7022 if (i.base_reg == 0)
7023 {
7024 i.rm.mode = 0;
7025 if (!i.disp_operands)
9bb129e8 7026 fake_zero_displacement = 1;
29b0f896
AM		 7027 if (i.index_reg == 0)
7028 {
73053c1f
JB		 7029 i386_operand_type newdisp;
7030
6c30d220 7031 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 7032 /* Operand is just <disp> */
20f0a1fc 7033 if (flag_code == CODE_64BIT)
29b0f896
AM		 7034 {
7035 /* 64bit mode overwrites the 32bit absolute
7036 addressing by RIP relative addressing and
7037 absolute addressing is encoded by one of the
7038 redundant SIB forms. */
7039 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7040 i.sib.base = NO_BASE_REGISTER;
7041 i.sib.index = NO_INDEX_REGISTER;
73053c1f 7042 newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32);
20f0a1fc 7043 }
fc225355
L		 7044 else if ((flag_code == CODE_16BIT)
7045 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 7046 {
7047 i.rm.regmem = NO_BASE_REGISTER_16;
73053c1f 7048 newdisp = disp16;
20f0a1fc
NC		 7049 }
7050 else
7051 {
7052 i.rm.regmem = NO_BASE_REGISTER;
73053c1f 7053 newdisp = disp32;
29b0f896 7054 }
73053c1f
JB		 7055 i.types[op] = operand_type_and_not (i.types[op], anydisp);
7056 i.types[op] = operand_type_or (i.types[op], newdisp);
29b0f896 7057 }
6c30d220 7058 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 7059 {
6c30d220 7060 /* !i.base_reg && i.index_reg */
db51cc60
L		 7061 if (i.index_reg->reg_num == RegEiz
7062 || i.index_reg->reg_num == RegRiz)
7063 i.sib.index = NO_INDEX_REGISTER;
7064 else
7065 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 7066 i.sib.base = NO_BASE_REGISTER;
7067 i.sib.scale = i.log2_scale_factor;
7068 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 7069 i.types[op].bitfield.disp8 = 0;
7070 i.types[op].bitfield.disp16 = 0;
7071 i.types[op].bitfield.disp64 = 0;
43083a50 7072 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
40fb9820
L		 7073 {
7074 /* Must be 32 bit */
7075 i.types[op].bitfield.disp32 = 1;
7076 i.types[op].bitfield.disp32s = 0;
7077 }
29b0f896 7078 else
40fb9820
L		 7079 {
7080 i.types[op].bitfield.disp32 = 0;
7081 i.types[op].bitfield.disp32s = 1;
7082 }
29b0f896 7083 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 7084 i.rex |= REX_X;
29b0f896
AM		 7085 }
7086 }
7087 /* RIP addressing for 64bit mode. */
9a04903e
JB		 7088 else if (i.base_reg->reg_num == RegRip ||
7089 i.base_reg->reg_num == RegEip)
29b0f896 7090 {
6c30d220 7091 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 7092 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 7093 i.types[op].bitfield.disp8 = 0;
7094 i.types[op].bitfield.disp16 = 0;
7095 i.types[op].bitfield.disp32 = 0;
7096 i.types[op].bitfield.disp32s = 1;
7097 i.types[op].bitfield.disp64 = 0;
71903a11 7098 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 7099 if (! i.disp_operands)
7100 fake_zero_displacement = 1;
29b0f896 7101 }
dc821c5f 7102 else if (i.base_reg->reg_type.bitfield.word)
29b0f896 7103 {
6c30d220 7104 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 7105 switch (i.base_reg->reg_num)
7106 {
7107 case 3: /* (%bx) */
7108 if (i.index_reg == 0)
7109 i.rm.regmem = 7;
7110 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
7111 i.rm.regmem = i.index_reg->reg_num - 6;
7112 break;
7113 case 5: /* (%bp) */
7114 default_seg = &ss;
7115 if (i.index_reg == 0)
7116 {
7117 i.rm.regmem = 6;
40fb9820 7118 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 7119 {
7120 /* fake (%bp) into 0(%bp) */
b5014f7a 7121 i.types[op].bitfield.disp8 = 1;
252b5132 7122 fake_zero_displacement = 1;
29b0f896
AM		 7123 }
7124 }
7125 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
7126 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
7127 break;
7128 default: /* (%si) -> 4 or (%di) -> 5 */
7129 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
7130 }
7131 i.rm.mode = mode_from_disp_size (i.types[op]);
7132 }
7133 else /* i.base_reg and 32/64 bit mode */
7134 {
7135 if (flag_code == CODE_64BIT
40fb9820
L		 7136 && operand_type_check (i.types[op], disp))
7137 {
73053c1f
JB		 7138 i.types[op].bitfield.disp16 = 0;
7139 i.types[op].bitfield.disp64 = 0;
40fb9820 7140 if (i.prefix[ADDR_PREFIX] == 0)
73053c1f
JB		 7141 {
7142 i.types[op].bitfield.disp32 = 0;
7143 i.types[op].bitfield.disp32s = 1;
7144 }
40fb9820 7145 else
73053c1f
JB		 7146 {
7147 i.types[op].bitfield.disp32 = 1;
7148 i.types[op].bitfield.disp32s = 0;
7149 }
40fb9820 7150 }
20f0a1fc 7151
6c30d220
L		 7152 if (!i.tm.opcode_modifier.vecsib)
7153 i.rm.regmem = i.base_reg->reg_num;
29b0f896 7154 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 7155 i.rex |= REX_B;
29b0f896
AM		 7156 i.sib.base = i.base_reg->reg_num;
7157 /* x86-64 ignores REX prefix bit here to avoid decoder
7158 complications. */
848930b2
JB		 7159 if (!(i.base_reg->reg_flags & RegRex)
7160 && (i.base_reg->reg_num == EBP_REG_NUM
7161 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 7162 default_seg = &ss;
848930b2 7163 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 7164 {
848930b2 7165 fake_zero_displacement = 1;
b5014f7a 7166 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 7167 }
7168 i.sib.scale = i.log2_scale_factor;
7169 if (i.index_reg == 0)
7170 {
6c30d220 7171 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 7172 /* <disp>(%esp) becomes two byte modrm with no index
7173 register. We've already stored the code for esp
7174 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
7175 Any base register besides %esp will not use the
7176 extra modrm byte. */
7177 i.sib.index = NO_INDEX_REGISTER;
29b0f896 7178 }
6c30d220 7179 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 7180 {
db51cc60
L		 7181 if (i.index_reg->reg_num == RegEiz
7182 || i.index_reg->reg_num == RegRiz)
7183 i.sib.index = NO_INDEX_REGISTER;
7184 else
7185 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 7186 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
7187 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 7188 i.rex |= REX_X;
29b0f896 7189 }
67a4f2b7
AO		 7190
7191 if (i.disp_operands
7192 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
7193 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
7194 i.rm.mode = 0;
7195 else
a501d77e
L		 7196 {
7197 if (!fake_zero_displacement
7198 && !i.disp_operands
7199 && i.disp_encoding)
7200 {
7201 fake_zero_displacement = 1;
7202 if (i.disp_encoding == disp_encoding_8bit)
7203 i.types[op].bitfield.disp8 = 1;
7204 else
7205 i.types[op].bitfield.disp32 = 1;
7206 }
7207 i.rm.mode = mode_from_disp_size (i.types[op]);
7208 }
29b0f896 7209 }
252b5132 7210
29b0f896
AM		 7211 if (fake_zero_displacement)
7212 {
7213 /* Fakes a zero displacement assuming that i.types[op]
7214 holds the correct displacement size. */
7215 expressionS *exp;
7216
9c2799c2 7217 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 7218 exp = &disp_expressions[i.disp_operands++];
7219 i.op[op].disps = exp;
7220 exp->X_op = O_constant;
7221 exp->X_add_number = 0;
7222 exp->X_add_symbol = (symbolS *) 0;
7223 exp->X_op_symbol = (symbolS *) 0;
7224 }
c0f3af97
L		 7225
7226 mem = op;
29b0f896 7227 }
c0f3af97
L		 7228 else
7229 mem = ~0;
252b5132 7230
8c43a48b 7231 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 7232 {
7233 if (operand_type_check (i.types[0], imm))
7234 i.vex.register_specifier = NULL;
7235 else
7236 {
7237 /* VEX.vvvv encodes one of the sources when the first
7238 operand is not an immediate. */
1ef99a7b 7239 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 7240 i.vex.register_specifier = i.op[0].regs;
7241 else
7242 i.vex.register_specifier = i.op[1].regs;
7243 }
7244
7245 /* Destination is a XMM register encoded in the ModRM.reg
7246 and VEX.R bit. */
7247 i.rm.reg = i.op[2].regs->reg_num;
7248 if ((i.op[2].regs->reg_flags & RegRex) != 0)
7249 i.rex |= REX_R;
7250
7251 /* ModRM.rm and VEX.B encodes the other source. */
7252 if (!i.mem_operands)
7253 {
7254 i.rm.mode = 3;
7255
1ef99a7b 7256 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 7257 i.rm.regmem = i.op[1].regs->reg_num;
7258 else
7259 i.rm.regmem = i.op[0].regs->reg_num;
7260
7261 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7262 i.rex |= REX_B;
7263 }
7264 }
2426c15f 7265 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 7266 {
7267 i.vex.register_specifier = i.op[2].regs;
7268 if (!i.mem_operands)
7269 {
7270 i.rm.mode = 3;
7271 i.rm.regmem = i.op[1].regs->reg_num;
7272 if ((i.op[1].regs->reg_flags & RegRex) != 0)
7273 i.rex |= REX_B;
7274 }
7275 }
29b0f896
AM		 7276 /* Fill in i.rm.reg or i.rm.regmem field with register operand
7277 (if any) based on i.tm.extension_opcode. Again, we must be
7278 careful to make sure that segment/control/debug/test/MMX
7279 registers are coded into the i.rm.reg field. */
f88c9eb0 7280 else if (i.reg_operands)
29b0f896 7281 {
99018f42 7282 unsigned int op;
7ab9ffdd
L		 7283 unsigned int vex_reg = ~0;
7284
7285 for (op = 0; op < i.operands; op++)
dc821c5f 7286 if (i.types[op].bitfield.reg
7ab9ffdd 7287 || i.types[op].bitfield.regmmx
1b54b8d7 7288 || i.types[op].bitfield.regsimd
7e8b059b 7289 || i.types[op].bitfield.regbnd
43234a1e 7290 || i.types[op].bitfield.regmask
7ab9ffdd
L		 7291 || i.types[op].bitfield.sreg2
7292 || i.types[op].bitfield.sreg3
7293 || i.types[op].bitfield.control
7294 || i.types[op].bitfield.debug
7295 || i.types[op].bitfield.test)
7296 break;
c0209578 7297
7ab9ffdd
L		 7298 if (vex_3_sources)
7299 op = dest;
2426c15f 7300 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 7301 {
7302 /* For instructions with VexNDS, the register-only
7303 source operand is encoded in VEX prefix. */
7304 gas_assert (mem != (unsigned int) ~0);
c0f3af97 7305
7ab9ffdd 7306 if (op > mem)
c0f3af97 7307 {
7ab9ffdd
L		 7308 vex_reg = op++;
7309 gas_assert (op < i.operands);
c0f3af97
L		 7310 }
7311 else
c0f3af97 7312 {
f12dc422
L		 7313 /* Check register-only source operand when two source
7314 operands are swapped. */
7315 if (!i.tm.operand_types[op].bitfield.baseindex
7316 && i.tm.operand_types[op + 1].bitfield.baseindex)
7317 {
7318 vex_reg = op;
7319 op += 2;
7320 gas_assert (mem == (vex_reg + 1)
7321 && op < i.operands);
7322 }
7323 else
7324 {
7325 vex_reg = op + 1;
7326 gas_assert (vex_reg < i.operands);
7327 }
c0f3af97 7328 }
7ab9ffdd 7329 }
2426c15f 7330 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 7331 {
f12dc422 7332 /* For instructions with VexNDD, the register destination
7ab9ffdd 7333 is encoded in VEX prefix. */
f12dc422
L		 7334 if (i.mem_operands == 0)
7335 {
7336 /* There is no memory operand. */
7337 gas_assert ((op + 2) == i.operands);
7338 vex_reg = op + 1;
7339 }
7340 else
8d63c93e 7341 {
ed438a93
JB		 7342 /* There are only 2 non-immediate operands. */
7343 gas_assert (op < i.imm_operands + 2
7344 && i.operands == i.imm_operands + 2);
7345 vex_reg = i.imm_operands + 1;
f12dc422 7346 }
7ab9ffdd
L		 7347 }
7348 else
7349 gas_assert (op < i.operands);
99018f42 7350
7ab9ffdd
L		 7351 if (vex_reg != (unsigned int) ~0)
7352 {
f12dc422 7353 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 7354
dc821c5f
JB		 7355 if ((!type->bitfield.reg
7356 || (!type->bitfield.dword && !type->bitfield.qword))
10c17abd 7357 && !type->bitfield.regsimd
43234a1e 7358 && !operand_type_equal (type, &regmask))
7ab9ffdd 7359 abort ();
f88c9eb0 7360
7ab9ffdd
L		 7361 i.vex.register_specifier = i.op[vex_reg].regs;
7362 }
7363
1b9f0c97
L		 7364 /* Don't set OP operand twice. */
7365 if (vex_reg != op)
7ab9ffdd 7366 {
1b9f0c97
L		 7367 /* If there is an extension opcode to put here, the
7368 register number must be put into the regmem field. */
7369 if (i.tm.extension_opcode != None)
7370 {
7371 i.rm.regmem = i.op[op].regs->reg_num;
7372 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7373 i.rex |= REX_B;
43234a1e
L		 7374 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7375 i.vrex |= REX_B;
1b9f0c97
L		 7376 }
7377 else
7378 {
7379 i.rm.reg = i.op[op].regs->reg_num;
7380 if ((i.op[op].regs->reg_flags & RegRex) != 0)
7381 i.rex |= REX_R;
43234a1e
L		 7382 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
7383 i.vrex |= REX_R;
1b9f0c97 7384 }
7ab9ffdd 7385 }
252b5132 7386
29b0f896
AM		 7387 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
7388 must set it to 3 to indicate this is a register operand
7389 in the regmem field. */
7390 if (!i.mem_operands)
7391 i.rm.mode = 3;
7392 }
252b5132 7393
29b0f896 7394 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 7395 if (i.tm.extension_opcode != None)
29b0f896
AM		 7396 i.rm.reg = i.tm.extension_opcode;
7397 }
7398 return default_seg;
7399}
252b5132 7400
29b0f896 7401static void
e3bb37b5 7402output_branch (void)
29b0f896
AM		 7403{
7404 char *p;
f8a5c266 7405 int size;
29b0f896
AM		 7406 int code16;
7407 int prefix;
7408 relax_substateT subtype;
7409 symbolS *sym;
7410 offsetT off;
7411
f8a5c266 7412 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 7413 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 7414
7415 prefix = 0;
7416 if (i.prefix[DATA_PREFIX] != 0)
252b5132 7417 {
29b0f896
AM		 7418 prefix = 1;
7419 i.prefixes -= 1;
7420 code16 ^= CODE16;
252b5132 7421 }
29b0f896
AM		 7422 /* Pentium4 branch hints. */
7423 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7424 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 7425 {
29b0f896
AM		 7426 prefix++;
7427 i.prefixes--;
7428 }
7429 if (i.prefix[REX_PREFIX] != 0)
7430 {
7431 prefix++;
7432 i.prefixes--;
2f66722d
AM		 7433 }
7434
7e8b059b
L		 7435 /* BND prefixed jump. */
7436 if (i.prefix[BND_PREFIX] != 0)
7437 {
7438 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7439 i.prefixes -= 1;
7440 }
7441
29b0f896
AM		 7442 if (i.prefixes != 0 && !intel_syntax)
7443 as_warn (_("skipping prefixes on this instruction"));
7444
7445 /* It's always a symbol; End frag & setup for relax.
7446 Make sure there is enough room in this frag for the largest
7447 instruction we may generate in md_convert_frag. This is 2
7448 bytes for the opcode and room for the prefix and largest
7449 displacement. */
7450 frag_grow (prefix + 2 + 4);
7451 /* Prefix and 1 opcode byte go in fr_fix. */
7452 p = frag_more (prefix + 1);
7453 if (i.prefix[DATA_PREFIX] != 0)
7454 *p++ = DATA_PREFIX_OPCODE;
7455 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7456 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7457 *p++ = i.prefix[SEG_PREFIX];
7458 if (i.prefix[REX_PREFIX] != 0)
7459 *p++ = i.prefix[REX_PREFIX];
7460 *p = i.tm.base_opcode;
7461
7462 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 7463 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 7464 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 7465 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 7466 else
f8a5c266 7467 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 7468 subtype |= code16;
3e73aa7c 7469
29b0f896
AM		 7470 sym = i.op[0].disps->X_add_symbol;
7471 off = i.op[0].disps->X_add_number;
3e73aa7c 7472
29b0f896
AM		 7473 if (i.op[0].disps->X_op != O_constant
7474 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 7475 {
29b0f896
AM		 7476 /* Handle complex expressions. */
7477 sym = make_expr_symbol (i.op[0].disps);
7478 off = 0;
7479 }
3e73aa7c 7480
29b0f896
AM		 7481 /* 1 possible extra opcode + 4 byte displacement go in var part.
7482 Pass reloc in fr_var. */
d258b828 7483 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 7484}
3e73aa7c 7485
bd7ab16b
L		 7486#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7487/* Return TRUE iff PLT32 relocation should be used for branching to
7488 symbol S. */
7489
7490static bfd_boolean
7491need_plt32_p (symbolS *s)
7492{
7493 /* PLT32 relocation is ELF only. */
7494 if (!IS_ELF)
7495 return FALSE;
7496
7497 /* Since there is no need to prepare for PLT branch on x86-64, we
7498 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
7499 be used as a marker for 32-bit PC-relative branches. */
7500 if (!object_64bit)
7501 return FALSE;
7502
7503 /* Weak or undefined symbol need PLT32 relocation. */
7504 if (S_IS_WEAK (s) || !S_IS_DEFINED (s))
7505 return TRUE;
7506
7507 /* Non-global symbol doesn't need PLT32 relocation. */
7508 if (! S_IS_EXTERNAL (s))
7509 return FALSE;
7510
7511 /* Other global symbols need PLT32 relocation. NB: Symbol with
7512 non-default visibilities are treated as normal global symbol
7513 so that PLT32 relocation can be used as a marker for 32-bit
7514 PC-relative branches. It is useful for linker relaxation. */
7515 return TRUE;
7516}
7517#endif
7518
29b0f896 7519static void
e3bb37b5 7520output_jump (void)
29b0f896
AM		 7521{
7522 char *p;
7523 int size;
3e02c1cc 7524 fixS *fixP;
bd7ab16b 7525 bfd_reloc_code_real_type jump_reloc = i.reloc[0];
29b0f896 7526
40fb9820 7527 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 7528 {
7529 /* This is a loop or jecxz type instruction. */
7530 size = 1;
7531 if (i.prefix[ADDR_PREFIX] != 0)
7532 {
7533 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7534 i.prefixes -= 1;
7535 }
7536 /* Pentium4 branch hints. */
7537 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7538 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7539 {
7540 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7541 i.prefixes--;
3e73aa7c
JH		 7542 }
7543 }
29b0f896
AM		 7544 else
7545 {
7546 int code16;
3e73aa7c 7547
29b0f896
AM		 7548 code16 = 0;
7549 if (flag_code == CODE_16BIT)
7550 code16 = CODE16;
3e73aa7c 7551
29b0f896
AM		 7552 if (i.prefix[DATA_PREFIX] != 0)
7553 {
7554 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7555 i.prefixes -= 1;
7556 code16 ^= CODE16;
7557 }
252b5132 7558
29b0f896
AM		 7559 size = 4;
7560 if (code16)
7561 size = 2;
7562 }
9fcc94b6 7563
29b0f896
AM		 7564 if (i.prefix[REX_PREFIX] != 0)
7565 {
7566 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7567 i.prefixes -= 1;
7568 }
252b5132 7569
7e8b059b
L		 7570 /* BND prefixed jump. */
7571 if (i.prefix[BND_PREFIX] != 0)
7572 {
7573 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7574 i.prefixes -= 1;
7575 }
7576
29b0f896
AM		 7577 if (i.prefixes != 0 && !intel_syntax)
7578 as_warn (_("skipping prefixes on this instruction"));
e0890092 7579
42164a71
L		 7580 p = frag_more (i.tm.opcode_length + size);
7581 switch (i.tm.opcode_length)
7582 {
7583 case 2:
7584 *p++ = i.tm.base_opcode >> 8;
1a0670f3 7585 /* Fall through. */
42164a71
L		 7586 case 1:
7587 *p++ = i.tm.base_opcode;
7588 break;
7589 default:
7590 abort ();
7591 }
e0890092 7592
bd7ab16b
L		 7593#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7594 if (size == 4
7595 && jump_reloc == NO_RELOC
7596 && need_plt32_p (i.op[0].disps->X_add_symbol))
7597 jump_reloc = BFD_RELOC_X86_64_PLT32;
7598#endif
7599
7600 jump_reloc = reloc (size, 1, 1, jump_reloc);
7601
3e02c1cc 7602 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
bd7ab16b 7603 i.op[0].disps, 1, jump_reloc);
3e02c1cc
AM		 7604
7605 /* All jumps handled here are signed, but don't use a signed limit
7606 check for 32 and 16 bit jumps as we want to allow wrap around at
7607 4G and 64k respectively. */
7608 if (size == 1)
7609 fixP->fx_signed = 1;
29b0f896 7610}
e0890092 7611
29b0f896 7612static void
e3bb37b5 7613output_interseg_jump (void)
29b0f896
AM		 7614{
7615 char *p;
7616 int size;
7617 int prefix;
7618 int code16;
252b5132 7619
29b0f896
AM		 7620 code16 = 0;
7621 if (flag_code == CODE_16BIT)
7622 code16 = CODE16;
a217f122 7623
29b0f896
AM		 7624 prefix = 0;
7625 if (i.prefix[DATA_PREFIX] != 0)
7626 {
7627 prefix = 1;
7628 i.prefixes -= 1;
7629 code16 ^= CODE16;
7630 }
7631 if (i.prefix[REX_PREFIX] != 0)
7632 {
7633 prefix++;
7634 i.prefixes -= 1;
7635 }
252b5132 7636
29b0f896
AM		 7637 size = 4;
7638 if (code16)
7639 size = 2;
252b5132 7640
29b0f896
AM		 7641 if (i.prefixes != 0 && !intel_syntax)
7642 as_warn (_("skipping prefixes on this instruction"));
252b5132 7643
29b0f896
AM		 7644 /* 1 opcode; 2 segment; offset */
7645 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 7646
29b0f896
AM		 7647 if (i.prefix[DATA_PREFIX] != 0)
7648 *p++ = DATA_PREFIX_OPCODE;
252b5132 7649
29b0f896
AM		 7650 if (i.prefix[REX_PREFIX] != 0)
7651 *p++ = i.prefix[REX_PREFIX];
252b5132 7652
29b0f896
AM		 7653 *p++ = i.tm.base_opcode;
7654 if (i.op[1].imms->X_op == O_constant)
7655 {
7656 offsetT n = i.op[1].imms->X_add_number;
252b5132 7657
29b0f896
AM		 7658 if (size == 2
7659 && !fits_in_unsigned_word (n)
7660 && !fits_in_signed_word (n))
7661 {
7662 as_bad (_("16-bit jump out of range"));
7663 return;
7664 }
7665 md_number_to_chars (p, n, size);
7666 }
7667 else
7668 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 7669 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 7670 if (i.op[0].imms->X_op != O_constant)
7671 as_bad (_("can't handle non absolute segment in `%s'"),
7672 i.tm.name);
7673 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7674}
a217f122 7675
29b0f896 7676static void
e3bb37b5 7677output_insn (void)
29b0f896 7678{
2bbd9c25
JJ		 7679 fragS *insn_start_frag;
7680 offsetT insn_start_off;
7681
29b0f896
AM		 7682 /* Tie dwarf2 debug info to the address at the start of the insn.
7683 We can't do this after the insn has been output as the current
7684 frag may have been closed off. eg. by frag_var. */
7685 dwarf2_emit_insn (0);
7686
2bbd9c25
JJ		 7687 insn_start_frag = frag_now;
7688 insn_start_off = frag_now_fix ();
7689
29b0f896 7690 /* Output jumps. */
40fb9820 7691 if (i.tm.opcode_modifier.jump)
29b0f896 7692 output_branch ();
40fb9820
L		 7693 else if (i.tm.opcode_modifier.jumpbyte
7694 || i.tm.opcode_modifier.jumpdword)
29b0f896 7695 output_jump ();
40fb9820 7696 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 7697 output_interseg_jump ();
7698 else
7699 {
7700 /* Output normal instructions here. */
7701 char *p;
7702 unsigned char *q;
47465058 7703 unsigned int j;
331d2d0d 7704 unsigned int prefix;
4dffcebc 7705
e4e00185
AS		 7706 if (avoid_fence
7707 && i.tm.base_opcode == 0xfae
7708 && i.operands == 1
7709 && i.imm_operands == 1
7710 && (i.op[0].imms->X_add_number == 0xe8
7711 || i.op[0].imms->X_add_number == 0xf0
7712 || i.op[0].imms->X_add_number == 0xf8))
7713 {
7714 /* Encode lfence, mfence, and sfence as
7715 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7716 offsetT val = 0x240483f0ULL;
7717 p = frag_more (5);
7718 md_number_to_chars (p, val, 5);
7719 return;
7720 }
7721
d022bddd
IT		 7722 /* Some processors fail on LOCK prefix. This options makes
7723 assembler ignore LOCK prefix and serves as a workaround. */
7724 if (omit_lock_prefix)
7725 {
7726 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7727 return;
7728 i.prefix[LOCK_PREFIX] = 0;
7729 }
7730
43234a1e
L		 7731 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7732 don't need the explicit prefix. */
7733 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 7734 {
c0f3af97 7735 switch (i.tm.opcode_length)
bc4bd9ab 7736 {
c0f3af97
L		 7737 case 3:
7738 if (i.tm.base_opcode & 0xff000000)
4dffcebc 7739 {
c0f3af97 7740 prefix = (i.tm.base_opcode >> 24) & 0xff;
bd59a631 7741 add_prefix (prefix);
c0f3af97
L		 7742 }
7743 break;
7744 case 2:
7745 if ((i.tm.base_opcode & 0xff0000) != 0)
7746 {
7747 prefix = (i.tm.base_opcode >> 16) & 0xff;
bd59a631
JB		 7748 if (!i.tm.cpu_flags.bitfield.cpupadlock
7749 || prefix != REPE_PREFIX_OPCODE
7750 || (i.prefix[REP_PREFIX] != REPE_PREFIX_OPCODE))
4dffcebc
L		 7751 add_prefix (prefix);
7752 }
c0f3af97
L		 7753 break;
7754 case 1:
7755 break;
390c91cf
L		 7756 case 0:
7757 /* Check for pseudo prefixes. */
7758 as_bad_where (insn_start_frag->fr_file,
7759 insn_start_frag->fr_line,
7760 _("pseudo prefix without instruction"));
7761 return;
c0f3af97
L		 7762 default:
7763 abort ();
bc4bd9ab 7764 }
c0f3af97 7765
6d19a37a 7766#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 7767 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7768 R_X86_64_GOTTPOFF relocation so that linker can safely
7769 perform IE->LE optimization. */
7770 if (x86_elf_abi == X86_64_X32_ABI
7771 && i.operands == 2
7772 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7773 && i.prefix[REX_PREFIX] == 0)
7774 add_prefix (REX_OPCODE);
6d19a37a 7775#endif
cf61b747 7776
c0f3af97
L		 7777 /* The prefix bytes. */
7778 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7779 if (*q)
7780 FRAG_APPEND_1_CHAR (*q);
0f10071e 7781 }
ae5c1c7b 7782 else
c0f3af97
L		 7783 {
7784 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7785 if (*q)
7786 switch (j)
7787 {
7788 case REX_PREFIX:
7789 /* REX byte is encoded in VEX prefix. */
7790 break;
7791 case SEG_PREFIX:
7792 case ADDR_PREFIX:
7793 FRAG_APPEND_1_CHAR (*q);
7794 break;
7795 default:
7796 /* There should be no other prefixes for instructions
7797 with VEX prefix. */
7798 abort ();
7799 }
7800
43234a1e
L		 7801 /* For EVEX instructions i.vrex should become 0 after
7802 build_evex_prefix. For VEX instructions upper 16 registers
7803 aren't available, so VREX should be 0. */
7804 if (i.vrex)
7805 abort ();
c0f3af97
L		 7806 /* Now the VEX prefix. */
7807 p = frag_more (i.vex.length);
7808 for (j = 0; j < i.vex.length; j++)
7809 p[j] = i.vex.bytes[j];
7810 }
252b5132 7811
29b0f896 7812 /* Now the opcode; be careful about word order here! */
4dffcebc 7813 if (i.tm.opcode_length == 1)
29b0f896
AM		 7814 {
7815 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7816 }
7817 else
7818 {
4dffcebc 7819 switch (i.tm.opcode_length)
331d2d0d 7820 {
43234a1e
L		 7821 case 4:
7822 p = frag_more (4);
7823 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7824 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7825 break;
4dffcebc 7826 case 3:
331d2d0d
L		 7827 p = frag_more (3);
7828 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7829 break;
7830 case 2:
7831 p = frag_more (2);
7832 break;
7833 default:
7834 abort ();
7835 break;
331d2d0d 7836 }
0f10071e 7837
29b0f896
AM		 7838 /* Put out high byte first: can't use md_number_to_chars! */
7839 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7840 *p = i.tm.base_opcode & 0xff;
7841 }
3e73aa7c 7842
29b0f896 7843 /* Now the modrm byte and sib byte (if present). */
40fb9820 7844 if (i.tm.opcode_modifier.modrm)
29b0f896 7845 {
4a3523fa
L		 7846 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7847 | i.rm.reg << 3
7848 | i.rm.mode << 6));
29b0f896
AM		 7849 /* If i.rm.regmem == ESP (4)
7850 && i.rm.mode != (Register mode)
7851 && not 16 bit
7852 ==> need second modrm byte. */
7853 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7854 && i.rm.mode != 3
dc821c5f 7855 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
4a3523fa
L		 7856 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7857 | i.sib.index << 3
7858 | i.sib.scale << 6));
29b0f896 7859 }
3e73aa7c 7860
29b0f896 7861 if (i.disp_operands)
2bbd9c25 7862 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7863
29b0f896 7864 if (i.imm_operands)
2bbd9c25 7865 output_imm (insn_start_frag, insn_start_off);
29b0f896 7866 }
252b5132 7867
29b0f896
AM		 7868#ifdef DEBUG386
7869 if (flag_debug)
7870 {
7b81dfbb 7871 pi ("" /*line*/, &i);
29b0f896
AM		 7872 }
7873#endif /* DEBUG386 */
7874}
252b5132 7875
e205caa7
L		 7876/* Return the size of the displacement operand N. */
7877
7878static int
7879disp_size (unsigned int n)
7880{
7881 int size = 4;
43234a1e 7882
b5014f7a 7883 if (i.types[n].bitfield.disp64)
40fb9820
L		 7884 size = 8;
7885 else if (i.types[n].bitfield.disp8)
7886 size = 1;
7887 else if (i.types[n].bitfield.disp16)
7888 size = 2;
e205caa7
L		 7889 return size;
7890}
7891
7892/* Return the size of the immediate operand N. */
7893
7894static int
7895imm_size (unsigned int n)
7896{
7897 int size = 4;
40fb9820
L		 7898 if (i.types[n].bitfield.imm64)
7899 size = 8;
7900 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7901 size = 1;
7902 else if (i.types[n].bitfield.imm16)
7903 size = 2;
e205caa7
L		 7904 return size;
7905}
7906
29b0f896 7907static void
64e74474 7908output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7909{
7910 char *p;
7911 unsigned int n;
252b5132 7912
29b0f896
AM		 7913 for (n = 0; n < i.operands; n++)
7914 {
b5014f7a 7915 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 7916 {
7917 if (i.op[n].disps->X_op == O_constant)
7918 {
e205caa7 7919 int size = disp_size (n);
43234a1e 7920 offsetT val = i.op[n].disps->X_add_number;
252b5132 7921
b5014f7a 7922 val = offset_in_range (val >> i.memshift, size);
29b0f896
AM		 7923 p = frag_more (size);
7924 md_number_to_chars (p, val, size);
7925 }
7926 else
7927 {
f86103b7 7928 enum bfd_reloc_code_real reloc_type;
e205caa7 7929 int size = disp_size (n);
40fb9820 7930 int sign = i.types[n].bitfield.disp32s;
29b0f896 7931 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
02a86693 7932 fixS *fixP;
29b0f896 7933
e205caa7 7934 /* We can't have 8 bit displacement here. */
9c2799c2 7935 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7936
29b0f896
AM		 7937 /* The PC relative address is computed relative
7938 to the instruction boundary, so in case immediate
7939 fields follows, we need to adjust the value. */
7940 if (pcrel && i.imm_operands)
7941 {
29b0f896 7942 unsigned int n1;
e205caa7 7943 int sz = 0;
252b5132 7944
29b0f896 7945 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7946 if (operand_type_check (i.types[n1], imm))
252b5132 7947 {
e205caa7
L		 7948 /* Only one immediate is allowed for PC
7949 relative address. */
9c2799c2 7950 gas_assert (sz == 0);
e205caa7
L		 7951 sz = imm_size (n1);
7952 i.op[n].disps->X_add_number -= sz;
252b5132 7953 }
29b0f896 7954 /* We should find the immediate. */
9c2799c2 7955 gas_assert (sz != 0);
29b0f896 7956 }
520dc8e8 7957
29b0f896 7958 p = frag_more (size);
d258b828 7959 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7960 if (GOT_symbol
2bbd9c25 7961 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7962 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7963 || reloc_type == BFD_RELOC_X86_64_32S
7964 || (reloc_type == BFD_RELOC_64
7965 && object_64bit))
d6ab8113
JB		 7966 && (i.op[n].disps->X_op == O_symbol
7967 || (i.op[n].disps->X_op == O_add
7968 && ((symbol_get_value_expression
7969 (i.op[n].disps->X_op_symbol)->X_op)
7970 == O_subtract))))
7971 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7972 {
7973 offsetT add;
7974
7975 if (insn_start_frag == frag_now)
7976 add = (p - frag_now->fr_literal) - insn_start_off;
7977 else
7978 {
7979 fragS *fr;
7980
7981 add = insn_start_frag->fr_fix - insn_start_off;
7982 for (fr = insn_start_frag->fr_next;
7983 fr && fr != frag_now; fr = fr->fr_next)
7984 add += fr->fr_fix;
7985 add += p - frag_now->fr_literal;
7986 }
7987
4fa24527 7988 if (!object_64bit)
7b81dfbb
AJ		 7989 {
7990 reloc_type = BFD_RELOC_386_GOTPC;
7991 i.op[n].imms->X_add_number += add;
7992 }
7993 else if (reloc_type == BFD_RELOC_64)
7994 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7995 else
7b81dfbb
AJ		 7996 /* Don't do the adjustment for x86-64, as there
7997 the pcrel addressing is relative to the _next_
7998 insn, and that is taken care of in other code. */
d6ab8113 7999 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 8000 }
02a86693
L		 8001 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
8002 size, i.op[n].disps, pcrel,
8003 reloc_type);
8004 /* Check for "call/jmp *mem", "mov mem, %reg",
8005 "test %reg, mem" and "binop mem, %reg" where binop
8006 is one of adc, add, and, cmp, or, sbb, sub, xor
0cb4071e
L		 8007 instructions. Always generate R_386_GOT32X for
8008 "sym*GOT" operand in 32-bit mode. */
8009 if ((generate_relax_relocations
8010 || (!object_64bit
8011 && i.rm.mode == 0
8012 && i.rm.regmem == 5))
8013 && (i.rm.mode == 2
8014 || (i.rm.mode == 0 && i.rm.regmem == 5))
02a86693
L		 8015 && ((i.operands == 1
8016 && i.tm.base_opcode == 0xff
8017 && (i.rm.reg == 2 || i.rm.reg == 4))
8018 || (i.operands == 2
8019 && (i.tm.base_opcode == 0x8b
8020 || i.tm.base_opcode == 0x85
8021 || (i.tm.base_opcode & 0xc7) == 0x03))))
8022 {
8023 if (object_64bit)
8024 {
8025 fixP->fx_tcbit = i.rex != 0;
8026 if (i.base_reg
8027 && (i.base_reg->reg_num == RegRip
8028 || i.base_reg->reg_num == RegEip))
8029 fixP->fx_tcbit2 = 1;
8030 }
8031 else
8032 fixP->fx_tcbit2 = 1;
8033 }
29b0f896
AM		 8034 }
8035 }
8036 }
8037}
252b5132 8038
29b0f896 8039static void
64e74474 8040output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 8041{
8042 char *p;
8043 unsigned int n;
252b5132 8044
29b0f896
AM		 8045 for (n = 0; n < i.operands; n++)
8046 {
43234a1e
L		 8047 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
8048 if (i.rounding && (int) n == i.rounding->operand)
8049 continue;
8050
40fb9820 8051 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 8052 {
8053 if (i.op[n].imms->X_op == O_constant)
8054 {
e205caa7 8055 int size = imm_size (n);
29b0f896 8056 offsetT val;
b4cac588 8057
29b0f896
AM		 8058 val = offset_in_range (i.op[n].imms->X_add_number,
8059 size);
8060 p = frag_more (size);
8061 md_number_to_chars (p, val, size);
8062 }
8063 else
8064 {
8065 /* Not absolute_section.
8066 Need a 32-bit fixup (don't support 8bit
8067 non-absolute imms). Try to support other
8068 sizes ... */
f86103b7 8069 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 8070 int size = imm_size (n);
8071 int sign;
29b0f896 8072
40fb9820 8073 if (i.types[n].bitfield.imm32s
a7d61044 8074 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 8075 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 8076 sign = 1;
e205caa7
L		 8077 else
8078 sign = 0;
520dc8e8 8079
29b0f896 8080 p = frag_more (size);
d258b828 8081 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 8082
2bbd9c25
JJ		 8083 /* This is tough to explain. We end up with this one if we
8084 * have operands that look like
8085 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
8086 * obtain the absolute address of the GOT, and it is strongly
8087 * preferable from a performance point of view to avoid using
8088 * a runtime relocation for this. The actual sequence of
8089 * instructions often look something like:
8090 *
8091 * call .L66
8092 * .L66:
8093 * popl %ebx
8094 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
8095 *
8096 * The call and pop essentially return the absolute address
8097 * of the label .L66 and store it in %ebx. The linker itself
8098 * will ultimately change the first operand of the addl so
8099 * that %ebx points to the GOT, but to keep things simple, the
8100 * .o file must have this operand set so that it generates not
8101 * the absolute address of .L66, but the absolute address of
8102 * itself. This allows the linker itself simply treat a GOTPC
8103 * relocation as asking for a pcrel offset to the GOT to be
8104 * added in, and the addend of the relocation is stored in the
8105 * operand field for the instruction itself.
8106 *
8107 * Our job here is to fix the operand so that it would add
8108 * the correct offset so that %ebx would point to itself. The
8109 * thing that is tricky is that .-.L66 will point to the
8110 * beginning of the instruction, so we need to further modify
8111 * the operand so that it will point to itself. There are
8112 * other cases where you have something like:
8113 *
8114 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
8115 *
8116 * and here no correction would be required. Internally in
8117 * the assembler we treat operands of this form as not being
8118 * pcrel since the '.' is explicitly mentioned, and I wonder
8119 * whether it would simplify matters to do it this way. Who
8120 * knows. In earlier versions of the PIC patches, the
8121 * pcrel_adjust field was used to store the correction, but
8122 * since the expression is not pcrel, I felt it would be
8123 * confusing to do it this way. */
8124
d6ab8113 8125 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 8126 || reloc_type == BFD_RELOC_X86_64_32S
8127 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 8128 && GOT_symbol
8129 && GOT_symbol == i.op[n].imms->X_add_symbol
8130 && (i.op[n].imms->X_op == O_symbol
8131 || (i.op[n].imms->X_op == O_add
8132 && ((symbol_get_value_expression
8133 (i.op[n].imms->X_op_symbol)->X_op)
8134 == O_subtract))))
8135 {
2bbd9c25
JJ		 8136 offsetT add;
8137
8138 if (insn_start_frag == frag_now)
8139 add = (p - frag_now->fr_literal) - insn_start_off;
8140 else
8141 {
8142 fragS *fr;
8143
8144 add = insn_start_frag->fr_fix - insn_start_off;
8145 for (fr = insn_start_frag->fr_next;
8146 fr && fr != frag_now; fr = fr->fr_next)
8147 add += fr->fr_fix;
8148 add += p - frag_now->fr_literal;
8149 }
8150
4fa24527 8151 if (!object_64bit)
d6ab8113 8152 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 8153 else if (size == 4)
d6ab8113 8154 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 8155 else if (size == 8)
8156 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 8157 i.op[n].imms->X_add_number += add;
29b0f896 8158 }
29b0f896
AM		 8159 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
8160 i.op[n].imms, 0, reloc_type);
8161 }
8162 }
8163 }
252b5132
RH		 8164}
8165\f
d182319b
JB		 8166/* x86_cons_fix_new is called via the expression parsing code when a
8167 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 8168static int cons_sign = -1;
8169
8170void
e3bb37b5 8171x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 8172 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 8173{
d258b828 8174 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 8175
8176#ifdef TE_PE
8177 if (exp->X_op == O_secrel)
8178 {
8179 exp->X_op = O_symbol;
8180 r = BFD_RELOC_32_SECREL;
8181 }
8182#endif
8183
8184 fix_new_exp (frag, off, len, exp, 0, r);
8185}
8186
357d1bd8
L		 8187/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
8188 purpose of the `.dc.a' internal pseudo-op. */
8189
8190int
8191x86_address_bytes (void)
8192{
8193 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
8194 return 4;
8195 return stdoutput->arch_info->bits_per_address / 8;
8196}
8197
d382c579
TG		 8198#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
8199 || defined (LEX_AT)
d258b828 8200# define lex_got(reloc, adjust, types) NULL
718ddfc0 8201#else
f3c180ae
AM		 8202/* Parse operands of the form
8203 <symbol>@GOTOFF+<nnn>
8204 and similar .plt or .got references.
8205
8206 If we find one, set up the correct relocation in RELOC and copy the
8207 input string, minus the `@GOTOFF' into a malloc'd buffer for
8208 parsing by the calling routine. Return this buffer, and if ADJUST
8209 is non-null set it to the length of the string we removed from the
8210 input line. Otherwise return NULL. */
8211static char *
91d6fa6a 8212lex_got (enum bfd_reloc_code_real *rel,
64e74474 8213 int *adjust,
d258b828 8214 i386_operand_type *types)
f3c180ae 8215{
7b81dfbb
AJ		 8216 /* Some of the relocations depend on the size of what field is to
8217 be relocated. But in our callers i386_immediate and i386_displacement
8218 we don't yet know the operand size (this will be set by insn
8219 matching). Hence we record the word32 relocation here,
8220 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 8221 static const struct {
8222 const char *str;
cff8d58a 8223 int len;
4fa24527 8224 const enum bfd_reloc_code_real rel[2];
40fb9820 8225 const i386_operand_type types64;
f3c180ae 8226 } gotrel[] = {
8ce3d284 8227#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 8228 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
8229 BFD_RELOC_SIZE32 },
8230 OPERAND_TYPE_IMM32_64 },
8ce3d284 8231#endif
cff8d58a
L		 8232 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
8233 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 8234 OPERAND_TYPE_IMM64 },
cff8d58a
L		 8235 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
8236 BFD_RELOC_X86_64_PLT32 },
40fb9820 8237 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8238 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
8239 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 8240 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 8241 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
8242 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 8243 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 8244 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
8245 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 8246 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8247 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
8248 BFD_RELOC_X86_64_TLSGD },
40fb9820 8249 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8250 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
8251 _dummy_first_bfd_reloc_code_real },
40fb9820 8252 OPERAND_TYPE_NONE },
cff8d58a
L		 8253 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
8254 BFD_RELOC_X86_64_TLSLD },
40fb9820 8255 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8256 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
8257 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 8258 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8259 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
8260 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 8261 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 8262 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
8263 _dummy_first_bfd_reloc_code_real },
40fb9820 8264 OPERAND_TYPE_NONE },
cff8d58a
L		 8265 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
8266 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 8267 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 8268 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
8269 _dummy_first_bfd_reloc_code_real },
40fb9820 8270 OPERAND_TYPE_NONE },
cff8d58a
L		 8271 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
8272 _dummy_first_bfd_reloc_code_real },
40fb9820 8273 OPERAND_TYPE_NONE },
cff8d58a
L		 8274 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
8275 BFD_RELOC_X86_64_GOT32 },
40fb9820 8276 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 8277 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
8278 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 8279 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 8280 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
8281 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 8282 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 8283 };
8284 char *cp;
8285 unsigned int j;
8286
d382c579 8287#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 8288 if (!IS_ELF)
8289 return NULL;
d382c579 8290#endif
718ddfc0 8291
f3c180ae 8292 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 8293 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 8294 return NULL;
8295
47465058 8296 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 8297 {
cff8d58a 8298 int len = gotrel[j].len;
28f81592 8299 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 8300 {
4fa24527 8301 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 8302 {
28f81592
AM		 8303 int first, second;
8304 char *tmpbuf, *past_reloc;
f3c180ae 8305
91d6fa6a 8306 *rel = gotrel[j].rel[object_64bit];
f3c180ae 8307
3956db08
JB		 8308 if (types)
8309 {
8310 if (flag_code != CODE_64BIT)
40fb9820
L		 8311 {
8312 types->bitfield.imm32 = 1;
8313 types->bitfield.disp32 = 1;
8314 }
3956db08
JB		 8315 else
8316 *types = gotrel[j].types64;
8317 }
8318
8fd4256d 8319 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 8320 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
8321
28f81592 8322 /* The length of the first part of our input line. */
f3c180ae 8323 first = cp - input_line_pointer;
28f81592
AM		 8324
8325 /* The second part goes from after the reloc token until
67c11a9b 8326 (and including) an end_of_line char or comma. */
28f81592 8327 past_reloc = cp + 1 + len;
67c11a9b
AM		 8328 cp = past_reloc;
8329 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8330 ++cp;
8331 second = cp + 1 - past_reloc;
28f81592
AM		 8332
8333 /* Allocate and copy string. The trailing NUL shouldn't
8334 be necessary, but be safe. */
add39d23 8335 tmpbuf = XNEWVEC (char, first + second + 2);
f3c180ae 8336 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 8337 if (second != 0 && *past_reloc != ' ')
8338 /* Replace the relocation token with ' ', so that
8339 errors like foo@GOTOFF1 will be detected. */
8340 tmpbuf[first++] = ' ';
af89796a
L		 8341 else
8342 /* Increment length by 1 if the relocation token is
8343 removed. */
8344 len++;
8345 if (adjust)
8346 *adjust = len;
0787a12d
AM		 8347 memcpy (tmpbuf + first, past_reloc, second);
8348 tmpbuf[first + second] = '\0';
f3c180ae
AM		 8349 return tmpbuf;
8350 }
8351
4fa24527
JB		 8352 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8353 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 8354 return NULL;
8355 }
8356 }
8357
8358 /* Might be a symbol version string. Don't as_bad here. */
8359 return NULL;
8360}
4e4f7c87 8361#endif
f3c180ae 8362
a988325c
NC		 8363#ifdef TE_PE
8364#ifdef lex_got
8365#undef lex_got
8366#endif
8367/* Parse operands of the form
8368 <symbol>@SECREL32+<nnn>
8369
8370 If we find one, set up the correct relocation in RELOC and copy the
8371 input string, minus the `@SECREL32' into a malloc'd buffer for
8372 parsing by the calling routine. Return this buffer, and if ADJUST
8373 is non-null set it to the length of the string we removed from the
34bca508
L		 8374 input line. Otherwise return NULL.
8375
a988325c
NC		 8376 This function is copied from the ELF version above adjusted for PE targets. */
8377
8378static char *
8379lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
8380 int *adjust ATTRIBUTE_UNUSED,
d258b828 8381 i386_operand_type *types)
a988325c
NC		 8382{
8383 static const struct
8384 {
8385 const char *str;
8386 int len;
8387 const enum bfd_reloc_code_real rel[2];
8388 const i386_operand_type types64;
8389 }
8390 gotrel[] =
8391 {
8392 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
8393 BFD_RELOC_32_SECREL },
8394 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
8395 };
8396
8397 char *cp;
8398 unsigned j;
8399
8400 for (cp = input_line_pointer; *cp != '@'; cp++)
8401 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
8402 return NULL;
8403
8404 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
8405 {
8406 int len = gotrel[j].len;
8407
8408 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
8409 {
8410 if (gotrel[j].rel[object_64bit] != 0)
8411 {
8412 int first, second;
8413 char *tmpbuf, *past_reloc;
8414
8415 *rel = gotrel[j].rel[object_64bit];
8416 if (adjust)
8417 *adjust = len;
8418
8419 if (types)
8420 {
8421 if (flag_code != CODE_64BIT)
8422 {
8423 types->bitfield.imm32 = 1;
8424 types->bitfield.disp32 = 1;
8425 }
8426 else
8427 *types = gotrel[j].types64;
8428 }
8429
8430 /* The length of the first part of our input line. */
8431 first = cp - input_line_pointer;
8432
8433 /* The second part goes from after the reloc token until
8434 (and including) an end_of_line char or comma. */
8435 past_reloc = cp + 1 + len;
8436 cp = past_reloc;
8437 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
8438 ++cp;
8439 second = cp + 1 - past_reloc;
8440
8441 /* Allocate and copy string. The trailing NUL shouldn't
8442 be necessary, but be safe. */
add39d23 8443 tmpbuf = XNEWVEC (char, first + second + 2);
a988325c
NC		 8444 memcpy (tmpbuf, input_line_pointer, first);
8445 if (second != 0 && *past_reloc != ' ')
8446 /* Replace the relocation token with ' ', so that
8447 errors like foo@SECLREL321 will be detected. */
8448 tmpbuf[first++] = ' ';
8449 memcpy (tmpbuf + first, past_reloc, second);
8450 tmpbuf[first + second] = '\0';
8451 return tmpbuf;
8452 }
8453
8454 as_bad (_("@%s reloc is not supported with %d-bit output format"),
8455 gotrel[j].str, 1 << (5 + object_64bit));
8456 return NULL;
8457 }
8458 }
8459
8460 /* Might be a symbol version string. Don't as_bad here. */
8461 return NULL;
8462}
8463
8464#endif /* TE_PE */
8465
62ebcb5c 8466bfd_reloc_code_real_type
e3bb37b5 8467x86_cons (expressionS *exp, int size)
f3c180ae 8468{
62ebcb5c
AM		 8469 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8470
ee86248c
JB		 8471 intel_syntax = -intel_syntax;
8472
3c7b9c2c 8473 exp->X_md = 0;
4fa24527 8474 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 8475 {
8476 /* Handle @GOTOFF and the like in an expression. */
8477 char *save;
8478 char *gotfree_input_line;
4a57f2cf 8479 int adjust = 0;
f3c180ae
AM		 8480
8481 save = input_line_pointer;
d258b828 8482 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 8483 if (gotfree_input_line)
8484 input_line_pointer = gotfree_input_line;
8485
8486 expression (exp);
8487
8488 if (gotfree_input_line)
8489 {
8490 /* expression () has merrily parsed up to the end of line,
8491 or a comma - in the wrong buffer. Transfer how far
8492 input_line_pointer has moved to the right buffer. */
8493 input_line_pointer = (save
8494 + (input_line_pointer - gotfree_input_line)
8495 + adjust);
8496 free (gotfree_input_line);
3992d3b7
AM		 8497 if (exp->X_op == O_constant
8498 || exp->X_op == O_absent
8499 || exp->X_op == O_illegal
0398aac5 8500 || exp->X_op == O_register
3992d3b7
AM		 8501 || exp->X_op == O_big)
8502 {
8503 char c = *input_line_pointer;
8504 *input_line_pointer = 0;
8505 as_bad (_("missing or invalid expression `%s'"), save);
8506 *input_line_pointer = c;
8507 }
f3c180ae
AM		 8508 }
8509 }
8510 else
8511 expression (exp);
ee86248c
JB		 8512
8513 intel_syntax = -intel_syntax;
8514
8515 if (intel_syntax)
8516 i386_intel_simplify (exp);
62ebcb5c
AM		 8517
8518 return got_reloc;
f3c180ae 8519}
f3c180ae 8520
9f32dd5b
L		 8521static void
8522signed_cons (int size)
6482c264 8523{
d182319b
JB		 8524 if (flag_code == CODE_64BIT)
8525 cons_sign = 1;
8526 cons (size);
8527 cons_sign = -1;
6482c264
NC		 8528}
8529
d182319b 8530#ifdef TE_PE
6482c264 8531static void
7016a5d5 8532pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 8533{
8534 expressionS exp;
8535
8536 do
8537 {
8538 expression (&exp);
8539 if (exp.X_op == O_symbol)
8540 exp.X_op = O_secrel;
8541
8542 emit_expr (&exp, 4);
8543 }
8544 while (*input_line_pointer++ == ',');
8545
8546 input_line_pointer--;
8547 demand_empty_rest_of_line ();
8548}
6482c264
NC		 8549#endif
8550
43234a1e
L		 8551/* Handle Vector operations. */
8552
8553static char *
8554check_VecOperations (char *op_string, char *op_end)
8555{
8556 const reg_entry *mask;
8557 const char *saved;
8558 char *end_op;
8559
8560 while (*op_string
8561 && (op_end == NULL || op_string < op_end))
8562 {
8563 saved = op_string;
8564 if (*op_string == '{')
8565 {
8566 op_string++;
8567
8568 /* Check broadcasts. */
8569 if (strncmp (op_string, "1to", 3) == 0)
8570 {
8571 int bcst_type;
8572
8573 if (i.broadcast)
8574 goto duplicated_vec_op;
8575
8576 op_string += 3;
8577 if (*op_string == '8')
8e6e0792 8578 bcst_type = 8;
b28d1bda 8579 else if (*op_string == '4')
8e6e0792 8580 bcst_type = 4;
b28d1bda 8581 else if (*op_string == '2')
8e6e0792 8582 bcst_type = 2;
43234a1e
L		 8583 else if (*op_string == '1'
8584 && *(op_string+1) == '6')
8585 {
8e6e0792 8586 bcst_type = 16;
43234a1e
L		 8587 op_string++;
8588 }
8589 else
8590 {
8591 as_bad (_("Unsupported broadcast: `%s'"), saved);
8592 return NULL;
8593 }
8594 op_string++;
8595
8596 broadcast_op.type = bcst_type;
8597 broadcast_op.operand = this_operand;
8598 i.broadcast = &broadcast_op;
8599 }
8600 /* Check masking operation. */
8601 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8602 {
8603 /* k0 can't be used for write mask. */
6d2cd6b2 8604 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
43234a1e 8605 {
6d2cd6b2
JB		 8606 as_bad (_("`%s%s' can't be used for write mask"),
8607 register_prefix, mask->reg_name);
43234a1e
L		 8608 return NULL;
8609 }
8610
8611 if (!i.mask)
8612 {
8613 mask_op.mask = mask;
8614 mask_op.zeroing = 0;
8615 mask_op.operand = this_operand;
8616 i.mask = &mask_op;
8617 }
8618 else
8619 {
8620 if (i.mask->mask)
8621 goto duplicated_vec_op;
8622
8623 i.mask->mask = mask;
8624
8625 /* Only "{z}" is allowed here. No need to check
8626 zeroing mask explicitly. */
8627 if (i.mask->operand != this_operand)
8628 {
8629 as_bad (_("invalid write mask `%s'"), saved);
8630 return NULL;
8631 }
8632 }
8633
8634 op_string = end_op;
8635 }
8636 /* Check zeroing-flag for masking operation. */
8637 else if (*op_string == 'z')
8638 {
8639 if (!i.mask)
8640 {
8641 mask_op.mask = NULL;
8642 mask_op.zeroing = 1;
8643 mask_op.operand = this_operand;
8644 i.mask = &mask_op;
8645 }
8646 else
8647 {
8648 if (i.mask->zeroing)
8649 {
8650 duplicated_vec_op:
8651 as_bad (_("duplicated `%s'"), saved);
8652 return NULL;
8653 }
8654
8655 i.mask->zeroing = 1;
8656
8657 /* Only "{%k}" is allowed here. No need to check mask
8658 register explicitly. */
8659 if (i.mask->operand != this_operand)
8660 {
8661 as_bad (_("invalid zeroing-masking `%s'"),
8662 saved);
8663 return NULL;
8664 }
8665 }
8666
8667 op_string++;
8668 }
8669 else
8670 goto unknown_vec_op;
8671
8672 if (*op_string != '}')
8673 {
8674 as_bad (_("missing `}' in `%s'"), saved);
8675 return NULL;
8676 }
8677 op_string++;
0ba3a731
L		 8678
8679 /* Strip whitespace since the addition of pseudo prefixes
8680 changed how the scrubber treats '{'. */
8681 if (is_space_char (*op_string))
8682 ++op_string;
8683
43234a1e
L		 8684 continue;
8685 }
8686 unknown_vec_op:
8687 /* We don't know this one. */
8688 as_bad (_("unknown vector operation: `%s'"), saved);
8689 return NULL;
8690 }
8691
6d2cd6b2
JB		 8692 if (i.mask && i.mask->zeroing && !i.mask->mask)
8693 {
8694 as_bad (_("zeroing-masking only allowed with write mask"));
8695 return NULL;
8696 }
8697
43234a1e
L		 8698 return op_string;
8699}
8700
252b5132 8701static int
70e41ade 8702i386_immediate (char *imm_start)
252b5132
RH		 8703{
8704 char *save_input_line_pointer;
f3c180ae 8705 char *gotfree_input_line;
252b5132 8706 segT exp_seg = 0;
47926f60 8707 expressionS *exp;
40fb9820
L		 8708 i386_operand_type types;
8709
0dfbf9d7 8710 operand_type_set (&types, ~0);
252b5132
RH		 8711
8712 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8713 {
31b2323c
L		 8714 as_bad (_("at most %d immediate operands are allowed"),
8715 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 8716 return 0;
8717 }
8718
8719 exp = &im_expressions[i.imm_operands++];
520dc8e8 8720 i.op[this_operand].imms = exp;
252b5132
RH		 8721
8722 if (is_space_char (*imm_start))
8723 ++imm_start;
8724
8725 save_input_line_pointer = input_line_pointer;
8726 input_line_pointer = imm_start;
8727
d258b828 8728 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8729 if (gotfree_input_line)
8730 input_line_pointer = gotfree_input_line;
252b5132
RH		 8731
8732 exp_seg = expression (exp);
8733
83183c0c 8734 SKIP_WHITESPACE ();
43234a1e
L		 8735
8736 /* Handle vector operations. */
8737 if (*input_line_pointer == '{')
8738 {
8739 input_line_pointer = check_VecOperations (input_line_pointer,
8740 NULL);
8741 if (input_line_pointer == NULL)
8742 return 0;
8743 }
8744
252b5132 8745 if (*input_line_pointer)
f3c180ae 8746 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 8747
8748 input_line_pointer = save_input_line_pointer;
f3c180ae 8749 if (gotfree_input_line)
ee86248c
JB		 8750 {
8751 free (gotfree_input_line);
8752
8753 if (exp->X_op == O_constant || exp->X_op == O_register)
8754 exp->X_op = O_illegal;
8755 }
8756
8757 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8758}
252b5132 8759
ee86248c
JB		 8760static int
8761i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8762 i386_operand_type types, const char *imm_start)
8763{
8764 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 8765 {
313c53d1
L		 8766 if (imm_start)
8767 as_bad (_("missing or invalid immediate expression `%s'"),
8768 imm_start);
3992d3b7 8769 return 0;
252b5132 8770 }
3e73aa7c 8771 else if (exp->X_op == O_constant)
252b5132 8772 {
47926f60 8773 /* Size it properly later. */
40fb9820 8774 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 8775 /* If not 64bit, sign extend val. */
8776 if (flag_code != CODE_64BIT
4eed87de
AM		 8777 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8778 exp->X_add_number
8779 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 8780 }
4c63da97 8781#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 8782 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 8783 && exp_seg != absolute_section
47926f60 8784 && exp_seg != text_section
24eab124
AM		 8785 && exp_seg != data_section
8786 && exp_seg != bss_section
8787 && exp_seg != undefined_section
f86103b7 8788 && !bfd_is_com_section (exp_seg))
252b5132 8789 {
d0b47220 8790 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 8791 return 0;
8792 }
8793#endif
a841bdf5 8794 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 8795 {
313c53d1
L		 8796 if (imm_start)
8797 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 8798 return 0;
8799 }
252b5132
RH		 8800 else
8801 {
8802 /* This is an address. The size of the address will be
24eab124 8803 determined later, depending on destination register,
3e73aa7c 8804 suffix, or the default for the section. */
40fb9820
L		 8805 i.types[this_operand].bitfield.imm8 = 1;
8806 i.types[this_operand].bitfield.imm16 = 1;
8807 i.types[this_operand].bitfield.imm32 = 1;
8808 i.types[this_operand].bitfield.imm32s = 1;
8809 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8810 i.types[this_operand] = operand_type_and (i.types[this_operand],
8811 types);
252b5132
RH		 8812 }
8813
8814 return 1;
8815}
8816
551c1ca1 8817static char *
e3bb37b5 8818i386_scale (char *scale)
252b5132 8819{
551c1ca1
AM		 8820 offsetT val;
8821 char *save = input_line_pointer;
252b5132 8822
551c1ca1
AM		 8823 input_line_pointer = scale;
8824 val = get_absolute_expression ();
8825
8826 switch (val)
252b5132 8827 {
551c1ca1 8828 case 1:
252b5132
RH		 8829 i.log2_scale_factor = 0;
8830 break;
551c1ca1 8831 case 2:
252b5132
RH		 8832 i.log2_scale_factor = 1;
8833 break;
551c1ca1 8834 case 4:
252b5132
RH		 8835 i.log2_scale_factor = 2;
8836 break;
551c1ca1 8837 case 8:
252b5132
RH		 8838 i.log2_scale_factor = 3;
8839 break;
8840 default:
a724f0f4
JB		 8841 {
8842 char sep = *input_line_pointer;
8843
8844 *input_line_pointer = '\0';
8845 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8846 scale);
8847 *input_line_pointer = sep;
8848 input_line_pointer = save;
8849 return NULL;
8850 }
252b5132 8851 }
29b0f896 8852 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8853 {
8854 as_warn (_("scale factor of %d without an index register"),
24eab124 8855 1 << i.log2_scale_factor);
252b5132 8856 i.log2_scale_factor = 0;
252b5132 8857 }
551c1ca1
AM		 8858 scale = input_line_pointer;
8859 input_line_pointer = save;
8860 return scale;
252b5132
RH		 8861}
8862
252b5132 8863static int
e3bb37b5 8864i386_displacement (char *disp_start, char *disp_end)
252b5132 8865{
29b0f896 8866 expressionS *exp;
252b5132
RH		 8867 segT exp_seg = 0;
8868 char *save_input_line_pointer;
f3c180ae 8869 char *gotfree_input_line;
40fb9820
L		 8870 int override;
8871 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8872 int ret;
252b5132 8873
31b2323c
L		 8874 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8875 {
8876 as_bad (_("at most %d displacement operands are allowed"),
8877 MAX_MEMORY_OPERANDS);
8878 return 0;
8879 }
8880
0dfbf9d7 8881 operand_type_set (&bigdisp, 0);
40fb9820
L		 8882 if ((i.types[this_operand].bitfield.jumpabsolute)
8883 || (!current_templates->start->opcode_modifier.jump
8884 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8885 {
40fb9820 8886 bigdisp.bitfield.disp32 = 1;
e05278af 8887 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8888 if (flag_code == CODE_64BIT)
8889 {
8890 if (!override)
8891 {
8892 bigdisp.bitfield.disp32s = 1;
8893 bigdisp.bitfield.disp64 = 1;
8894 }
8895 }
8896 else if ((flag_code == CODE_16BIT) ^ override)
8897 {
8898 bigdisp.bitfield.disp32 = 0;
8899 bigdisp.bitfield.disp16 = 1;
8900 }
e05278af
JB		 8901 }
8902 else
8903 {
8904 /* For PC-relative branches, the width of the displacement
8905 is dependent upon data size, not address size. */
e05278af 8906 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8907 if (flag_code == CODE_64BIT)
8908 {
8909 if (override || i.suffix == WORD_MNEM_SUFFIX)
8910 bigdisp.bitfield.disp16 = 1;
8911 else
8912 {
8913 bigdisp.bitfield.disp32 = 1;
8914 bigdisp.bitfield.disp32s = 1;
8915 }
8916 }
8917 else
e05278af
JB		 8918 {
8919 if (!override)
8920 override = (i.suffix == (flag_code != CODE_16BIT
8921 ? WORD_MNEM_SUFFIX
8922 : LONG_MNEM_SUFFIX));
40fb9820
L		 8923 bigdisp.bitfield.disp32 = 1;
8924 if ((flag_code == CODE_16BIT) ^ override)
8925 {
8926 bigdisp.bitfield.disp32 = 0;
8927 bigdisp.bitfield.disp16 = 1;
8928 }
e05278af 8929 }
e05278af 8930 }
c6fb90c8
L		 8931 i.types[this_operand] = operand_type_or (i.types[this_operand],
8932 bigdisp);
252b5132
RH		 8933
8934 exp = &disp_expressions[i.disp_operands];
520dc8e8 8935 i.op[this_operand].disps = exp;
252b5132
RH		 8936 i.disp_operands++;
8937 save_input_line_pointer = input_line_pointer;
8938 input_line_pointer = disp_start;
8939 END_STRING_AND_SAVE (disp_end);
8940
8941#ifndef GCC_ASM_O_HACK
8942#define GCC_ASM_O_HACK 0
8943#endif
8944#if GCC_ASM_O_HACK
8945 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8946 if (i.types[this_operand].bitfield.baseIndex
24eab124 8947 && displacement_string_end[-1] == '+')
252b5132
RH		 8948 {
8949 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8950 constraint within gcc asm statements.
8951 For instance:
8952
8953 #define _set_tssldt_desc(n,addr,limit,type) \
8954 __asm__ __volatile__ ( \
8955 "movw %w2,%0\n\t" \
8956 "movw %w1,2+%0\n\t" \
8957 "rorl $16,%1\n\t" \
8958 "movb %b1,4+%0\n\t" \
8959 "movb %4,5+%0\n\t" \
8960 "movb $0,6+%0\n\t" \
8961 "movb %h1,7+%0\n\t" \
8962 "rorl $16,%1" \
8963 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8964
8965 This works great except that the output assembler ends
8966 up looking a bit weird if it turns out that there is
8967 no offset. You end up producing code that looks like:
8968
8969 #APP
8970 movw $235,(%eax)
8971 movw %dx,2+(%eax)
8972 rorl $16,%edx
8973 movb %dl,4+(%eax)
8974 movb $137,5+(%eax)
8975 movb $0,6+(%eax)
8976 movb %dh,7+(%eax)
8977 rorl $16,%edx
8978 #NO_APP
8979
47926f60 8980 So here we provide the missing zero. */
24eab124
AM		 8981
8982 *displacement_string_end = '0';
252b5132
RH		 8983 }
8984#endif
d258b828 8985 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8986 if (gotfree_input_line)
8987 input_line_pointer = gotfree_input_line;
252b5132 8988
24eab124 8989 exp_seg = expression (exp);
252b5132 8990
636c26b0
AM		 8991 SKIP_WHITESPACE ();
8992 if (*input_line_pointer)
8993 as_bad (_("junk `%s' after expression"), input_line_pointer);
8994#if GCC_ASM_O_HACK
8995 RESTORE_END_STRING (disp_end + 1);
8996#endif
636c26b0 8997 input_line_pointer = save_input_line_pointer;
636c26b0 8998 if (gotfree_input_line)
ee86248c
JB		 8999 {
9000 free (gotfree_input_line);
9001
9002 if (exp->X_op == O_constant || exp->X_op == O_register)
9003 exp->X_op = O_illegal;
9004 }
9005
9006 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
9007
9008 RESTORE_END_STRING (disp_end);
9009
9010 return ret;
9011}
9012
9013static int
9014i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
9015 i386_operand_type types, const char *disp_start)
9016{
9017 i386_operand_type bigdisp;
9018 int ret = 1;
636c26b0 9019
24eab124
AM		 9020 /* We do this to make sure that the section symbol is in
9021 the symbol table. We will ultimately change the relocation
47926f60 9022 to be relative to the beginning of the section. */
1ae12ab7 9023 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 9024 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
9025 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 9026 {
636c26b0 9027 if (exp->X_op != O_symbol)
3992d3b7 9028 goto inv_disp;
636c26b0 9029
e5cb08ac 9030 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 9031 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
9032 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 9033 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 9034 exp->X_op = O_subtract;
9035 exp->X_op_symbol = GOT_symbol;
1ae12ab7 9036 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 9037 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 9038 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
9039 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 9040 else
29b0f896 9041 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 9042 }
252b5132 9043
3992d3b7
AM		 9044 else if (exp->X_op == O_absent
9045 || exp->X_op == O_illegal
ee86248c 9046 || exp->X_op == O_big)
2daf4fd8 9047 {
3992d3b7
AM		 9048 inv_disp:
9049 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 9050 disp_start);
3992d3b7 9051 ret = 0;
2daf4fd8
AM		 9052 }
9053
0e1147d9
L		 9054 else if (flag_code == CODE_64BIT
9055 && !i.prefix[ADDR_PREFIX]
9056 && exp->X_op == O_constant)
9057 {
9058 /* Since displacement is signed extended to 64bit, don't allow
9059 disp32 and turn off disp32s if they are out of range. */
9060 i.types[this_operand].bitfield.disp32 = 0;
9061 if (!fits_in_signed_long (exp->X_add_number))
9062 {
9063 i.types[this_operand].bitfield.disp32s = 0;
9064 if (i.types[this_operand].bitfield.baseindex)
9065 {
9066 as_bad (_("0x%lx out range of signed 32bit displacement"),
9067 (long) exp->X_add_number);
9068 ret = 0;
9069 }
9070 }
9071 }
9072
4c63da97 9073#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 9074 else if (exp->X_op != O_constant
9075 && OUTPUT_FLAVOR == bfd_target_aout_flavour
9076 && exp_seg != absolute_section
9077 && exp_seg != text_section
9078 && exp_seg != data_section
9079 && exp_seg != bss_section
9080 && exp_seg != undefined_section
9081 && !bfd_is_com_section (exp_seg))
24eab124 9082 {
d0b47220 9083 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 9084 ret = 0;
24eab124 9085 }
252b5132 9086#endif
3956db08 9087
40fb9820
L		 9088 /* Check if this is a displacement only operand. */
9089 bigdisp = i.types[this_operand];
9090 bigdisp.bitfield.disp8 = 0;
9091 bigdisp.bitfield.disp16 = 0;
9092 bigdisp.bitfield.disp32 = 0;
9093 bigdisp.bitfield.disp32s = 0;
9094 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 9095 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 9096 i.types[this_operand] = operand_type_and (i.types[this_operand],
9097 types);
3956db08 9098
3992d3b7 9099 return ret;
252b5132
RH		 9100}
9101
2abc2bec
JB		 9102/* Return the active addressing mode, taking address override and
9103 registers forming the address into consideration. Update the
9104 address override prefix if necessary. */
47926f60 9105
2abc2bec
JB		 9106static enum flag_code
9107i386_addressing_mode (void)
252b5132 9108{
be05d201
L		 9109 enum flag_code addr_mode;
9110
9111 if (i.prefix[ADDR_PREFIX])
9112 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
9113 else
9114 {
9115 addr_mode = flag_code;
9116
24eab124 9117#if INFER_ADDR_PREFIX
be05d201
L		 9118 if (i.mem_operands == 0)
9119 {
9120 /* Infer address prefix from the first memory operand. */
9121 const reg_entry *addr_reg = i.base_reg;
9122
9123 if (addr_reg == NULL)
9124 addr_reg = i.index_reg;
eecb386c 9125
be05d201
L		 9126 if (addr_reg)
9127 {
9128 if (addr_reg->reg_num == RegEip
9129 || addr_reg->reg_num == RegEiz
dc821c5f 9130 || addr_reg->reg_type.bitfield.dword)
be05d201
L		 9131 addr_mode = CODE_32BIT;
9132 else if (flag_code != CODE_64BIT
dc821c5f 9133 && addr_reg->reg_type.bitfield.word)
be05d201
L		 9134 addr_mode = CODE_16BIT;
9135
9136 if (addr_mode != flag_code)
9137 {
9138 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
9139 i.prefixes += 1;
9140 /* Change the size of any displacement too. At most one
9141 of Disp16 or Disp32 is set.
9142 FIXME. There doesn't seem to be any real need for
9143 separate Disp16 and Disp32 flags. The same goes for
9144 Imm16 and Imm32. Removing them would probably clean
9145 up the code quite a lot. */
9146 if (flag_code != CODE_64BIT
9147 && (i.types[this_operand].bitfield.disp16
9148 || i.types[this_operand].bitfield.disp32))
9149 i.types[this_operand]
9150 = operand_type_xor (i.types[this_operand], disp16_32);
9151 }
9152 }
9153 }
24eab124 9154#endif
be05d201
L		 9155 }
9156
2abc2bec
JB		 9157 return addr_mode;
9158}
9159
9160/* Make sure the memory operand we've been dealt is valid.
9161 Return 1 on success, 0 on a failure. */
9162
9163static int
9164i386_index_check (const char *operand_string)
9165{
9166 const char *kind = "base/index";
9167 enum flag_code addr_mode = i386_addressing_mode ();
9168
fc0763e6
JB		 9169 if (current_templates->start->opcode_modifier.isstring
9170 && !current_templates->start->opcode_modifier.immext
9171 && (current_templates->end[-1].opcode_modifier.isstring
9172 || i.mem_operands))
9173 {
9174 /* Memory operands of string insns are special in that they only allow
9175 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 9176 const reg_entry *expected_reg;
9177 static const char *di_si[][2] =
9178 {
9179 { "esi", "edi" },
9180 { "si", "di" },
9181 { "rsi", "rdi" }
9182 };
9183 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 9184
9185 kind = "string address";
9186
8325cc63 9187 if (current_templates->start->opcode_modifier.repprefixok)
fc0763e6
JB		 9188 {
9189 i386_operand_type type = current_templates->end[-1].operand_types[0];
9190
9191 if (!type.bitfield.baseindex
9192 || ((!i.mem_operands != !intel_syntax)
9193 && current_templates->end[-1].operand_types[1]
9194 .bitfield.baseindex))
9195 type = current_templates->end[-1].operand_types[1];
be05d201
L		 9196 expected_reg = hash_find (reg_hash,
9197 di_si[addr_mode][type.bitfield.esseg]);
9198
fc0763e6
JB		 9199 }
9200 else
be05d201 9201 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 9202
be05d201
L		 9203 if (i.base_reg != expected_reg
9204 || i.index_reg
fc0763e6 9205 || operand_type_check (i.types[this_operand], disp))
fc0763e6 9206 {
be05d201
L		 9207 /* The second memory operand must have the same size as
9208 the first one. */
9209 if (i.mem_operands
9210 && i.base_reg
9211 && !((addr_mode == CODE_64BIT
dc821c5f 9212 && i.base_reg->reg_type.bitfield.qword)
be05d201 9213 || (addr_mode == CODE_32BIT
dc821c5f
JB		 9214 ? i.base_reg->reg_type.bitfield.dword
9215 : i.base_reg->reg_type.bitfield.word)))
be05d201
L		 9216 goto bad_address;
9217
fc0763e6
JB		 9218 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
9219 operand_string,
9220 intel_syntax ? '[' : '(',
9221 register_prefix,
be05d201 9222 expected_reg->reg_name,
fc0763e6 9223 intel_syntax ? ']' : ')');
be05d201 9224 return 1;
fc0763e6 9225 }
be05d201
L		 9226 else
9227 return 1;
9228
9229bad_address:
9230 as_bad (_("`%s' is not a valid %s expression"),
9231 operand_string, kind);
9232 return 0;
3e73aa7c
JH		 9233 }
9234 else
9235 {
be05d201
L		 9236 if (addr_mode != CODE_16BIT)
9237 {
9238 /* 32-bit/64-bit checks. */
9239 if ((i.base_reg
9240 && (addr_mode == CODE_64BIT
dc821c5f
JB		 9241 ? !i.base_reg->reg_type.bitfield.qword
9242 : !i.base_reg->reg_type.bitfield.dword)
be05d201
L		 9243 && (i.index_reg
9244 || (i.base_reg->reg_num
9245 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
9246 || (i.index_reg
1b54b8d7
JB		 9247 && !i.index_reg->reg_type.bitfield.xmmword
9248 && !i.index_reg->reg_type.bitfield.ymmword
9249 && !i.index_reg->reg_type.bitfield.zmmword
be05d201 9250 && ((addr_mode == CODE_64BIT
dc821c5f 9251 ? !(i.index_reg->reg_type.bitfield.qword
be05d201 9252 || i.index_reg->reg_num == RegRiz)
dc821c5f 9253 : !(i.index_reg->reg_type.bitfield.dword
be05d201
L		 9254 || i.index_reg->reg_num == RegEiz))
9255 || !i.index_reg->reg_type.bitfield.baseindex)))
9256 goto bad_address;
8178be5b
JB		 9257
9258 /* bndmk, bndldx, and bndstx have special restrictions. */
9259 if (current_templates->start->base_opcode == 0xf30f1b
9260 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
9261 {
9262 /* They cannot use RIP-relative addressing. */
9263 if (i.base_reg && i.base_reg->reg_num == RegRip)
9264 {
9265 as_bad (_("`%s' cannot be used here"), operand_string);
9266 return 0;
9267 }
9268
9269 /* bndldx and bndstx ignore their scale factor. */
9270 if (current_templates->start->base_opcode != 0xf30f1b
9271 && i.log2_scale_factor)
9272 as_warn (_("register scaling is being ignored here"));
9273 }
be05d201
L		 9274 }
9275 else
3e73aa7c 9276 {
be05d201 9277 /* 16-bit checks. */
3e73aa7c 9278 if ((i.base_reg
dc821c5f 9279 && (!i.base_reg->reg_type.bitfield.word
40fb9820 9280 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 9281 || (i.index_reg
dc821c5f 9282 && (!i.index_reg->reg_type.bitfield.word
40fb9820 9283 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 9284 || !(i.base_reg
9285 && i.base_reg->reg_num < 6
9286 && i.index_reg->reg_num >= 6
9287 && i.log2_scale_factor == 0))))
be05d201 9288 goto bad_address;
3e73aa7c
JH		 9289 }
9290 }
be05d201 9291 return 1;
24eab124 9292}
252b5132 9293
43234a1e
L		 9294/* Handle vector immediates. */
9295
9296static int
9297RC_SAE_immediate (const char *imm_start)
9298{
9299 unsigned int match_found, j;
9300 const char *pstr = imm_start;
9301 expressionS *exp;
9302
9303 if (*pstr != '{')
9304 return 0;
9305
9306 pstr++;
9307 match_found = 0;
9308 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
9309 {
9310 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
9311 {
9312 if (!i.rounding)
9313 {
9314 rc_op.type = RC_NamesTable[j].type;
9315 rc_op.operand = this_operand;
9316 i.rounding = &rc_op;
9317 }
9318 else
9319 {
9320 as_bad (_("duplicated `%s'"), imm_start);
9321 return 0;
9322 }
9323 pstr += RC_NamesTable[j].len;
9324 match_found = 1;
9325 break;
9326 }
9327 }
9328 if (!match_found)
9329 return 0;
9330
9331 if (*pstr++ != '}')
9332 {
9333 as_bad (_("Missing '}': '%s'"), imm_start);
9334 return 0;
9335 }
9336 /* RC/SAE immediate string should contain nothing more. */;
9337 if (*pstr != 0)
9338 {
9339 as_bad (_("Junk after '}': '%s'"), imm_start);
9340 return 0;
9341 }
9342
9343 exp = &im_expressions[i.imm_operands++];
9344 i.op[this_operand].imms = exp;
9345
9346 exp->X_op = O_constant;
9347 exp->X_add_number = 0;
9348 exp->X_add_symbol = (symbolS *) 0;
9349 exp->X_op_symbol = (symbolS *) 0;
9350
9351 i.types[this_operand].bitfield.imm8 = 1;
9352 return 1;
9353}
9354
8325cc63
JB		 9355/* Only string instructions can have a second memory operand, so
9356 reduce current_templates to just those if it contains any. */
9357static int
9358maybe_adjust_templates (void)
9359{
9360 const insn_template *t;
9361
9362 gas_assert (i.mem_operands == 1);
9363
9364 for (t = current_templates->start; t < current_templates->end; ++t)
9365 if (t->opcode_modifier.isstring)
9366 break;
9367
9368 if (t < current_templates->end)
9369 {
9370 static templates aux_templates;
9371 bfd_boolean recheck;
9372
9373 aux_templates.start = t;
9374 for (; t < current_templates->end; ++t)
9375 if (!t->opcode_modifier.isstring)
9376 break;
9377 aux_templates.end = t;
9378
9379 /* Determine whether to re-check the first memory operand. */
9380 recheck = (aux_templates.start != current_templates->start
9381 || t != current_templates->end);
9382
9383 current_templates = &aux_templates;
9384
9385 if (recheck)
9386 {
9387 i.mem_operands = 0;
9388 if (i.memop1_string != NULL
9389 && i386_index_check (i.memop1_string) == 0)
9390 return 0;
9391 i.mem_operands = 1;
9392 }
9393 }
9394
9395 return 1;
9396}
9397
fc0763e6 9398/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 9399 on error. */
252b5132 9400
252b5132 9401static int
a7619375 9402i386_att_operand (char *operand_string)
252b5132 9403{
af6bdddf
AM		 9404 const reg_entry *r;
9405 char *end_op;
24eab124 9406 char *op_string = operand_string;
252b5132 9407
24eab124 9408 if (is_space_char (*op_string))
252b5132
RH		 9409 ++op_string;
9410
24eab124 9411 /* We check for an absolute prefix (differentiating,
47926f60 9412 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 9413 if (*op_string == ABSOLUTE_PREFIX)
9414 {
9415 ++op_string;
9416 if (is_space_char (*op_string))
9417 ++op_string;
40fb9820 9418 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 9419 }
252b5132 9420
47926f60 9421 /* Check if operand is a register. */
4d1bb795 9422 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 9423 {
40fb9820
L		 9424 i386_operand_type temp;
9425
24eab124
AM		 9426 /* Check for a segment override by searching for ':' after a
9427 segment register. */
9428 op_string = end_op;
9429 if (is_space_char (*op_string))
9430 ++op_string;
40fb9820
L		 9431 if (*op_string == ':'
9432 && (r->reg_type.bitfield.sreg2
9433 || r->reg_type.bitfield.sreg3))
24eab124
AM		 9434 {
9435 switch (r->reg_num)
9436 {
9437 case 0:
9438 i.seg[i.mem_operands] = &es;
9439 break;
9440 case 1:
9441 i.seg[i.mem_operands] = &cs;
9442 break;
9443 case 2:
9444 i.seg[i.mem_operands] = &ss;
9445 break;
9446 case 3:
9447 i.seg[i.mem_operands] = &ds;
9448 break;
9449 case 4:
9450 i.seg[i.mem_operands] = &fs;
9451 break;
9452 case 5:
9453 i.seg[i.mem_operands] = &gs;
9454 break;
9455 }
252b5132 9456
24eab124 9457 /* Skip the ':' and whitespace. */
252b5132
RH		 9458 ++op_string;
9459 if (is_space_char (*op_string))
24eab124 9460 ++op_string;
252b5132 9461
24eab124
AM		 9462 if (!is_digit_char (*op_string)
9463 && !is_identifier_char (*op_string)
9464 && *op_string != '('
9465 && *op_string != ABSOLUTE_PREFIX)
9466 {
9467 as_bad (_("bad memory operand `%s'"), op_string);
9468 return 0;
9469 }
47926f60 9470 /* Handle case of %es:*foo. */
24eab124
AM		 9471 if (*op_string == ABSOLUTE_PREFIX)
9472 {
9473 ++op_string;
9474 if (is_space_char (*op_string))
9475 ++op_string;
40fb9820 9476 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 9477 }
9478 goto do_memory_reference;
9479 }
43234a1e
L		 9480
9481 /* Handle vector operations. */
9482 if (*op_string == '{')
9483 {
9484 op_string = check_VecOperations (op_string, NULL);
9485 if (op_string == NULL)
9486 return 0;
9487 }
9488
24eab124
AM		 9489 if (*op_string)
9490 {
d0b47220 9491 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 9492 return 0;
9493 }
40fb9820
L		 9494 temp = r->reg_type;
9495 temp.bitfield.baseindex = 0;
c6fb90c8
L		 9496 i.types[this_operand] = operand_type_or (i.types[this_operand],
9497 temp);
7d5e4556 9498 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 9499 i.op[this_operand].regs = r;
24eab124
AM		 9500 i.reg_operands++;
9501 }
af6bdddf
AM		 9502 else if (*op_string == REGISTER_PREFIX)
9503 {
9504 as_bad (_("bad register name `%s'"), op_string);
9505 return 0;
9506 }
24eab124 9507 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 9508 {
24eab124 9509 ++op_string;
40fb9820 9510 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 9511 {
d0b47220 9512 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 9513 return 0;
9514 }
9515 if (!i386_immediate (op_string))
9516 return 0;
9517 }
43234a1e
L		 9518 else if (RC_SAE_immediate (operand_string))
9519 {
9520 /* If it is a RC or SAE immediate, do nothing. */
9521 ;
9522 }
24eab124
AM		 9523 else if (is_digit_char (*op_string)
9524 || is_identifier_char (*op_string)
d02603dc 9525 || *op_string == '"'
e5cb08ac 9526 || *op_string == '(')
24eab124 9527 {
47926f60 9528 /* This is a memory reference of some sort. */
af6bdddf 9529 char *base_string;
252b5132 9530
47926f60 9531 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 9532 char *displacement_string_start;
9533 char *displacement_string_end;
43234a1e 9534 char *vop_start;
252b5132 9535
24eab124 9536 do_memory_reference:
8325cc63
JB		 9537 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9538 return 0;
24eab124 9539 if ((i.mem_operands == 1
40fb9820 9540 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 9541 || i.mem_operands == 2)
9542 {
9543 as_bad (_("too many memory references for `%s'"),
9544 current_templates->start->name);
9545 return 0;
9546 }
252b5132 9547
24eab124
AM		 9548 /* Check for base index form. We detect the base index form by
9549 looking for an ')' at the end of the operand, searching
9550 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9551 after the '('. */
af6bdddf 9552 base_string = op_string + strlen (op_string);
c3332e24 9553
43234a1e
L		 9554 /* Handle vector operations. */
9555 vop_start = strchr (op_string, '{');
9556 if (vop_start && vop_start < base_string)
9557 {
9558 if (check_VecOperations (vop_start, base_string) == NULL)
9559 return 0;
9560 base_string = vop_start;
9561 }
9562
af6bdddf
AM		 9563 --base_string;
9564 if (is_space_char (*base_string))
9565 --base_string;
252b5132 9566
47926f60 9567 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 9568 displacement_string_start = op_string;
9569 displacement_string_end = base_string + 1;
252b5132 9570
24eab124
AM		 9571 if (*base_string == ')')
9572 {
af6bdddf 9573 char *temp_string;
24eab124
AM		 9574 unsigned int parens_balanced = 1;
9575 /* We've already checked that the number of left & right ()'s are
47926f60 9576 equal, so this loop will not be infinite. */
24eab124
AM		 9577 do
9578 {
9579 base_string--;
9580 if (*base_string == ')')
9581 parens_balanced++;
9582 if (*base_string == '(')
9583 parens_balanced--;
9584 }
9585 while (parens_balanced);
c3332e24 9586
af6bdddf 9587 temp_string = base_string;
c3332e24 9588
24eab124 9589 /* Skip past '(' and whitespace. */
252b5132
RH		 9590 ++base_string;
9591 if (is_space_char (*base_string))
24eab124 9592 ++base_string;
252b5132 9593
af6bdddf 9594 if (*base_string == ','
4eed87de
AM		 9595 || ((i.base_reg = parse_register (base_string, &end_op))
9596 != NULL))
252b5132 9597 {
af6bdddf 9598 displacement_string_end = temp_string;
252b5132 9599
40fb9820 9600 i.types[this_operand].bitfield.baseindex = 1;
252b5132 9601
af6bdddf 9602 if (i.base_reg)
24eab124 9603 {
24eab124
AM		 9604 base_string = end_op;
9605 if (is_space_char (*base_string))
9606 ++base_string;
af6bdddf
AM		 9607 }
9608
9609 /* There may be an index reg or scale factor here. */
9610 if (*base_string == ',')
9611 {
9612 ++base_string;
9613 if (is_space_char (*base_string))
9614 ++base_string;
9615
4eed87de
AM		 9616 if ((i.index_reg = parse_register (base_string, &end_op))
9617 != NULL)
24eab124 9618 {
af6bdddf 9619 base_string = end_op;
24eab124
AM		 9620 if (is_space_char (*base_string))
9621 ++base_string;
af6bdddf
AM		 9622 if (*base_string == ',')
9623 {
9624 ++base_string;
9625 if (is_space_char (*base_string))
9626 ++base_string;
9627 }
e5cb08ac 9628 else if (*base_string != ')')
af6bdddf 9629 {
4eed87de
AM		 9630 as_bad (_("expecting `,' or `)' "
9631 "after index register in `%s'"),
af6bdddf
AM		 9632 operand_string);
9633 return 0;
9634 }
24eab124 9635 }
af6bdddf 9636 else if (*base_string == REGISTER_PREFIX)
24eab124 9637 {
f76bf5e0
L		 9638 end_op = strchr (base_string, ',');
9639 if (end_op)
9640 *end_op = '\0';
af6bdddf 9641 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 9642 return 0;
9643 }
252b5132 9644
47926f60 9645 /* Check for scale factor. */
551c1ca1 9646 if (*base_string != ')')
af6bdddf 9647 {
551c1ca1
AM		 9648 char *end_scale = i386_scale (base_string);
9649
9650 if (!end_scale)
af6bdddf 9651 return 0;
24eab124 9652
551c1ca1 9653 base_string = end_scale;
af6bdddf
AM		 9654 if (is_space_char (*base_string))
9655 ++base_string;
9656 if (*base_string != ')')
9657 {
4eed87de
AM		 9658 as_bad (_("expecting `)' "
9659 "after scale factor in `%s'"),
af6bdddf
AM		 9660 operand_string);
9661 return 0;
9662 }
9663 }
9664 else if (!i.index_reg)
24eab124 9665 {
4eed87de
AM		 9666 as_bad (_("expecting index register or scale factor "
9667 "after `,'; got '%c'"),
af6bdddf 9668 *base_string);
24eab124
AM		 9669 return 0;
9670 }
9671 }
af6bdddf 9672 else if (*base_string != ')')
24eab124 9673 {
4eed87de
AM		 9674 as_bad (_("expecting `,' or `)' "
9675 "after base register in `%s'"),
af6bdddf 9676 operand_string);
24eab124
AM		 9677 return 0;
9678 }
c3332e24 9679 }
af6bdddf 9680 else if (*base_string == REGISTER_PREFIX)
c3332e24 9681 {
f76bf5e0
L		 9682 end_op = strchr (base_string, ',');
9683 if (end_op)
9684 *end_op = '\0';
af6bdddf 9685 as_bad (_("bad register name `%s'"), base_string);
24eab124 9686 return 0;
c3332e24 9687 }
24eab124
AM		 9688 }
9689
9690 /* If there's an expression beginning the operand, parse it,
9691 assuming displacement_string_start and
9692 displacement_string_end are meaningful. */
9693 if (displacement_string_start != displacement_string_end)
9694 {
9695 if (!i386_displacement (displacement_string_start,
9696 displacement_string_end))
9697 return 0;
9698 }
9699
9700 /* Special case for (%dx) while doing input/output op. */
9701 if (i.base_reg
2fb5be8d 9702 && i.base_reg->reg_type.bitfield.inoutportreg
24eab124
AM		 9703 && i.index_reg == 0
9704 && i.log2_scale_factor == 0
9705 && i.seg[i.mem_operands] == 0
40fb9820 9706 && !operand_type_check (i.types[this_operand], disp))
24eab124 9707 {
2fb5be8d 9708 i.types[this_operand] = i.base_reg->reg_type;
24eab124
AM		 9709 return 1;
9710 }
9711
eecb386c
AM		 9712 if (i386_index_check (operand_string) == 0)
9713 return 0;
5c07affc 9714 i.types[this_operand].bitfield.mem = 1;
8325cc63
JB		 9715 if (i.mem_operands == 0)
9716 i.memop1_string = xstrdup (operand_string);
24eab124
AM		 9717 i.mem_operands++;
9718 }
9719 else
ce8a8b2f
AM		 9720 {
9721 /* It's not a memory operand; argh! */
24eab124
AM		 9722 as_bad (_("invalid char %s beginning operand %d `%s'"),
9723 output_invalid (*op_string),
9724 this_operand + 1,
9725 op_string);
9726 return 0;
9727 }
47926f60 9728 return 1; /* Normal return. */
252b5132
RH		 9729}
9730\f
fa94de6b
RM		 9731/* Calculate the maximum variable size (i.e., excluding fr_fix)
9732 that an rs_machine_dependent frag may reach. */
9733
9734unsigned int
9735i386_frag_max_var (fragS *frag)
9736{
9737 /* The only relaxable frags are for jumps.
9738 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9739 gas_assert (frag->fr_type == rs_machine_dependent);
9740 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9741}
9742
b084df0b
L		 9743#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9744static int
8dcea932 9745elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
b084df0b
L		 9746{
9747 /* STT_GNU_IFUNC symbol must go through PLT. */
9748 if ((symbol_get_bfdsym (fr_symbol)->flags
9749 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9750 return 0;
9751
9752 if (!S_IS_EXTERNAL (fr_symbol))
9753 /* Symbol may be weak or local. */
9754 return !S_IS_WEAK (fr_symbol);
9755
8dcea932
L		 9756 /* Global symbols with non-default visibility can't be preempted. */
9757 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9758 return 1;
9759
9760 if (fr_var != NO_RELOC)
9761 switch ((enum bfd_reloc_code_real) fr_var)
9762 {
9763 case BFD_RELOC_386_PLT32:
9764 case BFD_RELOC_X86_64_PLT32:
33eaf5de 9765 /* Symbol with PLT relocation may be preempted. */
8dcea932
L		 9766 return 0;
9767 default:
9768 abort ();
9769 }
9770
b084df0b
L		 9771 /* Global symbols with default visibility in a shared library may be
9772 preempted by another definition. */
8dcea932 9773 return !shared;
b084df0b
L		 9774}
9775#endif
9776
ee7fcc42
AM		 9777/* md_estimate_size_before_relax()
9778
9779 Called just before relax() for rs_machine_dependent frags. The x86
9780 assembler uses these frags to handle variable size jump
9781 instructions.
9782
9783 Any symbol that is now undefined will not become defined.
9784 Return the correct fr_subtype in the frag.
9785 Return the initial "guess for variable size of frag" to caller.
9786 The guess is actually the growth beyond the fixed part. Whatever
9787 we do to grow the fixed or variable part contributes to our
9788 returned value. */
9789
252b5132 9790int
7016a5d5 9791md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 9792{
252b5132 9793 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 9794 check for un-relaxable symbols. On an ELF system, we can't relax
9795 an externally visible symbol, because it may be overridden by a
9796 shared library. */
9797 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 9798#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9799 || (IS_ELF
8dcea932
L		 9800 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9801 fragP->fr_var))
fbeb56a4
DK		 9802#endif
9803#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 9804 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 9805 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 9806#endif
9807 )
252b5132 9808 {
b98ef147
AM		 9809 /* Symbol is undefined in this segment, or we need to keep a
9810 reloc so that weak symbols can be overridden. */
9811 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 9812 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 9813 unsigned char *opcode;
9814 int old_fr_fix;
f6af82bd 9815
ee7fcc42 9816 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 9817 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 9818 else if (size == 2)
f6af82bd 9819 reloc_type = BFD_RELOC_16_PCREL;
bd7ab16b
L		 9820#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9821 else if (need_plt32_p (fragP->fr_symbol))
9822 reloc_type = BFD_RELOC_X86_64_PLT32;
9823#endif
f6af82bd
AM		 9824 else
9825 reloc_type = BFD_RELOC_32_PCREL;
252b5132 9826
ee7fcc42
AM		 9827 old_fr_fix = fragP->fr_fix;
9828 opcode = (unsigned char *) fragP->fr_opcode;
9829
fddf5b5b 9830 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 9831 {
fddf5b5b
AM		 9832 case UNCOND_JUMP:
9833 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 9834 opcode[0] = 0xe9;
252b5132 9835 fragP->fr_fix += size;
062cd5e7
AS		 9836 fix_new (fragP, old_fr_fix, size,
9837 fragP->fr_symbol,
9838 fragP->fr_offset, 1,
9839 reloc_type);
252b5132
RH		 9840 break;
9841
fddf5b5b 9842 case COND_JUMP86:
412167cb
AM		 9843 if (size == 2
9844 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 9845 {
9846 /* Negate the condition, and branch past an
9847 unconditional jump. */
9848 opcode[0] ^= 1;
9849 opcode[1] = 3;
9850 /* Insert an unconditional jump. */
9851 opcode[2] = 0xe9;
9852 /* We added two extra opcode bytes, and have a two byte
9853 offset. */
9854 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 9855 fix_new (fragP, old_fr_fix + 2, 2,
9856 fragP->fr_symbol,
9857 fragP->fr_offset, 1,
9858 reloc_type);
fddf5b5b
AM		 9859 break;
9860 }
9861 /* Fall through. */
9862
9863 case COND_JUMP:
412167cb
AM		 9864 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9865 {
3e02c1cc
AM		 9866 fixS *fixP;
9867
412167cb 9868 fragP->fr_fix += 1;
3e02c1cc
AM		 9869 fixP = fix_new (fragP, old_fr_fix, 1,
9870 fragP->fr_symbol,
9871 fragP->fr_offset, 1,
9872 BFD_RELOC_8_PCREL);
9873 fixP->fx_signed = 1;
412167cb
AM		 9874 break;
9875 }
93c2a809 9876
24eab124 9877 /* This changes the byte-displacement jump 0x7N
fddf5b5b 9878 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 9879 opcode[1] = opcode[0] + 0x10;
f6af82bd 9880 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 9881 /* We've added an opcode byte. */
9882 fragP->fr_fix += 1 + size;
062cd5e7
AS		 9883 fix_new (fragP, old_fr_fix + 1, size,
9884 fragP->fr_symbol,
9885 fragP->fr_offset, 1,
9886 reloc_type);
252b5132 9887 break;
fddf5b5b
AM		 9888
9889 default:
9890 BAD_CASE (fragP->fr_subtype);
9891 break;
252b5132
RH		 9892 }
9893 frag_wane (fragP);
ee7fcc42 9894 return fragP->fr_fix - old_fr_fix;
252b5132 9895 }
93c2a809 9896
93c2a809
AM		 9897 /* Guess size depending on current relax state. Initially the relax
9898 state will correspond to a short jump and we return 1, because
9899 the variable part of the frag (the branch offset) is one byte
9900 long. However, we can relax a section more than once and in that
9901 case we must either set fr_subtype back to the unrelaxed state,
9902 or return the value for the appropriate branch. */
9903 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 9904}
9905
47926f60
KH		 9906/* Called after relax() is finished.
9907
9908 In: Address of frag.
9909 fr_type == rs_machine_dependent.
9910 fr_subtype is what the address relaxed to.
9911
9912 Out: Any fixSs and constants are set up.
9913 Caller will turn frag into a ".space 0". */
9914
252b5132 9915void
7016a5d5
TG		 9916md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9917 fragS *fragP)
252b5132 9918{
29b0f896 9919 unsigned char *opcode;
252b5132 9920 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9921 offsetT target_address;
9922 offsetT opcode_address;
252b5132 9923 unsigned int extension = 0;
847f7ad4 9924 offsetT displacement_from_opcode_start;
252b5132
RH		 9925
9926 opcode = (unsigned char *) fragP->fr_opcode;
9927
47926f60 9928 /* Address we want to reach in file space. */
252b5132 9929 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9930
47926f60 9931 /* Address opcode resides at in file space. */
252b5132
RH		 9932 opcode_address = fragP->fr_address + fragP->fr_fix;
9933
47926f60 9934 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9935 displacement_from_opcode_start = target_address - opcode_address;
9936
fddf5b5b 9937 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9938 {
47926f60
KH		 9939 /* Don't have to change opcode. */
9940 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9941 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9942 }
9943 else
9944 {
9945 if (no_cond_jump_promotion
9946 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9947 as_warn_where (fragP->fr_file, fragP->fr_line,
9948 _("long jump required"));
252b5132 9949
fddf5b5b
AM		 9950 switch (fragP->fr_subtype)
9951 {
9952 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9953 extension = 4; /* 1 opcode + 4 displacement */
9954 opcode[0] = 0xe9;
9955 where_to_put_displacement = &opcode[1];
9956 break;
252b5132 9957
fddf5b5b
AM		 9958 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9959 extension = 2; /* 1 opcode + 2 displacement */
9960 opcode[0] = 0xe9;
9961 where_to_put_displacement = &opcode[1];
9962 break;
252b5132 9963
fddf5b5b
AM		 9964 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9965 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9966 extension = 5; /* 2 opcode + 4 displacement */
9967 opcode[1] = opcode[0] + 0x10;
9968 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9969 where_to_put_displacement = &opcode[2];
9970 break;
252b5132 9971
fddf5b5b
AM		 9972 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9973 extension = 3; /* 2 opcode + 2 displacement */
9974 opcode[1] = opcode[0] + 0x10;
9975 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9976 where_to_put_displacement = &opcode[2];
9977 break;
252b5132 9978
fddf5b5b
AM		 9979 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9980 extension = 4;
9981 opcode[0] ^= 1;
9982 opcode[1] = 3;
9983 opcode[2] = 0xe9;
9984 where_to_put_displacement = &opcode[3];
9985 break;
9986
9987 default:
9988 BAD_CASE (fragP->fr_subtype);
9989 break;
9990 }
252b5132 9991 }
fddf5b5b 9992
7b81dfbb
AJ		 9993 /* If size if less then four we are sure that the operand fits,
9994 but if it's 4, then it could be that the displacement is larger
9995 then -/+ 2GB. */
9996 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9997 && object_64bit
9998 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9999 + ((addressT) 1 << 31))
10000 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 10001 {
10002 as_bad_where (fragP->fr_file, fragP->fr_line,
10003 _("jump target out of range"));
10004 /* Make us emit 0. */
10005 displacement_from_opcode_start = extension;
10006 }
47926f60 10007 /* Now put displacement after opcode. */
252b5132
RH		 10008 md_number_to_chars ((char *) where_to_put_displacement,
10009 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 10010 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 10011 fragP->fr_fix += extension;
10012}
10013\f
7016a5d5 10014/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 10015 by our caller that we have all the info we need to fix it up.
10016
7016a5d5
TG		 10017 Parameter valP is the pointer to the value of the bits.
10018
252b5132
RH		 10019 On the 386, immediates, displacements, and data pointers are all in
10020 the same (little-endian) format, so we don't need to care about which
10021 we are handling. */
10022
94f592af 10023void
7016a5d5 10024md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 10025{
94f592af 10026 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 10027 valueT value = *valP;
252b5132 10028
f86103b7 10029#if !defined (TE_Mach)
93382f6d
AM		 10030 if (fixP->fx_pcrel)
10031 {
10032 switch (fixP->fx_r_type)
10033 {
5865bb77
ILT		 10034 default:
10035 break;
10036
d6ab8113
JB		 10037 case BFD_RELOC_64:
10038 fixP->fx_r_type = BFD_RELOC_64_PCREL;
10039 break;
93382f6d 10040 case BFD_RELOC_32:
ae8887b5 10041 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 10042 fixP->fx_r_type = BFD_RELOC_32_PCREL;
10043 break;
10044 case BFD_RELOC_16:
10045 fixP->fx_r_type = BFD_RELOC_16_PCREL;
10046 break;
10047 case BFD_RELOC_8:
10048 fixP->fx_r_type = BFD_RELOC_8_PCREL;
10049 break;
10050 }
10051 }
252b5132 10052
a161fe53 10053 if (fixP->fx_addsy != NULL
31312f95 10054 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 10055 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 10056 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 10057 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 10058 && !use_rela_relocations)
252b5132 10059 {
31312f95
AM		 10060 /* This is a hack. There should be a better way to handle this.
10061 This covers for the fact that bfd_install_relocation will
10062 subtract the current location (for partial_inplace, PC relative
10063 relocations); see more below. */
252b5132 10064#ifndef OBJ_AOUT
718ddfc0 10065 if (IS_ELF
252b5132
RH		 10066#ifdef TE_PE
10067 || OUTPUT_FLAVOR == bfd_target_coff_flavour
10068#endif
10069 )
10070 value += fixP->fx_where + fixP->fx_frag->fr_address;
10071#endif
10072#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 10073 if (IS_ELF)
252b5132 10074 {
6539b54b 10075 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 10076
6539b54b 10077 if ((sym_seg == seg
2f66722d 10078 || (symbol_section_p (fixP->fx_addsy)
6539b54b 10079 && sym_seg != absolute_section))
af65af87 10080 && !generic_force_reloc (fixP))
2f66722d
AM		 10081 {
10082 /* Yes, we add the values in twice. This is because
6539b54b
AM		 10083 bfd_install_relocation subtracts them out again. I think
10084 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 10085 it. FIXME. */
10086 value += fixP->fx_where + fixP->fx_frag->fr_address;
10087 }
252b5132
RH		 10088 }
10089#endif
10090#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 10091 /* For some reason, the PE format does not store a
10092 section address offset for a PC relative symbol. */
10093 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 10094 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 10095 value += md_pcrel_from (fixP);
10096#endif
10097 }
fbeb56a4 10098#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 10099 if (fixP->fx_addsy != NULL
10100 && S_IS_WEAK (fixP->fx_addsy)
10101 /* PR 16858: Do not modify weak function references. */
10102 && ! fixP->fx_pcrel)
fbeb56a4 10103 {
296a8689
NC		 10104#if !defined (TE_PEP)
10105 /* For x86 PE weak function symbols are neither PC-relative
10106 nor do they set S_IS_FUNCTION. So the only reliable way
10107 to detect them is to check the flags of their containing
10108 section. */
10109 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
10110 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
10111 ;
10112 else
10113#endif
fbeb56a4
DK		 10114 value -= S_GET_VALUE (fixP->fx_addsy);
10115 }
10116#endif
252b5132
RH		 10117
10118 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 10119 and we must not disappoint it. */
252b5132 10120#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 10121 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 10122 switch (fixP->fx_r_type)
10123 {
10124 case BFD_RELOC_386_PLT32:
3e73aa7c 10125 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 10126 /* Make the jump instruction point to the address of the operand. At
10127 runtime we merely add the offset to the actual PLT entry. */
10128 value = -4;
10129 break;
31312f95 10130
13ae64f3
JJ		 10131 case BFD_RELOC_386_TLS_GD:
10132 case BFD_RELOC_386_TLS_LDM:
13ae64f3 10133 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10134 case BFD_RELOC_386_TLS_IE:
10135 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 10136 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 10137 case BFD_RELOC_X86_64_TLSGD:
10138 case BFD_RELOC_X86_64_TLSLD:
10139 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 10140 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 10141 value = 0; /* Fully resolved at runtime. No addend. */
10142 /* Fallthrough */
10143 case BFD_RELOC_386_TLS_LE:
10144 case BFD_RELOC_386_TLS_LDO_32:
10145 case BFD_RELOC_386_TLS_LE_32:
10146 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10147 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 10148 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 10149 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 10150 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10151 break;
10152
67a4f2b7
AO		 10153 case BFD_RELOC_386_TLS_DESC_CALL:
10154 case BFD_RELOC_X86_64_TLSDESC_CALL:
10155 value = 0; /* Fully resolved at runtime. No addend. */
10156 S_SET_THREAD_LOCAL (fixP->fx_addsy);
10157 fixP->fx_done = 0;
10158 return;
10159
47926f60
KH		 10160 case BFD_RELOC_VTABLE_INHERIT:
10161 case BFD_RELOC_VTABLE_ENTRY:
10162 fixP->fx_done = 0;
94f592af 10163 return;
47926f60
KH		 10164
10165 default:
10166 break;
10167 }
10168#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 10169 *valP = value;
f86103b7 10170#endif /* !defined (TE_Mach) */
3e73aa7c 10171
3e73aa7c 10172 /* Are we finished with this relocation now? */
c6682705 10173 if (fixP->fx_addsy == NULL)
3e73aa7c 10174 fixP->fx_done = 1;
fbeb56a4
DK		 10175#if defined (OBJ_COFF) && defined (TE_PE)
10176 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
10177 {
10178 fixP->fx_done = 0;
10179 /* Remember value for tc_gen_reloc. */
10180 fixP->fx_addnumber = value;
10181 /* Clear out the frag for now. */
10182 value = 0;
10183 }
10184#endif
3e73aa7c
JH		 10185 else if (use_rela_relocations)
10186 {
10187 fixP->fx_no_overflow = 1;
062cd5e7
AS		 10188 /* Remember value for tc_gen_reloc. */
10189 fixP->fx_addnumber = value;
3e73aa7c
JH		 10190 value = 0;
10191 }
f86103b7 10192
94f592af 10193 md_number_to_chars (p, value, fixP->fx_size);
252b5132 10194}
252b5132 10195\f
6d4af3c2 10196const char *
499ac353 10197md_atof (int type, char *litP, int *sizeP)
252b5132 10198{
499ac353
NC		 10199 /* This outputs the LITTLENUMs in REVERSE order;
10200 in accord with the bigendian 386. */
10201 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 10202}
10203\f
2d545b82 10204static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 10205
252b5132 10206static char *
e3bb37b5 10207output_invalid (int c)
252b5132 10208{
3882b010 10209 if (ISPRINT (c))
f9f21a03
L		 10210 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
10211 "'%c'", c);
252b5132 10212 else
f9f21a03 10213 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 10214 "(0x%x)", (unsigned char) c);
252b5132
RH		 10215 return output_invalid_buf;
10216}
10217
af6bdddf 10218/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 10219
10220static const reg_entry *
4d1bb795 10221parse_real_register (char *reg_string, char **end_op)
252b5132 10222{
af6bdddf
AM		 10223 char *s = reg_string;
10224 char *p;
252b5132
RH		 10225 char reg_name_given[MAX_REG_NAME_SIZE + 1];
10226 const reg_entry *r;
10227
10228 /* Skip possible REGISTER_PREFIX and possible whitespace. */
10229 if (*s == REGISTER_PREFIX)
10230 ++s;
10231
10232 if (is_space_char (*s))
10233 ++s;
10234
10235 p = reg_name_given;
af6bdddf 10236 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 10237 {
10238 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 10239 return (const reg_entry *) NULL;
10240 s++;
252b5132
RH		 10241 }
10242
6588847e
DN		 10243 /* For naked regs, make sure that we are not dealing with an identifier.
10244 This prevents confusing an identifier like `eax_var' with register
10245 `eax'. */
10246 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
10247 return (const reg_entry *) NULL;
10248
af6bdddf 10249 *end_op = s;
252b5132
RH		 10250
10251 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
10252
5f47d35b 10253 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 10254 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 10255 {
0e0eea78
JB		 10256 if (!cpu_arch_flags.bitfield.cpu8087
10257 && !cpu_arch_flags.bitfield.cpu287
10258 && !cpu_arch_flags.bitfield.cpu387)
10259 return (const reg_entry *) NULL;
10260
5f47d35b
AM		 10261 if (is_space_char (*s))
10262 ++s;
10263 if (*s == '(')
10264 {
af6bdddf 10265 ++s;
5f47d35b
AM		 10266 if (is_space_char (*s))
10267 ++s;
10268 if (*s >= '0' && *s <= '7')
10269 {
db557034 10270 int fpr = *s - '0';
af6bdddf 10271 ++s;
5f47d35b
AM		 10272 if (is_space_char (*s))
10273 ++s;
10274 if (*s == ')')
10275 {
10276 *end_op = s + 1;
1e9cc1c2 10277 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 10278 know (r);
10279 return r + fpr;
5f47d35b 10280 }
5f47d35b 10281 }
47926f60 10282 /* We have "%st(" then garbage. */
5f47d35b
AM		 10283 return (const reg_entry *) NULL;
10284 }
10285 }
10286
a60de03c
JB		 10287 if (r == NULL || allow_pseudo_reg)
10288 return r;
10289
0dfbf9d7 10290 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 10291 return (const reg_entry *) NULL;
10292
dc821c5f 10293 if ((r->reg_type.bitfield.dword
192dc9c6
JB		 10294 || r->reg_type.bitfield.sreg3
10295 || r->reg_type.bitfield.control
10296 || r->reg_type.bitfield.debug
10297 || r->reg_type.bitfield.test)
10298 && !cpu_arch_flags.bitfield.cpui386)
10299 return (const reg_entry *) NULL;
10300
6e041cf4 10301 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
192dc9c6
JB		 10302 return (const reg_entry *) NULL;
10303
6e041cf4
JB		 10304 if (!cpu_arch_flags.bitfield.cpuavx512f)
10305 {
10306 if (r->reg_type.bitfield.zmmword || r->reg_type.bitfield.regmask)
10307 return (const reg_entry *) NULL;
40f12533 10308
6e041cf4
JB		 10309 if (!cpu_arch_flags.bitfield.cpuavx)
10310 {
10311 if (r->reg_type.bitfield.ymmword)
10312 return (const reg_entry *) NULL;
1848e567 10313
6e041cf4
JB		 10314 if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword)
10315 return (const reg_entry *) NULL;
10316 }
10317 }
43234a1e 10318
1adf7f56
JB		 10319 if (r->reg_type.bitfield.regbnd && !cpu_arch_flags.bitfield.cpumpx)
10320 return (const reg_entry *) NULL;
10321
db51cc60 10322 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 10323 if (!allow_index_reg
db51cc60
L		 10324 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
10325 return (const reg_entry *) NULL;
10326
1d3f8286
JB		 10327 /* Upper 16 vector registers are only available with VREX in 64bit
10328 mode, and require EVEX encoding. */
10329 if (r->reg_flags & RegVRex)
43234a1e
L		 10330 {
10331 if (!cpu_arch_flags.bitfield.cpuvrex
10332 || flag_code != CODE_64BIT)
10333 return (const reg_entry *) NULL;
1d3f8286
JB		 10334
10335 i.vec_encoding = vex_encoding_evex;
43234a1e
L		 10336 }
10337
4787f4a5
JB		 10338 if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword)
10339 && (!cpu_arch_flags.bitfield.cpulm || !r->reg_type.bitfield.control)
1ae00879 10340 && flag_code != CODE_64BIT)
20f0a1fc 10341 return (const reg_entry *) NULL;
1ae00879 10342
b7240065
JB		 10343 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
10344 return (const reg_entry *) NULL;
10345
252b5132
RH		 10346 return r;
10347}
4d1bb795
JB		 10348
10349/* REG_STRING starts *before* REGISTER_PREFIX. */
10350
10351static const reg_entry *
10352parse_register (char *reg_string, char **end_op)
10353{
10354 const reg_entry *r;
10355
10356 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
10357 r = parse_real_register (reg_string, end_op);
10358 else
10359 r = NULL;
10360 if (!r)
10361 {
10362 char *save = input_line_pointer;
10363 char c;
10364 symbolS *symbolP;
10365
10366 input_line_pointer = reg_string;
d02603dc 10367 c = get_symbol_name (&reg_string);
4d1bb795
JB		 10368 symbolP = symbol_find (reg_string);
10369 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
10370 {
10371 const expressionS *e = symbol_get_value_expression (symbolP);
10372
0398aac5 10373 know (e->X_op == O_register);
4eed87de 10374 know (e->X_add_number >= 0
c3fe08fa 10375 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 10376 r = i386_regtab + e->X_add_number;
d3bb6b49 10377 if ((r->reg_flags & RegVRex))
86fa6981 10378 i.vec_encoding = vex_encoding_evex;
4d1bb795
JB		 10379 *end_op = input_line_pointer;
10380 }
10381 *input_line_pointer = c;
10382 input_line_pointer = save;
10383 }
10384 return r;
10385}
10386
10387int
10388i386_parse_name (char *name, expressionS *e, char *nextcharP)
10389{
10390 const reg_entry *r;
10391 char *end = input_line_pointer;
10392
10393 *end = *nextcharP;
10394 r = parse_register (name, &input_line_pointer);
10395 if (r && end <= input_line_pointer)
10396 {
10397 *nextcharP = *input_line_pointer;
10398 *input_line_pointer = 0;
10399 e->X_op = O_register;
10400 e->X_add_number = r - i386_regtab;
10401 return 1;
10402 }
10403 input_line_pointer = end;
10404 *end = 0;
ee86248c 10405 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 10406}
10407
10408void
10409md_operand (expressionS *e)
10410{
ee86248c
JB		 10411 char *end;
10412 const reg_entry *r;
4d1bb795 10413
ee86248c
JB		 10414 switch (*input_line_pointer)
10415 {
10416 case REGISTER_PREFIX:
10417 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 10418 if (r)
10419 {
10420 e->X_op = O_register;
10421 e->X_add_number = r - i386_regtab;
10422 input_line_pointer = end;
10423 }
ee86248c
JB		 10424 break;
10425
10426 case '[':
9c2799c2 10427 gas_assert (intel_syntax);
ee86248c
JB		 10428 end = input_line_pointer++;
10429 expression (e);
10430 if (*input_line_pointer == ']')
10431 {
10432 ++input_line_pointer;
10433 e->X_op_symbol = make_expr_symbol (e);
10434 e->X_add_symbol = NULL;
10435 e->X_add_number = 0;
10436 e->X_op = O_index;
10437 }
10438 else
10439 {
10440 e->X_op = O_absent;
10441 input_line_pointer = end;
10442 }
10443 break;
4d1bb795
JB		 10444 }
10445}
10446
252b5132 10447\f
4cc782b5 10448#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
b6f8c7c4 10449const char *md_shortopts = "kVQ:sqnO::";
252b5132 10450#else
b6f8c7c4 10451const char *md_shortopts = "qnO::";
252b5132 10452#endif
6e0b89ee 10453
3e73aa7c 10454#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 10455#define OPTION_64 (OPTION_MD_BASE + 1)
10456#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 10457#define OPTION_MARCH (OPTION_MD_BASE + 3)
10458#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 10459#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
10460#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
10461#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
10462#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
bd5dea88 10463#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
c0f3af97 10464#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 10465#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 10466#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
10467#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
10468#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 10469#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 10470#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
10471#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 10472#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
d1982f93 10473#define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 10474#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
8dcea932 10475#define OPTION_MSHARED (OPTION_MD_BASE + 21)
5db04b09
L		 10476#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
10477#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
e4e00185 10478#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
b3b91714 10479
99ad8390
NC		 10480struct option md_longopts[] =
10481{
3e73aa7c 10482 {"32", no_argument, NULL, OPTION_32},
321098a5 10483#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 10484 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 10485 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 10486#endif
10487#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 10488 {"x32", no_argument, NULL, OPTION_X32},
8dcea932 10489 {"mshared", no_argument, NULL, OPTION_MSHARED},
6e0b89ee 10490#endif
b3b91714 10491 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 10492 {"march", required_argument, NULL, OPTION_MARCH},
10493 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 10494 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10495 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10496 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10497 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
c0f3af97 10498 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 10499 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 10500 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 10501 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 10502 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 10503 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10504 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 10505# if defined (TE_PE) || defined (TE_PEP)
10506 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10507#endif
d1982f93 10508 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
e4e00185 10509 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
0cb4071e 10510 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
d3d3c6db 10511 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
5db04b09
L		 10512 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10513 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
252b5132
RH		 10514 {NULL, no_argument, NULL, 0}
10515};
10516size_t md_longopts_size = sizeof (md_longopts);
10517
10518int
17b9d67d 10519md_parse_option (int c, const char *arg)
252b5132 10520{
91d6fa6a 10521 unsigned int j;
293f5f65 10522 char *arch, *next, *saved;
9103f4f4 10523
252b5132
RH		 10524 switch (c)
10525 {
12b55ccc
L		 10526 case 'n':
10527 optimize_align_code = 0;
10528 break;
10529
a38cf1db
AM		 10530 case 'q':
10531 quiet_warnings = 1;
252b5132
RH		 10532 break;
10533
10534#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 10535 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10536 should be emitted or not. FIXME: Not implemented. */
10537 case 'Q':
252b5132
RH		 10538 break;
10539
10540 /* -V: SVR4 argument to print version ID. */
10541 case 'V':
10542 print_version_id ();
10543 break;
10544
a38cf1db
AM		 10545 /* -k: Ignore for FreeBSD compatibility. */
10546 case 'k':
252b5132 10547 break;
4cc782b5
ILT		 10548
10549 case 's':
10550 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 10551 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 10552 break;
8dcea932
L		 10553
10554 case OPTION_MSHARED:
10555 shared = 1;
10556 break;
99ad8390 10557#endif
321098a5 10558#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 10559 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 10560 case OPTION_64:
10561 {
10562 const char **list, **l;
10563
3e73aa7c
JH		 10564 list = bfd_target_list ();
10565 for (l = list; *l != NULL; l++)
8620418b 10566 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 10567 || strcmp (*l, "coff-x86-64") == 0
10568 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 10569 || strcmp (*l, "pei-x86-64") == 0
10570 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 10571 {
10572 default_arch = "x86_64";
10573 break;
10574 }
3e73aa7c 10575 if (*l == NULL)
2b5d6a91 10576 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 10577 free (list);
10578 }
10579 break;
10580#endif
252b5132 10581
351f65ca 10582#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 10583 case OPTION_X32:
351f65ca
L		 10584 if (IS_ELF)
10585 {
10586 const char **list, **l;
10587
10588 list = bfd_target_list ();
10589 for (l = list; *l != NULL; l++)
10590 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10591 {
10592 default_arch = "x86_64:32";
10593 break;
10594 }
10595 if (*l == NULL)
2b5d6a91 10596 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 10597 free (list);
10598 }
10599 else
10600 as_fatal (_("32bit x86_64 is only supported for ELF"));
10601 break;
10602#endif
10603
6e0b89ee
AM		 10604 case OPTION_32:
10605 default_arch = "i386";
10606 break;
10607
b3b91714
AM		 10608 case OPTION_DIVIDE:
10609#ifdef SVR4_COMMENT_CHARS
10610 {
10611 char *n, *t;
10612 const char *s;
10613
add39d23 10614 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
b3b91714
AM		 10615 t = n;
10616 for (s = i386_comment_chars; *s != '\0'; s++)
10617 if (*s != '/')
10618 *t++ = *s;
10619 *t = '\0';
10620 i386_comment_chars = n;
10621 }
10622#endif
10623 break;
10624
9103f4f4 10625 case OPTION_MARCH:
293f5f65
L		 10626 saved = xstrdup (arg);
10627 arch = saved;
10628 /* Allow -march=+nosse. */
10629 if (*arch == '+')
10630 arch++;
6305a203 10631 do
9103f4f4 10632 {
6305a203 10633 if (*arch == '.')
2b5d6a91 10634 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10635 next = strchr (arch, '+');
10636 if (next)
10637 *next++ = '\0';
91d6fa6a 10638 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10639 {
91d6fa6a 10640 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 10641 {
6305a203 10642 /* Processor. */
1ded5609
JB		 10643 if (! cpu_arch[j].flags.bitfield.cpui386)
10644 continue;
10645
91d6fa6a 10646 cpu_arch_name = cpu_arch[j].name;
6305a203 10647 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 10648 cpu_arch_flags = cpu_arch[j].flags;
10649 cpu_arch_isa = cpu_arch[j].type;
10650 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 10651 if (!cpu_arch_tune_set)
10652 {
10653 cpu_arch_tune = cpu_arch_isa;
10654 cpu_arch_tune_flags = cpu_arch_isa_flags;
10655 }
10656 break;
10657 }
91d6fa6a
NC		 10658 else if (*cpu_arch [j].name == '.'
10659 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203 10660 {
33eaf5de 10661 /* ISA extension. */
6305a203 10662 i386_cpu_flags flags;
309d3373 10663
293f5f65
L		 10664 flags = cpu_flags_or (cpu_arch_flags,
10665 cpu_arch[j].flags);
81486035 10666
5b64d091 10667 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 10668 {
10669 if (cpu_sub_arch_name)
10670 {
10671 char *name = cpu_sub_arch_name;
10672 cpu_sub_arch_name = concat (name,
91d6fa6a 10673 cpu_arch[j].name,
1bf57e9f 10674 (const char *) NULL);
6305a203
L		 10675 free (name);
10676 }
10677 else
91d6fa6a 10678 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 10679 cpu_arch_flags = flags;
a586129e 10680 cpu_arch_isa_flags = flags;
6305a203 10681 }
0089dace
L		 10682 else
10683 cpu_arch_isa_flags
10684 = cpu_flags_or (cpu_arch_isa_flags,
10685 cpu_arch[j].flags);
6305a203 10686 break;
ccc9c027 10687 }
9103f4f4 10688 }
6305a203 10689
293f5f65
L		 10690 if (j >= ARRAY_SIZE (cpu_arch))
10691 {
33eaf5de 10692 /* Disable an ISA extension. */
293f5f65
L		 10693 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10694 if (strcmp (arch, cpu_noarch [j].name) == 0)
10695 {
10696 i386_cpu_flags flags;
10697
10698 flags = cpu_flags_and_not (cpu_arch_flags,
10699 cpu_noarch[j].flags);
10700 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10701 {
10702 if (cpu_sub_arch_name)
10703 {
10704 char *name = cpu_sub_arch_name;
10705 cpu_sub_arch_name = concat (arch,
10706 (const char *) NULL);
10707 free (name);
10708 }
10709 else
10710 cpu_sub_arch_name = xstrdup (arch);
10711 cpu_arch_flags = flags;
10712 cpu_arch_isa_flags = flags;
10713 }
10714 break;
10715 }
10716
10717 if (j >= ARRAY_SIZE (cpu_noarch))
10718 j = ARRAY_SIZE (cpu_arch);
10719 }
10720
91d6fa6a 10721 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10722 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10723
10724 arch = next;
9103f4f4 10725 }
293f5f65
L		 10726 while (next != NULL);
10727 free (saved);
9103f4f4
L		 10728 break;
10729
10730 case OPTION_MTUNE:
10731 if (*arg == '.')
2b5d6a91 10732 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 10733 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10734 {
91d6fa6a 10735 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 10736 {
ccc9c027 10737 cpu_arch_tune_set = 1;
91d6fa6a
NC		 10738 cpu_arch_tune = cpu_arch [j].type;
10739 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 10740 break;
10741 }
10742 }
91d6fa6a 10743 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10744 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 10745 break;
10746
1efbbeb4
L		 10747 case OPTION_MMNEMONIC:
10748 if (strcasecmp (arg, "att") == 0)
10749 intel_mnemonic = 0;
10750 else if (strcasecmp (arg, "intel") == 0)
10751 intel_mnemonic = 1;
10752 else
2b5d6a91 10753 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 10754 break;
10755
10756 case OPTION_MSYNTAX:
10757 if (strcasecmp (arg, "att") == 0)
10758 intel_syntax = 0;
10759 else if (strcasecmp (arg, "intel") == 0)
10760 intel_syntax = 1;
10761 else
2b5d6a91 10762 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 10763 break;
10764
10765 case OPTION_MINDEX_REG:
10766 allow_index_reg = 1;
10767 break;
10768
10769 case OPTION_MNAKED_REG:
10770 allow_naked_reg = 1;
10771 break;
10772
c0f3af97
L		 10773 case OPTION_MSSE2AVX:
10774 sse2avx = 1;
10775 break;
10776
daf50ae7
L		 10777 case OPTION_MSSE_CHECK:
10778 if (strcasecmp (arg, "error") == 0)
7bab8ab5 10779 sse_check = check_error;
daf50ae7 10780 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 10781 sse_check = check_warning;
daf50ae7 10782 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 10783 sse_check = check_none;
daf50ae7 10784 else
2b5d6a91 10785 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 10786 break;
10787
7bab8ab5
JB		 10788 case OPTION_MOPERAND_CHECK:
10789 if (strcasecmp (arg, "error") == 0)
10790 operand_check = check_error;
10791 else if (strcasecmp (arg, "warning") == 0)
10792 operand_check = check_warning;
10793 else if (strcasecmp (arg, "none") == 0)
10794 operand_check = check_none;
10795 else
10796 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10797 break;
10798
539f890d
L		 10799 case OPTION_MAVXSCALAR:
10800 if (strcasecmp (arg, "128") == 0)
10801 avxscalar = vex128;
10802 else if (strcasecmp (arg, "256") == 0)
10803 avxscalar = vex256;
10804 else
2b5d6a91 10805 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 10806 break;
10807
7e8b059b
L		 10808 case OPTION_MADD_BND_PREFIX:
10809 add_bnd_prefix = 1;
10810 break;
10811
43234a1e
L		 10812 case OPTION_MEVEXLIG:
10813 if (strcmp (arg, "128") == 0)
10814 evexlig = evexl128;
10815 else if (strcmp (arg, "256") == 0)
10816 evexlig = evexl256;
10817 else if (strcmp (arg, "512") == 0)
10818 evexlig = evexl512;
10819 else
10820 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10821 break;
10822
d3d3c6db
IT		 10823 case OPTION_MEVEXRCIG:
10824 if (strcmp (arg, "rne") == 0)
10825 evexrcig = rne;
10826 else if (strcmp (arg, "rd") == 0)
10827 evexrcig = rd;
10828 else if (strcmp (arg, "ru") == 0)
10829 evexrcig = ru;
10830 else if (strcmp (arg, "rz") == 0)
10831 evexrcig = rz;
10832 else
10833 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10834 break;
10835
43234a1e
L		 10836 case OPTION_MEVEXWIG:
10837 if (strcmp (arg, "0") == 0)
10838 evexwig = evexw0;
10839 else if (strcmp (arg, "1") == 0)
10840 evexwig = evexw1;
10841 else
10842 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10843 break;
10844
167ad85b
TG		 10845# if defined (TE_PE) || defined (TE_PEP)
10846 case OPTION_MBIG_OBJ:
10847 use_big_obj = 1;
10848 break;
10849#endif
10850
d1982f93 10851 case OPTION_MOMIT_LOCK_PREFIX:
d022bddd
IT		 10852 if (strcasecmp (arg, "yes") == 0)
10853 omit_lock_prefix = 1;
10854 else if (strcasecmp (arg, "no") == 0)
10855 omit_lock_prefix = 0;
10856 else
10857 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10858 break;
10859
e4e00185
AS		 10860 case OPTION_MFENCE_AS_LOCK_ADD:
10861 if (strcasecmp (arg, "yes") == 0)
10862 avoid_fence = 1;
10863 else if (strcasecmp (arg, "no") == 0)
10864 avoid_fence = 0;
10865 else
10866 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10867 break;
10868
0cb4071e
L		 10869 case OPTION_MRELAX_RELOCATIONS:
10870 if (strcasecmp (arg, "yes") == 0)
10871 generate_relax_relocations = 1;
10872 else if (strcasecmp (arg, "no") == 0)
10873 generate_relax_relocations = 0;
10874 else
10875 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10876 break;
10877
5db04b09 10878 case OPTION_MAMD64:
e89c5eaa 10879 intel64 = 0;
5db04b09
L		 10880 break;
10881
10882 case OPTION_MINTEL64:
e89c5eaa 10883 intel64 = 1;
5db04b09
L		 10884 break;
10885
b6f8c7c4
L		 10886 case 'O':
10887 if (arg == NULL)
10888 {
10889 optimize = 1;
10890 /* Turn off -Os. */
10891 optimize_for_space = 0;
10892 }
10893 else if (*arg == 's')
10894 {
10895 optimize_for_space = 1;
10896 /* Turn on all encoding optimizations. */
10897 optimize = -1;
10898 }
10899 else
10900 {
10901 optimize = atoi (arg);
10902 /* Turn off -Os. */
10903 optimize_for_space = 0;
10904 }
10905 break;
10906
252b5132
RH		 10907 default:
10908 return 0;
10909 }
10910 return 1;
10911}
10912
8a2c8fef
L		 10913#define MESSAGE_TEMPLATE \
10914" "
10915
293f5f65
L		 10916static char *
10917output_message (FILE *stream, char *p, char *message, char *start,
10918 int *left_p, const char *name, int len)
10919{
10920 int size = sizeof (MESSAGE_TEMPLATE);
10921 int left = *left_p;
10922
10923 /* Reserve 2 spaces for ", " or ",\0" */
10924 left -= len + 2;
10925
10926 /* Check if there is any room. */
10927 if (left >= 0)
10928 {
10929 if (p != start)
10930 {
10931 *p++ = ',';
10932 *p++ = ' ';
10933 }
10934 p = mempcpy (p, name, len);
10935 }
10936 else
10937 {
10938 /* Output the current message now and start a new one. */
10939 *p++ = ',';
10940 *p = '\0';
10941 fprintf (stream, "%s\n", message);
10942 p = start;
10943 left = size - (start - message) - len - 2;
10944
10945 gas_assert (left >= 0);
10946
10947 p = mempcpy (p, name, len);
10948 }
10949
10950 *left_p = left;
10951 return p;
10952}
10953
8a2c8fef 10954static void
1ded5609 10955show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 10956{
10957 static char message[] = MESSAGE_TEMPLATE;
10958 char *start = message + 27;
10959 char *p;
10960 int size = sizeof (MESSAGE_TEMPLATE);
10961 int left;
10962 const char *name;
10963 int len;
10964 unsigned int j;
10965
10966 p = start;
10967 left = size - (start - message);
10968 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10969 {
10970 /* Should it be skipped? */
10971 if (cpu_arch [j].skip)
10972 continue;
10973
10974 name = cpu_arch [j].name;
10975 len = cpu_arch [j].len;
10976 if (*name == '.')
10977 {
10978 /* It is an extension. Skip if we aren't asked to show it. */
10979 if (ext)
10980 {
10981 name++;
10982 len--;
10983 }
10984 else
10985 continue;
10986 }
10987 else if (ext)
10988 {
10989 /* It is an processor. Skip if we show only extension. */
10990 continue;
10991 }
1ded5609
JB		 10992 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10993 {
10994 /* It is an impossible processor - skip. */
10995 continue;
10996 }
8a2c8fef 10997
293f5f65 10998 p = output_message (stream, p, message, start, &left, name, len);
8a2c8fef
L		 10999 }
11000
293f5f65
L		 11001 /* Display disabled extensions. */
11002 if (ext)
11003 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
11004 {
11005 name = cpu_noarch [j].name;
11006 len = cpu_noarch [j].len;
11007 p = output_message (stream, p, message, start, &left, name,
11008 len);
11009 }
11010
8a2c8fef
L		 11011 *p = '\0';
11012 fprintf (stream, "%s\n", message);
11013}
11014
252b5132 11015void
8a2c8fef 11016md_show_usage (FILE *stream)
252b5132 11017{
4cc782b5
ILT		 11018#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11019 fprintf (stream, _("\
a38cf1db
AM		 11020 -Q ignored\n\
11021 -V print assembler version number\n\
b3b91714
AM		 11022 -k ignored\n"));
11023#endif
11024 fprintf (stream, _("\
12b55ccc 11025 -n Do not optimize code alignment\n\
b3b91714
AM		 11026 -q quieten some warnings\n"));
11027#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11028 fprintf (stream, _("\
a38cf1db 11029 -s ignored\n"));
b3b91714 11030#endif
321098a5
L		 11031#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
11032 || defined (TE_PE) || defined (TE_PEP))
751d281c 11033 fprintf (stream, _("\
570561f7 11034 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 11035#endif
b3b91714
AM		 11036#ifdef SVR4_COMMENT_CHARS
11037 fprintf (stream, _("\
11038 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 11039#else
11040 fprintf (stream, _("\
b3b91714 11041 --divide ignored\n"));
4cc782b5 11042#endif
9103f4f4 11043 fprintf (stream, _("\
6305a203 11044 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 11045 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 11046 show_arch (stream, 0, 1);
8a2c8fef
L		 11047 fprintf (stream, _("\
11048 EXTENSION is combination of:\n"));
1ded5609 11049 show_arch (stream, 1, 0);
6305a203 11050 fprintf (stream, _("\
8a2c8fef 11051 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 11052 show_arch (stream, 0, 0);
ba104c83 11053 fprintf (stream, _("\
c0f3af97
L		 11054 -msse2avx encode SSE instructions with VEX prefix\n"));
11055 fprintf (stream, _("\
daf50ae7
L		 11056 -msse-check=[none|error|warning]\n\
11057 check SSE instructions\n"));
11058 fprintf (stream, _("\
7bab8ab5
JB		 11059 -moperand-check=[none|error|warning]\n\
11060 check operand combinations for validity\n"));
11061 fprintf (stream, _("\
539f890d
L		 11062 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
11063 length\n"));
11064 fprintf (stream, _("\
43234a1e
L		 11065 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
11066 length\n"));
11067 fprintf (stream, _("\
11068 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
11069 for EVEX.W bit ignored instructions\n"));
11070 fprintf (stream, _("\
d3d3c6db
IT		 11071 -mevexrcig=[rne|rd|ru|rz]\n\
11072 encode EVEX instructions with specific EVEX.RC value\n\
11073 for SAE-only ignored instructions\n"));
11074 fprintf (stream, _("\
ba104c83
L		 11075 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
11076 fprintf (stream, _("\
11077 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
11078 fprintf (stream, _("\
11079 -mindex-reg support pseudo index registers\n"));
11080 fprintf (stream, _("\
11081 -mnaked-reg don't require `%%' prefix for registers\n"));
11082 fprintf (stream, _("\
7e8b059b 11083 -madd-bnd-prefix add BND prefix for all valid branches\n"));
8dcea932
L		 11084 fprintf (stream, _("\
11085 -mshared disable branch optimization for shared code\n"));
167ad85b
TG		 11086# if defined (TE_PE) || defined (TE_PEP)
11087 fprintf (stream, _("\
11088 -mbig-obj generate big object files\n"));
11089#endif
d022bddd
IT		 11090 fprintf (stream, _("\
11091 -momit-lock-prefix=[no|yes]\n\
11092 strip all lock prefixes\n"));
5db04b09 11093 fprintf (stream, _("\
e4e00185
AS		 11094 -mfence-as-lock-add=[no|yes]\n\
11095 encode lfence, mfence and sfence as\n\
11096 lock addl $0x0, (%%{re}sp)\n"));
11097 fprintf (stream, _("\
0cb4071e
L		 11098 -mrelax-relocations=[no|yes]\n\
11099 generate relax relocations\n"));
11100 fprintf (stream, _("\
5db04b09
L		 11101 -mamd64 accept only AMD64 ISA\n"));
11102 fprintf (stream, _("\
11103 -mintel64 accept only Intel64 ISA\n"));
252b5132
RH		 11104}
11105
3e73aa7c 11106#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 11107 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 11108 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 11109
11110/* Pick the target format to use. */
11111
47926f60 11112const char *
e3bb37b5 11113i386_target_format (void)
252b5132 11114{
351f65ca
L		 11115 if (!strncmp (default_arch, "x86_64", 6))
11116 {
11117 update_code_flag (CODE_64BIT, 1);
11118 if (default_arch[6] == '\0')
7f56bc95 11119 x86_elf_abi = X86_64_ABI;
351f65ca 11120 else
7f56bc95 11121 x86_elf_abi = X86_64_X32_ABI;
351f65ca 11122 }
3e73aa7c 11123 else if (!strcmp (default_arch, "i386"))
78f12dd3 11124 update_code_flag (CODE_32BIT, 1);
5197d474
L		 11125 else if (!strcmp (default_arch, "iamcu"))
11126 {
11127 update_code_flag (CODE_32BIT, 1);
11128 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
11129 {
11130 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
11131 cpu_arch_name = "iamcu";
11132 cpu_sub_arch_name = NULL;
11133 cpu_arch_flags = iamcu_flags;
11134 cpu_arch_isa = PROCESSOR_IAMCU;
11135 cpu_arch_isa_flags = iamcu_flags;
11136 if (!cpu_arch_tune_set)
11137 {
11138 cpu_arch_tune = cpu_arch_isa;
11139 cpu_arch_tune_flags = cpu_arch_isa_flags;
11140 }
11141 }
8d471ec1 11142 else if (cpu_arch_isa != PROCESSOR_IAMCU)
5197d474
L		 11143 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
11144 cpu_arch_name);
11145 }
3e73aa7c 11146 else
2b5d6a91 11147 as_fatal (_("unknown architecture"));
89507696
JB		 11148
11149 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
11150 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11151 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
11152 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
11153
252b5132
RH		 11154 switch (OUTPUT_FLAVOR)
11155 {
9384f2ff 11156#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 11157 case bfd_target_aout_flavour:
47926f60 11158 return AOUT_TARGET_FORMAT;
4c63da97 11159#endif
9384f2ff
AM		 11160#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
11161# if defined (TE_PE) || defined (TE_PEP)
11162 case bfd_target_coff_flavour:
167ad85b
TG		 11163 if (flag_code == CODE_64BIT)
11164 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
11165 else
11166 return "pe-i386";
9384f2ff 11167# elif defined (TE_GO32)
0561d57c
JK		 11168 case bfd_target_coff_flavour:
11169 return "coff-go32";
9384f2ff 11170# else
252b5132
RH		 11171 case bfd_target_coff_flavour:
11172 return "coff-i386";
9384f2ff 11173# endif
4c63da97 11174#endif
3e73aa7c 11175#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 11176 case bfd_target_elf_flavour:
3e73aa7c 11177 {
351f65ca
L		 11178 const char *format;
11179
11180 switch (x86_elf_abi)
4fa24527 11181 {
351f65ca
L		 11182 default:
11183 format = ELF_TARGET_FORMAT;
11184 break;
7f56bc95 11185 case X86_64_ABI:
351f65ca 11186 use_rela_relocations = 1;
4fa24527 11187 object_64bit = 1;
351f65ca
L		 11188 format = ELF_TARGET_FORMAT64;
11189 break;
7f56bc95 11190 case X86_64_X32_ABI:
4fa24527 11191 use_rela_relocations = 1;
351f65ca 11192 object_64bit = 1;
862be3fb 11193 disallow_64bit_reloc = 1;
351f65ca
L		 11194 format = ELF_TARGET_FORMAT32;
11195 break;
4fa24527 11196 }
3632d14b 11197 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 11198 {
7f56bc95 11199 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 11200 as_fatal (_("Intel L1OM is 64bit only"));
11201 return ELF_TARGET_L1OM_FORMAT;
11202 }
b49f93f6 11203 else if (cpu_arch_isa == PROCESSOR_K1OM)
7a9068fe
L		 11204 {
11205 if (x86_elf_abi != X86_64_ABI)
11206 as_fatal (_("Intel K1OM is 64bit only"));
11207 return ELF_TARGET_K1OM_FORMAT;
11208 }
81486035
L		 11209 else if (cpu_arch_isa == PROCESSOR_IAMCU)
11210 {
11211 if (x86_elf_abi != I386_ABI)
11212 as_fatal (_("Intel MCU is 32bit only"));
11213 return ELF_TARGET_IAMCU_FORMAT;
11214 }
8a9036a4 11215 else
351f65ca 11216 return format;
3e73aa7c 11217 }
e57f8c65
TG		 11218#endif
11219#if defined (OBJ_MACH_O)
11220 case bfd_target_mach_o_flavour:
d382c579
TG		 11221 if (flag_code == CODE_64BIT)
11222 {
11223 use_rela_relocations = 1;
11224 object_64bit = 1;
11225 return "mach-o-x86-64";
11226 }
11227 else
11228 return "mach-o-i386";
4c63da97 11229#endif
252b5132
RH		 11230 default:
11231 abort ();
11232 return NULL;
11233 }
11234}
11235
47926f60 11236#endif /* OBJ_MAYBE_ more than one */
252b5132 11237\f
252b5132 11238symbolS *
7016a5d5 11239md_undefined_symbol (char *name)
252b5132 11240{
18dc2407
ILT		 11241 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
11242 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
11243 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
11244 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 11245 {
11246 if (!GOT_symbol)
11247 {
11248 if (symbol_find (name))
11249 as_bad (_("GOT already in symbol table"));
11250 GOT_symbol = symbol_new (name, undefined_section,
11251 (valueT) 0, &zero_address_frag);
11252 };
11253 return GOT_symbol;
11254 }
252b5132
RH		 11255 return 0;
11256}
11257
11258/* Round up a section size to the appropriate boundary. */
47926f60 11259
252b5132 11260valueT
7016a5d5 11261md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 11262{
4c63da97
AM		 11263#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
11264 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
11265 {
11266 /* For a.out, force the section size to be aligned. If we don't do
11267 this, BFD will align it for us, but it will not write out the
11268 final bytes of the section. This may be a bug in BFD, but it is
11269 easier to fix it here since that is how the other a.out targets
11270 work. */
11271 int align;
11272
11273 align = bfd_get_section_alignment (stdoutput, segment);
8d3842cd 11274 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
4c63da97 11275 }
252b5132
RH		 11276#endif
11277
11278 return size;
11279}
11280
11281/* On the i386, PC-relative offsets are relative to the start of the
11282 next instruction. That is, the address of the offset, plus its
11283 size, since the offset is always the last part of the insn. */
11284
11285long
e3bb37b5 11286md_pcrel_from (fixS *fixP)
252b5132
RH		 11287{
11288 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
11289}
11290
11291#ifndef I386COFF
11292
11293static void
e3bb37b5 11294s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 11295{
29b0f896 11296 int temp;
252b5132 11297
8a75718c
JB		 11298#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11299 if (IS_ELF)
11300 obj_elf_section_change_hook ();
11301#endif
252b5132
RH		 11302 temp = get_absolute_expression ();
11303 subseg_set (bss_section, (subsegT) temp);
11304 demand_empty_rest_of_line ();
11305}
11306
11307#endif
11308
252b5132 11309void
e3bb37b5 11310i386_validate_fix (fixS *fixp)
252b5132 11311{
02a86693 11312 if (fixp->fx_subsy)
252b5132 11313 {
02a86693 11314 if (fixp->fx_subsy == GOT_symbol)
23df1078 11315 {
02a86693
L		 11316 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
11317 {
11318 if (!object_64bit)
11319 abort ();
11320#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11321 if (fixp->fx_tcbit2)
56ceb5b5
L		 11322 fixp->fx_r_type = (fixp->fx_tcbit
11323 ? BFD_RELOC_X86_64_REX_GOTPCRELX
11324 : BFD_RELOC_X86_64_GOTPCRELX);
02a86693
L		 11325 else
11326#endif
11327 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
11328 }
d6ab8113 11329 else
02a86693
L		 11330 {
11331 if (!object_64bit)
11332 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
11333 else
11334 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
11335 }
11336 fixp->fx_subsy = 0;
23df1078 11337 }
252b5132 11338 }
02a86693
L		 11339#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11340 else if (!object_64bit)
11341 {
11342 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
11343 && fixp->fx_tcbit2)
11344 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
11345 }
11346#endif
252b5132
RH		 11347}
11348
252b5132 11349arelent *
7016a5d5 11350tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 11351{
11352 arelent *rel;
11353 bfd_reloc_code_real_type code;
11354
11355 switch (fixp->fx_r_type)
11356 {
8ce3d284 11357#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 11358 case BFD_RELOC_SIZE32:
11359 case BFD_RELOC_SIZE64:
11360 if (S_IS_DEFINED (fixp->fx_addsy)
11361 && !S_IS_EXTERNAL (fixp->fx_addsy))
11362 {
11363 /* Resolve size relocation against local symbol to size of
11364 the symbol plus addend. */
11365 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
11366 if (fixp->fx_r_type == BFD_RELOC_SIZE32
11367 && !fits_in_unsigned_long (value))
11368 as_bad_where (fixp->fx_file, fixp->fx_line,
11369 _("symbol size computation overflow"));
11370 fixp->fx_addsy = NULL;
11371 fixp->fx_subsy = NULL;
11372 md_apply_fix (fixp, (valueT *) &value, NULL);
11373 return NULL;
11374 }
8ce3d284 11375#endif
1a0670f3 11376 /* Fall through. */
8fd4256d 11377
3e73aa7c
JH		 11378 case BFD_RELOC_X86_64_PLT32:
11379 case BFD_RELOC_X86_64_GOT32:
11380 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 11381 case BFD_RELOC_X86_64_GOTPCRELX:
11382 case BFD_RELOC_X86_64_REX_GOTPCRELX:
252b5132
RH		 11383 case BFD_RELOC_386_PLT32:
11384 case BFD_RELOC_386_GOT32:
02a86693 11385 case BFD_RELOC_386_GOT32X:
252b5132
RH		 11386 case BFD_RELOC_386_GOTOFF:
11387 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 11388 case BFD_RELOC_386_TLS_GD:
11389 case BFD_RELOC_386_TLS_LDM:
11390 case BFD_RELOC_386_TLS_LDO_32:
11391 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 11392 case BFD_RELOC_386_TLS_IE:
11393 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 11394 case BFD_RELOC_386_TLS_LE_32:
11395 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 11396 case BFD_RELOC_386_TLS_GOTDESC:
11397 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 11398 case BFD_RELOC_X86_64_TLSGD:
11399 case BFD_RELOC_X86_64_TLSLD:
11400 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 11401 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 11402 case BFD_RELOC_X86_64_GOTTPOFF:
11403 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 11404 case BFD_RELOC_X86_64_TPOFF64:
11405 case BFD_RELOC_X86_64_GOTOFF64:
11406 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 11407 case BFD_RELOC_X86_64_GOT64:
11408 case BFD_RELOC_X86_64_GOTPCREL64:
11409 case BFD_RELOC_X86_64_GOTPC64:
11410 case BFD_RELOC_X86_64_GOTPLT64:
11411 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 11412 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11413 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 11414 case BFD_RELOC_RVA:
11415 case BFD_RELOC_VTABLE_ENTRY:
11416 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 11417#ifdef TE_PE
11418 case BFD_RELOC_32_SECREL:
11419#endif
252b5132
RH		 11420 code = fixp->fx_r_type;
11421 break;
dbbaec26
L		 11422 case BFD_RELOC_X86_64_32S:
11423 if (!fixp->fx_pcrel)
11424 {
11425 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
11426 code = fixp->fx_r_type;
11427 break;
11428 }
1a0670f3 11429 /* Fall through. */
252b5132 11430 default:
93382f6d 11431 if (fixp->fx_pcrel)
252b5132 11432 {
93382f6d
AM		 11433 switch (fixp->fx_size)
11434 {
11435 default:
b091f402
AM		 11436 as_bad_where (fixp->fx_file, fixp->fx_line,
11437 _("can not do %d byte pc-relative relocation"),
11438 fixp->fx_size);
93382f6d
AM		 11439 code = BFD_RELOC_32_PCREL;
11440 break;
11441 case 1: code = BFD_RELOC_8_PCREL; break;
11442 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 11443 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 11444#ifdef BFD64
11445 case 8: code = BFD_RELOC_64_PCREL; break;
11446#endif
93382f6d
AM		 11447 }
11448 }
11449 else
11450 {
11451 switch (fixp->fx_size)
11452 {
11453 default:
b091f402
AM		 11454 as_bad_where (fixp->fx_file, fixp->fx_line,
11455 _("can not do %d byte relocation"),
11456 fixp->fx_size);
93382f6d
AM		 11457 code = BFD_RELOC_32;
11458 break;
11459 case 1: code = BFD_RELOC_8; break;
11460 case 2: code = BFD_RELOC_16; break;
11461 case 4: code = BFD_RELOC_32; break;
937149dd 11462#ifdef BFD64
3e73aa7c 11463 case 8: code = BFD_RELOC_64; break;
937149dd 11464#endif
93382f6d 11465 }
252b5132
RH		 11466 }
11467 break;
11468 }
252b5132 11469
d182319b
JB		 11470 if ((code == BFD_RELOC_32
11471 || code == BFD_RELOC_32_PCREL
11472 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 11473 && GOT_symbol
11474 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 11475 {
4fa24527 11476 if (!object_64bit)
d6ab8113
JB		 11477 code = BFD_RELOC_386_GOTPC;
11478 else
11479 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 11480 }
7b81dfbb
AJ		 11481 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
11482 && GOT_symbol
11483 && fixp->fx_addsy == GOT_symbol)
11484 {
11485 code = BFD_RELOC_X86_64_GOTPC64;
11486 }
252b5132 11487
add39d23
TS		 11488 rel = XNEW (arelent);
11489 rel->sym_ptr_ptr = XNEW (asymbol *);
49309057 11490 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 11491
11492 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 11493
3e73aa7c
JH		 11494 if (!use_rela_relocations)
11495 {
11496 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
11497 vtable entry to be used in the relocation's section offset. */
11498 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
11499 rel->address = fixp->fx_offset;
fbeb56a4
DK		 11500#if defined (OBJ_COFF) && defined (TE_PE)
11501 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
11502 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
11503 else
11504#endif
c6682705 11505 rel->addend = 0;
3e73aa7c
JH		 11506 }
11507 /* Use the rela in 64bit mode. */
252b5132 11508 else
3e73aa7c 11509 {
862be3fb
L		 11510 if (disallow_64bit_reloc)
11511 switch (code)
11512 {
862be3fb
L		 11513 case BFD_RELOC_X86_64_DTPOFF64:
11514 case BFD_RELOC_X86_64_TPOFF64:
11515 case BFD_RELOC_64_PCREL:
11516 case BFD_RELOC_X86_64_GOTOFF64:
11517 case BFD_RELOC_X86_64_GOT64:
11518 case BFD_RELOC_X86_64_GOTPCREL64:
11519 case BFD_RELOC_X86_64_GOTPC64:
11520 case BFD_RELOC_X86_64_GOTPLT64:
11521 case BFD_RELOC_X86_64_PLTOFF64:
11522 as_bad_where (fixp->fx_file, fixp->fx_line,
11523 _("cannot represent relocation type %s in x32 mode"),
11524 bfd_get_reloc_code_name (code));
11525 break;
11526 default:
11527 break;
11528 }
11529
062cd5e7
AS		 11530 if (!fixp->fx_pcrel)
11531 rel->addend = fixp->fx_offset;
11532 else
11533 switch (code)
11534 {
11535 case BFD_RELOC_X86_64_PLT32:
11536 case BFD_RELOC_X86_64_GOT32:
11537 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 11538 case BFD_RELOC_X86_64_GOTPCRELX:
11539 case BFD_RELOC_X86_64_REX_GOTPCRELX:
bffbf940
JJ		 11540 case BFD_RELOC_X86_64_TLSGD:
11541 case BFD_RELOC_X86_64_TLSLD:
11542 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 11543 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11544 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 11545 rel->addend = fixp->fx_offset - fixp->fx_size;
11546 break;
11547 default:
11548 rel->addend = (section->vma
11549 - fixp->fx_size
11550 + fixp->fx_addnumber
11551 + md_pcrel_from (fixp));
11552 break;
11553 }
3e73aa7c
JH		 11554 }
11555
252b5132
RH		 11556 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11557 if (rel->howto == NULL)
11558 {
11559 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 11560 _("cannot represent relocation type %s"),
252b5132
RH		 11561 bfd_get_reloc_code_name (code));
11562 /* Set howto to a garbage value so that we can keep going. */
11563 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 11564 gas_assert (rel->howto != NULL);
252b5132
RH		 11565 }
11566
11567 return rel;
11568}
11569
ee86248c 11570#include "tc-i386-intel.c"
54cfded0 11571
a60de03c
JB		 11572void
11573tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 11574{
a60de03c
JB		 11575 int saved_naked_reg;
11576 char saved_register_dot;
54cfded0 11577
a60de03c
JB		 11578 saved_naked_reg = allow_naked_reg;
11579 allow_naked_reg = 1;
11580 saved_register_dot = register_chars['.'];
11581 register_chars['.'] = '.';
11582 allow_pseudo_reg = 1;
11583 expression_and_evaluate (exp);
11584 allow_pseudo_reg = 0;
11585 register_chars['.'] = saved_register_dot;
11586 allow_naked_reg = saved_naked_reg;
11587
e96d56a1 11588 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 11589 {
a60de03c
JB		 11590 if ((addressT) exp->X_add_number < i386_regtab_size)
11591 {
11592 exp->X_op = O_constant;
11593 exp->X_add_number = i386_regtab[exp->X_add_number]
11594 .dw2_regnum[flag_code >> 1];
11595 }
11596 else
11597 exp->X_op = O_illegal;
54cfded0 11598 }
54cfded0
AM		 11599}
11600
11601void
11602tc_x86_frame_initial_instructions (void)
11603{
a60de03c
JB		 11604 static unsigned int sp_regno[2];
11605
11606 if (!sp_regno[flag_code >> 1])
11607 {
11608 char *saved_input = input_line_pointer;
11609 char sp[][4] = {"esp", "rsp"};
11610 expressionS exp;
a4447b93 11611
a60de03c
JB		 11612 input_line_pointer = sp[flag_code >> 1];
11613 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 11614 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 11615 sp_regno[flag_code >> 1] = exp.X_add_number;
11616 input_line_pointer = saved_input;
11617 }
a4447b93 11618
61ff971f
L		 11619 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11620 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 11621}
d2b2c203 11622
d7921315
L		 11623int
11624x86_dwarf2_addr_size (void)
11625{
11626#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11627 if (x86_elf_abi == X86_64_X32_ABI)
11628 return 4;
11629#endif
11630 return bfd_arch_bits_per_address (stdoutput) / 8;
11631}
11632
d2b2c203
DJ		 11633int
11634i386_elf_section_type (const char *str, size_t len)
11635{
11636 if (flag_code == CODE_64BIT
11637 && len == sizeof ("unwind") - 1
11638 && strncmp (str, "unwind", 6) == 0)
11639 return SHT_X86_64_UNWIND;
11640
11641 return -1;
11642}
bb41ade5 11643
ad5fec3b
EB		 11644#ifdef TE_SOLARIS
11645void
11646i386_solaris_fix_up_eh_frame (segT sec)
11647{
11648 if (flag_code == CODE_64BIT)
11649 elf_section_type (sec) = SHT_X86_64_UNWIND;
11650}
11651#endif
11652
bb41ade5
AM		 11653#ifdef TE_PE
11654void
11655tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11656{
91d6fa6a 11657 expressionS exp;
bb41ade5 11658
91d6fa6a
NC		 11659 exp.X_op = O_secrel;
11660 exp.X_add_symbol = symbol;
11661 exp.X_add_number = 0;
11662 emit_expr (&exp, size);
bb41ade5
AM		 11663}
11664#endif
3b22753a
L		 11665
11666#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11667/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11668
01e1a5bc 11669bfd_vma
6d4af3c2 11670x86_64_section_letter (int letter, const char **ptr_msg)
3b22753a
L		 11671{
11672 if (flag_code == CODE_64BIT)
11673 {
11674 if (letter == 'l')
11675 return SHF_X86_64_LARGE;
11676
8f3bae45 11677 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 11678 }
3b22753a 11679 else
8f3bae45 11680 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 11681 return -1;
11682}
11683
01e1a5bc 11684bfd_vma
3b22753a
L		 11685x86_64_section_word (char *str, size_t len)
11686{
8620418b 11687 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 11688 return SHF_X86_64_LARGE;
11689
11690 return -1;
11691}
11692
11693static void
11694handle_large_common (int small ATTRIBUTE_UNUSED)
11695{
11696 if (flag_code != CODE_64BIT)
11697 {
11698 s_comm_internal (0, elf_common_parse);
11699 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11700 }
11701 else
11702 {
11703 static segT lbss_section;
11704 asection *saved_com_section_ptr = elf_com_section_ptr;
11705 asection *saved_bss_section = bss_section;
11706
11707 if (lbss_section == NULL)
11708 {
11709 flagword applicable;
11710 segT seg = now_seg;
11711 subsegT subseg = now_subseg;
11712
11713 /* The .lbss section is for local .largecomm symbols. */
11714 lbss_section = subseg_new (".lbss", 0);
11715 applicable = bfd_applicable_section_flags (stdoutput);
11716 bfd_set_section_flags (stdoutput, lbss_section,
11717 applicable & SEC_ALLOC);
11718 seg_info (lbss_section)->bss = 1;
11719
11720 subseg_set (seg, subseg);
11721 }
11722
11723 elf_com_section_ptr = &_bfd_elf_large_com_section;
11724 bss_section = lbss_section;
11725
11726 s_comm_internal (0, elf_common_parse);
11727
11728 elf_com_section_ptr = saved_com_section_ptr;
11729 bss_section = saved_bss_section;
11730 }
11731}
11732#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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