Commit | Line | Data |
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252b5132 | 1 | /* i386.c -- Assemble code for the Intel 80386 |
4c63da97 | 2 | Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000 |
47926f60 | 3 | Free Software Foundation, Inc. |
252b5132 RH |
4 | |
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to the Free | |
19 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
20 | 02111-1307, USA. */ | |
21 | ||
47926f60 KH |
22 | /* Intel 80386 machine specific gas. |
23 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
24 | Bugs & suggestions are completely welcome. This is free software. | |
25 | Please help us make it better. */ | |
252b5132 RH |
26 | |
27 | #include <ctype.h> | |
28 | ||
29 | #include "as.h" | |
30 | #include "subsegs.h" | |
31 | #include "opcode/i386.h" | |
32 | ||
252b5132 RH |
33 | #ifndef REGISTER_WARNINGS |
34 | #define REGISTER_WARNINGS 1 | |
35 | #endif | |
36 | ||
c3332e24 | 37 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 38 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
39 | #endif |
40 | ||
252b5132 RH |
41 | #ifndef SCALE1_WHEN_NO_INDEX |
42 | /* Specifying a scale factor besides 1 when there is no index is | |
43 | futile. eg. `mov (%ebx,2),%al' does exactly the same as | |
44 | `mov (%ebx),%al'. To slavishly follow what the programmer | |
45 | specified, set SCALE1_WHEN_NO_INDEX to 0. */ | |
46 | #define SCALE1_WHEN_NO_INDEX 1 | |
47 | #endif | |
48 | ||
49 | #define true 1 | |
50 | #define false 0 | |
51 | ||
52 | static unsigned int mode_from_disp_size PARAMS ((unsigned int)); | |
847f7ad4 AM |
53 | static int fits_in_signed_byte PARAMS ((offsetT)); |
54 | static int fits_in_unsigned_byte PARAMS ((offsetT)); | |
55 | static int fits_in_unsigned_word PARAMS ((offsetT)); | |
56 | static int fits_in_signed_word PARAMS ((offsetT)); | |
57 | static int smallest_imm_type PARAMS ((offsetT)); | |
58 | static offsetT offset_in_range PARAMS ((offsetT, int)); | |
252b5132 RH |
59 | static int add_prefix PARAMS ((unsigned int)); |
60 | static void set_16bit_code_flag PARAMS ((int)); | |
47926f60 | 61 | static void set_16bit_gcc_code_flag PARAMS ((int)); |
252b5132 | 62 | static void set_intel_syntax PARAMS ((int)); |
e413e4e9 | 63 | static void set_cpu_arch PARAMS ((int)); |
252b5132 RH |
64 | |
65 | #ifdef BFD_ASSEMBLER | |
66 | static bfd_reloc_code_real_type reloc | |
67 | PARAMS ((int, int, bfd_reloc_code_real_type)); | |
68 | #endif | |
69 | ||
70 | /* 'md_assemble ()' gathers together information and puts it into a | |
47926f60 | 71 | i386_insn. */ |
252b5132 | 72 | |
520dc8e8 AM |
73 | union i386_op |
74 | { | |
75 | expressionS *disps; | |
76 | expressionS *imms; | |
77 | const reg_entry *regs; | |
78 | }; | |
79 | ||
252b5132 RH |
80 | struct _i386_insn |
81 | { | |
47926f60 | 82 | /* TM holds the template for the insn were currently assembling. */ |
252b5132 RH |
83 | template tm; |
84 | ||
85 | /* SUFFIX holds the instruction mnemonic suffix if given. | |
86 | (e.g. 'l' for 'movl') */ | |
87 | char suffix; | |
88 | ||
47926f60 | 89 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
90 | unsigned int operands; |
91 | ||
92 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
93 | of given register, displacement, memory operands and immediate | |
47926f60 | 94 | operands. */ |
252b5132 RH |
95 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
96 | ||
97 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 98 | use OP[i] for the corresponding operand. */ |
252b5132 RH |
99 | unsigned int types[MAX_OPERANDS]; |
100 | ||
520dc8e8 AM |
101 | /* Displacement expression, immediate expression, or register for each |
102 | operand. */ | |
103 | union i386_op op[MAX_OPERANDS]; | |
252b5132 RH |
104 | |
105 | /* Relocation type for operand */ | |
106 | #ifdef BFD_ASSEMBLER | |
107 | enum bfd_reloc_code_real disp_reloc[MAX_OPERANDS]; | |
108 | #else | |
109 | int disp_reloc[MAX_OPERANDS]; | |
110 | #endif | |
111 | ||
252b5132 RH |
112 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
113 | the base index byte below. */ | |
114 | const reg_entry *base_reg; | |
115 | const reg_entry *index_reg; | |
116 | unsigned int log2_scale_factor; | |
117 | ||
118 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 119 | explicit segment overrides are given. */ |
ce8a8b2f | 120 | const seg_entry *seg[2]; |
252b5132 RH |
121 | |
122 | /* PREFIX holds all the given prefix opcodes (usually null). | |
123 | PREFIXES is the number of prefix opcodes. */ | |
124 | unsigned int prefixes; | |
125 | unsigned char prefix[MAX_PREFIXES]; | |
126 | ||
127 | /* RM and SIB are the modrm byte and the sib byte where the | |
128 | addressing modes of this insn are encoded. */ | |
129 | ||
130 | modrm_byte rm; | |
131 | sib_byte sib; | |
132 | }; | |
133 | ||
134 | typedef struct _i386_insn i386_insn; | |
135 | ||
136 | /* List of chars besides those in app.c:symbol_chars that can start an | |
137 | operand. Used to prevent the scrubber eating vital white-space. */ | |
138 | #ifdef LEX_AT | |
139 | const char extra_symbol_chars[] = "*%-(@"; | |
140 | #else | |
141 | const char extra_symbol_chars[] = "*%-("; | |
142 | #endif | |
143 | ||
144 | /* This array holds the chars that always start a comment. If the | |
ce8a8b2f | 145 | pre-processor is disabled, these aren't very useful. */ |
60bcf0fa | 146 | #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD)) |
252b5132 RH |
147 | /* Putting '/' here makes it impossible to use the divide operator. |
148 | However, we need it for compatibility with SVR4 systems. */ | |
149 | const char comment_chars[] = "#/"; | |
150 | #define PREFIX_SEPARATOR '\\' | |
151 | #else | |
152 | const char comment_chars[] = "#"; | |
153 | #define PREFIX_SEPARATOR '/' | |
154 | #endif | |
155 | ||
156 | /* This array holds the chars that only start a comment at the beginning of | |
157 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
158 | .line and .file directives will appear in the pre-processed output. |
159 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 160 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
161 | #NO_APP at the beginning of its output. |
162 | Also note that comments started like this one will always work if | |
252b5132 | 163 | '/' isn't otherwise defined. */ |
60bcf0fa | 164 | #if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD)) |
252b5132 RH |
165 | const char line_comment_chars[] = ""; |
166 | #else | |
167 | const char line_comment_chars[] = "/"; | |
168 | #endif | |
169 | ||
63a0b638 | 170 | const char line_separator_chars[] = ";"; |
252b5132 | 171 | |
ce8a8b2f AM |
172 | /* Chars that can be used to separate mant from exp in floating point |
173 | nums. */ | |
252b5132 RH |
174 | const char EXP_CHARS[] = "eE"; |
175 | ||
ce8a8b2f AM |
176 | /* Chars that mean this number is a floating point constant |
177 | As in 0f12.456 | |
178 | or 0d1.2345e12. */ | |
252b5132 RH |
179 | const char FLT_CHARS[] = "fFdDxX"; |
180 | ||
ce8a8b2f | 181 | /* Tables for lexical analysis. */ |
252b5132 RH |
182 | static char mnemonic_chars[256]; |
183 | static char register_chars[256]; | |
184 | static char operand_chars[256]; | |
185 | static char identifier_chars[256]; | |
186 | static char digit_chars[256]; | |
187 | ||
ce8a8b2f | 188 | /* Lexical macros. */ |
252b5132 RH |
189 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
190 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
191 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
192 | #define is_space_char(x) ((x) == ' ') | |
193 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
194 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
195 | ||
ce8a8b2f | 196 | /* All non-digit non-letter charcters that may occur in an operand. */ |
252b5132 RH |
197 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
198 | ||
199 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
200 | effect this we maintain a stack of saved characters that we've smashed | |
201 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 202 | assembler instruction). */ |
252b5132 | 203 | static char save_stack[32]; |
ce8a8b2f | 204 | static char *save_stack_p; |
252b5132 RH |
205 | #define END_STRING_AND_SAVE(s) \ |
206 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
207 | #define RESTORE_END_STRING(s) \ | |
208 | do { *(s) = *--save_stack_p; } while (0) | |
209 | ||
47926f60 | 210 | /* The instruction we're assembling. */ |
252b5132 RH |
211 | static i386_insn i; |
212 | ||
213 | /* Possible templates for current insn. */ | |
214 | static const templates *current_templates; | |
215 | ||
47926f60 | 216 | /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */ |
252b5132 RH |
217 | static expressionS disp_expressions[2], im_expressions[2]; |
218 | ||
47926f60 KH |
219 | /* Current operand we are working on. */ |
220 | static int this_operand; | |
252b5132 | 221 | |
47926f60 KH |
222 | /* 1 if we're writing 16-bit code, |
223 | 0 if 32-bit. */ | |
224 | static int flag_16bit_code; | |
252b5132 | 225 | |
47926f60 KH |
226 | /* 1 for intel syntax, |
227 | 0 if att syntax. */ | |
228 | static int intel_syntax = 0; | |
252b5132 | 229 | |
47926f60 KH |
230 | /* 1 if register prefix % not required. */ |
231 | static int allow_naked_reg = 0; | |
252b5132 | 232 | |
47926f60 KH |
233 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
234 | leave, push, and pop instructions so that gcc has the same stack | |
235 | frame as in 32 bit mode. */ | |
236 | static char stackop_size = '\0'; | |
eecb386c | 237 | |
47926f60 KH |
238 | /* Non-zero to quieten some warnings. */ |
239 | static int quiet_warnings = 0; | |
a38cf1db | 240 | |
47926f60 KH |
241 | /* CPU name. */ |
242 | static const char *cpu_arch_name = NULL; | |
a38cf1db | 243 | |
47926f60 KH |
244 | /* CPU feature flags. */ |
245 | static unsigned int cpu_arch_flags = 0; | |
a38cf1db | 246 | |
252b5132 RH |
247 | /* Interface to relax_segment. |
248 | There are 2 relax states for 386 jump insns: one for conditional & | |
a217f122 AM |
249 | one for unconditional jumps. This is because these two types of |
250 | jumps add different sizes to frags when we're figuring out what | |
252b5132 RH |
251 | sort of jump to choose to reach a given label. */ |
252 | ||
47926f60 | 253 | /* Types. */ |
ce8a8b2f AM |
254 | #define COND_JUMP 1 |
255 | #define UNCOND_JUMP 2 | |
47926f60 | 256 | /* Sizes. */ |
252b5132 RH |
257 | #define CODE16 1 |
258 | #define SMALL 0 | |
259 | #define SMALL16 (SMALL|CODE16) | |
260 | #define BIG 2 | |
261 | #define BIG16 (BIG|CODE16) | |
262 | ||
263 | #ifndef INLINE | |
264 | #ifdef __GNUC__ | |
265 | #define INLINE __inline__ | |
266 | #else | |
267 | #define INLINE | |
268 | #endif | |
269 | #endif | |
270 | ||
271 | #define ENCODE_RELAX_STATE(type,size) \ | |
272 | ((relax_substateT)((type<<2) | (size))) | |
273 | #define SIZE_FROM_RELAX_STATE(s) \ | |
274 | ( (((s) & 0x3) == BIG ? 4 : (((s) & 0x3) == BIG16 ? 2 : 1)) ) | |
275 | ||
276 | /* This table is used by relax_frag to promote short jumps to long | |
277 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
278 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
279 | don't allow a short jump in a 32 bit code segment to be promoted to | |
280 | a 16 bit offset jump because it's slower (requires data size | |
281 | prefix), and doesn't work, unless the destination is in the bottom | |
282 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
283 | ||
284 | const relax_typeS md_relax_table[] = | |
285 | { | |
24eab124 AM |
286 | /* The fields are: |
287 | 1) most positive reach of this state, | |
288 | 2) most negative reach of this state, | |
289 | 3) how many bytes this mode will add to the size of the current frag | |
ce8a8b2f | 290 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 RH |
291 | {1, 1, 0, 0}, |
292 | {1, 1, 0, 0}, | |
293 | {1, 1, 0, 0}, | |
294 | {1, 1, 0, 0}, | |
295 | ||
296 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
297 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
298 | /* dword conditionals adds 4 bytes to frag: | |
299 | 1 extra opcode byte, 3 extra displacement bytes. */ | |
300 | {0, 0, 4, 0}, | |
301 | /* word conditionals add 2 bytes to frag: | |
302 | 1 extra opcode byte, 1 extra displacement byte. */ | |
303 | {0, 0, 2, 0}, | |
304 | ||
305 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, | |
306 | {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
307 | /* dword jmp adds 3 bytes to frag: | |
308 | 0 extra opcode bytes, 3 extra displacement bytes. */ | |
309 | {0, 0, 3, 0}, | |
310 | /* word jmp adds 1 byte to frag: | |
311 | 0 extra opcode bytes, 1 extra displacement byte. */ | |
312 | {0, 0, 1, 0} | |
313 | ||
314 | }; | |
315 | ||
e413e4e9 AM |
316 | static const arch_entry cpu_arch[] = { |
317 | {"i8086", Cpu086 }, | |
318 | {"i186", Cpu086|Cpu186 }, | |
319 | {"i286", Cpu086|Cpu186|Cpu286 }, | |
320 | {"i386", Cpu086|Cpu186|Cpu286|Cpu386 }, | |
321 | {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 }, | |
322 | {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX }, | |
323 | {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE }, | |
324 | {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX }, | |
325 | {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE }, | |
326 | {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX|Cpu3dnow }, | |
327 | {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|Cpu3dnow }, | |
328 | {NULL, 0 } | |
329 | }; | |
330 | ||
252b5132 RH |
331 | void |
332 | i386_align_code (fragP, count) | |
333 | fragS *fragP; | |
334 | int count; | |
335 | { | |
ce8a8b2f AM |
336 | /* Various efficient no-op patterns for aligning code labels. |
337 | Note: Don't try to assemble the instructions in the comments. | |
338 | 0L and 0w are not legal. */ | |
252b5132 RH |
339 | static const char f32_1[] = |
340 | {0x90}; /* nop */ | |
341 | static const char f32_2[] = | |
342 | {0x89,0xf6}; /* movl %esi,%esi */ | |
343 | static const char f32_3[] = | |
344 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
345 | static const char f32_4[] = | |
346 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
347 | static const char f32_5[] = | |
348 | {0x90, /* nop */ | |
349 | 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
350 | static const char f32_6[] = | |
351 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
352 | static const char f32_7[] = | |
353 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
354 | static const char f32_8[] = | |
355 | {0x90, /* nop */ | |
356 | 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
357 | static const char f32_9[] = | |
358 | {0x89,0xf6, /* movl %esi,%esi */ | |
359 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
360 | static const char f32_10[] = | |
361 | {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ | |
362 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
363 | static const char f32_11[] = | |
364 | {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ | |
365 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
366 | static const char f32_12[] = | |
367 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
368 | 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ | |
369 | static const char f32_13[] = | |
370 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
371 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
372 | static const char f32_14[] = | |
373 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ | |
374 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
375 | static const char f32_15[] = | |
376 | {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */ | |
377 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; | |
c3332e24 AM |
378 | static const char f16_3[] = |
379 | {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */ | |
252b5132 RH |
380 | static const char f16_4[] = |
381 | {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
382 | static const char f16_5[] = | |
383 | {0x90, /* nop */ | |
384 | 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
385 | static const char f16_6[] = | |
386 | {0x89,0xf6, /* mov %si,%si */ | |
387 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
388 | static const char f16_7[] = | |
389 | {0x8d,0x74,0x00, /* lea 0(%si),%si */ | |
390 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
391 | static const char f16_8[] = | |
392 | {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ | |
393 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
394 | static const char *const f32_patt[] = { | |
395 | f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, | |
396 | f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15 | |
397 | }; | |
398 | static const char *const f16_patt[] = { | |
c3332e24 | 399 | f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8, |
252b5132 RH |
400 | f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15 |
401 | }; | |
402 | ||
403 | if (count > 0 && count <= 15) | |
404 | { | |
405 | if (flag_16bit_code) | |
406 | { | |
47926f60 KH |
407 | memcpy (fragP->fr_literal + fragP->fr_fix, |
408 | f16_patt[count - 1], count); | |
409 | if (count > 8) | |
410 | /* Adjust jump offset. */ | |
252b5132 RH |
411 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; |
412 | } | |
413 | else | |
47926f60 KH |
414 | memcpy (fragP->fr_literal + fragP->fr_fix, |
415 | f32_patt[count - 1], count); | |
252b5132 RH |
416 | fragP->fr_var = count; |
417 | } | |
418 | } | |
419 | ||
420 | static char *output_invalid PARAMS ((int c)); | |
421 | static int i386_operand PARAMS ((char *operand_string)); | |
422 | static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float)); | |
423 | static const reg_entry *parse_register PARAMS ((char *reg_string, | |
424 | char **end_op)); | |
425 | ||
426 | #ifndef I386COFF | |
427 | static void s_bss PARAMS ((int)); | |
428 | #endif | |
429 | ||
ce8a8b2f | 430 | symbolS *GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
252b5132 RH |
431 | |
432 | static INLINE unsigned int | |
433 | mode_from_disp_size (t) | |
434 | unsigned int t; | |
435 | { | |
47926f60 | 436 | return (t & Disp8) ? 1 : (t & (Disp16 | Disp32)) ? 2 : 0; |
252b5132 RH |
437 | } |
438 | ||
439 | static INLINE int | |
440 | fits_in_signed_byte (num) | |
847f7ad4 | 441 | offsetT num; |
252b5132 RH |
442 | { |
443 | return (num >= -128) && (num <= 127); | |
47926f60 | 444 | } |
252b5132 RH |
445 | |
446 | static INLINE int | |
447 | fits_in_unsigned_byte (num) | |
847f7ad4 | 448 | offsetT num; |
252b5132 RH |
449 | { |
450 | return (num & 0xff) == num; | |
47926f60 | 451 | } |
252b5132 RH |
452 | |
453 | static INLINE int | |
454 | fits_in_unsigned_word (num) | |
847f7ad4 | 455 | offsetT num; |
252b5132 RH |
456 | { |
457 | return (num & 0xffff) == num; | |
47926f60 | 458 | } |
252b5132 RH |
459 | |
460 | static INLINE int | |
461 | fits_in_signed_word (num) | |
847f7ad4 | 462 | offsetT num; |
252b5132 RH |
463 | { |
464 | return (-32768 <= num) && (num <= 32767); | |
47926f60 | 465 | } |
252b5132 RH |
466 | |
467 | static int | |
468 | smallest_imm_type (num) | |
847f7ad4 | 469 | offsetT num; |
252b5132 | 470 | { |
e413e4e9 | 471 | if (cpu_arch_flags != 0 |
47926f60 | 472 | && cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486)) |
e413e4e9 AM |
473 | { |
474 | /* This code is disabled on the 486 because all the Imm1 forms | |
475 | in the opcode table are slower on the i486. They're the | |
476 | versions with the implicitly specified single-position | |
477 | displacement, which has another syntax if you really want to | |
478 | use that form. */ | |
479 | if (num == 1) | |
480 | return Imm1 | Imm8 | Imm8S | Imm16 | Imm32; | |
481 | } | |
252b5132 RH |
482 | return (fits_in_signed_byte (num) |
483 | ? (Imm8S | Imm8 | Imm16 | Imm32) | |
484 | : fits_in_unsigned_byte (num) | |
485 | ? (Imm8 | Imm16 | Imm32) | |
486 | : (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
487 | ? (Imm16 | Imm32) | |
488 | : (Imm32)); | |
47926f60 | 489 | } |
252b5132 | 490 | |
847f7ad4 AM |
491 | static offsetT |
492 | offset_in_range (val, size) | |
493 | offsetT val; | |
494 | int size; | |
495 | { | |
508866be | 496 | addressT mask; |
ba2adb93 | 497 | |
847f7ad4 AM |
498 | switch (size) |
499 | { | |
508866be L |
500 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
501 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 502 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
47926f60 | 503 | default: abort (); |
847f7ad4 AM |
504 | } |
505 | ||
ba2adb93 | 506 | /* If BFD64, sign extend val. */ |
47926f60 | 507 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) |
508866be | 508 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); |
ba2adb93 | 509 | |
47926f60 | 510 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
847f7ad4 AM |
511 | { |
512 | char buf1[40], buf2[40]; | |
513 | ||
514 | sprint_value (buf1, val); | |
515 | sprint_value (buf2, val & mask); | |
516 | as_warn (_("%s shortened to %s"), buf1, buf2); | |
517 | } | |
518 | return val & mask; | |
519 | } | |
520 | ||
252b5132 RH |
521 | /* Returns 0 if attempting to add a prefix where one from the same |
522 | class already exists, 1 if non rep/repne added, 2 if rep/repne | |
523 | added. */ | |
524 | static int | |
525 | add_prefix (prefix) | |
526 | unsigned int prefix; | |
527 | { | |
528 | int ret = 1; | |
529 | int q; | |
530 | ||
531 | switch (prefix) | |
532 | { | |
533 | default: | |
534 | abort (); | |
535 | ||
536 | case CS_PREFIX_OPCODE: | |
537 | case DS_PREFIX_OPCODE: | |
538 | case ES_PREFIX_OPCODE: | |
539 | case FS_PREFIX_OPCODE: | |
540 | case GS_PREFIX_OPCODE: | |
541 | case SS_PREFIX_OPCODE: | |
542 | q = SEG_PREFIX; | |
543 | break; | |
544 | ||
545 | case REPNE_PREFIX_OPCODE: | |
546 | case REPE_PREFIX_OPCODE: | |
547 | ret = 2; | |
548 | /* fall thru */ | |
549 | case LOCK_PREFIX_OPCODE: | |
550 | q = LOCKREP_PREFIX; | |
551 | break; | |
552 | ||
553 | case FWAIT_OPCODE: | |
554 | q = WAIT_PREFIX; | |
555 | break; | |
556 | ||
557 | case ADDR_PREFIX_OPCODE: | |
558 | q = ADDR_PREFIX; | |
559 | break; | |
560 | ||
561 | case DATA_PREFIX_OPCODE: | |
562 | q = DATA_PREFIX; | |
563 | break; | |
564 | } | |
565 | ||
566 | if (i.prefix[q]) | |
567 | { | |
568 | as_bad (_("same type of prefix used twice")); | |
569 | return 0; | |
570 | } | |
571 | ||
572 | i.prefixes += 1; | |
573 | i.prefix[q] = prefix; | |
574 | return ret; | |
575 | } | |
576 | ||
577 | static void | |
578 | set_16bit_code_flag (new_16bit_code_flag) | |
eecb386c AM |
579 | int new_16bit_code_flag; |
580 | { | |
581 | flag_16bit_code = new_16bit_code_flag; | |
582 | stackop_size = '\0'; | |
583 | } | |
584 | ||
585 | static void | |
586 | set_16bit_gcc_code_flag (new_16bit_code_flag) | |
587 | int new_16bit_code_flag; | |
252b5132 RH |
588 | { |
589 | flag_16bit_code = new_16bit_code_flag; | |
eecb386c | 590 | stackop_size = new_16bit_code_flag ? 'l' : '\0'; |
252b5132 RH |
591 | } |
592 | ||
593 | static void | |
594 | set_intel_syntax (syntax_flag) | |
eecb386c | 595 | int syntax_flag; |
252b5132 RH |
596 | { |
597 | /* Find out if register prefixing is specified. */ | |
598 | int ask_naked_reg = 0; | |
599 | ||
600 | SKIP_WHITESPACE (); | |
601 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
602 | { | |
603 | char *string = input_line_pointer; | |
604 | int e = get_symbol_end (); | |
605 | ||
47926f60 | 606 | if (strcmp (string, "prefix") == 0) |
252b5132 | 607 | ask_naked_reg = 1; |
47926f60 | 608 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
609 | ask_naked_reg = -1; |
610 | else | |
d0b47220 | 611 | as_bad (_("bad argument to syntax directive.")); |
252b5132 RH |
612 | *input_line_pointer = e; |
613 | } | |
614 | demand_empty_rest_of_line (); | |
c3332e24 | 615 | |
252b5132 RH |
616 | intel_syntax = syntax_flag; |
617 | ||
618 | if (ask_naked_reg == 0) | |
619 | { | |
620 | #ifdef BFD_ASSEMBLER | |
621 | allow_naked_reg = (intel_syntax | |
24eab124 | 622 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); |
252b5132 | 623 | #else |
47926f60 KH |
624 | /* Conservative default. */ |
625 | allow_naked_reg = 0; | |
252b5132 RH |
626 | #endif |
627 | } | |
628 | else | |
629 | allow_naked_reg = (ask_naked_reg < 0); | |
630 | } | |
631 | ||
e413e4e9 AM |
632 | static void |
633 | set_cpu_arch (dummy) | |
47926f60 | 634 | int dummy ATTRIBUTE_UNUSED; |
e413e4e9 | 635 | { |
47926f60 | 636 | SKIP_WHITESPACE (); |
e413e4e9 AM |
637 | |
638 | if (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
639 | { | |
640 | char *string = input_line_pointer; | |
641 | int e = get_symbol_end (); | |
642 | int i; | |
643 | ||
644 | for (i = 0; cpu_arch[i].name; i++) | |
645 | { | |
646 | if (strcmp (string, cpu_arch[i].name) == 0) | |
647 | { | |
648 | cpu_arch_name = cpu_arch[i].name; | |
649 | cpu_arch_flags = cpu_arch[i].flags; | |
650 | break; | |
651 | } | |
652 | } | |
653 | if (!cpu_arch[i].name) | |
654 | as_bad (_("no such architecture: `%s'"), string); | |
655 | ||
656 | *input_line_pointer = e; | |
657 | } | |
658 | else | |
659 | as_bad (_("missing cpu architecture")); | |
660 | ||
661 | demand_empty_rest_of_line (); | |
662 | } | |
663 | ||
252b5132 RH |
664 | const pseudo_typeS md_pseudo_table[] = |
665 | { | |
252b5132 RH |
666 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) |
667 | {"align", s_align_bytes, 0}, | |
668 | #else | |
669 | {"align", s_align_ptwo, 0}, | |
e413e4e9 AM |
670 | #endif |
671 | {"arch", set_cpu_arch, 0}, | |
672 | #ifndef I386COFF | |
673 | {"bss", s_bss, 0}, | |
252b5132 RH |
674 | #endif |
675 | {"ffloat", float_cons, 'f'}, | |
676 | {"dfloat", float_cons, 'd'}, | |
677 | {"tfloat", float_cons, 'x'}, | |
678 | {"value", cons, 2}, | |
679 | {"noopt", s_ignore, 0}, | |
680 | {"optim", s_ignore, 0}, | |
eecb386c | 681 | {"code16gcc", set_16bit_gcc_code_flag, 1}, |
252b5132 RH |
682 | {"code16", set_16bit_code_flag, 1}, |
683 | {"code32", set_16bit_code_flag, 0}, | |
684 | {"intel_syntax", set_intel_syntax, 1}, | |
685 | {"att_syntax", set_intel_syntax, 0}, | |
686 | {0, 0, 0} | |
687 | }; | |
688 | ||
47926f60 | 689 | /* For interface with expression (). */ |
252b5132 RH |
690 | extern char *input_line_pointer; |
691 | ||
47926f60 | 692 | /* Hash table for instruction mnemonic lookup. */ |
252b5132 | 693 | static struct hash_control *op_hash; |
47926f60 KH |
694 | |
695 | /* Hash table for register lookup. */ | |
252b5132 RH |
696 | static struct hash_control *reg_hash; |
697 | \f | |
252b5132 RH |
698 | void |
699 | md_begin () | |
700 | { | |
701 | const char *hash_err; | |
702 | ||
47926f60 | 703 | /* Initialize op_hash hash table. */ |
252b5132 RH |
704 | op_hash = hash_new (); |
705 | ||
706 | { | |
707 | register const template *optab; | |
708 | register templates *core_optab; | |
709 | ||
47926f60 KH |
710 | /* Setup for loop. */ |
711 | optab = i386_optab; | |
252b5132 RH |
712 | core_optab = (templates *) xmalloc (sizeof (templates)); |
713 | core_optab->start = optab; | |
714 | ||
715 | while (1) | |
716 | { | |
717 | ++optab; | |
718 | if (optab->name == NULL | |
719 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
720 | { | |
721 | /* different name --> ship out current template list; | |
47926f60 | 722 | add to hash table; & begin anew. */ |
252b5132 RH |
723 | core_optab->end = optab; |
724 | hash_err = hash_insert (op_hash, | |
725 | (optab - 1)->name, | |
726 | (PTR) core_optab); | |
727 | if (hash_err) | |
728 | { | |
729 | hash_error: | |
730 | as_fatal (_("Internal Error: Can't hash %s: %s"), | |
731 | (optab - 1)->name, | |
732 | hash_err); | |
733 | } | |
734 | if (optab->name == NULL) | |
735 | break; | |
736 | core_optab = (templates *) xmalloc (sizeof (templates)); | |
737 | core_optab->start = optab; | |
738 | } | |
739 | } | |
740 | } | |
741 | ||
47926f60 | 742 | /* Initialize reg_hash hash table. */ |
252b5132 RH |
743 | reg_hash = hash_new (); |
744 | { | |
745 | register const reg_entry *regtab; | |
746 | ||
747 | for (regtab = i386_regtab; | |
748 | regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]); | |
749 | regtab++) | |
750 | { | |
751 | hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab); | |
752 | if (hash_err) | |
753 | goto hash_error; | |
754 | } | |
755 | } | |
756 | ||
47926f60 | 757 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 RH |
758 | { |
759 | register int c; | |
760 | register char *p; | |
761 | ||
762 | for (c = 0; c < 256; c++) | |
763 | { | |
764 | if (isdigit (c)) | |
765 | { | |
766 | digit_chars[c] = c; | |
767 | mnemonic_chars[c] = c; | |
768 | register_chars[c] = c; | |
769 | operand_chars[c] = c; | |
770 | } | |
771 | else if (islower (c)) | |
772 | { | |
773 | mnemonic_chars[c] = c; | |
774 | register_chars[c] = c; | |
775 | operand_chars[c] = c; | |
776 | } | |
777 | else if (isupper (c)) | |
778 | { | |
779 | mnemonic_chars[c] = tolower (c); | |
780 | register_chars[c] = mnemonic_chars[c]; | |
781 | operand_chars[c] = c; | |
782 | } | |
783 | ||
784 | if (isalpha (c) || isdigit (c)) | |
785 | identifier_chars[c] = c; | |
786 | else if (c >= 128) | |
787 | { | |
788 | identifier_chars[c] = c; | |
789 | operand_chars[c] = c; | |
790 | } | |
791 | } | |
792 | ||
793 | #ifdef LEX_AT | |
794 | identifier_chars['@'] = '@'; | |
795 | #endif | |
252b5132 RH |
796 | digit_chars['-'] = '-'; |
797 | identifier_chars['_'] = '_'; | |
798 | identifier_chars['.'] = '.'; | |
799 | ||
800 | for (p = operand_special_chars; *p != '\0'; p++) | |
801 | operand_chars[(unsigned char) *p] = *p; | |
802 | } | |
803 | ||
804 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
805 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
806 | { | |
807 | record_alignment (text_section, 2); | |
808 | record_alignment (data_section, 2); | |
809 | record_alignment (bss_section, 2); | |
810 | } | |
811 | #endif | |
812 | } | |
813 | ||
814 | void | |
815 | i386_print_statistics (file) | |
816 | FILE *file; | |
817 | { | |
818 | hash_print_statistics (file, "i386 opcode", op_hash); | |
819 | hash_print_statistics (file, "i386 register", reg_hash); | |
820 | } | |
821 | \f | |
252b5132 RH |
822 | #ifdef DEBUG386 |
823 | ||
ce8a8b2f | 824 | /* Debugging routines for md_assemble. */ |
252b5132 RH |
825 | static void pi PARAMS ((char *, i386_insn *)); |
826 | static void pte PARAMS ((template *)); | |
827 | static void pt PARAMS ((unsigned int)); | |
828 | static void pe PARAMS ((expressionS *)); | |
829 | static void ps PARAMS ((symbolS *)); | |
830 | ||
831 | static void | |
832 | pi (line, x) | |
833 | char *line; | |
834 | i386_insn *x; | |
835 | { | |
836 | register template *p; | |
837 | int i; | |
838 | ||
839 | fprintf (stdout, "%s: template ", line); | |
840 | pte (&x->tm); | |
841 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x", | |
842 | x->rm.mode, x->rm.reg, x->rm.regmem); | |
843 | fprintf (stdout, " base %x index %x scale %x\n", | |
844 | x->bi.base, x->bi.index, x->bi.scale); | |
845 | for (i = 0; i < x->operands; i++) | |
846 | { | |
847 | fprintf (stdout, " #%d: ", i + 1); | |
848 | pt (x->types[i]); | |
849 | fprintf (stdout, "\n"); | |
850 | if (x->types[i] | |
3f4438ab | 851 | & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM)) |
520dc8e8 | 852 | fprintf (stdout, "%s\n", x->op[i].regs->reg_name); |
252b5132 | 853 | if (x->types[i] & Imm) |
520dc8e8 | 854 | pe (x->op[i].imms); |
252b5132 | 855 | if (x->types[i] & Disp) |
520dc8e8 | 856 | pe (x->op[i].disps); |
252b5132 RH |
857 | } |
858 | } | |
859 | ||
860 | static void | |
861 | pte (t) | |
862 | template *t; | |
863 | { | |
864 | int i; | |
865 | fprintf (stdout, " %d operands ", t->operands); | |
47926f60 | 866 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
867 | if (t->extension_opcode != None) |
868 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
869 | if (t->opcode_modifier & D) | |
870 | fprintf (stdout, "D"); | |
871 | if (t->opcode_modifier & W) | |
872 | fprintf (stdout, "W"); | |
873 | fprintf (stdout, "\n"); | |
874 | for (i = 0; i < t->operands; i++) | |
875 | { | |
876 | fprintf (stdout, " #%d type ", i + 1); | |
877 | pt (t->operand_types[i]); | |
878 | fprintf (stdout, "\n"); | |
879 | } | |
880 | } | |
881 | ||
882 | static void | |
883 | pe (e) | |
884 | expressionS *e; | |
885 | { | |
24eab124 | 886 | fprintf (stdout, " operation %d\n", e->X_op); |
b77ad1d4 AM |
887 | fprintf (stdout, " add_number %ld (%lx)\n", |
888 | (long) e->X_add_number, (long) e->X_add_number); | |
252b5132 RH |
889 | if (e->X_add_symbol) |
890 | { | |
891 | fprintf (stdout, " add_symbol "); | |
892 | ps (e->X_add_symbol); | |
893 | fprintf (stdout, "\n"); | |
894 | } | |
895 | if (e->X_op_symbol) | |
896 | { | |
897 | fprintf (stdout, " op_symbol "); | |
898 | ps (e->X_op_symbol); | |
899 | fprintf (stdout, "\n"); | |
900 | } | |
901 | } | |
902 | ||
903 | static void | |
904 | ps (s) | |
905 | symbolS *s; | |
906 | { | |
907 | fprintf (stdout, "%s type %s%s", | |
908 | S_GET_NAME (s), | |
909 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
910 | segment_name (S_GET_SEGMENT (s))); | |
911 | } | |
912 | ||
913 | struct type_name | |
914 | { | |
915 | unsigned int mask; | |
916 | char *tname; | |
917 | } | |
918 | ||
919 | type_names[] = | |
920 | { | |
921 | { Reg8, "r8" }, | |
922 | { Reg16, "r16" }, | |
923 | { Reg32, "r32" }, | |
924 | { Imm8, "i8" }, | |
925 | { Imm8S, "i8s" }, | |
926 | { Imm16, "i16" }, | |
927 | { Imm32, "i32" }, | |
928 | { Imm1, "i1" }, | |
929 | { BaseIndex, "BaseIndex" }, | |
930 | { Disp8, "d8" }, | |
931 | { Disp16, "d16" }, | |
932 | { Disp32, "d32" }, | |
933 | { InOutPortReg, "InOutPortReg" }, | |
934 | { ShiftCount, "ShiftCount" }, | |
935 | { Control, "control reg" }, | |
936 | { Test, "test reg" }, | |
937 | { Debug, "debug reg" }, | |
938 | { FloatReg, "FReg" }, | |
939 | { FloatAcc, "FAcc" }, | |
940 | { SReg2, "SReg2" }, | |
941 | { SReg3, "SReg3" }, | |
942 | { Acc, "Acc" }, | |
943 | { JumpAbsolute, "Jump Absolute" }, | |
944 | { RegMMX, "rMMX" }, | |
3f4438ab | 945 | { RegXMM, "rXMM" }, |
252b5132 RH |
946 | { EsSeg, "es" }, |
947 | { 0, "" } | |
948 | }; | |
949 | ||
950 | static void | |
951 | pt (t) | |
952 | unsigned int t; | |
953 | { | |
954 | register struct type_name *ty; | |
955 | ||
956 | if (t == Unknown) | |
957 | { | |
958 | fprintf (stdout, _("Unknown")); | |
959 | } | |
960 | else | |
961 | { | |
962 | for (ty = type_names; ty->mask; ty++) | |
963 | if (t & ty->mask) | |
964 | fprintf (stdout, "%s, ", ty->tname); | |
965 | } | |
966 | fflush (stdout); | |
967 | } | |
968 | ||
969 | #endif /* DEBUG386 */ | |
970 | \f | |
971 | int | |
972 | tc_i386_force_relocation (fixp) | |
973 | struct fix *fixp; | |
974 | { | |
975 | #ifdef BFD_ASSEMBLER | |
976 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
977 | || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
978 | return 1; | |
979 | return 0; | |
980 | #else | |
ce8a8b2f | 981 | /* For COFF. */ |
f6af82bd | 982 | return fixp->fx_r_type == 7; |
252b5132 RH |
983 | #endif |
984 | } | |
985 | ||
986 | #ifdef BFD_ASSEMBLER | |
987 | static bfd_reloc_code_real_type reloc | |
988 | PARAMS ((int, int, bfd_reloc_code_real_type)); | |
989 | ||
990 | static bfd_reloc_code_real_type | |
991 | reloc (size, pcrel, other) | |
992 | int size; | |
993 | int pcrel; | |
994 | bfd_reloc_code_real_type other; | |
995 | { | |
47926f60 KH |
996 | if (other != NO_RELOC) |
997 | return other; | |
252b5132 RH |
998 | |
999 | if (pcrel) | |
1000 | { | |
1001 | switch (size) | |
1002 | { | |
1003 | case 1: return BFD_RELOC_8_PCREL; | |
1004 | case 2: return BFD_RELOC_16_PCREL; | |
1005 | case 4: return BFD_RELOC_32_PCREL; | |
1006 | } | |
d0b47220 | 1007 | as_bad (_("can not do %d byte pc-relative relocation"), size); |
252b5132 RH |
1008 | } |
1009 | else | |
1010 | { | |
1011 | switch (size) | |
1012 | { | |
1013 | case 1: return BFD_RELOC_8; | |
1014 | case 2: return BFD_RELOC_16; | |
1015 | case 4: return BFD_RELOC_32; | |
1016 | } | |
d0b47220 | 1017 | as_bad (_("can not do %d byte relocation"), size); |
252b5132 RH |
1018 | } |
1019 | ||
1020 | return BFD_RELOC_NONE; | |
1021 | } | |
1022 | ||
47926f60 KH |
1023 | /* Here we decide which fixups can be adjusted to make them relative to |
1024 | the beginning of the section instead of the symbol. Basically we need | |
1025 | to make sure that the dynamic relocations are done correctly, so in | |
1026 | some cases we force the original symbol to be used. */ | |
1027 | ||
252b5132 | 1028 | int |
c0c949c7 | 1029 | tc_i386_fix_adjustable (fixP) |
47926f60 | 1030 | fixS *fixP; |
252b5132 | 1031 | { |
6d249963 | 1032 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
79d292aa ILT |
1033 | /* Prevent all adjustments to global symbols, or else dynamic |
1034 | linking will not work correctly. */ | |
b98ef147 AM |
1035 | if (S_IS_EXTERNAL (fixP->fx_addsy) |
1036 | || S_IS_WEAK (fixP->fx_addsy)) | |
252b5132 RH |
1037 | return 0; |
1038 | #endif | |
ce8a8b2f | 1039 | /* adjust_reloc_syms doesn't know about the GOT. */ |
252b5132 RH |
1040 | if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF |
1041 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 | |
1042 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 | |
1043 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
1044 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
1045 | return 0; | |
1046 | return 1; | |
1047 | } | |
1048 | #else | |
1049 | #define reloc(SIZE,PCREL,OTHER) 0 | |
1050 | #define BFD_RELOC_16 0 | |
1051 | #define BFD_RELOC_32 0 | |
1052 | #define BFD_RELOC_16_PCREL 0 | |
1053 | #define BFD_RELOC_32_PCREL 0 | |
1054 | #define BFD_RELOC_386_PLT32 0 | |
1055 | #define BFD_RELOC_386_GOT32 0 | |
1056 | #define BFD_RELOC_386_GOTOFF 0 | |
1057 | #endif | |
1058 | ||
47926f60 | 1059 | static int intel_float_operand PARAMS ((char *mnemonic)); |
b4cac588 AM |
1060 | |
1061 | static int | |
252b5132 RH |
1062 | intel_float_operand (mnemonic) |
1063 | char *mnemonic; | |
1064 | { | |
47926f60 | 1065 | if (mnemonic[0] == 'f' && mnemonic[1] == 'i') |
cc5ca5ce | 1066 | return 2; |
252b5132 RH |
1067 | |
1068 | if (mnemonic[0] == 'f') | |
1069 | return 1; | |
1070 | ||
1071 | return 0; | |
1072 | } | |
1073 | ||
1074 | /* This is the guts of the machine-dependent assembler. LINE points to a | |
1075 | machine dependent instruction. This function is supposed to emit | |
1076 | the frags/bytes it assembles to. */ | |
1077 | ||
1078 | void | |
1079 | md_assemble (line) | |
1080 | char *line; | |
1081 | { | |
47926f60 | 1082 | /* Points to template once we've found it. */ |
252b5132 RH |
1083 | const template *t; |
1084 | ||
1085 | /* Count the size of the instruction generated. */ | |
1086 | int insn_size = 0; | |
1087 | ||
1088 | int j; | |
1089 | ||
1090 | char mnemonic[MAX_MNEM_SIZE]; | |
1091 | ||
47926f60 | 1092 | /* Initialize globals. */ |
252b5132 RH |
1093 | memset (&i, '\0', sizeof (i)); |
1094 | for (j = 0; j < MAX_OPERANDS; j++) | |
1095 | i.disp_reloc[j] = NO_RELOC; | |
1096 | memset (disp_expressions, '\0', sizeof (disp_expressions)); | |
1097 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 1098 | save_stack_p = save_stack; |
252b5132 RH |
1099 | |
1100 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
1101 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 1102 | start of a (possibly prefixed) mnemonic. */ |
252b5132 RH |
1103 | { |
1104 | char *l = line; | |
1105 | char *token_start = l; | |
1106 | char *mnem_p; | |
1107 | ||
47926f60 | 1108 | /* Non-zero if we found a prefix only acceptable with string insns. */ |
252b5132 RH |
1109 | const char *expecting_string_instruction = NULL; |
1110 | ||
1111 | while (1) | |
1112 | { | |
1113 | mnem_p = mnemonic; | |
1114 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
1115 | { | |
1116 | mnem_p++; | |
1117 | if (mnem_p >= mnemonic + sizeof (mnemonic)) | |
1118 | { | |
e413e4e9 | 1119 | as_bad (_("no such instruction: `%s'"), token_start); |
252b5132 RH |
1120 | return; |
1121 | } | |
1122 | l++; | |
1123 | } | |
1124 | if (!is_space_char (*l) | |
1125 | && *l != END_OF_INSN | |
1126 | && *l != PREFIX_SEPARATOR) | |
1127 | { | |
1128 | as_bad (_("invalid character %s in mnemonic"), | |
1129 | output_invalid (*l)); | |
1130 | return; | |
1131 | } | |
1132 | if (token_start == l) | |
1133 | { | |
1134 | if (*l == PREFIX_SEPARATOR) | |
1135 | as_bad (_("expecting prefix; got nothing")); | |
1136 | else | |
1137 | as_bad (_("expecting mnemonic; got nothing")); | |
1138 | return; | |
1139 | } | |
1140 | ||
1141 | /* Look up instruction (or prefix) via hash table. */ | |
1142 | current_templates = hash_find (op_hash, mnemonic); | |
1143 | ||
1144 | if (*l != END_OF_INSN | |
1145 | && (! is_space_char (*l) || l[1] != END_OF_INSN) | |
1146 | && current_templates | |
1147 | && (current_templates->start->opcode_modifier & IsPrefix)) | |
1148 | { | |
1149 | /* If we are in 16-bit mode, do not allow addr16 or data16. | |
1150 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
1151 | if ((current_templates->start->opcode_modifier & (Size16 | Size32)) | |
1152 | && (((current_templates->start->opcode_modifier & Size32) != 0) | |
1153 | ^ flag_16bit_code)) | |
1154 | { | |
1155 | as_bad (_("redundant %s prefix"), | |
1156 | current_templates->start->name); | |
1157 | return; | |
1158 | } | |
1159 | /* Add prefix, checking for repeated prefixes. */ | |
1160 | switch (add_prefix (current_templates->start->base_opcode)) | |
1161 | { | |
1162 | case 0: | |
1163 | return; | |
1164 | case 2: | |
47926f60 | 1165 | expecting_string_instruction = current_templates->start->name; |
252b5132 RH |
1166 | break; |
1167 | } | |
1168 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
1169 | token_start = ++l; | |
1170 | } | |
1171 | else | |
1172 | break; | |
1173 | } | |
1174 | ||
1175 | if (!current_templates) | |
1176 | { | |
24eab124 | 1177 | /* See if we can get a match by trimming off a suffix. */ |
252b5132 RH |
1178 | switch (mnem_p[-1]) |
1179 | { | |
252b5132 RH |
1180 | case WORD_MNEM_SUFFIX: |
1181 | case BYTE_MNEM_SUFFIX: | |
1182 | case SHORT_MNEM_SUFFIX: | |
252b5132 | 1183 | case LONG_MNEM_SUFFIX: |
252b5132 RH |
1184 | i.suffix = mnem_p[-1]; |
1185 | mnem_p[-1] = '\0'; | |
1186 | current_templates = hash_find (op_hash, mnemonic); | |
24eab124 AM |
1187 | break; |
1188 | ||
ce8a8b2f | 1189 | /* Intel Syntax. */ |
add0c677 | 1190 | case DWORD_MNEM_SUFFIX: |
24eab124 AM |
1191 | if (intel_syntax) |
1192 | { | |
1193 | i.suffix = mnem_p[-1]; | |
1194 | mnem_p[-1] = '\0'; | |
1195 | current_templates = hash_find (op_hash, mnemonic); | |
1196 | break; | |
1197 | } | |
252b5132 RH |
1198 | } |
1199 | if (!current_templates) | |
1200 | { | |
e413e4e9 | 1201 | as_bad (_("no such instruction: `%s'"), token_start); |
252b5132 RH |
1202 | return; |
1203 | } | |
1204 | } | |
1205 | ||
e413e4e9 AM |
1206 | /* Check if instruction is supported on specified architecture. */ |
1207 | if (cpu_arch_flags != 0) | |
1208 | { | |
47926f60 | 1209 | if (current_templates->start->cpu_flags & ~cpu_arch_flags) |
e413e4e9 AM |
1210 | { |
1211 | as_warn (_("`%s' is not supported on `%s'"), | |
1212 | current_templates->start->name, cpu_arch_name); | |
1213 | } | |
47926f60 | 1214 | else if ((Cpu386 & ~cpu_arch_flags) && !flag_16bit_code) |
e413e4e9 AM |
1215 | { |
1216 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
1217 | } | |
1218 | } | |
1219 | ||
ce8a8b2f | 1220 | /* Check for rep/repne without a string instruction. */ |
252b5132 RH |
1221 | if (expecting_string_instruction |
1222 | && !(current_templates->start->opcode_modifier & IsString)) | |
1223 | { | |
1224 | as_bad (_("expecting string instruction after `%s'"), | |
1225 | expecting_string_instruction); | |
1226 | return; | |
1227 | } | |
1228 | ||
47926f60 | 1229 | /* There may be operands to parse. */ |
252b5132 RH |
1230 | if (*l != END_OF_INSN) |
1231 | { | |
47926f60 | 1232 | /* 1 if operand is pending after ','. */ |
252b5132 RH |
1233 | unsigned int expecting_operand = 0; |
1234 | ||
47926f60 | 1235 | /* Non-zero if operand parens not balanced. */ |
252b5132 RH |
1236 | unsigned int paren_not_balanced; |
1237 | ||
1238 | do | |
1239 | { | |
ce8a8b2f | 1240 | /* Skip optional white space before operand. */ |
252b5132 RH |
1241 | if (is_space_char (*l)) |
1242 | ++l; | |
1243 | if (!is_operand_char (*l) && *l != END_OF_INSN) | |
1244 | { | |
1245 | as_bad (_("invalid character %s before operand %d"), | |
1246 | output_invalid (*l), | |
1247 | i.operands + 1); | |
1248 | return; | |
1249 | } | |
1250 | token_start = l; /* after white space */ | |
1251 | paren_not_balanced = 0; | |
1252 | while (paren_not_balanced || *l != ',') | |
1253 | { | |
1254 | if (*l == END_OF_INSN) | |
1255 | { | |
1256 | if (paren_not_balanced) | |
1257 | { | |
24eab124 | 1258 | if (!intel_syntax) |
252b5132 RH |
1259 | as_bad (_("unbalanced parenthesis in operand %d."), |
1260 | i.operands + 1); | |
24eab124 | 1261 | else |
252b5132 RH |
1262 | as_bad (_("unbalanced brackets in operand %d."), |
1263 | i.operands + 1); | |
1264 | return; | |
1265 | } | |
1266 | else | |
1267 | break; /* we are done */ | |
1268 | } | |
1269 | else if (!is_operand_char (*l) && !is_space_char (*l)) | |
1270 | { | |
1271 | as_bad (_("invalid character %s in operand %d"), | |
1272 | output_invalid (*l), | |
1273 | i.operands + 1); | |
1274 | return; | |
1275 | } | |
24eab124 AM |
1276 | if (!intel_syntax) |
1277 | { | |
252b5132 RH |
1278 | if (*l == '(') |
1279 | ++paren_not_balanced; | |
1280 | if (*l == ')') | |
1281 | --paren_not_balanced; | |
24eab124 AM |
1282 | } |
1283 | else | |
1284 | { | |
252b5132 RH |
1285 | if (*l == '[') |
1286 | ++paren_not_balanced; | |
1287 | if (*l == ']') | |
1288 | --paren_not_balanced; | |
24eab124 | 1289 | } |
252b5132 RH |
1290 | l++; |
1291 | } | |
1292 | if (l != token_start) | |
47926f60 | 1293 | { /* Yes, we've read in another operand. */ |
252b5132 RH |
1294 | unsigned int operand_ok; |
1295 | this_operand = i.operands++; | |
1296 | if (i.operands > MAX_OPERANDS) | |
1297 | { | |
1298 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
1299 | MAX_OPERANDS); | |
1300 | return; | |
1301 | } | |
47926f60 | 1302 | /* Now parse operand adding info to 'i' as we go along. */ |
252b5132 RH |
1303 | END_STRING_AND_SAVE (l); |
1304 | ||
24eab124 | 1305 | if (intel_syntax) |
47926f60 KH |
1306 | operand_ok = |
1307 | i386_intel_operand (token_start, | |
1308 | intel_float_operand (mnemonic)); | |
24eab124 AM |
1309 | else |
1310 | operand_ok = i386_operand (token_start); | |
252b5132 | 1311 | |
ce8a8b2f | 1312 | RESTORE_END_STRING (l); |
252b5132 RH |
1313 | if (!operand_ok) |
1314 | return; | |
1315 | } | |
1316 | else | |
1317 | { | |
1318 | if (expecting_operand) | |
1319 | { | |
1320 | expecting_operand_after_comma: | |
1321 | as_bad (_("expecting operand after ','; got nothing")); | |
1322 | return; | |
1323 | } | |
1324 | if (*l == ',') | |
1325 | { | |
1326 | as_bad (_("expecting operand before ','; got nothing")); | |
1327 | return; | |
1328 | } | |
1329 | } | |
1330 | ||
ce8a8b2f | 1331 | /* Now *l must be either ',' or END_OF_INSN. */ |
252b5132 RH |
1332 | if (*l == ',') |
1333 | { | |
1334 | if (*++l == END_OF_INSN) | |
ce8a8b2f AM |
1335 | { |
1336 | /* Just skip it, if it's \n complain. */ | |
252b5132 RH |
1337 | goto expecting_operand_after_comma; |
1338 | } | |
1339 | expecting_operand = 1; | |
1340 | } | |
1341 | } | |
ce8a8b2f | 1342 | while (*l != END_OF_INSN); |
252b5132 RH |
1343 | } |
1344 | } | |
1345 | ||
1346 | /* Now we've parsed the mnemonic into a set of templates, and have the | |
1347 | operands at hand. | |
1348 | ||
1349 | Next, we find a template that matches the given insn, | |
1350 | making sure the overlap of the given operands types is consistent | |
47926f60 | 1351 | with the template operand types. */ |
252b5132 RH |
1352 | |
1353 | #define MATCH(overlap, given, template) \ | |
3138f287 AM |
1354 | ((overlap & ~JumpAbsolute) \ |
1355 | && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute))) | |
252b5132 RH |
1356 | |
1357 | /* If given types r0 and r1 are registers they must be of the same type | |
1358 | unless the expected operand type register overlap is null. | |
1359 | Note that Acc in a template matches every size of reg. */ | |
1360 | #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \ | |
1361 | ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \ | |
1362 | ((g0) & Reg) == ((g1) & Reg) || \ | |
1363 | ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 ) | |
1364 | ||
1365 | { | |
1366 | register unsigned int overlap0, overlap1; | |
252b5132 RH |
1367 | unsigned int overlap2; |
1368 | unsigned int found_reverse_match; | |
1369 | int suffix_check; | |
1370 | ||
cc5ca5ce AM |
1371 | /* All intel opcodes have reversed operands except for "bound" and |
1372 | "enter". We also don't reverse intersegment "jmp" and "call" | |
1373 | instructions with 2 immediate operands so that the immediate segment | |
1374 | precedes the offset, as it does when in AT&T mode. "enter" and the | |
1375 | intersegment "jmp" and "call" instructions are the only ones that | |
1376 | have two immediate operands. */ | |
520dc8e8 | 1377 | if (intel_syntax && i.operands > 1 |
cc5ca5ce AM |
1378 | && (strcmp (mnemonic, "bound") != 0) |
1379 | && !((i.types[0] & Imm) && (i.types[1] & Imm))) | |
252b5132 | 1380 | { |
520dc8e8 | 1381 | union i386_op temp_op; |
24eab124 AM |
1382 | unsigned int temp_type; |
1383 | int xchg1 = 0; | |
ab9da554 | 1384 | int xchg2 = 0; |
252b5132 | 1385 | |
24eab124 AM |
1386 | if (i.operands == 2) |
1387 | { | |
1388 | xchg1 = 0; | |
1389 | xchg2 = 1; | |
1390 | } | |
1391 | else if (i.operands == 3) | |
1392 | { | |
1393 | xchg1 = 0; | |
1394 | xchg2 = 2; | |
1395 | } | |
520dc8e8 AM |
1396 | temp_type = i.types[xchg2]; |
1397 | i.types[xchg2] = i.types[xchg1]; | |
1398 | i.types[xchg1] = temp_type; | |
1399 | temp_op = i.op[xchg2]; | |
1400 | i.op[xchg2] = i.op[xchg1]; | |
1401 | i.op[xchg1] = temp_op; | |
36bf8ab9 AM |
1402 | |
1403 | if (i.mem_operands == 2) | |
1404 | { | |
1405 | const seg_entry *temp_seg; | |
1406 | temp_seg = i.seg[0]; | |
1407 | i.seg[0] = i.seg[1]; | |
1408 | i.seg[1] = temp_seg; | |
1409 | } | |
24eab124 | 1410 | } |
773f551c AM |
1411 | |
1412 | if (i.imm_operands) | |
1413 | { | |
1414 | /* Try to ensure constant immediates are represented in the smallest | |
1415 | opcode possible. */ | |
1416 | char guess_suffix = 0; | |
1417 | int op; | |
1418 | ||
1419 | if (i.suffix) | |
1420 | guess_suffix = i.suffix; | |
1421 | else if (i.reg_operands) | |
1422 | { | |
1423 | /* Figure out a suffix from the last register operand specified. | |
1424 | We can't do this properly yet, ie. excluding InOutPortReg, | |
1425 | but the following works for instructions with immediates. | |
1426 | In any case, we can't set i.suffix yet. */ | |
47926f60 | 1427 | for (op = i.operands; --op >= 0;) |
773f551c AM |
1428 | if (i.types[op] & Reg) |
1429 | { | |
1430 | if (i.types[op] & Reg8) | |
1431 | guess_suffix = BYTE_MNEM_SUFFIX; | |
1432 | else if (i.types[op] & Reg16) | |
1433 | guess_suffix = WORD_MNEM_SUFFIX; | |
1434 | break; | |
1435 | } | |
1436 | } | |
726c5dcd AM |
1437 | else if (flag_16bit_code ^ (i.prefix[DATA_PREFIX] != 0)) |
1438 | guess_suffix = WORD_MNEM_SUFFIX; | |
1439 | ||
47926f60 | 1440 | for (op = i.operands; --op >= 0;) |
773f551c AM |
1441 | if ((i.types[op] & Imm) |
1442 | && i.op[op].imms->X_op == O_constant) | |
1443 | { | |
1444 | /* If a suffix is given, this operand may be shortened. */ | |
1445 | switch (guess_suffix) | |
1446 | { | |
1447 | case WORD_MNEM_SUFFIX: | |
1448 | i.types[op] |= Imm16; | |
1449 | break; | |
1450 | case BYTE_MNEM_SUFFIX: | |
1451 | i.types[op] |= Imm16 | Imm8 | Imm8S; | |
1452 | break; | |
1453 | } | |
1454 | ||
1455 | /* If this operand is at most 16 bits, convert it to a | |
1456 | signed 16 bit number before trying to see whether it will | |
1457 | fit in an even smaller size. This allows a 16-bit operand | |
1458 | such as $0xffe0 to be recognised as within Imm8S range. */ | |
1459 | if ((i.types[op] & Imm16) | |
1460 | && (i.op[op].imms->X_add_number & ~(offsetT)0xffff) == 0) | |
1461 | { | |
1462 | i.op[op].imms->X_add_number = | |
1463 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
1464 | } | |
1465 | i.types[op] |= smallest_imm_type ((long) i.op[op].imms->X_add_number); | |
1466 | } | |
1467 | } | |
1468 | ||
45288df1 AM |
1469 | if (i.disp_operands) |
1470 | { | |
1471 | /* Try to use the smallest displacement type too. */ | |
1472 | int op; | |
1473 | ||
47926f60 | 1474 | for (op = i.operands; --op >= 0;) |
45288df1 AM |
1475 | if ((i.types[op] & Disp) |
1476 | && i.op[op].imms->X_op == O_constant) | |
1477 | { | |
1478 | offsetT disp = i.op[op].disps->X_add_number; | |
1479 | ||
1480 | if (i.types[op] & Disp16) | |
1481 | { | |
1482 | /* We know this operand is at most 16 bits, so | |
1483 | convert to a signed 16 bit number before trying | |
1484 | to see whether it will fit in an even smaller | |
1485 | size. */ | |
47926f60 | 1486 | |
45288df1 AM |
1487 | disp = (((disp & 0xffff) ^ 0x8000) - 0x8000); |
1488 | } | |
1489 | if (fits_in_signed_byte (disp)) | |
1490 | i.types[op] |= Disp8; | |
1491 | } | |
1492 | } | |
1493 | ||
252b5132 RH |
1494 | overlap0 = 0; |
1495 | overlap1 = 0; | |
1496 | overlap2 = 0; | |
1497 | found_reverse_match = 0; | |
1498 | suffix_check = (i.suffix == BYTE_MNEM_SUFFIX | |
1499 | ? No_bSuf | |
1500 | : (i.suffix == WORD_MNEM_SUFFIX | |
1501 | ? No_wSuf | |
1502 | : (i.suffix == SHORT_MNEM_SUFFIX | |
1503 | ? No_sSuf | |
1504 | : (i.suffix == LONG_MNEM_SUFFIX | |
24eab124 | 1505 | ? No_lSuf |
add0c677 | 1506 | : (i.suffix == DWORD_MNEM_SUFFIX |
24eab124 AM |
1507 | ? No_dSuf |
1508 | : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX ? No_xSuf : 0)))))); | |
252b5132 RH |
1509 | |
1510 | for (t = current_templates->start; | |
1511 | t < current_templates->end; | |
1512 | t++) | |
1513 | { | |
47926f60 | 1514 | /* Must have right number of operands. */ |
252b5132 RH |
1515 | if (i.operands != t->operands) |
1516 | continue; | |
1517 | ||
7f3f1ea2 AM |
1518 | /* Check the suffix, except for some instructions in intel mode. */ |
1519 | if ((t->opcode_modifier & suffix_check) | |
fa2255cb DN |
1520 | && !(intel_syntax |
1521 | && (t->opcode_modifier & IgnoreSize)) | |
7f3f1ea2 AM |
1522 | && !(intel_syntax |
1523 | && t->base_opcode == 0xd9 | |
ce8a8b2f AM |
1524 | && (t->extension_opcode == 5 /* 0xd9,5 "fldcw" */ |
1525 | || t->extension_opcode == 7))) /* 0xd9,7 "f{n}stcw" */ | |
24eab124 | 1526 | continue; |
252b5132 RH |
1527 | |
1528 | else if (!t->operands) | |
47926f60 KH |
1529 | /* 0 operands always matches. */ |
1530 | break; | |
252b5132 RH |
1531 | |
1532 | overlap0 = i.types[0] & t->operand_types[0]; | |
1533 | switch (t->operands) | |
1534 | { | |
1535 | case 1: | |
1536 | if (!MATCH (overlap0, i.types[0], t->operand_types[0])) | |
1537 | continue; | |
1538 | break; | |
1539 | case 2: | |
1540 | case 3: | |
1541 | overlap1 = i.types[1] & t->operand_types[1]; | |
1542 | if (!MATCH (overlap0, i.types[0], t->operand_types[0]) | |
1543 | || !MATCH (overlap1, i.types[1], t->operand_types[1]) | |
1544 | || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], | |
1545 | t->operand_types[0], | |
1546 | overlap1, i.types[1], | |
1547 | t->operand_types[1])) | |
1548 | { | |
47926f60 | 1549 | /* Check if other direction is valid ... */ |
252b5132 RH |
1550 | if ((t->opcode_modifier & (D|FloatD)) == 0) |
1551 | continue; | |
1552 | ||
47926f60 | 1553 | /* Try reversing direction of operands. */ |
252b5132 RH |
1554 | overlap0 = i.types[0] & t->operand_types[1]; |
1555 | overlap1 = i.types[1] & t->operand_types[0]; | |
1556 | if (!MATCH (overlap0, i.types[0], t->operand_types[1]) | |
1557 | || !MATCH (overlap1, i.types[1], t->operand_types[0]) | |
1558 | || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], | |
1559 | t->operand_types[1], | |
1560 | overlap1, i.types[1], | |
1561 | t->operand_types[0])) | |
1562 | { | |
47926f60 | 1563 | /* Does not match either direction. */ |
252b5132 RH |
1564 | continue; |
1565 | } | |
1566 | /* found_reverse_match holds which of D or FloatDR | |
1567 | we've found. */ | |
1568 | found_reverse_match = t->opcode_modifier & (D|FloatDR); | |
1569 | break; | |
1570 | } | |
47926f60 | 1571 | /* Found a forward 2 operand match here. */ |
252b5132 RH |
1572 | if (t->operands == 3) |
1573 | { | |
1574 | /* Here we make use of the fact that there are no | |
1575 | reverse match 3 operand instructions, and all 3 | |
1576 | operand instructions only need to be checked for | |
1577 | register consistency between operands 2 and 3. */ | |
1578 | overlap2 = i.types[2] & t->operand_types[2]; | |
1579 | if (!MATCH (overlap2, i.types[2], t->operand_types[2]) | |
1580 | || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1], | |
1581 | t->operand_types[1], | |
1582 | overlap2, i.types[2], | |
24eab124 | 1583 | t->operand_types[2])) |
252b5132 | 1584 | |
24eab124 | 1585 | continue; |
252b5132 | 1586 | } |
47926f60 | 1587 | /* Found either forward/reverse 2 or 3 operand match here: |
ce8a8b2f | 1588 | slip through to break. */ |
252b5132 | 1589 | } |
47926f60 KH |
1590 | /* We've found a match; break out of loop. */ |
1591 | break; | |
ce8a8b2f | 1592 | } |
252b5132 | 1593 | if (t == current_templates->end) |
47926f60 KH |
1594 | { |
1595 | /* We found no match. */ | |
252b5132 RH |
1596 | as_bad (_("suffix or operands invalid for `%s'"), |
1597 | current_templates->start->name); | |
1598 | return; | |
1599 | } | |
1600 | ||
a38cf1db | 1601 | if (!quiet_warnings) |
3138f287 | 1602 | { |
a38cf1db AM |
1603 | if (!intel_syntax |
1604 | && ((i.types[0] & JumpAbsolute) | |
1605 | != (t->operand_types[0] & JumpAbsolute))) | |
1606 | { | |
1607 | as_warn (_("indirect %s without `*'"), t->name); | |
1608 | } | |
3138f287 | 1609 | |
a38cf1db AM |
1610 | if ((t->opcode_modifier & (IsPrefix|IgnoreSize)) |
1611 | == (IsPrefix|IgnoreSize)) | |
1612 | { | |
1613 | /* Warn them that a data or address size prefix doesn't | |
1614 | affect assembly of the next line of code. */ | |
1615 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
1616 | } | |
252b5132 RH |
1617 | } |
1618 | ||
1619 | /* Copy the template we found. */ | |
1620 | i.tm = *t; | |
1621 | if (found_reverse_match) | |
1622 | { | |
7f3f1ea2 AM |
1623 | /* If we found a reverse match we must alter the opcode |
1624 | direction bit. found_reverse_match holds bits to change | |
1625 | (different for int & float insns). */ | |
1626 | ||
1627 | i.tm.base_opcode ^= found_reverse_match; | |
1628 | ||
252b5132 RH |
1629 | i.tm.operand_types[0] = t->operand_types[1]; |
1630 | i.tm.operand_types[1] = t->operand_types[0]; | |
1631 | } | |
1632 | ||
d0b47220 AM |
1633 | /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */ |
1634 | if (SYSV386_COMPAT | |
7f3f1ea2 AM |
1635 | && intel_syntax |
1636 | && (i.tm.base_opcode & 0xfffffde0) == 0xdce0) | |
1637 | i.tm.base_opcode ^= FloatR; | |
252b5132 RH |
1638 | |
1639 | if (i.tm.opcode_modifier & FWait) | |
1640 | if (! add_prefix (FWAIT_OPCODE)) | |
1641 | return; | |
1642 | ||
ce8a8b2f | 1643 | /* Check string instruction segment overrides. */ |
252b5132 RH |
1644 | if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0) |
1645 | { | |
1646 | int mem_op = (i.types[0] & AnyMem) ? 0 : 1; | |
1647 | if ((i.tm.operand_types[mem_op] & EsSeg) != 0) | |
1648 | { | |
1649 | if (i.seg[0] != NULL && i.seg[0] != &es) | |
1650 | { | |
1651 | as_bad (_("`%s' operand %d must use `%%es' segment"), | |
1652 | i.tm.name, | |
1653 | mem_op + 1); | |
1654 | return; | |
1655 | } | |
1656 | /* There's only ever one segment override allowed per instruction. | |
1657 | This instruction possibly has a legal segment override on the | |
1658 | second operand, so copy the segment to where non-string | |
1659 | instructions store it, allowing common code. */ | |
1660 | i.seg[0] = i.seg[1]; | |
1661 | } | |
1662 | else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0) | |
1663 | { | |
1664 | if (i.seg[1] != NULL && i.seg[1] != &es) | |
1665 | { | |
1666 | as_bad (_("`%s' operand %d must use `%%es' segment"), | |
1667 | i.tm.name, | |
1668 | mem_op + 2); | |
1669 | return; | |
1670 | } | |
1671 | } | |
1672 | } | |
1673 | ||
1674 | /* If matched instruction specifies an explicit instruction mnemonic | |
1675 | suffix, use it. */ | |
1676 | if (i.tm.opcode_modifier & (Size16 | Size32)) | |
1677 | { | |
1678 | if (i.tm.opcode_modifier & Size16) | |
1679 | i.suffix = WORD_MNEM_SUFFIX; | |
1680 | else | |
add0c677 | 1681 | i.suffix = LONG_MNEM_SUFFIX; |
252b5132 RH |
1682 | } |
1683 | else if (i.reg_operands) | |
1684 | { | |
1685 | /* If there's no instruction mnemonic suffix we try to invent one | |
47926f60 | 1686 | based on register operands. */ |
252b5132 RH |
1687 | if (!i.suffix) |
1688 | { | |
1689 | /* We take i.suffix from the last register operand specified, | |
1690 | Destination register type is more significant than source | |
1691 | register type. */ | |
1692 | int op; | |
47926f60 | 1693 | for (op = i.operands; --op >= 0;) |
cc5ca5ce AM |
1694 | if ((i.types[op] & Reg) |
1695 | && !(i.tm.operand_types[op] & InOutPortReg)) | |
252b5132 RH |
1696 | { |
1697 | i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX : | |
1698 | (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX : | |
add0c677 | 1699 | LONG_MNEM_SUFFIX); |
252b5132 RH |
1700 | break; |
1701 | } | |
1702 | } | |
1703 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
1704 | { | |
1705 | int op; | |
47926f60 | 1706 | for (op = i.operands; --op >= 0;) |
252b5132 RH |
1707 | { |
1708 | /* If this is an eight bit register, it's OK. If it's | |
1709 | the 16 or 32 bit version of an eight bit register, | |
47926f60 | 1710 | we will just use the low portion, and that's OK too. */ |
252b5132 RH |
1711 | if (i.types[op] & Reg8) |
1712 | continue; | |
1713 | ||
47926f60 | 1714 | /* movzx and movsx should not generate this warning. */ |
24eab124 AM |
1715 | if (intel_syntax |
1716 | && (i.tm.base_opcode == 0xfb7 | |
1717 | || i.tm.base_opcode == 0xfb6 | |
1718 | || i.tm.base_opcode == 0xfbe | |
1719 | || i.tm.base_opcode == 0xfbf)) | |
1720 | continue; | |
252b5132 | 1721 | |
520dc8e8 | 1722 | if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4 |
252b5132 RH |
1723 | #if 0 |
1724 | /* Check that the template allows eight bit regs | |
1725 | This kills insns such as `orb $1,%edx', which | |
1726 | maybe should be allowed. */ | |
1727 | && (i.tm.operand_types[op] & (Reg8|InOutPortReg)) | |
1728 | #endif | |
1729 | ) | |
1730 | { | |
1731 | #if REGISTER_WARNINGS | |
a38cf1db AM |
1732 | if (!quiet_warnings |
1733 | && (i.tm.operand_types[op] & InOutPortReg) == 0) | |
252b5132 | 1734 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), |
520dc8e8 AM |
1735 | (i.op[op].regs - (i.types[op] & Reg16 ? 8 : 16))->reg_name, |
1736 | i.op[op].regs->reg_name, | |
252b5132 RH |
1737 | i.suffix); |
1738 | #endif | |
1739 | continue; | |
1740 | } | |
ce8a8b2f | 1741 | /* Any other register is bad. */ |
3f4438ab AM |
1742 | if (i.types[op] & (Reg | RegMMX | RegXMM |
1743 | | SReg2 | SReg3 | |
1744 | | Control | Debug | Test | |
1745 | | FloatReg | FloatAcc)) | |
252b5132 RH |
1746 | { |
1747 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
520dc8e8 | 1748 | i.op[op].regs->reg_name, |
252b5132 RH |
1749 | i.tm.name, |
1750 | i.suffix); | |
1751 | return; | |
1752 | } | |
1753 | } | |
1754 | } | |
add0c677 | 1755 | else if (i.suffix == LONG_MNEM_SUFFIX) |
252b5132 RH |
1756 | { |
1757 | int op; | |
47926f60 KH |
1758 | |
1759 | for (op = i.operands; --op >= 0;) | |
252b5132 RH |
1760 | /* Reject eight bit registers, except where the template |
1761 | requires them. (eg. movzb) */ | |
1762 | if ((i.types[op] & Reg8) != 0 | |
47926f60 | 1763 | && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0) |
252b5132 RH |
1764 | { |
1765 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
520dc8e8 | 1766 | i.op[op].regs->reg_name, |
252b5132 RH |
1767 | i.tm.name, |
1768 | i.suffix); | |
1769 | return; | |
1770 | } | |
1771 | #if REGISTER_WARNINGS | |
1772 | /* Warn if the e prefix on a general reg is missing. */ | |
a38cf1db AM |
1773 | else if (!quiet_warnings |
1774 | && (i.types[op] & Reg16) != 0 | |
252b5132 RH |
1775 | && (i.tm.operand_types[op] & (Reg32|Acc)) != 0) |
1776 | { | |
1777 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), | |
520dc8e8 AM |
1778 | (i.op[op].regs + 8)->reg_name, |
1779 | i.op[op].regs->reg_name, | |
252b5132 RH |
1780 | i.suffix); |
1781 | } | |
1782 | #endif | |
1783 | } | |
1784 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
1785 | { | |
1786 | int op; | |
47926f60 | 1787 | for (op = i.operands; --op >= 0;) |
252b5132 RH |
1788 | /* Reject eight bit registers, except where the template |
1789 | requires them. (eg. movzb) */ | |
1790 | if ((i.types[op] & Reg8) != 0 | |
1791 | && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0) | |
1792 | { | |
1793 | as_bad (_("`%%%s' not allowed with `%s%c'"), | |
520dc8e8 | 1794 | i.op[op].regs->reg_name, |
252b5132 RH |
1795 | i.tm.name, |
1796 | i.suffix); | |
1797 | return; | |
1798 | } | |
1799 | #if REGISTER_WARNINGS | |
1800 | /* Warn if the e prefix on a general reg is present. */ | |
a38cf1db AM |
1801 | else if (!quiet_warnings |
1802 | && (i.types[op] & Reg32) != 0 | |
252b5132 RH |
1803 | && (i.tm.operand_types[op] & (Reg16|Acc)) != 0) |
1804 | { | |
1805 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), | |
520dc8e8 AM |
1806 | (i.op[op].regs - 8)->reg_name, |
1807 | i.op[op].regs->reg_name, | |
252b5132 RH |
1808 | i.suffix); |
1809 | } | |
1810 | #endif | |
1811 | } | |
fa2255cb DN |
1812 | else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize)) |
1813 | /* Do nothing if the instruction is going to ignore the prefix. */ | |
1814 | ; | |
252b5132 | 1815 | else |
47926f60 | 1816 | abort (); |
252b5132 | 1817 | } |
eecb386c AM |
1818 | else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix) |
1819 | { | |
1820 | i.suffix = stackop_size; | |
1821 | } | |
252b5132 RH |
1822 | |
1823 | /* Make still unresolved immediate matches conform to size of immediate | |
1824 | given in i.suffix. Note: overlap2 cannot be an immediate! */ | |
1825 | if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32)) | |
1826 | && overlap0 != Imm8 && overlap0 != Imm8S | |
1827 | && overlap0 != Imm16 && overlap0 != Imm32) | |
1828 | { | |
1829 | if (i.suffix) | |
1830 | { | |
24eab124 AM |
1831 | overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) : |
1832 | (i.suffix == WORD_MNEM_SUFFIX ? Imm16 : Imm32)); | |
252b5132 RH |
1833 | } |
1834 | else if (overlap0 == (Imm16 | Imm32)) | |
1835 | { | |
24eab124 | 1836 | overlap0 = |
252b5132 RH |
1837 | (flag_16bit_code ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32; |
1838 | } | |
1839 | else | |
1840 | { | |
1841 | as_bad (_("no instruction mnemonic suffix given; can't determine immediate size")); | |
1842 | return; | |
1843 | } | |
1844 | } | |
1845 | if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32)) | |
1846 | && overlap1 != Imm8 && overlap1 != Imm8S | |
1847 | && overlap1 != Imm16 && overlap1 != Imm32) | |
1848 | { | |
1849 | if (i.suffix) | |
1850 | { | |
24eab124 AM |
1851 | overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) : |
1852 | (i.suffix == WORD_MNEM_SUFFIX ? Imm16 : Imm32)); | |
252b5132 RH |
1853 | } |
1854 | else if (overlap1 == (Imm16 | Imm32)) | |
1855 | { | |
24eab124 | 1856 | overlap1 = |
252b5132 RH |
1857 | (flag_16bit_code ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32; |
1858 | } | |
1859 | else | |
1860 | { | |
1861 | as_bad (_("no instruction mnemonic suffix given; can't determine immediate size")); | |
1862 | return; | |
1863 | } | |
1864 | } | |
1865 | assert ((overlap2 & Imm) == 0); | |
1866 | ||
1867 | i.types[0] = overlap0; | |
1868 | if (overlap0 & ImplicitRegister) | |
1869 | i.reg_operands--; | |
1870 | if (overlap0 & Imm1) | |
ce8a8b2f | 1871 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 RH |
1872 | |
1873 | i.types[1] = overlap1; | |
1874 | if (overlap1 & ImplicitRegister) | |
1875 | i.reg_operands--; | |
1876 | ||
1877 | i.types[2] = overlap2; | |
1878 | if (overlap2 & ImplicitRegister) | |
1879 | i.reg_operands--; | |
1880 | ||
1881 | /* Finalize opcode. First, we change the opcode based on the operand | |
1882 | size given by i.suffix: We need not change things for byte insns. */ | |
1883 | ||
1884 | if (!i.suffix && (i.tm.opcode_modifier & W)) | |
1885 | { | |
1886 | as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction")); | |
1887 | return; | |
1888 | } | |
1889 | ||
ce8a8b2f | 1890 | /* For movzx and movsx, need to check the register type. */ |
252b5132 | 1891 | if (intel_syntax |
24eab124 | 1892 | && (i.tm.base_opcode == 0xfb6 || i.tm.base_opcode == 0xfbe)) |
252b5132 | 1893 | if (i.suffix && i.suffix == BYTE_MNEM_SUFFIX) |
24eab124 AM |
1894 | { |
1895 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
252b5132 | 1896 | |
520dc8e8 | 1897 | if ((i.op[1].regs->reg_type & Reg16) != 0) |
24eab124 AM |
1898 | if (!add_prefix (prefix)) |
1899 | return; | |
1900 | } | |
252b5132 RH |
1901 | |
1902 | if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX) | |
1903 | { | |
1904 | /* It's not a byte, select word/dword operation. */ | |
1905 | if (i.tm.opcode_modifier & W) | |
1906 | { | |
1907 | if (i.tm.opcode_modifier & ShortForm) | |
1908 | i.tm.base_opcode |= 8; | |
1909 | else | |
1910 | i.tm.base_opcode |= 1; | |
1911 | } | |
1912 | /* Now select between word & dword operations via the operand | |
1913 | size prefix, except for instructions that will ignore this | |
1914 | prefix anyway. */ | |
add0c677 | 1915 | if (((intel_syntax && (i.suffix == DWORD_MNEM_SUFFIX)) |
252b5132 RH |
1916 | || i.suffix == LONG_MNEM_SUFFIX) == flag_16bit_code |
1917 | && !(i.tm.opcode_modifier & IgnoreSize)) | |
1918 | { | |
1919 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
1920 | if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */ | |
1921 | prefix = ADDR_PREFIX_OPCODE; | |
1922 | ||
1923 | if (! add_prefix (prefix)) | |
1924 | return; | |
1925 | } | |
1926 | /* Size floating point instruction. */ | |
1927 | if (i.suffix == LONG_MNEM_SUFFIX | |
add0c677 | 1928 | || (intel_syntax && i.suffix == DWORD_MNEM_SUFFIX)) |
252b5132 RH |
1929 | { |
1930 | if (i.tm.opcode_modifier & FloatMF) | |
1931 | i.tm.base_opcode ^= 4; | |
1932 | } | |
252b5132 RH |
1933 | } |
1934 | ||
3f4438ab | 1935 | if (i.tm.opcode_modifier & ImmExt) |
252b5132 | 1936 | { |
3f4438ab AM |
1937 | /* These AMD 3DNow! and Intel Katmai New Instructions have an |
1938 | opcode suffix which is coded in the same place as an 8-bit | |
1939 | immediate field would be. Here we fake an 8-bit immediate | |
1940 | operand from the opcode suffix stored in tm.extension_opcode. */ | |
252b5132 RH |
1941 | |
1942 | expressionS *exp; | |
1943 | ||
47926f60 | 1944 | assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS); |
252b5132 RH |
1945 | |
1946 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 1947 | i.op[i.operands].imms = exp; |
252b5132 RH |
1948 | i.types[i.operands++] = Imm8; |
1949 | exp->X_op = O_constant; | |
1950 | exp->X_add_number = i.tm.extension_opcode; | |
1951 | i.tm.extension_opcode = None; | |
1952 | } | |
1953 | ||
47926f60 | 1954 | /* For insns with operands there are more diddles to do to the opcode. */ |
252b5132 RH |
1955 | if (i.operands) |
1956 | { | |
24eab124 | 1957 | /* Default segment register this instruction will use |
252b5132 RH |
1958 | for memory accesses. 0 means unknown. |
1959 | This is only for optimizing out unnecessary segment overrides. */ | |
1960 | const seg_entry *default_seg = 0; | |
1961 | ||
252b5132 RH |
1962 | /* The imul $imm, %reg instruction is converted into |
1963 | imul $imm, %reg, %reg, and the clr %reg instruction | |
1964 | is converted into xor %reg, %reg. */ | |
1965 | if (i.tm.opcode_modifier & regKludge) | |
1966 | { | |
1967 | unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1; | |
47926f60 KH |
1968 | /* Pretend we saw the extra register operand. */ |
1969 | assert (i.op[first_reg_op + 1].regs == 0); | |
1970 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; | |
1971 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
252b5132 RH |
1972 | i.reg_operands = 2; |
1973 | } | |
1974 | ||
1975 | if (i.tm.opcode_modifier & ShortForm) | |
1976 | { | |
47926f60 | 1977 | /* The register or float register operand is in operand 0 or 1. */ |
252b5132 | 1978 | unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1; |
47926f60 | 1979 | /* Register goes in low 3 bits of opcode. */ |
520dc8e8 | 1980 | i.tm.base_opcode |= i.op[op].regs->reg_num; |
a38cf1db | 1981 | if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0) |
252b5132 RH |
1982 | { |
1983 | /* Warn about some common errors, but press on regardless. | |
1984 | The first case can be generated by gcc (<= 2.8.1). */ | |
1985 | if (i.operands == 2) | |
1986 | { | |
47926f60 | 1987 | /* Reversed arguments on faddp, fsubp, etc. */ |
252b5132 | 1988 | as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name, |
520dc8e8 AM |
1989 | i.op[1].regs->reg_name, |
1990 | i.op[0].regs->reg_name); | |
252b5132 RH |
1991 | } |
1992 | else | |
1993 | { | |
47926f60 | 1994 | /* Extraneous `l' suffix on fp insn. */ |
252b5132 | 1995 | as_warn (_("translating to `%s %%%s'"), i.tm.name, |
520dc8e8 | 1996 | i.op[0].regs->reg_name); |
252b5132 RH |
1997 | } |
1998 | } | |
1999 | } | |
2000 | else if (i.tm.opcode_modifier & Modrm) | |
2001 | { | |
2002 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
2003 | must be put into the modrm byte). | |
2004 | Now, we make the modrm & index base bytes based on all the | |
47926f60 | 2005 | info we've collected. */ |
252b5132 RH |
2006 | |
2007 | /* i.reg_operands MUST be the number of real register operands; | |
47926f60 | 2008 | implicit registers do not count. */ |
252b5132 RH |
2009 | if (i.reg_operands == 2) |
2010 | { | |
2011 | unsigned int source, dest; | |
2012 | source = ((i.types[0] | |
3f4438ab AM |
2013 | & (Reg | RegMMX | RegXMM |
2014 | | SReg2 | SReg3 | |
2015 | | Control | Debug | Test)) | |
252b5132 RH |
2016 | ? 0 : 1); |
2017 | dest = source + 1; | |
2018 | ||
252b5132 | 2019 | i.rm.mode = 3; |
3f4438ab AM |
2020 | /* One of the register operands will be encoded in the |
2021 | i.tm.reg field, the other in the combined i.tm.mode | |
2022 | and i.tm.regmem fields. If no form of this | |
2023 | instruction supports a memory destination operand, | |
2024 | then we assume the source operand may sometimes be | |
2025 | a memory operand and so we need to store the | |
2026 | destination in the i.rm.reg field. */ | |
2027 | if ((i.tm.operand_types[dest] & AnyMem) == 0) | |
252b5132 | 2028 | { |
520dc8e8 AM |
2029 | i.rm.reg = i.op[dest].regs->reg_num; |
2030 | i.rm.regmem = i.op[source].regs->reg_num; | |
252b5132 RH |
2031 | } |
2032 | else | |
2033 | { | |
520dc8e8 AM |
2034 | i.rm.reg = i.op[source].regs->reg_num; |
2035 | i.rm.regmem = i.op[dest].regs->reg_num; | |
252b5132 RH |
2036 | } |
2037 | } | |
2038 | else | |
47926f60 | 2039 | { /* If it's not 2 reg operands... */ |
252b5132 RH |
2040 | if (i.mem_operands) |
2041 | { | |
2042 | unsigned int fake_zero_displacement = 0; | |
2043 | unsigned int op = ((i.types[0] & AnyMem) | |
2044 | ? 0 | |
2045 | : (i.types[1] & AnyMem) ? 1 : 2); | |
2046 | ||
2047 | default_seg = &ds; | |
2048 | ||
2049 | if (! i.base_reg) | |
2050 | { | |
2051 | i.rm.mode = 0; | |
2052 | if (! i.disp_operands) | |
2053 | fake_zero_displacement = 1; | |
2054 | if (! i.index_reg) | |
2055 | { | |
47926f60 | 2056 | /* Operand is just <disp> */ |
252b5132 RH |
2057 | if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0)) |
2058 | { | |
2059 | i.rm.regmem = NO_BASE_REGISTER_16; | |
2060 | i.types[op] &= ~Disp; | |
2061 | i.types[op] |= Disp16; | |
2062 | } | |
2063 | else | |
2064 | { | |
2065 | i.rm.regmem = NO_BASE_REGISTER; | |
2066 | i.types[op] &= ~Disp; | |
2067 | i.types[op] |= Disp32; | |
2068 | } | |
2069 | } | |
47926f60 | 2070 | else /* ! i.base_reg && i.index_reg */ |
252b5132 RH |
2071 | { |
2072 | i.sib.index = i.index_reg->reg_num; | |
2073 | i.sib.base = NO_BASE_REGISTER; | |
2074 | i.sib.scale = i.log2_scale_factor; | |
2075 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
2076 | i.types[op] &= ~Disp; | |
47926f60 | 2077 | i.types[op] |= Disp32; /* Must be 32 bit. */ |
252b5132 RH |
2078 | } |
2079 | } | |
2080 | else if (i.base_reg->reg_type & Reg16) | |
2081 | { | |
2082 | switch (i.base_reg->reg_num) | |
2083 | { | |
47926f60 | 2084 | case 3: /* (%bx) */ |
252b5132 RH |
2085 | if (! i.index_reg) |
2086 | i.rm.regmem = 7; | |
47926f60 | 2087 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ |
252b5132 RH |
2088 | i.rm.regmem = i.index_reg->reg_num - 6; |
2089 | break; | |
47926f60 | 2090 | case 5: /* (%bp) */ |
252b5132 RH |
2091 | default_seg = &ss; |
2092 | if (! i.index_reg) | |
2093 | { | |
2094 | i.rm.regmem = 6; | |
2095 | if ((i.types[op] & Disp) == 0) | |
2096 | { | |
47926f60 | 2097 | /* fake (%bp) into 0(%bp) */ |
252b5132 RH |
2098 | i.types[op] |= Disp8; |
2099 | fake_zero_displacement = 1; | |
2100 | } | |
2101 | } | |
47926f60 | 2102 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ |
252b5132 RH |
2103 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; |
2104 | break; | |
47926f60 | 2105 | default: /* (%si) -> 4 or (%di) -> 5 */ |
252b5132 RH |
2106 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; |
2107 | } | |
2108 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
2109 | } | |
47926f60 | 2110 | else /* i.base_reg and 32 bit mode */ |
252b5132 RH |
2111 | { |
2112 | i.rm.regmem = i.base_reg->reg_num; | |
2113 | i.sib.base = i.base_reg->reg_num; | |
2114 | if (i.base_reg->reg_num == EBP_REG_NUM) | |
2115 | { | |
2116 | default_seg = &ss; | |
2117 | if (i.disp_operands == 0) | |
2118 | { | |
2119 | fake_zero_displacement = 1; | |
2120 | i.types[op] |= Disp8; | |
2121 | } | |
2122 | } | |
2123 | else if (i.base_reg->reg_num == ESP_REG_NUM) | |
2124 | { | |
2125 | default_seg = &ss; | |
2126 | } | |
2127 | i.sib.scale = i.log2_scale_factor; | |
2128 | if (! i.index_reg) | |
2129 | { | |
2130 | /* <disp>(%esp) becomes two byte modrm | |
2131 | with no index register. We've already | |
2132 | stored the code for esp in i.rm.regmem | |
2133 | ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any | |
2134 | base register besides %esp will not use | |
2135 | the extra modrm byte. */ | |
2136 | i.sib.index = NO_INDEX_REGISTER; | |
2137 | #if ! SCALE1_WHEN_NO_INDEX | |
2138 | /* Another case where we force the second | |
2139 | modrm byte. */ | |
2140 | if (i.log2_scale_factor) | |
2141 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
2142 | #endif | |
2143 | } | |
2144 | else | |
2145 | { | |
2146 | i.sib.index = i.index_reg->reg_num; | |
2147 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
2148 | } | |
2149 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
2150 | } | |
2151 | ||
2152 | if (fake_zero_displacement) | |
2153 | { | |
2154 | /* Fakes a zero displacement assuming that i.types[op] | |
47926f60 | 2155 | holds the correct displacement size. */ |
b4cac588 AM |
2156 | expressionS *exp; |
2157 | ||
520dc8e8 | 2158 | assert (i.op[op].disps == 0); |
252b5132 | 2159 | exp = &disp_expressions[i.disp_operands++]; |
520dc8e8 | 2160 | i.op[op].disps = exp; |
252b5132 RH |
2161 | exp->X_op = O_constant; |
2162 | exp->X_add_number = 0; | |
2163 | exp->X_add_symbol = (symbolS *) 0; | |
2164 | exp->X_op_symbol = (symbolS *) 0; | |
2165 | } | |
2166 | } | |
2167 | ||
2168 | /* Fill in i.rm.reg or i.rm.regmem field with register | |
2169 | operand (if any) based on i.tm.extension_opcode. | |
2170 | Again, we must be careful to make sure that | |
2171 | segment/control/debug/test/MMX registers are coded | |
47926f60 | 2172 | into the i.rm.reg field. */ |
252b5132 RH |
2173 | if (i.reg_operands) |
2174 | { | |
2175 | unsigned int op = | |
2176 | ((i.types[0] | |
3f4438ab AM |
2177 | & (Reg | RegMMX | RegXMM |
2178 | | SReg2 | SReg3 | |
2179 | | Control | Debug | Test)) | |
252b5132 RH |
2180 | ? 0 |
2181 | : ((i.types[1] | |
3f4438ab AM |
2182 | & (Reg | RegMMX | RegXMM |
2183 | | SReg2 | SReg3 | |
2184 | | Control | Debug | Test)) | |
252b5132 RH |
2185 | ? 1 |
2186 | : 2)); | |
2187 | /* If there is an extension opcode to put here, the | |
47926f60 | 2188 | register number must be put into the regmem field. */ |
252b5132 | 2189 | if (i.tm.extension_opcode != None) |
520dc8e8 | 2190 | i.rm.regmem = i.op[op].regs->reg_num; |
252b5132 | 2191 | else |
520dc8e8 | 2192 | i.rm.reg = i.op[op].regs->reg_num; |
252b5132 RH |
2193 | |
2194 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 | |
2195 | we must set it to 3 to indicate this is a register | |
2196 | operand in the regmem field. */ | |
2197 | if (!i.mem_operands) | |
2198 | i.rm.mode = 3; | |
2199 | } | |
2200 | ||
47926f60 | 2201 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
252b5132 RH |
2202 | if (i.tm.extension_opcode != None) |
2203 | i.rm.reg = i.tm.extension_opcode; | |
2204 | } | |
2205 | } | |
2206 | else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm)) | |
2207 | { | |
47926f60 KH |
2208 | if (i.tm.base_opcode == POP_SEG_SHORT |
2209 | && i.op[0].regs->reg_num == 1) | |
252b5132 RH |
2210 | { |
2211 | as_bad (_("you can't `pop %%cs'")); | |
2212 | return; | |
2213 | } | |
520dc8e8 | 2214 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); |
252b5132 RH |
2215 | } |
2216 | else if ((i.tm.base_opcode & ~(D|W)) == MOV_AX_DISP32) | |
2217 | { | |
2218 | default_seg = &ds; | |
2219 | } | |
2220 | else if ((i.tm.opcode_modifier & IsString) != 0) | |
2221 | { | |
2222 | /* For the string instructions that allow a segment override | |
2223 | on one of their operands, the default segment is ds. */ | |
2224 | default_seg = &ds; | |
2225 | } | |
2226 | ||
2227 | /* If a segment was explicitly specified, | |
2228 | and the specified segment is not the default, | |
2229 | use an opcode prefix to select it. | |
2230 | If we never figured out what the default segment is, | |
2231 | then default_seg will be zero at this point, | |
2232 | and the specified segment prefix will always be used. */ | |
2233 | if ((i.seg[0]) && (i.seg[0] != default_seg)) | |
2234 | { | |
2235 | if (! add_prefix (i.seg[0]->seg_prefix)) | |
2236 | return; | |
2237 | } | |
2238 | } | |
a38cf1db | 2239 | else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0) |
252b5132 | 2240 | { |
24eab124 AM |
2241 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ |
2242 | as_warn (_("translating to `%sp'"), i.tm.name); | |
252b5132 RH |
2243 | } |
2244 | } | |
2245 | ||
47926f60 | 2246 | /* Handle conversion of 'int $3' --> special int3 insn. */ |
520dc8e8 | 2247 | if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3) |
252b5132 RH |
2248 | { |
2249 | i.tm.base_opcode = INT3_OPCODE; | |
2250 | i.imm_operands = 0; | |
2251 | } | |
2252 | ||
2f66722d | 2253 | if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword)) |
520dc8e8 | 2254 | && i.op[0].disps->X_op == O_constant) |
2f66722d AM |
2255 | { |
2256 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
2257 | the absolute address given by the constant. Since ix86 jumps and | |
2258 | calls are pc relative, we need to generate a reloc. */ | |
520dc8e8 AM |
2259 | i.op[0].disps->X_add_symbol = &abs_symbol; |
2260 | i.op[0].disps->X_op = O_symbol; | |
2f66722d AM |
2261 | } |
2262 | ||
47926f60 | 2263 | /* We are ready to output the insn. */ |
252b5132 RH |
2264 | { |
2265 | register char *p; | |
2266 | ||
47926f60 | 2267 | /* Output jumps. */ |
252b5132 RH |
2268 | if (i.tm.opcode_modifier & Jump) |
2269 | { | |
a217f122 AM |
2270 | int size; |
2271 | int code16; | |
2272 | int prefix; | |
252b5132 | 2273 | |
a217f122 AM |
2274 | code16 = 0; |
2275 | if (flag_16bit_code) | |
2276 | code16 = CODE16; | |
2277 | ||
2278 | prefix = 0; | |
2279 | if (i.prefix[DATA_PREFIX]) | |
252b5132 | 2280 | { |
a217f122 | 2281 | prefix = 1; |
252b5132 | 2282 | i.prefixes -= 1; |
a217f122 | 2283 | code16 ^= CODE16; |
252b5132 | 2284 | } |
252b5132 | 2285 | |
a217f122 AM |
2286 | size = 4; |
2287 | if (code16) | |
2288 | size = 2; | |
2289 | ||
2290 | if (i.prefixes != 0 && !intel_syntax) | |
252b5132 RH |
2291 | as_warn (_("skipping prefixes on this instruction")); |
2292 | ||
2f66722d AM |
2293 | /* It's always a symbol; End frag & setup for relax. |
2294 | Make sure there is enough room in this frag for the largest | |
2295 | instruction we may generate in md_convert_frag. This is 2 | |
2296 | bytes for the opcode and room for the prefix and largest | |
2297 | displacement. */ | |
2298 | frag_grow (prefix + 2 + size); | |
2299 | insn_size += prefix + 1; | |
2300 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
2301 | p = frag_more (prefix + 1); | |
2302 | if (prefix) | |
2303 | *p++ = DATA_PREFIX_OPCODE; | |
2304 | *p = i.tm.base_opcode; | |
ee7fcc42 AM |
2305 | /* 1 possible extra opcode + displacement go in var part. |
2306 | Pass reloc in fr_var. */ | |
2f66722d AM |
2307 | frag_var (rs_machine_dependent, |
2308 | 1 + size, | |
ee7fcc42 | 2309 | i.disp_reloc[0], |
2f66722d AM |
2310 | ((unsigned char) *p == JUMP_PC_RELATIVE |
2311 | ? ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL) | code16 | |
2312 | : ENCODE_RELAX_STATE (COND_JUMP, SMALL) | code16), | |
520dc8e8 AM |
2313 | i.op[0].disps->X_add_symbol, |
2314 | i.op[0].disps->X_add_number, | |
2f66722d | 2315 | p); |
252b5132 RH |
2316 | } |
2317 | else if (i.tm.opcode_modifier & (JumpByte | JumpDword)) | |
2318 | { | |
a217f122 | 2319 | int size; |
252b5132 | 2320 | |
a217f122 | 2321 | if (i.tm.opcode_modifier & JumpByte) |
252b5132 | 2322 | { |
a217f122 AM |
2323 | /* This is a loop or jecxz type instruction. */ |
2324 | size = 1; | |
252b5132 RH |
2325 | if (i.prefix[ADDR_PREFIX]) |
2326 | { | |
2327 | insn_size += 1; | |
2328 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); | |
2329 | i.prefixes -= 1; | |
2330 | } | |
2331 | } | |
2332 | else | |
2333 | { | |
a217f122 AM |
2334 | int code16; |
2335 | ||
2336 | code16 = 0; | |
2337 | if (flag_16bit_code) | |
2338 | code16 = CODE16; | |
252b5132 RH |
2339 | |
2340 | if (i.prefix[DATA_PREFIX]) | |
2341 | { | |
2342 | insn_size += 1; | |
2343 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); | |
2344 | i.prefixes -= 1; | |
a217f122 | 2345 | code16 ^= CODE16; |
252b5132 | 2346 | } |
252b5132 | 2347 | |
a217f122 | 2348 | size = 4; |
252b5132 RH |
2349 | if (code16) |
2350 | size = 2; | |
2351 | } | |
2352 | ||
a217f122 | 2353 | if (i.prefixes != 0 && !intel_syntax) |
252b5132 RH |
2354 | as_warn (_("skipping prefixes on this instruction")); |
2355 | ||
2356 | if (fits_in_unsigned_byte (i.tm.base_opcode)) | |
2357 | { | |
2358 | insn_size += 1 + size; | |
2359 | p = frag_more (1 + size); | |
2360 | } | |
2361 | else | |
2362 | { | |
47926f60 | 2363 | /* Opcode can be at most two bytes. */ |
a217f122 | 2364 | insn_size += 2 + size; |
252b5132 RH |
2365 | p = frag_more (2 + size); |
2366 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
2367 | } | |
2368 | *p++ = i.tm.base_opcode & 0xff; | |
2369 | ||
2f66722d | 2370 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
520dc8e8 | 2371 | i.op[0].disps, 1, reloc (size, 1, i.disp_reloc[0])); |
252b5132 RH |
2372 | } |
2373 | else if (i.tm.opcode_modifier & JumpInterSegment) | |
2374 | { | |
2375 | int size; | |
a217f122 AM |
2376 | int prefix; |
2377 | int code16; | |
252b5132 | 2378 | |
a217f122 AM |
2379 | code16 = 0; |
2380 | if (flag_16bit_code) | |
2381 | code16 = CODE16; | |
2382 | ||
2383 | prefix = 0; | |
2384 | if (i.prefix[DATA_PREFIX]) | |
252b5132 | 2385 | { |
a217f122 | 2386 | prefix = 1; |
252b5132 | 2387 | i.prefixes -= 1; |
a217f122 | 2388 | code16 ^= CODE16; |
252b5132 | 2389 | } |
252b5132 RH |
2390 | |
2391 | size = 4; | |
252b5132 | 2392 | if (code16) |
f6af82bd | 2393 | size = 2; |
252b5132 | 2394 | |
a217f122 | 2395 | if (i.prefixes != 0 && !intel_syntax) |
252b5132 RH |
2396 | as_warn (_("skipping prefixes on this instruction")); |
2397 | ||
47926f60 KH |
2398 | /* 1 opcode; 2 segment; offset */ |
2399 | insn_size += prefix + 1 + 2 + size; | |
252b5132 RH |
2400 | p = frag_more (prefix + 1 + 2 + size); |
2401 | if (prefix) | |
2402 | *p++ = DATA_PREFIX_OPCODE; | |
2403 | *p++ = i.tm.base_opcode; | |
520dc8e8 | 2404 | if (i.op[1].imms->X_op == O_constant) |
252b5132 | 2405 | { |
847f7ad4 | 2406 | offsetT n = i.op[1].imms->X_add_number; |
252b5132 | 2407 | |
773f551c AM |
2408 | if (size == 2 |
2409 | && !fits_in_unsigned_word (n) | |
2410 | && !fits_in_signed_word (n)) | |
252b5132 RH |
2411 | { |
2412 | as_bad (_("16-bit jump out of range")); | |
2413 | return; | |
2414 | } | |
847f7ad4 | 2415 | md_number_to_chars (p, n, size); |
252b5132 RH |
2416 | } |
2417 | else | |
2418 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
520dc8e8 AM |
2419 | i.op[1].imms, 0, reloc (size, 0, i.disp_reloc[0])); |
2420 | if (i.op[0].imms->X_op != O_constant) | |
252b5132 RH |
2421 | as_bad (_("can't handle non absolute segment in `%s'"), |
2422 | i.tm.name); | |
520dc8e8 | 2423 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); |
252b5132 RH |
2424 | } |
2425 | else | |
2426 | { | |
47926f60 | 2427 | /* Output normal instructions here. */ |
252b5132 RH |
2428 | unsigned char *q; |
2429 | ||
47926f60 | 2430 | /* The prefix bytes. */ |
252b5132 RH |
2431 | for (q = i.prefix; |
2432 | q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]); | |
2433 | q++) | |
2434 | { | |
2435 | if (*q) | |
2436 | { | |
2437 | insn_size += 1; | |
2438 | p = frag_more (1); | |
2439 | md_number_to_chars (p, (valueT) *q, 1); | |
2440 | } | |
2441 | } | |
2442 | ||
47926f60 | 2443 | /* Now the opcode; be careful about word order here! */ |
252b5132 RH |
2444 | if (fits_in_unsigned_byte (i.tm.base_opcode)) |
2445 | { | |
2446 | insn_size += 1; | |
2447 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
2448 | } | |
2449 | else if (fits_in_unsigned_word (i.tm.base_opcode)) | |
2450 | { | |
2451 | insn_size += 2; | |
2452 | p = frag_more (2); | |
47926f60 | 2453 | /* Put out high byte first: can't use md_number_to_chars! */ |
252b5132 RH |
2454 | *p++ = (i.tm.base_opcode >> 8) & 0xff; |
2455 | *p = i.tm.base_opcode & 0xff; | |
2456 | } | |
2457 | else | |
47926f60 | 2458 | { /* Opcode is either 3 or 4 bytes. */ |
252b5132 RH |
2459 | if (i.tm.base_opcode & 0xff000000) |
2460 | { | |
2461 | insn_size += 4; | |
2462 | p = frag_more (4); | |
2463 | *p++ = (i.tm.base_opcode >> 24) & 0xff; | |
2464 | } | |
2465 | else | |
2466 | { | |
2467 | insn_size += 3; | |
2468 | p = frag_more (3); | |
2469 | } | |
2470 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
2471 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
2472 | *p = (i.tm.base_opcode) & 0xff; | |
2473 | } | |
2474 | ||
2475 | /* Now the modrm byte and sib byte (if present). */ | |
2476 | if (i.tm.opcode_modifier & Modrm) | |
2477 | { | |
2478 | insn_size += 1; | |
2479 | p = frag_more (1); | |
2480 | md_number_to_chars (p, | |
2481 | (valueT) (i.rm.regmem << 0 | |
2482 | | i.rm.reg << 3 | |
2483 | | i.rm.mode << 6), | |
2484 | 1); | |
2485 | /* If i.rm.regmem == ESP (4) | |
2486 | && i.rm.mode != (Register mode) | |
2487 | && not 16 bit | |
2488 | ==> need second modrm byte. */ | |
2489 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
2490 | && i.rm.mode != 3 | |
2491 | && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0)) | |
2492 | { | |
2493 | insn_size += 1; | |
2494 | p = frag_more (1); | |
2495 | md_number_to_chars (p, | |
2496 | (valueT) (i.sib.base << 0 | |
2497 | | i.sib.index << 3 | |
2498 | | i.sib.scale << 6), | |
2499 | 1); | |
2500 | } | |
2501 | } | |
2502 | ||
2503 | if (i.disp_operands) | |
2504 | { | |
2505 | register unsigned int n; | |
2506 | ||
2507 | for (n = 0; n < i.operands; n++) | |
2508 | { | |
520dc8e8 | 2509 | if (i.types[n] & Disp) |
252b5132 | 2510 | { |
520dc8e8 | 2511 | if (i.op[n].disps->X_op == O_constant) |
252b5132 | 2512 | { |
847f7ad4 AM |
2513 | int size; |
2514 | offsetT val; | |
b4cac588 | 2515 | |
847f7ad4 | 2516 | size = 4; |
b4cac588 | 2517 | if (i.types[n] & (Disp8 | Disp16)) |
252b5132 | 2518 | { |
b4cac588 | 2519 | size = 2; |
b4cac588 | 2520 | if (i.types[n] & Disp8) |
847f7ad4 | 2521 | size = 1; |
252b5132 | 2522 | } |
847f7ad4 AM |
2523 | val = offset_in_range (i.op[n].disps->X_add_number, |
2524 | size); | |
b4cac588 AM |
2525 | insn_size += size; |
2526 | p = frag_more (size); | |
847f7ad4 | 2527 | md_number_to_chars (p, val, size); |
252b5132 | 2528 | } |
252b5132 | 2529 | else |
520dc8e8 AM |
2530 | { |
2531 | int size = 4; | |
2532 | ||
2533 | if (i.types[n] & Disp16) | |
2534 | size = 2; | |
2535 | ||
2536 | insn_size += size; | |
2537 | p = frag_more (size); | |
2538 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
2539 | i.op[n].disps, 0, | |
2540 | reloc (size, 0, i.disp_reloc[n])); | |
252b5132 RH |
2541 | } |
2542 | } | |
2543 | } | |
ce8a8b2f | 2544 | } |
252b5132 | 2545 | |
47926f60 | 2546 | /* Output immediate. */ |
252b5132 RH |
2547 | if (i.imm_operands) |
2548 | { | |
2549 | register unsigned int n; | |
2550 | ||
2551 | for (n = 0; n < i.operands; n++) | |
2552 | { | |
520dc8e8 | 2553 | if (i.types[n] & Imm) |
252b5132 | 2554 | { |
520dc8e8 | 2555 | if (i.op[n].imms->X_op == O_constant) |
252b5132 | 2556 | { |
847f7ad4 AM |
2557 | int size; |
2558 | offsetT val; | |
b4cac588 | 2559 | |
847f7ad4 | 2560 | size = 4; |
b4cac588 | 2561 | if (i.types[n] & (Imm8 | Imm8S | Imm16)) |
252b5132 | 2562 | { |
b4cac588 | 2563 | size = 2; |
b4cac588 | 2564 | if (i.types[n] & (Imm8 | Imm8S)) |
847f7ad4 | 2565 | size = 1; |
252b5132 | 2566 | } |
847f7ad4 AM |
2567 | val = offset_in_range (i.op[n].imms->X_add_number, |
2568 | size); | |
b4cac588 AM |
2569 | insn_size += size; |
2570 | p = frag_more (size); | |
847f7ad4 | 2571 | md_number_to_chars (p, val, size); |
252b5132 RH |
2572 | } |
2573 | else | |
ce8a8b2f AM |
2574 | { |
2575 | /* Not absolute_section. | |
2576 | Need a 32-bit fixup (don't support 8bit | |
520dc8e8 | 2577 | non-absolute imms). Try to support other |
47926f60 | 2578 | sizes ... */ |
f6af82bd AM |
2579 | #ifdef BFD_ASSEMBLER |
2580 | enum bfd_reloc_code_real reloc_type; | |
2581 | #else | |
2582 | int reloc_type; | |
2583 | #endif | |
520dc8e8 | 2584 | int size = 4; |
252b5132 | 2585 | |
520dc8e8 | 2586 | if (i.types[n] & Imm16) |
252b5132 | 2587 | size = 2; |
520dc8e8 AM |
2588 | else if (i.types[n] & (Imm8 | Imm8S)) |
2589 | size = 1; | |
2590 | ||
252b5132 RH |
2591 | insn_size += size; |
2592 | p = frag_more (size); | |
f6af82bd | 2593 | reloc_type = reloc (size, 0, i.disp_reloc[0]); |
252b5132 | 2594 | #ifdef BFD_ASSEMBLER |
f6af82bd | 2595 | if (reloc_type == BFD_RELOC_32 |
252b5132 | 2596 | && GOT_symbol |
520dc8e8 AM |
2597 | && GOT_symbol == i.op[n].imms->X_add_symbol |
2598 | && (i.op[n].imms->X_op == O_symbol | |
2599 | || (i.op[n].imms->X_op == O_add | |
49309057 | 2600 | && ((symbol_get_value_expression |
520dc8e8 | 2601 | (i.op[n].imms->X_op_symbol)->X_op) |
252b5132 RH |
2602 | == O_subtract)))) |
2603 | { | |
f6af82bd | 2604 | reloc_type = BFD_RELOC_386_GOTPC; |
520dc8e8 | 2605 | i.op[n].imms->X_add_number += 3; |
252b5132 RH |
2606 | } |
2607 | #endif | |
2608 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
520dc8e8 | 2609 | i.op[n].imms, 0, reloc_type); |
252b5132 RH |
2610 | } |
2611 | } | |
2612 | } | |
ce8a8b2f | 2613 | } |
252b5132 RH |
2614 | } |
2615 | ||
2616 | #ifdef DEBUG386 | |
2617 | if (flag_debug) | |
2618 | { | |
2619 | pi (line, &i); | |
2620 | } | |
47926f60 | 2621 | #endif /* DEBUG386 */ |
252b5132 RH |
2622 | } |
2623 | } | |
2624 | \f | |
252b5132 RH |
2625 | static int i386_immediate PARAMS ((char *)); |
2626 | ||
2627 | static int | |
2628 | i386_immediate (imm_start) | |
2629 | char *imm_start; | |
2630 | { | |
2631 | char *save_input_line_pointer; | |
2632 | segT exp_seg = 0; | |
47926f60 | 2633 | expressionS *exp; |
252b5132 RH |
2634 | |
2635 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
2636 | { | |
d0b47220 | 2637 | as_bad (_("only 1 or 2 immediate operands are allowed")); |
252b5132 RH |
2638 | return 0; |
2639 | } | |
2640 | ||
2641 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 2642 | i.op[this_operand].imms = exp; |
252b5132 RH |
2643 | |
2644 | if (is_space_char (*imm_start)) | |
2645 | ++imm_start; | |
2646 | ||
2647 | save_input_line_pointer = input_line_pointer; | |
2648 | input_line_pointer = imm_start; | |
2649 | ||
2650 | #ifndef LEX_AT | |
24eab124 | 2651 | { |
47926f60 KH |
2652 | /* We can have operands of the form |
2653 | <symbol>@GOTOFF+<nnn> | |
2654 | Take the easy way out here and copy everything | |
2655 | into a temporary buffer... */ | |
24eab124 AM |
2656 | register char *cp; |
2657 | ||
2658 | cp = strchr (input_line_pointer, '@'); | |
2659 | if (cp != NULL) | |
2660 | { | |
2661 | char *tmpbuf; | |
2662 | int len = 0; | |
2663 | int first; | |
2664 | ||
47926f60 | 2665 | /* GOT relocations are not supported in 16 bit mode. */ |
24eab124 AM |
2666 | if (flag_16bit_code) |
2667 | as_bad (_("GOT relocations not supported in 16 bit mode")); | |
2668 | ||
2669 | if (GOT_symbol == NULL) | |
2670 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); | |
2671 | ||
2672 | if (strncmp (cp + 1, "PLT", 3) == 0) | |
2673 | { | |
2674 | i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32; | |
2675 | len = 3; | |
2676 | } | |
2677 | else if (strncmp (cp + 1, "GOTOFF", 6) == 0) | |
2678 | { | |
2679 | i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF; | |
2680 | len = 6; | |
2681 | } | |
2682 | else if (strncmp (cp + 1, "GOT", 3) == 0) | |
2683 | { | |
2684 | i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32; | |
2685 | len = 3; | |
2686 | } | |
2687 | else | |
d0b47220 | 2688 | as_bad (_("bad reloc specifier in expression")); |
24eab124 AM |
2689 | |
2690 | /* Replace the relocation token with ' ', so that errors like | |
2691 | foo@GOTOFF1 will be detected. */ | |
2692 | first = cp - input_line_pointer; | |
47926f60 | 2693 | tmpbuf = (char *) alloca (strlen (input_line_pointer)); |
24eab124 AM |
2694 | memcpy (tmpbuf, input_line_pointer, first); |
2695 | tmpbuf[first] = ' '; | |
2696 | strcpy (tmpbuf + first + 1, cp + 1 + len); | |
2697 | input_line_pointer = tmpbuf; | |
2698 | } | |
2699 | } | |
252b5132 RH |
2700 | #endif |
2701 | ||
2702 | exp_seg = expression (exp); | |
2703 | ||
83183c0c | 2704 | SKIP_WHITESPACE (); |
252b5132 | 2705 | if (*input_line_pointer) |
d0b47220 | 2706 | as_bad (_("ignoring junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
2707 | |
2708 | input_line_pointer = save_input_line_pointer; | |
2709 | ||
2daf4fd8 | 2710 | if (exp->X_op == O_absent || exp->X_op == O_big) |
252b5132 | 2711 | { |
47926f60 | 2712 | /* Missing or bad expr becomes absolute 0. */ |
d0b47220 | 2713 | as_bad (_("missing or invalid immediate expression `%s' taken as 0"), |
24eab124 | 2714 | imm_start); |
252b5132 RH |
2715 | exp->X_op = O_constant; |
2716 | exp->X_add_number = 0; | |
2717 | exp->X_add_symbol = (symbolS *) 0; | |
2718 | exp->X_op_symbol = (symbolS *) 0; | |
252b5132 | 2719 | } |
2daf4fd8 AM |
2720 | |
2721 | if (exp->X_op == O_constant) | |
252b5132 | 2722 | { |
47926f60 KH |
2723 | /* Size it properly later. */ |
2724 | i.types[this_operand] |= Imm32; | |
252b5132 | 2725 | } |
4c63da97 | 2726 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
47926f60 | 2727 | else if (1 |
4c63da97 | 2728 | #ifdef BFD_ASSEMBLER |
47926f60 | 2729 | && OUTPUT_FLAVOR == bfd_target_aout_flavour |
4c63da97 | 2730 | #endif |
47926f60 | 2731 | && exp_seg != text_section |
24eab124 AM |
2732 | && exp_seg != data_section |
2733 | && exp_seg != bss_section | |
2734 | && exp_seg != undefined_section | |
252b5132 | 2735 | #ifdef BFD_ASSEMBLER |
24eab124 | 2736 | && !bfd_is_com_section (exp_seg) |
252b5132 | 2737 | #endif |
24eab124 | 2738 | ) |
252b5132 | 2739 | { |
4c63da97 | 2740 | #ifdef BFD_ASSEMBLER |
d0b47220 | 2741 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
4c63da97 | 2742 | #else |
d0b47220 | 2743 | as_bad (_("unimplemented segment type %d in operand"), exp_seg); |
4c63da97 | 2744 | #endif |
252b5132 RH |
2745 | return 0; |
2746 | } | |
2747 | #endif | |
2748 | else | |
2749 | { | |
2750 | /* This is an address. The size of the address will be | |
24eab124 AM |
2751 | determined later, depending on destination register, |
2752 | suffix, or the default for the section. We exclude | |
2753 | Imm8S here so that `push $foo' and other instructions | |
2754 | with an Imm8S form will use Imm16 or Imm32. */ | |
252b5132 RH |
2755 | i.types[this_operand] |= (Imm8 | Imm16 | Imm32); |
2756 | } | |
2757 | ||
2758 | return 1; | |
2759 | } | |
2760 | ||
2761 | static int i386_scale PARAMS ((char *)); | |
2762 | ||
2763 | static int | |
2764 | i386_scale (scale) | |
2765 | char *scale; | |
2766 | { | |
2767 | if (!isdigit (*scale)) | |
2768 | goto bad_scale; | |
2769 | ||
2770 | switch (*scale) | |
2771 | { | |
2772 | case '0': | |
2773 | case '1': | |
2774 | i.log2_scale_factor = 0; | |
2775 | break; | |
2776 | case '2': | |
2777 | i.log2_scale_factor = 1; | |
2778 | break; | |
2779 | case '4': | |
2780 | i.log2_scale_factor = 2; | |
2781 | break; | |
2782 | case '8': | |
2783 | i.log2_scale_factor = 3; | |
2784 | break; | |
2785 | default: | |
2786 | bad_scale: | |
2787 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
24eab124 | 2788 | scale); |
252b5132 RH |
2789 | return 0; |
2790 | } | |
2791 | if (i.log2_scale_factor != 0 && ! i.index_reg) | |
2792 | { | |
2793 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 2794 | 1 << i.log2_scale_factor); |
252b5132 RH |
2795 | #if SCALE1_WHEN_NO_INDEX |
2796 | i.log2_scale_factor = 0; | |
2797 | #endif | |
2798 | } | |
2799 | return 1; | |
2800 | } | |
2801 | ||
2802 | static int i386_displacement PARAMS ((char *, char *)); | |
2803 | ||
2804 | static int | |
2805 | i386_displacement (disp_start, disp_end) | |
2806 | char *disp_start; | |
2807 | char *disp_end; | |
2808 | { | |
2809 | register expressionS *exp; | |
2810 | segT exp_seg = 0; | |
2811 | char *save_input_line_pointer; | |
2812 | int bigdisp = Disp32; | |
2813 | ||
252b5132 RH |
2814 | if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0)) |
2815 | bigdisp = Disp16; | |
2816 | i.types[this_operand] |= bigdisp; | |
2817 | ||
2818 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 2819 | i.op[this_operand].disps = exp; |
252b5132 RH |
2820 | i.disp_operands++; |
2821 | save_input_line_pointer = input_line_pointer; | |
2822 | input_line_pointer = disp_start; | |
2823 | END_STRING_AND_SAVE (disp_end); | |
2824 | ||
2825 | #ifndef GCC_ASM_O_HACK | |
2826 | #define GCC_ASM_O_HACK 0 | |
2827 | #endif | |
2828 | #if GCC_ASM_O_HACK | |
2829 | END_STRING_AND_SAVE (disp_end + 1); | |
2830 | if ((i.types[this_operand] & BaseIndex) != 0 | |
24eab124 | 2831 | && displacement_string_end[-1] == '+') |
252b5132 RH |
2832 | { |
2833 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
2834 | constraint within gcc asm statements. |
2835 | For instance: | |
2836 | ||
2837 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
2838 | __asm__ __volatile__ ( \ | |
2839 | "movw %w2,%0\n\t" \ | |
2840 | "movw %w1,2+%0\n\t" \ | |
2841 | "rorl $16,%1\n\t" \ | |
2842 | "movb %b1,4+%0\n\t" \ | |
2843 | "movb %4,5+%0\n\t" \ | |
2844 | "movb $0,6+%0\n\t" \ | |
2845 | "movb %h1,7+%0\n\t" \ | |
2846 | "rorl $16,%1" \ | |
2847 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
2848 | ||
2849 | This works great except that the output assembler ends | |
2850 | up looking a bit weird if it turns out that there is | |
2851 | no offset. You end up producing code that looks like: | |
2852 | ||
2853 | #APP | |
2854 | movw $235,(%eax) | |
2855 | movw %dx,2+(%eax) | |
2856 | rorl $16,%edx | |
2857 | movb %dl,4+(%eax) | |
2858 | movb $137,5+(%eax) | |
2859 | movb $0,6+(%eax) | |
2860 | movb %dh,7+(%eax) | |
2861 | rorl $16,%edx | |
2862 | #NO_APP | |
2863 | ||
47926f60 | 2864 | So here we provide the missing zero. */ |
24eab124 AM |
2865 | |
2866 | *displacement_string_end = '0'; | |
252b5132 RH |
2867 | } |
2868 | #endif | |
2869 | #ifndef LEX_AT | |
24eab124 | 2870 | { |
47926f60 KH |
2871 | /* We can have operands of the form |
2872 | <symbol>@GOTOFF+<nnn> | |
2873 | Take the easy way out here and copy everything | |
2874 | into a temporary buffer... */ | |
24eab124 AM |
2875 | register char *cp; |
2876 | ||
2877 | cp = strchr (input_line_pointer, '@'); | |
2878 | if (cp != NULL) | |
2879 | { | |
2880 | char *tmpbuf; | |
2881 | int len = 0; | |
2882 | int first; | |
2883 | ||
47926f60 | 2884 | /* GOT relocations are not supported in 16 bit mode. */ |
24eab124 AM |
2885 | if (flag_16bit_code) |
2886 | as_bad (_("GOT relocations not supported in 16 bit mode")); | |
2887 | ||
2888 | if (GOT_symbol == NULL) | |
2889 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); | |
2890 | ||
2891 | if (strncmp (cp + 1, "PLT", 3) == 0) | |
2892 | { | |
2893 | i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32; | |
2894 | len = 3; | |
2895 | } | |
2896 | else if (strncmp (cp + 1, "GOTOFF", 6) == 0) | |
2897 | { | |
2898 | i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF; | |
2899 | len = 6; | |
2900 | } | |
2901 | else if (strncmp (cp + 1, "GOT", 3) == 0) | |
2902 | { | |
2903 | i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32; | |
2904 | len = 3; | |
2905 | } | |
2906 | else | |
d0b47220 | 2907 | as_bad (_("bad reloc specifier in expression")); |
24eab124 AM |
2908 | |
2909 | /* Replace the relocation token with ' ', so that errors like | |
2910 | foo@GOTOFF1 will be detected. */ | |
2911 | first = cp - input_line_pointer; | |
47926f60 | 2912 | tmpbuf = (char *) alloca (strlen (input_line_pointer)); |
24eab124 AM |
2913 | memcpy (tmpbuf, input_line_pointer, first); |
2914 | tmpbuf[first] = ' '; | |
2915 | strcpy (tmpbuf + first + 1, cp + 1 + len); | |
2916 | input_line_pointer = tmpbuf; | |
2917 | } | |
2918 | } | |
252b5132 RH |
2919 | #endif |
2920 | ||
24eab124 | 2921 | exp_seg = expression (exp); |
252b5132 RH |
2922 | |
2923 | #ifdef BFD_ASSEMBLER | |
24eab124 AM |
2924 | /* We do this to make sure that the section symbol is in |
2925 | the symbol table. We will ultimately change the relocation | |
47926f60 | 2926 | to be relative to the beginning of the section. */ |
24eab124 AM |
2927 | if (i.disp_reloc[this_operand] == BFD_RELOC_386_GOTOFF) |
2928 | { | |
2929 | if (S_IS_LOCAL(exp->X_add_symbol) | |
2930 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section) | |
2931 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); | |
2932 | assert (exp->X_op == O_symbol); | |
2933 | exp->X_op = O_subtract; | |
2934 | exp->X_op_symbol = GOT_symbol; | |
2935 | i.disp_reloc[this_operand] = BFD_RELOC_32; | |
2936 | } | |
252b5132 RH |
2937 | #endif |
2938 | ||
24eab124 AM |
2939 | SKIP_WHITESPACE (); |
2940 | if (*input_line_pointer) | |
d0b47220 | 2941 | as_bad (_("ignoring junk `%s' after expression"), |
24eab124 | 2942 | input_line_pointer); |
252b5132 | 2943 | #if GCC_ASM_O_HACK |
24eab124 | 2944 | RESTORE_END_STRING (disp_end + 1); |
252b5132 | 2945 | #endif |
24eab124 AM |
2946 | RESTORE_END_STRING (disp_end); |
2947 | input_line_pointer = save_input_line_pointer; | |
2948 | ||
2daf4fd8 AM |
2949 | if (exp->X_op == O_absent || exp->X_op == O_big) |
2950 | { | |
47926f60 | 2951 | /* Missing or bad expr becomes absolute 0. */ |
d0b47220 | 2952 | as_bad (_("missing or invalid displacement expression `%s' taken as 0"), |
2daf4fd8 AM |
2953 | disp_start); |
2954 | exp->X_op = O_constant; | |
2955 | exp->X_add_number = 0; | |
2956 | exp->X_add_symbol = (symbolS *) 0; | |
2957 | exp->X_op_symbol = (symbolS *) 0; | |
2958 | } | |
2959 | ||
4c63da97 | 2960 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
45288df1 | 2961 | if (exp->X_op != O_constant |
4c63da97 | 2962 | #ifdef BFD_ASSEMBLER |
45288df1 | 2963 | && OUTPUT_FLAVOR == bfd_target_aout_flavour |
4c63da97 | 2964 | #endif |
45288df1 AM |
2965 | && exp_seg != text_section |
2966 | && exp_seg != data_section | |
2967 | && exp_seg != bss_section | |
2968 | && exp_seg != undefined_section) | |
24eab124 | 2969 | { |
4c63da97 | 2970 | #ifdef BFD_ASSEMBLER |
d0b47220 | 2971 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
4c63da97 | 2972 | #else |
d0b47220 | 2973 | as_bad (_("unimplemented segment type %d in operand"), exp_seg); |
4c63da97 | 2974 | #endif |
24eab124 AM |
2975 | return 0; |
2976 | } | |
252b5132 RH |
2977 | #endif |
2978 | return 1; | |
2979 | } | |
2980 | ||
2981 | static int i386_operand_modifier PARAMS ((char **, int)); | |
2982 | ||
2983 | static int | |
2984 | i386_operand_modifier (op_string, got_a_float) | |
2985 | char **op_string; | |
2986 | int got_a_float; | |
2987 | { | |
24eab124 AM |
2988 | if (!strncasecmp (*op_string, "BYTE PTR", 8)) |
2989 | { | |
2990 | i.suffix = BYTE_MNEM_SUFFIX; | |
2991 | *op_string += 8; | |
2992 | return BYTE_PTR; | |
252b5132 | 2993 | |
24eab124 AM |
2994 | } |
2995 | else if (!strncasecmp (*op_string, "WORD PTR", 8)) | |
2996 | { | |
47926f60 | 2997 | if (got_a_float == 2) /* "fi..." */ |
cc5ca5ce AM |
2998 | i.suffix = SHORT_MNEM_SUFFIX; |
2999 | else | |
3000 | i.suffix = WORD_MNEM_SUFFIX; | |
24eab124 AM |
3001 | *op_string += 8; |
3002 | return WORD_PTR; | |
3003 | } | |
252b5132 | 3004 | |
24eab124 AM |
3005 | else if (!strncasecmp (*op_string, "DWORD PTR", 9)) |
3006 | { | |
47926f60 | 3007 | if (got_a_float == 1) /* "f..." */ |
24eab124 AM |
3008 | i.suffix = SHORT_MNEM_SUFFIX; |
3009 | else | |
add0c677 | 3010 | i.suffix = LONG_MNEM_SUFFIX; |
24eab124 AM |
3011 | *op_string += 9; |
3012 | return DWORD_PTR; | |
3013 | } | |
252b5132 | 3014 | |
24eab124 AM |
3015 | else if (!strncasecmp (*op_string, "QWORD PTR", 9)) |
3016 | { | |
add0c677 | 3017 | i.suffix = DWORD_MNEM_SUFFIX; |
24eab124 AM |
3018 | *op_string += 9; |
3019 | return QWORD_PTR; | |
3020 | } | |
252b5132 | 3021 | |
24eab124 AM |
3022 | else if (!strncasecmp (*op_string, "XWORD PTR", 9)) |
3023 | { | |
3024 | i.suffix = LONG_DOUBLE_MNEM_SUFFIX; | |
3025 | *op_string += 9; | |
3026 | return XWORD_PTR; | |
3027 | } | |
252b5132 | 3028 | |
6588847e DN |
3029 | /* Compare with space separator to avoid confusing identifier `short_var' |
3030 | with attribute `short'. */ | |
3031 | else if (!strncasecmp (*op_string, "SHORT ", 6)) | |
24eab124 AM |
3032 | { |
3033 | *op_string += 5; | |
3034 | return SHORT; | |
3035 | } | |
252b5132 | 3036 | |
24eab124 AM |
3037 | else if (!strncasecmp (*op_string, "OFFSET FLAT:", 12)) |
3038 | { | |
3039 | *op_string += 12; | |
3040 | return OFFSET_FLAT; | |
3041 | } | |
252b5132 | 3042 | |
6588847e DN |
3043 | /* Compare with space separator to avoid confusing identifier `flat_var' |
3044 | with attribute `flat'. */ | |
3045 | else if (!strncasecmp (*op_string, "FLAT ", 5)) | |
24eab124 AM |
3046 | { |
3047 | *op_string += 4; | |
3048 | return FLAT; | |
3049 | } | |
252b5132 | 3050 | |
24eab124 | 3051 | else return NONE_FOUND; |
c3332e24 | 3052 | } |
252b5132 RH |
3053 | |
3054 | static char * build_displacement_string PARAMS ((int, char *)); | |
3055 | ||
3056 | static char * | |
3057 | build_displacement_string (initial_disp, op_string) | |
3058 | int initial_disp; | |
3059 | char *op_string; | |
3060 | { | |
3061 | char *temp_string = (char *) malloc (strlen (op_string) + 1); | |
3062 | char *end_of_operand_string; | |
3063 | char *tc; | |
3064 | char *temp_disp; | |
3065 | ||
3066 | temp_string[0] = '\0'; | |
3067 | tc = end_of_operand_string = strchr (op_string, '['); | |
36bf8ab9 | 3068 | if (initial_disp && !end_of_operand_string) |
252b5132 RH |
3069 | { |
3070 | strcpy (temp_string, op_string); | |
36bf8ab9 | 3071 | return temp_string; |
252b5132 RH |
3072 | } |
3073 | ||
47926f60 | 3074 | /* Build the whole displacement string. */ |
252b5132 RH |
3075 | if (initial_disp) |
3076 | { | |
3077 | strncpy (temp_string, op_string, end_of_operand_string - op_string); | |
3078 | temp_string[end_of_operand_string - op_string] = '\0'; | |
3079 | temp_disp = tc; | |
3080 | } | |
c3332e24 | 3081 | else |
252b5132 RH |
3082 | temp_disp = op_string; |
3083 | ||
3084 | while (*temp_disp != '\0') | |
3085 | { | |
af6bdddf | 3086 | char *end_op; |
252b5132 RH |
3087 | int add_minus = (*temp_disp == '-'); |
3088 | ||
3089 | if (*temp_disp == '+' || *temp_disp == '-' || *temp_disp == '[') | |
24eab124 | 3090 | temp_disp++; |
252b5132 RH |
3091 | |
3092 | if (is_space_char (*temp_disp)) | |
24eab124 | 3093 | temp_disp++; |
252b5132 | 3094 | |
47926f60 | 3095 | /* Don't consider registers. */ |
af6bdddf AM |
3096 | if ( !((*temp_disp == REGISTER_PREFIX || allow_naked_reg) |
3097 | && parse_register (temp_disp, &end_op)) ) | |
24eab124 AM |
3098 | { |
3099 | char *string_start = temp_disp; | |
3100 | ||
3101 | while (*temp_disp != ']' | |
3102 | && *temp_disp != '+' | |
3103 | && *temp_disp != '-' | |
3104 | && *temp_disp != '*') | |
3105 | ++temp_disp; | |
3106 | ||
3107 | if (add_minus) | |
3108 | strcat (temp_string, "-"); | |
3109 | else | |
3110 | strcat (temp_string, "+"); | |
3111 | ||
3112 | strncat (temp_string, string_start, temp_disp - string_start); | |
3113 | if (*temp_disp == '+' || *temp_disp == '-') | |
3114 | --temp_disp; | |
3115 | } | |
252b5132 RH |
3116 | |
3117 | while (*temp_disp != '\0' | |
24eab124 AM |
3118 | && *temp_disp != '+' |
3119 | && *temp_disp != '-') | |
3120 | ++temp_disp; | |
252b5132 RH |
3121 | } |
3122 | ||
3123 | return temp_string; | |
3124 | } | |
3125 | ||
3126 | static int i386_parse_seg PARAMS ((char *)); | |
3127 | ||
3128 | static int | |
3129 | i386_parse_seg (op_string) | |
3130 | char *op_string; | |
3131 | { | |
3132 | if (is_space_char (*op_string)) | |
3133 | ++op_string; | |
3134 | ||
47926f60 | 3135 | /* Should be one of es, cs, ss, ds fs or gs. */ |
252b5132 RH |
3136 | switch (*op_string++) |
3137 | { | |
3138 | case 'e': | |
3139 | i.seg[i.mem_operands] = &es; | |
3140 | break; | |
3141 | case 'c': | |
3142 | i.seg[i.mem_operands] = &cs; | |
3143 | break; | |
3144 | case 's': | |
3145 | i.seg[i.mem_operands] = &ss; | |
3146 | break; | |
3147 | case 'd': | |
3148 | i.seg[i.mem_operands] = &ds; | |
3149 | break; | |
3150 | case 'f': | |
3151 | i.seg[i.mem_operands] = &fs; | |
3152 | break; | |
3153 | case 'g': | |
3154 | i.seg[i.mem_operands] = &gs; | |
3155 | break; | |
3156 | default: | |
3157 | as_bad (_("bad segment name `%s'"), op_string); | |
3158 | return 0; | |
3159 | } | |
3160 | ||
3161 | if (*op_string++ != 's') | |
3162 | { | |
24eab124 AM |
3163 | as_bad (_("bad segment name `%s'"), op_string); |
3164 | return 0; | |
252b5132 RH |
3165 | } |
3166 | ||
3167 | if (is_space_char (*op_string)) | |
3168 | ++op_string; | |
3169 | ||
3170 | if (*op_string != ':') | |
3171 | { | |
24eab124 AM |
3172 | as_bad (_("bad segment name `%s'"), op_string); |
3173 | return 0; | |
252b5132 RH |
3174 | } |
3175 | ||
c3332e24 AM |
3176 | return 1; |
3177 | ||
252b5132 RH |
3178 | } |
3179 | ||
eecb386c | 3180 | static int i386_index_check PARAMS((const char *)); |
252b5132 | 3181 | |
eecb386c | 3182 | /* Make sure the memory operand we've been dealt is valid. |
47926f60 KH |
3183 | Return 1 on success, 0 on a failure. */ |
3184 | ||
252b5132 | 3185 | static int |
eecb386c AM |
3186 | i386_index_check (operand_string) |
3187 | const char *operand_string; | |
252b5132 | 3188 | { |
24eab124 | 3189 | #if INFER_ADDR_PREFIX |
eecb386c AM |
3190 | int fudged = 0; |
3191 | ||
24eab124 AM |
3192 | tryprefix: |
3193 | #endif | |
d0b47220 | 3194 | if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0) |
47926f60 | 3195 | /* 16 bit mode checks. */ |
d0b47220 AM |
3196 | ? ((i.base_reg |
3197 | && ((i.base_reg->reg_type & (Reg16|BaseIndex)) | |
3198 | != (Reg16|BaseIndex))) | |
3199 | || (i.index_reg | |
3200 | && (((i.index_reg->reg_type & (Reg16|BaseIndex)) | |
3201 | != (Reg16|BaseIndex)) | |
3202 | || ! (i.base_reg | |
3203 | && i.base_reg->reg_num < 6 | |
3204 | && i.index_reg->reg_num >= 6 | |
3205 | && i.log2_scale_factor == 0)))) | |
47926f60 | 3206 | /* 32 bit mode checks. */ |
d0b47220 AM |
3207 | : ((i.base_reg |
3208 | && (i.base_reg->reg_type & Reg32) == 0) | |
3209 | || (i.index_reg | |
3210 | && ((i.index_reg->reg_type & (Reg32|BaseIndex)) | |
3211 | != (Reg32|BaseIndex))))) | |
24eab124 AM |
3212 | { |
3213 | #if INFER_ADDR_PREFIX | |
eecb386c | 3214 | if (i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0') |
24eab124 AM |
3215 | { |
3216 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
3217 | i.prefixes += 1; | |
b23bac36 AM |
3218 | /* Change the size of any displacement too. At most one of |
3219 | Disp16 or Disp32 is set. | |
3220 | FIXME. There doesn't seem to be any real need for separate | |
3221 | Disp16 and Disp32 flags. The same goes for Imm16 and Imm32. | |
47926f60 | 3222 | Removing them would probably clean up the code quite a lot. */ |
b23bac36 AM |
3223 | if (i.types[this_operand] & (Disp16|Disp32)) |
3224 | i.types[this_operand] ^= (Disp16|Disp32); | |
eecb386c | 3225 | fudged = 1; |
24eab124 AM |
3226 | goto tryprefix; |
3227 | } | |
eecb386c AM |
3228 | if (fudged) |
3229 | as_bad (_("`%s' is not a valid base/index expression"), | |
3230 | operand_string); | |
3231 | else | |
c388dee8 | 3232 | #endif |
eecb386c AM |
3233 | as_bad (_("`%s' is not a valid %s bit base/index expression"), |
3234 | operand_string, | |
3235 | flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0) ? "16" : "32"); | |
3236 | return 0; | |
24eab124 AM |
3237 | } |
3238 | return 1; | |
3239 | } | |
252b5132 | 3240 | |
24eab124 AM |
3241 | static int i386_intel_memory_operand PARAMS ((char *)); |
3242 | ||
3243 | static int | |
3244 | i386_intel_memory_operand (operand_string) | |
3245 | char *operand_string; | |
3246 | { | |
3247 | char *op_string = operand_string; | |
252b5132 RH |
3248 | char *end_of_operand_string; |
3249 | ||
24eab124 AM |
3250 | if ((i.mem_operands == 1 |
3251 | && (current_templates->start->opcode_modifier & IsString) == 0) | |
3252 | || i.mem_operands == 2) | |
252b5132 | 3253 | { |
24eab124 AM |
3254 | as_bad (_("too many memory references for `%s'"), |
3255 | current_templates->start->name); | |
3256 | return 0; | |
252b5132 RH |
3257 | } |
3258 | ||
36bf8ab9 | 3259 | /* First check for a segment override. */ |
252b5132 RH |
3260 | if (*op_string != '[') |
3261 | { | |
3262 | char *end_seg; | |
252b5132 RH |
3263 | |
3264 | end_seg = strchr (op_string, ':'); | |
3265 | if (end_seg) | |
24eab124 AM |
3266 | { |
3267 | if (!i386_parse_seg (op_string)) | |
3268 | return 0; | |
3269 | op_string = end_seg + 1; | |
3270 | } | |
36bf8ab9 | 3271 | } |
252b5132 | 3272 | |
47926f60 | 3273 | /* Look for displacement preceding open bracket. */ |
36bf8ab9 AM |
3274 | if (*op_string != '[') |
3275 | { | |
3276 | char *temp_string; | |
24eab124 | 3277 | |
36bf8ab9 | 3278 | if (i.disp_operands) |
24eab124 | 3279 | return 0; |
252b5132 | 3280 | |
36bf8ab9 AM |
3281 | temp_string = build_displacement_string (true, op_string); |
3282 | ||
3283 | if (!i386_displacement (temp_string, temp_string + strlen (temp_string))) | |
3284 | { | |
3285 | free (temp_string); | |
3286 | return 0; | |
3287 | } | |
3288 | free (temp_string); | |
3289 | ||
252b5132 RH |
3290 | end_of_operand_string = strchr (op_string, '['); |
3291 | if (!end_of_operand_string) | |
24eab124 | 3292 | end_of_operand_string = op_string + strlen (op_string); |
252b5132 RH |
3293 | |
3294 | if (is_space_char (*end_of_operand_string)) | |
24eab124 | 3295 | --end_of_operand_string; |
252b5132 RH |
3296 | |
3297 | op_string = end_of_operand_string; | |
24eab124 | 3298 | } |
252b5132 RH |
3299 | |
3300 | if (*op_string == '[') | |
3301 | { | |
3302 | ++op_string; | |
3303 | ||
ce8a8b2f | 3304 | /* Pick off each component and figure out where it belongs. */ |
252b5132 RH |
3305 | |
3306 | end_of_operand_string = op_string; | |
3307 | ||
3308 | while (*op_string != ']') | |
24eab124 | 3309 | { |
af6bdddf AM |
3310 | const reg_entry *temp_reg; |
3311 | char *end_op; | |
3312 | char *temp_string; | |
24eab124 AM |
3313 | |
3314 | while (*end_of_operand_string != '+' | |
3315 | && *end_of_operand_string != '-' | |
3316 | && *end_of_operand_string != '*' | |
3317 | && *end_of_operand_string != ']') | |
3318 | end_of_operand_string++; | |
3319 | ||
af6bdddf AM |
3320 | temp_string = op_string; |
3321 | if (*temp_string == '+') | |
24eab124 | 3322 | { |
af6bdddf | 3323 | ++temp_string; |
24eab124 AM |
3324 | if (is_space_char (*temp_string)) |
3325 | ++temp_string; | |
24eab124 AM |
3326 | } |
3327 | ||
af6bdddf AM |
3328 | if ((*temp_string == REGISTER_PREFIX || allow_naked_reg) |
3329 | && (temp_reg = parse_register (temp_string, &end_op)) != NULL) | |
24eab124 | 3330 | { |
24eab124 AM |
3331 | if (i.base_reg == NULL) |
3332 | i.base_reg = temp_reg; | |
3333 | else | |
3334 | i.index_reg = temp_reg; | |
3335 | ||
3336 | i.types[this_operand] |= BaseIndex; | |
24eab124 | 3337 | } |
af6bdddf | 3338 | else if (*temp_string == REGISTER_PREFIX) |
24eab124 | 3339 | { |
af6bdddf AM |
3340 | as_bad (_("bad register name `%s'"), temp_string); |
3341 | return 0; | |
3342 | } | |
3343 | else if (is_digit_char (*op_string) | |
3344 | || *op_string == '+' || *op_string == '-') | |
3345 | { | |
36bf8ab9 AM |
3346 | char *temp_str; |
3347 | ||
3348 | if (i.disp_operands != 0) | |
3349 | return 0; | |
3350 | ||
af6bdddf | 3351 | temp_string = build_displacement_string (false, op_string); |
24eab124 | 3352 | |
36bf8ab9 AM |
3353 | temp_str = temp_string; |
3354 | if (*temp_str == '+') | |
3355 | ++temp_str; | |
24eab124 | 3356 | |
36bf8ab9 AM |
3357 | if (!i386_displacement (temp_str, temp_str + strlen (temp_str))) |
3358 | { | |
3359 | free (temp_string); | |
3360 | return 0; | |
3361 | } | |
3362 | free (temp_string); | |
24eab124 AM |
3363 | |
3364 | ++op_string; | |
3365 | end_of_operand_string = op_string; | |
3366 | while (*end_of_operand_string != ']' | |
3367 | && *end_of_operand_string != '+' | |
3368 | && *end_of_operand_string != '-' | |
3369 | && *end_of_operand_string != '*') | |
3370 | ++end_of_operand_string; | |
3371 | } | |
3372 | else if (*op_string == '*') | |
3373 | { | |
3374 | ++op_string; | |
3375 | ||
3376 | if (i.base_reg && !i.index_reg) | |
3377 | { | |
3378 | i.index_reg = i.base_reg; | |
3379 | i.base_reg = 0; | |
3380 | } | |
3381 | ||
3382 | if (!i386_scale (op_string)) | |
3383 | return 0; | |
3384 | } | |
3385 | op_string = end_of_operand_string; | |
3386 | ++end_of_operand_string; | |
3387 | } | |
3388 | } | |
3389 | ||
eecb386c AM |
3390 | if (i386_index_check (operand_string) == 0) |
3391 | return 0; | |
252b5132 | 3392 | |
24eab124 | 3393 | i.mem_operands++; |
252b5132 RH |
3394 | return 1; |
3395 | } | |
3396 | ||
252b5132 RH |
3397 | static int |
3398 | i386_intel_operand (operand_string, got_a_float) | |
3399 | char *operand_string; | |
3400 | int got_a_float; | |
3401 | { | |
47926f60 | 3402 | const reg_entry *r; |
af6bdddf | 3403 | char *end_op; |
252b5132 RH |
3404 | char *op_string = operand_string; |
3405 | ||
3406 | int operand_modifier = i386_operand_modifier (&op_string, got_a_float); | |
3407 | if (is_space_char (*op_string)) | |
3408 | ++op_string; | |
3409 | ||
3410 | switch (operand_modifier) | |
3411 | { | |
3412 | case BYTE_PTR: | |
3413 | case WORD_PTR: | |
3414 | case DWORD_PTR: | |
3415 | case QWORD_PTR: | |
3416 | case XWORD_PTR: | |
252b5132 | 3417 | if (!i386_intel_memory_operand (op_string)) |
24eab124 | 3418 | return 0; |
252b5132 RH |
3419 | break; |
3420 | ||
3421 | case FLAT: | |
252b5132 RH |
3422 | case OFFSET_FLAT: |
3423 | if (!i386_immediate (op_string)) | |
24eab124 | 3424 | return 0; |
252b5132 RH |
3425 | break; |
3426 | ||
3427 | case SHORT: | |
252b5132 | 3428 | case NONE_FOUND: |
ce8a8b2f | 3429 | /* Should be register or immediate. */ |
c3332e24 AM |
3430 | if (is_digit_char (*op_string) |
3431 | && strchr (op_string, '[') == 0) | |
3432 | { | |
3433 | if (!i386_immediate (op_string)) | |
3434 | return 0; | |
3435 | } | |
af6bdddf AM |
3436 | else if ((*op_string == REGISTER_PREFIX || allow_naked_reg) |
3437 | && (r = parse_register (op_string, &end_op)) != NULL) | |
c3332e24 | 3438 | { |
c3332e24 AM |
3439 | /* Check for a segment override by searching for ':' after a |
3440 | segment register. */ | |
3441 | op_string = end_op; | |
3442 | if (is_space_char (*op_string)) | |
3443 | ++op_string; | |
3444 | if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3))) | |
3445 | { | |
3446 | switch (r->reg_num) | |
3447 | { | |
3448 | case 0: | |
3449 | i.seg[i.mem_operands] = &es; | |
3450 | break; | |
3451 | case 1: | |
3452 | i.seg[i.mem_operands] = &cs; | |
3453 | break; | |
3454 | case 2: | |
3455 | i.seg[i.mem_operands] = &ss; | |
3456 | break; | |
3457 | case 3: | |
3458 | i.seg[i.mem_operands] = &ds; | |
3459 | break; | |
3460 | case 4: | |
3461 | i.seg[i.mem_operands] = &fs; | |
3462 | break; | |
3463 | case 5: | |
3464 | i.seg[i.mem_operands] = &gs; | |
3465 | break; | |
3466 | } | |
252b5132 | 3467 | |
c3332e24 AM |
3468 | } |
3469 | i.types[this_operand] |= r->reg_type & ~BaseIndex; | |
520dc8e8 | 3470 | i.op[this_operand].regs = r; |
c3332e24 AM |
3471 | i.reg_operands++; |
3472 | } | |
af6bdddf | 3473 | else if (*op_string == REGISTER_PREFIX) |
c3332e24 | 3474 | { |
af6bdddf AM |
3475 | as_bad (_("bad register name `%s'"), op_string); |
3476 | return 0; | |
c3332e24 | 3477 | } |
af6bdddf AM |
3478 | else if (!i386_intel_memory_operand (op_string)) |
3479 | return 0; | |
3480 | ||
c3332e24 | 3481 | break; |
ce8a8b2f | 3482 | } |
24eab124 | 3483 | |
252b5132 RH |
3484 | return 1; |
3485 | } | |
3486 | ||
3487 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero | |
47926f60 | 3488 | on error. */ |
252b5132 | 3489 | |
252b5132 RH |
3490 | static int |
3491 | i386_operand (operand_string) | |
3492 | char *operand_string; | |
3493 | { | |
af6bdddf AM |
3494 | const reg_entry *r; |
3495 | char *end_op; | |
24eab124 | 3496 | char *op_string = operand_string; |
252b5132 | 3497 | |
24eab124 | 3498 | if (is_space_char (*op_string)) |
252b5132 RH |
3499 | ++op_string; |
3500 | ||
24eab124 | 3501 | /* We check for an absolute prefix (differentiating, |
47926f60 | 3502 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
3503 | if (*op_string == ABSOLUTE_PREFIX) |
3504 | { | |
3505 | ++op_string; | |
3506 | if (is_space_char (*op_string)) | |
3507 | ++op_string; | |
3508 | i.types[this_operand] |= JumpAbsolute; | |
3509 | } | |
252b5132 | 3510 | |
47926f60 | 3511 | /* Check if operand is a register. */ |
af6bdddf AM |
3512 | if ((*op_string == REGISTER_PREFIX || allow_naked_reg) |
3513 | && (r = parse_register (op_string, &end_op)) != NULL) | |
24eab124 | 3514 | { |
24eab124 AM |
3515 | /* Check for a segment override by searching for ':' after a |
3516 | segment register. */ | |
3517 | op_string = end_op; | |
3518 | if (is_space_char (*op_string)) | |
3519 | ++op_string; | |
3520 | if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3))) | |
3521 | { | |
3522 | switch (r->reg_num) | |
3523 | { | |
3524 | case 0: | |
3525 | i.seg[i.mem_operands] = &es; | |
3526 | break; | |
3527 | case 1: | |
3528 | i.seg[i.mem_operands] = &cs; | |
3529 | break; | |
3530 | case 2: | |
3531 | i.seg[i.mem_operands] = &ss; | |
3532 | break; | |
3533 | case 3: | |
3534 | i.seg[i.mem_operands] = &ds; | |
3535 | break; | |
3536 | case 4: | |
3537 | i.seg[i.mem_operands] = &fs; | |
3538 | break; | |
3539 | case 5: | |
3540 | i.seg[i.mem_operands] = &gs; | |
3541 | break; | |
3542 | } | |
252b5132 | 3543 | |
24eab124 | 3544 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
3545 | ++op_string; |
3546 | if (is_space_char (*op_string)) | |
24eab124 | 3547 | ++op_string; |
252b5132 | 3548 | |
24eab124 AM |
3549 | if (!is_digit_char (*op_string) |
3550 | && !is_identifier_char (*op_string) | |
3551 | && *op_string != '(' | |
3552 | && *op_string != ABSOLUTE_PREFIX) | |
3553 | { | |
3554 | as_bad (_("bad memory operand `%s'"), op_string); | |
3555 | return 0; | |
3556 | } | |
47926f60 | 3557 | /* Handle case of %es:*foo. */ |
24eab124 AM |
3558 | if (*op_string == ABSOLUTE_PREFIX) |
3559 | { | |
3560 | ++op_string; | |
3561 | if (is_space_char (*op_string)) | |
3562 | ++op_string; | |
3563 | i.types[this_operand] |= JumpAbsolute; | |
3564 | } | |
3565 | goto do_memory_reference; | |
3566 | } | |
3567 | if (*op_string) | |
3568 | { | |
d0b47220 | 3569 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
3570 | return 0; |
3571 | } | |
3572 | i.types[this_operand] |= r->reg_type & ~BaseIndex; | |
520dc8e8 | 3573 | i.op[this_operand].regs = r; |
24eab124 AM |
3574 | i.reg_operands++; |
3575 | } | |
af6bdddf AM |
3576 | else if (*op_string == REGISTER_PREFIX) |
3577 | { | |
3578 | as_bad (_("bad register name `%s'"), op_string); | |
3579 | return 0; | |
3580 | } | |
24eab124 | 3581 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 3582 | { |
24eab124 AM |
3583 | ++op_string; |
3584 | if (i.types[this_operand] & JumpAbsolute) | |
3585 | { | |
d0b47220 | 3586 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
3587 | return 0; |
3588 | } | |
3589 | if (!i386_immediate (op_string)) | |
3590 | return 0; | |
3591 | } | |
3592 | else if (is_digit_char (*op_string) | |
3593 | || is_identifier_char (*op_string) | |
3594 | || *op_string == '(' ) | |
3595 | { | |
47926f60 | 3596 | /* This is a memory reference of some sort. */ |
af6bdddf | 3597 | char *base_string; |
252b5132 | 3598 | |
47926f60 | 3599 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
3600 | char *displacement_string_start; |
3601 | char *displacement_string_end; | |
252b5132 | 3602 | |
24eab124 | 3603 | do_memory_reference: |
24eab124 AM |
3604 | if ((i.mem_operands == 1 |
3605 | && (current_templates->start->opcode_modifier & IsString) == 0) | |
3606 | || i.mem_operands == 2) | |
3607 | { | |
3608 | as_bad (_("too many memory references for `%s'"), | |
3609 | current_templates->start->name); | |
3610 | return 0; | |
3611 | } | |
252b5132 | 3612 | |
24eab124 AM |
3613 | /* Check for base index form. We detect the base index form by |
3614 | looking for an ')' at the end of the operand, searching | |
3615 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
3616 | after the '('. */ | |
af6bdddf | 3617 | base_string = op_string + strlen (op_string); |
c3332e24 | 3618 | |
af6bdddf AM |
3619 | --base_string; |
3620 | if (is_space_char (*base_string)) | |
3621 | --base_string; | |
252b5132 | 3622 | |
47926f60 | 3623 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
3624 | displacement_string_start = op_string; |
3625 | displacement_string_end = base_string + 1; | |
252b5132 | 3626 | |
24eab124 AM |
3627 | if (*base_string == ')') |
3628 | { | |
af6bdddf | 3629 | char *temp_string; |
24eab124 AM |
3630 | unsigned int parens_balanced = 1; |
3631 | /* We've already checked that the number of left & right ()'s are | |
47926f60 | 3632 | equal, so this loop will not be infinite. */ |
24eab124 AM |
3633 | do |
3634 | { | |
3635 | base_string--; | |
3636 | if (*base_string == ')') | |
3637 | parens_balanced++; | |
3638 | if (*base_string == '(') | |
3639 | parens_balanced--; | |
3640 | } | |
3641 | while (parens_balanced); | |
c3332e24 | 3642 | |
af6bdddf | 3643 | temp_string = base_string; |
c3332e24 | 3644 | |
24eab124 | 3645 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
3646 | ++base_string; |
3647 | if (is_space_char (*base_string)) | |
24eab124 | 3648 | ++base_string; |
252b5132 | 3649 | |
af6bdddf AM |
3650 | if (*base_string == ',' |
3651 | || ((*base_string == REGISTER_PREFIX || allow_naked_reg) | |
3652 | && (i.base_reg = parse_register (base_string, &end_op)) != NULL)) | |
252b5132 | 3653 | { |
af6bdddf | 3654 | displacement_string_end = temp_string; |
252b5132 | 3655 | |
af6bdddf | 3656 | i.types[this_operand] |= BaseIndex; |
252b5132 | 3657 | |
af6bdddf | 3658 | if (i.base_reg) |
24eab124 | 3659 | { |
24eab124 AM |
3660 | base_string = end_op; |
3661 | if (is_space_char (*base_string)) | |
3662 | ++base_string; | |
af6bdddf AM |
3663 | } |
3664 | ||
3665 | /* There may be an index reg or scale factor here. */ | |
3666 | if (*base_string == ',') | |
3667 | { | |
3668 | ++base_string; | |
3669 | if (is_space_char (*base_string)) | |
3670 | ++base_string; | |
3671 | ||
3672 | if ((*base_string == REGISTER_PREFIX || allow_naked_reg) | |
3673 | && (i.index_reg = parse_register (base_string, &end_op)) != NULL) | |
24eab124 | 3674 | { |
af6bdddf | 3675 | base_string = end_op; |
24eab124 AM |
3676 | if (is_space_char (*base_string)) |
3677 | ++base_string; | |
af6bdddf AM |
3678 | if (*base_string == ',') |
3679 | { | |
3680 | ++base_string; | |
3681 | if (is_space_char (*base_string)) | |
3682 | ++base_string; | |
3683 | } | |
3684 | else if (*base_string != ')' ) | |
3685 | { | |
3686 | as_bad (_("expecting `,' or `)' after index register in `%s'"), | |
3687 | operand_string); | |
3688 | return 0; | |
3689 | } | |
24eab124 | 3690 | } |
af6bdddf | 3691 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 3692 | { |
af6bdddf | 3693 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
3694 | return 0; |
3695 | } | |
252b5132 | 3696 | |
47926f60 | 3697 | /* Check for scale factor. */ |
af6bdddf AM |
3698 | if (isdigit ((unsigned char) *base_string)) |
3699 | { | |
3700 | if (!i386_scale (base_string)) | |
3701 | return 0; | |
24eab124 | 3702 | |
af6bdddf AM |
3703 | ++base_string; |
3704 | if (is_space_char (*base_string)) | |
3705 | ++base_string; | |
3706 | if (*base_string != ')') | |
3707 | { | |
3708 | as_bad (_("expecting `)' after scale factor in `%s'"), | |
3709 | operand_string); | |
3710 | return 0; | |
3711 | } | |
3712 | } | |
3713 | else if (!i.index_reg) | |
24eab124 | 3714 | { |
af6bdddf AM |
3715 | as_bad (_("expecting index register or scale factor after `,'; got '%c'"), |
3716 | *base_string); | |
24eab124 AM |
3717 | return 0; |
3718 | } | |
3719 | } | |
af6bdddf | 3720 | else if (*base_string != ')') |
24eab124 | 3721 | { |
af6bdddf AM |
3722 | as_bad (_("expecting `,' or `)' after base register in `%s'"), |
3723 | operand_string); | |
24eab124 AM |
3724 | return 0; |
3725 | } | |
c3332e24 | 3726 | } |
af6bdddf | 3727 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 3728 | { |
af6bdddf | 3729 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 3730 | return 0; |
c3332e24 | 3731 | } |
24eab124 AM |
3732 | } |
3733 | ||
3734 | /* If there's an expression beginning the operand, parse it, | |
3735 | assuming displacement_string_start and | |
3736 | displacement_string_end are meaningful. */ | |
3737 | if (displacement_string_start != displacement_string_end) | |
3738 | { | |
3739 | if (!i386_displacement (displacement_string_start, | |
3740 | displacement_string_end)) | |
3741 | return 0; | |
3742 | } | |
3743 | ||
3744 | /* Special case for (%dx) while doing input/output op. */ | |
3745 | if (i.base_reg | |
3746 | && i.base_reg->reg_type == (Reg16 | InOutPortReg) | |
3747 | && i.index_reg == 0 | |
3748 | && i.log2_scale_factor == 0 | |
3749 | && i.seg[i.mem_operands] == 0 | |
3750 | && (i.types[this_operand] & Disp) == 0) | |
3751 | { | |
3752 | i.types[this_operand] = InOutPortReg; | |
3753 | return 1; | |
3754 | } | |
3755 | ||
eecb386c AM |
3756 | if (i386_index_check (operand_string) == 0) |
3757 | return 0; | |
24eab124 AM |
3758 | i.mem_operands++; |
3759 | } | |
3760 | else | |
ce8a8b2f AM |
3761 | { |
3762 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
3763 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
3764 | output_invalid (*op_string), | |
3765 | this_operand + 1, | |
3766 | op_string); | |
3767 | return 0; | |
3768 | } | |
47926f60 | 3769 | return 1; /* Normal return. */ |
252b5132 RH |
3770 | } |
3771 | \f | |
ee7fcc42 AM |
3772 | /* md_estimate_size_before_relax() |
3773 | ||
3774 | Called just before relax() for rs_machine_dependent frags. The x86 | |
3775 | assembler uses these frags to handle variable size jump | |
3776 | instructions. | |
3777 | ||
3778 | Any symbol that is now undefined will not become defined. | |
3779 | Return the correct fr_subtype in the frag. | |
3780 | Return the initial "guess for variable size of frag" to caller. | |
3781 | The guess is actually the growth beyond the fixed part. Whatever | |
3782 | we do to grow the fixed or variable part contributes to our | |
3783 | returned value. */ | |
3784 | ||
252b5132 RH |
3785 | int |
3786 | md_estimate_size_before_relax (fragP, segment) | |
3787 | register fragS *fragP; | |
3788 | register segT segment; | |
3789 | { | |
252b5132 | 3790 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
3791 | check for un-relaxable symbols. On an ELF system, we can't relax |
3792 | an externally visible symbol, because it may be overridden by a | |
3793 | shared library. */ | |
3794 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 3795 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
b98ef147 AM |
3796 | || S_IS_EXTERNAL (fragP->fr_symbol) |
3797 | || S_IS_WEAK (fragP->fr_symbol) | |
3798 | #endif | |
3799 | ) | |
252b5132 | 3800 | { |
b98ef147 AM |
3801 | /* Symbol is undefined in this segment, or we need to keep a |
3802 | reloc so that weak symbols can be overridden. */ | |
3803 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f6af82bd AM |
3804 | #ifdef BFD_ASSEMBLER |
3805 | enum bfd_reloc_code_real reloc_type; | |
3806 | #else | |
3807 | int reloc_type; | |
3808 | #endif | |
ee7fcc42 AM |
3809 | unsigned char *opcode; |
3810 | int old_fr_fix; | |
f6af82bd | 3811 | |
ee7fcc42 AM |
3812 | if (fragP->fr_var != NO_RELOC) |
3813 | reloc_type = fragP->fr_var; | |
b98ef147 | 3814 | else if (size == 2) |
f6af82bd AM |
3815 | reloc_type = BFD_RELOC_16_PCREL; |
3816 | else | |
3817 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 3818 | |
ee7fcc42 AM |
3819 | old_fr_fix = fragP->fr_fix; |
3820 | opcode = (unsigned char *) fragP->fr_opcode; | |
3821 | ||
252b5132 RH |
3822 | switch (opcode[0]) |
3823 | { | |
47926f60 KH |
3824 | case JUMP_PC_RELATIVE: |
3825 | /* Make jmp (0xeb) a dword displacement jump. */ | |
47926f60 | 3826 | opcode[0] = 0xe9; |
252b5132 RH |
3827 | fragP->fr_fix += size; |
3828 | fix_new (fragP, old_fr_fix, size, | |
3829 | fragP->fr_symbol, | |
3830 | fragP->fr_offset, 1, | |
f6af82bd | 3831 | reloc_type); |
252b5132 RH |
3832 | break; |
3833 | ||
3834 | default: | |
24eab124 | 3835 | /* This changes the byte-displacement jump 0x7N |
f6af82bd | 3836 | to the dword-displacement jump 0x0f,0x8N. */ |
252b5132 | 3837 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 3838 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
3839 | /* We've added an opcode byte. */ |
3840 | fragP->fr_fix += 1 + size; | |
252b5132 RH |
3841 | fix_new (fragP, old_fr_fix + 1, size, |
3842 | fragP->fr_symbol, | |
3843 | fragP->fr_offset, 1, | |
f6af82bd | 3844 | reloc_type); |
252b5132 RH |
3845 | break; |
3846 | } | |
3847 | frag_wane (fragP); | |
ee7fcc42 | 3848 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 3849 | } |
47926f60 KH |
3850 | /* Guess a short jump. */ |
3851 | return 1; | |
ee7fcc42 AM |
3852 | } |
3853 | ||
47926f60 KH |
3854 | /* Called after relax() is finished. |
3855 | ||
3856 | In: Address of frag. | |
3857 | fr_type == rs_machine_dependent. | |
3858 | fr_subtype is what the address relaxed to. | |
3859 | ||
3860 | Out: Any fixSs and constants are set up. | |
3861 | Caller will turn frag into a ".space 0". */ | |
3862 | ||
252b5132 RH |
3863 | #ifndef BFD_ASSEMBLER |
3864 | void | |
3865 | md_convert_frag (headers, sec, fragP) | |
a04b544b ILT |
3866 | object_headers *headers ATTRIBUTE_UNUSED; |
3867 | segT sec ATTRIBUTE_UNUSED; | |
252b5132 RH |
3868 | register fragS *fragP; |
3869 | #else | |
3870 | void | |
3871 | md_convert_frag (abfd, sec, fragP) | |
ab9da554 ILT |
3872 | bfd *abfd ATTRIBUTE_UNUSED; |
3873 | segT sec ATTRIBUTE_UNUSED; | |
252b5132 RH |
3874 | register fragS *fragP; |
3875 | #endif | |
3876 | { | |
3877 | register unsigned char *opcode; | |
3878 | unsigned char *where_to_put_displacement = NULL; | |
847f7ad4 AM |
3879 | offsetT target_address; |
3880 | offsetT opcode_address; | |
252b5132 | 3881 | unsigned int extension = 0; |
847f7ad4 | 3882 | offsetT displacement_from_opcode_start; |
252b5132 RH |
3883 | |
3884 | opcode = (unsigned char *) fragP->fr_opcode; | |
3885 | ||
47926f60 | 3886 | /* Address we want to reach in file space. */ |
252b5132 | 3887 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
47926f60 KH |
3888 | #ifdef BFD_ASSEMBLER |
3889 | /* Not needed otherwise? */ | |
49309057 | 3890 | target_address += symbol_get_frag (fragP->fr_symbol)->fr_address; |
252b5132 RH |
3891 | #endif |
3892 | ||
47926f60 | 3893 | /* Address opcode resides at in file space. */ |
252b5132 RH |
3894 | opcode_address = fragP->fr_address + fragP->fr_fix; |
3895 | ||
47926f60 | 3896 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
3897 | displacement_from_opcode_start = target_address - opcode_address; |
3898 | ||
3899 | switch (fragP->fr_subtype) | |
3900 | { | |
3901 | case ENCODE_RELAX_STATE (COND_JUMP, SMALL): | |
3902 | case ENCODE_RELAX_STATE (COND_JUMP, SMALL16): | |
3903 | case ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL): | |
3904 | case ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL16): | |
47926f60 KH |
3905 | /* Don't have to change opcode. */ |
3906 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 RH |
3907 | where_to_put_displacement = &opcode[1]; |
3908 | break; | |
3909 | ||
3910 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): | |
47926f60 | 3911 | extension = 5; /* 2 opcode + 4 displacement */ |
252b5132 RH |
3912 | opcode[1] = opcode[0] + 0x10; |
3913 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
3914 | where_to_put_displacement = &opcode[2]; | |
3915 | break; | |
3916 | ||
3917 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
47926f60 | 3918 | extension = 4; /* 1 opcode + 4 displacement */ |
252b5132 RH |
3919 | opcode[0] = 0xe9; |
3920 | where_to_put_displacement = &opcode[1]; | |
3921 | break; | |
3922 | ||
3923 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): | |
47926f60 | 3924 | extension = 3; /* 2 opcode + 2 displacement */ |
252b5132 RH |
3925 | opcode[1] = opcode[0] + 0x10; |
3926 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
3927 | where_to_put_displacement = &opcode[2]; | |
3928 | break; | |
3929 | ||
3930 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): | |
47926f60 | 3931 | extension = 2; /* 1 opcode + 2 displacement */ |
252b5132 RH |
3932 | opcode[0] = 0xe9; |
3933 | where_to_put_displacement = &opcode[1]; | |
3934 | break; | |
3935 | ||
3936 | default: | |
3937 | BAD_CASE (fragP->fr_subtype); | |
3938 | break; | |
3939 | } | |
47926f60 | 3940 | /* Now put displacement after opcode. */ |
252b5132 RH |
3941 | md_number_to_chars ((char *) where_to_put_displacement, |
3942 | (valueT) (displacement_from_opcode_start - extension), | |
3943 | SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); | |
3944 | fragP->fr_fix += extension; | |
3945 | } | |
3946 | \f | |
47926f60 KH |
3947 | /* Size of byte displacement jmp. */ |
3948 | int md_short_jump_size = 2; | |
3949 | ||
3950 | /* Size of dword displacement jmp. */ | |
3951 | int md_long_jump_size = 5; | |
252b5132 | 3952 | |
47926f60 KH |
3953 | /* Size of relocation record. */ |
3954 | const int md_reloc_size = 8; | |
252b5132 RH |
3955 | |
3956 | void | |
3957 | md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol) | |
3958 | char *ptr; | |
3959 | addressT from_addr, to_addr; | |
ab9da554 ILT |
3960 | fragS *frag ATTRIBUTE_UNUSED; |
3961 | symbolS *to_symbol ATTRIBUTE_UNUSED; | |
252b5132 | 3962 | { |
847f7ad4 | 3963 | offsetT offset; |
252b5132 RH |
3964 | |
3965 | offset = to_addr - (from_addr + 2); | |
47926f60 KH |
3966 | /* Opcode for byte-disp jump. */ |
3967 | md_number_to_chars (ptr, (valueT) 0xeb, 1); | |
252b5132 RH |
3968 | md_number_to_chars (ptr + 1, (valueT) offset, 1); |
3969 | } | |
3970 | ||
3971 | void | |
3972 | md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol) | |
3973 | char *ptr; | |
3974 | addressT from_addr, to_addr; | |
a38cf1db AM |
3975 | fragS *frag ATTRIBUTE_UNUSED; |
3976 | symbolS *to_symbol ATTRIBUTE_UNUSED; | |
252b5132 | 3977 | { |
847f7ad4 | 3978 | offsetT offset; |
252b5132 | 3979 | |
a38cf1db AM |
3980 | offset = to_addr - (from_addr + 5); |
3981 | md_number_to_chars (ptr, (valueT) 0xe9, 1); | |
3982 | md_number_to_chars (ptr + 1, (valueT) offset, 4); | |
252b5132 RH |
3983 | } |
3984 | \f | |
3985 | /* Apply a fixup (fixS) to segment data, once it has been determined | |
3986 | by our caller that we have all the info we need to fix it up. | |
3987 | ||
3988 | On the 386, immediates, displacements, and data pointers are all in | |
3989 | the same (little-endian) format, so we don't need to care about which | |
3990 | we are handling. */ | |
3991 | ||
3992 | int | |
3993 | md_apply_fix3 (fixP, valp, seg) | |
47926f60 KH |
3994 | /* The fix we're to put in. */ |
3995 | fixS *fixP; | |
3996 | ||
3997 | /* Pointer to the value of the bits. */ | |
3998 | valueT *valp; | |
3999 | ||
4000 | /* Segment fix is from. */ | |
4001 | segT seg ATTRIBUTE_UNUSED; | |
252b5132 RH |
4002 | { |
4003 | register char *p = fixP->fx_where + fixP->fx_frag->fr_literal; | |
4004 | valueT value = *valp; | |
4005 | ||
e1b283bb | 4006 | #if defined (BFD_ASSEMBLER) && !defined (TE_Mach) |
93382f6d AM |
4007 | if (fixP->fx_pcrel) |
4008 | { | |
4009 | switch (fixP->fx_r_type) | |
4010 | { | |
5865bb77 ILT |
4011 | default: |
4012 | break; | |
4013 | ||
93382f6d AM |
4014 | case BFD_RELOC_32: |
4015 | fixP->fx_r_type = BFD_RELOC_32_PCREL; | |
4016 | break; | |
4017 | case BFD_RELOC_16: | |
4018 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
4019 | break; | |
4020 | case BFD_RELOC_8: | |
4021 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
4022 | break; | |
4023 | } | |
4024 | } | |
252b5132 | 4025 | |
0723899b ILT |
4026 | /* This is a hack. There should be a better way to handle this. |
4027 | This covers for the fact that bfd_install_relocation will | |
4028 | subtract the current location (for partial_inplace, PC relative | |
4029 | relocations); see more below. */ | |
93382f6d AM |
4030 | if ((fixP->fx_r_type == BFD_RELOC_32_PCREL |
4031 | || fixP->fx_r_type == BFD_RELOC_16_PCREL | |
4032 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) | |
4033 | && fixP->fx_addsy) | |
252b5132 RH |
4034 | { |
4035 | #ifndef OBJ_AOUT | |
4036 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
4037 | #ifdef TE_PE | |
4038 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
4039 | #endif | |
4040 | ) | |
4041 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
4042 | #endif | |
4043 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2f66722d | 4044 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) |
252b5132 | 4045 | { |
2f66722d AM |
4046 | segT fseg = S_GET_SEGMENT (fixP->fx_addsy); |
4047 | ||
4048 | if ((fseg == seg | |
4049 | || (symbol_section_p (fixP->fx_addsy) | |
4050 | && fseg != absolute_section)) | |
4051 | && ! S_IS_EXTERNAL (fixP->fx_addsy) | |
4052 | && ! S_IS_WEAK (fixP->fx_addsy) | |
4053 | && S_IS_DEFINED (fixP->fx_addsy) | |
4054 | && ! S_IS_COMMON (fixP->fx_addsy)) | |
4055 | { | |
4056 | /* Yes, we add the values in twice. This is because | |
4057 | bfd_perform_relocation subtracts them out again. I think | |
4058 | bfd_perform_relocation is broken, but I don't dare change | |
4059 | it. FIXME. */ | |
4060 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
4061 | } | |
252b5132 RH |
4062 | } |
4063 | #endif | |
4064 | #if defined (OBJ_COFF) && defined (TE_PE) | |
4065 | /* For some reason, the PE format does not store a section | |
24eab124 | 4066 | address offset for a PC relative symbol. */ |
252b5132 RH |
4067 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg) |
4068 | value += md_pcrel_from (fixP); | |
4069 | #endif | |
4070 | } | |
4071 | ||
4072 | /* Fix a few things - the dynamic linker expects certain values here, | |
47926f60 | 4073 | and we must not dissappoint it. */ |
252b5132 RH |
4074 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
4075 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour | |
4076 | && fixP->fx_addsy) | |
47926f60 KH |
4077 | switch (fixP->fx_r_type) |
4078 | { | |
4079 | case BFD_RELOC_386_PLT32: | |
4080 | /* Make the jump instruction point to the address of the operand. At | |
4081 | runtime we merely add the offset to the actual PLT entry. */ | |
4082 | value = -4; | |
4083 | break; | |
4084 | case BFD_RELOC_386_GOTPC: | |
4085 | ||
4086 | /* This is tough to explain. We end up with this one if we have | |
252b5132 RH |
4087 | * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal |
4088 | * here is to obtain the absolute address of the GOT, and it is strongly | |
4089 | * preferable from a performance point of view to avoid using a runtime | |
c3332e24 | 4090 | * relocation for this. The actual sequence of instructions often look |
252b5132 | 4091 | * something like: |
c3332e24 | 4092 | * |
24eab124 | 4093 | * call .L66 |
252b5132 | 4094 | * .L66: |
24eab124 AM |
4095 | * popl %ebx |
4096 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
c3332e24 | 4097 | * |
24eab124 | 4098 | * The call and pop essentially return the absolute address of |
252b5132 RH |
4099 | * the label .L66 and store it in %ebx. The linker itself will |
4100 | * ultimately change the first operand of the addl so that %ebx points to | |
4101 | * the GOT, but to keep things simple, the .o file must have this operand | |
4102 | * set so that it generates not the absolute address of .L66, but the | |
4103 | * absolute address of itself. This allows the linker itself simply | |
4104 | * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be | |
4105 | * added in, and the addend of the relocation is stored in the operand | |
4106 | * field for the instruction itself. | |
c3332e24 | 4107 | * |
24eab124 | 4108 | * Our job here is to fix the operand so that it would add the correct |
252b5132 RH |
4109 | * offset so that %ebx would point to itself. The thing that is tricky is |
4110 | * that .-.L66 will point to the beginning of the instruction, so we need | |
4111 | * to further modify the operand so that it will point to itself. | |
4112 | * There are other cases where you have something like: | |
c3332e24 | 4113 | * |
24eab124 | 4114 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] |
c3332e24 | 4115 | * |
252b5132 | 4116 | * and here no correction would be required. Internally in the assembler |
c3332e24 | 4117 | * we treat operands of this form as not being pcrel since the '.' is |
252b5132 RH |
4118 | * explicitly mentioned, and I wonder whether it would simplify matters |
4119 | * to do it this way. Who knows. In earlier versions of the PIC patches, | |
4120 | * the pcrel_adjust field was used to store the correction, but since the | |
47926f60 KH |
4121 | * expression is not pcrel, I felt it would be confusing to do it this |
4122 | * way. */ | |
4123 | ||
4124 | value -= 1; | |
4125 | break; | |
4126 | case BFD_RELOC_386_GOT32: | |
4127 | value = 0; /* Fully resolved at runtime. No addend. */ | |
4128 | break; | |
4129 | case BFD_RELOC_386_GOTOFF: | |
4130 | break; | |
4131 | ||
4132 | case BFD_RELOC_VTABLE_INHERIT: | |
4133 | case BFD_RELOC_VTABLE_ENTRY: | |
4134 | fixP->fx_done = 0; | |
4135 | return 1; | |
4136 | ||
4137 | default: | |
4138 | break; | |
4139 | } | |
4140 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
93382f6d | 4141 | *valp = value; |
47926f60 | 4142 | #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */ |
252b5132 RH |
4143 | md_number_to_chars (p, value, fixP->fx_size); |
4144 | ||
4145 | return 1; | |
4146 | } | |
252b5132 | 4147 | \f |
252b5132 RH |
4148 | #define MAX_LITTLENUMS 6 |
4149 | ||
47926f60 KH |
4150 | /* Turn the string pointed to by litP into a floating point constant |
4151 | of type TYPE, and emit the appropriate bytes. The number of | |
4152 | LITTLENUMS emitted is stored in *SIZEP. An error message is | |
4153 | returned, or NULL on OK. */ | |
4154 | ||
252b5132 RH |
4155 | char * |
4156 | md_atof (type, litP, sizeP) | |
2ab9b79e | 4157 | int type; |
252b5132 RH |
4158 | char *litP; |
4159 | int *sizeP; | |
4160 | { | |
4161 | int prec; | |
4162 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
4163 | LITTLENUM_TYPE *wordP; | |
4164 | char *t; | |
4165 | ||
4166 | switch (type) | |
4167 | { | |
4168 | case 'f': | |
4169 | case 'F': | |
4170 | prec = 2; | |
4171 | break; | |
4172 | ||
4173 | case 'd': | |
4174 | case 'D': | |
4175 | prec = 4; | |
4176 | break; | |
4177 | ||
4178 | case 'x': | |
4179 | case 'X': | |
4180 | prec = 5; | |
4181 | break; | |
4182 | ||
4183 | default: | |
4184 | *sizeP = 0; | |
4185 | return _("Bad call to md_atof ()"); | |
4186 | } | |
4187 | t = atof_ieee (input_line_pointer, type, words); | |
4188 | if (t) | |
4189 | input_line_pointer = t; | |
4190 | ||
4191 | *sizeP = prec * sizeof (LITTLENUM_TYPE); | |
4192 | /* This loops outputs the LITTLENUMs in REVERSE order; in accord with | |
4193 | the bigendian 386. */ | |
4194 | for (wordP = words + prec - 1; prec--;) | |
4195 | { | |
4196 | md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE)); | |
4197 | litP += sizeof (LITTLENUM_TYPE); | |
4198 | } | |
4199 | return 0; | |
4200 | } | |
4201 | \f | |
4202 | char output_invalid_buf[8]; | |
4203 | ||
252b5132 RH |
4204 | static char * |
4205 | output_invalid (c) | |
4206 | int c; | |
4207 | { | |
4208 | if (isprint (c)) | |
4209 | sprintf (output_invalid_buf, "'%c'", c); | |
4210 | else | |
4211 | sprintf (output_invalid_buf, "(0x%x)", (unsigned) c); | |
4212 | return output_invalid_buf; | |
4213 | } | |
4214 | ||
af6bdddf | 4215 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
4216 | |
4217 | static const reg_entry * | |
4218 | parse_register (reg_string, end_op) | |
4219 | char *reg_string; | |
4220 | char **end_op; | |
4221 | { | |
af6bdddf AM |
4222 | char *s = reg_string; |
4223 | char *p; | |
252b5132 RH |
4224 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
4225 | const reg_entry *r; | |
4226 | ||
4227 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
4228 | if (*s == REGISTER_PREFIX) | |
4229 | ++s; | |
4230 | ||
4231 | if (is_space_char (*s)) | |
4232 | ++s; | |
4233 | ||
4234 | p = reg_name_given; | |
af6bdddf | 4235 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
4236 | { |
4237 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
4238 | return (const reg_entry *) NULL; |
4239 | s++; | |
252b5132 RH |
4240 | } |
4241 | ||
6588847e DN |
4242 | /* For naked regs, make sure that we are not dealing with an identifier. |
4243 | This prevents confusing an identifier like `eax_var' with register | |
4244 | `eax'. */ | |
4245 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
4246 | return (const reg_entry *) NULL; | |
4247 | ||
af6bdddf | 4248 | *end_op = s; |
252b5132 RH |
4249 | |
4250 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
4251 | ||
5f47d35b | 4252 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
47926f60 | 4253 | if (r == i386_regtab /* %st is first entry of table */) |
5f47d35b | 4254 | { |
5f47d35b AM |
4255 | if (is_space_char (*s)) |
4256 | ++s; | |
4257 | if (*s == '(') | |
4258 | { | |
af6bdddf | 4259 | ++s; |
5f47d35b AM |
4260 | if (is_space_char (*s)) |
4261 | ++s; | |
4262 | if (*s >= '0' && *s <= '7') | |
4263 | { | |
4264 | r = &i386_float_regtab[*s - '0']; | |
af6bdddf | 4265 | ++s; |
5f47d35b AM |
4266 | if (is_space_char (*s)) |
4267 | ++s; | |
4268 | if (*s == ')') | |
4269 | { | |
4270 | *end_op = s + 1; | |
4271 | return r; | |
4272 | } | |
5f47d35b | 4273 | } |
47926f60 | 4274 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
4275 | return (const reg_entry *) NULL; |
4276 | } | |
4277 | } | |
4278 | ||
252b5132 RH |
4279 | return r; |
4280 | } | |
4281 | \f | |
4cc782b5 | 4282 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
65172ab8 | 4283 | const char *md_shortopts = "kVQ:sq"; |
252b5132 | 4284 | #else |
65172ab8 | 4285 | const char *md_shortopts = "q"; |
252b5132 RH |
4286 | #endif |
4287 | struct option md_longopts[] = { | |
4288 | {NULL, no_argument, NULL, 0} | |
4289 | }; | |
4290 | size_t md_longopts_size = sizeof (md_longopts); | |
4291 | ||
4292 | int | |
4293 | md_parse_option (c, arg) | |
4294 | int c; | |
ab9da554 | 4295 | char *arg ATTRIBUTE_UNUSED; |
252b5132 RH |
4296 | { |
4297 | switch (c) | |
4298 | { | |
a38cf1db AM |
4299 | case 'q': |
4300 | quiet_warnings = 1; | |
252b5132 RH |
4301 | break; |
4302 | ||
4303 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
4304 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
4305 | should be emitted or not. FIXME: Not implemented. */ | |
4306 | case 'Q': | |
252b5132 RH |
4307 | break; |
4308 | ||
4309 | /* -V: SVR4 argument to print version ID. */ | |
4310 | case 'V': | |
4311 | print_version_id (); | |
4312 | break; | |
4313 | ||
a38cf1db AM |
4314 | /* -k: Ignore for FreeBSD compatibility. */ |
4315 | case 'k': | |
252b5132 | 4316 | break; |
4cc782b5 ILT |
4317 | |
4318 | case 's': | |
4319 | /* -s: On i386 Solaris, this tells the native assembler to use | |
4320 | .stab instead of .stab.excl. We always use .stab anyhow. */ | |
4321 | break; | |
252b5132 RH |
4322 | #endif |
4323 | ||
4324 | default: | |
4325 | return 0; | |
4326 | } | |
4327 | return 1; | |
4328 | } | |
4329 | ||
4330 | void | |
4331 | md_show_usage (stream) | |
4332 | FILE *stream; | |
4333 | { | |
4cc782b5 ILT |
4334 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
4335 | fprintf (stream, _("\ | |
a38cf1db AM |
4336 | -Q ignored\n\ |
4337 | -V print assembler version number\n\ | |
4338 | -k ignored\n\ | |
4339 | -q quieten some warnings\n\ | |
4340 | -s ignored\n")); | |
4341 | #else | |
4342 | fprintf (stream, _("\ | |
4343 | -q quieten some warnings\n")); | |
4cc782b5 | 4344 | #endif |
252b5132 RH |
4345 | } |
4346 | ||
4347 | #ifdef BFD_ASSEMBLER | |
4c63da97 AM |
4348 | #if ((defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_COFF)) \ |
4349 | || (defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_AOUT)) \ | |
4350 | || (defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT))) | |
252b5132 RH |
4351 | |
4352 | /* Pick the target format to use. */ | |
4353 | ||
47926f60 | 4354 | const char * |
252b5132 RH |
4355 | i386_target_format () |
4356 | { | |
4357 | switch (OUTPUT_FLAVOR) | |
4358 | { | |
4c63da97 AM |
4359 | #ifdef OBJ_MAYBE_AOUT |
4360 | case bfd_target_aout_flavour: | |
47926f60 | 4361 | return AOUT_TARGET_FORMAT; |
4c63da97 AM |
4362 | #endif |
4363 | #ifdef OBJ_MAYBE_COFF | |
252b5132 RH |
4364 | case bfd_target_coff_flavour: |
4365 | return "coff-i386"; | |
4c63da97 AM |
4366 | #endif |
4367 | #ifdef OBJ_MAYBE_ELF | |
252b5132 RH |
4368 | case bfd_target_elf_flavour: |
4369 | return "elf32-i386"; | |
4c63da97 | 4370 | #endif |
252b5132 RH |
4371 | default: |
4372 | abort (); | |
4373 | return NULL; | |
4374 | } | |
4375 | } | |
4376 | ||
47926f60 KH |
4377 | #endif /* OBJ_MAYBE_ more than one */ |
4378 | #endif /* BFD_ASSEMBLER */ | |
252b5132 | 4379 | \f |
252b5132 RH |
4380 | symbolS * |
4381 | md_undefined_symbol (name) | |
4382 | char *name; | |
4383 | { | |
18dc2407 ILT |
4384 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
4385 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
4386 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
4387 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
4388 | { |
4389 | if (!GOT_symbol) | |
4390 | { | |
4391 | if (symbol_find (name)) | |
4392 | as_bad (_("GOT already in symbol table")); | |
4393 | GOT_symbol = symbol_new (name, undefined_section, | |
4394 | (valueT) 0, &zero_address_frag); | |
4395 | }; | |
4396 | return GOT_symbol; | |
4397 | } | |
252b5132 RH |
4398 | return 0; |
4399 | } | |
4400 | ||
4401 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 4402 | |
252b5132 RH |
4403 | valueT |
4404 | md_section_align (segment, size) | |
ab9da554 | 4405 | segT segment ATTRIBUTE_UNUSED; |
252b5132 RH |
4406 | valueT size; |
4407 | { | |
252b5132 | 4408 | #ifdef BFD_ASSEMBLER |
4c63da97 AM |
4409 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
4410 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
4411 | { | |
4412 | /* For a.out, force the section size to be aligned. If we don't do | |
4413 | this, BFD will align it for us, but it will not write out the | |
4414 | final bytes of the section. This may be a bug in BFD, but it is | |
4415 | easier to fix it here since that is how the other a.out targets | |
4416 | work. */ | |
4417 | int align; | |
4418 | ||
4419 | align = bfd_get_section_alignment (stdoutput, segment); | |
4420 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); | |
4421 | } | |
252b5132 RH |
4422 | #endif |
4423 | #endif | |
4424 | ||
4425 | return size; | |
4426 | } | |
4427 | ||
4428 | /* On the i386, PC-relative offsets are relative to the start of the | |
4429 | next instruction. That is, the address of the offset, plus its | |
4430 | size, since the offset is always the last part of the insn. */ | |
4431 | ||
4432 | long | |
4433 | md_pcrel_from (fixP) | |
4434 | fixS *fixP; | |
4435 | { | |
4436 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
4437 | } | |
4438 | ||
4439 | #ifndef I386COFF | |
4440 | ||
4441 | static void | |
4442 | s_bss (ignore) | |
ab9da554 | 4443 | int ignore ATTRIBUTE_UNUSED; |
252b5132 RH |
4444 | { |
4445 | register int temp; | |
4446 | ||
4447 | temp = get_absolute_expression (); | |
4448 | subseg_set (bss_section, (subsegT) temp); | |
4449 | demand_empty_rest_of_line (); | |
4450 | } | |
4451 | ||
4452 | #endif | |
4453 | ||
252b5132 RH |
4454 | #ifdef BFD_ASSEMBLER |
4455 | ||
4456 | void | |
4457 | i386_validate_fix (fixp) | |
4458 | fixS *fixp; | |
4459 | { | |
4460 | if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol) | |
4461 | { | |
4462 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
4463 | fixp->fx_subsy = 0; | |
4464 | } | |
4465 | } | |
4466 | ||
252b5132 RH |
4467 | arelent * |
4468 | tc_gen_reloc (section, fixp) | |
ab9da554 | 4469 | asection *section ATTRIBUTE_UNUSED; |
252b5132 RH |
4470 | fixS *fixp; |
4471 | { | |
4472 | arelent *rel; | |
4473 | bfd_reloc_code_real_type code; | |
4474 | ||
4475 | switch (fixp->fx_r_type) | |
4476 | { | |
4477 | case BFD_RELOC_386_PLT32: | |
4478 | case BFD_RELOC_386_GOT32: | |
4479 | case BFD_RELOC_386_GOTOFF: | |
4480 | case BFD_RELOC_386_GOTPC: | |
4481 | case BFD_RELOC_RVA: | |
4482 | case BFD_RELOC_VTABLE_ENTRY: | |
4483 | case BFD_RELOC_VTABLE_INHERIT: | |
4484 | code = fixp->fx_r_type; | |
4485 | break; | |
4486 | default: | |
93382f6d | 4487 | if (fixp->fx_pcrel) |
252b5132 | 4488 | { |
93382f6d AM |
4489 | switch (fixp->fx_size) |
4490 | { | |
4491 | default: | |
d0b47220 | 4492 | as_bad (_("can not do %d byte pc-relative relocation"), |
93382f6d AM |
4493 | fixp->fx_size); |
4494 | code = BFD_RELOC_32_PCREL; | |
4495 | break; | |
4496 | case 1: code = BFD_RELOC_8_PCREL; break; | |
4497 | case 2: code = BFD_RELOC_16_PCREL; break; | |
4498 | case 4: code = BFD_RELOC_32_PCREL; break; | |
4499 | } | |
4500 | } | |
4501 | else | |
4502 | { | |
4503 | switch (fixp->fx_size) | |
4504 | { | |
4505 | default: | |
d0b47220 | 4506 | as_bad (_("can not do %d byte relocation"), fixp->fx_size); |
93382f6d AM |
4507 | code = BFD_RELOC_32; |
4508 | break; | |
4509 | case 1: code = BFD_RELOC_8; break; | |
4510 | case 2: code = BFD_RELOC_16; break; | |
4511 | case 4: code = BFD_RELOC_32; break; | |
4512 | } | |
252b5132 RH |
4513 | } |
4514 | break; | |
4515 | } | |
252b5132 RH |
4516 | |
4517 | if (code == BFD_RELOC_32 | |
4518 | && GOT_symbol | |
4519 | && fixp->fx_addsy == GOT_symbol) | |
4520 | code = BFD_RELOC_386_GOTPC; | |
4521 | ||
4522 | rel = (arelent *) xmalloc (sizeof (arelent)); | |
49309057 ILT |
4523 | rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
4524 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
4525 | |
4526 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
4527 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
4528 | vtable entry to be used in the relocation's section offset. */ | |
4529 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
4530 | rel->address = fixp->fx_offset; | |
4531 | ||
4532 | if (fixp->fx_pcrel) | |
4533 | rel->addend = fixp->fx_addnumber; | |
4534 | else | |
4535 | rel->addend = 0; | |
4536 | ||
4537 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); | |
4538 | if (rel->howto == NULL) | |
4539 | { | |
4540 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 4541 | _("cannot represent relocation type %s"), |
252b5132 RH |
4542 | bfd_get_reloc_code_name (code)); |
4543 | /* Set howto to a garbage value so that we can keep going. */ | |
4544 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
4545 | assert (rel->howto != NULL); | |
4546 | } | |
4547 | ||
4548 | return rel; | |
4549 | } | |
4550 | ||
47926f60 | 4551 | #else /* ! BFD_ASSEMBLER */ |
252b5132 RH |
4552 | |
4553 | #if (defined(OBJ_AOUT) | defined(OBJ_BOUT)) | |
4554 | void | |
4555 | tc_aout_fix_to_chars (where, fixP, segment_address_in_file) | |
4556 | char *where; | |
4557 | fixS *fixP; | |
4558 | relax_addressT segment_address_in_file; | |
4559 | { | |
47926f60 KH |
4560 | /* In: length of relocation (or of address) in chars: 1, 2 or 4. |
4561 | Out: GNU LD relocation length code: 0, 1, or 2. */ | |
252b5132 | 4562 | |
47926f60 | 4563 | static const unsigned char nbytes_r_length[] = { 42, 0, 1, 42, 2 }; |
252b5132 RH |
4564 | long r_symbolnum; |
4565 | ||
4566 | know (fixP->fx_addsy != NULL); | |
4567 | ||
4568 | md_number_to_chars (where, | |
4569 | (valueT) (fixP->fx_frag->fr_address | |
4570 | + fixP->fx_where - segment_address_in_file), | |
4571 | 4); | |
4572 | ||
4573 | r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy) | |
4574 | ? S_GET_TYPE (fixP->fx_addsy) | |
4575 | : fixP->fx_addsy->sy_number); | |
4576 | ||
4577 | where[6] = (r_symbolnum >> 16) & 0x0ff; | |
4578 | where[5] = (r_symbolnum >> 8) & 0x0ff; | |
4579 | where[4] = r_symbolnum & 0x0ff; | |
4580 | where[7] = ((((!S_IS_DEFINED (fixP->fx_addsy)) << 3) & 0x08) | |
4581 | | ((nbytes_r_length[fixP->fx_size] << 1) & 0x06) | |
4582 | | (((fixP->fx_pcrel << 0) & 0x01) & 0x0f)); | |
4583 | } | |
4584 | ||
47926f60 | 4585 | #endif /* OBJ_AOUT or OBJ_BOUT. */ |
252b5132 RH |
4586 | |
4587 | #if defined (I386COFF) | |
4588 | ||
4589 | short | |
4590 | tc_coff_fix2rtype (fixP) | |
4591 | fixS *fixP; | |
4592 | { | |
4593 | if (fixP->fx_r_type == R_IMAGEBASE) | |
4594 | return R_IMAGEBASE; | |
4595 | ||
4596 | return (fixP->fx_pcrel ? | |
4597 | (fixP->fx_size == 1 ? R_PCRBYTE : | |
4598 | fixP->fx_size == 2 ? R_PCRWORD : | |
4599 | R_PCRLONG) : | |
4600 | (fixP->fx_size == 1 ? R_RELBYTE : | |
4601 | fixP->fx_size == 2 ? R_RELWORD : | |
4602 | R_DIR32)); | |
4603 | } | |
4604 | ||
4605 | int | |
4606 | tc_coff_sizemachdep (frag) | |
4607 | fragS *frag; | |
4608 | { | |
4609 | if (frag->fr_next) | |
4610 | return (frag->fr_next->fr_address - frag->fr_address); | |
4611 | else | |
4612 | return 0; | |
4613 | } | |
4614 | ||
47926f60 | 4615 | #endif /* I386COFF */ |
252b5132 | 4616 | |
47926f60 | 4617 | #endif /* ! BFD_ASSEMBLER */ |