Commit | Line | Data |
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b534c6d3 | 1 | /* tc-i386.c -- Assemble code for the Intel 80386 |
219d1afa | 2 | Copyright (C) 1989-2018 Free Software Foundation, Inc. |
252b5132 RH |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
19 | 02110-1301, USA. */ | |
252b5132 | 20 | |
47926f60 KH |
21 | /* Intel 80386 machine specific gas. |
22 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 23 | x86_64 support by Jan Hubicka (jh@suse.cz) |
0f10071e | 24 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
47926f60 KH |
25 | Bugs & suggestions are completely welcome. This is free software. |
26 | Please help us make it better. */ | |
252b5132 | 27 | |
252b5132 | 28 | #include "as.h" |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | #include "subsegs.h" |
316e2c05 | 31 | #include "dwarf2dbg.h" |
54cfded0 | 32 | #include "dw2gencfi.h" |
d2b2c203 | 33 | #include "elf/x86-64.h" |
40fb9820 | 34 | #include "opcodes/i386-init.h" |
252b5132 | 35 | |
252b5132 RH |
36 | #ifndef REGISTER_WARNINGS |
37 | #define REGISTER_WARNINGS 1 | |
38 | #endif | |
39 | ||
c3332e24 | 40 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 41 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
42 | #endif |
43 | ||
29b0f896 AM |
44 | #ifndef DEFAULT_ARCH |
45 | #define DEFAULT_ARCH "i386" | |
246fcdee | 46 | #endif |
252b5132 | 47 | |
edde18a5 AM |
48 | #ifndef INLINE |
49 | #if __GNUC__ >= 2 | |
50 | #define INLINE __inline__ | |
51 | #else | |
52 | #define INLINE | |
53 | #endif | |
54 | #endif | |
55 | ||
6305a203 L |
56 | /* Prefixes will be emitted in the order defined below. |
57 | WAIT_PREFIX must be the first prefix since FWAIT is really is an | |
58 | instruction, and so must come before any prefixes. | |
59 | The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, | |
42164a71 | 60 | REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */ |
6305a203 L |
61 | #define WAIT_PREFIX 0 |
62 | #define SEG_PREFIX 1 | |
63 | #define ADDR_PREFIX 2 | |
64 | #define DATA_PREFIX 3 | |
c32fa91d | 65 | #define REP_PREFIX 4 |
42164a71 | 66 | #define HLE_PREFIX REP_PREFIX |
7e8b059b | 67 | #define BND_PREFIX REP_PREFIX |
c32fa91d | 68 | #define LOCK_PREFIX 5 |
4e9ac44a L |
69 | #define REX_PREFIX 6 /* must come last. */ |
70 | #define MAX_PREFIXES 7 /* max prefixes per opcode */ | |
6305a203 L |
71 | |
72 | /* we define the syntax here (modulo base,index,scale syntax) */ | |
73 | #define REGISTER_PREFIX '%' | |
74 | #define IMMEDIATE_PREFIX '$' | |
75 | #define ABSOLUTE_PREFIX '*' | |
76 | ||
77 | /* these are the instruction mnemonic suffixes in AT&T syntax or | |
78 | memory operand size in Intel syntax. */ | |
79 | #define WORD_MNEM_SUFFIX 'w' | |
80 | #define BYTE_MNEM_SUFFIX 'b' | |
81 | #define SHORT_MNEM_SUFFIX 's' | |
82 | #define LONG_MNEM_SUFFIX 'l' | |
83 | #define QWORD_MNEM_SUFFIX 'q' | |
84 | #define XMMWORD_MNEM_SUFFIX 'x' | |
c0f3af97 | 85 | #define YMMWORD_MNEM_SUFFIX 'y' |
43234a1e | 86 | #define ZMMWORD_MNEM_SUFFIX 'z' |
6305a203 L |
87 | /* Intel Syntax. Use a non-ascii letter since since it never appears |
88 | in instructions. */ | |
89 | #define LONG_DOUBLE_MNEM_SUFFIX '\1' | |
90 | ||
91 | #define END_OF_INSN '\0' | |
92 | ||
93 | /* | |
94 | 'templates' is for grouping together 'template' structures for opcodes | |
95 | of the same name. This is only used for storing the insns in the grand | |
96 | ole hash table of insns. | |
97 | The templates themselves start at START and range up to (but not including) | |
98 | END. | |
99 | */ | |
100 | typedef struct | |
101 | { | |
d3ce72d0 NC |
102 | const insn_template *start; |
103 | const insn_template *end; | |
6305a203 L |
104 | } |
105 | templates; | |
106 | ||
107 | /* 386 operand encoding bytes: see 386 book for details of this. */ | |
108 | typedef struct | |
109 | { | |
110 | unsigned int regmem; /* codes register or memory operand */ | |
111 | unsigned int reg; /* codes register operand (or extended opcode) */ | |
112 | unsigned int mode; /* how to interpret regmem & reg */ | |
113 | } | |
114 | modrm_byte; | |
115 | ||
116 | /* x86-64 extension prefix. */ | |
117 | typedef int rex_byte; | |
118 | ||
6305a203 L |
119 | /* 386 opcode byte to code indirect addressing. */ |
120 | typedef struct | |
121 | { | |
122 | unsigned base; | |
123 | unsigned index; | |
124 | unsigned scale; | |
125 | } | |
126 | sib_byte; | |
127 | ||
6305a203 L |
128 | /* x86 arch names, types and features */ |
129 | typedef struct | |
130 | { | |
131 | const char *name; /* arch name */ | |
8a2c8fef | 132 | unsigned int len; /* arch string length */ |
6305a203 L |
133 | enum processor_type type; /* arch type */ |
134 | i386_cpu_flags flags; /* cpu feature flags */ | |
8a2c8fef | 135 | unsigned int skip; /* show_arch should skip this. */ |
6305a203 L |
136 | } |
137 | arch_entry; | |
138 | ||
293f5f65 L |
139 | /* Used to turn off indicated flags. */ |
140 | typedef struct | |
141 | { | |
142 | const char *name; /* arch name */ | |
143 | unsigned int len; /* arch string length */ | |
144 | i386_cpu_flags flags; /* cpu feature flags */ | |
145 | } | |
146 | noarch_entry; | |
147 | ||
78f12dd3 | 148 | static void update_code_flag (int, int); |
e3bb37b5 L |
149 | static void set_code_flag (int); |
150 | static void set_16bit_gcc_code_flag (int); | |
151 | static void set_intel_syntax (int); | |
1efbbeb4 | 152 | static void set_intel_mnemonic (int); |
db51cc60 | 153 | static void set_allow_index_reg (int); |
7bab8ab5 | 154 | static void set_check (int); |
e3bb37b5 | 155 | static void set_cpu_arch (int); |
6482c264 | 156 | #ifdef TE_PE |
e3bb37b5 | 157 | static void pe_directive_secrel (int); |
6482c264 | 158 | #endif |
e3bb37b5 L |
159 | static void signed_cons (int); |
160 | static char *output_invalid (int c); | |
ee86248c JB |
161 | static int i386_finalize_immediate (segT, expressionS *, i386_operand_type, |
162 | const char *); | |
163 | static int i386_finalize_displacement (segT, expressionS *, i386_operand_type, | |
164 | const char *); | |
a7619375 | 165 | static int i386_att_operand (char *); |
e3bb37b5 | 166 | static int i386_intel_operand (char *, int); |
ee86248c JB |
167 | static int i386_intel_simplify (expressionS *); |
168 | static int i386_intel_parse_name (const char *, expressionS *); | |
e3bb37b5 L |
169 | static const reg_entry *parse_register (char *, char **); |
170 | static char *parse_insn (char *, char *); | |
171 | static char *parse_operands (char *, const char *); | |
172 | static void swap_operands (void); | |
4d456e3d | 173 | static void swap_2_operands (int, int); |
e3bb37b5 L |
174 | static void optimize_imm (void); |
175 | static void optimize_disp (void); | |
83b16ac6 | 176 | static const insn_template *match_template (char); |
e3bb37b5 L |
177 | static int check_string (void); |
178 | static int process_suffix (void); | |
179 | static int check_byte_reg (void); | |
180 | static int check_long_reg (void); | |
181 | static int check_qword_reg (void); | |
182 | static int check_word_reg (void); | |
183 | static int finalize_imm (void); | |
184 | static int process_operands (void); | |
185 | static const seg_entry *build_modrm_byte (void); | |
186 | static void output_insn (void); | |
187 | static void output_imm (fragS *, offsetT); | |
188 | static void output_disp (fragS *, offsetT); | |
29b0f896 | 189 | #ifndef I386COFF |
e3bb37b5 | 190 | static void s_bss (int); |
252b5132 | 191 | #endif |
17d4e2a2 L |
192 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
193 | static void handle_large_common (int small ATTRIBUTE_UNUSED); | |
194 | #endif | |
252b5132 | 195 | |
a847613f | 196 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 197 | |
43234a1e L |
198 | /* This struct describes rounding control and SAE in the instruction. */ |
199 | struct RC_Operation | |
200 | { | |
201 | enum rc_type | |
202 | { | |
203 | rne = 0, | |
204 | rd, | |
205 | ru, | |
206 | rz, | |
207 | saeonly | |
208 | } type; | |
209 | int operand; | |
210 | }; | |
211 | ||
212 | static struct RC_Operation rc_op; | |
213 | ||
214 | /* The struct describes masking, applied to OPERAND in the instruction. | |
215 | MASK is a pointer to the corresponding mask register. ZEROING tells | |
216 | whether merging or zeroing mask is used. */ | |
217 | struct Mask_Operation | |
218 | { | |
219 | const reg_entry *mask; | |
220 | unsigned int zeroing; | |
221 | /* The operand where this operation is associated. */ | |
222 | int operand; | |
223 | }; | |
224 | ||
225 | static struct Mask_Operation mask_op; | |
226 | ||
227 | /* The struct describes broadcasting, applied to OPERAND. FACTOR is | |
228 | broadcast factor. */ | |
229 | struct Broadcast_Operation | |
230 | { | |
231 | /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */ | |
232 | int type; | |
233 | ||
234 | /* Index of broadcasted operand. */ | |
235 | int operand; | |
236 | }; | |
237 | ||
238 | static struct Broadcast_Operation broadcast_op; | |
239 | ||
c0f3af97 L |
240 | /* VEX prefix. */ |
241 | typedef struct | |
242 | { | |
43234a1e L |
243 | /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */ |
244 | unsigned char bytes[4]; | |
c0f3af97 L |
245 | unsigned int length; |
246 | /* Destination or source register specifier. */ | |
247 | const reg_entry *register_specifier; | |
248 | } vex_prefix; | |
249 | ||
252b5132 | 250 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 251 | i386_insn. */ |
252b5132 | 252 | |
520dc8e8 AM |
253 | union i386_op |
254 | { | |
255 | expressionS *disps; | |
256 | expressionS *imms; | |
257 | const reg_entry *regs; | |
258 | }; | |
259 | ||
a65babc9 L |
260 | enum i386_error |
261 | { | |
86e026a4 | 262 | operand_size_mismatch, |
a65babc9 L |
263 | operand_type_mismatch, |
264 | register_type_mismatch, | |
265 | number_of_operands_mismatch, | |
266 | invalid_instruction_suffix, | |
267 | bad_imm4, | |
268 | old_gcc_only, | |
269 | unsupported_with_intel_mnemonic, | |
270 | unsupported_syntax, | |
6c30d220 L |
271 | unsupported, |
272 | invalid_vsib_address, | |
7bab8ab5 | 273 | invalid_vector_register_set, |
43234a1e L |
274 | unsupported_vector_index_register, |
275 | unsupported_broadcast, | |
276 | broadcast_not_on_src_operand, | |
277 | broadcast_needed, | |
278 | unsupported_masking, | |
279 | mask_not_on_destination, | |
280 | no_default_mask, | |
281 | unsupported_rc_sae, | |
282 | rc_sae_operand_not_last_imm, | |
283 | invalid_register_operand, | |
a65babc9 L |
284 | }; |
285 | ||
252b5132 RH |
286 | struct _i386_insn |
287 | { | |
47926f60 | 288 | /* TM holds the template for the insn were currently assembling. */ |
d3ce72d0 | 289 | insn_template tm; |
252b5132 | 290 | |
7d5e4556 L |
291 | /* SUFFIX holds the instruction size suffix for byte, word, dword |
292 | or qword, if given. */ | |
252b5132 RH |
293 | char suffix; |
294 | ||
47926f60 | 295 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
296 | unsigned int operands; |
297 | ||
298 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
299 | of given register, displacement, memory operands and immediate | |
47926f60 | 300 | operands. */ |
252b5132 RH |
301 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
302 | ||
303 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 304 | use OP[i] for the corresponding operand. */ |
40fb9820 | 305 | i386_operand_type types[MAX_OPERANDS]; |
252b5132 | 306 | |
520dc8e8 AM |
307 | /* Displacement expression, immediate expression, or register for each |
308 | operand. */ | |
309 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 310 | |
3e73aa7c JH |
311 | /* Flags for operands. */ |
312 | unsigned int flags[MAX_OPERANDS]; | |
313 | #define Operand_PCrel 1 | |
314 | ||
252b5132 | 315 | /* Relocation type for operand */ |
f86103b7 | 316 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
252b5132 | 317 | |
252b5132 RH |
318 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
319 | the base index byte below. */ | |
320 | const reg_entry *base_reg; | |
321 | const reg_entry *index_reg; | |
322 | unsigned int log2_scale_factor; | |
323 | ||
324 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 325 | explicit segment overrides are given. */ |
ce8a8b2f | 326 | const seg_entry *seg[2]; |
252b5132 | 327 | |
8325cc63 JB |
328 | /* Copied first memory operand string, for re-checking. */ |
329 | char *memop1_string; | |
330 | ||
252b5132 RH |
331 | /* PREFIX holds all the given prefix opcodes (usually null). |
332 | PREFIXES is the number of prefix opcodes. */ | |
333 | unsigned int prefixes; | |
334 | unsigned char prefix[MAX_PREFIXES]; | |
335 | ||
336 | /* RM and SIB are the modrm byte and the sib byte where the | |
c1e679ec | 337 | addressing modes of this insn are encoded. */ |
252b5132 | 338 | modrm_byte rm; |
3e73aa7c | 339 | rex_byte rex; |
43234a1e | 340 | rex_byte vrex; |
252b5132 | 341 | sib_byte sib; |
c0f3af97 | 342 | vex_prefix vex; |
b6169b20 | 343 | |
43234a1e L |
344 | /* Masking attributes. */ |
345 | struct Mask_Operation *mask; | |
346 | ||
347 | /* Rounding control and SAE attributes. */ | |
348 | struct RC_Operation *rounding; | |
349 | ||
350 | /* Broadcasting attributes. */ | |
351 | struct Broadcast_Operation *broadcast; | |
352 | ||
353 | /* Compressed disp8*N attribute. */ | |
354 | unsigned int memshift; | |
355 | ||
86fa6981 L |
356 | /* Prefer load or store in encoding. */ |
357 | enum | |
358 | { | |
359 | dir_encoding_default = 0, | |
360 | dir_encoding_load, | |
361 | dir_encoding_store | |
362 | } dir_encoding; | |
891edac4 | 363 | |
a501d77e L |
364 | /* Prefer 8bit or 32bit displacement in encoding. */ |
365 | enum | |
366 | { | |
367 | disp_encoding_default = 0, | |
368 | disp_encoding_8bit, | |
369 | disp_encoding_32bit | |
370 | } disp_encoding; | |
f8a5c266 | 371 | |
6b6b6807 L |
372 | /* Prefer the REX byte in encoding. */ |
373 | bfd_boolean rex_encoding; | |
374 | ||
86fa6981 L |
375 | /* How to encode vector instructions. */ |
376 | enum | |
377 | { | |
378 | vex_encoding_default = 0, | |
379 | vex_encoding_vex2, | |
380 | vex_encoding_vex3, | |
381 | vex_encoding_evex | |
382 | } vec_encoding; | |
383 | ||
d5de92cf L |
384 | /* REP prefix. */ |
385 | const char *rep_prefix; | |
386 | ||
165de32a L |
387 | /* HLE prefix. */ |
388 | const char *hle_prefix; | |
42164a71 | 389 | |
7e8b059b L |
390 | /* Have BND prefix. */ |
391 | const char *bnd_prefix; | |
392 | ||
04ef582a L |
393 | /* Have NOTRACK prefix. */ |
394 | const char *notrack_prefix; | |
395 | ||
891edac4 | 396 | /* Error message. */ |
a65babc9 | 397 | enum i386_error error; |
252b5132 RH |
398 | }; |
399 | ||
400 | typedef struct _i386_insn i386_insn; | |
401 | ||
43234a1e L |
402 | /* Link RC type with corresponding string, that'll be looked for in |
403 | asm. */ | |
404 | struct RC_name | |
405 | { | |
406 | enum rc_type type; | |
407 | const char *name; | |
408 | unsigned int len; | |
409 | }; | |
410 | ||
411 | static const struct RC_name RC_NamesTable[] = | |
412 | { | |
413 | { rne, STRING_COMMA_LEN ("rn-sae") }, | |
414 | { rd, STRING_COMMA_LEN ("rd-sae") }, | |
415 | { ru, STRING_COMMA_LEN ("ru-sae") }, | |
416 | { rz, STRING_COMMA_LEN ("rz-sae") }, | |
417 | { saeonly, STRING_COMMA_LEN ("sae") }, | |
418 | }; | |
419 | ||
252b5132 RH |
420 | /* List of chars besides those in app.c:symbol_chars that can start an |
421 | operand. Used to prevent the scrubber eating vital white-space. */ | |
86fa6981 | 422 | const char extra_symbol_chars[] = "*%-([{}" |
252b5132 | 423 | #ifdef LEX_AT |
32137342 NC |
424 | "@" |
425 | #endif | |
426 | #ifdef LEX_QM | |
427 | "?" | |
252b5132 | 428 | #endif |
32137342 | 429 | ; |
252b5132 | 430 | |
29b0f896 AM |
431 | #if (defined (TE_I386AIX) \ |
432 | || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ | |
3896cfd5 | 433 | && !defined (TE_GNU) \ |
29b0f896 | 434 | && !defined (TE_LINUX) \ |
8d63c93e RM |
435 | && !defined (TE_NACL) \ |
436 | && !defined (TE_NETWARE) \ | |
29b0f896 | 437 | && !defined (TE_FreeBSD) \ |
5b806d27 | 438 | && !defined (TE_DragonFly) \ |
29b0f896 | 439 | && !defined (TE_NetBSD))) |
252b5132 | 440 | /* This array holds the chars that always start a comment. If the |
b3b91714 AM |
441 | pre-processor is disabled, these aren't very useful. The option |
442 | --divide will remove '/' from this list. */ | |
443 | const char *i386_comment_chars = "#/"; | |
444 | #define SVR4_COMMENT_CHARS 1 | |
252b5132 | 445 | #define PREFIX_SEPARATOR '\\' |
252b5132 | 446 | |
b3b91714 AM |
447 | #else |
448 | const char *i386_comment_chars = "#"; | |
449 | #define PREFIX_SEPARATOR '/' | |
450 | #endif | |
451 | ||
252b5132 RH |
452 | /* This array holds the chars that only start a comment at the beginning of |
453 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
454 | .line and .file directives will appear in the pre-processed output. |
455 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 456 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
457 | #NO_APP at the beginning of its output. |
458 | Also note that comments started like this one will always work if | |
252b5132 | 459 | '/' isn't otherwise defined. */ |
b3b91714 | 460 | const char line_comment_chars[] = "#/"; |
252b5132 | 461 | |
63a0b638 | 462 | const char line_separator_chars[] = ";"; |
252b5132 | 463 | |
ce8a8b2f AM |
464 | /* Chars that can be used to separate mant from exp in floating point |
465 | nums. */ | |
252b5132 RH |
466 | const char EXP_CHARS[] = "eE"; |
467 | ||
ce8a8b2f AM |
468 | /* Chars that mean this number is a floating point constant |
469 | As in 0f12.456 | |
470 | or 0d1.2345e12. */ | |
252b5132 RH |
471 | const char FLT_CHARS[] = "fFdDxX"; |
472 | ||
ce8a8b2f | 473 | /* Tables for lexical analysis. */ |
252b5132 RH |
474 | static char mnemonic_chars[256]; |
475 | static char register_chars[256]; | |
476 | static char operand_chars[256]; | |
477 | static char identifier_chars[256]; | |
478 | static char digit_chars[256]; | |
479 | ||
ce8a8b2f | 480 | /* Lexical macros. */ |
252b5132 RH |
481 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
482 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
483 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
484 | #define is_space_char(x) ((x) == ' ') | |
485 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
486 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
487 | ||
0234cb7c | 488 | /* All non-digit non-letter characters that may occur in an operand. */ |
252b5132 RH |
489 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
490 | ||
491 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
492 | effect this we maintain a stack of saved characters that we've smashed | |
493 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 494 | assembler instruction). */ |
252b5132 | 495 | static char save_stack[32]; |
ce8a8b2f | 496 | static char *save_stack_p; |
252b5132 RH |
497 | #define END_STRING_AND_SAVE(s) \ |
498 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
499 | #define RESTORE_END_STRING(s) \ | |
500 | do { *(s) = *--save_stack_p; } while (0) | |
501 | ||
47926f60 | 502 | /* The instruction we're assembling. */ |
252b5132 RH |
503 | static i386_insn i; |
504 | ||
505 | /* Possible templates for current insn. */ | |
506 | static const templates *current_templates; | |
507 | ||
31b2323c L |
508 | /* Per instruction expressionS buffers: max displacements & immediates. */ |
509 | static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; | |
510 | static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; | |
252b5132 | 511 | |
47926f60 | 512 | /* Current operand we are working on. */ |
ee86248c | 513 | static int this_operand = -1; |
252b5132 | 514 | |
3e73aa7c JH |
515 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
516 | these. */ | |
517 | ||
518 | enum flag_code { | |
519 | CODE_32BIT, | |
520 | CODE_16BIT, | |
521 | CODE_64BIT }; | |
522 | ||
523 | static enum flag_code flag_code; | |
4fa24527 | 524 | static unsigned int object_64bit; |
862be3fb | 525 | static unsigned int disallow_64bit_reloc; |
3e73aa7c JH |
526 | static int use_rela_relocations = 0; |
527 | ||
7af8ed2d NC |
528 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
529 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ | |
530 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) | |
531 | ||
351f65ca L |
532 | /* The ELF ABI to use. */ |
533 | enum x86_elf_abi | |
534 | { | |
535 | I386_ABI, | |
7f56bc95 L |
536 | X86_64_ABI, |
537 | X86_64_X32_ABI | |
351f65ca L |
538 | }; |
539 | ||
540 | static enum x86_elf_abi x86_elf_abi = I386_ABI; | |
7af8ed2d | 541 | #endif |
351f65ca | 542 | |
167ad85b TG |
543 | #if defined (TE_PE) || defined (TE_PEP) |
544 | /* Use big object file format. */ | |
545 | static int use_big_obj = 0; | |
546 | #endif | |
547 | ||
8dcea932 L |
548 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
549 | /* 1 if generating code for a shared library. */ | |
550 | static int shared = 0; | |
551 | #endif | |
552 | ||
47926f60 KH |
553 | /* 1 for intel syntax, |
554 | 0 if att syntax. */ | |
555 | static int intel_syntax = 0; | |
252b5132 | 556 | |
e89c5eaa L |
557 | /* 1 for Intel64 ISA, |
558 | 0 if AMD64 ISA. */ | |
559 | static int intel64; | |
560 | ||
1efbbeb4 L |
561 | /* 1 for intel mnemonic, |
562 | 0 if att mnemonic. */ | |
563 | static int intel_mnemonic = !SYSV386_COMPAT; | |
564 | ||
5209009a | 565 | /* 1 if support old (<= 2.8.1) versions of gcc. */ |
1efbbeb4 L |
566 | static int old_gcc = OLDGCC_COMPAT; |
567 | ||
a60de03c JB |
568 | /* 1 if pseudo registers are permitted. */ |
569 | static int allow_pseudo_reg = 0; | |
570 | ||
47926f60 KH |
571 | /* 1 if register prefix % not required. */ |
572 | static int allow_naked_reg = 0; | |
252b5132 | 573 | |
33eaf5de | 574 | /* 1 if the assembler should add BND prefix for all control-transferring |
7e8b059b L |
575 | instructions supporting it, even if this prefix wasn't specified |
576 | explicitly. */ | |
577 | static int add_bnd_prefix = 0; | |
578 | ||
ba104c83 | 579 | /* 1 if pseudo index register, eiz/riz, is allowed . */ |
db51cc60 L |
580 | static int allow_index_reg = 0; |
581 | ||
d022bddd IT |
582 | /* 1 if the assembler should ignore LOCK prefix, even if it was |
583 | specified explicitly. */ | |
584 | static int omit_lock_prefix = 0; | |
585 | ||
e4e00185 AS |
586 | /* 1 if the assembler should encode lfence, mfence, and sfence as |
587 | "lock addl $0, (%{re}sp)". */ | |
588 | static int avoid_fence = 0; | |
589 | ||
0cb4071e L |
590 | /* 1 if the assembler should generate relax relocations. */ |
591 | ||
592 | static int generate_relax_relocations | |
593 | = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS; | |
594 | ||
7bab8ab5 | 595 | static enum check_kind |
daf50ae7 | 596 | { |
7bab8ab5 JB |
597 | check_none = 0, |
598 | check_warning, | |
599 | check_error | |
daf50ae7 | 600 | } |
7bab8ab5 | 601 | sse_check, operand_check = check_warning; |
daf50ae7 | 602 | |
2ca3ace5 L |
603 | /* Register prefix used for error message. */ |
604 | static const char *register_prefix = "%"; | |
605 | ||
47926f60 KH |
606 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
607 | leave, push, and pop instructions so that gcc has the same stack | |
608 | frame as in 32 bit mode. */ | |
609 | static char stackop_size = '\0'; | |
eecb386c | 610 | |
12b55ccc L |
611 | /* Non-zero to optimize code alignment. */ |
612 | int optimize_align_code = 1; | |
613 | ||
47926f60 KH |
614 | /* Non-zero to quieten some warnings. */ |
615 | static int quiet_warnings = 0; | |
a38cf1db | 616 | |
47926f60 KH |
617 | /* CPU name. */ |
618 | static const char *cpu_arch_name = NULL; | |
6305a203 | 619 | static char *cpu_sub_arch_name = NULL; |
a38cf1db | 620 | |
47926f60 | 621 | /* CPU feature flags. */ |
40fb9820 L |
622 | static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; |
623 | ||
ccc9c027 L |
624 | /* If we have selected a cpu we are generating instructions for. */ |
625 | static int cpu_arch_tune_set = 0; | |
626 | ||
9103f4f4 | 627 | /* Cpu we are generating instructions for. */ |
fbf3f584 | 628 | enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; |
9103f4f4 L |
629 | |
630 | /* CPU feature flags of cpu we are generating instructions for. */ | |
40fb9820 | 631 | static i386_cpu_flags cpu_arch_tune_flags; |
9103f4f4 | 632 | |
ccc9c027 | 633 | /* CPU instruction set architecture used. */ |
fbf3f584 | 634 | enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; |
ccc9c027 | 635 | |
9103f4f4 | 636 | /* CPU feature flags of instruction set architecture used. */ |
fbf3f584 | 637 | i386_cpu_flags cpu_arch_isa_flags; |
9103f4f4 | 638 | |
fddf5b5b AM |
639 | /* If set, conditional jumps are not automatically promoted to handle |
640 | larger than a byte offset. */ | |
641 | static unsigned int no_cond_jump_promotion = 0; | |
642 | ||
c0f3af97 L |
643 | /* Encode SSE instructions with VEX prefix. */ |
644 | static unsigned int sse2avx; | |
645 | ||
539f890d L |
646 | /* Encode scalar AVX instructions with specific vector length. */ |
647 | static enum | |
648 | { | |
649 | vex128 = 0, | |
650 | vex256 | |
651 | } avxscalar; | |
652 | ||
43234a1e L |
653 | /* Encode scalar EVEX LIG instructions with specific vector length. */ |
654 | static enum | |
655 | { | |
656 | evexl128 = 0, | |
657 | evexl256, | |
658 | evexl512 | |
659 | } evexlig; | |
660 | ||
661 | /* Encode EVEX WIG instructions with specific evex.w. */ | |
662 | static enum | |
663 | { | |
664 | evexw0 = 0, | |
665 | evexw1 | |
666 | } evexwig; | |
667 | ||
d3d3c6db IT |
668 | /* Value to encode in EVEX RC bits, for SAE-only instructions. */ |
669 | static enum rc_type evexrcig = rne; | |
670 | ||
29b0f896 | 671 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
87c245cc | 672 | static symbolS *GOT_symbol; |
29b0f896 | 673 | |
a4447b93 RH |
674 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
675 | unsigned int x86_dwarf2_return_column; | |
676 | ||
677 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
678 | int x86_cie_data_alignment; | |
679 | ||
252b5132 | 680 | /* Interface to relax_segment. |
fddf5b5b AM |
681 | There are 3 major relax states for 386 jump insns because the |
682 | different types of jumps add different sizes to frags when we're | |
683 | figuring out what sort of jump to choose to reach a given label. */ | |
252b5132 | 684 | |
47926f60 | 685 | /* Types. */ |
93c2a809 AM |
686 | #define UNCOND_JUMP 0 |
687 | #define COND_JUMP 1 | |
688 | #define COND_JUMP86 2 | |
fddf5b5b | 689 | |
47926f60 | 690 | /* Sizes. */ |
252b5132 RH |
691 | #define CODE16 1 |
692 | #define SMALL 0 | |
29b0f896 | 693 | #define SMALL16 (SMALL | CODE16) |
252b5132 | 694 | #define BIG 2 |
29b0f896 | 695 | #define BIG16 (BIG | CODE16) |
252b5132 RH |
696 | |
697 | #ifndef INLINE | |
698 | #ifdef __GNUC__ | |
699 | #define INLINE __inline__ | |
700 | #else | |
701 | #define INLINE | |
702 | #endif | |
703 | #endif | |
704 | ||
fddf5b5b AM |
705 | #define ENCODE_RELAX_STATE(type, size) \ |
706 | ((relax_substateT) (((type) << 2) | (size))) | |
707 | #define TYPE_FROM_RELAX_STATE(s) \ | |
708 | ((s) >> 2) | |
709 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
710 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
711 | |
712 | /* This table is used by relax_frag to promote short jumps to long | |
713 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
714 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
715 | don't allow a short jump in a 32 bit code segment to be promoted to | |
716 | a 16 bit offset jump because it's slower (requires data size | |
717 | prefix), and doesn't work, unless the destination is in the bottom | |
718 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
719 | ||
720 | const relax_typeS md_relax_table[] = | |
721 | { | |
24eab124 AM |
722 | /* The fields are: |
723 | 1) most positive reach of this state, | |
724 | 2) most negative reach of this state, | |
93c2a809 | 725 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 726 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 727 | |
fddf5b5b | 728 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
729 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
730 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
731 | /* dword jmp adds 4 bytes to frag: | |
732 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 733 | {0, 0, 4, 0}, |
93c2a809 AM |
734 | /* word jmp adds 2 byte2 to frag: |
735 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
736 | {0, 0, 2, 0}, |
737 | ||
93c2a809 AM |
738 | /* COND_JUMP states. */ |
739 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
740 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
741 | /* dword conditionals adds 5 bytes to frag: | |
742 | 1 extra opcode byte, 4 displacement bytes. */ | |
743 | {0, 0, 5, 0}, | |
fddf5b5b | 744 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
745 | 1 extra opcode byte, 2 displacement bytes. */ |
746 | {0, 0, 3, 0}, | |
747 | ||
748 | /* COND_JUMP86 states. */ | |
749 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
750 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
751 | /* dword conditionals adds 5 bytes to frag: | |
752 | 1 extra opcode byte, 4 displacement bytes. */ | |
753 | {0, 0, 5, 0}, | |
754 | /* word conditionals add 4 bytes to frag: | |
755 | 1 displacement byte and a 3 byte long branch insn. */ | |
756 | {0, 0, 4, 0} | |
252b5132 RH |
757 | }; |
758 | ||
9103f4f4 L |
759 | static const arch_entry cpu_arch[] = |
760 | { | |
89507696 JB |
761 | /* Do not replace the first two entries - i386_target_format() |
762 | relies on them being there in this order. */ | |
8a2c8fef | 763 | { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32, |
293f5f65 | 764 | CPU_GENERIC32_FLAGS, 0 }, |
8a2c8fef | 765 | { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64, |
293f5f65 | 766 | CPU_GENERIC64_FLAGS, 0 }, |
8a2c8fef | 767 | { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN, |
293f5f65 | 768 | CPU_NONE_FLAGS, 0 }, |
8a2c8fef | 769 | { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN, |
293f5f65 | 770 | CPU_I186_FLAGS, 0 }, |
8a2c8fef | 771 | { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN, |
293f5f65 | 772 | CPU_I286_FLAGS, 0 }, |
8a2c8fef | 773 | { STRING_COMMA_LEN ("i386"), PROCESSOR_I386, |
293f5f65 | 774 | CPU_I386_FLAGS, 0 }, |
8a2c8fef | 775 | { STRING_COMMA_LEN ("i486"), PROCESSOR_I486, |
293f5f65 | 776 | CPU_I486_FLAGS, 0 }, |
8a2c8fef | 777 | { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM, |
293f5f65 | 778 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 779 | { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 780 | CPU_I686_FLAGS, 0 }, |
8a2c8fef | 781 | { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM, |
293f5f65 | 782 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 783 | { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 784 | CPU_PENTIUMPRO_FLAGS, 0 }, |
8a2c8fef | 785 | { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 786 | CPU_P2_FLAGS, 0 }, |
8a2c8fef | 787 | { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO, |
293f5f65 | 788 | CPU_P3_FLAGS, 0 }, |
8a2c8fef | 789 | { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4, |
293f5f65 | 790 | CPU_P4_FLAGS, 0 }, |
8a2c8fef | 791 | { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA, |
293f5f65 | 792 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 793 | { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA, |
293f5f65 | 794 | CPU_NOCONA_FLAGS, 0 }, |
8a2c8fef | 795 | { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE, |
293f5f65 | 796 | CPU_CORE_FLAGS, 1 }, |
8a2c8fef | 797 | { STRING_COMMA_LEN ("core"), PROCESSOR_CORE, |
293f5f65 | 798 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 799 | { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2, |
293f5f65 | 800 | CPU_CORE2_FLAGS, 1 }, |
8a2c8fef | 801 | { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2, |
293f5f65 | 802 | CPU_CORE2_FLAGS, 0 }, |
8a2c8fef | 803 | { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7, |
293f5f65 | 804 | CPU_COREI7_FLAGS, 0 }, |
8a2c8fef | 805 | { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM, |
293f5f65 | 806 | CPU_L1OM_FLAGS, 0 }, |
7a9068fe | 807 | { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM, |
293f5f65 | 808 | CPU_K1OM_FLAGS, 0 }, |
81486035 | 809 | { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU, |
293f5f65 | 810 | CPU_IAMCU_FLAGS, 0 }, |
8a2c8fef | 811 | { STRING_COMMA_LEN ("k6"), PROCESSOR_K6, |
293f5f65 | 812 | CPU_K6_FLAGS, 0 }, |
8a2c8fef | 813 | { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6, |
293f5f65 | 814 | CPU_K6_2_FLAGS, 0 }, |
8a2c8fef | 815 | { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON, |
293f5f65 | 816 | CPU_ATHLON_FLAGS, 0 }, |
8a2c8fef | 817 | { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8, |
293f5f65 | 818 | CPU_K8_FLAGS, 1 }, |
8a2c8fef | 819 | { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8, |
293f5f65 | 820 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 821 | { STRING_COMMA_LEN ("k8"), PROCESSOR_K8, |
293f5f65 | 822 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 823 | { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10, |
293f5f65 | 824 | CPU_AMDFAM10_FLAGS, 0 }, |
8aedb9fe | 825 | { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD, |
293f5f65 | 826 | CPU_BDVER1_FLAGS, 0 }, |
8aedb9fe | 827 | { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD, |
293f5f65 | 828 | CPU_BDVER2_FLAGS, 0 }, |
5e5c50d3 | 829 | { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD, |
293f5f65 | 830 | CPU_BDVER3_FLAGS, 0 }, |
c7b0bd56 | 831 | { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD, |
293f5f65 | 832 | CPU_BDVER4_FLAGS, 0 }, |
029f3522 | 833 | { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER, |
293f5f65 | 834 | CPU_ZNVER1_FLAGS, 0 }, |
7b458c12 | 835 | { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT, |
293f5f65 | 836 | CPU_BTVER1_FLAGS, 0 }, |
7b458c12 | 837 | { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT, |
293f5f65 | 838 | CPU_BTVER2_FLAGS, 0 }, |
8a2c8fef | 839 | { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN, |
293f5f65 | 840 | CPU_8087_FLAGS, 0 }, |
8a2c8fef | 841 | { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN, |
293f5f65 | 842 | CPU_287_FLAGS, 0 }, |
8a2c8fef | 843 | { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN, |
293f5f65 | 844 | CPU_387_FLAGS, 0 }, |
1848e567 L |
845 | { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN, |
846 | CPU_687_FLAGS, 0 }, | |
8a2c8fef | 847 | { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 848 | CPU_MMX_FLAGS, 0 }, |
8a2c8fef | 849 | { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN, |
293f5f65 | 850 | CPU_SSE_FLAGS, 0 }, |
8a2c8fef | 851 | { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN, |
293f5f65 | 852 | CPU_SSE2_FLAGS, 0 }, |
8a2c8fef | 853 | { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 854 | CPU_SSE3_FLAGS, 0 }, |
8a2c8fef | 855 | { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 856 | CPU_SSSE3_FLAGS, 0 }, |
8a2c8fef | 857 | { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN, |
293f5f65 | 858 | CPU_SSE4_1_FLAGS, 0 }, |
8a2c8fef | 859 | { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN, |
293f5f65 | 860 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 861 | { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN, |
293f5f65 | 862 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 863 | { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN, |
293f5f65 | 864 | CPU_AVX_FLAGS, 0 }, |
6c30d220 | 865 | { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN, |
293f5f65 | 866 | CPU_AVX2_FLAGS, 0 }, |
43234a1e | 867 | { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN, |
293f5f65 | 868 | CPU_AVX512F_FLAGS, 0 }, |
43234a1e | 869 | { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN, |
293f5f65 | 870 | CPU_AVX512CD_FLAGS, 0 }, |
43234a1e | 871 | { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN, |
293f5f65 | 872 | CPU_AVX512ER_FLAGS, 0 }, |
43234a1e | 873 | { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN, |
293f5f65 | 874 | CPU_AVX512PF_FLAGS, 0 }, |
1dfc6506 | 875 | { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN, |
293f5f65 | 876 | CPU_AVX512DQ_FLAGS, 0 }, |
1dfc6506 | 877 | { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN, |
293f5f65 | 878 | CPU_AVX512BW_FLAGS, 0 }, |
1dfc6506 | 879 | { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN, |
293f5f65 | 880 | CPU_AVX512VL_FLAGS, 0 }, |
8a2c8fef | 881 | { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 882 | CPU_VMX_FLAGS, 0 }, |
8729a6f6 | 883 | { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN, |
293f5f65 | 884 | CPU_VMFUNC_FLAGS, 0 }, |
8a2c8fef | 885 | { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN, |
293f5f65 | 886 | CPU_SMX_FLAGS, 0 }, |
8a2c8fef | 887 | { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN, |
293f5f65 | 888 | CPU_XSAVE_FLAGS, 0 }, |
c7b8aa3a | 889 | { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 890 | CPU_XSAVEOPT_FLAGS, 0 }, |
1dfc6506 | 891 | { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN, |
293f5f65 | 892 | CPU_XSAVEC_FLAGS, 0 }, |
1dfc6506 | 893 | { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN, |
293f5f65 | 894 | CPU_XSAVES_FLAGS, 0 }, |
8a2c8fef | 895 | { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN, |
293f5f65 | 896 | CPU_AES_FLAGS, 0 }, |
8a2c8fef | 897 | { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 898 | CPU_PCLMUL_FLAGS, 0 }, |
8a2c8fef | 899 | { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 900 | CPU_PCLMUL_FLAGS, 1 }, |
c7b8aa3a | 901 | { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN, |
293f5f65 | 902 | CPU_FSGSBASE_FLAGS, 0 }, |
c7b8aa3a | 903 | { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN, |
293f5f65 | 904 | CPU_RDRND_FLAGS, 0 }, |
c7b8aa3a | 905 | { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN, |
293f5f65 | 906 | CPU_F16C_FLAGS, 0 }, |
6c30d220 | 907 | { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN, |
293f5f65 | 908 | CPU_BMI2_FLAGS, 0 }, |
8a2c8fef | 909 | { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN, |
293f5f65 | 910 | CPU_FMA_FLAGS, 0 }, |
8a2c8fef | 911 | { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN, |
293f5f65 | 912 | CPU_FMA4_FLAGS, 0 }, |
8a2c8fef | 913 | { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN, |
293f5f65 | 914 | CPU_XOP_FLAGS, 0 }, |
8a2c8fef | 915 | { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN, |
293f5f65 | 916 | CPU_LWP_FLAGS, 0 }, |
8a2c8fef | 917 | { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN, |
293f5f65 | 918 | CPU_MOVBE_FLAGS, 0 }, |
60aa667e | 919 | { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN, |
293f5f65 | 920 | CPU_CX16_FLAGS, 0 }, |
8a2c8fef | 921 | { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN, |
293f5f65 | 922 | CPU_EPT_FLAGS, 0 }, |
6c30d220 | 923 | { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN, |
293f5f65 | 924 | CPU_LZCNT_FLAGS, 0 }, |
42164a71 | 925 | { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN, |
293f5f65 | 926 | CPU_HLE_FLAGS, 0 }, |
42164a71 | 927 | { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN, |
293f5f65 | 928 | CPU_RTM_FLAGS, 0 }, |
6c30d220 | 929 | { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN, |
293f5f65 | 930 | CPU_INVPCID_FLAGS, 0 }, |
8a2c8fef | 931 | { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN, |
293f5f65 | 932 | CPU_CLFLUSH_FLAGS, 0 }, |
22109423 | 933 | { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN, |
293f5f65 | 934 | CPU_NOP_FLAGS, 0 }, |
8a2c8fef | 935 | { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN, |
293f5f65 | 936 | CPU_SYSCALL_FLAGS, 0 }, |
8a2c8fef | 937 | { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN, |
293f5f65 | 938 | CPU_RDTSCP_FLAGS, 0 }, |
8a2c8fef | 939 | { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN, |
293f5f65 | 940 | CPU_3DNOW_FLAGS, 0 }, |
8a2c8fef | 941 | { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN, |
293f5f65 | 942 | CPU_3DNOWA_FLAGS, 0 }, |
8a2c8fef | 943 | { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN, |
293f5f65 | 944 | CPU_PADLOCK_FLAGS, 0 }, |
8a2c8fef | 945 | { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN, |
293f5f65 | 946 | CPU_SVME_FLAGS, 1 }, |
8a2c8fef | 947 | { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN, |
293f5f65 | 948 | CPU_SVME_FLAGS, 0 }, |
8a2c8fef | 949 | { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, |
293f5f65 | 950 | CPU_SSE4A_FLAGS, 0 }, |
8a2c8fef | 951 | { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN, |
293f5f65 | 952 | CPU_ABM_FLAGS, 0 }, |
87973e9f | 953 | { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 954 | CPU_BMI_FLAGS, 0 }, |
2a2a0f38 | 955 | { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN, |
293f5f65 | 956 | CPU_TBM_FLAGS, 0 }, |
e2e1fcde | 957 | { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN, |
293f5f65 | 958 | CPU_ADX_FLAGS, 0 }, |
e2e1fcde | 959 | { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN, |
293f5f65 | 960 | CPU_RDSEED_FLAGS, 0 }, |
e2e1fcde | 961 | { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN, |
293f5f65 | 962 | CPU_PRFCHW_FLAGS, 0 }, |
5c111e37 | 963 | { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN, |
293f5f65 | 964 | CPU_SMAP_FLAGS, 0 }, |
7e8b059b | 965 | { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN, |
293f5f65 | 966 | CPU_MPX_FLAGS, 0 }, |
a0046408 | 967 | { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN, |
293f5f65 | 968 | CPU_SHA_FLAGS, 0 }, |
963f3586 | 969 | { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 970 | CPU_CLFLUSHOPT_FLAGS, 0 }, |
dcf893b5 | 971 | { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN, |
293f5f65 | 972 | CPU_PREFETCHWT1_FLAGS, 0 }, |
2cf200a4 | 973 | { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN, |
293f5f65 | 974 | CPU_SE1_FLAGS, 0 }, |
c5e7287a | 975 | { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN, |
293f5f65 | 976 | CPU_CLWB_FLAGS, 0 }, |
2cc1b5aa | 977 | { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN, |
293f5f65 | 978 | CPU_AVX512IFMA_FLAGS, 0 }, |
14f195c9 | 979 | { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 980 | CPU_AVX512VBMI_FLAGS, 0 }, |
920d2ddc IT |
981 | { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN, |
982 | CPU_AVX512_4FMAPS_FLAGS, 0 }, | |
47acf0bd IT |
983 | { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN, |
984 | CPU_AVX512_4VNNIW_FLAGS, 0 }, | |
620214f7 IT |
985 | { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN, |
986 | CPU_AVX512_VPOPCNTDQ_FLAGS, 0 }, | |
53467f57 IT |
987 | { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN, |
988 | CPU_AVX512_VBMI2_FLAGS, 0 }, | |
8cfcb765 IT |
989 | { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN, |
990 | CPU_AVX512_VNNI_FLAGS, 0 }, | |
ee6872be IT |
991 | { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN, |
992 | CPU_AVX512_BITALG_FLAGS, 0 }, | |
029f3522 | 993 | { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN, |
293f5f65 | 994 | CPU_CLZERO_FLAGS, 0 }, |
9916071f | 995 | { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN, |
293f5f65 | 996 | CPU_MWAITX_FLAGS, 0 }, |
8eab4136 | 997 | { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN, |
293f5f65 | 998 | CPU_OSPKE_FLAGS, 0 }, |
8bc52696 | 999 | { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN, |
293f5f65 | 1000 | CPU_RDPID_FLAGS, 0 }, |
6b40c462 L |
1001 | { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN, |
1002 | CPU_PTWRITE_FLAGS, 0 }, | |
d777820b IT |
1003 | { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN, |
1004 | CPU_IBT_FLAGS, 0 }, | |
1005 | { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN, | |
1006 | CPU_SHSTK_FLAGS, 0 }, | |
48521003 IT |
1007 | { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN, |
1008 | CPU_GFNI_FLAGS, 0 }, | |
8dcf1fad IT |
1009 | { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN, |
1010 | CPU_VAES_FLAGS, 0 }, | |
ff1982d5 IT |
1011 | { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN, |
1012 | CPU_VPCLMULQDQ_FLAGS, 0 }, | |
3233d7d0 IT |
1013 | { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN, |
1014 | CPU_WBNOINVD_FLAGS, 0 }, | |
be3a8dca IT |
1015 | { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN, |
1016 | CPU_PCONFIG_FLAGS, 0 }, | |
293f5f65 L |
1017 | }; |
1018 | ||
1019 | static const noarch_entry cpu_noarch[] = | |
1020 | { | |
1021 | { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS }, | |
1848e567 L |
1022 | { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS }, |
1023 | { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS }, | |
1024 | { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS }, | |
293f5f65 L |
1025 | { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS }, |
1026 | { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS }, | |
1848e567 L |
1027 | { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS }, |
1028 | { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS }, | |
1029 | { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS }, | |
1030 | { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS }, | |
1031 | { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS }, | |
1032 | { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS }, | |
293f5f65 | 1033 | { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS }, |
1848e567 | 1034 | { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS }, |
144b71e2 L |
1035 | { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS }, |
1036 | { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS }, | |
1037 | { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS }, | |
1038 | { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS }, | |
1039 | { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS }, | |
1040 | { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS }, | |
1041 | { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS }, | |
1042 | { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS }, | |
1043 | { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS }, | |
920d2ddc | 1044 | { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS }, |
47acf0bd | 1045 | { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS }, |
620214f7 | 1046 | { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS }, |
53467f57 | 1047 | { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS }, |
8cfcb765 | 1048 | { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS }, |
ee6872be | 1049 | { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS }, |
d777820b IT |
1050 | { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS }, |
1051 | { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS }, | |
e413e4e9 AM |
1052 | }; |
1053 | ||
704209c0 | 1054 | #ifdef I386COFF |
a6c24e68 NC |
1055 | /* Like s_lcomm_internal in gas/read.c but the alignment string |
1056 | is allowed to be optional. */ | |
1057 | ||
1058 | static symbolS * | |
1059 | pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size) | |
1060 | { | |
1061 | addressT align = 0; | |
1062 | ||
1063 | SKIP_WHITESPACE (); | |
1064 | ||
7ab9ffdd | 1065 | if (needs_align |
a6c24e68 NC |
1066 | && *input_line_pointer == ',') |
1067 | { | |
1068 | align = parse_align (needs_align - 1); | |
7ab9ffdd | 1069 | |
a6c24e68 NC |
1070 | if (align == (addressT) -1) |
1071 | return NULL; | |
1072 | } | |
1073 | else | |
1074 | { | |
1075 | if (size >= 8) | |
1076 | align = 3; | |
1077 | else if (size >= 4) | |
1078 | align = 2; | |
1079 | else if (size >= 2) | |
1080 | align = 1; | |
1081 | else | |
1082 | align = 0; | |
1083 | } | |
1084 | ||
1085 | bss_alloc (symbolP, size, align); | |
1086 | return symbolP; | |
1087 | } | |
1088 | ||
704209c0 | 1089 | static void |
a6c24e68 NC |
1090 | pe_lcomm (int needs_align) |
1091 | { | |
1092 | s_comm_internal (needs_align * 2, pe_lcomm_internal); | |
1093 | } | |
704209c0 | 1094 | #endif |
a6c24e68 | 1095 | |
29b0f896 AM |
1096 | const pseudo_typeS md_pseudo_table[] = |
1097 | { | |
1098 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) | |
1099 | {"align", s_align_bytes, 0}, | |
1100 | #else | |
1101 | {"align", s_align_ptwo, 0}, | |
1102 | #endif | |
1103 | {"arch", set_cpu_arch, 0}, | |
1104 | #ifndef I386COFF | |
1105 | {"bss", s_bss, 0}, | |
a6c24e68 NC |
1106 | #else |
1107 | {"lcomm", pe_lcomm, 1}, | |
29b0f896 AM |
1108 | #endif |
1109 | {"ffloat", float_cons, 'f'}, | |
1110 | {"dfloat", float_cons, 'd'}, | |
1111 | {"tfloat", float_cons, 'x'}, | |
1112 | {"value", cons, 2}, | |
d182319b | 1113 | {"slong", signed_cons, 4}, |
29b0f896 AM |
1114 | {"noopt", s_ignore, 0}, |
1115 | {"optim", s_ignore, 0}, | |
1116 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, | |
1117 | {"code16", set_code_flag, CODE_16BIT}, | |
1118 | {"code32", set_code_flag, CODE_32BIT}, | |
da5f19a2 | 1119 | #ifdef BFD64 |
29b0f896 | 1120 | {"code64", set_code_flag, CODE_64BIT}, |
da5f19a2 | 1121 | #endif |
29b0f896 AM |
1122 | {"intel_syntax", set_intel_syntax, 1}, |
1123 | {"att_syntax", set_intel_syntax, 0}, | |
1efbbeb4 L |
1124 | {"intel_mnemonic", set_intel_mnemonic, 1}, |
1125 | {"att_mnemonic", set_intel_mnemonic, 0}, | |
db51cc60 L |
1126 | {"allow_index_reg", set_allow_index_reg, 1}, |
1127 | {"disallow_index_reg", set_allow_index_reg, 0}, | |
7bab8ab5 JB |
1128 | {"sse_check", set_check, 0}, |
1129 | {"operand_check", set_check, 1}, | |
3b22753a L |
1130 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
1131 | {"largecomm", handle_large_common, 0}, | |
07a53e5c | 1132 | #else |
68d20676 | 1133 | {"file", dwarf2_directive_file, 0}, |
07a53e5c RH |
1134 | {"loc", dwarf2_directive_loc, 0}, |
1135 | {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, | |
3b22753a | 1136 | #endif |
6482c264 NC |
1137 | #ifdef TE_PE |
1138 | {"secrel32", pe_directive_secrel, 0}, | |
1139 | #endif | |
29b0f896 AM |
1140 | {0, 0, 0} |
1141 | }; | |
1142 | ||
1143 | /* For interface with expression (). */ | |
1144 | extern char *input_line_pointer; | |
1145 | ||
1146 | /* Hash table for instruction mnemonic lookup. */ | |
1147 | static struct hash_control *op_hash; | |
1148 | ||
1149 | /* Hash table for register lookup. */ | |
1150 | static struct hash_control *reg_hash; | |
1151 | \f | |
ce8a8b2f AM |
1152 | /* Various efficient no-op patterns for aligning code labels. |
1153 | Note: Don't try to assemble the instructions in the comments. | |
1154 | 0L and 0w are not legal. */ | |
62a02d25 L |
1155 | static const unsigned char f32_1[] = |
1156 | {0x90}; /* nop */ | |
1157 | static const unsigned char f32_2[] = | |
1158 | {0x66,0x90}; /* xchg %ax,%ax */ | |
1159 | static const unsigned char f32_3[] = | |
1160 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
1161 | static const unsigned char f32_4[] = | |
1162 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
1163 | static const unsigned char f32_5[] = | |
1164 | {0x90, /* nop */ | |
1165 | 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
1166 | static const unsigned char f32_6[] = | |
1167 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
1168 | static const unsigned char f32_7[] = | |
1169 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
1170 | static const unsigned char f32_8[] = | |
1171 | {0x90, /* nop */ | |
1172 | 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
1173 | static const unsigned char f32_9[] = | |
1174 | {0x89,0xf6, /* movl %esi,%esi */ | |
1175 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
1176 | static const unsigned char f32_10[] = | |
1177 | {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ | |
1178 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
1179 | static const unsigned char f32_11[] = | |
1180 | {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ | |
1181 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
1182 | static const unsigned char f32_12[] = | |
1183 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
1184 | 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ | |
1185 | static const unsigned char f32_13[] = | |
1186 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
1187 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
1188 | static const unsigned char f32_14[] = | |
1189 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ | |
1190 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
1191 | static const unsigned char f16_3[] = | |
1192 | {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */ | |
1193 | static const unsigned char f16_4[] = | |
1194 | {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
1195 | static const unsigned char f16_5[] = | |
1196 | {0x90, /* nop */ | |
1197 | 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
1198 | static const unsigned char f16_6[] = | |
1199 | {0x89,0xf6, /* mov %si,%si */ | |
1200 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
1201 | static const unsigned char f16_7[] = | |
1202 | {0x8d,0x74,0x00, /* lea 0(%si),%si */ | |
1203 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
1204 | static const unsigned char f16_8[] = | |
1205 | {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ | |
1206 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
1207 | static const unsigned char jump_31[] = | |
1208 | {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */ | |
1209 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90, | |
1210 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90, | |
1211 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; | |
1212 | /* 32-bit NOPs patterns. */ | |
1213 | static const unsigned char *const f32_patt[] = { | |
1214 | f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, | |
1215 | f32_9, f32_10, f32_11, f32_12, f32_13, f32_14 | |
1216 | }; | |
1217 | /* 16-bit NOPs patterns. */ | |
1218 | static const unsigned char *const f16_patt[] = { | |
1219 | f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8 | |
1220 | }; | |
1221 | /* nopl (%[re]ax) */ | |
1222 | static const unsigned char alt_3[] = | |
1223 | {0x0f,0x1f,0x00}; | |
1224 | /* nopl 0(%[re]ax) */ | |
1225 | static const unsigned char alt_4[] = | |
1226 | {0x0f,0x1f,0x40,0x00}; | |
1227 | /* nopl 0(%[re]ax,%[re]ax,1) */ | |
1228 | static const unsigned char alt_5[] = | |
1229 | {0x0f,0x1f,0x44,0x00,0x00}; | |
1230 | /* nopw 0(%[re]ax,%[re]ax,1) */ | |
1231 | static const unsigned char alt_6[] = | |
1232 | {0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
1233 | /* nopl 0L(%[re]ax) */ | |
1234 | static const unsigned char alt_7[] = | |
1235 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
1236 | /* nopl 0L(%[re]ax,%[re]ax,1) */ | |
1237 | static const unsigned char alt_8[] = | |
1238 | {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1239 | /* nopw 0L(%[re]ax,%[re]ax,1) */ | |
1240 | static const unsigned char alt_9[] = | |
1241 | {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1242 | /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
1243 | static const unsigned char alt_10[] = | |
1244 | {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1245 | /* 32-bit and 64-bit NOPs patterns. */ | |
1246 | static const unsigned char *const alt_patt[] = { | |
1247 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
1248 | alt_9, alt_10 | |
1249 | }; | |
1250 | /* 64-bit only: nopw %cs:0L(%eax,%eax,1) */ | |
1251 | static const unsigned char alt64_11[] = | |
1252 | {0x67,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1253 | /* 64-bit NOPs patterns. */ | |
1254 | static const unsigned char *const alt64_patt[] = { | |
1255 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
1256 | alt_9, alt_10, alt64_11 | |
1257 | }; | |
1258 | ||
1259 | /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum | |
1260 | size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */ | |
1261 | ||
1262 | static void | |
1263 | i386_output_nops (char *where, const unsigned char *const *patt, | |
1264 | int count, int max_single_nop_size) | |
1265 | ||
1266 | { | |
1267 | while (count > max_single_nop_size) | |
1268 | { | |
1269 | count -= max_single_nop_size; | |
1270 | memcpy (where + count, patt[max_single_nop_size - 1], | |
1271 | max_single_nop_size); | |
1272 | } | |
1273 | ||
1274 | if (count) | |
1275 | memcpy (where, patt[count - 1], count); | |
1276 | } | |
1277 | ||
1278 | ||
1279 | /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a | |
1280 | single NOP instruction LIMIT. */ | |
1281 | ||
1282 | void | |
1283 | i386_generate_nops (fragS *f, char *where, offsetT count, int limit) | |
1284 | { | |
1285 | /* Output NOPs for .nop directive. */ | |
1286 | int max_single_nop_size; | |
1287 | const unsigned char *const *patt; | |
1288 | ||
1289 | if (flag_code == CODE_16BIT) | |
1290 | { | |
1291 | patt = f16_patt; | |
1292 | max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]); | |
1293 | } | |
1294 | else if (flag_code == CODE_64BIT) | |
1295 | { | |
1296 | patt = alt64_patt; | |
1297 | max_single_nop_size = sizeof (alt64_patt) / sizeof (alt64_patt[0]); | |
1298 | } | |
1299 | else | |
1300 | { | |
1301 | patt = alt_patt; | |
1302 | max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]); | |
1303 | } | |
1304 | if (limit == 0) | |
1305 | limit = max_single_nop_size; | |
1306 | else if (limit > max_single_nop_size) | |
1307 | { | |
1308 | as_bad_where (f->fr_file, f->fr_line, | |
1309 | _("invalide single nop size: %d (expect within [0, %d])"), | |
1310 | limit, max_single_nop_size); | |
1311 | return; | |
1312 | } | |
1313 | ||
1314 | i386_output_nops (where, patt, count, limit); | |
1315 | } | |
252b5132 | 1316 | |
62a02d25 L |
1317 | void |
1318 | i386_align_code (fragS *fragP, int count) | |
1319 | { | |
76bc74dc L |
1320 | /* Only align for at least a positive non-zero boundary. */ |
1321 | if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE) | |
33fef721 | 1322 | return; |
3e73aa7c | 1323 | |
ccc9c027 L |
1324 | /* We need to decide which NOP sequence to use for 32bit and |
1325 | 64bit. When -mtune= is used: | |
4eed87de | 1326 | |
76bc74dc L |
1327 | 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and |
1328 | PROCESSOR_GENERIC32, f32_patt will be used. | |
80b8656c L |
1329 | 2. For the rest, alt_patt will be used. |
1330 | ||
1331 | When -mtune= isn't used, alt_patt will be used if | |
22109423 | 1332 | cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will |
76bc74dc | 1333 | be used. |
ccc9c027 L |
1334 | |
1335 | When -march= or .arch is used, we can't use anything beyond | |
1336 | cpu_arch_isa_flags. */ | |
1337 | ||
1338 | if (flag_code == CODE_16BIT) | |
1339 | { | |
ccc9c027 | 1340 | if (count > 8) |
33fef721 | 1341 | { |
76bc74dc L |
1342 | memcpy (fragP->fr_literal + fragP->fr_fix, |
1343 | jump_31, count); | |
1344 | /* Adjust jump offset. */ | |
1345 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; | |
252b5132 | 1346 | } |
76bc74dc L |
1347 | else |
1348 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
1349 | f16_patt[count - 1], count); | |
252b5132 | 1350 | } |
33fef721 | 1351 | else |
ccc9c027 | 1352 | { |
bad6e36d | 1353 | const unsigned char *const *patt = NULL; |
ccc9c027 | 1354 | |
fbf3f584 | 1355 | if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN) |
ccc9c027 L |
1356 | { |
1357 | /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ | |
1358 | switch (cpu_arch_tune) | |
1359 | { | |
1360 | case PROCESSOR_UNKNOWN: | |
1361 | /* We use cpu_arch_isa_flags to check if we SHOULD | |
22109423 L |
1362 | optimize with nops. */ |
1363 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1364 | patt = alt_patt; |
ccc9c027 L |
1365 | else |
1366 | patt = f32_patt; | |
1367 | break; | |
ccc9c027 L |
1368 | case PROCESSOR_PENTIUM4: |
1369 | case PROCESSOR_NOCONA: | |
ef05d495 | 1370 | case PROCESSOR_CORE: |
76bc74dc | 1371 | case PROCESSOR_CORE2: |
bd5295b2 | 1372 | case PROCESSOR_COREI7: |
3632d14b | 1373 | case PROCESSOR_L1OM: |
7a9068fe | 1374 | case PROCESSOR_K1OM: |
76bc74dc | 1375 | case PROCESSOR_GENERIC64: |
ccc9c027 L |
1376 | case PROCESSOR_K6: |
1377 | case PROCESSOR_ATHLON: | |
1378 | case PROCESSOR_K8: | |
4eed87de | 1379 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1380 | case PROCESSOR_BD: |
029f3522 | 1381 | case PROCESSOR_ZNVER: |
7b458c12 | 1382 | case PROCESSOR_BT: |
80b8656c | 1383 | patt = alt_patt; |
ccc9c027 | 1384 | break; |
76bc74dc | 1385 | case PROCESSOR_I386: |
ccc9c027 L |
1386 | case PROCESSOR_I486: |
1387 | case PROCESSOR_PENTIUM: | |
2dde1948 | 1388 | case PROCESSOR_PENTIUMPRO: |
81486035 | 1389 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1390 | case PROCESSOR_GENERIC32: |
1391 | patt = f32_patt; | |
1392 | break; | |
4eed87de | 1393 | } |
ccc9c027 L |
1394 | } |
1395 | else | |
1396 | { | |
fbf3f584 | 1397 | switch (fragP->tc_frag_data.tune) |
ccc9c027 L |
1398 | { |
1399 | case PROCESSOR_UNKNOWN: | |
e6a14101 | 1400 | /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be |
ccc9c027 L |
1401 | PROCESSOR_UNKNOWN. */ |
1402 | abort (); | |
1403 | break; | |
1404 | ||
76bc74dc | 1405 | case PROCESSOR_I386: |
ccc9c027 L |
1406 | case PROCESSOR_I486: |
1407 | case PROCESSOR_PENTIUM: | |
81486035 | 1408 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1409 | case PROCESSOR_K6: |
1410 | case PROCESSOR_ATHLON: | |
1411 | case PROCESSOR_K8: | |
4eed87de | 1412 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1413 | case PROCESSOR_BD: |
029f3522 | 1414 | case PROCESSOR_ZNVER: |
7b458c12 | 1415 | case PROCESSOR_BT: |
ccc9c027 L |
1416 | case PROCESSOR_GENERIC32: |
1417 | /* We use cpu_arch_isa_flags to check if we CAN optimize | |
22109423 L |
1418 | with nops. */ |
1419 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1420 | patt = alt_patt; |
ccc9c027 L |
1421 | else |
1422 | patt = f32_patt; | |
1423 | break; | |
76bc74dc L |
1424 | case PROCESSOR_PENTIUMPRO: |
1425 | case PROCESSOR_PENTIUM4: | |
1426 | case PROCESSOR_NOCONA: | |
1427 | case PROCESSOR_CORE: | |
ef05d495 | 1428 | case PROCESSOR_CORE2: |
bd5295b2 | 1429 | case PROCESSOR_COREI7: |
3632d14b | 1430 | case PROCESSOR_L1OM: |
7a9068fe | 1431 | case PROCESSOR_K1OM: |
22109423 | 1432 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) |
80b8656c | 1433 | patt = alt_patt; |
ccc9c027 L |
1434 | else |
1435 | patt = f32_patt; | |
1436 | break; | |
1437 | case PROCESSOR_GENERIC64: | |
80b8656c | 1438 | patt = alt_patt; |
ccc9c027 | 1439 | break; |
4eed87de | 1440 | } |
ccc9c027 L |
1441 | } |
1442 | ||
76bc74dc L |
1443 | if (patt == f32_patt) |
1444 | { | |
1445 | /* If the padding is less than 15 bytes, we use the normal | |
1446 | ones. Otherwise, we use a jump instruction and adjust | |
711eedef L |
1447 | its offset. */ |
1448 | int limit; | |
76ba9986 | 1449 | |
711eedef L |
1450 | /* For 64bit, the limit is 3 bytes. */ |
1451 | if (flag_code == CODE_64BIT | |
1452 | && fragP->tc_frag_data.isa_flags.bitfield.cpulm) | |
1453 | limit = 3; | |
1454 | else | |
1455 | limit = 15; | |
1456 | if (count < limit) | |
76bc74dc L |
1457 | memcpy (fragP->fr_literal + fragP->fr_fix, |
1458 | patt[count - 1], count); | |
1459 | else | |
1460 | { | |
1461 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
1462 | jump_31, count); | |
1463 | /* Adjust jump offset. */ | |
1464 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; | |
1465 | } | |
1466 | } | |
1467 | else | |
1468 | { | |
80b8656c L |
1469 | /* Maximum length of an instruction is 10 byte. If the |
1470 | padding is greater than 10 bytes and we don't use jump, | |
76bc74dc | 1471 | we have to break it into smaller pieces. */ |
62a02d25 L |
1472 | i386_output_nops (fragP->fr_literal + fragP->fr_fix, |
1473 | patt, count, 10); | |
76bc74dc | 1474 | } |
ccc9c027 | 1475 | } |
33fef721 | 1476 | fragP->fr_var = count; |
252b5132 RH |
1477 | } |
1478 | ||
c6fb90c8 | 1479 | static INLINE int |
0dfbf9d7 | 1480 | operand_type_all_zero (const union i386_operand_type *x) |
40fb9820 | 1481 | { |
0dfbf9d7 | 1482 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1483 | { |
1484 | case 3: | |
0dfbf9d7 | 1485 | if (x->array[2]) |
c6fb90c8 | 1486 | return 0; |
1a0670f3 | 1487 | /* Fall through. */ |
c6fb90c8 | 1488 | case 2: |
0dfbf9d7 | 1489 | if (x->array[1]) |
c6fb90c8 | 1490 | return 0; |
1a0670f3 | 1491 | /* Fall through. */ |
c6fb90c8 | 1492 | case 1: |
0dfbf9d7 | 1493 | return !x->array[0]; |
c6fb90c8 L |
1494 | default: |
1495 | abort (); | |
1496 | } | |
40fb9820 L |
1497 | } |
1498 | ||
c6fb90c8 | 1499 | static INLINE void |
0dfbf9d7 | 1500 | operand_type_set (union i386_operand_type *x, unsigned int v) |
40fb9820 | 1501 | { |
0dfbf9d7 | 1502 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1503 | { |
1504 | case 3: | |
0dfbf9d7 | 1505 | x->array[2] = v; |
1a0670f3 | 1506 | /* Fall through. */ |
c6fb90c8 | 1507 | case 2: |
0dfbf9d7 | 1508 | x->array[1] = v; |
1a0670f3 | 1509 | /* Fall through. */ |
c6fb90c8 | 1510 | case 1: |
0dfbf9d7 | 1511 | x->array[0] = v; |
1a0670f3 | 1512 | /* Fall through. */ |
c6fb90c8 L |
1513 | break; |
1514 | default: | |
1515 | abort (); | |
1516 | } | |
1517 | } | |
40fb9820 | 1518 | |
c6fb90c8 | 1519 | static INLINE int |
0dfbf9d7 L |
1520 | operand_type_equal (const union i386_operand_type *x, |
1521 | const union i386_operand_type *y) | |
c6fb90c8 | 1522 | { |
0dfbf9d7 | 1523 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1524 | { |
1525 | case 3: | |
0dfbf9d7 | 1526 | if (x->array[2] != y->array[2]) |
c6fb90c8 | 1527 | return 0; |
1a0670f3 | 1528 | /* Fall through. */ |
c6fb90c8 | 1529 | case 2: |
0dfbf9d7 | 1530 | if (x->array[1] != y->array[1]) |
c6fb90c8 | 1531 | return 0; |
1a0670f3 | 1532 | /* Fall through. */ |
c6fb90c8 | 1533 | case 1: |
0dfbf9d7 | 1534 | return x->array[0] == y->array[0]; |
c6fb90c8 L |
1535 | break; |
1536 | default: | |
1537 | abort (); | |
1538 | } | |
1539 | } | |
40fb9820 | 1540 | |
0dfbf9d7 L |
1541 | static INLINE int |
1542 | cpu_flags_all_zero (const union i386_cpu_flags *x) | |
1543 | { | |
1544 | switch (ARRAY_SIZE(x->array)) | |
1545 | { | |
53467f57 IT |
1546 | case 4: |
1547 | if (x->array[3]) | |
1548 | return 0; | |
1549 | /* Fall through. */ | |
0dfbf9d7 L |
1550 | case 3: |
1551 | if (x->array[2]) | |
1552 | return 0; | |
1a0670f3 | 1553 | /* Fall through. */ |
0dfbf9d7 L |
1554 | case 2: |
1555 | if (x->array[1]) | |
1556 | return 0; | |
1a0670f3 | 1557 | /* Fall through. */ |
0dfbf9d7 L |
1558 | case 1: |
1559 | return !x->array[0]; | |
1560 | default: | |
1561 | abort (); | |
1562 | } | |
1563 | } | |
1564 | ||
0dfbf9d7 L |
1565 | static INLINE int |
1566 | cpu_flags_equal (const union i386_cpu_flags *x, | |
1567 | const union i386_cpu_flags *y) | |
1568 | { | |
1569 | switch (ARRAY_SIZE(x->array)) | |
1570 | { | |
53467f57 IT |
1571 | case 4: |
1572 | if (x->array[3] != y->array[3]) | |
1573 | return 0; | |
1574 | /* Fall through. */ | |
0dfbf9d7 L |
1575 | case 3: |
1576 | if (x->array[2] != y->array[2]) | |
1577 | return 0; | |
1a0670f3 | 1578 | /* Fall through. */ |
0dfbf9d7 L |
1579 | case 2: |
1580 | if (x->array[1] != y->array[1]) | |
1581 | return 0; | |
1a0670f3 | 1582 | /* Fall through. */ |
0dfbf9d7 L |
1583 | case 1: |
1584 | return x->array[0] == y->array[0]; | |
1585 | break; | |
1586 | default: | |
1587 | abort (); | |
1588 | } | |
1589 | } | |
c6fb90c8 L |
1590 | |
1591 | static INLINE int | |
1592 | cpu_flags_check_cpu64 (i386_cpu_flags f) | |
1593 | { | |
1594 | return !((flag_code == CODE_64BIT && f.bitfield.cpuno64) | |
1595 | || (flag_code != CODE_64BIT && f.bitfield.cpu64)); | |
40fb9820 L |
1596 | } |
1597 | ||
c6fb90c8 L |
1598 | static INLINE i386_cpu_flags |
1599 | cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1600 | { |
c6fb90c8 L |
1601 | switch (ARRAY_SIZE (x.array)) |
1602 | { | |
53467f57 IT |
1603 | case 4: |
1604 | x.array [3] &= y.array [3]; | |
1605 | /* Fall through. */ | |
c6fb90c8 L |
1606 | case 3: |
1607 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1608 | /* Fall through. */ |
c6fb90c8 L |
1609 | case 2: |
1610 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1611 | /* Fall through. */ |
c6fb90c8 L |
1612 | case 1: |
1613 | x.array [0] &= y.array [0]; | |
1614 | break; | |
1615 | default: | |
1616 | abort (); | |
1617 | } | |
1618 | return x; | |
1619 | } | |
40fb9820 | 1620 | |
c6fb90c8 L |
1621 | static INLINE i386_cpu_flags |
1622 | cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1623 | { |
c6fb90c8 | 1624 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1625 | { |
53467f57 IT |
1626 | case 4: |
1627 | x.array [3] |= y.array [3]; | |
1628 | /* Fall through. */ | |
c6fb90c8 L |
1629 | case 3: |
1630 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1631 | /* Fall through. */ |
c6fb90c8 L |
1632 | case 2: |
1633 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1634 | /* Fall through. */ |
c6fb90c8 L |
1635 | case 1: |
1636 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1637 | break; |
1638 | default: | |
1639 | abort (); | |
1640 | } | |
40fb9820 L |
1641 | return x; |
1642 | } | |
1643 | ||
309d3373 JB |
1644 | static INLINE i386_cpu_flags |
1645 | cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y) | |
1646 | { | |
1647 | switch (ARRAY_SIZE (x.array)) | |
1648 | { | |
53467f57 IT |
1649 | case 4: |
1650 | x.array [3] &= ~y.array [3]; | |
1651 | /* Fall through. */ | |
309d3373 JB |
1652 | case 3: |
1653 | x.array [2] &= ~y.array [2]; | |
1a0670f3 | 1654 | /* Fall through. */ |
309d3373 JB |
1655 | case 2: |
1656 | x.array [1] &= ~y.array [1]; | |
1a0670f3 | 1657 | /* Fall through. */ |
309d3373 JB |
1658 | case 1: |
1659 | x.array [0] &= ~y.array [0]; | |
1660 | break; | |
1661 | default: | |
1662 | abort (); | |
1663 | } | |
1664 | return x; | |
1665 | } | |
1666 | ||
c0f3af97 L |
1667 | #define CPU_FLAGS_ARCH_MATCH 0x1 |
1668 | #define CPU_FLAGS_64BIT_MATCH 0x2 | |
a5ff0eb2 | 1669 | #define CPU_FLAGS_AES_MATCH 0x4 |
ce2f5b3c L |
1670 | #define CPU_FLAGS_PCLMUL_MATCH 0x8 |
1671 | #define CPU_FLAGS_AVX_MATCH 0x10 | |
c0f3af97 | 1672 | |
a5ff0eb2 | 1673 | #define CPU_FLAGS_32BIT_MATCH \ |
ce2f5b3c L |
1674 | (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \ |
1675 | | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH) | |
c0f3af97 L |
1676 | #define CPU_FLAGS_PERFECT_MATCH \ |
1677 | (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH) | |
1678 | ||
1679 | /* Return CPU flags match bits. */ | |
3629bb00 | 1680 | |
40fb9820 | 1681 | static int |
d3ce72d0 | 1682 | cpu_flags_match (const insn_template *t) |
40fb9820 | 1683 | { |
c0f3af97 L |
1684 | i386_cpu_flags x = t->cpu_flags; |
1685 | int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0; | |
40fb9820 L |
1686 | |
1687 | x.bitfield.cpu64 = 0; | |
1688 | x.bitfield.cpuno64 = 0; | |
1689 | ||
0dfbf9d7 | 1690 | if (cpu_flags_all_zero (&x)) |
c0f3af97 L |
1691 | { |
1692 | /* This instruction is available on all archs. */ | |
1693 | match |= CPU_FLAGS_32BIT_MATCH; | |
1694 | } | |
3629bb00 L |
1695 | else |
1696 | { | |
c0f3af97 | 1697 | /* This instruction is available only on some archs. */ |
3629bb00 L |
1698 | i386_cpu_flags cpu = cpu_arch_flags; |
1699 | ||
3629bb00 | 1700 | cpu = cpu_flags_and (x, cpu); |
c0f3af97 L |
1701 | if (!cpu_flags_all_zero (&cpu)) |
1702 | { | |
a5ff0eb2 L |
1703 | if (x.bitfield.cpuavx) |
1704 | { | |
ce2f5b3c | 1705 | /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */ |
a5ff0eb2 L |
1706 | if (cpu.bitfield.cpuavx) |
1707 | { | |
1708 | /* Check SSE2AVX. */ | |
1709 | if (!t->opcode_modifier.sse2avx|| sse2avx) | |
1710 | { | |
1711 | match |= (CPU_FLAGS_ARCH_MATCH | |
1712 | | CPU_FLAGS_AVX_MATCH); | |
1713 | /* Check AES. */ | |
1714 | if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes) | |
1715 | match |= CPU_FLAGS_AES_MATCH; | |
ce2f5b3c L |
1716 | /* Check PCLMUL. */ |
1717 | if (!x.bitfield.cpupclmul | |
1718 | || cpu.bitfield.cpupclmul) | |
1719 | match |= CPU_FLAGS_PCLMUL_MATCH; | |
a5ff0eb2 L |
1720 | } |
1721 | } | |
1722 | else | |
1723 | match |= CPU_FLAGS_ARCH_MATCH; | |
1724 | } | |
73b090a9 L |
1725 | else if (x.bitfield.cpuavx512vl) |
1726 | { | |
1727 | /* Match AVX512VL. */ | |
1728 | if (cpu.bitfield.cpuavx512vl) | |
1729 | { | |
1730 | /* Need another match. */ | |
1731 | cpu.bitfield.cpuavx512vl = 0; | |
1732 | if (!cpu_flags_all_zero (&cpu)) | |
1733 | match |= CPU_FLAGS_32BIT_MATCH; | |
1734 | else | |
1735 | match |= CPU_FLAGS_ARCH_MATCH; | |
1736 | } | |
1737 | else | |
1738 | match |= CPU_FLAGS_ARCH_MATCH; | |
1739 | } | |
a5ff0eb2 | 1740 | else |
c0f3af97 L |
1741 | match |= CPU_FLAGS_32BIT_MATCH; |
1742 | } | |
3629bb00 | 1743 | } |
c0f3af97 | 1744 | return match; |
40fb9820 L |
1745 | } |
1746 | ||
c6fb90c8 L |
1747 | static INLINE i386_operand_type |
1748 | operand_type_and (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1749 | { |
c6fb90c8 L |
1750 | switch (ARRAY_SIZE (x.array)) |
1751 | { | |
1752 | case 3: | |
1753 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1754 | /* Fall through. */ |
c6fb90c8 L |
1755 | case 2: |
1756 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1757 | /* Fall through. */ |
c6fb90c8 L |
1758 | case 1: |
1759 | x.array [0] &= y.array [0]; | |
1760 | break; | |
1761 | default: | |
1762 | abort (); | |
1763 | } | |
1764 | return x; | |
40fb9820 L |
1765 | } |
1766 | ||
c6fb90c8 L |
1767 | static INLINE i386_operand_type |
1768 | operand_type_or (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1769 | { |
c6fb90c8 | 1770 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1771 | { |
c6fb90c8 L |
1772 | case 3: |
1773 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1774 | /* Fall through. */ |
c6fb90c8 L |
1775 | case 2: |
1776 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1777 | /* Fall through. */ |
c6fb90c8 L |
1778 | case 1: |
1779 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1780 | break; |
1781 | default: | |
1782 | abort (); | |
1783 | } | |
c6fb90c8 L |
1784 | return x; |
1785 | } | |
40fb9820 | 1786 | |
c6fb90c8 L |
1787 | static INLINE i386_operand_type |
1788 | operand_type_xor (i386_operand_type x, i386_operand_type y) | |
1789 | { | |
1790 | switch (ARRAY_SIZE (x.array)) | |
1791 | { | |
1792 | case 3: | |
1793 | x.array [2] ^= y.array [2]; | |
1a0670f3 | 1794 | /* Fall through. */ |
c6fb90c8 L |
1795 | case 2: |
1796 | x.array [1] ^= y.array [1]; | |
1a0670f3 | 1797 | /* Fall through. */ |
c6fb90c8 L |
1798 | case 1: |
1799 | x.array [0] ^= y.array [0]; | |
1800 | break; | |
1801 | default: | |
1802 | abort (); | |
1803 | } | |
40fb9820 L |
1804 | return x; |
1805 | } | |
1806 | ||
1807 | static const i386_operand_type acc32 = OPERAND_TYPE_ACC32; | |
1808 | static const i386_operand_type acc64 = OPERAND_TYPE_ACC64; | |
1809 | static const i386_operand_type control = OPERAND_TYPE_CONTROL; | |
65da13b5 L |
1810 | static const i386_operand_type inoutportreg |
1811 | = OPERAND_TYPE_INOUTPORTREG; | |
40fb9820 L |
1812 | static const i386_operand_type reg16_inoutportreg |
1813 | = OPERAND_TYPE_REG16_INOUTPORTREG; | |
1814 | static const i386_operand_type disp16 = OPERAND_TYPE_DISP16; | |
1815 | static const i386_operand_type disp32 = OPERAND_TYPE_DISP32; | |
1816 | static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S; | |
1817 | static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32; | |
1818 | static const i386_operand_type anydisp | |
1819 | = OPERAND_TYPE_ANYDISP; | |
40fb9820 | 1820 | static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM; |
43234a1e | 1821 | static const i386_operand_type regmask = OPERAND_TYPE_REGMASK; |
40fb9820 L |
1822 | static const i386_operand_type imm8 = OPERAND_TYPE_IMM8; |
1823 | static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S; | |
1824 | static const i386_operand_type imm16 = OPERAND_TYPE_IMM16; | |
1825 | static const i386_operand_type imm32 = OPERAND_TYPE_IMM32; | |
1826 | static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S; | |
1827 | static const i386_operand_type imm64 = OPERAND_TYPE_IMM64; | |
1828 | static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32; | |
1829 | static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S; | |
1830 | static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S; | |
a683cc34 | 1831 | static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4; |
40fb9820 L |
1832 | |
1833 | enum operand_type | |
1834 | { | |
1835 | reg, | |
40fb9820 L |
1836 | imm, |
1837 | disp, | |
1838 | anymem | |
1839 | }; | |
1840 | ||
c6fb90c8 | 1841 | static INLINE int |
40fb9820 L |
1842 | operand_type_check (i386_operand_type t, enum operand_type c) |
1843 | { | |
1844 | switch (c) | |
1845 | { | |
1846 | case reg: | |
dc821c5f | 1847 | return t.bitfield.reg; |
40fb9820 | 1848 | |
40fb9820 L |
1849 | case imm: |
1850 | return (t.bitfield.imm8 | |
1851 | || t.bitfield.imm8s | |
1852 | || t.bitfield.imm16 | |
1853 | || t.bitfield.imm32 | |
1854 | || t.bitfield.imm32s | |
1855 | || t.bitfield.imm64); | |
1856 | ||
1857 | case disp: | |
1858 | return (t.bitfield.disp8 | |
1859 | || t.bitfield.disp16 | |
1860 | || t.bitfield.disp32 | |
1861 | || t.bitfield.disp32s | |
1862 | || t.bitfield.disp64); | |
1863 | ||
1864 | case anymem: | |
1865 | return (t.bitfield.disp8 | |
1866 | || t.bitfield.disp16 | |
1867 | || t.bitfield.disp32 | |
1868 | || t.bitfield.disp32s | |
1869 | || t.bitfield.disp64 | |
1870 | || t.bitfield.baseindex); | |
1871 | ||
1872 | default: | |
1873 | abort (); | |
1874 | } | |
2cfe26b6 AM |
1875 | |
1876 | return 0; | |
40fb9820 L |
1877 | } |
1878 | ||
ca0d63fe | 1879 | /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on |
5c07affc L |
1880 | operand J for instruction template T. */ |
1881 | ||
1882 | static INLINE int | |
d3ce72d0 | 1883 | match_reg_size (const insn_template *t, unsigned int j) |
5c07affc L |
1884 | { |
1885 | return !((i.types[j].bitfield.byte | |
1886 | && !t->operand_types[j].bitfield.byte) | |
1887 | || (i.types[j].bitfield.word | |
1888 | && !t->operand_types[j].bitfield.word) | |
1889 | || (i.types[j].bitfield.dword | |
1890 | && !t->operand_types[j].bitfield.dword) | |
1891 | || (i.types[j].bitfield.qword | |
ca0d63fe JB |
1892 | && !t->operand_types[j].bitfield.qword) |
1893 | || (i.types[j].bitfield.tbyte | |
1894 | && !t->operand_types[j].bitfield.tbyte)); | |
5c07affc L |
1895 | } |
1896 | ||
1b54b8d7 JB |
1897 | /* Return 1 if there is no conflict in SIMD register on |
1898 | operand J for instruction template T. */ | |
1899 | ||
1900 | static INLINE int | |
1901 | match_simd_size (const insn_template *t, unsigned int j) | |
1902 | { | |
1903 | return !((i.types[j].bitfield.xmmword | |
1904 | && !t->operand_types[j].bitfield.xmmword) | |
1905 | || (i.types[j].bitfield.ymmword | |
1906 | && !t->operand_types[j].bitfield.ymmword) | |
1907 | || (i.types[j].bitfield.zmmword | |
1908 | && !t->operand_types[j].bitfield.zmmword)); | |
1909 | } | |
1910 | ||
5c07affc L |
1911 | /* Return 1 if there is no conflict in any size on operand J for |
1912 | instruction template T. */ | |
1913 | ||
1914 | static INLINE int | |
d3ce72d0 | 1915 | match_mem_size (const insn_template *t, unsigned int j) |
5c07affc L |
1916 | { |
1917 | return (match_reg_size (t, j) | |
1918 | && !((i.types[j].bitfield.unspecified | |
af508cb9 | 1919 | && !i.broadcast |
5c07affc L |
1920 | && !t->operand_types[j].bitfield.unspecified) |
1921 | || (i.types[j].bitfield.fword | |
1922 | && !t->operand_types[j].bitfield.fword) | |
1b54b8d7 JB |
1923 | /* For scalar opcode templates to allow register and memory |
1924 | operands at the same time, some special casing is needed | |
1925 | here. */ | |
1926 | || ((t->operand_types[j].bitfield.regsimd | |
1927 | && !t->opcode_modifier.broadcast | |
1928 | && (t->operand_types[j].bitfield.dword | |
1929 | || t->operand_types[j].bitfield.qword)) | |
1930 | ? (i.types[j].bitfield.xmmword | |
1931 | || i.types[j].bitfield.ymmword | |
1932 | || i.types[j].bitfield.zmmword) | |
1933 | : !match_simd_size(t, j)))); | |
5c07affc L |
1934 | } |
1935 | ||
1936 | /* Return 1 if there is no size conflict on any operands for | |
1937 | instruction template T. */ | |
1938 | ||
1939 | static INLINE int | |
d3ce72d0 | 1940 | operand_size_match (const insn_template *t) |
5c07affc L |
1941 | { |
1942 | unsigned int j; | |
1943 | int match = 1; | |
1944 | ||
1945 | /* Don't check jump instructions. */ | |
1946 | if (t->opcode_modifier.jump | |
1947 | || t->opcode_modifier.jumpbyte | |
1948 | || t->opcode_modifier.jumpdword | |
1949 | || t->opcode_modifier.jumpintersegment) | |
1950 | return match; | |
1951 | ||
1952 | /* Check memory and accumulator operand size. */ | |
1953 | for (j = 0; j < i.operands; j++) | |
1954 | { | |
1b54b8d7 JB |
1955 | if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd |
1956 | && t->operand_types[j].bitfield.anysize) | |
5c07affc L |
1957 | continue; |
1958 | ||
1b54b8d7 | 1959 | if (t->operand_types[j].bitfield.reg |
dc821c5f | 1960 | && !match_reg_size (t, j)) |
5c07affc L |
1961 | { |
1962 | match = 0; | |
1963 | break; | |
1964 | } | |
1965 | ||
1b54b8d7 JB |
1966 | if (t->operand_types[j].bitfield.regsimd |
1967 | && !match_simd_size (t, j)) | |
1968 | { | |
1969 | match = 0; | |
1970 | break; | |
1971 | } | |
1972 | ||
1973 | if (t->operand_types[j].bitfield.acc | |
1974 | && (!match_reg_size (t, j) || !match_simd_size (t, j))) | |
1975 | { | |
1976 | match = 0; | |
1977 | break; | |
1978 | } | |
1979 | ||
5c07affc L |
1980 | if (i.types[j].bitfield.mem && !match_mem_size (t, j)) |
1981 | { | |
1982 | match = 0; | |
1983 | break; | |
1984 | } | |
1985 | } | |
1986 | ||
891edac4 | 1987 | if (match) |
5c07affc | 1988 | return match; |
891edac4 L |
1989 | else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd) |
1990 | { | |
1991 | mismatch: | |
86e026a4 | 1992 | i.error = operand_size_mismatch; |
891edac4 L |
1993 | return 0; |
1994 | } | |
5c07affc L |
1995 | |
1996 | /* Check reverse. */ | |
9c2799c2 | 1997 | gas_assert (i.operands == 2); |
5c07affc L |
1998 | |
1999 | match = 1; | |
2000 | for (j = 0; j < 2; j++) | |
2001 | { | |
dc821c5f JB |
2002 | if ((t->operand_types[j].bitfield.reg |
2003 | || t->operand_types[j].bitfield.acc) | |
5c07affc | 2004 | && !match_reg_size (t, j ? 0 : 1)) |
891edac4 | 2005 | goto mismatch; |
5c07affc L |
2006 | |
2007 | if (i.types[j].bitfield.mem | |
2008 | && !match_mem_size (t, j ? 0 : 1)) | |
891edac4 | 2009 | goto mismatch; |
5c07affc L |
2010 | } |
2011 | ||
2012 | return match; | |
2013 | } | |
2014 | ||
c6fb90c8 | 2015 | static INLINE int |
40fb9820 L |
2016 | operand_type_match (i386_operand_type overlap, |
2017 | i386_operand_type given) | |
2018 | { | |
2019 | i386_operand_type temp = overlap; | |
2020 | ||
2021 | temp.bitfield.jumpabsolute = 0; | |
7d5e4556 | 2022 | temp.bitfield.unspecified = 0; |
5c07affc L |
2023 | temp.bitfield.byte = 0; |
2024 | temp.bitfield.word = 0; | |
2025 | temp.bitfield.dword = 0; | |
2026 | temp.bitfield.fword = 0; | |
2027 | temp.bitfield.qword = 0; | |
2028 | temp.bitfield.tbyte = 0; | |
2029 | temp.bitfield.xmmword = 0; | |
c0f3af97 | 2030 | temp.bitfield.ymmword = 0; |
43234a1e | 2031 | temp.bitfield.zmmword = 0; |
0dfbf9d7 | 2032 | if (operand_type_all_zero (&temp)) |
891edac4 | 2033 | goto mismatch; |
40fb9820 | 2034 | |
891edac4 L |
2035 | if (given.bitfield.baseindex == overlap.bitfield.baseindex |
2036 | && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute) | |
2037 | return 1; | |
2038 | ||
2039 | mismatch: | |
a65babc9 | 2040 | i.error = operand_type_mismatch; |
891edac4 | 2041 | return 0; |
40fb9820 L |
2042 | } |
2043 | ||
7d5e4556 | 2044 | /* If given types g0 and g1 are registers they must be of the same type |
10c17abd JB |
2045 | unless the expected operand type register overlap is null. |
2046 | Memory operand size of certain SIMD instructions is also being checked | |
2047 | here. */ | |
40fb9820 | 2048 | |
c6fb90c8 | 2049 | static INLINE int |
dc821c5f | 2050 | operand_type_register_match (i386_operand_type g0, |
40fb9820 | 2051 | i386_operand_type t0, |
40fb9820 L |
2052 | i386_operand_type g1, |
2053 | i386_operand_type t1) | |
2054 | { | |
10c17abd JB |
2055 | if (!g0.bitfield.reg |
2056 | && !g0.bitfield.regsimd | |
2057 | && (!operand_type_check (g0, anymem) | |
2058 | || g0.bitfield.unspecified | |
2059 | || !t0.bitfield.regsimd)) | |
40fb9820 L |
2060 | return 1; |
2061 | ||
10c17abd JB |
2062 | if (!g1.bitfield.reg |
2063 | && !g1.bitfield.regsimd | |
2064 | && (!operand_type_check (g1, anymem) | |
2065 | || g1.bitfield.unspecified | |
2066 | || !t1.bitfield.regsimd)) | |
40fb9820 L |
2067 | return 1; |
2068 | ||
dc821c5f JB |
2069 | if (g0.bitfield.byte == g1.bitfield.byte |
2070 | && g0.bitfield.word == g1.bitfield.word | |
2071 | && g0.bitfield.dword == g1.bitfield.dword | |
10c17abd JB |
2072 | && g0.bitfield.qword == g1.bitfield.qword |
2073 | && g0.bitfield.xmmword == g1.bitfield.xmmword | |
2074 | && g0.bitfield.ymmword == g1.bitfield.ymmword | |
2075 | && g0.bitfield.zmmword == g1.bitfield.zmmword) | |
40fb9820 L |
2076 | return 1; |
2077 | ||
dc821c5f JB |
2078 | if (!(t0.bitfield.byte & t1.bitfield.byte) |
2079 | && !(t0.bitfield.word & t1.bitfield.word) | |
2080 | && !(t0.bitfield.dword & t1.bitfield.dword) | |
10c17abd JB |
2081 | && !(t0.bitfield.qword & t1.bitfield.qword) |
2082 | && !(t0.bitfield.xmmword & t1.bitfield.xmmword) | |
2083 | && !(t0.bitfield.ymmword & t1.bitfield.ymmword) | |
2084 | && !(t0.bitfield.zmmword & t1.bitfield.zmmword)) | |
891edac4 L |
2085 | return 1; |
2086 | ||
a65babc9 | 2087 | i.error = register_type_mismatch; |
891edac4 L |
2088 | |
2089 | return 0; | |
40fb9820 L |
2090 | } |
2091 | ||
4c692bc7 JB |
2092 | static INLINE unsigned int |
2093 | register_number (const reg_entry *r) | |
2094 | { | |
2095 | unsigned int nr = r->reg_num; | |
2096 | ||
2097 | if (r->reg_flags & RegRex) | |
2098 | nr += 8; | |
2099 | ||
200cbe0f L |
2100 | if (r->reg_flags & RegVRex) |
2101 | nr += 16; | |
2102 | ||
4c692bc7 JB |
2103 | return nr; |
2104 | } | |
2105 | ||
252b5132 | 2106 | static INLINE unsigned int |
40fb9820 | 2107 | mode_from_disp_size (i386_operand_type t) |
252b5132 | 2108 | { |
b5014f7a | 2109 | if (t.bitfield.disp8) |
40fb9820 L |
2110 | return 1; |
2111 | else if (t.bitfield.disp16 | |
2112 | || t.bitfield.disp32 | |
2113 | || t.bitfield.disp32s) | |
2114 | return 2; | |
2115 | else | |
2116 | return 0; | |
252b5132 RH |
2117 | } |
2118 | ||
2119 | static INLINE int | |
65879393 | 2120 | fits_in_signed_byte (addressT num) |
252b5132 | 2121 | { |
65879393 | 2122 | return num + 0x80 <= 0xff; |
47926f60 | 2123 | } |
252b5132 RH |
2124 | |
2125 | static INLINE int | |
65879393 | 2126 | fits_in_unsigned_byte (addressT num) |
252b5132 | 2127 | { |
65879393 | 2128 | return num <= 0xff; |
47926f60 | 2129 | } |
252b5132 RH |
2130 | |
2131 | static INLINE int | |
65879393 | 2132 | fits_in_unsigned_word (addressT num) |
252b5132 | 2133 | { |
65879393 | 2134 | return num <= 0xffff; |
47926f60 | 2135 | } |
252b5132 RH |
2136 | |
2137 | static INLINE int | |
65879393 | 2138 | fits_in_signed_word (addressT num) |
252b5132 | 2139 | { |
65879393 | 2140 | return num + 0x8000 <= 0xffff; |
47926f60 | 2141 | } |
2a962e6d | 2142 | |
3e73aa7c | 2143 | static INLINE int |
65879393 | 2144 | fits_in_signed_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2145 | { |
2146 | #ifndef BFD64 | |
2147 | return 1; | |
2148 | #else | |
65879393 | 2149 | return num + 0x80000000 <= 0xffffffff; |
3e73aa7c JH |
2150 | #endif |
2151 | } /* fits_in_signed_long() */ | |
2a962e6d | 2152 | |
3e73aa7c | 2153 | static INLINE int |
65879393 | 2154 | fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2155 | { |
2156 | #ifndef BFD64 | |
2157 | return 1; | |
2158 | #else | |
65879393 | 2159 | return num <= 0xffffffff; |
3e73aa7c JH |
2160 | #endif |
2161 | } /* fits_in_unsigned_long() */ | |
252b5132 | 2162 | |
43234a1e | 2163 | static INLINE int |
b5014f7a | 2164 | fits_in_disp8 (offsetT num) |
43234a1e L |
2165 | { |
2166 | int shift = i.memshift; | |
2167 | unsigned int mask; | |
2168 | ||
2169 | if (shift == -1) | |
2170 | abort (); | |
2171 | ||
2172 | mask = (1 << shift) - 1; | |
2173 | ||
2174 | /* Return 0 if NUM isn't properly aligned. */ | |
2175 | if ((num & mask)) | |
2176 | return 0; | |
2177 | ||
2178 | /* Check if NUM will fit in 8bit after shift. */ | |
2179 | return fits_in_signed_byte (num >> shift); | |
2180 | } | |
2181 | ||
a683cc34 SP |
2182 | static INLINE int |
2183 | fits_in_imm4 (offsetT num) | |
2184 | { | |
2185 | return (num & 0xf) == num; | |
2186 | } | |
2187 | ||
40fb9820 | 2188 | static i386_operand_type |
e3bb37b5 | 2189 | smallest_imm_type (offsetT num) |
252b5132 | 2190 | { |
40fb9820 | 2191 | i386_operand_type t; |
7ab9ffdd | 2192 | |
0dfbf9d7 | 2193 | operand_type_set (&t, 0); |
40fb9820 L |
2194 | t.bitfield.imm64 = 1; |
2195 | ||
2196 | if (cpu_arch_tune != PROCESSOR_I486 && num == 1) | |
e413e4e9 AM |
2197 | { |
2198 | /* This code is disabled on the 486 because all the Imm1 forms | |
2199 | in the opcode table are slower on the i486. They're the | |
2200 | versions with the implicitly specified single-position | |
2201 | displacement, which has another syntax if you really want to | |
2202 | use that form. */ | |
40fb9820 L |
2203 | t.bitfield.imm1 = 1; |
2204 | t.bitfield.imm8 = 1; | |
2205 | t.bitfield.imm8s = 1; | |
2206 | t.bitfield.imm16 = 1; | |
2207 | t.bitfield.imm32 = 1; | |
2208 | t.bitfield.imm32s = 1; | |
2209 | } | |
2210 | else if (fits_in_signed_byte (num)) | |
2211 | { | |
2212 | t.bitfield.imm8 = 1; | |
2213 | t.bitfield.imm8s = 1; | |
2214 | t.bitfield.imm16 = 1; | |
2215 | t.bitfield.imm32 = 1; | |
2216 | t.bitfield.imm32s = 1; | |
2217 | } | |
2218 | else if (fits_in_unsigned_byte (num)) | |
2219 | { | |
2220 | t.bitfield.imm8 = 1; | |
2221 | t.bitfield.imm16 = 1; | |
2222 | t.bitfield.imm32 = 1; | |
2223 | t.bitfield.imm32s = 1; | |
2224 | } | |
2225 | else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
2226 | { | |
2227 | t.bitfield.imm16 = 1; | |
2228 | t.bitfield.imm32 = 1; | |
2229 | t.bitfield.imm32s = 1; | |
2230 | } | |
2231 | else if (fits_in_signed_long (num)) | |
2232 | { | |
2233 | t.bitfield.imm32 = 1; | |
2234 | t.bitfield.imm32s = 1; | |
2235 | } | |
2236 | else if (fits_in_unsigned_long (num)) | |
2237 | t.bitfield.imm32 = 1; | |
2238 | ||
2239 | return t; | |
47926f60 | 2240 | } |
252b5132 | 2241 | |
847f7ad4 | 2242 | static offsetT |
e3bb37b5 | 2243 | offset_in_range (offsetT val, int size) |
847f7ad4 | 2244 | { |
508866be | 2245 | addressT mask; |
ba2adb93 | 2246 | |
847f7ad4 AM |
2247 | switch (size) |
2248 | { | |
508866be L |
2249 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
2250 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 2251 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
3e73aa7c JH |
2252 | #ifdef BFD64 |
2253 | case 8: mask = ((addressT) 2 << 63) - 1; break; | |
2254 | #endif | |
47926f60 | 2255 | default: abort (); |
847f7ad4 AM |
2256 | } |
2257 | ||
9de868bf L |
2258 | #ifdef BFD64 |
2259 | /* If BFD64, sign extend val for 32bit address mode. */ | |
2260 | if (flag_code != CODE_64BIT | |
2261 | || i.prefix[ADDR_PREFIX]) | |
3e73aa7c JH |
2262 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) |
2263 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
fa289fb8 | 2264 | #endif |
ba2adb93 | 2265 | |
47926f60 | 2266 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
847f7ad4 AM |
2267 | { |
2268 | char buf1[40], buf2[40]; | |
2269 | ||
2270 | sprint_value (buf1, val); | |
2271 | sprint_value (buf2, val & mask); | |
2272 | as_warn (_("%s shortened to %s"), buf1, buf2); | |
2273 | } | |
2274 | return val & mask; | |
2275 | } | |
2276 | ||
c32fa91d L |
2277 | enum PREFIX_GROUP |
2278 | { | |
2279 | PREFIX_EXIST = 0, | |
2280 | PREFIX_LOCK, | |
2281 | PREFIX_REP, | |
04ef582a | 2282 | PREFIX_DS, |
c32fa91d L |
2283 | PREFIX_OTHER |
2284 | }; | |
2285 | ||
2286 | /* Returns | |
2287 | a. PREFIX_EXIST if attempting to add a prefix where one from the | |
2288 | same class already exists. | |
2289 | b. PREFIX_LOCK if lock prefix is added. | |
2290 | c. PREFIX_REP if rep/repne prefix is added. | |
04ef582a L |
2291 | d. PREFIX_DS if ds prefix is added. |
2292 | e. PREFIX_OTHER if other prefix is added. | |
c32fa91d L |
2293 | */ |
2294 | ||
2295 | static enum PREFIX_GROUP | |
e3bb37b5 | 2296 | add_prefix (unsigned int prefix) |
252b5132 | 2297 | { |
c32fa91d | 2298 | enum PREFIX_GROUP ret = PREFIX_OTHER; |
b1905489 | 2299 | unsigned int q; |
252b5132 | 2300 | |
29b0f896 AM |
2301 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
2302 | && flag_code == CODE_64BIT) | |
b1905489 | 2303 | { |
161a04f6 L |
2304 | if ((i.prefix[REX_PREFIX] & prefix & REX_W) |
2305 | || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B)) | |
2306 | && (prefix & (REX_R | REX_X | REX_B)))) | |
c32fa91d | 2307 | ret = PREFIX_EXIST; |
b1905489 JB |
2308 | q = REX_PREFIX; |
2309 | } | |
3e73aa7c | 2310 | else |
b1905489 JB |
2311 | { |
2312 | switch (prefix) | |
2313 | { | |
2314 | default: | |
2315 | abort (); | |
2316 | ||
b1905489 | 2317 | case DS_PREFIX_OPCODE: |
04ef582a L |
2318 | ret = PREFIX_DS; |
2319 | /* Fall through. */ | |
2320 | case CS_PREFIX_OPCODE: | |
b1905489 JB |
2321 | case ES_PREFIX_OPCODE: |
2322 | case FS_PREFIX_OPCODE: | |
2323 | case GS_PREFIX_OPCODE: | |
2324 | case SS_PREFIX_OPCODE: | |
2325 | q = SEG_PREFIX; | |
2326 | break; | |
2327 | ||
2328 | case REPNE_PREFIX_OPCODE: | |
2329 | case REPE_PREFIX_OPCODE: | |
c32fa91d L |
2330 | q = REP_PREFIX; |
2331 | ret = PREFIX_REP; | |
2332 | break; | |
2333 | ||
b1905489 | 2334 | case LOCK_PREFIX_OPCODE: |
c32fa91d L |
2335 | q = LOCK_PREFIX; |
2336 | ret = PREFIX_LOCK; | |
b1905489 JB |
2337 | break; |
2338 | ||
2339 | case FWAIT_OPCODE: | |
2340 | q = WAIT_PREFIX; | |
2341 | break; | |
2342 | ||
2343 | case ADDR_PREFIX_OPCODE: | |
2344 | q = ADDR_PREFIX; | |
2345 | break; | |
2346 | ||
2347 | case DATA_PREFIX_OPCODE: | |
2348 | q = DATA_PREFIX; | |
2349 | break; | |
2350 | } | |
2351 | if (i.prefix[q] != 0) | |
c32fa91d | 2352 | ret = PREFIX_EXIST; |
b1905489 | 2353 | } |
252b5132 | 2354 | |
b1905489 | 2355 | if (ret) |
252b5132 | 2356 | { |
b1905489 JB |
2357 | if (!i.prefix[q]) |
2358 | ++i.prefixes; | |
2359 | i.prefix[q] |= prefix; | |
252b5132 | 2360 | } |
b1905489 JB |
2361 | else |
2362 | as_bad (_("same type of prefix used twice")); | |
252b5132 | 2363 | |
252b5132 RH |
2364 | return ret; |
2365 | } | |
2366 | ||
2367 | static void | |
78f12dd3 | 2368 | update_code_flag (int value, int check) |
eecb386c | 2369 | { |
78f12dd3 L |
2370 | PRINTF_LIKE ((*as_error)); |
2371 | ||
1e9cc1c2 | 2372 | flag_code = (enum flag_code) value; |
40fb9820 L |
2373 | if (flag_code == CODE_64BIT) |
2374 | { | |
2375 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2376 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
40fb9820 L |
2377 | } |
2378 | else | |
2379 | { | |
2380 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2381 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
40fb9820 L |
2382 | } |
2383 | if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm ) | |
3e73aa7c | 2384 | { |
78f12dd3 L |
2385 | if (check) |
2386 | as_error = as_fatal; | |
2387 | else | |
2388 | as_error = as_bad; | |
2389 | (*as_error) (_("64bit mode not supported on `%s'."), | |
2390 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2391 | } |
40fb9820 | 2392 | if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) |
3e73aa7c | 2393 | { |
78f12dd3 L |
2394 | if (check) |
2395 | as_error = as_fatal; | |
2396 | else | |
2397 | as_error = as_bad; | |
2398 | (*as_error) (_("32bit mode not supported on `%s'."), | |
2399 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2400 | } |
eecb386c AM |
2401 | stackop_size = '\0'; |
2402 | } | |
2403 | ||
78f12dd3 L |
2404 | static void |
2405 | set_code_flag (int value) | |
2406 | { | |
2407 | update_code_flag (value, 0); | |
2408 | } | |
2409 | ||
eecb386c | 2410 | static void |
e3bb37b5 | 2411 | set_16bit_gcc_code_flag (int new_code_flag) |
252b5132 | 2412 | { |
1e9cc1c2 | 2413 | flag_code = (enum flag_code) new_code_flag; |
40fb9820 L |
2414 | if (flag_code != CODE_16BIT) |
2415 | abort (); | |
2416 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2417 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
9306ca4a | 2418 | stackop_size = LONG_MNEM_SUFFIX; |
252b5132 RH |
2419 | } |
2420 | ||
2421 | static void | |
e3bb37b5 | 2422 | set_intel_syntax (int syntax_flag) |
252b5132 RH |
2423 | { |
2424 | /* Find out if register prefixing is specified. */ | |
2425 | int ask_naked_reg = 0; | |
2426 | ||
2427 | SKIP_WHITESPACE (); | |
29b0f896 | 2428 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
252b5132 | 2429 | { |
d02603dc NC |
2430 | char *string; |
2431 | int e = get_symbol_name (&string); | |
252b5132 | 2432 | |
47926f60 | 2433 | if (strcmp (string, "prefix") == 0) |
252b5132 | 2434 | ask_naked_reg = 1; |
47926f60 | 2435 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
2436 | ask_naked_reg = -1; |
2437 | else | |
d0b47220 | 2438 | as_bad (_("bad argument to syntax directive.")); |
d02603dc | 2439 | (void) restore_line_pointer (e); |
252b5132 RH |
2440 | } |
2441 | demand_empty_rest_of_line (); | |
c3332e24 | 2442 | |
252b5132 RH |
2443 | intel_syntax = syntax_flag; |
2444 | ||
2445 | if (ask_naked_reg == 0) | |
f86103b7 AM |
2446 | allow_naked_reg = (intel_syntax |
2447 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); | |
252b5132 RH |
2448 | else |
2449 | allow_naked_reg = (ask_naked_reg < 0); | |
9306ca4a | 2450 | |
ee86248c | 2451 | expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0); |
7ab9ffdd | 2452 | |
e4a3b5a4 | 2453 | identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; |
9306ca4a | 2454 | identifier_chars['$'] = intel_syntax ? '$' : 0; |
e4a3b5a4 | 2455 | register_prefix = allow_naked_reg ? "" : "%"; |
252b5132 RH |
2456 | } |
2457 | ||
1efbbeb4 L |
2458 | static void |
2459 | set_intel_mnemonic (int mnemonic_flag) | |
2460 | { | |
e1d4d893 | 2461 | intel_mnemonic = mnemonic_flag; |
1efbbeb4 L |
2462 | } |
2463 | ||
db51cc60 L |
2464 | static void |
2465 | set_allow_index_reg (int flag) | |
2466 | { | |
2467 | allow_index_reg = flag; | |
2468 | } | |
2469 | ||
cb19c032 | 2470 | static void |
7bab8ab5 | 2471 | set_check (int what) |
cb19c032 | 2472 | { |
7bab8ab5 JB |
2473 | enum check_kind *kind; |
2474 | const char *str; | |
2475 | ||
2476 | if (what) | |
2477 | { | |
2478 | kind = &operand_check; | |
2479 | str = "operand"; | |
2480 | } | |
2481 | else | |
2482 | { | |
2483 | kind = &sse_check; | |
2484 | str = "sse"; | |
2485 | } | |
2486 | ||
cb19c032 L |
2487 | SKIP_WHITESPACE (); |
2488 | ||
2489 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
2490 | { | |
d02603dc NC |
2491 | char *string; |
2492 | int e = get_symbol_name (&string); | |
cb19c032 L |
2493 | |
2494 | if (strcmp (string, "none") == 0) | |
7bab8ab5 | 2495 | *kind = check_none; |
cb19c032 | 2496 | else if (strcmp (string, "warning") == 0) |
7bab8ab5 | 2497 | *kind = check_warning; |
cb19c032 | 2498 | else if (strcmp (string, "error") == 0) |
7bab8ab5 | 2499 | *kind = check_error; |
cb19c032 | 2500 | else |
7bab8ab5 | 2501 | as_bad (_("bad argument to %s_check directive."), str); |
d02603dc | 2502 | (void) restore_line_pointer (e); |
cb19c032 L |
2503 | } |
2504 | else | |
7bab8ab5 | 2505 | as_bad (_("missing argument for %s_check directive"), str); |
cb19c032 L |
2506 | |
2507 | demand_empty_rest_of_line (); | |
2508 | } | |
2509 | ||
8a9036a4 L |
2510 | static void |
2511 | check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED, | |
1e9cc1c2 | 2512 | i386_cpu_flags new_flag ATTRIBUTE_UNUSED) |
8a9036a4 L |
2513 | { |
2514 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2515 | static const char *arch; | |
2516 | ||
2517 | /* Intel LIOM is only supported on ELF. */ | |
2518 | if (!IS_ELF) | |
2519 | return; | |
2520 | ||
2521 | if (!arch) | |
2522 | { | |
2523 | /* Use cpu_arch_name if it is set in md_parse_option. Otherwise | |
2524 | use default_arch. */ | |
2525 | arch = cpu_arch_name; | |
2526 | if (!arch) | |
2527 | arch = default_arch; | |
2528 | } | |
2529 | ||
81486035 L |
2530 | /* If we are targeting Intel MCU, we must enable it. */ |
2531 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU | |
2532 | || new_flag.bitfield.cpuiamcu) | |
2533 | return; | |
2534 | ||
3632d14b | 2535 | /* If we are targeting Intel L1OM, we must enable it. */ |
8a9036a4 | 2536 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM |
1e9cc1c2 | 2537 | || new_flag.bitfield.cpul1om) |
8a9036a4 | 2538 | return; |
76ba9986 | 2539 | |
7a9068fe L |
2540 | /* If we are targeting Intel K1OM, we must enable it. */ |
2541 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM | |
2542 | || new_flag.bitfield.cpuk1om) | |
2543 | return; | |
2544 | ||
8a9036a4 L |
2545 | as_bad (_("`%s' is not supported on `%s'"), name, arch); |
2546 | #endif | |
2547 | } | |
2548 | ||
e413e4e9 | 2549 | static void |
e3bb37b5 | 2550 | set_cpu_arch (int dummy ATTRIBUTE_UNUSED) |
e413e4e9 | 2551 | { |
47926f60 | 2552 | SKIP_WHITESPACE (); |
e413e4e9 | 2553 | |
29b0f896 | 2554 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
e413e4e9 | 2555 | { |
d02603dc NC |
2556 | char *string; |
2557 | int e = get_symbol_name (&string); | |
91d6fa6a | 2558 | unsigned int j; |
40fb9820 | 2559 | i386_cpu_flags flags; |
e413e4e9 | 2560 | |
91d6fa6a | 2561 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
e413e4e9 | 2562 | { |
91d6fa6a | 2563 | if (strcmp (string, cpu_arch[j].name) == 0) |
e413e4e9 | 2564 | { |
91d6fa6a | 2565 | check_cpu_arch_compatible (string, cpu_arch[j].flags); |
8a9036a4 | 2566 | |
5c6af06e JB |
2567 | if (*string != '.') |
2568 | { | |
91d6fa6a | 2569 | cpu_arch_name = cpu_arch[j].name; |
5c6af06e | 2570 | cpu_sub_arch_name = NULL; |
91d6fa6a | 2571 | cpu_arch_flags = cpu_arch[j].flags; |
40fb9820 L |
2572 | if (flag_code == CODE_64BIT) |
2573 | { | |
2574 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2575 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
2576 | } | |
2577 | else | |
2578 | { | |
2579 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2580 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
2581 | } | |
91d6fa6a NC |
2582 | cpu_arch_isa = cpu_arch[j].type; |
2583 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
ccc9c027 L |
2584 | if (!cpu_arch_tune_set) |
2585 | { | |
2586 | cpu_arch_tune = cpu_arch_isa; | |
2587 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
2588 | } | |
5c6af06e JB |
2589 | break; |
2590 | } | |
40fb9820 | 2591 | |
293f5f65 L |
2592 | flags = cpu_flags_or (cpu_arch_flags, |
2593 | cpu_arch[j].flags); | |
81486035 | 2594 | |
5b64d091 | 2595 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
5c6af06e | 2596 | { |
6305a203 L |
2597 | if (cpu_sub_arch_name) |
2598 | { | |
2599 | char *name = cpu_sub_arch_name; | |
2600 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 2601 | cpu_arch[j].name, |
1bf57e9f | 2602 | (const char *) NULL); |
6305a203 L |
2603 | free (name); |
2604 | } | |
2605 | else | |
91d6fa6a | 2606 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
40fb9820 | 2607 | cpu_arch_flags = flags; |
a586129e | 2608 | cpu_arch_isa_flags = flags; |
5c6af06e | 2609 | } |
d02603dc | 2610 | (void) restore_line_pointer (e); |
5c6af06e JB |
2611 | demand_empty_rest_of_line (); |
2612 | return; | |
e413e4e9 AM |
2613 | } |
2614 | } | |
293f5f65 L |
2615 | |
2616 | if (*string == '.' && j >= ARRAY_SIZE (cpu_arch)) | |
2617 | { | |
33eaf5de | 2618 | /* Disable an ISA extension. */ |
293f5f65 L |
2619 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
2620 | if (strcmp (string + 1, cpu_noarch [j].name) == 0) | |
2621 | { | |
2622 | flags = cpu_flags_and_not (cpu_arch_flags, | |
2623 | cpu_noarch[j].flags); | |
2624 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
2625 | { | |
2626 | if (cpu_sub_arch_name) | |
2627 | { | |
2628 | char *name = cpu_sub_arch_name; | |
2629 | cpu_sub_arch_name = concat (name, string, | |
2630 | (const char *) NULL); | |
2631 | free (name); | |
2632 | } | |
2633 | else | |
2634 | cpu_sub_arch_name = xstrdup (string); | |
2635 | cpu_arch_flags = flags; | |
2636 | cpu_arch_isa_flags = flags; | |
2637 | } | |
2638 | (void) restore_line_pointer (e); | |
2639 | demand_empty_rest_of_line (); | |
2640 | return; | |
2641 | } | |
2642 | ||
2643 | j = ARRAY_SIZE (cpu_arch); | |
2644 | } | |
2645 | ||
91d6fa6a | 2646 | if (j >= ARRAY_SIZE (cpu_arch)) |
e413e4e9 AM |
2647 | as_bad (_("no such architecture: `%s'"), string); |
2648 | ||
2649 | *input_line_pointer = e; | |
2650 | } | |
2651 | else | |
2652 | as_bad (_("missing cpu architecture")); | |
2653 | ||
fddf5b5b AM |
2654 | no_cond_jump_promotion = 0; |
2655 | if (*input_line_pointer == ',' | |
29b0f896 | 2656 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
fddf5b5b | 2657 | { |
d02603dc NC |
2658 | char *string; |
2659 | char e; | |
2660 | ||
2661 | ++input_line_pointer; | |
2662 | e = get_symbol_name (&string); | |
fddf5b5b AM |
2663 | |
2664 | if (strcmp (string, "nojumps") == 0) | |
2665 | no_cond_jump_promotion = 1; | |
2666 | else if (strcmp (string, "jumps") == 0) | |
2667 | ; | |
2668 | else | |
2669 | as_bad (_("no such architecture modifier: `%s'"), string); | |
2670 | ||
d02603dc | 2671 | (void) restore_line_pointer (e); |
fddf5b5b AM |
2672 | } |
2673 | ||
e413e4e9 AM |
2674 | demand_empty_rest_of_line (); |
2675 | } | |
2676 | ||
8a9036a4 L |
2677 | enum bfd_architecture |
2678 | i386_arch (void) | |
2679 | { | |
3632d14b | 2680 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 L |
2681 | { |
2682 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2683 | || flag_code != CODE_64BIT) | |
2684 | as_fatal (_("Intel L1OM is 64bit ELF only")); | |
2685 | return bfd_arch_l1om; | |
2686 | } | |
7a9068fe L |
2687 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2688 | { | |
2689 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2690 | || flag_code != CODE_64BIT) | |
2691 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2692 | return bfd_arch_k1om; | |
2693 | } | |
81486035 L |
2694 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
2695 | { | |
2696 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2697 | || flag_code == CODE_64BIT) | |
2698 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2699 | return bfd_arch_iamcu; | |
2700 | } | |
8a9036a4 L |
2701 | else |
2702 | return bfd_arch_i386; | |
2703 | } | |
2704 | ||
b9d79e03 | 2705 | unsigned long |
7016a5d5 | 2706 | i386_mach (void) |
b9d79e03 | 2707 | { |
351f65ca | 2708 | if (!strncmp (default_arch, "x86_64", 6)) |
8a9036a4 | 2709 | { |
3632d14b | 2710 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 2711 | { |
351f65ca L |
2712 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour |
2713 | || default_arch[6] != '\0') | |
8a9036a4 L |
2714 | as_fatal (_("Intel L1OM is 64bit ELF only")); |
2715 | return bfd_mach_l1om; | |
2716 | } | |
7a9068fe L |
2717 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2718 | { | |
2719 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2720 | || default_arch[6] != '\0') | |
2721 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2722 | return bfd_mach_k1om; | |
2723 | } | |
351f65ca | 2724 | else if (default_arch[6] == '\0') |
8a9036a4 | 2725 | return bfd_mach_x86_64; |
351f65ca L |
2726 | else |
2727 | return bfd_mach_x64_32; | |
8a9036a4 | 2728 | } |
5197d474 L |
2729 | else if (!strcmp (default_arch, "i386") |
2730 | || !strcmp (default_arch, "iamcu")) | |
81486035 L |
2731 | { |
2732 | if (cpu_arch_isa == PROCESSOR_IAMCU) | |
2733 | { | |
2734 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
2735 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2736 | return bfd_mach_i386_iamcu; | |
2737 | } | |
2738 | else | |
2739 | return bfd_mach_i386_i386; | |
2740 | } | |
b9d79e03 | 2741 | else |
2b5d6a91 | 2742 | as_fatal (_("unknown architecture")); |
b9d79e03 | 2743 | } |
b9d79e03 | 2744 | \f |
252b5132 | 2745 | void |
7016a5d5 | 2746 | md_begin (void) |
252b5132 RH |
2747 | { |
2748 | const char *hash_err; | |
2749 | ||
86fa6981 L |
2750 | /* Support pseudo prefixes like {disp32}. */ |
2751 | lex_type ['{'] = LEX_BEGIN_NAME; | |
2752 | ||
47926f60 | 2753 | /* Initialize op_hash hash table. */ |
252b5132 RH |
2754 | op_hash = hash_new (); |
2755 | ||
2756 | { | |
d3ce72d0 | 2757 | const insn_template *optab; |
29b0f896 | 2758 | templates *core_optab; |
252b5132 | 2759 | |
47926f60 KH |
2760 | /* Setup for loop. */ |
2761 | optab = i386_optab; | |
add39d23 | 2762 | core_optab = XNEW (templates); |
252b5132 RH |
2763 | core_optab->start = optab; |
2764 | ||
2765 | while (1) | |
2766 | { | |
2767 | ++optab; | |
2768 | if (optab->name == NULL | |
2769 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
2770 | { | |
2771 | /* different name --> ship out current template list; | |
47926f60 | 2772 | add to hash table; & begin anew. */ |
252b5132 RH |
2773 | core_optab->end = optab; |
2774 | hash_err = hash_insert (op_hash, | |
2775 | (optab - 1)->name, | |
5a49b8ac | 2776 | (void *) core_optab); |
252b5132 RH |
2777 | if (hash_err) |
2778 | { | |
b37df7c4 | 2779 | as_fatal (_("can't hash %s: %s"), |
252b5132 RH |
2780 | (optab - 1)->name, |
2781 | hash_err); | |
2782 | } | |
2783 | if (optab->name == NULL) | |
2784 | break; | |
add39d23 | 2785 | core_optab = XNEW (templates); |
252b5132 RH |
2786 | core_optab->start = optab; |
2787 | } | |
2788 | } | |
2789 | } | |
2790 | ||
47926f60 | 2791 | /* Initialize reg_hash hash table. */ |
252b5132 RH |
2792 | reg_hash = hash_new (); |
2793 | { | |
29b0f896 | 2794 | const reg_entry *regtab; |
c3fe08fa | 2795 | unsigned int regtab_size = i386_regtab_size; |
252b5132 | 2796 | |
c3fe08fa | 2797 | for (regtab = i386_regtab; regtab_size--; regtab++) |
252b5132 | 2798 | { |
5a49b8ac | 2799 | hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab); |
252b5132 | 2800 | if (hash_err) |
b37df7c4 | 2801 | as_fatal (_("can't hash %s: %s"), |
3e73aa7c JH |
2802 | regtab->reg_name, |
2803 | hash_err); | |
252b5132 RH |
2804 | } |
2805 | } | |
2806 | ||
47926f60 | 2807 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 | 2808 | { |
29b0f896 AM |
2809 | int c; |
2810 | char *p; | |
252b5132 RH |
2811 | |
2812 | for (c = 0; c < 256; c++) | |
2813 | { | |
3882b010 | 2814 | if (ISDIGIT (c)) |
252b5132 RH |
2815 | { |
2816 | digit_chars[c] = c; | |
2817 | mnemonic_chars[c] = c; | |
2818 | register_chars[c] = c; | |
2819 | operand_chars[c] = c; | |
2820 | } | |
3882b010 | 2821 | else if (ISLOWER (c)) |
252b5132 RH |
2822 | { |
2823 | mnemonic_chars[c] = c; | |
2824 | register_chars[c] = c; | |
2825 | operand_chars[c] = c; | |
2826 | } | |
3882b010 | 2827 | else if (ISUPPER (c)) |
252b5132 | 2828 | { |
3882b010 | 2829 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
2830 | register_chars[c] = mnemonic_chars[c]; |
2831 | operand_chars[c] = c; | |
2832 | } | |
43234a1e | 2833 | else if (c == '{' || c == '}') |
86fa6981 L |
2834 | { |
2835 | mnemonic_chars[c] = c; | |
2836 | operand_chars[c] = c; | |
2837 | } | |
252b5132 | 2838 | |
3882b010 | 2839 | if (ISALPHA (c) || ISDIGIT (c)) |
252b5132 RH |
2840 | identifier_chars[c] = c; |
2841 | else if (c >= 128) | |
2842 | { | |
2843 | identifier_chars[c] = c; | |
2844 | operand_chars[c] = c; | |
2845 | } | |
2846 | } | |
2847 | ||
2848 | #ifdef LEX_AT | |
2849 | identifier_chars['@'] = '@'; | |
32137342 NC |
2850 | #endif |
2851 | #ifdef LEX_QM | |
2852 | identifier_chars['?'] = '?'; | |
2853 | operand_chars['?'] = '?'; | |
252b5132 | 2854 | #endif |
252b5132 | 2855 | digit_chars['-'] = '-'; |
c0f3af97 | 2856 | mnemonic_chars['_'] = '_'; |
791fe849 | 2857 | mnemonic_chars['-'] = '-'; |
0003779b | 2858 | mnemonic_chars['.'] = '.'; |
252b5132 RH |
2859 | identifier_chars['_'] = '_'; |
2860 | identifier_chars['.'] = '.'; | |
2861 | ||
2862 | for (p = operand_special_chars; *p != '\0'; p++) | |
2863 | operand_chars[(unsigned char) *p] = *p; | |
2864 | } | |
2865 | ||
a4447b93 RH |
2866 | if (flag_code == CODE_64BIT) |
2867 | { | |
ca19b261 KT |
2868 | #if defined (OBJ_COFF) && defined (TE_PE) |
2869 | x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour | |
2870 | ? 32 : 16); | |
2871 | #else | |
a4447b93 | 2872 | x86_dwarf2_return_column = 16; |
ca19b261 | 2873 | #endif |
61ff971f | 2874 | x86_cie_data_alignment = -8; |
a4447b93 RH |
2875 | } |
2876 | else | |
2877 | { | |
2878 | x86_dwarf2_return_column = 8; | |
2879 | x86_cie_data_alignment = -4; | |
2880 | } | |
252b5132 RH |
2881 | } |
2882 | ||
2883 | void | |
e3bb37b5 | 2884 | i386_print_statistics (FILE *file) |
252b5132 RH |
2885 | { |
2886 | hash_print_statistics (file, "i386 opcode", op_hash); | |
2887 | hash_print_statistics (file, "i386 register", reg_hash); | |
2888 | } | |
2889 | \f | |
252b5132 RH |
2890 | #ifdef DEBUG386 |
2891 | ||
ce8a8b2f | 2892 | /* Debugging routines for md_assemble. */ |
d3ce72d0 | 2893 | static void pte (insn_template *); |
40fb9820 | 2894 | static void pt (i386_operand_type); |
e3bb37b5 L |
2895 | static void pe (expressionS *); |
2896 | static void ps (symbolS *); | |
252b5132 RH |
2897 | |
2898 | static void | |
e3bb37b5 | 2899 | pi (char *line, i386_insn *x) |
252b5132 | 2900 | { |
09137c09 | 2901 | unsigned int j; |
252b5132 RH |
2902 | |
2903 | fprintf (stdout, "%s: template ", line); | |
2904 | pte (&x->tm); | |
09f131f2 JH |
2905 | fprintf (stdout, " address: base %s index %s scale %x\n", |
2906 | x->base_reg ? x->base_reg->reg_name : "none", | |
2907 | x->index_reg ? x->index_reg->reg_name : "none", | |
2908 | x->log2_scale_factor); | |
2909 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 2910 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
2911 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
2912 | x->sib.base, x->sib.index, x->sib.scale); | |
2913 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
161a04f6 L |
2914 | (x->rex & REX_W) != 0, |
2915 | (x->rex & REX_R) != 0, | |
2916 | (x->rex & REX_X) != 0, | |
2917 | (x->rex & REX_B) != 0); | |
09137c09 | 2918 | for (j = 0; j < x->operands; j++) |
252b5132 | 2919 | { |
09137c09 SP |
2920 | fprintf (stdout, " #%d: ", j + 1); |
2921 | pt (x->types[j]); | |
252b5132 | 2922 | fprintf (stdout, "\n"); |
dc821c5f | 2923 | if (x->types[j].bitfield.reg |
09137c09 | 2924 | || x->types[j].bitfield.regmmx |
1b54b8d7 | 2925 | || x->types[j].bitfield.regsimd |
09137c09 SP |
2926 | || x->types[j].bitfield.sreg2 |
2927 | || x->types[j].bitfield.sreg3 | |
2928 | || x->types[j].bitfield.control | |
2929 | || x->types[j].bitfield.debug | |
2930 | || x->types[j].bitfield.test) | |
2931 | fprintf (stdout, "%s\n", x->op[j].regs->reg_name); | |
2932 | if (operand_type_check (x->types[j], imm)) | |
2933 | pe (x->op[j].imms); | |
2934 | if (operand_type_check (x->types[j], disp)) | |
2935 | pe (x->op[j].disps); | |
252b5132 RH |
2936 | } |
2937 | } | |
2938 | ||
2939 | static void | |
d3ce72d0 | 2940 | pte (insn_template *t) |
252b5132 | 2941 | { |
09137c09 | 2942 | unsigned int j; |
252b5132 | 2943 | fprintf (stdout, " %d operands ", t->operands); |
47926f60 | 2944 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
2945 | if (t->extension_opcode != None) |
2946 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
40fb9820 | 2947 | if (t->opcode_modifier.d) |
252b5132 | 2948 | fprintf (stdout, "D"); |
40fb9820 | 2949 | if (t->opcode_modifier.w) |
252b5132 RH |
2950 | fprintf (stdout, "W"); |
2951 | fprintf (stdout, "\n"); | |
09137c09 | 2952 | for (j = 0; j < t->operands; j++) |
252b5132 | 2953 | { |
09137c09 SP |
2954 | fprintf (stdout, " #%d type ", j + 1); |
2955 | pt (t->operand_types[j]); | |
252b5132 RH |
2956 | fprintf (stdout, "\n"); |
2957 | } | |
2958 | } | |
2959 | ||
2960 | static void | |
e3bb37b5 | 2961 | pe (expressionS *e) |
252b5132 | 2962 | { |
24eab124 | 2963 | fprintf (stdout, " operation %d\n", e->X_op); |
b77ad1d4 AM |
2964 | fprintf (stdout, " add_number %ld (%lx)\n", |
2965 | (long) e->X_add_number, (long) e->X_add_number); | |
252b5132 RH |
2966 | if (e->X_add_symbol) |
2967 | { | |
2968 | fprintf (stdout, " add_symbol "); | |
2969 | ps (e->X_add_symbol); | |
2970 | fprintf (stdout, "\n"); | |
2971 | } | |
2972 | if (e->X_op_symbol) | |
2973 | { | |
2974 | fprintf (stdout, " op_symbol "); | |
2975 | ps (e->X_op_symbol); | |
2976 | fprintf (stdout, "\n"); | |
2977 | } | |
2978 | } | |
2979 | ||
2980 | static void | |
e3bb37b5 | 2981 | ps (symbolS *s) |
252b5132 RH |
2982 | { |
2983 | fprintf (stdout, "%s type %s%s", | |
2984 | S_GET_NAME (s), | |
2985 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
2986 | segment_name (S_GET_SEGMENT (s))); | |
2987 | } | |
2988 | ||
7b81dfbb | 2989 | static struct type_name |
252b5132 | 2990 | { |
40fb9820 L |
2991 | i386_operand_type mask; |
2992 | const char *name; | |
252b5132 | 2993 | } |
7b81dfbb | 2994 | const type_names[] = |
252b5132 | 2995 | { |
40fb9820 L |
2996 | { OPERAND_TYPE_REG8, "r8" }, |
2997 | { OPERAND_TYPE_REG16, "r16" }, | |
2998 | { OPERAND_TYPE_REG32, "r32" }, | |
2999 | { OPERAND_TYPE_REG64, "r64" }, | |
3000 | { OPERAND_TYPE_IMM8, "i8" }, | |
3001 | { OPERAND_TYPE_IMM8, "i8s" }, | |
3002 | { OPERAND_TYPE_IMM16, "i16" }, | |
3003 | { OPERAND_TYPE_IMM32, "i32" }, | |
3004 | { OPERAND_TYPE_IMM32S, "i32s" }, | |
3005 | { OPERAND_TYPE_IMM64, "i64" }, | |
3006 | { OPERAND_TYPE_IMM1, "i1" }, | |
3007 | { OPERAND_TYPE_BASEINDEX, "BaseIndex" }, | |
3008 | { OPERAND_TYPE_DISP8, "d8" }, | |
3009 | { OPERAND_TYPE_DISP16, "d16" }, | |
3010 | { OPERAND_TYPE_DISP32, "d32" }, | |
3011 | { OPERAND_TYPE_DISP32S, "d32s" }, | |
3012 | { OPERAND_TYPE_DISP64, "d64" }, | |
3013 | { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" }, | |
3014 | { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" }, | |
3015 | { OPERAND_TYPE_CONTROL, "control reg" }, | |
3016 | { OPERAND_TYPE_TEST, "test reg" }, | |
3017 | { OPERAND_TYPE_DEBUG, "debug reg" }, | |
3018 | { OPERAND_TYPE_FLOATREG, "FReg" }, | |
3019 | { OPERAND_TYPE_FLOATACC, "FAcc" }, | |
3020 | { OPERAND_TYPE_SREG2, "SReg2" }, | |
3021 | { OPERAND_TYPE_SREG3, "SReg3" }, | |
3022 | { OPERAND_TYPE_ACC, "Acc" }, | |
3023 | { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" }, | |
3024 | { OPERAND_TYPE_REGMMX, "rMMX" }, | |
3025 | { OPERAND_TYPE_REGXMM, "rXMM" }, | |
0349dc08 | 3026 | { OPERAND_TYPE_REGYMM, "rYMM" }, |
43234a1e L |
3027 | { OPERAND_TYPE_REGZMM, "rZMM" }, |
3028 | { OPERAND_TYPE_REGMASK, "Mask reg" }, | |
40fb9820 | 3029 | { OPERAND_TYPE_ESSEG, "es" }, |
252b5132 RH |
3030 | }; |
3031 | ||
3032 | static void | |
40fb9820 | 3033 | pt (i386_operand_type t) |
252b5132 | 3034 | { |
40fb9820 | 3035 | unsigned int j; |
c6fb90c8 | 3036 | i386_operand_type a; |
252b5132 | 3037 | |
40fb9820 | 3038 | for (j = 0; j < ARRAY_SIZE (type_names); j++) |
c6fb90c8 L |
3039 | { |
3040 | a = operand_type_and (t, type_names[j].mask); | |
0349dc08 | 3041 | if (!operand_type_all_zero (&a)) |
c6fb90c8 L |
3042 | fprintf (stdout, "%s, ", type_names[j].name); |
3043 | } | |
252b5132 RH |
3044 | fflush (stdout); |
3045 | } | |
3046 | ||
3047 | #endif /* DEBUG386 */ | |
3048 | \f | |
252b5132 | 3049 | static bfd_reloc_code_real_type |
3956db08 | 3050 | reloc (unsigned int size, |
64e74474 AM |
3051 | int pcrel, |
3052 | int sign, | |
3053 | bfd_reloc_code_real_type other) | |
252b5132 | 3054 | { |
47926f60 | 3055 | if (other != NO_RELOC) |
3956db08 | 3056 | { |
91d6fa6a | 3057 | reloc_howto_type *rel; |
3956db08 JB |
3058 | |
3059 | if (size == 8) | |
3060 | switch (other) | |
3061 | { | |
64e74474 AM |
3062 | case BFD_RELOC_X86_64_GOT32: |
3063 | return BFD_RELOC_X86_64_GOT64; | |
3064 | break; | |
553d1284 L |
3065 | case BFD_RELOC_X86_64_GOTPLT64: |
3066 | return BFD_RELOC_X86_64_GOTPLT64; | |
3067 | break; | |
64e74474 AM |
3068 | case BFD_RELOC_X86_64_PLTOFF64: |
3069 | return BFD_RELOC_X86_64_PLTOFF64; | |
3070 | break; | |
3071 | case BFD_RELOC_X86_64_GOTPC32: | |
3072 | other = BFD_RELOC_X86_64_GOTPC64; | |
3073 | break; | |
3074 | case BFD_RELOC_X86_64_GOTPCREL: | |
3075 | other = BFD_RELOC_X86_64_GOTPCREL64; | |
3076 | break; | |
3077 | case BFD_RELOC_X86_64_TPOFF32: | |
3078 | other = BFD_RELOC_X86_64_TPOFF64; | |
3079 | break; | |
3080 | case BFD_RELOC_X86_64_DTPOFF32: | |
3081 | other = BFD_RELOC_X86_64_DTPOFF64; | |
3082 | break; | |
3083 | default: | |
3084 | break; | |
3956db08 | 3085 | } |
e05278af | 3086 | |
8ce3d284 | 3087 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
3088 | if (other == BFD_RELOC_SIZE32) |
3089 | { | |
3090 | if (size == 8) | |
1ab668bf | 3091 | other = BFD_RELOC_SIZE64; |
8fd4256d | 3092 | if (pcrel) |
1ab668bf AM |
3093 | { |
3094 | as_bad (_("there are no pc-relative size relocations")); | |
3095 | return NO_RELOC; | |
3096 | } | |
8fd4256d | 3097 | } |
8ce3d284 | 3098 | #endif |
8fd4256d | 3099 | |
e05278af | 3100 | /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ |
f2d8a97c | 3101 | if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc)) |
e05278af JB |
3102 | sign = -1; |
3103 | ||
91d6fa6a NC |
3104 | rel = bfd_reloc_type_lookup (stdoutput, other); |
3105 | if (!rel) | |
3956db08 | 3106 | as_bad (_("unknown relocation (%u)"), other); |
91d6fa6a | 3107 | else if (size != bfd_get_reloc_size (rel)) |
3956db08 | 3108 | as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), |
91d6fa6a | 3109 | bfd_get_reloc_size (rel), |
3956db08 | 3110 | size); |
91d6fa6a | 3111 | else if (pcrel && !rel->pc_relative) |
3956db08 | 3112 | as_bad (_("non-pc-relative relocation for pc-relative field")); |
91d6fa6a | 3113 | else if ((rel->complain_on_overflow == complain_overflow_signed |
3956db08 | 3114 | && !sign) |
91d6fa6a | 3115 | || (rel->complain_on_overflow == complain_overflow_unsigned |
64e74474 | 3116 | && sign > 0)) |
3956db08 JB |
3117 | as_bad (_("relocated field and relocation type differ in signedness")); |
3118 | else | |
3119 | return other; | |
3120 | return NO_RELOC; | |
3121 | } | |
252b5132 RH |
3122 | |
3123 | if (pcrel) | |
3124 | { | |
3e73aa7c | 3125 | if (!sign) |
3956db08 | 3126 | as_bad (_("there are no unsigned pc-relative relocations")); |
252b5132 RH |
3127 | switch (size) |
3128 | { | |
3129 | case 1: return BFD_RELOC_8_PCREL; | |
3130 | case 2: return BFD_RELOC_16_PCREL; | |
d258b828 | 3131 | case 4: return BFD_RELOC_32_PCREL; |
d6ab8113 | 3132 | case 8: return BFD_RELOC_64_PCREL; |
252b5132 | 3133 | } |
3956db08 | 3134 | as_bad (_("cannot do %u byte pc-relative relocation"), size); |
252b5132 RH |
3135 | } |
3136 | else | |
3137 | { | |
3956db08 | 3138 | if (sign > 0) |
e5cb08ac | 3139 | switch (size) |
3e73aa7c JH |
3140 | { |
3141 | case 4: return BFD_RELOC_X86_64_32S; | |
3142 | } | |
3143 | else | |
3144 | switch (size) | |
3145 | { | |
3146 | case 1: return BFD_RELOC_8; | |
3147 | case 2: return BFD_RELOC_16; | |
3148 | case 4: return BFD_RELOC_32; | |
3149 | case 8: return BFD_RELOC_64; | |
3150 | } | |
3956db08 JB |
3151 | as_bad (_("cannot do %s %u byte relocation"), |
3152 | sign > 0 ? "signed" : "unsigned", size); | |
252b5132 RH |
3153 | } |
3154 | ||
0cc9e1d3 | 3155 | return NO_RELOC; |
252b5132 RH |
3156 | } |
3157 | ||
47926f60 KH |
3158 | /* Here we decide which fixups can be adjusted to make them relative to |
3159 | the beginning of the section instead of the symbol. Basically we need | |
3160 | to make sure that the dynamic relocations are done correctly, so in | |
3161 | some cases we force the original symbol to be used. */ | |
3162 | ||
252b5132 | 3163 | int |
e3bb37b5 | 3164 | tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) |
252b5132 | 3165 | { |
6d249963 | 3166 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 3167 | if (!IS_ELF) |
31312f95 AM |
3168 | return 1; |
3169 | ||
a161fe53 AM |
3170 | /* Don't adjust pc-relative references to merge sections in 64-bit |
3171 | mode. */ | |
3172 | if (use_rela_relocations | |
3173 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 | |
3174 | && fixP->fx_pcrel) | |
252b5132 | 3175 | return 0; |
31312f95 | 3176 | |
8d01d9a9 AJ |
3177 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
3178 | and changed later by validate_fix. */ | |
3179 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol | |
3180 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) | |
3181 | return 0; | |
3182 | ||
8fd4256d L |
3183 | /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol |
3184 | for size relocations. */ | |
3185 | if (fixP->fx_r_type == BFD_RELOC_SIZE32 | |
3186 | || fixP->fx_r_type == BFD_RELOC_SIZE64 | |
3187 | || fixP->fx_r_type == BFD_RELOC_386_GOTOFF | |
252b5132 RH |
3188 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 |
3189 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 | |
02a86693 | 3190 | || fixP->fx_r_type == BFD_RELOC_386_GOT32X |
13ae64f3 JJ |
3191 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
3192 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM | |
3193 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 | |
3194 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 | |
37e55690 JJ |
3195 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
3196 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE | |
13ae64f3 JJ |
3197 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
3198 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE | |
67a4f2b7 AO |
3199 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC |
3200 | || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL | |
3e73aa7c JH |
3201 | || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 |
3202 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 | |
80b3ee89 | 3203 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
56ceb5b5 L |
3204 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX |
3205 | || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX | |
bffbf940 JJ |
3206 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
3207 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD | |
3208 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 | |
d6ab8113 | 3209 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 |
bffbf940 JJ |
3210 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF |
3211 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 | |
d6ab8113 JB |
3212 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 |
3213 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 | |
67a4f2b7 AO |
3214 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
3215 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL | |
252b5132 RH |
3216 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
3217 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
3218 | return 0; | |
31312f95 | 3219 | #endif |
252b5132 RH |
3220 | return 1; |
3221 | } | |
252b5132 | 3222 | |
b4cac588 | 3223 | static int |
e3bb37b5 | 3224 | intel_float_operand (const char *mnemonic) |
252b5132 | 3225 | { |
9306ca4a JB |
3226 | /* Note that the value returned is meaningful only for opcodes with (memory) |
3227 | operands, hence the code here is free to improperly handle opcodes that | |
3228 | have no operands (for better performance and smaller code). */ | |
3229 | ||
3230 | if (mnemonic[0] != 'f') | |
3231 | return 0; /* non-math */ | |
3232 | ||
3233 | switch (mnemonic[1]) | |
3234 | { | |
3235 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and | |
3236 | the fs segment override prefix not currently handled because no | |
3237 | call path can make opcodes without operands get here */ | |
3238 | case 'i': | |
3239 | return 2 /* integer op */; | |
3240 | case 'l': | |
3241 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) | |
3242 | return 3; /* fldcw/fldenv */ | |
3243 | break; | |
3244 | case 'n': | |
3245 | if (mnemonic[2] != 'o' /* fnop */) | |
3246 | return 3; /* non-waiting control op */ | |
3247 | break; | |
3248 | case 'r': | |
3249 | if (mnemonic[2] == 's') | |
3250 | return 3; /* frstor/frstpm */ | |
3251 | break; | |
3252 | case 's': | |
3253 | if (mnemonic[2] == 'a') | |
3254 | return 3; /* fsave */ | |
3255 | if (mnemonic[2] == 't') | |
3256 | { | |
3257 | switch (mnemonic[3]) | |
3258 | { | |
3259 | case 'c': /* fstcw */ | |
3260 | case 'd': /* fstdw */ | |
3261 | case 'e': /* fstenv */ | |
3262 | case 's': /* fsts[gw] */ | |
3263 | return 3; | |
3264 | } | |
3265 | } | |
3266 | break; | |
3267 | case 'x': | |
3268 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') | |
3269 | return 0; /* fxsave/fxrstor are not really math ops */ | |
3270 | break; | |
3271 | } | |
252b5132 | 3272 | |
9306ca4a | 3273 | return 1; |
252b5132 RH |
3274 | } |
3275 | ||
c0f3af97 L |
3276 | /* Build the VEX prefix. */ |
3277 | ||
3278 | static void | |
d3ce72d0 | 3279 | build_vex_prefix (const insn_template *t) |
c0f3af97 L |
3280 | { |
3281 | unsigned int register_specifier; | |
3282 | unsigned int implied_prefix; | |
3283 | unsigned int vector_length; | |
3284 | ||
3285 | /* Check register specifier. */ | |
3286 | if (i.vex.register_specifier) | |
43234a1e L |
3287 | { |
3288 | register_specifier = | |
3289 | ~register_number (i.vex.register_specifier) & 0xf; | |
3290 | gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0); | |
3291 | } | |
c0f3af97 L |
3292 | else |
3293 | register_specifier = 0xf; | |
3294 | ||
33eaf5de | 3295 | /* Use 2-byte VEX prefix by swapping destination and source |
fa99fab2 | 3296 | operand. */ |
86fa6981 L |
3297 | if (i.vec_encoding != vex_encoding_vex3 |
3298 | && i.dir_encoding == dir_encoding_default | |
fa99fab2 | 3299 | && i.operands == i.reg_operands |
7f399153 | 3300 | && i.tm.opcode_modifier.vexopcode == VEX0F |
86fa6981 | 3301 | && i.tm.opcode_modifier.load |
fa99fab2 L |
3302 | && i.rex == REX_B) |
3303 | { | |
3304 | unsigned int xchg = i.operands - 1; | |
3305 | union i386_op temp_op; | |
3306 | i386_operand_type temp_type; | |
3307 | ||
3308 | temp_type = i.types[xchg]; | |
3309 | i.types[xchg] = i.types[0]; | |
3310 | i.types[0] = temp_type; | |
3311 | temp_op = i.op[xchg]; | |
3312 | i.op[xchg] = i.op[0]; | |
3313 | i.op[0] = temp_op; | |
3314 | ||
9c2799c2 | 3315 | gas_assert (i.rm.mode == 3); |
fa99fab2 L |
3316 | |
3317 | i.rex = REX_R; | |
3318 | xchg = i.rm.regmem; | |
3319 | i.rm.regmem = i.rm.reg; | |
3320 | i.rm.reg = xchg; | |
3321 | ||
3322 | /* Use the next insn. */ | |
3323 | i.tm = t[1]; | |
3324 | } | |
3325 | ||
539f890d L |
3326 | if (i.tm.opcode_modifier.vex == VEXScalar) |
3327 | vector_length = avxscalar; | |
10c17abd JB |
3328 | else if (i.tm.opcode_modifier.vex == VEX256) |
3329 | vector_length = 1; | |
539f890d | 3330 | else |
10c17abd JB |
3331 | { |
3332 | unsigned int op; | |
3333 | ||
3334 | vector_length = 0; | |
3335 | for (op = 0; op < t->operands; ++op) | |
3336 | if (t->operand_types[op].bitfield.xmmword | |
3337 | && t->operand_types[op].bitfield.ymmword | |
3338 | && i.types[op].bitfield.ymmword) | |
3339 | { | |
3340 | vector_length = 1; | |
3341 | break; | |
3342 | } | |
3343 | } | |
c0f3af97 L |
3344 | |
3345 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
3346 | { | |
3347 | case 0: | |
3348 | implied_prefix = 0; | |
3349 | break; | |
3350 | case DATA_PREFIX_OPCODE: | |
3351 | implied_prefix = 1; | |
3352 | break; | |
3353 | case REPE_PREFIX_OPCODE: | |
3354 | implied_prefix = 2; | |
3355 | break; | |
3356 | case REPNE_PREFIX_OPCODE: | |
3357 | implied_prefix = 3; | |
3358 | break; | |
3359 | default: | |
3360 | abort (); | |
3361 | } | |
3362 | ||
3363 | /* Use 2-byte VEX prefix if possible. */ | |
86fa6981 L |
3364 | if (i.vec_encoding != vex_encoding_vex3 |
3365 | && i.tm.opcode_modifier.vexopcode == VEX0F | |
04251de0 | 3366 | && i.tm.opcode_modifier.vexw != VEXW1 |
c0f3af97 L |
3367 | && (i.rex & (REX_W | REX_X | REX_B)) == 0) |
3368 | { | |
3369 | /* 2-byte VEX prefix. */ | |
3370 | unsigned int r; | |
3371 | ||
3372 | i.vex.length = 2; | |
3373 | i.vex.bytes[0] = 0xc5; | |
3374 | ||
3375 | /* Check the REX.R bit. */ | |
3376 | r = (i.rex & REX_R) ? 0 : 1; | |
3377 | i.vex.bytes[1] = (r << 7 | |
3378 | | register_specifier << 3 | |
3379 | | vector_length << 2 | |
3380 | | implied_prefix); | |
3381 | } | |
3382 | else | |
3383 | { | |
3384 | /* 3-byte VEX prefix. */ | |
3385 | unsigned int m, w; | |
3386 | ||
f88c9eb0 | 3387 | i.vex.length = 3; |
f88c9eb0 | 3388 | |
7f399153 | 3389 | switch (i.tm.opcode_modifier.vexopcode) |
5dd85c99 | 3390 | { |
7f399153 L |
3391 | case VEX0F: |
3392 | m = 0x1; | |
80de6e00 | 3393 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3394 | break; |
3395 | case VEX0F38: | |
3396 | m = 0x2; | |
80de6e00 | 3397 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3398 | break; |
3399 | case VEX0F3A: | |
3400 | m = 0x3; | |
80de6e00 | 3401 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3402 | break; |
3403 | case XOP08: | |
5dd85c99 SP |
3404 | m = 0x8; |
3405 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3406 | break; |
3407 | case XOP09: | |
f88c9eb0 SP |
3408 | m = 0x9; |
3409 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3410 | break; |
3411 | case XOP0A: | |
f88c9eb0 SP |
3412 | m = 0xa; |
3413 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3414 | break; |
3415 | default: | |
3416 | abort (); | |
f88c9eb0 | 3417 | } |
c0f3af97 | 3418 | |
c0f3af97 L |
3419 | /* The high 3 bits of the second VEX byte are 1's compliment |
3420 | of RXB bits from REX. */ | |
3421 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
3422 | ||
3423 | /* Check the REX.W bit. */ | |
3424 | w = (i.rex & REX_W) ? 1 : 0; | |
b28d1bda IT |
3425 | if (i.tm.opcode_modifier.vexw == VEXW1) |
3426 | w = 1; | |
c0f3af97 L |
3427 | |
3428 | i.vex.bytes[2] = (w << 7 | |
3429 | | register_specifier << 3 | |
3430 | | vector_length << 2 | |
3431 | | implied_prefix); | |
3432 | } | |
3433 | } | |
3434 | ||
43234a1e L |
3435 | /* Build the EVEX prefix. */ |
3436 | ||
3437 | static void | |
3438 | build_evex_prefix (void) | |
3439 | { | |
3440 | unsigned int register_specifier; | |
3441 | unsigned int implied_prefix; | |
3442 | unsigned int m, w; | |
3443 | rex_byte vrex_used = 0; | |
3444 | ||
3445 | /* Check register specifier. */ | |
3446 | if (i.vex.register_specifier) | |
3447 | { | |
3448 | gas_assert ((i.vrex & REX_X) == 0); | |
3449 | ||
3450 | register_specifier = i.vex.register_specifier->reg_num; | |
3451 | if ((i.vex.register_specifier->reg_flags & RegRex)) | |
3452 | register_specifier += 8; | |
3453 | /* The upper 16 registers are encoded in the fourth byte of the | |
3454 | EVEX prefix. */ | |
3455 | if (!(i.vex.register_specifier->reg_flags & RegVRex)) | |
3456 | i.vex.bytes[3] = 0x8; | |
3457 | register_specifier = ~register_specifier & 0xf; | |
3458 | } | |
3459 | else | |
3460 | { | |
3461 | register_specifier = 0xf; | |
3462 | ||
3463 | /* Encode upper 16 vector index register in the fourth byte of | |
3464 | the EVEX prefix. */ | |
3465 | if (!(i.vrex & REX_X)) | |
3466 | i.vex.bytes[3] = 0x8; | |
3467 | else | |
3468 | vrex_used |= REX_X; | |
3469 | } | |
3470 | ||
3471 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
3472 | { | |
3473 | case 0: | |
3474 | implied_prefix = 0; | |
3475 | break; | |
3476 | case DATA_PREFIX_OPCODE: | |
3477 | implied_prefix = 1; | |
3478 | break; | |
3479 | case REPE_PREFIX_OPCODE: | |
3480 | implied_prefix = 2; | |
3481 | break; | |
3482 | case REPNE_PREFIX_OPCODE: | |
3483 | implied_prefix = 3; | |
3484 | break; | |
3485 | default: | |
3486 | abort (); | |
3487 | } | |
3488 | ||
3489 | /* 4 byte EVEX prefix. */ | |
3490 | i.vex.length = 4; | |
3491 | i.vex.bytes[0] = 0x62; | |
3492 | ||
3493 | /* mmmm bits. */ | |
3494 | switch (i.tm.opcode_modifier.vexopcode) | |
3495 | { | |
3496 | case VEX0F: | |
3497 | m = 1; | |
3498 | break; | |
3499 | case VEX0F38: | |
3500 | m = 2; | |
3501 | break; | |
3502 | case VEX0F3A: | |
3503 | m = 3; | |
3504 | break; | |
3505 | default: | |
3506 | abort (); | |
3507 | break; | |
3508 | } | |
3509 | ||
3510 | /* The high 3 bits of the second EVEX byte are 1's compliment of RXB | |
3511 | bits from REX. */ | |
3512 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
3513 | ||
3514 | /* The fifth bit of the second EVEX byte is 1's compliment of the | |
3515 | REX_R bit in VREX. */ | |
3516 | if (!(i.vrex & REX_R)) | |
3517 | i.vex.bytes[1] |= 0x10; | |
3518 | else | |
3519 | vrex_used |= REX_R; | |
3520 | ||
3521 | if ((i.reg_operands + i.imm_operands) == i.operands) | |
3522 | { | |
3523 | /* When all operands are registers, the REX_X bit in REX is not | |
3524 | used. We reuse it to encode the upper 16 registers, which is | |
3525 | indicated by the REX_B bit in VREX. The REX_X bit is encoded | |
3526 | as 1's compliment. */ | |
3527 | if ((i.vrex & REX_B)) | |
3528 | { | |
3529 | vrex_used |= REX_B; | |
3530 | i.vex.bytes[1] &= ~0x40; | |
3531 | } | |
3532 | } | |
3533 | ||
3534 | /* EVEX instructions shouldn't need the REX prefix. */ | |
3535 | i.vrex &= ~vrex_used; | |
3536 | gas_assert (i.vrex == 0); | |
3537 | ||
3538 | /* Check the REX.W bit. */ | |
3539 | w = (i.rex & REX_W) ? 1 : 0; | |
3540 | if (i.tm.opcode_modifier.vexw) | |
3541 | { | |
3542 | if (i.tm.opcode_modifier.vexw == VEXW1) | |
3543 | w = 1; | |
3544 | } | |
3545 | /* If w is not set it means we are dealing with WIG instruction. */ | |
3546 | else if (!w) | |
3547 | { | |
3548 | if (evexwig == evexw1) | |
3549 | w = 1; | |
3550 | } | |
3551 | ||
3552 | /* Encode the U bit. */ | |
3553 | implied_prefix |= 0x4; | |
3554 | ||
3555 | /* The third byte of the EVEX prefix. */ | |
3556 | i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix); | |
3557 | ||
3558 | /* The fourth byte of the EVEX prefix. */ | |
3559 | /* The zeroing-masking bit. */ | |
3560 | if (i.mask && i.mask->zeroing) | |
3561 | i.vex.bytes[3] |= 0x80; | |
3562 | ||
3563 | /* Don't always set the broadcast bit if there is no RC. */ | |
3564 | if (!i.rounding) | |
3565 | { | |
3566 | /* Encode the vector length. */ | |
3567 | unsigned int vec_length; | |
3568 | ||
3569 | switch (i.tm.opcode_modifier.evex) | |
3570 | { | |
3571 | case EVEXLIG: /* LL' is ignored */ | |
3572 | vec_length = evexlig << 5; | |
3573 | break; | |
3574 | case EVEX128: | |
3575 | vec_length = 0 << 5; | |
3576 | break; | |
3577 | case EVEX256: | |
3578 | vec_length = 1 << 5; | |
3579 | break; | |
3580 | case EVEX512: | |
3581 | vec_length = 2 << 5; | |
3582 | break; | |
3583 | default: | |
3584 | abort (); | |
3585 | break; | |
3586 | } | |
3587 | i.vex.bytes[3] |= vec_length; | |
3588 | /* Encode the broadcast bit. */ | |
3589 | if (i.broadcast) | |
3590 | i.vex.bytes[3] |= 0x10; | |
3591 | } | |
3592 | else | |
3593 | { | |
3594 | if (i.rounding->type != saeonly) | |
3595 | i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5); | |
3596 | else | |
d3d3c6db | 3597 | i.vex.bytes[3] |= 0x10 | (evexrcig << 5); |
43234a1e L |
3598 | } |
3599 | ||
3600 | if (i.mask && i.mask->mask) | |
3601 | i.vex.bytes[3] |= i.mask->mask->reg_num; | |
3602 | } | |
3603 | ||
65da13b5 L |
3604 | static void |
3605 | process_immext (void) | |
3606 | { | |
3607 | expressionS *exp; | |
3608 | ||
4c692bc7 JB |
3609 | if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme) |
3610 | && i.operands > 0) | |
65da13b5 | 3611 | { |
4c692bc7 JB |
3612 | /* MONITOR/MWAIT as well as SVME instructions have fixed operands |
3613 | with an opcode suffix which is coded in the same place as an | |
3614 | 8-bit immediate field would be. | |
3615 | Here we check those operands and remove them afterwards. */ | |
65da13b5 L |
3616 | unsigned int x; |
3617 | ||
3618 | for (x = 0; x < i.operands; x++) | |
4c692bc7 | 3619 | if (register_number (i.op[x].regs) != x) |
65da13b5 | 3620 | as_bad (_("can't use register '%s%s' as operand %d in '%s'."), |
1fed0ba1 L |
3621 | register_prefix, i.op[x].regs->reg_name, x + 1, |
3622 | i.tm.name); | |
3623 | ||
3624 | i.operands = 0; | |
65da13b5 L |
3625 | } |
3626 | ||
9916071f AP |
3627 | if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0) |
3628 | { | |
3629 | /* MONITORX/MWAITX instructions have fixed operands with an opcode | |
3630 | suffix which is coded in the same place as an 8-bit immediate | |
3631 | field would be. | |
3632 | Here we check those operands and remove them afterwards. */ | |
3633 | unsigned int x; | |
3634 | ||
3635 | if (i.operands != 3) | |
3636 | abort(); | |
3637 | ||
3638 | for (x = 0; x < 2; x++) | |
3639 | if (register_number (i.op[x].regs) != x) | |
3640 | goto bad_register_operand; | |
3641 | ||
3642 | /* Check for third operand for mwaitx/monitorx insn. */ | |
3643 | if (register_number (i.op[x].regs) | |
3644 | != (x + (i.tm.extension_opcode == 0xfb))) | |
3645 | { | |
3646 | bad_register_operand: | |
3647 | as_bad (_("can't use register '%s%s' as operand %d in '%s'."), | |
3648 | register_prefix, i.op[x].regs->reg_name, x+1, | |
3649 | i.tm.name); | |
3650 | } | |
3651 | ||
3652 | i.operands = 0; | |
3653 | } | |
3654 | ||
c0f3af97 | 3655 | /* These AMD 3DNow! and SSE2 instructions have an opcode suffix |
65da13b5 L |
3656 | which is coded in the same place as an 8-bit immediate field |
3657 | would be. Here we fake an 8-bit immediate operand from the | |
3658 | opcode suffix stored in tm.extension_opcode. | |
3659 | ||
c1e679ec | 3660 | AVX instructions also use this encoding, for some of |
c0f3af97 | 3661 | 3 argument instructions. */ |
65da13b5 | 3662 | |
43234a1e | 3663 | gas_assert (i.imm_operands <= 1 |
7ab9ffdd | 3664 | && (i.operands <= 2 |
43234a1e L |
3665 | || ((i.tm.opcode_modifier.vex |
3666 | || i.tm.opcode_modifier.evex) | |
7ab9ffdd | 3667 | && i.operands <= 4))); |
65da13b5 L |
3668 | |
3669 | exp = &im_expressions[i.imm_operands++]; | |
3670 | i.op[i.operands].imms = exp; | |
3671 | i.types[i.operands] = imm8; | |
3672 | i.operands++; | |
3673 | exp->X_op = O_constant; | |
3674 | exp->X_add_number = i.tm.extension_opcode; | |
3675 | i.tm.extension_opcode = None; | |
3676 | } | |
3677 | ||
42164a71 L |
3678 | |
3679 | static int | |
3680 | check_hle (void) | |
3681 | { | |
3682 | switch (i.tm.opcode_modifier.hleprefixok) | |
3683 | { | |
3684 | default: | |
3685 | abort (); | |
82c2def5 | 3686 | case HLEPrefixNone: |
165de32a L |
3687 | as_bad (_("invalid instruction `%s' after `%s'"), |
3688 | i.tm.name, i.hle_prefix); | |
42164a71 | 3689 | return 0; |
82c2def5 | 3690 | case HLEPrefixLock: |
42164a71 L |
3691 | if (i.prefix[LOCK_PREFIX]) |
3692 | return 1; | |
165de32a | 3693 | as_bad (_("missing `lock' with `%s'"), i.hle_prefix); |
42164a71 | 3694 | return 0; |
82c2def5 | 3695 | case HLEPrefixAny: |
42164a71 | 3696 | return 1; |
82c2def5 | 3697 | case HLEPrefixRelease: |
42164a71 L |
3698 | if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE) |
3699 | { | |
3700 | as_bad (_("instruction `%s' after `xacquire' not allowed"), | |
3701 | i.tm.name); | |
3702 | return 0; | |
3703 | } | |
3704 | if (i.mem_operands == 0 | |
3705 | || !operand_type_check (i.types[i.operands - 1], anymem)) | |
3706 | { | |
3707 | as_bad (_("memory destination needed for instruction `%s'" | |
3708 | " after `xrelease'"), i.tm.name); | |
3709 | return 0; | |
3710 | } | |
3711 | return 1; | |
3712 | } | |
3713 | } | |
3714 | ||
252b5132 RH |
3715 | /* This is the guts of the machine-dependent assembler. LINE points to a |
3716 | machine dependent instruction. This function is supposed to emit | |
3717 | the frags/bytes it assembles to. */ | |
3718 | ||
3719 | void | |
65da13b5 | 3720 | md_assemble (char *line) |
252b5132 | 3721 | { |
40fb9820 | 3722 | unsigned int j; |
83b16ac6 | 3723 | char mnemonic[MAX_MNEM_SIZE], mnem_suffix; |
d3ce72d0 | 3724 | const insn_template *t; |
252b5132 | 3725 | |
47926f60 | 3726 | /* Initialize globals. */ |
252b5132 RH |
3727 | memset (&i, '\0', sizeof (i)); |
3728 | for (j = 0; j < MAX_OPERANDS; j++) | |
1ae12ab7 | 3729 | i.reloc[j] = NO_RELOC; |
252b5132 RH |
3730 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
3731 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 3732 | save_stack_p = save_stack; |
252b5132 RH |
3733 | |
3734 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
3735 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 3736 | start of a (possibly prefixed) mnemonic. */ |
252b5132 | 3737 | |
29b0f896 AM |
3738 | line = parse_insn (line, mnemonic); |
3739 | if (line == NULL) | |
3740 | return; | |
83b16ac6 | 3741 | mnem_suffix = i.suffix; |
252b5132 | 3742 | |
29b0f896 | 3743 | line = parse_operands (line, mnemonic); |
ee86248c | 3744 | this_operand = -1; |
8325cc63 JB |
3745 | xfree (i.memop1_string); |
3746 | i.memop1_string = NULL; | |
29b0f896 AM |
3747 | if (line == NULL) |
3748 | return; | |
252b5132 | 3749 | |
29b0f896 AM |
3750 | /* Now we've parsed the mnemonic into a set of templates, and have the |
3751 | operands at hand. */ | |
3752 | ||
3753 | /* All intel opcodes have reversed operands except for "bound" and | |
3754 | "enter". We also don't reverse intersegment "jmp" and "call" | |
3755 | instructions with 2 immediate operands so that the immediate segment | |
050dfa73 | 3756 | precedes the offset, as it does when in AT&T mode. */ |
4d456e3d L |
3757 | if (intel_syntax |
3758 | && i.operands > 1 | |
29b0f896 | 3759 | && (strcmp (mnemonic, "bound") != 0) |
30123838 | 3760 | && (strcmp (mnemonic, "invlpga") != 0) |
40fb9820 L |
3761 | && !(operand_type_check (i.types[0], imm) |
3762 | && operand_type_check (i.types[1], imm))) | |
29b0f896 AM |
3763 | swap_operands (); |
3764 | ||
ec56d5c0 JB |
3765 | /* The order of the immediates should be reversed |
3766 | for 2 immediates extrq and insertq instructions */ | |
3767 | if (i.imm_operands == 2 | |
3768 | && (strcmp (mnemonic, "extrq") == 0 | |
3769 | || strcmp (mnemonic, "insertq") == 0)) | |
3770 | swap_2_operands (0, 1); | |
3771 | ||
29b0f896 AM |
3772 | if (i.imm_operands) |
3773 | optimize_imm (); | |
3774 | ||
b300c311 L |
3775 | /* Don't optimize displacement for movabs since it only takes 64bit |
3776 | displacement. */ | |
3777 | if (i.disp_operands | |
a501d77e | 3778 | && i.disp_encoding != disp_encoding_32bit |
862be3fb L |
3779 | && (flag_code != CODE_64BIT |
3780 | || strcmp (mnemonic, "movabs") != 0)) | |
3781 | optimize_disp (); | |
29b0f896 AM |
3782 | |
3783 | /* Next, we find a template that matches the given insn, | |
3784 | making sure the overlap of the given operands types is consistent | |
3785 | with the template operand types. */ | |
252b5132 | 3786 | |
83b16ac6 | 3787 | if (!(t = match_template (mnem_suffix))) |
29b0f896 | 3788 | return; |
252b5132 | 3789 | |
7bab8ab5 | 3790 | if (sse_check != check_none |
81f8a913 | 3791 | && !i.tm.opcode_modifier.noavx |
daf50ae7 L |
3792 | && (i.tm.cpu_flags.bitfield.cpusse |
3793 | || i.tm.cpu_flags.bitfield.cpusse2 | |
3794 | || i.tm.cpu_flags.bitfield.cpusse3 | |
3795 | || i.tm.cpu_flags.bitfield.cpussse3 | |
3796 | || i.tm.cpu_flags.bitfield.cpusse4_1 | |
3797 | || i.tm.cpu_flags.bitfield.cpusse4_2)) | |
3798 | { | |
7bab8ab5 | 3799 | (sse_check == check_warning |
daf50ae7 L |
3800 | ? as_warn |
3801 | : as_bad) (_("SSE instruction `%s' is used"), i.tm.name); | |
3802 | } | |
3803 | ||
321fd21e L |
3804 | /* Zap movzx and movsx suffix. The suffix has been set from |
3805 | "word ptr" or "byte ptr" on the source operand in Intel syntax | |
3806 | or extracted from mnemonic in AT&T syntax. But we'll use | |
3807 | the destination register to choose the suffix for encoding. */ | |
3808 | if ((i.tm.base_opcode & ~9) == 0x0fb6) | |
cd61ebfe | 3809 | { |
321fd21e L |
3810 | /* In Intel syntax, there must be a suffix. In AT&T syntax, if |
3811 | there is no suffix, the default will be byte extension. */ | |
3812 | if (i.reg_operands != 2 | |
3813 | && !i.suffix | |
7ab9ffdd | 3814 | && intel_syntax) |
321fd21e L |
3815 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); |
3816 | ||
3817 | i.suffix = 0; | |
cd61ebfe | 3818 | } |
24eab124 | 3819 | |
40fb9820 | 3820 | if (i.tm.opcode_modifier.fwait) |
29b0f896 AM |
3821 | if (!add_prefix (FWAIT_OPCODE)) |
3822 | return; | |
252b5132 | 3823 | |
d5de92cf L |
3824 | /* Check if REP prefix is OK. */ |
3825 | if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok) | |
3826 | { | |
3827 | as_bad (_("invalid instruction `%s' after `%s'"), | |
3828 | i.tm.name, i.rep_prefix); | |
3829 | return; | |
3830 | } | |
3831 | ||
c1ba0266 L |
3832 | /* Check for lock without a lockable instruction. Destination operand |
3833 | must be memory unless it is xchg (0x86). */ | |
c32fa91d L |
3834 | if (i.prefix[LOCK_PREFIX] |
3835 | && (!i.tm.opcode_modifier.islockable | |
c1ba0266 L |
3836 | || i.mem_operands == 0 |
3837 | || (i.tm.base_opcode != 0x86 | |
3838 | && !operand_type_check (i.types[i.operands - 1], anymem)))) | |
c32fa91d L |
3839 | { |
3840 | as_bad (_("expecting lockable instruction after `lock'")); | |
3841 | return; | |
3842 | } | |
3843 | ||
42164a71 | 3844 | /* Check if HLE prefix is OK. */ |
165de32a | 3845 | if (i.hle_prefix && !check_hle ()) |
42164a71 L |
3846 | return; |
3847 | ||
7e8b059b L |
3848 | /* Check BND prefix. */ |
3849 | if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok) | |
3850 | as_bad (_("expecting valid branch instruction after `bnd'")); | |
3851 | ||
04ef582a | 3852 | /* Check NOTRACK prefix. */ |
9fef80d6 L |
3853 | if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok) |
3854 | as_bad (_("expecting indirect branch instruction after `notrack'")); | |
04ef582a | 3855 | |
327e8c42 JB |
3856 | if (i.tm.cpu_flags.bitfield.cpumpx) |
3857 | { | |
3858 | if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX]) | |
3859 | as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions.")); | |
3860 | else if (flag_code != CODE_16BIT | |
3861 | ? i.prefix[ADDR_PREFIX] | |
3862 | : i.mem_operands && !i.prefix[ADDR_PREFIX]) | |
3863 | as_bad (_("16-bit address isn't allowed in MPX instructions")); | |
3864 | } | |
7e8b059b L |
3865 | |
3866 | /* Insert BND prefix. */ | |
3867 | if (add_bnd_prefix | |
3868 | && i.tm.opcode_modifier.bndprefixok | |
3869 | && !i.prefix[BND_PREFIX]) | |
3870 | add_prefix (BND_PREFIX_OPCODE); | |
3871 | ||
29b0f896 | 3872 | /* Check string instruction segment overrides. */ |
40fb9820 | 3873 | if (i.tm.opcode_modifier.isstring && i.mem_operands != 0) |
29b0f896 AM |
3874 | { |
3875 | if (!check_string ()) | |
5dd0794d | 3876 | return; |
fc0763e6 | 3877 | i.disp_operands = 0; |
29b0f896 | 3878 | } |
5dd0794d | 3879 | |
29b0f896 AM |
3880 | if (!process_suffix ()) |
3881 | return; | |
e413e4e9 | 3882 | |
bc0844ae L |
3883 | /* Update operand types. */ |
3884 | for (j = 0; j < i.operands; j++) | |
3885 | i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]); | |
3886 | ||
29b0f896 AM |
3887 | /* Make still unresolved immediate matches conform to size of immediate |
3888 | given in i.suffix. */ | |
3889 | if (!finalize_imm ()) | |
3890 | return; | |
252b5132 | 3891 | |
40fb9820 | 3892 | if (i.types[0].bitfield.imm1) |
29b0f896 | 3893 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 | 3894 | |
9afe6eb8 L |
3895 | /* We only need to check those implicit registers for instructions |
3896 | with 3 operands or less. */ | |
3897 | if (i.operands <= 3) | |
3898 | for (j = 0; j < i.operands; j++) | |
3899 | if (i.types[j].bitfield.inoutportreg | |
3900 | || i.types[j].bitfield.shiftcount | |
1b54b8d7 | 3901 | || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword)) |
9afe6eb8 | 3902 | i.reg_operands--; |
40fb9820 | 3903 | |
c0f3af97 L |
3904 | /* ImmExt should be processed after SSE2AVX. */ |
3905 | if (!i.tm.opcode_modifier.sse2avx | |
3906 | && i.tm.opcode_modifier.immext) | |
65da13b5 | 3907 | process_immext (); |
252b5132 | 3908 | |
29b0f896 AM |
3909 | /* For insns with operands there are more diddles to do to the opcode. */ |
3910 | if (i.operands) | |
3911 | { | |
3912 | if (!process_operands ()) | |
3913 | return; | |
3914 | } | |
40fb9820 | 3915 | else if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 AM |
3916 | { |
3917 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ | |
3918 | as_warn (_("translating to `%sp'"), i.tm.name); | |
3919 | } | |
252b5132 | 3920 | |
9e5e5283 L |
3921 | if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex) |
3922 | { | |
3923 | if (flag_code == CODE_16BIT) | |
3924 | { | |
3925 | as_bad (_("instruction `%s' isn't supported in 16-bit mode."), | |
3926 | i.tm.name); | |
3927 | return; | |
3928 | } | |
c0f3af97 | 3929 | |
9e5e5283 L |
3930 | if (i.tm.opcode_modifier.vex) |
3931 | build_vex_prefix (t); | |
3932 | else | |
3933 | build_evex_prefix (); | |
3934 | } | |
43234a1e | 3935 | |
5dd85c99 SP |
3936 | /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4 |
3937 | instructions may define INT_OPCODE as well, so avoid this corner | |
3938 | case for those instructions that use MODRM. */ | |
3939 | if (i.tm.base_opcode == INT_OPCODE | |
a6461c02 SP |
3940 | && !i.tm.opcode_modifier.modrm |
3941 | && i.op[0].imms->X_add_number == 3) | |
29b0f896 AM |
3942 | { |
3943 | i.tm.base_opcode = INT3_OPCODE; | |
3944 | i.imm_operands = 0; | |
3945 | } | |
252b5132 | 3946 | |
40fb9820 L |
3947 | if ((i.tm.opcode_modifier.jump |
3948 | || i.tm.opcode_modifier.jumpbyte | |
3949 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 AM |
3950 | && i.op[0].disps->X_op == O_constant) |
3951 | { | |
3952 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
3953 | the absolute address given by the constant. Since ix86 jumps and | |
3954 | calls are pc relative, we need to generate a reloc. */ | |
3955 | i.op[0].disps->X_add_symbol = &abs_symbol; | |
3956 | i.op[0].disps->X_op = O_symbol; | |
3957 | } | |
252b5132 | 3958 | |
40fb9820 | 3959 | if (i.tm.opcode_modifier.rex64) |
161a04f6 | 3960 | i.rex |= REX_W; |
252b5132 | 3961 | |
29b0f896 AM |
3962 | /* For 8 bit registers we need an empty rex prefix. Also if the |
3963 | instruction already has a prefix, we need to convert old | |
3964 | registers to new ones. */ | |
773f551c | 3965 | |
dc821c5f | 3966 | if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte |
29b0f896 | 3967 | && (i.op[0].regs->reg_flags & RegRex64) != 0) |
dc821c5f | 3968 | || (i.types[1].bitfield.reg && i.types[1].bitfield.byte |
29b0f896 | 3969 | && (i.op[1].regs->reg_flags & RegRex64) != 0) |
dc821c5f JB |
3970 | || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte) |
3971 | || (i.types[1].bitfield.reg && i.types[1].bitfield.byte)) | |
29b0f896 AM |
3972 | && i.rex != 0)) |
3973 | { | |
3974 | int x; | |
726c5dcd | 3975 | |
29b0f896 AM |
3976 | i.rex |= REX_OPCODE; |
3977 | for (x = 0; x < 2; x++) | |
3978 | { | |
3979 | /* Look for 8 bit operand that uses old registers. */ | |
dc821c5f | 3980 | if (i.types[x].bitfield.reg && i.types[x].bitfield.byte |
29b0f896 | 3981 | && (i.op[x].regs->reg_flags & RegRex64) == 0) |
773f551c | 3982 | { |
29b0f896 AM |
3983 | /* In case it is "hi" register, give up. */ |
3984 | if (i.op[x].regs->reg_num > 3) | |
a540244d | 3985 | as_bad (_("can't encode register '%s%s' in an " |
4eed87de | 3986 | "instruction requiring REX prefix."), |
a540244d | 3987 | register_prefix, i.op[x].regs->reg_name); |
773f551c | 3988 | |
29b0f896 AM |
3989 | /* Otherwise it is equivalent to the extended register. |
3990 | Since the encoding doesn't change this is merely | |
3991 | cosmetic cleanup for debug output. */ | |
3992 | ||
3993 | i.op[x].regs = i.op[x].regs + 8; | |
773f551c | 3994 | } |
29b0f896 AM |
3995 | } |
3996 | } | |
773f551c | 3997 | |
6b6b6807 L |
3998 | if (i.rex == 0 && i.rex_encoding) |
3999 | { | |
4000 | /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand | |
4001 | that uses legacy register. If it is "hi" register, don't add | |
4002 | the REX_OPCODE byte. */ | |
4003 | int x; | |
4004 | for (x = 0; x < 2; x++) | |
4005 | if (i.types[x].bitfield.reg | |
4006 | && i.types[x].bitfield.byte | |
4007 | && (i.op[x].regs->reg_flags & RegRex64) == 0 | |
4008 | && i.op[x].regs->reg_num > 3) | |
4009 | { | |
4010 | i.rex_encoding = FALSE; | |
4011 | break; | |
4012 | } | |
4013 | ||
4014 | if (i.rex_encoding) | |
4015 | i.rex = REX_OPCODE; | |
4016 | } | |
4017 | ||
7ab9ffdd | 4018 | if (i.rex != 0) |
29b0f896 AM |
4019 | add_prefix (REX_OPCODE | i.rex); |
4020 | ||
4021 | /* We are ready to output the insn. */ | |
4022 | output_insn (); | |
4023 | } | |
4024 | ||
4025 | static char * | |
e3bb37b5 | 4026 | parse_insn (char *line, char *mnemonic) |
29b0f896 AM |
4027 | { |
4028 | char *l = line; | |
4029 | char *token_start = l; | |
4030 | char *mnem_p; | |
5c6af06e | 4031 | int supported; |
d3ce72d0 | 4032 | const insn_template *t; |
b6169b20 | 4033 | char *dot_p = NULL; |
29b0f896 | 4034 | |
29b0f896 AM |
4035 | while (1) |
4036 | { | |
4037 | mnem_p = mnemonic; | |
4038 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
4039 | { | |
b6169b20 L |
4040 | if (*mnem_p == '.') |
4041 | dot_p = mnem_p; | |
29b0f896 AM |
4042 | mnem_p++; |
4043 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
45288df1 | 4044 | { |
29b0f896 AM |
4045 | as_bad (_("no such instruction: `%s'"), token_start); |
4046 | return NULL; | |
4047 | } | |
4048 | l++; | |
4049 | } | |
4050 | if (!is_space_char (*l) | |
4051 | && *l != END_OF_INSN | |
e44823cf JB |
4052 | && (intel_syntax |
4053 | || (*l != PREFIX_SEPARATOR | |
4054 | && *l != ','))) | |
29b0f896 AM |
4055 | { |
4056 | as_bad (_("invalid character %s in mnemonic"), | |
4057 | output_invalid (*l)); | |
4058 | return NULL; | |
4059 | } | |
4060 | if (token_start == l) | |
4061 | { | |
e44823cf | 4062 | if (!intel_syntax && *l == PREFIX_SEPARATOR) |
29b0f896 AM |
4063 | as_bad (_("expecting prefix; got nothing")); |
4064 | else | |
4065 | as_bad (_("expecting mnemonic; got nothing")); | |
4066 | return NULL; | |
4067 | } | |
45288df1 | 4068 | |
29b0f896 | 4069 | /* Look up instruction (or prefix) via hash table. */ |
d3ce72d0 | 4070 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
47926f60 | 4071 | |
29b0f896 AM |
4072 | if (*l != END_OF_INSN |
4073 | && (!is_space_char (*l) || l[1] != END_OF_INSN) | |
4074 | && current_templates | |
40fb9820 | 4075 | && current_templates->start->opcode_modifier.isprefix) |
29b0f896 | 4076 | { |
c6fb90c8 | 4077 | if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags)) |
2dd88dca JB |
4078 | { |
4079 | as_bad ((flag_code != CODE_64BIT | |
4080 | ? _("`%s' is only supported in 64-bit mode") | |
4081 | : _("`%s' is not supported in 64-bit mode")), | |
4082 | current_templates->start->name); | |
4083 | return NULL; | |
4084 | } | |
29b0f896 AM |
4085 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
4086 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
40fb9820 L |
4087 | if ((current_templates->start->opcode_modifier.size16 |
4088 | || current_templates->start->opcode_modifier.size32) | |
29b0f896 | 4089 | && flag_code != CODE_64BIT |
40fb9820 | 4090 | && (current_templates->start->opcode_modifier.size32 |
29b0f896 AM |
4091 | ^ (flag_code == CODE_16BIT))) |
4092 | { | |
4093 | as_bad (_("redundant %s prefix"), | |
4094 | current_templates->start->name); | |
4095 | return NULL; | |
45288df1 | 4096 | } |
86fa6981 | 4097 | if (current_templates->start->opcode_length == 0) |
29b0f896 | 4098 | { |
86fa6981 L |
4099 | /* Handle pseudo prefixes. */ |
4100 | switch (current_templates->start->base_opcode) | |
4101 | { | |
4102 | case 0x0: | |
4103 | /* {disp8} */ | |
4104 | i.disp_encoding = disp_encoding_8bit; | |
4105 | break; | |
4106 | case 0x1: | |
4107 | /* {disp32} */ | |
4108 | i.disp_encoding = disp_encoding_32bit; | |
4109 | break; | |
4110 | case 0x2: | |
4111 | /* {load} */ | |
4112 | i.dir_encoding = dir_encoding_load; | |
4113 | break; | |
4114 | case 0x3: | |
4115 | /* {store} */ | |
4116 | i.dir_encoding = dir_encoding_store; | |
4117 | break; | |
4118 | case 0x4: | |
4119 | /* {vex2} */ | |
4120 | i.vec_encoding = vex_encoding_vex2; | |
4121 | break; | |
4122 | case 0x5: | |
4123 | /* {vex3} */ | |
4124 | i.vec_encoding = vex_encoding_vex3; | |
4125 | break; | |
4126 | case 0x6: | |
4127 | /* {evex} */ | |
4128 | i.vec_encoding = vex_encoding_evex; | |
4129 | break; | |
6b6b6807 L |
4130 | case 0x7: |
4131 | /* {rex} */ | |
4132 | i.rex_encoding = TRUE; | |
4133 | break; | |
86fa6981 L |
4134 | default: |
4135 | abort (); | |
4136 | } | |
4137 | } | |
4138 | else | |
4139 | { | |
4140 | /* Add prefix, checking for repeated prefixes. */ | |
4e9ac44a | 4141 | switch (add_prefix (current_templates->start->base_opcode)) |
86fa6981 | 4142 | { |
4e9ac44a L |
4143 | case PREFIX_EXIST: |
4144 | return NULL; | |
4145 | case PREFIX_DS: | |
d777820b | 4146 | if (current_templates->start->cpu_flags.bitfield.cpuibt) |
4e9ac44a L |
4147 | i.notrack_prefix = current_templates->start->name; |
4148 | break; | |
4149 | case PREFIX_REP: | |
4150 | if (current_templates->start->cpu_flags.bitfield.cpuhle) | |
4151 | i.hle_prefix = current_templates->start->name; | |
4152 | else if (current_templates->start->cpu_flags.bitfield.cpumpx) | |
4153 | i.bnd_prefix = current_templates->start->name; | |
4154 | else | |
4155 | i.rep_prefix = current_templates->start->name; | |
4156 | break; | |
4157 | default: | |
4158 | break; | |
86fa6981 | 4159 | } |
29b0f896 AM |
4160 | } |
4161 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
4162 | token_start = ++l; | |
4163 | } | |
4164 | else | |
4165 | break; | |
4166 | } | |
45288df1 | 4167 | |
30a55f88 | 4168 | if (!current_templates) |
b6169b20 | 4169 | { |
f8a5c266 L |
4170 | /* Check if we should swap operand or force 32bit displacement in |
4171 | encoding. */ | |
30a55f88 | 4172 | if (mnem_p - 2 == dot_p && dot_p[1] == 's') |
86fa6981 | 4173 | i.dir_encoding = dir_encoding_store; |
8d63c93e | 4174 | else if (mnem_p - 3 == dot_p |
a501d77e L |
4175 | && dot_p[1] == 'd' |
4176 | && dot_p[2] == '8') | |
4177 | i.disp_encoding = disp_encoding_8bit; | |
8d63c93e | 4178 | else if (mnem_p - 4 == dot_p |
f8a5c266 L |
4179 | && dot_p[1] == 'd' |
4180 | && dot_p[2] == '3' | |
4181 | && dot_p[3] == '2') | |
a501d77e | 4182 | i.disp_encoding = disp_encoding_32bit; |
30a55f88 L |
4183 | else |
4184 | goto check_suffix; | |
4185 | mnem_p = dot_p; | |
4186 | *dot_p = '\0'; | |
d3ce72d0 | 4187 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
b6169b20 L |
4188 | } |
4189 | ||
29b0f896 AM |
4190 | if (!current_templates) |
4191 | { | |
b6169b20 | 4192 | check_suffix: |
29b0f896 AM |
4193 | /* See if we can get a match by trimming off a suffix. */ |
4194 | switch (mnem_p[-1]) | |
4195 | { | |
4196 | case WORD_MNEM_SUFFIX: | |
9306ca4a JB |
4197 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) |
4198 | i.suffix = SHORT_MNEM_SUFFIX; | |
4199 | else | |
1a0670f3 | 4200 | /* Fall through. */ |
29b0f896 AM |
4201 | case BYTE_MNEM_SUFFIX: |
4202 | case QWORD_MNEM_SUFFIX: | |
4203 | i.suffix = mnem_p[-1]; | |
4204 | mnem_p[-1] = '\0'; | |
d3ce72d0 NC |
4205 | current_templates = (const templates *) hash_find (op_hash, |
4206 | mnemonic); | |
29b0f896 AM |
4207 | break; |
4208 | case SHORT_MNEM_SUFFIX: | |
4209 | case LONG_MNEM_SUFFIX: | |
4210 | if (!intel_syntax) | |
4211 | { | |
4212 | i.suffix = mnem_p[-1]; | |
4213 | mnem_p[-1] = '\0'; | |
d3ce72d0 NC |
4214 | current_templates = (const templates *) hash_find (op_hash, |
4215 | mnemonic); | |
29b0f896 AM |
4216 | } |
4217 | break; | |
252b5132 | 4218 | |
29b0f896 AM |
4219 | /* Intel Syntax. */ |
4220 | case 'd': | |
4221 | if (intel_syntax) | |
4222 | { | |
9306ca4a | 4223 | if (intel_float_operand (mnemonic) == 1) |
29b0f896 AM |
4224 | i.suffix = SHORT_MNEM_SUFFIX; |
4225 | else | |
4226 | i.suffix = LONG_MNEM_SUFFIX; | |
4227 | mnem_p[-1] = '\0'; | |
d3ce72d0 NC |
4228 | current_templates = (const templates *) hash_find (op_hash, |
4229 | mnemonic); | |
29b0f896 AM |
4230 | } |
4231 | break; | |
4232 | } | |
4233 | if (!current_templates) | |
4234 | { | |
4235 | as_bad (_("no such instruction: `%s'"), token_start); | |
4236 | return NULL; | |
4237 | } | |
4238 | } | |
252b5132 | 4239 | |
40fb9820 L |
4240 | if (current_templates->start->opcode_modifier.jump |
4241 | || current_templates->start->opcode_modifier.jumpbyte) | |
29b0f896 AM |
4242 | { |
4243 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
4244 | predict taken and predict not taken respectively. | |
4245 | I'm not sure that branch hints actually do anything on loop | |
4246 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
4247 | may work in the future and it doesn't hurt to accept them | |
4248 | now. */ | |
4249 | if (l[0] == ',' && l[1] == 'p') | |
4250 | { | |
4251 | if (l[2] == 't') | |
4252 | { | |
4253 | if (!add_prefix (DS_PREFIX_OPCODE)) | |
4254 | return NULL; | |
4255 | l += 3; | |
4256 | } | |
4257 | else if (l[2] == 'n') | |
4258 | { | |
4259 | if (!add_prefix (CS_PREFIX_OPCODE)) | |
4260 | return NULL; | |
4261 | l += 3; | |
4262 | } | |
4263 | } | |
4264 | } | |
4265 | /* Any other comma loses. */ | |
4266 | if (*l == ',') | |
4267 | { | |
4268 | as_bad (_("invalid character %s in mnemonic"), | |
4269 | output_invalid (*l)); | |
4270 | return NULL; | |
4271 | } | |
252b5132 | 4272 | |
29b0f896 | 4273 | /* Check if instruction is supported on specified architecture. */ |
5c6af06e JB |
4274 | supported = 0; |
4275 | for (t = current_templates->start; t < current_templates->end; ++t) | |
4276 | { | |
c0f3af97 L |
4277 | supported |= cpu_flags_match (t); |
4278 | if (supported == CPU_FLAGS_PERFECT_MATCH) | |
3629bb00 | 4279 | goto skip; |
5c6af06e | 4280 | } |
3629bb00 | 4281 | |
c0f3af97 | 4282 | if (!(supported & CPU_FLAGS_64BIT_MATCH)) |
5c6af06e JB |
4283 | { |
4284 | as_bad (flag_code == CODE_64BIT | |
4285 | ? _("`%s' is not supported in 64-bit mode") | |
4286 | : _("`%s' is only supported in 64-bit mode"), | |
4287 | current_templates->start->name); | |
4288 | return NULL; | |
4289 | } | |
c0f3af97 | 4290 | if (supported != CPU_FLAGS_PERFECT_MATCH) |
29b0f896 | 4291 | { |
3629bb00 | 4292 | as_bad (_("`%s' is not supported on `%s%s'"), |
7ab9ffdd | 4293 | current_templates->start->name, |
41aacd83 | 4294 | cpu_arch_name ? cpu_arch_name : default_arch, |
3629bb00 L |
4295 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); |
4296 | return NULL; | |
29b0f896 | 4297 | } |
3629bb00 L |
4298 | |
4299 | skip: | |
4300 | if (!cpu_arch_flags.bitfield.cpui386 | |
40fb9820 | 4301 | && (flag_code != CODE_16BIT)) |
29b0f896 AM |
4302 | { |
4303 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
4304 | } | |
252b5132 | 4305 | |
29b0f896 AM |
4306 | return l; |
4307 | } | |
252b5132 | 4308 | |
29b0f896 | 4309 | static char * |
e3bb37b5 | 4310 | parse_operands (char *l, const char *mnemonic) |
29b0f896 AM |
4311 | { |
4312 | char *token_start; | |
3138f287 | 4313 | |
29b0f896 AM |
4314 | /* 1 if operand is pending after ','. */ |
4315 | unsigned int expecting_operand = 0; | |
252b5132 | 4316 | |
29b0f896 AM |
4317 | /* Non-zero if operand parens not balanced. */ |
4318 | unsigned int paren_not_balanced; | |
4319 | ||
4320 | while (*l != END_OF_INSN) | |
4321 | { | |
4322 | /* Skip optional white space before operand. */ | |
4323 | if (is_space_char (*l)) | |
4324 | ++l; | |
d02603dc | 4325 | if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"') |
29b0f896 AM |
4326 | { |
4327 | as_bad (_("invalid character %s before operand %d"), | |
4328 | output_invalid (*l), | |
4329 | i.operands + 1); | |
4330 | return NULL; | |
4331 | } | |
d02603dc | 4332 | token_start = l; /* After white space. */ |
29b0f896 AM |
4333 | paren_not_balanced = 0; |
4334 | while (paren_not_balanced || *l != ',') | |
4335 | { | |
4336 | if (*l == END_OF_INSN) | |
4337 | { | |
4338 | if (paren_not_balanced) | |
4339 | { | |
4340 | if (!intel_syntax) | |
4341 | as_bad (_("unbalanced parenthesis in operand %d."), | |
4342 | i.operands + 1); | |
4343 | else | |
4344 | as_bad (_("unbalanced brackets in operand %d."), | |
4345 | i.operands + 1); | |
4346 | return NULL; | |
4347 | } | |
4348 | else | |
4349 | break; /* we are done */ | |
4350 | } | |
d02603dc | 4351 | else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"') |
29b0f896 AM |
4352 | { |
4353 | as_bad (_("invalid character %s in operand %d"), | |
4354 | output_invalid (*l), | |
4355 | i.operands + 1); | |
4356 | return NULL; | |
4357 | } | |
4358 | if (!intel_syntax) | |
4359 | { | |
4360 | if (*l == '(') | |
4361 | ++paren_not_balanced; | |
4362 | if (*l == ')') | |
4363 | --paren_not_balanced; | |
4364 | } | |
4365 | else | |
4366 | { | |
4367 | if (*l == '[') | |
4368 | ++paren_not_balanced; | |
4369 | if (*l == ']') | |
4370 | --paren_not_balanced; | |
4371 | } | |
4372 | l++; | |
4373 | } | |
4374 | if (l != token_start) | |
4375 | { /* Yes, we've read in another operand. */ | |
4376 | unsigned int operand_ok; | |
4377 | this_operand = i.operands++; | |
4378 | if (i.operands > MAX_OPERANDS) | |
4379 | { | |
4380 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
4381 | MAX_OPERANDS); | |
4382 | return NULL; | |
4383 | } | |
9d46ce34 | 4384 | i.types[this_operand].bitfield.unspecified = 1; |
29b0f896 AM |
4385 | /* Now parse operand adding info to 'i' as we go along. */ |
4386 | END_STRING_AND_SAVE (l); | |
4387 | ||
4388 | if (intel_syntax) | |
4389 | operand_ok = | |
4390 | i386_intel_operand (token_start, | |
4391 | intel_float_operand (mnemonic)); | |
4392 | else | |
a7619375 | 4393 | operand_ok = i386_att_operand (token_start); |
29b0f896 AM |
4394 | |
4395 | RESTORE_END_STRING (l); | |
4396 | if (!operand_ok) | |
4397 | return NULL; | |
4398 | } | |
4399 | else | |
4400 | { | |
4401 | if (expecting_operand) | |
4402 | { | |
4403 | expecting_operand_after_comma: | |
4404 | as_bad (_("expecting operand after ','; got nothing")); | |
4405 | return NULL; | |
4406 | } | |
4407 | if (*l == ',') | |
4408 | { | |
4409 | as_bad (_("expecting operand before ','; got nothing")); | |
4410 | return NULL; | |
4411 | } | |
4412 | } | |
7f3f1ea2 | 4413 | |
29b0f896 AM |
4414 | /* Now *l must be either ',' or END_OF_INSN. */ |
4415 | if (*l == ',') | |
4416 | { | |
4417 | if (*++l == END_OF_INSN) | |
4418 | { | |
4419 | /* Just skip it, if it's \n complain. */ | |
4420 | goto expecting_operand_after_comma; | |
4421 | } | |
4422 | expecting_operand = 1; | |
4423 | } | |
4424 | } | |
4425 | return l; | |
4426 | } | |
7f3f1ea2 | 4427 | |
050dfa73 | 4428 | static void |
4d456e3d | 4429 | swap_2_operands (int xchg1, int xchg2) |
050dfa73 MM |
4430 | { |
4431 | union i386_op temp_op; | |
40fb9820 | 4432 | i386_operand_type temp_type; |
050dfa73 | 4433 | enum bfd_reloc_code_real temp_reloc; |
4eed87de | 4434 | |
050dfa73 MM |
4435 | temp_type = i.types[xchg2]; |
4436 | i.types[xchg2] = i.types[xchg1]; | |
4437 | i.types[xchg1] = temp_type; | |
4438 | temp_op = i.op[xchg2]; | |
4439 | i.op[xchg2] = i.op[xchg1]; | |
4440 | i.op[xchg1] = temp_op; | |
4441 | temp_reloc = i.reloc[xchg2]; | |
4442 | i.reloc[xchg2] = i.reloc[xchg1]; | |
4443 | i.reloc[xchg1] = temp_reloc; | |
43234a1e L |
4444 | |
4445 | if (i.mask) | |
4446 | { | |
4447 | if (i.mask->operand == xchg1) | |
4448 | i.mask->operand = xchg2; | |
4449 | else if (i.mask->operand == xchg2) | |
4450 | i.mask->operand = xchg1; | |
4451 | } | |
4452 | if (i.broadcast) | |
4453 | { | |
4454 | if (i.broadcast->operand == xchg1) | |
4455 | i.broadcast->operand = xchg2; | |
4456 | else if (i.broadcast->operand == xchg2) | |
4457 | i.broadcast->operand = xchg1; | |
4458 | } | |
4459 | if (i.rounding) | |
4460 | { | |
4461 | if (i.rounding->operand == xchg1) | |
4462 | i.rounding->operand = xchg2; | |
4463 | else if (i.rounding->operand == xchg2) | |
4464 | i.rounding->operand = xchg1; | |
4465 | } | |
050dfa73 MM |
4466 | } |
4467 | ||
29b0f896 | 4468 | static void |
e3bb37b5 | 4469 | swap_operands (void) |
29b0f896 | 4470 | { |
b7c61d9a | 4471 | switch (i.operands) |
050dfa73 | 4472 | { |
c0f3af97 | 4473 | case 5: |
b7c61d9a | 4474 | case 4: |
4d456e3d | 4475 | swap_2_operands (1, i.operands - 2); |
1a0670f3 | 4476 | /* Fall through. */ |
b7c61d9a L |
4477 | case 3: |
4478 | case 2: | |
4d456e3d | 4479 | swap_2_operands (0, i.operands - 1); |
b7c61d9a L |
4480 | break; |
4481 | default: | |
4482 | abort (); | |
29b0f896 | 4483 | } |
29b0f896 AM |
4484 | |
4485 | if (i.mem_operands == 2) | |
4486 | { | |
4487 | const seg_entry *temp_seg; | |
4488 | temp_seg = i.seg[0]; | |
4489 | i.seg[0] = i.seg[1]; | |
4490 | i.seg[1] = temp_seg; | |
4491 | } | |
4492 | } | |
252b5132 | 4493 | |
29b0f896 AM |
4494 | /* Try to ensure constant immediates are represented in the smallest |
4495 | opcode possible. */ | |
4496 | static void | |
e3bb37b5 | 4497 | optimize_imm (void) |
29b0f896 AM |
4498 | { |
4499 | char guess_suffix = 0; | |
4500 | int op; | |
252b5132 | 4501 | |
29b0f896 AM |
4502 | if (i.suffix) |
4503 | guess_suffix = i.suffix; | |
4504 | else if (i.reg_operands) | |
4505 | { | |
4506 | /* Figure out a suffix from the last register operand specified. | |
4507 | We can't do this properly yet, ie. excluding InOutPortReg, | |
4508 | but the following works for instructions with immediates. | |
4509 | In any case, we can't set i.suffix yet. */ | |
4510 | for (op = i.operands; --op >= 0;) | |
dc821c5f | 4511 | if (i.types[op].bitfield.reg && i.types[op].bitfield.byte) |
7ab9ffdd | 4512 | { |
40fb9820 L |
4513 | guess_suffix = BYTE_MNEM_SUFFIX; |
4514 | break; | |
4515 | } | |
dc821c5f | 4516 | else if (i.types[op].bitfield.reg && i.types[op].bitfield.word) |
252b5132 | 4517 | { |
40fb9820 L |
4518 | guess_suffix = WORD_MNEM_SUFFIX; |
4519 | break; | |
4520 | } | |
dc821c5f | 4521 | else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword) |
40fb9820 L |
4522 | { |
4523 | guess_suffix = LONG_MNEM_SUFFIX; | |
4524 | break; | |
4525 | } | |
dc821c5f | 4526 | else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword) |
40fb9820 L |
4527 | { |
4528 | guess_suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 | 4529 | break; |
252b5132 | 4530 | } |
29b0f896 AM |
4531 | } |
4532 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) | |
4533 | guess_suffix = WORD_MNEM_SUFFIX; | |
4534 | ||
4535 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 4536 | if (operand_type_check (i.types[op], imm)) |
29b0f896 AM |
4537 | { |
4538 | switch (i.op[op].imms->X_op) | |
252b5132 | 4539 | { |
29b0f896 AM |
4540 | case O_constant: |
4541 | /* If a suffix is given, this operand may be shortened. */ | |
4542 | switch (guess_suffix) | |
252b5132 | 4543 | { |
29b0f896 | 4544 | case LONG_MNEM_SUFFIX: |
40fb9820 L |
4545 | i.types[op].bitfield.imm32 = 1; |
4546 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
4547 | break; |
4548 | case WORD_MNEM_SUFFIX: | |
40fb9820 L |
4549 | i.types[op].bitfield.imm16 = 1; |
4550 | i.types[op].bitfield.imm32 = 1; | |
4551 | i.types[op].bitfield.imm32s = 1; | |
4552 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
4553 | break; |
4554 | case BYTE_MNEM_SUFFIX: | |
40fb9820 L |
4555 | i.types[op].bitfield.imm8 = 1; |
4556 | i.types[op].bitfield.imm8s = 1; | |
4557 | i.types[op].bitfield.imm16 = 1; | |
4558 | i.types[op].bitfield.imm32 = 1; | |
4559 | i.types[op].bitfield.imm32s = 1; | |
4560 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 | 4561 | break; |
252b5132 | 4562 | } |
252b5132 | 4563 | |
29b0f896 AM |
4564 | /* If this operand is at most 16 bits, convert it |
4565 | to a signed 16 bit number before trying to see | |
4566 | whether it will fit in an even smaller size. | |
4567 | This allows a 16-bit operand such as $0xffe0 to | |
4568 | be recognised as within Imm8S range. */ | |
40fb9820 | 4569 | if ((i.types[op].bitfield.imm16) |
29b0f896 | 4570 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) |
252b5132 | 4571 | { |
29b0f896 AM |
4572 | i.op[op].imms->X_add_number = |
4573 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
4574 | } | |
a28def75 L |
4575 | #ifdef BFD64 |
4576 | /* Store 32-bit immediate in 64-bit for 64-bit BFD. */ | |
40fb9820 | 4577 | if ((i.types[op].bitfield.imm32) |
29b0f896 AM |
4578 | && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) |
4579 | == 0)) | |
4580 | { | |
4581 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number | |
4582 | ^ ((offsetT) 1 << 31)) | |
4583 | - ((offsetT) 1 << 31)); | |
4584 | } | |
a28def75 | 4585 | #endif |
40fb9820 | 4586 | i.types[op] |
c6fb90c8 L |
4587 | = operand_type_or (i.types[op], |
4588 | smallest_imm_type (i.op[op].imms->X_add_number)); | |
252b5132 | 4589 | |
29b0f896 AM |
4590 | /* We must avoid matching of Imm32 templates when 64bit |
4591 | only immediate is available. */ | |
4592 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
40fb9820 | 4593 | i.types[op].bitfield.imm32 = 0; |
29b0f896 | 4594 | break; |
252b5132 | 4595 | |
29b0f896 AM |
4596 | case O_absent: |
4597 | case O_register: | |
4598 | abort (); | |
4599 | ||
4600 | /* Symbols and expressions. */ | |
4601 | default: | |
9cd96992 JB |
4602 | /* Convert symbolic operand to proper sizes for matching, but don't |
4603 | prevent matching a set of insns that only supports sizes other | |
4604 | than those matching the insn suffix. */ | |
4605 | { | |
40fb9820 | 4606 | i386_operand_type mask, allowed; |
d3ce72d0 | 4607 | const insn_template *t; |
9cd96992 | 4608 | |
0dfbf9d7 L |
4609 | operand_type_set (&mask, 0); |
4610 | operand_type_set (&allowed, 0); | |
40fb9820 | 4611 | |
4eed87de AM |
4612 | for (t = current_templates->start; |
4613 | t < current_templates->end; | |
4614 | ++t) | |
c6fb90c8 L |
4615 | allowed = operand_type_or (allowed, |
4616 | t->operand_types[op]); | |
9cd96992 JB |
4617 | switch (guess_suffix) |
4618 | { | |
4619 | case QWORD_MNEM_SUFFIX: | |
40fb9820 L |
4620 | mask.bitfield.imm64 = 1; |
4621 | mask.bitfield.imm32s = 1; | |
9cd96992 JB |
4622 | break; |
4623 | case LONG_MNEM_SUFFIX: | |
40fb9820 | 4624 | mask.bitfield.imm32 = 1; |
9cd96992 JB |
4625 | break; |
4626 | case WORD_MNEM_SUFFIX: | |
40fb9820 | 4627 | mask.bitfield.imm16 = 1; |
9cd96992 JB |
4628 | break; |
4629 | case BYTE_MNEM_SUFFIX: | |
40fb9820 | 4630 | mask.bitfield.imm8 = 1; |
9cd96992 JB |
4631 | break; |
4632 | default: | |
9cd96992 JB |
4633 | break; |
4634 | } | |
c6fb90c8 | 4635 | allowed = operand_type_and (mask, allowed); |
0dfbf9d7 | 4636 | if (!operand_type_all_zero (&allowed)) |
c6fb90c8 | 4637 | i.types[op] = operand_type_and (i.types[op], mask); |
9cd96992 | 4638 | } |
29b0f896 | 4639 | break; |
252b5132 | 4640 | } |
29b0f896 AM |
4641 | } |
4642 | } | |
47926f60 | 4643 | |
29b0f896 AM |
4644 | /* Try to use the smallest displacement type too. */ |
4645 | static void | |
e3bb37b5 | 4646 | optimize_disp (void) |
29b0f896 AM |
4647 | { |
4648 | int op; | |
3e73aa7c | 4649 | |
29b0f896 | 4650 | for (op = i.operands; --op >= 0;) |
40fb9820 | 4651 | if (operand_type_check (i.types[op], disp)) |
252b5132 | 4652 | { |
b300c311 | 4653 | if (i.op[op].disps->X_op == O_constant) |
252b5132 | 4654 | { |
91d6fa6a | 4655 | offsetT op_disp = i.op[op].disps->X_add_number; |
29b0f896 | 4656 | |
40fb9820 | 4657 | if (i.types[op].bitfield.disp16 |
91d6fa6a | 4658 | && (op_disp & ~(offsetT) 0xffff) == 0) |
b300c311 L |
4659 | { |
4660 | /* If this operand is at most 16 bits, convert | |
4661 | to a signed 16 bit number and don't use 64bit | |
4662 | displacement. */ | |
91d6fa6a | 4663 | op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000); |
40fb9820 | 4664 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 4665 | } |
a28def75 L |
4666 | #ifdef BFD64 |
4667 | /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */ | |
40fb9820 | 4668 | if (i.types[op].bitfield.disp32 |
91d6fa6a | 4669 | && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0) |
b300c311 L |
4670 | { |
4671 | /* If this operand is at most 32 bits, convert | |
4672 | to a signed 32 bit number and don't use 64bit | |
4673 | displacement. */ | |
91d6fa6a NC |
4674 | op_disp &= (((offsetT) 2 << 31) - 1); |
4675 | op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
40fb9820 | 4676 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 4677 | } |
a28def75 | 4678 | #endif |
91d6fa6a | 4679 | if (!op_disp && i.types[op].bitfield.baseindex) |
b300c311 | 4680 | { |
40fb9820 L |
4681 | i.types[op].bitfield.disp8 = 0; |
4682 | i.types[op].bitfield.disp16 = 0; | |
4683 | i.types[op].bitfield.disp32 = 0; | |
4684 | i.types[op].bitfield.disp32s = 0; | |
4685 | i.types[op].bitfield.disp64 = 0; | |
b300c311 L |
4686 | i.op[op].disps = 0; |
4687 | i.disp_operands--; | |
4688 | } | |
4689 | else if (flag_code == CODE_64BIT) | |
4690 | { | |
91d6fa6a | 4691 | if (fits_in_signed_long (op_disp)) |
28a9d8f5 | 4692 | { |
40fb9820 L |
4693 | i.types[op].bitfield.disp64 = 0; |
4694 | i.types[op].bitfield.disp32s = 1; | |
28a9d8f5 | 4695 | } |
0e1147d9 | 4696 | if (i.prefix[ADDR_PREFIX] |
91d6fa6a | 4697 | && fits_in_unsigned_long (op_disp)) |
40fb9820 | 4698 | i.types[op].bitfield.disp32 = 1; |
b300c311 | 4699 | } |
40fb9820 L |
4700 | if ((i.types[op].bitfield.disp32 |
4701 | || i.types[op].bitfield.disp32s | |
4702 | || i.types[op].bitfield.disp16) | |
b5014f7a | 4703 | && fits_in_disp8 (op_disp)) |
40fb9820 | 4704 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 4705 | } |
67a4f2b7 AO |
4706 | else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
4707 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) | |
4708 | { | |
4709 | fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, | |
4710 | i.op[op].disps, 0, i.reloc[op]); | |
40fb9820 L |
4711 | i.types[op].bitfield.disp8 = 0; |
4712 | i.types[op].bitfield.disp16 = 0; | |
4713 | i.types[op].bitfield.disp32 = 0; | |
4714 | i.types[op].bitfield.disp32s = 0; | |
4715 | i.types[op].bitfield.disp64 = 0; | |
67a4f2b7 AO |
4716 | } |
4717 | else | |
b300c311 | 4718 | /* We only support 64bit displacement on constants. */ |
40fb9820 | 4719 | i.types[op].bitfield.disp64 = 0; |
252b5132 | 4720 | } |
29b0f896 AM |
4721 | } |
4722 | ||
6c30d220 L |
4723 | /* Check if operands are valid for the instruction. */ |
4724 | ||
4725 | static int | |
4726 | check_VecOperands (const insn_template *t) | |
4727 | { | |
43234a1e L |
4728 | unsigned int op; |
4729 | ||
6c30d220 L |
4730 | /* Without VSIB byte, we can't have a vector register for index. */ |
4731 | if (!t->opcode_modifier.vecsib | |
4732 | && i.index_reg | |
1b54b8d7 JB |
4733 | && (i.index_reg->reg_type.bitfield.xmmword |
4734 | || i.index_reg->reg_type.bitfield.ymmword | |
4735 | || i.index_reg->reg_type.bitfield.zmmword)) | |
6c30d220 L |
4736 | { |
4737 | i.error = unsupported_vector_index_register; | |
4738 | return 1; | |
4739 | } | |
4740 | ||
ad8ecc81 MZ |
4741 | /* Check if default mask is allowed. */ |
4742 | if (t->opcode_modifier.nodefmask | |
4743 | && (!i.mask || i.mask->mask->reg_num == 0)) | |
4744 | { | |
4745 | i.error = no_default_mask; | |
4746 | return 1; | |
4747 | } | |
4748 | ||
7bab8ab5 JB |
4749 | /* For VSIB byte, we need a vector register for index, and all vector |
4750 | registers must be distinct. */ | |
4751 | if (t->opcode_modifier.vecsib) | |
4752 | { | |
4753 | if (!i.index_reg | |
6c30d220 | 4754 | || !((t->opcode_modifier.vecsib == VecSIB128 |
1b54b8d7 | 4755 | && i.index_reg->reg_type.bitfield.xmmword) |
6c30d220 | 4756 | || (t->opcode_modifier.vecsib == VecSIB256 |
1b54b8d7 | 4757 | && i.index_reg->reg_type.bitfield.ymmword) |
43234a1e | 4758 | || (t->opcode_modifier.vecsib == VecSIB512 |
1b54b8d7 | 4759 | && i.index_reg->reg_type.bitfield.zmmword))) |
7bab8ab5 JB |
4760 | { |
4761 | i.error = invalid_vsib_address; | |
4762 | return 1; | |
4763 | } | |
4764 | ||
43234a1e L |
4765 | gas_assert (i.reg_operands == 2 || i.mask); |
4766 | if (i.reg_operands == 2 && !i.mask) | |
4767 | { | |
1b54b8d7 JB |
4768 | gas_assert (i.types[0].bitfield.regsimd); |
4769 | gas_assert (i.types[0].bitfield.xmmword | |
4770 | || i.types[0].bitfield.ymmword); | |
4771 | gas_assert (i.types[2].bitfield.regsimd); | |
4772 | gas_assert (i.types[2].bitfield.xmmword | |
4773 | || i.types[2].bitfield.ymmword); | |
43234a1e L |
4774 | if (operand_check == check_none) |
4775 | return 0; | |
4776 | if (register_number (i.op[0].regs) | |
4777 | != register_number (i.index_reg) | |
4778 | && register_number (i.op[2].regs) | |
4779 | != register_number (i.index_reg) | |
4780 | && register_number (i.op[0].regs) | |
4781 | != register_number (i.op[2].regs)) | |
4782 | return 0; | |
4783 | if (operand_check == check_error) | |
4784 | { | |
4785 | i.error = invalid_vector_register_set; | |
4786 | return 1; | |
4787 | } | |
4788 | as_warn (_("mask, index, and destination registers should be distinct")); | |
4789 | } | |
8444f82a MZ |
4790 | else if (i.reg_operands == 1 && i.mask) |
4791 | { | |
1b54b8d7 JB |
4792 | if (i.types[1].bitfield.regsimd |
4793 | && (i.types[1].bitfield.xmmword | |
4794 | || i.types[1].bitfield.ymmword | |
4795 | || i.types[1].bitfield.zmmword) | |
8444f82a MZ |
4796 | && (register_number (i.op[1].regs) |
4797 | == register_number (i.index_reg))) | |
4798 | { | |
4799 | if (operand_check == check_error) | |
4800 | { | |
4801 | i.error = invalid_vector_register_set; | |
4802 | return 1; | |
4803 | } | |
4804 | if (operand_check != check_none) | |
4805 | as_warn (_("index and destination registers should be distinct")); | |
4806 | } | |
4807 | } | |
43234a1e | 4808 | } |
7bab8ab5 | 4809 | |
43234a1e L |
4810 | /* Check if broadcast is supported by the instruction and is applied |
4811 | to the memory operand. */ | |
4812 | if (i.broadcast) | |
4813 | { | |
4814 | int broadcasted_opnd_size; | |
4815 | ||
4816 | /* Check if specified broadcast is supported in this instruction, | |
4817 | and it's applied to memory operand of DWORD or QWORD type, | |
4818 | depending on VecESize. */ | |
4819 | if (i.broadcast->type != t->opcode_modifier.broadcast | |
4820 | || !i.types[i.broadcast->operand].bitfield.mem | |
4821 | || (t->opcode_modifier.vecesize == 0 | |
4822 | && !i.types[i.broadcast->operand].bitfield.dword | |
4823 | && !i.types[i.broadcast->operand].bitfield.unspecified) | |
4824 | || (t->opcode_modifier.vecesize == 1 | |
4825 | && !i.types[i.broadcast->operand].bitfield.qword | |
4826 | && !i.types[i.broadcast->operand].bitfield.unspecified)) | |
4827 | goto bad_broadcast; | |
4828 | ||
4829 | broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32; | |
4830 | if (i.broadcast->type == BROADCAST_1TO16) | |
4831 | broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */ | |
4832 | else if (i.broadcast->type == BROADCAST_1TO8) | |
4833 | broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */ | |
b28d1bda IT |
4834 | else if (i.broadcast->type == BROADCAST_1TO4) |
4835 | broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */ | |
4836 | else if (i.broadcast->type == BROADCAST_1TO2) | |
4837 | broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */ | |
43234a1e L |
4838 | else |
4839 | goto bad_broadcast; | |
4840 | ||
4841 | if ((broadcasted_opnd_size == 256 | |
4842 | && !t->operand_types[i.broadcast->operand].bitfield.ymmword) | |
4843 | || (broadcasted_opnd_size == 512 | |
4844 | && !t->operand_types[i.broadcast->operand].bitfield.zmmword)) | |
4845 | { | |
4846 | bad_broadcast: | |
4847 | i.error = unsupported_broadcast; | |
4848 | return 1; | |
4849 | } | |
4850 | } | |
4851 | /* If broadcast is supported in this instruction, we need to check if | |
4852 | operand of one-element size isn't specified without broadcast. */ | |
4853 | else if (t->opcode_modifier.broadcast && i.mem_operands) | |
4854 | { | |
4855 | /* Find memory operand. */ | |
4856 | for (op = 0; op < i.operands; op++) | |
4857 | if (operand_type_check (i.types[op], anymem)) | |
4858 | break; | |
4859 | gas_assert (op < i.operands); | |
4860 | /* Check size of the memory operand. */ | |
4861 | if ((t->opcode_modifier.vecesize == 0 | |
4862 | && i.types[op].bitfield.dword) | |
4863 | || (t->opcode_modifier.vecesize == 1 | |
4864 | && i.types[op].bitfield.qword)) | |
4865 | { | |
4866 | i.error = broadcast_needed; | |
4867 | return 1; | |
4868 | } | |
4869 | } | |
4870 | ||
4871 | /* Check if requested masking is supported. */ | |
4872 | if (i.mask | |
4873 | && (!t->opcode_modifier.masking | |
4874 | || (i.mask->zeroing | |
4875 | && t->opcode_modifier.masking == MERGING_MASKING))) | |
4876 | { | |
4877 | i.error = unsupported_masking; | |
4878 | return 1; | |
4879 | } | |
4880 | ||
4881 | /* Check if masking is applied to dest operand. */ | |
4882 | if (i.mask && (i.mask->operand != (int) (i.operands - 1))) | |
4883 | { | |
4884 | i.error = mask_not_on_destination; | |
4885 | return 1; | |
4886 | } | |
4887 | ||
43234a1e L |
4888 | /* Check RC/SAE. */ |
4889 | if (i.rounding) | |
4890 | { | |
4891 | if ((i.rounding->type != saeonly | |
4892 | && !t->opcode_modifier.staticrounding) | |
4893 | || (i.rounding->type == saeonly | |
4894 | && (t->opcode_modifier.staticrounding | |
4895 | || !t->opcode_modifier.sae))) | |
4896 | { | |
4897 | i.error = unsupported_rc_sae; | |
4898 | return 1; | |
4899 | } | |
4900 | /* If the instruction has several immediate operands and one of | |
4901 | them is rounding, the rounding operand should be the last | |
4902 | immediate operand. */ | |
4903 | if (i.imm_operands > 1 | |
4904 | && i.rounding->operand != (int) (i.imm_operands - 1)) | |
7bab8ab5 | 4905 | { |
43234a1e | 4906 | i.error = rc_sae_operand_not_last_imm; |
7bab8ab5 JB |
4907 | return 1; |
4908 | } | |
6c30d220 L |
4909 | } |
4910 | ||
43234a1e | 4911 | /* Check vector Disp8 operand. */ |
b5014f7a JB |
4912 | if (t->opcode_modifier.disp8memshift |
4913 | && i.disp_encoding != disp_encoding_32bit) | |
43234a1e L |
4914 | { |
4915 | if (i.broadcast) | |
4916 | i.memshift = t->opcode_modifier.vecesize ? 3 : 2; | |
4917 | else | |
4918 | i.memshift = t->opcode_modifier.disp8memshift; | |
4919 | ||
4920 | for (op = 0; op < i.operands; op++) | |
4921 | if (operand_type_check (i.types[op], disp) | |
4922 | && i.op[op].disps->X_op == O_constant) | |
4923 | { | |
b5014f7a | 4924 | if (fits_in_disp8 (i.op[op].disps->X_add_number)) |
43234a1e | 4925 | { |
b5014f7a JB |
4926 | i.types[op].bitfield.disp8 = 1; |
4927 | return 0; | |
43234a1e | 4928 | } |
b5014f7a | 4929 | i.types[op].bitfield.disp8 = 0; |
43234a1e L |
4930 | } |
4931 | } | |
b5014f7a JB |
4932 | |
4933 | i.memshift = 0; | |
43234a1e | 4934 | |
6c30d220 L |
4935 | return 0; |
4936 | } | |
4937 | ||
43f3e2ee | 4938 | /* Check if operands are valid for the instruction. Update VEX |
a683cc34 SP |
4939 | operand types. */ |
4940 | ||
4941 | static int | |
4942 | VEX_check_operands (const insn_template *t) | |
4943 | { | |
86fa6981 | 4944 | if (i.vec_encoding == vex_encoding_evex) |
43234a1e | 4945 | { |
86fa6981 L |
4946 | /* This instruction must be encoded with EVEX prefix. */ |
4947 | if (!t->opcode_modifier.evex) | |
4948 | { | |
4949 | i.error = unsupported; | |
4950 | return 1; | |
4951 | } | |
4952 | return 0; | |
43234a1e L |
4953 | } |
4954 | ||
a683cc34 | 4955 | if (!t->opcode_modifier.vex) |
86fa6981 L |
4956 | { |
4957 | /* This instruction template doesn't have VEX prefix. */ | |
4958 | if (i.vec_encoding != vex_encoding_default) | |
4959 | { | |
4960 | i.error = unsupported; | |
4961 | return 1; | |
4962 | } | |
4963 | return 0; | |
4964 | } | |
a683cc34 SP |
4965 | |
4966 | /* Only check VEX_Imm4, which must be the first operand. */ | |
4967 | if (t->operand_types[0].bitfield.vec_imm4) | |
4968 | { | |
4969 | if (i.op[0].imms->X_op != O_constant | |
4970 | || !fits_in_imm4 (i.op[0].imms->X_add_number)) | |
891edac4 | 4971 | { |
a65babc9 | 4972 | i.error = bad_imm4; |
891edac4 L |
4973 | return 1; |
4974 | } | |
a683cc34 SP |
4975 | |
4976 | /* Turn off Imm8 so that update_imm won't complain. */ | |
4977 | i.types[0] = vec_imm4; | |
4978 | } | |
4979 | ||
4980 | return 0; | |
4981 | } | |
4982 | ||
d3ce72d0 | 4983 | static const insn_template * |
83b16ac6 | 4984 | match_template (char mnem_suffix) |
29b0f896 AM |
4985 | { |
4986 | /* Points to template once we've found it. */ | |
d3ce72d0 | 4987 | const insn_template *t; |
40fb9820 | 4988 | i386_operand_type overlap0, overlap1, overlap2, overlap3; |
c0f3af97 | 4989 | i386_operand_type overlap4; |
29b0f896 | 4990 | unsigned int found_reverse_match; |
83b16ac6 | 4991 | i386_opcode_modifier suffix_check, mnemsuf_check; |
40fb9820 | 4992 | i386_operand_type operand_types [MAX_OPERANDS]; |
539e75ad | 4993 | int addr_prefix_disp; |
a5c311ca | 4994 | unsigned int j; |
3629bb00 | 4995 | unsigned int found_cpu_match; |
45664ddb | 4996 | unsigned int check_register; |
5614d22c | 4997 | enum i386_error specific_error = 0; |
29b0f896 | 4998 | |
c0f3af97 L |
4999 | #if MAX_OPERANDS != 5 |
5000 | # error "MAX_OPERANDS must be 5." | |
f48ff2ae L |
5001 | #endif |
5002 | ||
29b0f896 | 5003 | found_reverse_match = 0; |
539e75ad | 5004 | addr_prefix_disp = -1; |
40fb9820 L |
5005 | |
5006 | memset (&suffix_check, 0, sizeof (suffix_check)); | |
5007 | if (i.suffix == BYTE_MNEM_SUFFIX) | |
5008 | suffix_check.no_bsuf = 1; | |
5009 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
5010 | suffix_check.no_wsuf = 1; | |
5011 | else if (i.suffix == SHORT_MNEM_SUFFIX) | |
5012 | suffix_check.no_ssuf = 1; | |
5013 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
5014 | suffix_check.no_lsuf = 1; | |
5015 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
5016 | suffix_check.no_qsuf = 1; | |
5017 | else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX) | |
7ce189b3 | 5018 | suffix_check.no_ldsuf = 1; |
29b0f896 | 5019 | |
83b16ac6 JB |
5020 | memset (&mnemsuf_check, 0, sizeof (mnemsuf_check)); |
5021 | if (intel_syntax) | |
5022 | { | |
5023 | switch (mnem_suffix) | |
5024 | { | |
5025 | case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break; | |
5026 | case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break; | |
5027 | case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break; | |
5028 | case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break; | |
5029 | case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break; | |
5030 | } | |
5031 | } | |
5032 | ||
01559ecc L |
5033 | /* Must have right number of operands. */ |
5034 | i.error = number_of_operands_mismatch; | |
5035 | ||
45aa61fe | 5036 | for (t = current_templates->start; t < current_templates->end; t++) |
29b0f896 | 5037 | { |
539e75ad L |
5038 | addr_prefix_disp = -1; |
5039 | ||
29b0f896 AM |
5040 | if (i.operands != t->operands) |
5041 | continue; | |
5042 | ||
50aecf8c | 5043 | /* Check processor support. */ |
a65babc9 | 5044 | i.error = unsupported; |
c0f3af97 L |
5045 | found_cpu_match = (cpu_flags_match (t) |
5046 | == CPU_FLAGS_PERFECT_MATCH); | |
50aecf8c L |
5047 | if (!found_cpu_match) |
5048 | continue; | |
5049 | ||
e1d4d893 | 5050 | /* Check old gcc support. */ |
a65babc9 | 5051 | i.error = old_gcc_only; |
e1d4d893 L |
5052 | if (!old_gcc && t->opcode_modifier.oldgcc) |
5053 | continue; | |
5054 | ||
5055 | /* Check AT&T mnemonic. */ | |
a65babc9 | 5056 | i.error = unsupported_with_intel_mnemonic; |
e1d4d893 | 5057 | if (intel_mnemonic && t->opcode_modifier.attmnemonic) |
1efbbeb4 L |
5058 | continue; |
5059 | ||
e92bae62 | 5060 | /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */ |
a65babc9 | 5061 | i.error = unsupported_syntax; |
5c07affc | 5062 | if ((intel_syntax && t->opcode_modifier.attsyntax) |
e92bae62 L |
5063 | || (!intel_syntax && t->opcode_modifier.intelsyntax) |
5064 | || (intel64 && t->opcode_modifier.amd64) | |
5065 | || (!intel64 && t->opcode_modifier.intel64)) | |
1efbbeb4 L |
5066 | continue; |
5067 | ||
20592a94 | 5068 | /* Check the suffix, except for some instructions in intel mode. */ |
a65babc9 | 5069 | i.error = invalid_instruction_suffix; |
567e4e96 L |
5070 | if ((!intel_syntax || !t->opcode_modifier.ignoresize) |
5071 | && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf) | |
5072 | || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf) | |
5073 | || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf) | |
5074 | || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf) | |
5075 | || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf) | |
5076 | || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf))) | |
29b0f896 | 5077 | continue; |
83b16ac6 JB |
5078 | /* In Intel mode all mnemonic suffixes must be explicitly allowed. */ |
5079 | if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf) | |
5080 | || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf) | |
5081 | || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf) | |
5082 | || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf) | |
5083 | || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf) | |
5084 | || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf)) | |
5085 | continue; | |
29b0f896 | 5086 | |
5c07affc | 5087 | if (!operand_size_match (t)) |
7d5e4556 | 5088 | continue; |
539e75ad | 5089 | |
5c07affc L |
5090 | for (j = 0; j < MAX_OPERANDS; j++) |
5091 | operand_types[j] = t->operand_types[j]; | |
5092 | ||
45aa61fe AM |
5093 | /* In general, don't allow 64-bit operands in 32-bit mode. */ |
5094 | if (i.suffix == QWORD_MNEM_SUFFIX | |
5095 | && flag_code != CODE_64BIT | |
5096 | && (intel_syntax | |
40fb9820 | 5097 | ? (!t->opcode_modifier.ignoresize |
45aa61fe AM |
5098 | && !intel_float_operand (t->name)) |
5099 | : intel_float_operand (t->name) != 2) | |
40fb9820 | 5100 | && ((!operand_types[0].bitfield.regmmx |
1b54b8d7 | 5101 | && !operand_types[0].bitfield.regsimd) |
40fb9820 | 5102 | || (!operand_types[t->operands > 1].bitfield.regmmx |
1b54b8d7 | 5103 | && !operand_types[t->operands > 1].bitfield.regsimd)) |
45aa61fe AM |
5104 | && (t->base_opcode != 0x0fc7 |
5105 | || t->extension_opcode != 1 /* cmpxchg8b */)) | |
5106 | continue; | |
5107 | ||
192dc9c6 JB |
5108 | /* In general, don't allow 32-bit operands on pre-386. */ |
5109 | else if (i.suffix == LONG_MNEM_SUFFIX | |
5110 | && !cpu_arch_flags.bitfield.cpui386 | |
5111 | && (intel_syntax | |
5112 | ? (!t->opcode_modifier.ignoresize | |
5113 | && !intel_float_operand (t->name)) | |
5114 | : intel_float_operand (t->name) != 2) | |
5115 | && ((!operand_types[0].bitfield.regmmx | |
1b54b8d7 | 5116 | && !operand_types[0].bitfield.regsimd) |
192dc9c6 | 5117 | || (!operand_types[t->operands > 1].bitfield.regmmx |
1b54b8d7 | 5118 | && !operand_types[t->operands > 1].bitfield.regsimd))) |
192dc9c6 JB |
5119 | continue; |
5120 | ||
29b0f896 | 5121 | /* Do not verify operands when there are none. */ |
50aecf8c | 5122 | else |
29b0f896 | 5123 | { |
c6fb90c8 | 5124 | if (!t->operands) |
2dbab7d5 L |
5125 | /* We've found a match; break out of loop. */ |
5126 | break; | |
29b0f896 | 5127 | } |
252b5132 | 5128 | |
539e75ad L |
5129 | /* Address size prefix will turn Disp64/Disp32/Disp16 operand |
5130 | into Disp32/Disp16/Disp32 operand. */ | |
5131 | if (i.prefix[ADDR_PREFIX] != 0) | |
5132 | { | |
40fb9820 | 5133 | /* There should be only one Disp operand. */ |
539e75ad L |
5134 | switch (flag_code) |
5135 | { | |
5136 | case CODE_16BIT: | |
40fb9820 L |
5137 | for (j = 0; j < MAX_OPERANDS; j++) |
5138 | { | |
5139 | if (operand_types[j].bitfield.disp16) | |
5140 | { | |
5141 | addr_prefix_disp = j; | |
5142 | operand_types[j].bitfield.disp32 = 1; | |
5143 | operand_types[j].bitfield.disp16 = 0; | |
5144 | break; | |
5145 | } | |
5146 | } | |
539e75ad L |
5147 | break; |
5148 | case CODE_32BIT: | |
40fb9820 L |
5149 | for (j = 0; j < MAX_OPERANDS; j++) |
5150 | { | |
5151 | if (operand_types[j].bitfield.disp32) | |
5152 | { | |
5153 | addr_prefix_disp = j; | |
5154 | operand_types[j].bitfield.disp32 = 0; | |
5155 | operand_types[j].bitfield.disp16 = 1; | |
5156 | break; | |
5157 | } | |
5158 | } | |
539e75ad L |
5159 | break; |
5160 | case CODE_64BIT: | |
40fb9820 L |
5161 | for (j = 0; j < MAX_OPERANDS; j++) |
5162 | { | |
5163 | if (operand_types[j].bitfield.disp64) | |
5164 | { | |
5165 | addr_prefix_disp = j; | |
5166 | operand_types[j].bitfield.disp64 = 0; | |
5167 | operand_types[j].bitfield.disp32 = 1; | |
5168 | break; | |
5169 | } | |
5170 | } | |
539e75ad L |
5171 | break; |
5172 | } | |
539e75ad L |
5173 | } |
5174 | ||
02a86693 L |
5175 | /* Force 0x8b encoding for "mov foo@GOT, %eax". */ |
5176 | if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0) | |
5177 | continue; | |
5178 | ||
56ffb741 L |
5179 | /* We check register size if needed. */ |
5180 | check_register = t->opcode_modifier.checkregsize; | |
c6fb90c8 | 5181 | overlap0 = operand_type_and (i.types[0], operand_types[0]); |
29b0f896 AM |
5182 | switch (t->operands) |
5183 | { | |
5184 | case 1: | |
40fb9820 | 5185 | if (!operand_type_match (overlap0, i.types[0])) |
29b0f896 AM |
5186 | continue; |
5187 | break; | |
5188 | case 2: | |
33eaf5de | 5189 | /* xchg %eax, %eax is a special case. It is an alias for nop |
8b38ad71 L |
5190 | only in 32bit mode and we can use opcode 0x90. In 64bit |
5191 | mode, we can't use 0x90 for xchg %eax, %eax since it should | |
5192 | zero-extend %eax to %rax. */ | |
5193 | if (flag_code == CODE_64BIT | |
5194 | && t->base_opcode == 0x90 | |
0dfbf9d7 L |
5195 | && operand_type_equal (&i.types [0], &acc32) |
5196 | && operand_type_equal (&i.types [1], &acc32)) | |
8b38ad71 | 5197 | continue; |
86fa6981 L |
5198 | /* If we want store form, we reverse direction of operands. */ |
5199 | if (i.dir_encoding == dir_encoding_store | |
5200 | && t->opcode_modifier.d) | |
5201 | goto check_reverse; | |
1a0670f3 | 5202 | /* Fall through. */ |
b6169b20 | 5203 | |
29b0f896 | 5204 | case 3: |
86fa6981 L |
5205 | /* If we want store form, we skip the current load. */ |
5206 | if (i.dir_encoding == dir_encoding_store | |
5207 | && i.mem_operands == 0 | |
5208 | && t->opcode_modifier.load) | |
fa99fab2 | 5209 | continue; |
1a0670f3 | 5210 | /* Fall through. */ |
f48ff2ae | 5211 | case 4: |
c0f3af97 | 5212 | case 5: |
c6fb90c8 | 5213 | overlap1 = operand_type_and (i.types[1], operand_types[1]); |
40fb9820 L |
5214 | if (!operand_type_match (overlap0, i.types[0]) |
5215 | || !operand_type_match (overlap1, i.types[1]) | |
45664ddb | 5216 | || (check_register |
dc821c5f | 5217 | && !operand_type_register_match (i.types[0], |
40fb9820 | 5218 | operand_types[0], |
dc821c5f | 5219 | i.types[1], |
40fb9820 | 5220 | operand_types[1]))) |
29b0f896 AM |
5221 | { |
5222 | /* Check if other direction is valid ... */ | |
40fb9820 | 5223 | if (!t->opcode_modifier.d && !t->opcode_modifier.floatd) |
29b0f896 AM |
5224 | continue; |
5225 | ||
b6169b20 | 5226 | check_reverse: |
29b0f896 | 5227 | /* Try reversing direction of operands. */ |
c6fb90c8 L |
5228 | overlap0 = operand_type_and (i.types[0], operand_types[1]); |
5229 | overlap1 = operand_type_and (i.types[1], operand_types[0]); | |
40fb9820 L |
5230 | if (!operand_type_match (overlap0, i.types[0]) |
5231 | || !operand_type_match (overlap1, i.types[1]) | |
45664ddb | 5232 | || (check_register |
dc821c5f | 5233 | && !operand_type_register_match (i.types[0], |
45664ddb | 5234 | operand_types[1], |
45664ddb L |
5235 | i.types[1], |
5236 | operand_types[0]))) | |
29b0f896 AM |
5237 | { |
5238 | /* Does not match either direction. */ | |
5239 | continue; | |
5240 | } | |
5241 | /* found_reverse_match holds which of D or FloatDR | |
5242 | we've found. */ | |
40fb9820 | 5243 | if (t->opcode_modifier.d) |
8a2ed489 | 5244 | found_reverse_match = Opcode_D; |
40fb9820 | 5245 | else if (t->opcode_modifier.floatd) |
8a2ed489 L |
5246 | found_reverse_match = Opcode_FloatD; |
5247 | else | |
5248 | found_reverse_match = 0; | |
40fb9820 | 5249 | if (t->opcode_modifier.floatr) |
8a2ed489 | 5250 | found_reverse_match |= Opcode_FloatR; |
29b0f896 | 5251 | } |
f48ff2ae | 5252 | else |
29b0f896 | 5253 | { |
f48ff2ae | 5254 | /* Found a forward 2 operand match here. */ |
d1cbb4db L |
5255 | switch (t->operands) |
5256 | { | |
c0f3af97 L |
5257 | case 5: |
5258 | overlap4 = operand_type_and (i.types[4], | |
5259 | operand_types[4]); | |
1a0670f3 | 5260 | /* Fall through. */ |
d1cbb4db | 5261 | case 4: |
c6fb90c8 L |
5262 | overlap3 = operand_type_and (i.types[3], |
5263 | operand_types[3]); | |
1a0670f3 | 5264 | /* Fall through. */ |
d1cbb4db | 5265 | case 3: |
c6fb90c8 L |
5266 | overlap2 = operand_type_and (i.types[2], |
5267 | operand_types[2]); | |
d1cbb4db L |
5268 | break; |
5269 | } | |
29b0f896 | 5270 | |
f48ff2ae L |
5271 | switch (t->operands) |
5272 | { | |
c0f3af97 L |
5273 | case 5: |
5274 | if (!operand_type_match (overlap4, i.types[4]) | |
dc821c5f | 5275 | || !operand_type_register_match (i.types[3], |
c0f3af97 | 5276 | operand_types[3], |
c0f3af97 L |
5277 | i.types[4], |
5278 | operand_types[4])) | |
5279 | continue; | |
1a0670f3 | 5280 | /* Fall through. */ |
f48ff2ae | 5281 | case 4: |
40fb9820 | 5282 | if (!operand_type_match (overlap3, i.types[3]) |
45664ddb | 5283 | || (check_register |
dc821c5f | 5284 | && !operand_type_register_match (i.types[2], |
45664ddb | 5285 | operand_types[2], |
45664ddb L |
5286 | i.types[3], |
5287 | operand_types[3]))) | |
f48ff2ae | 5288 | continue; |
1a0670f3 | 5289 | /* Fall through. */ |
f48ff2ae L |
5290 | case 3: |
5291 | /* Here we make use of the fact that there are no | |
5292 | reverse match 3 operand instructions, and all 3 | |
5293 | operand instructions only need to be checked for | |
5294 | register consistency between operands 2 and 3. */ | |
40fb9820 | 5295 | if (!operand_type_match (overlap2, i.types[2]) |
45664ddb | 5296 | || (check_register |
dc821c5f | 5297 | && !operand_type_register_match (i.types[1], |
45664ddb | 5298 | operand_types[1], |
45664ddb L |
5299 | i.types[2], |
5300 | operand_types[2]))) | |
f48ff2ae L |
5301 | continue; |
5302 | break; | |
5303 | } | |
29b0f896 | 5304 | } |
f48ff2ae | 5305 | /* Found either forward/reverse 2, 3 or 4 operand match here: |
29b0f896 AM |
5306 | slip through to break. */ |
5307 | } | |
3629bb00 | 5308 | if (!found_cpu_match) |
29b0f896 AM |
5309 | { |
5310 | found_reverse_match = 0; | |
5311 | continue; | |
5312 | } | |
c0f3af97 | 5313 | |
5614d22c JB |
5314 | /* Check if vector and VEX operands are valid. */ |
5315 | if (check_VecOperands (t) || VEX_check_operands (t)) | |
5316 | { | |
5317 | specific_error = i.error; | |
5318 | continue; | |
5319 | } | |
a683cc34 | 5320 | |
29b0f896 AM |
5321 | /* We've found a match; break out of loop. */ |
5322 | break; | |
5323 | } | |
5324 | ||
5325 | if (t == current_templates->end) | |
5326 | { | |
5327 | /* We found no match. */ | |
a65babc9 | 5328 | const char *err_msg; |
5614d22c | 5329 | switch (specific_error ? specific_error : i.error) |
a65babc9 L |
5330 | { |
5331 | default: | |
5332 | abort (); | |
86e026a4 | 5333 | case operand_size_mismatch: |
a65babc9 L |
5334 | err_msg = _("operand size mismatch"); |
5335 | break; | |
5336 | case operand_type_mismatch: | |
5337 | err_msg = _("operand type mismatch"); | |
5338 | break; | |
5339 | case register_type_mismatch: | |
5340 | err_msg = _("register type mismatch"); | |
5341 | break; | |
5342 | case number_of_operands_mismatch: | |
5343 | err_msg = _("number of operands mismatch"); | |
5344 | break; | |
5345 | case invalid_instruction_suffix: | |
5346 | err_msg = _("invalid instruction suffix"); | |
5347 | break; | |
5348 | case bad_imm4: | |
4a2608e3 | 5349 | err_msg = _("constant doesn't fit in 4 bits"); |
a65babc9 L |
5350 | break; |
5351 | case old_gcc_only: | |
5352 | err_msg = _("only supported with old gcc"); | |
5353 | break; | |
5354 | case unsupported_with_intel_mnemonic: | |
5355 | err_msg = _("unsupported with Intel mnemonic"); | |
5356 | break; | |
5357 | case unsupported_syntax: | |
5358 | err_msg = _("unsupported syntax"); | |
5359 | break; | |
5360 | case unsupported: | |
35262a23 | 5361 | as_bad (_("unsupported instruction `%s'"), |
10efe3f6 L |
5362 | current_templates->start->name); |
5363 | return NULL; | |
6c30d220 L |
5364 | case invalid_vsib_address: |
5365 | err_msg = _("invalid VSIB address"); | |
5366 | break; | |
7bab8ab5 JB |
5367 | case invalid_vector_register_set: |
5368 | err_msg = _("mask, index, and destination registers must be distinct"); | |
5369 | break; | |
6c30d220 L |
5370 | case unsupported_vector_index_register: |
5371 | err_msg = _("unsupported vector index register"); | |
5372 | break; | |
43234a1e L |
5373 | case unsupported_broadcast: |
5374 | err_msg = _("unsupported broadcast"); | |
5375 | break; | |
5376 | case broadcast_not_on_src_operand: | |
5377 | err_msg = _("broadcast not on source memory operand"); | |
5378 | break; | |
5379 | case broadcast_needed: | |
5380 | err_msg = _("broadcast is needed for operand of such type"); | |
5381 | break; | |
5382 | case unsupported_masking: | |
5383 | err_msg = _("unsupported masking"); | |
5384 | break; | |
5385 | case mask_not_on_destination: | |
5386 | err_msg = _("mask not on destination operand"); | |
5387 | break; | |
5388 | case no_default_mask: | |
5389 | err_msg = _("default mask isn't allowed"); | |
5390 | break; | |
5391 | case unsupported_rc_sae: | |
5392 | err_msg = _("unsupported static rounding/sae"); | |
5393 | break; | |
5394 | case rc_sae_operand_not_last_imm: | |
5395 | if (intel_syntax) | |
5396 | err_msg = _("RC/SAE operand must precede immediate operands"); | |
5397 | else | |
5398 | err_msg = _("RC/SAE operand must follow immediate operands"); | |
5399 | break; | |
5400 | case invalid_register_operand: | |
5401 | err_msg = _("invalid register operand"); | |
5402 | break; | |
a65babc9 L |
5403 | } |
5404 | as_bad (_("%s for `%s'"), err_msg, | |
891edac4 | 5405 | current_templates->start->name); |
fa99fab2 | 5406 | return NULL; |
29b0f896 | 5407 | } |
252b5132 | 5408 | |
29b0f896 AM |
5409 | if (!quiet_warnings) |
5410 | { | |
5411 | if (!intel_syntax | |
40fb9820 L |
5412 | && (i.types[0].bitfield.jumpabsolute |
5413 | != operand_types[0].bitfield.jumpabsolute)) | |
29b0f896 AM |
5414 | { |
5415 | as_warn (_("indirect %s without `*'"), t->name); | |
5416 | } | |
5417 | ||
40fb9820 L |
5418 | if (t->opcode_modifier.isprefix |
5419 | && t->opcode_modifier.ignoresize) | |
29b0f896 AM |
5420 | { |
5421 | /* Warn them that a data or address size prefix doesn't | |
5422 | affect assembly of the next line of code. */ | |
5423 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
5424 | } | |
5425 | } | |
5426 | ||
5427 | /* Copy the template we found. */ | |
5428 | i.tm = *t; | |
539e75ad L |
5429 | |
5430 | if (addr_prefix_disp != -1) | |
5431 | i.tm.operand_types[addr_prefix_disp] | |
5432 | = operand_types[addr_prefix_disp]; | |
5433 | ||
29b0f896 AM |
5434 | if (found_reverse_match) |
5435 | { | |
5436 | /* If we found a reverse match we must alter the opcode | |
5437 | direction bit. found_reverse_match holds bits to change | |
5438 | (different for int & float insns). */ | |
5439 | ||
5440 | i.tm.base_opcode ^= found_reverse_match; | |
5441 | ||
539e75ad L |
5442 | i.tm.operand_types[0] = operand_types[1]; |
5443 | i.tm.operand_types[1] = operand_types[0]; | |
29b0f896 AM |
5444 | } |
5445 | ||
fa99fab2 | 5446 | return t; |
29b0f896 AM |
5447 | } |
5448 | ||
5449 | static int | |
e3bb37b5 | 5450 | check_string (void) |
29b0f896 | 5451 | { |
40fb9820 L |
5452 | int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1; |
5453 | if (i.tm.operand_types[mem_op].bitfield.esseg) | |
29b0f896 AM |
5454 | { |
5455 | if (i.seg[0] != NULL && i.seg[0] != &es) | |
5456 | { | |
a87af027 | 5457 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
29b0f896 | 5458 | i.tm.name, |
a87af027 JB |
5459 | mem_op + 1, |
5460 | register_prefix); | |
29b0f896 AM |
5461 | return 0; |
5462 | } | |
5463 | /* There's only ever one segment override allowed per instruction. | |
5464 | This instruction possibly has a legal segment override on the | |
5465 | second operand, so copy the segment to where non-string | |
5466 | instructions store it, allowing common code. */ | |
5467 | i.seg[0] = i.seg[1]; | |
5468 | } | |
40fb9820 | 5469 | else if (i.tm.operand_types[mem_op + 1].bitfield.esseg) |
29b0f896 AM |
5470 | { |
5471 | if (i.seg[1] != NULL && i.seg[1] != &es) | |
5472 | { | |
a87af027 | 5473 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
29b0f896 | 5474 | i.tm.name, |
a87af027 JB |
5475 | mem_op + 2, |
5476 | register_prefix); | |
29b0f896 AM |
5477 | return 0; |
5478 | } | |
5479 | } | |
5480 | return 1; | |
5481 | } | |
5482 | ||
5483 | static int | |
543613e9 | 5484 | process_suffix (void) |
29b0f896 AM |
5485 | { |
5486 | /* If matched instruction specifies an explicit instruction mnemonic | |
5487 | suffix, use it. */ | |
40fb9820 L |
5488 | if (i.tm.opcode_modifier.size16) |
5489 | i.suffix = WORD_MNEM_SUFFIX; | |
5490 | else if (i.tm.opcode_modifier.size32) | |
5491 | i.suffix = LONG_MNEM_SUFFIX; | |
5492 | else if (i.tm.opcode_modifier.size64) | |
5493 | i.suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 AM |
5494 | else if (i.reg_operands) |
5495 | { | |
5496 | /* If there's no instruction mnemonic suffix we try to invent one | |
5497 | based on register operands. */ | |
5498 | if (!i.suffix) | |
5499 | { | |
5500 | /* We take i.suffix from the last register operand specified, | |
5501 | Destination register type is more significant than source | |
381d071f L |
5502 | register type. crc32 in SSE4.2 prefers source register |
5503 | type. */ | |
5504 | if (i.tm.base_opcode == 0xf20f38f1) | |
5505 | { | |
dc821c5f | 5506 | if (i.types[0].bitfield.reg && i.types[0].bitfield.word) |
40fb9820 | 5507 | i.suffix = WORD_MNEM_SUFFIX; |
dc821c5f | 5508 | else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword) |
40fb9820 | 5509 | i.suffix = LONG_MNEM_SUFFIX; |
dc821c5f | 5510 | else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword) |
40fb9820 | 5511 | i.suffix = QWORD_MNEM_SUFFIX; |
381d071f | 5512 | } |
9344ff29 | 5513 | else if (i.tm.base_opcode == 0xf20f38f0) |
20592a94 | 5514 | { |
dc821c5f | 5515 | if (i.types[0].bitfield.reg && i.types[0].bitfield.byte) |
20592a94 L |
5516 | i.suffix = BYTE_MNEM_SUFFIX; |
5517 | } | |
381d071f L |
5518 | |
5519 | if (!i.suffix) | |
5520 | { | |
5521 | int op; | |
5522 | ||
20592a94 L |
5523 | if (i.tm.base_opcode == 0xf20f38f1 |
5524 | || i.tm.base_opcode == 0xf20f38f0) | |
5525 | { | |
5526 | /* We have to know the operand size for crc32. */ | |
5527 | as_bad (_("ambiguous memory operand size for `%s`"), | |
5528 | i.tm.name); | |
5529 | return 0; | |
5530 | } | |
5531 | ||
381d071f | 5532 | for (op = i.operands; --op >= 0;) |
b76bc5d5 JB |
5533 | if (!i.tm.operand_types[op].bitfield.inoutportreg |
5534 | && !i.tm.operand_types[op].bitfield.shiftcount) | |
381d071f | 5535 | { |
dc821c5f | 5536 | if (i.types[op].bitfield.reg && i.types[op].bitfield.byte) |
40fb9820 L |
5537 | { |
5538 | i.suffix = BYTE_MNEM_SUFFIX; | |
5539 | break; | |
5540 | } | |
dc821c5f | 5541 | if (i.types[op].bitfield.reg && i.types[op].bitfield.word) |
40fb9820 L |
5542 | { |
5543 | i.suffix = WORD_MNEM_SUFFIX; | |
5544 | break; | |
5545 | } | |
dc821c5f | 5546 | if (i.types[op].bitfield.reg && i.types[op].bitfield.dword) |
40fb9820 L |
5547 | { |
5548 | i.suffix = LONG_MNEM_SUFFIX; | |
5549 | break; | |
5550 | } | |
dc821c5f | 5551 | if (i.types[op].bitfield.reg && i.types[op].bitfield.qword) |
40fb9820 L |
5552 | { |
5553 | i.suffix = QWORD_MNEM_SUFFIX; | |
5554 | break; | |
5555 | } | |
381d071f L |
5556 | } |
5557 | } | |
29b0f896 AM |
5558 | } |
5559 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
5560 | { | |
2eb952a4 L |
5561 | if (intel_syntax |
5562 | && i.tm.opcode_modifier.ignoresize | |
5563 | && i.tm.opcode_modifier.no_bsuf) | |
5564 | i.suffix = 0; | |
5565 | else if (!check_byte_reg ()) | |
29b0f896 AM |
5566 | return 0; |
5567 | } | |
5568 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
5569 | { | |
2eb952a4 L |
5570 | if (intel_syntax |
5571 | && i.tm.opcode_modifier.ignoresize | |
5572 | && i.tm.opcode_modifier.no_lsuf) | |
5573 | i.suffix = 0; | |
5574 | else if (!check_long_reg ()) | |
29b0f896 AM |
5575 | return 0; |
5576 | } | |
5577 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
5578 | { | |
955e1e6a L |
5579 | if (intel_syntax |
5580 | && i.tm.opcode_modifier.ignoresize | |
5581 | && i.tm.opcode_modifier.no_qsuf) | |
5582 | i.suffix = 0; | |
5583 | else if (!check_qword_reg ()) | |
29b0f896 AM |
5584 | return 0; |
5585 | } | |
5586 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
5587 | { | |
2eb952a4 L |
5588 | if (intel_syntax |
5589 | && i.tm.opcode_modifier.ignoresize | |
5590 | && i.tm.opcode_modifier.no_wsuf) | |
5591 | i.suffix = 0; | |
5592 | else if (!check_word_reg ()) | |
29b0f896 AM |
5593 | return 0; |
5594 | } | |
c0f3af97 | 5595 | else if (i.suffix == XMMWORD_MNEM_SUFFIX |
43234a1e L |
5596 | || i.suffix == YMMWORD_MNEM_SUFFIX |
5597 | || i.suffix == ZMMWORD_MNEM_SUFFIX) | |
582d5edd | 5598 | { |
43234a1e | 5599 | /* Skip if the instruction has x/y/z suffix. match_template |
582d5edd L |
5600 | should check if it is a valid suffix. */ |
5601 | } | |
40fb9820 | 5602 | else if (intel_syntax && i.tm.opcode_modifier.ignoresize) |
29b0f896 AM |
5603 | /* Do nothing if the instruction is going to ignore the prefix. */ |
5604 | ; | |
5605 | else | |
5606 | abort (); | |
5607 | } | |
40fb9820 | 5608 | else if (i.tm.opcode_modifier.defaultsize |
9306ca4a JB |
5609 | && !i.suffix |
5610 | /* exclude fldenv/frstor/fsave/fstenv */ | |
40fb9820 | 5611 | && i.tm.opcode_modifier.no_ssuf) |
29b0f896 AM |
5612 | { |
5613 | i.suffix = stackop_size; | |
5614 | } | |
9306ca4a JB |
5615 | else if (intel_syntax |
5616 | && !i.suffix | |
40fb9820 L |
5617 | && (i.tm.operand_types[0].bitfield.jumpabsolute |
5618 | || i.tm.opcode_modifier.jumpbyte | |
5619 | || i.tm.opcode_modifier.jumpintersegment | |
64e74474 AM |
5620 | || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */ |
5621 | && i.tm.extension_opcode <= 3))) | |
9306ca4a JB |
5622 | { |
5623 | switch (flag_code) | |
5624 | { | |
5625 | case CODE_64BIT: | |
40fb9820 | 5626 | if (!i.tm.opcode_modifier.no_qsuf) |
9306ca4a JB |
5627 | { |
5628 | i.suffix = QWORD_MNEM_SUFFIX; | |
5629 | break; | |
5630 | } | |
1a0670f3 | 5631 | /* Fall through. */ |
9306ca4a | 5632 | case CODE_32BIT: |
40fb9820 | 5633 | if (!i.tm.opcode_modifier.no_lsuf) |
9306ca4a JB |
5634 | i.suffix = LONG_MNEM_SUFFIX; |
5635 | break; | |
5636 | case CODE_16BIT: | |
40fb9820 | 5637 | if (!i.tm.opcode_modifier.no_wsuf) |
9306ca4a JB |
5638 | i.suffix = WORD_MNEM_SUFFIX; |
5639 | break; | |
5640 | } | |
5641 | } | |
252b5132 | 5642 | |
9306ca4a | 5643 | if (!i.suffix) |
29b0f896 | 5644 | { |
9306ca4a JB |
5645 | if (!intel_syntax) |
5646 | { | |
40fb9820 | 5647 | if (i.tm.opcode_modifier.w) |
9306ca4a | 5648 | { |
4eed87de AM |
5649 | as_bad (_("no instruction mnemonic suffix given and " |
5650 | "no register operands; can't size instruction")); | |
9306ca4a JB |
5651 | return 0; |
5652 | } | |
5653 | } | |
5654 | else | |
5655 | { | |
40fb9820 | 5656 | unsigned int suffixes; |
7ab9ffdd | 5657 | |
40fb9820 L |
5658 | suffixes = !i.tm.opcode_modifier.no_bsuf; |
5659 | if (!i.tm.opcode_modifier.no_wsuf) | |
5660 | suffixes |= 1 << 1; | |
5661 | if (!i.tm.opcode_modifier.no_lsuf) | |
5662 | suffixes |= 1 << 2; | |
fc4adea1 | 5663 | if (!i.tm.opcode_modifier.no_ldsuf) |
40fb9820 L |
5664 | suffixes |= 1 << 3; |
5665 | if (!i.tm.opcode_modifier.no_ssuf) | |
5666 | suffixes |= 1 << 4; | |
c2b9da16 | 5667 | if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf) |
40fb9820 L |
5668 | suffixes |= 1 << 5; |
5669 | ||
5670 | /* There are more than suffix matches. */ | |
5671 | if (i.tm.opcode_modifier.w | |
9306ca4a | 5672 | || ((suffixes & (suffixes - 1)) |
40fb9820 L |
5673 | && !i.tm.opcode_modifier.defaultsize |
5674 | && !i.tm.opcode_modifier.ignoresize)) | |
9306ca4a JB |
5675 | { |
5676 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); | |
5677 | return 0; | |
5678 | } | |
5679 | } | |
29b0f896 | 5680 | } |
252b5132 | 5681 | |
9306ca4a JB |
5682 | /* Change the opcode based on the operand size given by i.suffix; |
5683 | We don't need to change things for byte insns. */ | |
5684 | ||
582d5edd L |
5685 | if (i.suffix |
5686 | && i.suffix != BYTE_MNEM_SUFFIX | |
c0f3af97 | 5687 | && i.suffix != XMMWORD_MNEM_SUFFIX |
43234a1e L |
5688 | && i.suffix != YMMWORD_MNEM_SUFFIX |
5689 | && i.suffix != ZMMWORD_MNEM_SUFFIX) | |
29b0f896 AM |
5690 | { |
5691 | /* It's not a byte, select word/dword operation. */ | |
40fb9820 | 5692 | if (i.tm.opcode_modifier.w) |
29b0f896 | 5693 | { |
40fb9820 | 5694 | if (i.tm.opcode_modifier.shortform) |
29b0f896 AM |
5695 | i.tm.base_opcode |= 8; |
5696 | else | |
5697 | i.tm.base_opcode |= 1; | |
5698 | } | |
0f3f3d8b | 5699 | |
29b0f896 AM |
5700 | /* Now select between word & dword operations via the operand |
5701 | size prefix, except for instructions that will ignore this | |
5702 | prefix anyway. */ | |
ca61edf2 | 5703 | if (i.tm.opcode_modifier.addrprefixop0) |
cb712a9e | 5704 | { |
ca61edf2 L |
5705 | /* The address size override prefix changes the size of the |
5706 | first operand. */ | |
40fb9820 | 5707 | if ((flag_code == CODE_32BIT |
dc821c5f | 5708 | && i.op->regs[0].reg_type.bitfield.word) |
40fb9820 | 5709 | || (flag_code != CODE_32BIT |
dc821c5f | 5710 | && i.op->regs[0].reg_type.bitfield.dword)) |
cb712a9e L |
5711 | if (!add_prefix (ADDR_PREFIX_OPCODE)) |
5712 | return 0; | |
5713 | } | |
5714 | else if (i.suffix != QWORD_MNEM_SUFFIX | |
5715 | && i.suffix != LONG_DOUBLE_MNEM_SUFFIX | |
40fb9820 L |
5716 | && !i.tm.opcode_modifier.ignoresize |
5717 | && !i.tm.opcode_modifier.floatmf | |
cb712a9e L |
5718 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) |
5719 | || (flag_code == CODE_64BIT | |
40fb9820 | 5720 | && i.tm.opcode_modifier.jumpbyte))) |
24eab124 AM |
5721 | { |
5722 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
543613e9 | 5723 | |
40fb9820 | 5724 | if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */ |
29b0f896 | 5725 | prefix = ADDR_PREFIX_OPCODE; |
252b5132 | 5726 | |
29b0f896 AM |
5727 | if (!add_prefix (prefix)) |
5728 | return 0; | |
24eab124 | 5729 | } |
252b5132 | 5730 | |
29b0f896 AM |
5731 | /* Set mode64 for an operand. */ |
5732 | if (i.suffix == QWORD_MNEM_SUFFIX | |
9146926a | 5733 | && flag_code == CODE_64BIT |
40fb9820 | 5734 | && !i.tm.opcode_modifier.norex64) |
46e883c5 L |
5735 | { |
5736 | /* Special case for xchg %rax,%rax. It is NOP and doesn't | |
d9a5e5e5 L |
5737 | need rex64. cmpxchg8b is also a special case. */ |
5738 | if (! (i.operands == 2 | |
5739 | && i.tm.base_opcode == 0x90 | |
5740 | && i.tm.extension_opcode == None | |
0dfbf9d7 L |
5741 | && operand_type_equal (&i.types [0], &acc64) |
5742 | && operand_type_equal (&i.types [1], &acc64)) | |
d9a5e5e5 L |
5743 | && ! (i.operands == 1 |
5744 | && i.tm.base_opcode == 0xfc7 | |
5745 | && i.tm.extension_opcode == 1 | |
40fb9820 L |
5746 | && !operand_type_check (i.types [0], reg) |
5747 | && operand_type_check (i.types [0], anymem))) | |
f6bee062 | 5748 | i.rex |= REX_W; |
46e883c5 | 5749 | } |
3e73aa7c | 5750 | |
29b0f896 AM |
5751 | /* Size floating point instruction. */ |
5752 | if (i.suffix == LONG_MNEM_SUFFIX) | |
40fb9820 | 5753 | if (i.tm.opcode_modifier.floatmf) |
543613e9 | 5754 | i.tm.base_opcode ^= 4; |
29b0f896 | 5755 | } |
7ecd2f8b | 5756 | |
29b0f896 AM |
5757 | return 1; |
5758 | } | |
3e73aa7c | 5759 | |
29b0f896 | 5760 | static int |
543613e9 | 5761 | check_byte_reg (void) |
29b0f896 AM |
5762 | { |
5763 | int op; | |
543613e9 | 5764 | |
29b0f896 AM |
5765 | for (op = i.operands; --op >= 0;) |
5766 | { | |
dc821c5f JB |
5767 | /* Skip non-register operands. */ |
5768 | if (!i.types[op].bitfield.reg) | |
5769 | continue; | |
5770 | ||
29b0f896 AM |
5771 | /* If this is an eight bit register, it's OK. If it's the 16 or |
5772 | 32 bit version of an eight bit register, we will just use the | |
5773 | low portion, and that's OK too. */ | |
dc821c5f | 5774 | if (i.types[op].bitfield.byte) |
29b0f896 AM |
5775 | continue; |
5776 | ||
5a819eb9 JB |
5777 | /* I/O port address operands are OK too. */ |
5778 | if (i.tm.operand_types[op].bitfield.inoutportreg) | |
5779 | continue; | |
5780 | ||
9344ff29 L |
5781 | /* crc32 doesn't generate this warning. */ |
5782 | if (i.tm.base_opcode == 0xf20f38f0) | |
5783 | continue; | |
5784 | ||
dc821c5f JB |
5785 | if ((i.types[op].bitfield.word |
5786 | || i.types[op].bitfield.dword | |
5787 | || i.types[op].bitfield.qword) | |
5a819eb9 JB |
5788 | && i.op[op].regs->reg_num < 4 |
5789 | /* Prohibit these changes in 64bit mode, since the lowering | |
5790 | would be more complicated. */ | |
5791 | && flag_code != CODE_64BIT) | |
29b0f896 | 5792 | { |
29b0f896 | 5793 | #if REGISTER_WARNINGS |
5a819eb9 | 5794 | if (!quiet_warnings) |
a540244d L |
5795 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
5796 | register_prefix, | |
dc821c5f | 5797 | (i.op[op].regs + (i.types[op].bitfield.word |
29b0f896 AM |
5798 | ? REGNAM_AL - REGNAM_AX |
5799 | : REGNAM_AL - REGNAM_EAX))->reg_name, | |
a540244d | 5800 | register_prefix, |
29b0f896 AM |
5801 | i.op[op].regs->reg_name, |
5802 | i.suffix); | |
5803 | #endif | |
5804 | continue; | |
5805 | } | |
5806 | /* Any other register is bad. */ | |
dc821c5f | 5807 | if (i.types[op].bitfield.reg |
40fb9820 | 5808 | || i.types[op].bitfield.regmmx |
1b54b8d7 | 5809 | || i.types[op].bitfield.regsimd |
40fb9820 L |
5810 | || i.types[op].bitfield.sreg2 |
5811 | || i.types[op].bitfield.sreg3 | |
5812 | || i.types[op].bitfield.control | |
5813 | || i.types[op].bitfield.debug | |
ca0d63fe | 5814 | || i.types[op].bitfield.test) |
29b0f896 | 5815 | { |
a540244d L |
5816 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
5817 | register_prefix, | |
29b0f896 AM |
5818 | i.op[op].regs->reg_name, |
5819 | i.tm.name, | |
5820 | i.suffix); | |
5821 | return 0; | |
5822 | } | |
5823 | } | |
5824 | return 1; | |
5825 | } | |
5826 | ||
5827 | static int | |
e3bb37b5 | 5828 | check_long_reg (void) |
29b0f896 AM |
5829 | { |
5830 | int op; | |
5831 | ||
5832 | for (op = i.operands; --op >= 0;) | |
dc821c5f JB |
5833 | /* Skip non-register operands. */ |
5834 | if (!i.types[op].bitfield.reg) | |
5835 | continue; | |
29b0f896 AM |
5836 | /* Reject eight bit registers, except where the template requires |
5837 | them. (eg. movzb) */ | |
dc821c5f JB |
5838 | else if (i.types[op].bitfield.byte |
5839 | && (i.tm.operand_types[op].bitfield.reg | |
5840 | || i.tm.operand_types[op].bitfield.acc) | |
5841 | && (i.tm.operand_types[op].bitfield.word | |
5842 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 5843 | { |
a540244d L |
5844 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
5845 | register_prefix, | |
29b0f896 AM |
5846 | i.op[op].regs->reg_name, |
5847 | i.tm.name, | |
5848 | i.suffix); | |
5849 | return 0; | |
5850 | } | |
e4630f71 | 5851 | /* Warn if the e prefix on a general reg is missing. */ |
29b0f896 | 5852 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
dc821c5f JB |
5853 | && i.types[op].bitfield.word |
5854 | && (i.tm.operand_types[op].bitfield.reg | |
5855 | || i.tm.operand_types[op].bitfield.acc) | |
5856 | && i.tm.operand_types[op].bitfield.dword) | |
29b0f896 AM |
5857 | { |
5858 | /* Prohibit these changes in the 64bit mode, since the | |
5859 | lowering is more complicated. */ | |
5860 | if (flag_code == CODE_64BIT) | |
252b5132 | 5861 | { |
2b5d6a91 | 5862 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
2ca3ace5 | 5863 | register_prefix, i.op[op].regs->reg_name, |
29b0f896 AM |
5864 | i.suffix); |
5865 | return 0; | |
252b5132 | 5866 | } |
29b0f896 | 5867 | #if REGISTER_WARNINGS |
cecf1424 JB |
5868 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
5869 | register_prefix, | |
5870 | (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name, | |
5871 | register_prefix, i.op[op].regs->reg_name, i.suffix); | |
29b0f896 | 5872 | #endif |
252b5132 | 5873 | } |
e4630f71 | 5874 | /* Warn if the r prefix on a general reg is present. */ |
dc821c5f JB |
5875 | else if (i.types[op].bitfield.qword |
5876 | && (i.tm.operand_types[op].bitfield.reg | |
5877 | || i.tm.operand_types[op].bitfield.acc) | |
5878 | && i.tm.operand_types[op].bitfield.dword) | |
252b5132 | 5879 | { |
34828aad | 5880 | if (intel_syntax |
ca61edf2 | 5881 | && i.tm.opcode_modifier.toqword |
1b54b8d7 | 5882 | && !i.types[0].bitfield.regsimd) |
34828aad | 5883 | { |
ca61edf2 | 5884 | /* Convert to QWORD. We want REX byte. */ |
34828aad L |
5885 | i.suffix = QWORD_MNEM_SUFFIX; |
5886 | } | |
5887 | else | |
5888 | { | |
2b5d6a91 | 5889 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
5890 | register_prefix, i.op[op].regs->reg_name, |
5891 | i.suffix); | |
5892 | return 0; | |
5893 | } | |
29b0f896 AM |
5894 | } |
5895 | return 1; | |
5896 | } | |
252b5132 | 5897 | |
29b0f896 | 5898 | static int |
e3bb37b5 | 5899 | check_qword_reg (void) |
29b0f896 AM |
5900 | { |
5901 | int op; | |
252b5132 | 5902 | |
29b0f896 | 5903 | for (op = i.operands; --op >= 0; ) |
dc821c5f JB |
5904 | /* Skip non-register operands. */ |
5905 | if (!i.types[op].bitfield.reg) | |
5906 | continue; | |
29b0f896 AM |
5907 | /* Reject eight bit registers, except where the template requires |
5908 | them. (eg. movzb) */ | |
dc821c5f JB |
5909 | else if (i.types[op].bitfield.byte |
5910 | && (i.tm.operand_types[op].bitfield.reg | |
5911 | || i.tm.operand_types[op].bitfield.acc) | |
5912 | && (i.tm.operand_types[op].bitfield.word | |
5913 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 5914 | { |
a540244d L |
5915 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
5916 | register_prefix, | |
29b0f896 AM |
5917 | i.op[op].regs->reg_name, |
5918 | i.tm.name, | |
5919 | i.suffix); | |
5920 | return 0; | |
5921 | } | |
e4630f71 | 5922 | /* Warn if the r prefix on a general reg is missing. */ |
dc821c5f JB |
5923 | else if ((i.types[op].bitfield.word |
5924 | || i.types[op].bitfield.dword) | |
5925 | && (i.tm.operand_types[op].bitfield.reg | |
5926 | || i.tm.operand_types[op].bitfield.acc) | |
5927 | && i.tm.operand_types[op].bitfield.qword) | |
29b0f896 AM |
5928 | { |
5929 | /* Prohibit these changes in the 64bit mode, since the | |
5930 | lowering is more complicated. */ | |
34828aad | 5931 | if (intel_syntax |
ca61edf2 | 5932 | && i.tm.opcode_modifier.todword |
1b54b8d7 | 5933 | && !i.types[0].bitfield.regsimd) |
34828aad | 5934 | { |
ca61edf2 | 5935 | /* Convert to DWORD. We don't want REX byte. */ |
34828aad L |
5936 | i.suffix = LONG_MNEM_SUFFIX; |
5937 | } | |
5938 | else | |
5939 | { | |
2b5d6a91 | 5940 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
5941 | register_prefix, i.op[op].regs->reg_name, |
5942 | i.suffix); | |
5943 | return 0; | |
5944 | } | |
252b5132 | 5945 | } |
29b0f896 AM |
5946 | return 1; |
5947 | } | |
252b5132 | 5948 | |
29b0f896 | 5949 | static int |
e3bb37b5 | 5950 | check_word_reg (void) |
29b0f896 AM |
5951 | { |
5952 | int op; | |
5953 | for (op = i.operands; --op >= 0;) | |
dc821c5f JB |
5954 | /* Skip non-register operands. */ |
5955 | if (!i.types[op].bitfield.reg) | |
5956 | continue; | |
29b0f896 AM |
5957 | /* Reject eight bit registers, except where the template requires |
5958 | them. (eg. movzb) */ | |
dc821c5f JB |
5959 | else if (i.types[op].bitfield.byte |
5960 | && (i.tm.operand_types[op].bitfield.reg | |
5961 | || i.tm.operand_types[op].bitfield.acc) | |
5962 | && (i.tm.operand_types[op].bitfield.word | |
5963 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 5964 | { |
a540244d L |
5965 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
5966 | register_prefix, | |
29b0f896 AM |
5967 | i.op[op].regs->reg_name, |
5968 | i.tm.name, | |
5969 | i.suffix); | |
5970 | return 0; | |
5971 | } | |
e4630f71 | 5972 | /* Warn if the e or r prefix on a general reg is present. */ |
29b0f896 | 5973 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
dc821c5f JB |
5974 | && (i.types[op].bitfield.dword |
5975 | || i.types[op].bitfield.qword) | |
5976 | && (i.tm.operand_types[op].bitfield.reg | |
5977 | || i.tm.operand_types[op].bitfield.acc) | |
5978 | && i.tm.operand_types[op].bitfield.word) | |
252b5132 | 5979 | { |
29b0f896 AM |
5980 | /* Prohibit these changes in the 64bit mode, since the |
5981 | lowering is more complicated. */ | |
5982 | if (flag_code == CODE_64BIT) | |
252b5132 | 5983 | { |
2b5d6a91 | 5984 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
2ca3ace5 | 5985 | register_prefix, i.op[op].regs->reg_name, |
29b0f896 AM |
5986 | i.suffix); |
5987 | return 0; | |
252b5132 | 5988 | } |
29b0f896 | 5989 | #if REGISTER_WARNINGS |
cecf1424 JB |
5990 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
5991 | register_prefix, | |
5992 | (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name, | |
5993 | register_prefix, i.op[op].regs->reg_name, i.suffix); | |
29b0f896 AM |
5994 | #endif |
5995 | } | |
5996 | return 1; | |
5997 | } | |
252b5132 | 5998 | |
29b0f896 | 5999 | static int |
40fb9820 | 6000 | update_imm (unsigned int j) |
29b0f896 | 6001 | { |
bc0844ae | 6002 | i386_operand_type overlap = i.types[j]; |
40fb9820 L |
6003 | if ((overlap.bitfield.imm8 |
6004 | || overlap.bitfield.imm8s | |
6005 | || overlap.bitfield.imm16 | |
6006 | || overlap.bitfield.imm32 | |
6007 | || overlap.bitfield.imm32s | |
6008 | || overlap.bitfield.imm64) | |
0dfbf9d7 L |
6009 | && !operand_type_equal (&overlap, &imm8) |
6010 | && !operand_type_equal (&overlap, &imm8s) | |
6011 | && !operand_type_equal (&overlap, &imm16) | |
6012 | && !operand_type_equal (&overlap, &imm32) | |
6013 | && !operand_type_equal (&overlap, &imm32s) | |
6014 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 AM |
6015 | { |
6016 | if (i.suffix) | |
6017 | { | |
40fb9820 L |
6018 | i386_operand_type temp; |
6019 | ||
0dfbf9d7 | 6020 | operand_type_set (&temp, 0); |
7ab9ffdd | 6021 | if (i.suffix == BYTE_MNEM_SUFFIX) |
40fb9820 L |
6022 | { |
6023 | temp.bitfield.imm8 = overlap.bitfield.imm8; | |
6024 | temp.bitfield.imm8s = overlap.bitfield.imm8s; | |
6025 | } | |
6026 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
6027 | temp.bitfield.imm16 = overlap.bitfield.imm16; | |
6028 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
6029 | { | |
6030 | temp.bitfield.imm64 = overlap.bitfield.imm64; | |
6031 | temp.bitfield.imm32s = overlap.bitfield.imm32s; | |
6032 | } | |
6033 | else | |
6034 | temp.bitfield.imm32 = overlap.bitfield.imm32; | |
6035 | overlap = temp; | |
29b0f896 | 6036 | } |
0dfbf9d7 L |
6037 | else if (operand_type_equal (&overlap, &imm16_32_32s) |
6038 | || operand_type_equal (&overlap, &imm16_32) | |
6039 | || operand_type_equal (&overlap, &imm16_32s)) | |
29b0f896 | 6040 | { |
40fb9820 | 6041 | if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
65da13b5 | 6042 | overlap = imm16; |
40fb9820 | 6043 | else |
65da13b5 | 6044 | overlap = imm32s; |
29b0f896 | 6045 | } |
0dfbf9d7 L |
6046 | if (!operand_type_equal (&overlap, &imm8) |
6047 | && !operand_type_equal (&overlap, &imm8s) | |
6048 | && !operand_type_equal (&overlap, &imm16) | |
6049 | && !operand_type_equal (&overlap, &imm32) | |
6050 | && !operand_type_equal (&overlap, &imm32s) | |
6051 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 | 6052 | { |
4eed87de AM |
6053 | as_bad (_("no instruction mnemonic suffix given; " |
6054 | "can't determine immediate size")); | |
29b0f896 AM |
6055 | return 0; |
6056 | } | |
6057 | } | |
40fb9820 | 6058 | i.types[j] = overlap; |
29b0f896 | 6059 | |
40fb9820 L |
6060 | return 1; |
6061 | } | |
6062 | ||
6063 | static int | |
6064 | finalize_imm (void) | |
6065 | { | |
bc0844ae | 6066 | unsigned int j, n; |
29b0f896 | 6067 | |
bc0844ae L |
6068 | /* Update the first 2 immediate operands. */ |
6069 | n = i.operands > 2 ? 2 : i.operands; | |
6070 | if (n) | |
6071 | { | |
6072 | for (j = 0; j < n; j++) | |
6073 | if (update_imm (j) == 0) | |
6074 | return 0; | |
40fb9820 | 6075 | |
bc0844ae L |
6076 | /* The 3rd operand can't be immediate operand. */ |
6077 | gas_assert (operand_type_check (i.types[2], imm) == 0); | |
6078 | } | |
29b0f896 AM |
6079 | |
6080 | return 1; | |
6081 | } | |
6082 | ||
6083 | static int | |
e3bb37b5 | 6084 | process_operands (void) |
29b0f896 AM |
6085 | { |
6086 | /* Default segment register this instruction will use for memory | |
6087 | accesses. 0 means unknown. This is only for optimizing out | |
6088 | unnecessary segment overrides. */ | |
6089 | const seg_entry *default_seg = 0; | |
6090 | ||
2426c15f | 6091 | if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv) |
29b0f896 | 6092 | { |
91d6fa6a NC |
6093 | unsigned int dupl = i.operands; |
6094 | unsigned int dest = dupl - 1; | |
9fcfb3d7 L |
6095 | unsigned int j; |
6096 | ||
c0f3af97 | 6097 | /* The destination must be an xmm register. */ |
9c2799c2 | 6098 | gas_assert (i.reg_operands |
91d6fa6a | 6099 | && MAX_OPERANDS > dupl |
7ab9ffdd | 6100 | && operand_type_equal (&i.types[dest], ®xmm)); |
c0f3af97 | 6101 | |
1b54b8d7 JB |
6102 | if (i.tm.operand_types[0].bitfield.acc |
6103 | && i.tm.operand_types[0].bitfield.xmmword) | |
e2ec9d29 | 6104 | { |
8cd7925b | 6105 | if (i.tm.opcode_modifier.vexsources == VEX3SOURCES) |
c0f3af97 L |
6106 | { |
6107 | /* Keep xmm0 for instructions with VEX prefix and 3 | |
6108 | sources. */ | |
1b54b8d7 JB |
6109 | i.tm.operand_types[0].bitfield.acc = 0; |
6110 | i.tm.operand_types[0].bitfield.regsimd = 1; | |
c0f3af97 L |
6111 | goto duplicate; |
6112 | } | |
e2ec9d29 | 6113 | else |
c0f3af97 L |
6114 | { |
6115 | /* We remove the first xmm0 and keep the number of | |
6116 | operands unchanged, which in fact duplicates the | |
6117 | destination. */ | |
6118 | for (j = 1; j < i.operands; j++) | |
6119 | { | |
6120 | i.op[j - 1] = i.op[j]; | |
6121 | i.types[j - 1] = i.types[j]; | |
6122 | i.tm.operand_types[j - 1] = i.tm.operand_types[j]; | |
6123 | } | |
6124 | } | |
6125 | } | |
6126 | else if (i.tm.opcode_modifier.implicit1stxmm0) | |
7ab9ffdd | 6127 | { |
91d6fa6a | 6128 | gas_assert ((MAX_OPERANDS - 1) > dupl |
8cd7925b L |
6129 | && (i.tm.opcode_modifier.vexsources |
6130 | == VEX3SOURCES)); | |
c0f3af97 L |
6131 | |
6132 | /* Add the implicit xmm0 for instructions with VEX prefix | |
6133 | and 3 sources. */ | |
6134 | for (j = i.operands; j > 0; j--) | |
6135 | { | |
6136 | i.op[j] = i.op[j - 1]; | |
6137 | i.types[j] = i.types[j - 1]; | |
6138 | i.tm.operand_types[j] = i.tm.operand_types[j - 1]; | |
6139 | } | |
6140 | i.op[0].regs | |
6141 | = (const reg_entry *) hash_find (reg_hash, "xmm0"); | |
7ab9ffdd | 6142 | i.types[0] = regxmm; |
c0f3af97 L |
6143 | i.tm.operand_types[0] = regxmm; |
6144 | ||
6145 | i.operands += 2; | |
6146 | i.reg_operands += 2; | |
6147 | i.tm.operands += 2; | |
6148 | ||
91d6fa6a | 6149 | dupl++; |
c0f3af97 | 6150 | dest++; |
91d6fa6a NC |
6151 | i.op[dupl] = i.op[dest]; |
6152 | i.types[dupl] = i.types[dest]; | |
6153 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
e2ec9d29 | 6154 | } |
c0f3af97 L |
6155 | else |
6156 | { | |
6157 | duplicate: | |
6158 | i.operands++; | |
6159 | i.reg_operands++; | |
6160 | i.tm.operands++; | |
6161 | ||
91d6fa6a NC |
6162 | i.op[dupl] = i.op[dest]; |
6163 | i.types[dupl] = i.types[dest]; | |
6164 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
c0f3af97 L |
6165 | } |
6166 | ||
6167 | if (i.tm.opcode_modifier.immext) | |
6168 | process_immext (); | |
6169 | } | |
1b54b8d7 JB |
6170 | else if (i.tm.operand_types[0].bitfield.acc |
6171 | && i.tm.operand_types[0].bitfield.xmmword) | |
c0f3af97 L |
6172 | { |
6173 | unsigned int j; | |
6174 | ||
9fcfb3d7 L |
6175 | for (j = 1; j < i.operands; j++) |
6176 | { | |
6177 | i.op[j - 1] = i.op[j]; | |
6178 | i.types[j - 1] = i.types[j]; | |
6179 | ||
6180 | /* We need to adjust fields in i.tm since they are used by | |
6181 | build_modrm_byte. */ | |
6182 | i.tm.operand_types [j - 1] = i.tm.operand_types [j]; | |
6183 | } | |
6184 | ||
e2ec9d29 L |
6185 | i.operands--; |
6186 | i.reg_operands--; | |
e2ec9d29 L |
6187 | i.tm.operands--; |
6188 | } | |
920d2ddc IT |
6189 | else if (i.tm.opcode_modifier.implicitquadgroup) |
6190 | { | |
6191 | /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */ | |
10c17abd | 6192 | gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd); |
920d2ddc IT |
6193 | unsigned int regnum = register_number (i.op[1].regs); |
6194 | unsigned int first_reg_in_group = regnum & ~3; | |
6195 | unsigned int last_reg_in_group = first_reg_in_group + 3; | |
6196 | if (regnum != first_reg_in_group) { | |
6197 | as_warn (_("the second source register `%s%s' implicitly denotes" | |
6198 | " `%s%.3s%d' to `%s%.3s%d' source group in `%s'"), | |
6199 | register_prefix, i.op[1].regs->reg_name, | |
6200 | register_prefix, i.op[1].regs->reg_name, first_reg_in_group, | |
6201 | register_prefix, i.op[1].regs->reg_name, last_reg_in_group, | |
6202 | i.tm.name); | |
6203 | } | |
6204 | } | |
e2ec9d29 L |
6205 | else if (i.tm.opcode_modifier.regkludge) |
6206 | { | |
6207 | /* The imul $imm, %reg instruction is converted into | |
6208 | imul $imm, %reg, %reg, and the clr %reg instruction | |
6209 | is converted into xor %reg, %reg. */ | |
6210 | ||
6211 | unsigned int first_reg_op; | |
6212 | ||
6213 | if (operand_type_check (i.types[0], reg)) | |
6214 | first_reg_op = 0; | |
6215 | else | |
6216 | first_reg_op = 1; | |
6217 | /* Pretend we saw the extra register operand. */ | |
9c2799c2 | 6218 | gas_assert (i.reg_operands == 1 |
7ab9ffdd | 6219 | && i.op[first_reg_op + 1].regs == 0); |
e2ec9d29 L |
6220 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; |
6221 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
6222 | i.operands++; | |
6223 | i.reg_operands++; | |
29b0f896 AM |
6224 | } |
6225 | ||
40fb9820 | 6226 | if (i.tm.opcode_modifier.shortform) |
29b0f896 | 6227 | { |
40fb9820 L |
6228 | if (i.types[0].bitfield.sreg2 |
6229 | || i.types[0].bitfield.sreg3) | |
29b0f896 | 6230 | { |
4eed87de AM |
6231 | if (i.tm.base_opcode == POP_SEG_SHORT |
6232 | && i.op[0].regs->reg_num == 1) | |
29b0f896 | 6233 | { |
a87af027 | 6234 | as_bad (_("you can't `pop %scs'"), register_prefix); |
4eed87de | 6235 | return 0; |
29b0f896 | 6236 | } |
4eed87de AM |
6237 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); |
6238 | if ((i.op[0].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 6239 | i.rex |= REX_B; |
4eed87de AM |
6240 | } |
6241 | else | |
6242 | { | |
7ab9ffdd | 6243 | /* The register or float register operand is in operand |
85f10a01 | 6244 | 0 or 1. */ |
40fb9820 | 6245 | unsigned int op; |
7ab9ffdd | 6246 | |
ca0d63fe | 6247 | if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte) |
7ab9ffdd L |
6248 | || operand_type_check (i.types[0], reg)) |
6249 | op = 0; | |
6250 | else | |
6251 | op = 1; | |
4eed87de AM |
6252 | /* Register goes in low 3 bits of opcode. */ |
6253 | i.tm.base_opcode |= i.op[op].regs->reg_num; | |
6254 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 6255 | i.rex |= REX_B; |
40fb9820 | 6256 | if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 | 6257 | { |
4eed87de AM |
6258 | /* Warn about some common errors, but press on regardless. |
6259 | The first case can be generated by gcc (<= 2.8.1). */ | |
6260 | if (i.operands == 2) | |
6261 | { | |
6262 | /* Reversed arguments on faddp, fsubp, etc. */ | |
a540244d | 6263 | as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, |
d8a1b51e JB |
6264 | register_prefix, i.op[!intel_syntax].regs->reg_name, |
6265 | register_prefix, i.op[intel_syntax].regs->reg_name); | |
4eed87de AM |
6266 | } |
6267 | else | |
6268 | { | |
6269 | /* Extraneous `l' suffix on fp insn. */ | |
a540244d L |
6270 | as_warn (_("translating to `%s %s%s'"), i.tm.name, |
6271 | register_prefix, i.op[0].regs->reg_name); | |
4eed87de | 6272 | } |
29b0f896 AM |
6273 | } |
6274 | } | |
6275 | } | |
40fb9820 | 6276 | else if (i.tm.opcode_modifier.modrm) |
29b0f896 AM |
6277 | { |
6278 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
52271982 AM |
6279 | must be put into the modrm byte). Now, we make the modrm and |
6280 | index base bytes based on all the info we've collected. */ | |
29b0f896 AM |
6281 | |
6282 | default_seg = build_modrm_byte (); | |
6283 | } | |
8a2ed489 | 6284 | else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32) |
29b0f896 AM |
6285 | { |
6286 | default_seg = &ds; | |
6287 | } | |
40fb9820 | 6288 | else if (i.tm.opcode_modifier.isstring) |
29b0f896 AM |
6289 | { |
6290 | /* For the string instructions that allow a segment override | |
6291 | on one of their operands, the default segment is ds. */ | |
6292 | default_seg = &ds; | |
6293 | } | |
6294 | ||
75178d9d L |
6295 | if (i.tm.base_opcode == 0x8d /* lea */ |
6296 | && i.seg[0] | |
6297 | && !quiet_warnings) | |
30123838 | 6298 | as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); |
52271982 AM |
6299 | |
6300 | /* If a segment was explicitly specified, and the specified segment | |
6301 | is not the default, use an opcode prefix to select it. If we | |
6302 | never figured out what the default segment is, then default_seg | |
6303 | will be zero at this point, and the specified segment prefix will | |
6304 | always be used. */ | |
29b0f896 AM |
6305 | if ((i.seg[0]) && (i.seg[0] != default_seg)) |
6306 | { | |
6307 | if (!add_prefix (i.seg[0]->seg_prefix)) | |
6308 | return 0; | |
6309 | } | |
6310 | return 1; | |
6311 | } | |
6312 | ||
6313 | static const seg_entry * | |
e3bb37b5 | 6314 | build_modrm_byte (void) |
29b0f896 AM |
6315 | { |
6316 | const seg_entry *default_seg = 0; | |
c0f3af97 | 6317 | unsigned int source, dest; |
8cd7925b | 6318 | int vex_3_sources; |
c0f3af97 L |
6319 | |
6320 | /* The first operand of instructions with VEX prefix and 3 sources | |
6321 | must be VEX_Imm4. */ | |
8cd7925b | 6322 | vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES; |
c0f3af97 L |
6323 | if (vex_3_sources) |
6324 | { | |
91d6fa6a | 6325 | unsigned int nds, reg_slot; |
4c2c6516 | 6326 | expressionS *exp; |
c0f3af97 | 6327 | |
922d8de8 | 6328 | if (i.tm.opcode_modifier.veximmext |
a683cc34 SP |
6329 | && i.tm.opcode_modifier.immext) |
6330 | { | |
6331 | dest = i.operands - 2; | |
6332 | gas_assert (dest == 3); | |
6333 | } | |
922d8de8 | 6334 | else |
a683cc34 | 6335 | dest = i.operands - 1; |
c0f3af97 | 6336 | nds = dest - 1; |
922d8de8 | 6337 | |
a683cc34 SP |
6338 | /* There are 2 kinds of instructions: |
6339 | 1. 5 operands: 4 register operands or 3 register operands | |
6340 | plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and | |
43234a1e L |
6341 | VexW0 or VexW1. The destination must be either XMM, YMM or |
6342 | ZMM register. | |
a683cc34 SP |
6343 | 2. 4 operands: 4 register operands or 3 register operands |
6344 | plus 1 memory operand, VexXDS, and VexImmExt */ | |
922d8de8 | 6345 | gas_assert ((i.reg_operands == 4 |
a683cc34 SP |
6346 | || (i.reg_operands == 3 && i.mem_operands == 1)) |
6347 | && i.tm.opcode_modifier.vexvvvv == VEXXDS | |
6348 | && (i.tm.opcode_modifier.veximmext | |
6349 | || (i.imm_operands == 1 | |
6350 | && i.types[0].bitfield.vec_imm4 | |
6351 | && (i.tm.opcode_modifier.vexw == VEXW0 | |
6352 | || i.tm.opcode_modifier.vexw == VEXW1) | |
10c17abd | 6353 | && i.tm.operand_types[dest].bitfield.regsimd))); |
a683cc34 SP |
6354 | |
6355 | if (i.imm_operands == 0) | |
6356 | { | |
6357 | /* When there is no immediate operand, generate an 8bit | |
6358 | immediate operand to encode the first operand. */ | |
6359 | exp = &im_expressions[i.imm_operands++]; | |
6360 | i.op[i.operands].imms = exp; | |
6361 | i.types[i.operands] = imm8; | |
6362 | i.operands++; | |
6363 | /* If VexW1 is set, the first operand is the source and | |
6364 | the second operand is encoded in the immediate operand. */ | |
6365 | if (i.tm.opcode_modifier.vexw == VEXW1) | |
6366 | { | |
6367 | source = 0; | |
6368 | reg_slot = 1; | |
6369 | } | |
6370 | else | |
6371 | { | |
6372 | source = 1; | |
6373 | reg_slot = 0; | |
6374 | } | |
6375 | ||
6376 | /* FMA swaps REG and NDS. */ | |
6377 | if (i.tm.cpu_flags.bitfield.cpufma) | |
6378 | { | |
6379 | unsigned int tmp; | |
6380 | tmp = reg_slot; | |
6381 | reg_slot = nds; | |
6382 | nds = tmp; | |
6383 | } | |
6384 | ||
10c17abd | 6385 | gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd); |
a683cc34 | 6386 | exp->X_op = O_constant; |
4c692bc7 | 6387 | exp->X_add_number = register_number (i.op[reg_slot].regs) << 4; |
43234a1e L |
6388 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
6389 | } | |
922d8de8 | 6390 | else |
a683cc34 SP |
6391 | { |
6392 | unsigned int imm_slot; | |
6393 | ||
6394 | if (i.tm.opcode_modifier.vexw == VEXW0) | |
6395 | { | |
6396 | /* If VexW0 is set, the third operand is the source and | |
6397 | the second operand is encoded in the immediate | |
6398 | operand. */ | |
6399 | source = 2; | |
6400 | reg_slot = 1; | |
6401 | } | |
6402 | else | |
6403 | { | |
6404 | /* VexW1 is set, the second operand is the source and | |
6405 | the third operand is encoded in the immediate | |
6406 | operand. */ | |
6407 | source = 1; | |
6408 | reg_slot = 2; | |
6409 | } | |
6410 | ||
6411 | if (i.tm.opcode_modifier.immext) | |
6412 | { | |
33eaf5de | 6413 | /* When ImmExt is set, the immediate byte is the last |
a683cc34 SP |
6414 | operand. */ |
6415 | imm_slot = i.operands - 1; | |
6416 | source--; | |
6417 | reg_slot--; | |
6418 | } | |
6419 | else | |
6420 | { | |
6421 | imm_slot = 0; | |
6422 | ||
6423 | /* Turn on Imm8 so that output_imm will generate it. */ | |
6424 | i.types[imm_slot].bitfield.imm8 = 1; | |
6425 | } | |
6426 | ||
10c17abd | 6427 | gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd); |
a683cc34 | 6428 | i.op[imm_slot].imms->X_add_number |
4c692bc7 | 6429 | |= register_number (i.op[reg_slot].regs) << 4; |
43234a1e | 6430 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
a683cc34 SP |
6431 | } |
6432 | ||
10c17abd | 6433 | gas_assert (i.tm.operand_types[nds].bitfield.regsimd); |
dae39acc | 6434 | i.vex.register_specifier = i.op[nds].regs; |
c0f3af97 L |
6435 | } |
6436 | else | |
6437 | source = dest = 0; | |
29b0f896 AM |
6438 | |
6439 | /* i.reg_operands MUST be the number of real register operands; | |
c0f3af97 L |
6440 | implicit registers do not count. If there are 3 register |
6441 | operands, it must be a instruction with VexNDS. For a | |
6442 | instruction with VexNDD, the destination register is encoded | |
6443 | in VEX prefix. If there are 4 register operands, it must be | |
6444 | a instruction with VEX prefix and 3 sources. */ | |
7ab9ffdd L |
6445 | if (i.mem_operands == 0 |
6446 | && ((i.reg_operands == 2 | |
2426c15f | 6447 | && i.tm.opcode_modifier.vexvvvv <= VEXXDS) |
7ab9ffdd | 6448 | || (i.reg_operands == 3 |
2426c15f | 6449 | && i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd | 6450 | || (i.reg_operands == 4 && vex_3_sources))) |
29b0f896 | 6451 | { |
cab737b9 L |
6452 | switch (i.operands) |
6453 | { | |
6454 | case 2: | |
6455 | source = 0; | |
6456 | break; | |
6457 | case 3: | |
c81128dc L |
6458 | /* When there are 3 operands, one of them may be immediate, |
6459 | which may be the first or the last operand. Otherwise, | |
c0f3af97 L |
6460 | the first operand must be shift count register (cl) or it |
6461 | is an instruction with VexNDS. */ | |
9c2799c2 | 6462 | gas_assert (i.imm_operands == 1 |
7ab9ffdd | 6463 | || (i.imm_operands == 0 |
2426c15f | 6464 | && (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd | 6465 | || i.types[0].bitfield.shiftcount))); |
40fb9820 L |
6466 | if (operand_type_check (i.types[0], imm) |
6467 | || i.types[0].bitfield.shiftcount) | |
6468 | source = 1; | |
6469 | else | |
6470 | source = 0; | |
cab737b9 L |
6471 | break; |
6472 | case 4: | |
368d64cc L |
6473 | /* When there are 4 operands, the first two must be 8bit |
6474 | immediate operands. The source operand will be the 3rd | |
c0f3af97 L |
6475 | one. |
6476 | ||
6477 | For instructions with VexNDS, if the first operand | |
6478 | an imm8, the source operand is the 2nd one. If the last | |
6479 | operand is imm8, the source operand is the first one. */ | |
9c2799c2 | 6480 | gas_assert ((i.imm_operands == 2 |
7ab9ffdd L |
6481 | && i.types[0].bitfield.imm8 |
6482 | && i.types[1].bitfield.imm8) | |
2426c15f | 6483 | || (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd L |
6484 | && i.imm_operands == 1 |
6485 | && (i.types[0].bitfield.imm8 | |
43234a1e L |
6486 | || i.types[i.operands - 1].bitfield.imm8 |
6487 | || i.rounding))); | |
9f2670f2 L |
6488 | if (i.imm_operands == 2) |
6489 | source = 2; | |
6490 | else | |
c0f3af97 L |
6491 | { |
6492 | if (i.types[0].bitfield.imm8) | |
6493 | source = 1; | |
6494 | else | |
6495 | source = 0; | |
6496 | } | |
c0f3af97 L |
6497 | break; |
6498 | case 5: | |
43234a1e L |
6499 | if (i.tm.opcode_modifier.evex) |
6500 | { | |
6501 | /* For EVEX instructions, when there are 5 operands, the | |
6502 | first one must be immediate operand. If the second one | |
6503 | is immediate operand, the source operand is the 3th | |
6504 | one. If the last one is immediate operand, the source | |
6505 | operand is the 2nd one. */ | |
6506 | gas_assert (i.imm_operands == 2 | |
6507 | && i.tm.opcode_modifier.sae | |
6508 | && operand_type_check (i.types[0], imm)); | |
6509 | if (operand_type_check (i.types[1], imm)) | |
6510 | source = 2; | |
6511 | else if (operand_type_check (i.types[4], imm)) | |
6512 | source = 1; | |
6513 | else | |
6514 | abort (); | |
6515 | } | |
cab737b9 L |
6516 | break; |
6517 | default: | |
6518 | abort (); | |
6519 | } | |
6520 | ||
c0f3af97 L |
6521 | if (!vex_3_sources) |
6522 | { | |
6523 | dest = source + 1; | |
6524 | ||
43234a1e L |
6525 | /* RC/SAE operand could be between DEST and SRC. That happens |
6526 | when one operand is GPR and the other one is XMM/YMM/ZMM | |
6527 | register. */ | |
6528 | if (i.rounding && i.rounding->operand == (int) dest) | |
6529 | dest++; | |
6530 | ||
2426c15f | 6531 | if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
c0f3af97 | 6532 | { |
43234a1e | 6533 | /* For instructions with VexNDS, the register-only source |
c5d0745b | 6534 | operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask |
43234a1e L |
6535 | register. It is encoded in VEX prefix. We need to |
6536 | clear RegMem bit before calling operand_type_equal. */ | |
f12dc422 L |
6537 | |
6538 | i386_operand_type op; | |
6539 | unsigned int vvvv; | |
6540 | ||
6541 | /* Check register-only source operand when two source | |
6542 | operands are swapped. */ | |
6543 | if (!i.tm.operand_types[source].bitfield.baseindex | |
6544 | && i.tm.operand_types[dest].bitfield.baseindex) | |
6545 | { | |
6546 | vvvv = source; | |
6547 | source = dest; | |
6548 | } | |
6549 | else | |
6550 | vvvv = dest; | |
6551 | ||
6552 | op = i.tm.operand_types[vvvv]; | |
fa99fab2 | 6553 | op.bitfield.regmem = 0; |
c0f3af97 | 6554 | if ((dest + 1) >= i.operands |
dc821c5f JB |
6555 | || ((!op.bitfield.reg |
6556 | || (!op.bitfield.dword && !op.bitfield.qword)) | |
10c17abd | 6557 | && !op.bitfield.regsimd |
43234a1e | 6558 | && !operand_type_equal (&op, ®mask))) |
c0f3af97 | 6559 | abort (); |
f12dc422 | 6560 | i.vex.register_specifier = i.op[vvvv].regs; |
c0f3af97 L |
6561 | dest++; |
6562 | } | |
6563 | } | |
29b0f896 AM |
6564 | |
6565 | i.rm.mode = 3; | |
6566 | /* One of the register operands will be encoded in the i.tm.reg | |
6567 | field, the other in the combined i.tm.mode and i.tm.regmem | |
6568 | fields. If no form of this instruction supports a memory | |
6569 | destination operand, then we assume the source operand may | |
6570 | sometimes be a memory operand and so we need to store the | |
6571 | destination in the i.rm.reg field. */ | |
40fb9820 L |
6572 | if (!i.tm.operand_types[dest].bitfield.regmem |
6573 | && operand_type_check (i.tm.operand_types[dest], anymem) == 0) | |
29b0f896 AM |
6574 | { |
6575 | i.rm.reg = i.op[dest].regs->reg_num; | |
6576 | i.rm.regmem = i.op[source].regs->reg_num; | |
6577 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 6578 | i.rex |= REX_R; |
43234a1e L |
6579 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
6580 | i.vrex |= REX_R; | |
29b0f896 | 6581 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 6582 | i.rex |= REX_B; |
43234a1e L |
6583 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
6584 | i.vrex |= REX_B; | |
29b0f896 AM |
6585 | } |
6586 | else | |
6587 | { | |
6588 | i.rm.reg = i.op[source].regs->reg_num; | |
6589 | i.rm.regmem = i.op[dest].regs->reg_num; | |
6590 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 6591 | i.rex |= REX_B; |
43234a1e L |
6592 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
6593 | i.vrex |= REX_B; | |
29b0f896 | 6594 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 6595 | i.rex |= REX_R; |
43234a1e L |
6596 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
6597 | i.vrex |= REX_R; | |
29b0f896 | 6598 | } |
161a04f6 | 6599 | if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B))) |
c4a530c5 | 6600 | { |
40fb9820 L |
6601 | if (!i.types[0].bitfield.control |
6602 | && !i.types[1].bitfield.control) | |
c4a530c5 | 6603 | abort (); |
161a04f6 | 6604 | i.rex &= ~(REX_R | REX_B); |
c4a530c5 JB |
6605 | add_prefix (LOCK_PREFIX_OPCODE); |
6606 | } | |
29b0f896 AM |
6607 | } |
6608 | else | |
6609 | { /* If it's not 2 reg operands... */ | |
c0f3af97 L |
6610 | unsigned int mem; |
6611 | ||
29b0f896 AM |
6612 | if (i.mem_operands) |
6613 | { | |
6614 | unsigned int fake_zero_displacement = 0; | |
99018f42 | 6615 | unsigned int op; |
4eed87de | 6616 | |
7ab9ffdd L |
6617 | for (op = 0; op < i.operands; op++) |
6618 | if (operand_type_check (i.types[op], anymem)) | |
6619 | break; | |
7ab9ffdd | 6620 | gas_assert (op < i.operands); |
29b0f896 | 6621 | |
6c30d220 L |
6622 | if (i.tm.opcode_modifier.vecsib) |
6623 | { | |
6624 | if (i.index_reg->reg_num == RegEiz | |
6625 | || i.index_reg->reg_num == RegRiz) | |
6626 | abort (); | |
6627 | ||
6628 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
6629 | if (!i.base_reg) | |
6630 | { | |
6631 | i.sib.base = NO_BASE_REGISTER; | |
6632 | i.sib.scale = i.log2_scale_factor; | |
6633 | i.types[op].bitfield.disp8 = 0; | |
6634 | i.types[op].bitfield.disp16 = 0; | |
6635 | i.types[op].bitfield.disp64 = 0; | |
43083a50 | 6636 | if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX]) |
6c30d220 L |
6637 | { |
6638 | /* Must be 32 bit */ | |
6639 | i.types[op].bitfield.disp32 = 1; | |
6640 | i.types[op].bitfield.disp32s = 0; | |
6641 | } | |
6642 | else | |
6643 | { | |
6644 | i.types[op].bitfield.disp32 = 0; | |
6645 | i.types[op].bitfield.disp32s = 1; | |
6646 | } | |
6647 | } | |
6648 | i.sib.index = i.index_reg->reg_num; | |
6649 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
6650 | i.rex |= REX_X; | |
43234a1e L |
6651 | if ((i.index_reg->reg_flags & RegVRex) != 0) |
6652 | i.vrex |= REX_X; | |
6c30d220 L |
6653 | } |
6654 | ||
29b0f896 AM |
6655 | default_seg = &ds; |
6656 | ||
6657 | if (i.base_reg == 0) | |
6658 | { | |
6659 | i.rm.mode = 0; | |
6660 | if (!i.disp_operands) | |
9bb129e8 | 6661 | fake_zero_displacement = 1; |
29b0f896 AM |
6662 | if (i.index_reg == 0) |
6663 | { | |
6c30d220 | 6664 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 6665 | /* Operand is just <disp> */ |
20f0a1fc | 6666 | if (flag_code == CODE_64BIT) |
29b0f896 AM |
6667 | { |
6668 | /* 64bit mode overwrites the 32bit absolute | |
6669 | addressing by RIP relative addressing and | |
6670 | absolute addressing is encoded by one of the | |
6671 | redundant SIB forms. */ | |
6672 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
6673 | i.sib.base = NO_BASE_REGISTER; | |
6674 | i.sib.index = NO_INDEX_REGISTER; | |
fc225355 | 6675 | i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) |
40fb9820 | 6676 | ? disp32s : disp32); |
20f0a1fc | 6677 | } |
fc225355 L |
6678 | else if ((flag_code == CODE_16BIT) |
6679 | ^ (i.prefix[ADDR_PREFIX] != 0)) | |
20f0a1fc NC |
6680 | { |
6681 | i.rm.regmem = NO_BASE_REGISTER_16; | |
40fb9820 | 6682 | i.types[op] = disp16; |
20f0a1fc NC |
6683 | } |
6684 | else | |
6685 | { | |
6686 | i.rm.regmem = NO_BASE_REGISTER; | |
40fb9820 | 6687 | i.types[op] = disp32; |
29b0f896 AM |
6688 | } |
6689 | } | |
6c30d220 | 6690 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 6691 | { |
6c30d220 | 6692 | /* !i.base_reg && i.index_reg */ |
db51cc60 L |
6693 | if (i.index_reg->reg_num == RegEiz |
6694 | || i.index_reg->reg_num == RegRiz) | |
6695 | i.sib.index = NO_INDEX_REGISTER; | |
6696 | else | |
6697 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
6698 | i.sib.base = NO_BASE_REGISTER; |
6699 | i.sib.scale = i.log2_scale_factor; | |
6700 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
40fb9820 L |
6701 | i.types[op].bitfield.disp8 = 0; |
6702 | i.types[op].bitfield.disp16 = 0; | |
6703 | i.types[op].bitfield.disp64 = 0; | |
43083a50 | 6704 | if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX]) |
40fb9820 L |
6705 | { |
6706 | /* Must be 32 bit */ | |
6707 | i.types[op].bitfield.disp32 = 1; | |
6708 | i.types[op].bitfield.disp32s = 0; | |
6709 | } | |
29b0f896 | 6710 | else |
40fb9820 L |
6711 | { |
6712 | i.types[op].bitfield.disp32 = 0; | |
6713 | i.types[op].bitfield.disp32s = 1; | |
6714 | } | |
29b0f896 | 6715 | if ((i.index_reg->reg_flags & RegRex) != 0) |
161a04f6 | 6716 | i.rex |= REX_X; |
29b0f896 AM |
6717 | } |
6718 | } | |
6719 | /* RIP addressing for 64bit mode. */ | |
9a04903e JB |
6720 | else if (i.base_reg->reg_num == RegRip || |
6721 | i.base_reg->reg_num == RegEip) | |
29b0f896 | 6722 | { |
6c30d220 | 6723 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 6724 | i.rm.regmem = NO_BASE_REGISTER; |
40fb9820 L |
6725 | i.types[op].bitfield.disp8 = 0; |
6726 | i.types[op].bitfield.disp16 = 0; | |
6727 | i.types[op].bitfield.disp32 = 0; | |
6728 | i.types[op].bitfield.disp32s = 1; | |
6729 | i.types[op].bitfield.disp64 = 0; | |
71903a11 | 6730 | i.flags[op] |= Operand_PCrel; |
20f0a1fc NC |
6731 | if (! i.disp_operands) |
6732 | fake_zero_displacement = 1; | |
29b0f896 | 6733 | } |
dc821c5f | 6734 | else if (i.base_reg->reg_type.bitfield.word) |
29b0f896 | 6735 | { |
6c30d220 | 6736 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
6737 | switch (i.base_reg->reg_num) |
6738 | { | |
6739 | case 3: /* (%bx) */ | |
6740 | if (i.index_reg == 0) | |
6741 | i.rm.regmem = 7; | |
6742 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
6743 | i.rm.regmem = i.index_reg->reg_num - 6; | |
6744 | break; | |
6745 | case 5: /* (%bp) */ | |
6746 | default_seg = &ss; | |
6747 | if (i.index_reg == 0) | |
6748 | { | |
6749 | i.rm.regmem = 6; | |
40fb9820 | 6750 | if (operand_type_check (i.types[op], disp) == 0) |
29b0f896 AM |
6751 | { |
6752 | /* fake (%bp) into 0(%bp) */ | |
b5014f7a | 6753 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 6754 | fake_zero_displacement = 1; |
29b0f896 AM |
6755 | } |
6756 | } | |
6757 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
6758 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
6759 | break; | |
6760 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
6761 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
6762 | } | |
6763 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
6764 | } | |
6765 | else /* i.base_reg and 32/64 bit mode */ | |
6766 | { | |
6767 | if (flag_code == CODE_64BIT | |
40fb9820 L |
6768 | && operand_type_check (i.types[op], disp)) |
6769 | { | |
6770 | i386_operand_type temp; | |
0dfbf9d7 | 6771 | operand_type_set (&temp, 0); |
40fb9820 L |
6772 | temp.bitfield.disp8 = i.types[op].bitfield.disp8; |
6773 | i.types[op] = temp; | |
6774 | if (i.prefix[ADDR_PREFIX] == 0) | |
6775 | i.types[op].bitfield.disp32s = 1; | |
6776 | else | |
6777 | i.types[op].bitfield.disp32 = 1; | |
6778 | } | |
20f0a1fc | 6779 | |
6c30d220 L |
6780 | if (!i.tm.opcode_modifier.vecsib) |
6781 | i.rm.regmem = i.base_reg->reg_num; | |
29b0f896 | 6782 | if ((i.base_reg->reg_flags & RegRex) != 0) |
161a04f6 | 6783 | i.rex |= REX_B; |
29b0f896 AM |
6784 | i.sib.base = i.base_reg->reg_num; |
6785 | /* x86-64 ignores REX prefix bit here to avoid decoder | |
6786 | complications. */ | |
848930b2 JB |
6787 | if (!(i.base_reg->reg_flags & RegRex) |
6788 | && (i.base_reg->reg_num == EBP_REG_NUM | |
6789 | || i.base_reg->reg_num == ESP_REG_NUM)) | |
29b0f896 | 6790 | default_seg = &ss; |
848930b2 | 6791 | if (i.base_reg->reg_num == 5 && i.disp_operands == 0) |
29b0f896 | 6792 | { |
848930b2 | 6793 | fake_zero_displacement = 1; |
b5014f7a | 6794 | i.types[op].bitfield.disp8 = 1; |
29b0f896 AM |
6795 | } |
6796 | i.sib.scale = i.log2_scale_factor; | |
6797 | if (i.index_reg == 0) | |
6798 | { | |
6c30d220 | 6799 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
6800 | /* <disp>(%esp) becomes two byte modrm with no index |
6801 | register. We've already stored the code for esp | |
6802 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. | |
6803 | Any base register besides %esp will not use the | |
6804 | extra modrm byte. */ | |
6805 | i.sib.index = NO_INDEX_REGISTER; | |
29b0f896 | 6806 | } |
6c30d220 | 6807 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 6808 | { |
db51cc60 L |
6809 | if (i.index_reg->reg_num == RegEiz |
6810 | || i.index_reg->reg_num == RegRiz) | |
6811 | i.sib.index = NO_INDEX_REGISTER; | |
6812 | else | |
6813 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
6814 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
6815 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
161a04f6 | 6816 | i.rex |= REX_X; |
29b0f896 | 6817 | } |
67a4f2b7 AO |
6818 | |
6819 | if (i.disp_operands | |
6820 | && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL | |
6821 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) | |
6822 | i.rm.mode = 0; | |
6823 | else | |
a501d77e L |
6824 | { |
6825 | if (!fake_zero_displacement | |
6826 | && !i.disp_operands | |
6827 | && i.disp_encoding) | |
6828 | { | |
6829 | fake_zero_displacement = 1; | |
6830 | if (i.disp_encoding == disp_encoding_8bit) | |
6831 | i.types[op].bitfield.disp8 = 1; | |
6832 | else | |
6833 | i.types[op].bitfield.disp32 = 1; | |
6834 | } | |
6835 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
6836 | } | |
29b0f896 | 6837 | } |
252b5132 | 6838 | |
29b0f896 AM |
6839 | if (fake_zero_displacement) |
6840 | { | |
6841 | /* Fakes a zero displacement assuming that i.types[op] | |
6842 | holds the correct displacement size. */ | |
6843 | expressionS *exp; | |
6844 | ||
9c2799c2 | 6845 | gas_assert (i.op[op].disps == 0); |
29b0f896 AM |
6846 | exp = &disp_expressions[i.disp_operands++]; |
6847 | i.op[op].disps = exp; | |
6848 | exp->X_op = O_constant; | |
6849 | exp->X_add_number = 0; | |
6850 | exp->X_add_symbol = (symbolS *) 0; | |
6851 | exp->X_op_symbol = (symbolS *) 0; | |
6852 | } | |
c0f3af97 L |
6853 | |
6854 | mem = op; | |
29b0f896 | 6855 | } |
c0f3af97 L |
6856 | else |
6857 | mem = ~0; | |
252b5132 | 6858 | |
8c43a48b | 6859 | if (i.tm.opcode_modifier.vexsources == XOP2SOURCES) |
5dd85c99 SP |
6860 | { |
6861 | if (operand_type_check (i.types[0], imm)) | |
6862 | i.vex.register_specifier = NULL; | |
6863 | else | |
6864 | { | |
6865 | /* VEX.vvvv encodes one of the sources when the first | |
6866 | operand is not an immediate. */ | |
1ef99a7b | 6867 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
6868 | i.vex.register_specifier = i.op[0].regs; |
6869 | else | |
6870 | i.vex.register_specifier = i.op[1].regs; | |
6871 | } | |
6872 | ||
6873 | /* Destination is a XMM register encoded in the ModRM.reg | |
6874 | and VEX.R bit. */ | |
6875 | i.rm.reg = i.op[2].regs->reg_num; | |
6876 | if ((i.op[2].regs->reg_flags & RegRex) != 0) | |
6877 | i.rex |= REX_R; | |
6878 | ||
6879 | /* ModRM.rm and VEX.B encodes the other source. */ | |
6880 | if (!i.mem_operands) | |
6881 | { | |
6882 | i.rm.mode = 3; | |
6883 | ||
1ef99a7b | 6884 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
6885 | i.rm.regmem = i.op[1].regs->reg_num; |
6886 | else | |
6887 | i.rm.regmem = i.op[0].regs->reg_num; | |
6888 | ||
6889 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
6890 | i.rex |= REX_B; | |
6891 | } | |
6892 | } | |
2426c15f | 6893 | else if (i.tm.opcode_modifier.vexvvvv == VEXLWP) |
f88c9eb0 SP |
6894 | { |
6895 | i.vex.register_specifier = i.op[2].regs; | |
6896 | if (!i.mem_operands) | |
6897 | { | |
6898 | i.rm.mode = 3; | |
6899 | i.rm.regmem = i.op[1].regs->reg_num; | |
6900 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
6901 | i.rex |= REX_B; | |
6902 | } | |
6903 | } | |
29b0f896 AM |
6904 | /* Fill in i.rm.reg or i.rm.regmem field with register operand |
6905 | (if any) based on i.tm.extension_opcode. Again, we must be | |
6906 | careful to make sure that segment/control/debug/test/MMX | |
6907 | registers are coded into the i.rm.reg field. */ | |
f88c9eb0 | 6908 | else if (i.reg_operands) |
29b0f896 | 6909 | { |
99018f42 | 6910 | unsigned int op; |
7ab9ffdd L |
6911 | unsigned int vex_reg = ~0; |
6912 | ||
6913 | for (op = 0; op < i.operands; op++) | |
dc821c5f | 6914 | if (i.types[op].bitfield.reg |
7ab9ffdd | 6915 | || i.types[op].bitfield.regmmx |
1b54b8d7 | 6916 | || i.types[op].bitfield.regsimd |
7e8b059b | 6917 | || i.types[op].bitfield.regbnd |
43234a1e | 6918 | || i.types[op].bitfield.regmask |
7ab9ffdd L |
6919 | || i.types[op].bitfield.sreg2 |
6920 | || i.types[op].bitfield.sreg3 | |
6921 | || i.types[op].bitfield.control | |
6922 | || i.types[op].bitfield.debug | |
6923 | || i.types[op].bitfield.test) | |
6924 | break; | |
c0209578 | 6925 | |
7ab9ffdd L |
6926 | if (vex_3_sources) |
6927 | op = dest; | |
2426c15f | 6928 | else if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd L |
6929 | { |
6930 | /* For instructions with VexNDS, the register-only | |
6931 | source operand is encoded in VEX prefix. */ | |
6932 | gas_assert (mem != (unsigned int) ~0); | |
c0f3af97 | 6933 | |
7ab9ffdd | 6934 | if (op > mem) |
c0f3af97 | 6935 | { |
7ab9ffdd L |
6936 | vex_reg = op++; |
6937 | gas_assert (op < i.operands); | |
c0f3af97 L |
6938 | } |
6939 | else | |
c0f3af97 | 6940 | { |
f12dc422 L |
6941 | /* Check register-only source operand when two source |
6942 | operands are swapped. */ | |
6943 | if (!i.tm.operand_types[op].bitfield.baseindex | |
6944 | && i.tm.operand_types[op + 1].bitfield.baseindex) | |
6945 | { | |
6946 | vex_reg = op; | |
6947 | op += 2; | |
6948 | gas_assert (mem == (vex_reg + 1) | |
6949 | && op < i.operands); | |
6950 | } | |
6951 | else | |
6952 | { | |
6953 | vex_reg = op + 1; | |
6954 | gas_assert (vex_reg < i.operands); | |
6955 | } | |
c0f3af97 | 6956 | } |
7ab9ffdd | 6957 | } |
2426c15f | 6958 | else if (i.tm.opcode_modifier.vexvvvv == VEXNDD) |
7ab9ffdd | 6959 | { |
f12dc422 | 6960 | /* For instructions with VexNDD, the register destination |
7ab9ffdd | 6961 | is encoded in VEX prefix. */ |
f12dc422 L |
6962 | if (i.mem_operands == 0) |
6963 | { | |
6964 | /* There is no memory operand. */ | |
6965 | gas_assert ((op + 2) == i.operands); | |
6966 | vex_reg = op + 1; | |
6967 | } | |
6968 | else | |
8d63c93e | 6969 | { |
f12dc422 L |
6970 | /* There are only 2 operands. */ |
6971 | gas_assert (op < 2 && i.operands == 2); | |
6972 | vex_reg = 1; | |
6973 | } | |
7ab9ffdd L |
6974 | } |
6975 | else | |
6976 | gas_assert (op < i.operands); | |
99018f42 | 6977 | |
7ab9ffdd L |
6978 | if (vex_reg != (unsigned int) ~0) |
6979 | { | |
f12dc422 | 6980 | i386_operand_type *type = &i.tm.operand_types[vex_reg]; |
7ab9ffdd | 6981 | |
dc821c5f JB |
6982 | if ((!type->bitfield.reg |
6983 | || (!type->bitfield.dword && !type->bitfield.qword)) | |
10c17abd | 6984 | && !type->bitfield.regsimd |
43234a1e | 6985 | && !operand_type_equal (type, ®mask)) |
7ab9ffdd | 6986 | abort (); |
f88c9eb0 | 6987 | |
7ab9ffdd L |
6988 | i.vex.register_specifier = i.op[vex_reg].regs; |
6989 | } | |
6990 | ||
1b9f0c97 L |
6991 | /* Don't set OP operand twice. */ |
6992 | if (vex_reg != op) | |
7ab9ffdd | 6993 | { |
1b9f0c97 L |
6994 | /* If there is an extension opcode to put here, the |
6995 | register number must be put into the regmem field. */ | |
6996 | if (i.tm.extension_opcode != None) | |
6997 | { | |
6998 | i.rm.regmem = i.op[op].regs->reg_num; | |
6999 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
7000 | i.rex |= REX_B; | |
43234a1e L |
7001 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
7002 | i.vrex |= REX_B; | |
1b9f0c97 L |
7003 | } |
7004 | else | |
7005 | { | |
7006 | i.rm.reg = i.op[op].regs->reg_num; | |
7007 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
7008 | i.rex |= REX_R; | |
43234a1e L |
7009 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
7010 | i.vrex |= REX_R; | |
1b9f0c97 | 7011 | } |
7ab9ffdd | 7012 | } |
252b5132 | 7013 | |
29b0f896 AM |
7014 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we |
7015 | must set it to 3 to indicate this is a register operand | |
7016 | in the regmem field. */ | |
7017 | if (!i.mem_operands) | |
7018 | i.rm.mode = 3; | |
7019 | } | |
252b5132 | 7020 | |
29b0f896 | 7021 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
c1e679ec | 7022 | if (i.tm.extension_opcode != None) |
29b0f896 AM |
7023 | i.rm.reg = i.tm.extension_opcode; |
7024 | } | |
7025 | return default_seg; | |
7026 | } | |
252b5132 | 7027 | |
29b0f896 | 7028 | static void |
e3bb37b5 | 7029 | output_branch (void) |
29b0f896 AM |
7030 | { |
7031 | char *p; | |
f8a5c266 | 7032 | int size; |
29b0f896 AM |
7033 | int code16; |
7034 | int prefix; | |
7035 | relax_substateT subtype; | |
7036 | symbolS *sym; | |
7037 | offsetT off; | |
7038 | ||
f8a5c266 | 7039 | code16 = flag_code == CODE_16BIT ? CODE16 : 0; |
a501d77e | 7040 | size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL; |
29b0f896 AM |
7041 | |
7042 | prefix = 0; | |
7043 | if (i.prefix[DATA_PREFIX] != 0) | |
252b5132 | 7044 | { |
29b0f896 AM |
7045 | prefix = 1; |
7046 | i.prefixes -= 1; | |
7047 | code16 ^= CODE16; | |
252b5132 | 7048 | } |
29b0f896 AM |
7049 | /* Pentium4 branch hints. */ |
7050 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
7051 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2f66722d | 7052 | { |
29b0f896 AM |
7053 | prefix++; |
7054 | i.prefixes--; | |
7055 | } | |
7056 | if (i.prefix[REX_PREFIX] != 0) | |
7057 | { | |
7058 | prefix++; | |
7059 | i.prefixes--; | |
2f66722d AM |
7060 | } |
7061 | ||
7e8b059b L |
7062 | /* BND prefixed jump. */ |
7063 | if (i.prefix[BND_PREFIX] != 0) | |
7064 | { | |
7065 | FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]); | |
7066 | i.prefixes -= 1; | |
7067 | } | |
7068 | ||
29b0f896 AM |
7069 | if (i.prefixes != 0 && !intel_syntax) |
7070 | as_warn (_("skipping prefixes on this instruction")); | |
7071 | ||
7072 | /* It's always a symbol; End frag & setup for relax. | |
7073 | Make sure there is enough room in this frag for the largest | |
7074 | instruction we may generate in md_convert_frag. This is 2 | |
7075 | bytes for the opcode and room for the prefix and largest | |
7076 | displacement. */ | |
7077 | frag_grow (prefix + 2 + 4); | |
7078 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
7079 | p = frag_more (prefix + 1); | |
7080 | if (i.prefix[DATA_PREFIX] != 0) | |
7081 | *p++ = DATA_PREFIX_OPCODE; | |
7082 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE | |
7083 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
7084 | *p++ = i.prefix[SEG_PREFIX]; | |
7085 | if (i.prefix[REX_PREFIX] != 0) | |
7086 | *p++ = i.prefix[REX_PREFIX]; | |
7087 | *p = i.tm.base_opcode; | |
7088 | ||
7089 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
f8a5c266 | 7090 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size); |
40fb9820 | 7091 | else if (cpu_arch_flags.bitfield.cpui386) |
f8a5c266 | 7092 | subtype = ENCODE_RELAX_STATE (COND_JUMP, size); |
29b0f896 | 7093 | else |
f8a5c266 | 7094 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, size); |
29b0f896 | 7095 | subtype |= code16; |
3e73aa7c | 7096 | |
29b0f896 AM |
7097 | sym = i.op[0].disps->X_add_symbol; |
7098 | off = i.op[0].disps->X_add_number; | |
3e73aa7c | 7099 | |
29b0f896 AM |
7100 | if (i.op[0].disps->X_op != O_constant |
7101 | && i.op[0].disps->X_op != O_symbol) | |
3e73aa7c | 7102 | { |
29b0f896 AM |
7103 | /* Handle complex expressions. */ |
7104 | sym = make_expr_symbol (i.op[0].disps); | |
7105 | off = 0; | |
7106 | } | |
3e73aa7c | 7107 | |
29b0f896 AM |
7108 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
7109 | Pass reloc in fr_var. */ | |
d258b828 | 7110 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); |
29b0f896 | 7111 | } |
3e73aa7c | 7112 | |
bd7ab16b L |
7113 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
7114 | /* Return TRUE iff PLT32 relocation should be used for branching to | |
7115 | symbol S. */ | |
7116 | ||
7117 | static bfd_boolean | |
7118 | need_plt32_p (symbolS *s) | |
7119 | { | |
7120 | /* PLT32 relocation is ELF only. */ | |
7121 | if (!IS_ELF) | |
7122 | return FALSE; | |
7123 | ||
7124 | /* Since there is no need to prepare for PLT branch on x86-64, we | |
7125 | can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can | |
7126 | be used as a marker for 32-bit PC-relative branches. */ | |
7127 | if (!object_64bit) | |
7128 | return FALSE; | |
7129 | ||
7130 | /* Weak or undefined symbol need PLT32 relocation. */ | |
7131 | if (S_IS_WEAK (s) || !S_IS_DEFINED (s)) | |
7132 | return TRUE; | |
7133 | ||
7134 | /* Non-global symbol doesn't need PLT32 relocation. */ | |
7135 | if (! S_IS_EXTERNAL (s)) | |
7136 | return FALSE; | |
7137 | ||
7138 | /* Other global symbols need PLT32 relocation. NB: Symbol with | |
7139 | non-default visibilities are treated as normal global symbol | |
7140 | so that PLT32 relocation can be used as a marker for 32-bit | |
7141 | PC-relative branches. It is useful for linker relaxation. */ | |
7142 | return TRUE; | |
7143 | } | |
7144 | #endif | |
7145 | ||
29b0f896 | 7146 | static void |
e3bb37b5 | 7147 | output_jump (void) |
29b0f896 AM |
7148 | { |
7149 | char *p; | |
7150 | int size; | |
3e02c1cc | 7151 | fixS *fixP; |
bd7ab16b | 7152 | bfd_reloc_code_real_type jump_reloc = i.reloc[0]; |
29b0f896 | 7153 | |
40fb9820 | 7154 | if (i.tm.opcode_modifier.jumpbyte) |
29b0f896 AM |
7155 | { |
7156 | /* This is a loop or jecxz type instruction. */ | |
7157 | size = 1; | |
7158 | if (i.prefix[ADDR_PREFIX] != 0) | |
7159 | { | |
7160 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); | |
7161 | i.prefixes -= 1; | |
7162 | } | |
7163 | /* Pentium4 branch hints. */ | |
7164 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
7165 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
7166 | { | |
7167 | FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); | |
7168 | i.prefixes--; | |
3e73aa7c JH |
7169 | } |
7170 | } | |
29b0f896 AM |
7171 | else |
7172 | { | |
7173 | int code16; | |
3e73aa7c | 7174 | |
29b0f896 AM |
7175 | code16 = 0; |
7176 | if (flag_code == CODE_16BIT) | |
7177 | code16 = CODE16; | |
3e73aa7c | 7178 | |
29b0f896 AM |
7179 | if (i.prefix[DATA_PREFIX] != 0) |
7180 | { | |
7181 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); | |
7182 | i.prefixes -= 1; | |
7183 | code16 ^= CODE16; | |
7184 | } | |
252b5132 | 7185 | |
29b0f896 AM |
7186 | size = 4; |
7187 | if (code16) | |
7188 | size = 2; | |
7189 | } | |
9fcc94b6 | 7190 | |
29b0f896 AM |
7191 | if (i.prefix[REX_PREFIX] != 0) |
7192 | { | |
7193 | FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); | |
7194 | i.prefixes -= 1; | |
7195 | } | |
252b5132 | 7196 | |
7e8b059b L |
7197 | /* BND prefixed jump. */ |
7198 | if (i.prefix[BND_PREFIX] != 0) | |
7199 | { | |
7200 | FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]); | |
7201 | i.prefixes -= 1; | |
7202 | } | |
7203 | ||
29b0f896 AM |
7204 | if (i.prefixes != 0 && !intel_syntax) |
7205 | as_warn (_("skipping prefixes on this instruction")); | |
e0890092 | 7206 | |
42164a71 L |
7207 | p = frag_more (i.tm.opcode_length + size); |
7208 | switch (i.tm.opcode_length) | |
7209 | { | |
7210 | case 2: | |
7211 | *p++ = i.tm.base_opcode >> 8; | |
1a0670f3 | 7212 | /* Fall through. */ |
42164a71 L |
7213 | case 1: |
7214 | *p++ = i.tm.base_opcode; | |
7215 | break; | |
7216 | default: | |
7217 | abort (); | |
7218 | } | |
e0890092 | 7219 | |
bd7ab16b L |
7220 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
7221 | if (size == 4 | |
7222 | && jump_reloc == NO_RELOC | |
7223 | && need_plt32_p (i.op[0].disps->X_add_symbol)) | |
7224 | jump_reloc = BFD_RELOC_X86_64_PLT32; | |
7225 | #endif | |
7226 | ||
7227 | jump_reloc = reloc (size, 1, 1, jump_reloc); | |
7228 | ||
3e02c1cc | 7229 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
bd7ab16b | 7230 | i.op[0].disps, 1, jump_reloc); |
3e02c1cc AM |
7231 | |
7232 | /* All jumps handled here are signed, but don't use a signed limit | |
7233 | check for 32 and 16 bit jumps as we want to allow wrap around at | |
7234 | 4G and 64k respectively. */ | |
7235 | if (size == 1) | |
7236 | fixP->fx_signed = 1; | |
29b0f896 | 7237 | } |
e0890092 | 7238 | |
29b0f896 | 7239 | static void |
e3bb37b5 | 7240 | output_interseg_jump (void) |
29b0f896 AM |
7241 | { |
7242 | char *p; | |
7243 | int size; | |
7244 | int prefix; | |
7245 | int code16; | |
252b5132 | 7246 | |
29b0f896 AM |
7247 | code16 = 0; |
7248 | if (flag_code == CODE_16BIT) | |
7249 | code16 = CODE16; | |
a217f122 | 7250 | |
29b0f896 AM |
7251 | prefix = 0; |
7252 | if (i.prefix[DATA_PREFIX] != 0) | |
7253 | { | |
7254 | prefix = 1; | |
7255 | i.prefixes -= 1; | |
7256 | code16 ^= CODE16; | |
7257 | } | |
7258 | if (i.prefix[REX_PREFIX] != 0) | |
7259 | { | |
7260 | prefix++; | |
7261 | i.prefixes -= 1; | |
7262 | } | |
252b5132 | 7263 | |
29b0f896 AM |
7264 | size = 4; |
7265 | if (code16) | |
7266 | size = 2; | |
252b5132 | 7267 | |
29b0f896 AM |
7268 | if (i.prefixes != 0 && !intel_syntax) |
7269 | as_warn (_("skipping prefixes on this instruction")); | |
252b5132 | 7270 | |
29b0f896 AM |
7271 | /* 1 opcode; 2 segment; offset */ |
7272 | p = frag_more (prefix + 1 + 2 + size); | |
3e73aa7c | 7273 | |
29b0f896 AM |
7274 | if (i.prefix[DATA_PREFIX] != 0) |
7275 | *p++ = DATA_PREFIX_OPCODE; | |
252b5132 | 7276 | |
29b0f896 AM |
7277 | if (i.prefix[REX_PREFIX] != 0) |
7278 | *p++ = i.prefix[REX_PREFIX]; | |
252b5132 | 7279 | |
29b0f896 AM |
7280 | *p++ = i.tm.base_opcode; |
7281 | if (i.op[1].imms->X_op == O_constant) | |
7282 | { | |
7283 | offsetT n = i.op[1].imms->X_add_number; | |
252b5132 | 7284 | |
29b0f896 AM |
7285 | if (size == 2 |
7286 | && !fits_in_unsigned_word (n) | |
7287 | && !fits_in_signed_word (n)) | |
7288 | { | |
7289 | as_bad (_("16-bit jump out of range")); | |
7290 | return; | |
7291 | } | |
7292 | md_number_to_chars (p, n, size); | |
7293 | } | |
7294 | else | |
7295 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
d258b828 | 7296 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); |
29b0f896 AM |
7297 | if (i.op[0].imms->X_op != O_constant) |
7298 | as_bad (_("can't handle non absolute segment in `%s'"), | |
7299 | i.tm.name); | |
7300 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); | |
7301 | } | |
a217f122 | 7302 | |
29b0f896 | 7303 | static void |
e3bb37b5 | 7304 | output_insn (void) |
29b0f896 | 7305 | { |
2bbd9c25 JJ |
7306 | fragS *insn_start_frag; |
7307 | offsetT insn_start_off; | |
7308 | ||
29b0f896 AM |
7309 | /* Tie dwarf2 debug info to the address at the start of the insn. |
7310 | We can't do this after the insn has been output as the current | |
7311 | frag may have been closed off. eg. by frag_var. */ | |
7312 | dwarf2_emit_insn (0); | |
7313 | ||
2bbd9c25 JJ |
7314 | insn_start_frag = frag_now; |
7315 | insn_start_off = frag_now_fix (); | |
7316 | ||
29b0f896 | 7317 | /* Output jumps. */ |
40fb9820 | 7318 | if (i.tm.opcode_modifier.jump) |
29b0f896 | 7319 | output_branch (); |
40fb9820 L |
7320 | else if (i.tm.opcode_modifier.jumpbyte |
7321 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 | 7322 | output_jump (); |
40fb9820 | 7323 | else if (i.tm.opcode_modifier.jumpintersegment) |
29b0f896 AM |
7324 | output_interseg_jump (); |
7325 | else | |
7326 | { | |
7327 | /* Output normal instructions here. */ | |
7328 | char *p; | |
7329 | unsigned char *q; | |
47465058 | 7330 | unsigned int j; |
331d2d0d | 7331 | unsigned int prefix; |
4dffcebc | 7332 | |
e4e00185 AS |
7333 | if (avoid_fence |
7334 | && i.tm.base_opcode == 0xfae | |
7335 | && i.operands == 1 | |
7336 | && i.imm_operands == 1 | |
7337 | && (i.op[0].imms->X_add_number == 0xe8 | |
7338 | || i.op[0].imms->X_add_number == 0xf0 | |
7339 | || i.op[0].imms->X_add_number == 0xf8)) | |
7340 | { | |
7341 | /* Encode lfence, mfence, and sfence as | |
7342 | f0 83 04 24 00 lock addl $0x0, (%{re}sp). */ | |
7343 | offsetT val = 0x240483f0ULL; | |
7344 | p = frag_more (5); | |
7345 | md_number_to_chars (p, val, 5); | |
7346 | return; | |
7347 | } | |
7348 | ||
d022bddd IT |
7349 | /* Some processors fail on LOCK prefix. This options makes |
7350 | assembler ignore LOCK prefix and serves as a workaround. */ | |
7351 | if (omit_lock_prefix) | |
7352 | { | |
7353 | if (i.tm.base_opcode == LOCK_PREFIX_OPCODE) | |
7354 | return; | |
7355 | i.prefix[LOCK_PREFIX] = 0; | |
7356 | } | |
7357 | ||
43234a1e L |
7358 | /* Since the VEX/EVEX prefix contains the implicit prefix, we |
7359 | don't need the explicit prefix. */ | |
7360 | if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex) | |
bc4bd9ab | 7361 | { |
c0f3af97 | 7362 | switch (i.tm.opcode_length) |
bc4bd9ab | 7363 | { |
c0f3af97 L |
7364 | case 3: |
7365 | if (i.tm.base_opcode & 0xff000000) | |
4dffcebc | 7366 | { |
c0f3af97 L |
7367 | prefix = (i.tm.base_opcode >> 24) & 0xff; |
7368 | goto check_prefix; | |
7369 | } | |
7370 | break; | |
7371 | case 2: | |
7372 | if ((i.tm.base_opcode & 0xff0000) != 0) | |
7373 | { | |
7374 | prefix = (i.tm.base_opcode >> 16) & 0xff; | |
7375 | if (i.tm.cpu_flags.bitfield.cpupadlock) | |
7376 | { | |
4dffcebc | 7377 | check_prefix: |
c0f3af97 | 7378 | if (prefix != REPE_PREFIX_OPCODE |
c32fa91d | 7379 | || (i.prefix[REP_PREFIX] |
c0f3af97 L |
7380 | != REPE_PREFIX_OPCODE)) |
7381 | add_prefix (prefix); | |
7382 | } | |
7383 | else | |
4dffcebc L |
7384 | add_prefix (prefix); |
7385 | } | |
c0f3af97 L |
7386 | break; |
7387 | case 1: | |
7388 | break; | |
390c91cf L |
7389 | case 0: |
7390 | /* Check for pseudo prefixes. */ | |
7391 | as_bad_where (insn_start_frag->fr_file, | |
7392 | insn_start_frag->fr_line, | |
7393 | _("pseudo prefix without instruction")); | |
7394 | return; | |
c0f3af97 L |
7395 | default: |
7396 | abort (); | |
bc4bd9ab | 7397 | } |
c0f3af97 | 7398 | |
6d19a37a | 7399 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
cf61b747 L |
7400 | /* For x32, add a dummy REX_OPCODE prefix for mov/add with |
7401 | R_X86_64_GOTTPOFF relocation so that linker can safely | |
7402 | perform IE->LE optimization. */ | |
7403 | if (x86_elf_abi == X86_64_X32_ABI | |
7404 | && i.operands == 2 | |
7405 | && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF | |
7406 | && i.prefix[REX_PREFIX] == 0) | |
7407 | add_prefix (REX_OPCODE); | |
6d19a37a | 7408 | #endif |
cf61b747 | 7409 | |
c0f3af97 L |
7410 | /* The prefix bytes. */ |
7411 | for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) | |
7412 | if (*q) | |
7413 | FRAG_APPEND_1_CHAR (*q); | |
0f10071e | 7414 | } |
ae5c1c7b | 7415 | else |
c0f3af97 L |
7416 | { |
7417 | for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++) | |
7418 | if (*q) | |
7419 | switch (j) | |
7420 | { | |
7421 | case REX_PREFIX: | |
7422 | /* REX byte is encoded in VEX prefix. */ | |
7423 | break; | |
7424 | case SEG_PREFIX: | |
7425 | case ADDR_PREFIX: | |
7426 | FRAG_APPEND_1_CHAR (*q); | |
7427 | break; | |
7428 | default: | |
7429 | /* There should be no other prefixes for instructions | |
7430 | with VEX prefix. */ | |
7431 | abort (); | |
7432 | } | |
7433 | ||
43234a1e L |
7434 | /* For EVEX instructions i.vrex should become 0 after |
7435 | build_evex_prefix. For VEX instructions upper 16 registers | |
7436 | aren't available, so VREX should be 0. */ | |
7437 | if (i.vrex) | |
7438 | abort (); | |
c0f3af97 L |
7439 | /* Now the VEX prefix. */ |
7440 | p = frag_more (i.vex.length); | |
7441 | for (j = 0; j < i.vex.length; j++) | |
7442 | p[j] = i.vex.bytes[j]; | |
7443 | } | |
252b5132 | 7444 | |
29b0f896 | 7445 | /* Now the opcode; be careful about word order here! */ |
4dffcebc | 7446 | if (i.tm.opcode_length == 1) |
29b0f896 AM |
7447 | { |
7448 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
7449 | } | |
7450 | else | |
7451 | { | |
4dffcebc | 7452 | switch (i.tm.opcode_length) |
331d2d0d | 7453 | { |
43234a1e L |
7454 | case 4: |
7455 | p = frag_more (4); | |
7456 | *p++ = (i.tm.base_opcode >> 24) & 0xff; | |
7457 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
7458 | break; | |
4dffcebc | 7459 | case 3: |
331d2d0d L |
7460 | p = frag_more (3); |
7461 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
4dffcebc L |
7462 | break; |
7463 | case 2: | |
7464 | p = frag_more (2); | |
7465 | break; | |
7466 | default: | |
7467 | abort (); | |
7468 | break; | |
331d2d0d | 7469 | } |
0f10071e | 7470 | |
29b0f896 AM |
7471 | /* Put out high byte first: can't use md_number_to_chars! */ |
7472 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
7473 | *p = i.tm.base_opcode & 0xff; | |
7474 | } | |
3e73aa7c | 7475 | |
29b0f896 | 7476 | /* Now the modrm byte and sib byte (if present). */ |
40fb9820 | 7477 | if (i.tm.opcode_modifier.modrm) |
29b0f896 | 7478 | { |
4a3523fa L |
7479 | FRAG_APPEND_1_CHAR ((i.rm.regmem << 0 |
7480 | | i.rm.reg << 3 | |
7481 | | i.rm.mode << 6)); | |
29b0f896 AM |
7482 | /* If i.rm.regmem == ESP (4) |
7483 | && i.rm.mode != (Register mode) | |
7484 | && not 16 bit | |
7485 | ==> need second modrm byte. */ | |
7486 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
7487 | && i.rm.mode != 3 | |
dc821c5f | 7488 | && !(i.base_reg && i.base_reg->reg_type.bitfield.word)) |
4a3523fa L |
7489 | FRAG_APPEND_1_CHAR ((i.sib.base << 0 |
7490 | | i.sib.index << 3 | |
7491 | | i.sib.scale << 6)); | |
29b0f896 | 7492 | } |
3e73aa7c | 7493 | |
29b0f896 | 7494 | if (i.disp_operands) |
2bbd9c25 | 7495 | output_disp (insn_start_frag, insn_start_off); |
3e73aa7c | 7496 | |
29b0f896 | 7497 | if (i.imm_operands) |
2bbd9c25 | 7498 | output_imm (insn_start_frag, insn_start_off); |
29b0f896 | 7499 | } |
252b5132 | 7500 | |
29b0f896 AM |
7501 | #ifdef DEBUG386 |
7502 | if (flag_debug) | |
7503 | { | |
7b81dfbb | 7504 | pi ("" /*line*/, &i); |
29b0f896 AM |
7505 | } |
7506 | #endif /* DEBUG386 */ | |
7507 | } | |
252b5132 | 7508 | |
e205caa7 L |
7509 | /* Return the size of the displacement operand N. */ |
7510 | ||
7511 | static int | |
7512 | disp_size (unsigned int n) | |
7513 | { | |
7514 | int size = 4; | |
43234a1e | 7515 | |
b5014f7a | 7516 | if (i.types[n].bitfield.disp64) |
40fb9820 L |
7517 | size = 8; |
7518 | else if (i.types[n].bitfield.disp8) | |
7519 | size = 1; | |
7520 | else if (i.types[n].bitfield.disp16) | |
7521 | size = 2; | |
e205caa7 L |
7522 | return size; |
7523 | } | |
7524 | ||
7525 | /* Return the size of the immediate operand N. */ | |
7526 | ||
7527 | static int | |
7528 | imm_size (unsigned int n) | |
7529 | { | |
7530 | int size = 4; | |
40fb9820 L |
7531 | if (i.types[n].bitfield.imm64) |
7532 | size = 8; | |
7533 | else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) | |
7534 | size = 1; | |
7535 | else if (i.types[n].bitfield.imm16) | |
7536 | size = 2; | |
e205caa7 L |
7537 | return size; |
7538 | } | |
7539 | ||
29b0f896 | 7540 | static void |
64e74474 | 7541 | output_disp (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
7542 | { |
7543 | char *p; | |
7544 | unsigned int n; | |
252b5132 | 7545 | |
29b0f896 AM |
7546 | for (n = 0; n < i.operands; n++) |
7547 | { | |
b5014f7a | 7548 | if (operand_type_check (i.types[n], disp)) |
29b0f896 AM |
7549 | { |
7550 | if (i.op[n].disps->X_op == O_constant) | |
7551 | { | |
e205caa7 | 7552 | int size = disp_size (n); |
43234a1e | 7553 | offsetT val = i.op[n].disps->X_add_number; |
252b5132 | 7554 | |
b5014f7a | 7555 | val = offset_in_range (val >> i.memshift, size); |
29b0f896 AM |
7556 | p = frag_more (size); |
7557 | md_number_to_chars (p, val, size); | |
7558 | } | |
7559 | else | |
7560 | { | |
f86103b7 | 7561 | enum bfd_reloc_code_real reloc_type; |
e205caa7 | 7562 | int size = disp_size (n); |
40fb9820 | 7563 | int sign = i.types[n].bitfield.disp32s; |
29b0f896 | 7564 | int pcrel = (i.flags[n] & Operand_PCrel) != 0; |
02a86693 | 7565 | fixS *fixP; |
29b0f896 | 7566 | |
e205caa7 | 7567 | /* We can't have 8 bit displacement here. */ |
9c2799c2 | 7568 | gas_assert (!i.types[n].bitfield.disp8); |
e205caa7 | 7569 | |
29b0f896 AM |
7570 | /* The PC relative address is computed relative |
7571 | to the instruction boundary, so in case immediate | |
7572 | fields follows, we need to adjust the value. */ | |
7573 | if (pcrel && i.imm_operands) | |
7574 | { | |
29b0f896 | 7575 | unsigned int n1; |
e205caa7 | 7576 | int sz = 0; |
252b5132 | 7577 | |
29b0f896 | 7578 | for (n1 = 0; n1 < i.operands; n1++) |
40fb9820 | 7579 | if (operand_type_check (i.types[n1], imm)) |
252b5132 | 7580 | { |
e205caa7 L |
7581 | /* Only one immediate is allowed for PC |
7582 | relative address. */ | |
9c2799c2 | 7583 | gas_assert (sz == 0); |
e205caa7 L |
7584 | sz = imm_size (n1); |
7585 | i.op[n].disps->X_add_number -= sz; | |
252b5132 | 7586 | } |
29b0f896 | 7587 | /* We should find the immediate. */ |
9c2799c2 | 7588 | gas_assert (sz != 0); |
29b0f896 | 7589 | } |
520dc8e8 | 7590 | |
29b0f896 | 7591 | p = frag_more (size); |
d258b828 | 7592 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
d6ab8113 | 7593 | if (GOT_symbol |
2bbd9c25 | 7594 | && GOT_symbol == i.op[n].disps->X_add_symbol |
d6ab8113 | 7595 | && (((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
7596 | || reloc_type == BFD_RELOC_X86_64_32S |
7597 | || (reloc_type == BFD_RELOC_64 | |
7598 | && object_64bit)) | |
d6ab8113 JB |
7599 | && (i.op[n].disps->X_op == O_symbol |
7600 | || (i.op[n].disps->X_op == O_add | |
7601 | && ((symbol_get_value_expression | |
7602 | (i.op[n].disps->X_op_symbol)->X_op) | |
7603 | == O_subtract)))) | |
7604 | || reloc_type == BFD_RELOC_32_PCREL)) | |
2bbd9c25 JJ |
7605 | { |
7606 | offsetT add; | |
7607 | ||
7608 | if (insn_start_frag == frag_now) | |
7609 | add = (p - frag_now->fr_literal) - insn_start_off; | |
7610 | else | |
7611 | { | |
7612 | fragS *fr; | |
7613 | ||
7614 | add = insn_start_frag->fr_fix - insn_start_off; | |
7615 | for (fr = insn_start_frag->fr_next; | |
7616 | fr && fr != frag_now; fr = fr->fr_next) | |
7617 | add += fr->fr_fix; | |
7618 | add += p - frag_now->fr_literal; | |
7619 | } | |
7620 | ||
4fa24527 | 7621 | if (!object_64bit) |
7b81dfbb AJ |
7622 | { |
7623 | reloc_type = BFD_RELOC_386_GOTPC; | |
7624 | i.op[n].imms->X_add_number += add; | |
7625 | } | |
7626 | else if (reloc_type == BFD_RELOC_64) | |
7627 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
d6ab8113 | 7628 | else |
7b81dfbb AJ |
7629 | /* Don't do the adjustment for x86-64, as there |
7630 | the pcrel addressing is relative to the _next_ | |
7631 | insn, and that is taken care of in other code. */ | |
d6ab8113 | 7632 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
2bbd9c25 | 7633 | } |
02a86693 L |
7634 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, |
7635 | size, i.op[n].disps, pcrel, | |
7636 | reloc_type); | |
7637 | /* Check for "call/jmp *mem", "mov mem, %reg", | |
7638 | "test %reg, mem" and "binop mem, %reg" where binop | |
7639 | is one of adc, add, and, cmp, or, sbb, sub, xor | |
0cb4071e L |
7640 | instructions. Always generate R_386_GOT32X for |
7641 | "sym*GOT" operand in 32-bit mode. */ | |
7642 | if ((generate_relax_relocations | |
7643 | || (!object_64bit | |
7644 | && i.rm.mode == 0 | |
7645 | && i.rm.regmem == 5)) | |
7646 | && (i.rm.mode == 2 | |
7647 | || (i.rm.mode == 0 && i.rm.regmem == 5)) | |
02a86693 L |
7648 | && ((i.operands == 1 |
7649 | && i.tm.base_opcode == 0xff | |
7650 | && (i.rm.reg == 2 || i.rm.reg == 4)) | |
7651 | || (i.operands == 2 | |
7652 | && (i.tm.base_opcode == 0x8b | |
7653 | || i.tm.base_opcode == 0x85 | |
7654 | || (i.tm.base_opcode & 0xc7) == 0x03)))) | |
7655 | { | |
7656 | if (object_64bit) | |
7657 | { | |
7658 | fixP->fx_tcbit = i.rex != 0; | |
7659 | if (i.base_reg | |
7660 | && (i.base_reg->reg_num == RegRip | |
7661 | || i.base_reg->reg_num == RegEip)) | |
7662 | fixP->fx_tcbit2 = 1; | |
7663 | } | |
7664 | else | |
7665 | fixP->fx_tcbit2 = 1; | |
7666 | } | |
29b0f896 AM |
7667 | } |
7668 | } | |
7669 | } | |
7670 | } | |
252b5132 | 7671 | |
29b0f896 | 7672 | static void |
64e74474 | 7673 | output_imm (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
7674 | { |
7675 | char *p; | |
7676 | unsigned int n; | |
252b5132 | 7677 | |
29b0f896 AM |
7678 | for (n = 0; n < i.operands; n++) |
7679 | { | |
43234a1e L |
7680 | /* Skip SAE/RC Imm operand in EVEX. They are already handled. */ |
7681 | if (i.rounding && (int) n == i.rounding->operand) | |
7682 | continue; | |
7683 | ||
40fb9820 | 7684 | if (operand_type_check (i.types[n], imm)) |
29b0f896 AM |
7685 | { |
7686 | if (i.op[n].imms->X_op == O_constant) | |
7687 | { | |
e205caa7 | 7688 | int size = imm_size (n); |
29b0f896 | 7689 | offsetT val; |
b4cac588 | 7690 | |
29b0f896 AM |
7691 | val = offset_in_range (i.op[n].imms->X_add_number, |
7692 | size); | |
7693 | p = frag_more (size); | |
7694 | md_number_to_chars (p, val, size); | |
7695 | } | |
7696 | else | |
7697 | { | |
7698 | /* Not absolute_section. | |
7699 | Need a 32-bit fixup (don't support 8bit | |
7700 | non-absolute imms). Try to support other | |
7701 | sizes ... */ | |
f86103b7 | 7702 | enum bfd_reloc_code_real reloc_type; |
e205caa7 L |
7703 | int size = imm_size (n); |
7704 | int sign; | |
29b0f896 | 7705 | |
40fb9820 | 7706 | if (i.types[n].bitfield.imm32s |
a7d61044 | 7707 | && (i.suffix == QWORD_MNEM_SUFFIX |
40fb9820 | 7708 | || (!i.suffix && i.tm.opcode_modifier.no_lsuf))) |
29b0f896 | 7709 | sign = 1; |
e205caa7 L |
7710 | else |
7711 | sign = 0; | |
520dc8e8 | 7712 | |
29b0f896 | 7713 | p = frag_more (size); |
d258b828 | 7714 | reloc_type = reloc (size, 0, sign, i.reloc[n]); |
f86103b7 | 7715 | |
2bbd9c25 JJ |
7716 | /* This is tough to explain. We end up with this one if we |
7717 | * have operands that look like | |
7718 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to | |
7719 | * obtain the absolute address of the GOT, and it is strongly | |
7720 | * preferable from a performance point of view to avoid using | |
7721 | * a runtime relocation for this. The actual sequence of | |
7722 | * instructions often look something like: | |
7723 | * | |
7724 | * call .L66 | |
7725 | * .L66: | |
7726 | * popl %ebx | |
7727 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
7728 | * | |
7729 | * The call and pop essentially return the absolute address | |
7730 | * of the label .L66 and store it in %ebx. The linker itself | |
7731 | * will ultimately change the first operand of the addl so | |
7732 | * that %ebx points to the GOT, but to keep things simple, the | |
7733 | * .o file must have this operand set so that it generates not | |
7734 | * the absolute address of .L66, but the absolute address of | |
7735 | * itself. This allows the linker itself simply treat a GOTPC | |
7736 | * relocation as asking for a pcrel offset to the GOT to be | |
7737 | * added in, and the addend of the relocation is stored in the | |
7738 | * operand field for the instruction itself. | |
7739 | * | |
7740 | * Our job here is to fix the operand so that it would add | |
7741 | * the correct offset so that %ebx would point to itself. The | |
7742 | * thing that is tricky is that .-.L66 will point to the | |
7743 | * beginning of the instruction, so we need to further modify | |
7744 | * the operand so that it will point to itself. There are | |
7745 | * other cases where you have something like: | |
7746 | * | |
7747 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
7748 | * | |
7749 | * and here no correction would be required. Internally in | |
7750 | * the assembler we treat operands of this form as not being | |
7751 | * pcrel since the '.' is explicitly mentioned, and I wonder | |
7752 | * whether it would simplify matters to do it this way. Who | |
7753 | * knows. In earlier versions of the PIC patches, the | |
7754 | * pcrel_adjust field was used to store the correction, but | |
7755 | * since the expression is not pcrel, I felt it would be | |
7756 | * confusing to do it this way. */ | |
7757 | ||
d6ab8113 | 7758 | if ((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
7759 | || reloc_type == BFD_RELOC_X86_64_32S |
7760 | || reloc_type == BFD_RELOC_64) | |
29b0f896 AM |
7761 | && GOT_symbol |
7762 | && GOT_symbol == i.op[n].imms->X_add_symbol | |
7763 | && (i.op[n].imms->X_op == O_symbol | |
7764 | || (i.op[n].imms->X_op == O_add | |
7765 | && ((symbol_get_value_expression | |
7766 | (i.op[n].imms->X_op_symbol)->X_op) | |
7767 | == O_subtract)))) | |
7768 | { | |
2bbd9c25 JJ |
7769 | offsetT add; |
7770 | ||
7771 | if (insn_start_frag == frag_now) | |
7772 | add = (p - frag_now->fr_literal) - insn_start_off; | |
7773 | else | |
7774 | { | |
7775 | fragS *fr; | |
7776 | ||
7777 | add = insn_start_frag->fr_fix - insn_start_off; | |
7778 | for (fr = insn_start_frag->fr_next; | |
7779 | fr && fr != frag_now; fr = fr->fr_next) | |
7780 | add += fr->fr_fix; | |
7781 | add += p - frag_now->fr_literal; | |
7782 | } | |
7783 | ||
4fa24527 | 7784 | if (!object_64bit) |
d6ab8113 | 7785 | reloc_type = BFD_RELOC_386_GOTPC; |
7b81dfbb | 7786 | else if (size == 4) |
d6ab8113 | 7787 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
7b81dfbb AJ |
7788 | else if (size == 8) |
7789 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
2bbd9c25 | 7790 | i.op[n].imms->X_add_number += add; |
29b0f896 | 7791 | } |
29b0f896 AM |
7792 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
7793 | i.op[n].imms, 0, reloc_type); | |
7794 | } | |
7795 | } | |
7796 | } | |
252b5132 RH |
7797 | } |
7798 | \f | |
d182319b JB |
7799 | /* x86_cons_fix_new is called via the expression parsing code when a |
7800 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
d182319b JB |
7801 | static int cons_sign = -1; |
7802 | ||
7803 | void | |
e3bb37b5 | 7804 | x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, |
62ebcb5c | 7805 | expressionS *exp, bfd_reloc_code_real_type r) |
d182319b | 7806 | { |
d258b828 | 7807 | r = reloc (len, 0, cons_sign, r); |
d182319b JB |
7808 | |
7809 | #ifdef TE_PE | |
7810 | if (exp->X_op == O_secrel) | |
7811 | { | |
7812 | exp->X_op = O_symbol; | |
7813 | r = BFD_RELOC_32_SECREL; | |
7814 | } | |
7815 | #endif | |
7816 | ||
7817 | fix_new_exp (frag, off, len, exp, 0, r); | |
7818 | } | |
7819 | ||
357d1bd8 L |
7820 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
7821 | purpose of the `.dc.a' internal pseudo-op. */ | |
7822 | ||
7823 | int | |
7824 | x86_address_bytes (void) | |
7825 | { | |
7826 | if ((stdoutput->arch_info->mach & bfd_mach_x64_32)) | |
7827 | return 4; | |
7828 | return stdoutput->arch_info->bits_per_address / 8; | |
7829 | } | |
7830 | ||
d382c579 TG |
7831 | #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \ |
7832 | || defined (LEX_AT) | |
d258b828 | 7833 | # define lex_got(reloc, adjust, types) NULL |
718ddfc0 | 7834 | #else |
f3c180ae AM |
7835 | /* Parse operands of the form |
7836 | <symbol>@GOTOFF+<nnn> | |
7837 | and similar .plt or .got references. | |
7838 | ||
7839 | If we find one, set up the correct relocation in RELOC and copy the | |
7840 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
7841 | parsing by the calling routine. Return this buffer, and if ADJUST | |
7842 | is non-null set it to the length of the string we removed from the | |
7843 | input line. Otherwise return NULL. */ | |
7844 | static char * | |
91d6fa6a | 7845 | lex_got (enum bfd_reloc_code_real *rel, |
64e74474 | 7846 | int *adjust, |
d258b828 | 7847 | i386_operand_type *types) |
f3c180ae | 7848 | { |
7b81dfbb AJ |
7849 | /* Some of the relocations depend on the size of what field is to |
7850 | be relocated. But in our callers i386_immediate and i386_displacement | |
7851 | we don't yet know the operand size (this will be set by insn | |
7852 | matching). Hence we record the word32 relocation here, | |
7853 | and adjust the reloc according to the real size in reloc(). */ | |
f3c180ae AM |
7854 | static const struct { |
7855 | const char *str; | |
cff8d58a | 7856 | int len; |
4fa24527 | 7857 | const enum bfd_reloc_code_real rel[2]; |
40fb9820 | 7858 | const i386_operand_type types64; |
f3c180ae | 7859 | } gotrel[] = { |
8ce3d284 | 7860 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
7861 | { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32, |
7862 | BFD_RELOC_SIZE32 }, | |
7863 | OPERAND_TYPE_IMM32_64 }, | |
8ce3d284 | 7864 | #endif |
cff8d58a L |
7865 | { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real, |
7866 | BFD_RELOC_X86_64_PLTOFF64 }, | |
40fb9820 | 7867 | OPERAND_TYPE_IMM64 }, |
cff8d58a L |
7868 | { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32, |
7869 | BFD_RELOC_X86_64_PLT32 }, | |
40fb9820 | 7870 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
7871 | { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real, |
7872 | BFD_RELOC_X86_64_GOTPLT64 }, | |
40fb9820 | 7873 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
7874 | { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF, |
7875 | BFD_RELOC_X86_64_GOTOFF64 }, | |
40fb9820 | 7876 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
7877 | { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real, |
7878 | BFD_RELOC_X86_64_GOTPCREL }, | |
40fb9820 | 7879 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
7880 | { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD, |
7881 | BFD_RELOC_X86_64_TLSGD }, | |
40fb9820 | 7882 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
7883 | { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM, |
7884 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 7885 | OPERAND_TYPE_NONE }, |
cff8d58a L |
7886 | { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real, |
7887 | BFD_RELOC_X86_64_TLSLD }, | |
40fb9820 | 7888 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
7889 | { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32, |
7890 | BFD_RELOC_X86_64_GOTTPOFF }, | |
40fb9820 | 7891 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
7892 | { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32, |
7893 | BFD_RELOC_X86_64_TPOFF32 }, | |
40fb9820 | 7894 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
7895 | { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE, |
7896 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 7897 | OPERAND_TYPE_NONE }, |
cff8d58a L |
7898 | { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32, |
7899 | BFD_RELOC_X86_64_DTPOFF32 }, | |
40fb9820 | 7900 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
7901 | { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE, |
7902 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 7903 | OPERAND_TYPE_NONE }, |
cff8d58a L |
7904 | { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE, |
7905 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 7906 | OPERAND_TYPE_NONE }, |
cff8d58a L |
7907 | { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32, |
7908 | BFD_RELOC_X86_64_GOT32 }, | |
40fb9820 | 7909 | OPERAND_TYPE_IMM32_32S_64_DISP32 }, |
cff8d58a L |
7910 | { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC, |
7911 | BFD_RELOC_X86_64_GOTPC32_TLSDESC }, | |
40fb9820 | 7912 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
7913 | { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL, |
7914 | BFD_RELOC_X86_64_TLSDESC_CALL }, | |
40fb9820 | 7915 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
f3c180ae AM |
7916 | }; |
7917 | char *cp; | |
7918 | unsigned int j; | |
7919 | ||
d382c579 | 7920 | #if defined (OBJ_MAYBE_ELF) |
718ddfc0 JB |
7921 | if (!IS_ELF) |
7922 | return NULL; | |
d382c579 | 7923 | #endif |
718ddfc0 | 7924 | |
f3c180ae | 7925 | for (cp = input_line_pointer; *cp != '@'; cp++) |
67c11a9b | 7926 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') |
f3c180ae AM |
7927 | return NULL; |
7928 | ||
47465058 | 7929 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) |
f3c180ae | 7930 | { |
cff8d58a | 7931 | int len = gotrel[j].len; |
28f81592 | 7932 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae | 7933 | { |
4fa24527 | 7934 | if (gotrel[j].rel[object_64bit] != 0) |
f3c180ae | 7935 | { |
28f81592 AM |
7936 | int first, second; |
7937 | char *tmpbuf, *past_reloc; | |
f3c180ae | 7938 | |
91d6fa6a | 7939 | *rel = gotrel[j].rel[object_64bit]; |
f3c180ae | 7940 | |
3956db08 JB |
7941 | if (types) |
7942 | { | |
7943 | if (flag_code != CODE_64BIT) | |
40fb9820 L |
7944 | { |
7945 | types->bitfield.imm32 = 1; | |
7946 | types->bitfield.disp32 = 1; | |
7947 | } | |
3956db08 JB |
7948 | else |
7949 | *types = gotrel[j].types64; | |
7950 | } | |
7951 | ||
8fd4256d | 7952 | if (j != 0 && GOT_symbol == NULL) |
f3c180ae AM |
7953 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); |
7954 | ||
28f81592 | 7955 | /* The length of the first part of our input line. */ |
f3c180ae | 7956 | first = cp - input_line_pointer; |
28f81592 AM |
7957 | |
7958 | /* The second part goes from after the reloc token until | |
67c11a9b | 7959 | (and including) an end_of_line char or comma. */ |
28f81592 | 7960 | past_reloc = cp + 1 + len; |
67c11a9b AM |
7961 | cp = past_reloc; |
7962 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
7963 | ++cp; | |
7964 | second = cp + 1 - past_reloc; | |
28f81592 AM |
7965 | |
7966 | /* Allocate and copy string. The trailing NUL shouldn't | |
7967 | be necessary, but be safe. */ | |
add39d23 | 7968 | tmpbuf = XNEWVEC (char, first + second + 2); |
f3c180ae | 7969 | memcpy (tmpbuf, input_line_pointer, first); |
0787a12d AM |
7970 | if (second != 0 && *past_reloc != ' ') |
7971 | /* Replace the relocation token with ' ', so that | |
7972 | errors like foo@GOTOFF1 will be detected. */ | |
7973 | tmpbuf[first++] = ' '; | |
af89796a L |
7974 | else |
7975 | /* Increment length by 1 if the relocation token is | |
7976 | removed. */ | |
7977 | len++; | |
7978 | if (adjust) | |
7979 | *adjust = len; | |
0787a12d AM |
7980 | memcpy (tmpbuf + first, past_reloc, second); |
7981 | tmpbuf[first + second] = '\0'; | |
f3c180ae AM |
7982 | return tmpbuf; |
7983 | } | |
7984 | ||
4fa24527 JB |
7985 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
7986 | gotrel[j].str, 1 << (5 + object_64bit)); | |
f3c180ae AM |
7987 | return NULL; |
7988 | } | |
7989 | } | |
7990 | ||
7991 | /* Might be a symbol version string. Don't as_bad here. */ | |
7992 | return NULL; | |
7993 | } | |
4e4f7c87 | 7994 | #endif |
f3c180ae | 7995 | |
a988325c NC |
7996 | #ifdef TE_PE |
7997 | #ifdef lex_got | |
7998 | #undef lex_got | |
7999 | #endif | |
8000 | /* Parse operands of the form | |
8001 | <symbol>@SECREL32+<nnn> | |
8002 | ||
8003 | If we find one, set up the correct relocation in RELOC and copy the | |
8004 | input string, minus the `@SECREL32' into a malloc'd buffer for | |
8005 | parsing by the calling routine. Return this buffer, and if ADJUST | |
8006 | is non-null set it to the length of the string we removed from the | |
34bca508 L |
8007 | input line. Otherwise return NULL. |
8008 | ||
a988325c NC |
8009 | This function is copied from the ELF version above adjusted for PE targets. */ |
8010 | ||
8011 | static char * | |
8012 | lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED, | |
8013 | int *adjust ATTRIBUTE_UNUSED, | |
d258b828 | 8014 | i386_operand_type *types) |
a988325c NC |
8015 | { |
8016 | static const struct | |
8017 | { | |
8018 | const char *str; | |
8019 | int len; | |
8020 | const enum bfd_reloc_code_real rel[2]; | |
8021 | const i386_operand_type types64; | |
8022 | } | |
8023 | gotrel[] = | |
8024 | { | |
8025 | { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL, | |
8026 | BFD_RELOC_32_SECREL }, | |
8027 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, | |
8028 | }; | |
8029 | ||
8030 | char *cp; | |
8031 | unsigned j; | |
8032 | ||
8033 | for (cp = input_line_pointer; *cp != '@'; cp++) | |
8034 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') | |
8035 | return NULL; | |
8036 | ||
8037 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) | |
8038 | { | |
8039 | int len = gotrel[j].len; | |
8040 | ||
8041 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) | |
8042 | { | |
8043 | if (gotrel[j].rel[object_64bit] != 0) | |
8044 | { | |
8045 | int first, second; | |
8046 | char *tmpbuf, *past_reloc; | |
8047 | ||
8048 | *rel = gotrel[j].rel[object_64bit]; | |
8049 | if (adjust) | |
8050 | *adjust = len; | |
8051 | ||
8052 | if (types) | |
8053 | { | |
8054 | if (flag_code != CODE_64BIT) | |
8055 | { | |
8056 | types->bitfield.imm32 = 1; | |
8057 | types->bitfield.disp32 = 1; | |
8058 | } | |
8059 | else | |
8060 | *types = gotrel[j].types64; | |
8061 | } | |
8062 | ||
8063 | /* The length of the first part of our input line. */ | |
8064 | first = cp - input_line_pointer; | |
8065 | ||
8066 | /* The second part goes from after the reloc token until | |
8067 | (and including) an end_of_line char or comma. */ | |
8068 | past_reloc = cp + 1 + len; | |
8069 | cp = past_reloc; | |
8070 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
8071 | ++cp; | |
8072 | second = cp + 1 - past_reloc; | |
8073 | ||
8074 | /* Allocate and copy string. The trailing NUL shouldn't | |
8075 | be necessary, but be safe. */ | |
add39d23 | 8076 | tmpbuf = XNEWVEC (char, first + second + 2); |
a988325c NC |
8077 | memcpy (tmpbuf, input_line_pointer, first); |
8078 | if (second != 0 && *past_reloc != ' ') | |
8079 | /* Replace the relocation token with ' ', so that | |
8080 | errors like foo@SECLREL321 will be detected. */ | |
8081 | tmpbuf[first++] = ' '; | |
8082 | memcpy (tmpbuf + first, past_reloc, second); | |
8083 | tmpbuf[first + second] = '\0'; | |
8084 | return tmpbuf; | |
8085 | } | |
8086 | ||
8087 | as_bad (_("@%s reloc is not supported with %d-bit output format"), | |
8088 | gotrel[j].str, 1 << (5 + object_64bit)); | |
8089 | return NULL; | |
8090 | } | |
8091 | } | |
8092 | ||
8093 | /* Might be a symbol version string. Don't as_bad here. */ | |
8094 | return NULL; | |
8095 | } | |
8096 | ||
8097 | #endif /* TE_PE */ | |
8098 | ||
62ebcb5c | 8099 | bfd_reloc_code_real_type |
e3bb37b5 | 8100 | x86_cons (expressionS *exp, int size) |
f3c180ae | 8101 | { |
62ebcb5c AM |
8102 | bfd_reloc_code_real_type got_reloc = NO_RELOC; |
8103 | ||
ee86248c JB |
8104 | intel_syntax = -intel_syntax; |
8105 | ||
3c7b9c2c | 8106 | exp->X_md = 0; |
4fa24527 | 8107 | if (size == 4 || (object_64bit && size == 8)) |
f3c180ae AM |
8108 | { |
8109 | /* Handle @GOTOFF and the like in an expression. */ | |
8110 | char *save; | |
8111 | char *gotfree_input_line; | |
4a57f2cf | 8112 | int adjust = 0; |
f3c180ae AM |
8113 | |
8114 | save = input_line_pointer; | |
d258b828 | 8115 | gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); |
f3c180ae AM |
8116 | if (gotfree_input_line) |
8117 | input_line_pointer = gotfree_input_line; | |
8118 | ||
8119 | expression (exp); | |
8120 | ||
8121 | if (gotfree_input_line) | |
8122 | { | |
8123 | /* expression () has merrily parsed up to the end of line, | |
8124 | or a comma - in the wrong buffer. Transfer how far | |
8125 | input_line_pointer has moved to the right buffer. */ | |
8126 | input_line_pointer = (save | |
8127 | + (input_line_pointer - gotfree_input_line) | |
8128 | + adjust); | |
8129 | free (gotfree_input_line); | |
3992d3b7 AM |
8130 | if (exp->X_op == O_constant |
8131 | || exp->X_op == O_absent | |
8132 | || exp->X_op == O_illegal | |
0398aac5 | 8133 | || exp->X_op == O_register |
3992d3b7 AM |
8134 | || exp->X_op == O_big) |
8135 | { | |
8136 | char c = *input_line_pointer; | |
8137 | *input_line_pointer = 0; | |
8138 | as_bad (_("missing or invalid expression `%s'"), save); | |
8139 | *input_line_pointer = c; | |
8140 | } | |
f3c180ae AM |
8141 | } |
8142 | } | |
8143 | else | |
8144 | expression (exp); | |
ee86248c JB |
8145 | |
8146 | intel_syntax = -intel_syntax; | |
8147 | ||
8148 | if (intel_syntax) | |
8149 | i386_intel_simplify (exp); | |
62ebcb5c AM |
8150 | |
8151 | return got_reloc; | |
f3c180ae | 8152 | } |
f3c180ae | 8153 | |
9f32dd5b L |
8154 | static void |
8155 | signed_cons (int size) | |
6482c264 | 8156 | { |
d182319b JB |
8157 | if (flag_code == CODE_64BIT) |
8158 | cons_sign = 1; | |
8159 | cons (size); | |
8160 | cons_sign = -1; | |
6482c264 NC |
8161 | } |
8162 | ||
d182319b | 8163 | #ifdef TE_PE |
6482c264 | 8164 | static void |
7016a5d5 | 8165 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
6482c264 NC |
8166 | { |
8167 | expressionS exp; | |
8168 | ||
8169 | do | |
8170 | { | |
8171 | expression (&exp); | |
8172 | if (exp.X_op == O_symbol) | |
8173 | exp.X_op = O_secrel; | |
8174 | ||
8175 | emit_expr (&exp, 4); | |
8176 | } | |
8177 | while (*input_line_pointer++ == ','); | |
8178 | ||
8179 | input_line_pointer--; | |
8180 | demand_empty_rest_of_line (); | |
8181 | } | |
6482c264 NC |
8182 | #endif |
8183 | ||
43234a1e L |
8184 | /* Handle Vector operations. */ |
8185 | ||
8186 | static char * | |
8187 | check_VecOperations (char *op_string, char *op_end) | |
8188 | { | |
8189 | const reg_entry *mask; | |
8190 | const char *saved; | |
8191 | char *end_op; | |
8192 | ||
8193 | while (*op_string | |
8194 | && (op_end == NULL || op_string < op_end)) | |
8195 | { | |
8196 | saved = op_string; | |
8197 | if (*op_string == '{') | |
8198 | { | |
8199 | op_string++; | |
8200 | ||
8201 | /* Check broadcasts. */ | |
8202 | if (strncmp (op_string, "1to", 3) == 0) | |
8203 | { | |
8204 | int bcst_type; | |
8205 | ||
8206 | if (i.broadcast) | |
8207 | goto duplicated_vec_op; | |
8208 | ||
8209 | op_string += 3; | |
8210 | if (*op_string == '8') | |
8211 | bcst_type = BROADCAST_1TO8; | |
b28d1bda IT |
8212 | else if (*op_string == '4') |
8213 | bcst_type = BROADCAST_1TO4; | |
8214 | else if (*op_string == '2') | |
8215 | bcst_type = BROADCAST_1TO2; | |
43234a1e L |
8216 | else if (*op_string == '1' |
8217 | && *(op_string+1) == '6') | |
8218 | { | |
8219 | bcst_type = BROADCAST_1TO16; | |
8220 | op_string++; | |
8221 | } | |
8222 | else | |
8223 | { | |
8224 | as_bad (_("Unsupported broadcast: `%s'"), saved); | |
8225 | return NULL; | |
8226 | } | |
8227 | op_string++; | |
8228 | ||
8229 | broadcast_op.type = bcst_type; | |
8230 | broadcast_op.operand = this_operand; | |
8231 | i.broadcast = &broadcast_op; | |
8232 | } | |
8233 | /* Check masking operation. */ | |
8234 | else if ((mask = parse_register (op_string, &end_op)) != NULL) | |
8235 | { | |
8236 | /* k0 can't be used for write mask. */ | |
6d2cd6b2 | 8237 | if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0) |
43234a1e | 8238 | { |
6d2cd6b2 JB |
8239 | as_bad (_("`%s%s' can't be used for write mask"), |
8240 | register_prefix, mask->reg_name); | |
43234a1e L |
8241 | return NULL; |
8242 | } | |
8243 | ||
8244 | if (!i.mask) | |
8245 | { | |
8246 | mask_op.mask = mask; | |
8247 | mask_op.zeroing = 0; | |
8248 | mask_op.operand = this_operand; | |
8249 | i.mask = &mask_op; | |
8250 | } | |
8251 | else | |
8252 | { | |
8253 | if (i.mask->mask) | |
8254 | goto duplicated_vec_op; | |
8255 | ||
8256 | i.mask->mask = mask; | |
8257 | ||
8258 | /* Only "{z}" is allowed here. No need to check | |
8259 | zeroing mask explicitly. */ | |
8260 | if (i.mask->operand != this_operand) | |
8261 | { | |
8262 | as_bad (_("invalid write mask `%s'"), saved); | |
8263 | return NULL; | |
8264 | } | |
8265 | } | |
8266 | ||
8267 | op_string = end_op; | |
8268 | } | |
8269 | /* Check zeroing-flag for masking operation. */ | |
8270 | else if (*op_string == 'z') | |
8271 | { | |
8272 | if (!i.mask) | |
8273 | { | |
8274 | mask_op.mask = NULL; | |
8275 | mask_op.zeroing = 1; | |
8276 | mask_op.operand = this_operand; | |
8277 | i.mask = &mask_op; | |
8278 | } | |
8279 | else | |
8280 | { | |
8281 | if (i.mask->zeroing) | |
8282 | { | |
8283 | duplicated_vec_op: | |
8284 | as_bad (_("duplicated `%s'"), saved); | |
8285 | return NULL; | |
8286 | } | |
8287 | ||
8288 | i.mask->zeroing = 1; | |
8289 | ||
8290 | /* Only "{%k}" is allowed here. No need to check mask | |
8291 | register explicitly. */ | |
8292 | if (i.mask->operand != this_operand) | |
8293 | { | |
8294 | as_bad (_("invalid zeroing-masking `%s'"), | |
8295 | saved); | |
8296 | return NULL; | |
8297 | } | |
8298 | } | |
8299 | ||
8300 | op_string++; | |
8301 | } | |
8302 | else | |
8303 | goto unknown_vec_op; | |
8304 | ||
8305 | if (*op_string != '}') | |
8306 | { | |
8307 | as_bad (_("missing `}' in `%s'"), saved); | |
8308 | return NULL; | |
8309 | } | |
8310 | op_string++; | |
8311 | continue; | |
8312 | } | |
8313 | unknown_vec_op: | |
8314 | /* We don't know this one. */ | |
8315 | as_bad (_("unknown vector operation: `%s'"), saved); | |
8316 | return NULL; | |
8317 | } | |
8318 | ||
6d2cd6b2 JB |
8319 | if (i.mask && i.mask->zeroing && !i.mask->mask) |
8320 | { | |
8321 | as_bad (_("zeroing-masking only allowed with write mask")); | |
8322 | return NULL; | |
8323 | } | |
8324 | ||
43234a1e L |
8325 | return op_string; |
8326 | } | |
8327 | ||
252b5132 | 8328 | static int |
70e41ade | 8329 | i386_immediate (char *imm_start) |
252b5132 RH |
8330 | { |
8331 | char *save_input_line_pointer; | |
f3c180ae | 8332 | char *gotfree_input_line; |
252b5132 | 8333 | segT exp_seg = 0; |
47926f60 | 8334 | expressionS *exp; |
40fb9820 L |
8335 | i386_operand_type types; |
8336 | ||
0dfbf9d7 | 8337 | operand_type_set (&types, ~0); |
252b5132 RH |
8338 | |
8339 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
8340 | { | |
31b2323c L |
8341 | as_bad (_("at most %d immediate operands are allowed"), |
8342 | MAX_IMMEDIATE_OPERANDS); | |
252b5132 RH |
8343 | return 0; |
8344 | } | |
8345 | ||
8346 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 8347 | i.op[this_operand].imms = exp; |
252b5132 RH |
8348 | |
8349 | if (is_space_char (*imm_start)) | |
8350 | ++imm_start; | |
8351 | ||
8352 | save_input_line_pointer = input_line_pointer; | |
8353 | input_line_pointer = imm_start; | |
8354 | ||
d258b828 | 8355 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
8356 | if (gotfree_input_line) |
8357 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
8358 | |
8359 | exp_seg = expression (exp); | |
8360 | ||
83183c0c | 8361 | SKIP_WHITESPACE (); |
43234a1e L |
8362 | |
8363 | /* Handle vector operations. */ | |
8364 | if (*input_line_pointer == '{') | |
8365 | { | |
8366 | input_line_pointer = check_VecOperations (input_line_pointer, | |
8367 | NULL); | |
8368 | if (input_line_pointer == NULL) | |
8369 | return 0; | |
8370 | } | |
8371 | ||
252b5132 | 8372 | if (*input_line_pointer) |
f3c180ae | 8373 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
8374 | |
8375 | input_line_pointer = save_input_line_pointer; | |
f3c180ae | 8376 | if (gotfree_input_line) |
ee86248c JB |
8377 | { |
8378 | free (gotfree_input_line); | |
8379 | ||
8380 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
8381 | exp->X_op = O_illegal; | |
8382 | } | |
8383 | ||
8384 | return i386_finalize_immediate (exp_seg, exp, types, imm_start); | |
8385 | } | |
252b5132 | 8386 | |
ee86248c JB |
8387 | static int |
8388 | i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
8389 | i386_operand_type types, const char *imm_start) | |
8390 | { | |
8391 | if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big) | |
252b5132 | 8392 | { |
313c53d1 L |
8393 | if (imm_start) |
8394 | as_bad (_("missing or invalid immediate expression `%s'"), | |
8395 | imm_start); | |
3992d3b7 | 8396 | return 0; |
252b5132 | 8397 | } |
3e73aa7c | 8398 | else if (exp->X_op == O_constant) |
252b5132 | 8399 | { |
47926f60 | 8400 | /* Size it properly later. */ |
40fb9820 | 8401 | i.types[this_operand].bitfield.imm64 = 1; |
13f864ae L |
8402 | /* If not 64bit, sign extend val. */ |
8403 | if (flag_code != CODE_64BIT | |
4eed87de AM |
8404 | && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) |
8405 | exp->X_add_number | |
8406 | = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
252b5132 | 8407 | } |
4c63da97 | 8408 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
f86103b7 | 8409 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 8410 | && exp_seg != absolute_section |
47926f60 | 8411 | && exp_seg != text_section |
24eab124 AM |
8412 | && exp_seg != data_section |
8413 | && exp_seg != bss_section | |
8414 | && exp_seg != undefined_section | |
f86103b7 | 8415 | && !bfd_is_com_section (exp_seg)) |
252b5132 | 8416 | { |
d0b47220 | 8417 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
252b5132 RH |
8418 | return 0; |
8419 | } | |
8420 | #endif | |
a841bdf5 | 8421 | else if (!intel_syntax && exp_seg == reg_section) |
bb8f5920 | 8422 | { |
313c53d1 L |
8423 | if (imm_start) |
8424 | as_bad (_("illegal immediate register operand %s"), imm_start); | |
bb8f5920 L |
8425 | return 0; |
8426 | } | |
252b5132 RH |
8427 | else |
8428 | { | |
8429 | /* This is an address. The size of the address will be | |
24eab124 | 8430 | determined later, depending on destination register, |
3e73aa7c | 8431 | suffix, or the default for the section. */ |
40fb9820 L |
8432 | i.types[this_operand].bitfield.imm8 = 1; |
8433 | i.types[this_operand].bitfield.imm16 = 1; | |
8434 | i.types[this_operand].bitfield.imm32 = 1; | |
8435 | i.types[this_operand].bitfield.imm32s = 1; | |
8436 | i.types[this_operand].bitfield.imm64 = 1; | |
c6fb90c8 L |
8437 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
8438 | types); | |
252b5132 RH |
8439 | } |
8440 | ||
8441 | return 1; | |
8442 | } | |
8443 | ||
551c1ca1 | 8444 | static char * |
e3bb37b5 | 8445 | i386_scale (char *scale) |
252b5132 | 8446 | { |
551c1ca1 AM |
8447 | offsetT val; |
8448 | char *save = input_line_pointer; | |
252b5132 | 8449 | |
551c1ca1 AM |
8450 | input_line_pointer = scale; |
8451 | val = get_absolute_expression (); | |
8452 | ||
8453 | switch (val) | |
252b5132 | 8454 | { |
551c1ca1 | 8455 | case 1: |
252b5132 RH |
8456 | i.log2_scale_factor = 0; |
8457 | break; | |
551c1ca1 | 8458 | case 2: |
252b5132 RH |
8459 | i.log2_scale_factor = 1; |
8460 | break; | |
551c1ca1 | 8461 | case 4: |
252b5132 RH |
8462 | i.log2_scale_factor = 2; |
8463 | break; | |
551c1ca1 | 8464 | case 8: |
252b5132 RH |
8465 | i.log2_scale_factor = 3; |
8466 | break; | |
8467 | default: | |
a724f0f4 JB |
8468 | { |
8469 | char sep = *input_line_pointer; | |
8470 | ||
8471 | *input_line_pointer = '\0'; | |
8472 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
8473 | scale); | |
8474 | *input_line_pointer = sep; | |
8475 | input_line_pointer = save; | |
8476 | return NULL; | |
8477 | } | |
252b5132 | 8478 | } |
29b0f896 | 8479 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
252b5132 RH |
8480 | { |
8481 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 8482 | 1 << i.log2_scale_factor); |
252b5132 | 8483 | i.log2_scale_factor = 0; |
252b5132 | 8484 | } |
551c1ca1 AM |
8485 | scale = input_line_pointer; |
8486 | input_line_pointer = save; | |
8487 | return scale; | |
252b5132 RH |
8488 | } |
8489 | ||
252b5132 | 8490 | static int |
e3bb37b5 | 8491 | i386_displacement (char *disp_start, char *disp_end) |
252b5132 | 8492 | { |
29b0f896 | 8493 | expressionS *exp; |
252b5132 RH |
8494 | segT exp_seg = 0; |
8495 | char *save_input_line_pointer; | |
f3c180ae | 8496 | char *gotfree_input_line; |
40fb9820 L |
8497 | int override; |
8498 | i386_operand_type bigdisp, types = anydisp; | |
3992d3b7 | 8499 | int ret; |
252b5132 | 8500 | |
31b2323c L |
8501 | if (i.disp_operands == MAX_MEMORY_OPERANDS) |
8502 | { | |
8503 | as_bad (_("at most %d displacement operands are allowed"), | |
8504 | MAX_MEMORY_OPERANDS); | |
8505 | return 0; | |
8506 | } | |
8507 | ||
0dfbf9d7 | 8508 | operand_type_set (&bigdisp, 0); |
40fb9820 L |
8509 | if ((i.types[this_operand].bitfield.jumpabsolute) |
8510 | || (!current_templates->start->opcode_modifier.jump | |
8511 | && !current_templates->start->opcode_modifier.jumpdword)) | |
e05278af | 8512 | { |
40fb9820 | 8513 | bigdisp.bitfield.disp32 = 1; |
e05278af | 8514 | override = (i.prefix[ADDR_PREFIX] != 0); |
40fb9820 L |
8515 | if (flag_code == CODE_64BIT) |
8516 | { | |
8517 | if (!override) | |
8518 | { | |
8519 | bigdisp.bitfield.disp32s = 1; | |
8520 | bigdisp.bitfield.disp64 = 1; | |
8521 | } | |
8522 | } | |
8523 | else if ((flag_code == CODE_16BIT) ^ override) | |
8524 | { | |
8525 | bigdisp.bitfield.disp32 = 0; | |
8526 | bigdisp.bitfield.disp16 = 1; | |
8527 | } | |
e05278af JB |
8528 | } |
8529 | else | |
8530 | { | |
8531 | /* For PC-relative branches, the width of the displacement | |
8532 | is dependent upon data size, not address size. */ | |
e05278af | 8533 | override = (i.prefix[DATA_PREFIX] != 0); |
40fb9820 L |
8534 | if (flag_code == CODE_64BIT) |
8535 | { | |
8536 | if (override || i.suffix == WORD_MNEM_SUFFIX) | |
8537 | bigdisp.bitfield.disp16 = 1; | |
8538 | else | |
8539 | { | |
8540 | bigdisp.bitfield.disp32 = 1; | |
8541 | bigdisp.bitfield.disp32s = 1; | |
8542 | } | |
8543 | } | |
8544 | else | |
e05278af JB |
8545 | { |
8546 | if (!override) | |
8547 | override = (i.suffix == (flag_code != CODE_16BIT | |
8548 | ? WORD_MNEM_SUFFIX | |
8549 | : LONG_MNEM_SUFFIX)); | |
40fb9820 L |
8550 | bigdisp.bitfield.disp32 = 1; |
8551 | if ((flag_code == CODE_16BIT) ^ override) | |
8552 | { | |
8553 | bigdisp.bitfield.disp32 = 0; | |
8554 | bigdisp.bitfield.disp16 = 1; | |
8555 | } | |
e05278af | 8556 | } |
e05278af | 8557 | } |
c6fb90c8 L |
8558 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
8559 | bigdisp); | |
252b5132 RH |
8560 | |
8561 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 8562 | i.op[this_operand].disps = exp; |
252b5132 RH |
8563 | i.disp_operands++; |
8564 | save_input_line_pointer = input_line_pointer; | |
8565 | input_line_pointer = disp_start; | |
8566 | END_STRING_AND_SAVE (disp_end); | |
8567 | ||
8568 | #ifndef GCC_ASM_O_HACK | |
8569 | #define GCC_ASM_O_HACK 0 | |
8570 | #endif | |
8571 | #if GCC_ASM_O_HACK | |
8572 | END_STRING_AND_SAVE (disp_end + 1); | |
40fb9820 | 8573 | if (i.types[this_operand].bitfield.baseIndex |
24eab124 | 8574 | && displacement_string_end[-1] == '+') |
252b5132 RH |
8575 | { |
8576 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
8577 | constraint within gcc asm statements. |
8578 | For instance: | |
8579 | ||
8580 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
8581 | __asm__ __volatile__ ( \ | |
8582 | "movw %w2,%0\n\t" \ | |
8583 | "movw %w1,2+%0\n\t" \ | |
8584 | "rorl $16,%1\n\t" \ | |
8585 | "movb %b1,4+%0\n\t" \ | |
8586 | "movb %4,5+%0\n\t" \ | |
8587 | "movb $0,6+%0\n\t" \ | |
8588 | "movb %h1,7+%0\n\t" \ | |
8589 | "rorl $16,%1" \ | |
8590 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
8591 | ||
8592 | This works great except that the output assembler ends | |
8593 | up looking a bit weird if it turns out that there is | |
8594 | no offset. You end up producing code that looks like: | |
8595 | ||
8596 | #APP | |
8597 | movw $235,(%eax) | |
8598 | movw %dx,2+(%eax) | |
8599 | rorl $16,%edx | |
8600 | movb %dl,4+(%eax) | |
8601 | movb $137,5+(%eax) | |
8602 | movb $0,6+(%eax) | |
8603 | movb %dh,7+(%eax) | |
8604 | rorl $16,%edx | |
8605 | #NO_APP | |
8606 | ||
47926f60 | 8607 | So here we provide the missing zero. */ |
24eab124 AM |
8608 | |
8609 | *displacement_string_end = '0'; | |
252b5132 RH |
8610 | } |
8611 | #endif | |
d258b828 | 8612 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
8613 | if (gotfree_input_line) |
8614 | input_line_pointer = gotfree_input_line; | |
252b5132 | 8615 | |
24eab124 | 8616 | exp_seg = expression (exp); |
252b5132 | 8617 | |
636c26b0 AM |
8618 | SKIP_WHITESPACE (); |
8619 | if (*input_line_pointer) | |
8620 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
8621 | #if GCC_ASM_O_HACK | |
8622 | RESTORE_END_STRING (disp_end + 1); | |
8623 | #endif | |
636c26b0 | 8624 | input_line_pointer = save_input_line_pointer; |
636c26b0 | 8625 | if (gotfree_input_line) |
ee86248c JB |
8626 | { |
8627 | free (gotfree_input_line); | |
8628 | ||
8629 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
8630 | exp->X_op = O_illegal; | |
8631 | } | |
8632 | ||
8633 | ret = i386_finalize_displacement (exp_seg, exp, types, disp_start); | |
8634 | ||
8635 | RESTORE_END_STRING (disp_end); | |
8636 | ||
8637 | return ret; | |
8638 | } | |
8639 | ||
8640 | static int | |
8641 | i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
8642 | i386_operand_type types, const char *disp_start) | |
8643 | { | |
8644 | i386_operand_type bigdisp; | |
8645 | int ret = 1; | |
636c26b0 | 8646 | |
24eab124 AM |
8647 | /* We do this to make sure that the section symbol is in |
8648 | the symbol table. We will ultimately change the relocation | |
47926f60 | 8649 | to be relative to the beginning of the section. */ |
1ae12ab7 | 8650 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
d6ab8113 JB |
8651 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
8652 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) | |
24eab124 | 8653 | { |
636c26b0 | 8654 | if (exp->X_op != O_symbol) |
3992d3b7 | 8655 | goto inv_disp; |
636c26b0 | 8656 | |
e5cb08ac | 8657 | if (S_IS_LOCAL (exp->X_add_symbol) |
c64efb4b L |
8658 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section |
8659 | && S_GET_SEGMENT (exp->X_add_symbol) != expr_section) | |
24eab124 | 8660 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); |
24eab124 AM |
8661 | exp->X_op = O_subtract; |
8662 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 | 8663 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
29b0f896 | 8664 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
d6ab8113 JB |
8665 | else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
8666 | i.reloc[this_operand] = BFD_RELOC_64; | |
23df1078 | 8667 | else |
29b0f896 | 8668 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 8669 | } |
252b5132 | 8670 | |
3992d3b7 AM |
8671 | else if (exp->X_op == O_absent |
8672 | || exp->X_op == O_illegal | |
ee86248c | 8673 | || exp->X_op == O_big) |
2daf4fd8 | 8674 | { |
3992d3b7 AM |
8675 | inv_disp: |
8676 | as_bad (_("missing or invalid displacement expression `%s'"), | |
2daf4fd8 | 8677 | disp_start); |
3992d3b7 | 8678 | ret = 0; |
2daf4fd8 AM |
8679 | } |
8680 | ||
0e1147d9 L |
8681 | else if (flag_code == CODE_64BIT |
8682 | && !i.prefix[ADDR_PREFIX] | |
8683 | && exp->X_op == O_constant) | |
8684 | { | |
8685 | /* Since displacement is signed extended to 64bit, don't allow | |
8686 | disp32 and turn off disp32s if they are out of range. */ | |
8687 | i.types[this_operand].bitfield.disp32 = 0; | |
8688 | if (!fits_in_signed_long (exp->X_add_number)) | |
8689 | { | |
8690 | i.types[this_operand].bitfield.disp32s = 0; | |
8691 | if (i.types[this_operand].bitfield.baseindex) | |
8692 | { | |
8693 | as_bad (_("0x%lx out range of signed 32bit displacement"), | |
8694 | (long) exp->X_add_number); | |
8695 | ret = 0; | |
8696 | } | |
8697 | } | |
8698 | } | |
8699 | ||
4c63da97 | 8700 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
3992d3b7 AM |
8701 | else if (exp->X_op != O_constant |
8702 | && OUTPUT_FLAVOR == bfd_target_aout_flavour | |
8703 | && exp_seg != absolute_section | |
8704 | && exp_seg != text_section | |
8705 | && exp_seg != data_section | |
8706 | && exp_seg != bss_section | |
8707 | && exp_seg != undefined_section | |
8708 | && !bfd_is_com_section (exp_seg)) | |
24eab124 | 8709 | { |
d0b47220 | 8710 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
3992d3b7 | 8711 | ret = 0; |
24eab124 | 8712 | } |
252b5132 | 8713 | #endif |
3956db08 | 8714 | |
40fb9820 L |
8715 | /* Check if this is a displacement only operand. */ |
8716 | bigdisp = i.types[this_operand]; | |
8717 | bigdisp.bitfield.disp8 = 0; | |
8718 | bigdisp.bitfield.disp16 = 0; | |
8719 | bigdisp.bitfield.disp32 = 0; | |
8720 | bigdisp.bitfield.disp32s = 0; | |
8721 | bigdisp.bitfield.disp64 = 0; | |
0dfbf9d7 | 8722 | if (operand_type_all_zero (&bigdisp)) |
c6fb90c8 L |
8723 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
8724 | types); | |
3956db08 | 8725 | |
3992d3b7 | 8726 | return ret; |
252b5132 RH |
8727 | } |
8728 | ||
2abc2bec JB |
8729 | /* Return the active addressing mode, taking address override and |
8730 | registers forming the address into consideration. Update the | |
8731 | address override prefix if necessary. */ | |
47926f60 | 8732 | |
2abc2bec JB |
8733 | static enum flag_code |
8734 | i386_addressing_mode (void) | |
252b5132 | 8735 | { |
be05d201 L |
8736 | enum flag_code addr_mode; |
8737 | ||
8738 | if (i.prefix[ADDR_PREFIX]) | |
8739 | addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT; | |
8740 | else | |
8741 | { | |
8742 | addr_mode = flag_code; | |
8743 | ||
24eab124 | 8744 | #if INFER_ADDR_PREFIX |
be05d201 L |
8745 | if (i.mem_operands == 0) |
8746 | { | |
8747 | /* Infer address prefix from the first memory operand. */ | |
8748 | const reg_entry *addr_reg = i.base_reg; | |
8749 | ||
8750 | if (addr_reg == NULL) | |
8751 | addr_reg = i.index_reg; | |
eecb386c | 8752 | |
be05d201 L |
8753 | if (addr_reg) |
8754 | { | |
8755 | if (addr_reg->reg_num == RegEip | |
8756 | || addr_reg->reg_num == RegEiz | |
dc821c5f | 8757 | || addr_reg->reg_type.bitfield.dword) |
be05d201 L |
8758 | addr_mode = CODE_32BIT; |
8759 | else if (flag_code != CODE_64BIT | |
dc821c5f | 8760 | && addr_reg->reg_type.bitfield.word) |
be05d201 L |
8761 | addr_mode = CODE_16BIT; |
8762 | ||
8763 | if (addr_mode != flag_code) | |
8764 | { | |
8765 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
8766 | i.prefixes += 1; | |
8767 | /* Change the size of any displacement too. At most one | |
8768 | of Disp16 or Disp32 is set. | |
8769 | FIXME. There doesn't seem to be any real need for | |
8770 | separate Disp16 and Disp32 flags. The same goes for | |
8771 | Imm16 and Imm32. Removing them would probably clean | |
8772 | up the code quite a lot. */ | |
8773 | if (flag_code != CODE_64BIT | |
8774 | && (i.types[this_operand].bitfield.disp16 | |
8775 | || i.types[this_operand].bitfield.disp32)) | |
8776 | i.types[this_operand] | |
8777 | = operand_type_xor (i.types[this_operand], disp16_32); | |
8778 | } | |
8779 | } | |
8780 | } | |
24eab124 | 8781 | #endif |
be05d201 L |
8782 | } |
8783 | ||
2abc2bec JB |
8784 | return addr_mode; |
8785 | } | |
8786 | ||
8787 | /* Make sure the memory operand we've been dealt is valid. | |
8788 | Return 1 on success, 0 on a failure. */ | |
8789 | ||
8790 | static int | |
8791 | i386_index_check (const char *operand_string) | |
8792 | { | |
8793 | const char *kind = "base/index"; | |
8794 | enum flag_code addr_mode = i386_addressing_mode (); | |
8795 | ||
fc0763e6 JB |
8796 | if (current_templates->start->opcode_modifier.isstring |
8797 | && !current_templates->start->opcode_modifier.immext | |
8798 | && (current_templates->end[-1].opcode_modifier.isstring | |
8799 | || i.mem_operands)) | |
8800 | { | |
8801 | /* Memory operands of string insns are special in that they only allow | |
8802 | a single register (rDI, rSI, or rBX) as their memory address. */ | |
be05d201 L |
8803 | const reg_entry *expected_reg; |
8804 | static const char *di_si[][2] = | |
8805 | { | |
8806 | { "esi", "edi" }, | |
8807 | { "si", "di" }, | |
8808 | { "rsi", "rdi" } | |
8809 | }; | |
8810 | static const char *bx[] = { "ebx", "bx", "rbx" }; | |
fc0763e6 JB |
8811 | |
8812 | kind = "string address"; | |
8813 | ||
8325cc63 | 8814 | if (current_templates->start->opcode_modifier.repprefixok) |
fc0763e6 JB |
8815 | { |
8816 | i386_operand_type type = current_templates->end[-1].operand_types[0]; | |
8817 | ||
8818 | if (!type.bitfield.baseindex | |
8819 | || ((!i.mem_operands != !intel_syntax) | |
8820 | && current_templates->end[-1].operand_types[1] | |
8821 | .bitfield.baseindex)) | |
8822 | type = current_templates->end[-1].operand_types[1]; | |
be05d201 L |
8823 | expected_reg = hash_find (reg_hash, |
8824 | di_si[addr_mode][type.bitfield.esseg]); | |
8825 | ||
fc0763e6 JB |
8826 | } |
8827 | else | |
be05d201 | 8828 | expected_reg = hash_find (reg_hash, bx[addr_mode]); |
fc0763e6 | 8829 | |
be05d201 L |
8830 | if (i.base_reg != expected_reg |
8831 | || i.index_reg | |
fc0763e6 | 8832 | || operand_type_check (i.types[this_operand], disp)) |
fc0763e6 | 8833 | { |
be05d201 L |
8834 | /* The second memory operand must have the same size as |
8835 | the first one. */ | |
8836 | if (i.mem_operands | |
8837 | && i.base_reg | |
8838 | && !((addr_mode == CODE_64BIT | |
dc821c5f | 8839 | && i.base_reg->reg_type.bitfield.qword) |
be05d201 | 8840 | || (addr_mode == CODE_32BIT |
dc821c5f JB |
8841 | ? i.base_reg->reg_type.bitfield.dword |
8842 | : i.base_reg->reg_type.bitfield.word))) | |
be05d201 L |
8843 | goto bad_address; |
8844 | ||
fc0763e6 JB |
8845 | as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"), |
8846 | operand_string, | |
8847 | intel_syntax ? '[' : '(', | |
8848 | register_prefix, | |
be05d201 | 8849 | expected_reg->reg_name, |
fc0763e6 | 8850 | intel_syntax ? ']' : ')'); |
be05d201 | 8851 | return 1; |
fc0763e6 | 8852 | } |
be05d201 L |
8853 | else |
8854 | return 1; | |
8855 | ||
8856 | bad_address: | |
8857 | as_bad (_("`%s' is not a valid %s expression"), | |
8858 | operand_string, kind); | |
8859 | return 0; | |
3e73aa7c JH |
8860 | } |
8861 | else | |
8862 | { | |
be05d201 L |
8863 | if (addr_mode != CODE_16BIT) |
8864 | { | |
8865 | /* 32-bit/64-bit checks. */ | |
8866 | if ((i.base_reg | |
8867 | && (addr_mode == CODE_64BIT | |
dc821c5f JB |
8868 | ? !i.base_reg->reg_type.bitfield.qword |
8869 | : !i.base_reg->reg_type.bitfield.dword) | |
be05d201 L |
8870 | && (i.index_reg |
8871 | || (i.base_reg->reg_num | |
8872 | != (addr_mode == CODE_64BIT ? RegRip : RegEip)))) | |
8873 | || (i.index_reg | |
1b54b8d7 JB |
8874 | && !i.index_reg->reg_type.bitfield.xmmword |
8875 | && !i.index_reg->reg_type.bitfield.ymmword | |
8876 | && !i.index_reg->reg_type.bitfield.zmmword | |
be05d201 | 8877 | && ((addr_mode == CODE_64BIT |
dc821c5f | 8878 | ? !(i.index_reg->reg_type.bitfield.qword |
be05d201 | 8879 | || i.index_reg->reg_num == RegRiz) |
dc821c5f | 8880 | : !(i.index_reg->reg_type.bitfield.dword |
be05d201 L |
8881 | || i.index_reg->reg_num == RegEiz)) |
8882 | || !i.index_reg->reg_type.bitfield.baseindex))) | |
8883 | goto bad_address; | |
8178be5b JB |
8884 | |
8885 | /* bndmk, bndldx, and bndstx have special restrictions. */ | |
8886 | if (current_templates->start->base_opcode == 0xf30f1b | |
8887 | || (current_templates->start->base_opcode & ~1) == 0x0f1a) | |
8888 | { | |
8889 | /* They cannot use RIP-relative addressing. */ | |
8890 | if (i.base_reg && i.base_reg->reg_num == RegRip) | |
8891 | { | |
8892 | as_bad (_("`%s' cannot be used here"), operand_string); | |
8893 | return 0; | |
8894 | } | |
8895 | ||
8896 | /* bndldx and bndstx ignore their scale factor. */ | |
8897 | if (current_templates->start->base_opcode != 0xf30f1b | |
8898 | && i.log2_scale_factor) | |
8899 | as_warn (_("register scaling is being ignored here")); | |
8900 | } | |
be05d201 L |
8901 | } |
8902 | else | |
3e73aa7c | 8903 | { |
be05d201 | 8904 | /* 16-bit checks. */ |
3e73aa7c | 8905 | if ((i.base_reg |
dc821c5f | 8906 | && (!i.base_reg->reg_type.bitfield.word |
40fb9820 | 8907 | || !i.base_reg->reg_type.bitfield.baseindex)) |
3e73aa7c | 8908 | || (i.index_reg |
dc821c5f | 8909 | && (!i.index_reg->reg_type.bitfield.word |
40fb9820 | 8910 | || !i.index_reg->reg_type.bitfield.baseindex |
29b0f896 AM |
8911 | || !(i.base_reg |
8912 | && i.base_reg->reg_num < 6 | |
8913 | && i.index_reg->reg_num >= 6 | |
8914 | && i.log2_scale_factor == 0)))) | |
be05d201 | 8915 | goto bad_address; |
3e73aa7c JH |
8916 | } |
8917 | } | |
be05d201 | 8918 | return 1; |
24eab124 | 8919 | } |
252b5132 | 8920 | |
43234a1e L |
8921 | /* Handle vector immediates. */ |
8922 | ||
8923 | static int | |
8924 | RC_SAE_immediate (const char *imm_start) | |
8925 | { | |
8926 | unsigned int match_found, j; | |
8927 | const char *pstr = imm_start; | |
8928 | expressionS *exp; | |
8929 | ||
8930 | if (*pstr != '{') | |
8931 | return 0; | |
8932 | ||
8933 | pstr++; | |
8934 | match_found = 0; | |
8935 | for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++) | |
8936 | { | |
8937 | if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len)) | |
8938 | { | |
8939 | if (!i.rounding) | |
8940 | { | |
8941 | rc_op.type = RC_NamesTable[j].type; | |
8942 | rc_op.operand = this_operand; | |
8943 | i.rounding = &rc_op; | |
8944 | } | |
8945 | else | |
8946 | { | |
8947 | as_bad (_("duplicated `%s'"), imm_start); | |
8948 | return 0; | |
8949 | } | |
8950 | pstr += RC_NamesTable[j].len; | |
8951 | match_found = 1; | |
8952 | break; | |
8953 | } | |
8954 | } | |
8955 | if (!match_found) | |
8956 | return 0; | |
8957 | ||
8958 | if (*pstr++ != '}') | |
8959 | { | |
8960 | as_bad (_("Missing '}': '%s'"), imm_start); | |
8961 | return 0; | |
8962 | } | |
8963 | /* RC/SAE immediate string should contain nothing more. */; | |
8964 | if (*pstr != 0) | |
8965 | { | |
8966 | as_bad (_("Junk after '}': '%s'"), imm_start); | |
8967 | return 0; | |
8968 | } | |
8969 | ||
8970 | exp = &im_expressions[i.imm_operands++]; | |
8971 | i.op[this_operand].imms = exp; | |
8972 | ||
8973 | exp->X_op = O_constant; | |
8974 | exp->X_add_number = 0; | |
8975 | exp->X_add_symbol = (symbolS *) 0; | |
8976 | exp->X_op_symbol = (symbolS *) 0; | |
8977 | ||
8978 | i.types[this_operand].bitfield.imm8 = 1; | |
8979 | return 1; | |
8980 | } | |
8981 | ||
8325cc63 JB |
8982 | /* Only string instructions can have a second memory operand, so |
8983 | reduce current_templates to just those if it contains any. */ | |
8984 | static int | |
8985 | maybe_adjust_templates (void) | |
8986 | { | |
8987 | const insn_template *t; | |
8988 | ||
8989 | gas_assert (i.mem_operands == 1); | |
8990 | ||
8991 | for (t = current_templates->start; t < current_templates->end; ++t) | |
8992 | if (t->opcode_modifier.isstring) | |
8993 | break; | |
8994 | ||
8995 | if (t < current_templates->end) | |
8996 | { | |
8997 | static templates aux_templates; | |
8998 | bfd_boolean recheck; | |
8999 | ||
9000 | aux_templates.start = t; | |
9001 | for (; t < current_templates->end; ++t) | |
9002 | if (!t->opcode_modifier.isstring) | |
9003 | break; | |
9004 | aux_templates.end = t; | |
9005 | ||
9006 | /* Determine whether to re-check the first memory operand. */ | |
9007 | recheck = (aux_templates.start != current_templates->start | |
9008 | || t != current_templates->end); | |
9009 | ||
9010 | current_templates = &aux_templates; | |
9011 | ||
9012 | if (recheck) | |
9013 | { | |
9014 | i.mem_operands = 0; | |
9015 | if (i.memop1_string != NULL | |
9016 | && i386_index_check (i.memop1_string) == 0) | |
9017 | return 0; | |
9018 | i.mem_operands = 1; | |
9019 | } | |
9020 | } | |
9021 | ||
9022 | return 1; | |
9023 | } | |
9024 | ||
fc0763e6 | 9025 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero |
47926f60 | 9026 | on error. */ |
252b5132 | 9027 | |
252b5132 | 9028 | static int |
a7619375 | 9029 | i386_att_operand (char *operand_string) |
252b5132 | 9030 | { |
af6bdddf AM |
9031 | const reg_entry *r; |
9032 | char *end_op; | |
24eab124 | 9033 | char *op_string = operand_string; |
252b5132 | 9034 | |
24eab124 | 9035 | if (is_space_char (*op_string)) |
252b5132 RH |
9036 | ++op_string; |
9037 | ||
24eab124 | 9038 | /* We check for an absolute prefix (differentiating, |
47926f60 | 9039 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
9040 | if (*op_string == ABSOLUTE_PREFIX) |
9041 | { | |
9042 | ++op_string; | |
9043 | if (is_space_char (*op_string)) | |
9044 | ++op_string; | |
40fb9820 | 9045 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 | 9046 | } |
252b5132 | 9047 | |
47926f60 | 9048 | /* Check if operand is a register. */ |
4d1bb795 | 9049 | if ((r = parse_register (op_string, &end_op)) != NULL) |
24eab124 | 9050 | { |
40fb9820 L |
9051 | i386_operand_type temp; |
9052 | ||
24eab124 AM |
9053 | /* Check for a segment override by searching for ':' after a |
9054 | segment register. */ | |
9055 | op_string = end_op; | |
9056 | if (is_space_char (*op_string)) | |
9057 | ++op_string; | |
40fb9820 L |
9058 | if (*op_string == ':' |
9059 | && (r->reg_type.bitfield.sreg2 | |
9060 | || r->reg_type.bitfield.sreg3)) | |
24eab124 AM |
9061 | { |
9062 | switch (r->reg_num) | |
9063 | { | |
9064 | case 0: | |
9065 | i.seg[i.mem_operands] = &es; | |
9066 | break; | |
9067 | case 1: | |
9068 | i.seg[i.mem_operands] = &cs; | |
9069 | break; | |
9070 | case 2: | |
9071 | i.seg[i.mem_operands] = &ss; | |
9072 | break; | |
9073 | case 3: | |
9074 | i.seg[i.mem_operands] = &ds; | |
9075 | break; | |
9076 | case 4: | |
9077 | i.seg[i.mem_operands] = &fs; | |
9078 | break; | |
9079 | case 5: | |
9080 | i.seg[i.mem_operands] = &gs; | |
9081 | break; | |
9082 | } | |
252b5132 | 9083 | |
24eab124 | 9084 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
9085 | ++op_string; |
9086 | if (is_space_char (*op_string)) | |
24eab124 | 9087 | ++op_string; |
252b5132 | 9088 | |
24eab124 AM |
9089 | if (!is_digit_char (*op_string) |
9090 | && !is_identifier_char (*op_string) | |
9091 | && *op_string != '(' | |
9092 | && *op_string != ABSOLUTE_PREFIX) | |
9093 | { | |
9094 | as_bad (_("bad memory operand `%s'"), op_string); | |
9095 | return 0; | |
9096 | } | |
47926f60 | 9097 | /* Handle case of %es:*foo. */ |
24eab124 AM |
9098 | if (*op_string == ABSOLUTE_PREFIX) |
9099 | { | |
9100 | ++op_string; | |
9101 | if (is_space_char (*op_string)) | |
9102 | ++op_string; | |
40fb9820 | 9103 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 AM |
9104 | } |
9105 | goto do_memory_reference; | |
9106 | } | |
43234a1e L |
9107 | |
9108 | /* Handle vector operations. */ | |
9109 | if (*op_string == '{') | |
9110 | { | |
9111 | op_string = check_VecOperations (op_string, NULL); | |
9112 | if (op_string == NULL) | |
9113 | return 0; | |
9114 | } | |
9115 | ||
24eab124 AM |
9116 | if (*op_string) |
9117 | { | |
d0b47220 | 9118 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
9119 | return 0; |
9120 | } | |
40fb9820 L |
9121 | temp = r->reg_type; |
9122 | temp.bitfield.baseindex = 0; | |
c6fb90c8 L |
9123 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
9124 | temp); | |
7d5e4556 | 9125 | i.types[this_operand].bitfield.unspecified = 0; |
520dc8e8 | 9126 | i.op[this_operand].regs = r; |
24eab124 AM |
9127 | i.reg_operands++; |
9128 | } | |
af6bdddf AM |
9129 | else if (*op_string == REGISTER_PREFIX) |
9130 | { | |
9131 | as_bad (_("bad register name `%s'"), op_string); | |
9132 | return 0; | |
9133 | } | |
24eab124 | 9134 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 9135 | { |
24eab124 | 9136 | ++op_string; |
40fb9820 | 9137 | if (i.types[this_operand].bitfield.jumpabsolute) |
24eab124 | 9138 | { |
d0b47220 | 9139 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
9140 | return 0; |
9141 | } | |
9142 | if (!i386_immediate (op_string)) | |
9143 | return 0; | |
9144 | } | |
43234a1e L |
9145 | else if (RC_SAE_immediate (operand_string)) |
9146 | { | |
9147 | /* If it is a RC or SAE immediate, do nothing. */ | |
9148 | ; | |
9149 | } | |
24eab124 AM |
9150 | else if (is_digit_char (*op_string) |
9151 | || is_identifier_char (*op_string) | |
d02603dc | 9152 | || *op_string == '"' |
e5cb08ac | 9153 | || *op_string == '(') |
24eab124 | 9154 | { |
47926f60 | 9155 | /* This is a memory reference of some sort. */ |
af6bdddf | 9156 | char *base_string; |
252b5132 | 9157 | |
47926f60 | 9158 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
9159 | char *displacement_string_start; |
9160 | char *displacement_string_end; | |
43234a1e | 9161 | char *vop_start; |
252b5132 | 9162 | |
24eab124 | 9163 | do_memory_reference: |
8325cc63 JB |
9164 | if (i.mem_operands == 1 && !maybe_adjust_templates ()) |
9165 | return 0; | |
24eab124 | 9166 | if ((i.mem_operands == 1 |
40fb9820 | 9167 | && !current_templates->start->opcode_modifier.isstring) |
24eab124 AM |
9168 | || i.mem_operands == 2) |
9169 | { | |
9170 | as_bad (_("too many memory references for `%s'"), | |
9171 | current_templates->start->name); | |
9172 | return 0; | |
9173 | } | |
252b5132 | 9174 | |
24eab124 AM |
9175 | /* Check for base index form. We detect the base index form by |
9176 | looking for an ')' at the end of the operand, searching | |
9177 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
9178 | after the '('. */ | |
af6bdddf | 9179 | base_string = op_string + strlen (op_string); |
c3332e24 | 9180 | |
43234a1e L |
9181 | /* Handle vector operations. */ |
9182 | vop_start = strchr (op_string, '{'); | |
9183 | if (vop_start && vop_start < base_string) | |
9184 | { | |
9185 | if (check_VecOperations (vop_start, base_string) == NULL) | |
9186 | return 0; | |
9187 | base_string = vop_start; | |
9188 | } | |
9189 | ||
af6bdddf AM |
9190 | --base_string; |
9191 | if (is_space_char (*base_string)) | |
9192 | --base_string; | |
252b5132 | 9193 | |
47926f60 | 9194 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
9195 | displacement_string_start = op_string; |
9196 | displacement_string_end = base_string + 1; | |
252b5132 | 9197 | |
24eab124 AM |
9198 | if (*base_string == ')') |
9199 | { | |
af6bdddf | 9200 | char *temp_string; |
24eab124 AM |
9201 | unsigned int parens_balanced = 1; |
9202 | /* We've already checked that the number of left & right ()'s are | |
47926f60 | 9203 | equal, so this loop will not be infinite. */ |
24eab124 AM |
9204 | do |
9205 | { | |
9206 | base_string--; | |
9207 | if (*base_string == ')') | |
9208 | parens_balanced++; | |
9209 | if (*base_string == '(') | |
9210 | parens_balanced--; | |
9211 | } | |
9212 | while (parens_balanced); | |
c3332e24 | 9213 | |
af6bdddf | 9214 | temp_string = base_string; |
c3332e24 | 9215 | |
24eab124 | 9216 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
9217 | ++base_string; |
9218 | if (is_space_char (*base_string)) | |
24eab124 | 9219 | ++base_string; |
252b5132 | 9220 | |
af6bdddf | 9221 | if (*base_string == ',' |
4eed87de AM |
9222 | || ((i.base_reg = parse_register (base_string, &end_op)) |
9223 | != NULL)) | |
252b5132 | 9224 | { |
af6bdddf | 9225 | displacement_string_end = temp_string; |
252b5132 | 9226 | |
40fb9820 | 9227 | i.types[this_operand].bitfield.baseindex = 1; |
252b5132 | 9228 | |
af6bdddf | 9229 | if (i.base_reg) |
24eab124 | 9230 | { |
24eab124 AM |
9231 | base_string = end_op; |
9232 | if (is_space_char (*base_string)) | |
9233 | ++base_string; | |
af6bdddf AM |
9234 | } |
9235 | ||
9236 | /* There may be an index reg or scale factor here. */ | |
9237 | if (*base_string == ',') | |
9238 | { | |
9239 | ++base_string; | |
9240 | if (is_space_char (*base_string)) | |
9241 | ++base_string; | |
9242 | ||
4eed87de AM |
9243 | if ((i.index_reg = parse_register (base_string, &end_op)) |
9244 | != NULL) | |
24eab124 | 9245 | { |
af6bdddf | 9246 | base_string = end_op; |
24eab124 AM |
9247 | if (is_space_char (*base_string)) |
9248 | ++base_string; | |
af6bdddf AM |
9249 | if (*base_string == ',') |
9250 | { | |
9251 | ++base_string; | |
9252 | if (is_space_char (*base_string)) | |
9253 | ++base_string; | |
9254 | } | |
e5cb08ac | 9255 | else if (*base_string != ')') |
af6bdddf | 9256 | { |
4eed87de AM |
9257 | as_bad (_("expecting `,' or `)' " |
9258 | "after index register in `%s'"), | |
af6bdddf AM |
9259 | operand_string); |
9260 | return 0; | |
9261 | } | |
24eab124 | 9262 | } |
af6bdddf | 9263 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 9264 | { |
f76bf5e0 L |
9265 | end_op = strchr (base_string, ','); |
9266 | if (end_op) | |
9267 | *end_op = '\0'; | |
af6bdddf | 9268 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
9269 | return 0; |
9270 | } | |
252b5132 | 9271 | |
47926f60 | 9272 | /* Check for scale factor. */ |
551c1ca1 | 9273 | if (*base_string != ')') |
af6bdddf | 9274 | { |
551c1ca1 AM |
9275 | char *end_scale = i386_scale (base_string); |
9276 | ||
9277 | if (!end_scale) | |
af6bdddf | 9278 | return 0; |
24eab124 | 9279 | |
551c1ca1 | 9280 | base_string = end_scale; |
af6bdddf AM |
9281 | if (is_space_char (*base_string)) |
9282 | ++base_string; | |
9283 | if (*base_string != ')') | |
9284 | { | |
4eed87de AM |
9285 | as_bad (_("expecting `)' " |
9286 | "after scale factor in `%s'"), | |
af6bdddf AM |
9287 | operand_string); |
9288 | return 0; | |
9289 | } | |
9290 | } | |
9291 | else if (!i.index_reg) | |
24eab124 | 9292 | { |
4eed87de AM |
9293 | as_bad (_("expecting index register or scale factor " |
9294 | "after `,'; got '%c'"), | |
af6bdddf | 9295 | *base_string); |
24eab124 AM |
9296 | return 0; |
9297 | } | |
9298 | } | |
af6bdddf | 9299 | else if (*base_string != ')') |
24eab124 | 9300 | { |
4eed87de AM |
9301 | as_bad (_("expecting `,' or `)' " |
9302 | "after base register in `%s'"), | |
af6bdddf | 9303 | operand_string); |
24eab124 AM |
9304 | return 0; |
9305 | } | |
c3332e24 | 9306 | } |
af6bdddf | 9307 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 9308 | { |
f76bf5e0 L |
9309 | end_op = strchr (base_string, ','); |
9310 | if (end_op) | |
9311 | *end_op = '\0'; | |
af6bdddf | 9312 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 9313 | return 0; |
c3332e24 | 9314 | } |
24eab124 AM |
9315 | } |
9316 | ||
9317 | /* If there's an expression beginning the operand, parse it, | |
9318 | assuming displacement_string_start and | |
9319 | displacement_string_end are meaningful. */ | |
9320 | if (displacement_string_start != displacement_string_end) | |
9321 | { | |
9322 | if (!i386_displacement (displacement_string_start, | |
9323 | displacement_string_end)) | |
9324 | return 0; | |
9325 | } | |
9326 | ||
9327 | /* Special case for (%dx) while doing input/output op. */ | |
9328 | if (i.base_reg | |
0dfbf9d7 L |
9329 | && operand_type_equal (&i.base_reg->reg_type, |
9330 | ®16_inoutportreg) | |
24eab124 AM |
9331 | && i.index_reg == 0 |
9332 | && i.log2_scale_factor == 0 | |
9333 | && i.seg[i.mem_operands] == 0 | |
40fb9820 | 9334 | && !operand_type_check (i.types[this_operand], disp)) |
24eab124 | 9335 | { |
65da13b5 | 9336 | i.types[this_operand] = inoutportreg; |
24eab124 AM |
9337 | return 1; |
9338 | } | |
9339 | ||
eecb386c AM |
9340 | if (i386_index_check (operand_string) == 0) |
9341 | return 0; | |
5c07affc | 9342 | i.types[this_operand].bitfield.mem = 1; |
8325cc63 JB |
9343 | if (i.mem_operands == 0) |
9344 | i.memop1_string = xstrdup (operand_string); | |
24eab124 AM |
9345 | i.mem_operands++; |
9346 | } | |
9347 | else | |
ce8a8b2f AM |
9348 | { |
9349 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
9350 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
9351 | output_invalid (*op_string), | |
9352 | this_operand + 1, | |
9353 | op_string); | |
9354 | return 0; | |
9355 | } | |
47926f60 | 9356 | return 1; /* Normal return. */ |
252b5132 RH |
9357 | } |
9358 | \f | |
fa94de6b RM |
9359 | /* Calculate the maximum variable size (i.e., excluding fr_fix) |
9360 | that an rs_machine_dependent frag may reach. */ | |
9361 | ||
9362 | unsigned int | |
9363 | i386_frag_max_var (fragS *frag) | |
9364 | { | |
9365 | /* The only relaxable frags are for jumps. | |
9366 | Unconditional jumps can grow by 4 bytes and others by 5 bytes. */ | |
9367 | gas_assert (frag->fr_type == rs_machine_dependent); | |
9368 | return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5; | |
9369 | } | |
9370 | ||
b084df0b L |
9371 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
9372 | static int | |
8dcea932 | 9373 | elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var) |
b084df0b L |
9374 | { |
9375 | /* STT_GNU_IFUNC symbol must go through PLT. */ | |
9376 | if ((symbol_get_bfdsym (fr_symbol)->flags | |
9377 | & BSF_GNU_INDIRECT_FUNCTION) != 0) | |
9378 | return 0; | |
9379 | ||
9380 | if (!S_IS_EXTERNAL (fr_symbol)) | |
9381 | /* Symbol may be weak or local. */ | |
9382 | return !S_IS_WEAK (fr_symbol); | |
9383 | ||
8dcea932 L |
9384 | /* Global symbols with non-default visibility can't be preempted. */ |
9385 | if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT) | |
9386 | return 1; | |
9387 | ||
9388 | if (fr_var != NO_RELOC) | |
9389 | switch ((enum bfd_reloc_code_real) fr_var) | |
9390 | { | |
9391 | case BFD_RELOC_386_PLT32: | |
9392 | case BFD_RELOC_X86_64_PLT32: | |
33eaf5de | 9393 | /* Symbol with PLT relocation may be preempted. */ |
8dcea932 L |
9394 | return 0; |
9395 | default: | |
9396 | abort (); | |
9397 | } | |
9398 | ||
b084df0b L |
9399 | /* Global symbols with default visibility in a shared library may be |
9400 | preempted by another definition. */ | |
8dcea932 | 9401 | return !shared; |
b084df0b L |
9402 | } |
9403 | #endif | |
9404 | ||
ee7fcc42 AM |
9405 | /* md_estimate_size_before_relax() |
9406 | ||
9407 | Called just before relax() for rs_machine_dependent frags. The x86 | |
9408 | assembler uses these frags to handle variable size jump | |
9409 | instructions. | |
9410 | ||
9411 | Any symbol that is now undefined will not become defined. | |
9412 | Return the correct fr_subtype in the frag. | |
9413 | Return the initial "guess for variable size of frag" to caller. | |
9414 | The guess is actually the growth beyond the fixed part. Whatever | |
9415 | we do to grow the fixed or variable part contributes to our | |
9416 | returned value. */ | |
9417 | ||
252b5132 | 9418 | int |
7016a5d5 | 9419 | md_estimate_size_before_relax (fragS *fragP, segT segment) |
252b5132 | 9420 | { |
252b5132 | 9421 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
9422 | check for un-relaxable symbols. On an ELF system, we can't relax |
9423 | an externally visible symbol, because it may be overridden by a | |
9424 | shared library. */ | |
9425 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 9426 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 9427 | || (IS_ELF |
8dcea932 L |
9428 | && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol, |
9429 | fragP->fr_var)) | |
fbeb56a4 DK |
9430 | #endif |
9431 | #if defined (OBJ_COFF) && defined (TE_PE) | |
7ab9ffdd | 9432 | || (OUTPUT_FLAVOR == bfd_target_coff_flavour |
fbeb56a4 | 9433 | && S_IS_WEAK (fragP->fr_symbol)) |
b98ef147 AM |
9434 | #endif |
9435 | ) | |
252b5132 | 9436 | { |
b98ef147 AM |
9437 | /* Symbol is undefined in this segment, or we need to keep a |
9438 | reloc so that weak symbols can be overridden. */ | |
9439 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f86103b7 | 9440 | enum bfd_reloc_code_real reloc_type; |
ee7fcc42 AM |
9441 | unsigned char *opcode; |
9442 | int old_fr_fix; | |
f6af82bd | 9443 | |
ee7fcc42 | 9444 | if (fragP->fr_var != NO_RELOC) |
1e9cc1c2 | 9445 | reloc_type = (enum bfd_reloc_code_real) fragP->fr_var; |
b98ef147 | 9446 | else if (size == 2) |
f6af82bd | 9447 | reloc_type = BFD_RELOC_16_PCREL; |
bd7ab16b L |
9448 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
9449 | else if (need_plt32_p (fragP->fr_symbol)) | |
9450 | reloc_type = BFD_RELOC_X86_64_PLT32; | |
9451 | #endif | |
f6af82bd AM |
9452 | else |
9453 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 9454 | |
ee7fcc42 AM |
9455 | old_fr_fix = fragP->fr_fix; |
9456 | opcode = (unsigned char *) fragP->fr_opcode; | |
9457 | ||
fddf5b5b | 9458 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 9459 | { |
fddf5b5b AM |
9460 | case UNCOND_JUMP: |
9461 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 9462 | opcode[0] = 0xe9; |
252b5132 | 9463 | fragP->fr_fix += size; |
062cd5e7 AS |
9464 | fix_new (fragP, old_fr_fix, size, |
9465 | fragP->fr_symbol, | |
9466 | fragP->fr_offset, 1, | |
9467 | reloc_type); | |
252b5132 RH |
9468 | break; |
9469 | ||
fddf5b5b | 9470 | case COND_JUMP86: |
412167cb AM |
9471 | if (size == 2 |
9472 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) | |
fddf5b5b AM |
9473 | { |
9474 | /* Negate the condition, and branch past an | |
9475 | unconditional jump. */ | |
9476 | opcode[0] ^= 1; | |
9477 | opcode[1] = 3; | |
9478 | /* Insert an unconditional jump. */ | |
9479 | opcode[2] = 0xe9; | |
9480 | /* We added two extra opcode bytes, and have a two byte | |
9481 | offset. */ | |
9482 | fragP->fr_fix += 2 + 2; | |
062cd5e7 AS |
9483 | fix_new (fragP, old_fr_fix + 2, 2, |
9484 | fragP->fr_symbol, | |
9485 | fragP->fr_offset, 1, | |
9486 | reloc_type); | |
fddf5b5b AM |
9487 | break; |
9488 | } | |
9489 | /* Fall through. */ | |
9490 | ||
9491 | case COND_JUMP: | |
412167cb AM |
9492 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
9493 | { | |
3e02c1cc AM |
9494 | fixS *fixP; |
9495 | ||
412167cb | 9496 | fragP->fr_fix += 1; |
3e02c1cc AM |
9497 | fixP = fix_new (fragP, old_fr_fix, 1, |
9498 | fragP->fr_symbol, | |
9499 | fragP->fr_offset, 1, | |
9500 | BFD_RELOC_8_PCREL); | |
9501 | fixP->fx_signed = 1; | |
412167cb AM |
9502 | break; |
9503 | } | |
93c2a809 | 9504 | |
24eab124 | 9505 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 9506 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 9507 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 9508 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
9509 | /* We've added an opcode byte. */ |
9510 | fragP->fr_fix += 1 + size; | |
062cd5e7 AS |
9511 | fix_new (fragP, old_fr_fix + 1, size, |
9512 | fragP->fr_symbol, | |
9513 | fragP->fr_offset, 1, | |
9514 | reloc_type); | |
252b5132 | 9515 | break; |
fddf5b5b AM |
9516 | |
9517 | default: | |
9518 | BAD_CASE (fragP->fr_subtype); | |
9519 | break; | |
252b5132 RH |
9520 | } |
9521 | frag_wane (fragP); | |
ee7fcc42 | 9522 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 9523 | } |
93c2a809 | 9524 | |
93c2a809 AM |
9525 | /* Guess size depending on current relax state. Initially the relax |
9526 | state will correspond to a short jump and we return 1, because | |
9527 | the variable part of the frag (the branch offset) is one byte | |
9528 | long. However, we can relax a section more than once and in that | |
9529 | case we must either set fr_subtype back to the unrelaxed state, | |
9530 | or return the value for the appropriate branch. */ | |
9531 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
9532 | } |
9533 | ||
47926f60 KH |
9534 | /* Called after relax() is finished. |
9535 | ||
9536 | In: Address of frag. | |
9537 | fr_type == rs_machine_dependent. | |
9538 | fr_subtype is what the address relaxed to. | |
9539 | ||
9540 | Out: Any fixSs and constants are set up. | |
9541 | Caller will turn frag into a ".space 0". */ | |
9542 | ||
252b5132 | 9543 | void |
7016a5d5 TG |
9544 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, |
9545 | fragS *fragP) | |
252b5132 | 9546 | { |
29b0f896 | 9547 | unsigned char *opcode; |
252b5132 | 9548 | unsigned char *where_to_put_displacement = NULL; |
847f7ad4 AM |
9549 | offsetT target_address; |
9550 | offsetT opcode_address; | |
252b5132 | 9551 | unsigned int extension = 0; |
847f7ad4 | 9552 | offsetT displacement_from_opcode_start; |
252b5132 RH |
9553 | |
9554 | opcode = (unsigned char *) fragP->fr_opcode; | |
9555 | ||
47926f60 | 9556 | /* Address we want to reach in file space. */ |
252b5132 | 9557 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 9558 | |
47926f60 | 9559 | /* Address opcode resides at in file space. */ |
252b5132 RH |
9560 | opcode_address = fragP->fr_address + fragP->fr_fix; |
9561 | ||
47926f60 | 9562 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
9563 | displacement_from_opcode_start = target_address - opcode_address; |
9564 | ||
fddf5b5b | 9565 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 9566 | { |
47926f60 KH |
9567 | /* Don't have to change opcode. */ |
9568 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 9569 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
9570 | } |
9571 | else | |
9572 | { | |
9573 | if (no_cond_jump_promotion | |
9574 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4eed87de AM |
9575 | as_warn_where (fragP->fr_file, fragP->fr_line, |
9576 | _("long jump required")); | |
252b5132 | 9577 | |
fddf5b5b AM |
9578 | switch (fragP->fr_subtype) |
9579 | { | |
9580 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
9581 | extension = 4; /* 1 opcode + 4 displacement */ | |
9582 | opcode[0] = 0xe9; | |
9583 | where_to_put_displacement = &opcode[1]; | |
9584 | break; | |
252b5132 | 9585 | |
fddf5b5b AM |
9586 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
9587 | extension = 2; /* 1 opcode + 2 displacement */ | |
9588 | opcode[0] = 0xe9; | |
9589 | where_to_put_displacement = &opcode[1]; | |
9590 | break; | |
252b5132 | 9591 | |
fddf5b5b AM |
9592 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
9593 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
9594 | extension = 5; /* 2 opcode + 4 displacement */ | |
9595 | opcode[1] = opcode[0] + 0x10; | |
9596 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
9597 | where_to_put_displacement = &opcode[2]; | |
9598 | break; | |
252b5132 | 9599 | |
fddf5b5b AM |
9600 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
9601 | extension = 3; /* 2 opcode + 2 displacement */ | |
9602 | opcode[1] = opcode[0] + 0x10; | |
9603 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
9604 | where_to_put_displacement = &opcode[2]; | |
9605 | break; | |
252b5132 | 9606 | |
fddf5b5b AM |
9607 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
9608 | extension = 4; | |
9609 | opcode[0] ^= 1; | |
9610 | opcode[1] = 3; | |
9611 | opcode[2] = 0xe9; | |
9612 | where_to_put_displacement = &opcode[3]; | |
9613 | break; | |
9614 | ||
9615 | default: | |
9616 | BAD_CASE (fragP->fr_subtype); | |
9617 | break; | |
9618 | } | |
252b5132 | 9619 | } |
fddf5b5b | 9620 | |
7b81dfbb AJ |
9621 | /* If size if less then four we are sure that the operand fits, |
9622 | but if it's 4, then it could be that the displacement is larger | |
9623 | then -/+ 2GB. */ | |
9624 | if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 | |
9625 | && object_64bit | |
9626 | && ((addressT) (displacement_from_opcode_start - extension | |
4eed87de AM |
9627 | + ((addressT) 1 << 31)) |
9628 | > (((addressT) 2 << 31) - 1))) | |
7b81dfbb AJ |
9629 | { |
9630 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
9631 | _("jump target out of range")); | |
9632 | /* Make us emit 0. */ | |
9633 | displacement_from_opcode_start = extension; | |
9634 | } | |
47926f60 | 9635 | /* Now put displacement after opcode. */ |
252b5132 RH |
9636 | md_number_to_chars ((char *) where_to_put_displacement, |
9637 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 9638 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
9639 | fragP->fr_fix += extension; |
9640 | } | |
9641 | \f | |
7016a5d5 | 9642 | /* Apply a fixup (fixP) to segment data, once it has been determined |
252b5132 RH |
9643 | by our caller that we have all the info we need to fix it up. |
9644 | ||
7016a5d5 TG |
9645 | Parameter valP is the pointer to the value of the bits. |
9646 | ||
252b5132 RH |
9647 | On the 386, immediates, displacements, and data pointers are all in |
9648 | the same (little-endian) format, so we don't need to care about which | |
9649 | we are handling. */ | |
9650 | ||
94f592af | 9651 | void |
7016a5d5 | 9652 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 9653 | { |
94f592af | 9654 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
c6682705 | 9655 | valueT value = *valP; |
252b5132 | 9656 | |
f86103b7 | 9657 | #if !defined (TE_Mach) |
93382f6d AM |
9658 | if (fixP->fx_pcrel) |
9659 | { | |
9660 | switch (fixP->fx_r_type) | |
9661 | { | |
5865bb77 ILT |
9662 | default: |
9663 | break; | |
9664 | ||
d6ab8113 JB |
9665 | case BFD_RELOC_64: |
9666 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
9667 | break; | |
93382f6d | 9668 | case BFD_RELOC_32: |
ae8887b5 | 9669 | case BFD_RELOC_X86_64_32S: |
93382f6d AM |
9670 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
9671 | break; | |
9672 | case BFD_RELOC_16: | |
9673 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
9674 | break; | |
9675 | case BFD_RELOC_8: | |
9676 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
9677 | break; | |
9678 | } | |
9679 | } | |
252b5132 | 9680 | |
a161fe53 | 9681 | if (fixP->fx_addsy != NULL |
31312f95 | 9682 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
d6ab8113 | 9683 | || fixP->fx_r_type == BFD_RELOC_64_PCREL |
31312f95 | 9684 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
d258b828 | 9685 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) |
31312f95 | 9686 | && !use_rela_relocations) |
252b5132 | 9687 | { |
31312f95 AM |
9688 | /* This is a hack. There should be a better way to handle this. |
9689 | This covers for the fact that bfd_install_relocation will | |
9690 | subtract the current location (for partial_inplace, PC relative | |
9691 | relocations); see more below. */ | |
252b5132 | 9692 | #ifndef OBJ_AOUT |
718ddfc0 | 9693 | if (IS_ELF |
252b5132 RH |
9694 | #ifdef TE_PE |
9695 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
9696 | #endif | |
9697 | ) | |
9698 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
9699 | #endif | |
9700 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 9701 | if (IS_ELF) |
252b5132 | 9702 | { |
6539b54b | 9703 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
2f66722d | 9704 | |
6539b54b | 9705 | if ((sym_seg == seg |
2f66722d | 9706 | || (symbol_section_p (fixP->fx_addsy) |
6539b54b | 9707 | && sym_seg != absolute_section)) |
af65af87 | 9708 | && !generic_force_reloc (fixP)) |
2f66722d AM |
9709 | { |
9710 | /* Yes, we add the values in twice. This is because | |
6539b54b AM |
9711 | bfd_install_relocation subtracts them out again. I think |
9712 | bfd_install_relocation is broken, but I don't dare change | |
2f66722d AM |
9713 | it. FIXME. */ |
9714 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
9715 | } | |
252b5132 RH |
9716 | } |
9717 | #endif | |
9718 | #if defined (OBJ_COFF) && defined (TE_PE) | |
977cdf5a NC |
9719 | /* For some reason, the PE format does not store a |
9720 | section address offset for a PC relative symbol. */ | |
9721 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg | |
7be1c489 | 9722 | || S_IS_WEAK (fixP->fx_addsy)) |
252b5132 RH |
9723 | value += md_pcrel_from (fixP); |
9724 | #endif | |
9725 | } | |
fbeb56a4 | 9726 | #if defined (OBJ_COFF) && defined (TE_PE) |
f01c1a09 NC |
9727 | if (fixP->fx_addsy != NULL |
9728 | && S_IS_WEAK (fixP->fx_addsy) | |
9729 | /* PR 16858: Do not modify weak function references. */ | |
9730 | && ! fixP->fx_pcrel) | |
fbeb56a4 | 9731 | { |
296a8689 NC |
9732 | #if !defined (TE_PEP) |
9733 | /* For x86 PE weak function symbols are neither PC-relative | |
9734 | nor do they set S_IS_FUNCTION. So the only reliable way | |
9735 | to detect them is to check the flags of their containing | |
9736 | section. */ | |
9737 | if (S_GET_SEGMENT (fixP->fx_addsy) != NULL | |
9738 | && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE) | |
9739 | ; | |
9740 | else | |
9741 | #endif | |
fbeb56a4 DK |
9742 | value -= S_GET_VALUE (fixP->fx_addsy); |
9743 | } | |
9744 | #endif | |
252b5132 RH |
9745 | |
9746 | /* Fix a few things - the dynamic linker expects certain values here, | |
0234cb7c | 9747 | and we must not disappoint it. */ |
252b5132 | 9748 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 9749 | if (IS_ELF && fixP->fx_addsy) |
47926f60 KH |
9750 | switch (fixP->fx_r_type) |
9751 | { | |
9752 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 9753 | case BFD_RELOC_X86_64_PLT32: |
47926f60 KH |
9754 | /* Make the jump instruction point to the address of the operand. At |
9755 | runtime we merely add the offset to the actual PLT entry. */ | |
9756 | value = -4; | |
9757 | break; | |
31312f95 | 9758 | |
13ae64f3 JJ |
9759 | case BFD_RELOC_386_TLS_GD: |
9760 | case BFD_RELOC_386_TLS_LDM: | |
13ae64f3 | 9761 | case BFD_RELOC_386_TLS_IE_32: |
37e55690 JJ |
9762 | case BFD_RELOC_386_TLS_IE: |
9763 | case BFD_RELOC_386_TLS_GOTIE: | |
67a4f2b7 | 9764 | case BFD_RELOC_386_TLS_GOTDESC: |
bffbf940 JJ |
9765 | case BFD_RELOC_X86_64_TLSGD: |
9766 | case BFD_RELOC_X86_64_TLSLD: | |
9767 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 | 9768 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
00f7efb6 JJ |
9769 | value = 0; /* Fully resolved at runtime. No addend. */ |
9770 | /* Fallthrough */ | |
9771 | case BFD_RELOC_386_TLS_LE: | |
9772 | case BFD_RELOC_386_TLS_LDO_32: | |
9773 | case BFD_RELOC_386_TLS_LE_32: | |
9774 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 9775 | case BFD_RELOC_X86_64_DTPOFF64: |
00f7efb6 | 9776 | case BFD_RELOC_X86_64_TPOFF32: |
d6ab8113 | 9777 | case BFD_RELOC_X86_64_TPOFF64: |
00f7efb6 JJ |
9778 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
9779 | break; | |
9780 | ||
67a4f2b7 AO |
9781 | case BFD_RELOC_386_TLS_DESC_CALL: |
9782 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
9783 | value = 0; /* Fully resolved at runtime. No addend. */ | |
9784 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
9785 | fixP->fx_done = 0; | |
9786 | return; | |
9787 | ||
47926f60 KH |
9788 | case BFD_RELOC_VTABLE_INHERIT: |
9789 | case BFD_RELOC_VTABLE_ENTRY: | |
9790 | fixP->fx_done = 0; | |
94f592af | 9791 | return; |
47926f60 KH |
9792 | |
9793 | default: | |
9794 | break; | |
9795 | } | |
9796 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
c6682705 | 9797 | *valP = value; |
f86103b7 | 9798 | #endif /* !defined (TE_Mach) */ |
3e73aa7c | 9799 | |
3e73aa7c | 9800 | /* Are we finished with this relocation now? */ |
c6682705 | 9801 | if (fixP->fx_addsy == NULL) |
3e73aa7c | 9802 | fixP->fx_done = 1; |
fbeb56a4 DK |
9803 | #if defined (OBJ_COFF) && defined (TE_PE) |
9804 | else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) | |
9805 | { | |
9806 | fixP->fx_done = 0; | |
9807 | /* Remember value for tc_gen_reloc. */ | |
9808 | fixP->fx_addnumber = value; | |
9809 | /* Clear out the frag for now. */ | |
9810 | value = 0; | |
9811 | } | |
9812 | #endif | |
3e73aa7c JH |
9813 | else if (use_rela_relocations) |
9814 | { | |
9815 | fixP->fx_no_overflow = 1; | |
062cd5e7 AS |
9816 | /* Remember value for tc_gen_reloc. */ |
9817 | fixP->fx_addnumber = value; | |
3e73aa7c JH |
9818 | value = 0; |
9819 | } | |
f86103b7 | 9820 | |
94f592af | 9821 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 9822 | } |
252b5132 | 9823 | \f |
6d4af3c2 | 9824 | const char * |
499ac353 | 9825 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 9826 | { |
499ac353 NC |
9827 | /* This outputs the LITTLENUMs in REVERSE order; |
9828 | in accord with the bigendian 386. */ | |
9829 | return ieee_md_atof (type, litP, sizeP, FALSE); | |
252b5132 RH |
9830 | } |
9831 | \f | |
2d545b82 | 9832 | static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; |
252b5132 | 9833 | |
252b5132 | 9834 | static char * |
e3bb37b5 | 9835 | output_invalid (int c) |
252b5132 | 9836 | { |
3882b010 | 9837 | if (ISPRINT (c)) |
f9f21a03 L |
9838 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
9839 | "'%c'", c); | |
252b5132 | 9840 | else |
f9f21a03 | 9841 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
2d545b82 | 9842 | "(0x%x)", (unsigned char) c); |
252b5132 RH |
9843 | return output_invalid_buf; |
9844 | } | |
9845 | ||
af6bdddf | 9846 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
9847 | |
9848 | static const reg_entry * | |
4d1bb795 | 9849 | parse_real_register (char *reg_string, char **end_op) |
252b5132 | 9850 | { |
af6bdddf AM |
9851 | char *s = reg_string; |
9852 | char *p; | |
252b5132 RH |
9853 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
9854 | const reg_entry *r; | |
9855 | ||
9856 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
9857 | if (*s == REGISTER_PREFIX) | |
9858 | ++s; | |
9859 | ||
9860 | if (is_space_char (*s)) | |
9861 | ++s; | |
9862 | ||
9863 | p = reg_name_given; | |
af6bdddf | 9864 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
9865 | { |
9866 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
9867 | return (const reg_entry *) NULL; |
9868 | s++; | |
252b5132 RH |
9869 | } |
9870 | ||
6588847e DN |
9871 | /* For naked regs, make sure that we are not dealing with an identifier. |
9872 | This prevents confusing an identifier like `eax_var' with register | |
9873 | `eax'. */ | |
9874 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
9875 | return (const reg_entry *) NULL; | |
9876 | ||
af6bdddf | 9877 | *end_op = s; |
252b5132 RH |
9878 | |
9879 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
9880 | ||
5f47d35b | 9881 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
47926f60 | 9882 | if (r == i386_regtab /* %st is first entry of table */) |
5f47d35b | 9883 | { |
5f47d35b AM |
9884 | if (is_space_char (*s)) |
9885 | ++s; | |
9886 | if (*s == '(') | |
9887 | { | |
af6bdddf | 9888 | ++s; |
5f47d35b AM |
9889 | if (is_space_char (*s)) |
9890 | ++s; | |
9891 | if (*s >= '0' && *s <= '7') | |
9892 | { | |
db557034 | 9893 | int fpr = *s - '0'; |
af6bdddf | 9894 | ++s; |
5f47d35b AM |
9895 | if (is_space_char (*s)) |
9896 | ++s; | |
9897 | if (*s == ')') | |
9898 | { | |
9899 | *end_op = s + 1; | |
1e9cc1c2 | 9900 | r = (const reg_entry *) hash_find (reg_hash, "st(0)"); |
db557034 AM |
9901 | know (r); |
9902 | return r + fpr; | |
5f47d35b | 9903 | } |
5f47d35b | 9904 | } |
47926f60 | 9905 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
9906 | return (const reg_entry *) NULL; |
9907 | } | |
9908 | } | |
9909 | ||
a60de03c JB |
9910 | if (r == NULL || allow_pseudo_reg) |
9911 | return r; | |
9912 | ||
0dfbf9d7 | 9913 | if (operand_type_all_zero (&r->reg_type)) |
a60de03c JB |
9914 | return (const reg_entry *) NULL; |
9915 | ||
dc821c5f | 9916 | if ((r->reg_type.bitfield.dword |
192dc9c6 JB |
9917 | || r->reg_type.bitfield.sreg3 |
9918 | || r->reg_type.bitfield.control | |
9919 | || r->reg_type.bitfield.debug | |
9920 | || r->reg_type.bitfield.test) | |
9921 | && !cpu_arch_flags.bitfield.cpui386) | |
9922 | return (const reg_entry *) NULL; | |
9923 | ||
ca0d63fe | 9924 | if (r->reg_type.bitfield.tbyte |
309d3373 JB |
9925 | && !cpu_arch_flags.bitfield.cpu8087 |
9926 | && !cpu_arch_flags.bitfield.cpu287 | |
9927 | && !cpu_arch_flags.bitfield.cpu387) | |
9928 | return (const reg_entry *) NULL; | |
9929 | ||
1848e567 | 9930 | if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx) |
192dc9c6 JB |
9931 | return (const reg_entry *) NULL; |
9932 | ||
1b54b8d7 | 9933 | if (r->reg_type.bitfield.xmmword && !cpu_arch_flags.bitfield.cpuregxmm) |
192dc9c6 JB |
9934 | return (const reg_entry *) NULL; |
9935 | ||
1b54b8d7 | 9936 | if (r->reg_type.bitfield.ymmword && !cpu_arch_flags.bitfield.cpuregymm) |
40f12533 L |
9937 | return (const reg_entry *) NULL; |
9938 | ||
1b54b8d7 | 9939 | if (r->reg_type.bitfield.zmmword && !cpu_arch_flags.bitfield.cpuregzmm) |
1848e567 L |
9940 | return (const reg_entry *) NULL; |
9941 | ||
9942 | if (r->reg_type.bitfield.regmask | |
9943 | && !cpu_arch_flags.bitfield.cpuregmask) | |
43234a1e L |
9944 | return (const reg_entry *) NULL; |
9945 | ||
db51cc60 | 9946 | /* Don't allow fake index register unless allow_index_reg isn't 0. */ |
a60de03c | 9947 | if (!allow_index_reg |
db51cc60 L |
9948 | && (r->reg_num == RegEiz || r->reg_num == RegRiz)) |
9949 | return (const reg_entry *) NULL; | |
9950 | ||
43234a1e L |
9951 | /* Upper 16 vector register is only available with VREX in 64bit |
9952 | mode. */ | |
9953 | if ((r->reg_flags & RegVRex)) | |
9954 | { | |
86fa6981 L |
9955 | if (i.vec_encoding == vex_encoding_default) |
9956 | i.vec_encoding = vex_encoding_evex; | |
9957 | ||
43234a1e | 9958 | if (!cpu_arch_flags.bitfield.cpuvrex |
86fa6981 | 9959 | || i.vec_encoding != vex_encoding_evex |
43234a1e L |
9960 | || flag_code != CODE_64BIT) |
9961 | return (const reg_entry *) NULL; | |
43234a1e L |
9962 | } |
9963 | ||
a60de03c | 9964 | if (((r->reg_flags & (RegRex64 | RegRex)) |
dc821c5f | 9965 | || r->reg_type.bitfield.qword) |
40fb9820 | 9966 | && (!cpu_arch_flags.bitfield.cpulm |
0dfbf9d7 | 9967 | || !operand_type_equal (&r->reg_type, &control)) |
1ae00879 | 9968 | && flag_code != CODE_64BIT) |
20f0a1fc | 9969 | return (const reg_entry *) NULL; |
1ae00879 | 9970 | |
b7240065 JB |
9971 | if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax) |
9972 | return (const reg_entry *) NULL; | |
9973 | ||
252b5132 RH |
9974 | return r; |
9975 | } | |
4d1bb795 JB |
9976 | |
9977 | /* REG_STRING starts *before* REGISTER_PREFIX. */ | |
9978 | ||
9979 | static const reg_entry * | |
9980 | parse_register (char *reg_string, char **end_op) | |
9981 | { | |
9982 | const reg_entry *r; | |
9983 | ||
9984 | if (*reg_string == REGISTER_PREFIX || allow_naked_reg) | |
9985 | r = parse_real_register (reg_string, end_op); | |
9986 | else | |
9987 | r = NULL; | |
9988 | if (!r) | |
9989 | { | |
9990 | char *save = input_line_pointer; | |
9991 | char c; | |
9992 | symbolS *symbolP; | |
9993 | ||
9994 | input_line_pointer = reg_string; | |
d02603dc | 9995 | c = get_symbol_name (®_string); |
4d1bb795 JB |
9996 | symbolP = symbol_find (reg_string); |
9997 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) | |
9998 | { | |
9999 | const expressionS *e = symbol_get_value_expression (symbolP); | |
10000 | ||
0398aac5 | 10001 | know (e->X_op == O_register); |
4eed87de | 10002 | know (e->X_add_number >= 0 |
c3fe08fa | 10003 | && (valueT) e->X_add_number < i386_regtab_size); |
4d1bb795 | 10004 | r = i386_regtab + e->X_add_number; |
d3bb6b49 | 10005 | if ((r->reg_flags & RegVRex)) |
86fa6981 | 10006 | i.vec_encoding = vex_encoding_evex; |
4d1bb795 JB |
10007 | *end_op = input_line_pointer; |
10008 | } | |
10009 | *input_line_pointer = c; | |
10010 | input_line_pointer = save; | |
10011 | } | |
10012 | return r; | |
10013 | } | |
10014 | ||
10015 | int | |
10016 | i386_parse_name (char *name, expressionS *e, char *nextcharP) | |
10017 | { | |
10018 | const reg_entry *r; | |
10019 | char *end = input_line_pointer; | |
10020 | ||
10021 | *end = *nextcharP; | |
10022 | r = parse_register (name, &input_line_pointer); | |
10023 | if (r && end <= input_line_pointer) | |
10024 | { | |
10025 | *nextcharP = *input_line_pointer; | |
10026 | *input_line_pointer = 0; | |
10027 | e->X_op = O_register; | |
10028 | e->X_add_number = r - i386_regtab; | |
10029 | return 1; | |
10030 | } | |
10031 | input_line_pointer = end; | |
10032 | *end = 0; | |
ee86248c | 10033 | return intel_syntax ? i386_intel_parse_name (name, e) : 0; |
4d1bb795 JB |
10034 | } |
10035 | ||
10036 | void | |
10037 | md_operand (expressionS *e) | |
10038 | { | |
ee86248c JB |
10039 | char *end; |
10040 | const reg_entry *r; | |
4d1bb795 | 10041 | |
ee86248c JB |
10042 | switch (*input_line_pointer) |
10043 | { | |
10044 | case REGISTER_PREFIX: | |
10045 | r = parse_real_register (input_line_pointer, &end); | |
4d1bb795 JB |
10046 | if (r) |
10047 | { | |
10048 | e->X_op = O_register; | |
10049 | e->X_add_number = r - i386_regtab; | |
10050 | input_line_pointer = end; | |
10051 | } | |
ee86248c JB |
10052 | break; |
10053 | ||
10054 | case '[': | |
9c2799c2 | 10055 | gas_assert (intel_syntax); |
ee86248c JB |
10056 | end = input_line_pointer++; |
10057 | expression (e); | |
10058 | if (*input_line_pointer == ']') | |
10059 | { | |
10060 | ++input_line_pointer; | |
10061 | e->X_op_symbol = make_expr_symbol (e); | |
10062 | e->X_add_symbol = NULL; | |
10063 | e->X_add_number = 0; | |
10064 | e->X_op = O_index; | |
10065 | } | |
10066 | else | |
10067 | { | |
10068 | e->X_op = O_absent; | |
10069 | input_line_pointer = end; | |
10070 | } | |
10071 | break; | |
4d1bb795 JB |
10072 | } |
10073 | } | |
10074 | ||
252b5132 | 10075 | \f |
4cc782b5 | 10076 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
12b55ccc | 10077 | const char *md_shortopts = "kVQ:sqn"; |
252b5132 | 10078 | #else |
12b55ccc | 10079 | const char *md_shortopts = "qn"; |
252b5132 | 10080 | #endif |
6e0b89ee | 10081 | |
3e73aa7c | 10082 | #define OPTION_32 (OPTION_MD_BASE + 0) |
b3b91714 AM |
10083 | #define OPTION_64 (OPTION_MD_BASE + 1) |
10084 | #define OPTION_DIVIDE (OPTION_MD_BASE + 2) | |
9103f4f4 L |
10085 | #define OPTION_MARCH (OPTION_MD_BASE + 3) |
10086 | #define OPTION_MTUNE (OPTION_MD_BASE + 4) | |
1efbbeb4 L |
10087 | #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) |
10088 | #define OPTION_MSYNTAX (OPTION_MD_BASE + 6) | |
10089 | #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) | |
10090 | #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) | |
10091 | #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9) | |
c0f3af97 | 10092 | #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10) |
daf50ae7 | 10093 | #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11) |
7bab8ab5 JB |
10094 | #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12) |
10095 | #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13) | |
10096 | #define OPTION_X32 (OPTION_MD_BASE + 14) | |
7e8b059b | 10097 | #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15) |
43234a1e L |
10098 | #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16) |
10099 | #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17) | |
167ad85b | 10100 | #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18) |
d1982f93 | 10101 | #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19) |
d3d3c6db | 10102 | #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20) |
8dcea932 | 10103 | #define OPTION_MSHARED (OPTION_MD_BASE + 21) |
5db04b09 L |
10104 | #define OPTION_MAMD64 (OPTION_MD_BASE + 22) |
10105 | #define OPTION_MINTEL64 (OPTION_MD_BASE + 23) | |
e4e00185 | 10106 | #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24) |
0cb4071e | 10107 | #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25) |
b3b91714 | 10108 | |
99ad8390 NC |
10109 | struct option md_longopts[] = |
10110 | { | |
3e73aa7c | 10111 | {"32", no_argument, NULL, OPTION_32}, |
321098a5 | 10112 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 10113 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c | 10114 | {"64", no_argument, NULL, OPTION_64}, |
351f65ca L |
10115 | #endif |
10116 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
570561f7 | 10117 | {"x32", no_argument, NULL, OPTION_X32}, |
8dcea932 | 10118 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
6e0b89ee | 10119 | #endif |
b3b91714 | 10120 | {"divide", no_argument, NULL, OPTION_DIVIDE}, |
9103f4f4 L |
10121 | {"march", required_argument, NULL, OPTION_MARCH}, |
10122 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1efbbeb4 L |
10123 | {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, |
10124 | {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, | |
10125 | {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, | |
10126 | {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, | |
10127 | {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC}, | |
c0f3af97 | 10128 | {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX}, |
daf50ae7 | 10129 | {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK}, |
7bab8ab5 | 10130 | {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK}, |
539f890d | 10131 | {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR}, |
7e8b059b | 10132 | {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX}, |
43234a1e L |
10133 | {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG}, |
10134 | {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG}, | |
167ad85b TG |
10135 | # if defined (TE_PE) || defined (TE_PEP) |
10136 | {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ}, | |
10137 | #endif | |
d1982f93 | 10138 | {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX}, |
e4e00185 | 10139 | {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD}, |
0cb4071e | 10140 | {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS}, |
d3d3c6db | 10141 | {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG}, |
5db04b09 L |
10142 | {"mamd64", no_argument, NULL, OPTION_MAMD64}, |
10143 | {"mintel64", no_argument, NULL, OPTION_MINTEL64}, | |
252b5132 RH |
10144 | {NULL, no_argument, NULL, 0} |
10145 | }; | |
10146 | size_t md_longopts_size = sizeof (md_longopts); | |
10147 | ||
10148 | int | |
17b9d67d | 10149 | md_parse_option (int c, const char *arg) |
252b5132 | 10150 | { |
91d6fa6a | 10151 | unsigned int j; |
293f5f65 | 10152 | char *arch, *next, *saved; |
9103f4f4 | 10153 | |
252b5132 RH |
10154 | switch (c) |
10155 | { | |
12b55ccc L |
10156 | case 'n': |
10157 | optimize_align_code = 0; | |
10158 | break; | |
10159 | ||
a38cf1db AM |
10160 | case 'q': |
10161 | quiet_warnings = 1; | |
252b5132 RH |
10162 | break; |
10163 | ||
10164 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
10165 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
10166 | should be emitted or not. FIXME: Not implemented. */ | |
10167 | case 'Q': | |
252b5132 RH |
10168 | break; |
10169 | ||
10170 | /* -V: SVR4 argument to print version ID. */ | |
10171 | case 'V': | |
10172 | print_version_id (); | |
10173 | break; | |
10174 | ||
a38cf1db AM |
10175 | /* -k: Ignore for FreeBSD compatibility. */ |
10176 | case 'k': | |
252b5132 | 10177 | break; |
4cc782b5 ILT |
10178 | |
10179 | case 's': | |
10180 | /* -s: On i386 Solaris, this tells the native assembler to use | |
29b0f896 | 10181 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
4cc782b5 | 10182 | break; |
8dcea932 L |
10183 | |
10184 | case OPTION_MSHARED: | |
10185 | shared = 1; | |
10186 | break; | |
99ad8390 | 10187 | #endif |
321098a5 | 10188 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 10189 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c JH |
10190 | case OPTION_64: |
10191 | { | |
10192 | const char **list, **l; | |
10193 | ||
3e73aa7c JH |
10194 | list = bfd_target_list (); |
10195 | for (l = list; *l != NULL; l++) | |
8620418b | 10196 | if (CONST_STRNEQ (*l, "elf64-x86-64") |
99ad8390 NC |
10197 | || strcmp (*l, "coff-x86-64") == 0 |
10198 | || strcmp (*l, "pe-x86-64") == 0 | |
d382c579 TG |
10199 | || strcmp (*l, "pei-x86-64") == 0 |
10200 | || strcmp (*l, "mach-o-x86-64") == 0) | |
6e0b89ee AM |
10201 | { |
10202 | default_arch = "x86_64"; | |
10203 | break; | |
10204 | } | |
3e73aa7c | 10205 | if (*l == NULL) |
2b5d6a91 | 10206 | as_fatal (_("no compiled in support for x86_64")); |
3e73aa7c JH |
10207 | free (list); |
10208 | } | |
10209 | break; | |
10210 | #endif | |
252b5132 | 10211 | |
351f65ca | 10212 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
570561f7 | 10213 | case OPTION_X32: |
351f65ca L |
10214 | if (IS_ELF) |
10215 | { | |
10216 | const char **list, **l; | |
10217 | ||
10218 | list = bfd_target_list (); | |
10219 | for (l = list; *l != NULL; l++) | |
10220 | if (CONST_STRNEQ (*l, "elf32-x86-64")) | |
10221 | { | |
10222 | default_arch = "x86_64:32"; | |
10223 | break; | |
10224 | } | |
10225 | if (*l == NULL) | |
2b5d6a91 | 10226 | as_fatal (_("no compiled in support for 32bit x86_64")); |
351f65ca L |
10227 | free (list); |
10228 | } | |
10229 | else | |
10230 | as_fatal (_("32bit x86_64 is only supported for ELF")); | |
10231 | break; | |
10232 | #endif | |
10233 | ||
6e0b89ee AM |
10234 | case OPTION_32: |
10235 | default_arch = "i386"; | |
10236 | break; | |
10237 | ||
b3b91714 AM |
10238 | case OPTION_DIVIDE: |
10239 | #ifdef SVR4_COMMENT_CHARS | |
10240 | { | |
10241 | char *n, *t; | |
10242 | const char *s; | |
10243 | ||
add39d23 | 10244 | n = XNEWVEC (char, strlen (i386_comment_chars) + 1); |
b3b91714 AM |
10245 | t = n; |
10246 | for (s = i386_comment_chars; *s != '\0'; s++) | |
10247 | if (*s != '/') | |
10248 | *t++ = *s; | |
10249 | *t = '\0'; | |
10250 | i386_comment_chars = n; | |
10251 | } | |
10252 | #endif | |
10253 | break; | |
10254 | ||
9103f4f4 | 10255 | case OPTION_MARCH: |
293f5f65 L |
10256 | saved = xstrdup (arg); |
10257 | arch = saved; | |
10258 | /* Allow -march=+nosse. */ | |
10259 | if (*arch == '+') | |
10260 | arch++; | |
6305a203 | 10261 | do |
9103f4f4 | 10262 | { |
6305a203 | 10263 | if (*arch == '.') |
2b5d6a91 | 10264 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
10265 | next = strchr (arch, '+'); |
10266 | if (next) | |
10267 | *next++ = '\0'; | |
91d6fa6a | 10268 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 10269 | { |
91d6fa6a | 10270 | if (strcmp (arch, cpu_arch [j].name) == 0) |
ccc9c027 | 10271 | { |
6305a203 | 10272 | /* Processor. */ |
1ded5609 JB |
10273 | if (! cpu_arch[j].flags.bitfield.cpui386) |
10274 | continue; | |
10275 | ||
91d6fa6a | 10276 | cpu_arch_name = cpu_arch[j].name; |
6305a203 | 10277 | cpu_sub_arch_name = NULL; |
91d6fa6a NC |
10278 | cpu_arch_flags = cpu_arch[j].flags; |
10279 | cpu_arch_isa = cpu_arch[j].type; | |
10280 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
6305a203 L |
10281 | if (!cpu_arch_tune_set) |
10282 | { | |
10283 | cpu_arch_tune = cpu_arch_isa; | |
10284 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
10285 | } | |
10286 | break; | |
10287 | } | |
91d6fa6a NC |
10288 | else if (*cpu_arch [j].name == '.' |
10289 | && strcmp (arch, cpu_arch [j].name + 1) == 0) | |
6305a203 | 10290 | { |
33eaf5de | 10291 | /* ISA extension. */ |
6305a203 | 10292 | i386_cpu_flags flags; |
309d3373 | 10293 | |
293f5f65 L |
10294 | flags = cpu_flags_or (cpu_arch_flags, |
10295 | cpu_arch[j].flags); | |
81486035 | 10296 | |
5b64d091 | 10297 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
6305a203 L |
10298 | { |
10299 | if (cpu_sub_arch_name) | |
10300 | { | |
10301 | char *name = cpu_sub_arch_name; | |
10302 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 10303 | cpu_arch[j].name, |
1bf57e9f | 10304 | (const char *) NULL); |
6305a203 L |
10305 | free (name); |
10306 | } | |
10307 | else | |
91d6fa6a | 10308 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
6305a203 | 10309 | cpu_arch_flags = flags; |
a586129e | 10310 | cpu_arch_isa_flags = flags; |
6305a203 L |
10311 | } |
10312 | break; | |
ccc9c027 | 10313 | } |
9103f4f4 | 10314 | } |
6305a203 | 10315 | |
293f5f65 L |
10316 | if (j >= ARRAY_SIZE (cpu_arch)) |
10317 | { | |
33eaf5de | 10318 | /* Disable an ISA extension. */ |
293f5f65 L |
10319 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
10320 | if (strcmp (arch, cpu_noarch [j].name) == 0) | |
10321 | { | |
10322 | i386_cpu_flags flags; | |
10323 | ||
10324 | flags = cpu_flags_and_not (cpu_arch_flags, | |
10325 | cpu_noarch[j].flags); | |
10326 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
10327 | { | |
10328 | if (cpu_sub_arch_name) | |
10329 | { | |
10330 | char *name = cpu_sub_arch_name; | |
10331 | cpu_sub_arch_name = concat (arch, | |
10332 | (const char *) NULL); | |
10333 | free (name); | |
10334 | } | |
10335 | else | |
10336 | cpu_sub_arch_name = xstrdup (arch); | |
10337 | cpu_arch_flags = flags; | |
10338 | cpu_arch_isa_flags = flags; | |
10339 | } | |
10340 | break; | |
10341 | } | |
10342 | ||
10343 | if (j >= ARRAY_SIZE (cpu_noarch)) | |
10344 | j = ARRAY_SIZE (cpu_arch); | |
10345 | } | |
10346 | ||
91d6fa6a | 10347 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 10348 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
10349 | |
10350 | arch = next; | |
9103f4f4 | 10351 | } |
293f5f65 L |
10352 | while (next != NULL); |
10353 | free (saved); | |
9103f4f4 L |
10354 | break; |
10355 | ||
10356 | case OPTION_MTUNE: | |
10357 | if (*arg == '.') | |
2b5d6a91 | 10358 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
91d6fa6a | 10359 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 10360 | { |
91d6fa6a | 10361 | if (strcmp (arg, cpu_arch [j].name) == 0) |
9103f4f4 | 10362 | { |
ccc9c027 | 10363 | cpu_arch_tune_set = 1; |
91d6fa6a NC |
10364 | cpu_arch_tune = cpu_arch [j].type; |
10365 | cpu_arch_tune_flags = cpu_arch[j].flags; | |
9103f4f4 L |
10366 | break; |
10367 | } | |
10368 | } | |
91d6fa6a | 10369 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 10370 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
9103f4f4 L |
10371 | break; |
10372 | ||
1efbbeb4 L |
10373 | case OPTION_MMNEMONIC: |
10374 | if (strcasecmp (arg, "att") == 0) | |
10375 | intel_mnemonic = 0; | |
10376 | else if (strcasecmp (arg, "intel") == 0) | |
10377 | intel_mnemonic = 1; | |
10378 | else | |
2b5d6a91 | 10379 | as_fatal (_("invalid -mmnemonic= option: `%s'"), arg); |
1efbbeb4 L |
10380 | break; |
10381 | ||
10382 | case OPTION_MSYNTAX: | |
10383 | if (strcasecmp (arg, "att") == 0) | |
10384 | intel_syntax = 0; | |
10385 | else if (strcasecmp (arg, "intel") == 0) | |
10386 | intel_syntax = 1; | |
10387 | else | |
2b5d6a91 | 10388 | as_fatal (_("invalid -msyntax= option: `%s'"), arg); |
1efbbeb4 L |
10389 | break; |
10390 | ||
10391 | case OPTION_MINDEX_REG: | |
10392 | allow_index_reg = 1; | |
10393 | break; | |
10394 | ||
10395 | case OPTION_MNAKED_REG: | |
10396 | allow_naked_reg = 1; | |
10397 | break; | |
10398 | ||
10399 | case OPTION_MOLD_GCC: | |
10400 | old_gcc = 1; | |
1efbbeb4 L |
10401 | break; |
10402 | ||
c0f3af97 L |
10403 | case OPTION_MSSE2AVX: |
10404 | sse2avx = 1; | |
10405 | break; | |
10406 | ||
daf50ae7 L |
10407 | case OPTION_MSSE_CHECK: |
10408 | if (strcasecmp (arg, "error") == 0) | |
7bab8ab5 | 10409 | sse_check = check_error; |
daf50ae7 | 10410 | else if (strcasecmp (arg, "warning") == 0) |
7bab8ab5 | 10411 | sse_check = check_warning; |
daf50ae7 | 10412 | else if (strcasecmp (arg, "none") == 0) |
7bab8ab5 | 10413 | sse_check = check_none; |
daf50ae7 | 10414 | else |
2b5d6a91 | 10415 | as_fatal (_("invalid -msse-check= option: `%s'"), arg); |
daf50ae7 L |
10416 | break; |
10417 | ||
7bab8ab5 JB |
10418 | case OPTION_MOPERAND_CHECK: |
10419 | if (strcasecmp (arg, "error") == 0) | |
10420 | operand_check = check_error; | |
10421 | else if (strcasecmp (arg, "warning") == 0) | |
10422 | operand_check = check_warning; | |
10423 | else if (strcasecmp (arg, "none") == 0) | |
10424 | operand_check = check_none; | |
10425 | else | |
10426 | as_fatal (_("invalid -moperand-check= option: `%s'"), arg); | |
10427 | break; | |
10428 | ||
539f890d L |
10429 | case OPTION_MAVXSCALAR: |
10430 | if (strcasecmp (arg, "128") == 0) | |
10431 | avxscalar = vex128; | |
10432 | else if (strcasecmp (arg, "256") == 0) | |
10433 | avxscalar = vex256; | |
10434 | else | |
2b5d6a91 | 10435 | as_fatal (_("invalid -mavxscalar= option: `%s'"), arg); |
539f890d L |
10436 | break; |
10437 | ||
7e8b059b L |
10438 | case OPTION_MADD_BND_PREFIX: |
10439 | add_bnd_prefix = 1; | |
10440 | break; | |
10441 | ||
43234a1e L |
10442 | case OPTION_MEVEXLIG: |
10443 | if (strcmp (arg, "128") == 0) | |
10444 | evexlig = evexl128; | |
10445 | else if (strcmp (arg, "256") == 0) | |
10446 | evexlig = evexl256; | |
10447 | else if (strcmp (arg, "512") == 0) | |
10448 | evexlig = evexl512; | |
10449 | else | |
10450 | as_fatal (_("invalid -mevexlig= option: `%s'"), arg); | |
10451 | break; | |
10452 | ||
d3d3c6db IT |
10453 | case OPTION_MEVEXRCIG: |
10454 | if (strcmp (arg, "rne") == 0) | |
10455 | evexrcig = rne; | |
10456 | else if (strcmp (arg, "rd") == 0) | |
10457 | evexrcig = rd; | |
10458 | else if (strcmp (arg, "ru") == 0) | |
10459 | evexrcig = ru; | |
10460 | else if (strcmp (arg, "rz") == 0) | |
10461 | evexrcig = rz; | |
10462 | else | |
10463 | as_fatal (_("invalid -mevexrcig= option: `%s'"), arg); | |
10464 | break; | |
10465 | ||
43234a1e L |
10466 | case OPTION_MEVEXWIG: |
10467 | if (strcmp (arg, "0") == 0) | |
10468 | evexwig = evexw0; | |
10469 | else if (strcmp (arg, "1") == 0) | |
10470 | evexwig = evexw1; | |
10471 | else | |
10472 | as_fatal (_("invalid -mevexwig= option: `%s'"), arg); | |
10473 | break; | |
10474 | ||
167ad85b TG |
10475 | # if defined (TE_PE) || defined (TE_PEP) |
10476 | case OPTION_MBIG_OBJ: | |
10477 | use_big_obj = 1; | |
10478 | break; | |
10479 | #endif | |
10480 | ||
d1982f93 | 10481 | case OPTION_MOMIT_LOCK_PREFIX: |
d022bddd IT |
10482 | if (strcasecmp (arg, "yes") == 0) |
10483 | omit_lock_prefix = 1; | |
10484 | else if (strcasecmp (arg, "no") == 0) | |
10485 | omit_lock_prefix = 0; | |
10486 | else | |
10487 | as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg); | |
10488 | break; | |
10489 | ||
e4e00185 AS |
10490 | case OPTION_MFENCE_AS_LOCK_ADD: |
10491 | if (strcasecmp (arg, "yes") == 0) | |
10492 | avoid_fence = 1; | |
10493 | else if (strcasecmp (arg, "no") == 0) | |
10494 | avoid_fence = 0; | |
10495 | else | |
10496 | as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg); | |
10497 | break; | |
10498 | ||
0cb4071e L |
10499 | case OPTION_MRELAX_RELOCATIONS: |
10500 | if (strcasecmp (arg, "yes") == 0) | |
10501 | generate_relax_relocations = 1; | |
10502 | else if (strcasecmp (arg, "no") == 0) | |
10503 | generate_relax_relocations = 0; | |
10504 | else | |
10505 | as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg); | |
10506 | break; | |
10507 | ||
5db04b09 | 10508 | case OPTION_MAMD64: |
e89c5eaa | 10509 | intel64 = 0; |
5db04b09 L |
10510 | break; |
10511 | ||
10512 | case OPTION_MINTEL64: | |
e89c5eaa | 10513 | intel64 = 1; |
5db04b09 L |
10514 | break; |
10515 | ||
252b5132 RH |
10516 | default: |
10517 | return 0; | |
10518 | } | |
10519 | return 1; | |
10520 | } | |
10521 | ||
8a2c8fef L |
10522 | #define MESSAGE_TEMPLATE \ |
10523 | " " | |
10524 | ||
293f5f65 L |
10525 | static char * |
10526 | output_message (FILE *stream, char *p, char *message, char *start, | |
10527 | int *left_p, const char *name, int len) | |
10528 | { | |
10529 | int size = sizeof (MESSAGE_TEMPLATE); | |
10530 | int left = *left_p; | |
10531 | ||
10532 | /* Reserve 2 spaces for ", " or ",\0" */ | |
10533 | left -= len + 2; | |
10534 | ||
10535 | /* Check if there is any room. */ | |
10536 | if (left >= 0) | |
10537 | { | |
10538 | if (p != start) | |
10539 | { | |
10540 | *p++ = ','; | |
10541 | *p++ = ' '; | |
10542 | } | |
10543 | p = mempcpy (p, name, len); | |
10544 | } | |
10545 | else | |
10546 | { | |
10547 | /* Output the current message now and start a new one. */ | |
10548 | *p++ = ','; | |
10549 | *p = '\0'; | |
10550 | fprintf (stream, "%s\n", message); | |
10551 | p = start; | |
10552 | left = size - (start - message) - len - 2; | |
10553 | ||
10554 | gas_assert (left >= 0); | |
10555 | ||
10556 | p = mempcpy (p, name, len); | |
10557 | } | |
10558 | ||
10559 | *left_p = left; | |
10560 | return p; | |
10561 | } | |
10562 | ||
8a2c8fef | 10563 | static void |
1ded5609 | 10564 | show_arch (FILE *stream, int ext, int check) |
8a2c8fef L |
10565 | { |
10566 | static char message[] = MESSAGE_TEMPLATE; | |
10567 | char *start = message + 27; | |
10568 | char *p; | |
10569 | int size = sizeof (MESSAGE_TEMPLATE); | |
10570 | int left; | |
10571 | const char *name; | |
10572 | int len; | |
10573 | unsigned int j; | |
10574 | ||
10575 | p = start; | |
10576 | left = size - (start - message); | |
10577 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) | |
10578 | { | |
10579 | /* Should it be skipped? */ | |
10580 | if (cpu_arch [j].skip) | |
10581 | continue; | |
10582 | ||
10583 | name = cpu_arch [j].name; | |
10584 | len = cpu_arch [j].len; | |
10585 | if (*name == '.') | |
10586 | { | |
10587 | /* It is an extension. Skip if we aren't asked to show it. */ | |
10588 | if (ext) | |
10589 | { | |
10590 | name++; | |
10591 | len--; | |
10592 | } | |
10593 | else | |
10594 | continue; | |
10595 | } | |
10596 | else if (ext) | |
10597 | { | |
10598 | /* It is an processor. Skip if we show only extension. */ | |
10599 | continue; | |
10600 | } | |
1ded5609 JB |
10601 | else if (check && ! cpu_arch[j].flags.bitfield.cpui386) |
10602 | { | |
10603 | /* It is an impossible processor - skip. */ | |
10604 | continue; | |
10605 | } | |
8a2c8fef | 10606 | |
293f5f65 | 10607 | p = output_message (stream, p, message, start, &left, name, len); |
8a2c8fef L |
10608 | } |
10609 | ||
293f5f65 L |
10610 | /* Display disabled extensions. */ |
10611 | if (ext) | |
10612 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) | |
10613 | { | |
10614 | name = cpu_noarch [j].name; | |
10615 | len = cpu_noarch [j].len; | |
10616 | p = output_message (stream, p, message, start, &left, name, | |
10617 | len); | |
10618 | } | |
10619 | ||
8a2c8fef L |
10620 | *p = '\0'; |
10621 | fprintf (stream, "%s\n", message); | |
10622 | } | |
10623 | ||
252b5132 | 10624 | void |
8a2c8fef | 10625 | md_show_usage (FILE *stream) |
252b5132 | 10626 | { |
4cc782b5 ILT |
10627 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
10628 | fprintf (stream, _("\ | |
a38cf1db AM |
10629 | -Q ignored\n\ |
10630 | -V print assembler version number\n\ | |
b3b91714 AM |
10631 | -k ignored\n")); |
10632 | #endif | |
10633 | fprintf (stream, _("\ | |
12b55ccc | 10634 | -n Do not optimize code alignment\n\ |
b3b91714 AM |
10635 | -q quieten some warnings\n")); |
10636 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
10637 | fprintf (stream, _("\ | |
a38cf1db | 10638 | -s ignored\n")); |
b3b91714 | 10639 | #endif |
321098a5 L |
10640 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
10641 | || defined (TE_PE) || defined (TE_PEP)) | |
751d281c | 10642 | fprintf (stream, _("\ |
570561f7 | 10643 | --32/--64/--x32 generate 32bit/64bit/x32 code\n")); |
751d281c | 10644 | #endif |
b3b91714 AM |
10645 | #ifdef SVR4_COMMENT_CHARS |
10646 | fprintf (stream, _("\ | |
10647 | --divide do not treat `/' as a comment character\n")); | |
a38cf1db AM |
10648 | #else |
10649 | fprintf (stream, _("\ | |
b3b91714 | 10650 | --divide ignored\n")); |
4cc782b5 | 10651 | #endif |
9103f4f4 | 10652 | fprintf (stream, _("\ |
6305a203 | 10653 | -march=CPU[,+EXTENSION...]\n\ |
8a2c8fef | 10654 | generate code for CPU and EXTENSION, CPU is one of:\n")); |
1ded5609 | 10655 | show_arch (stream, 0, 1); |
8a2c8fef L |
10656 | fprintf (stream, _("\ |
10657 | EXTENSION is combination of:\n")); | |
1ded5609 | 10658 | show_arch (stream, 1, 0); |
6305a203 | 10659 | fprintf (stream, _("\ |
8a2c8fef | 10660 | -mtune=CPU optimize for CPU, CPU is one of:\n")); |
1ded5609 | 10661 | show_arch (stream, 0, 0); |
ba104c83 | 10662 | fprintf (stream, _("\ |
c0f3af97 L |
10663 | -msse2avx encode SSE instructions with VEX prefix\n")); |
10664 | fprintf (stream, _("\ | |
daf50ae7 L |
10665 | -msse-check=[none|error|warning]\n\ |
10666 | check SSE instructions\n")); | |
10667 | fprintf (stream, _("\ | |
7bab8ab5 JB |
10668 | -moperand-check=[none|error|warning]\n\ |
10669 | check operand combinations for validity\n")); | |
10670 | fprintf (stream, _("\ | |
539f890d L |
10671 | -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\ |
10672 | length\n")); | |
10673 | fprintf (stream, _("\ | |
43234a1e L |
10674 | -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\ |
10675 | length\n")); | |
10676 | fprintf (stream, _("\ | |
10677 | -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\ | |
10678 | for EVEX.W bit ignored instructions\n")); | |
10679 | fprintf (stream, _("\ | |
d3d3c6db IT |
10680 | -mevexrcig=[rne|rd|ru|rz]\n\ |
10681 | encode EVEX instructions with specific EVEX.RC value\n\ | |
10682 | for SAE-only ignored instructions\n")); | |
10683 | fprintf (stream, _("\ | |
ba104c83 L |
10684 | -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n")); |
10685 | fprintf (stream, _("\ | |
10686 | -msyntax=[att|intel] use AT&T/Intel syntax\n")); | |
10687 | fprintf (stream, _("\ | |
10688 | -mindex-reg support pseudo index registers\n")); | |
10689 | fprintf (stream, _("\ | |
10690 | -mnaked-reg don't require `%%' prefix for registers\n")); | |
10691 | fprintf (stream, _("\ | |
10692 | -mold-gcc support old (<= 2.8.1) versions of gcc\n")); | |
7e8b059b L |
10693 | fprintf (stream, _("\ |
10694 | -madd-bnd-prefix add BND prefix for all valid branches\n")); | |
8dcea932 L |
10695 | fprintf (stream, _("\ |
10696 | -mshared disable branch optimization for shared code\n")); | |
167ad85b TG |
10697 | # if defined (TE_PE) || defined (TE_PEP) |
10698 | fprintf (stream, _("\ | |
10699 | -mbig-obj generate big object files\n")); | |
10700 | #endif | |
d022bddd IT |
10701 | fprintf (stream, _("\ |
10702 | -momit-lock-prefix=[no|yes]\n\ | |
10703 | strip all lock prefixes\n")); | |
5db04b09 | 10704 | fprintf (stream, _("\ |
e4e00185 AS |
10705 | -mfence-as-lock-add=[no|yes]\n\ |
10706 | encode lfence, mfence and sfence as\n\ | |
10707 | lock addl $0x0, (%%{re}sp)\n")); | |
10708 | fprintf (stream, _("\ | |
0cb4071e L |
10709 | -mrelax-relocations=[no|yes]\n\ |
10710 | generate relax relocations\n")); | |
10711 | fprintf (stream, _("\ | |
5db04b09 L |
10712 | -mamd64 accept only AMD64 ISA\n")); |
10713 | fprintf (stream, _("\ | |
10714 | -mintel64 accept only Intel64 ISA\n")); | |
252b5132 RH |
10715 | } |
10716 | ||
3e73aa7c | 10717 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
321098a5 | 10718 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
e57f8c65 | 10719 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
252b5132 RH |
10720 | |
10721 | /* Pick the target format to use. */ | |
10722 | ||
47926f60 | 10723 | const char * |
e3bb37b5 | 10724 | i386_target_format (void) |
252b5132 | 10725 | { |
351f65ca L |
10726 | if (!strncmp (default_arch, "x86_64", 6)) |
10727 | { | |
10728 | update_code_flag (CODE_64BIT, 1); | |
10729 | if (default_arch[6] == '\0') | |
7f56bc95 | 10730 | x86_elf_abi = X86_64_ABI; |
351f65ca | 10731 | else |
7f56bc95 | 10732 | x86_elf_abi = X86_64_X32_ABI; |
351f65ca | 10733 | } |
3e73aa7c | 10734 | else if (!strcmp (default_arch, "i386")) |
78f12dd3 | 10735 | update_code_flag (CODE_32BIT, 1); |
5197d474 L |
10736 | else if (!strcmp (default_arch, "iamcu")) |
10737 | { | |
10738 | update_code_flag (CODE_32BIT, 1); | |
10739 | if (cpu_arch_isa == PROCESSOR_UNKNOWN) | |
10740 | { | |
10741 | static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS; | |
10742 | cpu_arch_name = "iamcu"; | |
10743 | cpu_sub_arch_name = NULL; | |
10744 | cpu_arch_flags = iamcu_flags; | |
10745 | cpu_arch_isa = PROCESSOR_IAMCU; | |
10746 | cpu_arch_isa_flags = iamcu_flags; | |
10747 | if (!cpu_arch_tune_set) | |
10748 | { | |
10749 | cpu_arch_tune = cpu_arch_isa; | |
10750 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
10751 | } | |
10752 | } | |
8d471ec1 | 10753 | else if (cpu_arch_isa != PROCESSOR_IAMCU) |
5197d474 L |
10754 | as_fatal (_("Intel MCU doesn't support `%s' architecture"), |
10755 | cpu_arch_name); | |
10756 | } | |
3e73aa7c | 10757 | else |
2b5d6a91 | 10758 | as_fatal (_("unknown architecture")); |
89507696 JB |
10759 | |
10760 | if (cpu_flags_all_zero (&cpu_arch_isa_flags)) | |
10761 | cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
10762 | if (cpu_flags_all_zero (&cpu_arch_tune_flags)) | |
10763 | cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
10764 | ||
252b5132 RH |
10765 | switch (OUTPUT_FLAVOR) |
10766 | { | |
9384f2ff | 10767 | #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT) |
4c63da97 | 10768 | case bfd_target_aout_flavour: |
47926f60 | 10769 | return AOUT_TARGET_FORMAT; |
4c63da97 | 10770 | #endif |
9384f2ff AM |
10771 | #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF) |
10772 | # if defined (TE_PE) || defined (TE_PEP) | |
10773 | case bfd_target_coff_flavour: | |
167ad85b TG |
10774 | if (flag_code == CODE_64BIT) |
10775 | return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64"; | |
10776 | else | |
10777 | return "pe-i386"; | |
9384f2ff | 10778 | # elif defined (TE_GO32) |
0561d57c JK |
10779 | case bfd_target_coff_flavour: |
10780 | return "coff-go32"; | |
9384f2ff | 10781 | # else |
252b5132 RH |
10782 | case bfd_target_coff_flavour: |
10783 | return "coff-i386"; | |
9384f2ff | 10784 | # endif |
4c63da97 | 10785 | #endif |
3e73aa7c | 10786 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 10787 | case bfd_target_elf_flavour: |
3e73aa7c | 10788 | { |
351f65ca L |
10789 | const char *format; |
10790 | ||
10791 | switch (x86_elf_abi) | |
4fa24527 | 10792 | { |
351f65ca L |
10793 | default: |
10794 | format = ELF_TARGET_FORMAT; | |
10795 | break; | |
7f56bc95 | 10796 | case X86_64_ABI: |
351f65ca | 10797 | use_rela_relocations = 1; |
4fa24527 | 10798 | object_64bit = 1; |
351f65ca L |
10799 | format = ELF_TARGET_FORMAT64; |
10800 | break; | |
7f56bc95 | 10801 | case X86_64_X32_ABI: |
4fa24527 | 10802 | use_rela_relocations = 1; |
351f65ca | 10803 | object_64bit = 1; |
862be3fb | 10804 | disallow_64bit_reloc = 1; |
351f65ca L |
10805 | format = ELF_TARGET_FORMAT32; |
10806 | break; | |
4fa24527 | 10807 | } |
3632d14b | 10808 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 10809 | { |
7f56bc95 | 10810 | if (x86_elf_abi != X86_64_ABI) |
8a9036a4 L |
10811 | as_fatal (_("Intel L1OM is 64bit only")); |
10812 | return ELF_TARGET_L1OM_FORMAT; | |
10813 | } | |
b49f93f6 | 10814 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
7a9068fe L |
10815 | { |
10816 | if (x86_elf_abi != X86_64_ABI) | |
10817 | as_fatal (_("Intel K1OM is 64bit only")); | |
10818 | return ELF_TARGET_K1OM_FORMAT; | |
10819 | } | |
81486035 L |
10820 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
10821 | { | |
10822 | if (x86_elf_abi != I386_ABI) | |
10823 | as_fatal (_("Intel MCU is 32bit only")); | |
10824 | return ELF_TARGET_IAMCU_FORMAT; | |
10825 | } | |
8a9036a4 | 10826 | else |
351f65ca | 10827 | return format; |
3e73aa7c | 10828 | } |
e57f8c65 TG |
10829 | #endif |
10830 | #if defined (OBJ_MACH_O) | |
10831 | case bfd_target_mach_o_flavour: | |
d382c579 TG |
10832 | if (flag_code == CODE_64BIT) |
10833 | { | |
10834 | use_rela_relocations = 1; | |
10835 | object_64bit = 1; | |
10836 | return "mach-o-x86-64"; | |
10837 | } | |
10838 | else | |
10839 | return "mach-o-i386"; | |
4c63da97 | 10840 | #endif |
252b5132 RH |
10841 | default: |
10842 | abort (); | |
10843 | return NULL; | |
10844 | } | |
10845 | } | |
10846 | ||
47926f60 | 10847 | #endif /* OBJ_MAYBE_ more than one */ |
252b5132 | 10848 | \f |
252b5132 | 10849 | symbolS * |
7016a5d5 | 10850 | md_undefined_symbol (char *name) |
252b5132 | 10851 | { |
18dc2407 ILT |
10852 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
10853 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
10854 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
10855 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
10856 | { |
10857 | if (!GOT_symbol) | |
10858 | { | |
10859 | if (symbol_find (name)) | |
10860 | as_bad (_("GOT already in symbol table")); | |
10861 | GOT_symbol = symbol_new (name, undefined_section, | |
10862 | (valueT) 0, &zero_address_frag); | |
10863 | }; | |
10864 | return GOT_symbol; | |
10865 | } | |
252b5132 RH |
10866 | return 0; |
10867 | } | |
10868 | ||
10869 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 10870 | |
252b5132 | 10871 | valueT |
7016a5d5 | 10872 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
252b5132 | 10873 | { |
4c63da97 AM |
10874 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
10875 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
10876 | { | |
10877 | /* For a.out, force the section size to be aligned. If we don't do | |
10878 | this, BFD will align it for us, but it will not write out the | |
10879 | final bytes of the section. This may be a bug in BFD, but it is | |
10880 | easier to fix it here since that is how the other a.out targets | |
10881 | work. */ | |
10882 | int align; | |
10883 | ||
10884 | align = bfd_get_section_alignment (stdoutput, segment); | |
8d3842cd | 10885 | size = ((size + (1 << align) - 1) & (-((valueT) 1 << align))); |
4c63da97 | 10886 | } |
252b5132 RH |
10887 | #endif |
10888 | ||
10889 | return size; | |
10890 | } | |
10891 | ||
10892 | /* On the i386, PC-relative offsets are relative to the start of the | |
10893 | next instruction. That is, the address of the offset, plus its | |
10894 | size, since the offset is always the last part of the insn. */ | |
10895 | ||
10896 | long | |
e3bb37b5 | 10897 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
10898 | { |
10899 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
10900 | } | |
10901 | ||
10902 | #ifndef I386COFF | |
10903 | ||
10904 | static void | |
e3bb37b5 | 10905 | s_bss (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 10906 | { |
29b0f896 | 10907 | int temp; |
252b5132 | 10908 | |
8a75718c JB |
10909 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
10910 | if (IS_ELF) | |
10911 | obj_elf_section_change_hook (); | |
10912 | #endif | |
252b5132 RH |
10913 | temp = get_absolute_expression (); |
10914 | subseg_set (bss_section, (subsegT) temp); | |
10915 | demand_empty_rest_of_line (); | |
10916 | } | |
10917 | ||
10918 | #endif | |
10919 | ||
252b5132 | 10920 | void |
e3bb37b5 | 10921 | i386_validate_fix (fixS *fixp) |
252b5132 | 10922 | { |
02a86693 | 10923 | if (fixp->fx_subsy) |
252b5132 | 10924 | { |
02a86693 | 10925 | if (fixp->fx_subsy == GOT_symbol) |
23df1078 | 10926 | { |
02a86693 L |
10927 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
10928 | { | |
10929 | if (!object_64bit) | |
10930 | abort (); | |
10931 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
10932 | if (fixp->fx_tcbit2) | |
56ceb5b5 L |
10933 | fixp->fx_r_type = (fixp->fx_tcbit |
10934 | ? BFD_RELOC_X86_64_REX_GOTPCRELX | |
10935 | : BFD_RELOC_X86_64_GOTPCRELX); | |
02a86693 L |
10936 | else |
10937 | #endif | |
10938 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
10939 | } | |
d6ab8113 | 10940 | else |
02a86693 L |
10941 | { |
10942 | if (!object_64bit) | |
10943 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
10944 | else | |
10945 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; | |
10946 | } | |
10947 | fixp->fx_subsy = 0; | |
23df1078 | 10948 | } |
252b5132 | 10949 | } |
02a86693 L |
10950 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
10951 | else if (!object_64bit) | |
10952 | { | |
10953 | if (fixp->fx_r_type == BFD_RELOC_386_GOT32 | |
10954 | && fixp->fx_tcbit2) | |
10955 | fixp->fx_r_type = BFD_RELOC_386_GOT32X; | |
10956 | } | |
10957 | #endif | |
252b5132 RH |
10958 | } |
10959 | ||
252b5132 | 10960 | arelent * |
7016a5d5 | 10961 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
10962 | { |
10963 | arelent *rel; | |
10964 | bfd_reloc_code_real_type code; | |
10965 | ||
10966 | switch (fixp->fx_r_type) | |
10967 | { | |
8ce3d284 | 10968 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
10969 | case BFD_RELOC_SIZE32: |
10970 | case BFD_RELOC_SIZE64: | |
10971 | if (S_IS_DEFINED (fixp->fx_addsy) | |
10972 | && !S_IS_EXTERNAL (fixp->fx_addsy)) | |
10973 | { | |
10974 | /* Resolve size relocation against local symbol to size of | |
10975 | the symbol plus addend. */ | |
10976 | valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset; | |
10977 | if (fixp->fx_r_type == BFD_RELOC_SIZE32 | |
10978 | && !fits_in_unsigned_long (value)) | |
10979 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
10980 | _("symbol size computation overflow")); | |
10981 | fixp->fx_addsy = NULL; | |
10982 | fixp->fx_subsy = NULL; | |
10983 | md_apply_fix (fixp, (valueT *) &value, NULL); | |
10984 | return NULL; | |
10985 | } | |
8ce3d284 | 10986 | #endif |
1a0670f3 | 10987 | /* Fall through. */ |
8fd4256d | 10988 | |
3e73aa7c JH |
10989 | case BFD_RELOC_X86_64_PLT32: |
10990 | case BFD_RELOC_X86_64_GOT32: | |
10991 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
10992 | case BFD_RELOC_X86_64_GOTPCRELX: |
10993 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
252b5132 RH |
10994 | case BFD_RELOC_386_PLT32: |
10995 | case BFD_RELOC_386_GOT32: | |
02a86693 | 10996 | case BFD_RELOC_386_GOT32X: |
252b5132 RH |
10997 | case BFD_RELOC_386_GOTOFF: |
10998 | case BFD_RELOC_386_GOTPC: | |
13ae64f3 JJ |
10999 | case BFD_RELOC_386_TLS_GD: |
11000 | case BFD_RELOC_386_TLS_LDM: | |
11001 | case BFD_RELOC_386_TLS_LDO_32: | |
11002 | case BFD_RELOC_386_TLS_IE_32: | |
37e55690 JJ |
11003 | case BFD_RELOC_386_TLS_IE: |
11004 | case BFD_RELOC_386_TLS_GOTIE: | |
13ae64f3 JJ |
11005 | case BFD_RELOC_386_TLS_LE_32: |
11006 | case BFD_RELOC_386_TLS_LE: | |
67a4f2b7 AO |
11007 | case BFD_RELOC_386_TLS_GOTDESC: |
11008 | case BFD_RELOC_386_TLS_DESC_CALL: | |
bffbf940 JJ |
11009 | case BFD_RELOC_X86_64_TLSGD: |
11010 | case BFD_RELOC_X86_64_TLSLD: | |
11011 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 11012 | case BFD_RELOC_X86_64_DTPOFF64: |
bffbf940 JJ |
11013 | case BFD_RELOC_X86_64_GOTTPOFF: |
11014 | case BFD_RELOC_X86_64_TPOFF32: | |
d6ab8113 JB |
11015 | case BFD_RELOC_X86_64_TPOFF64: |
11016 | case BFD_RELOC_X86_64_GOTOFF64: | |
11017 | case BFD_RELOC_X86_64_GOTPC32: | |
7b81dfbb AJ |
11018 | case BFD_RELOC_X86_64_GOT64: |
11019 | case BFD_RELOC_X86_64_GOTPCREL64: | |
11020 | case BFD_RELOC_X86_64_GOTPC64: | |
11021 | case BFD_RELOC_X86_64_GOTPLT64: | |
11022 | case BFD_RELOC_X86_64_PLTOFF64: | |
67a4f2b7 AO |
11023 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
11024 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
252b5132 RH |
11025 | case BFD_RELOC_RVA: |
11026 | case BFD_RELOC_VTABLE_ENTRY: | |
11027 | case BFD_RELOC_VTABLE_INHERIT: | |
6482c264 NC |
11028 | #ifdef TE_PE |
11029 | case BFD_RELOC_32_SECREL: | |
11030 | #endif | |
252b5132 RH |
11031 | code = fixp->fx_r_type; |
11032 | break; | |
dbbaec26 L |
11033 | case BFD_RELOC_X86_64_32S: |
11034 | if (!fixp->fx_pcrel) | |
11035 | { | |
11036 | /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ | |
11037 | code = fixp->fx_r_type; | |
11038 | break; | |
11039 | } | |
1a0670f3 | 11040 | /* Fall through. */ |
252b5132 | 11041 | default: |
93382f6d | 11042 | if (fixp->fx_pcrel) |
252b5132 | 11043 | { |
93382f6d AM |
11044 | switch (fixp->fx_size) |
11045 | { | |
11046 | default: | |
b091f402 AM |
11047 | as_bad_where (fixp->fx_file, fixp->fx_line, |
11048 | _("can not do %d byte pc-relative relocation"), | |
11049 | fixp->fx_size); | |
93382f6d AM |
11050 | code = BFD_RELOC_32_PCREL; |
11051 | break; | |
11052 | case 1: code = BFD_RELOC_8_PCREL; break; | |
11053 | case 2: code = BFD_RELOC_16_PCREL; break; | |
d258b828 | 11054 | case 4: code = BFD_RELOC_32_PCREL; break; |
d6ab8113 JB |
11055 | #ifdef BFD64 |
11056 | case 8: code = BFD_RELOC_64_PCREL; break; | |
11057 | #endif | |
93382f6d AM |
11058 | } |
11059 | } | |
11060 | else | |
11061 | { | |
11062 | switch (fixp->fx_size) | |
11063 | { | |
11064 | default: | |
b091f402 AM |
11065 | as_bad_where (fixp->fx_file, fixp->fx_line, |
11066 | _("can not do %d byte relocation"), | |
11067 | fixp->fx_size); | |
93382f6d AM |
11068 | code = BFD_RELOC_32; |
11069 | break; | |
11070 | case 1: code = BFD_RELOC_8; break; | |
11071 | case 2: code = BFD_RELOC_16; break; | |
11072 | case 4: code = BFD_RELOC_32; break; | |
937149dd | 11073 | #ifdef BFD64 |
3e73aa7c | 11074 | case 8: code = BFD_RELOC_64; break; |
937149dd | 11075 | #endif |
93382f6d | 11076 | } |
252b5132 RH |
11077 | } |
11078 | break; | |
11079 | } | |
252b5132 | 11080 | |
d182319b JB |
11081 | if ((code == BFD_RELOC_32 |
11082 | || code == BFD_RELOC_32_PCREL | |
11083 | || code == BFD_RELOC_X86_64_32S) | |
252b5132 RH |
11084 | && GOT_symbol |
11085 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c | 11086 | { |
4fa24527 | 11087 | if (!object_64bit) |
d6ab8113 JB |
11088 | code = BFD_RELOC_386_GOTPC; |
11089 | else | |
11090 | code = BFD_RELOC_X86_64_GOTPC32; | |
3e73aa7c | 11091 | } |
7b81dfbb AJ |
11092 | if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) |
11093 | && GOT_symbol | |
11094 | && fixp->fx_addsy == GOT_symbol) | |
11095 | { | |
11096 | code = BFD_RELOC_X86_64_GOTPC64; | |
11097 | } | |
252b5132 | 11098 | |
add39d23 TS |
11099 | rel = XNEW (arelent); |
11100 | rel->sym_ptr_ptr = XNEW (asymbol *); | |
49309057 | 11101 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
11102 | |
11103 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
c87db184 | 11104 | |
3e73aa7c JH |
11105 | if (!use_rela_relocations) |
11106 | { | |
11107 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
11108 | vtable entry to be used in the relocation's section offset. */ | |
11109 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
11110 | rel->address = fixp->fx_offset; | |
fbeb56a4 DK |
11111 | #if defined (OBJ_COFF) && defined (TE_PE) |
11112 | else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy)) | |
11113 | rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2); | |
11114 | else | |
11115 | #endif | |
c6682705 | 11116 | rel->addend = 0; |
3e73aa7c JH |
11117 | } |
11118 | /* Use the rela in 64bit mode. */ | |
252b5132 | 11119 | else |
3e73aa7c | 11120 | { |
862be3fb L |
11121 | if (disallow_64bit_reloc) |
11122 | switch (code) | |
11123 | { | |
862be3fb L |
11124 | case BFD_RELOC_X86_64_DTPOFF64: |
11125 | case BFD_RELOC_X86_64_TPOFF64: | |
11126 | case BFD_RELOC_64_PCREL: | |
11127 | case BFD_RELOC_X86_64_GOTOFF64: | |
11128 | case BFD_RELOC_X86_64_GOT64: | |
11129 | case BFD_RELOC_X86_64_GOTPCREL64: | |
11130 | case BFD_RELOC_X86_64_GOTPC64: | |
11131 | case BFD_RELOC_X86_64_GOTPLT64: | |
11132 | case BFD_RELOC_X86_64_PLTOFF64: | |
11133 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
11134 | _("cannot represent relocation type %s in x32 mode"), | |
11135 | bfd_get_reloc_code_name (code)); | |
11136 | break; | |
11137 | default: | |
11138 | break; | |
11139 | } | |
11140 | ||
062cd5e7 AS |
11141 | if (!fixp->fx_pcrel) |
11142 | rel->addend = fixp->fx_offset; | |
11143 | else | |
11144 | switch (code) | |
11145 | { | |
11146 | case BFD_RELOC_X86_64_PLT32: | |
11147 | case BFD_RELOC_X86_64_GOT32: | |
11148 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
11149 | case BFD_RELOC_X86_64_GOTPCRELX: |
11150 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
bffbf940 JJ |
11151 | case BFD_RELOC_X86_64_TLSGD: |
11152 | case BFD_RELOC_X86_64_TLSLD: | |
11153 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 AO |
11154 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
11155 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
062cd5e7 AS |
11156 | rel->addend = fixp->fx_offset - fixp->fx_size; |
11157 | break; | |
11158 | default: | |
11159 | rel->addend = (section->vma | |
11160 | - fixp->fx_size | |
11161 | + fixp->fx_addnumber | |
11162 | + md_pcrel_from (fixp)); | |
11163 | break; | |
11164 | } | |
3e73aa7c JH |
11165 | } |
11166 | ||
252b5132 RH |
11167 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
11168 | if (rel->howto == NULL) | |
11169 | { | |
11170 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 11171 | _("cannot represent relocation type %s"), |
252b5132 RH |
11172 | bfd_get_reloc_code_name (code)); |
11173 | /* Set howto to a garbage value so that we can keep going. */ | |
11174 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
9c2799c2 | 11175 | gas_assert (rel->howto != NULL); |
252b5132 RH |
11176 | } |
11177 | ||
11178 | return rel; | |
11179 | } | |
11180 | ||
ee86248c | 11181 | #include "tc-i386-intel.c" |
54cfded0 | 11182 | |
a60de03c JB |
11183 | void |
11184 | tc_x86_parse_to_dw2regnum (expressionS *exp) | |
54cfded0 | 11185 | { |
a60de03c JB |
11186 | int saved_naked_reg; |
11187 | char saved_register_dot; | |
54cfded0 | 11188 | |
a60de03c JB |
11189 | saved_naked_reg = allow_naked_reg; |
11190 | allow_naked_reg = 1; | |
11191 | saved_register_dot = register_chars['.']; | |
11192 | register_chars['.'] = '.'; | |
11193 | allow_pseudo_reg = 1; | |
11194 | expression_and_evaluate (exp); | |
11195 | allow_pseudo_reg = 0; | |
11196 | register_chars['.'] = saved_register_dot; | |
11197 | allow_naked_reg = saved_naked_reg; | |
11198 | ||
e96d56a1 | 11199 | if (exp->X_op == O_register && exp->X_add_number >= 0) |
54cfded0 | 11200 | { |
a60de03c JB |
11201 | if ((addressT) exp->X_add_number < i386_regtab_size) |
11202 | { | |
11203 | exp->X_op = O_constant; | |
11204 | exp->X_add_number = i386_regtab[exp->X_add_number] | |
11205 | .dw2_regnum[flag_code >> 1]; | |
11206 | } | |
11207 | else | |
11208 | exp->X_op = O_illegal; | |
54cfded0 | 11209 | } |
54cfded0 AM |
11210 | } |
11211 | ||
11212 | void | |
11213 | tc_x86_frame_initial_instructions (void) | |
11214 | { | |
a60de03c JB |
11215 | static unsigned int sp_regno[2]; |
11216 | ||
11217 | if (!sp_regno[flag_code >> 1]) | |
11218 | { | |
11219 | char *saved_input = input_line_pointer; | |
11220 | char sp[][4] = {"esp", "rsp"}; | |
11221 | expressionS exp; | |
a4447b93 | 11222 | |
a60de03c JB |
11223 | input_line_pointer = sp[flag_code >> 1]; |
11224 | tc_x86_parse_to_dw2regnum (&exp); | |
9c2799c2 | 11225 | gas_assert (exp.X_op == O_constant); |
a60de03c JB |
11226 | sp_regno[flag_code >> 1] = exp.X_add_number; |
11227 | input_line_pointer = saved_input; | |
11228 | } | |
a4447b93 | 11229 | |
61ff971f L |
11230 | cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment); |
11231 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); | |
54cfded0 | 11232 | } |
d2b2c203 | 11233 | |
d7921315 L |
11234 | int |
11235 | x86_dwarf2_addr_size (void) | |
11236 | { | |
11237 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) | |
11238 | if (x86_elf_abi == X86_64_X32_ABI) | |
11239 | return 4; | |
11240 | #endif | |
11241 | return bfd_arch_bits_per_address (stdoutput) / 8; | |
11242 | } | |
11243 | ||
d2b2c203 DJ |
11244 | int |
11245 | i386_elf_section_type (const char *str, size_t len) | |
11246 | { | |
11247 | if (flag_code == CODE_64BIT | |
11248 | && len == sizeof ("unwind") - 1 | |
11249 | && strncmp (str, "unwind", 6) == 0) | |
11250 | return SHT_X86_64_UNWIND; | |
11251 | ||
11252 | return -1; | |
11253 | } | |
bb41ade5 | 11254 | |
ad5fec3b EB |
11255 | #ifdef TE_SOLARIS |
11256 | void | |
11257 | i386_solaris_fix_up_eh_frame (segT sec) | |
11258 | { | |
11259 | if (flag_code == CODE_64BIT) | |
11260 | elf_section_type (sec) = SHT_X86_64_UNWIND; | |
11261 | } | |
11262 | #endif | |
11263 | ||
bb41ade5 AM |
11264 | #ifdef TE_PE |
11265 | void | |
11266 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) | |
11267 | { | |
91d6fa6a | 11268 | expressionS exp; |
bb41ade5 | 11269 | |
91d6fa6a NC |
11270 | exp.X_op = O_secrel; |
11271 | exp.X_add_symbol = symbol; | |
11272 | exp.X_add_number = 0; | |
11273 | emit_expr (&exp, size); | |
bb41ade5 AM |
11274 | } |
11275 | #endif | |
3b22753a L |
11276 | |
11277 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
11278 | /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ | |
11279 | ||
01e1a5bc | 11280 | bfd_vma |
6d4af3c2 | 11281 | x86_64_section_letter (int letter, const char **ptr_msg) |
3b22753a L |
11282 | { |
11283 | if (flag_code == CODE_64BIT) | |
11284 | { | |
11285 | if (letter == 'l') | |
11286 | return SHF_X86_64_LARGE; | |
11287 | ||
8f3bae45 | 11288 | *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string"); |
64e74474 | 11289 | } |
3b22753a | 11290 | else |
8f3bae45 | 11291 | *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string"); |
3b22753a L |
11292 | return -1; |
11293 | } | |
11294 | ||
01e1a5bc | 11295 | bfd_vma |
3b22753a L |
11296 | x86_64_section_word (char *str, size_t len) |
11297 | { | |
8620418b | 11298 | if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large")) |
3b22753a L |
11299 | return SHF_X86_64_LARGE; |
11300 | ||
11301 | return -1; | |
11302 | } | |
11303 | ||
11304 | static void | |
11305 | handle_large_common (int small ATTRIBUTE_UNUSED) | |
11306 | { | |
11307 | if (flag_code != CODE_64BIT) | |
11308 | { | |
11309 | s_comm_internal (0, elf_common_parse); | |
11310 | as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); | |
11311 | } | |
11312 | else | |
11313 | { | |
11314 | static segT lbss_section; | |
11315 | asection *saved_com_section_ptr = elf_com_section_ptr; | |
11316 | asection *saved_bss_section = bss_section; | |
11317 | ||
11318 | if (lbss_section == NULL) | |
11319 | { | |
11320 | flagword applicable; | |
11321 | segT seg = now_seg; | |
11322 | subsegT subseg = now_subseg; | |
11323 | ||
11324 | /* The .lbss section is for local .largecomm symbols. */ | |
11325 | lbss_section = subseg_new (".lbss", 0); | |
11326 | applicable = bfd_applicable_section_flags (stdoutput); | |
11327 | bfd_set_section_flags (stdoutput, lbss_section, | |
11328 | applicable & SEC_ALLOC); | |
11329 | seg_info (lbss_section)->bss = 1; | |
11330 | ||
11331 | subseg_set (seg, subseg); | |
11332 | } | |
11333 | ||
11334 | elf_com_section_ptr = &_bfd_elf_large_com_section; | |
11335 | bss_section = lbss_section; | |
11336 | ||
11337 | s_comm_internal (0, elf_common_parse); | |
11338 | ||
11339 | elf_com_section_ptr = saved_com_section_ptr; | |
11340 | bss_section = saved_bss_section; | |
11341 | } | |
11342 | } | |
11343 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |