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[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
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b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
6f2750fe 2 Copyright (C) 1989-2016 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d
L		 68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 86#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 87/* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89#define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91#define END_OF_INSN '\0'
92
93/*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100typedef struct
101{
d3ce72d0
NC		 102 const insn_template *start;
103 const insn_template *end;
6305a203
L		 104}
105templates;
106
107/* 386 operand encoding bytes: see 386 book for details of this. */
108typedef struct
109{
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113}
114modrm_byte;
115
116/* x86-64 extension prefix. */
117typedef int rex_byte;
118
6305a203
L		 119/* 386 opcode byte to code indirect addressing. */
120typedef struct
121{
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125}
126sib_byte;
127
6305a203
L		 128/* x86 arch names, types and features */
129typedef struct
130{
131 const char *name; /* arch name */
8a2c8fef 132 unsigned int len; /* arch string length */
6305a203
L		 133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 135 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 136}
137arch_entry;
138
293f5f65
L		 139/* Used to turn off indicated flags. */
140typedef struct
141{
142 const char *name; /* arch name */
143 unsigned int len; /* arch string length */
144 i386_cpu_flags flags; /* cpu feature flags */
145}
146noarch_entry;
147
78f12dd3 148static void update_code_flag (int, int);
e3bb37b5
L		 149static void set_code_flag (int);
150static void set_16bit_gcc_code_flag (int);
151static void set_intel_syntax (int);
1efbbeb4 152static void set_intel_mnemonic (int);
db51cc60 153static void set_allow_index_reg (int);
7bab8ab5 154static void set_check (int);
e3bb37b5 155static void set_cpu_arch (int);
6482c264 156#ifdef TE_PE
e3bb37b5 157static void pe_directive_secrel (int);
6482c264 158#endif
e3bb37b5
L		 159static void signed_cons (int);
160static char *output_invalid (int c);
ee86248c
JB		 161static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
162 const char *);
163static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
164 const char *);
a7619375 165static int i386_att_operand (char *);
e3bb37b5 166static int i386_intel_operand (char *, int);
ee86248c
JB		 167static int i386_intel_simplify (expressionS *);
168static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 169static const reg_entry *parse_register (char *, char **);
170static char *parse_insn (char *, char *);
171static char *parse_operands (char *, const char *);
172static void swap_operands (void);
4d456e3d 173static void swap_2_operands (int, int);
e3bb37b5
L		 174static void optimize_imm (void);
175static void optimize_disp (void);
d3ce72d0 176static const insn_template *match_template (void);
e3bb37b5
L		 177static int check_string (void);
178static int process_suffix (void);
179static int check_byte_reg (void);
180static int check_long_reg (void);
181static int check_qword_reg (void);
182static int check_word_reg (void);
183static int finalize_imm (void);
184static int process_operands (void);
185static const seg_entry *build_modrm_byte (void);
186static void output_insn (void);
187static void output_imm (fragS *, offsetT);
188static void output_disp (fragS *, offsetT);
29b0f896 189#ifndef I386COFF
e3bb37b5 190static void s_bss (int);
252b5132 191#endif
17d4e2a2
L		 192#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193static void handle_large_common (int small ATTRIBUTE_UNUSED);
194#endif
252b5132 195
a847613f 196static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 197
43234a1e
L		 198/* This struct describes rounding control and SAE in the instruction. */
199struct RC_Operation
200{
201 enum rc_type
202 {
203 rne = 0,
204 rd,
205 ru,
206 rz,
207 saeonly
208 } type;
209 int operand;
210};
211
212static struct RC_Operation rc_op;
213
214/* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217struct Mask_Operation
218{
219 const reg_entry *mask;
220 unsigned int zeroing;
221 /* The operand where this operation is associated. */
222 int operand;
223};
224
225static struct Mask_Operation mask_op;
226
227/* The struct describes broadcasting, applied to OPERAND. FACTOR is
228 broadcast factor. */
229struct Broadcast_Operation
230{
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
232 int type;
233
234 /* Index of broadcasted operand. */
235 int operand;
236};
237
238static struct Broadcast_Operation broadcast_op;
239
c0f3af97
L		 240/* VEX prefix. */
241typedef struct
242{
43234a1e
L		 243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes[4];
c0f3af97
L		 245 unsigned int length;
246 /* Destination or source register specifier. */
247 const reg_entry *register_specifier;
248} vex_prefix;
249
252b5132 250/* 'md_assemble ()' gathers together information and puts it into a
47926f60 251 i386_insn. */
252b5132 252
520dc8e8
AM		 253union i386_op
254 {
255 expressionS *disps;
256 expressionS *imms;
257 const reg_entry *regs;
258 };
259
a65babc9
L		 260enum i386_error
261 {
86e026a4 262 operand_size_mismatch,
a65babc9
L		 263 operand_type_mismatch,
264 register_type_mismatch,
265 number_of_operands_mismatch,
266 invalid_instruction_suffix,
267 bad_imm4,
268 old_gcc_only,
269 unsupported_with_intel_mnemonic,
270 unsupported_syntax,
6c30d220
L		 271 unsupported,
272 invalid_vsib_address,
7bab8ab5 273 invalid_vector_register_set,
43234a1e
L		 274 unsupported_vector_index_register,
275 unsupported_broadcast,
276 broadcast_not_on_src_operand,
277 broadcast_needed,
278 unsupported_masking,
279 mask_not_on_destination,
280 no_default_mask,
281 unsupported_rc_sae,
282 rc_sae_operand_not_last_imm,
283 invalid_register_operand,
284 try_vector_disp8
a65babc9
L		 285 };
286
252b5132
RH		 287struct _i386_insn
288 {
47926f60 289 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 290 insn_template tm;
252b5132 291
7d5e4556
L		 292 /* SUFFIX holds the instruction size suffix for byte, word, dword
293 or qword, if given. */
252b5132
RH		 294 char suffix;
295
47926f60 296 /* OPERANDS gives the number of given operands. */
252b5132
RH		 297 unsigned int operands;
298
299 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
300 of given register, displacement, memory operands and immediate
47926f60 301 operands. */
252b5132
RH		 302 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
303
304 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 305 use OP[i] for the corresponding operand. */
40fb9820 306 i386_operand_type types[MAX_OPERANDS];
252b5132 307
520dc8e8
AM		 308 /* Displacement expression, immediate expression, or register for each
309 operand. */
310 union i386_op op[MAX_OPERANDS];
252b5132 311
3e73aa7c
JH		 312 /* Flags for operands. */
313 unsigned int flags[MAX_OPERANDS];
314#define Operand_PCrel 1
315
252b5132 316 /* Relocation type for operand */
f86103b7 317 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 318
252b5132
RH		 319 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
320 the base index byte below. */
321 const reg_entry *base_reg;
322 const reg_entry *index_reg;
323 unsigned int log2_scale_factor;
324
325 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 326 explicit segment overrides are given. */
ce8a8b2f 327 const seg_entry *seg[2];
252b5132
RH		 328
329 /* PREFIX holds all the given prefix opcodes (usually null).
330 PREFIXES is the number of prefix opcodes. */
331 unsigned int prefixes;
332 unsigned char prefix[MAX_PREFIXES];
333
334 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 335 addressing modes of this insn are encoded. */
252b5132 336 modrm_byte rm;
3e73aa7c 337 rex_byte rex;
43234a1e 338 rex_byte vrex;
252b5132 339 sib_byte sib;
c0f3af97 340 vex_prefix vex;
b6169b20 341
43234a1e
L		 342 /* Masking attributes. */
343 struct Mask_Operation *mask;
344
345 /* Rounding control and SAE attributes. */
346 struct RC_Operation *rounding;
347
348 /* Broadcasting attributes. */
349 struct Broadcast_Operation *broadcast;
350
351 /* Compressed disp8*N attribute. */
352 unsigned int memshift;
353
b6169b20 354 /* Swap operand in encoding. */
4473e004 355 unsigned int swap_operand;
891edac4 356
a501d77e
L		 357 /* Prefer 8bit or 32bit displacement in encoding. */
358 enum
359 {
360 disp_encoding_default = 0,
361 disp_encoding_8bit,
362 disp_encoding_32bit
363 } disp_encoding;
f8a5c266 364
d5de92cf
L		 365 /* REP prefix. */
366 const char *rep_prefix;
367
165de32a
L		 368 /* HLE prefix. */
369 const char *hle_prefix;
42164a71 370
7e8b059b
L		 371 /* Have BND prefix. */
372 const char *bnd_prefix;
373
43234a1e
L		 374 /* Need VREX to support upper 16 registers. */
375 int need_vrex;
376
891edac4 377 /* Error message. */
a65babc9 378 enum i386_error error;
252b5132
RH		 379 };
380
381typedef struct _i386_insn i386_insn;
382
43234a1e
L		 383/* Link RC type with corresponding string, that'll be looked for in
384 asm. */
385struct RC_name
386{
387 enum rc_type type;
388 const char *name;
389 unsigned int len;
390};
391
392static const struct RC_name RC_NamesTable[] =
393{
394 { rne, STRING_COMMA_LEN ("rn-sae") },
395 { rd, STRING_COMMA_LEN ("rd-sae") },
396 { ru, STRING_COMMA_LEN ("ru-sae") },
397 { rz, STRING_COMMA_LEN ("rz-sae") },
398 { saeonly, STRING_COMMA_LEN ("sae") },
399};
400
252b5132
RH		 401/* List of chars besides those in app.c:symbol_chars that can start an
402 operand. Used to prevent the scrubber eating vital white-space. */
43234a1e 403const char extra_symbol_chars[] = "*%-([{"
252b5132 404#ifdef LEX_AT
32137342
NC		 405 "@"
406#endif
407#ifdef LEX_QM
408 "?"
252b5132 409#endif
32137342 410 ;
252b5132 411
29b0f896
AM		 412#if (defined (TE_I386AIX) \
413 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 414 && !defined (TE_GNU) \
29b0f896 415 && !defined (TE_LINUX) \
8d63c93e
RM		 416 && !defined (TE_NACL) \
417 && !defined (TE_NETWARE) \
29b0f896 418 && !defined (TE_FreeBSD) \
5b806d27 419 && !defined (TE_DragonFly) \
29b0f896 420 && !defined (TE_NetBSD)))
252b5132 421/* This array holds the chars that always start a comment. If the
b3b91714
AM		 422 pre-processor is disabled, these aren't very useful. The option
423 --divide will remove '/' from this list. */
424const char *i386_comment_chars = "#/";
425#define SVR4_COMMENT_CHARS 1
252b5132 426#define PREFIX_SEPARATOR '\\'
252b5132 427
b3b91714
AM		 428#else
429const char *i386_comment_chars = "#";
430#define PREFIX_SEPARATOR '/'
431#endif
432
252b5132
RH		 433/* This array holds the chars that only start a comment at the beginning of
434 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 435 .line and .file directives will appear in the pre-processed output.
436 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 437 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 438 #NO_APP at the beginning of its output.
439 Also note that comments started like this one will always work if
252b5132 440 '/' isn't otherwise defined. */
b3b91714 441const char line_comment_chars[] = "#/";
252b5132 442
63a0b638 443const char line_separator_chars[] = ";";
252b5132 444
ce8a8b2f
AM		 445/* Chars that can be used to separate mant from exp in floating point
446 nums. */
252b5132
RH		 447const char EXP_CHARS[] = "eE";
448
ce8a8b2f
AM		 449/* Chars that mean this number is a floating point constant
450 As in 0f12.456
451 or 0d1.2345e12. */
252b5132
RH		 452const char FLT_CHARS[] = "fFdDxX";
453
ce8a8b2f 454/* Tables for lexical analysis. */
252b5132
RH		 455static char mnemonic_chars[256];
456static char register_chars[256];
457static char operand_chars[256];
458static char identifier_chars[256];
459static char digit_chars[256];
460
ce8a8b2f 461/* Lexical macros. */
252b5132
RH		 462#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
463#define is_operand_char(x) (operand_chars[(unsigned char) x])
464#define is_register_char(x) (register_chars[(unsigned char) x])
465#define is_space_char(x) ((x) == ' ')
466#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
467#define is_digit_char(x) (digit_chars[(unsigned char) x])
468
0234cb7c 469/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 470static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
471
472/* md_assemble() always leaves the strings it's passed unaltered. To
473 effect this we maintain a stack of saved characters that we've smashed
474 with '\0's (indicating end of strings for various sub-fields of the
47926f60 475 assembler instruction). */
252b5132 476static char save_stack[32];
ce8a8b2f 477static char *save_stack_p;
252b5132
RH		 478#define END_STRING_AND_SAVE(s) \
479 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
480#define RESTORE_END_STRING(s) \
481 do { *(s) = *--save_stack_p; } while (0)
482
47926f60 483/* The instruction we're assembling. */
252b5132
RH		 484static i386_insn i;
485
486/* Possible templates for current insn. */
487static const templates *current_templates;
488
31b2323c
L		 489/* Per instruction expressionS buffers: max displacements & immediates. */
490static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
491static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 492
47926f60 493/* Current operand we are working on. */
ee86248c 494static int this_operand = -1;
252b5132 495
3e73aa7c
JH		 496/* We support four different modes. FLAG_CODE variable is used to distinguish
497 these. */
498
499enum flag_code {
500 CODE_32BIT,
501 CODE_16BIT,
502 CODE_64BIT };
503
504static enum flag_code flag_code;
4fa24527 505static unsigned int object_64bit;
862be3fb 506static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 507static int use_rela_relocations = 0;
508
7af8ed2d
NC		 509#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
510 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
511 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
512
351f65ca
L		 513/* The ELF ABI to use. */
514enum x86_elf_abi
515{
516 I386_ABI,
7f56bc95
L		 517 X86_64_ABI,
518 X86_64_X32_ABI
351f65ca
L		 519};
520
521static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 522#endif
351f65ca 523
167ad85b
TG		 524#if defined (TE_PE) || defined (TE_PEP)
525/* Use big object file format. */
526static int use_big_obj = 0;
527#endif
528
8dcea932
L		 529#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
530/* 1 if generating code for a shared library. */
531static int shared = 0;
532#endif
533
47926f60
KH		 534/* 1 for intel syntax,
535 0 if att syntax. */
536static int intel_syntax = 0;
252b5132 537
e89c5eaa
L		 538/* 1 for Intel64 ISA,
539 0 if AMD64 ISA. */
540static int intel64;
541
1efbbeb4
L		 542/* 1 for intel mnemonic,
543 0 if att mnemonic. */
544static int intel_mnemonic = !SYSV386_COMPAT;
545
5209009a 546/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 547static int old_gcc = OLDGCC_COMPAT;
548
a60de03c
JB		 549/* 1 if pseudo registers are permitted. */
550static int allow_pseudo_reg = 0;
551
47926f60
KH		 552/* 1 if register prefix % not required. */
553static int allow_naked_reg = 0;
252b5132 554
7e8b059b
L		 555/* 1 if the assembler should add BND prefix for all control-tranferring
556 instructions supporting it, even if this prefix wasn't specified
557 explicitly. */
558static int add_bnd_prefix = 0;
559
ba104c83 560/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 561static int allow_index_reg = 0;
562
d022bddd
IT		 563/* 1 if the assembler should ignore LOCK prefix, even if it was
564 specified explicitly. */
565static int omit_lock_prefix = 0;
566
e4e00185
AS		 567/* 1 if the assembler should encode lfence, mfence, and sfence as
568 "lock addl $0, (%{re}sp)". */
569static int avoid_fence = 0;
570
0cb4071e
L		 571/* 1 if the assembler should generate relax relocations. */
572
573static int generate_relax_relocations
574 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
575
7bab8ab5 576static enum check_kind
daf50ae7 577 {
7bab8ab5
JB		 578 check_none = 0,
579 check_warning,
580 check_error
daf50ae7 581 }
7bab8ab5 582sse_check, operand_check = check_warning;
daf50ae7 583
2ca3ace5
L		 584/* Register prefix used for error message. */
585static const char *register_prefix = "%";
586
47926f60
KH		 587/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
588 leave, push, and pop instructions so that gcc has the same stack
589 frame as in 32 bit mode. */
590static char stackop_size = '\0';
eecb386c 591
12b55ccc
L		 592/* Non-zero to optimize code alignment. */
593int optimize_align_code = 1;
594
47926f60
KH		 595/* Non-zero to quieten some warnings. */
596static int quiet_warnings = 0;
a38cf1db 597
47926f60
KH		 598/* CPU name. */
599static const char *cpu_arch_name = NULL;
6305a203 600static char *cpu_sub_arch_name = NULL;
a38cf1db 601
47926f60 602/* CPU feature flags. */
40fb9820
L		 603static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
604
ccc9c027
L		 605/* If we have selected a cpu we are generating instructions for. */
606static int cpu_arch_tune_set = 0;
607
9103f4f4 608/* Cpu we are generating instructions for. */
fbf3f584 609enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 610
611/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 612static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 613
ccc9c027 614/* CPU instruction set architecture used. */
fbf3f584 615enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 616
9103f4f4 617/* CPU feature flags of instruction set architecture used. */
fbf3f584 618i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 619
fddf5b5b
AM		 620/* If set, conditional jumps are not automatically promoted to handle
621 larger than a byte offset. */
622static unsigned int no_cond_jump_promotion = 0;
623
c0f3af97
L		 624/* Encode SSE instructions with VEX prefix. */
625static unsigned int sse2avx;
626
539f890d
L		 627/* Encode scalar AVX instructions with specific vector length. */
628static enum
629 {
630 vex128 = 0,
631 vex256
632 } avxscalar;
633
43234a1e
L		 634/* Encode scalar EVEX LIG instructions with specific vector length. */
635static enum
636 {
637 evexl128 = 0,
638 evexl256,
639 evexl512
640 } evexlig;
641
642/* Encode EVEX WIG instructions with specific evex.w. */
643static enum
644 {
645 evexw0 = 0,
646 evexw1
647 } evexwig;
648
d3d3c6db
IT		 649/* Value to encode in EVEX RC bits, for SAE-only instructions. */
650static enum rc_type evexrcig = rne;
651
29b0f896 652/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 653static symbolS *GOT_symbol;
29b0f896 654
a4447b93
RH		 655/* The dwarf2 return column, adjusted for 32 or 64 bit. */
656unsigned int x86_dwarf2_return_column;
657
658/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
659int x86_cie_data_alignment;
660
252b5132 661/* Interface to relax_segment.
fddf5b5b
AM		 662 There are 3 major relax states for 386 jump insns because the
663 different types of jumps add different sizes to frags when we're
664 figuring out what sort of jump to choose to reach a given label. */
252b5132 665
47926f60 666/* Types. */
93c2a809
AM		 667#define UNCOND_JUMP 0
668#define COND_JUMP 1
669#define COND_JUMP86 2
fddf5b5b 670
47926f60 671/* Sizes. */
252b5132
RH		 672#define CODE16 1
673#define SMALL 0
29b0f896 674#define SMALL16 (SMALL | CODE16)
252b5132 675#define BIG 2
29b0f896 676#define BIG16 (BIG | CODE16)
252b5132
RH		 677
678#ifndef INLINE
679#ifdef __GNUC__
680#define INLINE __inline__
681#else
682#define INLINE
683#endif
684#endif
685
fddf5b5b
AM		 686#define ENCODE_RELAX_STATE(type, size) \
687 ((relax_substateT) (((type) << 2) | (size)))
688#define TYPE_FROM_RELAX_STATE(s) \
689 ((s) >> 2)
690#define DISP_SIZE_FROM_RELAX_STATE(s) \
691 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 692
693/* This table is used by relax_frag to promote short jumps to long
694 ones where necessary. SMALL (short) jumps may be promoted to BIG
695 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
696 don't allow a short jump in a 32 bit code segment to be promoted to
697 a 16 bit offset jump because it's slower (requires data size
698 prefix), and doesn't work, unless the destination is in the bottom
699 64k of the code segment (The top 16 bits of eip are zeroed). */
700
701const relax_typeS md_relax_table[] =
702{
24eab124
AM		 703 /* The fields are:
704 1) most positive reach of this state,
705 2) most negative reach of this state,
93c2a809 706 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 707 4) which index into the table to try if we can't fit into this one. */
252b5132 708
fddf5b5b 709 /* UNCOND_JUMP states. */
93c2a809
AM		 710 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
711 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
712 /* dword jmp adds 4 bytes to frag:
713 0 extra opcode bytes, 4 displacement bytes. */
252b5132 714 {0, 0, 4, 0},
93c2a809
AM		 715 /* word jmp adds 2 byte2 to frag:
716 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 717 {0, 0, 2, 0},
718
93c2a809
AM		 719 /* COND_JUMP states. */
720 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
721 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
722 /* dword conditionals adds 5 bytes to frag:
723 1 extra opcode byte, 4 displacement bytes. */
724 {0, 0, 5, 0},
fddf5b5b 725 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 726 1 extra opcode byte, 2 displacement bytes. */
727 {0, 0, 3, 0},
728
729 /* COND_JUMP86 states. */
730 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
731 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
732 /* dword conditionals adds 5 bytes to frag:
733 1 extra opcode byte, 4 displacement bytes. */
734 {0, 0, 5, 0},
735 /* word conditionals add 4 bytes to frag:
736 1 displacement byte and a 3 byte long branch insn. */
737 {0, 0, 4, 0}
252b5132
RH		 738};
739
9103f4f4
L		 740static const arch_entry cpu_arch[] =
741{
89507696
JB		 742 /* Do not replace the first two entries - i386_target_format()
743 relies on them being there in this order. */
8a2c8fef 744 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
293f5f65 745 CPU_GENERIC32_FLAGS, 0 },
8a2c8fef 746 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
293f5f65 747 CPU_GENERIC64_FLAGS, 0 },
8a2c8fef 748 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
293f5f65 749 CPU_NONE_FLAGS, 0 },
8a2c8fef 750 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
293f5f65 751 CPU_I186_FLAGS, 0 },
8a2c8fef 752 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
293f5f65 753 CPU_I286_FLAGS, 0 },
8a2c8fef 754 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
293f5f65 755 CPU_I386_FLAGS, 0 },
8a2c8fef 756 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
293f5f65 757 CPU_I486_FLAGS, 0 },
8a2c8fef 758 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
293f5f65 759 CPU_I586_FLAGS, 0 },
8a2c8fef 760 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
293f5f65 761 CPU_I686_FLAGS, 0 },
8a2c8fef 762 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
293f5f65 763 CPU_I586_FLAGS, 0 },
8a2c8fef 764 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
293f5f65 765 CPU_PENTIUMPRO_FLAGS, 0 },
8a2c8fef 766 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
293f5f65 767 CPU_P2_FLAGS, 0 },
8a2c8fef 768 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
293f5f65 769 CPU_P3_FLAGS, 0 },
8a2c8fef 770 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
293f5f65 771 CPU_P4_FLAGS, 0 },
8a2c8fef 772 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
293f5f65 773 CPU_CORE_FLAGS, 0 },
8a2c8fef 774 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
293f5f65 775 CPU_NOCONA_FLAGS, 0 },
8a2c8fef 776 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
293f5f65 777 CPU_CORE_FLAGS, 1 },
8a2c8fef 778 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
293f5f65 779 CPU_CORE_FLAGS, 0 },
8a2c8fef 780 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
293f5f65 781 CPU_CORE2_FLAGS, 1 },
8a2c8fef 782 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
293f5f65 783 CPU_CORE2_FLAGS, 0 },
8a2c8fef 784 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
293f5f65 785 CPU_COREI7_FLAGS, 0 },
8a2c8fef 786 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
293f5f65 787 CPU_L1OM_FLAGS, 0 },
7a9068fe 788 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
293f5f65 789 CPU_K1OM_FLAGS, 0 },
81486035 790 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
293f5f65 791 CPU_IAMCU_FLAGS, 0 },
8a2c8fef 792 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
293f5f65 793 CPU_K6_FLAGS, 0 },
8a2c8fef 794 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
293f5f65 795 CPU_K6_2_FLAGS, 0 },
8a2c8fef 796 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
293f5f65 797 CPU_ATHLON_FLAGS, 0 },
8a2c8fef 798 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
293f5f65 799 CPU_K8_FLAGS, 1 },
8a2c8fef 800 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
293f5f65 801 CPU_K8_FLAGS, 0 },
8a2c8fef 802 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
293f5f65 803 CPU_K8_FLAGS, 0 },
8a2c8fef 804 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
293f5f65 805 CPU_AMDFAM10_FLAGS, 0 },
8aedb9fe 806 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
293f5f65 807 CPU_BDVER1_FLAGS, 0 },
8aedb9fe 808 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
293f5f65 809 CPU_BDVER2_FLAGS, 0 },
5e5c50d3 810 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
293f5f65 811 CPU_BDVER3_FLAGS, 0 },
c7b0bd56 812 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
293f5f65 813 CPU_BDVER4_FLAGS, 0 },
029f3522 814 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
293f5f65 815 CPU_ZNVER1_FLAGS, 0 },
7b458c12 816 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
293f5f65 817 CPU_BTVER1_FLAGS, 0 },
7b458c12 818 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
293f5f65 819 CPU_BTVER2_FLAGS, 0 },
8a2c8fef 820 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
293f5f65 821 CPU_8087_FLAGS, 0 },
8a2c8fef 822 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
293f5f65 823 CPU_287_FLAGS, 0 },
8a2c8fef 824 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
293f5f65 825 CPU_387_FLAGS, 0 },
8a2c8fef 826 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
293f5f65 827 CPU_MMX_FLAGS, 0 },
8a2c8fef 828 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
293f5f65 829 CPU_SSE_FLAGS, 0 },
8a2c8fef 830 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
293f5f65 831 CPU_SSE2_FLAGS, 0 },
8a2c8fef 832 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
293f5f65 833 CPU_SSE3_FLAGS, 0 },
8a2c8fef 834 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
293f5f65 835 CPU_SSSE3_FLAGS, 0 },
8a2c8fef 836 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
293f5f65 837 CPU_SSE4_1_FLAGS, 0 },
8a2c8fef 838 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
293f5f65 839 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 840 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
293f5f65 841 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 842 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
293f5f65 843 CPU_AVX_FLAGS, 0 },
6c30d220 844 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
293f5f65 845 CPU_AVX2_FLAGS, 0 },
43234a1e 846 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
293f5f65 847 CPU_AVX512F_FLAGS, 0 },
43234a1e 848 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
293f5f65 849 CPU_AVX512CD_FLAGS, 0 },
43234a1e 850 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
293f5f65 851 CPU_AVX512ER_FLAGS, 0 },
43234a1e 852 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
293f5f65 853 CPU_AVX512PF_FLAGS, 0 },
1dfc6506 854 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
293f5f65 855 CPU_AVX512DQ_FLAGS, 0 },
1dfc6506 856 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
293f5f65 857 CPU_AVX512BW_FLAGS, 0 },
1dfc6506 858 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
293f5f65 859 CPU_AVX512VL_FLAGS, 0 },
8a2c8fef 860 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
293f5f65 861 CPU_VMX_FLAGS, 0 },
8729a6f6 862 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
293f5f65 863 CPU_VMFUNC_FLAGS, 0 },
8a2c8fef 864 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
293f5f65 865 CPU_SMX_FLAGS, 0 },
8a2c8fef 866 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
293f5f65 867 CPU_XSAVE_FLAGS, 0 },
c7b8aa3a 868 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
293f5f65 869 CPU_XSAVEOPT_FLAGS, 0 },
1dfc6506 870 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
293f5f65 871 CPU_XSAVEC_FLAGS, 0 },
1dfc6506 872 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
293f5f65 873 CPU_XSAVES_FLAGS, 0 },
8a2c8fef 874 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
293f5f65 875 CPU_AES_FLAGS, 0 },
8a2c8fef 876 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
293f5f65 877 CPU_PCLMUL_FLAGS, 0 },
8a2c8fef 878 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
293f5f65 879 CPU_PCLMUL_FLAGS, 1 },
c7b8aa3a 880 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
293f5f65 881 CPU_FSGSBASE_FLAGS, 0 },
c7b8aa3a 882 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
293f5f65 883 CPU_RDRND_FLAGS, 0 },
c7b8aa3a 884 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
293f5f65 885 CPU_F16C_FLAGS, 0 },
6c30d220 886 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
293f5f65 887 CPU_BMI2_FLAGS, 0 },
8a2c8fef 888 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
293f5f65 889 CPU_FMA_FLAGS, 0 },
8a2c8fef 890 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
293f5f65 891 CPU_FMA4_FLAGS, 0 },
8a2c8fef 892 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
293f5f65 893 CPU_XOP_FLAGS, 0 },
8a2c8fef 894 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
293f5f65 895 CPU_LWP_FLAGS, 0 },
8a2c8fef 896 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
293f5f65 897 CPU_MOVBE_FLAGS, 0 },
60aa667e 898 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
293f5f65 899 CPU_CX16_FLAGS, 0 },
8a2c8fef 900 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
293f5f65 901 CPU_EPT_FLAGS, 0 },
6c30d220 902 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
293f5f65 903 CPU_LZCNT_FLAGS, 0 },
42164a71 904 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
293f5f65 905 CPU_HLE_FLAGS, 0 },
42164a71 906 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
293f5f65 907 CPU_RTM_FLAGS, 0 },
6c30d220 908 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
293f5f65 909 CPU_INVPCID_FLAGS, 0 },
8a2c8fef 910 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
293f5f65 911 CPU_CLFLUSH_FLAGS, 0 },
22109423 912 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
293f5f65 913 CPU_NOP_FLAGS, 0 },
8a2c8fef 914 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
293f5f65 915 CPU_SYSCALL_FLAGS, 0 },
8a2c8fef 916 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
293f5f65 917 CPU_RDTSCP_FLAGS, 0 },
8a2c8fef 918 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
293f5f65 919 CPU_3DNOW_FLAGS, 0 },
8a2c8fef 920 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
293f5f65 921 CPU_3DNOWA_FLAGS, 0 },
8a2c8fef 922 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
293f5f65 923 CPU_PADLOCK_FLAGS, 0 },
8a2c8fef 924 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
293f5f65 925 CPU_SVME_FLAGS, 1 },
8a2c8fef 926 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
293f5f65 927 CPU_SVME_FLAGS, 0 },
8a2c8fef 928 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
293f5f65 929 CPU_SSE4A_FLAGS, 0 },
8a2c8fef 930 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
293f5f65 931 CPU_ABM_FLAGS, 0 },
87973e9f 932 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
293f5f65 933 CPU_BMI_FLAGS, 0 },
2a2a0f38 934 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
293f5f65 935 CPU_TBM_FLAGS, 0 },
e2e1fcde 936 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
293f5f65 937 CPU_ADX_FLAGS, 0 },
e2e1fcde 938 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
293f5f65 939 CPU_RDSEED_FLAGS, 0 },
e2e1fcde 940 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
293f5f65 941 CPU_PRFCHW_FLAGS, 0 },
5c111e37 942 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
293f5f65 943 CPU_SMAP_FLAGS, 0 },
7e8b059b 944 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
293f5f65 945 CPU_MPX_FLAGS, 0 },
a0046408 946 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
293f5f65 947 CPU_SHA_FLAGS, 0 },
963f3586 948 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
293f5f65 949 CPU_CLFLUSHOPT_FLAGS, 0 },
dcf893b5 950 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
293f5f65 951 CPU_PREFETCHWT1_FLAGS, 0 },
2cf200a4 952 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
293f5f65 953 CPU_SE1_FLAGS, 0 },
c5e7287a 954 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
293f5f65 955 CPU_CLWB_FLAGS, 0 },
9d8596f0 956 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN,
293f5f65 957 CPU_PCOMMIT_FLAGS, 0 },
2cc1b5aa 958 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
293f5f65 959 CPU_AVX512IFMA_FLAGS, 0 },
14f195c9 960 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
293f5f65 961 CPU_AVX512VBMI_FLAGS, 0 },
029f3522 962 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
293f5f65 963 CPU_CLZERO_FLAGS, 0 },
9916071f 964 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
293f5f65 965 CPU_MWAITX_FLAGS, 0 },
8eab4136 966 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
293f5f65 967 CPU_OSPKE_FLAGS, 0 },
8bc52696 968 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
293f5f65
L		 969 CPU_RDPID_FLAGS, 0 },
970};
971
972static const noarch_entry cpu_noarch[] =
973{
974 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
975 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
976 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
977 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
e413e4e9
AM		 978};
979
704209c0 980#ifdef I386COFF
a6c24e68
NC		 981/* Like s_lcomm_internal in gas/read.c but the alignment string
982 is allowed to be optional. */
983
984static symbolS *
985pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
986{
987 addressT align = 0;
988
989 SKIP_WHITESPACE ();
990
7ab9ffdd 991 if (needs_align
a6c24e68
NC		 992 && *input_line_pointer == ',')
993 {
994 align = parse_align (needs_align - 1);
7ab9ffdd 995
a6c24e68
NC		 996 if (align == (addressT) -1)
997 return NULL;
998 }
999 else
1000 {
1001 if (size >= 8)
1002 align = 3;
1003 else if (size >= 4)
1004 align = 2;
1005 else if (size >= 2)
1006 align = 1;
1007 else
1008 align = 0;
1009 }
1010
1011 bss_alloc (symbolP, size, align);
1012 return symbolP;
1013}
1014
704209c0 1015static void
a6c24e68
NC		 1016pe_lcomm (int needs_align)
1017{
1018 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1019}
704209c0 1020#endif
a6c24e68 1021
29b0f896
AM		 1022const pseudo_typeS md_pseudo_table[] =
1023{
1024#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1025 {"align", s_align_bytes, 0},
1026#else
1027 {"align", s_align_ptwo, 0},
1028#endif
1029 {"arch", set_cpu_arch, 0},
1030#ifndef I386COFF
1031 {"bss", s_bss, 0},
a6c24e68
NC		 1032#else
1033 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1034#endif
1035 {"ffloat", float_cons, 'f'},
1036 {"dfloat", float_cons, 'd'},
1037 {"tfloat", float_cons, 'x'},
1038 {"value", cons, 2},
d182319b 1039 {"slong", signed_cons, 4},
29b0f896
AM		 1040 {"noopt", s_ignore, 0},
1041 {"optim", s_ignore, 0},
1042 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1043 {"code16", set_code_flag, CODE_16BIT},
1044 {"code32", set_code_flag, CODE_32BIT},
1045 {"code64", set_code_flag, CODE_64BIT},
1046 {"intel_syntax", set_intel_syntax, 1},
1047 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1048 {"intel_mnemonic", set_intel_mnemonic, 1},
1049 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1050 {"allow_index_reg", set_allow_index_reg, 1},
1051 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1052 {"sse_check", set_check, 0},
1053 {"operand_check", set_check, 1},
3b22753a
L		 1054#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1055 {"largecomm", handle_large_common, 0},
07a53e5c 1056#else
e3bb37b5 1057 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 1058 {"loc", dwarf2_directive_loc, 0},
1059 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1060#endif
6482c264
NC		 1061#ifdef TE_PE
1062 {"secrel32", pe_directive_secrel, 0},
1063#endif
29b0f896
AM		 1064 {0, 0, 0}
1065};
1066
1067/* For interface with expression (). */
1068extern char *input_line_pointer;
1069
1070/* Hash table for instruction mnemonic lookup. */
1071static struct hash_control *op_hash;
1072
1073/* Hash table for register lookup. */
1074static struct hash_control *reg_hash;
1075\f
252b5132 1076void
e3bb37b5 1077i386_align_code (fragS *fragP, int count)
252b5132 1078{
ce8a8b2f
AM		 1079 /* Various efficient no-op patterns for aligning code labels.
1080 Note: Don't try to assemble the instructions in the comments.
1081 0L and 0w are not legal. */
bad6e36d 1082 static const unsigned char f32_1[] =
252b5132 1083 {0x90}; /* nop */
bad6e36d 1084 static const unsigned char f32_2[] =
ccc9c027 1085 {0x66,0x90}; /* xchg %ax,%ax */
bad6e36d 1086 static const unsigned char f32_3[] =
252b5132 1087 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
bad6e36d 1088 static const unsigned char f32_4[] =
252b5132 1089 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
bad6e36d 1090 static const unsigned char f32_5[] =
252b5132
RH		 1091 {0x90, /* nop */
1092 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
bad6e36d 1093 static const unsigned char f32_6[] =
252b5132 1094 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
bad6e36d 1095 static const unsigned char f32_7[] =
252b5132 1096 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
bad6e36d 1097 static const unsigned char f32_8[] =
252b5132
RH		 1098 {0x90, /* nop */
1099 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
bad6e36d 1100 static const unsigned char f32_9[] =
252b5132
RH		 1101 {0x89,0xf6, /* movl %esi,%esi */
1102 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1103 static const unsigned char f32_10[] =
252b5132
RH		 1104 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1105 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1106 static const unsigned char f32_11[] =
252b5132
RH		 1107 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1108 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1109 static const unsigned char f32_12[] =
252b5132
RH		 1110 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1111 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
bad6e36d 1112 static const unsigned char f32_13[] =
252b5132
RH		 1113 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1114 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1115 static const unsigned char f32_14[] =
252b5132
RH		 1116 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1117 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1118 static const unsigned char f16_3[] =
c3332e24 1119 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
bad6e36d 1120 static const unsigned char f16_4[] =
252b5132 1121 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
bad6e36d 1122 static const unsigned char f16_5[] =
252b5132
RH		 1123 {0x90, /* nop */
1124 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
bad6e36d 1125 static const unsigned char f16_6[] =
252b5132
RH		 1126 {0x89,0xf6, /* mov %si,%si */
1127 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1128 static const unsigned char f16_7[] =
252b5132
RH		 1129 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1130 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1131 static const unsigned char f16_8[] =
252b5132
RH		 1132 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1133 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1134 static const unsigned char jump_31[] =
76bc74dc
L		 1135 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1136 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1137 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1138 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
bad6e36d 1139 static const unsigned char *const f32_patt[] = {
252b5132 1140 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1141 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132 1142 };
bad6e36d 1143 static const unsigned char *const f16_patt[] = {
76bc74dc 1144 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1145 };
ccc9c027 1146 /* nopl (%[re]ax) */
bad6e36d 1147 static const unsigned char alt_3[] =
ccc9c027
L		 1148 {0x0f,0x1f,0x00};
1149 /* nopl 0(%[re]ax) */
bad6e36d 1150 static const unsigned char alt_4[] =
ccc9c027
L		 1151 {0x0f,0x1f,0x40,0x00};
1152 /* nopl 0(%[re]ax,%[re]ax,1) */
bad6e36d 1153 static const unsigned char alt_5[] =
ccc9c027
L		 1154 {0x0f,0x1f,0x44,0x00,0x00};
1155 /* nopw 0(%[re]ax,%[re]ax,1) */
bad6e36d 1156 static const unsigned char alt_6[] =
ccc9c027
L		 1157 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1158 /* nopl 0L(%[re]ax) */
bad6e36d 1159 static const unsigned char alt_7[] =
ccc9c027
L		 1160 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1161 /* nopl 0L(%[re]ax,%[re]ax,1) */
bad6e36d 1162 static const unsigned char alt_8[] =
ccc9c027
L		 1163 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1164 /* nopw 0L(%[re]ax,%[re]ax,1) */
bad6e36d 1165 static const unsigned char alt_9[] =
ccc9c027
L		 1166 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1167 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
bad6e36d 1168 static const unsigned char alt_10[] =
ccc9c027 1169 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
bad6e36d 1170 static const unsigned char *const alt_patt[] = {
ccc9c027 1171 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
80b8656c 1172 alt_9, alt_10
ccc9c027 1173 };
252b5132 1174
76bc74dc
L		 1175 /* Only align for at least a positive non-zero boundary. */
1176 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1177 return;
3e73aa7c 1178
ccc9c027
L		 1179 /* We need to decide which NOP sequence to use for 32bit and
1180 64bit. When -mtune= is used:
4eed87de 1181
76bc74dc
L		 1182 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1183 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1184 2. For the rest, alt_patt will be used.
1185
1186 When -mtune= isn't used, alt_patt will be used if
22109423 1187 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1188 be used.
ccc9c027
L		 1189
1190 When -march= or .arch is used, we can't use anything beyond
1191 cpu_arch_isa_flags. */
1192
1193 if (flag_code == CODE_16BIT)
1194 {
ccc9c027 1195 if (count > 8)
33fef721 1196 {
76bc74dc
L		 1197 memcpy (fragP->fr_literal + fragP->fr_fix,
1198 jump_31, count);
1199 /* Adjust jump offset. */
1200 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1201 }
76bc74dc
L		 1202 else
1203 memcpy (fragP->fr_literal + fragP->fr_fix,
1204 f16_patt[count - 1], count);
252b5132 1205 }
33fef721 1206 else
ccc9c027 1207 {
bad6e36d 1208 const unsigned char *const *patt = NULL;
ccc9c027 1209
fbf3f584 1210 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1211 {
1212 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1213 switch (cpu_arch_tune)
1214 {
1215 case PROCESSOR_UNKNOWN:
1216 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1217 optimize with nops. */
1218 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1219 patt = alt_patt;
ccc9c027
L		 1220 else
1221 patt = f32_patt;
1222 break;
ccc9c027
L		 1223 case PROCESSOR_PENTIUM4:
1224 case PROCESSOR_NOCONA:
ef05d495 1225 case PROCESSOR_CORE:
76bc74dc 1226 case PROCESSOR_CORE2:
bd5295b2 1227 case PROCESSOR_COREI7:
3632d14b 1228 case PROCESSOR_L1OM:
7a9068fe 1229 case PROCESSOR_K1OM:
76bc74dc 1230 case PROCESSOR_GENERIC64:
ccc9c027
L		 1231 case PROCESSOR_K6:
1232 case PROCESSOR_ATHLON:
1233 case PROCESSOR_K8:
4eed87de 1234 case PROCESSOR_AMDFAM10:
8aedb9fe 1235 case PROCESSOR_BD:
029f3522 1236 case PROCESSOR_ZNVER:
7b458c12 1237 case PROCESSOR_BT:
80b8656c 1238 patt = alt_patt;
ccc9c027 1239 break;
76bc74dc 1240 case PROCESSOR_I386:
ccc9c027
L		 1241 case PROCESSOR_I486:
1242 case PROCESSOR_PENTIUM:
2dde1948 1243 case PROCESSOR_PENTIUMPRO:
81486035 1244 case PROCESSOR_IAMCU:
ccc9c027
L		 1245 case PROCESSOR_GENERIC32:
1246 patt = f32_patt;
1247 break;
4eed87de 1248 }
ccc9c027
L		 1249 }
1250 else
1251 {
fbf3f584 1252 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1253 {
1254 case PROCESSOR_UNKNOWN:
e6a14101 1255 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1256 PROCESSOR_UNKNOWN. */
1257 abort ();
1258 break;
1259
76bc74dc 1260 case PROCESSOR_I386:
ccc9c027
L		 1261 case PROCESSOR_I486:
1262 case PROCESSOR_PENTIUM:
81486035 1263 case PROCESSOR_IAMCU:
ccc9c027
L		 1264 case PROCESSOR_K6:
1265 case PROCESSOR_ATHLON:
1266 case PROCESSOR_K8:
4eed87de 1267 case PROCESSOR_AMDFAM10:
8aedb9fe 1268 case PROCESSOR_BD:
029f3522 1269 case PROCESSOR_ZNVER:
7b458c12 1270 case PROCESSOR_BT:
ccc9c027
L		 1271 case PROCESSOR_GENERIC32:
1272 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1273 with nops. */
1274 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1275 patt = alt_patt;
ccc9c027
L		 1276 else
1277 patt = f32_patt;
1278 break;
76bc74dc
L		 1279 case PROCESSOR_PENTIUMPRO:
1280 case PROCESSOR_PENTIUM4:
1281 case PROCESSOR_NOCONA:
1282 case PROCESSOR_CORE:
ef05d495 1283 case PROCESSOR_CORE2:
bd5295b2 1284 case PROCESSOR_COREI7:
3632d14b 1285 case PROCESSOR_L1OM:
7a9068fe 1286 case PROCESSOR_K1OM:
22109423 1287 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1288 patt = alt_patt;
ccc9c027
L		 1289 else
1290 patt = f32_patt;
1291 break;
1292 case PROCESSOR_GENERIC64:
80b8656c 1293 patt = alt_patt;
ccc9c027 1294 break;
4eed87de 1295 }
ccc9c027
L		 1296 }
1297
76bc74dc
L		 1298 if (patt == f32_patt)
1299 {
1300 /* If the padding is less than 15 bytes, we use the normal
1301 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1302 its offset. */
1303 int limit;
76ba9986 1304
711eedef
L		 1305 /* For 64bit, the limit is 3 bytes. */
1306 if (flag_code == CODE_64BIT
1307 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1308 limit = 3;
1309 else
1310 limit = 15;
1311 if (count < limit)
76bc74dc
L		 1312 memcpy (fragP->fr_literal + fragP->fr_fix,
1313 patt[count - 1], count);
1314 else
1315 {
1316 memcpy (fragP->fr_literal + fragP->fr_fix,
1317 jump_31, count);
1318 /* Adjust jump offset. */
1319 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1320 }
1321 }
1322 else
1323 {
80b8656c
L		 1324 /* Maximum length of an instruction is 10 byte. If the
1325 padding is greater than 10 bytes and we don't use jump,
76bc74dc
L		 1326 we have to break it into smaller pieces. */
1327 int padding = count;
80b8656c 1328 while (padding > 10)
76bc74dc 1329 {
80b8656c 1330 padding -= 10;
76bc74dc 1331 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
80b8656c 1332 patt [9], 10);
76bc74dc
L		 1333 }
1334
1335 if (padding)
1336 memcpy (fragP->fr_literal + fragP->fr_fix,
1337 patt [padding - 1], padding);
1338 }
ccc9c027 1339 }
33fef721 1340 fragP->fr_var = count;
252b5132
RH		 1341}
1342
c6fb90c8 1343static INLINE int
0dfbf9d7 1344operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1345{
0dfbf9d7 1346 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1347 {
1348 case 3:
0dfbf9d7 1349 if (x->array[2])
c6fb90c8
L		 1350 return 0;
1351 case 2:
0dfbf9d7 1352 if (x->array[1])
c6fb90c8
L		 1353 return 0;
1354 case 1:
0dfbf9d7 1355 return !x->array[0];
c6fb90c8
L		 1356 default:
1357 abort ();
1358 }
40fb9820
L		 1359}
1360
c6fb90c8 1361static INLINE void
0dfbf9d7 1362operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1363{
0dfbf9d7 1364 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1365 {
1366 case 3:
0dfbf9d7 1367 x->array[2] = v;
c6fb90c8 1368 case 2:
0dfbf9d7 1369 x->array[1] = v;
c6fb90c8 1370 case 1:
0dfbf9d7 1371 x->array[0] = v;
c6fb90c8
L		 1372 break;
1373 default:
1374 abort ();
1375 }
1376}
40fb9820 1377
c6fb90c8 1378static INLINE int
0dfbf9d7
L		 1379operand_type_equal (const union i386_operand_type *x,
1380 const union i386_operand_type *y)
c6fb90c8 1381{
0dfbf9d7 1382 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1383 {
1384 case 3:
0dfbf9d7 1385 if (x->array[2] != y->array[2])
c6fb90c8
L		 1386 return 0;
1387 case 2:
0dfbf9d7 1388 if (x->array[1] != y->array[1])
c6fb90c8
L		 1389 return 0;
1390 case 1:
0dfbf9d7 1391 return x->array[0] == y->array[0];
c6fb90c8
L		 1392 break;
1393 default:
1394 abort ();
1395 }
1396}
40fb9820 1397
0dfbf9d7
L		 1398static INLINE int
1399cpu_flags_all_zero (const union i386_cpu_flags *x)
1400{
1401 switch (ARRAY_SIZE(x->array))
1402 {
1403 case 3:
1404 if (x->array[2])
1405 return 0;
1406 case 2:
1407 if (x->array[1])
1408 return 0;
1409 case 1:
1410 return !x->array[0];
1411 default:
1412 abort ();
1413 }
1414}
1415
0dfbf9d7
L		 1416static INLINE int
1417cpu_flags_equal (const union i386_cpu_flags *x,
1418 const union i386_cpu_flags *y)
1419{
1420 switch (ARRAY_SIZE(x->array))
1421 {
1422 case 3:
1423 if (x->array[2] != y->array[2])
1424 return 0;
1425 case 2:
1426 if (x->array[1] != y->array[1])
1427 return 0;
1428 case 1:
1429 return x->array[0] == y->array[0];
1430 break;
1431 default:
1432 abort ();
1433 }
1434}
c6fb90c8
L		 1435
1436static INLINE int
1437cpu_flags_check_cpu64 (i386_cpu_flags f)
1438{
1439 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1440 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1441}
1442
c6fb90c8
L		 1443static INLINE i386_cpu_flags
1444cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1445{
c6fb90c8
L		 1446 switch (ARRAY_SIZE (x.array))
1447 {
1448 case 3:
1449 x.array [2] &= y.array [2];
1450 case 2:
1451 x.array [1] &= y.array [1];
1452 case 1:
1453 x.array [0] &= y.array [0];
1454 break;
1455 default:
1456 abort ();
1457 }
1458 return x;
1459}
40fb9820 1460
c6fb90c8
L		 1461static INLINE i386_cpu_flags
1462cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1463{
c6fb90c8 1464 switch (ARRAY_SIZE (x.array))
40fb9820 1465 {
c6fb90c8
L		 1466 case 3:
1467 x.array [2] |= y.array [2];
1468 case 2:
1469 x.array [1] |= y.array [1];
1470 case 1:
1471 x.array [0] |= y.array [0];
40fb9820
L		 1472 break;
1473 default:
1474 abort ();
1475 }
40fb9820
L		 1476 return x;
1477}
1478
309d3373
JB		 1479static INLINE i386_cpu_flags
1480cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1481{
1482 switch (ARRAY_SIZE (x.array))
1483 {
1484 case 3:
1485 x.array [2] &= ~y.array [2];
1486 case 2:
1487 x.array [1] &= ~y.array [1];
1488 case 1:
1489 x.array [0] &= ~y.array [0];
1490 break;
1491 default:
1492 abort ();
1493 }
1494 return x;
1495}
1496
81486035
L		 1497static int
1498valid_iamcu_cpu_flags (const i386_cpu_flags *flags)
1499{
1500 if (cpu_arch_isa == PROCESSOR_IAMCU)
1501 {
1502 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_COMPAT_FLAGS;
1503 i386_cpu_flags compat_flags;
1504 compat_flags = cpu_flags_and_not (*flags, iamcu_flags);
1505 return cpu_flags_all_zero (&compat_flags);
1506 }
1507 else
1508 return 1;
1509}
1510
c0f3af97
L		 1511#define CPU_FLAGS_ARCH_MATCH 0x1
1512#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1513#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1514#define CPU_FLAGS_PCLMUL_MATCH 0x8
1515#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1516
a5ff0eb2 1517#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1518 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1519 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1520#define CPU_FLAGS_PERFECT_MATCH \
1521 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1522
1523/* Return CPU flags match bits. */
3629bb00 1524
40fb9820 1525static int
d3ce72d0 1526cpu_flags_match (const insn_template *t)
40fb9820 1527{
c0f3af97
L		 1528 i386_cpu_flags x = t->cpu_flags;
1529 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1530
1531 x.bitfield.cpu64 = 0;
1532 x.bitfield.cpuno64 = 0;
1533
0dfbf9d7 1534 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1535 {
1536 /* This instruction is available on all archs. */
1537 match |= CPU_FLAGS_32BIT_MATCH;
1538 }
3629bb00
L		 1539 else
1540 {
c0f3af97 1541 /* This instruction is available only on some archs. */
3629bb00
L		 1542 i386_cpu_flags cpu = cpu_arch_flags;
1543
3629bb00 1544 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1545 if (!cpu_flags_all_zero (&cpu))
1546 {
a5ff0eb2
L		 1547 if (x.bitfield.cpuavx)
1548 {
ce2f5b3c 1549 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1550 if (cpu.bitfield.cpuavx)
1551 {
1552 /* Check SSE2AVX. */
1553 if (!t->opcode_modifier.sse2avx|| sse2avx)
1554 {
1555 match |= (CPU_FLAGS_ARCH_MATCH
1556 | CPU_FLAGS_AVX_MATCH);
1557 /* Check AES. */
1558 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1559 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1560 /* Check PCLMUL. */
1561 if (!x.bitfield.cpupclmul
1562 || cpu.bitfield.cpupclmul)
1563 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1564 }
1565 }
1566 else
1567 match |= CPU_FLAGS_ARCH_MATCH;
1568 }
73b090a9
L		 1569 else if (x.bitfield.cpuavx512vl)
1570 {
1571 /* Match AVX512VL. */
1572 if (cpu.bitfield.cpuavx512vl)
1573 {
1574 /* Need another match. */
1575 cpu.bitfield.cpuavx512vl = 0;
1576 if (!cpu_flags_all_zero (&cpu))
1577 match |= CPU_FLAGS_32BIT_MATCH;
1578 else
1579 match |= CPU_FLAGS_ARCH_MATCH;
1580 }
1581 else
1582 match |= CPU_FLAGS_ARCH_MATCH;
1583 }
a5ff0eb2 1584 else
c0f3af97
L		 1585 match |= CPU_FLAGS_32BIT_MATCH;
1586 }
3629bb00 1587 }
c0f3af97 1588 return match;
40fb9820
L		 1589}
1590
c6fb90c8
L		 1591static INLINE i386_operand_type
1592operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1593{
c6fb90c8
L		 1594 switch (ARRAY_SIZE (x.array))
1595 {
1596 case 3:
1597 x.array [2] &= y.array [2];
1598 case 2:
1599 x.array [1] &= y.array [1];
1600 case 1:
1601 x.array [0] &= y.array [0];
1602 break;
1603 default:
1604 abort ();
1605 }
1606 return x;
40fb9820
L		 1607}
1608
c6fb90c8
L		 1609static INLINE i386_operand_type
1610operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1611{
c6fb90c8 1612 switch (ARRAY_SIZE (x.array))
40fb9820 1613 {
c6fb90c8
L		 1614 case 3:
1615 x.array [2] |= y.array [2];
1616 case 2:
1617 x.array [1] |= y.array [1];
1618 case 1:
1619 x.array [0] |= y.array [0];
40fb9820
L		 1620 break;
1621 default:
1622 abort ();
1623 }
c6fb90c8
L		 1624 return x;
1625}
40fb9820 1626
c6fb90c8
L		 1627static INLINE i386_operand_type
1628operand_type_xor (i386_operand_type x, i386_operand_type y)
1629{
1630 switch (ARRAY_SIZE (x.array))
1631 {
1632 case 3:
1633 x.array [2] ^= y.array [2];
1634 case 2:
1635 x.array [1] ^= y.array [1];
1636 case 1:
1637 x.array [0] ^= y.array [0];
1638 break;
1639 default:
1640 abort ();
1641 }
40fb9820
L		 1642 return x;
1643}
1644
1645static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1646static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1647static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1648static const i386_operand_type inoutportreg
1649 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1650static const i386_operand_type reg16_inoutportreg
1651 = OPERAND_TYPE_REG16_INOUTPORTREG;
1652static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1653static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1654static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1655static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1656static const i386_operand_type anydisp
1657 = OPERAND_TYPE_ANYDISP;
40fb9820 1658static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1659static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1660static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1661static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1662static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1663static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1664static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1665static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1666static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1667static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1668static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1669static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1670static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1671static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1672
1673enum operand_type
1674{
1675 reg,
40fb9820
L		 1676 imm,
1677 disp,
1678 anymem
1679};
1680
c6fb90c8 1681static INLINE int
40fb9820
L		 1682operand_type_check (i386_operand_type t, enum operand_type c)
1683{
1684 switch (c)
1685 {
1686 case reg:
1687 return (t.bitfield.reg8
1688 || t.bitfield.reg16
1689 || t.bitfield.reg32
1690 || t.bitfield.reg64);
1691
40fb9820
L		 1692 case imm:
1693 return (t.bitfield.imm8
1694 || t.bitfield.imm8s
1695 || t.bitfield.imm16
1696 || t.bitfield.imm32
1697 || t.bitfield.imm32s
1698 || t.bitfield.imm64);
1699
1700 case disp:
1701 return (t.bitfield.disp8
1702 || t.bitfield.disp16
1703 || t.bitfield.disp32
1704 || t.bitfield.disp32s
1705 || t.bitfield.disp64);
1706
1707 case anymem:
1708 return (t.bitfield.disp8
1709 || t.bitfield.disp16
1710 || t.bitfield.disp32
1711 || t.bitfield.disp32s
1712 || t.bitfield.disp64
1713 || t.bitfield.baseindex);
1714
1715 default:
1716 abort ();
1717 }
2cfe26b6
AM		 1718
1719 return 0;
40fb9820
L		 1720}
1721
5c07affc
L		 1722/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1723 operand J for instruction template T. */
1724
1725static INLINE int
d3ce72d0 1726match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1727{
1728 return !((i.types[j].bitfield.byte
1729 && !t->operand_types[j].bitfield.byte)
1730 || (i.types[j].bitfield.word
1731 && !t->operand_types[j].bitfield.word)
1732 || (i.types[j].bitfield.dword
1733 && !t->operand_types[j].bitfield.dword)
1734 || (i.types[j].bitfield.qword
1735 && !t->operand_types[j].bitfield.qword));
1736}
1737
1738/* Return 1 if there is no conflict in any size on operand J for
1739 instruction template T. */
1740
1741static INLINE int
d3ce72d0 1742match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1743{
1744 return (match_reg_size (t, j)
1745 && !((i.types[j].bitfield.unspecified
af508cb9 1746 && !i.broadcast
5c07affc
L		 1747 && !t->operand_types[j].bitfield.unspecified)
1748 || (i.types[j].bitfield.fword
1749 && !t->operand_types[j].bitfield.fword)
1750 || (i.types[j].bitfield.tbyte
1751 && !t->operand_types[j].bitfield.tbyte)
1752 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1753 && !t->operand_types[j].bitfield.xmmword)
1754 || (i.types[j].bitfield.ymmword
43234a1e
L		 1755 && !t->operand_types[j].bitfield.ymmword)
1756 || (i.types[j].bitfield.zmmword
1757 && !t->operand_types[j].bitfield.zmmword)));
5c07affc
L		 1758}
1759
1760/* Return 1 if there is no size conflict on any operands for
1761 instruction template T. */
1762
1763static INLINE int
d3ce72d0 1764operand_size_match (const insn_template *t)
5c07affc
L		 1765{
1766 unsigned int j;
1767 int match = 1;
1768
1769 /* Don't check jump instructions. */
1770 if (t->opcode_modifier.jump
1771 || t->opcode_modifier.jumpbyte
1772 || t->opcode_modifier.jumpdword
1773 || t->opcode_modifier.jumpintersegment)
1774 return match;
1775
1776 /* Check memory and accumulator operand size. */
1777 for (j = 0; j < i.operands; j++)
1778 {
1779 if (t->operand_types[j].bitfield.anysize)
1780 continue;
1781
1782 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1783 {
1784 match = 0;
1785 break;
1786 }
1787
1788 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1789 {
1790 match = 0;
1791 break;
1792 }
1793 }
1794
891edac4 1795 if (match)
5c07affc 1796 return match;
891edac4
L		 1797 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1798 {
1799mismatch:
86e026a4 1800 i.error = operand_size_mismatch;
891edac4
L		 1801 return 0;
1802 }
5c07affc
L		 1803
1804 /* Check reverse. */
9c2799c2 1805 gas_assert (i.operands == 2);
5c07affc
L		 1806
1807 match = 1;
1808 for (j = 0; j < 2; j++)
1809 {
1810 if (t->operand_types[j].bitfield.acc
1811 && !match_reg_size (t, j ? 0 : 1))
891edac4 1812 goto mismatch;
5c07affc
L		 1813
1814 if (i.types[j].bitfield.mem
1815 && !match_mem_size (t, j ? 0 : 1))
891edac4 1816 goto mismatch;
5c07affc
L		 1817 }
1818
1819 return match;
1820}
1821
c6fb90c8 1822static INLINE int
40fb9820
L		 1823operand_type_match (i386_operand_type overlap,
1824 i386_operand_type given)
1825{
1826 i386_operand_type temp = overlap;
1827
1828 temp.bitfield.jumpabsolute = 0;
7d5e4556 1829 temp.bitfield.unspecified = 0;
5c07affc
L		 1830 temp.bitfield.byte = 0;
1831 temp.bitfield.word = 0;
1832 temp.bitfield.dword = 0;
1833 temp.bitfield.fword = 0;
1834 temp.bitfield.qword = 0;
1835 temp.bitfield.tbyte = 0;
1836 temp.bitfield.xmmword = 0;
c0f3af97 1837 temp.bitfield.ymmword = 0;
43234a1e 1838 temp.bitfield.zmmword = 0;
0dfbf9d7 1839 if (operand_type_all_zero (&temp))
891edac4 1840 goto mismatch;
40fb9820 1841
891edac4
L		 1842 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1843 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1844 return 1;
1845
1846mismatch:
a65babc9 1847 i.error = operand_type_mismatch;
891edac4 1848 return 0;
40fb9820
L		 1849}
1850
7d5e4556 1851/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1852 unless the expected operand type register overlap is null.
1853 Note that Acc in a template matches every size of reg. */
1854
c6fb90c8 1855static INLINE int
40fb9820
L		 1856operand_type_register_match (i386_operand_type m0,
1857 i386_operand_type g0,
1858 i386_operand_type t0,
1859 i386_operand_type m1,
1860 i386_operand_type g1,
1861 i386_operand_type t1)
1862{
1863 if (!operand_type_check (g0, reg))
1864 return 1;
1865
1866 if (!operand_type_check (g1, reg))
1867 return 1;
1868
1869 if (g0.bitfield.reg8 == g1.bitfield.reg8
1870 && g0.bitfield.reg16 == g1.bitfield.reg16
1871 && g0.bitfield.reg32 == g1.bitfield.reg32
1872 && g0.bitfield.reg64 == g1.bitfield.reg64)
1873 return 1;
1874
1875 if (m0.bitfield.acc)
1876 {
1877 t0.bitfield.reg8 = 1;
1878 t0.bitfield.reg16 = 1;
1879 t0.bitfield.reg32 = 1;
1880 t0.bitfield.reg64 = 1;
1881 }
1882
1883 if (m1.bitfield.acc)
1884 {
1885 t1.bitfield.reg8 = 1;
1886 t1.bitfield.reg16 = 1;
1887 t1.bitfield.reg32 = 1;
1888 t1.bitfield.reg64 = 1;
1889 }
1890
891edac4
L		 1891 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1892 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1893 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1894 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1895 return 1;
1896
a65babc9 1897 i.error = register_type_mismatch;
891edac4
L		 1898
1899 return 0;
40fb9820
L		 1900}
1901
4c692bc7
JB		 1902static INLINE unsigned int
1903register_number (const reg_entry *r)
1904{
1905 unsigned int nr = r->reg_num;
1906
1907 if (r->reg_flags & RegRex)
1908 nr += 8;
1909
200cbe0f
L		 1910 if (r->reg_flags & RegVRex)
1911 nr += 16;
1912
4c692bc7
JB		 1913 return nr;
1914}
1915
252b5132 1916static INLINE unsigned int
40fb9820 1917mode_from_disp_size (i386_operand_type t)
252b5132 1918{
43234a1e 1919 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
40fb9820
L		 1920 return 1;
1921 else if (t.bitfield.disp16
1922 || t.bitfield.disp32
1923 || t.bitfield.disp32s)
1924 return 2;
1925 else
1926 return 0;
252b5132
RH		 1927}
1928
1929static INLINE int
65879393 1930fits_in_signed_byte (addressT num)
252b5132 1931{
65879393 1932 return num + 0x80 <= 0xff;
47926f60 1933}
252b5132
RH		 1934
1935static INLINE int
65879393 1936fits_in_unsigned_byte (addressT num)
252b5132 1937{
65879393 1938 return num <= 0xff;
47926f60 1939}
252b5132
RH		 1940
1941static INLINE int
65879393 1942fits_in_unsigned_word (addressT num)
252b5132 1943{
65879393 1944 return num <= 0xffff;
47926f60 1945}
252b5132
RH		 1946
1947static INLINE int
65879393 1948fits_in_signed_word (addressT num)
252b5132 1949{
65879393 1950 return num + 0x8000 <= 0xffff;
47926f60 1951}
2a962e6d 1952
3e73aa7c 1953static INLINE int
65879393 1954fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1955{
1956#ifndef BFD64
1957 return 1;
1958#else
65879393 1959 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 1960#endif
1961} /* fits_in_signed_long() */
2a962e6d 1962
3e73aa7c 1963static INLINE int
65879393 1964fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1965{
1966#ifndef BFD64
1967 return 1;
1968#else
65879393 1969 return num <= 0xffffffff;
3e73aa7c
JH		 1970#endif
1971} /* fits_in_unsigned_long() */
252b5132 1972
43234a1e
L		 1973static INLINE int
1974fits_in_vec_disp8 (offsetT num)
1975{
1976 int shift = i.memshift;
1977 unsigned int mask;
1978
1979 if (shift == -1)
1980 abort ();
1981
1982 mask = (1 << shift) - 1;
1983
1984 /* Return 0 if NUM isn't properly aligned. */
1985 if ((num & mask))
1986 return 0;
1987
1988 /* Check if NUM will fit in 8bit after shift. */
1989 return fits_in_signed_byte (num >> shift);
1990}
1991
a683cc34
SP		 1992static INLINE int
1993fits_in_imm4 (offsetT num)
1994{
1995 return (num & 0xf) == num;
1996}
1997
40fb9820 1998static i386_operand_type
e3bb37b5 1999smallest_imm_type (offsetT num)
252b5132 2000{
40fb9820 2001 i386_operand_type t;
7ab9ffdd 2002
0dfbf9d7 2003 operand_type_set (&t, 0);
40fb9820
L		 2004 t.bitfield.imm64 = 1;
2005
2006 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2007 {
2008 /* This code is disabled on the 486 because all the Imm1 forms
2009 in the opcode table are slower on the i486. They're the
2010 versions with the implicitly specified single-position
2011 displacement, which has another syntax if you really want to
2012 use that form. */
40fb9820
L		 2013 t.bitfield.imm1 = 1;
2014 t.bitfield.imm8 = 1;
2015 t.bitfield.imm8s = 1;
2016 t.bitfield.imm16 = 1;
2017 t.bitfield.imm32 = 1;
2018 t.bitfield.imm32s = 1;
2019 }
2020 else if (fits_in_signed_byte (num))
2021 {
2022 t.bitfield.imm8 = 1;
2023 t.bitfield.imm8s = 1;
2024 t.bitfield.imm16 = 1;
2025 t.bitfield.imm32 = 1;
2026 t.bitfield.imm32s = 1;
2027 }
2028 else if (fits_in_unsigned_byte (num))
2029 {
2030 t.bitfield.imm8 = 1;
2031 t.bitfield.imm16 = 1;
2032 t.bitfield.imm32 = 1;
2033 t.bitfield.imm32s = 1;
2034 }
2035 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2036 {
2037 t.bitfield.imm16 = 1;
2038 t.bitfield.imm32 = 1;
2039 t.bitfield.imm32s = 1;
2040 }
2041 else if (fits_in_signed_long (num))
2042 {
2043 t.bitfield.imm32 = 1;
2044 t.bitfield.imm32s = 1;
2045 }
2046 else if (fits_in_unsigned_long (num))
2047 t.bitfield.imm32 = 1;
2048
2049 return t;
47926f60 2050}
252b5132 2051
847f7ad4 2052static offsetT
e3bb37b5 2053offset_in_range (offsetT val, int size)
847f7ad4 2054{
508866be 2055 addressT mask;
ba2adb93 2056
847f7ad4
AM		 2057 switch (size)
2058 {
508866be
L		 2059 case 1: mask = ((addressT) 1 << 8) - 1; break;
2060 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2061 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2062#ifdef BFD64
2063 case 8: mask = ((addressT) 2 << 63) - 1; break;
2064#endif
47926f60 2065 default: abort ();
847f7ad4
AM		 2066 }
2067
9de868bf
L		 2068#ifdef BFD64
2069 /* If BFD64, sign extend val for 32bit address mode. */
2070 if (flag_code != CODE_64BIT
2071 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2072 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2073 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2074#endif
ba2adb93 2075
47926f60 2076 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2077 {
2078 char buf1[40], buf2[40];
2079
2080 sprint_value (buf1, val);
2081 sprint_value (buf2, val & mask);
2082 as_warn (_("%s shortened to %s"), buf1, buf2);
2083 }
2084 return val & mask;
2085}
2086
c32fa91d
L		 2087enum PREFIX_GROUP
2088{
2089 PREFIX_EXIST = 0,
2090 PREFIX_LOCK,
2091 PREFIX_REP,
2092 PREFIX_OTHER
2093};
2094
2095/* Returns
2096 a. PREFIX_EXIST if attempting to add a prefix where one from the
2097 same class already exists.
2098 b. PREFIX_LOCK if lock prefix is added.
2099 c. PREFIX_REP if rep/repne prefix is added.
2100 d. PREFIX_OTHER if other prefix is added.
2101 */
2102
2103static enum PREFIX_GROUP
e3bb37b5 2104add_prefix (unsigned int prefix)
252b5132 2105{
c32fa91d 2106 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2107 unsigned int q;
252b5132 2108
29b0f896
AM		 2109 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2110 && flag_code == CODE_64BIT)
b1905489 2111 {
161a04f6
L		 2112 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2113 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2114 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2115 ret = PREFIX_EXIST;
b1905489
JB		 2116 q = REX_PREFIX;
2117 }
3e73aa7c 2118 else
b1905489
JB		 2119 {
2120 switch (prefix)
2121 {
2122 default:
2123 abort ();
2124
2125 case CS_PREFIX_OPCODE:
2126 case DS_PREFIX_OPCODE:
2127 case ES_PREFIX_OPCODE:
2128 case FS_PREFIX_OPCODE:
2129 case GS_PREFIX_OPCODE:
2130 case SS_PREFIX_OPCODE:
2131 q = SEG_PREFIX;
2132 break;
2133
2134 case REPNE_PREFIX_OPCODE:
2135 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2136 q = REP_PREFIX;
2137 ret = PREFIX_REP;
2138 break;
2139
b1905489 2140 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2141 q = LOCK_PREFIX;
2142 ret = PREFIX_LOCK;
b1905489
JB		 2143 break;
2144
2145 case FWAIT_OPCODE:
2146 q = WAIT_PREFIX;
2147 break;
2148
2149 case ADDR_PREFIX_OPCODE:
2150 q = ADDR_PREFIX;
2151 break;
2152
2153 case DATA_PREFIX_OPCODE:
2154 q = DATA_PREFIX;
2155 break;
2156 }
2157 if (i.prefix[q] != 0)
c32fa91d 2158 ret = PREFIX_EXIST;
b1905489 2159 }
252b5132 2160
b1905489 2161 if (ret)
252b5132 2162 {
b1905489
JB		 2163 if (!i.prefix[q])
2164 ++i.prefixes;
2165 i.prefix[q] |= prefix;
252b5132 2166 }
b1905489
JB		 2167 else
2168 as_bad (_("same type of prefix used twice"));
252b5132 2169
252b5132
RH		 2170 return ret;
2171}
2172
2173static void
78f12dd3 2174update_code_flag (int value, int check)
eecb386c 2175{
78f12dd3
L		 2176 PRINTF_LIKE ((*as_error));
2177
1e9cc1c2 2178 flag_code = (enum flag_code) value;
40fb9820
L		 2179 if (flag_code == CODE_64BIT)
2180 {
2181 cpu_arch_flags.bitfield.cpu64 = 1;
2182 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2183 }
2184 else
2185 {
2186 cpu_arch_flags.bitfield.cpu64 = 0;
2187 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2188 }
2189 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2190 {
78f12dd3
L		 2191 if (check)
2192 as_error = as_fatal;
2193 else
2194 as_error = as_bad;
2195 (*as_error) (_("64bit mode not supported on `%s'."),
2196 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2197 }
40fb9820 2198 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2199 {
78f12dd3
L		 2200 if (check)
2201 as_error = as_fatal;
2202 else
2203 as_error = as_bad;
2204 (*as_error) (_("32bit mode not supported on `%s'."),
2205 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2206 }
eecb386c
AM		 2207 stackop_size = '\0';
2208}
2209
78f12dd3
L		 2210static void
2211set_code_flag (int value)
2212{
2213 update_code_flag (value, 0);
2214}
2215
eecb386c 2216static void
e3bb37b5 2217set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2218{
1e9cc1c2 2219 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2220 if (flag_code != CODE_16BIT)
2221 abort ();
2222 cpu_arch_flags.bitfield.cpu64 = 0;
2223 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2224 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2225}
2226
2227static void
e3bb37b5 2228set_intel_syntax (int syntax_flag)
252b5132
RH		 2229{
2230 /* Find out if register prefixing is specified. */
2231 int ask_naked_reg = 0;
2232
2233 SKIP_WHITESPACE ();
29b0f896 2234 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132 2235 {
d02603dc
NC		 2236 char *string;
2237 int e = get_symbol_name (&string);
252b5132 2238
47926f60 2239 if (strcmp (string, "prefix") == 0)
252b5132 2240 ask_naked_reg = 1;
47926f60 2241 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2242 ask_naked_reg = -1;
2243 else
d0b47220 2244 as_bad (_("bad argument to syntax directive."));
d02603dc 2245 (void) restore_line_pointer (e);
252b5132
RH		 2246 }
2247 demand_empty_rest_of_line ();
c3332e24 2248
252b5132
RH		 2249 intel_syntax = syntax_flag;
2250
2251 if (ask_naked_reg == 0)
f86103b7
AM		 2252 allow_naked_reg = (intel_syntax
2253 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2254 else
2255 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2256
ee86248c 2257 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2258
e4a3b5a4 2259 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2260 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2261 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2262}
2263
1efbbeb4
L		 2264static void
2265set_intel_mnemonic (int mnemonic_flag)
2266{
e1d4d893 2267 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2268}
2269
db51cc60
L		 2270static void
2271set_allow_index_reg (int flag)
2272{
2273 allow_index_reg = flag;
2274}
2275
cb19c032 2276static void
7bab8ab5 2277set_check (int what)
cb19c032 2278{
7bab8ab5
JB		 2279 enum check_kind *kind;
2280 const char *str;
2281
2282 if (what)
2283 {
2284 kind = &operand_check;
2285 str = "operand";
2286 }
2287 else
2288 {
2289 kind = &sse_check;
2290 str = "sse";
2291 }
2292
cb19c032
L		 2293 SKIP_WHITESPACE ();
2294
2295 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2296 {
d02603dc
NC		 2297 char *string;
2298 int e = get_symbol_name (&string);
cb19c032
L		 2299
2300 if (strcmp (string, "none") == 0)
7bab8ab5 2301 *kind = check_none;
cb19c032 2302 else if (strcmp (string, "warning") == 0)
7bab8ab5 2303 *kind = check_warning;
cb19c032 2304 else if (strcmp (string, "error") == 0)
7bab8ab5 2305 *kind = check_error;
cb19c032 2306 else
7bab8ab5 2307 as_bad (_("bad argument to %s_check directive."), str);
d02603dc 2308 (void) restore_line_pointer (e);
cb19c032
L		 2309 }
2310 else
7bab8ab5 2311 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2312
2313 demand_empty_rest_of_line ();
2314}
2315
8a9036a4
L		 2316static void
2317check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2318 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2319{
2320#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2321 static const char *arch;
2322
2323 /* Intel LIOM is only supported on ELF. */
2324 if (!IS_ELF)
2325 return;
2326
2327 if (!arch)
2328 {
2329 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2330 use default_arch. */
2331 arch = cpu_arch_name;
2332 if (!arch)
2333 arch = default_arch;
2334 }
2335
81486035
L		 2336 /* If we are targeting Intel MCU, we must enable it. */
2337 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2338 || new_flag.bitfield.cpuiamcu)
2339 return;
2340
3632d14b 2341 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2342 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2343 || new_flag.bitfield.cpul1om)
8a9036a4 2344 return;
76ba9986 2345
7a9068fe
L		 2346 /* If we are targeting Intel K1OM, we must enable it. */
2347 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2348 || new_flag.bitfield.cpuk1om)
2349 return;
2350
8a9036a4
L		 2351 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2352#endif
2353}
2354
e413e4e9 2355static void
e3bb37b5 2356set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2357{
47926f60 2358 SKIP_WHITESPACE ();
e413e4e9 2359
29b0f896 2360 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9 2361 {
d02603dc
NC		 2362 char *string;
2363 int e = get_symbol_name (&string);
91d6fa6a 2364 unsigned int j;
40fb9820 2365 i386_cpu_flags flags;
e413e4e9 2366
91d6fa6a 2367 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2368 {
91d6fa6a 2369 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2370 {
91d6fa6a 2371 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2372
5c6af06e
JB		 2373 if (*string != '.')
2374 {
91d6fa6a 2375 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2376 cpu_sub_arch_name = NULL;
91d6fa6a 2377 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2378 if (flag_code == CODE_64BIT)
2379 {
2380 cpu_arch_flags.bitfield.cpu64 = 1;
2381 cpu_arch_flags.bitfield.cpuno64 = 0;
2382 }
2383 else
2384 {
2385 cpu_arch_flags.bitfield.cpu64 = 0;
2386 cpu_arch_flags.bitfield.cpuno64 = 1;
2387 }
91d6fa6a
NC		 2388 cpu_arch_isa = cpu_arch[j].type;
2389 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2390 if (!cpu_arch_tune_set)
2391 {
2392 cpu_arch_tune = cpu_arch_isa;
2393 cpu_arch_tune_flags = cpu_arch_isa_flags;
2394 }
5c6af06e
JB		 2395 break;
2396 }
40fb9820 2397
293f5f65
L		 2398 flags = cpu_flags_or (cpu_arch_flags,
2399 cpu_arch[j].flags);
81486035
L		 2400
2401 if (!valid_iamcu_cpu_flags (&flags))
2402 as_fatal (_("`%s' isn't valid for Intel MCU"),
2403 cpu_arch[j].name);
2404 else if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2405 {
6305a203
L		 2406 if (cpu_sub_arch_name)
2407 {
2408 char *name = cpu_sub_arch_name;
2409 cpu_sub_arch_name = concat (name,
91d6fa6a 2410 cpu_arch[j].name,
1bf57e9f 2411 (const char *) NULL);
6305a203
L		 2412 free (name);
2413 }
2414 else
91d6fa6a 2415 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2416 cpu_arch_flags = flags;
a586129e 2417 cpu_arch_isa_flags = flags;
5c6af06e 2418 }
d02603dc 2419 (void) restore_line_pointer (e);
5c6af06e
JB		 2420 demand_empty_rest_of_line ();
2421 return;
e413e4e9
AM		 2422 }
2423 }
293f5f65
L		 2424
2425 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2426 {
2427 /* Disable an ISA entension. */
2428 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2429 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2430 {
2431 flags = cpu_flags_and_not (cpu_arch_flags,
2432 cpu_noarch[j].flags);
2433 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2434 {
2435 if (cpu_sub_arch_name)
2436 {
2437 char *name = cpu_sub_arch_name;
2438 cpu_sub_arch_name = concat (name, string,
2439 (const char *) NULL);
2440 free (name);
2441 }
2442 else
2443 cpu_sub_arch_name = xstrdup (string);
2444 cpu_arch_flags = flags;
2445 cpu_arch_isa_flags = flags;
2446 }
2447 (void) restore_line_pointer (e);
2448 demand_empty_rest_of_line ();
2449 return;
2450 }
2451
2452 j = ARRAY_SIZE (cpu_arch);
2453 }
2454
91d6fa6a 2455 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2456 as_bad (_("no such architecture: `%s'"), string);
2457
2458 *input_line_pointer = e;
2459 }
2460 else
2461 as_bad (_("missing cpu architecture"));
2462
fddf5b5b
AM		 2463 no_cond_jump_promotion = 0;
2464 if (*input_line_pointer == ','
29b0f896 2465 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b 2466 {
d02603dc
NC		 2467 char *string;
2468 char e;
2469
2470 ++input_line_pointer;
2471 e = get_symbol_name (&string);
fddf5b5b
AM		 2472
2473 if (strcmp (string, "nojumps") == 0)
2474 no_cond_jump_promotion = 1;
2475 else if (strcmp (string, "jumps") == 0)
2476 ;
2477 else
2478 as_bad (_("no such architecture modifier: `%s'"), string);
2479
d02603dc 2480 (void) restore_line_pointer (e);
fddf5b5b
AM		 2481 }
2482
e413e4e9
AM		 2483 demand_empty_rest_of_line ();
2484}
2485
8a9036a4
L		 2486enum bfd_architecture
2487i386_arch (void)
2488{
3632d14b 2489 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2490 {
2491 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2492 || flag_code != CODE_64BIT)
2493 as_fatal (_("Intel L1OM is 64bit ELF only"));
2494 return bfd_arch_l1om;
2495 }
7a9068fe
L		 2496 else if (cpu_arch_isa == PROCESSOR_K1OM)
2497 {
2498 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2499 || flag_code != CODE_64BIT)
2500 as_fatal (_("Intel K1OM is 64bit ELF only"));
2501 return bfd_arch_k1om;
2502 }
81486035
L		 2503 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2504 {
2505 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2506 || flag_code == CODE_64BIT)
2507 as_fatal (_("Intel MCU is 32bit ELF only"));
2508 return bfd_arch_iamcu;
2509 }
8a9036a4
L		 2510 else
2511 return bfd_arch_i386;
2512}
2513
b9d79e03 2514unsigned long
7016a5d5 2515i386_mach (void)
b9d79e03 2516{
351f65ca 2517 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2518 {
3632d14b 2519 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2520 {
351f65ca
L		 2521 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2522 || default_arch[6] != '\0')
8a9036a4
L		 2523 as_fatal (_("Intel L1OM is 64bit ELF only"));
2524 return bfd_mach_l1om;
2525 }
7a9068fe
L		 2526 else if (cpu_arch_isa == PROCESSOR_K1OM)
2527 {
2528 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2529 || default_arch[6] != '\0')
2530 as_fatal (_("Intel K1OM is 64bit ELF only"));
2531 return bfd_mach_k1om;
2532 }
351f65ca 2533 else if (default_arch[6] == '\0')
8a9036a4 2534 return bfd_mach_x86_64;
351f65ca
L		 2535 else
2536 return bfd_mach_x64_32;
8a9036a4 2537 }
5197d474
L		 2538 else if (!strcmp (default_arch, "i386")
2539 || !strcmp (default_arch, "iamcu"))
81486035
L		 2540 {
2541 if (cpu_arch_isa == PROCESSOR_IAMCU)
2542 {
2543 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2544 as_fatal (_("Intel MCU is 32bit ELF only"));
2545 return bfd_mach_i386_iamcu;
2546 }
2547 else
2548 return bfd_mach_i386_i386;
2549 }
b9d79e03 2550 else
2b5d6a91 2551 as_fatal (_("unknown architecture"));
b9d79e03 2552}
b9d79e03 2553\f
252b5132 2554void
7016a5d5 2555md_begin (void)
252b5132
RH		 2556{
2557 const char *hash_err;
2558
47926f60 2559 /* Initialize op_hash hash table. */
252b5132
RH		 2560 op_hash = hash_new ();
2561
2562 {
d3ce72d0 2563 const insn_template *optab;
29b0f896 2564 templates *core_optab;
252b5132 2565
47926f60
KH		 2566 /* Setup for loop. */
2567 optab = i386_optab;
add39d23 2568 core_optab = XNEW (templates);
252b5132
RH		 2569 core_optab->start = optab;
2570
2571 while (1)
2572 {
2573 ++optab;
2574 if (optab->name == NULL
2575 || strcmp (optab->name, (optab - 1)->name) != 0)
2576 {
2577 /* different name --> ship out current template list;
47926f60 2578 add to hash table; & begin anew. */
252b5132
RH		 2579 core_optab->end = optab;
2580 hash_err = hash_insert (op_hash,
2581 (optab - 1)->name,
5a49b8ac 2582 (void *) core_optab);
252b5132
RH		 2583 if (hash_err)
2584 {
b37df7c4 2585 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2586 (optab - 1)->name,
2587 hash_err);
2588 }
2589 if (optab->name == NULL)
2590 break;
add39d23 2591 core_optab = XNEW (templates);
252b5132
RH		 2592 core_optab->start = optab;
2593 }
2594 }
2595 }
2596
47926f60 2597 /* Initialize reg_hash hash table. */
252b5132
RH		 2598 reg_hash = hash_new ();
2599 {
29b0f896 2600 const reg_entry *regtab;
c3fe08fa 2601 unsigned int regtab_size = i386_regtab_size;
252b5132 2602
c3fe08fa 2603 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2604 {
5a49b8ac 2605 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2606 if (hash_err)
b37df7c4 2607 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2608 regtab->reg_name,
2609 hash_err);
252b5132
RH		 2610 }
2611 }
2612
47926f60 2613 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2614 {
29b0f896
AM		 2615 int c;
2616 char *p;
252b5132
RH		 2617
2618 for (c = 0; c < 256; c++)
2619 {
3882b010 2620 if (ISDIGIT (c))
252b5132
RH		 2621 {
2622 digit_chars[c] = c;
2623 mnemonic_chars[c] = c;
2624 register_chars[c] = c;
2625 operand_chars[c] = c;
2626 }
3882b010 2627 else if (ISLOWER (c))
252b5132
RH		 2628 {
2629 mnemonic_chars[c] = c;
2630 register_chars[c] = c;
2631 operand_chars[c] = c;
2632 }
3882b010 2633 else if (ISUPPER (c))
252b5132 2634 {
3882b010 2635 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2636 register_chars[c] = mnemonic_chars[c];
2637 operand_chars[c] = c;
2638 }
43234a1e
L		 2639 else if (c == '{' || c == '}')
2640 operand_chars[c] = c;
252b5132 2641
3882b010 2642 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2643 identifier_chars[c] = c;
2644 else if (c >= 128)
2645 {
2646 identifier_chars[c] = c;
2647 operand_chars[c] = c;
2648 }
2649 }
2650
2651#ifdef LEX_AT
2652 identifier_chars['@'] = '@';
32137342
NC		 2653#endif
2654#ifdef LEX_QM
2655 identifier_chars['?'] = '?';
2656 operand_chars['?'] = '?';
252b5132 2657#endif
252b5132 2658 digit_chars['-'] = '-';
c0f3af97 2659 mnemonic_chars['_'] = '_';
791fe849 2660 mnemonic_chars['-'] = '-';
0003779b 2661 mnemonic_chars['.'] = '.';
252b5132
RH		 2662 identifier_chars['_'] = '_';
2663 identifier_chars['.'] = '.';
2664
2665 for (p = operand_special_chars; *p != '\0'; p++)
2666 operand_chars[(unsigned char) *p] = *p;
2667 }
2668
a4447b93
RH		 2669 if (flag_code == CODE_64BIT)
2670 {
ca19b261
KT		 2671#if defined (OBJ_COFF) && defined (TE_PE)
2672 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2673 ? 32 : 16);
2674#else
a4447b93 2675 x86_dwarf2_return_column = 16;
ca19b261 2676#endif
61ff971f 2677 x86_cie_data_alignment = -8;
a4447b93
RH		 2678 }
2679 else
2680 {
2681 x86_dwarf2_return_column = 8;
2682 x86_cie_data_alignment = -4;
2683 }
252b5132
RH		 2684}
2685
2686void
e3bb37b5 2687i386_print_statistics (FILE *file)
252b5132
RH		 2688{
2689 hash_print_statistics (file, "i386 opcode", op_hash);
2690 hash_print_statistics (file, "i386 register", reg_hash);
2691}
2692\f
252b5132
RH		 2693#ifdef DEBUG386
2694
ce8a8b2f 2695/* Debugging routines for md_assemble. */
d3ce72d0 2696static void pte (insn_template *);
40fb9820 2697static void pt (i386_operand_type);
e3bb37b5
L		 2698static void pe (expressionS *);
2699static void ps (symbolS *);
252b5132
RH		 2700
2701static void
e3bb37b5 2702pi (char *line, i386_insn *x)
252b5132 2703{
09137c09 2704 unsigned int j;
252b5132
RH		 2705
2706 fprintf (stdout, "%s: template ", line);
2707 pte (&x->tm);
09f131f2
JH		 2708 fprintf (stdout, " address: base %s index %s scale %x\n",
2709 x->base_reg ? x->base_reg->reg_name : "none",
2710 x->index_reg ? x->index_reg->reg_name : "none",
2711 x->log2_scale_factor);
2712 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2713 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2714 fprintf (stdout, " sib: base %x index %x scale %x\n",
2715 x->sib.base, x->sib.index, x->sib.scale);
2716 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2717 (x->rex & REX_W) != 0,
2718 (x->rex & REX_R) != 0,
2719 (x->rex & REX_X) != 0,
2720 (x->rex & REX_B) != 0);
09137c09 2721 for (j = 0; j < x->operands; j++)
252b5132 2722 {
09137c09
SP		 2723 fprintf (stdout, " #%d: ", j + 1);
2724 pt (x->types[j]);
252b5132 2725 fprintf (stdout, "\n");
09137c09
SP		 2726 if (x->types[j].bitfield.reg8
2727 || x->types[j].bitfield.reg16
2728 || x->types[j].bitfield.reg32
2729 || x->types[j].bitfield.reg64
2730 || x->types[j].bitfield.regmmx
2731 || x->types[j].bitfield.regxmm
2732 || x->types[j].bitfield.regymm
43234a1e 2733 || x->types[j].bitfield.regzmm
09137c09
SP		 2734 || x->types[j].bitfield.sreg2
2735 || x->types[j].bitfield.sreg3
2736 || x->types[j].bitfield.control
2737 || x->types[j].bitfield.debug
2738 || x->types[j].bitfield.test)
2739 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2740 if (operand_type_check (x->types[j], imm))
2741 pe (x->op[j].imms);
2742 if (operand_type_check (x->types[j], disp))
2743 pe (x->op[j].disps);
252b5132
RH		 2744 }
2745}
2746
2747static void
d3ce72d0 2748pte (insn_template *t)
252b5132 2749{
09137c09 2750 unsigned int j;
252b5132 2751 fprintf (stdout, " %d operands ", t->operands);
47926f60 2752 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2753 if (t->extension_opcode != None)
2754 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2755 if (t->opcode_modifier.d)
252b5132 2756 fprintf (stdout, "D");
40fb9820 2757 if (t->opcode_modifier.w)
252b5132
RH		 2758 fprintf (stdout, "W");
2759 fprintf (stdout, "\n");
09137c09 2760 for (j = 0; j < t->operands; j++)
252b5132 2761 {
09137c09
SP		 2762 fprintf (stdout, " #%d type ", j + 1);
2763 pt (t->operand_types[j]);
252b5132
RH		 2764 fprintf (stdout, "\n");
2765 }
2766}
2767
2768static void
e3bb37b5 2769pe (expressionS *e)
252b5132 2770{
24eab124 2771 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2772 fprintf (stdout, " add_number %ld (%lx)\n",
2773 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2774 if (e->X_add_symbol)
2775 {
2776 fprintf (stdout, " add_symbol ");
2777 ps (e->X_add_symbol);
2778 fprintf (stdout, "\n");
2779 }
2780 if (e->X_op_symbol)
2781 {
2782 fprintf (stdout, " op_symbol ");
2783 ps (e->X_op_symbol);
2784 fprintf (stdout, "\n");
2785 }
2786}
2787
2788static void
e3bb37b5 2789ps (symbolS *s)
252b5132
RH		 2790{
2791 fprintf (stdout, "%s type %s%s",
2792 S_GET_NAME (s),
2793 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2794 segment_name (S_GET_SEGMENT (s)));
2795}
2796
7b81dfbb 2797static struct type_name
252b5132 2798 {
40fb9820
L		 2799 i386_operand_type mask;
2800 const char *name;
252b5132 2801 }
7b81dfbb 2802const type_names[] =
252b5132 2803{
40fb9820
L		 2804 { OPERAND_TYPE_REG8, "r8" },
2805 { OPERAND_TYPE_REG16, "r16" },
2806 { OPERAND_TYPE_REG32, "r32" },
2807 { OPERAND_TYPE_REG64, "r64" },
2808 { OPERAND_TYPE_IMM8, "i8" },
2809 { OPERAND_TYPE_IMM8, "i8s" },
2810 { OPERAND_TYPE_IMM16, "i16" },
2811 { OPERAND_TYPE_IMM32, "i32" },
2812 { OPERAND_TYPE_IMM32S, "i32s" },
2813 { OPERAND_TYPE_IMM64, "i64" },
2814 { OPERAND_TYPE_IMM1, "i1" },
2815 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2816 { OPERAND_TYPE_DISP8, "d8" },
2817 { OPERAND_TYPE_DISP16, "d16" },
2818 { OPERAND_TYPE_DISP32, "d32" },
2819 { OPERAND_TYPE_DISP32S, "d32s" },
2820 { OPERAND_TYPE_DISP64, "d64" },
43234a1e 2821 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
40fb9820
L		 2822 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2823 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2824 { OPERAND_TYPE_CONTROL, "control reg" },
2825 { OPERAND_TYPE_TEST, "test reg" },
2826 { OPERAND_TYPE_DEBUG, "debug reg" },
2827 { OPERAND_TYPE_FLOATREG, "FReg" },
2828 { OPERAND_TYPE_FLOATACC, "FAcc" },
2829 { OPERAND_TYPE_SREG2, "SReg2" },
2830 { OPERAND_TYPE_SREG3, "SReg3" },
2831 { OPERAND_TYPE_ACC, "Acc" },
2832 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2833 { OPERAND_TYPE_REGMMX, "rMMX" },
2834 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2835 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2836 { OPERAND_TYPE_REGZMM, "rZMM" },
2837 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2838 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2839};
2840
2841static void
40fb9820 2842pt (i386_operand_type t)
252b5132 2843{
40fb9820 2844 unsigned int j;
c6fb90c8 2845 i386_operand_type a;
252b5132 2846
40fb9820 2847 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2848 {
2849 a = operand_type_and (t, type_names[j].mask);
0349dc08 2850 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2851 fprintf (stdout, "%s, ", type_names[j].name);
2852 }
252b5132
RH		 2853 fflush (stdout);
2854}
2855
2856#endif /* DEBUG386 */
2857\f
252b5132 2858static bfd_reloc_code_real_type
3956db08 2859reloc (unsigned int size,
64e74474
AM		 2860 int pcrel,
2861 int sign,
2862 bfd_reloc_code_real_type other)
252b5132 2863{
47926f60 2864 if (other != NO_RELOC)
3956db08 2865 {
91d6fa6a 2866 reloc_howto_type *rel;
3956db08
JB		 2867
2868 if (size == 8)
2869 switch (other)
2870 {
64e74474
AM		 2871 case BFD_RELOC_X86_64_GOT32:
2872 return BFD_RELOC_X86_64_GOT64;
2873 break;
553d1284
L		 2874 case BFD_RELOC_X86_64_GOTPLT64:
2875 return BFD_RELOC_X86_64_GOTPLT64;
2876 break;
64e74474
AM		 2877 case BFD_RELOC_X86_64_PLTOFF64:
2878 return BFD_RELOC_X86_64_PLTOFF64;
2879 break;
2880 case BFD_RELOC_X86_64_GOTPC32:
2881 other = BFD_RELOC_X86_64_GOTPC64;
2882 break;
2883 case BFD_RELOC_X86_64_GOTPCREL:
2884 other = BFD_RELOC_X86_64_GOTPCREL64;
2885 break;
2886 case BFD_RELOC_X86_64_TPOFF32:
2887 other = BFD_RELOC_X86_64_TPOFF64;
2888 break;
2889 case BFD_RELOC_X86_64_DTPOFF32:
2890 other = BFD_RELOC_X86_64_DTPOFF64;
2891 break;
2892 default:
2893 break;
3956db08 2894 }
e05278af 2895
8ce3d284 2896#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2897 if (other == BFD_RELOC_SIZE32)
2898 {
2899 if (size == 8)
1ab668bf 2900 other = BFD_RELOC_SIZE64;
8fd4256d 2901 if (pcrel)
1ab668bf
AM		 2902 {
2903 as_bad (_("there are no pc-relative size relocations"));
2904 return NO_RELOC;
2905 }
8fd4256d 2906 }
8ce3d284 2907#endif
8fd4256d 2908
e05278af 2909 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2910 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2911 sign = -1;
2912
91d6fa6a
NC		 2913 rel = bfd_reloc_type_lookup (stdoutput, other);
2914 if (!rel)
3956db08 2915 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2916 else if (size != bfd_get_reloc_size (rel))
3956db08 2917 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2918 bfd_get_reloc_size (rel),
3956db08 2919 size);
91d6fa6a 2920 else if (pcrel && !rel->pc_relative)
3956db08 2921 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2922 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2923 && !sign)
91d6fa6a 2924 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2925 && sign > 0))
3956db08
JB		 2926 as_bad (_("relocated field and relocation type differ in signedness"));
2927 else
2928 return other;
2929 return NO_RELOC;
2930 }
252b5132
RH		 2931
2932 if (pcrel)
2933 {
3e73aa7c 2934 if (!sign)
3956db08 2935 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2936 switch (size)
2937 {
2938 case 1: return BFD_RELOC_8_PCREL;
2939 case 2: return BFD_RELOC_16_PCREL;
d258b828 2940 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2941 case 8: return BFD_RELOC_64_PCREL;
252b5132 2942 }
3956db08 2943 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2944 }
2945 else
2946 {
3956db08 2947 if (sign > 0)
e5cb08ac 2948 switch (size)
3e73aa7c
JH		 2949 {
2950 case 4: return BFD_RELOC_X86_64_32S;
2951 }
2952 else
2953 switch (size)
2954 {
2955 case 1: return BFD_RELOC_8;
2956 case 2: return BFD_RELOC_16;
2957 case 4: return BFD_RELOC_32;
2958 case 8: return BFD_RELOC_64;
2959 }
3956db08
JB		 2960 as_bad (_("cannot do %s %u byte relocation"),
2961 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2962 }
2963
0cc9e1d3 2964 return NO_RELOC;
252b5132
RH		 2965}
2966
47926f60
KH		 2967/* Here we decide which fixups can be adjusted to make them relative to
2968 the beginning of the section instead of the symbol. Basically we need
2969 to make sure that the dynamic relocations are done correctly, so in
2970 some cases we force the original symbol to be used. */
2971
252b5132 2972int
e3bb37b5 2973tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2974{
6d249963 2975#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2976 if (!IS_ELF)
31312f95
AM		 2977 return 1;
2978
a161fe53
AM		 2979 /* Don't adjust pc-relative references to merge sections in 64-bit
2980 mode. */
2981 if (use_rela_relocations
2982 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2983 && fixP->fx_pcrel)
252b5132 2984 return 0;
31312f95 2985
8d01d9a9
AJ		 2986 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2987 and changed later by validate_fix. */
2988 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2989 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2990 return 0;
2991
8fd4256d
L		 2992 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2993 for size relocations. */
2994 if (fixP->fx_r_type == BFD_RELOC_SIZE32
2995 || fixP->fx_r_type == BFD_RELOC_SIZE64
2996 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 2997 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2998 || fixP->fx_r_type == BFD_RELOC_386_GOT32
02a86693 2999 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
13ae64f3
JJ		 3000 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3001 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3002 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3003 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 3004 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3005 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 3006 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3007 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 3008 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3009 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 3010 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3011 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 3012 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
56ceb5b5
L		 3013 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3014 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
bffbf940
JJ		 3015 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3016 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3017 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 3018 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 3019 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3020 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 3021 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3022 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 3023 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3024 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 3025 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3026 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3027 return 0;
31312f95 3028#endif
252b5132
RH		 3029 return 1;
3030}
252b5132 3031
b4cac588 3032static int
e3bb37b5 3033intel_float_operand (const char *mnemonic)
252b5132 3034{
9306ca4a
JB		 3035 /* Note that the value returned is meaningful only for opcodes with (memory)
3036 operands, hence the code here is free to improperly handle opcodes that
3037 have no operands (for better performance and smaller code). */
3038
3039 if (mnemonic[0] != 'f')
3040 return 0; /* non-math */
3041
3042 switch (mnemonic[1])
3043 {
3044 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3045 the fs segment override prefix not currently handled because no
3046 call path can make opcodes without operands get here */
3047 case 'i':
3048 return 2 /* integer op */;
3049 case 'l':
3050 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3051 return 3; /* fldcw/fldenv */
3052 break;
3053 case 'n':
3054 if (mnemonic[2] != 'o' /* fnop */)
3055 return 3; /* non-waiting control op */
3056 break;
3057 case 'r':
3058 if (mnemonic[2] == 's')
3059 return 3; /* frstor/frstpm */
3060 break;
3061 case 's':
3062 if (mnemonic[2] == 'a')
3063 return 3; /* fsave */
3064 if (mnemonic[2] == 't')
3065 {
3066 switch (mnemonic[3])
3067 {
3068 case 'c': /* fstcw */
3069 case 'd': /* fstdw */
3070 case 'e': /* fstenv */
3071 case 's': /* fsts[gw] */
3072 return 3;
3073 }
3074 }
3075 break;
3076 case 'x':
3077 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3078 return 0; /* fxsave/fxrstor are not really math ops */
3079 break;
3080 }
252b5132 3081
9306ca4a 3082 return 1;
252b5132
RH		 3083}
3084
c0f3af97
L		 3085/* Build the VEX prefix. */
3086
3087static void
d3ce72d0 3088build_vex_prefix (const insn_template *t)
c0f3af97
L		 3089{
3090 unsigned int register_specifier;
3091 unsigned int implied_prefix;
3092 unsigned int vector_length;
3093
3094 /* Check register specifier. */
3095 if (i.vex.register_specifier)
43234a1e
L		 3096 {
3097 register_specifier =
3098 ~register_number (i.vex.register_specifier) & 0xf;
3099 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3100 }
c0f3af97
L		 3101 else
3102 register_specifier = 0xf;
3103
fa99fab2
L		 3104 /* Use 2-byte VEX prefix by swappping destination and source
3105 operand. */
3106 if (!i.swap_operand
3107 && i.operands == i.reg_operands
7f399153 3108 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 3109 && i.tm.opcode_modifier.s
3110 && i.rex == REX_B)
3111 {
3112 unsigned int xchg = i.operands - 1;
3113 union i386_op temp_op;
3114 i386_operand_type temp_type;
3115
3116 temp_type = i.types[xchg];
3117 i.types[xchg] = i.types[0];
3118 i.types[0] = temp_type;
3119 temp_op = i.op[xchg];
3120 i.op[xchg] = i.op[0];
3121 i.op[0] = temp_op;
3122
9c2799c2 3123 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3124
3125 i.rex = REX_R;
3126 xchg = i.rm.regmem;
3127 i.rm.regmem = i.rm.reg;
3128 i.rm.reg = xchg;
3129
3130 /* Use the next insn. */
3131 i.tm = t[1];
3132 }
3133
539f890d
L		 3134 if (i.tm.opcode_modifier.vex == VEXScalar)
3135 vector_length = avxscalar;
3136 else
3137 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3138
3139 switch ((i.tm.base_opcode >> 8) & 0xff)
3140 {
3141 case 0:
3142 implied_prefix = 0;
3143 break;
3144 case DATA_PREFIX_OPCODE:
3145 implied_prefix = 1;
3146 break;
3147 case REPE_PREFIX_OPCODE:
3148 implied_prefix = 2;
3149 break;
3150 case REPNE_PREFIX_OPCODE:
3151 implied_prefix = 3;
3152 break;
3153 default:
3154 abort ();
3155 }
3156
3157 /* Use 2-byte VEX prefix if possible. */
7f399153 3158 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3159 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3160 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3161 {
3162 /* 2-byte VEX prefix. */
3163 unsigned int r;
3164
3165 i.vex.length = 2;
3166 i.vex.bytes[0] = 0xc5;
3167
3168 /* Check the REX.R bit. */
3169 r = (i.rex & REX_R) ? 0 : 1;
3170 i.vex.bytes[1] = (r << 7
3171 | register_specifier << 3
3172 | vector_length << 2
3173 | implied_prefix);
3174 }
3175 else
3176 {
3177 /* 3-byte VEX prefix. */
3178 unsigned int m, w;
3179
f88c9eb0 3180 i.vex.length = 3;
f88c9eb0 3181
7f399153 3182 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3183 {
7f399153
L		 3184 case VEX0F:
3185 m = 0x1;
80de6e00 3186 i.vex.bytes[0] = 0xc4;
7f399153
L		 3187 break;
3188 case VEX0F38:
3189 m = 0x2;
80de6e00 3190 i.vex.bytes[0] = 0xc4;
7f399153
L		 3191 break;
3192 case VEX0F3A:
3193 m = 0x3;
80de6e00 3194 i.vex.bytes[0] = 0xc4;
7f399153
L		 3195 break;
3196 case XOP08:
5dd85c99
SP		 3197 m = 0x8;
3198 i.vex.bytes[0] = 0x8f;
7f399153
L		 3199 break;
3200 case XOP09:
f88c9eb0
SP		 3201 m = 0x9;
3202 i.vex.bytes[0] = 0x8f;
7f399153
L		 3203 break;
3204 case XOP0A:
f88c9eb0
SP		 3205 m = 0xa;
3206 i.vex.bytes[0] = 0x8f;
7f399153
L		 3207 break;
3208 default:
3209 abort ();
f88c9eb0 3210 }
c0f3af97 3211
c0f3af97
L		 3212 /* The high 3 bits of the second VEX byte are 1's compliment
3213 of RXB bits from REX. */
3214 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3215
3216 /* Check the REX.W bit. */
3217 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3218 if (i.tm.opcode_modifier.vexw == VEXW1)
3219 w = 1;
c0f3af97
L		 3220
3221 i.vex.bytes[2] = (w << 7
3222 | register_specifier << 3
3223 | vector_length << 2
3224 | implied_prefix);
3225 }
3226}
3227
43234a1e
L		 3228/* Build the EVEX prefix. */
3229
3230static void
3231build_evex_prefix (void)
3232{
3233 unsigned int register_specifier;
3234 unsigned int implied_prefix;
3235 unsigned int m, w;
3236 rex_byte vrex_used = 0;
3237
3238 /* Check register specifier. */
3239 if (i.vex.register_specifier)
3240 {
3241 gas_assert ((i.vrex & REX_X) == 0);
3242
3243 register_specifier = i.vex.register_specifier->reg_num;
3244 if ((i.vex.register_specifier->reg_flags & RegRex))
3245 register_specifier += 8;
3246 /* The upper 16 registers are encoded in the fourth byte of the
3247 EVEX prefix. */
3248 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3249 i.vex.bytes[3] = 0x8;
3250 register_specifier = ~register_specifier & 0xf;
3251 }
3252 else
3253 {
3254 register_specifier = 0xf;
3255
3256 /* Encode upper 16 vector index register in the fourth byte of
3257 the EVEX prefix. */
3258 if (!(i.vrex & REX_X))
3259 i.vex.bytes[3] = 0x8;
3260 else
3261 vrex_used |= REX_X;
3262 }
3263
3264 switch ((i.tm.base_opcode >> 8) & 0xff)
3265 {
3266 case 0:
3267 implied_prefix = 0;
3268 break;
3269 case DATA_PREFIX_OPCODE:
3270 implied_prefix = 1;
3271 break;
3272 case REPE_PREFIX_OPCODE:
3273 implied_prefix = 2;
3274 break;
3275 case REPNE_PREFIX_OPCODE:
3276 implied_prefix = 3;
3277 break;
3278 default:
3279 abort ();
3280 }
3281
3282 /* 4 byte EVEX prefix. */
3283 i.vex.length = 4;
3284 i.vex.bytes[0] = 0x62;
3285
3286 /* mmmm bits. */
3287 switch (i.tm.opcode_modifier.vexopcode)
3288 {
3289 case VEX0F:
3290 m = 1;
3291 break;
3292 case VEX0F38:
3293 m = 2;
3294 break;
3295 case VEX0F3A:
3296 m = 3;
3297 break;
3298 default:
3299 abort ();
3300 break;
3301 }
3302
3303 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3304 bits from REX. */
3305 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3306
3307 /* The fifth bit of the second EVEX byte is 1's compliment of the
3308 REX_R bit in VREX. */
3309 if (!(i.vrex & REX_R))
3310 i.vex.bytes[1] |= 0x10;
3311 else
3312 vrex_used |= REX_R;
3313
3314 if ((i.reg_operands + i.imm_operands) == i.operands)
3315 {
3316 /* When all operands are registers, the REX_X bit in REX is not
3317 used. We reuse it to encode the upper 16 registers, which is
3318 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3319 as 1's compliment. */
3320 if ((i.vrex & REX_B))
3321 {
3322 vrex_used |= REX_B;
3323 i.vex.bytes[1] &= ~0x40;
3324 }
3325 }
3326
3327 /* EVEX instructions shouldn't need the REX prefix. */
3328 i.vrex &= ~vrex_used;
3329 gas_assert (i.vrex == 0);
3330
3331 /* Check the REX.W bit. */
3332 w = (i.rex & REX_W) ? 1 : 0;
3333 if (i.tm.opcode_modifier.vexw)
3334 {
3335 if (i.tm.opcode_modifier.vexw == VEXW1)
3336 w = 1;
3337 }
3338 /* If w is not set it means we are dealing with WIG instruction. */
3339 else if (!w)
3340 {
3341 if (evexwig == evexw1)
3342 w = 1;
3343 }
3344
3345 /* Encode the U bit. */
3346 implied_prefix |= 0x4;
3347
3348 /* The third byte of the EVEX prefix. */
3349 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3350
3351 /* The fourth byte of the EVEX prefix. */
3352 /* The zeroing-masking bit. */
3353 if (i.mask && i.mask->zeroing)
3354 i.vex.bytes[3] |= 0x80;
3355
3356 /* Don't always set the broadcast bit if there is no RC. */
3357 if (!i.rounding)
3358 {
3359 /* Encode the vector length. */
3360 unsigned int vec_length;
3361
3362 switch (i.tm.opcode_modifier.evex)
3363 {
3364 case EVEXLIG: /* LL' is ignored */
3365 vec_length = evexlig << 5;
3366 break;
3367 case EVEX128:
3368 vec_length = 0 << 5;
3369 break;
3370 case EVEX256:
3371 vec_length = 1 << 5;
3372 break;
3373 case EVEX512:
3374 vec_length = 2 << 5;
3375 break;
3376 default:
3377 abort ();
3378 break;
3379 }
3380 i.vex.bytes[3] |= vec_length;
3381 /* Encode the broadcast bit. */
3382 if (i.broadcast)
3383 i.vex.bytes[3] |= 0x10;
3384 }
3385 else
3386 {
3387 if (i.rounding->type != saeonly)
3388 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3389 else
d3d3c6db 3390 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3391 }
3392
3393 if (i.mask && i.mask->mask)
3394 i.vex.bytes[3] |= i.mask->mask->reg_num;
3395}
3396
65da13b5
L		 3397static void
3398process_immext (void)
3399{
3400 expressionS *exp;
3401
4c692bc7
JB		 3402 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3403 && i.operands > 0)
65da13b5 3404 {
4c692bc7
JB		 3405 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3406 with an opcode suffix which is coded in the same place as an
3407 8-bit immediate field would be.
3408 Here we check those operands and remove them afterwards. */
65da13b5
L		 3409 unsigned int x;
3410
3411 for (x = 0; x < i.operands; x++)
4c692bc7 3412 if (register_number (i.op[x].regs) != x)
65da13b5 3413 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3414 register_prefix, i.op[x].regs->reg_name, x + 1,
3415 i.tm.name);
3416
3417 i.operands = 0;
65da13b5
L		 3418 }
3419
9916071f
AP		 3420 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3421 {
3422 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3423 suffix which is coded in the same place as an 8-bit immediate
3424 field would be.
3425 Here we check those operands and remove them afterwards. */
3426 unsigned int x;
3427
3428 if (i.operands != 3)
3429 abort();
3430
3431 for (x = 0; x < 2; x++)
3432 if (register_number (i.op[x].regs) != x)
3433 goto bad_register_operand;
3434
3435 /* Check for third operand for mwaitx/monitorx insn. */
3436 if (register_number (i.op[x].regs)
3437 != (x + (i.tm.extension_opcode == 0xfb)))
3438 {
3439bad_register_operand:
3440 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3441 register_prefix, i.op[x].regs->reg_name, x+1,
3442 i.tm.name);
3443 }
3444
3445 i.operands = 0;
3446 }
3447
c0f3af97 3448 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3449 which is coded in the same place as an 8-bit immediate field
3450 would be. Here we fake an 8-bit immediate operand from the
3451 opcode suffix stored in tm.extension_opcode.
3452
c1e679ec 3453 AVX instructions also use this encoding, for some of
c0f3af97 3454 3 argument instructions. */
65da13b5 3455
43234a1e 3456 gas_assert (i.imm_operands <= 1
7ab9ffdd 3457 && (i.operands <= 2
43234a1e
L		 3458 || ((i.tm.opcode_modifier.vex
3459 || i.tm.opcode_modifier.evex)
7ab9ffdd 3460 && i.operands <= 4)));
65da13b5
L		 3461
3462 exp = &im_expressions[i.imm_operands++];
3463 i.op[i.operands].imms = exp;
3464 i.types[i.operands] = imm8;
3465 i.operands++;
3466 exp->X_op = O_constant;
3467 exp->X_add_number = i.tm.extension_opcode;
3468 i.tm.extension_opcode = None;
3469}
3470
42164a71
L		 3471
3472static int
3473check_hle (void)
3474{
3475 switch (i.tm.opcode_modifier.hleprefixok)
3476 {
3477 default:
3478 abort ();
82c2def5 3479 case HLEPrefixNone:
165de32a
L		 3480 as_bad (_("invalid instruction `%s' after `%s'"),
3481 i.tm.name, i.hle_prefix);
42164a71 3482 return 0;
82c2def5 3483 case HLEPrefixLock:
42164a71
L		 3484 if (i.prefix[LOCK_PREFIX])
3485 return 1;
165de32a 3486 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3487 return 0;
82c2def5 3488 case HLEPrefixAny:
42164a71 3489 return 1;
82c2def5 3490 case HLEPrefixRelease:
42164a71
L		 3491 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3492 {
3493 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3494 i.tm.name);
3495 return 0;
3496 }
3497 if (i.mem_operands == 0
3498 || !operand_type_check (i.types[i.operands - 1], anymem))
3499 {
3500 as_bad (_("memory destination needed for instruction `%s'"
3501 " after `xrelease'"), i.tm.name);
3502 return 0;
3503 }
3504 return 1;
3505 }
3506}
3507
252b5132
RH		 3508/* This is the guts of the machine-dependent assembler. LINE points to a
3509 machine dependent instruction. This function is supposed to emit
3510 the frags/bytes it assembles to. */
3511
3512void
65da13b5 3513md_assemble (char *line)
252b5132 3514{
40fb9820 3515 unsigned int j;
252b5132 3516 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 3517 const insn_template *t;
252b5132 3518
47926f60 3519 /* Initialize globals. */
252b5132
RH		 3520 memset (&i, '\0', sizeof (i));
3521 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3522 i.reloc[j] = NO_RELOC;
252b5132
RH		 3523 memset (disp_expressions, '\0', sizeof (disp_expressions));
3524 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3525 save_stack_p = save_stack;
252b5132
RH		 3526
3527 /* First parse an instruction mnemonic & call i386_operand for the operands.
3528 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3529 start of a (possibly prefixed) mnemonic. */
252b5132 3530
29b0f896
AM		 3531 line = parse_insn (line, mnemonic);
3532 if (line == NULL)
3533 return;
252b5132 3534
29b0f896 3535 line = parse_operands (line, mnemonic);
ee86248c 3536 this_operand = -1;
29b0f896
AM		 3537 if (line == NULL)
3538 return;
252b5132 3539
29b0f896
AM		 3540 /* Now we've parsed the mnemonic into a set of templates, and have the
3541 operands at hand. */
3542
3543 /* All intel opcodes have reversed operands except for "bound" and
3544 "enter". We also don't reverse intersegment "jmp" and "call"
3545 instructions with 2 immediate operands so that the immediate segment
050dfa73 3546 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3547 if (intel_syntax
3548 && i.operands > 1
29b0f896 3549 && (strcmp (mnemonic, "bound") != 0)
30123838 3550 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3551 && !(operand_type_check (i.types[0], imm)
3552 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3553 swap_operands ();
3554
ec56d5c0
JB		 3555 /* The order of the immediates should be reversed
3556 for 2 immediates extrq and insertq instructions */
3557 if (i.imm_operands == 2
3558 && (strcmp (mnemonic, "extrq") == 0
3559 || strcmp (mnemonic, "insertq") == 0))
3560 swap_2_operands (0, 1);
3561
29b0f896
AM		 3562 if (i.imm_operands)
3563 optimize_imm ();
3564
b300c311
L		 3565 /* Don't optimize displacement for movabs since it only takes 64bit
3566 displacement. */
3567 if (i.disp_operands
a501d77e 3568 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3569 && (flag_code != CODE_64BIT
3570 || strcmp (mnemonic, "movabs") != 0))
3571 optimize_disp ();
29b0f896
AM		 3572
3573 /* Next, we find a template that matches the given insn,
3574 making sure the overlap of the given operands types is consistent
3575 with the template operand types. */
252b5132 3576
fa99fab2 3577 if (!(t = match_template ()))
29b0f896 3578 return;
252b5132 3579
7bab8ab5 3580 if (sse_check != check_none
81f8a913 3581 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3582 && (i.tm.cpu_flags.bitfield.cpusse
3583 || i.tm.cpu_flags.bitfield.cpusse2
3584 || i.tm.cpu_flags.bitfield.cpusse3
3585 || i.tm.cpu_flags.bitfield.cpussse3
3586 || i.tm.cpu_flags.bitfield.cpusse4_1
3587 || i.tm.cpu_flags.bitfield.cpusse4_2))
3588 {
7bab8ab5 3589 (sse_check == check_warning
daf50ae7
L		 3590 ? as_warn
3591 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3592 }
3593
321fd21e
L		 3594 /* Zap movzx and movsx suffix. The suffix has been set from
3595 "word ptr" or "byte ptr" on the source operand in Intel syntax
3596 or extracted from mnemonic in AT&T syntax. But we'll use
3597 the destination register to choose the suffix for encoding. */
3598 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3599 {
321fd21e
L		 3600 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3601 there is no suffix, the default will be byte extension. */
3602 if (i.reg_operands != 2
3603 && !i.suffix
7ab9ffdd 3604 && intel_syntax)
321fd21e
L		 3605 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3606
3607 i.suffix = 0;
cd61ebfe 3608 }
24eab124 3609
40fb9820 3610 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3611 if (!add_prefix (FWAIT_OPCODE))
3612 return;
252b5132 3613
d5de92cf
L		 3614 /* Check if REP prefix is OK. */
3615 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3616 {
3617 as_bad (_("invalid instruction `%s' after `%s'"),
3618 i.tm.name, i.rep_prefix);
3619 return;
3620 }
3621
c1ba0266
L		 3622 /* Check for lock without a lockable instruction. Destination operand
3623 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3624 if (i.prefix[LOCK_PREFIX]
3625 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3626 || i.mem_operands == 0
3627 || (i.tm.base_opcode != 0x86
3628 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3629 {
3630 as_bad (_("expecting lockable instruction after `lock'"));
3631 return;
3632 }
3633
42164a71 3634 /* Check if HLE prefix is OK. */
165de32a 3635 if (i.hle_prefix && !check_hle ())
42164a71
L		 3636 return;
3637
7e8b059b
L		 3638 /* Check BND prefix. */
3639 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3640 as_bad (_("expecting valid branch instruction after `bnd'"));
3641
3642 if (i.tm.cpu_flags.bitfield.cpumpx
3643 && flag_code == CODE_64BIT
3644 && i.prefix[ADDR_PREFIX])
3645 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3646
3647 /* Insert BND prefix. */
3648 if (add_bnd_prefix
3649 && i.tm.opcode_modifier.bndprefixok
3650 && !i.prefix[BND_PREFIX])
3651 add_prefix (BND_PREFIX_OPCODE);
3652
29b0f896 3653 /* Check string instruction segment overrides. */
40fb9820 3654 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3655 {
3656 if (!check_string ())
5dd0794d 3657 return;
fc0763e6 3658 i.disp_operands = 0;
29b0f896 3659 }
5dd0794d 3660
29b0f896
AM		 3661 if (!process_suffix ())
3662 return;
e413e4e9 3663
bc0844ae
L		 3664 /* Update operand types. */
3665 for (j = 0; j < i.operands; j++)
3666 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3667
29b0f896
AM		 3668 /* Make still unresolved immediate matches conform to size of immediate
3669 given in i.suffix. */
3670 if (!finalize_imm ())
3671 return;
252b5132 3672
40fb9820 3673 if (i.types[0].bitfield.imm1)
29b0f896 3674 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3675
9afe6eb8
L		 3676 /* We only need to check those implicit registers for instructions
3677 with 3 operands or less. */
3678 if (i.operands <= 3)
3679 for (j = 0; j < i.operands; j++)
3680 if (i.types[j].bitfield.inoutportreg
3681 || i.types[j].bitfield.shiftcount
3682 || i.types[j].bitfield.acc
3683 || i.types[j].bitfield.floatacc)
3684 i.reg_operands--;
40fb9820 3685
c0f3af97
L		 3686 /* ImmExt should be processed after SSE2AVX. */
3687 if (!i.tm.opcode_modifier.sse2avx
3688 && i.tm.opcode_modifier.immext)
65da13b5 3689 process_immext ();
252b5132 3690
29b0f896
AM		 3691 /* For insns with operands there are more diddles to do to the opcode. */
3692 if (i.operands)
3693 {
3694 if (!process_operands ())
3695 return;
3696 }
40fb9820 3697 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3698 {
3699 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3700 as_warn (_("translating to `%sp'"), i.tm.name);
3701 }
252b5132 3702
9e5e5283
L		 3703 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3704 {
3705 if (flag_code == CODE_16BIT)
3706 {
3707 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3708 i.tm.name);
3709 return;
3710 }
c0f3af97 3711
9e5e5283
L		 3712 if (i.tm.opcode_modifier.vex)
3713 build_vex_prefix (t);
3714 else
3715 build_evex_prefix ();
3716 }
43234a1e 3717
5dd85c99
SP		 3718 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3719 instructions may define INT_OPCODE as well, so avoid this corner
3720 case for those instructions that use MODRM. */
3721 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3722 && !i.tm.opcode_modifier.modrm
3723 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3724 {
3725 i.tm.base_opcode = INT3_OPCODE;
3726 i.imm_operands = 0;
3727 }
252b5132 3728
40fb9820
L		 3729 if ((i.tm.opcode_modifier.jump
3730 || i.tm.opcode_modifier.jumpbyte
3731 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3732 && i.op[0].disps->X_op == O_constant)
3733 {
3734 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3735 the absolute address given by the constant. Since ix86 jumps and
3736 calls are pc relative, we need to generate a reloc. */
3737 i.op[0].disps->X_add_symbol = &abs_symbol;
3738 i.op[0].disps->X_op = O_symbol;
3739 }
252b5132 3740
40fb9820 3741 if (i.tm.opcode_modifier.rex64)
161a04f6 3742 i.rex |= REX_W;
252b5132 3743
29b0f896
AM		 3744 /* For 8 bit registers we need an empty rex prefix. Also if the
3745 instruction already has a prefix, we need to convert old
3746 registers to new ones. */
773f551c 3747
40fb9820 3748 if ((i.types[0].bitfield.reg8
29b0f896 3749 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3750 || (i.types[1].bitfield.reg8
29b0f896 3751 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3752 || ((i.types[0].bitfield.reg8
3753 || i.types[1].bitfield.reg8)
29b0f896
AM		 3754 && i.rex != 0))
3755 {
3756 int x;
726c5dcd 3757
29b0f896
AM		 3758 i.rex |= REX_OPCODE;
3759 for (x = 0; x < 2; x++)
3760 {
3761 /* Look for 8 bit operand that uses old registers. */
40fb9820 3762 if (i.types[x].bitfield.reg8
29b0f896 3763 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3764 {
29b0f896
AM		 3765 /* In case it is "hi" register, give up. */
3766 if (i.op[x].regs->reg_num > 3)
a540244d 3767 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3768 "instruction requiring REX prefix."),
a540244d 3769 register_prefix, i.op[x].regs->reg_name);
773f551c 3770
29b0f896
AM		 3771 /* Otherwise it is equivalent to the extended register.
3772 Since the encoding doesn't change this is merely
3773 cosmetic cleanup for debug output. */
3774
3775 i.op[x].regs = i.op[x].regs + 8;
773f551c 3776 }
29b0f896
AM		 3777 }
3778 }
773f551c 3779
7ab9ffdd 3780 if (i.rex != 0)
29b0f896
AM		 3781 add_prefix (REX_OPCODE | i.rex);
3782
3783 /* We are ready to output the insn. */
3784 output_insn ();
3785}
3786
3787static char *
e3bb37b5 3788parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3789{
3790 char *l = line;
3791 char *token_start = l;
3792 char *mnem_p;
5c6af06e 3793 int supported;
d3ce72d0 3794 const insn_template *t;
b6169b20 3795 char *dot_p = NULL;
29b0f896 3796
29b0f896
AM		 3797 while (1)
3798 {
3799 mnem_p = mnemonic;
3800 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3801 {
b6169b20
L		 3802 if (*mnem_p == '.')
3803 dot_p = mnem_p;
29b0f896
AM		 3804 mnem_p++;
3805 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3806 {
29b0f896
AM		 3807 as_bad (_("no such instruction: `%s'"), token_start);
3808 return NULL;
3809 }
3810 l++;
3811 }
3812 if (!is_space_char (*l)
3813 && *l != END_OF_INSN
e44823cf
JB		 3814 && (intel_syntax
3815 || (*l != PREFIX_SEPARATOR
3816 && *l != ',')))
29b0f896
AM		 3817 {
3818 as_bad (_("invalid character %s in mnemonic"),
3819 output_invalid (*l));
3820 return NULL;
3821 }
3822 if (token_start == l)
3823 {
e44823cf 3824 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3825 as_bad (_("expecting prefix; got nothing"));
3826 else
3827 as_bad (_("expecting mnemonic; got nothing"));
3828 return NULL;
3829 }
45288df1 3830
29b0f896 3831 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3832 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3833
29b0f896
AM		 3834 if (*l != END_OF_INSN
3835 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3836 && current_templates
40fb9820 3837 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3838 {
c6fb90c8 3839 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3840 {
3841 as_bad ((flag_code != CODE_64BIT
3842 ? _("`%s' is only supported in 64-bit mode")
3843 : _("`%s' is not supported in 64-bit mode")),
3844 current_templates->start->name);
3845 return NULL;
3846 }
29b0f896
AM		 3847 /* If we are in 16-bit mode, do not allow addr16 or data16.
3848 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3849 if ((current_templates->start->opcode_modifier.size16
3850 || current_templates->start->opcode_modifier.size32)
29b0f896 3851 && flag_code != CODE_64BIT
40fb9820 3852 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3853 ^ (flag_code == CODE_16BIT)))
3854 {
3855 as_bad (_("redundant %s prefix"),
3856 current_templates->start->name);
3857 return NULL;
45288df1 3858 }
29b0f896
AM		 3859 /* Add prefix, checking for repeated prefixes. */
3860 switch (add_prefix (current_templates->start->base_opcode))
3861 {
c32fa91d 3862 case PREFIX_EXIST:
29b0f896 3863 return NULL;
c32fa91d 3864 case PREFIX_REP:
42164a71 3865 if (current_templates->start->cpu_flags.bitfield.cpuhle)
165de32a 3866 i.hle_prefix = current_templates->start->name;
7e8b059b
L		 3867 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3868 i.bnd_prefix = current_templates->start->name;
42164a71 3869 else
d5de92cf 3870 i.rep_prefix = current_templates->start->name;
29b0f896 3871 break;
c32fa91d
L		 3872 default:
3873 break;
29b0f896
AM		 3874 }
3875 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3876 token_start = ++l;
3877 }
3878 else
3879 break;
3880 }
45288df1 3881
30a55f88 3882 if (!current_templates)
b6169b20 3883 {
f8a5c266
L		 3884 /* Check if we should swap operand or force 32bit displacement in
3885 encoding. */
30a55f88
L		 3886 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3887 i.swap_operand = 1;
8d63c93e 3888 else if (mnem_p - 3 == dot_p
a501d77e
L		 3889 && dot_p[1] == 'd'
3890 && dot_p[2] == '8')
3891 i.disp_encoding = disp_encoding_8bit;
8d63c93e 3892 else if (mnem_p - 4 == dot_p
f8a5c266
L		 3893 && dot_p[1] == 'd'
3894 && dot_p[2] == '3'
3895 && dot_p[3] == '2')
a501d77e 3896 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 3897 else
3898 goto check_suffix;
3899 mnem_p = dot_p;
3900 *dot_p = '\0';
d3ce72d0 3901 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3902 }
3903
29b0f896
AM		 3904 if (!current_templates)
3905 {
b6169b20 3906check_suffix:
29b0f896
AM		 3907 /* See if we can get a match by trimming off a suffix. */
3908 switch (mnem_p[-1])
3909 {
3910 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3911 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3912 i.suffix = SHORT_MNEM_SUFFIX;
3913 else
29b0f896
AM		 3914 case BYTE_MNEM_SUFFIX:
3915 case QWORD_MNEM_SUFFIX:
3916 i.suffix = mnem_p[-1];
3917 mnem_p[-1] = '\0';
d3ce72d0
NC		 3918 current_templates = (const templates *) hash_find (op_hash,
3919 mnemonic);
29b0f896
AM		 3920 break;
3921 case SHORT_MNEM_SUFFIX:
3922 case LONG_MNEM_SUFFIX:
3923 if (!intel_syntax)
3924 {
3925 i.suffix = mnem_p[-1];
3926 mnem_p[-1] = '\0';
d3ce72d0
NC		 3927 current_templates = (const templates *) hash_find (op_hash,
3928 mnemonic);
29b0f896
AM		 3929 }
3930 break;
252b5132 3931
29b0f896
AM		 3932 /* Intel Syntax. */
3933 case 'd':
3934 if (intel_syntax)
3935 {
9306ca4a 3936 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3937 i.suffix = SHORT_MNEM_SUFFIX;
3938 else
3939 i.suffix = LONG_MNEM_SUFFIX;
3940 mnem_p[-1] = '\0';
d3ce72d0
NC		 3941 current_templates = (const templates *) hash_find (op_hash,
3942 mnemonic);
29b0f896
AM		 3943 }
3944 break;
3945 }
3946 if (!current_templates)
3947 {
3948 as_bad (_("no such instruction: `%s'"), token_start);
3949 return NULL;
3950 }
3951 }
252b5132 3952
40fb9820
L		 3953 if (current_templates->start->opcode_modifier.jump
3954 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3955 {
3956 /* Check for a branch hint. We allow ",pt" and ",pn" for
3957 predict taken and predict not taken respectively.
3958 I'm not sure that branch hints actually do anything on loop
3959 and jcxz insns (JumpByte) for current Pentium4 chips. They
3960 may work in the future and it doesn't hurt to accept them
3961 now. */
3962 if (l[0] == ',' && l[1] == 'p')
3963 {
3964 if (l[2] == 't')
3965 {
3966 if (!add_prefix (DS_PREFIX_OPCODE))
3967 return NULL;
3968 l += 3;
3969 }
3970 else if (l[2] == 'n')
3971 {
3972 if (!add_prefix (CS_PREFIX_OPCODE))
3973 return NULL;
3974 l += 3;
3975 }
3976 }
3977 }
3978 /* Any other comma loses. */
3979 if (*l == ',')
3980 {
3981 as_bad (_("invalid character %s in mnemonic"),
3982 output_invalid (*l));
3983 return NULL;
3984 }
252b5132 3985
29b0f896 3986 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3987 supported = 0;
3988 for (t = current_templates->start; t < current_templates->end; ++t)
3989 {
c0f3af97
L		 3990 supported |= cpu_flags_match (t);
3991 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3992 goto skip;
5c6af06e 3993 }
3629bb00 3994
c0f3af97 3995 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3996 {
3997 as_bad (flag_code == CODE_64BIT
3998 ? _("`%s' is not supported in 64-bit mode")
3999 : _("`%s' is only supported in 64-bit mode"),
4000 current_templates->start->name);
4001 return NULL;
4002 }
c0f3af97 4003 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 4004 {
3629bb00 4005 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 4006 current_templates->start->name,
41aacd83 4007 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 4008 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4009 return NULL;
29b0f896 4010 }
3629bb00
L		 4011
4012skip:
4013 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 4014 && (flag_code != CODE_16BIT))
29b0f896
AM		 4015 {
4016 as_warn (_("use .code16 to ensure correct addressing mode"));
4017 }
252b5132 4018
29b0f896
AM		 4019 return l;
4020}
252b5132 4021
29b0f896 4022static char *
e3bb37b5 4023parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 4024{
4025 char *token_start;
3138f287 4026
29b0f896
AM		 4027 /* 1 if operand is pending after ','. */
4028 unsigned int expecting_operand = 0;
252b5132 4029
29b0f896
AM		 4030 /* Non-zero if operand parens not balanced. */
4031 unsigned int paren_not_balanced;
4032
4033 while (*l != END_OF_INSN)
4034 {
4035 /* Skip optional white space before operand. */
4036 if (is_space_char (*l))
4037 ++l;
d02603dc 4038 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
29b0f896
AM		 4039 {
4040 as_bad (_("invalid character %s before operand %d"),
4041 output_invalid (*l),
4042 i.operands + 1);
4043 return NULL;
4044 }
d02603dc 4045 token_start = l; /* After white space. */
29b0f896
AM		 4046 paren_not_balanced = 0;
4047 while (paren_not_balanced || *l != ',')
4048 {
4049 if (*l == END_OF_INSN)
4050 {
4051 if (paren_not_balanced)
4052 {
4053 if (!intel_syntax)
4054 as_bad (_("unbalanced parenthesis in operand %d."),
4055 i.operands + 1);
4056 else
4057 as_bad (_("unbalanced brackets in operand %d."),
4058 i.operands + 1);
4059 return NULL;
4060 }
4061 else
4062 break; /* we are done */
4063 }
d02603dc 4064 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
29b0f896
AM		 4065 {
4066 as_bad (_("invalid character %s in operand %d"),
4067 output_invalid (*l),
4068 i.operands + 1);
4069 return NULL;
4070 }
4071 if (!intel_syntax)
4072 {
4073 if (*l == '(')
4074 ++paren_not_balanced;
4075 if (*l == ')')
4076 --paren_not_balanced;
4077 }
4078 else
4079 {
4080 if (*l == '[')
4081 ++paren_not_balanced;
4082 if (*l == ']')
4083 --paren_not_balanced;
4084 }
4085 l++;
4086 }
4087 if (l != token_start)
4088 { /* Yes, we've read in another operand. */
4089 unsigned int operand_ok;
4090 this_operand = i.operands++;
7d5e4556 4091 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4092 if (i.operands > MAX_OPERANDS)
4093 {
4094 as_bad (_("spurious operands; (%d operands/instruction max)"),
4095 MAX_OPERANDS);
4096 return NULL;
4097 }
4098 /* Now parse operand adding info to 'i' as we go along. */
4099 END_STRING_AND_SAVE (l);
4100
4101 if (intel_syntax)
4102 operand_ok =
4103 i386_intel_operand (token_start,
4104 intel_float_operand (mnemonic));
4105 else
a7619375 4106 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4107
4108 RESTORE_END_STRING (l);
4109 if (!operand_ok)
4110 return NULL;
4111 }
4112 else
4113 {
4114 if (expecting_operand)
4115 {
4116 expecting_operand_after_comma:
4117 as_bad (_("expecting operand after ','; got nothing"));
4118 return NULL;
4119 }
4120 if (*l == ',')
4121 {
4122 as_bad (_("expecting operand before ','; got nothing"));
4123 return NULL;
4124 }
4125 }
7f3f1ea2 4126
29b0f896
AM		 4127 /* Now *l must be either ',' or END_OF_INSN. */
4128 if (*l == ',')
4129 {
4130 if (*++l == END_OF_INSN)
4131 {
4132 /* Just skip it, if it's \n complain. */
4133 goto expecting_operand_after_comma;
4134 }
4135 expecting_operand = 1;
4136 }
4137 }
4138 return l;
4139}
7f3f1ea2 4140
050dfa73 4141static void
4d456e3d 4142swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4143{
4144 union i386_op temp_op;
40fb9820 4145 i386_operand_type temp_type;
050dfa73 4146 enum bfd_reloc_code_real temp_reloc;
4eed87de 4147
050dfa73
MM		 4148 temp_type = i.types[xchg2];
4149 i.types[xchg2] = i.types[xchg1];
4150 i.types[xchg1] = temp_type;
4151 temp_op = i.op[xchg2];
4152 i.op[xchg2] = i.op[xchg1];
4153 i.op[xchg1] = temp_op;
4154 temp_reloc = i.reloc[xchg2];
4155 i.reloc[xchg2] = i.reloc[xchg1];
4156 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4157
4158 if (i.mask)
4159 {
4160 if (i.mask->operand == xchg1)
4161 i.mask->operand = xchg2;
4162 else if (i.mask->operand == xchg2)
4163 i.mask->operand = xchg1;
4164 }
4165 if (i.broadcast)
4166 {
4167 if (i.broadcast->operand == xchg1)
4168 i.broadcast->operand = xchg2;
4169 else if (i.broadcast->operand == xchg2)
4170 i.broadcast->operand = xchg1;
4171 }
4172 if (i.rounding)
4173 {
4174 if (i.rounding->operand == xchg1)
4175 i.rounding->operand = xchg2;
4176 else if (i.rounding->operand == xchg2)
4177 i.rounding->operand = xchg1;
4178 }
050dfa73
MM		 4179}
4180
29b0f896 4181static void
e3bb37b5 4182swap_operands (void)
29b0f896 4183{
b7c61d9a 4184 switch (i.operands)
050dfa73 4185 {
c0f3af97 4186 case 5:
b7c61d9a 4187 case 4:
4d456e3d 4188 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 4189 case 3:
4190 case 2:
4d456e3d 4191 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4192 break;
4193 default:
4194 abort ();
29b0f896 4195 }
29b0f896
AM		 4196
4197 if (i.mem_operands == 2)
4198 {
4199 const seg_entry *temp_seg;
4200 temp_seg = i.seg[0];
4201 i.seg[0] = i.seg[1];
4202 i.seg[1] = temp_seg;
4203 }
4204}
252b5132 4205
29b0f896
AM		 4206/* Try to ensure constant immediates are represented in the smallest
4207 opcode possible. */
4208static void
e3bb37b5 4209optimize_imm (void)
29b0f896
AM		 4210{
4211 char guess_suffix = 0;
4212 int op;
252b5132 4213
29b0f896
AM		 4214 if (i.suffix)
4215 guess_suffix = i.suffix;
4216 else if (i.reg_operands)
4217 {
4218 /* Figure out a suffix from the last register operand specified.
4219 We can't do this properly yet, ie. excluding InOutPortReg,
4220 but the following works for instructions with immediates.
4221 In any case, we can't set i.suffix yet. */
4222 for (op = i.operands; --op >= 0;)
40fb9820 4223 if (i.types[op].bitfield.reg8)
7ab9ffdd 4224 {
40fb9820
L		 4225 guess_suffix = BYTE_MNEM_SUFFIX;
4226 break;
4227 }
4228 else if (i.types[op].bitfield.reg16)
252b5132 4229 {
40fb9820
L		 4230 guess_suffix = WORD_MNEM_SUFFIX;
4231 break;
4232 }
4233 else if (i.types[op].bitfield.reg32)
4234 {
4235 guess_suffix = LONG_MNEM_SUFFIX;
4236 break;
4237 }
4238 else if (i.types[op].bitfield.reg64)
4239 {
4240 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4241 break;
252b5132 4242 }
29b0f896
AM		 4243 }
4244 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4245 guess_suffix = WORD_MNEM_SUFFIX;
4246
4247 for (op = i.operands; --op >= 0;)
40fb9820 4248 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4249 {
4250 switch (i.op[op].imms->X_op)
252b5132 4251 {
29b0f896
AM		 4252 case O_constant:
4253 /* If a suffix is given, this operand may be shortened. */
4254 switch (guess_suffix)
252b5132 4255 {
29b0f896 4256 case LONG_MNEM_SUFFIX:
40fb9820
L		 4257 i.types[op].bitfield.imm32 = 1;
4258 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4259 break;
4260 case WORD_MNEM_SUFFIX:
40fb9820
L		 4261 i.types[op].bitfield.imm16 = 1;
4262 i.types[op].bitfield.imm32 = 1;
4263 i.types[op].bitfield.imm32s = 1;
4264 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4265 break;
4266 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4267 i.types[op].bitfield.imm8 = 1;
4268 i.types[op].bitfield.imm8s = 1;
4269 i.types[op].bitfield.imm16 = 1;
4270 i.types[op].bitfield.imm32 = 1;
4271 i.types[op].bitfield.imm32s = 1;
4272 i.types[op].bitfield.imm64 = 1;
29b0f896 4273 break;
252b5132 4274 }
252b5132 4275
29b0f896
AM		 4276 /* If this operand is at most 16 bits, convert it
4277 to a signed 16 bit number before trying to see
4278 whether it will fit in an even smaller size.
4279 This allows a 16-bit operand such as $0xffe0 to
4280 be recognised as within Imm8S range. */
40fb9820 4281 if ((i.types[op].bitfield.imm16)
29b0f896 4282 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4283 {
29b0f896
AM		 4284 i.op[op].imms->X_add_number =
4285 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4286 }
a28def75
L		 4287#ifdef BFD64
4288 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
40fb9820 4289 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4290 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4291 == 0))
4292 {
4293 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4294 ^ ((offsetT) 1 << 31))
4295 - ((offsetT) 1 << 31));
4296 }
a28def75 4297#endif
40fb9820 4298 i.types[op]
c6fb90c8
L		 4299 = operand_type_or (i.types[op],
4300 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4301
29b0f896
AM		 4302 /* We must avoid matching of Imm32 templates when 64bit
4303 only immediate is available. */
4304 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4305 i.types[op].bitfield.imm32 = 0;
29b0f896 4306 break;
252b5132 4307
29b0f896
AM		 4308 case O_absent:
4309 case O_register:
4310 abort ();
4311
4312 /* Symbols and expressions. */
4313 default:
9cd96992
JB		 4314 /* Convert symbolic operand to proper sizes for matching, but don't
4315 prevent matching a set of insns that only supports sizes other
4316 than those matching the insn suffix. */
4317 {
40fb9820 4318 i386_operand_type mask, allowed;
d3ce72d0 4319 const insn_template *t;
9cd96992 4320
0dfbf9d7
L		 4321 operand_type_set (&mask, 0);
4322 operand_type_set (&allowed, 0);
40fb9820 4323
4eed87de
AM		 4324 for (t = current_templates->start;
4325 t < current_templates->end;
4326 ++t)
c6fb90c8
L		 4327 allowed = operand_type_or (allowed,
4328 t->operand_types[op]);
9cd96992
JB		 4329 switch (guess_suffix)
4330 {
4331 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4332 mask.bitfield.imm64 = 1;
4333 mask.bitfield.imm32s = 1;
9cd96992
JB		 4334 break;
4335 case LONG_MNEM_SUFFIX:
40fb9820 4336 mask.bitfield.imm32 = 1;
9cd96992
JB		 4337 break;
4338 case WORD_MNEM_SUFFIX:
40fb9820 4339 mask.bitfield.imm16 = 1;
9cd96992
JB		 4340 break;
4341 case BYTE_MNEM_SUFFIX:
40fb9820 4342 mask.bitfield.imm8 = 1;
9cd96992
JB		 4343 break;
4344 default:
9cd96992
JB		 4345 break;
4346 }
c6fb90c8 4347 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4348 if (!operand_type_all_zero (&allowed))
c6fb90c8 4349 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4350 }
29b0f896 4351 break;
252b5132 4352 }
29b0f896
AM		 4353 }
4354}
47926f60 4355
29b0f896
AM		 4356/* Try to use the smallest displacement type too. */
4357static void
e3bb37b5 4358optimize_disp (void)
29b0f896
AM		 4359{
4360 int op;
3e73aa7c 4361
29b0f896 4362 for (op = i.operands; --op >= 0;)
40fb9820 4363 if (operand_type_check (i.types[op], disp))
252b5132 4364 {
b300c311 4365 if (i.op[op].disps->X_op == O_constant)
252b5132 4366 {
91d6fa6a 4367 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4368
40fb9820 4369 if (i.types[op].bitfield.disp16
91d6fa6a 4370 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4371 {
4372 /* If this operand is at most 16 bits, convert
4373 to a signed 16 bit number and don't use 64bit
4374 displacement. */
91d6fa6a 4375 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4376 i.types[op].bitfield.disp64 = 0;
b300c311 4377 }
a28def75
L		 4378#ifdef BFD64
4379 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
40fb9820 4380 if (i.types[op].bitfield.disp32
91d6fa6a 4381 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4382 {
4383 /* If this operand is at most 32 bits, convert
4384 to a signed 32 bit number and don't use 64bit
4385 displacement. */
91d6fa6a
NC		 4386 op_disp &= (((offsetT) 2 << 31) - 1);
4387 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4388 i.types[op].bitfield.disp64 = 0;
b300c311 4389 }
a28def75 4390#endif
91d6fa6a 4391 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4392 {
40fb9820
L		 4393 i.types[op].bitfield.disp8 = 0;
4394 i.types[op].bitfield.disp16 = 0;
4395 i.types[op].bitfield.disp32 = 0;
4396 i.types[op].bitfield.disp32s = 0;
4397 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4398 i.op[op].disps = 0;
4399 i.disp_operands--;
4400 }
4401 else if (flag_code == CODE_64BIT)
4402 {
91d6fa6a 4403 if (fits_in_signed_long (op_disp))
28a9d8f5 4404 {
40fb9820
L		 4405 i.types[op].bitfield.disp64 = 0;
4406 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4407 }
0e1147d9 4408 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4409 && fits_in_unsigned_long (op_disp))
40fb9820 4410 i.types[op].bitfield.disp32 = 1;
b300c311 4411 }
40fb9820
L		 4412 if ((i.types[op].bitfield.disp32
4413 || i.types[op].bitfield.disp32s
4414 || i.types[op].bitfield.disp16)
91d6fa6a 4415 && fits_in_signed_byte (op_disp))
40fb9820 4416 i.types[op].bitfield.disp8 = 1;
252b5132 4417 }
67a4f2b7
AO		 4418 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4419 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4420 {
4421 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4422 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4423 i.types[op].bitfield.disp8 = 0;
4424 i.types[op].bitfield.disp16 = 0;
4425 i.types[op].bitfield.disp32 = 0;
4426 i.types[op].bitfield.disp32s = 0;
4427 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4428 }
4429 else
b300c311 4430 /* We only support 64bit displacement on constants. */
40fb9820 4431 i.types[op].bitfield.disp64 = 0;
252b5132 4432 }
29b0f896
AM		 4433}
4434
6c30d220
L		 4435/* Check if operands are valid for the instruction. */
4436
4437static int
4438check_VecOperands (const insn_template *t)
4439{
43234a1e
L		 4440 unsigned int op;
4441
6c30d220
L		 4442 /* Without VSIB byte, we can't have a vector register for index. */
4443 if (!t->opcode_modifier.vecsib
4444 && i.index_reg
4445 && (i.index_reg->reg_type.bitfield.regxmm
43234a1e
L		 4446 || i.index_reg->reg_type.bitfield.regymm
4447 || i.index_reg->reg_type.bitfield.regzmm))
6c30d220
L		 4448 {
4449 i.error = unsupported_vector_index_register;
4450 return 1;
4451 }
4452
ad8ecc81
MZ		 4453 /* Check if default mask is allowed. */
4454 if (t->opcode_modifier.nodefmask
4455 && (!i.mask || i.mask->mask->reg_num == 0))
4456 {
4457 i.error = no_default_mask;
4458 return 1;
4459 }
4460
7bab8ab5
JB		 4461 /* For VSIB byte, we need a vector register for index, and all vector
4462 registers must be distinct. */
4463 if (t->opcode_modifier.vecsib)
4464 {
4465 if (!i.index_reg
6c30d220
L		 4466 || !((t->opcode_modifier.vecsib == VecSIB128
4467 && i.index_reg->reg_type.bitfield.regxmm)
4468 || (t->opcode_modifier.vecsib == VecSIB256
43234a1e
L		 4469 && i.index_reg->reg_type.bitfield.regymm)
4470 || (t->opcode_modifier.vecsib == VecSIB512
4471 && i.index_reg->reg_type.bitfield.regzmm)))
7bab8ab5
JB		 4472 {
4473 i.error = invalid_vsib_address;
4474 return 1;
4475 }
4476
43234a1e
L		 4477 gas_assert (i.reg_operands == 2 || i.mask);
4478 if (i.reg_operands == 2 && !i.mask)
4479 {
4480 gas_assert (i.types[0].bitfield.regxmm
7c84a0ca 4481 || i.types[0].bitfield.regymm);
43234a1e 4482 gas_assert (i.types[2].bitfield.regxmm
7c84a0ca 4483 || i.types[2].bitfield.regymm);
43234a1e
L		 4484 if (operand_check == check_none)
4485 return 0;
4486 if (register_number (i.op[0].regs)
4487 != register_number (i.index_reg)
4488 && register_number (i.op[2].regs)
4489 != register_number (i.index_reg)
4490 && register_number (i.op[0].regs)
4491 != register_number (i.op[2].regs))
4492 return 0;
4493 if (operand_check == check_error)
4494 {
4495 i.error = invalid_vector_register_set;
4496 return 1;
4497 }
4498 as_warn (_("mask, index, and destination registers should be distinct"));
4499 }
8444f82a
MZ		 4500 else if (i.reg_operands == 1 && i.mask)
4501 {
4502 if ((i.types[1].bitfield.regymm
4503 || i.types[1].bitfield.regzmm)
4504 && (register_number (i.op[1].regs)
4505 == register_number (i.index_reg)))
4506 {
4507 if (operand_check == check_error)
4508 {
4509 i.error = invalid_vector_register_set;
4510 return 1;
4511 }
4512 if (operand_check != check_none)
4513 as_warn (_("index and destination registers should be distinct"));
4514 }
4515 }
43234a1e 4516 }
7bab8ab5 4517
43234a1e
L		 4518 /* Check if broadcast is supported by the instruction and is applied
4519 to the memory operand. */
4520 if (i.broadcast)
4521 {
4522 int broadcasted_opnd_size;
4523
4524 /* Check if specified broadcast is supported in this instruction,
4525 and it's applied to memory operand of DWORD or QWORD type,
4526 depending on VecESize. */
4527 if (i.broadcast->type != t->opcode_modifier.broadcast
4528 || !i.types[i.broadcast->operand].bitfield.mem
4529 || (t->opcode_modifier.vecesize == 0
4530 && !i.types[i.broadcast->operand].bitfield.dword
4531 && !i.types[i.broadcast->operand].bitfield.unspecified)
4532 || (t->opcode_modifier.vecesize == 1
4533 && !i.types[i.broadcast->operand].bitfield.qword
4534 && !i.types[i.broadcast->operand].bitfield.unspecified))
4535 goto bad_broadcast;
4536
4537 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4538 if (i.broadcast->type == BROADCAST_1TO16)
4539 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4540 else if (i.broadcast->type == BROADCAST_1TO8)
4541 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
b28d1bda
IT		 4542 else if (i.broadcast->type == BROADCAST_1TO4)
4543 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4544 else if (i.broadcast->type == BROADCAST_1TO2)
4545 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
43234a1e
L		 4546 else
4547 goto bad_broadcast;
4548
4549 if ((broadcasted_opnd_size == 256
4550 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4551 || (broadcasted_opnd_size == 512
4552 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4553 {
4554 bad_broadcast:
4555 i.error = unsupported_broadcast;
4556 return 1;
4557 }
4558 }
4559 /* If broadcast is supported in this instruction, we need to check if
4560 operand of one-element size isn't specified without broadcast. */
4561 else if (t->opcode_modifier.broadcast && i.mem_operands)
4562 {
4563 /* Find memory operand. */
4564 for (op = 0; op < i.operands; op++)
4565 if (operand_type_check (i.types[op], anymem))
4566 break;
4567 gas_assert (op < i.operands);
4568 /* Check size of the memory operand. */
4569 if ((t->opcode_modifier.vecesize == 0
4570 && i.types[op].bitfield.dword)
4571 || (t->opcode_modifier.vecesize == 1
4572 && i.types[op].bitfield.qword))
4573 {
4574 i.error = broadcast_needed;
4575 return 1;
4576 }
4577 }
4578
4579 /* Check if requested masking is supported. */
4580 if (i.mask
4581 && (!t->opcode_modifier.masking
4582 || (i.mask->zeroing
4583 && t->opcode_modifier.masking == MERGING_MASKING)))
4584 {
4585 i.error = unsupported_masking;
4586 return 1;
4587 }
4588
4589 /* Check if masking is applied to dest operand. */
4590 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4591 {
4592 i.error = mask_not_on_destination;
4593 return 1;
4594 }
4595
43234a1e
L		 4596 /* Check RC/SAE. */
4597 if (i.rounding)
4598 {
4599 if ((i.rounding->type != saeonly
4600 && !t->opcode_modifier.staticrounding)
4601 || (i.rounding->type == saeonly
4602 && (t->opcode_modifier.staticrounding
4603 || !t->opcode_modifier.sae)))
4604 {
4605 i.error = unsupported_rc_sae;
4606 return 1;
4607 }
4608 /* If the instruction has several immediate operands and one of
4609 them is rounding, the rounding operand should be the last
4610 immediate operand. */
4611 if (i.imm_operands > 1
4612 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4613 {
43234a1e 4614 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4615 return 1;
4616 }
6c30d220
L		 4617 }
4618
43234a1e
L		 4619 /* Check vector Disp8 operand. */
4620 if (t->opcode_modifier.disp8memshift)
4621 {
4622 if (i.broadcast)
4623 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4624 else
4625 i.memshift = t->opcode_modifier.disp8memshift;
4626
4627 for (op = 0; op < i.operands; op++)
4628 if (operand_type_check (i.types[op], disp)
4629 && i.op[op].disps->X_op == O_constant)
4630 {
4631 offsetT value = i.op[op].disps->X_add_number;
5be33403
L		 4632 int vec_disp8_ok
4633 = (i.disp_encoding != disp_encoding_32bit
4634 && fits_in_vec_disp8 (value));
43234a1e
L		 4635 if (t->operand_types [op].bitfield.vec_disp8)
4636 {
4637 if (vec_disp8_ok)
4638 i.types[op].bitfield.vec_disp8 = 1;
4639 else
4640 {
4641 /* Vector insn can only have Vec_Disp8/Disp32 in
4642 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4643 mode. */
4644 i.types[op].bitfield.disp8 = 0;
4645 if (flag_code != CODE_16BIT)
4646 i.types[op].bitfield.disp16 = 0;
4647 }
4648 }
4649 else if (flag_code != CODE_16BIT)
4650 {
4651 /* One form of this instruction supports vector Disp8.
4652 Try vector Disp8 if we need to use Disp32. */
4653 if (vec_disp8_ok && !fits_in_signed_byte (value))
4654 {
4655 i.error = try_vector_disp8;
4656 return 1;
4657 }
4658 }
4659 }
4660 }
4661 else
4662 i.memshift = -1;
4663
6c30d220
L		 4664 return 0;
4665}
4666
43f3e2ee 4667/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4668 operand types. */
4669
4670static int
4671VEX_check_operands (const insn_template *t)
4672{
43234a1e
L		 4673 /* VREX is only valid with EVEX prefix. */
4674 if (i.need_vrex && !t->opcode_modifier.evex)
4675 {
4676 i.error = invalid_register_operand;
4677 return 1;
4678 }
4679
a683cc34
SP		 4680 if (!t->opcode_modifier.vex)
4681 return 0;
4682
4683 /* Only check VEX_Imm4, which must be the first operand. */
4684 if (t->operand_types[0].bitfield.vec_imm4)
4685 {
4686 if (i.op[0].imms->X_op != O_constant
4687 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4688 {
a65babc9 4689 i.error = bad_imm4;
891edac4
L		 4690 return 1;
4691 }
a683cc34
SP		 4692
4693 /* Turn off Imm8 so that update_imm won't complain. */
4694 i.types[0] = vec_imm4;
4695 }
4696
4697 return 0;
4698}
4699
d3ce72d0 4700static const insn_template *
e3bb37b5 4701match_template (void)
29b0f896
AM		 4702{
4703 /* Points to template once we've found it. */
d3ce72d0 4704 const insn_template *t;
40fb9820 4705 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4706 i386_operand_type overlap4;
29b0f896 4707 unsigned int found_reverse_match;
40fb9820
L		 4708 i386_opcode_modifier suffix_check;
4709 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4710 int addr_prefix_disp;
a5c311ca 4711 unsigned int j;
3629bb00 4712 unsigned int found_cpu_match;
45664ddb 4713 unsigned int check_register;
5614d22c 4714 enum i386_error specific_error = 0;
29b0f896 4715
c0f3af97
L		 4716#if MAX_OPERANDS != 5
4717# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4718#endif
4719
29b0f896 4720 found_reverse_match = 0;
539e75ad 4721 addr_prefix_disp = -1;
40fb9820
L		 4722
4723 memset (&suffix_check, 0, sizeof (suffix_check));
4724 if (i.suffix == BYTE_MNEM_SUFFIX)
4725 suffix_check.no_bsuf = 1;
4726 else if (i.suffix == WORD_MNEM_SUFFIX)
4727 suffix_check.no_wsuf = 1;
4728 else if (i.suffix == SHORT_MNEM_SUFFIX)
4729 suffix_check.no_ssuf = 1;
4730 else if (i.suffix == LONG_MNEM_SUFFIX)
4731 suffix_check.no_lsuf = 1;
4732 else if (i.suffix == QWORD_MNEM_SUFFIX)
4733 suffix_check.no_qsuf = 1;
4734 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4735 suffix_check.no_ldsuf = 1;
29b0f896 4736
01559ecc
L		 4737 /* Must have right number of operands. */
4738 i.error = number_of_operands_mismatch;
4739
45aa61fe 4740 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4741 {
539e75ad
L		 4742 addr_prefix_disp = -1;
4743
29b0f896
AM		 4744 if (i.operands != t->operands)
4745 continue;
4746
50aecf8c 4747 /* Check processor support. */
a65babc9 4748 i.error = unsupported;
c0f3af97
L		 4749 found_cpu_match = (cpu_flags_match (t)
4750 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4751 if (!found_cpu_match)
4752 continue;
4753
e1d4d893 4754 /* Check old gcc support. */
a65babc9 4755 i.error = old_gcc_only;
e1d4d893
L		 4756 if (!old_gcc && t->opcode_modifier.oldgcc)
4757 continue;
4758
4759 /* Check AT&T mnemonic. */
a65babc9 4760 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4761 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4762 continue;
4763
e92bae62 4764 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
a65babc9 4765 i.error = unsupported_syntax;
5c07affc 4766 if ((intel_syntax && t->opcode_modifier.attsyntax)
e92bae62
L		 4767 || (!intel_syntax && t->opcode_modifier.intelsyntax)
4768 || (intel64 && t->opcode_modifier.amd64)
4769 || (!intel64 && t->opcode_modifier.intel64))
1efbbeb4
L		 4770 continue;
4771
20592a94 4772 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4773 i.error = invalid_instruction_suffix;
567e4e96
L		 4774 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4775 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4776 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4777 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4778 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4779 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4780 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 4781 continue;
4782
5c07affc 4783 if (!operand_size_match (t))
7d5e4556 4784 continue;
539e75ad 4785
5c07affc
L		 4786 for (j = 0; j < MAX_OPERANDS; j++)
4787 operand_types[j] = t->operand_types[j];
4788
45aa61fe
AM		 4789 /* In general, don't allow 64-bit operands in 32-bit mode. */
4790 if (i.suffix == QWORD_MNEM_SUFFIX
4791 && flag_code != CODE_64BIT
4792 && (intel_syntax
40fb9820 4793 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4794 && !intel_float_operand (t->name))
4795 : intel_float_operand (t->name) != 2)
40fb9820 4796 && ((!operand_types[0].bitfield.regmmx
c0f3af97 4797 && !operand_types[0].bitfield.regxmm
43234a1e
L		 4798 && !operand_types[0].bitfield.regymm
4799 && !operand_types[0].bitfield.regzmm)
40fb9820 4800 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736
AM		 4801 && operand_types[t->operands > 1].bitfield.regxmm
4802 && operand_types[t->operands > 1].bitfield.regymm
4803 && operand_types[t->operands > 1].bitfield.regzmm))
45aa61fe
AM		 4804 && (t->base_opcode != 0x0fc7
4805 || t->extension_opcode != 1 /* cmpxchg8b */))
4806 continue;
4807
192dc9c6
JB		 4808 /* In general, don't allow 32-bit operands on pre-386. */
4809 else if (i.suffix == LONG_MNEM_SUFFIX
4810 && !cpu_arch_flags.bitfield.cpui386
4811 && (intel_syntax
4812 ? (!t->opcode_modifier.ignoresize
4813 && !intel_float_operand (t->name))
4814 : intel_float_operand (t->name) != 2)
4815 && ((!operand_types[0].bitfield.regmmx
4816 && !operand_types[0].bitfield.regxmm)
4817 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736 4818 && operand_types[t->operands > 1].bitfield.regxmm)))
192dc9c6
JB		 4819 continue;
4820
29b0f896 4821 /* Do not verify operands when there are none. */
50aecf8c 4822 else
29b0f896 4823 {
c6fb90c8 4824 if (!t->operands)
2dbab7d5
L		 4825 /* We've found a match; break out of loop. */
4826 break;
29b0f896 4827 }
252b5132 4828
539e75ad
L		 4829 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4830 into Disp32/Disp16/Disp32 operand. */
4831 if (i.prefix[ADDR_PREFIX] != 0)
4832 {
40fb9820 4833 /* There should be only one Disp operand. */
539e75ad
L		 4834 switch (flag_code)
4835 {
4836 case CODE_16BIT:
40fb9820
L		 4837 for (j = 0; j < MAX_OPERANDS; j++)
4838 {
4839 if (operand_types[j].bitfield.disp16)
4840 {
4841 addr_prefix_disp = j;
4842 operand_types[j].bitfield.disp32 = 1;
4843 operand_types[j].bitfield.disp16 = 0;
4844 break;
4845 }
4846 }
539e75ad
L		 4847 break;
4848 case CODE_32BIT:
40fb9820
L		 4849 for (j = 0; j < MAX_OPERANDS; j++)
4850 {
4851 if (operand_types[j].bitfield.disp32)
4852 {
4853 addr_prefix_disp = j;
4854 operand_types[j].bitfield.disp32 = 0;
4855 operand_types[j].bitfield.disp16 = 1;
4856 break;
4857 }
4858 }
539e75ad
L		 4859 break;
4860 case CODE_64BIT:
40fb9820
L		 4861 for (j = 0; j < MAX_OPERANDS; j++)
4862 {
4863 if (operand_types[j].bitfield.disp64)
4864 {
4865 addr_prefix_disp = j;
4866 operand_types[j].bitfield.disp64 = 0;
4867 operand_types[j].bitfield.disp32 = 1;
4868 break;
4869 }
4870 }
539e75ad
L		 4871 break;
4872 }
539e75ad
L		 4873 }
4874
02a86693
L		 4875 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
4876 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
4877 continue;
4878
56ffb741
L		 4879 /* We check register size if needed. */
4880 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4881 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4882 switch (t->operands)
4883 {
4884 case 1:
40fb9820 4885 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4886 continue;
4887 break;
4888 case 2:
8b38ad71
L		 4889 /* xchg %eax, %eax is a special case. It is an aliase for nop
4890 only in 32bit mode and we can use opcode 0x90. In 64bit
4891 mode, we can't use 0x90 for xchg %eax, %eax since it should
4892 zero-extend %eax to %rax. */
4893 if (flag_code == CODE_64BIT
4894 && t->base_opcode == 0x90
0dfbf9d7
L		 4895 && operand_type_equal (&i.types [0], &acc32)
4896 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4897 continue;
b6169b20
L		 4898 if (i.swap_operand)
4899 {
4900 /* If we swap operand in encoding, we either match
4901 the next one or reverse direction of operands. */
4902 if (t->opcode_modifier.s)
4903 continue;
4904 else if (t->opcode_modifier.d)
4905 goto check_reverse;
4906 }
4907
29b0f896 4908 case 3:
fa99fab2
L		 4909 /* If we swap operand in encoding, we match the next one. */
4910 if (i.swap_operand && t->opcode_modifier.s)
4911 continue;
f48ff2ae 4912 case 4:
c0f3af97 4913 case 5:
c6fb90c8 4914 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4915 if (!operand_type_match (overlap0, i.types[0])
4916 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4917 || (check_register
4918 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4919 operand_types[0],
4920 overlap1, i.types[1],
4921 operand_types[1])))
29b0f896
AM		 4922 {
4923 /* Check if other direction is valid ... */
40fb9820 4924 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4925 continue;
4926
b6169b20 4927check_reverse:
29b0f896 4928 /* Try reversing direction of operands. */
c6fb90c8
L		 4929 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4930 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4931 if (!operand_type_match (overlap0, i.types[0])
4932 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4933 || (check_register
4934 && !operand_type_register_match (overlap0,
4935 i.types[0],
4936 operand_types[1],
4937 overlap1,
4938 i.types[1],
4939 operand_types[0])))
29b0f896
AM		 4940 {
4941 /* Does not match either direction. */
4942 continue;
4943 }
4944 /* found_reverse_match holds which of D or FloatDR
4945 we've found. */
40fb9820 4946 if (t->opcode_modifier.d)
8a2ed489 4947 found_reverse_match = Opcode_D;
40fb9820 4948 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4949 found_reverse_match = Opcode_FloatD;
4950 else
4951 found_reverse_match = 0;
40fb9820 4952 if (t->opcode_modifier.floatr)
8a2ed489 4953 found_reverse_match |= Opcode_FloatR;
29b0f896 4954 }
f48ff2ae 4955 else
29b0f896 4956 {
f48ff2ae 4957 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4958 switch (t->operands)
4959 {
c0f3af97
L		 4960 case 5:
4961 overlap4 = operand_type_and (i.types[4],
4962 operand_types[4]);
d1cbb4db 4963 case 4:
c6fb90c8
L		 4964 overlap3 = operand_type_and (i.types[3],
4965 operand_types[3]);
d1cbb4db 4966 case 3:
c6fb90c8
L		 4967 overlap2 = operand_type_and (i.types[2],
4968 operand_types[2]);
d1cbb4db
L		 4969 break;
4970 }
29b0f896 4971
f48ff2ae
L		 4972 switch (t->operands)
4973 {
c0f3af97
L		 4974 case 5:
4975 if (!operand_type_match (overlap4, i.types[4])
4976 || !operand_type_register_match (overlap3,
4977 i.types[3],
4978 operand_types[3],
4979 overlap4,
4980 i.types[4],
4981 operand_types[4]))
4982 continue;
f48ff2ae 4983 case 4:
40fb9820 4984 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4985 || (check_register
4986 && !operand_type_register_match (overlap2,
4987 i.types[2],
4988 operand_types[2],
4989 overlap3,
4990 i.types[3],
4991 operand_types[3])))
f48ff2ae
L		 4992 continue;
4993 case 3:
4994 /* Here we make use of the fact that there are no
4995 reverse match 3 operand instructions, and all 3
4996 operand instructions only need to be checked for
4997 register consistency between operands 2 and 3. */
40fb9820 4998 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4999 || (check_register
5000 && !operand_type_register_match (overlap1,
5001 i.types[1],
5002 operand_types[1],
5003 overlap2,
5004 i.types[2],
5005 operand_types[2])))
f48ff2ae
L		 5006 continue;
5007 break;
5008 }
29b0f896 5009 }
f48ff2ae 5010 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 5011 slip through to break. */
5012 }
3629bb00 5013 if (!found_cpu_match)
29b0f896
AM		 5014 {
5015 found_reverse_match = 0;
5016 continue;
5017 }
c0f3af97 5018
5614d22c
JB		 5019 /* Check if vector and VEX operands are valid. */
5020 if (check_VecOperands (t) || VEX_check_operands (t))
5021 {
5022 specific_error = i.error;
5023 continue;
5024 }
a683cc34 5025
29b0f896
AM		 5026 /* We've found a match; break out of loop. */
5027 break;
5028 }
5029
5030 if (t == current_templates->end)
5031 {
5032 /* We found no match. */
a65babc9 5033 const char *err_msg;
5614d22c 5034 switch (specific_error ? specific_error : i.error)
a65babc9
L		 5035 {
5036 default:
5037 abort ();
86e026a4 5038 case operand_size_mismatch:
a65babc9
L		 5039 err_msg = _("operand size mismatch");
5040 break;
5041 case operand_type_mismatch:
5042 err_msg = _("operand type mismatch");
5043 break;
5044 case register_type_mismatch:
5045 err_msg = _("register type mismatch");
5046 break;
5047 case number_of_operands_mismatch:
5048 err_msg = _("number of operands mismatch");
5049 break;
5050 case invalid_instruction_suffix:
5051 err_msg = _("invalid instruction suffix");
5052 break;
5053 case bad_imm4:
4a2608e3 5054 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 5055 break;
5056 case old_gcc_only:
5057 err_msg = _("only supported with old gcc");
5058 break;
5059 case unsupported_with_intel_mnemonic:
5060 err_msg = _("unsupported with Intel mnemonic");
5061 break;
5062 case unsupported_syntax:
5063 err_msg = _("unsupported syntax");
5064 break;
5065 case unsupported:
35262a23 5066 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 5067 current_templates->start->name);
5068 return NULL;
6c30d220
L		 5069 case invalid_vsib_address:
5070 err_msg = _("invalid VSIB address");
5071 break;
7bab8ab5
JB		 5072 case invalid_vector_register_set:
5073 err_msg = _("mask, index, and destination registers must be distinct");
5074 break;
6c30d220
L		 5075 case unsupported_vector_index_register:
5076 err_msg = _("unsupported vector index register");
5077 break;
43234a1e
L		 5078 case unsupported_broadcast:
5079 err_msg = _("unsupported broadcast");
5080 break;
5081 case broadcast_not_on_src_operand:
5082 err_msg = _("broadcast not on source memory operand");
5083 break;
5084 case broadcast_needed:
5085 err_msg = _("broadcast is needed for operand of such type");
5086 break;
5087 case unsupported_masking:
5088 err_msg = _("unsupported masking");
5089 break;
5090 case mask_not_on_destination:
5091 err_msg = _("mask not on destination operand");
5092 break;
5093 case no_default_mask:
5094 err_msg = _("default mask isn't allowed");
5095 break;
5096 case unsupported_rc_sae:
5097 err_msg = _("unsupported static rounding/sae");
5098 break;
5099 case rc_sae_operand_not_last_imm:
5100 if (intel_syntax)
5101 err_msg = _("RC/SAE operand must precede immediate operands");
5102 else
5103 err_msg = _("RC/SAE operand must follow immediate operands");
5104 break;
5105 case invalid_register_operand:
5106 err_msg = _("invalid register operand");
5107 break;
a65babc9
L		 5108 }
5109 as_bad (_("%s for `%s'"), err_msg,
891edac4 5110 current_templates->start->name);
fa99fab2 5111 return NULL;
29b0f896 5112 }
252b5132 5113
29b0f896
AM		 5114 if (!quiet_warnings)
5115 {
5116 if (!intel_syntax
40fb9820
L		 5117 && (i.types[0].bitfield.jumpabsolute
5118 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5119 {
5120 as_warn (_("indirect %s without `*'"), t->name);
5121 }
5122
40fb9820
L		 5123 if (t->opcode_modifier.isprefix
5124 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5125 {
5126 /* Warn them that a data or address size prefix doesn't
5127 affect assembly of the next line of code. */
5128 as_warn (_("stand-alone `%s' prefix"), t->name);
5129 }
5130 }
5131
5132 /* Copy the template we found. */
5133 i.tm = *t;
539e75ad
L		 5134
5135 if (addr_prefix_disp != -1)
5136 i.tm.operand_types[addr_prefix_disp]
5137 = operand_types[addr_prefix_disp];
5138
29b0f896
AM		 5139 if (found_reverse_match)
5140 {
5141 /* If we found a reverse match we must alter the opcode
5142 direction bit. found_reverse_match holds bits to change
5143 (different for int & float insns). */
5144
5145 i.tm.base_opcode ^= found_reverse_match;
5146
539e75ad
L		 5147 i.tm.operand_types[0] = operand_types[1];
5148 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5149 }
5150
fa99fab2 5151 return t;
29b0f896
AM		 5152}
5153
5154static int
e3bb37b5 5155check_string (void)
29b0f896 5156{
40fb9820
L		 5157 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5158 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5159 {
5160 if (i.seg[0] != NULL && i.seg[0] != &es)
5161 {
a87af027 5162 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5163 i.tm.name,
a87af027
JB		 5164 mem_op + 1,
5165 register_prefix);
29b0f896
AM		 5166 return 0;
5167 }
5168 /* There's only ever one segment override allowed per instruction.
5169 This instruction possibly has a legal segment override on the
5170 second operand, so copy the segment to where non-string
5171 instructions store it, allowing common code. */
5172 i.seg[0] = i.seg[1];
5173 }
40fb9820 5174 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5175 {
5176 if (i.seg[1] != NULL && i.seg[1] != &es)
5177 {
a87af027 5178 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5179 i.tm.name,
a87af027
JB		 5180 mem_op + 2,
5181 register_prefix);
29b0f896
AM		 5182 return 0;
5183 }
5184 }
5185 return 1;
5186}
5187
5188static int
543613e9 5189process_suffix (void)
29b0f896
AM		 5190{
5191 /* If matched instruction specifies an explicit instruction mnemonic
5192 suffix, use it. */
40fb9820
L		 5193 if (i.tm.opcode_modifier.size16)
5194 i.suffix = WORD_MNEM_SUFFIX;
5195 else if (i.tm.opcode_modifier.size32)
5196 i.suffix = LONG_MNEM_SUFFIX;
5197 else if (i.tm.opcode_modifier.size64)
5198 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5199 else if (i.reg_operands)
5200 {
5201 /* If there's no instruction mnemonic suffix we try to invent one
5202 based on register operands. */
5203 if (!i.suffix)
5204 {
5205 /* We take i.suffix from the last register operand specified,
5206 Destination register type is more significant than source
381d071f
L		 5207 register type. crc32 in SSE4.2 prefers source register
5208 type. */
5209 if (i.tm.base_opcode == 0xf20f38f1)
5210 {
40fb9820
L		 5211 if (i.types[0].bitfield.reg16)
5212 i.suffix = WORD_MNEM_SUFFIX;
5213 else if (i.types[0].bitfield.reg32)
5214 i.suffix = LONG_MNEM_SUFFIX;
5215 else if (i.types[0].bitfield.reg64)
5216 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5217 }
9344ff29 5218 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5219 {
40fb9820 5220 if (i.types[0].bitfield.reg8)
20592a94
L		 5221 i.suffix = BYTE_MNEM_SUFFIX;
5222 }
381d071f
L		 5223
5224 if (!i.suffix)
5225 {
5226 int op;
5227
20592a94
L		 5228 if (i.tm.base_opcode == 0xf20f38f1
5229 || i.tm.base_opcode == 0xf20f38f0)
5230 {
5231 /* We have to know the operand size for crc32. */
5232 as_bad (_("ambiguous memory operand size for `%s`"),
5233 i.tm.name);
5234 return 0;
5235 }
5236
381d071f 5237 for (op = i.operands; --op >= 0;)
40fb9820 5238 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 5239 {
40fb9820
L		 5240 if (i.types[op].bitfield.reg8)
5241 {
5242 i.suffix = BYTE_MNEM_SUFFIX;
5243 break;
5244 }
5245 else if (i.types[op].bitfield.reg16)
5246 {
5247 i.suffix = WORD_MNEM_SUFFIX;
5248 break;
5249 }
5250 else if (i.types[op].bitfield.reg32)
5251 {
5252 i.suffix = LONG_MNEM_SUFFIX;
5253 break;
5254 }
5255 else if (i.types[op].bitfield.reg64)
5256 {
5257 i.suffix = QWORD_MNEM_SUFFIX;
5258 break;
5259 }
381d071f
L		 5260 }
5261 }
29b0f896
AM		 5262 }
5263 else if (i.suffix == BYTE_MNEM_SUFFIX)
5264 {
2eb952a4
L		 5265 if (intel_syntax
5266 && i.tm.opcode_modifier.ignoresize
5267 && i.tm.opcode_modifier.no_bsuf)
5268 i.suffix = 0;
5269 else if (!check_byte_reg ())
29b0f896
AM		 5270 return 0;
5271 }
5272 else if (i.suffix == LONG_MNEM_SUFFIX)
5273 {
2eb952a4
L		 5274 if (intel_syntax
5275 && i.tm.opcode_modifier.ignoresize
5276 && i.tm.opcode_modifier.no_lsuf)
5277 i.suffix = 0;
5278 else if (!check_long_reg ())
29b0f896
AM		 5279 return 0;
5280 }
5281 else if (i.suffix == QWORD_MNEM_SUFFIX)
5282 {
955e1e6a
L		 5283 if (intel_syntax
5284 && i.tm.opcode_modifier.ignoresize
5285 && i.tm.opcode_modifier.no_qsuf)
5286 i.suffix = 0;
5287 else if (!check_qword_reg ())
29b0f896
AM		 5288 return 0;
5289 }
5290 else if (i.suffix == WORD_MNEM_SUFFIX)
5291 {
2eb952a4
L		 5292 if (intel_syntax
5293 && i.tm.opcode_modifier.ignoresize
5294 && i.tm.opcode_modifier.no_wsuf)
5295 i.suffix = 0;
5296 else if (!check_word_reg ())
29b0f896
AM		 5297 return 0;
5298 }
c0f3af97 5299 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5300 || i.suffix == YMMWORD_MNEM_SUFFIX
5301 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5302 {
43234a1e 5303 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5304 should check if it is a valid suffix. */
5305 }
40fb9820 5306 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5307 /* Do nothing if the instruction is going to ignore the prefix. */
5308 ;
5309 else
5310 abort ();
5311 }
40fb9820 5312 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5313 && !i.suffix
5314 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5315 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5316 {
5317 i.suffix = stackop_size;
5318 }
9306ca4a
JB		 5319 else if (intel_syntax
5320 && !i.suffix
40fb9820
L		 5321 && (i.tm.operand_types[0].bitfield.jumpabsolute
5322 || i.tm.opcode_modifier.jumpbyte
5323 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5324 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5325 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5326 {
5327 switch (flag_code)
5328 {
5329 case CODE_64BIT:
40fb9820 5330 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5331 {
5332 i.suffix = QWORD_MNEM_SUFFIX;
5333 break;
5334 }
5335 case CODE_32BIT:
40fb9820 5336 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5337 i.suffix = LONG_MNEM_SUFFIX;
5338 break;
5339 case CODE_16BIT:
40fb9820 5340 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5341 i.suffix = WORD_MNEM_SUFFIX;
5342 break;
5343 }
5344 }
252b5132 5345
9306ca4a 5346 if (!i.suffix)
29b0f896 5347 {
9306ca4a
JB		 5348 if (!intel_syntax)
5349 {
40fb9820 5350 if (i.tm.opcode_modifier.w)
9306ca4a 5351 {
4eed87de
AM		 5352 as_bad (_("no instruction mnemonic suffix given and "
5353 "no register operands; can't size instruction"));
9306ca4a
JB		 5354 return 0;
5355 }
5356 }
5357 else
5358 {
40fb9820 5359 unsigned int suffixes;
7ab9ffdd 5360
40fb9820
L		 5361 suffixes = !i.tm.opcode_modifier.no_bsuf;
5362 if (!i.tm.opcode_modifier.no_wsuf)
5363 suffixes |= 1 << 1;
5364 if (!i.tm.opcode_modifier.no_lsuf)
5365 suffixes |= 1 << 2;
fc4adea1 5366 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5367 suffixes |= 1 << 3;
5368 if (!i.tm.opcode_modifier.no_ssuf)
5369 suffixes |= 1 << 4;
5370 if (!i.tm.opcode_modifier.no_qsuf)
5371 suffixes |= 1 << 5;
5372
5373 /* There are more than suffix matches. */
5374 if (i.tm.opcode_modifier.w
9306ca4a 5375 || ((suffixes & (suffixes - 1))
40fb9820
L		 5376 && !i.tm.opcode_modifier.defaultsize
5377 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5378 {
5379 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5380 return 0;
5381 }
5382 }
29b0f896 5383 }
252b5132 5384
9306ca4a
JB		 5385 /* Change the opcode based on the operand size given by i.suffix;
5386 We don't need to change things for byte insns. */
5387
582d5edd
L		 5388 if (i.suffix
5389 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5390 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5391 && i.suffix != YMMWORD_MNEM_SUFFIX
5392 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5393 {
5394 /* It's not a byte, select word/dword operation. */
40fb9820 5395 if (i.tm.opcode_modifier.w)
29b0f896 5396 {
40fb9820 5397 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5398 i.tm.base_opcode |= 8;
5399 else
5400 i.tm.base_opcode |= 1;
5401 }
0f3f3d8b 5402
29b0f896
AM		 5403 /* Now select between word & dword operations via the operand
5404 size prefix, except for instructions that will ignore this
5405 prefix anyway. */
ca61edf2 5406 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5407 {
ca61edf2
L		 5408 /* The address size override prefix changes the size of the
5409 first operand. */
40fb9820
L		 5410 if ((flag_code == CODE_32BIT
5411 && i.op->regs[0].reg_type.bitfield.reg16)
5412 || (flag_code != CODE_32BIT
5413 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 5414 if (!add_prefix (ADDR_PREFIX_OPCODE))
5415 return 0;
5416 }
5417 else if (i.suffix != QWORD_MNEM_SUFFIX
5418 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5419 && !i.tm.opcode_modifier.ignoresize
5420 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5421 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5422 || (flag_code == CODE_64BIT
40fb9820 5423 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5424 {
5425 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5426
40fb9820 5427 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5428 prefix = ADDR_PREFIX_OPCODE;
252b5132 5429
29b0f896
AM		 5430 if (!add_prefix (prefix))
5431 return 0;
24eab124 5432 }
252b5132 5433
29b0f896
AM		 5434 /* Set mode64 for an operand. */
5435 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5436 && flag_code == CODE_64BIT
40fb9820 5437 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5438 {
5439 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5440 need rex64. cmpxchg8b is also a special case. */
5441 if (! (i.operands == 2
5442 && i.tm.base_opcode == 0x90
5443 && i.tm.extension_opcode == None
0dfbf9d7
L		 5444 && operand_type_equal (&i.types [0], &acc64)
5445 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5446 && ! (i.operands == 1
5447 && i.tm.base_opcode == 0xfc7
5448 && i.tm.extension_opcode == 1
40fb9820
L		 5449 && !operand_type_check (i.types [0], reg)
5450 && operand_type_check (i.types [0], anymem)))
f6bee062 5451 i.rex |= REX_W;
46e883c5 5452 }
3e73aa7c 5453
29b0f896
AM		 5454 /* Size floating point instruction. */
5455 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5456 if (i.tm.opcode_modifier.floatmf)
543613e9 5457 i.tm.base_opcode ^= 4;
29b0f896 5458 }
7ecd2f8b 5459
29b0f896
AM		 5460 return 1;
5461}
3e73aa7c 5462
29b0f896 5463static int
543613e9 5464check_byte_reg (void)
29b0f896
AM		 5465{
5466 int op;
543613e9 5467
29b0f896
AM		 5468 for (op = i.operands; --op >= 0;)
5469 {
5470 /* If this is an eight bit register, it's OK. If it's the 16 or
5471 32 bit version of an eight bit register, we will just use the
5472 low portion, and that's OK too. */
40fb9820 5473 if (i.types[op].bitfield.reg8)
29b0f896
AM		 5474 continue;
5475
5a819eb9
JB		 5476 /* I/O port address operands are OK too. */
5477 if (i.tm.operand_types[op].bitfield.inoutportreg)
5478 continue;
5479
9344ff29
L		 5480 /* crc32 doesn't generate this warning. */
5481 if (i.tm.base_opcode == 0xf20f38f0)
5482 continue;
5483
40fb9820
L		 5484 if ((i.types[op].bitfield.reg16
5485 || i.types[op].bitfield.reg32
5486 || i.types[op].bitfield.reg64)
5a819eb9
JB		 5487 && i.op[op].regs->reg_num < 4
5488 /* Prohibit these changes in 64bit mode, since the lowering
5489 would be more complicated. */
5490 && flag_code != CODE_64BIT)
29b0f896 5491 {
29b0f896 5492#if REGISTER_WARNINGS
5a819eb9 5493 if (!quiet_warnings)
a540244d
L		 5494 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5495 register_prefix,
40fb9820 5496 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 5497 ? REGNAM_AL - REGNAM_AX
5498 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5499 register_prefix,
29b0f896
AM		 5500 i.op[op].regs->reg_name,
5501 i.suffix);
5502#endif
5503 continue;
5504 }
5505 /* Any other register is bad. */
40fb9820
L		 5506 if (i.types[op].bitfield.reg16
5507 || i.types[op].bitfield.reg32
5508 || i.types[op].bitfield.reg64
5509 || i.types[op].bitfield.regmmx
5510 || i.types[op].bitfield.regxmm
c0f3af97 5511 || i.types[op].bitfield.regymm
43234a1e 5512 || i.types[op].bitfield.regzmm
40fb9820
L		 5513 || i.types[op].bitfield.sreg2
5514 || i.types[op].bitfield.sreg3
5515 || i.types[op].bitfield.control
5516 || i.types[op].bitfield.debug
5517 || i.types[op].bitfield.test
5518 || i.types[op].bitfield.floatreg
5519 || i.types[op].bitfield.floatacc)
29b0f896 5520 {
a540244d
L		 5521 as_bad (_("`%s%s' not allowed with `%s%c'"),
5522 register_prefix,
29b0f896
AM		 5523 i.op[op].regs->reg_name,
5524 i.tm.name,
5525 i.suffix);
5526 return 0;
5527 }
5528 }
5529 return 1;
5530}
5531
5532static int
e3bb37b5 5533check_long_reg (void)
29b0f896
AM		 5534{
5535 int op;
5536
5537 for (op = i.operands; --op >= 0;)
5538 /* Reject eight bit registers, except where the template requires
5539 them. (eg. movzb) */
40fb9820
L		 5540 if (i.types[op].bitfield.reg8
5541 && (i.tm.operand_types[op].bitfield.reg16
5542 || i.tm.operand_types[op].bitfield.reg32
5543 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5544 {
a540244d
L		 5545 as_bad (_("`%s%s' not allowed with `%s%c'"),
5546 register_prefix,
29b0f896
AM		 5547 i.op[op].regs->reg_name,
5548 i.tm.name,
5549 i.suffix);
5550 return 0;
5551 }
e4630f71 5552 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5553 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5554 && i.types[op].bitfield.reg16
5555 && (i.tm.operand_types[op].bitfield.reg32
5556 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5557 {
5558 /* Prohibit these changes in the 64bit mode, since the
5559 lowering is more complicated. */
5560 if (flag_code == CODE_64BIT)
252b5132 5561 {
2b5d6a91 5562 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5563 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5564 i.suffix);
5565 return 0;
252b5132 5566 }
29b0f896 5567#if REGISTER_WARNINGS
cecf1424
JB		 5568 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5569 register_prefix,
5570 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5571 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5572#endif
252b5132 5573 }
e4630f71 5574 /* Warn if the r prefix on a general reg is present. */
40fb9820
L		 5575 else if (i.types[op].bitfield.reg64
5576 && (i.tm.operand_types[op].bitfield.reg32
5577 || i.tm.operand_types[op].bitfield.acc))
252b5132 5578 {
34828aad 5579 if (intel_syntax
ca61edf2 5580 && i.tm.opcode_modifier.toqword
40fb9820 5581 && !i.types[0].bitfield.regxmm)
34828aad 5582 {
ca61edf2 5583 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5584 i.suffix = QWORD_MNEM_SUFFIX;
5585 }
5586 else
5587 {
2b5d6a91 5588 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5589 register_prefix, i.op[op].regs->reg_name,
5590 i.suffix);
5591 return 0;
5592 }
29b0f896
AM		 5593 }
5594 return 1;
5595}
252b5132 5596
29b0f896 5597static int
e3bb37b5 5598check_qword_reg (void)
29b0f896
AM		 5599{
5600 int op;
252b5132 5601
29b0f896
AM		 5602 for (op = i.operands; --op >= 0; )
5603 /* Reject eight bit registers, except where the template requires
5604 them. (eg. movzb) */
40fb9820
L		 5605 if (i.types[op].bitfield.reg8
5606 && (i.tm.operand_types[op].bitfield.reg16
5607 || i.tm.operand_types[op].bitfield.reg32
5608 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5609 {
a540244d
L		 5610 as_bad (_("`%s%s' not allowed with `%s%c'"),
5611 register_prefix,
29b0f896
AM		 5612 i.op[op].regs->reg_name,
5613 i.tm.name,
5614 i.suffix);
5615 return 0;
5616 }
e4630f71 5617 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 5618 else if ((i.types[op].bitfield.reg16
5619 || i.types[op].bitfield.reg32)
5620 && (i.tm.operand_types[op].bitfield.reg32
5621 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5622 {
5623 /* Prohibit these changes in the 64bit mode, since the
5624 lowering is more complicated. */
34828aad 5625 if (intel_syntax
ca61edf2 5626 && i.tm.opcode_modifier.todword
40fb9820 5627 && !i.types[0].bitfield.regxmm)
34828aad 5628 {
ca61edf2 5629 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5630 i.suffix = LONG_MNEM_SUFFIX;
5631 }
5632 else
5633 {
2b5d6a91 5634 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5635 register_prefix, i.op[op].regs->reg_name,
5636 i.suffix);
5637 return 0;
5638 }
252b5132 5639 }
29b0f896
AM		 5640 return 1;
5641}
252b5132 5642
29b0f896 5643static int
e3bb37b5 5644check_word_reg (void)
29b0f896
AM		 5645{
5646 int op;
5647 for (op = i.operands; --op >= 0;)
5648 /* Reject eight bit registers, except where the template requires
5649 them. (eg. movzb) */
40fb9820
L		 5650 if (i.types[op].bitfield.reg8
5651 && (i.tm.operand_types[op].bitfield.reg16
5652 || i.tm.operand_types[op].bitfield.reg32
5653 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5654 {
a540244d
L		 5655 as_bad (_("`%s%s' not allowed with `%s%c'"),
5656 register_prefix,
29b0f896
AM		 5657 i.op[op].regs->reg_name,
5658 i.tm.name,
5659 i.suffix);
5660 return 0;
5661 }
e4630f71 5662 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5663 else if ((!quiet_warnings || flag_code == CODE_64BIT)
e4630f71
JB		 5664 && (i.types[op].bitfield.reg32
5665 || i.types[op].bitfield.reg64)
40fb9820
L		 5666 && (i.tm.operand_types[op].bitfield.reg16
5667 || i.tm.operand_types[op].bitfield.acc))
252b5132 5668 {
29b0f896
AM		 5669 /* Prohibit these changes in the 64bit mode, since the
5670 lowering is more complicated. */
5671 if (flag_code == CODE_64BIT)
252b5132 5672 {
2b5d6a91 5673 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5674 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5675 i.suffix);
5676 return 0;
252b5132 5677 }
29b0f896 5678#if REGISTER_WARNINGS
cecf1424
JB		 5679 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5680 register_prefix,
5681 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5682 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5683#endif
5684 }
5685 return 1;
5686}
252b5132 5687
29b0f896 5688static int
40fb9820 5689update_imm (unsigned int j)
29b0f896 5690{
bc0844ae 5691 i386_operand_type overlap = i.types[j];
40fb9820
L		 5692 if ((overlap.bitfield.imm8
5693 || overlap.bitfield.imm8s
5694 || overlap.bitfield.imm16
5695 || overlap.bitfield.imm32
5696 || overlap.bitfield.imm32s
5697 || overlap.bitfield.imm64)
0dfbf9d7
L		 5698 && !operand_type_equal (&overlap, &imm8)
5699 && !operand_type_equal (&overlap, &imm8s)
5700 && !operand_type_equal (&overlap, &imm16)
5701 && !operand_type_equal (&overlap, &imm32)
5702 && !operand_type_equal (&overlap, &imm32s)
5703 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5704 {
5705 if (i.suffix)
5706 {
40fb9820
L		 5707 i386_operand_type temp;
5708
0dfbf9d7 5709 operand_type_set (&temp, 0);
7ab9ffdd 5710 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5711 {
5712 temp.bitfield.imm8 = overlap.bitfield.imm8;
5713 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5714 }
5715 else if (i.suffix == WORD_MNEM_SUFFIX)
5716 temp.bitfield.imm16 = overlap.bitfield.imm16;
5717 else if (i.suffix == QWORD_MNEM_SUFFIX)
5718 {
5719 temp.bitfield.imm64 = overlap.bitfield.imm64;
5720 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5721 }
5722 else
5723 temp.bitfield.imm32 = overlap.bitfield.imm32;
5724 overlap = temp;
29b0f896 5725 }
0dfbf9d7
L		 5726 else if (operand_type_equal (&overlap, &imm16_32_32s)
5727 || operand_type_equal (&overlap, &imm16_32)
5728 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5729 {
40fb9820 5730 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5731 overlap = imm16;
40fb9820 5732 else
65da13b5 5733 overlap = imm32s;
29b0f896 5734 }
0dfbf9d7
L		 5735 if (!operand_type_equal (&overlap, &imm8)
5736 && !operand_type_equal (&overlap, &imm8s)
5737 && !operand_type_equal (&overlap, &imm16)
5738 && !operand_type_equal (&overlap, &imm32)
5739 && !operand_type_equal (&overlap, &imm32s)
5740 && !operand_type_equal (&overlap, &imm64))
29b0f896 5741 {
4eed87de
AM		 5742 as_bad (_("no instruction mnemonic suffix given; "
5743 "can't determine immediate size"));
29b0f896
AM		 5744 return 0;
5745 }
5746 }
40fb9820 5747 i.types[j] = overlap;
29b0f896 5748
40fb9820
L		 5749 return 1;
5750}
5751
5752static int
5753finalize_imm (void)
5754{
bc0844ae 5755 unsigned int j, n;
29b0f896 5756
bc0844ae
L		 5757 /* Update the first 2 immediate operands. */
5758 n = i.operands > 2 ? 2 : i.operands;
5759 if (n)
5760 {
5761 for (j = 0; j < n; j++)
5762 if (update_imm (j) == 0)
5763 return 0;
40fb9820 5764
bc0844ae
L		 5765 /* The 3rd operand can't be immediate operand. */
5766 gas_assert (operand_type_check (i.types[2], imm) == 0);
5767 }
29b0f896
AM		 5768
5769 return 1;
5770}
5771
c0f3af97
L		 5772static int
5773bad_implicit_operand (int xmm)
5774{
91d6fa6a
NC		 5775 const char *ireg = xmm ? "xmm0" : "ymm0";
5776
c0f3af97
L		 5777 if (intel_syntax)
5778 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5779 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5780 else
5781 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5782 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5783 return 0;
5784}
5785
29b0f896 5786static int
e3bb37b5 5787process_operands (void)
29b0f896
AM		 5788{
5789 /* Default segment register this instruction will use for memory
5790 accesses. 0 means unknown. This is only for optimizing out
5791 unnecessary segment overrides. */
5792 const seg_entry *default_seg = 0;
5793
2426c15f 5794 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5795 {
91d6fa6a
NC		 5796 unsigned int dupl = i.operands;
5797 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5798 unsigned int j;
5799
c0f3af97 5800 /* The destination must be an xmm register. */
9c2799c2 5801 gas_assert (i.reg_operands
91d6fa6a 5802 && MAX_OPERANDS > dupl
7ab9ffdd 5803 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5804
5805 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5806 {
c0f3af97 5807 /* The first operand is implicit and must be xmm0. */
9c2799c2 5808 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5809 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5810 return bad_implicit_operand (1);
5811
8cd7925b 5812 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5813 {
5814 /* Keep xmm0 for instructions with VEX prefix and 3
5815 sources. */
5816 goto duplicate;
5817 }
e2ec9d29 5818 else
c0f3af97
L		 5819 {
5820 /* We remove the first xmm0 and keep the number of
5821 operands unchanged, which in fact duplicates the
5822 destination. */
5823 for (j = 1; j < i.operands; j++)
5824 {
5825 i.op[j - 1] = i.op[j];
5826 i.types[j - 1] = i.types[j];
5827 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5828 }
5829 }
5830 }
5831 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5832 {
91d6fa6a 5833 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5834 && (i.tm.opcode_modifier.vexsources
5835 == VEX3SOURCES));
c0f3af97
L		 5836
5837 /* Add the implicit xmm0 for instructions with VEX prefix
5838 and 3 sources. */
5839 for (j = i.operands; j > 0; j--)
5840 {
5841 i.op[j] = i.op[j - 1];
5842 i.types[j] = i.types[j - 1];
5843 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5844 }
5845 i.op[0].regs
5846 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5847 i.types[0] = regxmm;
c0f3af97
L		 5848 i.tm.operand_types[0] = regxmm;
5849
5850 i.operands += 2;
5851 i.reg_operands += 2;
5852 i.tm.operands += 2;
5853
91d6fa6a 5854 dupl++;
c0f3af97 5855 dest++;
91d6fa6a
NC		 5856 i.op[dupl] = i.op[dest];
5857 i.types[dupl] = i.types[dest];
5858 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5859 }
c0f3af97
L		 5860 else
5861 {
5862duplicate:
5863 i.operands++;
5864 i.reg_operands++;
5865 i.tm.operands++;
5866
91d6fa6a
NC		 5867 i.op[dupl] = i.op[dest];
5868 i.types[dupl] = i.types[dest];
5869 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5870 }
5871
5872 if (i.tm.opcode_modifier.immext)
5873 process_immext ();
5874 }
5875 else if (i.tm.opcode_modifier.firstxmm0)
5876 {
5877 unsigned int j;
5878
43234a1e 5879 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
9c2799c2 5880 gas_assert (i.reg_operands
7ab9ffdd 5881 && (operand_type_equal (&i.types[0], &regxmm)
43234a1e
L		 5882 || operand_type_equal (&i.types[0], &regymm)
5883 || operand_type_equal (&i.types[0], &regzmm)));
4c692bc7 5884 if (register_number (i.op[0].regs) != 0)
c0f3af97 5885 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5886
5887 for (j = 1; j < i.operands; j++)
5888 {
5889 i.op[j - 1] = i.op[j];
5890 i.types[j - 1] = i.types[j];
5891
5892 /* We need to adjust fields in i.tm since they are used by
5893 build_modrm_byte. */
5894 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5895 }
5896
e2ec9d29
L		 5897 i.operands--;
5898 i.reg_operands--;
e2ec9d29
L		 5899 i.tm.operands--;
5900 }
5901 else if (i.tm.opcode_modifier.regkludge)
5902 {
5903 /* The imul $imm, %reg instruction is converted into
5904 imul $imm, %reg, %reg, and the clr %reg instruction
5905 is converted into xor %reg, %reg. */
5906
5907 unsigned int first_reg_op;
5908
5909 if (operand_type_check (i.types[0], reg))
5910 first_reg_op = 0;
5911 else
5912 first_reg_op = 1;
5913 /* Pretend we saw the extra register operand. */
9c2799c2 5914 gas_assert (i.reg_operands == 1
7ab9ffdd 5915 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5916 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5917 i.types[first_reg_op + 1] = i.types[first_reg_op];
5918 i.operands++;
5919 i.reg_operands++;
29b0f896
AM		 5920 }
5921
40fb9820 5922 if (i.tm.opcode_modifier.shortform)
29b0f896 5923 {
40fb9820
L		 5924 if (i.types[0].bitfield.sreg2
5925 || i.types[0].bitfield.sreg3)
29b0f896 5926 {
4eed87de
AM		 5927 if (i.tm.base_opcode == POP_SEG_SHORT
5928 && i.op[0].regs->reg_num == 1)
29b0f896 5929 {
a87af027 5930 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5931 return 0;
29b0f896 5932 }
4eed87de
AM		 5933 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5934 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5935 i.rex |= REX_B;
4eed87de
AM		 5936 }
5937 else
5938 {
7ab9ffdd 5939 /* The register or float register operand is in operand
85f10a01 5940 0 or 1. */
40fb9820 5941 unsigned int op;
7ab9ffdd
L		 5942
5943 if (i.types[0].bitfield.floatreg
5944 || operand_type_check (i.types[0], reg))
5945 op = 0;
5946 else
5947 op = 1;
4eed87de
AM		 5948 /* Register goes in low 3 bits of opcode. */
5949 i.tm.base_opcode |= i.op[op].regs->reg_num;
5950 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5951 i.rex |= REX_B;
40fb9820 5952 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5953 {
4eed87de
AM		 5954 /* Warn about some common errors, but press on regardless.
5955 The first case can be generated by gcc (<= 2.8.1). */
5956 if (i.operands == 2)
5957 {
5958 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5959 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5960 register_prefix, i.op[!intel_syntax].regs->reg_name,
5961 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5962 }
5963 else
5964 {
5965 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5966 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5967 register_prefix, i.op[0].regs->reg_name);
4eed87de 5968 }
29b0f896
AM		 5969 }
5970 }
5971 }
40fb9820 5972 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5973 {
5974 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5975 must be put into the modrm byte). Now, we make the modrm and
5976 index base bytes based on all the info we've collected. */
29b0f896
AM		 5977
5978 default_seg = build_modrm_byte ();
5979 }
8a2ed489 5980 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5981 {
5982 default_seg = &ds;
5983 }
40fb9820 5984 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5985 {
5986 /* For the string instructions that allow a segment override
5987 on one of their operands, the default segment is ds. */
5988 default_seg = &ds;
5989 }
5990
75178d9d
L		 5991 if (i.tm.base_opcode == 0x8d /* lea */
5992 && i.seg[0]
5993 && !quiet_warnings)
30123838 5994 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5995
5996 /* If a segment was explicitly specified, and the specified segment
5997 is not the default, use an opcode prefix to select it. If we
5998 never figured out what the default segment is, then default_seg
5999 will be zero at this point, and the specified segment prefix will
6000 always be used. */
29b0f896
AM		 6001 if ((i.seg[0]) && (i.seg[0] != default_seg))
6002 {
6003 if (!add_prefix (i.seg[0]->seg_prefix))
6004 return 0;
6005 }
6006 return 1;
6007}
6008
6009static const seg_entry *
e3bb37b5 6010build_modrm_byte (void)
29b0f896
AM		 6011{
6012 const seg_entry *default_seg = 0;
c0f3af97 6013 unsigned int source, dest;
8cd7925b 6014 int vex_3_sources;
c0f3af97
L		 6015
6016 /* The first operand of instructions with VEX prefix and 3 sources
6017 must be VEX_Imm4. */
8cd7925b 6018 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 6019 if (vex_3_sources)
6020 {
91d6fa6a 6021 unsigned int nds, reg_slot;
4c2c6516 6022 expressionS *exp;
c0f3af97 6023
922d8de8 6024 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 6025 && i.tm.opcode_modifier.immext)
6026 {
6027 dest = i.operands - 2;
6028 gas_assert (dest == 3);
6029 }
922d8de8 6030 else
a683cc34 6031 dest = i.operands - 1;
c0f3af97 6032 nds = dest - 1;
922d8de8 6033
a683cc34
SP		 6034 /* There are 2 kinds of instructions:
6035 1. 5 operands: 4 register operands or 3 register operands
6036 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 6037 VexW0 or VexW1. The destination must be either XMM, YMM or
6038 ZMM register.
a683cc34
SP		 6039 2. 4 operands: 4 register operands or 3 register operands
6040 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 6041 gas_assert ((i.reg_operands == 4
a683cc34
SP		 6042 || (i.reg_operands == 3 && i.mem_operands == 1))
6043 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6044 && (i.tm.opcode_modifier.veximmext
6045 || (i.imm_operands == 1
6046 && i.types[0].bitfield.vec_imm4
6047 && (i.tm.opcode_modifier.vexw == VEXW0
6048 || i.tm.opcode_modifier.vexw == VEXW1)
6049 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 6050 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
6051 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 6052
6053 if (i.imm_operands == 0)
6054 {
6055 /* When there is no immediate operand, generate an 8bit
6056 immediate operand to encode the first operand. */
6057 exp = &im_expressions[i.imm_operands++];
6058 i.op[i.operands].imms = exp;
6059 i.types[i.operands] = imm8;
6060 i.operands++;
6061 /* If VexW1 is set, the first operand is the source and
6062 the second operand is encoded in the immediate operand. */
6063 if (i.tm.opcode_modifier.vexw == VEXW1)
6064 {
6065 source = 0;
6066 reg_slot = 1;
6067 }
6068 else
6069 {
6070 source = 1;
6071 reg_slot = 0;
6072 }
6073
6074 /* FMA swaps REG and NDS. */
6075 if (i.tm.cpu_flags.bitfield.cpufma)
6076 {
6077 unsigned int tmp;
6078 tmp = reg_slot;
6079 reg_slot = nds;
6080 nds = tmp;
6081 }
6082
24981e7b
L		 6083 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6084 &regxmm)
a683cc34 6085 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6086 &regymm)
6087 || operand_type_equal (&i.tm.operand_types[reg_slot],
6088 &regzmm));
a683cc34 6089 exp->X_op = O_constant;
4c692bc7 6090 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6091 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6092 }
922d8de8 6093 else
a683cc34
SP		 6094 {
6095 unsigned int imm_slot;
6096
6097 if (i.tm.opcode_modifier.vexw == VEXW0)
6098 {
6099 /* If VexW0 is set, the third operand is the source and
6100 the second operand is encoded in the immediate
6101 operand. */
6102 source = 2;
6103 reg_slot = 1;
6104 }
6105 else
6106 {
6107 /* VexW1 is set, the second operand is the source and
6108 the third operand is encoded in the immediate
6109 operand. */
6110 source = 1;
6111 reg_slot = 2;
6112 }
6113
6114 if (i.tm.opcode_modifier.immext)
6115 {
6116 /* When ImmExt is set, the immdiate byte is the last
6117 operand. */
6118 imm_slot = i.operands - 1;
6119 source--;
6120 reg_slot--;
6121 }
6122 else
6123 {
6124 imm_slot = 0;
6125
6126 /* Turn on Imm8 so that output_imm will generate it. */
6127 i.types[imm_slot].bitfield.imm8 = 1;
6128 }
6129
24981e7b
L		 6130 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6131 &regxmm)
6132 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6133 &regymm)
6134 || operand_type_equal (&i.tm.operand_types[reg_slot],
6135 &regzmm));
a683cc34 6136 i.op[imm_slot].imms->X_add_number
4c692bc7 6137 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6138 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6139 }
6140
6141 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6142 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 6143 &regymm)
6144 || operand_type_equal (&i.tm.operand_types[nds],
6145 &regzmm));
dae39acc 6146 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6147 }
6148 else
6149 source = dest = 0;
29b0f896
AM		 6150
6151 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6152 implicit registers do not count. If there are 3 register
6153 operands, it must be a instruction with VexNDS. For a
6154 instruction with VexNDD, the destination register is encoded
6155 in VEX prefix. If there are 4 register operands, it must be
6156 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6157 if (i.mem_operands == 0
6158 && ((i.reg_operands == 2
2426c15f 6159 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6160 || (i.reg_operands == 3
2426c15f 6161 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6162 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6163 {
cab737b9
L		 6164 switch (i.operands)
6165 {
6166 case 2:
6167 source = 0;
6168 break;
6169 case 3:
c81128dc
L		 6170 /* When there are 3 operands, one of them may be immediate,
6171 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6172 the first operand must be shift count register (cl) or it
6173 is an instruction with VexNDS. */
9c2799c2 6174 gas_assert (i.imm_operands == 1
7ab9ffdd 6175 || (i.imm_operands == 0
2426c15f 6176 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6177 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6178 if (operand_type_check (i.types[0], imm)
6179 || i.types[0].bitfield.shiftcount)
6180 source = 1;
6181 else
6182 source = 0;
cab737b9
L		 6183 break;
6184 case 4:
368d64cc
L		 6185 /* When there are 4 operands, the first two must be 8bit
6186 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6187 one.
6188
6189 For instructions with VexNDS, if the first operand
6190 an imm8, the source operand is the 2nd one. If the last
6191 operand is imm8, the source operand is the first one. */
9c2799c2 6192 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6193 && i.types[0].bitfield.imm8
6194 && i.types[1].bitfield.imm8)
2426c15f 6195 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6196 && i.imm_operands == 1
6197 && (i.types[0].bitfield.imm8
43234a1e
L		 6198 || i.types[i.operands - 1].bitfield.imm8
6199 || i.rounding)));
9f2670f2
L		 6200 if (i.imm_operands == 2)
6201 source = 2;
6202 else
c0f3af97
L		 6203 {
6204 if (i.types[0].bitfield.imm8)
6205 source = 1;
6206 else
6207 source = 0;
6208 }
c0f3af97
L		 6209 break;
6210 case 5:
43234a1e
L		 6211 if (i.tm.opcode_modifier.evex)
6212 {
6213 /* For EVEX instructions, when there are 5 operands, the
6214 first one must be immediate operand. If the second one
6215 is immediate operand, the source operand is the 3th
6216 one. If the last one is immediate operand, the source
6217 operand is the 2nd one. */
6218 gas_assert (i.imm_operands == 2
6219 && i.tm.opcode_modifier.sae
6220 && operand_type_check (i.types[0], imm));
6221 if (operand_type_check (i.types[1], imm))
6222 source = 2;
6223 else if (operand_type_check (i.types[4], imm))
6224 source = 1;
6225 else
6226 abort ();
6227 }
cab737b9
L		 6228 break;
6229 default:
6230 abort ();
6231 }
6232
c0f3af97
L		 6233 if (!vex_3_sources)
6234 {
6235 dest = source + 1;
6236
43234a1e
L		 6237 /* RC/SAE operand could be between DEST and SRC. That happens
6238 when one operand is GPR and the other one is XMM/YMM/ZMM
6239 register. */
6240 if (i.rounding && i.rounding->operand == (int) dest)
6241 dest++;
6242
2426c15f 6243 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6244 {
43234a1e
L		 6245 /* For instructions with VexNDS, the register-only source
6246 operand must be 32/64bit integer, XMM, YMM or ZMM
6247 register. It is encoded in VEX prefix. We need to
6248 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6249
6250 i386_operand_type op;
6251 unsigned int vvvv;
6252
6253 /* Check register-only source operand when two source
6254 operands are swapped. */
6255 if (!i.tm.operand_types[source].bitfield.baseindex
6256 && i.tm.operand_types[dest].bitfield.baseindex)
6257 {
6258 vvvv = source;
6259 source = dest;
6260 }
6261 else
6262 vvvv = dest;
6263
6264 op = i.tm.operand_types[vvvv];
fa99fab2 6265 op.bitfield.regmem = 0;
c0f3af97 6266 if ((dest + 1) >= i.operands
ac4eb736
AM		 6267 || (!op.bitfield.reg32
6268 && op.bitfield.reg64
f12dc422 6269 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6270 && !operand_type_equal (&op, &regymm)
6271 && !operand_type_equal (&op, &regzmm)
6272 && !operand_type_equal (&op, &regmask)))
c0f3af97 6273 abort ();
f12dc422 6274 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6275 dest++;
6276 }
6277 }
29b0f896
AM		 6278
6279 i.rm.mode = 3;
6280 /* One of the register operands will be encoded in the i.tm.reg
6281 field, the other in the combined i.tm.mode and i.tm.regmem
6282 fields. If no form of this instruction supports a memory
6283 destination operand, then we assume the source operand may
6284 sometimes be a memory operand and so we need to store the
6285 destination in the i.rm.reg field. */
40fb9820
L		 6286 if (!i.tm.operand_types[dest].bitfield.regmem
6287 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6288 {
6289 i.rm.reg = i.op[dest].regs->reg_num;
6290 i.rm.regmem = i.op[source].regs->reg_num;
6291 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6292 i.rex |= REX_R;
43234a1e
L		 6293 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6294 i.vrex |= REX_R;
29b0f896 6295 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6296 i.rex |= REX_B;
43234a1e
L		 6297 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6298 i.vrex |= REX_B;
29b0f896
AM		 6299 }
6300 else
6301 {
6302 i.rm.reg = i.op[source].regs->reg_num;
6303 i.rm.regmem = i.op[dest].regs->reg_num;
6304 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6305 i.rex |= REX_B;
43234a1e
L		 6306 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6307 i.vrex |= REX_B;
29b0f896 6308 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6309 i.rex |= REX_R;
43234a1e
L		 6310 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6311 i.vrex |= REX_R;
29b0f896 6312 }
161a04f6 6313 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6314 {
40fb9820
L		 6315 if (!i.types[0].bitfield.control
6316 && !i.types[1].bitfield.control)
c4a530c5 6317 abort ();
161a04f6 6318 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6319 add_prefix (LOCK_PREFIX_OPCODE);
6320 }
29b0f896
AM		 6321 }
6322 else
6323 { /* If it's not 2 reg operands... */
c0f3af97
L		 6324 unsigned int mem;
6325
29b0f896
AM		 6326 if (i.mem_operands)
6327 {
6328 unsigned int fake_zero_displacement = 0;
99018f42 6329 unsigned int op;
4eed87de 6330
7ab9ffdd
L		 6331 for (op = 0; op < i.operands; op++)
6332 if (operand_type_check (i.types[op], anymem))
6333 break;
7ab9ffdd 6334 gas_assert (op < i.operands);
29b0f896 6335
6c30d220
L		 6336 if (i.tm.opcode_modifier.vecsib)
6337 {
6338 if (i.index_reg->reg_num == RegEiz
6339 || i.index_reg->reg_num == RegRiz)
6340 abort ();
6341
6342 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6343 if (!i.base_reg)
6344 {
6345 i.sib.base = NO_BASE_REGISTER;
6346 i.sib.scale = i.log2_scale_factor;
43234a1e
L		 6347 /* No Vec_Disp8 if there is no base. */
6348 i.types[op].bitfield.vec_disp8 = 0;
6c30d220
L		 6349 i.types[op].bitfield.disp8 = 0;
6350 i.types[op].bitfield.disp16 = 0;
6351 i.types[op].bitfield.disp64 = 0;
6352 if (flag_code != CODE_64BIT)
6353 {
6354 /* Must be 32 bit */
6355 i.types[op].bitfield.disp32 = 1;
6356 i.types[op].bitfield.disp32s = 0;
6357 }
6358 else
6359 {
6360 i.types[op].bitfield.disp32 = 0;
6361 i.types[op].bitfield.disp32s = 1;
6362 }
6363 }
6364 i.sib.index = i.index_reg->reg_num;
6365 if ((i.index_reg->reg_flags & RegRex) != 0)
6366 i.rex |= REX_X;
43234a1e
L		 6367 if ((i.index_reg->reg_flags & RegVRex) != 0)
6368 i.vrex |= REX_X;
6c30d220
L		 6369 }
6370
29b0f896
AM		 6371 default_seg = &ds;
6372
6373 if (i.base_reg == 0)
6374 {
6375 i.rm.mode = 0;
6376 if (!i.disp_operands)
6c30d220
L		 6377 {
6378 fake_zero_displacement = 1;
6379 /* Instructions with VSIB byte need 32bit displacement
6380 if there is no base register. */
6381 if (i.tm.opcode_modifier.vecsib)
6382 i.types[op].bitfield.disp32 = 1;
6383 }
29b0f896
AM		 6384 if (i.index_reg == 0)
6385 {
6c30d220 6386 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6387 /* Operand is just <disp> */
20f0a1fc 6388 if (flag_code == CODE_64BIT)
29b0f896
AM		 6389 {
6390 /* 64bit mode overwrites the 32bit absolute
6391 addressing by RIP relative addressing and
6392 absolute addressing is encoded by one of the
6393 redundant SIB forms. */
6394 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6395 i.sib.base = NO_BASE_REGISTER;
6396 i.sib.index = NO_INDEX_REGISTER;
fc225355 6397 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6398 ? disp32s : disp32);
20f0a1fc 6399 }
fc225355
L		 6400 else if ((flag_code == CODE_16BIT)
6401 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6402 {
6403 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6404 i.types[op] = disp16;
20f0a1fc
NC		 6405 }
6406 else
6407 {
6408 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6409 i.types[op] = disp32;
29b0f896
AM		 6410 }
6411 }
6c30d220 6412 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6413 {
6c30d220 6414 /* !i.base_reg && i.index_reg */
db51cc60
L		 6415 if (i.index_reg->reg_num == RegEiz
6416 || i.index_reg->reg_num == RegRiz)
6417 i.sib.index = NO_INDEX_REGISTER;
6418 else
6419 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6420 i.sib.base = NO_BASE_REGISTER;
6421 i.sib.scale = i.log2_scale_factor;
6422 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
43234a1e
L		 6423 /* No Vec_Disp8 if there is no base. */
6424 i.types[op].bitfield.vec_disp8 = 0;
40fb9820
L		 6425 i.types[op].bitfield.disp8 = 0;
6426 i.types[op].bitfield.disp16 = 0;
6427 i.types[op].bitfield.disp64 = 0;
29b0f896 6428 if (flag_code != CODE_64BIT)
40fb9820
L		 6429 {
6430 /* Must be 32 bit */
6431 i.types[op].bitfield.disp32 = 1;
6432 i.types[op].bitfield.disp32s = 0;
6433 }
29b0f896 6434 else
40fb9820
L		 6435 {
6436 i.types[op].bitfield.disp32 = 0;
6437 i.types[op].bitfield.disp32s = 1;
6438 }
29b0f896 6439 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6440 i.rex |= REX_X;
29b0f896
AM		 6441 }
6442 }
6443 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6444 else if (i.base_reg->reg_num == RegRip ||
6445 i.base_reg->reg_num == RegEip)
29b0f896 6446 {
6c30d220 6447 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6448 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6449 i.types[op].bitfield.disp8 = 0;
6450 i.types[op].bitfield.disp16 = 0;
6451 i.types[op].bitfield.disp32 = 0;
6452 i.types[op].bitfield.disp32s = 1;
6453 i.types[op].bitfield.disp64 = 0;
43234a1e 6454 i.types[op].bitfield.vec_disp8 = 0;
71903a11 6455 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6456 if (! i.disp_operands)
6457 fake_zero_displacement = 1;
29b0f896 6458 }
40fb9820 6459 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 6460 {
6c30d220 6461 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6462 switch (i.base_reg->reg_num)
6463 {
6464 case 3: /* (%bx) */
6465 if (i.index_reg == 0)
6466 i.rm.regmem = 7;
6467 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6468 i.rm.regmem = i.index_reg->reg_num - 6;
6469 break;
6470 case 5: /* (%bp) */
6471 default_seg = &ss;
6472 if (i.index_reg == 0)
6473 {
6474 i.rm.regmem = 6;
40fb9820 6475 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6476 {
6477 /* fake (%bp) into 0(%bp) */
43234a1e
L		 6478 if (i.tm.operand_types[op].bitfield.vec_disp8)
6479 i.types[op].bitfield.vec_disp8 = 1;
6480 else
6481 i.types[op].bitfield.disp8 = 1;
252b5132 6482 fake_zero_displacement = 1;
29b0f896
AM		 6483 }
6484 }
6485 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6486 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6487 break;
6488 default: /* (%si) -> 4 or (%di) -> 5 */
6489 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6490 }
6491 i.rm.mode = mode_from_disp_size (i.types[op]);
6492 }
6493 else /* i.base_reg and 32/64 bit mode */
6494 {
6495 if (flag_code == CODE_64BIT
40fb9820
L		 6496 && operand_type_check (i.types[op], disp))
6497 {
6498 i386_operand_type temp;
0dfbf9d7 6499 operand_type_set (&temp, 0);
40fb9820 6500 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
43234a1e
L		 6501 temp.bitfield.vec_disp8
6502 = i.types[op].bitfield.vec_disp8;
40fb9820
L		 6503 i.types[op] = temp;
6504 if (i.prefix[ADDR_PREFIX] == 0)
6505 i.types[op].bitfield.disp32s = 1;
6506 else
6507 i.types[op].bitfield.disp32 = 1;
6508 }
20f0a1fc 6509
6c30d220
L		 6510 if (!i.tm.opcode_modifier.vecsib)
6511 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6512 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6513 i.rex |= REX_B;
29b0f896
AM		 6514 i.sib.base = i.base_reg->reg_num;
6515 /* x86-64 ignores REX prefix bit here to avoid decoder
6516 complications. */
848930b2
JB		 6517 if (!(i.base_reg->reg_flags & RegRex)
6518 && (i.base_reg->reg_num == EBP_REG_NUM
6519 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6520 default_seg = &ss;
848930b2 6521 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6522 {
848930b2 6523 fake_zero_displacement = 1;
43234a1e
L		 6524 if (i.tm.operand_types [op].bitfield.vec_disp8)
6525 i.types[op].bitfield.vec_disp8 = 1;
6526 else
6527 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6528 }
6529 i.sib.scale = i.log2_scale_factor;
6530 if (i.index_reg == 0)
6531 {
6c30d220 6532 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6533 /* <disp>(%esp) becomes two byte modrm with no index
6534 register. We've already stored the code for esp
6535 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6536 Any base register besides %esp will not use the
6537 extra modrm byte. */
6538 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6539 }
6c30d220 6540 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6541 {
db51cc60
L		 6542 if (i.index_reg->reg_num == RegEiz
6543 || i.index_reg->reg_num == RegRiz)
6544 i.sib.index = NO_INDEX_REGISTER;
6545 else
6546 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6547 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6548 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6549 i.rex |= REX_X;
29b0f896 6550 }
67a4f2b7
AO		 6551
6552 if (i.disp_operands
6553 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6554 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6555 i.rm.mode = 0;
6556 else
a501d77e
L		 6557 {
6558 if (!fake_zero_displacement
6559 && !i.disp_operands
6560 && i.disp_encoding)
6561 {
6562 fake_zero_displacement = 1;
6563 if (i.disp_encoding == disp_encoding_8bit)
6564 i.types[op].bitfield.disp8 = 1;
6565 else
6566 i.types[op].bitfield.disp32 = 1;
6567 }
6568 i.rm.mode = mode_from_disp_size (i.types[op]);
6569 }
29b0f896 6570 }
252b5132 6571
29b0f896
AM		 6572 if (fake_zero_displacement)
6573 {
6574 /* Fakes a zero displacement assuming that i.types[op]
6575 holds the correct displacement size. */
6576 expressionS *exp;
6577
9c2799c2 6578 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6579 exp = &disp_expressions[i.disp_operands++];
6580 i.op[op].disps = exp;
6581 exp->X_op = O_constant;
6582 exp->X_add_number = 0;
6583 exp->X_add_symbol = (symbolS *) 0;
6584 exp->X_op_symbol = (symbolS *) 0;
6585 }
c0f3af97
L		 6586
6587 mem = op;
29b0f896 6588 }
c0f3af97
L		 6589 else
6590 mem = ~0;
252b5132 6591
8c43a48b 6592 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6593 {
6594 if (operand_type_check (i.types[0], imm))
6595 i.vex.register_specifier = NULL;
6596 else
6597 {
6598 /* VEX.vvvv encodes one of the sources when the first
6599 operand is not an immediate. */
1ef99a7b 6600 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6601 i.vex.register_specifier = i.op[0].regs;
6602 else
6603 i.vex.register_specifier = i.op[1].regs;
6604 }
6605
6606 /* Destination is a XMM register encoded in the ModRM.reg
6607 and VEX.R bit. */
6608 i.rm.reg = i.op[2].regs->reg_num;
6609 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6610 i.rex |= REX_R;
6611
6612 /* ModRM.rm and VEX.B encodes the other source. */
6613 if (!i.mem_operands)
6614 {
6615 i.rm.mode = 3;
6616
1ef99a7b 6617 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6618 i.rm.regmem = i.op[1].regs->reg_num;
6619 else
6620 i.rm.regmem = i.op[0].regs->reg_num;
6621
6622 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6623 i.rex |= REX_B;
6624 }
6625 }
2426c15f 6626 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6627 {
6628 i.vex.register_specifier = i.op[2].regs;
6629 if (!i.mem_operands)
6630 {
6631 i.rm.mode = 3;
6632 i.rm.regmem = i.op[1].regs->reg_num;
6633 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6634 i.rex |= REX_B;
6635 }
6636 }
29b0f896
AM		 6637 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6638 (if any) based on i.tm.extension_opcode. Again, we must be
6639 careful to make sure that segment/control/debug/test/MMX
6640 registers are coded into the i.rm.reg field. */
f88c9eb0 6641 else if (i.reg_operands)
29b0f896 6642 {
99018f42 6643 unsigned int op;
7ab9ffdd
L		 6644 unsigned int vex_reg = ~0;
6645
6646 for (op = 0; op < i.operands; op++)
6647 if (i.types[op].bitfield.reg8
6648 || i.types[op].bitfield.reg16
6649 || i.types[op].bitfield.reg32
6650 || i.types[op].bitfield.reg64
6651 || i.types[op].bitfield.regmmx
6652 || i.types[op].bitfield.regxmm
6653 || i.types[op].bitfield.regymm
7e8b059b 6654 || i.types[op].bitfield.regbnd
43234a1e
L		 6655 || i.types[op].bitfield.regzmm
6656 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6657 || i.types[op].bitfield.sreg2
6658 || i.types[op].bitfield.sreg3
6659 || i.types[op].bitfield.control
6660 || i.types[op].bitfield.debug
6661 || i.types[op].bitfield.test)
6662 break;
c0209578 6663
7ab9ffdd
L		 6664 if (vex_3_sources)
6665 op = dest;
2426c15f 6666 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6667 {
6668 /* For instructions with VexNDS, the register-only
6669 source operand is encoded in VEX prefix. */
6670 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6671
7ab9ffdd 6672 if (op > mem)
c0f3af97 6673 {
7ab9ffdd
L		 6674 vex_reg = op++;
6675 gas_assert (op < i.operands);
c0f3af97
L		 6676 }
6677 else
c0f3af97 6678 {
f12dc422
L		 6679 /* Check register-only source operand when two source
6680 operands are swapped. */
6681 if (!i.tm.operand_types[op].bitfield.baseindex
6682 && i.tm.operand_types[op + 1].bitfield.baseindex)
6683 {
6684 vex_reg = op;
6685 op += 2;
6686 gas_assert (mem == (vex_reg + 1)
6687 && op < i.operands);
6688 }
6689 else
6690 {
6691 vex_reg = op + 1;
6692 gas_assert (vex_reg < i.operands);
6693 }
c0f3af97 6694 }
7ab9ffdd 6695 }
2426c15f 6696 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6697 {
f12dc422 6698 /* For instructions with VexNDD, the register destination
7ab9ffdd 6699 is encoded in VEX prefix. */
f12dc422
L		 6700 if (i.mem_operands == 0)
6701 {
6702 /* There is no memory operand. */
6703 gas_assert ((op + 2) == i.operands);
6704 vex_reg = op + 1;
6705 }
6706 else
8d63c93e 6707 {
f12dc422
L		 6708 /* There are only 2 operands. */
6709 gas_assert (op < 2 && i.operands == 2);
6710 vex_reg = 1;
6711 }
7ab9ffdd
L		 6712 }
6713 else
6714 gas_assert (op < i.operands);
99018f42 6715
7ab9ffdd
L		 6716 if (vex_reg != (unsigned int) ~0)
6717 {
f12dc422 6718 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6719
f12dc422
L		 6720 if (type->bitfield.reg32 != 1
6721 && type->bitfield.reg64 != 1
6722 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6723 && !operand_type_equal (type, &regymm)
6724 && !operand_type_equal (type, &regzmm)
6725 && !operand_type_equal (type, &regmask))
7ab9ffdd 6726 abort ();
f88c9eb0 6727
7ab9ffdd
L		 6728 i.vex.register_specifier = i.op[vex_reg].regs;
6729 }
6730
1b9f0c97
L		 6731 /* Don't set OP operand twice. */
6732 if (vex_reg != op)
7ab9ffdd 6733 {
1b9f0c97
L		 6734 /* If there is an extension opcode to put here, the
6735 register number must be put into the regmem field. */
6736 if (i.tm.extension_opcode != None)
6737 {
6738 i.rm.regmem = i.op[op].regs->reg_num;
6739 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6740 i.rex |= REX_B;
43234a1e
L		 6741 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6742 i.vrex |= REX_B;
1b9f0c97
L		 6743 }
6744 else
6745 {
6746 i.rm.reg = i.op[op].regs->reg_num;
6747 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6748 i.rex |= REX_R;
43234a1e
L		 6749 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6750 i.vrex |= REX_R;
1b9f0c97 6751 }
7ab9ffdd 6752 }
252b5132 6753
29b0f896
AM		 6754 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6755 must set it to 3 to indicate this is a register operand
6756 in the regmem field. */
6757 if (!i.mem_operands)
6758 i.rm.mode = 3;
6759 }
252b5132 6760
29b0f896 6761 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6762 if (i.tm.extension_opcode != None)
29b0f896
AM		 6763 i.rm.reg = i.tm.extension_opcode;
6764 }
6765 return default_seg;
6766}
252b5132 6767
29b0f896 6768static void
e3bb37b5 6769output_branch (void)
29b0f896
AM		 6770{
6771 char *p;
f8a5c266 6772 int size;
29b0f896
AM		 6773 int code16;
6774 int prefix;
6775 relax_substateT subtype;
6776 symbolS *sym;
6777 offsetT off;
6778
f8a5c266 6779 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6780 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6781
6782 prefix = 0;
6783 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6784 {
29b0f896
AM		 6785 prefix = 1;
6786 i.prefixes -= 1;
6787 code16 ^= CODE16;
252b5132 6788 }
29b0f896
AM		 6789 /* Pentium4 branch hints. */
6790 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6791 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6792 {
29b0f896
AM		 6793 prefix++;
6794 i.prefixes--;
6795 }
6796 if (i.prefix[REX_PREFIX] != 0)
6797 {
6798 prefix++;
6799 i.prefixes--;
2f66722d
AM		 6800 }
6801
7e8b059b
L		 6802 /* BND prefixed jump. */
6803 if (i.prefix[BND_PREFIX] != 0)
6804 {
6805 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6806 i.prefixes -= 1;
6807 }
6808
29b0f896
AM		 6809 if (i.prefixes != 0 && !intel_syntax)
6810 as_warn (_("skipping prefixes on this instruction"));
6811
6812 /* It's always a symbol; End frag & setup for relax.
6813 Make sure there is enough room in this frag for the largest
6814 instruction we may generate in md_convert_frag. This is 2
6815 bytes for the opcode and room for the prefix and largest
6816 displacement. */
6817 frag_grow (prefix + 2 + 4);
6818 /* Prefix and 1 opcode byte go in fr_fix. */
6819 p = frag_more (prefix + 1);
6820 if (i.prefix[DATA_PREFIX] != 0)
6821 *p++ = DATA_PREFIX_OPCODE;
6822 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6823 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6824 *p++ = i.prefix[SEG_PREFIX];
6825 if (i.prefix[REX_PREFIX] != 0)
6826 *p++ = i.prefix[REX_PREFIX];
6827 *p = i.tm.base_opcode;
6828
6829 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6830 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6831 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6832 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6833 else
f8a5c266 6834 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 6835 subtype |= code16;
3e73aa7c 6836
29b0f896
AM		 6837 sym = i.op[0].disps->X_add_symbol;
6838 off = i.op[0].disps->X_add_number;
3e73aa7c 6839
29b0f896
AM		 6840 if (i.op[0].disps->X_op != O_constant
6841 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 6842 {
29b0f896
AM		 6843 /* Handle complex expressions. */
6844 sym = make_expr_symbol (i.op[0].disps);
6845 off = 0;
6846 }
3e73aa7c 6847
29b0f896
AM		 6848 /* 1 possible extra opcode + 4 byte displacement go in var part.
6849 Pass reloc in fr_var. */
d258b828 6850 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 6851}
3e73aa7c 6852
29b0f896 6853static void
e3bb37b5 6854output_jump (void)
29b0f896
AM		 6855{
6856 char *p;
6857 int size;
3e02c1cc 6858 fixS *fixP;
29b0f896 6859
40fb9820 6860 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 6861 {
6862 /* This is a loop or jecxz type instruction. */
6863 size = 1;
6864 if (i.prefix[ADDR_PREFIX] != 0)
6865 {
6866 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6867 i.prefixes -= 1;
6868 }
6869 /* Pentium4 branch hints. */
6870 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6871 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6872 {
6873 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6874 i.prefixes--;
3e73aa7c
JH		 6875 }
6876 }
29b0f896
AM		 6877 else
6878 {
6879 int code16;
3e73aa7c 6880
29b0f896
AM		 6881 code16 = 0;
6882 if (flag_code == CODE_16BIT)
6883 code16 = CODE16;
3e73aa7c 6884
29b0f896
AM		 6885 if (i.prefix[DATA_PREFIX] != 0)
6886 {
6887 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6888 i.prefixes -= 1;
6889 code16 ^= CODE16;
6890 }
252b5132 6891
29b0f896
AM		 6892 size = 4;
6893 if (code16)
6894 size = 2;
6895 }
9fcc94b6 6896
29b0f896
AM		 6897 if (i.prefix[REX_PREFIX] != 0)
6898 {
6899 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6900 i.prefixes -= 1;
6901 }
252b5132 6902
7e8b059b
L		 6903 /* BND prefixed jump. */
6904 if (i.prefix[BND_PREFIX] != 0)
6905 {
6906 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6907 i.prefixes -= 1;
6908 }
6909
29b0f896
AM		 6910 if (i.prefixes != 0 && !intel_syntax)
6911 as_warn (_("skipping prefixes on this instruction"));
e0890092 6912
42164a71
L		 6913 p = frag_more (i.tm.opcode_length + size);
6914 switch (i.tm.opcode_length)
6915 {
6916 case 2:
6917 *p++ = i.tm.base_opcode >> 8;
6918 case 1:
6919 *p++ = i.tm.base_opcode;
6920 break;
6921 default:
6922 abort ();
6923 }
e0890092 6924
3e02c1cc 6925 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 6926 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3e02c1cc
AM		 6927
6928 /* All jumps handled here are signed, but don't use a signed limit
6929 check for 32 and 16 bit jumps as we want to allow wrap around at
6930 4G and 64k respectively. */
6931 if (size == 1)
6932 fixP->fx_signed = 1;
29b0f896 6933}
e0890092 6934
29b0f896 6935static void
e3bb37b5 6936output_interseg_jump (void)
29b0f896
AM		 6937{
6938 char *p;
6939 int size;
6940 int prefix;
6941 int code16;
252b5132 6942
29b0f896
AM		 6943 code16 = 0;
6944 if (flag_code == CODE_16BIT)
6945 code16 = CODE16;
a217f122 6946
29b0f896
AM		 6947 prefix = 0;
6948 if (i.prefix[DATA_PREFIX] != 0)
6949 {
6950 prefix = 1;
6951 i.prefixes -= 1;
6952 code16 ^= CODE16;
6953 }
6954 if (i.prefix[REX_PREFIX] != 0)
6955 {
6956 prefix++;
6957 i.prefixes -= 1;
6958 }
252b5132 6959
29b0f896
AM		 6960 size = 4;
6961 if (code16)
6962 size = 2;
252b5132 6963
29b0f896
AM		 6964 if (i.prefixes != 0 && !intel_syntax)
6965 as_warn (_("skipping prefixes on this instruction"));
252b5132 6966
29b0f896
AM		 6967 /* 1 opcode; 2 segment; offset */
6968 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 6969
29b0f896
AM		 6970 if (i.prefix[DATA_PREFIX] != 0)
6971 *p++ = DATA_PREFIX_OPCODE;
252b5132 6972
29b0f896
AM		 6973 if (i.prefix[REX_PREFIX] != 0)
6974 *p++ = i.prefix[REX_PREFIX];
252b5132 6975
29b0f896
AM		 6976 *p++ = i.tm.base_opcode;
6977 if (i.op[1].imms->X_op == O_constant)
6978 {
6979 offsetT n = i.op[1].imms->X_add_number;
252b5132 6980
29b0f896
AM		 6981 if (size == 2
6982 && !fits_in_unsigned_word (n)
6983 && !fits_in_signed_word (n))
6984 {
6985 as_bad (_("16-bit jump out of range"));
6986 return;
6987 }
6988 md_number_to_chars (p, n, size);
6989 }
6990 else
6991 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 6992 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 6993 if (i.op[0].imms->X_op != O_constant)
6994 as_bad (_("can't handle non absolute segment in `%s'"),
6995 i.tm.name);
6996 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6997}
a217f122 6998
29b0f896 6999static void
e3bb37b5 7000output_insn (void)
29b0f896 7001{
2bbd9c25
JJ		 7002 fragS *insn_start_frag;
7003 offsetT insn_start_off;
7004
29b0f896
AM		 7005 /* Tie dwarf2 debug info to the address at the start of the insn.
7006 We can't do this after the insn has been output as the current
7007 frag may have been closed off. eg. by frag_var. */
7008 dwarf2_emit_insn (0);
7009
2bbd9c25
JJ		 7010 insn_start_frag = frag_now;
7011 insn_start_off = frag_now_fix ();
7012
29b0f896 7013 /* Output jumps. */
40fb9820 7014 if (i.tm.opcode_modifier.jump)
29b0f896 7015 output_branch ();
40fb9820
L		 7016 else if (i.tm.opcode_modifier.jumpbyte
7017 || i.tm.opcode_modifier.jumpdword)
29b0f896 7018 output_jump ();
40fb9820 7019 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 7020 output_interseg_jump ();
7021 else
7022 {
7023 /* Output normal instructions here. */
7024 char *p;
7025 unsigned char *q;
47465058 7026 unsigned int j;
331d2d0d 7027 unsigned int prefix;
4dffcebc 7028
e4e00185
AS		 7029 if (avoid_fence
7030 && i.tm.base_opcode == 0xfae
7031 && i.operands == 1
7032 && i.imm_operands == 1
7033 && (i.op[0].imms->X_add_number == 0xe8
7034 || i.op[0].imms->X_add_number == 0xf0
7035 || i.op[0].imms->X_add_number == 0xf8))
7036 {
7037 /* Encode lfence, mfence, and sfence as
7038 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7039 offsetT val = 0x240483f0ULL;
7040 p = frag_more (5);
7041 md_number_to_chars (p, val, 5);
7042 return;
7043 }
7044
d022bddd
IT		 7045 /* Some processors fail on LOCK prefix. This options makes
7046 assembler ignore LOCK prefix and serves as a workaround. */
7047 if (omit_lock_prefix)
7048 {
7049 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7050 return;
7051 i.prefix[LOCK_PREFIX] = 0;
7052 }
7053
43234a1e
L		 7054 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7055 don't need the explicit prefix. */
7056 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 7057 {
c0f3af97 7058 switch (i.tm.opcode_length)
bc4bd9ab 7059 {
c0f3af97
L		 7060 case 3:
7061 if (i.tm.base_opcode & 0xff000000)
4dffcebc 7062 {
c0f3af97
L		 7063 prefix = (i.tm.base_opcode >> 24) & 0xff;
7064 goto check_prefix;
7065 }
7066 break;
7067 case 2:
7068 if ((i.tm.base_opcode & 0xff0000) != 0)
7069 {
7070 prefix = (i.tm.base_opcode >> 16) & 0xff;
7071 if (i.tm.cpu_flags.bitfield.cpupadlock)
7072 {
4dffcebc 7073check_prefix:
c0f3af97 7074 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 7075 || (i.prefix[REP_PREFIX]
c0f3af97
L		 7076 != REPE_PREFIX_OPCODE))
7077 add_prefix (prefix);
7078 }
7079 else
4dffcebc
L		 7080 add_prefix (prefix);
7081 }
c0f3af97
L		 7082 break;
7083 case 1:
7084 break;
7085 default:
7086 abort ();
bc4bd9ab 7087 }
c0f3af97 7088
6d19a37a 7089#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 7090 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7091 R_X86_64_GOTTPOFF relocation so that linker can safely
7092 perform IE->LE optimization. */
7093 if (x86_elf_abi == X86_64_X32_ABI
7094 && i.operands == 2
7095 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7096 && i.prefix[REX_PREFIX] == 0)
7097 add_prefix (REX_OPCODE);
6d19a37a 7098#endif
cf61b747 7099
c0f3af97
L		 7100 /* The prefix bytes. */
7101 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7102 if (*q)
7103 FRAG_APPEND_1_CHAR (*q);
0f10071e 7104 }
ae5c1c7b 7105 else
c0f3af97
L		 7106 {
7107 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7108 if (*q)
7109 switch (j)
7110 {
7111 case REX_PREFIX:
7112 /* REX byte is encoded in VEX prefix. */
7113 break;
7114 case SEG_PREFIX:
7115 case ADDR_PREFIX:
7116 FRAG_APPEND_1_CHAR (*q);
7117 break;
7118 default:
7119 /* There should be no other prefixes for instructions
7120 with VEX prefix. */
7121 abort ();
7122 }
7123
43234a1e
L		 7124 /* For EVEX instructions i.vrex should become 0 after
7125 build_evex_prefix. For VEX instructions upper 16 registers
7126 aren't available, so VREX should be 0. */
7127 if (i.vrex)
7128 abort ();
c0f3af97
L		 7129 /* Now the VEX prefix. */
7130 p = frag_more (i.vex.length);
7131 for (j = 0; j < i.vex.length; j++)
7132 p[j] = i.vex.bytes[j];
7133 }
252b5132 7134
29b0f896 7135 /* Now the opcode; be careful about word order here! */
4dffcebc 7136 if (i.tm.opcode_length == 1)
29b0f896
AM		 7137 {
7138 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7139 }
7140 else
7141 {
4dffcebc 7142 switch (i.tm.opcode_length)
331d2d0d 7143 {
43234a1e
L		 7144 case 4:
7145 p = frag_more (4);
7146 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7147 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7148 break;
4dffcebc 7149 case 3:
331d2d0d
L		 7150 p = frag_more (3);
7151 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7152 break;
7153 case 2:
7154 p = frag_more (2);
7155 break;
7156 default:
7157 abort ();
7158 break;
331d2d0d 7159 }
0f10071e 7160
29b0f896
AM		 7161 /* Put out high byte first: can't use md_number_to_chars! */
7162 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7163 *p = i.tm.base_opcode & 0xff;
7164 }
3e73aa7c 7165
29b0f896 7166 /* Now the modrm byte and sib byte (if present). */
40fb9820 7167 if (i.tm.opcode_modifier.modrm)
29b0f896 7168 {
4a3523fa
L		 7169 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7170 | i.rm.reg << 3
7171 | i.rm.mode << 6));
29b0f896
AM		 7172 /* If i.rm.regmem == ESP (4)
7173 && i.rm.mode != (Register mode)
7174 && not 16 bit
7175 ==> need second modrm byte. */
7176 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7177 && i.rm.mode != 3
40fb9820 7178 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 7179 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7180 | i.sib.index << 3
7181 | i.sib.scale << 6));
29b0f896 7182 }
3e73aa7c 7183
29b0f896 7184 if (i.disp_operands)
2bbd9c25 7185 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7186
29b0f896 7187 if (i.imm_operands)
2bbd9c25 7188 output_imm (insn_start_frag, insn_start_off);
29b0f896 7189 }
252b5132 7190
29b0f896
AM		 7191#ifdef DEBUG386
7192 if (flag_debug)
7193 {
7b81dfbb 7194 pi ("" /*line*/, &i);
29b0f896
AM		 7195 }
7196#endif /* DEBUG386 */
7197}
252b5132 7198
e205caa7
L		 7199/* Return the size of the displacement operand N. */
7200
7201static int
7202disp_size (unsigned int n)
7203{
7204 int size = 4;
43234a1e
L		 7205
7206 /* Vec_Disp8 has to be 8bit. */
7207 if (i.types[n].bitfield.vec_disp8)
7208 size = 1;
7209 else if (i.types[n].bitfield.disp64)
40fb9820
L		 7210 size = 8;
7211 else if (i.types[n].bitfield.disp8)
7212 size = 1;
7213 else if (i.types[n].bitfield.disp16)
7214 size = 2;
e205caa7
L		 7215 return size;
7216}
7217
7218/* Return the size of the immediate operand N. */
7219
7220static int
7221imm_size (unsigned int n)
7222{
7223 int size = 4;
40fb9820
L		 7224 if (i.types[n].bitfield.imm64)
7225 size = 8;
7226 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7227 size = 1;
7228 else if (i.types[n].bitfield.imm16)
7229 size = 2;
e205caa7
L		 7230 return size;
7231}
7232
29b0f896 7233static void
64e74474 7234output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7235{
7236 char *p;
7237 unsigned int n;
252b5132 7238
29b0f896
AM		 7239 for (n = 0; n < i.operands; n++)
7240 {
43234a1e
L		 7241 if (i.types[n].bitfield.vec_disp8
7242 || operand_type_check (i.types[n], disp))
29b0f896
AM		 7243 {
7244 if (i.op[n].disps->X_op == O_constant)
7245 {
e205caa7 7246 int size = disp_size (n);
43234a1e 7247 offsetT val = i.op[n].disps->X_add_number;
252b5132 7248
43234a1e
L		 7249 if (i.types[n].bitfield.vec_disp8)
7250 val >>= i.memshift;
7251 val = offset_in_range (val, size);
29b0f896
AM		 7252 p = frag_more (size);
7253 md_number_to_chars (p, val, size);
7254 }
7255 else
7256 {
f86103b7 7257 enum bfd_reloc_code_real reloc_type;
e205caa7 7258 int size = disp_size (n);
40fb9820 7259 int sign = i.types[n].bitfield.disp32s;
29b0f896 7260 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
02a86693 7261 fixS *fixP;
29b0f896 7262
e205caa7 7263 /* We can't have 8 bit displacement here. */
9c2799c2 7264 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7265
29b0f896
AM		 7266 /* The PC relative address is computed relative
7267 to the instruction boundary, so in case immediate
7268 fields follows, we need to adjust the value. */
7269 if (pcrel && i.imm_operands)
7270 {
29b0f896 7271 unsigned int n1;
e205caa7 7272 int sz = 0;
252b5132 7273
29b0f896 7274 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7275 if (operand_type_check (i.types[n1], imm))
252b5132 7276 {
e205caa7
L		 7277 /* Only one immediate is allowed for PC
7278 relative address. */
9c2799c2 7279 gas_assert (sz == 0);
e205caa7
L		 7280 sz = imm_size (n1);
7281 i.op[n].disps->X_add_number -= sz;
252b5132 7282 }
29b0f896 7283 /* We should find the immediate. */
9c2799c2 7284 gas_assert (sz != 0);
29b0f896 7285 }
520dc8e8 7286
29b0f896 7287 p = frag_more (size);
d258b828 7288 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7289 if (GOT_symbol
2bbd9c25 7290 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7291 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7292 || reloc_type == BFD_RELOC_X86_64_32S
7293 || (reloc_type == BFD_RELOC_64
7294 && object_64bit))
d6ab8113
JB		 7295 && (i.op[n].disps->X_op == O_symbol
7296 || (i.op[n].disps->X_op == O_add
7297 && ((symbol_get_value_expression
7298 (i.op[n].disps->X_op_symbol)->X_op)
7299 == O_subtract))))
7300 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7301 {
7302 offsetT add;
7303
7304 if (insn_start_frag == frag_now)
7305 add = (p - frag_now->fr_literal) - insn_start_off;
7306 else
7307 {
7308 fragS *fr;
7309
7310 add = insn_start_frag->fr_fix - insn_start_off;
7311 for (fr = insn_start_frag->fr_next;
7312 fr && fr != frag_now; fr = fr->fr_next)
7313 add += fr->fr_fix;
7314 add += p - frag_now->fr_literal;
7315 }
7316
4fa24527 7317 if (!object_64bit)
7b81dfbb
AJ		 7318 {
7319 reloc_type = BFD_RELOC_386_GOTPC;
7320 i.op[n].imms->X_add_number += add;
7321 }
7322 else if (reloc_type == BFD_RELOC_64)
7323 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7324 else
7b81dfbb
AJ		 7325 /* Don't do the adjustment for x86-64, as there
7326 the pcrel addressing is relative to the _next_
7327 insn, and that is taken care of in other code. */
d6ab8113 7328 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7329 }
02a86693
L		 7330 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7331 size, i.op[n].disps, pcrel,
7332 reloc_type);
7333 /* Check for "call/jmp *mem", "mov mem, %reg",
7334 "test %reg, mem" and "binop mem, %reg" where binop
7335 is one of adc, add, and, cmp, or, sbb, sub, xor
0cb4071e
L		 7336 instructions. Always generate R_386_GOT32X for
7337 "sym*GOT" operand in 32-bit mode. */
7338 if ((generate_relax_relocations
7339 || (!object_64bit
7340 && i.rm.mode == 0
7341 && i.rm.regmem == 5))
7342 && (i.rm.mode == 2
7343 || (i.rm.mode == 0 && i.rm.regmem == 5))
02a86693
L		 7344 && ((i.operands == 1
7345 && i.tm.base_opcode == 0xff
7346 && (i.rm.reg == 2 || i.rm.reg == 4))
7347 || (i.operands == 2
7348 && (i.tm.base_opcode == 0x8b
7349 || i.tm.base_opcode == 0x85
7350 || (i.tm.base_opcode & 0xc7) == 0x03))))
7351 {
7352 if (object_64bit)
7353 {
7354 fixP->fx_tcbit = i.rex != 0;
7355 if (i.base_reg
7356 && (i.base_reg->reg_num == RegRip
7357 || i.base_reg->reg_num == RegEip))
7358 fixP->fx_tcbit2 = 1;
7359 }
7360 else
7361 fixP->fx_tcbit2 = 1;
7362 }
29b0f896
AM		 7363 }
7364 }
7365 }
7366}
252b5132 7367
29b0f896 7368static void
64e74474 7369output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7370{
7371 char *p;
7372 unsigned int n;
252b5132 7373
29b0f896
AM		 7374 for (n = 0; n < i.operands; n++)
7375 {
43234a1e
L		 7376 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7377 if (i.rounding && (int) n == i.rounding->operand)
7378 continue;
7379
40fb9820 7380 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7381 {
7382 if (i.op[n].imms->X_op == O_constant)
7383 {
e205caa7 7384 int size = imm_size (n);
29b0f896 7385 offsetT val;
b4cac588 7386
29b0f896
AM		 7387 val = offset_in_range (i.op[n].imms->X_add_number,
7388 size);
7389 p = frag_more (size);
7390 md_number_to_chars (p, val, size);
7391 }
7392 else
7393 {
7394 /* Not absolute_section.
7395 Need a 32-bit fixup (don't support 8bit
7396 non-absolute imms). Try to support other
7397 sizes ... */
f86103b7 7398 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7399 int size = imm_size (n);
7400 int sign;
29b0f896 7401
40fb9820 7402 if (i.types[n].bitfield.imm32s
a7d61044 7403 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7404 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7405 sign = 1;
e205caa7
L		 7406 else
7407 sign = 0;
520dc8e8 7408
29b0f896 7409 p = frag_more (size);
d258b828 7410 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 7411
2bbd9c25
JJ		 7412 /* This is tough to explain. We end up with this one if we
7413 * have operands that look like
7414 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7415 * obtain the absolute address of the GOT, and it is strongly
7416 * preferable from a performance point of view to avoid using
7417 * a runtime relocation for this. The actual sequence of
7418 * instructions often look something like:
7419 *
7420 * call .L66
7421 * .L66:
7422 * popl %ebx
7423 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7424 *
7425 * The call and pop essentially return the absolute address
7426 * of the label .L66 and store it in %ebx. The linker itself
7427 * will ultimately change the first operand of the addl so
7428 * that %ebx points to the GOT, but to keep things simple, the
7429 * .o file must have this operand set so that it generates not
7430 * the absolute address of .L66, but the absolute address of
7431 * itself. This allows the linker itself simply treat a GOTPC
7432 * relocation as asking for a pcrel offset to the GOT to be
7433 * added in, and the addend of the relocation is stored in the
7434 * operand field for the instruction itself.
7435 *
7436 * Our job here is to fix the operand so that it would add
7437 * the correct offset so that %ebx would point to itself. The
7438 * thing that is tricky is that .-.L66 will point to the
7439 * beginning of the instruction, so we need to further modify
7440 * the operand so that it will point to itself. There are
7441 * other cases where you have something like:
7442 *
7443 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7444 *
7445 * and here no correction would be required. Internally in
7446 * the assembler we treat operands of this form as not being
7447 * pcrel since the '.' is explicitly mentioned, and I wonder
7448 * whether it would simplify matters to do it this way. Who
7449 * knows. In earlier versions of the PIC patches, the
7450 * pcrel_adjust field was used to store the correction, but
7451 * since the expression is not pcrel, I felt it would be
7452 * confusing to do it this way. */
7453
d6ab8113 7454 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7455 || reloc_type == BFD_RELOC_X86_64_32S
7456 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7457 && GOT_symbol
7458 && GOT_symbol == i.op[n].imms->X_add_symbol
7459 && (i.op[n].imms->X_op == O_symbol
7460 || (i.op[n].imms->X_op == O_add
7461 && ((symbol_get_value_expression
7462 (i.op[n].imms->X_op_symbol)->X_op)
7463 == O_subtract))))
7464 {
2bbd9c25
JJ		 7465 offsetT add;
7466
7467 if (insn_start_frag == frag_now)
7468 add = (p - frag_now->fr_literal) - insn_start_off;
7469 else
7470 {
7471 fragS *fr;
7472
7473 add = insn_start_frag->fr_fix - insn_start_off;
7474 for (fr = insn_start_frag->fr_next;
7475 fr && fr != frag_now; fr = fr->fr_next)
7476 add += fr->fr_fix;
7477 add += p - frag_now->fr_literal;
7478 }
7479
4fa24527 7480 if (!object_64bit)
d6ab8113 7481 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7482 else if (size == 4)
d6ab8113 7483 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7484 else if (size == 8)
7485 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7486 i.op[n].imms->X_add_number += add;
29b0f896 7487 }
29b0f896
AM		 7488 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7489 i.op[n].imms, 0, reloc_type);
7490 }
7491 }
7492 }
252b5132
RH		 7493}
7494\f
d182319b
JB		 7495/* x86_cons_fix_new is called via the expression parsing code when a
7496 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 7497static int cons_sign = -1;
7498
7499void
e3bb37b5 7500x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 7501 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 7502{
d258b828 7503 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 7504
7505#ifdef TE_PE
7506 if (exp->X_op == O_secrel)
7507 {
7508 exp->X_op = O_symbol;
7509 r = BFD_RELOC_32_SECREL;
7510 }
7511#endif
7512
7513 fix_new_exp (frag, off, len, exp, 0, r);
7514}
7515
357d1bd8
L		 7516/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7517 purpose of the `.dc.a' internal pseudo-op. */
7518
7519int
7520x86_address_bytes (void)
7521{
7522 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7523 return 4;
7524 return stdoutput->arch_info->bits_per_address / 8;
7525}
7526
d382c579
TG		 7527#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7528 || defined (LEX_AT)
d258b828 7529# define lex_got(reloc, adjust, types) NULL
718ddfc0 7530#else
f3c180ae
AM		 7531/* Parse operands of the form
7532 <symbol>@GOTOFF+<nnn>
7533 and similar .plt or .got references.
7534
7535 If we find one, set up the correct relocation in RELOC and copy the
7536 input string, minus the `@GOTOFF' into a malloc'd buffer for
7537 parsing by the calling routine. Return this buffer, and if ADJUST
7538 is non-null set it to the length of the string we removed from the
7539 input line. Otherwise return NULL. */
7540static char *
91d6fa6a 7541lex_got (enum bfd_reloc_code_real *rel,
64e74474 7542 int *adjust,
d258b828 7543 i386_operand_type *types)
f3c180ae 7544{
7b81dfbb
AJ		 7545 /* Some of the relocations depend on the size of what field is to
7546 be relocated. But in our callers i386_immediate and i386_displacement
7547 we don't yet know the operand size (this will be set by insn
7548 matching). Hence we record the word32 relocation here,
7549 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7550 static const struct {
7551 const char *str;
cff8d58a 7552 int len;
4fa24527 7553 const enum bfd_reloc_code_real rel[2];
40fb9820 7554 const i386_operand_type types64;
f3c180ae 7555 } gotrel[] = {
8ce3d284 7556#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7557 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7558 BFD_RELOC_SIZE32 },
7559 OPERAND_TYPE_IMM32_64 },
8ce3d284 7560#endif
cff8d58a
L		 7561 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7562 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7563 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7564 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7565 BFD_RELOC_X86_64_PLT32 },
40fb9820 7566 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7567 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7568 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7569 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7570 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7571 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7572 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7573 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7574 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7575 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7576 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7577 BFD_RELOC_X86_64_TLSGD },
40fb9820 7578 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7579 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7580 _dummy_first_bfd_reloc_code_real },
40fb9820 7581 OPERAND_TYPE_NONE },
cff8d58a
L		 7582 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7583 BFD_RELOC_X86_64_TLSLD },
40fb9820 7584 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7585 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7586 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7587 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7588 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7589 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7590 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7591 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7592 _dummy_first_bfd_reloc_code_real },
40fb9820 7593 OPERAND_TYPE_NONE },
cff8d58a
L		 7594 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7595 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7596 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7597 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7598 _dummy_first_bfd_reloc_code_real },
40fb9820 7599 OPERAND_TYPE_NONE },
cff8d58a
L		 7600 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7601 _dummy_first_bfd_reloc_code_real },
40fb9820 7602 OPERAND_TYPE_NONE },
cff8d58a
L		 7603 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7604 BFD_RELOC_X86_64_GOT32 },
40fb9820 7605 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7606 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7607 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7608 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7609 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7610 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7611 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7612 };
7613 char *cp;
7614 unsigned int j;
7615
d382c579 7616#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7617 if (!IS_ELF)
7618 return NULL;
d382c579 7619#endif
718ddfc0 7620
f3c180ae 7621 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7622 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7623 return NULL;
7624
47465058 7625 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7626 {
cff8d58a 7627 int len = gotrel[j].len;
28f81592 7628 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7629 {
4fa24527 7630 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7631 {
28f81592
AM		 7632 int first, second;
7633 char *tmpbuf, *past_reloc;
f3c180ae 7634
91d6fa6a 7635 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7636
3956db08
JB		 7637 if (types)
7638 {
7639 if (flag_code != CODE_64BIT)
40fb9820
L		 7640 {
7641 types->bitfield.imm32 = 1;
7642 types->bitfield.disp32 = 1;
7643 }
3956db08
JB		 7644 else
7645 *types = gotrel[j].types64;
7646 }
7647
8fd4256d 7648 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7649 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7650
28f81592 7651 /* The length of the first part of our input line. */
f3c180ae 7652 first = cp - input_line_pointer;
28f81592
AM		 7653
7654 /* The second part goes from after the reloc token until
67c11a9b 7655 (and including) an end_of_line char or comma. */
28f81592 7656 past_reloc = cp + 1 + len;
67c11a9b
AM		 7657 cp = past_reloc;
7658 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7659 ++cp;
7660 second = cp + 1 - past_reloc;
28f81592
AM		 7661
7662 /* Allocate and copy string. The trailing NUL shouldn't
7663 be necessary, but be safe. */
add39d23 7664 tmpbuf = XNEWVEC (char, first + second + 2);
f3c180ae 7665 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7666 if (second != 0 && *past_reloc != ' ')
7667 /* Replace the relocation token with ' ', so that
7668 errors like foo@GOTOFF1 will be detected. */
7669 tmpbuf[first++] = ' ';
af89796a
L		 7670 else
7671 /* Increment length by 1 if the relocation token is
7672 removed. */
7673 len++;
7674 if (adjust)
7675 *adjust = len;
0787a12d
AM		 7676 memcpy (tmpbuf + first, past_reloc, second);
7677 tmpbuf[first + second] = '\0';
f3c180ae
AM		 7678 return tmpbuf;
7679 }
7680
4fa24527
JB		 7681 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7682 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7683 return NULL;
7684 }
7685 }
7686
7687 /* Might be a symbol version string. Don't as_bad here. */
7688 return NULL;
7689}
4e4f7c87 7690#endif
f3c180ae 7691
a988325c
NC		 7692#ifdef TE_PE
7693#ifdef lex_got
7694#undef lex_got
7695#endif
7696/* Parse operands of the form
7697 <symbol>@SECREL32+<nnn>
7698
7699 If we find one, set up the correct relocation in RELOC and copy the
7700 input string, minus the `@SECREL32' into a malloc'd buffer for
7701 parsing by the calling routine. Return this buffer, and if ADJUST
7702 is non-null set it to the length of the string we removed from the
34bca508
L		 7703 input line. Otherwise return NULL.
7704
a988325c
NC		 7705 This function is copied from the ELF version above adjusted for PE targets. */
7706
7707static char *
7708lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7709 int *adjust ATTRIBUTE_UNUSED,
d258b828 7710 i386_operand_type *types)
a988325c
NC		 7711{
7712 static const struct
7713 {
7714 const char *str;
7715 int len;
7716 const enum bfd_reloc_code_real rel[2];
7717 const i386_operand_type types64;
7718 }
7719 gotrel[] =
7720 {
7721 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7722 BFD_RELOC_32_SECREL },
7723 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7724 };
7725
7726 char *cp;
7727 unsigned j;
7728
7729 for (cp = input_line_pointer; *cp != '@'; cp++)
7730 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7731 return NULL;
7732
7733 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7734 {
7735 int len = gotrel[j].len;
7736
7737 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7738 {
7739 if (gotrel[j].rel[object_64bit] != 0)
7740 {
7741 int first, second;
7742 char *tmpbuf, *past_reloc;
7743
7744 *rel = gotrel[j].rel[object_64bit];
7745 if (adjust)
7746 *adjust = len;
7747
7748 if (types)
7749 {
7750 if (flag_code != CODE_64BIT)
7751 {
7752 types->bitfield.imm32 = 1;
7753 types->bitfield.disp32 = 1;
7754 }
7755 else
7756 *types = gotrel[j].types64;
7757 }
7758
7759 /* The length of the first part of our input line. */
7760 first = cp - input_line_pointer;
7761
7762 /* The second part goes from after the reloc token until
7763 (and including) an end_of_line char or comma. */
7764 past_reloc = cp + 1 + len;
7765 cp = past_reloc;
7766 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7767 ++cp;
7768 second = cp + 1 - past_reloc;
7769
7770 /* Allocate and copy string. The trailing NUL shouldn't
7771 be necessary, but be safe. */
add39d23 7772 tmpbuf = XNEWVEC (char, first + second + 2);
a988325c
NC		 7773 memcpy (tmpbuf, input_line_pointer, first);
7774 if (second != 0 && *past_reloc != ' ')
7775 /* Replace the relocation token with ' ', so that
7776 errors like foo@SECLREL321 will be detected. */
7777 tmpbuf[first++] = ' ';
7778 memcpy (tmpbuf + first, past_reloc, second);
7779 tmpbuf[first + second] = '\0';
7780 return tmpbuf;
7781 }
7782
7783 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7784 gotrel[j].str, 1 << (5 + object_64bit));
7785 return NULL;
7786 }
7787 }
7788
7789 /* Might be a symbol version string. Don't as_bad here. */
7790 return NULL;
7791}
7792
7793#endif /* TE_PE */
7794
62ebcb5c 7795bfd_reloc_code_real_type
e3bb37b5 7796x86_cons (expressionS *exp, int size)
f3c180ae 7797{
62ebcb5c
AM		 7798 bfd_reloc_code_real_type got_reloc = NO_RELOC;
7799
ee86248c
JB		 7800 intel_syntax = -intel_syntax;
7801
3c7b9c2c 7802 exp->X_md = 0;
4fa24527 7803 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 7804 {
7805 /* Handle @GOTOFF and the like in an expression. */
7806 char *save;
7807 char *gotfree_input_line;
4a57f2cf 7808 int adjust = 0;
f3c180ae
AM		 7809
7810 save = input_line_pointer;
d258b828 7811 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 7812 if (gotfree_input_line)
7813 input_line_pointer = gotfree_input_line;
7814
7815 expression (exp);
7816
7817 if (gotfree_input_line)
7818 {
7819 /* expression () has merrily parsed up to the end of line,
7820 or a comma - in the wrong buffer. Transfer how far
7821 input_line_pointer has moved to the right buffer. */
7822 input_line_pointer = (save
7823 + (input_line_pointer - gotfree_input_line)
7824 + adjust);
7825 free (gotfree_input_line);
3992d3b7
AM		 7826 if (exp->X_op == O_constant
7827 || exp->X_op == O_absent
7828 || exp->X_op == O_illegal
0398aac5 7829 || exp->X_op == O_register
3992d3b7
AM		 7830 || exp->X_op == O_big)
7831 {
7832 char c = *input_line_pointer;
7833 *input_line_pointer = 0;
7834 as_bad (_("missing or invalid expression `%s'"), save);
7835 *input_line_pointer = c;
7836 }
f3c180ae
AM		 7837 }
7838 }
7839 else
7840 expression (exp);
ee86248c
JB		 7841
7842 intel_syntax = -intel_syntax;
7843
7844 if (intel_syntax)
7845 i386_intel_simplify (exp);
62ebcb5c
AM		 7846
7847 return got_reloc;
f3c180ae 7848}
f3c180ae 7849
9f32dd5b
L		 7850static void
7851signed_cons (int size)
6482c264 7852{
d182319b
JB		 7853 if (flag_code == CODE_64BIT)
7854 cons_sign = 1;
7855 cons (size);
7856 cons_sign = -1;
6482c264
NC		 7857}
7858
d182319b 7859#ifdef TE_PE
6482c264 7860static void
7016a5d5 7861pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 7862{
7863 expressionS exp;
7864
7865 do
7866 {
7867 expression (&exp);
7868 if (exp.X_op == O_symbol)
7869 exp.X_op = O_secrel;
7870
7871 emit_expr (&exp, 4);
7872 }
7873 while (*input_line_pointer++ == ',');
7874
7875 input_line_pointer--;
7876 demand_empty_rest_of_line ();
7877}
6482c264
NC		 7878#endif
7879
43234a1e
L		 7880/* Handle Vector operations. */
7881
7882static char *
7883check_VecOperations (char *op_string, char *op_end)
7884{
7885 const reg_entry *mask;
7886 const char *saved;
7887 char *end_op;
7888
7889 while (*op_string
7890 && (op_end == NULL || op_string < op_end))
7891 {
7892 saved = op_string;
7893 if (*op_string == '{')
7894 {
7895 op_string++;
7896
7897 /* Check broadcasts. */
7898 if (strncmp (op_string, "1to", 3) == 0)
7899 {
7900 int bcst_type;
7901
7902 if (i.broadcast)
7903 goto duplicated_vec_op;
7904
7905 op_string += 3;
7906 if (*op_string == '8')
7907 bcst_type = BROADCAST_1TO8;
b28d1bda
IT		 7908 else if (*op_string == '4')
7909 bcst_type = BROADCAST_1TO4;
7910 else if (*op_string == '2')
7911 bcst_type = BROADCAST_1TO2;
43234a1e
L		 7912 else if (*op_string == '1'
7913 && *(op_string+1) == '6')
7914 {
7915 bcst_type = BROADCAST_1TO16;
7916 op_string++;
7917 }
7918 else
7919 {
7920 as_bad (_("Unsupported broadcast: `%s'"), saved);
7921 return NULL;
7922 }
7923 op_string++;
7924
7925 broadcast_op.type = bcst_type;
7926 broadcast_op.operand = this_operand;
7927 i.broadcast = &broadcast_op;
7928 }
7929 /* Check masking operation. */
7930 else if ((mask = parse_register (op_string, &end_op)) != NULL)
7931 {
7932 /* k0 can't be used for write mask. */
7933 if (mask->reg_num == 0)
7934 {
7935 as_bad (_("`%s' can't be used for write mask"),
7936 op_string);
7937 return NULL;
7938 }
7939
7940 if (!i.mask)
7941 {
7942 mask_op.mask = mask;
7943 mask_op.zeroing = 0;
7944 mask_op.operand = this_operand;
7945 i.mask = &mask_op;
7946 }
7947 else
7948 {
7949 if (i.mask->mask)
7950 goto duplicated_vec_op;
7951
7952 i.mask->mask = mask;
7953
7954 /* Only "{z}" is allowed here. No need to check
7955 zeroing mask explicitly. */
7956 if (i.mask->operand != this_operand)
7957 {
7958 as_bad (_("invalid write mask `%s'"), saved);
7959 return NULL;
7960 }
7961 }
7962
7963 op_string = end_op;
7964 }
7965 /* Check zeroing-flag for masking operation. */
7966 else if (*op_string == 'z')
7967 {
7968 if (!i.mask)
7969 {
7970 mask_op.mask = NULL;
7971 mask_op.zeroing = 1;
7972 mask_op.operand = this_operand;
7973 i.mask = &mask_op;
7974 }
7975 else
7976 {
7977 if (i.mask->zeroing)
7978 {
7979 duplicated_vec_op:
7980 as_bad (_("duplicated `%s'"), saved);
7981 return NULL;
7982 }
7983
7984 i.mask->zeroing = 1;
7985
7986 /* Only "{%k}" is allowed here. No need to check mask
7987 register explicitly. */
7988 if (i.mask->operand != this_operand)
7989 {
7990 as_bad (_("invalid zeroing-masking `%s'"),
7991 saved);
7992 return NULL;
7993 }
7994 }
7995
7996 op_string++;
7997 }
7998 else
7999 goto unknown_vec_op;
8000
8001 if (*op_string != '}')
8002 {
8003 as_bad (_("missing `}' in `%s'"), saved);
8004 return NULL;
8005 }
8006 op_string++;
8007 continue;
8008 }
8009 unknown_vec_op:
8010 /* We don't know this one. */
8011 as_bad (_("unknown vector operation: `%s'"), saved);
8012 return NULL;
8013 }
8014
8015 return op_string;
8016}
8017
252b5132 8018static int
70e41ade 8019i386_immediate (char *imm_start)
252b5132
RH		 8020{
8021 char *save_input_line_pointer;
f3c180ae 8022 char *gotfree_input_line;
252b5132 8023 segT exp_seg = 0;
47926f60 8024 expressionS *exp;
40fb9820
L		 8025 i386_operand_type types;
8026
0dfbf9d7 8027 operand_type_set (&types, ~0);
252b5132
RH		 8028
8029 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8030 {
31b2323c
L		 8031 as_bad (_("at most %d immediate operands are allowed"),
8032 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 8033 return 0;
8034 }
8035
8036 exp = &im_expressions[i.imm_operands++];
520dc8e8 8037 i.op[this_operand].imms = exp;
252b5132
RH		 8038
8039 if (is_space_char (*imm_start))
8040 ++imm_start;
8041
8042 save_input_line_pointer = input_line_pointer;
8043 input_line_pointer = imm_start;
8044
d258b828 8045 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8046 if (gotfree_input_line)
8047 input_line_pointer = gotfree_input_line;
252b5132
RH		 8048
8049 exp_seg = expression (exp);
8050
83183c0c 8051 SKIP_WHITESPACE ();
43234a1e
L		 8052
8053 /* Handle vector operations. */
8054 if (*input_line_pointer == '{')
8055 {
8056 input_line_pointer = check_VecOperations (input_line_pointer,
8057 NULL);
8058 if (input_line_pointer == NULL)
8059 return 0;
8060 }
8061
252b5132 8062 if (*input_line_pointer)
f3c180ae 8063 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 8064
8065 input_line_pointer = save_input_line_pointer;
f3c180ae 8066 if (gotfree_input_line)
ee86248c
JB		 8067 {
8068 free (gotfree_input_line);
8069
8070 if (exp->X_op == O_constant || exp->X_op == O_register)
8071 exp->X_op = O_illegal;
8072 }
8073
8074 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8075}
252b5132 8076
ee86248c
JB		 8077static int
8078i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8079 i386_operand_type types, const char *imm_start)
8080{
8081 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 8082 {
313c53d1
L		 8083 if (imm_start)
8084 as_bad (_("missing or invalid immediate expression `%s'"),
8085 imm_start);
3992d3b7 8086 return 0;
252b5132 8087 }
3e73aa7c 8088 else if (exp->X_op == O_constant)
252b5132 8089 {
47926f60 8090 /* Size it properly later. */
40fb9820 8091 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 8092 /* If not 64bit, sign extend val. */
8093 if (flag_code != CODE_64BIT
4eed87de
AM		 8094 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8095 exp->X_add_number
8096 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 8097 }
4c63da97 8098#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 8099 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 8100 && exp_seg != absolute_section
47926f60 8101 && exp_seg != text_section
24eab124
AM		 8102 && exp_seg != data_section
8103 && exp_seg != bss_section
8104 && exp_seg != undefined_section
f86103b7 8105 && !bfd_is_com_section (exp_seg))
252b5132 8106 {
d0b47220 8107 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 8108 return 0;
8109 }
8110#endif
a841bdf5 8111 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 8112 {
313c53d1
L		 8113 if (imm_start)
8114 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 8115 return 0;
8116 }
252b5132
RH		 8117 else
8118 {
8119 /* This is an address. The size of the address will be
24eab124 8120 determined later, depending on destination register,
3e73aa7c 8121 suffix, or the default for the section. */
40fb9820
L		 8122 i.types[this_operand].bitfield.imm8 = 1;
8123 i.types[this_operand].bitfield.imm16 = 1;
8124 i.types[this_operand].bitfield.imm32 = 1;
8125 i.types[this_operand].bitfield.imm32s = 1;
8126 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8127 i.types[this_operand] = operand_type_and (i.types[this_operand],
8128 types);
252b5132
RH		 8129 }
8130
8131 return 1;
8132}
8133
551c1ca1 8134static char *
e3bb37b5 8135i386_scale (char *scale)
252b5132 8136{
551c1ca1
AM		 8137 offsetT val;
8138 char *save = input_line_pointer;
252b5132 8139
551c1ca1
AM		 8140 input_line_pointer = scale;
8141 val = get_absolute_expression ();
8142
8143 switch (val)
252b5132 8144 {
551c1ca1 8145 case 1:
252b5132
RH		 8146 i.log2_scale_factor = 0;
8147 break;
551c1ca1 8148 case 2:
252b5132
RH		 8149 i.log2_scale_factor = 1;
8150 break;
551c1ca1 8151 case 4:
252b5132
RH		 8152 i.log2_scale_factor = 2;
8153 break;
551c1ca1 8154 case 8:
252b5132
RH		 8155 i.log2_scale_factor = 3;
8156 break;
8157 default:
a724f0f4
JB		 8158 {
8159 char sep = *input_line_pointer;
8160
8161 *input_line_pointer = '\0';
8162 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8163 scale);
8164 *input_line_pointer = sep;
8165 input_line_pointer = save;
8166 return NULL;
8167 }
252b5132 8168 }
29b0f896 8169 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8170 {
8171 as_warn (_("scale factor of %d without an index register"),
24eab124 8172 1 << i.log2_scale_factor);
252b5132 8173 i.log2_scale_factor = 0;
252b5132 8174 }
551c1ca1
AM		 8175 scale = input_line_pointer;
8176 input_line_pointer = save;
8177 return scale;
252b5132
RH		 8178}
8179
252b5132 8180static int
e3bb37b5 8181i386_displacement (char *disp_start, char *disp_end)
252b5132 8182{
29b0f896 8183 expressionS *exp;
252b5132
RH		 8184 segT exp_seg = 0;
8185 char *save_input_line_pointer;
f3c180ae 8186 char *gotfree_input_line;
40fb9820
L		 8187 int override;
8188 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8189 int ret;
252b5132 8190
31b2323c
L		 8191 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8192 {
8193 as_bad (_("at most %d displacement operands are allowed"),
8194 MAX_MEMORY_OPERANDS);
8195 return 0;
8196 }
8197
0dfbf9d7 8198 operand_type_set (&bigdisp, 0);
40fb9820
L		 8199 if ((i.types[this_operand].bitfield.jumpabsolute)
8200 || (!current_templates->start->opcode_modifier.jump
8201 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8202 {
40fb9820 8203 bigdisp.bitfield.disp32 = 1;
e05278af 8204 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8205 if (flag_code == CODE_64BIT)
8206 {
8207 if (!override)
8208 {
8209 bigdisp.bitfield.disp32s = 1;
8210 bigdisp.bitfield.disp64 = 1;
8211 }
8212 }
8213 else if ((flag_code == CODE_16BIT) ^ override)
8214 {
8215 bigdisp.bitfield.disp32 = 0;
8216 bigdisp.bitfield.disp16 = 1;
8217 }
e05278af
JB		 8218 }
8219 else
8220 {
8221 /* For PC-relative branches, the width of the displacement
8222 is dependent upon data size, not address size. */
e05278af 8223 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8224 if (flag_code == CODE_64BIT)
8225 {
8226 if (override || i.suffix == WORD_MNEM_SUFFIX)
8227 bigdisp.bitfield.disp16 = 1;
8228 else
8229 {
8230 bigdisp.bitfield.disp32 = 1;
8231 bigdisp.bitfield.disp32s = 1;
8232 }
8233 }
8234 else
e05278af
JB		 8235 {
8236 if (!override)
8237 override = (i.suffix == (flag_code != CODE_16BIT
8238 ? WORD_MNEM_SUFFIX
8239 : LONG_MNEM_SUFFIX));
40fb9820
L		 8240 bigdisp.bitfield.disp32 = 1;
8241 if ((flag_code == CODE_16BIT) ^ override)
8242 {
8243 bigdisp.bitfield.disp32 = 0;
8244 bigdisp.bitfield.disp16 = 1;
8245 }
e05278af 8246 }
e05278af 8247 }
c6fb90c8
L		 8248 i.types[this_operand] = operand_type_or (i.types[this_operand],
8249 bigdisp);
252b5132
RH		 8250
8251 exp = &disp_expressions[i.disp_operands];
520dc8e8 8252 i.op[this_operand].disps = exp;
252b5132
RH		 8253 i.disp_operands++;
8254 save_input_line_pointer = input_line_pointer;
8255 input_line_pointer = disp_start;
8256 END_STRING_AND_SAVE (disp_end);
8257
8258#ifndef GCC_ASM_O_HACK
8259#define GCC_ASM_O_HACK 0
8260#endif
8261#if GCC_ASM_O_HACK
8262 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8263 if (i.types[this_operand].bitfield.baseIndex
24eab124 8264 && displacement_string_end[-1] == '+')
252b5132
RH		 8265 {
8266 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8267 constraint within gcc asm statements.
8268 For instance:
8269
8270 #define _set_tssldt_desc(n,addr,limit,type) \
8271 __asm__ __volatile__ ( \
8272 "movw %w2,%0\n\t" \
8273 "movw %w1,2+%0\n\t" \
8274 "rorl $16,%1\n\t" \
8275 "movb %b1,4+%0\n\t" \
8276 "movb %4,5+%0\n\t" \
8277 "movb $0,6+%0\n\t" \
8278 "movb %h1,7+%0\n\t" \
8279 "rorl $16,%1" \
8280 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8281
8282 This works great except that the output assembler ends
8283 up looking a bit weird if it turns out that there is
8284 no offset. You end up producing code that looks like:
8285
8286 #APP
8287 movw $235,(%eax)
8288 movw %dx,2+(%eax)
8289 rorl $16,%edx
8290 movb %dl,4+(%eax)
8291 movb $137,5+(%eax)
8292 movb $0,6+(%eax)
8293 movb %dh,7+(%eax)
8294 rorl $16,%edx
8295 #NO_APP
8296
47926f60 8297 So here we provide the missing zero. */
24eab124
AM		 8298
8299 *displacement_string_end = '0';
252b5132
RH		 8300 }
8301#endif
d258b828 8302 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8303 if (gotfree_input_line)
8304 input_line_pointer = gotfree_input_line;
252b5132 8305
24eab124 8306 exp_seg = expression (exp);
252b5132 8307
636c26b0
AM		 8308 SKIP_WHITESPACE ();
8309 if (*input_line_pointer)
8310 as_bad (_("junk `%s' after expression"), input_line_pointer);
8311#if GCC_ASM_O_HACK
8312 RESTORE_END_STRING (disp_end + 1);
8313#endif
636c26b0 8314 input_line_pointer = save_input_line_pointer;
636c26b0 8315 if (gotfree_input_line)
ee86248c
JB		 8316 {
8317 free (gotfree_input_line);
8318
8319 if (exp->X_op == O_constant || exp->X_op == O_register)
8320 exp->X_op = O_illegal;
8321 }
8322
8323 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8324
8325 RESTORE_END_STRING (disp_end);
8326
8327 return ret;
8328}
8329
8330static int
8331i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8332 i386_operand_type types, const char *disp_start)
8333{
8334 i386_operand_type bigdisp;
8335 int ret = 1;
636c26b0 8336
24eab124
AM		 8337 /* We do this to make sure that the section symbol is in
8338 the symbol table. We will ultimately change the relocation
47926f60 8339 to be relative to the beginning of the section. */
1ae12ab7 8340 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8341 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8342 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8343 {
636c26b0 8344 if (exp->X_op != O_symbol)
3992d3b7 8345 goto inv_disp;
636c26b0 8346
e5cb08ac 8347 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8348 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8349 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8350 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8351 exp->X_op = O_subtract;
8352 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8353 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8354 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8355 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8356 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8357 else
29b0f896 8358 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8359 }
252b5132 8360
3992d3b7
AM		 8361 else if (exp->X_op == O_absent
8362 || exp->X_op == O_illegal
ee86248c 8363 || exp->X_op == O_big)
2daf4fd8 8364 {
3992d3b7
AM		 8365 inv_disp:
8366 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8367 disp_start);
3992d3b7 8368 ret = 0;
2daf4fd8
AM		 8369 }
8370
0e1147d9
L		 8371 else if (flag_code == CODE_64BIT
8372 && !i.prefix[ADDR_PREFIX]
8373 && exp->X_op == O_constant)
8374 {
8375 /* Since displacement is signed extended to 64bit, don't allow
8376 disp32 and turn off disp32s if they are out of range. */
8377 i.types[this_operand].bitfield.disp32 = 0;
8378 if (!fits_in_signed_long (exp->X_add_number))
8379 {
8380 i.types[this_operand].bitfield.disp32s = 0;
8381 if (i.types[this_operand].bitfield.baseindex)
8382 {
8383 as_bad (_("0x%lx out range of signed 32bit displacement"),
8384 (long) exp->X_add_number);
8385 ret = 0;
8386 }
8387 }
8388 }
8389
4c63da97 8390#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8391 else if (exp->X_op != O_constant
8392 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8393 && exp_seg != absolute_section
8394 && exp_seg != text_section
8395 && exp_seg != data_section
8396 && exp_seg != bss_section
8397 && exp_seg != undefined_section
8398 && !bfd_is_com_section (exp_seg))
24eab124 8399 {
d0b47220 8400 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8401 ret = 0;
24eab124 8402 }
252b5132 8403#endif
3956db08 8404
40fb9820
L		 8405 /* Check if this is a displacement only operand. */
8406 bigdisp = i.types[this_operand];
8407 bigdisp.bitfield.disp8 = 0;
8408 bigdisp.bitfield.disp16 = 0;
8409 bigdisp.bitfield.disp32 = 0;
8410 bigdisp.bitfield.disp32s = 0;
8411 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8412 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8413 i.types[this_operand] = operand_type_and (i.types[this_operand],
8414 types);
3956db08 8415
3992d3b7 8416 return ret;
252b5132
RH		 8417}
8418
eecb386c 8419/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 8420 Return 1 on success, 0 on a failure. */
8421
252b5132 8422static int
e3bb37b5 8423i386_index_check (const char *operand_string)
252b5132 8424{
fc0763e6 8425 const char *kind = "base/index";
be05d201
L		 8426 enum flag_code addr_mode;
8427
8428 if (i.prefix[ADDR_PREFIX])
8429 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8430 else
8431 {
8432 addr_mode = flag_code;
8433
24eab124 8434#if INFER_ADDR_PREFIX
be05d201
L		 8435 if (i.mem_operands == 0)
8436 {
8437 /* Infer address prefix from the first memory operand. */
8438 const reg_entry *addr_reg = i.base_reg;
8439
8440 if (addr_reg == NULL)
8441 addr_reg = i.index_reg;
eecb386c 8442
be05d201
L		 8443 if (addr_reg)
8444 {
8445 if (addr_reg->reg_num == RegEip
8446 || addr_reg->reg_num == RegEiz
8447 || addr_reg->reg_type.bitfield.reg32)
8448 addr_mode = CODE_32BIT;
8449 else if (flag_code != CODE_64BIT
8450 && addr_reg->reg_type.bitfield.reg16)
8451 addr_mode = CODE_16BIT;
8452
8453 if (addr_mode != flag_code)
8454 {
8455 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8456 i.prefixes += 1;
8457 /* Change the size of any displacement too. At most one
8458 of Disp16 or Disp32 is set.
8459 FIXME. There doesn't seem to be any real need for
8460 separate Disp16 and Disp32 flags. The same goes for
8461 Imm16 and Imm32. Removing them would probably clean
8462 up the code quite a lot. */
8463 if (flag_code != CODE_64BIT
8464 && (i.types[this_operand].bitfield.disp16
8465 || i.types[this_operand].bitfield.disp32))
8466 i.types[this_operand]
8467 = operand_type_xor (i.types[this_operand], disp16_32);
8468 }
8469 }
8470 }
24eab124 8471#endif
be05d201
L		 8472 }
8473
fc0763e6
JB		 8474 if (current_templates->start->opcode_modifier.isstring
8475 && !current_templates->start->opcode_modifier.immext
8476 && (current_templates->end[-1].opcode_modifier.isstring
8477 || i.mem_operands))
8478 {
8479 /* Memory operands of string insns are special in that they only allow
8480 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8481 const reg_entry *expected_reg;
8482 static const char *di_si[][2] =
8483 {
8484 { "esi", "edi" },
8485 { "si", "di" },
8486 { "rsi", "rdi" }
8487 };
8488 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8489
8490 kind = "string address";
8491
8492 if (current_templates->start->opcode_modifier.w)
8493 {
8494 i386_operand_type type = current_templates->end[-1].operand_types[0];
8495
8496 if (!type.bitfield.baseindex
8497 || ((!i.mem_operands != !intel_syntax)
8498 && current_templates->end[-1].operand_types[1]
8499 .bitfield.baseindex))
8500 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8501 expected_reg = hash_find (reg_hash,
8502 di_si[addr_mode][type.bitfield.esseg]);
8503
fc0763e6
JB		 8504 }
8505 else
be05d201 8506 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8507
be05d201
L		 8508 if (i.base_reg != expected_reg
8509 || i.index_reg
fc0763e6 8510 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8511 {
be05d201
L		 8512 /* The second memory operand must have the same size as
8513 the first one. */
8514 if (i.mem_operands
8515 && i.base_reg
8516 && !((addr_mode == CODE_64BIT
8517 && i.base_reg->reg_type.bitfield.reg64)
8518 || (addr_mode == CODE_32BIT
8519 ? i.base_reg->reg_type.bitfield.reg32
8520 : i.base_reg->reg_type.bitfield.reg16)))
8521 goto bad_address;
8522
fc0763e6
JB		 8523 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8524 operand_string,
8525 intel_syntax ? '[' : '(',
8526 register_prefix,
be05d201 8527 expected_reg->reg_name,
fc0763e6 8528 intel_syntax ? ']' : ')');
be05d201 8529 return 1;
fc0763e6 8530 }
be05d201
L		 8531 else
8532 return 1;
8533
8534bad_address:
8535 as_bad (_("`%s' is not a valid %s expression"),
8536 operand_string, kind);
8537 return 0;
3e73aa7c
JH		 8538 }
8539 else
8540 {
be05d201
L		 8541 if (addr_mode != CODE_16BIT)
8542 {
8543 /* 32-bit/64-bit checks. */
8544 if ((i.base_reg
8545 && (addr_mode == CODE_64BIT
8546 ? !i.base_reg->reg_type.bitfield.reg64
8547 : !i.base_reg->reg_type.bitfield.reg32)
8548 && (i.index_reg
8549 || (i.base_reg->reg_num
8550 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8551 || (i.index_reg
8552 && !i.index_reg->reg_type.bitfield.regxmm
8553 && !i.index_reg->reg_type.bitfield.regymm
43234a1e 8554 && !i.index_reg->reg_type.bitfield.regzmm
be05d201
L		 8555 && ((addr_mode == CODE_64BIT
8556 ? !(i.index_reg->reg_type.bitfield.reg64
8557 || i.index_reg->reg_num == RegRiz)
8558 : !(i.index_reg->reg_type.bitfield.reg32
8559 || i.index_reg->reg_num == RegEiz))
8560 || !i.index_reg->reg_type.bitfield.baseindex)))
8561 goto bad_address;
8562 }
8563 else
3e73aa7c 8564 {
be05d201 8565 /* 16-bit checks. */
3e73aa7c 8566 if ((i.base_reg
40fb9820
L		 8567 && (!i.base_reg->reg_type.bitfield.reg16
8568 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8569 || (i.index_reg
40fb9820
L		 8570 && (!i.index_reg->reg_type.bitfield.reg16
8571 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8572 || !(i.base_reg
8573 && i.base_reg->reg_num < 6
8574 && i.index_reg->reg_num >= 6
8575 && i.log2_scale_factor == 0))))
be05d201 8576 goto bad_address;
3e73aa7c
JH		 8577 }
8578 }
be05d201 8579 return 1;
24eab124 8580}
252b5132 8581
43234a1e
L		 8582/* Handle vector immediates. */
8583
8584static int
8585RC_SAE_immediate (const char *imm_start)
8586{
8587 unsigned int match_found, j;
8588 const char *pstr = imm_start;
8589 expressionS *exp;
8590
8591 if (*pstr != '{')
8592 return 0;
8593
8594 pstr++;
8595 match_found = 0;
8596 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8597 {
8598 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8599 {
8600 if (!i.rounding)
8601 {
8602 rc_op.type = RC_NamesTable[j].type;
8603 rc_op.operand = this_operand;
8604 i.rounding = &rc_op;
8605 }
8606 else
8607 {
8608 as_bad (_("duplicated `%s'"), imm_start);
8609 return 0;
8610 }
8611 pstr += RC_NamesTable[j].len;
8612 match_found = 1;
8613 break;
8614 }
8615 }
8616 if (!match_found)
8617 return 0;
8618
8619 if (*pstr++ != '}')
8620 {
8621 as_bad (_("Missing '}': '%s'"), imm_start);
8622 return 0;
8623 }
8624 /* RC/SAE immediate string should contain nothing more. */;
8625 if (*pstr != 0)
8626 {
8627 as_bad (_("Junk after '}': '%s'"), imm_start);
8628 return 0;
8629 }
8630
8631 exp = &im_expressions[i.imm_operands++];
8632 i.op[this_operand].imms = exp;
8633
8634 exp->X_op = O_constant;
8635 exp->X_add_number = 0;
8636 exp->X_add_symbol = (symbolS *) 0;
8637 exp->X_op_symbol = (symbolS *) 0;
8638
8639 i.types[this_operand].bitfield.imm8 = 1;
8640 return 1;
8641}
8642
fc0763e6 8643/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8644 on error. */
252b5132 8645
252b5132 8646static int
a7619375 8647i386_att_operand (char *operand_string)
252b5132 8648{
af6bdddf
AM		 8649 const reg_entry *r;
8650 char *end_op;
24eab124 8651 char *op_string = operand_string;
252b5132 8652
24eab124 8653 if (is_space_char (*op_string))
252b5132
RH		 8654 ++op_string;
8655
24eab124 8656 /* We check for an absolute prefix (differentiating,
47926f60 8657 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8658 if (*op_string == ABSOLUTE_PREFIX)
8659 {
8660 ++op_string;
8661 if (is_space_char (*op_string))
8662 ++op_string;
40fb9820 8663 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8664 }
252b5132 8665
47926f60 8666 /* Check if operand is a register. */
4d1bb795 8667 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8668 {
40fb9820
L		 8669 i386_operand_type temp;
8670
24eab124
AM		 8671 /* Check for a segment override by searching for ':' after a
8672 segment register. */
8673 op_string = end_op;
8674 if (is_space_char (*op_string))
8675 ++op_string;
40fb9820
L		 8676 if (*op_string == ':'
8677 && (r->reg_type.bitfield.sreg2
8678 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8679 {
8680 switch (r->reg_num)
8681 {
8682 case 0:
8683 i.seg[i.mem_operands] = &es;
8684 break;
8685 case 1:
8686 i.seg[i.mem_operands] = &cs;
8687 break;
8688 case 2:
8689 i.seg[i.mem_operands] = &ss;
8690 break;
8691 case 3:
8692 i.seg[i.mem_operands] = &ds;
8693 break;
8694 case 4:
8695 i.seg[i.mem_operands] = &fs;
8696 break;
8697 case 5:
8698 i.seg[i.mem_operands] = &gs;
8699 break;
8700 }
252b5132 8701
24eab124 8702 /* Skip the ':' and whitespace. */
252b5132
RH		 8703 ++op_string;
8704 if (is_space_char (*op_string))
24eab124 8705 ++op_string;
252b5132 8706
24eab124
AM		 8707 if (!is_digit_char (*op_string)
8708 && !is_identifier_char (*op_string)
8709 && *op_string != '('
8710 && *op_string != ABSOLUTE_PREFIX)
8711 {
8712 as_bad (_("bad memory operand `%s'"), op_string);
8713 return 0;
8714 }
47926f60 8715 /* Handle case of %es:*foo. */
24eab124
AM		 8716 if (*op_string == ABSOLUTE_PREFIX)
8717 {
8718 ++op_string;
8719 if (is_space_char (*op_string))
8720 ++op_string;
40fb9820 8721 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8722 }
8723 goto do_memory_reference;
8724 }
43234a1e
L		 8725
8726 /* Handle vector operations. */
8727 if (*op_string == '{')
8728 {
8729 op_string = check_VecOperations (op_string, NULL);
8730 if (op_string == NULL)
8731 return 0;
8732 }
8733
24eab124
AM		 8734 if (*op_string)
8735 {
d0b47220 8736 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 8737 return 0;
8738 }
40fb9820
L		 8739 temp = r->reg_type;
8740 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8741 i.types[this_operand] = operand_type_or (i.types[this_operand],
8742 temp);
7d5e4556 8743 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 8744 i.op[this_operand].regs = r;
24eab124
AM		 8745 i.reg_operands++;
8746 }
af6bdddf
AM		 8747 else if (*op_string == REGISTER_PREFIX)
8748 {
8749 as_bad (_("bad register name `%s'"), op_string);
8750 return 0;
8751 }
24eab124 8752 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 8753 {
24eab124 8754 ++op_string;
40fb9820 8755 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 8756 {
d0b47220 8757 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 8758 return 0;
8759 }
8760 if (!i386_immediate (op_string))
8761 return 0;
8762 }
43234a1e
L		 8763 else if (RC_SAE_immediate (operand_string))
8764 {
8765 /* If it is a RC or SAE immediate, do nothing. */
8766 ;
8767 }
24eab124
AM		 8768 else if (is_digit_char (*op_string)
8769 || is_identifier_char (*op_string)
d02603dc 8770 || *op_string == '"'
e5cb08ac 8771 || *op_string == '(')
24eab124 8772 {
47926f60 8773 /* This is a memory reference of some sort. */
af6bdddf 8774 char *base_string;
252b5132 8775
47926f60 8776 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 8777 char *displacement_string_start;
8778 char *displacement_string_end;
43234a1e 8779 char *vop_start;
252b5132 8780
24eab124 8781 do_memory_reference:
24eab124 8782 if ((i.mem_operands == 1
40fb9820 8783 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 8784 || i.mem_operands == 2)
8785 {
8786 as_bad (_("too many memory references for `%s'"),
8787 current_templates->start->name);
8788 return 0;
8789 }
252b5132 8790
24eab124
AM		 8791 /* Check for base index form. We detect the base index form by
8792 looking for an ')' at the end of the operand, searching
8793 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8794 after the '('. */
af6bdddf 8795 base_string = op_string + strlen (op_string);
c3332e24 8796
43234a1e
L		 8797 /* Handle vector operations. */
8798 vop_start = strchr (op_string, '{');
8799 if (vop_start && vop_start < base_string)
8800 {
8801 if (check_VecOperations (vop_start, base_string) == NULL)
8802 return 0;
8803 base_string = vop_start;
8804 }
8805
af6bdddf
AM		 8806 --base_string;
8807 if (is_space_char (*base_string))
8808 --base_string;
252b5132 8809
47926f60 8810 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 8811 displacement_string_start = op_string;
8812 displacement_string_end = base_string + 1;
252b5132 8813
24eab124
AM		 8814 if (*base_string == ')')
8815 {
af6bdddf 8816 char *temp_string;
24eab124
AM		 8817 unsigned int parens_balanced = 1;
8818 /* We've already checked that the number of left & right ()'s are
47926f60 8819 equal, so this loop will not be infinite. */
24eab124
AM		 8820 do
8821 {
8822 base_string--;
8823 if (*base_string == ')')
8824 parens_balanced++;
8825 if (*base_string == '(')
8826 parens_balanced--;
8827 }
8828 while (parens_balanced);
c3332e24 8829
af6bdddf 8830 temp_string = base_string;
c3332e24 8831
24eab124 8832 /* Skip past '(' and whitespace. */
252b5132
RH		 8833 ++base_string;
8834 if (is_space_char (*base_string))
24eab124 8835 ++base_string;
252b5132 8836
af6bdddf 8837 if (*base_string == ','
4eed87de
AM		 8838 || ((i.base_reg = parse_register (base_string, &end_op))
8839 != NULL))
252b5132 8840 {
af6bdddf 8841 displacement_string_end = temp_string;
252b5132 8842
40fb9820 8843 i.types[this_operand].bitfield.baseindex = 1;
252b5132 8844
af6bdddf 8845 if (i.base_reg)
24eab124 8846 {
24eab124
AM		 8847 base_string = end_op;
8848 if (is_space_char (*base_string))
8849 ++base_string;
af6bdddf
AM		 8850 }
8851
8852 /* There may be an index reg or scale factor here. */
8853 if (*base_string == ',')
8854 {
8855 ++base_string;
8856 if (is_space_char (*base_string))
8857 ++base_string;
8858
4eed87de
AM		 8859 if ((i.index_reg = parse_register (base_string, &end_op))
8860 != NULL)
24eab124 8861 {
af6bdddf 8862 base_string = end_op;
24eab124
AM		 8863 if (is_space_char (*base_string))
8864 ++base_string;
af6bdddf
AM		 8865 if (*base_string == ',')
8866 {
8867 ++base_string;
8868 if (is_space_char (*base_string))
8869 ++base_string;
8870 }
e5cb08ac 8871 else if (*base_string != ')')
af6bdddf 8872 {
4eed87de
AM		 8873 as_bad (_("expecting `,' or `)' "
8874 "after index register in `%s'"),
af6bdddf
AM		 8875 operand_string);
8876 return 0;
8877 }
24eab124 8878 }
af6bdddf 8879 else if (*base_string == REGISTER_PREFIX)
24eab124 8880 {
f76bf5e0
L		 8881 end_op = strchr (base_string, ',');
8882 if (end_op)
8883 *end_op = '\0';
af6bdddf 8884 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 8885 return 0;
8886 }
252b5132 8887
47926f60 8888 /* Check for scale factor. */
551c1ca1 8889 if (*base_string != ')')
af6bdddf 8890 {
551c1ca1
AM		 8891 char *end_scale = i386_scale (base_string);
8892
8893 if (!end_scale)
af6bdddf 8894 return 0;
24eab124 8895
551c1ca1 8896 base_string = end_scale;
af6bdddf
AM		 8897 if (is_space_char (*base_string))
8898 ++base_string;
8899 if (*base_string != ')')
8900 {
4eed87de
AM		 8901 as_bad (_("expecting `)' "
8902 "after scale factor in `%s'"),
af6bdddf
AM		 8903 operand_string);
8904 return 0;
8905 }
8906 }
8907 else if (!i.index_reg)
24eab124 8908 {
4eed87de
AM		 8909 as_bad (_("expecting index register or scale factor "
8910 "after `,'; got '%c'"),
af6bdddf 8911 *base_string);
24eab124
AM		 8912 return 0;
8913 }
8914 }
af6bdddf 8915 else if (*base_string != ')')
24eab124 8916 {
4eed87de
AM		 8917 as_bad (_("expecting `,' or `)' "
8918 "after base register in `%s'"),
af6bdddf 8919 operand_string);
24eab124
AM		 8920 return 0;
8921 }
c3332e24 8922 }
af6bdddf 8923 else if (*base_string == REGISTER_PREFIX)
c3332e24 8924 {
f76bf5e0
L		 8925 end_op = strchr (base_string, ',');
8926 if (end_op)
8927 *end_op = '\0';
af6bdddf 8928 as_bad (_("bad register name `%s'"), base_string);
24eab124 8929 return 0;
c3332e24 8930 }
24eab124
AM		 8931 }
8932
8933 /* If there's an expression beginning the operand, parse it,
8934 assuming displacement_string_start and
8935 displacement_string_end are meaningful. */
8936 if (displacement_string_start != displacement_string_end)
8937 {
8938 if (!i386_displacement (displacement_string_start,
8939 displacement_string_end))
8940 return 0;
8941 }
8942
8943 /* Special case for (%dx) while doing input/output op. */
8944 if (i.base_reg
0dfbf9d7
L		 8945 && operand_type_equal (&i.base_reg->reg_type,
8946 &reg16_inoutportreg)
24eab124
AM		 8947 && i.index_reg == 0
8948 && i.log2_scale_factor == 0
8949 && i.seg[i.mem_operands] == 0
40fb9820 8950 && !operand_type_check (i.types[this_operand], disp))
24eab124 8951 {
65da13b5 8952 i.types[this_operand] = inoutportreg;
24eab124
AM		 8953 return 1;
8954 }
8955
eecb386c
AM		 8956 if (i386_index_check (operand_string) == 0)
8957 return 0;
5c07affc 8958 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 8959 i.mem_operands++;
8960 }
8961 else
ce8a8b2f
AM		 8962 {
8963 /* It's not a memory operand; argh! */
24eab124
AM		 8964 as_bad (_("invalid char %s beginning operand %d `%s'"),
8965 output_invalid (*op_string),
8966 this_operand + 1,
8967 op_string);
8968 return 0;
8969 }
47926f60 8970 return 1; /* Normal return. */
252b5132
RH		 8971}
8972\f
fa94de6b
RM		 8973/* Calculate the maximum variable size (i.e., excluding fr_fix)
8974 that an rs_machine_dependent frag may reach. */
8975
8976unsigned int
8977i386_frag_max_var (fragS *frag)
8978{
8979 /* The only relaxable frags are for jumps.
8980 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8981 gas_assert (frag->fr_type == rs_machine_dependent);
8982 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
8983}
8984
b084df0b
L		 8985#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8986static int
8dcea932 8987elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
b084df0b
L		 8988{
8989 /* STT_GNU_IFUNC symbol must go through PLT. */
8990 if ((symbol_get_bfdsym (fr_symbol)->flags
8991 & BSF_GNU_INDIRECT_FUNCTION) != 0)
8992 return 0;
8993
8994 if (!S_IS_EXTERNAL (fr_symbol))
8995 /* Symbol may be weak or local. */
8996 return !S_IS_WEAK (fr_symbol);
8997
8dcea932
L		 8998 /* Global symbols with non-default visibility can't be preempted. */
8999 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9000 return 1;
9001
9002 if (fr_var != NO_RELOC)
9003 switch ((enum bfd_reloc_code_real) fr_var)
9004 {
9005 case BFD_RELOC_386_PLT32:
9006 case BFD_RELOC_X86_64_PLT32:
9007 /* Symbol with PLT relocatin may be preempted. */
9008 return 0;
9009 default:
9010 abort ();
9011 }
9012
b084df0b
L		 9013 /* Global symbols with default visibility in a shared library may be
9014 preempted by another definition. */
8dcea932 9015 return !shared;
b084df0b
L		 9016}
9017#endif
9018
ee7fcc42
AM		 9019/* md_estimate_size_before_relax()
9020
9021 Called just before relax() for rs_machine_dependent frags. The x86
9022 assembler uses these frags to handle variable size jump
9023 instructions.
9024
9025 Any symbol that is now undefined will not become defined.
9026 Return the correct fr_subtype in the frag.
9027 Return the initial "guess for variable size of frag" to caller.
9028 The guess is actually the growth beyond the fixed part. Whatever
9029 we do to grow the fixed or variable part contributes to our
9030 returned value. */
9031
252b5132 9032int
7016a5d5 9033md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 9034{
252b5132 9035 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 9036 check for un-relaxable symbols. On an ELF system, we can't relax
9037 an externally visible symbol, because it may be overridden by a
9038 shared library. */
9039 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 9040#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9041 || (IS_ELF
8dcea932
L		 9042 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9043 fragP->fr_var))
fbeb56a4
DK		 9044#endif
9045#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 9046 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 9047 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 9048#endif
9049 )
252b5132 9050 {
b98ef147
AM		 9051 /* Symbol is undefined in this segment, or we need to keep a
9052 reloc so that weak symbols can be overridden. */
9053 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 9054 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 9055 unsigned char *opcode;
9056 int old_fr_fix;
f6af82bd 9057
ee7fcc42 9058 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 9059 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 9060 else if (size == 2)
f6af82bd
AM		 9061 reloc_type = BFD_RELOC_16_PCREL;
9062 else
9063 reloc_type = BFD_RELOC_32_PCREL;
252b5132 9064
ee7fcc42
AM		 9065 old_fr_fix = fragP->fr_fix;
9066 opcode = (unsigned char *) fragP->fr_opcode;
9067
fddf5b5b 9068 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 9069 {
fddf5b5b
AM		 9070 case UNCOND_JUMP:
9071 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 9072 opcode[0] = 0xe9;
252b5132 9073 fragP->fr_fix += size;
062cd5e7
AS		 9074 fix_new (fragP, old_fr_fix, size,
9075 fragP->fr_symbol,
9076 fragP->fr_offset, 1,
9077 reloc_type);
252b5132
RH		 9078 break;
9079
fddf5b5b 9080 case COND_JUMP86:
412167cb
AM		 9081 if (size == 2
9082 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 9083 {
9084 /* Negate the condition, and branch past an
9085 unconditional jump. */
9086 opcode[0] ^= 1;
9087 opcode[1] = 3;
9088 /* Insert an unconditional jump. */
9089 opcode[2] = 0xe9;
9090 /* We added two extra opcode bytes, and have a two byte
9091 offset. */
9092 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 9093 fix_new (fragP, old_fr_fix + 2, 2,
9094 fragP->fr_symbol,
9095 fragP->fr_offset, 1,
9096 reloc_type);
fddf5b5b
AM		 9097 break;
9098 }
9099 /* Fall through. */
9100
9101 case COND_JUMP:
412167cb
AM		 9102 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9103 {
3e02c1cc
AM		 9104 fixS *fixP;
9105
412167cb 9106 fragP->fr_fix += 1;
3e02c1cc
AM		 9107 fixP = fix_new (fragP, old_fr_fix, 1,
9108 fragP->fr_symbol,
9109 fragP->fr_offset, 1,
9110 BFD_RELOC_8_PCREL);
9111 fixP->fx_signed = 1;
412167cb
AM		 9112 break;
9113 }
93c2a809 9114
24eab124 9115 /* This changes the byte-displacement jump 0x7N
fddf5b5b 9116 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 9117 opcode[1] = opcode[0] + 0x10;
f6af82bd 9118 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 9119 /* We've added an opcode byte. */
9120 fragP->fr_fix += 1 + size;
062cd5e7
AS		 9121 fix_new (fragP, old_fr_fix + 1, size,
9122 fragP->fr_symbol,
9123 fragP->fr_offset, 1,
9124 reloc_type);
252b5132 9125 break;
fddf5b5b
AM		 9126
9127 default:
9128 BAD_CASE (fragP->fr_subtype);
9129 break;
252b5132
RH		 9130 }
9131 frag_wane (fragP);
ee7fcc42 9132 return fragP->fr_fix - old_fr_fix;
252b5132 9133 }
93c2a809 9134
93c2a809
AM		 9135 /* Guess size depending on current relax state. Initially the relax
9136 state will correspond to a short jump and we return 1, because
9137 the variable part of the frag (the branch offset) is one byte
9138 long. However, we can relax a section more than once and in that
9139 case we must either set fr_subtype back to the unrelaxed state,
9140 or return the value for the appropriate branch. */
9141 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 9142}
9143
47926f60
KH		 9144/* Called after relax() is finished.
9145
9146 In: Address of frag.
9147 fr_type == rs_machine_dependent.
9148 fr_subtype is what the address relaxed to.
9149
9150 Out: Any fixSs and constants are set up.
9151 Caller will turn frag into a ".space 0". */
9152
252b5132 9153void
7016a5d5
TG		 9154md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9155 fragS *fragP)
252b5132 9156{
29b0f896 9157 unsigned char *opcode;
252b5132 9158 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9159 offsetT target_address;
9160 offsetT opcode_address;
252b5132 9161 unsigned int extension = 0;
847f7ad4 9162 offsetT displacement_from_opcode_start;
252b5132
RH		 9163
9164 opcode = (unsigned char *) fragP->fr_opcode;
9165
47926f60 9166 /* Address we want to reach in file space. */
252b5132 9167 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9168
47926f60 9169 /* Address opcode resides at in file space. */
252b5132
RH		 9170 opcode_address = fragP->fr_address + fragP->fr_fix;
9171
47926f60 9172 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9173 displacement_from_opcode_start = target_address - opcode_address;
9174
fddf5b5b 9175 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9176 {
47926f60
KH		 9177 /* Don't have to change opcode. */
9178 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9179 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9180 }
9181 else
9182 {
9183 if (no_cond_jump_promotion
9184 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9185 as_warn_where (fragP->fr_file, fragP->fr_line,
9186 _("long jump required"));
252b5132 9187
fddf5b5b
AM		 9188 switch (fragP->fr_subtype)
9189 {
9190 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9191 extension = 4; /* 1 opcode + 4 displacement */
9192 opcode[0] = 0xe9;
9193 where_to_put_displacement = &opcode[1];
9194 break;
252b5132 9195
fddf5b5b
AM		 9196 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9197 extension = 2; /* 1 opcode + 2 displacement */
9198 opcode[0] = 0xe9;
9199 where_to_put_displacement = &opcode[1];
9200 break;
252b5132 9201
fddf5b5b
AM		 9202 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9203 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9204 extension = 5; /* 2 opcode + 4 displacement */
9205 opcode[1] = opcode[0] + 0x10;
9206 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9207 where_to_put_displacement = &opcode[2];
9208 break;
252b5132 9209
fddf5b5b
AM		 9210 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9211 extension = 3; /* 2 opcode + 2 displacement */
9212 opcode[1] = opcode[0] + 0x10;
9213 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9214 where_to_put_displacement = &opcode[2];
9215 break;
252b5132 9216
fddf5b5b
AM		 9217 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9218 extension = 4;
9219 opcode[0] ^= 1;
9220 opcode[1] = 3;
9221 opcode[2] = 0xe9;
9222 where_to_put_displacement = &opcode[3];
9223 break;
9224
9225 default:
9226 BAD_CASE (fragP->fr_subtype);
9227 break;
9228 }
252b5132 9229 }
fddf5b5b 9230
7b81dfbb
AJ		 9231 /* If size if less then four we are sure that the operand fits,
9232 but if it's 4, then it could be that the displacement is larger
9233 then -/+ 2GB. */
9234 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9235 && object_64bit
9236 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9237 + ((addressT) 1 << 31))
9238 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9239 {
9240 as_bad_where (fragP->fr_file, fragP->fr_line,
9241 _("jump target out of range"));
9242 /* Make us emit 0. */
9243 displacement_from_opcode_start = extension;
9244 }
47926f60 9245 /* Now put displacement after opcode. */
252b5132
RH		 9246 md_number_to_chars ((char *) where_to_put_displacement,
9247 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9248 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9249 fragP->fr_fix += extension;
9250}
9251\f
7016a5d5 9252/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9253 by our caller that we have all the info we need to fix it up.
9254
7016a5d5
TG		 9255 Parameter valP is the pointer to the value of the bits.
9256
252b5132
RH		 9257 On the 386, immediates, displacements, and data pointers are all in
9258 the same (little-endian) format, so we don't need to care about which
9259 we are handling. */
9260
94f592af 9261void
7016a5d5 9262md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9263{
94f592af 9264 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9265 valueT value = *valP;
252b5132 9266
f86103b7 9267#if !defined (TE_Mach)
93382f6d
AM		 9268 if (fixP->fx_pcrel)
9269 {
9270 switch (fixP->fx_r_type)
9271 {
5865bb77
ILT		 9272 default:
9273 break;
9274
d6ab8113
JB		 9275 case BFD_RELOC_64:
9276 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9277 break;
93382f6d 9278 case BFD_RELOC_32:
ae8887b5 9279 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9280 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9281 break;
9282 case BFD_RELOC_16:
9283 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9284 break;
9285 case BFD_RELOC_8:
9286 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9287 break;
9288 }
9289 }
252b5132 9290
a161fe53 9291 if (fixP->fx_addsy != NULL
31312f95 9292 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9293 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9294 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 9295 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 9296 && !use_rela_relocations)
252b5132 9297 {
31312f95
AM		 9298 /* This is a hack. There should be a better way to handle this.
9299 This covers for the fact that bfd_install_relocation will
9300 subtract the current location (for partial_inplace, PC relative
9301 relocations); see more below. */
252b5132 9302#ifndef OBJ_AOUT
718ddfc0 9303 if (IS_ELF
252b5132
RH		 9304#ifdef TE_PE
9305 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9306#endif
9307 )
9308 value += fixP->fx_where + fixP->fx_frag->fr_address;
9309#endif
9310#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9311 if (IS_ELF)
252b5132 9312 {
6539b54b 9313 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9314
6539b54b 9315 if ((sym_seg == seg
2f66722d 9316 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9317 && sym_seg != absolute_section))
af65af87 9318 && !generic_force_reloc (fixP))
2f66722d
AM		 9319 {
9320 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9321 bfd_install_relocation subtracts them out again. I think
9322 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9323 it. FIXME. */
9324 value += fixP->fx_where + fixP->fx_frag->fr_address;
9325 }
252b5132
RH		 9326 }
9327#endif
9328#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9329 /* For some reason, the PE format does not store a
9330 section address offset for a PC relative symbol. */
9331 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9332 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9333 value += md_pcrel_from (fixP);
9334#endif
9335 }
fbeb56a4 9336#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9337 if (fixP->fx_addsy != NULL
9338 && S_IS_WEAK (fixP->fx_addsy)
9339 /* PR 16858: Do not modify weak function references. */
9340 && ! fixP->fx_pcrel)
fbeb56a4 9341 {
296a8689
NC		 9342#if !defined (TE_PEP)
9343 /* For x86 PE weak function symbols are neither PC-relative
9344 nor do they set S_IS_FUNCTION. So the only reliable way
9345 to detect them is to check the flags of their containing
9346 section. */
9347 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9348 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9349 ;
9350 else
9351#endif
fbeb56a4
DK		 9352 value -= S_GET_VALUE (fixP->fx_addsy);
9353 }
9354#endif
252b5132
RH		 9355
9356 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9357 and we must not disappoint it. */
252b5132 9358#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9359 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9360 switch (fixP->fx_r_type)
9361 {
9362 case BFD_RELOC_386_PLT32:
3e73aa7c 9363 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 9364 /* Make the jump instruction point to the address of the operand. At
9365 runtime we merely add the offset to the actual PLT entry. */
9366 value = -4;
9367 break;
31312f95 9368
13ae64f3
JJ		 9369 case BFD_RELOC_386_TLS_GD:
9370 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9371 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9372 case BFD_RELOC_386_TLS_IE:
9373 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9374 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9375 case BFD_RELOC_X86_64_TLSGD:
9376 case BFD_RELOC_X86_64_TLSLD:
9377 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9378 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9379 value = 0; /* Fully resolved at runtime. No addend. */
9380 /* Fallthrough */
9381 case BFD_RELOC_386_TLS_LE:
9382 case BFD_RELOC_386_TLS_LDO_32:
9383 case BFD_RELOC_386_TLS_LE_32:
9384 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9385 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9386 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9387 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9388 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9389 break;
9390
67a4f2b7
AO		 9391 case BFD_RELOC_386_TLS_DESC_CALL:
9392 case BFD_RELOC_X86_64_TLSDESC_CALL:
9393 value = 0; /* Fully resolved at runtime. No addend. */
9394 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9395 fixP->fx_done = 0;
9396 return;
9397
47926f60
KH		 9398 case BFD_RELOC_VTABLE_INHERIT:
9399 case BFD_RELOC_VTABLE_ENTRY:
9400 fixP->fx_done = 0;
94f592af 9401 return;
47926f60
KH		 9402
9403 default:
9404 break;
9405 }
9406#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9407 *valP = value;
f86103b7 9408#endif /* !defined (TE_Mach) */
3e73aa7c 9409
3e73aa7c 9410 /* Are we finished with this relocation now? */
c6682705 9411 if (fixP->fx_addsy == NULL)
3e73aa7c 9412 fixP->fx_done = 1;
fbeb56a4
DK		 9413#if defined (OBJ_COFF) && defined (TE_PE)
9414 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9415 {
9416 fixP->fx_done = 0;
9417 /* Remember value for tc_gen_reloc. */
9418 fixP->fx_addnumber = value;
9419 /* Clear out the frag for now. */
9420 value = 0;
9421 }
9422#endif
3e73aa7c
JH		 9423 else if (use_rela_relocations)
9424 {
9425 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9426 /* Remember value for tc_gen_reloc. */
9427 fixP->fx_addnumber = value;
3e73aa7c
JH		 9428 value = 0;
9429 }
f86103b7 9430
94f592af 9431 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9432}
252b5132 9433\f
6d4af3c2 9434const char *
499ac353 9435md_atof (int type, char *litP, int *sizeP)
252b5132 9436{
499ac353
NC		 9437 /* This outputs the LITTLENUMs in REVERSE order;
9438 in accord with the bigendian 386. */
9439 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9440}
9441\f
2d545b82 9442static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9443
252b5132 9444static char *
e3bb37b5 9445output_invalid (int c)
252b5132 9446{
3882b010 9447 if (ISPRINT (c))
f9f21a03
L		 9448 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9449 "'%c'", c);
252b5132 9450 else
f9f21a03 9451 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9452 "(0x%x)", (unsigned char) c);
252b5132
RH		 9453 return output_invalid_buf;
9454}
9455
af6bdddf 9456/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9457
9458static const reg_entry *
4d1bb795 9459parse_real_register (char *reg_string, char **end_op)
252b5132 9460{
af6bdddf
AM		 9461 char *s = reg_string;
9462 char *p;
252b5132
RH		 9463 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9464 const reg_entry *r;
9465
9466 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9467 if (*s == REGISTER_PREFIX)
9468 ++s;
9469
9470 if (is_space_char (*s))
9471 ++s;
9472
9473 p = reg_name_given;
af6bdddf 9474 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9475 {
9476 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9477 return (const reg_entry *) NULL;
9478 s++;
252b5132
RH		 9479 }
9480
6588847e
DN		 9481 /* For naked regs, make sure that we are not dealing with an identifier.
9482 This prevents confusing an identifier like `eax_var' with register
9483 `eax'. */
9484 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9485 return (const reg_entry *) NULL;
9486
af6bdddf 9487 *end_op = s;
252b5132
RH		 9488
9489 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9490
5f47d35b 9491 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9492 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9493 {
5f47d35b
AM		 9494 if (is_space_char (*s))
9495 ++s;
9496 if (*s == '(')
9497 {
af6bdddf 9498 ++s;
5f47d35b
AM		 9499 if (is_space_char (*s))
9500 ++s;
9501 if (*s >= '0' && *s <= '7')
9502 {
db557034 9503 int fpr = *s - '0';
af6bdddf 9504 ++s;
5f47d35b
AM		 9505 if (is_space_char (*s))
9506 ++s;
9507 if (*s == ')')
9508 {
9509 *end_op = s + 1;
1e9cc1c2 9510 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9511 know (r);
9512 return r + fpr;
5f47d35b 9513 }
5f47d35b 9514 }
47926f60 9515 /* We have "%st(" then garbage. */
5f47d35b
AM		 9516 return (const reg_entry *) NULL;
9517 }
9518 }
9519
a60de03c
JB		 9520 if (r == NULL || allow_pseudo_reg)
9521 return r;
9522
0dfbf9d7 9523 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9524 return (const reg_entry *) NULL;
9525
192dc9c6
JB		 9526 if ((r->reg_type.bitfield.reg32
9527 || r->reg_type.bitfield.sreg3
9528 || r->reg_type.bitfield.control
9529 || r->reg_type.bitfield.debug
9530 || r->reg_type.bitfield.test)
9531 && !cpu_arch_flags.bitfield.cpui386)
9532 return (const reg_entry *) NULL;
9533
309d3373
JB		 9534 if (r->reg_type.bitfield.floatreg
9535 && !cpu_arch_flags.bitfield.cpu8087
9536 && !cpu_arch_flags.bitfield.cpu287
9537 && !cpu_arch_flags.bitfield.cpu387)
9538 return (const reg_entry *) NULL;
9539
192dc9c6
JB		 9540 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
9541 return (const reg_entry *) NULL;
9542
9543 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
9544 return (const reg_entry *) NULL;
9545
40f12533
L		 9546 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
9547 return (const reg_entry *) NULL;
9548
43234a1e
L		 9549 if ((r->reg_type.bitfield.regzmm || r->reg_type.bitfield.regmask)
9550 && !cpu_arch_flags.bitfield.cpuavx512f)
9551 return (const reg_entry *) NULL;
9552
db51cc60 9553 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9554 if (!allow_index_reg
db51cc60
L		 9555 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9556 return (const reg_entry *) NULL;
9557
43234a1e
L		 9558 /* Upper 16 vector register is only available with VREX in 64bit
9559 mode. */
9560 if ((r->reg_flags & RegVRex))
9561 {
9562 if (!cpu_arch_flags.bitfield.cpuvrex
9563 || flag_code != CODE_64BIT)
9564 return (const reg_entry *) NULL;
9565
9566 i.need_vrex = 1;
9567 }
9568
a60de03c
JB		 9569 if (((r->reg_flags & (RegRex64 | RegRex))
9570 || r->reg_type.bitfield.reg64)
40fb9820 9571 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9572 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9573 && flag_code != CODE_64BIT)
20f0a1fc 9574 return (const reg_entry *) NULL;
1ae00879 9575
b7240065
JB		 9576 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9577 return (const reg_entry *) NULL;
9578
252b5132
RH		 9579 return r;
9580}
4d1bb795
JB		 9581
9582/* REG_STRING starts *before* REGISTER_PREFIX. */
9583
9584static const reg_entry *
9585parse_register (char *reg_string, char **end_op)
9586{
9587 const reg_entry *r;
9588
9589 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9590 r = parse_real_register (reg_string, end_op);
9591 else
9592 r = NULL;
9593 if (!r)
9594 {
9595 char *save = input_line_pointer;
9596 char c;
9597 symbolS *symbolP;
9598
9599 input_line_pointer = reg_string;
d02603dc 9600 c = get_symbol_name (&reg_string);
4d1bb795
JB		 9601 symbolP = symbol_find (reg_string);
9602 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9603 {
9604 const expressionS *e = symbol_get_value_expression (symbolP);
9605
0398aac5 9606 know (e->X_op == O_register);
4eed87de 9607 know (e->X_add_number >= 0
c3fe08fa 9608 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 9609 r = i386_regtab + e->X_add_number;
d3bb6b49
IT		 9610 if ((r->reg_flags & RegVRex))
9611 i.need_vrex = 1;
4d1bb795
JB		 9612 *end_op = input_line_pointer;
9613 }
9614 *input_line_pointer = c;
9615 input_line_pointer = save;
9616 }
9617 return r;
9618}
9619
9620int
9621i386_parse_name (char *name, expressionS *e, char *nextcharP)
9622{
9623 const reg_entry *r;
9624 char *end = input_line_pointer;
9625
9626 *end = *nextcharP;
9627 r = parse_register (name, &input_line_pointer);
9628 if (r && end <= input_line_pointer)
9629 {
9630 *nextcharP = *input_line_pointer;
9631 *input_line_pointer = 0;
9632 e->X_op = O_register;
9633 e->X_add_number = r - i386_regtab;
9634 return 1;
9635 }
9636 input_line_pointer = end;
9637 *end = 0;
ee86248c 9638 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9639}
9640
9641void
9642md_operand (expressionS *e)
9643{
ee86248c
JB		 9644 char *end;
9645 const reg_entry *r;
4d1bb795 9646
ee86248c
JB		 9647 switch (*input_line_pointer)
9648 {
9649 case REGISTER_PREFIX:
9650 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9651 if (r)
9652 {
9653 e->X_op = O_register;
9654 e->X_add_number = r - i386_regtab;
9655 input_line_pointer = end;
9656 }
ee86248c
JB		 9657 break;
9658
9659 case '[':
9c2799c2 9660 gas_assert (intel_syntax);
ee86248c
JB		 9661 end = input_line_pointer++;
9662 expression (e);
9663 if (*input_line_pointer == ']')
9664 {
9665 ++input_line_pointer;
9666 e->X_op_symbol = make_expr_symbol (e);
9667 e->X_add_symbol = NULL;
9668 e->X_add_number = 0;
9669 e->X_op = O_index;
9670 }
9671 else
9672 {
9673 e->X_op = O_absent;
9674 input_line_pointer = end;
9675 }
9676 break;
4d1bb795
JB		 9677 }
9678}
9679
252b5132 9680\f
4cc782b5 9681#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9682const char *md_shortopts = "kVQ:sqn";
252b5132 9683#else
12b55ccc 9684const char *md_shortopts = "qn";
252b5132 9685#endif
6e0b89ee 9686
3e73aa7c 9687#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9688#define OPTION_64 (OPTION_MD_BASE + 1)
9689#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9690#define OPTION_MARCH (OPTION_MD_BASE + 3)
9691#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9692#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9693#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9694#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9695#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9696#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9697#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9698#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9699#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9700#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9701#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9702#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9703#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9704#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 9705#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
d1982f93 9706#define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 9707#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
8dcea932 9708#define OPTION_MSHARED (OPTION_MD_BASE + 21)
5db04b09
L		 9709#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9710#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
e4e00185 9711#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
0cb4071e 9712#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
b3b91714 9713
99ad8390
NC		 9714struct option md_longopts[] =
9715{
3e73aa7c 9716 {"32", no_argument, NULL, OPTION_32},
321098a5 9717#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9718 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9719 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 9720#endif
9721#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9722 {"x32", no_argument, NULL, OPTION_X32},
8dcea932 9723 {"mshared", no_argument, NULL, OPTION_MSHARED},
6e0b89ee 9724#endif
b3b91714 9725 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 9726 {"march", required_argument, NULL, OPTION_MARCH},
9727 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 9728 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9729 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9730 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9731 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9732 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 9733 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 9734 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 9735 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 9736 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 9737 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 9738 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9739 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 9740# if defined (TE_PE) || defined (TE_PEP)
9741 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
9742#endif
d1982f93 9743 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
e4e00185 9744 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
0cb4071e 9745 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
d3d3c6db 9746 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
5db04b09
L		 9747 {"mamd64", no_argument, NULL, OPTION_MAMD64},
9748 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
252b5132
RH		 9749 {NULL, no_argument, NULL, 0}
9750};
9751size_t md_longopts_size = sizeof (md_longopts);
9752
9753int
17b9d67d 9754md_parse_option (int c, const char *arg)
252b5132 9755{
91d6fa6a 9756 unsigned int j;
293f5f65 9757 char *arch, *next, *saved;
9103f4f4 9758
252b5132
RH		 9759 switch (c)
9760 {
12b55ccc
L		 9761 case 'n':
9762 optimize_align_code = 0;
9763 break;
9764
a38cf1db
AM		 9765 case 'q':
9766 quiet_warnings = 1;
252b5132
RH		 9767 break;
9768
9769#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 9770 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9771 should be emitted or not. FIXME: Not implemented. */
9772 case 'Q':
252b5132
RH		 9773 break;
9774
9775 /* -V: SVR4 argument to print version ID. */
9776 case 'V':
9777 print_version_id ();
9778 break;
9779
a38cf1db
AM		 9780 /* -k: Ignore for FreeBSD compatibility. */
9781 case 'k':
252b5132 9782 break;
4cc782b5
ILT		 9783
9784 case 's':
9785 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 9786 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 9787 break;
8dcea932
L		 9788
9789 case OPTION_MSHARED:
9790 shared = 1;
9791 break;
99ad8390 9792#endif
321098a5 9793#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9794 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 9795 case OPTION_64:
9796 {
9797 const char **list, **l;
9798
3e73aa7c
JH		 9799 list = bfd_target_list ();
9800 for (l = list; *l != NULL; l++)
8620418b 9801 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 9802 || strcmp (*l, "coff-x86-64") == 0
9803 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 9804 || strcmp (*l, "pei-x86-64") == 0
9805 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 9806 {
9807 default_arch = "x86_64";
9808 break;
9809 }
3e73aa7c 9810 if (*l == NULL)
2b5d6a91 9811 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 9812 free (list);
9813 }
9814 break;
9815#endif
252b5132 9816
351f65ca 9817#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9818 case OPTION_X32:
351f65ca
L		 9819 if (IS_ELF)
9820 {
9821 const char **list, **l;
9822
9823 list = bfd_target_list ();
9824 for (l = list; *l != NULL; l++)
9825 if (CONST_STRNEQ (*l, "elf32-x86-64"))
9826 {
9827 default_arch = "x86_64:32";
9828 break;
9829 }
9830 if (*l == NULL)
2b5d6a91 9831 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 9832 free (list);
9833 }
9834 else
9835 as_fatal (_("32bit x86_64 is only supported for ELF"));
9836 break;
9837#endif
9838
6e0b89ee
AM		 9839 case OPTION_32:
9840 default_arch = "i386";
9841 break;
9842
b3b91714
AM		 9843 case OPTION_DIVIDE:
9844#ifdef SVR4_COMMENT_CHARS
9845 {
9846 char *n, *t;
9847 const char *s;
9848
add39d23 9849 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
b3b91714
AM		 9850 t = n;
9851 for (s = i386_comment_chars; *s != '\0'; s++)
9852 if (*s != '/')
9853 *t++ = *s;
9854 *t = '\0';
9855 i386_comment_chars = n;
9856 }
9857#endif
9858 break;
9859
9103f4f4 9860 case OPTION_MARCH:
293f5f65
L		 9861 saved = xstrdup (arg);
9862 arch = saved;
9863 /* Allow -march=+nosse. */
9864 if (*arch == '+')
9865 arch++;
6305a203 9866 do
9103f4f4 9867 {
6305a203 9868 if (*arch == '.')
2b5d6a91 9869 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9870 next = strchr (arch, '+');
9871 if (next)
9872 *next++ = '\0';
91d6fa6a 9873 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9874 {
91d6fa6a 9875 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 9876 {
6305a203 9877 /* Processor. */
1ded5609
JB		 9878 if (! cpu_arch[j].flags.bitfield.cpui386)
9879 continue;
9880
91d6fa6a 9881 cpu_arch_name = cpu_arch[j].name;
6305a203 9882 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 9883 cpu_arch_flags = cpu_arch[j].flags;
9884 cpu_arch_isa = cpu_arch[j].type;
9885 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 9886 if (!cpu_arch_tune_set)
9887 {
9888 cpu_arch_tune = cpu_arch_isa;
9889 cpu_arch_tune_flags = cpu_arch_isa_flags;
9890 }
9891 break;
9892 }
91d6fa6a
NC		 9893 else if (*cpu_arch [j].name == '.'
9894 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 9895 {
9896 /* ISA entension. */
9897 i386_cpu_flags flags;
309d3373 9898
293f5f65
L		 9899 flags = cpu_flags_or (cpu_arch_flags,
9900 cpu_arch[j].flags);
81486035
L		 9901
9902 if (!valid_iamcu_cpu_flags (&flags))
9903 as_fatal (_("`%s' isn't valid for Intel MCU"), arch);
9904 else if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 9905 {
9906 if (cpu_sub_arch_name)
9907 {
9908 char *name = cpu_sub_arch_name;
9909 cpu_sub_arch_name = concat (name,
91d6fa6a 9910 cpu_arch[j].name,
1bf57e9f 9911 (const char *) NULL);
6305a203
L		 9912 free (name);
9913 }
9914 else
91d6fa6a 9915 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 9916 cpu_arch_flags = flags;
a586129e 9917 cpu_arch_isa_flags = flags;
6305a203
L		 9918 }
9919 break;
ccc9c027 9920 }
9103f4f4 9921 }
6305a203 9922
293f5f65
L		 9923 if (j >= ARRAY_SIZE (cpu_arch))
9924 {
9925 /* Disable an ISA entension. */
9926 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
9927 if (strcmp (arch, cpu_noarch [j].name) == 0)
9928 {
9929 i386_cpu_flags flags;
9930
9931 flags = cpu_flags_and_not (cpu_arch_flags,
9932 cpu_noarch[j].flags);
9933 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
9934 {
9935 if (cpu_sub_arch_name)
9936 {
9937 char *name = cpu_sub_arch_name;
9938 cpu_sub_arch_name = concat (arch,
9939 (const char *) NULL);
9940 free (name);
9941 }
9942 else
9943 cpu_sub_arch_name = xstrdup (arch);
9944 cpu_arch_flags = flags;
9945 cpu_arch_isa_flags = flags;
9946 }
9947 break;
9948 }
9949
9950 if (j >= ARRAY_SIZE (cpu_noarch))
9951 j = ARRAY_SIZE (cpu_arch);
9952 }
9953
91d6fa6a 9954 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9955 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9956
9957 arch = next;
9103f4f4 9958 }
293f5f65
L		 9959 while (next != NULL);
9960 free (saved);
9103f4f4
L		 9961 break;
9962
9963 case OPTION_MTUNE:
9964 if (*arg == '.')
2b5d6a91 9965 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 9966 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9967 {
91d6fa6a 9968 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 9969 {
ccc9c027 9970 cpu_arch_tune_set = 1;
91d6fa6a
NC		 9971 cpu_arch_tune = cpu_arch [j].type;
9972 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 9973 break;
9974 }
9975 }
91d6fa6a 9976 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9977 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 9978 break;
9979
1efbbeb4
L		 9980 case OPTION_MMNEMONIC:
9981 if (strcasecmp (arg, "att") == 0)
9982 intel_mnemonic = 0;
9983 else if (strcasecmp (arg, "intel") == 0)
9984 intel_mnemonic = 1;
9985 else
2b5d6a91 9986 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 9987 break;
9988
9989 case OPTION_MSYNTAX:
9990 if (strcasecmp (arg, "att") == 0)
9991 intel_syntax = 0;
9992 else if (strcasecmp (arg, "intel") == 0)
9993 intel_syntax = 1;
9994 else
2b5d6a91 9995 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 9996 break;
9997
9998 case OPTION_MINDEX_REG:
9999 allow_index_reg = 1;
10000 break;
10001
10002 case OPTION_MNAKED_REG:
10003 allow_naked_reg = 1;
10004 break;
10005
10006 case OPTION_MOLD_GCC:
10007 old_gcc = 1;
1efbbeb4
L		 10008 break;
10009
c0f3af97
L		 10010 case OPTION_MSSE2AVX:
10011 sse2avx = 1;
10012 break;
10013
daf50ae7
L		 10014 case OPTION_MSSE_CHECK:
10015 if (strcasecmp (arg, "error") == 0)
7bab8ab5 10016 sse_check = check_error;
daf50ae7 10017 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 10018 sse_check = check_warning;
daf50ae7 10019 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 10020 sse_check = check_none;
daf50ae7 10021 else
2b5d6a91 10022 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 10023 break;
10024
7bab8ab5
JB		 10025 case OPTION_MOPERAND_CHECK:
10026 if (strcasecmp (arg, "error") == 0)
10027 operand_check = check_error;
10028 else if (strcasecmp (arg, "warning") == 0)
10029 operand_check = check_warning;
10030 else if (strcasecmp (arg, "none") == 0)
10031 operand_check = check_none;
10032 else
10033 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10034 break;
10035
539f890d
L		 10036 case OPTION_MAVXSCALAR:
10037 if (strcasecmp (arg, "128") == 0)
10038 avxscalar = vex128;
10039 else if (strcasecmp (arg, "256") == 0)
10040 avxscalar = vex256;
10041 else
2b5d6a91 10042 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 10043 break;
10044
7e8b059b
L		 10045 case OPTION_MADD_BND_PREFIX:
10046 add_bnd_prefix = 1;
10047 break;
10048
43234a1e
L		 10049 case OPTION_MEVEXLIG:
10050 if (strcmp (arg, "128") == 0)
10051 evexlig = evexl128;
10052 else if (strcmp (arg, "256") == 0)
10053 evexlig = evexl256;
10054 else if (strcmp (arg, "512") == 0)
10055 evexlig = evexl512;
10056 else
10057 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10058 break;
10059
d3d3c6db
IT		 10060 case OPTION_MEVEXRCIG:
10061 if (strcmp (arg, "rne") == 0)
10062 evexrcig = rne;
10063 else if (strcmp (arg, "rd") == 0)
10064 evexrcig = rd;
10065 else if (strcmp (arg, "ru") == 0)
10066 evexrcig = ru;
10067 else if (strcmp (arg, "rz") == 0)
10068 evexrcig = rz;
10069 else
10070 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10071 break;
10072
43234a1e
L		 10073 case OPTION_MEVEXWIG:
10074 if (strcmp (arg, "0") == 0)
10075 evexwig = evexw0;
10076 else if (strcmp (arg, "1") == 0)
10077 evexwig = evexw1;
10078 else
10079 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10080 break;
10081
167ad85b
TG		 10082# if defined (TE_PE) || defined (TE_PEP)
10083 case OPTION_MBIG_OBJ:
10084 use_big_obj = 1;
10085 break;
10086#endif
10087
d1982f93 10088 case OPTION_MOMIT_LOCK_PREFIX:
d022bddd
IT		 10089 if (strcasecmp (arg, "yes") == 0)
10090 omit_lock_prefix = 1;
10091 else if (strcasecmp (arg, "no") == 0)
10092 omit_lock_prefix = 0;
10093 else
10094 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10095 break;
10096
e4e00185
AS		 10097 case OPTION_MFENCE_AS_LOCK_ADD:
10098 if (strcasecmp (arg, "yes") == 0)
10099 avoid_fence = 1;
10100 else if (strcasecmp (arg, "no") == 0)
10101 avoid_fence = 0;
10102 else
10103 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10104 break;
10105
0cb4071e
L		 10106 case OPTION_MRELAX_RELOCATIONS:
10107 if (strcasecmp (arg, "yes") == 0)
10108 generate_relax_relocations = 1;
10109 else if (strcasecmp (arg, "no") == 0)
10110 generate_relax_relocations = 0;
10111 else
10112 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10113 break;
10114
5db04b09 10115 case OPTION_MAMD64:
e89c5eaa 10116 intel64 = 0;
5db04b09
L		 10117 break;
10118
10119 case OPTION_MINTEL64:
e89c5eaa 10120 intel64 = 1;
5db04b09
L		 10121 break;
10122
252b5132
RH		 10123 default:
10124 return 0;
10125 }
10126 return 1;
10127}
10128
8a2c8fef
L		 10129#define MESSAGE_TEMPLATE \
10130" "
10131
293f5f65
L		 10132static char *
10133output_message (FILE *stream, char *p, char *message, char *start,
10134 int *left_p, const char *name, int len)
10135{
10136 int size = sizeof (MESSAGE_TEMPLATE);
10137 int left = *left_p;
10138
10139 /* Reserve 2 spaces for ", " or ",\0" */
10140 left -= len + 2;
10141
10142 /* Check if there is any room. */
10143 if (left >= 0)
10144 {
10145 if (p != start)
10146 {
10147 *p++ = ',';
10148 *p++ = ' ';
10149 }
10150 p = mempcpy (p, name, len);
10151 }
10152 else
10153 {
10154 /* Output the current message now and start a new one. */
10155 *p++ = ',';
10156 *p = '\0';
10157 fprintf (stream, "%s\n", message);
10158 p = start;
10159 left = size - (start - message) - len - 2;
10160
10161 gas_assert (left >= 0);
10162
10163 p = mempcpy (p, name, len);
10164 }
10165
10166 *left_p = left;
10167 return p;
10168}
10169
8a2c8fef 10170static void
1ded5609 10171show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 10172{
10173 static char message[] = MESSAGE_TEMPLATE;
10174 char *start = message + 27;
10175 char *p;
10176 int size = sizeof (MESSAGE_TEMPLATE);
10177 int left;
10178 const char *name;
10179 int len;
10180 unsigned int j;
10181
10182 p = start;
10183 left = size - (start - message);
10184 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10185 {
10186 /* Should it be skipped? */
10187 if (cpu_arch [j].skip)
10188 continue;
10189
10190 name = cpu_arch [j].name;
10191 len = cpu_arch [j].len;
10192 if (*name == '.')
10193 {
10194 /* It is an extension. Skip if we aren't asked to show it. */
10195 if (ext)
10196 {
10197 name++;
10198 len--;
10199 }
10200 else
10201 continue;
10202 }
10203 else if (ext)
10204 {
10205 /* It is an processor. Skip if we show only extension. */
10206 continue;
10207 }
1ded5609
JB		 10208 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10209 {
10210 /* It is an impossible processor - skip. */
10211 continue;
10212 }
8a2c8fef 10213
293f5f65 10214 p = output_message (stream, p, message, start, &left, name, len);
8a2c8fef
L		 10215 }
10216
293f5f65
L		 10217 /* Display disabled extensions. */
10218 if (ext)
10219 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10220 {
10221 name = cpu_noarch [j].name;
10222 len = cpu_noarch [j].len;
10223 p = output_message (stream, p, message, start, &left, name,
10224 len);
10225 }
10226
8a2c8fef
L		 10227 *p = '\0';
10228 fprintf (stream, "%s\n", message);
10229}
10230
252b5132 10231void
8a2c8fef 10232md_show_usage (FILE *stream)
252b5132 10233{
4cc782b5
ILT		 10234#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10235 fprintf (stream, _("\
a38cf1db
AM		 10236 -Q ignored\n\
10237 -V print assembler version number\n\
b3b91714
AM		 10238 -k ignored\n"));
10239#endif
10240 fprintf (stream, _("\
12b55ccc 10241 -n Do not optimize code alignment\n\
b3b91714
AM		 10242 -q quieten some warnings\n"));
10243#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10244 fprintf (stream, _("\
a38cf1db 10245 -s ignored\n"));
b3b91714 10246#endif
321098a5
L		 10247#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10248 || defined (TE_PE) || defined (TE_PEP))
751d281c 10249 fprintf (stream, _("\
570561f7 10250 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10251#endif
b3b91714
AM		 10252#ifdef SVR4_COMMENT_CHARS
10253 fprintf (stream, _("\
10254 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10255#else
10256 fprintf (stream, _("\
b3b91714 10257 --divide ignored\n"));
4cc782b5 10258#endif
9103f4f4 10259 fprintf (stream, _("\
6305a203 10260 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10261 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10262 show_arch (stream, 0, 1);
8a2c8fef
L		 10263 fprintf (stream, _("\
10264 EXTENSION is combination of:\n"));
1ded5609 10265 show_arch (stream, 1, 0);
6305a203 10266 fprintf (stream, _("\
8a2c8fef 10267 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10268 show_arch (stream, 0, 0);
ba104c83 10269 fprintf (stream, _("\
c0f3af97
L		 10270 -msse2avx encode SSE instructions with VEX prefix\n"));
10271 fprintf (stream, _("\
daf50ae7
L		 10272 -msse-check=[none|error|warning]\n\
10273 check SSE instructions\n"));
10274 fprintf (stream, _("\
7bab8ab5
JB		 10275 -moperand-check=[none|error|warning]\n\
10276 check operand combinations for validity\n"));
10277 fprintf (stream, _("\
539f890d
L		 10278 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10279 length\n"));
10280 fprintf (stream, _("\
43234a1e
L		 10281 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10282 length\n"));
10283 fprintf (stream, _("\
10284 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10285 for EVEX.W bit ignored instructions\n"));
10286 fprintf (stream, _("\
d3d3c6db
IT		 10287 -mevexrcig=[rne|rd|ru|rz]\n\
10288 encode EVEX instructions with specific EVEX.RC value\n\
10289 for SAE-only ignored instructions\n"));
10290 fprintf (stream, _("\
ba104c83
L		 10291 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10292 fprintf (stream, _("\
10293 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10294 fprintf (stream, _("\
10295 -mindex-reg support pseudo index registers\n"));
10296 fprintf (stream, _("\
10297 -mnaked-reg don't require `%%' prefix for registers\n"));
10298 fprintf (stream, _("\
10299 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 10300 fprintf (stream, _("\
10301 -madd-bnd-prefix add BND prefix for all valid branches\n"));
8dcea932
L		 10302 fprintf (stream, _("\
10303 -mshared disable branch optimization for shared code\n"));
167ad85b
TG		 10304# if defined (TE_PE) || defined (TE_PEP)
10305 fprintf (stream, _("\
10306 -mbig-obj generate big object files\n"));
10307#endif
d022bddd
IT		 10308 fprintf (stream, _("\
10309 -momit-lock-prefix=[no|yes]\n\
10310 strip all lock prefixes\n"));
5db04b09 10311 fprintf (stream, _("\
e4e00185
AS		 10312 -mfence-as-lock-add=[no|yes]\n\
10313 encode lfence, mfence and sfence as\n\
10314 lock addl $0x0, (%%{re}sp)\n"));
10315 fprintf (stream, _("\
0cb4071e
L		 10316 -mrelax-relocations=[no|yes]\n\
10317 generate relax relocations\n"));
10318 fprintf (stream, _("\
5db04b09
L		 10319 -mamd64 accept only AMD64 ISA\n"));
10320 fprintf (stream, _("\
10321 -mintel64 accept only Intel64 ISA\n"));
252b5132
RH		 10322}
10323
3e73aa7c 10324#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 10325 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 10326 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 10327
10328/* Pick the target format to use. */
10329
47926f60 10330const char *
e3bb37b5 10331i386_target_format (void)
252b5132 10332{
351f65ca
L		 10333 if (!strncmp (default_arch, "x86_64", 6))
10334 {
10335 update_code_flag (CODE_64BIT, 1);
10336 if (default_arch[6] == '\0')
7f56bc95 10337 x86_elf_abi = X86_64_ABI;
351f65ca 10338 else
7f56bc95 10339 x86_elf_abi = X86_64_X32_ABI;
351f65ca 10340 }
3e73aa7c 10341 else if (!strcmp (default_arch, "i386"))
78f12dd3 10342 update_code_flag (CODE_32BIT, 1);
5197d474
L		 10343 else if (!strcmp (default_arch, "iamcu"))
10344 {
10345 update_code_flag (CODE_32BIT, 1);
10346 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10347 {
10348 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10349 cpu_arch_name = "iamcu";
10350 cpu_sub_arch_name = NULL;
10351 cpu_arch_flags = iamcu_flags;
10352 cpu_arch_isa = PROCESSOR_IAMCU;
10353 cpu_arch_isa_flags = iamcu_flags;
10354 if (!cpu_arch_tune_set)
10355 {
10356 cpu_arch_tune = cpu_arch_isa;
10357 cpu_arch_tune_flags = cpu_arch_isa_flags;
10358 }
10359 }
10360 else
10361 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10362 cpu_arch_name);
10363 }
3e73aa7c 10364 else
2b5d6a91 10365 as_fatal (_("unknown architecture"));
89507696
JB		 10366
10367 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10368 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10369 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10370 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10371
252b5132
RH		 10372 switch (OUTPUT_FLAVOR)
10373 {
9384f2ff 10374#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 10375 case bfd_target_aout_flavour:
47926f60 10376 return AOUT_TARGET_FORMAT;
4c63da97 10377#endif
9384f2ff
AM		 10378#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10379# if defined (TE_PE) || defined (TE_PEP)
10380 case bfd_target_coff_flavour:
167ad85b
TG		 10381 if (flag_code == CODE_64BIT)
10382 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10383 else
10384 return "pe-i386";
9384f2ff 10385# elif defined (TE_GO32)
0561d57c
JK		 10386 case bfd_target_coff_flavour:
10387 return "coff-go32";
9384f2ff 10388# else
252b5132
RH		 10389 case bfd_target_coff_flavour:
10390 return "coff-i386";
9384f2ff 10391# endif
4c63da97 10392#endif
3e73aa7c 10393#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 10394 case bfd_target_elf_flavour:
3e73aa7c 10395 {
351f65ca
L		 10396 const char *format;
10397
10398 switch (x86_elf_abi)
4fa24527 10399 {
351f65ca
L		 10400 default:
10401 format = ELF_TARGET_FORMAT;
10402 break;
7f56bc95 10403 case X86_64_ABI:
351f65ca 10404 use_rela_relocations = 1;
4fa24527 10405 object_64bit = 1;
351f65ca
L		 10406 format = ELF_TARGET_FORMAT64;
10407 break;
7f56bc95 10408 case X86_64_X32_ABI:
4fa24527 10409 use_rela_relocations = 1;
351f65ca 10410 object_64bit = 1;
862be3fb 10411 disallow_64bit_reloc = 1;
351f65ca
L		 10412 format = ELF_TARGET_FORMAT32;
10413 break;
4fa24527 10414 }
3632d14b 10415 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10416 {
7f56bc95 10417 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10418 as_fatal (_("Intel L1OM is 64bit only"));
10419 return ELF_TARGET_L1OM_FORMAT;
10420 }
b49f93f6 10421 else if (cpu_arch_isa == PROCESSOR_K1OM)
7a9068fe
L		 10422 {
10423 if (x86_elf_abi != X86_64_ABI)
10424 as_fatal (_("Intel K1OM is 64bit only"));
10425 return ELF_TARGET_K1OM_FORMAT;
10426 }
81486035
L		 10427 else if (cpu_arch_isa == PROCESSOR_IAMCU)
10428 {
10429 if (x86_elf_abi != I386_ABI)
10430 as_fatal (_("Intel MCU is 32bit only"));
10431 return ELF_TARGET_IAMCU_FORMAT;
10432 }
8a9036a4 10433 else
351f65ca 10434 return format;
3e73aa7c 10435 }
e57f8c65
TG		 10436#endif
10437#if defined (OBJ_MACH_O)
10438 case bfd_target_mach_o_flavour:
d382c579
TG		 10439 if (flag_code == CODE_64BIT)
10440 {
10441 use_rela_relocations = 1;
10442 object_64bit = 1;
10443 return "mach-o-x86-64";
10444 }
10445 else
10446 return "mach-o-i386";
4c63da97 10447#endif
252b5132
RH		 10448 default:
10449 abort ();
10450 return NULL;
10451 }
10452}
10453
47926f60 10454#endif /* OBJ_MAYBE_ more than one */
252b5132 10455\f
252b5132 10456symbolS *
7016a5d5 10457md_undefined_symbol (char *name)
252b5132 10458{
18dc2407
ILT		 10459 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10460 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10461 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10462 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10463 {
10464 if (!GOT_symbol)
10465 {
10466 if (symbol_find (name))
10467 as_bad (_("GOT already in symbol table"));
10468 GOT_symbol = symbol_new (name, undefined_section,
10469 (valueT) 0, &zero_address_frag);
10470 };
10471 return GOT_symbol;
10472 }
252b5132
RH		 10473 return 0;
10474}
10475
10476/* Round up a section size to the appropriate boundary. */
47926f60 10477
252b5132 10478valueT
7016a5d5 10479md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10480{
4c63da97
AM		 10481#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10482 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10483 {
10484 /* For a.out, force the section size to be aligned. If we don't do
10485 this, BFD will align it for us, but it will not write out the
10486 final bytes of the section. This may be a bug in BFD, but it is
10487 easier to fix it here since that is how the other a.out targets
10488 work. */
10489 int align;
10490
10491 align = bfd_get_section_alignment (stdoutput, segment);
8d3842cd 10492 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
4c63da97 10493 }
252b5132
RH		 10494#endif
10495
10496 return size;
10497}
10498
10499/* On the i386, PC-relative offsets are relative to the start of the
10500 next instruction. That is, the address of the offset, plus its
10501 size, since the offset is always the last part of the insn. */
10502
10503long
e3bb37b5 10504md_pcrel_from (fixS *fixP)
252b5132
RH		 10505{
10506 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10507}
10508
10509#ifndef I386COFF
10510
10511static void
e3bb37b5 10512s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10513{
29b0f896 10514 int temp;
252b5132 10515
8a75718c
JB		 10516#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10517 if (IS_ELF)
10518 obj_elf_section_change_hook ();
10519#endif
252b5132
RH		 10520 temp = get_absolute_expression ();
10521 subseg_set (bss_section, (subsegT) temp);
10522 demand_empty_rest_of_line ();
10523}
10524
10525#endif
10526
252b5132 10527void
e3bb37b5 10528i386_validate_fix (fixS *fixp)
252b5132 10529{
02a86693 10530 if (fixp->fx_subsy)
252b5132 10531 {
02a86693 10532 if (fixp->fx_subsy == GOT_symbol)
23df1078 10533 {
02a86693
L		 10534 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10535 {
10536 if (!object_64bit)
10537 abort ();
10538#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10539 if (fixp->fx_tcbit2)
56ceb5b5
L		 10540 fixp->fx_r_type = (fixp->fx_tcbit
10541 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10542 : BFD_RELOC_X86_64_GOTPCRELX);
02a86693
L		 10543 else
10544#endif
10545 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10546 }
d6ab8113 10547 else
02a86693
L		 10548 {
10549 if (!object_64bit)
10550 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10551 else
10552 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
10553 }
10554 fixp->fx_subsy = 0;
23df1078 10555 }
252b5132 10556 }
02a86693
L		 10557#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10558 else if (!object_64bit)
10559 {
10560 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
10561 && fixp->fx_tcbit2)
10562 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
10563 }
10564#endif
252b5132
RH		 10565}
10566
252b5132 10567arelent *
7016a5d5 10568tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10569{
10570 arelent *rel;
10571 bfd_reloc_code_real_type code;
10572
10573 switch (fixp->fx_r_type)
10574 {
8ce3d284 10575#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10576 case BFD_RELOC_SIZE32:
10577 case BFD_RELOC_SIZE64:
10578 if (S_IS_DEFINED (fixp->fx_addsy)
10579 && !S_IS_EXTERNAL (fixp->fx_addsy))
10580 {
10581 /* Resolve size relocation against local symbol to size of
10582 the symbol plus addend. */
10583 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10584 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10585 && !fits_in_unsigned_long (value))
10586 as_bad_where (fixp->fx_file, fixp->fx_line,
10587 _("symbol size computation overflow"));
10588 fixp->fx_addsy = NULL;
10589 fixp->fx_subsy = NULL;
10590 md_apply_fix (fixp, (valueT *) &value, NULL);
10591 return NULL;
10592 }
8ce3d284 10593#endif
8fd4256d 10594
3e73aa7c
JH		 10595 case BFD_RELOC_X86_64_PLT32:
10596 case BFD_RELOC_X86_64_GOT32:
10597 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 10598 case BFD_RELOC_X86_64_GOTPCRELX:
10599 case BFD_RELOC_X86_64_REX_GOTPCRELX:
252b5132
RH		 10600 case BFD_RELOC_386_PLT32:
10601 case BFD_RELOC_386_GOT32:
02a86693 10602 case BFD_RELOC_386_GOT32X:
252b5132
RH		 10603 case BFD_RELOC_386_GOTOFF:
10604 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10605 case BFD_RELOC_386_TLS_GD:
10606 case BFD_RELOC_386_TLS_LDM:
10607 case BFD_RELOC_386_TLS_LDO_32:
10608 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10609 case BFD_RELOC_386_TLS_IE:
10610 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10611 case BFD_RELOC_386_TLS_LE_32:
10612 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10613 case BFD_RELOC_386_TLS_GOTDESC:
10614 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10615 case BFD_RELOC_X86_64_TLSGD:
10616 case BFD_RELOC_X86_64_TLSLD:
10617 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10618 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10619 case BFD_RELOC_X86_64_GOTTPOFF:
10620 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10621 case BFD_RELOC_X86_64_TPOFF64:
10622 case BFD_RELOC_X86_64_GOTOFF64:
10623 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10624 case BFD_RELOC_X86_64_GOT64:
10625 case BFD_RELOC_X86_64_GOTPCREL64:
10626 case BFD_RELOC_X86_64_GOTPC64:
10627 case BFD_RELOC_X86_64_GOTPLT64:
10628 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10629 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10630 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10631 case BFD_RELOC_RVA:
10632 case BFD_RELOC_VTABLE_ENTRY:
10633 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10634#ifdef TE_PE
10635 case BFD_RELOC_32_SECREL:
10636#endif
252b5132
RH		 10637 code = fixp->fx_r_type;
10638 break;
dbbaec26
L		 10639 case BFD_RELOC_X86_64_32S:
10640 if (!fixp->fx_pcrel)
10641 {
10642 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10643 code = fixp->fx_r_type;
10644 break;
10645 }
252b5132 10646 default:
93382f6d 10647 if (fixp->fx_pcrel)
252b5132 10648 {
93382f6d
AM		 10649 switch (fixp->fx_size)
10650 {
10651 default:
b091f402
AM		 10652 as_bad_where (fixp->fx_file, fixp->fx_line,
10653 _("can not do %d byte pc-relative relocation"),
10654 fixp->fx_size);
93382f6d
AM		 10655 code = BFD_RELOC_32_PCREL;
10656 break;
10657 case 1: code = BFD_RELOC_8_PCREL; break;
10658 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 10659 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 10660#ifdef BFD64
10661 case 8: code = BFD_RELOC_64_PCREL; break;
10662#endif
93382f6d
AM		 10663 }
10664 }
10665 else
10666 {
10667 switch (fixp->fx_size)
10668 {
10669 default:
b091f402
AM		 10670 as_bad_where (fixp->fx_file, fixp->fx_line,
10671 _("can not do %d byte relocation"),
10672 fixp->fx_size);
93382f6d
AM		 10673 code = BFD_RELOC_32;
10674 break;
10675 case 1: code = BFD_RELOC_8; break;
10676 case 2: code = BFD_RELOC_16; break;
10677 case 4: code = BFD_RELOC_32; break;
937149dd 10678#ifdef BFD64
3e73aa7c 10679 case 8: code = BFD_RELOC_64; break;
937149dd 10680#endif
93382f6d 10681 }
252b5132
RH		 10682 }
10683 break;
10684 }
252b5132 10685
d182319b
JB		 10686 if ((code == BFD_RELOC_32
10687 || code == BFD_RELOC_32_PCREL
10688 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10689 && GOT_symbol
10690 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10691 {
4fa24527 10692 if (!object_64bit)
d6ab8113
JB		 10693 code = BFD_RELOC_386_GOTPC;
10694 else
10695 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10696 }
7b81dfbb
AJ		 10697 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10698 && GOT_symbol
10699 && fixp->fx_addsy == GOT_symbol)
10700 {
10701 code = BFD_RELOC_X86_64_GOTPC64;
10702 }
252b5132 10703
add39d23
TS		 10704 rel = XNEW (arelent);
10705 rel->sym_ptr_ptr = XNEW (asymbol *);
49309057 10706 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10707
10708 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10709
3e73aa7c
JH		 10710 if (!use_rela_relocations)
10711 {
10712 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10713 vtable entry to be used in the relocation's section offset. */
10714 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10715 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10716#if defined (OBJ_COFF) && defined (TE_PE)
10717 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10718 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10719 else
10720#endif
c6682705 10721 rel->addend = 0;
3e73aa7c
JH		 10722 }
10723 /* Use the rela in 64bit mode. */
252b5132 10724 else
3e73aa7c 10725 {
862be3fb
L		 10726 if (disallow_64bit_reloc)
10727 switch (code)
10728 {
862be3fb
L		 10729 case BFD_RELOC_X86_64_DTPOFF64:
10730 case BFD_RELOC_X86_64_TPOFF64:
10731 case BFD_RELOC_64_PCREL:
10732 case BFD_RELOC_X86_64_GOTOFF64:
10733 case BFD_RELOC_X86_64_GOT64:
10734 case BFD_RELOC_X86_64_GOTPCREL64:
10735 case BFD_RELOC_X86_64_GOTPC64:
10736 case BFD_RELOC_X86_64_GOTPLT64:
10737 case BFD_RELOC_X86_64_PLTOFF64:
10738 as_bad_where (fixp->fx_file, fixp->fx_line,
10739 _("cannot represent relocation type %s in x32 mode"),
10740 bfd_get_reloc_code_name (code));
10741 break;
10742 default:
10743 break;
10744 }
10745
062cd5e7
AS		 10746 if (!fixp->fx_pcrel)
10747 rel->addend = fixp->fx_offset;
10748 else
10749 switch (code)
10750 {
10751 case BFD_RELOC_X86_64_PLT32:
10752 case BFD_RELOC_X86_64_GOT32:
10753 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 10754 case BFD_RELOC_X86_64_GOTPCRELX:
10755 case BFD_RELOC_X86_64_REX_GOTPCRELX:
bffbf940
JJ		 10756 case BFD_RELOC_X86_64_TLSGD:
10757 case BFD_RELOC_X86_64_TLSLD:
10758 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 10759 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10760 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 10761 rel->addend = fixp->fx_offset - fixp->fx_size;
10762 break;
10763 default:
10764 rel->addend = (section->vma
10765 - fixp->fx_size
10766 + fixp->fx_addnumber
10767 + md_pcrel_from (fixp));
10768 break;
10769 }
3e73aa7c
JH		 10770 }
10771
252b5132
RH		 10772 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
10773 if (rel->howto == NULL)
10774 {
10775 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 10776 _("cannot represent relocation type %s"),
252b5132
RH		 10777 bfd_get_reloc_code_name (code));
10778 /* Set howto to a garbage value so that we can keep going. */
10779 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 10780 gas_assert (rel->howto != NULL);
252b5132
RH		 10781 }
10782
10783 return rel;
10784}
10785
ee86248c 10786#include "tc-i386-intel.c"
54cfded0 10787
a60de03c
JB		 10788void
10789tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 10790{
a60de03c
JB		 10791 int saved_naked_reg;
10792 char saved_register_dot;
54cfded0 10793
a60de03c
JB		 10794 saved_naked_reg = allow_naked_reg;
10795 allow_naked_reg = 1;
10796 saved_register_dot = register_chars['.'];
10797 register_chars['.'] = '.';
10798 allow_pseudo_reg = 1;
10799 expression_and_evaluate (exp);
10800 allow_pseudo_reg = 0;
10801 register_chars['.'] = saved_register_dot;
10802 allow_naked_reg = saved_naked_reg;
10803
e96d56a1 10804 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 10805 {
a60de03c
JB		 10806 if ((addressT) exp->X_add_number < i386_regtab_size)
10807 {
10808 exp->X_op = O_constant;
10809 exp->X_add_number = i386_regtab[exp->X_add_number]
10810 .dw2_regnum[flag_code >> 1];
10811 }
10812 else
10813 exp->X_op = O_illegal;
54cfded0 10814 }
54cfded0
AM		 10815}
10816
10817void
10818tc_x86_frame_initial_instructions (void)
10819{
a60de03c
JB		 10820 static unsigned int sp_regno[2];
10821
10822 if (!sp_regno[flag_code >> 1])
10823 {
10824 char *saved_input = input_line_pointer;
10825 char sp[][4] = {"esp", "rsp"};
10826 expressionS exp;
a4447b93 10827
a60de03c
JB		 10828 input_line_pointer = sp[flag_code >> 1];
10829 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 10830 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 10831 sp_regno[flag_code >> 1] = exp.X_add_number;
10832 input_line_pointer = saved_input;
10833 }
a4447b93 10834
61ff971f
L		 10835 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
10836 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 10837}
d2b2c203 10838
d7921315
L		 10839int
10840x86_dwarf2_addr_size (void)
10841{
10842#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10843 if (x86_elf_abi == X86_64_X32_ABI)
10844 return 4;
10845#endif
10846 return bfd_arch_bits_per_address (stdoutput) / 8;
10847}
10848
d2b2c203
DJ		 10849int
10850i386_elf_section_type (const char *str, size_t len)
10851{
10852 if (flag_code == CODE_64BIT
10853 && len == sizeof ("unwind") - 1
10854 && strncmp (str, "unwind", 6) == 0)
10855 return SHT_X86_64_UNWIND;
10856
10857 return -1;
10858}
bb41ade5 10859
ad5fec3b
EB		 10860#ifdef TE_SOLARIS
10861void
10862i386_solaris_fix_up_eh_frame (segT sec)
10863{
10864 if (flag_code == CODE_64BIT)
10865 elf_section_type (sec) = SHT_X86_64_UNWIND;
10866}
10867#endif
10868
bb41ade5
AM		 10869#ifdef TE_PE
10870void
10871tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10872{
91d6fa6a 10873 expressionS exp;
bb41ade5 10874
91d6fa6a
NC		 10875 exp.X_op = O_secrel;
10876 exp.X_add_symbol = symbol;
10877 exp.X_add_number = 0;
10878 emit_expr (&exp, size);
bb41ade5
AM		 10879}
10880#endif
3b22753a
L		 10881
10882#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10883/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10884
01e1a5bc 10885bfd_vma
6d4af3c2 10886x86_64_section_letter (int letter, const char **ptr_msg)
3b22753a
L		 10887{
10888 if (flag_code == CODE_64BIT)
10889 {
10890 if (letter == 'l')
10891 return SHF_X86_64_LARGE;
10892
8f3bae45 10893 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 10894 }
3b22753a 10895 else
8f3bae45 10896 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 10897 return -1;
10898}
10899
01e1a5bc 10900bfd_vma
3b22753a
L		 10901x86_64_section_word (char *str, size_t len)
10902{
8620418b 10903 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 10904 return SHF_X86_64_LARGE;
10905
10906 return -1;
10907}
10908
10909static void
10910handle_large_common (int small ATTRIBUTE_UNUSED)
10911{
10912 if (flag_code != CODE_64BIT)
10913 {
10914 s_comm_internal (0, elf_common_parse);
10915 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10916 }
10917 else
10918 {
10919 static segT lbss_section;
10920 asection *saved_com_section_ptr = elf_com_section_ptr;
10921 asection *saved_bss_section = bss_section;
10922
10923 if (lbss_section == NULL)
10924 {
10925 flagword applicable;
10926 segT seg = now_seg;
10927 subsegT subseg = now_subseg;
10928
10929 /* The .lbss section is for local .largecomm symbols. */
10930 lbss_section = subseg_new (".lbss", 0);
10931 applicable = bfd_applicable_section_flags (stdoutput);
10932 bfd_set_section_flags (stdoutput, lbss_section,
10933 applicable & SEC_ALLOC);
10934 seg_info (lbss_section)->bss = 1;
10935
10936 subseg_set (seg, subseg);
10937 }
10938
10939 elf_com_section_ptr = &_bfd_elf_large_com_section;
10940 bss_section = lbss_section;
10941
10942 s_comm_internal (0, elf_common_parse);
10943
10944 elf_com_section_ptr = saved_com_section_ptr;
10945 bss_section = saved_bss_section;
10946 }
10947}
10948#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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