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* gdbtypes.h (CHECK_TYPEDEF): Don't yield a value.
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
0bfee649 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
6305a203
L		 58/* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
62 LOCKREP_PREFIX. */
63#define WAIT_PREFIX 0
64#define SEG_PREFIX 1
65#define ADDR_PREFIX 2
66#define DATA_PREFIX 3
67#define LOCKREP_PREFIX 4
68#define REX_PREFIX 5 /* must come last. */
69#define MAX_PREFIXES 6 /* max prefixes per opcode */
70
71/* we define the syntax here (modulo base,index,scale syntax) */
72#define REGISTER_PREFIX '%'
73#define IMMEDIATE_PREFIX '$'
74#define ABSOLUTE_PREFIX '*'
75
76/* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78#define WORD_MNEM_SUFFIX 'w'
79#define BYTE_MNEM_SUFFIX 'b'
80#define SHORT_MNEM_SUFFIX 's'
81#define LONG_MNEM_SUFFIX 'l'
82#define QWORD_MNEM_SUFFIX 'q'
83#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 84#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 85/* Intel Syntax. Use a non-ascii letter since since it never appears
86 in instructions. */
87#define LONG_DOUBLE_MNEM_SUFFIX '\1'
88
89#define END_OF_INSN '\0'
90
91/*
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
96 END.
97 */
98typedef struct
99{
100 const template *start;
101 const template *end;
102}
103templates;
104
105/* 386 operand encoding bytes: see 386 book for details of this. */
106typedef struct
107{
108 unsigned int regmem; /* codes register or memory operand */
109 unsigned int reg; /* codes register operand (or extended opcode) */
110 unsigned int mode; /* how to interpret regmem & reg */
111}
112modrm_byte;
113
114/* x86-64 extension prefix. */
115typedef int rex_byte;
116
117/* The SSE5 instructions have a two bit instruction modifier (OC) that
118 is stored in two separate bytes in the instruction. Pick apart OC
119 into the 2 separate bits for instruction. */
120#define DREX_OC0(x) (((x) & 1) != 0)
121#define DREX_OC1(x) (((x) & 2) != 0)
122
123#define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */
124#define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */
125
126/* OC mappings */
127#define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */
128#define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */
129#define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */
130#define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */
131
132#define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */
133#define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */
134
135/* Information needed to create the DREX byte in SSE5 instructions. */
136typedef struct
137{
138 unsigned int reg; /* register */
139 unsigned int rex; /* REX flags */
140 unsigned int modrm_reg; /* which arg goes in the modrm.reg field */
141 unsigned int modrm_regmem; /* which arg goes in the modrm.regmem field */
142} drex_byte;
143
144/* 386 opcode byte to code indirect addressing. */
145typedef struct
146{
147 unsigned base;
148 unsigned index;
149 unsigned scale;
150}
151sib_byte;
152
6305a203
L		 153/* x86 arch names, types and features */
154typedef struct
155{
156 const char *name; /* arch name */
157 enum processor_type type; /* arch type */
158 i386_cpu_flags flags; /* cpu feature flags */
159}
160arch_entry;
161
e3bb37b5
L		 162static void set_code_flag (int);
163static void set_16bit_gcc_code_flag (int);
164static void set_intel_syntax (int);
1efbbeb4 165static void set_intel_mnemonic (int);
db51cc60 166static void set_allow_index_reg (int);
cb19c032 167static void set_sse_check (int);
e3bb37b5 168static void set_cpu_arch (int);
6482c264 169#ifdef TE_PE
e3bb37b5 170static void pe_directive_secrel (int);
6482c264 171#endif
e3bb37b5
L		 172static void signed_cons (int);
173static char *output_invalid (int c);
a7619375 174static int i386_att_operand (char *);
e3bb37b5
L		 175static int i386_intel_operand (char *, int);
176static const reg_entry *parse_register (char *, char **);
177static char *parse_insn (char *, char *);
178static char *parse_operands (char *, const char *);
179static void swap_operands (void);
4d456e3d 180static void swap_2_operands (int, int);
e3bb37b5
L		 181static void optimize_imm (void);
182static void optimize_disp (void);
fa99fab2 183static const template *match_template (void);
e3bb37b5
L		 184static int check_string (void);
185static int process_suffix (void);
186static int check_byte_reg (void);
187static int check_long_reg (void);
188static int check_qword_reg (void);
189static int check_word_reg (void);
190static int finalize_imm (void);
85f10a01 191static void process_drex (void);
e3bb37b5
L		 192static int process_operands (void);
193static const seg_entry *build_modrm_byte (void);
194static void output_insn (void);
195static void output_imm (fragS *, offsetT);
196static void output_disp (fragS *, offsetT);
29b0f896 197#ifndef I386COFF
e3bb37b5 198static void s_bss (int);
252b5132 199#endif
17d4e2a2
L		 200#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201static void handle_large_common (int small ATTRIBUTE_UNUSED);
202#endif
252b5132 203
a847613f 204static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 205
c0f3af97
L		 206/* VEX prefix. */
207typedef struct
208{
209 /* VEX prefix is either 2 byte or 3 byte. */
210 unsigned char bytes[3];
211 unsigned int length;
212 /* Destination or source register specifier. */
213 const reg_entry *register_specifier;
214} vex_prefix;
215
252b5132 216/* 'md_assemble ()' gathers together information and puts it into a
47926f60 217 i386_insn. */
252b5132 218
520dc8e8
AM		 219union i386_op
220 {
221 expressionS *disps;
222 expressionS *imms;
223 const reg_entry *regs;
224 };
225
252b5132
RH		 226struct _i386_insn
227 {
47926f60 228 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 229 template tm;
230
7d5e4556
L		 231 /* SUFFIX holds the instruction size suffix for byte, word, dword
232 or qword, if given. */
252b5132
RH		 233 char suffix;
234
47926f60 235 /* OPERANDS gives the number of given operands. */
252b5132
RH		 236 unsigned int operands;
237
238 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
239 of given register, displacement, memory operands and immediate
47926f60 240 operands. */
252b5132
RH		 241 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
242
243 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 244 use OP[i] for the corresponding operand. */
40fb9820 245 i386_operand_type types[MAX_OPERANDS];
252b5132 246
520dc8e8
AM		 247 /* Displacement expression, immediate expression, or register for each
248 operand. */
249 union i386_op op[MAX_OPERANDS];
252b5132 250
3e73aa7c
JH		 251 /* Flags for operands. */
252 unsigned int flags[MAX_OPERANDS];
253#define Operand_PCrel 1
254
252b5132 255 /* Relocation type for operand */
f86103b7 256 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 257
252b5132
RH		 258 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
259 the base index byte below. */
260 const reg_entry *base_reg;
261 const reg_entry *index_reg;
262 unsigned int log2_scale_factor;
263
264 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 265 explicit segment overrides are given. */
ce8a8b2f 266 const seg_entry *seg[2];
252b5132
RH		 267
268 /* PREFIX holds all the given prefix opcodes (usually null).
269 PREFIXES is the number of prefix opcodes. */
270 unsigned int prefixes;
271 unsigned char prefix[MAX_PREFIXES];
272
273 /* RM and SIB are the modrm byte and the sib byte where the
85f10a01
MM		 274 addressing modes of this insn are encoded. DREX is the byte
275 added by the SSE5 instructions. */
252b5132
RH		 276
277 modrm_byte rm;
3e73aa7c 278 rex_byte rex;
252b5132 279 sib_byte sib;
85f10a01 280 drex_byte drex;
c0f3af97 281 vex_prefix vex;
b6169b20
L		 282
283 /* Swap operand in encoding. */
284 unsigned int swap_operand : 1;
252b5132
RH		 285 };
286
287typedef struct _i386_insn i386_insn;
288
289/* List of chars besides those in app.c:symbol_chars that can start an
290 operand. Used to prevent the scrubber eating vital white-space. */
32137342 291const char extra_symbol_chars[] = "*%-(["
252b5132 292#ifdef LEX_AT
32137342
NC		 293 "@"
294#endif
295#ifdef LEX_QM
296 "?"
252b5132 297#endif
32137342 298 ;
252b5132 299
29b0f896
AM		 300#if (defined (TE_I386AIX) \
301 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 302 && !defined (TE_GNU) \
29b0f896 303 && !defined (TE_LINUX) \
32137342 304 && !defined (TE_NETWARE) \
29b0f896
AM		 305 && !defined (TE_FreeBSD) \
306 && !defined (TE_NetBSD)))
252b5132 307/* This array holds the chars that always start a comment. If the
b3b91714
AM		 308 pre-processor is disabled, these aren't very useful. The option
309 --divide will remove '/' from this list. */
310const char *i386_comment_chars = "#/";
311#define SVR4_COMMENT_CHARS 1
252b5132 312#define PREFIX_SEPARATOR '\\'
252b5132 313
b3b91714
AM		 314#else
315const char *i386_comment_chars = "#";
316#define PREFIX_SEPARATOR '/'
317#endif
318
252b5132
RH		 319/* This array holds the chars that only start a comment at the beginning of
320 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 321 .line and .file directives will appear in the pre-processed output.
322 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 323 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 324 #NO_APP at the beginning of its output.
325 Also note that comments started like this one will always work if
252b5132 326 '/' isn't otherwise defined. */
b3b91714 327const char line_comment_chars[] = "#/";
252b5132 328
63a0b638 329const char line_separator_chars[] = ";";
252b5132 330
ce8a8b2f
AM		 331/* Chars that can be used to separate mant from exp in floating point
332 nums. */
252b5132
RH		 333const char EXP_CHARS[] = "eE";
334
ce8a8b2f
AM		 335/* Chars that mean this number is a floating point constant
336 As in 0f12.456
337 or 0d1.2345e12. */
252b5132
RH		 338const char FLT_CHARS[] = "fFdDxX";
339
ce8a8b2f 340/* Tables for lexical analysis. */
252b5132
RH		 341static char mnemonic_chars[256];
342static char register_chars[256];
343static char operand_chars[256];
344static char identifier_chars[256];
345static char digit_chars[256];
346
ce8a8b2f 347/* Lexical macros. */
252b5132
RH		 348#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
349#define is_operand_char(x) (operand_chars[(unsigned char) x])
350#define is_register_char(x) (register_chars[(unsigned char) x])
351#define is_space_char(x) ((x) == ' ')
352#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
353#define is_digit_char(x) (digit_chars[(unsigned char) x])
354
0234cb7c 355/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 356static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
357
358/* md_assemble() always leaves the strings it's passed unaltered. To
359 effect this we maintain a stack of saved characters that we've smashed
360 with '\0's (indicating end of strings for various sub-fields of the
47926f60 361 assembler instruction). */
252b5132 362static char save_stack[32];
ce8a8b2f 363static char *save_stack_p;
252b5132
RH		 364#define END_STRING_AND_SAVE(s) \
365 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
366#define RESTORE_END_STRING(s) \
367 do { *(s) = *--save_stack_p; } while (0)
368
47926f60 369/* The instruction we're assembling. */
252b5132
RH		 370static i386_insn i;
371
372/* Possible templates for current insn. */
373static const templates *current_templates;
374
31b2323c
L		 375/* Per instruction expressionS buffers: max displacements & immediates. */
376static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
377static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 378
47926f60
KH		 379/* Current operand we are working on. */
380static int this_operand;
252b5132 381
3e73aa7c
JH		 382/* We support four different modes. FLAG_CODE variable is used to distinguish
383 these. */
384
385enum flag_code {
386 CODE_32BIT,
387 CODE_16BIT,
388 CODE_64BIT };
389
390static enum flag_code flag_code;
4fa24527 391static unsigned int object_64bit;
3e73aa7c
JH		 392static int use_rela_relocations = 0;
393
394/* The names used to print error messages. */
b77a7acd 395static const char *flag_code_names[] =
3e73aa7c
JH		 396 {
397 "32",
398 "16",
399 "64"
400 };
252b5132 401
47926f60
KH		 402/* 1 for intel syntax,
403 0 if att syntax. */
404static int intel_syntax = 0;
252b5132 405
1efbbeb4
L		 406/* 1 for intel mnemonic,
407 0 if att mnemonic. */
408static int intel_mnemonic = !SYSV386_COMPAT;
409
5209009a 410/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 411static int old_gcc = OLDGCC_COMPAT;
412
a60de03c
JB		 413/* 1 if pseudo registers are permitted. */
414static int allow_pseudo_reg = 0;
415
47926f60
KH		 416/* 1 if register prefix % not required. */
417static int allow_naked_reg = 0;
252b5132 418
ba104c83 419/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 420static int allow_index_reg = 0;
421
daf50ae7
L		 422static enum
423 {
424 sse_check_none = 0,
425 sse_check_warning,
426 sse_check_error
427 }
428sse_check;
429
2ca3ace5
L		 430/* Register prefix used for error message. */
431static const char *register_prefix = "%";
432
47926f60
KH		 433/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
434 leave, push, and pop instructions so that gcc has the same stack
435 frame as in 32 bit mode. */
436static char stackop_size = '\0';
eecb386c 437
12b55ccc
L		 438/* Non-zero to optimize code alignment. */
439int optimize_align_code = 1;
440
47926f60
KH		 441/* Non-zero to quieten some warnings. */
442static int quiet_warnings = 0;
a38cf1db 443
47926f60
KH		 444/* CPU name. */
445static const char *cpu_arch_name = NULL;
6305a203 446static char *cpu_sub_arch_name = NULL;
a38cf1db 447
47926f60 448/* CPU feature flags. */
40fb9820
L		 449static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
450
ccc9c027
L		 451/* If we have selected a cpu we are generating instructions for. */
452static int cpu_arch_tune_set = 0;
453
9103f4f4 454/* Cpu we are generating instructions for. */
fbf3f584 455enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 456
457/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 458static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 459
ccc9c027 460/* CPU instruction set architecture used. */
fbf3f584 461enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 462
9103f4f4 463/* CPU feature flags of instruction set architecture used. */
fbf3f584 464i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 465
fddf5b5b
AM		 466/* If set, conditional jumps are not automatically promoted to handle
467 larger than a byte offset. */
468static unsigned int no_cond_jump_promotion = 0;
469
c0f3af97
L		 470/* Encode SSE instructions with VEX prefix. */
471static unsigned int sse2avx;
472
29b0f896 473/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 474static symbolS *GOT_symbol;
29b0f896 475
a4447b93
RH		 476/* The dwarf2 return column, adjusted for 32 or 64 bit. */
477unsigned int x86_dwarf2_return_column;
478
479/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
480int x86_cie_data_alignment;
481
252b5132 482/* Interface to relax_segment.
fddf5b5b
AM		 483 There are 3 major relax states for 386 jump insns because the
484 different types of jumps add different sizes to frags when we're
485 figuring out what sort of jump to choose to reach a given label. */
252b5132 486
47926f60 487/* Types. */
93c2a809
AM		 488#define UNCOND_JUMP 0
489#define COND_JUMP 1
490#define COND_JUMP86 2
fddf5b5b 491
47926f60 492/* Sizes. */
252b5132
RH		 493#define CODE16 1
494#define SMALL 0
29b0f896 495#define SMALL16 (SMALL | CODE16)
252b5132 496#define BIG 2
29b0f896 497#define BIG16 (BIG | CODE16)
252b5132
RH		 498
499#ifndef INLINE
500#ifdef __GNUC__
501#define INLINE __inline__
502#else
503#define INLINE
504#endif
505#endif
506
fddf5b5b
AM		 507#define ENCODE_RELAX_STATE(type, size) \
508 ((relax_substateT) (((type) << 2) | (size)))
509#define TYPE_FROM_RELAX_STATE(s) \
510 ((s) >> 2)
511#define DISP_SIZE_FROM_RELAX_STATE(s) \
512 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 513
514/* This table is used by relax_frag to promote short jumps to long
515 ones where necessary. SMALL (short) jumps may be promoted to BIG
516 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
517 don't allow a short jump in a 32 bit code segment to be promoted to
518 a 16 bit offset jump because it's slower (requires data size
519 prefix), and doesn't work, unless the destination is in the bottom
520 64k of the code segment (The top 16 bits of eip are zeroed). */
521
522const relax_typeS md_relax_table[] =
523{
24eab124
AM		 524 /* The fields are:
525 1) most positive reach of this state,
526 2) most negative reach of this state,
93c2a809 527 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 528 4) which index into the table to try if we can't fit into this one. */
252b5132 529
fddf5b5b 530 /* UNCOND_JUMP states. */
93c2a809
AM		 531 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
532 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
533 /* dword jmp adds 4 bytes to frag:
534 0 extra opcode bytes, 4 displacement bytes. */
252b5132 535 {0, 0, 4, 0},
93c2a809
AM		 536 /* word jmp adds 2 byte2 to frag:
537 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 538 {0, 0, 2, 0},
539
93c2a809
AM		 540 /* COND_JUMP states. */
541 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
542 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
543 /* dword conditionals adds 5 bytes to frag:
544 1 extra opcode byte, 4 displacement bytes. */
545 {0, 0, 5, 0},
fddf5b5b 546 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 547 1 extra opcode byte, 2 displacement bytes. */
548 {0, 0, 3, 0},
549
550 /* COND_JUMP86 states. */
551 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
552 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
553 /* dword conditionals adds 5 bytes to frag:
554 1 extra opcode byte, 4 displacement bytes. */
555 {0, 0, 5, 0},
556 /* word conditionals add 4 bytes to frag:
557 1 displacement byte and a 3 byte long branch insn. */
558 {0, 0, 4, 0}
252b5132
RH		 559};
560
9103f4f4
L		 561static const arch_entry cpu_arch[] =
562{
6305a203
L		 563 { "generic32", PROCESSOR_GENERIC32,
564 CPU_GENERIC32_FLAGS },
565 { "generic64", PROCESSOR_GENERIC64,
566 CPU_GENERIC64_FLAGS },
567 { "i8086", PROCESSOR_UNKNOWN,
568 CPU_NONE_FLAGS },
569 { "i186", PROCESSOR_UNKNOWN,
570 CPU_I186_FLAGS },
571 { "i286", PROCESSOR_UNKNOWN,
572 CPU_I286_FLAGS },
573 { "i386", PROCESSOR_I386,
574 CPU_I386_FLAGS },
575 { "i486", PROCESSOR_I486,
576 CPU_I486_FLAGS },
577 { "i586", PROCESSOR_PENTIUM,
578 CPU_I586_FLAGS },
579 { "i686", PROCESSOR_PENTIUMPRO,
580 CPU_I686_FLAGS },
581 { "pentium", PROCESSOR_PENTIUM,
582 CPU_I586_FLAGS },
583 { "pentiumpro", PROCESSOR_PENTIUMPRO,
584 CPU_I686_FLAGS },
585 { "pentiumii", PROCESSOR_PENTIUMPRO,
586 CPU_P2_FLAGS },
587 { "pentiumiii",PROCESSOR_PENTIUMPRO,
588 CPU_P3_FLAGS },
589 { "pentium4", PROCESSOR_PENTIUM4,
590 CPU_P4_FLAGS },
591 { "prescott", PROCESSOR_NOCONA,
592 CPU_CORE_FLAGS },
593 { "nocona", PROCESSOR_NOCONA,
594 CPU_NOCONA_FLAGS },
595 { "yonah", PROCESSOR_CORE,
596 CPU_CORE_FLAGS },
597 { "core", PROCESSOR_CORE,
598 CPU_CORE_FLAGS },
599 { "merom", PROCESSOR_CORE2,
600 CPU_CORE2_FLAGS },
601 { "core2", PROCESSOR_CORE2,
602 CPU_CORE2_FLAGS },
bd5295b2
L		 603 { "corei7", PROCESSOR_COREI7,
604 CPU_COREI7_FLAGS },
6305a203
L		 605 { "k6", PROCESSOR_K6,
606 CPU_K6_FLAGS },
607 { "k6_2", PROCESSOR_K6,
608 CPU_K6_2_FLAGS },
609 { "athlon", PROCESSOR_ATHLON,
610 CPU_ATHLON_FLAGS },
611 { "sledgehammer", PROCESSOR_K8,
612 CPU_K8_FLAGS },
613 { "opteron", PROCESSOR_K8,
614 CPU_K8_FLAGS },
615 { "k8", PROCESSOR_K8,
616 CPU_K8_FLAGS },
617 { "amdfam10", PROCESSOR_AMDFAM10,
618 CPU_AMDFAM10_FLAGS },
619 { ".mmx", PROCESSOR_UNKNOWN,
620 CPU_MMX_FLAGS },
621 { ".sse", PROCESSOR_UNKNOWN,
622 CPU_SSE_FLAGS },
623 { ".sse2", PROCESSOR_UNKNOWN,
624 CPU_SSE2_FLAGS },
625 { ".sse3", PROCESSOR_UNKNOWN,
626 CPU_SSE3_FLAGS },
627 { ".ssse3", PROCESSOR_UNKNOWN,
628 CPU_SSSE3_FLAGS },
629 { ".sse4.1", PROCESSOR_UNKNOWN,
630 CPU_SSE4_1_FLAGS },
631 { ".sse4.2", PROCESSOR_UNKNOWN,
632 CPU_SSE4_2_FLAGS },
633 { ".sse4", PROCESSOR_UNKNOWN,
634 CPU_SSE4_2_FLAGS },
c0f3af97
L		 635 { ".avx", PROCESSOR_UNKNOWN,
636 CPU_AVX_FLAGS },
6305a203
L		 637 { ".vmx", PROCESSOR_UNKNOWN,
638 CPU_VMX_FLAGS },
639 { ".smx", PROCESSOR_UNKNOWN,
640 CPU_SMX_FLAGS },
f03fe4c1
L		 641 { ".xsave", PROCESSOR_UNKNOWN,
642 CPU_XSAVE_FLAGS },
c0f3af97
L		 643 { ".aes", PROCESSOR_UNKNOWN,
644 CPU_AES_FLAGS },
594ab6a3
L		 645 { ".pclmul", PROCESSOR_UNKNOWN,
646 CPU_PCLMUL_FLAGS },
c0f3af97 647 { ".clmul", PROCESSOR_UNKNOWN,
594ab6a3 648 CPU_PCLMUL_FLAGS },
c0f3af97
L		 649 { ".fma", PROCESSOR_UNKNOWN,
650 CPU_FMA_FLAGS },
f1f8f695
L		 651 { ".movbe", PROCESSOR_UNKNOWN,
652 CPU_MOVBE_FLAGS },
653 { ".ept", PROCESSOR_UNKNOWN,
654 CPU_EPT_FLAGS },
bd5295b2
L		 655 { ".clflush", PROCESSOR_UNKNOWN,
656 CPU_CLFLUSH_FLAGS },
657 { ".syscall", PROCESSOR_UNKNOWN,
658 CPU_SYSCALL_FLAGS },
1b7f3fb0
L		 659 { ".rdtscp", PROCESSOR_UNKNOWN,
660 CPU_RDTSCP_FLAGS },
6305a203
L		 661 { ".3dnow", PROCESSOR_UNKNOWN,
662 CPU_3DNOW_FLAGS },
663 { ".3dnowa", PROCESSOR_UNKNOWN,
664 CPU_3DNOWA_FLAGS },
665 { ".padlock", PROCESSOR_UNKNOWN,
666 CPU_PADLOCK_FLAGS },
667 { ".pacifica", PROCESSOR_UNKNOWN,
668 CPU_SVME_FLAGS },
669 { ".svme", PROCESSOR_UNKNOWN,
670 CPU_SVME_FLAGS },
671 { ".sse4a", PROCESSOR_UNKNOWN,
672 CPU_SSE4A_FLAGS },
673 { ".abm", PROCESSOR_UNKNOWN,
674 CPU_ABM_FLAGS },
675 { ".sse5", PROCESSOR_UNKNOWN,
676 CPU_SSE5_FLAGS },
e413e4e9
AM		 677};
678
704209c0 679#ifdef I386COFF
a6c24e68
NC		 680/* Like s_lcomm_internal in gas/read.c but the alignment string
681 is allowed to be optional. */
682
683static symbolS *
684pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
685{
686 addressT align = 0;
687
688 SKIP_WHITESPACE ();
689
690 if (needs_align
691 && *input_line_pointer == ',')
692 {
693 align = parse_align (needs_align - 1);
694
695 if (align == (addressT) -1)
696 return NULL;
697 }
698 else
699 {
700 if (size >= 8)
701 align = 3;
702 else if (size >= 4)
703 align = 2;
704 else if (size >= 2)
705 align = 1;
706 else
707 align = 0;
708 }
709
710 bss_alloc (symbolP, size, align);
711 return symbolP;
712}
713
704209c0 714static void
a6c24e68
NC		 715pe_lcomm (int needs_align)
716{
717 s_comm_internal (needs_align * 2, pe_lcomm_internal);
718}
704209c0 719#endif
a6c24e68 720
29b0f896
AM		 721const pseudo_typeS md_pseudo_table[] =
722{
723#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
724 {"align", s_align_bytes, 0},
725#else
726 {"align", s_align_ptwo, 0},
727#endif
728 {"arch", set_cpu_arch, 0},
729#ifndef I386COFF
730 {"bss", s_bss, 0},
a6c24e68
NC		 731#else
732 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 733#endif
734 {"ffloat", float_cons, 'f'},
735 {"dfloat", float_cons, 'd'},
736 {"tfloat", float_cons, 'x'},
737 {"value", cons, 2},
d182319b 738 {"slong", signed_cons, 4},
29b0f896
AM		 739 {"noopt", s_ignore, 0},
740 {"optim", s_ignore, 0},
741 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
742 {"code16", set_code_flag, CODE_16BIT},
743 {"code32", set_code_flag, CODE_32BIT},
744 {"code64", set_code_flag, CODE_64BIT},
745 {"intel_syntax", set_intel_syntax, 1},
746 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 747 {"intel_mnemonic", set_intel_mnemonic, 1},
748 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 749 {"allow_index_reg", set_allow_index_reg, 1},
750 {"disallow_index_reg", set_allow_index_reg, 0},
cb19c032 751 {"sse_check", set_sse_check, 0},
3b22753a
L		 752#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
753 {"largecomm", handle_large_common, 0},
07a53e5c 754#else
e3bb37b5 755 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 756 {"loc", dwarf2_directive_loc, 0},
757 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 758#endif
6482c264
NC		 759#ifdef TE_PE
760 {"secrel32", pe_directive_secrel, 0},
761#endif
29b0f896
AM		 762 {0, 0, 0}
763};
764
765/* For interface with expression (). */
766extern char *input_line_pointer;
767
768/* Hash table for instruction mnemonic lookup. */
769static struct hash_control *op_hash;
770
771/* Hash table for register lookup. */
772static struct hash_control *reg_hash;
773\f
252b5132 774void
e3bb37b5 775i386_align_code (fragS *fragP, int count)
252b5132 776{
ce8a8b2f
AM		 777 /* Various efficient no-op patterns for aligning code labels.
778 Note: Don't try to assemble the instructions in the comments.
779 0L and 0w are not legal. */
252b5132
RH		 780 static const char f32_1[] =
781 {0x90}; /* nop */
782 static const char f32_2[] =
ccc9c027 783 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 784 static const char f32_3[] =
785 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
786 static const char f32_4[] =
787 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
788 static const char f32_5[] =
789 {0x90, /* nop */
790 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
791 static const char f32_6[] =
792 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
793 static const char f32_7[] =
794 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
795 static const char f32_8[] =
796 {0x90, /* nop */
797 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
798 static const char f32_9[] =
799 {0x89,0xf6, /* movl %esi,%esi */
800 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
801 static const char f32_10[] =
802 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
803 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
804 static const char f32_11[] =
805 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
806 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
807 static const char f32_12[] =
808 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
809 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
810 static const char f32_13[] =
811 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
812 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
813 static const char f32_14[] =
814 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
815 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 816 static const char f16_3[] =
817 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 818 static const char f16_4[] =
819 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
820 static const char f16_5[] =
821 {0x90, /* nop */
822 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
823 static const char f16_6[] =
824 {0x89,0xf6, /* mov %si,%si */
825 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
826 static const char f16_7[] =
827 {0x8d,0x74,0x00, /* lea 0(%si),%si */
828 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
829 static const char f16_8[] =
830 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
831 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 832 static const char jump_31[] =
833 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
834 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
835 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
836 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 837 static const char *const f32_patt[] = {
838 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 839 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 840 };
841 static const char *const f16_patt[] = {
76bc74dc 842 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 843 };
ccc9c027
L		 844 /* nopl (%[re]ax) */
845 static const char alt_3[] =
846 {0x0f,0x1f,0x00};
847 /* nopl 0(%[re]ax) */
848 static const char alt_4[] =
849 {0x0f,0x1f,0x40,0x00};
850 /* nopl 0(%[re]ax,%[re]ax,1) */
851 static const char alt_5[] =
852 {0x0f,0x1f,0x44,0x00,0x00};
853 /* nopw 0(%[re]ax,%[re]ax,1) */
854 static const char alt_6[] =
855 {0x66,0x0f,0x1f,0x44,0x00,0x00};
856 /* nopl 0L(%[re]ax) */
857 static const char alt_7[] =
858 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
859 /* nopl 0L(%[re]ax,%[re]ax,1) */
860 static const char alt_8[] =
861 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
862 /* nopw 0L(%[re]ax,%[re]ax,1) */
863 static const char alt_9[] =
864 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
865 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
866 static const char alt_10[] =
867 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
868 /* data16
869 nopw %cs:0L(%[re]ax,%[re]ax,1) */
870 static const char alt_long_11[] =
871 {0x66,
872 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
873 /* data16
874 data16
875 nopw %cs:0L(%[re]ax,%[re]ax,1) */
876 static const char alt_long_12[] =
877 {0x66,
878 0x66,
879 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
880 /* data16
881 data16
882 data16
883 nopw %cs:0L(%[re]ax,%[re]ax,1) */
884 static const char alt_long_13[] =
885 {0x66,
886 0x66,
887 0x66,
888 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
889 /* data16
890 data16
891 data16
892 data16
893 nopw %cs:0L(%[re]ax,%[re]ax,1) */
894 static const char alt_long_14[] =
895 {0x66,
896 0x66,
897 0x66,
898 0x66,
899 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
900 /* data16
901 data16
902 data16
903 data16
904 data16
905 nopw %cs:0L(%[re]ax,%[re]ax,1) */
906 static const char alt_long_15[] =
907 {0x66,
908 0x66,
909 0x66,
910 0x66,
911 0x66,
912 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
913 /* nopl 0(%[re]ax,%[re]ax,1)
914 nopw 0(%[re]ax,%[re]ax,1) */
915 static const char alt_short_11[] =
916 {0x0f,0x1f,0x44,0x00,0x00,
917 0x66,0x0f,0x1f,0x44,0x00,0x00};
918 /* nopw 0(%[re]ax,%[re]ax,1)
919 nopw 0(%[re]ax,%[re]ax,1) */
920 static const char alt_short_12[] =
921 {0x66,0x0f,0x1f,0x44,0x00,0x00,
922 0x66,0x0f,0x1f,0x44,0x00,0x00};
923 /* nopw 0(%[re]ax,%[re]ax,1)
924 nopl 0L(%[re]ax) */
925 static const char alt_short_13[] =
926 {0x66,0x0f,0x1f,0x44,0x00,0x00,
927 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
928 /* nopl 0L(%[re]ax)
929 nopl 0L(%[re]ax) */
930 static const char alt_short_14[] =
931 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
932 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
933 /* nopl 0L(%[re]ax)
934 nopl 0L(%[re]ax,%[re]ax,1) */
935 static const char alt_short_15[] =
936 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
937 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
938 static const char *const alt_short_patt[] = {
939 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
940 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
941 alt_short_14, alt_short_15
942 };
943 static const char *const alt_long_patt[] = {
944 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
945 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
946 alt_long_14, alt_long_15
947 };
252b5132 948
76bc74dc
L		 949 /* Only align for at least a positive non-zero boundary. */
950 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 951 return;
3e73aa7c 952
ccc9c027
L		 953 /* We need to decide which NOP sequence to use for 32bit and
954 64bit. When -mtune= is used:
4eed87de 955
76bc74dc
L		 956 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
957 PROCESSOR_GENERIC32, f32_patt will be used.
958 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 959 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
960 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc
L		 961 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
962 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 963
76bc74dc
L		 964 When -mtune= isn't used, alt_long_patt will be used if
965 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
966 be used.
ccc9c027
L		 967
968 When -march= or .arch is used, we can't use anything beyond
969 cpu_arch_isa_flags. */
970
971 if (flag_code == CODE_16BIT)
972 {
ccc9c027 973 if (count > 8)
33fef721 974 {
76bc74dc
L		 975 memcpy (fragP->fr_literal + fragP->fr_fix,
976 jump_31, count);
977 /* Adjust jump offset. */
978 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 979 }
76bc74dc
L		 980 else
981 memcpy (fragP->fr_literal + fragP->fr_fix,
982 f16_patt[count - 1], count);
252b5132 983 }
33fef721 984 else
ccc9c027
L		 985 {
986 const char *const *patt = NULL;
987
fbf3f584 988 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 989 {
990 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
991 switch (cpu_arch_tune)
992 {
993 case PROCESSOR_UNKNOWN:
994 /* We use cpu_arch_isa_flags to check if we SHOULD
995 optimize for Cpu686. */
fbf3f584 996 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
76bc74dc 997 patt = alt_long_patt;
ccc9c027
L		 998 else
999 patt = f32_patt;
1000 break;
ccc9c027
L		 1001 case PROCESSOR_PENTIUMPRO:
1002 case PROCESSOR_PENTIUM4:
1003 case PROCESSOR_NOCONA:
ef05d495 1004 case PROCESSOR_CORE:
76bc74dc 1005 case PROCESSOR_CORE2:
bd5295b2 1006 case PROCESSOR_COREI7:
76bc74dc
L		 1007 case PROCESSOR_GENERIC64:
1008 patt = alt_long_patt;
1009 break;
ccc9c027
L		 1010 case PROCESSOR_K6:
1011 case PROCESSOR_ATHLON:
1012 case PROCESSOR_K8:
4eed87de 1013 case PROCESSOR_AMDFAM10:
ccc9c027
L		 1014 patt = alt_short_patt;
1015 break;
76bc74dc 1016 case PROCESSOR_I386:
ccc9c027
L		 1017 case PROCESSOR_I486:
1018 case PROCESSOR_PENTIUM:
1019 case PROCESSOR_GENERIC32:
1020 patt = f32_patt;
1021 break;
4eed87de 1022 }
ccc9c027
L		 1023 }
1024 else
1025 {
fbf3f584 1026 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1027 {
1028 case PROCESSOR_UNKNOWN:
e6a14101 1029 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1030 PROCESSOR_UNKNOWN. */
1031 abort ();
1032 break;
1033
76bc74dc 1034 case PROCESSOR_I386:
ccc9c027
L		 1035 case PROCESSOR_I486:
1036 case PROCESSOR_PENTIUM:
ccc9c027
L		 1037 case PROCESSOR_K6:
1038 case PROCESSOR_ATHLON:
1039 case PROCESSOR_K8:
4eed87de 1040 case PROCESSOR_AMDFAM10:
ccc9c027
L		 1041 case PROCESSOR_GENERIC32:
1042 /* We use cpu_arch_isa_flags to check if we CAN optimize
1043 for Cpu686. */
fbf3f584 1044 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1045 patt = alt_short_patt;
1046 else
1047 patt = f32_patt;
1048 break;
76bc74dc
L		 1049 case PROCESSOR_PENTIUMPRO:
1050 case PROCESSOR_PENTIUM4:
1051 case PROCESSOR_NOCONA:
1052 case PROCESSOR_CORE:
ef05d495 1053 case PROCESSOR_CORE2:
bd5295b2 1054 case PROCESSOR_COREI7:
fbf3f584 1055 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1056 patt = alt_long_patt;
1057 else
1058 patt = f32_patt;
1059 break;
1060 case PROCESSOR_GENERIC64:
76bc74dc 1061 patt = alt_long_patt;
ccc9c027 1062 break;
4eed87de 1063 }
ccc9c027
L		 1064 }
1065
76bc74dc
L		 1066 if (patt == f32_patt)
1067 {
1068 /* If the padding is less than 15 bytes, we use the normal
1069 ones. Otherwise, we use a jump instruction and adjust
1070 its offset. */
1071 if (count < 15)
1072 memcpy (fragP->fr_literal + fragP->fr_fix,
1073 patt[count - 1], count);
1074 else
1075 {
1076 memcpy (fragP->fr_literal + fragP->fr_fix,
1077 jump_31, count);
1078 /* Adjust jump offset. */
1079 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1080 }
1081 }
1082 else
1083 {
1084 /* Maximum length of an instruction is 15 byte. If the
1085 padding is greater than 15 bytes and we don't use jump,
1086 we have to break it into smaller pieces. */
1087 int padding = count;
1088 while (padding > 15)
1089 {
1090 padding -= 15;
1091 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1092 patt [14], 15);
1093 }
1094
1095 if (padding)
1096 memcpy (fragP->fr_literal + fragP->fr_fix,
1097 patt [padding - 1], padding);
1098 }
ccc9c027 1099 }
33fef721 1100 fragP->fr_var = count;
252b5132
RH		 1101}
1102
c6fb90c8 1103static INLINE int
0dfbf9d7 1104operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1105{
0dfbf9d7 1106 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1107 {
1108 case 3:
0dfbf9d7 1109 if (x->array[2])
c6fb90c8
L		 1110 return 0;
1111 case 2:
0dfbf9d7 1112 if (x->array[1])
c6fb90c8
L		 1113 return 0;
1114 case 1:
0dfbf9d7 1115 return !x->array[0];
c6fb90c8
L		 1116 default:
1117 abort ();
1118 }
40fb9820
L		 1119}
1120
c6fb90c8 1121static INLINE void
0dfbf9d7 1122operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1123{
0dfbf9d7 1124 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1125 {
1126 case 3:
0dfbf9d7 1127 x->array[2] = v;
c6fb90c8 1128 case 2:
0dfbf9d7 1129 x->array[1] = v;
c6fb90c8 1130 case 1:
0dfbf9d7 1131 x->array[0] = v;
c6fb90c8
L		 1132 break;
1133 default:
1134 abort ();
1135 }
1136}
40fb9820 1137
c6fb90c8 1138static INLINE int
0dfbf9d7
L		 1139operand_type_equal (const union i386_operand_type *x,
1140 const union i386_operand_type *y)
c6fb90c8 1141{
0dfbf9d7 1142 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1143 {
1144 case 3:
0dfbf9d7 1145 if (x->array[2] != y->array[2])
c6fb90c8
L		 1146 return 0;
1147 case 2:
0dfbf9d7 1148 if (x->array[1] != y->array[1])
c6fb90c8
L		 1149 return 0;
1150 case 1:
0dfbf9d7 1151 return x->array[0] == y->array[0];
c6fb90c8
L		 1152 break;
1153 default:
1154 abort ();
1155 }
1156}
40fb9820 1157
0dfbf9d7
L		 1158static INLINE int
1159cpu_flags_all_zero (const union i386_cpu_flags *x)
1160{
1161 switch (ARRAY_SIZE(x->array))
1162 {
1163 case 3:
1164 if (x->array[2])
1165 return 0;
1166 case 2:
1167 if (x->array[1])
1168 return 0;
1169 case 1:
1170 return !x->array[0];
1171 default:
1172 abort ();
1173 }
1174}
1175
1176static INLINE void
1177cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1178{
1179 switch (ARRAY_SIZE(x->array))
1180 {
1181 case 3:
1182 x->array[2] = v;
1183 case 2:
1184 x->array[1] = v;
1185 case 1:
1186 x->array[0] = v;
1187 break;
1188 default:
1189 abort ();
1190 }
1191}
1192
1193static INLINE int
1194cpu_flags_equal (const union i386_cpu_flags *x,
1195 const union i386_cpu_flags *y)
1196{
1197 switch (ARRAY_SIZE(x->array))
1198 {
1199 case 3:
1200 if (x->array[2] != y->array[2])
1201 return 0;
1202 case 2:
1203 if (x->array[1] != y->array[1])
1204 return 0;
1205 case 1:
1206 return x->array[0] == y->array[0];
1207 break;
1208 default:
1209 abort ();
1210 }
1211}
c6fb90c8
L		 1212
1213static INLINE int
1214cpu_flags_check_cpu64 (i386_cpu_flags f)
1215{
1216 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1217 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1218}
1219
c6fb90c8
L		 1220static INLINE i386_cpu_flags
1221cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1222{
c6fb90c8
L		 1223 switch (ARRAY_SIZE (x.array))
1224 {
1225 case 3:
1226 x.array [2] &= y.array [2];
1227 case 2:
1228 x.array [1] &= y.array [1];
1229 case 1:
1230 x.array [0] &= y.array [0];
1231 break;
1232 default:
1233 abort ();
1234 }
1235 return x;
1236}
40fb9820 1237
c6fb90c8
L		 1238static INLINE i386_cpu_flags
1239cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1240{
c6fb90c8 1241 switch (ARRAY_SIZE (x.array))
40fb9820 1242 {
c6fb90c8
L		 1243 case 3:
1244 x.array [2] |= y.array [2];
1245 case 2:
1246 x.array [1] |= y.array [1];
1247 case 1:
1248 x.array [0] |= y.array [0];
40fb9820
L		 1249 break;
1250 default:
1251 abort ();
1252 }
40fb9820
L		 1253 return x;
1254}
1255
c0f3af97
L		 1256#define CPU_FLAGS_ARCH_MATCH 0x1
1257#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1258#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1259#define CPU_FLAGS_PCLMUL_MATCH 0x8
1260#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1261
a5ff0eb2 1262#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1263 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1264 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1265#define CPU_FLAGS_PERFECT_MATCH \
1266 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1267
1268/* Return CPU flags match bits. */
3629bb00 1269
40fb9820 1270static int
c0f3af97 1271cpu_flags_match (const template *t)
40fb9820 1272{
c0f3af97
L		 1273 i386_cpu_flags x = t->cpu_flags;
1274 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1275
1276 x.bitfield.cpu64 = 0;
1277 x.bitfield.cpuno64 = 0;
1278
0dfbf9d7 1279 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1280 {
1281 /* This instruction is available on all archs. */
1282 match |= CPU_FLAGS_32BIT_MATCH;
1283 }
3629bb00
L		 1284 else
1285 {
c0f3af97 1286 /* This instruction is available only on some archs. */
3629bb00
L		 1287 i386_cpu_flags cpu = cpu_arch_flags;
1288
1289 cpu.bitfield.cpu64 = 0;
1290 cpu.bitfield.cpuno64 = 0;
1291 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1292 if (!cpu_flags_all_zero (&cpu))
1293 {
a5ff0eb2
L		 1294 if (x.bitfield.cpuavx)
1295 {
ce2f5b3c 1296 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1297 if (cpu.bitfield.cpuavx)
1298 {
1299 /* Check SSE2AVX. */
1300 if (!t->opcode_modifier.sse2avx|| sse2avx)
1301 {
1302 match |= (CPU_FLAGS_ARCH_MATCH
1303 | CPU_FLAGS_AVX_MATCH);
1304 /* Check AES. */
1305 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1306 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1307 /* Check PCLMUL. */
1308 if (!x.bitfield.cpupclmul
1309 || cpu.bitfield.cpupclmul)
1310 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1311 }
1312 }
1313 else
1314 match |= CPU_FLAGS_ARCH_MATCH;
1315 }
1316 else
c0f3af97
L		 1317 match |= CPU_FLAGS_32BIT_MATCH;
1318 }
3629bb00 1319 }
c0f3af97 1320 return match;
40fb9820
L		 1321}
1322
c6fb90c8
L		 1323static INLINE i386_operand_type
1324operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1325{
c6fb90c8
L		 1326 switch (ARRAY_SIZE (x.array))
1327 {
1328 case 3:
1329 x.array [2] &= y.array [2];
1330 case 2:
1331 x.array [1] &= y.array [1];
1332 case 1:
1333 x.array [0] &= y.array [0];
1334 break;
1335 default:
1336 abort ();
1337 }
1338 return x;
40fb9820
L		 1339}
1340
c6fb90c8
L		 1341static INLINE i386_operand_type
1342operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1343{
c6fb90c8 1344 switch (ARRAY_SIZE (x.array))
40fb9820 1345 {
c6fb90c8
L		 1346 case 3:
1347 x.array [2] |= y.array [2];
1348 case 2:
1349 x.array [1] |= y.array [1];
1350 case 1:
1351 x.array [0] |= y.array [0];
40fb9820
L		 1352 break;
1353 default:
1354 abort ();
1355 }
c6fb90c8
L		 1356 return x;
1357}
40fb9820 1358
c6fb90c8
L		 1359static INLINE i386_operand_type
1360operand_type_xor (i386_operand_type x, i386_operand_type y)
1361{
1362 switch (ARRAY_SIZE (x.array))
1363 {
1364 case 3:
1365 x.array [2] ^= y.array [2];
1366 case 2:
1367 x.array [1] ^= y.array [1];
1368 case 1:
1369 x.array [0] ^= y.array [0];
1370 break;
1371 default:
1372 abort ();
1373 }
40fb9820
L		 1374 return x;
1375}
1376
1377static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1378static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1379static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1380static const i386_operand_type inoutportreg
1381 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1382static const i386_operand_type reg16_inoutportreg
1383 = OPERAND_TYPE_REG16_INOUTPORTREG;
1384static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1385static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1386static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1387static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1388static const i386_operand_type anydisp
1389 = OPERAND_TYPE_ANYDISP;
40fb9820 1390static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1391static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1392static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1393static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1394static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1395static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1396static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1397static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1398static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1399static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1400static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1401
1402enum operand_type
1403{
1404 reg,
40fb9820
L		 1405 imm,
1406 disp,
1407 anymem
1408};
1409
c6fb90c8 1410static INLINE int
40fb9820
L		 1411operand_type_check (i386_operand_type t, enum operand_type c)
1412{
1413 switch (c)
1414 {
1415 case reg:
1416 return (t.bitfield.reg8
1417 || t.bitfield.reg16
1418 || t.bitfield.reg32
1419 || t.bitfield.reg64);
1420
40fb9820
L		 1421 case imm:
1422 return (t.bitfield.imm8
1423 || t.bitfield.imm8s
1424 || t.bitfield.imm16
1425 || t.bitfield.imm32
1426 || t.bitfield.imm32s
1427 || t.bitfield.imm64);
1428
1429 case disp:
1430 return (t.bitfield.disp8
1431 || t.bitfield.disp16
1432 || t.bitfield.disp32
1433 || t.bitfield.disp32s
1434 || t.bitfield.disp64);
1435
1436 case anymem:
1437 return (t.bitfield.disp8
1438 || t.bitfield.disp16
1439 || t.bitfield.disp32
1440 || t.bitfield.disp32s
1441 || t.bitfield.disp64
1442 || t.bitfield.baseindex);
1443
1444 default:
1445 abort ();
1446 }
2cfe26b6
AM		 1447
1448 return 0;
40fb9820
L		 1449}
1450
5c07affc
L		 1451/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1452 operand J for instruction template T. */
1453
1454static INLINE int
1455match_reg_size (const template *t, unsigned int j)
1456{
1457 return !((i.types[j].bitfield.byte
1458 && !t->operand_types[j].bitfield.byte)
1459 || (i.types[j].bitfield.word
1460 && !t->operand_types[j].bitfield.word)
1461 || (i.types[j].bitfield.dword
1462 && !t->operand_types[j].bitfield.dword)
1463 || (i.types[j].bitfield.qword
1464 && !t->operand_types[j].bitfield.qword));
1465}
1466
1467/* Return 1 if there is no conflict in any size on operand J for
1468 instruction template T. */
1469
1470static INLINE int
1471match_mem_size (const template *t, unsigned int j)
1472{
1473 return (match_reg_size (t, j)
1474 && !((i.types[j].bitfield.unspecified
1475 && !t->operand_types[j].bitfield.unspecified)
1476 || (i.types[j].bitfield.fword
1477 && !t->operand_types[j].bitfield.fword)
1478 || (i.types[j].bitfield.tbyte
1479 && !t->operand_types[j].bitfield.tbyte)
1480 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1481 && !t->operand_types[j].bitfield.xmmword)
1482 || (i.types[j].bitfield.ymmword
1483 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1484}
1485
1486/* Return 1 if there is no size conflict on any operands for
1487 instruction template T. */
1488
1489static INLINE int
1490operand_size_match (const template *t)
1491{
1492 unsigned int j;
1493 int match = 1;
1494
1495 /* Don't check jump instructions. */
1496 if (t->opcode_modifier.jump
1497 || t->opcode_modifier.jumpbyte
1498 || t->opcode_modifier.jumpdword
1499 || t->opcode_modifier.jumpintersegment)
1500 return match;
1501
1502 /* Check memory and accumulator operand size. */
1503 for (j = 0; j < i.operands; j++)
1504 {
1505 if (t->operand_types[j].bitfield.anysize)
1506 continue;
1507
1508 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1509 {
1510 match = 0;
1511 break;
1512 }
1513
1514 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1515 {
1516 match = 0;
1517 break;
1518 }
1519 }
1520
1521 if (match
1522 || (!t->opcode_modifier.d && !t->opcode_modifier.floatd))
1523 return match;
1524
1525 /* Check reverse. */
1526 assert (i.operands == 2);
1527
1528 match = 1;
1529 for (j = 0; j < 2; j++)
1530 {
1531 if (t->operand_types[j].bitfield.acc
1532 && !match_reg_size (t, j ? 0 : 1))
1533 {
1534 match = 0;
1535 break;
1536 }
1537
1538 if (i.types[j].bitfield.mem
1539 && !match_mem_size (t, j ? 0 : 1))
1540 {
1541 match = 0;
1542 break;
1543 }
1544 }
1545
1546 return match;
1547}
1548
c6fb90c8 1549static INLINE int
40fb9820
L		 1550operand_type_match (i386_operand_type overlap,
1551 i386_operand_type given)
1552{
1553 i386_operand_type temp = overlap;
1554
1555 temp.bitfield.jumpabsolute = 0;
7d5e4556 1556 temp.bitfield.unspecified = 0;
5c07affc
L		 1557 temp.bitfield.byte = 0;
1558 temp.bitfield.word = 0;
1559 temp.bitfield.dword = 0;
1560 temp.bitfield.fword = 0;
1561 temp.bitfield.qword = 0;
1562 temp.bitfield.tbyte = 0;
1563 temp.bitfield.xmmword = 0;
c0f3af97 1564 temp.bitfield.ymmword = 0;
0dfbf9d7 1565 if (operand_type_all_zero (&temp))
40fb9820
L		 1566 return 0;
1567
1568 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1569 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1570}
1571
7d5e4556 1572/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1573 unless the expected operand type register overlap is null.
1574 Note that Acc in a template matches every size of reg. */
1575
c6fb90c8 1576static INLINE int
40fb9820
L		 1577operand_type_register_match (i386_operand_type m0,
1578 i386_operand_type g0,
1579 i386_operand_type t0,
1580 i386_operand_type m1,
1581 i386_operand_type g1,
1582 i386_operand_type t1)
1583{
1584 if (!operand_type_check (g0, reg))
1585 return 1;
1586
1587 if (!operand_type_check (g1, reg))
1588 return 1;
1589
1590 if (g0.bitfield.reg8 == g1.bitfield.reg8
1591 && g0.bitfield.reg16 == g1.bitfield.reg16
1592 && g0.bitfield.reg32 == g1.bitfield.reg32
1593 && g0.bitfield.reg64 == g1.bitfield.reg64)
1594 return 1;
1595
1596 if (m0.bitfield.acc)
1597 {
1598 t0.bitfield.reg8 = 1;
1599 t0.bitfield.reg16 = 1;
1600 t0.bitfield.reg32 = 1;
1601 t0.bitfield.reg64 = 1;
1602 }
1603
1604 if (m1.bitfield.acc)
1605 {
1606 t1.bitfield.reg8 = 1;
1607 t1.bitfield.reg16 = 1;
1608 t1.bitfield.reg32 = 1;
1609 t1.bitfield.reg64 = 1;
1610 }
1611
1612 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1613 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1614 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1615 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1616}
1617
252b5132 1618static INLINE unsigned int
40fb9820 1619mode_from_disp_size (i386_operand_type t)
252b5132 1620{
40fb9820
L		 1621 if (t.bitfield.disp8)
1622 return 1;
1623 else if (t.bitfield.disp16
1624 || t.bitfield.disp32
1625 || t.bitfield.disp32s)
1626 return 2;
1627 else
1628 return 0;
252b5132
RH		 1629}
1630
1631static INLINE int
e3bb37b5 1632fits_in_signed_byte (offsetT num)
252b5132
RH		 1633{
1634 return (num >= -128) && (num <= 127);
47926f60 1635}
252b5132
RH		 1636
1637static INLINE int
e3bb37b5 1638fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1639{
1640 return (num & 0xff) == num;
47926f60 1641}
252b5132
RH		 1642
1643static INLINE int
e3bb37b5 1644fits_in_unsigned_word (offsetT num)
252b5132
RH		 1645{
1646 return (num & 0xffff) == num;
47926f60 1647}
252b5132
RH		 1648
1649static INLINE int
e3bb37b5 1650fits_in_signed_word (offsetT num)
252b5132
RH		 1651{
1652 return (-32768 <= num) && (num <= 32767);
47926f60 1653}
2a962e6d 1654
3e73aa7c 1655static INLINE int
e3bb37b5 1656fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1657{
1658#ifndef BFD64
1659 return 1;
1660#else
1661 return (!(((offsetT) -1 << 31) & num)
1662 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1663#endif
1664} /* fits_in_signed_long() */
2a962e6d 1665
3e73aa7c 1666static INLINE int
e3bb37b5 1667fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1668{
1669#ifndef BFD64
1670 return 1;
1671#else
1672 return (num & (((offsetT) 2 << 31) - 1)) == num;
1673#endif
1674} /* fits_in_unsigned_long() */
252b5132 1675
40fb9820 1676static i386_operand_type
e3bb37b5 1677smallest_imm_type (offsetT num)
252b5132 1678{
40fb9820
L		 1679 i386_operand_type t;
1680
0dfbf9d7 1681 operand_type_set (&t, 0);
40fb9820
L		 1682 t.bitfield.imm64 = 1;
1683
1684 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1685 {
1686 /* This code is disabled on the 486 because all the Imm1 forms
1687 in the opcode table are slower on the i486. They're the
1688 versions with the implicitly specified single-position
1689 displacement, which has another syntax if you really want to
1690 use that form. */
40fb9820
L		 1691 t.bitfield.imm1 = 1;
1692 t.bitfield.imm8 = 1;
1693 t.bitfield.imm8s = 1;
1694 t.bitfield.imm16 = 1;
1695 t.bitfield.imm32 = 1;
1696 t.bitfield.imm32s = 1;
1697 }
1698 else if (fits_in_signed_byte (num))
1699 {
1700 t.bitfield.imm8 = 1;
1701 t.bitfield.imm8s = 1;
1702 t.bitfield.imm16 = 1;
1703 t.bitfield.imm32 = 1;
1704 t.bitfield.imm32s = 1;
1705 }
1706 else if (fits_in_unsigned_byte (num))
1707 {
1708 t.bitfield.imm8 = 1;
1709 t.bitfield.imm16 = 1;
1710 t.bitfield.imm32 = 1;
1711 t.bitfield.imm32s = 1;
1712 }
1713 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1714 {
1715 t.bitfield.imm16 = 1;
1716 t.bitfield.imm32 = 1;
1717 t.bitfield.imm32s = 1;
1718 }
1719 else if (fits_in_signed_long (num))
1720 {
1721 t.bitfield.imm32 = 1;
1722 t.bitfield.imm32s = 1;
1723 }
1724 else if (fits_in_unsigned_long (num))
1725 t.bitfield.imm32 = 1;
1726
1727 return t;
47926f60 1728}
252b5132 1729
847f7ad4 1730static offsetT
e3bb37b5 1731offset_in_range (offsetT val, int size)
847f7ad4 1732{
508866be 1733 addressT mask;
ba2adb93 1734
847f7ad4
AM		 1735 switch (size)
1736 {
508866be
L		 1737 case 1: mask = ((addressT) 1 << 8) - 1; break;
1738 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1739 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1740#ifdef BFD64
1741 case 8: mask = ((addressT) 2 << 63) - 1; break;
1742#endif
47926f60 1743 default: abort ();
847f7ad4
AM		 1744 }
1745
ba2adb93 1746 /* If BFD64, sign extend val. */
3e73aa7c
JH		 1747 if (!use_rela_relocations)
1748 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1749 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 1750
47926f60 1751 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1752 {
1753 char buf1[40], buf2[40];
1754
1755 sprint_value (buf1, val);
1756 sprint_value (buf2, val & mask);
1757 as_warn (_("%s shortened to %s"), buf1, buf2);
1758 }
1759 return val & mask;
1760}
1761
252b5132
RH		 1762/* Returns 0 if attempting to add a prefix where one from the same
1763 class already exists, 1 if non rep/repne added, 2 if rep/repne
1764 added. */
1765static int
e3bb37b5 1766add_prefix (unsigned int prefix)
252b5132
RH		 1767{
1768 int ret = 1;
b1905489 1769 unsigned int q;
252b5132 1770
29b0f896
AM		 1771 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1772 && flag_code == CODE_64BIT)
b1905489 1773 {
161a04f6
L		 1774 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1775 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1776 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 1777 ret = 0;
1778 q = REX_PREFIX;
1779 }
3e73aa7c 1780 else
b1905489
JB		 1781 {
1782 switch (prefix)
1783 {
1784 default:
1785 abort ();
1786
1787 case CS_PREFIX_OPCODE:
1788 case DS_PREFIX_OPCODE:
1789 case ES_PREFIX_OPCODE:
1790 case FS_PREFIX_OPCODE:
1791 case GS_PREFIX_OPCODE:
1792 case SS_PREFIX_OPCODE:
1793 q = SEG_PREFIX;
1794 break;
1795
1796 case REPNE_PREFIX_OPCODE:
1797 case REPE_PREFIX_OPCODE:
1798 ret = 2;
1799 /* fall thru */
1800 case LOCK_PREFIX_OPCODE:
1801 q = LOCKREP_PREFIX;
1802 break;
1803
1804 case FWAIT_OPCODE:
1805 q = WAIT_PREFIX;
1806 break;
1807
1808 case ADDR_PREFIX_OPCODE:
1809 q = ADDR_PREFIX;
1810 break;
1811
1812 case DATA_PREFIX_OPCODE:
1813 q = DATA_PREFIX;
1814 break;
1815 }
1816 if (i.prefix[q] != 0)
1817 ret = 0;
1818 }
252b5132 1819
b1905489 1820 if (ret)
252b5132 1821 {
b1905489
JB		 1822 if (!i.prefix[q])
1823 ++i.prefixes;
1824 i.prefix[q] |= prefix;
252b5132 1825 }
b1905489
JB		 1826 else
1827 as_bad (_("same type of prefix used twice"));
252b5132 1828
252b5132
RH		 1829 return ret;
1830}
1831
1832static void
e3bb37b5 1833set_code_flag (int value)
eecb386c 1834{
3e73aa7c 1835 flag_code = value;
40fb9820
L		 1836 if (flag_code == CODE_64BIT)
1837 {
1838 cpu_arch_flags.bitfield.cpu64 = 1;
1839 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1840 }
1841 else
1842 {
1843 cpu_arch_flags.bitfield.cpu64 = 0;
1844 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1845 }
1846 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1847 {
1848 as_bad (_("64bit mode not supported on this CPU."));
1849 }
40fb9820 1850 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1851 {
1852 as_bad (_("32bit mode not supported on this CPU."));
1853 }
eecb386c
AM		 1854 stackop_size = '\0';
1855}
1856
1857static void
e3bb37b5 1858set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1859{
3e73aa7c 1860 flag_code = new_code_flag;
40fb9820
L		 1861 if (flag_code != CODE_16BIT)
1862 abort ();
1863 cpu_arch_flags.bitfield.cpu64 = 0;
1864 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 1865 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1866}
1867
1868static void
e3bb37b5 1869set_intel_syntax (int syntax_flag)
252b5132
RH		 1870{
1871 /* Find out if register prefixing is specified. */
1872 int ask_naked_reg = 0;
1873
1874 SKIP_WHITESPACE ();
29b0f896 1875 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1876 {
1877 char *string = input_line_pointer;
1878 int e = get_symbol_end ();
1879
47926f60 1880 if (strcmp (string, "prefix") == 0)
252b5132 1881 ask_naked_reg = 1;
47926f60 1882 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1883 ask_naked_reg = -1;
1884 else
d0b47220 1885 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1886 *input_line_pointer = e;
1887 }
1888 demand_empty_rest_of_line ();
c3332e24 1889
252b5132
RH		 1890 intel_syntax = syntax_flag;
1891
1892 if (ask_naked_reg == 0)
f86103b7
AM		 1893 allow_naked_reg = (intel_syntax
1894 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1895 else
1896 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1897
e4a3b5a4 1898 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1899 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1900 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1901}
1902
1efbbeb4
L		 1903static void
1904set_intel_mnemonic (int mnemonic_flag)
1905{
e1d4d893 1906 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 1907}
1908
db51cc60
L		 1909static void
1910set_allow_index_reg (int flag)
1911{
1912 allow_index_reg = flag;
1913}
1914
cb19c032
L		 1915static void
1916set_sse_check (int dummy ATTRIBUTE_UNUSED)
1917{
1918 SKIP_WHITESPACE ();
1919
1920 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1921 {
1922 char *string = input_line_pointer;
1923 int e = get_symbol_end ();
1924
1925 if (strcmp (string, "none") == 0)
1926 sse_check = sse_check_none;
1927 else if (strcmp (string, "warning") == 0)
1928 sse_check = sse_check_warning;
1929 else if (strcmp (string, "error") == 0)
1930 sse_check = sse_check_error;
1931 else
1932 as_bad (_("bad argument to sse_check directive."));
1933 *input_line_pointer = e;
1934 }
1935 else
1936 as_bad (_("missing argument for sse_check directive"));
1937
1938 demand_empty_rest_of_line ();
1939}
1940
e413e4e9 1941static void
e3bb37b5 1942set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1943{
47926f60 1944 SKIP_WHITESPACE ();
e413e4e9 1945
29b0f896 1946 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1947 {
1948 char *string = input_line_pointer;
1949 int e = get_symbol_end ();
9103f4f4 1950 unsigned int i;
40fb9820 1951 i386_cpu_flags flags;
e413e4e9 1952
9103f4f4 1953 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1954 {
1955 if (strcmp (string, cpu_arch[i].name) == 0)
1956 {
5c6af06e
JB		 1957 if (*string != '.')
1958 {
1959 cpu_arch_name = cpu_arch[i].name;
1960 cpu_sub_arch_name = NULL;
40fb9820
L		 1961 cpu_arch_flags = cpu_arch[i].flags;
1962 if (flag_code == CODE_64BIT)
1963 {
1964 cpu_arch_flags.bitfield.cpu64 = 1;
1965 cpu_arch_flags.bitfield.cpuno64 = 0;
1966 }
1967 else
1968 {
1969 cpu_arch_flags.bitfield.cpu64 = 0;
1970 cpu_arch_flags.bitfield.cpuno64 = 1;
1971 }
ccc9c027 1972 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1973 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1974 if (!cpu_arch_tune_set)
1975 {
1976 cpu_arch_tune = cpu_arch_isa;
1977 cpu_arch_tune_flags = cpu_arch_isa_flags;
1978 }
5c6af06e
JB		 1979 break;
1980 }
40fb9820 1981
c6fb90c8
L		 1982 flags = cpu_flags_or (cpu_arch_flags,
1983 cpu_arch[i].flags);
0dfbf9d7 1984 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 1985 {
6305a203
L		 1986 if (cpu_sub_arch_name)
1987 {
1988 char *name = cpu_sub_arch_name;
1989 cpu_sub_arch_name = concat (name,
1990 cpu_arch[i].name,
1bf57e9f 1991 (const char *) NULL);
6305a203
L		 1992 free (name);
1993 }
1994 else
1995 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
40fb9820 1996 cpu_arch_flags = flags;
5c6af06e
JB		 1997 }
1998 *input_line_pointer = e;
1999 demand_empty_rest_of_line ();
2000 return;
e413e4e9
AM		 2001 }
2002 }
9103f4f4 2003 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2004 as_bad (_("no such architecture: `%s'"), string);
2005
2006 *input_line_pointer = e;
2007 }
2008 else
2009 as_bad (_("missing cpu architecture"));
2010
fddf5b5b
AM		 2011 no_cond_jump_promotion = 0;
2012 if (*input_line_pointer == ','
29b0f896 2013 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2014 {
2015 char *string = ++input_line_pointer;
2016 int e = get_symbol_end ();
2017
2018 if (strcmp (string, "nojumps") == 0)
2019 no_cond_jump_promotion = 1;
2020 else if (strcmp (string, "jumps") == 0)
2021 ;
2022 else
2023 as_bad (_("no such architecture modifier: `%s'"), string);
2024
2025 *input_line_pointer = e;
2026 }
2027
e413e4e9
AM		 2028 demand_empty_rest_of_line ();
2029}
2030
b9d79e03
JH		 2031unsigned long
2032i386_mach ()
2033{
2034 if (!strcmp (default_arch, "x86_64"))
2035 return bfd_mach_x86_64;
2036 else if (!strcmp (default_arch, "i386"))
2037 return bfd_mach_i386_i386;
2038 else
2039 as_fatal (_("Unknown architecture"));
2040}
b9d79e03 2041\f
252b5132
RH		 2042void
2043md_begin ()
2044{
2045 const char *hash_err;
2046
47926f60 2047 /* Initialize op_hash hash table. */
252b5132
RH		 2048 op_hash = hash_new ();
2049
2050 {
29b0f896
AM		 2051 const template *optab;
2052 templates *core_optab;
252b5132 2053
47926f60
KH		 2054 /* Setup for loop. */
2055 optab = i386_optab;
252b5132
RH		 2056 core_optab = (templates *) xmalloc (sizeof (templates));
2057 core_optab->start = optab;
2058
2059 while (1)
2060 {
2061 ++optab;
2062 if (optab->name == NULL
2063 || strcmp (optab->name, (optab - 1)->name) != 0)
2064 {
2065 /* different name --> ship out current template list;
47926f60 2066 add to hash table; & begin anew. */
252b5132
RH		 2067 core_optab->end = optab;
2068 hash_err = hash_insert (op_hash,
2069 (optab - 1)->name,
5a49b8ac 2070 (void *) core_optab);
252b5132
RH		 2071 if (hash_err)
2072 {
252b5132
RH		 2073 as_fatal (_("Internal Error: Can't hash %s: %s"),
2074 (optab - 1)->name,
2075 hash_err);
2076 }
2077 if (optab->name == NULL)
2078 break;
2079 core_optab = (templates *) xmalloc (sizeof (templates));
2080 core_optab->start = optab;
2081 }
2082 }
2083 }
2084
47926f60 2085 /* Initialize reg_hash hash table. */
252b5132
RH		 2086 reg_hash = hash_new ();
2087 {
29b0f896 2088 const reg_entry *regtab;
c3fe08fa 2089 unsigned int regtab_size = i386_regtab_size;
252b5132 2090
c3fe08fa 2091 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2092 {
5a49b8ac 2093 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2094 if (hash_err)
3e73aa7c
JH		 2095 as_fatal (_("Internal Error: Can't hash %s: %s"),
2096 regtab->reg_name,
2097 hash_err);
252b5132
RH		 2098 }
2099 }
2100
47926f60 2101 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2102 {
29b0f896
AM		 2103 int c;
2104 char *p;
252b5132
RH		 2105
2106 for (c = 0; c < 256; c++)
2107 {
3882b010 2108 if (ISDIGIT (c))
252b5132
RH		 2109 {
2110 digit_chars[c] = c;
2111 mnemonic_chars[c] = c;
2112 register_chars[c] = c;
2113 operand_chars[c] = c;
2114 }
3882b010 2115 else if (ISLOWER (c))
252b5132
RH		 2116 {
2117 mnemonic_chars[c] = c;
2118 register_chars[c] = c;
2119 operand_chars[c] = c;
2120 }
3882b010 2121 else if (ISUPPER (c))
252b5132 2122 {
3882b010 2123 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2124 register_chars[c] = mnemonic_chars[c];
2125 operand_chars[c] = c;
2126 }
2127
3882b010 2128 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2129 identifier_chars[c] = c;
2130 else if (c >= 128)
2131 {
2132 identifier_chars[c] = c;
2133 operand_chars[c] = c;
2134 }
2135 }
2136
2137#ifdef LEX_AT
2138 identifier_chars['@'] = '@';
32137342
NC		 2139#endif
2140#ifdef LEX_QM
2141 identifier_chars['?'] = '?';
2142 operand_chars['?'] = '?';
252b5132 2143#endif
252b5132 2144 digit_chars['-'] = '-';
c0f3af97 2145 mnemonic_chars['_'] = '_';
791fe849 2146 mnemonic_chars['-'] = '-';
0003779b 2147 mnemonic_chars['.'] = '.';
252b5132
RH		 2148 identifier_chars['_'] = '_';
2149 identifier_chars['.'] = '.';
2150
2151 for (p = operand_special_chars; *p != '\0'; p++)
2152 operand_chars[(unsigned char) *p] = *p;
2153 }
2154
2155#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2156 if (IS_ELF)
252b5132
RH		 2157 {
2158 record_alignment (text_section, 2);
2159 record_alignment (data_section, 2);
2160 record_alignment (bss_section, 2);
2161 }
2162#endif
a4447b93
RH		 2163
2164 if (flag_code == CODE_64BIT)
2165 {
2166 x86_dwarf2_return_column = 16;
2167 x86_cie_data_alignment = -8;
2168 }
2169 else
2170 {
2171 x86_dwarf2_return_column = 8;
2172 x86_cie_data_alignment = -4;
2173 }
252b5132
RH		 2174}
2175
2176void
e3bb37b5 2177i386_print_statistics (FILE *file)
252b5132
RH		 2178{
2179 hash_print_statistics (file, "i386 opcode", op_hash);
2180 hash_print_statistics (file, "i386 register", reg_hash);
2181}
2182\f
252b5132
RH		 2183#ifdef DEBUG386
2184
ce8a8b2f 2185/* Debugging routines for md_assemble. */
e3bb37b5 2186static void pte (template *);
40fb9820 2187static void pt (i386_operand_type);
e3bb37b5
L		 2188static void pe (expressionS *);
2189static void ps (symbolS *);
252b5132
RH		 2190
2191static void
e3bb37b5 2192pi (char *line, i386_insn *x)
252b5132 2193{
09f131f2 2194 unsigned int i;
252b5132
RH		 2195
2196 fprintf (stdout, "%s: template ", line);
2197 pte (&x->tm);
09f131f2
JH		 2198 fprintf (stdout, " address: base %s index %s scale %x\n",
2199 x->base_reg ? x->base_reg->reg_name : "none",
2200 x->index_reg ? x->index_reg->reg_name : "none",
2201 x->log2_scale_factor);
2202 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2203 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2204 fprintf (stdout, " sib: base %x index %x scale %x\n",
2205 x->sib.base, x->sib.index, x->sib.scale);
2206 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2207 (x->rex & REX_W) != 0,
2208 (x->rex & REX_R) != 0,
2209 (x->rex & REX_X) != 0,
2210 (x->rex & REX_B) != 0);
85f10a01
MM		 2211 fprintf (stdout, " drex: reg %d rex 0x%x\n",
2212 x->drex.reg, x->drex.rex);
252b5132
RH		 2213 for (i = 0; i < x->operands; i++)
2214 {
2215 fprintf (stdout, " #%d: ", i + 1);
2216 pt (x->types[i]);
2217 fprintf (stdout, "\n");
40fb9820
L		 2218 if (x->types[i].bitfield.reg8
2219 || x->types[i].bitfield.reg16
2220 || x->types[i].bitfield.reg32
2221 || x->types[i].bitfield.reg64
2222 || x->types[i].bitfield.regmmx
2223 || x->types[i].bitfield.regxmm
c0f3af97 2224 || x->types[i].bitfield.regymm
40fb9820
L		 2225 || x->types[i].bitfield.sreg2
2226 || x->types[i].bitfield.sreg3
2227 || x->types[i].bitfield.control
2228 || x->types[i].bitfield.debug
2229 || x->types[i].bitfield.test)
520dc8e8 2230 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 2231 if (operand_type_check (x->types[i], imm))
520dc8e8 2232 pe (x->op[i].imms);
40fb9820 2233 if (operand_type_check (x->types[i], disp))
520dc8e8 2234 pe (x->op[i].disps);
252b5132
RH		 2235 }
2236}
2237
2238static void
e3bb37b5 2239pte (template *t)
252b5132 2240{
09f131f2 2241 unsigned int i;
252b5132 2242 fprintf (stdout, " %d operands ", t->operands);
47926f60 2243 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2244 if (t->extension_opcode != None)
2245 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2246 if (t->opcode_modifier.d)
252b5132 2247 fprintf (stdout, "D");
40fb9820 2248 if (t->opcode_modifier.w)
252b5132
RH		 2249 fprintf (stdout, "W");
2250 fprintf (stdout, "\n");
2251 for (i = 0; i < t->operands; i++)
2252 {
2253 fprintf (stdout, " #%d type ", i + 1);
2254 pt (t->operand_types[i]);
2255 fprintf (stdout, "\n");
2256 }
2257}
2258
2259static void
e3bb37b5 2260pe (expressionS *e)
252b5132 2261{
24eab124 2262 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2263 fprintf (stdout, " add_number %ld (%lx)\n",
2264 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2265 if (e->X_add_symbol)
2266 {
2267 fprintf (stdout, " add_symbol ");
2268 ps (e->X_add_symbol);
2269 fprintf (stdout, "\n");
2270 }
2271 if (e->X_op_symbol)
2272 {
2273 fprintf (stdout, " op_symbol ");
2274 ps (e->X_op_symbol);
2275 fprintf (stdout, "\n");
2276 }
2277}
2278
2279static void
e3bb37b5 2280ps (symbolS *s)
252b5132
RH		 2281{
2282 fprintf (stdout, "%s type %s%s",
2283 S_GET_NAME (s),
2284 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2285 segment_name (S_GET_SEGMENT (s)));
2286}
2287
7b81dfbb 2288static struct type_name
252b5132 2289 {
40fb9820
L		 2290 i386_operand_type mask;
2291 const char *name;
252b5132 2292 }
7b81dfbb 2293const type_names[] =
252b5132 2294{
40fb9820
L		 2295 { OPERAND_TYPE_REG8, "r8" },
2296 { OPERAND_TYPE_REG16, "r16" },
2297 { OPERAND_TYPE_REG32, "r32" },
2298 { OPERAND_TYPE_REG64, "r64" },
2299 { OPERAND_TYPE_IMM8, "i8" },
2300 { OPERAND_TYPE_IMM8, "i8s" },
2301 { OPERAND_TYPE_IMM16, "i16" },
2302 { OPERAND_TYPE_IMM32, "i32" },
2303 { OPERAND_TYPE_IMM32S, "i32s" },
2304 { OPERAND_TYPE_IMM64, "i64" },
2305 { OPERAND_TYPE_IMM1, "i1" },
2306 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2307 { OPERAND_TYPE_DISP8, "d8" },
2308 { OPERAND_TYPE_DISP16, "d16" },
2309 { OPERAND_TYPE_DISP32, "d32" },
2310 { OPERAND_TYPE_DISP32S, "d32s" },
2311 { OPERAND_TYPE_DISP64, "d64" },
2312 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2313 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2314 { OPERAND_TYPE_CONTROL, "control reg" },
2315 { OPERAND_TYPE_TEST, "test reg" },
2316 { OPERAND_TYPE_DEBUG, "debug reg" },
2317 { OPERAND_TYPE_FLOATREG, "FReg" },
2318 { OPERAND_TYPE_FLOATACC, "FAcc" },
2319 { OPERAND_TYPE_SREG2, "SReg2" },
2320 { OPERAND_TYPE_SREG3, "SReg3" },
2321 { OPERAND_TYPE_ACC, "Acc" },
2322 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2323 { OPERAND_TYPE_REGMMX, "rMMX" },
2324 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2325 { OPERAND_TYPE_REGYMM, "rYMM" },
40fb9820 2326 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2327};
2328
2329static void
40fb9820 2330pt (i386_operand_type t)
252b5132 2331{
40fb9820 2332 unsigned int j;
c6fb90c8 2333 i386_operand_type a;
252b5132 2334
40fb9820 2335 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2336 {
2337 a = operand_type_and (t, type_names[j].mask);
0349dc08 2338 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2339 fprintf (stdout, "%s, ", type_names[j].name);
2340 }
252b5132
RH		 2341 fflush (stdout);
2342}
2343
2344#endif /* DEBUG386 */
2345\f
252b5132 2346static bfd_reloc_code_real_type
3956db08 2347reloc (unsigned int size,
64e74474
AM		 2348 int pcrel,
2349 int sign,
2350 bfd_reloc_code_real_type other)
252b5132 2351{
47926f60 2352 if (other != NO_RELOC)
3956db08
JB		 2353 {
2354 reloc_howto_type *reloc;
2355
2356 if (size == 8)
2357 switch (other)
2358 {
64e74474
AM		 2359 case BFD_RELOC_X86_64_GOT32:
2360 return BFD_RELOC_X86_64_GOT64;
2361 break;
2362 case BFD_RELOC_X86_64_PLTOFF64:
2363 return BFD_RELOC_X86_64_PLTOFF64;
2364 break;
2365 case BFD_RELOC_X86_64_GOTPC32:
2366 other = BFD_RELOC_X86_64_GOTPC64;
2367 break;
2368 case BFD_RELOC_X86_64_GOTPCREL:
2369 other = BFD_RELOC_X86_64_GOTPCREL64;
2370 break;
2371 case BFD_RELOC_X86_64_TPOFF32:
2372 other = BFD_RELOC_X86_64_TPOFF64;
2373 break;
2374 case BFD_RELOC_X86_64_DTPOFF32:
2375 other = BFD_RELOC_X86_64_DTPOFF64;
2376 break;
2377 default:
2378 break;
3956db08 2379 }
e05278af
JB		 2380
2381 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2382 if (size == 4 && flag_code != CODE_64BIT)
2383 sign = -1;
2384
3956db08
JB		 2385 reloc = bfd_reloc_type_lookup (stdoutput, other);
2386 if (!reloc)
2387 as_bad (_("unknown relocation (%u)"), other);
2388 else if (size != bfd_get_reloc_size (reloc))
2389 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2390 bfd_get_reloc_size (reloc),
2391 size);
2392 else if (pcrel && !reloc->pc_relative)
2393 as_bad (_("non-pc-relative relocation for pc-relative field"));
2394 else if ((reloc->complain_on_overflow == complain_overflow_signed
2395 && !sign)
2396 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 2397 && sign > 0))
3956db08
JB		 2398 as_bad (_("relocated field and relocation type differ in signedness"));
2399 else
2400 return other;
2401 return NO_RELOC;
2402 }
252b5132
RH		 2403
2404 if (pcrel)
2405 {
3e73aa7c 2406 if (!sign)
3956db08 2407 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2408 switch (size)
2409 {
2410 case 1: return BFD_RELOC_8_PCREL;
2411 case 2: return BFD_RELOC_16_PCREL;
2412 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2413 case 8: return BFD_RELOC_64_PCREL;
252b5132 2414 }
3956db08 2415 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2416 }
2417 else
2418 {
3956db08 2419 if (sign > 0)
e5cb08ac 2420 switch (size)
3e73aa7c
JH		 2421 {
2422 case 4: return BFD_RELOC_X86_64_32S;
2423 }
2424 else
2425 switch (size)
2426 {
2427 case 1: return BFD_RELOC_8;
2428 case 2: return BFD_RELOC_16;
2429 case 4: return BFD_RELOC_32;
2430 case 8: return BFD_RELOC_64;
2431 }
3956db08
JB		 2432 as_bad (_("cannot do %s %u byte relocation"),
2433 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2434 }
2435
bfb32b52 2436 abort ();
252b5132
RH		 2437 return BFD_RELOC_NONE;
2438}
2439
47926f60
KH		 2440/* Here we decide which fixups can be adjusted to make them relative to
2441 the beginning of the section instead of the symbol. Basically we need
2442 to make sure that the dynamic relocations are done correctly, so in
2443 some cases we force the original symbol to be used. */
2444
252b5132 2445int
e3bb37b5 2446tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2447{
6d249963 2448#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2449 if (!IS_ELF)
31312f95
AM		 2450 return 1;
2451
a161fe53
AM		 2452 /* Don't adjust pc-relative references to merge sections in 64-bit
2453 mode. */
2454 if (use_rela_relocations
2455 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2456 && fixP->fx_pcrel)
252b5132 2457 return 0;
31312f95 2458
8d01d9a9
AJ		 2459 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2460 and changed later by validate_fix. */
2461 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2462 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2463 return 0;
2464
ce8a8b2f 2465 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2466 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2467 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2468 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2469 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2470 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2471 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2472 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2473 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2474 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2475 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2476 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2477 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2478 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2479 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2480 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2481 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2482 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2483 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2484 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2485 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2486 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2487 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2488 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2489 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2490 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2491 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2492 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2493 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2494 return 0;
31312f95 2495#endif
252b5132
RH		 2496 return 1;
2497}
252b5132 2498
b4cac588 2499static int
e3bb37b5 2500intel_float_operand (const char *mnemonic)
252b5132 2501{
9306ca4a
JB		 2502 /* Note that the value returned is meaningful only for opcodes with (memory)
2503 operands, hence the code here is free to improperly handle opcodes that
2504 have no operands (for better performance and smaller code). */
2505
2506 if (mnemonic[0] != 'f')
2507 return 0; /* non-math */
2508
2509 switch (mnemonic[1])
2510 {
2511 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2512 the fs segment override prefix not currently handled because no
2513 call path can make opcodes without operands get here */
2514 case 'i':
2515 return 2 /* integer op */;
2516 case 'l':
2517 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2518 return 3; /* fldcw/fldenv */
2519 break;
2520 case 'n':
2521 if (mnemonic[2] != 'o' /* fnop */)
2522 return 3; /* non-waiting control op */
2523 break;
2524 case 'r':
2525 if (mnemonic[2] == 's')
2526 return 3; /* frstor/frstpm */
2527 break;
2528 case 's':
2529 if (mnemonic[2] == 'a')
2530 return 3; /* fsave */
2531 if (mnemonic[2] == 't')
2532 {
2533 switch (mnemonic[3])
2534 {
2535 case 'c': /* fstcw */
2536 case 'd': /* fstdw */
2537 case 'e': /* fstenv */
2538 case 's': /* fsts[gw] */
2539 return 3;
2540 }
2541 }
2542 break;
2543 case 'x':
2544 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2545 return 0; /* fxsave/fxrstor are not really math ops */
2546 break;
2547 }
252b5132 2548
9306ca4a 2549 return 1;
252b5132
RH		 2550}
2551
c0f3af97
L		 2552/* Build the VEX prefix. */
2553
2554static void
fa99fab2 2555build_vex_prefix (const template *t)
c0f3af97
L		 2556{
2557 unsigned int register_specifier;
2558 unsigned int implied_prefix;
2559 unsigned int vector_length;
2560
2561 /* Check register specifier. */
2562 if (i.vex.register_specifier)
2563 {
2564 register_specifier = i.vex.register_specifier->reg_num;
2565 if ((i.vex.register_specifier->reg_flags & RegRex))
2566 register_specifier += 8;
2567 register_specifier = ~register_specifier & 0xf;
2568 }
2569 else
2570 register_specifier = 0xf;
2571
fa99fab2
L		 2572 /* Use 2-byte VEX prefix by swappping destination and source
2573 operand. */
2574 if (!i.swap_operand
2575 && i.operands == i.reg_operands
2576 && i.tm.opcode_modifier.vex0f
2577 && i.tm.opcode_modifier.s
2578 && i.rex == REX_B)
2579 {
2580 unsigned int xchg = i.operands - 1;
2581 union i386_op temp_op;
2582 i386_operand_type temp_type;
2583
2584 temp_type = i.types[xchg];
2585 i.types[xchg] = i.types[0];
2586 i.types[0] = temp_type;
2587 temp_op = i.op[xchg];
2588 i.op[xchg] = i.op[0];
2589 i.op[0] = temp_op;
2590
2591 assert (i.rm.mode == 3);
2592
2593 i.rex = REX_R;
2594 xchg = i.rm.regmem;
2595 i.rm.regmem = i.rm.reg;
2596 i.rm.reg = xchg;
2597
2598 /* Use the next insn. */
2599 i.tm = t[1];
2600 }
2601
c0f3af97
L		 2602 vector_length = i.tm.opcode_modifier.vex256 ? 1 : 0;
2603
2604 switch ((i.tm.base_opcode >> 8) & 0xff)
2605 {
2606 case 0:
2607 implied_prefix = 0;
2608 break;
2609 case DATA_PREFIX_OPCODE:
2610 implied_prefix = 1;
2611 break;
2612 case REPE_PREFIX_OPCODE:
2613 implied_prefix = 2;
2614 break;
2615 case REPNE_PREFIX_OPCODE:
2616 implied_prefix = 3;
2617 break;
2618 default:
2619 abort ();
2620 }
2621
2622 /* Use 2-byte VEX prefix if possible. */
2623 if (i.tm.opcode_modifier.vex0f
2624 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2625 {
2626 /* 2-byte VEX prefix. */
2627 unsigned int r;
2628
2629 i.vex.length = 2;
2630 i.vex.bytes[0] = 0xc5;
2631
2632 /* Check the REX.R bit. */
2633 r = (i.rex & REX_R) ? 0 : 1;
2634 i.vex.bytes[1] = (r << 7
2635 | register_specifier << 3
2636 | vector_length << 2
2637 | implied_prefix);
2638 }
2639 else
2640 {
2641 /* 3-byte VEX prefix. */
2642 unsigned int m, w;
2643
2644 if (i.tm.opcode_modifier.vex0f)
2645 m = 0x1;
2646 else if (i.tm.opcode_modifier.vex0f38)
2647 m = 0x2;
2648 else if (i.tm.opcode_modifier.vex0f3a)
2649 m = 0x3;
2650 else
2651 abort ();
2652
2653 i.vex.length = 3;
2654 i.vex.bytes[0] = 0xc4;
2655
2656 /* The high 3 bits of the second VEX byte are 1's compliment
2657 of RXB bits from REX. */
2658 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2659
2660 /* Check the REX.W bit. */
2661 w = (i.rex & REX_W) ? 1 : 0;
2662 if (i.tm.opcode_modifier.vexw0 || i.tm.opcode_modifier.vexw1)
2663 {
2664 if (w)
2665 abort ();
2666
2667 if (i.tm.opcode_modifier.vexw1)
2668 w = 1;
2669 }
2670
2671 i.vex.bytes[2] = (w << 7
2672 | register_specifier << 3
2673 | vector_length << 2
2674 | implied_prefix);
2675 }
2676}
2677
65da13b5
L		 2678static void
2679process_immext (void)
2680{
2681 expressionS *exp;
2682
2683 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2684 {
1fed0ba1
L		 2685 /* SSE3 Instructions have the fixed operands with an opcode
2686 suffix which is coded in the same place as an 8-bit immediate
2687 field would be. Here we check those operands and remove them
2688 afterwards. */
65da13b5
L		 2689 unsigned int x;
2690
2691 for (x = 0; x < i.operands; x++)
2692 if (i.op[x].regs->reg_num != x)
2693 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 2694 register_prefix, i.op[x].regs->reg_name, x + 1,
2695 i.tm.name);
2696
2697 i.operands = 0;
65da13b5
L		 2698 }
2699
c0f3af97 2700 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 2701 which is coded in the same place as an 8-bit immediate field
2702 would be. Here we fake an 8-bit immediate operand from the
2703 opcode suffix stored in tm.extension_opcode.
2704
c0f3af97
L		 2705 SSE5 and AVX instructions also use this encoding, for some of
2706 3 argument instructions. */
65da13b5
L		 2707
2708 assert (i.imm_operands == 0
2709 && (i.operands <= 2
2710 || (i.tm.cpu_flags.bitfield.cpusse5
c0f3af97
L		 2711 && i.operands <= 3)
2712 || (i.tm.opcode_modifier.vex
2713 && i.operands <= 4)));
65da13b5
L		 2714
2715 exp = &im_expressions[i.imm_operands++];
2716 i.op[i.operands].imms = exp;
2717 i.types[i.operands] = imm8;
2718 i.operands++;
2719 exp->X_op = O_constant;
2720 exp->X_add_number = i.tm.extension_opcode;
2721 i.tm.extension_opcode = None;
2722}
2723
252b5132
RH		 2724/* This is the guts of the machine-dependent assembler. LINE points to a
2725 machine dependent instruction. This function is supposed to emit
2726 the frags/bytes it assembles to. */
2727
2728void
65da13b5 2729md_assemble (char *line)
252b5132 2730{
40fb9820 2731 unsigned int j;
252b5132 2732 char mnemonic[MAX_MNEM_SIZE];
fa99fab2 2733 const template *t;
252b5132 2734
47926f60 2735 /* Initialize globals. */
252b5132
RH		 2736 memset (&i, '\0', sizeof (i));
2737 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2738 i.reloc[j] = NO_RELOC;
252b5132
RH		 2739 memset (disp_expressions, '\0', sizeof (disp_expressions));
2740 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2741 save_stack_p = save_stack;
252b5132
RH		 2742
2743 /* First parse an instruction mnemonic & call i386_operand for the operands.
2744 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2745 start of a (possibly prefixed) mnemonic. */
252b5132 2746
29b0f896
AM		 2747 line = parse_insn (line, mnemonic);
2748 if (line == NULL)
2749 return;
252b5132 2750
29b0f896
AM		 2751 line = parse_operands (line, mnemonic);
2752 if (line == NULL)
2753 return;
252b5132 2754
29b0f896
AM		 2755 /* Now we've parsed the mnemonic into a set of templates, and have the
2756 operands at hand. */
2757
2758 /* All intel opcodes have reversed operands except for "bound" and
2759 "enter". We also don't reverse intersegment "jmp" and "call"
2760 instructions with 2 immediate operands so that the immediate segment
050dfa73 2761 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2762 if (intel_syntax
2763 && i.operands > 1
29b0f896 2764 && (strcmp (mnemonic, "bound") != 0)
30123838 2765 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2766 && !(operand_type_check (i.types[0], imm)
2767 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2768 swap_operands ();
2769
ec56d5c0
JB		 2770 /* The order of the immediates should be reversed
2771 for 2 immediates extrq and insertq instructions */
2772 if (i.imm_operands == 2
2773 && (strcmp (mnemonic, "extrq") == 0
2774 || strcmp (mnemonic, "insertq") == 0))
2775 swap_2_operands (0, 1);
2776
29b0f896
AM		 2777 if (i.imm_operands)
2778 optimize_imm ();
2779
b300c311
L		 2780 /* Don't optimize displacement for movabs since it only takes 64bit
2781 displacement. */
2782 if (i.disp_operands
2783 && (flag_code != CODE_64BIT
2784 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2785 optimize_disp ();
2786
2787 /* Next, we find a template that matches the given insn,
2788 making sure the overlap of the given operands types is consistent
2789 with the template operand types. */
252b5132 2790
fa99fab2 2791 if (!(t = match_template ()))
29b0f896 2792 return;
252b5132 2793
daf50ae7 2794 if (sse_check != sse_check_none
81f8a913 2795 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 2796 && (i.tm.cpu_flags.bitfield.cpusse
2797 || i.tm.cpu_flags.bitfield.cpusse2
2798 || i.tm.cpu_flags.bitfield.cpusse3
2799 || i.tm.cpu_flags.bitfield.cpussse3
2800 || i.tm.cpu_flags.bitfield.cpusse4_1
2801 || i.tm.cpu_flags.bitfield.cpusse4_2))
2802 {
2803 (sse_check == sse_check_warning
2804 ? as_warn
2805 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
2806 }
2807
321fd21e
L		 2808 /* Zap movzx and movsx suffix. The suffix has been set from
2809 "word ptr" or "byte ptr" on the source operand in Intel syntax
2810 or extracted from mnemonic in AT&T syntax. But we'll use
2811 the destination register to choose the suffix for encoding. */
2812 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 2813 {
321fd21e
L		 2814 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2815 there is no suffix, the default will be byte extension. */
2816 if (i.reg_operands != 2
2817 && !i.suffix
2818 && intel_syntax)
2819 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2820
2821 i.suffix = 0;
cd61ebfe 2822 }
24eab124 2823
40fb9820 2824 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2825 if (!add_prefix (FWAIT_OPCODE))
2826 return;
252b5132 2827
29b0f896 2828 /* Check string instruction segment overrides. */
40fb9820 2829 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 2830 {
2831 if (!check_string ())
5dd0794d 2832 return;
fc0763e6 2833 i.disp_operands = 0;
29b0f896 2834 }
5dd0794d 2835
29b0f896
AM		 2836 if (!process_suffix ())
2837 return;
e413e4e9 2838
29b0f896
AM		 2839 /* Make still unresolved immediate matches conform to size of immediate
2840 given in i.suffix. */
2841 if (!finalize_imm ())
2842 return;
252b5132 2843
40fb9820 2844 if (i.types[0].bitfield.imm1)
29b0f896 2845 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 2846
40fb9820 2847 for (j = 0; j < 3; j++)
c6fb90c8
L		 2848 if (i.types[j].bitfield.inoutportreg
2849 || i.types[j].bitfield.shiftcount
2850 || i.types[j].bitfield.acc
2851 || i.types[j].bitfield.floatacc)
40fb9820
L		 2852 i.reg_operands--;
2853
c0f3af97
L		 2854 /* ImmExt should be processed after SSE2AVX. */
2855 if (!i.tm.opcode_modifier.sse2avx
2856 && i.tm.opcode_modifier.immext)
65da13b5 2857 process_immext ();
252b5132 2858
29b0f896
AM		 2859 /* For insns with operands there are more diddles to do to the opcode. */
2860 if (i.operands)
2861 {
2862 if (!process_operands ())
2863 return;
2864 }
40fb9820 2865 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 2866 {
2867 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2868 as_warn (_("translating to `%sp'"), i.tm.name);
2869 }
252b5132 2870
c0f3af97 2871 if (i.tm.opcode_modifier.vex)
fa99fab2 2872 build_vex_prefix (t);
c0f3af97 2873
29b0f896
AM		 2874 /* Handle conversion of 'int $3' --> special int3 insn. */
2875 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2876 {
2877 i.tm.base_opcode = INT3_OPCODE;
2878 i.imm_operands = 0;
2879 }
252b5132 2880
40fb9820
L		 2881 if ((i.tm.opcode_modifier.jump
2882 || i.tm.opcode_modifier.jumpbyte
2883 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 2884 && i.op[0].disps->X_op == O_constant)
2885 {
2886 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2887 the absolute address given by the constant. Since ix86 jumps and
2888 calls are pc relative, we need to generate a reloc. */
2889 i.op[0].disps->X_add_symbol = &abs_symbol;
2890 i.op[0].disps->X_op = O_symbol;
2891 }
252b5132 2892
40fb9820 2893 if (i.tm.opcode_modifier.rex64)
161a04f6 2894 i.rex |= REX_W;
252b5132 2895
29b0f896
AM		 2896 /* For 8 bit registers we need an empty rex prefix. Also if the
2897 instruction already has a prefix, we need to convert old
2898 registers to new ones. */
773f551c 2899
40fb9820 2900 if ((i.types[0].bitfield.reg8
29b0f896 2901 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 2902 || (i.types[1].bitfield.reg8
29b0f896 2903 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 2904 || ((i.types[0].bitfield.reg8
2905 || i.types[1].bitfield.reg8)
29b0f896
AM		 2906 && i.rex != 0))
2907 {
2908 int x;
726c5dcd 2909
29b0f896
AM		 2910 i.rex |= REX_OPCODE;
2911 for (x = 0; x < 2; x++)
2912 {
2913 /* Look for 8 bit operand that uses old registers. */
40fb9820 2914 if (i.types[x].bitfield.reg8
29b0f896 2915 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 2916 {
29b0f896
AM		 2917 /* In case it is "hi" register, give up. */
2918 if (i.op[x].regs->reg_num > 3)
a540244d 2919 as_bad (_("can't encode register '%s%s' in an "
4eed87de 2920 "instruction requiring REX prefix."),
a540244d 2921 register_prefix, i.op[x].regs->reg_name);
773f551c 2922
29b0f896
AM		 2923 /* Otherwise it is equivalent to the extended register.
2924 Since the encoding doesn't change this is merely
2925 cosmetic cleanup for debug output. */
2926
2927 i.op[x].regs = i.op[x].regs + 8;
773f551c 2928 }
29b0f896
AM		 2929 }
2930 }
773f551c 2931
85f10a01
MM		 2932 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2933 REX prefix. */
2934 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
2935 {
2936 i.drex.rex = i.rex;
2937 i.rex = 0;
2938 }
2939 else if (i.rex != 0)
29b0f896
AM		 2940 add_prefix (REX_OPCODE | i.rex);
2941
2942 /* We are ready to output the insn. */
2943 output_insn ();
2944}
2945
2946static char *
e3bb37b5 2947parse_insn (char *line, char *mnemonic)
29b0f896
AM		 2948{
2949 char *l = line;
2950 char *token_start = l;
2951 char *mnem_p;
5c6af06e
JB		 2952 int supported;
2953 const template *t;
b6169b20 2954 char *dot_p = NULL;
29b0f896
AM		 2955
2956 /* Non-zero if we found a prefix only acceptable with string insns. */
2957 const char *expecting_string_instruction = NULL;
45288df1 2958
29b0f896
AM		 2959 while (1)
2960 {
2961 mnem_p = mnemonic;
2962 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2963 {
b6169b20
L		 2964 if (*mnem_p == '.')
2965 dot_p = mnem_p;
29b0f896
AM		 2966 mnem_p++;
2967 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 2968 {
29b0f896
AM		 2969 as_bad (_("no such instruction: `%s'"), token_start);
2970 return NULL;
2971 }
2972 l++;
2973 }
2974 if (!is_space_char (*l)
2975 && *l != END_OF_INSN
e44823cf
JB		 2976 && (intel_syntax
2977 || (*l != PREFIX_SEPARATOR
2978 && *l != ',')))
29b0f896
AM		 2979 {
2980 as_bad (_("invalid character %s in mnemonic"),
2981 output_invalid (*l));
2982 return NULL;
2983 }
2984 if (token_start == l)
2985 {
e44823cf 2986 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 2987 as_bad (_("expecting prefix; got nothing"));
2988 else
2989 as_bad (_("expecting mnemonic; got nothing"));
2990 return NULL;
2991 }
45288df1 2992
29b0f896
AM		 2993 /* Look up instruction (or prefix) via hash table. */
2994 current_templates = hash_find (op_hash, mnemonic);
47926f60 2995
29b0f896
AM		 2996 if (*l != END_OF_INSN
2997 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2998 && current_templates
40fb9820 2999 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3000 {
c6fb90c8 3001 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3002 {
3003 as_bad ((flag_code != CODE_64BIT
3004 ? _("`%s' is only supported in 64-bit mode")
3005 : _("`%s' is not supported in 64-bit mode")),
3006 current_templates->start->name);
3007 return NULL;
3008 }
29b0f896
AM		 3009 /* If we are in 16-bit mode, do not allow addr16 or data16.
3010 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3011 if ((current_templates->start->opcode_modifier.size16
3012 || current_templates->start->opcode_modifier.size32)
29b0f896 3013 && flag_code != CODE_64BIT
40fb9820 3014 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3015 ^ (flag_code == CODE_16BIT)))
3016 {
3017 as_bad (_("redundant %s prefix"),
3018 current_templates->start->name);
3019 return NULL;
45288df1 3020 }
29b0f896
AM		 3021 /* Add prefix, checking for repeated prefixes. */
3022 switch (add_prefix (current_templates->start->base_opcode))
3023 {
3024 case 0:
3025 return NULL;
3026 case 2:
3027 expecting_string_instruction = current_templates->start->name;
3028 break;
3029 }
3030 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3031 token_start = ++l;
3032 }
3033 else
3034 break;
3035 }
45288df1 3036
30a55f88 3037 if (!current_templates)
b6169b20 3038 {
30a55f88
L		 3039 /* Check if we should swap operand in encoding. */
3040 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3041 i.swap_operand = 1;
3042 else
3043 goto check_suffix;
3044 mnem_p = dot_p;
3045 *dot_p = '\0';
3046 current_templates = hash_find (op_hash, mnemonic);
b6169b20
L		 3047 }
3048
29b0f896
AM		 3049 if (!current_templates)
3050 {
b6169b20 3051check_suffix:
29b0f896
AM		 3052 /* See if we can get a match by trimming off a suffix. */
3053 switch (mnem_p[-1])
3054 {
3055 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3056 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3057 i.suffix = SHORT_MNEM_SUFFIX;
3058 else
29b0f896
AM		 3059 case BYTE_MNEM_SUFFIX:
3060 case QWORD_MNEM_SUFFIX:
3061 i.suffix = mnem_p[-1];
3062 mnem_p[-1] = '\0';
3063 current_templates = hash_find (op_hash, mnemonic);
3064 break;
3065 case SHORT_MNEM_SUFFIX:
3066 case LONG_MNEM_SUFFIX:
3067 if (!intel_syntax)
3068 {
3069 i.suffix = mnem_p[-1];
3070 mnem_p[-1] = '\0';
3071 current_templates = hash_find (op_hash, mnemonic);
3072 }
3073 break;
252b5132 3074
29b0f896
AM		 3075 /* Intel Syntax. */
3076 case 'd':
3077 if (intel_syntax)
3078 {
9306ca4a 3079 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3080 i.suffix = SHORT_MNEM_SUFFIX;
3081 else
3082 i.suffix = LONG_MNEM_SUFFIX;
3083 mnem_p[-1] = '\0';
3084 current_templates = hash_find (op_hash, mnemonic);
3085 }
3086 break;
3087 }
3088 if (!current_templates)
3089 {
3090 as_bad (_("no such instruction: `%s'"), token_start);
3091 return NULL;
3092 }
3093 }
252b5132 3094
40fb9820
L		 3095 if (current_templates->start->opcode_modifier.jump
3096 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3097 {
3098 /* Check for a branch hint. We allow ",pt" and ",pn" for
3099 predict taken and predict not taken respectively.
3100 I'm not sure that branch hints actually do anything on loop
3101 and jcxz insns (JumpByte) for current Pentium4 chips. They
3102 may work in the future and it doesn't hurt to accept them
3103 now. */
3104 if (l[0] == ',' && l[1] == 'p')
3105 {
3106 if (l[2] == 't')
3107 {
3108 if (!add_prefix (DS_PREFIX_OPCODE))
3109 return NULL;
3110 l += 3;
3111 }
3112 else if (l[2] == 'n')
3113 {
3114 if (!add_prefix (CS_PREFIX_OPCODE))
3115 return NULL;
3116 l += 3;
3117 }
3118 }
3119 }
3120 /* Any other comma loses. */
3121 if (*l == ',')
3122 {
3123 as_bad (_("invalid character %s in mnemonic"),
3124 output_invalid (*l));
3125 return NULL;
3126 }
252b5132 3127
29b0f896 3128 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3129 supported = 0;
3130 for (t = current_templates->start; t < current_templates->end; ++t)
3131 {
c0f3af97
L		 3132 supported |= cpu_flags_match (t);
3133 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3134 goto skip;
5c6af06e 3135 }
3629bb00 3136
c0f3af97 3137 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3138 {
3139 as_bad (flag_code == CODE_64BIT
3140 ? _("`%s' is not supported in 64-bit mode")
3141 : _("`%s' is only supported in 64-bit mode"),
3142 current_templates->start->name);
3143 return NULL;
3144 }
c0f3af97 3145 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3146 {
3629bb00 3147 as_bad (_("`%s' is not supported on `%s%s'"),
41aacd83
L		 3148 current_templates->start->name,
3149 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3150 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3151 return NULL;
29b0f896 3152 }
3629bb00
L		 3153
3154skip:
3155 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3156 && (flag_code != CODE_16BIT))
29b0f896
AM		 3157 {
3158 as_warn (_("use .code16 to ensure correct addressing mode"));
3159 }
252b5132 3160
29b0f896 3161 /* Check for rep/repne without a string instruction. */
f41bbced 3162 if (expecting_string_instruction)
29b0f896 3163 {
f41bbced
JB		 3164 static templates override;
3165
3166 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 3167 if (t->opcode_modifier.isstring)
f41bbced
JB		 3168 break;
3169 if (t >= current_templates->end)
3170 {
3171 as_bad (_("expecting string instruction after `%s'"),
64e74474 3172 expecting_string_instruction);
f41bbced
JB		 3173 return NULL;
3174 }
3175 for (override.start = t; t < current_templates->end; ++t)
40fb9820 3176 if (!t->opcode_modifier.isstring)
f41bbced
JB		 3177 break;
3178 override.end = t;
3179 current_templates = &override;
29b0f896 3180 }
252b5132 3181
29b0f896
AM		 3182 return l;
3183}
252b5132 3184
29b0f896 3185static char *
e3bb37b5 3186parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3187{
3188 char *token_start;
3138f287 3189
29b0f896
AM		 3190 /* 1 if operand is pending after ','. */
3191 unsigned int expecting_operand = 0;
252b5132 3192
29b0f896
AM		 3193 /* Non-zero if operand parens not balanced. */
3194 unsigned int paren_not_balanced;
3195
3196 while (*l != END_OF_INSN)
3197 {
3198 /* Skip optional white space before operand. */
3199 if (is_space_char (*l))
3200 ++l;
3201 if (!is_operand_char (*l) && *l != END_OF_INSN)
3202 {
3203 as_bad (_("invalid character %s before operand %d"),
3204 output_invalid (*l),
3205 i.operands + 1);
3206 return NULL;
3207 }
3208 token_start = l; /* after white space */
3209 paren_not_balanced = 0;
3210 while (paren_not_balanced || *l != ',')
3211 {
3212 if (*l == END_OF_INSN)
3213 {
3214 if (paren_not_balanced)
3215 {
3216 if (!intel_syntax)
3217 as_bad (_("unbalanced parenthesis in operand %d."),
3218 i.operands + 1);
3219 else
3220 as_bad (_("unbalanced brackets in operand %d."),
3221 i.operands + 1);
3222 return NULL;
3223 }
3224 else
3225 break; /* we are done */
3226 }
3227 else if (!is_operand_char (*l) && !is_space_char (*l))
3228 {
3229 as_bad (_("invalid character %s in operand %d"),
3230 output_invalid (*l),
3231 i.operands + 1);
3232 return NULL;
3233 }
3234 if (!intel_syntax)
3235 {
3236 if (*l == '(')
3237 ++paren_not_balanced;
3238 if (*l == ')')
3239 --paren_not_balanced;
3240 }
3241 else
3242 {
3243 if (*l == '[')
3244 ++paren_not_balanced;
3245 if (*l == ']')
3246 --paren_not_balanced;
3247 }
3248 l++;
3249 }
3250 if (l != token_start)
3251 { /* Yes, we've read in another operand. */
3252 unsigned int operand_ok;
3253 this_operand = i.operands++;
7d5e4556 3254 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3255 if (i.operands > MAX_OPERANDS)
3256 {
3257 as_bad (_("spurious operands; (%d operands/instruction max)"),
3258 MAX_OPERANDS);
3259 return NULL;
3260 }
3261 /* Now parse operand adding info to 'i' as we go along. */
3262 END_STRING_AND_SAVE (l);
3263
3264 if (intel_syntax)
3265 operand_ok =
3266 i386_intel_operand (token_start,
3267 intel_float_operand (mnemonic));
3268 else
a7619375 3269 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3270
3271 RESTORE_END_STRING (l);
3272 if (!operand_ok)
3273 return NULL;
3274 }
3275 else
3276 {
3277 if (expecting_operand)
3278 {
3279 expecting_operand_after_comma:
3280 as_bad (_("expecting operand after ','; got nothing"));
3281 return NULL;
3282 }
3283 if (*l == ',')
3284 {
3285 as_bad (_("expecting operand before ','; got nothing"));
3286 return NULL;
3287 }
3288 }
7f3f1ea2 3289
29b0f896
AM		 3290 /* Now *l must be either ',' or END_OF_INSN. */
3291 if (*l == ',')
3292 {
3293 if (*++l == END_OF_INSN)
3294 {
3295 /* Just skip it, if it's \n complain. */
3296 goto expecting_operand_after_comma;
3297 }
3298 expecting_operand = 1;
3299 }
3300 }
3301 return l;
3302}
7f3f1ea2 3303
050dfa73 3304static void
4d456e3d 3305swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3306{
3307 union i386_op temp_op;
40fb9820 3308 i386_operand_type temp_type;
050dfa73 3309 enum bfd_reloc_code_real temp_reloc;
4eed87de 3310
050dfa73
MM		 3311 temp_type = i.types[xchg2];
3312 i.types[xchg2] = i.types[xchg1];
3313 i.types[xchg1] = temp_type;
3314 temp_op = i.op[xchg2];
3315 i.op[xchg2] = i.op[xchg1];
3316 i.op[xchg1] = temp_op;
3317 temp_reloc = i.reloc[xchg2];
3318 i.reloc[xchg2] = i.reloc[xchg1];
3319 i.reloc[xchg1] = temp_reloc;
3320}
3321
29b0f896 3322static void
e3bb37b5 3323swap_operands (void)
29b0f896 3324{
b7c61d9a 3325 switch (i.operands)
050dfa73 3326 {
c0f3af97 3327 case 5:
b7c61d9a 3328 case 4:
4d456e3d 3329 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3330 case 3:
3331 case 2:
4d456e3d 3332 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3333 break;
3334 default:
3335 abort ();
29b0f896 3336 }
29b0f896
AM		 3337
3338 if (i.mem_operands == 2)
3339 {
3340 const seg_entry *temp_seg;
3341 temp_seg = i.seg[0];
3342 i.seg[0] = i.seg[1];
3343 i.seg[1] = temp_seg;
3344 }
3345}
252b5132 3346
29b0f896
AM		 3347/* Try to ensure constant immediates are represented in the smallest
3348 opcode possible. */
3349static void
e3bb37b5 3350optimize_imm (void)
29b0f896
AM		 3351{
3352 char guess_suffix = 0;
3353 int op;
252b5132 3354
29b0f896
AM		 3355 if (i.suffix)
3356 guess_suffix = i.suffix;
3357 else if (i.reg_operands)
3358 {
3359 /* Figure out a suffix from the last register operand specified.
3360 We can't do this properly yet, ie. excluding InOutPortReg,
3361 but the following works for instructions with immediates.
3362 In any case, we can't set i.suffix yet. */
3363 for (op = i.operands; --op >= 0;)
40fb9820
L		 3364 if (i.types[op].bitfield.reg8)
3365 {
3366 guess_suffix = BYTE_MNEM_SUFFIX;
3367 break;
3368 }
3369 else if (i.types[op].bitfield.reg16)
252b5132 3370 {
40fb9820
L		 3371 guess_suffix = WORD_MNEM_SUFFIX;
3372 break;
3373 }
3374 else if (i.types[op].bitfield.reg32)
3375 {
3376 guess_suffix = LONG_MNEM_SUFFIX;
3377 break;
3378 }
3379 else if (i.types[op].bitfield.reg64)
3380 {
3381 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3382 break;
252b5132 3383 }
29b0f896
AM		 3384 }
3385 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3386 guess_suffix = WORD_MNEM_SUFFIX;
3387
3388 for (op = i.operands; --op >= 0;)
40fb9820 3389 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3390 {
3391 switch (i.op[op].imms->X_op)
252b5132 3392 {
29b0f896
AM		 3393 case O_constant:
3394 /* If a suffix is given, this operand may be shortened. */
3395 switch (guess_suffix)
252b5132 3396 {
29b0f896 3397 case LONG_MNEM_SUFFIX:
40fb9820
L		 3398 i.types[op].bitfield.imm32 = 1;
3399 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3400 break;
3401 case WORD_MNEM_SUFFIX:
40fb9820
L		 3402 i.types[op].bitfield.imm16 = 1;
3403 i.types[op].bitfield.imm32 = 1;
3404 i.types[op].bitfield.imm32s = 1;
3405 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3406 break;
3407 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3408 i.types[op].bitfield.imm8 = 1;
3409 i.types[op].bitfield.imm8s = 1;
3410 i.types[op].bitfield.imm16 = 1;
3411 i.types[op].bitfield.imm32 = 1;
3412 i.types[op].bitfield.imm32s = 1;
3413 i.types[op].bitfield.imm64 = 1;
29b0f896 3414 break;
252b5132 3415 }
252b5132 3416
29b0f896
AM		 3417 /* If this operand is at most 16 bits, convert it
3418 to a signed 16 bit number before trying to see
3419 whether it will fit in an even smaller size.
3420 This allows a 16-bit operand such as $0xffe0 to
3421 be recognised as within Imm8S range. */
40fb9820 3422 if ((i.types[op].bitfield.imm16)
29b0f896 3423 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3424 {
29b0f896
AM		 3425 i.op[op].imms->X_add_number =
3426 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3427 }
40fb9820 3428 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3429 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3430 == 0))
3431 {
3432 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3433 ^ ((offsetT) 1 << 31))
3434 - ((offsetT) 1 << 31));
3435 }
40fb9820 3436 i.types[op]
c6fb90c8
L		 3437 = operand_type_or (i.types[op],
3438 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3439
29b0f896
AM		 3440 /* We must avoid matching of Imm32 templates when 64bit
3441 only immediate is available. */
3442 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3443 i.types[op].bitfield.imm32 = 0;
29b0f896 3444 break;
252b5132 3445
29b0f896
AM		 3446 case O_absent:
3447 case O_register:
3448 abort ();
3449
3450 /* Symbols and expressions. */
3451 default:
9cd96992
JB		 3452 /* Convert symbolic operand to proper sizes for matching, but don't
3453 prevent matching a set of insns that only supports sizes other
3454 than those matching the insn suffix. */
3455 {
40fb9820 3456 i386_operand_type mask, allowed;
9cd96992
JB		 3457 const template *t;
3458
0dfbf9d7
L		 3459 operand_type_set (&mask, 0);
3460 operand_type_set (&allowed, 0);
40fb9820 3461
4eed87de
AM		 3462 for (t = current_templates->start;
3463 t < current_templates->end;
3464 ++t)
c6fb90c8
L		 3465 allowed = operand_type_or (allowed,
3466 t->operand_types[op]);
9cd96992
JB		 3467 switch (guess_suffix)
3468 {
3469 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3470 mask.bitfield.imm64 = 1;
3471 mask.bitfield.imm32s = 1;
9cd96992
JB		 3472 break;
3473 case LONG_MNEM_SUFFIX:
40fb9820 3474 mask.bitfield.imm32 = 1;
9cd96992
JB		 3475 break;
3476 case WORD_MNEM_SUFFIX:
40fb9820 3477 mask.bitfield.imm16 = 1;
9cd96992
JB		 3478 break;
3479 case BYTE_MNEM_SUFFIX:
40fb9820 3480 mask.bitfield.imm8 = 1;
9cd96992
JB		 3481 break;
3482 default:
9cd96992
JB		 3483 break;
3484 }
c6fb90c8 3485 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3486 if (!operand_type_all_zero (&allowed))
c6fb90c8 3487 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3488 }
29b0f896 3489 break;
252b5132 3490 }
29b0f896
AM		 3491 }
3492}
47926f60 3493
29b0f896
AM		 3494/* Try to use the smallest displacement type too. */
3495static void
e3bb37b5 3496optimize_disp (void)
29b0f896
AM		 3497{
3498 int op;
3e73aa7c 3499
29b0f896 3500 for (op = i.operands; --op >= 0;)
40fb9820 3501 if (operand_type_check (i.types[op], disp))
252b5132 3502 {
b300c311 3503 if (i.op[op].disps->X_op == O_constant)
252b5132 3504 {
b300c311 3505 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 3506
40fb9820 3507 if (i.types[op].bitfield.disp16
b300c311
L		 3508 && (disp & ~(offsetT) 0xffff) == 0)
3509 {
3510 /* If this operand is at most 16 bits, convert
3511 to a signed 16 bit number and don't use 64bit
3512 displacement. */
3513 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3514 i.types[op].bitfield.disp64 = 0;
b300c311 3515 }
40fb9820 3516 if (i.types[op].bitfield.disp32
b300c311
L		 3517 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
3518 {
3519 /* If this operand is at most 32 bits, convert
3520 to a signed 32 bit number and don't use 64bit
3521 displacement. */
3522 disp &= (((offsetT) 2 << 31) - 1);
3523 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3524 i.types[op].bitfield.disp64 = 0;
b300c311 3525 }
40fb9820 3526 if (!disp && i.types[op].bitfield.baseindex)
b300c311 3527 {
40fb9820
L		 3528 i.types[op].bitfield.disp8 = 0;
3529 i.types[op].bitfield.disp16 = 0;
3530 i.types[op].bitfield.disp32 = 0;
3531 i.types[op].bitfield.disp32s = 0;
3532 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3533 i.op[op].disps = 0;
3534 i.disp_operands--;
3535 }
3536 else if (flag_code == CODE_64BIT)
3537 {
3538 if (fits_in_signed_long (disp))
28a9d8f5 3539 {
40fb9820
L		 3540 i.types[op].bitfield.disp64 = 0;
3541 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3542 }
b300c311 3543 if (fits_in_unsigned_long (disp))
40fb9820 3544 i.types[op].bitfield.disp32 = 1;
b300c311 3545 }
40fb9820
L		 3546 if ((i.types[op].bitfield.disp32
3547 || i.types[op].bitfield.disp32s
3548 || i.types[op].bitfield.disp16)
b300c311 3549 && fits_in_signed_byte (disp))
40fb9820 3550 i.types[op].bitfield.disp8 = 1;
252b5132 3551 }
67a4f2b7
AO		 3552 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3553 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3554 {
3555 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3556 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3557 i.types[op].bitfield.disp8 = 0;
3558 i.types[op].bitfield.disp16 = 0;
3559 i.types[op].bitfield.disp32 = 0;
3560 i.types[op].bitfield.disp32s = 0;
3561 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3562 }
3563 else
b300c311 3564 /* We only support 64bit displacement on constants. */
40fb9820 3565 i.types[op].bitfield.disp64 = 0;
252b5132 3566 }
29b0f896
AM		 3567}
3568
fa99fab2 3569static const template *
e3bb37b5 3570match_template (void)
29b0f896
AM		 3571{
3572 /* Points to template once we've found it. */
3573 const template *t;
40fb9820 3574 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 3575 i386_operand_type overlap4;
29b0f896 3576 unsigned int found_reverse_match;
40fb9820
L		 3577 i386_opcode_modifier suffix_check;
3578 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3579 int addr_prefix_disp;
a5c311ca 3580 unsigned int j;
3629bb00 3581 unsigned int found_cpu_match;
45664ddb 3582 unsigned int check_register;
29b0f896 3583
c0f3af97
L		 3584#if MAX_OPERANDS != 5
3585# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 3586#endif
3587
29b0f896 3588 found_reverse_match = 0;
539e75ad 3589 addr_prefix_disp = -1;
40fb9820
L		 3590
3591 memset (&suffix_check, 0, sizeof (suffix_check));
3592 if (i.suffix == BYTE_MNEM_SUFFIX)
3593 suffix_check.no_bsuf = 1;
3594 else if (i.suffix == WORD_MNEM_SUFFIX)
3595 suffix_check.no_wsuf = 1;
3596 else if (i.suffix == SHORT_MNEM_SUFFIX)
3597 suffix_check.no_ssuf = 1;
3598 else if (i.suffix == LONG_MNEM_SUFFIX)
3599 suffix_check.no_lsuf = 1;
3600 else if (i.suffix == QWORD_MNEM_SUFFIX)
3601 suffix_check.no_qsuf = 1;
3602 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3603 suffix_check.no_ldsuf = 1;
29b0f896 3604
45aa61fe 3605 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3606 {
539e75ad
L		 3607 addr_prefix_disp = -1;
3608
29b0f896
AM		 3609 /* Must have right number of operands. */
3610 if (i.operands != t->operands)
3611 continue;
3612
50aecf8c 3613 /* Check processor support. */
c0f3af97
L		 3614 found_cpu_match = (cpu_flags_match (t)
3615 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 3616 if (!found_cpu_match)
3617 continue;
3618
e1d4d893
L		 3619 /* Check old gcc support. */
3620 if (!old_gcc && t->opcode_modifier.oldgcc)
3621 continue;
3622
3623 /* Check AT&T mnemonic. */
3624 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3625 continue;
3626
5c07affc
L		 3627 /* Check AT&T syntax Intel syntax. */
3628 if ((intel_syntax && t->opcode_modifier.attsyntax)
3629 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3630 continue;
3631
20592a94 3632 /* Check the suffix, except for some instructions in intel mode. */
567e4e96
L		 3633 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3634 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3635 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3636 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3637 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3638 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3639 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3640 continue;
3641
5c07affc 3642 if (!operand_size_match (t))
7d5e4556 3643 continue;
539e75ad 3644
5c07affc
L		 3645 for (j = 0; j < MAX_OPERANDS; j++)
3646 operand_types[j] = t->operand_types[j];
3647
45aa61fe
AM		 3648 /* In general, don't allow 64-bit operands in 32-bit mode. */
3649 if (i.suffix == QWORD_MNEM_SUFFIX
3650 && flag_code != CODE_64BIT
3651 && (intel_syntax
40fb9820 3652 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3653 && !intel_float_operand (t->name))
3654 : intel_float_operand (t->name) != 2)
40fb9820 3655 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 3656 && !operand_types[0].bitfield.regxmm
3657 && !operand_types[0].bitfield.regymm)
40fb9820 3658 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 3659 && !!operand_types[t->operands > 1].bitfield.regxmm
3660 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 3661 && (t->base_opcode != 0x0fc7
3662 || t->extension_opcode != 1 /* cmpxchg8b */))
3663 continue;
3664
192dc9c6
JB		 3665 /* In general, don't allow 32-bit operands on pre-386. */
3666 else if (i.suffix == LONG_MNEM_SUFFIX
3667 && !cpu_arch_flags.bitfield.cpui386
3668 && (intel_syntax
3669 ? (!t->opcode_modifier.ignoresize
3670 && !intel_float_operand (t->name))
3671 : intel_float_operand (t->name) != 2)
3672 && ((!operand_types[0].bitfield.regmmx
3673 && !operand_types[0].bitfield.regxmm)
3674 || (!operand_types[t->operands > 1].bitfield.regmmx
3675 && !!operand_types[t->operands > 1].bitfield.regxmm)))
3676 continue;
3677
29b0f896 3678 /* Do not verify operands when there are none. */
50aecf8c 3679 else
29b0f896 3680 {
c6fb90c8 3681 if (!t->operands)
2dbab7d5
L		 3682 /* We've found a match; break out of loop. */
3683 break;
29b0f896 3684 }
252b5132 3685
539e75ad
L		 3686 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3687 into Disp32/Disp16/Disp32 operand. */
3688 if (i.prefix[ADDR_PREFIX] != 0)
3689 {
40fb9820 3690 /* There should be only one Disp operand. */
539e75ad
L		 3691 switch (flag_code)
3692 {
3693 case CODE_16BIT:
40fb9820
L		 3694 for (j = 0; j < MAX_OPERANDS; j++)
3695 {
3696 if (operand_types[j].bitfield.disp16)
3697 {
3698 addr_prefix_disp = j;
3699 operand_types[j].bitfield.disp32 = 1;
3700 operand_types[j].bitfield.disp16 = 0;
3701 break;
3702 }
3703 }
539e75ad
L		 3704 break;
3705 case CODE_32BIT:
40fb9820
L		 3706 for (j = 0; j < MAX_OPERANDS; j++)
3707 {
3708 if (operand_types[j].bitfield.disp32)
3709 {
3710 addr_prefix_disp = j;
3711 operand_types[j].bitfield.disp32 = 0;
3712 operand_types[j].bitfield.disp16 = 1;
3713 break;
3714 }
3715 }
539e75ad
L		 3716 break;
3717 case CODE_64BIT:
40fb9820
L		 3718 for (j = 0; j < MAX_OPERANDS; j++)
3719 {
3720 if (operand_types[j].bitfield.disp64)
3721 {
3722 addr_prefix_disp = j;
3723 operand_types[j].bitfield.disp64 = 0;
3724 operand_types[j].bitfield.disp32 = 1;
3725 break;
3726 }
3727 }
539e75ad
L		 3728 break;
3729 }
539e75ad
L		 3730 }
3731
45664ddb
L		 3732 /* We check register size only if size of operands can be
3733 encoded the canonical way. */
3734 check_register = t->opcode_modifier.w;
c6fb90c8 3735 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3736 switch (t->operands)
3737 {
3738 case 1:
40fb9820 3739 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3740 continue;
3741 break;
3742 case 2:
8b38ad71
L		 3743 /* xchg %eax, %eax is a special case. It is an aliase for nop
3744 only in 32bit mode and we can use opcode 0x90. In 64bit
3745 mode, we can't use 0x90 for xchg %eax, %eax since it should
3746 zero-extend %eax to %rax. */
3747 if (flag_code == CODE_64BIT
3748 && t->base_opcode == 0x90
0dfbf9d7
L		 3749 && operand_type_equal (&i.types [0], &acc32)
3750 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 3751 continue;
b6169b20
L		 3752 if (i.swap_operand)
3753 {
3754 /* If we swap operand in encoding, we either match
3755 the next one or reverse direction of operands. */
3756 if (t->opcode_modifier.s)
3757 continue;
3758 else if (t->opcode_modifier.d)
3759 goto check_reverse;
3760 }
3761
29b0f896 3762 case 3:
fa99fab2
L		 3763 /* If we swap operand in encoding, we match the next one. */
3764 if (i.swap_operand && t->opcode_modifier.s)
3765 continue;
f48ff2ae 3766 case 4:
c0f3af97 3767 case 5:
c6fb90c8 3768 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 3769 if (!operand_type_match (overlap0, i.types[0])
3770 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3771 || (check_register
3772 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 3773 operand_types[0],
3774 overlap1, i.types[1],
3775 operand_types[1])))
29b0f896
AM		 3776 {
3777 /* Check if other direction is valid ... */
40fb9820 3778 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 3779 continue;
3780
b6169b20 3781check_reverse:
29b0f896 3782 /* Try reversing direction of operands. */
c6fb90c8
L		 3783 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3784 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 3785 if (!operand_type_match (overlap0, i.types[0])
3786 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3787 || (check_register
3788 && !operand_type_register_match (overlap0,
3789 i.types[0],
3790 operand_types[1],
3791 overlap1,
3792 i.types[1],
3793 operand_types[0])))
29b0f896
AM		 3794 {
3795 /* Does not match either direction. */
3796 continue;
3797 }
3798 /* found_reverse_match holds which of D or FloatDR
3799 we've found. */
40fb9820 3800 if (t->opcode_modifier.d)
8a2ed489 3801 found_reverse_match = Opcode_D;
40fb9820 3802 else if (t->opcode_modifier.floatd)
8a2ed489
L		 3803 found_reverse_match = Opcode_FloatD;
3804 else
3805 found_reverse_match = 0;
40fb9820 3806 if (t->opcode_modifier.floatr)
8a2ed489 3807 found_reverse_match |= Opcode_FloatR;
29b0f896 3808 }
f48ff2ae 3809 else
29b0f896 3810 {
f48ff2ae 3811 /* Found a forward 2 operand match here. */
d1cbb4db
L		 3812 switch (t->operands)
3813 {
c0f3af97
L		 3814 case 5:
3815 overlap4 = operand_type_and (i.types[4],
3816 operand_types[4]);
d1cbb4db 3817 case 4:
c6fb90c8
L		 3818 overlap3 = operand_type_and (i.types[3],
3819 operand_types[3]);
d1cbb4db 3820 case 3:
c6fb90c8
L		 3821 overlap2 = operand_type_and (i.types[2],
3822 operand_types[2]);
d1cbb4db
L		 3823 break;
3824 }
29b0f896 3825
f48ff2ae
L		 3826 switch (t->operands)
3827 {
c0f3af97
L		 3828 case 5:
3829 if (!operand_type_match (overlap4, i.types[4])
3830 || !operand_type_register_match (overlap3,
3831 i.types[3],
3832 operand_types[3],
3833 overlap4,
3834 i.types[4],
3835 operand_types[4]))
3836 continue;
f48ff2ae 3837 case 4:
40fb9820 3838 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 3839 || (check_register
3840 && !operand_type_register_match (overlap2,
3841 i.types[2],
3842 operand_types[2],
3843 overlap3,
3844 i.types[3],
3845 operand_types[3])))
f48ff2ae
L		 3846 continue;
3847 case 3:
3848 /* Here we make use of the fact that there are no
3849 reverse match 3 operand instructions, and all 3
3850 operand instructions only need to be checked for
3851 register consistency between operands 2 and 3. */
40fb9820 3852 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 3853 || (check_register
3854 && !operand_type_register_match (overlap1,
3855 i.types[1],
3856 operand_types[1],
3857 overlap2,
3858 i.types[2],
3859 operand_types[2])))
f48ff2ae
L		 3860 continue;
3861 break;
3862 }
29b0f896 3863 }
f48ff2ae 3864 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 3865 slip through to break. */
3866 }
3629bb00 3867 if (!found_cpu_match)
29b0f896
AM		 3868 {
3869 found_reverse_match = 0;
3870 continue;
3871 }
c0f3af97 3872
29b0f896
AM		 3873 /* We've found a match; break out of loop. */
3874 break;
3875 }
3876
3877 if (t == current_templates->end)
3878 {
3879 /* We found no match. */
95f283e8
L		 3880 if (intel_syntax)
3881 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
3882 current_templates->start->name);
3883 else
3884 as_bad (_("suffix or operands invalid for `%s'"),
3885 current_templates->start->name);
fa99fab2 3886 return NULL;
29b0f896 3887 }
252b5132 3888
29b0f896
AM		 3889 if (!quiet_warnings)
3890 {
3891 if (!intel_syntax
40fb9820
L		 3892 && (i.types[0].bitfield.jumpabsolute
3893 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 3894 {
3895 as_warn (_("indirect %s without `*'"), t->name);
3896 }
3897
40fb9820
L		 3898 if (t->opcode_modifier.isprefix
3899 && t->opcode_modifier.ignoresize)
29b0f896
AM		 3900 {
3901 /* Warn them that a data or address size prefix doesn't
3902 affect assembly of the next line of code. */
3903 as_warn (_("stand-alone `%s' prefix"), t->name);
3904 }
3905 }
3906
3907 /* Copy the template we found. */
3908 i.tm = *t;
539e75ad
L		 3909
3910 if (addr_prefix_disp != -1)
3911 i.tm.operand_types[addr_prefix_disp]
3912 = operand_types[addr_prefix_disp];
3913
29b0f896
AM		 3914 if (found_reverse_match)
3915 {
3916 /* If we found a reverse match we must alter the opcode
3917 direction bit. found_reverse_match holds bits to change
3918 (different for int & float insns). */
3919
3920 i.tm.base_opcode ^= found_reverse_match;
3921
539e75ad
L		 3922 i.tm.operand_types[0] = operand_types[1];
3923 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 3924 }
3925
fa99fab2 3926 return t;
29b0f896
AM		 3927}
3928
3929static int
e3bb37b5 3930check_string (void)
29b0f896 3931{
40fb9820
L		 3932 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3933 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 3934 {
3935 if (i.seg[0] != NULL && i.seg[0] != &es)
3936 {
a87af027 3937 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 3938 i.tm.name,
a87af027
JB		 3939 mem_op + 1,
3940 register_prefix);
29b0f896
AM		 3941 return 0;
3942 }
3943 /* There's only ever one segment override allowed per instruction.
3944 This instruction possibly has a legal segment override on the
3945 second operand, so copy the segment to where non-string
3946 instructions store it, allowing common code. */
3947 i.seg[0] = i.seg[1];
3948 }
40fb9820 3949 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 3950 {
3951 if (i.seg[1] != NULL && i.seg[1] != &es)
3952 {
a87af027 3953 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 3954 i.tm.name,
a87af027
JB		 3955 mem_op + 2,
3956 register_prefix);
29b0f896
AM		 3957 return 0;
3958 }
3959 }
3960 return 1;
3961}
3962
3963static int
543613e9 3964process_suffix (void)
29b0f896
AM		 3965{
3966 /* If matched instruction specifies an explicit instruction mnemonic
3967 suffix, use it. */
40fb9820
L		 3968 if (i.tm.opcode_modifier.size16)
3969 i.suffix = WORD_MNEM_SUFFIX;
3970 else if (i.tm.opcode_modifier.size32)
3971 i.suffix = LONG_MNEM_SUFFIX;
3972 else if (i.tm.opcode_modifier.size64)
3973 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 3974 else if (i.reg_operands)
3975 {
3976 /* If there's no instruction mnemonic suffix we try to invent one
3977 based on register operands. */
3978 if (!i.suffix)
3979 {
3980 /* We take i.suffix from the last register operand specified,
3981 Destination register type is more significant than source
381d071f
L		 3982 register type. crc32 in SSE4.2 prefers source register
3983 type. */
3984 if (i.tm.base_opcode == 0xf20f38f1)
3985 {
40fb9820
L		 3986 if (i.types[0].bitfield.reg16)
3987 i.suffix = WORD_MNEM_SUFFIX;
3988 else if (i.types[0].bitfield.reg32)
3989 i.suffix = LONG_MNEM_SUFFIX;
3990 else if (i.types[0].bitfield.reg64)
3991 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 3992 }
9344ff29 3993 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 3994 {
40fb9820 3995 if (i.types[0].bitfield.reg8)
20592a94
L		 3996 i.suffix = BYTE_MNEM_SUFFIX;
3997 }
381d071f
L		 3998
3999 if (!i.suffix)
4000 {
4001 int op;
4002
20592a94
L		 4003 if (i.tm.base_opcode == 0xf20f38f1
4004 || i.tm.base_opcode == 0xf20f38f0)
4005 {
4006 /* We have to know the operand size for crc32. */
4007 as_bad (_("ambiguous memory operand size for `%s`"),
4008 i.tm.name);
4009 return 0;
4010 }
4011
381d071f 4012 for (op = i.operands; --op >= 0;)
40fb9820 4013 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 4014 {
40fb9820
L		 4015 if (i.types[op].bitfield.reg8)
4016 {
4017 i.suffix = BYTE_MNEM_SUFFIX;
4018 break;
4019 }
4020 else if (i.types[op].bitfield.reg16)
4021 {
4022 i.suffix = WORD_MNEM_SUFFIX;
4023 break;
4024 }
4025 else if (i.types[op].bitfield.reg32)
4026 {
4027 i.suffix = LONG_MNEM_SUFFIX;
4028 break;
4029 }
4030 else if (i.types[op].bitfield.reg64)
4031 {
4032 i.suffix = QWORD_MNEM_SUFFIX;
4033 break;
4034 }
381d071f
L		 4035 }
4036 }
29b0f896
AM		 4037 }
4038 else if (i.suffix == BYTE_MNEM_SUFFIX)
4039 {
4040 if (!check_byte_reg ())
4041 return 0;
4042 }
4043 else if (i.suffix == LONG_MNEM_SUFFIX)
4044 {
4045 if (!check_long_reg ())
4046 return 0;
4047 }
4048 else if (i.suffix == QWORD_MNEM_SUFFIX)
4049 {
955e1e6a
L		 4050 if (intel_syntax
4051 && i.tm.opcode_modifier.ignoresize
4052 && i.tm.opcode_modifier.no_qsuf)
4053 i.suffix = 0;
4054 else if (!check_qword_reg ())
29b0f896
AM		 4055 return 0;
4056 }
4057 else if (i.suffix == WORD_MNEM_SUFFIX)
4058 {
4059 if (!check_word_reg ())
4060 return 0;
4061 }
c0f3af97
L		 4062 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4063 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 4064 {
c0f3af97 4065 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 4066 should check if it is a valid suffix. */
4067 }
40fb9820 4068 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 4069 /* Do nothing if the instruction is going to ignore the prefix. */
4070 ;
4071 else
4072 abort ();
4073 }
40fb9820 4074 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 4075 && !i.suffix
4076 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 4077 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 4078 {
4079 i.suffix = stackop_size;
4080 }
9306ca4a
JB		 4081 else if (intel_syntax
4082 && !i.suffix
40fb9820
L		 4083 && (i.tm.operand_types[0].bitfield.jumpabsolute
4084 || i.tm.opcode_modifier.jumpbyte
4085 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 4086 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4087 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 4088 {
4089 switch (flag_code)
4090 {
4091 case CODE_64BIT:
40fb9820 4092 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 4093 {
4094 i.suffix = QWORD_MNEM_SUFFIX;
4095 break;
4096 }
4097 case CODE_32BIT:
40fb9820 4098 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 4099 i.suffix = LONG_MNEM_SUFFIX;
4100 break;
4101 case CODE_16BIT:
40fb9820 4102 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 4103 i.suffix = WORD_MNEM_SUFFIX;
4104 break;
4105 }
4106 }
252b5132 4107
9306ca4a 4108 if (!i.suffix)
29b0f896 4109 {
9306ca4a
JB		 4110 if (!intel_syntax)
4111 {
40fb9820 4112 if (i.tm.opcode_modifier.w)
9306ca4a 4113 {
4eed87de
AM		 4114 as_bad (_("no instruction mnemonic suffix given and "
4115 "no register operands; can't size instruction"));
9306ca4a
JB		 4116 return 0;
4117 }
4118 }
4119 else
4120 {
40fb9820
L		 4121 unsigned int suffixes;
4122
4123 suffixes = !i.tm.opcode_modifier.no_bsuf;
4124 if (!i.tm.opcode_modifier.no_wsuf)
4125 suffixes |= 1 << 1;
4126 if (!i.tm.opcode_modifier.no_lsuf)
4127 suffixes |= 1 << 2;
fc4adea1 4128 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 4129 suffixes |= 1 << 3;
4130 if (!i.tm.opcode_modifier.no_ssuf)
4131 suffixes |= 1 << 4;
4132 if (!i.tm.opcode_modifier.no_qsuf)
4133 suffixes |= 1 << 5;
4134
4135 /* There are more than suffix matches. */
4136 if (i.tm.opcode_modifier.w
9306ca4a 4137 || ((suffixes & (suffixes - 1))
40fb9820
L		 4138 && !i.tm.opcode_modifier.defaultsize
4139 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 4140 {
4141 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4142 return 0;
4143 }
4144 }
29b0f896 4145 }
252b5132 4146
9306ca4a
JB		 4147 /* Change the opcode based on the operand size given by i.suffix;
4148 We don't need to change things for byte insns. */
4149
582d5edd
L		 4150 if (i.suffix
4151 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 4152 && i.suffix != XMMWORD_MNEM_SUFFIX
4153 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 4154 {
4155 /* It's not a byte, select word/dword operation. */
40fb9820 4156 if (i.tm.opcode_modifier.w)
29b0f896 4157 {
40fb9820 4158 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4159 i.tm.base_opcode |= 8;
4160 else
4161 i.tm.base_opcode |= 1;
4162 }
0f3f3d8b 4163
29b0f896
AM		 4164 /* Now select between word & dword operations via the operand
4165 size prefix, except for instructions that will ignore this
4166 prefix anyway. */
ca61edf2 4167 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4168 {
ca61edf2
L		 4169 /* The address size override prefix changes the size of the
4170 first operand. */
40fb9820
L		 4171 if ((flag_code == CODE_32BIT
4172 && i.op->regs[0].reg_type.bitfield.reg16)
4173 || (flag_code != CODE_32BIT
4174 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4175 if (!add_prefix (ADDR_PREFIX_OPCODE))
4176 return 0;
4177 }
4178 else if (i.suffix != QWORD_MNEM_SUFFIX
4179 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4180 && !i.tm.opcode_modifier.ignoresize
4181 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4182 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4183 || (flag_code == CODE_64BIT
40fb9820 4184 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4185 {
4186 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4187
40fb9820 4188 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4189 prefix = ADDR_PREFIX_OPCODE;
252b5132 4190
29b0f896
AM		 4191 if (!add_prefix (prefix))
4192 return 0;
24eab124 4193 }
252b5132 4194
29b0f896
AM		 4195 /* Set mode64 for an operand. */
4196 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4197 && flag_code == CODE_64BIT
40fb9820 4198 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4199 {
4200 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4201 need rex64. cmpxchg8b is also a special case. */
4202 if (! (i.operands == 2
4203 && i.tm.base_opcode == 0x90
4204 && i.tm.extension_opcode == None
0dfbf9d7
L		 4205 && operand_type_equal (&i.types [0], &acc64)
4206 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4207 && ! (i.operands == 1
4208 && i.tm.base_opcode == 0xfc7
4209 && i.tm.extension_opcode == 1
40fb9820
L		 4210 && !operand_type_check (i.types [0], reg)
4211 && operand_type_check (i.types [0], anymem)))
f6bee062 4212 i.rex |= REX_W;
46e883c5 4213 }
3e73aa7c 4214
29b0f896
AM		 4215 /* Size floating point instruction. */
4216 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4217 if (i.tm.opcode_modifier.floatmf)
543613e9 4218 i.tm.base_opcode ^= 4;
29b0f896 4219 }
7ecd2f8b 4220
29b0f896
AM		 4221 return 1;
4222}
3e73aa7c 4223
29b0f896 4224static int
543613e9 4225check_byte_reg (void)
29b0f896
AM		 4226{
4227 int op;
543613e9 4228
29b0f896
AM		 4229 for (op = i.operands; --op >= 0;)
4230 {
4231 /* If this is an eight bit register, it's OK. If it's the 16 or
4232 32 bit version of an eight bit register, we will just use the
4233 low portion, and that's OK too. */
40fb9820 4234 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4235 continue;
4236
ca61edf2
L		 4237 /* Don't generate this warning if not needed. */
4238 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
29b0f896
AM		 4239 continue;
4240
9344ff29
L		 4241 /* crc32 doesn't generate this warning. */
4242 if (i.tm.base_opcode == 0xf20f38f0)
4243 continue;
4244
40fb9820
L		 4245 if ((i.types[op].bitfield.reg16
4246 || i.types[op].bitfield.reg32
4247 || i.types[op].bitfield.reg64)
4248 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 4249 {
4250 /* Prohibit these changes in the 64bit mode, since the
4251 lowering is more complicated. */
4252 if (flag_code == CODE_64BIT
40fb9820 4253 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 4254 {
2ca3ace5
L		 4255 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4256 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4257 i.suffix);
4258 return 0;
4259 }
4260#if REGISTER_WARNINGS
4261 if (!quiet_warnings
40fb9820 4262 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 4263 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4264 register_prefix,
40fb9820 4265 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4266 ? REGNAM_AL - REGNAM_AX
4267 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4268 register_prefix,
29b0f896
AM		 4269 i.op[op].regs->reg_name,
4270 i.suffix);
4271#endif
4272 continue;
4273 }
4274 /* Any other register is bad. */
40fb9820
L		 4275 if (i.types[op].bitfield.reg16
4276 || i.types[op].bitfield.reg32
4277 || i.types[op].bitfield.reg64
4278 || i.types[op].bitfield.regmmx
4279 || i.types[op].bitfield.regxmm
c0f3af97 4280 || i.types[op].bitfield.regymm
40fb9820
L		 4281 || i.types[op].bitfield.sreg2
4282 || i.types[op].bitfield.sreg3
4283 || i.types[op].bitfield.control
4284 || i.types[op].bitfield.debug
4285 || i.types[op].bitfield.test
4286 || i.types[op].bitfield.floatreg
4287 || i.types[op].bitfield.floatacc)
29b0f896 4288 {
a540244d
L		 4289 as_bad (_("`%s%s' not allowed with `%s%c'"),
4290 register_prefix,
29b0f896
AM		 4291 i.op[op].regs->reg_name,
4292 i.tm.name,
4293 i.suffix);
4294 return 0;
4295 }
4296 }
4297 return 1;
4298}
4299
4300static int
e3bb37b5 4301check_long_reg (void)
29b0f896
AM		 4302{
4303 int op;
4304
4305 for (op = i.operands; --op >= 0;)
4306 /* Reject eight bit registers, except where the template requires
4307 them. (eg. movzb) */
40fb9820
L		 4308 if (i.types[op].bitfield.reg8
4309 && (i.tm.operand_types[op].bitfield.reg16
4310 || i.tm.operand_types[op].bitfield.reg32
4311 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4312 {
a540244d
L		 4313 as_bad (_("`%s%s' not allowed with `%s%c'"),
4314 register_prefix,
29b0f896
AM		 4315 i.op[op].regs->reg_name,
4316 i.tm.name,
4317 i.suffix);
4318 return 0;
4319 }
4320 /* Warn if the e prefix on a general reg is missing. */
4321 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4322 && i.types[op].bitfield.reg16
4323 && (i.tm.operand_types[op].bitfield.reg32
4324 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4325 {
4326 /* Prohibit these changes in the 64bit mode, since the
4327 lowering is more complicated. */
4328 if (flag_code == CODE_64BIT)
252b5132 4329 {
2ca3ace5
L		 4330 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4331 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4332 i.suffix);
4333 return 0;
252b5132 4334 }
29b0f896
AM		 4335#if REGISTER_WARNINGS
4336 else
a540244d
L		 4337 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4338 register_prefix,
29b0f896 4339 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4340 register_prefix,
29b0f896
AM		 4341 i.op[op].regs->reg_name,
4342 i.suffix);
4343#endif
252b5132 4344 }
29b0f896 4345 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4346 else if (i.types[op].bitfield.reg64
4347 && (i.tm.operand_types[op].bitfield.reg32
4348 || i.tm.operand_types[op].bitfield.acc))
252b5132 4349 {
34828aad 4350 if (intel_syntax
ca61edf2 4351 && i.tm.opcode_modifier.toqword
40fb9820 4352 && !i.types[0].bitfield.regxmm)
34828aad 4353 {
ca61edf2 4354 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4355 i.suffix = QWORD_MNEM_SUFFIX;
4356 }
4357 else
4358 {
4359 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4360 register_prefix, i.op[op].regs->reg_name,
4361 i.suffix);
4362 return 0;
4363 }
29b0f896
AM		 4364 }
4365 return 1;
4366}
252b5132 4367
29b0f896 4368static int
e3bb37b5 4369check_qword_reg (void)
29b0f896
AM		 4370{
4371 int op;
252b5132 4372
29b0f896
AM		 4373 for (op = i.operands; --op >= 0; )
4374 /* Reject eight bit registers, except where the template requires
4375 them. (eg. movzb) */
40fb9820
L		 4376 if (i.types[op].bitfield.reg8
4377 && (i.tm.operand_types[op].bitfield.reg16
4378 || i.tm.operand_types[op].bitfield.reg32
4379 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4380 {
a540244d
L		 4381 as_bad (_("`%s%s' not allowed with `%s%c'"),
4382 register_prefix,
29b0f896
AM		 4383 i.op[op].regs->reg_name,
4384 i.tm.name,
4385 i.suffix);
4386 return 0;
4387 }
4388 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4389 else if ((i.types[op].bitfield.reg16
4390 || i.types[op].bitfield.reg32)
4391 && (i.tm.operand_types[op].bitfield.reg32
4392 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4393 {
4394 /* Prohibit these changes in the 64bit mode, since the
4395 lowering is more complicated. */
34828aad 4396 if (intel_syntax
ca61edf2 4397 && i.tm.opcode_modifier.todword
40fb9820 4398 && !i.types[0].bitfield.regxmm)
34828aad 4399 {
ca61edf2 4400 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4401 i.suffix = LONG_MNEM_SUFFIX;
4402 }
4403 else
4404 {
4405 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4406 register_prefix, i.op[op].regs->reg_name,
4407 i.suffix);
4408 return 0;
4409 }
252b5132 4410 }
29b0f896
AM		 4411 return 1;
4412}
252b5132 4413
29b0f896 4414static int
e3bb37b5 4415check_word_reg (void)
29b0f896
AM		 4416{
4417 int op;
4418 for (op = i.operands; --op >= 0;)
4419 /* Reject eight bit registers, except where the template requires
4420 them. (eg. movzb) */
40fb9820
L		 4421 if (i.types[op].bitfield.reg8
4422 && (i.tm.operand_types[op].bitfield.reg16
4423 || i.tm.operand_types[op].bitfield.reg32
4424 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4425 {
a540244d
L		 4426 as_bad (_("`%s%s' not allowed with `%s%c'"),
4427 register_prefix,
29b0f896
AM		 4428 i.op[op].regs->reg_name,
4429 i.tm.name,
4430 i.suffix);
4431 return 0;
4432 }
4433 /* Warn if the e prefix on a general reg is present. */
4434 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4435 && i.types[op].bitfield.reg32
4436 && (i.tm.operand_types[op].bitfield.reg16
4437 || i.tm.operand_types[op].bitfield.acc))
252b5132 4438 {
29b0f896
AM		 4439 /* Prohibit these changes in the 64bit mode, since the
4440 lowering is more complicated. */
4441 if (flag_code == CODE_64BIT)
252b5132 4442 {
2ca3ace5
L		 4443 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4444 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4445 i.suffix);
4446 return 0;
252b5132 4447 }
29b0f896
AM		 4448 else
4449#if REGISTER_WARNINGS
a540244d
L		 4450 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4451 register_prefix,
29b0f896 4452 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4453 register_prefix,
29b0f896
AM		 4454 i.op[op].regs->reg_name,
4455 i.suffix);
4456#endif
4457 }
4458 return 1;
4459}
252b5132 4460
29b0f896 4461static int
40fb9820 4462update_imm (unsigned int j)
29b0f896 4463{
40fb9820
L		 4464 i386_operand_type overlap;
4465
c6fb90c8 4466 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
40fb9820
L		 4467 if ((overlap.bitfield.imm8
4468 || overlap.bitfield.imm8s
4469 || overlap.bitfield.imm16
4470 || overlap.bitfield.imm32
4471 || overlap.bitfield.imm32s
4472 || overlap.bitfield.imm64)
0dfbf9d7
L		 4473 && !operand_type_equal (&overlap, &imm8)
4474 && !operand_type_equal (&overlap, &imm8s)
4475 && !operand_type_equal (&overlap, &imm16)
4476 && !operand_type_equal (&overlap, &imm32)
4477 && !operand_type_equal (&overlap, &imm32s)
4478 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 4479 {
4480 if (i.suffix)
4481 {
40fb9820
L		 4482 i386_operand_type temp;
4483
0dfbf9d7 4484 operand_type_set (&temp, 0);
40fb9820
L		 4485 if (i.suffix == BYTE_MNEM_SUFFIX)
4486 {
4487 temp.bitfield.imm8 = overlap.bitfield.imm8;
4488 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4489 }
4490 else if (i.suffix == WORD_MNEM_SUFFIX)
4491 temp.bitfield.imm16 = overlap.bitfield.imm16;
4492 else if (i.suffix == QWORD_MNEM_SUFFIX)
4493 {
4494 temp.bitfield.imm64 = overlap.bitfield.imm64;
4495 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4496 }
4497 else
4498 temp.bitfield.imm32 = overlap.bitfield.imm32;
4499 overlap = temp;
29b0f896 4500 }
0dfbf9d7
L		 4501 else if (operand_type_equal (&overlap, &imm16_32_32s)
4502 || operand_type_equal (&overlap, &imm16_32)
4503 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 4504 {
40fb9820 4505 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 4506 overlap = imm16;
40fb9820 4507 else
65da13b5 4508 overlap = imm32s;
29b0f896 4509 }
0dfbf9d7
L		 4510 if (!operand_type_equal (&overlap, &imm8)
4511 && !operand_type_equal (&overlap, &imm8s)
4512 && !operand_type_equal (&overlap, &imm16)
4513 && !operand_type_equal (&overlap, &imm32)
4514 && !operand_type_equal (&overlap, &imm32s)
4515 && !operand_type_equal (&overlap, &imm64))
29b0f896 4516 {
4eed87de
AM		 4517 as_bad (_("no instruction mnemonic suffix given; "
4518 "can't determine immediate size"));
29b0f896
AM		 4519 return 0;
4520 }
4521 }
40fb9820 4522 i.types[j] = overlap;
29b0f896 4523
40fb9820
L		 4524 return 1;
4525}
4526
4527static int
4528finalize_imm (void)
4529{
4530 unsigned int j;
29b0f896 4531
40fb9820
L		 4532 for (j = 0; j < 2; j++)
4533 if (update_imm (j) == 0)
4534 return 0;
4535
c6fb90c8 4536 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
40fb9820 4537 assert (operand_type_check (i.types[2], imm) == 0);
29b0f896
AM		 4538
4539 return 1;
4540}
4541
85f10a01
MM		 4542static void
4543process_drex (void)
4544{
5dd15031
JJ		 4545 i.drex.modrm_reg = 0;
4546 i.drex.modrm_regmem = 0;
85f10a01
MM		 4547
4548 /* SSE5 4 operand instructions must have the destination the same as
4549 one of the inputs. Figure out the destination register and cache
4550 it away in the drex field, and remember which fields to use for
4551 the modrm byte. */
4552 if (i.tm.opcode_modifier.drex
4553 && i.tm.opcode_modifier.drexv
4554 && i.operands == 4)
4555 {
4556 i.tm.extension_opcode = None;
4557
4558 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
4559 if (i.types[0].bitfield.regxmm != 0
4560 && i.types[1].bitfield.regxmm != 0
4561 && i.types[2].bitfield.regxmm != 0
4562 && i.types[3].bitfield.regxmm != 0
4563 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4564 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4565 {
4566 /* Clear the arguments that are stored in drex. */
0dfbf9d7
L		 4567 operand_type_set (&i.types[0], 0);
4568 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4569 i.reg_operands -= 2;
4570
4571 /* There are two different ways to encode a 4 operand
4572 instruction with all registers that uses OC1 set to
4573 0 or 1. Favor setting OC1 to 0 since this mimics the
4574 actions of other SSE5 assemblers. Use modrm encoding 2
4575 for register/register. Include the high order bit that
4576 is normally stored in the REX byte in the register
4577 field. */
4578 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4579 i.drex.modrm_reg = 2;
4580 i.drex.modrm_regmem = 1;
4581 i.drex.reg = (i.op[3].regs->reg_num
4582 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4583 }
4584
4585 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
4586 else if (i.types[0].bitfield.regxmm != 0
4587 && i.types[1].bitfield.regxmm != 0
4588 && (i.types[2].bitfield.regxmm
4589 || operand_type_check (i.types[2], anymem))
4590 && i.types[3].bitfield.regxmm != 0
4591 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4592 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4593 {
4594 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4595 operand_type_set (&i.types[0], 0);
4596 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4597 i.reg_operands -= 2;
4598
4599 /* Specify the modrm encoding for memory addressing. Include
4600 the high order bit that is normally stored in the REX byte
4601 in the register field. */
4602 i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
4603 i.drex.modrm_reg = 1;
4604 i.drex.modrm_regmem = 2;
4605 i.drex.reg = (i.op[3].regs->reg_num
4606 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4607 }
4608
4609 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
4610 else if (i.types[0].bitfield.regxmm != 0
4611 && operand_type_check (i.types[1], anymem) != 0
4612 && i.types[2].bitfield.regxmm != 0
4613 && i.types[3].bitfield.regxmm != 0
4614 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4615 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4616 {
4617 /* Clear the arguments that are stored in drex. */
0dfbf9d7
L		 4618 operand_type_set (&i.types[0], 0);
4619 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4620 i.reg_operands -= 2;
4621
4622 /* Specify the modrm encoding for memory addressing. Include
4623 the high order bit that is normally stored in the REX byte
4624 in the register field. */
4625 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4626 i.drex.modrm_reg = 2;
4627 i.drex.modrm_regmem = 1;
4628 i.drex.reg = (i.op[3].regs->reg_num
4629 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4630 }
4631
4632 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4633 else if (i.types[0].bitfield.regxmm != 0
4634 && i.types[1].bitfield.regxmm != 0
4635 && i.types[2].bitfield.regxmm != 0
4636 && i.types[3].bitfield.regxmm != 0
4637 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4638 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4639 {
4640 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4641 operand_type_set (&i.types[2], 0);
4642 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4643 i.reg_operands -= 2;
4644
4645 /* There are two different ways to encode a 4 operand
4646 instruction with all registers that uses OC1 set to
4647 0 or 1. Favor setting OC1 to 0 since this mimics the
4648 actions of other SSE5 assemblers. Use modrm encoding
4649 2 for register/register. Include the high order bit that
4650 is normally stored in the REX byte in the register
4651 field. */
4652 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4653 i.drex.modrm_reg = 1;
4654 i.drex.modrm_regmem = 0;
4655
4656 /* Remember the register, including the upper bits */
4657 i.drex.reg = (i.op[3].regs->reg_num
4658 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4659 }
4660
4661 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4662 else if (i.types[0].bitfield.regxmm != 0
4663 && (i.types[1].bitfield.regxmm
4664 || operand_type_check (i.types[1], anymem))
4665 && i.types[2].bitfield.regxmm != 0
4666 && i.types[3].bitfield.regxmm != 0
4667 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4668 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4669 {
4670 /* Clear the arguments that are stored in drex. */
0dfbf9d7
L		 4671 operand_type_set (&i.types[2], 0);
4672 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4673 i.reg_operands -= 2;
4674
4675 /* Specify the modrm encoding and remember the register
4676 including the bits normally stored in the REX byte. */
4677 i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
4678 i.drex.modrm_reg = 0;
4679 i.drex.modrm_regmem = 1;
4680 i.drex.reg = (i.op[3].regs->reg_num
4681 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4682 }
4683
4684 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4685 else if (operand_type_check (i.types[0], anymem) != 0
4686 && i.types[1].bitfield.regxmm != 0
4687 && i.types[2].bitfield.regxmm != 0
4688 && i.types[3].bitfield.regxmm != 0
4689 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4690 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4691 {
4692 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4693 operand_type_set (&i.types[2], 0);
4694 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4695 i.reg_operands -= 2;
4696
4697 /* Specify the modrm encoding and remember the register
4698 including the bits normally stored in the REX byte. */
4699 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4700 i.drex.modrm_reg = 1;
4701 i.drex.modrm_regmem = 0;
4702 i.drex.reg = (i.op[3].regs->reg_num
4703 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4704 }
4705
4706 else
4707 as_bad (_("Incorrect operands for the '%s' instruction"),
4708 i.tm.name);
4709 }
4710
4711 /* SSE5 instructions with the DREX byte where the only memory operand
4712 is in the 2nd argument, and the first and last xmm register must
4713 match, and is encoded in the DREX byte. */
4714 else if (i.tm.opcode_modifier.drex
4715 && !i.tm.opcode_modifier.drexv
4716 && i.operands == 4)
4717 {
4718 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4719 if (i.types[0].bitfield.regxmm != 0
4720 && (i.types[1].bitfield.regxmm
4721 || operand_type_check(i.types[1], anymem))
4722 && i.types[2].bitfield.regxmm != 0
4723 && i.types[3].bitfield.regxmm != 0
4724 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4725 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4726 {
4727 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4728 operand_type_set (&i.types[0], 0);
4729 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4730 i.reg_operands -= 2;
4731
4732 /* Specify the modrm encoding and remember the register
4733 including the high bit normally stored in the REX
4734 byte. */
4735 i.drex.modrm_reg = 2;
4736 i.drex.modrm_regmem = 1;
4737 i.drex.reg = (i.op[3].regs->reg_num
4738 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4739 }
4740
4741 else
4742 as_bad (_("Incorrect operands for the '%s' instruction"),
4743 i.tm.name);
4744 }
4745
4746 /* SSE5 3 operand instructions that the result is a register, being
4747 either operand can be a memory operand, using OC0 to note which
4748 one is the memory. */
4749 else if (i.tm.opcode_modifier.drex
4750 && i.tm.opcode_modifier.drexv
4751 && i.operands == 3)
4752 {
4753 i.tm.extension_opcode = None;
4754
4755 /* Case 1: 3 operand insn, src1 = register. */
4756 if (i.types[0].bitfield.regxmm != 0
4757 && i.types[1].bitfield.regxmm != 0
4758 && i.types[2].bitfield.regxmm != 0)
4759 {
4760 /* Clear the arguments that are stored in drex. */
0dfbf9d7 4761 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4762 i.reg_operands--;
4763
4764 /* Specify the modrm encoding and remember the register
4765 including the high bit normally stored in the REX byte. */
4766 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4767 i.drex.modrm_reg = 1;
4768 i.drex.modrm_regmem = 0;
4769 i.drex.reg = (i.op[2].regs->reg_num
4770 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4771 }
4772
4773 /* Case 2: 3 operand insn, src1 = memory. */
4774 else if (operand_type_check (i.types[0], anymem) != 0
4775 && i.types[1].bitfield.regxmm != 0
4776 && i.types[2].bitfield.regxmm != 0)
4777 {
4778 /* Clear the arguments that are stored in drex. */
0dfbf9d7 4779 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4780 i.reg_operands--;
4781
4782 /* Specify the modrm encoding and remember the register
4783 including the high bit normally stored in the REX
4784 byte. */
4785 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4786 i.drex.modrm_reg = 1;
4787 i.drex.modrm_regmem = 0;
4788 i.drex.reg = (i.op[2].regs->reg_num
4789 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4790 }
4791
4792 /* Case 3: 3 operand insn, src2 = memory. */
4793 else if (i.types[0].bitfield.regxmm != 0
4794 && operand_type_check (i.types[1], anymem) != 0
4795 && i.types[2].bitfield.regxmm != 0)
4796 {
4797 /* Clear the arguments that are stored in drex. */
0dfbf9d7 4798 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4799 i.reg_operands--;
4800
4801 /* Specify the modrm encoding and remember the register
4802 including the high bit normally stored in the REX byte. */
4803 i.tm.extension_opcode = DREX_X1_XMEM_X2;
4804 i.drex.modrm_reg = 0;
4805 i.drex.modrm_regmem = 1;
4806 i.drex.reg = (i.op[2].regs->reg_num
4807 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4808 }
4809
4810 else
4811 as_bad (_("Incorrect operands for the '%s' instruction"),
4812 i.tm.name);
4813 }
4814
4815 /* SSE5 4 operand instructions that are the comparison instructions
4816 where the first operand is the immediate value of the comparison
4817 to be done. */
4818 else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
4819 {
4820 /* Case 1: 4 operand insn, src1 = reg/memory. */
4821 if (operand_type_check (i.types[0], imm) != 0
4822 && (i.types[1].bitfield.regxmm
4823 || operand_type_check (i.types[1], anymem))
4824 && i.types[2].bitfield.regxmm != 0
4825 && i.types[3].bitfield.regxmm != 0)
4826 {
4827 /* clear the arguments that are stored in drex */
0dfbf9d7 4828 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4829 i.reg_operands--;
4830
4831 /* Specify the modrm encoding and remember the register
4832 including the high bit normally stored in the REX byte. */
4833 i.drex.modrm_reg = 2;
4834 i.drex.modrm_regmem = 1;
4835 i.drex.reg = (i.op[3].regs->reg_num
4836 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4837 }
4838
4839 /* Case 2: 3 operand insn with ImmExt that places the
4840 opcode_extension as an immediate argument. This is used for
4841 all of the varients of comparison that supplies the appropriate
4842 value as part of the instruction. */
4843 else if ((i.types[0].bitfield.regxmm
4844 || operand_type_check (i.types[0], anymem))
4845 && i.types[1].bitfield.regxmm != 0
4846 && i.types[2].bitfield.regxmm != 0
4847 && operand_type_check (i.types[3], imm) != 0)
4848 {
4849 /* clear the arguments that are stored in drex */
0dfbf9d7 4850 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4851 i.reg_operands--;
4852
4853 /* Specify the modrm encoding and remember the register
4854 including the high bit normally stored in the REX byte. */
4855 i.drex.modrm_reg = 1;
4856 i.drex.modrm_regmem = 0;
4857 i.drex.reg = (i.op[2].regs->reg_num
4858 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4859 }
4860
4861 else
4862 as_bad (_("Incorrect operands for the '%s' instruction"),
4863 i.tm.name);
4864 }
4865
4866 else if (i.tm.opcode_modifier.drex
4867 || i.tm.opcode_modifier.drexv
4868 || i.tm.opcode_modifier.drexc)
4869 as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
4870}
4871
c0f3af97
L		 4872static int
4873bad_implicit_operand (int xmm)
4874{
4875 const char *reg = xmm ? "xmm0" : "ymm0";
4876 if (intel_syntax)
4877 as_bad (_("the last operand of `%s' must be `%s%s'"),
4878 i.tm.name, register_prefix, reg);
4879 else
4880 as_bad (_("the first operand of `%s' must be `%s%s'"),
4881 i.tm.name, register_prefix, reg);
4882 return 0;
4883}
4884
29b0f896 4885static int
e3bb37b5 4886process_operands (void)
29b0f896
AM		 4887{
4888 /* Default segment register this instruction will use for memory
4889 accesses. 0 means unknown. This is only for optimizing out
4890 unnecessary segment overrides. */
4891 const seg_entry *default_seg = 0;
4892
85f10a01
MM		 4893 /* Handle all of the DREX munging that SSE5 needs. */
4894 if (i.tm.opcode_modifier.drex
4895 || i.tm.opcode_modifier.drexv
4896 || i.tm.opcode_modifier.drexc)
4897 process_drex ();
4898
c0f3af97
L		 4899 if (i.tm.opcode_modifier.sse2avx
4900 && (i.tm.opcode_modifier.vexnds
4901 || i.tm.opcode_modifier.vexndd))
29b0f896 4902 {
c0f3af97
L		 4903 unsigned int dup = i.operands;
4904 unsigned int dest = dup - 1;
9fcfb3d7
L		 4905 unsigned int j;
4906
c0f3af97 4907 /* The destination must be an xmm register. */
0dfbf9d7 4908 assert (i.reg_operands
c0f3af97
L		 4909 && MAX_OPERANDS > dup
4910 && operand_type_equal (&i.types[dest], &regxmm));
4911
4912 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 4913 {
c0f3af97
L		 4914 /* The first operand is implicit and must be xmm0. */
4915 assert (operand_type_equal (&i.types[0], &regxmm));
4916 if (i.op[0].regs->reg_num != 0)
4917 return bad_implicit_operand (1);
4918
4919 if (i.tm.opcode_modifier.vex3sources)
4920 {
4921 /* Keep xmm0 for instructions with VEX prefix and 3
4922 sources. */
4923 goto duplicate;
4924 }
e2ec9d29 4925 else
c0f3af97
L		 4926 {
4927 /* We remove the first xmm0 and keep the number of
4928 operands unchanged, which in fact duplicates the
4929 destination. */
4930 for (j = 1; j < i.operands; j++)
4931 {
4932 i.op[j - 1] = i.op[j];
4933 i.types[j - 1] = i.types[j];
4934 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
4935 }
4936 }
4937 }
4938 else if (i.tm.opcode_modifier.implicit1stxmm0)
4939 {
4940 assert ((MAX_OPERANDS - 1) > dup
4941 && i.tm.opcode_modifier.vex3sources);
4942
4943 /* Add the implicit xmm0 for instructions with VEX prefix
4944 and 3 sources. */
4945 for (j = i.operands; j > 0; j--)
4946 {
4947 i.op[j] = i.op[j - 1];
4948 i.types[j] = i.types[j - 1];
4949 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
4950 }
4951 i.op[0].regs
4952 = (const reg_entry *) hash_find (reg_hash, "xmm0");
4953 i.types[0] = regxmm;
4954 i.tm.operand_types[0] = regxmm;
4955
4956 i.operands += 2;
4957 i.reg_operands += 2;
4958 i.tm.operands += 2;
4959
4960 dup++;
4961 dest++;
4962 i.op[dup] = i.op[dest];
4963 i.types[dup] = i.types[dest];
4964 i.tm.operand_types[dup] = i.tm.operand_types[dest];
e2ec9d29 4965 }
c0f3af97
L		 4966 else
4967 {
4968duplicate:
4969 i.operands++;
4970 i.reg_operands++;
4971 i.tm.operands++;
4972
4973 i.op[dup] = i.op[dest];
4974 i.types[dup] = i.types[dest];
4975 i.tm.operand_types[dup] = i.tm.operand_types[dest];
4976 }
4977
4978 if (i.tm.opcode_modifier.immext)
4979 process_immext ();
4980 }
4981 else if (i.tm.opcode_modifier.firstxmm0)
4982 {
4983 unsigned int j;
4984
4985 /* The first operand is implicit and must be xmm0/ymm0. */
4986 assert (i.reg_operands
4987 && (operand_type_equal (&i.types[0], &regxmm)
4988 || operand_type_equal (&i.types[0], &regymm)));
4989 if (i.op[0].regs->reg_num != 0)
4990 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 4991
4992 for (j = 1; j < i.operands; j++)
4993 {
4994 i.op[j - 1] = i.op[j];
4995 i.types[j - 1] = i.types[j];
4996
4997 /* We need to adjust fields in i.tm since they are used by
4998 build_modrm_byte. */
4999 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5000 }
5001
e2ec9d29
L		 5002 i.operands--;
5003 i.reg_operands--;
e2ec9d29
L		 5004 i.tm.operands--;
5005 }
5006 else if (i.tm.opcode_modifier.regkludge)
5007 {
5008 /* The imul $imm, %reg instruction is converted into
5009 imul $imm, %reg, %reg, and the clr %reg instruction
5010 is converted into xor %reg, %reg. */
5011
5012 unsigned int first_reg_op;
5013
5014 if (operand_type_check (i.types[0], reg))
5015 first_reg_op = 0;
5016 else
5017 first_reg_op = 1;
5018 /* Pretend we saw the extra register operand. */
5019 assert (i.reg_operands == 1
5020 && i.op[first_reg_op + 1].regs == 0);
5021 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5022 i.types[first_reg_op + 1] = i.types[first_reg_op];
5023 i.operands++;
5024 i.reg_operands++;
29b0f896
AM		 5025 }
5026
40fb9820 5027 if (i.tm.opcode_modifier.shortform)
29b0f896 5028 {
40fb9820
L		 5029 if (i.types[0].bitfield.sreg2
5030 || i.types[0].bitfield.sreg3)
29b0f896 5031 {
4eed87de
AM		 5032 if (i.tm.base_opcode == POP_SEG_SHORT
5033 && i.op[0].regs->reg_num == 1)
29b0f896 5034 {
a87af027 5035 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5036 return 0;
29b0f896 5037 }
4eed87de
AM		 5038 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5039 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5040 i.rex |= REX_B;
4eed87de
AM		 5041 }
5042 else
5043 {
85f10a01
MM		 5044 /* The register or float register operand is in operand
5045 0 or 1. */
40fb9820
L		 5046 unsigned int op;
5047
5048 if (i.types[0].bitfield.floatreg
5049 || operand_type_check (i.types[0], reg))
5050 op = 0;
5051 else
5052 op = 1;
4eed87de
AM		 5053 /* Register goes in low 3 bits of opcode. */
5054 i.tm.base_opcode |= i.op[op].regs->reg_num;
5055 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5056 i.rex |= REX_B;
40fb9820 5057 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5058 {
4eed87de
AM		 5059 /* Warn about some common errors, but press on regardless.
5060 The first case can be generated by gcc (<= 2.8.1). */
5061 if (i.operands == 2)
5062 {
5063 /* Reversed arguments on faddp, fsubp, etc. */
a540244d
L		 5064 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
5065 register_prefix, i.op[1].regs->reg_name,
5066 register_prefix, i.op[0].regs->reg_name);
4eed87de
AM		 5067 }
5068 else
5069 {
5070 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5071 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5072 register_prefix, i.op[0].regs->reg_name);
4eed87de 5073 }
29b0f896
AM		 5074 }
5075 }
5076 }
40fb9820 5077 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5078 {
5079 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5080 must be put into the modrm byte). Now, we make the modrm and
5081 index base bytes based on all the info we've collected. */
29b0f896
AM		 5082
5083 default_seg = build_modrm_byte ();
5084 }
8a2ed489 5085 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5086 {
5087 default_seg = &ds;
5088 }
40fb9820 5089 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5090 {
5091 /* For the string instructions that allow a segment override
5092 on one of their operands, the default segment is ds. */
5093 default_seg = &ds;
5094 }
5095
75178d9d
L		 5096 if (i.tm.base_opcode == 0x8d /* lea */
5097 && i.seg[0]
5098 && !quiet_warnings)
30123838 5099 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5100
5101 /* If a segment was explicitly specified, and the specified segment
5102 is not the default, use an opcode prefix to select it. If we
5103 never figured out what the default segment is, then default_seg
5104 will be zero at this point, and the specified segment prefix will
5105 always be used. */
29b0f896
AM		 5106 if ((i.seg[0]) && (i.seg[0] != default_seg))
5107 {
5108 if (!add_prefix (i.seg[0]->seg_prefix))
5109 return 0;
5110 }
5111 return 1;
5112}
5113
5114static const seg_entry *
e3bb37b5 5115build_modrm_byte (void)
29b0f896
AM		 5116{
5117 const seg_entry *default_seg = 0;
c0f3af97
L		 5118 unsigned int source, dest;
5119 int vex_3_sources;
5120
5121 /* The first operand of instructions with VEX prefix and 3 sources
5122 must be VEX_Imm4. */
5123 vex_3_sources = i.tm.opcode_modifier.vex3sources;
5124 if (vex_3_sources)
5125 {
5126 unsigned int nds, reg;
5127
0bfee649 5128 dest = i.operands - 1;
c0f3af97 5129 nds = dest - 1;
0bfee649
L		 5130 source = 1;
5131 reg = 0;
5132
5133 /* This instruction must have 4 operands: 4 register operands
5134 or 3 register operands plus 1 memory operand. It must have
5135 VexNDS and VexImmExt. */
5136 assert (i.operands == 4
5137 && (i.reg_operands == 4
5138 || (i.reg_operands == 3 && i.mem_operands == 1))
5139 && i.tm.opcode_modifier.vexnds
5140 && i.tm.opcode_modifier.veximmext
5141 && (operand_type_equal (&i.tm.operand_types[dest],
5142 &regxmm)
5143 || operand_type_equal (&i.tm.operand_types[dest],
5144 &regymm))
5145 && (operand_type_equal (&i.tm.operand_types[nds],
5146 &regxmm)
5147 || operand_type_equal (&i.tm.operand_types[nds],
5148 &regymm))
5149 && (operand_type_equal (&i.tm.operand_types[reg],
5150 &regxmm)
c0f3af97 5151 || operand_type_equal (&i.tm.operand_types[reg],
0bfee649 5152 &regymm)));
c0f3af97 5153
0bfee649
L		 5154 /* Generate an 8bit immediate operand to encode the register
5155 operand. */
5156 expressionS *exp = &im_expressions[i.imm_operands++];
5157 i.op[i.operands].imms = exp;
5158 i.types[i.operands] = imm8;
5159 i.operands++;
5160 exp->X_op = O_constant;
5161 exp->X_add_number
5162 = ((i.op[0].regs->reg_num
5163 + ((i.op[0].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
dae39acc 5164
dae39acc 5165 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 5166 }
5167 else
5168 source = dest = 0;
29b0f896 5169
85f10a01
MM		 5170 /* SSE5 4 operand instructions are encoded in such a way that one of
5171 the inputs must match the destination register. Process_drex hides
5172 the 3rd argument in the drex field, so that by the time we get
5173 here, it looks to GAS as if this is a 2 operand instruction. */
5174 if ((i.tm.opcode_modifier.drex
5175 || i.tm.opcode_modifier.drexv
b5016f89 5176 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 5177 && i.reg_operands == 2)
5178 {
5179 const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
5180 const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
5181
5182 i.rm.reg = reg->reg_num;
5183 i.rm.regmem = regmem->reg_num;
5184 i.rm.mode = 3;
5185 if ((reg->reg_flags & RegRex) != 0)
5186 i.rex |= REX_R;
5187 if ((regmem->reg_flags & RegRex) != 0)
5188 i.rex |= REX_B;
5189 }
5190
29b0f896 5191 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 5192 implicit registers do not count. If there are 3 register
5193 operands, it must be a instruction with VexNDS. For a
5194 instruction with VexNDD, the destination register is encoded
5195 in VEX prefix. If there are 4 register operands, it must be
5196 a instruction with VEX prefix and 3 sources. */
5197 else if (i.mem_operands == 0
5198 && ((i.reg_operands == 2
5199 && !i.tm.opcode_modifier.vexndd)
5200 || (i.reg_operands == 3
5201 && i.tm.opcode_modifier.vexnds)
5202 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 5203 {
cab737b9
L		 5204 switch (i.operands)
5205 {
5206 case 2:
5207 source = 0;
5208 break;
5209 case 3:
c81128dc
L		 5210 /* When there are 3 operands, one of them may be immediate,
5211 which may be the first or the last operand. Otherwise,
c0f3af97
L		 5212 the first operand must be shift count register (cl) or it
5213 is an instruction with VexNDS. */
c81128dc
L		 5214 assert (i.imm_operands == 1
5215 || (i.imm_operands == 0
c0f3af97
L		 5216 && (i.tm.opcode_modifier.vexnds
5217 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 5218 if (operand_type_check (i.types[0], imm)
5219 || i.types[0].bitfield.shiftcount)
5220 source = 1;
5221 else
5222 source = 0;
cab737b9
L		 5223 break;
5224 case 4:
368d64cc
L		 5225 /* When there are 4 operands, the first two must be 8bit
5226 immediate operands. The source operand will be the 3rd
c0f3af97
L		 5227 one.
5228
5229 For instructions with VexNDS, if the first operand
5230 an imm8, the source operand is the 2nd one. If the last
5231 operand is imm8, the source operand is the first one. */
5232 assert ((i.imm_operands == 2
5233 && i.types[0].bitfield.imm8
5234 && i.types[1].bitfield.imm8)
5235 || (i.tm.opcode_modifier.vexnds
5236 && i.imm_operands == 1
5237 && (i.types[0].bitfield.imm8
5238 || i.types[i.operands - 1].bitfield.imm8)));
5239 if (i.tm.opcode_modifier.vexnds)
5240 {
5241 if (i.types[0].bitfield.imm8)
5242 source = 1;
5243 else
5244 source = 0;
5245 }
5246 else
5247 source = 2;
5248 break;
5249 case 5:
cab737b9
L		 5250 break;
5251 default:
5252 abort ();
5253 }
5254
c0f3af97
L		 5255 if (!vex_3_sources)
5256 {
5257 dest = source + 1;
5258
5259 if (i.tm.opcode_modifier.vexnds)
5260 {
5261 /* For instructions with VexNDS, the register-only
5262 source operand must be XMM or YMM register. It is
fa99fab2
L		 5263 encoded in VEX prefix. We need to clear RegMem bit
5264 before calling operand_type_equal. */
5265 i386_operand_type op = i.tm.operand_types[dest];
5266 op.bitfield.regmem = 0;
c0f3af97 5267 if ((dest + 1) >= i.operands
fa99fab2
L		 5268 || (!operand_type_equal (&op, &regxmm)
5269 && !operand_type_equal (&op, &regymm)))
c0f3af97
L		 5270 abort ();
5271 i.vex.register_specifier = i.op[dest].regs;
5272 dest++;
5273 }
5274 }
29b0f896
AM		 5275
5276 i.rm.mode = 3;
5277 /* One of the register operands will be encoded in the i.tm.reg
5278 field, the other in the combined i.tm.mode and i.tm.regmem
5279 fields. If no form of this instruction supports a memory
5280 destination operand, then we assume the source operand may
5281 sometimes be a memory operand and so we need to store the
5282 destination in the i.rm.reg field. */
40fb9820
L		 5283 if (!i.tm.operand_types[dest].bitfield.regmem
5284 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 5285 {
5286 i.rm.reg = i.op[dest].regs->reg_num;
5287 i.rm.regmem = i.op[source].regs->reg_num;
5288 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5289 i.rex |= REX_R;
29b0f896 5290 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5291 i.rex |= REX_B;
29b0f896
AM		 5292 }
5293 else
5294 {
5295 i.rm.reg = i.op[source].regs->reg_num;
5296 i.rm.regmem = i.op[dest].regs->reg_num;
5297 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5298 i.rex |= REX_B;
29b0f896 5299 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5300 i.rex |= REX_R;
29b0f896 5301 }
161a04f6 5302 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 5303 {
40fb9820
L		 5304 if (!i.types[0].bitfield.control
5305 && !i.types[1].bitfield.control)
c4a530c5 5306 abort ();
161a04f6 5307 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 5308 add_prefix (LOCK_PREFIX_OPCODE);
5309 }
29b0f896
AM		 5310 }
5311 else
5312 { /* If it's not 2 reg operands... */
c0f3af97
L		 5313 unsigned int mem;
5314
29b0f896
AM		 5315 if (i.mem_operands)
5316 {
5317 unsigned int fake_zero_displacement = 0;
99018f42 5318 unsigned int op;
4eed87de 5319
85f10a01
MM		 5320 /* This has been precalculated for SSE5 instructions
5321 that have a DREX field earlier in process_drex. */
b5016f89
L		 5322 if (i.tm.opcode_modifier.drex
5323 || i.tm.opcode_modifier.drexv
5324 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 5325 op = i.drex.modrm_regmem;
5326 else
5327 {
c0209578
L		 5328 for (op = 0; op < i.operands; op++)
5329 if (operand_type_check (i.types[op], anymem))
5330 break;
5331 assert (op < i.operands);
85f10a01 5332 }
29b0f896
AM		 5333
5334 default_seg = &ds;
5335
5336 if (i.base_reg == 0)
5337 {
5338 i.rm.mode = 0;
5339 if (!i.disp_operands)
5340 fake_zero_displacement = 1;
5341 if (i.index_reg == 0)
5342 {
5343 /* Operand is just <disp> */
20f0a1fc 5344 if (flag_code == CODE_64BIT)
29b0f896
AM		 5345 {
5346 /* 64bit mode overwrites the 32bit absolute
5347 addressing by RIP relative addressing and
5348 absolute addressing is encoded by one of the
5349 redundant SIB forms. */
5350 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5351 i.sib.base = NO_BASE_REGISTER;
5352 i.sib.index = NO_INDEX_REGISTER;
fc225355 5353 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 5354 ? disp32s : disp32);
20f0a1fc 5355 }
fc225355
L		 5356 else if ((flag_code == CODE_16BIT)
5357 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 5358 {
5359 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 5360 i.types[op] = disp16;
20f0a1fc
NC		 5361 }
5362 else
5363 {
5364 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 5365 i.types[op] = disp32;
29b0f896
AM		 5366 }
5367 }
5368 else /* !i.base_reg && i.index_reg */
5369 {
db51cc60
L		 5370 if (i.index_reg->reg_num == RegEiz
5371 || i.index_reg->reg_num == RegRiz)
5372 i.sib.index = NO_INDEX_REGISTER;
5373 else
5374 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5375 i.sib.base = NO_BASE_REGISTER;
5376 i.sib.scale = i.log2_scale_factor;
5377 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 5378 i.types[op].bitfield.disp8 = 0;
5379 i.types[op].bitfield.disp16 = 0;
5380 i.types[op].bitfield.disp64 = 0;
29b0f896 5381 if (flag_code != CODE_64BIT)
40fb9820
L		 5382 {
5383 /* Must be 32 bit */
5384 i.types[op].bitfield.disp32 = 1;
5385 i.types[op].bitfield.disp32s = 0;
5386 }
29b0f896 5387 else
40fb9820
L		 5388 {
5389 i.types[op].bitfield.disp32 = 0;
5390 i.types[op].bitfield.disp32s = 1;
5391 }
29b0f896 5392 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5393 i.rex |= REX_X;
29b0f896
AM		 5394 }
5395 }
5396 /* RIP addressing for 64bit mode. */
9a04903e
JB		 5397 else if (i.base_reg->reg_num == RegRip ||
5398 i.base_reg->reg_num == RegEip)
29b0f896
AM		 5399 {
5400 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5401 i.types[op].bitfield.disp8 = 0;
5402 i.types[op].bitfield.disp16 = 0;
5403 i.types[op].bitfield.disp32 = 0;
5404 i.types[op].bitfield.disp32s = 1;
5405 i.types[op].bitfield.disp64 = 0;
71903a11 5406 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5407 if (! i.disp_operands)
5408 fake_zero_displacement = 1;
29b0f896 5409 }
40fb9820 5410 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 5411 {
5412 switch (i.base_reg->reg_num)
5413 {
5414 case 3: /* (%bx) */
5415 if (i.index_reg == 0)
5416 i.rm.regmem = 7;
5417 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5418 i.rm.regmem = i.index_reg->reg_num - 6;
5419 break;
5420 case 5: /* (%bp) */
5421 default_seg = &ss;
5422 if (i.index_reg == 0)
5423 {
5424 i.rm.regmem = 6;
40fb9820 5425 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5426 {
5427 /* fake (%bp) into 0(%bp) */
40fb9820 5428 i.types[op].bitfield.disp8 = 1;
252b5132 5429 fake_zero_displacement = 1;
29b0f896
AM		 5430 }
5431 }
5432 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5433 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5434 break;
5435 default: /* (%si) -> 4 or (%di) -> 5 */
5436 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5437 }
5438 i.rm.mode = mode_from_disp_size (i.types[op]);
5439 }
5440 else /* i.base_reg and 32/64 bit mode */
5441 {
5442 if (flag_code == CODE_64BIT
40fb9820
L		 5443 && operand_type_check (i.types[op], disp))
5444 {
5445 i386_operand_type temp;
0dfbf9d7 5446 operand_type_set (&temp, 0);
40fb9820
L		 5447 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5448 i.types[op] = temp;
5449 if (i.prefix[ADDR_PREFIX] == 0)
5450 i.types[op].bitfield.disp32s = 1;
5451 else
5452 i.types[op].bitfield.disp32 = 1;
5453 }
20f0a1fc 5454
29b0f896
AM		 5455 i.rm.regmem = i.base_reg->reg_num;
5456 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5457 i.rex |= REX_B;
29b0f896
AM		 5458 i.sib.base = i.base_reg->reg_num;
5459 /* x86-64 ignores REX prefix bit here to avoid decoder
5460 complications. */
5461 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5462 {
5463 default_seg = &ss;
5464 if (i.disp_operands == 0)
5465 {
5466 fake_zero_displacement = 1;
40fb9820 5467 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5468 }
5469 }
5470 else if (i.base_reg->reg_num == ESP_REG_NUM)
5471 {
5472 default_seg = &ss;
5473 }
5474 i.sib.scale = i.log2_scale_factor;
5475 if (i.index_reg == 0)
5476 {
5477 /* <disp>(%esp) becomes two byte modrm with no index
5478 register. We've already stored the code for esp
5479 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5480 Any base register besides %esp will not use the
5481 extra modrm byte. */
5482 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 5483 }
5484 else
5485 {
db51cc60
L		 5486 if (i.index_reg->reg_num == RegEiz
5487 || i.index_reg->reg_num == RegRiz)
5488 i.sib.index = NO_INDEX_REGISTER;
5489 else
5490 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5491 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5492 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5493 i.rex |= REX_X;
29b0f896 5494 }
67a4f2b7
AO		 5495
5496 if (i.disp_operands
5497 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5498 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5499 i.rm.mode = 0;
5500 else
5501 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 5502 }
252b5132 5503
29b0f896
AM		 5504 if (fake_zero_displacement)
5505 {
5506 /* Fakes a zero displacement assuming that i.types[op]
5507 holds the correct displacement size. */
5508 expressionS *exp;
5509
5510 assert (i.op[op].disps == 0);
5511 exp = &disp_expressions[i.disp_operands++];
5512 i.op[op].disps = exp;
5513 exp->X_op = O_constant;
5514 exp->X_add_number = 0;
5515 exp->X_add_symbol = (symbolS *) 0;
5516 exp->X_op_symbol = (symbolS *) 0;
5517 }
c0f3af97
L		 5518
5519 mem = op;
29b0f896 5520 }
c0f3af97
L		 5521 else
5522 mem = ~0;
252b5132 5523
29b0f896
AM		 5524 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5525 (if any) based on i.tm.extension_opcode. Again, we must be
5526 careful to make sure that segment/control/debug/test/MMX
5527 registers are coded into the i.rm.reg field. */
5528 if (i.reg_operands)
5529 {
99018f42
L		 5530 unsigned int op;
5531
85f10a01
MM		 5532 /* This has been precalculated for SSE5 instructions
5533 that have a DREX field earlier in process_drex. */
b5016f89
L		 5534 if (i.tm.opcode_modifier.drex
5535 || i.tm.opcode_modifier.drexv
5536 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 5537 {
5538 op = i.drex.modrm_reg;
5539 i.rm.reg = i.op[op].regs->reg_num;
5540 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5541 i.rex |= REX_R;
5542 }
5543 else
5544 {
c0f3af97
L		 5545 unsigned int vex_reg = ~0;
5546
c0209578
L		 5547 for (op = 0; op < i.operands; op++)
5548 if (i.types[op].bitfield.reg8
5549 || i.types[op].bitfield.reg16
5550 || i.types[op].bitfield.reg32
5551 || i.types[op].bitfield.reg64
5552 || i.types[op].bitfield.regmmx
5553 || i.types[op].bitfield.regxmm
c0f3af97 5554 || i.types[op].bitfield.regymm
c0209578
L		 5555 || i.types[op].bitfield.sreg2
5556 || i.types[op].bitfield.sreg3
5557 || i.types[op].bitfield.control
5558 || i.types[op].bitfield.debug
5559 || i.types[op].bitfield.test)
5560 break;
5561
c0f3af97
L		 5562 if (vex_3_sources)
5563 op = dest;
5564 else if (i.tm.opcode_modifier.vexnds)
5565 {
5566 /* For instructions with VexNDS, the register-only
5567 source operand is encoded in VEX prefix. */
5568 assert (mem != (unsigned int) ~0);
5569
5570 if (op > mem)
5571 {
5572 vex_reg = op++;
5573 assert (op < i.operands);
5574 }
5575 else
5576 {
5577 vex_reg = op + 1;
5578 assert (vex_reg < i.operands);
5579 }
5580 }
5581 else if (i.tm.opcode_modifier.vexndd)
5582 {
5583 /* For instructions with VexNDD, there should be
5584 no memory operand and the register destination
5585 is encoded in VEX prefix. */
5586 assert (i.mem_operands == 0
5587 && (op + 2) == i.operands);
5588 vex_reg = op + 1;
5589 }
5590 else
5591 assert (op < i.operands);
5592
5593 if (vex_reg != (unsigned int) ~0)
5594 {
5595 assert (i.reg_operands == 2);
5596
5597 if (!operand_type_equal (&i.tm.operand_types[vex_reg],
5598 & regxmm)
5599 && !operand_type_equal (&i.tm.operand_types[vex_reg],
5600 &regymm))
5601 abort ();
5602 i.vex.register_specifier = i.op[vex_reg].regs;
5603 }
99018f42 5604
85f10a01
MM		 5605 /* If there is an extension opcode to put here, the
5606 register number must be put into the regmem field. */
c0209578
L		 5607 if (i.tm.extension_opcode != None)
5608 {
5609 i.rm.regmem = i.op[op].regs->reg_num;
5610 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5611 i.rex |= REX_B;
5612 }
5613 else
5614 {
5615 i.rm.reg = i.op[op].regs->reg_num;
5616 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5617 i.rex |= REX_R;
5618 }
85f10a01 5619 }
252b5132 5620
29b0f896
AM		 5621 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5622 must set it to 3 to indicate this is a register operand
5623 in the regmem field. */
5624 if (!i.mem_operands)
5625 i.rm.mode = 3;
5626 }
252b5132 5627
29b0f896 5628 /* Fill in i.rm.reg field with extension opcode (if any). */
85f10a01
MM		 5629 if (i.tm.extension_opcode != None
5630 && !(i.tm.opcode_modifier.drex
5631 || i.tm.opcode_modifier.drexv
5632 || i.tm.opcode_modifier.drexc))
29b0f896
AM		 5633 i.rm.reg = i.tm.extension_opcode;
5634 }
5635 return default_seg;
5636}
252b5132 5637
29b0f896 5638static void
e3bb37b5 5639output_branch (void)
29b0f896
AM		 5640{
5641 char *p;
5642 int code16;
5643 int prefix;
5644 relax_substateT subtype;
5645 symbolS *sym;
5646 offsetT off;
5647
5648 code16 = 0;
5649 if (flag_code == CODE_16BIT)
5650 code16 = CODE16;
5651
5652 prefix = 0;
5653 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5654 {
29b0f896
AM		 5655 prefix = 1;
5656 i.prefixes -= 1;
5657 code16 ^= CODE16;
252b5132 5658 }
29b0f896
AM		 5659 /* Pentium4 branch hints. */
5660 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5661 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5662 {
29b0f896
AM		 5663 prefix++;
5664 i.prefixes--;
5665 }
5666 if (i.prefix[REX_PREFIX] != 0)
5667 {
5668 prefix++;
5669 i.prefixes--;
2f66722d
AM		 5670 }
5671
29b0f896
AM		 5672 if (i.prefixes != 0 && !intel_syntax)
5673 as_warn (_("skipping prefixes on this instruction"));
5674
5675 /* It's always a symbol; End frag & setup for relax.
5676 Make sure there is enough room in this frag for the largest
5677 instruction we may generate in md_convert_frag. This is 2
5678 bytes for the opcode and room for the prefix and largest
5679 displacement. */
5680 frag_grow (prefix + 2 + 4);
5681 /* Prefix and 1 opcode byte go in fr_fix. */
5682 p = frag_more (prefix + 1);
5683 if (i.prefix[DATA_PREFIX] != 0)
5684 *p++ = DATA_PREFIX_OPCODE;
5685 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5686 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5687 *p++ = i.prefix[SEG_PREFIX];
5688 if (i.prefix[REX_PREFIX] != 0)
5689 *p++ = i.prefix[REX_PREFIX];
5690 *p = i.tm.base_opcode;
5691
5692 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5693 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 5694 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 5695 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5696 else
5697 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5698 subtype |= code16;
3e73aa7c 5699
29b0f896
AM		 5700 sym = i.op[0].disps->X_add_symbol;
5701 off = i.op[0].disps->X_add_number;
3e73aa7c 5702
29b0f896
AM		 5703 if (i.op[0].disps->X_op != O_constant
5704 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5705 {
29b0f896
AM		 5706 /* Handle complex expressions. */
5707 sym = make_expr_symbol (i.op[0].disps);
5708 off = 0;
5709 }
3e73aa7c 5710
29b0f896
AM		 5711 /* 1 possible extra opcode + 4 byte displacement go in var part.
5712 Pass reloc in fr_var. */
5713 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5714}
3e73aa7c 5715
29b0f896 5716static void
e3bb37b5 5717output_jump (void)
29b0f896
AM		 5718{
5719 char *p;
5720 int size;
3e02c1cc 5721 fixS *fixP;
29b0f896 5722
40fb9820 5723 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 5724 {
5725 /* This is a loop or jecxz type instruction. */
5726 size = 1;
5727 if (i.prefix[ADDR_PREFIX] != 0)
5728 {
5729 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5730 i.prefixes -= 1;
5731 }
5732 /* Pentium4 branch hints. */
5733 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5734 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5735 {
5736 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5737 i.prefixes--;
3e73aa7c
JH		 5738 }
5739 }
29b0f896
AM		 5740 else
5741 {
5742 int code16;
3e73aa7c 5743
29b0f896
AM		 5744 code16 = 0;
5745 if (flag_code == CODE_16BIT)
5746 code16 = CODE16;
3e73aa7c 5747
29b0f896
AM		 5748 if (i.prefix[DATA_PREFIX] != 0)
5749 {
5750 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5751 i.prefixes -= 1;
5752 code16 ^= CODE16;
5753 }
252b5132 5754
29b0f896
AM		 5755 size = 4;
5756 if (code16)
5757 size = 2;
5758 }
9fcc94b6 5759
29b0f896
AM		 5760 if (i.prefix[REX_PREFIX] != 0)
5761 {
5762 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5763 i.prefixes -= 1;
5764 }
252b5132 5765
29b0f896
AM		 5766 if (i.prefixes != 0 && !intel_syntax)
5767 as_warn (_("skipping prefixes on this instruction"));
e0890092 5768
29b0f896
AM		 5769 p = frag_more (1 + size);
5770 *p++ = i.tm.base_opcode;
e0890092 5771
3e02c1cc
AM		 5772 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5773 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5774
5775 /* All jumps handled here are signed, but don't use a signed limit
5776 check for 32 and 16 bit jumps as we want to allow wrap around at
5777 4G and 64k respectively. */
5778 if (size == 1)
5779 fixP->fx_signed = 1;
29b0f896 5780}
e0890092 5781
29b0f896 5782static void
e3bb37b5 5783output_interseg_jump (void)
29b0f896
AM		 5784{
5785 char *p;
5786 int size;
5787 int prefix;
5788 int code16;
252b5132 5789
29b0f896
AM		 5790 code16 = 0;
5791 if (flag_code == CODE_16BIT)
5792 code16 = CODE16;
a217f122 5793
29b0f896
AM		 5794 prefix = 0;
5795 if (i.prefix[DATA_PREFIX] != 0)
5796 {
5797 prefix = 1;
5798 i.prefixes -= 1;
5799 code16 ^= CODE16;
5800 }
5801 if (i.prefix[REX_PREFIX] != 0)
5802 {
5803 prefix++;
5804 i.prefixes -= 1;
5805 }
252b5132 5806
29b0f896
AM		 5807 size = 4;
5808 if (code16)
5809 size = 2;
252b5132 5810
29b0f896
AM		 5811 if (i.prefixes != 0 && !intel_syntax)
5812 as_warn (_("skipping prefixes on this instruction"));
252b5132 5813
29b0f896
AM		 5814 /* 1 opcode; 2 segment; offset */
5815 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 5816
29b0f896
AM		 5817 if (i.prefix[DATA_PREFIX] != 0)
5818 *p++ = DATA_PREFIX_OPCODE;
252b5132 5819
29b0f896
AM		 5820 if (i.prefix[REX_PREFIX] != 0)
5821 *p++ = i.prefix[REX_PREFIX];
252b5132 5822
29b0f896
AM		 5823 *p++ = i.tm.base_opcode;
5824 if (i.op[1].imms->X_op == O_constant)
5825 {
5826 offsetT n = i.op[1].imms->X_add_number;
252b5132 5827
29b0f896
AM		 5828 if (size == 2
5829 && !fits_in_unsigned_word (n)
5830 && !fits_in_signed_word (n))
5831 {
5832 as_bad (_("16-bit jump out of range"));
5833 return;
5834 }
5835 md_number_to_chars (p, n, size);
5836 }
5837 else
5838 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5839 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5840 if (i.op[0].imms->X_op != O_constant)
5841 as_bad (_("can't handle non absolute segment in `%s'"),
5842 i.tm.name);
5843 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5844}
a217f122 5845
29b0f896 5846static void
e3bb37b5 5847output_insn (void)
29b0f896 5848{
2bbd9c25
JJ		 5849 fragS *insn_start_frag;
5850 offsetT insn_start_off;
5851
29b0f896
AM		 5852 /* Tie dwarf2 debug info to the address at the start of the insn.
5853 We can't do this after the insn has been output as the current
5854 frag may have been closed off. eg. by frag_var. */
5855 dwarf2_emit_insn (0);
5856
2bbd9c25
JJ		 5857 insn_start_frag = frag_now;
5858 insn_start_off = frag_now_fix ();
5859
29b0f896 5860 /* Output jumps. */
40fb9820 5861 if (i.tm.opcode_modifier.jump)
29b0f896 5862 output_branch ();
40fb9820
L		 5863 else if (i.tm.opcode_modifier.jumpbyte
5864 || i.tm.opcode_modifier.jumpdword)
29b0f896 5865 output_jump ();
40fb9820 5866 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 5867 output_interseg_jump ();
5868 else
5869 {
5870 /* Output normal instructions here. */
5871 char *p;
5872 unsigned char *q;
47465058 5873 unsigned int j;
331d2d0d 5874 unsigned int prefix;
4dffcebc 5875
c0f3af97
L		 5876 /* Since the VEX prefix contains the implicit prefix, we don't
5877 need the explicit prefix. */
5878 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 5879 {
c0f3af97 5880 switch (i.tm.opcode_length)
bc4bd9ab 5881 {
c0f3af97
L		 5882 case 3:
5883 if (i.tm.base_opcode & 0xff000000)
4dffcebc 5884 {
c0f3af97
L		 5885 prefix = (i.tm.base_opcode >> 24) & 0xff;
5886 goto check_prefix;
5887 }
5888 break;
5889 case 2:
5890 if ((i.tm.base_opcode & 0xff0000) != 0)
5891 {
5892 prefix = (i.tm.base_opcode >> 16) & 0xff;
5893 if (i.tm.cpu_flags.bitfield.cpupadlock)
5894 {
4dffcebc 5895check_prefix:
c0f3af97
L		 5896 if (prefix != REPE_PREFIX_OPCODE
5897 || (i.prefix[LOCKREP_PREFIX]
5898 != REPE_PREFIX_OPCODE))
5899 add_prefix (prefix);
5900 }
5901 else
4dffcebc
L		 5902 add_prefix (prefix);
5903 }
c0f3af97
L		 5904 break;
5905 case 1:
5906 break;
5907 default:
5908 abort ();
bc4bd9ab 5909 }
c0f3af97
L		 5910
5911 /* The prefix bytes. */
5912 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5913 if (*q)
5914 FRAG_APPEND_1_CHAR (*q);
0f10071e 5915 }
252b5132 5916
c0f3af97
L		 5917 if (i.tm.opcode_modifier.vex)
5918 {
5919 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
5920 if (*q)
5921 switch (j)
5922 {
5923 case REX_PREFIX:
5924 /* REX byte is encoded in VEX prefix. */
5925 break;
5926 case SEG_PREFIX:
5927 case ADDR_PREFIX:
5928 FRAG_APPEND_1_CHAR (*q);
5929 break;
5930 default:
5931 /* There should be no other prefixes for instructions
5932 with VEX prefix. */
5933 abort ();
5934 }
5935
5936 /* Now the VEX prefix. */
5937 p = frag_more (i.vex.length);
5938 for (j = 0; j < i.vex.length; j++)
5939 p[j] = i.vex.bytes[j];
5940 }
252b5132 5941
29b0f896 5942 /* Now the opcode; be careful about word order here! */
4dffcebc 5943 if (i.tm.opcode_length == 1)
29b0f896
AM		 5944 {
5945 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5946 }
5947 else
5948 {
4dffcebc 5949 switch (i.tm.opcode_length)
331d2d0d 5950 {
4dffcebc 5951 case 3:
331d2d0d
L		 5952 p = frag_more (3);
5953 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 5954 break;
5955 case 2:
5956 p = frag_more (2);
5957 break;
5958 default:
5959 abort ();
5960 break;
331d2d0d 5961 }
0f10071e 5962
29b0f896
AM		 5963 /* Put out high byte first: can't use md_number_to_chars! */
5964 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5965 *p = i.tm.base_opcode & 0xff;
85f10a01
MM		 5966
5967 /* On SSE5, encode the OC1 bit in the DREX field if this
5968 encoding has multiple formats. */
5969 if (i.tm.opcode_modifier.drex
5970 && i.tm.opcode_modifier.drexv
5971 && DREX_OC1 (i.tm.extension_opcode))
5972 *p |= DREX_OC1_MASK;
29b0f896 5973 }
3e73aa7c 5974
29b0f896 5975 /* Now the modrm byte and sib byte (if present). */
40fb9820 5976 if (i.tm.opcode_modifier.modrm)
29b0f896 5977 {
4a3523fa
L		 5978 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5979 | i.rm.reg << 3
5980 | i.rm.mode << 6));
29b0f896
AM		 5981 /* If i.rm.regmem == ESP (4)
5982 && i.rm.mode != (Register mode)
5983 && not 16 bit
5984 ==> need second modrm byte. */
5985 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5986 && i.rm.mode != 3
40fb9820 5987 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 5988 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5989 | i.sib.index << 3
5990 | i.sib.scale << 6));
29b0f896 5991 }
3e73aa7c 5992
85f10a01
MM		 5993 /* Write the DREX byte if needed. */
5994 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
5995 {
5996 p = frag_more (1);
5997 *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
5998
5999 /* Encode the OC0 bit if this encoding has multiple
6000 formats. */
6001 if ((i.tm.opcode_modifier.drex
6002 || i.tm.opcode_modifier.drexv)
6003 && DREX_OC0 (i.tm.extension_opcode))
6004 *p |= DREX_OC0_MASK;
6005 }
6006
29b0f896 6007 if (i.disp_operands)
2bbd9c25 6008 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 6009
29b0f896 6010 if (i.imm_operands)
2bbd9c25 6011 output_imm (insn_start_frag, insn_start_off);
29b0f896 6012 }
252b5132 6013
29b0f896
AM		 6014#ifdef DEBUG386
6015 if (flag_debug)
6016 {
7b81dfbb 6017 pi ("" /*line*/, &i);
29b0f896
AM		 6018 }
6019#endif /* DEBUG386 */
6020}
252b5132 6021
e205caa7
L		 6022/* Return the size of the displacement operand N. */
6023
6024static int
6025disp_size (unsigned int n)
6026{
6027 int size = 4;
40fb9820
L		 6028 if (i.types[n].bitfield.disp64)
6029 size = 8;
6030 else if (i.types[n].bitfield.disp8)
6031 size = 1;
6032 else if (i.types[n].bitfield.disp16)
6033 size = 2;
e205caa7
L		 6034 return size;
6035}
6036
6037/* Return the size of the immediate operand N. */
6038
6039static int
6040imm_size (unsigned int n)
6041{
6042 int size = 4;
40fb9820
L		 6043 if (i.types[n].bitfield.imm64)
6044 size = 8;
6045 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
6046 size = 1;
6047 else if (i.types[n].bitfield.imm16)
6048 size = 2;
e205caa7
L		 6049 return size;
6050}
6051
29b0f896 6052static void
64e74474 6053output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6054{
6055 char *p;
6056 unsigned int n;
252b5132 6057
29b0f896
AM		 6058 for (n = 0; n < i.operands; n++)
6059 {
40fb9820 6060 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 6061 {
6062 if (i.op[n].disps->X_op == O_constant)
6063 {
e205caa7 6064 int size = disp_size (n);
29b0f896 6065 offsetT val;
252b5132 6066
29b0f896
AM		 6067 val = offset_in_range (i.op[n].disps->X_add_number,
6068 size);
6069 p = frag_more (size);
6070 md_number_to_chars (p, val, size);
6071 }
6072 else
6073 {
f86103b7 6074 enum bfd_reloc_code_real reloc_type;
e205caa7 6075 int size = disp_size (n);
40fb9820 6076 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 6077 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
6078
e205caa7 6079 /* We can't have 8 bit displacement here. */
40fb9820 6080 assert (!i.types[n].bitfield.disp8);
e205caa7 6081
29b0f896
AM		 6082 /* The PC relative address is computed relative
6083 to the instruction boundary, so in case immediate
6084 fields follows, we need to adjust the value. */
6085 if (pcrel && i.imm_operands)
6086 {
29b0f896 6087 unsigned int n1;
e205caa7 6088 int sz = 0;
252b5132 6089
29b0f896 6090 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 6091 if (operand_type_check (i.types[n1], imm))
252b5132 6092 {
e205caa7
L		 6093 /* Only one immediate is allowed for PC
6094 relative address. */
6095 assert (sz == 0);
6096 sz = imm_size (n1);
6097 i.op[n].disps->X_add_number -= sz;
252b5132 6098 }
29b0f896 6099 /* We should find the immediate. */
e205caa7 6100 assert (sz != 0);
29b0f896 6101 }
520dc8e8 6102
29b0f896 6103 p = frag_more (size);
2bbd9c25 6104 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 6105 if (GOT_symbol
2bbd9c25 6106 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 6107 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6108 || reloc_type == BFD_RELOC_X86_64_32S
6109 || (reloc_type == BFD_RELOC_64
6110 && object_64bit))
d6ab8113
JB		 6111 && (i.op[n].disps->X_op == O_symbol
6112 || (i.op[n].disps->X_op == O_add
6113 && ((symbol_get_value_expression
6114 (i.op[n].disps->X_op_symbol)->X_op)
6115 == O_subtract))))
6116 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 6117 {
6118 offsetT add;
6119
6120 if (insn_start_frag == frag_now)
6121 add = (p - frag_now->fr_literal) - insn_start_off;
6122 else
6123 {
6124 fragS *fr;
6125
6126 add = insn_start_frag->fr_fix - insn_start_off;
6127 for (fr = insn_start_frag->fr_next;
6128 fr && fr != frag_now; fr = fr->fr_next)
6129 add += fr->fr_fix;
6130 add += p - frag_now->fr_literal;
6131 }
6132
4fa24527 6133 if (!object_64bit)
7b81dfbb
AJ		 6134 {
6135 reloc_type = BFD_RELOC_386_GOTPC;
6136 i.op[n].imms->X_add_number += add;
6137 }
6138 else if (reloc_type == BFD_RELOC_64)
6139 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 6140 else
7b81dfbb
AJ		 6141 /* Don't do the adjustment for x86-64, as there
6142 the pcrel addressing is relative to the _next_
6143 insn, and that is taken care of in other code. */
d6ab8113 6144 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 6145 }
062cd5e7 6146 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 6147 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 6148 }
6149 }
6150 }
6151}
252b5132 6152
29b0f896 6153static void
64e74474 6154output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6155{
6156 char *p;
6157 unsigned int n;
252b5132 6158
29b0f896
AM		 6159 for (n = 0; n < i.operands; n++)
6160 {
40fb9820 6161 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 6162 {
6163 if (i.op[n].imms->X_op == O_constant)
6164 {
e205caa7 6165 int size = imm_size (n);
29b0f896 6166 offsetT val;
b4cac588 6167
29b0f896
AM		 6168 val = offset_in_range (i.op[n].imms->X_add_number,
6169 size);
6170 p = frag_more (size);
6171 md_number_to_chars (p, val, size);
6172 }
6173 else
6174 {
6175 /* Not absolute_section.
6176 Need a 32-bit fixup (don't support 8bit
6177 non-absolute imms). Try to support other
6178 sizes ... */
f86103b7 6179 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 6180 int size = imm_size (n);
6181 int sign;
29b0f896 6182
40fb9820 6183 if (i.types[n].bitfield.imm32s
a7d61044 6184 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 6185 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 6186 sign = 1;
e205caa7
L		 6187 else
6188 sign = 0;
520dc8e8 6189
29b0f896
AM		 6190 p = frag_more (size);
6191 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 6192
2bbd9c25
JJ		 6193 /* This is tough to explain. We end up with this one if we
6194 * have operands that look like
6195 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6196 * obtain the absolute address of the GOT, and it is strongly
6197 * preferable from a performance point of view to avoid using
6198 * a runtime relocation for this. The actual sequence of
6199 * instructions often look something like:
6200 *
6201 * call .L66
6202 * .L66:
6203 * popl %ebx
6204 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6205 *
6206 * The call and pop essentially return the absolute address
6207 * of the label .L66 and store it in %ebx. The linker itself
6208 * will ultimately change the first operand of the addl so
6209 * that %ebx points to the GOT, but to keep things simple, the
6210 * .o file must have this operand set so that it generates not
6211 * the absolute address of .L66, but the absolute address of
6212 * itself. This allows the linker itself simply treat a GOTPC
6213 * relocation as asking for a pcrel offset to the GOT to be
6214 * added in, and the addend of the relocation is stored in the
6215 * operand field for the instruction itself.
6216 *
6217 * Our job here is to fix the operand so that it would add
6218 * the correct offset so that %ebx would point to itself. The
6219 * thing that is tricky is that .-.L66 will point to the
6220 * beginning of the instruction, so we need to further modify
6221 * the operand so that it will point to itself. There are
6222 * other cases where you have something like:
6223 *
6224 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6225 *
6226 * and here no correction would be required. Internally in
6227 * the assembler we treat operands of this form as not being
6228 * pcrel since the '.' is explicitly mentioned, and I wonder
6229 * whether it would simplify matters to do it this way. Who
6230 * knows. In earlier versions of the PIC patches, the
6231 * pcrel_adjust field was used to store the correction, but
6232 * since the expression is not pcrel, I felt it would be
6233 * confusing to do it this way. */
6234
d6ab8113 6235 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6236 || reloc_type == BFD_RELOC_X86_64_32S
6237 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 6238 && GOT_symbol
6239 && GOT_symbol == i.op[n].imms->X_add_symbol
6240 && (i.op[n].imms->X_op == O_symbol
6241 || (i.op[n].imms->X_op == O_add
6242 && ((symbol_get_value_expression
6243 (i.op[n].imms->X_op_symbol)->X_op)
6244 == O_subtract))))
6245 {
2bbd9c25
JJ		 6246 offsetT add;
6247
6248 if (insn_start_frag == frag_now)
6249 add = (p - frag_now->fr_literal) - insn_start_off;
6250 else
6251 {
6252 fragS *fr;
6253
6254 add = insn_start_frag->fr_fix - insn_start_off;
6255 for (fr = insn_start_frag->fr_next;
6256 fr && fr != frag_now; fr = fr->fr_next)
6257 add += fr->fr_fix;
6258 add += p - frag_now->fr_literal;
6259 }
6260
4fa24527 6261 if (!object_64bit)
d6ab8113 6262 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 6263 else if (size == 4)
d6ab8113 6264 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 6265 else if (size == 8)
6266 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 6267 i.op[n].imms->X_add_number += add;
29b0f896 6268 }
29b0f896
AM		 6269 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6270 i.op[n].imms, 0, reloc_type);
6271 }
6272 }
6273 }
252b5132
RH		 6274}
6275\f
d182319b
JB		 6276/* x86_cons_fix_new is called via the expression parsing code when a
6277 reloc is needed. We use this hook to get the correct .got reloc. */
6278static enum bfd_reloc_code_real got_reloc = NO_RELOC;
6279static int cons_sign = -1;
6280
6281void
e3bb37b5 6282x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 6283 expressionS *exp)
d182319b
JB		 6284{
6285 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
6286
6287 got_reloc = NO_RELOC;
6288
6289#ifdef TE_PE
6290 if (exp->X_op == O_secrel)
6291 {
6292 exp->X_op = O_symbol;
6293 r = BFD_RELOC_32_SECREL;
6294 }
6295#endif
6296
6297 fix_new_exp (frag, off, len, exp, 0, r);
6298}
6299
718ddfc0
JB		 6300#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6301# define lex_got(reloc, adjust, types) NULL
6302#else
f3c180ae
AM		 6303/* Parse operands of the form
6304 <symbol>@GOTOFF+<nnn>
6305 and similar .plt or .got references.
6306
6307 If we find one, set up the correct relocation in RELOC and copy the
6308 input string, minus the `@GOTOFF' into a malloc'd buffer for
6309 parsing by the calling routine. Return this buffer, and if ADJUST
6310 is non-null set it to the length of the string we removed from the
6311 input line. Otherwise return NULL. */
6312static char *
3956db08 6313lex_got (enum bfd_reloc_code_real *reloc,
64e74474 6314 int *adjust,
40fb9820 6315 i386_operand_type *types)
f3c180ae 6316{
7b81dfbb
AJ		 6317 /* Some of the relocations depend on the size of what field is to
6318 be relocated. But in our callers i386_immediate and i386_displacement
6319 we don't yet know the operand size (this will be set by insn
6320 matching). Hence we record the word32 relocation here,
6321 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 6322 static const struct {
6323 const char *str;
4fa24527 6324 const enum bfd_reloc_code_real rel[2];
40fb9820 6325 const i386_operand_type types64;
f3c180ae 6326 } gotrel[] = {
4eed87de
AM		 6327 { "PLTOFF", { 0,
6328 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 6329 OPERAND_TYPE_IMM64 },
4eed87de
AM		 6330 { "PLT", { BFD_RELOC_386_PLT32,
6331 BFD_RELOC_X86_64_PLT32 },
40fb9820 6332 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6333 { "GOTPLT", { 0,
6334 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 6335 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 6336 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
6337 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 6338 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 6339 { "GOTPCREL", { 0,
6340 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 6341 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6342 { "TLSGD", { BFD_RELOC_386_TLS_GD,
6343 BFD_RELOC_X86_64_TLSGD },
40fb9820 6344 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6345 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
6346 0 },
40fb9820 6347 OPERAND_TYPE_NONE },
4eed87de
AM		 6348 { "TLSLD", { 0,
6349 BFD_RELOC_X86_64_TLSLD },
40fb9820 6350 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6351 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
6352 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 6353 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6354 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
6355 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 6356 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 6357 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
6358 0 },
40fb9820 6359 OPERAND_TYPE_NONE },
4eed87de
AM		 6360 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
6361 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820
L		 6362
6363 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 6364 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
6365 0 },
40fb9820 6366 OPERAND_TYPE_NONE },
4eed87de
AM		 6367 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
6368 0 },
40fb9820 6369 OPERAND_TYPE_NONE },
4eed87de
AM		 6370 { "GOT", { BFD_RELOC_386_GOT32,
6371 BFD_RELOC_X86_64_GOT32 },
40fb9820 6372 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM		 6373 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
6374 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 6375 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6376 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
6377 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 6378 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 6379 };
6380 char *cp;
6381 unsigned int j;
6382
718ddfc0
JB		 6383 if (!IS_ELF)
6384 return NULL;
6385
f3c180ae 6386 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 6387 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 6388 return NULL;
6389
47465058 6390 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae
AM		 6391 {
6392 int len;
6393
6394 len = strlen (gotrel[j].str);
28f81592 6395 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 6396 {
4fa24527 6397 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 6398 {
28f81592
AM		 6399 int first, second;
6400 char *tmpbuf, *past_reloc;
f3c180ae 6401
4fa24527 6402 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 6403 if (adjust)
6404 *adjust = len;
f3c180ae 6405
3956db08
JB		 6406 if (types)
6407 {
6408 if (flag_code != CODE_64BIT)
40fb9820
L		 6409 {
6410 types->bitfield.imm32 = 1;
6411 types->bitfield.disp32 = 1;
6412 }
3956db08
JB		 6413 else
6414 *types = gotrel[j].types64;
6415 }
6416
f3c180ae
AM		 6417 if (GOT_symbol == NULL)
6418 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6419
28f81592 6420 /* The length of the first part of our input line. */
f3c180ae 6421 first = cp - input_line_pointer;
28f81592
AM		 6422
6423 /* The second part goes from after the reloc token until
67c11a9b 6424 (and including) an end_of_line char or comma. */
28f81592 6425 past_reloc = cp + 1 + len;
67c11a9b
AM		 6426 cp = past_reloc;
6427 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6428 ++cp;
6429 second = cp + 1 - past_reloc;
28f81592
AM		 6430
6431 /* Allocate and copy string. The trailing NUL shouldn't
6432 be necessary, but be safe. */
6433 tmpbuf = xmalloc (first + second + 2);
f3c180ae 6434 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 6435 if (second != 0 && *past_reloc != ' ')
6436 /* Replace the relocation token with ' ', so that
6437 errors like foo@GOTOFF1 will be detected. */
6438 tmpbuf[first++] = ' ';
6439 memcpy (tmpbuf + first, past_reloc, second);
6440 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6441 return tmpbuf;
6442 }
6443
4fa24527
JB		 6444 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6445 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6446 return NULL;
6447 }
6448 }
6449
6450 /* Might be a symbol version string. Don't as_bad here. */
6451 return NULL;
6452}
6453
f3c180ae 6454void
e3bb37b5 6455x86_cons (expressionS *exp, int size)
f3c180ae 6456{
4fa24527 6457 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6458 {
6459 /* Handle @GOTOFF and the like in an expression. */
6460 char *save;
6461 char *gotfree_input_line;
6462 int adjust;
6463
6464 save = input_line_pointer;
3956db08 6465 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6466 if (gotfree_input_line)
6467 input_line_pointer = gotfree_input_line;
6468
6469 expression (exp);
6470
6471 if (gotfree_input_line)
6472 {
6473 /* expression () has merrily parsed up to the end of line,
6474 or a comma - in the wrong buffer. Transfer how far
6475 input_line_pointer has moved to the right buffer. */
6476 input_line_pointer = (save
6477 + (input_line_pointer - gotfree_input_line)
6478 + adjust);
6479 free (gotfree_input_line);
3992d3b7
AM		 6480 if (exp->X_op == O_constant
6481 || exp->X_op == O_absent
6482 || exp->X_op == O_illegal
6483 || exp->X_op == O_register
6484 || exp->X_op == O_big)
6485 {
6486 char c = *input_line_pointer;
6487 *input_line_pointer = 0;
6488 as_bad (_("missing or invalid expression `%s'"), save);
6489 *input_line_pointer = c;
6490 }
f3c180ae
AM		 6491 }
6492 }
6493 else
6494 expression (exp);
6495}
6496#endif
6497
d182319b 6498static void signed_cons (int size)
6482c264 6499{
d182319b
JB		 6500 if (flag_code == CODE_64BIT)
6501 cons_sign = 1;
6502 cons (size);
6503 cons_sign = -1;
6482c264
NC		 6504}
6505
d182319b 6506#ifdef TE_PE
6482c264
NC		 6507static void
6508pe_directive_secrel (dummy)
6509 int dummy ATTRIBUTE_UNUSED;
6510{
6511 expressionS exp;
6512
6513 do
6514 {
6515 expression (&exp);
6516 if (exp.X_op == O_symbol)
6517 exp.X_op = O_secrel;
6518
6519 emit_expr (&exp, 4);
6520 }
6521 while (*input_line_pointer++ == ',');
6522
6523 input_line_pointer--;
6524 demand_empty_rest_of_line ();
6525}
6482c264
NC		 6526#endif
6527
252b5132 6528static int
70e41ade 6529i386_immediate (char *imm_start)
252b5132
RH		 6530{
6531 char *save_input_line_pointer;
f3c180ae 6532 char *gotfree_input_line;
252b5132 6533 segT exp_seg = 0;
47926f60 6534 expressionS *exp;
40fb9820
L		 6535 i386_operand_type types;
6536
0dfbf9d7 6537 operand_type_set (&types, ~0);
252b5132
RH		 6538
6539 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6540 {
31b2323c
L		 6541 as_bad (_("at most %d immediate operands are allowed"),
6542 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 6543 return 0;
6544 }
6545
6546 exp = &im_expressions[i.imm_operands++];
520dc8e8 6547 i.op[this_operand].imms = exp;
252b5132
RH		 6548
6549 if (is_space_char (*imm_start))
6550 ++imm_start;
6551
6552 save_input_line_pointer = input_line_pointer;
6553 input_line_pointer = imm_start;
6554
3956db08 6555 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6556 if (gotfree_input_line)
6557 input_line_pointer = gotfree_input_line;
252b5132
RH		 6558
6559 exp_seg = expression (exp);
6560
83183c0c 6561 SKIP_WHITESPACE ();
252b5132 6562 if (*input_line_pointer)
f3c180ae 6563 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 6564
6565 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 6566 if (gotfree_input_line)
6567 free (gotfree_input_line);
252b5132 6568
3992d3b7
AM		 6569 if (exp->X_op == O_absent
6570 || exp->X_op == O_illegal
6571 || exp->X_op == O_big
6572 || (gotfree_input_line
6573 && (exp->X_op == O_constant
6574 || exp->X_op == O_register)))
252b5132 6575 {
3992d3b7 6576 as_bad (_("missing or invalid immediate expression `%s'"),
24eab124 6577 imm_start);
3992d3b7 6578 return 0;
252b5132 6579 }
3e73aa7c 6580 else if (exp->X_op == O_constant)
252b5132 6581 {
47926f60 6582 /* Size it properly later. */
40fb9820 6583 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 6584 /* If BFD64, sign extend val. */
4eed87de
AM		 6585 if (!use_rela_relocations
6586 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6587 exp->X_add_number
6588 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 6589 }
4c63da97 6590#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 6591 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 6592 && exp_seg != absolute_section
47926f60 6593 && exp_seg != text_section
24eab124
AM		 6594 && exp_seg != data_section
6595 && exp_seg != bss_section
6596 && exp_seg != undefined_section
f86103b7 6597 && !bfd_is_com_section (exp_seg))
252b5132 6598 {
d0b47220 6599 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 6600 return 0;
6601 }
6602#endif
bb8f5920
L		 6603 else if (!intel_syntax && exp->X_op == O_register)
6604 {
6605 as_bad (_("illegal immediate register operand %s"), imm_start);
6606 return 0;
6607 }
252b5132
RH		 6608 else
6609 {
6610 /* This is an address. The size of the address will be
24eab124 6611 determined later, depending on destination register,
3e73aa7c 6612 suffix, or the default for the section. */
40fb9820
L		 6613 i.types[this_operand].bitfield.imm8 = 1;
6614 i.types[this_operand].bitfield.imm16 = 1;
6615 i.types[this_operand].bitfield.imm32 = 1;
6616 i.types[this_operand].bitfield.imm32s = 1;
6617 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 6618 i.types[this_operand] = operand_type_and (i.types[this_operand],
6619 types);
252b5132
RH		 6620 }
6621
6622 return 1;
6623}
6624
551c1ca1 6625static char *
e3bb37b5 6626i386_scale (char *scale)
252b5132 6627{
551c1ca1
AM		 6628 offsetT val;
6629 char *save = input_line_pointer;
252b5132 6630
551c1ca1
AM		 6631 input_line_pointer = scale;
6632 val = get_absolute_expression ();
6633
6634 switch (val)
252b5132 6635 {
551c1ca1 6636 case 1:
252b5132
RH		 6637 i.log2_scale_factor = 0;
6638 break;
551c1ca1 6639 case 2:
252b5132
RH		 6640 i.log2_scale_factor = 1;
6641 break;
551c1ca1 6642 case 4:
252b5132
RH		 6643 i.log2_scale_factor = 2;
6644 break;
551c1ca1 6645 case 8:
252b5132
RH		 6646 i.log2_scale_factor = 3;
6647 break;
6648 default:
a724f0f4
JB		 6649 {
6650 char sep = *input_line_pointer;
6651
6652 *input_line_pointer = '\0';
6653 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6654 scale);
6655 *input_line_pointer = sep;
6656 input_line_pointer = save;
6657 return NULL;
6658 }
252b5132 6659 }
29b0f896 6660 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 6661 {
6662 as_warn (_("scale factor of %d without an index register"),
24eab124 6663 1 << i.log2_scale_factor);
252b5132 6664 i.log2_scale_factor = 0;
252b5132 6665 }
551c1ca1
AM		 6666 scale = input_line_pointer;
6667 input_line_pointer = save;
6668 return scale;
252b5132
RH		 6669}
6670
252b5132 6671static int
e3bb37b5 6672i386_displacement (char *disp_start, char *disp_end)
252b5132 6673{
29b0f896 6674 expressionS *exp;
252b5132
RH		 6675 segT exp_seg = 0;
6676 char *save_input_line_pointer;
f3c180ae 6677 char *gotfree_input_line;
40fb9820
L		 6678 int override;
6679 i386_operand_type bigdisp, types = anydisp;
3992d3b7 6680 int ret;
252b5132 6681
31b2323c
L		 6682 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6683 {
6684 as_bad (_("at most %d displacement operands are allowed"),
6685 MAX_MEMORY_OPERANDS);
6686 return 0;
6687 }
6688
0dfbf9d7 6689 operand_type_set (&bigdisp, 0);
40fb9820
L		 6690 if ((i.types[this_operand].bitfield.jumpabsolute)
6691 || (!current_templates->start->opcode_modifier.jump
6692 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 6693 {
40fb9820 6694 bigdisp.bitfield.disp32 = 1;
e05278af 6695 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 6696 if (flag_code == CODE_64BIT)
6697 {
6698 if (!override)
6699 {
6700 bigdisp.bitfield.disp32s = 1;
6701 bigdisp.bitfield.disp64 = 1;
6702 }
6703 }
6704 else if ((flag_code == CODE_16BIT) ^ override)
6705 {
6706 bigdisp.bitfield.disp32 = 0;
6707 bigdisp.bitfield.disp16 = 1;
6708 }
e05278af
JB		 6709 }
6710 else
6711 {
6712 /* For PC-relative branches, the width of the displacement
6713 is dependent upon data size, not address size. */
e05278af 6714 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 6715 if (flag_code == CODE_64BIT)
6716 {
6717 if (override || i.suffix == WORD_MNEM_SUFFIX)
6718 bigdisp.bitfield.disp16 = 1;
6719 else
6720 {
6721 bigdisp.bitfield.disp32 = 1;
6722 bigdisp.bitfield.disp32s = 1;
6723 }
6724 }
6725 else
e05278af
JB		 6726 {
6727 if (!override)
6728 override = (i.suffix == (flag_code != CODE_16BIT
6729 ? WORD_MNEM_SUFFIX
6730 : LONG_MNEM_SUFFIX));
40fb9820
L		 6731 bigdisp.bitfield.disp32 = 1;
6732 if ((flag_code == CODE_16BIT) ^ override)
6733 {
6734 bigdisp.bitfield.disp32 = 0;
6735 bigdisp.bitfield.disp16 = 1;
6736 }
e05278af 6737 }
e05278af 6738 }
c6fb90c8
L		 6739 i.types[this_operand] = operand_type_or (i.types[this_operand],
6740 bigdisp);
252b5132
RH		 6741
6742 exp = &disp_expressions[i.disp_operands];
520dc8e8 6743 i.op[this_operand].disps = exp;
252b5132
RH		 6744 i.disp_operands++;
6745 save_input_line_pointer = input_line_pointer;
6746 input_line_pointer = disp_start;
6747 END_STRING_AND_SAVE (disp_end);
6748
6749#ifndef GCC_ASM_O_HACK
6750#define GCC_ASM_O_HACK 0
6751#endif
6752#if GCC_ASM_O_HACK
6753 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 6754 if (i.types[this_operand].bitfield.baseIndex
24eab124 6755 && displacement_string_end[-1] == '+')
252b5132
RH		 6756 {
6757 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 6758 constraint within gcc asm statements.
6759 For instance:
6760
6761 #define _set_tssldt_desc(n,addr,limit,type) \
6762 __asm__ __volatile__ ( \
6763 "movw %w2,%0\n\t" \
6764 "movw %w1,2+%0\n\t" \
6765 "rorl $16,%1\n\t" \
6766 "movb %b1,4+%0\n\t" \
6767 "movb %4,5+%0\n\t" \
6768 "movb $0,6+%0\n\t" \
6769 "movb %h1,7+%0\n\t" \
6770 "rorl $16,%1" \
6771 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6772
6773 This works great except that the output assembler ends
6774 up looking a bit weird if it turns out that there is
6775 no offset. You end up producing code that looks like:
6776
6777 #APP
6778 movw $235,(%eax)
6779 movw %dx,2+(%eax)
6780 rorl $16,%edx
6781 movb %dl,4+(%eax)
6782 movb $137,5+(%eax)
6783 movb $0,6+(%eax)
6784 movb %dh,7+(%eax)
6785 rorl $16,%edx
6786 #NO_APP
6787
47926f60 6788 So here we provide the missing zero. */
24eab124
AM		 6789
6790 *displacement_string_end = '0';
252b5132
RH		 6791 }
6792#endif
3956db08 6793 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6794 if (gotfree_input_line)
6795 input_line_pointer = gotfree_input_line;
252b5132 6796
24eab124 6797 exp_seg = expression (exp);
252b5132 6798
636c26b0
AM		 6799 SKIP_WHITESPACE ();
6800 if (*input_line_pointer)
6801 as_bad (_("junk `%s' after expression"), input_line_pointer);
6802#if GCC_ASM_O_HACK
6803 RESTORE_END_STRING (disp_end + 1);
6804#endif
636c26b0 6805 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 6806 if (gotfree_input_line)
6807 free (gotfree_input_line);
3992d3b7 6808 ret = 1;
636c26b0 6809
24eab124
AM		 6810 /* We do this to make sure that the section symbol is in
6811 the symbol table. We will ultimately change the relocation
47926f60 6812 to be relative to the beginning of the section. */
1ae12ab7 6813 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 6814 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6815 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 6816 {
636c26b0 6817 if (exp->X_op != O_symbol)
3992d3b7 6818 goto inv_disp;
636c26b0 6819
e5cb08ac 6820 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 6821 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6822 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 6823 exp->X_op = O_subtract;
6824 exp->X_op_symbol = GOT_symbol;
1ae12ab7 6825 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 6826 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 6827 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6828 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 6829 else
29b0f896 6830 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 6831 }
252b5132 6832
3992d3b7
AM		 6833 else if (exp->X_op == O_absent
6834 || exp->X_op == O_illegal
6835 || exp->X_op == O_big
6836 || (gotfree_input_line
6837 && (exp->X_op == O_constant
6838 || exp->X_op == O_register)))
2daf4fd8 6839 {
3992d3b7
AM		 6840 inv_disp:
6841 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 6842 disp_start);
3992d3b7 6843 ret = 0;
2daf4fd8
AM		 6844 }
6845
4c63da97 6846#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 6847 else if (exp->X_op != O_constant
6848 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6849 && exp_seg != absolute_section
6850 && exp_seg != text_section
6851 && exp_seg != data_section
6852 && exp_seg != bss_section
6853 && exp_seg != undefined_section
6854 && !bfd_is_com_section (exp_seg))
24eab124 6855 {
d0b47220 6856 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 6857 ret = 0;
24eab124 6858 }
252b5132 6859#endif
3956db08 6860
3992d3b7
AM		 6861 RESTORE_END_STRING (disp_end);
6862
40fb9820
L		 6863 /* Check if this is a displacement only operand. */
6864 bigdisp = i.types[this_operand];
6865 bigdisp.bitfield.disp8 = 0;
6866 bigdisp.bitfield.disp16 = 0;
6867 bigdisp.bitfield.disp32 = 0;
6868 bigdisp.bitfield.disp32s = 0;
6869 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 6870 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 6871 i.types[this_operand] = operand_type_and (i.types[this_operand],
6872 types);
3956db08 6873
3992d3b7 6874 return ret;
252b5132
RH		 6875}
6876
eecb386c 6877/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 6878 Return 1 on success, 0 on a failure. */
6879
252b5132 6880static int
e3bb37b5 6881i386_index_check (const char *operand_string)
252b5132 6882{
3e73aa7c 6883 int ok;
fc0763e6 6884 const char *kind = "base/index";
24eab124 6885#if INFER_ADDR_PREFIX
eecb386c
AM		 6886 int fudged = 0;
6887
24eab124
AM		 6888 tryprefix:
6889#endif
3e73aa7c 6890 ok = 1;
fc0763e6
JB		 6891 if (current_templates->start->opcode_modifier.isstring
6892 && !current_templates->start->opcode_modifier.immext
6893 && (current_templates->end[-1].opcode_modifier.isstring
6894 || i.mem_operands))
6895 {
6896 /* Memory operands of string insns are special in that they only allow
6897 a single register (rDI, rSI, or rBX) as their memory address. */
6898 unsigned int expected;
6899
6900 kind = "string address";
6901
6902 if (current_templates->start->opcode_modifier.w)
6903 {
6904 i386_operand_type type = current_templates->end[-1].operand_types[0];
6905
6906 if (!type.bitfield.baseindex
6907 || ((!i.mem_operands != !intel_syntax)
6908 && current_templates->end[-1].operand_types[1]
6909 .bitfield.baseindex))
6910 type = current_templates->end[-1].operand_types[1];
6911 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
6912 }
6913 else
6914 expected = 3 /* rBX */;
6915
6916 if (!i.base_reg || i.index_reg
6917 || operand_type_check (i.types[this_operand], disp))
6918 ok = -1;
6919 else if (!(flag_code == CODE_64BIT
6920 ? i.prefix[ADDR_PREFIX]
6921 ? i.base_reg->reg_type.bitfield.reg32
6922 : i.base_reg->reg_type.bitfield.reg64
6923 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6924 ? i.base_reg->reg_type.bitfield.reg32
6925 : i.base_reg->reg_type.bitfield.reg16))
6926 ok = 0;
6927 else if (i.base_reg->reg_num != expected)
6928 ok = -1;
6929
6930 if (ok < 0)
6931 {
6932 unsigned int j;
6933
6934 for (j = 0; j < i386_regtab_size; ++j)
6935 if ((flag_code == CODE_64BIT
6936 ? i.prefix[ADDR_PREFIX]
6937 ? i386_regtab[j].reg_type.bitfield.reg32
6938 : i386_regtab[j].reg_type.bitfield.reg64
6939 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6940 ? i386_regtab[j].reg_type.bitfield.reg32
6941 : i386_regtab[j].reg_type.bitfield.reg16)
6942 && i386_regtab[j].reg_num == expected)
6943 break;
6944 assert (j < i386_regtab_size);
6945 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6946 operand_string,
6947 intel_syntax ? '[' : '(',
6948 register_prefix,
6949 i386_regtab[j].reg_name,
6950 intel_syntax ? ']' : ')');
6951 ok = 1;
6952 }
6953 }
6954 else if (flag_code == CODE_64BIT)
64e74474 6955 {
64e74474 6956 if ((i.base_reg
40fb9820
L		 6957 && ((i.prefix[ADDR_PREFIX] == 0
6958 && !i.base_reg->reg_type.bitfield.reg64)
6959 || (i.prefix[ADDR_PREFIX]
6960 && !i.base_reg->reg_type.bitfield.reg32))
6961 && (i.index_reg
9a04903e
JB		 6962 || i.base_reg->reg_num !=
6963 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 6964 || (i.index_reg
40fb9820
L		 6965 && (!i.index_reg->reg_type.bitfield.baseindex
6966 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 6967 && i.index_reg->reg_num != RegRiz
6968 && !i.index_reg->reg_type.bitfield.reg64
6969 )
40fb9820 6970 || (i.prefix[ADDR_PREFIX]
db51cc60 6971 && i.index_reg->reg_num != RegEiz
40fb9820 6972 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 6973 ok = 0;
3e73aa7c
JH		 6974 }
6975 else
6976 {
6977 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6978 {
6979 /* 16bit checks. */
6980 if ((i.base_reg
40fb9820
L		 6981 && (!i.base_reg->reg_type.bitfield.reg16
6982 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 6983 || (i.index_reg
40fb9820
L		 6984 && (!i.index_reg->reg_type.bitfield.reg16
6985 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 6986 || !(i.base_reg
6987 && i.base_reg->reg_num < 6
6988 && i.index_reg->reg_num >= 6
6989 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 6990 ok = 0;
6991 }
6992 else
e5cb08ac 6993 {
3e73aa7c
JH		 6994 /* 32bit checks. */
6995 if ((i.base_reg
40fb9820 6996 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 6997 || (i.index_reg
db51cc60
L		 6998 && ((!i.index_reg->reg_type.bitfield.reg32
6999 && i.index_reg->reg_num != RegEiz)
40fb9820 7000 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 7001 ok = 0;
3e73aa7c
JH		 7002 }
7003 }
7004 if (!ok)
24eab124
AM		 7005 {
7006#if INFER_ADDR_PREFIX
fc0763e6 7007 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
24eab124
AM		 7008 {
7009 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
7010 i.prefixes += 1;
b23bac36
AM		 7011 /* Change the size of any displacement too. At most one of
7012 Disp16 or Disp32 is set.
7013 FIXME. There doesn't seem to be any real need for separate
7014 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 7015 Removing them would probably clean up the code quite a lot. */
4eed87de 7016 if (flag_code != CODE_64BIT
40fb9820
L		 7017 && (i.types[this_operand].bitfield.disp16
7018 || i.types[this_operand].bitfield.disp32))
7019 i.types[this_operand]
c6fb90c8 7020 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 7021 fudged = 1;
24eab124
AM		 7022 goto tryprefix;
7023 }
eecb386c 7024 if (fudged)
fc0763e6
JB		 7025 as_bad (_("`%s' is not a valid %s expression"),
7026 operand_string,
7027 kind);
eecb386c 7028 else
c388dee8 7029#endif
fc0763e6 7030 as_bad (_("`%s' is not a valid %s-bit %s expression"),
eecb386c 7031 operand_string,
fc0763e6
JB		 7032 flag_code_names[i.prefix[ADDR_PREFIX]
7033 ? flag_code == CODE_32BIT
7034 ? CODE_16BIT
7035 : CODE_32BIT
7036 : flag_code],
7037 kind);
24eab124 7038 }
20f0a1fc 7039 return ok;
24eab124 7040}
252b5132 7041
fc0763e6 7042/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 7043 on error. */
252b5132 7044
252b5132 7045static int
a7619375 7046i386_att_operand (char *operand_string)
252b5132 7047{
af6bdddf
AM		 7048 const reg_entry *r;
7049 char *end_op;
24eab124 7050 char *op_string = operand_string;
252b5132 7051
24eab124 7052 if (is_space_char (*op_string))
252b5132
RH		 7053 ++op_string;
7054
24eab124 7055 /* We check for an absolute prefix (differentiating,
47926f60 7056 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 7057 if (*op_string == ABSOLUTE_PREFIX)
7058 {
7059 ++op_string;
7060 if (is_space_char (*op_string))
7061 ++op_string;
40fb9820 7062 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 7063 }
252b5132 7064
47926f60 7065 /* Check if operand is a register. */
4d1bb795 7066 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 7067 {
40fb9820
L		 7068 i386_operand_type temp;
7069
24eab124
AM		 7070 /* Check for a segment override by searching for ':' after a
7071 segment register. */
7072 op_string = end_op;
7073 if (is_space_char (*op_string))
7074 ++op_string;
40fb9820
L		 7075 if (*op_string == ':'
7076 && (r->reg_type.bitfield.sreg2
7077 || r->reg_type.bitfield.sreg3))
24eab124
AM		 7078 {
7079 switch (r->reg_num)
7080 {
7081 case 0:
7082 i.seg[i.mem_operands] = &es;
7083 break;
7084 case 1:
7085 i.seg[i.mem_operands] = &cs;
7086 break;
7087 case 2:
7088 i.seg[i.mem_operands] = &ss;
7089 break;
7090 case 3:
7091 i.seg[i.mem_operands] = &ds;
7092 break;
7093 case 4:
7094 i.seg[i.mem_operands] = &fs;
7095 break;
7096 case 5:
7097 i.seg[i.mem_operands] = &gs;
7098 break;
7099 }
252b5132 7100
24eab124 7101 /* Skip the ':' and whitespace. */
252b5132
RH		 7102 ++op_string;
7103 if (is_space_char (*op_string))
24eab124 7104 ++op_string;
252b5132 7105
24eab124
AM		 7106 if (!is_digit_char (*op_string)
7107 && !is_identifier_char (*op_string)
7108 && *op_string != '('
7109 && *op_string != ABSOLUTE_PREFIX)
7110 {
7111 as_bad (_("bad memory operand `%s'"), op_string);
7112 return 0;
7113 }
47926f60 7114 /* Handle case of %es:*foo. */
24eab124
AM		 7115 if (*op_string == ABSOLUTE_PREFIX)
7116 {
7117 ++op_string;
7118 if (is_space_char (*op_string))
7119 ++op_string;
40fb9820 7120 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 7121 }
7122 goto do_memory_reference;
7123 }
7124 if (*op_string)
7125 {
d0b47220 7126 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 7127 return 0;
7128 }
40fb9820
L		 7129 temp = r->reg_type;
7130 temp.bitfield.baseindex = 0;
c6fb90c8
L		 7131 i.types[this_operand] = operand_type_or (i.types[this_operand],
7132 temp);
7d5e4556 7133 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 7134 i.op[this_operand].regs = r;
24eab124
AM		 7135 i.reg_operands++;
7136 }
af6bdddf
AM		 7137 else if (*op_string == REGISTER_PREFIX)
7138 {
7139 as_bad (_("bad register name `%s'"), op_string);
7140 return 0;
7141 }
24eab124 7142 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 7143 {
24eab124 7144 ++op_string;
40fb9820 7145 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 7146 {
d0b47220 7147 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 7148 return 0;
7149 }
7150 if (!i386_immediate (op_string))
7151 return 0;
7152 }
7153 else if (is_digit_char (*op_string)
7154 || is_identifier_char (*op_string)
e5cb08ac 7155 || *op_string == '(')
24eab124 7156 {
47926f60 7157 /* This is a memory reference of some sort. */
af6bdddf 7158 char *base_string;
252b5132 7159
47926f60 7160 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 7161 char *displacement_string_start;
7162 char *displacement_string_end;
252b5132 7163
24eab124 7164 do_memory_reference:
24eab124 7165 if ((i.mem_operands == 1
40fb9820 7166 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 7167 || i.mem_operands == 2)
7168 {
7169 as_bad (_("too many memory references for `%s'"),
7170 current_templates->start->name);
7171 return 0;
7172 }
252b5132 7173
24eab124
AM		 7174 /* Check for base index form. We detect the base index form by
7175 looking for an ')' at the end of the operand, searching
7176 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7177 after the '('. */
af6bdddf 7178 base_string = op_string + strlen (op_string);
c3332e24 7179
af6bdddf
AM		 7180 --base_string;
7181 if (is_space_char (*base_string))
7182 --base_string;
252b5132 7183
47926f60 7184 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 7185 displacement_string_start = op_string;
7186 displacement_string_end = base_string + 1;
252b5132 7187
24eab124
AM		 7188 if (*base_string == ')')
7189 {
af6bdddf 7190 char *temp_string;
24eab124
AM		 7191 unsigned int parens_balanced = 1;
7192 /* We've already checked that the number of left & right ()'s are
47926f60 7193 equal, so this loop will not be infinite. */
24eab124
AM		 7194 do
7195 {
7196 base_string--;
7197 if (*base_string == ')')
7198 parens_balanced++;
7199 if (*base_string == '(')
7200 parens_balanced--;
7201 }
7202 while (parens_balanced);
c3332e24 7203
af6bdddf 7204 temp_string = base_string;
c3332e24 7205
24eab124 7206 /* Skip past '(' and whitespace. */
252b5132
RH		 7207 ++base_string;
7208 if (is_space_char (*base_string))
24eab124 7209 ++base_string;
252b5132 7210
af6bdddf 7211 if (*base_string == ','
4eed87de
AM		 7212 || ((i.base_reg = parse_register (base_string, &end_op))
7213 != NULL))
252b5132 7214 {
af6bdddf 7215 displacement_string_end = temp_string;
252b5132 7216
40fb9820 7217 i.types[this_operand].bitfield.baseindex = 1;
252b5132 7218
af6bdddf 7219 if (i.base_reg)
24eab124 7220 {
24eab124
AM		 7221 base_string = end_op;
7222 if (is_space_char (*base_string))
7223 ++base_string;
af6bdddf
AM		 7224 }
7225
7226 /* There may be an index reg or scale factor here. */
7227 if (*base_string == ',')
7228 {
7229 ++base_string;
7230 if (is_space_char (*base_string))
7231 ++base_string;
7232
4eed87de
AM		 7233 if ((i.index_reg = parse_register (base_string, &end_op))
7234 != NULL)
24eab124 7235 {
af6bdddf 7236 base_string = end_op;
24eab124
AM		 7237 if (is_space_char (*base_string))
7238 ++base_string;
af6bdddf
AM		 7239 if (*base_string == ',')
7240 {
7241 ++base_string;
7242 if (is_space_char (*base_string))
7243 ++base_string;
7244 }
e5cb08ac 7245 else if (*base_string != ')')
af6bdddf 7246 {
4eed87de
AM		 7247 as_bad (_("expecting `,' or `)' "
7248 "after index register in `%s'"),
af6bdddf
AM		 7249 operand_string);
7250 return 0;
7251 }
24eab124 7252 }
af6bdddf 7253 else if (*base_string == REGISTER_PREFIX)
24eab124 7254 {
af6bdddf 7255 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 7256 return 0;
7257 }
252b5132 7258
47926f60 7259 /* Check for scale factor. */
551c1ca1 7260 if (*base_string != ')')
af6bdddf 7261 {
551c1ca1
AM		 7262 char *end_scale = i386_scale (base_string);
7263
7264 if (!end_scale)
af6bdddf 7265 return 0;
24eab124 7266
551c1ca1 7267 base_string = end_scale;
af6bdddf
AM		 7268 if (is_space_char (*base_string))
7269 ++base_string;
7270 if (*base_string != ')')
7271 {
4eed87de
AM		 7272 as_bad (_("expecting `)' "
7273 "after scale factor in `%s'"),
af6bdddf
AM		 7274 operand_string);
7275 return 0;
7276 }
7277 }
7278 else if (!i.index_reg)
24eab124 7279 {
4eed87de
AM		 7280 as_bad (_("expecting index register or scale factor "
7281 "after `,'; got '%c'"),
af6bdddf 7282 *base_string);
24eab124
AM		 7283 return 0;
7284 }
7285 }
af6bdddf 7286 else if (*base_string != ')')
24eab124 7287 {
4eed87de
AM		 7288 as_bad (_("expecting `,' or `)' "
7289 "after base register in `%s'"),
af6bdddf 7290 operand_string);
24eab124
AM		 7291 return 0;
7292 }
c3332e24 7293 }
af6bdddf 7294 else if (*base_string == REGISTER_PREFIX)
c3332e24 7295 {
af6bdddf 7296 as_bad (_("bad register name `%s'"), base_string);
24eab124 7297 return 0;
c3332e24 7298 }
24eab124
AM		 7299 }
7300
7301 /* If there's an expression beginning the operand, parse it,
7302 assuming displacement_string_start and
7303 displacement_string_end are meaningful. */
7304 if (displacement_string_start != displacement_string_end)
7305 {
7306 if (!i386_displacement (displacement_string_start,
7307 displacement_string_end))
7308 return 0;
7309 }
7310
7311 /* Special case for (%dx) while doing input/output op. */
7312 if (i.base_reg
0dfbf9d7
L		 7313 && operand_type_equal (&i.base_reg->reg_type,
7314 &reg16_inoutportreg)
24eab124
AM		 7315 && i.index_reg == 0
7316 && i.log2_scale_factor == 0
7317 && i.seg[i.mem_operands] == 0
40fb9820 7318 && !operand_type_check (i.types[this_operand], disp))
24eab124 7319 {
65da13b5 7320 i.types[this_operand] = inoutportreg;
24eab124
AM		 7321 return 1;
7322 }
7323
eecb386c
AM		 7324 if (i386_index_check (operand_string) == 0)
7325 return 0;
5c07affc 7326 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 7327 i.mem_operands++;
7328 }
7329 else
ce8a8b2f
AM		 7330 {
7331 /* It's not a memory operand; argh! */
24eab124
AM		 7332 as_bad (_("invalid char %s beginning operand %d `%s'"),
7333 output_invalid (*op_string),
7334 this_operand + 1,
7335 op_string);
7336 return 0;
7337 }
47926f60 7338 return 1; /* Normal return. */
252b5132
RH		 7339}
7340\f
ee7fcc42
AM		 7341/* md_estimate_size_before_relax()
7342
7343 Called just before relax() for rs_machine_dependent frags. The x86
7344 assembler uses these frags to handle variable size jump
7345 instructions.
7346
7347 Any symbol that is now undefined will not become defined.
7348 Return the correct fr_subtype in the frag.
7349 Return the initial "guess for variable size of frag" to caller.
7350 The guess is actually the growth beyond the fixed part. Whatever
7351 we do to grow the fixed or variable part contributes to our
7352 returned value. */
7353
252b5132
RH		 7354int
7355md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 7356 fragS *fragP;
7357 segT segment;
252b5132 7358{
252b5132 7359 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 7360 check for un-relaxable symbols. On an ELF system, we can't relax
7361 an externally visible symbol, because it may be overridden by a
7362 shared library. */
7363 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 7364#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7365 || (IS_ELF
31312f95
AM		 7366 && (S_IS_EXTERNAL (fragP->fr_symbol)
7367 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 7368#endif
7369 )
252b5132 7370 {
b98ef147
AM		 7371 /* Symbol is undefined in this segment, or we need to keep a
7372 reloc so that weak symbols can be overridden. */
7373 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 7374 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 7375 unsigned char *opcode;
7376 int old_fr_fix;
f6af82bd 7377
ee7fcc42
AM		 7378 if (fragP->fr_var != NO_RELOC)
7379 reloc_type = fragP->fr_var;
b98ef147 7380 else if (size == 2)
f6af82bd
AM		 7381 reloc_type = BFD_RELOC_16_PCREL;
7382 else
7383 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7384
ee7fcc42
AM		 7385 old_fr_fix = fragP->fr_fix;
7386 opcode = (unsigned char *) fragP->fr_opcode;
7387
fddf5b5b 7388 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7389 {
fddf5b5b
AM		 7390 case UNCOND_JUMP:
7391 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7392 opcode[0] = 0xe9;
252b5132 7393 fragP->fr_fix += size;
062cd5e7
AS		 7394 fix_new (fragP, old_fr_fix, size,
7395 fragP->fr_symbol,
7396 fragP->fr_offset, 1,
7397 reloc_type);
252b5132
RH		 7398 break;
7399
fddf5b5b 7400 case COND_JUMP86:
412167cb
AM		 7401 if (size == 2
7402 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 7403 {
7404 /* Negate the condition, and branch past an
7405 unconditional jump. */
7406 opcode[0] ^= 1;
7407 opcode[1] = 3;
7408 /* Insert an unconditional jump. */
7409 opcode[2] = 0xe9;
7410 /* We added two extra opcode bytes, and have a two byte
7411 offset. */
7412 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7413 fix_new (fragP, old_fr_fix + 2, 2,
7414 fragP->fr_symbol,
7415 fragP->fr_offset, 1,
7416 reloc_type);
fddf5b5b
AM		 7417 break;
7418 }
7419 /* Fall through. */
7420
7421 case COND_JUMP:
412167cb
AM		 7422 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7423 {
3e02c1cc
AM		 7424 fixS *fixP;
7425
412167cb 7426 fragP->fr_fix += 1;
3e02c1cc
AM		 7427 fixP = fix_new (fragP, old_fr_fix, 1,
7428 fragP->fr_symbol,
7429 fragP->fr_offset, 1,
7430 BFD_RELOC_8_PCREL);
7431 fixP->fx_signed = 1;
412167cb
AM		 7432 break;
7433 }
93c2a809 7434
24eab124 7435 /* This changes the byte-displacement jump 0x7N
fddf5b5b 7436 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 7437 opcode[1] = opcode[0] + 0x10;
f6af82bd 7438 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 7439 /* We've added an opcode byte. */
7440 fragP->fr_fix += 1 + size;
062cd5e7
AS		 7441 fix_new (fragP, old_fr_fix + 1, size,
7442 fragP->fr_symbol,
7443 fragP->fr_offset, 1,
7444 reloc_type);
252b5132 7445 break;
fddf5b5b
AM		 7446
7447 default:
7448 BAD_CASE (fragP->fr_subtype);
7449 break;
252b5132
RH		 7450 }
7451 frag_wane (fragP);
ee7fcc42 7452 return fragP->fr_fix - old_fr_fix;
252b5132 7453 }
93c2a809 7454
93c2a809
AM		 7455 /* Guess size depending on current relax state. Initially the relax
7456 state will correspond to a short jump and we return 1, because
7457 the variable part of the frag (the branch offset) is one byte
7458 long. However, we can relax a section more than once and in that
7459 case we must either set fr_subtype back to the unrelaxed state,
7460 or return the value for the appropriate branch. */
7461 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 7462}
7463
47926f60
KH		 7464/* Called after relax() is finished.
7465
7466 In: Address of frag.
7467 fr_type == rs_machine_dependent.
7468 fr_subtype is what the address relaxed to.
7469
7470 Out: Any fixSs and constants are set up.
7471 Caller will turn frag into a ".space 0". */
7472
252b5132
RH		 7473void
7474md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 7475 bfd *abfd ATTRIBUTE_UNUSED;
7476 segT sec ATTRIBUTE_UNUSED;
29b0f896 7477 fragS *fragP;
252b5132 7478{
29b0f896 7479 unsigned char *opcode;
252b5132 7480 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 7481 offsetT target_address;
7482 offsetT opcode_address;
252b5132 7483 unsigned int extension = 0;
847f7ad4 7484 offsetT displacement_from_opcode_start;
252b5132
RH		 7485
7486 opcode = (unsigned char *) fragP->fr_opcode;
7487
47926f60 7488 /* Address we want to reach in file space. */
252b5132 7489 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 7490
47926f60 7491 /* Address opcode resides at in file space. */
252b5132
RH		 7492 opcode_address = fragP->fr_address + fragP->fr_fix;
7493
47926f60 7494 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 7495 displacement_from_opcode_start = target_address - opcode_address;
7496
fddf5b5b 7497 if ((fragP->fr_subtype & BIG) == 0)
252b5132 7498 {
47926f60
KH		 7499 /* Don't have to change opcode. */
7500 extension = 1; /* 1 opcode + 1 displacement */
252b5132 7501 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 7502 }
7503 else
7504 {
7505 if (no_cond_jump_promotion
7506 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 7507 as_warn_where (fragP->fr_file, fragP->fr_line,
7508 _("long jump required"));
252b5132 7509
fddf5b5b
AM		 7510 switch (fragP->fr_subtype)
7511 {
7512 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7513 extension = 4; /* 1 opcode + 4 displacement */
7514 opcode[0] = 0xe9;
7515 where_to_put_displacement = &opcode[1];
7516 break;
252b5132 7517
fddf5b5b
AM		 7518 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7519 extension = 2; /* 1 opcode + 2 displacement */
7520 opcode[0] = 0xe9;
7521 where_to_put_displacement = &opcode[1];
7522 break;
252b5132 7523
fddf5b5b
AM		 7524 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7525 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7526 extension = 5; /* 2 opcode + 4 displacement */
7527 opcode[1] = opcode[0] + 0x10;
7528 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7529 where_to_put_displacement = &opcode[2];
7530 break;
252b5132 7531
fddf5b5b
AM		 7532 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7533 extension = 3; /* 2 opcode + 2 displacement */
7534 opcode[1] = opcode[0] + 0x10;
7535 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7536 where_to_put_displacement = &opcode[2];
7537 break;
252b5132 7538
fddf5b5b
AM		 7539 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7540 extension = 4;
7541 opcode[0] ^= 1;
7542 opcode[1] = 3;
7543 opcode[2] = 0xe9;
7544 where_to_put_displacement = &opcode[3];
7545 break;
7546
7547 default:
7548 BAD_CASE (fragP->fr_subtype);
7549 break;
7550 }
252b5132 7551 }
fddf5b5b 7552
7b81dfbb
AJ		 7553 /* If size if less then four we are sure that the operand fits,
7554 but if it's 4, then it could be that the displacement is larger
7555 then -/+ 2GB. */
7556 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7557 && object_64bit
7558 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 7559 + ((addressT) 1 << 31))
7560 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 7561 {
7562 as_bad_where (fragP->fr_file, fragP->fr_line,
7563 _("jump target out of range"));
7564 /* Make us emit 0. */
7565 displacement_from_opcode_start = extension;
7566 }
47926f60 7567 /* Now put displacement after opcode. */
252b5132
RH		 7568 md_number_to_chars ((char *) where_to_put_displacement,
7569 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 7570 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 7571 fragP->fr_fix += extension;
7572}
7573\f
252b5132
RH		 7574/* Apply a fixup (fixS) to segment data, once it has been determined
7575 by our caller that we have all the info we need to fix it up.
7576
7577 On the 386, immediates, displacements, and data pointers are all in
7578 the same (little-endian) format, so we don't need to care about which
7579 we are handling. */
7580
94f592af 7581void
55cf6793 7582md_apply_fix (fixP, valP, seg)
47926f60
KH		 7583 /* The fix we're to put in. */
7584 fixS *fixP;
47926f60 7585 /* Pointer to the value of the bits. */
c6682705 7586 valueT *valP;
47926f60
KH		 7587 /* Segment fix is from. */
7588 segT seg ATTRIBUTE_UNUSED;
252b5132 7589{
94f592af 7590 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 7591 valueT value = *valP;
252b5132 7592
f86103b7 7593#if !defined (TE_Mach)
93382f6d
AM		 7594 if (fixP->fx_pcrel)
7595 {
7596 switch (fixP->fx_r_type)
7597 {
5865bb77
ILT		 7598 default:
7599 break;
7600
d6ab8113
JB		 7601 case BFD_RELOC_64:
7602 fixP->fx_r_type = BFD_RELOC_64_PCREL;
7603 break;
93382f6d 7604 case BFD_RELOC_32:
ae8887b5 7605 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 7606 fixP->fx_r_type = BFD_RELOC_32_PCREL;
7607 break;
7608 case BFD_RELOC_16:
7609 fixP->fx_r_type = BFD_RELOC_16_PCREL;
7610 break;
7611 case BFD_RELOC_8:
7612 fixP->fx_r_type = BFD_RELOC_8_PCREL;
7613 break;
7614 }
7615 }
252b5132 7616
a161fe53 7617 if (fixP->fx_addsy != NULL
31312f95 7618 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 7619 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 7620 || fixP->fx_r_type == BFD_RELOC_16_PCREL
7621 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7622 && !use_rela_relocations)
252b5132 7623 {
31312f95
AM		 7624 /* This is a hack. There should be a better way to handle this.
7625 This covers for the fact that bfd_install_relocation will
7626 subtract the current location (for partial_inplace, PC relative
7627 relocations); see more below. */
252b5132 7628#ifndef OBJ_AOUT
718ddfc0 7629 if (IS_ELF
252b5132
RH		 7630#ifdef TE_PE
7631 || OUTPUT_FLAVOR == bfd_target_coff_flavour
7632#endif
7633 )
7634 value += fixP->fx_where + fixP->fx_frag->fr_address;
7635#endif
7636#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7637 if (IS_ELF)
252b5132 7638 {
6539b54b 7639 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 7640
6539b54b 7641 if ((sym_seg == seg
2f66722d 7642 || (symbol_section_p (fixP->fx_addsy)
6539b54b 7643 && sym_seg != absolute_section))
ae6063d4 7644 && !generic_force_reloc (fixP))
2f66722d
AM		 7645 {
7646 /* Yes, we add the values in twice. This is because
6539b54b
AM		 7647 bfd_install_relocation subtracts them out again. I think
7648 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 7649 it. FIXME. */
7650 value += fixP->fx_where + fixP->fx_frag->fr_address;
7651 }
252b5132
RH		 7652 }
7653#endif
7654#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 7655 /* For some reason, the PE format does not store a
7656 section address offset for a PC relative symbol. */
7657 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 7658 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 7659 value += md_pcrel_from (fixP);
7660#endif
7661 }
7662
7663 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 7664 and we must not disappoint it. */
252b5132 7665#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7666 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 7667 switch (fixP->fx_r_type)
7668 {
7669 case BFD_RELOC_386_PLT32:
3e73aa7c 7670 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 7671 /* Make the jump instruction point to the address of the operand. At
7672 runtime we merely add the offset to the actual PLT entry. */
7673 value = -4;
7674 break;
31312f95 7675
13ae64f3
JJ		 7676 case BFD_RELOC_386_TLS_GD:
7677 case BFD_RELOC_386_TLS_LDM:
13ae64f3 7678 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7679 case BFD_RELOC_386_TLS_IE:
7680 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 7681 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 7682 case BFD_RELOC_X86_64_TLSGD:
7683 case BFD_RELOC_X86_64_TLSLD:
7684 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 7685 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 7686 value = 0; /* Fully resolved at runtime. No addend. */
7687 /* Fallthrough */
7688 case BFD_RELOC_386_TLS_LE:
7689 case BFD_RELOC_386_TLS_LDO_32:
7690 case BFD_RELOC_386_TLS_LE_32:
7691 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7692 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 7693 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 7694 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 7695 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7696 break;
7697
67a4f2b7
AO		 7698 case BFD_RELOC_386_TLS_DESC_CALL:
7699 case BFD_RELOC_X86_64_TLSDESC_CALL:
7700 value = 0; /* Fully resolved at runtime. No addend. */
7701 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7702 fixP->fx_done = 0;
7703 return;
7704
00f7efb6
JJ		 7705 case BFD_RELOC_386_GOT32:
7706 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 7707 value = 0; /* Fully resolved at runtime. No addend. */
7708 break;
47926f60
KH		 7709
7710 case BFD_RELOC_VTABLE_INHERIT:
7711 case BFD_RELOC_VTABLE_ENTRY:
7712 fixP->fx_done = 0;
94f592af 7713 return;
47926f60
KH		 7714
7715 default:
7716 break;
7717 }
7718#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 7719 *valP = value;
f86103b7 7720#endif /* !defined (TE_Mach) */
3e73aa7c 7721
3e73aa7c 7722 /* Are we finished with this relocation now? */
c6682705 7723 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 7724 fixP->fx_done = 1;
7725 else if (use_rela_relocations)
7726 {
7727 fixP->fx_no_overflow = 1;
062cd5e7
AS		 7728 /* Remember value for tc_gen_reloc. */
7729 fixP->fx_addnumber = value;
3e73aa7c
JH		 7730 value = 0;
7731 }
f86103b7 7732
94f592af 7733 md_number_to_chars (p, value, fixP->fx_size);
252b5132 7734}
252b5132 7735\f
252b5132 7736char *
499ac353 7737md_atof (int type, char *litP, int *sizeP)
252b5132 7738{
499ac353
NC		 7739 /* This outputs the LITTLENUMs in REVERSE order;
7740 in accord with the bigendian 386. */
7741 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 7742}
7743\f
2d545b82 7744static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 7745
252b5132 7746static char *
e3bb37b5 7747output_invalid (int c)
252b5132 7748{
3882b010 7749 if (ISPRINT (c))
f9f21a03
L		 7750 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7751 "'%c'", c);
252b5132 7752 else
f9f21a03 7753 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 7754 "(0x%x)", (unsigned char) c);
252b5132
RH		 7755 return output_invalid_buf;
7756}
7757
af6bdddf 7758/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 7759
7760static const reg_entry *
4d1bb795 7761parse_real_register (char *reg_string, char **end_op)
252b5132 7762{
af6bdddf
AM		 7763 char *s = reg_string;
7764 char *p;
252b5132
RH		 7765 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7766 const reg_entry *r;
7767
7768 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7769 if (*s == REGISTER_PREFIX)
7770 ++s;
7771
7772 if (is_space_char (*s))
7773 ++s;
7774
7775 p = reg_name_given;
af6bdddf 7776 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 7777 {
7778 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 7779 return (const reg_entry *) NULL;
7780 s++;
252b5132
RH		 7781 }
7782
6588847e
DN		 7783 /* For naked regs, make sure that we are not dealing with an identifier.
7784 This prevents confusing an identifier like `eax_var' with register
7785 `eax'. */
7786 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7787 return (const reg_entry *) NULL;
7788
af6bdddf 7789 *end_op = s;
252b5132
RH		 7790
7791 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7792
5f47d35b 7793 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 7794 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 7795 {
5f47d35b
AM		 7796 if (is_space_char (*s))
7797 ++s;
7798 if (*s == '(')
7799 {
af6bdddf 7800 ++s;
5f47d35b
AM		 7801 if (is_space_char (*s))
7802 ++s;
7803 if (*s >= '0' && *s <= '7')
7804 {
db557034 7805 int fpr = *s - '0';
af6bdddf 7806 ++s;
5f47d35b
AM		 7807 if (is_space_char (*s))
7808 ++s;
7809 if (*s == ')')
7810 {
7811 *end_op = s + 1;
db557034
AM		 7812 r = hash_find (reg_hash, "st(0)");
7813 know (r);
7814 return r + fpr;
5f47d35b 7815 }
5f47d35b 7816 }
47926f60 7817 /* We have "%st(" then garbage. */
5f47d35b
AM		 7818 return (const reg_entry *) NULL;
7819 }
7820 }
7821
a60de03c
JB		 7822 if (r == NULL || allow_pseudo_reg)
7823 return r;
7824
0dfbf9d7 7825 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 7826 return (const reg_entry *) NULL;
7827
192dc9c6
JB		 7828 if ((r->reg_type.bitfield.reg32
7829 || r->reg_type.bitfield.sreg3
7830 || r->reg_type.bitfield.control
7831 || r->reg_type.bitfield.debug
7832 || r->reg_type.bitfield.test)
7833 && !cpu_arch_flags.bitfield.cpui386)
7834 return (const reg_entry *) NULL;
7835
7836 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
7837 return (const reg_entry *) NULL;
7838
7839 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
7840 return (const reg_entry *) NULL;
7841
40f12533
L		 7842 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
7843 return (const reg_entry *) NULL;
7844
db51cc60 7845 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 7846 if (!allow_index_reg
db51cc60
L		 7847 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7848 return (const reg_entry *) NULL;
7849
a60de03c
JB		 7850 if (((r->reg_flags & (RegRex64 | RegRex))
7851 || r->reg_type.bitfield.reg64)
40fb9820 7852 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 7853 || !operand_type_equal (&r->reg_type, &control))
1ae00879 7854 && flag_code != CODE_64BIT)
20f0a1fc 7855 return (const reg_entry *) NULL;
1ae00879 7856
b7240065
JB		 7857 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7858 return (const reg_entry *) NULL;
7859
252b5132
RH		 7860 return r;
7861}
4d1bb795
JB		 7862
7863/* REG_STRING starts *before* REGISTER_PREFIX. */
7864
7865static const reg_entry *
7866parse_register (char *reg_string, char **end_op)
7867{
7868 const reg_entry *r;
7869
7870 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7871 r = parse_real_register (reg_string, end_op);
7872 else
7873 r = NULL;
7874 if (!r)
7875 {
7876 char *save = input_line_pointer;
7877 char c;
7878 symbolS *symbolP;
7879
7880 input_line_pointer = reg_string;
7881 c = get_symbol_end ();
7882 symbolP = symbol_find (reg_string);
7883 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7884 {
7885 const expressionS *e = symbol_get_value_expression (symbolP);
7886
7887 know (e->X_op == O_register);
4eed87de 7888 know (e->X_add_number >= 0
c3fe08fa 7889 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 7890 r = i386_regtab + e->X_add_number;
7891 *end_op = input_line_pointer;
7892 }
7893 *input_line_pointer = c;
7894 input_line_pointer = save;
7895 }
7896 return r;
7897}
7898
7899int
7900i386_parse_name (char *name, expressionS *e, char *nextcharP)
7901{
7902 const reg_entry *r;
7903 char *end = input_line_pointer;
7904
7905 *end = *nextcharP;
7906 r = parse_register (name, &input_line_pointer);
7907 if (r && end <= input_line_pointer)
7908 {
7909 *nextcharP = *input_line_pointer;
7910 *input_line_pointer = 0;
7911 e->X_op = O_register;
7912 e->X_add_number = r - i386_regtab;
7913 return 1;
7914 }
7915 input_line_pointer = end;
7916 *end = 0;
7917 return 0;
7918}
7919
7920void
7921md_operand (expressionS *e)
7922{
7923 if (*input_line_pointer == REGISTER_PREFIX)
7924 {
7925 char *end;
7926 const reg_entry *r = parse_real_register (input_line_pointer, &end);
7927
7928 if (r)
7929 {
7930 e->X_op = O_register;
7931 e->X_add_number = r - i386_regtab;
7932 input_line_pointer = end;
7933 }
7934 }
7935}
7936
252b5132 7937\f
4cc782b5 7938#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 7939const char *md_shortopts = "kVQ:sqn";
252b5132 7940#else
12b55ccc 7941const char *md_shortopts = "qn";
252b5132 7942#endif
6e0b89ee 7943
3e73aa7c 7944#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 7945#define OPTION_64 (OPTION_MD_BASE + 1)
7946#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 7947#define OPTION_MARCH (OPTION_MD_BASE + 3)
7948#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 7949#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7950#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7951#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7952#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7953#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 7954#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 7955#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
b3b91714 7956
99ad8390
NC		 7957struct option md_longopts[] =
7958{
3e73aa7c 7959 {"32", no_argument, NULL, OPTION_32},
99ad8390 7960#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 7961 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 7962#endif
b3b91714 7963 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 7964 {"march", required_argument, NULL, OPTION_MARCH},
7965 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 7966 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
7967 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
7968 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
7969 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
7970 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 7971 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 7972 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
252b5132
RH		 7973 {NULL, no_argument, NULL, 0}
7974};
7975size_t md_longopts_size = sizeof (md_longopts);
7976
7977int
9103f4f4 7978md_parse_option (int c, char *arg)
252b5132 7979{
9103f4f4 7980 unsigned int i;
6305a203 7981 char *arch, *next;
9103f4f4 7982
252b5132
RH		 7983 switch (c)
7984 {
12b55ccc
L		 7985 case 'n':
7986 optimize_align_code = 0;
7987 break;
7988
a38cf1db
AM		 7989 case 'q':
7990 quiet_warnings = 1;
252b5132
RH		 7991 break;
7992
7993#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 7994 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7995 should be emitted or not. FIXME: Not implemented. */
7996 case 'Q':
252b5132
RH		 7997 break;
7998
7999 /* -V: SVR4 argument to print version ID. */
8000 case 'V':
8001 print_version_id ();
8002 break;
8003
a38cf1db
AM		 8004 /* -k: Ignore for FreeBSD compatibility. */
8005 case 'k':
252b5132 8006 break;
4cc782b5
ILT		 8007
8008 case 's':
8009 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 8010 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 8011 break;
99ad8390
NC		 8012#endif
8013#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 8014 case OPTION_64:
8015 {
8016 const char **list, **l;
8017
3e73aa7c
JH		 8018 list = bfd_target_list ();
8019 for (l = list; *l != NULL; l++)
8620418b 8020 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 8021 || strcmp (*l, "coff-x86-64") == 0
8022 || strcmp (*l, "pe-x86-64") == 0
8023 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 8024 {
8025 default_arch = "x86_64";
8026 break;
8027 }
3e73aa7c 8028 if (*l == NULL)
6e0b89ee 8029 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 8030 free (list);
8031 }
8032 break;
8033#endif
252b5132 8034
6e0b89ee
AM		 8035 case OPTION_32:
8036 default_arch = "i386";
8037 break;
8038
b3b91714
AM		 8039 case OPTION_DIVIDE:
8040#ifdef SVR4_COMMENT_CHARS
8041 {
8042 char *n, *t;
8043 const char *s;
8044
8045 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
8046 t = n;
8047 for (s = i386_comment_chars; *s != '\0'; s++)
8048 if (*s != '/')
8049 *t++ = *s;
8050 *t = '\0';
8051 i386_comment_chars = n;
8052 }
8053#endif
8054 break;
8055
9103f4f4 8056 case OPTION_MARCH:
6305a203
L		 8057 arch = xstrdup (arg);
8058 do
9103f4f4 8059 {
6305a203
L		 8060 if (*arch == '.')
8061 as_fatal (_("Invalid -march= option: `%s'"), arg);
8062 next = strchr (arch, '+');
8063 if (next)
8064 *next++ = '\0';
8065 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
9103f4f4 8066 {
6305a203 8067 if (strcmp (arch, cpu_arch [i].name) == 0)
ccc9c027 8068 {
6305a203
L		 8069 /* Processor. */
8070 cpu_arch_name = cpu_arch[i].name;
8071 cpu_sub_arch_name = NULL;
8072 cpu_arch_flags = cpu_arch[i].flags;
8073 cpu_arch_isa = cpu_arch[i].type;
8074 cpu_arch_isa_flags = cpu_arch[i].flags;
8075 if (!cpu_arch_tune_set)
8076 {
8077 cpu_arch_tune = cpu_arch_isa;
8078 cpu_arch_tune_flags = cpu_arch_isa_flags;
8079 }
8080 break;
8081 }
8082 else if (*cpu_arch [i].name == '.'
8083 && strcmp (arch, cpu_arch [i].name + 1) == 0)
8084 {
8085 /* ISA entension. */
8086 i386_cpu_flags flags;
8087 flags = cpu_flags_or (cpu_arch_flags,
8088 cpu_arch[i].flags);
0dfbf9d7 8089 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 8090 {
8091 if (cpu_sub_arch_name)
8092 {
8093 char *name = cpu_sub_arch_name;
8094 cpu_sub_arch_name = concat (name,
8095 cpu_arch[i].name,
1bf57e9f 8096 (const char *) NULL);
6305a203
L		 8097 free (name);
8098 }
8099 else
8100 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
8101 cpu_arch_flags = flags;
8102 }
8103 break;
ccc9c027 8104 }
9103f4f4 8105 }
6305a203
L		 8106
8107 if (i >= ARRAY_SIZE (cpu_arch))
8108 as_fatal (_("Invalid -march= option: `%s'"), arg);
8109
8110 arch = next;
9103f4f4 8111 }
6305a203 8112 while (next != NULL );
9103f4f4
L		 8113 break;
8114
8115 case OPTION_MTUNE:
8116 if (*arg == '.')
8117 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8118 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
8119 {
8120 if (strcmp (arg, cpu_arch [i].name) == 0)
8121 {
ccc9c027 8122 cpu_arch_tune_set = 1;
9103f4f4
L		 8123 cpu_arch_tune = cpu_arch [i].type;
8124 cpu_arch_tune_flags = cpu_arch[i].flags;
8125 break;
8126 }
8127 }
8128 if (i >= ARRAY_SIZE (cpu_arch))
8129 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8130 break;
8131
1efbbeb4
L		 8132 case OPTION_MMNEMONIC:
8133 if (strcasecmp (arg, "att") == 0)
8134 intel_mnemonic = 0;
8135 else if (strcasecmp (arg, "intel") == 0)
8136 intel_mnemonic = 1;
8137 else
8138 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
8139 break;
8140
8141 case OPTION_MSYNTAX:
8142 if (strcasecmp (arg, "att") == 0)
8143 intel_syntax = 0;
8144 else if (strcasecmp (arg, "intel") == 0)
8145 intel_syntax = 1;
8146 else
8147 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
8148 break;
8149
8150 case OPTION_MINDEX_REG:
8151 allow_index_reg = 1;
8152 break;
8153
8154 case OPTION_MNAKED_REG:
8155 allow_naked_reg = 1;
8156 break;
8157
8158 case OPTION_MOLD_GCC:
8159 old_gcc = 1;
1efbbeb4
L		 8160 break;
8161
c0f3af97
L		 8162 case OPTION_MSSE2AVX:
8163 sse2avx = 1;
8164 break;
8165
daf50ae7
L		 8166 case OPTION_MSSE_CHECK:
8167 if (strcasecmp (arg, "error") == 0)
8168 sse_check = sse_check_error;
8169 else if (strcasecmp (arg, "warning") == 0)
8170 sse_check = sse_check_warning;
8171 else if (strcasecmp (arg, "none") == 0)
8172 sse_check = sse_check_none;
8173 else
8174 as_fatal (_("Invalid -msse-check= option: `%s'"), arg);
8175 break;
8176
252b5132
RH		 8177 default:
8178 return 0;
8179 }
8180 return 1;
8181}
8182
8183void
8184md_show_usage (stream)
8185 FILE *stream;
8186{
4cc782b5
ILT		 8187#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8188 fprintf (stream, _("\
a38cf1db
AM		 8189 -Q ignored\n\
8190 -V print assembler version number\n\
b3b91714
AM		 8191 -k ignored\n"));
8192#endif
8193 fprintf (stream, _("\
12b55ccc 8194 -n Do not optimize code alignment\n\
b3b91714
AM		 8195 -q quieten some warnings\n"));
8196#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8197 fprintf (stream, _("\
a38cf1db 8198 -s ignored\n"));
b3b91714 8199#endif
751d281c
L		 8200#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
8201 fprintf (stream, _("\
8202 --32/--64 generate 32bit/64bit code\n"));
8203#endif
b3b91714
AM		 8204#ifdef SVR4_COMMENT_CHARS
8205 fprintf (stream, _("\
8206 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 8207#else
8208 fprintf (stream, _("\
b3b91714 8209 --divide ignored\n"));
4cc782b5 8210#endif
9103f4f4 8211 fprintf (stream, _("\
6305a203
L		 8212 -march=CPU[,+EXTENSION...]\n\
8213 generate code for CPU and EXTENSION, CPU is one of:\n\
2cb4f3d5
L		 8214 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8215 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
bd5295b2 8216 core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
2cb4f3d5 8217 generic32, generic64\n\
599121aa
L		 8218 EXTENSION is combination of:\n\
8219 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
f1f8f695 8220 avx, vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
bd5295b2
L		 8221 clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\
8222 sse5, svme, abm, padlock\n"));
6305a203 8223 fprintf (stream, _("\
2cb4f3d5
L		 8224 -mtune=CPU optimize for CPU, CPU is one of:\n\
8225 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8226 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
bd5295b2 8227 core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
2cb4f3d5 8228 generic32, generic64\n"));
ba104c83 8229 fprintf (stream, _("\
c0f3af97
L		 8230 -msse2avx encode SSE instructions with VEX prefix\n"));
8231 fprintf (stream, _("\
daf50ae7
L		 8232 -msse-check=[none|error|warning]\n\
8233 check SSE instructions\n"));
8234 fprintf (stream, _("\
ba104c83
L		 8235 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8236 fprintf (stream, _("\
8237 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8238 fprintf (stream, _("\
8239 -mindex-reg support pseudo index registers\n"));
8240 fprintf (stream, _("\
8241 -mnaked-reg don't require `%%' prefix for registers\n"));
8242 fprintf (stream, _("\
8243 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 8244}
8245
3e73aa7c 8246#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
872ce6ff 8247 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
252b5132
RH		 8248
8249/* Pick the target format to use. */
8250
47926f60 8251const char *
e3bb37b5 8252i386_target_format (void)
252b5132 8253{
3e73aa7c 8254 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 8255 {
8256 set_code_flag (CODE_64BIT);
0dfbf9d7 8257 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 8258 {
8259 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8260 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8261 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8262 cpu_arch_isa_flags.bitfield.cpui486 = 1;
8263 cpu_arch_isa_flags.bitfield.cpui586 = 1;
8264 cpu_arch_isa_flags.bitfield.cpui686 = 1;
bd5295b2 8265 cpu_arch_isa_flags.bitfield.cpuclflush = 1;
40fb9820 8266 cpu_arch_isa_flags.bitfield.cpummx= 1;
40fb9820
L		 8267 cpu_arch_isa_flags.bitfield.cpusse = 1;
8268 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
8269 }
0dfbf9d7 8270 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 8271 {
8272 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8273 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8274 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8275 cpu_arch_tune_flags.bitfield.cpui486 = 1;
8276 cpu_arch_tune_flags.bitfield.cpui586 = 1;
8277 cpu_arch_tune_flags.bitfield.cpui686 = 1;
bd5295b2 8278 cpu_arch_tune_flags.bitfield.cpuclflush = 1;
40fb9820 8279 cpu_arch_tune_flags.bitfield.cpummx= 1;
40fb9820
L		 8280 cpu_arch_tune_flags.bitfield.cpusse = 1;
8281 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
8282 }
9103f4f4 8283 }
3e73aa7c 8284 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 8285 {
8286 set_code_flag (CODE_32BIT);
0dfbf9d7 8287 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 8288 {
8289 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8290 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8291 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8292 }
0dfbf9d7 8293 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 8294 {
8295 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8296 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8297 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8298 }
9103f4f4 8299 }
3e73aa7c
JH		 8300 else
8301 as_fatal (_("Unknown architecture"));
252b5132
RH		 8302 switch (OUTPUT_FLAVOR)
8303 {
872ce6ff
L		 8304#ifdef TE_PEP
8305 case bfd_target_coff_flavour:
b01ee69d 8306 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "pe-i386";
872ce6ff
L		 8307 break;
8308#endif
4c63da97
AM		 8309#ifdef OBJ_MAYBE_AOUT
8310 case bfd_target_aout_flavour:
47926f60 8311 return AOUT_TARGET_FORMAT;
4c63da97
AM		 8312#endif
8313#ifdef OBJ_MAYBE_COFF
252b5132
RH		 8314 case bfd_target_coff_flavour:
8315 return "coff-i386";
4c63da97 8316#endif
3e73aa7c 8317#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 8318 case bfd_target_elf_flavour:
3e73aa7c 8319 {
e5cb08ac 8320 if (flag_code == CODE_64BIT)
4fa24527
JB		 8321 {
8322 object_64bit = 1;
8323 use_rela_relocations = 1;
8324 }
9d7cbccd 8325 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 8326 }
4c63da97 8327#endif
252b5132
RH		 8328 default:
8329 abort ();
8330 return NULL;
8331 }
8332}
8333
47926f60 8334#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 8335
8336#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 8337void
8338i386_elf_emit_arch_note (void)
a847613f 8339{
718ddfc0 8340 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 8341 {
8342 char *p;
8343 asection *seg = now_seg;
8344 subsegT subseg = now_subseg;
8345 Elf_Internal_Note i_note;
8346 Elf_External_Note e_note;
8347 asection *note_secp;
8348 int len;
8349
8350 /* Create the .note section. */
8351 note_secp = subseg_new (".note", 0);
8352 bfd_set_section_flags (stdoutput,
8353 note_secp,
8354 SEC_HAS_CONTENTS | SEC_READONLY);
8355
8356 /* Process the arch string. */
8357 len = strlen (cpu_arch_name);
8358
8359 i_note.namesz = len + 1;
8360 i_note.descsz = 0;
8361 i_note.type = NT_ARCH;
8362 p = frag_more (sizeof (e_note.namesz));
8363 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8364 p = frag_more (sizeof (e_note.descsz));
8365 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8366 p = frag_more (sizeof (e_note.type));
8367 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8368 p = frag_more (len + 1);
8369 strcpy (p, cpu_arch_name);
8370
8371 frag_align (2, 0, 0);
8372
8373 subseg_set (seg, subseg);
8374 }
8375}
8376#endif
252b5132 8377\f
252b5132
RH		 8378symbolS *
8379md_undefined_symbol (name)
8380 char *name;
8381{
18dc2407
ILT		 8382 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8383 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8384 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8385 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 8386 {
8387 if (!GOT_symbol)
8388 {
8389 if (symbol_find (name))
8390 as_bad (_("GOT already in symbol table"));
8391 GOT_symbol = symbol_new (name, undefined_section,
8392 (valueT) 0, &zero_address_frag);
8393 };
8394 return GOT_symbol;
8395 }
252b5132
RH		 8396 return 0;
8397}
8398
8399/* Round up a section size to the appropriate boundary. */
47926f60 8400
252b5132
RH		 8401valueT
8402md_section_align (segment, size)
ab9da554 8403 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 8404 valueT size;
8405{
4c63da97
AM		 8406#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8407 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8408 {
8409 /* For a.out, force the section size to be aligned. If we don't do
8410 this, BFD will align it for us, but it will not write out the
8411 final bytes of the section. This may be a bug in BFD, but it is
8412 easier to fix it here since that is how the other a.out targets
8413 work. */
8414 int align;
8415
8416 align = bfd_get_section_alignment (stdoutput, segment);
8417 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8418 }
252b5132
RH		 8419#endif
8420
8421 return size;
8422}
8423
8424/* On the i386, PC-relative offsets are relative to the start of the
8425 next instruction. That is, the address of the offset, plus its
8426 size, since the offset is always the last part of the insn. */
8427
8428long
e3bb37b5 8429md_pcrel_from (fixS *fixP)
252b5132
RH		 8430{
8431 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8432}
8433
8434#ifndef I386COFF
8435
8436static void
e3bb37b5 8437s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 8438{
29b0f896 8439 int temp;
252b5132 8440
8a75718c
JB		 8441#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8442 if (IS_ELF)
8443 obj_elf_section_change_hook ();
8444#endif
252b5132
RH		 8445 temp = get_absolute_expression ();
8446 subseg_set (bss_section, (subsegT) temp);
8447 demand_empty_rest_of_line ();
8448}
8449
8450#endif
8451
252b5132 8452void
e3bb37b5 8453i386_validate_fix (fixS *fixp)
252b5132
RH		 8454{
8455 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8456 {
23df1078
JH		 8457 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8458 {
4fa24527 8459 if (!object_64bit)
23df1078
JH		 8460 abort ();
8461 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8462 }
8463 else
8464 {
4fa24527 8465 if (!object_64bit)
d6ab8113
JB		 8466 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8467 else
8468 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 8469 }
252b5132
RH		 8470 fixp->fx_subsy = 0;
8471 }
8472}
8473
252b5132
RH		 8474arelent *
8475tc_gen_reloc (section, fixp)
ab9da554 8476 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 8477 fixS *fixp;
8478{
8479 arelent *rel;
8480 bfd_reloc_code_real_type code;
8481
8482 switch (fixp->fx_r_type)
8483 {
3e73aa7c
JH		 8484 case BFD_RELOC_X86_64_PLT32:
8485 case BFD_RELOC_X86_64_GOT32:
8486 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 8487 case BFD_RELOC_386_PLT32:
8488 case BFD_RELOC_386_GOT32:
8489 case BFD_RELOC_386_GOTOFF:
8490 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 8491 case BFD_RELOC_386_TLS_GD:
8492 case BFD_RELOC_386_TLS_LDM:
8493 case BFD_RELOC_386_TLS_LDO_32:
8494 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8495 case BFD_RELOC_386_TLS_IE:
8496 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 8497 case BFD_RELOC_386_TLS_LE_32:
8498 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 8499 case BFD_RELOC_386_TLS_GOTDESC:
8500 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 8501 case BFD_RELOC_X86_64_TLSGD:
8502 case BFD_RELOC_X86_64_TLSLD:
8503 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8504 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 8505 case BFD_RELOC_X86_64_GOTTPOFF:
8506 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 8507 case BFD_RELOC_X86_64_TPOFF64:
8508 case BFD_RELOC_X86_64_GOTOFF64:
8509 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 8510 case BFD_RELOC_X86_64_GOT64:
8511 case BFD_RELOC_X86_64_GOTPCREL64:
8512 case BFD_RELOC_X86_64_GOTPC64:
8513 case BFD_RELOC_X86_64_GOTPLT64:
8514 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 8515 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8516 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 8517 case BFD_RELOC_RVA:
8518 case BFD_RELOC_VTABLE_ENTRY:
8519 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 8520#ifdef TE_PE
8521 case BFD_RELOC_32_SECREL:
8522#endif
252b5132
RH		 8523 code = fixp->fx_r_type;
8524 break;
dbbaec26
L		 8525 case BFD_RELOC_X86_64_32S:
8526 if (!fixp->fx_pcrel)
8527 {
8528 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8529 code = fixp->fx_r_type;
8530 break;
8531 }
252b5132 8532 default:
93382f6d 8533 if (fixp->fx_pcrel)
252b5132 8534 {
93382f6d
AM		 8535 switch (fixp->fx_size)
8536 {
8537 default:
b091f402
AM		 8538 as_bad_where (fixp->fx_file, fixp->fx_line,
8539 _("can not do %d byte pc-relative relocation"),
8540 fixp->fx_size);
93382f6d
AM		 8541 code = BFD_RELOC_32_PCREL;
8542 break;
8543 case 1: code = BFD_RELOC_8_PCREL; break;
8544 case 2: code = BFD_RELOC_16_PCREL; break;
8545 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 8546#ifdef BFD64
8547 case 8: code = BFD_RELOC_64_PCREL; break;
8548#endif
93382f6d
AM		 8549 }
8550 }
8551 else
8552 {
8553 switch (fixp->fx_size)
8554 {
8555 default:
b091f402
AM		 8556 as_bad_where (fixp->fx_file, fixp->fx_line,
8557 _("can not do %d byte relocation"),
8558 fixp->fx_size);
93382f6d
AM		 8559 code = BFD_RELOC_32;
8560 break;
8561 case 1: code = BFD_RELOC_8; break;
8562 case 2: code = BFD_RELOC_16; break;
8563 case 4: code = BFD_RELOC_32; break;
937149dd 8564#ifdef BFD64
3e73aa7c 8565 case 8: code = BFD_RELOC_64; break;
937149dd 8566#endif
93382f6d 8567 }
252b5132
RH		 8568 }
8569 break;
8570 }
252b5132 8571
d182319b
JB		 8572 if ((code == BFD_RELOC_32
8573 || code == BFD_RELOC_32_PCREL
8574 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 8575 && GOT_symbol
8576 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 8577 {
4fa24527 8578 if (!object_64bit)
d6ab8113
JB		 8579 code = BFD_RELOC_386_GOTPC;
8580 else
8581 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 8582 }
7b81dfbb
AJ		 8583 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
8584 && GOT_symbol
8585 && fixp->fx_addsy == GOT_symbol)
8586 {
8587 code = BFD_RELOC_X86_64_GOTPC64;
8588 }
252b5132
RH		 8589
8590 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 8591 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
8592 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 8593
8594 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 8595
3e73aa7c
JH		 8596 if (!use_rela_relocations)
8597 {
8598 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8599 vtable entry to be used in the relocation's section offset. */
8600 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8601 rel->address = fixp->fx_offset;
252b5132 8602
c6682705 8603 rel->addend = 0;
3e73aa7c
JH		 8604 }
8605 /* Use the rela in 64bit mode. */
252b5132 8606 else
3e73aa7c 8607 {
062cd5e7
AS		 8608 if (!fixp->fx_pcrel)
8609 rel->addend = fixp->fx_offset;
8610 else
8611 switch (code)
8612 {
8613 case BFD_RELOC_X86_64_PLT32:
8614 case BFD_RELOC_X86_64_GOT32:
8615 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 8616 case BFD_RELOC_X86_64_TLSGD:
8617 case BFD_RELOC_X86_64_TLSLD:
8618 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 8619 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8620 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 8621 rel->addend = fixp->fx_offset - fixp->fx_size;
8622 break;
8623 default:
8624 rel->addend = (section->vma
8625 - fixp->fx_size
8626 + fixp->fx_addnumber
8627 + md_pcrel_from (fixp));
8628 break;
8629 }
3e73aa7c
JH		 8630 }
8631
252b5132
RH		 8632 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
8633 if (rel->howto == NULL)
8634 {
8635 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 8636 _("cannot represent relocation type %s"),
252b5132
RH		 8637 bfd_get_reloc_code_name (code));
8638 /* Set howto to a garbage value so that we can keep going. */
8639 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
8640 assert (rel->howto != NULL);
8641 }
8642
8643 return rel;
8644}
8645
64a0c779
DN		 8646\f
8647/* Parse operands using Intel syntax. This implements a recursive descent
8648 parser based on the BNF grammar published in Appendix B of the MASM 6.1
8649 Programmer's Guide.
8650
8651 FIXME: We do not recognize the full operand grammar defined in the MASM
8652 documentation. In particular, all the structure/union and
8653 high-level macro operands are missing.
8654
8655 Uppercase words are terminals, lower case words are non-terminals.
8656 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
8657 bars '|' denote choices. Most grammar productions are implemented in
8658 functions called 'intel_<production>'.
8659
8660 Initial production is 'expr'.
8661
9306ca4a 8662 addOp + | -
64a0c779
DN		 8663
8664 alpha [a-zA-Z]
8665
9306ca4a
JB		 8666 binOp & | AND | \| | OR | ^ | XOR
8667
64a0c779
DN		 8668 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
8669
8670 constant digits [[ radixOverride ]]
8671
c0f3af97 8672 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD | YMMWORD
64a0c779
DN		 8673
8674 digits decdigit
b77a7acd
AJ		 8675 | digits decdigit
8676 | digits hexdigit
64a0c779
DN		 8677
8678 decdigit [0-9]
8679
9306ca4a
JB		 8680 e04 e04 addOp e05
8681 | e05
8682
8683 e05 e05 binOp e06
b77a7acd 8684 | e06
64a0c779
DN		 8685
8686 e06 e06 mulOp e09
b77a7acd 8687 | e09
64a0c779
DN		 8688
8689 e09 OFFSET e10
a724f0f4
JB		 8690 | SHORT e10
8691 | + e10
8692 | - e10
9306ca4a
JB		 8693 | ~ e10
8694 | NOT e10
64a0c779
DN		 8695 | e09 PTR e10
8696 | e09 : e10
8697 | e10
8698
8699 e10 e10 [ expr ]
b77a7acd 8700 | e11
64a0c779
DN		 8701
8702 e11 ( expr )
b77a7acd 8703 | [ expr ]
64a0c779
DN		 8704 | constant
8705 | dataType
8706 | id
8707 | $
8708 | register
8709
a724f0f4 8710 => expr expr cmpOp e04
9306ca4a 8711 | e04
64a0c779
DN		 8712
8713 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 8714 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 8715
8716 hexdigit a | b | c | d | e | f
b77a7acd 8717 | A | B | C | D | E | F
64a0c779
DN		 8718
8719 id alpha
b77a7acd 8720 | id alpha
64a0c779
DN		 8721 | id decdigit
8722
9306ca4a 8723 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 8724
8725 quote " | '
8726
8727 register specialRegister
b77a7acd 8728 | gpRegister
64a0c779
DN		 8729 | byteRegister
8730
8731 segmentRegister CS | DS | ES | FS | GS | SS
8732
9306ca4a 8733 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 8734 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 8735 | TR3 | TR4 | TR5 | TR6 | TR7
8736
64a0c779
DN		 8737 We simplify the grammar in obvious places (e.g., register parsing is
8738 done by calling parse_register) and eliminate immediate left recursion
8739 to implement a recursive-descent parser.
8740
a724f0f4
JB		 8741 expr e04 expr'
8742
8743 expr' cmpOp e04 expr'
8744 | Empty
9306ca4a
JB		 8745
8746 e04 e05 e04'
8747
8748 e04' addOp e05 e04'
8749 | Empty
64a0c779
DN		 8750
8751 e05 e06 e05'
8752
9306ca4a 8753 e05' binOp e06 e05'
b77a7acd 8754 | Empty
64a0c779
DN		 8755
8756 e06 e09 e06'
8757
8758 e06' mulOp e09 e06'
b77a7acd 8759 | Empty
64a0c779
DN		 8760
8761 e09 OFFSET e10 e09'
a724f0f4
JB		 8762 | SHORT e10'
8763 | + e10'
8764 | - e10'
8765 | ~ e10'
8766 | NOT e10'
b77a7acd 8767 | e10 e09'
64a0c779
DN		 8768
8769 e09' PTR e10 e09'
b77a7acd 8770 | : e10 e09'
64a0c779
DN		 8771 | Empty
8772
8773 e10 e11 e10'
8774
8775 e10' [ expr ] e10'
b77a7acd 8776 | Empty
64a0c779
DN		 8777
8778 e11 ( expr )
b77a7acd 8779 | [ expr ]
64a0c779
DN		 8780 | BYTE
8781 | WORD
8782 | DWORD
9306ca4a 8783 | FWORD
64a0c779 8784 | QWORD
9306ca4a
JB		 8785 | TBYTE
8786 | OWORD
8787 | XMMWORD
c0f3af97 8788 | YMMWORD
64a0c779
DN		 8789 | .
8790 | $
8791 | register
8792 | id
8793 | constant */
8794
8795/* Parsing structure for the intel syntax parser. Used to implement the
8796 semantic actions for the operand grammar. */
8797struct intel_parser_s
8798 {
8799 char *op_string; /* The string being parsed. */
8800 int got_a_float; /* Whether the operand is a float. */
4a1805b1 8801 int op_modifier; /* Operand modifier. */
64a0c779 8802 int is_mem; /* 1 if operand is memory reference. */
4eed87de
AM		 8803 int in_offset; /* >=1 if parsing operand of offset. */
8804 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 8805 const reg_entry *reg; /* Last register reference found. */
8806 char *disp; /* Displacement string being built. */
a724f0f4 8807 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 8808 };
8809
8810static struct intel_parser_s intel_parser;
8811
8812/* Token structure for parsing intel syntax. */
8813struct intel_token
8814 {
8815 int code; /* Token code. */
8816 const reg_entry *reg; /* Register entry for register tokens. */
8817 char *str; /* String representation. */
8818 };
8819
8820static struct intel_token cur_token, prev_token;
8821
50705ef4
AM		 8822/* Token codes for the intel parser. Since T_SHORT is already used
8823 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 8824#define T_NIL -1
8825#define T_CONST 1
8826#define T_REG 2
8827#define T_BYTE 3
8828#define T_WORD 4
9306ca4a
JB		 8829#define T_DWORD 5
8830#define T_FWORD 6
8831#define T_QWORD 7
8832#define T_TBYTE 8
8833#define T_XMMWORD 9
50705ef4 8834#undef T_SHORT
9306ca4a
JB		 8835#define T_SHORT 10
8836#define T_OFFSET 11
8837#define T_PTR 12
8838#define T_ID 13
8839#define T_SHL 14
8840#define T_SHR 15
c0f3af97 8841#define T_YMMWORD 16
64a0c779
DN		 8842
8843/* Prototypes for intel parser functions. */
e3bb37b5
L		 8844static int intel_match_token (int);
8845static void intel_putback_token (void);
8846static void intel_get_token (void);
8847static int intel_expr (void);
8848static int intel_e04 (void);
8849static int intel_e05 (void);
8850static int intel_e06 (void);
8851static int intel_e09 (void);
8852static int intel_e10 (void);
8853static int intel_e11 (void);
64a0c779 8854
64a0c779 8855static int
e3bb37b5 8856i386_intel_operand (char *operand_string, int got_a_float)
64a0c779
DN		 8857{
8858 int ret;
8859 char *p;
fc0763e6
JB		 8860 const reg_entry *final_base = i.base_reg;
8861 const reg_entry *final_index = i.index_reg;
64a0c779 8862
a724f0f4
JB		 8863 p = intel_parser.op_string = xstrdup (operand_string);
8864 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
8865
8866 for (;;)
64a0c779 8867 {
a724f0f4
JB		 8868 /* Initialize token holders. */
8869 cur_token.code = prev_token.code = T_NIL;
8870 cur_token.reg = prev_token.reg = NULL;
8871 cur_token.str = prev_token.str = NULL;
8872
8873 /* Initialize parser structure. */
8874 intel_parser.got_a_float = got_a_float;
8875 intel_parser.op_modifier = 0;
8876 intel_parser.is_mem = 0;
8877 intel_parser.in_offset = 0;
8878 intel_parser.in_bracket = 0;
8879 intel_parser.reg = NULL;
8880 intel_parser.disp[0] = '\0';
8881 intel_parser.next_operand = NULL;
8882
fc0763e6
JB		 8883 i.base_reg = NULL;
8884 i.index_reg = NULL;
8885
a724f0f4
JB		 8886 /* Read the first token and start the parser. */
8887 intel_get_token ();
8888 ret = intel_expr ();
8889
8890 if (!ret)
8891 break;
8892
9306ca4a
JB		 8893 if (cur_token.code != T_NIL)
8894 {
8895 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
8896 current_templates->start->name, cur_token.str);
8897 ret = 0;
8898 }
64a0c779
DN		 8899 /* If we found a memory reference, hand it over to i386_displacement
8900 to fill in the rest of the operand fields. */
9306ca4a 8901 else if (intel_parser.is_mem)
64a0c779
DN		 8902 {
8903 if ((i.mem_operands == 1
40fb9820 8904 && !current_templates->start->opcode_modifier.isstring)
64a0c779
DN		 8905 || i.mem_operands == 2)
8906 {
8907 as_bad (_("too many memory references for '%s'"),
8908 current_templates->start->name);
8909 ret = 0;
8910 }
8911 else
8912 {
8913 char *s = intel_parser.disp;
64a0c779 8914
a724f0f4
JB		 8915 if (!quiet_warnings && intel_parser.is_mem < 0)
8916 /* See the comments in intel_bracket_expr. */
8917 as_warn (_("Treating `%s' as memory reference"), operand_string);
8918
64a0c779
DN		 8919 /* Add the displacement expression. */
8920 if (*s != '\0')
a4622f40
AM		 8921 ret = i386_displacement (s, s + strlen (s));
8922 if (ret)
a724f0f4
JB		 8923 {
8924 /* Swap base and index in 16-bit memory operands like
8925 [si+bx]. Since i386_index_check is also used in AT&T
8926 mode we have to do that here. */
8927 if (i.base_reg
8928 && i.index_reg
40fb9820
L		 8929 && i.base_reg->reg_type.bitfield.reg16
8930 && i.index_reg->reg_type.bitfield.reg16
a724f0f4
JB		 8931 && i.base_reg->reg_num >= 6
8932 && i.index_reg->reg_num < 6)
8933 {
8934 const reg_entry *base = i.index_reg;
8935
8936 i.index_reg = i.base_reg;
8937 i.base_reg = base;
8938 }
8939 ret = i386_index_check (operand_string);
8940 }
fc0763e6
JB		 8941 if (ret)
8942 {
8943 i.types[this_operand].bitfield.mem = 1;
8944 i.mem_operands++;
8945 }
64a0c779
DN		 8946 }
8947 }
8948
8949 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 8950 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779 8951 || intel_parser.reg == NULL)
b7240065
JB		 8952 {
8953 if (i.mem_operands < 2 && i.seg[i.mem_operands])
8954 {
8955 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8956 as_warn (_("Segment override ignored"));
8957 i.seg[i.mem_operands] = NULL;
8958 }
8959 ret = i386_immediate (intel_parser.disp);
8960 }
a724f0f4 8961
fc0763e6
JB		 8962 if (!final_base && !final_index)
8963 {
8964 final_base = i.base_reg;
8965 final_index = i.index_reg;
8966 }
8967
a724f0f4 8968 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
4eed87de 8969 ret = 0;
a724f0f4
JB		 8970 if (!ret || !intel_parser.next_operand)
8971 break;
8972 intel_parser.op_string = intel_parser.next_operand;
8973 this_operand = i.operands++;
7d5e4556 8974 i.types[this_operand].bitfield.unspecified = 1;
64a0c779
DN		 8975 }
8976
8977 free (p);
8978 free (intel_parser.disp);
8979
fc0763e6
JB		 8980 if (final_base || final_index)
8981 {
8982 i.base_reg = final_base;
8983 i.index_reg = final_index;
8984 }
8985
64a0c779
DN		 8986 return ret;
8987}
8988
a724f0f4
JB		 8989#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
8990
8991/* expr e04 expr'
8992
8993 expr' cmpOp e04 expr'
8994 | Empty */
64a0c779 8995static int
e3bb37b5 8996intel_expr (void)
64a0c779 8997{
a724f0f4
JB		 8998 /* XXX Implement the comparison operators. */
8999 return intel_e04 ();
9306ca4a
JB		 9000}
9001
a724f0f4 9002/* e04 e05 e04'
9306ca4a 9003
a724f0f4 9004 e04' addOp e05 e04'
9306ca4a
JB		 9005 | Empty */
9006static int
e3bb37b5 9007intel_e04 (void)
9306ca4a 9008{
a724f0f4 9009 int nregs = -1;
9306ca4a 9010
a724f0f4 9011 for (;;)
9306ca4a 9012 {
a724f0f4
JB		 9013 if (!intel_e05())
9014 return 0;
9306ca4a 9015
a724f0f4
JB		 9016 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
9017 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 9018
a724f0f4
JB		 9019 if (cur_token.code == '+')
9020 nregs = -1;
9021 else if (cur_token.code == '-')
9022 nregs = NUM_ADDRESS_REGS;
9023 else
9024 return 1;
64a0c779 9025
a724f0f4
JB		 9026 strcat (intel_parser.disp, cur_token.str);
9027 intel_match_token (cur_token.code);
9028 }
64a0c779
DN		 9029}
9030
64a0c779
DN		 9031/* e05 e06 e05'
9032
9306ca4a 9033 e05' binOp e06 e05'
64a0c779
DN		 9034 | Empty */
9035static int
e3bb37b5 9036intel_e05 (void)
64a0c779 9037{
a724f0f4 9038 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 9039
a724f0f4 9040 for (;;)
64a0c779 9041 {
a724f0f4
JB		 9042 if (!intel_e06())
9043 return 0;
9044
4eed87de
AM		 9045 if (cur_token.code == '&'
9046 || cur_token.code == '|'
9047 || cur_token.code == '^')
a724f0f4
JB		 9048 {
9049 char str[2];
9050
9051 str[0] = cur_token.code;
9052 str[1] = 0;
9053 strcat (intel_parser.disp, str);
9054 }
9055 else
9056 break;
9306ca4a 9057
64a0c779
DN		 9058 intel_match_token (cur_token.code);
9059
a724f0f4
JB		 9060 if (nregs < 0)
9061 nregs = ~nregs;
64a0c779 9062 }
a724f0f4
JB		 9063 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
9064 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
9065 return 1;
4a1805b1 9066}
64a0c779
DN		 9067
9068/* e06 e09 e06'
9069
9070 e06' mulOp e09 e06'
b77a7acd 9071 | Empty */
64a0c779 9072static int
e3bb37b5 9073intel_e06 (void)
64a0c779 9074{
a724f0f4 9075 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 9076
a724f0f4 9077 for (;;)
64a0c779 9078 {
a724f0f4
JB		 9079 if (!intel_e09())
9080 return 0;
9306ca4a 9081
4eed87de
AM		 9082 if (cur_token.code == '*'
9083 || cur_token.code == '/'
9084 || cur_token.code == '%')
a724f0f4
JB		 9085 {
9086 char str[2];
9306ca4a 9087
a724f0f4
JB		 9088 str[0] = cur_token.code;
9089 str[1] = 0;
9090 strcat (intel_parser.disp, str);
9091 }
9092 else if (cur_token.code == T_SHL)
9093 strcat (intel_parser.disp, "<<");
9094 else if (cur_token.code == T_SHR)
9095 strcat (intel_parser.disp, ">>");
9096 else
9097 break;
9306ca4a 9098
64e74474 9099 intel_match_token (cur_token.code);
64a0c779 9100
a724f0f4
JB		 9101 if (nregs < 0)
9102 nregs = ~nregs;
64a0c779 9103 }
a724f0f4
JB		 9104 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
9105 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
9106 return 1;
64a0c779
DN		 9107}
9108
a724f0f4
JB		 9109/* e09 OFFSET e09
9110 | SHORT e09
9111 | + e09
9112 | - e09
9113 | ~ e09
9114 | NOT e09
9306ca4a
JB		 9115 | e10 e09'
9116
64a0c779 9117 e09' PTR e10 e09'
b77a7acd 9118 | : e10 e09'
64a0c779
DN		 9119 | Empty */
9120static int
e3bb37b5 9121intel_e09 (void)
64a0c779 9122{
a724f0f4
JB		 9123 int nregs = ~NUM_ADDRESS_REGS;
9124 int in_offset = 0;
9125
9126 for (;;)
64a0c779 9127 {
a724f0f4
JB		 9128 /* Don't consume constants here. */
9129 if (cur_token.code == '+' || cur_token.code == '-')
9130 {
9131 /* Need to look one token ahead - if the next token
9132 is a constant, the current token is its sign. */
9133 int next_code;
9134
9135 intel_match_token (cur_token.code);
9136 next_code = cur_token.code;
9137 intel_putback_token ();
9138 if (next_code == T_CONST)
9139 break;
9140 }
9141
9142 /* e09 OFFSET e09 */
9143 if (cur_token.code == T_OFFSET)
9144 {
9145 if (!in_offset++)
9146 ++intel_parser.in_offset;
9147 }
9148
9149 /* e09 SHORT e09 */
9150 else if (cur_token.code == T_SHORT)
9151 intel_parser.op_modifier |= 1 << T_SHORT;
9152
9153 /* e09 + e09 */
9154 else if (cur_token.code == '+')
9155 strcat (intel_parser.disp, "+");
9156
9157 /* e09 - e09
9158 | ~ e09
9159 | NOT e09 */
9160 else if (cur_token.code == '-' || cur_token.code == '~')
9161 {
9162 char str[2];
64a0c779 9163
a724f0f4
JB		 9164 if (nregs < 0)
9165 nregs = ~nregs;
9166 str[0] = cur_token.code;
9167 str[1] = 0;
9168 strcat (intel_parser.disp, str);
9169 }
9170
9171 /* e09 e10 e09' */
9172 else
9173 break;
9174
9175 intel_match_token (cur_token.code);
64a0c779
DN		 9176 }
9177
a724f0f4 9178 for (;;)
9306ca4a 9179 {
a724f0f4
JB		 9180 if (!intel_e10 ())
9181 return 0;
9306ca4a 9182
a724f0f4
JB		 9183 /* e09' PTR e10 e09' */
9184 if (cur_token.code == T_PTR)
9185 {
9186 char suffix;
9306ca4a 9187
a724f0f4 9188 if (prev_token.code == T_BYTE)
7d5e4556
L		 9189 {
9190 suffix = BYTE_MNEM_SUFFIX;
9191 i.types[this_operand].bitfield.byte = 1;
9192 }
9306ca4a 9193
a724f0f4
JB		 9194 else if (prev_token.code == T_WORD)
9195 {
34b772a6
JB		 9196 if ((current_templates->start->name[0] == 'l'
9197 && current_templates->start->name[2] == 's'
9198 && current_templates->start->name[3] == 0)
9199 || current_templates->start->base_opcode == 0x62 /* bound */)
a724f0f4
JB		 9200 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
9201 else if (intel_parser.got_a_float == 2) /* "fi..." */
9202 suffix = SHORT_MNEM_SUFFIX;
9203 else
9204 suffix = WORD_MNEM_SUFFIX;
7d5e4556 9205 i.types[this_operand].bitfield.word = 1;
a724f0f4 9206 }
64a0c779 9207
a724f0f4
JB		 9208 else if (prev_token.code == T_DWORD)
9209 {
34b772a6
JB		 9210 if ((current_templates->start->name[0] == 'l'
9211 && current_templates->start->name[2] == 's'
9212 && current_templates->start->name[3] == 0)
9213 || current_templates->start->base_opcode == 0x62 /* bound */)
a724f0f4
JB		 9214 suffix = WORD_MNEM_SUFFIX;
9215 else if (flag_code == CODE_16BIT
40fb9820
L		 9216 && (current_templates->start->opcode_modifier.jump
9217 || current_templates->start->opcode_modifier.jumpdword))
a724f0f4
JB		 9218 suffix = LONG_DOUBLE_MNEM_SUFFIX;
9219 else if (intel_parser.got_a_float == 1) /* "f..." */
9220 suffix = SHORT_MNEM_SUFFIX;
9221 else
9222 suffix = LONG_MNEM_SUFFIX;
7d5e4556 9223 i.types[this_operand].bitfield.dword = 1;
a724f0f4 9224 }
9306ca4a 9225
a724f0f4
JB		 9226 else if (prev_token.code == T_FWORD)
9227 {
9228 if (current_templates->start->name[0] == 'l'
9229 && current_templates->start->name[2] == 's'
9230 && current_templates->start->name[3] == 0)
9231 suffix = LONG_MNEM_SUFFIX;
9232 else if (!intel_parser.got_a_float)
9233 {
9234 if (flag_code == CODE_16BIT)
9235 add_prefix (DATA_PREFIX_OPCODE);
9236 suffix = LONG_DOUBLE_MNEM_SUFFIX;
9237 }
9238 else
9239 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7d5e4556 9240 i.types[this_operand].bitfield.fword = 1;
a724f0f4 9241 }
64a0c779 9242
a724f0f4
JB		 9243 else if (prev_token.code == T_QWORD)
9244 {
34b772a6
JB		 9245 if (current_templates->start->base_opcode == 0x62 /* bound */
9246 || intel_parser.got_a_float == 1) /* "f..." */
a724f0f4
JB		 9247 suffix = LONG_MNEM_SUFFIX;
9248 else
34b772a6 9249 suffix = QWORD_MNEM_SUFFIX;
7d5e4556 9250 i.types[this_operand].bitfield.qword = 1;
a724f0f4 9251 }
64a0c779 9252
a724f0f4
JB		 9253 else if (prev_token.code == T_TBYTE)
9254 {
9255 if (intel_parser.got_a_float == 1)
9256 suffix = LONG_DOUBLE_MNEM_SUFFIX;
9257 else
9258 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
9259 }
9306ca4a 9260
a724f0f4 9261 else if (prev_token.code == T_XMMWORD)
9306ca4a 9262 {
582d5edd 9263 suffix = XMMWORD_MNEM_SUFFIX;
7d5e4556 9264 i.types[this_operand].bitfield.xmmword = 1;
9306ca4a 9265 }
64a0c779 9266
c0f3af97
L		 9267 else if (prev_token.code == T_YMMWORD)
9268 {
9269 suffix = YMMWORD_MNEM_SUFFIX;
9270 i.types[this_operand].bitfield.ymmword = 1;
9271 }
9272
f16b83df 9273 else
a724f0f4
JB		 9274 {
9275 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
9276 return 0;
9277 }
9278
7d5e4556
L		 9279 i.types[this_operand].bitfield.unspecified = 0;
9280
435acd52
JB		 9281 /* Operands for jump/call using 'ptr' notation denote absolute
9282 addresses. */
40fb9820
L		 9283 if (current_templates->start->opcode_modifier.jump
9284 || current_templates->start->opcode_modifier.jumpdword)
9285 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 9286
a724f0f4
JB		 9287 if (current_templates->start->base_opcode == 0x8d /* lea */)
9288 ;
9289 else if (!i.suffix)
9290 i.suffix = suffix;
9291 else if (i.suffix != suffix)
9292 {
9293 as_bad (_("Conflicting operand modifiers"));
9294 return 0;
9295 }
64a0c779 9296
9306ca4a
JB		 9297 }
9298
a724f0f4
JB		 9299 /* e09' : e10 e09' */
9300 else if (cur_token.code == ':')
9306ca4a 9301 {
a724f0f4
JB		 9302 if (prev_token.code != T_REG)
9303 {
9304 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
9305 segment/group identifier (which we don't have), using comma
9306 as the operand separator there is even less consistent, since
9307 there all branches only have a single operand. */
9308 if (this_operand != 0
9309 || intel_parser.in_offset
9310 || intel_parser.in_bracket
40fb9820
L		 9311 || (!current_templates->start->opcode_modifier.jump
9312 && !current_templates->start->opcode_modifier.jumpdword
9313 && !current_templates->start->opcode_modifier.jumpintersegment
9314 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
a724f0f4
JB		 9315 return intel_match_token (T_NIL);
9316 /* Remember the start of the 2nd operand and terminate 1st
9317 operand here.
9318 XXX This isn't right, yet (when SSSS:OOOO is right operand of
9319 another expression), but it gets at least the simplest case
9320 (a plain number or symbol on the left side) right. */
9321 intel_parser.next_operand = intel_parser.op_string;
9322 *--intel_parser.op_string = '\0';
9323 return intel_match_token (':');
9324 }
9306ca4a 9325 }
64a0c779 9326
a724f0f4 9327 /* e09' Empty */
64a0c779 9328 else
a724f0f4 9329 break;
64a0c779 9330
a724f0f4
JB		 9331 intel_match_token (cur_token.code);
9332
9333 }
9334
9335 if (in_offset)
9336 {
9337 --intel_parser.in_offset;
9338 if (nregs < 0)
9339 nregs = ~nregs;
9340 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 9341 {
a724f0f4 9342 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 9343 return 0;
9344 }
a724f0f4
JB		 9345 intel_parser.op_modifier |= 1 << T_OFFSET;
9346 }
9306ca4a 9347
a724f0f4
JB		 9348 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
9349 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
9350 return 1;
9351}
64a0c779 9352
a724f0f4 9353static int
e3bb37b5 9354intel_bracket_expr (void)
a724f0f4
JB		 9355{
9356 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
9357 const char *start = intel_parser.op_string;
9358 int len;
9359
9360 if (i.op[this_operand].regs)
9361 return intel_match_token (T_NIL);
9362
9363 intel_match_token ('[');
9364
9365 /* Mark as a memory operand only if it's not already known to be an
9366 offset expression. If it's an offset expression, we need to keep
9367 the brace in. */
9368 if (!intel_parser.in_offset)
9369 {
9370 ++intel_parser.in_bracket;
435acd52
JB		 9371
9372 /* Operands for jump/call inside brackets denote absolute addresses. */
40fb9820
L		 9373 if (current_templates->start->opcode_modifier.jump
9374 || current_templates->start->opcode_modifier.jumpdword)
9375 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 9376
a724f0f4
JB		 9377 /* Unfortunately gas always diverged from MASM in a respect that can't
9378 be easily fixed without risking to break code sequences likely to be
9379 encountered (the testsuite even check for this): MASM doesn't consider
9380 an expression inside brackets unconditionally as a memory reference.
9381 When that is e.g. a constant, an offset expression, or the sum of the
9382 two, this is still taken as a constant load. gas, however, always
9383 treated these as memory references. As a compromise, we'll try to make
9384 offset expressions inside brackets work the MASM way (since that's
9385 less likely to be found in real world code), but make constants alone
9386 continue to work the traditional gas way. In either case, issue a
9387 warning. */
9388 intel_parser.op_modifier &= ~was_offset;
64a0c779 9389 }
a724f0f4 9390 else
64e74474 9391 strcat (intel_parser.disp, "[");
a724f0f4
JB		 9392
9393 /* Add a '+' to the displacement string if necessary. */
9394 if (*intel_parser.disp != '\0'
9395 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
9396 strcat (intel_parser.disp, "+");
64a0c779 9397
a724f0f4
JB		 9398 if (intel_expr ()
9399 && (len = intel_parser.op_string - start - 1,
9400 intel_match_token (']')))
64a0c779 9401 {
a724f0f4
JB		 9402 /* Preserve brackets when the operand is an offset expression. */
9403 if (intel_parser.in_offset)
9404 strcat (intel_parser.disp, "]");
9405 else
9406 {
9407 --intel_parser.in_bracket;
9408 if (i.base_reg || i.index_reg)
9409 intel_parser.is_mem = 1;
9410 if (!intel_parser.is_mem)
9411 {
9412 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
9413 /* Defer the warning until all of the operand was parsed. */
9414 intel_parser.is_mem = -1;
9415 else if (!quiet_warnings)
4eed87de
AM		 9416 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
9417 len, start, len, start);
a724f0f4
JB		 9418 }
9419 }
9420 intel_parser.op_modifier |= was_offset;
64a0c779 9421
a724f0f4 9422 return 1;
64a0c779 9423 }
a724f0f4 9424 return 0;
64a0c779
DN		 9425}
9426
9427/* e10 e11 e10'
9428
9429 e10' [ expr ] e10'
b77a7acd 9430 | Empty */
64a0c779 9431static int
e3bb37b5 9432intel_e10 (void)
64a0c779 9433{
a724f0f4
JB		 9434 if (!intel_e11 ())
9435 return 0;
64a0c779 9436
a724f0f4 9437 while (cur_token.code == '[')
64a0c779 9438 {
a724f0f4 9439 if (!intel_bracket_expr ())
21d6c4af 9440 return 0;
64a0c779
DN		 9441 }
9442
a724f0f4 9443 return 1;
64a0c779
DN		 9444}
9445
64a0c779 9446/* e11 ( expr )
b77a7acd 9447 | [ expr ]
64a0c779
DN		 9448 | BYTE
9449 | WORD
9450 | DWORD
9306ca4a 9451 | FWORD
64a0c779 9452 | QWORD
9306ca4a
JB		 9453 | TBYTE
9454 | OWORD
9455 | XMMWORD
c0f3af97 9456 | YMMWORD
4a1805b1 9457 | $
64a0c779
DN		 9458 | .
9459 | register
9460 | id
9461 | constant */
9462static int
e3bb37b5 9463intel_e11 (void)
64a0c779 9464{
a724f0f4 9465 switch (cur_token.code)
64a0c779 9466 {
a724f0f4
JB		 9467 /* e11 ( expr ) */
9468 case '(':
64a0c779
DN		 9469 intel_match_token ('(');
9470 strcat (intel_parser.disp, "(");
9471
9472 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 9473 {
9474 strcat (intel_parser.disp, ")");
9475 return 1;
9476 }
a724f0f4 9477 return 0;
4a1805b1 9478
a724f0f4
JB		 9479 /* e11 [ expr ] */
9480 case '[':
a724f0f4 9481 return intel_bracket_expr ();
64a0c779 9482
a724f0f4
JB		 9483 /* e11 $
9484 | . */
9485 case '.':
64a0c779
DN		 9486 strcat (intel_parser.disp, cur_token.str);
9487 intel_match_token (cur_token.code);
21d6c4af
DN		 9488
9489 /* Mark as a memory operand only if it's not already known to be an
9490 offset expression. */
a724f0f4 9491 if (!intel_parser.in_offset)
21d6c4af 9492 intel_parser.is_mem = 1;
64a0c779
DN		 9493
9494 return 1;
64a0c779 9495
a724f0f4
JB		 9496 /* e11 register */
9497 case T_REG:
9498 {
9499 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 9500
a724f0f4 9501 intel_match_token (T_REG);
64a0c779 9502
a724f0f4
JB		 9503 /* Check for segment change. */
9504 if (cur_token.code == ':')
9505 {
40fb9820
L		 9506 if (!reg->reg_type.bitfield.sreg2
9507 && !reg->reg_type.bitfield.sreg3)
a724f0f4 9508 {
4eed87de
AM		 9509 as_bad (_("`%s' is not a valid segment register"),
9510 reg->reg_name);
a724f0f4
JB		 9511 return 0;
9512 }
b7240065
JB		 9513 else if (i.mem_operands >= 2)
9514 as_warn (_("Segment override ignored"));
a724f0f4
JB		 9515 else if (i.seg[i.mem_operands])
9516 as_warn (_("Extra segment override ignored"));
9517 else
9518 {
9519 if (!intel_parser.in_offset)
9520 intel_parser.is_mem = 1;
9521 switch (reg->reg_num)
9522 {
9523 case 0:
9524 i.seg[i.mem_operands] = &es;
9525 break;
9526 case 1:
9527 i.seg[i.mem_operands] = &cs;
9528 break;
9529 case 2:
9530 i.seg[i.mem_operands] = &ss;
9531 break;
9532 case 3:
9533 i.seg[i.mem_operands] = &ds;
9534 break;
9535 case 4:
9536 i.seg[i.mem_operands] = &fs;
9537 break;
9538 case 5:
9539 i.seg[i.mem_operands] = &gs;
9540 break;
9541 }
9542 }
9543 }
64a0c779 9544
b7240065
JB		 9545 else if (reg->reg_type.bitfield.sreg3 && reg->reg_num == RegFlat)
9546 {
9547 as_bad (_("cannot use `FLAT' here"));
9548 return 0;
9549 }
9550
a724f0f4
JB		 9551 /* Not a segment register. Check for register scaling. */
9552 else if (cur_token.code == '*')
9553 {
9554 if (!intel_parser.in_bracket)
9555 {
9556 as_bad (_("Register scaling only allowed in memory operands"));
9557 return 0;
9558 }
64a0c779 9559
40fb9820 9560 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
a724f0f4
JB		 9561 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
9562 else if (i.index_reg)
9563 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 9564
a724f0f4
JB		 9565 /* What follows must be a valid scale. */
9566 intel_match_token ('*');
9567 i.index_reg = reg;
40fb9820 9568 i.types[this_operand].bitfield.baseindex = 1;
64a0c779 9569
a724f0f4
JB		 9570 /* Set the scale after setting the register (otherwise,
9571 i386_scale will complain) */
9572 if (cur_token.code == '+' || cur_token.code == '-')
9573 {
9574 char *str, sign = cur_token.code;
9575 intel_match_token (cur_token.code);
9576 if (cur_token.code != T_CONST)
9577 {
9578 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9579 cur_token.str);
9580 return 0;
9581 }
9582 str = (char *) xmalloc (strlen (cur_token.str) + 2);
9583 strcpy (str + 1, cur_token.str);
9584 *str = sign;
9585 if (!i386_scale (str))
9586 return 0;
9587 free (str);
9588 }
9589 else if (!i386_scale (cur_token.str))
64a0c779 9590 return 0;
a724f0f4
JB		 9591 intel_match_token (cur_token.code);
9592 }
64a0c779 9593
a724f0f4
JB		 9594 /* No scaling. If this is a memory operand, the register is either a
9595 base register (first occurrence) or an index register (second
9596 occurrence). */
7b0441f6 9597 else if (intel_parser.in_bracket)
a724f0f4 9598 {
64a0c779 9599
a724f0f4
JB		 9600 if (!i.base_reg)
9601 i.base_reg = reg;
9602 else if (!i.index_reg)
9603 i.index_reg = reg;
9604 else
9605 {
9606 as_bad (_("Too many register references in memory operand"));
9607 return 0;
9608 }
64a0c779 9609
40fb9820 9610 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4 9611 }
4a1805b1 9612
4d1bb795
JB		 9613 /* It's neither base nor index. */
9614 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4 9615 {
40fb9820
L		 9616 i386_operand_type temp = reg->reg_type;
9617 temp.bitfield.baseindex = 0;
c6fb90c8
L		 9618 i.types[this_operand] = operand_type_or (i.types[this_operand],
9619 temp);
7d5e4556 9620 i.types[this_operand].bitfield.unspecified = 0;
a724f0f4
JB		 9621 i.op[this_operand].regs = reg;
9622 i.reg_operands++;
9623 }
9624 else
9625 {
9626 as_bad (_("Invalid use of register"));
9627 return 0;
9628 }
64a0c779 9629
a724f0f4
JB		 9630 /* Since registers are not part of the displacement string (except
9631 when we're parsing offset operands), we may need to remove any
9632 preceding '+' from the displacement string. */
9633 if (*intel_parser.disp != '\0'
9634 && !intel_parser.in_offset)
9635 {
9636 char *s = intel_parser.disp;
9637 s += strlen (s) - 1;
9638 if (*s == '+')
9639 *s = '\0';
9640 }
4a1805b1 9641
a724f0f4
JB		 9642 return 1;
9643 }
9644
9645 /* e11 BYTE
9646 | WORD
9647 | DWORD
9648 | FWORD
9649 | QWORD
9650 | TBYTE
9651 | OWORD
c0f3af97
L		 9652 | XMMWORD
9653 | YMMWORD */
a724f0f4
JB		 9654 case T_BYTE:
9655 case T_WORD:
9656 case T_DWORD:
9657 case T_FWORD:
9658 case T_QWORD:
9659 case T_TBYTE:
9660 case T_XMMWORD:
c0f3af97 9661 case T_YMMWORD:
a724f0f4 9662 intel_match_token (cur_token.code);
64a0c779 9663
a724f0f4
JB		 9664 if (cur_token.code == T_PTR)
9665 return 1;
9666
9667 /* It must have been an identifier. */
9668 intel_putback_token ();
9669 cur_token.code = T_ID;
9670 /* FALLTHRU */
9671
9672 /* e11 id
9673 | constant */
9674 case T_ID:
9675 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 9676 {
9677 symbolS *symbolP;
9678
a724f0f4
JB		 9679 /* The identifier represents a memory reference only if it's not
9680 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 9681 symbolP = symbol_find(cur_token.str);
9682 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
9683 intel_parser.is_mem = 1;
9684 }
a724f0f4 9685 /* FALLTHRU */
64a0c779 9686
a724f0f4
JB		 9687 case T_CONST:
9688 case '-':
9689 case '+':
9690 {
9691 char *save_str, sign = 0;
64a0c779 9692
a724f0f4
JB		 9693 /* Allow constants that start with `+' or `-'. */
9694 if (cur_token.code == '-' || cur_token.code == '+')
9695 {
9696 sign = cur_token.code;
9697 intel_match_token (cur_token.code);
9698 if (cur_token.code != T_CONST)
9699 {
9700 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9701 cur_token.str);
9702 return 0;
9703 }
9704 }
64a0c779 9705
a724f0f4
JB		 9706 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
9707 strcpy (save_str + !!sign, cur_token.str);
9708 if (sign)
9709 *save_str = sign;
64a0c779 9710
a724f0f4
JB		 9711 /* Get the next token to check for register scaling. */
9712 intel_match_token (cur_token.code);
64a0c779 9713
4eed87de
AM		 9714 /* Check if this constant is a scaling factor for an
9715 index register. */
a724f0f4
JB		 9716 if (cur_token.code == '*')
9717 {
9718 if (intel_match_token ('*') && cur_token.code == T_REG)
9719 {
9720 const reg_entry *reg = cur_token.reg;
9721
9722 if (!intel_parser.in_bracket)
9723 {
4eed87de
AM		 9724 as_bad (_("Register scaling only allowed "
9725 "in memory operands"));
a724f0f4
JB		 9726 return 0;
9727 }
9728
4eed87de
AM		 9729 /* Disallow things like [1*si].
9730 sp and esp are invalid as index. */
40fb9820 9731 if (reg->reg_type.bitfield.reg16)
4eed87de 9732 reg = i386_regtab + REGNAM_AX + 4;
a724f0f4 9733 else if (i.index_reg)
4eed87de 9734 reg = i386_regtab + REGNAM_EAX + 4;
a724f0f4
JB		 9735
9736 /* The constant is followed by `* reg', so it must be
9737 a valid scale. */
9738 i.index_reg = reg;
40fb9820 9739 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4
JB		 9740
9741 /* Set the scale after setting the register (otherwise,
9742 i386_scale will complain) */
9743 if (!i386_scale (save_str))
64a0c779 9744 return 0;
a724f0f4
JB		 9745 intel_match_token (T_REG);
9746
9747 /* Since registers are not part of the displacement
9748 string, we may need to remove any preceding '+' from
9749 the displacement string. */
9750 if (*intel_parser.disp != '\0')
9751 {
9752 char *s = intel_parser.disp;
9753 s += strlen (s) - 1;
9754 if (*s == '+')
9755 *s = '\0';
9756 }
9757
9758 free (save_str);
9759
9760 return 1;
9761 }
64a0c779 9762
a724f0f4
JB		 9763 /* The constant was not used for register scaling. Since we have
9764 already consumed the token following `*' we now need to put it
9765 back in the stream. */
64a0c779 9766 intel_putback_token ();
a724f0f4 9767 }
64a0c779 9768
a724f0f4
JB		 9769 /* Add the constant to the displacement string. */
9770 strcat (intel_parser.disp, save_str);
9771 free (save_str);
64a0c779 9772
a724f0f4
JB		 9773 return 1;
9774 }
64a0c779
DN		 9775 }
9776
64a0c779
DN		 9777 as_bad (_("Unrecognized token '%s'"), cur_token.str);
9778 return 0;
9779}
9780
64a0c779
DN		 9781/* Match the given token against cur_token. If they match, read the next
9782 token from the operand string. */
9783static int
e3bb37b5 9784intel_match_token (int code)
64a0c779
DN		 9785{
9786 if (cur_token.code == code)
9787 {
9788 intel_get_token ();
9789 return 1;
9790 }
9791 else
9792 {
0477af35 9793 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 9794 return 0;
9795 }
9796}
9797
64a0c779
DN		 9798/* Read a new token from intel_parser.op_string and store it in cur_token. */
9799static void
e3bb37b5 9800intel_get_token (void)
64a0c779
DN		 9801{
9802 char *end_op;
9803 const reg_entry *reg;
9804 struct intel_token new_token;
9805
9806 new_token.code = T_NIL;
9807 new_token.reg = NULL;
9808 new_token.str = NULL;
9809
4a1805b1 9810 /* Free the memory allocated to the previous token and move
64a0c779
DN		 9811 cur_token to prev_token. */
9812 if (prev_token.str)
9813 free (prev_token.str);
9814
9815 prev_token = cur_token;
9816
9817 /* Skip whitespace. */
9818 while (is_space_char (*intel_parser.op_string))
9819 intel_parser.op_string++;
9820
9821 /* Return an empty token if we find nothing else on the line. */
9822 if (*intel_parser.op_string == '\0')
9823 {
9824 cur_token = new_token;
9825 return;
9826 }
9827
9828 /* The new token cannot be larger than the remainder of the operand
9829 string. */
a724f0f4 9830 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 9831 new_token.str[0] = '\0';
9832
9833 if (strchr ("0123456789", *intel_parser.op_string))
9834 {
9835 char *p = new_token.str;
9836 char *q = intel_parser.op_string;
9837 new_token.code = T_CONST;
9838
9839 /* Allow any kind of identifier char to encompass floating point and
9840 hexadecimal numbers. */
9841 while (is_identifier_char (*q))
9842 *p++ = *q++;
9843 *p = '\0';
9844
9845 /* Recognize special symbol names [0-9][bf]. */
9846 if (strlen (intel_parser.op_string) == 2
4a1805b1 9847 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 9848 || intel_parser.op_string[1] == 'f'))
9849 new_token.code = T_ID;
9850 }
9851
4d1bb795 9852 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 9853 {
4d1bb795
JB		 9854 size_t len = end_op - intel_parser.op_string;
9855
64a0c779
DN		 9856 new_token.code = T_REG;
9857 new_token.reg = reg;
9858
4d1bb795
JB		 9859 memcpy (new_token.str, intel_parser.op_string, len);
9860 new_token.str[len] = '\0';
64a0c779
DN		 9861 }
9862
9863 else if (is_identifier_char (*intel_parser.op_string))
9864 {
9865 char *p = new_token.str;
9866 char *q = intel_parser.op_string;
9867
9868 /* A '.' or '$' followed by an identifier char is an identifier.
9869 Otherwise, it's operator '.' followed by an expression. */
9870 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
9871 {
9306ca4a
JB		 9872 new_token.code = '.';
9873 new_token.str[0] = '.';
64a0c779
DN		 9874 new_token.str[1] = '\0';
9875 }
9876 else
9877 {
9878 while (is_identifier_char (*q) || *q == '@')
9879 *p++ = *q++;
9880 *p = '\0';
9881
9306ca4a
JB		 9882 if (strcasecmp (new_token.str, "NOT") == 0)
9883 new_token.code = '~';
9884
9885 else if (strcasecmp (new_token.str, "MOD") == 0)
9886 new_token.code = '%';
9887
9888 else if (strcasecmp (new_token.str, "AND") == 0)
9889 new_token.code = '&';
9890
9891 else if (strcasecmp (new_token.str, "OR") == 0)
9892 new_token.code = '|';
9893
9894 else if (strcasecmp (new_token.str, "XOR") == 0)
9895 new_token.code = '^';
9896
9897 else if (strcasecmp (new_token.str, "SHL") == 0)
9898 new_token.code = T_SHL;
9899
9900 else if (strcasecmp (new_token.str, "SHR") == 0)
9901 new_token.code = T_SHR;
9902
9903 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 9904 new_token.code = T_BYTE;
9905
9906 else if (strcasecmp (new_token.str, "WORD") == 0)
9907 new_token.code = T_WORD;
9908
9909 else if (strcasecmp (new_token.str, "DWORD") == 0)
9910 new_token.code = T_DWORD;
9911
9306ca4a
JB		 9912 else if (strcasecmp (new_token.str, "FWORD") == 0)
9913 new_token.code = T_FWORD;
9914
64a0c779
DN		 9915 else if (strcasecmp (new_token.str, "QWORD") == 0)
9916 new_token.code = T_QWORD;
9917
9306ca4a
JB		 9918 else if (strcasecmp (new_token.str, "TBYTE") == 0
9919 /* XXX remove (gcc still uses it) */
9920 || strcasecmp (new_token.str, "XWORD") == 0)
9921 new_token.code = T_TBYTE;
9922
9923 else if (strcasecmp (new_token.str, "XMMWORD") == 0
9924 || strcasecmp (new_token.str, "OWORD") == 0)
9925 new_token.code = T_XMMWORD;
64a0c779 9926
c0f3af97
L		 9927 else if (strcasecmp (new_token.str, "YMMWORD") == 0)
9928 new_token.code = T_YMMWORD;
9929
64a0c779
DN		 9930 else if (strcasecmp (new_token.str, "PTR") == 0)
9931 new_token.code = T_PTR;
9932
9933 else if (strcasecmp (new_token.str, "SHORT") == 0)
9934 new_token.code = T_SHORT;
9935
9936 else if (strcasecmp (new_token.str, "OFFSET") == 0)
9937 {
9938 new_token.code = T_OFFSET;
9939
9940 /* ??? This is not mentioned in the MASM grammar but gcc
9941 makes use of it with -mintel-syntax. OFFSET may be
9942 followed by FLAT: */
9943 if (strncasecmp (q, " FLAT:", 6) == 0)
9944 strcat (new_token.str, " FLAT:");
9945 }
9946
64a0c779
DN		 9947 else
9948 new_token.code = T_ID;
9949 }
9950 }
9951
9306ca4a
JB		 9952 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
9953 {
9954 new_token.code = *intel_parser.op_string;
9955 new_token.str[0] = *intel_parser.op_string;
9956 new_token.str[1] = '\0';
9957 }
9958
9959 else if (strchr ("<>", *intel_parser.op_string)
9960 && *intel_parser.op_string == *(intel_parser.op_string + 1))
9961 {
9962 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
9963 new_token.str[0] = *intel_parser.op_string;
9964 new_token.str[1] = *intel_parser.op_string;
9965 new_token.str[2] = '\0';
9966 }
9967
64a0c779 9968 else
0477af35 9969 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 9970
9971 intel_parser.op_string += strlen (new_token.str);
9972 cur_token = new_token;
9973}
9974
64a0c779
DN		 9975/* Put cur_token back into the token stream and make cur_token point to
9976 prev_token. */
9977static void
e3bb37b5 9978intel_putback_token (void)
64a0c779 9979{
a724f0f4
JB		 9980 if (cur_token.code != T_NIL)
9981 {
9982 intel_parser.op_string -= strlen (cur_token.str);
9983 free (cur_token.str);
9984 }
64a0c779 9985 cur_token = prev_token;
4a1805b1 9986
64a0c779
DN		 9987 /* Forget prev_token. */
9988 prev_token.code = T_NIL;
9989 prev_token.reg = NULL;
9990 prev_token.str = NULL;
9991}
54cfded0 9992
a60de03c
JB		 9993void
9994tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 9995{
a60de03c
JB		 9996 int saved_naked_reg;
9997 char saved_register_dot;
54cfded0 9998
a60de03c
JB		 9999 saved_naked_reg = allow_naked_reg;
10000 allow_naked_reg = 1;
10001 saved_register_dot = register_chars['.'];
10002 register_chars['.'] = '.';
10003 allow_pseudo_reg = 1;
10004 expression_and_evaluate (exp);
10005 allow_pseudo_reg = 0;
10006 register_chars['.'] = saved_register_dot;
10007 allow_naked_reg = saved_naked_reg;
10008
10009 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 10010 {
a60de03c
JB		 10011 if ((addressT) exp->X_add_number < i386_regtab_size)
10012 {
10013 exp->X_op = O_constant;
10014 exp->X_add_number = i386_regtab[exp->X_add_number]
10015 .dw2_regnum[flag_code >> 1];
10016 }
10017 else
10018 exp->X_op = O_illegal;
54cfded0 10019 }
54cfded0
AM		 10020}
10021
10022void
10023tc_x86_frame_initial_instructions (void)
10024{
a60de03c
JB		 10025 static unsigned int sp_regno[2];
10026
10027 if (!sp_regno[flag_code >> 1])
10028 {
10029 char *saved_input = input_line_pointer;
10030 char sp[][4] = {"esp", "rsp"};
10031 expressionS exp;
a4447b93 10032
a60de03c
JB		 10033 input_line_pointer = sp[flag_code >> 1];
10034 tc_x86_parse_to_dw2regnum (&exp);
10035 assert (exp.X_op == O_constant);
10036 sp_regno[flag_code >> 1] = exp.X_add_number;
10037 input_line_pointer = saved_input;
10038 }
a4447b93 10039
a60de03c 10040 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
a4447b93 10041 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 10042}
d2b2c203
DJ		 10043
10044int
10045i386_elf_section_type (const char *str, size_t len)
10046{
10047 if (flag_code == CODE_64BIT
10048 && len == sizeof ("unwind") - 1
10049 && strncmp (str, "unwind", 6) == 0)
10050 return SHT_X86_64_UNWIND;
10051
10052 return -1;
10053}
bb41ade5 10054
ad5fec3b
EB		 10055#ifdef TE_SOLARIS
10056void
10057i386_solaris_fix_up_eh_frame (segT sec)
10058{
10059 if (flag_code == CODE_64BIT)
10060 elf_section_type (sec) = SHT_X86_64_UNWIND;
10061}
10062#endif
10063
bb41ade5
AM		 10064#ifdef TE_PE
10065void
10066tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10067{
10068 expressionS expr;
10069
10070 expr.X_op = O_secrel;
10071 expr.X_add_symbol = symbol;
10072 expr.X_add_number = 0;
10073 emit_expr (&expr, size);
10074}
10075#endif
3b22753a
L		 10076
10077#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10078/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10079
01e1a5bc 10080bfd_vma
3b22753a
L		 10081x86_64_section_letter (int letter, char **ptr_msg)
10082{
10083 if (flag_code == CODE_64BIT)
10084 {
10085 if (letter == 'l')
10086 return SHF_X86_64_LARGE;
10087
10088 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 10089 }
3b22753a 10090 else
64e74474 10091 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 10092 return -1;
10093}
10094
01e1a5bc 10095bfd_vma
3b22753a
L		 10096x86_64_section_word (char *str, size_t len)
10097{
8620418b 10098 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 10099 return SHF_X86_64_LARGE;
10100
10101 return -1;
10102}
10103
10104static void
10105handle_large_common (int small ATTRIBUTE_UNUSED)
10106{
10107 if (flag_code != CODE_64BIT)
10108 {
10109 s_comm_internal (0, elf_common_parse);
10110 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10111 }
10112 else
10113 {
10114 static segT lbss_section;
10115 asection *saved_com_section_ptr = elf_com_section_ptr;
10116 asection *saved_bss_section = bss_section;
10117
10118 if (lbss_section == NULL)
10119 {
10120 flagword applicable;
10121 segT seg = now_seg;
10122 subsegT subseg = now_subseg;
10123
10124 /* The .lbss section is for local .largecomm symbols. */
10125 lbss_section = subseg_new (".lbss", 0);
10126 applicable = bfd_applicable_section_flags (stdoutput);
10127 bfd_set_section_flags (stdoutput, lbss_section,
10128 applicable & SEC_ALLOC);
10129 seg_info (lbss_section)->bss = 1;
10130
10131 subseg_set (seg, subseg);
10132 }
10133
10134 elf_com_section_ptr = &_bfd_elf_large_com_section;
10135 bss_section = lbss_section;
10136
10137 s_comm_internal (0, elf_common_parse);
10138
10139 elf_com_section_ptr = saved_com_section_ptr;
10140 bss_section = saved_bss_section;
10141 }
10142}
10143#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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