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b534c6d3 | 1 | /* tc-i386.c -- Assemble code for the Intel 80386 |
b3adc24a | 2 | Copyright (C) 1989-2020 Free Software Foundation, Inc. |
252b5132 RH |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
19 | 02110-1301, USA. */ | |
252b5132 | 20 | |
47926f60 KH |
21 | /* Intel 80386 machine specific gas. |
22 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 23 | x86_64 support by Jan Hubicka (jh@suse.cz) |
0f10071e | 24 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
47926f60 KH |
25 | Bugs & suggestions are completely welcome. This is free software. |
26 | Please help us make it better. */ | |
252b5132 | 27 | |
252b5132 | 28 | #include "as.h" |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | #include "subsegs.h" |
316e2c05 | 31 | #include "dwarf2dbg.h" |
54cfded0 | 32 | #include "dw2gencfi.h" |
d2b2c203 | 33 | #include "elf/x86-64.h" |
40fb9820 | 34 | #include "opcodes/i386-init.h" |
252b5132 | 35 | |
41fd2579 L |
36 | #ifdef HAVE_LIMITS_H |
37 | #include <limits.h> | |
38 | #else | |
39 | #ifdef HAVE_SYS_PARAM_H | |
40 | #include <sys/param.h> | |
41 | #endif | |
42 | #ifndef INT_MAX | |
43 | #define INT_MAX (int) (((unsigned) (-1)) >> 1) | |
44 | #endif | |
45 | #endif | |
46 | ||
c3332e24 | 47 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 48 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
49 | #endif |
50 | ||
29b0f896 AM |
51 | #ifndef DEFAULT_ARCH |
52 | #define DEFAULT_ARCH "i386" | |
246fcdee | 53 | #endif |
252b5132 | 54 | |
edde18a5 AM |
55 | #ifndef INLINE |
56 | #if __GNUC__ >= 2 | |
57 | #define INLINE __inline__ | |
58 | #else | |
59 | #define INLINE | |
60 | #endif | |
61 | #endif | |
62 | ||
6305a203 L |
63 | /* Prefixes will be emitted in the order defined below. |
64 | WAIT_PREFIX must be the first prefix since FWAIT is really is an | |
65 | instruction, and so must come before any prefixes. | |
66 | The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, | |
42164a71 | 67 | REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */ |
6305a203 L |
68 | #define WAIT_PREFIX 0 |
69 | #define SEG_PREFIX 1 | |
70 | #define ADDR_PREFIX 2 | |
71 | #define DATA_PREFIX 3 | |
c32fa91d | 72 | #define REP_PREFIX 4 |
42164a71 | 73 | #define HLE_PREFIX REP_PREFIX |
7e8b059b | 74 | #define BND_PREFIX REP_PREFIX |
c32fa91d | 75 | #define LOCK_PREFIX 5 |
4e9ac44a L |
76 | #define REX_PREFIX 6 /* must come last. */ |
77 | #define MAX_PREFIXES 7 /* max prefixes per opcode */ | |
6305a203 L |
78 | |
79 | /* we define the syntax here (modulo base,index,scale syntax) */ | |
80 | #define REGISTER_PREFIX '%' | |
81 | #define IMMEDIATE_PREFIX '$' | |
82 | #define ABSOLUTE_PREFIX '*' | |
83 | ||
84 | /* these are the instruction mnemonic suffixes in AT&T syntax or | |
85 | memory operand size in Intel syntax. */ | |
86 | #define WORD_MNEM_SUFFIX 'w' | |
87 | #define BYTE_MNEM_SUFFIX 'b' | |
88 | #define SHORT_MNEM_SUFFIX 's' | |
89 | #define LONG_MNEM_SUFFIX 'l' | |
90 | #define QWORD_MNEM_SUFFIX 'q' | |
6305a203 L |
91 | /* Intel Syntax. Use a non-ascii letter since since it never appears |
92 | in instructions. */ | |
93 | #define LONG_DOUBLE_MNEM_SUFFIX '\1' | |
94 | ||
95 | #define END_OF_INSN '\0' | |
96 | ||
79dec6b7 JB |
97 | /* This matches the C -> StaticRounding alias in the opcode table. */ |
98 | #define commutative staticrounding | |
99 | ||
6305a203 L |
100 | /* |
101 | 'templates' is for grouping together 'template' structures for opcodes | |
102 | of the same name. This is only used for storing the insns in the grand | |
103 | ole hash table of insns. | |
104 | The templates themselves start at START and range up to (but not including) | |
105 | END. | |
106 | */ | |
107 | typedef struct | |
108 | { | |
d3ce72d0 NC |
109 | const insn_template *start; |
110 | const insn_template *end; | |
6305a203 L |
111 | } |
112 | templates; | |
113 | ||
114 | /* 386 operand encoding bytes: see 386 book for details of this. */ | |
115 | typedef struct | |
116 | { | |
117 | unsigned int regmem; /* codes register or memory operand */ | |
118 | unsigned int reg; /* codes register operand (or extended opcode) */ | |
119 | unsigned int mode; /* how to interpret regmem & reg */ | |
120 | } | |
121 | modrm_byte; | |
122 | ||
123 | /* x86-64 extension prefix. */ | |
124 | typedef int rex_byte; | |
125 | ||
6305a203 L |
126 | /* 386 opcode byte to code indirect addressing. */ |
127 | typedef struct | |
128 | { | |
129 | unsigned base; | |
130 | unsigned index; | |
131 | unsigned scale; | |
132 | } | |
133 | sib_byte; | |
134 | ||
6305a203 L |
135 | /* x86 arch names, types and features */ |
136 | typedef struct | |
137 | { | |
138 | const char *name; /* arch name */ | |
8a2c8fef | 139 | unsigned int len; /* arch string length */ |
6305a203 L |
140 | enum processor_type type; /* arch type */ |
141 | i386_cpu_flags flags; /* cpu feature flags */ | |
8a2c8fef | 142 | unsigned int skip; /* show_arch should skip this. */ |
6305a203 L |
143 | } |
144 | arch_entry; | |
145 | ||
293f5f65 L |
146 | /* Used to turn off indicated flags. */ |
147 | typedef struct | |
148 | { | |
149 | const char *name; /* arch name */ | |
150 | unsigned int len; /* arch string length */ | |
151 | i386_cpu_flags flags; /* cpu feature flags */ | |
152 | } | |
153 | noarch_entry; | |
154 | ||
78f12dd3 | 155 | static void update_code_flag (int, int); |
e3bb37b5 L |
156 | static void set_code_flag (int); |
157 | static void set_16bit_gcc_code_flag (int); | |
158 | static void set_intel_syntax (int); | |
1efbbeb4 | 159 | static void set_intel_mnemonic (int); |
db51cc60 | 160 | static void set_allow_index_reg (int); |
7bab8ab5 | 161 | static void set_check (int); |
e3bb37b5 | 162 | static void set_cpu_arch (int); |
6482c264 | 163 | #ifdef TE_PE |
e3bb37b5 | 164 | static void pe_directive_secrel (int); |
6482c264 | 165 | #endif |
e3bb37b5 L |
166 | static void signed_cons (int); |
167 | static char *output_invalid (int c); | |
ee86248c JB |
168 | static int i386_finalize_immediate (segT, expressionS *, i386_operand_type, |
169 | const char *); | |
170 | static int i386_finalize_displacement (segT, expressionS *, i386_operand_type, | |
171 | const char *); | |
a7619375 | 172 | static int i386_att_operand (char *); |
e3bb37b5 | 173 | static int i386_intel_operand (char *, int); |
ee86248c JB |
174 | static int i386_intel_simplify (expressionS *); |
175 | static int i386_intel_parse_name (const char *, expressionS *); | |
e3bb37b5 L |
176 | static const reg_entry *parse_register (char *, char **); |
177 | static char *parse_insn (char *, char *); | |
178 | static char *parse_operands (char *, const char *); | |
179 | static void swap_operands (void); | |
4d456e3d | 180 | static void swap_2_operands (int, int); |
48bcea9f | 181 | static enum flag_code i386_addressing_mode (void); |
e3bb37b5 L |
182 | static void optimize_imm (void); |
183 | static void optimize_disp (void); | |
83b16ac6 | 184 | static const insn_template *match_template (char); |
e3bb37b5 L |
185 | static int check_string (void); |
186 | static int process_suffix (void); | |
187 | static int check_byte_reg (void); | |
188 | static int check_long_reg (void); | |
189 | static int check_qword_reg (void); | |
190 | static int check_word_reg (void); | |
191 | static int finalize_imm (void); | |
192 | static int process_operands (void); | |
193 | static const seg_entry *build_modrm_byte (void); | |
194 | static void output_insn (void); | |
195 | static void output_imm (fragS *, offsetT); | |
196 | static void output_disp (fragS *, offsetT); | |
29b0f896 | 197 | #ifndef I386COFF |
e3bb37b5 | 198 | static void s_bss (int); |
252b5132 | 199 | #endif |
17d4e2a2 L |
200 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
201 | static void handle_large_common (int small ATTRIBUTE_UNUSED); | |
b4a3a7b4 L |
202 | |
203 | /* GNU_PROPERTY_X86_ISA_1_USED. */ | |
204 | static unsigned int x86_isa_1_used; | |
205 | /* GNU_PROPERTY_X86_FEATURE_2_USED. */ | |
206 | static unsigned int x86_feature_2_used; | |
207 | /* Generate x86 used ISA and feature properties. */ | |
208 | static unsigned int x86_used_note = DEFAULT_X86_USED_NOTE; | |
17d4e2a2 | 209 | #endif |
252b5132 | 210 | |
a847613f | 211 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 212 | |
43234a1e L |
213 | /* This struct describes rounding control and SAE in the instruction. */ |
214 | struct RC_Operation | |
215 | { | |
216 | enum rc_type | |
217 | { | |
218 | rne = 0, | |
219 | rd, | |
220 | ru, | |
221 | rz, | |
222 | saeonly | |
223 | } type; | |
224 | int operand; | |
225 | }; | |
226 | ||
227 | static struct RC_Operation rc_op; | |
228 | ||
229 | /* The struct describes masking, applied to OPERAND in the instruction. | |
230 | MASK is a pointer to the corresponding mask register. ZEROING tells | |
231 | whether merging or zeroing mask is used. */ | |
232 | struct Mask_Operation | |
233 | { | |
234 | const reg_entry *mask; | |
235 | unsigned int zeroing; | |
236 | /* The operand where this operation is associated. */ | |
237 | int operand; | |
238 | }; | |
239 | ||
240 | static struct Mask_Operation mask_op; | |
241 | ||
242 | /* The struct describes broadcasting, applied to OPERAND. FACTOR is | |
243 | broadcast factor. */ | |
244 | struct Broadcast_Operation | |
245 | { | |
8e6e0792 | 246 | /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */ |
43234a1e L |
247 | int type; |
248 | ||
249 | /* Index of broadcasted operand. */ | |
250 | int operand; | |
4a1b91ea L |
251 | |
252 | /* Number of bytes to broadcast. */ | |
253 | int bytes; | |
43234a1e L |
254 | }; |
255 | ||
256 | static struct Broadcast_Operation broadcast_op; | |
257 | ||
c0f3af97 L |
258 | /* VEX prefix. */ |
259 | typedef struct | |
260 | { | |
43234a1e L |
261 | /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */ |
262 | unsigned char bytes[4]; | |
c0f3af97 L |
263 | unsigned int length; |
264 | /* Destination or source register specifier. */ | |
265 | const reg_entry *register_specifier; | |
266 | } vex_prefix; | |
267 | ||
252b5132 | 268 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 269 | i386_insn. */ |
252b5132 | 270 | |
520dc8e8 AM |
271 | union i386_op |
272 | { | |
273 | expressionS *disps; | |
274 | expressionS *imms; | |
275 | const reg_entry *regs; | |
276 | }; | |
277 | ||
a65babc9 L |
278 | enum i386_error |
279 | { | |
86e026a4 | 280 | operand_size_mismatch, |
a65babc9 L |
281 | operand_type_mismatch, |
282 | register_type_mismatch, | |
283 | number_of_operands_mismatch, | |
284 | invalid_instruction_suffix, | |
285 | bad_imm4, | |
a65babc9 L |
286 | unsupported_with_intel_mnemonic, |
287 | unsupported_syntax, | |
6c30d220 L |
288 | unsupported, |
289 | invalid_vsib_address, | |
7bab8ab5 | 290 | invalid_vector_register_set, |
43234a1e L |
291 | unsupported_vector_index_register, |
292 | unsupported_broadcast, | |
43234a1e L |
293 | broadcast_needed, |
294 | unsupported_masking, | |
295 | mask_not_on_destination, | |
296 | no_default_mask, | |
297 | unsupported_rc_sae, | |
298 | rc_sae_operand_not_last_imm, | |
299 | invalid_register_operand, | |
a65babc9 L |
300 | }; |
301 | ||
252b5132 RH |
302 | struct _i386_insn |
303 | { | |
47926f60 | 304 | /* TM holds the template for the insn were currently assembling. */ |
d3ce72d0 | 305 | insn_template tm; |
252b5132 | 306 | |
7d5e4556 L |
307 | /* SUFFIX holds the instruction size suffix for byte, word, dword |
308 | or qword, if given. */ | |
252b5132 RH |
309 | char suffix; |
310 | ||
47926f60 | 311 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
312 | unsigned int operands; |
313 | ||
314 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
315 | of given register, displacement, memory operands and immediate | |
47926f60 | 316 | operands. */ |
252b5132 RH |
317 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
318 | ||
319 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 320 | use OP[i] for the corresponding operand. */ |
40fb9820 | 321 | i386_operand_type types[MAX_OPERANDS]; |
252b5132 | 322 | |
520dc8e8 AM |
323 | /* Displacement expression, immediate expression, or register for each |
324 | operand. */ | |
325 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 326 | |
3e73aa7c JH |
327 | /* Flags for operands. */ |
328 | unsigned int flags[MAX_OPERANDS]; | |
329 | #define Operand_PCrel 1 | |
c48dadc9 | 330 | #define Operand_Mem 2 |
3e73aa7c | 331 | |
252b5132 | 332 | /* Relocation type for operand */ |
f86103b7 | 333 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
252b5132 | 334 | |
252b5132 RH |
335 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
336 | the base index byte below. */ | |
337 | const reg_entry *base_reg; | |
338 | const reg_entry *index_reg; | |
339 | unsigned int log2_scale_factor; | |
340 | ||
341 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 342 | explicit segment overrides are given. */ |
ce8a8b2f | 343 | const seg_entry *seg[2]; |
252b5132 | 344 | |
8325cc63 JB |
345 | /* Copied first memory operand string, for re-checking. */ |
346 | char *memop1_string; | |
347 | ||
252b5132 RH |
348 | /* PREFIX holds all the given prefix opcodes (usually null). |
349 | PREFIXES is the number of prefix opcodes. */ | |
350 | unsigned int prefixes; | |
351 | unsigned char prefix[MAX_PREFIXES]; | |
352 | ||
50128d0c JB |
353 | /* Register is in low 3 bits of opcode. */ |
354 | bfd_boolean short_form; | |
355 | ||
6f2f06be JB |
356 | /* The operand to a branch insn indicates an absolute branch. */ |
357 | bfd_boolean jumpabsolute; | |
358 | ||
b4a3a7b4 L |
359 | /* Has MMX register operands. */ |
360 | bfd_boolean has_regmmx; | |
361 | ||
362 | /* Has XMM register operands. */ | |
363 | bfd_boolean has_regxmm; | |
364 | ||
365 | /* Has YMM register operands. */ | |
366 | bfd_boolean has_regymm; | |
367 | ||
368 | /* Has ZMM register operands. */ | |
369 | bfd_boolean has_regzmm; | |
370 | ||
e379e5f3 L |
371 | /* Has GOTPC or TLS relocation. */ |
372 | bfd_boolean has_gotpc_tls_reloc; | |
373 | ||
252b5132 | 374 | /* RM and SIB are the modrm byte and the sib byte where the |
c1e679ec | 375 | addressing modes of this insn are encoded. */ |
252b5132 | 376 | modrm_byte rm; |
3e73aa7c | 377 | rex_byte rex; |
43234a1e | 378 | rex_byte vrex; |
252b5132 | 379 | sib_byte sib; |
c0f3af97 | 380 | vex_prefix vex; |
b6169b20 | 381 | |
43234a1e L |
382 | /* Masking attributes. */ |
383 | struct Mask_Operation *mask; | |
384 | ||
385 | /* Rounding control and SAE attributes. */ | |
386 | struct RC_Operation *rounding; | |
387 | ||
388 | /* Broadcasting attributes. */ | |
389 | struct Broadcast_Operation *broadcast; | |
390 | ||
391 | /* Compressed disp8*N attribute. */ | |
392 | unsigned int memshift; | |
393 | ||
86fa6981 L |
394 | /* Prefer load or store in encoding. */ |
395 | enum | |
396 | { | |
397 | dir_encoding_default = 0, | |
398 | dir_encoding_load, | |
64c49ab3 JB |
399 | dir_encoding_store, |
400 | dir_encoding_swap | |
86fa6981 | 401 | } dir_encoding; |
891edac4 | 402 | |
a501d77e L |
403 | /* Prefer 8bit or 32bit displacement in encoding. */ |
404 | enum | |
405 | { | |
406 | disp_encoding_default = 0, | |
407 | disp_encoding_8bit, | |
408 | disp_encoding_32bit | |
409 | } disp_encoding; | |
f8a5c266 | 410 | |
6b6b6807 L |
411 | /* Prefer the REX byte in encoding. */ |
412 | bfd_boolean rex_encoding; | |
413 | ||
b6f8c7c4 L |
414 | /* Disable instruction size optimization. */ |
415 | bfd_boolean no_optimize; | |
416 | ||
86fa6981 L |
417 | /* How to encode vector instructions. */ |
418 | enum | |
419 | { | |
420 | vex_encoding_default = 0, | |
42e04b36 | 421 | vex_encoding_vex, |
86fa6981 L |
422 | vex_encoding_vex3, |
423 | vex_encoding_evex | |
424 | } vec_encoding; | |
425 | ||
d5de92cf L |
426 | /* REP prefix. */ |
427 | const char *rep_prefix; | |
428 | ||
165de32a L |
429 | /* HLE prefix. */ |
430 | const char *hle_prefix; | |
42164a71 | 431 | |
7e8b059b L |
432 | /* Have BND prefix. */ |
433 | const char *bnd_prefix; | |
434 | ||
04ef582a L |
435 | /* Have NOTRACK prefix. */ |
436 | const char *notrack_prefix; | |
437 | ||
891edac4 | 438 | /* Error message. */ |
a65babc9 | 439 | enum i386_error error; |
252b5132 RH |
440 | }; |
441 | ||
442 | typedef struct _i386_insn i386_insn; | |
443 | ||
43234a1e L |
444 | /* Link RC type with corresponding string, that'll be looked for in |
445 | asm. */ | |
446 | struct RC_name | |
447 | { | |
448 | enum rc_type type; | |
449 | const char *name; | |
450 | unsigned int len; | |
451 | }; | |
452 | ||
453 | static const struct RC_name RC_NamesTable[] = | |
454 | { | |
455 | { rne, STRING_COMMA_LEN ("rn-sae") }, | |
456 | { rd, STRING_COMMA_LEN ("rd-sae") }, | |
457 | { ru, STRING_COMMA_LEN ("ru-sae") }, | |
458 | { rz, STRING_COMMA_LEN ("rz-sae") }, | |
459 | { saeonly, STRING_COMMA_LEN ("sae") }, | |
460 | }; | |
461 | ||
252b5132 RH |
462 | /* List of chars besides those in app.c:symbol_chars that can start an |
463 | operand. Used to prevent the scrubber eating vital white-space. */ | |
86fa6981 | 464 | const char extra_symbol_chars[] = "*%-([{}" |
252b5132 | 465 | #ifdef LEX_AT |
32137342 NC |
466 | "@" |
467 | #endif | |
468 | #ifdef LEX_QM | |
469 | "?" | |
252b5132 | 470 | #endif |
32137342 | 471 | ; |
252b5132 | 472 | |
29b0f896 AM |
473 | #if (defined (TE_I386AIX) \ |
474 | || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ | |
3896cfd5 | 475 | && !defined (TE_GNU) \ |
29b0f896 | 476 | && !defined (TE_LINUX) \ |
8d63c93e | 477 | && !defined (TE_NACL) \ |
29b0f896 | 478 | && !defined (TE_FreeBSD) \ |
5b806d27 | 479 | && !defined (TE_DragonFly) \ |
29b0f896 | 480 | && !defined (TE_NetBSD))) |
252b5132 | 481 | /* This array holds the chars that always start a comment. If the |
b3b91714 AM |
482 | pre-processor is disabled, these aren't very useful. The option |
483 | --divide will remove '/' from this list. */ | |
484 | const char *i386_comment_chars = "#/"; | |
485 | #define SVR4_COMMENT_CHARS 1 | |
252b5132 | 486 | #define PREFIX_SEPARATOR '\\' |
252b5132 | 487 | |
b3b91714 AM |
488 | #else |
489 | const char *i386_comment_chars = "#"; | |
490 | #define PREFIX_SEPARATOR '/' | |
491 | #endif | |
492 | ||
252b5132 RH |
493 | /* This array holds the chars that only start a comment at the beginning of |
494 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
495 | .line and .file directives will appear in the pre-processed output. |
496 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 497 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
498 | #NO_APP at the beginning of its output. |
499 | Also note that comments started like this one will always work if | |
252b5132 | 500 | '/' isn't otherwise defined. */ |
b3b91714 | 501 | const char line_comment_chars[] = "#/"; |
252b5132 | 502 | |
63a0b638 | 503 | const char line_separator_chars[] = ";"; |
252b5132 | 504 | |
ce8a8b2f AM |
505 | /* Chars that can be used to separate mant from exp in floating point |
506 | nums. */ | |
252b5132 RH |
507 | const char EXP_CHARS[] = "eE"; |
508 | ||
ce8a8b2f AM |
509 | /* Chars that mean this number is a floating point constant |
510 | As in 0f12.456 | |
511 | or 0d1.2345e12. */ | |
252b5132 RH |
512 | const char FLT_CHARS[] = "fFdDxX"; |
513 | ||
ce8a8b2f | 514 | /* Tables for lexical analysis. */ |
252b5132 RH |
515 | static char mnemonic_chars[256]; |
516 | static char register_chars[256]; | |
517 | static char operand_chars[256]; | |
518 | static char identifier_chars[256]; | |
519 | static char digit_chars[256]; | |
520 | ||
ce8a8b2f | 521 | /* Lexical macros. */ |
252b5132 RH |
522 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
523 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
524 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
525 | #define is_space_char(x) ((x) == ' ') | |
526 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
527 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
528 | ||
0234cb7c | 529 | /* All non-digit non-letter characters that may occur in an operand. */ |
252b5132 RH |
530 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
531 | ||
532 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
533 | effect this we maintain a stack of saved characters that we've smashed | |
534 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 535 | assembler instruction). */ |
252b5132 | 536 | static char save_stack[32]; |
ce8a8b2f | 537 | static char *save_stack_p; |
252b5132 RH |
538 | #define END_STRING_AND_SAVE(s) \ |
539 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
540 | #define RESTORE_END_STRING(s) \ | |
541 | do { *(s) = *--save_stack_p; } while (0) | |
542 | ||
47926f60 | 543 | /* The instruction we're assembling. */ |
252b5132 RH |
544 | static i386_insn i; |
545 | ||
546 | /* Possible templates for current insn. */ | |
547 | static const templates *current_templates; | |
548 | ||
31b2323c L |
549 | /* Per instruction expressionS buffers: max displacements & immediates. */ |
550 | static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; | |
551 | static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; | |
252b5132 | 552 | |
47926f60 | 553 | /* Current operand we are working on. */ |
ee86248c | 554 | static int this_operand = -1; |
252b5132 | 555 | |
3e73aa7c JH |
556 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
557 | these. */ | |
558 | ||
559 | enum flag_code { | |
560 | CODE_32BIT, | |
561 | CODE_16BIT, | |
562 | CODE_64BIT }; | |
563 | ||
564 | static enum flag_code flag_code; | |
4fa24527 | 565 | static unsigned int object_64bit; |
862be3fb | 566 | static unsigned int disallow_64bit_reloc; |
3e73aa7c | 567 | static int use_rela_relocations = 0; |
e379e5f3 L |
568 | /* __tls_get_addr/___tls_get_addr symbol for TLS. */ |
569 | static const char *tls_get_addr; | |
3e73aa7c | 570 | |
7af8ed2d NC |
571 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
572 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ | |
573 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) | |
574 | ||
351f65ca L |
575 | /* The ELF ABI to use. */ |
576 | enum x86_elf_abi | |
577 | { | |
578 | I386_ABI, | |
7f56bc95 L |
579 | X86_64_ABI, |
580 | X86_64_X32_ABI | |
351f65ca L |
581 | }; |
582 | ||
583 | static enum x86_elf_abi x86_elf_abi = I386_ABI; | |
7af8ed2d | 584 | #endif |
351f65ca | 585 | |
167ad85b TG |
586 | #if defined (TE_PE) || defined (TE_PEP) |
587 | /* Use big object file format. */ | |
588 | static int use_big_obj = 0; | |
589 | #endif | |
590 | ||
8dcea932 L |
591 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
592 | /* 1 if generating code for a shared library. */ | |
593 | static int shared = 0; | |
594 | #endif | |
595 | ||
47926f60 KH |
596 | /* 1 for intel syntax, |
597 | 0 if att syntax. */ | |
598 | static int intel_syntax = 0; | |
252b5132 | 599 | |
4b5aaf5f L |
600 | static enum x86_64_isa |
601 | { | |
602 | amd64 = 1, /* AMD64 ISA. */ | |
603 | intel64 /* Intel64 ISA. */ | |
604 | } isa64; | |
e89c5eaa | 605 | |
1efbbeb4 L |
606 | /* 1 for intel mnemonic, |
607 | 0 if att mnemonic. */ | |
608 | static int intel_mnemonic = !SYSV386_COMPAT; | |
609 | ||
a60de03c JB |
610 | /* 1 if pseudo registers are permitted. */ |
611 | static int allow_pseudo_reg = 0; | |
612 | ||
47926f60 KH |
613 | /* 1 if register prefix % not required. */ |
614 | static int allow_naked_reg = 0; | |
252b5132 | 615 | |
33eaf5de | 616 | /* 1 if the assembler should add BND prefix for all control-transferring |
7e8b059b L |
617 | instructions supporting it, even if this prefix wasn't specified |
618 | explicitly. */ | |
619 | static int add_bnd_prefix = 0; | |
620 | ||
ba104c83 | 621 | /* 1 if pseudo index register, eiz/riz, is allowed . */ |
db51cc60 L |
622 | static int allow_index_reg = 0; |
623 | ||
d022bddd IT |
624 | /* 1 if the assembler should ignore LOCK prefix, even if it was |
625 | specified explicitly. */ | |
626 | static int omit_lock_prefix = 0; | |
627 | ||
e4e00185 AS |
628 | /* 1 if the assembler should encode lfence, mfence, and sfence as |
629 | "lock addl $0, (%{re}sp)". */ | |
630 | static int avoid_fence = 0; | |
631 | ||
e379e5f3 L |
632 | /* Type of the previous instruction. */ |
633 | static struct | |
634 | { | |
635 | segT seg; | |
636 | const char *file; | |
637 | const char *name; | |
638 | unsigned int line; | |
639 | enum last_insn_kind | |
640 | { | |
641 | last_insn_other = 0, | |
642 | last_insn_directive, | |
643 | last_insn_prefix | |
644 | } kind; | |
645 | } last_insn; | |
646 | ||
0cb4071e L |
647 | /* 1 if the assembler should generate relax relocations. */ |
648 | ||
649 | static int generate_relax_relocations | |
650 | = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS; | |
651 | ||
7bab8ab5 | 652 | static enum check_kind |
daf50ae7 | 653 | { |
7bab8ab5 JB |
654 | check_none = 0, |
655 | check_warning, | |
656 | check_error | |
daf50ae7 | 657 | } |
7bab8ab5 | 658 | sse_check, operand_check = check_warning; |
daf50ae7 | 659 | |
e379e5f3 L |
660 | /* Non-zero if branches should be aligned within power of 2 boundary. */ |
661 | static int align_branch_power = 0; | |
662 | ||
663 | /* Types of branches to align. */ | |
664 | enum align_branch_kind | |
665 | { | |
666 | align_branch_none = 0, | |
667 | align_branch_jcc = 1, | |
668 | align_branch_fused = 2, | |
669 | align_branch_jmp = 3, | |
670 | align_branch_call = 4, | |
671 | align_branch_indirect = 5, | |
672 | align_branch_ret = 6 | |
673 | }; | |
674 | ||
675 | /* Type bits of branches to align. */ | |
676 | enum align_branch_bit | |
677 | { | |
678 | align_branch_jcc_bit = 1 << align_branch_jcc, | |
679 | align_branch_fused_bit = 1 << align_branch_fused, | |
680 | align_branch_jmp_bit = 1 << align_branch_jmp, | |
681 | align_branch_call_bit = 1 << align_branch_call, | |
682 | align_branch_indirect_bit = 1 << align_branch_indirect, | |
683 | align_branch_ret_bit = 1 << align_branch_ret | |
684 | }; | |
685 | ||
686 | static unsigned int align_branch = (align_branch_jcc_bit | |
687 | | align_branch_fused_bit | |
688 | | align_branch_jmp_bit); | |
689 | ||
79d72f45 HL |
690 | /* Types of condition jump used by macro-fusion. */ |
691 | enum mf_jcc_kind | |
692 | { | |
693 | mf_jcc_jo = 0, /* base opcode 0x70 */ | |
694 | mf_jcc_jc, /* base opcode 0x72 */ | |
695 | mf_jcc_je, /* base opcode 0x74 */ | |
696 | mf_jcc_jna, /* base opcode 0x76 */ | |
697 | mf_jcc_js, /* base opcode 0x78 */ | |
698 | mf_jcc_jp, /* base opcode 0x7a */ | |
699 | mf_jcc_jl, /* base opcode 0x7c */ | |
700 | mf_jcc_jle, /* base opcode 0x7e */ | |
701 | }; | |
702 | ||
703 | /* Types of compare flag-modifying insntructions used by macro-fusion. */ | |
704 | enum mf_cmp_kind | |
705 | { | |
706 | mf_cmp_test_and, /* test/cmp */ | |
707 | mf_cmp_alu_cmp, /* add/sub/cmp */ | |
708 | mf_cmp_incdec /* inc/dec */ | |
709 | }; | |
710 | ||
e379e5f3 L |
711 | /* The maximum padding size for fused jcc. CMP like instruction can |
712 | be 9 bytes and jcc can be 6 bytes. Leave room just in case for | |
713 | prefixes. */ | |
714 | #define MAX_FUSED_JCC_PADDING_SIZE 20 | |
715 | ||
716 | /* The maximum number of prefixes added for an instruction. */ | |
717 | static unsigned int align_branch_prefix_size = 5; | |
718 | ||
b6f8c7c4 L |
719 | /* Optimization: |
720 | 1. Clear the REX_W bit with register operand if possible. | |
721 | 2. Above plus use 128bit vector instruction to clear the full vector | |
722 | register. | |
723 | */ | |
724 | static int optimize = 0; | |
725 | ||
726 | /* Optimization: | |
727 | 1. Clear the REX_W bit with register operand if possible. | |
728 | 2. Above plus use 128bit vector instruction to clear the full vector | |
729 | register. | |
730 | 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to | |
731 | "testb $imm7,%r8". | |
732 | */ | |
733 | static int optimize_for_space = 0; | |
734 | ||
2ca3ace5 L |
735 | /* Register prefix used for error message. */ |
736 | static const char *register_prefix = "%"; | |
737 | ||
47926f60 KH |
738 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
739 | leave, push, and pop instructions so that gcc has the same stack | |
740 | frame as in 32 bit mode. */ | |
741 | static char stackop_size = '\0'; | |
eecb386c | 742 | |
12b55ccc L |
743 | /* Non-zero to optimize code alignment. */ |
744 | int optimize_align_code = 1; | |
745 | ||
47926f60 KH |
746 | /* Non-zero to quieten some warnings. */ |
747 | static int quiet_warnings = 0; | |
a38cf1db | 748 | |
47926f60 KH |
749 | /* CPU name. */ |
750 | static const char *cpu_arch_name = NULL; | |
6305a203 | 751 | static char *cpu_sub_arch_name = NULL; |
a38cf1db | 752 | |
47926f60 | 753 | /* CPU feature flags. */ |
40fb9820 L |
754 | static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; |
755 | ||
ccc9c027 L |
756 | /* If we have selected a cpu we are generating instructions for. */ |
757 | static int cpu_arch_tune_set = 0; | |
758 | ||
9103f4f4 | 759 | /* Cpu we are generating instructions for. */ |
fbf3f584 | 760 | enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; |
9103f4f4 L |
761 | |
762 | /* CPU feature flags of cpu we are generating instructions for. */ | |
40fb9820 | 763 | static i386_cpu_flags cpu_arch_tune_flags; |
9103f4f4 | 764 | |
ccc9c027 | 765 | /* CPU instruction set architecture used. */ |
fbf3f584 | 766 | enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; |
ccc9c027 | 767 | |
9103f4f4 | 768 | /* CPU feature flags of instruction set architecture used. */ |
fbf3f584 | 769 | i386_cpu_flags cpu_arch_isa_flags; |
9103f4f4 | 770 | |
fddf5b5b AM |
771 | /* If set, conditional jumps are not automatically promoted to handle |
772 | larger than a byte offset. */ | |
773 | static unsigned int no_cond_jump_promotion = 0; | |
774 | ||
c0f3af97 L |
775 | /* Encode SSE instructions with VEX prefix. */ |
776 | static unsigned int sse2avx; | |
777 | ||
539f890d L |
778 | /* Encode scalar AVX instructions with specific vector length. */ |
779 | static enum | |
780 | { | |
781 | vex128 = 0, | |
782 | vex256 | |
783 | } avxscalar; | |
784 | ||
03751133 L |
785 | /* Encode VEX WIG instructions with specific vex.w. */ |
786 | static enum | |
787 | { | |
788 | vexw0 = 0, | |
789 | vexw1 | |
790 | } vexwig; | |
791 | ||
43234a1e L |
792 | /* Encode scalar EVEX LIG instructions with specific vector length. */ |
793 | static enum | |
794 | { | |
795 | evexl128 = 0, | |
796 | evexl256, | |
797 | evexl512 | |
798 | } evexlig; | |
799 | ||
800 | /* Encode EVEX WIG instructions with specific evex.w. */ | |
801 | static enum | |
802 | { | |
803 | evexw0 = 0, | |
804 | evexw1 | |
805 | } evexwig; | |
806 | ||
d3d3c6db IT |
807 | /* Value to encode in EVEX RC bits, for SAE-only instructions. */ |
808 | static enum rc_type evexrcig = rne; | |
809 | ||
29b0f896 | 810 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
87c245cc | 811 | static symbolS *GOT_symbol; |
29b0f896 | 812 | |
a4447b93 RH |
813 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
814 | unsigned int x86_dwarf2_return_column; | |
815 | ||
816 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
817 | int x86_cie_data_alignment; | |
818 | ||
252b5132 | 819 | /* Interface to relax_segment. |
fddf5b5b AM |
820 | There are 3 major relax states for 386 jump insns because the |
821 | different types of jumps add different sizes to frags when we're | |
e379e5f3 L |
822 | figuring out what sort of jump to choose to reach a given label. |
823 | ||
824 | BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align | |
825 | branches which are handled by md_estimate_size_before_relax() and | |
826 | i386_generic_table_relax_frag(). */ | |
252b5132 | 827 | |
47926f60 | 828 | /* Types. */ |
93c2a809 AM |
829 | #define UNCOND_JUMP 0 |
830 | #define COND_JUMP 1 | |
831 | #define COND_JUMP86 2 | |
e379e5f3 L |
832 | #define BRANCH_PADDING 3 |
833 | #define BRANCH_PREFIX 4 | |
834 | #define FUSED_JCC_PADDING 5 | |
fddf5b5b | 835 | |
47926f60 | 836 | /* Sizes. */ |
252b5132 RH |
837 | #define CODE16 1 |
838 | #define SMALL 0 | |
29b0f896 | 839 | #define SMALL16 (SMALL | CODE16) |
252b5132 | 840 | #define BIG 2 |
29b0f896 | 841 | #define BIG16 (BIG | CODE16) |
252b5132 RH |
842 | |
843 | #ifndef INLINE | |
844 | #ifdef __GNUC__ | |
845 | #define INLINE __inline__ | |
846 | #else | |
847 | #define INLINE | |
848 | #endif | |
849 | #endif | |
850 | ||
fddf5b5b AM |
851 | #define ENCODE_RELAX_STATE(type, size) \ |
852 | ((relax_substateT) (((type) << 2) | (size))) | |
853 | #define TYPE_FROM_RELAX_STATE(s) \ | |
854 | ((s) >> 2) | |
855 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
856 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
857 | |
858 | /* This table is used by relax_frag to promote short jumps to long | |
859 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
860 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
861 | don't allow a short jump in a 32 bit code segment to be promoted to | |
862 | a 16 bit offset jump because it's slower (requires data size | |
863 | prefix), and doesn't work, unless the destination is in the bottom | |
864 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
865 | ||
866 | const relax_typeS md_relax_table[] = | |
867 | { | |
24eab124 AM |
868 | /* The fields are: |
869 | 1) most positive reach of this state, | |
870 | 2) most negative reach of this state, | |
93c2a809 | 871 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 872 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 873 | |
fddf5b5b | 874 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
875 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
876 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
877 | /* dword jmp adds 4 bytes to frag: | |
878 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 879 | {0, 0, 4, 0}, |
93c2a809 AM |
880 | /* word jmp adds 2 byte2 to frag: |
881 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
882 | {0, 0, 2, 0}, |
883 | ||
93c2a809 AM |
884 | /* COND_JUMP states. */ |
885 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
886 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
887 | /* dword conditionals adds 5 bytes to frag: | |
888 | 1 extra opcode byte, 4 displacement bytes. */ | |
889 | {0, 0, 5, 0}, | |
fddf5b5b | 890 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
891 | 1 extra opcode byte, 2 displacement bytes. */ |
892 | {0, 0, 3, 0}, | |
893 | ||
894 | /* COND_JUMP86 states. */ | |
895 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
896 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
897 | /* dword conditionals adds 5 bytes to frag: | |
898 | 1 extra opcode byte, 4 displacement bytes. */ | |
899 | {0, 0, 5, 0}, | |
900 | /* word conditionals add 4 bytes to frag: | |
901 | 1 displacement byte and a 3 byte long branch insn. */ | |
902 | {0, 0, 4, 0} | |
252b5132 RH |
903 | }; |
904 | ||
9103f4f4 L |
905 | static const arch_entry cpu_arch[] = |
906 | { | |
89507696 JB |
907 | /* Do not replace the first two entries - i386_target_format() |
908 | relies on them being there in this order. */ | |
8a2c8fef | 909 | { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32, |
293f5f65 | 910 | CPU_GENERIC32_FLAGS, 0 }, |
8a2c8fef | 911 | { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64, |
293f5f65 | 912 | CPU_GENERIC64_FLAGS, 0 }, |
8a2c8fef | 913 | { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN, |
293f5f65 | 914 | CPU_NONE_FLAGS, 0 }, |
8a2c8fef | 915 | { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN, |
293f5f65 | 916 | CPU_I186_FLAGS, 0 }, |
8a2c8fef | 917 | { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN, |
293f5f65 | 918 | CPU_I286_FLAGS, 0 }, |
8a2c8fef | 919 | { STRING_COMMA_LEN ("i386"), PROCESSOR_I386, |
293f5f65 | 920 | CPU_I386_FLAGS, 0 }, |
8a2c8fef | 921 | { STRING_COMMA_LEN ("i486"), PROCESSOR_I486, |
293f5f65 | 922 | CPU_I486_FLAGS, 0 }, |
8a2c8fef | 923 | { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM, |
293f5f65 | 924 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 925 | { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 926 | CPU_I686_FLAGS, 0 }, |
8a2c8fef | 927 | { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM, |
293f5f65 | 928 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 929 | { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 930 | CPU_PENTIUMPRO_FLAGS, 0 }, |
8a2c8fef | 931 | { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 932 | CPU_P2_FLAGS, 0 }, |
8a2c8fef | 933 | { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO, |
293f5f65 | 934 | CPU_P3_FLAGS, 0 }, |
8a2c8fef | 935 | { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4, |
293f5f65 | 936 | CPU_P4_FLAGS, 0 }, |
8a2c8fef | 937 | { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA, |
293f5f65 | 938 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 939 | { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA, |
293f5f65 | 940 | CPU_NOCONA_FLAGS, 0 }, |
8a2c8fef | 941 | { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE, |
293f5f65 | 942 | CPU_CORE_FLAGS, 1 }, |
8a2c8fef | 943 | { STRING_COMMA_LEN ("core"), PROCESSOR_CORE, |
293f5f65 | 944 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 945 | { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2, |
293f5f65 | 946 | CPU_CORE2_FLAGS, 1 }, |
8a2c8fef | 947 | { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2, |
293f5f65 | 948 | CPU_CORE2_FLAGS, 0 }, |
8a2c8fef | 949 | { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7, |
293f5f65 | 950 | CPU_COREI7_FLAGS, 0 }, |
8a2c8fef | 951 | { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM, |
293f5f65 | 952 | CPU_L1OM_FLAGS, 0 }, |
7a9068fe | 953 | { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM, |
293f5f65 | 954 | CPU_K1OM_FLAGS, 0 }, |
81486035 | 955 | { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU, |
293f5f65 | 956 | CPU_IAMCU_FLAGS, 0 }, |
8a2c8fef | 957 | { STRING_COMMA_LEN ("k6"), PROCESSOR_K6, |
293f5f65 | 958 | CPU_K6_FLAGS, 0 }, |
8a2c8fef | 959 | { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6, |
293f5f65 | 960 | CPU_K6_2_FLAGS, 0 }, |
8a2c8fef | 961 | { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON, |
293f5f65 | 962 | CPU_ATHLON_FLAGS, 0 }, |
8a2c8fef | 963 | { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8, |
293f5f65 | 964 | CPU_K8_FLAGS, 1 }, |
8a2c8fef | 965 | { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8, |
293f5f65 | 966 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 967 | { STRING_COMMA_LEN ("k8"), PROCESSOR_K8, |
293f5f65 | 968 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 969 | { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10, |
293f5f65 | 970 | CPU_AMDFAM10_FLAGS, 0 }, |
8aedb9fe | 971 | { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD, |
293f5f65 | 972 | CPU_BDVER1_FLAGS, 0 }, |
8aedb9fe | 973 | { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD, |
293f5f65 | 974 | CPU_BDVER2_FLAGS, 0 }, |
5e5c50d3 | 975 | { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD, |
293f5f65 | 976 | CPU_BDVER3_FLAGS, 0 }, |
c7b0bd56 | 977 | { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD, |
293f5f65 | 978 | CPU_BDVER4_FLAGS, 0 }, |
029f3522 | 979 | { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER, |
293f5f65 | 980 | CPU_ZNVER1_FLAGS, 0 }, |
a9660a6f AP |
981 | { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER, |
982 | CPU_ZNVER2_FLAGS, 0 }, | |
7b458c12 | 983 | { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT, |
293f5f65 | 984 | CPU_BTVER1_FLAGS, 0 }, |
7b458c12 | 985 | { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT, |
293f5f65 | 986 | CPU_BTVER2_FLAGS, 0 }, |
8a2c8fef | 987 | { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN, |
293f5f65 | 988 | CPU_8087_FLAGS, 0 }, |
8a2c8fef | 989 | { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN, |
293f5f65 | 990 | CPU_287_FLAGS, 0 }, |
8a2c8fef | 991 | { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN, |
293f5f65 | 992 | CPU_387_FLAGS, 0 }, |
1848e567 L |
993 | { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN, |
994 | CPU_687_FLAGS, 0 }, | |
d871f3f4 L |
995 | { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN, |
996 | CPU_CMOV_FLAGS, 0 }, | |
997 | { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN, | |
998 | CPU_FXSR_FLAGS, 0 }, | |
8a2c8fef | 999 | { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1000 | CPU_MMX_FLAGS, 0 }, |
8a2c8fef | 1001 | { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN, |
293f5f65 | 1002 | CPU_SSE_FLAGS, 0 }, |
8a2c8fef | 1003 | { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN, |
293f5f65 | 1004 | CPU_SSE2_FLAGS, 0 }, |
8a2c8fef | 1005 | { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 1006 | CPU_SSE3_FLAGS, 0 }, |
af5c13b0 L |
1007 | { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, |
1008 | CPU_SSE4A_FLAGS, 0 }, | |
8a2c8fef | 1009 | { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 1010 | CPU_SSSE3_FLAGS, 0 }, |
8a2c8fef | 1011 | { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN, |
293f5f65 | 1012 | CPU_SSE4_1_FLAGS, 0 }, |
8a2c8fef | 1013 | { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN, |
293f5f65 | 1014 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 1015 | { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN, |
293f5f65 | 1016 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 1017 | { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1018 | CPU_AVX_FLAGS, 0 }, |
6c30d220 | 1019 | { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN, |
293f5f65 | 1020 | CPU_AVX2_FLAGS, 0 }, |
43234a1e | 1021 | { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN, |
293f5f65 | 1022 | CPU_AVX512F_FLAGS, 0 }, |
43234a1e | 1023 | { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN, |
293f5f65 | 1024 | CPU_AVX512CD_FLAGS, 0 }, |
43234a1e | 1025 | { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN, |
293f5f65 | 1026 | CPU_AVX512ER_FLAGS, 0 }, |
43234a1e | 1027 | { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN, |
293f5f65 | 1028 | CPU_AVX512PF_FLAGS, 0 }, |
1dfc6506 | 1029 | { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN, |
293f5f65 | 1030 | CPU_AVX512DQ_FLAGS, 0 }, |
1dfc6506 | 1031 | { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN, |
293f5f65 | 1032 | CPU_AVX512BW_FLAGS, 0 }, |
1dfc6506 | 1033 | { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN, |
293f5f65 | 1034 | CPU_AVX512VL_FLAGS, 0 }, |
8a2c8fef | 1035 | { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1036 | CPU_VMX_FLAGS, 0 }, |
8729a6f6 | 1037 | { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN, |
293f5f65 | 1038 | CPU_VMFUNC_FLAGS, 0 }, |
8a2c8fef | 1039 | { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1040 | CPU_SMX_FLAGS, 0 }, |
8a2c8fef | 1041 | { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN, |
293f5f65 | 1042 | CPU_XSAVE_FLAGS, 0 }, |
c7b8aa3a | 1043 | { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 1044 | CPU_XSAVEOPT_FLAGS, 0 }, |
1dfc6506 | 1045 | { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN, |
293f5f65 | 1046 | CPU_XSAVEC_FLAGS, 0 }, |
1dfc6506 | 1047 | { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN, |
293f5f65 | 1048 | CPU_XSAVES_FLAGS, 0 }, |
8a2c8fef | 1049 | { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN, |
293f5f65 | 1050 | CPU_AES_FLAGS, 0 }, |
8a2c8fef | 1051 | { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 1052 | CPU_PCLMUL_FLAGS, 0 }, |
8a2c8fef | 1053 | { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 1054 | CPU_PCLMUL_FLAGS, 1 }, |
c7b8aa3a | 1055 | { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN, |
293f5f65 | 1056 | CPU_FSGSBASE_FLAGS, 0 }, |
c7b8aa3a | 1057 | { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN, |
293f5f65 | 1058 | CPU_RDRND_FLAGS, 0 }, |
c7b8aa3a | 1059 | { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN, |
293f5f65 | 1060 | CPU_F16C_FLAGS, 0 }, |
6c30d220 | 1061 | { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN, |
293f5f65 | 1062 | CPU_BMI2_FLAGS, 0 }, |
8a2c8fef | 1063 | { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN, |
293f5f65 | 1064 | CPU_FMA_FLAGS, 0 }, |
8a2c8fef | 1065 | { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN, |
293f5f65 | 1066 | CPU_FMA4_FLAGS, 0 }, |
8a2c8fef | 1067 | { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN, |
293f5f65 | 1068 | CPU_XOP_FLAGS, 0 }, |
8a2c8fef | 1069 | { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN, |
293f5f65 | 1070 | CPU_LWP_FLAGS, 0 }, |
8a2c8fef | 1071 | { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN, |
293f5f65 | 1072 | CPU_MOVBE_FLAGS, 0 }, |
60aa667e | 1073 | { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN, |
293f5f65 | 1074 | CPU_CX16_FLAGS, 0 }, |
8a2c8fef | 1075 | { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN, |
293f5f65 | 1076 | CPU_EPT_FLAGS, 0 }, |
6c30d220 | 1077 | { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN, |
293f5f65 | 1078 | CPU_LZCNT_FLAGS, 0 }, |
272a84b1 L |
1079 | { STRING_COMMA_LEN (".popcnt"), PROCESSOR_UNKNOWN, |
1080 | CPU_POPCNT_FLAGS, 0 }, | |
42164a71 | 1081 | { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN, |
293f5f65 | 1082 | CPU_HLE_FLAGS, 0 }, |
42164a71 | 1083 | { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN, |
293f5f65 | 1084 | CPU_RTM_FLAGS, 0 }, |
6c30d220 | 1085 | { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN, |
293f5f65 | 1086 | CPU_INVPCID_FLAGS, 0 }, |
8a2c8fef | 1087 | { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN, |
293f5f65 | 1088 | CPU_CLFLUSH_FLAGS, 0 }, |
22109423 | 1089 | { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN, |
293f5f65 | 1090 | CPU_NOP_FLAGS, 0 }, |
8a2c8fef | 1091 | { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN, |
293f5f65 | 1092 | CPU_SYSCALL_FLAGS, 0 }, |
8a2c8fef | 1093 | { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN, |
293f5f65 | 1094 | CPU_RDTSCP_FLAGS, 0 }, |
8a2c8fef | 1095 | { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN, |
293f5f65 | 1096 | CPU_3DNOW_FLAGS, 0 }, |
8a2c8fef | 1097 | { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN, |
293f5f65 | 1098 | CPU_3DNOWA_FLAGS, 0 }, |
8a2c8fef | 1099 | { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN, |
293f5f65 | 1100 | CPU_PADLOCK_FLAGS, 0 }, |
8a2c8fef | 1101 | { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN, |
293f5f65 | 1102 | CPU_SVME_FLAGS, 1 }, |
8a2c8fef | 1103 | { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN, |
293f5f65 | 1104 | CPU_SVME_FLAGS, 0 }, |
8a2c8fef | 1105 | { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, |
293f5f65 | 1106 | CPU_SSE4A_FLAGS, 0 }, |
8a2c8fef | 1107 | { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN, |
293f5f65 | 1108 | CPU_ABM_FLAGS, 0 }, |
87973e9f | 1109 | { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 1110 | CPU_BMI_FLAGS, 0 }, |
2a2a0f38 | 1111 | { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN, |
293f5f65 | 1112 | CPU_TBM_FLAGS, 0 }, |
e2e1fcde | 1113 | { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1114 | CPU_ADX_FLAGS, 0 }, |
e2e1fcde | 1115 | { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN, |
293f5f65 | 1116 | CPU_RDSEED_FLAGS, 0 }, |
e2e1fcde | 1117 | { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN, |
293f5f65 | 1118 | CPU_PRFCHW_FLAGS, 0 }, |
5c111e37 | 1119 | { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN, |
293f5f65 | 1120 | CPU_SMAP_FLAGS, 0 }, |
7e8b059b | 1121 | { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1122 | CPU_MPX_FLAGS, 0 }, |
a0046408 | 1123 | { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN, |
293f5f65 | 1124 | CPU_SHA_FLAGS, 0 }, |
963f3586 | 1125 | { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 1126 | CPU_CLFLUSHOPT_FLAGS, 0 }, |
dcf893b5 | 1127 | { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN, |
293f5f65 | 1128 | CPU_PREFETCHWT1_FLAGS, 0 }, |
2cf200a4 | 1129 | { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN, |
293f5f65 | 1130 | CPU_SE1_FLAGS, 0 }, |
c5e7287a | 1131 | { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN, |
293f5f65 | 1132 | CPU_CLWB_FLAGS, 0 }, |
2cc1b5aa | 1133 | { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN, |
293f5f65 | 1134 | CPU_AVX512IFMA_FLAGS, 0 }, |
14f195c9 | 1135 | { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 1136 | CPU_AVX512VBMI_FLAGS, 0 }, |
920d2ddc IT |
1137 | { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN, |
1138 | CPU_AVX512_4FMAPS_FLAGS, 0 }, | |
47acf0bd IT |
1139 | { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN, |
1140 | CPU_AVX512_4VNNIW_FLAGS, 0 }, | |
620214f7 IT |
1141 | { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN, |
1142 | CPU_AVX512_VPOPCNTDQ_FLAGS, 0 }, | |
53467f57 IT |
1143 | { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN, |
1144 | CPU_AVX512_VBMI2_FLAGS, 0 }, | |
8cfcb765 IT |
1145 | { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN, |
1146 | CPU_AVX512_VNNI_FLAGS, 0 }, | |
ee6872be IT |
1147 | { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN, |
1148 | CPU_AVX512_BITALG_FLAGS, 0 }, | |
029f3522 | 1149 | { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN, |
293f5f65 | 1150 | CPU_CLZERO_FLAGS, 0 }, |
9916071f | 1151 | { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1152 | CPU_MWAITX_FLAGS, 0 }, |
8eab4136 | 1153 | { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN, |
293f5f65 | 1154 | CPU_OSPKE_FLAGS, 0 }, |
8bc52696 | 1155 | { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN, |
293f5f65 | 1156 | CPU_RDPID_FLAGS, 0 }, |
6b40c462 L |
1157 | { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN, |
1158 | CPU_PTWRITE_FLAGS, 0 }, | |
d777820b IT |
1159 | { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN, |
1160 | CPU_IBT_FLAGS, 0 }, | |
1161 | { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN, | |
1162 | CPU_SHSTK_FLAGS, 0 }, | |
48521003 IT |
1163 | { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN, |
1164 | CPU_GFNI_FLAGS, 0 }, | |
8dcf1fad IT |
1165 | { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN, |
1166 | CPU_VAES_FLAGS, 0 }, | |
ff1982d5 IT |
1167 | { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN, |
1168 | CPU_VPCLMULQDQ_FLAGS, 0 }, | |
3233d7d0 IT |
1169 | { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN, |
1170 | CPU_WBNOINVD_FLAGS, 0 }, | |
be3a8dca IT |
1171 | { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN, |
1172 | CPU_PCONFIG_FLAGS, 0 }, | |
de89d0a3 IT |
1173 | { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN, |
1174 | CPU_WAITPKG_FLAGS, 0 }, | |
c48935d7 IT |
1175 | { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN, |
1176 | CPU_CLDEMOTE_FLAGS, 0 }, | |
c0a30a9f L |
1177 | { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN, |
1178 | CPU_MOVDIRI_FLAGS, 0 }, | |
1179 | { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN, | |
1180 | CPU_MOVDIR64B_FLAGS, 0 }, | |
d6aab7a1 XG |
1181 | { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN, |
1182 | CPU_AVX512_BF16_FLAGS, 0 }, | |
9186c494 L |
1183 | { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN, |
1184 | CPU_AVX512_VP2INTERSECT_FLAGS, 0 }, | |
dd455cf5 L |
1185 | { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN, |
1186 | CPU_ENQCMD_FLAGS, 0 }, | |
142861df JB |
1187 | { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN, |
1188 | CPU_RDPRU_FLAGS, 0 }, | |
1189 | { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN, | |
1190 | CPU_MCOMMIT_FLAGS, 0 }, | |
293f5f65 L |
1191 | }; |
1192 | ||
1193 | static const noarch_entry cpu_noarch[] = | |
1194 | { | |
1195 | { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS }, | |
1848e567 L |
1196 | { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS }, |
1197 | { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS }, | |
1198 | { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS }, | |
d871f3f4 L |
1199 | { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS }, |
1200 | { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS }, | |
293f5f65 L |
1201 | { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS }, |
1202 | { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS }, | |
1848e567 L |
1203 | { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS }, |
1204 | { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS }, | |
af5c13b0 | 1205 | { STRING_COMMA_LEN ("nosse4a"), CPU_ANY_SSE4A_FLAGS }, |
1848e567 L |
1206 | { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS }, |
1207 | { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS }, | |
1208 | { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS }, | |
af5c13b0 | 1209 | { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS }, |
293f5f65 | 1210 | { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS }, |
1848e567 | 1211 | { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS }, |
144b71e2 L |
1212 | { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS }, |
1213 | { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS }, | |
1214 | { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS }, | |
1215 | { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS }, | |
1216 | { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS }, | |
1217 | { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS }, | |
1218 | { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS }, | |
1219 | { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS }, | |
1220 | { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS }, | |
920d2ddc | 1221 | { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS }, |
47acf0bd | 1222 | { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS }, |
620214f7 | 1223 | { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS }, |
53467f57 | 1224 | { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS }, |
8cfcb765 | 1225 | { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS }, |
ee6872be | 1226 | { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS }, |
d777820b IT |
1227 | { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS }, |
1228 | { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS }, | |
c0a30a9f L |
1229 | { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS }, |
1230 | { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS }, | |
d6aab7a1 | 1231 | { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS }, |
9186c494 | 1232 | { STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS }, |
dd455cf5 | 1233 | { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS }, |
e413e4e9 AM |
1234 | }; |
1235 | ||
704209c0 | 1236 | #ifdef I386COFF |
a6c24e68 NC |
1237 | /* Like s_lcomm_internal in gas/read.c but the alignment string |
1238 | is allowed to be optional. */ | |
1239 | ||
1240 | static symbolS * | |
1241 | pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size) | |
1242 | { | |
1243 | addressT align = 0; | |
1244 | ||
1245 | SKIP_WHITESPACE (); | |
1246 | ||
7ab9ffdd | 1247 | if (needs_align |
a6c24e68 NC |
1248 | && *input_line_pointer == ',') |
1249 | { | |
1250 | align = parse_align (needs_align - 1); | |
7ab9ffdd | 1251 | |
a6c24e68 NC |
1252 | if (align == (addressT) -1) |
1253 | return NULL; | |
1254 | } | |
1255 | else | |
1256 | { | |
1257 | if (size >= 8) | |
1258 | align = 3; | |
1259 | else if (size >= 4) | |
1260 | align = 2; | |
1261 | else if (size >= 2) | |
1262 | align = 1; | |
1263 | else | |
1264 | align = 0; | |
1265 | } | |
1266 | ||
1267 | bss_alloc (symbolP, size, align); | |
1268 | return symbolP; | |
1269 | } | |
1270 | ||
704209c0 | 1271 | static void |
a6c24e68 NC |
1272 | pe_lcomm (int needs_align) |
1273 | { | |
1274 | s_comm_internal (needs_align * 2, pe_lcomm_internal); | |
1275 | } | |
704209c0 | 1276 | #endif |
a6c24e68 | 1277 | |
29b0f896 AM |
1278 | const pseudo_typeS md_pseudo_table[] = |
1279 | { | |
1280 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) | |
1281 | {"align", s_align_bytes, 0}, | |
1282 | #else | |
1283 | {"align", s_align_ptwo, 0}, | |
1284 | #endif | |
1285 | {"arch", set_cpu_arch, 0}, | |
1286 | #ifndef I386COFF | |
1287 | {"bss", s_bss, 0}, | |
a6c24e68 NC |
1288 | #else |
1289 | {"lcomm", pe_lcomm, 1}, | |
29b0f896 AM |
1290 | #endif |
1291 | {"ffloat", float_cons, 'f'}, | |
1292 | {"dfloat", float_cons, 'd'}, | |
1293 | {"tfloat", float_cons, 'x'}, | |
1294 | {"value", cons, 2}, | |
d182319b | 1295 | {"slong", signed_cons, 4}, |
29b0f896 AM |
1296 | {"noopt", s_ignore, 0}, |
1297 | {"optim", s_ignore, 0}, | |
1298 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, | |
1299 | {"code16", set_code_flag, CODE_16BIT}, | |
1300 | {"code32", set_code_flag, CODE_32BIT}, | |
da5f19a2 | 1301 | #ifdef BFD64 |
29b0f896 | 1302 | {"code64", set_code_flag, CODE_64BIT}, |
da5f19a2 | 1303 | #endif |
29b0f896 AM |
1304 | {"intel_syntax", set_intel_syntax, 1}, |
1305 | {"att_syntax", set_intel_syntax, 0}, | |
1efbbeb4 L |
1306 | {"intel_mnemonic", set_intel_mnemonic, 1}, |
1307 | {"att_mnemonic", set_intel_mnemonic, 0}, | |
db51cc60 L |
1308 | {"allow_index_reg", set_allow_index_reg, 1}, |
1309 | {"disallow_index_reg", set_allow_index_reg, 0}, | |
7bab8ab5 JB |
1310 | {"sse_check", set_check, 0}, |
1311 | {"operand_check", set_check, 1}, | |
3b22753a L |
1312 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
1313 | {"largecomm", handle_large_common, 0}, | |
07a53e5c | 1314 | #else |
68d20676 | 1315 | {"file", dwarf2_directive_file, 0}, |
07a53e5c RH |
1316 | {"loc", dwarf2_directive_loc, 0}, |
1317 | {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, | |
3b22753a | 1318 | #endif |
6482c264 NC |
1319 | #ifdef TE_PE |
1320 | {"secrel32", pe_directive_secrel, 0}, | |
1321 | #endif | |
29b0f896 AM |
1322 | {0, 0, 0} |
1323 | }; | |
1324 | ||
1325 | /* For interface with expression (). */ | |
1326 | extern char *input_line_pointer; | |
1327 | ||
1328 | /* Hash table for instruction mnemonic lookup. */ | |
1329 | static struct hash_control *op_hash; | |
1330 | ||
1331 | /* Hash table for register lookup. */ | |
1332 | static struct hash_control *reg_hash; | |
1333 | \f | |
ce8a8b2f AM |
1334 | /* Various efficient no-op patterns for aligning code labels. |
1335 | Note: Don't try to assemble the instructions in the comments. | |
1336 | 0L and 0w are not legal. */ | |
62a02d25 L |
1337 | static const unsigned char f32_1[] = |
1338 | {0x90}; /* nop */ | |
1339 | static const unsigned char f32_2[] = | |
1340 | {0x66,0x90}; /* xchg %ax,%ax */ | |
1341 | static const unsigned char f32_3[] = | |
1342 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
1343 | static const unsigned char f32_4[] = | |
1344 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
62a02d25 L |
1345 | static const unsigned char f32_6[] = |
1346 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
1347 | static const unsigned char f32_7[] = | |
1348 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
62a02d25 | 1349 | static const unsigned char f16_3[] = |
3ae729d5 | 1350 | {0x8d,0x74,0x00}; /* lea 0(%si),%si */ |
62a02d25 | 1351 | static const unsigned char f16_4[] = |
3ae729d5 L |
1352 | {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */ |
1353 | static const unsigned char jump_disp8[] = | |
1354 | {0xeb}; /* jmp disp8 */ | |
1355 | static const unsigned char jump32_disp32[] = | |
1356 | {0xe9}; /* jmp disp32 */ | |
1357 | static const unsigned char jump16_disp32[] = | |
1358 | {0x66,0xe9}; /* jmp disp32 */ | |
62a02d25 L |
1359 | /* 32-bit NOPs patterns. */ |
1360 | static const unsigned char *const f32_patt[] = { | |
3ae729d5 | 1361 | f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7 |
62a02d25 L |
1362 | }; |
1363 | /* 16-bit NOPs patterns. */ | |
1364 | static const unsigned char *const f16_patt[] = { | |
3ae729d5 | 1365 | f32_1, f32_2, f16_3, f16_4 |
62a02d25 L |
1366 | }; |
1367 | /* nopl (%[re]ax) */ | |
1368 | static const unsigned char alt_3[] = | |
1369 | {0x0f,0x1f,0x00}; | |
1370 | /* nopl 0(%[re]ax) */ | |
1371 | static const unsigned char alt_4[] = | |
1372 | {0x0f,0x1f,0x40,0x00}; | |
1373 | /* nopl 0(%[re]ax,%[re]ax,1) */ | |
1374 | static const unsigned char alt_5[] = | |
1375 | {0x0f,0x1f,0x44,0x00,0x00}; | |
1376 | /* nopw 0(%[re]ax,%[re]ax,1) */ | |
1377 | static const unsigned char alt_6[] = | |
1378 | {0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
1379 | /* nopl 0L(%[re]ax) */ | |
1380 | static const unsigned char alt_7[] = | |
1381 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
1382 | /* nopl 0L(%[re]ax,%[re]ax,1) */ | |
1383 | static const unsigned char alt_8[] = | |
1384 | {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1385 | /* nopw 0L(%[re]ax,%[re]ax,1) */ | |
1386 | static const unsigned char alt_9[] = | |
1387 | {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1388 | /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
1389 | static const unsigned char alt_10[] = | |
1390 | {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
3ae729d5 L |
1391 | /* data16 nopw %cs:0L(%eax,%eax,1) */ |
1392 | static const unsigned char alt_11[] = | |
1393 | {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
62a02d25 L |
1394 | /* 32-bit and 64-bit NOPs patterns. */ |
1395 | static const unsigned char *const alt_patt[] = { | |
1396 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
3ae729d5 | 1397 | alt_9, alt_10, alt_11 |
62a02d25 L |
1398 | }; |
1399 | ||
1400 | /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum | |
1401 | size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */ | |
1402 | ||
1403 | static void | |
1404 | i386_output_nops (char *where, const unsigned char *const *patt, | |
1405 | int count, int max_single_nop_size) | |
1406 | ||
1407 | { | |
3ae729d5 L |
1408 | /* Place the longer NOP first. */ |
1409 | int last; | |
1410 | int offset; | |
3076e594 NC |
1411 | const unsigned char *nops; |
1412 | ||
1413 | if (max_single_nop_size < 1) | |
1414 | { | |
1415 | as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"), | |
1416 | max_single_nop_size); | |
1417 | return; | |
1418 | } | |
1419 | ||
1420 | nops = patt[max_single_nop_size - 1]; | |
3ae729d5 L |
1421 | |
1422 | /* Use the smaller one if the requsted one isn't available. */ | |
1423 | if (nops == NULL) | |
62a02d25 | 1424 | { |
3ae729d5 L |
1425 | max_single_nop_size--; |
1426 | nops = patt[max_single_nop_size - 1]; | |
62a02d25 L |
1427 | } |
1428 | ||
3ae729d5 L |
1429 | last = count % max_single_nop_size; |
1430 | ||
1431 | count -= last; | |
1432 | for (offset = 0; offset < count; offset += max_single_nop_size) | |
1433 | memcpy (where + offset, nops, max_single_nop_size); | |
1434 | ||
1435 | if (last) | |
1436 | { | |
1437 | nops = patt[last - 1]; | |
1438 | if (nops == NULL) | |
1439 | { | |
1440 | /* Use the smaller one plus one-byte NOP if the needed one | |
1441 | isn't available. */ | |
1442 | last--; | |
1443 | nops = patt[last - 1]; | |
1444 | memcpy (where + offset, nops, last); | |
1445 | where[offset + last] = *patt[0]; | |
1446 | } | |
1447 | else | |
1448 | memcpy (where + offset, nops, last); | |
1449 | } | |
62a02d25 L |
1450 | } |
1451 | ||
3ae729d5 L |
1452 | static INLINE int |
1453 | fits_in_imm7 (offsetT num) | |
1454 | { | |
1455 | return (num & 0x7f) == num; | |
1456 | } | |
1457 | ||
1458 | static INLINE int | |
1459 | fits_in_imm31 (offsetT num) | |
1460 | { | |
1461 | return (num & 0x7fffffff) == num; | |
1462 | } | |
62a02d25 L |
1463 | |
1464 | /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a | |
1465 | single NOP instruction LIMIT. */ | |
1466 | ||
1467 | void | |
3ae729d5 | 1468 | i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit) |
62a02d25 | 1469 | { |
3ae729d5 | 1470 | const unsigned char *const *patt = NULL; |
62a02d25 | 1471 | int max_single_nop_size; |
3ae729d5 L |
1472 | /* Maximum number of NOPs before switching to jump over NOPs. */ |
1473 | int max_number_of_nops; | |
62a02d25 | 1474 | |
3ae729d5 | 1475 | switch (fragP->fr_type) |
62a02d25 | 1476 | { |
3ae729d5 L |
1477 | case rs_fill_nop: |
1478 | case rs_align_code: | |
1479 | break; | |
e379e5f3 L |
1480 | case rs_machine_dependent: |
1481 | /* Allow NOP padding for jumps and calls. */ | |
1482 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING | |
1483 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
1484 | break; | |
1485 | /* Fall through. */ | |
3ae729d5 | 1486 | default: |
62a02d25 L |
1487 | return; |
1488 | } | |
1489 | ||
ccc9c027 L |
1490 | /* We need to decide which NOP sequence to use for 32bit and |
1491 | 64bit. When -mtune= is used: | |
4eed87de | 1492 | |
76bc74dc L |
1493 | 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and |
1494 | PROCESSOR_GENERIC32, f32_patt will be used. | |
80b8656c L |
1495 | 2. For the rest, alt_patt will be used. |
1496 | ||
1497 | When -mtune= isn't used, alt_patt will be used if | |
22109423 | 1498 | cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will |
76bc74dc | 1499 | be used. |
ccc9c027 L |
1500 | |
1501 | When -march= or .arch is used, we can't use anything beyond | |
1502 | cpu_arch_isa_flags. */ | |
1503 | ||
1504 | if (flag_code == CODE_16BIT) | |
1505 | { | |
3ae729d5 L |
1506 | patt = f16_patt; |
1507 | max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]); | |
1508 | /* Limit number of NOPs to 2 in 16-bit mode. */ | |
1509 | max_number_of_nops = 2; | |
252b5132 | 1510 | } |
33fef721 | 1511 | else |
ccc9c027 | 1512 | { |
fbf3f584 | 1513 | if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN) |
ccc9c027 L |
1514 | { |
1515 | /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ | |
1516 | switch (cpu_arch_tune) | |
1517 | { | |
1518 | case PROCESSOR_UNKNOWN: | |
1519 | /* We use cpu_arch_isa_flags to check if we SHOULD | |
22109423 L |
1520 | optimize with nops. */ |
1521 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1522 | patt = alt_patt; |
ccc9c027 L |
1523 | else |
1524 | patt = f32_patt; | |
1525 | break; | |
ccc9c027 L |
1526 | case PROCESSOR_PENTIUM4: |
1527 | case PROCESSOR_NOCONA: | |
ef05d495 | 1528 | case PROCESSOR_CORE: |
76bc74dc | 1529 | case PROCESSOR_CORE2: |
bd5295b2 | 1530 | case PROCESSOR_COREI7: |
3632d14b | 1531 | case PROCESSOR_L1OM: |
7a9068fe | 1532 | case PROCESSOR_K1OM: |
76bc74dc | 1533 | case PROCESSOR_GENERIC64: |
ccc9c027 L |
1534 | case PROCESSOR_K6: |
1535 | case PROCESSOR_ATHLON: | |
1536 | case PROCESSOR_K8: | |
4eed87de | 1537 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1538 | case PROCESSOR_BD: |
029f3522 | 1539 | case PROCESSOR_ZNVER: |
7b458c12 | 1540 | case PROCESSOR_BT: |
80b8656c | 1541 | patt = alt_patt; |
ccc9c027 | 1542 | break; |
76bc74dc | 1543 | case PROCESSOR_I386: |
ccc9c027 L |
1544 | case PROCESSOR_I486: |
1545 | case PROCESSOR_PENTIUM: | |
2dde1948 | 1546 | case PROCESSOR_PENTIUMPRO: |
81486035 | 1547 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1548 | case PROCESSOR_GENERIC32: |
1549 | patt = f32_patt; | |
1550 | break; | |
4eed87de | 1551 | } |
ccc9c027 L |
1552 | } |
1553 | else | |
1554 | { | |
fbf3f584 | 1555 | switch (fragP->tc_frag_data.tune) |
ccc9c027 L |
1556 | { |
1557 | case PROCESSOR_UNKNOWN: | |
e6a14101 | 1558 | /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be |
ccc9c027 L |
1559 | PROCESSOR_UNKNOWN. */ |
1560 | abort (); | |
1561 | break; | |
1562 | ||
76bc74dc | 1563 | case PROCESSOR_I386: |
ccc9c027 L |
1564 | case PROCESSOR_I486: |
1565 | case PROCESSOR_PENTIUM: | |
81486035 | 1566 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1567 | case PROCESSOR_K6: |
1568 | case PROCESSOR_ATHLON: | |
1569 | case PROCESSOR_K8: | |
4eed87de | 1570 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1571 | case PROCESSOR_BD: |
029f3522 | 1572 | case PROCESSOR_ZNVER: |
7b458c12 | 1573 | case PROCESSOR_BT: |
ccc9c027 L |
1574 | case PROCESSOR_GENERIC32: |
1575 | /* We use cpu_arch_isa_flags to check if we CAN optimize | |
22109423 L |
1576 | with nops. */ |
1577 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1578 | patt = alt_patt; |
ccc9c027 L |
1579 | else |
1580 | patt = f32_patt; | |
1581 | break; | |
76bc74dc L |
1582 | case PROCESSOR_PENTIUMPRO: |
1583 | case PROCESSOR_PENTIUM4: | |
1584 | case PROCESSOR_NOCONA: | |
1585 | case PROCESSOR_CORE: | |
ef05d495 | 1586 | case PROCESSOR_CORE2: |
bd5295b2 | 1587 | case PROCESSOR_COREI7: |
3632d14b | 1588 | case PROCESSOR_L1OM: |
7a9068fe | 1589 | case PROCESSOR_K1OM: |
22109423 | 1590 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) |
80b8656c | 1591 | patt = alt_patt; |
ccc9c027 L |
1592 | else |
1593 | patt = f32_patt; | |
1594 | break; | |
1595 | case PROCESSOR_GENERIC64: | |
80b8656c | 1596 | patt = alt_patt; |
ccc9c027 | 1597 | break; |
4eed87de | 1598 | } |
ccc9c027 L |
1599 | } |
1600 | ||
76bc74dc L |
1601 | if (patt == f32_patt) |
1602 | { | |
3ae729d5 L |
1603 | max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]); |
1604 | /* Limit number of NOPs to 2 for older processors. */ | |
1605 | max_number_of_nops = 2; | |
76bc74dc L |
1606 | } |
1607 | else | |
1608 | { | |
3ae729d5 L |
1609 | max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]); |
1610 | /* Limit number of NOPs to 7 for newer processors. */ | |
1611 | max_number_of_nops = 7; | |
1612 | } | |
1613 | } | |
1614 | ||
1615 | if (limit == 0) | |
1616 | limit = max_single_nop_size; | |
1617 | ||
1618 | if (fragP->fr_type == rs_fill_nop) | |
1619 | { | |
1620 | /* Output NOPs for .nop directive. */ | |
1621 | if (limit > max_single_nop_size) | |
1622 | { | |
1623 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1624 | _("invalid single nop size: %d " | |
1625 | "(expect within [0, %d])"), | |
1626 | limit, max_single_nop_size); | |
1627 | return; | |
1628 | } | |
1629 | } | |
e379e5f3 | 1630 | else if (fragP->fr_type != rs_machine_dependent) |
3ae729d5 L |
1631 | fragP->fr_var = count; |
1632 | ||
1633 | if ((count / max_single_nop_size) > max_number_of_nops) | |
1634 | { | |
1635 | /* Generate jump over NOPs. */ | |
1636 | offsetT disp = count - 2; | |
1637 | if (fits_in_imm7 (disp)) | |
1638 | { | |
1639 | /* Use "jmp disp8" if possible. */ | |
1640 | count = disp; | |
1641 | where[0] = jump_disp8[0]; | |
1642 | where[1] = count; | |
1643 | where += 2; | |
1644 | } | |
1645 | else | |
1646 | { | |
1647 | unsigned int size_of_jump; | |
1648 | ||
1649 | if (flag_code == CODE_16BIT) | |
1650 | { | |
1651 | where[0] = jump16_disp32[0]; | |
1652 | where[1] = jump16_disp32[1]; | |
1653 | size_of_jump = 2; | |
1654 | } | |
1655 | else | |
1656 | { | |
1657 | where[0] = jump32_disp32[0]; | |
1658 | size_of_jump = 1; | |
1659 | } | |
1660 | ||
1661 | count -= size_of_jump + 4; | |
1662 | if (!fits_in_imm31 (count)) | |
1663 | { | |
1664 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1665 | _("jump over nop padding out of range")); | |
1666 | return; | |
1667 | } | |
1668 | ||
1669 | md_number_to_chars (where + size_of_jump, count, 4); | |
1670 | where += size_of_jump + 4; | |
76bc74dc | 1671 | } |
ccc9c027 | 1672 | } |
3ae729d5 L |
1673 | |
1674 | /* Generate multiple NOPs. */ | |
1675 | i386_output_nops (where, patt, count, limit); | |
252b5132 RH |
1676 | } |
1677 | ||
c6fb90c8 | 1678 | static INLINE int |
0dfbf9d7 | 1679 | operand_type_all_zero (const union i386_operand_type *x) |
40fb9820 | 1680 | { |
0dfbf9d7 | 1681 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1682 | { |
1683 | case 3: | |
0dfbf9d7 | 1684 | if (x->array[2]) |
c6fb90c8 | 1685 | return 0; |
1a0670f3 | 1686 | /* Fall through. */ |
c6fb90c8 | 1687 | case 2: |
0dfbf9d7 | 1688 | if (x->array[1]) |
c6fb90c8 | 1689 | return 0; |
1a0670f3 | 1690 | /* Fall through. */ |
c6fb90c8 | 1691 | case 1: |
0dfbf9d7 | 1692 | return !x->array[0]; |
c6fb90c8 L |
1693 | default: |
1694 | abort (); | |
1695 | } | |
40fb9820 L |
1696 | } |
1697 | ||
c6fb90c8 | 1698 | static INLINE void |
0dfbf9d7 | 1699 | operand_type_set (union i386_operand_type *x, unsigned int v) |
40fb9820 | 1700 | { |
0dfbf9d7 | 1701 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1702 | { |
1703 | case 3: | |
0dfbf9d7 | 1704 | x->array[2] = v; |
1a0670f3 | 1705 | /* Fall through. */ |
c6fb90c8 | 1706 | case 2: |
0dfbf9d7 | 1707 | x->array[1] = v; |
1a0670f3 | 1708 | /* Fall through. */ |
c6fb90c8 | 1709 | case 1: |
0dfbf9d7 | 1710 | x->array[0] = v; |
1a0670f3 | 1711 | /* Fall through. */ |
c6fb90c8 L |
1712 | break; |
1713 | default: | |
1714 | abort (); | |
1715 | } | |
bab6aec1 JB |
1716 | |
1717 | x->bitfield.class = ClassNone; | |
75e5731b | 1718 | x->bitfield.instance = InstanceNone; |
c6fb90c8 | 1719 | } |
40fb9820 | 1720 | |
c6fb90c8 | 1721 | static INLINE int |
0dfbf9d7 L |
1722 | operand_type_equal (const union i386_operand_type *x, |
1723 | const union i386_operand_type *y) | |
c6fb90c8 | 1724 | { |
0dfbf9d7 | 1725 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1726 | { |
1727 | case 3: | |
0dfbf9d7 | 1728 | if (x->array[2] != y->array[2]) |
c6fb90c8 | 1729 | return 0; |
1a0670f3 | 1730 | /* Fall through. */ |
c6fb90c8 | 1731 | case 2: |
0dfbf9d7 | 1732 | if (x->array[1] != y->array[1]) |
c6fb90c8 | 1733 | return 0; |
1a0670f3 | 1734 | /* Fall through. */ |
c6fb90c8 | 1735 | case 1: |
0dfbf9d7 | 1736 | return x->array[0] == y->array[0]; |
c6fb90c8 L |
1737 | break; |
1738 | default: | |
1739 | abort (); | |
1740 | } | |
1741 | } | |
40fb9820 | 1742 | |
0dfbf9d7 L |
1743 | static INLINE int |
1744 | cpu_flags_all_zero (const union i386_cpu_flags *x) | |
1745 | { | |
1746 | switch (ARRAY_SIZE(x->array)) | |
1747 | { | |
53467f57 IT |
1748 | case 4: |
1749 | if (x->array[3]) | |
1750 | return 0; | |
1751 | /* Fall through. */ | |
0dfbf9d7 L |
1752 | case 3: |
1753 | if (x->array[2]) | |
1754 | return 0; | |
1a0670f3 | 1755 | /* Fall through. */ |
0dfbf9d7 L |
1756 | case 2: |
1757 | if (x->array[1]) | |
1758 | return 0; | |
1a0670f3 | 1759 | /* Fall through. */ |
0dfbf9d7 L |
1760 | case 1: |
1761 | return !x->array[0]; | |
1762 | default: | |
1763 | abort (); | |
1764 | } | |
1765 | } | |
1766 | ||
0dfbf9d7 L |
1767 | static INLINE int |
1768 | cpu_flags_equal (const union i386_cpu_flags *x, | |
1769 | const union i386_cpu_flags *y) | |
1770 | { | |
1771 | switch (ARRAY_SIZE(x->array)) | |
1772 | { | |
53467f57 IT |
1773 | case 4: |
1774 | if (x->array[3] != y->array[3]) | |
1775 | return 0; | |
1776 | /* Fall through. */ | |
0dfbf9d7 L |
1777 | case 3: |
1778 | if (x->array[2] != y->array[2]) | |
1779 | return 0; | |
1a0670f3 | 1780 | /* Fall through. */ |
0dfbf9d7 L |
1781 | case 2: |
1782 | if (x->array[1] != y->array[1]) | |
1783 | return 0; | |
1a0670f3 | 1784 | /* Fall through. */ |
0dfbf9d7 L |
1785 | case 1: |
1786 | return x->array[0] == y->array[0]; | |
1787 | break; | |
1788 | default: | |
1789 | abort (); | |
1790 | } | |
1791 | } | |
c6fb90c8 L |
1792 | |
1793 | static INLINE int | |
1794 | cpu_flags_check_cpu64 (i386_cpu_flags f) | |
1795 | { | |
1796 | return !((flag_code == CODE_64BIT && f.bitfield.cpuno64) | |
1797 | || (flag_code != CODE_64BIT && f.bitfield.cpu64)); | |
40fb9820 L |
1798 | } |
1799 | ||
c6fb90c8 L |
1800 | static INLINE i386_cpu_flags |
1801 | cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1802 | { |
c6fb90c8 L |
1803 | switch (ARRAY_SIZE (x.array)) |
1804 | { | |
53467f57 IT |
1805 | case 4: |
1806 | x.array [3] &= y.array [3]; | |
1807 | /* Fall through. */ | |
c6fb90c8 L |
1808 | case 3: |
1809 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1810 | /* Fall through. */ |
c6fb90c8 L |
1811 | case 2: |
1812 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1813 | /* Fall through. */ |
c6fb90c8 L |
1814 | case 1: |
1815 | x.array [0] &= y.array [0]; | |
1816 | break; | |
1817 | default: | |
1818 | abort (); | |
1819 | } | |
1820 | return x; | |
1821 | } | |
40fb9820 | 1822 | |
c6fb90c8 L |
1823 | static INLINE i386_cpu_flags |
1824 | cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1825 | { |
c6fb90c8 | 1826 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1827 | { |
53467f57 IT |
1828 | case 4: |
1829 | x.array [3] |= y.array [3]; | |
1830 | /* Fall through. */ | |
c6fb90c8 L |
1831 | case 3: |
1832 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1833 | /* Fall through. */ |
c6fb90c8 L |
1834 | case 2: |
1835 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1836 | /* Fall through. */ |
c6fb90c8 L |
1837 | case 1: |
1838 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1839 | break; |
1840 | default: | |
1841 | abort (); | |
1842 | } | |
40fb9820 L |
1843 | return x; |
1844 | } | |
1845 | ||
309d3373 JB |
1846 | static INLINE i386_cpu_flags |
1847 | cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y) | |
1848 | { | |
1849 | switch (ARRAY_SIZE (x.array)) | |
1850 | { | |
53467f57 IT |
1851 | case 4: |
1852 | x.array [3] &= ~y.array [3]; | |
1853 | /* Fall through. */ | |
309d3373 JB |
1854 | case 3: |
1855 | x.array [2] &= ~y.array [2]; | |
1a0670f3 | 1856 | /* Fall through. */ |
309d3373 JB |
1857 | case 2: |
1858 | x.array [1] &= ~y.array [1]; | |
1a0670f3 | 1859 | /* Fall through. */ |
309d3373 JB |
1860 | case 1: |
1861 | x.array [0] &= ~y.array [0]; | |
1862 | break; | |
1863 | default: | |
1864 | abort (); | |
1865 | } | |
1866 | return x; | |
1867 | } | |
1868 | ||
6c0946d0 JB |
1869 | static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS; |
1870 | ||
c0f3af97 L |
1871 | #define CPU_FLAGS_ARCH_MATCH 0x1 |
1872 | #define CPU_FLAGS_64BIT_MATCH 0x2 | |
1873 | ||
c0f3af97 | 1874 | #define CPU_FLAGS_PERFECT_MATCH \ |
db12e14e | 1875 | (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH) |
c0f3af97 L |
1876 | |
1877 | /* Return CPU flags match bits. */ | |
3629bb00 | 1878 | |
40fb9820 | 1879 | static int |
d3ce72d0 | 1880 | cpu_flags_match (const insn_template *t) |
40fb9820 | 1881 | { |
c0f3af97 L |
1882 | i386_cpu_flags x = t->cpu_flags; |
1883 | int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0; | |
40fb9820 L |
1884 | |
1885 | x.bitfield.cpu64 = 0; | |
1886 | x.bitfield.cpuno64 = 0; | |
1887 | ||
0dfbf9d7 | 1888 | if (cpu_flags_all_zero (&x)) |
c0f3af97 L |
1889 | { |
1890 | /* This instruction is available on all archs. */ | |
db12e14e | 1891 | match |= CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1892 | } |
3629bb00 L |
1893 | else |
1894 | { | |
c0f3af97 | 1895 | /* This instruction is available only on some archs. */ |
3629bb00 L |
1896 | i386_cpu_flags cpu = cpu_arch_flags; |
1897 | ||
ab592e75 JB |
1898 | /* AVX512VL is no standalone feature - match it and then strip it. */ |
1899 | if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl) | |
1900 | return match; | |
1901 | x.bitfield.cpuavx512vl = 0; | |
1902 | ||
3629bb00 | 1903 | cpu = cpu_flags_and (x, cpu); |
c0f3af97 L |
1904 | if (!cpu_flags_all_zero (&cpu)) |
1905 | { | |
a5ff0eb2 L |
1906 | if (x.bitfield.cpuavx) |
1907 | { | |
929f69fa | 1908 | /* We need to check a few extra flags with AVX. */ |
b9d49817 JB |
1909 | if (cpu.bitfield.cpuavx |
1910 | && (!t->opcode_modifier.sse2avx || sse2avx) | |
1911 | && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes) | |
929f69fa | 1912 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) |
b9d49817 JB |
1913 | && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul)) |
1914 | match |= CPU_FLAGS_ARCH_MATCH; | |
a5ff0eb2 | 1915 | } |
929f69fa JB |
1916 | else if (x.bitfield.cpuavx512f) |
1917 | { | |
1918 | /* We need to check a few extra flags with AVX512F. */ | |
1919 | if (cpu.bitfield.cpuavx512f | |
1920 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) | |
1921 | && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes) | |
1922 | && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq)) | |
1923 | match |= CPU_FLAGS_ARCH_MATCH; | |
1924 | } | |
a5ff0eb2 | 1925 | else |
db12e14e | 1926 | match |= CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1927 | } |
3629bb00 | 1928 | } |
c0f3af97 | 1929 | return match; |
40fb9820 L |
1930 | } |
1931 | ||
c6fb90c8 L |
1932 | static INLINE i386_operand_type |
1933 | operand_type_and (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1934 | { |
bab6aec1 JB |
1935 | if (x.bitfield.class != y.bitfield.class) |
1936 | x.bitfield.class = ClassNone; | |
75e5731b JB |
1937 | if (x.bitfield.instance != y.bitfield.instance) |
1938 | x.bitfield.instance = InstanceNone; | |
bab6aec1 | 1939 | |
c6fb90c8 L |
1940 | switch (ARRAY_SIZE (x.array)) |
1941 | { | |
1942 | case 3: | |
1943 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1944 | /* Fall through. */ |
c6fb90c8 L |
1945 | case 2: |
1946 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1947 | /* Fall through. */ |
c6fb90c8 L |
1948 | case 1: |
1949 | x.array [0] &= y.array [0]; | |
1950 | break; | |
1951 | default: | |
1952 | abort (); | |
1953 | } | |
1954 | return x; | |
40fb9820 L |
1955 | } |
1956 | ||
73053c1f JB |
1957 | static INLINE i386_operand_type |
1958 | operand_type_and_not (i386_operand_type x, i386_operand_type y) | |
1959 | { | |
bab6aec1 | 1960 | gas_assert (y.bitfield.class == ClassNone); |
75e5731b | 1961 | gas_assert (y.bitfield.instance == InstanceNone); |
bab6aec1 | 1962 | |
73053c1f JB |
1963 | switch (ARRAY_SIZE (x.array)) |
1964 | { | |
1965 | case 3: | |
1966 | x.array [2] &= ~y.array [2]; | |
1967 | /* Fall through. */ | |
1968 | case 2: | |
1969 | x.array [1] &= ~y.array [1]; | |
1970 | /* Fall through. */ | |
1971 | case 1: | |
1972 | x.array [0] &= ~y.array [0]; | |
1973 | break; | |
1974 | default: | |
1975 | abort (); | |
1976 | } | |
1977 | return x; | |
1978 | } | |
1979 | ||
c6fb90c8 L |
1980 | static INLINE i386_operand_type |
1981 | operand_type_or (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1982 | { |
bab6aec1 JB |
1983 | gas_assert (x.bitfield.class == ClassNone || |
1984 | y.bitfield.class == ClassNone || | |
1985 | x.bitfield.class == y.bitfield.class); | |
75e5731b JB |
1986 | gas_assert (x.bitfield.instance == InstanceNone || |
1987 | y.bitfield.instance == InstanceNone || | |
1988 | x.bitfield.instance == y.bitfield.instance); | |
bab6aec1 | 1989 | |
c6fb90c8 | 1990 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1991 | { |
c6fb90c8 L |
1992 | case 3: |
1993 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1994 | /* Fall through. */ |
c6fb90c8 L |
1995 | case 2: |
1996 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1997 | /* Fall through. */ |
c6fb90c8 L |
1998 | case 1: |
1999 | x.array [0] |= y.array [0]; | |
40fb9820 L |
2000 | break; |
2001 | default: | |
2002 | abort (); | |
2003 | } | |
c6fb90c8 L |
2004 | return x; |
2005 | } | |
40fb9820 | 2006 | |
c6fb90c8 L |
2007 | static INLINE i386_operand_type |
2008 | operand_type_xor (i386_operand_type x, i386_operand_type y) | |
2009 | { | |
bab6aec1 | 2010 | gas_assert (y.bitfield.class == ClassNone); |
75e5731b | 2011 | gas_assert (y.bitfield.instance == InstanceNone); |
bab6aec1 | 2012 | |
c6fb90c8 L |
2013 | switch (ARRAY_SIZE (x.array)) |
2014 | { | |
2015 | case 3: | |
2016 | x.array [2] ^= y.array [2]; | |
1a0670f3 | 2017 | /* Fall through. */ |
c6fb90c8 L |
2018 | case 2: |
2019 | x.array [1] ^= y.array [1]; | |
1a0670f3 | 2020 | /* Fall through. */ |
c6fb90c8 L |
2021 | case 1: |
2022 | x.array [0] ^= y.array [0]; | |
2023 | break; | |
2024 | default: | |
2025 | abort (); | |
2026 | } | |
40fb9820 L |
2027 | return x; |
2028 | } | |
2029 | ||
40fb9820 L |
2030 | static const i386_operand_type disp16 = OPERAND_TYPE_DISP16; |
2031 | static const i386_operand_type disp32 = OPERAND_TYPE_DISP32; | |
2032 | static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S; | |
2033 | static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32; | |
bab6aec1 JB |
2034 | static const i386_operand_type anydisp = OPERAND_TYPE_ANYDISP; |
2035 | static const i386_operand_type anyimm = OPERAND_TYPE_ANYIMM; | |
40fb9820 | 2036 | static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM; |
43234a1e | 2037 | static const i386_operand_type regmask = OPERAND_TYPE_REGMASK; |
40fb9820 L |
2038 | static const i386_operand_type imm8 = OPERAND_TYPE_IMM8; |
2039 | static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S; | |
2040 | static const i386_operand_type imm16 = OPERAND_TYPE_IMM16; | |
2041 | static const i386_operand_type imm32 = OPERAND_TYPE_IMM32; | |
2042 | static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S; | |
2043 | static const i386_operand_type imm64 = OPERAND_TYPE_IMM64; | |
2044 | static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32; | |
2045 | static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S; | |
2046 | static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S; | |
2047 | ||
2048 | enum operand_type | |
2049 | { | |
2050 | reg, | |
40fb9820 L |
2051 | imm, |
2052 | disp, | |
2053 | anymem | |
2054 | }; | |
2055 | ||
c6fb90c8 | 2056 | static INLINE int |
40fb9820 L |
2057 | operand_type_check (i386_operand_type t, enum operand_type c) |
2058 | { | |
2059 | switch (c) | |
2060 | { | |
2061 | case reg: | |
bab6aec1 | 2062 | return t.bitfield.class == Reg; |
40fb9820 | 2063 | |
40fb9820 L |
2064 | case imm: |
2065 | return (t.bitfield.imm8 | |
2066 | || t.bitfield.imm8s | |
2067 | || t.bitfield.imm16 | |
2068 | || t.bitfield.imm32 | |
2069 | || t.bitfield.imm32s | |
2070 | || t.bitfield.imm64); | |
2071 | ||
2072 | case disp: | |
2073 | return (t.bitfield.disp8 | |
2074 | || t.bitfield.disp16 | |
2075 | || t.bitfield.disp32 | |
2076 | || t.bitfield.disp32s | |
2077 | || t.bitfield.disp64); | |
2078 | ||
2079 | case anymem: | |
2080 | return (t.bitfield.disp8 | |
2081 | || t.bitfield.disp16 | |
2082 | || t.bitfield.disp32 | |
2083 | || t.bitfield.disp32s | |
2084 | || t.bitfield.disp64 | |
2085 | || t.bitfield.baseindex); | |
2086 | ||
2087 | default: | |
2088 | abort (); | |
2089 | } | |
2cfe26b6 AM |
2090 | |
2091 | return 0; | |
40fb9820 L |
2092 | } |
2093 | ||
7a54636a L |
2094 | /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size |
2095 | between operand GIVEN and opeand WANTED for instruction template T. */ | |
5c07affc L |
2096 | |
2097 | static INLINE int | |
7a54636a L |
2098 | match_operand_size (const insn_template *t, unsigned int wanted, |
2099 | unsigned int given) | |
5c07affc | 2100 | { |
3ac21baa JB |
2101 | return !((i.types[given].bitfield.byte |
2102 | && !t->operand_types[wanted].bitfield.byte) | |
2103 | || (i.types[given].bitfield.word | |
2104 | && !t->operand_types[wanted].bitfield.word) | |
2105 | || (i.types[given].bitfield.dword | |
2106 | && !t->operand_types[wanted].bitfield.dword) | |
2107 | || (i.types[given].bitfield.qword | |
2108 | && !t->operand_types[wanted].bitfield.qword) | |
2109 | || (i.types[given].bitfield.tbyte | |
2110 | && !t->operand_types[wanted].bitfield.tbyte)); | |
5c07affc L |
2111 | } |
2112 | ||
dd40ce22 L |
2113 | /* Return 1 if there is no conflict in SIMD register between operand |
2114 | GIVEN and opeand WANTED for instruction template T. */ | |
1b54b8d7 JB |
2115 | |
2116 | static INLINE int | |
dd40ce22 L |
2117 | match_simd_size (const insn_template *t, unsigned int wanted, |
2118 | unsigned int given) | |
1b54b8d7 | 2119 | { |
3ac21baa JB |
2120 | return !((i.types[given].bitfield.xmmword |
2121 | && !t->operand_types[wanted].bitfield.xmmword) | |
2122 | || (i.types[given].bitfield.ymmword | |
2123 | && !t->operand_types[wanted].bitfield.ymmword) | |
2124 | || (i.types[given].bitfield.zmmword | |
2125 | && !t->operand_types[wanted].bitfield.zmmword)); | |
1b54b8d7 JB |
2126 | } |
2127 | ||
7a54636a L |
2128 | /* Return 1 if there is no conflict in any size between operand GIVEN |
2129 | and opeand WANTED for instruction template T. */ | |
5c07affc L |
2130 | |
2131 | static INLINE int | |
dd40ce22 L |
2132 | match_mem_size (const insn_template *t, unsigned int wanted, |
2133 | unsigned int given) | |
5c07affc | 2134 | { |
7a54636a | 2135 | return (match_operand_size (t, wanted, given) |
3ac21baa | 2136 | && !((i.types[given].bitfield.unspecified |
af508cb9 | 2137 | && !i.broadcast |
3ac21baa JB |
2138 | && !t->operand_types[wanted].bitfield.unspecified) |
2139 | || (i.types[given].bitfield.fword | |
2140 | && !t->operand_types[wanted].bitfield.fword) | |
1b54b8d7 JB |
2141 | /* For scalar opcode templates to allow register and memory |
2142 | operands at the same time, some special casing is needed | |
d6793fa1 JB |
2143 | here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and |
2144 | down-conversion vpmov*. */ | |
3528c362 | 2145 | || ((t->operand_types[wanted].bitfield.class == RegSIMD |
1b54b8d7 | 2146 | && !t->opcode_modifier.broadcast |
3ac21baa JB |
2147 | && (t->operand_types[wanted].bitfield.byte |
2148 | || t->operand_types[wanted].bitfield.word | |
2149 | || t->operand_types[wanted].bitfield.dword | |
2150 | || t->operand_types[wanted].bitfield.qword)) | |
2151 | ? (i.types[given].bitfield.xmmword | |
2152 | || i.types[given].bitfield.ymmword | |
2153 | || i.types[given].bitfield.zmmword) | |
2154 | : !match_simd_size(t, wanted, given)))); | |
5c07affc L |
2155 | } |
2156 | ||
3ac21baa JB |
2157 | /* Return value has MATCH_STRAIGHT set if there is no size conflict on any |
2158 | operands for instruction template T, and it has MATCH_REVERSE set if there | |
2159 | is no size conflict on any operands for the template with operands reversed | |
2160 | (and the template allows for reversing in the first place). */ | |
5c07affc | 2161 | |
3ac21baa JB |
2162 | #define MATCH_STRAIGHT 1 |
2163 | #define MATCH_REVERSE 2 | |
2164 | ||
2165 | static INLINE unsigned int | |
d3ce72d0 | 2166 | operand_size_match (const insn_template *t) |
5c07affc | 2167 | { |
3ac21baa | 2168 | unsigned int j, match = MATCH_STRAIGHT; |
5c07affc | 2169 | |
0cfa3eb3 | 2170 | /* Don't check non-absolute jump instructions. */ |
5c07affc | 2171 | if (t->opcode_modifier.jump |
0cfa3eb3 | 2172 | && t->opcode_modifier.jump != JUMP_ABSOLUTE) |
5c07affc L |
2173 | return match; |
2174 | ||
2175 | /* Check memory and accumulator operand size. */ | |
2176 | for (j = 0; j < i.operands; j++) | |
2177 | { | |
3528c362 JB |
2178 | if (i.types[j].bitfield.class != Reg |
2179 | && i.types[j].bitfield.class != RegSIMD | |
601e8564 | 2180 | && t->opcode_modifier.anysize) |
5c07affc L |
2181 | continue; |
2182 | ||
bab6aec1 | 2183 | if (t->operand_types[j].bitfield.class == Reg |
7a54636a | 2184 | && !match_operand_size (t, j, j)) |
5c07affc L |
2185 | { |
2186 | match = 0; | |
2187 | break; | |
2188 | } | |
2189 | ||
3528c362 | 2190 | if (t->operand_types[j].bitfield.class == RegSIMD |
3ac21baa | 2191 | && !match_simd_size (t, j, j)) |
1b54b8d7 JB |
2192 | { |
2193 | match = 0; | |
2194 | break; | |
2195 | } | |
2196 | ||
75e5731b | 2197 | if (t->operand_types[j].bitfield.instance == Accum |
7a54636a | 2198 | && (!match_operand_size (t, j, j) || !match_simd_size (t, j, j))) |
1b54b8d7 JB |
2199 | { |
2200 | match = 0; | |
2201 | break; | |
2202 | } | |
2203 | ||
c48dadc9 | 2204 | if ((i.flags[j] & Operand_Mem) && !match_mem_size (t, j, j)) |
5c07affc L |
2205 | { |
2206 | match = 0; | |
2207 | break; | |
2208 | } | |
2209 | } | |
2210 | ||
3ac21baa | 2211 | if (!t->opcode_modifier.d) |
891edac4 | 2212 | { |
dc1e8a47 | 2213 | mismatch: |
3ac21baa JB |
2214 | if (!match) |
2215 | i.error = operand_size_mismatch; | |
2216 | return match; | |
891edac4 | 2217 | } |
5c07affc L |
2218 | |
2219 | /* Check reverse. */ | |
f5eb1d70 | 2220 | gas_assert (i.operands >= 2 && i.operands <= 3); |
5c07affc | 2221 | |
f5eb1d70 | 2222 | for (j = 0; j < i.operands; j++) |
5c07affc | 2223 | { |
f5eb1d70 JB |
2224 | unsigned int given = i.operands - j - 1; |
2225 | ||
bab6aec1 | 2226 | if (t->operand_types[j].bitfield.class == Reg |
f5eb1d70 | 2227 | && !match_operand_size (t, j, given)) |
891edac4 | 2228 | goto mismatch; |
5c07affc | 2229 | |
3528c362 | 2230 | if (t->operand_types[j].bitfield.class == RegSIMD |
f5eb1d70 | 2231 | && !match_simd_size (t, j, given)) |
dbbc8b7e JB |
2232 | goto mismatch; |
2233 | ||
75e5731b | 2234 | if (t->operand_types[j].bitfield.instance == Accum |
f5eb1d70 JB |
2235 | && (!match_operand_size (t, j, given) |
2236 | || !match_simd_size (t, j, given))) | |
dbbc8b7e JB |
2237 | goto mismatch; |
2238 | ||
f5eb1d70 | 2239 | if ((i.flags[given] & Operand_Mem) && !match_mem_size (t, j, given)) |
891edac4 | 2240 | goto mismatch; |
5c07affc L |
2241 | } |
2242 | ||
3ac21baa | 2243 | return match | MATCH_REVERSE; |
5c07affc L |
2244 | } |
2245 | ||
c6fb90c8 | 2246 | static INLINE int |
40fb9820 L |
2247 | operand_type_match (i386_operand_type overlap, |
2248 | i386_operand_type given) | |
2249 | { | |
2250 | i386_operand_type temp = overlap; | |
2251 | ||
7d5e4556 | 2252 | temp.bitfield.unspecified = 0; |
5c07affc L |
2253 | temp.bitfield.byte = 0; |
2254 | temp.bitfield.word = 0; | |
2255 | temp.bitfield.dword = 0; | |
2256 | temp.bitfield.fword = 0; | |
2257 | temp.bitfield.qword = 0; | |
2258 | temp.bitfield.tbyte = 0; | |
2259 | temp.bitfield.xmmword = 0; | |
c0f3af97 | 2260 | temp.bitfield.ymmword = 0; |
43234a1e | 2261 | temp.bitfield.zmmword = 0; |
0dfbf9d7 | 2262 | if (operand_type_all_zero (&temp)) |
891edac4 | 2263 | goto mismatch; |
40fb9820 | 2264 | |
6f2f06be | 2265 | if (given.bitfield.baseindex == overlap.bitfield.baseindex) |
891edac4 L |
2266 | return 1; |
2267 | ||
dc1e8a47 | 2268 | mismatch: |
a65babc9 | 2269 | i.error = operand_type_mismatch; |
891edac4 | 2270 | return 0; |
40fb9820 L |
2271 | } |
2272 | ||
7d5e4556 | 2273 | /* If given types g0 and g1 are registers they must be of the same type |
10c17abd | 2274 | unless the expected operand type register overlap is null. |
5de4d9ef | 2275 | Some Intel syntax memory operand size checking also happens here. */ |
40fb9820 | 2276 | |
c6fb90c8 | 2277 | static INLINE int |
dc821c5f | 2278 | operand_type_register_match (i386_operand_type g0, |
40fb9820 | 2279 | i386_operand_type t0, |
40fb9820 L |
2280 | i386_operand_type g1, |
2281 | i386_operand_type t1) | |
2282 | { | |
bab6aec1 | 2283 | if (g0.bitfield.class != Reg |
3528c362 | 2284 | && g0.bitfield.class != RegSIMD |
10c17abd JB |
2285 | && (!operand_type_check (g0, anymem) |
2286 | || g0.bitfield.unspecified | |
5de4d9ef JB |
2287 | || (t0.bitfield.class != Reg |
2288 | && t0.bitfield.class != RegSIMD))) | |
40fb9820 L |
2289 | return 1; |
2290 | ||
bab6aec1 | 2291 | if (g1.bitfield.class != Reg |
3528c362 | 2292 | && g1.bitfield.class != RegSIMD |
10c17abd JB |
2293 | && (!operand_type_check (g1, anymem) |
2294 | || g1.bitfield.unspecified | |
5de4d9ef JB |
2295 | || (t1.bitfield.class != Reg |
2296 | && t1.bitfield.class != RegSIMD))) | |
40fb9820 L |
2297 | return 1; |
2298 | ||
dc821c5f JB |
2299 | if (g0.bitfield.byte == g1.bitfield.byte |
2300 | && g0.bitfield.word == g1.bitfield.word | |
2301 | && g0.bitfield.dword == g1.bitfield.dword | |
10c17abd JB |
2302 | && g0.bitfield.qword == g1.bitfield.qword |
2303 | && g0.bitfield.xmmword == g1.bitfield.xmmword | |
2304 | && g0.bitfield.ymmword == g1.bitfield.ymmword | |
2305 | && g0.bitfield.zmmword == g1.bitfield.zmmword) | |
40fb9820 L |
2306 | return 1; |
2307 | ||
dc821c5f JB |
2308 | if (!(t0.bitfield.byte & t1.bitfield.byte) |
2309 | && !(t0.bitfield.word & t1.bitfield.word) | |
2310 | && !(t0.bitfield.dword & t1.bitfield.dword) | |
10c17abd JB |
2311 | && !(t0.bitfield.qword & t1.bitfield.qword) |
2312 | && !(t0.bitfield.xmmword & t1.bitfield.xmmword) | |
2313 | && !(t0.bitfield.ymmword & t1.bitfield.ymmword) | |
2314 | && !(t0.bitfield.zmmword & t1.bitfield.zmmword)) | |
891edac4 L |
2315 | return 1; |
2316 | ||
a65babc9 | 2317 | i.error = register_type_mismatch; |
891edac4 L |
2318 | |
2319 | return 0; | |
40fb9820 L |
2320 | } |
2321 | ||
4c692bc7 JB |
2322 | static INLINE unsigned int |
2323 | register_number (const reg_entry *r) | |
2324 | { | |
2325 | unsigned int nr = r->reg_num; | |
2326 | ||
2327 | if (r->reg_flags & RegRex) | |
2328 | nr += 8; | |
2329 | ||
200cbe0f L |
2330 | if (r->reg_flags & RegVRex) |
2331 | nr += 16; | |
2332 | ||
4c692bc7 JB |
2333 | return nr; |
2334 | } | |
2335 | ||
252b5132 | 2336 | static INLINE unsigned int |
40fb9820 | 2337 | mode_from_disp_size (i386_operand_type t) |
252b5132 | 2338 | { |
b5014f7a | 2339 | if (t.bitfield.disp8) |
40fb9820 L |
2340 | return 1; |
2341 | else if (t.bitfield.disp16 | |
2342 | || t.bitfield.disp32 | |
2343 | || t.bitfield.disp32s) | |
2344 | return 2; | |
2345 | else | |
2346 | return 0; | |
252b5132 RH |
2347 | } |
2348 | ||
2349 | static INLINE int | |
65879393 | 2350 | fits_in_signed_byte (addressT num) |
252b5132 | 2351 | { |
65879393 | 2352 | return num + 0x80 <= 0xff; |
47926f60 | 2353 | } |
252b5132 RH |
2354 | |
2355 | static INLINE int | |
65879393 | 2356 | fits_in_unsigned_byte (addressT num) |
252b5132 | 2357 | { |
65879393 | 2358 | return num <= 0xff; |
47926f60 | 2359 | } |
252b5132 RH |
2360 | |
2361 | static INLINE int | |
65879393 | 2362 | fits_in_unsigned_word (addressT num) |
252b5132 | 2363 | { |
65879393 | 2364 | return num <= 0xffff; |
47926f60 | 2365 | } |
252b5132 RH |
2366 | |
2367 | static INLINE int | |
65879393 | 2368 | fits_in_signed_word (addressT num) |
252b5132 | 2369 | { |
65879393 | 2370 | return num + 0x8000 <= 0xffff; |
47926f60 | 2371 | } |
2a962e6d | 2372 | |
3e73aa7c | 2373 | static INLINE int |
65879393 | 2374 | fits_in_signed_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2375 | { |
2376 | #ifndef BFD64 | |
2377 | return 1; | |
2378 | #else | |
65879393 | 2379 | return num + 0x80000000 <= 0xffffffff; |
3e73aa7c JH |
2380 | #endif |
2381 | } /* fits_in_signed_long() */ | |
2a962e6d | 2382 | |
3e73aa7c | 2383 | static INLINE int |
65879393 | 2384 | fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2385 | { |
2386 | #ifndef BFD64 | |
2387 | return 1; | |
2388 | #else | |
65879393 | 2389 | return num <= 0xffffffff; |
3e73aa7c JH |
2390 | #endif |
2391 | } /* fits_in_unsigned_long() */ | |
252b5132 | 2392 | |
43234a1e | 2393 | static INLINE int |
b5014f7a | 2394 | fits_in_disp8 (offsetT num) |
43234a1e L |
2395 | { |
2396 | int shift = i.memshift; | |
2397 | unsigned int mask; | |
2398 | ||
2399 | if (shift == -1) | |
2400 | abort (); | |
2401 | ||
2402 | mask = (1 << shift) - 1; | |
2403 | ||
2404 | /* Return 0 if NUM isn't properly aligned. */ | |
2405 | if ((num & mask)) | |
2406 | return 0; | |
2407 | ||
2408 | /* Check if NUM will fit in 8bit after shift. */ | |
2409 | return fits_in_signed_byte (num >> shift); | |
2410 | } | |
2411 | ||
a683cc34 SP |
2412 | static INLINE int |
2413 | fits_in_imm4 (offsetT num) | |
2414 | { | |
2415 | return (num & 0xf) == num; | |
2416 | } | |
2417 | ||
40fb9820 | 2418 | static i386_operand_type |
e3bb37b5 | 2419 | smallest_imm_type (offsetT num) |
252b5132 | 2420 | { |
40fb9820 | 2421 | i386_operand_type t; |
7ab9ffdd | 2422 | |
0dfbf9d7 | 2423 | operand_type_set (&t, 0); |
40fb9820 L |
2424 | t.bitfield.imm64 = 1; |
2425 | ||
2426 | if (cpu_arch_tune != PROCESSOR_I486 && num == 1) | |
e413e4e9 AM |
2427 | { |
2428 | /* This code is disabled on the 486 because all the Imm1 forms | |
2429 | in the opcode table are slower on the i486. They're the | |
2430 | versions with the implicitly specified single-position | |
2431 | displacement, which has another syntax if you really want to | |
2432 | use that form. */ | |
40fb9820 L |
2433 | t.bitfield.imm1 = 1; |
2434 | t.bitfield.imm8 = 1; | |
2435 | t.bitfield.imm8s = 1; | |
2436 | t.bitfield.imm16 = 1; | |
2437 | t.bitfield.imm32 = 1; | |
2438 | t.bitfield.imm32s = 1; | |
2439 | } | |
2440 | else if (fits_in_signed_byte (num)) | |
2441 | { | |
2442 | t.bitfield.imm8 = 1; | |
2443 | t.bitfield.imm8s = 1; | |
2444 | t.bitfield.imm16 = 1; | |
2445 | t.bitfield.imm32 = 1; | |
2446 | t.bitfield.imm32s = 1; | |
2447 | } | |
2448 | else if (fits_in_unsigned_byte (num)) | |
2449 | { | |
2450 | t.bitfield.imm8 = 1; | |
2451 | t.bitfield.imm16 = 1; | |
2452 | t.bitfield.imm32 = 1; | |
2453 | t.bitfield.imm32s = 1; | |
2454 | } | |
2455 | else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
2456 | { | |
2457 | t.bitfield.imm16 = 1; | |
2458 | t.bitfield.imm32 = 1; | |
2459 | t.bitfield.imm32s = 1; | |
2460 | } | |
2461 | else if (fits_in_signed_long (num)) | |
2462 | { | |
2463 | t.bitfield.imm32 = 1; | |
2464 | t.bitfield.imm32s = 1; | |
2465 | } | |
2466 | else if (fits_in_unsigned_long (num)) | |
2467 | t.bitfield.imm32 = 1; | |
2468 | ||
2469 | return t; | |
47926f60 | 2470 | } |
252b5132 | 2471 | |
847f7ad4 | 2472 | static offsetT |
e3bb37b5 | 2473 | offset_in_range (offsetT val, int size) |
847f7ad4 | 2474 | { |
508866be | 2475 | addressT mask; |
ba2adb93 | 2476 | |
847f7ad4 AM |
2477 | switch (size) |
2478 | { | |
508866be L |
2479 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
2480 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 2481 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
3e73aa7c JH |
2482 | #ifdef BFD64 |
2483 | case 8: mask = ((addressT) 2 << 63) - 1; break; | |
2484 | #endif | |
47926f60 | 2485 | default: abort (); |
847f7ad4 AM |
2486 | } |
2487 | ||
9de868bf L |
2488 | #ifdef BFD64 |
2489 | /* If BFD64, sign extend val for 32bit address mode. */ | |
2490 | if (flag_code != CODE_64BIT | |
2491 | || i.prefix[ADDR_PREFIX]) | |
3e73aa7c JH |
2492 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) |
2493 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
fa289fb8 | 2494 | #endif |
ba2adb93 | 2495 | |
47926f60 | 2496 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
847f7ad4 AM |
2497 | { |
2498 | char buf1[40], buf2[40]; | |
2499 | ||
2500 | sprint_value (buf1, val); | |
2501 | sprint_value (buf2, val & mask); | |
2502 | as_warn (_("%s shortened to %s"), buf1, buf2); | |
2503 | } | |
2504 | return val & mask; | |
2505 | } | |
2506 | ||
c32fa91d L |
2507 | enum PREFIX_GROUP |
2508 | { | |
2509 | PREFIX_EXIST = 0, | |
2510 | PREFIX_LOCK, | |
2511 | PREFIX_REP, | |
04ef582a | 2512 | PREFIX_DS, |
c32fa91d L |
2513 | PREFIX_OTHER |
2514 | }; | |
2515 | ||
2516 | /* Returns | |
2517 | a. PREFIX_EXIST if attempting to add a prefix where one from the | |
2518 | same class already exists. | |
2519 | b. PREFIX_LOCK if lock prefix is added. | |
2520 | c. PREFIX_REP if rep/repne prefix is added. | |
04ef582a L |
2521 | d. PREFIX_DS if ds prefix is added. |
2522 | e. PREFIX_OTHER if other prefix is added. | |
c32fa91d L |
2523 | */ |
2524 | ||
2525 | static enum PREFIX_GROUP | |
e3bb37b5 | 2526 | add_prefix (unsigned int prefix) |
252b5132 | 2527 | { |
c32fa91d | 2528 | enum PREFIX_GROUP ret = PREFIX_OTHER; |
b1905489 | 2529 | unsigned int q; |
252b5132 | 2530 | |
29b0f896 AM |
2531 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
2532 | && flag_code == CODE_64BIT) | |
b1905489 | 2533 | { |
161a04f6 | 2534 | if ((i.prefix[REX_PREFIX] & prefix & REX_W) |
44846f29 JB |
2535 | || (i.prefix[REX_PREFIX] & prefix & REX_R) |
2536 | || (i.prefix[REX_PREFIX] & prefix & REX_X) | |
2537 | || (i.prefix[REX_PREFIX] & prefix & REX_B)) | |
c32fa91d | 2538 | ret = PREFIX_EXIST; |
b1905489 JB |
2539 | q = REX_PREFIX; |
2540 | } | |
3e73aa7c | 2541 | else |
b1905489 JB |
2542 | { |
2543 | switch (prefix) | |
2544 | { | |
2545 | default: | |
2546 | abort (); | |
2547 | ||
b1905489 | 2548 | case DS_PREFIX_OPCODE: |
04ef582a L |
2549 | ret = PREFIX_DS; |
2550 | /* Fall through. */ | |
2551 | case CS_PREFIX_OPCODE: | |
b1905489 JB |
2552 | case ES_PREFIX_OPCODE: |
2553 | case FS_PREFIX_OPCODE: | |
2554 | case GS_PREFIX_OPCODE: | |
2555 | case SS_PREFIX_OPCODE: | |
2556 | q = SEG_PREFIX; | |
2557 | break; | |
2558 | ||
2559 | case REPNE_PREFIX_OPCODE: | |
2560 | case REPE_PREFIX_OPCODE: | |
c32fa91d L |
2561 | q = REP_PREFIX; |
2562 | ret = PREFIX_REP; | |
2563 | break; | |
2564 | ||
b1905489 | 2565 | case LOCK_PREFIX_OPCODE: |
c32fa91d L |
2566 | q = LOCK_PREFIX; |
2567 | ret = PREFIX_LOCK; | |
b1905489 JB |
2568 | break; |
2569 | ||
2570 | case FWAIT_OPCODE: | |
2571 | q = WAIT_PREFIX; | |
2572 | break; | |
2573 | ||
2574 | case ADDR_PREFIX_OPCODE: | |
2575 | q = ADDR_PREFIX; | |
2576 | break; | |
2577 | ||
2578 | case DATA_PREFIX_OPCODE: | |
2579 | q = DATA_PREFIX; | |
2580 | break; | |
2581 | } | |
2582 | if (i.prefix[q] != 0) | |
c32fa91d | 2583 | ret = PREFIX_EXIST; |
b1905489 | 2584 | } |
252b5132 | 2585 | |
b1905489 | 2586 | if (ret) |
252b5132 | 2587 | { |
b1905489 JB |
2588 | if (!i.prefix[q]) |
2589 | ++i.prefixes; | |
2590 | i.prefix[q] |= prefix; | |
252b5132 | 2591 | } |
b1905489 JB |
2592 | else |
2593 | as_bad (_("same type of prefix used twice")); | |
252b5132 | 2594 | |
252b5132 RH |
2595 | return ret; |
2596 | } | |
2597 | ||
2598 | static void | |
78f12dd3 | 2599 | update_code_flag (int value, int check) |
eecb386c | 2600 | { |
78f12dd3 L |
2601 | PRINTF_LIKE ((*as_error)); |
2602 | ||
1e9cc1c2 | 2603 | flag_code = (enum flag_code) value; |
40fb9820 L |
2604 | if (flag_code == CODE_64BIT) |
2605 | { | |
2606 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2607 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
40fb9820 L |
2608 | } |
2609 | else | |
2610 | { | |
2611 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2612 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
40fb9820 L |
2613 | } |
2614 | if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm ) | |
3e73aa7c | 2615 | { |
78f12dd3 L |
2616 | if (check) |
2617 | as_error = as_fatal; | |
2618 | else | |
2619 | as_error = as_bad; | |
2620 | (*as_error) (_("64bit mode not supported on `%s'."), | |
2621 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2622 | } |
40fb9820 | 2623 | if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) |
3e73aa7c | 2624 | { |
78f12dd3 L |
2625 | if (check) |
2626 | as_error = as_fatal; | |
2627 | else | |
2628 | as_error = as_bad; | |
2629 | (*as_error) (_("32bit mode not supported on `%s'."), | |
2630 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2631 | } |
eecb386c AM |
2632 | stackop_size = '\0'; |
2633 | } | |
2634 | ||
78f12dd3 L |
2635 | static void |
2636 | set_code_flag (int value) | |
2637 | { | |
2638 | update_code_flag (value, 0); | |
2639 | } | |
2640 | ||
eecb386c | 2641 | static void |
e3bb37b5 | 2642 | set_16bit_gcc_code_flag (int new_code_flag) |
252b5132 | 2643 | { |
1e9cc1c2 | 2644 | flag_code = (enum flag_code) new_code_flag; |
40fb9820 L |
2645 | if (flag_code != CODE_16BIT) |
2646 | abort (); | |
2647 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2648 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
9306ca4a | 2649 | stackop_size = LONG_MNEM_SUFFIX; |
252b5132 RH |
2650 | } |
2651 | ||
2652 | static void | |
e3bb37b5 | 2653 | set_intel_syntax (int syntax_flag) |
252b5132 RH |
2654 | { |
2655 | /* Find out if register prefixing is specified. */ | |
2656 | int ask_naked_reg = 0; | |
2657 | ||
2658 | SKIP_WHITESPACE (); | |
29b0f896 | 2659 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
252b5132 | 2660 | { |
d02603dc NC |
2661 | char *string; |
2662 | int e = get_symbol_name (&string); | |
252b5132 | 2663 | |
47926f60 | 2664 | if (strcmp (string, "prefix") == 0) |
252b5132 | 2665 | ask_naked_reg = 1; |
47926f60 | 2666 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
2667 | ask_naked_reg = -1; |
2668 | else | |
d0b47220 | 2669 | as_bad (_("bad argument to syntax directive.")); |
d02603dc | 2670 | (void) restore_line_pointer (e); |
252b5132 RH |
2671 | } |
2672 | demand_empty_rest_of_line (); | |
c3332e24 | 2673 | |
252b5132 RH |
2674 | intel_syntax = syntax_flag; |
2675 | ||
2676 | if (ask_naked_reg == 0) | |
f86103b7 AM |
2677 | allow_naked_reg = (intel_syntax |
2678 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); | |
252b5132 RH |
2679 | else |
2680 | allow_naked_reg = (ask_naked_reg < 0); | |
9306ca4a | 2681 | |
ee86248c | 2682 | expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0); |
7ab9ffdd | 2683 | |
e4a3b5a4 | 2684 | identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; |
9306ca4a | 2685 | identifier_chars['$'] = intel_syntax ? '$' : 0; |
e4a3b5a4 | 2686 | register_prefix = allow_naked_reg ? "" : "%"; |
252b5132 RH |
2687 | } |
2688 | ||
1efbbeb4 L |
2689 | static void |
2690 | set_intel_mnemonic (int mnemonic_flag) | |
2691 | { | |
e1d4d893 | 2692 | intel_mnemonic = mnemonic_flag; |
1efbbeb4 L |
2693 | } |
2694 | ||
db51cc60 L |
2695 | static void |
2696 | set_allow_index_reg (int flag) | |
2697 | { | |
2698 | allow_index_reg = flag; | |
2699 | } | |
2700 | ||
cb19c032 | 2701 | static void |
7bab8ab5 | 2702 | set_check (int what) |
cb19c032 | 2703 | { |
7bab8ab5 JB |
2704 | enum check_kind *kind; |
2705 | const char *str; | |
2706 | ||
2707 | if (what) | |
2708 | { | |
2709 | kind = &operand_check; | |
2710 | str = "operand"; | |
2711 | } | |
2712 | else | |
2713 | { | |
2714 | kind = &sse_check; | |
2715 | str = "sse"; | |
2716 | } | |
2717 | ||
cb19c032 L |
2718 | SKIP_WHITESPACE (); |
2719 | ||
2720 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
2721 | { | |
d02603dc NC |
2722 | char *string; |
2723 | int e = get_symbol_name (&string); | |
cb19c032 L |
2724 | |
2725 | if (strcmp (string, "none") == 0) | |
7bab8ab5 | 2726 | *kind = check_none; |
cb19c032 | 2727 | else if (strcmp (string, "warning") == 0) |
7bab8ab5 | 2728 | *kind = check_warning; |
cb19c032 | 2729 | else if (strcmp (string, "error") == 0) |
7bab8ab5 | 2730 | *kind = check_error; |
cb19c032 | 2731 | else |
7bab8ab5 | 2732 | as_bad (_("bad argument to %s_check directive."), str); |
d02603dc | 2733 | (void) restore_line_pointer (e); |
cb19c032 L |
2734 | } |
2735 | else | |
7bab8ab5 | 2736 | as_bad (_("missing argument for %s_check directive"), str); |
cb19c032 L |
2737 | |
2738 | demand_empty_rest_of_line (); | |
2739 | } | |
2740 | ||
8a9036a4 L |
2741 | static void |
2742 | check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED, | |
1e9cc1c2 | 2743 | i386_cpu_flags new_flag ATTRIBUTE_UNUSED) |
8a9036a4 L |
2744 | { |
2745 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2746 | static const char *arch; | |
2747 | ||
2748 | /* Intel LIOM is only supported on ELF. */ | |
2749 | if (!IS_ELF) | |
2750 | return; | |
2751 | ||
2752 | if (!arch) | |
2753 | { | |
2754 | /* Use cpu_arch_name if it is set in md_parse_option. Otherwise | |
2755 | use default_arch. */ | |
2756 | arch = cpu_arch_name; | |
2757 | if (!arch) | |
2758 | arch = default_arch; | |
2759 | } | |
2760 | ||
81486035 L |
2761 | /* If we are targeting Intel MCU, we must enable it. */ |
2762 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU | |
2763 | || new_flag.bitfield.cpuiamcu) | |
2764 | return; | |
2765 | ||
3632d14b | 2766 | /* If we are targeting Intel L1OM, we must enable it. */ |
8a9036a4 | 2767 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM |
1e9cc1c2 | 2768 | || new_flag.bitfield.cpul1om) |
8a9036a4 | 2769 | return; |
76ba9986 | 2770 | |
7a9068fe L |
2771 | /* If we are targeting Intel K1OM, we must enable it. */ |
2772 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM | |
2773 | || new_flag.bitfield.cpuk1om) | |
2774 | return; | |
2775 | ||
8a9036a4 L |
2776 | as_bad (_("`%s' is not supported on `%s'"), name, arch); |
2777 | #endif | |
2778 | } | |
2779 | ||
e413e4e9 | 2780 | static void |
e3bb37b5 | 2781 | set_cpu_arch (int dummy ATTRIBUTE_UNUSED) |
e413e4e9 | 2782 | { |
47926f60 | 2783 | SKIP_WHITESPACE (); |
e413e4e9 | 2784 | |
29b0f896 | 2785 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
e413e4e9 | 2786 | { |
d02603dc NC |
2787 | char *string; |
2788 | int e = get_symbol_name (&string); | |
91d6fa6a | 2789 | unsigned int j; |
40fb9820 | 2790 | i386_cpu_flags flags; |
e413e4e9 | 2791 | |
91d6fa6a | 2792 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
e413e4e9 | 2793 | { |
91d6fa6a | 2794 | if (strcmp (string, cpu_arch[j].name) == 0) |
e413e4e9 | 2795 | { |
91d6fa6a | 2796 | check_cpu_arch_compatible (string, cpu_arch[j].flags); |
8a9036a4 | 2797 | |
5c6af06e JB |
2798 | if (*string != '.') |
2799 | { | |
91d6fa6a | 2800 | cpu_arch_name = cpu_arch[j].name; |
5c6af06e | 2801 | cpu_sub_arch_name = NULL; |
91d6fa6a | 2802 | cpu_arch_flags = cpu_arch[j].flags; |
40fb9820 L |
2803 | if (flag_code == CODE_64BIT) |
2804 | { | |
2805 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2806 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
2807 | } | |
2808 | else | |
2809 | { | |
2810 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2811 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
2812 | } | |
91d6fa6a NC |
2813 | cpu_arch_isa = cpu_arch[j].type; |
2814 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
ccc9c027 L |
2815 | if (!cpu_arch_tune_set) |
2816 | { | |
2817 | cpu_arch_tune = cpu_arch_isa; | |
2818 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
2819 | } | |
5c6af06e JB |
2820 | break; |
2821 | } | |
40fb9820 | 2822 | |
293f5f65 L |
2823 | flags = cpu_flags_or (cpu_arch_flags, |
2824 | cpu_arch[j].flags); | |
81486035 | 2825 | |
5b64d091 | 2826 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
5c6af06e | 2827 | { |
6305a203 L |
2828 | if (cpu_sub_arch_name) |
2829 | { | |
2830 | char *name = cpu_sub_arch_name; | |
2831 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 2832 | cpu_arch[j].name, |
1bf57e9f | 2833 | (const char *) NULL); |
6305a203 L |
2834 | free (name); |
2835 | } | |
2836 | else | |
91d6fa6a | 2837 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
40fb9820 | 2838 | cpu_arch_flags = flags; |
a586129e | 2839 | cpu_arch_isa_flags = flags; |
5c6af06e | 2840 | } |
0089dace L |
2841 | else |
2842 | cpu_arch_isa_flags | |
2843 | = cpu_flags_or (cpu_arch_isa_flags, | |
2844 | cpu_arch[j].flags); | |
d02603dc | 2845 | (void) restore_line_pointer (e); |
5c6af06e JB |
2846 | demand_empty_rest_of_line (); |
2847 | return; | |
e413e4e9 AM |
2848 | } |
2849 | } | |
293f5f65 L |
2850 | |
2851 | if (*string == '.' && j >= ARRAY_SIZE (cpu_arch)) | |
2852 | { | |
33eaf5de | 2853 | /* Disable an ISA extension. */ |
293f5f65 L |
2854 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
2855 | if (strcmp (string + 1, cpu_noarch [j].name) == 0) | |
2856 | { | |
2857 | flags = cpu_flags_and_not (cpu_arch_flags, | |
2858 | cpu_noarch[j].flags); | |
2859 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
2860 | { | |
2861 | if (cpu_sub_arch_name) | |
2862 | { | |
2863 | char *name = cpu_sub_arch_name; | |
2864 | cpu_sub_arch_name = concat (name, string, | |
2865 | (const char *) NULL); | |
2866 | free (name); | |
2867 | } | |
2868 | else | |
2869 | cpu_sub_arch_name = xstrdup (string); | |
2870 | cpu_arch_flags = flags; | |
2871 | cpu_arch_isa_flags = flags; | |
2872 | } | |
2873 | (void) restore_line_pointer (e); | |
2874 | demand_empty_rest_of_line (); | |
2875 | return; | |
2876 | } | |
2877 | ||
2878 | j = ARRAY_SIZE (cpu_arch); | |
2879 | } | |
2880 | ||
91d6fa6a | 2881 | if (j >= ARRAY_SIZE (cpu_arch)) |
e413e4e9 AM |
2882 | as_bad (_("no such architecture: `%s'"), string); |
2883 | ||
2884 | *input_line_pointer = e; | |
2885 | } | |
2886 | else | |
2887 | as_bad (_("missing cpu architecture")); | |
2888 | ||
fddf5b5b AM |
2889 | no_cond_jump_promotion = 0; |
2890 | if (*input_line_pointer == ',' | |
29b0f896 | 2891 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
fddf5b5b | 2892 | { |
d02603dc NC |
2893 | char *string; |
2894 | char e; | |
2895 | ||
2896 | ++input_line_pointer; | |
2897 | e = get_symbol_name (&string); | |
fddf5b5b AM |
2898 | |
2899 | if (strcmp (string, "nojumps") == 0) | |
2900 | no_cond_jump_promotion = 1; | |
2901 | else if (strcmp (string, "jumps") == 0) | |
2902 | ; | |
2903 | else | |
2904 | as_bad (_("no such architecture modifier: `%s'"), string); | |
2905 | ||
d02603dc | 2906 | (void) restore_line_pointer (e); |
fddf5b5b AM |
2907 | } |
2908 | ||
e413e4e9 AM |
2909 | demand_empty_rest_of_line (); |
2910 | } | |
2911 | ||
8a9036a4 L |
2912 | enum bfd_architecture |
2913 | i386_arch (void) | |
2914 | { | |
3632d14b | 2915 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 L |
2916 | { |
2917 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2918 | || flag_code != CODE_64BIT) | |
2919 | as_fatal (_("Intel L1OM is 64bit ELF only")); | |
2920 | return bfd_arch_l1om; | |
2921 | } | |
7a9068fe L |
2922 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2923 | { | |
2924 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2925 | || flag_code != CODE_64BIT) | |
2926 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2927 | return bfd_arch_k1om; | |
2928 | } | |
81486035 L |
2929 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
2930 | { | |
2931 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2932 | || flag_code == CODE_64BIT) | |
2933 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2934 | return bfd_arch_iamcu; | |
2935 | } | |
8a9036a4 L |
2936 | else |
2937 | return bfd_arch_i386; | |
2938 | } | |
2939 | ||
b9d79e03 | 2940 | unsigned long |
7016a5d5 | 2941 | i386_mach (void) |
b9d79e03 | 2942 | { |
351f65ca | 2943 | if (!strncmp (default_arch, "x86_64", 6)) |
8a9036a4 | 2944 | { |
3632d14b | 2945 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 2946 | { |
351f65ca L |
2947 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour |
2948 | || default_arch[6] != '\0') | |
8a9036a4 L |
2949 | as_fatal (_("Intel L1OM is 64bit ELF only")); |
2950 | return bfd_mach_l1om; | |
2951 | } | |
7a9068fe L |
2952 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2953 | { | |
2954 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2955 | || default_arch[6] != '\0') | |
2956 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2957 | return bfd_mach_k1om; | |
2958 | } | |
351f65ca | 2959 | else if (default_arch[6] == '\0') |
8a9036a4 | 2960 | return bfd_mach_x86_64; |
351f65ca L |
2961 | else |
2962 | return bfd_mach_x64_32; | |
8a9036a4 | 2963 | } |
5197d474 L |
2964 | else if (!strcmp (default_arch, "i386") |
2965 | || !strcmp (default_arch, "iamcu")) | |
81486035 L |
2966 | { |
2967 | if (cpu_arch_isa == PROCESSOR_IAMCU) | |
2968 | { | |
2969 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
2970 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2971 | return bfd_mach_i386_iamcu; | |
2972 | } | |
2973 | else | |
2974 | return bfd_mach_i386_i386; | |
2975 | } | |
b9d79e03 | 2976 | else |
2b5d6a91 | 2977 | as_fatal (_("unknown architecture")); |
b9d79e03 | 2978 | } |
b9d79e03 | 2979 | \f |
252b5132 | 2980 | void |
7016a5d5 | 2981 | md_begin (void) |
252b5132 RH |
2982 | { |
2983 | const char *hash_err; | |
2984 | ||
86fa6981 L |
2985 | /* Support pseudo prefixes like {disp32}. */ |
2986 | lex_type ['{'] = LEX_BEGIN_NAME; | |
2987 | ||
47926f60 | 2988 | /* Initialize op_hash hash table. */ |
252b5132 RH |
2989 | op_hash = hash_new (); |
2990 | ||
2991 | { | |
d3ce72d0 | 2992 | const insn_template *optab; |
29b0f896 | 2993 | templates *core_optab; |
252b5132 | 2994 | |
47926f60 KH |
2995 | /* Setup for loop. */ |
2996 | optab = i386_optab; | |
add39d23 | 2997 | core_optab = XNEW (templates); |
252b5132 RH |
2998 | core_optab->start = optab; |
2999 | ||
3000 | while (1) | |
3001 | { | |
3002 | ++optab; | |
3003 | if (optab->name == NULL | |
3004 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
3005 | { | |
3006 | /* different name --> ship out current template list; | |
47926f60 | 3007 | add to hash table; & begin anew. */ |
252b5132 RH |
3008 | core_optab->end = optab; |
3009 | hash_err = hash_insert (op_hash, | |
3010 | (optab - 1)->name, | |
5a49b8ac | 3011 | (void *) core_optab); |
252b5132 RH |
3012 | if (hash_err) |
3013 | { | |
b37df7c4 | 3014 | as_fatal (_("can't hash %s: %s"), |
252b5132 RH |
3015 | (optab - 1)->name, |
3016 | hash_err); | |
3017 | } | |
3018 | if (optab->name == NULL) | |
3019 | break; | |
add39d23 | 3020 | core_optab = XNEW (templates); |
252b5132 RH |
3021 | core_optab->start = optab; |
3022 | } | |
3023 | } | |
3024 | } | |
3025 | ||
47926f60 | 3026 | /* Initialize reg_hash hash table. */ |
252b5132 RH |
3027 | reg_hash = hash_new (); |
3028 | { | |
29b0f896 | 3029 | const reg_entry *regtab; |
c3fe08fa | 3030 | unsigned int regtab_size = i386_regtab_size; |
252b5132 | 3031 | |
c3fe08fa | 3032 | for (regtab = i386_regtab; regtab_size--; regtab++) |
252b5132 | 3033 | { |
5a49b8ac | 3034 | hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab); |
252b5132 | 3035 | if (hash_err) |
b37df7c4 | 3036 | as_fatal (_("can't hash %s: %s"), |
3e73aa7c JH |
3037 | regtab->reg_name, |
3038 | hash_err); | |
252b5132 RH |
3039 | } |
3040 | } | |
3041 | ||
47926f60 | 3042 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 | 3043 | { |
29b0f896 AM |
3044 | int c; |
3045 | char *p; | |
252b5132 RH |
3046 | |
3047 | for (c = 0; c < 256; c++) | |
3048 | { | |
3882b010 | 3049 | if (ISDIGIT (c)) |
252b5132 RH |
3050 | { |
3051 | digit_chars[c] = c; | |
3052 | mnemonic_chars[c] = c; | |
3053 | register_chars[c] = c; | |
3054 | operand_chars[c] = c; | |
3055 | } | |
3882b010 | 3056 | else if (ISLOWER (c)) |
252b5132 RH |
3057 | { |
3058 | mnemonic_chars[c] = c; | |
3059 | register_chars[c] = c; | |
3060 | operand_chars[c] = c; | |
3061 | } | |
3882b010 | 3062 | else if (ISUPPER (c)) |
252b5132 | 3063 | { |
3882b010 | 3064 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
3065 | register_chars[c] = mnemonic_chars[c]; |
3066 | operand_chars[c] = c; | |
3067 | } | |
43234a1e | 3068 | else if (c == '{' || c == '}') |
86fa6981 L |
3069 | { |
3070 | mnemonic_chars[c] = c; | |
3071 | operand_chars[c] = c; | |
3072 | } | |
252b5132 | 3073 | |
3882b010 | 3074 | if (ISALPHA (c) || ISDIGIT (c)) |
252b5132 RH |
3075 | identifier_chars[c] = c; |
3076 | else if (c >= 128) | |
3077 | { | |
3078 | identifier_chars[c] = c; | |
3079 | operand_chars[c] = c; | |
3080 | } | |
3081 | } | |
3082 | ||
3083 | #ifdef LEX_AT | |
3084 | identifier_chars['@'] = '@'; | |
32137342 NC |
3085 | #endif |
3086 | #ifdef LEX_QM | |
3087 | identifier_chars['?'] = '?'; | |
3088 | operand_chars['?'] = '?'; | |
252b5132 | 3089 | #endif |
252b5132 | 3090 | digit_chars['-'] = '-'; |
c0f3af97 | 3091 | mnemonic_chars['_'] = '_'; |
791fe849 | 3092 | mnemonic_chars['-'] = '-'; |
0003779b | 3093 | mnemonic_chars['.'] = '.'; |
252b5132 RH |
3094 | identifier_chars['_'] = '_'; |
3095 | identifier_chars['.'] = '.'; | |
3096 | ||
3097 | for (p = operand_special_chars; *p != '\0'; p++) | |
3098 | operand_chars[(unsigned char) *p] = *p; | |
3099 | } | |
3100 | ||
a4447b93 RH |
3101 | if (flag_code == CODE_64BIT) |
3102 | { | |
ca19b261 KT |
3103 | #if defined (OBJ_COFF) && defined (TE_PE) |
3104 | x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour | |
3105 | ? 32 : 16); | |
3106 | #else | |
a4447b93 | 3107 | x86_dwarf2_return_column = 16; |
ca19b261 | 3108 | #endif |
61ff971f | 3109 | x86_cie_data_alignment = -8; |
a4447b93 RH |
3110 | } |
3111 | else | |
3112 | { | |
3113 | x86_dwarf2_return_column = 8; | |
3114 | x86_cie_data_alignment = -4; | |
3115 | } | |
e379e5f3 L |
3116 | |
3117 | /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it | |
3118 | can be turned into BRANCH_PREFIX frag. */ | |
3119 | if (align_branch_prefix_size > MAX_FUSED_JCC_PADDING_SIZE) | |
3120 | abort (); | |
252b5132 RH |
3121 | } |
3122 | ||
3123 | void | |
e3bb37b5 | 3124 | i386_print_statistics (FILE *file) |
252b5132 RH |
3125 | { |
3126 | hash_print_statistics (file, "i386 opcode", op_hash); | |
3127 | hash_print_statistics (file, "i386 register", reg_hash); | |
3128 | } | |
3129 | \f | |
252b5132 RH |
3130 | #ifdef DEBUG386 |
3131 | ||
ce8a8b2f | 3132 | /* Debugging routines for md_assemble. */ |
d3ce72d0 | 3133 | static void pte (insn_template *); |
40fb9820 | 3134 | static void pt (i386_operand_type); |
e3bb37b5 L |
3135 | static void pe (expressionS *); |
3136 | static void ps (symbolS *); | |
252b5132 RH |
3137 | |
3138 | static void | |
2c703856 | 3139 | pi (const char *line, i386_insn *x) |
252b5132 | 3140 | { |
09137c09 | 3141 | unsigned int j; |
252b5132 RH |
3142 | |
3143 | fprintf (stdout, "%s: template ", line); | |
3144 | pte (&x->tm); | |
09f131f2 JH |
3145 | fprintf (stdout, " address: base %s index %s scale %x\n", |
3146 | x->base_reg ? x->base_reg->reg_name : "none", | |
3147 | x->index_reg ? x->index_reg->reg_name : "none", | |
3148 | x->log2_scale_factor); | |
3149 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 3150 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
3151 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
3152 | x->sib.base, x->sib.index, x->sib.scale); | |
3153 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
161a04f6 L |
3154 | (x->rex & REX_W) != 0, |
3155 | (x->rex & REX_R) != 0, | |
3156 | (x->rex & REX_X) != 0, | |
3157 | (x->rex & REX_B) != 0); | |
09137c09 | 3158 | for (j = 0; j < x->operands; j++) |
252b5132 | 3159 | { |
09137c09 SP |
3160 | fprintf (stdout, " #%d: ", j + 1); |
3161 | pt (x->types[j]); | |
252b5132 | 3162 | fprintf (stdout, "\n"); |
bab6aec1 | 3163 | if (x->types[j].bitfield.class == Reg |
3528c362 JB |
3164 | || x->types[j].bitfield.class == RegMMX |
3165 | || x->types[j].bitfield.class == RegSIMD | |
00cee14f | 3166 | || x->types[j].bitfield.class == SReg |
4a5c67ed JB |
3167 | || x->types[j].bitfield.class == RegCR |
3168 | || x->types[j].bitfield.class == RegDR | |
3169 | || x->types[j].bitfield.class == RegTR) | |
09137c09 SP |
3170 | fprintf (stdout, "%s\n", x->op[j].regs->reg_name); |
3171 | if (operand_type_check (x->types[j], imm)) | |
3172 | pe (x->op[j].imms); | |
3173 | if (operand_type_check (x->types[j], disp)) | |
3174 | pe (x->op[j].disps); | |
252b5132 RH |
3175 | } |
3176 | } | |
3177 | ||
3178 | static void | |
d3ce72d0 | 3179 | pte (insn_template *t) |
252b5132 | 3180 | { |
09137c09 | 3181 | unsigned int j; |
252b5132 | 3182 | fprintf (stdout, " %d operands ", t->operands); |
47926f60 | 3183 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
3184 | if (t->extension_opcode != None) |
3185 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
40fb9820 | 3186 | if (t->opcode_modifier.d) |
252b5132 | 3187 | fprintf (stdout, "D"); |
40fb9820 | 3188 | if (t->opcode_modifier.w) |
252b5132 RH |
3189 | fprintf (stdout, "W"); |
3190 | fprintf (stdout, "\n"); | |
09137c09 | 3191 | for (j = 0; j < t->operands; j++) |
252b5132 | 3192 | { |
09137c09 SP |
3193 | fprintf (stdout, " #%d type ", j + 1); |
3194 | pt (t->operand_types[j]); | |
252b5132 RH |
3195 | fprintf (stdout, "\n"); |
3196 | } | |
3197 | } | |
3198 | ||
3199 | static void | |
e3bb37b5 | 3200 | pe (expressionS *e) |
252b5132 | 3201 | { |
24eab124 | 3202 | fprintf (stdout, " operation %d\n", e->X_op); |
b77ad1d4 AM |
3203 | fprintf (stdout, " add_number %ld (%lx)\n", |
3204 | (long) e->X_add_number, (long) e->X_add_number); | |
252b5132 RH |
3205 | if (e->X_add_symbol) |
3206 | { | |
3207 | fprintf (stdout, " add_symbol "); | |
3208 | ps (e->X_add_symbol); | |
3209 | fprintf (stdout, "\n"); | |
3210 | } | |
3211 | if (e->X_op_symbol) | |
3212 | { | |
3213 | fprintf (stdout, " op_symbol "); | |
3214 | ps (e->X_op_symbol); | |
3215 | fprintf (stdout, "\n"); | |
3216 | } | |
3217 | } | |
3218 | ||
3219 | static void | |
e3bb37b5 | 3220 | ps (symbolS *s) |
252b5132 RH |
3221 | { |
3222 | fprintf (stdout, "%s type %s%s", | |
3223 | S_GET_NAME (s), | |
3224 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
3225 | segment_name (S_GET_SEGMENT (s))); | |
3226 | } | |
3227 | ||
7b81dfbb | 3228 | static struct type_name |
252b5132 | 3229 | { |
40fb9820 L |
3230 | i386_operand_type mask; |
3231 | const char *name; | |
252b5132 | 3232 | } |
7b81dfbb | 3233 | const type_names[] = |
252b5132 | 3234 | { |
40fb9820 L |
3235 | { OPERAND_TYPE_REG8, "r8" }, |
3236 | { OPERAND_TYPE_REG16, "r16" }, | |
3237 | { OPERAND_TYPE_REG32, "r32" }, | |
3238 | { OPERAND_TYPE_REG64, "r64" }, | |
2c703856 JB |
3239 | { OPERAND_TYPE_ACC8, "acc8" }, |
3240 | { OPERAND_TYPE_ACC16, "acc16" }, | |
3241 | { OPERAND_TYPE_ACC32, "acc32" }, | |
3242 | { OPERAND_TYPE_ACC64, "acc64" }, | |
40fb9820 L |
3243 | { OPERAND_TYPE_IMM8, "i8" }, |
3244 | { OPERAND_TYPE_IMM8, "i8s" }, | |
3245 | { OPERAND_TYPE_IMM16, "i16" }, | |
3246 | { OPERAND_TYPE_IMM32, "i32" }, | |
3247 | { OPERAND_TYPE_IMM32S, "i32s" }, | |
3248 | { OPERAND_TYPE_IMM64, "i64" }, | |
3249 | { OPERAND_TYPE_IMM1, "i1" }, | |
3250 | { OPERAND_TYPE_BASEINDEX, "BaseIndex" }, | |
3251 | { OPERAND_TYPE_DISP8, "d8" }, | |
3252 | { OPERAND_TYPE_DISP16, "d16" }, | |
3253 | { OPERAND_TYPE_DISP32, "d32" }, | |
3254 | { OPERAND_TYPE_DISP32S, "d32s" }, | |
3255 | { OPERAND_TYPE_DISP64, "d64" }, | |
3256 | { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" }, | |
3257 | { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" }, | |
3258 | { OPERAND_TYPE_CONTROL, "control reg" }, | |
3259 | { OPERAND_TYPE_TEST, "test reg" }, | |
3260 | { OPERAND_TYPE_DEBUG, "debug reg" }, | |
3261 | { OPERAND_TYPE_FLOATREG, "FReg" }, | |
3262 | { OPERAND_TYPE_FLOATACC, "FAcc" }, | |
21df382b | 3263 | { OPERAND_TYPE_SREG, "SReg" }, |
40fb9820 L |
3264 | { OPERAND_TYPE_REGMMX, "rMMX" }, |
3265 | { OPERAND_TYPE_REGXMM, "rXMM" }, | |
0349dc08 | 3266 | { OPERAND_TYPE_REGYMM, "rYMM" }, |
43234a1e L |
3267 | { OPERAND_TYPE_REGZMM, "rZMM" }, |
3268 | { OPERAND_TYPE_REGMASK, "Mask reg" }, | |
252b5132 RH |
3269 | }; |
3270 | ||
3271 | static void | |
40fb9820 | 3272 | pt (i386_operand_type t) |
252b5132 | 3273 | { |
40fb9820 | 3274 | unsigned int j; |
c6fb90c8 | 3275 | i386_operand_type a; |
252b5132 | 3276 | |
40fb9820 | 3277 | for (j = 0; j < ARRAY_SIZE (type_names); j++) |
c6fb90c8 L |
3278 | { |
3279 | a = operand_type_and (t, type_names[j].mask); | |
2c703856 | 3280 | if (operand_type_equal (&a, &type_names[j].mask)) |
c6fb90c8 L |
3281 | fprintf (stdout, "%s, ", type_names[j].name); |
3282 | } | |
252b5132 RH |
3283 | fflush (stdout); |
3284 | } | |
3285 | ||
3286 | #endif /* DEBUG386 */ | |
3287 | \f | |
252b5132 | 3288 | static bfd_reloc_code_real_type |
3956db08 | 3289 | reloc (unsigned int size, |
64e74474 AM |
3290 | int pcrel, |
3291 | int sign, | |
3292 | bfd_reloc_code_real_type other) | |
252b5132 | 3293 | { |
47926f60 | 3294 | if (other != NO_RELOC) |
3956db08 | 3295 | { |
91d6fa6a | 3296 | reloc_howto_type *rel; |
3956db08 JB |
3297 | |
3298 | if (size == 8) | |
3299 | switch (other) | |
3300 | { | |
64e74474 AM |
3301 | case BFD_RELOC_X86_64_GOT32: |
3302 | return BFD_RELOC_X86_64_GOT64; | |
3303 | break; | |
553d1284 L |
3304 | case BFD_RELOC_X86_64_GOTPLT64: |
3305 | return BFD_RELOC_X86_64_GOTPLT64; | |
3306 | break; | |
64e74474 AM |
3307 | case BFD_RELOC_X86_64_PLTOFF64: |
3308 | return BFD_RELOC_X86_64_PLTOFF64; | |
3309 | break; | |
3310 | case BFD_RELOC_X86_64_GOTPC32: | |
3311 | other = BFD_RELOC_X86_64_GOTPC64; | |
3312 | break; | |
3313 | case BFD_RELOC_X86_64_GOTPCREL: | |
3314 | other = BFD_RELOC_X86_64_GOTPCREL64; | |
3315 | break; | |
3316 | case BFD_RELOC_X86_64_TPOFF32: | |
3317 | other = BFD_RELOC_X86_64_TPOFF64; | |
3318 | break; | |
3319 | case BFD_RELOC_X86_64_DTPOFF32: | |
3320 | other = BFD_RELOC_X86_64_DTPOFF64; | |
3321 | break; | |
3322 | default: | |
3323 | break; | |
3956db08 | 3324 | } |
e05278af | 3325 | |
8ce3d284 | 3326 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
3327 | if (other == BFD_RELOC_SIZE32) |
3328 | { | |
3329 | if (size == 8) | |
1ab668bf | 3330 | other = BFD_RELOC_SIZE64; |
8fd4256d | 3331 | if (pcrel) |
1ab668bf AM |
3332 | { |
3333 | as_bad (_("there are no pc-relative size relocations")); | |
3334 | return NO_RELOC; | |
3335 | } | |
8fd4256d | 3336 | } |
8ce3d284 | 3337 | #endif |
8fd4256d | 3338 | |
e05278af | 3339 | /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ |
f2d8a97c | 3340 | if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc)) |
e05278af JB |
3341 | sign = -1; |
3342 | ||
91d6fa6a NC |
3343 | rel = bfd_reloc_type_lookup (stdoutput, other); |
3344 | if (!rel) | |
3956db08 | 3345 | as_bad (_("unknown relocation (%u)"), other); |
91d6fa6a | 3346 | else if (size != bfd_get_reloc_size (rel)) |
3956db08 | 3347 | as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), |
91d6fa6a | 3348 | bfd_get_reloc_size (rel), |
3956db08 | 3349 | size); |
91d6fa6a | 3350 | else if (pcrel && !rel->pc_relative) |
3956db08 | 3351 | as_bad (_("non-pc-relative relocation for pc-relative field")); |
91d6fa6a | 3352 | else if ((rel->complain_on_overflow == complain_overflow_signed |
3956db08 | 3353 | && !sign) |
91d6fa6a | 3354 | || (rel->complain_on_overflow == complain_overflow_unsigned |
64e74474 | 3355 | && sign > 0)) |
3956db08 JB |
3356 | as_bad (_("relocated field and relocation type differ in signedness")); |
3357 | else | |
3358 | return other; | |
3359 | return NO_RELOC; | |
3360 | } | |
252b5132 RH |
3361 | |
3362 | if (pcrel) | |
3363 | { | |
3e73aa7c | 3364 | if (!sign) |
3956db08 | 3365 | as_bad (_("there are no unsigned pc-relative relocations")); |
252b5132 RH |
3366 | switch (size) |
3367 | { | |
3368 | case 1: return BFD_RELOC_8_PCREL; | |
3369 | case 2: return BFD_RELOC_16_PCREL; | |
d258b828 | 3370 | case 4: return BFD_RELOC_32_PCREL; |
d6ab8113 | 3371 | case 8: return BFD_RELOC_64_PCREL; |
252b5132 | 3372 | } |
3956db08 | 3373 | as_bad (_("cannot do %u byte pc-relative relocation"), size); |
252b5132 RH |
3374 | } |
3375 | else | |
3376 | { | |
3956db08 | 3377 | if (sign > 0) |
e5cb08ac | 3378 | switch (size) |
3e73aa7c JH |
3379 | { |
3380 | case 4: return BFD_RELOC_X86_64_32S; | |
3381 | } | |
3382 | else | |
3383 | switch (size) | |
3384 | { | |
3385 | case 1: return BFD_RELOC_8; | |
3386 | case 2: return BFD_RELOC_16; | |
3387 | case 4: return BFD_RELOC_32; | |
3388 | case 8: return BFD_RELOC_64; | |
3389 | } | |
3956db08 JB |
3390 | as_bad (_("cannot do %s %u byte relocation"), |
3391 | sign > 0 ? "signed" : "unsigned", size); | |
252b5132 RH |
3392 | } |
3393 | ||
0cc9e1d3 | 3394 | return NO_RELOC; |
252b5132 RH |
3395 | } |
3396 | ||
47926f60 KH |
3397 | /* Here we decide which fixups can be adjusted to make them relative to |
3398 | the beginning of the section instead of the symbol. Basically we need | |
3399 | to make sure that the dynamic relocations are done correctly, so in | |
3400 | some cases we force the original symbol to be used. */ | |
3401 | ||
252b5132 | 3402 | int |
e3bb37b5 | 3403 | tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) |
252b5132 | 3404 | { |
6d249963 | 3405 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 3406 | if (!IS_ELF) |
31312f95 AM |
3407 | return 1; |
3408 | ||
a161fe53 AM |
3409 | /* Don't adjust pc-relative references to merge sections in 64-bit |
3410 | mode. */ | |
3411 | if (use_rela_relocations | |
3412 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 | |
3413 | && fixP->fx_pcrel) | |
252b5132 | 3414 | return 0; |
31312f95 | 3415 | |
8d01d9a9 AJ |
3416 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
3417 | and changed later by validate_fix. */ | |
3418 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol | |
3419 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) | |
3420 | return 0; | |
3421 | ||
8fd4256d L |
3422 | /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol |
3423 | for size relocations. */ | |
3424 | if (fixP->fx_r_type == BFD_RELOC_SIZE32 | |
3425 | || fixP->fx_r_type == BFD_RELOC_SIZE64 | |
3426 | || fixP->fx_r_type == BFD_RELOC_386_GOTOFF | |
252b5132 | 3427 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 |
02a86693 | 3428 | || fixP->fx_r_type == BFD_RELOC_386_GOT32X |
13ae64f3 JJ |
3429 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
3430 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM | |
3431 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 | |
3432 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 | |
37e55690 JJ |
3433 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
3434 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE | |
13ae64f3 JJ |
3435 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
3436 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE | |
67a4f2b7 AO |
3437 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC |
3438 | || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL | |
3e73aa7c | 3439 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 |
80b3ee89 | 3440 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
56ceb5b5 L |
3441 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX |
3442 | || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX | |
bffbf940 JJ |
3443 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
3444 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD | |
3445 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 | |
d6ab8113 | 3446 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 |
bffbf940 JJ |
3447 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF |
3448 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 | |
d6ab8113 JB |
3449 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 |
3450 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 | |
67a4f2b7 AO |
3451 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
3452 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL | |
252b5132 RH |
3453 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
3454 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
3455 | return 0; | |
31312f95 | 3456 | #endif |
252b5132 RH |
3457 | return 1; |
3458 | } | |
252b5132 | 3459 | |
b4cac588 | 3460 | static int |
e3bb37b5 | 3461 | intel_float_operand (const char *mnemonic) |
252b5132 | 3462 | { |
9306ca4a JB |
3463 | /* Note that the value returned is meaningful only for opcodes with (memory) |
3464 | operands, hence the code here is free to improperly handle opcodes that | |
3465 | have no operands (for better performance and smaller code). */ | |
3466 | ||
3467 | if (mnemonic[0] != 'f') | |
3468 | return 0; /* non-math */ | |
3469 | ||
3470 | switch (mnemonic[1]) | |
3471 | { | |
3472 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and | |
3473 | the fs segment override prefix not currently handled because no | |
3474 | call path can make opcodes without operands get here */ | |
3475 | case 'i': | |
3476 | return 2 /* integer op */; | |
3477 | case 'l': | |
3478 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) | |
3479 | return 3; /* fldcw/fldenv */ | |
3480 | break; | |
3481 | case 'n': | |
3482 | if (mnemonic[2] != 'o' /* fnop */) | |
3483 | return 3; /* non-waiting control op */ | |
3484 | break; | |
3485 | case 'r': | |
3486 | if (mnemonic[2] == 's') | |
3487 | return 3; /* frstor/frstpm */ | |
3488 | break; | |
3489 | case 's': | |
3490 | if (mnemonic[2] == 'a') | |
3491 | return 3; /* fsave */ | |
3492 | if (mnemonic[2] == 't') | |
3493 | { | |
3494 | switch (mnemonic[3]) | |
3495 | { | |
3496 | case 'c': /* fstcw */ | |
3497 | case 'd': /* fstdw */ | |
3498 | case 'e': /* fstenv */ | |
3499 | case 's': /* fsts[gw] */ | |
3500 | return 3; | |
3501 | } | |
3502 | } | |
3503 | break; | |
3504 | case 'x': | |
3505 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') | |
3506 | return 0; /* fxsave/fxrstor are not really math ops */ | |
3507 | break; | |
3508 | } | |
252b5132 | 3509 | |
9306ca4a | 3510 | return 1; |
252b5132 RH |
3511 | } |
3512 | ||
c0f3af97 L |
3513 | /* Build the VEX prefix. */ |
3514 | ||
3515 | static void | |
d3ce72d0 | 3516 | build_vex_prefix (const insn_template *t) |
c0f3af97 L |
3517 | { |
3518 | unsigned int register_specifier; | |
3519 | unsigned int implied_prefix; | |
3520 | unsigned int vector_length; | |
03751133 | 3521 | unsigned int w; |
c0f3af97 L |
3522 | |
3523 | /* Check register specifier. */ | |
3524 | if (i.vex.register_specifier) | |
43234a1e L |
3525 | { |
3526 | register_specifier = | |
3527 | ~register_number (i.vex.register_specifier) & 0xf; | |
3528 | gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0); | |
3529 | } | |
c0f3af97 L |
3530 | else |
3531 | register_specifier = 0xf; | |
3532 | ||
79f0fa25 L |
3533 | /* Use 2-byte VEX prefix by swapping destination and source operand |
3534 | if there are more than 1 register operand. */ | |
3535 | if (i.reg_operands > 1 | |
3536 | && i.vec_encoding != vex_encoding_vex3 | |
86fa6981 | 3537 | && i.dir_encoding == dir_encoding_default |
fa99fab2 | 3538 | && i.operands == i.reg_operands |
dbbc8b7e | 3539 | && operand_type_equal (&i.types[0], &i.types[i.operands - 1]) |
7f399153 | 3540 | && i.tm.opcode_modifier.vexopcode == VEX0F |
dbbc8b7e | 3541 | && (i.tm.opcode_modifier.load || i.tm.opcode_modifier.d) |
fa99fab2 L |
3542 | && i.rex == REX_B) |
3543 | { | |
3544 | unsigned int xchg = i.operands - 1; | |
3545 | union i386_op temp_op; | |
3546 | i386_operand_type temp_type; | |
3547 | ||
3548 | temp_type = i.types[xchg]; | |
3549 | i.types[xchg] = i.types[0]; | |
3550 | i.types[0] = temp_type; | |
3551 | temp_op = i.op[xchg]; | |
3552 | i.op[xchg] = i.op[0]; | |
3553 | i.op[0] = temp_op; | |
3554 | ||
9c2799c2 | 3555 | gas_assert (i.rm.mode == 3); |
fa99fab2 L |
3556 | |
3557 | i.rex = REX_R; | |
3558 | xchg = i.rm.regmem; | |
3559 | i.rm.regmem = i.rm.reg; | |
3560 | i.rm.reg = xchg; | |
3561 | ||
dbbc8b7e JB |
3562 | if (i.tm.opcode_modifier.d) |
3563 | i.tm.base_opcode ^= (i.tm.base_opcode & 0xee) != 0x6e | |
3564 | ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD; | |
3565 | else /* Use the next insn. */ | |
3566 | i.tm = t[1]; | |
fa99fab2 L |
3567 | } |
3568 | ||
79dec6b7 JB |
3569 | /* Use 2-byte VEX prefix by swapping commutative source operands if there |
3570 | are no memory operands and at least 3 register ones. */ | |
3571 | if (i.reg_operands >= 3 | |
3572 | && i.vec_encoding != vex_encoding_vex3 | |
3573 | && i.reg_operands == i.operands - i.imm_operands | |
3574 | && i.tm.opcode_modifier.vex | |
3575 | && i.tm.opcode_modifier.commutative | |
3576 | && (i.tm.opcode_modifier.sse2avx || optimize > 1) | |
3577 | && i.rex == REX_B | |
3578 | && i.vex.register_specifier | |
3579 | && !(i.vex.register_specifier->reg_flags & RegRex)) | |
3580 | { | |
3581 | unsigned int xchg = i.operands - i.reg_operands; | |
3582 | union i386_op temp_op; | |
3583 | i386_operand_type temp_type; | |
3584 | ||
3585 | gas_assert (i.tm.opcode_modifier.vexopcode == VEX0F); | |
3586 | gas_assert (!i.tm.opcode_modifier.sae); | |
3587 | gas_assert (operand_type_equal (&i.types[i.operands - 2], | |
3588 | &i.types[i.operands - 3])); | |
3589 | gas_assert (i.rm.mode == 3); | |
3590 | ||
3591 | temp_type = i.types[xchg]; | |
3592 | i.types[xchg] = i.types[xchg + 1]; | |
3593 | i.types[xchg + 1] = temp_type; | |
3594 | temp_op = i.op[xchg]; | |
3595 | i.op[xchg] = i.op[xchg + 1]; | |
3596 | i.op[xchg + 1] = temp_op; | |
3597 | ||
3598 | i.rex = 0; | |
3599 | xchg = i.rm.regmem | 8; | |
3600 | i.rm.regmem = ~register_specifier & 0xf; | |
3601 | gas_assert (!(i.rm.regmem & 8)); | |
3602 | i.vex.register_specifier += xchg - i.rm.regmem; | |
3603 | register_specifier = ~xchg & 0xf; | |
3604 | } | |
3605 | ||
539f890d L |
3606 | if (i.tm.opcode_modifier.vex == VEXScalar) |
3607 | vector_length = avxscalar; | |
10c17abd JB |
3608 | else if (i.tm.opcode_modifier.vex == VEX256) |
3609 | vector_length = 1; | |
539f890d | 3610 | else |
10c17abd | 3611 | { |
56522fc5 | 3612 | unsigned int op; |
10c17abd | 3613 | |
c7213af9 L |
3614 | /* Determine vector length from the last multi-length vector |
3615 | operand. */ | |
10c17abd | 3616 | vector_length = 0; |
56522fc5 | 3617 | for (op = t->operands; op--;) |
10c17abd JB |
3618 | if (t->operand_types[op].bitfield.xmmword |
3619 | && t->operand_types[op].bitfield.ymmword | |
3620 | && i.types[op].bitfield.ymmword) | |
3621 | { | |
3622 | vector_length = 1; | |
3623 | break; | |
3624 | } | |
3625 | } | |
c0f3af97 L |
3626 | |
3627 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
3628 | { | |
3629 | case 0: | |
3630 | implied_prefix = 0; | |
3631 | break; | |
3632 | case DATA_PREFIX_OPCODE: | |
3633 | implied_prefix = 1; | |
3634 | break; | |
3635 | case REPE_PREFIX_OPCODE: | |
3636 | implied_prefix = 2; | |
3637 | break; | |
3638 | case REPNE_PREFIX_OPCODE: | |
3639 | implied_prefix = 3; | |
3640 | break; | |
3641 | default: | |
3642 | abort (); | |
3643 | } | |
3644 | ||
03751133 L |
3645 | /* Check the REX.W bit and VEXW. */ |
3646 | if (i.tm.opcode_modifier.vexw == VEXWIG) | |
3647 | w = (vexwig == vexw1 || (i.rex & REX_W)) ? 1 : 0; | |
3648 | else if (i.tm.opcode_modifier.vexw) | |
3649 | w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0; | |
3650 | else | |
931d03b7 | 3651 | w = (flag_code == CODE_64BIT ? i.rex & REX_W : vexwig == vexw1) ? 1 : 0; |
03751133 | 3652 | |
c0f3af97 | 3653 | /* Use 2-byte VEX prefix if possible. */ |
03751133 L |
3654 | if (w == 0 |
3655 | && i.vec_encoding != vex_encoding_vex3 | |
86fa6981 | 3656 | && i.tm.opcode_modifier.vexopcode == VEX0F |
c0f3af97 L |
3657 | && (i.rex & (REX_W | REX_X | REX_B)) == 0) |
3658 | { | |
3659 | /* 2-byte VEX prefix. */ | |
3660 | unsigned int r; | |
3661 | ||
3662 | i.vex.length = 2; | |
3663 | i.vex.bytes[0] = 0xc5; | |
3664 | ||
3665 | /* Check the REX.R bit. */ | |
3666 | r = (i.rex & REX_R) ? 0 : 1; | |
3667 | i.vex.bytes[1] = (r << 7 | |
3668 | | register_specifier << 3 | |
3669 | | vector_length << 2 | |
3670 | | implied_prefix); | |
3671 | } | |
3672 | else | |
3673 | { | |
3674 | /* 3-byte VEX prefix. */ | |
03751133 | 3675 | unsigned int m; |
c0f3af97 | 3676 | |
f88c9eb0 | 3677 | i.vex.length = 3; |
f88c9eb0 | 3678 | |
7f399153 | 3679 | switch (i.tm.opcode_modifier.vexopcode) |
5dd85c99 | 3680 | { |
7f399153 L |
3681 | case VEX0F: |
3682 | m = 0x1; | |
80de6e00 | 3683 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3684 | break; |
3685 | case VEX0F38: | |
3686 | m = 0x2; | |
80de6e00 | 3687 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3688 | break; |
3689 | case VEX0F3A: | |
3690 | m = 0x3; | |
80de6e00 | 3691 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3692 | break; |
3693 | case XOP08: | |
5dd85c99 SP |
3694 | m = 0x8; |
3695 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3696 | break; |
3697 | case XOP09: | |
f88c9eb0 SP |
3698 | m = 0x9; |
3699 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3700 | break; |
3701 | case XOP0A: | |
f88c9eb0 SP |
3702 | m = 0xa; |
3703 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3704 | break; |
3705 | default: | |
3706 | abort (); | |
f88c9eb0 | 3707 | } |
c0f3af97 | 3708 | |
c0f3af97 L |
3709 | /* The high 3 bits of the second VEX byte are 1's compliment |
3710 | of RXB bits from REX. */ | |
3711 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
3712 | ||
c0f3af97 L |
3713 | i.vex.bytes[2] = (w << 7 |
3714 | | register_specifier << 3 | |
3715 | | vector_length << 2 | |
3716 | | implied_prefix); | |
3717 | } | |
3718 | } | |
3719 | ||
e771e7c9 JB |
3720 | static INLINE bfd_boolean |
3721 | is_evex_encoding (const insn_template *t) | |
3722 | { | |
7091c612 | 3723 | return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift |
e771e7c9 | 3724 | || t->opcode_modifier.broadcast || t->opcode_modifier.masking |
a80195f1 | 3725 | || t->opcode_modifier.sae; |
e771e7c9 JB |
3726 | } |
3727 | ||
7a8655d2 JB |
3728 | static INLINE bfd_boolean |
3729 | is_any_vex_encoding (const insn_template *t) | |
3730 | { | |
3731 | return t->opcode_modifier.vex || t->opcode_modifier.vexopcode | |
3732 | || is_evex_encoding (t); | |
3733 | } | |
3734 | ||
43234a1e L |
3735 | /* Build the EVEX prefix. */ |
3736 | ||
3737 | static void | |
3738 | build_evex_prefix (void) | |
3739 | { | |
3740 | unsigned int register_specifier; | |
3741 | unsigned int implied_prefix; | |
3742 | unsigned int m, w; | |
3743 | rex_byte vrex_used = 0; | |
3744 | ||
3745 | /* Check register specifier. */ | |
3746 | if (i.vex.register_specifier) | |
3747 | { | |
3748 | gas_assert ((i.vrex & REX_X) == 0); | |
3749 | ||
3750 | register_specifier = i.vex.register_specifier->reg_num; | |
3751 | if ((i.vex.register_specifier->reg_flags & RegRex)) | |
3752 | register_specifier += 8; | |
3753 | /* The upper 16 registers are encoded in the fourth byte of the | |
3754 | EVEX prefix. */ | |
3755 | if (!(i.vex.register_specifier->reg_flags & RegVRex)) | |
3756 | i.vex.bytes[3] = 0x8; | |
3757 | register_specifier = ~register_specifier & 0xf; | |
3758 | } | |
3759 | else | |
3760 | { | |
3761 | register_specifier = 0xf; | |
3762 | ||
3763 | /* Encode upper 16 vector index register in the fourth byte of | |
3764 | the EVEX prefix. */ | |
3765 | if (!(i.vrex & REX_X)) | |
3766 | i.vex.bytes[3] = 0x8; | |
3767 | else | |
3768 | vrex_used |= REX_X; | |
3769 | } | |
3770 | ||
3771 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
3772 | { | |
3773 | case 0: | |
3774 | implied_prefix = 0; | |
3775 | break; | |
3776 | case DATA_PREFIX_OPCODE: | |
3777 | implied_prefix = 1; | |
3778 | break; | |
3779 | case REPE_PREFIX_OPCODE: | |
3780 | implied_prefix = 2; | |
3781 | break; | |
3782 | case REPNE_PREFIX_OPCODE: | |
3783 | implied_prefix = 3; | |
3784 | break; | |
3785 | default: | |
3786 | abort (); | |
3787 | } | |
3788 | ||
3789 | /* 4 byte EVEX prefix. */ | |
3790 | i.vex.length = 4; | |
3791 | i.vex.bytes[0] = 0x62; | |
3792 | ||
3793 | /* mmmm bits. */ | |
3794 | switch (i.tm.opcode_modifier.vexopcode) | |
3795 | { | |
3796 | case VEX0F: | |
3797 | m = 1; | |
3798 | break; | |
3799 | case VEX0F38: | |
3800 | m = 2; | |
3801 | break; | |
3802 | case VEX0F3A: | |
3803 | m = 3; | |
3804 | break; | |
3805 | default: | |
3806 | abort (); | |
3807 | break; | |
3808 | } | |
3809 | ||
3810 | /* The high 3 bits of the second EVEX byte are 1's compliment of RXB | |
3811 | bits from REX. */ | |
3812 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
3813 | ||
3814 | /* The fifth bit of the second EVEX byte is 1's compliment of the | |
3815 | REX_R bit in VREX. */ | |
3816 | if (!(i.vrex & REX_R)) | |
3817 | i.vex.bytes[1] |= 0x10; | |
3818 | else | |
3819 | vrex_used |= REX_R; | |
3820 | ||
3821 | if ((i.reg_operands + i.imm_operands) == i.operands) | |
3822 | { | |
3823 | /* When all operands are registers, the REX_X bit in REX is not | |
3824 | used. We reuse it to encode the upper 16 registers, which is | |
3825 | indicated by the REX_B bit in VREX. The REX_X bit is encoded | |
3826 | as 1's compliment. */ | |
3827 | if ((i.vrex & REX_B)) | |
3828 | { | |
3829 | vrex_used |= REX_B; | |
3830 | i.vex.bytes[1] &= ~0x40; | |
3831 | } | |
3832 | } | |
3833 | ||
3834 | /* EVEX instructions shouldn't need the REX prefix. */ | |
3835 | i.vrex &= ~vrex_used; | |
3836 | gas_assert (i.vrex == 0); | |
3837 | ||
6865c043 L |
3838 | /* Check the REX.W bit and VEXW. */ |
3839 | if (i.tm.opcode_modifier.vexw == VEXWIG) | |
3840 | w = (evexwig == evexw1 || (i.rex & REX_W)) ? 1 : 0; | |
3841 | else if (i.tm.opcode_modifier.vexw) | |
3842 | w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0; | |
3843 | else | |
931d03b7 | 3844 | w = (flag_code == CODE_64BIT ? i.rex & REX_W : evexwig == evexw1) ? 1 : 0; |
43234a1e L |
3845 | |
3846 | /* Encode the U bit. */ | |
3847 | implied_prefix |= 0x4; | |
3848 | ||
3849 | /* The third byte of the EVEX prefix. */ | |
3850 | i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix); | |
3851 | ||
3852 | /* The fourth byte of the EVEX prefix. */ | |
3853 | /* The zeroing-masking bit. */ | |
3854 | if (i.mask && i.mask->zeroing) | |
3855 | i.vex.bytes[3] |= 0x80; | |
3856 | ||
3857 | /* Don't always set the broadcast bit if there is no RC. */ | |
3858 | if (!i.rounding) | |
3859 | { | |
3860 | /* Encode the vector length. */ | |
3861 | unsigned int vec_length; | |
3862 | ||
e771e7c9 JB |
3863 | if (!i.tm.opcode_modifier.evex |
3864 | || i.tm.opcode_modifier.evex == EVEXDYN) | |
3865 | { | |
56522fc5 | 3866 | unsigned int op; |
e771e7c9 | 3867 | |
c7213af9 L |
3868 | /* Determine vector length from the last multi-length vector |
3869 | operand. */ | |
e771e7c9 | 3870 | vec_length = 0; |
56522fc5 | 3871 | for (op = i.operands; op--;) |
e771e7c9 JB |
3872 | if (i.tm.operand_types[op].bitfield.xmmword |
3873 | + i.tm.operand_types[op].bitfield.ymmword | |
3874 | + i.tm.operand_types[op].bitfield.zmmword > 1) | |
3875 | { | |
3876 | if (i.types[op].bitfield.zmmword) | |
c7213af9 L |
3877 | { |
3878 | i.tm.opcode_modifier.evex = EVEX512; | |
3879 | break; | |
3880 | } | |
e771e7c9 | 3881 | else if (i.types[op].bitfield.ymmword) |
c7213af9 L |
3882 | { |
3883 | i.tm.opcode_modifier.evex = EVEX256; | |
3884 | break; | |
3885 | } | |
e771e7c9 | 3886 | else if (i.types[op].bitfield.xmmword) |
c7213af9 L |
3887 | { |
3888 | i.tm.opcode_modifier.evex = EVEX128; | |
3889 | break; | |
3890 | } | |
625cbd7a JB |
3891 | else if (i.broadcast && (int) op == i.broadcast->operand) |
3892 | { | |
4a1b91ea | 3893 | switch (i.broadcast->bytes) |
625cbd7a JB |
3894 | { |
3895 | case 64: | |
3896 | i.tm.opcode_modifier.evex = EVEX512; | |
3897 | break; | |
3898 | case 32: | |
3899 | i.tm.opcode_modifier.evex = EVEX256; | |
3900 | break; | |
3901 | case 16: | |
3902 | i.tm.opcode_modifier.evex = EVEX128; | |
3903 | break; | |
3904 | default: | |
c7213af9 | 3905 | abort (); |
625cbd7a | 3906 | } |
c7213af9 | 3907 | break; |
625cbd7a | 3908 | } |
e771e7c9 | 3909 | } |
c7213af9 | 3910 | |
56522fc5 | 3911 | if (op >= MAX_OPERANDS) |
c7213af9 | 3912 | abort (); |
e771e7c9 JB |
3913 | } |
3914 | ||
43234a1e L |
3915 | switch (i.tm.opcode_modifier.evex) |
3916 | { | |
3917 | case EVEXLIG: /* LL' is ignored */ | |
3918 | vec_length = evexlig << 5; | |
3919 | break; | |
3920 | case EVEX128: | |
3921 | vec_length = 0 << 5; | |
3922 | break; | |
3923 | case EVEX256: | |
3924 | vec_length = 1 << 5; | |
3925 | break; | |
3926 | case EVEX512: | |
3927 | vec_length = 2 << 5; | |
3928 | break; | |
3929 | default: | |
3930 | abort (); | |
3931 | break; | |
3932 | } | |
3933 | i.vex.bytes[3] |= vec_length; | |
3934 | /* Encode the broadcast bit. */ | |
3935 | if (i.broadcast) | |
3936 | i.vex.bytes[3] |= 0x10; | |
3937 | } | |
3938 | else | |
3939 | { | |
3940 | if (i.rounding->type != saeonly) | |
3941 | i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5); | |
3942 | else | |
d3d3c6db | 3943 | i.vex.bytes[3] |= 0x10 | (evexrcig << 5); |
43234a1e L |
3944 | } |
3945 | ||
3946 | if (i.mask && i.mask->mask) | |
3947 | i.vex.bytes[3] |= i.mask->mask->reg_num; | |
3948 | } | |
3949 | ||
65da13b5 L |
3950 | static void |
3951 | process_immext (void) | |
3952 | { | |
3953 | expressionS *exp; | |
3954 | ||
c0f3af97 | 3955 | /* These AMD 3DNow! and SSE2 instructions have an opcode suffix |
65da13b5 L |
3956 | which is coded in the same place as an 8-bit immediate field |
3957 | would be. Here we fake an 8-bit immediate operand from the | |
3958 | opcode suffix stored in tm.extension_opcode. | |
3959 | ||
c1e679ec | 3960 | AVX instructions also use this encoding, for some of |
c0f3af97 | 3961 | 3 argument instructions. */ |
65da13b5 | 3962 | |
43234a1e | 3963 | gas_assert (i.imm_operands <= 1 |
7ab9ffdd | 3964 | && (i.operands <= 2 |
7a8655d2 | 3965 | || (is_any_vex_encoding (&i.tm) |
7ab9ffdd | 3966 | && i.operands <= 4))); |
65da13b5 L |
3967 | |
3968 | exp = &im_expressions[i.imm_operands++]; | |
3969 | i.op[i.operands].imms = exp; | |
3970 | i.types[i.operands] = imm8; | |
3971 | i.operands++; | |
3972 | exp->X_op = O_constant; | |
3973 | exp->X_add_number = i.tm.extension_opcode; | |
3974 | i.tm.extension_opcode = None; | |
3975 | } | |
3976 | ||
42164a71 L |
3977 | |
3978 | static int | |
3979 | check_hle (void) | |
3980 | { | |
3981 | switch (i.tm.opcode_modifier.hleprefixok) | |
3982 | { | |
3983 | default: | |
3984 | abort (); | |
82c2def5 | 3985 | case HLEPrefixNone: |
165de32a L |
3986 | as_bad (_("invalid instruction `%s' after `%s'"), |
3987 | i.tm.name, i.hle_prefix); | |
42164a71 | 3988 | return 0; |
82c2def5 | 3989 | case HLEPrefixLock: |
42164a71 L |
3990 | if (i.prefix[LOCK_PREFIX]) |
3991 | return 1; | |
165de32a | 3992 | as_bad (_("missing `lock' with `%s'"), i.hle_prefix); |
42164a71 | 3993 | return 0; |
82c2def5 | 3994 | case HLEPrefixAny: |
42164a71 | 3995 | return 1; |
82c2def5 | 3996 | case HLEPrefixRelease: |
42164a71 L |
3997 | if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE) |
3998 | { | |
3999 | as_bad (_("instruction `%s' after `xacquire' not allowed"), | |
4000 | i.tm.name); | |
4001 | return 0; | |
4002 | } | |
8dc0818e | 4003 | if (i.mem_operands == 0 || !(i.flags[i.operands - 1] & Operand_Mem)) |
42164a71 L |
4004 | { |
4005 | as_bad (_("memory destination needed for instruction `%s'" | |
4006 | " after `xrelease'"), i.tm.name); | |
4007 | return 0; | |
4008 | } | |
4009 | return 1; | |
4010 | } | |
4011 | } | |
4012 | ||
b6f8c7c4 L |
4013 | /* Try the shortest encoding by shortening operand size. */ |
4014 | ||
4015 | static void | |
4016 | optimize_encoding (void) | |
4017 | { | |
a0a1771e | 4018 | unsigned int j; |
b6f8c7c4 L |
4019 | |
4020 | if (optimize_for_space | |
72aea328 | 4021 | && !is_any_vex_encoding (&i.tm) |
b6f8c7c4 L |
4022 | && i.reg_operands == 1 |
4023 | && i.imm_operands == 1 | |
4024 | && !i.types[1].bitfield.byte | |
4025 | && i.op[0].imms->X_op == O_constant | |
4026 | && fits_in_imm7 (i.op[0].imms->X_add_number) | |
72aea328 | 4027 | && (i.tm.base_opcode == 0xa8 |
b6f8c7c4 L |
4028 | || (i.tm.base_opcode == 0xf6 |
4029 | && i.tm.extension_opcode == 0x0))) | |
4030 | { | |
4031 | /* Optimize: -Os: | |
4032 | test $imm7, %r64/%r32/%r16 -> test $imm7, %r8 | |
4033 | */ | |
4034 | unsigned int base_regnum = i.op[1].regs->reg_num; | |
4035 | if (flag_code == CODE_64BIT || base_regnum < 4) | |
4036 | { | |
4037 | i.types[1].bitfield.byte = 1; | |
4038 | /* Ignore the suffix. */ | |
4039 | i.suffix = 0; | |
7697afb6 JB |
4040 | /* Convert to byte registers. */ |
4041 | if (i.types[1].bitfield.word) | |
4042 | j = 16; | |
4043 | else if (i.types[1].bitfield.dword) | |
4044 | j = 32; | |
4045 | else | |
4046 | j = 48; | |
4047 | if (!(i.op[1].regs->reg_flags & RegRex) && base_regnum < 4) | |
4048 | j += 8; | |
4049 | i.op[1].regs -= j; | |
b6f8c7c4 L |
4050 | } |
4051 | } | |
4052 | else if (flag_code == CODE_64BIT | |
72aea328 | 4053 | && !is_any_vex_encoding (&i.tm) |
d3d50934 L |
4054 | && ((i.types[1].bitfield.qword |
4055 | && i.reg_operands == 1 | |
b6f8c7c4 L |
4056 | && i.imm_operands == 1 |
4057 | && i.op[0].imms->X_op == O_constant | |
507916b8 | 4058 | && ((i.tm.base_opcode == 0xb8 |
b6f8c7c4 L |
4059 | && i.tm.extension_opcode == None |
4060 | && fits_in_unsigned_long (i.op[0].imms->X_add_number)) | |
4061 | || (fits_in_imm31 (i.op[0].imms->X_add_number) | |
72aea328 JB |
4062 | && ((i.tm.base_opcode == 0x24 |
4063 | || i.tm.base_opcode == 0xa8) | |
b6f8c7c4 L |
4064 | || (i.tm.base_opcode == 0x80 |
4065 | && i.tm.extension_opcode == 0x4) | |
4066 | || ((i.tm.base_opcode == 0xf6 | |
507916b8 | 4067 | || (i.tm.base_opcode | 1) == 0xc7) |
b8364fa7 JB |
4068 | && i.tm.extension_opcode == 0x0))) |
4069 | || (fits_in_imm7 (i.op[0].imms->X_add_number) | |
4070 | && i.tm.base_opcode == 0x83 | |
4071 | && i.tm.extension_opcode == 0x4))) | |
d3d50934 L |
4072 | || (i.types[0].bitfield.qword |
4073 | && ((i.reg_operands == 2 | |
4074 | && i.op[0].regs == i.op[1].regs | |
72aea328 JB |
4075 | && (i.tm.base_opcode == 0x30 |
4076 | || i.tm.base_opcode == 0x28)) | |
d3d50934 L |
4077 | || (i.reg_operands == 1 |
4078 | && i.operands == 1 | |
72aea328 | 4079 | && i.tm.base_opcode == 0x30))))) |
b6f8c7c4 L |
4080 | { |
4081 | /* Optimize: -O: | |
4082 | andq $imm31, %r64 -> andl $imm31, %r32 | |
b8364fa7 | 4083 | andq $imm7, %r64 -> andl $imm7, %r32 |
b6f8c7c4 L |
4084 | testq $imm31, %r64 -> testl $imm31, %r32 |
4085 | xorq %r64, %r64 -> xorl %r32, %r32 | |
4086 | subq %r64, %r64 -> subl %r32, %r32 | |
4087 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4088 | movq $imm32, %r64 -> movl $imm32, %r32 | |
4089 | */ | |
4090 | i.tm.opcode_modifier.norex64 = 1; | |
507916b8 | 4091 | if (i.tm.base_opcode == 0xb8 || (i.tm.base_opcode | 1) == 0xc7) |
b6f8c7c4 L |
4092 | { |
4093 | /* Handle | |
4094 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4095 | movq $imm32, %r64 -> movl $imm32, %r32 | |
4096 | */ | |
4097 | i.tm.operand_types[0].bitfield.imm32 = 1; | |
4098 | i.tm.operand_types[0].bitfield.imm32s = 0; | |
4099 | i.tm.operand_types[0].bitfield.imm64 = 0; | |
4100 | i.types[0].bitfield.imm32 = 1; | |
4101 | i.types[0].bitfield.imm32s = 0; | |
4102 | i.types[0].bitfield.imm64 = 0; | |
4103 | i.types[1].bitfield.dword = 1; | |
4104 | i.types[1].bitfield.qword = 0; | |
507916b8 | 4105 | if ((i.tm.base_opcode | 1) == 0xc7) |
b6f8c7c4 L |
4106 | { |
4107 | /* Handle | |
4108 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4109 | */ | |
507916b8 | 4110 | i.tm.base_opcode = 0xb8; |
b6f8c7c4 | 4111 | i.tm.extension_opcode = None; |
507916b8 | 4112 | i.tm.opcode_modifier.w = 0; |
b6f8c7c4 L |
4113 | i.tm.opcode_modifier.modrm = 0; |
4114 | } | |
4115 | } | |
4116 | } | |
5641ec01 JB |
4117 | else if (optimize > 1 |
4118 | && !optimize_for_space | |
72aea328 | 4119 | && !is_any_vex_encoding (&i.tm) |
5641ec01 JB |
4120 | && i.reg_operands == 2 |
4121 | && i.op[0].regs == i.op[1].regs | |
4122 | && ((i.tm.base_opcode & ~(Opcode_D | 1)) == 0x8 | |
4123 | || (i.tm.base_opcode & ~(Opcode_D | 1)) == 0x20) | |
4124 | && (flag_code != CODE_64BIT || !i.types[0].bitfield.dword)) | |
4125 | { | |
4126 | /* Optimize: -O2: | |
4127 | andb %rN, %rN -> testb %rN, %rN | |
4128 | andw %rN, %rN -> testw %rN, %rN | |
4129 | andq %rN, %rN -> testq %rN, %rN | |
4130 | orb %rN, %rN -> testb %rN, %rN | |
4131 | orw %rN, %rN -> testw %rN, %rN | |
4132 | orq %rN, %rN -> testq %rN, %rN | |
4133 | ||
4134 | and outside of 64-bit mode | |
4135 | ||
4136 | andl %rN, %rN -> testl %rN, %rN | |
4137 | orl %rN, %rN -> testl %rN, %rN | |
4138 | */ | |
4139 | i.tm.base_opcode = 0x84 | (i.tm.base_opcode & 1); | |
4140 | } | |
99112332 | 4141 | else if (i.reg_operands == 3 |
b6f8c7c4 L |
4142 | && i.op[0].regs == i.op[1].regs |
4143 | && !i.types[2].bitfield.xmmword | |
4144 | && (i.tm.opcode_modifier.vex | |
7a69eac3 | 4145 | || ((!i.mask || i.mask->zeroing) |
b6f8c7c4 | 4146 | && !i.rounding |
e771e7c9 | 4147 | && is_evex_encoding (&i.tm) |
80c34c38 | 4148 | && (i.vec_encoding != vex_encoding_evex |
dd22218c | 4149 | || cpu_arch_isa_flags.bitfield.cpuavx512vl |
80c34c38 | 4150 | || i.tm.cpu_flags.bitfield.cpuavx512vl |
7091c612 | 4151 | || (i.tm.operand_types[2].bitfield.zmmword |
dd22218c | 4152 | && i.types[2].bitfield.ymmword)))) |
b6f8c7c4 L |
4153 | && ((i.tm.base_opcode == 0x55 |
4154 | || i.tm.base_opcode == 0x6655 | |
4155 | || i.tm.base_opcode == 0x66df | |
4156 | || i.tm.base_opcode == 0x57 | |
4157 | || i.tm.base_opcode == 0x6657 | |
8305403a L |
4158 | || i.tm.base_opcode == 0x66ef |
4159 | || i.tm.base_opcode == 0x66f8 | |
4160 | || i.tm.base_opcode == 0x66f9 | |
4161 | || i.tm.base_opcode == 0x66fa | |
1424ad86 JB |
4162 | || i.tm.base_opcode == 0x66fb |
4163 | || i.tm.base_opcode == 0x42 | |
4164 | || i.tm.base_opcode == 0x6642 | |
4165 | || i.tm.base_opcode == 0x47 | |
4166 | || i.tm.base_opcode == 0x6647) | |
b6f8c7c4 L |
4167 | && i.tm.extension_opcode == None)) |
4168 | { | |
99112332 | 4169 | /* Optimize: -O1: |
8305403a L |
4170 | VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd, |
4171 | vpsubq and vpsubw: | |
b6f8c7c4 L |
4172 | EVEX VOP %zmmM, %zmmM, %zmmN |
4173 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4174 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4175 | EVEX VOP %ymmM, %ymmM, %ymmN |
4176 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4177 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4178 | VEX VOP %ymmM, %ymmM, %ymmN |
4179 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
4180 | VOP, one of vpandn and vpxor: | |
4181 | VEX VOP %ymmM, %ymmM, %ymmN | |
4182 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
4183 | VOP, one of vpandnd and vpandnq: | |
4184 | EVEX VOP %zmmM, %zmmM, %zmmN | |
4185 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4186 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4187 | EVEX VOP %ymmM, %ymmM, %ymmN |
4188 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4189 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4190 | VOP, one of vpxord and vpxorq: |
4191 | EVEX VOP %zmmM, %zmmM, %zmmN | |
4192 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4193 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4194 | EVEX VOP %ymmM, %ymmM, %ymmN |
4195 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4196 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
1424ad86 JB |
4197 | VOP, one of kxord and kxorq: |
4198 | VEX VOP %kM, %kM, %kN | |
4199 | -> VEX kxorw %kM, %kM, %kN | |
4200 | VOP, one of kandnd and kandnq: | |
4201 | VEX VOP %kM, %kM, %kN | |
4202 | -> VEX kandnw %kM, %kM, %kN | |
b6f8c7c4 | 4203 | */ |
e771e7c9 | 4204 | if (is_evex_encoding (&i.tm)) |
b6f8c7c4 | 4205 | { |
7b1d7ca1 | 4206 | if (i.vec_encoding != vex_encoding_evex) |
b6f8c7c4 L |
4207 | { |
4208 | i.tm.opcode_modifier.vex = VEX128; | |
4209 | i.tm.opcode_modifier.vexw = VEXW0; | |
4210 | i.tm.opcode_modifier.evex = 0; | |
4211 | } | |
7b1d7ca1 | 4212 | else if (optimize > 1) |
dd22218c L |
4213 | i.tm.opcode_modifier.evex = EVEX128; |
4214 | else | |
4215 | return; | |
b6f8c7c4 | 4216 | } |
f74a6307 | 4217 | else if (i.tm.operand_types[0].bitfield.class == RegMask) |
1424ad86 JB |
4218 | { |
4219 | i.tm.base_opcode &= 0xff; | |
4220 | i.tm.opcode_modifier.vexw = VEXW0; | |
4221 | } | |
b6f8c7c4 L |
4222 | else |
4223 | i.tm.opcode_modifier.vex = VEX128; | |
4224 | ||
4225 | if (i.tm.opcode_modifier.vex) | |
4226 | for (j = 0; j < 3; j++) | |
4227 | { | |
4228 | i.types[j].bitfield.xmmword = 1; | |
4229 | i.types[j].bitfield.ymmword = 0; | |
4230 | } | |
4231 | } | |
392a5972 | 4232 | else if (i.vec_encoding != vex_encoding_evex |
97ed31ae | 4233 | && !i.types[0].bitfield.zmmword |
392a5972 | 4234 | && !i.types[1].bitfield.zmmword |
97ed31ae | 4235 | && !i.mask |
a0a1771e | 4236 | && !i.broadcast |
97ed31ae | 4237 | && is_evex_encoding (&i.tm) |
392a5972 L |
4238 | && ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0x666f |
4239 | || (i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf36f | |
a0a1771e JB |
4240 | || (i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf26f |
4241 | || (i.tm.base_opcode & ~4) == 0x66db | |
4242 | || (i.tm.base_opcode & ~4) == 0x66eb) | |
97ed31ae L |
4243 | && i.tm.extension_opcode == None) |
4244 | { | |
4245 | /* Optimize: -O1: | |
4246 | VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, | |
4247 | vmovdqu32 and vmovdqu64: | |
4248 | EVEX VOP %xmmM, %xmmN | |
4249 | -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16) | |
4250 | EVEX VOP %ymmM, %ymmN | |
4251 | -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16) | |
4252 | EVEX VOP %xmmM, mem | |
4253 | -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16) | |
4254 | EVEX VOP %ymmM, mem | |
4255 | -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16) | |
4256 | EVEX VOP mem, %xmmN | |
4257 | -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16) | |
4258 | EVEX VOP mem, %ymmN | |
4259 | -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16) | |
a0a1771e JB |
4260 | VOP, one of vpand, vpandn, vpor, vpxor: |
4261 | EVEX VOP{d,q} %xmmL, %xmmM, %xmmN | |
4262 | -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16) | |
4263 | EVEX VOP{d,q} %ymmL, %ymmM, %ymmN | |
4264 | -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16) | |
4265 | EVEX VOP{d,q} mem, %xmmM, %xmmN | |
4266 | -> VEX VOP mem, %xmmM, %xmmN (M and N < 16) | |
4267 | EVEX VOP{d,q} mem, %ymmM, %ymmN | |
4268 | -> VEX VOP mem, %ymmM, %ymmN (M and N < 16) | |
97ed31ae | 4269 | */ |
a0a1771e | 4270 | for (j = 0; j < i.operands; j++) |
392a5972 L |
4271 | if (operand_type_check (i.types[j], disp) |
4272 | && i.op[j].disps->X_op == O_constant) | |
4273 | { | |
4274 | /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix | |
4275 | has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4 | |
4276 | bytes, we choose EVEX Disp8 over VEX Disp32. */ | |
4277 | int evex_disp8, vex_disp8; | |
4278 | unsigned int memshift = i.memshift; | |
4279 | offsetT n = i.op[j].disps->X_add_number; | |
4280 | ||
4281 | evex_disp8 = fits_in_disp8 (n); | |
4282 | i.memshift = 0; | |
4283 | vex_disp8 = fits_in_disp8 (n); | |
4284 | if (evex_disp8 != vex_disp8) | |
4285 | { | |
4286 | i.memshift = memshift; | |
4287 | return; | |
4288 | } | |
4289 | ||
4290 | i.types[j].bitfield.disp8 = vex_disp8; | |
4291 | break; | |
4292 | } | |
4293 | if ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0xf26f) | |
4294 | i.tm.base_opcode ^= 0xf36f ^ 0xf26f; | |
97ed31ae L |
4295 | i.tm.opcode_modifier.vex |
4296 | = i.types[0].bitfield.ymmword ? VEX256 : VEX128; | |
4297 | i.tm.opcode_modifier.vexw = VEXW0; | |
79dec6b7 JB |
4298 | /* VPAND, VPOR, and VPXOR are commutative. */ |
4299 | if (i.reg_operands == 3 && i.tm.base_opcode != 0x66df) | |
4300 | i.tm.opcode_modifier.commutative = 1; | |
97ed31ae L |
4301 | i.tm.opcode_modifier.evex = 0; |
4302 | i.tm.opcode_modifier.masking = 0; | |
a0a1771e | 4303 | i.tm.opcode_modifier.broadcast = 0; |
97ed31ae L |
4304 | i.tm.opcode_modifier.disp8memshift = 0; |
4305 | i.memshift = 0; | |
a0a1771e JB |
4306 | if (j < i.operands) |
4307 | i.types[j].bitfield.disp8 | |
4308 | = fits_in_disp8 (i.op[j].disps->X_add_number); | |
97ed31ae | 4309 | } |
b6f8c7c4 L |
4310 | } |
4311 | ||
252b5132 RH |
4312 | /* This is the guts of the machine-dependent assembler. LINE points to a |
4313 | machine dependent instruction. This function is supposed to emit | |
4314 | the frags/bytes it assembles to. */ | |
4315 | ||
4316 | void | |
65da13b5 | 4317 | md_assemble (char *line) |
252b5132 | 4318 | { |
40fb9820 | 4319 | unsigned int j; |
83b16ac6 | 4320 | char mnemonic[MAX_MNEM_SIZE], mnem_suffix; |
d3ce72d0 | 4321 | const insn_template *t; |
252b5132 | 4322 | |
47926f60 | 4323 | /* Initialize globals. */ |
252b5132 RH |
4324 | memset (&i, '\0', sizeof (i)); |
4325 | for (j = 0; j < MAX_OPERANDS; j++) | |
1ae12ab7 | 4326 | i.reloc[j] = NO_RELOC; |
252b5132 RH |
4327 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
4328 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 4329 | save_stack_p = save_stack; |
252b5132 RH |
4330 | |
4331 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
4332 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 4333 | start of a (possibly prefixed) mnemonic. */ |
252b5132 | 4334 | |
29b0f896 AM |
4335 | line = parse_insn (line, mnemonic); |
4336 | if (line == NULL) | |
4337 | return; | |
83b16ac6 | 4338 | mnem_suffix = i.suffix; |
252b5132 | 4339 | |
29b0f896 | 4340 | line = parse_operands (line, mnemonic); |
ee86248c | 4341 | this_operand = -1; |
8325cc63 JB |
4342 | xfree (i.memop1_string); |
4343 | i.memop1_string = NULL; | |
29b0f896 AM |
4344 | if (line == NULL) |
4345 | return; | |
252b5132 | 4346 | |
29b0f896 AM |
4347 | /* Now we've parsed the mnemonic into a set of templates, and have the |
4348 | operands at hand. */ | |
4349 | ||
eedb0f2c JB |
4350 | /* All Intel opcodes have reversed operands except for "bound", "enter" |
4351 | "monitor*", and "mwait*". We also don't reverse intersegment "jmp" | |
4352 | and "call" instructions with 2 immediate operands so that the immediate | |
4353 | segment precedes the offset, as it does when in AT&T mode. */ | |
4d456e3d L |
4354 | if (intel_syntax |
4355 | && i.operands > 1 | |
29b0f896 | 4356 | && (strcmp (mnemonic, "bound") != 0) |
30123838 | 4357 | && (strcmp (mnemonic, "invlpga") != 0) |
eedb0f2c JB |
4358 | && (strncmp (mnemonic, "monitor", 7) != 0) |
4359 | && (strncmp (mnemonic, "mwait", 5) != 0) | |
40fb9820 L |
4360 | && !(operand_type_check (i.types[0], imm) |
4361 | && operand_type_check (i.types[1], imm))) | |
29b0f896 AM |
4362 | swap_operands (); |
4363 | ||
ec56d5c0 JB |
4364 | /* The order of the immediates should be reversed |
4365 | for 2 immediates extrq and insertq instructions */ | |
4366 | if (i.imm_operands == 2 | |
4367 | && (strcmp (mnemonic, "extrq") == 0 | |
4368 | || strcmp (mnemonic, "insertq") == 0)) | |
4369 | swap_2_operands (0, 1); | |
4370 | ||
29b0f896 AM |
4371 | if (i.imm_operands) |
4372 | optimize_imm (); | |
4373 | ||
b300c311 L |
4374 | /* Don't optimize displacement for movabs since it only takes 64bit |
4375 | displacement. */ | |
4376 | if (i.disp_operands | |
a501d77e | 4377 | && i.disp_encoding != disp_encoding_32bit |
862be3fb L |
4378 | && (flag_code != CODE_64BIT |
4379 | || strcmp (mnemonic, "movabs") != 0)) | |
4380 | optimize_disp (); | |
29b0f896 AM |
4381 | |
4382 | /* Next, we find a template that matches the given insn, | |
4383 | making sure the overlap of the given operands types is consistent | |
4384 | with the template operand types. */ | |
252b5132 | 4385 | |
83b16ac6 | 4386 | if (!(t = match_template (mnem_suffix))) |
29b0f896 | 4387 | return; |
252b5132 | 4388 | |
7bab8ab5 | 4389 | if (sse_check != check_none |
81f8a913 | 4390 | && !i.tm.opcode_modifier.noavx |
6e3e5c9e | 4391 | && !i.tm.cpu_flags.bitfield.cpuavx |
569d50f1 | 4392 | && !i.tm.cpu_flags.bitfield.cpuavx512f |
daf50ae7 L |
4393 | && (i.tm.cpu_flags.bitfield.cpusse |
4394 | || i.tm.cpu_flags.bitfield.cpusse2 | |
4395 | || i.tm.cpu_flags.bitfield.cpusse3 | |
4396 | || i.tm.cpu_flags.bitfield.cpussse3 | |
4397 | || i.tm.cpu_flags.bitfield.cpusse4_1 | |
6e3e5c9e | 4398 | || i.tm.cpu_flags.bitfield.cpusse4_2 |
569d50f1 | 4399 | || i.tm.cpu_flags.bitfield.cpusse4a |
6e3e5c9e JB |
4400 | || i.tm.cpu_flags.bitfield.cpupclmul |
4401 | || i.tm.cpu_flags.bitfield.cpuaes | |
569d50f1 | 4402 | || i.tm.cpu_flags.bitfield.cpusha |
6e3e5c9e | 4403 | || i.tm.cpu_flags.bitfield.cpugfni)) |
daf50ae7 | 4404 | { |
7bab8ab5 | 4405 | (sse_check == check_warning |
daf50ae7 L |
4406 | ? as_warn |
4407 | : as_bad) (_("SSE instruction `%s' is used"), i.tm.name); | |
4408 | } | |
4409 | ||
40fb9820 | 4410 | if (i.tm.opcode_modifier.fwait) |
29b0f896 AM |
4411 | if (!add_prefix (FWAIT_OPCODE)) |
4412 | return; | |
252b5132 | 4413 | |
d5de92cf L |
4414 | /* Check if REP prefix is OK. */ |
4415 | if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok) | |
4416 | { | |
4417 | as_bad (_("invalid instruction `%s' after `%s'"), | |
4418 | i.tm.name, i.rep_prefix); | |
4419 | return; | |
4420 | } | |
4421 | ||
c1ba0266 L |
4422 | /* Check for lock without a lockable instruction. Destination operand |
4423 | must be memory unless it is xchg (0x86). */ | |
c32fa91d L |
4424 | if (i.prefix[LOCK_PREFIX] |
4425 | && (!i.tm.opcode_modifier.islockable | |
c1ba0266 L |
4426 | || i.mem_operands == 0 |
4427 | || (i.tm.base_opcode != 0x86 | |
8dc0818e | 4428 | && !(i.flags[i.operands - 1] & Operand_Mem)))) |
c32fa91d L |
4429 | { |
4430 | as_bad (_("expecting lockable instruction after `lock'")); | |
4431 | return; | |
4432 | } | |
4433 | ||
7a8655d2 JB |
4434 | /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */ |
4435 | if (i.prefix[DATA_PREFIX] && is_any_vex_encoding (&i.tm)) | |
4436 | { | |
4437 | as_bad (_("data size prefix invalid with `%s'"), i.tm.name); | |
4438 | return; | |
4439 | } | |
4440 | ||
42164a71 | 4441 | /* Check if HLE prefix is OK. */ |
165de32a | 4442 | if (i.hle_prefix && !check_hle ()) |
42164a71 L |
4443 | return; |
4444 | ||
7e8b059b L |
4445 | /* Check BND prefix. */ |
4446 | if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok) | |
4447 | as_bad (_("expecting valid branch instruction after `bnd'")); | |
4448 | ||
04ef582a | 4449 | /* Check NOTRACK prefix. */ |
9fef80d6 L |
4450 | if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok) |
4451 | as_bad (_("expecting indirect branch instruction after `notrack'")); | |
04ef582a | 4452 | |
327e8c42 JB |
4453 | if (i.tm.cpu_flags.bitfield.cpumpx) |
4454 | { | |
4455 | if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX]) | |
4456 | as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions.")); | |
4457 | else if (flag_code != CODE_16BIT | |
4458 | ? i.prefix[ADDR_PREFIX] | |
4459 | : i.mem_operands && !i.prefix[ADDR_PREFIX]) | |
4460 | as_bad (_("16-bit address isn't allowed in MPX instructions")); | |
4461 | } | |
7e8b059b L |
4462 | |
4463 | /* Insert BND prefix. */ | |
76d3a78a JB |
4464 | if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok) |
4465 | { | |
4466 | if (!i.prefix[BND_PREFIX]) | |
4467 | add_prefix (BND_PREFIX_OPCODE); | |
4468 | else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE) | |
4469 | { | |
4470 | as_warn (_("replacing `rep'/`repe' prefix by `bnd'")); | |
4471 | i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE; | |
4472 | } | |
4473 | } | |
7e8b059b | 4474 | |
29b0f896 | 4475 | /* Check string instruction segment overrides. */ |
51c8edf6 | 4476 | if (i.tm.opcode_modifier.isstring >= IS_STRING_ES_OP0) |
29b0f896 | 4477 | { |
51c8edf6 | 4478 | gas_assert (i.mem_operands); |
29b0f896 | 4479 | if (!check_string ()) |
5dd0794d | 4480 | return; |
fc0763e6 | 4481 | i.disp_operands = 0; |
29b0f896 | 4482 | } |
5dd0794d | 4483 | |
b6f8c7c4 L |
4484 | if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize) |
4485 | optimize_encoding (); | |
4486 | ||
29b0f896 AM |
4487 | if (!process_suffix ()) |
4488 | return; | |
e413e4e9 | 4489 | |
bc0844ae L |
4490 | /* Update operand types. */ |
4491 | for (j = 0; j < i.operands; j++) | |
4492 | i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]); | |
4493 | ||
29b0f896 AM |
4494 | /* Make still unresolved immediate matches conform to size of immediate |
4495 | given in i.suffix. */ | |
4496 | if (!finalize_imm ()) | |
4497 | return; | |
252b5132 | 4498 | |
40fb9820 | 4499 | if (i.types[0].bitfield.imm1) |
29b0f896 | 4500 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 | 4501 | |
9afe6eb8 L |
4502 | /* We only need to check those implicit registers for instructions |
4503 | with 3 operands or less. */ | |
4504 | if (i.operands <= 3) | |
4505 | for (j = 0; j < i.operands; j++) | |
75e5731b JB |
4506 | if (i.types[j].bitfield.instance != InstanceNone |
4507 | && !i.types[j].bitfield.xmmword) | |
9afe6eb8 | 4508 | i.reg_operands--; |
40fb9820 | 4509 | |
c0f3af97 L |
4510 | /* ImmExt should be processed after SSE2AVX. */ |
4511 | if (!i.tm.opcode_modifier.sse2avx | |
4512 | && i.tm.opcode_modifier.immext) | |
65da13b5 | 4513 | process_immext (); |
252b5132 | 4514 | |
29b0f896 AM |
4515 | /* For insns with operands there are more diddles to do to the opcode. */ |
4516 | if (i.operands) | |
4517 | { | |
4518 | if (!process_operands ()) | |
4519 | return; | |
4520 | } | |
40fb9820 | 4521 | else if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 AM |
4522 | { |
4523 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ | |
4524 | as_warn (_("translating to `%sp'"), i.tm.name); | |
4525 | } | |
252b5132 | 4526 | |
7a8655d2 | 4527 | if (is_any_vex_encoding (&i.tm)) |
9e5e5283 | 4528 | { |
c1dc7af5 | 4529 | if (!cpu_arch_flags.bitfield.cpui286) |
9e5e5283 | 4530 | { |
c1dc7af5 | 4531 | as_bad (_("instruction `%s' isn't supported outside of protected mode."), |
9e5e5283 L |
4532 | i.tm.name); |
4533 | return; | |
4534 | } | |
c0f3af97 | 4535 | |
9e5e5283 L |
4536 | if (i.tm.opcode_modifier.vex) |
4537 | build_vex_prefix (t); | |
4538 | else | |
4539 | build_evex_prefix (); | |
4540 | } | |
43234a1e | 4541 | |
5dd85c99 SP |
4542 | /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4 |
4543 | instructions may define INT_OPCODE as well, so avoid this corner | |
4544 | case for those instructions that use MODRM. */ | |
4545 | if (i.tm.base_opcode == INT_OPCODE | |
a6461c02 SP |
4546 | && !i.tm.opcode_modifier.modrm |
4547 | && i.op[0].imms->X_add_number == 3) | |
29b0f896 AM |
4548 | { |
4549 | i.tm.base_opcode = INT3_OPCODE; | |
4550 | i.imm_operands = 0; | |
4551 | } | |
252b5132 | 4552 | |
0cfa3eb3 JB |
4553 | if ((i.tm.opcode_modifier.jump == JUMP |
4554 | || i.tm.opcode_modifier.jump == JUMP_BYTE | |
4555 | || i.tm.opcode_modifier.jump == JUMP_DWORD) | |
29b0f896 AM |
4556 | && i.op[0].disps->X_op == O_constant) |
4557 | { | |
4558 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
4559 | the absolute address given by the constant. Since ix86 jumps and | |
4560 | calls are pc relative, we need to generate a reloc. */ | |
4561 | i.op[0].disps->X_add_symbol = &abs_symbol; | |
4562 | i.op[0].disps->X_op = O_symbol; | |
4563 | } | |
252b5132 | 4564 | |
40fb9820 | 4565 | if (i.tm.opcode_modifier.rex64) |
161a04f6 | 4566 | i.rex |= REX_W; |
252b5132 | 4567 | |
29b0f896 AM |
4568 | /* For 8 bit registers we need an empty rex prefix. Also if the |
4569 | instruction already has a prefix, we need to convert old | |
4570 | registers to new ones. */ | |
773f551c | 4571 | |
bab6aec1 | 4572 | if ((i.types[0].bitfield.class == Reg && i.types[0].bitfield.byte |
29b0f896 | 4573 | && (i.op[0].regs->reg_flags & RegRex64) != 0) |
bab6aec1 | 4574 | || (i.types[1].bitfield.class == Reg && i.types[1].bitfield.byte |
29b0f896 | 4575 | && (i.op[1].regs->reg_flags & RegRex64) != 0) |
bab6aec1 JB |
4576 | || (((i.types[0].bitfield.class == Reg && i.types[0].bitfield.byte) |
4577 | || (i.types[1].bitfield.class == Reg && i.types[1].bitfield.byte)) | |
29b0f896 AM |
4578 | && i.rex != 0)) |
4579 | { | |
4580 | int x; | |
726c5dcd | 4581 | |
29b0f896 AM |
4582 | i.rex |= REX_OPCODE; |
4583 | for (x = 0; x < 2; x++) | |
4584 | { | |
4585 | /* Look for 8 bit operand that uses old registers. */ | |
bab6aec1 | 4586 | if (i.types[x].bitfield.class == Reg && i.types[x].bitfield.byte |
29b0f896 | 4587 | && (i.op[x].regs->reg_flags & RegRex64) == 0) |
773f551c | 4588 | { |
3f93af61 | 4589 | gas_assert (!(i.op[x].regs->reg_flags & RegRex)); |
29b0f896 AM |
4590 | /* In case it is "hi" register, give up. */ |
4591 | if (i.op[x].regs->reg_num > 3) | |
a540244d | 4592 | as_bad (_("can't encode register '%s%s' in an " |
4eed87de | 4593 | "instruction requiring REX prefix."), |
a540244d | 4594 | register_prefix, i.op[x].regs->reg_name); |
773f551c | 4595 | |
29b0f896 AM |
4596 | /* Otherwise it is equivalent to the extended register. |
4597 | Since the encoding doesn't change this is merely | |
4598 | cosmetic cleanup for debug output. */ | |
4599 | ||
4600 | i.op[x].regs = i.op[x].regs + 8; | |
773f551c | 4601 | } |
29b0f896 AM |
4602 | } |
4603 | } | |
773f551c | 4604 | |
6b6b6807 L |
4605 | if (i.rex == 0 && i.rex_encoding) |
4606 | { | |
4607 | /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand | |
3f93af61 | 4608 | that uses legacy register. If it is "hi" register, don't add |
6b6b6807 L |
4609 | the REX_OPCODE byte. */ |
4610 | int x; | |
4611 | for (x = 0; x < 2; x++) | |
bab6aec1 | 4612 | if (i.types[x].bitfield.class == Reg |
6b6b6807 L |
4613 | && i.types[x].bitfield.byte |
4614 | && (i.op[x].regs->reg_flags & RegRex64) == 0 | |
4615 | && i.op[x].regs->reg_num > 3) | |
4616 | { | |
3f93af61 | 4617 | gas_assert (!(i.op[x].regs->reg_flags & RegRex)); |
6b6b6807 L |
4618 | i.rex_encoding = FALSE; |
4619 | break; | |
4620 | } | |
4621 | ||
4622 | if (i.rex_encoding) | |
4623 | i.rex = REX_OPCODE; | |
4624 | } | |
4625 | ||
7ab9ffdd | 4626 | if (i.rex != 0) |
29b0f896 AM |
4627 | add_prefix (REX_OPCODE | i.rex); |
4628 | ||
4629 | /* We are ready to output the insn. */ | |
4630 | output_insn (); | |
e379e5f3 L |
4631 | |
4632 | last_insn.seg = now_seg; | |
4633 | ||
4634 | if (i.tm.opcode_modifier.isprefix) | |
4635 | { | |
4636 | last_insn.kind = last_insn_prefix; | |
4637 | last_insn.name = i.tm.name; | |
4638 | last_insn.file = as_where (&last_insn.line); | |
4639 | } | |
4640 | else | |
4641 | last_insn.kind = last_insn_other; | |
29b0f896 AM |
4642 | } |
4643 | ||
4644 | static char * | |
e3bb37b5 | 4645 | parse_insn (char *line, char *mnemonic) |
29b0f896 AM |
4646 | { |
4647 | char *l = line; | |
4648 | char *token_start = l; | |
4649 | char *mnem_p; | |
5c6af06e | 4650 | int supported; |
d3ce72d0 | 4651 | const insn_template *t; |
b6169b20 | 4652 | char *dot_p = NULL; |
29b0f896 | 4653 | |
29b0f896 AM |
4654 | while (1) |
4655 | { | |
4656 | mnem_p = mnemonic; | |
4657 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
4658 | { | |
b6169b20 L |
4659 | if (*mnem_p == '.') |
4660 | dot_p = mnem_p; | |
29b0f896 AM |
4661 | mnem_p++; |
4662 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
45288df1 | 4663 | { |
29b0f896 AM |
4664 | as_bad (_("no such instruction: `%s'"), token_start); |
4665 | return NULL; | |
4666 | } | |
4667 | l++; | |
4668 | } | |
4669 | if (!is_space_char (*l) | |
4670 | && *l != END_OF_INSN | |
e44823cf JB |
4671 | && (intel_syntax |
4672 | || (*l != PREFIX_SEPARATOR | |
4673 | && *l != ','))) | |
29b0f896 AM |
4674 | { |
4675 | as_bad (_("invalid character %s in mnemonic"), | |
4676 | output_invalid (*l)); | |
4677 | return NULL; | |
4678 | } | |
4679 | if (token_start == l) | |
4680 | { | |
e44823cf | 4681 | if (!intel_syntax && *l == PREFIX_SEPARATOR) |
29b0f896 AM |
4682 | as_bad (_("expecting prefix; got nothing")); |
4683 | else | |
4684 | as_bad (_("expecting mnemonic; got nothing")); | |
4685 | return NULL; | |
4686 | } | |
45288df1 | 4687 | |
29b0f896 | 4688 | /* Look up instruction (or prefix) via hash table. */ |
d3ce72d0 | 4689 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
47926f60 | 4690 | |
29b0f896 AM |
4691 | if (*l != END_OF_INSN |
4692 | && (!is_space_char (*l) || l[1] != END_OF_INSN) | |
4693 | && current_templates | |
40fb9820 | 4694 | && current_templates->start->opcode_modifier.isprefix) |
29b0f896 | 4695 | { |
c6fb90c8 | 4696 | if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags)) |
2dd88dca JB |
4697 | { |
4698 | as_bad ((flag_code != CODE_64BIT | |
4699 | ? _("`%s' is only supported in 64-bit mode") | |
4700 | : _("`%s' is not supported in 64-bit mode")), | |
4701 | current_templates->start->name); | |
4702 | return NULL; | |
4703 | } | |
29b0f896 AM |
4704 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
4705 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
673fe0f0 JB |
4706 | if ((current_templates->start->opcode_modifier.size == SIZE16 |
4707 | || current_templates->start->opcode_modifier.size == SIZE32) | |
29b0f896 | 4708 | && flag_code != CODE_64BIT |
673fe0f0 | 4709 | && ((current_templates->start->opcode_modifier.size == SIZE32) |
29b0f896 AM |
4710 | ^ (flag_code == CODE_16BIT))) |
4711 | { | |
4712 | as_bad (_("redundant %s prefix"), | |
4713 | current_templates->start->name); | |
4714 | return NULL; | |
45288df1 | 4715 | } |
86fa6981 | 4716 | if (current_templates->start->opcode_length == 0) |
29b0f896 | 4717 | { |
86fa6981 L |
4718 | /* Handle pseudo prefixes. */ |
4719 | switch (current_templates->start->base_opcode) | |
4720 | { | |
4721 | case 0x0: | |
4722 | /* {disp8} */ | |
4723 | i.disp_encoding = disp_encoding_8bit; | |
4724 | break; | |
4725 | case 0x1: | |
4726 | /* {disp32} */ | |
4727 | i.disp_encoding = disp_encoding_32bit; | |
4728 | break; | |
4729 | case 0x2: | |
4730 | /* {load} */ | |
4731 | i.dir_encoding = dir_encoding_load; | |
4732 | break; | |
4733 | case 0x3: | |
4734 | /* {store} */ | |
4735 | i.dir_encoding = dir_encoding_store; | |
4736 | break; | |
4737 | case 0x4: | |
42e04b36 L |
4738 | /* {vex} */ |
4739 | i.vec_encoding = vex_encoding_vex; | |
86fa6981 L |
4740 | break; |
4741 | case 0x5: | |
4742 | /* {vex3} */ | |
4743 | i.vec_encoding = vex_encoding_vex3; | |
4744 | break; | |
4745 | case 0x6: | |
4746 | /* {evex} */ | |
4747 | i.vec_encoding = vex_encoding_evex; | |
4748 | break; | |
6b6b6807 L |
4749 | case 0x7: |
4750 | /* {rex} */ | |
4751 | i.rex_encoding = TRUE; | |
4752 | break; | |
b6f8c7c4 L |
4753 | case 0x8: |
4754 | /* {nooptimize} */ | |
4755 | i.no_optimize = TRUE; | |
4756 | break; | |
86fa6981 L |
4757 | default: |
4758 | abort (); | |
4759 | } | |
4760 | } | |
4761 | else | |
4762 | { | |
4763 | /* Add prefix, checking for repeated prefixes. */ | |
4e9ac44a | 4764 | switch (add_prefix (current_templates->start->base_opcode)) |
86fa6981 | 4765 | { |
4e9ac44a L |
4766 | case PREFIX_EXIST: |
4767 | return NULL; | |
4768 | case PREFIX_DS: | |
d777820b | 4769 | if (current_templates->start->cpu_flags.bitfield.cpuibt) |
4e9ac44a L |
4770 | i.notrack_prefix = current_templates->start->name; |
4771 | break; | |
4772 | case PREFIX_REP: | |
4773 | if (current_templates->start->cpu_flags.bitfield.cpuhle) | |
4774 | i.hle_prefix = current_templates->start->name; | |
4775 | else if (current_templates->start->cpu_flags.bitfield.cpumpx) | |
4776 | i.bnd_prefix = current_templates->start->name; | |
4777 | else | |
4778 | i.rep_prefix = current_templates->start->name; | |
4779 | break; | |
4780 | default: | |
4781 | break; | |
86fa6981 | 4782 | } |
29b0f896 AM |
4783 | } |
4784 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
4785 | token_start = ++l; | |
4786 | } | |
4787 | else | |
4788 | break; | |
4789 | } | |
45288df1 | 4790 | |
30a55f88 | 4791 | if (!current_templates) |
b6169b20 | 4792 | { |
07d5e953 JB |
4793 | /* Deprecated functionality (new code should use pseudo-prefixes instead): |
4794 | Check if we should swap operand or force 32bit displacement in | |
f8a5c266 | 4795 | encoding. */ |
30a55f88 | 4796 | if (mnem_p - 2 == dot_p && dot_p[1] == 's') |
64c49ab3 | 4797 | i.dir_encoding = dir_encoding_swap; |
8d63c93e | 4798 | else if (mnem_p - 3 == dot_p |
a501d77e L |
4799 | && dot_p[1] == 'd' |
4800 | && dot_p[2] == '8') | |
4801 | i.disp_encoding = disp_encoding_8bit; | |
8d63c93e | 4802 | else if (mnem_p - 4 == dot_p |
f8a5c266 L |
4803 | && dot_p[1] == 'd' |
4804 | && dot_p[2] == '3' | |
4805 | && dot_p[3] == '2') | |
a501d77e | 4806 | i.disp_encoding = disp_encoding_32bit; |
30a55f88 L |
4807 | else |
4808 | goto check_suffix; | |
4809 | mnem_p = dot_p; | |
4810 | *dot_p = '\0'; | |
d3ce72d0 | 4811 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
b6169b20 L |
4812 | } |
4813 | ||
29b0f896 AM |
4814 | if (!current_templates) |
4815 | { | |
dc1e8a47 | 4816 | check_suffix: |
1c529385 | 4817 | if (mnem_p > mnemonic) |
29b0f896 | 4818 | { |
1c529385 LH |
4819 | /* See if we can get a match by trimming off a suffix. */ |
4820 | switch (mnem_p[-1]) | |
29b0f896 | 4821 | { |
1c529385 LH |
4822 | case WORD_MNEM_SUFFIX: |
4823 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) | |
29b0f896 AM |
4824 | i.suffix = SHORT_MNEM_SUFFIX; |
4825 | else | |
1c529385 LH |
4826 | /* Fall through. */ |
4827 | case BYTE_MNEM_SUFFIX: | |
4828 | case QWORD_MNEM_SUFFIX: | |
4829 | i.suffix = mnem_p[-1]; | |
29b0f896 | 4830 | mnem_p[-1] = '\0'; |
d3ce72d0 | 4831 | current_templates = (const templates *) hash_find (op_hash, |
1c529385 LH |
4832 | mnemonic); |
4833 | break; | |
4834 | case SHORT_MNEM_SUFFIX: | |
4835 | case LONG_MNEM_SUFFIX: | |
4836 | if (!intel_syntax) | |
4837 | { | |
4838 | i.suffix = mnem_p[-1]; | |
4839 | mnem_p[-1] = '\0'; | |
4840 | current_templates = (const templates *) hash_find (op_hash, | |
4841 | mnemonic); | |
4842 | } | |
4843 | break; | |
4844 | ||
4845 | /* Intel Syntax. */ | |
4846 | case 'd': | |
4847 | if (intel_syntax) | |
4848 | { | |
4849 | if (intel_float_operand (mnemonic) == 1) | |
4850 | i.suffix = SHORT_MNEM_SUFFIX; | |
4851 | else | |
4852 | i.suffix = LONG_MNEM_SUFFIX; | |
4853 | mnem_p[-1] = '\0'; | |
4854 | current_templates = (const templates *) hash_find (op_hash, | |
4855 | mnemonic); | |
4856 | } | |
4857 | break; | |
29b0f896 | 4858 | } |
29b0f896 | 4859 | } |
1c529385 | 4860 | |
29b0f896 AM |
4861 | if (!current_templates) |
4862 | { | |
4863 | as_bad (_("no such instruction: `%s'"), token_start); | |
4864 | return NULL; | |
4865 | } | |
4866 | } | |
252b5132 | 4867 | |
0cfa3eb3 JB |
4868 | if (current_templates->start->opcode_modifier.jump == JUMP |
4869 | || current_templates->start->opcode_modifier.jump == JUMP_BYTE) | |
29b0f896 AM |
4870 | { |
4871 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
4872 | predict taken and predict not taken respectively. | |
4873 | I'm not sure that branch hints actually do anything on loop | |
4874 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
4875 | may work in the future and it doesn't hurt to accept them | |
4876 | now. */ | |
4877 | if (l[0] == ',' && l[1] == 'p') | |
4878 | { | |
4879 | if (l[2] == 't') | |
4880 | { | |
4881 | if (!add_prefix (DS_PREFIX_OPCODE)) | |
4882 | return NULL; | |
4883 | l += 3; | |
4884 | } | |
4885 | else if (l[2] == 'n') | |
4886 | { | |
4887 | if (!add_prefix (CS_PREFIX_OPCODE)) | |
4888 | return NULL; | |
4889 | l += 3; | |
4890 | } | |
4891 | } | |
4892 | } | |
4893 | /* Any other comma loses. */ | |
4894 | if (*l == ',') | |
4895 | { | |
4896 | as_bad (_("invalid character %s in mnemonic"), | |
4897 | output_invalid (*l)); | |
4898 | return NULL; | |
4899 | } | |
252b5132 | 4900 | |
29b0f896 | 4901 | /* Check if instruction is supported on specified architecture. */ |
5c6af06e JB |
4902 | supported = 0; |
4903 | for (t = current_templates->start; t < current_templates->end; ++t) | |
4904 | { | |
c0f3af97 L |
4905 | supported |= cpu_flags_match (t); |
4906 | if (supported == CPU_FLAGS_PERFECT_MATCH) | |
548d0ee6 JB |
4907 | { |
4908 | if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT)) | |
4909 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
3629bb00 | 4910 | |
548d0ee6 JB |
4911 | return l; |
4912 | } | |
29b0f896 | 4913 | } |
3629bb00 | 4914 | |
548d0ee6 JB |
4915 | if (!(supported & CPU_FLAGS_64BIT_MATCH)) |
4916 | as_bad (flag_code == CODE_64BIT | |
4917 | ? _("`%s' is not supported in 64-bit mode") | |
4918 | : _("`%s' is only supported in 64-bit mode"), | |
4919 | current_templates->start->name); | |
4920 | else | |
4921 | as_bad (_("`%s' is not supported on `%s%s'"), | |
4922 | current_templates->start->name, | |
4923 | cpu_arch_name ? cpu_arch_name : default_arch, | |
4924 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); | |
252b5132 | 4925 | |
548d0ee6 | 4926 | return NULL; |
29b0f896 | 4927 | } |
252b5132 | 4928 | |
29b0f896 | 4929 | static char * |
e3bb37b5 | 4930 | parse_operands (char *l, const char *mnemonic) |
29b0f896 AM |
4931 | { |
4932 | char *token_start; | |
3138f287 | 4933 | |
29b0f896 AM |
4934 | /* 1 if operand is pending after ','. */ |
4935 | unsigned int expecting_operand = 0; | |
252b5132 | 4936 | |
29b0f896 AM |
4937 | /* Non-zero if operand parens not balanced. */ |
4938 | unsigned int paren_not_balanced; | |
4939 | ||
4940 | while (*l != END_OF_INSN) | |
4941 | { | |
4942 | /* Skip optional white space before operand. */ | |
4943 | if (is_space_char (*l)) | |
4944 | ++l; | |
d02603dc | 4945 | if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"') |
29b0f896 AM |
4946 | { |
4947 | as_bad (_("invalid character %s before operand %d"), | |
4948 | output_invalid (*l), | |
4949 | i.operands + 1); | |
4950 | return NULL; | |
4951 | } | |
d02603dc | 4952 | token_start = l; /* After white space. */ |
29b0f896 AM |
4953 | paren_not_balanced = 0; |
4954 | while (paren_not_balanced || *l != ',') | |
4955 | { | |
4956 | if (*l == END_OF_INSN) | |
4957 | { | |
4958 | if (paren_not_balanced) | |
4959 | { | |
4960 | if (!intel_syntax) | |
4961 | as_bad (_("unbalanced parenthesis in operand %d."), | |
4962 | i.operands + 1); | |
4963 | else | |
4964 | as_bad (_("unbalanced brackets in operand %d."), | |
4965 | i.operands + 1); | |
4966 | return NULL; | |
4967 | } | |
4968 | else | |
4969 | break; /* we are done */ | |
4970 | } | |
d02603dc | 4971 | else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"') |
29b0f896 AM |
4972 | { |
4973 | as_bad (_("invalid character %s in operand %d"), | |
4974 | output_invalid (*l), | |
4975 | i.operands + 1); | |
4976 | return NULL; | |
4977 | } | |
4978 | if (!intel_syntax) | |
4979 | { | |
4980 | if (*l == '(') | |
4981 | ++paren_not_balanced; | |
4982 | if (*l == ')') | |
4983 | --paren_not_balanced; | |
4984 | } | |
4985 | else | |
4986 | { | |
4987 | if (*l == '[') | |
4988 | ++paren_not_balanced; | |
4989 | if (*l == ']') | |
4990 | --paren_not_balanced; | |
4991 | } | |
4992 | l++; | |
4993 | } | |
4994 | if (l != token_start) | |
4995 | { /* Yes, we've read in another operand. */ | |
4996 | unsigned int operand_ok; | |
4997 | this_operand = i.operands++; | |
4998 | if (i.operands > MAX_OPERANDS) | |
4999 | { | |
5000 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
5001 | MAX_OPERANDS); | |
5002 | return NULL; | |
5003 | } | |
9d46ce34 | 5004 | i.types[this_operand].bitfield.unspecified = 1; |
29b0f896 AM |
5005 | /* Now parse operand adding info to 'i' as we go along. */ |
5006 | END_STRING_AND_SAVE (l); | |
5007 | ||
1286ab78 L |
5008 | if (i.mem_operands > 1) |
5009 | { | |
5010 | as_bad (_("too many memory references for `%s'"), | |
5011 | mnemonic); | |
5012 | return 0; | |
5013 | } | |
5014 | ||
29b0f896 AM |
5015 | if (intel_syntax) |
5016 | operand_ok = | |
5017 | i386_intel_operand (token_start, | |
5018 | intel_float_operand (mnemonic)); | |
5019 | else | |
a7619375 | 5020 | operand_ok = i386_att_operand (token_start); |
29b0f896 AM |
5021 | |
5022 | RESTORE_END_STRING (l); | |
5023 | if (!operand_ok) | |
5024 | return NULL; | |
5025 | } | |
5026 | else | |
5027 | { | |
5028 | if (expecting_operand) | |
5029 | { | |
5030 | expecting_operand_after_comma: | |
5031 | as_bad (_("expecting operand after ','; got nothing")); | |
5032 | return NULL; | |
5033 | } | |
5034 | if (*l == ',') | |
5035 | { | |
5036 | as_bad (_("expecting operand before ','; got nothing")); | |
5037 | return NULL; | |
5038 | } | |
5039 | } | |
7f3f1ea2 | 5040 | |
29b0f896 AM |
5041 | /* Now *l must be either ',' or END_OF_INSN. */ |
5042 | if (*l == ',') | |
5043 | { | |
5044 | if (*++l == END_OF_INSN) | |
5045 | { | |
5046 | /* Just skip it, if it's \n complain. */ | |
5047 | goto expecting_operand_after_comma; | |
5048 | } | |
5049 | expecting_operand = 1; | |
5050 | } | |
5051 | } | |
5052 | return l; | |
5053 | } | |
7f3f1ea2 | 5054 | |
050dfa73 | 5055 | static void |
4d456e3d | 5056 | swap_2_operands (int xchg1, int xchg2) |
050dfa73 MM |
5057 | { |
5058 | union i386_op temp_op; | |
40fb9820 | 5059 | i386_operand_type temp_type; |
c48dadc9 | 5060 | unsigned int temp_flags; |
050dfa73 | 5061 | enum bfd_reloc_code_real temp_reloc; |
4eed87de | 5062 | |
050dfa73 MM |
5063 | temp_type = i.types[xchg2]; |
5064 | i.types[xchg2] = i.types[xchg1]; | |
5065 | i.types[xchg1] = temp_type; | |
c48dadc9 JB |
5066 | |
5067 | temp_flags = i.flags[xchg2]; | |
5068 | i.flags[xchg2] = i.flags[xchg1]; | |
5069 | i.flags[xchg1] = temp_flags; | |
5070 | ||
050dfa73 MM |
5071 | temp_op = i.op[xchg2]; |
5072 | i.op[xchg2] = i.op[xchg1]; | |
5073 | i.op[xchg1] = temp_op; | |
c48dadc9 | 5074 | |
050dfa73 MM |
5075 | temp_reloc = i.reloc[xchg2]; |
5076 | i.reloc[xchg2] = i.reloc[xchg1]; | |
5077 | i.reloc[xchg1] = temp_reloc; | |
43234a1e L |
5078 | |
5079 | if (i.mask) | |
5080 | { | |
5081 | if (i.mask->operand == xchg1) | |
5082 | i.mask->operand = xchg2; | |
5083 | else if (i.mask->operand == xchg2) | |
5084 | i.mask->operand = xchg1; | |
5085 | } | |
5086 | if (i.broadcast) | |
5087 | { | |
5088 | if (i.broadcast->operand == xchg1) | |
5089 | i.broadcast->operand = xchg2; | |
5090 | else if (i.broadcast->operand == xchg2) | |
5091 | i.broadcast->operand = xchg1; | |
5092 | } | |
5093 | if (i.rounding) | |
5094 | { | |
5095 | if (i.rounding->operand == xchg1) | |
5096 | i.rounding->operand = xchg2; | |
5097 | else if (i.rounding->operand == xchg2) | |
5098 | i.rounding->operand = xchg1; | |
5099 | } | |
050dfa73 MM |
5100 | } |
5101 | ||
29b0f896 | 5102 | static void |
e3bb37b5 | 5103 | swap_operands (void) |
29b0f896 | 5104 | { |
b7c61d9a | 5105 | switch (i.operands) |
050dfa73 | 5106 | { |
c0f3af97 | 5107 | case 5: |
b7c61d9a | 5108 | case 4: |
4d456e3d | 5109 | swap_2_operands (1, i.operands - 2); |
1a0670f3 | 5110 | /* Fall through. */ |
b7c61d9a L |
5111 | case 3: |
5112 | case 2: | |
4d456e3d | 5113 | swap_2_operands (0, i.operands - 1); |
b7c61d9a L |
5114 | break; |
5115 | default: | |
5116 | abort (); | |
29b0f896 | 5117 | } |
29b0f896 AM |
5118 | |
5119 | if (i.mem_operands == 2) | |
5120 | { | |
5121 | const seg_entry *temp_seg; | |
5122 | temp_seg = i.seg[0]; | |
5123 | i.seg[0] = i.seg[1]; | |
5124 | i.seg[1] = temp_seg; | |
5125 | } | |
5126 | } | |
252b5132 | 5127 | |
29b0f896 AM |
5128 | /* Try to ensure constant immediates are represented in the smallest |
5129 | opcode possible. */ | |
5130 | static void | |
e3bb37b5 | 5131 | optimize_imm (void) |
29b0f896 AM |
5132 | { |
5133 | char guess_suffix = 0; | |
5134 | int op; | |
252b5132 | 5135 | |
29b0f896 AM |
5136 | if (i.suffix) |
5137 | guess_suffix = i.suffix; | |
5138 | else if (i.reg_operands) | |
5139 | { | |
5140 | /* Figure out a suffix from the last register operand specified. | |
75e5731b JB |
5141 | We can't do this properly yet, i.e. excluding special register |
5142 | instances, but the following works for instructions with | |
5143 | immediates. In any case, we can't set i.suffix yet. */ | |
29b0f896 | 5144 | for (op = i.operands; --op >= 0;) |
bab6aec1 JB |
5145 | if (i.types[op].bitfield.class != Reg) |
5146 | continue; | |
5147 | else if (i.types[op].bitfield.byte) | |
7ab9ffdd | 5148 | { |
40fb9820 L |
5149 | guess_suffix = BYTE_MNEM_SUFFIX; |
5150 | break; | |
5151 | } | |
bab6aec1 | 5152 | else if (i.types[op].bitfield.word) |
252b5132 | 5153 | { |
40fb9820 L |
5154 | guess_suffix = WORD_MNEM_SUFFIX; |
5155 | break; | |
5156 | } | |
bab6aec1 | 5157 | else if (i.types[op].bitfield.dword) |
40fb9820 L |
5158 | { |
5159 | guess_suffix = LONG_MNEM_SUFFIX; | |
5160 | break; | |
5161 | } | |
bab6aec1 | 5162 | else if (i.types[op].bitfield.qword) |
40fb9820 L |
5163 | { |
5164 | guess_suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 | 5165 | break; |
252b5132 | 5166 | } |
29b0f896 AM |
5167 | } |
5168 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) | |
5169 | guess_suffix = WORD_MNEM_SUFFIX; | |
5170 | ||
5171 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 5172 | if (operand_type_check (i.types[op], imm)) |
29b0f896 AM |
5173 | { |
5174 | switch (i.op[op].imms->X_op) | |
252b5132 | 5175 | { |
29b0f896 AM |
5176 | case O_constant: |
5177 | /* If a suffix is given, this operand may be shortened. */ | |
5178 | switch (guess_suffix) | |
252b5132 | 5179 | { |
29b0f896 | 5180 | case LONG_MNEM_SUFFIX: |
40fb9820 L |
5181 | i.types[op].bitfield.imm32 = 1; |
5182 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
5183 | break; |
5184 | case WORD_MNEM_SUFFIX: | |
40fb9820 L |
5185 | i.types[op].bitfield.imm16 = 1; |
5186 | i.types[op].bitfield.imm32 = 1; | |
5187 | i.types[op].bitfield.imm32s = 1; | |
5188 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
5189 | break; |
5190 | case BYTE_MNEM_SUFFIX: | |
40fb9820 L |
5191 | i.types[op].bitfield.imm8 = 1; |
5192 | i.types[op].bitfield.imm8s = 1; | |
5193 | i.types[op].bitfield.imm16 = 1; | |
5194 | i.types[op].bitfield.imm32 = 1; | |
5195 | i.types[op].bitfield.imm32s = 1; | |
5196 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 | 5197 | break; |
252b5132 | 5198 | } |
252b5132 | 5199 | |
29b0f896 AM |
5200 | /* If this operand is at most 16 bits, convert it |
5201 | to a signed 16 bit number before trying to see | |
5202 | whether it will fit in an even smaller size. | |
5203 | This allows a 16-bit operand such as $0xffe0 to | |
5204 | be recognised as within Imm8S range. */ | |
40fb9820 | 5205 | if ((i.types[op].bitfield.imm16) |
29b0f896 | 5206 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) |
252b5132 | 5207 | { |
29b0f896 AM |
5208 | i.op[op].imms->X_add_number = |
5209 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
5210 | } | |
a28def75 L |
5211 | #ifdef BFD64 |
5212 | /* Store 32-bit immediate in 64-bit for 64-bit BFD. */ | |
40fb9820 | 5213 | if ((i.types[op].bitfield.imm32) |
29b0f896 AM |
5214 | && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) |
5215 | == 0)) | |
5216 | { | |
5217 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number | |
5218 | ^ ((offsetT) 1 << 31)) | |
5219 | - ((offsetT) 1 << 31)); | |
5220 | } | |
a28def75 | 5221 | #endif |
40fb9820 | 5222 | i.types[op] |
c6fb90c8 L |
5223 | = operand_type_or (i.types[op], |
5224 | smallest_imm_type (i.op[op].imms->X_add_number)); | |
252b5132 | 5225 | |
29b0f896 AM |
5226 | /* We must avoid matching of Imm32 templates when 64bit |
5227 | only immediate is available. */ | |
5228 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
40fb9820 | 5229 | i.types[op].bitfield.imm32 = 0; |
29b0f896 | 5230 | break; |
252b5132 | 5231 | |
29b0f896 AM |
5232 | case O_absent: |
5233 | case O_register: | |
5234 | abort (); | |
5235 | ||
5236 | /* Symbols and expressions. */ | |
5237 | default: | |
9cd96992 JB |
5238 | /* Convert symbolic operand to proper sizes for matching, but don't |
5239 | prevent matching a set of insns that only supports sizes other | |
5240 | than those matching the insn suffix. */ | |
5241 | { | |
40fb9820 | 5242 | i386_operand_type mask, allowed; |
d3ce72d0 | 5243 | const insn_template *t; |
9cd96992 | 5244 | |
0dfbf9d7 L |
5245 | operand_type_set (&mask, 0); |
5246 | operand_type_set (&allowed, 0); | |
40fb9820 | 5247 | |
4eed87de AM |
5248 | for (t = current_templates->start; |
5249 | t < current_templates->end; | |
5250 | ++t) | |
bab6aec1 JB |
5251 | { |
5252 | allowed = operand_type_or (allowed, t->operand_types[op]); | |
5253 | allowed = operand_type_and (allowed, anyimm); | |
5254 | } | |
9cd96992 JB |
5255 | switch (guess_suffix) |
5256 | { | |
5257 | case QWORD_MNEM_SUFFIX: | |
40fb9820 L |
5258 | mask.bitfield.imm64 = 1; |
5259 | mask.bitfield.imm32s = 1; | |
9cd96992 JB |
5260 | break; |
5261 | case LONG_MNEM_SUFFIX: | |
40fb9820 | 5262 | mask.bitfield.imm32 = 1; |
9cd96992 JB |
5263 | break; |
5264 | case WORD_MNEM_SUFFIX: | |
40fb9820 | 5265 | mask.bitfield.imm16 = 1; |
9cd96992 JB |
5266 | break; |
5267 | case BYTE_MNEM_SUFFIX: | |
40fb9820 | 5268 | mask.bitfield.imm8 = 1; |
9cd96992 JB |
5269 | break; |
5270 | default: | |
9cd96992 JB |
5271 | break; |
5272 | } | |
c6fb90c8 | 5273 | allowed = operand_type_and (mask, allowed); |
0dfbf9d7 | 5274 | if (!operand_type_all_zero (&allowed)) |
c6fb90c8 | 5275 | i.types[op] = operand_type_and (i.types[op], mask); |
9cd96992 | 5276 | } |
29b0f896 | 5277 | break; |
252b5132 | 5278 | } |
29b0f896 AM |
5279 | } |
5280 | } | |
47926f60 | 5281 | |
29b0f896 AM |
5282 | /* Try to use the smallest displacement type too. */ |
5283 | static void | |
e3bb37b5 | 5284 | optimize_disp (void) |
29b0f896 AM |
5285 | { |
5286 | int op; | |
3e73aa7c | 5287 | |
29b0f896 | 5288 | for (op = i.operands; --op >= 0;) |
40fb9820 | 5289 | if (operand_type_check (i.types[op], disp)) |
252b5132 | 5290 | { |
b300c311 | 5291 | if (i.op[op].disps->X_op == O_constant) |
252b5132 | 5292 | { |
91d6fa6a | 5293 | offsetT op_disp = i.op[op].disps->X_add_number; |
29b0f896 | 5294 | |
40fb9820 | 5295 | if (i.types[op].bitfield.disp16 |
91d6fa6a | 5296 | && (op_disp & ~(offsetT) 0xffff) == 0) |
b300c311 L |
5297 | { |
5298 | /* If this operand is at most 16 bits, convert | |
5299 | to a signed 16 bit number and don't use 64bit | |
5300 | displacement. */ | |
91d6fa6a | 5301 | op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000); |
40fb9820 | 5302 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 5303 | } |
a28def75 L |
5304 | #ifdef BFD64 |
5305 | /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */ | |
40fb9820 | 5306 | if (i.types[op].bitfield.disp32 |
91d6fa6a | 5307 | && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0) |
b300c311 L |
5308 | { |
5309 | /* If this operand is at most 32 bits, convert | |
5310 | to a signed 32 bit number and don't use 64bit | |
5311 | displacement. */ | |
91d6fa6a NC |
5312 | op_disp &= (((offsetT) 2 << 31) - 1); |
5313 | op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
40fb9820 | 5314 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 5315 | } |
a28def75 | 5316 | #endif |
91d6fa6a | 5317 | if (!op_disp && i.types[op].bitfield.baseindex) |
b300c311 | 5318 | { |
40fb9820 L |
5319 | i.types[op].bitfield.disp8 = 0; |
5320 | i.types[op].bitfield.disp16 = 0; | |
5321 | i.types[op].bitfield.disp32 = 0; | |
5322 | i.types[op].bitfield.disp32s = 0; | |
5323 | i.types[op].bitfield.disp64 = 0; | |
b300c311 L |
5324 | i.op[op].disps = 0; |
5325 | i.disp_operands--; | |
5326 | } | |
5327 | else if (flag_code == CODE_64BIT) | |
5328 | { | |
91d6fa6a | 5329 | if (fits_in_signed_long (op_disp)) |
28a9d8f5 | 5330 | { |
40fb9820 L |
5331 | i.types[op].bitfield.disp64 = 0; |
5332 | i.types[op].bitfield.disp32s = 1; | |
28a9d8f5 | 5333 | } |
0e1147d9 | 5334 | if (i.prefix[ADDR_PREFIX] |
91d6fa6a | 5335 | && fits_in_unsigned_long (op_disp)) |
40fb9820 | 5336 | i.types[op].bitfield.disp32 = 1; |
b300c311 | 5337 | } |
40fb9820 L |
5338 | if ((i.types[op].bitfield.disp32 |
5339 | || i.types[op].bitfield.disp32s | |
5340 | || i.types[op].bitfield.disp16) | |
b5014f7a | 5341 | && fits_in_disp8 (op_disp)) |
40fb9820 | 5342 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 5343 | } |
67a4f2b7 AO |
5344 | else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
5345 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) | |
5346 | { | |
5347 | fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, | |
5348 | i.op[op].disps, 0, i.reloc[op]); | |
40fb9820 L |
5349 | i.types[op].bitfield.disp8 = 0; |
5350 | i.types[op].bitfield.disp16 = 0; | |
5351 | i.types[op].bitfield.disp32 = 0; | |
5352 | i.types[op].bitfield.disp32s = 0; | |
5353 | i.types[op].bitfield.disp64 = 0; | |
67a4f2b7 AO |
5354 | } |
5355 | else | |
b300c311 | 5356 | /* We only support 64bit displacement on constants. */ |
40fb9820 | 5357 | i.types[op].bitfield.disp64 = 0; |
252b5132 | 5358 | } |
29b0f896 AM |
5359 | } |
5360 | ||
4a1b91ea L |
5361 | /* Return 1 if there is a match in broadcast bytes between operand |
5362 | GIVEN and instruction template T. */ | |
5363 | ||
5364 | static INLINE int | |
5365 | match_broadcast_size (const insn_template *t, unsigned int given) | |
5366 | { | |
5367 | return ((t->opcode_modifier.broadcast == BYTE_BROADCAST | |
5368 | && i.types[given].bitfield.byte) | |
5369 | || (t->opcode_modifier.broadcast == WORD_BROADCAST | |
5370 | && i.types[given].bitfield.word) | |
5371 | || (t->opcode_modifier.broadcast == DWORD_BROADCAST | |
5372 | && i.types[given].bitfield.dword) | |
5373 | || (t->opcode_modifier.broadcast == QWORD_BROADCAST | |
5374 | && i.types[given].bitfield.qword)); | |
5375 | } | |
5376 | ||
6c30d220 L |
5377 | /* Check if operands are valid for the instruction. */ |
5378 | ||
5379 | static int | |
5380 | check_VecOperands (const insn_template *t) | |
5381 | { | |
43234a1e | 5382 | unsigned int op; |
e2195274 | 5383 | i386_cpu_flags cpu; |
e2195274 JB |
5384 | |
5385 | /* Templates allowing for ZMMword as well as YMMword and/or XMMword for | |
5386 | any one operand are implicity requiring AVX512VL support if the actual | |
5387 | operand size is YMMword or XMMword. Since this function runs after | |
5388 | template matching, there's no need to check for YMMword/XMMword in | |
5389 | the template. */ | |
5390 | cpu = cpu_flags_and (t->cpu_flags, avx512); | |
5391 | if (!cpu_flags_all_zero (&cpu) | |
5392 | && !t->cpu_flags.bitfield.cpuavx512vl | |
5393 | && !cpu_arch_flags.bitfield.cpuavx512vl) | |
5394 | { | |
5395 | for (op = 0; op < t->operands; ++op) | |
5396 | { | |
5397 | if (t->operand_types[op].bitfield.zmmword | |
5398 | && (i.types[op].bitfield.ymmword | |
5399 | || i.types[op].bitfield.xmmword)) | |
5400 | { | |
5401 | i.error = unsupported; | |
5402 | return 1; | |
5403 | } | |
5404 | } | |
5405 | } | |
43234a1e | 5406 | |
6c30d220 L |
5407 | /* Without VSIB byte, we can't have a vector register for index. */ |
5408 | if (!t->opcode_modifier.vecsib | |
5409 | && i.index_reg | |
1b54b8d7 JB |
5410 | && (i.index_reg->reg_type.bitfield.xmmword |
5411 | || i.index_reg->reg_type.bitfield.ymmword | |
5412 | || i.index_reg->reg_type.bitfield.zmmword)) | |
6c30d220 L |
5413 | { |
5414 | i.error = unsupported_vector_index_register; | |
5415 | return 1; | |
5416 | } | |
5417 | ||
ad8ecc81 MZ |
5418 | /* Check if default mask is allowed. */ |
5419 | if (t->opcode_modifier.nodefmask | |
5420 | && (!i.mask || i.mask->mask->reg_num == 0)) | |
5421 | { | |
5422 | i.error = no_default_mask; | |
5423 | return 1; | |
5424 | } | |
5425 | ||
7bab8ab5 JB |
5426 | /* For VSIB byte, we need a vector register for index, and all vector |
5427 | registers must be distinct. */ | |
5428 | if (t->opcode_modifier.vecsib) | |
5429 | { | |
5430 | if (!i.index_reg | |
6c30d220 | 5431 | || !((t->opcode_modifier.vecsib == VecSIB128 |
1b54b8d7 | 5432 | && i.index_reg->reg_type.bitfield.xmmword) |
6c30d220 | 5433 | || (t->opcode_modifier.vecsib == VecSIB256 |
1b54b8d7 | 5434 | && i.index_reg->reg_type.bitfield.ymmword) |
43234a1e | 5435 | || (t->opcode_modifier.vecsib == VecSIB512 |
1b54b8d7 | 5436 | && i.index_reg->reg_type.bitfield.zmmword))) |
7bab8ab5 JB |
5437 | { |
5438 | i.error = invalid_vsib_address; | |
5439 | return 1; | |
5440 | } | |
5441 | ||
43234a1e L |
5442 | gas_assert (i.reg_operands == 2 || i.mask); |
5443 | if (i.reg_operands == 2 && !i.mask) | |
5444 | { | |
3528c362 | 5445 | gas_assert (i.types[0].bitfield.class == RegSIMD); |
1b54b8d7 JB |
5446 | gas_assert (i.types[0].bitfield.xmmword |
5447 | || i.types[0].bitfield.ymmword); | |
3528c362 | 5448 | gas_assert (i.types[2].bitfield.class == RegSIMD); |
1b54b8d7 JB |
5449 | gas_assert (i.types[2].bitfield.xmmword |
5450 | || i.types[2].bitfield.ymmword); | |
43234a1e L |
5451 | if (operand_check == check_none) |
5452 | return 0; | |
5453 | if (register_number (i.op[0].regs) | |
5454 | != register_number (i.index_reg) | |
5455 | && register_number (i.op[2].regs) | |
5456 | != register_number (i.index_reg) | |
5457 | && register_number (i.op[0].regs) | |
5458 | != register_number (i.op[2].regs)) | |
5459 | return 0; | |
5460 | if (operand_check == check_error) | |
5461 | { | |
5462 | i.error = invalid_vector_register_set; | |
5463 | return 1; | |
5464 | } | |
5465 | as_warn (_("mask, index, and destination registers should be distinct")); | |
5466 | } | |
8444f82a MZ |
5467 | else if (i.reg_operands == 1 && i.mask) |
5468 | { | |
3528c362 | 5469 | if (i.types[1].bitfield.class == RegSIMD |
1b54b8d7 JB |
5470 | && (i.types[1].bitfield.xmmword |
5471 | || i.types[1].bitfield.ymmword | |
5472 | || i.types[1].bitfield.zmmword) | |
8444f82a MZ |
5473 | && (register_number (i.op[1].regs) |
5474 | == register_number (i.index_reg))) | |
5475 | { | |
5476 | if (operand_check == check_error) | |
5477 | { | |
5478 | i.error = invalid_vector_register_set; | |
5479 | return 1; | |
5480 | } | |
5481 | if (operand_check != check_none) | |
5482 | as_warn (_("index and destination registers should be distinct")); | |
5483 | } | |
5484 | } | |
43234a1e | 5485 | } |
7bab8ab5 | 5486 | |
43234a1e L |
5487 | /* Check if broadcast is supported by the instruction and is applied |
5488 | to the memory operand. */ | |
5489 | if (i.broadcast) | |
5490 | { | |
8e6e0792 | 5491 | i386_operand_type type, overlap; |
43234a1e L |
5492 | |
5493 | /* Check if specified broadcast is supported in this instruction, | |
4a1b91ea | 5494 | and its broadcast bytes match the memory operand. */ |
32546502 | 5495 | op = i.broadcast->operand; |
8e6e0792 | 5496 | if (!t->opcode_modifier.broadcast |
c48dadc9 | 5497 | || !(i.flags[op] & Operand_Mem) |
c39e5b26 | 5498 | || (!i.types[op].bitfield.unspecified |
4a1b91ea | 5499 | && !match_broadcast_size (t, op))) |
43234a1e L |
5500 | { |
5501 | bad_broadcast: | |
5502 | i.error = unsupported_broadcast; | |
5503 | return 1; | |
5504 | } | |
8e6e0792 | 5505 | |
4a1b91ea L |
5506 | i.broadcast->bytes = ((1 << (t->opcode_modifier.broadcast - 1)) |
5507 | * i.broadcast->type); | |
8e6e0792 | 5508 | operand_type_set (&type, 0); |
4a1b91ea | 5509 | switch (i.broadcast->bytes) |
8e6e0792 | 5510 | { |
4a1b91ea L |
5511 | case 2: |
5512 | type.bitfield.word = 1; | |
5513 | break; | |
5514 | case 4: | |
5515 | type.bitfield.dword = 1; | |
5516 | break; | |
8e6e0792 JB |
5517 | case 8: |
5518 | type.bitfield.qword = 1; | |
5519 | break; | |
5520 | case 16: | |
5521 | type.bitfield.xmmword = 1; | |
5522 | break; | |
5523 | case 32: | |
5524 | type.bitfield.ymmword = 1; | |
5525 | break; | |
5526 | case 64: | |
5527 | type.bitfield.zmmword = 1; | |
5528 | break; | |
5529 | default: | |
5530 | goto bad_broadcast; | |
5531 | } | |
5532 | ||
5533 | overlap = operand_type_and (type, t->operand_types[op]); | |
5534 | if (operand_type_all_zero (&overlap)) | |
5535 | goto bad_broadcast; | |
5536 | ||
5537 | if (t->opcode_modifier.checkregsize) | |
5538 | { | |
5539 | unsigned int j; | |
5540 | ||
e2195274 | 5541 | type.bitfield.baseindex = 1; |
8e6e0792 JB |
5542 | for (j = 0; j < i.operands; ++j) |
5543 | { | |
5544 | if (j != op | |
5545 | && !operand_type_register_match(i.types[j], | |
5546 | t->operand_types[j], | |
5547 | type, | |
5548 | t->operand_types[op])) | |
5549 | goto bad_broadcast; | |
5550 | } | |
5551 | } | |
43234a1e L |
5552 | } |
5553 | /* If broadcast is supported in this instruction, we need to check if | |
5554 | operand of one-element size isn't specified without broadcast. */ | |
5555 | else if (t->opcode_modifier.broadcast && i.mem_operands) | |
5556 | { | |
5557 | /* Find memory operand. */ | |
5558 | for (op = 0; op < i.operands; op++) | |
8dc0818e | 5559 | if (i.flags[op] & Operand_Mem) |
43234a1e L |
5560 | break; |
5561 | gas_assert (op < i.operands); | |
5562 | /* Check size of the memory operand. */ | |
4a1b91ea | 5563 | if (match_broadcast_size (t, op)) |
43234a1e L |
5564 | { |
5565 | i.error = broadcast_needed; | |
5566 | return 1; | |
5567 | } | |
5568 | } | |
c39e5b26 JB |
5569 | else |
5570 | op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */ | |
43234a1e L |
5571 | |
5572 | /* Check if requested masking is supported. */ | |
ae2387fe | 5573 | if (i.mask) |
43234a1e | 5574 | { |
ae2387fe JB |
5575 | switch (t->opcode_modifier.masking) |
5576 | { | |
5577 | case BOTH_MASKING: | |
5578 | break; | |
5579 | case MERGING_MASKING: | |
5580 | if (i.mask->zeroing) | |
5581 | { | |
5582 | case 0: | |
5583 | i.error = unsupported_masking; | |
5584 | return 1; | |
5585 | } | |
5586 | break; | |
5587 | case DYNAMIC_MASKING: | |
5588 | /* Memory destinations allow only merging masking. */ | |
5589 | if (i.mask->zeroing && i.mem_operands) | |
5590 | { | |
5591 | /* Find memory operand. */ | |
5592 | for (op = 0; op < i.operands; op++) | |
c48dadc9 | 5593 | if (i.flags[op] & Operand_Mem) |
ae2387fe JB |
5594 | break; |
5595 | gas_assert (op < i.operands); | |
5596 | if (op == i.operands - 1) | |
5597 | { | |
5598 | i.error = unsupported_masking; | |
5599 | return 1; | |
5600 | } | |
5601 | } | |
5602 | break; | |
5603 | default: | |
5604 | abort (); | |
5605 | } | |
43234a1e L |
5606 | } |
5607 | ||
5608 | /* Check if masking is applied to dest operand. */ | |
5609 | if (i.mask && (i.mask->operand != (int) (i.operands - 1))) | |
5610 | { | |
5611 | i.error = mask_not_on_destination; | |
5612 | return 1; | |
5613 | } | |
5614 | ||
43234a1e L |
5615 | /* Check RC/SAE. */ |
5616 | if (i.rounding) | |
5617 | { | |
a80195f1 JB |
5618 | if (!t->opcode_modifier.sae |
5619 | || (i.rounding->type != saeonly && !t->opcode_modifier.staticrounding)) | |
43234a1e L |
5620 | { |
5621 | i.error = unsupported_rc_sae; | |
5622 | return 1; | |
5623 | } | |
5624 | /* If the instruction has several immediate operands and one of | |
5625 | them is rounding, the rounding operand should be the last | |
5626 | immediate operand. */ | |
5627 | if (i.imm_operands > 1 | |
5628 | && i.rounding->operand != (int) (i.imm_operands - 1)) | |
7bab8ab5 | 5629 | { |
43234a1e | 5630 | i.error = rc_sae_operand_not_last_imm; |
7bab8ab5 JB |
5631 | return 1; |
5632 | } | |
6c30d220 L |
5633 | } |
5634 | ||
43234a1e | 5635 | /* Check vector Disp8 operand. */ |
b5014f7a JB |
5636 | if (t->opcode_modifier.disp8memshift |
5637 | && i.disp_encoding != disp_encoding_32bit) | |
43234a1e L |
5638 | { |
5639 | if (i.broadcast) | |
4a1b91ea | 5640 | i.memshift = t->opcode_modifier.broadcast - 1; |
7091c612 | 5641 | else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL) |
43234a1e | 5642 | i.memshift = t->opcode_modifier.disp8memshift; |
7091c612 JB |
5643 | else |
5644 | { | |
5645 | const i386_operand_type *type = NULL; | |
5646 | ||
5647 | i.memshift = 0; | |
5648 | for (op = 0; op < i.operands; op++) | |
8dc0818e | 5649 | if (i.flags[op] & Operand_Mem) |
7091c612 | 5650 | { |
4174bfff JB |
5651 | if (t->opcode_modifier.evex == EVEXLIG) |
5652 | i.memshift = 2 + (i.suffix == QWORD_MNEM_SUFFIX); | |
5653 | else if (t->operand_types[op].bitfield.xmmword | |
5654 | + t->operand_types[op].bitfield.ymmword | |
5655 | + t->operand_types[op].bitfield.zmmword <= 1) | |
7091c612 JB |
5656 | type = &t->operand_types[op]; |
5657 | else if (!i.types[op].bitfield.unspecified) | |
5658 | type = &i.types[op]; | |
5659 | } | |
3528c362 | 5660 | else if (i.types[op].bitfield.class == RegSIMD |
4174bfff | 5661 | && t->opcode_modifier.evex != EVEXLIG) |
7091c612 JB |
5662 | { |
5663 | if (i.types[op].bitfield.zmmword) | |
5664 | i.memshift = 6; | |
5665 | else if (i.types[op].bitfield.ymmword && i.memshift < 5) | |
5666 | i.memshift = 5; | |
5667 | else if (i.types[op].bitfield.xmmword && i.memshift < 4) | |
5668 | i.memshift = 4; | |
5669 | } | |
5670 | ||
5671 | if (type) | |
5672 | { | |
5673 | if (type->bitfield.zmmword) | |
5674 | i.memshift = 6; | |
5675 | else if (type->bitfield.ymmword) | |
5676 | i.memshift = 5; | |
5677 | else if (type->bitfield.xmmword) | |
5678 | i.memshift = 4; | |
5679 | } | |
5680 | ||
5681 | /* For the check in fits_in_disp8(). */ | |
5682 | if (i.memshift == 0) | |
5683 | i.memshift = -1; | |
5684 | } | |
43234a1e L |
5685 | |
5686 | for (op = 0; op < i.operands; op++) | |
5687 | if (operand_type_check (i.types[op], disp) | |
5688 | && i.op[op].disps->X_op == O_constant) | |
5689 | { | |
b5014f7a | 5690 | if (fits_in_disp8 (i.op[op].disps->X_add_number)) |
43234a1e | 5691 | { |
b5014f7a JB |
5692 | i.types[op].bitfield.disp8 = 1; |
5693 | return 0; | |
43234a1e | 5694 | } |
b5014f7a | 5695 | i.types[op].bitfield.disp8 = 0; |
43234a1e L |
5696 | } |
5697 | } | |
b5014f7a JB |
5698 | |
5699 | i.memshift = 0; | |
43234a1e | 5700 | |
6c30d220 L |
5701 | return 0; |
5702 | } | |
5703 | ||
43f3e2ee | 5704 | /* Check if operands are valid for the instruction. Update VEX |
a683cc34 SP |
5705 | operand types. */ |
5706 | ||
5707 | static int | |
5708 | VEX_check_operands (const insn_template *t) | |
5709 | { | |
86fa6981 | 5710 | if (i.vec_encoding == vex_encoding_evex) |
43234a1e | 5711 | { |
86fa6981 | 5712 | /* This instruction must be encoded with EVEX prefix. */ |
e771e7c9 | 5713 | if (!is_evex_encoding (t)) |
86fa6981 L |
5714 | { |
5715 | i.error = unsupported; | |
5716 | return 1; | |
5717 | } | |
5718 | return 0; | |
43234a1e L |
5719 | } |
5720 | ||
a683cc34 | 5721 | if (!t->opcode_modifier.vex) |
86fa6981 L |
5722 | { |
5723 | /* This instruction template doesn't have VEX prefix. */ | |
5724 | if (i.vec_encoding != vex_encoding_default) | |
5725 | { | |
5726 | i.error = unsupported; | |
5727 | return 1; | |
5728 | } | |
5729 | return 0; | |
5730 | } | |
a683cc34 | 5731 | |
9d3bf266 JB |
5732 | /* Check the special Imm4 cases; must be the first operand. */ |
5733 | if (t->cpu_flags.bitfield.cpuxop && t->operands == 5) | |
a683cc34 SP |
5734 | { |
5735 | if (i.op[0].imms->X_op != O_constant | |
5736 | || !fits_in_imm4 (i.op[0].imms->X_add_number)) | |
891edac4 | 5737 | { |
a65babc9 | 5738 | i.error = bad_imm4; |
891edac4 L |
5739 | return 1; |
5740 | } | |
a683cc34 | 5741 | |
9d3bf266 JB |
5742 | /* Turn off Imm<N> so that update_imm won't complain. */ |
5743 | operand_type_set (&i.types[0], 0); | |
a683cc34 SP |
5744 | } |
5745 | ||
5746 | return 0; | |
5747 | } | |
5748 | ||
d3ce72d0 | 5749 | static const insn_template * |
83b16ac6 | 5750 | match_template (char mnem_suffix) |
29b0f896 AM |
5751 | { |
5752 | /* Points to template once we've found it. */ | |
d3ce72d0 | 5753 | const insn_template *t; |
40fb9820 | 5754 | i386_operand_type overlap0, overlap1, overlap2, overlap3; |
c0f3af97 | 5755 | i386_operand_type overlap4; |
29b0f896 | 5756 | unsigned int found_reverse_match; |
dc2be329 | 5757 | i386_opcode_modifier suffix_check; |
40fb9820 | 5758 | i386_operand_type operand_types [MAX_OPERANDS]; |
539e75ad | 5759 | int addr_prefix_disp; |
45a4bb20 | 5760 | unsigned int j, size_match, check_register; |
5614d22c | 5761 | enum i386_error specific_error = 0; |
29b0f896 | 5762 | |
c0f3af97 L |
5763 | #if MAX_OPERANDS != 5 |
5764 | # error "MAX_OPERANDS must be 5." | |
f48ff2ae L |
5765 | #endif |
5766 | ||
29b0f896 | 5767 | found_reverse_match = 0; |
539e75ad | 5768 | addr_prefix_disp = -1; |
40fb9820 | 5769 | |
dc2be329 | 5770 | /* Prepare for mnemonic suffix check. */ |
40fb9820 | 5771 | memset (&suffix_check, 0, sizeof (suffix_check)); |
dc2be329 L |
5772 | switch (mnem_suffix) |
5773 | { | |
5774 | case BYTE_MNEM_SUFFIX: | |
5775 | suffix_check.no_bsuf = 1; | |
5776 | break; | |
5777 | case WORD_MNEM_SUFFIX: | |
5778 | suffix_check.no_wsuf = 1; | |
5779 | break; | |
5780 | case SHORT_MNEM_SUFFIX: | |
5781 | suffix_check.no_ssuf = 1; | |
5782 | break; | |
5783 | case LONG_MNEM_SUFFIX: | |
5784 | suffix_check.no_lsuf = 1; | |
5785 | break; | |
5786 | case QWORD_MNEM_SUFFIX: | |
5787 | suffix_check.no_qsuf = 1; | |
5788 | break; | |
5789 | default: | |
5790 | /* NB: In Intel syntax, normally we can check for memory operand | |
5791 | size when there is no mnemonic suffix. But jmp and call have | |
5792 | 2 different encodings with Dword memory operand size, one with | |
5793 | No_ldSuf and the other without. i.suffix is set to | |
5794 | LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */ | |
5795 | if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX) | |
5796 | suffix_check.no_ldsuf = 1; | |
83b16ac6 JB |
5797 | } |
5798 | ||
01559ecc L |
5799 | /* Must have right number of operands. */ |
5800 | i.error = number_of_operands_mismatch; | |
5801 | ||
45aa61fe | 5802 | for (t = current_templates->start; t < current_templates->end; t++) |
29b0f896 | 5803 | { |
539e75ad | 5804 | addr_prefix_disp = -1; |
dbbc8b7e | 5805 | found_reverse_match = 0; |
539e75ad | 5806 | |
29b0f896 AM |
5807 | if (i.operands != t->operands) |
5808 | continue; | |
5809 | ||
50aecf8c | 5810 | /* Check processor support. */ |
a65babc9 | 5811 | i.error = unsupported; |
45a4bb20 | 5812 | if (cpu_flags_match (t) != CPU_FLAGS_PERFECT_MATCH) |
50aecf8c L |
5813 | continue; |
5814 | ||
e1d4d893 | 5815 | /* Check AT&T mnemonic. */ |
a65babc9 | 5816 | i.error = unsupported_with_intel_mnemonic; |
e1d4d893 | 5817 | if (intel_mnemonic && t->opcode_modifier.attmnemonic) |
1efbbeb4 L |
5818 | continue; |
5819 | ||
4b5aaf5f | 5820 | /* Check AT&T/Intel syntax. */ |
a65babc9 | 5821 | i.error = unsupported_syntax; |
5c07affc | 5822 | if ((intel_syntax && t->opcode_modifier.attsyntax) |
4b5aaf5f | 5823 | || (!intel_syntax && t->opcode_modifier.intelsyntax)) |
1efbbeb4 L |
5824 | continue; |
5825 | ||
4b5aaf5f L |
5826 | /* Check Intel64/AMD64 ISA. */ |
5827 | switch (isa64) | |
5828 | { | |
5829 | default: | |
5830 | /* Default: Don't accept Intel64. */ | |
5831 | if (t->opcode_modifier.isa64 == INTEL64) | |
5832 | continue; | |
5833 | break; | |
5834 | case amd64: | |
5835 | /* -mamd64: Don't accept Intel64 and Intel64 only. */ | |
5836 | if (t->opcode_modifier.isa64 >= INTEL64) | |
5837 | continue; | |
5838 | break; | |
5839 | case intel64: | |
5840 | /* -mintel64: Don't accept AMD64. */ | |
5990e377 | 5841 | if (t->opcode_modifier.isa64 == AMD64 && flag_code == CODE_64BIT) |
4b5aaf5f L |
5842 | continue; |
5843 | break; | |
5844 | } | |
5845 | ||
dc2be329 | 5846 | /* Check the suffix. */ |
a65babc9 | 5847 | i.error = invalid_instruction_suffix; |
dc2be329 L |
5848 | if ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf) |
5849 | || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf) | |
5850 | || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf) | |
5851 | || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf) | |
5852 | || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf) | |
5853 | || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)) | |
83b16ac6 | 5854 | continue; |
29b0f896 | 5855 | |
3ac21baa JB |
5856 | size_match = operand_size_match (t); |
5857 | if (!size_match) | |
7d5e4556 | 5858 | continue; |
539e75ad | 5859 | |
6f2f06be JB |
5860 | /* This is intentionally not |
5861 | ||
0cfa3eb3 | 5862 | if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE)) |
6f2f06be JB |
5863 | |
5864 | as the case of a missing * on the operand is accepted (perhaps with | |
5865 | a warning, issued further down). */ | |
0cfa3eb3 | 5866 | if (i.jumpabsolute && t->opcode_modifier.jump != JUMP_ABSOLUTE) |
6f2f06be JB |
5867 | { |
5868 | i.error = operand_type_mismatch; | |
5869 | continue; | |
5870 | } | |
5871 | ||
5c07affc L |
5872 | for (j = 0; j < MAX_OPERANDS; j++) |
5873 | operand_types[j] = t->operand_types[j]; | |
5874 | ||
45aa61fe AM |
5875 | /* In general, don't allow 64-bit operands in 32-bit mode. */ |
5876 | if (i.suffix == QWORD_MNEM_SUFFIX | |
5877 | && flag_code != CODE_64BIT | |
5878 | && (intel_syntax | |
40fb9820 | 5879 | ? (!t->opcode_modifier.ignoresize |
625cbd7a | 5880 | && !t->opcode_modifier.broadcast |
45aa61fe AM |
5881 | && !intel_float_operand (t->name)) |
5882 | : intel_float_operand (t->name) != 2) | |
3528c362 JB |
5883 | && ((operand_types[0].bitfield.class != RegMMX |
5884 | && operand_types[0].bitfield.class != RegSIMD) | |
5885 | || (operand_types[t->operands > 1].bitfield.class != RegMMX | |
5886 | && operand_types[t->operands > 1].bitfield.class != RegSIMD)) | |
45aa61fe AM |
5887 | && (t->base_opcode != 0x0fc7 |
5888 | || t->extension_opcode != 1 /* cmpxchg8b */)) | |
5889 | continue; | |
5890 | ||
192dc9c6 JB |
5891 | /* In general, don't allow 32-bit operands on pre-386. */ |
5892 | else if (i.suffix == LONG_MNEM_SUFFIX | |
5893 | && !cpu_arch_flags.bitfield.cpui386 | |
5894 | && (intel_syntax | |
5895 | ? (!t->opcode_modifier.ignoresize | |
5896 | && !intel_float_operand (t->name)) | |
5897 | : intel_float_operand (t->name) != 2) | |
3528c362 JB |
5898 | && ((operand_types[0].bitfield.class != RegMMX |
5899 | && operand_types[0].bitfield.class != RegSIMD) | |
5900 | || (operand_types[t->operands > 1].bitfield.class != RegMMX | |
5901 | && operand_types[t->operands > 1].bitfield.class | |
5902 | != RegSIMD))) | |
192dc9c6 JB |
5903 | continue; |
5904 | ||
29b0f896 | 5905 | /* Do not verify operands when there are none. */ |
50aecf8c | 5906 | else |
29b0f896 | 5907 | { |
c6fb90c8 | 5908 | if (!t->operands) |
2dbab7d5 L |
5909 | /* We've found a match; break out of loop. */ |
5910 | break; | |
29b0f896 | 5911 | } |
252b5132 | 5912 | |
48bcea9f JB |
5913 | if (!t->opcode_modifier.jump |
5914 | || t->opcode_modifier.jump == JUMP_ABSOLUTE) | |
5915 | { | |
5916 | /* There should be only one Disp operand. */ | |
5917 | for (j = 0; j < MAX_OPERANDS; j++) | |
5918 | if (operand_type_check (operand_types[j], disp)) | |
539e75ad | 5919 | break; |
48bcea9f JB |
5920 | if (j < MAX_OPERANDS) |
5921 | { | |
5922 | bfd_boolean override = (i.prefix[ADDR_PREFIX] != 0); | |
5923 | ||
5924 | addr_prefix_disp = j; | |
5925 | ||
5926 | /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16 | |
5927 | operand into Disp32/Disp32/Disp16/Disp32 operand. */ | |
5928 | switch (flag_code) | |
40fb9820 | 5929 | { |
48bcea9f JB |
5930 | case CODE_16BIT: |
5931 | override = !override; | |
5932 | /* Fall through. */ | |
5933 | case CODE_32BIT: | |
5934 | if (operand_types[j].bitfield.disp32 | |
5935 | && operand_types[j].bitfield.disp16) | |
40fb9820 | 5936 | { |
48bcea9f JB |
5937 | operand_types[j].bitfield.disp16 = override; |
5938 | operand_types[j].bitfield.disp32 = !override; | |
40fb9820 | 5939 | } |
48bcea9f JB |
5940 | operand_types[j].bitfield.disp32s = 0; |
5941 | operand_types[j].bitfield.disp64 = 0; | |
5942 | break; | |
5943 | ||
5944 | case CODE_64BIT: | |
5945 | if (operand_types[j].bitfield.disp32s | |
5946 | || operand_types[j].bitfield.disp64) | |
40fb9820 | 5947 | { |
48bcea9f JB |
5948 | operand_types[j].bitfield.disp64 &= !override; |
5949 | operand_types[j].bitfield.disp32s &= !override; | |
5950 | operand_types[j].bitfield.disp32 = override; | |
40fb9820 | 5951 | } |
48bcea9f JB |
5952 | operand_types[j].bitfield.disp16 = 0; |
5953 | break; | |
40fb9820 | 5954 | } |
539e75ad | 5955 | } |
48bcea9f | 5956 | } |
539e75ad | 5957 | |
02a86693 L |
5958 | /* Force 0x8b encoding for "mov foo@GOT, %eax". */ |
5959 | if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0) | |
5960 | continue; | |
5961 | ||
56ffb741 | 5962 | /* We check register size if needed. */ |
e2195274 JB |
5963 | if (t->opcode_modifier.checkregsize) |
5964 | { | |
5965 | check_register = (1 << t->operands) - 1; | |
5966 | if (i.broadcast) | |
5967 | check_register &= ~(1 << i.broadcast->operand); | |
5968 | } | |
5969 | else | |
5970 | check_register = 0; | |
5971 | ||
c6fb90c8 | 5972 | overlap0 = operand_type_and (i.types[0], operand_types[0]); |
29b0f896 AM |
5973 | switch (t->operands) |
5974 | { | |
5975 | case 1: | |
40fb9820 | 5976 | if (!operand_type_match (overlap0, i.types[0])) |
29b0f896 AM |
5977 | continue; |
5978 | break; | |
5979 | case 2: | |
33eaf5de | 5980 | /* xchg %eax, %eax is a special case. It is an alias for nop |
8b38ad71 L |
5981 | only in 32bit mode and we can use opcode 0x90. In 64bit |
5982 | mode, we can't use 0x90 for xchg %eax, %eax since it should | |
5983 | zero-extend %eax to %rax. */ | |
5984 | if (flag_code == CODE_64BIT | |
5985 | && t->base_opcode == 0x90 | |
75e5731b JB |
5986 | && i.types[0].bitfield.instance == Accum |
5987 | && i.types[0].bitfield.dword | |
5988 | && i.types[1].bitfield.instance == Accum | |
5989 | && i.types[1].bitfield.dword) | |
8b38ad71 | 5990 | continue; |
1212781b JB |
5991 | /* xrelease mov %eax, <disp> is another special case. It must not |
5992 | match the accumulator-only encoding of mov. */ | |
5993 | if (flag_code != CODE_64BIT | |
5994 | && i.hle_prefix | |
5995 | && t->base_opcode == 0xa0 | |
75e5731b | 5996 | && i.types[0].bitfield.instance == Accum |
8dc0818e | 5997 | && (i.flags[1] & Operand_Mem)) |
1212781b | 5998 | continue; |
f5eb1d70 JB |
5999 | /* Fall through. */ |
6000 | ||
6001 | case 3: | |
3ac21baa JB |
6002 | if (!(size_match & MATCH_STRAIGHT)) |
6003 | goto check_reverse; | |
64c49ab3 JB |
6004 | /* Reverse direction of operands if swapping is possible in the first |
6005 | place (operands need to be symmetric) and | |
6006 | - the load form is requested, and the template is a store form, | |
6007 | - the store form is requested, and the template is a load form, | |
6008 | - the non-default (swapped) form is requested. */ | |
6009 | overlap1 = operand_type_and (operand_types[0], operand_types[1]); | |
f5eb1d70 | 6010 | if (t->opcode_modifier.d && i.reg_operands == i.operands |
64c49ab3 JB |
6011 | && !operand_type_all_zero (&overlap1)) |
6012 | switch (i.dir_encoding) | |
6013 | { | |
6014 | case dir_encoding_load: | |
6015 | if (operand_type_check (operand_types[i.operands - 1], anymem) | |
dfd69174 | 6016 | || t->opcode_modifier.regmem) |
64c49ab3 JB |
6017 | goto check_reverse; |
6018 | break; | |
6019 | ||
6020 | case dir_encoding_store: | |
6021 | if (!operand_type_check (operand_types[i.operands - 1], anymem) | |
dfd69174 | 6022 | && !t->opcode_modifier.regmem) |
64c49ab3 JB |
6023 | goto check_reverse; |
6024 | break; | |
6025 | ||
6026 | case dir_encoding_swap: | |
6027 | goto check_reverse; | |
6028 | ||
6029 | case dir_encoding_default: | |
6030 | break; | |
6031 | } | |
86fa6981 | 6032 | /* If we want store form, we skip the current load. */ |
64c49ab3 JB |
6033 | if ((i.dir_encoding == dir_encoding_store |
6034 | || i.dir_encoding == dir_encoding_swap) | |
86fa6981 L |
6035 | && i.mem_operands == 0 |
6036 | && t->opcode_modifier.load) | |
fa99fab2 | 6037 | continue; |
1a0670f3 | 6038 | /* Fall through. */ |
f48ff2ae | 6039 | case 4: |
c0f3af97 | 6040 | case 5: |
c6fb90c8 | 6041 | overlap1 = operand_type_and (i.types[1], operand_types[1]); |
40fb9820 L |
6042 | if (!operand_type_match (overlap0, i.types[0]) |
6043 | || !operand_type_match (overlap1, i.types[1]) | |
e2195274 | 6044 | || ((check_register & 3) == 3 |
dc821c5f | 6045 | && !operand_type_register_match (i.types[0], |
40fb9820 | 6046 | operand_types[0], |
dc821c5f | 6047 | i.types[1], |
40fb9820 | 6048 | operand_types[1]))) |
29b0f896 AM |
6049 | { |
6050 | /* Check if other direction is valid ... */ | |
38e314eb | 6051 | if (!t->opcode_modifier.d) |
29b0f896 AM |
6052 | continue; |
6053 | ||
dc1e8a47 | 6054 | check_reverse: |
3ac21baa JB |
6055 | if (!(size_match & MATCH_REVERSE)) |
6056 | continue; | |
29b0f896 | 6057 | /* Try reversing direction of operands. */ |
f5eb1d70 JB |
6058 | overlap0 = operand_type_and (i.types[0], operand_types[i.operands - 1]); |
6059 | overlap1 = operand_type_and (i.types[i.operands - 1], operand_types[0]); | |
40fb9820 | 6060 | if (!operand_type_match (overlap0, i.types[0]) |
f5eb1d70 | 6061 | || !operand_type_match (overlap1, i.types[i.operands - 1]) |
45664ddb | 6062 | || (check_register |
dc821c5f | 6063 | && !operand_type_register_match (i.types[0], |
f5eb1d70 JB |
6064 | operand_types[i.operands - 1], |
6065 | i.types[i.operands - 1], | |
45664ddb | 6066 | operand_types[0]))) |
29b0f896 AM |
6067 | { |
6068 | /* Does not match either direction. */ | |
6069 | continue; | |
6070 | } | |
38e314eb | 6071 | /* found_reverse_match holds which of D or FloatR |
29b0f896 | 6072 | we've found. */ |
38e314eb JB |
6073 | if (!t->opcode_modifier.d) |
6074 | found_reverse_match = 0; | |
6075 | else if (operand_types[0].bitfield.tbyte) | |
8a2ed489 | 6076 | found_reverse_match = Opcode_FloatD; |
dbbc8b7e | 6077 | else if (operand_types[0].bitfield.xmmword |
f5eb1d70 | 6078 | || operand_types[i.operands - 1].bitfield.xmmword |
3528c362 JB |
6079 | || operand_types[0].bitfield.class == RegMMX |
6080 | || operand_types[i.operands - 1].bitfield.class == RegMMX | |
dbbc8b7e JB |
6081 | || is_any_vex_encoding(t)) |
6082 | found_reverse_match = (t->base_opcode & 0xee) != 0x6e | |
6083 | ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD; | |
8a2ed489 | 6084 | else |
38e314eb | 6085 | found_reverse_match = Opcode_D; |
40fb9820 | 6086 | if (t->opcode_modifier.floatr) |
8a2ed489 | 6087 | found_reverse_match |= Opcode_FloatR; |
29b0f896 | 6088 | } |
f48ff2ae | 6089 | else |
29b0f896 | 6090 | { |
f48ff2ae | 6091 | /* Found a forward 2 operand match here. */ |
d1cbb4db L |
6092 | switch (t->operands) |
6093 | { | |
c0f3af97 L |
6094 | case 5: |
6095 | overlap4 = operand_type_and (i.types[4], | |
6096 | operand_types[4]); | |
1a0670f3 | 6097 | /* Fall through. */ |
d1cbb4db | 6098 | case 4: |
c6fb90c8 L |
6099 | overlap3 = operand_type_and (i.types[3], |
6100 | operand_types[3]); | |
1a0670f3 | 6101 | /* Fall through. */ |
d1cbb4db | 6102 | case 3: |
c6fb90c8 L |
6103 | overlap2 = operand_type_and (i.types[2], |
6104 | operand_types[2]); | |
d1cbb4db L |
6105 | break; |
6106 | } | |
29b0f896 | 6107 | |
f48ff2ae L |
6108 | switch (t->operands) |
6109 | { | |
c0f3af97 L |
6110 | case 5: |
6111 | if (!operand_type_match (overlap4, i.types[4]) | |
dc821c5f | 6112 | || !operand_type_register_match (i.types[3], |
c0f3af97 | 6113 | operand_types[3], |
c0f3af97 L |
6114 | i.types[4], |
6115 | operand_types[4])) | |
6116 | continue; | |
1a0670f3 | 6117 | /* Fall through. */ |
f48ff2ae | 6118 | case 4: |
40fb9820 | 6119 | if (!operand_type_match (overlap3, i.types[3]) |
e2195274 JB |
6120 | || ((check_register & 0xa) == 0xa |
6121 | && !operand_type_register_match (i.types[1], | |
f7768225 JB |
6122 | operand_types[1], |
6123 | i.types[3], | |
e2195274 JB |
6124 | operand_types[3])) |
6125 | || ((check_register & 0xc) == 0xc | |
6126 | && !operand_type_register_match (i.types[2], | |
6127 | operand_types[2], | |
6128 | i.types[3], | |
6129 | operand_types[3]))) | |
f48ff2ae | 6130 | continue; |
1a0670f3 | 6131 | /* Fall through. */ |
f48ff2ae L |
6132 | case 3: |
6133 | /* Here we make use of the fact that there are no | |
23e42951 | 6134 | reverse match 3 operand instructions. */ |
40fb9820 | 6135 | if (!operand_type_match (overlap2, i.types[2]) |
e2195274 JB |
6136 | || ((check_register & 5) == 5 |
6137 | && !operand_type_register_match (i.types[0], | |
23e42951 JB |
6138 | operand_types[0], |
6139 | i.types[2], | |
e2195274 JB |
6140 | operand_types[2])) |
6141 | || ((check_register & 6) == 6 | |
6142 | && !operand_type_register_match (i.types[1], | |
6143 | operand_types[1], | |
6144 | i.types[2], | |
6145 | operand_types[2]))) | |
f48ff2ae L |
6146 | continue; |
6147 | break; | |
6148 | } | |
29b0f896 | 6149 | } |
f48ff2ae | 6150 | /* Found either forward/reverse 2, 3 or 4 operand match here: |
29b0f896 AM |
6151 | slip through to break. */ |
6152 | } | |
c0f3af97 | 6153 | |
5614d22c JB |
6154 | /* Check if vector and VEX operands are valid. */ |
6155 | if (check_VecOperands (t) || VEX_check_operands (t)) | |
6156 | { | |
6157 | specific_error = i.error; | |
6158 | continue; | |
6159 | } | |
a683cc34 | 6160 | |
29b0f896 AM |
6161 | /* We've found a match; break out of loop. */ |
6162 | break; | |
6163 | } | |
6164 | ||
6165 | if (t == current_templates->end) | |
6166 | { | |
6167 | /* We found no match. */ | |
a65babc9 | 6168 | const char *err_msg; |
5614d22c | 6169 | switch (specific_error ? specific_error : i.error) |
a65babc9 L |
6170 | { |
6171 | default: | |
6172 | abort (); | |
86e026a4 | 6173 | case operand_size_mismatch: |
a65babc9 L |
6174 | err_msg = _("operand size mismatch"); |
6175 | break; | |
6176 | case operand_type_mismatch: | |
6177 | err_msg = _("operand type mismatch"); | |
6178 | break; | |
6179 | case register_type_mismatch: | |
6180 | err_msg = _("register type mismatch"); | |
6181 | break; | |
6182 | case number_of_operands_mismatch: | |
6183 | err_msg = _("number of operands mismatch"); | |
6184 | break; | |
6185 | case invalid_instruction_suffix: | |
6186 | err_msg = _("invalid instruction suffix"); | |
6187 | break; | |
6188 | case bad_imm4: | |
4a2608e3 | 6189 | err_msg = _("constant doesn't fit in 4 bits"); |
a65babc9 | 6190 | break; |
a65babc9 L |
6191 | case unsupported_with_intel_mnemonic: |
6192 | err_msg = _("unsupported with Intel mnemonic"); | |
6193 | break; | |
6194 | case unsupported_syntax: | |
6195 | err_msg = _("unsupported syntax"); | |
6196 | break; | |
6197 | case unsupported: | |
35262a23 | 6198 | as_bad (_("unsupported instruction `%s'"), |
10efe3f6 L |
6199 | current_templates->start->name); |
6200 | return NULL; | |
6c30d220 L |
6201 | case invalid_vsib_address: |
6202 | err_msg = _("invalid VSIB address"); | |
6203 | break; | |
7bab8ab5 JB |
6204 | case invalid_vector_register_set: |
6205 | err_msg = _("mask, index, and destination registers must be distinct"); | |
6206 | break; | |
6c30d220 L |
6207 | case unsupported_vector_index_register: |
6208 | err_msg = _("unsupported vector index register"); | |
6209 | break; | |
43234a1e L |
6210 | case unsupported_broadcast: |
6211 | err_msg = _("unsupported broadcast"); | |
6212 | break; | |
43234a1e L |
6213 | case broadcast_needed: |
6214 | err_msg = _("broadcast is needed for operand of such type"); | |
6215 | break; | |
6216 | case unsupported_masking: | |
6217 | err_msg = _("unsupported masking"); | |
6218 | break; | |
6219 | case mask_not_on_destination: | |
6220 | err_msg = _("mask not on destination operand"); | |
6221 | break; | |
6222 | case no_default_mask: | |
6223 | err_msg = _("default mask isn't allowed"); | |
6224 | break; | |
6225 | case unsupported_rc_sae: | |
6226 | err_msg = _("unsupported static rounding/sae"); | |
6227 | break; | |
6228 | case rc_sae_operand_not_last_imm: | |
6229 | if (intel_syntax) | |
6230 | err_msg = _("RC/SAE operand must precede immediate operands"); | |
6231 | else | |
6232 | err_msg = _("RC/SAE operand must follow immediate operands"); | |
6233 | break; | |
6234 | case invalid_register_operand: | |
6235 | err_msg = _("invalid register operand"); | |
6236 | break; | |
a65babc9 L |
6237 | } |
6238 | as_bad (_("%s for `%s'"), err_msg, | |
891edac4 | 6239 | current_templates->start->name); |
fa99fab2 | 6240 | return NULL; |
29b0f896 | 6241 | } |
252b5132 | 6242 | |
29b0f896 AM |
6243 | if (!quiet_warnings) |
6244 | { | |
6245 | if (!intel_syntax | |
0cfa3eb3 | 6246 | && (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))) |
6f2f06be | 6247 | as_warn (_("indirect %s without `*'"), t->name); |
29b0f896 | 6248 | |
40fb9820 L |
6249 | if (t->opcode_modifier.isprefix |
6250 | && t->opcode_modifier.ignoresize) | |
29b0f896 AM |
6251 | { |
6252 | /* Warn them that a data or address size prefix doesn't | |
6253 | affect assembly of the next line of code. */ | |
6254 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
6255 | } | |
6256 | } | |
6257 | ||
6258 | /* Copy the template we found. */ | |
6259 | i.tm = *t; | |
539e75ad L |
6260 | |
6261 | if (addr_prefix_disp != -1) | |
6262 | i.tm.operand_types[addr_prefix_disp] | |
6263 | = operand_types[addr_prefix_disp]; | |
6264 | ||
29b0f896 AM |
6265 | if (found_reverse_match) |
6266 | { | |
dfd69174 JB |
6267 | /* If we found a reverse match we must alter the opcode direction |
6268 | bit and clear/flip the regmem modifier one. found_reverse_match | |
6269 | holds bits to change (different for int & float insns). */ | |
29b0f896 AM |
6270 | |
6271 | i.tm.base_opcode ^= found_reverse_match; | |
6272 | ||
f5eb1d70 JB |
6273 | i.tm.operand_types[0] = operand_types[i.operands - 1]; |
6274 | i.tm.operand_types[i.operands - 1] = operand_types[0]; | |
dfd69174 JB |
6275 | |
6276 | /* Certain SIMD insns have their load forms specified in the opcode | |
6277 | table, and hence we need to _set_ RegMem instead of clearing it. | |
6278 | We need to avoid setting the bit though on insns like KMOVW. */ | |
6279 | i.tm.opcode_modifier.regmem | |
6280 | = i.tm.opcode_modifier.modrm && i.tm.opcode_modifier.d | |
6281 | && i.tm.operands > 2U - i.tm.opcode_modifier.sse2avx | |
6282 | && !i.tm.opcode_modifier.regmem; | |
29b0f896 AM |
6283 | } |
6284 | ||
fa99fab2 | 6285 | return t; |
29b0f896 AM |
6286 | } |
6287 | ||
6288 | static int | |
e3bb37b5 | 6289 | check_string (void) |
29b0f896 | 6290 | { |
51c8edf6 JB |
6291 | unsigned int es_op = i.tm.opcode_modifier.isstring - IS_STRING_ES_OP0; |
6292 | unsigned int op = i.tm.operand_types[0].bitfield.baseindex ? es_op : 0; | |
8dc0818e | 6293 | |
51c8edf6 | 6294 | if (i.seg[op] != NULL && i.seg[op] != &es) |
29b0f896 | 6295 | { |
51c8edf6 JB |
6296 | as_bad (_("`%s' operand %u must use `%ses' segment"), |
6297 | i.tm.name, | |
6298 | intel_syntax ? i.tm.operands - es_op : es_op + 1, | |
6299 | register_prefix); | |
6300 | return 0; | |
29b0f896 | 6301 | } |
51c8edf6 JB |
6302 | |
6303 | /* There's only ever one segment override allowed per instruction. | |
6304 | This instruction possibly has a legal segment override on the | |
6305 | second operand, so copy the segment to where non-string | |
6306 | instructions store it, allowing common code. */ | |
6307 | i.seg[op] = i.seg[1]; | |
6308 | ||
29b0f896 AM |
6309 | return 1; |
6310 | } | |
6311 | ||
6312 | static int | |
543613e9 | 6313 | process_suffix (void) |
29b0f896 AM |
6314 | { |
6315 | /* If matched instruction specifies an explicit instruction mnemonic | |
6316 | suffix, use it. */ | |
673fe0f0 | 6317 | if (i.tm.opcode_modifier.size == SIZE16) |
40fb9820 | 6318 | i.suffix = WORD_MNEM_SUFFIX; |
673fe0f0 | 6319 | else if (i.tm.opcode_modifier.size == SIZE32) |
40fb9820 | 6320 | i.suffix = LONG_MNEM_SUFFIX; |
673fe0f0 | 6321 | else if (i.tm.opcode_modifier.size == SIZE64) |
40fb9820 | 6322 | i.suffix = QWORD_MNEM_SUFFIX; |
13e600d0 | 6323 | else if (i.reg_operands |
c8f8eebc JB |
6324 | && (i.operands > 1 || i.types[0].bitfield.class == Reg) |
6325 | && !i.tm.opcode_modifier.addrprefixopreg) | |
29b0f896 | 6326 | { |
65fca059 JB |
6327 | unsigned int numop = i.operands; |
6328 | ||
6329 | /* movsx/movzx want only their source operand considered here, for the | |
6330 | ambiguity checking below. The suffix will be replaced afterwards | |
6331 | to represent the destination (register). */ | |
6332 | if (((i.tm.base_opcode | 8) == 0xfbe && i.tm.opcode_modifier.w) | |
6333 | || (i.tm.base_opcode == 0x63 && i.tm.cpu_flags.bitfield.cpu64)) | |
6334 | --i.operands; | |
6335 | ||
29b0f896 | 6336 | /* If there's no instruction mnemonic suffix we try to invent one |
13e600d0 | 6337 | based on GPR operands. */ |
29b0f896 AM |
6338 | if (!i.suffix) |
6339 | { | |
6340 | /* We take i.suffix from the last register operand specified, | |
6341 | Destination register type is more significant than source | |
381d071f L |
6342 | register type. crc32 in SSE4.2 prefers source register |
6343 | type. */ | |
1a035124 | 6344 | unsigned int op = i.tm.base_opcode != 0xf20f38f0 ? i.operands : 1; |
20592a94 | 6345 | |
1a035124 JB |
6346 | while (op--) |
6347 | if (i.tm.operand_types[op].bitfield.instance == InstanceNone | |
6348 | || i.tm.operand_types[op].bitfield.instance == Accum) | |
6349 | { | |
6350 | if (i.types[op].bitfield.class != Reg) | |
6351 | continue; | |
6352 | if (i.types[op].bitfield.byte) | |
6353 | i.suffix = BYTE_MNEM_SUFFIX; | |
6354 | else if (i.types[op].bitfield.word) | |
6355 | i.suffix = WORD_MNEM_SUFFIX; | |
6356 | else if (i.types[op].bitfield.dword) | |
6357 | i.suffix = LONG_MNEM_SUFFIX; | |
6358 | else if (i.types[op].bitfield.qword) | |
6359 | i.suffix = QWORD_MNEM_SUFFIX; | |
6360 | else | |
6361 | continue; | |
6362 | break; | |
6363 | } | |
65fca059 JB |
6364 | |
6365 | /* As an exception, movsx/movzx silently default to a byte source | |
6366 | in AT&T mode. */ | |
6367 | if ((i.tm.base_opcode | 8) == 0xfbe && i.tm.opcode_modifier.w | |
6368 | && !i.suffix && !intel_syntax) | |
6369 | i.suffix = BYTE_MNEM_SUFFIX; | |
29b0f896 AM |
6370 | } |
6371 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
6372 | { | |
2eb952a4 L |
6373 | if (intel_syntax |
6374 | && i.tm.opcode_modifier.ignoresize | |
6375 | && i.tm.opcode_modifier.no_bsuf) | |
6376 | i.suffix = 0; | |
6377 | else if (!check_byte_reg ()) | |
29b0f896 AM |
6378 | return 0; |
6379 | } | |
6380 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
6381 | { | |
2eb952a4 L |
6382 | if (intel_syntax |
6383 | && i.tm.opcode_modifier.ignoresize | |
9f123b91 JB |
6384 | && i.tm.opcode_modifier.no_lsuf |
6385 | && !i.tm.opcode_modifier.todword | |
6386 | && !i.tm.opcode_modifier.toqword) | |
2eb952a4 L |
6387 | i.suffix = 0; |
6388 | else if (!check_long_reg ()) | |
29b0f896 AM |
6389 | return 0; |
6390 | } | |
6391 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
6392 | { | |
955e1e6a L |
6393 | if (intel_syntax |
6394 | && i.tm.opcode_modifier.ignoresize | |
9f123b91 JB |
6395 | && i.tm.opcode_modifier.no_qsuf |
6396 | && !i.tm.opcode_modifier.todword | |
6397 | && !i.tm.opcode_modifier.toqword) | |
955e1e6a L |
6398 | i.suffix = 0; |
6399 | else if (!check_qword_reg ()) | |
29b0f896 AM |
6400 | return 0; |
6401 | } | |
6402 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
6403 | { | |
2eb952a4 L |
6404 | if (intel_syntax |
6405 | && i.tm.opcode_modifier.ignoresize | |
6406 | && i.tm.opcode_modifier.no_wsuf) | |
6407 | i.suffix = 0; | |
6408 | else if (!check_word_reg ()) | |
29b0f896 AM |
6409 | return 0; |
6410 | } | |
40fb9820 | 6411 | else if (intel_syntax && i.tm.opcode_modifier.ignoresize) |
29b0f896 AM |
6412 | /* Do nothing if the instruction is going to ignore the prefix. */ |
6413 | ; | |
6414 | else | |
6415 | abort (); | |
65fca059 JB |
6416 | |
6417 | /* Undo the movsx/movzx change done above. */ | |
6418 | i.operands = numop; | |
29b0f896 | 6419 | } |
62b3f548 | 6420 | else if (i.tm.opcode_modifier.defaultsize && !i.suffix) |
29b0f896 | 6421 | { |
13e600d0 JB |
6422 | i.suffix = stackop_size; |
6423 | if (stackop_size == LONG_MNEM_SUFFIX) | |
06f74c5c L |
6424 | { |
6425 | /* stackop_size is set to LONG_MNEM_SUFFIX for the | |
6426 | .code16gcc directive to support 16-bit mode with | |
6427 | 32-bit address. For IRET without a suffix, generate | |
6428 | 16-bit IRET (opcode 0xcf) to return from an interrupt | |
6429 | handler. */ | |
13e600d0 JB |
6430 | if (i.tm.base_opcode == 0xcf) |
6431 | { | |
6432 | i.suffix = WORD_MNEM_SUFFIX; | |
6433 | as_warn (_("generating 16-bit `iret' for .code16gcc directive")); | |
6434 | } | |
6435 | /* Warn about changed behavior for segment register push/pop. */ | |
6436 | else if ((i.tm.base_opcode | 1) == 0x07) | |
6437 | as_warn (_("generating 32-bit `%s', unlike earlier gas versions"), | |
6438 | i.tm.name); | |
06f74c5c | 6439 | } |
29b0f896 | 6440 | } |
c006a730 | 6441 | else if (!i.suffix |
0cfa3eb3 JB |
6442 | && (i.tm.opcode_modifier.jump == JUMP_ABSOLUTE |
6443 | || i.tm.opcode_modifier.jump == JUMP_BYTE | |
6444 | || i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT | |
64e74474 AM |
6445 | || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */ |
6446 | && i.tm.extension_opcode <= 3))) | |
9306ca4a JB |
6447 | { |
6448 | switch (flag_code) | |
6449 | { | |
6450 | case CODE_64BIT: | |
40fb9820 | 6451 | if (!i.tm.opcode_modifier.no_qsuf) |
9306ca4a JB |
6452 | { |
6453 | i.suffix = QWORD_MNEM_SUFFIX; | |
6454 | break; | |
6455 | } | |
1a0670f3 | 6456 | /* Fall through. */ |
9306ca4a | 6457 | case CODE_32BIT: |
40fb9820 | 6458 | if (!i.tm.opcode_modifier.no_lsuf) |
9306ca4a JB |
6459 | i.suffix = LONG_MNEM_SUFFIX; |
6460 | break; | |
6461 | case CODE_16BIT: | |
40fb9820 | 6462 | if (!i.tm.opcode_modifier.no_wsuf) |
9306ca4a JB |
6463 | i.suffix = WORD_MNEM_SUFFIX; |
6464 | break; | |
6465 | } | |
6466 | } | |
252b5132 | 6467 | |
c006a730 | 6468 | if (!i.suffix |
873494c8 JB |
6469 | && (!i.tm.opcode_modifier.defaultsize |
6470 | /* Also cover lret/retf/iret in 64-bit mode. */ | |
6471 | || (flag_code == CODE_64BIT | |
6472 | && !i.tm.opcode_modifier.no_lsuf | |
6473 | && !i.tm.opcode_modifier.no_qsuf)) | |
62b3f548 JB |
6474 | && !i.tm.opcode_modifier.ignoresize |
6475 | /* Accept FLDENV et al without suffix. */ | |
6476 | && (i.tm.opcode_modifier.no_ssuf || i.tm.opcode_modifier.floatmf)) | |
29b0f896 | 6477 | { |
6c0946d0 | 6478 | unsigned int suffixes, evex = 0; |
c006a730 JB |
6479 | |
6480 | suffixes = !i.tm.opcode_modifier.no_bsuf; | |
6481 | if (!i.tm.opcode_modifier.no_wsuf) | |
6482 | suffixes |= 1 << 1; | |
6483 | if (!i.tm.opcode_modifier.no_lsuf) | |
6484 | suffixes |= 1 << 2; | |
6485 | if (!i.tm.opcode_modifier.no_ldsuf) | |
6486 | suffixes |= 1 << 3; | |
6487 | if (!i.tm.opcode_modifier.no_ssuf) | |
6488 | suffixes |= 1 << 4; | |
6489 | if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf) | |
6490 | suffixes |= 1 << 5; | |
6491 | ||
6c0946d0 JB |
6492 | /* For [XYZ]MMWORD operands inspect operand sizes. While generally |
6493 | also suitable for AT&T syntax mode, it was requested that this be | |
6494 | restricted to just Intel syntax. */ | |
b9915cbc | 6495 | if (intel_syntax && is_any_vex_encoding (&i.tm) && !i.broadcast) |
6c0946d0 | 6496 | { |
b9915cbc | 6497 | unsigned int op; |
6c0946d0 | 6498 | |
b9915cbc | 6499 | for (op = 0; op < i.tm.operands; ++op) |
6c0946d0 | 6500 | { |
b9915cbc JB |
6501 | if (is_evex_encoding (&i.tm) |
6502 | && !cpu_arch_flags.bitfield.cpuavx512vl) | |
6c0946d0 | 6503 | { |
b9915cbc JB |
6504 | if (i.tm.operand_types[op].bitfield.ymmword) |
6505 | i.tm.operand_types[op].bitfield.xmmword = 0; | |
6506 | if (i.tm.operand_types[op].bitfield.zmmword) | |
6507 | i.tm.operand_types[op].bitfield.ymmword = 0; | |
6508 | if (!i.tm.opcode_modifier.evex | |
6509 | || i.tm.opcode_modifier.evex == EVEXDYN) | |
6510 | i.tm.opcode_modifier.evex = EVEX512; | |
6511 | } | |
6c0946d0 | 6512 | |
b9915cbc JB |
6513 | if (i.tm.operand_types[op].bitfield.xmmword |
6514 | + i.tm.operand_types[op].bitfield.ymmword | |
6515 | + i.tm.operand_types[op].bitfield.zmmword < 2) | |
6516 | continue; | |
6c0946d0 | 6517 | |
b9915cbc JB |
6518 | /* Any properly sized operand disambiguates the insn. */ |
6519 | if (i.types[op].bitfield.xmmword | |
6520 | || i.types[op].bitfield.ymmword | |
6521 | || i.types[op].bitfield.zmmword) | |
6522 | { | |
6523 | suffixes &= ~(7 << 6); | |
6524 | evex = 0; | |
6525 | break; | |
6526 | } | |
6c0946d0 | 6527 | |
b9915cbc JB |
6528 | if ((i.flags[op] & Operand_Mem) |
6529 | && i.tm.operand_types[op].bitfield.unspecified) | |
6530 | { | |
6531 | if (i.tm.operand_types[op].bitfield.xmmword) | |
6532 | suffixes |= 1 << 6; | |
6533 | if (i.tm.operand_types[op].bitfield.ymmword) | |
6534 | suffixes |= 1 << 7; | |
6535 | if (i.tm.operand_types[op].bitfield.zmmword) | |
6536 | suffixes |= 1 << 8; | |
6537 | if (is_evex_encoding (&i.tm)) | |
6538 | evex = EVEX512; | |
6c0946d0 JB |
6539 | } |
6540 | } | |
6541 | } | |
6542 | ||
6543 | /* Are multiple suffixes / operand sizes allowed? */ | |
c006a730 | 6544 | if (suffixes & (suffixes - 1)) |
9306ca4a | 6545 | { |
873494c8 JB |
6546 | if (intel_syntax |
6547 | && (!i.tm.opcode_modifier.defaultsize | |
6548 | || operand_check == check_error)) | |
9306ca4a | 6549 | { |
c006a730 | 6550 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); |
9306ca4a JB |
6551 | return 0; |
6552 | } | |
c006a730 | 6553 | if (operand_check == check_error) |
9306ca4a | 6554 | { |
c006a730 JB |
6555 | as_bad (_("no instruction mnemonic suffix given and " |
6556 | "no register operands; can't size `%s'"), i.tm.name); | |
9306ca4a JB |
6557 | return 0; |
6558 | } | |
c006a730 | 6559 | if (operand_check == check_warning) |
873494c8 JB |
6560 | as_warn (_("%s; using default for `%s'"), |
6561 | intel_syntax | |
6562 | ? _("ambiguous operand size") | |
6563 | : _("no instruction mnemonic suffix given and " | |
6564 | "no register operands"), | |
6565 | i.tm.name); | |
c006a730 JB |
6566 | |
6567 | if (i.tm.opcode_modifier.floatmf) | |
6568 | i.suffix = SHORT_MNEM_SUFFIX; | |
65fca059 JB |
6569 | else if ((i.tm.base_opcode | 8) == 0xfbe |
6570 | || (i.tm.base_opcode == 0x63 | |
6571 | && i.tm.cpu_flags.bitfield.cpu64)) | |
6572 | /* handled below */; | |
6c0946d0 JB |
6573 | else if (evex) |
6574 | i.tm.opcode_modifier.evex = evex; | |
c006a730 JB |
6575 | else if (flag_code == CODE_16BIT) |
6576 | i.suffix = WORD_MNEM_SUFFIX; | |
1a035124 | 6577 | else if (!i.tm.opcode_modifier.no_lsuf) |
c006a730 | 6578 | i.suffix = LONG_MNEM_SUFFIX; |
1a035124 JB |
6579 | else |
6580 | i.suffix = QWORD_MNEM_SUFFIX; | |
9306ca4a | 6581 | } |
29b0f896 | 6582 | } |
252b5132 | 6583 | |
65fca059 JB |
6584 | if ((i.tm.base_opcode | 8) == 0xfbe |
6585 | || (i.tm.base_opcode == 0x63 && i.tm.cpu_flags.bitfield.cpu64)) | |
6586 | { | |
6587 | /* In Intel syntax, movsx/movzx must have a "suffix" (checked above). | |
6588 | In AT&T syntax, if there is no suffix (warned about above), the default | |
6589 | will be byte extension. */ | |
6590 | if (i.tm.opcode_modifier.w && i.suffix && i.suffix != BYTE_MNEM_SUFFIX) | |
6591 | i.tm.base_opcode |= 1; | |
6592 | ||
6593 | /* For further processing, the suffix should represent the destination | |
6594 | (register). This is already the case when one was used with | |
6595 | mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was | |
6596 | no suffix to begin with. */ | |
6597 | if (i.tm.opcode_modifier.w || i.tm.base_opcode == 0x63 || !i.suffix) | |
6598 | { | |
6599 | if (i.types[1].bitfield.word) | |
6600 | i.suffix = WORD_MNEM_SUFFIX; | |
6601 | else if (i.types[1].bitfield.qword) | |
6602 | i.suffix = QWORD_MNEM_SUFFIX; | |
6603 | else | |
6604 | i.suffix = LONG_MNEM_SUFFIX; | |
6605 | ||
6606 | i.tm.opcode_modifier.w = 0; | |
6607 | } | |
6608 | } | |
6609 | ||
50128d0c JB |
6610 | if (!i.tm.opcode_modifier.modrm && i.reg_operands && i.tm.operands < 3) |
6611 | i.short_form = (i.tm.operand_types[0].bitfield.class == Reg) | |
6612 | != (i.tm.operand_types[1].bitfield.class == Reg); | |
6613 | ||
d2224064 JB |
6614 | /* Change the opcode based on the operand size given by i.suffix. */ |
6615 | switch (i.suffix) | |
29b0f896 | 6616 | { |
d2224064 JB |
6617 | /* Size floating point instruction. */ |
6618 | case LONG_MNEM_SUFFIX: | |
6619 | if (i.tm.opcode_modifier.floatmf) | |
6620 | { | |
6621 | i.tm.base_opcode ^= 4; | |
6622 | break; | |
6623 | } | |
6624 | /* fall through */ | |
6625 | case WORD_MNEM_SUFFIX: | |
6626 | case QWORD_MNEM_SUFFIX: | |
29b0f896 | 6627 | /* It's not a byte, select word/dword operation. */ |
40fb9820 | 6628 | if (i.tm.opcode_modifier.w) |
29b0f896 | 6629 | { |
50128d0c | 6630 | if (i.short_form) |
29b0f896 AM |
6631 | i.tm.base_opcode |= 8; |
6632 | else | |
6633 | i.tm.base_opcode |= 1; | |
6634 | } | |
d2224064 JB |
6635 | /* fall through */ |
6636 | case SHORT_MNEM_SUFFIX: | |
29b0f896 AM |
6637 | /* Now select between word & dword operations via the operand |
6638 | size prefix, except for instructions that will ignore this | |
6639 | prefix anyway. */ | |
c8f8eebc JB |
6640 | if (i.suffix != QWORD_MNEM_SUFFIX |
6641 | && !i.tm.opcode_modifier.ignoresize | |
6642 | && !i.tm.opcode_modifier.floatmf | |
6643 | && !is_any_vex_encoding (&i.tm) | |
6644 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) | |
6645 | || (flag_code == CODE_64BIT | |
6646 | && i.tm.opcode_modifier.jump == JUMP_BYTE))) | |
24eab124 AM |
6647 | { |
6648 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
543613e9 | 6649 | |
0cfa3eb3 | 6650 | if (i.tm.opcode_modifier.jump == JUMP_BYTE) /* jcxz, loop */ |
29b0f896 | 6651 | prefix = ADDR_PREFIX_OPCODE; |
252b5132 | 6652 | |
29b0f896 AM |
6653 | if (!add_prefix (prefix)) |
6654 | return 0; | |
24eab124 | 6655 | } |
252b5132 | 6656 | |
29b0f896 AM |
6657 | /* Set mode64 for an operand. */ |
6658 | if (i.suffix == QWORD_MNEM_SUFFIX | |
9146926a | 6659 | && flag_code == CODE_64BIT |
d2224064 | 6660 | && !i.tm.opcode_modifier.norex64 |
46e883c5 | 6661 | /* Special case for xchg %rax,%rax. It is NOP and doesn't |
d2224064 JB |
6662 | need rex64. */ |
6663 | && ! (i.operands == 2 | |
6664 | && i.tm.base_opcode == 0x90 | |
6665 | && i.tm.extension_opcode == None | |
75e5731b JB |
6666 | && i.types[0].bitfield.instance == Accum |
6667 | && i.types[0].bitfield.qword | |
6668 | && i.types[1].bitfield.instance == Accum | |
6669 | && i.types[1].bitfield.qword)) | |
d2224064 | 6670 | i.rex |= REX_W; |
3e73aa7c | 6671 | |
d2224064 | 6672 | break; |
29b0f896 | 6673 | } |
7ecd2f8b | 6674 | |
c8f8eebc | 6675 | if (i.tm.opcode_modifier.addrprefixopreg) |
c0a30a9f | 6676 | { |
c8f8eebc JB |
6677 | gas_assert (!i.suffix); |
6678 | gas_assert (i.reg_operands); | |
c0a30a9f | 6679 | |
c8f8eebc JB |
6680 | if (i.tm.operand_types[0].bitfield.instance == Accum |
6681 | || i.operands == 1) | |
6682 | { | |
6683 | /* The address size override prefix changes the size of the | |
6684 | first operand. */ | |
6685 | if (flag_code == CODE_64BIT | |
6686 | && i.op[0].regs->reg_type.bitfield.word) | |
6687 | { | |
6688 | as_bad (_("16-bit addressing unavailable for `%s'"), | |
6689 | i.tm.name); | |
6690 | return 0; | |
6691 | } | |
6692 | ||
6693 | if ((flag_code == CODE_32BIT | |
6694 | ? i.op[0].regs->reg_type.bitfield.word | |
6695 | : i.op[0].regs->reg_type.bitfield.dword) | |
6696 | && !add_prefix (ADDR_PREFIX_OPCODE)) | |
6697 | return 0; | |
6698 | } | |
c0a30a9f L |
6699 | else |
6700 | { | |
c8f8eebc JB |
6701 | /* Check invalid register operand when the address size override |
6702 | prefix changes the size of register operands. */ | |
6703 | unsigned int op; | |
6704 | enum { need_word, need_dword, need_qword } need; | |
6705 | ||
6706 | if (flag_code == CODE_32BIT) | |
6707 | need = i.prefix[ADDR_PREFIX] ? need_word : need_dword; | |
6708 | else if (i.prefix[ADDR_PREFIX]) | |
c0a30a9f L |
6709 | need = need_dword; |
6710 | else | |
6711 | need = flag_code == CODE_64BIT ? need_qword : need_word; | |
c0a30a9f | 6712 | |
c8f8eebc JB |
6713 | for (op = 0; op < i.operands; op++) |
6714 | { | |
6715 | if (i.types[op].bitfield.class != Reg) | |
6716 | continue; | |
6717 | ||
6718 | switch (need) | |
6719 | { | |
6720 | case need_word: | |
6721 | if (i.op[op].regs->reg_type.bitfield.word) | |
6722 | continue; | |
6723 | break; | |
6724 | case need_dword: | |
6725 | if (i.op[op].regs->reg_type.bitfield.dword) | |
6726 | continue; | |
6727 | break; | |
6728 | case need_qword: | |
6729 | if (i.op[op].regs->reg_type.bitfield.qword) | |
6730 | continue; | |
6731 | break; | |
6732 | } | |
6733 | ||
6734 | as_bad (_("invalid register operand size for `%s'"), | |
6735 | i.tm.name); | |
6736 | return 0; | |
6737 | } | |
6738 | } | |
c0a30a9f L |
6739 | } |
6740 | ||
29b0f896 AM |
6741 | return 1; |
6742 | } | |
3e73aa7c | 6743 | |
29b0f896 | 6744 | static int |
543613e9 | 6745 | check_byte_reg (void) |
29b0f896 AM |
6746 | { |
6747 | int op; | |
543613e9 | 6748 | |
29b0f896 AM |
6749 | for (op = i.operands; --op >= 0;) |
6750 | { | |
dc821c5f | 6751 | /* Skip non-register operands. */ |
bab6aec1 | 6752 | if (i.types[op].bitfield.class != Reg) |
dc821c5f JB |
6753 | continue; |
6754 | ||
29b0f896 AM |
6755 | /* If this is an eight bit register, it's OK. If it's the 16 or |
6756 | 32 bit version of an eight bit register, we will just use the | |
6757 | low portion, and that's OK too. */ | |
dc821c5f | 6758 | if (i.types[op].bitfield.byte) |
29b0f896 AM |
6759 | continue; |
6760 | ||
5a819eb9 | 6761 | /* I/O port address operands are OK too. */ |
75e5731b JB |
6762 | if (i.tm.operand_types[op].bitfield.instance == RegD |
6763 | && i.tm.operand_types[op].bitfield.word) | |
5a819eb9 JB |
6764 | continue; |
6765 | ||
9706160a JB |
6766 | /* crc32 only wants its source operand checked here. */ |
6767 | if (i.tm.base_opcode == 0xf20f38f0 && op) | |
9344ff29 L |
6768 | continue; |
6769 | ||
29b0f896 | 6770 | /* Any other register is bad. */ |
bab6aec1 | 6771 | if (i.types[op].bitfield.class == Reg |
3528c362 JB |
6772 | || i.types[op].bitfield.class == RegMMX |
6773 | || i.types[op].bitfield.class == RegSIMD | |
00cee14f | 6774 | || i.types[op].bitfield.class == SReg |
4a5c67ed JB |
6775 | || i.types[op].bitfield.class == RegCR |
6776 | || i.types[op].bitfield.class == RegDR | |
6777 | || i.types[op].bitfield.class == RegTR) | |
29b0f896 | 6778 | { |
a540244d L |
6779 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6780 | register_prefix, | |
29b0f896 AM |
6781 | i.op[op].regs->reg_name, |
6782 | i.tm.name, | |
6783 | i.suffix); | |
6784 | return 0; | |
6785 | } | |
6786 | } | |
6787 | return 1; | |
6788 | } | |
6789 | ||
6790 | static int | |
e3bb37b5 | 6791 | check_long_reg (void) |
29b0f896 AM |
6792 | { |
6793 | int op; | |
6794 | ||
6795 | for (op = i.operands; --op >= 0;) | |
dc821c5f | 6796 | /* Skip non-register operands. */ |
bab6aec1 | 6797 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 6798 | continue; |
29b0f896 AM |
6799 | /* Reject eight bit registers, except where the template requires |
6800 | them. (eg. movzb) */ | |
dc821c5f | 6801 | else if (i.types[op].bitfield.byte |
bab6aec1 | 6802 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 6803 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f JB |
6804 | && (i.tm.operand_types[op].bitfield.word |
6805 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 6806 | { |
a540244d L |
6807 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6808 | register_prefix, | |
29b0f896 AM |
6809 | i.op[op].regs->reg_name, |
6810 | i.tm.name, | |
6811 | i.suffix); | |
6812 | return 0; | |
6813 | } | |
be4c5e58 L |
6814 | /* Error if the e prefix on a general reg is missing. */ |
6815 | else if (i.types[op].bitfield.word | |
bab6aec1 | 6816 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 6817 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 6818 | && i.tm.operand_types[op].bitfield.dword) |
29b0f896 | 6819 | { |
be4c5e58 L |
6820 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
6821 | register_prefix, i.op[op].regs->reg_name, | |
6822 | i.suffix); | |
6823 | return 0; | |
252b5132 | 6824 | } |
e4630f71 | 6825 | /* Warn if the r prefix on a general reg is present. */ |
dc821c5f | 6826 | else if (i.types[op].bitfield.qword |
bab6aec1 | 6827 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 6828 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 6829 | && i.tm.operand_types[op].bitfield.dword) |
252b5132 | 6830 | { |
34828aad | 6831 | if (intel_syntax |
65fca059 | 6832 | && i.tm.opcode_modifier.toqword |
3528c362 | 6833 | && i.types[0].bitfield.class != RegSIMD) |
34828aad | 6834 | { |
ca61edf2 | 6835 | /* Convert to QWORD. We want REX byte. */ |
34828aad L |
6836 | i.suffix = QWORD_MNEM_SUFFIX; |
6837 | } | |
6838 | else | |
6839 | { | |
2b5d6a91 | 6840 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
6841 | register_prefix, i.op[op].regs->reg_name, |
6842 | i.suffix); | |
6843 | return 0; | |
6844 | } | |
29b0f896 AM |
6845 | } |
6846 | return 1; | |
6847 | } | |
252b5132 | 6848 | |
29b0f896 | 6849 | static int |
e3bb37b5 | 6850 | check_qword_reg (void) |
29b0f896 AM |
6851 | { |
6852 | int op; | |
252b5132 | 6853 | |
29b0f896 | 6854 | for (op = i.operands; --op >= 0; ) |
dc821c5f | 6855 | /* Skip non-register operands. */ |
bab6aec1 | 6856 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 6857 | continue; |
29b0f896 AM |
6858 | /* Reject eight bit registers, except where the template requires |
6859 | them. (eg. movzb) */ | |
dc821c5f | 6860 | else if (i.types[op].bitfield.byte |
bab6aec1 | 6861 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 6862 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f JB |
6863 | && (i.tm.operand_types[op].bitfield.word |
6864 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 6865 | { |
a540244d L |
6866 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6867 | register_prefix, | |
29b0f896 AM |
6868 | i.op[op].regs->reg_name, |
6869 | i.tm.name, | |
6870 | i.suffix); | |
6871 | return 0; | |
6872 | } | |
e4630f71 | 6873 | /* Warn if the r prefix on a general reg is missing. */ |
dc821c5f JB |
6874 | else if ((i.types[op].bitfield.word |
6875 | || i.types[op].bitfield.dword) | |
bab6aec1 | 6876 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 6877 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 6878 | && i.tm.operand_types[op].bitfield.qword) |
29b0f896 AM |
6879 | { |
6880 | /* Prohibit these changes in the 64bit mode, since the | |
6881 | lowering is more complicated. */ | |
34828aad | 6882 | if (intel_syntax |
ca61edf2 | 6883 | && i.tm.opcode_modifier.todword |
3528c362 | 6884 | && i.types[0].bitfield.class != RegSIMD) |
34828aad | 6885 | { |
ca61edf2 | 6886 | /* Convert to DWORD. We don't want REX byte. */ |
34828aad L |
6887 | i.suffix = LONG_MNEM_SUFFIX; |
6888 | } | |
6889 | else | |
6890 | { | |
2b5d6a91 | 6891 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
6892 | register_prefix, i.op[op].regs->reg_name, |
6893 | i.suffix); | |
6894 | return 0; | |
6895 | } | |
252b5132 | 6896 | } |
29b0f896 AM |
6897 | return 1; |
6898 | } | |
252b5132 | 6899 | |
29b0f896 | 6900 | static int |
e3bb37b5 | 6901 | check_word_reg (void) |
29b0f896 AM |
6902 | { |
6903 | int op; | |
6904 | for (op = i.operands; --op >= 0;) | |
dc821c5f | 6905 | /* Skip non-register operands. */ |
bab6aec1 | 6906 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 6907 | continue; |
29b0f896 AM |
6908 | /* Reject eight bit registers, except where the template requires |
6909 | them. (eg. movzb) */ | |
dc821c5f | 6910 | else if (i.types[op].bitfield.byte |
bab6aec1 | 6911 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 6912 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f JB |
6913 | && (i.tm.operand_types[op].bitfield.word |
6914 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 6915 | { |
a540244d L |
6916 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6917 | register_prefix, | |
29b0f896 AM |
6918 | i.op[op].regs->reg_name, |
6919 | i.tm.name, | |
6920 | i.suffix); | |
6921 | return 0; | |
6922 | } | |
9706160a JB |
6923 | /* Error if the e or r prefix on a general reg is present. */ |
6924 | else if ((i.types[op].bitfield.dword | |
dc821c5f | 6925 | || i.types[op].bitfield.qword) |
bab6aec1 | 6926 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 6927 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 6928 | && i.tm.operand_types[op].bitfield.word) |
252b5132 | 6929 | { |
9706160a JB |
6930 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
6931 | register_prefix, i.op[op].regs->reg_name, | |
6932 | i.suffix); | |
6933 | return 0; | |
29b0f896 AM |
6934 | } |
6935 | return 1; | |
6936 | } | |
252b5132 | 6937 | |
29b0f896 | 6938 | static int |
40fb9820 | 6939 | update_imm (unsigned int j) |
29b0f896 | 6940 | { |
bc0844ae | 6941 | i386_operand_type overlap = i.types[j]; |
40fb9820 L |
6942 | if ((overlap.bitfield.imm8 |
6943 | || overlap.bitfield.imm8s | |
6944 | || overlap.bitfield.imm16 | |
6945 | || overlap.bitfield.imm32 | |
6946 | || overlap.bitfield.imm32s | |
6947 | || overlap.bitfield.imm64) | |
0dfbf9d7 L |
6948 | && !operand_type_equal (&overlap, &imm8) |
6949 | && !operand_type_equal (&overlap, &imm8s) | |
6950 | && !operand_type_equal (&overlap, &imm16) | |
6951 | && !operand_type_equal (&overlap, &imm32) | |
6952 | && !operand_type_equal (&overlap, &imm32s) | |
6953 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 AM |
6954 | { |
6955 | if (i.suffix) | |
6956 | { | |
40fb9820 L |
6957 | i386_operand_type temp; |
6958 | ||
0dfbf9d7 | 6959 | operand_type_set (&temp, 0); |
7ab9ffdd | 6960 | if (i.suffix == BYTE_MNEM_SUFFIX) |
40fb9820 L |
6961 | { |
6962 | temp.bitfield.imm8 = overlap.bitfield.imm8; | |
6963 | temp.bitfield.imm8s = overlap.bitfield.imm8s; | |
6964 | } | |
6965 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
6966 | temp.bitfield.imm16 = overlap.bitfield.imm16; | |
6967 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
6968 | { | |
6969 | temp.bitfield.imm64 = overlap.bitfield.imm64; | |
6970 | temp.bitfield.imm32s = overlap.bitfield.imm32s; | |
6971 | } | |
6972 | else | |
6973 | temp.bitfield.imm32 = overlap.bitfield.imm32; | |
6974 | overlap = temp; | |
29b0f896 | 6975 | } |
0dfbf9d7 L |
6976 | else if (operand_type_equal (&overlap, &imm16_32_32s) |
6977 | || operand_type_equal (&overlap, &imm16_32) | |
6978 | || operand_type_equal (&overlap, &imm16_32s)) | |
29b0f896 | 6979 | { |
40fb9820 | 6980 | if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
65da13b5 | 6981 | overlap = imm16; |
40fb9820 | 6982 | else |
65da13b5 | 6983 | overlap = imm32s; |
29b0f896 | 6984 | } |
0dfbf9d7 L |
6985 | if (!operand_type_equal (&overlap, &imm8) |
6986 | && !operand_type_equal (&overlap, &imm8s) | |
6987 | && !operand_type_equal (&overlap, &imm16) | |
6988 | && !operand_type_equal (&overlap, &imm32) | |
6989 | && !operand_type_equal (&overlap, &imm32s) | |
6990 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 | 6991 | { |
4eed87de AM |
6992 | as_bad (_("no instruction mnemonic suffix given; " |
6993 | "can't determine immediate size")); | |
29b0f896 AM |
6994 | return 0; |
6995 | } | |
6996 | } | |
40fb9820 | 6997 | i.types[j] = overlap; |
29b0f896 | 6998 | |
40fb9820 L |
6999 | return 1; |
7000 | } | |
7001 | ||
7002 | static int | |
7003 | finalize_imm (void) | |
7004 | { | |
bc0844ae | 7005 | unsigned int j, n; |
29b0f896 | 7006 | |
bc0844ae L |
7007 | /* Update the first 2 immediate operands. */ |
7008 | n = i.operands > 2 ? 2 : i.operands; | |
7009 | if (n) | |
7010 | { | |
7011 | for (j = 0; j < n; j++) | |
7012 | if (update_imm (j) == 0) | |
7013 | return 0; | |
40fb9820 | 7014 | |
bc0844ae L |
7015 | /* The 3rd operand can't be immediate operand. */ |
7016 | gas_assert (operand_type_check (i.types[2], imm) == 0); | |
7017 | } | |
29b0f896 AM |
7018 | |
7019 | return 1; | |
7020 | } | |
7021 | ||
7022 | static int | |
e3bb37b5 | 7023 | process_operands (void) |
29b0f896 AM |
7024 | { |
7025 | /* Default segment register this instruction will use for memory | |
7026 | accesses. 0 means unknown. This is only for optimizing out | |
7027 | unnecessary segment overrides. */ | |
7028 | const seg_entry *default_seg = 0; | |
7029 | ||
2426c15f | 7030 | if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv) |
29b0f896 | 7031 | { |
91d6fa6a NC |
7032 | unsigned int dupl = i.operands; |
7033 | unsigned int dest = dupl - 1; | |
9fcfb3d7 L |
7034 | unsigned int j; |
7035 | ||
c0f3af97 | 7036 | /* The destination must be an xmm register. */ |
9c2799c2 | 7037 | gas_assert (i.reg_operands |
91d6fa6a | 7038 | && MAX_OPERANDS > dupl |
7ab9ffdd | 7039 | && operand_type_equal (&i.types[dest], ®xmm)); |
c0f3af97 | 7040 | |
75e5731b | 7041 | if (i.tm.operand_types[0].bitfield.instance == Accum |
1b54b8d7 | 7042 | && i.tm.operand_types[0].bitfield.xmmword) |
e2ec9d29 | 7043 | { |
8cd7925b | 7044 | if (i.tm.opcode_modifier.vexsources == VEX3SOURCES) |
c0f3af97 L |
7045 | { |
7046 | /* Keep xmm0 for instructions with VEX prefix and 3 | |
7047 | sources. */ | |
75e5731b | 7048 | i.tm.operand_types[0].bitfield.instance = InstanceNone; |
3528c362 | 7049 | i.tm.operand_types[0].bitfield.class = RegSIMD; |
c0f3af97 L |
7050 | goto duplicate; |
7051 | } | |
e2ec9d29 | 7052 | else |
c0f3af97 L |
7053 | { |
7054 | /* We remove the first xmm0 and keep the number of | |
7055 | operands unchanged, which in fact duplicates the | |
7056 | destination. */ | |
7057 | for (j = 1; j < i.operands; j++) | |
7058 | { | |
7059 | i.op[j - 1] = i.op[j]; | |
7060 | i.types[j - 1] = i.types[j]; | |
7061 | i.tm.operand_types[j - 1] = i.tm.operand_types[j]; | |
8dc0818e | 7062 | i.flags[j - 1] = i.flags[j]; |
c0f3af97 L |
7063 | } |
7064 | } | |
7065 | } | |
7066 | else if (i.tm.opcode_modifier.implicit1stxmm0) | |
7ab9ffdd | 7067 | { |
91d6fa6a | 7068 | gas_assert ((MAX_OPERANDS - 1) > dupl |
8cd7925b L |
7069 | && (i.tm.opcode_modifier.vexsources |
7070 | == VEX3SOURCES)); | |
c0f3af97 L |
7071 | |
7072 | /* Add the implicit xmm0 for instructions with VEX prefix | |
7073 | and 3 sources. */ | |
7074 | for (j = i.operands; j > 0; j--) | |
7075 | { | |
7076 | i.op[j] = i.op[j - 1]; | |
7077 | i.types[j] = i.types[j - 1]; | |
7078 | i.tm.operand_types[j] = i.tm.operand_types[j - 1]; | |
8dc0818e | 7079 | i.flags[j] = i.flags[j - 1]; |
c0f3af97 L |
7080 | } |
7081 | i.op[0].regs | |
7082 | = (const reg_entry *) hash_find (reg_hash, "xmm0"); | |
7ab9ffdd | 7083 | i.types[0] = regxmm; |
c0f3af97 L |
7084 | i.tm.operand_types[0] = regxmm; |
7085 | ||
7086 | i.operands += 2; | |
7087 | i.reg_operands += 2; | |
7088 | i.tm.operands += 2; | |
7089 | ||
91d6fa6a | 7090 | dupl++; |
c0f3af97 | 7091 | dest++; |
91d6fa6a NC |
7092 | i.op[dupl] = i.op[dest]; |
7093 | i.types[dupl] = i.types[dest]; | |
7094 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
8dc0818e | 7095 | i.flags[dupl] = i.flags[dest]; |
e2ec9d29 | 7096 | } |
c0f3af97 L |
7097 | else |
7098 | { | |
dc1e8a47 | 7099 | duplicate: |
c0f3af97 L |
7100 | i.operands++; |
7101 | i.reg_operands++; | |
7102 | i.tm.operands++; | |
7103 | ||
91d6fa6a NC |
7104 | i.op[dupl] = i.op[dest]; |
7105 | i.types[dupl] = i.types[dest]; | |
7106 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
8dc0818e | 7107 | i.flags[dupl] = i.flags[dest]; |
c0f3af97 L |
7108 | } |
7109 | ||
7110 | if (i.tm.opcode_modifier.immext) | |
7111 | process_immext (); | |
7112 | } | |
75e5731b | 7113 | else if (i.tm.operand_types[0].bitfield.instance == Accum |
1b54b8d7 | 7114 | && i.tm.operand_types[0].bitfield.xmmword) |
c0f3af97 L |
7115 | { |
7116 | unsigned int j; | |
7117 | ||
9fcfb3d7 L |
7118 | for (j = 1; j < i.operands; j++) |
7119 | { | |
7120 | i.op[j - 1] = i.op[j]; | |
7121 | i.types[j - 1] = i.types[j]; | |
7122 | ||
7123 | /* We need to adjust fields in i.tm since they are used by | |
7124 | build_modrm_byte. */ | |
7125 | i.tm.operand_types [j - 1] = i.tm.operand_types [j]; | |
8dc0818e JB |
7126 | |
7127 | i.flags[j - 1] = i.flags[j]; | |
9fcfb3d7 L |
7128 | } |
7129 | ||
e2ec9d29 L |
7130 | i.operands--; |
7131 | i.reg_operands--; | |
e2ec9d29 L |
7132 | i.tm.operands--; |
7133 | } | |
920d2ddc IT |
7134 | else if (i.tm.opcode_modifier.implicitquadgroup) |
7135 | { | |
a477a8c4 JB |
7136 | unsigned int regnum, first_reg_in_group, last_reg_in_group; |
7137 | ||
920d2ddc | 7138 | /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */ |
3528c362 | 7139 | gas_assert (i.operands >= 2 && i.types[1].bitfield.class == RegSIMD); |
a477a8c4 JB |
7140 | regnum = register_number (i.op[1].regs); |
7141 | first_reg_in_group = regnum & ~3; | |
7142 | last_reg_in_group = first_reg_in_group + 3; | |
7143 | if (regnum != first_reg_in_group) | |
7144 | as_warn (_("source register `%s%s' implicitly denotes" | |
7145 | " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"), | |
7146 | register_prefix, i.op[1].regs->reg_name, | |
7147 | register_prefix, i.op[1].regs->reg_name, first_reg_in_group, | |
7148 | register_prefix, i.op[1].regs->reg_name, last_reg_in_group, | |
7149 | i.tm.name); | |
7150 | } | |
e2ec9d29 L |
7151 | else if (i.tm.opcode_modifier.regkludge) |
7152 | { | |
7153 | /* The imul $imm, %reg instruction is converted into | |
7154 | imul $imm, %reg, %reg, and the clr %reg instruction | |
7155 | is converted into xor %reg, %reg. */ | |
7156 | ||
7157 | unsigned int first_reg_op; | |
7158 | ||
7159 | if (operand_type_check (i.types[0], reg)) | |
7160 | first_reg_op = 0; | |
7161 | else | |
7162 | first_reg_op = 1; | |
7163 | /* Pretend we saw the extra register operand. */ | |
9c2799c2 | 7164 | gas_assert (i.reg_operands == 1 |
7ab9ffdd | 7165 | && i.op[first_reg_op + 1].regs == 0); |
e2ec9d29 L |
7166 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; |
7167 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
7168 | i.operands++; | |
7169 | i.reg_operands++; | |
29b0f896 AM |
7170 | } |
7171 | ||
85b80b0f | 7172 | if (i.tm.opcode_modifier.modrm) |
29b0f896 AM |
7173 | { |
7174 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
52271982 AM |
7175 | must be put into the modrm byte). Now, we make the modrm and |
7176 | index base bytes based on all the info we've collected. */ | |
29b0f896 AM |
7177 | |
7178 | default_seg = build_modrm_byte (); | |
7179 | } | |
00cee14f | 7180 | else if (i.types[0].bitfield.class == SReg) |
85b80b0f JB |
7181 | { |
7182 | if (flag_code != CODE_64BIT | |
7183 | ? i.tm.base_opcode == POP_SEG_SHORT | |
7184 | && i.op[0].regs->reg_num == 1 | |
7185 | : (i.tm.base_opcode | 1) == POP_SEG386_SHORT | |
7186 | && i.op[0].regs->reg_num < 4) | |
7187 | { | |
7188 | as_bad (_("you can't `%s %s%s'"), | |
7189 | i.tm.name, register_prefix, i.op[0].regs->reg_name); | |
7190 | return 0; | |
7191 | } | |
7192 | if ( i.op[0].regs->reg_num > 3 && i.tm.opcode_length == 1 ) | |
7193 | { | |
7194 | i.tm.base_opcode ^= POP_SEG_SHORT ^ POP_SEG386_SHORT; | |
7195 | i.tm.opcode_length = 2; | |
7196 | } | |
7197 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); | |
7198 | } | |
8a2ed489 | 7199 | else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32) |
29b0f896 AM |
7200 | { |
7201 | default_seg = &ds; | |
7202 | } | |
40fb9820 | 7203 | else if (i.tm.opcode_modifier.isstring) |
29b0f896 AM |
7204 | { |
7205 | /* For the string instructions that allow a segment override | |
7206 | on one of their operands, the default segment is ds. */ | |
7207 | default_seg = &ds; | |
7208 | } | |
50128d0c | 7209 | else if (i.short_form) |
85b80b0f JB |
7210 | { |
7211 | /* The register or float register operand is in operand | |
7212 | 0 or 1. */ | |
bab6aec1 | 7213 | unsigned int op = i.tm.operand_types[0].bitfield.class != Reg; |
85b80b0f JB |
7214 | |
7215 | /* Register goes in low 3 bits of opcode. */ | |
7216 | i.tm.base_opcode |= i.op[op].regs->reg_num; | |
7217 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
7218 | i.rex |= REX_B; | |
7219 | if (!quiet_warnings && i.tm.opcode_modifier.ugh) | |
7220 | { | |
7221 | /* Warn about some common errors, but press on regardless. | |
7222 | The first case can be generated by gcc (<= 2.8.1). */ | |
7223 | if (i.operands == 2) | |
7224 | { | |
7225 | /* Reversed arguments on faddp, fsubp, etc. */ | |
7226 | as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, | |
7227 | register_prefix, i.op[!intel_syntax].regs->reg_name, | |
7228 | register_prefix, i.op[intel_syntax].regs->reg_name); | |
7229 | } | |
7230 | else | |
7231 | { | |
7232 | /* Extraneous `l' suffix on fp insn. */ | |
7233 | as_warn (_("translating to `%s %s%s'"), i.tm.name, | |
7234 | register_prefix, i.op[0].regs->reg_name); | |
7235 | } | |
7236 | } | |
7237 | } | |
29b0f896 | 7238 | |
514a8bb0 | 7239 | if ((i.seg[0] || i.prefix[SEG_PREFIX]) |
514a8bb0 JB |
7240 | && i.tm.base_opcode == 0x8d /* lea */ |
7241 | && !is_any_vex_encoding(&i.tm)) | |
92334ad2 JB |
7242 | { |
7243 | if (!quiet_warnings) | |
7244 | as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); | |
7245 | if (optimize) | |
7246 | { | |
7247 | i.seg[0] = NULL; | |
7248 | i.prefix[SEG_PREFIX] = 0; | |
7249 | } | |
7250 | } | |
52271982 AM |
7251 | |
7252 | /* If a segment was explicitly specified, and the specified segment | |
b6773884 JB |
7253 | is neither the default nor the one already recorded from a prefix, |
7254 | use an opcode prefix to select it. If we never figured out what | |
7255 | the default segment is, then default_seg will be zero at this | |
7256 | point, and the specified segment prefix will always be used. */ | |
7257 | if (i.seg[0] | |
7258 | && i.seg[0] != default_seg | |
7259 | && i.seg[0]->seg_prefix != i.prefix[SEG_PREFIX]) | |
29b0f896 AM |
7260 | { |
7261 | if (!add_prefix (i.seg[0]->seg_prefix)) | |
7262 | return 0; | |
7263 | } | |
7264 | return 1; | |
7265 | } | |
7266 | ||
7267 | static const seg_entry * | |
e3bb37b5 | 7268 | build_modrm_byte (void) |
29b0f896 AM |
7269 | { |
7270 | const seg_entry *default_seg = 0; | |
c0f3af97 | 7271 | unsigned int source, dest; |
8cd7925b | 7272 | int vex_3_sources; |
c0f3af97 | 7273 | |
8cd7925b | 7274 | vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES; |
c0f3af97 L |
7275 | if (vex_3_sources) |
7276 | { | |
91d6fa6a | 7277 | unsigned int nds, reg_slot; |
4c2c6516 | 7278 | expressionS *exp; |
c0f3af97 | 7279 | |
6b8d3588 | 7280 | dest = i.operands - 1; |
c0f3af97 | 7281 | nds = dest - 1; |
922d8de8 | 7282 | |
a683cc34 | 7283 | /* There are 2 kinds of instructions: |
bed3d976 | 7284 | 1. 5 operands: 4 register operands or 3 register operands |
9d3bf266 | 7285 | plus 1 memory operand plus one Imm4 operand, VexXDS, and |
bed3d976 | 7286 | VexW0 or VexW1. The destination must be either XMM, YMM or |
43234a1e | 7287 | ZMM register. |
bed3d976 | 7288 | 2. 4 operands: 4 register operands or 3 register operands |
2f1bada2 | 7289 | plus 1 memory operand, with VexXDS. */ |
922d8de8 | 7290 | gas_assert ((i.reg_operands == 4 |
bed3d976 JB |
7291 | || (i.reg_operands == 3 && i.mem_operands == 1)) |
7292 | && i.tm.opcode_modifier.vexvvvv == VEXXDS | |
dcd7e323 | 7293 | && i.tm.opcode_modifier.vexw |
3528c362 | 7294 | && i.tm.operand_types[dest].bitfield.class == RegSIMD); |
a683cc34 | 7295 | |
48db9223 JB |
7296 | /* If VexW1 is set, the first non-immediate operand is the source and |
7297 | the second non-immediate one is encoded in the immediate operand. */ | |
7298 | if (i.tm.opcode_modifier.vexw == VEXW1) | |
7299 | { | |
7300 | source = i.imm_operands; | |
7301 | reg_slot = i.imm_operands + 1; | |
7302 | } | |
7303 | else | |
7304 | { | |
7305 | source = i.imm_operands + 1; | |
7306 | reg_slot = i.imm_operands; | |
7307 | } | |
7308 | ||
a683cc34 | 7309 | if (i.imm_operands == 0) |
bed3d976 JB |
7310 | { |
7311 | /* When there is no immediate operand, generate an 8bit | |
7312 | immediate operand to encode the first operand. */ | |
7313 | exp = &im_expressions[i.imm_operands++]; | |
7314 | i.op[i.operands].imms = exp; | |
7315 | i.types[i.operands] = imm8; | |
7316 | i.operands++; | |
7317 | ||
3528c362 | 7318 | gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD); |
bed3d976 JB |
7319 | exp->X_op = O_constant; |
7320 | exp->X_add_number = register_number (i.op[reg_slot].regs) << 4; | |
43234a1e L |
7321 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
7322 | } | |
922d8de8 | 7323 | else |
bed3d976 | 7324 | { |
9d3bf266 JB |
7325 | gas_assert (i.imm_operands == 1); |
7326 | gas_assert (fits_in_imm4 (i.op[0].imms->X_add_number)); | |
7327 | gas_assert (!i.tm.opcode_modifier.immext); | |
a683cc34 | 7328 | |
9d3bf266 JB |
7329 | /* Turn on Imm8 again so that output_imm will generate it. */ |
7330 | i.types[0].bitfield.imm8 = 1; | |
bed3d976 | 7331 | |
3528c362 | 7332 | gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD); |
9d3bf266 | 7333 | i.op[0].imms->X_add_number |
bed3d976 | 7334 | |= register_number (i.op[reg_slot].regs) << 4; |
43234a1e | 7335 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
bed3d976 | 7336 | } |
a683cc34 | 7337 | |
3528c362 | 7338 | gas_assert (i.tm.operand_types[nds].bitfield.class == RegSIMD); |
dae39acc | 7339 | i.vex.register_specifier = i.op[nds].regs; |
c0f3af97 L |
7340 | } |
7341 | else | |
7342 | source = dest = 0; | |
29b0f896 AM |
7343 | |
7344 | /* i.reg_operands MUST be the number of real register operands; | |
c0f3af97 L |
7345 | implicit registers do not count. If there are 3 register |
7346 | operands, it must be a instruction with VexNDS. For a | |
7347 | instruction with VexNDD, the destination register is encoded | |
7348 | in VEX prefix. If there are 4 register operands, it must be | |
7349 | a instruction with VEX prefix and 3 sources. */ | |
7ab9ffdd L |
7350 | if (i.mem_operands == 0 |
7351 | && ((i.reg_operands == 2 | |
2426c15f | 7352 | && i.tm.opcode_modifier.vexvvvv <= VEXXDS) |
7ab9ffdd | 7353 | || (i.reg_operands == 3 |
2426c15f | 7354 | && i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd | 7355 | || (i.reg_operands == 4 && vex_3_sources))) |
29b0f896 | 7356 | { |
cab737b9 L |
7357 | switch (i.operands) |
7358 | { | |
7359 | case 2: | |
7360 | source = 0; | |
7361 | break; | |
7362 | case 3: | |
c81128dc L |
7363 | /* When there are 3 operands, one of them may be immediate, |
7364 | which may be the first or the last operand. Otherwise, | |
c0f3af97 L |
7365 | the first operand must be shift count register (cl) or it |
7366 | is an instruction with VexNDS. */ | |
9c2799c2 | 7367 | gas_assert (i.imm_operands == 1 |
7ab9ffdd | 7368 | || (i.imm_operands == 0 |
2426c15f | 7369 | && (i.tm.opcode_modifier.vexvvvv == VEXXDS |
75e5731b JB |
7370 | || (i.types[0].bitfield.instance == RegC |
7371 | && i.types[0].bitfield.byte)))); | |
40fb9820 | 7372 | if (operand_type_check (i.types[0], imm) |
75e5731b JB |
7373 | || (i.types[0].bitfield.instance == RegC |
7374 | && i.types[0].bitfield.byte)) | |
40fb9820 L |
7375 | source = 1; |
7376 | else | |
7377 | source = 0; | |
cab737b9 L |
7378 | break; |
7379 | case 4: | |
368d64cc L |
7380 | /* When there are 4 operands, the first two must be 8bit |
7381 | immediate operands. The source operand will be the 3rd | |
c0f3af97 L |
7382 | one. |
7383 | ||
7384 | For instructions with VexNDS, if the first operand | |
7385 | an imm8, the source operand is the 2nd one. If the last | |
7386 | operand is imm8, the source operand is the first one. */ | |
9c2799c2 | 7387 | gas_assert ((i.imm_operands == 2 |
7ab9ffdd L |
7388 | && i.types[0].bitfield.imm8 |
7389 | && i.types[1].bitfield.imm8) | |
2426c15f | 7390 | || (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd L |
7391 | && i.imm_operands == 1 |
7392 | && (i.types[0].bitfield.imm8 | |
43234a1e L |
7393 | || i.types[i.operands - 1].bitfield.imm8 |
7394 | || i.rounding))); | |
9f2670f2 L |
7395 | if (i.imm_operands == 2) |
7396 | source = 2; | |
7397 | else | |
c0f3af97 L |
7398 | { |
7399 | if (i.types[0].bitfield.imm8) | |
7400 | source = 1; | |
7401 | else | |
7402 | source = 0; | |
7403 | } | |
c0f3af97 L |
7404 | break; |
7405 | case 5: | |
e771e7c9 | 7406 | if (is_evex_encoding (&i.tm)) |
43234a1e L |
7407 | { |
7408 | /* For EVEX instructions, when there are 5 operands, the | |
7409 | first one must be immediate operand. If the second one | |
7410 | is immediate operand, the source operand is the 3th | |
7411 | one. If the last one is immediate operand, the source | |
7412 | operand is the 2nd one. */ | |
7413 | gas_assert (i.imm_operands == 2 | |
7414 | && i.tm.opcode_modifier.sae | |
7415 | && operand_type_check (i.types[0], imm)); | |
7416 | if (operand_type_check (i.types[1], imm)) | |
7417 | source = 2; | |
7418 | else if (operand_type_check (i.types[4], imm)) | |
7419 | source = 1; | |
7420 | else | |
7421 | abort (); | |
7422 | } | |
cab737b9 L |
7423 | break; |
7424 | default: | |
7425 | abort (); | |
7426 | } | |
7427 | ||
c0f3af97 L |
7428 | if (!vex_3_sources) |
7429 | { | |
7430 | dest = source + 1; | |
7431 | ||
43234a1e L |
7432 | /* RC/SAE operand could be between DEST and SRC. That happens |
7433 | when one operand is GPR and the other one is XMM/YMM/ZMM | |
7434 | register. */ | |
7435 | if (i.rounding && i.rounding->operand == (int) dest) | |
7436 | dest++; | |
7437 | ||
2426c15f | 7438 | if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
c0f3af97 | 7439 | { |
43234a1e | 7440 | /* For instructions with VexNDS, the register-only source |
c5d0745b | 7441 | operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask |
dfd69174 | 7442 | register. It is encoded in VEX prefix. */ |
f12dc422 L |
7443 | |
7444 | i386_operand_type op; | |
7445 | unsigned int vvvv; | |
7446 | ||
7447 | /* Check register-only source operand when two source | |
7448 | operands are swapped. */ | |
7449 | if (!i.tm.operand_types[source].bitfield.baseindex | |
7450 | && i.tm.operand_types[dest].bitfield.baseindex) | |
7451 | { | |
7452 | vvvv = source; | |
7453 | source = dest; | |
7454 | } | |
7455 | else | |
7456 | vvvv = dest; | |
7457 | ||
7458 | op = i.tm.operand_types[vvvv]; | |
c0f3af97 | 7459 | if ((dest + 1) >= i.operands |
bab6aec1 | 7460 | || ((op.bitfield.class != Reg |
dc821c5f | 7461 | || (!op.bitfield.dword && !op.bitfield.qword)) |
3528c362 | 7462 | && op.bitfield.class != RegSIMD |
43234a1e | 7463 | && !operand_type_equal (&op, ®mask))) |
c0f3af97 | 7464 | abort (); |
f12dc422 | 7465 | i.vex.register_specifier = i.op[vvvv].regs; |
c0f3af97 L |
7466 | dest++; |
7467 | } | |
7468 | } | |
29b0f896 AM |
7469 | |
7470 | i.rm.mode = 3; | |
dfd69174 JB |
7471 | /* One of the register operands will be encoded in the i.rm.reg |
7472 | field, the other in the combined i.rm.mode and i.rm.regmem | |
29b0f896 AM |
7473 | fields. If no form of this instruction supports a memory |
7474 | destination operand, then we assume the source operand may | |
7475 | sometimes be a memory operand and so we need to store the | |
7476 | destination in the i.rm.reg field. */ | |
dfd69174 | 7477 | if (!i.tm.opcode_modifier.regmem |
40fb9820 | 7478 | && operand_type_check (i.tm.operand_types[dest], anymem) == 0) |
29b0f896 AM |
7479 | { |
7480 | i.rm.reg = i.op[dest].regs->reg_num; | |
7481 | i.rm.regmem = i.op[source].regs->reg_num; | |
3528c362 JB |
7482 | if (i.op[dest].regs->reg_type.bitfield.class == RegMMX |
7483 | || i.op[source].regs->reg_type.bitfield.class == RegMMX) | |
b4a3a7b4 | 7484 | i.has_regmmx = TRUE; |
3528c362 JB |
7485 | else if (i.op[dest].regs->reg_type.bitfield.class == RegSIMD |
7486 | || i.op[source].regs->reg_type.bitfield.class == RegSIMD) | |
b4a3a7b4 L |
7487 | { |
7488 | if (i.types[dest].bitfield.zmmword | |
7489 | || i.types[source].bitfield.zmmword) | |
7490 | i.has_regzmm = TRUE; | |
7491 | else if (i.types[dest].bitfield.ymmword | |
7492 | || i.types[source].bitfield.ymmword) | |
7493 | i.has_regymm = TRUE; | |
7494 | else | |
7495 | i.has_regxmm = TRUE; | |
7496 | } | |
29b0f896 | 7497 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) |
161a04f6 | 7498 | i.rex |= REX_R; |
43234a1e L |
7499 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
7500 | i.vrex |= REX_R; | |
29b0f896 | 7501 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 7502 | i.rex |= REX_B; |
43234a1e L |
7503 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
7504 | i.vrex |= REX_B; | |
29b0f896 AM |
7505 | } |
7506 | else | |
7507 | { | |
7508 | i.rm.reg = i.op[source].regs->reg_num; | |
7509 | i.rm.regmem = i.op[dest].regs->reg_num; | |
7510 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 7511 | i.rex |= REX_B; |
43234a1e L |
7512 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
7513 | i.vrex |= REX_B; | |
29b0f896 | 7514 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 7515 | i.rex |= REX_R; |
43234a1e L |
7516 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
7517 | i.vrex |= REX_R; | |
29b0f896 | 7518 | } |
e0c7f900 | 7519 | if (flag_code != CODE_64BIT && (i.rex & REX_R)) |
c4a530c5 | 7520 | { |
4a5c67ed | 7521 | if (i.types[!i.tm.opcode_modifier.regmem].bitfield.class != RegCR) |
c4a530c5 | 7522 | abort (); |
e0c7f900 | 7523 | i.rex &= ~REX_R; |
c4a530c5 JB |
7524 | add_prefix (LOCK_PREFIX_OPCODE); |
7525 | } | |
29b0f896 AM |
7526 | } |
7527 | else | |
7528 | { /* If it's not 2 reg operands... */ | |
c0f3af97 L |
7529 | unsigned int mem; |
7530 | ||
29b0f896 AM |
7531 | if (i.mem_operands) |
7532 | { | |
7533 | unsigned int fake_zero_displacement = 0; | |
99018f42 | 7534 | unsigned int op; |
4eed87de | 7535 | |
7ab9ffdd | 7536 | for (op = 0; op < i.operands; op++) |
8dc0818e | 7537 | if (i.flags[op] & Operand_Mem) |
7ab9ffdd | 7538 | break; |
7ab9ffdd | 7539 | gas_assert (op < i.operands); |
29b0f896 | 7540 | |
6c30d220 L |
7541 | if (i.tm.opcode_modifier.vecsib) |
7542 | { | |
e968fc9b | 7543 | if (i.index_reg->reg_num == RegIZ) |
6c30d220 L |
7544 | abort (); |
7545 | ||
7546 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
7547 | if (!i.base_reg) | |
7548 | { | |
7549 | i.sib.base = NO_BASE_REGISTER; | |
7550 | i.sib.scale = i.log2_scale_factor; | |
7551 | i.types[op].bitfield.disp8 = 0; | |
7552 | i.types[op].bitfield.disp16 = 0; | |
7553 | i.types[op].bitfield.disp64 = 0; | |
43083a50 | 7554 | if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX]) |
6c30d220 L |
7555 | { |
7556 | /* Must be 32 bit */ | |
7557 | i.types[op].bitfield.disp32 = 1; | |
7558 | i.types[op].bitfield.disp32s = 0; | |
7559 | } | |
7560 | else | |
7561 | { | |
7562 | i.types[op].bitfield.disp32 = 0; | |
7563 | i.types[op].bitfield.disp32s = 1; | |
7564 | } | |
7565 | } | |
7566 | i.sib.index = i.index_reg->reg_num; | |
7567 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
7568 | i.rex |= REX_X; | |
43234a1e L |
7569 | if ((i.index_reg->reg_flags & RegVRex) != 0) |
7570 | i.vrex |= REX_X; | |
6c30d220 L |
7571 | } |
7572 | ||
29b0f896 AM |
7573 | default_seg = &ds; |
7574 | ||
7575 | if (i.base_reg == 0) | |
7576 | { | |
7577 | i.rm.mode = 0; | |
7578 | if (!i.disp_operands) | |
9bb129e8 | 7579 | fake_zero_displacement = 1; |
29b0f896 AM |
7580 | if (i.index_reg == 0) |
7581 | { | |
73053c1f JB |
7582 | i386_operand_type newdisp; |
7583 | ||
6c30d220 | 7584 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 7585 | /* Operand is just <disp> */ |
20f0a1fc | 7586 | if (flag_code == CODE_64BIT) |
29b0f896 AM |
7587 | { |
7588 | /* 64bit mode overwrites the 32bit absolute | |
7589 | addressing by RIP relative addressing and | |
7590 | absolute addressing is encoded by one of the | |
7591 | redundant SIB forms. */ | |
7592 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
7593 | i.sib.base = NO_BASE_REGISTER; | |
7594 | i.sib.index = NO_INDEX_REGISTER; | |
73053c1f | 7595 | newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32); |
20f0a1fc | 7596 | } |
fc225355 L |
7597 | else if ((flag_code == CODE_16BIT) |
7598 | ^ (i.prefix[ADDR_PREFIX] != 0)) | |
20f0a1fc NC |
7599 | { |
7600 | i.rm.regmem = NO_BASE_REGISTER_16; | |
73053c1f | 7601 | newdisp = disp16; |
20f0a1fc NC |
7602 | } |
7603 | else | |
7604 | { | |
7605 | i.rm.regmem = NO_BASE_REGISTER; | |
73053c1f | 7606 | newdisp = disp32; |
29b0f896 | 7607 | } |
73053c1f JB |
7608 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
7609 | i.types[op] = operand_type_or (i.types[op], newdisp); | |
29b0f896 | 7610 | } |
6c30d220 | 7611 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 7612 | { |
6c30d220 | 7613 | /* !i.base_reg && i.index_reg */ |
e968fc9b | 7614 | if (i.index_reg->reg_num == RegIZ) |
db51cc60 L |
7615 | i.sib.index = NO_INDEX_REGISTER; |
7616 | else | |
7617 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
7618 | i.sib.base = NO_BASE_REGISTER; |
7619 | i.sib.scale = i.log2_scale_factor; | |
7620 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
40fb9820 L |
7621 | i.types[op].bitfield.disp8 = 0; |
7622 | i.types[op].bitfield.disp16 = 0; | |
7623 | i.types[op].bitfield.disp64 = 0; | |
43083a50 | 7624 | if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX]) |
40fb9820 L |
7625 | { |
7626 | /* Must be 32 bit */ | |
7627 | i.types[op].bitfield.disp32 = 1; | |
7628 | i.types[op].bitfield.disp32s = 0; | |
7629 | } | |
29b0f896 | 7630 | else |
40fb9820 L |
7631 | { |
7632 | i.types[op].bitfield.disp32 = 0; | |
7633 | i.types[op].bitfield.disp32s = 1; | |
7634 | } | |
29b0f896 | 7635 | if ((i.index_reg->reg_flags & RegRex) != 0) |
161a04f6 | 7636 | i.rex |= REX_X; |
29b0f896 AM |
7637 | } |
7638 | } | |
7639 | /* RIP addressing for 64bit mode. */ | |
e968fc9b | 7640 | else if (i.base_reg->reg_num == RegIP) |
29b0f896 | 7641 | { |
6c30d220 | 7642 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 7643 | i.rm.regmem = NO_BASE_REGISTER; |
40fb9820 L |
7644 | i.types[op].bitfield.disp8 = 0; |
7645 | i.types[op].bitfield.disp16 = 0; | |
7646 | i.types[op].bitfield.disp32 = 0; | |
7647 | i.types[op].bitfield.disp32s = 1; | |
7648 | i.types[op].bitfield.disp64 = 0; | |
71903a11 | 7649 | i.flags[op] |= Operand_PCrel; |
20f0a1fc NC |
7650 | if (! i.disp_operands) |
7651 | fake_zero_displacement = 1; | |
29b0f896 | 7652 | } |
dc821c5f | 7653 | else if (i.base_reg->reg_type.bitfield.word) |
29b0f896 | 7654 | { |
6c30d220 | 7655 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
7656 | switch (i.base_reg->reg_num) |
7657 | { | |
7658 | case 3: /* (%bx) */ | |
7659 | if (i.index_reg == 0) | |
7660 | i.rm.regmem = 7; | |
7661 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
7662 | i.rm.regmem = i.index_reg->reg_num - 6; | |
7663 | break; | |
7664 | case 5: /* (%bp) */ | |
7665 | default_seg = &ss; | |
7666 | if (i.index_reg == 0) | |
7667 | { | |
7668 | i.rm.regmem = 6; | |
40fb9820 | 7669 | if (operand_type_check (i.types[op], disp) == 0) |
29b0f896 AM |
7670 | { |
7671 | /* fake (%bp) into 0(%bp) */ | |
b5014f7a | 7672 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 7673 | fake_zero_displacement = 1; |
29b0f896 AM |
7674 | } |
7675 | } | |
7676 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
7677 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
7678 | break; | |
7679 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
7680 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
7681 | } | |
7682 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
7683 | } | |
7684 | else /* i.base_reg and 32/64 bit mode */ | |
7685 | { | |
7686 | if (flag_code == CODE_64BIT | |
40fb9820 L |
7687 | && operand_type_check (i.types[op], disp)) |
7688 | { | |
73053c1f JB |
7689 | i.types[op].bitfield.disp16 = 0; |
7690 | i.types[op].bitfield.disp64 = 0; | |
40fb9820 | 7691 | if (i.prefix[ADDR_PREFIX] == 0) |
73053c1f JB |
7692 | { |
7693 | i.types[op].bitfield.disp32 = 0; | |
7694 | i.types[op].bitfield.disp32s = 1; | |
7695 | } | |
40fb9820 | 7696 | else |
73053c1f JB |
7697 | { |
7698 | i.types[op].bitfield.disp32 = 1; | |
7699 | i.types[op].bitfield.disp32s = 0; | |
7700 | } | |
40fb9820 | 7701 | } |
20f0a1fc | 7702 | |
6c30d220 L |
7703 | if (!i.tm.opcode_modifier.vecsib) |
7704 | i.rm.regmem = i.base_reg->reg_num; | |
29b0f896 | 7705 | if ((i.base_reg->reg_flags & RegRex) != 0) |
161a04f6 | 7706 | i.rex |= REX_B; |
29b0f896 AM |
7707 | i.sib.base = i.base_reg->reg_num; |
7708 | /* x86-64 ignores REX prefix bit here to avoid decoder | |
7709 | complications. */ | |
848930b2 JB |
7710 | if (!(i.base_reg->reg_flags & RegRex) |
7711 | && (i.base_reg->reg_num == EBP_REG_NUM | |
7712 | || i.base_reg->reg_num == ESP_REG_NUM)) | |
29b0f896 | 7713 | default_seg = &ss; |
848930b2 | 7714 | if (i.base_reg->reg_num == 5 && i.disp_operands == 0) |
29b0f896 | 7715 | { |
848930b2 | 7716 | fake_zero_displacement = 1; |
b5014f7a | 7717 | i.types[op].bitfield.disp8 = 1; |
29b0f896 AM |
7718 | } |
7719 | i.sib.scale = i.log2_scale_factor; | |
7720 | if (i.index_reg == 0) | |
7721 | { | |
6c30d220 | 7722 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
7723 | /* <disp>(%esp) becomes two byte modrm with no index |
7724 | register. We've already stored the code for esp | |
7725 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. | |
7726 | Any base register besides %esp will not use the | |
7727 | extra modrm byte. */ | |
7728 | i.sib.index = NO_INDEX_REGISTER; | |
29b0f896 | 7729 | } |
6c30d220 | 7730 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 7731 | { |
e968fc9b | 7732 | if (i.index_reg->reg_num == RegIZ) |
db51cc60 L |
7733 | i.sib.index = NO_INDEX_REGISTER; |
7734 | else | |
7735 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
7736 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
7737 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
161a04f6 | 7738 | i.rex |= REX_X; |
29b0f896 | 7739 | } |
67a4f2b7 AO |
7740 | |
7741 | if (i.disp_operands | |
7742 | && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL | |
7743 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) | |
7744 | i.rm.mode = 0; | |
7745 | else | |
a501d77e L |
7746 | { |
7747 | if (!fake_zero_displacement | |
7748 | && !i.disp_operands | |
7749 | && i.disp_encoding) | |
7750 | { | |
7751 | fake_zero_displacement = 1; | |
7752 | if (i.disp_encoding == disp_encoding_8bit) | |
7753 | i.types[op].bitfield.disp8 = 1; | |
7754 | else | |
7755 | i.types[op].bitfield.disp32 = 1; | |
7756 | } | |
7757 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
7758 | } | |
29b0f896 | 7759 | } |
252b5132 | 7760 | |
29b0f896 AM |
7761 | if (fake_zero_displacement) |
7762 | { | |
7763 | /* Fakes a zero displacement assuming that i.types[op] | |
7764 | holds the correct displacement size. */ | |
7765 | expressionS *exp; | |
7766 | ||
9c2799c2 | 7767 | gas_assert (i.op[op].disps == 0); |
29b0f896 AM |
7768 | exp = &disp_expressions[i.disp_operands++]; |
7769 | i.op[op].disps = exp; | |
7770 | exp->X_op = O_constant; | |
7771 | exp->X_add_number = 0; | |
7772 | exp->X_add_symbol = (symbolS *) 0; | |
7773 | exp->X_op_symbol = (symbolS *) 0; | |
7774 | } | |
c0f3af97 L |
7775 | |
7776 | mem = op; | |
29b0f896 | 7777 | } |
c0f3af97 L |
7778 | else |
7779 | mem = ~0; | |
252b5132 | 7780 | |
8c43a48b | 7781 | if (i.tm.opcode_modifier.vexsources == XOP2SOURCES) |
5dd85c99 SP |
7782 | { |
7783 | if (operand_type_check (i.types[0], imm)) | |
7784 | i.vex.register_specifier = NULL; | |
7785 | else | |
7786 | { | |
7787 | /* VEX.vvvv encodes one of the sources when the first | |
7788 | operand is not an immediate. */ | |
1ef99a7b | 7789 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
7790 | i.vex.register_specifier = i.op[0].regs; |
7791 | else | |
7792 | i.vex.register_specifier = i.op[1].regs; | |
7793 | } | |
7794 | ||
7795 | /* Destination is a XMM register encoded in the ModRM.reg | |
7796 | and VEX.R bit. */ | |
7797 | i.rm.reg = i.op[2].regs->reg_num; | |
7798 | if ((i.op[2].regs->reg_flags & RegRex) != 0) | |
7799 | i.rex |= REX_R; | |
7800 | ||
7801 | /* ModRM.rm and VEX.B encodes the other source. */ | |
7802 | if (!i.mem_operands) | |
7803 | { | |
7804 | i.rm.mode = 3; | |
7805 | ||
1ef99a7b | 7806 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
7807 | i.rm.regmem = i.op[1].regs->reg_num; |
7808 | else | |
7809 | i.rm.regmem = i.op[0].regs->reg_num; | |
7810 | ||
7811 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
7812 | i.rex |= REX_B; | |
7813 | } | |
7814 | } | |
2426c15f | 7815 | else if (i.tm.opcode_modifier.vexvvvv == VEXLWP) |
f88c9eb0 SP |
7816 | { |
7817 | i.vex.register_specifier = i.op[2].regs; | |
7818 | if (!i.mem_operands) | |
7819 | { | |
7820 | i.rm.mode = 3; | |
7821 | i.rm.regmem = i.op[1].regs->reg_num; | |
7822 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
7823 | i.rex |= REX_B; | |
7824 | } | |
7825 | } | |
29b0f896 AM |
7826 | /* Fill in i.rm.reg or i.rm.regmem field with register operand |
7827 | (if any) based on i.tm.extension_opcode. Again, we must be | |
7828 | careful to make sure that segment/control/debug/test/MMX | |
7829 | registers are coded into the i.rm.reg field. */ | |
f88c9eb0 | 7830 | else if (i.reg_operands) |
29b0f896 | 7831 | { |
99018f42 | 7832 | unsigned int op; |
7ab9ffdd L |
7833 | unsigned int vex_reg = ~0; |
7834 | ||
7835 | for (op = 0; op < i.operands; op++) | |
b4a3a7b4 | 7836 | { |
bab6aec1 | 7837 | if (i.types[op].bitfield.class == Reg |
f74a6307 JB |
7838 | || i.types[op].bitfield.class == RegBND |
7839 | || i.types[op].bitfield.class == RegMask | |
00cee14f | 7840 | || i.types[op].bitfield.class == SReg |
4a5c67ed JB |
7841 | || i.types[op].bitfield.class == RegCR |
7842 | || i.types[op].bitfield.class == RegDR | |
7843 | || i.types[op].bitfield.class == RegTR) | |
b4a3a7b4 | 7844 | break; |
3528c362 | 7845 | if (i.types[op].bitfield.class == RegSIMD) |
b4a3a7b4 L |
7846 | { |
7847 | if (i.types[op].bitfield.zmmword) | |
7848 | i.has_regzmm = TRUE; | |
7849 | else if (i.types[op].bitfield.ymmword) | |
7850 | i.has_regymm = TRUE; | |
7851 | else | |
7852 | i.has_regxmm = TRUE; | |
7853 | break; | |
7854 | } | |
3528c362 | 7855 | if (i.types[op].bitfield.class == RegMMX) |
b4a3a7b4 L |
7856 | { |
7857 | i.has_regmmx = TRUE; | |
7858 | break; | |
7859 | } | |
7860 | } | |
c0209578 | 7861 | |
7ab9ffdd L |
7862 | if (vex_3_sources) |
7863 | op = dest; | |
2426c15f | 7864 | else if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd L |
7865 | { |
7866 | /* For instructions with VexNDS, the register-only | |
7867 | source operand is encoded in VEX prefix. */ | |
7868 | gas_assert (mem != (unsigned int) ~0); | |
c0f3af97 | 7869 | |
7ab9ffdd | 7870 | if (op > mem) |
c0f3af97 | 7871 | { |
7ab9ffdd L |
7872 | vex_reg = op++; |
7873 | gas_assert (op < i.operands); | |
c0f3af97 L |
7874 | } |
7875 | else | |
c0f3af97 | 7876 | { |
f12dc422 L |
7877 | /* Check register-only source operand when two source |
7878 | operands are swapped. */ | |
7879 | if (!i.tm.operand_types[op].bitfield.baseindex | |
7880 | && i.tm.operand_types[op + 1].bitfield.baseindex) | |
7881 | { | |
7882 | vex_reg = op; | |
7883 | op += 2; | |
7884 | gas_assert (mem == (vex_reg + 1) | |
7885 | && op < i.operands); | |
7886 | } | |
7887 | else | |
7888 | { | |
7889 | vex_reg = op + 1; | |
7890 | gas_assert (vex_reg < i.operands); | |
7891 | } | |
c0f3af97 | 7892 | } |
7ab9ffdd | 7893 | } |
2426c15f | 7894 | else if (i.tm.opcode_modifier.vexvvvv == VEXNDD) |
7ab9ffdd | 7895 | { |
f12dc422 | 7896 | /* For instructions with VexNDD, the register destination |
7ab9ffdd | 7897 | is encoded in VEX prefix. */ |
f12dc422 L |
7898 | if (i.mem_operands == 0) |
7899 | { | |
7900 | /* There is no memory operand. */ | |
7901 | gas_assert ((op + 2) == i.operands); | |
7902 | vex_reg = op + 1; | |
7903 | } | |
7904 | else | |
8d63c93e | 7905 | { |
ed438a93 JB |
7906 | /* There are only 2 non-immediate operands. */ |
7907 | gas_assert (op < i.imm_operands + 2 | |
7908 | && i.operands == i.imm_operands + 2); | |
7909 | vex_reg = i.imm_operands + 1; | |
f12dc422 | 7910 | } |
7ab9ffdd L |
7911 | } |
7912 | else | |
7913 | gas_assert (op < i.operands); | |
99018f42 | 7914 | |
7ab9ffdd L |
7915 | if (vex_reg != (unsigned int) ~0) |
7916 | { | |
f12dc422 | 7917 | i386_operand_type *type = &i.tm.operand_types[vex_reg]; |
7ab9ffdd | 7918 | |
bab6aec1 | 7919 | if ((type->bitfield.class != Reg |
dc821c5f | 7920 | || (!type->bitfield.dword && !type->bitfield.qword)) |
3528c362 | 7921 | && type->bitfield.class != RegSIMD |
43234a1e | 7922 | && !operand_type_equal (type, ®mask)) |
7ab9ffdd | 7923 | abort (); |
f88c9eb0 | 7924 | |
7ab9ffdd L |
7925 | i.vex.register_specifier = i.op[vex_reg].regs; |
7926 | } | |
7927 | ||
1b9f0c97 L |
7928 | /* Don't set OP operand twice. */ |
7929 | if (vex_reg != op) | |
7ab9ffdd | 7930 | { |
1b9f0c97 L |
7931 | /* If there is an extension opcode to put here, the |
7932 | register number must be put into the regmem field. */ | |
7933 | if (i.tm.extension_opcode != None) | |
7934 | { | |
7935 | i.rm.regmem = i.op[op].regs->reg_num; | |
7936 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
7937 | i.rex |= REX_B; | |
43234a1e L |
7938 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
7939 | i.vrex |= REX_B; | |
1b9f0c97 L |
7940 | } |
7941 | else | |
7942 | { | |
7943 | i.rm.reg = i.op[op].regs->reg_num; | |
7944 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
7945 | i.rex |= REX_R; | |
43234a1e L |
7946 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
7947 | i.vrex |= REX_R; | |
1b9f0c97 | 7948 | } |
7ab9ffdd | 7949 | } |
252b5132 | 7950 | |
29b0f896 AM |
7951 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we |
7952 | must set it to 3 to indicate this is a register operand | |
7953 | in the regmem field. */ | |
7954 | if (!i.mem_operands) | |
7955 | i.rm.mode = 3; | |
7956 | } | |
252b5132 | 7957 | |
29b0f896 | 7958 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
c1e679ec | 7959 | if (i.tm.extension_opcode != None) |
29b0f896 AM |
7960 | i.rm.reg = i.tm.extension_opcode; |
7961 | } | |
7962 | return default_seg; | |
7963 | } | |
252b5132 | 7964 | |
376cd056 JB |
7965 | static unsigned int |
7966 | flip_code16 (unsigned int code16) | |
7967 | { | |
7968 | gas_assert (i.tm.operands == 1); | |
7969 | ||
7970 | return !(i.prefix[REX_PREFIX] & REX_W) | |
7971 | && (code16 ? i.tm.operand_types[0].bitfield.disp32 | |
7972 | || i.tm.operand_types[0].bitfield.disp32s | |
7973 | : i.tm.operand_types[0].bitfield.disp16) | |
7974 | ? CODE16 : 0; | |
7975 | } | |
7976 | ||
29b0f896 | 7977 | static void |
e3bb37b5 | 7978 | output_branch (void) |
29b0f896 AM |
7979 | { |
7980 | char *p; | |
f8a5c266 | 7981 | int size; |
29b0f896 AM |
7982 | int code16; |
7983 | int prefix; | |
7984 | relax_substateT subtype; | |
7985 | symbolS *sym; | |
7986 | offsetT off; | |
7987 | ||
f8a5c266 | 7988 | code16 = flag_code == CODE_16BIT ? CODE16 : 0; |
a501d77e | 7989 | size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL; |
29b0f896 AM |
7990 | |
7991 | prefix = 0; | |
7992 | if (i.prefix[DATA_PREFIX] != 0) | |
252b5132 | 7993 | { |
29b0f896 AM |
7994 | prefix = 1; |
7995 | i.prefixes -= 1; | |
376cd056 | 7996 | code16 ^= flip_code16(code16); |
252b5132 | 7997 | } |
29b0f896 AM |
7998 | /* Pentium4 branch hints. */ |
7999 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
8000 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2f66722d | 8001 | { |
29b0f896 AM |
8002 | prefix++; |
8003 | i.prefixes--; | |
8004 | } | |
8005 | if (i.prefix[REX_PREFIX] != 0) | |
8006 | { | |
8007 | prefix++; | |
8008 | i.prefixes--; | |
2f66722d AM |
8009 | } |
8010 | ||
7e8b059b L |
8011 | /* BND prefixed jump. */ |
8012 | if (i.prefix[BND_PREFIX] != 0) | |
8013 | { | |
6cb0a70e JB |
8014 | prefix++; |
8015 | i.prefixes--; | |
7e8b059b L |
8016 | } |
8017 | ||
f2810fe0 JB |
8018 | if (i.prefixes != 0) |
8019 | as_warn (_("skipping prefixes on `%s'"), i.tm.name); | |
29b0f896 AM |
8020 | |
8021 | /* It's always a symbol; End frag & setup for relax. | |
8022 | Make sure there is enough room in this frag for the largest | |
8023 | instruction we may generate in md_convert_frag. This is 2 | |
8024 | bytes for the opcode and room for the prefix and largest | |
8025 | displacement. */ | |
8026 | frag_grow (prefix + 2 + 4); | |
8027 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
8028 | p = frag_more (prefix + 1); | |
8029 | if (i.prefix[DATA_PREFIX] != 0) | |
8030 | *p++ = DATA_PREFIX_OPCODE; | |
8031 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE | |
8032 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
8033 | *p++ = i.prefix[SEG_PREFIX]; | |
6cb0a70e JB |
8034 | if (i.prefix[BND_PREFIX] != 0) |
8035 | *p++ = BND_PREFIX_OPCODE; | |
29b0f896 AM |
8036 | if (i.prefix[REX_PREFIX] != 0) |
8037 | *p++ = i.prefix[REX_PREFIX]; | |
8038 | *p = i.tm.base_opcode; | |
8039 | ||
8040 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
f8a5c266 | 8041 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size); |
40fb9820 | 8042 | else if (cpu_arch_flags.bitfield.cpui386) |
f8a5c266 | 8043 | subtype = ENCODE_RELAX_STATE (COND_JUMP, size); |
29b0f896 | 8044 | else |
f8a5c266 | 8045 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, size); |
29b0f896 | 8046 | subtype |= code16; |
3e73aa7c | 8047 | |
29b0f896 AM |
8048 | sym = i.op[0].disps->X_add_symbol; |
8049 | off = i.op[0].disps->X_add_number; | |
3e73aa7c | 8050 | |
29b0f896 AM |
8051 | if (i.op[0].disps->X_op != O_constant |
8052 | && i.op[0].disps->X_op != O_symbol) | |
3e73aa7c | 8053 | { |
29b0f896 AM |
8054 | /* Handle complex expressions. */ |
8055 | sym = make_expr_symbol (i.op[0].disps); | |
8056 | off = 0; | |
8057 | } | |
3e73aa7c | 8058 | |
29b0f896 AM |
8059 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
8060 | Pass reloc in fr_var. */ | |
d258b828 | 8061 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); |
29b0f896 | 8062 | } |
3e73aa7c | 8063 | |
bd7ab16b L |
8064 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8065 | /* Return TRUE iff PLT32 relocation should be used for branching to | |
8066 | symbol S. */ | |
8067 | ||
8068 | static bfd_boolean | |
8069 | need_plt32_p (symbolS *s) | |
8070 | { | |
8071 | /* PLT32 relocation is ELF only. */ | |
8072 | if (!IS_ELF) | |
8073 | return FALSE; | |
8074 | ||
a5def729 RO |
8075 | #ifdef TE_SOLARIS |
8076 | /* Don't emit PLT32 relocation on Solaris: neither native linker nor | |
8077 | krtld support it. */ | |
8078 | return FALSE; | |
8079 | #endif | |
8080 | ||
bd7ab16b L |
8081 | /* Since there is no need to prepare for PLT branch on x86-64, we |
8082 | can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can | |
8083 | be used as a marker for 32-bit PC-relative branches. */ | |
8084 | if (!object_64bit) | |
8085 | return FALSE; | |
8086 | ||
8087 | /* Weak or undefined symbol need PLT32 relocation. */ | |
8088 | if (S_IS_WEAK (s) || !S_IS_DEFINED (s)) | |
8089 | return TRUE; | |
8090 | ||
8091 | /* Non-global symbol doesn't need PLT32 relocation. */ | |
8092 | if (! S_IS_EXTERNAL (s)) | |
8093 | return FALSE; | |
8094 | ||
8095 | /* Other global symbols need PLT32 relocation. NB: Symbol with | |
8096 | non-default visibilities are treated as normal global symbol | |
8097 | so that PLT32 relocation can be used as a marker for 32-bit | |
8098 | PC-relative branches. It is useful for linker relaxation. */ | |
8099 | return TRUE; | |
8100 | } | |
8101 | #endif | |
8102 | ||
29b0f896 | 8103 | static void |
e3bb37b5 | 8104 | output_jump (void) |
29b0f896 AM |
8105 | { |
8106 | char *p; | |
8107 | int size; | |
3e02c1cc | 8108 | fixS *fixP; |
bd7ab16b | 8109 | bfd_reloc_code_real_type jump_reloc = i.reloc[0]; |
29b0f896 | 8110 | |
0cfa3eb3 | 8111 | if (i.tm.opcode_modifier.jump == JUMP_BYTE) |
29b0f896 AM |
8112 | { |
8113 | /* This is a loop or jecxz type instruction. */ | |
8114 | size = 1; | |
8115 | if (i.prefix[ADDR_PREFIX] != 0) | |
8116 | { | |
8117 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); | |
8118 | i.prefixes -= 1; | |
8119 | } | |
8120 | /* Pentium4 branch hints. */ | |
8121 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
8122 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
8123 | { | |
8124 | FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); | |
8125 | i.prefixes--; | |
3e73aa7c JH |
8126 | } |
8127 | } | |
29b0f896 AM |
8128 | else |
8129 | { | |
8130 | int code16; | |
3e73aa7c | 8131 | |
29b0f896 AM |
8132 | code16 = 0; |
8133 | if (flag_code == CODE_16BIT) | |
8134 | code16 = CODE16; | |
3e73aa7c | 8135 | |
29b0f896 AM |
8136 | if (i.prefix[DATA_PREFIX] != 0) |
8137 | { | |
8138 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); | |
8139 | i.prefixes -= 1; | |
376cd056 | 8140 | code16 ^= flip_code16(code16); |
29b0f896 | 8141 | } |
252b5132 | 8142 | |
29b0f896 AM |
8143 | size = 4; |
8144 | if (code16) | |
8145 | size = 2; | |
8146 | } | |
9fcc94b6 | 8147 | |
6cb0a70e JB |
8148 | /* BND prefixed jump. */ |
8149 | if (i.prefix[BND_PREFIX] != 0) | |
29b0f896 | 8150 | { |
6cb0a70e | 8151 | FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]); |
29b0f896 AM |
8152 | i.prefixes -= 1; |
8153 | } | |
252b5132 | 8154 | |
6cb0a70e | 8155 | if (i.prefix[REX_PREFIX] != 0) |
7e8b059b | 8156 | { |
6cb0a70e | 8157 | FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); |
7e8b059b L |
8158 | i.prefixes -= 1; |
8159 | } | |
8160 | ||
f2810fe0 JB |
8161 | if (i.prefixes != 0) |
8162 | as_warn (_("skipping prefixes on `%s'"), i.tm.name); | |
e0890092 | 8163 | |
42164a71 L |
8164 | p = frag_more (i.tm.opcode_length + size); |
8165 | switch (i.tm.opcode_length) | |
8166 | { | |
8167 | case 2: | |
8168 | *p++ = i.tm.base_opcode >> 8; | |
1a0670f3 | 8169 | /* Fall through. */ |
42164a71 L |
8170 | case 1: |
8171 | *p++ = i.tm.base_opcode; | |
8172 | break; | |
8173 | default: | |
8174 | abort (); | |
8175 | } | |
e0890092 | 8176 | |
bd7ab16b L |
8177 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8178 | if (size == 4 | |
8179 | && jump_reloc == NO_RELOC | |
8180 | && need_plt32_p (i.op[0].disps->X_add_symbol)) | |
8181 | jump_reloc = BFD_RELOC_X86_64_PLT32; | |
8182 | #endif | |
8183 | ||
8184 | jump_reloc = reloc (size, 1, 1, jump_reloc); | |
8185 | ||
3e02c1cc | 8186 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
bd7ab16b | 8187 | i.op[0].disps, 1, jump_reloc); |
3e02c1cc AM |
8188 | |
8189 | /* All jumps handled here are signed, but don't use a signed limit | |
8190 | check for 32 and 16 bit jumps as we want to allow wrap around at | |
8191 | 4G and 64k respectively. */ | |
8192 | if (size == 1) | |
8193 | fixP->fx_signed = 1; | |
29b0f896 | 8194 | } |
e0890092 | 8195 | |
29b0f896 | 8196 | static void |
e3bb37b5 | 8197 | output_interseg_jump (void) |
29b0f896 AM |
8198 | { |
8199 | char *p; | |
8200 | int size; | |
8201 | int prefix; | |
8202 | int code16; | |
252b5132 | 8203 | |
29b0f896 AM |
8204 | code16 = 0; |
8205 | if (flag_code == CODE_16BIT) | |
8206 | code16 = CODE16; | |
a217f122 | 8207 | |
29b0f896 AM |
8208 | prefix = 0; |
8209 | if (i.prefix[DATA_PREFIX] != 0) | |
8210 | { | |
8211 | prefix = 1; | |
8212 | i.prefixes -= 1; | |
8213 | code16 ^= CODE16; | |
8214 | } | |
6cb0a70e JB |
8215 | |
8216 | gas_assert (!i.prefix[REX_PREFIX]); | |
252b5132 | 8217 | |
29b0f896 AM |
8218 | size = 4; |
8219 | if (code16) | |
8220 | size = 2; | |
252b5132 | 8221 | |
f2810fe0 JB |
8222 | if (i.prefixes != 0) |
8223 | as_warn (_("skipping prefixes on `%s'"), i.tm.name); | |
252b5132 | 8224 | |
29b0f896 AM |
8225 | /* 1 opcode; 2 segment; offset */ |
8226 | p = frag_more (prefix + 1 + 2 + size); | |
3e73aa7c | 8227 | |
29b0f896 AM |
8228 | if (i.prefix[DATA_PREFIX] != 0) |
8229 | *p++ = DATA_PREFIX_OPCODE; | |
252b5132 | 8230 | |
29b0f896 AM |
8231 | if (i.prefix[REX_PREFIX] != 0) |
8232 | *p++ = i.prefix[REX_PREFIX]; | |
252b5132 | 8233 | |
29b0f896 AM |
8234 | *p++ = i.tm.base_opcode; |
8235 | if (i.op[1].imms->X_op == O_constant) | |
8236 | { | |
8237 | offsetT n = i.op[1].imms->X_add_number; | |
252b5132 | 8238 | |
29b0f896 AM |
8239 | if (size == 2 |
8240 | && !fits_in_unsigned_word (n) | |
8241 | && !fits_in_signed_word (n)) | |
8242 | { | |
8243 | as_bad (_("16-bit jump out of range")); | |
8244 | return; | |
8245 | } | |
8246 | md_number_to_chars (p, n, size); | |
8247 | } | |
8248 | else | |
8249 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
d258b828 | 8250 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); |
29b0f896 AM |
8251 | if (i.op[0].imms->X_op != O_constant) |
8252 | as_bad (_("can't handle non absolute segment in `%s'"), | |
8253 | i.tm.name); | |
8254 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); | |
8255 | } | |
a217f122 | 8256 | |
b4a3a7b4 L |
8257 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8258 | void | |
8259 | x86_cleanup (void) | |
8260 | { | |
8261 | char *p; | |
8262 | asection *seg = now_seg; | |
8263 | subsegT subseg = now_subseg; | |
8264 | asection *sec; | |
8265 | unsigned int alignment, align_size_1; | |
8266 | unsigned int isa_1_descsz, feature_2_descsz, descsz; | |
8267 | unsigned int isa_1_descsz_raw, feature_2_descsz_raw; | |
8268 | unsigned int padding; | |
8269 | ||
8270 | if (!IS_ELF || !x86_used_note) | |
8271 | return; | |
8272 | ||
b4a3a7b4 L |
8273 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X86; |
8274 | ||
8275 | /* The .note.gnu.property section layout: | |
8276 | ||
8277 | Field Length Contents | |
8278 | ---- ---- ---- | |
8279 | n_namsz 4 4 | |
8280 | n_descsz 4 The note descriptor size | |
8281 | n_type 4 NT_GNU_PROPERTY_TYPE_0 | |
8282 | n_name 4 "GNU" | |
8283 | n_desc n_descsz The program property array | |
8284 | .... .... .... | |
8285 | */ | |
8286 | ||
8287 | /* Create the .note.gnu.property section. */ | |
8288 | sec = subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME, 0); | |
fd361982 | 8289 | bfd_set_section_flags (sec, |
b4a3a7b4 L |
8290 | (SEC_ALLOC |
8291 | | SEC_LOAD | |
8292 | | SEC_DATA | |
8293 | | SEC_HAS_CONTENTS | |
8294 | | SEC_READONLY)); | |
8295 | ||
8296 | if (get_elf_backend_data (stdoutput)->s->elfclass == ELFCLASS64) | |
8297 | { | |
8298 | align_size_1 = 7; | |
8299 | alignment = 3; | |
8300 | } | |
8301 | else | |
8302 | { | |
8303 | align_size_1 = 3; | |
8304 | alignment = 2; | |
8305 | } | |
8306 | ||
fd361982 | 8307 | bfd_set_section_alignment (sec, alignment); |
b4a3a7b4 L |
8308 | elf_section_type (sec) = SHT_NOTE; |
8309 | ||
8310 | /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size | |
8311 | + 4-byte data */ | |
8312 | isa_1_descsz_raw = 4 + 4 + 4; | |
8313 | /* Align GNU_PROPERTY_X86_ISA_1_USED. */ | |
8314 | isa_1_descsz = (isa_1_descsz_raw + align_size_1) & ~align_size_1; | |
8315 | ||
8316 | feature_2_descsz_raw = isa_1_descsz; | |
8317 | /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size | |
8318 | + 4-byte data */ | |
8319 | feature_2_descsz_raw += 4 + 4 + 4; | |
8320 | /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */ | |
8321 | feature_2_descsz = ((feature_2_descsz_raw + align_size_1) | |
8322 | & ~align_size_1); | |
8323 | ||
8324 | descsz = feature_2_descsz; | |
8325 | /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */ | |
8326 | p = frag_more (4 + 4 + 4 + 4 + descsz); | |
8327 | ||
8328 | /* Write n_namsz. */ | |
8329 | md_number_to_chars (p, (valueT) 4, 4); | |
8330 | ||
8331 | /* Write n_descsz. */ | |
8332 | md_number_to_chars (p + 4, (valueT) descsz, 4); | |
8333 | ||
8334 | /* Write n_type. */ | |
8335 | md_number_to_chars (p + 4 * 2, (valueT) NT_GNU_PROPERTY_TYPE_0, 4); | |
8336 | ||
8337 | /* Write n_name. */ | |
8338 | memcpy (p + 4 * 3, "GNU", 4); | |
8339 | ||
8340 | /* Write 4-byte type. */ | |
8341 | md_number_to_chars (p + 4 * 4, | |
8342 | (valueT) GNU_PROPERTY_X86_ISA_1_USED, 4); | |
8343 | ||
8344 | /* Write 4-byte data size. */ | |
8345 | md_number_to_chars (p + 4 * 5, (valueT) 4, 4); | |
8346 | ||
8347 | /* Write 4-byte data. */ | |
8348 | md_number_to_chars (p + 4 * 6, (valueT) x86_isa_1_used, 4); | |
8349 | ||
8350 | /* Zero out paddings. */ | |
8351 | padding = isa_1_descsz - isa_1_descsz_raw; | |
8352 | if (padding) | |
8353 | memset (p + 4 * 7, 0, padding); | |
8354 | ||
8355 | /* Write 4-byte type. */ | |
8356 | md_number_to_chars (p + isa_1_descsz + 4 * 4, | |
8357 | (valueT) GNU_PROPERTY_X86_FEATURE_2_USED, 4); | |
8358 | ||
8359 | /* Write 4-byte data size. */ | |
8360 | md_number_to_chars (p + isa_1_descsz + 4 * 5, (valueT) 4, 4); | |
8361 | ||
8362 | /* Write 4-byte data. */ | |
8363 | md_number_to_chars (p + isa_1_descsz + 4 * 6, | |
8364 | (valueT) x86_feature_2_used, 4); | |
8365 | ||
8366 | /* Zero out paddings. */ | |
8367 | padding = feature_2_descsz - feature_2_descsz_raw; | |
8368 | if (padding) | |
8369 | memset (p + isa_1_descsz + 4 * 7, 0, padding); | |
8370 | ||
8371 | /* We probably can't restore the current segment, for there likely | |
8372 | isn't one yet... */ | |
8373 | if (seg && subseg) | |
8374 | subseg_set (seg, subseg); | |
8375 | } | |
8376 | #endif | |
8377 | ||
9c33702b JB |
8378 | static unsigned int |
8379 | encoding_length (const fragS *start_frag, offsetT start_off, | |
8380 | const char *frag_now_ptr) | |
8381 | { | |
8382 | unsigned int len = 0; | |
8383 | ||
8384 | if (start_frag != frag_now) | |
8385 | { | |
8386 | const fragS *fr = start_frag; | |
8387 | ||
8388 | do { | |
8389 | len += fr->fr_fix; | |
8390 | fr = fr->fr_next; | |
8391 | } while (fr && fr != frag_now); | |
8392 | } | |
8393 | ||
8394 | return len - start_off + (frag_now_ptr - frag_now->fr_literal); | |
8395 | } | |
8396 | ||
e379e5f3 | 8397 | /* Return 1 for test, and, cmp, add, sub, inc and dec which may |
79d72f45 HL |
8398 | be macro-fused with conditional jumps. |
8399 | NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address, | |
8400 | or is one of the following format: | |
8401 | ||
8402 | cmp m, imm | |
8403 | add m, imm | |
8404 | sub m, imm | |
8405 | test m, imm | |
8406 | and m, imm | |
8407 | inc m | |
8408 | dec m | |
8409 | ||
8410 | it is unfusible. */ | |
e379e5f3 L |
8411 | |
8412 | static int | |
79d72f45 | 8413 | maybe_fused_with_jcc_p (enum mf_cmp_kind* mf_cmp_p) |
e379e5f3 L |
8414 | { |
8415 | /* No RIP address. */ | |
8416 | if (i.base_reg && i.base_reg->reg_num == RegIP) | |
8417 | return 0; | |
8418 | ||
8419 | /* No VEX/EVEX encoding. */ | |
8420 | if (is_any_vex_encoding (&i.tm)) | |
8421 | return 0; | |
8422 | ||
79d72f45 HL |
8423 | /* add, sub without add/sub m, imm. */ |
8424 | if (i.tm.base_opcode <= 5 | |
e379e5f3 L |
8425 | || (i.tm.base_opcode >= 0x28 && i.tm.base_opcode <= 0x2d) |
8426 | || ((i.tm.base_opcode | 3) == 0x83 | |
79d72f45 | 8427 | && (i.tm.extension_opcode == 0x5 |
e379e5f3 | 8428 | || i.tm.extension_opcode == 0x0))) |
79d72f45 HL |
8429 | { |
8430 | *mf_cmp_p = mf_cmp_alu_cmp; | |
8431 | return !(i.mem_operands && i.imm_operands); | |
8432 | } | |
e379e5f3 | 8433 | |
79d72f45 HL |
8434 | /* and without and m, imm. */ |
8435 | if ((i.tm.base_opcode >= 0x20 && i.tm.base_opcode <= 0x25) | |
8436 | || ((i.tm.base_opcode | 3) == 0x83 | |
8437 | && i.tm.extension_opcode == 0x4)) | |
8438 | { | |
8439 | *mf_cmp_p = mf_cmp_test_and; | |
8440 | return !(i.mem_operands && i.imm_operands); | |
8441 | } | |
8442 | ||
8443 | /* test without test m imm. */ | |
e379e5f3 L |
8444 | if ((i.tm.base_opcode | 1) == 0x85 |
8445 | || (i.tm.base_opcode | 1) == 0xa9 | |
8446 | || ((i.tm.base_opcode | 1) == 0xf7 | |
79d72f45 HL |
8447 | && i.tm.extension_opcode == 0)) |
8448 | { | |
8449 | *mf_cmp_p = mf_cmp_test_and; | |
8450 | return !(i.mem_operands && i.imm_operands); | |
8451 | } | |
8452 | ||
8453 | /* cmp without cmp m, imm. */ | |
8454 | if ((i.tm.base_opcode >= 0x38 && i.tm.base_opcode <= 0x3d) | |
e379e5f3 L |
8455 | || ((i.tm.base_opcode | 3) == 0x83 |
8456 | && (i.tm.extension_opcode == 0x7))) | |
79d72f45 HL |
8457 | { |
8458 | *mf_cmp_p = mf_cmp_alu_cmp; | |
8459 | return !(i.mem_operands && i.imm_operands); | |
8460 | } | |
e379e5f3 | 8461 | |
79d72f45 | 8462 | /* inc, dec without inc/dec m. */ |
e379e5f3 L |
8463 | if ((i.tm.cpu_flags.bitfield.cpuno64 |
8464 | && (i.tm.base_opcode | 0xf) == 0x4f) | |
8465 | || ((i.tm.base_opcode | 1) == 0xff | |
8466 | && i.tm.extension_opcode <= 0x1)) | |
79d72f45 HL |
8467 | { |
8468 | *mf_cmp_p = mf_cmp_incdec; | |
8469 | return !i.mem_operands; | |
8470 | } | |
e379e5f3 L |
8471 | |
8472 | return 0; | |
8473 | } | |
8474 | ||
8475 | /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */ | |
8476 | ||
8477 | static int | |
79d72f45 | 8478 | add_fused_jcc_padding_frag_p (enum mf_cmp_kind* mf_cmp_p) |
e379e5f3 L |
8479 | { |
8480 | /* NB: Don't work with COND_JUMP86 without i386. */ | |
8481 | if (!align_branch_power | |
8482 | || now_seg == absolute_section | |
8483 | || !cpu_arch_flags.bitfield.cpui386 | |
8484 | || !(align_branch & align_branch_fused_bit)) | |
8485 | return 0; | |
8486 | ||
79d72f45 | 8487 | if (maybe_fused_with_jcc_p (mf_cmp_p)) |
e379e5f3 L |
8488 | { |
8489 | if (last_insn.kind == last_insn_other | |
8490 | || last_insn.seg != now_seg) | |
8491 | return 1; | |
8492 | if (flag_debug) | |
8493 | as_warn_where (last_insn.file, last_insn.line, | |
8494 | _("`%s` skips -malign-branch-boundary on `%s`"), | |
8495 | last_insn.name, i.tm.name); | |
8496 | } | |
8497 | ||
8498 | return 0; | |
8499 | } | |
8500 | ||
8501 | /* Return 1 if a BRANCH_PREFIX frag should be generated. */ | |
8502 | ||
8503 | static int | |
8504 | add_branch_prefix_frag_p (void) | |
8505 | { | |
8506 | /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix | |
8507 | to PadLock instructions since they include prefixes in opcode. */ | |
8508 | if (!align_branch_power | |
8509 | || !align_branch_prefix_size | |
8510 | || now_seg == absolute_section | |
8511 | || i.tm.cpu_flags.bitfield.cpupadlock | |
8512 | || !cpu_arch_flags.bitfield.cpui386) | |
8513 | return 0; | |
8514 | ||
8515 | /* Don't add prefix if it is a prefix or there is no operand in case | |
8516 | that segment prefix is special. */ | |
8517 | if (!i.operands || i.tm.opcode_modifier.isprefix) | |
8518 | return 0; | |
8519 | ||
8520 | if (last_insn.kind == last_insn_other | |
8521 | || last_insn.seg != now_seg) | |
8522 | return 1; | |
8523 | ||
8524 | if (flag_debug) | |
8525 | as_warn_where (last_insn.file, last_insn.line, | |
8526 | _("`%s` skips -malign-branch-boundary on `%s`"), | |
8527 | last_insn.name, i.tm.name); | |
8528 | ||
8529 | return 0; | |
8530 | } | |
8531 | ||
8532 | /* Return 1 if a BRANCH_PADDING frag should be generated. */ | |
8533 | ||
8534 | static int | |
79d72f45 HL |
8535 | add_branch_padding_frag_p (enum align_branch_kind *branch_p, |
8536 | enum mf_jcc_kind *mf_jcc_p) | |
e379e5f3 L |
8537 | { |
8538 | int add_padding; | |
8539 | ||
8540 | /* NB: Don't work with COND_JUMP86 without i386. */ | |
8541 | if (!align_branch_power | |
8542 | || now_seg == absolute_section | |
8543 | || !cpu_arch_flags.bitfield.cpui386) | |
8544 | return 0; | |
8545 | ||
8546 | add_padding = 0; | |
8547 | ||
8548 | /* Check for jcc and direct jmp. */ | |
8549 | if (i.tm.opcode_modifier.jump == JUMP) | |
8550 | { | |
8551 | if (i.tm.base_opcode == JUMP_PC_RELATIVE) | |
8552 | { | |
8553 | *branch_p = align_branch_jmp; | |
8554 | add_padding = align_branch & align_branch_jmp_bit; | |
8555 | } | |
8556 | else | |
8557 | { | |
79d72f45 HL |
8558 | /* Because J<cc> and JN<cc> share same group in macro-fusible table, |
8559 | igore the lowest bit. */ | |
8560 | *mf_jcc_p = (i.tm.base_opcode & 0x0e) >> 1; | |
e379e5f3 L |
8561 | *branch_p = align_branch_jcc; |
8562 | if ((align_branch & align_branch_jcc_bit)) | |
8563 | add_padding = 1; | |
8564 | } | |
8565 | } | |
8566 | else if (is_any_vex_encoding (&i.tm)) | |
8567 | return 0; | |
8568 | else if ((i.tm.base_opcode | 1) == 0xc3) | |
8569 | { | |
8570 | /* Near ret. */ | |
8571 | *branch_p = align_branch_ret; | |
8572 | if ((align_branch & align_branch_ret_bit)) | |
8573 | add_padding = 1; | |
8574 | } | |
8575 | else | |
8576 | { | |
8577 | /* Check for indirect jmp, direct and indirect calls. */ | |
8578 | if (i.tm.base_opcode == 0xe8) | |
8579 | { | |
8580 | /* Direct call. */ | |
8581 | *branch_p = align_branch_call; | |
8582 | if ((align_branch & align_branch_call_bit)) | |
8583 | add_padding = 1; | |
8584 | } | |
8585 | else if (i.tm.base_opcode == 0xff | |
8586 | && (i.tm.extension_opcode == 2 | |
8587 | || i.tm.extension_opcode == 4)) | |
8588 | { | |
8589 | /* Indirect call and jmp. */ | |
8590 | *branch_p = align_branch_indirect; | |
8591 | if ((align_branch & align_branch_indirect_bit)) | |
8592 | add_padding = 1; | |
8593 | } | |
8594 | ||
8595 | if (add_padding | |
8596 | && i.disp_operands | |
8597 | && tls_get_addr | |
8598 | && (i.op[0].disps->X_op == O_symbol | |
8599 | || (i.op[0].disps->X_op == O_subtract | |
8600 | && i.op[0].disps->X_op_symbol == GOT_symbol))) | |
8601 | { | |
8602 | symbolS *s = i.op[0].disps->X_add_symbol; | |
8603 | /* No padding to call to global or undefined tls_get_addr. */ | |
8604 | if ((S_IS_EXTERNAL (s) || !S_IS_DEFINED (s)) | |
8605 | && strcmp (S_GET_NAME (s), tls_get_addr) == 0) | |
8606 | return 0; | |
8607 | } | |
8608 | } | |
8609 | ||
8610 | if (add_padding | |
8611 | && last_insn.kind != last_insn_other | |
8612 | && last_insn.seg == now_seg) | |
8613 | { | |
8614 | if (flag_debug) | |
8615 | as_warn_where (last_insn.file, last_insn.line, | |
8616 | _("`%s` skips -malign-branch-boundary on `%s`"), | |
8617 | last_insn.name, i.tm.name); | |
8618 | return 0; | |
8619 | } | |
8620 | ||
8621 | return add_padding; | |
8622 | } | |
8623 | ||
29b0f896 | 8624 | static void |
e3bb37b5 | 8625 | output_insn (void) |
29b0f896 | 8626 | { |
2bbd9c25 JJ |
8627 | fragS *insn_start_frag; |
8628 | offsetT insn_start_off; | |
e379e5f3 L |
8629 | fragS *fragP = NULL; |
8630 | enum align_branch_kind branch = align_branch_none; | |
79d72f45 HL |
8631 | /* The initializer is arbitrary just to avoid uninitialized error. |
8632 | it's actually either assigned in add_branch_padding_frag_p | |
8633 | or never be used. */ | |
8634 | enum mf_jcc_kind mf_jcc = mf_jcc_jo; | |
2bbd9c25 | 8635 | |
b4a3a7b4 L |
8636 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8637 | if (IS_ELF && x86_used_note) | |
8638 | { | |
8639 | if (i.tm.cpu_flags.bitfield.cpucmov) | |
8640 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_CMOV; | |
8641 | if (i.tm.cpu_flags.bitfield.cpusse) | |
8642 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE; | |
8643 | if (i.tm.cpu_flags.bitfield.cpusse2) | |
8644 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE2; | |
8645 | if (i.tm.cpu_flags.bitfield.cpusse3) | |
8646 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE3; | |
8647 | if (i.tm.cpu_flags.bitfield.cpussse3) | |
8648 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSSE3; | |
8649 | if (i.tm.cpu_flags.bitfield.cpusse4_1) | |
8650 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_1; | |
8651 | if (i.tm.cpu_flags.bitfield.cpusse4_2) | |
8652 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_2; | |
8653 | if (i.tm.cpu_flags.bitfield.cpuavx) | |
8654 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX; | |
8655 | if (i.tm.cpu_flags.bitfield.cpuavx2) | |
8656 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX2; | |
8657 | if (i.tm.cpu_flags.bitfield.cpufma) | |
8658 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_FMA; | |
8659 | if (i.tm.cpu_flags.bitfield.cpuavx512f) | |
8660 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512F; | |
8661 | if (i.tm.cpu_flags.bitfield.cpuavx512cd) | |
8662 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512CD; | |
8663 | if (i.tm.cpu_flags.bitfield.cpuavx512er) | |
8664 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512ER; | |
8665 | if (i.tm.cpu_flags.bitfield.cpuavx512pf) | |
8666 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512PF; | |
8667 | if (i.tm.cpu_flags.bitfield.cpuavx512vl) | |
8668 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512VL; | |
8669 | if (i.tm.cpu_flags.bitfield.cpuavx512dq) | |
8670 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512DQ; | |
8671 | if (i.tm.cpu_flags.bitfield.cpuavx512bw) | |
8672 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512BW; | |
8673 | if (i.tm.cpu_flags.bitfield.cpuavx512_4fmaps) | |
8674 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS; | |
8675 | if (i.tm.cpu_flags.bitfield.cpuavx512_4vnniw) | |
8676 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW; | |
8677 | if (i.tm.cpu_flags.bitfield.cpuavx512_bitalg) | |
8678 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG; | |
8679 | if (i.tm.cpu_flags.bitfield.cpuavx512ifma) | |
8680 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA; | |
8681 | if (i.tm.cpu_flags.bitfield.cpuavx512vbmi) | |
8682 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI; | |
8683 | if (i.tm.cpu_flags.bitfield.cpuavx512_vbmi2) | |
8684 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2; | |
8685 | if (i.tm.cpu_flags.bitfield.cpuavx512_vnni) | |
8686 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI; | |
462cac58 L |
8687 | if (i.tm.cpu_flags.bitfield.cpuavx512_bf16) |
8688 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_BF16; | |
b4a3a7b4 L |
8689 | |
8690 | if (i.tm.cpu_flags.bitfield.cpu8087 | |
8691 | || i.tm.cpu_flags.bitfield.cpu287 | |
8692 | || i.tm.cpu_flags.bitfield.cpu387 | |
8693 | || i.tm.cpu_flags.bitfield.cpu687 | |
8694 | || i.tm.cpu_flags.bitfield.cpufisttp) | |
8695 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X87; | |
319ff62c JB |
8696 | if (i.has_regmmx |
8697 | || i.tm.base_opcode == 0xf77 /* emms */ | |
a7e12755 L |
8698 | || i.tm.base_opcode == 0xf0e /* femms */ |
8699 | || i.tm.base_opcode == 0xf2a /* cvtpi2ps */ | |
8700 | || i.tm.base_opcode == 0x660f2a /* cvtpi2pd */) | |
b4a3a7b4 L |
8701 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MMX; |
8702 | if (i.has_regxmm) | |
8703 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XMM; | |
8704 | if (i.has_regymm) | |
8705 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_YMM; | |
8706 | if (i.has_regzmm) | |
8707 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_ZMM; | |
8708 | if (i.tm.cpu_flags.bitfield.cpufxsr) | |
8709 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_FXSR; | |
8710 | if (i.tm.cpu_flags.bitfield.cpuxsave) | |
8711 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVE; | |
8712 | if (i.tm.cpu_flags.bitfield.cpuxsaveopt) | |
8713 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT; | |
8714 | if (i.tm.cpu_flags.bitfield.cpuxsavec) | |
8715 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEC; | |
8716 | } | |
8717 | #endif | |
8718 | ||
29b0f896 AM |
8719 | /* Tie dwarf2 debug info to the address at the start of the insn. |
8720 | We can't do this after the insn has been output as the current | |
8721 | frag may have been closed off. eg. by frag_var. */ | |
8722 | dwarf2_emit_insn (0); | |
8723 | ||
2bbd9c25 JJ |
8724 | insn_start_frag = frag_now; |
8725 | insn_start_off = frag_now_fix (); | |
8726 | ||
79d72f45 | 8727 | if (add_branch_padding_frag_p (&branch, &mf_jcc)) |
e379e5f3 L |
8728 | { |
8729 | char *p; | |
8730 | /* Branch can be 8 bytes. Leave some room for prefixes. */ | |
8731 | unsigned int max_branch_padding_size = 14; | |
8732 | ||
8733 | /* Align section to boundary. */ | |
8734 | record_alignment (now_seg, align_branch_power); | |
8735 | ||
8736 | /* Make room for padding. */ | |
8737 | frag_grow (max_branch_padding_size); | |
8738 | ||
8739 | /* Start of the padding. */ | |
8740 | p = frag_more (0); | |
8741 | ||
8742 | fragP = frag_now; | |
8743 | ||
8744 | frag_var (rs_machine_dependent, max_branch_padding_size, 0, | |
8745 | ENCODE_RELAX_STATE (BRANCH_PADDING, 0), | |
8746 | NULL, 0, p); | |
8747 | ||
79d72f45 | 8748 | fragP->tc_frag_data.mf_type = mf_jcc; |
e379e5f3 L |
8749 | fragP->tc_frag_data.branch_type = branch; |
8750 | fragP->tc_frag_data.max_bytes = max_branch_padding_size; | |
8751 | } | |
8752 | ||
29b0f896 | 8753 | /* Output jumps. */ |
0cfa3eb3 | 8754 | if (i.tm.opcode_modifier.jump == JUMP) |
29b0f896 | 8755 | output_branch (); |
0cfa3eb3 JB |
8756 | else if (i.tm.opcode_modifier.jump == JUMP_BYTE |
8757 | || i.tm.opcode_modifier.jump == JUMP_DWORD) | |
29b0f896 | 8758 | output_jump (); |
0cfa3eb3 | 8759 | else if (i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT) |
29b0f896 AM |
8760 | output_interseg_jump (); |
8761 | else | |
8762 | { | |
8763 | /* Output normal instructions here. */ | |
8764 | char *p; | |
8765 | unsigned char *q; | |
47465058 | 8766 | unsigned int j; |
331d2d0d | 8767 | unsigned int prefix; |
79d72f45 | 8768 | enum mf_cmp_kind mf_cmp; |
4dffcebc | 8769 | |
e4e00185 | 8770 | if (avoid_fence |
c3949f43 JB |
8771 | && (i.tm.base_opcode == 0xfaee8 |
8772 | || i.tm.base_opcode == 0xfaef0 | |
8773 | || i.tm.base_opcode == 0xfaef8)) | |
e4e00185 AS |
8774 | { |
8775 | /* Encode lfence, mfence, and sfence as | |
8776 | f0 83 04 24 00 lock addl $0x0, (%{re}sp). */ | |
8777 | offsetT val = 0x240483f0ULL; | |
8778 | p = frag_more (5); | |
8779 | md_number_to_chars (p, val, 5); | |
8780 | return; | |
8781 | } | |
8782 | ||
d022bddd IT |
8783 | /* Some processors fail on LOCK prefix. This options makes |
8784 | assembler ignore LOCK prefix and serves as a workaround. */ | |
8785 | if (omit_lock_prefix) | |
8786 | { | |
8787 | if (i.tm.base_opcode == LOCK_PREFIX_OPCODE) | |
8788 | return; | |
8789 | i.prefix[LOCK_PREFIX] = 0; | |
8790 | } | |
8791 | ||
e379e5f3 L |
8792 | if (branch) |
8793 | /* Skip if this is a branch. */ | |
8794 | ; | |
79d72f45 | 8795 | else if (add_fused_jcc_padding_frag_p (&mf_cmp)) |
e379e5f3 L |
8796 | { |
8797 | /* Make room for padding. */ | |
8798 | frag_grow (MAX_FUSED_JCC_PADDING_SIZE); | |
8799 | p = frag_more (0); | |
8800 | ||
8801 | fragP = frag_now; | |
8802 | ||
8803 | frag_var (rs_machine_dependent, MAX_FUSED_JCC_PADDING_SIZE, 0, | |
8804 | ENCODE_RELAX_STATE (FUSED_JCC_PADDING, 0), | |
8805 | NULL, 0, p); | |
8806 | ||
79d72f45 | 8807 | fragP->tc_frag_data.mf_type = mf_cmp; |
e379e5f3 L |
8808 | fragP->tc_frag_data.branch_type = align_branch_fused; |
8809 | fragP->tc_frag_data.max_bytes = MAX_FUSED_JCC_PADDING_SIZE; | |
8810 | } | |
8811 | else if (add_branch_prefix_frag_p ()) | |
8812 | { | |
8813 | unsigned int max_prefix_size = align_branch_prefix_size; | |
8814 | ||
8815 | /* Make room for padding. */ | |
8816 | frag_grow (max_prefix_size); | |
8817 | p = frag_more (0); | |
8818 | ||
8819 | fragP = frag_now; | |
8820 | ||
8821 | frag_var (rs_machine_dependent, max_prefix_size, 0, | |
8822 | ENCODE_RELAX_STATE (BRANCH_PREFIX, 0), | |
8823 | NULL, 0, p); | |
8824 | ||
8825 | fragP->tc_frag_data.max_bytes = max_prefix_size; | |
8826 | } | |
8827 | ||
43234a1e L |
8828 | /* Since the VEX/EVEX prefix contains the implicit prefix, we |
8829 | don't need the explicit prefix. */ | |
8830 | if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex) | |
bc4bd9ab | 8831 | { |
c0f3af97 | 8832 | switch (i.tm.opcode_length) |
bc4bd9ab | 8833 | { |
c0f3af97 L |
8834 | case 3: |
8835 | if (i.tm.base_opcode & 0xff000000) | |
4dffcebc | 8836 | { |
c0f3af97 | 8837 | prefix = (i.tm.base_opcode >> 24) & 0xff; |
c3949f43 JB |
8838 | if (!i.tm.cpu_flags.bitfield.cpupadlock |
8839 | || prefix != REPE_PREFIX_OPCODE | |
8840 | || (i.prefix[REP_PREFIX] != REPE_PREFIX_OPCODE)) | |
8841 | add_prefix (prefix); | |
c0f3af97 L |
8842 | } |
8843 | break; | |
8844 | case 2: | |
8845 | if ((i.tm.base_opcode & 0xff0000) != 0) | |
8846 | { | |
8847 | prefix = (i.tm.base_opcode >> 16) & 0xff; | |
c3949f43 | 8848 | add_prefix (prefix); |
4dffcebc | 8849 | } |
c0f3af97 L |
8850 | break; |
8851 | case 1: | |
8852 | break; | |
390c91cf L |
8853 | case 0: |
8854 | /* Check for pseudo prefixes. */ | |
8855 | as_bad_where (insn_start_frag->fr_file, | |
8856 | insn_start_frag->fr_line, | |
8857 | _("pseudo prefix without instruction")); | |
8858 | return; | |
c0f3af97 L |
8859 | default: |
8860 | abort (); | |
bc4bd9ab | 8861 | } |
c0f3af97 | 8862 | |
6d19a37a | 8863 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
cf61b747 L |
8864 | /* For x32, add a dummy REX_OPCODE prefix for mov/add with |
8865 | R_X86_64_GOTTPOFF relocation so that linker can safely | |
14470f07 L |
8866 | perform IE->LE optimization. A dummy REX_OPCODE prefix |
8867 | is also needed for lea with R_X86_64_GOTPC32_TLSDESC | |
8868 | relocation for GDesc -> IE/LE optimization. */ | |
cf61b747 L |
8869 | if (x86_elf_abi == X86_64_X32_ABI |
8870 | && i.operands == 2 | |
14470f07 L |
8871 | && (i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF |
8872 | || i.reloc[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC) | |
cf61b747 L |
8873 | && i.prefix[REX_PREFIX] == 0) |
8874 | add_prefix (REX_OPCODE); | |
6d19a37a | 8875 | #endif |
cf61b747 | 8876 | |
c0f3af97 L |
8877 | /* The prefix bytes. */ |
8878 | for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) | |
8879 | if (*q) | |
8880 | FRAG_APPEND_1_CHAR (*q); | |
0f10071e | 8881 | } |
ae5c1c7b | 8882 | else |
c0f3af97 L |
8883 | { |
8884 | for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++) | |
8885 | if (*q) | |
8886 | switch (j) | |
8887 | { | |
8888 | case REX_PREFIX: | |
8889 | /* REX byte is encoded in VEX prefix. */ | |
8890 | break; | |
8891 | case SEG_PREFIX: | |
8892 | case ADDR_PREFIX: | |
8893 | FRAG_APPEND_1_CHAR (*q); | |
8894 | break; | |
8895 | default: | |
8896 | /* There should be no other prefixes for instructions | |
8897 | with VEX prefix. */ | |
8898 | abort (); | |
8899 | } | |
8900 | ||
43234a1e L |
8901 | /* For EVEX instructions i.vrex should become 0 after |
8902 | build_evex_prefix. For VEX instructions upper 16 registers | |
8903 | aren't available, so VREX should be 0. */ | |
8904 | if (i.vrex) | |
8905 | abort (); | |
c0f3af97 L |
8906 | /* Now the VEX prefix. */ |
8907 | p = frag_more (i.vex.length); | |
8908 | for (j = 0; j < i.vex.length; j++) | |
8909 | p[j] = i.vex.bytes[j]; | |
8910 | } | |
252b5132 | 8911 | |
29b0f896 | 8912 | /* Now the opcode; be careful about word order here! */ |
4dffcebc | 8913 | if (i.tm.opcode_length == 1) |
29b0f896 AM |
8914 | { |
8915 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
8916 | } | |
8917 | else | |
8918 | { | |
4dffcebc | 8919 | switch (i.tm.opcode_length) |
331d2d0d | 8920 | { |
43234a1e L |
8921 | case 4: |
8922 | p = frag_more (4); | |
8923 | *p++ = (i.tm.base_opcode >> 24) & 0xff; | |
8924 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
8925 | break; | |
4dffcebc | 8926 | case 3: |
331d2d0d L |
8927 | p = frag_more (3); |
8928 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
4dffcebc L |
8929 | break; |
8930 | case 2: | |
8931 | p = frag_more (2); | |
8932 | break; | |
8933 | default: | |
8934 | abort (); | |
8935 | break; | |
331d2d0d | 8936 | } |
0f10071e | 8937 | |
29b0f896 AM |
8938 | /* Put out high byte first: can't use md_number_to_chars! */ |
8939 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
8940 | *p = i.tm.base_opcode & 0xff; | |
8941 | } | |
3e73aa7c | 8942 | |
29b0f896 | 8943 | /* Now the modrm byte and sib byte (if present). */ |
40fb9820 | 8944 | if (i.tm.opcode_modifier.modrm) |
29b0f896 | 8945 | { |
4a3523fa L |
8946 | FRAG_APPEND_1_CHAR ((i.rm.regmem << 0 |
8947 | | i.rm.reg << 3 | |
8948 | | i.rm.mode << 6)); | |
29b0f896 AM |
8949 | /* If i.rm.regmem == ESP (4) |
8950 | && i.rm.mode != (Register mode) | |
8951 | && not 16 bit | |
8952 | ==> need second modrm byte. */ | |
8953 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
8954 | && i.rm.mode != 3 | |
dc821c5f | 8955 | && !(i.base_reg && i.base_reg->reg_type.bitfield.word)) |
4a3523fa L |
8956 | FRAG_APPEND_1_CHAR ((i.sib.base << 0 |
8957 | | i.sib.index << 3 | |
8958 | | i.sib.scale << 6)); | |
29b0f896 | 8959 | } |
3e73aa7c | 8960 | |
29b0f896 | 8961 | if (i.disp_operands) |
2bbd9c25 | 8962 | output_disp (insn_start_frag, insn_start_off); |
3e73aa7c | 8963 | |
29b0f896 | 8964 | if (i.imm_operands) |
2bbd9c25 | 8965 | output_imm (insn_start_frag, insn_start_off); |
9c33702b JB |
8966 | |
8967 | /* | |
8968 | * frag_now_fix () returning plain abs_section_offset when we're in the | |
8969 | * absolute section, and abs_section_offset not getting updated as data | |
8970 | * gets added to the frag breaks the logic below. | |
8971 | */ | |
8972 | if (now_seg != absolute_section) | |
8973 | { | |
8974 | j = encoding_length (insn_start_frag, insn_start_off, frag_more (0)); | |
8975 | if (j > 15) | |
8976 | as_warn (_("instruction length of %u bytes exceeds the limit of 15"), | |
8977 | j); | |
e379e5f3 L |
8978 | else if (fragP) |
8979 | { | |
8980 | /* NB: Don't add prefix with GOTPC relocation since | |
8981 | output_disp() above depends on the fixed encoding | |
8982 | length. Can't add prefix with TLS relocation since | |
8983 | it breaks TLS linker optimization. */ | |
8984 | unsigned int max = i.has_gotpc_tls_reloc ? 0 : 15 - j; | |
8985 | /* Prefix count on the current instruction. */ | |
8986 | unsigned int count = i.vex.length; | |
8987 | unsigned int k; | |
8988 | for (k = 0; k < ARRAY_SIZE (i.prefix); k++) | |
8989 | /* REX byte is encoded in VEX/EVEX prefix. */ | |
8990 | if (i.prefix[k] && (k != REX_PREFIX || !i.vex.length)) | |
8991 | count++; | |
8992 | ||
8993 | /* Count prefixes for extended opcode maps. */ | |
8994 | if (!i.vex.length) | |
8995 | switch (i.tm.opcode_length) | |
8996 | { | |
8997 | case 3: | |
8998 | if (((i.tm.base_opcode >> 16) & 0xff) == 0xf) | |
8999 | { | |
9000 | count++; | |
9001 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
9002 | { | |
9003 | case 0x38: | |
9004 | case 0x3a: | |
9005 | count++; | |
9006 | break; | |
9007 | default: | |
9008 | break; | |
9009 | } | |
9010 | } | |
9011 | break; | |
9012 | case 2: | |
9013 | if (((i.tm.base_opcode >> 8) & 0xff) == 0xf) | |
9014 | count++; | |
9015 | break; | |
9016 | case 1: | |
9017 | break; | |
9018 | default: | |
9019 | abort (); | |
9020 | } | |
9021 | ||
9022 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
9023 | == BRANCH_PREFIX) | |
9024 | { | |
9025 | /* Set the maximum prefix size in BRANCH_PREFIX | |
9026 | frag. */ | |
9027 | if (fragP->tc_frag_data.max_bytes > max) | |
9028 | fragP->tc_frag_data.max_bytes = max; | |
9029 | if (fragP->tc_frag_data.max_bytes > count) | |
9030 | fragP->tc_frag_data.max_bytes -= count; | |
9031 | else | |
9032 | fragP->tc_frag_data.max_bytes = 0; | |
9033 | } | |
9034 | else | |
9035 | { | |
9036 | /* Remember the maximum prefix size in FUSED_JCC_PADDING | |
9037 | frag. */ | |
9038 | unsigned int max_prefix_size; | |
9039 | if (align_branch_prefix_size > max) | |
9040 | max_prefix_size = max; | |
9041 | else | |
9042 | max_prefix_size = align_branch_prefix_size; | |
9043 | if (max_prefix_size > count) | |
9044 | fragP->tc_frag_data.max_prefix_length | |
9045 | = max_prefix_size - count; | |
9046 | } | |
9047 | ||
9048 | /* Use existing segment prefix if possible. Use CS | |
9049 | segment prefix in 64-bit mode. In 32-bit mode, use SS | |
9050 | segment prefix with ESP/EBP base register and use DS | |
9051 | segment prefix without ESP/EBP base register. */ | |
9052 | if (i.prefix[SEG_PREFIX]) | |
9053 | fragP->tc_frag_data.default_prefix = i.prefix[SEG_PREFIX]; | |
9054 | else if (flag_code == CODE_64BIT) | |
9055 | fragP->tc_frag_data.default_prefix = CS_PREFIX_OPCODE; | |
9056 | else if (i.base_reg | |
9057 | && (i.base_reg->reg_num == 4 | |
9058 | || i.base_reg->reg_num == 5)) | |
9059 | fragP->tc_frag_data.default_prefix = SS_PREFIX_OPCODE; | |
9060 | else | |
9061 | fragP->tc_frag_data.default_prefix = DS_PREFIX_OPCODE; | |
9062 | } | |
9c33702b | 9063 | } |
29b0f896 | 9064 | } |
252b5132 | 9065 | |
e379e5f3 L |
9066 | /* NB: Don't work with COND_JUMP86 without i386. */ |
9067 | if (align_branch_power | |
9068 | && now_seg != absolute_section | |
9069 | && cpu_arch_flags.bitfield.cpui386) | |
9070 | { | |
9071 | /* Terminate each frag so that we can add prefix and check for | |
9072 | fused jcc. */ | |
9073 | frag_wane (frag_now); | |
9074 | frag_new (0); | |
9075 | } | |
9076 | ||
29b0f896 AM |
9077 | #ifdef DEBUG386 |
9078 | if (flag_debug) | |
9079 | { | |
7b81dfbb | 9080 | pi ("" /*line*/, &i); |
29b0f896 AM |
9081 | } |
9082 | #endif /* DEBUG386 */ | |
9083 | } | |
252b5132 | 9084 | |
e205caa7 L |
9085 | /* Return the size of the displacement operand N. */ |
9086 | ||
9087 | static int | |
9088 | disp_size (unsigned int n) | |
9089 | { | |
9090 | int size = 4; | |
43234a1e | 9091 | |
b5014f7a | 9092 | if (i.types[n].bitfield.disp64) |
40fb9820 L |
9093 | size = 8; |
9094 | else if (i.types[n].bitfield.disp8) | |
9095 | size = 1; | |
9096 | else if (i.types[n].bitfield.disp16) | |
9097 | size = 2; | |
e205caa7 L |
9098 | return size; |
9099 | } | |
9100 | ||
9101 | /* Return the size of the immediate operand N. */ | |
9102 | ||
9103 | static int | |
9104 | imm_size (unsigned int n) | |
9105 | { | |
9106 | int size = 4; | |
40fb9820 L |
9107 | if (i.types[n].bitfield.imm64) |
9108 | size = 8; | |
9109 | else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) | |
9110 | size = 1; | |
9111 | else if (i.types[n].bitfield.imm16) | |
9112 | size = 2; | |
e205caa7 L |
9113 | return size; |
9114 | } | |
9115 | ||
29b0f896 | 9116 | static void |
64e74474 | 9117 | output_disp (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
9118 | { |
9119 | char *p; | |
9120 | unsigned int n; | |
252b5132 | 9121 | |
29b0f896 AM |
9122 | for (n = 0; n < i.operands; n++) |
9123 | { | |
b5014f7a | 9124 | if (operand_type_check (i.types[n], disp)) |
29b0f896 AM |
9125 | { |
9126 | if (i.op[n].disps->X_op == O_constant) | |
9127 | { | |
e205caa7 | 9128 | int size = disp_size (n); |
43234a1e | 9129 | offsetT val = i.op[n].disps->X_add_number; |
252b5132 | 9130 | |
629cfaf1 JB |
9131 | val = offset_in_range (val >> (size == 1 ? i.memshift : 0), |
9132 | size); | |
29b0f896 AM |
9133 | p = frag_more (size); |
9134 | md_number_to_chars (p, val, size); | |
9135 | } | |
9136 | else | |
9137 | { | |
f86103b7 | 9138 | enum bfd_reloc_code_real reloc_type; |
e205caa7 | 9139 | int size = disp_size (n); |
40fb9820 | 9140 | int sign = i.types[n].bitfield.disp32s; |
29b0f896 | 9141 | int pcrel = (i.flags[n] & Operand_PCrel) != 0; |
02a86693 | 9142 | fixS *fixP; |
29b0f896 | 9143 | |
e205caa7 | 9144 | /* We can't have 8 bit displacement here. */ |
9c2799c2 | 9145 | gas_assert (!i.types[n].bitfield.disp8); |
e205caa7 | 9146 | |
29b0f896 AM |
9147 | /* The PC relative address is computed relative |
9148 | to the instruction boundary, so in case immediate | |
9149 | fields follows, we need to adjust the value. */ | |
9150 | if (pcrel && i.imm_operands) | |
9151 | { | |
29b0f896 | 9152 | unsigned int n1; |
e205caa7 | 9153 | int sz = 0; |
252b5132 | 9154 | |
29b0f896 | 9155 | for (n1 = 0; n1 < i.operands; n1++) |
40fb9820 | 9156 | if (operand_type_check (i.types[n1], imm)) |
252b5132 | 9157 | { |
e205caa7 L |
9158 | /* Only one immediate is allowed for PC |
9159 | relative address. */ | |
9c2799c2 | 9160 | gas_assert (sz == 0); |
e205caa7 L |
9161 | sz = imm_size (n1); |
9162 | i.op[n].disps->X_add_number -= sz; | |
252b5132 | 9163 | } |
29b0f896 | 9164 | /* We should find the immediate. */ |
9c2799c2 | 9165 | gas_assert (sz != 0); |
29b0f896 | 9166 | } |
520dc8e8 | 9167 | |
29b0f896 | 9168 | p = frag_more (size); |
d258b828 | 9169 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
d6ab8113 | 9170 | if (GOT_symbol |
2bbd9c25 | 9171 | && GOT_symbol == i.op[n].disps->X_add_symbol |
d6ab8113 | 9172 | && (((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
9173 | || reloc_type == BFD_RELOC_X86_64_32S |
9174 | || (reloc_type == BFD_RELOC_64 | |
9175 | && object_64bit)) | |
d6ab8113 JB |
9176 | && (i.op[n].disps->X_op == O_symbol |
9177 | || (i.op[n].disps->X_op == O_add | |
9178 | && ((symbol_get_value_expression | |
9179 | (i.op[n].disps->X_op_symbol)->X_op) | |
9180 | == O_subtract)))) | |
9181 | || reloc_type == BFD_RELOC_32_PCREL)) | |
2bbd9c25 | 9182 | { |
4fa24527 | 9183 | if (!object_64bit) |
7b81dfbb AJ |
9184 | { |
9185 | reloc_type = BFD_RELOC_386_GOTPC; | |
e379e5f3 | 9186 | i.has_gotpc_tls_reloc = TRUE; |
d583596c JB |
9187 | i.op[n].imms->X_add_number += |
9188 | encoding_length (insn_start_frag, insn_start_off, p); | |
7b81dfbb AJ |
9189 | } |
9190 | else if (reloc_type == BFD_RELOC_64) | |
9191 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
d6ab8113 | 9192 | else |
7b81dfbb AJ |
9193 | /* Don't do the adjustment for x86-64, as there |
9194 | the pcrel addressing is relative to the _next_ | |
9195 | insn, and that is taken care of in other code. */ | |
d6ab8113 | 9196 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
2bbd9c25 | 9197 | } |
e379e5f3 L |
9198 | else if (align_branch_power) |
9199 | { | |
9200 | switch (reloc_type) | |
9201 | { | |
9202 | case BFD_RELOC_386_TLS_GD: | |
9203 | case BFD_RELOC_386_TLS_LDM: | |
9204 | case BFD_RELOC_386_TLS_IE: | |
9205 | case BFD_RELOC_386_TLS_IE_32: | |
9206 | case BFD_RELOC_386_TLS_GOTIE: | |
9207 | case BFD_RELOC_386_TLS_GOTDESC: | |
9208 | case BFD_RELOC_386_TLS_DESC_CALL: | |
9209 | case BFD_RELOC_X86_64_TLSGD: | |
9210 | case BFD_RELOC_X86_64_TLSLD: | |
9211 | case BFD_RELOC_X86_64_GOTTPOFF: | |
9212 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: | |
9213 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
9214 | i.has_gotpc_tls_reloc = TRUE; | |
9215 | default: | |
9216 | break; | |
9217 | } | |
9218 | } | |
02a86693 L |
9219 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, |
9220 | size, i.op[n].disps, pcrel, | |
9221 | reloc_type); | |
9222 | /* Check for "call/jmp *mem", "mov mem, %reg", | |
9223 | "test %reg, mem" and "binop mem, %reg" where binop | |
9224 | is one of adc, add, and, cmp, or, sbb, sub, xor | |
e60f4d3b L |
9225 | instructions without data prefix. Always generate |
9226 | R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */ | |
9227 | if (i.prefix[DATA_PREFIX] == 0 | |
9228 | && (generate_relax_relocations | |
9229 | || (!object_64bit | |
9230 | && i.rm.mode == 0 | |
9231 | && i.rm.regmem == 5)) | |
0cb4071e L |
9232 | && (i.rm.mode == 2 |
9233 | || (i.rm.mode == 0 && i.rm.regmem == 5)) | |
2ae4c703 | 9234 | && !is_any_vex_encoding(&i.tm) |
02a86693 L |
9235 | && ((i.operands == 1 |
9236 | && i.tm.base_opcode == 0xff | |
9237 | && (i.rm.reg == 2 || i.rm.reg == 4)) | |
9238 | || (i.operands == 2 | |
9239 | && (i.tm.base_opcode == 0x8b | |
9240 | || i.tm.base_opcode == 0x85 | |
2ae4c703 | 9241 | || (i.tm.base_opcode & ~0x38) == 0x03)))) |
02a86693 L |
9242 | { |
9243 | if (object_64bit) | |
9244 | { | |
9245 | fixP->fx_tcbit = i.rex != 0; | |
9246 | if (i.base_reg | |
e968fc9b | 9247 | && (i.base_reg->reg_num == RegIP)) |
02a86693 L |
9248 | fixP->fx_tcbit2 = 1; |
9249 | } | |
9250 | else | |
9251 | fixP->fx_tcbit2 = 1; | |
9252 | } | |
29b0f896 AM |
9253 | } |
9254 | } | |
9255 | } | |
9256 | } | |
252b5132 | 9257 | |
29b0f896 | 9258 | static void |
64e74474 | 9259 | output_imm (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
9260 | { |
9261 | char *p; | |
9262 | unsigned int n; | |
252b5132 | 9263 | |
29b0f896 AM |
9264 | for (n = 0; n < i.operands; n++) |
9265 | { | |
43234a1e L |
9266 | /* Skip SAE/RC Imm operand in EVEX. They are already handled. */ |
9267 | if (i.rounding && (int) n == i.rounding->operand) | |
9268 | continue; | |
9269 | ||
40fb9820 | 9270 | if (operand_type_check (i.types[n], imm)) |
29b0f896 AM |
9271 | { |
9272 | if (i.op[n].imms->X_op == O_constant) | |
9273 | { | |
e205caa7 | 9274 | int size = imm_size (n); |
29b0f896 | 9275 | offsetT val; |
b4cac588 | 9276 | |
29b0f896 AM |
9277 | val = offset_in_range (i.op[n].imms->X_add_number, |
9278 | size); | |
9279 | p = frag_more (size); | |
9280 | md_number_to_chars (p, val, size); | |
9281 | } | |
9282 | else | |
9283 | { | |
9284 | /* Not absolute_section. | |
9285 | Need a 32-bit fixup (don't support 8bit | |
9286 | non-absolute imms). Try to support other | |
9287 | sizes ... */ | |
f86103b7 | 9288 | enum bfd_reloc_code_real reloc_type; |
e205caa7 L |
9289 | int size = imm_size (n); |
9290 | int sign; | |
29b0f896 | 9291 | |
40fb9820 | 9292 | if (i.types[n].bitfield.imm32s |
a7d61044 | 9293 | && (i.suffix == QWORD_MNEM_SUFFIX |
40fb9820 | 9294 | || (!i.suffix && i.tm.opcode_modifier.no_lsuf))) |
29b0f896 | 9295 | sign = 1; |
e205caa7 L |
9296 | else |
9297 | sign = 0; | |
520dc8e8 | 9298 | |
29b0f896 | 9299 | p = frag_more (size); |
d258b828 | 9300 | reloc_type = reloc (size, 0, sign, i.reloc[n]); |
f86103b7 | 9301 | |
2bbd9c25 JJ |
9302 | /* This is tough to explain. We end up with this one if we |
9303 | * have operands that look like | |
9304 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to | |
9305 | * obtain the absolute address of the GOT, and it is strongly | |
9306 | * preferable from a performance point of view to avoid using | |
9307 | * a runtime relocation for this. The actual sequence of | |
9308 | * instructions often look something like: | |
9309 | * | |
9310 | * call .L66 | |
9311 | * .L66: | |
9312 | * popl %ebx | |
9313 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
9314 | * | |
9315 | * The call and pop essentially return the absolute address | |
9316 | * of the label .L66 and store it in %ebx. The linker itself | |
9317 | * will ultimately change the first operand of the addl so | |
9318 | * that %ebx points to the GOT, but to keep things simple, the | |
9319 | * .o file must have this operand set so that it generates not | |
9320 | * the absolute address of .L66, but the absolute address of | |
9321 | * itself. This allows the linker itself simply treat a GOTPC | |
9322 | * relocation as asking for a pcrel offset to the GOT to be | |
9323 | * added in, and the addend of the relocation is stored in the | |
9324 | * operand field for the instruction itself. | |
9325 | * | |
9326 | * Our job here is to fix the operand so that it would add | |
9327 | * the correct offset so that %ebx would point to itself. The | |
9328 | * thing that is tricky is that .-.L66 will point to the | |
9329 | * beginning of the instruction, so we need to further modify | |
9330 | * the operand so that it will point to itself. There are | |
9331 | * other cases where you have something like: | |
9332 | * | |
9333 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
9334 | * | |
9335 | * and here no correction would be required. Internally in | |
9336 | * the assembler we treat operands of this form as not being | |
9337 | * pcrel since the '.' is explicitly mentioned, and I wonder | |
9338 | * whether it would simplify matters to do it this way. Who | |
9339 | * knows. In earlier versions of the PIC patches, the | |
9340 | * pcrel_adjust field was used to store the correction, but | |
9341 | * since the expression is not pcrel, I felt it would be | |
9342 | * confusing to do it this way. */ | |
9343 | ||
d6ab8113 | 9344 | if ((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
9345 | || reloc_type == BFD_RELOC_X86_64_32S |
9346 | || reloc_type == BFD_RELOC_64) | |
29b0f896 AM |
9347 | && GOT_symbol |
9348 | && GOT_symbol == i.op[n].imms->X_add_symbol | |
9349 | && (i.op[n].imms->X_op == O_symbol | |
9350 | || (i.op[n].imms->X_op == O_add | |
9351 | && ((symbol_get_value_expression | |
9352 | (i.op[n].imms->X_op_symbol)->X_op) | |
9353 | == O_subtract)))) | |
9354 | { | |
4fa24527 | 9355 | if (!object_64bit) |
d6ab8113 | 9356 | reloc_type = BFD_RELOC_386_GOTPC; |
7b81dfbb | 9357 | else if (size == 4) |
d6ab8113 | 9358 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
7b81dfbb AJ |
9359 | else if (size == 8) |
9360 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
e379e5f3 | 9361 | i.has_gotpc_tls_reloc = TRUE; |
d583596c JB |
9362 | i.op[n].imms->X_add_number += |
9363 | encoding_length (insn_start_frag, insn_start_off, p); | |
29b0f896 | 9364 | } |
29b0f896 AM |
9365 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
9366 | i.op[n].imms, 0, reloc_type); | |
9367 | } | |
9368 | } | |
9369 | } | |
252b5132 RH |
9370 | } |
9371 | \f | |
d182319b JB |
9372 | /* x86_cons_fix_new is called via the expression parsing code when a |
9373 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
d182319b JB |
9374 | static int cons_sign = -1; |
9375 | ||
9376 | void | |
e3bb37b5 | 9377 | x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, |
62ebcb5c | 9378 | expressionS *exp, bfd_reloc_code_real_type r) |
d182319b | 9379 | { |
d258b828 | 9380 | r = reloc (len, 0, cons_sign, r); |
d182319b JB |
9381 | |
9382 | #ifdef TE_PE | |
9383 | if (exp->X_op == O_secrel) | |
9384 | { | |
9385 | exp->X_op = O_symbol; | |
9386 | r = BFD_RELOC_32_SECREL; | |
9387 | } | |
9388 | #endif | |
9389 | ||
9390 | fix_new_exp (frag, off, len, exp, 0, r); | |
9391 | } | |
9392 | ||
357d1bd8 L |
9393 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
9394 | purpose of the `.dc.a' internal pseudo-op. */ | |
9395 | ||
9396 | int | |
9397 | x86_address_bytes (void) | |
9398 | { | |
9399 | if ((stdoutput->arch_info->mach & bfd_mach_x64_32)) | |
9400 | return 4; | |
9401 | return stdoutput->arch_info->bits_per_address / 8; | |
9402 | } | |
9403 | ||
d382c579 TG |
9404 | #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \ |
9405 | || defined (LEX_AT) | |
d258b828 | 9406 | # define lex_got(reloc, adjust, types) NULL |
718ddfc0 | 9407 | #else |
f3c180ae AM |
9408 | /* Parse operands of the form |
9409 | <symbol>@GOTOFF+<nnn> | |
9410 | and similar .plt or .got references. | |
9411 | ||
9412 | If we find one, set up the correct relocation in RELOC and copy the | |
9413 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
9414 | parsing by the calling routine. Return this buffer, and if ADJUST | |
9415 | is non-null set it to the length of the string we removed from the | |
9416 | input line. Otherwise return NULL. */ | |
9417 | static char * | |
91d6fa6a | 9418 | lex_got (enum bfd_reloc_code_real *rel, |
64e74474 | 9419 | int *adjust, |
d258b828 | 9420 | i386_operand_type *types) |
f3c180ae | 9421 | { |
7b81dfbb AJ |
9422 | /* Some of the relocations depend on the size of what field is to |
9423 | be relocated. But in our callers i386_immediate and i386_displacement | |
9424 | we don't yet know the operand size (this will be set by insn | |
9425 | matching). Hence we record the word32 relocation here, | |
9426 | and adjust the reloc according to the real size in reloc(). */ | |
f3c180ae AM |
9427 | static const struct { |
9428 | const char *str; | |
cff8d58a | 9429 | int len; |
4fa24527 | 9430 | const enum bfd_reloc_code_real rel[2]; |
40fb9820 | 9431 | const i386_operand_type types64; |
f3c180ae | 9432 | } gotrel[] = { |
8ce3d284 | 9433 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
9434 | { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32, |
9435 | BFD_RELOC_SIZE32 }, | |
9436 | OPERAND_TYPE_IMM32_64 }, | |
8ce3d284 | 9437 | #endif |
cff8d58a L |
9438 | { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real, |
9439 | BFD_RELOC_X86_64_PLTOFF64 }, | |
40fb9820 | 9440 | OPERAND_TYPE_IMM64 }, |
cff8d58a L |
9441 | { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32, |
9442 | BFD_RELOC_X86_64_PLT32 }, | |
40fb9820 | 9443 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
9444 | { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real, |
9445 | BFD_RELOC_X86_64_GOTPLT64 }, | |
40fb9820 | 9446 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
9447 | { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF, |
9448 | BFD_RELOC_X86_64_GOTOFF64 }, | |
40fb9820 | 9449 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
9450 | { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real, |
9451 | BFD_RELOC_X86_64_GOTPCREL }, | |
40fb9820 | 9452 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
9453 | { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD, |
9454 | BFD_RELOC_X86_64_TLSGD }, | |
40fb9820 | 9455 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
9456 | { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM, |
9457 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 9458 | OPERAND_TYPE_NONE }, |
cff8d58a L |
9459 | { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real, |
9460 | BFD_RELOC_X86_64_TLSLD }, | |
40fb9820 | 9461 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
9462 | { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32, |
9463 | BFD_RELOC_X86_64_GOTTPOFF }, | |
40fb9820 | 9464 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
9465 | { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32, |
9466 | BFD_RELOC_X86_64_TPOFF32 }, | |
40fb9820 | 9467 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
9468 | { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE, |
9469 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 9470 | OPERAND_TYPE_NONE }, |
cff8d58a L |
9471 | { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32, |
9472 | BFD_RELOC_X86_64_DTPOFF32 }, | |
40fb9820 | 9473 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
9474 | { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE, |
9475 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 9476 | OPERAND_TYPE_NONE }, |
cff8d58a L |
9477 | { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE, |
9478 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 9479 | OPERAND_TYPE_NONE }, |
cff8d58a L |
9480 | { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32, |
9481 | BFD_RELOC_X86_64_GOT32 }, | |
40fb9820 | 9482 | OPERAND_TYPE_IMM32_32S_64_DISP32 }, |
cff8d58a L |
9483 | { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC, |
9484 | BFD_RELOC_X86_64_GOTPC32_TLSDESC }, | |
40fb9820 | 9485 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
9486 | { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL, |
9487 | BFD_RELOC_X86_64_TLSDESC_CALL }, | |
40fb9820 | 9488 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
f3c180ae AM |
9489 | }; |
9490 | char *cp; | |
9491 | unsigned int j; | |
9492 | ||
d382c579 | 9493 | #if defined (OBJ_MAYBE_ELF) |
718ddfc0 JB |
9494 | if (!IS_ELF) |
9495 | return NULL; | |
d382c579 | 9496 | #endif |
718ddfc0 | 9497 | |
f3c180ae | 9498 | for (cp = input_line_pointer; *cp != '@'; cp++) |
67c11a9b | 9499 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') |
f3c180ae AM |
9500 | return NULL; |
9501 | ||
47465058 | 9502 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) |
f3c180ae | 9503 | { |
cff8d58a | 9504 | int len = gotrel[j].len; |
28f81592 | 9505 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae | 9506 | { |
4fa24527 | 9507 | if (gotrel[j].rel[object_64bit] != 0) |
f3c180ae | 9508 | { |
28f81592 AM |
9509 | int first, second; |
9510 | char *tmpbuf, *past_reloc; | |
f3c180ae | 9511 | |
91d6fa6a | 9512 | *rel = gotrel[j].rel[object_64bit]; |
f3c180ae | 9513 | |
3956db08 JB |
9514 | if (types) |
9515 | { | |
9516 | if (flag_code != CODE_64BIT) | |
40fb9820 L |
9517 | { |
9518 | types->bitfield.imm32 = 1; | |
9519 | types->bitfield.disp32 = 1; | |
9520 | } | |
3956db08 JB |
9521 | else |
9522 | *types = gotrel[j].types64; | |
9523 | } | |
9524 | ||
8fd4256d | 9525 | if (j != 0 && GOT_symbol == NULL) |
f3c180ae AM |
9526 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); |
9527 | ||
28f81592 | 9528 | /* The length of the first part of our input line. */ |
f3c180ae | 9529 | first = cp - input_line_pointer; |
28f81592 AM |
9530 | |
9531 | /* The second part goes from after the reloc token until | |
67c11a9b | 9532 | (and including) an end_of_line char or comma. */ |
28f81592 | 9533 | past_reloc = cp + 1 + len; |
67c11a9b AM |
9534 | cp = past_reloc; |
9535 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
9536 | ++cp; | |
9537 | second = cp + 1 - past_reloc; | |
28f81592 AM |
9538 | |
9539 | /* Allocate and copy string. The trailing NUL shouldn't | |
9540 | be necessary, but be safe. */ | |
add39d23 | 9541 | tmpbuf = XNEWVEC (char, first + second + 2); |
f3c180ae | 9542 | memcpy (tmpbuf, input_line_pointer, first); |
0787a12d AM |
9543 | if (second != 0 && *past_reloc != ' ') |
9544 | /* Replace the relocation token with ' ', so that | |
9545 | errors like foo@GOTOFF1 will be detected. */ | |
9546 | tmpbuf[first++] = ' '; | |
af89796a L |
9547 | else |
9548 | /* Increment length by 1 if the relocation token is | |
9549 | removed. */ | |
9550 | len++; | |
9551 | if (adjust) | |
9552 | *adjust = len; | |
0787a12d AM |
9553 | memcpy (tmpbuf + first, past_reloc, second); |
9554 | tmpbuf[first + second] = '\0'; | |
f3c180ae AM |
9555 | return tmpbuf; |
9556 | } | |
9557 | ||
4fa24527 JB |
9558 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
9559 | gotrel[j].str, 1 << (5 + object_64bit)); | |
f3c180ae AM |
9560 | return NULL; |
9561 | } | |
9562 | } | |
9563 | ||
9564 | /* Might be a symbol version string. Don't as_bad here. */ | |
9565 | return NULL; | |
9566 | } | |
4e4f7c87 | 9567 | #endif |
f3c180ae | 9568 | |
a988325c NC |
9569 | #ifdef TE_PE |
9570 | #ifdef lex_got | |
9571 | #undef lex_got | |
9572 | #endif | |
9573 | /* Parse operands of the form | |
9574 | <symbol>@SECREL32+<nnn> | |
9575 | ||
9576 | If we find one, set up the correct relocation in RELOC and copy the | |
9577 | input string, minus the `@SECREL32' into a malloc'd buffer for | |
9578 | parsing by the calling routine. Return this buffer, and if ADJUST | |
9579 | is non-null set it to the length of the string we removed from the | |
34bca508 L |
9580 | input line. Otherwise return NULL. |
9581 | ||
a988325c NC |
9582 | This function is copied from the ELF version above adjusted for PE targets. */ |
9583 | ||
9584 | static char * | |
9585 | lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED, | |
9586 | int *adjust ATTRIBUTE_UNUSED, | |
d258b828 | 9587 | i386_operand_type *types) |
a988325c NC |
9588 | { |
9589 | static const struct | |
9590 | { | |
9591 | const char *str; | |
9592 | int len; | |
9593 | const enum bfd_reloc_code_real rel[2]; | |
9594 | const i386_operand_type types64; | |
9595 | } | |
9596 | gotrel[] = | |
9597 | { | |
9598 | { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL, | |
9599 | BFD_RELOC_32_SECREL }, | |
9600 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, | |
9601 | }; | |
9602 | ||
9603 | char *cp; | |
9604 | unsigned j; | |
9605 | ||
9606 | for (cp = input_line_pointer; *cp != '@'; cp++) | |
9607 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') | |
9608 | return NULL; | |
9609 | ||
9610 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) | |
9611 | { | |
9612 | int len = gotrel[j].len; | |
9613 | ||
9614 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) | |
9615 | { | |
9616 | if (gotrel[j].rel[object_64bit] != 0) | |
9617 | { | |
9618 | int first, second; | |
9619 | char *tmpbuf, *past_reloc; | |
9620 | ||
9621 | *rel = gotrel[j].rel[object_64bit]; | |
9622 | if (adjust) | |
9623 | *adjust = len; | |
9624 | ||
9625 | if (types) | |
9626 | { | |
9627 | if (flag_code != CODE_64BIT) | |
9628 | { | |
9629 | types->bitfield.imm32 = 1; | |
9630 | types->bitfield.disp32 = 1; | |
9631 | } | |
9632 | else | |
9633 | *types = gotrel[j].types64; | |
9634 | } | |
9635 | ||
9636 | /* The length of the first part of our input line. */ | |
9637 | first = cp - input_line_pointer; | |
9638 | ||
9639 | /* The second part goes from after the reloc token until | |
9640 | (and including) an end_of_line char or comma. */ | |
9641 | past_reloc = cp + 1 + len; | |
9642 | cp = past_reloc; | |
9643 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
9644 | ++cp; | |
9645 | second = cp + 1 - past_reloc; | |
9646 | ||
9647 | /* Allocate and copy string. The trailing NUL shouldn't | |
9648 | be necessary, but be safe. */ | |
add39d23 | 9649 | tmpbuf = XNEWVEC (char, first + second + 2); |
a988325c NC |
9650 | memcpy (tmpbuf, input_line_pointer, first); |
9651 | if (second != 0 && *past_reloc != ' ') | |
9652 | /* Replace the relocation token with ' ', so that | |
9653 | errors like foo@SECLREL321 will be detected. */ | |
9654 | tmpbuf[first++] = ' '; | |
9655 | memcpy (tmpbuf + first, past_reloc, second); | |
9656 | tmpbuf[first + second] = '\0'; | |
9657 | return tmpbuf; | |
9658 | } | |
9659 | ||
9660 | as_bad (_("@%s reloc is not supported with %d-bit output format"), | |
9661 | gotrel[j].str, 1 << (5 + object_64bit)); | |
9662 | return NULL; | |
9663 | } | |
9664 | } | |
9665 | ||
9666 | /* Might be a symbol version string. Don't as_bad here. */ | |
9667 | return NULL; | |
9668 | } | |
9669 | ||
9670 | #endif /* TE_PE */ | |
9671 | ||
62ebcb5c | 9672 | bfd_reloc_code_real_type |
e3bb37b5 | 9673 | x86_cons (expressionS *exp, int size) |
f3c180ae | 9674 | { |
62ebcb5c AM |
9675 | bfd_reloc_code_real_type got_reloc = NO_RELOC; |
9676 | ||
ee86248c JB |
9677 | intel_syntax = -intel_syntax; |
9678 | ||
3c7b9c2c | 9679 | exp->X_md = 0; |
4fa24527 | 9680 | if (size == 4 || (object_64bit && size == 8)) |
f3c180ae AM |
9681 | { |
9682 | /* Handle @GOTOFF and the like in an expression. */ | |
9683 | char *save; | |
9684 | char *gotfree_input_line; | |
4a57f2cf | 9685 | int adjust = 0; |
f3c180ae AM |
9686 | |
9687 | save = input_line_pointer; | |
d258b828 | 9688 | gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); |
f3c180ae AM |
9689 | if (gotfree_input_line) |
9690 | input_line_pointer = gotfree_input_line; | |
9691 | ||
9692 | expression (exp); | |
9693 | ||
9694 | if (gotfree_input_line) | |
9695 | { | |
9696 | /* expression () has merrily parsed up to the end of line, | |
9697 | or a comma - in the wrong buffer. Transfer how far | |
9698 | input_line_pointer has moved to the right buffer. */ | |
9699 | input_line_pointer = (save | |
9700 | + (input_line_pointer - gotfree_input_line) | |
9701 | + adjust); | |
9702 | free (gotfree_input_line); | |
3992d3b7 AM |
9703 | if (exp->X_op == O_constant |
9704 | || exp->X_op == O_absent | |
9705 | || exp->X_op == O_illegal | |
0398aac5 | 9706 | || exp->X_op == O_register |
3992d3b7 AM |
9707 | || exp->X_op == O_big) |
9708 | { | |
9709 | char c = *input_line_pointer; | |
9710 | *input_line_pointer = 0; | |
9711 | as_bad (_("missing or invalid expression `%s'"), save); | |
9712 | *input_line_pointer = c; | |
9713 | } | |
b9519cfe L |
9714 | else if ((got_reloc == BFD_RELOC_386_PLT32 |
9715 | || got_reloc == BFD_RELOC_X86_64_PLT32) | |
9716 | && exp->X_op != O_symbol) | |
9717 | { | |
9718 | char c = *input_line_pointer; | |
9719 | *input_line_pointer = 0; | |
9720 | as_bad (_("invalid PLT expression `%s'"), save); | |
9721 | *input_line_pointer = c; | |
9722 | } | |
f3c180ae AM |
9723 | } |
9724 | } | |
9725 | else | |
9726 | expression (exp); | |
ee86248c JB |
9727 | |
9728 | intel_syntax = -intel_syntax; | |
9729 | ||
9730 | if (intel_syntax) | |
9731 | i386_intel_simplify (exp); | |
62ebcb5c AM |
9732 | |
9733 | return got_reloc; | |
f3c180ae | 9734 | } |
f3c180ae | 9735 | |
9f32dd5b L |
9736 | static void |
9737 | signed_cons (int size) | |
6482c264 | 9738 | { |
d182319b JB |
9739 | if (flag_code == CODE_64BIT) |
9740 | cons_sign = 1; | |
9741 | cons (size); | |
9742 | cons_sign = -1; | |
6482c264 NC |
9743 | } |
9744 | ||
d182319b | 9745 | #ifdef TE_PE |
6482c264 | 9746 | static void |
7016a5d5 | 9747 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
6482c264 NC |
9748 | { |
9749 | expressionS exp; | |
9750 | ||
9751 | do | |
9752 | { | |
9753 | expression (&exp); | |
9754 | if (exp.X_op == O_symbol) | |
9755 | exp.X_op = O_secrel; | |
9756 | ||
9757 | emit_expr (&exp, 4); | |
9758 | } | |
9759 | while (*input_line_pointer++ == ','); | |
9760 | ||
9761 | input_line_pointer--; | |
9762 | demand_empty_rest_of_line (); | |
9763 | } | |
6482c264 NC |
9764 | #endif |
9765 | ||
43234a1e L |
9766 | /* Handle Vector operations. */ |
9767 | ||
9768 | static char * | |
9769 | check_VecOperations (char *op_string, char *op_end) | |
9770 | { | |
9771 | const reg_entry *mask; | |
9772 | const char *saved; | |
9773 | char *end_op; | |
9774 | ||
9775 | while (*op_string | |
9776 | && (op_end == NULL || op_string < op_end)) | |
9777 | { | |
9778 | saved = op_string; | |
9779 | if (*op_string == '{') | |
9780 | { | |
9781 | op_string++; | |
9782 | ||
9783 | /* Check broadcasts. */ | |
9784 | if (strncmp (op_string, "1to", 3) == 0) | |
9785 | { | |
9786 | int bcst_type; | |
9787 | ||
9788 | if (i.broadcast) | |
9789 | goto duplicated_vec_op; | |
9790 | ||
9791 | op_string += 3; | |
9792 | if (*op_string == '8') | |
8e6e0792 | 9793 | bcst_type = 8; |
b28d1bda | 9794 | else if (*op_string == '4') |
8e6e0792 | 9795 | bcst_type = 4; |
b28d1bda | 9796 | else if (*op_string == '2') |
8e6e0792 | 9797 | bcst_type = 2; |
43234a1e L |
9798 | else if (*op_string == '1' |
9799 | && *(op_string+1) == '6') | |
9800 | { | |
8e6e0792 | 9801 | bcst_type = 16; |
43234a1e L |
9802 | op_string++; |
9803 | } | |
9804 | else | |
9805 | { | |
9806 | as_bad (_("Unsupported broadcast: `%s'"), saved); | |
9807 | return NULL; | |
9808 | } | |
9809 | op_string++; | |
9810 | ||
9811 | broadcast_op.type = bcst_type; | |
9812 | broadcast_op.operand = this_operand; | |
1f75763a | 9813 | broadcast_op.bytes = 0; |
43234a1e L |
9814 | i.broadcast = &broadcast_op; |
9815 | } | |
9816 | /* Check masking operation. */ | |
9817 | else if ((mask = parse_register (op_string, &end_op)) != NULL) | |
9818 | { | |
9819 | /* k0 can't be used for write mask. */ | |
f74a6307 | 9820 | if (mask->reg_type.bitfield.class != RegMask || !mask->reg_num) |
43234a1e | 9821 | { |
6d2cd6b2 JB |
9822 | as_bad (_("`%s%s' can't be used for write mask"), |
9823 | register_prefix, mask->reg_name); | |
43234a1e L |
9824 | return NULL; |
9825 | } | |
9826 | ||
9827 | if (!i.mask) | |
9828 | { | |
9829 | mask_op.mask = mask; | |
9830 | mask_op.zeroing = 0; | |
9831 | mask_op.operand = this_operand; | |
9832 | i.mask = &mask_op; | |
9833 | } | |
9834 | else | |
9835 | { | |
9836 | if (i.mask->mask) | |
9837 | goto duplicated_vec_op; | |
9838 | ||
9839 | i.mask->mask = mask; | |
9840 | ||
9841 | /* Only "{z}" is allowed here. No need to check | |
9842 | zeroing mask explicitly. */ | |
9843 | if (i.mask->operand != this_operand) | |
9844 | { | |
9845 | as_bad (_("invalid write mask `%s'"), saved); | |
9846 | return NULL; | |
9847 | } | |
9848 | } | |
9849 | ||
9850 | op_string = end_op; | |
9851 | } | |
9852 | /* Check zeroing-flag for masking operation. */ | |
9853 | else if (*op_string == 'z') | |
9854 | { | |
9855 | if (!i.mask) | |
9856 | { | |
9857 | mask_op.mask = NULL; | |
9858 | mask_op.zeroing = 1; | |
9859 | mask_op.operand = this_operand; | |
9860 | i.mask = &mask_op; | |
9861 | } | |
9862 | else | |
9863 | { | |
9864 | if (i.mask->zeroing) | |
9865 | { | |
9866 | duplicated_vec_op: | |
9867 | as_bad (_("duplicated `%s'"), saved); | |
9868 | return NULL; | |
9869 | } | |
9870 | ||
9871 | i.mask->zeroing = 1; | |
9872 | ||
9873 | /* Only "{%k}" is allowed here. No need to check mask | |
9874 | register explicitly. */ | |
9875 | if (i.mask->operand != this_operand) | |
9876 | { | |
9877 | as_bad (_("invalid zeroing-masking `%s'"), | |
9878 | saved); | |
9879 | return NULL; | |
9880 | } | |
9881 | } | |
9882 | ||
9883 | op_string++; | |
9884 | } | |
9885 | else | |
9886 | goto unknown_vec_op; | |
9887 | ||
9888 | if (*op_string != '}') | |
9889 | { | |
9890 | as_bad (_("missing `}' in `%s'"), saved); | |
9891 | return NULL; | |
9892 | } | |
9893 | op_string++; | |
0ba3a731 L |
9894 | |
9895 | /* Strip whitespace since the addition of pseudo prefixes | |
9896 | changed how the scrubber treats '{'. */ | |
9897 | if (is_space_char (*op_string)) | |
9898 | ++op_string; | |
9899 | ||
43234a1e L |
9900 | continue; |
9901 | } | |
9902 | unknown_vec_op: | |
9903 | /* We don't know this one. */ | |
9904 | as_bad (_("unknown vector operation: `%s'"), saved); | |
9905 | return NULL; | |
9906 | } | |
9907 | ||
6d2cd6b2 JB |
9908 | if (i.mask && i.mask->zeroing && !i.mask->mask) |
9909 | { | |
9910 | as_bad (_("zeroing-masking only allowed with write mask")); | |
9911 | return NULL; | |
9912 | } | |
9913 | ||
43234a1e L |
9914 | return op_string; |
9915 | } | |
9916 | ||
252b5132 | 9917 | static int |
70e41ade | 9918 | i386_immediate (char *imm_start) |
252b5132 RH |
9919 | { |
9920 | char *save_input_line_pointer; | |
f3c180ae | 9921 | char *gotfree_input_line; |
252b5132 | 9922 | segT exp_seg = 0; |
47926f60 | 9923 | expressionS *exp; |
40fb9820 L |
9924 | i386_operand_type types; |
9925 | ||
0dfbf9d7 | 9926 | operand_type_set (&types, ~0); |
252b5132 RH |
9927 | |
9928 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
9929 | { | |
31b2323c L |
9930 | as_bad (_("at most %d immediate operands are allowed"), |
9931 | MAX_IMMEDIATE_OPERANDS); | |
252b5132 RH |
9932 | return 0; |
9933 | } | |
9934 | ||
9935 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 9936 | i.op[this_operand].imms = exp; |
252b5132 RH |
9937 | |
9938 | if (is_space_char (*imm_start)) | |
9939 | ++imm_start; | |
9940 | ||
9941 | save_input_line_pointer = input_line_pointer; | |
9942 | input_line_pointer = imm_start; | |
9943 | ||
d258b828 | 9944 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
9945 | if (gotfree_input_line) |
9946 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
9947 | |
9948 | exp_seg = expression (exp); | |
9949 | ||
83183c0c | 9950 | SKIP_WHITESPACE (); |
43234a1e L |
9951 | |
9952 | /* Handle vector operations. */ | |
9953 | if (*input_line_pointer == '{') | |
9954 | { | |
9955 | input_line_pointer = check_VecOperations (input_line_pointer, | |
9956 | NULL); | |
9957 | if (input_line_pointer == NULL) | |
9958 | return 0; | |
9959 | } | |
9960 | ||
252b5132 | 9961 | if (*input_line_pointer) |
f3c180ae | 9962 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
9963 | |
9964 | input_line_pointer = save_input_line_pointer; | |
f3c180ae | 9965 | if (gotfree_input_line) |
ee86248c JB |
9966 | { |
9967 | free (gotfree_input_line); | |
9968 | ||
9969 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
9970 | exp->X_op = O_illegal; | |
9971 | } | |
9972 | ||
9973 | return i386_finalize_immediate (exp_seg, exp, types, imm_start); | |
9974 | } | |
252b5132 | 9975 | |
ee86248c JB |
9976 | static int |
9977 | i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
9978 | i386_operand_type types, const char *imm_start) | |
9979 | { | |
9980 | if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big) | |
252b5132 | 9981 | { |
313c53d1 L |
9982 | if (imm_start) |
9983 | as_bad (_("missing or invalid immediate expression `%s'"), | |
9984 | imm_start); | |
3992d3b7 | 9985 | return 0; |
252b5132 | 9986 | } |
3e73aa7c | 9987 | else if (exp->X_op == O_constant) |
252b5132 | 9988 | { |
47926f60 | 9989 | /* Size it properly later. */ |
40fb9820 | 9990 | i.types[this_operand].bitfield.imm64 = 1; |
13f864ae L |
9991 | /* If not 64bit, sign extend val. */ |
9992 | if (flag_code != CODE_64BIT | |
4eed87de AM |
9993 | && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) |
9994 | exp->X_add_number | |
9995 | = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
252b5132 | 9996 | } |
4c63da97 | 9997 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
f86103b7 | 9998 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 9999 | && exp_seg != absolute_section |
47926f60 | 10000 | && exp_seg != text_section |
24eab124 AM |
10001 | && exp_seg != data_section |
10002 | && exp_seg != bss_section | |
10003 | && exp_seg != undefined_section | |
f86103b7 | 10004 | && !bfd_is_com_section (exp_seg)) |
252b5132 | 10005 | { |
d0b47220 | 10006 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
252b5132 RH |
10007 | return 0; |
10008 | } | |
10009 | #endif | |
a841bdf5 | 10010 | else if (!intel_syntax && exp_seg == reg_section) |
bb8f5920 | 10011 | { |
313c53d1 L |
10012 | if (imm_start) |
10013 | as_bad (_("illegal immediate register operand %s"), imm_start); | |
bb8f5920 L |
10014 | return 0; |
10015 | } | |
252b5132 RH |
10016 | else |
10017 | { | |
10018 | /* This is an address. The size of the address will be | |
24eab124 | 10019 | determined later, depending on destination register, |
3e73aa7c | 10020 | suffix, or the default for the section. */ |
40fb9820 L |
10021 | i.types[this_operand].bitfield.imm8 = 1; |
10022 | i.types[this_operand].bitfield.imm16 = 1; | |
10023 | i.types[this_operand].bitfield.imm32 = 1; | |
10024 | i.types[this_operand].bitfield.imm32s = 1; | |
10025 | i.types[this_operand].bitfield.imm64 = 1; | |
c6fb90c8 L |
10026 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
10027 | types); | |
252b5132 RH |
10028 | } |
10029 | ||
10030 | return 1; | |
10031 | } | |
10032 | ||
551c1ca1 | 10033 | static char * |
e3bb37b5 | 10034 | i386_scale (char *scale) |
252b5132 | 10035 | { |
551c1ca1 AM |
10036 | offsetT val; |
10037 | char *save = input_line_pointer; | |
252b5132 | 10038 | |
551c1ca1 AM |
10039 | input_line_pointer = scale; |
10040 | val = get_absolute_expression (); | |
10041 | ||
10042 | switch (val) | |
252b5132 | 10043 | { |
551c1ca1 | 10044 | case 1: |
252b5132 RH |
10045 | i.log2_scale_factor = 0; |
10046 | break; | |
551c1ca1 | 10047 | case 2: |
252b5132 RH |
10048 | i.log2_scale_factor = 1; |
10049 | break; | |
551c1ca1 | 10050 | case 4: |
252b5132 RH |
10051 | i.log2_scale_factor = 2; |
10052 | break; | |
551c1ca1 | 10053 | case 8: |
252b5132 RH |
10054 | i.log2_scale_factor = 3; |
10055 | break; | |
10056 | default: | |
a724f0f4 JB |
10057 | { |
10058 | char sep = *input_line_pointer; | |
10059 | ||
10060 | *input_line_pointer = '\0'; | |
10061 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
10062 | scale); | |
10063 | *input_line_pointer = sep; | |
10064 | input_line_pointer = save; | |
10065 | return NULL; | |
10066 | } | |
252b5132 | 10067 | } |
29b0f896 | 10068 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
252b5132 RH |
10069 | { |
10070 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 10071 | 1 << i.log2_scale_factor); |
252b5132 | 10072 | i.log2_scale_factor = 0; |
252b5132 | 10073 | } |
551c1ca1 AM |
10074 | scale = input_line_pointer; |
10075 | input_line_pointer = save; | |
10076 | return scale; | |
252b5132 RH |
10077 | } |
10078 | ||
252b5132 | 10079 | static int |
e3bb37b5 | 10080 | i386_displacement (char *disp_start, char *disp_end) |
252b5132 | 10081 | { |
29b0f896 | 10082 | expressionS *exp; |
252b5132 RH |
10083 | segT exp_seg = 0; |
10084 | char *save_input_line_pointer; | |
f3c180ae | 10085 | char *gotfree_input_line; |
40fb9820 L |
10086 | int override; |
10087 | i386_operand_type bigdisp, types = anydisp; | |
3992d3b7 | 10088 | int ret; |
252b5132 | 10089 | |
31b2323c L |
10090 | if (i.disp_operands == MAX_MEMORY_OPERANDS) |
10091 | { | |
10092 | as_bad (_("at most %d displacement operands are allowed"), | |
10093 | MAX_MEMORY_OPERANDS); | |
10094 | return 0; | |
10095 | } | |
10096 | ||
0dfbf9d7 | 10097 | operand_type_set (&bigdisp, 0); |
6f2f06be | 10098 | if (i.jumpabsolute |
48bcea9f | 10099 | || i.types[this_operand].bitfield.baseindex |
0cfa3eb3 JB |
10100 | || (current_templates->start->opcode_modifier.jump != JUMP |
10101 | && current_templates->start->opcode_modifier.jump != JUMP_DWORD)) | |
e05278af | 10102 | { |
48bcea9f | 10103 | i386_addressing_mode (); |
e05278af | 10104 | override = (i.prefix[ADDR_PREFIX] != 0); |
40fb9820 L |
10105 | if (flag_code == CODE_64BIT) |
10106 | { | |
10107 | if (!override) | |
10108 | { | |
10109 | bigdisp.bitfield.disp32s = 1; | |
10110 | bigdisp.bitfield.disp64 = 1; | |
10111 | } | |
48bcea9f JB |
10112 | else |
10113 | bigdisp.bitfield.disp32 = 1; | |
40fb9820 L |
10114 | } |
10115 | else if ((flag_code == CODE_16BIT) ^ override) | |
40fb9820 | 10116 | bigdisp.bitfield.disp16 = 1; |
48bcea9f JB |
10117 | else |
10118 | bigdisp.bitfield.disp32 = 1; | |
e05278af JB |
10119 | } |
10120 | else | |
10121 | { | |
376cd056 JB |
10122 | /* For PC-relative branches, the width of the displacement may be |
10123 | dependent upon data size, but is never dependent upon address size. | |
10124 | Also make sure to not unintentionally match against a non-PC-relative | |
10125 | branch template. */ | |
10126 | static templates aux_templates; | |
10127 | const insn_template *t = current_templates->start; | |
10128 | bfd_boolean has_intel64 = FALSE; | |
10129 | ||
10130 | aux_templates.start = t; | |
10131 | while (++t < current_templates->end) | |
10132 | { | |
10133 | if (t->opcode_modifier.jump | |
10134 | != current_templates->start->opcode_modifier.jump) | |
10135 | break; | |
4b5aaf5f | 10136 | if ((t->opcode_modifier.isa64 >= INTEL64)) |
376cd056 JB |
10137 | has_intel64 = TRUE; |
10138 | } | |
10139 | if (t < current_templates->end) | |
10140 | { | |
10141 | aux_templates.end = t; | |
10142 | current_templates = &aux_templates; | |
10143 | } | |
10144 | ||
e05278af | 10145 | override = (i.prefix[DATA_PREFIX] != 0); |
40fb9820 L |
10146 | if (flag_code == CODE_64BIT) |
10147 | { | |
376cd056 JB |
10148 | if ((override || i.suffix == WORD_MNEM_SUFFIX) |
10149 | && (!intel64 || !has_intel64)) | |
40fb9820 L |
10150 | bigdisp.bitfield.disp16 = 1; |
10151 | else | |
48bcea9f | 10152 | bigdisp.bitfield.disp32s = 1; |
40fb9820 L |
10153 | } |
10154 | else | |
e05278af JB |
10155 | { |
10156 | if (!override) | |
10157 | override = (i.suffix == (flag_code != CODE_16BIT | |
10158 | ? WORD_MNEM_SUFFIX | |
10159 | : LONG_MNEM_SUFFIX)); | |
40fb9820 L |
10160 | bigdisp.bitfield.disp32 = 1; |
10161 | if ((flag_code == CODE_16BIT) ^ override) | |
10162 | { | |
10163 | bigdisp.bitfield.disp32 = 0; | |
10164 | bigdisp.bitfield.disp16 = 1; | |
10165 | } | |
e05278af | 10166 | } |
e05278af | 10167 | } |
c6fb90c8 L |
10168 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
10169 | bigdisp); | |
252b5132 RH |
10170 | |
10171 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 10172 | i.op[this_operand].disps = exp; |
252b5132 RH |
10173 | i.disp_operands++; |
10174 | save_input_line_pointer = input_line_pointer; | |
10175 | input_line_pointer = disp_start; | |
10176 | END_STRING_AND_SAVE (disp_end); | |
10177 | ||
10178 | #ifndef GCC_ASM_O_HACK | |
10179 | #define GCC_ASM_O_HACK 0 | |
10180 | #endif | |
10181 | #if GCC_ASM_O_HACK | |
10182 | END_STRING_AND_SAVE (disp_end + 1); | |
40fb9820 | 10183 | if (i.types[this_operand].bitfield.baseIndex |
24eab124 | 10184 | && displacement_string_end[-1] == '+') |
252b5132 RH |
10185 | { |
10186 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
10187 | constraint within gcc asm statements. |
10188 | For instance: | |
10189 | ||
10190 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
10191 | __asm__ __volatile__ ( \ | |
10192 | "movw %w2,%0\n\t" \ | |
10193 | "movw %w1,2+%0\n\t" \ | |
10194 | "rorl $16,%1\n\t" \ | |
10195 | "movb %b1,4+%0\n\t" \ | |
10196 | "movb %4,5+%0\n\t" \ | |
10197 | "movb $0,6+%0\n\t" \ | |
10198 | "movb %h1,7+%0\n\t" \ | |
10199 | "rorl $16,%1" \ | |
10200 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
10201 | ||
10202 | This works great except that the output assembler ends | |
10203 | up looking a bit weird if it turns out that there is | |
10204 | no offset. You end up producing code that looks like: | |
10205 | ||
10206 | #APP | |
10207 | movw $235,(%eax) | |
10208 | movw %dx,2+(%eax) | |
10209 | rorl $16,%edx | |
10210 | movb %dl,4+(%eax) | |
10211 | movb $137,5+(%eax) | |
10212 | movb $0,6+(%eax) | |
10213 | movb %dh,7+(%eax) | |
10214 | rorl $16,%edx | |
10215 | #NO_APP | |
10216 | ||
47926f60 | 10217 | So here we provide the missing zero. */ |
24eab124 AM |
10218 | |
10219 | *displacement_string_end = '0'; | |
252b5132 RH |
10220 | } |
10221 | #endif | |
d258b828 | 10222 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
10223 | if (gotfree_input_line) |
10224 | input_line_pointer = gotfree_input_line; | |
252b5132 | 10225 | |
24eab124 | 10226 | exp_seg = expression (exp); |
252b5132 | 10227 | |
636c26b0 AM |
10228 | SKIP_WHITESPACE (); |
10229 | if (*input_line_pointer) | |
10230 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
10231 | #if GCC_ASM_O_HACK | |
10232 | RESTORE_END_STRING (disp_end + 1); | |
10233 | #endif | |
636c26b0 | 10234 | input_line_pointer = save_input_line_pointer; |
636c26b0 | 10235 | if (gotfree_input_line) |
ee86248c JB |
10236 | { |
10237 | free (gotfree_input_line); | |
10238 | ||
10239 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
10240 | exp->X_op = O_illegal; | |
10241 | } | |
10242 | ||
10243 | ret = i386_finalize_displacement (exp_seg, exp, types, disp_start); | |
10244 | ||
10245 | RESTORE_END_STRING (disp_end); | |
10246 | ||
10247 | return ret; | |
10248 | } | |
10249 | ||
10250 | static int | |
10251 | i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
10252 | i386_operand_type types, const char *disp_start) | |
10253 | { | |
10254 | i386_operand_type bigdisp; | |
10255 | int ret = 1; | |
636c26b0 | 10256 | |
24eab124 AM |
10257 | /* We do this to make sure that the section symbol is in |
10258 | the symbol table. We will ultimately change the relocation | |
47926f60 | 10259 | to be relative to the beginning of the section. */ |
1ae12ab7 | 10260 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
d6ab8113 JB |
10261 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
10262 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) | |
24eab124 | 10263 | { |
636c26b0 | 10264 | if (exp->X_op != O_symbol) |
3992d3b7 | 10265 | goto inv_disp; |
636c26b0 | 10266 | |
e5cb08ac | 10267 | if (S_IS_LOCAL (exp->X_add_symbol) |
c64efb4b L |
10268 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section |
10269 | && S_GET_SEGMENT (exp->X_add_symbol) != expr_section) | |
24eab124 | 10270 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); |
24eab124 AM |
10271 | exp->X_op = O_subtract; |
10272 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 | 10273 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
29b0f896 | 10274 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
d6ab8113 JB |
10275 | else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
10276 | i.reloc[this_operand] = BFD_RELOC_64; | |
23df1078 | 10277 | else |
29b0f896 | 10278 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 10279 | } |
252b5132 | 10280 | |
3992d3b7 AM |
10281 | else if (exp->X_op == O_absent |
10282 | || exp->X_op == O_illegal | |
ee86248c | 10283 | || exp->X_op == O_big) |
2daf4fd8 | 10284 | { |
3992d3b7 AM |
10285 | inv_disp: |
10286 | as_bad (_("missing or invalid displacement expression `%s'"), | |
2daf4fd8 | 10287 | disp_start); |
3992d3b7 | 10288 | ret = 0; |
2daf4fd8 AM |
10289 | } |
10290 | ||
0e1147d9 L |
10291 | else if (flag_code == CODE_64BIT |
10292 | && !i.prefix[ADDR_PREFIX] | |
10293 | && exp->X_op == O_constant) | |
10294 | { | |
10295 | /* Since displacement is signed extended to 64bit, don't allow | |
10296 | disp32 and turn off disp32s if they are out of range. */ | |
10297 | i.types[this_operand].bitfield.disp32 = 0; | |
10298 | if (!fits_in_signed_long (exp->X_add_number)) | |
10299 | { | |
10300 | i.types[this_operand].bitfield.disp32s = 0; | |
10301 | if (i.types[this_operand].bitfield.baseindex) | |
10302 | { | |
10303 | as_bad (_("0x%lx out range of signed 32bit displacement"), | |
10304 | (long) exp->X_add_number); | |
10305 | ret = 0; | |
10306 | } | |
10307 | } | |
10308 | } | |
10309 | ||
4c63da97 | 10310 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
3992d3b7 AM |
10311 | else if (exp->X_op != O_constant |
10312 | && OUTPUT_FLAVOR == bfd_target_aout_flavour | |
10313 | && exp_seg != absolute_section | |
10314 | && exp_seg != text_section | |
10315 | && exp_seg != data_section | |
10316 | && exp_seg != bss_section | |
10317 | && exp_seg != undefined_section | |
10318 | && !bfd_is_com_section (exp_seg)) | |
24eab124 | 10319 | { |
d0b47220 | 10320 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
3992d3b7 | 10321 | ret = 0; |
24eab124 | 10322 | } |
252b5132 | 10323 | #endif |
3956db08 | 10324 | |
48bcea9f JB |
10325 | if (current_templates->start->opcode_modifier.jump == JUMP_BYTE |
10326 | /* Constants get taken care of by optimize_disp(). */ | |
10327 | && exp->X_op != O_constant) | |
10328 | i.types[this_operand].bitfield.disp8 = 1; | |
10329 | ||
40fb9820 L |
10330 | /* Check if this is a displacement only operand. */ |
10331 | bigdisp = i.types[this_operand]; | |
10332 | bigdisp.bitfield.disp8 = 0; | |
10333 | bigdisp.bitfield.disp16 = 0; | |
10334 | bigdisp.bitfield.disp32 = 0; | |
10335 | bigdisp.bitfield.disp32s = 0; | |
10336 | bigdisp.bitfield.disp64 = 0; | |
0dfbf9d7 | 10337 | if (operand_type_all_zero (&bigdisp)) |
c6fb90c8 L |
10338 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
10339 | types); | |
3956db08 | 10340 | |
3992d3b7 | 10341 | return ret; |
252b5132 RH |
10342 | } |
10343 | ||
2abc2bec JB |
10344 | /* Return the active addressing mode, taking address override and |
10345 | registers forming the address into consideration. Update the | |
10346 | address override prefix if necessary. */ | |
47926f60 | 10347 | |
2abc2bec JB |
10348 | static enum flag_code |
10349 | i386_addressing_mode (void) | |
252b5132 | 10350 | { |
be05d201 L |
10351 | enum flag_code addr_mode; |
10352 | ||
10353 | if (i.prefix[ADDR_PREFIX]) | |
10354 | addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT; | |
10355 | else | |
10356 | { | |
10357 | addr_mode = flag_code; | |
10358 | ||
24eab124 | 10359 | #if INFER_ADDR_PREFIX |
be05d201 L |
10360 | if (i.mem_operands == 0) |
10361 | { | |
10362 | /* Infer address prefix from the first memory operand. */ | |
10363 | const reg_entry *addr_reg = i.base_reg; | |
10364 | ||
10365 | if (addr_reg == NULL) | |
10366 | addr_reg = i.index_reg; | |
eecb386c | 10367 | |
be05d201 L |
10368 | if (addr_reg) |
10369 | { | |
e968fc9b | 10370 | if (addr_reg->reg_type.bitfield.dword) |
be05d201 L |
10371 | addr_mode = CODE_32BIT; |
10372 | else if (flag_code != CODE_64BIT | |
dc821c5f | 10373 | && addr_reg->reg_type.bitfield.word) |
be05d201 L |
10374 | addr_mode = CODE_16BIT; |
10375 | ||
10376 | if (addr_mode != flag_code) | |
10377 | { | |
10378 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
10379 | i.prefixes += 1; | |
10380 | /* Change the size of any displacement too. At most one | |
10381 | of Disp16 or Disp32 is set. | |
10382 | FIXME. There doesn't seem to be any real need for | |
10383 | separate Disp16 and Disp32 flags. The same goes for | |
10384 | Imm16 and Imm32. Removing them would probably clean | |
10385 | up the code quite a lot. */ | |
10386 | if (flag_code != CODE_64BIT | |
10387 | && (i.types[this_operand].bitfield.disp16 | |
10388 | || i.types[this_operand].bitfield.disp32)) | |
10389 | i.types[this_operand] | |
10390 | = operand_type_xor (i.types[this_operand], disp16_32); | |
10391 | } | |
10392 | } | |
10393 | } | |
24eab124 | 10394 | #endif |
be05d201 L |
10395 | } |
10396 | ||
2abc2bec JB |
10397 | return addr_mode; |
10398 | } | |
10399 | ||
10400 | /* Make sure the memory operand we've been dealt is valid. | |
10401 | Return 1 on success, 0 on a failure. */ | |
10402 | ||
10403 | static int | |
10404 | i386_index_check (const char *operand_string) | |
10405 | { | |
10406 | const char *kind = "base/index"; | |
10407 | enum flag_code addr_mode = i386_addressing_mode (); | |
10408 | ||
fc0763e6 | 10409 | if (current_templates->start->opcode_modifier.isstring |
c3949f43 | 10410 | && !current_templates->start->cpu_flags.bitfield.cpupadlock |
fc0763e6 JB |
10411 | && (current_templates->end[-1].opcode_modifier.isstring |
10412 | || i.mem_operands)) | |
10413 | { | |
10414 | /* Memory operands of string insns are special in that they only allow | |
10415 | a single register (rDI, rSI, or rBX) as their memory address. */ | |
be05d201 L |
10416 | const reg_entry *expected_reg; |
10417 | static const char *di_si[][2] = | |
10418 | { | |
10419 | { "esi", "edi" }, | |
10420 | { "si", "di" }, | |
10421 | { "rsi", "rdi" } | |
10422 | }; | |
10423 | static const char *bx[] = { "ebx", "bx", "rbx" }; | |
fc0763e6 JB |
10424 | |
10425 | kind = "string address"; | |
10426 | ||
8325cc63 | 10427 | if (current_templates->start->opcode_modifier.repprefixok) |
fc0763e6 | 10428 | { |
51c8edf6 JB |
10429 | int es_op = current_templates->end[-1].opcode_modifier.isstring |
10430 | - IS_STRING_ES_OP0; | |
10431 | int op = 0; | |
fc0763e6 | 10432 | |
51c8edf6 | 10433 | if (!current_templates->end[-1].operand_types[0].bitfield.baseindex |
fc0763e6 JB |
10434 | || ((!i.mem_operands != !intel_syntax) |
10435 | && current_templates->end[-1].operand_types[1] | |
10436 | .bitfield.baseindex)) | |
51c8edf6 JB |
10437 | op = 1; |
10438 | expected_reg = hash_find (reg_hash, di_si[addr_mode][op == es_op]); | |
fc0763e6 JB |
10439 | } |
10440 | else | |
be05d201 | 10441 | expected_reg = hash_find (reg_hash, bx[addr_mode]); |
fc0763e6 | 10442 | |
be05d201 L |
10443 | if (i.base_reg != expected_reg |
10444 | || i.index_reg | |
fc0763e6 | 10445 | || operand_type_check (i.types[this_operand], disp)) |
fc0763e6 | 10446 | { |
be05d201 L |
10447 | /* The second memory operand must have the same size as |
10448 | the first one. */ | |
10449 | if (i.mem_operands | |
10450 | && i.base_reg | |
10451 | && !((addr_mode == CODE_64BIT | |
dc821c5f | 10452 | && i.base_reg->reg_type.bitfield.qword) |
be05d201 | 10453 | || (addr_mode == CODE_32BIT |
dc821c5f JB |
10454 | ? i.base_reg->reg_type.bitfield.dword |
10455 | : i.base_reg->reg_type.bitfield.word))) | |
be05d201 L |
10456 | goto bad_address; |
10457 | ||
fc0763e6 JB |
10458 | as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"), |
10459 | operand_string, | |
10460 | intel_syntax ? '[' : '(', | |
10461 | register_prefix, | |
be05d201 | 10462 | expected_reg->reg_name, |
fc0763e6 | 10463 | intel_syntax ? ']' : ')'); |
be05d201 | 10464 | return 1; |
fc0763e6 | 10465 | } |
be05d201 L |
10466 | else |
10467 | return 1; | |
10468 | ||
dc1e8a47 | 10469 | bad_address: |
be05d201 L |
10470 | as_bad (_("`%s' is not a valid %s expression"), |
10471 | operand_string, kind); | |
10472 | return 0; | |
3e73aa7c JH |
10473 | } |
10474 | else | |
10475 | { | |
be05d201 L |
10476 | if (addr_mode != CODE_16BIT) |
10477 | { | |
10478 | /* 32-bit/64-bit checks. */ | |
10479 | if ((i.base_reg | |
e968fc9b JB |
10480 | && ((addr_mode == CODE_64BIT |
10481 | ? !i.base_reg->reg_type.bitfield.qword | |
10482 | : !i.base_reg->reg_type.bitfield.dword) | |
10483 | || (i.index_reg && i.base_reg->reg_num == RegIP) | |
10484 | || i.base_reg->reg_num == RegIZ)) | |
be05d201 | 10485 | || (i.index_reg |
1b54b8d7 JB |
10486 | && !i.index_reg->reg_type.bitfield.xmmword |
10487 | && !i.index_reg->reg_type.bitfield.ymmword | |
10488 | && !i.index_reg->reg_type.bitfield.zmmword | |
be05d201 | 10489 | && ((addr_mode == CODE_64BIT |
e968fc9b JB |
10490 | ? !i.index_reg->reg_type.bitfield.qword |
10491 | : !i.index_reg->reg_type.bitfield.dword) | |
be05d201 L |
10492 | || !i.index_reg->reg_type.bitfield.baseindex))) |
10493 | goto bad_address; | |
8178be5b JB |
10494 | |
10495 | /* bndmk, bndldx, and bndstx have special restrictions. */ | |
10496 | if (current_templates->start->base_opcode == 0xf30f1b | |
10497 | || (current_templates->start->base_opcode & ~1) == 0x0f1a) | |
10498 | { | |
10499 | /* They cannot use RIP-relative addressing. */ | |
e968fc9b | 10500 | if (i.base_reg && i.base_reg->reg_num == RegIP) |
8178be5b JB |
10501 | { |
10502 | as_bad (_("`%s' cannot be used here"), operand_string); | |
10503 | return 0; | |
10504 | } | |
10505 | ||
10506 | /* bndldx and bndstx ignore their scale factor. */ | |
10507 | if (current_templates->start->base_opcode != 0xf30f1b | |
10508 | && i.log2_scale_factor) | |
10509 | as_warn (_("register scaling is being ignored here")); | |
10510 | } | |
be05d201 L |
10511 | } |
10512 | else | |
3e73aa7c | 10513 | { |
be05d201 | 10514 | /* 16-bit checks. */ |
3e73aa7c | 10515 | if ((i.base_reg |
dc821c5f | 10516 | && (!i.base_reg->reg_type.bitfield.word |
40fb9820 | 10517 | || !i.base_reg->reg_type.bitfield.baseindex)) |
3e73aa7c | 10518 | || (i.index_reg |
dc821c5f | 10519 | && (!i.index_reg->reg_type.bitfield.word |
40fb9820 | 10520 | || !i.index_reg->reg_type.bitfield.baseindex |
29b0f896 AM |
10521 | || !(i.base_reg |
10522 | && i.base_reg->reg_num < 6 | |
10523 | && i.index_reg->reg_num >= 6 | |
10524 | && i.log2_scale_factor == 0)))) | |
be05d201 | 10525 | goto bad_address; |
3e73aa7c JH |
10526 | } |
10527 | } | |
be05d201 | 10528 | return 1; |
24eab124 | 10529 | } |
252b5132 | 10530 | |
43234a1e L |
10531 | /* Handle vector immediates. */ |
10532 | ||
10533 | static int | |
10534 | RC_SAE_immediate (const char *imm_start) | |
10535 | { | |
10536 | unsigned int match_found, j; | |
10537 | const char *pstr = imm_start; | |
10538 | expressionS *exp; | |
10539 | ||
10540 | if (*pstr != '{') | |
10541 | return 0; | |
10542 | ||
10543 | pstr++; | |
10544 | match_found = 0; | |
10545 | for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++) | |
10546 | { | |
10547 | if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len)) | |
10548 | { | |
10549 | if (!i.rounding) | |
10550 | { | |
10551 | rc_op.type = RC_NamesTable[j].type; | |
10552 | rc_op.operand = this_operand; | |
10553 | i.rounding = &rc_op; | |
10554 | } | |
10555 | else | |
10556 | { | |
10557 | as_bad (_("duplicated `%s'"), imm_start); | |
10558 | return 0; | |
10559 | } | |
10560 | pstr += RC_NamesTable[j].len; | |
10561 | match_found = 1; | |
10562 | break; | |
10563 | } | |
10564 | } | |
10565 | if (!match_found) | |
10566 | return 0; | |
10567 | ||
10568 | if (*pstr++ != '}') | |
10569 | { | |
10570 | as_bad (_("Missing '}': '%s'"), imm_start); | |
10571 | return 0; | |
10572 | } | |
10573 | /* RC/SAE immediate string should contain nothing more. */; | |
10574 | if (*pstr != 0) | |
10575 | { | |
10576 | as_bad (_("Junk after '}': '%s'"), imm_start); | |
10577 | return 0; | |
10578 | } | |
10579 | ||
10580 | exp = &im_expressions[i.imm_operands++]; | |
10581 | i.op[this_operand].imms = exp; | |
10582 | ||
10583 | exp->X_op = O_constant; | |
10584 | exp->X_add_number = 0; | |
10585 | exp->X_add_symbol = (symbolS *) 0; | |
10586 | exp->X_op_symbol = (symbolS *) 0; | |
10587 | ||
10588 | i.types[this_operand].bitfield.imm8 = 1; | |
10589 | return 1; | |
10590 | } | |
10591 | ||
8325cc63 JB |
10592 | /* Only string instructions can have a second memory operand, so |
10593 | reduce current_templates to just those if it contains any. */ | |
10594 | static int | |
10595 | maybe_adjust_templates (void) | |
10596 | { | |
10597 | const insn_template *t; | |
10598 | ||
10599 | gas_assert (i.mem_operands == 1); | |
10600 | ||
10601 | for (t = current_templates->start; t < current_templates->end; ++t) | |
10602 | if (t->opcode_modifier.isstring) | |
10603 | break; | |
10604 | ||
10605 | if (t < current_templates->end) | |
10606 | { | |
10607 | static templates aux_templates; | |
10608 | bfd_boolean recheck; | |
10609 | ||
10610 | aux_templates.start = t; | |
10611 | for (; t < current_templates->end; ++t) | |
10612 | if (!t->opcode_modifier.isstring) | |
10613 | break; | |
10614 | aux_templates.end = t; | |
10615 | ||
10616 | /* Determine whether to re-check the first memory operand. */ | |
10617 | recheck = (aux_templates.start != current_templates->start | |
10618 | || t != current_templates->end); | |
10619 | ||
10620 | current_templates = &aux_templates; | |
10621 | ||
10622 | if (recheck) | |
10623 | { | |
10624 | i.mem_operands = 0; | |
10625 | if (i.memop1_string != NULL | |
10626 | && i386_index_check (i.memop1_string) == 0) | |
10627 | return 0; | |
10628 | i.mem_operands = 1; | |
10629 | } | |
10630 | } | |
10631 | ||
10632 | return 1; | |
10633 | } | |
10634 | ||
fc0763e6 | 10635 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero |
47926f60 | 10636 | on error. */ |
252b5132 | 10637 | |
252b5132 | 10638 | static int |
a7619375 | 10639 | i386_att_operand (char *operand_string) |
252b5132 | 10640 | { |
af6bdddf AM |
10641 | const reg_entry *r; |
10642 | char *end_op; | |
24eab124 | 10643 | char *op_string = operand_string; |
252b5132 | 10644 | |
24eab124 | 10645 | if (is_space_char (*op_string)) |
252b5132 RH |
10646 | ++op_string; |
10647 | ||
24eab124 | 10648 | /* We check for an absolute prefix (differentiating, |
47926f60 | 10649 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
10650 | if (*op_string == ABSOLUTE_PREFIX) |
10651 | { | |
10652 | ++op_string; | |
10653 | if (is_space_char (*op_string)) | |
10654 | ++op_string; | |
6f2f06be | 10655 | i.jumpabsolute = TRUE; |
24eab124 | 10656 | } |
252b5132 | 10657 | |
47926f60 | 10658 | /* Check if operand is a register. */ |
4d1bb795 | 10659 | if ((r = parse_register (op_string, &end_op)) != NULL) |
24eab124 | 10660 | { |
40fb9820 L |
10661 | i386_operand_type temp; |
10662 | ||
24eab124 AM |
10663 | /* Check for a segment override by searching for ':' after a |
10664 | segment register. */ | |
10665 | op_string = end_op; | |
10666 | if (is_space_char (*op_string)) | |
10667 | ++op_string; | |
00cee14f | 10668 | if (*op_string == ':' && r->reg_type.bitfield.class == SReg) |
24eab124 AM |
10669 | { |
10670 | switch (r->reg_num) | |
10671 | { | |
10672 | case 0: | |
10673 | i.seg[i.mem_operands] = &es; | |
10674 | break; | |
10675 | case 1: | |
10676 | i.seg[i.mem_operands] = &cs; | |
10677 | break; | |
10678 | case 2: | |
10679 | i.seg[i.mem_operands] = &ss; | |
10680 | break; | |
10681 | case 3: | |
10682 | i.seg[i.mem_operands] = &ds; | |
10683 | break; | |
10684 | case 4: | |
10685 | i.seg[i.mem_operands] = &fs; | |
10686 | break; | |
10687 | case 5: | |
10688 | i.seg[i.mem_operands] = &gs; | |
10689 | break; | |
10690 | } | |
252b5132 | 10691 | |
24eab124 | 10692 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
10693 | ++op_string; |
10694 | if (is_space_char (*op_string)) | |
24eab124 | 10695 | ++op_string; |
252b5132 | 10696 | |
24eab124 AM |
10697 | if (!is_digit_char (*op_string) |
10698 | && !is_identifier_char (*op_string) | |
10699 | && *op_string != '(' | |
10700 | && *op_string != ABSOLUTE_PREFIX) | |
10701 | { | |
10702 | as_bad (_("bad memory operand `%s'"), op_string); | |
10703 | return 0; | |
10704 | } | |
47926f60 | 10705 | /* Handle case of %es:*foo. */ |
24eab124 AM |
10706 | if (*op_string == ABSOLUTE_PREFIX) |
10707 | { | |
10708 | ++op_string; | |
10709 | if (is_space_char (*op_string)) | |
10710 | ++op_string; | |
6f2f06be | 10711 | i.jumpabsolute = TRUE; |
24eab124 AM |
10712 | } |
10713 | goto do_memory_reference; | |
10714 | } | |
43234a1e L |
10715 | |
10716 | /* Handle vector operations. */ | |
10717 | if (*op_string == '{') | |
10718 | { | |
10719 | op_string = check_VecOperations (op_string, NULL); | |
10720 | if (op_string == NULL) | |
10721 | return 0; | |
10722 | } | |
10723 | ||
24eab124 AM |
10724 | if (*op_string) |
10725 | { | |
d0b47220 | 10726 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
10727 | return 0; |
10728 | } | |
40fb9820 L |
10729 | temp = r->reg_type; |
10730 | temp.bitfield.baseindex = 0; | |
c6fb90c8 L |
10731 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
10732 | temp); | |
7d5e4556 | 10733 | i.types[this_operand].bitfield.unspecified = 0; |
520dc8e8 | 10734 | i.op[this_operand].regs = r; |
24eab124 AM |
10735 | i.reg_operands++; |
10736 | } | |
af6bdddf AM |
10737 | else if (*op_string == REGISTER_PREFIX) |
10738 | { | |
10739 | as_bad (_("bad register name `%s'"), op_string); | |
10740 | return 0; | |
10741 | } | |
24eab124 | 10742 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 10743 | { |
24eab124 | 10744 | ++op_string; |
6f2f06be | 10745 | if (i.jumpabsolute) |
24eab124 | 10746 | { |
d0b47220 | 10747 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
10748 | return 0; |
10749 | } | |
10750 | if (!i386_immediate (op_string)) | |
10751 | return 0; | |
10752 | } | |
43234a1e L |
10753 | else if (RC_SAE_immediate (operand_string)) |
10754 | { | |
10755 | /* If it is a RC or SAE immediate, do nothing. */ | |
10756 | ; | |
10757 | } | |
24eab124 AM |
10758 | else if (is_digit_char (*op_string) |
10759 | || is_identifier_char (*op_string) | |
d02603dc | 10760 | || *op_string == '"' |
e5cb08ac | 10761 | || *op_string == '(') |
24eab124 | 10762 | { |
47926f60 | 10763 | /* This is a memory reference of some sort. */ |
af6bdddf | 10764 | char *base_string; |
252b5132 | 10765 | |
47926f60 | 10766 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
10767 | char *displacement_string_start; |
10768 | char *displacement_string_end; | |
43234a1e | 10769 | char *vop_start; |
252b5132 | 10770 | |
24eab124 | 10771 | do_memory_reference: |
8325cc63 JB |
10772 | if (i.mem_operands == 1 && !maybe_adjust_templates ()) |
10773 | return 0; | |
24eab124 | 10774 | if ((i.mem_operands == 1 |
40fb9820 | 10775 | && !current_templates->start->opcode_modifier.isstring) |
24eab124 AM |
10776 | || i.mem_operands == 2) |
10777 | { | |
10778 | as_bad (_("too many memory references for `%s'"), | |
10779 | current_templates->start->name); | |
10780 | return 0; | |
10781 | } | |
252b5132 | 10782 | |
24eab124 AM |
10783 | /* Check for base index form. We detect the base index form by |
10784 | looking for an ')' at the end of the operand, searching | |
10785 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
10786 | after the '('. */ | |
af6bdddf | 10787 | base_string = op_string + strlen (op_string); |
c3332e24 | 10788 | |
43234a1e L |
10789 | /* Handle vector operations. */ |
10790 | vop_start = strchr (op_string, '{'); | |
10791 | if (vop_start && vop_start < base_string) | |
10792 | { | |
10793 | if (check_VecOperations (vop_start, base_string) == NULL) | |
10794 | return 0; | |
10795 | base_string = vop_start; | |
10796 | } | |
10797 | ||
af6bdddf AM |
10798 | --base_string; |
10799 | if (is_space_char (*base_string)) | |
10800 | --base_string; | |
252b5132 | 10801 | |
47926f60 | 10802 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
10803 | displacement_string_start = op_string; |
10804 | displacement_string_end = base_string + 1; | |
252b5132 | 10805 | |
24eab124 AM |
10806 | if (*base_string == ')') |
10807 | { | |
af6bdddf | 10808 | char *temp_string; |
24eab124 AM |
10809 | unsigned int parens_balanced = 1; |
10810 | /* We've already checked that the number of left & right ()'s are | |
47926f60 | 10811 | equal, so this loop will not be infinite. */ |
24eab124 AM |
10812 | do |
10813 | { | |
10814 | base_string--; | |
10815 | if (*base_string == ')') | |
10816 | parens_balanced++; | |
10817 | if (*base_string == '(') | |
10818 | parens_balanced--; | |
10819 | } | |
10820 | while (parens_balanced); | |
c3332e24 | 10821 | |
af6bdddf | 10822 | temp_string = base_string; |
c3332e24 | 10823 | |
24eab124 | 10824 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
10825 | ++base_string; |
10826 | if (is_space_char (*base_string)) | |
24eab124 | 10827 | ++base_string; |
252b5132 | 10828 | |
af6bdddf | 10829 | if (*base_string == ',' |
4eed87de AM |
10830 | || ((i.base_reg = parse_register (base_string, &end_op)) |
10831 | != NULL)) | |
252b5132 | 10832 | { |
af6bdddf | 10833 | displacement_string_end = temp_string; |
252b5132 | 10834 | |
40fb9820 | 10835 | i.types[this_operand].bitfield.baseindex = 1; |
252b5132 | 10836 | |
af6bdddf | 10837 | if (i.base_reg) |
24eab124 | 10838 | { |
24eab124 AM |
10839 | base_string = end_op; |
10840 | if (is_space_char (*base_string)) | |
10841 | ++base_string; | |
af6bdddf AM |
10842 | } |
10843 | ||
10844 | /* There may be an index reg or scale factor here. */ | |
10845 | if (*base_string == ',') | |
10846 | { | |
10847 | ++base_string; | |
10848 | if (is_space_char (*base_string)) | |
10849 | ++base_string; | |
10850 | ||
4eed87de AM |
10851 | if ((i.index_reg = parse_register (base_string, &end_op)) |
10852 | != NULL) | |
24eab124 | 10853 | { |
af6bdddf | 10854 | base_string = end_op; |
24eab124 AM |
10855 | if (is_space_char (*base_string)) |
10856 | ++base_string; | |
af6bdddf AM |
10857 | if (*base_string == ',') |
10858 | { | |
10859 | ++base_string; | |
10860 | if (is_space_char (*base_string)) | |
10861 | ++base_string; | |
10862 | } | |
e5cb08ac | 10863 | else if (*base_string != ')') |
af6bdddf | 10864 | { |
4eed87de AM |
10865 | as_bad (_("expecting `,' or `)' " |
10866 | "after index register in `%s'"), | |
af6bdddf AM |
10867 | operand_string); |
10868 | return 0; | |
10869 | } | |
24eab124 | 10870 | } |
af6bdddf | 10871 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 10872 | { |
f76bf5e0 L |
10873 | end_op = strchr (base_string, ','); |
10874 | if (end_op) | |
10875 | *end_op = '\0'; | |
af6bdddf | 10876 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
10877 | return 0; |
10878 | } | |
252b5132 | 10879 | |
47926f60 | 10880 | /* Check for scale factor. */ |
551c1ca1 | 10881 | if (*base_string != ')') |
af6bdddf | 10882 | { |
551c1ca1 AM |
10883 | char *end_scale = i386_scale (base_string); |
10884 | ||
10885 | if (!end_scale) | |
af6bdddf | 10886 | return 0; |
24eab124 | 10887 | |
551c1ca1 | 10888 | base_string = end_scale; |
af6bdddf AM |
10889 | if (is_space_char (*base_string)) |
10890 | ++base_string; | |
10891 | if (*base_string != ')') | |
10892 | { | |
4eed87de AM |
10893 | as_bad (_("expecting `)' " |
10894 | "after scale factor in `%s'"), | |
af6bdddf AM |
10895 | operand_string); |
10896 | return 0; | |
10897 | } | |
10898 | } | |
10899 | else if (!i.index_reg) | |
24eab124 | 10900 | { |
4eed87de AM |
10901 | as_bad (_("expecting index register or scale factor " |
10902 | "after `,'; got '%c'"), | |
af6bdddf | 10903 | *base_string); |
24eab124 AM |
10904 | return 0; |
10905 | } | |
10906 | } | |
af6bdddf | 10907 | else if (*base_string != ')') |
24eab124 | 10908 | { |
4eed87de AM |
10909 | as_bad (_("expecting `,' or `)' " |
10910 | "after base register in `%s'"), | |
af6bdddf | 10911 | operand_string); |
24eab124 AM |
10912 | return 0; |
10913 | } | |
c3332e24 | 10914 | } |
af6bdddf | 10915 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 10916 | { |
f76bf5e0 L |
10917 | end_op = strchr (base_string, ','); |
10918 | if (end_op) | |
10919 | *end_op = '\0'; | |
af6bdddf | 10920 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 10921 | return 0; |
c3332e24 | 10922 | } |
24eab124 AM |
10923 | } |
10924 | ||
10925 | /* If there's an expression beginning the operand, parse it, | |
10926 | assuming displacement_string_start and | |
10927 | displacement_string_end are meaningful. */ | |
10928 | if (displacement_string_start != displacement_string_end) | |
10929 | { | |
10930 | if (!i386_displacement (displacement_string_start, | |
10931 | displacement_string_end)) | |
10932 | return 0; | |
10933 | } | |
10934 | ||
10935 | /* Special case for (%dx) while doing input/output op. */ | |
10936 | if (i.base_reg | |
75e5731b JB |
10937 | && i.base_reg->reg_type.bitfield.instance == RegD |
10938 | && i.base_reg->reg_type.bitfield.word | |
24eab124 AM |
10939 | && i.index_reg == 0 |
10940 | && i.log2_scale_factor == 0 | |
10941 | && i.seg[i.mem_operands] == 0 | |
40fb9820 | 10942 | && !operand_type_check (i.types[this_operand], disp)) |
24eab124 | 10943 | { |
2fb5be8d | 10944 | i.types[this_operand] = i.base_reg->reg_type; |
24eab124 AM |
10945 | return 1; |
10946 | } | |
10947 | ||
eecb386c AM |
10948 | if (i386_index_check (operand_string) == 0) |
10949 | return 0; | |
c48dadc9 | 10950 | i.flags[this_operand] |= Operand_Mem; |
8325cc63 JB |
10951 | if (i.mem_operands == 0) |
10952 | i.memop1_string = xstrdup (operand_string); | |
24eab124 AM |
10953 | i.mem_operands++; |
10954 | } | |
10955 | else | |
ce8a8b2f AM |
10956 | { |
10957 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
10958 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
10959 | output_invalid (*op_string), | |
10960 | this_operand + 1, | |
10961 | op_string); | |
10962 | return 0; | |
10963 | } | |
47926f60 | 10964 | return 1; /* Normal return. */ |
252b5132 RH |
10965 | } |
10966 | \f | |
fa94de6b RM |
10967 | /* Calculate the maximum variable size (i.e., excluding fr_fix) |
10968 | that an rs_machine_dependent frag may reach. */ | |
10969 | ||
10970 | unsigned int | |
10971 | i386_frag_max_var (fragS *frag) | |
10972 | { | |
10973 | /* The only relaxable frags are for jumps. | |
10974 | Unconditional jumps can grow by 4 bytes and others by 5 bytes. */ | |
10975 | gas_assert (frag->fr_type == rs_machine_dependent); | |
10976 | return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5; | |
10977 | } | |
10978 | ||
b084df0b L |
10979 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
10980 | static int | |
8dcea932 | 10981 | elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var) |
b084df0b L |
10982 | { |
10983 | /* STT_GNU_IFUNC symbol must go through PLT. */ | |
10984 | if ((symbol_get_bfdsym (fr_symbol)->flags | |
10985 | & BSF_GNU_INDIRECT_FUNCTION) != 0) | |
10986 | return 0; | |
10987 | ||
10988 | if (!S_IS_EXTERNAL (fr_symbol)) | |
10989 | /* Symbol may be weak or local. */ | |
10990 | return !S_IS_WEAK (fr_symbol); | |
10991 | ||
8dcea932 L |
10992 | /* Global symbols with non-default visibility can't be preempted. */ |
10993 | if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT) | |
10994 | return 1; | |
10995 | ||
10996 | if (fr_var != NO_RELOC) | |
10997 | switch ((enum bfd_reloc_code_real) fr_var) | |
10998 | { | |
10999 | case BFD_RELOC_386_PLT32: | |
11000 | case BFD_RELOC_X86_64_PLT32: | |
33eaf5de | 11001 | /* Symbol with PLT relocation may be preempted. */ |
8dcea932 L |
11002 | return 0; |
11003 | default: | |
11004 | abort (); | |
11005 | } | |
11006 | ||
b084df0b L |
11007 | /* Global symbols with default visibility in a shared library may be |
11008 | preempted by another definition. */ | |
8dcea932 | 11009 | return !shared; |
b084df0b L |
11010 | } |
11011 | #endif | |
11012 | ||
79d72f45 HL |
11013 | /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture |
11014 | Note also work for Skylake and Cascadelake. | |
11015 | --------------------------------------------------------------------- | |
11016 | | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND | | |
11017 | | ------ | ----------- | ------- | -------- | | |
11018 | | Jo | N | N | Y | | |
11019 | | Jno | N | N | Y | | |
11020 | | Jc/Jb | Y | N | Y | | |
11021 | | Jae/Jnb | Y | N | Y | | |
11022 | | Je/Jz | Y | Y | Y | | |
11023 | | Jne/Jnz | Y | Y | Y | | |
11024 | | Jna/Jbe | Y | N | Y | | |
11025 | | Ja/Jnbe | Y | N | Y | | |
11026 | | Js | N | N | Y | | |
11027 | | Jns | N | N | Y | | |
11028 | | Jp/Jpe | N | N | Y | | |
11029 | | Jnp/Jpo | N | N | Y | | |
11030 | | Jl/Jnge | Y | Y | Y | | |
11031 | | Jge/Jnl | Y | Y | Y | | |
11032 | | Jle/Jng | Y | Y | Y | | |
11033 | | Jg/Jnle | Y | Y | Y | | |
11034 | --------------------------------------------------------------------- */ | |
11035 | static int | |
11036 | i386_macro_fusible_p (enum mf_cmp_kind mf_cmp, enum mf_jcc_kind mf_jcc) | |
11037 | { | |
11038 | if (mf_cmp == mf_cmp_alu_cmp) | |
11039 | return ((mf_jcc >= mf_jcc_jc && mf_jcc <= mf_jcc_jna) | |
11040 | || mf_jcc == mf_jcc_jl || mf_jcc == mf_jcc_jle); | |
11041 | if (mf_cmp == mf_cmp_incdec) | |
11042 | return (mf_jcc == mf_jcc_je || mf_jcc == mf_jcc_jl | |
11043 | || mf_jcc == mf_jcc_jle); | |
11044 | if (mf_cmp == mf_cmp_test_and) | |
11045 | return 1; | |
11046 | return 0; | |
11047 | } | |
11048 | ||
e379e5f3 L |
11049 | /* Return the next non-empty frag. */ |
11050 | ||
11051 | static fragS * | |
11052 | i386_next_non_empty_frag (fragS *fragP) | |
11053 | { | |
11054 | /* There may be a frag with a ".fill 0" when there is no room in | |
11055 | the current frag for frag_grow in output_insn. */ | |
11056 | for (fragP = fragP->fr_next; | |
11057 | (fragP != NULL | |
11058 | && fragP->fr_type == rs_fill | |
11059 | && fragP->fr_fix == 0); | |
11060 | fragP = fragP->fr_next) | |
11061 | ; | |
11062 | return fragP; | |
11063 | } | |
11064 | ||
11065 | /* Return the next jcc frag after BRANCH_PADDING. */ | |
11066 | ||
11067 | static fragS * | |
79d72f45 | 11068 | i386_next_fusible_jcc_frag (fragS *maybe_cmp_fragP, fragS *pad_fragP) |
e379e5f3 | 11069 | { |
79d72f45 HL |
11070 | fragS *branch_fragP; |
11071 | if (!pad_fragP) | |
e379e5f3 L |
11072 | return NULL; |
11073 | ||
79d72f45 HL |
11074 | if (pad_fragP->fr_type == rs_machine_dependent |
11075 | && (TYPE_FROM_RELAX_STATE (pad_fragP->fr_subtype) | |
e379e5f3 L |
11076 | == BRANCH_PADDING)) |
11077 | { | |
79d72f45 HL |
11078 | branch_fragP = i386_next_non_empty_frag (pad_fragP); |
11079 | if (branch_fragP->fr_type != rs_machine_dependent) | |
e379e5f3 | 11080 | return NULL; |
79d72f45 HL |
11081 | if (TYPE_FROM_RELAX_STATE (branch_fragP->fr_subtype) == COND_JUMP |
11082 | && i386_macro_fusible_p (maybe_cmp_fragP->tc_frag_data.mf_type, | |
11083 | pad_fragP->tc_frag_data.mf_type)) | |
11084 | return branch_fragP; | |
e379e5f3 L |
11085 | } |
11086 | ||
11087 | return NULL; | |
11088 | } | |
11089 | ||
11090 | /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */ | |
11091 | ||
11092 | static void | |
11093 | i386_classify_machine_dependent_frag (fragS *fragP) | |
11094 | { | |
11095 | fragS *cmp_fragP; | |
11096 | fragS *pad_fragP; | |
11097 | fragS *branch_fragP; | |
11098 | fragS *next_fragP; | |
11099 | unsigned int max_prefix_length; | |
11100 | ||
11101 | if (fragP->tc_frag_data.classified) | |
11102 | return; | |
11103 | ||
11104 | /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert | |
11105 | FUSED_JCC_PADDING and merge BRANCH_PADDING. */ | |
11106 | for (next_fragP = fragP; | |
11107 | next_fragP != NULL; | |
11108 | next_fragP = next_fragP->fr_next) | |
11109 | { | |
11110 | next_fragP->tc_frag_data.classified = 1; | |
11111 | if (next_fragP->fr_type == rs_machine_dependent) | |
11112 | switch (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)) | |
11113 | { | |
11114 | case BRANCH_PADDING: | |
11115 | /* The BRANCH_PADDING frag must be followed by a branch | |
11116 | frag. */ | |
11117 | branch_fragP = i386_next_non_empty_frag (next_fragP); | |
11118 | next_fragP->tc_frag_data.u.branch_fragP = branch_fragP; | |
11119 | break; | |
11120 | case FUSED_JCC_PADDING: | |
11121 | /* Check if this is a fused jcc: | |
11122 | FUSED_JCC_PADDING | |
11123 | CMP like instruction | |
11124 | BRANCH_PADDING | |
11125 | COND_JUMP | |
11126 | */ | |
11127 | cmp_fragP = i386_next_non_empty_frag (next_fragP); | |
11128 | pad_fragP = i386_next_non_empty_frag (cmp_fragP); | |
79d72f45 | 11129 | branch_fragP = i386_next_fusible_jcc_frag (next_fragP, pad_fragP); |
e379e5f3 L |
11130 | if (branch_fragP) |
11131 | { | |
11132 | /* The BRANCH_PADDING frag is merged with the | |
11133 | FUSED_JCC_PADDING frag. */ | |
11134 | next_fragP->tc_frag_data.u.branch_fragP = branch_fragP; | |
11135 | /* CMP like instruction size. */ | |
11136 | next_fragP->tc_frag_data.cmp_size = cmp_fragP->fr_fix; | |
11137 | frag_wane (pad_fragP); | |
11138 | /* Skip to branch_fragP. */ | |
11139 | next_fragP = branch_fragP; | |
11140 | } | |
11141 | else if (next_fragP->tc_frag_data.max_prefix_length) | |
11142 | { | |
11143 | /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't | |
11144 | a fused jcc. */ | |
11145 | next_fragP->fr_subtype | |
11146 | = ENCODE_RELAX_STATE (BRANCH_PREFIX, 0); | |
11147 | next_fragP->tc_frag_data.max_bytes | |
11148 | = next_fragP->tc_frag_data.max_prefix_length; | |
11149 | /* This will be updated in the BRANCH_PREFIX scan. */ | |
11150 | next_fragP->tc_frag_data.max_prefix_length = 0; | |
11151 | } | |
11152 | else | |
11153 | frag_wane (next_fragP); | |
11154 | break; | |
11155 | } | |
11156 | } | |
11157 | ||
11158 | /* Stop if there is no BRANCH_PREFIX. */ | |
11159 | if (!align_branch_prefix_size) | |
11160 | return; | |
11161 | ||
11162 | /* Scan for BRANCH_PREFIX. */ | |
11163 | for (; fragP != NULL; fragP = fragP->fr_next) | |
11164 | { | |
11165 | if (fragP->fr_type != rs_machine_dependent | |
11166 | || (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
11167 | != BRANCH_PREFIX)) | |
11168 | continue; | |
11169 | ||
11170 | /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and | |
11171 | COND_JUMP_PREFIX. */ | |
11172 | max_prefix_length = 0; | |
11173 | for (next_fragP = fragP; | |
11174 | next_fragP != NULL; | |
11175 | next_fragP = next_fragP->fr_next) | |
11176 | { | |
11177 | if (next_fragP->fr_type == rs_fill) | |
11178 | /* Skip rs_fill frags. */ | |
11179 | continue; | |
11180 | else if (next_fragP->fr_type != rs_machine_dependent) | |
11181 | /* Stop for all other frags. */ | |
11182 | break; | |
11183 | ||
11184 | /* rs_machine_dependent frags. */ | |
11185 | if (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
11186 | == BRANCH_PREFIX) | |
11187 | { | |
11188 | /* Count BRANCH_PREFIX frags. */ | |
11189 | if (max_prefix_length >= MAX_FUSED_JCC_PADDING_SIZE) | |
11190 | { | |
11191 | max_prefix_length = MAX_FUSED_JCC_PADDING_SIZE; | |
11192 | frag_wane (next_fragP); | |
11193 | } | |
11194 | else | |
11195 | max_prefix_length | |
11196 | += next_fragP->tc_frag_data.max_bytes; | |
11197 | } | |
11198 | else if ((TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
11199 | == BRANCH_PADDING) | |
11200 | || (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
11201 | == FUSED_JCC_PADDING)) | |
11202 | { | |
11203 | /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */ | |
11204 | fragP->tc_frag_data.u.padding_fragP = next_fragP; | |
11205 | break; | |
11206 | } | |
11207 | else | |
11208 | /* Stop for other rs_machine_dependent frags. */ | |
11209 | break; | |
11210 | } | |
11211 | ||
11212 | fragP->tc_frag_data.max_prefix_length = max_prefix_length; | |
11213 | ||
11214 | /* Skip to the next frag. */ | |
11215 | fragP = next_fragP; | |
11216 | } | |
11217 | } | |
11218 | ||
11219 | /* Compute padding size for | |
11220 | ||
11221 | FUSED_JCC_PADDING | |
11222 | CMP like instruction | |
11223 | BRANCH_PADDING | |
11224 | COND_JUMP/UNCOND_JUMP | |
11225 | ||
11226 | or | |
11227 | ||
11228 | BRANCH_PADDING | |
11229 | COND_JUMP/UNCOND_JUMP | |
11230 | */ | |
11231 | ||
11232 | static int | |
11233 | i386_branch_padding_size (fragS *fragP, offsetT address) | |
11234 | { | |
11235 | unsigned int offset, size, padding_size; | |
11236 | fragS *branch_fragP = fragP->tc_frag_data.u.branch_fragP; | |
11237 | ||
11238 | /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */ | |
11239 | if (!address) | |
11240 | address = fragP->fr_address; | |
11241 | address += fragP->fr_fix; | |
11242 | ||
11243 | /* CMP like instrunction size. */ | |
11244 | size = fragP->tc_frag_data.cmp_size; | |
11245 | ||
11246 | /* The base size of the branch frag. */ | |
11247 | size += branch_fragP->fr_fix; | |
11248 | ||
11249 | /* Add opcode and displacement bytes for the rs_machine_dependent | |
11250 | branch frag. */ | |
11251 | if (branch_fragP->fr_type == rs_machine_dependent) | |
11252 | size += md_relax_table[branch_fragP->fr_subtype].rlx_length; | |
11253 | ||
11254 | /* Check if branch is within boundary and doesn't end at the last | |
11255 | byte. */ | |
11256 | offset = address & ((1U << align_branch_power) - 1); | |
11257 | if ((offset + size) >= (1U << align_branch_power)) | |
11258 | /* Padding needed to avoid crossing boundary. */ | |
11259 | padding_size = (1U << align_branch_power) - offset; | |
11260 | else | |
11261 | /* No padding needed. */ | |
11262 | padding_size = 0; | |
11263 | ||
11264 | /* The return value may be saved in tc_frag_data.length which is | |
11265 | unsigned byte. */ | |
11266 | if (!fits_in_unsigned_byte (padding_size)) | |
11267 | abort (); | |
11268 | ||
11269 | return padding_size; | |
11270 | } | |
11271 | ||
11272 | /* i386_generic_table_relax_frag() | |
11273 | ||
11274 | Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to | |
11275 | grow/shrink padding to align branch frags. Hand others to | |
11276 | relax_frag(). */ | |
11277 | ||
11278 | long | |
11279 | i386_generic_table_relax_frag (segT segment, fragS *fragP, long stretch) | |
11280 | { | |
11281 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING | |
11282 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
11283 | { | |
11284 | long padding_size = i386_branch_padding_size (fragP, 0); | |
11285 | long grow = padding_size - fragP->tc_frag_data.length; | |
11286 | ||
11287 | /* When the BRANCH_PREFIX frag is used, the computed address | |
11288 | must match the actual address and there should be no padding. */ | |
11289 | if (fragP->tc_frag_data.padding_address | |
11290 | && (fragP->tc_frag_data.padding_address != fragP->fr_address | |
11291 | || padding_size)) | |
11292 | abort (); | |
11293 | ||
11294 | /* Update the padding size. */ | |
11295 | if (grow) | |
11296 | fragP->tc_frag_data.length = padding_size; | |
11297 | ||
11298 | return grow; | |
11299 | } | |
11300 | else if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
11301 | { | |
11302 | fragS *padding_fragP, *next_fragP; | |
11303 | long padding_size, left_size, last_size; | |
11304 | ||
11305 | padding_fragP = fragP->tc_frag_data.u.padding_fragP; | |
11306 | if (!padding_fragP) | |
11307 | /* Use the padding set by the leading BRANCH_PREFIX frag. */ | |
11308 | return (fragP->tc_frag_data.length | |
11309 | - fragP->tc_frag_data.last_length); | |
11310 | ||
11311 | /* Compute the relative address of the padding frag in the very | |
11312 | first time where the BRANCH_PREFIX frag sizes are zero. */ | |
11313 | if (!fragP->tc_frag_data.padding_address) | |
11314 | fragP->tc_frag_data.padding_address | |
11315 | = padding_fragP->fr_address - (fragP->fr_address - stretch); | |
11316 | ||
11317 | /* First update the last length from the previous interation. */ | |
11318 | left_size = fragP->tc_frag_data.prefix_length; | |
11319 | for (next_fragP = fragP; | |
11320 | next_fragP != padding_fragP; | |
11321 | next_fragP = next_fragP->fr_next) | |
11322 | if (next_fragP->fr_type == rs_machine_dependent | |
11323 | && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
11324 | == BRANCH_PREFIX)) | |
11325 | { | |
11326 | if (left_size) | |
11327 | { | |
11328 | int max = next_fragP->tc_frag_data.max_bytes; | |
11329 | if (max) | |
11330 | { | |
11331 | int size; | |
11332 | if (max > left_size) | |
11333 | size = left_size; | |
11334 | else | |
11335 | size = max; | |
11336 | left_size -= size; | |
11337 | next_fragP->tc_frag_data.last_length = size; | |
11338 | } | |
11339 | } | |
11340 | else | |
11341 | next_fragP->tc_frag_data.last_length = 0; | |
11342 | } | |
11343 | ||
11344 | /* Check the padding size for the padding frag. */ | |
11345 | padding_size = i386_branch_padding_size | |
11346 | (padding_fragP, (fragP->fr_address | |
11347 | + fragP->tc_frag_data.padding_address)); | |
11348 | ||
11349 | last_size = fragP->tc_frag_data.prefix_length; | |
11350 | /* Check if there is change from the last interation. */ | |
11351 | if (padding_size == last_size) | |
11352 | { | |
11353 | /* Update the expected address of the padding frag. */ | |
11354 | padding_fragP->tc_frag_data.padding_address | |
11355 | = (fragP->fr_address + padding_size | |
11356 | + fragP->tc_frag_data.padding_address); | |
11357 | return 0; | |
11358 | } | |
11359 | ||
11360 | if (padding_size > fragP->tc_frag_data.max_prefix_length) | |
11361 | { | |
11362 | /* No padding if there is no sufficient room. Clear the | |
11363 | expected address of the padding frag. */ | |
11364 | padding_fragP->tc_frag_data.padding_address = 0; | |
11365 | padding_size = 0; | |
11366 | } | |
11367 | else | |
11368 | /* Store the expected address of the padding frag. */ | |
11369 | padding_fragP->tc_frag_data.padding_address | |
11370 | = (fragP->fr_address + padding_size | |
11371 | + fragP->tc_frag_data.padding_address); | |
11372 | ||
11373 | fragP->tc_frag_data.prefix_length = padding_size; | |
11374 | ||
11375 | /* Update the length for the current interation. */ | |
11376 | left_size = padding_size; | |
11377 | for (next_fragP = fragP; | |
11378 | next_fragP != padding_fragP; | |
11379 | next_fragP = next_fragP->fr_next) | |
11380 | if (next_fragP->fr_type == rs_machine_dependent | |
11381 | && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
11382 | == BRANCH_PREFIX)) | |
11383 | { | |
11384 | if (left_size) | |
11385 | { | |
11386 | int max = next_fragP->tc_frag_data.max_bytes; | |
11387 | if (max) | |
11388 | { | |
11389 | int size; | |
11390 | if (max > left_size) | |
11391 | size = left_size; | |
11392 | else | |
11393 | size = max; | |
11394 | left_size -= size; | |
11395 | next_fragP->tc_frag_data.length = size; | |
11396 | } | |
11397 | } | |
11398 | else | |
11399 | next_fragP->tc_frag_data.length = 0; | |
11400 | } | |
11401 | ||
11402 | return (fragP->tc_frag_data.length | |
11403 | - fragP->tc_frag_data.last_length); | |
11404 | } | |
11405 | return relax_frag (segment, fragP, stretch); | |
11406 | } | |
11407 | ||
ee7fcc42 AM |
11408 | /* md_estimate_size_before_relax() |
11409 | ||
11410 | Called just before relax() for rs_machine_dependent frags. The x86 | |
11411 | assembler uses these frags to handle variable size jump | |
11412 | instructions. | |
11413 | ||
11414 | Any symbol that is now undefined will not become defined. | |
11415 | Return the correct fr_subtype in the frag. | |
11416 | Return the initial "guess for variable size of frag" to caller. | |
11417 | The guess is actually the growth beyond the fixed part. Whatever | |
11418 | we do to grow the fixed or variable part contributes to our | |
11419 | returned value. */ | |
11420 | ||
252b5132 | 11421 | int |
7016a5d5 | 11422 | md_estimate_size_before_relax (fragS *fragP, segT segment) |
252b5132 | 11423 | { |
e379e5f3 L |
11424 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING |
11425 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX | |
11426 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
11427 | { | |
11428 | i386_classify_machine_dependent_frag (fragP); | |
11429 | return fragP->tc_frag_data.length; | |
11430 | } | |
11431 | ||
252b5132 | 11432 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
11433 | check for un-relaxable symbols. On an ELF system, we can't relax |
11434 | an externally visible symbol, because it may be overridden by a | |
11435 | shared library. */ | |
11436 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 11437 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 11438 | || (IS_ELF |
8dcea932 L |
11439 | && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol, |
11440 | fragP->fr_var)) | |
fbeb56a4 DK |
11441 | #endif |
11442 | #if defined (OBJ_COFF) && defined (TE_PE) | |
7ab9ffdd | 11443 | || (OUTPUT_FLAVOR == bfd_target_coff_flavour |
fbeb56a4 | 11444 | && S_IS_WEAK (fragP->fr_symbol)) |
b98ef147 AM |
11445 | #endif |
11446 | ) | |
252b5132 | 11447 | { |
b98ef147 AM |
11448 | /* Symbol is undefined in this segment, or we need to keep a |
11449 | reloc so that weak symbols can be overridden. */ | |
11450 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f86103b7 | 11451 | enum bfd_reloc_code_real reloc_type; |
ee7fcc42 AM |
11452 | unsigned char *opcode; |
11453 | int old_fr_fix; | |
f6af82bd | 11454 | |
ee7fcc42 | 11455 | if (fragP->fr_var != NO_RELOC) |
1e9cc1c2 | 11456 | reloc_type = (enum bfd_reloc_code_real) fragP->fr_var; |
b98ef147 | 11457 | else if (size == 2) |
f6af82bd | 11458 | reloc_type = BFD_RELOC_16_PCREL; |
bd7ab16b L |
11459 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
11460 | else if (need_plt32_p (fragP->fr_symbol)) | |
11461 | reloc_type = BFD_RELOC_X86_64_PLT32; | |
11462 | #endif | |
f6af82bd AM |
11463 | else |
11464 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 11465 | |
ee7fcc42 AM |
11466 | old_fr_fix = fragP->fr_fix; |
11467 | opcode = (unsigned char *) fragP->fr_opcode; | |
11468 | ||
fddf5b5b | 11469 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 11470 | { |
fddf5b5b AM |
11471 | case UNCOND_JUMP: |
11472 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 11473 | opcode[0] = 0xe9; |
252b5132 | 11474 | fragP->fr_fix += size; |
062cd5e7 AS |
11475 | fix_new (fragP, old_fr_fix, size, |
11476 | fragP->fr_symbol, | |
11477 | fragP->fr_offset, 1, | |
11478 | reloc_type); | |
252b5132 RH |
11479 | break; |
11480 | ||
fddf5b5b | 11481 | case COND_JUMP86: |
412167cb AM |
11482 | if (size == 2 |
11483 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) | |
fddf5b5b AM |
11484 | { |
11485 | /* Negate the condition, and branch past an | |
11486 | unconditional jump. */ | |
11487 | opcode[0] ^= 1; | |
11488 | opcode[1] = 3; | |
11489 | /* Insert an unconditional jump. */ | |
11490 | opcode[2] = 0xe9; | |
11491 | /* We added two extra opcode bytes, and have a two byte | |
11492 | offset. */ | |
11493 | fragP->fr_fix += 2 + 2; | |
062cd5e7 AS |
11494 | fix_new (fragP, old_fr_fix + 2, 2, |
11495 | fragP->fr_symbol, | |
11496 | fragP->fr_offset, 1, | |
11497 | reloc_type); | |
fddf5b5b AM |
11498 | break; |
11499 | } | |
11500 | /* Fall through. */ | |
11501 | ||
11502 | case COND_JUMP: | |
412167cb AM |
11503 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
11504 | { | |
3e02c1cc AM |
11505 | fixS *fixP; |
11506 | ||
412167cb | 11507 | fragP->fr_fix += 1; |
3e02c1cc AM |
11508 | fixP = fix_new (fragP, old_fr_fix, 1, |
11509 | fragP->fr_symbol, | |
11510 | fragP->fr_offset, 1, | |
11511 | BFD_RELOC_8_PCREL); | |
11512 | fixP->fx_signed = 1; | |
412167cb AM |
11513 | break; |
11514 | } | |
93c2a809 | 11515 | |
24eab124 | 11516 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 11517 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 11518 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 11519 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
11520 | /* We've added an opcode byte. */ |
11521 | fragP->fr_fix += 1 + size; | |
062cd5e7 AS |
11522 | fix_new (fragP, old_fr_fix + 1, size, |
11523 | fragP->fr_symbol, | |
11524 | fragP->fr_offset, 1, | |
11525 | reloc_type); | |
252b5132 | 11526 | break; |
fddf5b5b AM |
11527 | |
11528 | default: | |
11529 | BAD_CASE (fragP->fr_subtype); | |
11530 | break; | |
252b5132 RH |
11531 | } |
11532 | frag_wane (fragP); | |
ee7fcc42 | 11533 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 11534 | } |
93c2a809 | 11535 | |
93c2a809 AM |
11536 | /* Guess size depending on current relax state. Initially the relax |
11537 | state will correspond to a short jump and we return 1, because | |
11538 | the variable part of the frag (the branch offset) is one byte | |
11539 | long. However, we can relax a section more than once and in that | |
11540 | case we must either set fr_subtype back to the unrelaxed state, | |
11541 | or return the value for the appropriate branch. */ | |
11542 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
11543 | } |
11544 | ||
47926f60 KH |
11545 | /* Called after relax() is finished. |
11546 | ||
11547 | In: Address of frag. | |
11548 | fr_type == rs_machine_dependent. | |
11549 | fr_subtype is what the address relaxed to. | |
11550 | ||
11551 | Out: Any fixSs and constants are set up. | |
11552 | Caller will turn frag into a ".space 0". */ | |
11553 | ||
252b5132 | 11554 | void |
7016a5d5 TG |
11555 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, |
11556 | fragS *fragP) | |
252b5132 | 11557 | { |
29b0f896 | 11558 | unsigned char *opcode; |
252b5132 | 11559 | unsigned char *where_to_put_displacement = NULL; |
847f7ad4 AM |
11560 | offsetT target_address; |
11561 | offsetT opcode_address; | |
252b5132 | 11562 | unsigned int extension = 0; |
847f7ad4 | 11563 | offsetT displacement_from_opcode_start; |
252b5132 | 11564 | |
e379e5f3 L |
11565 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING |
11566 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING | |
11567 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
11568 | { | |
11569 | /* Generate nop padding. */ | |
11570 | unsigned int size = fragP->tc_frag_data.length; | |
11571 | if (size) | |
11572 | { | |
11573 | if (size > fragP->tc_frag_data.max_bytes) | |
11574 | abort (); | |
11575 | ||
11576 | if (flag_debug) | |
11577 | { | |
11578 | const char *msg; | |
11579 | const char *branch = "branch"; | |
11580 | const char *prefix = ""; | |
11581 | fragS *padding_fragP; | |
11582 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
11583 | == BRANCH_PREFIX) | |
11584 | { | |
11585 | padding_fragP = fragP->tc_frag_data.u.padding_fragP; | |
11586 | switch (fragP->tc_frag_data.default_prefix) | |
11587 | { | |
11588 | default: | |
11589 | abort (); | |
11590 | break; | |
11591 | case CS_PREFIX_OPCODE: | |
11592 | prefix = " cs"; | |
11593 | break; | |
11594 | case DS_PREFIX_OPCODE: | |
11595 | prefix = " ds"; | |
11596 | break; | |
11597 | case ES_PREFIX_OPCODE: | |
11598 | prefix = " es"; | |
11599 | break; | |
11600 | case FS_PREFIX_OPCODE: | |
11601 | prefix = " fs"; | |
11602 | break; | |
11603 | case GS_PREFIX_OPCODE: | |
11604 | prefix = " gs"; | |
11605 | break; | |
11606 | case SS_PREFIX_OPCODE: | |
11607 | prefix = " ss"; | |
11608 | break; | |
11609 | } | |
11610 | if (padding_fragP) | |
11611 | msg = _("%s:%u: add %d%s at 0x%llx to align " | |
11612 | "%s within %d-byte boundary\n"); | |
11613 | else | |
11614 | msg = _("%s:%u: add additional %d%s at 0x%llx to " | |
11615 | "align %s within %d-byte boundary\n"); | |
11616 | } | |
11617 | else | |
11618 | { | |
11619 | padding_fragP = fragP; | |
11620 | msg = _("%s:%u: add %d%s-byte nop at 0x%llx to align " | |
11621 | "%s within %d-byte boundary\n"); | |
11622 | } | |
11623 | ||
11624 | if (padding_fragP) | |
11625 | switch (padding_fragP->tc_frag_data.branch_type) | |
11626 | { | |
11627 | case align_branch_jcc: | |
11628 | branch = "jcc"; | |
11629 | break; | |
11630 | case align_branch_fused: | |
11631 | branch = "fused jcc"; | |
11632 | break; | |
11633 | case align_branch_jmp: | |
11634 | branch = "jmp"; | |
11635 | break; | |
11636 | case align_branch_call: | |
11637 | branch = "call"; | |
11638 | break; | |
11639 | case align_branch_indirect: | |
11640 | branch = "indiret branch"; | |
11641 | break; | |
11642 | case align_branch_ret: | |
11643 | branch = "ret"; | |
11644 | break; | |
11645 | default: | |
11646 | break; | |
11647 | } | |
11648 | ||
11649 | fprintf (stdout, msg, | |
11650 | fragP->fr_file, fragP->fr_line, size, prefix, | |
11651 | (long long) fragP->fr_address, branch, | |
11652 | 1 << align_branch_power); | |
11653 | } | |
11654 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
11655 | memset (fragP->fr_opcode, | |
11656 | fragP->tc_frag_data.default_prefix, size); | |
11657 | else | |
11658 | i386_generate_nops (fragP, (char *) fragP->fr_opcode, | |
11659 | size, 0); | |
11660 | fragP->fr_fix += size; | |
11661 | } | |
11662 | return; | |
11663 | } | |
11664 | ||
252b5132 RH |
11665 | opcode = (unsigned char *) fragP->fr_opcode; |
11666 | ||
47926f60 | 11667 | /* Address we want to reach in file space. */ |
252b5132 | 11668 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 11669 | |
47926f60 | 11670 | /* Address opcode resides at in file space. */ |
252b5132 RH |
11671 | opcode_address = fragP->fr_address + fragP->fr_fix; |
11672 | ||
47926f60 | 11673 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
11674 | displacement_from_opcode_start = target_address - opcode_address; |
11675 | ||
fddf5b5b | 11676 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 11677 | { |
47926f60 KH |
11678 | /* Don't have to change opcode. */ |
11679 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 11680 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
11681 | } |
11682 | else | |
11683 | { | |
11684 | if (no_cond_jump_promotion | |
11685 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4eed87de AM |
11686 | as_warn_where (fragP->fr_file, fragP->fr_line, |
11687 | _("long jump required")); | |
252b5132 | 11688 | |
fddf5b5b AM |
11689 | switch (fragP->fr_subtype) |
11690 | { | |
11691 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
11692 | extension = 4; /* 1 opcode + 4 displacement */ | |
11693 | opcode[0] = 0xe9; | |
11694 | where_to_put_displacement = &opcode[1]; | |
11695 | break; | |
252b5132 | 11696 | |
fddf5b5b AM |
11697 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
11698 | extension = 2; /* 1 opcode + 2 displacement */ | |
11699 | opcode[0] = 0xe9; | |
11700 | where_to_put_displacement = &opcode[1]; | |
11701 | break; | |
252b5132 | 11702 | |
fddf5b5b AM |
11703 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
11704 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
11705 | extension = 5; /* 2 opcode + 4 displacement */ | |
11706 | opcode[1] = opcode[0] + 0x10; | |
11707 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
11708 | where_to_put_displacement = &opcode[2]; | |
11709 | break; | |
252b5132 | 11710 | |
fddf5b5b AM |
11711 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
11712 | extension = 3; /* 2 opcode + 2 displacement */ | |
11713 | opcode[1] = opcode[0] + 0x10; | |
11714 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
11715 | where_to_put_displacement = &opcode[2]; | |
11716 | break; | |
252b5132 | 11717 | |
fddf5b5b AM |
11718 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
11719 | extension = 4; | |
11720 | opcode[0] ^= 1; | |
11721 | opcode[1] = 3; | |
11722 | opcode[2] = 0xe9; | |
11723 | where_to_put_displacement = &opcode[3]; | |
11724 | break; | |
11725 | ||
11726 | default: | |
11727 | BAD_CASE (fragP->fr_subtype); | |
11728 | break; | |
11729 | } | |
252b5132 | 11730 | } |
fddf5b5b | 11731 | |
7b81dfbb AJ |
11732 | /* If size if less then four we are sure that the operand fits, |
11733 | but if it's 4, then it could be that the displacement is larger | |
11734 | then -/+ 2GB. */ | |
11735 | if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 | |
11736 | && object_64bit | |
11737 | && ((addressT) (displacement_from_opcode_start - extension | |
4eed87de AM |
11738 | + ((addressT) 1 << 31)) |
11739 | > (((addressT) 2 << 31) - 1))) | |
7b81dfbb AJ |
11740 | { |
11741 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
11742 | _("jump target out of range")); | |
11743 | /* Make us emit 0. */ | |
11744 | displacement_from_opcode_start = extension; | |
11745 | } | |
47926f60 | 11746 | /* Now put displacement after opcode. */ |
252b5132 RH |
11747 | md_number_to_chars ((char *) where_to_put_displacement, |
11748 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 11749 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
11750 | fragP->fr_fix += extension; |
11751 | } | |
11752 | \f | |
7016a5d5 | 11753 | /* Apply a fixup (fixP) to segment data, once it has been determined |
252b5132 RH |
11754 | by our caller that we have all the info we need to fix it up. |
11755 | ||
7016a5d5 TG |
11756 | Parameter valP is the pointer to the value of the bits. |
11757 | ||
252b5132 RH |
11758 | On the 386, immediates, displacements, and data pointers are all in |
11759 | the same (little-endian) format, so we don't need to care about which | |
11760 | we are handling. */ | |
11761 | ||
94f592af | 11762 | void |
7016a5d5 | 11763 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 11764 | { |
94f592af | 11765 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
c6682705 | 11766 | valueT value = *valP; |
252b5132 | 11767 | |
f86103b7 | 11768 | #if !defined (TE_Mach) |
93382f6d AM |
11769 | if (fixP->fx_pcrel) |
11770 | { | |
11771 | switch (fixP->fx_r_type) | |
11772 | { | |
5865bb77 ILT |
11773 | default: |
11774 | break; | |
11775 | ||
d6ab8113 JB |
11776 | case BFD_RELOC_64: |
11777 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
11778 | break; | |
93382f6d | 11779 | case BFD_RELOC_32: |
ae8887b5 | 11780 | case BFD_RELOC_X86_64_32S: |
93382f6d AM |
11781 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
11782 | break; | |
11783 | case BFD_RELOC_16: | |
11784 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
11785 | break; | |
11786 | case BFD_RELOC_8: | |
11787 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
11788 | break; | |
11789 | } | |
11790 | } | |
252b5132 | 11791 | |
a161fe53 | 11792 | if (fixP->fx_addsy != NULL |
31312f95 | 11793 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
d6ab8113 | 11794 | || fixP->fx_r_type == BFD_RELOC_64_PCREL |
31312f95 | 11795 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
d258b828 | 11796 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) |
31312f95 | 11797 | && !use_rela_relocations) |
252b5132 | 11798 | { |
31312f95 AM |
11799 | /* This is a hack. There should be a better way to handle this. |
11800 | This covers for the fact that bfd_install_relocation will | |
11801 | subtract the current location (for partial_inplace, PC relative | |
11802 | relocations); see more below. */ | |
252b5132 | 11803 | #ifndef OBJ_AOUT |
718ddfc0 | 11804 | if (IS_ELF |
252b5132 RH |
11805 | #ifdef TE_PE |
11806 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
11807 | #endif | |
11808 | ) | |
11809 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
11810 | #endif | |
11811 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 11812 | if (IS_ELF) |
252b5132 | 11813 | { |
6539b54b | 11814 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
2f66722d | 11815 | |
6539b54b | 11816 | if ((sym_seg == seg |
2f66722d | 11817 | || (symbol_section_p (fixP->fx_addsy) |
6539b54b | 11818 | && sym_seg != absolute_section)) |
af65af87 | 11819 | && !generic_force_reloc (fixP)) |
2f66722d AM |
11820 | { |
11821 | /* Yes, we add the values in twice. This is because | |
6539b54b AM |
11822 | bfd_install_relocation subtracts them out again. I think |
11823 | bfd_install_relocation is broken, but I don't dare change | |
2f66722d AM |
11824 | it. FIXME. */ |
11825 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
11826 | } | |
252b5132 RH |
11827 | } |
11828 | #endif | |
11829 | #if defined (OBJ_COFF) && defined (TE_PE) | |
977cdf5a NC |
11830 | /* For some reason, the PE format does not store a |
11831 | section address offset for a PC relative symbol. */ | |
11832 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg | |
7be1c489 | 11833 | || S_IS_WEAK (fixP->fx_addsy)) |
252b5132 RH |
11834 | value += md_pcrel_from (fixP); |
11835 | #endif | |
11836 | } | |
fbeb56a4 | 11837 | #if defined (OBJ_COFF) && defined (TE_PE) |
f01c1a09 NC |
11838 | if (fixP->fx_addsy != NULL |
11839 | && S_IS_WEAK (fixP->fx_addsy) | |
11840 | /* PR 16858: Do not modify weak function references. */ | |
11841 | && ! fixP->fx_pcrel) | |
fbeb56a4 | 11842 | { |
296a8689 NC |
11843 | #if !defined (TE_PEP) |
11844 | /* For x86 PE weak function symbols are neither PC-relative | |
11845 | nor do they set S_IS_FUNCTION. So the only reliable way | |
11846 | to detect them is to check the flags of their containing | |
11847 | section. */ | |
11848 | if (S_GET_SEGMENT (fixP->fx_addsy) != NULL | |
11849 | && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE) | |
11850 | ; | |
11851 | else | |
11852 | #endif | |
fbeb56a4 DK |
11853 | value -= S_GET_VALUE (fixP->fx_addsy); |
11854 | } | |
11855 | #endif | |
252b5132 RH |
11856 | |
11857 | /* Fix a few things - the dynamic linker expects certain values here, | |
0234cb7c | 11858 | and we must not disappoint it. */ |
252b5132 | 11859 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 11860 | if (IS_ELF && fixP->fx_addsy) |
47926f60 KH |
11861 | switch (fixP->fx_r_type) |
11862 | { | |
11863 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 11864 | case BFD_RELOC_X86_64_PLT32: |
b9519cfe L |
11865 | /* Make the jump instruction point to the address of the operand. |
11866 | At runtime we merely add the offset to the actual PLT entry. | |
11867 | NB: Subtract the offset size only for jump instructions. */ | |
11868 | if (fixP->fx_pcrel) | |
11869 | value = -4; | |
47926f60 | 11870 | break; |
31312f95 | 11871 | |
13ae64f3 JJ |
11872 | case BFD_RELOC_386_TLS_GD: |
11873 | case BFD_RELOC_386_TLS_LDM: | |
13ae64f3 | 11874 | case BFD_RELOC_386_TLS_IE_32: |
37e55690 JJ |
11875 | case BFD_RELOC_386_TLS_IE: |
11876 | case BFD_RELOC_386_TLS_GOTIE: | |
67a4f2b7 | 11877 | case BFD_RELOC_386_TLS_GOTDESC: |
bffbf940 JJ |
11878 | case BFD_RELOC_X86_64_TLSGD: |
11879 | case BFD_RELOC_X86_64_TLSLD: | |
11880 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 | 11881 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
00f7efb6 JJ |
11882 | value = 0; /* Fully resolved at runtime. No addend. */ |
11883 | /* Fallthrough */ | |
11884 | case BFD_RELOC_386_TLS_LE: | |
11885 | case BFD_RELOC_386_TLS_LDO_32: | |
11886 | case BFD_RELOC_386_TLS_LE_32: | |
11887 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 11888 | case BFD_RELOC_X86_64_DTPOFF64: |
00f7efb6 | 11889 | case BFD_RELOC_X86_64_TPOFF32: |
d6ab8113 | 11890 | case BFD_RELOC_X86_64_TPOFF64: |
00f7efb6 JJ |
11891 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
11892 | break; | |
11893 | ||
67a4f2b7 AO |
11894 | case BFD_RELOC_386_TLS_DESC_CALL: |
11895 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
11896 | value = 0; /* Fully resolved at runtime. No addend. */ | |
11897 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
11898 | fixP->fx_done = 0; | |
11899 | return; | |
11900 | ||
47926f60 KH |
11901 | case BFD_RELOC_VTABLE_INHERIT: |
11902 | case BFD_RELOC_VTABLE_ENTRY: | |
11903 | fixP->fx_done = 0; | |
94f592af | 11904 | return; |
47926f60 KH |
11905 | |
11906 | default: | |
11907 | break; | |
11908 | } | |
11909 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
c6682705 | 11910 | *valP = value; |
f86103b7 | 11911 | #endif /* !defined (TE_Mach) */ |
3e73aa7c | 11912 | |
3e73aa7c | 11913 | /* Are we finished with this relocation now? */ |
c6682705 | 11914 | if (fixP->fx_addsy == NULL) |
3e73aa7c | 11915 | fixP->fx_done = 1; |
fbeb56a4 DK |
11916 | #if defined (OBJ_COFF) && defined (TE_PE) |
11917 | else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) | |
11918 | { | |
11919 | fixP->fx_done = 0; | |
11920 | /* Remember value for tc_gen_reloc. */ | |
11921 | fixP->fx_addnumber = value; | |
11922 | /* Clear out the frag for now. */ | |
11923 | value = 0; | |
11924 | } | |
11925 | #endif | |
3e73aa7c JH |
11926 | else if (use_rela_relocations) |
11927 | { | |
11928 | fixP->fx_no_overflow = 1; | |
062cd5e7 AS |
11929 | /* Remember value for tc_gen_reloc. */ |
11930 | fixP->fx_addnumber = value; | |
3e73aa7c JH |
11931 | value = 0; |
11932 | } | |
f86103b7 | 11933 | |
94f592af | 11934 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 11935 | } |
252b5132 | 11936 | \f |
6d4af3c2 | 11937 | const char * |
499ac353 | 11938 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 11939 | { |
499ac353 NC |
11940 | /* This outputs the LITTLENUMs in REVERSE order; |
11941 | in accord with the bigendian 386. */ | |
11942 | return ieee_md_atof (type, litP, sizeP, FALSE); | |
252b5132 RH |
11943 | } |
11944 | \f | |
2d545b82 | 11945 | static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; |
252b5132 | 11946 | |
252b5132 | 11947 | static char * |
e3bb37b5 | 11948 | output_invalid (int c) |
252b5132 | 11949 | { |
3882b010 | 11950 | if (ISPRINT (c)) |
f9f21a03 L |
11951 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
11952 | "'%c'", c); | |
252b5132 | 11953 | else |
f9f21a03 | 11954 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
2d545b82 | 11955 | "(0x%x)", (unsigned char) c); |
252b5132 RH |
11956 | return output_invalid_buf; |
11957 | } | |
11958 | ||
af6bdddf | 11959 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
11960 | |
11961 | static const reg_entry * | |
4d1bb795 | 11962 | parse_real_register (char *reg_string, char **end_op) |
252b5132 | 11963 | { |
af6bdddf AM |
11964 | char *s = reg_string; |
11965 | char *p; | |
252b5132 RH |
11966 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
11967 | const reg_entry *r; | |
11968 | ||
11969 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
11970 | if (*s == REGISTER_PREFIX) | |
11971 | ++s; | |
11972 | ||
11973 | if (is_space_char (*s)) | |
11974 | ++s; | |
11975 | ||
11976 | p = reg_name_given; | |
af6bdddf | 11977 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
11978 | { |
11979 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
11980 | return (const reg_entry *) NULL; |
11981 | s++; | |
252b5132 RH |
11982 | } |
11983 | ||
6588847e DN |
11984 | /* For naked regs, make sure that we are not dealing with an identifier. |
11985 | This prevents confusing an identifier like `eax_var' with register | |
11986 | `eax'. */ | |
11987 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
11988 | return (const reg_entry *) NULL; | |
11989 | ||
af6bdddf | 11990 | *end_op = s; |
252b5132 RH |
11991 | |
11992 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
11993 | ||
5f47d35b | 11994 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
47926f60 | 11995 | if (r == i386_regtab /* %st is first entry of table */) |
5f47d35b | 11996 | { |
0e0eea78 JB |
11997 | if (!cpu_arch_flags.bitfield.cpu8087 |
11998 | && !cpu_arch_flags.bitfield.cpu287 | |
11999 | && !cpu_arch_flags.bitfield.cpu387) | |
12000 | return (const reg_entry *) NULL; | |
12001 | ||
5f47d35b AM |
12002 | if (is_space_char (*s)) |
12003 | ++s; | |
12004 | if (*s == '(') | |
12005 | { | |
af6bdddf | 12006 | ++s; |
5f47d35b AM |
12007 | if (is_space_char (*s)) |
12008 | ++s; | |
12009 | if (*s >= '0' && *s <= '7') | |
12010 | { | |
db557034 | 12011 | int fpr = *s - '0'; |
af6bdddf | 12012 | ++s; |
5f47d35b AM |
12013 | if (is_space_char (*s)) |
12014 | ++s; | |
12015 | if (*s == ')') | |
12016 | { | |
12017 | *end_op = s + 1; | |
1e9cc1c2 | 12018 | r = (const reg_entry *) hash_find (reg_hash, "st(0)"); |
db557034 AM |
12019 | know (r); |
12020 | return r + fpr; | |
5f47d35b | 12021 | } |
5f47d35b | 12022 | } |
47926f60 | 12023 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
12024 | return (const reg_entry *) NULL; |
12025 | } | |
12026 | } | |
12027 | ||
a60de03c JB |
12028 | if (r == NULL || allow_pseudo_reg) |
12029 | return r; | |
12030 | ||
0dfbf9d7 | 12031 | if (operand_type_all_zero (&r->reg_type)) |
a60de03c JB |
12032 | return (const reg_entry *) NULL; |
12033 | ||
dc821c5f | 12034 | if ((r->reg_type.bitfield.dword |
00cee14f | 12035 | || (r->reg_type.bitfield.class == SReg && r->reg_num > 3) |
4a5c67ed JB |
12036 | || r->reg_type.bitfield.class == RegCR |
12037 | || r->reg_type.bitfield.class == RegDR | |
12038 | || r->reg_type.bitfield.class == RegTR) | |
192dc9c6 JB |
12039 | && !cpu_arch_flags.bitfield.cpui386) |
12040 | return (const reg_entry *) NULL; | |
12041 | ||
3528c362 | 12042 | if (r->reg_type.bitfield.class == RegMMX && !cpu_arch_flags.bitfield.cpummx) |
192dc9c6 JB |
12043 | return (const reg_entry *) NULL; |
12044 | ||
6e041cf4 JB |
12045 | if (!cpu_arch_flags.bitfield.cpuavx512f) |
12046 | { | |
f74a6307 JB |
12047 | if (r->reg_type.bitfield.zmmword |
12048 | || r->reg_type.bitfield.class == RegMask) | |
6e041cf4 | 12049 | return (const reg_entry *) NULL; |
40f12533 | 12050 | |
6e041cf4 JB |
12051 | if (!cpu_arch_flags.bitfield.cpuavx) |
12052 | { | |
12053 | if (r->reg_type.bitfield.ymmword) | |
12054 | return (const reg_entry *) NULL; | |
1848e567 | 12055 | |
6e041cf4 JB |
12056 | if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword) |
12057 | return (const reg_entry *) NULL; | |
12058 | } | |
12059 | } | |
43234a1e | 12060 | |
f74a6307 | 12061 | if (r->reg_type.bitfield.class == RegBND && !cpu_arch_flags.bitfield.cpumpx) |
1adf7f56 JB |
12062 | return (const reg_entry *) NULL; |
12063 | ||
db51cc60 | 12064 | /* Don't allow fake index register unless allow_index_reg isn't 0. */ |
e968fc9b | 12065 | if (!allow_index_reg && r->reg_num == RegIZ) |
db51cc60 L |
12066 | return (const reg_entry *) NULL; |
12067 | ||
1d3f8286 JB |
12068 | /* Upper 16 vector registers are only available with VREX in 64bit |
12069 | mode, and require EVEX encoding. */ | |
12070 | if (r->reg_flags & RegVRex) | |
43234a1e | 12071 | { |
e951d5ca | 12072 | if (!cpu_arch_flags.bitfield.cpuavx512f |
43234a1e L |
12073 | || flag_code != CODE_64BIT) |
12074 | return (const reg_entry *) NULL; | |
1d3f8286 JB |
12075 | |
12076 | i.vec_encoding = vex_encoding_evex; | |
43234a1e L |
12077 | } |
12078 | ||
4787f4a5 | 12079 | if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword) |
4a5c67ed | 12080 | && (!cpu_arch_flags.bitfield.cpulm || r->reg_type.bitfield.class != RegCR) |
1ae00879 | 12081 | && flag_code != CODE_64BIT) |
20f0a1fc | 12082 | return (const reg_entry *) NULL; |
1ae00879 | 12083 | |
00cee14f JB |
12084 | if (r->reg_type.bitfield.class == SReg && r->reg_num == RegFlat |
12085 | && !intel_syntax) | |
b7240065 JB |
12086 | return (const reg_entry *) NULL; |
12087 | ||
252b5132 RH |
12088 | return r; |
12089 | } | |
4d1bb795 JB |
12090 | |
12091 | /* REG_STRING starts *before* REGISTER_PREFIX. */ | |
12092 | ||
12093 | static const reg_entry * | |
12094 | parse_register (char *reg_string, char **end_op) | |
12095 | { | |
12096 | const reg_entry *r; | |
12097 | ||
12098 | if (*reg_string == REGISTER_PREFIX || allow_naked_reg) | |
12099 | r = parse_real_register (reg_string, end_op); | |
12100 | else | |
12101 | r = NULL; | |
12102 | if (!r) | |
12103 | { | |
12104 | char *save = input_line_pointer; | |
12105 | char c; | |
12106 | symbolS *symbolP; | |
12107 | ||
12108 | input_line_pointer = reg_string; | |
d02603dc | 12109 | c = get_symbol_name (®_string); |
4d1bb795 JB |
12110 | symbolP = symbol_find (reg_string); |
12111 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) | |
12112 | { | |
12113 | const expressionS *e = symbol_get_value_expression (symbolP); | |
12114 | ||
0398aac5 | 12115 | know (e->X_op == O_register); |
4eed87de | 12116 | know (e->X_add_number >= 0 |
c3fe08fa | 12117 | && (valueT) e->X_add_number < i386_regtab_size); |
4d1bb795 | 12118 | r = i386_regtab + e->X_add_number; |
d3bb6b49 | 12119 | if ((r->reg_flags & RegVRex)) |
86fa6981 | 12120 | i.vec_encoding = vex_encoding_evex; |
4d1bb795 JB |
12121 | *end_op = input_line_pointer; |
12122 | } | |
12123 | *input_line_pointer = c; | |
12124 | input_line_pointer = save; | |
12125 | } | |
12126 | return r; | |
12127 | } | |
12128 | ||
12129 | int | |
12130 | i386_parse_name (char *name, expressionS *e, char *nextcharP) | |
12131 | { | |
12132 | const reg_entry *r; | |
12133 | char *end = input_line_pointer; | |
12134 | ||
12135 | *end = *nextcharP; | |
12136 | r = parse_register (name, &input_line_pointer); | |
12137 | if (r && end <= input_line_pointer) | |
12138 | { | |
12139 | *nextcharP = *input_line_pointer; | |
12140 | *input_line_pointer = 0; | |
12141 | e->X_op = O_register; | |
12142 | e->X_add_number = r - i386_regtab; | |
12143 | return 1; | |
12144 | } | |
12145 | input_line_pointer = end; | |
12146 | *end = 0; | |
ee86248c | 12147 | return intel_syntax ? i386_intel_parse_name (name, e) : 0; |
4d1bb795 JB |
12148 | } |
12149 | ||
12150 | void | |
12151 | md_operand (expressionS *e) | |
12152 | { | |
ee86248c JB |
12153 | char *end; |
12154 | const reg_entry *r; | |
4d1bb795 | 12155 | |
ee86248c JB |
12156 | switch (*input_line_pointer) |
12157 | { | |
12158 | case REGISTER_PREFIX: | |
12159 | r = parse_real_register (input_line_pointer, &end); | |
4d1bb795 JB |
12160 | if (r) |
12161 | { | |
12162 | e->X_op = O_register; | |
12163 | e->X_add_number = r - i386_regtab; | |
12164 | input_line_pointer = end; | |
12165 | } | |
ee86248c JB |
12166 | break; |
12167 | ||
12168 | case '[': | |
9c2799c2 | 12169 | gas_assert (intel_syntax); |
ee86248c JB |
12170 | end = input_line_pointer++; |
12171 | expression (e); | |
12172 | if (*input_line_pointer == ']') | |
12173 | { | |
12174 | ++input_line_pointer; | |
12175 | e->X_op_symbol = make_expr_symbol (e); | |
12176 | e->X_add_symbol = NULL; | |
12177 | e->X_add_number = 0; | |
12178 | e->X_op = O_index; | |
12179 | } | |
12180 | else | |
12181 | { | |
12182 | e->X_op = O_absent; | |
12183 | input_line_pointer = end; | |
12184 | } | |
12185 | break; | |
4d1bb795 JB |
12186 | } |
12187 | } | |
12188 | ||
252b5132 | 12189 | \f |
4cc782b5 | 12190 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
b6f8c7c4 | 12191 | const char *md_shortopts = "kVQ:sqnO::"; |
252b5132 | 12192 | #else |
b6f8c7c4 | 12193 | const char *md_shortopts = "qnO::"; |
252b5132 | 12194 | #endif |
6e0b89ee | 12195 | |
3e73aa7c | 12196 | #define OPTION_32 (OPTION_MD_BASE + 0) |
b3b91714 AM |
12197 | #define OPTION_64 (OPTION_MD_BASE + 1) |
12198 | #define OPTION_DIVIDE (OPTION_MD_BASE + 2) | |
9103f4f4 L |
12199 | #define OPTION_MARCH (OPTION_MD_BASE + 3) |
12200 | #define OPTION_MTUNE (OPTION_MD_BASE + 4) | |
1efbbeb4 L |
12201 | #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) |
12202 | #define OPTION_MSYNTAX (OPTION_MD_BASE + 6) | |
12203 | #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) | |
12204 | #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) | |
bd5dea88 | 12205 | #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9) |
c0f3af97 | 12206 | #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10) |
daf50ae7 | 12207 | #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11) |
7bab8ab5 JB |
12208 | #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12) |
12209 | #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13) | |
12210 | #define OPTION_X32 (OPTION_MD_BASE + 14) | |
7e8b059b | 12211 | #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15) |
43234a1e L |
12212 | #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16) |
12213 | #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17) | |
167ad85b | 12214 | #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18) |
d1982f93 | 12215 | #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19) |
d3d3c6db | 12216 | #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20) |
8dcea932 | 12217 | #define OPTION_MSHARED (OPTION_MD_BASE + 21) |
5db04b09 L |
12218 | #define OPTION_MAMD64 (OPTION_MD_BASE + 22) |
12219 | #define OPTION_MINTEL64 (OPTION_MD_BASE + 23) | |
e4e00185 | 12220 | #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24) |
b4a3a7b4 | 12221 | #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25) |
03751133 | 12222 | #define OPTION_MVEXWIG (OPTION_MD_BASE + 26) |
e379e5f3 L |
12223 | #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27) |
12224 | #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28) | |
12225 | #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29) | |
76cf450b | 12226 | #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30) |
b3b91714 | 12227 | |
99ad8390 NC |
12228 | struct option md_longopts[] = |
12229 | { | |
3e73aa7c | 12230 | {"32", no_argument, NULL, OPTION_32}, |
321098a5 | 12231 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 12232 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c | 12233 | {"64", no_argument, NULL, OPTION_64}, |
351f65ca L |
12234 | #endif |
12235 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
570561f7 | 12236 | {"x32", no_argument, NULL, OPTION_X32}, |
8dcea932 | 12237 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
b4a3a7b4 | 12238 | {"mx86-used-note", required_argument, NULL, OPTION_X86_USED_NOTE}, |
6e0b89ee | 12239 | #endif |
b3b91714 | 12240 | {"divide", no_argument, NULL, OPTION_DIVIDE}, |
9103f4f4 L |
12241 | {"march", required_argument, NULL, OPTION_MARCH}, |
12242 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1efbbeb4 L |
12243 | {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, |
12244 | {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, | |
12245 | {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, | |
12246 | {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, | |
c0f3af97 | 12247 | {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX}, |
daf50ae7 | 12248 | {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK}, |
7bab8ab5 | 12249 | {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK}, |
539f890d | 12250 | {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR}, |
03751133 | 12251 | {"mvexwig", required_argument, NULL, OPTION_MVEXWIG}, |
7e8b059b | 12252 | {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX}, |
43234a1e L |
12253 | {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG}, |
12254 | {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG}, | |
167ad85b TG |
12255 | # if defined (TE_PE) || defined (TE_PEP) |
12256 | {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ}, | |
12257 | #endif | |
d1982f93 | 12258 | {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX}, |
e4e00185 | 12259 | {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD}, |
0cb4071e | 12260 | {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS}, |
d3d3c6db | 12261 | {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG}, |
e379e5f3 L |
12262 | {"malign-branch-boundary", required_argument, NULL, OPTION_MALIGN_BRANCH_BOUNDARY}, |
12263 | {"malign-branch-prefix-size", required_argument, NULL, OPTION_MALIGN_BRANCH_PREFIX_SIZE}, | |
12264 | {"malign-branch", required_argument, NULL, OPTION_MALIGN_BRANCH}, | |
76cf450b | 12265 | {"mbranches-within-32B-boundaries", no_argument, NULL, OPTION_MBRANCHES_WITH_32B_BOUNDARIES}, |
5db04b09 L |
12266 | {"mamd64", no_argument, NULL, OPTION_MAMD64}, |
12267 | {"mintel64", no_argument, NULL, OPTION_MINTEL64}, | |
252b5132 RH |
12268 | {NULL, no_argument, NULL, 0} |
12269 | }; | |
12270 | size_t md_longopts_size = sizeof (md_longopts); | |
12271 | ||
12272 | int | |
17b9d67d | 12273 | md_parse_option (int c, const char *arg) |
252b5132 | 12274 | { |
91d6fa6a | 12275 | unsigned int j; |
e379e5f3 | 12276 | char *arch, *next, *saved, *type; |
9103f4f4 | 12277 | |
252b5132 RH |
12278 | switch (c) |
12279 | { | |
12b55ccc L |
12280 | case 'n': |
12281 | optimize_align_code = 0; | |
12282 | break; | |
12283 | ||
a38cf1db AM |
12284 | case 'q': |
12285 | quiet_warnings = 1; | |
252b5132 RH |
12286 | break; |
12287 | ||
12288 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
12289 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
12290 | should be emitted or not. FIXME: Not implemented. */ | |
12291 | case 'Q': | |
d4693039 JB |
12292 | if ((arg[0] != 'y' && arg[0] != 'n') || arg[1]) |
12293 | return 0; | |
252b5132 RH |
12294 | break; |
12295 | ||
12296 | /* -V: SVR4 argument to print version ID. */ | |
12297 | case 'V': | |
12298 | print_version_id (); | |
12299 | break; | |
12300 | ||
a38cf1db AM |
12301 | /* -k: Ignore for FreeBSD compatibility. */ |
12302 | case 'k': | |
252b5132 | 12303 | break; |
4cc782b5 ILT |
12304 | |
12305 | case 's': | |
12306 | /* -s: On i386 Solaris, this tells the native assembler to use | |
29b0f896 | 12307 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
4cc782b5 | 12308 | break; |
8dcea932 L |
12309 | |
12310 | case OPTION_MSHARED: | |
12311 | shared = 1; | |
12312 | break; | |
b4a3a7b4 L |
12313 | |
12314 | case OPTION_X86_USED_NOTE: | |
12315 | if (strcasecmp (arg, "yes") == 0) | |
12316 | x86_used_note = 1; | |
12317 | else if (strcasecmp (arg, "no") == 0) | |
12318 | x86_used_note = 0; | |
12319 | else | |
12320 | as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg); | |
12321 | break; | |
12322 | ||
12323 | ||
99ad8390 | 12324 | #endif |
321098a5 | 12325 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 12326 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c JH |
12327 | case OPTION_64: |
12328 | { | |
12329 | const char **list, **l; | |
12330 | ||
3e73aa7c JH |
12331 | list = bfd_target_list (); |
12332 | for (l = list; *l != NULL; l++) | |
8620418b | 12333 | if (CONST_STRNEQ (*l, "elf64-x86-64") |
99ad8390 NC |
12334 | || strcmp (*l, "coff-x86-64") == 0 |
12335 | || strcmp (*l, "pe-x86-64") == 0 | |
d382c579 TG |
12336 | || strcmp (*l, "pei-x86-64") == 0 |
12337 | || strcmp (*l, "mach-o-x86-64") == 0) | |
6e0b89ee AM |
12338 | { |
12339 | default_arch = "x86_64"; | |
12340 | break; | |
12341 | } | |
3e73aa7c | 12342 | if (*l == NULL) |
2b5d6a91 | 12343 | as_fatal (_("no compiled in support for x86_64")); |
3e73aa7c JH |
12344 | free (list); |
12345 | } | |
12346 | break; | |
12347 | #endif | |
252b5132 | 12348 | |
351f65ca | 12349 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
570561f7 | 12350 | case OPTION_X32: |
351f65ca L |
12351 | if (IS_ELF) |
12352 | { | |
12353 | const char **list, **l; | |
12354 | ||
12355 | list = bfd_target_list (); | |
12356 | for (l = list; *l != NULL; l++) | |
12357 | if (CONST_STRNEQ (*l, "elf32-x86-64")) | |
12358 | { | |
12359 | default_arch = "x86_64:32"; | |
12360 | break; | |
12361 | } | |
12362 | if (*l == NULL) | |
2b5d6a91 | 12363 | as_fatal (_("no compiled in support for 32bit x86_64")); |
351f65ca L |
12364 | free (list); |
12365 | } | |
12366 | else | |
12367 | as_fatal (_("32bit x86_64 is only supported for ELF")); | |
12368 | break; | |
12369 | #endif | |
12370 | ||
6e0b89ee AM |
12371 | case OPTION_32: |
12372 | default_arch = "i386"; | |
12373 | break; | |
12374 | ||
b3b91714 AM |
12375 | case OPTION_DIVIDE: |
12376 | #ifdef SVR4_COMMENT_CHARS | |
12377 | { | |
12378 | char *n, *t; | |
12379 | const char *s; | |
12380 | ||
add39d23 | 12381 | n = XNEWVEC (char, strlen (i386_comment_chars) + 1); |
b3b91714 AM |
12382 | t = n; |
12383 | for (s = i386_comment_chars; *s != '\0'; s++) | |
12384 | if (*s != '/') | |
12385 | *t++ = *s; | |
12386 | *t = '\0'; | |
12387 | i386_comment_chars = n; | |
12388 | } | |
12389 | #endif | |
12390 | break; | |
12391 | ||
9103f4f4 | 12392 | case OPTION_MARCH: |
293f5f65 L |
12393 | saved = xstrdup (arg); |
12394 | arch = saved; | |
12395 | /* Allow -march=+nosse. */ | |
12396 | if (*arch == '+') | |
12397 | arch++; | |
6305a203 | 12398 | do |
9103f4f4 | 12399 | { |
6305a203 | 12400 | if (*arch == '.') |
2b5d6a91 | 12401 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
12402 | next = strchr (arch, '+'); |
12403 | if (next) | |
12404 | *next++ = '\0'; | |
91d6fa6a | 12405 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 12406 | { |
91d6fa6a | 12407 | if (strcmp (arch, cpu_arch [j].name) == 0) |
ccc9c027 | 12408 | { |
6305a203 | 12409 | /* Processor. */ |
1ded5609 JB |
12410 | if (! cpu_arch[j].flags.bitfield.cpui386) |
12411 | continue; | |
12412 | ||
91d6fa6a | 12413 | cpu_arch_name = cpu_arch[j].name; |
6305a203 | 12414 | cpu_sub_arch_name = NULL; |
91d6fa6a NC |
12415 | cpu_arch_flags = cpu_arch[j].flags; |
12416 | cpu_arch_isa = cpu_arch[j].type; | |
12417 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
6305a203 L |
12418 | if (!cpu_arch_tune_set) |
12419 | { | |
12420 | cpu_arch_tune = cpu_arch_isa; | |
12421 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
12422 | } | |
12423 | break; | |
12424 | } | |
91d6fa6a NC |
12425 | else if (*cpu_arch [j].name == '.' |
12426 | && strcmp (arch, cpu_arch [j].name + 1) == 0) | |
6305a203 | 12427 | { |
33eaf5de | 12428 | /* ISA extension. */ |
6305a203 | 12429 | i386_cpu_flags flags; |
309d3373 | 12430 | |
293f5f65 L |
12431 | flags = cpu_flags_or (cpu_arch_flags, |
12432 | cpu_arch[j].flags); | |
81486035 | 12433 | |
5b64d091 | 12434 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
6305a203 L |
12435 | { |
12436 | if (cpu_sub_arch_name) | |
12437 | { | |
12438 | char *name = cpu_sub_arch_name; | |
12439 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 12440 | cpu_arch[j].name, |
1bf57e9f | 12441 | (const char *) NULL); |
6305a203 L |
12442 | free (name); |
12443 | } | |
12444 | else | |
91d6fa6a | 12445 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
6305a203 | 12446 | cpu_arch_flags = flags; |
a586129e | 12447 | cpu_arch_isa_flags = flags; |
6305a203 | 12448 | } |
0089dace L |
12449 | else |
12450 | cpu_arch_isa_flags | |
12451 | = cpu_flags_or (cpu_arch_isa_flags, | |
12452 | cpu_arch[j].flags); | |
6305a203 | 12453 | break; |
ccc9c027 | 12454 | } |
9103f4f4 | 12455 | } |
6305a203 | 12456 | |
293f5f65 L |
12457 | if (j >= ARRAY_SIZE (cpu_arch)) |
12458 | { | |
33eaf5de | 12459 | /* Disable an ISA extension. */ |
293f5f65 L |
12460 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
12461 | if (strcmp (arch, cpu_noarch [j].name) == 0) | |
12462 | { | |
12463 | i386_cpu_flags flags; | |
12464 | ||
12465 | flags = cpu_flags_and_not (cpu_arch_flags, | |
12466 | cpu_noarch[j].flags); | |
12467 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
12468 | { | |
12469 | if (cpu_sub_arch_name) | |
12470 | { | |
12471 | char *name = cpu_sub_arch_name; | |
12472 | cpu_sub_arch_name = concat (arch, | |
12473 | (const char *) NULL); | |
12474 | free (name); | |
12475 | } | |
12476 | else | |
12477 | cpu_sub_arch_name = xstrdup (arch); | |
12478 | cpu_arch_flags = flags; | |
12479 | cpu_arch_isa_flags = flags; | |
12480 | } | |
12481 | break; | |
12482 | } | |
12483 | ||
12484 | if (j >= ARRAY_SIZE (cpu_noarch)) | |
12485 | j = ARRAY_SIZE (cpu_arch); | |
12486 | } | |
12487 | ||
91d6fa6a | 12488 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 12489 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
12490 | |
12491 | arch = next; | |
9103f4f4 | 12492 | } |
293f5f65 L |
12493 | while (next != NULL); |
12494 | free (saved); | |
9103f4f4 L |
12495 | break; |
12496 | ||
12497 | case OPTION_MTUNE: | |
12498 | if (*arg == '.') | |
2b5d6a91 | 12499 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
91d6fa6a | 12500 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 12501 | { |
91d6fa6a | 12502 | if (strcmp (arg, cpu_arch [j].name) == 0) |
9103f4f4 | 12503 | { |
ccc9c027 | 12504 | cpu_arch_tune_set = 1; |
91d6fa6a NC |
12505 | cpu_arch_tune = cpu_arch [j].type; |
12506 | cpu_arch_tune_flags = cpu_arch[j].flags; | |
9103f4f4 L |
12507 | break; |
12508 | } | |
12509 | } | |
91d6fa6a | 12510 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 12511 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
9103f4f4 L |
12512 | break; |
12513 | ||
1efbbeb4 L |
12514 | case OPTION_MMNEMONIC: |
12515 | if (strcasecmp (arg, "att") == 0) | |
12516 | intel_mnemonic = 0; | |
12517 | else if (strcasecmp (arg, "intel") == 0) | |
12518 | intel_mnemonic = 1; | |
12519 | else | |
2b5d6a91 | 12520 | as_fatal (_("invalid -mmnemonic= option: `%s'"), arg); |
1efbbeb4 L |
12521 | break; |
12522 | ||
12523 | case OPTION_MSYNTAX: | |
12524 | if (strcasecmp (arg, "att") == 0) | |
12525 | intel_syntax = 0; | |
12526 | else if (strcasecmp (arg, "intel") == 0) | |
12527 | intel_syntax = 1; | |
12528 | else | |
2b5d6a91 | 12529 | as_fatal (_("invalid -msyntax= option: `%s'"), arg); |
1efbbeb4 L |
12530 | break; |
12531 | ||
12532 | case OPTION_MINDEX_REG: | |
12533 | allow_index_reg = 1; | |
12534 | break; | |
12535 | ||
12536 | case OPTION_MNAKED_REG: | |
12537 | allow_naked_reg = 1; | |
12538 | break; | |
12539 | ||
c0f3af97 L |
12540 | case OPTION_MSSE2AVX: |
12541 | sse2avx = 1; | |
12542 | break; | |
12543 | ||
daf50ae7 L |
12544 | case OPTION_MSSE_CHECK: |
12545 | if (strcasecmp (arg, "error") == 0) | |
7bab8ab5 | 12546 | sse_check = check_error; |
daf50ae7 | 12547 | else if (strcasecmp (arg, "warning") == 0) |
7bab8ab5 | 12548 | sse_check = check_warning; |
daf50ae7 | 12549 | else if (strcasecmp (arg, "none") == 0) |
7bab8ab5 | 12550 | sse_check = check_none; |
daf50ae7 | 12551 | else |
2b5d6a91 | 12552 | as_fatal (_("invalid -msse-check= option: `%s'"), arg); |
daf50ae7 L |
12553 | break; |
12554 | ||
7bab8ab5 JB |
12555 | case OPTION_MOPERAND_CHECK: |
12556 | if (strcasecmp (arg, "error") == 0) | |
12557 | operand_check = check_error; | |
12558 | else if (strcasecmp (arg, "warning") == 0) | |
12559 | operand_check = check_warning; | |
12560 | else if (strcasecmp (arg, "none") == 0) | |
12561 | operand_check = check_none; | |
12562 | else | |
12563 | as_fatal (_("invalid -moperand-check= option: `%s'"), arg); | |
12564 | break; | |
12565 | ||
539f890d L |
12566 | case OPTION_MAVXSCALAR: |
12567 | if (strcasecmp (arg, "128") == 0) | |
12568 | avxscalar = vex128; | |
12569 | else if (strcasecmp (arg, "256") == 0) | |
12570 | avxscalar = vex256; | |
12571 | else | |
2b5d6a91 | 12572 | as_fatal (_("invalid -mavxscalar= option: `%s'"), arg); |
539f890d L |
12573 | break; |
12574 | ||
03751133 L |
12575 | case OPTION_MVEXWIG: |
12576 | if (strcmp (arg, "0") == 0) | |
40c9c8de | 12577 | vexwig = vexw0; |
03751133 | 12578 | else if (strcmp (arg, "1") == 0) |
40c9c8de | 12579 | vexwig = vexw1; |
03751133 L |
12580 | else |
12581 | as_fatal (_("invalid -mvexwig= option: `%s'"), arg); | |
12582 | break; | |
12583 | ||
7e8b059b L |
12584 | case OPTION_MADD_BND_PREFIX: |
12585 | add_bnd_prefix = 1; | |
12586 | break; | |
12587 | ||
43234a1e L |
12588 | case OPTION_MEVEXLIG: |
12589 | if (strcmp (arg, "128") == 0) | |
12590 | evexlig = evexl128; | |
12591 | else if (strcmp (arg, "256") == 0) | |
12592 | evexlig = evexl256; | |
12593 | else if (strcmp (arg, "512") == 0) | |
12594 | evexlig = evexl512; | |
12595 | else | |
12596 | as_fatal (_("invalid -mevexlig= option: `%s'"), arg); | |
12597 | break; | |
12598 | ||
d3d3c6db IT |
12599 | case OPTION_MEVEXRCIG: |
12600 | if (strcmp (arg, "rne") == 0) | |
12601 | evexrcig = rne; | |
12602 | else if (strcmp (arg, "rd") == 0) | |
12603 | evexrcig = rd; | |
12604 | else if (strcmp (arg, "ru") == 0) | |
12605 | evexrcig = ru; | |
12606 | else if (strcmp (arg, "rz") == 0) | |
12607 | evexrcig = rz; | |
12608 | else | |
12609 | as_fatal (_("invalid -mevexrcig= option: `%s'"), arg); | |
12610 | break; | |
12611 | ||
43234a1e L |
12612 | case OPTION_MEVEXWIG: |
12613 | if (strcmp (arg, "0") == 0) | |
12614 | evexwig = evexw0; | |
12615 | else if (strcmp (arg, "1") == 0) | |
12616 | evexwig = evexw1; | |
12617 | else | |
12618 | as_fatal (_("invalid -mevexwig= option: `%s'"), arg); | |
12619 | break; | |
12620 | ||
167ad85b TG |
12621 | # if defined (TE_PE) || defined (TE_PEP) |
12622 | case OPTION_MBIG_OBJ: | |
12623 | use_big_obj = 1; | |
12624 | break; | |
12625 | #endif | |
12626 | ||
d1982f93 | 12627 | case OPTION_MOMIT_LOCK_PREFIX: |
d022bddd IT |
12628 | if (strcasecmp (arg, "yes") == 0) |
12629 | omit_lock_prefix = 1; | |
12630 | else if (strcasecmp (arg, "no") == 0) | |
12631 | omit_lock_prefix = 0; | |
12632 | else | |
12633 | as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg); | |
12634 | break; | |
12635 | ||
e4e00185 AS |
12636 | case OPTION_MFENCE_AS_LOCK_ADD: |
12637 | if (strcasecmp (arg, "yes") == 0) | |
12638 | avoid_fence = 1; | |
12639 | else if (strcasecmp (arg, "no") == 0) | |
12640 | avoid_fence = 0; | |
12641 | else | |
12642 | as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg); | |
12643 | break; | |
12644 | ||
0cb4071e L |
12645 | case OPTION_MRELAX_RELOCATIONS: |
12646 | if (strcasecmp (arg, "yes") == 0) | |
12647 | generate_relax_relocations = 1; | |
12648 | else if (strcasecmp (arg, "no") == 0) | |
12649 | generate_relax_relocations = 0; | |
12650 | else | |
12651 | as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg); | |
12652 | break; | |
12653 | ||
e379e5f3 L |
12654 | case OPTION_MALIGN_BRANCH_BOUNDARY: |
12655 | { | |
12656 | char *end; | |
12657 | long int align = strtoul (arg, &end, 0); | |
12658 | if (*end == '\0') | |
12659 | { | |
12660 | if (align == 0) | |
12661 | { | |
12662 | align_branch_power = 0; | |
12663 | break; | |
12664 | } | |
12665 | else if (align >= 16) | |
12666 | { | |
12667 | int align_power; | |
12668 | for (align_power = 0; | |
12669 | (align & 1) == 0; | |
12670 | align >>= 1, align_power++) | |
12671 | continue; | |
12672 | /* Limit alignment power to 31. */ | |
12673 | if (align == 1 && align_power < 32) | |
12674 | { | |
12675 | align_branch_power = align_power; | |
12676 | break; | |
12677 | } | |
12678 | } | |
12679 | } | |
12680 | as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg); | |
12681 | } | |
12682 | break; | |
12683 | ||
12684 | case OPTION_MALIGN_BRANCH_PREFIX_SIZE: | |
12685 | { | |
12686 | char *end; | |
12687 | int align = strtoul (arg, &end, 0); | |
12688 | /* Some processors only support 5 prefixes. */ | |
12689 | if (*end == '\0' && align >= 0 && align < 6) | |
12690 | { | |
12691 | align_branch_prefix_size = align; | |
12692 | break; | |
12693 | } | |
12694 | as_fatal (_("invalid -malign-branch-prefix-size= value: %s"), | |
12695 | arg); | |
12696 | } | |
12697 | break; | |
12698 | ||
12699 | case OPTION_MALIGN_BRANCH: | |
12700 | align_branch = 0; | |
12701 | saved = xstrdup (arg); | |
12702 | type = saved; | |
12703 | do | |
12704 | { | |
12705 | next = strchr (type, '+'); | |
12706 | if (next) | |
12707 | *next++ = '\0'; | |
12708 | if (strcasecmp (type, "jcc") == 0) | |
12709 | align_branch |= align_branch_jcc_bit; | |
12710 | else if (strcasecmp (type, "fused") == 0) | |
12711 | align_branch |= align_branch_fused_bit; | |
12712 | else if (strcasecmp (type, "jmp") == 0) | |
12713 | align_branch |= align_branch_jmp_bit; | |
12714 | else if (strcasecmp (type, "call") == 0) | |
12715 | align_branch |= align_branch_call_bit; | |
12716 | else if (strcasecmp (type, "ret") == 0) | |
12717 | align_branch |= align_branch_ret_bit; | |
12718 | else if (strcasecmp (type, "indirect") == 0) | |
12719 | align_branch |= align_branch_indirect_bit; | |
12720 | else | |
12721 | as_fatal (_("invalid -malign-branch= option: `%s'"), arg); | |
12722 | type = next; | |
12723 | } | |
12724 | while (next != NULL); | |
12725 | free (saved); | |
12726 | break; | |
12727 | ||
76cf450b L |
12728 | case OPTION_MBRANCHES_WITH_32B_BOUNDARIES: |
12729 | align_branch_power = 5; | |
12730 | align_branch_prefix_size = 5; | |
12731 | align_branch = (align_branch_jcc_bit | |
12732 | | align_branch_fused_bit | |
12733 | | align_branch_jmp_bit); | |
12734 | break; | |
12735 | ||
5db04b09 | 12736 | case OPTION_MAMD64: |
4b5aaf5f | 12737 | isa64 = amd64; |
5db04b09 L |
12738 | break; |
12739 | ||
12740 | case OPTION_MINTEL64: | |
4b5aaf5f | 12741 | isa64 = intel64; |
5db04b09 L |
12742 | break; |
12743 | ||
b6f8c7c4 L |
12744 | case 'O': |
12745 | if (arg == NULL) | |
12746 | { | |
12747 | optimize = 1; | |
12748 | /* Turn off -Os. */ | |
12749 | optimize_for_space = 0; | |
12750 | } | |
12751 | else if (*arg == 's') | |
12752 | { | |
12753 | optimize_for_space = 1; | |
12754 | /* Turn on all encoding optimizations. */ | |
41fd2579 | 12755 | optimize = INT_MAX; |
b6f8c7c4 L |
12756 | } |
12757 | else | |
12758 | { | |
12759 | optimize = atoi (arg); | |
12760 | /* Turn off -Os. */ | |
12761 | optimize_for_space = 0; | |
12762 | } | |
12763 | break; | |
12764 | ||
252b5132 RH |
12765 | default: |
12766 | return 0; | |
12767 | } | |
12768 | return 1; | |
12769 | } | |
12770 | ||
8a2c8fef L |
12771 | #define MESSAGE_TEMPLATE \ |
12772 | " " | |
12773 | ||
293f5f65 L |
12774 | static char * |
12775 | output_message (FILE *stream, char *p, char *message, char *start, | |
12776 | int *left_p, const char *name, int len) | |
12777 | { | |
12778 | int size = sizeof (MESSAGE_TEMPLATE); | |
12779 | int left = *left_p; | |
12780 | ||
12781 | /* Reserve 2 spaces for ", " or ",\0" */ | |
12782 | left -= len + 2; | |
12783 | ||
12784 | /* Check if there is any room. */ | |
12785 | if (left >= 0) | |
12786 | { | |
12787 | if (p != start) | |
12788 | { | |
12789 | *p++ = ','; | |
12790 | *p++ = ' '; | |
12791 | } | |
12792 | p = mempcpy (p, name, len); | |
12793 | } | |
12794 | else | |
12795 | { | |
12796 | /* Output the current message now and start a new one. */ | |
12797 | *p++ = ','; | |
12798 | *p = '\0'; | |
12799 | fprintf (stream, "%s\n", message); | |
12800 | p = start; | |
12801 | left = size - (start - message) - len - 2; | |
12802 | ||
12803 | gas_assert (left >= 0); | |
12804 | ||
12805 | p = mempcpy (p, name, len); | |
12806 | } | |
12807 | ||
12808 | *left_p = left; | |
12809 | return p; | |
12810 | } | |
12811 | ||
8a2c8fef | 12812 | static void |
1ded5609 | 12813 | show_arch (FILE *stream, int ext, int check) |
8a2c8fef L |
12814 | { |
12815 | static char message[] = MESSAGE_TEMPLATE; | |
12816 | char *start = message + 27; | |
12817 | char *p; | |
12818 | int size = sizeof (MESSAGE_TEMPLATE); | |
12819 | int left; | |
12820 | const char *name; | |
12821 | int len; | |
12822 | unsigned int j; | |
12823 | ||
12824 | p = start; | |
12825 | left = size - (start - message); | |
12826 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) | |
12827 | { | |
12828 | /* Should it be skipped? */ | |
12829 | if (cpu_arch [j].skip) | |
12830 | continue; | |
12831 | ||
12832 | name = cpu_arch [j].name; | |
12833 | len = cpu_arch [j].len; | |
12834 | if (*name == '.') | |
12835 | { | |
12836 | /* It is an extension. Skip if we aren't asked to show it. */ | |
12837 | if (ext) | |
12838 | { | |
12839 | name++; | |
12840 | len--; | |
12841 | } | |
12842 | else | |
12843 | continue; | |
12844 | } | |
12845 | else if (ext) | |
12846 | { | |
12847 | /* It is an processor. Skip if we show only extension. */ | |
12848 | continue; | |
12849 | } | |
1ded5609 JB |
12850 | else if (check && ! cpu_arch[j].flags.bitfield.cpui386) |
12851 | { | |
12852 | /* It is an impossible processor - skip. */ | |
12853 | continue; | |
12854 | } | |
8a2c8fef | 12855 | |
293f5f65 | 12856 | p = output_message (stream, p, message, start, &left, name, len); |
8a2c8fef L |
12857 | } |
12858 | ||
293f5f65 L |
12859 | /* Display disabled extensions. */ |
12860 | if (ext) | |
12861 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) | |
12862 | { | |
12863 | name = cpu_noarch [j].name; | |
12864 | len = cpu_noarch [j].len; | |
12865 | p = output_message (stream, p, message, start, &left, name, | |
12866 | len); | |
12867 | } | |
12868 | ||
8a2c8fef L |
12869 | *p = '\0'; |
12870 | fprintf (stream, "%s\n", message); | |
12871 | } | |
12872 | ||
252b5132 | 12873 | void |
8a2c8fef | 12874 | md_show_usage (FILE *stream) |
252b5132 | 12875 | { |
4cc782b5 ILT |
12876 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
12877 | fprintf (stream, _("\ | |
d4693039 | 12878 | -Qy, -Qn ignored\n\ |
a38cf1db | 12879 | -V print assembler version number\n\ |
b3b91714 AM |
12880 | -k ignored\n")); |
12881 | #endif | |
12882 | fprintf (stream, _("\ | |
12b55ccc | 12883 | -n Do not optimize code alignment\n\ |
b3b91714 AM |
12884 | -q quieten some warnings\n")); |
12885 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
12886 | fprintf (stream, _("\ | |
a38cf1db | 12887 | -s ignored\n")); |
b3b91714 | 12888 | #endif |
d7f449c0 L |
12889 | #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
12890 | || defined (TE_PE) || defined (TE_PEP)) | |
751d281c | 12891 | fprintf (stream, _("\ |
570561f7 | 12892 | --32/--64/--x32 generate 32bit/64bit/x32 code\n")); |
751d281c | 12893 | #endif |
b3b91714 AM |
12894 | #ifdef SVR4_COMMENT_CHARS |
12895 | fprintf (stream, _("\ | |
12896 | --divide do not treat `/' as a comment character\n")); | |
a38cf1db AM |
12897 | #else |
12898 | fprintf (stream, _("\ | |
b3b91714 | 12899 | --divide ignored\n")); |
4cc782b5 | 12900 | #endif |
9103f4f4 | 12901 | fprintf (stream, _("\ |
6305a203 | 12902 | -march=CPU[,+EXTENSION...]\n\ |
8a2c8fef | 12903 | generate code for CPU and EXTENSION, CPU is one of:\n")); |
1ded5609 | 12904 | show_arch (stream, 0, 1); |
8a2c8fef L |
12905 | fprintf (stream, _("\ |
12906 | EXTENSION is combination of:\n")); | |
1ded5609 | 12907 | show_arch (stream, 1, 0); |
6305a203 | 12908 | fprintf (stream, _("\ |
8a2c8fef | 12909 | -mtune=CPU optimize for CPU, CPU is one of:\n")); |
1ded5609 | 12910 | show_arch (stream, 0, 0); |
ba104c83 | 12911 | fprintf (stream, _("\ |
c0f3af97 L |
12912 | -msse2avx encode SSE instructions with VEX prefix\n")); |
12913 | fprintf (stream, _("\ | |
7c5c05ef | 12914 | -msse-check=[none|error|warning] (default: warning)\n\ |
daf50ae7 L |
12915 | check SSE instructions\n")); |
12916 | fprintf (stream, _("\ | |
7c5c05ef | 12917 | -moperand-check=[none|error|warning] (default: warning)\n\ |
7bab8ab5 JB |
12918 | check operand combinations for validity\n")); |
12919 | fprintf (stream, _("\ | |
7c5c05ef L |
12920 | -mavxscalar=[128|256] (default: 128)\n\ |
12921 | encode scalar AVX instructions with specific vector\n\ | |
539f890d L |
12922 | length\n")); |
12923 | fprintf (stream, _("\ | |
03751133 L |
12924 | -mvexwig=[0|1] (default: 0)\n\ |
12925 | encode VEX instructions with specific VEX.W value\n\ | |
12926 | for VEX.W bit ignored instructions\n")); | |
12927 | fprintf (stream, _("\ | |
7c5c05ef L |
12928 | -mevexlig=[128|256|512] (default: 128)\n\ |
12929 | encode scalar EVEX instructions with specific vector\n\ | |
43234a1e L |
12930 | length\n")); |
12931 | fprintf (stream, _("\ | |
7c5c05ef L |
12932 | -mevexwig=[0|1] (default: 0)\n\ |
12933 | encode EVEX instructions with specific EVEX.W value\n\ | |
43234a1e L |
12934 | for EVEX.W bit ignored instructions\n")); |
12935 | fprintf (stream, _("\ | |
7c5c05ef | 12936 | -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\ |
d3d3c6db IT |
12937 | encode EVEX instructions with specific EVEX.RC value\n\ |
12938 | for SAE-only ignored instructions\n")); | |
12939 | fprintf (stream, _("\ | |
7c5c05ef L |
12940 | -mmnemonic=[att|intel] ")); |
12941 | if (SYSV386_COMPAT) | |
12942 | fprintf (stream, _("(default: att)\n")); | |
12943 | else | |
12944 | fprintf (stream, _("(default: intel)\n")); | |
12945 | fprintf (stream, _("\ | |
12946 | use AT&T/Intel mnemonic\n")); | |
ba104c83 | 12947 | fprintf (stream, _("\ |
7c5c05ef L |
12948 | -msyntax=[att|intel] (default: att)\n\ |
12949 | use AT&T/Intel syntax\n")); | |
ba104c83 L |
12950 | fprintf (stream, _("\ |
12951 | -mindex-reg support pseudo index registers\n")); | |
12952 | fprintf (stream, _("\ | |
12953 | -mnaked-reg don't require `%%' prefix for registers\n")); | |
12954 | fprintf (stream, _("\ | |
7e8b059b | 12955 | -madd-bnd-prefix add BND prefix for all valid branches\n")); |
b4a3a7b4 | 12956 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8dcea932 L |
12957 | fprintf (stream, _("\ |
12958 | -mshared disable branch optimization for shared code\n")); | |
b4a3a7b4 L |
12959 | fprintf (stream, _("\ |
12960 | -mx86-used-note=[no|yes] ")); | |
12961 | if (DEFAULT_X86_USED_NOTE) | |
12962 | fprintf (stream, _("(default: yes)\n")); | |
12963 | else | |
12964 | fprintf (stream, _("(default: no)\n")); | |
12965 | fprintf (stream, _("\ | |
12966 | generate x86 used ISA and feature properties\n")); | |
12967 | #endif | |
12968 | #if defined (TE_PE) || defined (TE_PEP) | |
167ad85b TG |
12969 | fprintf (stream, _("\ |
12970 | -mbig-obj generate big object files\n")); | |
12971 | #endif | |
d022bddd | 12972 | fprintf (stream, _("\ |
7c5c05ef | 12973 | -momit-lock-prefix=[no|yes] (default: no)\n\ |
d022bddd | 12974 | strip all lock prefixes\n")); |
5db04b09 | 12975 | fprintf (stream, _("\ |
7c5c05ef | 12976 | -mfence-as-lock-add=[no|yes] (default: no)\n\ |
e4e00185 AS |
12977 | encode lfence, mfence and sfence as\n\ |
12978 | lock addl $0x0, (%%{re}sp)\n")); | |
12979 | fprintf (stream, _("\ | |
7c5c05ef L |
12980 | -mrelax-relocations=[no|yes] ")); |
12981 | if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS) | |
12982 | fprintf (stream, _("(default: yes)\n")); | |
12983 | else | |
12984 | fprintf (stream, _("(default: no)\n")); | |
12985 | fprintf (stream, _("\ | |
0cb4071e L |
12986 | generate relax relocations\n")); |
12987 | fprintf (stream, _("\ | |
e379e5f3 L |
12988 | -malign-branch-boundary=NUM (default: 0)\n\ |
12989 | align branches within NUM byte boundary\n")); | |
12990 | fprintf (stream, _("\ | |
12991 | -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\ | |
12992 | TYPE is combination of jcc, fused, jmp, call, ret,\n\ | |
12993 | indirect\n\ | |
12994 | specify types of branches to align\n")); | |
12995 | fprintf (stream, _("\ | |
12996 | -malign-branch-prefix-size=NUM (default: 5)\n\ | |
12997 | align branches with NUM prefixes per instruction\n")); | |
12998 | fprintf (stream, _("\ | |
76cf450b L |
12999 | -mbranches-within-32B-boundaries\n\ |
13000 | align branches within 32 byte boundary\n")); | |
13001 | fprintf (stream, _("\ | |
7c5c05ef | 13002 | -mamd64 accept only AMD64 ISA [default]\n")); |
5db04b09 L |
13003 | fprintf (stream, _("\ |
13004 | -mintel64 accept only Intel64 ISA\n")); | |
252b5132 RH |
13005 | } |
13006 | ||
3e73aa7c | 13007 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
321098a5 | 13008 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
e57f8c65 | 13009 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
252b5132 RH |
13010 | |
13011 | /* Pick the target format to use. */ | |
13012 | ||
47926f60 | 13013 | const char * |
e3bb37b5 | 13014 | i386_target_format (void) |
252b5132 | 13015 | { |
351f65ca L |
13016 | if (!strncmp (default_arch, "x86_64", 6)) |
13017 | { | |
13018 | update_code_flag (CODE_64BIT, 1); | |
13019 | if (default_arch[6] == '\0') | |
7f56bc95 | 13020 | x86_elf_abi = X86_64_ABI; |
351f65ca | 13021 | else |
7f56bc95 | 13022 | x86_elf_abi = X86_64_X32_ABI; |
351f65ca | 13023 | } |
3e73aa7c | 13024 | else if (!strcmp (default_arch, "i386")) |
78f12dd3 | 13025 | update_code_flag (CODE_32BIT, 1); |
5197d474 L |
13026 | else if (!strcmp (default_arch, "iamcu")) |
13027 | { | |
13028 | update_code_flag (CODE_32BIT, 1); | |
13029 | if (cpu_arch_isa == PROCESSOR_UNKNOWN) | |
13030 | { | |
13031 | static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS; | |
13032 | cpu_arch_name = "iamcu"; | |
13033 | cpu_sub_arch_name = NULL; | |
13034 | cpu_arch_flags = iamcu_flags; | |
13035 | cpu_arch_isa = PROCESSOR_IAMCU; | |
13036 | cpu_arch_isa_flags = iamcu_flags; | |
13037 | if (!cpu_arch_tune_set) | |
13038 | { | |
13039 | cpu_arch_tune = cpu_arch_isa; | |
13040 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
13041 | } | |
13042 | } | |
8d471ec1 | 13043 | else if (cpu_arch_isa != PROCESSOR_IAMCU) |
5197d474 L |
13044 | as_fatal (_("Intel MCU doesn't support `%s' architecture"), |
13045 | cpu_arch_name); | |
13046 | } | |
3e73aa7c | 13047 | else |
2b5d6a91 | 13048 | as_fatal (_("unknown architecture")); |
89507696 JB |
13049 | |
13050 | if (cpu_flags_all_zero (&cpu_arch_isa_flags)) | |
13051 | cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
13052 | if (cpu_flags_all_zero (&cpu_arch_tune_flags)) | |
13053 | cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
13054 | ||
252b5132 RH |
13055 | switch (OUTPUT_FLAVOR) |
13056 | { | |
9384f2ff | 13057 | #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT) |
4c63da97 | 13058 | case bfd_target_aout_flavour: |
47926f60 | 13059 | return AOUT_TARGET_FORMAT; |
4c63da97 | 13060 | #endif |
9384f2ff AM |
13061 | #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF) |
13062 | # if defined (TE_PE) || defined (TE_PEP) | |
13063 | case bfd_target_coff_flavour: | |
167ad85b TG |
13064 | if (flag_code == CODE_64BIT) |
13065 | return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64"; | |
13066 | else | |
13067 | return "pe-i386"; | |
9384f2ff | 13068 | # elif defined (TE_GO32) |
0561d57c JK |
13069 | case bfd_target_coff_flavour: |
13070 | return "coff-go32"; | |
9384f2ff | 13071 | # else |
252b5132 RH |
13072 | case bfd_target_coff_flavour: |
13073 | return "coff-i386"; | |
9384f2ff | 13074 | # endif |
4c63da97 | 13075 | #endif |
3e73aa7c | 13076 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 13077 | case bfd_target_elf_flavour: |
3e73aa7c | 13078 | { |
351f65ca L |
13079 | const char *format; |
13080 | ||
13081 | switch (x86_elf_abi) | |
4fa24527 | 13082 | { |
351f65ca L |
13083 | default: |
13084 | format = ELF_TARGET_FORMAT; | |
e379e5f3 L |
13085 | #ifndef TE_SOLARIS |
13086 | tls_get_addr = "___tls_get_addr"; | |
13087 | #endif | |
351f65ca | 13088 | break; |
7f56bc95 | 13089 | case X86_64_ABI: |
351f65ca | 13090 | use_rela_relocations = 1; |
4fa24527 | 13091 | object_64bit = 1; |
e379e5f3 L |
13092 | #ifndef TE_SOLARIS |
13093 | tls_get_addr = "__tls_get_addr"; | |
13094 | #endif | |
351f65ca L |
13095 | format = ELF_TARGET_FORMAT64; |
13096 | break; | |
7f56bc95 | 13097 | case X86_64_X32_ABI: |
4fa24527 | 13098 | use_rela_relocations = 1; |
351f65ca | 13099 | object_64bit = 1; |
e379e5f3 L |
13100 | #ifndef TE_SOLARIS |
13101 | tls_get_addr = "__tls_get_addr"; | |
13102 | #endif | |
862be3fb | 13103 | disallow_64bit_reloc = 1; |
351f65ca L |
13104 | format = ELF_TARGET_FORMAT32; |
13105 | break; | |
4fa24527 | 13106 | } |
3632d14b | 13107 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 13108 | { |
7f56bc95 | 13109 | if (x86_elf_abi != X86_64_ABI) |
8a9036a4 L |
13110 | as_fatal (_("Intel L1OM is 64bit only")); |
13111 | return ELF_TARGET_L1OM_FORMAT; | |
13112 | } | |
b49f93f6 | 13113 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
7a9068fe L |
13114 | { |
13115 | if (x86_elf_abi != X86_64_ABI) | |
13116 | as_fatal (_("Intel K1OM is 64bit only")); | |
13117 | return ELF_TARGET_K1OM_FORMAT; | |
13118 | } | |
81486035 L |
13119 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
13120 | { | |
13121 | if (x86_elf_abi != I386_ABI) | |
13122 | as_fatal (_("Intel MCU is 32bit only")); | |
13123 | return ELF_TARGET_IAMCU_FORMAT; | |
13124 | } | |
8a9036a4 | 13125 | else |
351f65ca | 13126 | return format; |
3e73aa7c | 13127 | } |
e57f8c65 TG |
13128 | #endif |
13129 | #if defined (OBJ_MACH_O) | |
13130 | case bfd_target_mach_o_flavour: | |
d382c579 TG |
13131 | if (flag_code == CODE_64BIT) |
13132 | { | |
13133 | use_rela_relocations = 1; | |
13134 | object_64bit = 1; | |
13135 | return "mach-o-x86-64"; | |
13136 | } | |
13137 | else | |
13138 | return "mach-o-i386"; | |
4c63da97 | 13139 | #endif |
252b5132 RH |
13140 | default: |
13141 | abort (); | |
13142 | return NULL; | |
13143 | } | |
13144 | } | |
13145 | ||
47926f60 | 13146 | #endif /* OBJ_MAYBE_ more than one */ |
252b5132 | 13147 | \f |
252b5132 | 13148 | symbolS * |
7016a5d5 | 13149 | md_undefined_symbol (char *name) |
252b5132 | 13150 | { |
18dc2407 ILT |
13151 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
13152 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
13153 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
13154 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
13155 | { |
13156 | if (!GOT_symbol) | |
13157 | { | |
13158 | if (symbol_find (name)) | |
13159 | as_bad (_("GOT already in symbol table")); | |
13160 | GOT_symbol = symbol_new (name, undefined_section, | |
13161 | (valueT) 0, &zero_address_frag); | |
13162 | }; | |
13163 | return GOT_symbol; | |
13164 | } | |
252b5132 RH |
13165 | return 0; |
13166 | } | |
13167 | ||
13168 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 13169 | |
252b5132 | 13170 | valueT |
7016a5d5 | 13171 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
252b5132 | 13172 | { |
4c63da97 AM |
13173 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
13174 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
13175 | { | |
13176 | /* For a.out, force the section size to be aligned. If we don't do | |
13177 | this, BFD will align it for us, but it will not write out the | |
13178 | final bytes of the section. This may be a bug in BFD, but it is | |
13179 | easier to fix it here since that is how the other a.out targets | |
13180 | work. */ | |
13181 | int align; | |
13182 | ||
fd361982 | 13183 | align = bfd_section_alignment (segment); |
8d3842cd | 13184 | size = ((size + (1 << align) - 1) & (-((valueT) 1 << align))); |
4c63da97 | 13185 | } |
252b5132 RH |
13186 | #endif |
13187 | ||
13188 | return size; | |
13189 | } | |
13190 | ||
13191 | /* On the i386, PC-relative offsets are relative to the start of the | |
13192 | next instruction. That is, the address of the offset, plus its | |
13193 | size, since the offset is always the last part of the insn. */ | |
13194 | ||
13195 | long | |
e3bb37b5 | 13196 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
13197 | { |
13198 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
13199 | } | |
13200 | ||
13201 | #ifndef I386COFF | |
13202 | ||
13203 | static void | |
e3bb37b5 | 13204 | s_bss (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 13205 | { |
29b0f896 | 13206 | int temp; |
252b5132 | 13207 | |
8a75718c JB |
13208 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
13209 | if (IS_ELF) | |
13210 | obj_elf_section_change_hook (); | |
13211 | #endif | |
252b5132 RH |
13212 | temp = get_absolute_expression (); |
13213 | subseg_set (bss_section, (subsegT) temp); | |
13214 | demand_empty_rest_of_line (); | |
13215 | } | |
13216 | ||
13217 | #endif | |
13218 | ||
e379e5f3 L |
13219 | /* Remember constant directive. */ |
13220 | ||
13221 | void | |
13222 | i386_cons_align (int ignore ATTRIBUTE_UNUSED) | |
13223 | { | |
13224 | if (last_insn.kind != last_insn_directive | |
13225 | && (bfd_section_flags (now_seg) & SEC_CODE)) | |
13226 | { | |
13227 | last_insn.seg = now_seg; | |
13228 | last_insn.kind = last_insn_directive; | |
13229 | last_insn.name = "constant directive"; | |
13230 | last_insn.file = as_where (&last_insn.line); | |
13231 | } | |
13232 | } | |
13233 | ||
252b5132 | 13234 | void |
e3bb37b5 | 13235 | i386_validate_fix (fixS *fixp) |
252b5132 | 13236 | { |
02a86693 | 13237 | if (fixp->fx_subsy) |
252b5132 | 13238 | { |
02a86693 | 13239 | if (fixp->fx_subsy == GOT_symbol) |
23df1078 | 13240 | { |
02a86693 L |
13241 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
13242 | { | |
13243 | if (!object_64bit) | |
13244 | abort (); | |
13245 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
13246 | if (fixp->fx_tcbit2) | |
56ceb5b5 L |
13247 | fixp->fx_r_type = (fixp->fx_tcbit |
13248 | ? BFD_RELOC_X86_64_REX_GOTPCRELX | |
13249 | : BFD_RELOC_X86_64_GOTPCRELX); | |
02a86693 L |
13250 | else |
13251 | #endif | |
13252 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
13253 | } | |
d6ab8113 | 13254 | else |
02a86693 L |
13255 | { |
13256 | if (!object_64bit) | |
13257 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
13258 | else | |
13259 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; | |
13260 | } | |
13261 | fixp->fx_subsy = 0; | |
23df1078 | 13262 | } |
252b5132 | 13263 | } |
02a86693 L |
13264 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
13265 | else if (!object_64bit) | |
13266 | { | |
13267 | if (fixp->fx_r_type == BFD_RELOC_386_GOT32 | |
13268 | && fixp->fx_tcbit2) | |
13269 | fixp->fx_r_type = BFD_RELOC_386_GOT32X; | |
13270 | } | |
13271 | #endif | |
252b5132 RH |
13272 | } |
13273 | ||
252b5132 | 13274 | arelent * |
7016a5d5 | 13275 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
13276 | { |
13277 | arelent *rel; | |
13278 | bfd_reloc_code_real_type code; | |
13279 | ||
13280 | switch (fixp->fx_r_type) | |
13281 | { | |
8ce3d284 | 13282 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
13283 | case BFD_RELOC_SIZE32: |
13284 | case BFD_RELOC_SIZE64: | |
13285 | if (S_IS_DEFINED (fixp->fx_addsy) | |
13286 | && !S_IS_EXTERNAL (fixp->fx_addsy)) | |
13287 | { | |
13288 | /* Resolve size relocation against local symbol to size of | |
13289 | the symbol plus addend. */ | |
13290 | valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset; | |
13291 | if (fixp->fx_r_type == BFD_RELOC_SIZE32 | |
13292 | && !fits_in_unsigned_long (value)) | |
13293 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
13294 | _("symbol size computation overflow")); | |
13295 | fixp->fx_addsy = NULL; | |
13296 | fixp->fx_subsy = NULL; | |
13297 | md_apply_fix (fixp, (valueT *) &value, NULL); | |
13298 | return NULL; | |
13299 | } | |
8ce3d284 | 13300 | #endif |
1a0670f3 | 13301 | /* Fall through. */ |
8fd4256d | 13302 | |
3e73aa7c JH |
13303 | case BFD_RELOC_X86_64_PLT32: |
13304 | case BFD_RELOC_X86_64_GOT32: | |
13305 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
13306 | case BFD_RELOC_X86_64_GOTPCRELX: |
13307 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
252b5132 RH |
13308 | case BFD_RELOC_386_PLT32: |
13309 | case BFD_RELOC_386_GOT32: | |
02a86693 | 13310 | case BFD_RELOC_386_GOT32X: |
252b5132 RH |
13311 | case BFD_RELOC_386_GOTOFF: |
13312 | case BFD_RELOC_386_GOTPC: | |
13ae64f3 JJ |
13313 | case BFD_RELOC_386_TLS_GD: |
13314 | case BFD_RELOC_386_TLS_LDM: | |
13315 | case BFD_RELOC_386_TLS_LDO_32: | |
13316 | case BFD_RELOC_386_TLS_IE_32: | |
37e55690 JJ |
13317 | case BFD_RELOC_386_TLS_IE: |
13318 | case BFD_RELOC_386_TLS_GOTIE: | |
13ae64f3 JJ |
13319 | case BFD_RELOC_386_TLS_LE_32: |
13320 | case BFD_RELOC_386_TLS_LE: | |
67a4f2b7 AO |
13321 | case BFD_RELOC_386_TLS_GOTDESC: |
13322 | case BFD_RELOC_386_TLS_DESC_CALL: | |
bffbf940 JJ |
13323 | case BFD_RELOC_X86_64_TLSGD: |
13324 | case BFD_RELOC_X86_64_TLSLD: | |
13325 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 13326 | case BFD_RELOC_X86_64_DTPOFF64: |
bffbf940 JJ |
13327 | case BFD_RELOC_X86_64_GOTTPOFF: |
13328 | case BFD_RELOC_X86_64_TPOFF32: | |
d6ab8113 JB |
13329 | case BFD_RELOC_X86_64_TPOFF64: |
13330 | case BFD_RELOC_X86_64_GOTOFF64: | |
13331 | case BFD_RELOC_X86_64_GOTPC32: | |
7b81dfbb AJ |
13332 | case BFD_RELOC_X86_64_GOT64: |
13333 | case BFD_RELOC_X86_64_GOTPCREL64: | |
13334 | case BFD_RELOC_X86_64_GOTPC64: | |
13335 | case BFD_RELOC_X86_64_GOTPLT64: | |
13336 | case BFD_RELOC_X86_64_PLTOFF64: | |
67a4f2b7 AO |
13337 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
13338 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
252b5132 RH |
13339 | case BFD_RELOC_RVA: |
13340 | case BFD_RELOC_VTABLE_ENTRY: | |
13341 | case BFD_RELOC_VTABLE_INHERIT: | |
6482c264 NC |
13342 | #ifdef TE_PE |
13343 | case BFD_RELOC_32_SECREL: | |
13344 | #endif | |
252b5132 RH |
13345 | code = fixp->fx_r_type; |
13346 | break; | |
dbbaec26 L |
13347 | case BFD_RELOC_X86_64_32S: |
13348 | if (!fixp->fx_pcrel) | |
13349 | { | |
13350 | /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ | |
13351 | code = fixp->fx_r_type; | |
13352 | break; | |
13353 | } | |
1a0670f3 | 13354 | /* Fall through. */ |
252b5132 | 13355 | default: |
93382f6d | 13356 | if (fixp->fx_pcrel) |
252b5132 | 13357 | { |
93382f6d AM |
13358 | switch (fixp->fx_size) |
13359 | { | |
13360 | default: | |
b091f402 AM |
13361 | as_bad_where (fixp->fx_file, fixp->fx_line, |
13362 | _("can not do %d byte pc-relative relocation"), | |
13363 | fixp->fx_size); | |
93382f6d AM |
13364 | code = BFD_RELOC_32_PCREL; |
13365 | break; | |
13366 | case 1: code = BFD_RELOC_8_PCREL; break; | |
13367 | case 2: code = BFD_RELOC_16_PCREL; break; | |
d258b828 | 13368 | case 4: code = BFD_RELOC_32_PCREL; break; |
d6ab8113 JB |
13369 | #ifdef BFD64 |
13370 | case 8: code = BFD_RELOC_64_PCREL; break; | |
13371 | #endif | |
93382f6d AM |
13372 | } |
13373 | } | |
13374 | else | |
13375 | { | |
13376 | switch (fixp->fx_size) | |
13377 | { | |
13378 | default: | |
b091f402 AM |
13379 | as_bad_where (fixp->fx_file, fixp->fx_line, |
13380 | _("can not do %d byte relocation"), | |
13381 | fixp->fx_size); | |
93382f6d AM |
13382 | code = BFD_RELOC_32; |
13383 | break; | |
13384 | case 1: code = BFD_RELOC_8; break; | |
13385 | case 2: code = BFD_RELOC_16; break; | |
13386 | case 4: code = BFD_RELOC_32; break; | |
937149dd | 13387 | #ifdef BFD64 |
3e73aa7c | 13388 | case 8: code = BFD_RELOC_64; break; |
937149dd | 13389 | #endif |
93382f6d | 13390 | } |
252b5132 RH |
13391 | } |
13392 | break; | |
13393 | } | |
252b5132 | 13394 | |
d182319b JB |
13395 | if ((code == BFD_RELOC_32 |
13396 | || code == BFD_RELOC_32_PCREL | |
13397 | || code == BFD_RELOC_X86_64_32S) | |
252b5132 RH |
13398 | && GOT_symbol |
13399 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c | 13400 | { |
4fa24527 | 13401 | if (!object_64bit) |
d6ab8113 JB |
13402 | code = BFD_RELOC_386_GOTPC; |
13403 | else | |
13404 | code = BFD_RELOC_X86_64_GOTPC32; | |
3e73aa7c | 13405 | } |
7b81dfbb AJ |
13406 | if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) |
13407 | && GOT_symbol | |
13408 | && fixp->fx_addsy == GOT_symbol) | |
13409 | { | |
13410 | code = BFD_RELOC_X86_64_GOTPC64; | |
13411 | } | |
252b5132 | 13412 | |
add39d23 TS |
13413 | rel = XNEW (arelent); |
13414 | rel->sym_ptr_ptr = XNEW (asymbol *); | |
49309057 | 13415 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
13416 | |
13417 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
c87db184 | 13418 | |
3e73aa7c JH |
13419 | if (!use_rela_relocations) |
13420 | { | |
13421 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
13422 | vtable entry to be used in the relocation's section offset. */ | |
13423 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
13424 | rel->address = fixp->fx_offset; | |
fbeb56a4 DK |
13425 | #if defined (OBJ_COFF) && defined (TE_PE) |
13426 | else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy)) | |
13427 | rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2); | |
13428 | else | |
13429 | #endif | |
c6682705 | 13430 | rel->addend = 0; |
3e73aa7c JH |
13431 | } |
13432 | /* Use the rela in 64bit mode. */ | |
252b5132 | 13433 | else |
3e73aa7c | 13434 | { |
862be3fb L |
13435 | if (disallow_64bit_reloc) |
13436 | switch (code) | |
13437 | { | |
862be3fb L |
13438 | case BFD_RELOC_X86_64_DTPOFF64: |
13439 | case BFD_RELOC_X86_64_TPOFF64: | |
13440 | case BFD_RELOC_64_PCREL: | |
13441 | case BFD_RELOC_X86_64_GOTOFF64: | |
13442 | case BFD_RELOC_X86_64_GOT64: | |
13443 | case BFD_RELOC_X86_64_GOTPCREL64: | |
13444 | case BFD_RELOC_X86_64_GOTPC64: | |
13445 | case BFD_RELOC_X86_64_GOTPLT64: | |
13446 | case BFD_RELOC_X86_64_PLTOFF64: | |
13447 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
13448 | _("cannot represent relocation type %s in x32 mode"), | |
13449 | bfd_get_reloc_code_name (code)); | |
13450 | break; | |
13451 | default: | |
13452 | break; | |
13453 | } | |
13454 | ||
062cd5e7 AS |
13455 | if (!fixp->fx_pcrel) |
13456 | rel->addend = fixp->fx_offset; | |
13457 | else | |
13458 | switch (code) | |
13459 | { | |
13460 | case BFD_RELOC_X86_64_PLT32: | |
13461 | case BFD_RELOC_X86_64_GOT32: | |
13462 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
13463 | case BFD_RELOC_X86_64_GOTPCRELX: |
13464 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
bffbf940 JJ |
13465 | case BFD_RELOC_X86_64_TLSGD: |
13466 | case BFD_RELOC_X86_64_TLSLD: | |
13467 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 AO |
13468 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
13469 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
062cd5e7 AS |
13470 | rel->addend = fixp->fx_offset - fixp->fx_size; |
13471 | break; | |
13472 | default: | |
13473 | rel->addend = (section->vma | |
13474 | - fixp->fx_size | |
13475 | + fixp->fx_addnumber | |
13476 | + md_pcrel_from (fixp)); | |
13477 | break; | |
13478 | } | |
3e73aa7c JH |
13479 | } |
13480 | ||
252b5132 RH |
13481 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
13482 | if (rel->howto == NULL) | |
13483 | { | |
13484 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 13485 | _("cannot represent relocation type %s"), |
252b5132 RH |
13486 | bfd_get_reloc_code_name (code)); |
13487 | /* Set howto to a garbage value so that we can keep going. */ | |
13488 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
9c2799c2 | 13489 | gas_assert (rel->howto != NULL); |
252b5132 RH |
13490 | } |
13491 | ||
13492 | return rel; | |
13493 | } | |
13494 | ||
ee86248c | 13495 | #include "tc-i386-intel.c" |
54cfded0 | 13496 | |
a60de03c JB |
13497 | void |
13498 | tc_x86_parse_to_dw2regnum (expressionS *exp) | |
54cfded0 | 13499 | { |
a60de03c JB |
13500 | int saved_naked_reg; |
13501 | char saved_register_dot; | |
54cfded0 | 13502 | |
a60de03c JB |
13503 | saved_naked_reg = allow_naked_reg; |
13504 | allow_naked_reg = 1; | |
13505 | saved_register_dot = register_chars['.']; | |
13506 | register_chars['.'] = '.'; | |
13507 | allow_pseudo_reg = 1; | |
13508 | expression_and_evaluate (exp); | |
13509 | allow_pseudo_reg = 0; | |
13510 | register_chars['.'] = saved_register_dot; | |
13511 | allow_naked_reg = saved_naked_reg; | |
13512 | ||
e96d56a1 | 13513 | if (exp->X_op == O_register && exp->X_add_number >= 0) |
54cfded0 | 13514 | { |
a60de03c JB |
13515 | if ((addressT) exp->X_add_number < i386_regtab_size) |
13516 | { | |
13517 | exp->X_op = O_constant; | |
13518 | exp->X_add_number = i386_regtab[exp->X_add_number] | |
13519 | .dw2_regnum[flag_code >> 1]; | |
13520 | } | |
13521 | else | |
13522 | exp->X_op = O_illegal; | |
54cfded0 | 13523 | } |
54cfded0 AM |
13524 | } |
13525 | ||
13526 | void | |
13527 | tc_x86_frame_initial_instructions (void) | |
13528 | { | |
a60de03c JB |
13529 | static unsigned int sp_regno[2]; |
13530 | ||
13531 | if (!sp_regno[flag_code >> 1]) | |
13532 | { | |
13533 | char *saved_input = input_line_pointer; | |
13534 | char sp[][4] = {"esp", "rsp"}; | |
13535 | expressionS exp; | |
a4447b93 | 13536 | |
a60de03c JB |
13537 | input_line_pointer = sp[flag_code >> 1]; |
13538 | tc_x86_parse_to_dw2regnum (&exp); | |
9c2799c2 | 13539 | gas_assert (exp.X_op == O_constant); |
a60de03c JB |
13540 | sp_regno[flag_code >> 1] = exp.X_add_number; |
13541 | input_line_pointer = saved_input; | |
13542 | } | |
a4447b93 | 13543 | |
61ff971f L |
13544 | cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment); |
13545 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); | |
54cfded0 | 13546 | } |
d2b2c203 | 13547 | |
d7921315 L |
13548 | int |
13549 | x86_dwarf2_addr_size (void) | |
13550 | { | |
13551 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) | |
13552 | if (x86_elf_abi == X86_64_X32_ABI) | |
13553 | return 4; | |
13554 | #endif | |
13555 | return bfd_arch_bits_per_address (stdoutput) / 8; | |
13556 | } | |
13557 | ||
d2b2c203 DJ |
13558 | int |
13559 | i386_elf_section_type (const char *str, size_t len) | |
13560 | { | |
13561 | if (flag_code == CODE_64BIT | |
13562 | && len == sizeof ("unwind") - 1 | |
13563 | && strncmp (str, "unwind", 6) == 0) | |
13564 | return SHT_X86_64_UNWIND; | |
13565 | ||
13566 | return -1; | |
13567 | } | |
bb41ade5 | 13568 | |
ad5fec3b EB |
13569 | #ifdef TE_SOLARIS |
13570 | void | |
13571 | i386_solaris_fix_up_eh_frame (segT sec) | |
13572 | { | |
13573 | if (flag_code == CODE_64BIT) | |
13574 | elf_section_type (sec) = SHT_X86_64_UNWIND; | |
13575 | } | |
13576 | #endif | |
13577 | ||
bb41ade5 AM |
13578 | #ifdef TE_PE |
13579 | void | |
13580 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) | |
13581 | { | |
91d6fa6a | 13582 | expressionS exp; |
bb41ade5 | 13583 | |
91d6fa6a NC |
13584 | exp.X_op = O_secrel; |
13585 | exp.X_add_symbol = symbol; | |
13586 | exp.X_add_number = 0; | |
13587 | emit_expr (&exp, size); | |
bb41ade5 AM |
13588 | } |
13589 | #endif | |
3b22753a L |
13590 | |
13591 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
13592 | /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ | |
13593 | ||
01e1a5bc | 13594 | bfd_vma |
6d4af3c2 | 13595 | x86_64_section_letter (int letter, const char **ptr_msg) |
3b22753a L |
13596 | { |
13597 | if (flag_code == CODE_64BIT) | |
13598 | { | |
13599 | if (letter == 'l') | |
13600 | return SHF_X86_64_LARGE; | |
13601 | ||
8f3bae45 | 13602 | *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string"); |
64e74474 | 13603 | } |
3b22753a | 13604 | else |
8f3bae45 | 13605 | *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string"); |
3b22753a L |
13606 | return -1; |
13607 | } | |
13608 | ||
01e1a5bc | 13609 | bfd_vma |
3b22753a L |
13610 | x86_64_section_word (char *str, size_t len) |
13611 | { | |
8620418b | 13612 | if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large")) |
3b22753a L |
13613 | return SHF_X86_64_LARGE; |
13614 | ||
13615 | return -1; | |
13616 | } | |
13617 | ||
13618 | static void | |
13619 | handle_large_common (int small ATTRIBUTE_UNUSED) | |
13620 | { | |
13621 | if (flag_code != CODE_64BIT) | |
13622 | { | |
13623 | s_comm_internal (0, elf_common_parse); | |
13624 | as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); | |
13625 | } | |
13626 | else | |
13627 | { | |
13628 | static segT lbss_section; | |
13629 | asection *saved_com_section_ptr = elf_com_section_ptr; | |
13630 | asection *saved_bss_section = bss_section; | |
13631 | ||
13632 | if (lbss_section == NULL) | |
13633 | { | |
13634 | flagword applicable; | |
13635 | segT seg = now_seg; | |
13636 | subsegT subseg = now_subseg; | |
13637 | ||
13638 | /* The .lbss section is for local .largecomm symbols. */ | |
13639 | lbss_section = subseg_new (".lbss", 0); | |
13640 | applicable = bfd_applicable_section_flags (stdoutput); | |
fd361982 | 13641 | bfd_set_section_flags (lbss_section, applicable & SEC_ALLOC); |
3b22753a L |
13642 | seg_info (lbss_section)->bss = 1; |
13643 | ||
13644 | subseg_set (seg, subseg); | |
13645 | } | |
13646 | ||
13647 | elf_com_section_ptr = &_bfd_elf_large_com_section; | |
13648 | bss_section = lbss_section; | |
13649 | ||
13650 | s_comm_internal (0, elf_common_parse); | |
13651 | ||
13652 | elf_com_section_ptr = saved_com_section_ptr; | |
13653 | bss_section = saved_bss_section; | |
13654 | } | |
13655 | } | |
13656 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |