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* gdb.fortran/array_element.f: New file.
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
252b5132 1/* i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
aef6203b 3 2000, 2001, 2002, 2003, 2004, 2005
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
252b5132 35#include "opcode/i386.h"
d2b2c203 36#include "elf/x86-64.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
252b5132
RH		 46#ifndef SCALE1_WHEN_NO_INDEX
47/* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51#define SCALE1_WHEN_NO_INDEX 1
52#endif
53
29b0f896
AM		 54#ifndef DEFAULT_ARCH
55#define DEFAULT_ARCH "i386"
246fcdee 56#endif
252b5132 57
edde18a5
AM		 58#ifndef INLINE
59#if __GNUC__ >= 2
60#define INLINE __inline__
61#else
62#define INLINE
63#endif
64#endif
65
29b0f896
AM		 66static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
67static INLINE int fits_in_signed_byte PARAMS ((offsetT));
68static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
69static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
70static INLINE int fits_in_signed_word PARAMS ((offsetT));
71static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
72static INLINE int fits_in_signed_long PARAMS ((offsetT));
847f7ad4
AM		 73static int smallest_imm_type PARAMS ((offsetT));
74static offsetT offset_in_range PARAMS ((offsetT, int));
252b5132 75static int add_prefix PARAMS ((unsigned int));
3e73aa7c 76static void set_code_flag PARAMS ((int));
47926f60 77static void set_16bit_gcc_code_flag PARAMS ((int));
252b5132 78static void set_intel_syntax PARAMS ((int));
e413e4e9 79static void set_cpu_arch PARAMS ((int));
6482c264
NC		 80#ifdef TE_PE
81static void pe_directive_secrel PARAMS ((int));
82#endif
29b0f896
AM		 83static char *output_invalid PARAMS ((int c));
84static int i386_operand PARAMS ((char *operand_string));
85static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
86static const reg_entry *parse_register PARAMS ((char *reg_string,
87 char **end_op));
88static char *parse_insn PARAMS ((char *, char *));
89static char *parse_operands PARAMS ((char *, const char *));
90static void swap_operands PARAMS ((void));
91static void optimize_imm PARAMS ((void));
92static void optimize_disp PARAMS ((void));
93static int match_template PARAMS ((void));
94static int check_string PARAMS ((void));
95static int process_suffix PARAMS ((void));
96static int check_byte_reg PARAMS ((void));
97static int check_long_reg PARAMS ((void));
98static int check_qword_reg PARAMS ((void));
99static int check_word_reg PARAMS ((void));
100static int finalize_imm PARAMS ((void));
101static int process_operands PARAMS ((void));
102static const seg_entry *build_modrm_byte PARAMS ((void));
103static void output_insn PARAMS ((void));
104static void output_branch PARAMS ((void));
105static void output_jump PARAMS ((void));
106static void output_interseg_jump PARAMS ((void));
2bbd9c25
JJ		 107static void output_imm PARAMS ((fragS *insn_start_frag,
108 offsetT insn_start_off));
109static void output_disp PARAMS ((fragS *insn_start_frag,
110 offsetT insn_start_off));
29b0f896
AM		 111#ifndef I386COFF
112static void s_bss PARAMS ((int));
252b5132
RH		 113#endif
114
a847613f 115static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 116
252b5132 117/* 'md_assemble ()' gathers together information and puts it into a
47926f60 118 i386_insn. */
252b5132 119
520dc8e8
AM		 120union i386_op
121 {
122 expressionS *disps;
123 expressionS *imms;
124 const reg_entry *regs;
125 };
126
252b5132
RH		 127struct _i386_insn
128 {
47926f60 129 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 130 template tm;
131
132 /* SUFFIX holds the instruction mnemonic suffix if given.
133 (e.g. 'l' for 'movl') */
134 char suffix;
135
47926f60 136 /* OPERANDS gives the number of given operands. */
252b5132
RH		 137 unsigned int operands;
138
139 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
140 of given register, displacement, memory operands and immediate
47926f60 141 operands. */
252b5132
RH		 142 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
143
144 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 145 use OP[i] for the corresponding operand. */
252b5132
RH		 146 unsigned int types[MAX_OPERANDS];
147
520dc8e8
AM		 148 /* Displacement expression, immediate expression, or register for each
149 operand. */
150 union i386_op op[MAX_OPERANDS];
252b5132 151
3e73aa7c
JH		 152 /* Flags for operands. */
153 unsigned int flags[MAX_OPERANDS];
154#define Operand_PCrel 1
155
252b5132 156 /* Relocation type for operand */
f86103b7 157 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 158
252b5132
RH		 159 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
160 the base index byte below. */
161 const reg_entry *base_reg;
162 const reg_entry *index_reg;
163 unsigned int log2_scale_factor;
164
165 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 166 explicit segment overrides are given. */
ce8a8b2f 167 const seg_entry *seg[2];
252b5132
RH		 168
169 /* PREFIX holds all the given prefix opcodes (usually null).
170 PREFIXES is the number of prefix opcodes. */
171 unsigned int prefixes;
172 unsigned char prefix[MAX_PREFIXES];
173
174 /* RM and SIB are the modrm byte and the sib byte where the
175 addressing modes of this insn are encoded. */
176
177 modrm_byte rm;
3e73aa7c 178 rex_byte rex;
252b5132
RH		 179 sib_byte sib;
180 };
181
182typedef struct _i386_insn i386_insn;
183
184/* List of chars besides those in app.c:symbol_chars that can start an
185 operand. Used to prevent the scrubber eating vital white-space. */
32137342 186const char extra_symbol_chars[] = "*%-(["
252b5132 187#ifdef LEX_AT
32137342
NC		 188 "@"
189#endif
190#ifdef LEX_QM
191 "?"
252b5132 192#endif
32137342 193 ;
252b5132 194
29b0f896
AM		 195#if (defined (TE_I386AIX) \
196 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
197 && !defined (TE_LINUX) \
32137342 198 && !defined (TE_NETWARE) \
29b0f896
AM		 199 && !defined (TE_FreeBSD) \
200 && !defined (TE_NetBSD)))
252b5132 201/* This array holds the chars that always start a comment. If the
ce8a8b2f 202 pre-processor is disabled, these aren't very useful. */
252b5132
RH		 203const char comment_chars[] = "#/";
204#define PREFIX_SEPARATOR '\\'
252b5132
RH		 205
206/* This array holds the chars that only start a comment at the beginning of
207 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 208 .line and .file directives will appear in the pre-processed output.
209 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 210 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 211 #NO_APP at the beginning of its output.
212 Also note that comments started like this one will always work if
252b5132 213 '/' isn't otherwise defined. */
0d9f6d04 214const char line_comment_chars[] = "#";
29b0f896 215
252b5132 216#else
29b0f896
AM		 217/* Putting '/' here makes it impossible to use the divide operator.
218 However, we need it for compatibility with SVR4 systems. */
219const char comment_chars[] = "#";
220#define PREFIX_SEPARATOR '/'
221
0d9f6d04 222const char line_comment_chars[] = "/#";
252b5132
RH		 223#endif
224
63a0b638 225const char line_separator_chars[] = ";";
252b5132 226
ce8a8b2f
AM		 227/* Chars that can be used to separate mant from exp in floating point
228 nums. */
252b5132
RH		 229const char EXP_CHARS[] = "eE";
230
ce8a8b2f
AM		 231/* Chars that mean this number is a floating point constant
232 As in 0f12.456
233 or 0d1.2345e12. */
252b5132
RH		 234const char FLT_CHARS[] = "fFdDxX";
235
ce8a8b2f 236/* Tables for lexical analysis. */
252b5132
RH		 237static char mnemonic_chars[256];
238static char register_chars[256];
239static char operand_chars[256];
240static char identifier_chars[256];
241static char digit_chars[256];
242
ce8a8b2f 243/* Lexical macros. */
252b5132
RH		 244#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
245#define is_operand_char(x) (operand_chars[(unsigned char) x])
246#define is_register_char(x) (register_chars[(unsigned char) x])
247#define is_space_char(x) ((x) == ' ')
248#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
249#define is_digit_char(x) (digit_chars[(unsigned char) x])
250
0234cb7c 251/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 252static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
253
254/* md_assemble() always leaves the strings it's passed unaltered. To
255 effect this we maintain a stack of saved characters that we've smashed
256 with '\0's (indicating end of strings for various sub-fields of the
47926f60 257 assembler instruction). */
252b5132 258static char save_stack[32];
ce8a8b2f 259static char *save_stack_p;
252b5132
RH		 260#define END_STRING_AND_SAVE(s) \
261 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
262#define RESTORE_END_STRING(s) \
263 do { *(s) = *--save_stack_p; } while (0)
264
47926f60 265/* The instruction we're assembling. */
252b5132
RH		 266static i386_insn i;
267
268/* Possible templates for current insn. */
269static const templates *current_templates;
270
47926f60 271/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
252b5132
RH		 272static expressionS disp_expressions[2], im_expressions[2];
273
47926f60
KH		 274/* Current operand we are working on. */
275static int this_operand;
252b5132 276
3e73aa7c
JH		 277/* We support four different modes. FLAG_CODE variable is used to distinguish
278 these. */
279
280enum flag_code {
281 CODE_32BIT,
282 CODE_16BIT,
283 CODE_64BIT };
f3c180ae 284#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 285
286static enum flag_code flag_code;
287static int use_rela_relocations = 0;
288
289/* The names used to print error messages. */
b77a7acd 290static const char *flag_code_names[] =
3e73aa7c
JH		 291 {
292 "32",
293 "16",
294 "64"
295 };
252b5132 296
47926f60
KH		 297/* 1 for intel syntax,
298 0 if att syntax. */
299static int intel_syntax = 0;
252b5132 300
47926f60
KH		 301/* 1 if register prefix % not required. */
302static int allow_naked_reg = 0;
252b5132 303
47926f60
KH		 304/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
305 leave, push, and pop instructions so that gcc has the same stack
306 frame as in 32 bit mode. */
307static char stackop_size = '\0';
eecb386c 308
12b55ccc
L		 309/* Non-zero to optimize code alignment. */
310int optimize_align_code = 1;
311
47926f60
KH		 312/* Non-zero to quieten some warnings. */
313static int quiet_warnings = 0;
a38cf1db 314
47926f60
KH		 315/* CPU name. */
316static const char *cpu_arch_name = NULL;
5c6af06e 317static const char *cpu_sub_arch_name = NULL;
a38cf1db 318
47926f60 319/* CPU feature flags. */
29b0f896 320static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 321
fddf5b5b
AM		 322/* If set, conditional jumps are not automatically promoted to handle
323 larger than a byte offset. */
324static unsigned int no_cond_jump_promotion = 0;
325
29b0f896 326/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 327static symbolS *GOT_symbol;
29b0f896 328
a4447b93
RH		 329/* The dwarf2 return column, adjusted for 32 or 64 bit. */
330unsigned int x86_dwarf2_return_column;
331
332/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
333int x86_cie_data_alignment;
334
252b5132 335/* Interface to relax_segment.
fddf5b5b
AM		 336 There are 3 major relax states for 386 jump insns because the
337 different types of jumps add different sizes to frags when we're
338 figuring out what sort of jump to choose to reach a given label. */
252b5132 339
47926f60 340/* Types. */
93c2a809
AM		 341#define UNCOND_JUMP 0
342#define COND_JUMP 1
343#define COND_JUMP86 2
fddf5b5b 344
47926f60 345/* Sizes. */
252b5132
RH		 346#define CODE16 1
347#define SMALL 0
29b0f896 348#define SMALL16 (SMALL | CODE16)
252b5132 349#define BIG 2
29b0f896 350#define BIG16 (BIG | CODE16)
252b5132
RH		 351
352#ifndef INLINE
353#ifdef __GNUC__
354#define INLINE __inline__
355#else
356#define INLINE
357#endif
358#endif
359
fddf5b5b
AM		 360#define ENCODE_RELAX_STATE(type, size) \
361 ((relax_substateT) (((type) << 2) | (size)))
362#define TYPE_FROM_RELAX_STATE(s) \
363 ((s) >> 2)
364#define DISP_SIZE_FROM_RELAX_STATE(s) \
365 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 366
367/* This table is used by relax_frag to promote short jumps to long
368 ones where necessary. SMALL (short) jumps may be promoted to BIG
369 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
370 don't allow a short jump in a 32 bit code segment to be promoted to
371 a 16 bit offset jump because it's slower (requires data size
372 prefix), and doesn't work, unless the destination is in the bottom
373 64k of the code segment (The top 16 bits of eip are zeroed). */
374
375const relax_typeS md_relax_table[] =
376{
24eab124
AM		 377 /* The fields are:
378 1) most positive reach of this state,
379 2) most negative reach of this state,
93c2a809 380 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 381 4) which index into the table to try if we can't fit into this one. */
252b5132 382
fddf5b5b 383 /* UNCOND_JUMP states. */
93c2a809
AM		 384 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
385 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
386 /* dword jmp adds 4 bytes to frag:
387 0 extra opcode bytes, 4 displacement bytes. */
252b5132 388 {0, 0, 4, 0},
93c2a809
AM		 389 /* word jmp adds 2 byte2 to frag:
390 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 391 {0, 0, 2, 0},
392
93c2a809
AM		 393 /* COND_JUMP states. */
394 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
395 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
396 /* dword conditionals adds 5 bytes to frag:
397 1 extra opcode byte, 4 displacement bytes. */
398 {0, 0, 5, 0},
fddf5b5b 399 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 400 1 extra opcode byte, 2 displacement bytes. */
401 {0, 0, 3, 0},
402
403 /* COND_JUMP86 states. */
404 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
405 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
406 /* dword conditionals adds 5 bytes to frag:
407 1 extra opcode byte, 4 displacement bytes. */
408 {0, 0, 5, 0},
409 /* word conditionals add 4 bytes to frag:
410 1 displacement byte and a 3 byte long branch insn. */
411 {0, 0, 4, 0}
252b5132
RH		 412};
413
e413e4e9
AM		 414static const arch_entry cpu_arch[] = {
415 {"i8086", Cpu086 },
416 {"i186", Cpu086|Cpu186 },
417 {"i286", Cpu086|Cpu186|Cpu286 },
418 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
419 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
5c6af06e
JB		 420 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
421 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
422 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
423 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
424 {"pentiumii", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX },
425 {"pentiumiii",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE },
426 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
427 {"prescott", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI },
428 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX },
429 {"k6_2", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
430 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
431 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
432 {".mmx", CpuMMX },
433 {".sse", CpuMMX|CpuMMX2|CpuSSE },
434 {".sse2", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
435 {".3dnow", CpuMMX|Cpu3dnow },
436 {".3dnowa", CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
437 {".padlock", CpuPadLock },
e413e4e9
AM		 438 {NULL, 0 }
439};
440
29b0f896
AM		 441const pseudo_typeS md_pseudo_table[] =
442{
443#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
444 {"align", s_align_bytes, 0},
445#else
446 {"align", s_align_ptwo, 0},
447#endif
448 {"arch", set_cpu_arch, 0},
449#ifndef I386COFF
450 {"bss", s_bss, 0},
451#endif
452 {"ffloat", float_cons, 'f'},
453 {"dfloat", float_cons, 'd'},
454 {"tfloat", float_cons, 'x'},
455 {"value", cons, 2},
456 {"noopt", s_ignore, 0},
457 {"optim", s_ignore, 0},
458 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
459 {"code16", set_code_flag, CODE_16BIT},
460 {"code32", set_code_flag, CODE_32BIT},
461 {"code64", set_code_flag, CODE_64BIT},
462 {"intel_syntax", set_intel_syntax, 1},
463 {"att_syntax", set_intel_syntax, 0},
c6682705 464 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
29b0f896 465 {"loc", dwarf2_directive_loc, 0},
6482c264
NC		 466#ifdef TE_PE
467 {"secrel32", pe_directive_secrel, 0},
468#endif
29b0f896
AM		 469 {0, 0, 0}
470};
471
472/* For interface with expression (). */
473extern char *input_line_pointer;
474
475/* Hash table for instruction mnemonic lookup. */
476static struct hash_control *op_hash;
477
478/* Hash table for register lookup. */
479static struct hash_control *reg_hash;
480\f
252b5132
RH		 481void
482i386_align_code (fragP, count)
483 fragS *fragP;
484 int count;
485{
ce8a8b2f
AM		 486 /* Various efficient no-op patterns for aligning code labels.
487 Note: Don't try to assemble the instructions in the comments.
488 0L and 0w are not legal. */
252b5132
RH		 489 static const char f32_1[] =
490 {0x90}; /* nop */
491 static const char f32_2[] =
492 {0x89,0xf6}; /* movl %esi,%esi */
493 static const char f32_3[] =
494 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
495 static const char f32_4[] =
496 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
497 static const char f32_5[] =
498 {0x90, /* nop */
499 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
500 static const char f32_6[] =
501 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
502 static const char f32_7[] =
503 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
504 static const char f32_8[] =
505 {0x90, /* nop */
506 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
507 static const char f32_9[] =
508 {0x89,0xf6, /* movl %esi,%esi */
509 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
510 static const char f32_10[] =
511 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
512 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
513 static const char f32_11[] =
514 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
515 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
516 static const char f32_12[] =
517 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
518 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
519 static const char f32_13[] =
520 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
521 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
522 static const char f32_14[] =
523 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
524 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
525 static const char f32_15[] =
526 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
527 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 528 static const char f16_3[] =
529 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 530 static const char f16_4[] =
531 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
532 static const char f16_5[] =
533 {0x90, /* nop */
534 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
535 static const char f16_6[] =
536 {0x89,0xf6, /* mov %si,%si */
537 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
538 static const char f16_7[] =
539 {0x8d,0x74,0x00, /* lea 0(%si),%si */
540 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
541 static const char f16_8[] =
542 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
543 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
544 static const char *const f32_patt[] = {
545 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
546 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
547 };
548 static const char *const f16_patt[] = {
c3332e24 549 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 550 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
551 };
552
33fef721
JH		 553 if (count <= 0 || count > 15)
554 return;
3e73aa7c 555
33fef721
JH		 556 /* The recommended way to pad 64bit code is to use NOPs preceded by
557 maximally four 0x66 prefixes. Balance the size of nops. */
558 if (flag_code == CODE_64BIT)
252b5132 559 {
33fef721
JH		 560 int i;
561 int nnops = (count + 3) / 4;
562 int len = count / nnops;
563 int remains = count - nnops * len;
564 int pos = 0;
565
566 for (i = 0; i < remains; i++)
252b5132 567 {
33fef721
JH		 568 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
569 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
570 pos += len + 1;
571 }
572 for (; i < nnops; i++)
573 {
574 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
575 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
576 pos += len;
252b5132 577 }
252b5132 578 }
33fef721
JH		 579 else
580 if (flag_code == CODE_16BIT)
581 {
582 memcpy (fragP->fr_literal + fragP->fr_fix,
583 f16_patt[count - 1], count);
584 if (count > 8)
585 /* Adjust jump offset. */
586 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
587 }
588 else
589 memcpy (fragP->fr_literal + fragP->fr_fix,
590 f32_patt[count - 1], count);
591 fragP->fr_var = count;
252b5132
RH		 592}
593
252b5132
RH		 594static INLINE unsigned int
595mode_from_disp_size (t)
596 unsigned int t;
597{
3e73aa7c 598 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 599}
600
601static INLINE int
602fits_in_signed_byte (num)
847f7ad4 603 offsetT num;
252b5132
RH		 604{
605 return (num >= -128) && (num <= 127);
47926f60 606}
252b5132
RH		 607
608static INLINE int
609fits_in_unsigned_byte (num)
847f7ad4 610 offsetT num;
252b5132
RH		 611{
612 return (num & 0xff) == num;
47926f60 613}
252b5132
RH		 614
615static INLINE int
616fits_in_unsigned_word (num)
847f7ad4 617 offsetT num;
252b5132
RH		 618{
619 return (num & 0xffff) == num;
47926f60 620}
252b5132
RH		 621
622static INLINE int
623fits_in_signed_word (num)
847f7ad4 624 offsetT num;
252b5132
RH		 625{
626 return (-32768 <= num) && (num <= 32767);
47926f60 627}
3e73aa7c
JH		 628static INLINE int
629fits_in_signed_long (num)
630 offsetT num ATTRIBUTE_UNUSED;
631{
632#ifndef BFD64
633 return 1;
634#else
635 return (!(((offsetT) -1 << 31) & num)
636 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
637#endif
638} /* fits_in_signed_long() */
639static INLINE int
640fits_in_unsigned_long (num)
641 offsetT num ATTRIBUTE_UNUSED;
642{
643#ifndef BFD64
644 return 1;
645#else
646 return (num & (((offsetT) 2 << 31) - 1)) == num;
647#endif
648} /* fits_in_unsigned_long() */
252b5132
RH		 649
650static int
651smallest_imm_type (num)
847f7ad4 652 offsetT num;
252b5132 653{
a847613f 654 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 655 {
656 /* This code is disabled on the 486 because all the Imm1 forms
657 in the opcode table are slower on the i486. They're the
658 versions with the implicitly specified single-position
659 displacement, which has another syntax if you really want to
660 use that form. */
661 if (num == 1)
3e73aa7c 662 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 663 }
252b5132 664 return (fits_in_signed_byte (num)
3e73aa7c 665 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 666 : fits_in_unsigned_byte (num)
3e73aa7c 667 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 668 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 669 ? (Imm16 | Imm32 | Imm32S | Imm64)
670 : fits_in_signed_long (num)
671 ? (Imm32 | Imm32S | Imm64)
672 : fits_in_unsigned_long (num)
673 ? (Imm32 | Imm64)
674 : Imm64);
47926f60 675}
252b5132 676
847f7ad4
AM		 677static offsetT
678offset_in_range (val, size)
679 offsetT val;
680 int size;
681{
508866be 682 addressT mask;
ba2adb93 683
847f7ad4
AM		 684 switch (size)
685 {
508866be
L		 686 case 1: mask = ((addressT) 1 << 8) - 1; break;
687 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 688 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 689#ifdef BFD64
690 case 8: mask = ((addressT) 2 << 63) - 1; break;
691#endif
47926f60 692 default: abort ();
847f7ad4
AM		 693 }
694
ba2adb93 695 /* If BFD64, sign extend val. */
3e73aa7c
JH		 696 if (!use_rela_relocations)
697 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
698 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 699
47926f60 700 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 701 {
702 char buf1[40], buf2[40];
703
704 sprint_value (buf1, val);
705 sprint_value (buf2, val & mask);
706 as_warn (_("%s shortened to %s"), buf1, buf2);
707 }
708 return val & mask;
709}
710
252b5132
RH		 711/* Returns 0 if attempting to add a prefix where one from the same
712 class already exists, 1 if non rep/repne added, 2 if rep/repne
713 added. */
714static int
715add_prefix (prefix)
716 unsigned int prefix;
717{
718 int ret = 1;
719 int q;
720
29b0f896
AM		 721 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
722 && flag_code == CODE_64BIT)
3e73aa7c
JH		 723 q = REX_PREFIX;
724 else
725 switch (prefix)
726 {
727 default:
728 abort ();
729
730 case CS_PREFIX_OPCODE:
731 case DS_PREFIX_OPCODE:
732 case ES_PREFIX_OPCODE:
733 case FS_PREFIX_OPCODE:
734 case GS_PREFIX_OPCODE:
735 case SS_PREFIX_OPCODE:
736 q = SEG_PREFIX;
737 break;
252b5132 738
3e73aa7c
JH		 739 case REPNE_PREFIX_OPCODE:
740 case REPE_PREFIX_OPCODE:
741 ret = 2;
742 /* fall thru */
743 case LOCK_PREFIX_OPCODE:
744 q = LOCKREP_PREFIX;
745 break;
252b5132 746
3e73aa7c
JH		 747 case FWAIT_OPCODE:
748 q = WAIT_PREFIX;
749 break;
252b5132 750
3e73aa7c
JH		 751 case ADDR_PREFIX_OPCODE:
752 q = ADDR_PREFIX;
753 break;
252b5132 754
3e73aa7c
JH		 755 case DATA_PREFIX_OPCODE:
756 q = DATA_PREFIX;
757 break;
758 }
252b5132 759
29b0f896 760 if (i.prefix[q] != 0)
252b5132
RH		 761 {
762 as_bad (_("same type of prefix used twice"));
763 return 0;
764 }
765
766 i.prefixes += 1;
767 i.prefix[q] = prefix;
768 return ret;
769}
770
771static void
3e73aa7c 772set_code_flag (value)
e5cb08ac 773 int value;
eecb386c 774{
3e73aa7c
JH		 775 flag_code = value;
776 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
777 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
778 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
779 {
780 as_bad (_("64bit mode not supported on this CPU."));
781 }
782 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
783 {
784 as_bad (_("32bit mode not supported on this CPU."));
785 }
eecb386c
AM		 786 stackop_size = '\0';
787}
788
789static void
3e73aa7c
JH		 790set_16bit_gcc_code_flag (new_code_flag)
791 int new_code_flag;
252b5132 792{
3e73aa7c
JH		 793 flag_code = new_code_flag;
794 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
795 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
9306ca4a 796 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 797}
798
799static void
800set_intel_syntax (syntax_flag)
eecb386c 801 int syntax_flag;
252b5132
RH		 802{
803 /* Find out if register prefixing is specified. */
804 int ask_naked_reg = 0;
805
806 SKIP_WHITESPACE ();
29b0f896 807 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 808 {
809 char *string = input_line_pointer;
810 int e = get_symbol_end ();
811
47926f60 812 if (strcmp (string, "prefix") == 0)
252b5132 813 ask_naked_reg = 1;
47926f60 814 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 815 ask_naked_reg = -1;
816 else
d0b47220 817 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 818 *input_line_pointer = e;
819 }
820 demand_empty_rest_of_line ();
c3332e24 821
252b5132
RH		 822 intel_syntax = syntax_flag;
823
824 if (ask_naked_reg == 0)
f86103b7
AM		 825 allow_naked_reg = (intel_syntax
826 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 827 else
828 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a
JB		 829
830 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
831 identifier_chars['$'] = intel_syntax ? '$' : 0;
252b5132
RH		 832}
833
e413e4e9
AM		 834static void
835set_cpu_arch (dummy)
47926f60 836 int dummy ATTRIBUTE_UNUSED;
e413e4e9 837{
47926f60 838 SKIP_WHITESPACE ();
e413e4e9 839
29b0f896 840 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 841 {
842 char *string = input_line_pointer;
843 int e = get_symbol_end ();
844 int i;
845
846 for (i = 0; cpu_arch[i].name; i++)
847 {
848 if (strcmp (string, cpu_arch[i].name) == 0)
849 {
5c6af06e
JB		 850 if (*string != '.')
851 {
852 cpu_arch_name = cpu_arch[i].name;
853 cpu_sub_arch_name = NULL;
854 cpu_arch_flags = (cpu_arch[i].flags
855 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
856 break;
857 }
858 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
859 {
860 cpu_sub_arch_name = cpu_arch[i].name;
861 cpu_arch_flags |= cpu_arch[i].flags;
862 }
863 *input_line_pointer = e;
864 demand_empty_rest_of_line ();
865 return;
e413e4e9
AM		 866 }
867 }
868 if (!cpu_arch[i].name)
869 as_bad (_("no such architecture: `%s'"), string);
870
871 *input_line_pointer = e;
872 }
873 else
874 as_bad (_("missing cpu architecture"));
875
fddf5b5b
AM		 876 no_cond_jump_promotion = 0;
877 if (*input_line_pointer == ','
29b0f896 878 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 879 {
880 char *string = ++input_line_pointer;
881 int e = get_symbol_end ();
882
883 if (strcmp (string, "nojumps") == 0)
884 no_cond_jump_promotion = 1;
885 else if (strcmp (string, "jumps") == 0)
886 ;
887 else
888 as_bad (_("no such architecture modifier: `%s'"), string);
889
890 *input_line_pointer = e;
891 }
892
e413e4e9
AM		 893 demand_empty_rest_of_line ();
894}
895
b9d79e03
JH		 896unsigned long
897i386_mach ()
898{
899 if (!strcmp (default_arch, "x86_64"))
900 return bfd_mach_x86_64;
901 else if (!strcmp (default_arch, "i386"))
902 return bfd_mach_i386_i386;
903 else
904 as_fatal (_("Unknown architecture"));
905}
b9d79e03 906\f
252b5132
RH		 907void
908md_begin ()
909{
910 const char *hash_err;
911
47926f60 912 /* Initialize op_hash hash table. */
252b5132
RH		 913 op_hash = hash_new ();
914
915 {
29b0f896
AM		 916 const template *optab;
917 templates *core_optab;
252b5132 918
47926f60
KH		 919 /* Setup for loop. */
920 optab = i386_optab;
252b5132
RH		 921 core_optab = (templates *) xmalloc (sizeof (templates));
922 core_optab->start = optab;
923
924 while (1)
925 {
926 ++optab;
927 if (optab->name == NULL
928 || strcmp (optab->name, (optab - 1)->name) != 0)
929 {
930 /* different name --> ship out current template list;
47926f60 931 add to hash table; & begin anew. */
252b5132
RH		 932 core_optab->end = optab;
933 hash_err = hash_insert (op_hash,
934 (optab - 1)->name,
935 (PTR) core_optab);
936 if (hash_err)
937 {
252b5132
RH		 938 as_fatal (_("Internal Error: Can't hash %s: %s"),
939 (optab - 1)->name,
940 hash_err);
941 }
942 if (optab->name == NULL)
943 break;
944 core_optab = (templates *) xmalloc (sizeof (templates));
945 core_optab->start = optab;
946 }
947 }
948 }
949
47926f60 950 /* Initialize reg_hash hash table. */
252b5132
RH		 951 reg_hash = hash_new ();
952 {
29b0f896 953 const reg_entry *regtab;
252b5132
RH		 954
955 for (regtab = i386_regtab;
956 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
957 regtab++)
958 {
959 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
960 if (hash_err)
3e73aa7c
JH		 961 as_fatal (_("Internal Error: Can't hash %s: %s"),
962 regtab->reg_name,
963 hash_err);
252b5132
RH		 964 }
965 }
966
47926f60 967 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 968 {
29b0f896
AM		 969 int c;
970 char *p;
252b5132
RH		 971
972 for (c = 0; c < 256; c++)
973 {
3882b010 974 if (ISDIGIT (c))
252b5132
RH		 975 {
976 digit_chars[c] = c;
977 mnemonic_chars[c] = c;
978 register_chars[c] = c;
979 operand_chars[c] = c;
980 }
3882b010 981 else if (ISLOWER (c))
252b5132
RH		 982 {
983 mnemonic_chars[c] = c;
984 register_chars[c] = c;
985 operand_chars[c] = c;
986 }
3882b010 987 else if (ISUPPER (c))
252b5132 988 {
3882b010 989 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 990 register_chars[c] = mnemonic_chars[c];
991 operand_chars[c] = c;
992 }
993
3882b010 994 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 995 identifier_chars[c] = c;
996 else if (c >= 128)
997 {
998 identifier_chars[c] = c;
999 operand_chars[c] = c;
1000 }
1001 }
1002
1003#ifdef LEX_AT
1004 identifier_chars['@'] = '@';
32137342
NC		 1005#endif
1006#ifdef LEX_QM
1007 identifier_chars['?'] = '?';
1008 operand_chars['?'] = '?';
252b5132 1009#endif
252b5132 1010 digit_chars['-'] = '-';
791fe849 1011 mnemonic_chars['-'] = '-';
252b5132
RH		 1012 identifier_chars['_'] = '_';
1013 identifier_chars['.'] = '.';
1014
1015 for (p = operand_special_chars; *p != '\0'; p++)
1016 operand_chars[(unsigned char) *p] = *p;
1017 }
1018
1019#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1020 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1021 {
1022 record_alignment (text_section, 2);
1023 record_alignment (data_section, 2);
1024 record_alignment (bss_section, 2);
1025 }
1026#endif
a4447b93
RH		 1027
1028 if (flag_code == CODE_64BIT)
1029 {
1030 x86_dwarf2_return_column = 16;
1031 x86_cie_data_alignment = -8;
1032 }
1033 else
1034 {
1035 x86_dwarf2_return_column = 8;
1036 x86_cie_data_alignment = -4;
1037 }
252b5132
RH		 1038}
1039
1040void
1041i386_print_statistics (file)
1042 FILE *file;
1043{
1044 hash_print_statistics (file, "i386 opcode", op_hash);
1045 hash_print_statistics (file, "i386 register", reg_hash);
1046}
1047\f
252b5132
RH		 1048#ifdef DEBUG386
1049
ce8a8b2f 1050/* Debugging routines for md_assemble. */
252b5132
RH		 1051static void pi PARAMS ((char *, i386_insn *));
1052static void pte PARAMS ((template *));
1053static void pt PARAMS ((unsigned int));
1054static void pe PARAMS ((expressionS *));
1055static void ps PARAMS ((symbolS *));
1056
1057static void
1058pi (line, x)
1059 char *line;
1060 i386_insn *x;
1061{
09f131f2 1062 unsigned int i;
252b5132
RH		 1063
1064 fprintf (stdout, "%s: template ", line);
1065 pte (&x->tm);
09f131f2
JH		 1066 fprintf (stdout, " address: base %s index %s scale %x\n",
1067 x->base_reg ? x->base_reg->reg_name : "none",
1068 x->index_reg ? x->index_reg->reg_name : "none",
1069 x->log2_scale_factor);
1070 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1071 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1072 fprintf (stdout, " sib: base %x index %x scale %x\n",
1073 x->sib.base, x->sib.index, x->sib.scale);
1074 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
29b0f896
AM		 1075 (x->rex & REX_MODE64) != 0,
1076 (x->rex & REX_EXTX) != 0,
1077 (x->rex & REX_EXTY) != 0,
1078 (x->rex & REX_EXTZ) != 0);
252b5132
RH		 1079 for (i = 0; i < x->operands; i++)
1080 {
1081 fprintf (stdout, " #%d: ", i + 1);
1082 pt (x->types[i]);
1083 fprintf (stdout, "\n");
1084 if (x->types[i]
3f4438ab 1085 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1086 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1087 if (x->types[i] & Imm)
520dc8e8 1088 pe (x->op[i].imms);
252b5132 1089 if (x->types[i] & Disp)
520dc8e8 1090 pe (x->op[i].disps);
252b5132
RH		 1091 }
1092}
1093
1094static void
1095pte (t)
1096 template *t;
1097{
09f131f2 1098 unsigned int i;
252b5132 1099 fprintf (stdout, " %d operands ", t->operands);
47926f60 1100 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1101 if (t->extension_opcode != None)
1102 fprintf (stdout, "ext %x ", t->extension_opcode);
1103 if (t->opcode_modifier & D)
1104 fprintf (stdout, "D");
1105 if (t->opcode_modifier & W)
1106 fprintf (stdout, "W");
1107 fprintf (stdout, "\n");
1108 for (i = 0; i < t->operands; i++)
1109 {
1110 fprintf (stdout, " #%d type ", i + 1);
1111 pt (t->operand_types[i]);
1112 fprintf (stdout, "\n");
1113 }
1114}
1115
1116static void
1117pe (e)
1118 expressionS *e;
1119{
24eab124 1120 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1121 fprintf (stdout, " add_number %ld (%lx)\n",
1122 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1123 if (e->X_add_symbol)
1124 {
1125 fprintf (stdout, " add_symbol ");
1126 ps (e->X_add_symbol);
1127 fprintf (stdout, "\n");
1128 }
1129 if (e->X_op_symbol)
1130 {
1131 fprintf (stdout, " op_symbol ");
1132 ps (e->X_op_symbol);
1133 fprintf (stdout, "\n");
1134 }
1135}
1136
1137static void
1138ps (s)
1139 symbolS *s;
1140{
1141 fprintf (stdout, "%s type %s%s",
1142 S_GET_NAME (s),
1143 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1144 segment_name (S_GET_SEGMENT (s)));
1145}
1146
1147struct type_name
1148 {
1149 unsigned int mask;
1150 char *tname;
1151 }
1152
29b0f896 1153static const type_names[] =
252b5132
RH		 1154{
1155 { Reg8, "r8" },
1156 { Reg16, "r16" },
1157 { Reg32, "r32" },
09f131f2 1158 { Reg64, "r64" },
252b5132
RH		 1159 { Imm8, "i8" },
1160 { Imm8S, "i8s" },
1161 { Imm16, "i16" },
1162 { Imm32, "i32" },
09f131f2
JH		 1163 { Imm32S, "i32s" },
1164 { Imm64, "i64" },
252b5132
RH		 1165 { Imm1, "i1" },
1166 { BaseIndex, "BaseIndex" },
1167 { Disp8, "d8" },
1168 { Disp16, "d16" },
1169 { Disp32, "d32" },
09f131f2
JH		 1170 { Disp32S, "d32s" },
1171 { Disp64, "d64" },
252b5132
RH		 1172 { InOutPortReg, "InOutPortReg" },
1173 { ShiftCount, "ShiftCount" },
1174 { Control, "control reg" },
1175 { Test, "test reg" },
1176 { Debug, "debug reg" },
1177 { FloatReg, "FReg" },
1178 { FloatAcc, "FAcc" },
1179 { SReg2, "SReg2" },
1180 { SReg3, "SReg3" },
1181 { Acc, "Acc" },
1182 { JumpAbsolute, "Jump Absolute" },
1183 { RegMMX, "rMMX" },
3f4438ab 1184 { RegXMM, "rXMM" },
252b5132
RH		 1185 { EsSeg, "es" },
1186 { 0, "" }
1187};
1188
1189static void
1190pt (t)
1191 unsigned int t;
1192{
29b0f896 1193 const struct type_name *ty;
252b5132 1194
09f131f2
JH		 1195 for (ty = type_names; ty->mask; ty++)
1196 if (t & ty->mask)
1197 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1198 fflush (stdout);
1199}
1200
1201#endif /* DEBUG386 */
1202\f
29b0f896
AM		 1203static bfd_reloc_code_real_type reloc
1204 PARAMS ((int, int, int, bfd_reloc_code_real_type));
252b5132
RH		 1205
1206static bfd_reloc_code_real_type
3e73aa7c 1207reloc (size, pcrel, sign, other)
252b5132
RH		 1208 int size;
1209 int pcrel;
3e73aa7c 1210 int sign;
252b5132
RH		 1211 bfd_reloc_code_real_type other;
1212{
47926f60
KH		 1213 if (other != NO_RELOC)
1214 return other;
252b5132
RH		 1215
1216 if (pcrel)
1217 {
3e73aa7c 1218 if (!sign)
e5cb08ac 1219 as_bad (_("There are no unsigned pc-relative relocations"));
252b5132
RH		 1220 switch (size)
1221 {
1222 case 1: return BFD_RELOC_8_PCREL;
1223 case 2: return BFD_RELOC_16_PCREL;
1224 case 4: return BFD_RELOC_32_PCREL;
1225 }
d0b47220 1226 as_bad (_("can not do %d byte pc-relative relocation"), size);
252b5132
RH		 1227 }
1228 else
1229 {
3e73aa7c 1230 if (sign)
e5cb08ac 1231 switch (size)
3e73aa7c
JH		 1232 {
1233 case 4: return BFD_RELOC_X86_64_32S;
1234 }
1235 else
1236 switch (size)
1237 {
1238 case 1: return BFD_RELOC_8;
1239 case 2: return BFD_RELOC_16;
1240 case 4: return BFD_RELOC_32;
1241 case 8: return BFD_RELOC_64;
1242 }
1243 as_bad (_("can not do %s %d byte relocation"),
1244 sign ? "signed" : "unsigned", size);
252b5132
RH		 1245 }
1246
bfb32b52 1247 abort ();
252b5132
RH		 1248 return BFD_RELOC_NONE;
1249}
1250
47926f60
KH		 1251/* Here we decide which fixups can be adjusted to make them relative to
1252 the beginning of the section instead of the symbol. Basically we need
1253 to make sure that the dynamic relocations are done correctly, so in
1254 some cases we force the original symbol to be used. */
1255
252b5132 1256int
c0c949c7 1257tc_i386_fix_adjustable (fixP)
31312f95 1258 fixS *fixP ATTRIBUTE_UNUSED;
252b5132 1259{
6d249963 1260#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
31312f95
AM		 1261 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
1262 return 1;
1263
a161fe53
AM		 1264 /* Don't adjust pc-relative references to merge sections in 64-bit
1265 mode. */
1266 if (use_rela_relocations
1267 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1268 && fixP->fx_pcrel)
252b5132 1269 return 0;
31312f95 1270
8d01d9a9
AJ		 1271 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1272 and changed later by validate_fix. */
1273 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1274 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1275 return 0;
1276
ce8a8b2f 1277 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1278 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1279 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1280 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1281 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1282 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1283 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1284 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1285 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1286 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1287 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1288 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3e73aa7c
JH		 1289 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1290 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1291 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 1292 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1293 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1294 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
1295 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1296 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
252b5132
RH		 1297 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1298 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1299 return 0;
31312f95 1300#endif
252b5132
RH		 1301 return 1;
1302}
252b5132 1303
29b0f896 1304static int intel_float_operand PARAMS ((const char *mnemonic));
b4cac588
AM		 1305
1306static int
252b5132 1307intel_float_operand (mnemonic)
29b0f896 1308 const char *mnemonic;
252b5132 1309{
9306ca4a
JB		 1310 /* Note that the value returned is meaningful only for opcodes with (memory)
1311 operands, hence the code here is free to improperly handle opcodes that
1312 have no operands (for better performance and smaller code). */
1313
1314 if (mnemonic[0] != 'f')
1315 return 0; /* non-math */
1316
1317 switch (mnemonic[1])
1318 {
1319 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1320 the fs segment override prefix not currently handled because no
1321 call path can make opcodes without operands get here */
1322 case 'i':
1323 return 2 /* integer op */;
1324 case 'l':
1325 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1326 return 3; /* fldcw/fldenv */
1327 break;
1328 case 'n':
1329 if (mnemonic[2] != 'o' /* fnop */)
1330 return 3; /* non-waiting control op */
1331 break;
1332 case 'r':
1333 if (mnemonic[2] == 's')
1334 return 3; /* frstor/frstpm */
1335 break;
1336 case 's':
1337 if (mnemonic[2] == 'a')
1338 return 3; /* fsave */
1339 if (mnemonic[2] == 't')
1340 {
1341 switch (mnemonic[3])
1342 {
1343 case 'c': /* fstcw */
1344 case 'd': /* fstdw */
1345 case 'e': /* fstenv */
1346 case 's': /* fsts[gw] */
1347 return 3;
1348 }
1349 }
1350 break;
1351 case 'x':
1352 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1353 return 0; /* fxsave/fxrstor are not really math ops */
1354 break;
1355 }
252b5132 1356
9306ca4a 1357 return 1;
252b5132
RH		 1358}
1359
1360/* This is the guts of the machine-dependent assembler. LINE points to a
1361 machine dependent instruction. This function is supposed to emit
1362 the frags/bytes it assembles to. */
1363
1364void
1365md_assemble (line)
1366 char *line;
1367{
252b5132 1368 int j;
252b5132
RH		 1369 char mnemonic[MAX_MNEM_SIZE];
1370
47926f60 1371 /* Initialize globals. */
252b5132
RH		 1372 memset (&i, '\0', sizeof (i));
1373 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1374 i.reloc[j] = NO_RELOC;
252b5132
RH		 1375 memset (disp_expressions, '\0', sizeof (disp_expressions));
1376 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1377 save_stack_p = save_stack;
252b5132
RH		 1378
1379 /* First parse an instruction mnemonic & call i386_operand for the operands.
1380 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1381 start of a (possibly prefixed) mnemonic. */
252b5132 1382
29b0f896
AM		 1383 line = parse_insn (line, mnemonic);
1384 if (line == NULL)
1385 return;
252b5132 1386
29b0f896
AM		 1387 line = parse_operands (line, mnemonic);
1388 if (line == NULL)
1389 return;
252b5132 1390
29b0f896
AM		 1391 /* Now we've parsed the mnemonic into a set of templates, and have the
1392 operands at hand. */
1393
1394 /* All intel opcodes have reversed operands except for "bound" and
1395 "enter". We also don't reverse intersegment "jmp" and "call"
1396 instructions with 2 immediate operands so that the immediate segment
1397 precedes the offset, as it does when in AT&T mode. "enter" and the
1398 intersegment "jmp" and "call" instructions are the only ones that
1399 have two immediate operands. */
1400 if (intel_syntax && i.operands > 1
1401 && (strcmp (mnemonic, "bound") != 0)
1402 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1403 swap_operands ();
1404
1405 if (i.imm_operands)
1406 optimize_imm ();
1407
1408 if (i.disp_operands)
1409 optimize_disp ();
1410
1411 /* Next, we find a template that matches the given insn,
1412 making sure the overlap of the given operands types is consistent
1413 with the template operand types. */
252b5132 1414
29b0f896
AM		 1415 if (!match_template ())
1416 return;
252b5132 1417
cd61ebfe
AM		 1418 if (intel_syntax)
1419 {
1420 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1421 if (SYSV386_COMPAT
1422 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1423 i.tm.base_opcode ^= FloatR;
1424
1425 /* Zap movzx and movsx suffix. The suffix may have been set from
1426 "word ptr" or "byte ptr" on the source operand, but we'll use
1427 the suffix later to choose the destination register. */
1428 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 1429 {
1430 if (i.reg_operands < 2
1431 && !i.suffix
1432 && (~i.tm.opcode_modifier
1433 & (No_bSuf
1434 | No_wSuf
1435 | No_lSuf
1436 | No_sSuf
1437 | No_xSuf
1438 | No_qSuf)))
1439 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1440
1441 i.suffix = 0;
1442 }
cd61ebfe 1443 }
24eab124 1444
29b0f896
AM		 1445 if (i.tm.opcode_modifier & FWait)
1446 if (!add_prefix (FWAIT_OPCODE))
1447 return;
252b5132 1448
29b0f896
AM		 1449 /* Check string instruction segment overrides. */
1450 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1451 {
1452 if (!check_string ())
5dd0794d 1453 return;
29b0f896 1454 }
5dd0794d 1455
29b0f896
AM		 1456 if (!process_suffix ())
1457 return;
e413e4e9 1458
29b0f896
AM		 1459 /* Make still unresolved immediate matches conform to size of immediate
1460 given in i.suffix. */
1461 if (!finalize_imm ())
1462 return;
252b5132 1463
29b0f896
AM		 1464 if (i.types[0] & Imm1)
1465 i.imm_operands = 0; /* kludge for shift insns. */
1466 if (i.types[0] & ImplicitRegister)
1467 i.reg_operands--;
1468 if (i.types[1] & ImplicitRegister)
1469 i.reg_operands--;
1470 if (i.types[2] & ImplicitRegister)
1471 i.reg_operands--;
252b5132 1472
29b0f896
AM		 1473 if (i.tm.opcode_modifier & ImmExt)
1474 {
02fc3089
L		 1475 expressionS *exp;
1476
ca164297
L		 1477 if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0)
1478 {
67c1ffbe 1479 /* These Intel Prescott New Instructions have the fixed
ca164297
L		 1480 operands with an opcode suffix which is coded in the same
1481 place as an 8-bit immediate field would be. Here we check
1482 those operands and remove them afterwards. */
1483 unsigned int x;
1484
a4622f40 1485 for (x = 0; x < i.operands; x++)
ca164297
L		 1486 if (i.op[x].regs->reg_num != x)
1487 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1488 i.op[x].regs->reg_name, x + 1, i.tm.name);
1489 i.operands = 0;
1490 }
1491
29b0f896
AM		 1492 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1493 opcode suffix which is coded in the same place as an 8-bit
1494 immediate field would be. Here we fake an 8-bit immediate
1495 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1496
29b0f896 1497 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1498
29b0f896
AM		 1499 exp = &im_expressions[i.imm_operands++];
1500 i.op[i.operands].imms = exp;
1501 i.types[i.operands++] = Imm8;
1502 exp->X_op = O_constant;
1503 exp->X_add_number = i.tm.extension_opcode;
1504 i.tm.extension_opcode = None;
1505 }
252b5132 1506
29b0f896
AM		 1507 /* For insns with operands there are more diddles to do to the opcode. */
1508 if (i.operands)
1509 {
1510 if (!process_operands ())
1511 return;
1512 }
1513 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1514 {
1515 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1516 as_warn (_("translating to `%sp'"), i.tm.name);
1517 }
252b5132 1518
29b0f896
AM		 1519 /* Handle conversion of 'int $3' --> special int3 insn. */
1520 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1521 {
1522 i.tm.base_opcode = INT3_OPCODE;
1523 i.imm_operands = 0;
1524 }
252b5132 1525
29b0f896
AM		 1526 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1527 && i.op[0].disps->X_op == O_constant)
1528 {
1529 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1530 the absolute address given by the constant. Since ix86 jumps and
1531 calls are pc relative, we need to generate a reloc. */
1532 i.op[0].disps->X_add_symbol = &abs_symbol;
1533 i.op[0].disps->X_op = O_symbol;
1534 }
252b5132 1535
29b0f896
AM		 1536 if ((i.tm.opcode_modifier & Rex64) != 0)
1537 i.rex |= REX_MODE64;
252b5132 1538
29b0f896
AM		 1539 /* For 8 bit registers we need an empty rex prefix. Also if the
1540 instruction already has a prefix, we need to convert old
1541 registers to new ones. */
773f551c 1542
29b0f896
AM		 1543 if (((i.types[0] & Reg8) != 0
1544 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1545 || ((i.types[1] & Reg8) != 0
1546 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1547 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1548 && i.rex != 0))
1549 {
1550 int x;
726c5dcd 1551
29b0f896
AM		 1552 i.rex |= REX_OPCODE;
1553 for (x = 0; x < 2; x++)
1554 {
1555 /* Look for 8 bit operand that uses old registers. */
1556 if ((i.types[x] & Reg8) != 0
1557 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1558 {
29b0f896
AM		 1559 /* In case it is "hi" register, give up. */
1560 if (i.op[x].regs->reg_num > 3)
0477af35 1561 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
29b0f896 1562 i.op[x].regs->reg_name);
773f551c 1563
29b0f896
AM		 1564 /* Otherwise it is equivalent to the extended register.
1565 Since the encoding doesn't change this is merely
1566 cosmetic cleanup for debug output. */
1567
1568 i.op[x].regs = i.op[x].regs + 8;
773f551c 1569 }
29b0f896
AM		 1570 }
1571 }
773f551c 1572
29b0f896
AM		 1573 if (i.rex != 0)
1574 add_prefix (REX_OPCODE | i.rex);
1575
1576 /* We are ready to output the insn. */
1577 output_insn ();
1578}
1579
1580static char *
1581parse_insn (line, mnemonic)
1582 char *line;
1583 char *mnemonic;
1584{
1585 char *l = line;
1586 char *token_start = l;
1587 char *mnem_p;
5c6af06e
JB		 1588 int supported;
1589 const template *t;
29b0f896
AM		 1590
1591 /* Non-zero if we found a prefix only acceptable with string insns. */
1592 const char *expecting_string_instruction = NULL;
45288df1 1593
29b0f896
AM		 1594 while (1)
1595 {
1596 mnem_p = mnemonic;
1597 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1598 {
1599 mnem_p++;
1600 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1601 {
29b0f896
AM		 1602 as_bad (_("no such instruction: `%s'"), token_start);
1603 return NULL;
1604 }
1605 l++;
1606 }
1607 if (!is_space_char (*l)
1608 && *l != END_OF_INSN
e44823cf
JB		 1609 && (intel_syntax
1610 || (*l != PREFIX_SEPARATOR
1611 && *l != ',')))
29b0f896
AM		 1612 {
1613 as_bad (_("invalid character %s in mnemonic"),
1614 output_invalid (*l));
1615 return NULL;
1616 }
1617 if (token_start == l)
1618 {
e44823cf 1619 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 1620 as_bad (_("expecting prefix; got nothing"));
1621 else
1622 as_bad (_("expecting mnemonic; got nothing"));
1623 return NULL;
1624 }
45288df1 1625
29b0f896
AM		 1626 /* Look up instruction (or prefix) via hash table. */
1627 current_templates = hash_find (op_hash, mnemonic);
47926f60 1628
29b0f896
AM		 1629 if (*l != END_OF_INSN
1630 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1631 && current_templates
1632 && (current_templates->start->opcode_modifier & IsPrefix))
1633 {
1634 /* If we are in 16-bit mode, do not allow addr16 or data16.
1635 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1636 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1637 && flag_code != CODE_64BIT
1638 && (((current_templates->start->opcode_modifier & Size32) != 0)
1639 ^ (flag_code == CODE_16BIT)))
1640 {
1641 as_bad (_("redundant %s prefix"),
1642 current_templates->start->name);
1643 return NULL;
45288df1 1644 }
29b0f896
AM		 1645 /* Add prefix, checking for repeated prefixes. */
1646 switch (add_prefix (current_templates->start->base_opcode))
1647 {
1648 case 0:
1649 return NULL;
1650 case 2:
1651 expecting_string_instruction = current_templates->start->name;
1652 break;
1653 }
1654 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1655 token_start = ++l;
1656 }
1657 else
1658 break;
1659 }
45288df1 1660
29b0f896
AM		 1661 if (!current_templates)
1662 {
1663 /* See if we can get a match by trimming off a suffix. */
1664 switch (mnem_p[-1])
1665 {
1666 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 1667 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
1668 i.suffix = SHORT_MNEM_SUFFIX;
1669 else
29b0f896
AM		 1670 case BYTE_MNEM_SUFFIX:
1671 case QWORD_MNEM_SUFFIX:
1672 i.suffix = mnem_p[-1];
1673 mnem_p[-1] = '\0';
1674 current_templates = hash_find (op_hash, mnemonic);
1675 break;
1676 case SHORT_MNEM_SUFFIX:
1677 case LONG_MNEM_SUFFIX:
1678 if (!intel_syntax)
1679 {
1680 i.suffix = mnem_p[-1];
1681 mnem_p[-1] = '\0';
1682 current_templates = hash_find (op_hash, mnemonic);
1683 }
1684 break;
252b5132 1685
29b0f896
AM		 1686 /* Intel Syntax. */
1687 case 'd':
1688 if (intel_syntax)
1689 {
9306ca4a 1690 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 1691 i.suffix = SHORT_MNEM_SUFFIX;
1692 else
1693 i.suffix = LONG_MNEM_SUFFIX;
1694 mnem_p[-1] = '\0';
1695 current_templates = hash_find (op_hash, mnemonic);
1696 }
1697 break;
1698 }
1699 if (!current_templates)
1700 {
1701 as_bad (_("no such instruction: `%s'"), token_start);
1702 return NULL;
1703 }
1704 }
252b5132 1705
29b0f896
AM		 1706 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
1707 {
1708 /* Check for a branch hint. We allow ",pt" and ",pn" for
1709 predict taken and predict not taken respectively.
1710 I'm not sure that branch hints actually do anything on loop
1711 and jcxz insns (JumpByte) for current Pentium4 chips. They
1712 may work in the future and it doesn't hurt to accept them
1713 now. */
1714 if (l[0] == ',' && l[1] == 'p')
1715 {
1716 if (l[2] == 't')
1717 {
1718 if (!add_prefix (DS_PREFIX_OPCODE))
1719 return NULL;
1720 l += 3;
1721 }
1722 else if (l[2] == 'n')
1723 {
1724 if (!add_prefix (CS_PREFIX_OPCODE))
1725 return NULL;
1726 l += 3;
1727 }
1728 }
1729 }
1730 /* Any other comma loses. */
1731 if (*l == ',')
1732 {
1733 as_bad (_("invalid character %s in mnemonic"),
1734 output_invalid (*l));
1735 return NULL;
1736 }
252b5132 1737
29b0f896 1738 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 1739 supported = 0;
1740 for (t = current_templates->start; t < current_templates->end; ++t)
1741 {
1742 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
1743 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
1744 supported |= 1;
1745 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
1746 supported |= 2;
1747 }
1748 if (!(supported & 2))
1749 {
1750 as_bad (flag_code == CODE_64BIT
1751 ? _("`%s' is not supported in 64-bit mode")
1752 : _("`%s' is only supported in 64-bit mode"),
1753 current_templates->start->name);
1754 return NULL;
1755 }
1756 if (!(supported & 1))
29b0f896 1757 {
5c6af06e
JB		 1758 as_warn (_("`%s' is not supported on `%s%s'"),
1759 current_templates->start->name,
1760 cpu_arch_name,
1761 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896
AM		 1762 }
1763 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
1764 {
1765 as_warn (_("use .code16 to ensure correct addressing mode"));
1766 }
252b5132 1767
29b0f896 1768 /* Check for rep/repne without a string instruction. */
f41bbced 1769 if (expecting_string_instruction)
29b0f896 1770 {
f41bbced
JB		 1771 static templates override;
1772
1773 for (t = current_templates->start; t < current_templates->end; ++t)
1774 if (t->opcode_modifier & IsString)
1775 break;
1776 if (t >= current_templates->end)
1777 {
1778 as_bad (_("expecting string instruction after `%s'"),
1779 expecting_string_instruction);
1780 return NULL;
1781 }
1782 for (override.start = t; t < current_templates->end; ++t)
1783 if (!(t->opcode_modifier & IsString))
1784 break;
1785 override.end = t;
1786 current_templates = &override;
29b0f896 1787 }
252b5132 1788
29b0f896
AM		 1789 return l;
1790}
252b5132 1791
29b0f896
AM		 1792static char *
1793parse_operands (l, mnemonic)
1794 char *l;
1795 const char *mnemonic;
1796{
1797 char *token_start;
3138f287 1798
29b0f896
AM		 1799 /* 1 if operand is pending after ','. */
1800 unsigned int expecting_operand = 0;
252b5132 1801
29b0f896
AM		 1802 /* Non-zero if operand parens not balanced. */
1803 unsigned int paren_not_balanced;
1804
1805 while (*l != END_OF_INSN)
1806 {
1807 /* Skip optional white space before operand. */
1808 if (is_space_char (*l))
1809 ++l;
1810 if (!is_operand_char (*l) && *l != END_OF_INSN)
1811 {
1812 as_bad (_("invalid character %s before operand %d"),
1813 output_invalid (*l),
1814 i.operands + 1);
1815 return NULL;
1816 }
1817 token_start = l; /* after white space */
1818 paren_not_balanced = 0;
1819 while (paren_not_balanced || *l != ',')
1820 {
1821 if (*l == END_OF_INSN)
1822 {
1823 if (paren_not_balanced)
1824 {
1825 if (!intel_syntax)
1826 as_bad (_("unbalanced parenthesis in operand %d."),
1827 i.operands + 1);
1828 else
1829 as_bad (_("unbalanced brackets in operand %d."),
1830 i.operands + 1);
1831 return NULL;
1832 }
1833 else
1834 break; /* we are done */
1835 }
1836 else if (!is_operand_char (*l) && !is_space_char (*l))
1837 {
1838 as_bad (_("invalid character %s in operand %d"),
1839 output_invalid (*l),
1840 i.operands + 1);
1841 return NULL;
1842 }
1843 if (!intel_syntax)
1844 {
1845 if (*l == '(')
1846 ++paren_not_balanced;
1847 if (*l == ')')
1848 --paren_not_balanced;
1849 }
1850 else
1851 {
1852 if (*l == '[')
1853 ++paren_not_balanced;
1854 if (*l == ']')
1855 --paren_not_balanced;
1856 }
1857 l++;
1858 }
1859 if (l != token_start)
1860 { /* Yes, we've read in another operand. */
1861 unsigned int operand_ok;
1862 this_operand = i.operands++;
1863 if (i.operands > MAX_OPERANDS)
1864 {
1865 as_bad (_("spurious operands; (%d operands/instruction max)"),
1866 MAX_OPERANDS);
1867 return NULL;
1868 }
1869 /* Now parse operand adding info to 'i' as we go along. */
1870 END_STRING_AND_SAVE (l);
1871
1872 if (intel_syntax)
1873 operand_ok =
1874 i386_intel_operand (token_start,
1875 intel_float_operand (mnemonic));
1876 else
1877 operand_ok = i386_operand (token_start);
1878
1879 RESTORE_END_STRING (l);
1880 if (!operand_ok)
1881 return NULL;
1882 }
1883 else
1884 {
1885 if (expecting_operand)
1886 {
1887 expecting_operand_after_comma:
1888 as_bad (_("expecting operand after ','; got nothing"));
1889 return NULL;
1890 }
1891 if (*l == ',')
1892 {
1893 as_bad (_("expecting operand before ','; got nothing"));
1894 return NULL;
1895 }
1896 }
7f3f1ea2 1897
29b0f896
AM		 1898 /* Now *l must be either ',' or END_OF_INSN. */
1899 if (*l == ',')
1900 {
1901 if (*++l == END_OF_INSN)
1902 {
1903 /* Just skip it, if it's \n complain. */
1904 goto expecting_operand_after_comma;
1905 }
1906 expecting_operand = 1;
1907 }
1908 }
1909 return l;
1910}
7f3f1ea2 1911
29b0f896
AM		 1912static void
1913swap_operands ()
1914{
1915 union i386_op temp_op;
1916 unsigned int temp_type;
f86103b7 1917 enum bfd_reloc_code_real temp_reloc;
29b0f896
AM		 1918 int xchg1 = 0;
1919 int xchg2 = 0;
252b5132 1920
29b0f896
AM		 1921 if (i.operands == 2)
1922 {
1923 xchg1 = 0;
1924 xchg2 = 1;
1925 }
1926 else if (i.operands == 3)
1927 {
1928 xchg1 = 0;
1929 xchg2 = 2;
1930 }
1931 temp_type = i.types[xchg2];
1932 i.types[xchg2] = i.types[xchg1];
1933 i.types[xchg1] = temp_type;
1934 temp_op = i.op[xchg2];
1935 i.op[xchg2] = i.op[xchg1];
1936 i.op[xchg1] = temp_op;
1937 temp_reloc = i.reloc[xchg2];
1938 i.reloc[xchg2] = i.reloc[xchg1];
1939 i.reloc[xchg1] = temp_reloc;
1940
1941 if (i.mem_operands == 2)
1942 {
1943 const seg_entry *temp_seg;
1944 temp_seg = i.seg[0];
1945 i.seg[0] = i.seg[1];
1946 i.seg[1] = temp_seg;
1947 }
1948}
252b5132 1949
29b0f896
AM		 1950/* Try to ensure constant immediates are represented in the smallest
1951 opcode possible. */
1952static void
1953optimize_imm ()
1954{
1955 char guess_suffix = 0;
1956 int op;
252b5132 1957
29b0f896
AM		 1958 if (i.suffix)
1959 guess_suffix = i.suffix;
1960 else if (i.reg_operands)
1961 {
1962 /* Figure out a suffix from the last register operand specified.
1963 We can't do this properly yet, ie. excluding InOutPortReg,
1964 but the following works for instructions with immediates.
1965 In any case, we can't set i.suffix yet. */
1966 for (op = i.operands; --op >= 0;)
1967 if (i.types[op] & Reg)
252b5132 1968 {
29b0f896
AM		 1969 if (i.types[op] & Reg8)
1970 guess_suffix = BYTE_MNEM_SUFFIX;
1971 else if (i.types[op] & Reg16)
1972 guess_suffix = WORD_MNEM_SUFFIX;
1973 else if (i.types[op] & Reg32)
1974 guess_suffix = LONG_MNEM_SUFFIX;
1975 else if (i.types[op] & Reg64)
1976 guess_suffix = QWORD_MNEM_SUFFIX;
1977 break;
252b5132 1978 }
29b0f896
AM		 1979 }
1980 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
1981 guess_suffix = WORD_MNEM_SUFFIX;
1982
1983 for (op = i.operands; --op >= 0;)
1984 if (i.types[op] & Imm)
1985 {
1986 switch (i.op[op].imms->X_op)
252b5132 1987 {
29b0f896
AM		 1988 case O_constant:
1989 /* If a suffix is given, this operand may be shortened. */
1990 switch (guess_suffix)
252b5132 1991 {
29b0f896
AM		 1992 case LONG_MNEM_SUFFIX:
1993 i.types[op] |= Imm32 | Imm64;
1994 break;
1995 case WORD_MNEM_SUFFIX:
1996 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
1997 break;
1998 case BYTE_MNEM_SUFFIX:
1999 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2000 break;
252b5132 2001 }
252b5132 2002
29b0f896
AM		 2003 /* If this operand is at most 16 bits, convert it
2004 to a signed 16 bit number before trying to see
2005 whether it will fit in an even smaller size.
2006 This allows a 16-bit operand such as $0xffe0 to
2007 be recognised as within Imm8S range. */
2008 if ((i.types[op] & Imm16)
2009 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2010 {
29b0f896
AM		 2011 i.op[op].imms->X_add_number =
2012 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2013 }
2014 if ((i.types[op] & Imm32)
2015 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2016 == 0))
2017 {
2018 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2019 ^ ((offsetT) 1 << 31))
2020 - ((offsetT) 1 << 31));
2021 }
2022 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 2023
29b0f896
AM		 2024 /* We must avoid matching of Imm32 templates when 64bit
2025 only immediate is available. */
2026 if (guess_suffix == QWORD_MNEM_SUFFIX)
2027 i.types[op] &= ~Imm32;
2028 break;
252b5132 2029
29b0f896
AM		 2030 case O_absent:
2031 case O_register:
2032 abort ();
2033
2034 /* Symbols and expressions. */
2035 default:
2036 /* Convert symbolic operand to proper sizes for matching. */
2037 switch (guess_suffix)
2038 {
2039 case QWORD_MNEM_SUFFIX:
2040 i.types[op] = Imm64 | Imm32S;
2041 break;
2042 case LONG_MNEM_SUFFIX:
20f0a1fc 2043 i.types[op] = Imm32;
29b0f896
AM		 2044 break;
2045 case WORD_MNEM_SUFFIX:
20f0a1fc 2046 i.types[op] = Imm16;
29b0f896
AM		 2047 break;
2048 case BYTE_MNEM_SUFFIX:
20f0a1fc 2049 i.types[op] = Imm8 | Imm8S;
29b0f896 2050 break;
252b5132 2051 }
29b0f896 2052 break;
252b5132 2053 }
29b0f896
AM		 2054 }
2055}
47926f60 2056
29b0f896
AM		 2057/* Try to use the smallest displacement type too. */
2058static void
2059optimize_disp ()
2060{
2061 int op;
3e73aa7c 2062
29b0f896
AM		 2063 for (op = i.operands; --op >= 0;)
2064 if ((i.types[op] & Disp) && i.op[op].disps->X_op == O_constant)
252b5132 2065 {
29b0f896
AM		 2066 offsetT disp = i.op[op].disps->X_add_number;
2067
2068 if (i.types[op] & Disp16)
252b5132 2069 {
29b0f896
AM		 2070 /* We know this operand is at most 16 bits, so
2071 convert to a signed 16 bit number before trying
2072 to see whether it will fit in an even smaller
2073 size. */
2074
2075 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
252b5132 2076 }
29b0f896 2077 else if (i.types[op] & Disp32)
252b5132 2078 {
29b0f896
AM		 2079 /* We know this operand is at most 32 bits, so convert to a
2080 signed 32 bit number before trying to see whether it will
2081 fit in an even smaller size. */
2082 disp &= (((offsetT) 2 << 31) - 1);
2083 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 2084 }
34d9ee9e
JB		 2085 if (!disp && (i.types[op] & BaseIndex))
2086 {
2087 i.types[op] &= ~Disp;
2088 i.op[op].disps = 0;
2089 i.disp_operands--;
2090 }
2091 else if (flag_code == CODE_64BIT)
252b5132 2092 {
29b0f896
AM		 2093 if (fits_in_signed_long (disp))
2094 i.types[op] |= Disp32S;
2095 if (fits_in_unsigned_long (disp))
2096 i.types[op] |= Disp32;
252b5132 2097 }
29b0f896
AM		 2098 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2099 && fits_in_signed_byte (disp))
2100 i.types[op] |= Disp8;
252b5132 2101 }
29b0f896
AM		 2102}
2103
2104static int
2105match_template ()
2106{
2107 /* Points to template once we've found it. */
2108 const template *t;
2109 unsigned int overlap0, overlap1, overlap2;
2110 unsigned int found_reverse_match;
2111 int suffix_check;
2112
2113#define MATCH(overlap, given, template) \
2114 ((overlap & ~JumpAbsolute) \
2115 && (((given) & (BaseIndex | JumpAbsolute)) \
2116 == ((overlap) & (BaseIndex | JumpAbsolute))))
2117
2118 /* If given types r0 and r1 are registers they must be of the same type
2119 unless the expected operand type register overlap is null.
2120 Note that Acc in a template matches every size of reg. */
2121#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2122 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2123 || ((g0) & Reg) == ((g1) & Reg) \
2124 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2125
2126 overlap0 = 0;
2127 overlap1 = 0;
2128 overlap2 = 0;
2129 found_reverse_match = 0;
2130 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2131 ? No_bSuf
2132 : (i.suffix == WORD_MNEM_SUFFIX
2133 ? No_wSuf
2134 : (i.suffix == SHORT_MNEM_SUFFIX
2135 ? No_sSuf
2136 : (i.suffix == LONG_MNEM_SUFFIX
2137 ? No_lSuf
2138 : (i.suffix == QWORD_MNEM_SUFFIX
2139 ? No_qSuf
2140 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2141 ? No_xSuf : 0))))));
2142
20f0a1fc
NC		 2143 t = current_templates->start;
2144 if (i.suffix == QWORD_MNEM_SUFFIX
2145 && flag_code != CODE_64BIT
9306ca4a
JB		 2146 && (intel_syntax
2147 ? !(t->opcode_modifier & IgnoreSize)
2148 && !intel_float_operand (t->name)
2149 : intel_float_operand (t->name) != 2)
20f0a1fc
NC		 2150 && (!(t->operand_types[0] & (RegMMX | RegXMM))
2151 || !(t->operand_types[t->operands > 1] & (RegMMX | RegXMM)))
2152 && (t->base_opcode != 0x0fc7
2153 || t->extension_opcode != 1 /* cmpxchg8b */))
2154 t = current_templates->end;
2155 for (; t < current_templates->end; t++)
29b0f896
AM		 2156 {
2157 /* Must have right number of operands. */
2158 if (i.operands != t->operands)
2159 continue;
2160
2161 /* Check the suffix, except for some instructions in intel mode. */
2162 if ((t->opcode_modifier & suffix_check)
2163 && !(intel_syntax
9306ca4a 2164 && (t->opcode_modifier & IgnoreSize)))
29b0f896
AM		 2165 continue;
2166
2167 /* Do not verify operands when there are none. */
2168 else if (!t->operands)
2169 {
2170 if (t->cpu_flags & ~cpu_arch_flags)
2171 continue;
2172 /* We've found a match; break out of loop. */
2173 break;
2174 }
252b5132 2175
29b0f896
AM		 2176 overlap0 = i.types[0] & t->operand_types[0];
2177 switch (t->operands)
2178 {
2179 case 1:
2180 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
2181 continue;
2182 break;
2183 case 2:
2184 case 3:
2185 overlap1 = i.types[1] & t->operand_types[1];
2186 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
2187 || !MATCH (overlap1, i.types[1], t->operand_types[1])
2188 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2189 t->operand_types[0],
2190 overlap1, i.types[1],
2191 t->operand_types[1]))
2192 {
2193 /* Check if other direction is valid ... */
2194 if ((t->opcode_modifier & (D | FloatD)) == 0)
2195 continue;
2196
2197 /* Try reversing direction of operands. */
2198 overlap0 = i.types[0] & t->operand_types[1];
2199 overlap1 = i.types[1] & t->operand_types[0];
2200 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
2201 || !MATCH (overlap1, i.types[1], t->operand_types[0])
2202 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2203 t->operand_types[1],
2204 overlap1, i.types[1],
2205 t->operand_types[0]))
2206 {
2207 /* Does not match either direction. */
2208 continue;
2209 }
2210 /* found_reverse_match holds which of D or FloatDR
2211 we've found. */
2212 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2213 }
2214 /* Found a forward 2 operand match here. */
2215 else if (t->operands == 3)
2216 {
2217 /* Here we make use of the fact that there are no
2218 reverse match 3 operand instructions, and all 3
2219 operand instructions only need to be checked for
2220 register consistency between operands 2 and 3. */
2221 overlap2 = i.types[2] & t->operand_types[2];
2222 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
2223 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2224 t->operand_types[1],
2225 overlap2, i.types[2],
2226 t->operand_types[2]))
2227
2228 continue;
2229 }
2230 /* Found either forward/reverse 2 or 3 operand match here:
2231 slip through to break. */
2232 }
2233 if (t->cpu_flags & ~cpu_arch_flags)
2234 {
2235 found_reverse_match = 0;
2236 continue;
2237 }
2238 /* We've found a match; break out of loop. */
2239 break;
2240 }
2241
2242 if (t == current_templates->end)
2243 {
2244 /* We found no match. */
2245 as_bad (_("suffix or operands invalid for `%s'"),
2246 current_templates->start->name);
2247 return 0;
2248 }
252b5132 2249
29b0f896
AM		 2250 if (!quiet_warnings)
2251 {
2252 if (!intel_syntax
2253 && ((i.types[0] & JumpAbsolute)
2254 != (t->operand_types[0] & JumpAbsolute)))
2255 {
2256 as_warn (_("indirect %s without `*'"), t->name);
2257 }
2258
2259 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2260 == (IsPrefix | IgnoreSize))
2261 {
2262 /* Warn them that a data or address size prefix doesn't
2263 affect assembly of the next line of code. */
2264 as_warn (_("stand-alone `%s' prefix"), t->name);
2265 }
2266 }
2267
2268 /* Copy the template we found. */
2269 i.tm = *t;
2270 if (found_reverse_match)
2271 {
2272 /* If we found a reverse match we must alter the opcode
2273 direction bit. found_reverse_match holds bits to change
2274 (different for int & float insns). */
2275
2276 i.tm.base_opcode ^= found_reverse_match;
2277
2278 i.tm.operand_types[0] = t->operand_types[1];
2279 i.tm.operand_types[1] = t->operand_types[0];
2280 }
2281
2282 return 1;
2283}
2284
2285static int
2286check_string ()
2287{
2288 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2289 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2290 {
2291 if (i.seg[0] != NULL && i.seg[0] != &es)
2292 {
2293 as_bad (_("`%s' operand %d must use `%%es' segment"),
2294 i.tm.name,
2295 mem_op + 1);
2296 return 0;
2297 }
2298 /* There's only ever one segment override allowed per instruction.
2299 This instruction possibly has a legal segment override on the
2300 second operand, so copy the segment to where non-string
2301 instructions store it, allowing common code. */
2302 i.seg[0] = i.seg[1];
2303 }
2304 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2305 {
2306 if (i.seg[1] != NULL && i.seg[1] != &es)
2307 {
2308 as_bad (_("`%s' operand %d must use `%%es' segment"),
2309 i.tm.name,
2310 mem_op + 2);
2311 return 0;
2312 }
2313 }
2314 return 1;
2315}
2316
2317static int
543613e9 2318process_suffix (void)
29b0f896
AM		 2319{
2320 /* If matched instruction specifies an explicit instruction mnemonic
2321 suffix, use it. */
2322 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2323 {
2324 if (i.tm.opcode_modifier & Size16)
2325 i.suffix = WORD_MNEM_SUFFIX;
2326 else if (i.tm.opcode_modifier & Size64)
2327 i.suffix = QWORD_MNEM_SUFFIX;
2328 else
2329 i.suffix = LONG_MNEM_SUFFIX;
2330 }
2331 else if (i.reg_operands)
2332 {
2333 /* If there's no instruction mnemonic suffix we try to invent one
2334 based on register operands. */
2335 if (!i.suffix)
2336 {
2337 /* We take i.suffix from the last register operand specified,
2338 Destination register type is more significant than source
2339 register type. */
2340 int op;
543613e9 2341
29b0f896
AM		 2342 for (op = i.operands; --op >= 0;)
2343 if ((i.types[op] & Reg)
2344 && !(i.tm.operand_types[op] & InOutPortReg))
2345 {
2346 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2347 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2348 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2349 LONG_MNEM_SUFFIX);
2350 break;
2351 }
2352 }
2353 else if (i.suffix == BYTE_MNEM_SUFFIX)
2354 {
2355 if (!check_byte_reg ())
2356 return 0;
2357 }
2358 else if (i.suffix == LONG_MNEM_SUFFIX)
2359 {
2360 if (!check_long_reg ())
2361 return 0;
2362 }
2363 else if (i.suffix == QWORD_MNEM_SUFFIX)
2364 {
2365 if (!check_qword_reg ())
2366 return 0;
2367 }
2368 else if (i.suffix == WORD_MNEM_SUFFIX)
2369 {
2370 if (!check_word_reg ())
2371 return 0;
2372 }
2373 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2374 /* Do nothing if the instruction is going to ignore the prefix. */
2375 ;
2376 else
2377 abort ();
2378 }
9306ca4a
JB		 2379 else if ((i.tm.opcode_modifier & DefaultSize)
2380 && !i.suffix
2381 /* exclude fldenv/frstor/fsave/fstenv */
2382 && (i.tm.opcode_modifier & No_sSuf))
29b0f896
AM		 2383 {
2384 i.suffix = stackop_size;
2385 }
9306ca4a
JB		 2386 else if (intel_syntax
2387 && !i.suffix
2388 && ((i.tm.operand_types[0] & JumpAbsolute)
2389 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2390 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2391 && i.tm.extension_opcode <= 3)))
2392 {
2393 switch (flag_code)
2394 {
2395 case CODE_64BIT:
2396 if (!(i.tm.opcode_modifier & No_qSuf))
2397 {
2398 i.suffix = QWORD_MNEM_SUFFIX;
2399 break;
2400 }
2401 case CODE_32BIT:
2402 if (!(i.tm.opcode_modifier & No_lSuf))
2403 i.suffix = LONG_MNEM_SUFFIX;
2404 break;
2405 case CODE_16BIT:
2406 if (!(i.tm.opcode_modifier & No_wSuf))
2407 i.suffix = WORD_MNEM_SUFFIX;
2408 break;
2409 }
2410 }
252b5132 2411
9306ca4a 2412 if (!i.suffix)
29b0f896 2413 {
9306ca4a
JB		 2414 if (!intel_syntax)
2415 {
2416 if (i.tm.opcode_modifier & W)
2417 {
2418 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2419 return 0;
2420 }
2421 }
2422 else
2423 {
2424 unsigned int suffixes = ~i.tm.opcode_modifier
2425 & (No_bSuf
2426 | No_wSuf
2427 | No_lSuf
2428 | No_sSuf
2429 | No_xSuf
2430 | No_qSuf);
2431
2432 if ((i.tm.opcode_modifier & W)
2433 || ((suffixes & (suffixes - 1))
2434 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2435 {
2436 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2437 return 0;
2438 }
2439 }
29b0f896 2440 }
252b5132 2441
9306ca4a
JB		 2442 /* Change the opcode based on the operand size given by i.suffix;
2443 We don't need to change things for byte insns. */
2444
29b0f896
AM		 2445 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2446 {
2447 /* It's not a byte, select word/dword operation. */
2448 if (i.tm.opcode_modifier & W)
2449 {
2450 if (i.tm.opcode_modifier & ShortForm)
2451 i.tm.base_opcode |= 8;
2452 else
2453 i.tm.base_opcode |= 1;
2454 }
0f3f3d8b 2455
29b0f896
AM		 2456 /* Now select between word & dword operations via the operand
2457 size prefix, except for instructions that will ignore this
2458 prefix anyway. */
2459 if (i.suffix != QWORD_MNEM_SUFFIX
9306ca4a
JB		 2460 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2461 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
9146926a
AM		 2462 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2463 || (flag_code == CODE_64BIT
2464 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 2465 {
2466 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 2467
29b0f896
AM		 2468 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2469 prefix = ADDR_PREFIX_OPCODE;
252b5132 2470
29b0f896
AM		 2471 if (!add_prefix (prefix))
2472 return 0;
24eab124 2473 }
252b5132 2474
29b0f896
AM		 2475 /* Set mode64 for an operand. */
2476 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 2477 && flag_code == CODE_64BIT
29b0f896 2478 && (i.tm.opcode_modifier & NoRex64) == 0)
9146926a 2479 i.rex |= REX_MODE64;
3e73aa7c 2480
29b0f896
AM		 2481 /* Size floating point instruction. */
2482 if (i.suffix == LONG_MNEM_SUFFIX)
543613e9
NC		 2483 if (i.tm.opcode_modifier & FloatMF)
2484 i.tm.base_opcode ^= 4;
29b0f896 2485 }
7ecd2f8b 2486
29b0f896
AM		 2487 return 1;
2488}
3e73aa7c 2489
29b0f896 2490static int
543613e9 2491check_byte_reg (void)
29b0f896
AM		 2492{
2493 int op;
543613e9 2494
29b0f896
AM		 2495 for (op = i.operands; --op >= 0;)
2496 {
2497 /* If this is an eight bit register, it's OK. If it's the 16 or
2498 32 bit version of an eight bit register, we will just use the
2499 low portion, and that's OK too. */
2500 if (i.types[op] & Reg8)
2501 continue;
2502
2503 /* movzx and movsx should not generate this warning. */
2504 if (intel_syntax
2505 && (i.tm.base_opcode == 0xfb7
2506 || i.tm.base_opcode == 0xfb6
2507 || i.tm.base_opcode == 0x63
2508 || i.tm.base_opcode == 0xfbe
2509 || i.tm.base_opcode == 0xfbf))
2510 continue;
2511
65ec77d2 2512 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
29b0f896
AM		 2513 {
2514 /* Prohibit these changes in the 64bit mode, since the
2515 lowering is more complicated. */
2516 if (flag_code == CODE_64BIT
2517 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2518 {
0f3f3d8b 2519 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2520 i.op[op].regs->reg_name,
2521 i.suffix);
2522 return 0;
2523 }
2524#if REGISTER_WARNINGS
2525 if (!quiet_warnings
2526 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2527 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2528 (i.op[op].regs + (i.types[op] & Reg16
2529 ? REGNAM_AL - REGNAM_AX
2530 : REGNAM_AL - REGNAM_EAX))->reg_name,
2531 i.op[op].regs->reg_name,
2532 i.suffix);
2533#endif
2534 continue;
2535 }
2536 /* Any other register is bad. */
2537 if (i.types[op] & (Reg | RegMMX | RegXMM
2538 | SReg2 | SReg3
2539 | Control | Debug | Test
2540 | FloatReg | FloatAcc))
2541 {
2542 as_bad (_("`%%%s' not allowed with `%s%c'"),
2543 i.op[op].regs->reg_name,
2544 i.tm.name,
2545 i.suffix);
2546 return 0;
2547 }
2548 }
2549 return 1;
2550}
2551
2552static int
2553check_long_reg ()
2554{
2555 int op;
2556
2557 for (op = i.operands; --op >= 0;)
2558 /* Reject eight bit registers, except where the template requires
2559 them. (eg. movzb) */
2560 if ((i.types[op] & Reg8) != 0
2561 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2562 {
2563 as_bad (_("`%%%s' not allowed with `%s%c'"),
2564 i.op[op].regs->reg_name,
2565 i.tm.name,
2566 i.suffix);
2567 return 0;
2568 }
2569 /* Warn if the e prefix on a general reg is missing. */
2570 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2571 && (i.types[op] & Reg16) != 0
2572 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2573 {
2574 /* Prohibit these changes in the 64bit mode, since the
2575 lowering is more complicated. */
2576 if (flag_code == CODE_64BIT)
252b5132 2577 {
0f3f3d8b 2578 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2579 i.op[op].regs->reg_name,
2580 i.suffix);
2581 return 0;
252b5132 2582 }
29b0f896
AM		 2583#if REGISTER_WARNINGS
2584 else
2585 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2586 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
2587 i.op[op].regs->reg_name,
2588 i.suffix);
2589#endif
252b5132 2590 }
29b0f896
AM		 2591 /* Warn if the r prefix on a general reg is missing. */
2592 else if ((i.types[op] & Reg64) != 0
2593 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 2594 {
0f3f3d8b 2595 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2596 i.op[op].regs->reg_name,
2597 i.suffix);
2598 return 0;
2599 }
2600 return 1;
2601}
252b5132 2602
29b0f896
AM		 2603static int
2604check_qword_reg ()
2605{
2606 int op;
252b5132 2607
29b0f896
AM		 2608 for (op = i.operands; --op >= 0; )
2609 /* Reject eight bit registers, except where the template requires
2610 them. (eg. movzb) */
2611 if ((i.types[op] & Reg8) != 0
2612 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2613 {
2614 as_bad (_("`%%%s' not allowed with `%s%c'"),
2615 i.op[op].regs->reg_name,
2616 i.tm.name,
2617 i.suffix);
2618 return 0;
2619 }
2620 /* Warn if the e prefix on a general reg is missing. */
2621 else if (((i.types[op] & Reg16) != 0
2622 || (i.types[op] & Reg32) != 0)
2623 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2624 {
2625 /* Prohibit these changes in the 64bit mode, since the
2626 lowering is more complicated. */
0f3f3d8b 2627 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2628 i.op[op].regs->reg_name,
2629 i.suffix);
2630 return 0;
252b5132 2631 }
29b0f896
AM		 2632 return 1;
2633}
252b5132 2634
29b0f896
AM		 2635static int
2636check_word_reg ()
2637{
2638 int op;
2639 for (op = i.operands; --op >= 0;)
2640 /* Reject eight bit registers, except where the template requires
2641 them. (eg. movzb) */
2642 if ((i.types[op] & Reg8) != 0
2643 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2644 {
2645 as_bad (_("`%%%s' not allowed with `%s%c'"),
2646 i.op[op].regs->reg_name,
2647 i.tm.name,
2648 i.suffix);
2649 return 0;
2650 }
2651 /* Warn if the e prefix on a general reg is present. */
2652 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2653 && (i.types[op] & Reg32) != 0
2654 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 2655 {
29b0f896
AM		 2656 /* Prohibit these changes in the 64bit mode, since the
2657 lowering is more complicated. */
2658 if (flag_code == CODE_64BIT)
252b5132 2659 {
0f3f3d8b 2660 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2661 i.op[op].regs->reg_name,
2662 i.suffix);
2663 return 0;
252b5132 2664 }
29b0f896
AM		 2665 else
2666#if REGISTER_WARNINGS
2667 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2668 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
2669 i.op[op].regs->reg_name,
2670 i.suffix);
2671#endif
2672 }
2673 return 1;
2674}
252b5132 2675
29b0f896
AM		 2676static int
2677finalize_imm ()
2678{
2679 unsigned int overlap0, overlap1, overlap2;
2680
2681 overlap0 = i.types[0] & i.tm.operand_types[0];
20f0a1fc 2682 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
29b0f896
AM		 2683 && overlap0 != Imm8 && overlap0 != Imm8S
2684 && overlap0 != Imm16 && overlap0 != Imm32S
2685 && overlap0 != Imm32 && overlap0 != Imm64)
2686 {
2687 if (i.suffix)
2688 {
2689 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
2690 ? Imm8 | Imm8S
2691 : (i.suffix == WORD_MNEM_SUFFIX
2692 ? Imm16
2693 : (i.suffix == QWORD_MNEM_SUFFIX
2694 ? Imm64 | Imm32S
2695 : Imm32)));
2696 }
2697 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2698 || overlap0 == (Imm16 | Imm32)
2699 || overlap0 == (Imm16 | Imm32S))
2700 {
2701 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2702 ? Imm16 : Imm32S);
2703 }
2704 if (overlap0 != Imm8 && overlap0 != Imm8S
2705 && overlap0 != Imm16 && overlap0 != Imm32S
2706 && overlap0 != Imm32 && overlap0 != Imm64)
2707 {
2708 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2709 return 0;
2710 }
2711 }
2712 i.types[0] = overlap0;
2713
2714 overlap1 = i.types[1] & i.tm.operand_types[1];
37edbb65 2715 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
29b0f896
AM		 2716 && overlap1 != Imm8 && overlap1 != Imm8S
2717 && overlap1 != Imm16 && overlap1 != Imm32S
2718 && overlap1 != Imm32 && overlap1 != Imm64)
2719 {
2720 if (i.suffix)
2721 {
2722 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
2723 ? Imm8 | Imm8S
2724 : (i.suffix == WORD_MNEM_SUFFIX
2725 ? Imm16
2726 : (i.suffix == QWORD_MNEM_SUFFIX
2727 ? Imm64 | Imm32S
2728 : Imm32)));
2729 }
2730 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2731 || overlap1 == (Imm16 | Imm32)
2732 || overlap1 == (Imm16 | Imm32S))
2733 {
2734 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2735 ? Imm16 : Imm32S);
2736 }
2737 if (overlap1 != Imm8 && overlap1 != Imm8S
2738 && overlap1 != Imm16 && overlap1 != Imm32S
2739 && overlap1 != Imm32 && overlap1 != Imm64)
2740 {
2741 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
2742 return 0;
2743 }
2744 }
2745 i.types[1] = overlap1;
2746
2747 overlap2 = i.types[2] & i.tm.operand_types[2];
2748 assert ((overlap2 & Imm) == 0);
2749 i.types[2] = overlap2;
2750
2751 return 1;
2752}
2753
2754static int
2755process_operands ()
2756{
2757 /* Default segment register this instruction will use for memory
2758 accesses. 0 means unknown. This is only for optimizing out
2759 unnecessary segment overrides. */
2760 const seg_entry *default_seg = 0;
2761
2762 /* The imul $imm, %reg instruction is converted into
2763 imul $imm, %reg, %reg, and the clr %reg instruction
2764 is converted into xor %reg, %reg. */
2765 if (i.tm.opcode_modifier & regKludge)
2766 {
2767 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
2768 /* Pretend we saw the extra register operand. */
2769 assert (i.op[first_reg_op + 1].regs == 0);
2770 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2771 i.types[first_reg_op + 1] = i.types[first_reg_op];
2772 i.reg_operands = 2;
2773 }
2774
2775 if (i.tm.opcode_modifier & ShortForm)
2776 {
2777 /* The register or float register operand is in operand 0 or 1. */
2778 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2779 /* Register goes in low 3 bits of opcode. */
2780 i.tm.base_opcode |= i.op[op].regs->reg_num;
2781 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2782 i.rex |= REX_EXTZ;
2783 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2784 {
2785 /* Warn about some common errors, but press on regardless.
2786 The first case can be generated by gcc (<= 2.8.1). */
2787 if (i.operands == 2)
2788 {
2789 /* Reversed arguments on faddp, fsubp, etc. */
2790 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
2791 i.op[1].regs->reg_name,
2792 i.op[0].regs->reg_name);
2793 }
2794 else
2795 {
2796 /* Extraneous `l' suffix on fp insn. */
2797 as_warn (_("translating to `%s %%%s'"), i.tm.name,
2798 i.op[0].regs->reg_name);
2799 }
2800 }
2801 }
2802 else if (i.tm.opcode_modifier & Modrm)
2803 {
2804 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 2805 must be put into the modrm byte). Now, we make the modrm and
2806 index base bytes based on all the info we've collected. */
29b0f896
AM		 2807
2808 default_seg = build_modrm_byte ();
2809 }
2810 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2811 {
2812 if (i.tm.base_opcode == POP_SEG_SHORT
2813 && i.op[0].regs->reg_num == 1)
2814 {
2815 as_bad (_("you can't `pop %%cs'"));
2816 return 0;
2817 }
2818 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2819 if ((i.op[0].regs->reg_flags & RegRex) != 0)
2820 i.rex |= REX_EXTZ;
2821 }
2822 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
2823 {
2824 default_seg = &ds;
2825 }
2826 else if ((i.tm.opcode_modifier & IsString) != 0)
2827 {
2828 /* For the string instructions that allow a segment override
2829 on one of their operands, the default segment is ds. */
2830 default_seg = &ds;
2831 }
2832
52271982
AM		 2833 if (i.tm.base_opcode == 0x8d /* lea */ && i.seg[0] && !quiet_warnings)
2834 as_warn (_("segment override on `lea' is ineffectual"));
2835
2836 /* If a segment was explicitly specified, and the specified segment
2837 is not the default, use an opcode prefix to select it. If we
2838 never figured out what the default segment is, then default_seg
2839 will be zero at this point, and the specified segment prefix will
2840 always be used. */
29b0f896
AM		 2841 if ((i.seg[0]) && (i.seg[0] != default_seg))
2842 {
2843 if (!add_prefix (i.seg[0]->seg_prefix))
2844 return 0;
2845 }
2846 return 1;
2847}
2848
2849static const seg_entry *
2850build_modrm_byte ()
2851{
2852 const seg_entry *default_seg = 0;
2853
2854 /* i.reg_operands MUST be the number of real register operands;
2855 implicit registers do not count. */
2856 if (i.reg_operands == 2)
2857 {
2858 unsigned int source, dest;
2859 source = ((i.types[0]
2860 & (Reg | RegMMX | RegXMM
2861 | SReg2 | SReg3
2862 | Control | Debug | Test))
2863 ? 0 : 1);
2864 dest = source + 1;
2865
2866 i.rm.mode = 3;
2867 /* One of the register operands will be encoded in the i.tm.reg
2868 field, the other in the combined i.tm.mode and i.tm.regmem
2869 fields. If no form of this instruction supports a memory
2870 destination operand, then we assume the source operand may
2871 sometimes be a memory operand and so we need to store the
2872 destination in the i.rm.reg field. */
2873 if ((i.tm.operand_types[dest] & AnyMem) == 0)
2874 {
2875 i.rm.reg = i.op[dest].regs->reg_num;
2876 i.rm.regmem = i.op[source].regs->reg_num;
2877 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2878 i.rex |= REX_EXTX;
2879 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2880 i.rex |= REX_EXTZ;
2881 }
2882 else
2883 {
2884 i.rm.reg = i.op[source].regs->reg_num;
2885 i.rm.regmem = i.op[dest].regs->reg_num;
2886 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2887 i.rex |= REX_EXTZ;
2888 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2889 i.rex |= REX_EXTX;
2890 }
c4a530c5
JB		 2891 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
2892 {
2893 if (!((i.types[0] | i.types[1]) & Control))
2894 abort ();
2895 i.rex &= ~(REX_EXTX | REX_EXTZ);
2896 add_prefix (LOCK_PREFIX_OPCODE);
2897 }
29b0f896
AM		 2898 }
2899 else
2900 { /* If it's not 2 reg operands... */
2901 if (i.mem_operands)
2902 {
2903 unsigned int fake_zero_displacement = 0;
2904 unsigned int op = ((i.types[0] & AnyMem)
2905 ? 0
2906 : (i.types[1] & AnyMem) ? 1 : 2);
2907
2908 default_seg = &ds;
2909
2910 if (i.base_reg == 0)
2911 {
2912 i.rm.mode = 0;
2913 if (!i.disp_operands)
2914 fake_zero_displacement = 1;
2915 if (i.index_reg == 0)
2916 {
2917 /* Operand is just <disp> */
20f0a1fc 2918 if (flag_code == CODE_64BIT)
29b0f896
AM		 2919 {
2920 /* 64bit mode overwrites the 32bit absolute
2921 addressing by RIP relative addressing and
2922 absolute addressing is encoded by one of the
2923 redundant SIB forms. */
2924 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2925 i.sib.base = NO_BASE_REGISTER;
2926 i.sib.index = NO_INDEX_REGISTER;
20f0a1fc
NC		 2927 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) ? Disp32S : Disp32);
2928 }
2929 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
2930 {
2931 i.rm.regmem = NO_BASE_REGISTER_16;
2932 i.types[op] = Disp16;
2933 }
2934 else
2935 {
2936 i.rm.regmem = NO_BASE_REGISTER;
2937 i.types[op] = Disp32;
29b0f896
AM		 2938 }
2939 }
2940 else /* !i.base_reg && i.index_reg */
2941 {
2942 i.sib.index = i.index_reg->reg_num;
2943 i.sib.base = NO_BASE_REGISTER;
2944 i.sib.scale = i.log2_scale_factor;
2945 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2946 i.types[op] &= ~Disp;
2947 if (flag_code != CODE_64BIT)
2948 i.types[op] |= Disp32; /* Must be 32 bit */
2949 else
2950 i.types[op] |= Disp32S;
2951 if ((i.index_reg->reg_flags & RegRex) != 0)
2952 i.rex |= REX_EXTY;
2953 }
2954 }
2955 /* RIP addressing for 64bit mode. */
2956 else if (i.base_reg->reg_type == BaseIndex)
2957 {
2958 i.rm.regmem = NO_BASE_REGISTER;
20f0a1fc 2959 i.types[op] &= ~ Disp;
29b0f896
AM		 2960 i.types[op] |= Disp32S;
2961 i.flags[op] = Operand_PCrel;
20f0a1fc
NC		 2962 if (! i.disp_operands)
2963 fake_zero_displacement = 1;
29b0f896
AM		 2964 }
2965 else if (i.base_reg->reg_type & Reg16)
2966 {
2967 switch (i.base_reg->reg_num)
2968 {
2969 case 3: /* (%bx) */
2970 if (i.index_reg == 0)
2971 i.rm.regmem = 7;
2972 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2973 i.rm.regmem = i.index_reg->reg_num - 6;
2974 break;
2975 case 5: /* (%bp) */
2976 default_seg = &ss;
2977 if (i.index_reg == 0)
2978 {
2979 i.rm.regmem = 6;
2980 if ((i.types[op] & Disp) == 0)
2981 {
2982 /* fake (%bp) into 0(%bp) */
2983 i.types[op] |= Disp8;
252b5132 2984 fake_zero_displacement = 1;
29b0f896
AM		 2985 }
2986 }
2987 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2988 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
2989 break;
2990 default: /* (%si) -> 4 or (%di) -> 5 */
2991 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
2992 }
2993 i.rm.mode = mode_from_disp_size (i.types[op]);
2994 }
2995 else /* i.base_reg and 32/64 bit mode */
2996 {
2997 if (flag_code == CODE_64BIT
2998 && (i.types[op] & Disp))
20f0a1fc
NC		 2999 i.types[op] = (i.types[op] & Disp8) | (i.prefix[ADDR_PREFIX] == 0 ? Disp32S : Disp32);
3000
29b0f896
AM		 3001 i.rm.regmem = i.base_reg->reg_num;
3002 if ((i.base_reg->reg_flags & RegRex) != 0)
3003 i.rex |= REX_EXTZ;
3004 i.sib.base = i.base_reg->reg_num;
3005 /* x86-64 ignores REX prefix bit here to avoid decoder
3006 complications. */
3007 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3008 {
3009 default_seg = &ss;
3010 if (i.disp_operands == 0)
3011 {
3012 fake_zero_displacement = 1;
3013 i.types[op] |= Disp8;
3014 }
3015 }
3016 else if (i.base_reg->reg_num == ESP_REG_NUM)
3017 {
3018 default_seg = &ss;
3019 }
3020 i.sib.scale = i.log2_scale_factor;
3021 if (i.index_reg == 0)
3022 {
3023 /* <disp>(%esp) becomes two byte modrm with no index
3024 register. We've already stored the code for esp
3025 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3026 Any base register besides %esp will not use the
3027 extra modrm byte. */
3028 i.sib.index = NO_INDEX_REGISTER;
3029#if !SCALE1_WHEN_NO_INDEX
3030 /* Another case where we force the second modrm byte. */
3031 if (i.log2_scale_factor)
3032 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 3033#endif
29b0f896
AM		 3034 }
3035 else
3036 {
3037 i.sib.index = i.index_reg->reg_num;
3038 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3039 if ((i.index_reg->reg_flags & RegRex) != 0)
3040 i.rex |= REX_EXTY;
3041 }
3042 i.rm.mode = mode_from_disp_size (i.types[op]);
3043 }
252b5132 3044
29b0f896
AM		 3045 if (fake_zero_displacement)
3046 {
3047 /* Fakes a zero displacement assuming that i.types[op]
3048 holds the correct displacement size. */
3049 expressionS *exp;
3050
3051 assert (i.op[op].disps == 0);
3052 exp = &disp_expressions[i.disp_operands++];
3053 i.op[op].disps = exp;
3054 exp->X_op = O_constant;
3055 exp->X_add_number = 0;
3056 exp->X_add_symbol = (symbolS *) 0;
3057 exp->X_op_symbol = (symbolS *) 0;
3058 }
3059 }
252b5132 3060
29b0f896
AM		 3061 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3062 (if any) based on i.tm.extension_opcode. Again, we must be
3063 careful to make sure that segment/control/debug/test/MMX
3064 registers are coded into the i.rm.reg field. */
3065 if (i.reg_operands)
3066 {
3067 unsigned int op =
3068 ((i.types[0]
3069 & (Reg | RegMMX | RegXMM
3070 | SReg2 | SReg3
3071 | Control | Debug | Test))
3072 ? 0
3073 : ((i.types[1]
3074 & (Reg | RegMMX | RegXMM
3075 | SReg2 | SReg3
3076 | Control | Debug | Test))
3077 ? 1
3078 : 2));
3079 /* If there is an extension opcode to put here, the register
3080 number must be put into the regmem field. */
3081 if (i.tm.extension_opcode != None)
3082 {
3083 i.rm.regmem = i.op[op].regs->reg_num;
3084 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3085 i.rex |= REX_EXTZ;
3086 }
3087 else
3088 {
3089 i.rm.reg = i.op[op].regs->reg_num;
3090 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3091 i.rex |= REX_EXTX;
3092 }
252b5132 3093
29b0f896
AM		 3094 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3095 must set it to 3 to indicate this is a register operand
3096 in the regmem field. */
3097 if (!i.mem_operands)
3098 i.rm.mode = 3;
3099 }
252b5132 3100
29b0f896
AM		 3101 /* Fill in i.rm.reg field with extension opcode (if any). */
3102 if (i.tm.extension_opcode != None)
3103 i.rm.reg = i.tm.extension_opcode;
3104 }
3105 return default_seg;
3106}
252b5132 3107
29b0f896
AM		 3108static void
3109output_branch ()
3110{
3111 char *p;
3112 int code16;
3113 int prefix;
3114 relax_substateT subtype;
3115 symbolS *sym;
3116 offsetT off;
3117
3118 code16 = 0;
3119 if (flag_code == CODE_16BIT)
3120 code16 = CODE16;
3121
3122 prefix = 0;
3123 if (i.prefix[DATA_PREFIX] != 0)
252b5132 3124 {
29b0f896
AM		 3125 prefix = 1;
3126 i.prefixes -= 1;
3127 code16 ^= CODE16;
252b5132 3128 }
29b0f896
AM		 3129 /* Pentium4 branch hints. */
3130 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3131 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 3132 {
29b0f896
AM		 3133 prefix++;
3134 i.prefixes--;
3135 }
3136 if (i.prefix[REX_PREFIX] != 0)
3137 {
3138 prefix++;
3139 i.prefixes--;
2f66722d
AM		 3140 }
3141
29b0f896
AM		 3142 if (i.prefixes != 0 && !intel_syntax)
3143 as_warn (_("skipping prefixes on this instruction"));
3144
3145 /* It's always a symbol; End frag & setup for relax.
3146 Make sure there is enough room in this frag for the largest
3147 instruction we may generate in md_convert_frag. This is 2
3148 bytes for the opcode and room for the prefix and largest
3149 displacement. */
3150 frag_grow (prefix + 2 + 4);
3151 /* Prefix and 1 opcode byte go in fr_fix. */
3152 p = frag_more (prefix + 1);
3153 if (i.prefix[DATA_PREFIX] != 0)
3154 *p++ = DATA_PREFIX_OPCODE;
3155 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3156 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3157 *p++ = i.prefix[SEG_PREFIX];
3158 if (i.prefix[REX_PREFIX] != 0)
3159 *p++ = i.prefix[REX_PREFIX];
3160 *p = i.tm.base_opcode;
3161
3162 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3163 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3164 else if ((cpu_arch_flags & Cpu386) != 0)
3165 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3166 else
3167 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3168 subtype |= code16;
3e73aa7c 3169
29b0f896
AM		 3170 sym = i.op[0].disps->X_add_symbol;
3171 off = i.op[0].disps->X_add_number;
3e73aa7c 3172
29b0f896
AM		 3173 if (i.op[0].disps->X_op != O_constant
3174 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 3175 {
29b0f896
AM		 3176 /* Handle complex expressions. */
3177 sym = make_expr_symbol (i.op[0].disps);
3178 off = 0;
3179 }
3e73aa7c 3180
29b0f896
AM		 3181 /* 1 possible extra opcode + 4 byte displacement go in var part.
3182 Pass reloc in fr_var. */
3183 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3184}
3e73aa7c 3185
29b0f896
AM		 3186static void
3187output_jump ()
3188{
3189 char *p;
3190 int size;
3e02c1cc 3191 fixS *fixP;
29b0f896
AM		 3192
3193 if (i.tm.opcode_modifier & JumpByte)
3194 {
3195 /* This is a loop or jecxz type instruction. */
3196 size = 1;
3197 if (i.prefix[ADDR_PREFIX] != 0)
3198 {
3199 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3200 i.prefixes -= 1;
3201 }
3202 /* Pentium4 branch hints. */
3203 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3204 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3205 {
3206 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3207 i.prefixes--;
3e73aa7c
JH		 3208 }
3209 }
29b0f896
AM		 3210 else
3211 {
3212 int code16;
3e73aa7c 3213
29b0f896
AM		 3214 code16 = 0;
3215 if (flag_code == CODE_16BIT)
3216 code16 = CODE16;
3e73aa7c 3217
29b0f896
AM		 3218 if (i.prefix[DATA_PREFIX] != 0)
3219 {
3220 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3221 i.prefixes -= 1;
3222 code16 ^= CODE16;
3223 }
252b5132 3224
29b0f896
AM		 3225 size = 4;
3226 if (code16)
3227 size = 2;
3228 }
9fcc94b6 3229
29b0f896
AM		 3230 if (i.prefix[REX_PREFIX] != 0)
3231 {
3232 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3233 i.prefixes -= 1;
3234 }
252b5132 3235
29b0f896
AM		 3236 if (i.prefixes != 0 && !intel_syntax)
3237 as_warn (_("skipping prefixes on this instruction"));
e0890092 3238
29b0f896
AM		 3239 p = frag_more (1 + size);
3240 *p++ = i.tm.base_opcode;
e0890092 3241
3e02c1cc
AM		 3242 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3243 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3244
3245 /* All jumps handled here are signed, but don't use a signed limit
3246 check for 32 and 16 bit jumps as we want to allow wrap around at
3247 4G and 64k respectively. */
3248 if (size == 1)
3249 fixP->fx_signed = 1;
29b0f896 3250}
e0890092 3251
29b0f896
AM		 3252static void
3253output_interseg_jump ()
3254{
3255 char *p;
3256 int size;
3257 int prefix;
3258 int code16;
252b5132 3259
29b0f896
AM		 3260 code16 = 0;
3261 if (flag_code == CODE_16BIT)
3262 code16 = CODE16;
a217f122 3263
29b0f896
AM		 3264 prefix = 0;
3265 if (i.prefix[DATA_PREFIX] != 0)
3266 {
3267 prefix = 1;
3268 i.prefixes -= 1;
3269 code16 ^= CODE16;
3270 }
3271 if (i.prefix[REX_PREFIX] != 0)
3272 {
3273 prefix++;
3274 i.prefixes -= 1;
3275 }
252b5132 3276
29b0f896
AM		 3277 size = 4;
3278 if (code16)
3279 size = 2;
252b5132 3280
29b0f896
AM		 3281 if (i.prefixes != 0 && !intel_syntax)
3282 as_warn (_("skipping prefixes on this instruction"));
252b5132 3283
29b0f896
AM		 3284 /* 1 opcode; 2 segment; offset */
3285 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3286
29b0f896
AM		 3287 if (i.prefix[DATA_PREFIX] != 0)
3288 *p++ = DATA_PREFIX_OPCODE;
252b5132 3289
29b0f896
AM		 3290 if (i.prefix[REX_PREFIX] != 0)
3291 *p++ = i.prefix[REX_PREFIX];
252b5132 3292
29b0f896
AM		 3293 *p++ = i.tm.base_opcode;
3294 if (i.op[1].imms->X_op == O_constant)
3295 {
3296 offsetT n = i.op[1].imms->X_add_number;
252b5132 3297
29b0f896
AM		 3298 if (size == 2
3299 && !fits_in_unsigned_word (n)
3300 && !fits_in_signed_word (n))
3301 {
3302 as_bad (_("16-bit jump out of range"));
3303 return;
3304 }
3305 md_number_to_chars (p, n, size);
3306 }
3307 else
3308 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3309 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3310 if (i.op[0].imms->X_op != O_constant)
3311 as_bad (_("can't handle non absolute segment in `%s'"),
3312 i.tm.name);
3313 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3314}
a217f122 3315
29b0f896
AM		 3316static void
3317output_insn ()
3318{
2bbd9c25
JJ		 3319 fragS *insn_start_frag;
3320 offsetT insn_start_off;
3321
29b0f896
AM		 3322 /* Tie dwarf2 debug info to the address at the start of the insn.
3323 We can't do this after the insn has been output as the current
3324 frag may have been closed off. eg. by frag_var. */
3325 dwarf2_emit_insn (0);
3326
2bbd9c25
JJ		 3327 insn_start_frag = frag_now;
3328 insn_start_off = frag_now_fix ();
3329
29b0f896
AM		 3330 /* Output jumps. */
3331 if (i.tm.opcode_modifier & Jump)
3332 output_branch ();
3333 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3334 output_jump ();
3335 else if (i.tm.opcode_modifier & JumpInterSegment)
3336 output_interseg_jump ();
3337 else
3338 {
3339 /* Output normal instructions here. */
3340 char *p;
3341 unsigned char *q;
252b5132 3342
bc4bd9ab
MK		 3343 /* All opcodes on i386 have either 1 or 2 bytes. We may use one
3344 more higher byte to specify a prefix the instruction
3345 requires. */
3346 if ((i.tm.base_opcode & 0xff0000) != 0)
3347 {
3348 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3349 {
3350 unsigned int prefix;
3351 prefix = (i.tm.base_opcode >> 16) & 0xff;
3352
3353 if (prefix != REPE_PREFIX_OPCODE
3354 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3355 add_prefix (prefix);
3356 }
3357 else
3358 add_prefix ((i.tm.base_opcode >> 16) & 0xff);
0f10071e 3359 }
252b5132 3360
29b0f896
AM		 3361 /* The prefix bytes. */
3362 for (q = i.prefix;
3363 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3364 q++)
3365 {
3366 if (*q)
3367 {
3368 p = frag_more (1);
3369 md_number_to_chars (p, (valueT) *q, 1);
3370 }
3371 }
252b5132 3372
29b0f896
AM		 3373 /* Now the opcode; be careful about word order here! */
3374 if (fits_in_unsigned_byte (i.tm.base_opcode))
3375 {
3376 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3377 }
3378 else
3379 {
bc4bd9ab 3380 p = frag_more (2);
0f10071e 3381
29b0f896
AM		 3382 /* Put out high byte first: can't use md_number_to_chars! */
3383 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3384 *p = i.tm.base_opcode & 0xff;
3385 }
3e73aa7c 3386
29b0f896
AM		 3387 /* Now the modrm byte and sib byte (if present). */
3388 if (i.tm.opcode_modifier & Modrm)
3389 {
3390 p = frag_more (1);
3391 md_number_to_chars (p,
3392 (valueT) (i.rm.regmem << 0
3393 | i.rm.reg << 3
3394 | i.rm.mode << 6),
3395 1);
3396 /* If i.rm.regmem == ESP (4)
3397 && i.rm.mode != (Register mode)
3398 && not 16 bit
3399 ==> need second modrm byte. */
3400 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3401 && i.rm.mode != 3
3402 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3403 {
3404 p = frag_more (1);
3405 md_number_to_chars (p,
3406 (valueT) (i.sib.base << 0
3407 | i.sib.index << 3
3408 | i.sib.scale << 6),
3409 1);
3410 }
3411 }
3e73aa7c 3412
29b0f896 3413 if (i.disp_operands)
2bbd9c25 3414 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 3415
29b0f896 3416 if (i.imm_operands)
2bbd9c25 3417 output_imm (insn_start_frag, insn_start_off);
29b0f896 3418 }
252b5132 3419
29b0f896
AM		 3420#ifdef DEBUG386
3421 if (flag_debug)
3422 {
3423 pi (line, &i);
3424 }
3425#endif /* DEBUG386 */
3426}
252b5132 3427
29b0f896 3428static void
2bbd9c25
JJ		 3429output_disp (insn_start_frag, insn_start_off)
3430 fragS *insn_start_frag;
3431 offsetT insn_start_off;
29b0f896
AM		 3432{
3433 char *p;
3434 unsigned int n;
252b5132 3435
29b0f896
AM		 3436 for (n = 0; n < i.operands; n++)
3437 {
3438 if (i.types[n] & Disp)
3439 {
3440 if (i.op[n].disps->X_op == O_constant)
3441 {
3442 int size;
3443 offsetT val;
252b5132 3444
29b0f896
AM		 3445 size = 4;
3446 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3447 {
3448 size = 2;
3449 if (i.types[n] & Disp8)
3450 size = 1;
3451 if (i.types[n] & Disp64)
3452 size = 8;
3453 }
3454 val = offset_in_range (i.op[n].disps->X_add_number,
3455 size);
3456 p = frag_more (size);
3457 md_number_to_chars (p, val, size);
3458 }
3459 else
3460 {
f86103b7 3461 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 3462 int size = 4;
3463 int sign = 0;
3464 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
3465
3466 /* The PC relative address is computed relative
3467 to the instruction boundary, so in case immediate
3468 fields follows, we need to adjust the value. */
3469 if (pcrel && i.imm_operands)
3470 {
3471 int imm_size = 4;
3472 unsigned int n1;
252b5132 3473
29b0f896
AM		 3474 for (n1 = 0; n1 < i.operands; n1++)
3475 if (i.types[n1] & Imm)
252b5132 3476 {
29b0f896 3477 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 3478 {
29b0f896
AM		 3479 imm_size = 2;
3480 if (i.types[n1] & (Imm8 | Imm8S))
3481 imm_size = 1;
3482 if (i.types[n1] & Imm64)
3483 imm_size = 8;
252b5132 3484 }
29b0f896 3485 break;
252b5132 3486 }
29b0f896
AM		 3487 /* We should find the immediate. */
3488 if (n1 == i.operands)
3489 abort ();
3490 i.op[n].disps->X_add_number -= imm_size;
3491 }
520dc8e8 3492
29b0f896
AM		 3493 if (i.types[n] & Disp32S)
3494 sign = 1;
3e73aa7c 3495
29b0f896
AM		 3496 if (i.types[n] & (Disp16 | Disp64))
3497 {
3498 size = 2;
3499 if (i.types[n] & Disp64)
3500 size = 8;
3501 }
520dc8e8 3502
29b0f896 3503 p = frag_more (size);
2bbd9c25 3504 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
2bbd9c25
JJ		 3505 if (reloc_type == BFD_RELOC_32
3506 && GOT_symbol
3507 && GOT_symbol == i.op[n].disps->X_add_symbol
3508 && (i.op[n].disps->X_op == O_symbol
3509 || (i.op[n].disps->X_op == O_add
3510 && ((symbol_get_value_expression
3511 (i.op[n].disps->X_op_symbol)->X_op)
3512 == O_subtract))))
3513 {
3514 offsetT add;
3515
3516 if (insn_start_frag == frag_now)
3517 add = (p - frag_now->fr_literal) - insn_start_off;
3518 else
3519 {
3520 fragS *fr;
3521
3522 add = insn_start_frag->fr_fix - insn_start_off;
3523 for (fr = insn_start_frag->fr_next;
3524 fr && fr != frag_now; fr = fr->fr_next)
3525 add += fr->fr_fix;
3526 add += p - frag_now->fr_literal;
3527 }
3528
3529 /* We don't support dynamic linking on x86-64 yet. */
3530 if (flag_code == CODE_64BIT)
3531 abort ();
3532 reloc_type = BFD_RELOC_386_GOTPC;
3533 i.op[n].disps->X_add_number += add;
3534 }
062cd5e7 3535 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 3536 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 3537 }
3538 }
3539 }
3540}
252b5132 3541
29b0f896 3542static void
2bbd9c25
JJ		 3543output_imm (insn_start_frag, insn_start_off)
3544 fragS *insn_start_frag;
3545 offsetT insn_start_off;
29b0f896
AM		 3546{
3547 char *p;
3548 unsigned int n;
252b5132 3549
29b0f896
AM		 3550 for (n = 0; n < i.operands; n++)
3551 {
3552 if (i.types[n] & Imm)
3553 {
3554 if (i.op[n].imms->X_op == O_constant)
3555 {
3556 int size;
3557 offsetT val;
b4cac588 3558
29b0f896
AM		 3559 size = 4;
3560 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3561 {
3562 size = 2;
3563 if (i.types[n] & (Imm8 | Imm8S))
3564 size = 1;
3565 else if (i.types[n] & Imm64)
3566 size = 8;
3567 }
3568 val = offset_in_range (i.op[n].imms->X_add_number,
3569 size);
3570 p = frag_more (size);
3571 md_number_to_chars (p, val, size);
3572 }
3573 else
3574 {
3575 /* Not absolute_section.
3576 Need a 32-bit fixup (don't support 8bit
3577 non-absolute imms). Try to support other
3578 sizes ... */
f86103b7 3579 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 3580 int size = 4;
3581 int sign = 0;
3582
3583 if ((i.types[n] & (Imm32S))
a7d61044
JB		 3584 && (i.suffix == QWORD_MNEM_SUFFIX
3585 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
29b0f896
AM		 3586 sign = 1;
3587 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3588 {
3589 size = 2;
3590 if (i.types[n] & (Imm8 | Imm8S))
3591 size = 1;
3592 if (i.types[n] & Imm64)
3593 size = 8;
3594 }
520dc8e8 3595
29b0f896
AM		 3596 p = frag_more (size);
3597 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 3598
2bbd9c25
JJ		 3599 /* This is tough to explain. We end up with this one if we
3600 * have operands that look like
3601 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3602 * obtain the absolute address of the GOT, and it is strongly
3603 * preferable from a performance point of view to avoid using
3604 * a runtime relocation for this. The actual sequence of
3605 * instructions often look something like:
3606 *
3607 * call .L66
3608 * .L66:
3609 * popl %ebx
3610 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3611 *
3612 * The call and pop essentially return the absolute address
3613 * of the label .L66 and store it in %ebx. The linker itself
3614 * will ultimately change the first operand of the addl so
3615 * that %ebx points to the GOT, but to keep things simple, the
3616 * .o file must have this operand set so that it generates not
3617 * the absolute address of .L66, but the absolute address of
3618 * itself. This allows the linker itself simply treat a GOTPC
3619 * relocation as asking for a pcrel offset to the GOT to be
3620 * added in, and the addend of the relocation is stored in the
3621 * operand field for the instruction itself.
3622 *
3623 * Our job here is to fix the operand so that it would add
3624 * the correct offset so that %ebx would point to itself. The
3625 * thing that is tricky is that .-.L66 will point to the
3626 * beginning of the instruction, so we need to further modify
3627 * the operand so that it will point to itself. There are
3628 * other cases where you have something like:
3629 *
3630 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3631 *
3632 * and here no correction would be required. Internally in
3633 * the assembler we treat operands of this form as not being
3634 * pcrel since the '.' is explicitly mentioned, and I wonder
3635 * whether it would simplify matters to do it this way. Who
3636 * knows. In earlier versions of the PIC patches, the
3637 * pcrel_adjust field was used to store the correction, but
3638 * since the expression is not pcrel, I felt it would be
3639 * confusing to do it this way. */
3640
29b0f896
AM		 3641 if (reloc_type == BFD_RELOC_32
3642 && GOT_symbol
3643 && GOT_symbol == i.op[n].imms->X_add_symbol
3644 && (i.op[n].imms->X_op == O_symbol
3645 || (i.op[n].imms->X_op == O_add
3646 && ((symbol_get_value_expression
3647 (i.op[n].imms->X_op_symbol)->X_op)
3648 == O_subtract))))
3649 {
2bbd9c25
JJ		 3650 offsetT add;
3651
3652 if (insn_start_frag == frag_now)
3653 add = (p - frag_now->fr_literal) - insn_start_off;
3654 else
3655 {
3656 fragS *fr;
3657
3658 add = insn_start_frag->fr_fix - insn_start_off;
3659 for (fr = insn_start_frag->fr_next;
3660 fr && fr != frag_now; fr = fr->fr_next)
3661 add += fr->fr_fix;
3662 add += p - frag_now->fr_literal;
3663 }
3664
29b0f896
AM		 3665 /* We don't support dynamic linking on x86-64 yet. */
3666 if (flag_code == CODE_64BIT)
3667 abort ();
3668 reloc_type = BFD_RELOC_386_GOTPC;
2bbd9c25 3669 i.op[n].imms->X_add_number += add;
29b0f896 3670 }
29b0f896
AM		 3671 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3672 i.op[n].imms, 0, reloc_type);
3673 }
3674 }
3675 }
252b5132
RH		 3676}
3677\f
f3c180ae 3678#ifndef LEX_AT
f86103b7 3679static char *lex_got PARAMS ((enum bfd_reloc_code_real *, int *));
f3c180ae
AM		 3680
3681/* Parse operands of the form
3682 <symbol>@GOTOFF+<nnn>
3683 and similar .plt or .got references.
3684
3685 If we find one, set up the correct relocation in RELOC and copy the
3686 input string, minus the `@GOTOFF' into a malloc'd buffer for
3687 parsing by the calling routine. Return this buffer, and if ADJUST
3688 is non-null set it to the length of the string we removed from the
3689 input line. Otherwise return NULL. */
3690static char *
3691lex_got (reloc, adjust)
f86103b7 3692 enum bfd_reloc_code_real *reloc;
f3c180ae
AM		 3693 int *adjust;
3694{
3695 static const char * const mode_name[NUM_FLAG_CODE] = { "32", "16", "64" };
3696 static const struct {
3697 const char *str;
f86103b7 3698 const enum bfd_reloc_code_real rel[NUM_FLAG_CODE];
f3c180ae 3699 } gotrel[] = {
13ae64f3
JJ		 3700 { "PLT", { BFD_RELOC_386_PLT32, 0, BFD_RELOC_X86_64_PLT32 } },
3701 { "GOTOFF", { BFD_RELOC_386_GOTOFF, 0, 0 } },
3702 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL } },
bffbf940 3703 { "TLSGD", { BFD_RELOC_386_TLS_GD, 0, BFD_RELOC_X86_64_TLSGD } },
13ae64f3 3704 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0, 0 } },
bffbf940
JJ		 3705 { "TLSLD", { 0, 0, BFD_RELOC_X86_64_TLSLD } },
3706 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, 0, BFD_RELOC_X86_64_GOTTPOFF } },
3707 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, 0, BFD_RELOC_X86_64_TPOFF32 } },
13ae64f3 3708 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0, 0 } },
bffbf940 3709 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, 0, BFD_RELOC_X86_64_DTPOFF32 } },
37e55690
JJ		 3710 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0, 0 } },
3711 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0, 0 } },
13ae64f3 3712 { "GOT", { BFD_RELOC_386_GOT32, 0, BFD_RELOC_X86_64_GOT32 } }
f3c180ae
AM		 3713 };
3714 char *cp;
3715 unsigned int j;
3716
3717 for (cp = input_line_pointer; *cp != '@'; cp++)
3718 if (is_end_of_line[(unsigned char) *cp])
3719 return NULL;
3720
3721 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
3722 {
3723 int len;
3724
3725 len = strlen (gotrel[j].str);
28f81592 3726 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae
AM		 3727 {
3728 if (gotrel[j].rel[(unsigned int) flag_code] != 0)
3729 {
28f81592
AM		 3730 int first, second;
3731 char *tmpbuf, *past_reloc;
f3c180ae
AM		 3732
3733 *reloc = gotrel[j].rel[(unsigned int) flag_code];
28f81592
AM		 3734 if (adjust)
3735 *adjust = len;
f3c180ae
AM		 3736
3737 if (GOT_symbol == NULL)
3738 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3739
3740 /* Replace the relocation token with ' ', so that
3741 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 3742
3743 /* The length of the first part of our input line. */
f3c180ae 3744 first = cp - input_line_pointer;
28f81592
AM		 3745
3746 /* The second part goes from after the reloc token until
3747 (and including) an end_of_line char. Don't use strlen
3748 here as the end_of_line char may not be a NUL. */
3749 past_reloc = cp + 1 + len;
3750 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
3751 ;
3752 second = cp - past_reloc;
3753
3754 /* Allocate and copy string. The trailing NUL shouldn't
3755 be necessary, but be safe. */
3756 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 3757 memcpy (tmpbuf, input_line_pointer, first);
3758 tmpbuf[first] = ' ';
28f81592
AM		 3759 memcpy (tmpbuf + first + 1, past_reloc, second);
3760 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 3761 return tmpbuf;
3762 }
3763
3764 as_bad (_("@%s reloc is not supported in %s bit mode"),
3765 gotrel[j].str, mode_name[(unsigned int) flag_code]);
3766 return NULL;
3767 }
3768 }
3769
3770 /* Might be a symbol version string. Don't as_bad here. */
3771 return NULL;
3772}
3773
3774/* x86_cons_fix_new is called via the expression parsing code when a
3775 reloc is needed. We use this hook to get the correct .got reloc. */
f86103b7 3776static enum bfd_reloc_code_real got_reloc = NO_RELOC;
f3c180ae
AM		 3777
3778void
3779x86_cons_fix_new (frag, off, len, exp)
3780 fragS *frag;
3781 unsigned int off;
3782 unsigned int len;
3783 expressionS *exp;
3784{
f86103b7 3785 enum bfd_reloc_code_real r = reloc (len, 0, 0, got_reloc);
f3c180ae
AM		 3786 got_reloc = NO_RELOC;
3787 fix_new_exp (frag, off, len, exp, 0, r);
3788}
3789
3790void
3791x86_cons (exp, size)
3792 expressionS *exp;
3793 int size;
3794{
3795 if (size == 4)
3796 {
3797 /* Handle @GOTOFF and the like in an expression. */
3798 char *save;
3799 char *gotfree_input_line;
3800 int adjust;
3801
3802 save = input_line_pointer;
3803 gotfree_input_line = lex_got (&got_reloc, &adjust);
3804 if (gotfree_input_line)
3805 input_line_pointer = gotfree_input_line;
3806
3807 expression (exp);
3808
3809 if (gotfree_input_line)
3810 {
3811 /* expression () has merrily parsed up to the end of line,
3812 or a comma - in the wrong buffer. Transfer how far
3813 input_line_pointer has moved to the right buffer. */
3814 input_line_pointer = (save
3815 + (input_line_pointer - gotfree_input_line)
3816 + adjust);
3817 free (gotfree_input_line);
3818 }
3819 }
3820 else
3821 expression (exp);
3822}
3823#endif
3824
6482c264
NC		 3825#ifdef TE_PE
3826
6482c264
NC		 3827void
3828x86_pe_cons_fix_new (frag, off, len, exp)
3829 fragS *frag;
3830 unsigned int off;
3831 unsigned int len;
3832 expressionS *exp;
3833{
3834 enum bfd_reloc_code_real r = reloc (len, 0, 0, NO_RELOC);
3835
3836 if (exp->X_op == O_secrel)
3837 {
3838 exp->X_op = O_symbol;
3839 r = BFD_RELOC_32_SECREL;
3840 }
3841
3842 fix_new_exp (frag, off, len, exp, 0, r);
3843}
3844
3845static void
3846pe_directive_secrel (dummy)
3847 int dummy ATTRIBUTE_UNUSED;
3848{
3849 expressionS exp;
3850
3851 do
3852 {
3853 expression (&exp);
3854 if (exp.X_op == O_symbol)
3855 exp.X_op = O_secrel;
3856
3857 emit_expr (&exp, 4);
3858 }
3859 while (*input_line_pointer++ == ',');
3860
3861 input_line_pointer--;
3862 demand_empty_rest_of_line ();
3863}
3864
3865#endif
3866
252b5132
RH		 3867static int i386_immediate PARAMS ((char *));
3868
3869static int
3870i386_immediate (imm_start)
3871 char *imm_start;
3872{
3873 char *save_input_line_pointer;
f3c180ae
AM		 3874#ifndef LEX_AT
3875 char *gotfree_input_line;
3876#endif
252b5132 3877 segT exp_seg = 0;
47926f60 3878 expressionS *exp;
252b5132
RH		 3879
3880 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
3881 {
d0b47220 3882 as_bad (_("only 1 or 2 immediate operands are allowed"));
252b5132
RH		 3883 return 0;
3884 }
3885
3886 exp = &im_expressions[i.imm_operands++];
520dc8e8 3887 i.op[this_operand].imms = exp;
252b5132
RH		 3888
3889 if (is_space_char (*imm_start))
3890 ++imm_start;
3891
3892 save_input_line_pointer = input_line_pointer;
3893 input_line_pointer = imm_start;
3894
3895#ifndef LEX_AT
f3c180ae
AM		 3896 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3897 if (gotfree_input_line)
3898 input_line_pointer = gotfree_input_line;
252b5132
RH		 3899#endif
3900
3901 exp_seg = expression (exp);
3902
83183c0c 3903 SKIP_WHITESPACE ();
252b5132 3904 if (*input_line_pointer)
f3c180ae 3905 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 3906
3907 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 3908#ifndef LEX_AT
3909 if (gotfree_input_line)
3910 free (gotfree_input_line);
3911#endif
252b5132 3912
2daf4fd8 3913 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 3914 {
47926f60 3915 /* Missing or bad expr becomes absolute 0. */
d0b47220 3916 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 3917 imm_start);
252b5132
RH		 3918 exp->X_op = O_constant;
3919 exp->X_add_number = 0;
3920 exp->X_add_symbol = (symbolS *) 0;
3921 exp->X_op_symbol = (symbolS *) 0;
252b5132 3922 }
3e73aa7c 3923 else if (exp->X_op == O_constant)
252b5132 3924 {
47926f60 3925 /* Size it properly later. */
3e73aa7c
JH		 3926 i.types[this_operand] |= Imm64;
3927 /* If BFD64, sign extend val. */
3928 if (!use_rela_relocations)
3929 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
3930 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 3931 }
4c63da97 3932#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 3933 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 3934 && exp_seg != absolute_section
47926f60 3935 && exp_seg != text_section
24eab124
AM		 3936 && exp_seg != data_section
3937 && exp_seg != bss_section
3938 && exp_seg != undefined_section
f86103b7 3939 && !bfd_is_com_section (exp_seg))
252b5132 3940 {
d0b47220 3941 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 3942 return 0;
3943 }
3944#endif
3945 else
3946 {
3947 /* This is an address. The size of the address will be
24eab124 3948 determined later, depending on destination register,
3e73aa7c
JH		 3949 suffix, or the default for the section. */
3950 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
252b5132
RH		 3951 }
3952
3953 return 1;
3954}
3955
551c1ca1 3956static char *i386_scale PARAMS ((char *));
252b5132 3957
551c1ca1 3958static char *
252b5132
RH		 3959i386_scale (scale)
3960 char *scale;
3961{
551c1ca1
AM		 3962 offsetT val;
3963 char *save = input_line_pointer;
252b5132 3964
551c1ca1
AM		 3965 input_line_pointer = scale;
3966 val = get_absolute_expression ();
3967
3968 switch (val)
252b5132 3969 {
551c1ca1 3970 case 1:
252b5132
RH		 3971 i.log2_scale_factor = 0;
3972 break;
551c1ca1 3973 case 2:
252b5132
RH		 3974 i.log2_scale_factor = 1;
3975 break;
551c1ca1 3976 case 4:
252b5132
RH		 3977 i.log2_scale_factor = 2;
3978 break;
551c1ca1 3979 case 8:
252b5132
RH		 3980 i.log2_scale_factor = 3;
3981 break;
3982 default:
a724f0f4
JB		 3983 {
3984 char sep = *input_line_pointer;
3985
3986 *input_line_pointer = '\0';
3987 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3988 scale);
3989 *input_line_pointer = sep;
3990 input_line_pointer = save;
3991 return NULL;
3992 }
252b5132 3993 }
29b0f896 3994 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 3995 {
3996 as_warn (_("scale factor of %d without an index register"),
24eab124 3997 1 << i.log2_scale_factor);
252b5132
RH		 3998#if SCALE1_WHEN_NO_INDEX
3999 i.log2_scale_factor = 0;
4000#endif
4001 }
551c1ca1
AM		 4002 scale = input_line_pointer;
4003 input_line_pointer = save;
4004 return scale;
252b5132
RH		 4005}
4006
4007static int i386_displacement PARAMS ((char *, char *));
4008
4009static int
4010i386_displacement (disp_start, disp_end)
4011 char *disp_start;
4012 char *disp_end;
4013{
29b0f896 4014 expressionS *exp;
252b5132
RH		 4015 segT exp_seg = 0;
4016 char *save_input_line_pointer;
f3c180ae
AM		 4017#ifndef LEX_AT
4018 char *gotfree_input_line;
4019#endif
252b5132
RH		 4020 int bigdisp = Disp32;
4021
3e73aa7c 4022 if (flag_code == CODE_64BIT)
7ecd2f8b 4023 {
29b0f896
AM		 4024 if (i.prefix[ADDR_PREFIX] == 0)
4025 bigdisp = Disp64;
7ecd2f8b
JH		 4026 }
4027 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4028 bigdisp = Disp16;
252b5132
RH		 4029 i.types[this_operand] |= bigdisp;
4030
4031 exp = &disp_expressions[i.disp_operands];
520dc8e8 4032 i.op[this_operand].disps = exp;
252b5132
RH		 4033 i.disp_operands++;
4034 save_input_line_pointer = input_line_pointer;
4035 input_line_pointer = disp_start;
4036 END_STRING_AND_SAVE (disp_end);
4037
4038#ifndef GCC_ASM_O_HACK
4039#define GCC_ASM_O_HACK 0
4040#endif
4041#if GCC_ASM_O_HACK
4042 END_STRING_AND_SAVE (disp_end + 1);
4043 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 4044 && displacement_string_end[-1] == '+')
252b5132
RH		 4045 {
4046 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 4047 constraint within gcc asm statements.
4048 For instance:
4049
4050 #define _set_tssldt_desc(n,addr,limit,type) \
4051 __asm__ __volatile__ ( \
4052 "movw %w2,%0\n\t" \
4053 "movw %w1,2+%0\n\t" \
4054 "rorl $16,%1\n\t" \
4055 "movb %b1,4+%0\n\t" \
4056 "movb %4,5+%0\n\t" \
4057 "movb $0,6+%0\n\t" \
4058 "movb %h1,7+%0\n\t" \
4059 "rorl $16,%1" \
4060 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4061
4062 This works great except that the output assembler ends
4063 up looking a bit weird if it turns out that there is
4064 no offset. You end up producing code that looks like:
4065
4066 #APP
4067 movw $235,(%eax)
4068 movw %dx,2+(%eax)
4069 rorl $16,%edx
4070 movb %dl,4+(%eax)
4071 movb $137,5+(%eax)
4072 movb $0,6+(%eax)
4073 movb %dh,7+(%eax)
4074 rorl $16,%edx
4075 #NO_APP
4076
47926f60 4077 So here we provide the missing zero. */
24eab124
AM		 4078
4079 *displacement_string_end = '0';
252b5132
RH		 4080 }
4081#endif
4082#ifndef LEX_AT
f3c180ae
AM		 4083 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
4084 if (gotfree_input_line)
4085 input_line_pointer = gotfree_input_line;
252b5132
RH		 4086#endif
4087
24eab124 4088 exp_seg = expression (exp);
252b5132 4089
636c26b0
AM		 4090 SKIP_WHITESPACE ();
4091 if (*input_line_pointer)
4092 as_bad (_("junk `%s' after expression"), input_line_pointer);
4093#if GCC_ASM_O_HACK
4094 RESTORE_END_STRING (disp_end + 1);
4095#endif
4096 RESTORE_END_STRING (disp_end);
4097 input_line_pointer = save_input_line_pointer;
4098#ifndef LEX_AT
4099 if (gotfree_input_line)
4100 free (gotfree_input_line);
4101#endif
4102
24eab124
AM		 4103 /* We do this to make sure that the section symbol is in
4104 the symbol table. We will ultimately change the relocation
47926f60 4105 to be relative to the beginning of the section. */
1ae12ab7
AM		 4106 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
4107 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
24eab124 4108 {
636c26b0
AM		 4109 if (exp->X_op != O_symbol)
4110 {
4111 as_bad (_("bad expression used with @%s"),
4112 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4113 ? "GOTPCREL"
4114 : "GOTOFF"));
4115 return 0;
4116 }
4117
e5cb08ac 4118 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 4119 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4120 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 4121 exp->X_op = O_subtract;
4122 exp->X_op_symbol = GOT_symbol;
1ae12ab7 4123 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 4124 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
23df1078 4125 else
29b0f896 4126 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 4127 }
252b5132 4128
2daf4fd8
AM		 4129 if (exp->X_op == O_absent || exp->X_op == O_big)
4130 {
47926f60 4131 /* Missing or bad expr becomes absolute 0. */
d0b47220 4132 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 4133 disp_start);
4134 exp->X_op = O_constant;
4135 exp->X_add_number = 0;
4136 exp->X_add_symbol = (symbolS *) 0;
4137 exp->X_op_symbol = (symbolS *) 0;
4138 }
4139
4c63da97 4140#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 4141 if (exp->X_op != O_constant
45288df1 4142 && OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4143 && exp_seg != absolute_section
45288df1
AM		 4144 && exp_seg != text_section
4145 && exp_seg != data_section
4146 && exp_seg != bss_section
31312f95 4147 && exp_seg != undefined_section
f86103b7 4148 && !bfd_is_com_section (exp_seg))
24eab124 4149 {
d0b47220 4150 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
24eab124
AM		 4151 return 0;
4152 }
252b5132 4153#endif
3e73aa7c
JH		 4154 else if (flag_code == CODE_64BIT)
4155 i.types[this_operand] |= Disp32S | Disp32;
252b5132
RH		 4156 return 1;
4157}
4158
e5cb08ac 4159static int i386_index_check PARAMS ((const char *));
252b5132 4160
eecb386c 4161/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 4162 Return 1 on success, 0 on a failure. */
4163
252b5132 4164static int
eecb386c
AM		 4165i386_index_check (operand_string)
4166 const char *operand_string;
252b5132 4167{
3e73aa7c 4168 int ok;
24eab124 4169#if INFER_ADDR_PREFIX
eecb386c
AM		 4170 int fudged = 0;
4171
24eab124
AM		 4172 tryprefix:
4173#endif
3e73aa7c 4174 ok = 1;
20f0a1fc
NC		 4175 if (flag_code == CODE_64BIT)
4176 {
4177 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4178
4179 if ((i.base_reg
4180 && ((i.base_reg->reg_type & RegXX) == 0)
4181 && (i.base_reg->reg_type != BaseIndex
4182 || i.index_reg))
4183 || (i.index_reg
4184 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4185 != (RegXX | BaseIndex))))
4186 ok = 0;
3e73aa7c
JH		 4187 }
4188 else
4189 {
4190 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4191 {
4192 /* 16bit checks. */
4193 if ((i.base_reg
29b0f896
AM		 4194 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4195 != (Reg16 | BaseIndex)))
3e73aa7c 4196 || (i.index_reg
29b0f896
AM		 4197 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4198 != (Reg16 | BaseIndex))
4199 || !(i.base_reg
4200 && i.base_reg->reg_num < 6
4201 && i.index_reg->reg_num >= 6
4202 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 4203 ok = 0;
4204 }
4205 else
e5cb08ac 4206 {
3e73aa7c
JH		 4207 /* 32bit checks. */
4208 if ((i.base_reg
4209 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4210 || (i.index_reg
29b0f896
AM		 4211 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4212 != (Reg32 | BaseIndex))))
e5cb08ac 4213 ok = 0;
3e73aa7c
JH		 4214 }
4215 }
4216 if (!ok)
24eab124
AM		 4217 {
4218#if INFER_ADDR_PREFIX
20f0a1fc 4219 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 4220 {
4221 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4222 i.prefixes += 1;
b23bac36
AM		 4223 /* Change the size of any displacement too. At most one of
4224 Disp16 or Disp32 is set.
4225 FIXME. There doesn't seem to be any real need for separate
4226 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 4227 Removing them would probably clean up the code quite a lot. */
20f0a1fc 4228 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
29b0f896 4229 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 4230 fudged = 1;
24eab124
AM		 4231 goto tryprefix;
4232 }
eecb386c
AM		 4233 if (fudged)
4234 as_bad (_("`%s' is not a valid base/index expression"),
4235 operand_string);
4236 else
c388dee8 4237#endif
eecb386c
AM		 4238 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4239 operand_string,
3e73aa7c 4240 flag_code_names[flag_code]);
24eab124 4241 }
20f0a1fc 4242 return ok;
24eab124 4243}
252b5132 4244
252b5132 4245/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 4246 on error. */
252b5132 4247
252b5132
RH		 4248static int
4249i386_operand (operand_string)
4250 char *operand_string;
4251{
af6bdddf
AM		 4252 const reg_entry *r;
4253 char *end_op;
24eab124 4254 char *op_string = operand_string;
252b5132 4255
24eab124 4256 if (is_space_char (*op_string))
252b5132
RH		 4257 ++op_string;
4258
24eab124 4259 /* We check for an absolute prefix (differentiating,
47926f60 4260 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 4261 if (*op_string == ABSOLUTE_PREFIX)
4262 {
4263 ++op_string;
4264 if (is_space_char (*op_string))
4265 ++op_string;
4266 i.types[this_operand] |= JumpAbsolute;
4267 }
252b5132 4268
47926f60 4269 /* Check if operand is a register. */
af6bdddf
AM		 4270 if ((*op_string == REGISTER_PREFIX || allow_naked_reg)
4271 && (r = parse_register (op_string, &end_op)) != NULL)
24eab124 4272 {
24eab124
AM		 4273 /* Check for a segment override by searching for ':' after a
4274 segment register. */
4275 op_string = end_op;
4276 if (is_space_char (*op_string))
4277 ++op_string;
4278 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4279 {
4280 switch (r->reg_num)
4281 {
4282 case 0:
4283 i.seg[i.mem_operands] = &es;
4284 break;
4285 case 1:
4286 i.seg[i.mem_operands] = &cs;
4287 break;
4288 case 2:
4289 i.seg[i.mem_operands] = &ss;
4290 break;
4291 case 3:
4292 i.seg[i.mem_operands] = &ds;
4293 break;
4294 case 4:
4295 i.seg[i.mem_operands] = &fs;
4296 break;
4297 case 5:
4298 i.seg[i.mem_operands] = &gs;
4299 break;
4300 }
252b5132 4301
24eab124 4302 /* Skip the ':' and whitespace. */
252b5132
RH		 4303 ++op_string;
4304 if (is_space_char (*op_string))
24eab124 4305 ++op_string;
252b5132 4306
24eab124
AM		 4307 if (!is_digit_char (*op_string)
4308 && !is_identifier_char (*op_string)
4309 && *op_string != '('
4310 && *op_string != ABSOLUTE_PREFIX)
4311 {
4312 as_bad (_("bad memory operand `%s'"), op_string);
4313 return 0;
4314 }
47926f60 4315 /* Handle case of %es:*foo. */
24eab124
AM		 4316 if (*op_string == ABSOLUTE_PREFIX)
4317 {
4318 ++op_string;
4319 if (is_space_char (*op_string))
4320 ++op_string;
4321 i.types[this_operand] |= JumpAbsolute;
4322 }
4323 goto do_memory_reference;
4324 }
4325 if (*op_string)
4326 {
d0b47220 4327 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 4328 return 0;
4329 }
4330 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 4331 i.op[this_operand].regs = r;
24eab124
AM		 4332 i.reg_operands++;
4333 }
af6bdddf
AM		 4334 else if (*op_string == REGISTER_PREFIX)
4335 {
4336 as_bad (_("bad register name `%s'"), op_string);
4337 return 0;
4338 }
24eab124 4339 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 4340 {
24eab124
AM		 4341 ++op_string;
4342 if (i.types[this_operand] & JumpAbsolute)
4343 {
d0b47220 4344 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 4345 return 0;
4346 }
4347 if (!i386_immediate (op_string))
4348 return 0;
4349 }
4350 else if (is_digit_char (*op_string)
4351 || is_identifier_char (*op_string)
e5cb08ac 4352 || *op_string == '(')
24eab124 4353 {
47926f60 4354 /* This is a memory reference of some sort. */
af6bdddf 4355 char *base_string;
252b5132 4356
47926f60 4357 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 4358 char *displacement_string_start;
4359 char *displacement_string_end;
252b5132 4360
24eab124 4361 do_memory_reference:
24eab124
AM		 4362 if ((i.mem_operands == 1
4363 && (current_templates->start->opcode_modifier & IsString) == 0)
4364 || i.mem_operands == 2)
4365 {
4366 as_bad (_("too many memory references for `%s'"),
4367 current_templates->start->name);
4368 return 0;
4369 }
252b5132 4370
24eab124
AM		 4371 /* Check for base index form. We detect the base index form by
4372 looking for an ')' at the end of the operand, searching
4373 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4374 after the '('. */
af6bdddf 4375 base_string = op_string + strlen (op_string);
c3332e24 4376
af6bdddf
AM		 4377 --base_string;
4378 if (is_space_char (*base_string))
4379 --base_string;
252b5132 4380
47926f60 4381 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 4382 displacement_string_start = op_string;
4383 displacement_string_end = base_string + 1;
252b5132 4384
24eab124
AM		 4385 if (*base_string == ')')
4386 {
af6bdddf 4387 char *temp_string;
24eab124
AM		 4388 unsigned int parens_balanced = 1;
4389 /* We've already checked that the number of left & right ()'s are
47926f60 4390 equal, so this loop will not be infinite. */
24eab124
AM		 4391 do
4392 {
4393 base_string--;
4394 if (*base_string == ')')
4395 parens_balanced++;
4396 if (*base_string == '(')
4397 parens_balanced--;
4398 }
4399 while (parens_balanced);
c3332e24 4400
af6bdddf 4401 temp_string = base_string;
c3332e24 4402
24eab124 4403 /* Skip past '(' and whitespace. */
252b5132
RH		 4404 ++base_string;
4405 if (is_space_char (*base_string))
24eab124 4406 ++base_string;
252b5132 4407
af6bdddf
AM		 4408 if (*base_string == ','
4409 || ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4410 && (i.base_reg = parse_register (base_string, &end_op)) != NULL))
252b5132 4411 {
af6bdddf 4412 displacement_string_end = temp_string;
252b5132 4413
af6bdddf 4414 i.types[this_operand] |= BaseIndex;
252b5132 4415
af6bdddf 4416 if (i.base_reg)
24eab124 4417 {
24eab124
AM		 4418 base_string = end_op;
4419 if (is_space_char (*base_string))
4420 ++base_string;
af6bdddf
AM		 4421 }
4422
4423 /* There may be an index reg or scale factor here. */
4424 if (*base_string == ',')
4425 {
4426 ++base_string;
4427 if (is_space_char (*base_string))
4428 ++base_string;
4429
4430 if ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4431 && (i.index_reg = parse_register (base_string, &end_op)) != NULL)
24eab124 4432 {
af6bdddf 4433 base_string = end_op;
24eab124
AM		 4434 if (is_space_char (*base_string))
4435 ++base_string;
af6bdddf
AM		 4436 if (*base_string == ',')
4437 {
4438 ++base_string;
4439 if (is_space_char (*base_string))
4440 ++base_string;
4441 }
e5cb08ac 4442 else if (*base_string != ')')
af6bdddf
AM		 4443 {
4444 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4445 operand_string);
4446 return 0;
4447 }
24eab124 4448 }
af6bdddf 4449 else if (*base_string == REGISTER_PREFIX)
24eab124 4450 {
af6bdddf 4451 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 4452 return 0;
4453 }
252b5132 4454
47926f60 4455 /* Check for scale factor. */
551c1ca1 4456 if (*base_string != ')')
af6bdddf 4457 {
551c1ca1
AM		 4458 char *end_scale = i386_scale (base_string);
4459
4460 if (!end_scale)
af6bdddf 4461 return 0;
24eab124 4462
551c1ca1 4463 base_string = end_scale;
af6bdddf
AM		 4464 if (is_space_char (*base_string))
4465 ++base_string;
4466 if (*base_string != ')')
4467 {
4468 as_bad (_("expecting `)' after scale factor in `%s'"),
4469 operand_string);
4470 return 0;
4471 }
4472 }
4473 else if (!i.index_reg)
24eab124 4474 {
af6bdddf
AM		 4475 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4476 *base_string);
24eab124
AM		 4477 return 0;
4478 }
4479 }
af6bdddf 4480 else if (*base_string != ')')
24eab124 4481 {
af6bdddf
AM		 4482 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4483 operand_string);
24eab124
AM		 4484 return 0;
4485 }
c3332e24 4486 }
af6bdddf 4487 else if (*base_string == REGISTER_PREFIX)
c3332e24 4488 {
af6bdddf 4489 as_bad (_("bad register name `%s'"), base_string);
24eab124 4490 return 0;
c3332e24 4491 }
24eab124
AM		 4492 }
4493
4494 /* If there's an expression beginning the operand, parse it,
4495 assuming displacement_string_start and
4496 displacement_string_end are meaningful. */
4497 if (displacement_string_start != displacement_string_end)
4498 {
4499 if (!i386_displacement (displacement_string_start,
4500 displacement_string_end))
4501 return 0;
4502 }
4503
4504 /* Special case for (%dx) while doing input/output op. */
4505 if (i.base_reg
4506 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
4507 && i.index_reg == 0
4508 && i.log2_scale_factor == 0
4509 && i.seg[i.mem_operands] == 0
4510 && (i.types[this_operand] & Disp) == 0)
4511 {
4512 i.types[this_operand] = InOutPortReg;
4513 return 1;
4514 }
4515
eecb386c
AM		 4516 if (i386_index_check (operand_string) == 0)
4517 return 0;
24eab124
AM		 4518 i.mem_operands++;
4519 }
4520 else
ce8a8b2f
AM		 4521 {
4522 /* It's not a memory operand; argh! */
24eab124
AM		 4523 as_bad (_("invalid char %s beginning operand %d `%s'"),
4524 output_invalid (*op_string),
4525 this_operand + 1,
4526 op_string);
4527 return 0;
4528 }
47926f60 4529 return 1; /* Normal return. */
252b5132
RH		 4530}
4531\f
ee7fcc42
AM		 4532/* md_estimate_size_before_relax()
4533
4534 Called just before relax() for rs_machine_dependent frags. The x86
4535 assembler uses these frags to handle variable size jump
4536 instructions.
4537
4538 Any symbol that is now undefined will not become defined.
4539 Return the correct fr_subtype in the frag.
4540 Return the initial "guess for variable size of frag" to caller.
4541 The guess is actually the growth beyond the fixed part. Whatever
4542 we do to grow the fixed or variable part contributes to our
4543 returned value. */
4544
252b5132
RH		 4545int
4546md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 4547 fragS *fragP;
4548 segT segment;
252b5132 4549{
252b5132 4550 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 4551 check for un-relaxable symbols. On an ELF system, we can't relax
4552 an externally visible symbol, because it may be overridden by a
4553 shared library. */
4554 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 4555#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
31312f95
AM		 4556 || (OUTPUT_FLAVOR == bfd_target_elf_flavour
4557 && (S_IS_EXTERNAL (fragP->fr_symbol)
4558 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 4559#endif
4560 )
252b5132 4561 {
b98ef147
AM		 4562 /* Symbol is undefined in this segment, or we need to keep a
4563 reloc so that weak symbols can be overridden. */
4564 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 4565 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 4566 unsigned char *opcode;
4567 int old_fr_fix;
f6af82bd 4568
ee7fcc42
AM		 4569 if (fragP->fr_var != NO_RELOC)
4570 reloc_type = fragP->fr_var;
b98ef147 4571 else if (size == 2)
f6af82bd
AM		 4572 reloc_type = BFD_RELOC_16_PCREL;
4573 else
4574 reloc_type = BFD_RELOC_32_PCREL;
252b5132 4575
ee7fcc42
AM		 4576 old_fr_fix = fragP->fr_fix;
4577 opcode = (unsigned char *) fragP->fr_opcode;
4578
fddf5b5b 4579 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 4580 {
fddf5b5b
AM		 4581 case UNCOND_JUMP:
4582 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 4583 opcode[0] = 0xe9;
252b5132 4584 fragP->fr_fix += size;
062cd5e7
AS		 4585 fix_new (fragP, old_fr_fix, size,
4586 fragP->fr_symbol,
4587 fragP->fr_offset, 1,
4588 reloc_type);
252b5132
RH		 4589 break;
4590
fddf5b5b 4591 case COND_JUMP86:
412167cb
AM		 4592 if (size == 2
4593 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 4594 {
4595 /* Negate the condition, and branch past an
4596 unconditional jump. */
4597 opcode[0] ^= 1;
4598 opcode[1] = 3;
4599 /* Insert an unconditional jump. */
4600 opcode[2] = 0xe9;
4601 /* We added two extra opcode bytes, and have a two byte
4602 offset. */
4603 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 4604 fix_new (fragP, old_fr_fix + 2, 2,
4605 fragP->fr_symbol,
4606 fragP->fr_offset, 1,
4607 reloc_type);
fddf5b5b
AM		 4608 break;
4609 }
4610 /* Fall through. */
4611
4612 case COND_JUMP:
412167cb
AM		 4613 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
4614 {
3e02c1cc
AM		 4615 fixS *fixP;
4616
412167cb 4617 fragP->fr_fix += 1;
3e02c1cc
AM		 4618 fixP = fix_new (fragP, old_fr_fix, 1,
4619 fragP->fr_symbol,
4620 fragP->fr_offset, 1,
4621 BFD_RELOC_8_PCREL);
4622 fixP->fx_signed = 1;
412167cb
AM		 4623 break;
4624 }
93c2a809 4625
24eab124 4626 /* This changes the byte-displacement jump 0x7N
fddf5b5b 4627 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 4628 opcode[1] = opcode[0] + 0x10;
f6af82bd 4629 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 4630 /* We've added an opcode byte. */
4631 fragP->fr_fix += 1 + size;
062cd5e7
AS		 4632 fix_new (fragP, old_fr_fix + 1, size,
4633 fragP->fr_symbol,
4634 fragP->fr_offset, 1,
4635 reloc_type);
252b5132 4636 break;
fddf5b5b
AM		 4637
4638 default:
4639 BAD_CASE (fragP->fr_subtype);
4640 break;
252b5132
RH		 4641 }
4642 frag_wane (fragP);
ee7fcc42 4643 return fragP->fr_fix - old_fr_fix;
252b5132 4644 }
93c2a809 4645
93c2a809
AM		 4646 /* Guess size depending on current relax state. Initially the relax
4647 state will correspond to a short jump and we return 1, because
4648 the variable part of the frag (the branch offset) is one byte
4649 long. However, we can relax a section more than once and in that
4650 case we must either set fr_subtype back to the unrelaxed state,
4651 or return the value for the appropriate branch. */
4652 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 4653}
4654
47926f60
KH		 4655/* Called after relax() is finished.
4656
4657 In: Address of frag.
4658 fr_type == rs_machine_dependent.
4659 fr_subtype is what the address relaxed to.
4660
4661 Out: Any fixSs and constants are set up.
4662 Caller will turn frag into a ".space 0". */
4663
252b5132
RH		 4664void
4665md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 4666 bfd *abfd ATTRIBUTE_UNUSED;
4667 segT sec ATTRIBUTE_UNUSED;
29b0f896 4668 fragS *fragP;
252b5132 4669{
29b0f896 4670 unsigned char *opcode;
252b5132 4671 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 4672 offsetT target_address;
4673 offsetT opcode_address;
252b5132 4674 unsigned int extension = 0;
847f7ad4 4675 offsetT displacement_from_opcode_start;
252b5132
RH		 4676
4677 opcode = (unsigned char *) fragP->fr_opcode;
4678
47926f60 4679 /* Address we want to reach in file space. */
252b5132 4680 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 4681
47926f60 4682 /* Address opcode resides at in file space. */
252b5132
RH		 4683 opcode_address = fragP->fr_address + fragP->fr_fix;
4684
47926f60 4685 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 4686 displacement_from_opcode_start = target_address - opcode_address;
4687
fddf5b5b 4688 if ((fragP->fr_subtype & BIG) == 0)
252b5132 4689 {
47926f60
KH		 4690 /* Don't have to change opcode. */
4691 extension = 1; /* 1 opcode + 1 displacement */
252b5132 4692 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 4693 }
4694 else
4695 {
4696 if (no_cond_jump_promotion
4697 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4698 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
252b5132 4699
fddf5b5b
AM		 4700 switch (fragP->fr_subtype)
4701 {
4702 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
4703 extension = 4; /* 1 opcode + 4 displacement */
4704 opcode[0] = 0xe9;
4705 where_to_put_displacement = &opcode[1];
4706 break;
252b5132 4707
fddf5b5b
AM		 4708 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
4709 extension = 2; /* 1 opcode + 2 displacement */
4710 opcode[0] = 0xe9;
4711 where_to_put_displacement = &opcode[1];
4712 break;
252b5132 4713
fddf5b5b
AM		 4714 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
4715 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
4716 extension = 5; /* 2 opcode + 4 displacement */
4717 opcode[1] = opcode[0] + 0x10;
4718 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4719 where_to_put_displacement = &opcode[2];
4720 break;
252b5132 4721
fddf5b5b
AM		 4722 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
4723 extension = 3; /* 2 opcode + 2 displacement */
4724 opcode[1] = opcode[0] + 0x10;
4725 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4726 where_to_put_displacement = &opcode[2];
4727 break;
252b5132 4728
fddf5b5b
AM		 4729 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
4730 extension = 4;
4731 opcode[0] ^= 1;
4732 opcode[1] = 3;
4733 opcode[2] = 0xe9;
4734 where_to_put_displacement = &opcode[3];
4735 break;
4736
4737 default:
4738 BAD_CASE (fragP->fr_subtype);
4739 break;
4740 }
252b5132 4741 }
fddf5b5b 4742
47926f60 4743 /* Now put displacement after opcode. */
252b5132
RH		 4744 md_number_to_chars ((char *) where_to_put_displacement,
4745 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 4746 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 4747 fragP->fr_fix += extension;
4748}
4749\f
47926f60
KH		 4750/* Size of byte displacement jmp. */
4751int md_short_jump_size = 2;
4752
4753/* Size of dword displacement jmp. */
4754int md_long_jump_size = 5;
252b5132 4755
47926f60
KH		 4756/* Size of relocation record. */
4757const int md_reloc_size = 8;
252b5132
RH		 4758
4759void
4760md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4761 char *ptr;
4762 addressT from_addr, to_addr;
ab9da554
ILT		 4763 fragS *frag ATTRIBUTE_UNUSED;
4764 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4765{
847f7ad4 4766 offsetT offset;
252b5132
RH		 4767
4768 offset = to_addr - (from_addr + 2);
47926f60
KH		 4769 /* Opcode for byte-disp jump. */
4770 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 4771 md_number_to_chars (ptr + 1, (valueT) offset, 1);
4772}
4773
4774void
4775md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4776 char *ptr;
4777 addressT from_addr, to_addr;
a38cf1db
AM		 4778 fragS *frag ATTRIBUTE_UNUSED;
4779 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4780{
847f7ad4 4781 offsetT offset;
252b5132 4782
a38cf1db
AM		 4783 offset = to_addr - (from_addr + 5);
4784 md_number_to_chars (ptr, (valueT) 0xe9, 1);
4785 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 4786}
4787\f
4788/* Apply a fixup (fixS) to segment data, once it has been determined
4789 by our caller that we have all the info we need to fix it up.
4790
4791 On the 386, immediates, displacements, and data pointers are all in
4792 the same (little-endian) format, so we don't need to care about which
4793 we are handling. */
4794
94f592af 4795void
55cf6793 4796md_apply_fix (fixP, valP, seg)
47926f60
KH		 4797 /* The fix we're to put in. */
4798 fixS *fixP;
47926f60 4799 /* Pointer to the value of the bits. */
c6682705 4800 valueT *valP;
47926f60
KH		 4801 /* Segment fix is from. */
4802 segT seg ATTRIBUTE_UNUSED;
252b5132 4803{
94f592af 4804 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 4805 valueT value = *valP;
252b5132 4806
f86103b7 4807#if !defined (TE_Mach)
93382f6d
AM		 4808 if (fixP->fx_pcrel)
4809 {
4810 switch (fixP->fx_r_type)
4811 {
5865bb77
ILT		 4812 default:
4813 break;
4814
93382f6d 4815 case BFD_RELOC_32:
ae8887b5 4816 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 4817 fixP->fx_r_type = BFD_RELOC_32_PCREL;
4818 break;
4819 case BFD_RELOC_16:
4820 fixP->fx_r_type = BFD_RELOC_16_PCREL;
4821 break;
4822 case BFD_RELOC_8:
4823 fixP->fx_r_type = BFD_RELOC_8_PCREL;
4824 break;
4825 }
4826 }
252b5132 4827
a161fe53 4828 if (fixP->fx_addsy != NULL
31312f95
AM		 4829 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
4830 || fixP->fx_r_type == BFD_RELOC_16_PCREL
4831 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4832 && !use_rela_relocations)
252b5132 4833 {
31312f95
AM		 4834 /* This is a hack. There should be a better way to handle this.
4835 This covers for the fact that bfd_install_relocation will
4836 subtract the current location (for partial_inplace, PC relative
4837 relocations); see more below. */
252b5132
RH		 4838#ifndef OBJ_AOUT
4839 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4840#ifdef TE_PE
4841 || OUTPUT_FLAVOR == bfd_target_coff_flavour
4842#endif
4843 )
4844 value += fixP->fx_where + fixP->fx_frag->fr_address;
4845#endif
4846#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2f66722d 4847 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
252b5132 4848 {
6539b54b 4849 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 4850
6539b54b 4851 if ((sym_seg == seg
2f66722d 4852 || (symbol_section_p (fixP->fx_addsy)
6539b54b 4853 && sym_seg != absolute_section))
ae6063d4 4854 && !generic_force_reloc (fixP))
2f66722d
AM		 4855 {
4856 /* Yes, we add the values in twice. This is because
6539b54b
AM		 4857 bfd_install_relocation subtracts them out again. I think
4858 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 4859 it. FIXME. */
4860 value += fixP->fx_where + fixP->fx_frag->fr_address;
4861 }
252b5132
RH		 4862 }
4863#endif
4864#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 4865 /* For some reason, the PE format does not store a
4866 section address offset for a PC relative symbol. */
4867 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
4868#if defined(BFD_ASSEMBLER) || defined(S_IS_WEAK)
4869 || S_IS_WEAK (fixP->fx_addsy)
4870#endif
4871 )
252b5132
RH		 4872 value += md_pcrel_from (fixP);
4873#endif
4874 }
4875
4876 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 4877 and we must not disappoint it. */
252b5132
RH		 4878#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4879 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4880 && fixP->fx_addsy)
47926f60
KH		 4881 switch (fixP->fx_r_type)
4882 {
4883 case BFD_RELOC_386_PLT32:
3e73aa7c 4884 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 4885 /* Make the jump instruction point to the address of the operand. At
4886 runtime we merely add the offset to the actual PLT entry. */
4887 value = -4;
4888 break;
31312f95 4889
13ae64f3
JJ		 4890 case BFD_RELOC_386_TLS_GD:
4891 case BFD_RELOC_386_TLS_LDM:
13ae64f3 4892 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 4893 case BFD_RELOC_386_TLS_IE:
4894 case BFD_RELOC_386_TLS_GOTIE:
bffbf940
JJ		 4895 case BFD_RELOC_X86_64_TLSGD:
4896 case BFD_RELOC_X86_64_TLSLD:
4897 case BFD_RELOC_X86_64_GOTTPOFF:
00f7efb6
JJ		 4898 value = 0; /* Fully resolved at runtime. No addend. */
4899 /* Fallthrough */
4900 case BFD_RELOC_386_TLS_LE:
4901 case BFD_RELOC_386_TLS_LDO_32:
4902 case BFD_RELOC_386_TLS_LE_32:
4903 case BFD_RELOC_X86_64_DTPOFF32:
4904 case BFD_RELOC_X86_64_TPOFF32:
4905 S_SET_THREAD_LOCAL (fixP->fx_addsy);
4906 break;
4907
4908 case BFD_RELOC_386_GOT32:
4909 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 4910 value = 0; /* Fully resolved at runtime. No addend. */
4911 break;
47926f60
KH		 4912
4913 case BFD_RELOC_VTABLE_INHERIT:
4914 case BFD_RELOC_VTABLE_ENTRY:
4915 fixP->fx_done = 0;
94f592af 4916 return;
47926f60
KH		 4917
4918 default:
4919 break;
4920 }
4921#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 4922 *valP = value;
f86103b7 4923#endif /* !defined (TE_Mach) */
3e73aa7c 4924
3e73aa7c 4925 /* Are we finished with this relocation now? */
c6682705 4926 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 4927 fixP->fx_done = 1;
4928 else if (use_rela_relocations)
4929 {
4930 fixP->fx_no_overflow = 1;
062cd5e7
AS		 4931 /* Remember value for tc_gen_reloc. */
4932 fixP->fx_addnumber = value;
3e73aa7c
JH		 4933 value = 0;
4934 }
f86103b7 4935
94f592af 4936 md_number_to_chars (p, value, fixP->fx_size);
252b5132 4937}
252b5132 4938\f
252b5132
RH		 4939#define MAX_LITTLENUMS 6
4940
47926f60
KH		 4941/* Turn the string pointed to by litP into a floating point constant
4942 of type TYPE, and emit the appropriate bytes. The number of
4943 LITTLENUMS emitted is stored in *SIZEP. An error message is
4944 returned, or NULL on OK. */
4945
252b5132
RH		 4946char *
4947md_atof (type, litP, sizeP)
2ab9b79e 4948 int type;
252b5132
RH		 4949 char *litP;
4950 int *sizeP;
4951{
4952 int prec;
4953 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4954 LITTLENUM_TYPE *wordP;
4955 char *t;
4956
4957 switch (type)
4958 {
4959 case 'f':
4960 case 'F':
4961 prec = 2;
4962 break;
4963
4964 case 'd':
4965 case 'D':
4966 prec = 4;
4967 break;
4968
4969 case 'x':
4970 case 'X':
4971 prec = 5;
4972 break;
4973
4974 default:
4975 *sizeP = 0;
4976 return _("Bad call to md_atof ()");
4977 }
4978 t = atof_ieee (input_line_pointer, type, words);
4979 if (t)
4980 input_line_pointer = t;
4981
4982 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4983 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4984 the bigendian 386. */
4985 for (wordP = words + prec - 1; prec--;)
4986 {
4987 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
4988 litP += sizeof (LITTLENUM_TYPE);
4989 }
4990 return 0;
4991}
4992\f
87c245cc 4993static char output_invalid_buf[8];
252b5132 4994
252b5132
RH		 4995static char *
4996output_invalid (c)
4997 int c;
4998{
3882b010 4999 if (ISPRINT (c))
252b5132
RH		 5000 sprintf (output_invalid_buf, "'%c'", c);
5001 else
5002 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
5003 return output_invalid_buf;
5004}
5005
af6bdddf 5006/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 5007
5008static const reg_entry *
5009parse_register (reg_string, end_op)
5010 char *reg_string;
5011 char **end_op;
5012{
af6bdddf
AM		 5013 char *s = reg_string;
5014 char *p;
252b5132
RH		 5015 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5016 const reg_entry *r;
5017
5018 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5019 if (*s == REGISTER_PREFIX)
5020 ++s;
5021
5022 if (is_space_char (*s))
5023 ++s;
5024
5025 p = reg_name_given;
af6bdddf 5026 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 5027 {
5028 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 5029 return (const reg_entry *) NULL;
5030 s++;
252b5132
RH		 5031 }
5032
6588847e
DN		 5033 /* For naked regs, make sure that we are not dealing with an identifier.
5034 This prevents confusing an identifier like `eax_var' with register
5035 `eax'. */
5036 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5037 return (const reg_entry *) NULL;
5038
af6bdddf 5039 *end_op = s;
252b5132
RH		 5040
5041 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5042
5f47d35b 5043 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 5044 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 5045 {
5f47d35b
AM		 5046 if (is_space_char (*s))
5047 ++s;
5048 if (*s == '(')
5049 {
af6bdddf 5050 ++s;
5f47d35b
AM		 5051 if (is_space_char (*s))
5052 ++s;
5053 if (*s >= '0' && *s <= '7')
5054 {
5055 r = &i386_float_regtab[*s - '0'];
af6bdddf 5056 ++s;
5f47d35b
AM		 5057 if (is_space_char (*s))
5058 ++s;
5059 if (*s == ')')
5060 {
5061 *end_op = s + 1;
5062 return r;
5063 }
5f47d35b 5064 }
47926f60 5065 /* We have "%st(" then garbage. */
5f47d35b
AM		 5066 return (const reg_entry *) NULL;
5067 }
5068 }
5069
1ae00879 5070 if (r != NULL
20f0a1fc 5071 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
c4a530c5 5072 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
1ae00879 5073 && flag_code != CODE_64BIT)
20f0a1fc 5074 return (const reg_entry *) NULL;
1ae00879 5075
252b5132
RH		 5076 return r;
5077}
5078\f
4cc782b5 5079#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 5080const char *md_shortopts = "kVQ:sqn";
252b5132 5081#else
12b55ccc 5082const char *md_shortopts = "qn";
252b5132 5083#endif
6e0b89ee 5084
252b5132 5085struct option md_longopts[] = {
3e73aa7c
JH		 5086#define OPTION_32 (OPTION_MD_BASE + 0)
5087 {"32", no_argument, NULL, OPTION_32},
6e0b89ee 5088#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3e73aa7c
JH		 5089#define OPTION_64 (OPTION_MD_BASE + 1)
5090 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 5091#endif
252b5132
RH		 5092 {NULL, no_argument, NULL, 0}
5093};
5094size_t md_longopts_size = sizeof (md_longopts);
5095
5096int
5097md_parse_option (c, arg)
5098 int c;
ab9da554 5099 char *arg ATTRIBUTE_UNUSED;
252b5132
RH		 5100{
5101 switch (c)
5102 {
12b55ccc
L		 5103 case 'n':
5104 optimize_align_code = 0;
5105 break;
5106
a38cf1db
AM		 5107 case 'q':
5108 quiet_warnings = 1;
252b5132
RH		 5109 break;
5110
5111#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 5112 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5113 should be emitted or not. FIXME: Not implemented. */
5114 case 'Q':
252b5132
RH		 5115 break;
5116
5117 /* -V: SVR4 argument to print version ID. */
5118 case 'V':
5119 print_version_id ();
5120 break;
5121
a38cf1db
AM		 5122 /* -k: Ignore for FreeBSD compatibility. */
5123 case 'k':
252b5132 5124 break;
4cc782b5
ILT		 5125
5126 case 's':
5127 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 5128 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 5129 break;
6e0b89ee 5130
3e73aa7c
JH		 5131 case OPTION_64:
5132 {
5133 const char **list, **l;
5134
3e73aa7c
JH		 5135 list = bfd_target_list ();
5136 for (l = list; *l != NULL; l++)
6e0b89ee
AM		 5137 if (strcmp (*l, "elf64-x86-64") == 0)
5138 {
5139 default_arch = "x86_64";
5140 break;
5141 }
3e73aa7c 5142 if (*l == NULL)
6e0b89ee 5143 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 5144 free (list);
5145 }
5146 break;
5147#endif
252b5132 5148
6e0b89ee
AM		 5149 case OPTION_32:
5150 default_arch = "i386";
5151 break;
5152
252b5132
RH		 5153 default:
5154 return 0;
5155 }
5156 return 1;
5157}
5158
5159void
5160md_show_usage (stream)
5161 FILE *stream;
5162{
4cc782b5
ILT		 5163#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5164 fprintf (stream, _("\
a38cf1db
AM		 5165 -Q ignored\n\
5166 -V print assembler version number\n\
5167 -k ignored\n\
12b55ccc 5168 -n Do not optimize code alignment\n\
a38cf1db
AM		 5169 -q quieten some warnings\n\
5170 -s ignored\n"));
5171#else
5172 fprintf (stream, _("\
12b55ccc 5173 -n Do not optimize code alignment\n\
a38cf1db 5174 -q quieten some warnings\n"));
4cc782b5 5175#endif
252b5132
RH		 5176}
5177
3e73aa7c
JH		 5178#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5179 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 5180
5181/* Pick the target format to use. */
5182
47926f60 5183const char *
252b5132
RH		 5184i386_target_format ()
5185{
3e73aa7c
JH		 5186 if (!strcmp (default_arch, "x86_64"))
5187 set_code_flag (CODE_64BIT);
5188 else if (!strcmp (default_arch, "i386"))
5189 set_code_flag (CODE_32BIT);
5190 else
5191 as_fatal (_("Unknown architecture"));
252b5132
RH		 5192 switch (OUTPUT_FLAVOR)
5193 {
4c63da97
AM		 5194#ifdef OBJ_MAYBE_AOUT
5195 case bfd_target_aout_flavour:
47926f60 5196 return AOUT_TARGET_FORMAT;
4c63da97
AM		 5197#endif
5198#ifdef OBJ_MAYBE_COFF
252b5132
RH		 5199 case bfd_target_coff_flavour:
5200 return "coff-i386";
4c63da97 5201#endif
3e73aa7c 5202#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 5203 case bfd_target_elf_flavour:
3e73aa7c 5204 {
e5cb08ac
KH		 5205 if (flag_code == CODE_64BIT)
5206 use_rela_relocations = 1;
4ada7262 5207 return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT;
3e73aa7c 5208 }
4c63da97 5209#endif
252b5132
RH		 5210 default:
5211 abort ();
5212 return NULL;
5213 }
5214}
5215
47926f60 5216#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 5217
5218#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5219void i386_elf_emit_arch_note ()
5220{
5221 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
5222 && cpu_arch_name != NULL)
5223 {
5224 char *p;
5225 asection *seg = now_seg;
5226 subsegT subseg = now_subseg;
5227 Elf_Internal_Note i_note;
5228 Elf_External_Note e_note;
5229 asection *note_secp;
5230 int len;
5231
5232 /* Create the .note section. */
5233 note_secp = subseg_new (".note", 0);
5234 bfd_set_section_flags (stdoutput,
5235 note_secp,
5236 SEC_HAS_CONTENTS | SEC_READONLY);
5237
5238 /* Process the arch string. */
5239 len = strlen (cpu_arch_name);
5240
5241 i_note.namesz = len + 1;
5242 i_note.descsz = 0;
5243 i_note.type = NT_ARCH;
5244 p = frag_more (sizeof (e_note.namesz));
5245 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
5246 p = frag_more (sizeof (e_note.descsz));
5247 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
5248 p = frag_more (sizeof (e_note.type));
5249 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
5250 p = frag_more (len + 1);
5251 strcpy (p, cpu_arch_name);
5252
5253 frag_align (2, 0, 0);
5254
5255 subseg_set (seg, subseg);
5256 }
5257}
5258#endif
252b5132 5259\f
252b5132
RH		 5260symbolS *
5261md_undefined_symbol (name)
5262 char *name;
5263{
18dc2407
ILT		 5264 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
5265 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
5266 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
5267 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 5268 {
5269 if (!GOT_symbol)
5270 {
5271 if (symbol_find (name))
5272 as_bad (_("GOT already in symbol table"));
5273 GOT_symbol = symbol_new (name, undefined_section,
5274 (valueT) 0, &zero_address_frag);
5275 };
5276 return GOT_symbol;
5277 }
252b5132
RH		 5278 return 0;
5279}
5280
5281/* Round up a section size to the appropriate boundary. */
47926f60 5282
252b5132
RH		 5283valueT
5284md_section_align (segment, size)
ab9da554 5285 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 5286 valueT size;
5287{
4c63da97
AM		 5288#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5289 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
5290 {
5291 /* For a.out, force the section size to be aligned. If we don't do
5292 this, BFD will align it for us, but it will not write out the
5293 final bytes of the section. This may be a bug in BFD, but it is
5294 easier to fix it here since that is how the other a.out targets
5295 work. */
5296 int align;
5297
5298 align = bfd_get_section_alignment (stdoutput, segment);
5299 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
5300 }
252b5132
RH		 5301#endif
5302
5303 return size;
5304}
5305
5306/* On the i386, PC-relative offsets are relative to the start of the
5307 next instruction. That is, the address of the offset, plus its
5308 size, since the offset is always the last part of the insn. */
5309
5310long
5311md_pcrel_from (fixP)
5312 fixS *fixP;
5313{
5314 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
5315}
5316
5317#ifndef I386COFF
5318
5319static void
5320s_bss (ignore)
ab9da554 5321 int ignore ATTRIBUTE_UNUSED;
252b5132 5322{
29b0f896 5323 int temp;
252b5132 5324
8a75718c
JB		 5325#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5326 if (IS_ELF)
5327 obj_elf_section_change_hook ();
5328#endif
252b5132
RH		 5329 temp = get_absolute_expression ();
5330 subseg_set (bss_section, (subsegT) temp);
5331 demand_empty_rest_of_line ();
5332}
5333
5334#endif
5335
252b5132
RH		 5336void
5337i386_validate_fix (fixp)
5338 fixS *fixp;
5339{
5340 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
5341 {
3e73aa7c 5342 /* GOTOFF relocation are nonsense in 64bit mode. */
23df1078
JH		 5343 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
5344 {
5345 if (flag_code != CODE_64BIT)
5346 abort ();
5347 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
5348 }
5349 else
5350 {
5351 if (flag_code == CODE_64BIT)
5352 abort ();
5353 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
5354 }
252b5132
RH		 5355 fixp->fx_subsy = 0;
5356 }
5357}
5358
252b5132
RH		 5359arelent *
5360tc_gen_reloc (section, fixp)
ab9da554 5361 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 5362 fixS *fixp;
5363{
5364 arelent *rel;
5365 bfd_reloc_code_real_type code;
5366
5367 switch (fixp->fx_r_type)
5368 {
3e73aa7c
JH		 5369 case BFD_RELOC_X86_64_PLT32:
5370 case BFD_RELOC_X86_64_GOT32:
5371 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 5372 case BFD_RELOC_386_PLT32:
5373 case BFD_RELOC_386_GOT32:
5374 case BFD_RELOC_386_GOTOFF:
5375 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 5376 case BFD_RELOC_386_TLS_GD:
5377 case BFD_RELOC_386_TLS_LDM:
5378 case BFD_RELOC_386_TLS_LDO_32:
5379 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5380 case BFD_RELOC_386_TLS_IE:
5381 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 5382 case BFD_RELOC_386_TLS_LE_32:
5383 case BFD_RELOC_386_TLS_LE:
bffbf940
JJ		 5384 case BFD_RELOC_X86_64_TLSGD:
5385 case BFD_RELOC_X86_64_TLSLD:
5386 case BFD_RELOC_X86_64_DTPOFF32:
5387 case BFD_RELOC_X86_64_GOTTPOFF:
5388 case BFD_RELOC_X86_64_TPOFF32:
252b5132
RH		 5389 case BFD_RELOC_RVA:
5390 case BFD_RELOC_VTABLE_ENTRY:
5391 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 5392#ifdef TE_PE
5393 case BFD_RELOC_32_SECREL:
5394#endif
252b5132
RH		 5395 code = fixp->fx_r_type;
5396 break;
dbbaec26
L		 5397 case BFD_RELOC_X86_64_32S:
5398 if (!fixp->fx_pcrel)
5399 {
5400 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
5401 code = fixp->fx_r_type;
5402 break;
5403 }
252b5132 5404 default:
93382f6d 5405 if (fixp->fx_pcrel)
252b5132 5406 {
93382f6d
AM		 5407 switch (fixp->fx_size)
5408 {
5409 default:
b091f402
AM		 5410 as_bad_where (fixp->fx_file, fixp->fx_line,
5411 _("can not do %d byte pc-relative relocation"),
5412 fixp->fx_size);
93382f6d
AM		 5413 code = BFD_RELOC_32_PCREL;
5414 break;
5415 case 1: code = BFD_RELOC_8_PCREL; break;
5416 case 2: code = BFD_RELOC_16_PCREL; break;
5417 case 4: code = BFD_RELOC_32_PCREL; break;
5418 }
5419 }
5420 else
5421 {
5422 switch (fixp->fx_size)
5423 {
5424 default:
b091f402
AM		 5425 as_bad_where (fixp->fx_file, fixp->fx_line,
5426 _("can not do %d byte relocation"),
5427 fixp->fx_size);
93382f6d
AM		 5428 code = BFD_RELOC_32;
5429 break;
5430 case 1: code = BFD_RELOC_8; break;
5431 case 2: code = BFD_RELOC_16; break;
5432 case 4: code = BFD_RELOC_32; break;
937149dd 5433#ifdef BFD64
3e73aa7c 5434 case 8: code = BFD_RELOC_64; break;
937149dd 5435#endif
93382f6d 5436 }
252b5132
RH		 5437 }
5438 break;
5439 }
252b5132
RH		 5440
5441 if (code == BFD_RELOC_32
5442 && GOT_symbol
5443 && fixp->fx_addsy == GOT_symbol)
3e73aa7c
JH		 5444 {
5445 /* We don't support GOTPC on 64bit targets. */
5446 if (flag_code == CODE_64BIT)
bfb32b52 5447 abort ();
3e73aa7c
JH		 5448 code = BFD_RELOC_386_GOTPC;
5449 }
252b5132
RH		 5450
5451 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 5452 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5453 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 5454
5455 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 5456
3e73aa7c
JH		 5457 if (!use_rela_relocations)
5458 {
5459 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5460 vtable entry to be used in the relocation's section offset. */
5461 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5462 rel->address = fixp->fx_offset;
252b5132 5463
c6682705 5464 rel->addend = 0;
3e73aa7c
JH		 5465 }
5466 /* Use the rela in 64bit mode. */
252b5132 5467 else
3e73aa7c 5468 {
062cd5e7
AS		 5469 if (!fixp->fx_pcrel)
5470 rel->addend = fixp->fx_offset;
5471 else
5472 switch (code)
5473 {
5474 case BFD_RELOC_X86_64_PLT32:
5475 case BFD_RELOC_X86_64_GOT32:
5476 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 5477 case BFD_RELOC_X86_64_TLSGD:
5478 case BFD_RELOC_X86_64_TLSLD:
5479 case BFD_RELOC_X86_64_GOTTPOFF:
062cd5e7
AS		 5480 rel->addend = fixp->fx_offset - fixp->fx_size;
5481 break;
5482 default:
5483 rel->addend = (section->vma
5484 - fixp->fx_size
5485 + fixp->fx_addnumber
5486 + md_pcrel_from (fixp));
5487 break;
5488 }
3e73aa7c
JH		 5489 }
5490
252b5132
RH		 5491 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
5492 if (rel->howto == NULL)
5493 {
5494 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 5495 _("cannot represent relocation type %s"),
252b5132
RH		 5496 bfd_get_reloc_code_name (code));
5497 /* Set howto to a garbage value so that we can keep going. */
5498 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
5499 assert (rel->howto != NULL);
5500 }
5501
5502 return rel;
5503}
5504
64a0c779
DN		 5505\f
5506/* Parse operands using Intel syntax. This implements a recursive descent
5507 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5508 Programmer's Guide.
5509
5510 FIXME: We do not recognize the full operand grammar defined in the MASM
5511 documentation. In particular, all the structure/union and
5512 high-level macro operands are missing.
5513
5514 Uppercase words are terminals, lower case words are non-terminals.
5515 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5516 bars '|' denote choices. Most grammar productions are implemented in
5517 functions called 'intel_<production>'.
5518
5519 Initial production is 'expr'.
5520
9306ca4a 5521 addOp + | -
64a0c779
DN		 5522
5523 alpha [a-zA-Z]
5524
9306ca4a
JB		 5525 binOp & | AND | \| | OR | ^ | XOR
5526
64a0c779
DN		 5527 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5528
5529 constant digits [[ radixOverride ]]
5530
9306ca4a 5531 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 5532
5533 digits decdigit
b77a7acd
AJ		 5534 | digits decdigit
5535 | digits hexdigit
64a0c779
DN		 5536
5537 decdigit [0-9]
5538
9306ca4a
JB		 5539 e04 e04 addOp e05
5540 | e05
5541
5542 e05 e05 binOp e06
b77a7acd 5543 | e06
64a0c779
DN		 5544
5545 e06 e06 mulOp e09
b77a7acd 5546 | e09
64a0c779
DN		 5547
5548 e09 OFFSET e10
a724f0f4
JB		 5549 | SHORT e10
5550 | + e10
5551 | - e10
9306ca4a
JB		 5552 | ~ e10
5553 | NOT e10
64a0c779
DN		 5554 | e09 PTR e10
5555 | e09 : e10
5556 | e10
5557
5558 e10 e10 [ expr ]
b77a7acd 5559 | e11
64a0c779
DN		 5560
5561 e11 ( expr )
b77a7acd 5562 | [ expr ]
64a0c779
DN		 5563 | constant
5564 | dataType
5565 | id
5566 | $
5567 | register
5568
a724f0f4 5569 => expr expr cmpOp e04
9306ca4a 5570 | e04
64a0c779
DN		 5571
5572 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 5573 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 5574
5575 hexdigit a | b | c | d | e | f
b77a7acd 5576 | A | B | C | D | E | F
64a0c779
DN		 5577
5578 id alpha
b77a7acd 5579 | id alpha
64a0c779
DN		 5580 | id decdigit
5581
9306ca4a 5582 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 5583
5584 quote " | '
5585
5586 register specialRegister
b77a7acd 5587 | gpRegister
64a0c779
DN		 5588 | byteRegister
5589
5590 segmentRegister CS | DS | ES | FS | GS | SS
5591
9306ca4a 5592 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 5593 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 5594 | TR3 | TR4 | TR5 | TR6 | TR7
5595
64a0c779
DN		 5596 We simplify the grammar in obvious places (e.g., register parsing is
5597 done by calling parse_register) and eliminate immediate left recursion
5598 to implement a recursive-descent parser.
5599
a724f0f4
JB		 5600 expr e04 expr'
5601
5602 expr' cmpOp e04 expr'
5603 | Empty
9306ca4a
JB		 5604
5605 e04 e05 e04'
5606
5607 e04' addOp e05 e04'
5608 | Empty
64a0c779
DN		 5609
5610 e05 e06 e05'
5611
9306ca4a 5612 e05' binOp e06 e05'
b77a7acd 5613 | Empty
64a0c779
DN		 5614
5615 e06 e09 e06'
5616
5617 e06' mulOp e09 e06'
b77a7acd 5618 | Empty
64a0c779
DN		 5619
5620 e09 OFFSET e10 e09'
a724f0f4
JB		 5621 | SHORT e10'
5622 | + e10'
5623 | - e10'
5624 | ~ e10'
5625 | NOT e10'
b77a7acd 5626 | e10 e09'
64a0c779
DN		 5627
5628 e09' PTR e10 e09'
b77a7acd 5629 | : e10 e09'
64a0c779
DN		 5630 | Empty
5631
5632 e10 e11 e10'
5633
5634 e10' [ expr ] e10'
b77a7acd 5635 | Empty
64a0c779
DN		 5636
5637 e11 ( expr )
b77a7acd 5638 | [ expr ]
64a0c779
DN		 5639 | BYTE
5640 | WORD
5641 | DWORD
9306ca4a 5642 | FWORD
64a0c779 5643 | QWORD
9306ca4a
JB		 5644 | TBYTE
5645 | OWORD
5646 | XMMWORD
64a0c779
DN		 5647 | .
5648 | $
5649 | register
5650 | id
5651 | constant */
5652
5653/* Parsing structure for the intel syntax parser. Used to implement the
5654 semantic actions for the operand grammar. */
5655struct intel_parser_s
5656 {
5657 char *op_string; /* The string being parsed. */
5658 int got_a_float; /* Whether the operand is a float. */
4a1805b1 5659 int op_modifier; /* Operand modifier. */
64a0c779 5660 int is_mem; /* 1 if operand is memory reference. */
a724f0f4
JB		 5661 int in_offset; /* >=1 if parsing operand of offset. */
5662 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 5663 const reg_entry *reg; /* Last register reference found. */
5664 char *disp; /* Displacement string being built. */
a724f0f4 5665 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 5666 };
5667
5668static struct intel_parser_s intel_parser;
5669
5670/* Token structure for parsing intel syntax. */
5671struct intel_token
5672 {
5673 int code; /* Token code. */
5674 const reg_entry *reg; /* Register entry for register tokens. */
5675 char *str; /* String representation. */
5676 };
5677
5678static struct intel_token cur_token, prev_token;
5679
50705ef4
AM		 5680/* Token codes for the intel parser. Since T_SHORT is already used
5681 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 5682#define T_NIL -1
5683#define T_CONST 1
5684#define T_REG 2
5685#define T_BYTE 3
5686#define T_WORD 4
9306ca4a
JB		 5687#define T_DWORD 5
5688#define T_FWORD 6
5689#define T_QWORD 7
5690#define T_TBYTE 8
5691#define T_XMMWORD 9
50705ef4 5692#undef T_SHORT
9306ca4a
JB		 5693#define T_SHORT 10
5694#define T_OFFSET 11
5695#define T_PTR 12
5696#define T_ID 13
5697#define T_SHL 14
5698#define T_SHR 15
64a0c779
DN		 5699
5700/* Prototypes for intel parser functions. */
5701static int intel_match_token PARAMS ((int code));
cce0cbdc
DN		 5702static void intel_get_token PARAMS ((void));
5703static void intel_putback_token PARAMS ((void));
5704static int intel_expr PARAMS ((void));
9306ca4a 5705static int intel_e04 PARAMS ((void));
cce0cbdc 5706static int intel_e05 PARAMS ((void));
cce0cbdc 5707static int intel_e06 PARAMS ((void));
cce0cbdc 5708static int intel_e09 PARAMS ((void));
a724f0f4 5709static int intel_bracket_expr PARAMS ((void));
cce0cbdc 5710static int intel_e10 PARAMS ((void));
cce0cbdc 5711static int intel_e11 PARAMS ((void));
64a0c779 5712
64a0c779
DN		 5713static int
5714i386_intel_operand (operand_string, got_a_float)
5715 char *operand_string;
5716 int got_a_float;
5717{
5718 int ret;
5719 char *p;
5720
a724f0f4
JB		 5721 p = intel_parser.op_string = xstrdup (operand_string);
5722 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
5723
5724 for (;;)
64a0c779 5725 {
a724f0f4
JB		 5726 /* Initialize token holders. */
5727 cur_token.code = prev_token.code = T_NIL;
5728 cur_token.reg = prev_token.reg = NULL;
5729 cur_token.str = prev_token.str = NULL;
5730
5731 /* Initialize parser structure. */
5732 intel_parser.got_a_float = got_a_float;
5733 intel_parser.op_modifier = 0;
5734 intel_parser.is_mem = 0;
5735 intel_parser.in_offset = 0;
5736 intel_parser.in_bracket = 0;
5737 intel_parser.reg = NULL;
5738 intel_parser.disp[0] = '\0';
5739 intel_parser.next_operand = NULL;
5740
5741 /* Read the first token and start the parser. */
5742 intel_get_token ();
5743 ret = intel_expr ();
5744
5745 if (!ret)
5746 break;
5747
9306ca4a
JB		 5748 if (cur_token.code != T_NIL)
5749 {
5750 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
5751 current_templates->start->name, cur_token.str);
5752 ret = 0;
5753 }
64a0c779
DN		 5754 /* If we found a memory reference, hand it over to i386_displacement
5755 to fill in the rest of the operand fields. */
9306ca4a 5756 else if (intel_parser.is_mem)
64a0c779
DN		 5757 {
5758 if ((i.mem_operands == 1
5759 && (current_templates->start->opcode_modifier & IsString) == 0)
5760 || i.mem_operands == 2)
5761 {
5762 as_bad (_("too many memory references for '%s'"),
5763 current_templates->start->name);
5764 ret = 0;
5765 }
5766 else
5767 {
5768 char *s = intel_parser.disp;
5769 i.mem_operands++;
5770
a724f0f4
JB		 5771 if (!quiet_warnings && intel_parser.is_mem < 0)
5772 /* See the comments in intel_bracket_expr. */
5773 as_warn (_("Treating `%s' as memory reference"), operand_string);
5774
64a0c779
DN		 5775 /* Add the displacement expression. */
5776 if (*s != '\0')
a4622f40
AM		 5777 ret = i386_displacement (s, s + strlen (s));
5778 if (ret)
a724f0f4
JB		 5779 {
5780 /* Swap base and index in 16-bit memory operands like
5781 [si+bx]. Since i386_index_check is also used in AT&T
5782 mode we have to do that here. */
5783 if (i.base_reg
5784 && i.index_reg
5785 && (i.base_reg->reg_type & Reg16)
5786 && (i.index_reg->reg_type & Reg16)
5787 && i.base_reg->reg_num >= 6
5788 && i.index_reg->reg_num < 6)
5789 {
5790 const reg_entry *base = i.index_reg;
5791
5792 i.index_reg = i.base_reg;
5793 i.base_reg = base;
5794 }
5795 ret = i386_index_check (operand_string);
5796 }
64a0c779
DN		 5797 }
5798 }
5799
5800 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 5801 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 5802 || intel_parser.reg == NULL)
5803 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 5804
5805 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
5806 ret = 0;
5807 if (!ret || !intel_parser.next_operand)
5808 break;
5809 intel_parser.op_string = intel_parser.next_operand;
5810 this_operand = i.operands++;
64a0c779
DN		 5811 }
5812
5813 free (p);
5814 free (intel_parser.disp);
5815
5816 return ret;
5817}
5818
a724f0f4
JB		 5819#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
5820
5821/* expr e04 expr'
5822
5823 expr' cmpOp e04 expr'
5824 | Empty */
64a0c779
DN		 5825static int
5826intel_expr ()
5827{
a724f0f4
JB		 5828 /* XXX Implement the comparison operators. */
5829 return intel_e04 ();
9306ca4a
JB		 5830}
5831
a724f0f4 5832/* e04 e05 e04'
9306ca4a 5833
a724f0f4 5834 e04' addOp e05 e04'
9306ca4a
JB		 5835 | Empty */
5836static int
5837intel_e04 ()
5838{
a724f0f4 5839 int nregs = -1;
9306ca4a 5840
a724f0f4 5841 for (;;)
9306ca4a 5842 {
a724f0f4
JB		 5843 if (!intel_e05())
5844 return 0;
9306ca4a 5845
a724f0f4
JB		 5846 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
5847 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 5848
a724f0f4
JB		 5849 if (cur_token.code == '+')
5850 nregs = -1;
5851 else if (cur_token.code == '-')
5852 nregs = NUM_ADDRESS_REGS;
5853 else
5854 return 1;
64a0c779 5855
a724f0f4
JB		 5856 strcat (intel_parser.disp, cur_token.str);
5857 intel_match_token (cur_token.code);
5858 }
64a0c779
DN		 5859}
5860
64a0c779
DN		 5861/* e05 e06 e05'
5862
9306ca4a 5863 e05' binOp e06 e05'
64a0c779
DN		 5864 | Empty */
5865static int
5866intel_e05 ()
5867{
a724f0f4 5868 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 5869
a724f0f4 5870 for (;;)
64a0c779 5871 {
a724f0f4
JB		 5872 if (!intel_e06())
5873 return 0;
5874
5875 if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
5876 {
5877 char str[2];
5878
5879 str[0] = cur_token.code;
5880 str[1] = 0;
5881 strcat (intel_parser.disp, str);
5882 }
5883 else
5884 break;
9306ca4a 5885
64a0c779
DN		 5886 intel_match_token (cur_token.code);
5887
a724f0f4
JB		 5888 if (nregs < 0)
5889 nregs = ~nregs;
64a0c779 5890 }
a724f0f4
JB		 5891 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
5892 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
5893 return 1;
4a1805b1 5894}
64a0c779
DN		 5895
5896/* e06 e09 e06'
5897
5898 e06' mulOp e09 e06'
b77a7acd 5899 | Empty */
64a0c779
DN		 5900static int
5901intel_e06 ()
5902{
a724f0f4 5903 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 5904
a724f0f4 5905 for (;;)
64a0c779 5906 {
a724f0f4
JB		 5907 if (!intel_e09())
5908 return 0;
9306ca4a 5909
a724f0f4
JB		 5910 if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
5911 {
5912 char str[2];
9306ca4a 5913
a724f0f4
JB		 5914 str[0] = cur_token.code;
5915 str[1] = 0;
5916 strcat (intel_parser.disp, str);
5917 }
5918 else if (cur_token.code == T_SHL)
5919 strcat (intel_parser.disp, "<<");
5920 else if (cur_token.code == T_SHR)
5921 strcat (intel_parser.disp, ">>");
5922 else
5923 break;
9306ca4a 5924
a724f0f4 5925 intel_match_token (cur_token.code);
64a0c779 5926
a724f0f4
JB		 5927 if (nregs < 0)
5928 nregs = ~nregs;
64a0c779 5929 }
a724f0f4
JB		 5930 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
5931 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
5932 return 1;
64a0c779
DN		 5933}
5934
a724f0f4
JB		 5935/* e09 OFFSET e09
5936 | SHORT e09
5937 | + e09
5938 | - e09
5939 | ~ e09
5940 | NOT e09
9306ca4a
JB		 5941 | e10 e09'
5942
64a0c779 5943 e09' PTR e10 e09'
b77a7acd 5944 | : e10 e09'
64a0c779
DN		 5945 | Empty */
5946static int
5947intel_e09 ()
5948{
a724f0f4
JB		 5949 int nregs = ~NUM_ADDRESS_REGS;
5950 int in_offset = 0;
5951
5952 for (;;)
64a0c779 5953 {
a724f0f4
JB		 5954 /* Don't consume constants here. */
5955 if (cur_token.code == '+' || cur_token.code == '-')
5956 {
5957 /* Need to look one token ahead - if the next token
5958 is a constant, the current token is its sign. */
5959 int next_code;
5960
5961 intel_match_token (cur_token.code);
5962 next_code = cur_token.code;
5963 intel_putback_token ();
5964 if (next_code == T_CONST)
5965 break;
5966 }
5967
5968 /* e09 OFFSET e09 */
5969 if (cur_token.code == T_OFFSET)
5970 {
5971 if (!in_offset++)
5972 ++intel_parser.in_offset;
5973 }
5974
5975 /* e09 SHORT e09 */
5976 else if (cur_token.code == T_SHORT)
5977 intel_parser.op_modifier |= 1 << T_SHORT;
5978
5979 /* e09 + e09 */
5980 else if (cur_token.code == '+')
5981 strcat (intel_parser.disp, "+");
5982
5983 /* e09 - e09
5984 | ~ e09
5985 | NOT e09 */
5986 else if (cur_token.code == '-' || cur_token.code == '~')
5987 {
5988 char str[2];
64a0c779 5989
a724f0f4
JB		 5990 if (nregs < 0)
5991 nregs = ~nregs;
5992 str[0] = cur_token.code;
5993 str[1] = 0;
5994 strcat (intel_parser.disp, str);
5995 }
5996
5997 /* e09 e10 e09' */
5998 else
5999 break;
6000
6001 intel_match_token (cur_token.code);
64a0c779
DN		 6002 }
6003
a724f0f4 6004 for (;;)
9306ca4a 6005 {
a724f0f4
JB		 6006 if (!intel_e10 ())
6007 return 0;
9306ca4a 6008
a724f0f4
JB		 6009 /* e09' PTR e10 e09' */
6010 if (cur_token.code == T_PTR)
6011 {
6012 char suffix;
9306ca4a 6013
a724f0f4
JB		 6014 if (prev_token.code == T_BYTE)
6015 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 6016
a724f0f4
JB		 6017 else if (prev_token.code == T_WORD)
6018 {
6019 if (current_templates->start->name[0] == 'l'
6020 && current_templates->start->name[2] == 's'
6021 && current_templates->start->name[3] == 0)
6022 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6023 else if (intel_parser.got_a_float == 2) /* "fi..." */
6024 suffix = SHORT_MNEM_SUFFIX;
6025 else
6026 suffix = WORD_MNEM_SUFFIX;
6027 }
64a0c779 6028
a724f0f4
JB		 6029 else if (prev_token.code == T_DWORD)
6030 {
6031 if (current_templates->start->name[0] == 'l'
6032 && current_templates->start->name[2] == 's'
6033 && current_templates->start->name[3] == 0)
6034 suffix = WORD_MNEM_SUFFIX;
6035 else if (flag_code == CODE_16BIT
6036 && (current_templates->start->opcode_modifier
6037 & (Jump|JumpDword|JumpInterSegment)))
6038 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6039 else if (intel_parser.got_a_float == 1) /* "f..." */
6040 suffix = SHORT_MNEM_SUFFIX;
6041 else
6042 suffix = LONG_MNEM_SUFFIX;
6043 }
9306ca4a 6044
a724f0f4
JB		 6045 else if (prev_token.code == T_FWORD)
6046 {
6047 if (current_templates->start->name[0] == 'l'
6048 && current_templates->start->name[2] == 's'
6049 && current_templates->start->name[3] == 0)
6050 suffix = LONG_MNEM_SUFFIX;
6051 else if (!intel_parser.got_a_float)
6052 {
6053 if (flag_code == CODE_16BIT)
6054 add_prefix (DATA_PREFIX_OPCODE);
6055 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6056 }
6057 else
6058 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6059 }
64a0c779 6060
a724f0f4
JB		 6061 else if (prev_token.code == T_QWORD)
6062 {
6063 if (intel_parser.got_a_float == 1) /* "f..." */
6064 suffix = LONG_MNEM_SUFFIX;
6065 else
6066 suffix = QWORD_MNEM_SUFFIX;
6067 }
64a0c779 6068
a724f0f4
JB		 6069 else if (prev_token.code == T_TBYTE)
6070 {
6071 if (intel_parser.got_a_float == 1)
6072 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6073 else
6074 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6075 }
9306ca4a 6076
a724f0f4 6077 else if (prev_token.code == T_XMMWORD)
9306ca4a 6078 {
a724f0f4
JB		 6079 /* XXX ignored for now, but accepted since gcc uses it */
6080 suffix = 0;
9306ca4a 6081 }
64a0c779 6082
f16b83df 6083 else
a724f0f4
JB		 6084 {
6085 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
6086 return 0;
6087 }
6088
6089 if (current_templates->start->base_opcode == 0x8d /* lea */)
6090 ;
6091 else if (!i.suffix)
6092 i.suffix = suffix;
6093 else if (i.suffix != suffix)
6094 {
6095 as_bad (_("Conflicting operand modifiers"));
6096 return 0;
6097 }
64a0c779 6098
9306ca4a
JB		 6099 }
6100
a724f0f4
JB		 6101 /* e09' : e10 e09' */
6102 else if (cur_token.code == ':')
9306ca4a 6103 {
a724f0f4
JB		 6104 if (prev_token.code != T_REG)
6105 {
6106 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6107 segment/group identifier (which we don't have), using comma
6108 as the operand separator there is even less consistent, since
6109 there all branches only have a single operand. */
6110 if (this_operand != 0
6111 || intel_parser.in_offset
6112 || intel_parser.in_bracket
6113 || (!(current_templates->start->opcode_modifier
6114 & (Jump|JumpDword|JumpInterSegment))
6115 && !(current_templates->start->operand_types[0]
6116 & JumpAbsolute)))
6117 return intel_match_token (T_NIL);
6118 /* Remember the start of the 2nd operand and terminate 1st
6119 operand here.
6120 XXX This isn't right, yet (when SSSS:OOOO is right operand of
6121 another expression), but it gets at least the simplest case
6122 (a plain number or symbol on the left side) right. */
6123 intel_parser.next_operand = intel_parser.op_string;
6124 *--intel_parser.op_string = '\0';
6125 return intel_match_token (':');
6126 }
9306ca4a 6127 }
64a0c779 6128
a724f0f4 6129 /* e09' Empty */
64a0c779 6130 else
a724f0f4 6131 break;
64a0c779 6132
a724f0f4
JB		 6133 intel_match_token (cur_token.code);
6134
6135 }
6136
6137 if (in_offset)
6138 {
6139 --intel_parser.in_offset;
6140 if (nregs < 0)
6141 nregs = ~nregs;
6142 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 6143 {
a724f0f4 6144 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 6145 return 0;
6146 }
a724f0f4
JB		 6147 intel_parser.op_modifier |= 1 << T_OFFSET;
6148 }
9306ca4a 6149
a724f0f4
JB		 6150 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6151 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
6152 return 1;
6153}
64a0c779 6154
a724f0f4
JB		 6155static int
6156intel_bracket_expr ()
6157{
6158 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
6159 const char *start = intel_parser.op_string;
6160 int len;
6161
6162 if (i.op[this_operand].regs)
6163 return intel_match_token (T_NIL);
6164
6165 intel_match_token ('[');
6166
6167 /* Mark as a memory operand only if it's not already known to be an
6168 offset expression. If it's an offset expression, we need to keep
6169 the brace in. */
6170 if (!intel_parser.in_offset)
6171 {
6172 ++intel_parser.in_bracket;
6173 /* Unfortunately gas always diverged from MASM in a respect that can't
6174 be easily fixed without risking to break code sequences likely to be
6175 encountered (the testsuite even check for this): MASM doesn't consider
6176 an expression inside brackets unconditionally as a memory reference.
6177 When that is e.g. a constant, an offset expression, or the sum of the
6178 two, this is still taken as a constant load. gas, however, always
6179 treated these as memory references. As a compromise, we'll try to make
6180 offset expressions inside brackets work the MASM way (since that's
6181 less likely to be found in real world code), but make constants alone
6182 continue to work the traditional gas way. In either case, issue a
6183 warning. */
6184 intel_parser.op_modifier &= ~was_offset;
64a0c779 6185 }
a724f0f4
JB		 6186 else
6187 strcat (intel_parser.disp, "[");
6188
6189 /* Add a '+' to the displacement string if necessary. */
6190 if (*intel_parser.disp != '\0'
6191 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
6192 strcat (intel_parser.disp, "+");
64a0c779 6193
a724f0f4
JB		 6194 if (intel_expr ()
6195 && (len = intel_parser.op_string - start - 1,
6196 intel_match_token (']')))
64a0c779 6197 {
a724f0f4
JB		 6198 /* Preserve brackets when the operand is an offset expression. */
6199 if (intel_parser.in_offset)
6200 strcat (intel_parser.disp, "]");
6201 else
6202 {
6203 --intel_parser.in_bracket;
6204 if (i.base_reg || i.index_reg)
6205 intel_parser.is_mem = 1;
6206 if (!intel_parser.is_mem)
6207 {
6208 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
6209 /* Defer the warning until all of the operand was parsed. */
6210 intel_parser.is_mem = -1;
6211 else if (!quiet_warnings)
6212 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
6213 }
6214 }
6215 intel_parser.op_modifier |= was_offset;
64a0c779 6216
a724f0f4 6217 return 1;
64a0c779 6218 }
a724f0f4 6219 return 0;
64a0c779
DN		 6220}
6221
6222/* e10 e11 e10'
6223
6224 e10' [ expr ] e10'
b77a7acd 6225 | Empty */
64a0c779
DN		 6226static int
6227intel_e10 ()
6228{
a724f0f4
JB		 6229 if (!intel_e11 ())
6230 return 0;
64a0c779 6231
a724f0f4 6232 while (cur_token.code == '[')
64a0c779 6233 {
a724f0f4 6234 if (!intel_bracket_expr ())
21d6c4af 6235 return 0;
64a0c779
DN		 6236 }
6237
a724f0f4 6238 return 1;
64a0c779
DN		 6239}
6240
64a0c779 6241/* e11 ( expr )
b77a7acd 6242 | [ expr ]
64a0c779
DN		 6243 | BYTE
6244 | WORD
6245 | DWORD
9306ca4a 6246 | FWORD
64a0c779 6247 | QWORD
9306ca4a
JB		 6248 | TBYTE
6249 | OWORD
6250 | XMMWORD
4a1805b1 6251 | $
64a0c779
DN		 6252 | .
6253 | register
6254 | id
6255 | constant */
6256static int
6257intel_e11 ()
6258{
a724f0f4 6259 switch (cur_token.code)
64a0c779 6260 {
a724f0f4
JB		 6261 /* e11 ( expr ) */
6262 case '(':
64a0c779
DN		 6263 intel_match_token ('(');
6264 strcat (intel_parser.disp, "(");
6265
6266 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 6267 {
6268 strcat (intel_parser.disp, ")");
6269 return 1;
6270 }
a724f0f4 6271 return 0;
4a1805b1 6272
a724f0f4
JB		 6273 /* e11 [ expr ] */
6274 case '[':
6275 /* Operands for jump/call inside brackets denote absolute addresses.
6276 XXX This shouldn't be needed anymore (or if it should rather live
6277 in intel_bracket_expr). */
9306ca4a
JB		 6278 if (current_templates->start->opcode_modifier
6279 & (Jump|JumpDword|JumpByte|JumpInterSegment))
64a0c779
DN		 6280 i.types[this_operand] |= JumpAbsolute;
6281
a724f0f4 6282 return intel_bracket_expr ();
64a0c779 6283
a724f0f4
JB		 6284 /* e11 $
6285 | . */
6286 case '.':
64a0c779
DN		 6287 strcat (intel_parser.disp, cur_token.str);
6288 intel_match_token (cur_token.code);
21d6c4af
DN		 6289
6290 /* Mark as a memory operand only if it's not already known to be an
6291 offset expression. */
a724f0f4 6292 if (!intel_parser.in_offset)
21d6c4af 6293 intel_parser.is_mem = 1;
64a0c779
DN		 6294
6295 return 1;
64a0c779 6296
a724f0f4
JB		 6297 /* e11 register */
6298 case T_REG:
6299 {
6300 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 6301
a724f0f4 6302 intel_match_token (T_REG);
64a0c779 6303
a724f0f4
JB		 6304 /* Check for segment change. */
6305 if (cur_token.code == ':')
6306 {
6307 if (!(reg->reg_type & (SReg2 | SReg3)))
6308 {
6309 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
6310 return 0;
6311 }
6312 else if (i.seg[i.mem_operands])
6313 as_warn (_("Extra segment override ignored"));
6314 else
6315 {
6316 if (!intel_parser.in_offset)
6317 intel_parser.is_mem = 1;
6318 switch (reg->reg_num)
6319 {
6320 case 0:
6321 i.seg[i.mem_operands] = &es;
6322 break;
6323 case 1:
6324 i.seg[i.mem_operands] = &cs;
6325 break;
6326 case 2:
6327 i.seg[i.mem_operands] = &ss;
6328 break;
6329 case 3:
6330 i.seg[i.mem_operands] = &ds;
6331 break;
6332 case 4:
6333 i.seg[i.mem_operands] = &fs;
6334 break;
6335 case 5:
6336 i.seg[i.mem_operands] = &gs;
6337 break;
6338 }
6339 }
6340 }
64a0c779 6341
a724f0f4
JB		 6342 /* Not a segment register. Check for register scaling. */
6343 else if (cur_token.code == '*')
6344 {
6345 if (!intel_parser.in_bracket)
6346 {
6347 as_bad (_("Register scaling only allowed in memory operands"));
6348 return 0;
6349 }
64a0c779 6350
a724f0f4
JB		 6351 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
6352 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
6353 else if (i.index_reg)
6354 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 6355
a724f0f4
JB		 6356 /* What follows must be a valid scale. */
6357 intel_match_token ('*');
6358 i.index_reg = reg;
6359 i.types[this_operand] |= BaseIndex;
64a0c779 6360
a724f0f4
JB		 6361 /* Set the scale after setting the register (otherwise,
6362 i386_scale will complain) */
6363 if (cur_token.code == '+' || cur_token.code == '-')
6364 {
6365 char *str, sign = cur_token.code;
6366 intel_match_token (cur_token.code);
6367 if (cur_token.code != T_CONST)
6368 {
6369 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6370 cur_token.str);
6371 return 0;
6372 }
6373 str = (char *) xmalloc (strlen (cur_token.str) + 2);
6374 strcpy (str + 1, cur_token.str);
6375 *str = sign;
6376 if (!i386_scale (str))
6377 return 0;
6378 free (str);
6379 }
6380 else if (!i386_scale (cur_token.str))
64a0c779 6381 return 0;
a724f0f4
JB		 6382 intel_match_token (cur_token.code);
6383 }
64a0c779 6384
a724f0f4
JB		 6385 /* No scaling. If this is a memory operand, the register is either a
6386 base register (first occurrence) or an index register (second
6387 occurrence). */
6388 else if (intel_parser.in_bracket && !(reg->reg_type & (SReg2 | SReg3)))
6389 {
64a0c779 6390
a724f0f4
JB		 6391 if (!i.base_reg)
6392 i.base_reg = reg;
6393 else if (!i.index_reg)
6394 i.index_reg = reg;
6395 else
6396 {
6397 as_bad (_("Too many register references in memory operand"));
6398 return 0;
6399 }
64a0c779 6400
a724f0f4
JB		 6401 i.types[this_operand] |= BaseIndex;
6402 }
4a1805b1 6403
a724f0f4
JB		 6404 /* Offset modifier. Add the register to the displacement string to be
6405 parsed as an immediate expression after we're done. */
6406 else if (intel_parser.in_offset)
6407 {
6408 as_warn (_("Using register names in OFFSET expressions is deprecated"));
6409 strcat (intel_parser.disp, reg->reg_name);
6410 }
64a0c779 6411
a724f0f4
JB		 6412 /* It's neither base nor index nor offset. */
6413 else if (!intel_parser.is_mem)
6414 {
6415 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
6416 i.op[this_operand].regs = reg;
6417 i.reg_operands++;
6418 }
6419 else
6420 {
6421 as_bad (_("Invalid use of register"));
6422 return 0;
6423 }
64a0c779 6424
a724f0f4
JB		 6425 /* Since registers are not part of the displacement string (except
6426 when we're parsing offset operands), we may need to remove any
6427 preceding '+' from the displacement string. */
6428 if (*intel_parser.disp != '\0'
6429 && !intel_parser.in_offset)
6430 {
6431 char *s = intel_parser.disp;
6432 s += strlen (s) - 1;
6433 if (*s == '+')
6434 *s = '\0';
6435 }
4a1805b1 6436
a724f0f4
JB		 6437 return 1;
6438 }
6439
6440 /* e11 BYTE
6441 | WORD
6442 | DWORD
6443 | FWORD
6444 | QWORD
6445 | TBYTE
6446 | OWORD
6447 | XMMWORD */
6448 case T_BYTE:
6449 case T_WORD:
6450 case T_DWORD:
6451 case T_FWORD:
6452 case T_QWORD:
6453 case T_TBYTE:
6454 case T_XMMWORD:
6455 intel_match_token (cur_token.code);
64a0c779 6456
a724f0f4
JB		 6457 if (cur_token.code == T_PTR)
6458 return 1;
6459
6460 /* It must have been an identifier. */
6461 intel_putback_token ();
6462 cur_token.code = T_ID;
6463 /* FALLTHRU */
6464
6465 /* e11 id
6466 | constant */
6467 case T_ID:
6468 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 6469 {
6470 symbolS *symbolP;
6471
a724f0f4
JB		 6472 /* The identifier represents a memory reference only if it's not
6473 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 6474 symbolP = symbol_find(cur_token.str);
6475 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
6476 intel_parser.is_mem = 1;
6477 }
a724f0f4 6478 /* FALLTHRU */
64a0c779 6479
a724f0f4
JB		 6480 case T_CONST:
6481 case '-':
6482 case '+':
6483 {
6484 char *save_str, sign = 0;
64a0c779 6485
a724f0f4
JB		 6486 /* Allow constants that start with `+' or `-'. */
6487 if (cur_token.code == '-' || cur_token.code == '+')
6488 {
6489 sign = cur_token.code;
6490 intel_match_token (cur_token.code);
6491 if (cur_token.code != T_CONST)
6492 {
6493 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6494 cur_token.str);
6495 return 0;
6496 }
6497 }
64a0c779 6498
a724f0f4
JB		 6499 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
6500 strcpy (save_str + !!sign, cur_token.str);
6501 if (sign)
6502 *save_str = sign;
64a0c779 6503
a724f0f4
JB		 6504 /* Get the next token to check for register scaling. */
6505 intel_match_token (cur_token.code);
64a0c779 6506
a724f0f4
JB		 6507 /* Check if this constant is a scaling factor for an index register. */
6508 if (cur_token.code == '*')
6509 {
6510 if (intel_match_token ('*') && cur_token.code == T_REG)
6511 {
6512 const reg_entry *reg = cur_token.reg;
6513
6514 if (!intel_parser.in_bracket)
6515 {
6516 as_bad (_("Register scaling only allowed in memory operands"));
6517 return 0;
6518 }
6519
6520 if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */
6521 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
6522 else if (i.index_reg)
6523 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
6524
6525 /* The constant is followed by `* reg', so it must be
6526 a valid scale. */
6527 i.index_reg = reg;
6528 i.types[this_operand] |= BaseIndex;
6529
6530 /* Set the scale after setting the register (otherwise,
6531 i386_scale will complain) */
6532 if (!i386_scale (save_str))
64a0c779 6533 return 0;
a724f0f4
JB		 6534 intel_match_token (T_REG);
6535
6536 /* Since registers are not part of the displacement
6537 string, we may need to remove any preceding '+' from
6538 the displacement string. */
6539 if (*intel_parser.disp != '\0')
6540 {
6541 char *s = intel_parser.disp;
6542 s += strlen (s) - 1;
6543 if (*s == '+')
6544 *s = '\0';
6545 }
6546
6547 free (save_str);
6548
6549 return 1;
6550 }
64a0c779 6551
a724f0f4
JB		 6552 /* The constant was not used for register scaling. Since we have
6553 already consumed the token following `*' we now need to put it
6554 back in the stream. */
64a0c779 6555 intel_putback_token ();
a724f0f4 6556 }
64a0c779 6557
a724f0f4
JB		 6558 /* Add the constant to the displacement string. */
6559 strcat (intel_parser.disp, save_str);
6560 free (save_str);
64a0c779 6561
a724f0f4
JB		 6562 return 1;
6563 }
64a0c779
DN		 6564 }
6565
64a0c779
DN		 6566 as_bad (_("Unrecognized token '%s'"), cur_token.str);
6567 return 0;
6568}
6569
64a0c779
DN		 6570/* Match the given token against cur_token. If they match, read the next
6571 token from the operand string. */
6572static int
6573intel_match_token (code)
e5cb08ac 6574 int code;
64a0c779
DN		 6575{
6576 if (cur_token.code == code)
6577 {
6578 intel_get_token ();
6579 return 1;
6580 }
6581 else
6582 {
0477af35 6583 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 6584 return 0;
6585 }
6586}
6587
64a0c779
DN		 6588/* Read a new token from intel_parser.op_string and store it in cur_token. */
6589static void
6590intel_get_token ()
6591{
6592 char *end_op;
6593 const reg_entry *reg;
6594 struct intel_token new_token;
6595
6596 new_token.code = T_NIL;
6597 new_token.reg = NULL;
6598 new_token.str = NULL;
6599
4a1805b1 6600 /* Free the memory allocated to the previous token and move
64a0c779
DN		 6601 cur_token to prev_token. */
6602 if (prev_token.str)
6603 free (prev_token.str);
6604
6605 prev_token = cur_token;
6606
6607 /* Skip whitespace. */
6608 while (is_space_char (*intel_parser.op_string))
6609 intel_parser.op_string++;
6610
6611 /* Return an empty token if we find nothing else on the line. */
6612 if (*intel_parser.op_string == '\0')
6613 {
6614 cur_token = new_token;
6615 return;
6616 }
6617
6618 /* The new token cannot be larger than the remainder of the operand
6619 string. */
a724f0f4 6620 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 6621 new_token.str[0] = '\0';
6622
6623 if (strchr ("0123456789", *intel_parser.op_string))
6624 {
6625 char *p = new_token.str;
6626 char *q = intel_parser.op_string;
6627 new_token.code = T_CONST;
6628
6629 /* Allow any kind of identifier char to encompass floating point and
6630 hexadecimal numbers. */
6631 while (is_identifier_char (*q))
6632 *p++ = *q++;
6633 *p = '\0';
6634
6635 /* Recognize special symbol names [0-9][bf]. */
6636 if (strlen (intel_parser.op_string) == 2
4a1805b1 6637 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 6638 || intel_parser.op_string[1] == 'f'))
6639 new_token.code = T_ID;
6640 }
6641
64a0c779
DN		 6642 else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg)
6643 && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL))
6644 {
6645 new_token.code = T_REG;
6646 new_token.reg = reg;
6647
6648 if (*intel_parser.op_string == REGISTER_PREFIX)
6649 {
6650 new_token.str[0] = REGISTER_PREFIX;
6651 new_token.str[1] = '\0';
6652 }
6653
6654 strcat (new_token.str, reg->reg_name);
6655 }
6656
6657 else if (is_identifier_char (*intel_parser.op_string))
6658 {
6659 char *p = new_token.str;
6660 char *q = intel_parser.op_string;
6661
6662 /* A '.' or '$' followed by an identifier char is an identifier.
6663 Otherwise, it's operator '.' followed by an expression. */
6664 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
6665 {
9306ca4a
JB		 6666 new_token.code = '.';
6667 new_token.str[0] = '.';
64a0c779
DN		 6668 new_token.str[1] = '\0';
6669 }
6670 else
6671 {
6672 while (is_identifier_char (*q) || *q == '@')
6673 *p++ = *q++;
6674 *p = '\0';
6675
9306ca4a
JB		 6676 if (strcasecmp (new_token.str, "NOT") == 0)
6677 new_token.code = '~';
6678
6679 else if (strcasecmp (new_token.str, "MOD") == 0)
6680 new_token.code = '%';
6681
6682 else if (strcasecmp (new_token.str, "AND") == 0)
6683 new_token.code = '&';
6684
6685 else if (strcasecmp (new_token.str, "OR") == 0)
6686 new_token.code = '|';
6687
6688 else if (strcasecmp (new_token.str, "XOR") == 0)
6689 new_token.code = '^';
6690
6691 else if (strcasecmp (new_token.str, "SHL") == 0)
6692 new_token.code = T_SHL;
6693
6694 else if (strcasecmp (new_token.str, "SHR") == 0)
6695 new_token.code = T_SHR;
6696
6697 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 6698 new_token.code = T_BYTE;
6699
6700 else if (strcasecmp (new_token.str, "WORD") == 0)
6701 new_token.code = T_WORD;
6702
6703 else if (strcasecmp (new_token.str, "DWORD") == 0)
6704 new_token.code = T_DWORD;
6705
9306ca4a
JB		 6706 else if (strcasecmp (new_token.str, "FWORD") == 0)
6707 new_token.code = T_FWORD;
6708
64a0c779
DN		 6709 else if (strcasecmp (new_token.str, "QWORD") == 0)
6710 new_token.code = T_QWORD;
6711
9306ca4a
JB		 6712 else if (strcasecmp (new_token.str, "TBYTE") == 0
6713 /* XXX remove (gcc still uses it) */
6714 || strcasecmp (new_token.str, "XWORD") == 0)
6715 new_token.code = T_TBYTE;
6716
6717 else if (strcasecmp (new_token.str, "XMMWORD") == 0
6718 || strcasecmp (new_token.str, "OWORD") == 0)
6719 new_token.code = T_XMMWORD;
64a0c779
DN		 6720
6721 else if (strcasecmp (new_token.str, "PTR") == 0)
6722 new_token.code = T_PTR;
6723
6724 else if (strcasecmp (new_token.str, "SHORT") == 0)
6725 new_token.code = T_SHORT;
6726
6727 else if (strcasecmp (new_token.str, "OFFSET") == 0)
6728 {
6729 new_token.code = T_OFFSET;
6730
6731 /* ??? This is not mentioned in the MASM grammar but gcc
6732 makes use of it with -mintel-syntax. OFFSET may be
6733 followed by FLAT: */
6734 if (strncasecmp (q, " FLAT:", 6) == 0)
6735 strcat (new_token.str, " FLAT:");
6736 }
6737
6738 /* ??? This is not mentioned in the MASM grammar. */
6739 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 6740 {
6741 new_token.code = T_OFFSET;
6742 if (*q == ':')
6743 strcat (new_token.str, ":");
6744 else
6745 as_bad (_("`:' expected"));
6746 }
64a0c779
DN		 6747
6748 else
6749 new_token.code = T_ID;
6750 }
6751 }
6752
9306ca4a
JB		 6753 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
6754 {
6755 new_token.code = *intel_parser.op_string;
6756 new_token.str[0] = *intel_parser.op_string;
6757 new_token.str[1] = '\0';
6758 }
6759
6760 else if (strchr ("<>", *intel_parser.op_string)
6761 && *intel_parser.op_string == *(intel_parser.op_string + 1))
6762 {
6763 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
6764 new_token.str[0] = *intel_parser.op_string;
6765 new_token.str[1] = *intel_parser.op_string;
6766 new_token.str[2] = '\0';
6767 }
6768
64a0c779 6769 else
0477af35 6770 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 6771
6772 intel_parser.op_string += strlen (new_token.str);
6773 cur_token = new_token;
6774}
6775
64a0c779
DN		 6776/* Put cur_token back into the token stream and make cur_token point to
6777 prev_token. */
6778static void
6779intel_putback_token ()
6780{
a724f0f4
JB		 6781 if (cur_token.code != T_NIL)
6782 {
6783 intel_parser.op_string -= strlen (cur_token.str);
6784 free (cur_token.str);
6785 }
64a0c779 6786 cur_token = prev_token;
4a1805b1 6787
64a0c779
DN		 6788 /* Forget prev_token. */
6789 prev_token.code = T_NIL;
6790 prev_token.reg = NULL;
6791 prev_token.str = NULL;
6792}
54cfded0 6793
a4447b93 6794int
54cfded0
AM		 6795tc_x86_regname_to_dw2regnum (const char *regname)
6796{
6797 unsigned int regnum;
6798 unsigned int regnames_count;
089dfecd 6799 static const char *const regnames_32[] =
54cfded0 6800 {
a4447b93
RH		 6801 "eax", "ecx", "edx", "ebx",
6802 "esp", "ebp", "esi", "edi",
089dfecd
JB		 6803 "eip", "eflags", NULL,
6804 "st0", "st1", "st2", "st3",
6805 "st4", "st5", "st6", "st7",
6806 NULL, NULL,
6807 "xmm0", "xmm1", "xmm2", "xmm3",
6808 "xmm4", "xmm5", "xmm6", "xmm7",
6809 "mm0", "mm1", "mm2", "mm3",
6810 "mm4", "mm5", "mm6", "mm7"
54cfded0 6811 };
089dfecd 6812 static const char *const regnames_64[] =
54cfded0 6813 {
089dfecd
JB		 6814 "rax", "rdx", "rcx", "rbx",
6815 "rsi", "rdi", "rbp", "rsp",
6816 "r8", "r9", "r10", "r11",
54cfded0 6817 "r12", "r13", "r14", "r15",
089dfecd
JB		 6818 "rip",
6819 "xmm0", "xmm1", "xmm2", "xmm3",
6820 "xmm4", "xmm5", "xmm6", "xmm7",
6821 "xmm8", "xmm9", "xmm10", "xmm11",
6822 "xmm12", "xmm13", "xmm14", "xmm15",
6823 "st0", "st1", "st2", "st3",
6824 "st4", "st5", "st6", "st7",
6825 "mm0", "mm1", "mm2", "mm3",
6826 "mm4", "mm5", "mm6", "mm7"
54cfded0 6827 };
089dfecd 6828 const char *const *regnames;
54cfded0
AM		 6829
6830 if (flag_code == CODE_64BIT)
6831 {
6832 regnames = regnames_64;
0cea6190 6833 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 6834 }
6835 else
6836 {
6837 regnames = regnames_32;
0cea6190 6838 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 6839 }
6840
6841 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 6842 if (regnames[regnum] != NULL
6843 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 6844 return regnum;
6845
54cfded0
AM		 6846 return -1;
6847}
6848
6849void
6850tc_x86_frame_initial_instructions (void)
6851{
a4447b93
RH		 6852 static unsigned int sp_regno;
6853
6854 if (!sp_regno)
6855 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
6856 ? "rsp" : "esp");
6857
6858 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
6859 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 6860}
d2b2c203
DJ		 6861
6862int
6863i386_elf_section_type (const char *str, size_t len)
6864{
6865 if (flag_code == CODE_64BIT
6866 && len == sizeof ("unwind") - 1
6867 && strncmp (str, "unwind", 6) == 0)
6868 return SHT_X86_64_UNWIND;
6869
6870 return -1;
6871}
bb41ade5
AM		 6872
6873#ifdef TE_PE
6874void
6875tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
6876{
6877 expressionS expr;
6878
6879 expr.X_op = O_secrel;
6880 expr.X_add_symbol = symbol;
6881 expr.X_add_number = 0;
6882 emit_expr (&expr, size);
6883}
6884#endif
GDB Binutils - Deliverables
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