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* solib.c (solib_bfd_open): Do not call ops->bfd_open.
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
0bfee649 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
6305a203
L		 58/* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
62 LOCKREP_PREFIX. */
63#define WAIT_PREFIX 0
64#define SEG_PREFIX 1
65#define ADDR_PREFIX 2
66#define DATA_PREFIX 3
67#define LOCKREP_PREFIX 4
68#define REX_PREFIX 5 /* must come last. */
69#define MAX_PREFIXES 6 /* max prefixes per opcode */
70
71/* we define the syntax here (modulo base,index,scale syntax) */
72#define REGISTER_PREFIX '%'
73#define IMMEDIATE_PREFIX '$'
74#define ABSOLUTE_PREFIX '*'
75
76/* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78#define WORD_MNEM_SUFFIX 'w'
79#define BYTE_MNEM_SUFFIX 'b'
80#define SHORT_MNEM_SUFFIX 's'
81#define LONG_MNEM_SUFFIX 'l'
82#define QWORD_MNEM_SUFFIX 'q'
83#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 84#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 85/* Intel Syntax. Use a non-ascii letter since since it never appears
86 in instructions. */
87#define LONG_DOUBLE_MNEM_SUFFIX '\1'
88
89#define END_OF_INSN '\0'
90
91/*
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
96 END.
97 */
98typedef struct
99{
100 const template *start;
101 const template *end;
102}
103templates;
104
105/* 386 operand encoding bytes: see 386 book for details of this. */
106typedef struct
107{
108 unsigned int regmem; /* codes register or memory operand */
109 unsigned int reg; /* codes register operand (or extended opcode) */
110 unsigned int mode; /* how to interpret regmem & reg */
111}
112modrm_byte;
113
114/* x86-64 extension prefix. */
115typedef int rex_byte;
116
6305a203
L		 117/* 386 opcode byte to code indirect addressing. */
118typedef struct
119{
120 unsigned base;
121 unsigned index;
122 unsigned scale;
123}
124sib_byte;
125
6305a203
L		 126/* x86 arch names, types and features */
127typedef struct
128{
129 const char *name; /* arch name */
130 enum processor_type type; /* arch type */
131 i386_cpu_flags flags; /* cpu feature flags */
132}
133arch_entry;
134
e3bb37b5
L		 135static void set_code_flag (int);
136static void set_16bit_gcc_code_flag (int);
137static void set_intel_syntax (int);
1efbbeb4 138static void set_intel_mnemonic (int);
db51cc60 139static void set_allow_index_reg (int);
cb19c032 140static void set_sse_check (int);
e3bb37b5 141static void set_cpu_arch (int);
6482c264 142#ifdef TE_PE
e3bb37b5 143static void pe_directive_secrel (int);
6482c264 144#endif
e3bb37b5
L		 145static void signed_cons (int);
146static char *output_invalid (int c);
ee86248c
JB		 147static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
148 const char *);
149static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
150 const char *);
a7619375 151static int i386_att_operand (char *);
e3bb37b5 152static int i386_intel_operand (char *, int);
ee86248c
JB		 153static int i386_intel_simplify (expressionS *);
154static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 155static const reg_entry *parse_register (char *, char **);
156static char *parse_insn (char *, char *);
157static char *parse_operands (char *, const char *);
158static void swap_operands (void);
4d456e3d 159static void swap_2_operands (int, int);
e3bb37b5
L		 160static void optimize_imm (void);
161static void optimize_disp (void);
fa99fab2 162static const template *match_template (void);
e3bb37b5
L		 163static int check_string (void);
164static int process_suffix (void);
165static int check_byte_reg (void);
166static int check_long_reg (void);
167static int check_qword_reg (void);
168static int check_word_reg (void);
169static int finalize_imm (void);
170static int process_operands (void);
171static const seg_entry *build_modrm_byte (void);
172static void output_insn (void);
173static void output_imm (fragS *, offsetT);
174static void output_disp (fragS *, offsetT);
29b0f896 175#ifndef I386COFF
e3bb37b5 176static void s_bss (int);
252b5132 177#endif
17d4e2a2
L		 178#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
179static void handle_large_common (int small ATTRIBUTE_UNUSED);
180#endif
252b5132 181
a847613f 182static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 183
c0f3af97
L		 184/* VEX prefix. */
185typedef struct
186{
187 /* VEX prefix is either 2 byte or 3 byte. */
188 unsigned char bytes[3];
189 unsigned int length;
190 /* Destination or source register specifier. */
191 const reg_entry *register_specifier;
192} vex_prefix;
193
252b5132 194/* 'md_assemble ()' gathers together information and puts it into a
47926f60 195 i386_insn. */
252b5132 196
520dc8e8
AM		 197union i386_op
198 {
199 expressionS *disps;
200 expressionS *imms;
201 const reg_entry *regs;
202 };
203
252b5132
RH		 204struct _i386_insn
205 {
47926f60 206 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 207 template tm;
208
7d5e4556
L		 209 /* SUFFIX holds the instruction size suffix for byte, word, dword
210 or qword, if given. */
252b5132
RH		 211 char suffix;
212
47926f60 213 /* OPERANDS gives the number of given operands. */
252b5132
RH		 214 unsigned int operands;
215
216 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
217 of given register, displacement, memory operands and immediate
47926f60 218 operands. */
252b5132
RH		 219 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
220
221 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 222 use OP[i] for the corresponding operand. */
40fb9820 223 i386_operand_type types[MAX_OPERANDS];
252b5132 224
520dc8e8
AM		 225 /* Displacement expression, immediate expression, or register for each
226 operand. */
227 union i386_op op[MAX_OPERANDS];
252b5132 228
3e73aa7c
JH		 229 /* Flags for operands. */
230 unsigned int flags[MAX_OPERANDS];
231#define Operand_PCrel 1
232
252b5132 233 /* Relocation type for operand */
f86103b7 234 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 235
252b5132
RH		 236 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
237 the base index byte below. */
238 const reg_entry *base_reg;
239 const reg_entry *index_reg;
240 unsigned int log2_scale_factor;
241
242 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 243 explicit segment overrides are given. */
ce8a8b2f 244 const seg_entry *seg[2];
252b5132
RH		 245
246 /* PREFIX holds all the given prefix opcodes (usually null).
247 PREFIXES is the number of prefix opcodes. */
248 unsigned int prefixes;
249 unsigned char prefix[MAX_PREFIXES];
250
251 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 252 addressing modes of this insn are encoded. */
252b5132 253 modrm_byte rm;
3e73aa7c 254 rex_byte rex;
252b5132 255 sib_byte sib;
c0f3af97 256 vex_prefix vex;
b6169b20
L		 257
258 /* Swap operand in encoding. */
259 unsigned int swap_operand : 1;
252b5132
RH		 260 };
261
262typedef struct _i386_insn i386_insn;
263
264/* List of chars besides those in app.c:symbol_chars that can start an
265 operand. Used to prevent the scrubber eating vital white-space. */
32137342 266const char extra_symbol_chars[] = "*%-(["
252b5132 267#ifdef LEX_AT
32137342
NC		 268 "@"
269#endif
270#ifdef LEX_QM
271 "?"
252b5132 272#endif
32137342 273 ;
252b5132 274
29b0f896
AM		 275#if (defined (TE_I386AIX) \
276 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 277 && !defined (TE_GNU) \
29b0f896 278 && !defined (TE_LINUX) \
32137342 279 && !defined (TE_NETWARE) \
29b0f896
AM		 280 && !defined (TE_FreeBSD) \
281 && !defined (TE_NetBSD)))
252b5132 282/* This array holds the chars that always start a comment. If the
b3b91714
AM		 283 pre-processor is disabled, these aren't very useful. The option
284 --divide will remove '/' from this list. */
285const char *i386_comment_chars = "#/";
286#define SVR4_COMMENT_CHARS 1
252b5132 287#define PREFIX_SEPARATOR '\\'
252b5132 288
b3b91714
AM		 289#else
290const char *i386_comment_chars = "#";
291#define PREFIX_SEPARATOR '/'
292#endif
293
252b5132
RH		 294/* This array holds the chars that only start a comment at the beginning of
295 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 296 .line and .file directives will appear in the pre-processed output.
297 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 298 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 299 #NO_APP at the beginning of its output.
300 Also note that comments started like this one will always work if
252b5132 301 '/' isn't otherwise defined. */
b3b91714 302const char line_comment_chars[] = "#/";
252b5132 303
63a0b638 304const char line_separator_chars[] = ";";
252b5132 305
ce8a8b2f
AM		 306/* Chars that can be used to separate mant from exp in floating point
307 nums. */
252b5132
RH		 308const char EXP_CHARS[] = "eE";
309
ce8a8b2f
AM		 310/* Chars that mean this number is a floating point constant
311 As in 0f12.456
312 or 0d1.2345e12. */
252b5132
RH		 313const char FLT_CHARS[] = "fFdDxX";
314
ce8a8b2f 315/* Tables for lexical analysis. */
252b5132
RH		 316static char mnemonic_chars[256];
317static char register_chars[256];
318static char operand_chars[256];
319static char identifier_chars[256];
320static char digit_chars[256];
321
ce8a8b2f 322/* Lexical macros. */
252b5132
RH		 323#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
324#define is_operand_char(x) (operand_chars[(unsigned char) x])
325#define is_register_char(x) (register_chars[(unsigned char) x])
326#define is_space_char(x) ((x) == ' ')
327#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
328#define is_digit_char(x) (digit_chars[(unsigned char) x])
329
0234cb7c 330/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 331static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
332
333/* md_assemble() always leaves the strings it's passed unaltered. To
334 effect this we maintain a stack of saved characters that we've smashed
335 with '\0's (indicating end of strings for various sub-fields of the
47926f60 336 assembler instruction). */
252b5132 337static char save_stack[32];
ce8a8b2f 338static char *save_stack_p;
252b5132
RH		 339#define END_STRING_AND_SAVE(s) \
340 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
341#define RESTORE_END_STRING(s) \
342 do { *(s) = *--save_stack_p; } while (0)
343
47926f60 344/* The instruction we're assembling. */
252b5132
RH		 345static i386_insn i;
346
347/* Possible templates for current insn. */
348static const templates *current_templates;
349
31b2323c
L		 350/* Per instruction expressionS buffers: max displacements & immediates. */
351static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
352static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 353
47926f60 354/* Current operand we are working on. */
ee86248c 355static int this_operand = -1;
252b5132 356
3e73aa7c
JH		 357/* We support four different modes. FLAG_CODE variable is used to distinguish
358 these. */
359
360enum flag_code {
361 CODE_32BIT,
362 CODE_16BIT,
363 CODE_64BIT };
364
365static enum flag_code flag_code;
4fa24527 366static unsigned int object_64bit;
3e73aa7c
JH		 367static int use_rela_relocations = 0;
368
369/* The names used to print error messages. */
b77a7acd 370static const char *flag_code_names[] =
3e73aa7c
JH		 371 {
372 "32",
373 "16",
374 "64"
375 };
252b5132 376
47926f60
KH		 377/* 1 for intel syntax,
378 0 if att syntax. */
379static int intel_syntax = 0;
252b5132 380
1efbbeb4
L		 381/* 1 for intel mnemonic,
382 0 if att mnemonic. */
383static int intel_mnemonic = !SYSV386_COMPAT;
384
5209009a 385/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 386static int old_gcc = OLDGCC_COMPAT;
387
a60de03c
JB		 388/* 1 if pseudo registers are permitted. */
389static int allow_pseudo_reg = 0;
390
47926f60
KH		 391/* 1 if register prefix % not required. */
392static int allow_naked_reg = 0;
252b5132 393
ba104c83 394/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 395static int allow_index_reg = 0;
396
daf50ae7
L		 397static enum
398 {
399 sse_check_none = 0,
400 sse_check_warning,
401 sse_check_error
402 }
403sse_check;
404
2ca3ace5
L		 405/* Register prefix used for error message. */
406static const char *register_prefix = "%";
407
47926f60
KH		 408/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
409 leave, push, and pop instructions so that gcc has the same stack
410 frame as in 32 bit mode. */
411static char stackop_size = '\0';
eecb386c 412
12b55ccc
L		 413/* Non-zero to optimize code alignment. */
414int optimize_align_code = 1;
415
47926f60
KH		 416/* Non-zero to quieten some warnings. */
417static int quiet_warnings = 0;
a38cf1db 418
47926f60
KH		 419/* CPU name. */
420static const char *cpu_arch_name = NULL;
6305a203 421static char *cpu_sub_arch_name = NULL;
a38cf1db 422
47926f60 423/* CPU feature flags. */
40fb9820
L		 424static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
425
ccc9c027
L		 426/* If we have selected a cpu we are generating instructions for. */
427static int cpu_arch_tune_set = 0;
428
9103f4f4 429/* Cpu we are generating instructions for. */
fbf3f584 430enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 431
432/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 433static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 434
ccc9c027 435/* CPU instruction set architecture used. */
fbf3f584 436enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 437
9103f4f4 438/* CPU feature flags of instruction set architecture used. */
fbf3f584 439i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 440
fddf5b5b
AM		 441/* If set, conditional jumps are not automatically promoted to handle
442 larger than a byte offset. */
443static unsigned int no_cond_jump_promotion = 0;
444
c0f3af97
L		 445/* Encode SSE instructions with VEX prefix. */
446static unsigned int sse2avx;
447
29b0f896 448/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 449static symbolS *GOT_symbol;
29b0f896 450
a4447b93
RH		 451/* The dwarf2 return column, adjusted for 32 or 64 bit. */
452unsigned int x86_dwarf2_return_column;
453
454/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
455int x86_cie_data_alignment;
456
252b5132 457/* Interface to relax_segment.
fddf5b5b
AM		 458 There are 3 major relax states for 386 jump insns because the
459 different types of jumps add different sizes to frags when we're
460 figuring out what sort of jump to choose to reach a given label. */
252b5132 461
47926f60 462/* Types. */
93c2a809
AM		 463#define UNCOND_JUMP 0
464#define COND_JUMP 1
465#define COND_JUMP86 2
fddf5b5b 466
47926f60 467/* Sizes. */
252b5132
RH		 468#define CODE16 1
469#define SMALL 0
29b0f896 470#define SMALL16 (SMALL | CODE16)
252b5132 471#define BIG 2
29b0f896 472#define BIG16 (BIG | CODE16)
252b5132
RH		 473
474#ifndef INLINE
475#ifdef __GNUC__
476#define INLINE __inline__
477#else
478#define INLINE
479#endif
480#endif
481
fddf5b5b
AM		 482#define ENCODE_RELAX_STATE(type, size) \
483 ((relax_substateT) (((type) << 2) | (size)))
484#define TYPE_FROM_RELAX_STATE(s) \
485 ((s) >> 2)
486#define DISP_SIZE_FROM_RELAX_STATE(s) \
487 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 488
489/* This table is used by relax_frag to promote short jumps to long
490 ones where necessary. SMALL (short) jumps may be promoted to BIG
491 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
492 don't allow a short jump in a 32 bit code segment to be promoted to
493 a 16 bit offset jump because it's slower (requires data size
494 prefix), and doesn't work, unless the destination is in the bottom
495 64k of the code segment (The top 16 bits of eip are zeroed). */
496
497const relax_typeS md_relax_table[] =
498{
24eab124
AM		 499 /* The fields are:
500 1) most positive reach of this state,
501 2) most negative reach of this state,
93c2a809 502 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 503 4) which index into the table to try if we can't fit into this one. */
252b5132 504
fddf5b5b 505 /* UNCOND_JUMP states. */
93c2a809
AM		 506 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
507 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
508 /* dword jmp adds 4 bytes to frag:
509 0 extra opcode bytes, 4 displacement bytes. */
252b5132 510 {0, 0, 4, 0},
93c2a809
AM		 511 /* word jmp adds 2 byte2 to frag:
512 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 513 {0, 0, 2, 0},
514
93c2a809
AM		 515 /* COND_JUMP states. */
516 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
517 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
518 /* dword conditionals adds 5 bytes to frag:
519 1 extra opcode byte, 4 displacement bytes. */
520 {0, 0, 5, 0},
fddf5b5b 521 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 522 1 extra opcode byte, 2 displacement bytes. */
523 {0, 0, 3, 0},
524
525 /* COND_JUMP86 states. */
526 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
527 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
528 /* dword conditionals adds 5 bytes to frag:
529 1 extra opcode byte, 4 displacement bytes. */
530 {0, 0, 5, 0},
531 /* word conditionals add 4 bytes to frag:
532 1 displacement byte and a 3 byte long branch insn. */
533 {0, 0, 4, 0}
252b5132
RH		 534};
535
9103f4f4
L		 536static const arch_entry cpu_arch[] =
537{
6305a203
L		 538 { "generic32", PROCESSOR_GENERIC32,
539 CPU_GENERIC32_FLAGS },
540 { "generic64", PROCESSOR_GENERIC64,
541 CPU_GENERIC64_FLAGS },
542 { "i8086", PROCESSOR_UNKNOWN,
543 CPU_NONE_FLAGS },
544 { "i186", PROCESSOR_UNKNOWN,
545 CPU_I186_FLAGS },
546 { "i286", PROCESSOR_UNKNOWN,
547 CPU_I286_FLAGS },
548 { "i386", PROCESSOR_I386,
549 CPU_I386_FLAGS },
550 { "i486", PROCESSOR_I486,
551 CPU_I486_FLAGS },
552 { "i586", PROCESSOR_PENTIUM,
553 CPU_I586_FLAGS },
554 { "i686", PROCESSOR_PENTIUMPRO,
555 CPU_I686_FLAGS },
556 { "pentium", PROCESSOR_PENTIUM,
557 CPU_I586_FLAGS },
558 { "pentiumpro", PROCESSOR_PENTIUMPRO,
559 CPU_I686_FLAGS },
560 { "pentiumii", PROCESSOR_PENTIUMPRO,
561 CPU_P2_FLAGS },
562 { "pentiumiii",PROCESSOR_PENTIUMPRO,
563 CPU_P3_FLAGS },
564 { "pentium4", PROCESSOR_PENTIUM4,
565 CPU_P4_FLAGS },
566 { "prescott", PROCESSOR_NOCONA,
567 CPU_CORE_FLAGS },
568 { "nocona", PROCESSOR_NOCONA,
569 CPU_NOCONA_FLAGS },
570 { "yonah", PROCESSOR_CORE,
571 CPU_CORE_FLAGS },
572 { "core", PROCESSOR_CORE,
573 CPU_CORE_FLAGS },
574 { "merom", PROCESSOR_CORE2,
575 CPU_CORE2_FLAGS },
576 { "core2", PROCESSOR_CORE2,
577 CPU_CORE2_FLAGS },
bd5295b2
L		 578 { "corei7", PROCESSOR_COREI7,
579 CPU_COREI7_FLAGS },
6305a203
L		 580 { "k6", PROCESSOR_K6,
581 CPU_K6_FLAGS },
582 { "k6_2", PROCESSOR_K6,
583 CPU_K6_2_FLAGS },
584 { "athlon", PROCESSOR_ATHLON,
585 CPU_ATHLON_FLAGS },
586 { "sledgehammer", PROCESSOR_K8,
587 CPU_K8_FLAGS },
588 { "opteron", PROCESSOR_K8,
589 CPU_K8_FLAGS },
590 { "k8", PROCESSOR_K8,
591 CPU_K8_FLAGS },
592 { "amdfam10", PROCESSOR_AMDFAM10,
593 CPU_AMDFAM10_FLAGS },
594 { ".mmx", PROCESSOR_UNKNOWN,
595 CPU_MMX_FLAGS },
596 { ".sse", PROCESSOR_UNKNOWN,
597 CPU_SSE_FLAGS },
598 { ".sse2", PROCESSOR_UNKNOWN,
599 CPU_SSE2_FLAGS },
600 { ".sse3", PROCESSOR_UNKNOWN,
601 CPU_SSE3_FLAGS },
602 { ".ssse3", PROCESSOR_UNKNOWN,
603 CPU_SSSE3_FLAGS },
604 { ".sse4.1", PROCESSOR_UNKNOWN,
605 CPU_SSE4_1_FLAGS },
606 { ".sse4.2", PROCESSOR_UNKNOWN,
607 CPU_SSE4_2_FLAGS },
608 { ".sse4", PROCESSOR_UNKNOWN,
609 CPU_SSE4_2_FLAGS },
c0f3af97
L		 610 { ".avx", PROCESSOR_UNKNOWN,
611 CPU_AVX_FLAGS },
6305a203
L		 612 { ".vmx", PROCESSOR_UNKNOWN,
613 CPU_VMX_FLAGS },
614 { ".smx", PROCESSOR_UNKNOWN,
615 CPU_SMX_FLAGS },
f03fe4c1
L		 616 { ".xsave", PROCESSOR_UNKNOWN,
617 CPU_XSAVE_FLAGS },
c0f3af97
L		 618 { ".aes", PROCESSOR_UNKNOWN,
619 CPU_AES_FLAGS },
594ab6a3
L		 620 { ".pclmul", PROCESSOR_UNKNOWN,
621 CPU_PCLMUL_FLAGS },
c0f3af97 622 { ".clmul", PROCESSOR_UNKNOWN,
594ab6a3 623 CPU_PCLMUL_FLAGS },
c0f3af97
L		 624 { ".fma", PROCESSOR_UNKNOWN,
625 CPU_FMA_FLAGS },
922d8de8
DR		 626 { ".fma4", PROCESSOR_UNKNOWN,
627 CPU_FMA4_FLAGS },
f1f8f695
L		 628 { ".movbe", PROCESSOR_UNKNOWN,
629 CPU_MOVBE_FLAGS },
630 { ".ept", PROCESSOR_UNKNOWN,
631 CPU_EPT_FLAGS },
bd5295b2
L		 632 { ".clflush", PROCESSOR_UNKNOWN,
633 CPU_CLFLUSH_FLAGS },
634 { ".syscall", PROCESSOR_UNKNOWN,
635 CPU_SYSCALL_FLAGS },
1b7f3fb0
L		 636 { ".rdtscp", PROCESSOR_UNKNOWN,
637 CPU_RDTSCP_FLAGS },
6305a203
L		 638 { ".3dnow", PROCESSOR_UNKNOWN,
639 CPU_3DNOW_FLAGS },
640 { ".3dnowa", PROCESSOR_UNKNOWN,
641 CPU_3DNOWA_FLAGS },
642 { ".padlock", PROCESSOR_UNKNOWN,
643 CPU_PADLOCK_FLAGS },
644 { ".pacifica", PROCESSOR_UNKNOWN,
645 CPU_SVME_FLAGS },
646 { ".svme", PROCESSOR_UNKNOWN,
647 CPU_SVME_FLAGS },
648 { ".sse4a", PROCESSOR_UNKNOWN,
649 CPU_SSE4A_FLAGS },
650 { ".abm", PROCESSOR_UNKNOWN,
651 CPU_ABM_FLAGS },
e413e4e9
AM		 652};
653
704209c0 654#ifdef I386COFF
a6c24e68
NC		 655/* Like s_lcomm_internal in gas/read.c but the alignment string
656 is allowed to be optional. */
657
658static symbolS *
659pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
660{
661 addressT align = 0;
662
663 SKIP_WHITESPACE ();
664
7ab9ffdd 665 if (needs_align
a6c24e68
NC		 666 && *input_line_pointer == ',')
667 {
668 align = parse_align (needs_align - 1);
7ab9ffdd 669
a6c24e68
NC		 670 if (align == (addressT) -1)
671 return NULL;
672 }
673 else
674 {
675 if (size >= 8)
676 align = 3;
677 else if (size >= 4)
678 align = 2;
679 else if (size >= 2)
680 align = 1;
681 else
682 align = 0;
683 }
684
685 bss_alloc (symbolP, size, align);
686 return symbolP;
687}
688
704209c0 689static void
a6c24e68
NC		 690pe_lcomm (int needs_align)
691{
692 s_comm_internal (needs_align * 2, pe_lcomm_internal);
693}
704209c0 694#endif
a6c24e68 695
29b0f896
AM		 696const pseudo_typeS md_pseudo_table[] =
697{
698#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
699 {"align", s_align_bytes, 0},
700#else
701 {"align", s_align_ptwo, 0},
702#endif
703 {"arch", set_cpu_arch, 0},
704#ifndef I386COFF
705 {"bss", s_bss, 0},
a6c24e68
NC		 706#else
707 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 708#endif
709 {"ffloat", float_cons, 'f'},
710 {"dfloat", float_cons, 'd'},
711 {"tfloat", float_cons, 'x'},
712 {"value", cons, 2},
d182319b 713 {"slong", signed_cons, 4},
29b0f896
AM		 714 {"noopt", s_ignore, 0},
715 {"optim", s_ignore, 0},
716 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
717 {"code16", set_code_flag, CODE_16BIT},
718 {"code32", set_code_flag, CODE_32BIT},
719 {"code64", set_code_flag, CODE_64BIT},
720 {"intel_syntax", set_intel_syntax, 1},
721 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 722 {"intel_mnemonic", set_intel_mnemonic, 1},
723 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 724 {"allow_index_reg", set_allow_index_reg, 1},
725 {"disallow_index_reg", set_allow_index_reg, 0},
cb19c032 726 {"sse_check", set_sse_check, 0},
3b22753a
L		 727#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
728 {"largecomm", handle_large_common, 0},
07a53e5c 729#else
e3bb37b5 730 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 731 {"loc", dwarf2_directive_loc, 0},
732 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 733#endif
6482c264
NC		 734#ifdef TE_PE
735 {"secrel32", pe_directive_secrel, 0},
736#endif
29b0f896
AM		 737 {0, 0, 0}
738};
739
740/* For interface with expression (). */
741extern char *input_line_pointer;
742
743/* Hash table for instruction mnemonic lookup. */
744static struct hash_control *op_hash;
745
746/* Hash table for register lookup. */
747static struct hash_control *reg_hash;
748\f
252b5132 749void
e3bb37b5 750i386_align_code (fragS *fragP, int count)
252b5132 751{
ce8a8b2f
AM		 752 /* Various efficient no-op patterns for aligning code labels.
753 Note: Don't try to assemble the instructions in the comments.
754 0L and 0w are not legal. */
252b5132
RH		 755 static const char f32_1[] =
756 {0x90}; /* nop */
757 static const char f32_2[] =
ccc9c027 758 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 759 static const char f32_3[] =
760 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
761 static const char f32_4[] =
762 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
763 static const char f32_5[] =
764 {0x90, /* nop */
765 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
766 static const char f32_6[] =
767 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
768 static const char f32_7[] =
769 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
770 static const char f32_8[] =
771 {0x90, /* nop */
772 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
773 static const char f32_9[] =
774 {0x89,0xf6, /* movl %esi,%esi */
775 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
776 static const char f32_10[] =
777 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
778 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
779 static const char f32_11[] =
780 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
781 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
782 static const char f32_12[] =
783 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
784 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
785 static const char f32_13[] =
786 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
787 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
788 static const char f32_14[] =
789 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
790 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 791 static const char f16_3[] =
792 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 793 static const char f16_4[] =
794 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
795 static const char f16_5[] =
796 {0x90, /* nop */
797 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
798 static const char f16_6[] =
799 {0x89,0xf6, /* mov %si,%si */
800 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
801 static const char f16_7[] =
802 {0x8d,0x74,0x00, /* lea 0(%si),%si */
803 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
804 static const char f16_8[] =
805 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
806 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 807 static const char jump_31[] =
808 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
809 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
810 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
811 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 812 static const char *const f32_patt[] = {
813 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 814 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 815 };
816 static const char *const f16_patt[] = {
76bc74dc 817 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 818 };
ccc9c027
L		 819 /* nopl (%[re]ax) */
820 static const char alt_3[] =
821 {0x0f,0x1f,0x00};
822 /* nopl 0(%[re]ax) */
823 static const char alt_4[] =
824 {0x0f,0x1f,0x40,0x00};
825 /* nopl 0(%[re]ax,%[re]ax,1) */
826 static const char alt_5[] =
827 {0x0f,0x1f,0x44,0x00,0x00};
828 /* nopw 0(%[re]ax,%[re]ax,1) */
829 static const char alt_6[] =
830 {0x66,0x0f,0x1f,0x44,0x00,0x00};
831 /* nopl 0L(%[re]ax) */
832 static const char alt_7[] =
833 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
834 /* nopl 0L(%[re]ax,%[re]ax,1) */
835 static const char alt_8[] =
836 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
837 /* nopw 0L(%[re]ax,%[re]ax,1) */
838 static const char alt_9[] =
839 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
840 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
841 static const char alt_10[] =
842 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
843 /* data16
844 nopw %cs:0L(%[re]ax,%[re]ax,1) */
845 static const char alt_long_11[] =
846 {0x66,
847 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
848 /* data16
849 data16
850 nopw %cs:0L(%[re]ax,%[re]ax,1) */
851 static const char alt_long_12[] =
852 {0x66,
853 0x66,
854 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
855 /* data16
856 data16
857 data16
858 nopw %cs:0L(%[re]ax,%[re]ax,1) */
859 static const char alt_long_13[] =
860 {0x66,
861 0x66,
862 0x66,
863 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
864 /* data16
865 data16
866 data16
867 data16
868 nopw %cs:0L(%[re]ax,%[re]ax,1) */
869 static const char alt_long_14[] =
870 {0x66,
871 0x66,
872 0x66,
873 0x66,
874 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
875 /* data16
876 data16
877 data16
878 data16
879 data16
880 nopw %cs:0L(%[re]ax,%[re]ax,1) */
881 static const char alt_long_15[] =
882 {0x66,
883 0x66,
884 0x66,
885 0x66,
886 0x66,
887 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
888 /* nopl 0(%[re]ax,%[re]ax,1)
889 nopw 0(%[re]ax,%[re]ax,1) */
890 static const char alt_short_11[] =
891 {0x0f,0x1f,0x44,0x00,0x00,
892 0x66,0x0f,0x1f,0x44,0x00,0x00};
893 /* nopw 0(%[re]ax,%[re]ax,1)
894 nopw 0(%[re]ax,%[re]ax,1) */
895 static const char alt_short_12[] =
896 {0x66,0x0f,0x1f,0x44,0x00,0x00,
897 0x66,0x0f,0x1f,0x44,0x00,0x00};
898 /* nopw 0(%[re]ax,%[re]ax,1)
899 nopl 0L(%[re]ax) */
900 static const char alt_short_13[] =
901 {0x66,0x0f,0x1f,0x44,0x00,0x00,
902 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
903 /* nopl 0L(%[re]ax)
904 nopl 0L(%[re]ax) */
905 static const char alt_short_14[] =
906 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
907 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
908 /* nopl 0L(%[re]ax)
909 nopl 0L(%[re]ax,%[re]ax,1) */
910 static const char alt_short_15[] =
911 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
912 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
913 static const char *const alt_short_patt[] = {
914 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
915 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
916 alt_short_14, alt_short_15
917 };
918 static const char *const alt_long_patt[] = {
919 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
920 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
921 alt_long_14, alt_long_15
922 };
252b5132 923
76bc74dc
L		 924 /* Only align for at least a positive non-zero boundary. */
925 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 926 return;
3e73aa7c 927
ccc9c027
L		 928 /* We need to decide which NOP sequence to use for 32bit and
929 64bit. When -mtune= is used:
4eed87de 930
76bc74dc
L		 931 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
932 PROCESSOR_GENERIC32, f32_patt will be used.
933 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 934 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
935 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc
L		 936 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
937 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 938
76bc74dc
L		 939 When -mtune= isn't used, alt_long_patt will be used if
940 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
941 be used.
ccc9c027
L		 942
943 When -march= or .arch is used, we can't use anything beyond
944 cpu_arch_isa_flags. */
945
946 if (flag_code == CODE_16BIT)
947 {
ccc9c027 948 if (count > 8)
33fef721 949 {
76bc74dc
L		 950 memcpy (fragP->fr_literal + fragP->fr_fix,
951 jump_31, count);
952 /* Adjust jump offset. */
953 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 954 }
76bc74dc
L		 955 else
956 memcpy (fragP->fr_literal + fragP->fr_fix,
957 f16_patt[count - 1], count);
252b5132 958 }
33fef721 959 else
ccc9c027
L		 960 {
961 const char *const *patt = NULL;
962
fbf3f584 963 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 964 {
965 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
966 switch (cpu_arch_tune)
967 {
968 case PROCESSOR_UNKNOWN:
969 /* We use cpu_arch_isa_flags to check if we SHOULD
970 optimize for Cpu686. */
fbf3f584 971 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
76bc74dc 972 patt = alt_long_patt;
ccc9c027
L		 973 else
974 patt = f32_patt;
975 break;
ccc9c027
L		 976 case PROCESSOR_PENTIUMPRO:
977 case PROCESSOR_PENTIUM4:
978 case PROCESSOR_NOCONA:
ef05d495 979 case PROCESSOR_CORE:
76bc74dc 980 case PROCESSOR_CORE2:
bd5295b2 981 case PROCESSOR_COREI7:
76bc74dc
L		 982 case PROCESSOR_GENERIC64:
983 patt = alt_long_patt;
984 break;
ccc9c027
L		 985 case PROCESSOR_K6:
986 case PROCESSOR_ATHLON:
987 case PROCESSOR_K8:
4eed87de 988 case PROCESSOR_AMDFAM10:
ccc9c027
L		 989 patt = alt_short_patt;
990 break;
76bc74dc 991 case PROCESSOR_I386:
ccc9c027
L		 992 case PROCESSOR_I486:
993 case PROCESSOR_PENTIUM:
994 case PROCESSOR_GENERIC32:
995 patt = f32_patt;
996 break;
4eed87de 997 }
ccc9c027
L		 998 }
999 else
1000 {
fbf3f584 1001 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1002 {
1003 case PROCESSOR_UNKNOWN:
e6a14101 1004 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1005 PROCESSOR_UNKNOWN. */
1006 abort ();
1007 break;
1008
76bc74dc 1009 case PROCESSOR_I386:
ccc9c027
L		 1010 case PROCESSOR_I486:
1011 case PROCESSOR_PENTIUM:
ccc9c027
L		 1012 case PROCESSOR_K6:
1013 case PROCESSOR_ATHLON:
1014 case PROCESSOR_K8:
4eed87de 1015 case PROCESSOR_AMDFAM10:
ccc9c027
L		 1016 case PROCESSOR_GENERIC32:
1017 /* We use cpu_arch_isa_flags to check if we CAN optimize
1018 for Cpu686. */
fbf3f584 1019 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1020 patt = alt_short_patt;
1021 else
1022 patt = f32_patt;
1023 break;
76bc74dc
L		 1024 case PROCESSOR_PENTIUMPRO:
1025 case PROCESSOR_PENTIUM4:
1026 case PROCESSOR_NOCONA:
1027 case PROCESSOR_CORE:
ef05d495 1028 case PROCESSOR_CORE2:
bd5295b2 1029 case PROCESSOR_COREI7:
fbf3f584 1030 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1031 patt = alt_long_patt;
1032 else
1033 patt = f32_patt;
1034 break;
1035 case PROCESSOR_GENERIC64:
76bc74dc 1036 patt = alt_long_patt;
ccc9c027 1037 break;
4eed87de 1038 }
ccc9c027
L		 1039 }
1040
76bc74dc
L		 1041 if (patt == f32_patt)
1042 {
1043 /* If the padding is less than 15 bytes, we use the normal
1044 ones. Otherwise, we use a jump instruction and adjust
1045 its offset. */
1046 if (count < 15)
1047 memcpy (fragP->fr_literal + fragP->fr_fix,
1048 patt[count - 1], count);
1049 else
1050 {
1051 memcpy (fragP->fr_literal + fragP->fr_fix,
1052 jump_31, count);
1053 /* Adjust jump offset. */
1054 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1055 }
1056 }
1057 else
1058 {
1059 /* Maximum length of an instruction is 15 byte. If the
1060 padding is greater than 15 bytes and we don't use jump,
1061 we have to break it into smaller pieces. */
1062 int padding = count;
1063 while (padding > 15)
1064 {
1065 padding -= 15;
1066 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1067 patt [14], 15);
1068 }
1069
1070 if (padding)
1071 memcpy (fragP->fr_literal + fragP->fr_fix,
1072 patt [padding - 1], padding);
1073 }
ccc9c027 1074 }
33fef721 1075 fragP->fr_var = count;
252b5132
RH		 1076}
1077
c6fb90c8 1078static INLINE int
0dfbf9d7 1079operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1080{
0dfbf9d7 1081 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1082 {
1083 case 3:
0dfbf9d7 1084 if (x->array[2])
c6fb90c8
L		 1085 return 0;
1086 case 2:
0dfbf9d7 1087 if (x->array[1])
c6fb90c8
L		 1088 return 0;
1089 case 1:
0dfbf9d7 1090 return !x->array[0];
c6fb90c8
L		 1091 default:
1092 abort ();
1093 }
40fb9820
L		 1094}
1095
c6fb90c8 1096static INLINE void
0dfbf9d7 1097operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1098{
0dfbf9d7 1099 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1100 {
1101 case 3:
0dfbf9d7 1102 x->array[2] = v;
c6fb90c8 1103 case 2:
0dfbf9d7 1104 x->array[1] = v;
c6fb90c8 1105 case 1:
0dfbf9d7 1106 x->array[0] = v;
c6fb90c8
L		 1107 break;
1108 default:
1109 abort ();
1110 }
1111}
40fb9820 1112
c6fb90c8 1113static INLINE int
0dfbf9d7
L		 1114operand_type_equal (const union i386_operand_type *x,
1115 const union i386_operand_type *y)
c6fb90c8 1116{
0dfbf9d7 1117 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1118 {
1119 case 3:
0dfbf9d7 1120 if (x->array[2] != y->array[2])
c6fb90c8
L		 1121 return 0;
1122 case 2:
0dfbf9d7 1123 if (x->array[1] != y->array[1])
c6fb90c8
L		 1124 return 0;
1125 case 1:
0dfbf9d7 1126 return x->array[0] == y->array[0];
c6fb90c8
L		 1127 break;
1128 default:
1129 abort ();
1130 }
1131}
40fb9820 1132
0dfbf9d7
L		 1133static INLINE int
1134cpu_flags_all_zero (const union i386_cpu_flags *x)
1135{
1136 switch (ARRAY_SIZE(x->array))
1137 {
1138 case 3:
1139 if (x->array[2])
1140 return 0;
1141 case 2:
1142 if (x->array[1])
1143 return 0;
1144 case 1:
1145 return !x->array[0];
1146 default:
1147 abort ();
1148 }
1149}
1150
1151static INLINE void
1152cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1153{
1154 switch (ARRAY_SIZE(x->array))
1155 {
1156 case 3:
1157 x->array[2] = v;
1158 case 2:
1159 x->array[1] = v;
1160 case 1:
1161 x->array[0] = v;
1162 break;
1163 default:
1164 abort ();
1165 }
1166}
1167
1168static INLINE int
1169cpu_flags_equal (const union i386_cpu_flags *x,
1170 const union i386_cpu_flags *y)
1171{
1172 switch (ARRAY_SIZE(x->array))
1173 {
1174 case 3:
1175 if (x->array[2] != y->array[2])
1176 return 0;
1177 case 2:
1178 if (x->array[1] != y->array[1])
1179 return 0;
1180 case 1:
1181 return x->array[0] == y->array[0];
1182 break;
1183 default:
1184 abort ();
1185 }
1186}
c6fb90c8
L		 1187
1188static INLINE int
1189cpu_flags_check_cpu64 (i386_cpu_flags f)
1190{
1191 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1192 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1193}
1194
c6fb90c8
L		 1195static INLINE i386_cpu_flags
1196cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1197{
c6fb90c8
L		 1198 switch (ARRAY_SIZE (x.array))
1199 {
1200 case 3:
1201 x.array [2] &= y.array [2];
1202 case 2:
1203 x.array [1] &= y.array [1];
1204 case 1:
1205 x.array [0] &= y.array [0];
1206 break;
1207 default:
1208 abort ();
1209 }
1210 return x;
1211}
40fb9820 1212
c6fb90c8
L		 1213static INLINE i386_cpu_flags
1214cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1215{
c6fb90c8 1216 switch (ARRAY_SIZE (x.array))
40fb9820 1217 {
c6fb90c8
L		 1218 case 3:
1219 x.array [2] |= y.array [2];
1220 case 2:
1221 x.array [1] |= y.array [1];
1222 case 1:
1223 x.array [0] |= y.array [0];
40fb9820
L		 1224 break;
1225 default:
1226 abort ();
1227 }
40fb9820
L		 1228 return x;
1229}
1230
c0f3af97
L		 1231#define CPU_FLAGS_ARCH_MATCH 0x1
1232#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1233#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1234#define CPU_FLAGS_PCLMUL_MATCH 0x8
1235#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1236
a5ff0eb2 1237#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1238 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1239 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1240#define CPU_FLAGS_PERFECT_MATCH \
1241 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1242
1243/* Return CPU flags match bits. */
3629bb00 1244
40fb9820 1245static int
c0f3af97 1246cpu_flags_match (const template *t)
40fb9820 1247{
c0f3af97
L		 1248 i386_cpu_flags x = t->cpu_flags;
1249 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1250
1251 x.bitfield.cpu64 = 0;
1252 x.bitfield.cpuno64 = 0;
1253
0dfbf9d7 1254 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1255 {
1256 /* This instruction is available on all archs. */
1257 match |= CPU_FLAGS_32BIT_MATCH;
1258 }
3629bb00
L		 1259 else
1260 {
c0f3af97 1261 /* This instruction is available only on some archs. */
3629bb00
L		 1262 i386_cpu_flags cpu = cpu_arch_flags;
1263
1264 cpu.bitfield.cpu64 = 0;
1265 cpu.bitfield.cpuno64 = 0;
1266 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1267 if (!cpu_flags_all_zero (&cpu))
1268 {
a5ff0eb2
L		 1269 if (x.bitfield.cpuavx)
1270 {
ce2f5b3c 1271 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1272 if (cpu.bitfield.cpuavx)
1273 {
1274 /* Check SSE2AVX. */
1275 if (!t->opcode_modifier.sse2avx|| sse2avx)
1276 {
1277 match |= (CPU_FLAGS_ARCH_MATCH
1278 | CPU_FLAGS_AVX_MATCH);
1279 /* Check AES. */
1280 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1281 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1282 /* Check PCLMUL. */
1283 if (!x.bitfield.cpupclmul
1284 || cpu.bitfield.cpupclmul)
1285 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1286 }
1287 }
1288 else
1289 match |= CPU_FLAGS_ARCH_MATCH;
1290 }
1291 else
c0f3af97
L		 1292 match |= CPU_FLAGS_32BIT_MATCH;
1293 }
3629bb00 1294 }
c0f3af97 1295 return match;
40fb9820
L		 1296}
1297
c6fb90c8
L		 1298static INLINE i386_operand_type
1299operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1300{
c6fb90c8
L		 1301 switch (ARRAY_SIZE (x.array))
1302 {
1303 case 3:
1304 x.array [2] &= y.array [2];
1305 case 2:
1306 x.array [1] &= y.array [1];
1307 case 1:
1308 x.array [0] &= y.array [0];
1309 break;
1310 default:
1311 abort ();
1312 }
1313 return x;
40fb9820
L		 1314}
1315
c6fb90c8
L		 1316static INLINE i386_operand_type
1317operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1318{
c6fb90c8 1319 switch (ARRAY_SIZE (x.array))
40fb9820 1320 {
c6fb90c8
L		 1321 case 3:
1322 x.array [2] |= y.array [2];
1323 case 2:
1324 x.array [1] |= y.array [1];
1325 case 1:
1326 x.array [0] |= y.array [0];
40fb9820
L		 1327 break;
1328 default:
1329 abort ();
1330 }
c6fb90c8
L		 1331 return x;
1332}
40fb9820 1333
c6fb90c8
L		 1334static INLINE i386_operand_type
1335operand_type_xor (i386_operand_type x, i386_operand_type y)
1336{
1337 switch (ARRAY_SIZE (x.array))
1338 {
1339 case 3:
1340 x.array [2] ^= y.array [2];
1341 case 2:
1342 x.array [1] ^= y.array [1];
1343 case 1:
1344 x.array [0] ^= y.array [0];
1345 break;
1346 default:
1347 abort ();
1348 }
40fb9820
L		 1349 return x;
1350}
1351
1352static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1353static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1354static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1355static const i386_operand_type inoutportreg
1356 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1357static const i386_operand_type reg16_inoutportreg
1358 = OPERAND_TYPE_REG16_INOUTPORTREG;
1359static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1360static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1361static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1362static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1363static const i386_operand_type anydisp
1364 = OPERAND_TYPE_ANYDISP;
40fb9820 1365static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1366static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1367static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1368static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1369static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1370static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1371static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1372static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1373static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1374static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1375static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1376
1377enum operand_type
1378{
1379 reg,
40fb9820
L		 1380 imm,
1381 disp,
1382 anymem
1383};
1384
c6fb90c8 1385static INLINE int
40fb9820
L		 1386operand_type_check (i386_operand_type t, enum operand_type c)
1387{
1388 switch (c)
1389 {
1390 case reg:
1391 return (t.bitfield.reg8
1392 || t.bitfield.reg16
1393 || t.bitfield.reg32
1394 || t.bitfield.reg64);
1395
40fb9820
L		 1396 case imm:
1397 return (t.bitfield.imm8
1398 || t.bitfield.imm8s
1399 || t.bitfield.imm16
1400 || t.bitfield.imm32
1401 || t.bitfield.imm32s
1402 || t.bitfield.imm64);
1403
1404 case disp:
1405 return (t.bitfield.disp8
1406 || t.bitfield.disp16
1407 || t.bitfield.disp32
1408 || t.bitfield.disp32s
1409 || t.bitfield.disp64);
1410
1411 case anymem:
1412 return (t.bitfield.disp8
1413 || t.bitfield.disp16
1414 || t.bitfield.disp32
1415 || t.bitfield.disp32s
1416 || t.bitfield.disp64
1417 || t.bitfield.baseindex);
1418
1419 default:
1420 abort ();
1421 }
2cfe26b6
AM		 1422
1423 return 0;
40fb9820
L		 1424}
1425
5c07affc
L		 1426/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1427 operand J for instruction template T. */
1428
1429static INLINE int
1430match_reg_size (const template *t, unsigned int j)
1431{
1432 return !((i.types[j].bitfield.byte
1433 && !t->operand_types[j].bitfield.byte)
1434 || (i.types[j].bitfield.word
1435 && !t->operand_types[j].bitfield.word)
1436 || (i.types[j].bitfield.dword
1437 && !t->operand_types[j].bitfield.dword)
1438 || (i.types[j].bitfield.qword
1439 && !t->operand_types[j].bitfield.qword));
1440}
1441
1442/* Return 1 if there is no conflict in any size on operand J for
1443 instruction template T. */
1444
1445static INLINE int
1446match_mem_size (const template *t, unsigned int j)
1447{
1448 return (match_reg_size (t, j)
1449 && !((i.types[j].bitfield.unspecified
1450 && !t->operand_types[j].bitfield.unspecified)
1451 || (i.types[j].bitfield.fword
1452 && !t->operand_types[j].bitfield.fword)
1453 || (i.types[j].bitfield.tbyte
1454 && !t->operand_types[j].bitfield.tbyte)
1455 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1456 && !t->operand_types[j].bitfield.xmmword)
1457 || (i.types[j].bitfield.ymmword
1458 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1459}
1460
1461/* Return 1 if there is no size conflict on any operands for
1462 instruction template T. */
1463
1464static INLINE int
1465operand_size_match (const template *t)
1466{
1467 unsigned int j;
1468 int match = 1;
1469
1470 /* Don't check jump instructions. */
1471 if (t->opcode_modifier.jump
1472 || t->opcode_modifier.jumpbyte
1473 || t->opcode_modifier.jumpdword
1474 || t->opcode_modifier.jumpintersegment)
1475 return match;
1476
1477 /* Check memory and accumulator operand size. */
1478 for (j = 0; j < i.operands; j++)
1479 {
1480 if (t->operand_types[j].bitfield.anysize)
1481 continue;
1482
1483 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1484 {
1485 match = 0;
1486 break;
1487 }
1488
1489 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1490 {
1491 match = 0;
1492 break;
1493 }
1494 }
1495
1496 if (match
1497 || (!t->opcode_modifier.d && !t->opcode_modifier.floatd))
1498 return match;
1499
1500 /* Check reverse. */
9c2799c2 1501 gas_assert (i.operands == 2);
5c07affc
L		 1502
1503 match = 1;
1504 for (j = 0; j < 2; j++)
1505 {
1506 if (t->operand_types[j].bitfield.acc
1507 && !match_reg_size (t, j ? 0 : 1))
1508 {
1509 match = 0;
1510 break;
1511 }
1512
1513 if (i.types[j].bitfield.mem
1514 && !match_mem_size (t, j ? 0 : 1))
1515 {
1516 match = 0;
1517 break;
1518 }
1519 }
1520
1521 return match;
1522}
1523
c6fb90c8 1524static INLINE int
40fb9820
L		 1525operand_type_match (i386_operand_type overlap,
1526 i386_operand_type given)
1527{
1528 i386_operand_type temp = overlap;
1529
1530 temp.bitfield.jumpabsolute = 0;
7d5e4556 1531 temp.bitfield.unspecified = 0;
5c07affc
L		 1532 temp.bitfield.byte = 0;
1533 temp.bitfield.word = 0;
1534 temp.bitfield.dword = 0;
1535 temp.bitfield.fword = 0;
1536 temp.bitfield.qword = 0;
1537 temp.bitfield.tbyte = 0;
1538 temp.bitfield.xmmword = 0;
c0f3af97 1539 temp.bitfield.ymmword = 0;
0dfbf9d7 1540 if (operand_type_all_zero (&temp))
40fb9820
L		 1541 return 0;
1542
1543 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1544 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1545}
1546
7d5e4556 1547/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1548 unless the expected operand type register overlap is null.
1549 Note that Acc in a template matches every size of reg. */
1550
c6fb90c8 1551static INLINE int
40fb9820
L		 1552operand_type_register_match (i386_operand_type m0,
1553 i386_operand_type g0,
1554 i386_operand_type t0,
1555 i386_operand_type m1,
1556 i386_operand_type g1,
1557 i386_operand_type t1)
1558{
1559 if (!operand_type_check (g0, reg))
1560 return 1;
1561
1562 if (!operand_type_check (g1, reg))
1563 return 1;
1564
1565 if (g0.bitfield.reg8 == g1.bitfield.reg8
1566 && g0.bitfield.reg16 == g1.bitfield.reg16
1567 && g0.bitfield.reg32 == g1.bitfield.reg32
1568 && g0.bitfield.reg64 == g1.bitfield.reg64)
1569 return 1;
1570
1571 if (m0.bitfield.acc)
1572 {
1573 t0.bitfield.reg8 = 1;
1574 t0.bitfield.reg16 = 1;
1575 t0.bitfield.reg32 = 1;
1576 t0.bitfield.reg64 = 1;
1577 }
1578
1579 if (m1.bitfield.acc)
1580 {
1581 t1.bitfield.reg8 = 1;
1582 t1.bitfield.reg16 = 1;
1583 t1.bitfield.reg32 = 1;
1584 t1.bitfield.reg64 = 1;
1585 }
1586
1587 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1588 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1589 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1590 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1591}
1592
252b5132 1593static INLINE unsigned int
40fb9820 1594mode_from_disp_size (i386_operand_type t)
252b5132 1595{
40fb9820
L		 1596 if (t.bitfield.disp8)
1597 return 1;
1598 else if (t.bitfield.disp16
1599 || t.bitfield.disp32
1600 || t.bitfield.disp32s)
1601 return 2;
1602 else
1603 return 0;
252b5132
RH		 1604}
1605
1606static INLINE int
e3bb37b5 1607fits_in_signed_byte (offsetT num)
252b5132
RH		 1608{
1609 return (num >= -128) && (num <= 127);
47926f60 1610}
252b5132
RH		 1611
1612static INLINE int
e3bb37b5 1613fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1614{
1615 return (num & 0xff) == num;
47926f60 1616}
252b5132
RH		 1617
1618static INLINE int
e3bb37b5 1619fits_in_unsigned_word (offsetT num)
252b5132
RH		 1620{
1621 return (num & 0xffff) == num;
47926f60 1622}
252b5132
RH		 1623
1624static INLINE int
e3bb37b5 1625fits_in_signed_word (offsetT num)
252b5132
RH		 1626{
1627 return (-32768 <= num) && (num <= 32767);
47926f60 1628}
2a962e6d 1629
3e73aa7c 1630static INLINE int
e3bb37b5 1631fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1632{
1633#ifndef BFD64
1634 return 1;
1635#else
1636 return (!(((offsetT) -1 << 31) & num)
1637 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1638#endif
1639} /* fits_in_signed_long() */
2a962e6d 1640
3e73aa7c 1641static INLINE int
e3bb37b5 1642fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1643{
1644#ifndef BFD64
1645 return 1;
1646#else
1647 return (num & (((offsetT) 2 << 31) - 1)) == num;
1648#endif
1649} /* fits_in_unsigned_long() */
252b5132 1650
40fb9820 1651static i386_operand_type
e3bb37b5 1652smallest_imm_type (offsetT num)
252b5132 1653{
40fb9820 1654 i386_operand_type t;
7ab9ffdd 1655
0dfbf9d7 1656 operand_type_set (&t, 0);
40fb9820
L		 1657 t.bitfield.imm64 = 1;
1658
1659 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1660 {
1661 /* This code is disabled on the 486 because all the Imm1 forms
1662 in the opcode table are slower on the i486. They're the
1663 versions with the implicitly specified single-position
1664 displacement, which has another syntax if you really want to
1665 use that form. */
40fb9820
L		 1666 t.bitfield.imm1 = 1;
1667 t.bitfield.imm8 = 1;
1668 t.bitfield.imm8s = 1;
1669 t.bitfield.imm16 = 1;
1670 t.bitfield.imm32 = 1;
1671 t.bitfield.imm32s = 1;
1672 }
1673 else if (fits_in_signed_byte (num))
1674 {
1675 t.bitfield.imm8 = 1;
1676 t.bitfield.imm8s = 1;
1677 t.bitfield.imm16 = 1;
1678 t.bitfield.imm32 = 1;
1679 t.bitfield.imm32s = 1;
1680 }
1681 else if (fits_in_unsigned_byte (num))
1682 {
1683 t.bitfield.imm8 = 1;
1684 t.bitfield.imm16 = 1;
1685 t.bitfield.imm32 = 1;
1686 t.bitfield.imm32s = 1;
1687 }
1688 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1689 {
1690 t.bitfield.imm16 = 1;
1691 t.bitfield.imm32 = 1;
1692 t.bitfield.imm32s = 1;
1693 }
1694 else if (fits_in_signed_long (num))
1695 {
1696 t.bitfield.imm32 = 1;
1697 t.bitfield.imm32s = 1;
1698 }
1699 else if (fits_in_unsigned_long (num))
1700 t.bitfield.imm32 = 1;
1701
1702 return t;
47926f60 1703}
252b5132 1704
847f7ad4 1705static offsetT
e3bb37b5 1706offset_in_range (offsetT val, int size)
847f7ad4 1707{
508866be 1708 addressT mask;
ba2adb93 1709
847f7ad4
AM		 1710 switch (size)
1711 {
508866be
L		 1712 case 1: mask = ((addressT) 1 << 8) - 1; break;
1713 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1714 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1715#ifdef BFD64
1716 case 8: mask = ((addressT) 2 << 63) - 1; break;
1717#endif
47926f60 1718 default: abort ();
847f7ad4
AM		 1719 }
1720
ba2adb93 1721 /* If BFD64, sign extend val. */
3e73aa7c
JH		 1722 if (!use_rela_relocations)
1723 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1724 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 1725
47926f60 1726 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1727 {
1728 char buf1[40], buf2[40];
1729
1730 sprint_value (buf1, val);
1731 sprint_value (buf2, val & mask);
1732 as_warn (_("%s shortened to %s"), buf1, buf2);
1733 }
1734 return val & mask;
1735}
1736
252b5132
RH		 1737/* Returns 0 if attempting to add a prefix where one from the same
1738 class already exists, 1 if non rep/repne added, 2 if rep/repne
1739 added. */
1740static int
e3bb37b5 1741add_prefix (unsigned int prefix)
252b5132
RH		 1742{
1743 int ret = 1;
b1905489 1744 unsigned int q;
252b5132 1745
29b0f896
AM		 1746 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1747 && flag_code == CODE_64BIT)
b1905489 1748 {
161a04f6
L		 1749 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1750 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1751 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 1752 ret = 0;
1753 q = REX_PREFIX;
1754 }
3e73aa7c 1755 else
b1905489
JB		 1756 {
1757 switch (prefix)
1758 {
1759 default:
1760 abort ();
1761
1762 case CS_PREFIX_OPCODE:
1763 case DS_PREFIX_OPCODE:
1764 case ES_PREFIX_OPCODE:
1765 case FS_PREFIX_OPCODE:
1766 case GS_PREFIX_OPCODE:
1767 case SS_PREFIX_OPCODE:
1768 q = SEG_PREFIX;
1769 break;
1770
1771 case REPNE_PREFIX_OPCODE:
1772 case REPE_PREFIX_OPCODE:
1773 ret = 2;
1774 /* fall thru */
1775 case LOCK_PREFIX_OPCODE:
1776 q = LOCKREP_PREFIX;
1777 break;
1778
1779 case FWAIT_OPCODE:
1780 q = WAIT_PREFIX;
1781 break;
1782
1783 case ADDR_PREFIX_OPCODE:
1784 q = ADDR_PREFIX;
1785 break;
1786
1787 case DATA_PREFIX_OPCODE:
1788 q = DATA_PREFIX;
1789 break;
1790 }
1791 if (i.prefix[q] != 0)
1792 ret = 0;
1793 }
252b5132 1794
b1905489 1795 if (ret)
252b5132 1796 {
b1905489
JB		 1797 if (!i.prefix[q])
1798 ++i.prefixes;
1799 i.prefix[q] |= prefix;
252b5132 1800 }
b1905489
JB		 1801 else
1802 as_bad (_("same type of prefix used twice"));
252b5132 1803
252b5132
RH		 1804 return ret;
1805}
1806
1807static void
e3bb37b5 1808set_code_flag (int value)
eecb386c 1809{
3e73aa7c 1810 flag_code = value;
40fb9820
L		 1811 if (flag_code == CODE_64BIT)
1812 {
1813 cpu_arch_flags.bitfield.cpu64 = 1;
1814 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1815 }
1816 else
1817 {
1818 cpu_arch_flags.bitfield.cpu64 = 0;
1819 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1820 }
1821 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1822 {
1823 as_bad (_("64bit mode not supported on this CPU."));
1824 }
40fb9820 1825 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1826 {
1827 as_bad (_("32bit mode not supported on this CPU."));
1828 }
eecb386c
AM		 1829 stackop_size = '\0';
1830}
1831
1832static void
e3bb37b5 1833set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1834{
3e73aa7c 1835 flag_code = new_code_flag;
40fb9820
L		 1836 if (flag_code != CODE_16BIT)
1837 abort ();
1838 cpu_arch_flags.bitfield.cpu64 = 0;
1839 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 1840 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1841}
1842
1843static void
e3bb37b5 1844set_intel_syntax (int syntax_flag)
252b5132
RH		 1845{
1846 /* Find out if register prefixing is specified. */
1847 int ask_naked_reg = 0;
1848
1849 SKIP_WHITESPACE ();
29b0f896 1850 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1851 {
1852 char *string = input_line_pointer;
1853 int e = get_symbol_end ();
1854
47926f60 1855 if (strcmp (string, "prefix") == 0)
252b5132 1856 ask_naked_reg = 1;
47926f60 1857 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1858 ask_naked_reg = -1;
1859 else
d0b47220 1860 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1861 *input_line_pointer = e;
1862 }
1863 demand_empty_rest_of_line ();
c3332e24 1864
252b5132
RH		 1865 intel_syntax = syntax_flag;
1866
1867 if (ask_naked_reg == 0)
f86103b7
AM		 1868 allow_naked_reg = (intel_syntax
1869 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1870 else
1871 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1872
ee86248c 1873 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 1874
e4a3b5a4 1875 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1876 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1877 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1878}
1879
1efbbeb4
L		 1880static void
1881set_intel_mnemonic (int mnemonic_flag)
1882{
e1d4d893 1883 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 1884}
1885
db51cc60
L		 1886static void
1887set_allow_index_reg (int flag)
1888{
1889 allow_index_reg = flag;
1890}
1891
cb19c032
L		 1892static void
1893set_sse_check (int dummy ATTRIBUTE_UNUSED)
1894{
1895 SKIP_WHITESPACE ();
1896
1897 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1898 {
1899 char *string = input_line_pointer;
1900 int e = get_symbol_end ();
1901
1902 if (strcmp (string, "none") == 0)
1903 sse_check = sse_check_none;
1904 else if (strcmp (string, "warning") == 0)
1905 sse_check = sse_check_warning;
1906 else if (strcmp (string, "error") == 0)
1907 sse_check = sse_check_error;
1908 else
1909 as_bad (_("bad argument to sse_check directive."));
1910 *input_line_pointer = e;
1911 }
1912 else
1913 as_bad (_("missing argument for sse_check directive"));
1914
1915 demand_empty_rest_of_line ();
1916}
1917
e413e4e9 1918static void
e3bb37b5 1919set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1920{
47926f60 1921 SKIP_WHITESPACE ();
e413e4e9 1922
29b0f896 1923 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1924 {
1925 char *string = input_line_pointer;
1926 int e = get_symbol_end ();
9103f4f4 1927 unsigned int i;
40fb9820 1928 i386_cpu_flags flags;
e413e4e9 1929
9103f4f4 1930 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1931 {
1932 if (strcmp (string, cpu_arch[i].name) == 0)
1933 {
5c6af06e
JB		 1934 if (*string != '.')
1935 {
1936 cpu_arch_name = cpu_arch[i].name;
1937 cpu_sub_arch_name = NULL;
40fb9820
L		 1938 cpu_arch_flags = cpu_arch[i].flags;
1939 if (flag_code == CODE_64BIT)
1940 {
1941 cpu_arch_flags.bitfield.cpu64 = 1;
1942 cpu_arch_flags.bitfield.cpuno64 = 0;
1943 }
1944 else
1945 {
1946 cpu_arch_flags.bitfield.cpu64 = 0;
1947 cpu_arch_flags.bitfield.cpuno64 = 1;
1948 }
ccc9c027 1949 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1950 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1951 if (!cpu_arch_tune_set)
1952 {
1953 cpu_arch_tune = cpu_arch_isa;
1954 cpu_arch_tune_flags = cpu_arch_isa_flags;
1955 }
5c6af06e
JB		 1956 break;
1957 }
40fb9820 1958
c6fb90c8
L		 1959 flags = cpu_flags_or (cpu_arch_flags,
1960 cpu_arch[i].flags);
0dfbf9d7 1961 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 1962 {
6305a203
L		 1963 if (cpu_sub_arch_name)
1964 {
1965 char *name = cpu_sub_arch_name;
1966 cpu_sub_arch_name = concat (name,
1967 cpu_arch[i].name,
1bf57e9f 1968 (const char *) NULL);
6305a203
L		 1969 free (name);
1970 }
1971 else
1972 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
40fb9820 1973 cpu_arch_flags = flags;
5c6af06e
JB		 1974 }
1975 *input_line_pointer = e;
1976 demand_empty_rest_of_line ();
1977 return;
e413e4e9
AM		 1978 }
1979 }
9103f4f4 1980 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1981 as_bad (_("no such architecture: `%s'"), string);
1982
1983 *input_line_pointer = e;
1984 }
1985 else
1986 as_bad (_("missing cpu architecture"));
1987
fddf5b5b
AM		 1988 no_cond_jump_promotion = 0;
1989 if (*input_line_pointer == ','
29b0f896 1990 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1991 {
1992 char *string = ++input_line_pointer;
1993 int e = get_symbol_end ();
1994
1995 if (strcmp (string, "nojumps") == 0)
1996 no_cond_jump_promotion = 1;
1997 else if (strcmp (string, "jumps") == 0)
1998 ;
1999 else
2000 as_bad (_("no such architecture modifier: `%s'"), string);
2001
2002 *input_line_pointer = e;
2003 }
2004
e413e4e9
AM		 2005 demand_empty_rest_of_line ();
2006}
2007
b9d79e03
JH		 2008unsigned long
2009i386_mach ()
2010{
2011 if (!strcmp (default_arch, "x86_64"))
2012 return bfd_mach_x86_64;
2013 else if (!strcmp (default_arch, "i386"))
2014 return bfd_mach_i386_i386;
2015 else
2016 as_fatal (_("Unknown architecture"));
2017}
b9d79e03 2018\f
252b5132
RH		 2019void
2020md_begin ()
2021{
2022 const char *hash_err;
2023
47926f60 2024 /* Initialize op_hash hash table. */
252b5132
RH		 2025 op_hash = hash_new ();
2026
2027 {
29b0f896
AM		 2028 const template *optab;
2029 templates *core_optab;
252b5132 2030
47926f60
KH		 2031 /* Setup for loop. */
2032 optab = i386_optab;
252b5132
RH		 2033 core_optab = (templates *) xmalloc (sizeof (templates));
2034 core_optab->start = optab;
2035
2036 while (1)
2037 {
2038 ++optab;
2039 if (optab->name == NULL
2040 || strcmp (optab->name, (optab - 1)->name) != 0)
2041 {
2042 /* different name --> ship out current template list;
47926f60 2043 add to hash table; & begin anew. */
252b5132
RH		 2044 core_optab->end = optab;
2045 hash_err = hash_insert (op_hash,
2046 (optab - 1)->name,
5a49b8ac 2047 (void *) core_optab);
252b5132
RH		 2048 if (hash_err)
2049 {
252b5132
RH		 2050 as_fatal (_("Internal Error: Can't hash %s: %s"),
2051 (optab - 1)->name,
2052 hash_err);
2053 }
2054 if (optab->name == NULL)
2055 break;
2056 core_optab = (templates *) xmalloc (sizeof (templates));
2057 core_optab->start = optab;
2058 }
2059 }
2060 }
2061
47926f60 2062 /* Initialize reg_hash hash table. */
252b5132
RH		 2063 reg_hash = hash_new ();
2064 {
29b0f896 2065 const reg_entry *regtab;
c3fe08fa 2066 unsigned int regtab_size = i386_regtab_size;
252b5132 2067
c3fe08fa 2068 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2069 {
5a49b8ac 2070 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2071 if (hash_err)
3e73aa7c
JH		 2072 as_fatal (_("Internal Error: Can't hash %s: %s"),
2073 regtab->reg_name,
2074 hash_err);
252b5132
RH		 2075 }
2076 }
2077
47926f60 2078 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2079 {
29b0f896
AM		 2080 int c;
2081 char *p;
252b5132
RH		 2082
2083 for (c = 0; c < 256; c++)
2084 {
3882b010 2085 if (ISDIGIT (c))
252b5132
RH		 2086 {
2087 digit_chars[c] = c;
2088 mnemonic_chars[c] = c;
2089 register_chars[c] = c;
2090 operand_chars[c] = c;
2091 }
3882b010 2092 else if (ISLOWER (c))
252b5132
RH		 2093 {
2094 mnemonic_chars[c] = c;
2095 register_chars[c] = c;
2096 operand_chars[c] = c;
2097 }
3882b010 2098 else if (ISUPPER (c))
252b5132 2099 {
3882b010 2100 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2101 register_chars[c] = mnemonic_chars[c];
2102 operand_chars[c] = c;
2103 }
2104
3882b010 2105 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2106 identifier_chars[c] = c;
2107 else if (c >= 128)
2108 {
2109 identifier_chars[c] = c;
2110 operand_chars[c] = c;
2111 }
2112 }
2113
2114#ifdef LEX_AT
2115 identifier_chars['@'] = '@';
32137342
NC		 2116#endif
2117#ifdef LEX_QM
2118 identifier_chars['?'] = '?';
2119 operand_chars['?'] = '?';
252b5132 2120#endif
252b5132 2121 digit_chars['-'] = '-';
c0f3af97 2122 mnemonic_chars['_'] = '_';
791fe849 2123 mnemonic_chars['-'] = '-';
0003779b 2124 mnemonic_chars['.'] = '.';
252b5132
RH		 2125 identifier_chars['_'] = '_';
2126 identifier_chars['.'] = '.';
2127
2128 for (p = operand_special_chars; *p != '\0'; p++)
2129 operand_chars[(unsigned char) *p] = *p;
2130 }
2131
2132#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2133 if (IS_ELF)
252b5132
RH		 2134 {
2135 record_alignment (text_section, 2);
2136 record_alignment (data_section, 2);
2137 record_alignment (bss_section, 2);
2138 }
2139#endif
a4447b93
RH		 2140
2141 if (flag_code == CODE_64BIT)
2142 {
2143 x86_dwarf2_return_column = 16;
2144 x86_cie_data_alignment = -8;
2145 }
2146 else
2147 {
2148 x86_dwarf2_return_column = 8;
2149 x86_cie_data_alignment = -4;
2150 }
252b5132
RH		 2151}
2152
2153void
e3bb37b5 2154i386_print_statistics (FILE *file)
252b5132
RH		 2155{
2156 hash_print_statistics (file, "i386 opcode", op_hash);
2157 hash_print_statistics (file, "i386 register", reg_hash);
2158}
2159\f
252b5132
RH		 2160#ifdef DEBUG386
2161
ce8a8b2f 2162/* Debugging routines for md_assemble. */
e3bb37b5 2163static void pte (template *);
40fb9820 2164static void pt (i386_operand_type);
e3bb37b5
L		 2165static void pe (expressionS *);
2166static void ps (symbolS *);
252b5132
RH		 2167
2168static void
e3bb37b5 2169pi (char *line, i386_insn *x)
252b5132 2170{
09f131f2 2171 unsigned int i;
252b5132
RH		 2172
2173 fprintf (stdout, "%s: template ", line);
2174 pte (&x->tm);
09f131f2
JH		 2175 fprintf (stdout, " address: base %s index %s scale %x\n",
2176 x->base_reg ? x->base_reg->reg_name : "none",
2177 x->index_reg ? x->index_reg->reg_name : "none",
2178 x->log2_scale_factor);
2179 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2180 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2181 fprintf (stdout, " sib: base %x index %x scale %x\n",
2182 x->sib.base, x->sib.index, x->sib.scale);
2183 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2184 (x->rex & REX_W) != 0,
2185 (x->rex & REX_R) != 0,
2186 (x->rex & REX_X) != 0,
2187 (x->rex & REX_B) != 0);
252b5132
RH		 2188 for (i = 0; i < x->operands; i++)
2189 {
2190 fprintf (stdout, " #%d: ", i + 1);
2191 pt (x->types[i]);
2192 fprintf (stdout, "\n");
40fb9820
L		 2193 if (x->types[i].bitfield.reg8
2194 || x->types[i].bitfield.reg16
2195 || x->types[i].bitfield.reg32
2196 || x->types[i].bitfield.reg64
2197 || x->types[i].bitfield.regmmx
2198 || x->types[i].bitfield.regxmm
c0f3af97 2199 || x->types[i].bitfield.regymm
40fb9820
L		 2200 || x->types[i].bitfield.sreg2
2201 || x->types[i].bitfield.sreg3
2202 || x->types[i].bitfield.control
2203 || x->types[i].bitfield.debug
2204 || x->types[i].bitfield.test)
520dc8e8 2205 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 2206 if (operand_type_check (x->types[i], imm))
520dc8e8 2207 pe (x->op[i].imms);
40fb9820 2208 if (operand_type_check (x->types[i], disp))
520dc8e8 2209 pe (x->op[i].disps);
252b5132
RH		 2210 }
2211}
2212
2213static void
e3bb37b5 2214pte (template *t)
252b5132 2215{
09f131f2 2216 unsigned int i;
252b5132 2217 fprintf (stdout, " %d operands ", t->operands);
47926f60 2218 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2219 if (t->extension_opcode != None)
2220 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2221 if (t->opcode_modifier.d)
252b5132 2222 fprintf (stdout, "D");
40fb9820 2223 if (t->opcode_modifier.w)
252b5132
RH		 2224 fprintf (stdout, "W");
2225 fprintf (stdout, "\n");
2226 for (i = 0; i < t->operands; i++)
2227 {
2228 fprintf (stdout, " #%d type ", i + 1);
2229 pt (t->operand_types[i]);
2230 fprintf (stdout, "\n");
2231 }
2232}
2233
2234static void
e3bb37b5 2235pe (expressionS *e)
252b5132 2236{
24eab124 2237 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2238 fprintf (stdout, " add_number %ld (%lx)\n",
2239 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2240 if (e->X_add_symbol)
2241 {
2242 fprintf (stdout, " add_symbol ");
2243 ps (e->X_add_symbol);
2244 fprintf (stdout, "\n");
2245 }
2246 if (e->X_op_symbol)
2247 {
2248 fprintf (stdout, " op_symbol ");
2249 ps (e->X_op_symbol);
2250 fprintf (stdout, "\n");
2251 }
2252}
2253
2254static void
e3bb37b5 2255ps (symbolS *s)
252b5132
RH		 2256{
2257 fprintf (stdout, "%s type %s%s",
2258 S_GET_NAME (s),
2259 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2260 segment_name (S_GET_SEGMENT (s)));
2261}
2262
7b81dfbb 2263static struct type_name
252b5132 2264 {
40fb9820
L		 2265 i386_operand_type mask;
2266 const char *name;
252b5132 2267 }
7b81dfbb 2268const type_names[] =
252b5132 2269{
40fb9820
L		 2270 { OPERAND_TYPE_REG8, "r8" },
2271 { OPERAND_TYPE_REG16, "r16" },
2272 { OPERAND_TYPE_REG32, "r32" },
2273 { OPERAND_TYPE_REG64, "r64" },
2274 { OPERAND_TYPE_IMM8, "i8" },
2275 { OPERAND_TYPE_IMM8, "i8s" },
2276 { OPERAND_TYPE_IMM16, "i16" },
2277 { OPERAND_TYPE_IMM32, "i32" },
2278 { OPERAND_TYPE_IMM32S, "i32s" },
2279 { OPERAND_TYPE_IMM64, "i64" },
2280 { OPERAND_TYPE_IMM1, "i1" },
2281 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2282 { OPERAND_TYPE_DISP8, "d8" },
2283 { OPERAND_TYPE_DISP16, "d16" },
2284 { OPERAND_TYPE_DISP32, "d32" },
2285 { OPERAND_TYPE_DISP32S, "d32s" },
2286 { OPERAND_TYPE_DISP64, "d64" },
2287 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2288 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2289 { OPERAND_TYPE_CONTROL, "control reg" },
2290 { OPERAND_TYPE_TEST, "test reg" },
2291 { OPERAND_TYPE_DEBUG, "debug reg" },
2292 { OPERAND_TYPE_FLOATREG, "FReg" },
2293 { OPERAND_TYPE_FLOATACC, "FAcc" },
2294 { OPERAND_TYPE_SREG2, "SReg2" },
2295 { OPERAND_TYPE_SREG3, "SReg3" },
2296 { OPERAND_TYPE_ACC, "Acc" },
2297 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2298 { OPERAND_TYPE_REGMMX, "rMMX" },
2299 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2300 { OPERAND_TYPE_REGYMM, "rYMM" },
40fb9820 2301 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2302};
2303
2304static void
40fb9820 2305pt (i386_operand_type t)
252b5132 2306{
40fb9820 2307 unsigned int j;
c6fb90c8 2308 i386_operand_type a;
252b5132 2309
40fb9820 2310 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2311 {
2312 a = operand_type_and (t, type_names[j].mask);
0349dc08 2313 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2314 fprintf (stdout, "%s, ", type_names[j].name);
2315 }
252b5132
RH		 2316 fflush (stdout);
2317}
2318
2319#endif /* DEBUG386 */
2320\f
252b5132 2321static bfd_reloc_code_real_type
3956db08 2322reloc (unsigned int size,
64e74474
AM		 2323 int pcrel,
2324 int sign,
2325 bfd_reloc_code_real_type other)
252b5132 2326{
47926f60 2327 if (other != NO_RELOC)
3956db08
JB		 2328 {
2329 reloc_howto_type *reloc;
2330
2331 if (size == 8)
2332 switch (other)
2333 {
64e74474
AM		 2334 case BFD_RELOC_X86_64_GOT32:
2335 return BFD_RELOC_X86_64_GOT64;
2336 break;
2337 case BFD_RELOC_X86_64_PLTOFF64:
2338 return BFD_RELOC_X86_64_PLTOFF64;
2339 break;
2340 case BFD_RELOC_X86_64_GOTPC32:
2341 other = BFD_RELOC_X86_64_GOTPC64;
2342 break;
2343 case BFD_RELOC_X86_64_GOTPCREL:
2344 other = BFD_RELOC_X86_64_GOTPCREL64;
2345 break;
2346 case BFD_RELOC_X86_64_TPOFF32:
2347 other = BFD_RELOC_X86_64_TPOFF64;
2348 break;
2349 case BFD_RELOC_X86_64_DTPOFF32:
2350 other = BFD_RELOC_X86_64_DTPOFF64;
2351 break;
2352 default:
2353 break;
3956db08 2354 }
e05278af
JB		 2355
2356 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2357 if (size == 4 && flag_code != CODE_64BIT)
2358 sign = -1;
2359
3956db08
JB		 2360 reloc = bfd_reloc_type_lookup (stdoutput, other);
2361 if (!reloc)
2362 as_bad (_("unknown relocation (%u)"), other);
2363 else if (size != bfd_get_reloc_size (reloc))
2364 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2365 bfd_get_reloc_size (reloc),
2366 size);
2367 else if (pcrel && !reloc->pc_relative)
2368 as_bad (_("non-pc-relative relocation for pc-relative field"));
2369 else if ((reloc->complain_on_overflow == complain_overflow_signed
2370 && !sign)
2371 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 2372 && sign > 0))
3956db08
JB		 2373 as_bad (_("relocated field and relocation type differ in signedness"));
2374 else
2375 return other;
2376 return NO_RELOC;
2377 }
252b5132
RH		 2378
2379 if (pcrel)
2380 {
3e73aa7c 2381 if (!sign)
3956db08 2382 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2383 switch (size)
2384 {
2385 case 1: return BFD_RELOC_8_PCREL;
2386 case 2: return BFD_RELOC_16_PCREL;
2387 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2388 case 8: return BFD_RELOC_64_PCREL;
252b5132 2389 }
3956db08 2390 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2391 }
2392 else
2393 {
3956db08 2394 if (sign > 0)
e5cb08ac 2395 switch (size)
3e73aa7c
JH		 2396 {
2397 case 4: return BFD_RELOC_X86_64_32S;
2398 }
2399 else
2400 switch (size)
2401 {
2402 case 1: return BFD_RELOC_8;
2403 case 2: return BFD_RELOC_16;
2404 case 4: return BFD_RELOC_32;
2405 case 8: return BFD_RELOC_64;
2406 }
3956db08
JB		 2407 as_bad (_("cannot do %s %u byte relocation"),
2408 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2409 }
2410
0cc9e1d3 2411 return NO_RELOC;
252b5132
RH		 2412}
2413
47926f60
KH		 2414/* Here we decide which fixups can be adjusted to make them relative to
2415 the beginning of the section instead of the symbol. Basically we need
2416 to make sure that the dynamic relocations are done correctly, so in
2417 some cases we force the original symbol to be used. */
2418
252b5132 2419int
e3bb37b5 2420tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2421{
6d249963 2422#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2423 if (!IS_ELF)
31312f95
AM		 2424 return 1;
2425
a161fe53
AM		 2426 /* Don't adjust pc-relative references to merge sections in 64-bit
2427 mode. */
2428 if (use_rela_relocations
2429 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2430 && fixP->fx_pcrel)
252b5132 2431 return 0;
31312f95 2432
8d01d9a9
AJ		 2433 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2434 and changed later by validate_fix. */
2435 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2436 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2437 return 0;
2438
ce8a8b2f 2439 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2440 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2441 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2442 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2443 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2444 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2445 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2446 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2447 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2448 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2449 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2450 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2451 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2452 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2453 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2454 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2455 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2456 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2457 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2458 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2459 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2460 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2461 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2462 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2463 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2464 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2465 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2466 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2467 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2468 return 0;
d8045f23
NC		 2469
2470 if (fixP->fx_addsy != NULL
2471 && symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_GNU_INDIRECT_FUNCTION)
2472 return 0;
31312f95 2473#endif
252b5132
RH		 2474 return 1;
2475}
252b5132 2476
b4cac588 2477static int
e3bb37b5 2478intel_float_operand (const char *mnemonic)
252b5132 2479{
9306ca4a
JB		 2480 /* Note that the value returned is meaningful only for opcodes with (memory)
2481 operands, hence the code here is free to improperly handle opcodes that
2482 have no operands (for better performance and smaller code). */
2483
2484 if (mnemonic[0] != 'f')
2485 return 0; /* non-math */
2486
2487 switch (mnemonic[1])
2488 {
2489 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2490 the fs segment override prefix not currently handled because no
2491 call path can make opcodes without operands get here */
2492 case 'i':
2493 return 2 /* integer op */;
2494 case 'l':
2495 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2496 return 3; /* fldcw/fldenv */
2497 break;
2498 case 'n':
2499 if (mnemonic[2] != 'o' /* fnop */)
2500 return 3; /* non-waiting control op */
2501 break;
2502 case 'r':
2503 if (mnemonic[2] == 's')
2504 return 3; /* frstor/frstpm */
2505 break;
2506 case 's':
2507 if (mnemonic[2] == 'a')
2508 return 3; /* fsave */
2509 if (mnemonic[2] == 't')
2510 {
2511 switch (mnemonic[3])
2512 {
2513 case 'c': /* fstcw */
2514 case 'd': /* fstdw */
2515 case 'e': /* fstenv */
2516 case 's': /* fsts[gw] */
2517 return 3;
2518 }
2519 }
2520 break;
2521 case 'x':
2522 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2523 return 0; /* fxsave/fxrstor are not really math ops */
2524 break;
2525 }
252b5132 2526
9306ca4a 2527 return 1;
252b5132
RH		 2528}
2529
c0f3af97
L		 2530/* Build the VEX prefix. */
2531
2532static void
fa99fab2 2533build_vex_prefix (const template *t)
c0f3af97
L		 2534{
2535 unsigned int register_specifier;
2536 unsigned int implied_prefix;
2537 unsigned int vector_length;
2538
2539 /* Check register specifier. */
2540 if (i.vex.register_specifier)
2541 {
2542 register_specifier = i.vex.register_specifier->reg_num;
2543 if ((i.vex.register_specifier->reg_flags & RegRex))
2544 register_specifier += 8;
2545 register_specifier = ~register_specifier & 0xf;
2546 }
2547 else
2548 register_specifier = 0xf;
2549
fa99fab2
L		 2550 /* Use 2-byte VEX prefix by swappping destination and source
2551 operand. */
2552 if (!i.swap_operand
2553 && i.operands == i.reg_operands
2554 && i.tm.opcode_modifier.vex0f
2555 && i.tm.opcode_modifier.s
2556 && i.rex == REX_B)
2557 {
2558 unsigned int xchg = i.operands - 1;
2559 union i386_op temp_op;
2560 i386_operand_type temp_type;
2561
2562 temp_type = i.types[xchg];
2563 i.types[xchg] = i.types[0];
2564 i.types[0] = temp_type;
2565 temp_op = i.op[xchg];
2566 i.op[xchg] = i.op[0];
2567 i.op[0] = temp_op;
2568
9c2799c2 2569 gas_assert (i.rm.mode == 3);
fa99fab2
L		 2570
2571 i.rex = REX_R;
2572 xchg = i.rm.regmem;
2573 i.rm.regmem = i.rm.reg;
2574 i.rm.reg = xchg;
2575
2576 /* Use the next insn. */
2577 i.tm = t[1];
2578 }
2579
c0f3af97
L		 2580 vector_length = i.tm.opcode_modifier.vex256 ? 1 : 0;
2581
2582 switch ((i.tm.base_opcode >> 8) & 0xff)
2583 {
2584 case 0:
2585 implied_prefix = 0;
2586 break;
2587 case DATA_PREFIX_OPCODE:
2588 implied_prefix = 1;
2589 break;
2590 case REPE_PREFIX_OPCODE:
2591 implied_prefix = 2;
2592 break;
2593 case REPNE_PREFIX_OPCODE:
2594 implied_prefix = 3;
2595 break;
2596 default:
2597 abort ();
2598 }
2599
2600 /* Use 2-byte VEX prefix if possible. */
2601 if (i.tm.opcode_modifier.vex0f
2602 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2603 {
2604 /* 2-byte VEX prefix. */
2605 unsigned int r;
2606
2607 i.vex.length = 2;
2608 i.vex.bytes[0] = 0xc5;
2609
2610 /* Check the REX.R bit. */
2611 r = (i.rex & REX_R) ? 0 : 1;
2612 i.vex.bytes[1] = (r << 7
2613 | register_specifier << 3
2614 | vector_length << 2
2615 | implied_prefix);
2616 }
2617 else
2618 {
2619 /* 3-byte VEX prefix. */
2620 unsigned int m, w;
2621
2622 if (i.tm.opcode_modifier.vex0f)
2623 m = 0x1;
2624 else if (i.tm.opcode_modifier.vex0f38)
2625 m = 0x2;
2626 else if (i.tm.opcode_modifier.vex0f3a)
2627 m = 0x3;
2628 else
2629 abort ();
2630
2631 i.vex.length = 3;
2632 i.vex.bytes[0] = 0xc4;
2633
2634 /* The high 3 bits of the second VEX byte are 1's compliment
2635 of RXB bits from REX. */
2636 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2637
2638 /* Check the REX.W bit. */
2639 w = (i.rex & REX_W) ? 1 : 0;
2640 if (i.tm.opcode_modifier.vexw0 || i.tm.opcode_modifier.vexw1)
2641 {
2642 if (w)
2643 abort ();
2644
2645 if (i.tm.opcode_modifier.vexw1)
2646 w = 1;
2647 }
2648
2649 i.vex.bytes[2] = (w << 7
2650 | register_specifier << 3
2651 | vector_length << 2
2652 | implied_prefix);
2653 }
2654}
2655
65da13b5
L		 2656static void
2657process_immext (void)
2658{
2659 expressionS *exp;
2660
2661 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2662 {
1fed0ba1
L		 2663 /* SSE3 Instructions have the fixed operands with an opcode
2664 suffix which is coded in the same place as an 8-bit immediate
2665 field would be. Here we check those operands and remove them
2666 afterwards. */
65da13b5
L		 2667 unsigned int x;
2668
2669 for (x = 0; x < i.operands; x++)
2670 if (i.op[x].regs->reg_num != x)
2671 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 2672 register_prefix, i.op[x].regs->reg_name, x + 1,
2673 i.tm.name);
2674
2675 i.operands = 0;
65da13b5
L		 2676 }
2677
c0f3af97 2678 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 2679 which is coded in the same place as an 8-bit immediate field
2680 would be. Here we fake an 8-bit immediate operand from the
2681 opcode suffix stored in tm.extension_opcode.
2682
c1e679ec 2683 AVX instructions also use this encoding, for some of
c0f3af97 2684 3 argument instructions. */
65da13b5 2685
9c2799c2 2686 gas_assert (i.imm_operands == 0
7ab9ffdd
L		 2687 && (i.operands <= 2
2688 || (i.tm.opcode_modifier.vex
2689 && i.operands <= 4)));
65da13b5
L		 2690
2691 exp = &im_expressions[i.imm_operands++];
2692 i.op[i.operands].imms = exp;
2693 i.types[i.operands] = imm8;
2694 i.operands++;
2695 exp->X_op = O_constant;
2696 exp->X_add_number = i.tm.extension_opcode;
2697 i.tm.extension_opcode = None;
2698}
2699
252b5132
RH		 2700/* This is the guts of the machine-dependent assembler. LINE points to a
2701 machine dependent instruction. This function is supposed to emit
2702 the frags/bytes it assembles to. */
2703
2704void
65da13b5 2705md_assemble (char *line)
252b5132 2706{
40fb9820 2707 unsigned int j;
252b5132 2708 char mnemonic[MAX_MNEM_SIZE];
fa99fab2 2709 const template *t;
252b5132 2710
47926f60 2711 /* Initialize globals. */
252b5132
RH		 2712 memset (&i, '\0', sizeof (i));
2713 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2714 i.reloc[j] = NO_RELOC;
252b5132
RH		 2715 memset (disp_expressions, '\0', sizeof (disp_expressions));
2716 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2717 save_stack_p = save_stack;
252b5132
RH		 2718
2719 /* First parse an instruction mnemonic & call i386_operand for the operands.
2720 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2721 start of a (possibly prefixed) mnemonic. */
252b5132 2722
29b0f896
AM		 2723 line = parse_insn (line, mnemonic);
2724 if (line == NULL)
2725 return;
252b5132 2726
29b0f896 2727 line = parse_operands (line, mnemonic);
ee86248c 2728 this_operand = -1;
29b0f896
AM		 2729 if (line == NULL)
2730 return;
252b5132 2731
29b0f896
AM		 2732 /* Now we've parsed the mnemonic into a set of templates, and have the
2733 operands at hand. */
2734
2735 /* All intel opcodes have reversed operands except for "bound" and
2736 "enter". We also don't reverse intersegment "jmp" and "call"
2737 instructions with 2 immediate operands so that the immediate segment
050dfa73 2738 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2739 if (intel_syntax
2740 && i.operands > 1
29b0f896 2741 && (strcmp (mnemonic, "bound") != 0)
30123838 2742 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2743 && !(operand_type_check (i.types[0], imm)
2744 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2745 swap_operands ();
2746
ec56d5c0
JB		 2747 /* The order of the immediates should be reversed
2748 for 2 immediates extrq and insertq instructions */
2749 if (i.imm_operands == 2
2750 && (strcmp (mnemonic, "extrq") == 0
2751 || strcmp (mnemonic, "insertq") == 0))
2752 swap_2_operands (0, 1);
2753
29b0f896
AM		 2754 if (i.imm_operands)
2755 optimize_imm ();
2756
b300c311
L		 2757 /* Don't optimize displacement for movabs since it only takes 64bit
2758 displacement. */
2759 if (i.disp_operands
2760 && (flag_code != CODE_64BIT
2761 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2762 optimize_disp ();
2763
2764 /* Next, we find a template that matches the given insn,
2765 making sure the overlap of the given operands types is consistent
2766 with the template operand types. */
252b5132 2767
fa99fab2 2768 if (!(t = match_template ()))
29b0f896 2769 return;
252b5132 2770
daf50ae7 2771 if (sse_check != sse_check_none
81f8a913 2772 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 2773 && (i.tm.cpu_flags.bitfield.cpusse
2774 || i.tm.cpu_flags.bitfield.cpusse2
2775 || i.tm.cpu_flags.bitfield.cpusse3
2776 || i.tm.cpu_flags.bitfield.cpussse3
2777 || i.tm.cpu_flags.bitfield.cpusse4_1
2778 || i.tm.cpu_flags.bitfield.cpusse4_2))
2779 {
2780 (sse_check == sse_check_warning
2781 ? as_warn
2782 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
2783 }
2784
321fd21e
L		 2785 /* Zap movzx and movsx suffix. The suffix has been set from
2786 "word ptr" or "byte ptr" on the source operand in Intel syntax
2787 or extracted from mnemonic in AT&T syntax. But we'll use
2788 the destination register to choose the suffix for encoding. */
2789 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 2790 {
321fd21e
L		 2791 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2792 there is no suffix, the default will be byte extension. */
2793 if (i.reg_operands != 2
2794 && !i.suffix
7ab9ffdd 2795 && intel_syntax)
321fd21e
L		 2796 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2797
2798 i.suffix = 0;
cd61ebfe 2799 }
24eab124 2800
40fb9820 2801 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2802 if (!add_prefix (FWAIT_OPCODE))
2803 return;
252b5132 2804
29b0f896 2805 /* Check string instruction segment overrides. */
40fb9820 2806 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 2807 {
2808 if (!check_string ())
5dd0794d 2809 return;
fc0763e6 2810 i.disp_operands = 0;
29b0f896 2811 }
5dd0794d 2812
29b0f896
AM		 2813 if (!process_suffix ())
2814 return;
e413e4e9 2815
29b0f896
AM		 2816 /* Make still unresolved immediate matches conform to size of immediate
2817 given in i.suffix. */
2818 if (!finalize_imm ())
2819 return;
252b5132 2820
40fb9820 2821 if (i.types[0].bitfield.imm1)
29b0f896 2822 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 2823
915bcca5 2824 for (j = 0; j < i.operands; j++)
c6fb90c8
L		 2825 if (i.types[j].bitfield.inoutportreg
2826 || i.types[j].bitfield.shiftcount
2827 || i.types[j].bitfield.acc
2828 || i.types[j].bitfield.floatacc)
40fb9820
L		 2829 i.reg_operands--;
2830
c0f3af97
L		 2831 /* ImmExt should be processed after SSE2AVX. */
2832 if (!i.tm.opcode_modifier.sse2avx
2833 && i.tm.opcode_modifier.immext)
65da13b5 2834 process_immext ();
252b5132 2835
29b0f896
AM		 2836 /* For insns with operands there are more diddles to do to the opcode. */
2837 if (i.operands)
2838 {
2839 if (!process_operands ())
2840 return;
2841 }
40fb9820 2842 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 2843 {
2844 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2845 as_warn (_("translating to `%sp'"), i.tm.name);
2846 }
252b5132 2847
c0f3af97 2848 if (i.tm.opcode_modifier.vex)
fa99fab2 2849 build_vex_prefix (t);
c0f3af97 2850
29b0f896
AM		 2851 /* Handle conversion of 'int $3' --> special int3 insn. */
2852 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2853 {
2854 i.tm.base_opcode = INT3_OPCODE;
2855 i.imm_operands = 0;
2856 }
252b5132 2857
40fb9820
L		 2858 if ((i.tm.opcode_modifier.jump
2859 || i.tm.opcode_modifier.jumpbyte
2860 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 2861 && i.op[0].disps->X_op == O_constant)
2862 {
2863 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2864 the absolute address given by the constant. Since ix86 jumps and
2865 calls are pc relative, we need to generate a reloc. */
2866 i.op[0].disps->X_add_symbol = &abs_symbol;
2867 i.op[0].disps->X_op = O_symbol;
2868 }
252b5132 2869
40fb9820 2870 if (i.tm.opcode_modifier.rex64)
161a04f6 2871 i.rex |= REX_W;
252b5132 2872
29b0f896
AM		 2873 /* For 8 bit registers we need an empty rex prefix. Also if the
2874 instruction already has a prefix, we need to convert old
2875 registers to new ones. */
773f551c 2876
40fb9820 2877 if ((i.types[0].bitfield.reg8
29b0f896 2878 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 2879 || (i.types[1].bitfield.reg8
29b0f896 2880 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 2881 || ((i.types[0].bitfield.reg8
2882 || i.types[1].bitfield.reg8)
29b0f896
AM		 2883 && i.rex != 0))
2884 {
2885 int x;
726c5dcd 2886
29b0f896
AM		 2887 i.rex |= REX_OPCODE;
2888 for (x = 0; x < 2; x++)
2889 {
2890 /* Look for 8 bit operand that uses old registers. */
40fb9820 2891 if (i.types[x].bitfield.reg8
29b0f896 2892 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 2893 {
29b0f896
AM		 2894 /* In case it is "hi" register, give up. */
2895 if (i.op[x].regs->reg_num > 3)
a540244d 2896 as_bad (_("can't encode register '%s%s' in an "
4eed87de 2897 "instruction requiring REX prefix."),
a540244d 2898 register_prefix, i.op[x].regs->reg_name);
773f551c 2899
29b0f896
AM		 2900 /* Otherwise it is equivalent to the extended register.
2901 Since the encoding doesn't change this is merely
2902 cosmetic cleanup for debug output. */
2903
2904 i.op[x].regs = i.op[x].regs + 8;
773f551c 2905 }
29b0f896
AM		 2906 }
2907 }
773f551c 2908
7ab9ffdd 2909 if (i.rex != 0)
29b0f896
AM		 2910 add_prefix (REX_OPCODE | i.rex);
2911
2912 /* We are ready to output the insn. */
2913 output_insn ();
2914}
2915
2916static char *
e3bb37b5 2917parse_insn (char *line, char *mnemonic)
29b0f896
AM		 2918{
2919 char *l = line;
2920 char *token_start = l;
2921 char *mnem_p;
5c6af06e
JB		 2922 int supported;
2923 const template *t;
b6169b20 2924 char *dot_p = NULL;
29b0f896
AM		 2925
2926 /* Non-zero if we found a prefix only acceptable with string insns. */
2927 const char *expecting_string_instruction = NULL;
45288df1 2928
29b0f896
AM		 2929 while (1)
2930 {
2931 mnem_p = mnemonic;
2932 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2933 {
b6169b20
L		 2934 if (*mnem_p == '.')
2935 dot_p = mnem_p;
29b0f896
AM		 2936 mnem_p++;
2937 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 2938 {
29b0f896
AM		 2939 as_bad (_("no such instruction: `%s'"), token_start);
2940 return NULL;
2941 }
2942 l++;
2943 }
2944 if (!is_space_char (*l)
2945 && *l != END_OF_INSN
e44823cf
JB		 2946 && (intel_syntax
2947 || (*l != PREFIX_SEPARATOR
2948 && *l != ',')))
29b0f896
AM		 2949 {
2950 as_bad (_("invalid character %s in mnemonic"),
2951 output_invalid (*l));
2952 return NULL;
2953 }
2954 if (token_start == l)
2955 {
e44823cf 2956 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 2957 as_bad (_("expecting prefix; got nothing"));
2958 else
2959 as_bad (_("expecting mnemonic; got nothing"));
2960 return NULL;
2961 }
45288df1 2962
29b0f896
AM		 2963 /* Look up instruction (or prefix) via hash table. */
2964 current_templates = hash_find (op_hash, mnemonic);
47926f60 2965
29b0f896
AM		 2966 if (*l != END_OF_INSN
2967 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2968 && current_templates
40fb9820 2969 && current_templates->start->opcode_modifier.isprefix)
29b0f896 2970 {
c6fb90c8 2971 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 2972 {
2973 as_bad ((flag_code != CODE_64BIT
2974 ? _("`%s' is only supported in 64-bit mode")
2975 : _("`%s' is not supported in 64-bit mode")),
2976 current_templates->start->name);
2977 return NULL;
2978 }
29b0f896
AM		 2979 /* If we are in 16-bit mode, do not allow addr16 or data16.
2980 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 2981 if ((current_templates->start->opcode_modifier.size16
2982 || current_templates->start->opcode_modifier.size32)
29b0f896 2983 && flag_code != CODE_64BIT
40fb9820 2984 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 2985 ^ (flag_code == CODE_16BIT)))
2986 {
2987 as_bad (_("redundant %s prefix"),
2988 current_templates->start->name);
2989 return NULL;
45288df1 2990 }
29b0f896
AM		 2991 /* Add prefix, checking for repeated prefixes. */
2992 switch (add_prefix (current_templates->start->base_opcode))
2993 {
2994 case 0:
2995 return NULL;
2996 case 2:
2997 expecting_string_instruction = current_templates->start->name;
2998 break;
2999 }
3000 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3001 token_start = ++l;
3002 }
3003 else
3004 break;
3005 }
45288df1 3006
30a55f88 3007 if (!current_templates)
b6169b20 3008 {
30a55f88
L		 3009 /* Check if we should swap operand in encoding. */
3010 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3011 i.swap_operand = 1;
3012 else
3013 goto check_suffix;
3014 mnem_p = dot_p;
3015 *dot_p = '\0';
3016 current_templates = hash_find (op_hash, mnemonic);
b6169b20
L		 3017 }
3018
29b0f896
AM		 3019 if (!current_templates)
3020 {
b6169b20 3021check_suffix:
29b0f896
AM		 3022 /* See if we can get a match by trimming off a suffix. */
3023 switch (mnem_p[-1])
3024 {
3025 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3026 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3027 i.suffix = SHORT_MNEM_SUFFIX;
3028 else
29b0f896
AM		 3029 case BYTE_MNEM_SUFFIX:
3030 case QWORD_MNEM_SUFFIX:
3031 i.suffix = mnem_p[-1];
3032 mnem_p[-1] = '\0';
3033 current_templates = hash_find (op_hash, mnemonic);
3034 break;
3035 case SHORT_MNEM_SUFFIX:
3036 case LONG_MNEM_SUFFIX:
3037 if (!intel_syntax)
3038 {
3039 i.suffix = mnem_p[-1];
3040 mnem_p[-1] = '\0';
3041 current_templates = hash_find (op_hash, mnemonic);
3042 }
3043 break;
252b5132 3044
29b0f896
AM		 3045 /* Intel Syntax. */
3046 case 'd':
3047 if (intel_syntax)
3048 {
9306ca4a 3049 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3050 i.suffix = SHORT_MNEM_SUFFIX;
3051 else
3052 i.suffix = LONG_MNEM_SUFFIX;
3053 mnem_p[-1] = '\0';
3054 current_templates = hash_find (op_hash, mnemonic);
3055 }
3056 break;
3057 }
3058 if (!current_templates)
3059 {
3060 as_bad (_("no such instruction: `%s'"), token_start);
3061 return NULL;
3062 }
3063 }
252b5132 3064
40fb9820
L		 3065 if (current_templates->start->opcode_modifier.jump
3066 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3067 {
3068 /* Check for a branch hint. We allow ",pt" and ",pn" for
3069 predict taken and predict not taken respectively.
3070 I'm not sure that branch hints actually do anything on loop
3071 and jcxz insns (JumpByte) for current Pentium4 chips. They
3072 may work in the future and it doesn't hurt to accept them
3073 now. */
3074 if (l[0] == ',' && l[1] == 'p')
3075 {
3076 if (l[2] == 't')
3077 {
3078 if (!add_prefix (DS_PREFIX_OPCODE))
3079 return NULL;
3080 l += 3;
3081 }
3082 else if (l[2] == 'n')
3083 {
3084 if (!add_prefix (CS_PREFIX_OPCODE))
3085 return NULL;
3086 l += 3;
3087 }
3088 }
3089 }
3090 /* Any other comma loses. */
3091 if (*l == ',')
3092 {
3093 as_bad (_("invalid character %s in mnemonic"),
3094 output_invalid (*l));
3095 return NULL;
3096 }
252b5132 3097
29b0f896 3098 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3099 supported = 0;
3100 for (t = current_templates->start; t < current_templates->end; ++t)
3101 {
c0f3af97
L		 3102 supported |= cpu_flags_match (t);
3103 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3104 goto skip;
5c6af06e 3105 }
3629bb00 3106
c0f3af97 3107 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3108 {
3109 as_bad (flag_code == CODE_64BIT
3110 ? _("`%s' is not supported in 64-bit mode")
3111 : _("`%s' is only supported in 64-bit mode"),
3112 current_templates->start->name);
3113 return NULL;
3114 }
c0f3af97 3115 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3116 {
3629bb00 3117 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3118 current_templates->start->name,
41aacd83 3119 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3120 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3121 return NULL;
29b0f896 3122 }
3629bb00
L		 3123
3124skip:
3125 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3126 && (flag_code != CODE_16BIT))
29b0f896
AM		 3127 {
3128 as_warn (_("use .code16 to ensure correct addressing mode"));
3129 }
252b5132 3130
29b0f896 3131 /* Check for rep/repne without a string instruction. */
f41bbced 3132 if (expecting_string_instruction)
29b0f896 3133 {
f41bbced
JB		 3134 static templates override;
3135
3136 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 3137 if (t->opcode_modifier.isstring)
f41bbced
JB		 3138 break;
3139 if (t >= current_templates->end)
3140 {
3141 as_bad (_("expecting string instruction after `%s'"),
64e74474 3142 expecting_string_instruction);
f41bbced
JB		 3143 return NULL;
3144 }
3145 for (override.start = t; t < current_templates->end; ++t)
40fb9820 3146 if (!t->opcode_modifier.isstring)
f41bbced
JB		 3147 break;
3148 override.end = t;
3149 current_templates = &override;
29b0f896 3150 }
252b5132 3151
29b0f896
AM		 3152 return l;
3153}
252b5132 3154
29b0f896 3155static char *
e3bb37b5 3156parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3157{
3158 char *token_start;
3138f287 3159
29b0f896
AM		 3160 /* 1 if operand is pending after ','. */
3161 unsigned int expecting_operand = 0;
252b5132 3162
29b0f896
AM		 3163 /* Non-zero if operand parens not balanced. */
3164 unsigned int paren_not_balanced;
3165
3166 while (*l != END_OF_INSN)
3167 {
3168 /* Skip optional white space before operand. */
3169 if (is_space_char (*l))
3170 ++l;
3171 if (!is_operand_char (*l) && *l != END_OF_INSN)
3172 {
3173 as_bad (_("invalid character %s before operand %d"),
3174 output_invalid (*l),
3175 i.operands + 1);
3176 return NULL;
3177 }
3178 token_start = l; /* after white space */
3179 paren_not_balanced = 0;
3180 while (paren_not_balanced || *l != ',')
3181 {
3182 if (*l == END_OF_INSN)
3183 {
3184 if (paren_not_balanced)
3185 {
3186 if (!intel_syntax)
3187 as_bad (_("unbalanced parenthesis in operand %d."),
3188 i.operands + 1);
3189 else
3190 as_bad (_("unbalanced brackets in operand %d."),
3191 i.operands + 1);
3192 return NULL;
3193 }
3194 else
3195 break; /* we are done */
3196 }
3197 else if (!is_operand_char (*l) && !is_space_char (*l))
3198 {
3199 as_bad (_("invalid character %s in operand %d"),
3200 output_invalid (*l),
3201 i.operands + 1);
3202 return NULL;
3203 }
3204 if (!intel_syntax)
3205 {
3206 if (*l == '(')
3207 ++paren_not_balanced;
3208 if (*l == ')')
3209 --paren_not_balanced;
3210 }
3211 else
3212 {
3213 if (*l == '[')
3214 ++paren_not_balanced;
3215 if (*l == ']')
3216 --paren_not_balanced;
3217 }
3218 l++;
3219 }
3220 if (l != token_start)
3221 { /* Yes, we've read in another operand. */
3222 unsigned int operand_ok;
3223 this_operand = i.operands++;
7d5e4556 3224 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3225 if (i.operands > MAX_OPERANDS)
3226 {
3227 as_bad (_("spurious operands; (%d operands/instruction max)"),
3228 MAX_OPERANDS);
3229 return NULL;
3230 }
3231 /* Now parse operand adding info to 'i' as we go along. */
3232 END_STRING_AND_SAVE (l);
3233
3234 if (intel_syntax)
3235 operand_ok =
3236 i386_intel_operand (token_start,
3237 intel_float_operand (mnemonic));
3238 else
a7619375 3239 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3240
3241 RESTORE_END_STRING (l);
3242 if (!operand_ok)
3243 return NULL;
3244 }
3245 else
3246 {
3247 if (expecting_operand)
3248 {
3249 expecting_operand_after_comma:
3250 as_bad (_("expecting operand after ','; got nothing"));
3251 return NULL;
3252 }
3253 if (*l == ',')
3254 {
3255 as_bad (_("expecting operand before ','; got nothing"));
3256 return NULL;
3257 }
3258 }
7f3f1ea2 3259
29b0f896
AM		 3260 /* Now *l must be either ',' or END_OF_INSN. */
3261 if (*l == ',')
3262 {
3263 if (*++l == END_OF_INSN)
3264 {
3265 /* Just skip it, if it's \n complain. */
3266 goto expecting_operand_after_comma;
3267 }
3268 expecting_operand = 1;
3269 }
3270 }
3271 return l;
3272}
7f3f1ea2 3273
050dfa73 3274static void
4d456e3d 3275swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3276{
3277 union i386_op temp_op;
40fb9820 3278 i386_operand_type temp_type;
050dfa73 3279 enum bfd_reloc_code_real temp_reloc;
4eed87de 3280
050dfa73
MM		 3281 temp_type = i.types[xchg2];
3282 i.types[xchg2] = i.types[xchg1];
3283 i.types[xchg1] = temp_type;
3284 temp_op = i.op[xchg2];
3285 i.op[xchg2] = i.op[xchg1];
3286 i.op[xchg1] = temp_op;
3287 temp_reloc = i.reloc[xchg2];
3288 i.reloc[xchg2] = i.reloc[xchg1];
3289 i.reloc[xchg1] = temp_reloc;
3290}
3291
29b0f896 3292static void
e3bb37b5 3293swap_operands (void)
29b0f896 3294{
b7c61d9a 3295 switch (i.operands)
050dfa73 3296 {
c0f3af97 3297 case 5:
b7c61d9a 3298 case 4:
4d456e3d 3299 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3300 case 3:
3301 case 2:
4d456e3d 3302 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3303 break;
3304 default:
3305 abort ();
29b0f896 3306 }
29b0f896
AM		 3307
3308 if (i.mem_operands == 2)
3309 {
3310 const seg_entry *temp_seg;
3311 temp_seg = i.seg[0];
3312 i.seg[0] = i.seg[1];
3313 i.seg[1] = temp_seg;
3314 }
3315}
252b5132 3316
29b0f896
AM		 3317/* Try to ensure constant immediates are represented in the smallest
3318 opcode possible. */
3319static void
e3bb37b5 3320optimize_imm (void)
29b0f896
AM		 3321{
3322 char guess_suffix = 0;
3323 int op;
252b5132 3324
29b0f896
AM		 3325 if (i.suffix)
3326 guess_suffix = i.suffix;
3327 else if (i.reg_operands)
3328 {
3329 /* Figure out a suffix from the last register operand specified.
3330 We can't do this properly yet, ie. excluding InOutPortReg,
3331 but the following works for instructions with immediates.
3332 In any case, we can't set i.suffix yet. */
3333 for (op = i.operands; --op >= 0;)
40fb9820 3334 if (i.types[op].bitfield.reg8)
7ab9ffdd 3335 {
40fb9820
L		 3336 guess_suffix = BYTE_MNEM_SUFFIX;
3337 break;
3338 }
3339 else if (i.types[op].bitfield.reg16)
252b5132 3340 {
40fb9820
L		 3341 guess_suffix = WORD_MNEM_SUFFIX;
3342 break;
3343 }
3344 else if (i.types[op].bitfield.reg32)
3345 {
3346 guess_suffix = LONG_MNEM_SUFFIX;
3347 break;
3348 }
3349 else if (i.types[op].bitfield.reg64)
3350 {
3351 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3352 break;
252b5132 3353 }
29b0f896
AM		 3354 }
3355 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3356 guess_suffix = WORD_MNEM_SUFFIX;
3357
3358 for (op = i.operands; --op >= 0;)
40fb9820 3359 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3360 {
3361 switch (i.op[op].imms->X_op)
252b5132 3362 {
29b0f896
AM		 3363 case O_constant:
3364 /* If a suffix is given, this operand may be shortened. */
3365 switch (guess_suffix)
252b5132 3366 {
29b0f896 3367 case LONG_MNEM_SUFFIX:
40fb9820
L		 3368 i.types[op].bitfield.imm32 = 1;
3369 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3370 break;
3371 case WORD_MNEM_SUFFIX:
40fb9820
L		 3372 i.types[op].bitfield.imm16 = 1;
3373 i.types[op].bitfield.imm32 = 1;
3374 i.types[op].bitfield.imm32s = 1;
3375 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3376 break;
3377 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3378 i.types[op].bitfield.imm8 = 1;
3379 i.types[op].bitfield.imm8s = 1;
3380 i.types[op].bitfield.imm16 = 1;
3381 i.types[op].bitfield.imm32 = 1;
3382 i.types[op].bitfield.imm32s = 1;
3383 i.types[op].bitfield.imm64 = 1;
29b0f896 3384 break;
252b5132 3385 }
252b5132 3386
29b0f896
AM		 3387 /* If this operand is at most 16 bits, convert it
3388 to a signed 16 bit number before trying to see
3389 whether it will fit in an even smaller size.
3390 This allows a 16-bit operand such as $0xffe0 to
3391 be recognised as within Imm8S range. */
40fb9820 3392 if ((i.types[op].bitfield.imm16)
29b0f896 3393 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3394 {
29b0f896
AM		 3395 i.op[op].imms->X_add_number =
3396 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3397 }
40fb9820 3398 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3399 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3400 == 0))
3401 {
3402 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3403 ^ ((offsetT) 1 << 31))
3404 - ((offsetT) 1 << 31));
3405 }
40fb9820 3406 i.types[op]
c6fb90c8
L		 3407 = operand_type_or (i.types[op],
3408 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3409
29b0f896
AM		 3410 /* We must avoid matching of Imm32 templates when 64bit
3411 only immediate is available. */
3412 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3413 i.types[op].bitfield.imm32 = 0;
29b0f896 3414 break;
252b5132 3415
29b0f896
AM		 3416 case O_absent:
3417 case O_register:
3418 abort ();
3419
3420 /* Symbols and expressions. */
3421 default:
9cd96992
JB		 3422 /* Convert symbolic operand to proper sizes for matching, but don't
3423 prevent matching a set of insns that only supports sizes other
3424 than those matching the insn suffix. */
3425 {
40fb9820 3426 i386_operand_type mask, allowed;
9cd96992
JB		 3427 const template *t;
3428
0dfbf9d7
L		 3429 operand_type_set (&mask, 0);
3430 operand_type_set (&allowed, 0);
40fb9820 3431
4eed87de
AM		 3432 for (t = current_templates->start;
3433 t < current_templates->end;
3434 ++t)
c6fb90c8
L		 3435 allowed = operand_type_or (allowed,
3436 t->operand_types[op]);
9cd96992
JB		 3437 switch (guess_suffix)
3438 {
3439 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3440 mask.bitfield.imm64 = 1;
3441 mask.bitfield.imm32s = 1;
9cd96992
JB		 3442 break;
3443 case LONG_MNEM_SUFFIX:
40fb9820 3444 mask.bitfield.imm32 = 1;
9cd96992
JB		 3445 break;
3446 case WORD_MNEM_SUFFIX:
40fb9820 3447 mask.bitfield.imm16 = 1;
9cd96992
JB		 3448 break;
3449 case BYTE_MNEM_SUFFIX:
40fb9820 3450 mask.bitfield.imm8 = 1;
9cd96992
JB		 3451 break;
3452 default:
9cd96992
JB		 3453 break;
3454 }
c6fb90c8 3455 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3456 if (!operand_type_all_zero (&allowed))
c6fb90c8 3457 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3458 }
29b0f896 3459 break;
252b5132 3460 }
29b0f896
AM		 3461 }
3462}
47926f60 3463
29b0f896
AM		 3464/* Try to use the smallest displacement type too. */
3465static void
e3bb37b5 3466optimize_disp (void)
29b0f896
AM		 3467{
3468 int op;
3e73aa7c 3469
29b0f896 3470 for (op = i.operands; --op >= 0;)
40fb9820 3471 if (operand_type_check (i.types[op], disp))
252b5132 3472 {
b300c311 3473 if (i.op[op].disps->X_op == O_constant)
252b5132 3474 {
b300c311 3475 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 3476
40fb9820 3477 if (i.types[op].bitfield.disp16
b300c311
L		 3478 && (disp & ~(offsetT) 0xffff) == 0)
3479 {
3480 /* If this operand is at most 16 bits, convert
3481 to a signed 16 bit number and don't use 64bit
3482 displacement. */
3483 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3484 i.types[op].bitfield.disp64 = 0;
b300c311 3485 }
40fb9820 3486 if (i.types[op].bitfield.disp32
b300c311
L		 3487 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
3488 {
3489 /* If this operand is at most 32 bits, convert
3490 to a signed 32 bit number and don't use 64bit
3491 displacement. */
3492 disp &= (((offsetT) 2 << 31) - 1);
3493 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3494 i.types[op].bitfield.disp64 = 0;
b300c311 3495 }
40fb9820 3496 if (!disp && i.types[op].bitfield.baseindex)
b300c311 3497 {
40fb9820
L		 3498 i.types[op].bitfield.disp8 = 0;
3499 i.types[op].bitfield.disp16 = 0;
3500 i.types[op].bitfield.disp32 = 0;
3501 i.types[op].bitfield.disp32s = 0;
3502 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3503 i.op[op].disps = 0;
3504 i.disp_operands--;
3505 }
3506 else if (flag_code == CODE_64BIT)
3507 {
3508 if (fits_in_signed_long (disp))
28a9d8f5 3509 {
40fb9820
L		 3510 i.types[op].bitfield.disp64 = 0;
3511 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3512 }
b300c311 3513 if (fits_in_unsigned_long (disp))
40fb9820 3514 i.types[op].bitfield.disp32 = 1;
b300c311 3515 }
40fb9820
L		 3516 if ((i.types[op].bitfield.disp32
3517 || i.types[op].bitfield.disp32s
3518 || i.types[op].bitfield.disp16)
b300c311 3519 && fits_in_signed_byte (disp))
40fb9820 3520 i.types[op].bitfield.disp8 = 1;
252b5132 3521 }
67a4f2b7
AO		 3522 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3523 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3524 {
3525 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3526 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3527 i.types[op].bitfield.disp8 = 0;
3528 i.types[op].bitfield.disp16 = 0;
3529 i.types[op].bitfield.disp32 = 0;
3530 i.types[op].bitfield.disp32s = 0;
3531 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3532 }
3533 else
b300c311 3534 /* We only support 64bit displacement on constants. */
40fb9820 3535 i.types[op].bitfield.disp64 = 0;
252b5132 3536 }
29b0f896
AM		 3537}
3538
fa99fab2 3539static const template *
e3bb37b5 3540match_template (void)
29b0f896
AM		 3541{
3542 /* Points to template once we've found it. */
3543 const template *t;
40fb9820 3544 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 3545 i386_operand_type overlap4;
29b0f896 3546 unsigned int found_reverse_match;
40fb9820
L		 3547 i386_opcode_modifier suffix_check;
3548 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3549 int addr_prefix_disp;
a5c311ca 3550 unsigned int j;
3629bb00 3551 unsigned int found_cpu_match;
45664ddb 3552 unsigned int check_register;
29b0f896 3553
c0f3af97
L		 3554#if MAX_OPERANDS != 5
3555# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 3556#endif
3557
29b0f896 3558 found_reverse_match = 0;
539e75ad 3559 addr_prefix_disp = -1;
40fb9820
L		 3560
3561 memset (&suffix_check, 0, sizeof (suffix_check));
3562 if (i.suffix == BYTE_MNEM_SUFFIX)
3563 suffix_check.no_bsuf = 1;
3564 else if (i.suffix == WORD_MNEM_SUFFIX)
3565 suffix_check.no_wsuf = 1;
3566 else if (i.suffix == SHORT_MNEM_SUFFIX)
3567 suffix_check.no_ssuf = 1;
3568 else if (i.suffix == LONG_MNEM_SUFFIX)
3569 suffix_check.no_lsuf = 1;
3570 else if (i.suffix == QWORD_MNEM_SUFFIX)
3571 suffix_check.no_qsuf = 1;
3572 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3573 suffix_check.no_ldsuf = 1;
29b0f896 3574
45aa61fe 3575 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3576 {
539e75ad
L		 3577 addr_prefix_disp = -1;
3578
29b0f896
AM		 3579 /* Must have right number of operands. */
3580 if (i.operands != t->operands)
3581 continue;
3582
50aecf8c 3583 /* Check processor support. */
c0f3af97
L		 3584 found_cpu_match = (cpu_flags_match (t)
3585 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 3586 if (!found_cpu_match)
3587 continue;
3588
e1d4d893
L		 3589 /* Check old gcc support. */
3590 if (!old_gcc && t->opcode_modifier.oldgcc)
3591 continue;
3592
3593 /* Check AT&T mnemonic. */
3594 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3595 continue;
3596
5c07affc
L		 3597 /* Check AT&T syntax Intel syntax. */
3598 if ((intel_syntax && t->opcode_modifier.attsyntax)
3599 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3600 continue;
3601
20592a94 3602 /* Check the suffix, except for some instructions in intel mode. */
567e4e96
L		 3603 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3604 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3605 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3606 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3607 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3608 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3609 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3610 continue;
3611
5c07affc 3612 if (!operand_size_match (t))
7d5e4556 3613 continue;
539e75ad 3614
5c07affc
L		 3615 for (j = 0; j < MAX_OPERANDS; j++)
3616 operand_types[j] = t->operand_types[j];
3617
45aa61fe
AM		 3618 /* In general, don't allow 64-bit operands in 32-bit mode. */
3619 if (i.suffix == QWORD_MNEM_SUFFIX
3620 && flag_code != CODE_64BIT
3621 && (intel_syntax
40fb9820 3622 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3623 && !intel_float_operand (t->name))
3624 : intel_float_operand (t->name) != 2)
40fb9820 3625 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 3626 && !operand_types[0].bitfield.regxmm
3627 && !operand_types[0].bitfield.regymm)
40fb9820 3628 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 3629 && !!operand_types[t->operands > 1].bitfield.regxmm
3630 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 3631 && (t->base_opcode != 0x0fc7
3632 || t->extension_opcode != 1 /* cmpxchg8b */))
3633 continue;
3634
192dc9c6
JB		 3635 /* In general, don't allow 32-bit operands on pre-386. */
3636 else if (i.suffix == LONG_MNEM_SUFFIX
3637 && !cpu_arch_flags.bitfield.cpui386
3638 && (intel_syntax
3639 ? (!t->opcode_modifier.ignoresize
3640 && !intel_float_operand (t->name))
3641 : intel_float_operand (t->name) != 2)
3642 && ((!operand_types[0].bitfield.regmmx
3643 && !operand_types[0].bitfield.regxmm)
3644 || (!operand_types[t->operands > 1].bitfield.regmmx
3645 && !!operand_types[t->operands > 1].bitfield.regxmm)))
3646 continue;
3647
29b0f896 3648 /* Do not verify operands when there are none. */
50aecf8c 3649 else
29b0f896 3650 {
c6fb90c8 3651 if (!t->operands)
2dbab7d5
L		 3652 /* We've found a match; break out of loop. */
3653 break;
29b0f896 3654 }
252b5132 3655
539e75ad
L		 3656 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3657 into Disp32/Disp16/Disp32 operand. */
3658 if (i.prefix[ADDR_PREFIX] != 0)
3659 {
40fb9820 3660 /* There should be only one Disp operand. */
539e75ad
L		 3661 switch (flag_code)
3662 {
3663 case CODE_16BIT:
40fb9820
L		 3664 for (j = 0; j < MAX_OPERANDS; j++)
3665 {
3666 if (operand_types[j].bitfield.disp16)
3667 {
3668 addr_prefix_disp = j;
3669 operand_types[j].bitfield.disp32 = 1;
3670 operand_types[j].bitfield.disp16 = 0;
3671 break;
3672 }
3673 }
539e75ad
L		 3674 break;
3675 case CODE_32BIT:
40fb9820
L		 3676 for (j = 0; j < MAX_OPERANDS; j++)
3677 {
3678 if (operand_types[j].bitfield.disp32)
3679 {
3680 addr_prefix_disp = j;
3681 operand_types[j].bitfield.disp32 = 0;
3682 operand_types[j].bitfield.disp16 = 1;
3683 break;
3684 }
3685 }
539e75ad
L		 3686 break;
3687 case CODE_64BIT:
40fb9820
L		 3688 for (j = 0; j < MAX_OPERANDS; j++)
3689 {
3690 if (operand_types[j].bitfield.disp64)
3691 {
3692 addr_prefix_disp = j;
3693 operand_types[j].bitfield.disp64 = 0;
3694 operand_types[j].bitfield.disp32 = 1;
3695 break;
3696 }
3697 }
539e75ad
L		 3698 break;
3699 }
539e75ad
L		 3700 }
3701
45664ddb
L		 3702 /* We check register size only if size of operands can be
3703 encoded the canonical way. */
3704 check_register = t->opcode_modifier.w;
c6fb90c8 3705 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3706 switch (t->operands)
3707 {
3708 case 1:
40fb9820 3709 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3710 continue;
3711 break;
3712 case 2:
8b38ad71
L		 3713 /* xchg %eax, %eax is a special case. It is an aliase for nop
3714 only in 32bit mode and we can use opcode 0x90. In 64bit
3715 mode, we can't use 0x90 for xchg %eax, %eax since it should
3716 zero-extend %eax to %rax. */
3717 if (flag_code == CODE_64BIT
3718 && t->base_opcode == 0x90
0dfbf9d7
L		 3719 && operand_type_equal (&i.types [0], &acc32)
3720 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 3721 continue;
b6169b20
L		 3722 if (i.swap_operand)
3723 {
3724 /* If we swap operand in encoding, we either match
3725 the next one or reverse direction of operands. */
3726 if (t->opcode_modifier.s)
3727 continue;
3728 else if (t->opcode_modifier.d)
3729 goto check_reverse;
3730 }
3731
29b0f896 3732 case 3:
fa99fab2
L		 3733 /* If we swap operand in encoding, we match the next one. */
3734 if (i.swap_operand && t->opcode_modifier.s)
3735 continue;
f48ff2ae 3736 case 4:
c0f3af97 3737 case 5:
c6fb90c8 3738 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 3739 if (!operand_type_match (overlap0, i.types[0])
3740 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3741 || (check_register
3742 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 3743 operand_types[0],
3744 overlap1, i.types[1],
3745 operand_types[1])))
29b0f896
AM		 3746 {
3747 /* Check if other direction is valid ... */
40fb9820 3748 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 3749 continue;
3750
b6169b20 3751check_reverse:
29b0f896 3752 /* Try reversing direction of operands. */
c6fb90c8
L		 3753 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3754 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 3755 if (!operand_type_match (overlap0, i.types[0])
3756 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3757 || (check_register
3758 && !operand_type_register_match (overlap0,
3759 i.types[0],
3760 operand_types[1],
3761 overlap1,
3762 i.types[1],
3763 operand_types[0])))
29b0f896
AM		 3764 {
3765 /* Does not match either direction. */
3766 continue;
3767 }
3768 /* found_reverse_match holds which of D or FloatDR
3769 we've found. */
40fb9820 3770 if (t->opcode_modifier.d)
8a2ed489 3771 found_reverse_match = Opcode_D;
40fb9820 3772 else if (t->opcode_modifier.floatd)
8a2ed489
L		 3773 found_reverse_match = Opcode_FloatD;
3774 else
3775 found_reverse_match = 0;
40fb9820 3776 if (t->opcode_modifier.floatr)
8a2ed489 3777 found_reverse_match |= Opcode_FloatR;
29b0f896 3778 }
f48ff2ae 3779 else
29b0f896 3780 {
f48ff2ae 3781 /* Found a forward 2 operand match here. */
d1cbb4db
L		 3782 switch (t->operands)
3783 {
c0f3af97
L		 3784 case 5:
3785 overlap4 = operand_type_and (i.types[4],
3786 operand_types[4]);
d1cbb4db 3787 case 4:
c6fb90c8
L		 3788 overlap3 = operand_type_and (i.types[3],
3789 operand_types[3]);
d1cbb4db 3790 case 3:
c6fb90c8
L		 3791 overlap2 = operand_type_and (i.types[2],
3792 operand_types[2]);
d1cbb4db
L		 3793 break;
3794 }
29b0f896 3795
f48ff2ae
L		 3796 switch (t->operands)
3797 {
c0f3af97
L		 3798 case 5:
3799 if (!operand_type_match (overlap4, i.types[4])
3800 || !operand_type_register_match (overlap3,
3801 i.types[3],
3802 operand_types[3],
3803 overlap4,
3804 i.types[4],
3805 operand_types[4]))
3806 continue;
f48ff2ae 3807 case 4:
40fb9820 3808 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 3809 || (check_register
3810 && !operand_type_register_match (overlap2,
3811 i.types[2],
3812 operand_types[2],
3813 overlap3,
3814 i.types[3],
3815 operand_types[3])))
f48ff2ae
L		 3816 continue;
3817 case 3:
3818 /* Here we make use of the fact that there are no
3819 reverse match 3 operand instructions, and all 3
3820 operand instructions only need to be checked for
3821 register consistency between operands 2 and 3. */
40fb9820 3822 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 3823 || (check_register
3824 && !operand_type_register_match (overlap1,
3825 i.types[1],
3826 operand_types[1],
3827 overlap2,
3828 i.types[2],
3829 operand_types[2])))
f48ff2ae
L		 3830 continue;
3831 break;
3832 }
29b0f896 3833 }
f48ff2ae 3834 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 3835 slip through to break. */
3836 }
3629bb00 3837 if (!found_cpu_match)
29b0f896
AM		 3838 {
3839 found_reverse_match = 0;
3840 continue;
3841 }
c0f3af97 3842
29b0f896
AM		 3843 /* We've found a match; break out of loop. */
3844 break;
3845 }
3846
3847 if (t == current_templates->end)
3848 {
3849 /* We found no match. */
95f283e8
L		 3850 if (intel_syntax)
3851 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
3852 current_templates->start->name);
3853 else
3854 as_bad (_("suffix or operands invalid for `%s'"),
3855 current_templates->start->name);
fa99fab2 3856 return NULL;
29b0f896 3857 }
252b5132 3858
29b0f896
AM		 3859 if (!quiet_warnings)
3860 {
3861 if (!intel_syntax
40fb9820
L		 3862 && (i.types[0].bitfield.jumpabsolute
3863 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 3864 {
3865 as_warn (_("indirect %s without `*'"), t->name);
3866 }
3867
40fb9820
L		 3868 if (t->opcode_modifier.isprefix
3869 && t->opcode_modifier.ignoresize)
29b0f896
AM		 3870 {
3871 /* Warn them that a data or address size prefix doesn't
3872 affect assembly of the next line of code. */
3873 as_warn (_("stand-alone `%s' prefix"), t->name);
3874 }
3875 }
3876
3877 /* Copy the template we found. */
3878 i.tm = *t;
539e75ad
L		 3879
3880 if (addr_prefix_disp != -1)
3881 i.tm.operand_types[addr_prefix_disp]
3882 = operand_types[addr_prefix_disp];
3883
29b0f896
AM		 3884 if (found_reverse_match)
3885 {
3886 /* If we found a reverse match we must alter the opcode
3887 direction bit. found_reverse_match holds bits to change
3888 (different for int & float insns). */
3889
3890 i.tm.base_opcode ^= found_reverse_match;
3891
539e75ad
L		 3892 i.tm.operand_types[0] = operand_types[1];
3893 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 3894 }
3895
fa99fab2 3896 return t;
29b0f896
AM		 3897}
3898
3899static int
e3bb37b5 3900check_string (void)
29b0f896 3901{
40fb9820
L		 3902 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3903 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 3904 {
3905 if (i.seg[0] != NULL && i.seg[0] != &es)
3906 {
a87af027 3907 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 3908 i.tm.name,
a87af027
JB		 3909 mem_op + 1,
3910 register_prefix);
29b0f896
AM		 3911 return 0;
3912 }
3913 /* There's only ever one segment override allowed per instruction.
3914 This instruction possibly has a legal segment override on the
3915 second operand, so copy the segment to where non-string
3916 instructions store it, allowing common code. */
3917 i.seg[0] = i.seg[1];
3918 }
40fb9820 3919 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 3920 {
3921 if (i.seg[1] != NULL && i.seg[1] != &es)
3922 {
a87af027 3923 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 3924 i.tm.name,
a87af027
JB		 3925 mem_op + 2,
3926 register_prefix);
29b0f896
AM		 3927 return 0;
3928 }
3929 }
3930 return 1;
3931}
3932
3933static int
543613e9 3934process_suffix (void)
29b0f896
AM		 3935{
3936 /* If matched instruction specifies an explicit instruction mnemonic
3937 suffix, use it. */
40fb9820
L		 3938 if (i.tm.opcode_modifier.size16)
3939 i.suffix = WORD_MNEM_SUFFIX;
3940 else if (i.tm.opcode_modifier.size32)
3941 i.suffix = LONG_MNEM_SUFFIX;
3942 else if (i.tm.opcode_modifier.size64)
3943 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 3944 else if (i.reg_operands)
3945 {
3946 /* If there's no instruction mnemonic suffix we try to invent one
3947 based on register operands. */
3948 if (!i.suffix)
3949 {
3950 /* We take i.suffix from the last register operand specified,
3951 Destination register type is more significant than source
381d071f
L		 3952 register type. crc32 in SSE4.2 prefers source register
3953 type. */
3954 if (i.tm.base_opcode == 0xf20f38f1)
3955 {
40fb9820
L		 3956 if (i.types[0].bitfield.reg16)
3957 i.suffix = WORD_MNEM_SUFFIX;
3958 else if (i.types[0].bitfield.reg32)
3959 i.suffix = LONG_MNEM_SUFFIX;
3960 else if (i.types[0].bitfield.reg64)
3961 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 3962 }
9344ff29 3963 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 3964 {
40fb9820 3965 if (i.types[0].bitfield.reg8)
20592a94
L		 3966 i.suffix = BYTE_MNEM_SUFFIX;
3967 }
381d071f
L		 3968
3969 if (!i.suffix)
3970 {
3971 int op;
3972
20592a94
L		 3973 if (i.tm.base_opcode == 0xf20f38f1
3974 || i.tm.base_opcode == 0xf20f38f0)
3975 {
3976 /* We have to know the operand size for crc32. */
3977 as_bad (_("ambiguous memory operand size for `%s`"),
3978 i.tm.name);
3979 return 0;
3980 }
3981
381d071f 3982 for (op = i.operands; --op >= 0;)
40fb9820 3983 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 3984 {
40fb9820
L		 3985 if (i.types[op].bitfield.reg8)
3986 {
3987 i.suffix = BYTE_MNEM_SUFFIX;
3988 break;
3989 }
3990 else if (i.types[op].bitfield.reg16)
3991 {
3992 i.suffix = WORD_MNEM_SUFFIX;
3993 break;
3994 }
3995 else if (i.types[op].bitfield.reg32)
3996 {
3997 i.suffix = LONG_MNEM_SUFFIX;
3998 break;
3999 }
4000 else if (i.types[op].bitfield.reg64)
4001 {
4002 i.suffix = QWORD_MNEM_SUFFIX;
4003 break;
4004 }
381d071f
L		 4005 }
4006 }
29b0f896
AM		 4007 }
4008 else if (i.suffix == BYTE_MNEM_SUFFIX)
4009 {
4010 if (!check_byte_reg ())
4011 return 0;
4012 }
4013 else if (i.suffix == LONG_MNEM_SUFFIX)
4014 {
4015 if (!check_long_reg ())
4016 return 0;
4017 }
4018 else if (i.suffix == QWORD_MNEM_SUFFIX)
4019 {
955e1e6a
L		 4020 if (intel_syntax
4021 && i.tm.opcode_modifier.ignoresize
4022 && i.tm.opcode_modifier.no_qsuf)
4023 i.suffix = 0;
4024 else if (!check_qword_reg ())
29b0f896
AM		 4025 return 0;
4026 }
4027 else if (i.suffix == WORD_MNEM_SUFFIX)
4028 {
4029 if (!check_word_reg ())
4030 return 0;
4031 }
c0f3af97
L		 4032 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4033 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 4034 {
c0f3af97 4035 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 4036 should check if it is a valid suffix. */
4037 }
40fb9820 4038 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 4039 /* Do nothing if the instruction is going to ignore the prefix. */
4040 ;
4041 else
4042 abort ();
4043 }
40fb9820 4044 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 4045 && !i.suffix
4046 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 4047 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 4048 {
4049 i.suffix = stackop_size;
4050 }
9306ca4a
JB		 4051 else if (intel_syntax
4052 && !i.suffix
40fb9820
L		 4053 && (i.tm.operand_types[0].bitfield.jumpabsolute
4054 || i.tm.opcode_modifier.jumpbyte
4055 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 4056 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4057 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 4058 {
4059 switch (flag_code)
4060 {
4061 case CODE_64BIT:
40fb9820 4062 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 4063 {
4064 i.suffix = QWORD_MNEM_SUFFIX;
4065 break;
4066 }
4067 case CODE_32BIT:
40fb9820 4068 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 4069 i.suffix = LONG_MNEM_SUFFIX;
4070 break;
4071 case CODE_16BIT:
40fb9820 4072 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 4073 i.suffix = WORD_MNEM_SUFFIX;
4074 break;
4075 }
4076 }
252b5132 4077
9306ca4a 4078 if (!i.suffix)
29b0f896 4079 {
9306ca4a
JB		 4080 if (!intel_syntax)
4081 {
40fb9820 4082 if (i.tm.opcode_modifier.w)
9306ca4a 4083 {
4eed87de
AM		 4084 as_bad (_("no instruction mnemonic suffix given and "
4085 "no register operands; can't size instruction"));
9306ca4a
JB		 4086 return 0;
4087 }
4088 }
4089 else
4090 {
40fb9820 4091 unsigned int suffixes;
7ab9ffdd 4092
40fb9820
L		 4093 suffixes = !i.tm.opcode_modifier.no_bsuf;
4094 if (!i.tm.opcode_modifier.no_wsuf)
4095 suffixes |= 1 << 1;
4096 if (!i.tm.opcode_modifier.no_lsuf)
4097 suffixes |= 1 << 2;
fc4adea1 4098 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 4099 suffixes |= 1 << 3;
4100 if (!i.tm.opcode_modifier.no_ssuf)
4101 suffixes |= 1 << 4;
4102 if (!i.tm.opcode_modifier.no_qsuf)
4103 suffixes |= 1 << 5;
4104
4105 /* There are more than suffix matches. */
4106 if (i.tm.opcode_modifier.w
9306ca4a 4107 || ((suffixes & (suffixes - 1))
40fb9820
L		 4108 && !i.tm.opcode_modifier.defaultsize
4109 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 4110 {
4111 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4112 return 0;
4113 }
4114 }
29b0f896 4115 }
252b5132 4116
9306ca4a
JB		 4117 /* Change the opcode based on the operand size given by i.suffix;
4118 We don't need to change things for byte insns. */
4119
582d5edd
L		 4120 if (i.suffix
4121 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 4122 && i.suffix != XMMWORD_MNEM_SUFFIX
4123 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 4124 {
4125 /* It's not a byte, select word/dword operation. */
40fb9820 4126 if (i.tm.opcode_modifier.w)
29b0f896 4127 {
40fb9820 4128 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4129 i.tm.base_opcode |= 8;
4130 else
4131 i.tm.base_opcode |= 1;
4132 }
0f3f3d8b 4133
29b0f896
AM		 4134 /* Now select between word & dword operations via the operand
4135 size prefix, except for instructions that will ignore this
4136 prefix anyway. */
ca61edf2 4137 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4138 {
ca61edf2
L		 4139 /* The address size override prefix changes the size of the
4140 first operand. */
40fb9820
L		 4141 if ((flag_code == CODE_32BIT
4142 && i.op->regs[0].reg_type.bitfield.reg16)
4143 || (flag_code != CODE_32BIT
4144 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4145 if (!add_prefix (ADDR_PREFIX_OPCODE))
4146 return 0;
4147 }
4148 else if (i.suffix != QWORD_MNEM_SUFFIX
4149 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4150 && !i.tm.opcode_modifier.ignoresize
4151 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4152 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4153 || (flag_code == CODE_64BIT
40fb9820 4154 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4155 {
4156 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4157
40fb9820 4158 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4159 prefix = ADDR_PREFIX_OPCODE;
252b5132 4160
29b0f896
AM		 4161 if (!add_prefix (prefix))
4162 return 0;
24eab124 4163 }
252b5132 4164
29b0f896
AM		 4165 /* Set mode64 for an operand. */
4166 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4167 && flag_code == CODE_64BIT
40fb9820 4168 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4169 {
4170 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4171 need rex64. cmpxchg8b is also a special case. */
4172 if (! (i.operands == 2
4173 && i.tm.base_opcode == 0x90
4174 && i.tm.extension_opcode == None
0dfbf9d7
L		 4175 && operand_type_equal (&i.types [0], &acc64)
4176 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4177 && ! (i.operands == 1
4178 && i.tm.base_opcode == 0xfc7
4179 && i.tm.extension_opcode == 1
40fb9820
L		 4180 && !operand_type_check (i.types [0], reg)
4181 && operand_type_check (i.types [0], anymem)))
f6bee062 4182 i.rex |= REX_W;
46e883c5 4183 }
3e73aa7c 4184
29b0f896
AM		 4185 /* Size floating point instruction. */
4186 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4187 if (i.tm.opcode_modifier.floatmf)
543613e9 4188 i.tm.base_opcode ^= 4;
29b0f896 4189 }
7ecd2f8b 4190
29b0f896
AM		 4191 return 1;
4192}
3e73aa7c 4193
29b0f896 4194static int
543613e9 4195check_byte_reg (void)
29b0f896
AM		 4196{
4197 int op;
543613e9 4198
29b0f896
AM		 4199 for (op = i.operands; --op >= 0;)
4200 {
4201 /* If this is an eight bit register, it's OK. If it's the 16 or
4202 32 bit version of an eight bit register, we will just use the
4203 low portion, and that's OK too. */
40fb9820 4204 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4205 continue;
4206
ca61edf2
L		 4207 /* Don't generate this warning if not needed. */
4208 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
29b0f896
AM		 4209 continue;
4210
9344ff29
L		 4211 /* crc32 doesn't generate this warning. */
4212 if (i.tm.base_opcode == 0xf20f38f0)
4213 continue;
4214
40fb9820
L		 4215 if ((i.types[op].bitfield.reg16
4216 || i.types[op].bitfield.reg32
4217 || i.types[op].bitfield.reg64)
4218 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 4219 {
4220 /* Prohibit these changes in the 64bit mode, since the
4221 lowering is more complicated. */
4222 if (flag_code == CODE_64BIT
40fb9820 4223 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 4224 {
2ca3ace5
L		 4225 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4226 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4227 i.suffix);
4228 return 0;
4229 }
4230#if REGISTER_WARNINGS
4231 if (!quiet_warnings
40fb9820 4232 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 4233 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4234 register_prefix,
40fb9820 4235 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4236 ? REGNAM_AL - REGNAM_AX
4237 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4238 register_prefix,
29b0f896
AM		 4239 i.op[op].regs->reg_name,
4240 i.suffix);
4241#endif
4242 continue;
4243 }
4244 /* Any other register is bad. */
40fb9820
L		 4245 if (i.types[op].bitfield.reg16
4246 || i.types[op].bitfield.reg32
4247 || i.types[op].bitfield.reg64
4248 || i.types[op].bitfield.regmmx
4249 || i.types[op].bitfield.regxmm
c0f3af97 4250 || i.types[op].bitfield.regymm
40fb9820
L		 4251 || i.types[op].bitfield.sreg2
4252 || i.types[op].bitfield.sreg3
4253 || i.types[op].bitfield.control
4254 || i.types[op].bitfield.debug
4255 || i.types[op].bitfield.test
4256 || i.types[op].bitfield.floatreg
4257 || i.types[op].bitfield.floatacc)
29b0f896 4258 {
a540244d
L		 4259 as_bad (_("`%s%s' not allowed with `%s%c'"),
4260 register_prefix,
29b0f896
AM		 4261 i.op[op].regs->reg_name,
4262 i.tm.name,
4263 i.suffix);
4264 return 0;
4265 }
4266 }
4267 return 1;
4268}
4269
4270static int
e3bb37b5 4271check_long_reg (void)
29b0f896
AM		 4272{
4273 int op;
4274
4275 for (op = i.operands; --op >= 0;)
4276 /* Reject eight bit registers, except where the template requires
4277 them. (eg. movzb) */
40fb9820
L		 4278 if (i.types[op].bitfield.reg8
4279 && (i.tm.operand_types[op].bitfield.reg16
4280 || i.tm.operand_types[op].bitfield.reg32
4281 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4282 {
a540244d
L		 4283 as_bad (_("`%s%s' not allowed with `%s%c'"),
4284 register_prefix,
29b0f896
AM		 4285 i.op[op].regs->reg_name,
4286 i.tm.name,
4287 i.suffix);
4288 return 0;
4289 }
4290 /* Warn if the e prefix on a general reg is missing. */
4291 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4292 && i.types[op].bitfield.reg16
4293 && (i.tm.operand_types[op].bitfield.reg32
4294 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4295 {
4296 /* Prohibit these changes in the 64bit mode, since the
4297 lowering is more complicated. */
4298 if (flag_code == CODE_64BIT)
252b5132 4299 {
2ca3ace5
L		 4300 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4301 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4302 i.suffix);
4303 return 0;
252b5132 4304 }
29b0f896
AM		 4305#if REGISTER_WARNINGS
4306 else
a540244d
L		 4307 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4308 register_prefix,
29b0f896 4309 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4310 register_prefix,
29b0f896
AM		 4311 i.op[op].regs->reg_name,
4312 i.suffix);
4313#endif
252b5132 4314 }
29b0f896 4315 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4316 else if (i.types[op].bitfield.reg64
4317 && (i.tm.operand_types[op].bitfield.reg32
4318 || i.tm.operand_types[op].bitfield.acc))
252b5132 4319 {
34828aad 4320 if (intel_syntax
ca61edf2 4321 && i.tm.opcode_modifier.toqword
40fb9820 4322 && !i.types[0].bitfield.regxmm)
34828aad 4323 {
ca61edf2 4324 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4325 i.suffix = QWORD_MNEM_SUFFIX;
4326 }
4327 else
4328 {
4329 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4330 register_prefix, i.op[op].regs->reg_name,
4331 i.suffix);
4332 return 0;
4333 }
29b0f896
AM		 4334 }
4335 return 1;
4336}
252b5132 4337
29b0f896 4338static int
e3bb37b5 4339check_qword_reg (void)
29b0f896
AM		 4340{
4341 int op;
252b5132 4342
29b0f896
AM		 4343 for (op = i.operands; --op >= 0; )
4344 /* Reject eight bit registers, except where the template requires
4345 them. (eg. movzb) */
40fb9820
L		 4346 if (i.types[op].bitfield.reg8
4347 && (i.tm.operand_types[op].bitfield.reg16
4348 || i.tm.operand_types[op].bitfield.reg32
4349 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4350 {
a540244d
L		 4351 as_bad (_("`%s%s' not allowed with `%s%c'"),
4352 register_prefix,
29b0f896
AM		 4353 i.op[op].regs->reg_name,
4354 i.tm.name,
4355 i.suffix);
4356 return 0;
4357 }
4358 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4359 else if ((i.types[op].bitfield.reg16
4360 || i.types[op].bitfield.reg32)
4361 && (i.tm.operand_types[op].bitfield.reg32
4362 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4363 {
4364 /* Prohibit these changes in the 64bit mode, since the
4365 lowering is more complicated. */
34828aad 4366 if (intel_syntax
ca61edf2 4367 && i.tm.opcode_modifier.todword
40fb9820 4368 && !i.types[0].bitfield.regxmm)
34828aad 4369 {
ca61edf2 4370 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4371 i.suffix = LONG_MNEM_SUFFIX;
4372 }
4373 else
4374 {
4375 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4376 register_prefix, i.op[op].regs->reg_name,
4377 i.suffix);
4378 return 0;
4379 }
252b5132 4380 }
29b0f896
AM		 4381 return 1;
4382}
252b5132 4383
29b0f896 4384static int
e3bb37b5 4385check_word_reg (void)
29b0f896
AM		 4386{
4387 int op;
4388 for (op = i.operands; --op >= 0;)
4389 /* Reject eight bit registers, except where the template requires
4390 them. (eg. movzb) */
40fb9820
L		 4391 if (i.types[op].bitfield.reg8
4392 && (i.tm.operand_types[op].bitfield.reg16
4393 || i.tm.operand_types[op].bitfield.reg32
4394 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4395 {
a540244d
L		 4396 as_bad (_("`%s%s' not allowed with `%s%c'"),
4397 register_prefix,
29b0f896
AM		 4398 i.op[op].regs->reg_name,
4399 i.tm.name,
4400 i.suffix);
4401 return 0;
4402 }
4403 /* Warn if the e prefix on a general reg is present. */
4404 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4405 && i.types[op].bitfield.reg32
4406 && (i.tm.operand_types[op].bitfield.reg16
4407 || i.tm.operand_types[op].bitfield.acc))
252b5132 4408 {
29b0f896
AM		 4409 /* Prohibit these changes in the 64bit mode, since the
4410 lowering is more complicated. */
4411 if (flag_code == CODE_64BIT)
252b5132 4412 {
2ca3ace5
L		 4413 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4414 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4415 i.suffix);
4416 return 0;
252b5132 4417 }
29b0f896
AM		 4418 else
4419#if REGISTER_WARNINGS
a540244d
L		 4420 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4421 register_prefix,
29b0f896 4422 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4423 register_prefix,
29b0f896
AM		 4424 i.op[op].regs->reg_name,
4425 i.suffix);
4426#endif
4427 }
4428 return 1;
4429}
252b5132 4430
29b0f896 4431static int
40fb9820 4432update_imm (unsigned int j)
29b0f896 4433{
40fb9820
L		 4434 i386_operand_type overlap;
4435
c6fb90c8 4436 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
40fb9820
L		 4437 if ((overlap.bitfield.imm8
4438 || overlap.bitfield.imm8s
4439 || overlap.bitfield.imm16
4440 || overlap.bitfield.imm32
4441 || overlap.bitfield.imm32s
4442 || overlap.bitfield.imm64)
0dfbf9d7
L		 4443 && !operand_type_equal (&overlap, &imm8)
4444 && !operand_type_equal (&overlap, &imm8s)
4445 && !operand_type_equal (&overlap, &imm16)
4446 && !operand_type_equal (&overlap, &imm32)
4447 && !operand_type_equal (&overlap, &imm32s)
4448 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 4449 {
4450 if (i.suffix)
4451 {
40fb9820
L		 4452 i386_operand_type temp;
4453
0dfbf9d7 4454 operand_type_set (&temp, 0);
7ab9ffdd 4455 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 4456 {
4457 temp.bitfield.imm8 = overlap.bitfield.imm8;
4458 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4459 }
4460 else if (i.suffix == WORD_MNEM_SUFFIX)
4461 temp.bitfield.imm16 = overlap.bitfield.imm16;
4462 else if (i.suffix == QWORD_MNEM_SUFFIX)
4463 {
4464 temp.bitfield.imm64 = overlap.bitfield.imm64;
4465 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4466 }
4467 else
4468 temp.bitfield.imm32 = overlap.bitfield.imm32;
4469 overlap = temp;
29b0f896 4470 }
0dfbf9d7
L		 4471 else if (operand_type_equal (&overlap, &imm16_32_32s)
4472 || operand_type_equal (&overlap, &imm16_32)
4473 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 4474 {
40fb9820 4475 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 4476 overlap = imm16;
40fb9820 4477 else
65da13b5 4478 overlap = imm32s;
29b0f896 4479 }
0dfbf9d7
L		 4480 if (!operand_type_equal (&overlap, &imm8)
4481 && !operand_type_equal (&overlap, &imm8s)
4482 && !operand_type_equal (&overlap, &imm16)
4483 && !operand_type_equal (&overlap, &imm32)
4484 && !operand_type_equal (&overlap, &imm32s)
4485 && !operand_type_equal (&overlap, &imm64))
29b0f896 4486 {
4eed87de
AM		 4487 as_bad (_("no instruction mnemonic suffix given; "
4488 "can't determine immediate size"));
29b0f896
AM		 4489 return 0;
4490 }
4491 }
40fb9820 4492 i.types[j] = overlap;
29b0f896 4493
40fb9820
L		 4494 return 1;
4495}
4496
4497static int
4498finalize_imm (void)
4499{
4500 unsigned int j;
29b0f896 4501
40fb9820
L		 4502 for (j = 0; j < 2; j++)
4503 if (update_imm (j) == 0)
4504 return 0;
4505
c6fb90c8 4506 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
9c2799c2 4507 gas_assert (operand_type_check (i.types[2], imm) == 0);
29b0f896
AM		 4508
4509 return 1;
4510}
4511
c0f3af97
L		 4512static int
4513bad_implicit_operand (int xmm)
4514{
4515 const char *reg = xmm ? "xmm0" : "ymm0";
4516 if (intel_syntax)
4517 as_bad (_("the last operand of `%s' must be `%s%s'"),
4518 i.tm.name, register_prefix, reg);
4519 else
4520 as_bad (_("the first operand of `%s' must be `%s%s'"),
4521 i.tm.name, register_prefix, reg);
4522 return 0;
4523}
4524
29b0f896 4525static int
e3bb37b5 4526process_operands (void)
29b0f896
AM		 4527{
4528 /* Default segment register this instruction will use for memory
4529 accesses. 0 means unknown. This is only for optimizing out
4530 unnecessary segment overrides. */
4531 const seg_entry *default_seg = 0;
4532
c0f3af97
L		 4533 if (i.tm.opcode_modifier.sse2avx
4534 && (i.tm.opcode_modifier.vexnds
4535 || i.tm.opcode_modifier.vexndd))
29b0f896 4536 {
c0f3af97
L		 4537 unsigned int dup = i.operands;
4538 unsigned int dest = dup - 1;
9fcfb3d7
L		 4539 unsigned int j;
4540
c0f3af97 4541 /* The destination must be an xmm register. */
9c2799c2 4542 gas_assert (i.reg_operands
7ab9ffdd
L		 4543 && MAX_OPERANDS > dup
4544 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 4545
4546 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 4547 {
c0f3af97 4548 /* The first operand is implicit and must be xmm0. */
9c2799c2 4549 gas_assert (operand_type_equal (&i.types[0], &regxmm));
c0f3af97
L		 4550 if (i.op[0].regs->reg_num != 0)
4551 return bad_implicit_operand (1);
4552
4553 if (i.tm.opcode_modifier.vex3sources)
4554 {
4555 /* Keep xmm0 for instructions with VEX prefix and 3
4556 sources. */
4557 goto duplicate;
4558 }
e2ec9d29 4559 else
c0f3af97
L		 4560 {
4561 /* We remove the first xmm0 and keep the number of
4562 operands unchanged, which in fact duplicates the
4563 destination. */
4564 for (j = 1; j < i.operands; j++)
4565 {
4566 i.op[j - 1] = i.op[j];
4567 i.types[j - 1] = i.types[j];
4568 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
4569 }
4570 }
4571 }
4572 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 4573 {
9c2799c2 4574 gas_assert ((MAX_OPERANDS - 1) > dup
7ab9ffdd 4575 && i.tm.opcode_modifier.vex3sources);
c0f3af97
L		 4576
4577 /* Add the implicit xmm0 for instructions with VEX prefix
4578 and 3 sources. */
4579 for (j = i.operands; j > 0; j--)
4580 {
4581 i.op[j] = i.op[j - 1];
4582 i.types[j] = i.types[j - 1];
4583 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
4584 }
4585 i.op[0].regs
4586 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 4587 i.types[0] = regxmm;
c0f3af97
L		 4588 i.tm.operand_types[0] = regxmm;
4589
4590 i.operands += 2;
4591 i.reg_operands += 2;
4592 i.tm.operands += 2;
4593
4594 dup++;
4595 dest++;
4596 i.op[dup] = i.op[dest];
4597 i.types[dup] = i.types[dest];
4598 i.tm.operand_types[dup] = i.tm.operand_types[dest];
e2ec9d29 4599 }
c0f3af97
L		 4600 else
4601 {
4602duplicate:
4603 i.operands++;
4604 i.reg_operands++;
4605 i.tm.operands++;
4606
4607 i.op[dup] = i.op[dest];
4608 i.types[dup] = i.types[dest];
4609 i.tm.operand_types[dup] = i.tm.operand_types[dest];
4610 }
4611
4612 if (i.tm.opcode_modifier.immext)
4613 process_immext ();
4614 }
4615 else if (i.tm.opcode_modifier.firstxmm0)
4616 {
4617 unsigned int j;
4618
4619 /* The first operand is implicit and must be xmm0/ymm0. */
9c2799c2 4620 gas_assert (i.reg_operands
7ab9ffdd
L		 4621 && (operand_type_equal (&i.types[0], &regxmm)
4622 || operand_type_equal (&i.types[0], &regymm)));
c0f3af97
L		 4623 if (i.op[0].regs->reg_num != 0)
4624 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 4625
4626 for (j = 1; j < i.operands; j++)
4627 {
4628 i.op[j - 1] = i.op[j];
4629 i.types[j - 1] = i.types[j];
4630
4631 /* We need to adjust fields in i.tm since they are used by
4632 build_modrm_byte. */
4633 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4634 }
4635
e2ec9d29
L		 4636 i.operands--;
4637 i.reg_operands--;
e2ec9d29
L		 4638 i.tm.operands--;
4639 }
4640 else if (i.tm.opcode_modifier.regkludge)
4641 {
4642 /* The imul $imm, %reg instruction is converted into
4643 imul $imm, %reg, %reg, and the clr %reg instruction
4644 is converted into xor %reg, %reg. */
4645
4646 unsigned int first_reg_op;
4647
4648 if (operand_type_check (i.types[0], reg))
4649 first_reg_op = 0;
4650 else
4651 first_reg_op = 1;
4652 /* Pretend we saw the extra register operand. */
9c2799c2 4653 gas_assert (i.reg_operands == 1
7ab9ffdd 4654 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 4655 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4656 i.types[first_reg_op + 1] = i.types[first_reg_op];
4657 i.operands++;
4658 i.reg_operands++;
29b0f896
AM		 4659 }
4660
40fb9820 4661 if (i.tm.opcode_modifier.shortform)
29b0f896 4662 {
40fb9820
L		 4663 if (i.types[0].bitfield.sreg2
4664 || i.types[0].bitfield.sreg3)
29b0f896 4665 {
4eed87de
AM		 4666 if (i.tm.base_opcode == POP_SEG_SHORT
4667 && i.op[0].regs->reg_num == 1)
29b0f896 4668 {
a87af027 4669 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 4670 return 0;
29b0f896 4671 }
4eed87de
AM		 4672 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4673 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 4674 i.rex |= REX_B;
4eed87de
AM		 4675 }
4676 else
4677 {
7ab9ffdd 4678 /* The register or float register operand is in operand
85f10a01 4679 0 or 1. */
40fb9820 4680 unsigned int op;
7ab9ffdd
L		 4681
4682 if (i.types[0].bitfield.floatreg
4683 || operand_type_check (i.types[0], reg))
4684 op = 0;
4685 else
4686 op = 1;
4eed87de
AM		 4687 /* Register goes in low 3 bits of opcode. */
4688 i.tm.base_opcode |= i.op[op].regs->reg_num;
4689 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 4690 i.rex |= REX_B;
40fb9820 4691 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 4692 {
4eed87de
AM		 4693 /* Warn about some common errors, but press on regardless.
4694 The first case can be generated by gcc (<= 2.8.1). */
4695 if (i.operands == 2)
4696 {
4697 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 4698 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 4699 register_prefix, i.op[!intel_syntax].regs->reg_name,
4700 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 4701 }
4702 else
4703 {
4704 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 4705 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4706 register_prefix, i.op[0].regs->reg_name);
4eed87de 4707 }
29b0f896
AM		 4708 }
4709 }
4710 }
40fb9820 4711 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 4712 {
4713 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 4714 must be put into the modrm byte). Now, we make the modrm and
4715 index base bytes based on all the info we've collected. */
29b0f896
AM		 4716
4717 default_seg = build_modrm_byte ();
4718 }
8a2ed489 4719 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 4720 {
4721 default_seg = &ds;
4722 }
40fb9820 4723 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 4724 {
4725 /* For the string instructions that allow a segment override
4726 on one of their operands, the default segment is ds. */
4727 default_seg = &ds;
4728 }
4729
75178d9d
L		 4730 if (i.tm.base_opcode == 0x8d /* lea */
4731 && i.seg[0]
4732 && !quiet_warnings)
30123838 4733 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 4734
4735 /* If a segment was explicitly specified, and the specified segment
4736 is not the default, use an opcode prefix to select it. If we
4737 never figured out what the default segment is, then default_seg
4738 will be zero at this point, and the specified segment prefix will
4739 always be used. */
29b0f896
AM		 4740 if ((i.seg[0]) && (i.seg[0] != default_seg))
4741 {
4742 if (!add_prefix (i.seg[0]->seg_prefix))
4743 return 0;
4744 }
4745 return 1;
4746}
4747
4748static const seg_entry *
e3bb37b5 4749build_modrm_byte (void)
29b0f896
AM		 4750{
4751 const seg_entry *default_seg = 0;
c0f3af97 4752 unsigned int source, dest;
7ab9ffdd 4753 int vex_3_sources;
c0f3af97
L		 4754
4755 /* The first operand of instructions with VEX prefix and 3 sources
4756 must be VEX_Imm4. */
4757 vex_3_sources = i.tm.opcode_modifier.vex3sources;
4758 if (vex_3_sources)
4759 {
4760 unsigned int nds, reg;
4761
922d8de8
DR		 4762 if (i.tm.opcode_modifier.veximmext
4763 && i.tm.opcode_modifier.immext)
4764 {
4765 dest = i.operands - 2;
4766 gas_assert (dest == 3);
4767 }
4768 else
0bfee649 4769 dest = i.operands - 1;
c0f3af97 4770 nds = dest - 1;
922d8de8
DR		 4771
4772 /* This instruction must have 4 register operands
4773 or 3 register operands plus 1 memory operand.
4774 It must have VexNDS and VexImmExt. */
4775 gas_assert ((i.reg_operands == 4
7ab9ffdd
L		 4776 || (i.reg_operands == 3 && i.mem_operands == 1))
4777 && i.tm.opcode_modifier.vexnds
4778 && i.tm.opcode_modifier.veximmext
922d8de8
DR		 4779 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
4780 || operand_type_equal (&i.tm.operand_types[dest], &regymm)));
c0f3af97 4781
0bfee649
L		 4782 /* Generate an 8bit immediate operand to encode the register
4783 operand. */
4784 expressionS *exp = &im_expressions[i.imm_operands++];
4785 i.op[i.operands].imms = exp;
4786 i.types[i.operands] = imm8;
4787 i.operands++;
922d8de8
DR		 4788 /* If VexW1 is set, the first operand is the source and
4789 the second operand is encoded in the immediate operand. */
4790 if (i.tm.opcode_modifier.vexw1)
4791 {
4792 source = 0;
4793 reg = 1;
4794 }
4795 else
4796 {
4797 source = 1;
4798 reg = 0;
4799 }
4800 /* FMA4 swaps REG and NDS. */
4801 if (i.tm.cpu_flags.bitfield.cpufma4)
4802 {
4803 unsigned int tmp;
4804 tmp = reg;
4805 reg = nds;
4806 nds = tmp;
4807 }
4808 gas_assert ((operand_type_equal (&i.tm.operand_types[reg], &regxmm)
4809 || operand_type_equal (&i.tm.operand_types[reg],
4810 &regymm))
4811 && (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
4812 || operand_type_equal (&i.tm.operand_types[nds],
4813 &regymm)));
0bfee649
L		 4814 exp->X_op = O_constant;
4815 exp->X_add_number
922d8de8
DR		 4816 = ((i.op[reg].regs->reg_num
4817 + ((i.op[reg].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
dae39acc 4818 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 4819 }
4820 else
4821 source = dest = 0;
29b0f896
AM		 4822
4823 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 4824 implicit registers do not count. If there are 3 register
4825 operands, it must be a instruction with VexNDS. For a
4826 instruction with VexNDD, the destination register is encoded
4827 in VEX prefix. If there are 4 register operands, it must be
4828 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 4829 if (i.mem_operands == 0
4830 && ((i.reg_operands == 2
4831 && !i.tm.opcode_modifier.vexndd)
4832 || (i.reg_operands == 3
4833 && i.tm.opcode_modifier.vexnds)
4834 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 4835 {
cab737b9
L		 4836 switch (i.operands)
4837 {
4838 case 2:
4839 source = 0;
4840 break;
4841 case 3:
c81128dc
L		 4842 /* When there are 3 operands, one of them may be immediate,
4843 which may be the first or the last operand. Otherwise,
c0f3af97
L		 4844 the first operand must be shift count register (cl) or it
4845 is an instruction with VexNDS. */
9c2799c2 4846 gas_assert (i.imm_operands == 1
7ab9ffdd
L		 4847 || (i.imm_operands == 0
4848 && (i.tm.opcode_modifier.vexnds
4849 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 4850 if (operand_type_check (i.types[0], imm)
4851 || i.types[0].bitfield.shiftcount)
4852 source = 1;
4853 else
4854 source = 0;
cab737b9
L		 4855 break;
4856 case 4:
368d64cc
L		 4857 /* When there are 4 operands, the first two must be 8bit
4858 immediate operands. The source operand will be the 3rd
c0f3af97
L		 4859 one.
4860
4861 For instructions with VexNDS, if the first operand
4862 an imm8, the source operand is the 2nd one. If the last
4863 operand is imm8, the source operand is the first one. */
9c2799c2 4864 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 4865 && i.types[0].bitfield.imm8
4866 && i.types[1].bitfield.imm8)
4867 || (i.tm.opcode_modifier.vexnds
4868 && i.imm_operands == 1
4869 && (i.types[0].bitfield.imm8
4870 || i.types[i.operands - 1].bitfield.imm8)));
c0f3af97
L		 4871 if (i.tm.opcode_modifier.vexnds)
4872 {
4873 if (i.types[0].bitfield.imm8)
4874 source = 1;
4875 else
4876 source = 0;
4877 }
4878 else
4879 source = 2;
4880 break;
4881 case 5:
cab737b9
L		 4882 break;
4883 default:
4884 abort ();
4885 }
4886
c0f3af97
L		 4887 if (!vex_3_sources)
4888 {
4889 dest = source + 1;
4890
4891 if (i.tm.opcode_modifier.vexnds)
4892 {
4893 /* For instructions with VexNDS, the register-only
4894 source operand must be XMM or YMM register. It is
fa99fab2
L		 4895 encoded in VEX prefix. We need to clear RegMem bit
4896 before calling operand_type_equal. */
4897 i386_operand_type op = i.tm.operand_types[dest];
4898 op.bitfield.regmem = 0;
c0f3af97 4899 if ((dest + 1) >= i.operands
fa99fab2
L		 4900 || (!operand_type_equal (&op, &regxmm)
4901 && !operand_type_equal (&op, &regymm)))
c0f3af97
L		 4902 abort ();
4903 i.vex.register_specifier = i.op[dest].regs;
4904 dest++;
4905 }
4906 }
29b0f896
AM		 4907
4908 i.rm.mode = 3;
4909 /* One of the register operands will be encoded in the i.tm.reg
4910 field, the other in the combined i.tm.mode and i.tm.regmem
4911 fields. If no form of this instruction supports a memory
4912 destination operand, then we assume the source operand may
4913 sometimes be a memory operand and so we need to store the
4914 destination in the i.rm.reg field. */
40fb9820
L		 4915 if (!i.tm.operand_types[dest].bitfield.regmem
4916 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 4917 {
4918 i.rm.reg = i.op[dest].regs->reg_num;
4919 i.rm.regmem = i.op[source].regs->reg_num;
4920 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4921 i.rex |= REX_R;
29b0f896 4922 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4923 i.rex |= REX_B;
29b0f896
AM		 4924 }
4925 else
4926 {
4927 i.rm.reg = i.op[source].regs->reg_num;
4928 i.rm.regmem = i.op[dest].regs->reg_num;
4929 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4930 i.rex |= REX_B;
29b0f896 4931 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4932 i.rex |= REX_R;
29b0f896 4933 }
161a04f6 4934 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 4935 {
40fb9820
L		 4936 if (!i.types[0].bitfield.control
4937 && !i.types[1].bitfield.control)
c4a530c5 4938 abort ();
161a04f6 4939 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 4940 add_prefix (LOCK_PREFIX_OPCODE);
4941 }
29b0f896
AM		 4942 }
4943 else
4944 { /* If it's not 2 reg operands... */
c0f3af97
L		 4945 unsigned int mem;
4946
29b0f896
AM		 4947 if (i.mem_operands)
4948 {
4949 unsigned int fake_zero_displacement = 0;
99018f42 4950 unsigned int op;
4eed87de 4951
7ab9ffdd
L		 4952 for (op = 0; op < i.operands; op++)
4953 if (operand_type_check (i.types[op], anymem))
4954 break;
7ab9ffdd 4955 gas_assert (op < i.operands);
29b0f896
AM		 4956
4957 default_seg = &ds;
4958
4959 if (i.base_reg == 0)
4960 {
4961 i.rm.mode = 0;
4962 if (!i.disp_operands)
4963 fake_zero_displacement = 1;
4964 if (i.index_reg == 0)
4965 {
4966 /* Operand is just <disp> */
20f0a1fc 4967 if (flag_code == CODE_64BIT)
29b0f896
AM		 4968 {
4969 /* 64bit mode overwrites the 32bit absolute
4970 addressing by RIP relative addressing and
4971 absolute addressing is encoded by one of the
4972 redundant SIB forms. */
4973 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4974 i.sib.base = NO_BASE_REGISTER;
4975 i.sib.index = NO_INDEX_REGISTER;
fc225355 4976 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 4977 ? disp32s : disp32);
20f0a1fc 4978 }
fc225355
L		 4979 else if ((flag_code == CODE_16BIT)
4980 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 4981 {
4982 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 4983 i.types[op] = disp16;
20f0a1fc
NC		 4984 }
4985 else
4986 {
4987 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 4988 i.types[op] = disp32;
29b0f896
AM		 4989 }
4990 }
4991 else /* !i.base_reg && i.index_reg */
4992 {
db51cc60
L		 4993 if (i.index_reg->reg_num == RegEiz
4994 || i.index_reg->reg_num == RegRiz)
4995 i.sib.index = NO_INDEX_REGISTER;
4996 else
4997 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 4998 i.sib.base = NO_BASE_REGISTER;
4999 i.sib.scale = i.log2_scale_factor;
5000 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 5001 i.types[op].bitfield.disp8 = 0;
5002 i.types[op].bitfield.disp16 = 0;
5003 i.types[op].bitfield.disp64 = 0;
29b0f896 5004 if (flag_code != CODE_64BIT)
40fb9820
L		 5005 {
5006 /* Must be 32 bit */
5007 i.types[op].bitfield.disp32 = 1;
5008 i.types[op].bitfield.disp32s = 0;
5009 }
29b0f896 5010 else
40fb9820
L		 5011 {
5012 i.types[op].bitfield.disp32 = 0;
5013 i.types[op].bitfield.disp32s = 1;
5014 }
29b0f896 5015 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5016 i.rex |= REX_X;
29b0f896
AM		 5017 }
5018 }
5019 /* RIP addressing for 64bit mode. */
9a04903e
JB		 5020 else if (i.base_reg->reg_num == RegRip ||
5021 i.base_reg->reg_num == RegEip)
29b0f896
AM		 5022 {
5023 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5024 i.types[op].bitfield.disp8 = 0;
5025 i.types[op].bitfield.disp16 = 0;
5026 i.types[op].bitfield.disp32 = 0;
5027 i.types[op].bitfield.disp32s = 1;
5028 i.types[op].bitfield.disp64 = 0;
71903a11 5029 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5030 if (! i.disp_operands)
5031 fake_zero_displacement = 1;
29b0f896 5032 }
40fb9820 5033 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 5034 {
5035 switch (i.base_reg->reg_num)
5036 {
5037 case 3: /* (%bx) */
5038 if (i.index_reg == 0)
5039 i.rm.regmem = 7;
5040 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5041 i.rm.regmem = i.index_reg->reg_num - 6;
5042 break;
5043 case 5: /* (%bp) */
5044 default_seg = &ss;
5045 if (i.index_reg == 0)
5046 {
5047 i.rm.regmem = 6;
40fb9820 5048 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5049 {
5050 /* fake (%bp) into 0(%bp) */
40fb9820 5051 i.types[op].bitfield.disp8 = 1;
252b5132 5052 fake_zero_displacement = 1;
29b0f896
AM		 5053 }
5054 }
5055 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5056 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5057 break;
5058 default: /* (%si) -> 4 or (%di) -> 5 */
5059 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5060 }
5061 i.rm.mode = mode_from_disp_size (i.types[op]);
5062 }
5063 else /* i.base_reg and 32/64 bit mode */
5064 {
5065 if (flag_code == CODE_64BIT
40fb9820
L		 5066 && operand_type_check (i.types[op], disp))
5067 {
5068 i386_operand_type temp;
0dfbf9d7 5069 operand_type_set (&temp, 0);
40fb9820
L		 5070 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5071 i.types[op] = temp;
5072 if (i.prefix[ADDR_PREFIX] == 0)
5073 i.types[op].bitfield.disp32s = 1;
5074 else
5075 i.types[op].bitfield.disp32 = 1;
5076 }
20f0a1fc 5077
29b0f896
AM		 5078 i.rm.regmem = i.base_reg->reg_num;
5079 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5080 i.rex |= REX_B;
29b0f896
AM		 5081 i.sib.base = i.base_reg->reg_num;
5082 /* x86-64 ignores REX prefix bit here to avoid decoder
5083 complications. */
5084 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5085 {
5086 default_seg = &ss;
5087 if (i.disp_operands == 0)
5088 {
5089 fake_zero_displacement = 1;
40fb9820 5090 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5091 }
5092 }
5093 else if (i.base_reg->reg_num == ESP_REG_NUM)
5094 {
5095 default_seg = &ss;
5096 }
5097 i.sib.scale = i.log2_scale_factor;
5098 if (i.index_reg == 0)
5099 {
5100 /* <disp>(%esp) becomes two byte modrm with no index
5101 register. We've already stored the code for esp
5102 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5103 Any base register besides %esp will not use the
5104 extra modrm byte. */
5105 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 5106 }
5107 else
5108 {
db51cc60
L		 5109 if (i.index_reg->reg_num == RegEiz
5110 || i.index_reg->reg_num == RegRiz)
5111 i.sib.index = NO_INDEX_REGISTER;
5112 else
5113 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5114 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5115 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5116 i.rex |= REX_X;
29b0f896 5117 }
67a4f2b7
AO		 5118
5119 if (i.disp_operands
5120 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5121 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5122 i.rm.mode = 0;
5123 else
5124 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 5125 }
252b5132 5126
29b0f896
AM		 5127 if (fake_zero_displacement)
5128 {
5129 /* Fakes a zero displacement assuming that i.types[op]
5130 holds the correct displacement size. */
5131 expressionS *exp;
5132
9c2799c2 5133 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 5134 exp = &disp_expressions[i.disp_operands++];
5135 i.op[op].disps = exp;
5136 exp->X_op = O_constant;
5137 exp->X_add_number = 0;
5138 exp->X_add_symbol = (symbolS *) 0;
5139 exp->X_op_symbol = (symbolS *) 0;
5140 }
c0f3af97
L		 5141
5142 mem = op;
29b0f896 5143 }
c0f3af97
L		 5144 else
5145 mem = ~0;
252b5132 5146
29b0f896
AM		 5147 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5148 (if any) based on i.tm.extension_opcode. Again, we must be
5149 careful to make sure that segment/control/debug/test/MMX
5150 registers are coded into the i.rm.reg field. */
5151 if (i.reg_operands)
5152 {
99018f42 5153 unsigned int op;
7ab9ffdd
L		 5154 unsigned int vex_reg = ~0;
5155
5156 for (op = 0; op < i.operands; op++)
5157 if (i.types[op].bitfield.reg8
5158 || i.types[op].bitfield.reg16
5159 || i.types[op].bitfield.reg32
5160 || i.types[op].bitfield.reg64
5161 || i.types[op].bitfield.regmmx
5162 || i.types[op].bitfield.regxmm
5163 || i.types[op].bitfield.regymm
5164 || i.types[op].bitfield.sreg2
5165 || i.types[op].bitfield.sreg3
5166 || i.types[op].bitfield.control
5167 || i.types[op].bitfield.debug
5168 || i.types[op].bitfield.test)
5169 break;
c0209578 5170
7ab9ffdd
L		 5171 if (vex_3_sources)
5172 op = dest;
5173 else if (i.tm.opcode_modifier.vexnds)
5174 {
5175 /* For instructions with VexNDS, the register-only
5176 source operand is encoded in VEX prefix. */
5177 gas_assert (mem != (unsigned int) ~0);
c0f3af97 5178
7ab9ffdd 5179 if (op > mem)
c0f3af97 5180 {
7ab9ffdd
L		 5181 vex_reg = op++;
5182 gas_assert (op < i.operands);
c0f3af97
L		 5183 }
5184 else
c0f3af97 5185 {
7ab9ffdd
L		 5186 vex_reg = op + 1;
5187 gas_assert (vex_reg < i.operands);
c0f3af97 5188 }
7ab9ffdd
L		 5189 }
5190 else if (i.tm.opcode_modifier.vexndd)
5191 {
5192 /* For instructions with VexNDD, there should be
5193 no memory operand and the register destination
5194 is encoded in VEX prefix. */
5195 gas_assert (i.mem_operands == 0
5196 && (op + 2) == i.operands);
5197 vex_reg = op + 1;
5198 }
5199 else
5200 gas_assert (op < i.operands);
99018f42 5201
7ab9ffdd
L		 5202 if (vex_reg != (unsigned int) ~0)
5203 {
5204 gas_assert (i.reg_operands == 2);
5205
5206 if (!operand_type_equal (&i.tm.operand_types[vex_reg],
5207 & regxmm)
5208 && !operand_type_equal (&i.tm.operand_types[vex_reg],
5209 &regymm))
5210 abort ();
5211 i.vex.register_specifier = i.op[vex_reg].regs;
5212 }
5213
5214 /* If there is an extension opcode to put here, the
5215 register number must be put into the regmem field. */
5216 if (i.tm.extension_opcode != None)
5217 {
5218 i.rm.regmem = i.op[op].regs->reg_num;
5219 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5220 i.rex |= REX_B;
5221 }
5222 else
5223 {
5224 i.rm.reg = i.op[op].regs->reg_num;
5225 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5226 i.rex |= REX_R;
5227 }
252b5132 5228
29b0f896
AM		 5229 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5230 must set it to 3 to indicate this is a register operand
5231 in the regmem field. */
5232 if (!i.mem_operands)
5233 i.rm.mode = 3;
5234 }
252b5132 5235
29b0f896 5236 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 5237 if (i.tm.extension_opcode != None)
29b0f896
AM		 5238 i.rm.reg = i.tm.extension_opcode;
5239 }
5240 return default_seg;
5241}
252b5132 5242
29b0f896 5243static void
e3bb37b5 5244output_branch (void)
29b0f896
AM		 5245{
5246 char *p;
5247 int code16;
5248 int prefix;
5249 relax_substateT subtype;
5250 symbolS *sym;
5251 offsetT off;
5252
5253 code16 = 0;
5254 if (flag_code == CODE_16BIT)
5255 code16 = CODE16;
5256
5257 prefix = 0;
5258 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5259 {
29b0f896
AM		 5260 prefix = 1;
5261 i.prefixes -= 1;
5262 code16 ^= CODE16;
252b5132 5263 }
29b0f896
AM		 5264 /* Pentium4 branch hints. */
5265 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5266 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5267 {
29b0f896
AM		 5268 prefix++;
5269 i.prefixes--;
5270 }
5271 if (i.prefix[REX_PREFIX] != 0)
5272 {
5273 prefix++;
5274 i.prefixes--;
2f66722d
AM		 5275 }
5276
29b0f896
AM		 5277 if (i.prefixes != 0 && !intel_syntax)
5278 as_warn (_("skipping prefixes on this instruction"));
5279
5280 /* It's always a symbol; End frag & setup for relax.
5281 Make sure there is enough room in this frag for the largest
5282 instruction we may generate in md_convert_frag. This is 2
5283 bytes for the opcode and room for the prefix and largest
5284 displacement. */
5285 frag_grow (prefix + 2 + 4);
5286 /* Prefix and 1 opcode byte go in fr_fix. */
5287 p = frag_more (prefix + 1);
5288 if (i.prefix[DATA_PREFIX] != 0)
5289 *p++ = DATA_PREFIX_OPCODE;
5290 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5291 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5292 *p++ = i.prefix[SEG_PREFIX];
5293 if (i.prefix[REX_PREFIX] != 0)
5294 *p++ = i.prefix[REX_PREFIX];
5295 *p = i.tm.base_opcode;
5296
5297 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5298 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 5299 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 5300 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5301 else
5302 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5303 subtype |= code16;
3e73aa7c 5304
29b0f896
AM		 5305 sym = i.op[0].disps->X_add_symbol;
5306 off = i.op[0].disps->X_add_number;
3e73aa7c 5307
29b0f896
AM		 5308 if (i.op[0].disps->X_op != O_constant
5309 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5310 {
29b0f896
AM		 5311 /* Handle complex expressions. */
5312 sym = make_expr_symbol (i.op[0].disps);
5313 off = 0;
5314 }
3e73aa7c 5315
29b0f896
AM		 5316 /* 1 possible extra opcode + 4 byte displacement go in var part.
5317 Pass reloc in fr_var. */
5318 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5319}
3e73aa7c 5320
29b0f896 5321static void
e3bb37b5 5322output_jump (void)
29b0f896
AM		 5323{
5324 char *p;
5325 int size;
3e02c1cc 5326 fixS *fixP;
29b0f896 5327
40fb9820 5328 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 5329 {
5330 /* This is a loop or jecxz type instruction. */
5331 size = 1;
5332 if (i.prefix[ADDR_PREFIX] != 0)
5333 {
5334 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5335 i.prefixes -= 1;
5336 }
5337 /* Pentium4 branch hints. */
5338 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5339 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5340 {
5341 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5342 i.prefixes--;
3e73aa7c
JH		 5343 }
5344 }
29b0f896
AM		 5345 else
5346 {
5347 int code16;
3e73aa7c 5348
29b0f896
AM		 5349 code16 = 0;
5350 if (flag_code == CODE_16BIT)
5351 code16 = CODE16;
3e73aa7c 5352
29b0f896
AM		 5353 if (i.prefix[DATA_PREFIX] != 0)
5354 {
5355 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5356 i.prefixes -= 1;
5357 code16 ^= CODE16;
5358 }
252b5132 5359
29b0f896
AM		 5360 size = 4;
5361 if (code16)
5362 size = 2;
5363 }
9fcc94b6 5364
29b0f896
AM		 5365 if (i.prefix[REX_PREFIX] != 0)
5366 {
5367 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5368 i.prefixes -= 1;
5369 }
252b5132 5370
29b0f896
AM		 5371 if (i.prefixes != 0 && !intel_syntax)
5372 as_warn (_("skipping prefixes on this instruction"));
e0890092 5373
29b0f896
AM		 5374 p = frag_more (1 + size);
5375 *p++ = i.tm.base_opcode;
e0890092 5376
3e02c1cc
AM		 5377 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5378 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5379
5380 /* All jumps handled here are signed, but don't use a signed limit
5381 check for 32 and 16 bit jumps as we want to allow wrap around at
5382 4G and 64k respectively. */
5383 if (size == 1)
5384 fixP->fx_signed = 1;
29b0f896 5385}
e0890092 5386
29b0f896 5387static void
e3bb37b5 5388output_interseg_jump (void)
29b0f896
AM		 5389{
5390 char *p;
5391 int size;
5392 int prefix;
5393 int code16;
252b5132 5394
29b0f896
AM		 5395 code16 = 0;
5396 if (flag_code == CODE_16BIT)
5397 code16 = CODE16;
a217f122 5398
29b0f896
AM		 5399 prefix = 0;
5400 if (i.prefix[DATA_PREFIX] != 0)
5401 {
5402 prefix = 1;
5403 i.prefixes -= 1;
5404 code16 ^= CODE16;
5405 }
5406 if (i.prefix[REX_PREFIX] != 0)
5407 {
5408 prefix++;
5409 i.prefixes -= 1;
5410 }
252b5132 5411
29b0f896
AM		 5412 size = 4;
5413 if (code16)
5414 size = 2;
252b5132 5415
29b0f896
AM		 5416 if (i.prefixes != 0 && !intel_syntax)
5417 as_warn (_("skipping prefixes on this instruction"));
252b5132 5418
29b0f896
AM		 5419 /* 1 opcode; 2 segment; offset */
5420 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 5421
29b0f896
AM		 5422 if (i.prefix[DATA_PREFIX] != 0)
5423 *p++ = DATA_PREFIX_OPCODE;
252b5132 5424
29b0f896
AM		 5425 if (i.prefix[REX_PREFIX] != 0)
5426 *p++ = i.prefix[REX_PREFIX];
252b5132 5427
29b0f896
AM		 5428 *p++ = i.tm.base_opcode;
5429 if (i.op[1].imms->X_op == O_constant)
5430 {
5431 offsetT n = i.op[1].imms->X_add_number;
252b5132 5432
29b0f896
AM		 5433 if (size == 2
5434 && !fits_in_unsigned_word (n)
5435 && !fits_in_signed_word (n))
5436 {
5437 as_bad (_("16-bit jump out of range"));
5438 return;
5439 }
5440 md_number_to_chars (p, n, size);
5441 }
5442 else
5443 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5444 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5445 if (i.op[0].imms->X_op != O_constant)
5446 as_bad (_("can't handle non absolute segment in `%s'"),
5447 i.tm.name);
5448 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5449}
a217f122 5450
29b0f896 5451static void
e3bb37b5 5452output_insn (void)
29b0f896 5453{
2bbd9c25
JJ		 5454 fragS *insn_start_frag;
5455 offsetT insn_start_off;
5456
29b0f896
AM		 5457 /* Tie dwarf2 debug info to the address at the start of the insn.
5458 We can't do this after the insn has been output as the current
5459 frag may have been closed off. eg. by frag_var. */
5460 dwarf2_emit_insn (0);
5461
2bbd9c25
JJ		 5462 insn_start_frag = frag_now;
5463 insn_start_off = frag_now_fix ();
5464
29b0f896 5465 /* Output jumps. */
40fb9820 5466 if (i.tm.opcode_modifier.jump)
29b0f896 5467 output_branch ();
40fb9820
L		 5468 else if (i.tm.opcode_modifier.jumpbyte
5469 || i.tm.opcode_modifier.jumpdword)
29b0f896 5470 output_jump ();
40fb9820 5471 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 5472 output_interseg_jump ();
5473 else
5474 {
5475 /* Output normal instructions here. */
5476 char *p;
5477 unsigned char *q;
47465058 5478 unsigned int j;
331d2d0d 5479 unsigned int prefix;
4dffcebc 5480
c0f3af97
L		 5481 /* Since the VEX prefix contains the implicit prefix, we don't
5482 need the explicit prefix. */
5483 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 5484 {
c0f3af97 5485 switch (i.tm.opcode_length)
bc4bd9ab 5486 {
c0f3af97
L		 5487 case 3:
5488 if (i.tm.base_opcode & 0xff000000)
4dffcebc 5489 {
c0f3af97
L		 5490 prefix = (i.tm.base_opcode >> 24) & 0xff;
5491 goto check_prefix;
5492 }
5493 break;
5494 case 2:
5495 if ((i.tm.base_opcode & 0xff0000) != 0)
5496 {
5497 prefix = (i.tm.base_opcode >> 16) & 0xff;
5498 if (i.tm.cpu_flags.bitfield.cpupadlock)
5499 {
4dffcebc 5500check_prefix:
c0f3af97
L		 5501 if (prefix != REPE_PREFIX_OPCODE
5502 || (i.prefix[LOCKREP_PREFIX]
5503 != REPE_PREFIX_OPCODE))
5504 add_prefix (prefix);
5505 }
5506 else
4dffcebc
L		 5507 add_prefix (prefix);
5508 }
c0f3af97
L		 5509 break;
5510 case 1:
5511 break;
5512 default:
5513 abort ();
bc4bd9ab 5514 }
c0f3af97
L		 5515
5516 /* The prefix bytes. */
5517 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5518 if (*q)
5519 FRAG_APPEND_1_CHAR (*q);
0f10071e 5520 }
252b5132 5521
c0f3af97
L		 5522 if (i.tm.opcode_modifier.vex)
5523 {
5524 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
5525 if (*q)
5526 switch (j)
5527 {
5528 case REX_PREFIX:
5529 /* REX byte is encoded in VEX prefix. */
5530 break;
5531 case SEG_PREFIX:
5532 case ADDR_PREFIX:
5533 FRAG_APPEND_1_CHAR (*q);
5534 break;
5535 default:
5536 /* There should be no other prefixes for instructions
5537 with VEX prefix. */
5538 abort ();
5539 }
5540
5541 /* Now the VEX prefix. */
5542 p = frag_more (i.vex.length);
5543 for (j = 0; j < i.vex.length; j++)
5544 p[j] = i.vex.bytes[j];
5545 }
252b5132 5546
29b0f896 5547 /* Now the opcode; be careful about word order here! */
4dffcebc 5548 if (i.tm.opcode_length == 1)
29b0f896
AM		 5549 {
5550 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5551 }
5552 else
5553 {
4dffcebc 5554 switch (i.tm.opcode_length)
331d2d0d 5555 {
4dffcebc 5556 case 3:
331d2d0d
L		 5557 p = frag_more (3);
5558 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 5559 break;
5560 case 2:
5561 p = frag_more (2);
5562 break;
5563 default:
5564 abort ();
5565 break;
331d2d0d 5566 }
0f10071e 5567
29b0f896
AM		 5568 /* Put out high byte first: can't use md_number_to_chars! */
5569 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5570 *p = i.tm.base_opcode & 0xff;
5571 }
3e73aa7c 5572
29b0f896 5573 /* Now the modrm byte and sib byte (if present). */
40fb9820 5574 if (i.tm.opcode_modifier.modrm)
29b0f896 5575 {
4a3523fa
L		 5576 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5577 | i.rm.reg << 3
5578 | i.rm.mode << 6));
29b0f896
AM		 5579 /* If i.rm.regmem == ESP (4)
5580 && i.rm.mode != (Register mode)
5581 && not 16 bit
5582 ==> need second modrm byte. */
5583 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5584 && i.rm.mode != 3
40fb9820 5585 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 5586 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5587 | i.sib.index << 3
5588 | i.sib.scale << 6));
29b0f896 5589 }
3e73aa7c 5590
29b0f896 5591 if (i.disp_operands)
2bbd9c25 5592 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 5593
29b0f896 5594 if (i.imm_operands)
2bbd9c25 5595 output_imm (insn_start_frag, insn_start_off);
29b0f896 5596 }
252b5132 5597
29b0f896
AM		 5598#ifdef DEBUG386
5599 if (flag_debug)
5600 {
7b81dfbb 5601 pi ("" /*line*/, &i);
29b0f896
AM		 5602 }
5603#endif /* DEBUG386 */
5604}
252b5132 5605
e205caa7
L		 5606/* Return the size of the displacement operand N. */
5607
5608static int
5609disp_size (unsigned int n)
5610{
5611 int size = 4;
40fb9820
L		 5612 if (i.types[n].bitfield.disp64)
5613 size = 8;
5614 else if (i.types[n].bitfield.disp8)
5615 size = 1;
5616 else if (i.types[n].bitfield.disp16)
5617 size = 2;
e205caa7
L		 5618 return size;
5619}
5620
5621/* Return the size of the immediate operand N. */
5622
5623static int
5624imm_size (unsigned int n)
5625{
5626 int size = 4;
40fb9820
L		 5627 if (i.types[n].bitfield.imm64)
5628 size = 8;
5629 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5630 size = 1;
5631 else if (i.types[n].bitfield.imm16)
5632 size = 2;
e205caa7
L		 5633 return size;
5634}
5635
29b0f896 5636static void
64e74474 5637output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5638{
5639 char *p;
5640 unsigned int n;
252b5132 5641
29b0f896
AM		 5642 for (n = 0; n < i.operands; n++)
5643 {
40fb9820 5644 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 5645 {
5646 if (i.op[n].disps->X_op == O_constant)
5647 {
e205caa7 5648 int size = disp_size (n);
29b0f896 5649 offsetT val;
252b5132 5650
29b0f896
AM		 5651 val = offset_in_range (i.op[n].disps->X_add_number,
5652 size);
5653 p = frag_more (size);
5654 md_number_to_chars (p, val, size);
5655 }
5656 else
5657 {
f86103b7 5658 enum bfd_reloc_code_real reloc_type;
e205caa7 5659 int size = disp_size (n);
40fb9820 5660 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 5661 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5662
e205caa7 5663 /* We can't have 8 bit displacement here. */
9c2799c2 5664 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 5665
29b0f896
AM		 5666 /* The PC relative address is computed relative
5667 to the instruction boundary, so in case immediate
5668 fields follows, we need to adjust the value. */
5669 if (pcrel && i.imm_operands)
5670 {
29b0f896 5671 unsigned int n1;
e205caa7 5672 int sz = 0;
252b5132 5673
29b0f896 5674 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 5675 if (operand_type_check (i.types[n1], imm))
252b5132 5676 {
e205caa7
L		 5677 /* Only one immediate is allowed for PC
5678 relative address. */
9c2799c2 5679 gas_assert (sz == 0);
e205caa7
L		 5680 sz = imm_size (n1);
5681 i.op[n].disps->X_add_number -= sz;
252b5132 5682 }
29b0f896 5683 /* We should find the immediate. */
9c2799c2 5684 gas_assert (sz != 0);
29b0f896 5685 }
520dc8e8 5686
29b0f896 5687 p = frag_more (size);
2bbd9c25 5688 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 5689 if (GOT_symbol
2bbd9c25 5690 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 5691 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5692 || reloc_type == BFD_RELOC_X86_64_32S
5693 || (reloc_type == BFD_RELOC_64
5694 && object_64bit))
d6ab8113
JB		 5695 && (i.op[n].disps->X_op == O_symbol
5696 || (i.op[n].disps->X_op == O_add
5697 && ((symbol_get_value_expression
5698 (i.op[n].disps->X_op_symbol)->X_op)
5699 == O_subtract))))
5700 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 5701 {
5702 offsetT add;
5703
5704 if (insn_start_frag == frag_now)
5705 add = (p - frag_now->fr_literal) - insn_start_off;
5706 else
5707 {
5708 fragS *fr;
5709
5710 add = insn_start_frag->fr_fix - insn_start_off;
5711 for (fr = insn_start_frag->fr_next;
5712 fr && fr != frag_now; fr = fr->fr_next)
5713 add += fr->fr_fix;
5714 add += p - frag_now->fr_literal;
5715 }
5716
4fa24527 5717 if (!object_64bit)
7b81dfbb
AJ		 5718 {
5719 reloc_type = BFD_RELOC_386_GOTPC;
5720 i.op[n].imms->X_add_number += add;
5721 }
5722 else if (reloc_type == BFD_RELOC_64)
5723 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 5724 else
7b81dfbb
AJ		 5725 /* Don't do the adjustment for x86-64, as there
5726 the pcrel addressing is relative to the _next_
5727 insn, and that is taken care of in other code. */
d6ab8113 5728 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 5729 }
062cd5e7 5730 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 5731 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 5732 }
5733 }
5734 }
5735}
252b5132 5736
29b0f896 5737static void
64e74474 5738output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5739{
5740 char *p;
5741 unsigned int n;
252b5132 5742
29b0f896
AM		 5743 for (n = 0; n < i.operands; n++)
5744 {
40fb9820 5745 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 5746 {
5747 if (i.op[n].imms->X_op == O_constant)
5748 {
e205caa7 5749 int size = imm_size (n);
29b0f896 5750 offsetT val;
b4cac588 5751
29b0f896
AM		 5752 val = offset_in_range (i.op[n].imms->X_add_number,
5753 size);
5754 p = frag_more (size);
5755 md_number_to_chars (p, val, size);
5756 }
5757 else
5758 {
5759 /* Not absolute_section.
5760 Need a 32-bit fixup (don't support 8bit
5761 non-absolute imms). Try to support other
5762 sizes ... */
f86103b7 5763 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 5764 int size = imm_size (n);
5765 int sign;
29b0f896 5766
40fb9820 5767 if (i.types[n].bitfield.imm32s
a7d61044 5768 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 5769 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 5770 sign = 1;
e205caa7
L		 5771 else
5772 sign = 0;
520dc8e8 5773
29b0f896
AM		 5774 p = frag_more (size);
5775 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 5776
2bbd9c25
JJ		 5777 /* This is tough to explain. We end up with this one if we
5778 * have operands that look like
5779 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5780 * obtain the absolute address of the GOT, and it is strongly
5781 * preferable from a performance point of view to avoid using
5782 * a runtime relocation for this. The actual sequence of
5783 * instructions often look something like:
5784 *
5785 * call .L66
5786 * .L66:
5787 * popl %ebx
5788 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5789 *
5790 * The call and pop essentially return the absolute address
5791 * of the label .L66 and store it in %ebx. The linker itself
5792 * will ultimately change the first operand of the addl so
5793 * that %ebx points to the GOT, but to keep things simple, the
5794 * .o file must have this operand set so that it generates not
5795 * the absolute address of .L66, but the absolute address of
5796 * itself. This allows the linker itself simply treat a GOTPC
5797 * relocation as asking for a pcrel offset to the GOT to be
5798 * added in, and the addend of the relocation is stored in the
5799 * operand field for the instruction itself.
5800 *
5801 * Our job here is to fix the operand so that it would add
5802 * the correct offset so that %ebx would point to itself. The
5803 * thing that is tricky is that .-.L66 will point to the
5804 * beginning of the instruction, so we need to further modify
5805 * the operand so that it will point to itself. There are
5806 * other cases where you have something like:
5807 *
5808 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5809 *
5810 * and here no correction would be required. Internally in
5811 * the assembler we treat operands of this form as not being
5812 * pcrel since the '.' is explicitly mentioned, and I wonder
5813 * whether it would simplify matters to do it this way. Who
5814 * knows. In earlier versions of the PIC patches, the
5815 * pcrel_adjust field was used to store the correction, but
5816 * since the expression is not pcrel, I felt it would be
5817 * confusing to do it this way. */
5818
d6ab8113 5819 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5820 || reloc_type == BFD_RELOC_X86_64_32S
5821 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 5822 && GOT_symbol
5823 && GOT_symbol == i.op[n].imms->X_add_symbol
5824 && (i.op[n].imms->X_op == O_symbol
5825 || (i.op[n].imms->X_op == O_add
5826 && ((symbol_get_value_expression
5827 (i.op[n].imms->X_op_symbol)->X_op)
5828 == O_subtract))))
5829 {
2bbd9c25
JJ		 5830 offsetT add;
5831
5832 if (insn_start_frag == frag_now)
5833 add = (p - frag_now->fr_literal) - insn_start_off;
5834 else
5835 {
5836 fragS *fr;
5837
5838 add = insn_start_frag->fr_fix - insn_start_off;
5839 for (fr = insn_start_frag->fr_next;
5840 fr && fr != frag_now; fr = fr->fr_next)
5841 add += fr->fr_fix;
5842 add += p - frag_now->fr_literal;
5843 }
5844
4fa24527 5845 if (!object_64bit)
d6ab8113 5846 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 5847 else if (size == 4)
d6ab8113 5848 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 5849 else if (size == 8)
5850 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 5851 i.op[n].imms->X_add_number += add;
29b0f896 5852 }
29b0f896
AM		 5853 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5854 i.op[n].imms, 0, reloc_type);
5855 }
5856 }
5857 }
252b5132
RH		 5858}
5859\f
d182319b
JB		 5860/* x86_cons_fix_new is called via the expression parsing code when a
5861 reloc is needed. We use this hook to get the correct .got reloc. */
5862static enum bfd_reloc_code_real got_reloc = NO_RELOC;
5863static int cons_sign = -1;
5864
5865void
e3bb37b5 5866x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 5867 expressionS *exp)
d182319b
JB		 5868{
5869 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
5870
5871 got_reloc = NO_RELOC;
5872
5873#ifdef TE_PE
5874 if (exp->X_op == O_secrel)
5875 {
5876 exp->X_op = O_symbol;
5877 r = BFD_RELOC_32_SECREL;
5878 }
5879#endif
5880
5881 fix_new_exp (frag, off, len, exp, 0, r);
5882}
5883
718ddfc0
JB		 5884#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5885# define lex_got(reloc, adjust, types) NULL
5886#else
f3c180ae
AM		 5887/* Parse operands of the form
5888 <symbol>@GOTOFF+<nnn>
5889 and similar .plt or .got references.
5890
5891 If we find one, set up the correct relocation in RELOC and copy the
5892 input string, minus the `@GOTOFF' into a malloc'd buffer for
5893 parsing by the calling routine. Return this buffer, and if ADJUST
5894 is non-null set it to the length of the string we removed from the
5895 input line. Otherwise return NULL. */
5896static char *
3956db08 5897lex_got (enum bfd_reloc_code_real *reloc,
64e74474 5898 int *adjust,
40fb9820 5899 i386_operand_type *types)
f3c180ae 5900{
7b81dfbb
AJ		 5901 /* Some of the relocations depend on the size of what field is to
5902 be relocated. But in our callers i386_immediate and i386_displacement
5903 we don't yet know the operand size (this will be set by insn
5904 matching). Hence we record the word32 relocation here,
5905 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 5906 static const struct {
5907 const char *str;
4fa24527 5908 const enum bfd_reloc_code_real rel[2];
40fb9820 5909 const i386_operand_type types64;
f3c180ae 5910 } gotrel[] = {
4eed87de
AM		 5911 { "PLTOFF", { 0,
5912 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 5913 OPERAND_TYPE_IMM64 },
4eed87de
AM		 5914 { "PLT", { BFD_RELOC_386_PLT32,
5915 BFD_RELOC_X86_64_PLT32 },
40fb9820 5916 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5917 { "GOTPLT", { 0,
5918 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 5919 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 5920 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
5921 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 5922 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 5923 { "GOTPCREL", { 0,
5924 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 5925 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5926 { "TLSGD", { BFD_RELOC_386_TLS_GD,
5927 BFD_RELOC_X86_64_TLSGD },
40fb9820 5928 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5929 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
5930 0 },
40fb9820 5931 OPERAND_TYPE_NONE },
4eed87de
AM		 5932 { "TLSLD", { 0,
5933 BFD_RELOC_X86_64_TLSLD },
40fb9820 5934 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5935 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
5936 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 5937 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5938 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
5939 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 5940 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 5941 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
5942 0 },
40fb9820 5943 OPERAND_TYPE_NONE },
4eed87de
AM		 5944 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
5945 BFD_RELOC_X86_64_DTPOFF32 },
7ab9ffdd 5946
40fb9820 5947 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 5948 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
5949 0 },
40fb9820 5950 OPERAND_TYPE_NONE },
4eed87de
AM		 5951 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
5952 0 },
40fb9820 5953 OPERAND_TYPE_NONE },
4eed87de
AM		 5954 { "GOT", { BFD_RELOC_386_GOT32,
5955 BFD_RELOC_X86_64_GOT32 },
40fb9820 5956 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM		 5957 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
5958 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 5959 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5960 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
5961 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 5962 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 5963 };
5964 char *cp;
5965 unsigned int j;
5966
718ddfc0
JB		 5967 if (!IS_ELF)
5968 return NULL;
5969
f3c180ae 5970 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 5971 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 5972 return NULL;
5973
47465058 5974 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae
AM		 5975 {
5976 int len;
5977
5978 len = strlen (gotrel[j].str);
28f81592 5979 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 5980 {
4fa24527 5981 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 5982 {
28f81592
AM		 5983 int first, second;
5984 char *tmpbuf, *past_reloc;
f3c180ae 5985
4fa24527 5986 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 5987 if (adjust)
5988 *adjust = len;
f3c180ae 5989
3956db08
JB		 5990 if (types)
5991 {
5992 if (flag_code != CODE_64BIT)
40fb9820
L		 5993 {
5994 types->bitfield.imm32 = 1;
5995 types->bitfield.disp32 = 1;
5996 }
3956db08
JB		 5997 else
5998 *types = gotrel[j].types64;
5999 }
6000
f3c180ae
AM		 6001 if (GOT_symbol == NULL)
6002 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6003
28f81592 6004 /* The length of the first part of our input line. */
f3c180ae 6005 first = cp - input_line_pointer;
28f81592
AM		 6006
6007 /* The second part goes from after the reloc token until
67c11a9b 6008 (and including) an end_of_line char or comma. */
28f81592 6009 past_reloc = cp + 1 + len;
67c11a9b
AM		 6010 cp = past_reloc;
6011 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6012 ++cp;
6013 second = cp + 1 - past_reloc;
28f81592
AM		 6014
6015 /* Allocate and copy string. The trailing NUL shouldn't
6016 be necessary, but be safe. */
6017 tmpbuf = xmalloc (first + second + 2);
f3c180ae 6018 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 6019 if (second != 0 && *past_reloc != ' ')
6020 /* Replace the relocation token with ' ', so that
6021 errors like foo@GOTOFF1 will be detected. */
6022 tmpbuf[first++] = ' ';
6023 memcpy (tmpbuf + first, past_reloc, second);
6024 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6025 return tmpbuf;
6026 }
6027
4fa24527
JB		 6028 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6029 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6030 return NULL;
6031 }
6032 }
6033
6034 /* Might be a symbol version string. Don't as_bad here. */
6035 return NULL;
6036}
6037
f3c180ae 6038void
e3bb37b5 6039x86_cons (expressionS *exp, int size)
f3c180ae 6040{
ee86248c
JB		 6041 intel_syntax = -intel_syntax;
6042
4fa24527 6043 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6044 {
6045 /* Handle @GOTOFF and the like in an expression. */
6046 char *save;
6047 char *gotfree_input_line;
6048 int adjust;
6049
6050 save = input_line_pointer;
3956db08 6051 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6052 if (gotfree_input_line)
6053 input_line_pointer = gotfree_input_line;
6054
6055 expression (exp);
6056
6057 if (gotfree_input_line)
6058 {
6059 /* expression () has merrily parsed up to the end of line,
6060 or a comma - in the wrong buffer. Transfer how far
6061 input_line_pointer has moved to the right buffer. */
6062 input_line_pointer = (save
6063 + (input_line_pointer - gotfree_input_line)
6064 + adjust);
6065 free (gotfree_input_line);
3992d3b7
AM		 6066 if (exp->X_op == O_constant
6067 || exp->X_op == O_absent
6068 || exp->X_op == O_illegal
6069 || exp->X_op == O_register
6070 || exp->X_op == O_big)
6071 {
6072 char c = *input_line_pointer;
6073 *input_line_pointer = 0;
6074 as_bad (_("missing or invalid expression `%s'"), save);
6075 *input_line_pointer = c;
6076 }
f3c180ae
AM		 6077 }
6078 }
6079 else
6080 expression (exp);
ee86248c
JB		 6081
6082 intel_syntax = -intel_syntax;
6083
6084 if (intel_syntax)
6085 i386_intel_simplify (exp);
f3c180ae
AM		 6086}
6087#endif
6088
d182319b 6089static void signed_cons (int size)
6482c264 6090{
d182319b
JB		 6091 if (flag_code == CODE_64BIT)
6092 cons_sign = 1;
6093 cons (size);
6094 cons_sign = -1;
6482c264
NC		 6095}
6096
d182319b 6097#ifdef TE_PE
6482c264
NC		 6098static void
6099pe_directive_secrel (dummy)
6100 int dummy ATTRIBUTE_UNUSED;
6101{
6102 expressionS exp;
6103
6104 do
6105 {
6106 expression (&exp);
6107 if (exp.X_op == O_symbol)
6108 exp.X_op = O_secrel;
6109
6110 emit_expr (&exp, 4);
6111 }
6112 while (*input_line_pointer++ == ',');
6113
6114 input_line_pointer--;
6115 demand_empty_rest_of_line ();
6116}
6482c264
NC		 6117#endif
6118
252b5132 6119static int
70e41ade 6120i386_immediate (char *imm_start)
252b5132
RH		 6121{
6122 char *save_input_line_pointer;
f3c180ae 6123 char *gotfree_input_line;
252b5132 6124 segT exp_seg = 0;
47926f60 6125 expressionS *exp;
40fb9820
L		 6126 i386_operand_type types;
6127
0dfbf9d7 6128 operand_type_set (&types, ~0);
252b5132
RH		 6129
6130 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6131 {
31b2323c
L		 6132 as_bad (_("at most %d immediate operands are allowed"),
6133 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 6134 return 0;
6135 }
6136
6137 exp = &im_expressions[i.imm_operands++];
520dc8e8 6138 i.op[this_operand].imms = exp;
252b5132
RH		 6139
6140 if (is_space_char (*imm_start))
6141 ++imm_start;
6142
6143 save_input_line_pointer = input_line_pointer;
6144 input_line_pointer = imm_start;
6145
3956db08 6146 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6147 if (gotfree_input_line)
6148 input_line_pointer = gotfree_input_line;
252b5132
RH		 6149
6150 exp_seg = expression (exp);
6151
83183c0c 6152 SKIP_WHITESPACE ();
252b5132 6153 if (*input_line_pointer)
f3c180ae 6154 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 6155
6156 input_line_pointer = save_input_line_pointer;
f3c180ae 6157 if (gotfree_input_line)
ee86248c
JB		 6158 {
6159 free (gotfree_input_line);
6160
6161 if (exp->X_op == O_constant || exp->X_op == O_register)
6162 exp->X_op = O_illegal;
6163 }
6164
6165 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
6166}
252b5132 6167
ee86248c
JB		 6168static int
6169i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6170 i386_operand_type types, const char *imm_start)
6171{
6172 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 6173 {
3992d3b7 6174 as_bad (_("missing or invalid immediate expression `%s'"),
24eab124 6175 imm_start);
3992d3b7 6176 return 0;
252b5132 6177 }
3e73aa7c 6178 else if (exp->X_op == O_constant)
252b5132 6179 {
47926f60 6180 /* Size it properly later. */
40fb9820 6181 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 6182 /* If BFD64, sign extend val. */
4eed87de
AM		 6183 if (!use_rela_relocations
6184 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6185 exp->X_add_number
6186 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 6187 }
4c63da97 6188#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 6189 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 6190 && exp_seg != absolute_section
47926f60 6191 && exp_seg != text_section
24eab124
AM		 6192 && exp_seg != data_section
6193 && exp_seg != bss_section
6194 && exp_seg != undefined_section
f86103b7 6195 && !bfd_is_com_section (exp_seg))
252b5132 6196 {
d0b47220 6197 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 6198 return 0;
6199 }
6200#endif
bb8f5920
L		 6201 else if (!intel_syntax && exp->X_op == O_register)
6202 {
6203 as_bad (_("illegal immediate register operand %s"), imm_start);
6204 return 0;
6205 }
252b5132
RH		 6206 else
6207 {
6208 /* This is an address. The size of the address will be
24eab124 6209 determined later, depending on destination register,
3e73aa7c 6210 suffix, or the default for the section. */
40fb9820
L		 6211 i.types[this_operand].bitfield.imm8 = 1;
6212 i.types[this_operand].bitfield.imm16 = 1;
6213 i.types[this_operand].bitfield.imm32 = 1;
6214 i.types[this_operand].bitfield.imm32s = 1;
6215 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 6216 i.types[this_operand] = operand_type_and (i.types[this_operand],
6217 types);
252b5132
RH		 6218 }
6219
6220 return 1;
6221}
6222
551c1ca1 6223static char *
e3bb37b5 6224i386_scale (char *scale)
252b5132 6225{
551c1ca1
AM		 6226 offsetT val;
6227 char *save = input_line_pointer;
252b5132 6228
551c1ca1
AM		 6229 input_line_pointer = scale;
6230 val = get_absolute_expression ();
6231
6232 switch (val)
252b5132 6233 {
551c1ca1 6234 case 1:
252b5132
RH		 6235 i.log2_scale_factor = 0;
6236 break;
551c1ca1 6237 case 2:
252b5132
RH		 6238 i.log2_scale_factor = 1;
6239 break;
551c1ca1 6240 case 4:
252b5132
RH		 6241 i.log2_scale_factor = 2;
6242 break;
551c1ca1 6243 case 8:
252b5132
RH		 6244 i.log2_scale_factor = 3;
6245 break;
6246 default:
a724f0f4
JB		 6247 {
6248 char sep = *input_line_pointer;
6249
6250 *input_line_pointer = '\0';
6251 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6252 scale);
6253 *input_line_pointer = sep;
6254 input_line_pointer = save;
6255 return NULL;
6256 }
252b5132 6257 }
29b0f896 6258 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 6259 {
6260 as_warn (_("scale factor of %d without an index register"),
24eab124 6261 1 << i.log2_scale_factor);
252b5132 6262 i.log2_scale_factor = 0;
252b5132 6263 }
551c1ca1
AM		 6264 scale = input_line_pointer;
6265 input_line_pointer = save;
6266 return scale;
252b5132
RH		 6267}
6268
252b5132 6269static int
e3bb37b5 6270i386_displacement (char *disp_start, char *disp_end)
252b5132 6271{
29b0f896 6272 expressionS *exp;
252b5132
RH		 6273 segT exp_seg = 0;
6274 char *save_input_line_pointer;
f3c180ae 6275 char *gotfree_input_line;
40fb9820
L		 6276 int override;
6277 i386_operand_type bigdisp, types = anydisp;
3992d3b7 6278 int ret;
252b5132 6279
31b2323c
L		 6280 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6281 {
6282 as_bad (_("at most %d displacement operands are allowed"),
6283 MAX_MEMORY_OPERANDS);
6284 return 0;
6285 }
6286
0dfbf9d7 6287 operand_type_set (&bigdisp, 0);
40fb9820
L		 6288 if ((i.types[this_operand].bitfield.jumpabsolute)
6289 || (!current_templates->start->opcode_modifier.jump
6290 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 6291 {
40fb9820 6292 bigdisp.bitfield.disp32 = 1;
e05278af 6293 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 6294 if (flag_code == CODE_64BIT)
6295 {
6296 if (!override)
6297 {
6298 bigdisp.bitfield.disp32s = 1;
6299 bigdisp.bitfield.disp64 = 1;
6300 }
6301 }
6302 else if ((flag_code == CODE_16BIT) ^ override)
6303 {
6304 bigdisp.bitfield.disp32 = 0;
6305 bigdisp.bitfield.disp16 = 1;
6306 }
e05278af
JB		 6307 }
6308 else
6309 {
6310 /* For PC-relative branches, the width of the displacement
6311 is dependent upon data size, not address size. */
e05278af 6312 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 6313 if (flag_code == CODE_64BIT)
6314 {
6315 if (override || i.suffix == WORD_MNEM_SUFFIX)
6316 bigdisp.bitfield.disp16 = 1;
6317 else
6318 {
6319 bigdisp.bitfield.disp32 = 1;
6320 bigdisp.bitfield.disp32s = 1;
6321 }
6322 }
6323 else
e05278af
JB		 6324 {
6325 if (!override)
6326 override = (i.suffix == (flag_code != CODE_16BIT
6327 ? WORD_MNEM_SUFFIX
6328 : LONG_MNEM_SUFFIX));
40fb9820
L		 6329 bigdisp.bitfield.disp32 = 1;
6330 if ((flag_code == CODE_16BIT) ^ override)
6331 {
6332 bigdisp.bitfield.disp32 = 0;
6333 bigdisp.bitfield.disp16 = 1;
6334 }
e05278af 6335 }
e05278af 6336 }
c6fb90c8
L		 6337 i.types[this_operand] = operand_type_or (i.types[this_operand],
6338 bigdisp);
252b5132
RH		 6339
6340 exp = &disp_expressions[i.disp_operands];
520dc8e8 6341 i.op[this_operand].disps = exp;
252b5132
RH		 6342 i.disp_operands++;
6343 save_input_line_pointer = input_line_pointer;
6344 input_line_pointer = disp_start;
6345 END_STRING_AND_SAVE (disp_end);
6346
6347#ifndef GCC_ASM_O_HACK
6348#define GCC_ASM_O_HACK 0
6349#endif
6350#if GCC_ASM_O_HACK
6351 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 6352 if (i.types[this_operand].bitfield.baseIndex
24eab124 6353 && displacement_string_end[-1] == '+')
252b5132
RH		 6354 {
6355 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 6356 constraint within gcc asm statements.
6357 For instance:
6358
6359 #define _set_tssldt_desc(n,addr,limit,type) \
6360 __asm__ __volatile__ ( \
6361 "movw %w2,%0\n\t" \
6362 "movw %w1,2+%0\n\t" \
6363 "rorl $16,%1\n\t" \
6364 "movb %b1,4+%0\n\t" \
6365 "movb %4,5+%0\n\t" \
6366 "movb $0,6+%0\n\t" \
6367 "movb %h1,7+%0\n\t" \
6368 "rorl $16,%1" \
6369 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6370
6371 This works great except that the output assembler ends
6372 up looking a bit weird if it turns out that there is
6373 no offset. You end up producing code that looks like:
6374
6375 #APP
6376 movw $235,(%eax)
6377 movw %dx,2+(%eax)
6378 rorl $16,%edx
6379 movb %dl,4+(%eax)
6380 movb $137,5+(%eax)
6381 movb $0,6+(%eax)
6382 movb %dh,7+(%eax)
6383 rorl $16,%edx
6384 #NO_APP
6385
47926f60 6386 So here we provide the missing zero. */
24eab124
AM		 6387
6388 *displacement_string_end = '0';
252b5132
RH		 6389 }
6390#endif
3956db08 6391 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6392 if (gotfree_input_line)
6393 input_line_pointer = gotfree_input_line;
252b5132 6394
24eab124 6395 exp_seg = expression (exp);
252b5132 6396
636c26b0
AM		 6397 SKIP_WHITESPACE ();
6398 if (*input_line_pointer)
6399 as_bad (_("junk `%s' after expression"), input_line_pointer);
6400#if GCC_ASM_O_HACK
6401 RESTORE_END_STRING (disp_end + 1);
6402#endif
636c26b0 6403 input_line_pointer = save_input_line_pointer;
636c26b0 6404 if (gotfree_input_line)
ee86248c
JB		 6405 {
6406 free (gotfree_input_line);
6407
6408 if (exp->X_op == O_constant || exp->X_op == O_register)
6409 exp->X_op = O_illegal;
6410 }
6411
6412 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
6413
6414 RESTORE_END_STRING (disp_end);
6415
6416 return ret;
6417}
6418
6419static int
6420i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6421 i386_operand_type types, const char *disp_start)
6422{
6423 i386_operand_type bigdisp;
6424 int ret = 1;
636c26b0 6425
24eab124
AM		 6426 /* We do this to make sure that the section symbol is in
6427 the symbol table. We will ultimately change the relocation
47926f60 6428 to be relative to the beginning of the section. */
1ae12ab7 6429 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 6430 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6431 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 6432 {
636c26b0 6433 if (exp->X_op != O_symbol)
3992d3b7 6434 goto inv_disp;
636c26b0 6435
e5cb08ac 6436 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 6437 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6438 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 6439 exp->X_op = O_subtract;
6440 exp->X_op_symbol = GOT_symbol;
1ae12ab7 6441 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 6442 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 6443 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6444 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 6445 else
29b0f896 6446 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 6447 }
252b5132 6448
3992d3b7
AM		 6449 else if (exp->X_op == O_absent
6450 || exp->X_op == O_illegal
ee86248c 6451 || exp->X_op == O_big)
2daf4fd8 6452 {
3992d3b7
AM		 6453 inv_disp:
6454 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 6455 disp_start);
3992d3b7 6456 ret = 0;
2daf4fd8
AM		 6457 }
6458
4c63da97 6459#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 6460 else if (exp->X_op != O_constant
6461 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6462 && exp_seg != absolute_section
6463 && exp_seg != text_section
6464 && exp_seg != data_section
6465 && exp_seg != bss_section
6466 && exp_seg != undefined_section
6467 && !bfd_is_com_section (exp_seg))
24eab124 6468 {
d0b47220 6469 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 6470 ret = 0;
24eab124 6471 }
252b5132 6472#endif
3956db08 6473
40fb9820
L		 6474 /* Check if this is a displacement only operand. */
6475 bigdisp = i.types[this_operand];
6476 bigdisp.bitfield.disp8 = 0;
6477 bigdisp.bitfield.disp16 = 0;
6478 bigdisp.bitfield.disp32 = 0;
6479 bigdisp.bitfield.disp32s = 0;
6480 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 6481 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 6482 i.types[this_operand] = operand_type_and (i.types[this_operand],
6483 types);
3956db08 6484
3992d3b7 6485 return ret;
252b5132
RH		 6486}
6487
eecb386c 6488/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 6489 Return 1 on success, 0 on a failure. */
6490
252b5132 6491static int
e3bb37b5 6492i386_index_check (const char *operand_string)
252b5132 6493{
3e73aa7c 6494 int ok;
fc0763e6 6495 const char *kind = "base/index";
24eab124 6496#if INFER_ADDR_PREFIX
eecb386c
AM		 6497 int fudged = 0;
6498
24eab124
AM		 6499 tryprefix:
6500#endif
3e73aa7c 6501 ok = 1;
fc0763e6
JB		 6502 if (current_templates->start->opcode_modifier.isstring
6503 && !current_templates->start->opcode_modifier.immext
6504 && (current_templates->end[-1].opcode_modifier.isstring
6505 || i.mem_operands))
6506 {
6507 /* Memory operands of string insns are special in that they only allow
6508 a single register (rDI, rSI, or rBX) as their memory address. */
6509 unsigned int expected;
6510
6511 kind = "string address";
6512
6513 if (current_templates->start->opcode_modifier.w)
6514 {
6515 i386_operand_type type = current_templates->end[-1].operand_types[0];
6516
6517 if (!type.bitfield.baseindex
6518 || ((!i.mem_operands != !intel_syntax)
6519 && current_templates->end[-1].operand_types[1]
6520 .bitfield.baseindex))
6521 type = current_templates->end[-1].operand_types[1];
6522 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
6523 }
6524 else
6525 expected = 3 /* rBX */;
6526
6527 if (!i.base_reg || i.index_reg
6528 || operand_type_check (i.types[this_operand], disp))
6529 ok = -1;
6530 else if (!(flag_code == CODE_64BIT
6531 ? i.prefix[ADDR_PREFIX]
6532 ? i.base_reg->reg_type.bitfield.reg32
6533 : i.base_reg->reg_type.bitfield.reg64
6534 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6535 ? i.base_reg->reg_type.bitfield.reg32
6536 : i.base_reg->reg_type.bitfield.reg16))
6537 ok = 0;
6538 else if (i.base_reg->reg_num != expected)
6539 ok = -1;
6540
6541 if (ok < 0)
6542 {
6543 unsigned int j;
6544
6545 for (j = 0; j < i386_regtab_size; ++j)
6546 if ((flag_code == CODE_64BIT
6547 ? i.prefix[ADDR_PREFIX]
6548 ? i386_regtab[j].reg_type.bitfield.reg32
6549 : i386_regtab[j].reg_type.bitfield.reg64
6550 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6551 ? i386_regtab[j].reg_type.bitfield.reg32
6552 : i386_regtab[j].reg_type.bitfield.reg16)
6553 && i386_regtab[j].reg_num == expected)
6554 break;
9c2799c2 6555 gas_assert (j < i386_regtab_size);
fc0763e6
JB		 6556 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6557 operand_string,
6558 intel_syntax ? '[' : '(',
6559 register_prefix,
6560 i386_regtab[j].reg_name,
6561 intel_syntax ? ']' : ')');
6562 ok = 1;
6563 }
6564 }
6565 else if (flag_code == CODE_64BIT)
64e74474 6566 {
64e74474 6567 if ((i.base_reg
40fb9820
L		 6568 && ((i.prefix[ADDR_PREFIX] == 0
6569 && !i.base_reg->reg_type.bitfield.reg64)
6570 || (i.prefix[ADDR_PREFIX]
6571 && !i.base_reg->reg_type.bitfield.reg32))
6572 && (i.index_reg
9a04903e
JB		 6573 || i.base_reg->reg_num !=
6574 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 6575 || (i.index_reg
40fb9820
L		 6576 && (!i.index_reg->reg_type.bitfield.baseindex
6577 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 6578 && i.index_reg->reg_num != RegRiz
6579 && !i.index_reg->reg_type.bitfield.reg64
6580 )
40fb9820 6581 || (i.prefix[ADDR_PREFIX]
db51cc60 6582 && i.index_reg->reg_num != RegEiz
40fb9820 6583 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 6584 ok = 0;
3e73aa7c
JH		 6585 }
6586 else
6587 {
6588 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6589 {
6590 /* 16bit checks. */
6591 if ((i.base_reg
40fb9820
L		 6592 && (!i.base_reg->reg_type.bitfield.reg16
6593 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 6594 || (i.index_reg
40fb9820
L		 6595 && (!i.index_reg->reg_type.bitfield.reg16
6596 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 6597 || !(i.base_reg
6598 && i.base_reg->reg_num < 6
6599 && i.index_reg->reg_num >= 6
6600 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 6601 ok = 0;
6602 }
6603 else
e5cb08ac 6604 {
3e73aa7c
JH		 6605 /* 32bit checks. */
6606 if ((i.base_reg
40fb9820 6607 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 6608 || (i.index_reg
db51cc60
L		 6609 && ((!i.index_reg->reg_type.bitfield.reg32
6610 && i.index_reg->reg_num != RegEiz)
40fb9820 6611 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 6612 ok = 0;
3e73aa7c
JH		 6613 }
6614 }
6615 if (!ok)
24eab124
AM		 6616 {
6617#if INFER_ADDR_PREFIX
fc0763e6 6618 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
24eab124
AM		 6619 {
6620 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6621 i.prefixes += 1;
b23bac36
AM		 6622 /* Change the size of any displacement too. At most one of
6623 Disp16 or Disp32 is set.
6624 FIXME. There doesn't seem to be any real need for separate
6625 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 6626 Removing them would probably clean up the code quite a lot. */
4eed87de 6627 if (flag_code != CODE_64BIT
40fb9820
L		 6628 && (i.types[this_operand].bitfield.disp16
6629 || i.types[this_operand].bitfield.disp32))
6630 i.types[this_operand]
c6fb90c8 6631 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 6632 fudged = 1;
24eab124
AM		 6633 goto tryprefix;
6634 }
eecb386c 6635 if (fudged)
fc0763e6
JB		 6636 as_bad (_("`%s' is not a valid %s expression"),
6637 operand_string,
6638 kind);
eecb386c 6639 else
c388dee8 6640#endif
fc0763e6 6641 as_bad (_("`%s' is not a valid %s-bit %s expression"),
eecb386c 6642 operand_string,
fc0763e6
JB		 6643 flag_code_names[i.prefix[ADDR_PREFIX]
6644 ? flag_code == CODE_32BIT
6645 ? CODE_16BIT
6646 : CODE_32BIT
6647 : flag_code],
6648 kind);
24eab124 6649 }
20f0a1fc 6650 return ok;
24eab124 6651}
252b5132 6652
fc0763e6 6653/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 6654 on error. */
252b5132 6655
252b5132 6656static int
a7619375 6657i386_att_operand (char *operand_string)
252b5132 6658{
af6bdddf
AM		 6659 const reg_entry *r;
6660 char *end_op;
24eab124 6661 char *op_string = operand_string;
252b5132 6662
24eab124 6663 if (is_space_char (*op_string))
252b5132
RH		 6664 ++op_string;
6665
24eab124 6666 /* We check for an absolute prefix (differentiating,
47926f60 6667 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 6668 if (*op_string == ABSOLUTE_PREFIX)
6669 {
6670 ++op_string;
6671 if (is_space_char (*op_string))
6672 ++op_string;
40fb9820 6673 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 6674 }
252b5132 6675
47926f60 6676 /* Check if operand is a register. */
4d1bb795 6677 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 6678 {
40fb9820
L		 6679 i386_operand_type temp;
6680
24eab124
AM		 6681 /* Check for a segment override by searching for ':' after a
6682 segment register. */
6683 op_string = end_op;
6684 if (is_space_char (*op_string))
6685 ++op_string;
40fb9820
L		 6686 if (*op_string == ':'
6687 && (r->reg_type.bitfield.sreg2
6688 || r->reg_type.bitfield.sreg3))
24eab124
AM		 6689 {
6690 switch (r->reg_num)
6691 {
6692 case 0:
6693 i.seg[i.mem_operands] = &es;
6694 break;
6695 case 1:
6696 i.seg[i.mem_operands] = &cs;
6697 break;
6698 case 2:
6699 i.seg[i.mem_operands] = &ss;
6700 break;
6701 case 3:
6702 i.seg[i.mem_operands] = &ds;
6703 break;
6704 case 4:
6705 i.seg[i.mem_operands] = &fs;
6706 break;
6707 case 5:
6708 i.seg[i.mem_operands] = &gs;
6709 break;
6710 }
252b5132 6711
24eab124 6712 /* Skip the ':' and whitespace. */
252b5132
RH		 6713 ++op_string;
6714 if (is_space_char (*op_string))
24eab124 6715 ++op_string;
252b5132 6716
24eab124
AM		 6717 if (!is_digit_char (*op_string)
6718 && !is_identifier_char (*op_string)
6719 && *op_string != '('
6720 && *op_string != ABSOLUTE_PREFIX)
6721 {
6722 as_bad (_("bad memory operand `%s'"), op_string);
6723 return 0;
6724 }
47926f60 6725 /* Handle case of %es:*foo. */
24eab124
AM		 6726 if (*op_string == ABSOLUTE_PREFIX)
6727 {
6728 ++op_string;
6729 if (is_space_char (*op_string))
6730 ++op_string;
40fb9820 6731 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 6732 }
6733 goto do_memory_reference;
6734 }
6735 if (*op_string)
6736 {
d0b47220 6737 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 6738 return 0;
6739 }
40fb9820
L		 6740 temp = r->reg_type;
6741 temp.bitfield.baseindex = 0;
c6fb90c8
L		 6742 i.types[this_operand] = operand_type_or (i.types[this_operand],
6743 temp);
7d5e4556 6744 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 6745 i.op[this_operand].regs = r;
24eab124
AM		 6746 i.reg_operands++;
6747 }
af6bdddf
AM		 6748 else if (*op_string == REGISTER_PREFIX)
6749 {
6750 as_bad (_("bad register name `%s'"), op_string);
6751 return 0;
6752 }
24eab124 6753 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 6754 {
24eab124 6755 ++op_string;
40fb9820 6756 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 6757 {
d0b47220 6758 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 6759 return 0;
6760 }
6761 if (!i386_immediate (op_string))
6762 return 0;
6763 }
6764 else if (is_digit_char (*op_string)
6765 || is_identifier_char (*op_string)
e5cb08ac 6766 || *op_string == '(')
24eab124 6767 {
47926f60 6768 /* This is a memory reference of some sort. */
af6bdddf 6769 char *base_string;
252b5132 6770
47926f60 6771 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 6772 char *displacement_string_start;
6773 char *displacement_string_end;
252b5132 6774
24eab124 6775 do_memory_reference:
24eab124 6776 if ((i.mem_operands == 1
40fb9820 6777 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 6778 || i.mem_operands == 2)
6779 {
6780 as_bad (_("too many memory references for `%s'"),
6781 current_templates->start->name);
6782 return 0;
6783 }
252b5132 6784
24eab124
AM		 6785 /* Check for base index form. We detect the base index form by
6786 looking for an ')' at the end of the operand, searching
6787 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6788 after the '('. */
af6bdddf 6789 base_string = op_string + strlen (op_string);
c3332e24 6790
af6bdddf
AM		 6791 --base_string;
6792 if (is_space_char (*base_string))
6793 --base_string;
252b5132 6794
47926f60 6795 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 6796 displacement_string_start = op_string;
6797 displacement_string_end = base_string + 1;
252b5132 6798
24eab124
AM		 6799 if (*base_string == ')')
6800 {
af6bdddf 6801 char *temp_string;
24eab124
AM		 6802 unsigned int parens_balanced = 1;
6803 /* We've already checked that the number of left & right ()'s are
47926f60 6804 equal, so this loop will not be infinite. */
24eab124
AM		 6805 do
6806 {
6807 base_string--;
6808 if (*base_string == ')')
6809 parens_balanced++;
6810 if (*base_string == '(')
6811 parens_balanced--;
6812 }
6813 while (parens_balanced);
c3332e24 6814
af6bdddf 6815 temp_string = base_string;
c3332e24 6816
24eab124 6817 /* Skip past '(' and whitespace. */
252b5132
RH		 6818 ++base_string;
6819 if (is_space_char (*base_string))
24eab124 6820 ++base_string;
252b5132 6821
af6bdddf 6822 if (*base_string == ','
4eed87de
AM		 6823 || ((i.base_reg = parse_register (base_string, &end_op))
6824 != NULL))
252b5132 6825 {
af6bdddf 6826 displacement_string_end = temp_string;
252b5132 6827
40fb9820 6828 i.types[this_operand].bitfield.baseindex = 1;
252b5132 6829
af6bdddf 6830 if (i.base_reg)
24eab124 6831 {
24eab124
AM		 6832 base_string = end_op;
6833 if (is_space_char (*base_string))
6834 ++base_string;
af6bdddf
AM		 6835 }
6836
6837 /* There may be an index reg or scale factor here. */
6838 if (*base_string == ',')
6839 {
6840 ++base_string;
6841 if (is_space_char (*base_string))
6842 ++base_string;
6843
4eed87de
AM		 6844 if ((i.index_reg = parse_register (base_string, &end_op))
6845 != NULL)
24eab124 6846 {
af6bdddf 6847 base_string = end_op;
24eab124
AM		 6848 if (is_space_char (*base_string))
6849 ++base_string;
af6bdddf
AM		 6850 if (*base_string == ',')
6851 {
6852 ++base_string;
6853 if (is_space_char (*base_string))
6854 ++base_string;
6855 }
e5cb08ac 6856 else if (*base_string != ')')
af6bdddf 6857 {
4eed87de
AM		 6858 as_bad (_("expecting `,' or `)' "
6859 "after index register in `%s'"),
af6bdddf
AM		 6860 operand_string);
6861 return 0;
6862 }
24eab124 6863 }
af6bdddf 6864 else if (*base_string == REGISTER_PREFIX)
24eab124 6865 {
af6bdddf 6866 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 6867 return 0;
6868 }
252b5132 6869
47926f60 6870 /* Check for scale factor. */
551c1ca1 6871 if (*base_string != ')')
af6bdddf 6872 {
551c1ca1
AM		 6873 char *end_scale = i386_scale (base_string);
6874
6875 if (!end_scale)
af6bdddf 6876 return 0;
24eab124 6877
551c1ca1 6878 base_string = end_scale;
af6bdddf
AM		 6879 if (is_space_char (*base_string))
6880 ++base_string;
6881 if (*base_string != ')')
6882 {
4eed87de
AM		 6883 as_bad (_("expecting `)' "
6884 "after scale factor in `%s'"),
af6bdddf
AM		 6885 operand_string);
6886 return 0;
6887 }
6888 }
6889 else if (!i.index_reg)
24eab124 6890 {
4eed87de
AM		 6891 as_bad (_("expecting index register or scale factor "
6892 "after `,'; got '%c'"),
af6bdddf 6893 *base_string);
24eab124
AM		 6894 return 0;
6895 }
6896 }
af6bdddf 6897 else if (*base_string != ')')
24eab124 6898 {
4eed87de
AM		 6899 as_bad (_("expecting `,' or `)' "
6900 "after base register in `%s'"),
af6bdddf 6901 operand_string);
24eab124
AM		 6902 return 0;
6903 }
c3332e24 6904 }
af6bdddf 6905 else if (*base_string == REGISTER_PREFIX)
c3332e24 6906 {
af6bdddf 6907 as_bad (_("bad register name `%s'"), base_string);
24eab124 6908 return 0;
c3332e24 6909 }
24eab124
AM		 6910 }
6911
6912 /* If there's an expression beginning the operand, parse it,
6913 assuming displacement_string_start and
6914 displacement_string_end are meaningful. */
6915 if (displacement_string_start != displacement_string_end)
6916 {
6917 if (!i386_displacement (displacement_string_start,
6918 displacement_string_end))
6919 return 0;
6920 }
6921
6922 /* Special case for (%dx) while doing input/output op. */
6923 if (i.base_reg
0dfbf9d7
L		 6924 && operand_type_equal (&i.base_reg->reg_type,
6925 &reg16_inoutportreg)
24eab124
AM		 6926 && i.index_reg == 0
6927 && i.log2_scale_factor == 0
6928 && i.seg[i.mem_operands] == 0
40fb9820 6929 && !operand_type_check (i.types[this_operand], disp))
24eab124 6930 {
65da13b5 6931 i.types[this_operand] = inoutportreg;
24eab124
AM		 6932 return 1;
6933 }
6934
eecb386c
AM		 6935 if (i386_index_check (operand_string) == 0)
6936 return 0;
5c07affc 6937 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 6938 i.mem_operands++;
6939 }
6940 else
ce8a8b2f
AM		 6941 {
6942 /* It's not a memory operand; argh! */
24eab124
AM		 6943 as_bad (_("invalid char %s beginning operand %d `%s'"),
6944 output_invalid (*op_string),
6945 this_operand + 1,
6946 op_string);
6947 return 0;
6948 }
47926f60 6949 return 1; /* Normal return. */
252b5132
RH		 6950}
6951\f
ee7fcc42
AM		 6952/* md_estimate_size_before_relax()
6953
6954 Called just before relax() for rs_machine_dependent frags. The x86
6955 assembler uses these frags to handle variable size jump
6956 instructions.
6957
6958 Any symbol that is now undefined will not become defined.
6959 Return the correct fr_subtype in the frag.
6960 Return the initial "guess for variable size of frag" to caller.
6961 The guess is actually the growth beyond the fixed part. Whatever
6962 we do to grow the fixed or variable part contributes to our
6963 returned value. */
6964
252b5132
RH		 6965int
6966md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 6967 fragS *fragP;
6968 segT segment;
252b5132 6969{
252b5132 6970 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 6971 check for un-relaxable symbols. On an ELF system, we can't relax
6972 an externally visible symbol, because it may be overridden by a
6973 shared library. */
6974 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 6975#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6976 || (IS_ELF
31312f95 6977 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 6978 || S_IS_WEAK (fragP->fr_symbol)
6979 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
6980 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 6981#endif
6982#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 6983 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 6984 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 6985#endif
6986 )
252b5132 6987 {
b98ef147
AM		 6988 /* Symbol is undefined in this segment, or we need to keep a
6989 reloc so that weak symbols can be overridden. */
6990 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 6991 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 6992 unsigned char *opcode;
6993 int old_fr_fix;
f6af82bd 6994
ee7fcc42
AM		 6995 if (fragP->fr_var != NO_RELOC)
6996 reloc_type = fragP->fr_var;
b98ef147 6997 else if (size == 2)
f6af82bd
AM		 6998 reloc_type = BFD_RELOC_16_PCREL;
6999 else
7000 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7001
ee7fcc42
AM		 7002 old_fr_fix = fragP->fr_fix;
7003 opcode = (unsigned char *) fragP->fr_opcode;
7004
fddf5b5b 7005 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7006 {
fddf5b5b
AM		 7007 case UNCOND_JUMP:
7008 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7009 opcode[0] = 0xe9;
252b5132 7010 fragP->fr_fix += size;
062cd5e7
AS		 7011 fix_new (fragP, old_fr_fix, size,
7012 fragP->fr_symbol,
7013 fragP->fr_offset, 1,
7014 reloc_type);
252b5132
RH		 7015 break;
7016
fddf5b5b 7017 case COND_JUMP86:
412167cb
AM		 7018 if (size == 2
7019 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 7020 {
7021 /* Negate the condition, and branch past an
7022 unconditional jump. */
7023 opcode[0] ^= 1;
7024 opcode[1] = 3;
7025 /* Insert an unconditional jump. */
7026 opcode[2] = 0xe9;
7027 /* We added two extra opcode bytes, and have a two byte
7028 offset. */
7029 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7030 fix_new (fragP, old_fr_fix + 2, 2,
7031 fragP->fr_symbol,
7032 fragP->fr_offset, 1,
7033 reloc_type);
fddf5b5b
AM		 7034 break;
7035 }
7036 /* Fall through. */
7037
7038 case COND_JUMP:
412167cb
AM		 7039 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7040 {
3e02c1cc
AM		 7041 fixS *fixP;
7042
412167cb 7043 fragP->fr_fix += 1;
3e02c1cc
AM		 7044 fixP = fix_new (fragP, old_fr_fix, 1,
7045 fragP->fr_symbol,
7046 fragP->fr_offset, 1,
7047 BFD_RELOC_8_PCREL);
7048 fixP->fx_signed = 1;
412167cb
AM		 7049 break;
7050 }
93c2a809 7051
24eab124 7052 /* This changes the byte-displacement jump 0x7N
fddf5b5b 7053 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 7054 opcode[1] = opcode[0] + 0x10;
f6af82bd 7055 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 7056 /* We've added an opcode byte. */
7057 fragP->fr_fix += 1 + size;
062cd5e7
AS		 7058 fix_new (fragP, old_fr_fix + 1, size,
7059 fragP->fr_symbol,
7060 fragP->fr_offset, 1,
7061 reloc_type);
252b5132 7062 break;
fddf5b5b
AM		 7063
7064 default:
7065 BAD_CASE (fragP->fr_subtype);
7066 break;
252b5132
RH		 7067 }
7068 frag_wane (fragP);
ee7fcc42 7069 return fragP->fr_fix - old_fr_fix;
252b5132 7070 }
93c2a809 7071
93c2a809
AM		 7072 /* Guess size depending on current relax state. Initially the relax
7073 state will correspond to a short jump and we return 1, because
7074 the variable part of the frag (the branch offset) is one byte
7075 long. However, we can relax a section more than once and in that
7076 case we must either set fr_subtype back to the unrelaxed state,
7077 or return the value for the appropriate branch. */
7078 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 7079}
7080
47926f60
KH		 7081/* Called after relax() is finished.
7082
7083 In: Address of frag.
7084 fr_type == rs_machine_dependent.
7085 fr_subtype is what the address relaxed to.
7086
7087 Out: Any fixSs and constants are set up.
7088 Caller will turn frag into a ".space 0". */
7089
252b5132
RH		 7090void
7091md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 7092 bfd *abfd ATTRIBUTE_UNUSED;
7093 segT sec ATTRIBUTE_UNUSED;
29b0f896 7094 fragS *fragP;
252b5132 7095{
29b0f896 7096 unsigned char *opcode;
252b5132 7097 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 7098 offsetT target_address;
7099 offsetT opcode_address;
252b5132 7100 unsigned int extension = 0;
847f7ad4 7101 offsetT displacement_from_opcode_start;
252b5132
RH		 7102
7103 opcode = (unsigned char *) fragP->fr_opcode;
7104
47926f60 7105 /* Address we want to reach in file space. */
252b5132 7106 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 7107
47926f60 7108 /* Address opcode resides at in file space. */
252b5132
RH		 7109 opcode_address = fragP->fr_address + fragP->fr_fix;
7110
47926f60 7111 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 7112 displacement_from_opcode_start = target_address - opcode_address;
7113
fddf5b5b 7114 if ((fragP->fr_subtype & BIG) == 0)
252b5132 7115 {
47926f60
KH		 7116 /* Don't have to change opcode. */
7117 extension = 1; /* 1 opcode + 1 displacement */
252b5132 7118 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 7119 }
7120 else
7121 {
7122 if (no_cond_jump_promotion
7123 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 7124 as_warn_where (fragP->fr_file, fragP->fr_line,
7125 _("long jump required"));
252b5132 7126
fddf5b5b
AM		 7127 switch (fragP->fr_subtype)
7128 {
7129 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7130 extension = 4; /* 1 opcode + 4 displacement */
7131 opcode[0] = 0xe9;
7132 where_to_put_displacement = &opcode[1];
7133 break;
252b5132 7134
fddf5b5b
AM		 7135 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7136 extension = 2; /* 1 opcode + 2 displacement */
7137 opcode[0] = 0xe9;
7138 where_to_put_displacement = &opcode[1];
7139 break;
252b5132 7140
fddf5b5b
AM		 7141 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7142 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7143 extension = 5; /* 2 opcode + 4 displacement */
7144 opcode[1] = opcode[0] + 0x10;
7145 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7146 where_to_put_displacement = &opcode[2];
7147 break;
252b5132 7148
fddf5b5b
AM		 7149 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7150 extension = 3; /* 2 opcode + 2 displacement */
7151 opcode[1] = opcode[0] + 0x10;
7152 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7153 where_to_put_displacement = &opcode[2];
7154 break;
252b5132 7155
fddf5b5b
AM		 7156 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7157 extension = 4;
7158 opcode[0] ^= 1;
7159 opcode[1] = 3;
7160 opcode[2] = 0xe9;
7161 where_to_put_displacement = &opcode[3];
7162 break;
7163
7164 default:
7165 BAD_CASE (fragP->fr_subtype);
7166 break;
7167 }
252b5132 7168 }
fddf5b5b 7169
7b81dfbb
AJ		 7170 /* If size if less then four we are sure that the operand fits,
7171 but if it's 4, then it could be that the displacement is larger
7172 then -/+ 2GB. */
7173 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7174 && object_64bit
7175 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 7176 + ((addressT) 1 << 31))
7177 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 7178 {
7179 as_bad_where (fragP->fr_file, fragP->fr_line,
7180 _("jump target out of range"));
7181 /* Make us emit 0. */
7182 displacement_from_opcode_start = extension;
7183 }
47926f60 7184 /* Now put displacement after opcode. */
252b5132
RH		 7185 md_number_to_chars ((char *) where_to_put_displacement,
7186 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 7187 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 7188 fragP->fr_fix += extension;
7189}
7190\f
252b5132
RH		 7191/* Apply a fixup (fixS) to segment data, once it has been determined
7192 by our caller that we have all the info we need to fix it up.
7193
7194 On the 386, immediates, displacements, and data pointers are all in
7195 the same (little-endian) format, so we don't need to care about which
7196 we are handling. */
7197
94f592af 7198void
55cf6793 7199md_apply_fix (fixP, valP, seg)
47926f60
KH		 7200 /* The fix we're to put in. */
7201 fixS *fixP;
47926f60 7202 /* Pointer to the value of the bits. */
c6682705 7203 valueT *valP;
47926f60
KH		 7204 /* Segment fix is from. */
7205 segT seg ATTRIBUTE_UNUSED;
252b5132 7206{
94f592af 7207 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 7208 valueT value = *valP;
252b5132 7209
f86103b7 7210#if !defined (TE_Mach)
93382f6d
AM		 7211 if (fixP->fx_pcrel)
7212 {
7213 switch (fixP->fx_r_type)
7214 {
5865bb77
ILT		 7215 default:
7216 break;
7217
d6ab8113
JB		 7218 case BFD_RELOC_64:
7219 fixP->fx_r_type = BFD_RELOC_64_PCREL;
7220 break;
93382f6d 7221 case BFD_RELOC_32:
ae8887b5 7222 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 7223 fixP->fx_r_type = BFD_RELOC_32_PCREL;
7224 break;
7225 case BFD_RELOC_16:
7226 fixP->fx_r_type = BFD_RELOC_16_PCREL;
7227 break;
7228 case BFD_RELOC_8:
7229 fixP->fx_r_type = BFD_RELOC_8_PCREL;
7230 break;
7231 }
7232 }
252b5132 7233
a161fe53 7234 if (fixP->fx_addsy != NULL
31312f95 7235 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 7236 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 7237 || fixP->fx_r_type == BFD_RELOC_16_PCREL
7238 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7239 && !use_rela_relocations)
252b5132 7240 {
31312f95
AM		 7241 /* This is a hack. There should be a better way to handle this.
7242 This covers for the fact that bfd_install_relocation will
7243 subtract the current location (for partial_inplace, PC relative
7244 relocations); see more below. */
252b5132 7245#ifndef OBJ_AOUT
718ddfc0 7246 if (IS_ELF
252b5132
RH		 7247#ifdef TE_PE
7248 || OUTPUT_FLAVOR == bfd_target_coff_flavour
7249#endif
7250 )
7251 value += fixP->fx_where + fixP->fx_frag->fr_address;
7252#endif
7253#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7254 if (IS_ELF)
252b5132 7255 {
6539b54b 7256 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 7257
6539b54b 7258 if ((sym_seg == seg
2f66722d 7259 || (symbol_section_p (fixP->fx_addsy)
6539b54b 7260 && sym_seg != absolute_section))
c25bc9fc 7261 && !TC_FORCE_RELOCATION (fixP))
2f66722d
AM		 7262 {
7263 /* Yes, we add the values in twice. This is because
6539b54b
AM		 7264 bfd_install_relocation subtracts them out again. I think
7265 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 7266 it. FIXME. */
7267 value += fixP->fx_where + fixP->fx_frag->fr_address;
7268 }
252b5132
RH		 7269 }
7270#endif
7271#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 7272 /* For some reason, the PE format does not store a
7273 section address offset for a PC relative symbol. */
7274 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 7275 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 7276 value += md_pcrel_from (fixP);
7277#endif
7278 }
fbeb56a4
DK		 7279#if defined (OBJ_COFF) && defined (TE_PE)
7280 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7281 {
7282 value -= S_GET_VALUE (fixP->fx_addsy);
7283 }
7284#endif
252b5132
RH		 7285
7286 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 7287 and we must not disappoint it. */
252b5132 7288#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7289 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 7290 switch (fixP->fx_r_type)
7291 {
7292 case BFD_RELOC_386_PLT32:
3e73aa7c 7293 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 7294 /* Make the jump instruction point to the address of the operand. At
7295 runtime we merely add the offset to the actual PLT entry. */
7296 value = -4;
7297 break;
31312f95 7298
13ae64f3
JJ		 7299 case BFD_RELOC_386_TLS_GD:
7300 case BFD_RELOC_386_TLS_LDM:
13ae64f3 7301 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7302 case BFD_RELOC_386_TLS_IE:
7303 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 7304 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 7305 case BFD_RELOC_X86_64_TLSGD:
7306 case BFD_RELOC_X86_64_TLSLD:
7307 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 7308 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 7309 value = 0; /* Fully resolved at runtime. No addend. */
7310 /* Fallthrough */
7311 case BFD_RELOC_386_TLS_LE:
7312 case BFD_RELOC_386_TLS_LDO_32:
7313 case BFD_RELOC_386_TLS_LE_32:
7314 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7315 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 7316 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 7317 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 7318 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7319 break;
7320
67a4f2b7
AO		 7321 case BFD_RELOC_386_TLS_DESC_CALL:
7322 case BFD_RELOC_X86_64_TLSDESC_CALL:
7323 value = 0; /* Fully resolved at runtime. No addend. */
7324 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7325 fixP->fx_done = 0;
7326 return;
7327
00f7efb6
JJ		 7328 case BFD_RELOC_386_GOT32:
7329 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 7330 value = 0; /* Fully resolved at runtime. No addend. */
7331 break;
47926f60
KH		 7332
7333 case BFD_RELOC_VTABLE_INHERIT:
7334 case BFD_RELOC_VTABLE_ENTRY:
7335 fixP->fx_done = 0;
94f592af 7336 return;
47926f60
KH		 7337
7338 default:
7339 break;
7340 }
7341#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 7342 *valP = value;
f86103b7 7343#endif /* !defined (TE_Mach) */
3e73aa7c 7344
3e73aa7c 7345 /* Are we finished with this relocation now? */
c6682705 7346 if (fixP->fx_addsy == NULL)
3e73aa7c 7347 fixP->fx_done = 1;
fbeb56a4
DK		 7348#if defined (OBJ_COFF) && defined (TE_PE)
7349 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7350 {
7351 fixP->fx_done = 0;
7352 /* Remember value for tc_gen_reloc. */
7353 fixP->fx_addnumber = value;
7354 /* Clear out the frag for now. */
7355 value = 0;
7356 }
7357#endif
3e73aa7c
JH		 7358 else if (use_rela_relocations)
7359 {
7360 fixP->fx_no_overflow = 1;
062cd5e7
AS		 7361 /* Remember value for tc_gen_reloc. */
7362 fixP->fx_addnumber = value;
3e73aa7c
JH		 7363 value = 0;
7364 }
f86103b7 7365
94f592af 7366 md_number_to_chars (p, value, fixP->fx_size);
252b5132 7367}
252b5132 7368\f
252b5132 7369char *
499ac353 7370md_atof (int type, char *litP, int *sizeP)
252b5132 7371{
499ac353
NC		 7372 /* This outputs the LITTLENUMs in REVERSE order;
7373 in accord with the bigendian 386. */
7374 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 7375}
7376\f
2d545b82 7377static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 7378
252b5132 7379static char *
e3bb37b5 7380output_invalid (int c)
252b5132 7381{
3882b010 7382 if (ISPRINT (c))
f9f21a03
L		 7383 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7384 "'%c'", c);
252b5132 7385 else
f9f21a03 7386 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 7387 "(0x%x)", (unsigned char) c);
252b5132
RH		 7388 return output_invalid_buf;
7389}
7390
af6bdddf 7391/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 7392
7393static const reg_entry *
4d1bb795 7394parse_real_register (char *reg_string, char **end_op)
252b5132 7395{
af6bdddf
AM		 7396 char *s = reg_string;
7397 char *p;
252b5132
RH		 7398 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7399 const reg_entry *r;
7400
7401 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7402 if (*s == REGISTER_PREFIX)
7403 ++s;
7404
7405 if (is_space_char (*s))
7406 ++s;
7407
7408 p = reg_name_given;
af6bdddf 7409 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 7410 {
7411 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 7412 return (const reg_entry *) NULL;
7413 s++;
252b5132
RH		 7414 }
7415
6588847e
DN		 7416 /* For naked regs, make sure that we are not dealing with an identifier.
7417 This prevents confusing an identifier like `eax_var' with register
7418 `eax'. */
7419 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7420 return (const reg_entry *) NULL;
7421
af6bdddf 7422 *end_op = s;
252b5132
RH		 7423
7424 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7425
5f47d35b 7426 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 7427 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 7428 {
5f47d35b
AM		 7429 if (is_space_char (*s))
7430 ++s;
7431 if (*s == '(')
7432 {
af6bdddf 7433 ++s;
5f47d35b
AM		 7434 if (is_space_char (*s))
7435 ++s;
7436 if (*s >= '0' && *s <= '7')
7437 {
db557034 7438 int fpr = *s - '0';
af6bdddf 7439 ++s;
5f47d35b
AM		 7440 if (is_space_char (*s))
7441 ++s;
7442 if (*s == ')')
7443 {
7444 *end_op = s + 1;
db557034
AM		 7445 r = hash_find (reg_hash, "st(0)");
7446 know (r);
7447 return r + fpr;
5f47d35b 7448 }
5f47d35b 7449 }
47926f60 7450 /* We have "%st(" then garbage. */
5f47d35b
AM		 7451 return (const reg_entry *) NULL;
7452 }
7453 }
7454
a60de03c
JB		 7455 if (r == NULL || allow_pseudo_reg)
7456 return r;
7457
0dfbf9d7 7458 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 7459 return (const reg_entry *) NULL;
7460
192dc9c6
JB		 7461 if ((r->reg_type.bitfield.reg32
7462 || r->reg_type.bitfield.sreg3
7463 || r->reg_type.bitfield.control
7464 || r->reg_type.bitfield.debug
7465 || r->reg_type.bitfield.test)
7466 && !cpu_arch_flags.bitfield.cpui386)
7467 return (const reg_entry *) NULL;
7468
7469 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
7470 return (const reg_entry *) NULL;
7471
7472 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
7473 return (const reg_entry *) NULL;
7474
40f12533
L		 7475 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
7476 return (const reg_entry *) NULL;
7477
db51cc60 7478 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 7479 if (!allow_index_reg
db51cc60
L		 7480 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7481 return (const reg_entry *) NULL;
7482
a60de03c
JB		 7483 if (((r->reg_flags & (RegRex64 | RegRex))
7484 || r->reg_type.bitfield.reg64)
40fb9820 7485 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 7486 || !operand_type_equal (&r->reg_type, &control))
1ae00879 7487 && flag_code != CODE_64BIT)
20f0a1fc 7488 return (const reg_entry *) NULL;
1ae00879 7489
b7240065
JB		 7490 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7491 return (const reg_entry *) NULL;
7492
252b5132
RH		 7493 return r;
7494}
4d1bb795
JB		 7495
7496/* REG_STRING starts *before* REGISTER_PREFIX. */
7497
7498static const reg_entry *
7499parse_register (char *reg_string, char **end_op)
7500{
7501 const reg_entry *r;
7502
7503 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7504 r = parse_real_register (reg_string, end_op);
7505 else
7506 r = NULL;
7507 if (!r)
7508 {
7509 char *save = input_line_pointer;
7510 char c;
7511 symbolS *symbolP;
7512
7513 input_line_pointer = reg_string;
7514 c = get_symbol_end ();
7515 symbolP = symbol_find (reg_string);
7516 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7517 {
7518 const expressionS *e = symbol_get_value_expression (symbolP);
7519
7520 know (e->X_op == O_register);
4eed87de 7521 know (e->X_add_number >= 0
c3fe08fa 7522 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 7523 r = i386_regtab + e->X_add_number;
7524 *end_op = input_line_pointer;
7525 }
7526 *input_line_pointer = c;
7527 input_line_pointer = save;
7528 }
7529 return r;
7530}
7531
7532int
7533i386_parse_name (char *name, expressionS *e, char *nextcharP)
7534{
7535 const reg_entry *r;
7536 char *end = input_line_pointer;
7537
7538 *end = *nextcharP;
7539 r = parse_register (name, &input_line_pointer);
7540 if (r && end <= input_line_pointer)
7541 {
7542 *nextcharP = *input_line_pointer;
7543 *input_line_pointer = 0;
7544 e->X_op = O_register;
7545 e->X_add_number = r - i386_regtab;
7546 return 1;
7547 }
7548 input_line_pointer = end;
7549 *end = 0;
ee86248c 7550 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 7551}
7552
7553void
7554md_operand (expressionS *e)
7555{
ee86248c
JB		 7556 char *end;
7557 const reg_entry *r;
4d1bb795 7558
ee86248c
JB		 7559 switch (*input_line_pointer)
7560 {
7561 case REGISTER_PREFIX:
7562 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 7563 if (r)
7564 {
7565 e->X_op = O_register;
7566 e->X_add_number = r - i386_regtab;
7567 input_line_pointer = end;
7568 }
ee86248c
JB		 7569 break;
7570
7571 case '[':
9c2799c2 7572 gas_assert (intel_syntax);
ee86248c
JB		 7573 end = input_line_pointer++;
7574 expression (e);
7575 if (*input_line_pointer == ']')
7576 {
7577 ++input_line_pointer;
7578 e->X_op_symbol = make_expr_symbol (e);
7579 e->X_add_symbol = NULL;
7580 e->X_add_number = 0;
7581 e->X_op = O_index;
7582 }
7583 else
7584 {
7585 e->X_op = O_absent;
7586 input_line_pointer = end;
7587 }
7588 break;
4d1bb795
JB		 7589 }
7590}
7591
252b5132 7592\f
4cc782b5 7593#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 7594const char *md_shortopts = "kVQ:sqn";
252b5132 7595#else
12b55ccc 7596const char *md_shortopts = "qn";
252b5132 7597#endif
6e0b89ee 7598
3e73aa7c 7599#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 7600#define OPTION_64 (OPTION_MD_BASE + 1)
7601#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 7602#define OPTION_MARCH (OPTION_MD_BASE + 3)
7603#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 7604#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7605#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7606#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7607#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7608#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 7609#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 7610#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
b3b91714 7611
99ad8390
NC		 7612struct option md_longopts[] =
7613{
3e73aa7c 7614 {"32", no_argument, NULL, OPTION_32},
321098a5
L		 7615#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7616 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c 7617 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 7618#endif
b3b91714 7619 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 7620 {"march", required_argument, NULL, OPTION_MARCH},
7621 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 7622 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
7623 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
7624 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
7625 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
7626 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 7627 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 7628 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
252b5132
RH		 7629 {NULL, no_argument, NULL, 0}
7630};
7631size_t md_longopts_size = sizeof (md_longopts);
7632
7633int
9103f4f4 7634md_parse_option (int c, char *arg)
252b5132 7635{
9103f4f4 7636 unsigned int i;
6305a203 7637 char *arch, *next;
9103f4f4 7638
252b5132
RH		 7639 switch (c)
7640 {
12b55ccc
L		 7641 case 'n':
7642 optimize_align_code = 0;
7643 break;
7644
a38cf1db
AM		 7645 case 'q':
7646 quiet_warnings = 1;
252b5132
RH		 7647 break;
7648
7649#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 7650 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7651 should be emitted or not. FIXME: Not implemented. */
7652 case 'Q':
252b5132
RH		 7653 break;
7654
7655 /* -V: SVR4 argument to print version ID. */
7656 case 'V':
7657 print_version_id ();
7658 break;
7659
a38cf1db
AM		 7660 /* -k: Ignore for FreeBSD compatibility. */
7661 case 'k':
252b5132 7662 break;
4cc782b5
ILT		 7663
7664 case 's':
7665 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 7666 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 7667 break;
99ad8390 7668#endif
321098a5
L		 7669#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7670 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c
JH		 7671 case OPTION_64:
7672 {
7673 const char **list, **l;
7674
3e73aa7c
JH		 7675 list = bfd_target_list ();
7676 for (l = list; *l != NULL; l++)
8620418b 7677 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 7678 || strcmp (*l, "coff-x86-64") == 0
7679 || strcmp (*l, "pe-x86-64") == 0
7680 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 7681 {
7682 default_arch = "x86_64";
7683 break;
7684 }
3e73aa7c 7685 if (*l == NULL)
6e0b89ee 7686 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 7687 free (list);
7688 }
7689 break;
7690#endif
252b5132 7691
6e0b89ee
AM		 7692 case OPTION_32:
7693 default_arch = "i386";
7694 break;
7695
b3b91714
AM		 7696 case OPTION_DIVIDE:
7697#ifdef SVR4_COMMENT_CHARS
7698 {
7699 char *n, *t;
7700 const char *s;
7701
7702 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7703 t = n;
7704 for (s = i386_comment_chars; *s != '\0'; s++)
7705 if (*s != '/')
7706 *t++ = *s;
7707 *t = '\0';
7708 i386_comment_chars = n;
7709 }
7710#endif
7711 break;
7712
9103f4f4 7713 case OPTION_MARCH:
6305a203
L		 7714 arch = xstrdup (arg);
7715 do
9103f4f4 7716 {
6305a203
L		 7717 if (*arch == '.')
7718 as_fatal (_("Invalid -march= option: `%s'"), arg);
7719 next = strchr (arch, '+');
7720 if (next)
7721 *next++ = '\0';
7722 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
9103f4f4 7723 {
6305a203 7724 if (strcmp (arch, cpu_arch [i].name) == 0)
ccc9c027 7725 {
6305a203
L		 7726 /* Processor. */
7727 cpu_arch_name = cpu_arch[i].name;
7728 cpu_sub_arch_name = NULL;
7729 cpu_arch_flags = cpu_arch[i].flags;
7730 cpu_arch_isa = cpu_arch[i].type;
7731 cpu_arch_isa_flags = cpu_arch[i].flags;
7732 if (!cpu_arch_tune_set)
7733 {
7734 cpu_arch_tune = cpu_arch_isa;
7735 cpu_arch_tune_flags = cpu_arch_isa_flags;
7736 }
7737 break;
7738 }
7739 else if (*cpu_arch [i].name == '.'
7740 && strcmp (arch, cpu_arch [i].name + 1) == 0)
7741 {
7742 /* ISA entension. */
7743 i386_cpu_flags flags;
7744 flags = cpu_flags_or (cpu_arch_flags,
7745 cpu_arch[i].flags);
0dfbf9d7 7746 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 7747 {
7748 if (cpu_sub_arch_name)
7749 {
7750 char *name = cpu_sub_arch_name;
7751 cpu_sub_arch_name = concat (name,
7752 cpu_arch[i].name,
1bf57e9f 7753 (const char *) NULL);
6305a203
L		 7754 free (name);
7755 }
7756 else
7757 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
7758 cpu_arch_flags = flags;
7759 }
7760 break;
ccc9c027 7761 }
9103f4f4 7762 }
6305a203
L		 7763
7764 if (i >= ARRAY_SIZE (cpu_arch))
7765 as_fatal (_("Invalid -march= option: `%s'"), arg);
7766
7767 arch = next;
9103f4f4 7768 }
6305a203 7769 while (next != NULL );
9103f4f4
L		 7770 break;
7771
7772 case OPTION_MTUNE:
7773 if (*arg == '.')
7774 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7775 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7776 {
7777 if (strcmp (arg, cpu_arch [i].name) == 0)
7778 {
ccc9c027 7779 cpu_arch_tune_set = 1;
9103f4f4
L		 7780 cpu_arch_tune = cpu_arch [i].type;
7781 cpu_arch_tune_flags = cpu_arch[i].flags;
7782 break;
7783 }
7784 }
7785 if (i >= ARRAY_SIZE (cpu_arch))
7786 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7787 break;
7788
1efbbeb4
L		 7789 case OPTION_MMNEMONIC:
7790 if (strcasecmp (arg, "att") == 0)
7791 intel_mnemonic = 0;
7792 else if (strcasecmp (arg, "intel") == 0)
7793 intel_mnemonic = 1;
7794 else
7795 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
7796 break;
7797
7798 case OPTION_MSYNTAX:
7799 if (strcasecmp (arg, "att") == 0)
7800 intel_syntax = 0;
7801 else if (strcasecmp (arg, "intel") == 0)
7802 intel_syntax = 1;
7803 else
7804 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
7805 break;
7806
7807 case OPTION_MINDEX_REG:
7808 allow_index_reg = 1;
7809 break;
7810
7811 case OPTION_MNAKED_REG:
7812 allow_naked_reg = 1;
7813 break;
7814
7815 case OPTION_MOLD_GCC:
7816 old_gcc = 1;
1efbbeb4
L		 7817 break;
7818
c0f3af97
L		 7819 case OPTION_MSSE2AVX:
7820 sse2avx = 1;
7821 break;
7822
daf50ae7
L		 7823 case OPTION_MSSE_CHECK:
7824 if (strcasecmp (arg, "error") == 0)
7825 sse_check = sse_check_error;
7826 else if (strcasecmp (arg, "warning") == 0)
7827 sse_check = sse_check_warning;
7828 else if (strcasecmp (arg, "none") == 0)
7829 sse_check = sse_check_none;
7830 else
7831 as_fatal (_("Invalid -msse-check= option: `%s'"), arg);
7832 break;
7833
252b5132
RH		 7834 default:
7835 return 0;
7836 }
7837 return 1;
7838}
7839
7840void
7841md_show_usage (stream)
7842 FILE *stream;
7843{
4cc782b5
ILT		 7844#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7845 fprintf (stream, _("\
a38cf1db
AM		 7846 -Q ignored\n\
7847 -V print assembler version number\n\
b3b91714
AM		 7848 -k ignored\n"));
7849#endif
7850 fprintf (stream, _("\
12b55ccc 7851 -n Do not optimize code alignment\n\
b3b91714
AM		 7852 -q quieten some warnings\n"));
7853#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7854 fprintf (stream, _("\
a38cf1db 7855 -s ignored\n"));
b3b91714 7856#endif
321098a5
L		 7857#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7858 || defined (TE_PE) || defined (TE_PEP))
751d281c
L		 7859 fprintf (stream, _("\
7860 --32/--64 generate 32bit/64bit code\n"));
7861#endif
b3b91714
AM		 7862#ifdef SVR4_COMMENT_CHARS
7863 fprintf (stream, _("\
7864 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 7865#else
7866 fprintf (stream, _("\
b3b91714 7867 --divide ignored\n"));
4cc782b5 7868#endif
9103f4f4 7869 fprintf (stream, _("\
6305a203
L		 7870 -march=CPU[,+EXTENSION...]\n\
7871 generate code for CPU and EXTENSION, CPU is one of:\n\
2cb4f3d5
L		 7872 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
7873 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
bd5295b2 7874 core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
2cb4f3d5 7875 generic32, generic64\n\
599121aa
L		 7876 EXTENSION is combination of:\n\
7877 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
f1f8f695 7878 avx, vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
bd5295b2 7879 clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\
922d8de8 7880 svme, abm, padlock, fma4\n"));
6305a203 7881 fprintf (stream, _("\
2cb4f3d5
L		 7882 -mtune=CPU optimize for CPU, CPU is one of:\n\
7883 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
7884 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
bd5295b2 7885 core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
2cb4f3d5 7886 generic32, generic64\n"));
ba104c83 7887 fprintf (stream, _("\
c0f3af97
L		 7888 -msse2avx encode SSE instructions with VEX prefix\n"));
7889 fprintf (stream, _("\
daf50ae7
L		 7890 -msse-check=[none|error|warning]\n\
7891 check SSE instructions\n"));
7892 fprintf (stream, _("\
ba104c83
L		 7893 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
7894 fprintf (stream, _("\
7895 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
7896 fprintf (stream, _("\
7897 -mindex-reg support pseudo index registers\n"));
7898 fprintf (stream, _("\
7899 -mnaked-reg don't require `%%' prefix for registers\n"));
7900 fprintf (stream, _("\
7901 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 7902}
7903
3e73aa7c 7904#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 7905 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 7906 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 7907
7908/* Pick the target format to use. */
7909
47926f60 7910const char *
e3bb37b5 7911i386_target_format (void)
252b5132 7912{
3e73aa7c 7913 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 7914 {
7915 set_code_flag (CODE_64BIT);
0dfbf9d7 7916 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 7917 {
7918 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7919 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7920 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7921 cpu_arch_isa_flags.bitfield.cpui486 = 1;
7922 cpu_arch_isa_flags.bitfield.cpui586 = 1;
7923 cpu_arch_isa_flags.bitfield.cpui686 = 1;
bd5295b2 7924 cpu_arch_isa_flags.bitfield.cpuclflush = 1;
40fb9820 7925 cpu_arch_isa_flags.bitfield.cpummx= 1;
40fb9820
L		 7926 cpu_arch_isa_flags.bitfield.cpusse = 1;
7927 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
7928 }
0dfbf9d7 7929 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 7930 {
7931 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7932 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7933 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7934 cpu_arch_tune_flags.bitfield.cpui486 = 1;
7935 cpu_arch_tune_flags.bitfield.cpui586 = 1;
7936 cpu_arch_tune_flags.bitfield.cpui686 = 1;
bd5295b2 7937 cpu_arch_tune_flags.bitfield.cpuclflush = 1;
40fb9820 7938 cpu_arch_tune_flags.bitfield.cpummx= 1;
40fb9820
L		 7939 cpu_arch_tune_flags.bitfield.cpusse = 1;
7940 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
7941 }
9103f4f4 7942 }
3e73aa7c 7943 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 7944 {
7945 set_code_flag (CODE_32BIT);
0dfbf9d7 7946 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 7947 {
7948 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7949 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7950 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7951 }
0dfbf9d7 7952 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 7953 {
7954 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7955 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7956 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7957 }
9103f4f4 7958 }
3e73aa7c
JH		 7959 else
7960 as_fatal (_("Unknown architecture"));
252b5132
RH		 7961 switch (OUTPUT_FLAVOR)
7962 {
321098a5 7963#if defined (TE_PE) || defined (TE_PEP)
872ce6ff 7964 case bfd_target_coff_flavour:
321098a5 7965 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
872ce6ff 7966#endif
4c63da97
AM		 7967#ifdef OBJ_MAYBE_AOUT
7968 case bfd_target_aout_flavour:
47926f60 7969 return AOUT_TARGET_FORMAT;
4c63da97
AM		 7970#endif
7971#ifdef OBJ_MAYBE_COFF
252b5132
RH		 7972 case bfd_target_coff_flavour:
7973 return "coff-i386";
4c63da97 7974#endif
3e73aa7c 7975#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 7976 case bfd_target_elf_flavour:
3e73aa7c 7977 {
e5cb08ac 7978 if (flag_code == CODE_64BIT)
4fa24527
JB		 7979 {
7980 object_64bit = 1;
7981 use_rela_relocations = 1;
7982 }
9d7cbccd 7983 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 7984 }
e57f8c65
TG		 7985#endif
7986#if defined (OBJ_MACH_O)
7987 case bfd_target_mach_o_flavour:
7988 return flag_code == CODE_64BIT ? "mach-o-x86-64" : "mach-o-i386";
4c63da97 7989#endif
252b5132
RH		 7990 default:
7991 abort ();
7992 return NULL;
7993 }
7994}
7995
47926f60 7996#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 7997
7998#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 7999void
8000i386_elf_emit_arch_note (void)
a847613f 8001{
718ddfc0 8002 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 8003 {
8004 char *p;
8005 asection *seg = now_seg;
8006 subsegT subseg = now_subseg;
8007 Elf_Internal_Note i_note;
8008 Elf_External_Note e_note;
8009 asection *note_secp;
8010 int len;
8011
8012 /* Create the .note section. */
8013 note_secp = subseg_new (".note", 0);
8014 bfd_set_section_flags (stdoutput,
8015 note_secp,
8016 SEC_HAS_CONTENTS | SEC_READONLY);
8017
8018 /* Process the arch string. */
8019 len = strlen (cpu_arch_name);
8020
8021 i_note.namesz = len + 1;
8022 i_note.descsz = 0;
8023 i_note.type = NT_ARCH;
8024 p = frag_more (sizeof (e_note.namesz));
8025 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8026 p = frag_more (sizeof (e_note.descsz));
8027 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8028 p = frag_more (sizeof (e_note.type));
8029 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8030 p = frag_more (len + 1);
8031 strcpy (p, cpu_arch_name);
8032
8033 frag_align (2, 0, 0);
8034
8035 subseg_set (seg, subseg);
8036 }
8037}
8038#endif
252b5132 8039\f
252b5132
RH		 8040symbolS *
8041md_undefined_symbol (name)
8042 char *name;
8043{
18dc2407
ILT		 8044 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8045 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8046 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8047 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 8048 {
8049 if (!GOT_symbol)
8050 {
8051 if (symbol_find (name))
8052 as_bad (_("GOT already in symbol table"));
8053 GOT_symbol = symbol_new (name, undefined_section,
8054 (valueT) 0, &zero_address_frag);
8055 };
8056 return GOT_symbol;
8057 }
252b5132
RH		 8058 return 0;
8059}
8060
8061/* Round up a section size to the appropriate boundary. */
47926f60 8062
252b5132
RH		 8063valueT
8064md_section_align (segment, size)
ab9da554 8065 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 8066 valueT size;
8067{
4c63da97
AM		 8068#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8069 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8070 {
8071 /* For a.out, force the section size to be aligned. If we don't do
8072 this, BFD will align it for us, but it will not write out the
8073 final bytes of the section. This may be a bug in BFD, but it is
8074 easier to fix it here since that is how the other a.out targets
8075 work. */
8076 int align;
8077
8078 align = bfd_get_section_alignment (stdoutput, segment);
8079 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8080 }
252b5132
RH		 8081#endif
8082
8083 return size;
8084}
8085
8086/* On the i386, PC-relative offsets are relative to the start of the
8087 next instruction. That is, the address of the offset, plus its
8088 size, since the offset is always the last part of the insn. */
8089
8090long
e3bb37b5 8091md_pcrel_from (fixS *fixP)
252b5132
RH		 8092{
8093 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8094}
8095
8096#ifndef I386COFF
8097
8098static void
e3bb37b5 8099s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 8100{
29b0f896 8101 int temp;
252b5132 8102
8a75718c
JB		 8103#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8104 if (IS_ELF)
8105 obj_elf_section_change_hook ();
8106#endif
252b5132
RH		 8107 temp = get_absolute_expression ();
8108 subseg_set (bss_section, (subsegT) temp);
8109 demand_empty_rest_of_line ();
8110}
8111
8112#endif
8113
252b5132 8114void
e3bb37b5 8115i386_validate_fix (fixS *fixp)
252b5132
RH		 8116{
8117 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8118 {
23df1078
JH		 8119 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8120 {
4fa24527 8121 if (!object_64bit)
23df1078
JH		 8122 abort ();
8123 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8124 }
8125 else
8126 {
4fa24527 8127 if (!object_64bit)
d6ab8113
JB		 8128 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8129 else
8130 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 8131 }
252b5132
RH		 8132 fixp->fx_subsy = 0;
8133 }
8134}
8135
252b5132
RH		 8136arelent *
8137tc_gen_reloc (section, fixp)
ab9da554 8138 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 8139 fixS *fixp;
8140{
8141 arelent *rel;
8142 bfd_reloc_code_real_type code;
8143
8144 switch (fixp->fx_r_type)
8145 {
3e73aa7c
JH		 8146 case BFD_RELOC_X86_64_PLT32:
8147 case BFD_RELOC_X86_64_GOT32:
8148 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 8149 case BFD_RELOC_386_PLT32:
8150 case BFD_RELOC_386_GOT32:
8151 case BFD_RELOC_386_GOTOFF:
8152 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 8153 case BFD_RELOC_386_TLS_GD:
8154 case BFD_RELOC_386_TLS_LDM:
8155 case BFD_RELOC_386_TLS_LDO_32:
8156 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8157 case BFD_RELOC_386_TLS_IE:
8158 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 8159 case BFD_RELOC_386_TLS_LE_32:
8160 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 8161 case BFD_RELOC_386_TLS_GOTDESC:
8162 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 8163 case BFD_RELOC_X86_64_TLSGD:
8164 case BFD_RELOC_X86_64_TLSLD:
8165 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8166 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 8167 case BFD_RELOC_X86_64_GOTTPOFF:
8168 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 8169 case BFD_RELOC_X86_64_TPOFF64:
8170 case BFD_RELOC_X86_64_GOTOFF64:
8171 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 8172 case BFD_RELOC_X86_64_GOT64:
8173 case BFD_RELOC_X86_64_GOTPCREL64:
8174 case BFD_RELOC_X86_64_GOTPC64:
8175 case BFD_RELOC_X86_64_GOTPLT64:
8176 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 8177 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8178 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 8179 case BFD_RELOC_RVA:
8180 case BFD_RELOC_VTABLE_ENTRY:
8181 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 8182#ifdef TE_PE
8183 case BFD_RELOC_32_SECREL:
8184#endif
252b5132
RH		 8185 code = fixp->fx_r_type;
8186 break;
dbbaec26
L		 8187 case BFD_RELOC_X86_64_32S:
8188 if (!fixp->fx_pcrel)
8189 {
8190 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8191 code = fixp->fx_r_type;
8192 break;
8193 }
252b5132 8194 default:
93382f6d 8195 if (fixp->fx_pcrel)
252b5132 8196 {
93382f6d
AM		 8197 switch (fixp->fx_size)
8198 {
8199 default:
b091f402
AM		 8200 as_bad_where (fixp->fx_file, fixp->fx_line,
8201 _("can not do %d byte pc-relative relocation"),
8202 fixp->fx_size);
93382f6d
AM		 8203 code = BFD_RELOC_32_PCREL;
8204 break;
8205 case 1: code = BFD_RELOC_8_PCREL; break;
8206 case 2: code = BFD_RELOC_16_PCREL; break;
8207 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 8208#ifdef BFD64
8209 case 8: code = BFD_RELOC_64_PCREL; break;
8210#endif
93382f6d
AM		 8211 }
8212 }
8213 else
8214 {
8215 switch (fixp->fx_size)
8216 {
8217 default:
b091f402
AM		 8218 as_bad_where (fixp->fx_file, fixp->fx_line,
8219 _("can not do %d byte relocation"),
8220 fixp->fx_size);
93382f6d
AM		 8221 code = BFD_RELOC_32;
8222 break;
8223 case 1: code = BFD_RELOC_8; break;
8224 case 2: code = BFD_RELOC_16; break;
8225 case 4: code = BFD_RELOC_32; break;
937149dd 8226#ifdef BFD64
3e73aa7c 8227 case 8: code = BFD_RELOC_64; break;
937149dd 8228#endif
93382f6d 8229 }
252b5132
RH		 8230 }
8231 break;
8232 }
252b5132 8233
d182319b
JB		 8234 if ((code == BFD_RELOC_32
8235 || code == BFD_RELOC_32_PCREL
8236 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 8237 && GOT_symbol
8238 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 8239 {
4fa24527 8240 if (!object_64bit)
d6ab8113
JB		 8241 code = BFD_RELOC_386_GOTPC;
8242 else
8243 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 8244 }
7b81dfbb
AJ		 8245 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
8246 && GOT_symbol
8247 && fixp->fx_addsy == GOT_symbol)
8248 {
8249 code = BFD_RELOC_X86_64_GOTPC64;
8250 }
252b5132
RH		 8251
8252 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 8253 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
8254 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 8255
8256 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 8257
3e73aa7c
JH		 8258 if (!use_rela_relocations)
8259 {
8260 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8261 vtable entry to be used in the relocation's section offset. */
8262 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8263 rel->address = fixp->fx_offset;
fbeb56a4
DK		 8264#if defined (OBJ_COFF) && defined (TE_PE)
8265 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
8266 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
8267 else
8268#endif
c6682705 8269 rel->addend = 0;
3e73aa7c
JH		 8270 }
8271 /* Use the rela in 64bit mode. */
252b5132 8272 else
3e73aa7c 8273 {
062cd5e7
AS		 8274 if (!fixp->fx_pcrel)
8275 rel->addend = fixp->fx_offset;
8276 else
8277 switch (code)
8278 {
8279 case BFD_RELOC_X86_64_PLT32:
8280 case BFD_RELOC_X86_64_GOT32:
8281 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 8282 case BFD_RELOC_X86_64_TLSGD:
8283 case BFD_RELOC_X86_64_TLSLD:
8284 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 8285 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8286 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 8287 rel->addend = fixp->fx_offset - fixp->fx_size;
8288 break;
8289 default:
8290 rel->addend = (section->vma
8291 - fixp->fx_size
8292 + fixp->fx_addnumber
8293 + md_pcrel_from (fixp));
8294 break;
8295 }
3e73aa7c
JH		 8296 }
8297
252b5132
RH		 8298 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
8299 if (rel->howto == NULL)
8300 {
8301 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 8302 _("cannot represent relocation type %s"),
252b5132
RH		 8303 bfd_get_reloc_code_name (code));
8304 /* Set howto to a garbage value so that we can keep going. */
8305 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 8306 gas_assert (rel->howto != NULL);
252b5132
RH		 8307 }
8308
8309 return rel;
8310}
8311
ee86248c 8312#include "tc-i386-intel.c"
54cfded0 8313
a60de03c
JB		 8314void
8315tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 8316{
a60de03c
JB		 8317 int saved_naked_reg;
8318 char saved_register_dot;
54cfded0 8319
a60de03c
JB		 8320 saved_naked_reg = allow_naked_reg;
8321 allow_naked_reg = 1;
8322 saved_register_dot = register_chars['.'];
8323 register_chars['.'] = '.';
8324 allow_pseudo_reg = 1;
8325 expression_and_evaluate (exp);
8326 allow_pseudo_reg = 0;
8327 register_chars['.'] = saved_register_dot;
8328 allow_naked_reg = saved_naked_reg;
8329
8330 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 8331 {
a60de03c
JB		 8332 if ((addressT) exp->X_add_number < i386_regtab_size)
8333 {
8334 exp->X_op = O_constant;
8335 exp->X_add_number = i386_regtab[exp->X_add_number]
8336 .dw2_regnum[flag_code >> 1];
8337 }
8338 else
8339 exp->X_op = O_illegal;
54cfded0 8340 }
54cfded0
AM		 8341}
8342
8343void
8344tc_x86_frame_initial_instructions (void)
8345{
a60de03c
JB		 8346 static unsigned int sp_regno[2];
8347
8348 if (!sp_regno[flag_code >> 1])
8349 {
8350 char *saved_input = input_line_pointer;
8351 char sp[][4] = {"esp", "rsp"};
8352 expressionS exp;
a4447b93 8353
a60de03c
JB		 8354 input_line_pointer = sp[flag_code >> 1];
8355 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 8356 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 8357 sp_regno[flag_code >> 1] = exp.X_add_number;
8358 input_line_pointer = saved_input;
8359 }
a4447b93 8360
a60de03c 8361 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
a4447b93 8362 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 8363}
d2b2c203
DJ		 8364
8365int
8366i386_elf_section_type (const char *str, size_t len)
8367{
8368 if (flag_code == CODE_64BIT
8369 && len == sizeof ("unwind") - 1
8370 && strncmp (str, "unwind", 6) == 0)
8371 return SHT_X86_64_UNWIND;
8372
8373 return -1;
8374}
bb41ade5 8375
ad5fec3b
EB		 8376#ifdef TE_SOLARIS
8377void
8378i386_solaris_fix_up_eh_frame (segT sec)
8379{
8380 if (flag_code == CODE_64BIT)
8381 elf_section_type (sec) = SHT_X86_64_UNWIND;
8382}
8383#endif
8384
bb41ade5
AM		 8385#ifdef TE_PE
8386void
8387tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8388{
8389 expressionS expr;
8390
8391 expr.X_op = O_secrel;
8392 expr.X_add_symbol = symbol;
8393 expr.X_add_number = 0;
8394 emit_expr (&expr, size);
8395}
8396#endif
3b22753a
L		 8397
8398#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8399/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8400
01e1a5bc 8401bfd_vma
3b22753a
L		 8402x86_64_section_letter (int letter, char **ptr_msg)
8403{
8404 if (flag_code == CODE_64BIT)
8405 {
8406 if (letter == 'l')
8407 return SHF_X86_64_LARGE;
8408
8409 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 8410 }
3b22753a 8411 else
64e74474 8412 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 8413 return -1;
8414}
8415
01e1a5bc 8416bfd_vma
3b22753a
L		 8417x86_64_section_word (char *str, size_t len)
8418{
8620418b 8419 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 8420 return SHF_X86_64_LARGE;
8421
8422 return -1;
8423}
8424
8425static void
8426handle_large_common (int small ATTRIBUTE_UNUSED)
8427{
8428 if (flag_code != CODE_64BIT)
8429 {
8430 s_comm_internal (0, elf_common_parse);
8431 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8432 }
8433 else
8434 {
8435 static segT lbss_section;
8436 asection *saved_com_section_ptr = elf_com_section_ptr;
8437 asection *saved_bss_section = bss_section;
8438
8439 if (lbss_section == NULL)
8440 {
8441 flagword applicable;
8442 segT seg = now_seg;
8443 subsegT subseg = now_subseg;
8444
8445 /* The .lbss section is for local .largecomm symbols. */
8446 lbss_section = subseg_new (".lbss", 0);
8447 applicable = bfd_applicable_section_flags (stdoutput);
8448 bfd_set_section_flags (stdoutput, lbss_section,
8449 applicable & SEC_ALLOC);
8450 seg_info (lbss_section)->bss = 1;
8451
8452 subseg_set (seg, subseg);
8453 }
8454
8455 elf_com_section_ptr = &_bfd_elf_large_com_section;
8456 bss_section = lbss_section;
8457
8458 s_comm_internal (0, elf_common_parse);
8459
8460 elf_com_section_ptr = saved_com_section_ptr;
8461 bss_section = saved_bss_section;
8462 }
8463}
8464#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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