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b534c6d3 | 1 | /* tc-i386.c -- Assemble code for the Intel 80386 |
6f2750fe | 2 | Copyright (C) 1989-2016 Free Software Foundation, Inc. |
252b5132 RH |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
19 | 02110-1301, USA. */ | |
252b5132 | 20 | |
47926f60 KH |
21 | /* Intel 80386 machine specific gas. |
22 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 23 | x86_64 support by Jan Hubicka (jh@suse.cz) |
0f10071e | 24 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
47926f60 KH |
25 | Bugs & suggestions are completely welcome. This is free software. |
26 | Please help us make it better. */ | |
252b5132 | 27 | |
252b5132 | 28 | #include "as.h" |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | #include "subsegs.h" |
316e2c05 | 31 | #include "dwarf2dbg.h" |
54cfded0 | 32 | #include "dw2gencfi.h" |
d2b2c203 | 33 | #include "elf/x86-64.h" |
40fb9820 | 34 | #include "opcodes/i386-init.h" |
252b5132 | 35 | |
252b5132 RH |
36 | #ifndef REGISTER_WARNINGS |
37 | #define REGISTER_WARNINGS 1 | |
38 | #endif | |
39 | ||
c3332e24 | 40 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 41 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
42 | #endif |
43 | ||
29b0f896 AM |
44 | #ifndef DEFAULT_ARCH |
45 | #define DEFAULT_ARCH "i386" | |
246fcdee | 46 | #endif |
252b5132 | 47 | |
edde18a5 AM |
48 | #ifndef INLINE |
49 | #if __GNUC__ >= 2 | |
50 | #define INLINE __inline__ | |
51 | #else | |
52 | #define INLINE | |
53 | #endif | |
54 | #endif | |
55 | ||
6305a203 L |
56 | /* Prefixes will be emitted in the order defined below. |
57 | WAIT_PREFIX must be the first prefix since FWAIT is really is an | |
58 | instruction, and so must come before any prefixes. | |
59 | The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, | |
42164a71 | 60 | REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */ |
6305a203 L |
61 | #define WAIT_PREFIX 0 |
62 | #define SEG_PREFIX 1 | |
63 | #define ADDR_PREFIX 2 | |
64 | #define DATA_PREFIX 3 | |
c32fa91d | 65 | #define REP_PREFIX 4 |
42164a71 | 66 | #define HLE_PREFIX REP_PREFIX |
7e8b059b | 67 | #define BND_PREFIX REP_PREFIX |
c32fa91d L |
68 | #define LOCK_PREFIX 5 |
69 | #define REX_PREFIX 6 /* must come last. */ | |
70 | #define MAX_PREFIXES 7 /* max prefixes per opcode */ | |
6305a203 L |
71 | |
72 | /* we define the syntax here (modulo base,index,scale syntax) */ | |
73 | #define REGISTER_PREFIX '%' | |
74 | #define IMMEDIATE_PREFIX '$' | |
75 | #define ABSOLUTE_PREFIX '*' | |
76 | ||
77 | /* these are the instruction mnemonic suffixes in AT&T syntax or | |
78 | memory operand size in Intel syntax. */ | |
79 | #define WORD_MNEM_SUFFIX 'w' | |
80 | #define BYTE_MNEM_SUFFIX 'b' | |
81 | #define SHORT_MNEM_SUFFIX 's' | |
82 | #define LONG_MNEM_SUFFIX 'l' | |
83 | #define QWORD_MNEM_SUFFIX 'q' | |
84 | #define XMMWORD_MNEM_SUFFIX 'x' | |
c0f3af97 | 85 | #define YMMWORD_MNEM_SUFFIX 'y' |
43234a1e | 86 | #define ZMMWORD_MNEM_SUFFIX 'z' |
6305a203 L |
87 | /* Intel Syntax. Use a non-ascii letter since since it never appears |
88 | in instructions. */ | |
89 | #define LONG_DOUBLE_MNEM_SUFFIX '\1' | |
90 | ||
91 | #define END_OF_INSN '\0' | |
92 | ||
93 | /* | |
94 | 'templates' is for grouping together 'template' structures for opcodes | |
95 | of the same name. This is only used for storing the insns in the grand | |
96 | ole hash table of insns. | |
97 | The templates themselves start at START and range up to (but not including) | |
98 | END. | |
99 | */ | |
100 | typedef struct | |
101 | { | |
d3ce72d0 NC |
102 | const insn_template *start; |
103 | const insn_template *end; | |
6305a203 L |
104 | } |
105 | templates; | |
106 | ||
107 | /* 386 operand encoding bytes: see 386 book for details of this. */ | |
108 | typedef struct | |
109 | { | |
110 | unsigned int regmem; /* codes register or memory operand */ | |
111 | unsigned int reg; /* codes register operand (or extended opcode) */ | |
112 | unsigned int mode; /* how to interpret regmem & reg */ | |
113 | } | |
114 | modrm_byte; | |
115 | ||
116 | /* x86-64 extension prefix. */ | |
117 | typedef int rex_byte; | |
118 | ||
6305a203 L |
119 | /* 386 opcode byte to code indirect addressing. */ |
120 | typedef struct | |
121 | { | |
122 | unsigned base; | |
123 | unsigned index; | |
124 | unsigned scale; | |
125 | } | |
126 | sib_byte; | |
127 | ||
6305a203 L |
128 | /* x86 arch names, types and features */ |
129 | typedef struct | |
130 | { | |
131 | const char *name; /* arch name */ | |
8a2c8fef | 132 | unsigned int len; /* arch string length */ |
6305a203 L |
133 | enum processor_type type; /* arch type */ |
134 | i386_cpu_flags flags; /* cpu feature flags */ | |
8a2c8fef | 135 | unsigned int skip; /* show_arch should skip this. */ |
6305a203 L |
136 | } |
137 | arch_entry; | |
138 | ||
293f5f65 L |
139 | /* Used to turn off indicated flags. */ |
140 | typedef struct | |
141 | { | |
142 | const char *name; /* arch name */ | |
143 | unsigned int len; /* arch string length */ | |
144 | i386_cpu_flags flags; /* cpu feature flags */ | |
145 | } | |
146 | noarch_entry; | |
147 | ||
78f12dd3 | 148 | static void update_code_flag (int, int); |
e3bb37b5 L |
149 | static void set_code_flag (int); |
150 | static void set_16bit_gcc_code_flag (int); | |
151 | static void set_intel_syntax (int); | |
1efbbeb4 | 152 | static void set_intel_mnemonic (int); |
db51cc60 | 153 | static void set_allow_index_reg (int); |
7bab8ab5 | 154 | static void set_check (int); |
e3bb37b5 | 155 | static void set_cpu_arch (int); |
6482c264 | 156 | #ifdef TE_PE |
e3bb37b5 | 157 | static void pe_directive_secrel (int); |
6482c264 | 158 | #endif |
e3bb37b5 L |
159 | static void signed_cons (int); |
160 | static char *output_invalid (int c); | |
ee86248c JB |
161 | static int i386_finalize_immediate (segT, expressionS *, i386_operand_type, |
162 | const char *); | |
163 | static int i386_finalize_displacement (segT, expressionS *, i386_operand_type, | |
164 | const char *); | |
a7619375 | 165 | static int i386_att_operand (char *); |
e3bb37b5 | 166 | static int i386_intel_operand (char *, int); |
ee86248c JB |
167 | static int i386_intel_simplify (expressionS *); |
168 | static int i386_intel_parse_name (const char *, expressionS *); | |
e3bb37b5 L |
169 | static const reg_entry *parse_register (char *, char **); |
170 | static char *parse_insn (char *, char *); | |
171 | static char *parse_operands (char *, const char *); | |
172 | static void swap_operands (void); | |
4d456e3d | 173 | static void swap_2_operands (int, int); |
e3bb37b5 L |
174 | static void optimize_imm (void); |
175 | static void optimize_disp (void); | |
d3ce72d0 | 176 | static const insn_template *match_template (void); |
e3bb37b5 L |
177 | static int check_string (void); |
178 | static int process_suffix (void); | |
179 | static int check_byte_reg (void); | |
180 | static int check_long_reg (void); | |
181 | static int check_qword_reg (void); | |
182 | static int check_word_reg (void); | |
183 | static int finalize_imm (void); | |
184 | static int process_operands (void); | |
185 | static const seg_entry *build_modrm_byte (void); | |
186 | static void output_insn (void); | |
187 | static void output_imm (fragS *, offsetT); | |
188 | static void output_disp (fragS *, offsetT); | |
29b0f896 | 189 | #ifndef I386COFF |
e3bb37b5 | 190 | static void s_bss (int); |
252b5132 | 191 | #endif |
17d4e2a2 L |
192 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
193 | static void handle_large_common (int small ATTRIBUTE_UNUSED); | |
194 | #endif | |
252b5132 | 195 | |
a847613f | 196 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 197 | |
43234a1e L |
198 | /* This struct describes rounding control and SAE in the instruction. */ |
199 | struct RC_Operation | |
200 | { | |
201 | enum rc_type | |
202 | { | |
203 | rne = 0, | |
204 | rd, | |
205 | ru, | |
206 | rz, | |
207 | saeonly | |
208 | } type; | |
209 | int operand; | |
210 | }; | |
211 | ||
212 | static struct RC_Operation rc_op; | |
213 | ||
214 | /* The struct describes masking, applied to OPERAND in the instruction. | |
215 | MASK is a pointer to the corresponding mask register. ZEROING tells | |
216 | whether merging or zeroing mask is used. */ | |
217 | struct Mask_Operation | |
218 | { | |
219 | const reg_entry *mask; | |
220 | unsigned int zeroing; | |
221 | /* The operand where this operation is associated. */ | |
222 | int operand; | |
223 | }; | |
224 | ||
225 | static struct Mask_Operation mask_op; | |
226 | ||
227 | /* The struct describes broadcasting, applied to OPERAND. FACTOR is | |
228 | broadcast factor. */ | |
229 | struct Broadcast_Operation | |
230 | { | |
231 | /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */ | |
232 | int type; | |
233 | ||
234 | /* Index of broadcasted operand. */ | |
235 | int operand; | |
236 | }; | |
237 | ||
238 | static struct Broadcast_Operation broadcast_op; | |
239 | ||
c0f3af97 L |
240 | /* VEX prefix. */ |
241 | typedef struct | |
242 | { | |
43234a1e L |
243 | /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */ |
244 | unsigned char bytes[4]; | |
c0f3af97 L |
245 | unsigned int length; |
246 | /* Destination or source register specifier. */ | |
247 | const reg_entry *register_specifier; | |
248 | } vex_prefix; | |
249 | ||
252b5132 | 250 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 251 | i386_insn. */ |
252b5132 | 252 | |
520dc8e8 AM |
253 | union i386_op |
254 | { | |
255 | expressionS *disps; | |
256 | expressionS *imms; | |
257 | const reg_entry *regs; | |
258 | }; | |
259 | ||
a65babc9 L |
260 | enum i386_error |
261 | { | |
86e026a4 | 262 | operand_size_mismatch, |
a65babc9 L |
263 | operand_type_mismatch, |
264 | register_type_mismatch, | |
265 | number_of_operands_mismatch, | |
266 | invalid_instruction_suffix, | |
267 | bad_imm4, | |
268 | old_gcc_only, | |
269 | unsupported_with_intel_mnemonic, | |
270 | unsupported_syntax, | |
6c30d220 L |
271 | unsupported, |
272 | invalid_vsib_address, | |
7bab8ab5 | 273 | invalid_vector_register_set, |
43234a1e L |
274 | unsupported_vector_index_register, |
275 | unsupported_broadcast, | |
276 | broadcast_not_on_src_operand, | |
277 | broadcast_needed, | |
278 | unsupported_masking, | |
279 | mask_not_on_destination, | |
280 | no_default_mask, | |
281 | unsupported_rc_sae, | |
282 | rc_sae_operand_not_last_imm, | |
283 | invalid_register_operand, | |
284 | try_vector_disp8 | |
a65babc9 L |
285 | }; |
286 | ||
252b5132 RH |
287 | struct _i386_insn |
288 | { | |
47926f60 | 289 | /* TM holds the template for the insn were currently assembling. */ |
d3ce72d0 | 290 | insn_template tm; |
252b5132 | 291 | |
7d5e4556 L |
292 | /* SUFFIX holds the instruction size suffix for byte, word, dword |
293 | or qword, if given. */ | |
252b5132 RH |
294 | char suffix; |
295 | ||
47926f60 | 296 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
297 | unsigned int operands; |
298 | ||
299 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
300 | of given register, displacement, memory operands and immediate | |
47926f60 | 301 | operands. */ |
252b5132 RH |
302 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
303 | ||
304 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 305 | use OP[i] for the corresponding operand. */ |
40fb9820 | 306 | i386_operand_type types[MAX_OPERANDS]; |
252b5132 | 307 | |
520dc8e8 AM |
308 | /* Displacement expression, immediate expression, or register for each |
309 | operand. */ | |
310 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 311 | |
3e73aa7c JH |
312 | /* Flags for operands. */ |
313 | unsigned int flags[MAX_OPERANDS]; | |
314 | #define Operand_PCrel 1 | |
315 | ||
252b5132 | 316 | /* Relocation type for operand */ |
f86103b7 | 317 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
252b5132 | 318 | |
252b5132 RH |
319 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
320 | the base index byte below. */ | |
321 | const reg_entry *base_reg; | |
322 | const reg_entry *index_reg; | |
323 | unsigned int log2_scale_factor; | |
324 | ||
325 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 326 | explicit segment overrides are given. */ |
ce8a8b2f | 327 | const seg_entry *seg[2]; |
252b5132 | 328 | |
8325cc63 JB |
329 | /* Copied first memory operand string, for re-checking. */ |
330 | char *memop1_string; | |
331 | ||
252b5132 RH |
332 | /* PREFIX holds all the given prefix opcodes (usually null). |
333 | PREFIXES is the number of prefix opcodes. */ | |
334 | unsigned int prefixes; | |
335 | unsigned char prefix[MAX_PREFIXES]; | |
336 | ||
337 | /* RM and SIB are the modrm byte and the sib byte where the | |
c1e679ec | 338 | addressing modes of this insn are encoded. */ |
252b5132 | 339 | modrm_byte rm; |
3e73aa7c | 340 | rex_byte rex; |
43234a1e | 341 | rex_byte vrex; |
252b5132 | 342 | sib_byte sib; |
c0f3af97 | 343 | vex_prefix vex; |
b6169b20 | 344 | |
43234a1e L |
345 | /* Masking attributes. */ |
346 | struct Mask_Operation *mask; | |
347 | ||
348 | /* Rounding control and SAE attributes. */ | |
349 | struct RC_Operation *rounding; | |
350 | ||
351 | /* Broadcasting attributes. */ | |
352 | struct Broadcast_Operation *broadcast; | |
353 | ||
354 | /* Compressed disp8*N attribute. */ | |
355 | unsigned int memshift; | |
356 | ||
b6169b20 | 357 | /* Swap operand in encoding. */ |
4473e004 | 358 | unsigned int swap_operand; |
891edac4 | 359 | |
a501d77e L |
360 | /* Prefer 8bit or 32bit displacement in encoding. */ |
361 | enum | |
362 | { | |
363 | disp_encoding_default = 0, | |
364 | disp_encoding_8bit, | |
365 | disp_encoding_32bit | |
366 | } disp_encoding; | |
f8a5c266 | 367 | |
d5de92cf L |
368 | /* REP prefix. */ |
369 | const char *rep_prefix; | |
370 | ||
165de32a L |
371 | /* HLE prefix. */ |
372 | const char *hle_prefix; | |
42164a71 | 373 | |
7e8b059b L |
374 | /* Have BND prefix. */ |
375 | const char *bnd_prefix; | |
376 | ||
43234a1e L |
377 | /* Need VREX to support upper 16 registers. */ |
378 | int need_vrex; | |
379 | ||
891edac4 | 380 | /* Error message. */ |
a65babc9 | 381 | enum i386_error error; |
252b5132 RH |
382 | }; |
383 | ||
384 | typedef struct _i386_insn i386_insn; | |
385 | ||
43234a1e L |
386 | /* Link RC type with corresponding string, that'll be looked for in |
387 | asm. */ | |
388 | struct RC_name | |
389 | { | |
390 | enum rc_type type; | |
391 | const char *name; | |
392 | unsigned int len; | |
393 | }; | |
394 | ||
395 | static const struct RC_name RC_NamesTable[] = | |
396 | { | |
397 | { rne, STRING_COMMA_LEN ("rn-sae") }, | |
398 | { rd, STRING_COMMA_LEN ("rd-sae") }, | |
399 | { ru, STRING_COMMA_LEN ("ru-sae") }, | |
400 | { rz, STRING_COMMA_LEN ("rz-sae") }, | |
401 | { saeonly, STRING_COMMA_LEN ("sae") }, | |
402 | }; | |
403 | ||
252b5132 RH |
404 | /* List of chars besides those in app.c:symbol_chars that can start an |
405 | operand. Used to prevent the scrubber eating vital white-space. */ | |
43234a1e | 406 | const char extra_symbol_chars[] = "*%-([{" |
252b5132 | 407 | #ifdef LEX_AT |
32137342 NC |
408 | "@" |
409 | #endif | |
410 | #ifdef LEX_QM | |
411 | "?" | |
252b5132 | 412 | #endif |
32137342 | 413 | ; |
252b5132 | 414 | |
29b0f896 AM |
415 | #if (defined (TE_I386AIX) \ |
416 | || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ | |
3896cfd5 | 417 | && !defined (TE_GNU) \ |
29b0f896 | 418 | && !defined (TE_LINUX) \ |
8d63c93e RM |
419 | && !defined (TE_NACL) \ |
420 | && !defined (TE_NETWARE) \ | |
29b0f896 | 421 | && !defined (TE_FreeBSD) \ |
5b806d27 | 422 | && !defined (TE_DragonFly) \ |
29b0f896 | 423 | && !defined (TE_NetBSD))) |
252b5132 | 424 | /* This array holds the chars that always start a comment. If the |
b3b91714 AM |
425 | pre-processor is disabled, these aren't very useful. The option |
426 | --divide will remove '/' from this list. */ | |
427 | const char *i386_comment_chars = "#/"; | |
428 | #define SVR4_COMMENT_CHARS 1 | |
252b5132 | 429 | #define PREFIX_SEPARATOR '\\' |
252b5132 | 430 | |
b3b91714 AM |
431 | #else |
432 | const char *i386_comment_chars = "#"; | |
433 | #define PREFIX_SEPARATOR '/' | |
434 | #endif | |
435 | ||
252b5132 RH |
436 | /* This array holds the chars that only start a comment at the beginning of |
437 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
438 | .line and .file directives will appear in the pre-processed output. |
439 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 440 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
441 | #NO_APP at the beginning of its output. |
442 | Also note that comments started like this one will always work if | |
252b5132 | 443 | '/' isn't otherwise defined. */ |
b3b91714 | 444 | const char line_comment_chars[] = "#/"; |
252b5132 | 445 | |
63a0b638 | 446 | const char line_separator_chars[] = ";"; |
252b5132 | 447 | |
ce8a8b2f AM |
448 | /* Chars that can be used to separate mant from exp in floating point |
449 | nums. */ | |
252b5132 RH |
450 | const char EXP_CHARS[] = "eE"; |
451 | ||
ce8a8b2f AM |
452 | /* Chars that mean this number is a floating point constant |
453 | As in 0f12.456 | |
454 | or 0d1.2345e12. */ | |
252b5132 RH |
455 | const char FLT_CHARS[] = "fFdDxX"; |
456 | ||
ce8a8b2f | 457 | /* Tables for lexical analysis. */ |
252b5132 RH |
458 | static char mnemonic_chars[256]; |
459 | static char register_chars[256]; | |
460 | static char operand_chars[256]; | |
461 | static char identifier_chars[256]; | |
462 | static char digit_chars[256]; | |
463 | ||
ce8a8b2f | 464 | /* Lexical macros. */ |
252b5132 RH |
465 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
466 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
467 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
468 | #define is_space_char(x) ((x) == ' ') | |
469 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
470 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
471 | ||
0234cb7c | 472 | /* All non-digit non-letter characters that may occur in an operand. */ |
252b5132 RH |
473 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
474 | ||
475 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
476 | effect this we maintain a stack of saved characters that we've smashed | |
477 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 478 | assembler instruction). */ |
252b5132 | 479 | static char save_stack[32]; |
ce8a8b2f | 480 | static char *save_stack_p; |
252b5132 RH |
481 | #define END_STRING_AND_SAVE(s) \ |
482 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
483 | #define RESTORE_END_STRING(s) \ | |
484 | do { *(s) = *--save_stack_p; } while (0) | |
485 | ||
47926f60 | 486 | /* The instruction we're assembling. */ |
252b5132 RH |
487 | static i386_insn i; |
488 | ||
489 | /* Possible templates for current insn. */ | |
490 | static const templates *current_templates; | |
491 | ||
31b2323c L |
492 | /* Per instruction expressionS buffers: max displacements & immediates. */ |
493 | static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; | |
494 | static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; | |
252b5132 | 495 | |
47926f60 | 496 | /* Current operand we are working on. */ |
ee86248c | 497 | static int this_operand = -1; |
252b5132 | 498 | |
3e73aa7c JH |
499 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
500 | these. */ | |
501 | ||
502 | enum flag_code { | |
503 | CODE_32BIT, | |
504 | CODE_16BIT, | |
505 | CODE_64BIT }; | |
506 | ||
507 | static enum flag_code flag_code; | |
4fa24527 | 508 | static unsigned int object_64bit; |
862be3fb | 509 | static unsigned int disallow_64bit_reloc; |
3e73aa7c JH |
510 | static int use_rela_relocations = 0; |
511 | ||
7af8ed2d NC |
512 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
513 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ | |
514 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) | |
515 | ||
351f65ca L |
516 | /* The ELF ABI to use. */ |
517 | enum x86_elf_abi | |
518 | { | |
519 | I386_ABI, | |
7f56bc95 L |
520 | X86_64_ABI, |
521 | X86_64_X32_ABI | |
351f65ca L |
522 | }; |
523 | ||
524 | static enum x86_elf_abi x86_elf_abi = I386_ABI; | |
7af8ed2d | 525 | #endif |
351f65ca | 526 | |
167ad85b TG |
527 | #if defined (TE_PE) || defined (TE_PEP) |
528 | /* Use big object file format. */ | |
529 | static int use_big_obj = 0; | |
530 | #endif | |
531 | ||
8dcea932 L |
532 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
533 | /* 1 if generating code for a shared library. */ | |
534 | static int shared = 0; | |
535 | #endif | |
536 | ||
47926f60 KH |
537 | /* 1 for intel syntax, |
538 | 0 if att syntax. */ | |
539 | static int intel_syntax = 0; | |
252b5132 | 540 | |
e89c5eaa L |
541 | /* 1 for Intel64 ISA, |
542 | 0 if AMD64 ISA. */ | |
543 | static int intel64; | |
544 | ||
1efbbeb4 L |
545 | /* 1 for intel mnemonic, |
546 | 0 if att mnemonic. */ | |
547 | static int intel_mnemonic = !SYSV386_COMPAT; | |
548 | ||
5209009a | 549 | /* 1 if support old (<= 2.8.1) versions of gcc. */ |
1efbbeb4 L |
550 | static int old_gcc = OLDGCC_COMPAT; |
551 | ||
a60de03c JB |
552 | /* 1 if pseudo registers are permitted. */ |
553 | static int allow_pseudo_reg = 0; | |
554 | ||
47926f60 KH |
555 | /* 1 if register prefix % not required. */ |
556 | static int allow_naked_reg = 0; | |
252b5132 | 557 | |
7e8b059b L |
558 | /* 1 if the assembler should add BND prefix for all control-tranferring |
559 | instructions supporting it, even if this prefix wasn't specified | |
560 | explicitly. */ | |
561 | static int add_bnd_prefix = 0; | |
562 | ||
ba104c83 | 563 | /* 1 if pseudo index register, eiz/riz, is allowed . */ |
db51cc60 L |
564 | static int allow_index_reg = 0; |
565 | ||
d022bddd IT |
566 | /* 1 if the assembler should ignore LOCK prefix, even if it was |
567 | specified explicitly. */ | |
568 | static int omit_lock_prefix = 0; | |
569 | ||
e4e00185 AS |
570 | /* 1 if the assembler should encode lfence, mfence, and sfence as |
571 | "lock addl $0, (%{re}sp)". */ | |
572 | static int avoid_fence = 0; | |
573 | ||
0cb4071e L |
574 | /* 1 if the assembler should generate relax relocations. */ |
575 | ||
576 | static int generate_relax_relocations | |
577 | = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS; | |
578 | ||
7bab8ab5 | 579 | static enum check_kind |
daf50ae7 | 580 | { |
7bab8ab5 JB |
581 | check_none = 0, |
582 | check_warning, | |
583 | check_error | |
daf50ae7 | 584 | } |
7bab8ab5 | 585 | sse_check, operand_check = check_warning; |
daf50ae7 | 586 | |
2ca3ace5 L |
587 | /* Register prefix used for error message. */ |
588 | static const char *register_prefix = "%"; | |
589 | ||
47926f60 KH |
590 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
591 | leave, push, and pop instructions so that gcc has the same stack | |
592 | frame as in 32 bit mode. */ | |
593 | static char stackop_size = '\0'; | |
eecb386c | 594 | |
12b55ccc L |
595 | /* Non-zero to optimize code alignment. */ |
596 | int optimize_align_code = 1; | |
597 | ||
47926f60 KH |
598 | /* Non-zero to quieten some warnings. */ |
599 | static int quiet_warnings = 0; | |
a38cf1db | 600 | |
47926f60 KH |
601 | /* CPU name. */ |
602 | static const char *cpu_arch_name = NULL; | |
6305a203 | 603 | static char *cpu_sub_arch_name = NULL; |
a38cf1db | 604 | |
47926f60 | 605 | /* CPU feature flags. */ |
40fb9820 L |
606 | static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; |
607 | ||
ccc9c027 L |
608 | /* If we have selected a cpu we are generating instructions for. */ |
609 | static int cpu_arch_tune_set = 0; | |
610 | ||
9103f4f4 | 611 | /* Cpu we are generating instructions for. */ |
fbf3f584 | 612 | enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; |
9103f4f4 L |
613 | |
614 | /* CPU feature flags of cpu we are generating instructions for. */ | |
40fb9820 | 615 | static i386_cpu_flags cpu_arch_tune_flags; |
9103f4f4 | 616 | |
ccc9c027 | 617 | /* CPU instruction set architecture used. */ |
fbf3f584 | 618 | enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; |
ccc9c027 | 619 | |
9103f4f4 | 620 | /* CPU feature flags of instruction set architecture used. */ |
fbf3f584 | 621 | i386_cpu_flags cpu_arch_isa_flags; |
9103f4f4 | 622 | |
fddf5b5b AM |
623 | /* If set, conditional jumps are not automatically promoted to handle |
624 | larger than a byte offset. */ | |
625 | static unsigned int no_cond_jump_promotion = 0; | |
626 | ||
c0f3af97 L |
627 | /* Encode SSE instructions with VEX prefix. */ |
628 | static unsigned int sse2avx; | |
629 | ||
539f890d L |
630 | /* Encode scalar AVX instructions with specific vector length. */ |
631 | static enum | |
632 | { | |
633 | vex128 = 0, | |
634 | vex256 | |
635 | } avxscalar; | |
636 | ||
43234a1e L |
637 | /* Encode scalar EVEX LIG instructions with specific vector length. */ |
638 | static enum | |
639 | { | |
640 | evexl128 = 0, | |
641 | evexl256, | |
642 | evexl512 | |
643 | } evexlig; | |
644 | ||
645 | /* Encode EVEX WIG instructions with specific evex.w. */ | |
646 | static enum | |
647 | { | |
648 | evexw0 = 0, | |
649 | evexw1 | |
650 | } evexwig; | |
651 | ||
d3d3c6db IT |
652 | /* Value to encode in EVEX RC bits, for SAE-only instructions. */ |
653 | static enum rc_type evexrcig = rne; | |
654 | ||
29b0f896 | 655 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
87c245cc | 656 | static symbolS *GOT_symbol; |
29b0f896 | 657 | |
a4447b93 RH |
658 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
659 | unsigned int x86_dwarf2_return_column; | |
660 | ||
661 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
662 | int x86_cie_data_alignment; | |
663 | ||
252b5132 | 664 | /* Interface to relax_segment. |
fddf5b5b AM |
665 | There are 3 major relax states for 386 jump insns because the |
666 | different types of jumps add different sizes to frags when we're | |
667 | figuring out what sort of jump to choose to reach a given label. */ | |
252b5132 | 668 | |
47926f60 | 669 | /* Types. */ |
93c2a809 AM |
670 | #define UNCOND_JUMP 0 |
671 | #define COND_JUMP 1 | |
672 | #define COND_JUMP86 2 | |
fddf5b5b | 673 | |
47926f60 | 674 | /* Sizes. */ |
252b5132 RH |
675 | #define CODE16 1 |
676 | #define SMALL 0 | |
29b0f896 | 677 | #define SMALL16 (SMALL | CODE16) |
252b5132 | 678 | #define BIG 2 |
29b0f896 | 679 | #define BIG16 (BIG | CODE16) |
252b5132 RH |
680 | |
681 | #ifndef INLINE | |
682 | #ifdef __GNUC__ | |
683 | #define INLINE __inline__ | |
684 | #else | |
685 | #define INLINE | |
686 | #endif | |
687 | #endif | |
688 | ||
fddf5b5b AM |
689 | #define ENCODE_RELAX_STATE(type, size) \ |
690 | ((relax_substateT) (((type) << 2) | (size))) | |
691 | #define TYPE_FROM_RELAX_STATE(s) \ | |
692 | ((s) >> 2) | |
693 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
694 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
695 | |
696 | /* This table is used by relax_frag to promote short jumps to long | |
697 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
698 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
699 | don't allow a short jump in a 32 bit code segment to be promoted to | |
700 | a 16 bit offset jump because it's slower (requires data size | |
701 | prefix), and doesn't work, unless the destination is in the bottom | |
702 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
703 | ||
704 | const relax_typeS md_relax_table[] = | |
705 | { | |
24eab124 AM |
706 | /* The fields are: |
707 | 1) most positive reach of this state, | |
708 | 2) most negative reach of this state, | |
93c2a809 | 709 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 710 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 711 | |
fddf5b5b | 712 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
713 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
714 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
715 | /* dword jmp adds 4 bytes to frag: | |
716 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 717 | {0, 0, 4, 0}, |
93c2a809 AM |
718 | /* word jmp adds 2 byte2 to frag: |
719 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
720 | {0, 0, 2, 0}, |
721 | ||
93c2a809 AM |
722 | /* COND_JUMP states. */ |
723 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
724 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
725 | /* dword conditionals adds 5 bytes to frag: | |
726 | 1 extra opcode byte, 4 displacement bytes. */ | |
727 | {0, 0, 5, 0}, | |
fddf5b5b | 728 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
729 | 1 extra opcode byte, 2 displacement bytes. */ |
730 | {0, 0, 3, 0}, | |
731 | ||
732 | /* COND_JUMP86 states. */ | |
733 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
734 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
735 | /* dword conditionals adds 5 bytes to frag: | |
736 | 1 extra opcode byte, 4 displacement bytes. */ | |
737 | {0, 0, 5, 0}, | |
738 | /* word conditionals add 4 bytes to frag: | |
739 | 1 displacement byte and a 3 byte long branch insn. */ | |
740 | {0, 0, 4, 0} | |
252b5132 RH |
741 | }; |
742 | ||
9103f4f4 L |
743 | static const arch_entry cpu_arch[] = |
744 | { | |
89507696 JB |
745 | /* Do not replace the first two entries - i386_target_format() |
746 | relies on them being there in this order. */ | |
8a2c8fef | 747 | { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32, |
293f5f65 | 748 | CPU_GENERIC32_FLAGS, 0 }, |
8a2c8fef | 749 | { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64, |
293f5f65 | 750 | CPU_GENERIC64_FLAGS, 0 }, |
8a2c8fef | 751 | { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN, |
293f5f65 | 752 | CPU_NONE_FLAGS, 0 }, |
8a2c8fef | 753 | { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN, |
293f5f65 | 754 | CPU_I186_FLAGS, 0 }, |
8a2c8fef | 755 | { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN, |
293f5f65 | 756 | CPU_I286_FLAGS, 0 }, |
8a2c8fef | 757 | { STRING_COMMA_LEN ("i386"), PROCESSOR_I386, |
293f5f65 | 758 | CPU_I386_FLAGS, 0 }, |
8a2c8fef | 759 | { STRING_COMMA_LEN ("i486"), PROCESSOR_I486, |
293f5f65 | 760 | CPU_I486_FLAGS, 0 }, |
8a2c8fef | 761 | { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM, |
293f5f65 | 762 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 763 | { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 764 | CPU_I686_FLAGS, 0 }, |
8a2c8fef | 765 | { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM, |
293f5f65 | 766 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 767 | { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 768 | CPU_PENTIUMPRO_FLAGS, 0 }, |
8a2c8fef | 769 | { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 770 | CPU_P2_FLAGS, 0 }, |
8a2c8fef | 771 | { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO, |
293f5f65 | 772 | CPU_P3_FLAGS, 0 }, |
8a2c8fef | 773 | { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4, |
293f5f65 | 774 | CPU_P4_FLAGS, 0 }, |
8a2c8fef | 775 | { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA, |
293f5f65 | 776 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 777 | { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA, |
293f5f65 | 778 | CPU_NOCONA_FLAGS, 0 }, |
8a2c8fef | 779 | { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE, |
293f5f65 | 780 | CPU_CORE_FLAGS, 1 }, |
8a2c8fef | 781 | { STRING_COMMA_LEN ("core"), PROCESSOR_CORE, |
293f5f65 | 782 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 783 | { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2, |
293f5f65 | 784 | CPU_CORE2_FLAGS, 1 }, |
8a2c8fef | 785 | { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2, |
293f5f65 | 786 | CPU_CORE2_FLAGS, 0 }, |
8a2c8fef | 787 | { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7, |
293f5f65 | 788 | CPU_COREI7_FLAGS, 0 }, |
8a2c8fef | 789 | { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM, |
293f5f65 | 790 | CPU_L1OM_FLAGS, 0 }, |
7a9068fe | 791 | { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM, |
293f5f65 | 792 | CPU_K1OM_FLAGS, 0 }, |
81486035 | 793 | { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU, |
293f5f65 | 794 | CPU_IAMCU_FLAGS, 0 }, |
8a2c8fef | 795 | { STRING_COMMA_LEN ("k6"), PROCESSOR_K6, |
293f5f65 | 796 | CPU_K6_FLAGS, 0 }, |
8a2c8fef | 797 | { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6, |
293f5f65 | 798 | CPU_K6_2_FLAGS, 0 }, |
8a2c8fef | 799 | { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON, |
293f5f65 | 800 | CPU_ATHLON_FLAGS, 0 }, |
8a2c8fef | 801 | { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8, |
293f5f65 | 802 | CPU_K8_FLAGS, 1 }, |
8a2c8fef | 803 | { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8, |
293f5f65 | 804 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 805 | { STRING_COMMA_LEN ("k8"), PROCESSOR_K8, |
293f5f65 | 806 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 807 | { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10, |
293f5f65 | 808 | CPU_AMDFAM10_FLAGS, 0 }, |
8aedb9fe | 809 | { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD, |
293f5f65 | 810 | CPU_BDVER1_FLAGS, 0 }, |
8aedb9fe | 811 | { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD, |
293f5f65 | 812 | CPU_BDVER2_FLAGS, 0 }, |
5e5c50d3 | 813 | { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD, |
293f5f65 | 814 | CPU_BDVER3_FLAGS, 0 }, |
c7b0bd56 | 815 | { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD, |
293f5f65 | 816 | CPU_BDVER4_FLAGS, 0 }, |
029f3522 | 817 | { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER, |
293f5f65 | 818 | CPU_ZNVER1_FLAGS, 0 }, |
7b458c12 | 819 | { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT, |
293f5f65 | 820 | CPU_BTVER1_FLAGS, 0 }, |
7b458c12 | 821 | { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT, |
293f5f65 | 822 | CPU_BTVER2_FLAGS, 0 }, |
8a2c8fef | 823 | { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN, |
293f5f65 | 824 | CPU_8087_FLAGS, 0 }, |
8a2c8fef | 825 | { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN, |
293f5f65 | 826 | CPU_287_FLAGS, 0 }, |
8a2c8fef | 827 | { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN, |
293f5f65 | 828 | CPU_387_FLAGS, 0 }, |
1848e567 L |
829 | { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN, |
830 | CPU_687_FLAGS, 0 }, | |
8a2c8fef | 831 | { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 832 | CPU_MMX_FLAGS, 0 }, |
8a2c8fef | 833 | { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN, |
293f5f65 | 834 | CPU_SSE_FLAGS, 0 }, |
8a2c8fef | 835 | { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN, |
293f5f65 | 836 | CPU_SSE2_FLAGS, 0 }, |
8a2c8fef | 837 | { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 838 | CPU_SSE3_FLAGS, 0 }, |
8a2c8fef | 839 | { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 840 | CPU_SSSE3_FLAGS, 0 }, |
8a2c8fef | 841 | { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN, |
293f5f65 | 842 | CPU_SSE4_1_FLAGS, 0 }, |
8a2c8fef | 843 | { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN, |
293f5f65 | 844 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 845 | { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN, |
293f5f65 | 846 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 847 | { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN, |
293f5f65 | 848 | CPU_AVX_FLAGS, 0 }, |
6c30d220 | 849 | { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN, |
293f5f65 | 850 | CPU_AVX2_FLAGS, 0 }, |
43234a1e | 851 | { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN, |
293f5f65 | 852 | CPU_AVX512F_FLAGS, 0 }, |
43234a1e | 853 | { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN, |
293f5f65 | 854 | CPU_AVX512CD_FLAGS, 0 }, |
43234a1e | 855 | { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN, |
293f5f65 | 856 | CPU_AVX512ER_FLAGS, 0 }, |
43234a1e | 857 | { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN, |
293f5f65 | 858 | CPU_AVX512PF_FLAGS, 0 }, |
1dfc6506 | 859 | { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN, |
293f5f65 | 860 | CPU_AVX512DQ_FLAGS, 0 }, |
1dfc6506 | 861 | { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN, |
293f5f65 | 862 | CPU_AVX512BW_FLAGS, 0 }, |
1dfc6506 | 863 | { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN, |
293f5f65 | 864 | CPU_AVX512VL_FLAGS, 0 }, |
8a2c8fef | 865 | { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 866 | CPU_VMX_FLAGS, 0 }, |
8729a6f6 | 867 | { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN, |
293f5f65 | 868 | CPU_VMFUNC_FLAGS, 0 }, |
8a2c8fef | 869 | { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN, |
293f5f65 | 870 | CPU_SMX_FLAGS, 0 }, |
8a2c8fef | 871 | { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN, |
293f5f65 | 872 | CPU_XSAVE_FLAGS, 0 }, |
c7b8aa3a | 873 | { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 874 | CPU_XSAVEOPT_FLAGS, 0 }, |
1dfc6506 | 875 | { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN, |
293f5f65 | 876 | CPU_XSAVEC_FLAGS, 0 }, |
1dfc6506 | 877 | { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN, |
293f5f65 | 878 | CPU_XSAVES_FLAGS, 0 }, |
8a2c8fef | 879 | { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN, |
293f5f65 | 880 | CPU_AES_FLAGS, 0 }, |
8a2c8fef | 881 | { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 882 | CPU_PCLMUL_FLAGS, 0 }, |
8a2c8fef | 883 | { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 884 | CPU_PCLMUL_FLAGS, 1 }, |
c7b8aa3a | 885 | { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN, |
293f5f65 | 886 | CPU_FSGSBASE_FLAGS, 0 }, |
c7b8aa3a | 887 | { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN, |
293f5f65 | 888 | CPU_RDRND_FLAGS, 0 }, |
c7b8aa3a | 889 | { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN, |
293f5f65 | 890 | CPU_F16C_FLAGS, 0 }, |
6c30d220 | 891 | { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN, |
293f5f65 | 892 | CPU_BMI2_FLAGS, 0 }, |
8a2c8fef | 893 | { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN, |
293f5f65 | 894 | CPU_FMA_FLAGS, 0 }, |
8a2c8fef | 895 | { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN, |
293f5f65 | 896 | CPU_FMA4_FLAGS, 0 }, |
8a2c8fef | 897 | { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN, |
293f5f65 | 898 | CPU_XOP_FLAGS, 0 }, |
8a2c8fef | 899 | { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN, |
293f5f65 | 900 | CPU_LWP_FLAGS, 0 }, |
8a2c8fef | 901 | { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN, |
293f5f65 | 902 | CPU_MOVBE_FLAGS, 0 }, |
60aa667e | 903 | { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN, |
293f5f65 | 904 | CPU_CX16_FLAGS, 0 }, |
8a2c8fef | 905 | { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN, |
293f5f65 | 906 | CPU_EPT_FLAGS, 0 }, |
6c30d220 | 907 | { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN, |
293f5f65 | 908 | CPU_LZCNT_FLAGS, 0 }, |
42164a71 | 909 | { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN, |
293f5f65 | 910 | CPU_HLE_FLAGS, 0 }, |
42164a71 | 911 | { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN, |
293f5f65 | 912 | CPU_RTM_FLAGS, 0 }, |
6c30d220 | 913 | { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN, |
293f5f65 | 914 | CPU_INVPCID_FLAGS, 0 }, |
8a2c8fef | 915 | { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN, |
293f5f65 | 916 | CPU_CLFLUSH_FLAGS, 0 }, |
22109423 | 917 | { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN, |
293f5f65 | 918 | CPU_NOP_FLAGS, 0 }, |
8a2c8fef | 919 | { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN, |
293f5f65 | 920 | CPU_SYSCALL_FLAGS, 0 }, |
8a2c8fef | 921 | { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN, |
293f5f65 | 922 | CPU_RDTSCP_FLAGS, 0 }, |
8a2c8fef | 923 | { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN, |
293f5f65 | 924 | CPU_3DNOW_FLAGS, 0 }, |
8a2c8fef | 925 | { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN, |
293f5f65 | 926 | CPU_3DNOWA_FLAGS, 0 }, |
8a2c8fef | 927 | { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN, |
293f5f65 | 928 | CPU_PADLOCK_FLAGS, 0 }, |
8a2c8fef | 929 | { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN, |
293f5f65 | 930 | CPU_SVME_FLAGS, 1 }, |
8a2c8fef | 931 | { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN, |
293f5f65 | 932 | CPU_SVME_FLAGS, 0 }, |
8a2c8fef | 933 | { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, |
293f5f65 | 934 | CPU_SSE4A_FLAGS, 0 }, |
8a2c8fef | 935 | { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN, |
293f5f65 | 936 | CPU_ABM_FLAGS, 0 }, |
87973e9f | 937 | { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 938 | CPU_BMI_FLAGS, 0 }, |
2a2a0f38 | 939 | { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN, |
293f5f65 | 940 | CPU_TBM_FLAGS, 0 }, |
e2e1fcde | 941 | { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN, |
293f5f65 | 942 | CPU_ADX_FLAGS, 0 }, |
e2e1fcde | 943 | { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN, |
293f5f65 | 944 | CPU_RDSEED_FLAGS, 0 }, |
e2e1fcde | 945 | { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN, |
293f5f65 | 946 | CPU_PRFCHW_FLAGS, 0 }, |
5c111e37 | 947 | { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN, |
293f5f65 | 948 | CPU_SMAP_FLAGS, 0 }, |
7e8b059b | 949 | { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN, |
293f5f65 | 950 | CPU_MPX_FLAGS, 0 }, |
a0046408 | 951 | { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN, |
293f5f65 | 952 | CPU_SHA_FLAGS, 0 }, |
963f3586 | 953 | { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 954 | CPU_CLFLUSHOPT_FLAGS, 0 }, |
dcf893b5 | 955 | { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN, |
293f5f65 | 956 | CPU_PREFETCHWT1_FLAGS, 0 }, |
2cf200a4 | 957 | { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN, |
293f5f65 | 958 | CPU_SE1_FLAGS, 0 }, |
c5e7287a | 959 | { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN, |
293f5f65 | 960 | CPU_CLWB_FLAGS, 0 }, |
9d8596f0 | 961 | { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN, |
293f5f65 | 962 | CPU_PCOMMIT_FLAGS, 0 }, |
2cc1b5aa | 963 | { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN, |
293f5f65 | 964 | CPU_AVX512IFMA_FLAGS, 0 }, |
14f195c9 | 965 | { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 966 | CPU_AVX512VBMI_FLAGS, 0 }, |
029f3522 | 967 | { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN, |
293f5f65 | 968 | CPU_CLZERO_FLAGS, 0 }, |
9916071f | 969 | { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN, |
293f5f65 | 970 | CPU_MWAITX_FLAGS, 0 }, |
8eab4136 | 971 | { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN, |
293f5f65 | 972 | CPU_OSPKE_FLAGS, 0 }, |
8bc52696 | 973 | { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN, |
293f5f65 L |
974 | CPU_RDPID_FLAGS, 0 }, |
975 | }; | |
976 | ||
977 | static const noarch_entry cpu_noarch[] = | |
978 | { | |
979 | { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS }, | |
1848e567 L |
980 | { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS }, |
981 | { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS }, | |
982 | { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS }, | |
293f5f65 L |
983 | { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS }, |
984 | { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS }, | |
1848e567 L |
985 | { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS }, |
986 | { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS }, | |
987 | { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS }, | |
988 | { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS }, | |
989 | { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS }, | |
990 | { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS }, | |
293f5f65 | 991 | { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS }, |
1848e567 | 992 | { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS }, |
144b71e2 L |
993 | { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS }, |
994 | { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS }, | |
995 | { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS }, | |
996 | { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS }, | |
997 | { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS }, | |
998 | { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS }, | |
999 | { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS }, | |
1000 | { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS }, | |
1001 | { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS }, | |
e413e4e9 AM |
1002 | }; |
1003 | ||
704209c0 | 1004 | #ifdef I386COFF |
a6c24e68 NC |
1005 | /* Like s_lcomm_internal in gas/read.c but the alignment string |
1006 | is allowed to be optional. */ | |
1007 | ||
1008 | static symbolS * | |
1009 | pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size) | |
1010 | { | |
1011 | addressT align = 0; | |
1012 | ||
1013 | SKIP_WHITESPACE (); | |
1014 | ||
7ab9ffdd | 1015 | if (needs_align |
a6c24e68 NC |
1016 | && *input_line_pointer == ',') |
1017 | { | |
1018 | align = parse_align (needs_align - 1); | |
7ab9ffdd | 1019 | |
a6c24e68 NC |
1020 | if (align == (addressT) -1) |
1021 | return NULL; | |
1022 | } | |
1023 | else | |
1024 | { | |
1025 | if (size >= 8) | |
1026 | align = 3; | |
1027 | else if (size >= 4) | |
1028 | align = 2; | |
1029 | else if (size >= 2) | |
1030 | align = 1; | |
1031 | else | |
1032 | align = 0; | |
1033 | } | |
1034 | ||
1035 | bss_alloc (symbolP, size, align); | |
1036 | return symbolP; | |
1037 | } | |
1038 | ||
704209c0 | 1039 | static void |
a6c24e68 NC |
1040 | pe_lcomm (int needs_align) |
1041 | { | |
1042 | s_comm_internal (needs_align * 2, pe_lcomm_internal); | |
1043 | } | |
704209c0 | 1044 | #endif |
a6c24e68 | 1045 | |
29b0f896 AM |
1046 | const pseudo_typeS md_pseudo_table[] = |
1047 | { | |
1048 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) | |
1049 | {"align", s_align_bytes, 0}, | |
1050 | #else | |
1051 | {"align", s_align_ptwo, 0}, | |
1052 | #endif | |
1053 | {"arch", set_cpu_arch, 0}, | |
1054 | #ifndef I386COFF | |
1055 | {"bss", s_bss, 0}, | |
a6c24e68 NC |
1056 | #else |
1057 | {"lcomm", pe_lcomm, 1}, | |
29b0f896 AM |
1058 | #endif |
1059 | {"ffloat", float_cons, 'f'}, | |
1060 | {"dfloat", float_cons, 'd'}, | |
1061 | {"tfloat", float_cons, 'x'}, | |
1062 | {"value", cons, 2}, | |
d182319b | 1063 | {"slong", signed_cons, 4}, |
29b0f896 AM |
1064 | {"noopt", s_ignore, 0}, |
1065 | {"optim", s_ignore, 0}, | |
1066 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, | |
1067 | {"code16", set_code_flag, CODE_16BIT}, | |
1068 | {"code32", set_code_flag, CODE_32BIT}, | |
1069 | {"code64", set_code_flag, CODE_64BIT}, | |
1070 | {"intel_syntax", set_intel_syntax, 1}, | |
1071 | {"att_syntax", set_intel_syntax, 0}, | |
1efbbeb4 L |
1072 | {"intel_mnemonic", set_intel_mnemonic, 1}, |
1073 | {"att_mnemonic", set_intel_mnemonic, 0}, | |
db51cc60 L |
1074 | {"allow_index_reg", set_allow_index_reg, 1}, |
1075 | {"disallow_index_reg", set_allow_index_reg, 0}, | |
7bab8ab5 JB |
1076 | {"sse_check", set_check, 0}, |
1077 | {"operand_check", set_check, 1}, | |
3b22753a L |
1078 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
1079 | {"largecomm", handle_large_common, 0}, | |
07a53e5c | 1080 | #else |
e3bb37b5 | 1081 | {"file", (void (*) (int)) dwarf2_directive_file, 0}, |
07a53e5c RH |
1082 | {"loc", dwarf2_directive_loc, 0}, |
1083 | {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, | |
3b22753a | 1084 | #endif |
6482c264 NC |
1085 | #ifdef TE_PE |
1086 | {"secrel32", pe_directive_secrel, 0}, | |
1087 | #endif | |
29b0f896 AM |
1088 | {0, 0, 0} |
1089 | }; | |
1090 | ||
1091 | /* For interface with expression (). */ | |
1092 | extern char *input_line_pointer; | |
1093 | ||
1094 | /* Hash table for instruction mnemonic lookup. */ | |
1095 | static struct hash_control *op_hash; | |
1096 | ||
1097 | /* Hash table for register lookup. */ | |
1098 | static struct hash_control *reg_hash; | |
1099 | \f | |
252b5132 | 1100 | void |
e3bb37b5 | 1101 | i386_align_code (fragS *fragP, int count) |
252b5132 | 1102 | { |
ce8a8b2f AM |
1103 | /* Various efficient no-op patterns for aligning code labels. |
1104 | Note: Don't try to assemble the instructions in the comments. | |
1105 | 0L and 0w are not legal. */ | |
bad6e36d | 1106 | static const unsigned char f32_1[] = |
252b5132 | 1107 | {0x90}; /* nop */ |
bad6e36d | 1108 | static const unsigned char f32_2[] = |
ccc9c027 | 1109 | {0x66,0x90}; /* xchg %ax,%ax */ |
bad6e36d | 1110 | static const unsigned char f32_3[] = |
252b5132 | 1111 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ |
bad6e36d | 1112 | static const unsigned char f32_4[] = |
252b5132 | 1113 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ |
bad6e36d | 1114 | static const unsigned char f32_5[] = |
252b5132 RH |
1115 | {0x90, /* nop */ |
1116 | 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
bad6e36d | 1117 | static const unsigned char f32_6[] = |
252b5132 | 1118 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ |
bad6e36d | 1119 | static const unsigned char f32_7[] = |
252b5132 | 1120 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ |
bad6e36d | 1121 | static const unsigned char f32_8[] = |
252b5132 RH |
1122 | {0x90, /* nop */ |
1123 | 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
bad6e36d | 1124 | static const unsigned char f32_9[] = |
252b5132 RH |
1125 | {0x89,0xf6, /* movl %esi,%esi */ |
1126 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
bad6e36d | 1127 | static const unsigned char f32_10[] = |
252b5132 RH |
1128 | {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ |
1129 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
bad6e36d | 1130 | static const unsigned char f32_11[] = |
252b5132 RH |
1131 | {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ |
1132 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
bad6e36d | 1133 | static const unsigned char f32_12[] = |
252b5132 RH |
1134 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ |
1135 | 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ | |
bad6e36d | 1136 | static const unsigned char f32_13[] = |
252b5132 RH |
1137 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ |
1138 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
bad6e36d | 1139 | static const unsigned char f32_14[] = |
252b5132 RH |
1140 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ |
1141 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
bad6e36d | 1142 | static const unsigned char f16_3[] = |
c3332e24 | 1143 | {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */ |
bad6e36d | 1144 | static const unsigned char f16_4[] = |
252b5132 | 1145 | {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ |
bad6e36d | 1146 | static const unsigned char f16_5[] = |
252b5132 RH |
1147 | {0x90, /* nop */ |
1148 | 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
bad6e36d | 1149 | static const unsigned char f16_6[] = |
252b5132 RH |
1150 | {0x89,0xf6, /* mov %si,%si */ |
1151 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
bad6e36d | 1152 | static const unsigned char f16_7[] = |
252b5132 RH |
1153 | {0x8d,0x74,0x00, /* lea 0(%si),%si */ |
1154 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
bad6e36d | 1155 | static const unsigned char f16_8[] = |
252b5132 RH |
1156 | {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ |
1157 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
bad6e36d | 1158 | static const unsigned char jump_31[] = |
76bc74dc L |
1159 | {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */ |
1160 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90, | |
1161 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90, | |
1162 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; | |
bad6e36d | 1163 | static const unsigned char *const f32_patt[] = { |
252b5132 | 1164 | f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, |
76bc74dc | 1165 | f32_9, f32_10, f32_11, f32_12, f32_13, f32_14 |
252b5132 | 1166 | }; |
bad6e36d | 1167 | static const unsigned char *const f16_patt[] = { |
76bc74dc | 1168 | f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8 |
252b5132 | 1169 | }; |
ccc9c027 | 1170 | /* nopl (%[re]ax) */ |
bad6e36d | 1171 | static const unsigned char alt_3[] = |
ccc9c027 L |
1172 | {0x0f,0x1f,0x00}; |
1173 | /* nopl 0(%[re]ax) */ | |
bad6e36d | 1174 | static const unsigned char alt_4[] = |
ccc9c027 L |
1175 | {0x0f,0x1f,0x40,0x00}; |
1176 | /* nopl 0(%[re]ax,%[re]ax,1) */ | |
bad6e36d | 1177 | static const unsigned char alt_5[] = |
ccc9c027 L |
1178 | {0x0f,0x1f,0x44,0x00,0x00}; |
1179 | /* nopw 0(%[re]ax,%[re]ax,1) */ | |
bad6e36d | 1180 | static const unsigned char alt_6[] = |
ccc9c027 L |
1181 | {0x66,0x0f,0x1f,0x44,0x00,0x00}; |
1182 | /* nopl 0L(%[re]ax) */ | |
bad6e36d | 1183 | static const unsigned char alt_7[] = |
ccc9c027 L |
1184 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; |
1185 | /* nopl 0L(%[re]ax,%[re]ax,1) */ | |
bad6e36d | 1186 | static const unsigned char alt_8[] = |
ccc9c027 L |
1187 | {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; |
1188 | /* nopw 0L(%[re]ax,%[re]ax,1) */ | |
bad6e36d | 1189 | static const unsigned char alt_9[] = |
ccc9c027 L |
1190 | {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; |
1191 | /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
bad6e36d | 1192 | static const unsigned char alt_10[] = |
ccc9c027 | 1193 | {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; |
bad6e36d | 1194 | static const unsigned char *const alt_patt[] = { |
ccc9c027 | 1195 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, |
80b8656c | 1196 | alt_9, alt_10 |
ccc9c027 | 1197 | }; |
252b5132 | 1198 | |
76bc74dc L |
1199 | /* Only align for at least a positive non-zero boundary. */ |
1200 | if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE) | |
33fef721 | 1201 | return; |
3e73aa7c | 1202 | |
ccc9c027 L |
1203 | /* We need to decide which NOP sequence to use for 32bit and |
1204 | 64bit. When -mtune= is used: | |
4eed87de | 1205 | |
76bc74dc L |
1206 | 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and |
1207 | PROCESSOR_GENERIC32, f32_patt will be used. | |
80b8656c L |
1208 | 2. For the rest, alt_patt will be used. |
1209 | ||
1210 | When -mtune= isn't used, alt_patt will be used if | |
22109423 | 1211 | cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will |
76bc74dc | 1212 | be used. |
ccc9c027 L |
1213 | |
1214 | When -march= or .arch is used, we can't use anything beyond | |
1215 | cpu_arch_isa_flags. */ | |
1216 | ||
1217 | if (flag_code == CODE_16BIT) | |
1218 | { | |
ccc9c027 | 1219 | if (count > 8) |
33fef721 | 1220 | { |
76bc74dc L |
1221 | memcpy (fragP->fr_literal + fragP->fr_fix, |
1222 | jump_31, count); | |
1223 | /* Adjust jump offset. */ | |
1224 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; | |
252b5132 | 1225 | } |
76bc74dc L |
1226 | else |
1227 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
1228 | f16_patt[count - 1], count); | |
252b5132 | 1229 | } |
33fef721 | 1230 | else |
ccc9c027 | 1231 | { |
bad6e36d | 1232 | const unsigned char *const *patt = NULL; |
ccc9c027 | 1233 | |
fbf3f584 | 1234 | if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN) |
ccc9c027 L |
1235 | { |
1236 | /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ | |
1237 | switch (cpu_arch_tune) | |
1238 | { | |
1239 | case PROCESSOR_UNKNOWN: | |
1240 | /* We use cpu_arch_isa_flags to check if we SHOULD | |
22109423 L |
1241 | optimize with nops. */ |
1242 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1243 | patt = alt_patt; |
ccc9c027 L |
1244 | else |
1245 | patt = f32_patt; | |
1246 | break; | |
ccc9c027 L |
1247 | case PROCESSOR_PENTIUM4: |
1248 | case PROCESSOR_NOCONA: | |
ef05d495 | 1249 | case PROCESSOR_CORE: |
76bc74dc | 1250 | case PROCESSOR_CORE2: |
bd5295b2 | 1251 | case PROCESSOR_COREI7: |
3632d14b | 1252 | case PROCESSOR_L1OM: |
7a9068fe | 1253 | case PROCESSOR_K1OM: |
76bc74dc | 1254 | case PROCESSOR_GENERIC64: |
ccc9c027 L |
1255 | case PROCESSOR_K6: |
1256 | case PROCESSOR_ATHLON: | |
1257 | case PROCESSOR_K8: | |
4eed87de | 1258 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1259 | case PROCESSOR_BD: |
029f3522 | 1260 | case PROCESSOR_ZNVER: |
7b458c12 | 1261 | case PROCESSOR_BT: |
80b8656c | 1262 | patt = alt_patt; |
ccc9c027 | 1263 | break; |
76bc74dc | 1264 | case PROCESSOR_I386: |
ccc9c027 L |
1265 | case PROCESSOR_I486: |
1266 | case PROCESSOR_PENTIUM: | |
2dde1948 | 1267 | case PROCESSOR_PENTIUMPRO: |
81486035 | 1268 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1269 | case PROCESSOR_GENERIC32: |
1270 | patt = f32_patt; | |
1271 | break; | |
4eed87de | 1272 | } |
ccc9c027 L |
1273 | } |
1274 | else | |
1275 | { | |
fbf3f584 | 1276 | switch (fragP->tc_frag_data.tune) |
ccc9c027 L |
1277 | { |
1278 | case PROCESSOR_UNKNOWN: | |
e6a14101 | 1279 | /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be |
ccc9c027 L |
1280 | PROCESSOR_UNKNOWN. */ |
1281 | abort (); | |
1282 | break; | |
1283 | ||
76bc74dc | 1284 | case PROCESSOR_I386: |
ccc9c027 L |
1285 | case PROCESSOR_I486: |
1286 | case PROCESSOR_PENTIUM: | |
81486035 | 1287 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1288 | case PROCESSOR_K6: |
1289 | case PROCESSOR_ATHLON: | |
1290 | case PROCESSOR_K8: | |
4eed87de | 1291 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1292 | case PROCESSOR_BD: |
029f3522 | 1293 | case PROCESSOR_ZNVER: |
7b458c12 | 1294 | case PROCESSOR_BT: |
ccc9c027 L |
1295 | case PROCESSOR_GENERIC32: |
1296 | /* We use cpu_arch_isa_flags to check if we CAN optimize | |
22109423 L |
1297 | with nops. */ |
1298 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1299 | patt = alt_patt; |
ccc9c027 L |
1300 | else |
1301 | patt = f32_patt; | |
1302 | break; | |
76bc74dc L |
1303 | case PROCESSOR_PENTIUMPRO: |
1304 | case PROCESSOR_PENTIUM4: | |
1305 | case PROCESSOR_NOCONA: | |
1306 | case PROCESSOR_CORE: | |
ef05d495 | 1307 | case PROCESSOR_CORE2: |
bd5295b2 | 1308 | case PROCESSOR_COREI7: |
3632d14b | 1309 | case PROCESSOR_L1OM: |
7a9068fe | 1310 | case PROCESSOR_K1OM: |
22109423 | 1311 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) |
80b8656c | 1312 | patt = alt_patt; |
ccc9c027 L |
1313 | else |
1314 | patt = f32_patt; | |
1315 | break; | |
1316 | case PROCESSOR_GENERIC64: | |
80b8656c | 1317 | patt = alt_patt; |
ccc9c027 | 1318 | break; |
4eed87de | 1319 | } |
ccc9c027 L |
1320 | } |
1321 | ||
76bc74dc L |
1322 | if (patt == f32_patt) |
1323 | { | |
1324 | /* If the padding is less than 15 bytes, we use the normal | |
1325 | ones. Otherwise, we use a jump instruction and adjust | |
711eedef L |
1326 | its offset. */ |
1327 | int limit; | |
76ba9986 | 1328 | |
711eedef L |
1329 | /* For 64bit, the limit is 3 bytes. */ |
1330 | if (flag_code == CODE_64BIT | |
1331 | && fragP->tc_frag_data.isa_flags.bitfield.cpulm) | |
1332 | limit = 3; | |
1333 | else | |
1334 | limit = 15; | |
1335 | if (count < limit) | |
76bc74dc L |
1336 | memcpy (fragP->fr_literal + fragP->fr_fix, |
1337 | patt[count - 1], count); | |
1338 | else | |
1339 | { | |
1340 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
1341 | jump_31, count); | |
1342 | /* Adjust jump offset. */ | |
1343 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; | |
1344 | } | |
1345 | } | |
1346 | else | |
1347 | { | |
80b8656c L |
1348 | /* Maximum length of an instruction is 10 byte. If the |
1349 | padding is greater than 10 bytes and we don't use jump, | |
76bc74dc L |
1350 | we have to break it into smaller pieces. */ |
1351 | int padding = count; | |
80b8656c | 1352 | while (padding > 10) |
76bc74dc | 1353 | { |
80b8656c | 1354 | padding -= 10; |
76bc74dc | 1355 | memcpy (fragP->fr_literal + fragP->fr_fix + padding, |
80b8656c | 1356 | patt [9], 10); |
76bc74dc L |
1357 | } |
1358 | ||
1359 | if (padding) | |
1360 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
1361 | patt [padding - 1], padding); | |
1362 | } | |
ccc9c027 | 1363 | } |
33fef721 | 1364 | fragP->fr_var = count; |
252b5132 RH |
1365 | } |
1366 | ||
c6fb90c8 | 1367 | static INLINE int |
0dfbf9d7 | 1368 | operand_type_all_zero (const union i386_operand_type *x) |
40fb9820 | 1369 | { |
0dfbf9d7 | 1370 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1371 | { |
1372 | case 3: | |
0dfbf9d7 | 1373 | if (x->array[2]) |
c6fb90c8 L |
1374 | return 0; |
1375 | case 2: | |
0dfbf9d7 | 1376 | if (x->array[1]) |
c6fb90c8 L |
1377 | return 0; |
1378 | case 1: | |
0dfbf9d7 | 1379 | return !x->array[0]; |
c6fb90c8 L |
1380 | default: |
1381 | abort (); | |
1382 | } | |
40fb9820 L |
1383 | } |
1384 | ||
c6fb90c8 | 1385 | static INLINE void |
0dfbf9d7 | 1386 | operand_type_set (union i386_operand_type *x, unsigned int v) |
40fb9820 | 1387 | { |
0dfbf9d7 | 1388 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1389 | { |
1390 | case 3: | |
0dfbf9d7 | 1391 | x->array[2] = v; |
c6fb90c8 | 1392 | case 2: |
0dfbf9d7 | 1393 | x->array[1] = v; |
c6fb90c8 | 1394 | case 1: |
0dfbf9d7 | 1395 | x->array[0] = v; |
c6fb90c8 L |
1396 | break; |
1397 | default: | |
1398 | abort (); | |
1399 | } | |
1400 | } | |
40fb9820 | 1401 | |
c6fb90c8 | 1402 | static INLINE int |
0dfbf9d7 L |
1403 | operand_type_equal (const union i386_operand_type *x, |
1404 | const union i386_operand_type *y) | |
c6fb90c8 | 1405 | { |
0dfbf9d7 | 1406 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1407 | { |
1408 | case 3: | |
0dfbf9d7 | 1409 | if (x->array[2] != y->array[2]) |
c6fb90c8 L |
1410 | return 0; |
1411 | case 2: | |
0dfbf9d7 | 1412 | if (x->array[1] != y->array[1]) |
c6fb90c8 L |
1413 | return 0; |
1414 | case 1: | |
0dfbf9d7 | 1415 | return x->array[0] == y->array[0]; |
c6fb90c8 L |
1416 | break; |
1417 | default: | |
1418 | abort (); | |
1419 | } | |
1420 | } | |
40fb9820 | 1421 | |
0dfbf9d7 L |
1422 | static INLINE int |
1423 | cpu_flags_all_zero (const union i386_cpu_flags *x) | |
1424 | { | |
1425 | switch (ARRAY_SIZE(x->array)) | |
1426 | { | |
1427 | case 3: | |
1428 | if (x->array[2]) | |
1429 | return 0; | |
1430 | case 2: | |
1431 | if (x->array[1]) | |
1432 | return 0; | |
1433 | case 1: | |
1434 | return !x->array[0]; | |
1435 | default: | |
1436 | abort (); | |
1437 | } | |
1438 | } | |
1439 | ||
0dfbf9d7 L |
1440 | static INLINE int |
1441 | cpu_flags_equal (const union i386_cpu_flags *x, | |
1442 | const union i386_cpu_flags *y) | |
1443 | { | |
1444 | switch (ARRAY_SIZE(x->array)) | |
1445 | { | |
1446 | case 3: | |
1447 | if (x->array[2] != y->array[2]) | |
1448 | return 0; | |
1449 | case 2: | |
1450 | if (x->array[1] != y->array[1]) | |
1451 | return 0; | |
1452 | case 1: | |
1453 | return x->array[0] == y->array[0]; | |
1454 | break; | |
1455 | default: | |
1456 | abort (); | |
1457 | } | |
1458 | } | |
c6fb90c8 L |
1459 | |
1460 | static INLINE int | |
1461 | cpu_flags_check_cpu64 (i386_cpu_flags f) | |
1462 | { | |
1463 | return !((flag_code == CODE_64BIT && f.bitfield.cpuno64) | |
1464 | || (flag_code != CODE_64BIT && f.bitfield.cpu64)); | |
40fb9820 L |
1465 | } |
1466 | ||
c6fb90c8 L |
1467 | static INLINE i386_cpu_flags |
1468 | cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1469 | { |
c6fb90c8 L |
1470 | switch (ARRAY_SIZE (x.array)) |
1471 | { | |
1472 | case 3: | |
1473 | x.array [2] &= y.array [2]; | |
1474 | case 2: | |
1475 | x.array [1] &= y.array [1]; | |
1476 | case 1: | |
1477 | x.array [0] &= y.array [0]; | |
1478 | break; | |
1479 | default: | |
1480 | abort (); | |
1481 | } | |
1482 | return x; | |
1483 | } | |
40fb9820 | 1484 | |
c6fb90c8 L |
1485 | static INLINE i386_cpu_flags |
1486 | cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1487 | { |
c6fb90c8 | 1488 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1489 | { |
c6fb90c8 L |
1490 | case 3: |
1491 | x.array [2] |= y.array [2]; | |
1492 | case 2: | |
1493 | x.array [1] |= y.array [1]; | |
1494 | case 1: | |
1495 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1496 | break; |
1497 | default: | |
1498 | abort (); | |
1499 | } | |
40fb9820 L |
1500 | return x; |
1501 | } | |
1502 | ||
309d3373 JB |
1503 | static INLINE i386_cpu_flags |
1504 | cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y) | |
1505 | { | |
1506 | switch (ARRAY_SIZE (x.array)) | |
1507 | { | |
1508 | case 3: | |
1509 | x.array [2] &= ~y.array [2]; | |
1510 | case 2: | |
1511 | x.array [1] &= ~y.array [1]; | |
1512 | case 1: | |
1513 | x.array [0] &= ~y.array [0]; | |
1514 | break; | |
1515 | default: | |
1516 | abort (); | |
1517 | } | |
1518 | return x; | |
1519 | } | |
1520 | ||
81486035 L |
1521 | static int |
1522 | valid_iamcu_cpu_flags (const i386_cpu_flags *flags) | |
1523 | { | |
1524 | if (cpu_arch_isa == PROCESSOR_IAMCU) | |
1525 | { | |
1526 | static const i386_cpu_flags iamcu_flags = CPU_IAMCU_COMPAT_FLAGS; | |
1527 | i386_cpu_flags compat_flags; | |
1528 | compat_flags = cpu_flags_and_not (*flags, iamcu_flags); | |
1529 | return cpu_flags_all_zero (&compat_flags); | |
1530 | } | |
1531 | else | |
1532 | return 1; | |
1533 | } | |
1534 | ||
c0f3af97 L |
1535 | #define CPU_FLAGS_ARCH_MATCH 0x1 |
1536 | #define CPU_FLAGS_64BIT_MATCH 0x2 | |
a5ff0eb2 | 1537 | #define CPU_FLAGS_AES_MATCH 0x4 |
ce2f5b3c L |
1538 | #define CPU_FLAGS_PCLMUL_MATCH 0x8 |
1539 | #define CPU_FLAGS_AVX_MATCH 0x10 | |
c0f3af97 | 1540 | |
a5ff0eb2 | 1541 | #define CPU_FLAGS_32BIT_MATCH \ |
ce2f5b3c L |
1542 | (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \ |
1543 | | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH) | |
c0f3af97 L |
1544 | #define CPU_FLAGS_PERFECT_MATCH \ |
1545 | (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH) | |
1546 | ||
1547 | /* Return CPU flags match bits. */ | |
3629bb00 | 1548 | |
40fb9820 | 1549 | static int |
d3ce72d0 | 1550 | cpu_flags_match (const insn_template *t) |
40fb9820 | 1551 | { |
c0f3af97 L |
1552 | i386_cpu_flags x = t->cpu_flags; |
1553 | int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0; | |
40fb9820 L |
1554 | |
1555 | x.bitfield.cpu64 = 0; | |
1556 | x.bitfield.cpuno64 = 0; | |
1557 | ||
0dfbf9d7 | 1558 | if (cpu_flags_all_zero (&x)) |
c0f3af97 L |
1559 | { |
1560 | /* This instruction is available on all archs. */ | |
1561 | match |= CPU_FLAGS_32BIT_MATCH; | |
1562 | } | |
3629bb00 L |
1563 | else |
1564 | { | |
c0f3af97 | 1565 | /* This instruction is available only on some archs. */ |
3629bb00 L |
1566 | i386_cpu_flags cpu = cpu_arch_flags; |
1567 | ||
3629bb00 | 1568 | cpu = cpu_flags_and (x, cpu); |
c0f3af97 L |
1569 | if (!cpu_flags_all_zero (&cpu)) |
1570 | { | |
a5ff0eb2 L |
1571 | if (x.bitfield.cpuavx) |
1572 | { | |
ce2f5b3c | 1573 | /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */ |
a5ff0eb2 L |
1574 | if (cpu.bitfield.cpuavx) |
1575 | { | |
1576 | /* Check SSE2AVX. */ | |
1577 | if (!t->opcode_modifier.sse2avx|| sse2avx) | |
1578 | { | |
1579 | match |= (CPU_FLAGS_ARCH_MATCH | |
1580 | | CPU_FLAGS_AVX_MATCH); | |
1581 | /* Check AES. */ | |
1582 | if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes) | |
1583 | match |= CPU_FLAGS_AES_MATCH; | |
ce2f5b3c L |
1584 | /* Check PCLMUL. */ |
1585 | if (!x.bitfield.cpupclmul | |
1586 | || cpu.bitfield.cpupclmul) | |
1587 | match |= CPU_FLAGS_PCLMUL_MATCH; | |
a5ff0eb2 L |
1588 | } |
1589 | } | |
1590 | else | |
1591 | match |= CPU_FLAGS_ARCH_MATCH; | |
1592 | } | |
73b090a9 L |
1593 | else if (x.bitfield.cpuavx512vl) |
1594 | { | |
1595 | /* Match AVX512VL. */ | |
1596 | if (cpu.bitfield.cpuavx512vl) | |
1597 | { | |
1598 | /* Need another match. */ | |
1599 | cpu.bitfield.cpuavx512vl = 0; | |
1600 | if (!cpu_flags_all_zero (&cpu)) | |
1601 | match |= CPU_FLAGS_32BIT_MATCH; | |
1602 | else | |
1603 | match |= CPU_FLAGS_ARCH_MATCH; | |
1604 | } | |
1605 | else | |
1606 | match |= CPU_FLAGS_ARCH_MATCH; | |
1607 | } | |
a5ff0eb2 | 1608 | else |
c0f3af97 L |
1609 | match |= CPU_FLAGS_32BIT_MATCH; |
1610 | } | |
3629bb00 | 1611 | } |
c0f3af97 | 1612 | return match; |
40fb9820 L |
1613 | } |
1614 | ||
c6fb90c8 L |
1615 | static INLINE i386_operand_type |
1616 | operand_type_and (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1617 | { |
c6fb90c8 L |
1618 | switch (ARRAY_SIZE (x.array)) |
1619 | { | |
1620 | case 3: | |
1621 | x.array [2] &= y.array [2]; | |
1622 | case 2: | |
1623 | x.array [1] &= y.array [1]; | |
1624 | case 1: | |
1625 | x.array [0] &= y.array [0]; | |
1626 | break; | |
1627 | default: | |
1628 | abort (); | |
1629 | } | |
1630 | return x; | |
40fb9820 L |
1631 | } |
1632 | ||
c6fb90c8 L |
1633 | static INLINE i386_operand_type |
1634 | operand_type_or (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1635 | { |
c6fb90c8 | 1636 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1637 | { |
c6fb90c8 L |
1638 | case 3: |
1639 | x.array [2] |= y.array [2]; | |
1640 | case 2: | |
1641 | x.array [1] |= y.array [1]; | |
1642 | case 1: | |
1643 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1644 | break; |
1645 | default: | |
1646 | abort (); | |
1647 | } | |
c6fb90c8 L |
1648 | return x; |
1649 | } | |
40fb9820 | 1650 | |
c6fb90c8 L |
1651 | static INLINE i386_operand_type |
1652 | operand_type_xor (i386_operand_type x, i386_operand_type y) | |
1653 | { | |
1654 | switch (ARRAY_SIZE (x.array)) | |
1655 | { | |
1656 | case 3: | |
1657 | x.array [2] ^= y.array [2]; | |
1658 | case 2: | |
1659 | x.array [1] ^= y.array [1]; | |
1660 | case 1: | |
1661 | x.array [0] ^= y.array [0]; | |
1662 | break; | |
1663 | default: | |
1664 | abort (); | |
1665 | } | |
40fb9820 L |
1666 | return x; |
1667 | } | |
1668 | ||
1669 | static const i386_operand_type acc32 = OPERAND_TYPE_ACC32; | |
1670 | static const i386_operand_type acc64 = OPERAND_TYPE_ACC64; | |
1671 | static const i386_operand_type control = OPERAND_TYPE_CONTROL; | |
65da13b5 L |
1672 | static const i386_operand_type inoutportreg |
1673 | = OPERAND_TYPE_INOUTPORTREG; | |
40fb9820 L |
1674 | static const i386_operand_type reg16_inoutportreg |
1675 | = OPERAND_TYPE_REG16_INOUTPORTREG; | |
1676 | static const i386_operand_type disp16 = OPERAND_TYPE_DISP16; | |
1677 | static const i386_operand_type disp32 = OPERAND_TYPE_DISP32; | |
1678 | static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S; | |
1679 | static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32; | |
1680 | static const i386_operand_type anydisp | |
1681 | = OPERAND_TYPE_ANYDISP; | |
40fb9820 | 1682 | static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM; |
c0f3af97 | 1683 | static const i386_operand_type regymm = OPERAND_TYPE_REGYMM; |
43234a1e L |
1684 | static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM; |
1685 | static const i386_operand_type regmask = OPERAND_TYPE_REGMASK; | |
40fb9820 L |
1686 | static const i386_operand_type imm8 = OPERAND_TYPE_IMM8; |
1687 | static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S; | |
1688 | static const i386_operand_type imm16 = OPERAND_TYPE_IMM16; | |
1689 | static const i386_operand_type imm32 = OPERAND_TYPE_IMM32; | |
1690 | static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S; | |
1691 | static const i386_operand_type imm64 = OPERAND_TYPE_IMM64; | |
1692 | static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32; | |
1693 | static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S; | |
1694 | static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S; | |
a683cc34 | 1695 | static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4; |
40fb9820 L |
1696 | |
1697 | enum operand_type | |
1698 | { | |
1699 | reg, | |
40fb9820 L |
1700 | imm, |
1701 | disp, | |
1702 | anymem | |
1703 | }; | |
1704 | ||
c6fb90c8 | 1705 | static INLINE int |
40fb9820 L |
1706 | operand_type_check (i386_operand_type t, enum operand_type c) |
1707 | { | |
1708 | switch (c) | |
1709 | { | |
1710 | case reg: | |
1711 | return (t.bitfield.reg8 | |
1712 | || t.bitfield.reg16 | |
1713 | || t.bitfield.reg32 | |
1714 | || t.bitfield.reg64); | |
1715 | ||
40fb9820 L |
1716 | case imm: |
1717 | return (t.bitfield.imm8 | |
1718 | || t.bitfield.imm8s | |
1719 | || t.bitfield.imm16 | |
1720 | || t.bitfield.imm32 | |
1721 | || t.bitfield.imm32s | |
1722 | || t.bitfield.imm64); | |
1723 | ||
1724 | case disp: | |
1725 | return (t.bitfield.disp8 | |
1726 | || t.bitfield.disp16 | |
1727 | || t.bitfield.disp32 | |
1728 | || t.bitfield.disp32s | |
1729 | || t.bitfield.disp64); | |
1730 | ||
1731 | case anymem: | |
1732 | return (t.bitfield.disp8 | |
1733 | || t.bitfield.disp16 | |
1734 | || t.bitfield.disp32 | |
1735 | || t.bitfield.disp32s | |
1736 | || t.bitfield.disp64 | |
1737 | || t.bitfield.baseindex); | |
1738 | ||
1739 | default: | |
1740 | abort (); | |
1741 | } | |
2cfe26b6 AM |
1742 | |
1743 | return 0; | |
40fb9820 L |
1744 | } |
1745 | ||
5c07affc L |
1746 | /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on |
1747 | operand J for instruction template T. */ | |
1748 | ||
1749 | static INLINE int | |
d3ce72d0 | 1750 | match_reg_size (const insn_template *t, unsigned int j) |
5c07affc L |
1751 | { |
1752 | return !((i.types[j].bitfield.byte | |
1753 | && !t->operand_types[j].bitfield.byte) | |
1754 | || (i.types[j].bitfield.word | |
1755 | && !t->operand_types[j].bitfield.word) | |
1756 | || (i.types[j].bitfield.dword | |
1757 | && !t->operand_types[j].bitfield.dword) | |
1758 | || (i.types[j].bitfield.qword | |
1759 | && !t->operand_types[j].bitfield.qword)); | |
1760 | } | |
1761 | ||
1762 | /* Return 1 if there is no conflict in any size on operand J for | |
1763 | instruction template T. */ | |
1764 | ||
1765 | static INLINE int | |
d3ce72d0 | 1766 | match_mem_size (const insn_template *t, unsigned int j) |
5c07affc L |
1767 | { |
1768 | return (match_reg_size (t, j) | |
1769 | && !((i.types[j].bitfield.unspecified | |
af508cb9 | 1770 | && !i.broadcast |
5c07affc L |
1771 | && !t->operand_types[j].bitfield.unspecified) |
1772 | || (i.types[j].bitfield.fword | |
1773 | && !t->operand_types[j].bitfield.fword) | |
1774 | || (i.types[j].bitfield.tbyte | |
1775 | && !t->operand_types[j].bitfield.tbyte) | |
1776 | || (i.types[j].bitfield.xmmword | |
c0f3af97 L |
1777 | && !t->operand_types[j].bitfield.xmmword) |
1778 | || (i.types[j].bitfield.ymmword | |
43234a1e L |
1779 | && !t->operand_types[j].bitfield.ymmword) |
1780 | || (i.types[j].bitfield.zmmword | |
1781 | && !t->operand_types[j].bitfield.zmmword))); | |
5c07affc L |
1782 | } |
1783 | ||
1784 | /* Return 1 if there is no size conflict on any operands for | |
1785 | instruction template T. */ | |
1786 | ||
1787 | static INLINE int | |
d3ce72d0 | 1788 | operand_size_match (const insn_template *t) |
5c07affc L |
1789 | { |
1790 | unsigned int j; | |
1791 | int match = 1; | |
1792 | ||
1793 | /* Don't check jump instructions. */ | |
1794 | if (t->opcode_modifier.jump | |
1795 | || t->opcode_modifier.jumpbyte | |
1796 | || t->opcode_modifier.jumpdword | |
1797 | || t->opcode_modifier.jumpintersegment) | |
1798 | return match; | |
1799 | ||
1800 | /* Check memory and accumulator operand size. */ | |
1801 | for (j = 0; j < i.operands; j++) | |
1802 | { | |
1803 | if (t->operand_types[j].bitfield.anysize) | |
1804 | continue; | |
1805 | ||
1806 | if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j)) | |
1807 | { | |
1808 | match = 0; | |
1809 | break; | |
1810 | } | |
1811 | ||
1812 | if (i.types[j].bitfield.mem && !match_mem_size (t, j)) | |
1813 | { | |
1814 | match = 0; | |
1815 | break; | |
1816 | } | |
1817 | } | |
1818 | ||
891edac4 | 1819 | if (match) |
5c07affc | 1820 | return match; |
891edac4 L |
1821 | else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd) |
1822 | { | |
1823 | mismatch: | |
86e026a4 | 1824 | i.error = operand_size_mismatch; |
891edac4 L |
1825 | return 0; |
1826 | } | |
5c07affc L |
1827 | |
1828 | /* Check reverse. */ | |
9c2799c2 | 1829 | gas_assert (i.operands == 2); |
5c07affc L |
1830 | |
1831 | match = 1; | |
1832 | for (j = 0; j < 2; j++) | |
1833 | { | |
1834 | if (t->operand_types[j].bitfield.acc | |
1835 | && !match_reg_size (t, j ? 0 : 1)) | |
891edac4 | 1836 | goto mismatch; |
5c07affc L |
1837 | |
1838 | if (i.types[j].bitfield.mem | |
1839 | && !match_mem_size (t, j ? 0 : 1)) | |
891edac4 | 1840 | goto mismatch; |
5c07affc L |
1841 | } |
1842 | ||
1843 | return match; | |
1844 | } | |
1845 | ||
c6fb90c8 | 1846 | static INLINE int |
40fb9820 L |
1847 | operand_type_match (i386_operand_type overlap, |
1848 | i386_operand_type given) | |
1849 | { | |
1850 | i386_operand_type temp = overlap; | |
1851 | ||
1852 | temp.bitfield.jumpabsolute = 0; | |
7d5e4556 | 1853 | temp.bitfield.unspecified = 0; |
5c07affc L |
1854 | temp.bitfield.byte = 0; |
1855 | temp.bitfield.word = 0; | |
1856 | temp.bitfield.dword = 0; | |
1857 | temp.bitfield.fword = 0; | |
1858 | temp.bitfield.qword = 0; | |
1859 | temp.bitfield.tbyte = 0; | |
1860 | temp.bitfield.xmmword = 0; | |
c0f3af97 | 1861 | temp.bitfield.ymmword = 0; |
43234a1e | 1862 | temp.bitfield.zmmword = 0; |
0dfbf9d7 | 1863 | if (operand_type_all_zero (&temp)) |
891edac4 | 1864 | goto mismatch; |
40fb9820 | 1865 | |
891edac4 L |
1866 | if (given.bitfield.baseindex == overlap.bitfield.baseindex |
1867 | && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute) | |
1868 | return 1; | |
1869 | ||
1870 | mismatch: | |
a65babc9 | 1871 | i.error = operand_type_mismatch; |
891edac4 | 1872 | return 0; |
40fb9820 L |
1873 | } |
1874 | ||
7d5e4556 | 1875 | /* If given types g0 and g1 are registers they must be of the same type |
40fb9820 L |
1876 | unless the expected operand type register overlap is null. |
1877 | Note that Acc in a template matches every size of reg. */ | |
1878 | ||
c6fb90c8 | 1879 | static INLINE int |
40fb9820 L |
1880 | operand_type_register_match (i386_operand_type m0, |
1881 | i386_operand_type g0, | |
1882 | i386_operand_type t0, | |
1883 | i386_operand_type m1, | |
1884 | i386_operand_type g1, | |
1885 | i386_operand_type t1) | |
1886 | { | |
1887 | if (!operand_type_check (g0, reg)) | |
1888 | return 1; | |
1889 | ||
1890 | if (!operand_type_check (g1, reg)) | |
1891 | return 1; | |
1892 | ||
1893 | if (g0.bitfield.reg8 == g1.bitfield.reg8 | |
1894 | && g0.bitfield.reg16 == g1.bitfield.reg16 | |
1895 | && g0.bitfield.reg32 == g1.bitfield.reg32 | |
1896 | && g0.bitfield.reg64 == g1.bitfield.reg64) | |
1897 | return 1; | |
1898 | ||
1899 | if (m0.bitfield.acc) | |
1900 | { | |
1901 | t0.bitfield.reg8 = 1; | |
1902 | t0.bitfield.reg16 = 1; | |
1903 | t0.bitfield.reg32 = 1; | |
1904 | t0.bitfield.reg64 = 1; | |
1905 | } | |
1906 | ||
1907 | if (m1.bitfield.acc) | |
1908 | { | |
1909 | t1.bitfield.reg8 = 1; | |
1910 | t1.bitfield.reg16 = 1; | |
1911 | t1.bitfield.reg32 = 1; | |
1912 | t1.bitfield.reg64 = 1; | |
1913 | } | |
1914 | ||
891edac4 L |
1915 | if (!(t0.bitfield.reg8 & t1.bitfield.reg8) |
1916 | && !(t0.bitfield.reg16 & t1.bitfield.reg16) | |
1917 | && !(t0.bitfield.reg32 & t1.bitfield.reg32) | |
1918 | && !(t0.bitfield.reg64 & t1.bitfield.reg64)) | |
1919 | return 1; | |
1920 | ||
a65babc9 | 1921 | i.error = register_type_mismatch; |
891edac4 L |
1922 | |
1923 | return 0; | |
40fb9820 L |
1924 | } |
1925 | ||
4c692bc7 JB |
1926 | static INLINE unsigned int |
1927 | register_number (const reg_entry *r) | |
1928 | { | |
1929 | unsigned int nr = r->reg_num; | |
1930 | ||
1931 | if (r->reg_flags & RegRex) | |
1932 | nr += 8; | |
1933 | ||
200cbe0f L |
1934 | if (r->reg_flags & RegVRex) |
1935 | nr += 16; | |
1936 | ||
4c692bc7 JB |
1937 | return nr; |
1938 | } | |
1939 | ||
252b5132 | 1940 | static INLINE unsigned int |
40fb9820 | 1941 | mode_from_disp_size (i386_operand_type t) |
252b5132 | 1942 | { |
43234a1e | 1943 | if (t.bitfield.disp8 || t.bitfield.vec_disp8) |
40fb9820 L |
1944 | return 1; |
1945 | else if (t.bitfield.disp16 | |
1946 | || t.bitfield.disp32 | |
1947 | || t.bitfield.disp32s) | |
1948 | return 2; | |
1949 | else | |
1950 | return 0; | |
252b5132 RH |
1951 | } |
1952 | ||
1953 | static INLINE int | |
65879393 | 1954 | fits_in_signed_byte (addressT num) |
252b5132 | 1955 | { |
65879393 | 1956 | return num + 0x80 <= 0xff; |
47926f60 | 1957 | } |
252b5132 RH |
1958 | |
1959 | static INLINE int | |
65879393 | 1960 | fits_in_unsigned_byte (addressT num) |
252b5132 | 1961 | { |
65879393 | 1962 | return num <= 0xff; |
47926f60 | 1963 | } |
252b5132 RH |
1964 | |
1965 | static INLINE int | |
65879393 | 1966 | fits_in_unsigned_word (addressT num) |
252b5132 | 1967 | { |
65879393 | 1968 | return num <= 0xffff; |
47926f60 | 1969 | } |
252b5132 RH |
1970 | |
1971 | static INLINE int | |
65879393 | 1972 | fits_in_signed_word (addressT num) |
252b5132 | 1973 | { |
65879393 | 1974 | return num + 0x8000 <= 0xffff; |
47926f60 | 1975 | } |
2a962e6d | 1976 | |
3e73aa7c | 1977 | static INLINE int |
65879393 | 1978 | fits_in_signed_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
1979 | { |
1980 | #ifndef BFD64 | |
1981 | return 1; | |
1982 | #else | |
65879393 | 1983 | return num + 0x80000000 <= 0xffffffff; |
3e73aa7c JH |
1984 | #endif |
1985 | } /* fits_in_signed_long() */ | |
2a962e6d | 1986 | |
3e73aa7c | 1987 | static INLINE int |
65879393 | 1988 | fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
1989 | { |
1990 | #ifndef BFD64 | |
1991 | return 1; | |
1992 | #else | |
65879393 | 1993 | return num <= 0xffffffff; |
3e73aa7c JH |
1994 | #endif |
1995 | } /* fits_in_unsigned_long() */ | |
252b5132 | 1996 | |
43234a1e L |
1997 | static INLINE int |
1998 | fits_in_vec_disp8 (offsetT num) | |
1999 | { | |
2000 | int shift = i.memshift; | |
2001 | unsigned int mask; | |
2002 | ||
2003 | if (shift == -1) | |
2004 | abort (); | |
2005 | ||
2006 | mask = (1 << shift) - 1; | |
2007 | ||
2008 | /* Return 0 if NUM isn't properly aligned. */ | |
2009 | if ((num & mask)) | |
2010 | return 0; | |
2011 | ||
2012 | /* Check if NUM will fit in 8bit after shift. */ | |
2013 | return fits_in_signed_byte (num >> shift); | |
2014 | } | |
2015 | ||
a683cc34 SP |
2016 | static INLINE int |
2017 | fits_in_imm4 (offsetT num) | |
2018 | { | |
2019 | return (num & 0xf) == num; | |
2020 | } | |
2021 | ||
40fb9820 | 2022 | static i386_operand_type |
e3bb37b5 | 2023 | smallest_imm_type (offsetT num) |
252b5132 | 2024 | { |
40fb9820 | 2025 | i386_operand_type t; |
7ab9ffdd | 2026 | |
0dfbf9d7 | 2027 | operand_type_set (&t, 0); |
40fb9820 L |
2028 | t.bitfield.imm64 = 1; |
2029 | ||
2030 | if (cpu_arch_tune != PROCESSOR_I486 && num == 1) | |
e413e4e9 AM |
2031 | { |
2032 | /* This code is disabled on the 486 because all the Imm1 forms | |
2033 | in the opcode table are slower on the i486. They're the | |
2034 | versions with the implicitly specified single-position | |
2035 | displacement, which has another syntax if you really want to | |
2036 | use that form. */ | |
40fb9820 L |
2037 | t.bitfield.imm1 = 1; |
2038 | t.bitfield.imm8 = 1; | |
2039 | t.bitfield.imm8s = 1; | |
2040 | t.bitfield.imm16 = 1; | |
2041 | t.bitfield.imm32 = 1; | |
2042 | t.bitfield.imm32s = 1; | |
2043 | } | |
2044 | else if (fits_in_signed_byte (num)) | |
2045 | { | |
2046 | t.bitfield.imm8 = 1; | |
2047 | t.bitfield.imm8s = 1; | |
2048 | t.bitfield.imm16 = 1; | |
2049 | t.bitfield.imm32 = 1; | |
2050 | t.bitfield.imm32s = 1; | |
2051 | } | |
2052 | else if (fits_in_unsigned_byte (num)) | |
2053 | { | |
2054 | t.bitfield.imm8 = 1; | |
2055 | t.bitfield.imm16 = 1; | |
2056 | t.bitfield.imm32 = 1; | |
2057 | t.bitfield.imm32s = 1; | |
2058 | } | |
2059 | else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
2060 | { | |
2061 | t.bitfield.imm16 = 1; | |
2062 | t.bitfield.imm32 = 1; | |
2063 | t.bitfield.imm32s = 1; | |
2064 | } | |
2065 | else if (fits_in_signed_long (num)) | |
2066 | { | |
2067 | t.bitfield.imm32 = 1; | |
2068 | t.bitfield.imm32s = 1; | |
2069 | } | |
2070 | else if (fits_in_unsigned_long (num)) | |
2071 | t.bitfield.imm32 = 1; | |
2072 | ||
2073 | return t; | |
47926f60 | 2074 | } |
252b5132 | 2075 | |
847f7ad4 | 2076 | static offsetT |
e3bb37b5 | 2077 | offset_in_range (offsetT val, int size) |
847f7ad4 | 2078 | { |
508866be | 2079 | addressT mask; |
ba2adb93 | 2080 | |
847f7ad4 AM |
2081 | switch (size) |
2082 | { | |
508866be L |
2083 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
2084 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 2085 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
3e73aa7c JH |
2086 | #ifdef BFD64 |
2087 | case 8: mask = ((addressT) 2 << 63) - 1; break; | |
2088 | #endif | |
47926f60 | 2089 | default: abort (); |
847f7ad4 AM |
2090 | } |
2091 | ||
9de868bf L |
2092 | #ifdef BFD64 |
2093 | /* If BFD64, sign extend val for 32bit address mode. */ | |
2094 | if (flag_code != CODE_64BIT | |
2095 | || i.prefix[ADDR_PREFIX]) | |
3e73aa7c JH |
2096 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) |
2097 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
fa289fb8 | 2098 | #endif |
ba2adb93 | 2099 | |
47926f60 | 2100 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
847f7ad4 AM |
2101 | { |
2102 | char buf1[40], buf2[40]; | |
2103 | ||
2104 | sprint_value (buf1, val); | |
2105 | sprint_value (buf2, val & mask); | |
2106 | as_warn (_("%s shortened to %s"), buf1, buf2); | |
2107 | } | |
2108 | return val & mask; | |
2109 | } | |
2110 | ||
c32fa91d L |
2111 | enum PREFIX_GROUP |
2112 | { | |
2113 | PREFIX_EXIST = 0, | |
2114 | PREFIX_LOCK, | |
2115 | PREFIX_REP, | |
2116 | PREFIX_OTHER | |
2117 | }; | |
2118 | ||
2119 | /* Returns | |
2120 | a. PREFIX_EXIST if attempting to add a prefix where one from the | |
2121 | same class already exists. | |
2122 | b. PREFIX_LOCK if lock prefix is added. | |
2123 | c. PREFIX_REP if rep/repne prefix is added. | |
2124 | d. PREFIX_OTHER if other prefix is added. | |
2125 | */ | |
2126 | ||
2127 | static enum PREFIX_GROUP | |
e3bb37b5 | 2128 | add_prefix (unsigned int prefix) |
252b5132 | 2129 | { |
c32fa91d | 2130 | enum PREFIX_GROUP ret = PREFIX_OTHER; |
b1905489 | 2131 | unsigned int q; |
252b5132 | 2132 | |
29b0f896 AM |
2133 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
2134 | && flag_code == CODE_64BIT) | |
b1905489 | 2135 | { |
161a04f6 L |
2136 | if ((i.prefix[REX_PREFIX] & prefix & REX_W) |
2137 | || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B)) | |
2138 | && (prefix & (REX_R | REX_X | REX_B)))) | |
c32fa91d | 2139 | ret = PREFIX_EXIST; |
b1905489 JB |
2140 | q = REX_PREFIX; |
2141 | } | |
3e73aa7c | 2142 | else |
b1905489 JB |
2143 | { |
2144 | switch (prefix) | |
2145 | { | |
2146 | default: | |
2147 | abort (); | |
2148 | ||
2149 | case CS_PREFIX_OPCODE: | |
2150 | case DS_PREFIX_OPCODE: | |
2151 | case ES_PREFIX_OPCODE: | |
2152 | case FS_PREFIX_OPCODE: | |
2153 | case GS_PREFIX_OPCODE: | |
2154 | case SS_PREFIX_OPCODE: | |
2155 | q = SEG_PREFIX; | |
2156 | break; | |
2157 | ||
2158 | case REPNE_PREFIX_OPCODE: | |
2159 | case REPE_PREFIX_OPCODE: | |
c32fa91d L |
2160 | q = REP_PREFIX; |
2161 | ret = PREFIX_REP; | |
2162 | break; | |
2163 | ||
b1905489 | 2164 | case LOCK_PREFIX_OPCODE: |
c32fa91d L |
2165 | q = LOCK_PREFIX; |
2166 | ret = PREFIX_LOCK; | |
b1905489 JB |
2167 | break; |
2168 | ||
2169 | case FWAIT_OPCODE: | |
2170 | q = WAIT_PREFIX; | |
2171 | break; | |
2172 | ||
2173 | case ADDR_PREFIX_OPCODE: | |
2174 | q = ADDR_PREFIX; | |
2175 | break; | |
2176 | ||
2177 | case DATA_PREFIX_OPCODE: | |
2178 | q = DATA_PREFIX; | |
2179 | break; | |
2180 | } | |
2181 | if (i.prefix[q] != 0) | |
c32fa91d | 2182 | ret = PREFIX_EXIST; |
b1905489 | 2183 | } |
252b5132 | 2184 | |
b1905489 | 2185 | if (ret) |
252b5132 | 2186 | { |
b1905489 JB |
2187 | if (!i.prefix[q]) |
2188 | ++i.prefixes; | |
2189 | i.prefix[q] |= prefix; | |
252b5132 | 2190 | } |
b1905489 JB |
2191 | else |
2192 | as_bad (_("same type of prefix used twice")); | |
252b5132 | 2193 | |
252b5132 RH |
2194 | return ret; |
2195 | } | |
2196 | ||
2197 | static void | |
78f12dd3 | 2198 | update_code_flag (int value, int check) |
eecb386c | 2199 | { |
78f12dd3 L |
2200 | PRINTF_LIKE ((*as_error)); |
2201 | ||
1e9cc1c2 | 2202 | flag_code = (enum flag_code) value; |
40fb9820 L |
2203 | if (flag_code == CODE_64BIT) |
2204 | { | |
2205 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2206 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
40fb9820 L |
2207 | } |
2208 | else | |
2209 | { | |
2210 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2211 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
40fb9820 L |
2212 | } |
2213 | if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm ) | |
3e73aa7c | 2214 | { |
78f12dd3 L |
2215 | if (check) |
2216 | as_error = as_fatal; | |
2217 | else | |
2218 | as_error = as_bad; | |
2219 | (*as_error) (_("64bit mode not supported on `%s'."), | |
2220 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2221 | } |
40fb9820 | 2222 | if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) |
3e73aa7c | 2223 | { |
78f12dd3 L |
2224 | if (check) |
2225 | as_error = as_fatal; | |
2226 | else | |
2227 | as_error = as_bad; | |
2228 | (*as_error) (_("32bit mode not supported on `%s'."), | |
2229 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2230 | } |
eecb386c AM |
2231 | stackop_size = '\0'; |
2232 | } | |
2233 | ||
78f12dd3 L |
2234 | static void |
2235 | set_code_flag (int value) | |
2236 | { | |
2237 | update_code_flag (value, 0); | |
2238 | } | |
2239 | ||
eecb386c | 2240 | static void |
e3bb37b5 | 2241 | set_16bit_gcc_code_flag (int new_code_flag) |
252b5132 | 2242 | { |
1e9cc1c2 | 2243 | flag_code = (enum flag_code) new_code_flag; |
40fb9820 L |
2244 | if (flag_code != CODE_16BIT) |
2245 | abort (); | |
2246 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2247 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
9306ca4a | 2248 | stackop_size = LONG_MNEM_SUFFIX; |
252b5132 RH |
2249 | } |
2250 | ||
2251 | static void | |
e3bb37b5 | 2252 | set_intel_syntax (int syntax_flag) |
252b5132 RH |
2253 | { |
2254 | /* Find out if register prefixing is specified. */ | |
2255 | int ask_naked_reg = 0; | |
2256 | ||
2257 | SKIP_WHITESPACE (); | |
29b0f896 | 2258 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
252b5132 | 2259 | { |
d02603dc NC |
2260 | char *string; |
2261 | int e = get_symbol_name (&string); | |
252b5132 | 2262 | |
47926f60 | 2263 | if (strcmp (string, "prefix") == 0) |
252b5132 | 2264 | ask_naked_reg = 1; |
47926f60 | 2265 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
2266 | ask_naked_reg = -1; |
2267 | else | |
d0b47220 | 2268 | as_bad (_("bad argument to syntax directive.")); |
d02603dc | 2269 | (void) restore_line_pointer (e); |
252b5132 RH |
2270 | } |
2271 | demand_empty_rest_of_line (); | |
c3332e24 | 2272 | |
252b5132 RH |
2273 | intel_syntax = syntax_flag; |
2274 | ||
2275 | if (ask_naked_reg == 0) | |
f86103b7 AM |
2276 | allow_naked_reg = (intel_syntax |
2277 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); | |
252b5132 RH |
2278 | else |
2279 | allow_naked_reg = (ask_naked_reg < 0); | |
9306ca4a | 2280 | |
ee86248c | 2281 | expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0); |
7ab9ffdd | 2282 | |
e4a3b5a4 | 2283 | identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; |
9306ca4a | 2284 | identifier_chars['$'] = intel_syntax ? '$' : 0; |
e4a3b5a4 | 2285 | register_prefix = allow_naked_reg ? "" : "%"; |
252b5132 RH |
2286 | } |
2287 | ||
1efbbeb4 L |
2288 | static void |
2289 | set_intel_mnemonic (int mnemonic_flag) | |
2290 | { | |
e1d4d893 | 2291 | intel_mnemonic = mnemonic_flag; |
1efbbeb4 L |
2292 | } |
2293 | ||
db51cc60 L |
2294 | static void |
2295 | set_allow_index_reg (int flag) | |
2296 | { | |
2297 | allow_index_reg = flag; | |
2298 | } | |
2299 | ||
cb19c032 | 2300 | static void |
7bab8ab5 | 2301 | set_check (int what) |
cb19c032 | 2302 | { |
7bab8ab5 JB |
2303 | enum check_kind *kind; |
2304 | const char *str; | |
2305 | ||
2306 | if (what) | |
2307 | { | |
2308 | kind = &operand_check; | |
2309 | str = "operand"; | |
2310 | } | |
2311 | else | |
2312 | { | |
2313 | kind = &sse_check; | |
2314 | str = "sse"; | |
2315 | } | |
2316 | ||
cb19c032 L |
2317 | SKIP_WHITESPACE (); |
2318 | ||
2319 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
2320 | { | |
d02603dc NC |
2321 | char *string; |
2322 | int e = get_symbol_name (&string); | |
cb19c032 L |
2323 | |
2324 | if (strcmp (string, "none") == 0) | |
7bab8ab5 | 2325 | *kind = check_none; |
cb19c032 | 2326 | else if (strcmp (string, "warning") == 0) |
7bab8ab5 | 2327 | *kind = check_warning; |
cb19c032 | 2328 | else if (strcmp (string, "error") == 0) |
7bab8ab5 | 2329 | *kind = check_error; |
cb19c032 | 2330 | else |
7bab8ab5 | 2331 | as_bad (_("bad argument to %s_check directive."), str); |
d02603dc | 2332 | (void) restore_line_pointer (e); |
cb19c032 L |
2333 | } |
2334 | else | |
7bab8ab5 | 2335 | as_bad (_("missing argument for %s_check directive"), str); |
cb19c032 L |
2336 | |
2337 | demand_empty_rest_of_line (); | |
2338 | } | |
2339 | ||
8a9036a4 L |
2340 | static void |
2341 | check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED, | |
1e9cc1c2 | 2342 | i386_cpu_flags new_flag ATTRIBUTE_UNUSED) |
8a9036a4 L |
2343 | { |
2344 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2345 | static const char *arch; | |
2346 | ||
2347 | /* Intel LIOM is only supported on ELF. */ | |
2348 | if (!IS_ELF) | |
2349 | return; | |
2350 | ||
2351 | if (!arch) | |
2352 | { | |
2353 | /* Use cpu_arch_name if it is set in md_parse_option. Otherwise | |
2354 | use default_arch. */ | |
2355 | arch = cpu_arch_name; | |
2356 | if (!arch) | |
2357 | arch = default_arch; | |
2358 | } | |
2359 | ||
81486035 L |
2360 | /* If we are targeting Intel MCU, we must enable it. */ |
2361 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU | |
2362 | || new_flag.bitfield.cpuiamcu) | |
2363 | return; | |
2364 | ||
3632d14b | 2365 | /* If we are targeting Intel L1OM, we must enable it. */ |
8a9036a4 | 2366 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM |
1e9cc1c2 | 2367 | || new_flag.bitfield.cpul1om) |
8a9036a4 | 2368 | return; |
76ba9986 | 2369 | |
7a9068fe L |
2370 | /* If we are targeting Intel K1OM, we must enable it. */ |
2371 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM | |
2372 | || new_flag.bitfield.cpuk1om) | |
2373 | return; | |
2374 | ||
8a9036a4 L |
2375 | as_bad (_("`%s' is not supported on `%s'"), name, arch); |
2376 | #endif | |
2377 | } | |
2378 | ||
e413e4e9 | 2379 | static void |
e3bb37b5 | 2380 | set_cpu_arch (int dummy ATTRIBUTE_UNUSED) |
e413e4e9 | 2381 | { |
47926f60 | 2382 | SKIP_WHITESPACE (); |
e413e4e9 | 2383 | |
29b0f896 | 2384 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
e413e4e9 | 2385 | { |
d02603dc NC |
2386 | char *string; |
2387 | int e = get_symbol_name (&string); | |
91d6fa6a | 2388 | unsigned int j; |
40fb9820 | 2389 | i386_cpu_flags flags; |
e413e4e9 | 2390 | |
91d6fa6a | 2391 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
e413e4e9 | 2392 | { |
91d6fa6a | 2393 | if (strcmp (string, cpu_arch[j].name) == 0) |
e413e4e9 | 2394 | { |
91d6fa6a | 2395 | check_cpu_arch_compatible (string, cpu_arch[j].flags); |
8a9036a4 | 2396 | |
5c6af06e JB |
2397 | if (*string != '.') |
2398 | { | |
91d6fa6a | 2399 | cpu_arch_name = cpu_arch[j].name; |
5c6af06e | 2400 | cpu_sub_arch_name = NULL; |
91d6fa6a | 2401 | cpu_arch_flags = cpu_arch[j].flags; |
40fb9820 L |
2402 | if (flag_code == CODE_64BIT) |
2403 | { | |
2404 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2405 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
2406 | } | |
2407 | else | |
2408 | { | |
2409 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2410 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
2411 | } | |
91d6fa6a NC |
2412 | cpu_arch_isa = cpu_arch[j].type; |
2413 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
ccc9c027 L |
2414 | if (!cpu_arch_tune_set) |
2415 | { | |
2416 | cpu_arch_tune = cpu_arch_isa; | |
2417 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
2418 | } | |
5c6af06e JB |
2419 | break; |
2420 | } | |
40fb9820 | 2421 | |
293f5f65 L |
2422 | flags = cpu_flags_or (cpu_arch_flags, |
2423 | cpu_arch[j].flags); | |
81486035 L |
2424 | |
2425 | if (!valid_iamcu_cpu_flags (&flags)) | |
2426 | as_fatal (_("`%s' isn't valid for Intel MCU"), | |
2427 | cpu_arch[j].name); | |
2428 | else if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
5c6af06e | 2429 | { |
6305a203 L |
2430 | if (cpu_sub_arch_name) |
2431 | { | |
2432 | char *name = cpu_sub_arch_name; | |
2433 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 2434 | cpu_arch[j].name, |
1bf57e9f | 2435 | (const char *) NULL); |
6305a203 L |
2436 | free (name); |
2437 | } | |
2438 | else | |
91d6fa6a | 2439 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
40fb9820 | 2440 | cpu_arch_flags = flags; |
a586129e | 2441 | cpu_arch_isa_flags = flags; |
5c6af06e | 2442 | } |
d02603dc | 2443 | (void) restore_line_pointer (e); |
5c6af06e JB |
2444 | demand_empty_rest_of_line (); |
2445 | return; | |
e413e4e9 AM |
2446 | } |
2447 | } | |
293f5f65 L |
2448 | |
2449 | if (*string == '.' && j >= ARRAY_SIZE (cpu_arch)) | |
2450 | { | |
2451 | /* Disable an ISA entension. */ | |
2452 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) | |
2453 | if (strcmp (string + 1, cpu_noarch [j].name) == 0) | |
2454 | { | |
2455 | flags = cpu_flags_and_not (cpu_arch_flags, | |
2456 | cpu_noarch[j].flags); | |
2457 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
2458 | { | |
2459 | if (cpu_sub_arch_name) | |
2460 | { | |
2461 | char *name = cpu_sub_arch_name; | |
2462 | cpu_sub_arch_name = concat (name, string, | |
2463 | (const char *) NULL); | |
2464 | free (name); | |
2465 | } | |
2466 | else | |
2467 | cpu_sub_arch_name = xstrdup (string); | |
2468 | cpu_arch_flags = flags; | |
2469 | cpu_arch_isa_flags = flags; | |
2470 | } | |
2471 | (void) restore_line_pointer (e); | |
2472 | demand_empty_rest_of_line (); | |
2473 | return; | |
2474 | } | |
2475 | ||
2476 | j = ARRAY_SIZE (cpu_arch); | |
2477 | } | |
2478 | ||
91d6fa6a | 2479 | if (j >= ARRAY_SIZE (cpu_arch)) |
e413e4e9 AM |
2480 | as_bad (_("no such architecture: `%s'"), string); |
2481 | ||
2482 | *input_line_pointer = e; | |
2483 | } | |
2484 | else | |
2485 | as_bad (_("missing cpu architecture")); | |
2486 | ||
fddf5b5b AM |
2487 | no_cond_jump_promotion = 0; |
2488 | if (*input_line_pointer == ',' | |
29b0f896 | 2489 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
fddf5b5b | 2490 | { |
d02603dc NC |
2491 | char *string; |
2492 | char e; | |
2493 | ||
2494 | ++input_line_pointer; | |
2495 | e = get_symbol_name (&string); | |
fddf5b5b AM |
2496 | |
2497 | if (strcmp (string, "nojumps") == 0) | |
2498 | no_cond_jump_promotion = 1; | |
2499 | else if (strcmp (string, "jumps") == 0) | |
2500 | ; | |
2501 | else | |
2502 | as_bad (_("no such architecture modifier: `%s'"), string); | |
2503 | ||
d02603dc | 2504 | (void) restore_line_pointer (e); |
fddf5b5b AM |
2505 | } |
2506 | ||
e413e4e9 AM |
2507 | demand_empty_rest_of_line (); |
2508 | } | |
2509 | ||
8a9036a4 L |
2510 | enum bfd_architecture |
2511 | i386_arch (void) | |
2512 | { | |
3632d14b | 2513 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 L |
2514 | { |
2515 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2516 | || flag_code != CODE_64BIT) | |
2517 | as_fatal (_("Intel L1OM is 64bit ELF only")); | |
2518 | return bfd_arch_l1om; | |
2519 | } | |
7a9068fe L |
2520 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2521 | { | |
2522 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2523 | || flag_code != CODE_64BIT) | |
2524 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2525 | return bfd_arch_k1om; | |
2526 | } | |
81486035 L |
2527 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
2528 | { | |
2529 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2530 | || flag_code == CODE_64BIT) | |
2531 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2532 | return bfd_arch_iamcu; | |
2533 | } | |
8a9036a4 L |
2534 | else |
2535 | return bfd_arch_i386; | |
2536 | } | |
2537 | ||
b9d79e03 | 2538 | unsigned long |
7016a5d5 | 2539 | i386_mach (void) |
b9d79e03 | 2540 | { |
351f65ca | 2541 | if (!strncmp (default_arch, "x86_64", 6)) |
8a9036a4 | 2542 | { |
3632d14b | 2543 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 2544 | { |
351f65ca L |
2545 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour |
2546 | || default_arch[6] != '\0') | |
8a9036a4 L |
2547 | as_fatal (_("Intel L1OM is 64bit ELF only")); |
2548 | return bfd_mach_l1om; | |
2549 | } | |
7a9068fe L |
2550 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2551 | { | |
2552 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2553 | || default_arch[6] != '\0') | |
2554 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2555 | return bfd_mach_k1om; | |
2556 | } | |
351f65ca | 2557 | else if (default_arch[6] == '\0') |
8a9036a4 | 2558 | return bfd_mach_x86_64; |
351f65ca L |
2559 | else |
2560 | return bfd_mach_x64_32; | |
8a9036a4 | 2561 | } |
5197d474 L |
2562 | else if (!strcmp (default_arch, "i386") |
2563 | || !strcmp (default_arch, "iamcu")) | |
81486035 L |
2564 | { |
2565 | if (cpu_arch_isa == PROCESSOR_IAMCU) | |
2566 | { | |
2567 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
2568 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2569 | return bfd_mach_i386_iamcu; | |
2570 | } | |
2571 | else | |
2572 | return bfd_mach_i386_i386; | |
2573 | } | |
b9d79e03 | 2574 | else |
2b5d6a91 | 2575 | as_fatal (_("unknown architecture")); |
b9d79e03 | 2576 | } |
b9d79e03 | 2577 | \f |
252b5132 | 2578 | void |
7016a5d5 | 2579 | md_begin (void) |
252b5132 RH |
2580 | { |
2581 | const char *hash_err; | |
2582 | ||
47926f60 | 2583 | /* Initialize op_hash hash table. */ |
252b5132 RH |
2584 | op_hash = hash_new (); |
2585 | ||
2586 | { | |
d3ce72d0 | 2587 | const insn_template *optab; |
29b0f896 | 2588 | templates *core_optab; |
252b5132 | 2589 | |
47926f60 KH |
2590 | /* Setup for loop. */ |
2591 | optab = i386_optab; | |
add39d23 | 2592 | core_optab = XNEW (templates); |
252b5132 RH |
2593 | core_optab->start = optab; |
2594 | ||
2595 | while (1) | |
2596 | { | |
2597 | ++optab; | |
2598 | if (optab->name == NULL | |
2599 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
2600 | { | |
2601 | /* different name --> ship out current template list; | |
47926f60 | 2602 | add to hash table; & begin anew. */ |
252b5132 RH |
2603 | core_optab->end = optab; |
2604 | hash_err = hash_insert (op_hash, | |
2605 | (optab - 1)->name, | |
5a49b8ac | 2606 | (void *) core_optab); |
252b5132 RH |
2607 | if (hash_err) |
2608 | { | |
b37df7c4 | 2609 | as_fatal (_("can't hash %s: %s"), |
252b5132 RH |
2610 | (optab - 1)->name, |
2611 | hash_err); | |
2612 | } | |
2613 | if (optab->name == NULL) | |
2614 | break; | |
add39d23 | 2615 | core_optab = XNEW (templates); |
252b5132 RH |
2616 | core_optab->start = optab; |
2617 | } | |
2618 | } | |
2619 | } | |
2620 | ||
47926f60 | 2621 | /* Initialize reg_hash hash table. */ |
252b5132 RH |
2622 | reg_hash = hash_new (); |
2623 | { | |
29b0f896 | 2624 | const reg_entry *regtab; |
c3fe08fa | 2625 | unsigned int regtab_size = i386_regtab_size; |
252b5132 | 2626 | |
c3fe08fa | 2627 | for (regtab = i386_regtab; regtab_size--; regtab++) |
252b5132 | 2628 | { |
5a49b8ac | 2629 | hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab); |
252b5132 | 2630 | if (hash_err) |
b37df7c4 | 2631 | as_fatal (_("can't hash %s: %s"), |
3e73aa7c JH |
2632 | regtab->reg_name, |
2633 | hash_err); | |
252b5132 RH |
2634 | } |
2635 | } | |
2636 | ||
47926f60 | 2637 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 | 2638 | { |
29b0f896 AM |
2639 | int c; |
2640 | char *p; | |
252b5132 RH |
2641 | |
2642 | for (c = 0; c < 256; c++) | |
2643 | { | |
3882b010 | 2644 | if (ISDIGIT (c)) |
252b5132 RH |
2645 | { |
2646 | digit_chars[c] = c; | |
2647 | mnemonic_chars[c] = c; | |
2648 | register_chars[c] = c; | |
2649 | operand_chars[c] = c; | |
2650 | } | |
3882b010 | 2651 | else if (ISLOWER (c)) |
252b5132 RH |
2652 | { |
2653 | mnemonic_chars[c] = c; | |
2654 | register_chars[c] = c; | |
2655 | operand_chars[c] = c; | |
2656 | } | |
3882b010 | 2657 | else if (ISUPPER (c)) |
252b5132 | 2658 | { |
3882b010 | 2659 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
2660 | register_chars[c] = mnemonic_chars[c]; |
2661 | operand_chars[c] = c; | |
2662 | } | |
43234a1e L |
2663 | else if (c == '{' || c == '}') |
2664 | operand_chars[c] = c; | |
252b5132 | 2665 | |
3882b010 | 2666 | if (ISALPHA (c) || ISDIGIT (c)) |
252b5132 RH |
2667 | identifier_chars[c] = c; |
2668 | else if (c >= 128) | |
2669 | { | |
2670 | identifier_chars[c] = c; | |
2671 | operand_chars[c] = c; | |
2672 | } | |
2673 | } | |
2674 | ||
2675 | #ifdef LEX_AT | |
2676 | identifier_chars['@'] = '@'; | |
32137342 NC |
2677 | #endif |
2678 | #ifdef LEX_QM | |
2679 | identifier_chars['?'] = '?'; | |
2680 | operand_chars['?'] = '?'; | |
252b5132 | 2681 | #endif |
252b5132 | 2682 | digit_chars['-'] = '-'; |
c0f3af97 | 2683 | mnemonic_chars['_'] = '_'; |
791fe849 | 2684 | mnemonic_chars['-'] = '-'; |
0003779b | 2685 | mnemonic_chars['.'] = '.'; |
252b5132 RH |
2686 | identifier_chars['_'] = '_'; |
2687 | identifier_chars['.'] = '.'; | |
2688 | ||
2689 | for (p = operand_special_chars; *p != '\0'; p++) | |
2690 | operand_chars[(unsigned char) *p] = *p; | |
2691 | } | |
2692 | ||
a4447b93 RH |
2693 | if (flag_code == CODE_64BIT) |
2694 | { | |
ca19b261 KT |
2695 | #if defined (OBJ_COFF) && defined (TE_PE) |
2696 | x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour | |
2697 | ? 32 : 16); | |
2698 | #else | |
a4447b93 | 2699 | x86_dwarf2_return_column = 16; |
ca19b261 | 2700 | #endif |
61ff971f | 2701 | x86_cie_data_alignment = -8; |
a4447b93 RH |
2702 | } |
2703 | else | |
2704 | { | |
2705 | x86_dwarf2_return_column = 8; | |
2706 | x86_cie_data_alignment = -4; | |
2707 | } | |
252b5132 RH |
2708 | } |
2709 | ||
2710 | void | |
e3bb37b5 | 2711 | i386_print_statistics (FILE *file) |
252b5132 RH |
2712 | { |
2713 | hash_print_statistics (file, "i386 opcode", op_hash); | |
2714 | hash_print_statistics (file, "i386 register", reg_hash); | |
2715 | } | |
2716 | \f | |
252b5132 RH |
2717 | #ifdef DEBUG386 |
2718 | ||
ce8a8b2f | 2719 | /* Debugging routines for md_assemble. */ |
d3ce72d0 | 2720 | static void pte (insn_template *); |
40fb9820 | 2721 | static void pt (i386_operand_type); |
e3bb37b5 L |
2722 | static void pe (expressionS *); |
2723 | static void ps (symbolS *); | |
252b5132 RH |
2724 | |
2725 | static void | |
e3bb37b5 | 2726 | pi (char *line, i386_insn *x) |
252b5132 | 2727 | { |
09137c09 | 2728 | unsigned int j; |
252b5132 RH |
2729 | |
2730 | fprintf (stdout, "%s: template ", line); | |
2731 | pte (&x->tm); | |
09f131f2 JH |
2732 | fprintf (stdout, " address: base %s index %s scale %x\n", |
2733 | x->base_reg ? x->base_reg->reg_name : "none", | |
2734 | x->index_reg ? x->index_reg->reg_name : "none", | |
2735 | x->log2_scale_factor); | |
2736 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 2737 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
2738 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
2739 | x->sib.base, x->sib.index, x->sib.scale); | |
2740 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
161a04f6 L |
2741 | (x->rex & REX_W) != 0, |
2742 | (x->rex & REX_R) != 0, | |
2743 | (x->rex & REX_X) != 0, | |
2744 | (x->rex & REX_B) != 0); | |
09137c09 | 2745 | for (j = 0; j < x->operands; j++) |
252b5132 | 2746 | { |
09137c09 SP |
2747 | fprintf (stdout, " #%d: ", j + 1); |
2748 | pt (x->types[j]); | |
252b5132 | 2749 | fprintf (stdout, "\n"); |
09137c09 SP |
2750 | if (x->types[j].bitfield.reg8 |
2751 | || x->types[j].bitfield.reg16 | |
2752 | || x->types[j].bitfield.reg32 | |
2753 | || x->types[j].bitfield.reg64 | |
2754 | || x->types[j].bitfield.regmmx | |
2755 | || x->types[j].bitfield.regxmm | |
2756 | || x->types[j].bitfield.regymm | |
43234a1e | 2757 | || x->types[j].bitfield.regzmm |
09137c09 SP |
2758 | || x->types[j].bitfield.sreg2 |
2759 | || x->types[j].bitfield.sreg3 | |
2760 | || x->types[j].bitfield.control | |
2761 | || x->types[j].bitfield.debug | |
2762 | || x->types[j].bitfield.test) | |
2763 | fprintf (stdout, "%s\n", x->op[j].regs->reg_name); | |
2764 | if (operand_type_check (x->types[j], imm)) | |
2765 | pe (x->op[j].imms); | |
2766 | if (operand_type_check (x->types[j], disp)) | |
2767 | pe (x->op[j].disps); | |
252b5132 RH |
2768 | } |
2769 | } | |
2770 | ||
2771 | static void | |
d3ce72d0 | 2772 | pte (insn_template *t) |
252b5132 | 2773 | { |
09137c09 | 2774 | unsigned int j; |
252b5132 | 2775 | fprintf (stdout, " %d operands ", t->operands); |
47926f60 | 2776 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
2777 | if (t->extension_opcode != None) |
2778 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
40fb9820 | 2779 | if (t->opcode_modifier.d) |
252b5132 | 2780 | fprintf (stdout, "D"); |
40fb9820 | 2781 | if (t->opcode_modifier.w) |
252b5132 RH |
2782 | fprintf (stdout, "W"); |
2783 | fprintf (stdout, "\n"); | |
09137c09 | 2784 | for (j = 0; j < t->operands; j++) |
252b5132 | 2785 | { |
09137c09 SP |
2786 | fprintf (stdout, " #%d type ", j + 1); |
2787 | pt (t->operand_types[j]); | |
252b5132 RH |
2788 | fprintf (stdout, "\n"); |
2789 | } | |
2790 | } | |
2791 | ||
2792 | static void | |
e3bb37b5 | 2793 | pe (expressionS *e) |
252b5132 | 2794 | { |
24eab124 | 2795 | fprintf (stdout, " operation %d\n", e->X_op); |
b77ad1d4 AM |
2796 | fprintf (stdout, " add_number %ld (%lx)\n", |
2797 | (long) e->X_add_number, (long) e->X_add_number); | |
252b5132 RH |
2798 | if (e->X_add_symbol) |
2799 | { | |
2800 | fprintf (stdout, " add_symbol "); | |
2801 | ps (e->X_add_symbol); | |
2802 | fprintf (stdout, "\n"); | |
2803 | } | |
2804 | if (e->X_op_symbol) | |
2805 | { | |
2806 | fprintf (stdout, " op_symbol "); | |
2807 | ps (e->X_op_symbol); | |
2808 | fprintf (stdout, "\n"); | |
2809 | } | |
2810 | } | |
2811 | ||
2812 | static void | |
e3bb37b5 | 2813 | ps (symbolS *s) |
252b5132 RH |
2814 | { |
2815 | fprintf (stdout, "%s type %s%s", | |
2816 | S_GET_NAME (s), | |
2817 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
2818 | segment_name (S_GET_SEGMENT (s))); | |
2819 | } | |
2820 | ||
7b81dfbb | 2821 | static struct type_name |
252b5132 | 2822 | { |
40fb9820 L |
2823 | i386_operand_type mask; |
2824 | const char *name; | |
252b5132 | 2825 | } |
7b81dfbb | 2826 | const type_names[] = |
252b5132 | 2827 | { |
40fb9820 L |
2828 | { OPERAND_TYPE_REG8, "r8" }, |
2829 | { OPERAND_TYPE_REG16, "r16" }, | |
2830 | { OPERAND_TYPE_REG32, "r32" }, | |
2831 | { OPERAND_TYPE_REG64, "r64" }, | |
2832 | { OPERAND_TYPE_IMM8, "i8" }, | |
2833 | { OPERAND_TYPE_IMM8, "i8s" }, | |
2834 | { OPERAND_TYPE_IMM16, "i16" }, | |
2835 | { OPERAND_TYPE_IMM32, "i32" }, | |
2836 | { OPERAND_TYPE_IMM32S, "i32s" }, | |
2837 | { OPERAND_TYPE_IMM64, "i64" }, | |
2838 | { OPERAND_TYPE_IMM1, "i1" }, | |
2839 | { OPERAND_TYPE_BASEINDEX, "BaseIndex" }, | |
2840 | { OPERAND_TYPE_DISP8, "d8" }, | |
2841 | { OPERAND_TYPE_DISP16, "d16" }, | |
2842 | { OPERAND_TYPE_DISP32, "d32" }, | |
2843 | { OPERAND_TYPE_DISP32S, "d32s" }, | |
2844 | { OPERAND_TYPE_DISP64, "d64" }, | |
43234a1e | 2845 | { OPERAND_TYPE_VEC_DISP8, "Vector d8" }, |
40fb9820 L |
2846 | { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" }, |
2847 | { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" }, | |
2848 | { OPERAND_TYPE_CONTROL, "control reg" }, | |
2849 | { OPERAND_TYPE_TEST, "test reg" }, | |
2850 | { OPERAND_TYPE_DEBUG, "debug reg" }, | |
2851 | { OPERAND_TYPE_FLOATREG, "FReg" }, | |
2852 | { OPERAND_TYPE_FLOATACC, "FAcc" }, | |
2853 | { OPERAND_TYPE_SREG2, "SReg2" }, | |
2854 | { OPERAND_TYPE_SREG3, "SReg3" }, | |
2855 | { OPERAND_TYPE_ACC, "Acc" }, | |
2856 | { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" }, | |
2857 | { OPERAND_TYPE_REGMMX, "rMMX" }, | |
2858 | { OPERAND_TYPE_REGXMM, "rXMM" }, | |
0349dc08 | 2859 | { OPERAND_TYPE_REGYMM, "rYMM" }, |
43234a1e L |
2860 | { OPERAND_TYPE_REGZMM, "rZMM" }, |
2861 | { OPERAND_TYPE_REGMASK, "Mask reg" }, | |
40fb9820 | 2862 | { OPERAND_TYPE_ESSEG, "es" }, |
252b5132 RH |
2863 | }; |
2864 | ||
2865 | static void | |
40fb9820 | 2866 | pt (i386_operand_type t) |
252b5132 | 2867 | { |
40fb9820 | 2868 | unsigned int j; |
c6fb90c8 | 2869 | i386_operand_type a; |
252b5132 | 2870 | |
40fb9820 | 2871 | for (j = 0; j < ARRAY_SIZE (type_names); j++) |
c6fb90c8 L |
2872 | { |
2873 | a = operand_type_and (t, type_names[j].mask); | |
0349dc08 | 2874 | if (!operand_type_all_zero (&a)) |
c6fb90c8 L |
2875 | fprintf (stdout, "%s, ", type_names[j].name); |
2876 | } | |
252b5132 RH |
2877 | fflush (stdout); |
2878 | } | |
2879 | ||
2880 | #endif /* DEBUG386 */ | |
2881 | \f | |
252b5132 | 2882 | static bfd_reloc_code_real_type |
3956db08 | 2883 | reloc (unsigned int size, |
64e74474 AM |
2884 | int pcrel, |
2885 | int sign, | |
2886 | bfd_reloc_code_real_type other) | |
252b5132 | 2887 | { |
47926f60 | 2888 | if (other != NO_RELOC) |
3956db08 | 2889 | { |
91d6fa6a | 2890 | reloc_howto_type *rel; |
3956db08 JB |
2891 | |
2892 | if (size == 8) | |
2893 | switch (other) | |
2894 | { | |
64e74474 AM |
2895 | case BFD_RELOC_X86_64_GOT32: |
2896 | return BFD_RELOC_X86_64_GOT64; | |
2897 | break; | |
553d1284 L |
2898 | case BFD_RELOC_X86_64_GOTPLT64: |
2899 | return BFD_RELOC_X86_64_GOTPLT64; | |
2900 | break; | |
64e74474 AM |
2901 | case BFD_RELOC_X86_64_PLTOFF64: |
2902 | return BFD_RELOC_X86_64_PLTOFF64; | |
2903 | break; | |
2904 | case BFD_RELOC_X86_64_GOTPC32: | |
2905 | other = BFD_RELOC_X86_64_GOTPC64; | |
2906 | break; | |
2907 | case BFD_RELOC_X86_64_GOTPCREL: | |
2908 | other = BFD_RELOC_X86_64_GOTPCREL64; | |
2909 | break; | |
2910 | case BFD_RELOC_X86_64_TPOFF32: | |
2911 | other = BFD_RELOC_X86_64_TPOFF64; | |
2912 | break; | |
2913 | case BFD_RELOC_X86_64_DTPOFF32: | |
2914 | other = BFD_RELOC_X86_64_DTPOFF64; | |
2915 | break; | |
2916 | default: | |
2917 | break; | |
3956db08 | 2918 | } |
e05278af | 2919 | |
8ce3d284 | 2920 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
2921 | if (other == BFD_RELOC_SIZE32) |
2922 | { | |
2923 | if (size == 8) | |
1ab668bf | 2924 | other = BFD_RELOC_SIZE64; |
8fd4256d | 2925 | if (pcrel) |
1ab668bf AM |
2926 | { |
2927 | as_bad (_("there are no pc-relative size relocations")); | |
2928 | return NO_RELOC; | |
2929 | } | |
8fd4256d | 2930 | } |
8ce3d284 | 2931 | #endif |
8fd4256d | 2932 | |
e05278af | 2933 | /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ |
f2d8a97c | 2934 | if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc)) |
e05278af JB |
2935 | sign = -1; |
2936 | ||
91d6fa6a NC |
2937 | rel = bfd_reloc_type_lookup (stdoutput, other); |
2938 | if (!rel) | |
3956db08 | 2939 | as_bad (_("unknown relocation (%u)"), other); |
91d6fa6a | 2940 | else if (size != bfd_get_reloc_size (rel)) |
3956db08 | 2941 | as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), |
91d6fa6a | 2942 | bfd_get_reloc_size (rel), |
3956db08 | 2943 | size); |
91d6fa6a | 2944 | else if (pcrel && !rel->pc_relative) |
3956db08 | 2945 | as_bad (_("non-pc-relative relocation for pc-relative field")); |
91d6fa6a | 2946 | else if ((rel->complain_on_overflow == complain_overflow_signed |
3956db08 | 2947 | && !sign) |
91d6fa6a | 2948 | || (rel->complain_on_overflow == complain_overflow_unsigned |
64e74474 | 2949 | && sign > 0)) |
3956db08 JB |
2950 | as_bad (_("relocated field and relocation type differ in signedness")); |
2951 | else | |
2952 | return other; | |
2953 | return NO_RELOC; | |
2954 | } | |
252b5132 RH |
2955 | |
2956 | if (pcrel) | |
2957 | { | |
3e73aa7c | 2958 | if (!sign) |
3956db08 | 2959 | as_bad (_("there are no unsigned pc-relative relocations")); |
252b5132 RH |
2960 | switch (size) |
2961 | { | |
2962 | case 1: return BFD_RELOC_8_PCREL; | |
2963 | case 2: return BFD_RELOC_16_PCREL; | |
d258b828 | 2964 | case 4: return BFD_RELOC_32_PCREL; |
d6ab8113 | 2965 | case 8: return BFD_RELOC_64_PCREL; |
252b5132 | 2966 | } |
3956db08 | 2967 | as_bad (_("cannot do %u byte pc-relative relocation"), size); |
252b5132 RH |
2968 | } |
2969 | else | |
2970 | { | |
3956db08 | 2971 | if (sign > 0) |
e5cb08ac | 2972 | switch (size) |
3e73aa7c JH |
2973 | { |
2974 | case 4: return BFD_RELOC_X86_64_32S; | |
2975 | } | |
2976 | else | |
2977 | switch (size) | |
2978 | { | |
2979 | case 1: return BFD_RELOC_8; | |
2980 | case 2: return BFD_RELOC_16; | |
2981 | case 4: return BFD_RELOC_32; | |
2982 | case 8: return BFD_RELOC_64; | |
2983 | } | |
3956db08 JB |
2984 | as_bad (_("cannot do %s %u byte relocation"), |
2985 | sign > 0 ? "signed" : "unsigned", size); | |
252b5132 RH |
2986 | } |
2987 | ||
0cc9e1d3 | 2988 | return NO_RELOC; |
252b5132 RH |
2989 | } |
2990 | ||
47926f60 KH |
2991 | /* Here we decide which fixups can be adjusted to make them relative to |
2992 | the beginning of the section instead of the symbol. Basically we need | |
2993 | to make sure that the dynamic relocations are done correctly, so in | |
2994 | some cases we force the original symbol to be used. */ | |
2995 | ||
252b5132 | 2996 | int |
e3bb37b5 | 2997 | tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) |
252b5132 | 2998 | { |
6d249963 | 2999 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 3000 | if (!IS_ELF) |
31312f95 AM |
3001 | return 1; |
3002 | ||
a161fe53 AM |
3003 | /* Don't adjust pc-relative references to merge sections in 64-bit |
3004 | mode. */ | |
3005 | if (use_rela_relocations | |
3006 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 | |
3007 | && fixP->fx_pcrel) | |
252b5132 | 3008 | return 0; |
31312f95 | 3009 | |
8d01d9a9 AJ |
3010 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
3011 | and changed later by validate_fix. */ | |
3012 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol | |
3013 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) | |
3014 | return 0; | |
3015 | ||
8fd4256d L |
3016 | /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol |
3017 | for size relocations. */ | |
3018 | if (fixP->fx_r_type == BFD_RELOC_SIZE32 | |
3019 | || fixP->fx_r_type == BFD_RELOC_SIZE64 | |
3020 | || fixP->fx_r_type == BFD_RELOC_386_GOTOFF | |
252b5132 RH |
3021 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 |
3022 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 | |
02a86693 | 3023 | || fixP->fx_r_type == BFD_RELOC_386_GOT32X |
13ae64f3 JJ |
3024 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
3025 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM | |
3026 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 | |
3027 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 | |
37e55690 JJ |
3028 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
3029 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE | |
13ae64f3 JJ |
3030 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
3031 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE | |
67a4f2b7 AO |
3032 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC |
3033 | || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL | |
3e73aa7c JH |
3034 | || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 |
3035 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 | |
80b3ee89 | 3036 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
56ceb5b5 L |
3037 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX |
3038 | || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX | |
bffbf940 JJ |
3039 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
3040 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD | |
3041 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 | |
d6ab8113 | 3042 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 |
bffbf940 JJ |
3043 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF |
3044 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 | |
d6ab8113 JB |
3045 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 |
3046 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 | |
67a4f2b7 AO |
3047 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
3048 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL | |
252b5132 RH |
3049 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
3050 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
3051 | return 0; | |
31312f95 | 3052 | #endif |
252b5132 RH |
3053 | return 1; |
3054 | } | |
252b5132 | 3055 | |
b4cac588 | 3056 | static int |
e3bb37b5 | 3057 | intel_float_operand (const char *mnemonic) |
252b5132 | 3058 | { |
9306ca4a JB |
3059 | /* Note that the value returned is meaningful only for opcodes with (memory) |
3060 | operands, hence the code here is free to improperly handle opcodes that | |
3061 | have no operands (for better performance and smaller code). */ | |
3062 | ||
3063 | if (mnemonic[0] != 'f') | |
3064 | return 0; /* non-math */ | |
3065 | ||
3066 | switch (mnemonic[1]) | |
3067 | { | |
3068 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and | |
3069 | the fs segment override prefix not currently handled because no | |
3070 | call path can make opcodes without operands get here */ | |
3071 | case 'i': | |
3072 | return 2 /* integer op */; | |
3073 | case 'l': | |
3074 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) | |
3075 | return 3; /* fldcw/fldenv */ | |
3076 | break; | |
3077 | case 'n': | |
3078 | if (mnemonic[2] != 'o' /* fnop */) | |
3079 | return 3; /* non-waiting control op */ | |
3080 | break; | |
3081 | case 'r': | |
3082 | if (mnemonic[2] == 's') | |
3083 | return 3; /* frstor/frstpm */ | |
3084 | break; | |
3085 | case 's': | |
3086 | if (mnemonic[2] == 'a') | |
3087 | return 3; /* fsave */ | |
3088 | if (mnemonic[2] == 't') | |
3089 | { | |
3090 | switch (mnemonic[3]) | |
3091 | { | |
3092 | case 'c': /* fstcw */ | |
3093 | case 'd': /* fstdw */ | |
3094 | case 'e': /* fstenv */ | |
3095 | case 's': /* fsts[gw] */ | |
3096 | return 3; | |
3097 | } | |
3098 | } | |
3099 | break; | |
3100 | case 'x': | |
3101 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') | |
3102 | return 0; /* fxsave/fxrstor are not really math ops */ | |
3103 | break; | |
3104 | } | |
252b5132 | 3105 | |
9306ca4a | 3106 | return 1; |
252b5132 RH |
3107 | } |
3108 | ||
c0f3af97 L |
3109 | /* Build the VEX prefix. */ |
3110 | ||
3111 | static void | |
d3ce72d0 | 3112 | build_vex_prefix (const insn_template *t) |
c0f3af97 L |
3113 | { |
3114 | unsigned int register_specifier; | |
3115 | unsigned int implied_prefix; | |
3116 | unsigned int vector_length; | |
3117 | ||
3118 | /* Check register specifier. */ | |
3119 | if (i.vex.register_specifier) | |
43234a1e L |
3120 | { |
3121 | register_specifier = | |
3122 | ~register_number (i.vex.register_specifier) & 0xf; | |
3123 | gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0); | |
3124 | } | |
c0f3af97 L |
3125 | else |
3126 | register_specifier = 0xf; | |
3127 | ||
fa99fab2 L |
3128 | /* Use 2-byte VEX prefix by swappping destination and source |
3129 | operand. */ | |
3130 | if (!i.swap_operand | |
3131 | && i.operands == i.reg_operands | |
7f399153 | 3132 | && i.tm.opcode_modifier.vexopcode == VEX0F |
fa99fab2 L |
3133 | && i.tm.opcode_modifier.s |
3134 | && i.rex == REX_B) | |
3135 | { | |
3136 | unsigned int xchg = i.operands - 1; | |
3137 | union i386_op temp_op; | |
3138 | i386_operand_type temp_type; | |
3139 | ||
3140 | temp_type = i.types[xchg]; | |
3141 | i.types[xchg] = i.types[0]; | |
3142 | i.types[0] = temp_type; | |
3143 | temp_op = i.op[xchg]; | |
3144 | i.op[xchg] = i.op[0]; | |
3145 | i.op[0] = temp_op; | |
3146 | ||
9c2799c2 | 3147 | gas_assert (i.rm.mode == 3); |
fa99fab2 L |
3148 | |
3149 | i.rex = REX_R; | |
3150 | xchg = i.rm.regmem; | |
3151 | i.rm.regmem = i.rm.reg; | |
3152 | i.rm.reg = xchg; | |
3153 | ||
3154 | /* Use the next insn. */ | |
3155 | i.tm = t[1]; | |
3156 | } | |
3157 | ||
539f890d L |
3158 | if (i.tm.opcode_modifier.vex == VEXScalar) |
3159 | vector_length = avxscalar; | |
3160 | else | |
3161 | vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0; | |
c0f3af97 L |
3162 | |
3163 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
3164 | { | |
3165 | case 0: | |
3166 | implied_prefix = 0; | |
3167 | break; | |
3168 | case DATA_PREFIX_OPCODE: | |
3169 | implied_prefix = 1; | |
3170 | break; | |
3171 | case REPE_PREFIX_OPCODE: | |
3172 | implied_prefix = 2; | |
3173 | break; | |
3174 | case REPNE_PREFIX_OPCODE: | |
3175 | implied_prefix = 3; | |
3176 | break; | |
3177 | default: | |
3178 | abort (); | |
3179 | } | |
3180 | ||
3181 | /* Use 2-byte VEX prefix if possible. */ | |
7f399153 | 3182 | if (i.tm.opcode_modifier.vexopcode == VEX0F |
04251de0 | 3183 | && i.tm.opcode_modifier.vexw != VEXW1 |
c0f3af97 L |
3184 | && (i.rex & (REX_W | REX_X | REX_B)) == 0) |
3185 | { | |
3186 | /* 2-byte VEX prefix. */ | |
3187 | unsigned int r; | |
3188 | ||
3189 | i.vex.length = 2; | |
3190 | i.vex.bytes[0] = 0xc5; | |
3191 | ||
3192 | /* Check the REX.R bit. */ | |
3193 | r = (i.rex & REX_R) ? 0 : 1; | |
3194 | i.vex.bytes[1] = (r << 7 | |
3195 | | register_specifier << 3 | |
3196 | | vector_length << 2 | |
3197 | | implied_prefix); | |
3198 | } | |
3199 | else | |
3200 | { | |
3201 | /* 3-byte VEX prefix. */ | |
3202 | unsigned int m, w; | |
3203 | ||
f88c9eb0 | 3204 | i.vex.length = 3; |
f88c9eb0 | 3205 | |
7f399153 | 3206 | switch (i.tm.opcode_modifier.vexopcode) |
5dd85c99 | 3207 | { |
7f399153 L |
3208 | case VEX0F: |
3209 | m = 0x1; | |
80de6e00 | 3210 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3211 | break; |
3212 | case VEX0F38: | |
3213 | m = 0x2; | |
80de6e00 | 3214 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3215 | break; |
3216 | case VEX0F3A: | |
3217 | m = 0x3; | |
80de6e00 | 3218 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3219 | break; |
3220 | case XOP08: | |
5dd85c99 SP |
3221 | m = 0x8; |
3222 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3223 | break; |
3224 | case XOP09: | |
f88c9eb0 SP |
3225 | m = 0x9; |
3226 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3227 | break; |
3228 | case XOP0A: | |
f88c9eb0 SP |
3229 | m = 0xa; |
3230 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3231 | break; |
3232 | default: | |
3233 | abort (); | |
f88c9eb0 | 3234 | } |
c0f3af97 | 3235 | |
c0f3af97 L |
3236 | /* The high 3 bits of the second VEX byte are 1's compliment |
3237 | of RXB bits from REX. */ | |
3238 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
3239 | ||
3240 | /* Check the REX.W bit. */ | |
3241 | w = (i.rex & REX_W) ? 1 : 0; | |
b28d1bda IT |
3242 | if (i.tm.opcode_modifier.vexw == VEXW1) |
3243 | w = 1; | |
c0f3af97 L |
3244 | |
3245 | i.vex.bytes[2] = (w << 7 | |
3246 | | register_specifier << 3 | |
3247 | | vector_length << 2 | |
3248 | | implied_prefix); | |
3249 | } | |
3250 | } | |
3251 | ||
43234a1e L |
3252 | /* Build the EVEX prefix. */ |
3253 | ||
3254 | static void | |
3255 | build_evex_prefix (void) | |
3256 | { | |
3257 | unsigned int register_specifier; | |
3258 | unsigned int implied_prefix; | |
3259 | unsigned int m, w; | |
3260 | rex_byte vrex_used = 0; | |
3261 | ||
3262 | /* Check register specifier. */ | |
3263 | if (i.vex.register_specifier) | |
3264 | { | |
3265 | gas_assert ((i.vrex & REX_X) == 0); | |
3266 | ||
3267 | register_specifier = i.vex.register_specifier->reg_num; | |
3268 | if ((i.vex.register_specifier->reg_flags & RegRex)) | |
3269 | register_specifier += 8; | |
3270 | /* The upper 16 registers are encoded in the fourth byte of the | |
3271 | EVEX prefix. */ | |
3272 | if (!(i.vex.register_specifier->reg_flags & RegVRex)) | |
3273 | i.vex.bytes[3] = 0x8; | |
3274 | register_specifier = ~register_specifier & 0xf; | |
3275 | } | |
3276 | else | |
3277 | { | |
3278 | register_specifier = 0xf; | |
3279 | ||
3280 | /* Encode upper 16 vector index register in the fourth byte of | |
3281 | the EVEX prefix. */ | |
3282 | if (!(i.vrex & REX_X)) | |
3283 | i.vex.bytes[3] = 0x8; | |
3284 | else | |
3285 | vrex_used |= REX_X; | |
3286 | } | |
3287 | ||
3288 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
3289 | { | |
3290 | case 0: | |
3291 | implied_prefix = 0; | |
3292 | break; | |
3293 | case DATA_PREFIX_OPCODE: | |
3294 | implied_prefix = 1; | |
3295 | break; | |
3296 | case REPE_PREFIX_OPCODE: | |
3297 | implied_prefix = 2; | |
3298 | break; | |
3299 | case REPNE_PREFIX_OPCODE: | |
3300 | implied_prefix = 3; | |
3301 | break; | |
3302 | default: | |
3303 | abort (); | |
3304 | } | |
3305 | ||
3306 | /* 4 byte EVEX prefix. */ | |
3307 | i.vex.length = 4; | |
3308 | i.vex.bytes[0] = 0x62; | |
3309 | ||
3310 | /* mmmm bits. */ | |
3311 | switch (i.tm.opcode_modifier.vexopcode) | |
3312 | { | |
3313 | case VEX0F: | |
3314 | m = 1; | |
3315 | break; | |
3316 | case VEX0F38: | |
3317 | m = 2; | |
3318 | break; | |
3319 | case VEX0F3A: | |
3320 | m = 3; | |
3321 | break; | |
3322 | default: | |
3323 | abort (); | |
3324 | break; | |
3325 | } | |
3326 | ||
3327 | /* The high 3 bits of the second EVEX byte are 1's compliment of RXB | |
3328 | bits from REX. */ | |
3329 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
3330 | ||
3331 | /* The fifth bit of the second EVEX byte is 1's compliment of the | |
3332 | REX_R bit in VREX. */ | |
3333 | if (!(i.vrex & REX_R)) | |
3334 | i.vex.bytes[1] |= 0x10; | |
3335 | else | |
3336 | vrex_used |= REX_R; | |
3337 | ||
3338 | if ((i.reg_operands + i.imm_operands) == i.operands) | |
3339 | { | |
3340 | /* When all operands are registers, the REX_X bit in REX is not | |
3341 | used. We reuse it to encode the upper 16 registers, which is | |
3342 | indicated by the REX_B bit in VREX. The REX_X bit is encoded | |
3343 | as 1's compliment. */ | |
3344 | if ((i.vrex & REX_B)) | |
3345 | { | |
3346 | vrex_used |= REX_B; | |
3347 | i.vex.bytes[1] &= ~0x40; | |
3348 | } | |
3349 | } | |
3350 | ||
3351 | /* EVEX instructions shouldn't need the REX prefix. */ | |
3352 | i.vrex &= ~vrex_used; | |
3353 | gas_assert (i.vrex == 0); | |
3354 | ||
3355 | /* Check the REX.W bit. */ | |
3356 | w = (i.rex & REX_W) ? 1 : 0; | |
3357 | if (i.tm.opcode_modifier.vexw) | |
3358 | { | |
3359 | if (i.tm.opcode_modifier.vexw == VEXW1) | |
3360 | w = 1; | |
3361 | } | |
3362 | /* If w is not set it means we are dealing with WIG instruction. */ | |
3363 | else if (!w) | |
3364 | { | |
3365 | if (evexwig == evexw1) | |
3366 | w = 1; | |
3367 | } | |
3368 | ||
3369 | /* Encode the U bit. */ | |
3370 | implied_prefix |= 0x4; | |
3371 | ||
3372 | /* The third byte of the EVEX prefix. */ | |
3373 | i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix); | |
3374 | ||
3375 | /* The fourth byte of the EVEX prefix. */ | |
3376 | /* The zeroing-masking bit. */ | |
3377 | if (i.mask && i.mask->zeroing) | |
3378 | i.vex.bytes[3] |= 0x80; | |
3379 | ||
3380 | /* Don't always set the broadcast bit if there is no RC. */ | |
3381 | if (!i.rounding) | |
3382 | { | |
3383 | /* Encode the vector length. */ | |
3384 | unsigned int vec_length; | |
3385 | ||
3386 | switch (i.tm.opcode_modifier.evex) | |
3387 | { | |
3388 | case EVEXLIG: /* LL' is ignored */ | |
3389 | vec_length = evexlig << 5; | |
3390 | break; | |
3391 | case EVEX128: | |
3392 | vec_length = 0 << 5; | |
3393 | break; | |
3394 | case EVEX256: | |
3395 | vec_length = 1 << 5; | |
3396 | break; | |
3397 | case EVEX512: | |
3398 | vec_length = 2 << 5; | |
3399 | break; | |
3400 | default: | |
3401 | abort (); | |
3402 | break; | |
3403 | } | |
3404 | i.vex.bytes[3] |= vec_length; | |
3405 | /* Encode the broadcast bit. */ | |
3406 | if (i.broadcast) | |
3407 | i.vex.bytes[3] |= 0x10; | |
3408 | } | |
3409 | else | |
3410 | { | |
3411 | if (i.rounding->type != saeonly) | |
3412 | i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5); | |
3413 | else | |
d3d3c6db | 3414 | i.vex.bytes[3] |= 0x10 | (evexrcig << 5); |
43234a1e L |
3415 | } |
3416 | ||
3417 | if (i.mask && i.mask->mask) | |
3418 | i.vex.bytes[3] |= i.mask->mask->reg_num; | |
3419 | } | |
3420 | ||
65da13b5 L |
3421 | static void |
3422 | process_immext (void) | |
3423 | { | |
3424 | expressionS *exp; | |
3425 | ||
4c692bc7 JB |
3426 | if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme) |
3427 | && i.operands > 0) | |
65da13b5 | 3428 | { |
4c692bc7 JB |
3429 | /* MONITOR/MWAIT as well as SVME instructions have fixed operands |
3430 | with an opcode suffix which is coded in the same place as an | |
3431 | 8-bit immediate field would be. | |
3432 | Here we check those operands and remove them afterwards. */ | |
65da13b5 L |
3433 | unsigned int x; |
3434 | ||
3435 | for (x = 0; x < i.operands; x++) | |
4c692bc7 | 3436 | if (register_number (i.op[x].regs) != x) |
65da13b5 | 3437 | as_bad (_("can't use register '%s%s' as operand %d in '%s'."), |
1fed0ba1 L |
3438 | register_prefix, i.op[x].regs->reg_name, x + 1, |
3439 | i.tm.name); | |
3440 | ||
3441 | i.operands = 0; | |
65da13b5 L |
3442 | } |
3443 | ||
9916071f AP |
3444 | if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0) |
3445 | { | |
3446 | /* MONITORX/MWAITX instructions have fixed operands with an opcode | |
3447 | suffix which is coded in the same place as an 8-bit immediate | |
3448 | field would be. | |
3449 | Here we check those operands and remove them afterwards. */ | |
3450 | unsigned int x; | |
3451 | ||
3452 | if (i.operands != 3) | |
3453 | abort(); | |
3454 | ||
3455 | for (x = 0; x < 2; x++) | |
3456 | if (register_number (i.op[x].regs) != x) | |
3457 | goto bad_register_operand; | |
3458 | ||
3459 | /* Check for third operand for mwaitx/monitorx insn. */ | |
3460 | if (register_number (i.op[x].regs) | |
3461 | != (x + (i.tm.extension_opcode == 0xfb))) | |
3462 | { | |
3463 | bad_register_operand: | |
3464 | as_bad (_("can't use register '%s%s' as operand %d in '%s'."), | |
3465 | register_prefix, i.op[x].regs->reg_name, x+1, | |
3466 | i.tm.name); | |
3467 | } | |
3468 | ||
3469 | i.operands = 0; | |
3470 | } | |
3471 | ||
c0f3af97 | 3472 | /* These AMD 3DNow! and SSE2 instructions have an opcode suffix |
65da13b5 L |
3473 | which is coded in the same place as an 8-bit immediate field |
3474 | would be. Here we fake an 8-bit immediate operand from the | |
3475 | opcode suffix stored in tm.extension_opcode. | |
3476 | ||
c1e679ec | 3477 | AVX instructions also use this encoding, for some of |
c0f3af97 | 3478 | 3 argument instructions. */ |
65da13b5 | 3479 | |
43234a1e | 3480 | gas_assert (i.imm_operands <= 1 |
7ab9ffdd | 3481 | && (i.operands <= 2 |
43234a1e L |
3482 | || ((i.tm.opcode_modifier.vex |
3483 | || i.tm.opcode_modifier.evex) | |
7ab9ffdd | 3484 | && i.operands <= 4))); |
65da13b5 L |
3485 | |
3486 | exp = &im_expressions[i.imm_operands++]; | |
3487 | i.op[i.operands].imms = exp; | |
3488 | i.types[i.operands] = imm8; | |
3489 | i.operands++; | |
3490 | exp->X_op = O_constant; | |
3491 | exp->X_add_number = i.tm.extension_opcode; | |
3492 | i.tm.extension_opcode = None; | |
3493 | } | |
3494 | ||
42164a71 L |
3495 | |
3496 | static int | |
3497 | check_hle (void) | |
3498 | { | |
3499 | switch (i.tm.opcode_modifier.hleprefixok) | |
3500 | { | |
3501 | default: | |
3502 | abort (); | |
82c2def5 | 3503 | case HLEPrefixNone: |
165de32a L |
3504 | as_bad (_("invalid instruction `%s' after `%s'"), |
3505 | i.tm.name, i.hle_prefix); | |
42164a71 | 3506 | return 0; |
82c2def5 | 3507 | case HLEPrefixLock: |
42164a71 L |
3508 | if (i.prefix[LOCK_PREFIX]) |
3509 | return 1; | |
165de32a | 3510 | as_bad (_("missing `lock' with `%s'"), i.hle_prefix); |
42164a71 | 3511 | return 0; |
82c2def5 | 3512 | case HLEPrefixAny: |
42164a71 | 3513 | return 1; |
82c2def5 | 3514 | case HLEPrefixRelease: |
42164a71 L |
3515 | if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE) |
3516 | { | |
3517 | as_bad (_("instruction `%s' after `xacquire' not allowed"), | |
3518 | i.tm.name); | |
3519 | return 0; | |
3520 | } | |
3521 | if (i.mem_operands == 0 | |
3522 | || !operand_type_check (i.types[i.operands - 1], anymem)) | |
3523 | { | |
3524 | as_bad (_("memory destination needed for instruction `%s'" | |
3525 | " after `xrelease'"), i.tm.name); | |
3526 | return 0; | |
3527 | } | |
3528 | return 1; | |
3529 | } | |
3530 | } | |
3531 | ||
252b5132 RH |
3532 | /* This is the guts of the machine-dependent assembler. LINE points to a |
3533 | machine dependent instruction. This function is supposed to emit | |
3534 | the frags/bytes it assembles to. */ | |
3535 | ||
3536 | void | |
65da13b5 | 3537 | md_assemble (char *line) |
252b5132 | 3538 | { |
40fb9820 | 3539 | unsigned int j; |
252b5132 | 3540 | char mnemonic[MAX_MNEM_SIZE]; |
d3ce72d0 | 3541 | const insn_template *t; |
252b5132 | 3542 | |
47926f60 | 3543 | /* Initialize globals. */ |
252b5132 RH |
3544 | memset (&i, '\0', sizeof (i)); |
3545 | for (j = 0; j < MAX_OPERANDS; j++) | |
1ae12ab7 | 3546 | i.reloc[j] = NO_RELOC; |
252b5132 RH |
3547 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
3548 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 3549 | save_stack_p = save_stack; |
252b5132 RH |
3550 | |
3551 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
3552 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 3553 | start of a (possibly prefixed) mnemonic. */ |
252b5132 | 3554 | |
29b0f896 AM |
3555 | line = parse_insn (line, mnemonic); |
3556 | if (line == NULL) | |
3557 | return; | |
252b5132 | 3558 | |
29b0f896 | 3559 | line = parse_operands (line, mnemonic); |
ee86248c | 3560 | this_operand = -1; |
8325cc63 JB |
3561 | xfree (i.memop1_string); |
3562 | i.memop1_string = NULL; | |
29b0f896 AM |
3563 | if (line == NULL) |
3564 | return; | |
252b5132 | 3565 | |
29b0f896 AM |
3566 | /* Now we've parsed the mnemonic into a set of templates, and have the |
3567 | operands at hand. */ | |
3568 | ||
3569 | /* All intel opcodes have reversed operands except for "bound" and | |
3570 | "enter". We also don't reverse intersegment "jmp" and "call" | |
3571 | instructions with 2 immediate operands so that the immediate segment | |
050dfa73 | 3572 | precedes the offset, as it does when in AT&T mode. */ |
4d456e3d L |
3573 | if (intel_syntax |
3574 | && i.operands > 1 | |
29b0f896 | 3575 | && (strcmp (mnemonic, "bound") != 0) |
30123838 | 3576 | && (strcmp (mnemonic, "invlpga") != 0) |
40fb9820 L |
3577 | && !(operand_type_check (i.types[0], imm) |
3578 | && operand_type_check (i.types[1], imm))) | |
29b0f896 AM |
3579 | swap_operands (); |
3580 | ||
ec56d5c0 JB |
3581 | /* The order of the immediates should be reversed |
3582 | for 2 immediates extrq and insertq instructions */ | |
3583 | if (i.imm_operands == 2 | |
3584 | && (strcmp (mnemonic, "extrq") == 0 | |
3585 | || strcmp (mnemonic, "insertq") == 0)) | |
3586 | swap_2_operands (0, 1); | |
3587 | ||
29b0f896 AM |
3588 | if (i.imm_operands) |
3589 | optimize_imm (); | |
3590 | ||
b300c311 L |
3591 | /* Don't optimize displacement for movabs since it only takes 64bit |
3592 | displacement. */ | |
3593 | if (i.disp_operands | |
a501d77e | 3594 | && i.disp_encoding != disp_encoding_32bit |
862be3fb L |
3595 | && (flag_code != CODE_64BIT |
3596 | || strcmp (mnemonic, "movabs") != 0)) | |
3597 | optimize_disp (); | |
29b0f896 AM |
3598 | |
3599 | /* Next, we find a template that matches the given insn, | |
3600 | making sure the overlap of the given operands types is consistent | |
3601 | with the template operand types. */ | |
252b5132 | 3602 | |
fa99fab2 | 3603 | if (!(t = match_template ())) |
29b0f896 | 3604 | return; |
252b5132 | 3605 | |
7bab8ab5 | 3606 | if (sse_check != check_none |
81f8a913 | 3607 | && !i.tm.opcode_modifier.noavx |
daf50ae7 L |
3608 | && (i.tm.cpu_flags.bitfield.cpusse |
3609 | || i.tm.cpu_flags.bitfield.cpusse2 | |
3610 | || i.tm.cpu_flags.bitfield.cpusse3 | |
3611 | || i.tm.cpu_flags.bitfield.cpussse3 | |
3612 | || i.tm.cpu_flags.bitfield.cpusse4_1 | |
3613 | || i.tm.cpu_flags.bitfield.cpusse4_2)) | |
3614 | { | |
7bab8ab5 | 3615 | (sse_check == check_warning |
daf50ae7 L |
3616 | ? as_warn |
3617 | : as_bad) (_("SSE instruction `%s' is used"), i.tm.name); | |
3618 | } | |
3619 | ||
321fd21e L |
3620 | /* Zap movzx and movsx suffix. The suffix has been set from |
3621 | "word ptr" or "byte ptr" on the source operand in Intel syntax | |
3622 | or extracted from mnemonic in AT&T syntax. But we'll use | |
3623 | the destination register to choose the suffix for encoding. */ | |
3624 | if ((i.tm.base_opcode & ~9) == 0x0fb6) | |
cd61ebfe | 3625 | { |
321fd21e L |
3626 | /* In Intel syntax, there must be a suffix. In AT&T syntax, if |
3627 | there is no suffix, the default will be byte extension. */ | |
3628 | if (i.reg_operands != 2 | |
3629 | && !i.suffix | |
7ab9ffdd | 3630 | && intel_syntax) |
321fd21e L |
3631 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); |
3632 | ||
3633 | i.suffix = 0; | |
cd61ebfe | 3634 | } |
24eab124 | 3635 | |
40fb9820 | 3636 | if (i.tm.opcode_modifier.fwait) |
29b0f896 AM |
3637 | if (!add_prefix (FWAIT_OPCODE)) |
3638 | return; | |
252b5132 | 3639 | |
d5de92cf L |
3640 | /* Check if REP prefix is OK. */ |
3641 | if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok) | |
3642 | { | |
3643 | as_bad (_("invalid instruction `%s' after `%s'"), | |
3644 | i.tm.name, i.rep_prefix); | |
3645 | return; | |
3646 | } | |
3647 | ||
c1ba0266 L |
3648 | /* Check for lock without a lockable instruction. Destination operand |
3649 | must be memory unless it is xchg (0x86). */ | |
c32fa91d L |
3650 | if (i.prefix[LOCK_PREFIX] |
3651 | && (!i.tm.opcode_modifier.islockable | |
c1ba0266 L |
3652 | || i.mem_operands == 0 |
3653 | || (i.tm.base_opcode != 0x86 | |
3654 | && !operand_type_check (i.types[i.operands - 1], anymem)))) | |
c32fa91d L |
3655 | { |
3656 | as_bad (_("expecting lockable instruction after `lock'")); | |
3657 | return; | |
3658 | } | |
3659 | ||
42164a71 | 3660 | /* Check if HLE prefix is OK. */ |
165de32a | 3661 | if (i.hle_prefix && !check_hle ()) |
42164a71 L |
3662 | return; |
3663 | ||
7e8b059b L |
3664 | /* Check BND prefix. */ |
3665 | if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok) | |
3666 | as_bad (_("expecting valid branch instruction after `bnd'")); | |
3667 | ||
3668 | if (i.tm.cpu_flags.bitfield.cpumpx | |
3669 | && flag_code == CODE_64BIT | |
3670 | && i.prefix[ADDR_PREFIX]) | |
3671 | as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions.")); | |
3672 | ||
3673 | /* Insert BND prefix. */ | |
3674 | if (add_bnd_prefix | |
3675 | && i.tm.opcode_modifier.bndprefixok | |
3676 | && !i.prefix[BND_PREFIX]) | |
3677 | add_prefix (BND_PREFIX_OPCODE); | |
3678 | ||
29b0f896 | 3679 | /* Check string instruction segment overrides. */ |
40fb9820 | 3680 | if (i.tm.opcode_modifier.isstring && i.mem_operands != 0) |
29b0f896 AM |
3681 | { |
3682 | if (!check_string ()) | |
5dd0794d | 3683 | return; |
fc0763e6 | 3684 | i.disp_operands = 0; |
29b0f896 | 3685 | } |
5dd0794d | 3686 | |
29b0f896 AM |
3687 | if (!process_suffix ()) |
3688 | return; | |
e413e4e9 | 3689 | |
bc0844ae L |
3690 | /* Update operand types. */ |
3691 | for (j = 0; j < i.operands; j++) | |
3692 | i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]); | |
3693 | ||
29b0f896 AM |
3694 | /* Make still unresolved immediate matches conform to size of immediate |
3695 | given in i.suffix. */ | |
3696 | if (!finalize_imm ()) | |
3697 | return; | |
252b5132 | 3698 | |
40fb9820 | 3699 | if (i.types[0].bitfield.imm1) |
29b0f896 | 3700 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 | 3701 | |
9afe6eb8 L |
3702 | /* We only need to check those implicit registers for instructions |
3703 | with 3 operands or less. */ | |
3704 | if (i.operands <= 3) | |
3705 | for (j = 0; j < i.operands; j++) | |
3706 | if (i.types[j].bitfield.inoutportreg | |
3707 | || i.types[j].bitfield.shiftcount | |
3708 | || i.types[j].bitfield.acc | |
3709 | || i.types[j].bitfield.floatacc) | |
3710 | i.reg_operands--; | |
40fb9820 | 3711 | |
c0f3af97 L |
3712 | /* ImmExt should be processed after SSE2AVX. */ |
3713 | if (!i.tm.opcode_modifier.sse2avx | |
3714 | && i.tm.opcode_modifier.immext) | |
65da13b5 | 3715 | process_immext (); |
252b5132 | 3716 | |
29b0f896 AM |
3717 | /* For insns with operands there are more diddles to do to the opcode. */ |
3718 | if (i.operands) | |
3719 | { | |
3720 | if (!process_operands ()) | |
3721 | return; | |
3722 | } | |
40fb9820 | 3723 | else if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 AM |
3724 | { |
3725 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ | |
3726 | as_warn (_("translating to `%sp'"), i.tm.name); | |
3727 | } | |
252b5132 | 3728 | |
9e5e5283 L |
3729 | if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex) |
3730 | { | |
3731 | if (flag_code == CODE_16BIT) | |
3732 | { | |
3733 | as_bad (_("instruction `%s' isn't supported in 16-bit mode."), | |
3734 | i.tm.name); | |
3735 | return; | |
3736 | } | |
c0f3af97 | 3737 | |
9e5e5283 L |
3738 | if (i.tm.opcode_modifier.vex) |
3739 | build_vex_prefix (t); | |
3740 | else | |
3741 | build_evex_prefix (); | |
3742 | } | |
43234a1e | 3743 | |
5dd85c99 SP |
3744 | /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4 |
3745 | instructions may define INT_OPCODE as well, so avoid this corner | |
3746 | case for those instructions that use MODRM. */ | |
3747 | if (i.tm.base_opcode == INT_OPCODE | |
a6461c02 SP |
3748 | && !i.tm.opcode_modifier.modrm |
3749 | && i.op[0].imms->X_add_number == 3) | |
29b0f896 AM |
3750 | { |
3751 | i.tm.base_opcode = INT3_OPCODE; | |
3752 | i.imm_operands = 0; | |
3753 | } | |
252b5132 | 3754 | |
40fb9820 L |
3755 | if ((i.tm.opcode_modifier.jump |
3756 | || i.tm.opcode_modifier.jumpbyte | |
3757 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 AM |
3758 | && i.op[0].disps->X_op == O_constant) |
3759 | { | |
3760 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
3761 | the absolute address given by the constant. Since ix86 jumps and | |
3762 | calls are pc relative, we need to generate a reloc. */ | |
3763 | i.op[0].disps->X_add_symbol = &abs_symbol; | |
3764 | i.op[0].disps->X_op = O_symbol; | |
3765 | } | |
252b5132 | 3766 | |
40fb9820 | 3767 | if (i.tm.opcode_modifier.rex64) |
161a04f6 | 3768 | i.rex |= REX_W; |
252b5132 | 3769 | |
29b0f896 AM |
3770 | /* For 8 bit registers we need an empty rex prefix. Also if the |
3771 | instruction already has a prefix, we need to convert old | |
3772 | registers to new ones. */ | |
773f551c | 3773 | |
40fb9820 | 3774 | if ((i.types[0].bitfield.reg8 |
29b0f896 | 3775 | && (i.op[0].regs->reg_flags & RegRex64) != 0) |
40fb9820 | 3776 | || (i.types[1].bitfield.reg8 |
29b0f896 | 3777 | && (i.op[1].regs->reg_flags & RegRex64) != 0) |
40fb9820 L |
3778 | || ((i.types[0].bitfield.reg8 |
3779 | || i.types[1].bitfield.reg8) | |
29b0f896 AM |
3780 | && i.rex != 0)) |
3781 | { | |
3782 | int x; | |
726c5dcd | 3783 | |
29b0f896 AM |
3784 | i.rex |= REX_OPCODE; |
3785 | for (x = 0; x < 2; x++) | |
3786 | { | |
3787 | /* Look for 8 bit operand that uses old registers. */ | |
40fb9820 | 3788 | if (i.types[x].bitfield.reg8 |
29b0f896 | 3789 | && (i.op[x].regs->reg_flags & RegRex64) == 0) |
773f551c | 3790 | { |
29b0f896 AM |
3791 | /* In case it is "hi" register, give up. */ |
3792 | if (i.op[x].regs->reg_num > 3) | |
a540244d | 3793 | as_bad (_("can't encode register '%s%s' in an " |
4eed87de | 3794 | "instruction requiring REX prefix."), |
a540244d | 3795 | register_prefix, i.op[x].regs->reg_name); |
773f551c | 3796 | |
29b0f896 AM |
3797 | /* Otherwise it is equivalent to the extended register. |
3798 | Since the encoding doesn't change this is merely | |
3799 | cosmetic cleanup for debug output. */ | |
3800 | ||
3801 | i.op[x].regs = i.op[x].regs + 8; | |
773f551c | 3802 | } |
29b0f896 AM |
3803 | } |
3804 | } | |
773f551c | 3805 | |
7ab9ffdd | 3806 | if (i.rex != 0) |
29b0f896 AM |
3807 | add_prefix (REX_OPCODE | i.rex); |
3808 | ||
3809 | /* We are ready to output the insn. */ | |
3810 | output_insn (); | |
3811 | } | |
3812 | ||
3813 | static char * | |
e3bb37b5 | 3814 | parse_insn (char *line, char *mnemonic) |
29b0f896 AM |
3815 | { |
3816 | char *l = line; | |
3817 | char *token_start = l; | |
3818 | char *mnem_p; | |
5c6af06e | 3819 | int supported; |
d3ce72d0 | 3820 | const insn_template *t; |
b6169b20 | 3821 | char *dot_p = NULL; |
29b0f896 | 3822 | |
29b0f896 AM |
3823 | while (1) |
3824 | { | |
3825 | mnem_p = mnemonic; | |
3826 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
3827 | { | |
b6169b20 L |
3828 | if (*mnem_p == '.') |
3829 | dot_p = mnem_p; | |
29b0f896 AM |
3830 | mnem_p++; |
3831 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
45288df1 | 3832 | { |
29b0f896 AM |
3833 | as_bad (_("no such instruction: `%s'"), token_start); |
3834 | return NULL; | |
3835 | } | |
3836 | l++; | |
3837 | } | |
3838 | if (!is_space_char (*l) | |
3839 | && *l != END_OF_INSN | |
e44823cf JB |
3840 | && (intel_syntax |
3841 | || (*l != PREFIX_SEPARATOR | |
3842 | && *l != ','))) | |
29b0f896 AM |
3843 | { |
3844 | as_bad (_("invalid character %s in mnemonic"), | |
3845 | output_invalid (*l)); | |
3846 | return NULL; | |
3847 | } | |
3848 | if (token_start == l) | |
3849 | { | |
e44823cf | 3850 | if (!intel_syntax && *l == PREFIX_SEPARATOR) |
29b0f896 AM |
3851 | as_bad (_("expecting prefix; got nothing")); |
3852 | else | |
3853 | as_bad (_("expecting mnemonic; got nothing")); | |
3854 | return NULL; | |
3855 | } | |
45288df1 | 3856 | |
29b0f896 | 3857 | /* Look up instruction (or prefix) via hash table. */ |
d3ce72d0 | 3858 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
47926f60 | 3859 | |
29b0f896 AM |
3860 | if (*l != END_OF_INSN |
3861 | && (!is_space_char (*l) || l[1] != END_OF_INSN) | |
3862 | && current_templates | |
40fb9820 | 3863 | && current_templates->start->opcode_modifier.isprefix) |
29b0f896 | 3864 | { |
c6fb90c8 | 3865 | if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags)) |
2dd88dca JB |
3866 | { |
3867 | as_bad ((flag_code != CODE_64BIT | |
3868 | ? _("`%s' is only supported in 64-bit mode") | |
3869 | : _("`%s' is not supported in 64-bit mode")), | |
3870 | current_templates->start->name); | |
3871 | return NULL; | |
3872 | } | |
29b0f896 AM |
3873 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
3874 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
40fb9820 L |
3875 | if ((current_templates->start->opcode_modifier.size16 |
3876 | || current_templates->start->opcode_modifier.size32) | |
29b0f896 | 3877 | && flag_code != CODE_64BIT |
40fb9820 | 3878 | && (current_templates->start->opcode_modifier.size32 |
29b0f896 AM |
3879 | ^ (flag_code == CODE_16BIT))) |
3880 | { | |
3881 | as_bad (_("redundant %s prefix"), | |
3882 | current_templates->start->name); | |
3883 | return NULL; | |
45288df1 | 3884 | } |
29b0f896 AM |
3885 | /* Add prefix, checking for repeated prefixes. */ |
3886 | switch (add_prefix (current_templates->start->base_opcode)) | |
3887 | { | |
c32fa91d | 3888 | case PREFIX_EXIST: |
29b0f896 | 3889 | return NULL; |
c32fa91d | 3890 | case PREFIX_REP: |
42164a71 | 3891 | if (current_templates->start->cpu_flags.bitfield.cpuhle) |
165de32a | 3892 | i.hle_prefix = current_templates->start->name; |
7e8b059b L |
3893 | else if (current_templates->start->cpu_flags.bitfield.cpumpx) |
3894 | i.bnd_prefix = current_templates->start->name; | |
42164a71 | 3895 | else |
d5de92cf | 3896 | i.rep_prefix = current_templates->start->name; |
29b0f896 | 3897 | break; |
c32fa91d L |
3898 | default: |
3899 | break; | |
29b0f896 AM |
3900 | } |
3901 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
3902 | token_start = ++l; | |
3903 | } | |
3904 | else | |
3905 | break; | |
3906 | } | |
45288df1 | 3907 | |
30a55f88 | 3908 | if (!current_templates) |
b6169b20 | 3909 | { |
f8a5c266 L |
3910 | /* Check if we should swap operand or force 32bit displacement in |
3911 | encoding. */ | |
30a55f88 L |
3912 | if (mnem_p - 2 == dot_p && dot_p[1] == 's') |
3913 | i.swap_operand = 1; | |
8d63c93e | 3914 | else if (mnem_p - 3 == dot_p |
a501d77e L |
3915 | && dot_p[1] == 'd' |
3916 | && dot_p[2] == '8') | |
3917 | i.disp_encoding = disp_encoding_8bit; | |
8d63c93e | 3918 | else if (mnem_p - 4 == dot_p |
f8a5c266 L |
3919 | && dot_p[1] == 'd' |
3920 | && dot_p[2] == '3' | |
3921 | && dot_p[3] == '2') | |
a501d77e | 3922 | i.disp_encoding = disp_encoding_32bit; |
30a55f88 L |
3923 | else |
3924 | goto check_suffix; | |
3925 | mnem_p = dot_p; | |
3926 | *dot_p = '\0'; | |
d3ce72d0 | 3927 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
b6169b20 L |
3928 | } |
3929 | ||
29b0f896 AM |
3930 | if (!current_templates) |
3931 | { | |
b6169b20 | 3932 | check_suffix: |
29b0f896 AM |
3933 | /* See if we can get a match by trimming off a suffix. */ |
3934 | switch (mnem_p[-1]) | |
3935 | { | |
3936 | case WORD_MNEM_SUFFIX: | |
9306ca4a JB |
3937 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) |
3938 | i.suffix = SHORT_MNEM_SUFFIX; | |
3939 | else | |
29b0f896 AM |
3940 | case BYTE_MNEM_SUFFIX: |
3941 | case QWORD_MNEM_SUFFIX: | |
3942 | i.suffix = mnem_p[-1]; | |
3943 | mnem_p[-1] = '\0'; | |
d3ce72d0 NC |
3944 | current_templates = (const templates *) hash_find (op_hash, |
3945 | mnemonic); | |
29b0f896 AM |
3946 | break; |
3947 | case SHORT_MNEM_SUFFIX: | |
3948 | case LONG_MNEM_SUFFIX: | |
3949 | if (!intel_syntax) | |
3950 | { | |
3951 | i.suffix = mnem_p[-1]; | |
3952 | mnem_p[-1] = '\0'; | |
d3ce72d0 NC |
3953 | current_templates = (const templates *) hash_find (op_hash, |
3954 | mnemonic); | |
29b0f896 AM |
3955 | } |
3956 | break; | |
252b5132 | 3957 | |
29b0f896 AM |
3958 | /* Intel Syntax. */ |
3959 | case 'd': | |
3960 | if (intel_syntax) | |
3961 | { | |
9306ca4a | 3962 | if (intel_float_operand (mnemonic) == 1) |
29b0f896 AM |
3963 | i.suffix = SHORT_MNEM_SUFFIX; |
3964 | else | |
3965 | i.suffix = LONG_MNEM_SUFFIX; | |
3966 | mnem_p[-1] = '\0'; | |
d3ce72d0 NC |
3967 | current_templates = (const templates *) hash_find (op_hash, |
3968 | mnemonic); | |
29b0f896 AM |
3969 | } |
3970 | break; | |
3971 | } | |
3972 | if (!current_templates) | |
3973 | { | |
3974 | as_bad (_("no such instruction: `%s'"), token_start); | |
3975 | return NULL; | |
3976 | } | |
3977 | } | |
252b5132 | 3978 | |
40fb9820 L |
3979 | if (current_templates->start->opcode_modifier.jump |
3980 | || current_templates->start->opcode_modifier.jumpbyte) | |
29b0f896 AM |
3981 | { |
3982 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
3983 | predict taken and predict not taken respectively. | |
3984 | I'm not sure that branch hints actually do anything on loop | |
3985 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
3986 | may work in the future and it doesn't hurt to accept them | |
3987 | now. */ | |
3988 | if (l[0] == ',' && l[1] == 'p') | |
3989 | { | |
3990 | if (l[2] == 't') | |
3991 | { | |
3992 | if (!add_prefix (DS_PREFIX_OPCODE)) | |
3993 | return NULL; | |
3994 | l += 3; | |
3995 | } | |
3996 | else if (l[2] == 'n') | |
3997 | { | |
3998 | if (!add_prefix (CS_PREFIX_OPCODE)) | |
3999 | return NULL; | |
4000 | l += 3; | |
4001 | } | |
4002 | } | |
4003 | } | |
4004 | /* Any other comma loses. */ | |
4005 | if (*l == ',') | |
4006 | { | |
4007 | as_bad (_("invalid character %s in mnemonic"), | |
4008 | output_invalid (*l)); | |
4009 | return NULL; | |
4010 | } | |
252b5132 | 4011 | |
29b0f896 | 4012 | /* Check if instruction is supported on specified architecture. */ |
5c6af06e JB |
4013 | supported = 0; |
4014 | for (t = current_templates->start; t < current_templates->end; ++t) | |
4015 | { | |
c0f3af97 L |
4016 | supported |= cpu_flags_match (t); |
4017 | if (supported == CPU_FLAGS_PERFECT_MATCH) | |
3629bb00 | 4018 | goto skip; |
5c6af06e | 4019 | } |
3629bb00 | 4020 | |
c0f3af97 | 4021 | if (!(supported & CPU_FLAGS_64BIT_MATCH)) |
5c6af06e JB |
4022 | { |
4023 | as_bad (flag_code == CODE_64BIT | |
4024 | ? _("`%s' is not supported in 64-bit mode") | |
4025 | : _("`%s' is only supported in 64-bit mode"), | |
4026 | current_templates->start->name); | |
4027 | return NULL; | |
4028 | } | |
c0f3af97 | 4029 | if (supported != CPU_FLAGS_PERFECT_MATCH) |
29b0f896 | 4030 | { |
3629bb00 | 4031 | as_bad (_("`%s' is not supported on `%s%s'"), |
7ab9ffdd | 4032 | current_templates->start->name, |
41aacd83 | 4033 | cpu_arch_name ? cpu_arch_name : default_arch, |
3629bb00 L |
4034 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); |
4035 | return NULL; | |
29b0f896 | 4036 | } |
3629bb00 L |
4037 | |
4038 | skip: | |
4039 | if (!cpu_arch_flags.bitfield.cpui386 | |
40fb9820 | 4040 | && (flag_code != CODE_16BIT)) |
29b0f896 AM |
4041 | { |
4042 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
4043 | } | |
252b5132 | 4044 | |
29b0f896 AM |
4045 | return l; |
4046 | } | |
252b5132 | 4047 | |
29b0f896 | 4048 | static char * |
e3bb37b5 | 4049 | parse_operands (char *l, const char *mnemonic) |
29b0f896 AM |
4050 | { |
4051 | char *token_start; | |
3138f287 | 4052 | |
29b0f896 AM |
4053 | /* 1 if operand is pending after ','. */ |
4054 | unsigned int expecting_operand = 0; | |
252b5132 | 4055 | |
29b0f896 AM |
4056 | /* Non-zero if operand parens not balanced. */ |
4057 | unsigned int paren_not_balanced; | |
4058 | ||
4059 | while (*l != END_OF_INSN) | |
4060 | { | |
4061 | /* Skip optional white space before operand. */ | |
4062 | if (is_space_char (*l)) | |
4063 | ++l; | |
d02603dc | 4064 | if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"') |
29b0f896 AM |
4065 | { |
4066 | as_bad (_("invalid character %s before operand %d"), | |
4067 | output_invalid (*l), | |
4068 | i.operands + 1); | |
4069 | return NULL; | |
4070 | } | |
d02603dc | 4071 | token_start = l; /* After white space. */ |
29b0f896 AM |
4072 | paren_not_balanced = 0; |
4073 | while (paren_not_balanced || *l != ',') | |
4074 | { | |
4075 | if (*l == END_OF_INSN) | |
4076 | { | |
4077 | if (paren_not_balanced) | |
4078 | { | |
4079 | if (!intel_syntax) | |
4080 | as_bad (_("unbalanced parenthesis in operand %d."), | |
4081 | i.operands + 1); | |
4082 | else | |
4083 | as_bad (_("unbalanced brackets in operand %d."), | |
4084 | i.operands + 1); | |
4085 | return NULL; | |
4086 | } | |
4087 | else | |
4088 | break; /* we are done */ | |
4089 | } | |
d02603dc | 4090 | else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"') |
29b0f896 AM |
4091 | { |
4092 | as_bad (_("invalid character %s in operand %d"), | |
4093 | output_invalid (*l), | |
4094 | i.operands + 1); | |
4095 | return NULL; | |
4096 | } | |
4097 | if (!intel_syntax) | |
4098 | { | |
4099 | if (*l == '(') | |
4100 | ++paren_not_balanced; | |
4101 | if (*l == ')') | |
4102 | --paren_not_balanced; | |
4103 | } | |
4104 | else | |
4105 | { | |
4106 | if (*l == '[') | |
4107 | ++paren_not_balanced; | |
4108 | if (*l == ']') | |
4109 | --paren_not_balanced; | |
4110 | } | |
4111 | l++; | |
4112 | } | |
4113 | if (l != token_start) | |
4114 | { /* Yes, we've read in another operand. */ | |
4115 | unsigned int operand_ok; | |
4116 | this_operand = i.operands++; | |
7d5e4556 | 4117 | i.types[this_operand].bitfield.unspecified = 1; |
29b0f896 AM |
4118 | if (i.operands > MAX_OPERANDS) |
4119 | { | |
4120 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
4121 | MAX_OPERANDS); | |
4122 | return NULL; | |
4123 | } | |
4124 | /* Now parse operand adding info to 'i' as we go along. */ | |
4125 | END_STRING_AND_SAVE (l); | |
4126 | ||
4127 | if (intel_syntax) | |
4128 | operand_ok = | |
4129 | i386_intel_operand (token_start, | |
4130 | intel_float_operand (mnemonic)); | |
4131 | else | |
a7619375 | 4132 | operand_ok = i386_att_operand (token_start); |
29b0f896 AM |
4133 | |
4134 | RESTORE_END_STRING (l); | |
4135 | if (!operand_ok) | |
4136 | return NULL; | |
4137 | } | |
4138 | else | |
4139 | { | |
4140 | if (expecting_operand) | |
4141 | { | |
4142 | expecting_operand_after_comma: | |
4143 | as_bad (_("expecting operand after ','; got nothing")); | |
4144 | return NULL; | |
4145 | } | |
4146 | if (*l == ',') | |
4147 | { | |
4148 | as_bad (_("expecting operand before ','; got nothing")); | |
4149 | return NULL; | |
4150 | } | |
4151 | } | |
7f3f1ea2 | 4152 | |
29b0f896 AM |
4153 | /* Now *l must be either ',' or END_OF_INSN. */ |
4154 | if (*l == ',') | |
4155 | { | |
4156 | if (*++l == END_OF_INSN) | |
4157 | { | |
4158 | /* Just skip it, if it's \n complain. */ | |
4159 | goto expecting_operand_after_comma; | |
4160 | } | |
4161 | expecting_operand = 1; | |
4162 | } | |
4163 | } | |
4164 | return l; | |
4165 | } | |
7f3f1ea2 | 4166 | |
050dfa73 | 4167 | static void |
4d456e3d | 4168 | swap_2_operands (int xchg1, int xchg2) |
050dfa73 MM |
4169 | { |
4170 | union i386_op temp_op; | |
40fb9820 | 4171 | i386_operand_type temp_type; |
050dfa73 | 4172 | enum bfd_reloc_code_real temp_reloc; |
4eed87de | 4173 | |
050dfa73 MM |
4174 | temp_type = i.types[xchg2]; |
4175 | i.types[xchg2] = i.types[xchg1]; | |
4176 | i.types[xchg1] = temp_type; | |
4177 | temp_op = i.op[xchg2]; | |
4178 | i.op[xchg2] = i.op[xchg1]; | |
4179 | i.op[xchg1] = temp_op; | |
4180 | temp_reloc = i.reloc[xchg2]; | |
4181 | i.reloc[xchg2] = i.reloc[xchg1]; | |
4182 | i.reloc[xchg1] = temp_reloc; | |
43234a1e L |
4183 | |
4184 | if (i.mask) | |
4185 | { | |
4186 | if (i.mask->operand == xchg1) | |
4187 | i.mask->operand = xchg2; | |
4188 | else if (i.mask->operand == xchg2) | |
4189 | i.mask->operand = xchg1; | |
4190 | } | |
4191 | if (i.broadcast) | |
4192 | { | |
4193 | if (i.broadcast->operand == xchg1) | |
4194 | i.broadcast->operand = xchg2; | |
4195 | else if (i.broadcast->operand == xchg2) | |
4196 | i.broadcast->operand = xchg1; | |
4197 | } | |
4198 | if (i.rounding) | |
4199 | { | |
4200 | if (i.rounding->operand == xchg1) | |
4201 | i.rounding->operand = xchg2; | |
4202 | else if (i.rounding->operand == xchg2) | |
4203 | i.rounding->operand = xchg1; | |
4204 | } | |
050dfa73 MM |
4205 | } |
4206 | ||
29b0f896 | 4207 | static void |
e3bb37b5 | 4208 | swap_operands (void) |
29b0f896 | 4209 | { |
b7c61d9a | 4210 | switch (i.operands) |
050dfa73 | 4211 | { |
c0f3af97 | 4212 | case 5: |
b7c61d9a | 4213 | case 4: |
4d456e3d | 4214 | swap_2_operands (1, i.operands - 2); |
b7c61d9a L |
4215 | case 3: |
4216 | case 2: | |
4d456e3d | 4217 | swap_2_operands (0, i.operands - 1); |
b7c61d9a L |
4218 | break; |
4219 | default: | |
4220 | abort (); | |
29b0f896 | 4221 | } |
29b0f896 AM |
4222 | |
4223 | if (i.mem_operands == 2) | |
4224 | { | |
4225 | const seg_entry *temp_seg; | |
4226 | temp_seg = i.seg[0]; | |
4227 | i.seg[0] = i.seg[1]; | |
4228 | i.seg[1] = temp_seg; | |
4229 | } | |
4230 | } | |
252b5132 | 4231 | |
29b0f896 AM |
4232 | /* Try to ensure constant immediates are represented in the smallest |
4233 | opcode possible. */ | |
4234 | static void | |
e3bb37b5 | 4235 | optimize_imm (void) |
29b0f896 AM |
4236 | { |
4237 | char guess_suffix = 0; | |
4238 | int op; | |
252b5132 | 4239 | |
29b0f896 AM |
4240 | if (i.suffix) |
4241 | guess_suffix = i.suffix; | |
4242 | else if (i.reg_operands) | |
4243 | { | |
4244 | /* Figure out a suffix from the last register operand specified. | |
4245 | We can't do this properly yet, ie. excluding InOutPortReg, | |
4246 | but the following works for instructions with immediates. | |
4247 | In any case, we can't set i.suffix yet. */ | |
4248 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 4249 | if (i.types[op].bitfield.reg8) |
7ab9ffdd | 4250 | { |
40fb9820 L |
4251 | guess_suffix = BYTE_MNEM_SUFFIX; |
4252 | break; | |
4253 | } | |
4254 | else if (i.types[op].bitfield.reg16) | |
252b5132 | 4255 | { |
40fb9820 L |
4256 | guess_suffix = WORD_MNEM_SUFFIX; |
4257 | break; | |
4258 | } | |
4259 | else if (i.types[op].bitfield.reg32) | |
4260 | { | |
4261 | guess_suffix = LONG_MNEM_SUFFIX; | |
4262 | break; | |
4263 | } | |
4264 | else if (i.types[op].bitfield.reg64) | |
4265 | { | |
4266 | guess_suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 | 4267 | break; |
252b5132 | 4268 | } |
29b0f896 AM |
4269 | } |
4270 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) | |
4271 | guess_suffix = WORD_MNEM_SUFFIX; | |
4272 | ||
4273 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 4274 | if (operand_type_check (i.types[op], imm)) |
29b0f896 AM |
4275 | { |
4276 | switch (i.op[op].imms->X_op) | |
252b5132 | 4277 | { |
29b0f896 AM |
4278 | case O_constant: |
4279 | /* If a suffix is given, this operand may be shortened. */ | |
4280 | switch (guess_suffix) | |
252b5132 | 4281 | { |
29b0f896 | 4282 | case LONG_MNEM_SUFFIX: |
40fb9820 L |
4283 | i.types[op].bitfield.imm32 = 1; |
4284 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
4285 | break; |
4286 | case WORD_MNEM_SUFFIX: | |
40fb9820 L |
4287 | i.types[op].bitfield.imm16 = 1; |
4288 | i.types[op].bitfield.imm32 = 1; | |
4289 | i.types[op].bitfield.imm32s = 1; | |
4290 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
4291 | break; |
4292 | case BYTE_MNEM_SUFFIX: | |
40fb9820 L |
4293 | i.types[op].bitfield.imm8 = 1; |
4294 | i.types[op].bitfield.imm8s = 1; | |
4295 | i.types[op].bitfield.imm16 = 1; | |
4296 | i.types[op].bitfield.imm32 = 1; | |
4297 | i.types[op].bitfield.imm32s = 1; | |
4298 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 | 4299 | break; |
252b5132 | 4300 | } |
252b5132 | 4301 | |
29b0f896 AM |
4302 | /* If this operand is at most 16 bits, convert it |
4303 | to a signed 16 bit number before trying to see | |
4304 | whether it will fit in an even smaller size. | |
4305 | This allows a 16-bit operand such as $0xffe0 to | |
4306 | be recognised as within Imm8S range. */ | |
40fb9820 | 4307 | if ((i.types[op].bitfield.imm16) |
29b0f896 | 4308 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) |
252b5132 | 4309 | { |
29b0f896 AM |
4310 | i.op[op].imms->X_add_number = |
4311 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
4312 | } | |
a28def75 L |
4313 | #ifdef BFD64 |
4314 | /* Store 32-bit immediate in 64-bit for 64-bit BFD. */ | |
40fb9820 | 4315 | if ((i.types[op].bitfield.imm32) |
29b0f896 AM |
4316 | && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) |
4317 | == 0)) | |
4318 | { | |
4319 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number | |
4320 | ^ ((offsetT) 1 << 31)) | |
4321 | - ((offsetT) 1 << 31)); | |
4322 | } | |
a28def75 | 4323 | #endif |
40fb9820 | 4324 | i.types[op] |
c6fb90c8 L |
4325 | = operand_type_or (i.types[op], |
4326 | smallest_imm_type (i.op[op].imms->X_add_number)); | |
252b5132 | 4327 | |
29b0f896 AM |
4328 | /* We must avoid matching of Imm32 templates when 64bit |
4329 | only immediate is available. */ | |
4330 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
40fb9820 | 4331 | i.types[op].bitfield.imm32 = 0; |
29b0f896 | 4332 | break; |
252b5132 | 4333 | |
29b0f896 AM |
4334 | case O_absent: |
4335 | case O_register: | |
4336 | abort (); | |
4337 | ||
4338 | /* Symbols and expressions. */ | |
4339 | default: | |
9cd96992 JB |
4340 | /* Convert symbolic operand to proper sizes for matching, but don't |
4341 | prevent matching a set of insns that only supports sizes other | |
4342 | than those matching the insn suffix. */ | |
4343 | { | |
40fb9820 | 4344 | i386_operand_type mask, allowed; |
d3ce72d0 | 4345 | const insn_template *t; |
9cd96992 | 4346 | |
0dfbf9d7 L |
4347 | operand_type_set (&mask, 0); |
4348 | operand_type_set (&allowed, 0); | |
40fb9820 | 4349 | |
4eed87de AM |
4350 | for (t = current_templates->start; |
4351 | t < current_templates->end; | |
4352 | ++t) | |
c6fb90c8 L |
4353 | allowed = operand_type_or (allowed, |
4354 | t->operand_types[op]); | |
9cd96992 JB |
4355 | switch (guess_suffix) |
4356 | { | |
4357 | case QWORD_MNEM_SUFFIX: | |
40fb9820 L |
4358 | mask.bitfield.imm64 = 1; |
4359 | mask.bitfield.imm32s = 1; | |
9cd96992 JB |
4360 | break; |
4361 | case LONG_MNEM_SUFFIX: | |
40fb9820 | 4362 | mask.bitfield.imm32 = 1; |
9cd96992 JB |
4363 | break; |
4364 | case WORD_MNEM_SUFFIX: | |
40fb9820 | 4365 | mask.bitfield.imm16 = 1; |
9cd96992 JB |
4366 | break; |
4367 | case BYTE_MNEM_SUFFIX: | |
40fb9820 | 4368 | mask.bitfield.imm8 = 1; |
9cd96992 JB |
4369 | break; |
4370 | default: | |
9cd96992 JB |
4371 | break; |
4372 | } | |
c6fb90c8 | 4373 | allowed = operand_type_and (mask, allowed); |
0dfbf9d7 | 4374 | if (!operand_type_all_zero (&allowed)) |
c6fb90c8 | 4375 | i.types[op] = operand_type_and (i.types[op], mask); |
9cd96992 | 4376 | } |
29b0f896 | 4377 | break; |
252b5132 | 4378 | } |
29b0f896 AM |
4379 | } |
4380 | } | |
47926f60 | 4381 | |
29b0f896 AM |
4382 | /* Try to use the smallest displacement type too. */ |
4383 | static void | |
e3bb37b5 | 4384 | optimize_disp (void) |
29b0f896 AM |
4385 | { |
4386 | int op; | |
3e73aa7c | 4387 | |
29b0f896 | 4388 | for (op = i.operands; --op >= 0;) |
40fb9820 | 4389 | if (operand_type_check (i.types[op], disp)) |
252b5132 | 4390 | { |
b300c311 | 4391 | if (i.op[op].disps->X_op == O_constant) |
252b5132 | 4392 | { |
91d6fa6a | 4393 | offsetT op_disp = i.op[op].disps->X_add_number; |
29b0f896 | 4394 | |
40fb9820 | 4395 | if (i.types[op].bitfield.disp16 |
91d6fa6a | 4396 | && (op_disp & ~(offsetT) 0xffff) == 0) |
b300c311 L |
4397 | { |
4398 | /* If this operand is at most 16 bits, convert | |
4399 | to a signed 16 bit number and don't use 64bit | |
4400 | displacement. */ | |
91d6fa6a | 4401 | op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000); |
40fb9820 | 4402 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 4403 | } |
a28def75 L |
4404 | #ifdef BFD64 |
4405 | /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */ | |
40fb9820 | 4406 | if (i.types[op].bitfield.disp32 |
91d6fa6a | 4407 | && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0) |
b300c311 L |
4408 | { |
4409 | /* If this operand is at most 32 bits, convert | |
4410 | to a signed 32 bit number and don't use 64bit | |
4411 | displacement. */ | |
91d6fa6a NC |
4412 | op_disp &= (((offsetT) 2 << 31) - 1); |
4413 | op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
40fb9820 | 4414 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 4415 | } |
a28def75 | 4416 | #endif |
91d6fa6a | 4417 | if (!op_disp && i.types[op].bitfield.baseindex) |
b300c311 | 4418 | { |
40fb9820 L |
4419 | i.types[op].bitfield.disp8 = 0; |
4420 | i.types[op].bitfield.disp16 = 0; | |
4421 | i.types[op].bitfield.disp32 = 0; | |
4422 | i.types[op].bitfield.disp32s = 0; | |
4423 | i.types[op].bitfield.disp64 = 0; | |
b300c311 L |
4424 | i.op[op].disps = 0; |
4425 | i.disp_operands--; | |
4426 | } | |
4427 | else if (flag_code == CODE_64BIT) | |
4428 | { | |
91d6fa6a | 4429 | if (fits_in_signed_long (op_disp)) |
28a9d8f5 | 4430 | { |
40fb9820 L |
4431 | i.types[op].bitfield.disp64 = 0; |
4432 | i.types[op].bitfield.disp32s = 1; | |
28a9d8f5 | 4433 | } |
0e1147d9 | 4434 | if (i.prefix[ADDR_PREFIX] |
91d6fa6a | 4435 | && fits_in_unsigned_long (op_disp)) |
40fb9820 | 4436 | i.types[op].bitfield.disp32 = 1; |
b300c311 | 4437 | } |
40fb9820 L |
4438 | if ((i.types[op].bitfield.disp32 |
4439 | || i.types[op].bitfield.disp32s | |
4440 | || i.types[op].bitfield.disp16) | |
91d6fa6a | 4441 | && fits_in_signed_byte (op_disp)) |
40fb9820 | 4442 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 4443 | } |
67a4f2b7 AO |
4444 | else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
4445 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) | |
4446 | { | |
4447 | fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, | |
4448 | i.op[op].disps, 0, i.reloc[op]); | |
40fb9820 L |
4449 | i.types[op].bitfield.disp8 = 0; |
4450 | i.types[op].bitfield.disp16 = 0; | |
4451 | i.types[op].bitfield.disp32 = 0; | |
4452 | i.types[op].bitfield.disp32s = 0; | |
4453 | i.types[op].bitfield.disp64 = 0; | |
67a4f2b7 AO |
4454 | } |
4455 | else | |
b300c311 | 4456 | /* We only support 64bit displacement on constants. */ |
40fb9820 | 4457 | i.types[op].bitfield.disp64 = 0; |
252b5132 | 4458 | } |
29b0f896 AM |
4459 | } |
4460 | ||
6c30d220 L |
4461 | /* Check if operands are valid for the instruction. */ |
4462 | ||
4463 | static int | |
4464 | check_VecOperands (const insn_template *t) | |
4465 | { | |
43234a1e L |
4466 | unsigned int op; |
4467 | ||
6c30d220 L |
4468 | /* Without VSIB byte, we can't have a vector register for index. */ |
4469 | if (!t->opcode_modifier.vecsib | |
4470 | && i.index_reg | |
4471 | && (i.index_reg->reg_type.bitfield.regxmm | |
43234a1e L |
4472 | || i.index_reg->reg_type.bitfield.regymm |
4473 | || i.index_reg->reg_type.bitfield.regzmm)) | |
6c30d220 L |
4474 | { |
4475 | i.error = unsupported_vector_index_register; | |
4476 | return 1; | |
4477 | } | |
4478 | ||
ad8ecc81 MZ |
4479 | /* Check if default mask is allowed. */ |
4480 | if (t->opcode_modifier.nodefmask | |
4481 | && (!i.mask || i.mask->mask->reg_num == 0)) | |
4482 | { | |
4483 | i.error = no_default_mask; | |
4484 | return 1; | |
4485 | } | |
4486 | ||
7bab8ab5 JB |
4487 | /* For VSIB byte, we need a vector register for index, and all vector |
4488 | registers must be distinct. */ | |
4489 | if (t->opcode_modifier.vecsib) | |
4490 | { | |
4491 | if (!i.index_reg | |
6c30d220 L |
4492 | || !((t->opcode_modifier.vecsib == VecSIB128 |
4493 | && i.index_reg->reg_type.bitfield.regxmm) | |
4494 | || (t->opcode_modifier.vecsib == VecSIB256 | |
43234a1e L |
4495 | && i.index_reg->reg_type.bitfield.regymm) |
4496 | || (t->opcode_modifier.vecsib == VecSIB512 | |
4497 | && i.index_reg->reg_type.bitfield.regzmm))) | |
7bab8ab5 JB |
4498 | { |
4499 | i.error = invalid_vsib_address; | |
4500 | return 1; | |
4501 | } | |
4502 | ||
43234a1e L |
4503 | gas_assert (i.reg_operands == 2 || i.mask); |
4504 | if (i.reg_operands == 2 && !i.mask) | |
4505 | { | |
4506 | gas_assert (i.types[0].bitfield.regxmm | |
7c84a0ca | 4507 | || i.types[0].bitfield.regymm); |
43234a1e | 4508 | gas_assert (i.types[2].bitfield.regxmm |
7c84a0ca | 4509 | || i.types[2].bitfield.regymm); |
43234a1e L |
4510 | if (operand_check == check_none) |
4511 | return 0; | |
4512 | if (register_number (i.op[0].regs) | |
4513 | != register_number (i.index_reg) | |
4514 | && register_number (i.op[2].regs) | |
4515 | != register_number (i.index_reg) | |
4516 | && register_number (i.op[0].regs) | |
4517 | != register_number (i.op[2].regs)) | |
4518 | return 0; | |
4519 | if (operand_check == check_error) | |
4520 | { | |
4521 | i.error = invalid_vector_register_set; | |
4522 | return 1; | |
4523 | } | |
4524 | as_warn (_("mask, index, and destination registers should be distinct")); | |
4525 | } | |
8444f82a MZ |
4526 | else if (i.reg_operands == 1 && i.mask) |
4527 | { | |
4528 | if ((i.types[1].bitfield.regymm | |
4529 | || i.types[1].bitfield.regzmm) | |
4530 | && (register_number (i.op[1].regs) | |
4531 | == register_number (i.index_reg))) | |
4532 | { | |
4533 | if (operand_check == check_error) | |
4534 | { | |
4535 | i.error = invalid_vector_register_set; | |
4536 | return 1; | |
4537 | } | |
4538 | if (operand_check != check_none) | |
4539 | as_warn (_("index and destination registers should be distinct")); | |
4540 | } | |
4541 | } | |
43234a1e | 4542 | } |
7bab8ab5 | 4543 | |
43234a1e L |
4544 | /* Check if broadcast is supported by the instruction and is applied |
4545 | to the memory operand. */ | |
4546 | if (i.broadcast) | |
4547 | { | |
4548 | int broadcasted_opnd_size; | |
4549 | ||
4550 | /* Check if specified broadcast is supported in this instruction, | |
4551 | and it's applied to memory operand of DWORD or QWORD type, | |
4552 | depending on VecESize. */ | |
4553 | if (i.broadcast->type != t->opcode_modifier.broadcast | |
4554 | || !i.types[i.broadcast->operand].bitfield.mem | |
4555 | || (t->opcode_modifier.vecesize == 0 | |
4556 | && !i.types[i.broadcast->operand].bitfield.dword | |
4557 | && !i.types[i.broadcast->operand].bitfield.unspecified) | |
4558 | || (t->opcode_modifier.vecesize == 1 | |
4559 | && !i.types[i.broadcast->operand].bitfield.qword | |
4560 | && !i.types[i.broadcast->operand].bitfield.unspecified)) | |
4561 | goto bad_broadcast; | |
4562 | ||
4563 | broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32; | |
4564 | if (i.broadcast->type == BROADCAST_1TO16) | |
4565 | broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */ | |
4566 | else if (i.broadcast->type == BROADCAST_1TO8) | |
4567 | broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */ | |
b28d1bda IT |
4568 | else if (i.broadcast->type == BROADCAST_1TO4) |
4569 | broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */ | |
4570 | else if (i.broadcast->type == BROADCAST_1TO2) | |
4571 | broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */ | |
43234a1e L |
4572 | else |
4573 | goto bad_broadcast; | |
4574 | ||
4575 | if ((broadcasted_opnd_size == 256 | |
4576 | && !t->operand_types[i.broadcast->operand].bitfield.ymmword) | |
4577 | || (broadcasted_opnd_size == 512 | |
4578 | && !t->operand_types[i.broadcast->operand].bitfield.zmmword)) | |
4579 | { | |
4580 | bad_broadcast: | |
4581 | i.error = unsupported_broadcast; | |
4582 | return 1; | |
4583 | } | |
4584 | } | |
4585 | /* If broadcast is supported in this instruction, we need to check if | |
4586 | operand of one-element size isn't specified without broadcast. */ | |
4587 | else if (t->opcode_modifier.broadcast && i.mem_operands) | |
4588 | { | |
4589 | /* Find memory operand. */ | |
4590 | for (op = 0; op < i.operands; op++) | |
4591 | if (operand_type_check (i.types[op], anymem)) | |
4592 | break; | |
4593 | gas_assert (op < i.operands); | |
4594 | /* Check size of the memory operand. */ | |
4595 | if ((t->opcode_modifier.vecesize == 0 | |
4596 | && i.types[op].bitfield.dword) | |
4597 | || (t->opcode_modifier.vecesize == 1 | |
4598 | && i.types[op].bitfield.qword)) | |
4599 | { | |
4600 | i.error = broadcast_needed; | |
4601 | return 1; | |
4602 | } | |
4603 | } | |
4604 | ||
4605 | /* Check if requested masking is supported. */ | |
4606 | if (i.mask | |
4607 | && (!t->opcode_modifier.masking | |
4608 | || (i.mask->zeroing | |
4609 | && t->opcode_modifier.masking == MERGING_MASKING))) | |
4610 | { | |
4611 | i.error = unsupported_masking; | |
4612 | return 1; | |
4613 | } | |
4614 | ||
4615 | /* Check if masking is applied to dest operand. */ | |
4616 | if (i.mask && (i.mask->operand != (int) (i.operands - 1))) | |
4617 | { | |
4618 | i.error = mask_not_on_destination; | |
4619 | return 1; | |
4620 | } | |
4621 | ||
43234a1e L |
4622 | /* Check RC/SAE. */ |
4623 | if (i.rounding) | |
4624 | { | |
4625 | if ((i.rounding->type != saeonly | |
4626 | && !t->opcode_modifier.staticrounding) | |
4627 | || (i.rounding->type == saeonly | |
4628 | && (t->opcode_modifier.staticrounding | |
4629 | || !t->opcode_modifier.sae))) | |
4630 | { | |
4631 | i.error = unsupported_rc_sae; | |
4632 | return 1; | |
4633 | } | |
4634 | /* If the instruction has several immediate operands and one of | |
4635 | them is rounding, the rounding operand should be the last | |
4636 | immediate operand. */ | |
4637 | if (i.imm_operands > 1 | |
4638 | && i.rounding->operand != (int) (i.imm_operands - 1)) | |
7bab8ab5 | 4639 | { |
43234a1e | 4640 | i.error = rc_sae_operand_not_last_imm; |
7bab8ab5 JB |
4641 | return 1; |
4642 | } | |
6c30d220 L |
4643 | } |
4644 | ||
43234a1e L |
4645 | /* Check vector Disp8 operand. */ |
4646 | if (t->opcode_modifier.disp8memshift) | |
4647 | { | |
4648 | if (i.broadcast) | |
4649 | i.memshift = t->opcode_modifier.vecesize ? 3 : 2; | |
4650 | else | |
4651 | i.memshift = t->opcode_modifier.disp8memshift; | |
4652 | ||
4653 | for (op = 0; op < i.operands; op++) | |
4654 | if (operand_type_check (i.types[op], disp) | |
4655 | && i.op[op].disps->X_op == O_constant) | |
4656 | { | |
4657 | offsetT value = i.op[op].disps->X_add_number; | |
5be33403 L |
4658 | int vec_disp8_ok |
4659 | = (i.disp_encoding != disp_encoding_32bit | |
4660 | && fits_in_vec_disp8 (value)); | |
43234a1e L |
4661 | if (t->operand_types [op].bitfield.vec_disp8) |
4662 | { | |
4663 | if (vec_disp8_ok) | |
4664 | i.types[op].bitfield.vec_disp8 = 1; | |
4665 | else | |
4666 | { | |
4667 | /* Vector insn can only have Vec_Disp8/Disp32 in | |
4668 | 32/64bit modes, and Vec_Disp8/Disp16 in 16bit | |
4669 | mode. */ | |
4670 | i.types[op].bitfield.disp8 = 0; | |
4671 | if (flag_code != CODE_16BIT) | |
4672 | i.types[op].bitfield.disp16 = 0; | |
4673 | } | |
4674 | } | |
4675 | else if (flag_code != CODE_16BIT) | |
4676 | { | |
4677 | /* One form of this instruction supports vector Disp8. | |
4678 | Try vector Disp8 if we need to use Disp32. */ | |
4679 | if (vec_disp8_ok && !fits_in_signed_byte (value)) | |
4680 | { | |
4681 | i.error = try_vector_disp8; | |
4682 | return 1; | |
4683 | } | |
4684 | } | |
4685 | } | |
4686 | } | |
4687 | else | |
4688 | i.memshift = -1; | |
4689 | ||
6c30d220 L |
4690 | return 0; |
4691 | } | |
4692 | ||
43f3e2ee | 4693 | /* Check if operands are valid for the instruction. Update VEX |
a683cc34 SP |
4694 | operand types. */ |
4695 | ||
4696 | static int | |
4697 | VEX_check_operands (const insn_template *t) | |
4698 | { | |
43234a1e L |
4699 | /* VREX is only valid with EVEX prefix. */ |
4700 | if (i.need_vrex && !t->opcode_modifier.evex) | |
4701 | { | |
4702 | i.error = invalid_register_operand; | |
4703 | return 1; | |
4704 | } | |
4705 | ||
a683cc34 SP |
4706 | if (!t->opcode_modifier.vex) |
4707 | return 0; | |
4708 | ||
4709 | /* Only check VEX_Imm4, which must be the first operand. */ | |
4710 | if (t->operand_types[0].bitfield.vec_imm4) | |
4711 | { | |
4712 | if (i.op[0].imms->X_op != O_constant | |
4713 | || !fits_in_imm4 (i.op[0].imms->X_add_number)) | |
891edac4 | 4714 | { |
a65babc9 | 4715 | i.error = bad_imm4; |
891edac4 L |
4716 | return 1; |
4717 | } | |
a683cc34 SP |
4718 | |
4719 | /* Turn off Imm8 so that update_imm won't complain. */ | |
4720 | i.types[0] = vec_imm4; | |
4721 | } | |
4722 | ||
4723 | return 0; | |
4724 | } | |
4725 | ||
d3ce72d0 | 4726 | static const insn_template * |
e3bb37b5 | 4727 | match_template (void) |
29b0f896 AM |
4728 | { |
4729 | /* Points to template once we've found it. */ | |
d3ce72d0 | 4730 | const insn_template *t; |
40fb9820 | 4731 | i386_operand_type overlap0, overlap1, overlap2, overlap3; |
c0f3af97 | 4732 | i386_operand_type overlap4; |
29b0f896 | 4733 | unsigned int found_reverse_match; |
40fb9820 L |
4734 | i386_opcode_modifier suffix_check; |
4735 | i386_operand_type operand_types [MAX_OPERANDS]; | |
539e75ad | 4736 | int addr_prefix_disp; |
a5c311ca | 4737 | unsigned int j; |
3629bb00 | 4738 | unsigned int found_cpu_match; |
45664ddb | 4739 | unsigned int check_register; |
5614d22c | 4740 | enum i386_error specific_error = 0; |
29b0f896 | 4741 | |
c0f3af97 L |
4742 | #if MAX_OPERANDS != 5 |
4743 | # error "MAX_OPERANDS must be 5." | |
f48ff2ae L |
4744 | #endif |
4745 | ||
29b0f896 | 4746 | found_reverse_match = 0; |
539e75ad | 4747 | addr_prefix_disp = -1; |
40fb9820 L |
4748 | |
4749 | memset (&suffix_check, 0, sizeof (suffix_check)); | |
4750 | if (i.suffix == BYTE_MNEM_SUFFIX) | |
4751 | suffix_check.no_bsuf = 1; | |
4752 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
4753 | suffix_check.no_wsuf = 1; | |
4754 | else if (i.suffix == SHORT_MNEM_SUFFIX) | |
4755 | suffix_check.no_ssuf = 1; | |
4756 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
4757 | suffix_check.no_lsuf = 1; | |
4758 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
4759 | suffix_check.no_qsuf = 1; | |
4760 | else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX) | |
7ce189b3 | 4761 | suffix_check.no_ldsuf = 1; |
29b0f896 | 4762 | |
01559ecc L |
4763 | /* Must have right number of operands. */ |
4764 | i.error = number_of_operands_mismatch; | |
4765 | ||
45aa61fe | 4766 | for (t = current_templates->start; t < current_templates->end; t++) |
29b0f896 | 4767 | { |
539e75ad L |
4768 | addr_prefix_disp = -1; |
4769 | ||
29b0f896 AM |
4770 | if (i.operands != t->operands) |
4771 | continue; | |
4772 | ||
50aecf8c | 4773 | /* Check processor support. */ |
a65babc9 | 4774 | i.error = unsupported; |
c0f3af97 L |
4775 | found_cpu_match = (cpu_flags_match (t) |
4776 | == CPU_FLAGS_PERFECT_MATCH); | |
50aecf8c L |
4777 | if (!found_cpu_match) |
4778 | continue; | |
4779 | ||
e1d4d893 | 4780 | /* Check old gcc support. */ |
a65babc9 | 4781 | i.error = old_gcc_only; |
e1d4d893 L |
4782 | if (!old_gcc && t->opcode_modifier.oldgcc) |
4783 | continue; | |
4784 | ||
4785 | /* Check AT&T mnemonic. */ | |
a65babc9 | 4786 | i.error = unsupported_with_intel_mnemonic; |
e1d4d893 | 4787 | if (intel_mnemonic && t->opcode_modifier.attmnemonic) |
1efbbeb4 L |
4788 | continue; |
4789 | ||
e92bae62 | 4790 | /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */ |
a65babc9 | 4791 | i.error = unsupported_syntax; |
5c07affc | 4792 | if ((intel_syntax && t->opcode_modifier.attsyntax) |
e92bae62 L |
4793 | || (!intel_syntax && t->opcode_modifier.intelsyntax) |
4794 | || (intel64 && t->opcode_modifier.amd64) | |
4795 | || (!intel64 && t->opcode_modifier.intel64)) | |
1efbbeb4 L |
4796 | continue; |
4797 | ||
20592a94 | 4798 | /* Check the suffix, except for some instructions in intel mode. */ |
a65babc9 | 4799 | i.error = invalid_instruction_suffix; |
567e4e96 L |
4800 | if ((!intel_syntax || !t->opcode_modifier.ignoresize) |
4801 | && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf) | |
4802 | || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf) | |
4803 | || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf) | |
4804 | || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf) | |
4805 | || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf) | |
4806 | || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf))) | |
29b0f896 AM |
4807 | continue; |
4808 | ||
5c07affc | 4809 | if (!operand_size_match (t)) |
7d5e4556 | 4810 | continue; |
539e75ad | 4811 | |
5c07affc L |
4812 | for (j = 0; j < MAX_OPERANDS; j++) |
4813 | operand_types[j] = t->operand_types[j]; | |
4814 | ||
45aa61fe AM |
4815 | /* In general, don't allow 64-bit operands in 32-bit mode. */ |
4816 | if (i.suffix == QWORD_MNEM_SUFFIX | |
4817 | && flag_code != CODE_64BIT | |
4818 | && (intel_syntax | |
40fb9820 | 4819 | ? (!t->opcode_modifier.ignoresize |
45aa61fe AM |
4820 | && !intel_float_operand (t->name)) |
4821 | : intel_float_operand (t->name) != 2) | |
40fb9820 | 4822 | && ((!operand_types[0].bitfield.regmmx |
c0f3af97 | 4823 | && !operand_types[0].bitfield.regxmm |
43234a1e L |
4824 | && !operand_types[0].bitfield.regymm |
4825 | && !operand_types[0].bitfield.regzmm) | |
40fb9820 | 4826 | || (!operand_types[t->operands > 1].bitfield.regmmx |
ac4eb736 AM |
4827 | && operand_types[t->operands > 1].bitfield.regxmm |
4828 | && operand_types[t->operands > 1].bitfield.regymm | |
4829 | && operand_types[t->operands > 1].bitfield.regzmm)) | |
45aa61fe AM |
4830 | && (t->base_opcode != 0x0fc7 |
4831 | || t->extension_opcode != 1 /* cmpxchg8b */)) | |
4832 | continue; | |
4833 | ||
192dc9c6 JB |
4834 | /* In general, don't allow 32-bit operands on pre-386. */ |
4835 | else if (i.suffix == LONG_MNEM_SUFFIX | |
4836 | && !cpu_arch_flags.bitfield.cpui386 | |
4837 | && (intel_syntax | |
4838 | ? (!t->opcode_modifier.ignoresize | |
4839 | && !intel_float_operand (t->name)) | |
4840 | : intel_float_operand (t->name) != 2) | |
4841 | && ((!operand_types[0].bitfield.regmmx | |
4842 | && !operand_types[0].bitfield.regxmm) | |
4843 | || (!operand_types[t->operands > 1].bitfield.regmmx | |
ac4eb736 | 4844 | && operand_types[t->operands > 1].bitfield.regxmm))) |
192dc9c6 JB |
4845 | continue; |
4846 | ||
29b0f896 | 4847 | /* Do not verify operands when there are none. */ |
50aecf8c | 4848 | else |
29b0f896 | 4849 | { |
c6fb90c8 | 4850 | if (!t->operands) |
2dbab7d5 L |
4851 | /* We've found a match; break out of loop. */ |
4852 | break; | |
29b0f896 | 4853 | } |
252b5132 | 4854 | |
539e75ad L |
4855 | /* Address size prefix will turn Disp64/Disp32/Disp16 operand |
4856 | into Disp32/Disp16/Disp32 operand. */ | |
4857 | if (i.prefix[ADDR_PREFIX] != 0) | |
4858 | { | |
40fb9820 | 4859 | /* There should be only one Disp operand. */ |
539e75ad L |
4860 | switch (flag_code) |
4861 | { | |
4862 | case CODE_16BIT: | |
40fb9820 L |
4863 | for (j = 0; j < MAX_OPERANDS; j++) |
4864 | { | |
4865 | if (operand_types[j].bitfield.disp16) | |
4866 | { | |
4867 | addr_prefix_disp = j; | |
4868 | operand_types[j].bitfield.disp32 = 1; | |
4869 | operand_types[j].bitfield.disp16 = 0; | |
4870 | break; | |
4871 | } | |
4872 | } | |
539e75ad L |
4873 | break; |
4874 | case CODE_32BIT: | |
40fb9820 L |
4875 | for (j = 0; j < MAX_OPERANDS; j++) |
4876 | { | |
4877 | if (operand_types[j].bitfield.disp32) | |
4878 | { | |
4879 | addr_prefix_disp = j; | |
4880 | operand_types[j].bitfield.disp32 = 0; | |
4881 | operand_types[j].bitfield.disp16 = 1; | |
4882 | break; | |
4883 | } | |
4884 | } | |
539e75ad L |
4885 | break; |
4886 | case CODE_64BIT: | |
40fb9820 L |
4887 | for (j = 0; j < MAX_OPERANDS; j++) |
4888 | { | |
4889 | if (operand_types[j].bitfield.disp64) | |
4890 | { | |
4891 | addr_prefix_disp = j; | |
4892 | operand_types[j].bitfield.disp64 = 0; | |
4893 | operand_types[j].bitfield.disp32 = 1; | |
4894 | break; | |
4895 | } | |
4896 | } | |
539e75ad L |
4897 | break; |
4898 | } | |
539e75ad L |
4899 | } |
4900 | ||
02a86693 L |
4901 | /* Force 0x8b encoding for "mov foo@GOT, %eax". */ |
4902 | if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0) | |
4903 | continue; | |
4904 | ||
56ffb741 L |
4905 | /* We check register size if needed. */ |
4906 | check_register = t->opcode_modifier.checkregsize; | |
c6fb90c8 | 4907 | overlap0 = operand_type_and (i.types[0], operand_types[0]); |
29b0f896 AM |
4908 | switch (t->operands) |
4909 | { | |
4910 | case 1: | |
40fb9820 | 4911 | if (!operand_type_match (overlap0, i.types[0])) |
29b0f896 AM |
4912 | continue; |
4913 | break; | |
4914 | case 2: | |
8b38ad71 L |
4915 | /* xchg %eax, %eax is a special case. It is an aliase for nop |
4916 | only in 32bit mode and we can use opcode 0x90. In 64bit | |
4917 | mode, we can't use 0x90 for xchg %eax, %eax since it should | |
4918 | zero-extend %eax to %rax. */ | |
4919 | if (flag_code == CODE_64BIT | |
4920 | && t->base_opcode == 0x90 | |
0dfbf9d7 L |
4921 | && operand_type_equal (&i.types [0], &acc32) |
4922 | && operand_type_equal (&i.types [1], &acc32)) | |
8b38ad71 | 4923 | continue; |
b6169b20 L |
4924 | if (i.swap_operand) |
4925 | { | |
4926 | /* If we swap operand in encoding, we either match | |
4927 | the next one or reverse direction of operands. */ | |
4928 | if (t->opcode_modifier.s) | |
4929 | continue; | |
4930 | else if (t->opcode_modifier.d) | |
4931 | goto check_reverse; | |
4932 | } | |
4933 | ||
29b0f896 | 4934 | case 3: |
fa99fab2 L |
4935 | /* If we swap operand in encoding, we match the next one. */ |
4936 | if (i.swap_operand && t->opcode_modifier.s) | |
4937 | continue; | |
f48ff2ae | 4938 | case 4: |
c0f3af97 | 4939 | case 5: |
c6fb90c8 | 4940 | overlap1 = operand_type_and (i.types[1], operand_types[1]); |
40fb9820 L |
4941 | if (!operand_type_match (overlap0, i.types[0]) |
4942 | || !operand_type_match (overlap1, i.types[1]) | |
45664ddb L |
4943 | || (check_register |
4944 | && !operand_type_register_match (overlap0, i.types[0], | |
40fb9820 L |
4945 | operand_types[0], |
4946 | overlap1, i.types[1], | |
4947 | operand_types[1]))) | |
29b0f896 AM |
4948 | { |
4949 | /* Check if other direction is valid ... */ | |
40fb9820 | 4950 | if (!t->opcode_modifier.d && !t->opcode_modifier.floatd) |
29b0f896 AM |
4951 | continue; |
4952 | ||
b6169b20 | 4953 | check_reverse: |
29b0f896 | 4954 | /* Try reversing direction of operands. */ |
c6fb90c8 L |
4955 | overlap0 = operand_type_and (i.types[0], operand_types[1]); |
4956 | overlap1 = operand_type_and (i.types[1], operand_types[0]); | |
40fb9820 L |
4957 | if (!operand_type_match (overlap0, i.types[0]) |
4958 | || !operand_type_match (overlap1, i.types[1]) | |
45664ddb L |
4959 | || (check_register |
4960 | && !operand_type_register_match (overlap0, | |
4961 | i.types[0], | |
4962 | operand_types[1], | |
4963 | overlap1, | |
4964 | i.types[1], | |
4965 | operand_types[0]))) | |
29b0f896 AM |
4966 | { |
4967 | /* Does not match either direction. */ | |
4968 | continue; | |
4969 | } | |
4970 | /* found_reverse_match holds which of D or FloatDR | |
4971 | we've found. */ | |
40fb9820 | 4972 | if (t->opcode_modifier.d) |
8a2ed489 | 4973 | found_reverse_match = Opcode_D; |
40fb9820 | 4974 | else if (t->opcode_modifier.floatd) |
8a2ed489 L |
4975 | found_reverse_match = Opcode_FloatD; |
4976 | else | |
4977 | found_reverse_match = 0; | |
40fb9820 | 4978 | if (t->opcode_modifier.floatr) |
8a2ed489 | 4979 | found_reverse_match |= Opcode_FloatR; |
29b0f896 | 4980 | } |
f48ff2ae | 4981 | else |
29b0f896 | 4982 | { |
f48ff2ae | 4983 | /* Found a forward 2 operand match here. */ |
d1cbb4db L |
4984 | switch (t->operands) |
4985 | { | |
c0f3af97 L |
4986 | case 5: |
4987 | overlap4 = operand_type_and (i.types[4], | |
4988 | operand_types[4]); | |
d1cbb4db | 4989 | case 4: |
c6fb90c8 L |
4990 | overlap3 = operand_type_and (i.types[3], |
4991 | operand_types[3]); | |
d1cbb4db | 4992 | case 3: |
c6fb90c8 L |
4993 | overlap2 = operand_type_and (i.types[2], |
4994 | operand_types[2]); | |
d1cbb4db L |
4995 | break; |
4996 | } | |
29b0f896 | 4997 | |
f48ff2ae L |
4998 | switch (t->operands) |
4999 | { | |
c0f3af97 L |
5000 | case 5: |
5001 | if (!operand_type_match (overlap4, i.types[4]) | |
5002 | || !operand_type_register_match (overlap3, | |
5003 | i.types[3], | |
5004 | operand_types[3], | |
5005 | overlap4, | |
5006 | i.types[4], | |
5007 | operand_types[4])) | |
5008 | continue; | |
f48ff2ae | 5009 | case 4: |
40fb9820 | 5010 | if (!operand_type_match (overlap3, i.types[3]) |
45664ddb L |
5011 | || (check_register |
5012 | && !operand_type_register_match (overlap2, | |
5013 | i.types[2], | |
5014 | operand_types[2], | |
5015 | overlap3, | |
5016 | i.types[3], | |
5017 | operand_types[3]))) | |
f48ff2ae L |
5018 | continue; |
5019 | case 3: | |
5020 | /* Here we make use of the fact that there are no | |
5021 | reverse match 3 operand instructions, and all 3 | |
5022 | operand instructions only need to be checked for | |
5023 | register consistency between operands 2 and 3. */ | |
40fb9820 | 5024 | if (!operand_type_match (overlap2, i.types[2]) |
45664ddb L |
5025 | || (check_register |
5026 | && !operand_type_register_match (overlap1, | |
5027 | i.types[1], | |
5028 | operand_types[1], | |
5029 | overlap2, | |
5030 | i.types[2], | |
5031 | operand_types[2]))) | |
f48ff2ae L |
5032 | continue; |
5033 | break; | |
5034 | } | |
29b0f896 | 5035 | } |
f48ff2ae | 5036 | /* Found either forward/reverse 2, 3 or 4 operand match here: |
29b0f896 AM |
5037 | slip through to break. */ |
5038 | } | |
3629bb00 | 5039 | if (!found_cpu_match) |
29b0f896 AM |
5040 | { |
5041 | found_reverse_match = 0; | |
5042 | continue; | |
5043 | } | |
c0f3af97 | 5044 | |
5614d22c JB |
5045 | /* Check if vector and VEX operands are valid. */ |
5046 | if (check_VecOperands (t) || VEX_check_operands (t)) | |
5047 | { | |
5048 | specific_error = i.error; | |
5049 | continue; | |
5050 | } | |
a683cc34 | 5051 | |
29b0f896 AM |
5052 | /* We've found a match; break out of loop. */ |
5053 | break; | |
5054 | } | |
5055 | ||
5056 | if (t == current_templates->end) | |
5057 | { | |
5058 | /* We found no match. */ | |
a65babc9 | 5059 | const char *err_msg; |
5614d22c | 5060 | switch (specific_error ? specific_error : i.error) |
a65babc9 L |
5061 | { |
5062 | default: | |
5063 | abort (); | |
86e026a4 | 5064 | case operand_size_mismatch: |
a65babc9 L |
5065 | err_msg = _("operand size mismatch"); |
5066 | break; | |
5067 | case operand_type_mismatch: | |
5068 | err_msg = _("operand type mismatch"); | |
5069 | break; | |
5070 | case register_type_mismatch: | |
5071 | err_msg = _("register type mismatch"); | |
5072 | break; | |
5073 | case number_of_operands_mismatch: | |
5074 | err_msg = _("number of operands mismatch"); | |
5075 | break; | |
5076 | case invalid_instruction_suffix: | |
5077 | err_msg = _("invalid instruction suffix"); | |
5078 | break; | |
5079 | case bad_imm4: | |
4a2608e3 | 5080 | err_msg = _("constant doesn't fit in 4 bits"); |
a65babc9 L |
5081 | break; |
5082 | case old_gcc_only: | |
5083 | err_msg = _("only supported with old gcc"); | |
5084 | break; | |
5085 | case unsupported_with_intel_mnemonic: | |
5086 | err_msg = _("unsupported with Intel mnemonic"); | |
5087 | break; | |
5088 | case unsupported_syntax: | |
5089 | err_msg = _("unsupported syntax"); | |
5090 | break; | |
5091 | case unsupported: | |
35262a23 | 5092 | as_bad (_("unsupported instruction `%s'"), |
10efe3f6 L |
5093 | current_templates->start->name); |
5094 | return NULL; | |
6c30d220 L |
5095 | case invalid_vsib_address: |
5096 | err_msg = _("invalid VSIB address"); | |
5097 | break; | |
7bab8ab5 JB |
5098 | case invalid_vector_register_set: |
5099 | err_msg = _("mask, index, and destination registers must be distinct"); | |
5100 | break; | |
6c30d220 L |
5101 | case unsupported_vector_index_register: |
5102 | err_msg = _("unsupported vector index register"); | |
5103 | break; | |
43234a1e L |
5104 | case unsupported_broadcast: |
5105 | err_msg = _("unsupported broadcast"); | |
5106 | break; | |
5107 | case broadcast_not_on_src_operand: | |
5108 | err_msg = _("broadcast not on source memory operand"); | |
5109 | break; | |
5110 | case broadcast_needed: | |
5111 | err_msg = _("broadcast is needed for operand of such type"); | |
5112 | break; | |
5113 | case unsupported_masking: | |
5114 | err_msg = _("unsupported masking"); | |
5115 | break; | |
5116 | case mask_not_on_destination: | |
5117 | err_msg = _("mask not on destination operand"); | |
5118 | break; | |
5119 | case no_default_mask: | |
5120 | err_msg = _("default mask isn't allowed"); | |
5121 | break; | |
5122 | case unsupported_rc_sae: | |
5123 | err_msg = _("unsupported static rounding/sae"); | |
5124 | break; | |
5125 | case rc_sae_operand_not_last_imm: | |
5126 | if (intel_syntax) | |
5127 | err_msg = _("RC/SAE operand must precede immediate operands"); | |
5128 | else | |
5129 | err_msg = _("RC/SAE operand must follow immediate operands"); | |
5130 | break; | |
5131 | case invalid_register_operand: | |
5132 | err_msg = _("invalid register operand"); | |
5133 | break; | |
a65babc9 L |
5134 | } |
5135 | as_bad (_("%s for `%s'"), err_msg, | |
891edac4 | 5136 | current_templates->start->name); |
fa99fab2 | 5137 | return NULL; |
29b0f896 | 5138 | } |
252b5132 | 5139 | |
29b0f896 AM |
5140 | if (!quiet_warnings) |
5141 | { | |
5142 | if (!intel_syntax | |
40fb9820 L |
5143 | && (i.types[0].bitfield.jumpabsolute |
5144 | != operand_types[0].bitfield.jumpabsolute)) | |
29b0f896 AM |
5145 | { |
5146 | as_warn (_("indirect %s without `*'"), t->name); | |
5147 | } | |
5148 | ||
40fb9820 L |
5149 | if (t->opcode_modifier.isprefix |
5150 | && t->opcode_modifier.ignoresize) | |
29b0f896 AM |
5151 | { |
5152 | /* Warn them that a data or address size prefix doesn't | |
5153 | affect assembly of the next line of code. */ | |
5154 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
5155 | } | |
5156 | } | |
5157 | ||
5158 | /* Copy the template we found. */ | |
5159 | i.tm = *t; | |
539e75ad L |
5160 | |
5161 | if (addr_prefix_disp != -1) | |
5162 | i.tm.operand_types[addr_prefix_disp] | |
5163 | = operand_types[addr_prefix_disp]; | |
5164 | ||
29b0f896 AM |
5165 | if (found_reverse_match) |
5166 | { | |
5167 | /* If we found a reverse match we must alter the opcode | |
5168 | direction bit. found_reverse_match holds bits to change | |
5169 | (different for int & float insns). */ | |
5170 | ||
5171 | i.tm.base_opcode ^= found_reverse_match; | |
5172 | ||
539e75ad L |
5173 | i.tm.operand_types[0] = operand_types[1]; |
5174 | i.tm.operand_types[1] = operand_types[0]; | |
29b0f896 AM |
5175 | } |
5176 | ||
fa99fab2 | 5177 | return t; |
29b0f896 AM |
5178 | } |
5179 | ||
5180 | static int | |
e3bb37b5 | 5181 | check_string (void) |
29b0f896 | 5182 | { |
40fb9820 L |
5183 | int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1; |
5184 | if (i.tm.operand_types[mem_op].bitfield.esseg) | |
29b0f896 AM |
5185 | { |
5186 | if (i.seg[0] != NULL && i.seg[0] != &es) | |
5187 | { | |
a87af027 | 5188 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
29b0f896 | 5189 | i.tm.name, |
a87af027 JB |
5190 | mem_op + 1, |
5191 | register_prefix); | |
29b0f896 AM |
5192 | return 0; |
5193 | } | |
5194 | /* There's only ever one segment override allowed per instruction. | |
5195 | This instruction possibly has a legal segment override on the | |
5196 | second operand, so copy the segment to where non-string | |
5197 | instructions store it, allowing common code. */ | |
5198 | i.seg[0] = i.seg[1]; | |
5199 | } | |
40fb9820 | 5200 | else if (i.tm.operand_types[mem_op + 1].bitfield.esseg) |
29b0f896 AM |
5201 | { |
5202 | if (i.seg[1] != NULL && i.seg[1] != &es) | |
5203 | { | |
a87af027 | 5204 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
29b0f896 | 5205 | i.tm.name, |
a87af027 JB |
5206 | mem_op + 2, |
5207 | register_prefix); | |
29b0f896 AM |
5208 | return 0; |
5209 | } | |
5210 | } | |
5211 | return 1; | |
5212 | } | |
5213 | ||
5214 | static int | |
543613e9 | 5215 | process_suffix (void) |
29b0f896 AM |
5216 | { |
5217 | /* If matched instruction specifies an explicit instruction mnemonic | |
5218 | suffix, use it. */ | |
40fb9820 L |
5219 | if (i.tm.opcode_modifier.size16) |
5220 | i.suffix = WORD_MNEM_SUFFIX; | |
5221 | else if (i.tm.opcode_modifier.size32) | |
5222 | i.suffix = LONG_MNEM_SUFFIX; | |
5223 | else if (i.tm.opcode_modifier.size64) | |
5224 | i.suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 AM |
5225 | else if (i.reg_operands) |
5226 | { | |
5227 | /* If there's no instruction mnemonic suffix we try to invent one | |
5228 | based on register operands. */ | |
5229 | if (!i.suffix) | |
5230 | { | |
5231 | /* We take i.suffix from the last register operand specified, | |
5232 | Destination register type is more significant than source | |
381d071f L |
5233 | register type. crc32 in SSE4.2 prefers source register |
5234 | type. */ | |
5235 | if (i.tm.base_opcode == 0xf20f38f1) | |
5236 | { | |
40fb9820 L |
5237 | if (i.types[0].bitfield.reg16) |
5238 | i.suffix = WORD_MNEM_SUFFIX; | |
5239 | else if (i.types[0].bitfield.reg32) | |
5240 | i.suffix = LONG_MNEM_SUFFIX; | |
5241 | else if (i.types[0].bitfield.reg64) | |
5242 | i.suffix = QWORD_MNEM_SUFFIX; | |
381d071f | 5243 | } |
9344ff29 | 5244 | else if (i.tm.base_opcode == 0xf20f38f0) |
20592a94 | 5245 | { |
40fb9820 | 5246 | if (i.types[0].bitfield.reg8) |
20592a94 L |
5247 | i.suffix = BYTE_MNEM_SUFFIX; |
5248 | } | |
381d071f L |
5249 | |
5250 | if (!i.suffix) | |
5251 | { | |
5252 | int op; | |
5253 | ||
20592a94 L |
5254 | if (i.tm.base_opcode == 0xf20f38f1 |
5255 | || i.tm.base_opcode == 0xf20f38f0) | |
5256 | { | |
5257 | /* We have to know the operand size for crc32. */ | |
5258 | as_bad (_("ambiguous memory operand size for `%s`"), | |
5259 | i.tm.name); | |
5260 | return 0; | |
5261 | } | |
5262 | ||
381d071f | 5263 | for (op = i.operands; --op >= 0;) |
40fb9820 | 5264 | if (!i.tm.operand_types[op].bitfield.inoutportreg) |
381d071f | 5265 | { |
40fb9820 L |
5266 | if (i.types[op].bitfield.reg8) |
5267 | { | |
5268 | i.suffix = BYTE_MNEM_SUFFIX; | |
5269 | break; | |
5270 | } | |
5271 | else if (i.types[op].bitfield.reg16) | |
5272 | { | |
5273 | i.suffix = WORD_MNEM_SUFFIX; | |
5274 | break; | |
5275 | } | |
5276 | else if (i.types[op].bitfield.reg32) | |
5277 | { | |
5278 | i.suffix = LONG_MNEM_SUFFIX; | |
5279 | break; | |
5280 | } | |
5281 | else if (i.types[op].bitfield.reg64) | |
5282 | { | |
5283 | i.suffix = QWORD_MNEM_SUFFIX; | |
5284 | break; | |
5285 | } | |
381d071f L |
5286 | } |
5287 | } | |
29b0f896 AM |
5288 | } |
5289 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
5290 | { | |
2eb952a4 L |
5291 | if (intel_syntax |
5292 | && i.tm.opcode_modifier.ignoresize | |
5293 | && i.tm.opcode_modifier.no_bsuf) | |
5294 | i.suffix = 0; | |
5295 | else if (!check_byte_reg ()) | |
29b0f896 AM |
5296 | return 0; |
5297 | } | |
5298 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
5299 | { | |
2eb952a4 L |
5300 | if (intel_syntax |
5301 | && i.tm.opcode_modifier.ignoresize | |
5302 | && i.tm.opcode_modifier.no_lsuf) | |
5303 | i.suffix = 0; | |
5304 | else if (!check_long_reg ()) | |
29b0f896 AM |
5305 | return 0; |
5306 | } | |
5307 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
5308 | { | |
955e1e6a L |
5309 | if (intel_syntax |
5310 | && i.tm.opcode_modifier.ignoresize | |
5311 | && i.tm.opcode_modifier.no_qsuf) | |
5312 | i.suffix = 0; | |
5313 | else if (!check_qword_reg ()) | |
29b0f896 AM |
5314 | return 0; |
5315 | } | |
5316 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
5317 | { | |
2eb952a4 L |
5318 | if (intel_syntax |
5319 | && i.tm.opcode_modifier.ignoresize | |
5320 | && i.tm.opcode_modifier.no_wsuf) | |
5321 | i.suffix = 0; | |
5322 | else if (!check_word_reg ()) | |
29b0f896 AM |
5323 | return 0; |
5324 | } | |
c0f3af97 | 5325 | else if (i.suffix == XMMWORD_MNEM_SUFFIX |
43234a1e L |
5326 | || i.suffix == YMMWORD_MNEM_SUFFIX |
5327 | || i.suffix == ZMMWORD_MNEM_SUFFIX) | |
582d5edd | 5328 | { |
43234a1e | 5329 | /* Skip if the instruction has x/y/z suffix. match_template |
582d5edd L |
5330 | should check if it is a valid suffix. */ |
5331 | } | |
40fb9820 | 5332 | else if (intel_syntax && i.tm.opcode_modifier.ignoresize) |
29b0f896 AM |
5333 | /* Do nothing if the instruction is going to ignore the prefix. */ |
5334 | ; | |
5335 | else | |
5336 | abort (); | |
5337 | } | |
40fb9820 | 5338 | else if (i.tm.opcode_modifier.defaultsize |
9306ca4a JB |
5339 | && !i.suffix |
5340 | /* exclude fldenv/frstor/fsave/fstenv */ | |
40fb9820 | 5341 | && i.tm.opcode_modifier.no_ssuf) |
29b0f896 AM |
5342 | { |
5343 | i.suffix = stackop_size; | |
5344 | } | |
9306ca4a JB |
5345 | else if (intel_syntax |
5346 | && !i.suffix | |
40fb9820 L |
5347 | && (i.tm.operand_types[0].bitfield.jumpabsolute |
5348 | || i.tm.opcode_modifier.jumpbyte | |
5349 | || i.tm.opcode_modifier.jumpintersegment | |
64e74474 AM |
5350 | || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */ |
5351 | && i.tm.extension_opcode <= 3))) | |
9306ca4a JB |
5352 | { |
5353 | switch (flag_code) | |
5354 | { | |
5355 | case CODE_64BIT: | |
40fb9820 | 5356 | if (!i.tm.opcode_modifier.no_qsuf) |
9306ca4a JB |
5357 | { |
5358 | i.suffix = QWORD_MNEM_SUFFIX; | |
5359 | break; | |
5360 | } | |
5361 | case CODE_32BIT: | |
40fb9820 | 5362 | if (!i.tm.opcode_modifier.no_lsuf) |
9306ca4a JB |
5363 | i.suffix = LONG_MNEM_SUFFIX; |
5364 | break; | |
5365 | case CODE_16BIT: | |
40fb9820 | 5366 | if (!i.tm.opcode_modifier.no_wsuf) |
9306ca4a JB |
5367 | i.suffix = WORD_MNEM_SUFFIX; |
5368 | break; | |
5369 | } | |
5370 | } | |
252b5132 | 5371 | |
9306ca4a | 5372 | if (!i.suffix) |
29b0f896 | 5373 | { |
9306ca4a JB |
5374 | if (!intel_syntax) |
5375 | { | |
40fb9820 | 5376 | if (i.tm.opcode_modifier.w) |
9306ca4a | 5377 | { |
4eed87de AM |
5378 | as_bad (_("no instruction mnemonic suffix given and " |
5379 | "no register operands; can't size instruction")); | |
9306ca4a JB |
5380 | return 0; |
5381 | } | |
5382 | } | |
5383 | else | |
5384 | { | |
40fb9820 | 5385 | unsigned int suffixes; |
7ab9ffdd | 5386 | |
40fb9820 L |
5387 | suffixes = !i.tm.opcode_modifier.no_bsuf; |
5388 | if (!i.tm.opcode_modifier.no_wsuf) | |
5389 | suffixes |= 1 << 1; | |
5390 | if (!i.tm.opcode_modifier.no_lsuf) | |
5391 | suffixes |= 1 << 2; | |
fc4adea1 | 5392 | if (!i.tm.opcode_modifier.no_ldsuf) |
40fb9820 L |
5393 | suffixes |= 1 << 3; |
5394 | if (!i.tm.opcode_modifier.no_ssuf) | |
5395 | suffixes |= 1 << 4; | |
5396 | if (!i.tm.opcode_modifier.no_qsuf) | |
5397 | suffixes |= 1 << 5; | |
5398 | ||
5399 | /* There are more than suffix matches. */ | |
5400 | if (i.tm.opcode_modifier.w | |
9306ca4a | 5401 | || ((suffixes & (suffixes - 1)) |
40fb9820 L |
5402 | && !i.tm.opcode_modifier.defaultsize |
5403 | && !i.tm.opcode_modifier.ignoresize)) | |
9306ca4a JB |
5404 | { |
5405 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); | |
5406 | return 0; | |
5407 | } | |
5408 | } | |
29b0f896 | 5409 | } |
252b5132 | 5410 | |
9306ca4a JB |
5411 | /* Change the opcode based on the operand size given by i.suffix; |
5412 | We don't need to change things for byte insns. */ | |
5413 | ||
582d5edd L |
5414 | if (i.suffix |
5415 | && i.suffix != BYTE_MNEM_SUFFIX | |
c0f3af97 | 5416 | && i.suffix != XMMWORD_MNEM_SUFFIX |
43234a1e L |
5417 | && i.suffix != YMMWORD_MNEM_SUFFIX |
5418 | && i.suffix != ZMMWORD_MNEM_SUFFIX) | |
29b0f896 AM |
5419 | { |
5420 | /* It's not a byte, select word/dword operation. */ | |
40fb9820 | 5421 | if (i.tm.opcode_modifier.w) |
29b0f896 | 5422 | { |
40fb9820 | 5423 | if (i.tm.opcode_modifier.shortform) |
29b0f896 AM |
5424 | i.tm.base_opcode |= 8; |
5425 | else | |
5426 | i.tm.base_opcode |= 1; | |
5427 | } | |
0f3f3d8b | 5428 | |
29b0f896 AM |
5429 | /* Now select between word & dword operations via the operand |
5430 | size prefix, except for instructions that will ignore this | |
5431 | prefix anyway. */ | |
ca61edf2 | 5432 | if (i.tm.opcode_modifier.addrprefixop0) |
cb712a9e | 5433 | { |
ca61edf2 L |
5434 | /* The address size override prefix changes the size of the |
5435 | first operand. */ | |
40fb9820 L |
5436 | if ((flag_code == CODE_32BIT |
5437 | && i.op->regs[0].reg_type.bitfield.reg16) | |
5438 | || (flag_code != CODE_32BIT | |
5439 | && i.op->regs[0].reg_type.bitfield.reg32)) | |
cb712a9e L |
5440 | if (!add_prefix (ADDR_PREFIX_OPCODE)) |
5441 | return 0; | |
5442 | } | |
5443 | else if (i.suffix != QWORD_MNEM_SUFFIX | |
5444 | && i.suffix != LONG_DOUBLE_MNEM_SUFFIX | |
40fb9820 L |
5445 | && !i.tm.opcode_modifier.ignoresize |
5446 | && !i.tm.opcode_modifier.floatmf | |
cb712a9e L |
5447 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) |
5448 | || (flag_code == CODE_64BIT | |
40fb9820 | 5449 | && i.tm.opcode_modifier.jumpbyte))) |
24eab124 AM |
5450 | { |
5451 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
543613e9 | 5452 | |
40fb9820 | 5453 | if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */ |
29b0f896 | 5454 | prefix = ADDR_PREFIX_OPCODE; |
252b5132 | 5455 | |
29b0f896 AM |
5456 | if (!add_prefix (prefix)) |
5457 | return 0; | |
24eab124 | 5458 | } |
252b5132 | 5459 | |
29b0f896 AM |
5460 | /* Set mode64 for an operand. */ |
5461 | if (i.suffix == QWORD_MNEM_SUFFIX | |
9146926a | 5462 | && flag_code == CODE_64BIT |
40fb9820 | 5463 | && !i.tm.opcode_modifier.norex64) |
46e883c5 L |
5464 | { |
5465 | /* Special case for xchg %rax,%rax. It is NOP and doesn't | |
d9a5e5e5 L |
5466 | need rex64. cmpxchg8b is also a special case. */ |
5467 | if (! (i.operands == 2 | |
5468 | && i.tm.base_opcode == 0x90 | |
5469 | && i.tm.extension_opcode == None | |
0dfbf9d7 L |
5470 | && operand_type_equal (&i.types [0], &acc64) |
5471 | && operand_type_equal (&i.types [1], &acc64)) | |
d9a5e5e5 L |
5472 | && ! (i.operands == 1 |
5473 | && i.tm.base_opcode == 0xfc7 | |
5474 | && i.tm.extension_opcode == 1 | |
40fb9820 L |
5475 | && !operand_type_check (i.types [0], reg) |
5476 | && operand_type_check (i.types [0], anymem))) | |
f6bee062 | 5477 | i.rex |= REX_W; |
46e883c5 | 5478 | } |
3e73aa7c | 5479 | |
29b0f896 AM |
5480 | /* Size floating point instruction. */ |
5481 | if (i.suffix == LONG_MNEM_SUFFIX) | |
40fb9820 | 5482 | if (i.tm.opcode_modifier.floatmf) |
543613e9 | 5483 | i.tm.base_opcode ^= 4; |
29b0f896 | 5484 | } |
7ecd2f8b | 5485 | |
29b0f896 AM |
5486 | return 1; |
5487 | } | |
3e73aa7c | 5488 | |
29b0f896 | 5489 | static int |
543613e9 | 5490 | check_byte_reg (void) |
29b0f896 AM |
5491 | { |
5492 | int op; | |
543613e9 | 5493 | |
29b0f896 AM |
5494 | for (op = i.operands; --op >= 0;) |
5495 | { | |
5496 | /* If this is an eight bit register, it's OK. If it's the 16 or | |
5497 | 32 bit version of an eight bit register, we will just use the | |
5498 | low portion, and that's OK too. */ | |
40fb9820 | 5499 | if (i.types[op].bitfield.reg8) |
29b0f896 AM |
5500 | continue; |
5501 | ||
5a819eb9 JB |
5502 | /* I/O port address operands are OK too. */ |
5503 | if (i.tm.operand_types[op].bitfield.inoutportreg) | |
5504 | continue; | |
5505 | ||
9344ff29 L |
5506 | /* crc32 doesn't generate this warning. */ |
5507 | if (i.tm.base_opcode == 0xf20f38f0) | |
5508 | continue; | |
5509 | ||
40fb9820 L |
5510 | if ((i.types[op].bitfield.reg16 |
5511 | || i.types[op].bitfield.reg32 | |
5512 | || i.types[op].bitfield.reg64) | |
5a819eb9 JB |
5513 | && i.op[op].regs->reg_num < 4 |
5514 | /* Prohibit these changes in 64bit mode, since the lowering | |
5515 | would be more complicated. */ | |
5516 | && flag_code != CODE_64BIT) | |
29b0f896 | 5517 | { |
29b0f896 | 5518 | #if REGISTER_WARNINGS |
5a819eb9 | 5519 | if (!quiet_warnings) |
a540244d L |
5520 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
5521 | register_prefix, | |
40fb9820 | 5522 | (i.op[op].regs + (i.types[op].bitfield.reg16 |
29b0f896 AM |
5523 | ? REGNAM_AL - REGNAM_AX |
5524 | : REGNAM_AL - REGNAM_EAX))->reg_name, | |
a540244d | 5525 | register_prefix, |
29b0f896 AM |
5526 | i.op[op].regs->reg_name, |
5527 | i.suffix); | |
5528 | #endif | |
5529 | continue; | |
5530 | } | |
5531 | /* Any other register is bad. */ | |
40fb9820 L |
5532 | if (i.types[op].bitfield.reg16 |
5533 | || i.types[op].bitfield.reg32 | |
5534 | || i.types[op].bitfield.reg64 | |
5535 | || i.types[op].bitfield.regmmx | |
5536 | || i.types[op].bitfield.regxmm | |
c0f3af97 | 5537 | || i.types[op].bitfield.regymm |
43234a1e | 5538 | || i.types[op].bitfield.regzmm |
40fb9820 L |
5539 | || i.types[op].bitfield.sreg2 |
5540 | || i.types[op].bitfield.sreg3 | |
5541 | || i.types[op].bitfield.control | |
5542 | || i.types[op].bitfield.debug | |
5543 | || i.types[op].bitfield.test | |
5544 | || i.types[op].bitfield.floatreg | |
5545 | || i.types[op].bitfield.floatacc) | |
29b0f896 | 5546 | { |
a540244d L |
5547 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
5548 | register_prefix, | |
29b0f896 AM |
5549 | i.op[op].regs->reg_name, |
5550 | i.tm.name, | |
5551 | i.suffix); | |
5552 | return 0; | |
5553 | } | |
5554 | } | |
5555 | return 1; | |
5556 | } | |
5557 | ||
5558 | static int | |
e3bb37b5 | 5559 | check_long_reg (void) |
29b0f896 AM |
5560 | { |
5561 | int op; | |
5562 | ||
5563 | for (op = i.operands; --op >= 0;) | |
5564 | /* Reject eight bit registers, except where the template requires | |
5565 | them. (eg. movzb) */ | |
40fb9820 L |
5566 | if (i.types[op].bitfield.reg8 |
5567 | && (i.tm.operand_types[op].bitfield.reg16 | |
5568 | || i.tm.operand_types[op].bitfield.reg32 | |
5569 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 | 5570 | { |
a540244d L |
5571 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
5572 | register_prefix, | |
29b0f896 AM |
5573 | i.op[op].regs->reg_name, |
5574 | i.tm.name, | |
5575 | i.suffix); | |
5576 | return 0; | |
5577 | } | |
e4630f71 | 5578 | /* Warn if the e prefix on a general reg is missing. */ |
29b0f896 | 5579 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
40fb9820 L |
5580 | && i.types[op].bitfield.reg16 |
5581 | && (i.tm.operand_types[op].bitfield.reg32 | |
5582 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 AM |
5583 | { |
5584 | /* Prohibit these changes in the 64bit mode, since the | |
5585 | lowering is more complicated. */ | |
5586 | if (flag_code == CODE_64BIT) | |
252b5132 | 5587 | { |
2b5d6a91 | 5588 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
2ca3ace5 | 5589 | register_prefix, i.op[op].regs->reg_name, |
29b0f896 AM |
5590 | i.suffix); |
5591 | return 0; | |
252b5132 | 5592 | } |
29b0f896 | 5593 | #if REGISTER_WARNINGS |
cecf1424 JB |
5594 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
5595 | register_prefix, | |
5596 | (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name, | |
5597 | register_prefix, i.op[op].regs->reg_name, i.suffix); | |
29b0f896 | 5598 | #endif |
252b5132 | 5599 | } |
e4630f71 | 5600 | /* Warn if the r prefix on a general reg is present. */ |
40fb9820 L |
5601 | else if (i.types[op].bitfield.reg64 |
5602 | && (i.tm.operand_types[op].bitfield.reg32 | |
5603 | || i.tm.operand_types[op].bitfield.acc)) | |
252b5132 | 5604 | { |
34828aad | 5605 | if (intel_syntax |
ca61edf2 | 5606 | && i.tm.opcode_modifier.toqword |
40fb9820 | 5607 | && !i.types[0].bitfield.regxmm) |
34828aad | 5608 | { |
ca61edf2 | 5609 | /* Convert to QWORD. We want REX byte. */ |
34828aad L |
5610 | i.suffix = QWORD_MNEM_SUFFIX; |
5611 | } | |
5612 | else | |
5613 | { | |
2b5d6a91 | 5614 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
5615 | register_prefix, i.op[op].regs->reg_name, |
5616 | i.suffix); | |
5617 | return 0; | |
5618 | } | |
29b0f896 AM |
5619 | } |
5620 | return 1; | |
5621 | } | |
252b5132 | 5622 | |
29b0f896 | 5623 | static int |
e3bb37b5 | 5624 | check_qword_reg (void) |
29b0f896 AM |
5625 | { |
5626 | int op; | |
252b5132 | 5627 | |
29b0f896 AM |
5628 | for (op = i.operands; --op >= 0; ) |
5629 | /* Reject eight bit registers, except where the template requires | |
5630 | them. (eg. movzb) */ | |
40fb9820 L |
5631 | if (i.types[op].bitfield.reg8 |
5632 | && (i.tm.operand_types[op].bitfield.reg16 | |
5633 | || i.tm.operand_types[op].bitfield.reg32 | |
5634 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 | 5635 | { |
a540244d L |
5636 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
5637 | register_prefix, | |
29b0f896 AM |
5638 | i.op[op].regs->reg_name, |
5639 | i.tm.name, | |
5640 | i.suffix); | |
5641 | return 0; | |
5642 | } | |
e4630f71 | 5643 | /* Warn if the r prefix on a general reg is missing. */ |
40fb9820 L |
5644 | else if ((i.types[op].bitfield.reg16 |
5645 | || i.types[op].bitfield.reg32) | |
5646 | && (i.tm.operand_types[op].bitfield.reg32 | |
5647 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 AM |
5648 | { |
5649 | /* Prohibit these changes in the 64bit mode, since the | |
5650 | lowering is more complicated. */ | |
34828aad | 5651 | if (intel_syntax |
ca61edf2 | 5652 | && i.tm.opcode_modifier.todword |
40fb9820 | 5653 | && !i.types[0].bitfield.regxmm) |
34828aad | 5654 | { |
ca61edf2 | 5655 | /* Convert to DWORD. We don't want REX byte. */ |
34828aad L |
5656 | i.suffix = LONG_MNEM_SUFFIX; |
5657 | } | |
5658 | else | |
5659 | { | |
2b5d6a91 | 5660 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
5661 | register_prefix, i.op[op].regs->reg_name, |
5662 | i.suffix); | |
5663 | return 0; | |
5664 | } | |
252b5132 | 5665 | } |
29b0f896 AM |
5666 | return 1; |
5667 | } | |
252b5132 | 5668 | |
29b0f896 | 5669 | static int |
e3bb37b5 | 5670 | check_word_reg (void) |
29b0f896 AM |
5671 | { |
5672 | int op; | |
5673 | for (op = i.operands; --op >= 0;) | |
5674 | /* Reject eight bit registers, except where the template requires | |
5675 | them. (eg. movzb) */ | |
40fb9820 L |
5676 | if (i.types[op].bitfield.reg8 |
5677 | && (i.tm.operand_types[op].bitfield.reg16 | |
5678 | || i.tm.operand_types[op].bitfield.reg32 | |
5679 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 | 5680 | { |
a540244d L |
5681 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
5682 | register_prefix, | |
29b0f896 AM |
5683 | i.op[op].regs->reg_name, |
5684 | i.tm.name, | |
5685 | i.suffix); | |
5686 | return 0; | |
5687 | } | |
e4630f71 | 5688 | /* Warn if the e or r prefix on a general reg is present. */ |
29b0f896 | 5689 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
e4630f71 JB |
5690 | && (i.types[op].bitfield.reg32 |
5691 | || i.types[op].bitfield.reg64) | |
40fb9820 L |
5692 | && (i.tm.operand_types[op].bitfield.reg16 |
5693 | || i.tm.operand_types[op].bitfield.acc)) | |
252b5132 | 5694 | { |
29b0f896 AM |
5695 | /* Prohibit these changes in the 64bit mode, since the |
5696 | lowering is more complicated. */ | |
5697 | if (flag_code == CODE_64BIT) | |
252b5132 | 5698 | { |
2b5d6a91 | 5699 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
2ca3ace5 | 5700 | register_prefix, i.op[op].regs->reg_name, |
29b0f896 AM |
5701 | i.suffix); |
5702 | return 0; | |
252b5132 | 5703 | } |
29b0f896 | 5704 | #if REGISTER_WARNINGS |
cecf1424 JB |
5705 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
5706 | register_prefix, | |
5707 | (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name, | |
5708 | register_prefix, i.op[op].regs->reg_name, i.suffix); | |
29b0f896 AM |
5709 | #endif |
5710 | } | |
5711 | return 1; | |
5712 | } | |
252b5132 | 5713 | |
29b0f896 | 5714 | static int |
40fb9820 | 5715 | update_imm (unsigned int j) |
29b0f896 | 5716 | { |
bc0844ae | 5717 | i386_operand_type overlap = i.types[j]; |
40fb9820 L |
5718 | if ((overlap.bitfield.imm8 |
5719 | || overlap.bitfield.imm8s | |
5720 | || overlap.bitfield.imm16 | |
5721 | || overlap.bitfield.imm32 | |
5722 | || overlap.bitfield.imm32s | |
5723 | || overlap.bitfield.imm64) | |
0dfbf9d7 L |
5724 | && !operand_type_equal (&overlap, &imm8) |
5725 | && !operand_type_equal (&overlap, &imm8s) | |
5726 | && !operand_type_equal (&overlap, &imm16) | |
5727 | && !operand_type_equal (&overlap, &imm32) | |
5728 | && !operand_type_equal (&overlap, &imm32s) | |
5729 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 AM |
5730 | { |
5731 | if (i.suffix) | |
5732 | { | |
40fb9820 L |
5733 | i386_operand_type temp; |
5734 | ||
0dfbf9d7 | 5735 | operand_type_set (&temp, 0); |
7ab9ffdd | 5736 | if (i.suffix == BYTE_MNEM_SUFFIX) |
40fb9820 L |
5737 | { |
5738 | temp.bitfield.imm8 = overlap.bitfield.imm8; | |
5739 | temp.bitfield.imm8s = overlap.bitfield.imm8s; | |
5740 | } | |
5741 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
5742 | temp.bitfield.imm16 = overlap.bitfield.imm16; | |
5743 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
5744 | { | |
5745 | temp.bitfield.imm64 = overlap.bitfield.imm64; | |
5746 | temp.bitfield.imm32s = overlap.bitfield.imm32s; | |
5747 | } | |
5748 | else | |
5749 | temp.bitfield.imm32 = overlap.bitfield.imm32; | |
5750 | overlap = temp; | |
29b0f896 | 5751 | } |
0dfbf9d7 L |
5752 | else if (operand_type_equal (&overlap, &imm16_32_32s) |
5753 | || operand_type_equal (&overlap, &imm16_32) | |
5754 | || operand_type_equal (&overlap, &imm16_32s)) | |
29b0f896 | 5755 | { |
40fb9820 | 5756 | if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
65da13b5 | 5757 | overlap = imm16; |
40fb9820 | 5758 | else |
65da13b5 | 5759 | overlap = imm32s; |
29b0f896 | 5760 | } |
0dfbf9d7 L |
5761 | if (!operand_type_equal (&overlap, &imm8) |
5762 | && !operand_type_equal (&overlap, &imm8s) | |
5763 | && !operand_type_equal (&overlap, &imm16) | |
5764 | && !operand_type_equal (&overlap, &imm32) | |
5765 | && !operand_type_equal (&overlap, &imm32s) | |
5766 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 | 5767 | { |
4eed87de AM |
5768 | as_bad (_("no instruction mnemonic suffix given; " |
5769 | "can't determine immediate size")); | |
29b0f896 AM |
5770 | return 0; |
5771 | } | |
5772 | } | |
40fb9820 | 5773 | i.types[j] = overlap; |
29b0f896 | 5774 | |
40fb9820 L |
5775 | return 1; |
5776 | } | |
5777 | ||
5778 | static int | |
5779 | finalize_imm (void) | |
5780 | { | |
bc0844ae | 5781 | unsigned int j, n; |
29b0f896 | 5782 | |
bc0844ae L |
5783 | /* Update the first 2 immediate operands. */ |
5784 | n = i.operands > 2 ? 2 : i.operands; | |
5785 | if (n) | |
5786 | { | |
5787 | for (j = 0; j < n; j++) | |
5788 | if (update_imm (j) == 0) | |
5789 | return 0; | |
40fb9820 | 5790 | |
bc0844ae L |
5791 | /* The 3rd operand can't be immediate operand. */ |
5792 | gas_assert (operand_type_check (i.types[2], imm) == 0); | |
5793 | } | |
29b0f896 AM |
5794 | |
5795 | return 1; | |
5796 | } | |
5797 | ||
c0f3af97 L |
5798 | static int |
5799 | bad_implicit_operand (int xmm) | |
5800 | { | |
91d6fa6a NC |
5801 | const char *ireg = xmm ? "xmm0" : "ymm0"; |
5802 | ||
c0f3af97 L |
5803 | if (intel_syntax) |
5804 | as_bad (_("the last operand of `%s' must be `%s%s'"), | |
91d6fa6a | 5805 | i.tm.name, register_prefix, ireg); |
c0f3af97 L |
5806 | else |
5807 | as_bad (_("the first operand of `%s' must be `%s%s'"), | |
91d6fa6a | 5808 | i.tm.name, register_prefix, ireg); |
c0f3af97 L |
5809 | return 0; |
5810 | } | |
5811 | ||
29b0f896 | 5812 | static int |
e3bb37b5 | 5813 | process_operands (void) |
29b0f896 AM |
5814 | { |
5815 | /* Default segment register this instruction will use for memory | |
5816 | accesses. 0 means unknown. This is only for optimizing out | |
5817 | unnecessary segment overrides. */ | |
5818 | const seg_entry *default_seg = 0; | |
5819 | ||
2426c15f | 5820 | if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv) |
29b0f896 | 5821 | { |
91d6fa6a NC |
5822 | unsigned int dupl = i.operands; |
5823 | unsigned int dest = dupl - 1; | |
9fcfb3d7 L |
5824 | unsigned int j; |
5825 | ||
c0f3af97 | 5826 | /* The destination must be an xmm register. */ |
9c2799c2 | 5827 | gas_assert (i.reg_operands |
91d6fa6a | 5828 | && MAX_OPERANDS > dupl |
7ab9ffdd | 5829 | && operand_type_equal (&i.types[dest], ®xmm)); |
c0f3af97 L |
5830 | |
5831 | if (i.tm.opcode_modifier.firstxmm0) | |
e2ec9d29 | 5832 | { |
c0f3af97 | 5833 | /* The first operand is implicit and must be xmm0. */ |
9c2799c2 | 5834 | gas_assert (operand_type_equal (&i.types[0], ®xmm)); |
4c692bc7 | 5835 | if (register_number (i.op[0].regs) != 0) |
c0f3af97 L |
5836 | return bad_implicit_operand (1); |
5837 | ||
8cd7925b | 5838 | if (i.tm.opcode_modifier.vexsources == VEX3SOURCES) |
c0f3af97 L |
5839 | { |
5840 | /* Keep xmm0 for instructions with VEX prefix and 3 | |
5841 | sources. */ | |
5842 | goto duplicate; | |
5843 | } | |
e2ec9d29 | 5844 | else |
c0f3af97 L |
5845 | { |
5846 | /* We remove the first xmm0 and keep the number of | |
5847 | operands unchanged, which in fact duplicates the | |
5848 | destination. */ | |
5849 | for (j = 1; j < i.operands; j++) | |
5850 | { | |
5851 | i.op[j - 1] = i.op[j]; | |
5852 | i.types[j - 1] = i.types[j]; | |
5853 | i.tm.operand_types[j - 1] = i.tm.operand_types[j]; | |
5854 | } | |
5855 | } | |
5856 | } | |
5857 | else if (i.tm.opcode_modifier.implicit1stxmm0) | |
7ab9ffdd | 5858 | { |
91d6fa6a | 5859 | gas_assert ((MAX_OPERANDS - 1) > dupl |
8cd7925b L |
5860 | && (i.tm.opcode_modifier.vexsources |
5861 | == VEX3SOURCES)); | |
c0f3af97 L |
5862 | |
5863 | /* Add the implicit xmm0 for instructions with VEX prefix | |
5864 | and 3 sources. */ | |
5865 | for (j = i.operands; j > 0; j--) | |
5866 | { | |
5867 | i.op[j] = i.op[j - 1]; | |
5868 | i.types[j] = i.types[j - 1]; | |
5869 | i.tm.operand_types[j] = i.tm.operand_types[j - 1]; | |
5870 | } | |
5871 | i.op[0].regs | |
5872 | = (const reg_entry *) hash_find (reg_hash, "xmm0"); | |
7ab9ffdd | 5873 | i.types[0] = regxmm; |
c0f3af97 L |
5874 | i.tm.operand_types[0] = regxmm; |
5875 | ||
5876 | i.operands += 2; | |
5877 | i.reg_operands += 2; | |
5878 | i.tm.operands += 2; | |
5879 | ||
91d6fa6a | 5880 | dupl++; |
c0f3af97 | 5881 | dest++; |
91d6fa6a NC |
5882 | i.op[dupl] = i.op[dest]; |
5883 | i.types[dupl] = i.types[dest]; | |
5884 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
e2ec9d29 | 5885 | } |
c0f3af97 L |
5886 | else |
5887 | { | |
5888 | duplicate: | |
5889 | i.operands++; | |
5890 | i.reg_operands++; | |
5891 | i.tm.operands++; | |
5892 | ||
91d6fa6a NC |
5893 | i.op[dupl] = i.op[dest]; |
5894 | i.types[dupl] = i.types[dest]; | |
5895 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
c0f3af97 L |
5896 | } |
5897 | ||
5898 | if (i.tm.opcode_modifier.immext) | |
5899 | process_immext (); | |
5900 | } | |
5901 | else if (i.tm.opcode_modifier.firstxmm0) | |
5902 | { | |
5903 | unsigned int j; | |
5904 | ||
43234a1e | 5905 | /* The first operand is implicit and must be xmm0/ymm0/zmm0. */ |
9c2799c2 | 5906 | gas_assert (i.reg_operands |
7ab9ffdd | 5907 | && (operand_type_equal (&i.types[0], ®xmm) |
43234a1e L |
5908 | || operand_type_equal (&i.types[0], ®ymm) |
5909 | || operand_type_equal (&i.types[0], ®zmm))); | |
4c692bc7 | 5910 | if (register_number (i.op[0].regs) != 0) |
c0f3af97 | 5911 | return bad_implicit_operand (i.types[0].bitfield.regxmm); |
9fcfb3d7 L |
5912 | |
5913 | for (j = 1; j < i.operands; j++) | |
5914 | { | |
5915 | i.op[j - 1] = i.op[j]; | |
5916 | i.types[j - 1] = i.types[j]; | |
5917 | ||
5918 | /* We need to adjust fields in i.tm since they are used by | |
5919 | build_modrm_byte. */ | |
5920 | i.tm.operand_types [j - 1] = i.tm.operand_types [j]; | |
5921 | } | |
5922 | ||
e2ec9d29 L |
5923 | i.operands--; |
5924 | i.reg_operands--; | |
e2ec9d29 L |
5925 | i.tm.operands--; |
5926 | } | |
5927 | else if (i.tm.opcode_modifier.regkludge) | |
5928 | { | |
5929 | /* The imul $imm, %reg instruction is converted into | |
5930 | imul $imm, %reg, %reg, and the clr %reg instruction | |
5931 | is converted into xor %reg, %reg. */ | |
5932 | ||
5933 | unsigned int first_reg_op; | |
5934 | ||
5935 | if (operand_type_check (i.types[0], reg)) | |
5936 | first_reg_op = 0; | |
5937 | else | |
5938 | first_reg_op = 1; | |
5939 | /* Pretend we saw the extra register operand. */ | |
9c2799c2 | 5940 | gas_assert (i.reg_operands == 1 |
7ab9ffdd | 5941 | && i.op[first_reg_op + 1].regs == 0); |
e2ec9d29 L |
5942 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; |
5943 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
5944 | i.operands++; | |
5945 | i.reg_operands++; | |
29b0f896 AM |
5946 | } |
5947 | ||
40fb9820 | 5948 | if (i.tm.opcode_modifier.shortform) |
29b0f896 | 5949 | { |
40fb9820 L |
5950 | if (i.types[0].bitfield.sreg2 |
5951 | || i.types[0].bitfield.sreg3) | |
29b0f896 | 5952 | { |
4eed87de AM |
5953 | if (i.tm.base_opcode == POP_SEG_SHORT |
5954 | && i.op[0].regs->reg_num == 1) | |
29b0f896 | 5955 | { |
a87af027 | 5956 | as_bad (_("you can't `pop %scs'"), register_prefix); |
4eed87de | 5957 | return 0; |
29b0f896 | 5958 | } |
4eed87de AM |
5959 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); |
5960 | if ((i.op[0].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 5961 | i.rex |= REX_B; |
4eed87de AM |
5962 | } |
5963 | else | |
5964 | { | |
7ab9ffdd | 5965 | /* The register or float register operand is in operand |
85f10a01 | 5966 | 0 or 1. */ |
40fb9820 | 5967 | unsigned int op; |
7ab9ffdd L |
5968 | |
5969 | if (i.types[0].bitfield.floatreg | |
5970 | || operand_type_check (i.types[0], reg)) | |
5971 | op = 0; | |
5972 | else | |
5973 | op = 1; | |
4eed87de AM |
5974 | /* Register goes in low 3 bits of opcode. */ |
5975 | i.tm.base_opcode |= i.op[op].regs->reg_num; | |
5976 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 5977 | i.rex |= REX_B; |
40fb9820 | 5978 | if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 | 5979 | { |
4eed87de AM |
5980 | /* Warn about some common errors, but press on regardless. |
5981 | The first case can be generated by gcc (<= 2.8.1). */ | |
5982 | if (i.operands == 2) | |
5983 | { | |
5984 | /* Reversed arguments on faddp, fsubp, etc. */ | |
a540244d | 5985 | as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, |
d8a1b51e JB |
5986 | register_prefix, i.op[!intel_syntax].regs->reg_name, |
5987 | register_prefix, i.op[intel_syntax].regs->reg_name); | |
4eed87de AM |
5988 | } |
5989 | else | |
5990 | { | |
5991 | /* Extraneous `l' suffix on fp insn. */ | |
a540244d L |
5992 | as_warn (_("translating to `%s %s%s'"), i.tm.name, |
5993 | register_prefix, i.op[0].regs->reg_name); | |
4eed87de | 5994 | } |
29b0f896 AM |
5995 | } |
5996 | } | |
5997 | } | |
40fb9820 | 5998 | else if (i.tm.opcode_modifier.modrm) |
29b0f896 AM |
5999 | { |
6000 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
52271982 AM |
6001 | must be put into the modrm byte). Now, we make the modrm and |
6002 | index base bytes based on all the info we've collected. */ | |
29b0f896 AM |
6003 | |
6004 | default_seg = build_modrm_byte (); | |
6005 | } | |
8a2ed489 | 6006 | else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32) |
29b0f896 AM |
6007 | { |
6008 | default_seg = &ds; | |
6009 | } | |
40fb9820 | 6010 | else if (i.tm.opcode_modifier.isstring) |
29b0f896 AM |
6011 | { |
6012 | /* For the string instructions that allow a segment override | |
6013 | on one of their operands, the default segment is ds. */ | |
6014 | default_seg = &ds; | |
6015 | } | |
6016 | ||
75178d9d L |
6017 | if (i.tm.base_opcode == 0x8d /* lea */ |
6018 | && i.seg[0] | |
6019 | && !quiet_warnings) | |
30123838 | 6020 | as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); |
52271982 AM |
6021 | |
6022 | /* If a segment was explicitly specified, and the specified segment | |
6023 | is not the default, use an opcode prefix to select it. If we | |
6024 | never figured out what the default segment is, then default_seg | |
6025 | will be zero at this point, and the specified segment prefix will | |
6026 | always be used. */ | |
29b0f896 AM |
6027 | if ((i.seg[0]) && (i.seg[0] != default_seg)) |
6028 | { | |
6029 | if (!add_prefix (i.seg[0]->seg_prefix)) | |
6030 | return 0; | |
6031 | } | |
6032 | return 1; | |
6033 | } | |
6034 | ||
6035 | static const seg_entry * | |
e3bb37b5 | 6036 | build_modrm_byte (void) |
29b0f896 AM |
6037 | { |
6038 | const seg_entry *default_seg = 0; | |
c0f3af97 | 6039 | unsigned int source, dest; |
8cd7925b | 6040 | int vex_3_sources; |
c0f3af97 L |
6041 | |
6042 | /* The first operand of instructions with VEX prefix and 3 sources | |
6043 | must be VEX_Imm4. */ | |
8cd7925b | 6044 | vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES; |
c0f3af97 L |
6045 | if (vex_3_sources) |
6046 | { | |
91d6fa6a | 6047 | unsigned int nds, reg_slot; |
4c2c6516 | 6048 | expressionS *exp; |
c0f3af97 | 6049 | |
922d8de8 | 6050 | if (i.tm.opcode_modifier.veximmext |
a683cc34 SP |
6051 | && i.tm.opcode_modifier.immext) |
6052 | { | |
6053 | dest = i.operands - 2; | |
6054 | gas_assert (dest == 3); | |
6055 | } | |
922d8de8 | 6056 | else |
a683cc34 | 6057 | dest = i.operands - 1; |
c0f3af97 | 6058 | nds = dest - 1; |
922d8de8 | 6059 | |
a683cc34 SP |
6060 | /* There are 2 kinds of instructions: |
6061 | 1. 5 operands: 4 register operands or 3 register operands | |
6062 | plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and | |
43234a1e L |
6063 | VexW0 or VexW1. The destination must be either XMM, YMM or |
6064 | ZMM register. | |
a683cc34 SP |
6065 | 2. 4 operands: 4 register operands or 3 register operands |
6066 | plus 1 memory operand, VexXDS, and VexImmExt */ | |
922d8de8 | 6067 | gas_assert ((i.reg_operands == 4 |
a683cc34 SP |
6068 | || (i.reg_operands == 3 && i.mem_operands == 1)) |
6069 | && i.tm.opcode_modifier.vexvvvv == VEXXDS | |
6070 | && (i.tm.opcode_modifier.veximmext | |
6071 | || (i.imm_operands == 1 | |
6072 | && i.types[0].bitfield.vec_imm4 | |
6073 | && (i.tm.opcode_modifier.vexw == VEXW0 | |
6074 | || i.tm.opcode_modifier.vexw == VEXW1) | |
6075 | && (operand_type_equal (&i.tm.operand_types[dest], ®xmm) | |
43234a1e L |
6076 | || operand_type_equal (&i.tm.operand_types[dest], ®ymm) |
6077 | || operand_type_equal (&i.tm.operand_types[dest], ®zmm))))); | |
a683cc34 SP |
6078 | |
6079 | if (i.imm_operands == 0) | |
6080 | { | |
6081 | /* When there is no immediate operand, generate an 8bit | |
6082 | immediate operand to encode the first operand. */ | |
6083 | exp = &im_expressions[i.imm_operands++]; | |
6084 | i.op[i.operands].imms = exp; | |
6085 | i.types[i.operands] = imm8; | |
6086 | i.operands++; | |
6087 | /* If VexW1 is set, the first operand is the source and | |
6088 | the second operand is encoded in the immediate operand. */ | |
6089 | if (i.tm.opcode_modifier.vexw == VEXW1) | |
6090 | { | |
6091 | source = 0; | |
6092 | reg_slot = 1; | |
6093 | } | |
6094 | else | |
6095 | { | |
6096 | source = 1; | |
6097 | reg_slot = 0; | |
6098 | } | |
6099 | ||
6100 | /* FMA swaps REG and NDS. */ | |
6101 | if (i.tm.cpu_flags.bitfield.cpufma) | |
6102 | { | |
6103 | unsigned int tmp; | |
6104 | tmp = reg_slot; | |
6105 | reg_slot = nds; | |
6106 | nds = tmp; | |
6107 | } | |
6108 | ||
24981e7b L |
6109 | gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot], |
6110 | ®xmm) | |
a683cc34 | 6111 | || operand_type_equal (&i.tm.operand_types[reg_slot], |
43234a1e L |
6112 | ®ymm) |
6113 | || operand_type_equal (&i.tm.operand_types[reg_slot], | |
6114 | ®zmm)); | |
a683cc34 | 6115 | exp->X_op = O_constant; |
4c692bc7 | 6116 | exp->X_add_number = register_number (i.op[reg_slot].regs) << 4; |
43234a1e L |
6117 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
6118 | } | |
922d8de8 | 6119 | else |
a683cc34 SP |
6120 | { |
6121 | unsigned int imm_slot; | |
6122 | ||
6123 | if (i.tm.opcode_modifier.vexw == VEXW0) | |
6124 | { | |
6125 | /* If VexW0 is set, the third operand is the source and | |
6126 | the second operand is encoded in the immediate | |
6127 | operand. */ | |
6128 | source = 2; | |
6129 | reg_slot = 1; | |
6130 | } | |
6131 | else | |
6132 | { | |
6133 | /* VexW1 is set, the second operand is the source and | |
6134 | the third operand is encoded in the immediate | |
6135 | operand. */ | |
6136 | source = 1; | |
6137 | reg_slot = 2; | |
6138 | } | |
6139 | ||
6140 | if (i.tm.opcode_modifier.immext) | |
6141 | { | |
6142 | /* When ImmExt is set, the immdiate byte is the last | |
6143 | operand. */ | |
6144 | imm_slot = i.operands - 1; | |
6145 | source--; | |
6146 | reg_slot--; | |
6147 | } | |
6148 | else | |
6149 | { | |
6150 | imm_slot = 0; | |
6151 | ||
6152 | /* Turn on Imm8 so that output_imm will generate it. */ | |
6153 | i.types[imm_slot].bitfield.imm8 = 1; | |
6154 | } | |
6155 | ||
24981e7b L |
6156 | gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot], |
6157 | ®xmm) | |
6158 | || operand_type_equal (&i.tm.operand_types[reg_slot], | |
43234a1e L |
6159 | ®ymm) |
6160 | || operand_type_equal (&i.tm.operand_types[reg_slot], | |
6161 | ®zmm)); | |
a683cc34 | 6162 | i.op[imm_slot].imms->X_add_number |
4c692bc7 | 6163 | |= register_number (i.op[reg_slot].regs) << 4; |
43234a1e | 6164 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
a683cc34 SP |
6165 | } |
6166 | ||
6167 | gas_assert (operand_type_equal (&i.tm.operand_types[nds], ®xmm) | |
6168 | || operand_type_equal (&i.tm.operand_types[nds], | |
43234a1e L |
6169 | ®ymm) |
6170 | || operand_type_equal (&i.tm.operand_types[nds], | |
6171 | ®zmm)); | |
dae39acc | 6172 | i.vex.register_specifier = i.op[nds].regs; |
c0f3af97 L |
6173 | } |
6174 | else | |
6175 | source = dest = 0; | |
29b0f896 AM |
6176 | |
6177 | /* i.reg_operands MUST be the number of real register operands; | |
c0f3af97 L |
6178 | implicit registers do not count. If there are 3 register |
6179 | operands, it must be a instruction with VexNDS. For a | |
6180 | instruction with VexNDD, the destination register is encoded | |
6181 | in VEX prefix. If there are 4 register operands, it must be | |
6182 | a instruction with VEX prefix and 3 sources. */ | |
7ab9ffdd L |
6183 | if (i.mem_operands == 0 |
6184 | && ((i.reg_operands == 2 | |
2426c15f | 6185 | && i.tm.opcode_modifier.vexvvvv <= VEXXDS) |
7ab9ffdd | 6186 | || (i.reg_operands == 3 |
2426c15f | 6187 | && i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd | 6188 | || (i.reg_operands == 4 && vex_3_sources))) |
29b0f896 | 6189 | { |
cab737b9 L |
6190 | switch (i.operands) |
6191 | { | |
6192 | case 2: | |
6193 | source = 0; | |
6194 | break; | |
6195 | case 3: | |
c81128dc L |
6196 | /* When there are 3 operands, one of them may be immediate, |
6197 | which may be the first or the last operand. Otherwise, | |
c0f3af97 L |
6198 | the first operand must be shift count register (cl) or it |
6199 | is an instruction with VexNDS. */ | |
9c2799c2 | 6200 | gas_assert (i.imm_operands == 1 |
7ab9ffdd | 6201 | || (i.imm_operands == 0 |
2426c15f | 6202 | && (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd | 6203 | || i.types[0].bitfield.shiftcount))); |
40fb9820 L |
6204 | if (operand_type_check (i.types[0], imm) |
6205 | || i.types[0].bitfield.shiftcount) | |
6206 | source = 1; | |
6207 | else | |
6208 | source = 0; | |
cab737b9 L |
6209 | break; |
6210 | case 4: | |
368d64cc L |
6211 | /* When there are 4 operands, the first two must be 8bit |
6212 | immediate operands. The source operand will be the 3rd | |
c0f3af97 L |
6213 | one. |
6214 | ||
6215 | For instructions with VexNDS, if the first operand | |
6216 | an imm8, the source operand is the 2nd one. If the last | |
6217 | operand is imm8, the source operand is the first one. */ | |
9c2799c2 | 6218 | gas_assert ((i.imm_operands == 2 |
7ab9ffdd L |
6219 | && i.types[0].bitfield.imm8 |
6220 | && i.types[1].bitfield.imm8) | |
2426c15f | 6221 | || (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd L |
6222 | && i.imm_operands == 1 |
6223 | && (i.types[0].bitfield.imm8 | |
43234a1e L |
6224 | || i.types[i.operands - 1].bitfield.imm8 |
6225 | || i.rounding))); | |
9f2670f2 L |
6226 | if (i.imm_operands == 2) |
6227 | source = 2; | |
6228 | else | |
c0f3af97 L |
6229 | { |
6230 | if (i.types[0].bitfield.imm8) | |
6231 | source = 1; | |
6232 | else | |
6233 | source = 0; | |
6234 | } | |
c0f3af97 L |
6235 | break; |
6236 | case 5: | |
43234a1e L |
6237 | if (i.tm.opcode_modifier.evex) |
6238 | { | |
6239 | /* For EVEX instructions, when there are 5 operands, the | |
6240 | first one must be immediate operand. If the second one | |
6241 | is immediate operand, the source operand is the 3th | |
6242 | one. If the last one is immediate operand, the source | |
6243 | operand is the 2nd one. */ | |
6244 | gas_assert (i.imm_operands == 2 | |
6245 | && i.tm.opcode_modifier.sae | |
6246 | && operand_type_check (i.types[0], imm)); | |
6247 | if (operand_type_check (i.types[1], imm)) | |
6248 | source = 2; | |
6249 | else if (operand_type_check (i.types[4], imm)) | |
6250 | source = 1; | |
6251 | else | |
6252 | abort (); | |
6253 | } | |
cab737b9 L |
6254 | break; |
6255 | default: | |
6256 | abort (); | |
6257 | } | |
6258 | ||
c0f3af97 L |
6259 | if (!vex_3_sources) |
6260 | { | |
6261 | dest = source + 1; | |
6262 | ||
43234a1e L |
6263 | /* RC/SAE operand could be between DEST and SRC. That happens |
6264 | when one operand is GPR and the other one is XMM/YMM/ZMM | |
6265 | register. */ | |
6266 | if (i.rounding && i.rounding->operand == (int) dest) | |
6267 | dest++; | |
6268 | ||
2426c15f | 6269 | if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
c0f3af97 | 6270 | { |
43234a1e L |
6271 | /* For instructions with VexNDS, the register-only source |
6272 | operand must be 32/64bit integer, XMM, YMM or ZMM | |
6273 | register. It is encoded in VEX prefix. We need to | |
6274 | clear RegMem bit before calling operand_type_equal. */ | |
f12dc422 L |
6275 | |
6276 | i386_operand_type op; | |
6277 | unsigned int vvvv; | |
6278 | ||
6279 | /* Check register-only source operand when two source | |
6280 | operands are swapped. */ | |
6281 | if (!i.tm.operand_types[source].bitfield.baseindex | |
6282 | && i.tm.operand_types[dest].bitfield.baseindex) | |
6283 | { | |
6284 | vvvv = source; | |
6285 | source = dest; | |
6286 | } | |
6287 | else | |
6288 | vvvv = dest; | |
6289 | ||
6290 | op = i.tm.operand_types[vvvv]; | |
fa99fab2 | 6291 | op.bitfield.regmem = 0; |
c0f3af97 | 6292 | if ((dest + 1) >= i.operands |
ac4eb736 AM |
6293 | || (!op.bitfield.reg32 |
6294 | && op.bitfield.reg64 | |
f12dc422 | 6295 | && !operand_type_equal (&op, ®xmm) |
43234a1e L |
6296 | && !operand_type_equal (&op, ®ymm) |
6297 | && !operand_type_equal (&op, ®zmm) | |
6298 | && !operand_type_equal (&op, ®mask))) | |
c0f3af97 | 6299 | abort (); |
f12dc422 | 6300 | i.vex.register_specifier = i.op[vvvv].regs; |
c0f3af97 L |
6301 | dest++; |
6302 | } | |
6303 | } | |
29b0f896 AM |
6304 | |
6305 | i.rm.mode = 3; | |
6306 | /* One of the register operands will be encoded in the i.tm.reg | |
6307 | field, the other in the combined i.tm.mode and i.tm.regmem | |
6308 | fields. If no form of this instruction supports a memory | |
6309 | destination operand, then we assume the source operand may | |
6310 | sometimes be a memory operand and so we need to store the | |
6311 | destination in the i.rm.reg field. */ | |
40fb9820 L |
6312 | if (!i.tm.operand_types[dest].bitfield.regmem |
6313 | && operand_type_check (i.tm.operand_types[dest], anymem) == 0) | |
29b0f896 AM |
6314 | { |
6315 | i.rm.reg = i.op[dest].regs->reg_num; | |
6316 | i.rm.regmem = i.op[source].regs->reg_num; | |
6317 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 6318 | i.rex |= REX_R; |
43234a1e L |
6319 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
6320 | i.vrex |= REX_R; | |
29b0f896 | 6321 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 6322 | i.rex |= REX_B; |
43234a1e L |
6323 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
6324 | i.vrex |= REX_B; | |
29b0f896 AM |
6325 | } |
6326 | else | |
6327 | { | |
6328 | i.rm.reg = i.op[source].regs->reg_num; | |
6329 | i.rm.regmem = i.op[dest].regs->reg_num; | |
6330 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 6331 | i.rex |= REX_B; |
43234a1e L |
6332 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
6333 | i.vrex |= REX_B; | |
29b0f896 | 6334 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 6335 | i.rex |= REX_R; |
43234a1e L |
6336 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
6337 | i.vrex |= REX_R; | |
29b0f896 | 6338 | } |
161a04f6 | 6339 | if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B))) |
c4a530c5 | 6340 | { |
40fb9820 L |
6341 | if (!i.types[0].bitfield.control |
6342 | && !i.types[1].bitfield.control) | |
c4a530c5 | 6343 | abort (); |
161a04f6 | 6344 | i.rex &= ~(REX_R | REX_B); |
c4a530c5 JB |
6345 | add_prefix (LOCK_PREFIX_OPCODE); |
6346 | } | |
29b0f896 AM |
6347 | } |
6348 | else | |
6349 | { /* If it's not 2 reg operands... */ | |
c0f3af97 L |
6350 | unsigned int mem; |
6351 | ||
29b0f896 AM |
6352 | if (i.mem_operands) |
6353 | { | |
6354 | unsigned int fake_zero_displacement = 0; | |
99018f42 | 6355 | unsigned int op; |
4eed87de | 6356 | |
7ab9ffdd L |
6357 | for (op = 0; op < i.operands; op++) |
6358 | if (operand_type_check (i.types[op], anymem)) | |
6359 | break; | |
7ab9ffdd | 6360 | gas_assert (op < i.operands); |
29b0f896 | 6361 | |
6c30d220 L |
6362 | if (i.tm.opcode_modifier.vecsib) |
6363 | { | |
6364 | if (i.index_reg->reg_num == RegEiz | |
6365 | || i.index_reg->reg_num == RegRiz) | |
6366 | abort (); | |
6367 | ||
6368 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
6369 | if (!i.base_reg) | |
6370 | { | |
6371 | i.sib.base = NO_BASE_REGISTER; | |
6372 | i.sib.scale = i.log2_scale_factor; | |
43234a1e L |
6373 | /* No Vec_Disp8 if there is no base. */ |
6374 | i.types[op].bitfield.vec_disp8 = 0; | |
6c30d220 L |
6375 | i.types[op].bitfield.disp8 = 0; |
6376 | i.types[op].bitfield.disp16 = 0; | |
6377 | i.types[op].bitfield.disp64 = 0; | |
6378 | if (flag_code != CODE_64BIT) | |
6379 | { | |
6380 | /* Must be 32 bit */ | |
6381 | i.types[op].bitfield.disp32 = 1; | |
6382 | i.types[op].bitfield.disp32s = 0; | |
6383 | } | |
6384 | else | |
6385 | { | |
6386 | i.types[op].bitfield.disp32 = 0; | |
6387 | i.types[op].bitfield.disp32s = 1; | |
6388 | } | |
6389 | } | |
6390 | i.sib.index = i.index_reg->reg_num; | |
6391 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
6392 | i.rex |= REX_X; | |
43234a1e L |
6393 | if ((i.index_reg->reg_flags & RegVRex) != 0) |
6394 | i.vrex |= REX_X; | |
6c30d220 L |
6395 | } |
6396 | ||
29b0f896 AM |
6397 | default_seg = &ds; |
6398 | ||
6399 | if (i.base_reg == 0) | |
6400 | { | |
6401 | i.rm.mode = 0; | |
6402 | if (!i.disp_operands) | |
6c30d220 L |
6403 | { |
6404 | fake_zero_displacement = 1; | |
6405 | /* Instructions with VSIB byte need 32bit displacement | |
6406 | if there is no base register. */ | |
6407 | if (i.tm.opcode_modifier.vecsib) | |
6408 | i.types[op].bitfield.disp32 = 1; | |
6409 | } | |
29b0f896 AM |
6410 | if (i.index_reg == 0) |
6411 | { | |
6c30d220 | 6412 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 6413 | /* Operand is just <disp> */ |
20f0a1fc | 6414 | if (flag_code == CODE_64BIT) |
29b0f896 AM |
6415 | { |
6416 | /* 64bit mode overwrites the 32bit absolute | |
6417 | addressing by RIP relative addressing and | |
6418 | absolute addressing is encoded by one of the | |
6419 | redundant SIB forms. */ | |
6420 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
6421 | i.sib.base = NO_BASE_REGISTER; | |
6422 | i.sib.index = NO_INDEX_REGISTER; | |
fc225355 | 6423 | i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) |
40fb9820 | 6424 | ? disp32s : disp32); |
20f0a1fc | 6425 | } |
fc225355 L |
6426 | else if ((flag_code == CODE_16BIT) |
6427 | ^ (i.prefix[ADDR_PREFIX] != 0)) | |
20f0a1fc NC |
6428 | { |
6429 | i.rm.regmem = NO_BASE_REGISTER_16; | |
40fb9820 | 6430 | i.types[op] = disp16; |
20f0a1fc NC |
6431 | } |
6432 | else | |
6433 | { | |
6434 | i.rm.regmem = NO_BASE_REGISTER; | |
40fb9820 | 6435 | i.types[op] = disp32; |
29b0f896 AM |
6436 | } |
6437 | } | |
6c30d220 | 6438 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 6439 | { |
6c30d220 | 6440 | /* !i.base_reg && i.index_reg */ |
db51cc60 L |
6441 | if (i.index_reg->reg_num == RegEiz |
6442 | || i.index_reg->reg_num == RegRiz) | |
6443 | i.sib.index = NO_INDEX_REGISTER; | |
6444 | else | |
6445 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
6446 | i.sib.base = NO_BASE_REGISTER; |
6447 | i.sib.scale = i.log2_scale_factor; | |
6448 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
43234a1e L |
6449 | /* No Vec_Disp8 if there is no base. */ |
6450 | i.types[op].bitfield.vec_disp8 = 0; | |
40fb9820 L |
6451 | i.types[op].bitfield.disp8 = 0; |
6452 | i.types[op].bitfield.disp16 = 0; | |
6453 | i.types[op].bitfield.disp64 = 0; | |
29b0f896 | 6454 | if (flag_code != CODE_64BIT) |
40fb9820 L |
6455 | { |
6456 | /* Must be 32 bit */ | |
6457 | i.types[op].bitfield.disp32 = 1; | |
6458 | i.types[op].bitfield.disp32s = 0; | |
6459 | } | |
29b0f896 | 6460 | else |
40fb9820 L |
6461 | { |
6462 | i.types[op].bitfield.disp32 = 0; | |
6463 | i.types[op].bitfield.disp32s = 1; | |
6464 | } | |
29b0f896 | 6465 | if ((i.index_reg->reg_flags & RegRex) != 0) |
161a04f6 | 6466 | i.rex |= REX_X; |
29b0f896 AM |
6467 | } |
6468 | } | |
6469 | /* RIP addressing for 64bit mode. */ | |
9a04903e JB |
6470 | else if (i.base_reg->reg_num == RegRip || |
6471 | i.base_reg->reg_num == RegEip) | |
29b0f896 | 6472 | { |
6c30d220 | 6473 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 6474 | i.rm.regmem = NO_BASE_REGISTER; |
40fb9820 L |
6475 | i.types[op].bitfield.disp8 = 0; |
6476 | i.types[op].bitfield.disp16 = 0; | |
6477 | i.types[op].bitfield.disp32 = 0; | |
6478 | i.types[op].bitfield.disp32s = 1; | |
6479 | i.types[op].bitfield.disp64 = 0; | |
43234a1e | 6480 | i.types[op].bitfield.vec_disp8 = 0; |
71903a11 | 6481 | i.flags[op] |= Operand_PCrel; |
20f0a1fc NC |
6482 | if (! i.disp_operands) |
6483 | fake_zero_displacement = 1; | |
29b0f896 | 6484 | } |
40fb9820 | 6485 | else if (i.base_reg->reg_type.bitfield.reg16) |
29b0f896 | 6486 | { |
6c30d220 | 6487 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
6488 | switch (i.base_reg->reg_num) |
6489 | { | |
6490 | case 3: /* (%bx) */ | |
6491 | if (i.index_reg == 0) | |
6492 | i.rm.regmem = 7; | |
6493 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
6494 | i.rm.regmem = i.index_reg->reg_num - 6; | |
6495 | break; | |
6496 | case 5: /* (%bp) */ | |
6497 | default_seg = &ss; | |
6498 | if (i.index_reg == 0) | |
6499 | { | |
6500 | i.rm.regmem = 6; | |
40fb9820 | 6501 | if (operand_type_check (i.types[op], disp) == 0) |
29b0f896 AM |
6502 | { |
6503 | /* fake (%bp) into 0(%bp) */ | |
43234a1e L |
6504 | if (i.tm.operand_types[op].bitfield.vec_disp8) |
6505 | i.types[op].bitfield.vec_disp8 = 1; | |
6506 | else | |
6507 | i.types[op].bitfield.disp8 = 1; | |
252b5132 | 6508 | fake_zero_displacement = 1; |
29b0f896 AM |
6509 | } |
6510 | } | |
6511 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
6512 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
6513 | break; | |
6514 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
6515 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
6516 | } | |
6517 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
6518 | } | |
6519 | else /* i.base_reg and 32/64 bit mode */ | |
6520 | { | |
6521 | if (flag_code == CODE_64BIT | |
40fb9820 L |
6522 | && operand_type_check (i.types[op], disp)) |
6523 | { | |
6524 | i386_operand_type temp; | |
0dfbf9d7 | 6525 | operand_type_set (&temp, 0); |
40fb9820 | 6526 | temp.bitfield.disp8 = i.types[op].bitfield.disp8; |
43234a1e L |
6527 | temp.bitfield.vec_disp8 |
6528 | = i.types[op].bitfield.vec_disp8; | |
40fb9820 L |
6529 | i.types[op] = temp; |
6530 | if (i.prefix[ADDR_PREFIX] == 0) | |
6531 | i.types[op].bitfield.disp32s = 1; | |
6532 | else | |
6533 | i.types[op].bitfield.disp32 = 1; | |
6534 | } | |
20f0a1fc | 6535 | |
6c30d220 L |
6536 | if (!i.tm.opcode_modifier.vecsib) |
6537 | i.rm.regmem = i.base_reg->reg_num; | |
29b0f896 | 6538 | if ((i.base_reg->reg_flags & RegRex) != 0) |
161a04f6 | 6539 | i.rex |= REX_B; |
29b0f896 AM |
6540 | i.sib.base = i.base_reg->reg_num; |
6541 | /* x86-64 ignores REX prefix bit here to avoid decoder | |
6542 | complications. */ | |
848930b2 JB |
6543 | if (!(i.base_reg->reg_flags & RegRex) |
6544 | && (i.base_reg->reg_num == EBP_REG_NUM | |
6545 | || i.base_reg->reg_num == ESP_REG_NUM)) | |
29b0f896 | 6546 | default_seg = &ss; |
848930b2 | 6547 | if (i.base_reg->reg_num == 5 && i.disp_operands == 0) |
29b0f896 | 6548 | { |
848930b2 | 6549 | fake_zero_displacement = 1; |
43234a1e L |
6550 | if (i.tm.operand_types [op].bitfield.vec_disp8) |
6551 | i.types[op].bitfield.vec_disp8 = 1; | |
6552 | else | |
6553 | i.types[op].bitfield.disp8 = 1; | |
29b0f896 AM |
6554 | } |
6555 | i.sib.scale = i.log2_scale_factor; | |
6556 | if (i.index_reg == 0) | |
6557 | { | |
6c30d220 | 6558 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
6559 | /* <disp>(%esp) becomes two byte modrm with no index |
6560 | register. We've already stored the code for esp | |
6561 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. | |
6562 | Any base register besides %esp will not use the | |
6563 | extra modrm byte. */ | |
6564 | i.sib.index = NO_INDEX_REGISTER; | |
29b0f896 | 6565 | } |
6c30d220 | 6566 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 6567 | { |
db51cc60 L |
6568 | if (i.index_reg->reg_num == RegEiz |
6569 | || i.index_reg->reg_num == RegRiz) | |
6570 | i.sib.index = NO_INDEX_REGISTER; | |
6571 | else | |
6572 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
6573 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
6574 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
161a04f6 | 6575 | i.rex |= REX_X; |
29b0f896 | 6576 | } |
67a4f2b7 AO |
6577 | |
6578 | if (i.disp_operands | |
6579 | && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL | |
6580 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) | |
6581 | i.rm.mode = 0; | |
6582 | else | |
a501d77e L |
6583 | { |
6584 | if (!fake_zero_displacement | |
6585 | && !i.disp_operands | |
6586 | && i.disp_encoding) | |
6587 | { | |
6588 | fake_zero_displacement = 1; | |
6589 | if (i.disp_encoding == disp_encoding_8bit) | |
6590 | i.types[op].bitfield.disp8 = 1; | |
6591 | else | |
6592 | i.types[op].bitfield.disp32 = 1; | |
6593 | } | |
6594 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
6595 | } | |
29b0f896 | 6596 | } |
252b5132 | 6597 | |
29b0f896 AM |
6598 | if (fake_zero_displacement) |
6599 | { | |
6600 | /* Fakes a zero displacement assuming that i.types[op] | |
6601 | holds the correct displacement size. */ | |
6602 | expressionS *exp; | |
6603 | ||
9c2799c2 | 6604 | gas_assert (i.op[op].disps == 0); |
29b0f896 AM |
6605 | exp = &disp_expressions[i.disp_operands++]; |
6606 | i.op[op].disps = exp; | |
6607 | exp->X_op = O_constant; | |
6608 | exp->X_add_number = 0; | |
6609 | exp->X_add_symbol = (symbolS *) 0; | |
6610 | exp->X_op_symbol = (symbolS *) 0; | |
6611 | } | |
c0f3af97 L |
6612 | |
6613 | mem = op; | |
29b0f896 | 6614 | } |
c0f3af97 L |
6615 | else |
6616 | mem = ~0; | |
252b5132 | 6617 | |
8c43a48b | 6618 | if (i.tm.opcode_modifier.vexsources == XOP2SOURCES) |
5dd85c99 SP |
6619 | { |
6620 | if (operand_type_check (i.types[0], imm)) | |
6621 | i.vex.register_specifier = NULL; | |
6622 | else | |
6623 | { | |
6624 | /* VEX.vvvv encodes one of the sources when the first | |
6625 | operand is not an immediate. */ | |
1ef99a7b | 6626 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
6627 | i.vex.register_specifier = i.op[0].regs; |
6628 | else | |
6629 | i.vex.register_specifier = i.op[1].regs; | |
6630 | } | |
6631 | ||
6632 | /* Destination is a XMM register encoded in the ModRM.reg | |
6633 | and VEX.R bit. */ | |
6634 | i.rm.reg = i.op[2].regs->reg_num; | |
6635 | if ((i.op[2].regs->reg_flags & RegRex) != 0) | |
6636 | i.rex |= REX_R; | |
6637 | ||
6638 | /* ModRM.rm and VEX.B encodes the other source. */ | |
6639 | if (!i.mem_operands) | |
6640 | { | |
6641 | i.rm.mode = 3; | |
6642 | ||
1ef99a7b | 6643 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
6644 | i.rm.regmem = i.op[1].regs->reg_num; |
6645 | else | |
6646 | i.rm.regmem = i.op[0].regs->reg_num; | |
6647 | ||
6648 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
6649 | i.rex |= REX_B; | |
6650 | } | |
6651 | } | |
2426c15f | 6652 | else if (i.tm.opcode_modifier.vexvvvv == VEXLWP) |
f88c9eb0 SP |
6653 | { |
6654 | i.vex.register_specifier = i.op[2].regs; | |
6655 | if (!i.mem_operands) | |
6656 | { | |
6657 | i.rm.mode = 3; | |
6658 | i.rm.regmem = i.op[1].regs->reg_num; | |
6659 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
6660 | i.rex |= REX_B; | |
6661 | } | |
6662 | } | |
29b0f896 AM |
6663 | /* Fill in i.rm.reg or i.rm.regmem field with register operand |
6664 | (if any) based on i.tm.extension_opcode. Again, we must be | |
6665 | careful to make sure that segment/control/debug/test/MMX | |
6666 | registers are coded into the i.rm.reg field. */ | |
f88c9eb0 | 6667 | else if (i.reg_operands) |
29b0f896 | 6668 | { |
99018f42 | 6669 | unsigned int op; |
7ab9ffdd L |
6670 | unsigned int vex_reg = ~0; |
6671 | ||
6672 | for (op = 0; op < i.operands; op++) | |
6673 | if (i.types[op].bitfield.reg8 | |
6674 | || i.types[op].bitfield.reg16 | |
6675 | || i.types[op].bitfield.reg32 | |
6676 | || i.types[op].bitfield.reg64 | |
6677 | || i.types[op].bitfield.regmmx | |
6678 | || i.types[op].bitfield.regxmm | |
6679 | || i.types[op].bitfield.regymm | |
7e8b059b | 6680 | || i.types[op].bitfield.regbnd |
43234a1e L |
6681 | || i.types[op].bitfield.regzmm |
6682 | || i.types[op].bitfield.regmask | |
7ab9ffdd L |
6683 | || i.types[op].bitfield.sreg2 |
6684 | || i.types[op].bitfield.sreg3 | |
6685 | || i.types[op].bitfield.control | |
6686 | || i.types[op].bitfield.debug | |
6687 | || i.types[op].bitfield.test) | |
6688 | break; | |
c0209578 | 6689 | |
7ab9ffdd L |
6690 | if (vex_3_sources) |
6691 | op = dest; | |
2426c15f | 6692 | else if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd L |
6693 | { |
6694 | /* For instructions with VexNDS, the register-only | |
6695 | source operand is encoded in VEX prefix. */ | |
6696 | gas_assert (mem != (unsigned int) ~0); | |
c0f3af97 | 6697 | |
7ab9ffdd | 6698 | if (op > mem) |
c0f3af97 | 6699 | { |
7ab9ffdd L |
6700 | vex_reg = op++; |
6701 | gas_assert (op < i.operands); | |
c0f3af97 L |
6702 | } |
6703 | else | |
c0f3af97 | 6704 | { |
f12dc422 L |
6705 | /* Check register-only source operand when two source |
6706 | operands are swapped. */ | |
6707 | if (!i.tm.operand_types[op].bitfield.baseindex | |
6708 | && i.tm.operand_types[op + 1].bitfield.baseindex) | |
6709 | { | |
6710 | vex_reg = op; | |
6711 | op += 2; | |
6712 | gas_assert (mem == (vex_reg + 1) | |
6713 | && op < i.operands); | |
6714 | } | |
6715 | else | |
6716 | { | |
6717 | vex_reg = op + 1; | |
6718 | gas_assert (vex_reg < i.operands); | |
6719 | } | |
c0f3af97 | 6720 | } |
7ab9ffdd | 6721 | } |
2426c15f | 6722 | else if (i.tm.opcode_modifier.vexvvvv == VEXNDD) |
7ab9ffdd | 6723 | { |
f12dc422 | 6724 | /* For instructions with VexNDD, the register destination |
7ab9ffdd | 6725 | is encoded in VEX prefix. */ |
f12dc422 L |
6726 | if (i.mem_operands == 0) |
6727 | { | |
6728 | /* There is no memory operand. */ | |
6729 | gas_assert ((op + 2) == i.operands); | |
6730 | vex_reg = op + 1; | |
6731 | } | |
6732 | else | |
8d63c93e | 6733 | { |
f12dc422 L |
6734 | /* There are only 2 operands. */ |
6735 | gas_assert (op < 2 && i.operands == 2); | |
6736 | vex_reg = 1; | |
6737 | } | |
7ab9ffdd L |
6738 | } |
6739 | else | |
6740 | gas_assert (op < i.operands); | |
99018f42 | 6741 | |
7ab9ffdd L |
6742 | if (vex_reg != (unsigned int) ~0) |
6743 | { | |
f12dc422 | 6744 | i386_operand_type *type = &i.tm.operand_types[vex_reg]; |
7ab9ffdd | 6745 | |
f12dc422 L |
6746 | if (type->bitfield.reg32 != 1 |
6747 | && type->bitfield.reg64 != 1 | |
6748 | && !operand_type_equal (type, ®xmm) | |
43234a1e L |
6749 | && !operand_type_equal (type, ®ymm) |
6750 | && !operand_type_equal (type, ®zmm) | |
6751 | && !operand_type_equal (type, ®mask)) | |
7ab9ffdd | 6752 | abort (); |
f88c9eb0 | 6753 | |
7ab9ffdd L |
6754 | i.vex.register_specifier = i.op[vex_reg].regs; |
6755 | } | |
6756 | ||
1b9f0c97 L |
6757 | /* Don't set OP operand twice. */ |
6758 | if (vex_reg != op) | |
7ab9ffdd | 6759 | { |
1b9f0c97 L |
6760 | /* If there is an extension opcode to put here, the |
6761 | register number must be put into the regmem field. */ | |
6762 | if (i.tm.extension_opcode != None) | |
6763 | { | |
6764 | i.rm.regmem = i.op[op].regs->reg_num; | |
6765 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
6766 | i.rex |= REX_B; | |
43234a1e L |
6767 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
6768 | i.vrex |= REX_B; | |
1b9f0c97 L |
6769 | } |
6770 | else | |
6771 | { | |
6772 | i.rm.reg = i.op[op].regs->reg_num; | |
6773 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
6774 | i.rex |= REX_R; | |
43234a1e L |
6775 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
6776 | i.vrex |= REX_R; | |
1b9f0c97 | 6777 | } |
7ab9ffdd | 6778 | } |
252b5132 | 6779 | |
29b0f896 AM |
6780 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we |
6781 | must set it to 3 to indicate this is a register operand | |
6782 | in the regmem field. */ | |
6783 | if (!i.mem_operands) | |
6784 | i.rm.mode = 3; | |
6785 | } | |
252b5132 | 6786 | |
29b0f896 | 6787 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
c1e679ec | 6788 | if (i.tm.extension_opcode != None) |
29b0f896 AM |
6789 | i.rm.reg = i.tm.extension_opcode; |
6790 | } | |
6791 | return default_seg; | |
6792 | } | |
252b5132 | 6793 | |
29b0f896 | 6794 | static void |
e3bb37b5 | 6795 | output_branch (void) |
29b0f896 AM |
6796 | { |
6797 | char *p; | |
f8a5c266 | 6798 | int size; |
29b0f896 AM |
6799 | int code16; |
6800 | int prefix; | |
6801 | relax_substateT subtype; | |
6802 | symbolS *sym; | |
6803 | offsetT off; | |
6804 | ||
f8a5c266 | 6805 | code16 = flag_code == CODE_16BIT ? CODE16 : 0; |
a501d77e | 6806 | size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL; |
29b0f896 AM |
6807 | |
6808 | prefix = 0; | |
6809 | if (i.prefix[DATA_PREFIX] != 0) | |
252b5132 | 6810 | { |
29b0f896 AM |
6811 | prefix = 1; |
6812 | i.prefixes -= 1; | |
6813 | code16 ^= CODE16; | |
252b5132 | 6814 | } |
29b0f896 AM |
6815 | /* Pentium4 branch hints. */ |
6816 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
6817 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2f66722d | 6818 | { |
29b0f896 AM |
6819 | prefix++; |
6820 | i.prefixes--; | |
6821 | } | |
6822 | if (i.prefix[REX_PREFIX] != 0) | |
6823 | { | |
6824 | prefix++; | |
6825 | i.prefixes--; | |
2f66722d AM |
6826 | } |
6827 | ||
7e8b059b L |
6828 | /* BND prefixed jump. */ |
6829 | if (i.prefix[BND_PREFIX] != 0) | |
6830 | { | |
6831 | FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]); | |
6832 | i.prefixes -= 1; | |
6833 | } | |
6834 | ||
29b0f896 AM |
6835 | if (i.prefixes != 0 && !intel_syntax) |
6836 | as_warn (_("skipping prefixes on this instruction")); | |
6837 | ||
6838 | /* It's always a symbol; End frag & setup for relax. | |
6839 | Make sure there is enough room in this frag for the largest | |
6840 | instruction we may generate in md_convert_frag. This is 2 | |
6841 | bytes for the opcode and room for the prefix and largest | |
6842 | displacement. */ | |
6843 | frag_grow (prefix + 2 + 4); | |
6844 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
6845 | p = frag_more (prefix + 1); | |
6846 | if (i.prefix[DATA_PREFIX] != 0) | |
6847 | *p++ = DATA_PREFIX_OPCODE; | |
6848 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE | |
6849 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
6850 | *p++ = i.prefix[SEG_PREFIX]; | |
6851 | if (i.prefix[REX_PREFIX] != 0) | |
6852 | *p++ = i.prefix[REX_PREFIX]; | |
6853 | *p = i.tm.base_opcode; | |
6854 | ||
6855 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
f8a5c266 | 6856 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size); |
40fb9820 | 6857 | else if (cpu_arch_flags.bitfield.cpui386) |
f8a5c266 | 6858 | subtype = ENCODE_RELAX_STATE (COND_JUMP, size); |
29b0f896 | 6859 | else |
f8a5c266 | 6860 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, size); |
29b0f896 | 6861 | subtype |= code16; |
3e73aa7c | 6862 | |
29b0f896 AM |
6863 | sym = i.op[0].disps->X_add_symbol; |
6864 | off = i.op[0].disps->X_add_number; | |
3e73aa7c | 6865 | |
29b0f896 AM |
6866 | if (i.op[0].disps->X_op != O_constant |
6867 | && i.op[0].disps->X_op != O_symbol) | |
3e73aa7c | 6868 | { |
29b0f896 AM |
6869 | /* Handle complex expressions. */ |
6870 | sym = make_expr_symbol (i.op[0].disps); | |
6871 | off = 0; | |
6872 | } | |
3e73aa7c | 6873 | |
29b0f896 AM |
6874 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
6875 | Pass reloc in fr_var. */ | |
d258b828 | 6876 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); |
29b0f896 | 6877 | } |
3e73aa7c | 6878 | |
29b0f896 | 6879 | static void |
e3bb37b5 | 6880 | output_jump (void) |
29b0f896 AM |
6881 | { |
6882 | char *p; | |
6883 | int size; | |
3e02c1cc | 6884 | fixS *fixP; |
29b0f896 | 6885 | |
40fb9820 | 6886 | if (i.tm.opcode_modifier.jumpbyte) |
29b0f896 AM |
6887 | { |
6888 | /* This is a loop or jecxz type instruction. */ | |
6889 | size = 1; | |
6890 | if (i.prefix[ADDR_PREFIX] != 0) | |
6891 | { | |
6892 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); | |
6893 | i.prefixes -= 1; | |
6894 | } | |
6895 | /* Pentium4 branch hints. */ | |
6896 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
6897 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
6898 | { | |
6899 | FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); | |
6900 | i.prefixes--; | |
3e73aa7c JH |
6901 | } |
6902 | } | |
29b0f896 AM |
6903 | else |
6904 | { | |
6905 | int code16; | |
3e73aa7c | 6906 | |
29b0f896 AM |
6907 | code16 = 0; |
6908 | if (flag_code == CODE_16BIT) | |
6909 | code16 = CODE16; | |
3e73aa7c | 6910 | |
29b0f896 AM |
6911 | if (i.prefix[DATA_PREFIX] != 0) |
6912 | { | |
6913 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); | |
6914 | i.prefixes -= 1; | |
6915 | code16 ^= CODE16; | |
6916 | } | |
252b5132 | 6917 | |
29b0f896 AM |
6918 | size = 4; |
6919 | if (code16) | |
6920 | size = 2; | |
6921 | } | |
9fcc94b6 | 6922 | |
29b0f896 AM |
6923 | if (i.prefix[REX_PREFIX] != 0) |
6924 | { | |
6925 | FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); | |
6926 | i.prefixes -= 1; | |
6927 | } | |
252b5132 | 6928 | |
7e8b059b L |
6929 | /* BND prefixed jump. */ |
6930 | if (i.prefix[BND_PREFIX] != 0) | |
6931 | { | |
6932 | FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]); | |
6933 | i.prefixes -= 1; | |
6934 | } | |
6935 | ||
29b0f896 AM |
6936 | if (i.prefixes != 0 && !intel_syntax) |
6937 | as_warn (_("skipping prefixes on this instruction")); | |
e0890092 | 6938 | |
42164a71 L |
6939 | p = frag_more (i.tm.opcode_length + size); |
6940 | switch (i.tm.opcode_length) | |
6941 | { | |
6942 | case 2: | |
6943 | *p++ = i.tm.base_opcode >> 8; | |
6944 | case 1: | |
6945 | *p++ = i.tm.base_opcode; | |
6946 | break; | |
6947 | default: | |
6948 | abort (); | |
6949 | } | |
e0890092 | 6950 | |
3e02c1cc | 6951 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
d258b828 | 6952 | i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0])); |
3e02c1cc AM |
6953 | |
6954 | /* All jumps handled here are signed, but don't use a signed limit | |
6955 | check for 32 and 16 bit jumps as we want to allow wrap around at | |
6956 | 4G and 64k respectively. */ | |
6957 | if (size == 1) | |
6958 | fixP->fx_signed = 1; | |
29b0f896 | 6959 | } |
e0890092 | 6960 | |
29b0f896 | 6961 | static void |
e3bb37b5 | 6962 | output_interseg_jump (void) |
29b0f896 AM |
6963 | { |
6964 | char *p; | |
6965 | int size; | |
6966 | int prefix; | |
6967 | int code16; | |
252b5132 | 6968 | |
29b0f896 AM |
6969 | code16 = 0; |
6970 | if (flag_code == CODE_16BIT) | |
6971 | code16 = CODE16; | |
a217f122 | 6972 | |
29b0f896 AM |
6973 | prefix = 0; |
6974 | if (i.prefix[DATA_PREFIX] != 0) | |
6975 | { | |
6976 | prefix = 1; | |
6977 | i.prefixes -= 1; | |
6978 | code16 ^= CODE16; | |
6979 | } | |
6980 | if (i.prefix[REX_PREFIX] != 0) | |
6981 | { | |
6982 | prefix++; | |
6983 | i.prefixes -= 1; | |
6984 | } | |
252b5132 | 6985 | |
29b0f896 AM |
6986 | size = 4; |
6987 | if (code16) | |
6988 | size = 2; | |
252b5132 | 6989 | |
29b0f896 AM |
6990 | if (i.prefixes != 0 && !intel_syntax) |
6991 | as_warn (_("skipping prefixes on this instruction")); | |
252b5132 | 6992 | |
29b0f896 AM |
6993 | /* 1 opcode; 2 segment; offset */ |
6994 | p = frag_more (prefix + 1 + 2 + size); | |
3e73aa7c | 6995 | |
29b0f896 AM |
6996 | if (i.prefix[DATA_PREFIX] != 0) |
6997 | *p++ = DATA_PREFIX_OPCODE; | |
252b5132 | 6998 | |
29b0f896 AM |
6999 | if (i.prefix[REX_PREFIX] != 0) |
7000 | *p++ = i.prefix[REX_PREFIX]; | |
252b5132 | 7001 | |
29b0f896 AM |
7002 | *p++ = i.tm.base_opcode; |
7003 | if (i.op[1].imms->X_op == O_constant) | |
7004 | { | |
7005 | offsetT n = i.op[1].imms->X_add_number; | |
252b5132 | 7006 | |
29b0f896 AM |
7007 | if (size == 2 |
7008 | && !fits_in_unsigned_word (n) | |
7009 | && !fits_in_signed_word (n)) | |
7010 | { | |
7011 | as_bad (_("16-bit jump out of range")); | |
7012 | return; | |
7013 | } | |
7014 | md_number_to_chars (p, n, size); | |
7015 | } | |
7016 | else | |
7017 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
d258b828 | 7018 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); |
29b0f896 AM |
7019 | if (i.op[0].imms->X_op != O_constant) |
7020 | as_bad (_("can't handle non absolute segment in `%s'"), | |
7021 | i.tm.name); | |
7022 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); | |
7023 | } | |
a217f122 | 7024 | |
29b0f896 | 7025 | static void |
e3bb37b5 | 7026 | output_insn (void) |
29b0f896 | 7027 | { |
2bbd9c25 JJ |
7028 | fragS *insn_start_frag; |
7029 | offsetT insn_start_off; | |
7030 | ||
29b0f896 AM |
7031 | /* Tie dwarf2 debug info to the address at the start of the insn. |
7032 | We can't do this after the insn has been output as the current | |
7033 | frag may have been closed off. eg. by frag_var. */ | |
7034 | dwarf2_emit_insn (0); | |
7035 | ||
2bbd9c25 JJ |
7036 | insn_start_frag = frag_now; |
7037 | insn_start_off = frag_now_fix (); | |
7038 | ||
29b0f896 | 7039 | /* Output jumps. */ |
40fb9820 | 7040 | if (i.tm.opcode_modifier.jump) |
29b0f896 | 7041 | output_branch (); |
40fb9820 L |
7042 | else if (i.tm.opcode_modifier.jumpbyte |
7043 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 | 7044 | output_jump (); |
40fb9820 | 7045 | else if (i.tm.opcode_modifier.jumpintersegment) |
29b0f896 AM |
7046 | output_interseg_jump (); |
7047 | else | |
7048 | { | |
7049 | /* Output normal instructions here. */ | |
7050 | char *p; | |
7051 | unsigned char *q; | |
47465058 | 7052 | unsigned int j; |
331d2d0d | 7053 | unsigned int prefix; |
4dffcebc | 7054 | |
e4e00185 AS |
7055 | if (avoid_fence |
7056 | && i.tm.base_opcode == 0xfae | |
7057 | && i.operands == 1 | |
7058 | && i.imm_operands == 1 | |
7059 | && (i.op[0].imms->X_add_number == 0xe8 | |
7060 | || i.op[0].imms->X_add_number == 0xf0 | |
7061 | || i.op[0].imms->X_add_number == 0xf8)) | |
7062 | { | |
7063 | /* Encode lfence, mfence, and sfence as | |
7064 | f0 83 04 24 00 lock addl $0x0, (%{re}sp). */ | |
7065 | offsetT val = 0x240483f0ULL; | |
7066 | p = frag_more (5); | |
7067 | md_number_to_chars (p, val, 5); | |
7068 | return; | |
7069 | } | |
7070 | ||
d022bddd IT |
7071 | /* Some processors fail on LOCK prefix. This options makes |
7072 | assembler ignore LOCK prefix and serves as a workaround. */ | |
7073 | if (omit_lock_prefix) | |
7074 | { | |
7075 | if (i.tm.base_opcode == LOCK_PREFIX_OPCODE) | |
7076 | return; | |
7077 | i.prefix[LOCK_PREFIX] = 0; | |
7078 | } | |
7079 | ||
43234a1e L |
7080 | /* Since the VEX/EVEX prefix contains the implicit prefix, we |
7081 | don't need the explicit prefix. */ | |
7082 | if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex) | |
bc4bd9ab | 7083 | { |
c0f3af97 | 7084 | switch (i.tm.opcode_length) |
bc4bd9ab | 7085 | { |
c0f3af97 L |
7086 | case 3: |
7087 | if (i.tm.base_opcode & 0xff000000) | |
4dffcebc | 7088 | { |
c0f3af97 L |
7089 | prefix = (i.tm.base_opcode >> 24) & 0xff; |
7090 | goto check_prefix; | |
7091 | } | |
7092 | break; | |
7093 | case 2: | |
7094 | if ((i.tm.base_opcode & 0xff0000) != 0) | |
7095 | { | |
7096 | prefix = (i.tm.base_opcode >> 16) & 0xff; | |
7097 | if (i.tm.cpu_flags.bitfield.cpupadlock) | |
7098 | { | |
4dffcebc | 7099 | check_prefix: |
c0f3af97 | 7100 | if (prefix != REPE_PREFIX_OPCODE |
c32fa91d | 7101 | || (i.prefix[REP_PREFIX] |
c0f3af97 L |
7102 | != REPE_PREFIX_OPCODE)) |
7103 | add_prefix (prefix); | |
7104 | } | |
7105 | else | |
4dffcebc L |
7106 | add_prefix (prefix); |
7107 | } | |
c0f3af97 L |
7108 | break; |
7109 | case 1: | |
7110 | break; | |
7111 | default: | |
7112 | abort (); | |
bc4bd9ab | 7113 | } |
c0f3af97 | 7114 | |
6d19a37a | 7115 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
cf61b747 L |
7116 | /* For x32, add a dummy REX_OPCODE prefix for mov/add with |
7117 | R_X86_64_GOTTPOFF relocation so that linker can safely | |
7118 | perform IE->LE optimization. */ | |
7119 | if (x86_elf_abi == X86_64_X32_ABI | |
7120 | && i.operands == 2 | |
7121 | && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF | |
7122 | && i.prefix[REX_PREFIX] == 0) | |
7123 | add_prefix (REX_OPCODE); | |
6d19a37a | 7124 | #endif |
cf61b747 | 7125 | |
c0f3af97 L |
7126 | /* The prefix bytes. */ |
7127 | for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) | |
7128 | if (*q) | |
7129 | FRAG_APPEND_1_CHAR (*q); | |
0f10071e | 7130 | } |
ae5c1c7b | 7131 | else |
c0f3af97 L |
7132 | { |
7133 | for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++) | |
7134 | if (*q) | |
7135 | switch (j) | |
7136 | { | |
7137 | case REX_PREFIX: | |
7138 | /* REX byte is encoded in VEX prefix. */ | |
7139 | break; | |
7140 | case SEG_PREFIX: | |
7141 | case ADDR_PREFIX: | |
7142 | FRAG_APPEND_1_CHAR (*q); | |
7143 | break; | |
7144 | default: | |
7145 | /* There should be no other prefixes for instructions | |
7146 | with VEX prefix. */ | |
7147 | abort (); | |
7148 | } | |
7149 | ||
43234a1e L |
7150 | /* For EVEX instructions i.vrex should become 0 after |
7151 | build_evex_prefix. For VEX instructions upper 16 registers | |
7152 | aren't available, so VREX should be 0. */ | |
7153 | if (i.vrex) | |
7154 | abort (); | |
c0f3af97 L |
7155 | /* Now the VEX prefix. */ |
7156 | p = frag_more (i.vex.length); | |
7157 | for (j = 0; j < i.vex.length; j++) | |
7158 | p[j] = i.vex.bytes[j]; | |
7159 | } | |
252b5132 | 7160 | |
29b0f896 | 7161 | /* Now the opcode; be careful about word order here! */ |
4dffcebc | 7162 | if (i.tm.opcode_length == 1) |
29b0f896 AM |
7163 | { |
7164 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
7165 | } | |
7166 | else | |
7167 | { | |
4dffcebc | 7168 | switch (i.tm.opcode_length) |
331d2d0d | 7169 | { |
43234a1e L |
7170 | case 4: |
7171 | p = frag_more (4); | |
7172 | *p++ = (i.tm.base_opcode >> 24) & 0xff; | |
7173 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
7174 | break; | |
4dffcebc | 7175 | case 3: |
331d2d0d L |
7176 | p = frag_more (3); |
7177 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
4dffcebc L |
7178 | break; |
7179 | case 2: | |
7180 | p = frag_more (2); | |
7181 | break; | |
7182 | default: | |
7183 | abort (); | |
7184 | break; | |
331d2d0d | 7185 | } |
0f10071e | 7186 | |
29b0f896 AM |
7187 | /* Put out high byte first: can't use md_number_to_chars! */ |
7188 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
7189 | *p = i.tm.base_opcode & 0xff; | |
7190 | } | |
3e73aa7c | 7191 | |
29b0f896 | 7192 | /* Now the modrm byte and sib byte (if present). */ |
40fb9820 | 7193 | if (i.tm.opcode_modifier.modrm) |
29b0f896 | 7194 | { |
4a3523fa L |
7195 | FRAG_APPEND_1_CHAR ((i.rm.regmem << 0 |
7196 | | i.rm.reg << 3 | |
7197 | | i.rm.mode << 6)); | |
29b0f896 AM |
7198 | /* If i.rm.regmem == ESP (4) |
7199 | && i.rm.mode != (Register mode) | |
7200 | && not 16 bit | |
7201 | ==> need second modrm byte. */ | |
7202 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
7203 | && i.rm.mode != 3 | |
40fb9820 | 7204 | && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16)) |
4a3523fa L |
7205 | FRAG_APPEND_1_CHAR ((i.sib.base << 0 |
7206 | | i.sib.index << 3 | |
7207 | | i.sib.scale << 6)); | |
29b0f896 | 7208 | } |
3e73aa7c | 7209 | |
29b0f896 | 7210 | if (i.disp_operands) |
2bbd9c25 | 7211 | output_disp (insn_start_frag, insn_start_off); |
3e73aa7c | 7212 | |
29b0f896 | 7213 | if (i.imm_operands) |
2bbd9c25 | 7214 | output_imm (insn_start_frag, insn_start_off); |
29b0f896 | 7215 | } |
252b5132 | 7216 | |
29b0f896 AM |
7217 | #ifdef DEBUG386 |
7218 | if (flag_debug) | |
7219 | { | |
7b81dfbb | 7220 | pi ("" /*line*/, &i); |
29b0f896 AM |
7221 | } |
7222 | #endif /* DEBUG386 */ | |
7223 | } | |
252b5132 | 7224 | |
e205caa7 L |
7225 | /* Return the size of the displacement operand N. */ |
7226 | ||
7227 | static int | |
7228 | disp_size (unsigned int n) | |
7229 | { | |
7230 | int size = 4; | |
43234a1e L |
7231 | |
7232 | /* Vec_Disp8 has to be 8bit. */ | |
7233 | if (i.types[n].bitfield.vec_disp8) | |
7234 | size = 1; | |
7235 | else if (i.types[n].bitfield.disp64) | |
40fb9820 L |
7236 | size = 8; |
7237 | else if (i.types[n].bitfield.disp8) | |
7238 | size = 1; | |
7239 | else if (i.types[n].bitfield.disp16) | |
7240 | size = 2; | |
e205caa7 L |
7241 | return size; |
7242 | } | |
7243 | ||
7244 | /* Return the size of the immediate operand N. */ | |
7245 | ||
7246 | static int | |
7247 | imm_size (unsigned int n) | |
7248 | { | |
7249 | int size = 4; | |
40fb9820 L |
7250 | if (i.types[n].bitfield.imm64) |
7251 | size = 8; | |
7252 | else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) | |
7253 | size = 1; | |
7254 | else if (i.types[n].bitfield.imm16) | |
7255 | size = 2; | |
e205caa7 L |
7256 | return size; |
7257 | } | |
7258 | ||
29b0f896 | 7259 | static void |
64e74474 | 7260 | output_disp (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
7261 | { |
7262 | char *p; | |
7263 | unsigned int n; | |
252b5132 | 7264 | |
29b0f896 AM |
7265 | for (n = 0; n < i.operands; n++) |
7266 | { | |
43234a1e L |
7267 | if (i.types[n].bitfield.vec_disp8 |
7268 | || operand_type_check (i.types[n], disp)) | |
29b0f896 AM |
7269 | { |
7270 | if (i.op[n].disps->X_op == O_constant) | |
7271 | { | |
e205caa7 | 7272 | int size = disp_size (n); |
43234a1e | 7273 | offsetT val = i.op[n].disps->X_add_number; |
252b5132 | 7274 | |
43234a1e L |
7275 | if (i.types[n].bitfield.vec_disp8) |
7276 | val >>= i.memshift; | |
7277 | val = offset_in_range (val, size); | |
29b0f896 AM |
7278 | p = frag_more (size); |
7279 | md_number_to_chars (p, val, size); | |
7280 | } | |
7281 | else | |
7282 | { | |
f86103b7 | 7283 | enum bfd_reloc_code_real reloc_type; |
e205caa7 | 7284 | int size = disp_size (n); |
40fb9820 | 7285 | int sign = i.types[n].bitfield.disp32s; |
29b0f896 | 7286 | int pcrel = (i.flags[n] & Operand_PCrel) != 0; |
02a86693 | 7287 | fixS *fixP; |
29b0f896 | 7288 | |
e205caa7 | 7289 | /* We can't have 8 bit displacement here. */ |
9c2799c2 | 7290 | gas_assert (!i.types[n].bitfield.disp8); |
e205caa7 | 7291 | |
29b0f896 AM |
7292 | /* The PC relative address is computed relative |
7293 | to the instruction boundary, so in case immediate | |
7294 | fields follows, we need to adjust the value. */ | |
7295 | if (pcrel && i.imm_operands) | |
7296 | { | |
29b0f896 | 7297 | unsigned int n1; |
e205caa7 | 7298 | int sz = 0; |
252b5132 | 7299 | |
29b0f896 | 7300 | for (n1 = 0; n1 < i.operands; n1++) |
40fb9820 | 7301 | if (operand_type_check (i.types[n1], imm)) |
252b5132 | 7302 | { |
e205caa7 L |
7303 | /* Only one immediate is allowed for PC |
7304 | relative address. */ | |
9c2799c2 | 7305 | gas_assert (sz == 0); |
e205caa7 L |
7306 | sz = imm_size (n1); |
7307 | i.op[n].disps->X_add_number -= sz; | |
252b5132 | 7308 | } |
29b0f896 | 7309 | /* We should find the immediate. */ |
9c2799c2 | 7310 | gas_assert (sz != 0); |
29b0f896 | 7311 | } |
520dc8e8 | 7312 | |
29b0f896 | 7313 | p = frag_more (size); |
d258b828 | 7314 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
d6ab8113 | 7315 | if (GOT_symbol |
2bbd9c25 | 7316 | && GOT_symbol == i.op[n].disps->X_add_symbol |
d6ab8113 | 7317 | && (((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
7318 | || reloc_type == BFD_RELOC_X86_64_32S |
7319 | || (reloc_type == BFD_RELOC_64 | |
7320 | && object_64bit)) | |
d6ab8113 JB |
7321 | && (i.op[n].disps->X_op == O_symbol |
7322 | || (i.op[n].disps->X_op == O_add | |
7323 | && ((symbol_get_value_expression | |
7324 | (i.op[n].disps->X_op_symbol)->X_op) | |
7325 | == O_subtract)))) | |
7326 | || reloc_type == BFD_RELOC_32_PCREL)) | |
2bbd9c25 JJ |
7327 | { |
7328 | offsetT add; | |
7329 | ||
7330 | if (insn_start_frag == frag_now) | |
7331 | add = (p - frag_now->fr_literal) - insn_start_off; | |
7332 | else | |
7333 | { | |
7334 | fragS *fr; | |
7335 | ||
7336 | add = insn_start_frag->fr_fix - insn_start_off; | |
7337 | for (fr = insn_start_frag->fr_next; | |
7338 | fr && fr != frag_now; fr = fr->fr_next) | |
7339 | add += fr->fr_fix; | |
7340 | add += p - frag_now->fr_literal; | |
7341 | } | |
7342 | ||
4fa24527 | 7343 | if (!object_64bit) |
7b81dfbb AJ |
7344 | { |
7345 | reloc_type = BFD_RELOC_386_GOTPC; | |
7346 | i.op[n].imms->X_add_number += add; | |
7347 | } | |
7348 | else if (reloc_type == BFD_RELOC_64) | |
7349 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
d6ab8113 | 7350 | else |
7b81dfbb AJ |
7351 | /* Don't do the adjustment for x86-64, as there |
7352 | the pcrel addressing is relative to the _next_ | |
7353 | insn, and that is taken care of in other code. */ | |
d6ab8113 | 7354 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
2bbd9c25 | 7355 | } |
02a86693 L |
7356 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, |
7357 | size, i.op[n].disps, pcrel, | |
7358 | reloc_type); | |
7359 | /* Check for "call/jmp *mem", "mov mem, %reg", | |
7360 | "test %reg, mem" and "binop mem, %reg" where binop | |
7361 | is one of adc, add, and, cmp, or, sbb, sub, xor | |
0cb4071e L |
7362 | instructions. Always generate R_386_GOT32X for |
7363 | "sym*GOT" operand in 32-bit mode. */ | |
7364 | if ((generate_relax_relocations | |
7365 | || (!object_64bit | |
7366 | && i.rm.mode == 0 | |
7367 | && i.rm.regmem == 5)) | |
7368 | && (i.rm.mode == 2 | |
7369 | || (i.rm.mode == 0 && i.rm.regmem == 5)) | |
02a86693 L |
7370 | && ((i.operands == 1 |
7371 | && i.tm.base_opcode == 0xff | |
7372 | && (i.rm.reg == 2 || i.rm.reg == 4)) | |
7373 | || (i.operands == 2 | |
7374 | && (i.tm.base_opcode == 0x8b | |
7375 | || i.tm.base_opcode == 0x85 | |
7376 | || (i.tm.base_opcode & 0xc7) == 0x03)))) | |
7377 | { | |
7378 | if (object_64bit) | |
7379 | { | |
7380 | fixP->fx_tcbit = i.rex != 0; | |
7381 | if (i.base_reg | |
7382 | && (i.base_reg->reg_num == RegRip | |
7383 | || i.base_reg->reg_num == RegEip)) | |
7384 | fixP->fx_tcbit2 = 1; | |
7385 | } | |
7386 | else | |
7387 | fixP->fx_tcbit2 = 1; | |
7388 | } | |
29b0f896 AM |
7389 | } |
7390 | } | |
7391 | } | |
7392 | } | |
252b5132 | 7393 | |
29b0f896 | 7394 | static void |
64e74474 | 7395 | output_imm (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
7396 | { |
7397 | char *p; | |
7398 | unsigned int n; | |
252b5132 | 7399 | |
29b0f896 AM |
7400 | for (n = 0; n < i.operands; n++) |
7401 | { | |
43234a1e L |
7402 | /* Skip SAE/RC Imm operand in EVEX. They are already handled. */ |
7403 | if (i.rounding && (int) n == i.rounding->operand) | |
7404 | continue; | |
7405 | ||
40fb9820 | 7406 | if (operand_type_check (i.types[n], imm)) |
29b0f896 AM |
7407 | { |
7408 | if (i.op[n].imms->X_op == O_constant) | |
7409 | { | |
e205caa7 | 7410 | int size = imm_size (n); |
29b0f896 | 7411 | offsetT val; |
b4cac588 | 7412 | |
29b0f896 AM |
7413 | val = offset_in_range (i.op[n].imms->X_add_number, |
7414 | size); | |
7415 | p = frag_more (size); | |
7416 | md_number_to_chars (p, val, size); | |
7417 | } | |
7418 | else | |
7419 | { | |
7420 | /* Not absolute_section. | |
7421 | Need a 32-bit fixup (don't support 8bit | |
7422 | non-absolute imms). Try to support other | |
7423 | sizes ... */ | |
f86103b7 | 7424 | enum bfd_reloc_code_real reloc_type; |
e205caa7 L |
7425 | int size = imm_size (n); |
7426 | int sign; | |
29b0f896 | 7427 | |
40fb9820 | 7428 | if (i.types[n].bitfield.imm32s |
a7d61044 | 7429 | && (i.suffix == QWORD_MNEM_SUFFIX |
40fb9820 | 7430 | || (!i.suffix && i.tm.opcode_modifier.no_lsuf))) |
29b0f896 | 7431 | sign = 1; |
e205caa7 L |
7432 | else |
7433 | sign = 0; | |
520dc8e8 | 7434 | |
29b0f896 | 7435 | p = frag_more (size); |
d258b828 | 7436 | reloc_type = reloc (size, 0, sign, i.reloc[n]); |
f86103b7 | 7437 | |
2bbd9c25 JJ |
7438 | /* This is tough to explain. We end up with this one if we |
7439 | * have operands that look like | |
7440 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to | |
7441 | * obtain the absolute address of the GOT, and it is strongly | |
7442 | * preferable from a performance point of view to avoid using | |
7443 | * a runtime relocation for this. The actual sequence of | |
7444 | * instructions often look something like: | |
7445 | * | |
7446 | * call .L66 | |
7447 | * .L66: | |
7448 | * popl %ebx | |
7449 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
7450 | * | |
7451 | * The call and pop essentially return the absolute address | |
7452 | * of the label .L66 and store it in %ebx. The linker itself | |
7453 | * will ultimately change the first operand of the addl so | |
7454 | * that %ebx points to the GOT, but to keep things simple, the | |
7455 | * .o file must have this operand set so that it generates not | |
7456 | * the absolute address of .L66, but the absolute address of | |
7457 | * itself. This allows the linker itself simply treat a GOTPC | |
7458 | * relocation as asking for a pcrel offset to the GOT to be | |
7459 | * added in, and the addend of the relocation is stored in the | |
7460 | * operand field for the instruction itself. | |
7461 | * | |
7462 | * Our job here is to fix the operand so that it would add | |
7463 | * the correct offset so that %ebx would point to itself. The | |
7464 | * thing that is tricky is that .-.L66 will point to the | |
7465 | * beginning of the instruction, so we need to further modify | |
7466 | * the operand so that it will point to itself. There are | |
7467 | * other cases where you have something like: | |
7468 | * | |
7469 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
7470 | * | |
7471 | * and here no correction would be required. Internally in | |
7472 | * the assembler we treat operands of this form as not being | |
7473 | * pcrel since the '.' is explicitly mentioned, and I wonder | |
7474 | * whether it would simplify matters to do it this way. Who | |
7475 | * knows. In earlier versions of the PIC patches, the | |
7476 | * pcrel_adjust field was used to store the correction, but | |
7477 | * since the expression is not pcrel, I felt it would be | |
7478 | * confusing to do it this way. */ | |
7479 | ||
d6ab8113 | 7480 | if ((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
7481 | || reloc_type == BFD_RELOC_X86_64_32S |
7482 | || reloc_type == BFD_RELOC_64) | |
29b0f896 AM |
7483 | && GOT_symbol |
7484 | && GOT_symbol == i.op[n].imms->X_add_symbol | |
7485 | && (i.op[n].imms->X_op == O_symbol | |
7486 | || (i.op[n].imms->X_op == O_add | |
7487 | && ((symbol_get_value_expression | |
7488 | (i.op[n].imms->X_op_symbol)->X_op) | |
7489 | == O_subtract)))) | |
7490 | { | |
2bbd9c25 JJ |
7491 | offsetT add; |
7492 | ||
7493 | if (insn_start_frag == frag_now) | |
7494 | add = (p - frag_now->fr_literal) - insn_start_off; | |
7495 | else | |
7496 | { | |
7497 | fragS *fr; | |
7498 | ||
7499 | add = insn_start_frag->fr_fix - insn_start_off; | |
7500 | for (fr = insn_start_frag->fr_next; | |
7501 | fr && fr != frag_now; fr = fr->fr_next) | |
7502 | add += fr->fr_fix; | |
7503 | add += p - frag_now->fr_literal; | |
7504 | } | |
7505 | ||
4fa24527 | 7506 | if (!object_64bit) |
d6ab8113 | 7507 | reloc_type = BFD_RELOC_386_GOTPC; |
7b81dfbb | 7508 | else if (size == 4) |
d6ab8113 | 7509 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
7b81dfbb AJ |
7510 | else if (size == 8) |
7511 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
2bbd9c25 | 7512 | i.op[n].imms->X_add_number += add; |
29b0f896 | 7513 | } |
29b0f896 AM |
7514 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
7515 | i.op[n].imms, 0, reloc_type); | |
7516 | } | |
7517 | } | |
7518 | } | |
252b5132 RH |
7519 | } |
7520 | \f | |
d182319b JB |
7521 | /* x86_cons_fix_new is called via the expression parsing code when a |
7522 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
d182319b JB |
7523 | static int cons_sign = -1; |
7524 | ||
7525 | void | |
e3bb37b5 | 7526 | x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, |
62ebcb5c | 7527 | expressionS *exp, bfd_reloc_code_real_type r) |
d182319b | 7528 | { |
d258b828 | 7529 | r = reloc (len, 0, cons_sign, r); |
d182319b JB |
7530 | |
7531 | #ifdef TE_PE | |
7532 | if (exp->X_op == O_secrel) | |
7533 | { | |
7534 | exp->X_op = O_symbol; | |
7535 | r = BFD_RELOC_32_SECREL; | |
7536 | } | |
7537 | #endif | |
7538 | ||
7539 | fix_new_exp (frag, off, len, exp, 0, r); | |
7540 | } | |
7541 | ||
357d1bd8 L |
7542 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
7543 | purpose of the `.dc.a' internal pseudo-op. */ | |
7544 | ||
7545 | int | |
7546 | x86_address_bytes (void) | |
7547 | { | |
7548 | if ((stdoutput->arch_info->mach & bfd_mach_x64_32)) | |
7549 | return 4; | |
7550 | return stdoutput->arch_info->bits_per_address / 8; | |
7551 | } | |
7552 | ||
d382c579 TG |
7553 | #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \ |
7554 | || defined (LEX_AT) | |
d258b828 | 7555 | # define lex_got(reloc, adjust, types) NULL |
718ddfc0 | 7556 | #else |
f3c180ae AM |
7557 | /* Parse operands of the form |
7558 | <symbol>@GOTOFF+<nnn> | |
7559 | and similar .plt or .got references. | |
7560 | ||
7561 | If we find one, set up the correct relocation in RELOC and copy the | |
7562 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
7563 | parsing by the calling routine. Return this buffer, and if ADJUST | |
7564 | is non-null set it to the length of the string we removed from the | |
7565 | input line. Otherwise return NULL. */ | |
7566 | static char * | |
91d6fa6a | 7567 | lex_got (enum bfd_reloc_code_real *rel, |
64e74474 | 7568 | int *adjust, |
d258b828 | 7569 | i386_operand_type *types) |
f3c180ae | 7570 | { |
7b81dfbb AJ |
7571 | /* Some of the relocations depend on the size of what field is to |
7572 | be relocated. But in our callers i386_immediate and i386_displacement | |
7573 | we don't yet know the operand size (this will be set by insn | |
7574 | matching). Hence we record the word32 relocation here, | |
7575 | and adjust the reloc according to the real size in reloc(). */ | |
f3c180ae AM |
7576 | static const struct { |
7577 | const char *str; | |
cff8d58a | 7578 | int len; |
4fa24527 | 7579 | const enum bfd_reloc_code_real rel[2]; |
40fb9820 | 7580 | const i386_operand_type types64; |
f3c180ae | 7581 | } gotrel[] = { |
8ce3d284 | 7582 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
7583 | { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32, |
7584 | BFD_RELOC_SIZE32 }, | |
7585 | OPERAND_TYPE_IMM32_64 }, | |
8ce3d284 | 7586 | #endif |
cff8d58a L |
7587 | { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real, |
7588 | BFD_RELOC_X86_64_PLTOFF64 }, | |
40fb9820 | 7589 | OPERAND_TYPE_IMM64 }, |
cff8d58a L |
7590 | { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32, |
7591 | BFD_RELOC_X86_64_PLT32 }, | |
40fb9820 | 7592 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
7593 | { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real, |
7594 | BFD_RELOC_X86_64_GOTPLT64 }, | |
40fb9820 | 7595 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
7596 | { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF, |
7597 | BFD_RELOC_X86_64_GOTOFF64 }, | |
40fb9820 | 7598 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
7599 | { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real, |
7600 | BFD_RELOC_X86_64_GOTPCREL }, | |
40fb9820 | 7601 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
7602 | { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD, |
7603 | BFD_RELOC_X86_64_TLSGD }, | |
40fb9820 | 7604 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
7605 | { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM, |
7606 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 7607 | OPERAND_TYPE_NONE }, |
cff8d58a L |
7608 | { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real, |
7609 | BFD_RELOC_X86_64_TLSLD }, | |
40fb9820 | 7610 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
7611 | { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32, |
7612 | BFD_RELOC_X86_64_GOTTPOFF }, | |
40fb9820 | 7613 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
7614 | { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32, |
7615 | BFD_RELOC_X86_64_TPOFF32 }, | |
40fb9820 | 7616 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
7617 | { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE, |
7618 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 7619 | OPERAND_TYPE_NONE }, |
cff8d58a L |
7620 | { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32, |
7621 | BFD_RELOC_X86_64_DTPOFF32 }, | |
40fb9820 | 7622 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
7623 | { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE, |
7624 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 7625 | OPERAND_TYPE_NONE }, |
cff8d58a L |
7626 | { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE, |
7627 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 7628 | OPERAND_TYPE_NONE }, |
cff8d58a L |
7629 | { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32, |
7630 | BFD_RELOC_X86_64_GOT32 }, | |
40fb9820 | 7631 | OPERAND_TYPE_IMM32_32S_64_DISP32 }, |
cff8d58a L |
7632 | { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC, |
7633 | BFD_RELOC_X86_64_GOTPC32_TLSDESC }, | |
40fb9820 | 7634 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
7635 | { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL, |
7636 | BFD_RELOC_X86_64_TLSDESC_CALL }, | |
40fb9820 | 7637 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
f3c180ae AM |
7638 | }; |
7639 | char *cp; | |
7640 | unsigned int j; | |
7641 | ||
d382c579 | 7642 | #if defined (OBJ_MAYBE_ELF) |
718ddfc0 JB |
7643 | if (!IS_ELF) |
7644 | return NULL; | |
d382c579 | 7645 | #endif |
718ddfc0 | 7646 | |
f3c180ae | 7647 | for (cp = input_line_pointer; *cp != '@'; cp++) |
67c11a9b | 7648 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') |
f3c180ae AM |
7649 | return NULL; |
7650 | ||
47465058 | 7651 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) |
f3c180ae | 7652 | { |
cff8d58a | 7653 | int len = gotrel[j].len; |
28f81592 | 7654 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae | 7655 | { |
4fa24527 | 7656 | if (gotrel[j].rel[object_64bit] != 0) |
f3c180ae | 7657 | { |
28f81592 AM |
7658 | int first, second; |
7659 | char *tmpbuf, *past_reloc; | |
f3c180ae | 7660 | |
91d6fa6a | 7661 | *rel = gotrel[j].rel[object_64bit]; |
f3c180ae | 7662 | |
3956db08 JB |
7663 | if (types) |
7664 | { | |
7665 | if (flag_code != CODE_64BIT) | |
40fb9820 L |
7666 | { |
7667 | types->bitfield.imm32 = 1; | |
7668 | types->bitfield.disp32 = 1; | |
7669 | } | |
3956db08 JB |
7670 | else |
7671 | *types = gotrel[j].types64; | |
7672 | } | |
7673 | ||
8fd4256d | 7674 | if (j != 0 && GOT_symbol == NULL) |
f3c180ae AM |
7675 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); |
7676 | ||
28f81592 | 7677 | /* The length of the first part of our input line. */ |
f3c180ae | 7678 | first = cp - input_line_pointer; |
28f81592 AM |
7679 | |
7680 | /* The second part goes from after the reloc token until | |
67c11a9b | 7681 | (and including) an end_of_line char or comma. */ |
28f81592 | 7682 | past_reloc = cp + 1 + len; |
67c11a9b AM |
7683 | cp = past_reloc; |
7684 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
7685 | ++cp; | |
7686 | second = cp + 1 - past_reloc; | |
28f81592 AM |
7687 | |
7688 | /* Allocate and copy string. The trailing NUL shouldn't | |
7689 | be necessary, but be safe. */ | |
add39d23 | 7690 | tmpbuf = XNEWVEC (char, first + second + 2); |
f3c180ae | 7691 | memcpy (tmpbuf, input_line_pointer, first); |
0787a12d AM |
7692 | if (second != 0 && *past_reloc != ' ') |
7693 | /* Replace the relocation token with ' ', so that | |
7694 | errors like foo@GOTOFF1 will be detected. */ | |
7695 | tmpbuf[first++] = ' '; | |
af89796a L |
7696 | else |
7697 | /* Increment length by 1 if the relocation token is | |
7698 | removed. */ | |
7699 | len++; | |
7700 | if (adjust) | |
7701 | *adjust = len; | |
0787a12d AM |
7702 | memcpy (tmpbuf + first, past_reloc, second); |
7703 | tmpbuf[first + second] = '\0'; | |
f3c180ae AM |
7704 | return tmpbuf; |
7705 | } | |
7706 | ||
4fa24527 JB |
7707 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
7708 | gotrel[j].str, 1 << (5 + object_64bit)); | |
f3c180ae AM |
7709 | return NULL; |
7710 | } | |
7711 | } | |
7712 | ||
7713 | /* Might be a symbol version string. Don't as_bad here. */ | |
7714 | return NULL; | |
7715 | } | |
4e4f7c87 | 7716 | #endif |
f3c180ae | 7717 | |
a988325c NC |
7718 | #ifdef TE_PE |
7719 | #ifdef lex_got | |
7720 | #undef lex_got | |
7721 | #endif | |
7722 | /* Parse operands of the form | |
7723 | <symbol>@SECREL32+<nnn> | |
7724 | ||
7725 | If we find one, set up the correct relocation in RELOC and copy the | |
7726 | input string, minus the `@SECREL32' into a malloc'd buffer for | |
7727 | parsing by the calling routine. Return this buffer, and if ADJUST | |
7728 | is non-null set it to the length of the string we removed from the | |
34bca508 L |
7729 | input line. Otherwise return NULL. |
7730 | ||
a988325c NC |
7731 | This function is copied from the ELF version above adjusted for PE targets. */ |
7732 | ||
7733 | static char * | |
7734 | lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED, | |
7735 | int *adjust ATTRIBUTE_UNUSED, | |
d258b828 | 7736 | i386_operand_type *types) |
a988325c NC |
7737 | { |
7738 | static const struct | |
7739 | { | |
7740 | const char *str; | |
7741 | int len; | |
7742 | const enum bfd_reloc_code_real rel[2]; | |
7743 | const i386_operand_type types64; | |
7744 | } | |
7745 | gotrel[] = | |
7746 | { | |
7747 | { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL, | |
7748 | BFD_RELOC_32_SECREL }, | |
7749 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, | |
7750 | }; | |
7751 | ||
7752 | char *cp; | |
7753 | unsigned j; | |
7754 | ||
7755 | for (cp = input_line_pointer; *cp != '@'; cp++) | |
7756 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') | |
7757 | return NULL; | |
7758 | ||
7759 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) | |
7760 | { | |
7761 | int len = gotrel[j].len; | |
7762 | ||
7763 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) | |
7764 | { | |
7765 | if (gotrel[j].rel[object_64bit] != 0) | |
7766 | { | |
7767 | int first, second; | |
7768 | char *tmpbuf, *past_reloc; | |
7769 | ||
7770 | *rel = gotrel[j].rel[object_64bit]; | |
7771 | if (adjust) | |
7772 | *adjust = len; | |
7773 | ||
7774 | if (types) | |
7775 | { | |
7776 | if (flag_code != CODE_64BIT) | |
7777 | { | |
7778 | types->bitfield.imm32 = 1; | |
7779 | types->bitfield.disp32 = 1; | |
7780 | } | |
7781 | else | |
7782 | *types = gotrel[j].types64; | |
7783 | } | |
7784 | ||
7785 | /* The length of the first part of our input line. */ | |
7786 | first = cp - input_line_pointer; | |
7787 | ||
7788 | /* The second part goes from after the reloc token until | |
7789 | (and including) an end_of_line char or comma. */ | |
7790 | past_reloc = cp + 1 + len; | |
7791 | cp = past_reloc; | |
7792 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
7793 | ++cp; | |
7794 | second = cp + 1 - past_reloc; | |
7795 | ||
7796 | /* Allocate and copy string. The trailing NUL shouldn't | |
7797 | be necessary, but be safe. */ | |
add39d23 | 7798 | tmpbuf = XNEWVEC (char, first + second + 2); |
a988325c NC |
7799 | memcpy (tmpbuf, input_line_pointer, first); |
7800 | if (second != 0 && *past_reloc != ' ') | |
7801 | /* Replace the relocation token with ' ', so that | |
7802 | errors like foo@SECLREL321 will be detected. */ | |
7803 | tmpbuf[first++] = ' '; | |
7804 | memcpy (tmpbuf + first, past_reloc, second); | |
7805 | tmpbuf[first + second] = '\0'; | |
7806 | return tmpbuf; | |
7807 | } | |
7808 | ||
7809 | as_bad (_("@%s reloc is not supported with %d-bit output format"), | |
7810 | gotrel[j].str, 1 << (5 + object_64bit)); | |
7811 | return NULL; | |
7812 | } | |
7813 | } | |
7814 | ||
7815 | /* Might be a symbol version string. Don't as_bad here. */ | |
7816 | return NULL; | |
7817 | } | |
7818 | ||
7819 | #endif /* TE_PE */ | |
7820 | ||
62ebcb5c | 7821 | bfd_reloc_code_real_type |
e3bb37b5 | 7822 | x86_cons (expressionS *exp, int size) |
f3c180ae | 7823 | { |
62ebcb5c AM |
7824 | bfd_reloc_code_real_type got_reloc = NO_RELOC; |
7825 | ||
ee86248c JB |
7826 | intel_syntax = -intel_syntax; |
7827 | ||
3c7b9c2c | 7828 | exp->X_md = 0; |
4fa24527 | 7829 | if (size == 4 || (object_64bit && size == 8)) |
f3c180ae AM |
7830 | { |
7831 | /* Handle @GOTOFF and the like in an expression. */ | |
7832 | char *save; | |
7833 | char *gotfree_input_line; | |
4a57f2cf | 7834 | int adjust = 0; |
f3c180ae AM |
7835 | |
7836 | save = input_line_pointer; | |
d258b828 | 7837 | gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); |
f3c180ae AM |
7838 | if (gotfree_input_line) |
7839 | input_line_pointer = gotfree_input_line; | |
7840 | ||
7841 | expression (exp); | |
7842 | ||
7843 | if (gotfree_input_line) | |
7844 | { | |
7845 | /* expression () has merrily parsed up to the end of line, | |
7846 | or a comma - in the wrong buffer. Transfer how far | |
7847 | input_line_pointer has moved to the right buffer. */ | |
7848 | input_line_pointer = (save | |
7849 | + (input_line_pointer - gotfree_input_line) | |
7850 | + adjust); | |
7851 | free (gotfree_input_line); | |
3992d3b7 AM |
7852 | if (exp->X_op == O_constant |
7853 | || exp->X_op == O_absent | |
7854 | || exp->X_op == O_illegal | |
0398aac5 | 7855 | || exp->X_op == O_register |
3992d3b7 AM |
7856 | || exp->X_op == O_big) |
7857 | { | |
7858 | char c = *input_line_pointer; | |
7859 | *input_line_pointer = 0; | |
7860 | as_bad (_("missing or invalid expression `%s'"), save); | |
7861 | *input_line_pointer = c; | |
7862 | } | |
f3c180ae AM |
7863 | } |
7864 | } | |
7865 | else | |
7866 | expression (exp); | |
ee86248c JB |
7867 | |
7868 | intel_syntax = -intel_syntax; | |
7869 | ||
7870 | if (intel_syntax) | |
7871 | i386_intel_simplify (exp); | |
62ebcb5c AM |
7872 | |
7873 | return got_reloc; | |
f3c180ae | 7874 | } |
f3c180ae | 7875 | |
9f32dd5b L |
7876 | static void |
7877 | signed_cons (int size) | |
6482c264 | 7878 | { |
d182319b JB |
7879 | if (flag_code == CODE_64BIT) |
7880 | cons_sign = 1; | |
7881 | cons (size); | |
7882 | cons_sign = -1; | |
6482c264 NC |
7883 | } |
7884 | ||
d182319b | 7885 | #ifdef TE_PE |
6482c264 | 7886 | static void |
7016a5d5 | 7887 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
6482c264 NC |
7888 | { |
7889 | expressionS exp; | |
7890 | ||
7891 | do | |
7892 | { | |
7893 | expression (&exp); | |
7894 | if (exp.X_op == O_symbol) | |
7895 | exp.X_op = O_secrel; | |
7896 | ||
7897 | emit_expr (&exp, 4); | |
7898 | } | |
7899 | while (*input_line_pointer++ == ','); | |
7900 | ||
7901 | input_line_pointer--; | |
7902 | demand_empty_rest_of_line (); | |
7903 | } | |
6482c264 NC |
7904 | #endif |
7905 | ||
43234a1e L |
7906 | /* Handle Vector operations. */ |
7907 | ||
7908 | static char * | |
7909 | check_VecOperations (char *op_string, char *op_end) | |
7910 | { | |
7911 | const reg_entry *mask; | |
7912 | const char *saved; | |
7913 | char *end_op; | |
7914 | ||
7915 | while (*op_string | |
7916 | && (op_end == NULL || op_string < op_end)) | |
7917 | { | |
7918 | saved = op_string; | |
7919 | if (*op_string == '{') | |
7920 | { | |
7921 | op_string++; | |
7922 | ||
7923 | /* Check broadcasts. */ | |
7924 | if (strncmp (op_string, "1to", 3) == 0) | |
7925 | { | |
7926 | int bcst_type; | |
7927 | ||
7928 | if (i.broadcast) | |
7929 | goto duplicated_vec_op; | |
7930 | ||
7931 | op_string += 3; | |
7932 | if (*op_string == '8') | |
7933 | bcst_type = BROADCAST_1TO8; | |
b28d1bda IT |
7934 | else if (*op_string == '4') |
7935 | bcst_type = BROADCAST_1TO4; | |
7936 | else if (*op_string == '2') | |
7937 | bcst_type = BROADCAST_1TO2; | |
43234a1e L |
7938 | else if (*op_string == '1' |
7939 | && *(op_string+1) == '6') | |
7940 | { | |
7941 | bcst_type = BROADCAST_1TO16; | |
7942 | op_string++; | |
7943 | } | |
7944 | else | |
7945 | { | |
7946 | as_bad (_("Unsupported broadcast: `%s'"), saved); | |
7947 | return NULL; | |
7948 | } | |
7949 | op_string++; | |
7950 | ||
7951 | broadcast_op.type = bcst_type; | |
7952 | broadcast_op.operand = this_operand; | |
7953 | i.broadcast = &broadcast_op; | |
7954 | } | |
7955 | /* Check masking operation. */ | |
7956 | else if ((mask = parse_register (op_string, &end_op)) != NULL) | |
7957 | { | |
7958 | /* k0 can't be used for write mask. */ | |
7959 | if (mask->reg_num == 0) | |
7960 | { | |
7961 | as_bad (_("`%s' can't be used for write mask"), | |
7962 | op_string); | |
7963 | return NULL; | |
7964 | } | |
7965 | ||
7966 | if (!i.mask) | |
7967 | { | |
7968 | mask_op.mask = mask; | |
7969 | mask_op.zeroing = 0; | |
7970 | mask_op.operand = this_operand; | |
7971 | i.mask = &mask_op; | |
7972 | } | |
7973 | else | |
7974 | { | |
7975 | if (i.mask->mask) | |
7976 | goto duplicated_vec_op; | |
7977 | ||
7978 | i.mask->mask = mask; | |
7979 | ||
7980 | /* Only "{z}" is allowed here. No need to check | |
7981 | zeroing mask explicitly. */ | |
7982 | if (i.mask->operand != this_operand) | |
7983 | { | |
7984 | as_bad (_("invalid write mask `%s'"), saved); | |
7985 | return NULL; | |
7986 | } | |
7987 | } | |
7988 | ||
7989 | op_string = end_op; | |
7990 | } | |
7991 | /* Check zeroing-flag for masking operation. */ | |
7992 | else if (*op_string == 'z') | |
7993 | { | |
7994 | if (!i.mask) | |
7995 | { | |
7996 | mask_op.mask = NULL; | |
7997 | mask_op.zeroing = 1; | |
7998 | mask_op.operand = this_operand; | |
7999 | i.mask = &mask_op; | |
8000 | } | |
8001 | else | |
8002 | { | |
8003 | if (i.mask->zeroing) | |
8004 | { | |
8005 | duplicated_vec_op: | |
8006 | as_bad (_("duplicated `%s'"), saved); | |
8007 | return NULL; | |
8008 | } | |
8009 | ||
8010 | i.mask->zeroing = 1; | |
8011 | ||
8012 | /* Only "{%k}" is allowed here. No need to check mask | |
8013 | register explicitly. */ | |
8014 | if (i.mask->operand != this_operand) | |
8015 | { | |
8016 | as_bad (_("invalid zeroing-masking `%s'"), | |
8017 | saved); | |
8018 | return NULL; | |
8019 | } | |
8020 | } | |
8021 | ||
8022 | op_string++; | |
8023 | } | |
8024 | else | |
8025 | goto unknown_vec_op; | |
8026 | ||
8027 | if (*op_string != '}') | |
8028 | { | |
8029 | as_bad (_("missing `}' in `%s'"), saved); | |
8030 | return NULL; | |
8031 | } | |
8032 | op_string++; | |
8033 | continue; | |
8034 | } | |
8035 | unknown_vec_op: | |
8036 | /* We don't know this one. */ | |
8037 | as_bad (_("unknown vector operation: `%s'"), saved); | |
8038 | return NULL; | |
8039 | } | |
8040 | ||
8041 | return op_string; | |
8042 | } | |
8043 | ||
252b5132 | 8044 | static int |
70e41ade | 8045 | i386_immediate (char *imm_start) |
252b5132 RH |
8046 | { |
8047 | char *save_input_line_pointer; | |
f3c180ae | 8048 | char *gotfree_input_line; |
252b5132 | 8049 | segT exp_seg = 0; |
47926f60 | 8050 | expressionS *exp; |
40fb9820 L |
8051 | i386_operand_type types; |
8052 | ||
0dfbf9d7 | 8053 | operand_type_set (&types, ~0); |
252b5132 RH |
8054 | |
8055 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
8056 | { | |
31b2323c L |
8057 | as_bad (_("at most %d immediate operands are allowed"), |
8058 | MAX_IMMEDIATE_OPERANDS); | |
252b5132 RH |
8059 | return 0; |
8060 | } | |
8061 | ||
8062 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 8063 | i.op[this_operand].imms = exp; |
252b5132 RH |
8064 | |
8065 | if (is_space_char (*imm_start)) | |
8066 | ++imm_start; | |
8067 | ||
8068 | save_input_line_pointer = input_line_pointer; | |
8069 | input_line_pointer = imm_start; | |
8070 | ||
d258b828 | 8071 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
8072 | if (gotfree_input_line) |
8073 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
8074 | |
8075 | exp_seg = expression (exp); | |
8076 | ||
83183c0c | 8077 | SKIP_WHITESPACE (); |
43234a1e L |
8078 | |
8079 | /* Handle vector operations. */ | |
8080 | if (*input_line_pointer == '{') | |
8081 | { | |
8082 | input_line_pointer = check_VecOperations (input_line_pointer, | |
8083 | NULL); | |
8084 | if (input_line_pointer == NULL) | |
8085 | return 0; | |
8086 | } | |
8087 | ||
252b5132 | 8088 | if (*input_line_pointer) |
f3c180ae | 8089 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
8090 | |
8091 | input_line_pointer = save_input_line_pointer; | |
f3c180ae | 8092 | if (gotfree_input_line) |
ee86248c JB |
8093 | { |
8094 | free (gotfree_input_line); | |
8095 | ||
8096 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
8097 | exp->X_op = O_illegal; | |
8098 | } | |
8099 | ||
8100 | return i386_finalize_immediate (exp_seg, exp, types, imm_start); | |
8101 | } | |
252b5132 | 8102 | |
ee86248c JB |
8103 | static int |
8104 | i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
8105 | i386_operand_type types, const char *imm_start) | |
8106 | { | |
8107 | if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big) | |
252b5132 | 8108 | { |
313c53d1 L |
8109 | if (imm_start) |
8110 | as_bad (_("missing or invalid immediate expression `%s'"), | |
8111 | imm_start); | |
3992d3b7 | 8112 | return 0; |
252b5132 | 8113 | } |
3e73aa7c | 8114 | else if (exp->X_op == O_constant) |
252b5132 | 8115 | { |
47926f60 | 8116 | /* Size it properly later. */ |
40fb9820 | 8117 | i.types[this_operand].bitfield.imm64 = 1; |
13f864ae L |
8118 | /* If not 64bit, sign extend val. */ |
8119 | if (flag_code != CODE_64BIT | |
4eed87de AM |
8120 | && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) |
8121 | exp->X_add_number | |
8122 | = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
252b5132 | 8123 | } |
4c63da97 | 8124 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
f86103b7 | 8125 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 8126 | && exp_seg != absolute_section |
47926f60 | 8127 | && exp_seg != text_section |
24eab124 AM |
8128 | && exp_seg != data_section |
8129 | && exp_seg != bss_section | |
8130 | && exp_seg != undefined_section | |
f86103b7 | 8131 | && !bfd_is_com_section (exp_seg)) |
252b5132 | 8132 | { |
d0b47220 | 8133 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
252b5132 RH |
8134 | return 0; |
8135 | } | |
8136 | #endif | |
a841bdf5 | 8137 | else if (!intel_syntax && exp_seg == reg_section) |
bb8f5920 | 8138 | { |
313c53d1 L |
8139 | if (imm_start) |
8140 | as_bad (_("illegal immediate register operand %s"), imm_start); | |
bb8f5920 L |
8141 | return 0; |
8142 | } | |
252b5132 RH |
8143 | else |
8144 | { | |
8145 | /* This is an address. The size of the address will be | |
24eab124 | 8146 | determined later, depending on destination register, |
3e73aa7c | 8147 | suffix, or the default for the section. */ |
40fb9820 L |
8148 | i.types[this_operand].bitfield.imm8 = 1; |
8149 | i.types[this_operand].bitfield.imm16 = 1; | |
8150 | i.types[this_operand].bitfield.imm32 = 1; | |
8151 | i.types[this_operand].bitfield.imm32s = 1; | |
8152 | i.types[this_operand].bitfield.imm64 = 1; | |
c6fb90c8 L |
8153 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
8154 | types); | |
252b5132 RH |
8155 | } |
8156 | ||
8157 | return 1; | |
8158 | } | |
8159 | ||
551c1ca1 | 8160 | static char * |
e3bb37b5 | 8161 | i386_scale (char *scale) |
252b5132 | 8162 | { |
551c1ca1 AM |
8163 | offsetT val; |
8164 | char *save = input_line_pointer; | |
252b5132 | 8165 | |
551c1ca1 AM |
8166 | input_line_pointer = scale; |
8167 | val = get_absolute_expression (); | |
8168 | ||
8169 | switch (val) | |
252b5132 | 8170 | { |
551c1ca1 | 8171 | case 1: |
252b5132 RH |
8172 | i.log2_scale_factor = 0; |
8173 | break; | |
551c1ca1 | 8174 | case 2: |
252b5132 RH |
8175 | i.log2_scale_factor = 1; |
8176 | break; | |
551c1ca1 | 8177 | case 4: |
252b5132 RH |
8178 | i.log2_scale_factor = 2; |
8179 | break; | |
551c1ca1 | 8180 | case 8: |
252b5132 RH |
8181 | i.log2_scale_factor = 3; |
8182 | break; | |
8183 | default: | |
a724f0f4 JB |
8184 | { |
8185 | char sep = *input_line_pointer; | |
8186 | ||
8187 | *input_line_pointer = '\0'; | |
8188 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
8189 | scale); | |
8190 | *input_line_pointer = sep; | |
8191 | input_line_pointer = save; | |
8192 | return NULL; | |
8193 | } | |
252b5132 | 8194 | } |
29b0f896 | 8195 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
252b5132 RH |
8196 | { |
8197 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 8198 | 1 << i.log2_scale_factor); |
252b5132 | 8199 | i.log2_scale_factor = 0; |
252b5132 | 8200 | } |
551c1ca1 AM |
8201 | scale = input_line_pointer; |
8202 | input_line_pointer = save; | |
8203 | return scale; | |
252b5132 RH |
8204 | } |
8205 | ||
252b5132 | 8206 | static int |
e3bb37b5 | 8207 | i386_displacement (char *disp_start, char *disp_end) |
252b5132 | 8208 | { |
29b0f896 | 8209 | expressionS *exp; |
252b5132 RH |
8210 | segT exp_seg = 0; |
8211 | char *save_input_line_pointer; | |
f3c180ae | 8212 | char *gotfree_input_line; |
40fb9820 L |
8213 | int override; |
8214 | i386_operand_type bigdisp, types = anydisp; | |
3992d3b7 | 8215 | int ret; |
252b5132 | 8216 | |
31b2323c L |
8217 | if (i.disp_operands == MAX_MEMORY_OPERANDS) |
8218 | { | |
8219 | as_bad (_("at most %d displacement operands are allowed"), | |
8220 | MAX_MEMORY_OPERANDS); | |
8221 | return 0; | |
8222 | } | |
8223 | ||
0dfbf9d7 | 8224 | operand_type_set (&bigdisp, 0); |
40fb9820 L |
8225 | if ((i.types[this_operand].bitfield.jumpabsolute) |
8226 | || (!current_templates->start->opcode_modifier.jump | |
8227 | && !current_templates->start->opcode_modifier.jumpdword)) | |
e05278af | 8228 | { |
40fb9820 | 8229 | bigdisp.bitfield.disp32 = 1; |
e05278af | 8230 | override = (i.prefix[ADDR_PREFIX] != 0); |
40fb9820 L |
8231 | if (flag_code == CODE_64BIT) |
8232 | { | |
8233 | if (!override) | |
8234 | { | |
8235 | bigdisp.bitfield.disp32s = 1; | |
8236 | bigdisp.bitfield.disp64 = 1; | |
8237 | } | |
8238 | } | |
8239 | else if ((flag_code == CODE_16BIT) ^ override) | |
8240 | { | |
8241 | bigdisp.bitfield.disp32 = 0; | |
8242 | bigdisp.bitfield.disp16 = 1; | |
8243 | } | |
e05278af JB |
8244 | } |
8245 | else | |
8246 | { | |
8247 | /* For PC-relative branches, the width of the displacement | |
8248 | is dependent upon data size, not address size. */ | |
e05278af | 8249 | override = (i.prefix[DATA_PREFIX] != 0); |
40fb9820 L |
8250 | if (flag_code == CODE_64BIT) |
8251 | { | |
8252 | if (override || i.suffix == WORD_MNEM_SUFFIX) | |
8253 | bigdisp.bitfield.disp16 = 1; | |
8254 | else | |
8255 | { | |
8256 | bigdisp.bitfield.disp32 = 1; | |
8257 | bigdisp.bitfield.disp32s = 1; | |
8258 | } | |
8259 | } | |
8260 | else | |
e05278af JB |
8261 | { |
8262 | if (!override) | |
8263 | override = (i.suffix == (flag_code != CODE_16BIT | |
8264 | ? WORD_MNEM_SUFFIX | |
8265 | : LONG_MNEM_SUFFIX)); | |
40fb9820 L |
8266 | bigdisp.bitfield.disp32 = 1; |
8267 | if ((flag_code == CODE_16BIT) ^ override) | |
8268 | { | |
8269 | bigdisp.bitfield.disp32 = 0; | |
8270 | bigdisp.bitfield.disp16 = 1; | |
8271 | } | |
e05278af | 8272 | } |
e05278af | 8273 | } |
c6fb90c8 L |
8274 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
8275 | bigdisp); | |
252b5132 RH |
8276 | |
8277 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 8278 | i.op[this_operand].disps = exp; |
252b5132 RH |
8279 | i.disp_operands++; |
8280 | save_input_line_pointer = input_line_pointer; | |
8281 | input_line_pointer = disp_start; | |
8282 | END_STRING_AND_SAVE (disp_end); | |
8283 | ||
8284 | #ifndef GCC_ASM_O_HACK | |
8285 | #define GCC_ASM_O_HACK 0 | |
8286 | #endif | |
8287 | #if GCC_ASM_O_HACK | |
8288 | END_STRING_AND_SAVE (disp_end + 1); | |
40fb9820 | 8289 | if (i.types[this_operand].bitfield.baseIndex |
24eab124 | 8290 | && displacement_string_end[-1] == '+') |
252b5132 RH |
8291 | { |
8292 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
8293 | constraint within gcc asm statements. |
8294 | For instance: | |
8295 | ||
8296 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
8297 | __asm__ __volatile__ ( \ | |
8298 | "movw %w2,%0\n\t" \ | |
8299 | "movw %w1,2+%0\n\t" \ | |
8300 | "rorl $16,%1\n\t" \ | |
8301 | "movb %b1,4+%0\n\t" \ | |
8302 | "movb %4,5+%0\n\t" \ | |
8303 | "movb $0,6+%0\n\t" \ | |
8304 | "movb %h1,7+%0\n\t" \ | |
8305 | "rorl $16,%1" \ | |
8306 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
8307 | ||
8308 | This works great except that the output assembler ends | |
8309 | up looking a bit weird if it turns out that there is | |
8310 | no offset. You end up producing code that looks like: | |
8311 | ||
8312 | #APP | |
8313 | movw $235,(%eax) | |
8314 | movw %dx,2+(%eax) | |
8315 | rorl $16,%edx | |
8316 | movb %dl,4+(%eax) | |
8317 | movb $137,5+(%eax) | |
8318 | movb $0,6+(%eax) | |
8319 | movb %dh,7+(%eax) | |
8320 | rorl $16,%edx | |
8321 | #NO_APP | |
8322 | ||
47926f60 | 8323 | So here we provide the missing zero. */ |
24eab124 AM |
8324 | |
8325 | *displacement_string_end = '0'; | |
252b5132 RH |
8326 | } |
8327 | #endif | |
d258b828 | 8328 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
8329 | if (gotfree_input_line) |
8330 | input_line_pointer = gotfree_input_line; | |
252b5132 | 8331 | |
24eab124 | 8332 | exp_seg = expression (exp); |
252b5132 | 8333 | |
636c26b0 AM |
8334 | SKIP_WHITESPACE (); |
8335 | if (*input_line_pointer) | |
8336 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
8337 | #if GCC_ASM_O_HACK | |
8338 | RESTORE_END_STRING (disp_end + 1); | |
8339 | #endif | |
636c26b0 | 8340 | input_line_pointer = save_input_line_pointer; |
636c26b0 | 8341 | if (gotfree_input_line) |
ee86248c JB |
8342 | { |
8343 | free (gotfree_input_line); | |
8344 | ||
8345 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
8346 | exp->X_op = O_illegal; | |
8347 | } | |
8348 | ||
8349 | ret = i386_finalize_displacement (exp_seg, exp, types, disp_start); | |
8350 | ||
8351 | RESTORE_END_STRING (disp_end); | |
8352 | ||
8353 | return ret; | |
8354 | } | |
8355 | ||
8356 | static int | |
8357 | i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
8358 | i386_operand_type types, const char *disp_start) | |
8359 | { | |
8360 | i386_operand_type bigdisp; | |
8361 | int ret = 1; | |
636c26b0 | 8362 | |
24eab124 AM |
8363 | /* We do this to make sure that the section symbol is in |
8364 | the symbol table. We will ultimately change the relocation | |
47926f60 | 8365 | to be relative to the beginning of the section. */ |
1ae12ab7 | 8366 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
d6ab8113 JB |
8367 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
8368 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) | |
24eab124 | 8369 | { |
636c26b0 | 8370 | if (exp->X_op != O_symbol) |
3992d3b7 | 8371 | goto inv_disp; |
636c26b0 | 8372 | |
e5cb08ac | 8373 | if (S_IS_LOCAL (exp->X_add_symbol) |
c64efb4b L |
8374 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section |
8375 | && S_GET_SEGMENT (exp->X_add_symbol) != expr_section) | |
24eab124 | 8376 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); |
24eab124 AM |
8377 | exp->X_op = O_subtract; |
8378 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 | 8379 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
29b0f896 | 8380 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
d6ab8113 JB |
8381 | else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
8382 | i.reloc[this_operand] = BFD_RELOC_64; | |
23df1078 | 8383 | else |
29b0f896 | 8384 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 8385 | } |
252b5132 | 8386 | |
3992d3b7 AM |
8387 | else if (exp->X_op == O_absent |
8388 | || exp->X_op == O_illegal | |
ee86248c | 8389 | || exp->X_op == O_big) |
2daf4fd8 | 8390 | { |
3992d3b7 AM |
8391 | inv_disp: |
8392 | as_bad (_("missing or invalid displacement expression `%s'"), | |
2daf4fd8 | 8393 | disp_start); |
3992d3b7 | 8394 | ret = 0; |
2daf4fd8 AM |
8395 | } |
8396 | ||
0e1147d9 L |
8397 | else if (flag_code == CODE_64BIT |
8398 | && !i.prefix[ADDR_PREFIX] | |
8399 | && exp->X_op == O_constant) | |
8400 | { | |
8401 | /* Since displacement is signed extended to 64bit, don't allow | |
8402 | disp32 and turn off disp32s if they are out of range. */ | |
8403 | i.types[this_operand].bitfield.disp32 = 0; | |
8404 | if (!fits_in_signed_long (exp->X_add_number)) | |
8405 | { | |
8406 | i.types[this_operand].bitfield.disp32s = 0; | |
8407 | if (i.types[this_operand].bitfield.baseindex) | |
8408 | { | |
8409 | as_bad (_("0x%lx out range of signed 32bit displacement"), | |
8410 | (long) exp->X_add_number); | |
8411 | ret = 0; | |
8412 | } | |
8413 | } | |
8414 | } | |
8415 | ||
4c63da97 | 8416 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
3992d3b7 AM |
8417 | else if (exp->X_op != O_constant |
8418 | && OUTPUT_FLAVOR == bfd_target_aout_flavour | |
8419 | && exp_seg != absolute_section | |
8420 | && exp_seg != text_section | |
8421 | && exp_seg != data_section | |
8422 | && exp_seg != bss_section | |
8423 | && exp_seg != undefined_section | |
8424 | && !bfd_is_com_section (exp_seg)) | |
24eab124 | 8425 | { |
d0b47220 | 8426 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
3992d3b7 | 8427 | ret = 0; |
24eab124 | 8428 | } |
252b5132 | 8429 | #endif |
3956db08 | 8430 | |
40fb9820 L |
8431 | /* Check if this is a displacement only operand. */ |
8432 | bigdisp = i.types[this_operand]; | |
8433 | bigdisp.bitfield.disp8 = 0; | |
8434 | bigdisp.bitfield.disp16 = 0; | |
8435 | bigdisp.bitfield.disp32 = 0; | |
8436 | bigdisp.bitfield.disp32s = 0; | |
8437 | bigdisp.bitfield.disp64 = 0; | |
0dfbf9d7 | 8438 | if (operand_type_all_zero (&bigdisp)) |
c6fb90c8 L |
8439 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
8440 | types); | |
3956db08 | 8441 | |
3992d3b7 | 8442 | return ret; |
252b5132 RH |
8443 | } |
8444 | ||
eecb386c | 8445 | /* Make sure the memory operand we've been dealt is valid. |
47926f60 KH |
8446 | Return 1 on success, 0 on a failure. */ |
8447 | ||
252b5132 | 8448 | static int |
e3bb37b5 | 8449 | i386_index_check (const char *operand_string) |
252b5132 | 8450 | { |
fc0763e6 | 8451 | const char *kind = "base/index"; |
be05d201 L |
8452 | enum flag_code addr_mode; |
8453 | ||
8454 | if (i.prefix[ADDR_PREFIX]) | |
8455 | addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT; | |
8456 | else | |
8457 | { | |
8458 | addr_mode = flag_code; | |
8459 | ||
24eab124 | 8460 | #if INFER_ADDR_PREFIX |
be05d201 L |
8461 | if (i.mem_operands == 0) |
8462 | { | |
8463 | /* Infer address prefix from the first memory operand. */ | |
8464 | const reg_entry *addr_reg = i.base_reg; | |
8465 | ||
8466 | if (addr_reg == NULL) | |
8467 | addr_reg = i.index_reg; | |
eecb386c | 8468 | |
be05d201 L |
8469 | if (addr_reg) |
8470 | { | |
8471 | if (addr_reg->reg_num == RegEip | |
8472 | || addr_reg->reg_num == RegEiz | |
8473 | || addr_reg->reg_type.bitfield.reg32) | |
8474 | addr_mode = CODE_32BIT; | |
8475 | else if (flag_code != CODE_64BIT | |
8476 | && addr_reg->reg_type.bitfield.reg16) | |
8477 | addr_mode = CODE_16BIT; | |
8478 | ||
8479 | if (addr_mode != flag_code) | |
8480 | { | |
8481 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
8482 | i.prefixes += 1; | |
8483 | /* Change the size of any displacement too. At most one | |
8484 | of Disp16 or Disp32 is set. | |
8485 | FIXME. There doesn't seem to be any real need for | |
8486 | separate Disp16 and Disp32 flags. The same goes for | |
8487 | Imm16 and Imm32. Removing them would probably clean | |
8488 | up the code quite a lot. */ | |
8489 | if (flag_code != CODE_64BIT | |
8490 | && (i.types[this_operand].bitfield.disp16 | |
8491 | || i.types[this_operand].bitfield.disp32)) | |
8492 | i.types[this_operand] | |
8493 | = operand_type_xor (i.types[this_operand], disp16_32); | |
8494 | } | |
8495 | } | |
8496 | } | |
24eab124 | 8497 | #endif |
be05d201 L |
8498 | } |
8499 | ||
fc0763e6 JB |
8500 | if (current_templates->start->opcode_modifier.isstring |
8501 | && !current_templates->start->opcode_modifier.immext | |
8502 | && (current_templates->end[-1].opcode_modifier.isstring | |
8503 | || i.mem_operands)) | |
8504 | { | |
8505 | /* Memory operands of string insns are special in that they only allow | |
8506 | a single register (rDI, rSI, or rBX) as their memory address. */ | |
be05d201 L |
8507 | const reg_entry *expected_reg; |
8508 | static const char *di_si[][2] = | |
8509 | { | |
8510 | { "esi", "edi" }, | |
8511 | { "si", "di" }, | |
8512 | { "rsi", "rdi" } | |
8513 | }; | |
8514 | static const char *bx[] = { "ebx", "bx", "rbx" }; | |
fc0763e6 JB |
8515 | |
8516 | kind = "string address"; | |
8517 | ||
8325cc63 | 8518 | if (current_templates->start->opcode_modifier.repprefixok) |
fc0763e6 JB |
8519 | { |
8520 | i386_operand_type type = current_templates->end[-1].operand_types[0]; | |
8521 | ||
8522 | if (!type.bitfield.baseindex | |
8523 | || ((!i.mem_operands != !intel_syntax) | |
8524 | && current_templates->end[-1].operand_types[1] | |
8525 | .bitfield.baseindex)) | |
8526 | type = current_templates->end[-1].operand_types[1]; | |
be05d201 L |
8527 | expected_reg = hash_find (reg_hash, |
8528 | di_si[addr_mode][type.bitfield.esseg]); | |
8529 | ||
fc0763e6 JB |
8530 | } |
8531 | else | |
be05d201 | 8532 | expected_reg = hash_find (reg_hash, bx[addr_mode]); |
fc0763e6 | 8533 | |
be05d201 L |
8534 | if (i.base_reg != expected_reg |
8535 | || i.index_reg | |
fc0763e6 | 8536 | || operand_type_check (i.types[this_operand], disp)) |
fc0763e6 | 8537 | { |
be05d201 L |
8538 | /* The second memory operand must have the same size as |
8539 | the first one. */ | |
8540 | if (i.mem_operands | |
8541 | && i.base_reg | |
8542 | && !((addr_mode == CODE_64BIT | |
8543 | && i.base_reg->reg_type.bitfield.reg64) | |
8544 | || (addr_mode == CODE_32BIT | |
8545 | ? i.base_reg->reg_type.bitfield.reg32 | |
8546 | : i.base_reg->reg_type.bitfield.reg16))) | |
8547 | goto bad_address; | |
8548 | ||
fc0763e6 JB |
8549 | as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"), |
8550 | operand_string, | |
8551 | intel_syntax ? '[' : '(', | |
8552 | register_prefix, | |
be05d201 | 8553 | expected_reg->reg_name, |
fc0763e6 | 8554 | intel_syntax ? ']' : ')'); |
be05d201 | 8555 | return 1; |
fc0763e6 | 8556 | } |
be05d201 L |
8557 | else |
8558 | return 1; | |
8559 | ||
8560 | bad_address: | |
8561 | as_bad (_("`%s' is not a valid %s expression"), | |
8562 | operand_string, kind); | |
8563 | return 0; | |
3e73aa7c JH |
8564 | } |
8565 | else | |
8566 | { | |
be05d201 L |
8567 | if (addr_mode != CODE_16BIT) |
8568 | { | |
8569 | /* 32-bit/64-bit checks. */ | |
8570 | if ((i.base_reg | |
8571 | && (addr_mode == CODE_64BIT | |
8572 | ? !i.base_reg->reg_type.bitfield.reg64 | |
8573 | : !i.base_reg->reg_type.bitfield.reg32) | |
8574 | && (i.index_reg | |
8575 | || (i.base_reg->reg_num | |
8576 | != (addr_mode == CODE_64BIT ? RegRip : RegEip)))) | |
8577 | || (i.index_reg | |
8578 | && !i.index_reg->reg_type.bitfield.regxmm | |
8579 | && !i.index_reg->reg_type.bitfield.regymm | |
43234a1e | 8580 | && !i.index_reg->reg_type.bitfield.regzmm |
be05d201 L |
8581 | && ((addr_mode == CODE_64BIT |
8582 | ? !(i.index_reg->reg_type.bitfield.reg64 | |
8583 | || i.index_reg->reg_num == RegRiz) | |
8584 | : !(i.index_reg->reg_type.bitfield.reg32 | |
8585 | || i.index_reg->reg_num == RegEiz)) | |
8586 | || !i.index_reg->reg_type.bitfield.baseindex))) | |
8587 | goto bad_address; | |
8588 | } | |
8589 | else | |
3e73aa7c | 8590 | { |
be05d201 | 8591 | /* 16-bit checks. */ |
3e73aa7c | 8592 | if ((i.base_reg |
40fb9820 L |
8593 | && (!i.base_reg->reg_type.bitfield.reg16 |
8594 | || !i.base_reg->reg_type.bitfield.baseindex)) | |
3e73aa7c | 8595 | || (i.index_reg |
40fb9820 L |
8596 | && (!i.index_reg->reg_type.bitfield.reg16 |
8597 | || !i.index_reg->reg_type.bitfield.baseindex | |
29b0f896 AM |
8598 | || !(i.base_reg |
8599 | && i.base_reg->reg_num < 6 | |
8600 | && i.index_reg->reg_num >= 6 | |
8601 | && i.log2_scale_factor == 0)))) | |
be05d201 | 8602 | goto bad_address; |
3e73aa7c JH |
8603 | } |
8604 | } | |
be05d201 | 8605 | return 1; |
24eab124 | 8606 | } |
252b5132 | 8607 | |
43234a1e L |
8608 | /* Handle vector immediates. */ |
8609 | ||
8610 | static int | |
8611 | RC_SAE_immediate (const char *imm_start) | |
8612 | { | |
8613 | unsigned int match_found, j; | |
8614 | const char *pstr = imm_start; | |
8615 | expressionS *exp; | |
8616 | ||
8617 | if (*pstr != '{') | |
8618 | return 0; | |
8619 | ||
8620 | pstr++; | |
8621 | match_found = 0; | |
8622 | for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++) | |
8623 | { | |
8624 | if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len)) | |
8625 | { | |
8626 | if (!i.rounding) | |
8627 | { | |
8628 | rc_op.type = RC_NamesTable[j].type; | |
8629 | rc_op.operand = this_operand; | |
8630 | i.rounding = &rc_op; | |
8631 | } | |
8632 | else | |
8633 | { | |
8634 | as_bad (_("duplicated `%s'"), imm_start); | |
8635 | return 0; | |
8636 | } | |
8637 | pstr += RC_NamesTable[j].len; | |
8638 | match_found = 1; | |
8639 | break; | |
8640 | } | |
8641 | } | |
8642 | if (!match_found) | |
8643 | return 0; | |
8644 | ||
8645 | if (*pstr++ != '}') | |
8646 | { | |
8647 | as_bad (_("Missing '}': '%s'"), imm_start); | |
8648 | return 0; | |
8649 | } | |
8650 | /* RC/SAE immediate string should contain nothing more. */; | |
8651 | if (*pstr != 0) | |
8652 | { | |
8653 | as_bad (_("Junk after '}': '%s'"), imm_start); | |
8654 | return 0; | |
8655 | } | |
8656 | ||
8657 | exp = &im_expressions[i.imm_operands++]; | |
8658 | i.op[this_operand].imms = exp; | |
8659 | ||
8660 | exp->X_op = O_constant; | |
8661 | exp->X_add_number = 0; | |
8662 | exp->X_add_symbol = (symbolS *) 0; | |
8663 | exp->X_op_symbol = (symbolS *) 0; | |
8664 | ||
8665 | i.types[this_operand].bitfield.imm8 = 1; | |
8666 | return 1; | |
8667 | } | |
8668 | ||
8325cc63 JB |
8669 | /* Only string instructions can have a second memory operand, so |
8670 | reduce current_templates to just those if it contains any. */ | |
8671 | static int | |
8672 | maybe_adjust_templates (void) | |
8673 | { | |
8674 | const insn_template *t; | |
8675 | ||
8676 | gas_assert (i.mem_operands == 1); | |
8677 | ||
8678 | for (t = current_templates->start; t < current_templates->end; ++t) | |
8679 | if (t->opcode_modifier.isstring) | |
8680 | break; | |
8681 | ||
8682 | if (t < current_templates->end) | |
8683 | { | |
8684 | static templates aux_templates; | |
8685 | bfd_boolean recheck; | |
8686 | ||
8687 | aux_templates.start = t; | |
8688 | for (; t < current_templates->end; ++t) | |
8689 | if (!t->opcode_modifier.isstring) | |
8690 | break; | |
8691 | aux_templates.end = t; | |
8692 | ||
8693 | /* Determine whether to re-check the first memory operand. */ | |
8694 | recheck = (aux_templates.start != current_templates->start | |
8695 | || t != current_templates->end); | |
8696 | ||
8697 | current_templates = &aux_templates; | |
8698 | ||
8699 | if (recheck) | |
8700 | { | |
8701 | i.mem_operands = 0; | |
8702 | if (i.memop1_string != NULL | |
8703 | && i386_index_check (i.memop1_string) == 0) | |
8704 | return 0; | |
8705 | i.mem_operands = 1; | |
8706 | } | |
8707 | } | |
8708 | ||
8709 | return 1; | |
8710 | } | |
8711 | ||
fc0763e6 | 8712 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero |
47926f60 | 8713 | on error. */ |
252b5132 | 8714 | |
252b5132 | 8715 | static int |
a7619375 | 8716 | i386_att_operand (char *operand_string) |
252b5132 | 8717 | { |
af6bdddf AM |
8718 | const reg_entry *r; |
8719 | char *end_op; | |
24eab124 | 8720 | char *op_string = operand_string; |
252b5132 | 8721 | |
24eab124 | 8722 | if (is_space_char (*op_string)) |
252b5132 RH |
8723 | ++op_string; |
8724 | ||
24eab124 | 8725 | /* We check for an absolute prefix (differentiating, |
47926f60 | 8726 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
8727 | if (*op_string == ABSOLUTE_PREFIX) |
8728 | { | |
8729 | ++op_string; | |
8730 | if (is_space_char (*op_string)) | |
8731 | ++op_string; | |
40fb9820 | 8732 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 | 8733 | } |
252b5132 | 8734 | |
47926f60 | 8735 | /* Check if operand is a register. */ |
4d1bb795 | 8736 | if ((r = parse_register (op_string, &end_op)) != NULL) |
24eab124 | 8737 | { |
40fb9820 L |
8738 | i386_operand_type temp; |
8739 | ||
24eab124 AM |
8740 | /* Check for a segment override by searching for ':' after a |
8741 | segment register. */ | |
8742 | op_string = end_op; | |
8743 | if (is_space_char (*op_string)) | |
8744 | ++op_string; | |
40fb9820 L |
8745 | if (*op_string == ':' |
8746 | && (r->reg_type.bitfield.sreg2 | |
8747 | || r->reg_type.bitfield.sreg3)) | |
24eab124 AM |
8748 | { |
8749 | switch (r->reg_num) | |
8750 | { | |
8751 | case 0: | |
8752 | i.seg[i.mem_operands] = &es; | |
8753 | break; | |
8754 | case 1: | |
8755 | i.seg[i.mem_operands] = &cs; | |
8756 | break; | |
8757 | case 2: | |
8758 | i.seg[i.mem_operands] = &ss; | |
8759 | break; | |
8760 | case 3: | |
8761 | i.seg[i.mem_operands] = &ds; | |
8762 | break; | |
8763 | case 4: | |
8764 | i.seg[i.mem_operands] = &fs; | |
8765 | break; | |
8766 | case 5: | |
8767 | i.seg[i.mem_operands] = &gs; | |
8768 | break; | |
8769 | } | |
252b5132 | 8770 | |
24eab124 | 8771 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
8772 | ++op_string; |
8773 | if (is_space_char (*op_string)) | |
24eab124 | 8774 | ++op_string; |
252b5132 | 8775 | |
24eab124 AM |
8776 | if (!is_digit_char (*op_string) |
8777 | && !is_identifier_char (*op_string) | |
8778 | && *op_string != '(' | |
8779 | && *op_string != ABSOLUTE_PREFIX) | |
8780 | { | |
8781 | as_bad (_("bad memory operand `%s'"), op_string); | |
8782 | return 0; | |
8783 | } | |
47926f60 | 8784 | /* Handle case of %es:*foo. */ |
24eab124 AM |
8785 | if (*op_string == ABSOLUTE_PREFIX) |
8786 | { | |
8787 | ++op_string; | |
8788 | if (is_space_char (*op_string)) | |
8789 | ++op_string; | |
40fb9820 | 8790 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 AM |
8791 | } |
8792 | goto do_memory_reference; | |
8793 | } | |
43234a1e L |
8794 | |
8795 | /* Handle vector operations. */ | |
8796 | if (*op_string == '{') | |
8797 | { | |
8798 | op_string = check_VecOperations (op_string, NULL); | |
8799 | if (op_string == NULL) | |
8800 | return 0; | |
8801 | } | |
8802 | ||
24eab124 AM |
8803 | if (*op_string) |
8804 | { | |
d0b47220 | 8805 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
8806 | return 0; |
8807 | } | |
40fb9820 L |
8808 | temp = r->reg_type; |
8809 | temp.bitfield.baseindex = 0; | |
c6fb90c8 L |
8810 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
8811 | temp); | |
7d5e4556 | 8812 | i.types[this_operand].bitfield.unspecified = 0; |
520dc8e8 | 8813 | i.op[this_operand].regs = r; |
24eab124 AM |
8814 | i.reg_operands++; |
8815 | } | |
af6bdddf AM |
8816 | else if (*op_string == REGISTER_PREFIX) |
8817 | { | |
8818 | as_bad (_("bad register name `%s'"), op_string); | |
8819 | return 0; | |
8820 | } | |
24eab124 | 8821 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 8822 | { |
24eab124 | 8823 | ++op_string; |
40fb9820 | 8824 | if (i.types[this_operand].bitfield.jumpabsolute) |
24eab124 | 8825 | { |
d0b47220 | 8826 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
8827 | return 0; |
8828 | } | |
8829 | if (!i386_immediate (op_string)) | |
8830 | return 0; | |
8831 | } | |
43234a1e L |
8832 | else if (RC_SAE_immediate (operand_string)) |
8833 | { | |
8834 | /* If it is a RC or SAE immediate, do nothing. */ | |
8835 | ; | |
8836 | } | |
24eab124 AM |
8837 | else if (is_digit_char (*op_string) |
8838 | || is_identifier_char (*op_string) | |
d02603dc | 8839 | || *op_string == '"' |
e5cb08ac | 8840 | || *op_string == '(') |
24eab124 | 8841 | { |
47926f60 | 8842 | /* This is a memory reference of some sort. */ |
af6bdddf | 8843 | char *base_string; |
252b5132 | 8844 | |
47926f60 | 8845 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
8846 | char *displacement_string_start; |
8847 | char *displacement_string_end; | |
43234a1e | 8848 | char *vop_start; |
252b5132 | 8849 | |
24eab124 | 8850 | do_memory_reference: |
8325cc63 JB |
8851 | if (i.mem_operands == 1 && !maybe_adjust_templates ()) |
8852 | return 0; | |
24eab124 | 8853 | if ((i.mem_operands == 1 |
40fb9820 | 8854 | && !current_templates->start->opcode_modifier.isstring) |
24eab124 AM |
8855 | || i.mem_operands == 2) |
8856 | { | |
8857 | as_bad (_("too many memory references for `%s'"), | |
8858 | current_templates->start->name); | |
8859 | return 0; | |
8860 | } | |
252b5132 | 8861 | |
24eab124 AM |
8862 | /* Check for base index form. We detect the base index form by |
8863 | looking for an ')' at the end of the operand, searching | |
8864 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
8865 | after the '('. */ | |
af6bdddf | 8866 | base_string = op_string + strlen (op_string); |
c3332e24 | 8867 | |
43234a1e L |
8868 | /* Handle vector operations. */ |
8869 | vop_start = strchr (op_string, '{'); | |
8870 | if (vop_start && vop_start < base_string) | |
8871 | { | |
8872 | if (check_VecOperations (vop_start, base_string) == NULL) | |
8873 | return 0; | |
8874 | base_string = vop_start; | |
8875 | } | |
8876 | ||
af6bdddf AM |
8877 | --base_string; |
8878 | if (is_space_char (*base_string)) | |
8879 | --base_string; | |
252b5132 | 8880 | |
47926f60 | 8881 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
8882 | displacement_string_start = op_string; |
8883 | displacement_string_end = base_string + 1; | |
252b5132 | 8884 | |
24eab124 AM |
8885 | if (*base_string == ')') |
8886 | { | |
af6bdddf | 8887 | char *temp_string; |
24eab124 AM |
8888 | unsigned int parens_balanced = 1; |
8889 | /* We've already checked that the number of left & right ()'s are | |
47926f60 | 8890 | equal, so this loop will not be infinite. */ |
24eab124 AM |
8891 | do |
8892 | { | |
8893 | base_string--; | |
8894 | if (*base_string == ')') | |
8895 | parens_balanced++; | |
8896 | if (*base_string == '(') | |
8897 | parens_balanced--; | |
8898 | } | |
8899 | while (parens_balanced); | |
c3332e24 | 8900 | |
af6bdddf | 8901 | temp_string = base_string; |
c3332e24 | 8902 | |
24eab124 | 8903 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
8904 | ++base_string; |
8905 | if (is_space_char (*base_string)) | |
24eab124 | 8906 | ++base_string; |
252b5132 | 8907 | |
af6bdddf | 8908 | if (*base_string == ',' |
4eed87de AM |
8909 | || ((i.base_reg = parse_register (base_string, &end_op)) |
8910 | != NULL)) | |
252b5132 | 8911 | { |
af6bdddf | 8912 | displacement_string_end = temp_string; |
252b5132 | 8913 | |
40fb9820 | 8914 | i.types[this_operand].bitfield.baseindex = 1; |
252b5132 | 8915 | |
af6bdddf | 8916 | if (i.base_reg) |
24eab124 | 8917 | { |
24eab124 AM |
8918 | base_string = end_op; |
8919 | if (is_space_char (*base_string)) | |
8920 | ++base_string; | |
af6bdddf AM |
8921 | } |
8922 | ||
8923 | /* There may be an index reg or scale factor here. */ | |
8924 | if (*base_string == ',') | |
8925 | { | |
8926 | ++base_string; | |
8927 | if (is_space_char (*base_string)) | |
8928 | ++base_string; | |
8929 | ||
4eed87de AM |
8930 | if ((i.index_reg = parse_register (base_string, &end_op)) |
8931 | != NULL) | |
24eab124 | 8932 | { |
af6bdddf | 8933 | base_string = end_op; |
24eab124 AM |
8934 | if (is_space_char (*base_string)) |
8935 | ++base_string; | |
af6bdddf AM |
8936 | if (*base_string == ',') |
8937 | { | |
8938 | ++base_string; | |
8939 | if (is_space_char (*base_string)) | |
8940 | ++base_string; | |
8941 | } | |
e5cb08ac | 8942 | else if (*base_string != ')') |
af6bdddf | 8943 | { |
4eed87de AM |
8944 | as_bad (_("expecting `,' or `)' " |
8945 | "after index register in `%s'"), | |
af6bdddf AM |
8946 | operand_string); |
8947 | return 0; | |
8948 | } | |
24eab124 | 8949 | } |
af6bdddf | 8950 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 8951 | { |
f76bf5e0 L |
8952 | end_op = strchr (base_string, ','); |
8953 | if (end_op) | |
8954 | *end_op = '\0'; | |
af6bdddf | 8955 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
8956 | return 0; |
8957 | } | |
252b5132 | 8958 | |
47926f60 | 8959 | /* Check for scale factor. */ |
551c1ca1 | 8960 | if (*base_string != ')') |
af6bdddf | 8961 | { |
551c1ca1 AM |
8962 | char *end_scale = i386_scale (base_string); |
8963 | ||
8964 | if (!end_scale) | |
af6bdddf | 8965 | return 0; |
24eab124 | 8966 | |
551c1ca1 | 8967 | base_string = end_scale; |
af6bdddf AM |
8968 | if (is_space_char (*base_string)) |
8969 | ++base_string; | |
8970 | if (*base_string != ')') | |
8971 | { | |
4eed87de AM |
8972 | as_bad (_("expecting `)' " |
8973 | "after scale factor in `%s'"), | |
af6bdddf AM |
8974 | operand_string); |
8975 | return 0; | |
8976 | } | |
8977 | } | |
8978 | else if (!i.index_reg) | |
24eab124 | 8979 | { |
4eed87de AM |
8980 | as_bad (_("expecting index register or scale factor " |
8981 | "after `,'; got '%c'"), | |
af6bdddf | 8982 | *base_string); |
24eab124 AM |
8983 | return 0; |
8984 | } | |
8985 | } | |
af6bdddf | 8986 | else if (*base_string != ')') |
24eab124 | 8987 | { |
4eed87de AM |
8988 | as_bad (_("expecting `,' or `)' " |
8989 | "after base register in `%s'"), | |
af6bdddf | 8990 | operand_string); |
24eab124 AM |
8991 | return 0; |
8992 | } | |
c3332e24 | 8993 | } |
af6bdddf | 8994 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 8995 | { |
f76bf5e0 L |
8996 | end_op = strchr (base_string, ','); |
8997 | if (end_op) | |
8998 | *end_op = '\0'; | |
af6bdddf | 8999 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 9000 | return 0; |
c3332e24 | 9001 | } |
24eab124 AM |
9002 | } |
9003 | ||
9004 | /* If there's an expression beginning the operand, parse it, | |
9005 | assuming displacement_string_start and | |
9006 | displacement_string_end are meaningful. */ | |
9007 | if (displacement_string_start != displacement_string_end) | |
9008 | { | |
9009 | if (!i386_displacement (displacement_string_start, | |
9010 | displacement_string_end)) | |
9011 | return 0; | |
9012 | } | |
9013 | ||
9014 | /* Special case for (%dx) while doing input/output op. */ | |
9015 | if (i.base_reg | |
0dfbf9d7 L |
9016 | && operand_type_equal (&i.base_reg->reg_type, |
9017 | ®16_inoutportreg) | |
24eab124 AM |
9018 | && i.index_reg == 0 |
9019 | && i.log2_scale_factor == 0 | |
9020 | && i.seg[i.mem_operands] == 0 | |
40fb9820 | 9021 | && !operand_type_check (i.types[this_operand], disp)) |
24eab124 | 9022 | { |
65da13b5 | 9023 | i.types[this_operand] = inoutportreg; |
24eab124 AM |
9024 | return 1; |
9025 | } | |
9026 | ||
eecb386c AM |
9027 | if (i386_index_check (operand_string) == 0) |
9028 | return 0; | |
5c07affc | 9029 | i.types[this_operand].bitfield.mem = 1; |
8325cc63 JB |
9030 | if (i.mem_operands == 0) |
9031 | i.memop1_string = xstrdup (operand_string); | |
24eab124 AM |
9032 | i.mem_operands++; |
9033 | } | |
9034 | else | |
ce8a8b2f AM |
9035 | { |
9036 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
9037 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
9038 | output_invalid (*op_string), | |
9039 | this_operand + 1, | |
9040 | op_string); | |
9041 | return 0; | |
9042 | } | |
47926f60 | 9043 | return 1; /* Normal return. */ |
252b5132 RH |
9044 | } |
9045 | \f | |
fa94de6b RM |
9046 | /* Calculate the maximum variable size (i.e., excluding fr_fix) |
9047 | that an rs_machine_dependent frag may reach. */ | |
9048 | ||
9049 | unsigned int | |
9050 | i386_frag_max_var (fragS *frag) | |
9051 | { | |
9052 | /* The only relaxable frags are for jumps. | |
9053 | Unconditional jumps can grow by 4 bytes and others by 5 bytes. */ | |
9054 | gas_assert (frag->fr_type == rs_machine_dependent); | |
9055 | return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5; | |
9056 | } | |
9057 | ||
b084df0b L |
9058 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
9059 | static int | |
8dcea932 | 9060 | elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var) |
b084df0b L |
9061 | { |
9062 | /* STT_GNU_IFUNC symbol must go through PLT. */ | |
9063 | if ((symbol_get_bfdsym (fr_symbol)->flags | |
9064 | & BSF_GNU_INDIRECT_FUNCTION) != 0) | |
9065 | return 0; | |
9066 | ||
9067 | if (!S_IS_EXTERNAL (fr_symbol)) | |
9068 | /* Symbol may be weak or local. */ | |
9069 | return !S_IS_WEAK (fr_symbol); | |
9070 | ||
8dcea932 L |
9071 | /* Global symbols with non-default visibility can't be preempted. */ |
9072 | if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT) | |
9073 | return 1; | |
9074 | ||
9075 | if (fr_var != NO_RELOC) | |
9076 | switch ((enum bfd_reloc_code_real) fr_var) | |
9077 | { | |
9078 | case BFD_RELOC_386_PLT32: | |
9079 | case BFD_RELOC_X86_64_PLT32: | |
9080 | /* Symbol with PLT relocatin may be preempted. */ | |
9081 | return 0; | |
9082 | default: | |
9083 | abort (); | |
9084 | } | |
9085 | ||
b084df0b L |
9086 | /* Global symbols with default visibility in a shared library may be |
9087 | preempted by another definition. */ | |
8dcea932 | 9088 | return !shared; |
b084df0b L |
9089 | } |
9090 | #endif | |
9091 | ||
ee7fcc42 AM |
9092 | /* md_estimate_size_before_relax() |
9093 | ||
9094 | Called just before relax() for rs_machine_dependent frags. The x86 | |
9095 | assembler uses these frags to handle variable size jump | |
9096 | instructions. | |
9097 | ||
9098 | Any symbol that is now undefined will not become defined. | |
9099 | Return the correct fr_subtype in the frag. | |
9100 | Return the initial "guess for variable size of frag" to caller. | |
9101 | The guess is actually the growth beyond the fixed part. Whatever | |
9102 | we do to grow the fixed or variable part contributes to our | |
9103 | returned value. */ | |
9104 | ||
252b5132 | 9105 | int |
7016a5d5 | 9106 | md_estimate_size_before_relax (fragS *fragP, segT segment) |
252b5132 | 9107 | { |
252b5132 | 9108 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
9109 | check for un-relaxable symbols. On an ELF system, we can't relax |
9110 | an externally visible symbol, because it may be overridden by a | |
9111 | shared library. */ | |
9112 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 9113 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 9114 | || (IS_ELF |
8dcea932 L |
9115 | && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol, |
9116 | fragP->fr_var)) | |
fbeb56a4 DK |
9117 | #endif |
9118 | #if defined (OBJ_COFF) && defined (TE_PE) | |
7ab9ffdd | 9119 | || (OUTPUT_FLAVOR == bfd_target_coff_flavour |
fbeb56a4 | 9120 | && S_IS_WEAK (fragP->fr_symbol)) |
b98ef147 AM |
9121 | #endif |
9122 | ) | |
252b5132 | 9123 | { |
b98ef147 AM |
9124 | /* Symbol is undefined in this segment, or we need to keep a |
9125 | reloc so that weak symbols can be overridden. */ | |
9126 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f86103b7 | 9127 | enum bfd_reloc_code_real reloc_type; |
ee7fcc42 AM |
9128 | unsigned char *opcode; |
9129 | int old_fr_fix; | |
f6af82bd | 9130 | |
ee7fcc42 | 9131 | if (fragP->fr_var != NO_RELOC) |
1e9cc1c2 | 9132 | reloc_type = (enum bfd_reloc_code_real) fragP->fr_var; |
b98ef147 | 9133 | else if (size == 2) |
f6af82bd AM |
9134 | reloc_type = BFD_RELOC_16_PCREL; |
9135 | else | |
9136 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 9137 | |
ee7fcc42 AM |
9138 | old_fr_fix = fragP->fr_fix; |
9139 | opcode = (unsigned char *) fragP->fr_opcode; | |
9140 | ||
fddf5b5b | 9141 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 9142 | { |
fddf5b5b AM |
9143 | case UNCOND_JUMP: |
9144 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 9145 | opcode[0] = 0xe9; |
252b5132 | 9146 | fragP->fr_fix += size; |
062cd5e7 AS |
9147 | fix_new (fragP, old_fr_fix, size, |
9148 | fragP->fr_symbol, | |
9149 | fragP->fr_offset, 1, | |
9150 | reloc_type); | |
252b5132 RH |
9151 | break; |
9152 | ||
fddf5b5b | 9153 | case COND_JUMP86: |
412167cb AM |
9154 | if (size == 2 |
9155 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) | |
fddf5b5b AM |
9156 | { |
9157 | /* Negate the condition, and branch past an | |
9158 | unconditional jump. */ | |
9159 | opcode[0] ^= 1; | |
9160 | opcode[1] = 3; | |
9161 | /* Insert an unconditional jump. */ | |
9162 | opcode[2] = 0xe9; | |
9163 | /* We added two extra opcode bytes, and have a two byte | |
9164 | offset. */ | |
9165 | fragP->fr_fix += 2 + 2; | |
062cd5e7 AS |
9166 | fix_new (fragP, old_fr_fix + 2, 2, |
9167 | fragP->fr_symbol, | |
9168 | fragP->fr_offset, 1, | |
9169 | reloc_type); | |
fddf5b5b AM |
9170 | break; |
9171 | } | |
9172 | /* Fall through. */ | |
9173 | ||
9174 | case COND_JUMP: | |
412167cb AM |
9175 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
9176 | { | |
3e02c1cc AM |
9177 | fixS *fixP; |
9178 | ||
412167cb | 9179 | fragP->fr_fix += 1; |
3e02c1cc AM |
9180 | fixP = fix_new (fragP, old_fr_fix, 1, |
9181 | fragP->fr_symbol, | |
9182 | fragP->fr_offset, 1, | |
9183 | BFD_RELOC_8_PCREL); | |
9184 | fixP->fx_signed = 1; | |
412167cb AM |
9185 | break; |
9186 | } | |
93c2a809 | 9187 | |
24eab124 | 9188 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 9189 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 9190 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 9191 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
9192 | /* We've added an opcode byte. */ |
9193 | fragP->fr_fix += 1 + size; | |
062cd5e7 AS |
9194 | fix_new (fragP, old_fr_fix + 1, size, |
9195 | fragP->fr_symbol, | |
9196 | fragP->fr_offset, 1, | |
9197 | reloc_type); | |
252b5132 | 9198 | break; |
fddf5b5b AM |
9199 | |
9200 | default: | |
9201 | BAD_CASE (fragP->fr_subtype); | |
9202 | break; | |
252b5132 RH |
9203 | } |
9204 | frag_wane (fragP); | |
ee7fcc42 | 9205 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 9206 | } |
93c2a809 | 9207 | |
93c2a809 AM |
9208 | /* Guess size depending on current relax state. Initially the relax |
9209 | state will correspond to a short jump and we return 1, because | |
9210 | the variable part of the frag (the branch offset) is one byte | |
9211 | long. However, we can relax a section more than once and in that | |
9212 | case we must either set fr_subtype back to the unrelaxed state, | |
9213 | or return the value for the appropriate branch. */ | |
9214 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
9215 | } |
9216 | ||
47926f60 KH |
9217 | /* Called after relax() is finished. |
9218 | ||
9219 | In: Address of frag. | |
9220 | fr_type == rs_machine_dependent. | |
9221 | fr_subtype is what the address relaxed to. | |
9222 | ||
9223 | Out: Any fixSs and constants are set up. | |
9224 | Caller will turn frag into a ".space 0". */ | |
9225 | ||
252b5132 | 9226 | void |
7016a5d5 TG |
9227 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, |
9228 | fragS *fragP) | |
252b5132 | 9229 | { |
29b0f896 | 9230 | unsigned char *opcode; |
252b5132 | 9231 | unsigned char *where_to_put_displacement = NULL; |
847f7ad4 AM |
9232 | offsetT target_address; |
9233 | offsetT opcode_address; | |
252b5132 | 9234 | unsigned int extension = 0; |
847f7ad4 | 9235 | offsetT displacement_from_opcode_start; |
252b5132 RH |
9236 | |
9237 | opcode = (unsigned char *) fragP->fr_opcode; | |
9238 | ||
47926f60 | 9239 | /* Address we want to reach in file space. */ |
252b5132 | 9240 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 9241 | |
47926f60 | 9242 | /* Address opcode resides at in file space. */ |
252b5132 RH |
9243 | opcode_address = fragP->fr_address + fragP->fr_fix; |
9244 | ||
47926f60 | 9245 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
9246 | displacement_from_opcode_start = target_address - opcode_address; |
9247 | ||
fddf5b5b | 9248 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 9249 | { |
47926f60 KH |
9250 | /* Don't have to change opcode. */ |
9251 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 9252 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
9253 | } |
9254 | else | |
9255 | { | |
9256 | if (no_cond_jump_promotion | |
9257 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4eed87de AM |
9258 | as_warn_where (fragP->fr_file, fragP->fr_line, |
9259 | _("long jump required")); | |
252b5132 | 9260 | |
fddf5b5b AM |
9261 | switch (fragP->fr_subtype) |
9262 | { | |
9263 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
9264 | extension = 4; /* 1 opcode + 4 displacement */ | |
9265 | opcode[0] = 0xe9; | |
9266 | where_to_put_displacement = &opcode[1]; | |
9267 | break; | |
252b5132 | 9268 | |
fddf5b5b AM |
9269 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
9270 | extension = 2; /* 1 opcode + 2 displacement */ | |
9271 | opcode[0] = 0xe9; | |
9272 | where_to_put_displacement = &opcode[1]; | |
9273 | break; | |
252b5132 | 9274 | |
fddf5b5b AM |
9275 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
9276 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
9277 | extension = 5; /* 2 opcode + 4 displacement */ | |
9278 | opcode[1] = opcode[0] + 0x10; | |
9279 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
9280 | where_to_put_displacement = &opcode[2]; | |
9281 | break; | |
252b5132 | 9282 | |
fddf5b5b AM |
9283 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
9284 | extension = 3; /* 2 opcode + 2 displacement */ | |
9285 | opcode[1] = opcode[0] + 0x10; | |
9286 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
9287 | where_to_put_displacement = &opcode[2]; | |
9288 | break; | |
252b5132 | 9289 | |
fddf5b5b AM |
9290 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
9291 | extension = 4; | |
9292 | opcode[0] ^= 1; | |
9293 | opcode[1] = 3; | |
9294 | opcode[2] = 0xe9; | |
9295 | where_to_put_displacement = &opcode[3]; | |
9296 | break; | |
9297 | ||
9298 | default: | |
9299 | BAD_CASE (fragP->fr_subtype); | |
9300 | break; | |
9301 | } | |
252b5132 | 9302 | } |
fddf5b5b | 9303 | |
7b81dfbb AJ |
9304 | /* If size if less then four we are sure that the operand fits, |
9305 | but if it's 4, then it could be that the displacement is larger | |
9306 | then -/+ 2GB. */ | |
9307 | if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 | |
9308 | && object_64bit | |
9309 | && ((addressT) (displacement_from_opcode_start - extension | |
4eed87de AM |
9310 | + ((addressT) 1 << 31)) |
9311 | > (((addressT) 2 << 31) - 1))) | |
7b81dfbb AJ |
9312 | { |
9313 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
9314 | _("jump target out of range")); | |
9315 | /* Make us emit 0. */ | |
9316 | displacement_from_opcode_start = extension; | |
9317 | } | |
47926f60 | 9318 | /* Now put displacement after opcode. */ |
252b5132 RH |
9319 | md_number_to_chars ((char *) where_to_put_displacement, |
9320 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 9321 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
9322 | fragP->fr_fix += extension; |
9323 | } | |
9324 | \f | |
7016a5d5 | 9325 | /* Apply a fixup (fixP) to segment data, once it has been determined |
252b5132 RH |
9326 | by our caller that we have all the info we need to fix it up. |
9327 | ||
7016a5d5 TG |
9328 | Parameter valP is the pointer to the value of the bits. |
9329 | ||
252b5132 RH |
9330 | On the 386, immediates, displacements, and data pointers are all in |
9331 | the same (little-endian) format, so we don't need to care about which | |
9332 | we are handling. */ | |
9333 | ||
94f592af | 9334 | void |
7016a5d5 | 9335 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 9336 | { |
94f592af | 9337 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
c6682705 | 9338 | valueT value = *valP; |
252b5132 | 9339 | |
f86103b7 | 9340 | #if !defined (TE_Mach) |
93382f6d AM |
9341 | if (fixP->fx_pcrel) |
9342 | { | |
9343 | switch (fixP->fx_r_type) | |
9344 | { | |
5865bb77 ILT |
9345 | default: |
9346 | break; | |
9347 | ||
d6ab8113 JB |
9348 | case BFD_RELOC_64: |
9349 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
9350 | break; | |
93382f6d | 9351 | case BFD_RELOC_32: |
ae8887b5 | 9352 | case BFD_RELOC_X86_64_32S: |
93382f6d AM |
9353 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
9354 | break; | |
9355 | case BFD_RELOC_16: | |
9356 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
9357 | break; | |
9358 | case BFD_RELOC_8: | |
9359 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
9360 | break; | |
9361 | } | |
9362 | } | |
252b5132 | 9363 | |
a161fe53 | 9364 | if (fixP->fx_addsy != NULL |
31312f95 | 9365 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
d6ab8113 | 9366 | || fixP->fx_r_type == BFD_RELOC_64_PCREL |
31312f95 | 9367 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
d258b828 | 9368 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) |
31312f95 | 9369 | && !use_rela_relocations) |
252b5132 | 9370 | { |
31312f95 AM |
9371 | /* This is a hack. There should be a better way to handle this. |
9372 | This covers for the fact that bfd_install_relocation will | |
9373 | subtract the current location (for partial_inplace, PC relative | |
9374 | relocations); see more below. */ | |
252b5132 | 9375 | #ifndef OBJ_AOUT |
718ddfc0 | 9376 | if (IS_ELF |
252b5132 RH |
9377 | #ifdef TE_PE |
9378 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
9379 | #endif | |
9380 | ) | |
9381 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
9382 | #endif | |
9383 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 9384 | if (IS_ELF) |
252b5132 | 9385 | { |
6539b54b | 9386 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
2f66722d | 9387 | |
6539b54b | 9388 | if ((sym_seg == seg |
2f66722d | 9389 | || (symbol_section_p (fixP->fx_addsy) |
6539b54b | 9390 | && sym_seg != absolute_section)) |
af65af87 | 9391 | && !generic_force_reloc (fixP)) |
2f66722d AM |
9392 | { |
9393 | /* Yes, we add the values in twice. This is because | |
6539b54b AM |
9394 | bfd_install_relocation subtracts them out again. I think |
9395 | bfd_install_relocation is broken, but I don't dare change | |
2f66722d AM |
9396 | it. FIXME. */ |
9397 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
9398 | } | |
252b5132 RH |
9399 | } |
9400 | #endif | |
9401 | #if defined (OBJ_COFF) && defined (TE_PE) | |
977cdf5a NC |
9402 | /* For some reason, the PE format does not store a |
9403 | section address offset for a PC relative symbol. */ | |
9404 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg | |
7be1c489 | 9405 | || S_IS_WEAK (fixP->fx_addsy)) |
252b5132 RH |
9406 | value += md_pcrel_from (fixP); |
9407 | #endif | |
9408 | } | |
fbeb56a4 | 9409 | #if defined (OBJ_COFF) && defined (TE_PE) |
f01c1a09 NC |
9410 | if (fixP->fx_addsy != NULL |
9411 | && S_IS_WEAK (fixP->fx_addsy) | |
9412 | /* PR 16858: Do not modify weak function references. */ | |
9413 | && ! fixP->fx_pcrel) | |
fbeb56a4 | 9414 | { |
296a8689 NC |
9415 | #if !defined (TE_PEP) |
9416 | /* For x86 PE weak function symbols are neither PC-relative | |
9417 | nor do they set S_IS_FUNCTION. So the only reliable way | |
9418 | to detect them is to check the flags of their containing | |
9419 | section. */ | |
9420 | if (S_GET_SEGMENT (fixP->fx_addsy) != NULL | |
9421 | && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE) | |
9422 | ; | |
9423 | else | |
9424 | #endif | |
fbeb56a4 DK |
9425 | value -= S_GET_VALUE (fixP->fx_addsy); |
9426 | } | |
9427 | #endif | |
252b5132 RH |
9428 | |
9429 | /* Fix a few things - the dynamic linker expects certain values here, | |
0234cb7c | 9430 | and we must not disappoint it. */ |
252b5132 | 9431 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 9432 | if (IS_ELF && fixP->fx_addsy) |
47926f60 KH |
9433 | switch (fixP->fx_r_type) |
9434 | { | |
9435 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 9436 | case BFD_RELOC_X86_64_PLT32: |
47926f60 KH |
9437 | /* Make the jump instruction point to the address of the operand. At |
9438 | runtime we merely add the offset to the actual PLT entry. */ | |
9439 | value = -4; | |
9440 | break; | |
31312f95 | 9441 | |
13ae64f3 JJ |
9442 | case BFD_RELOC_386_TLS_GD: |
9443 | case BFD_RELOC_386_TLS_LDM: | |
13ae64f3 | 9444 | case BFD_RELOC_386_TLS_IE_32: |
37e55690 JJ |
9445 | case BFD_RELOC_386_TLS_IE: |
9446 | case BFD_RELOC_386_TLS_GOTIE: | |
67a4f2b7 | 9447 | case BFD_RELOC_386_TLS_GOTDESC: |
bffbf940 JJ |
9448 | case BFD_RELOC_X86_64_TLSGD: |
9449 | case BFD_RELOC_X86_64_TLSLD: | |
9450 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 | 9451 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
00f7efb6 JJ |
9452 | value = 0; /* Fully resolved at runtime. No addend. */ |
9453 | /* Fallthrough */ | |
9454 | case BFD_RELOC_386_TLS_LE: | |
9455 | case BFD_RELOC_386_TLS_LDO_32: | |
9456 | case BFD_RELOC_386_TLS_LE_32: | |
9457 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 9458 | case BFD_RELOC_X86_64_DTPOFF64: |
00f7efb6 | 9459 | case BFD_RELOC_X86_64_TPOFF32: |
d6ab8113 | 9460 | case BFD_RELOC_X86_64_TPOFF64: |
00f7efb6 JJ |
9461 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
9462 | break; | |
9463 | ||
67a4f2b7 AO |
9464 | case BFD_RELOC_386_TLS_DESC_CALL: |
9465 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
9466 | value = 0; /* Fully resolved at runtime. No addend. */ | |
9467 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
9468 | fixP->fx_done = 0; | |
9469 | return; | |
9470 | ||
47926f60 KH |
9471 | case BFD_RELOC_VTABLE_INHERIT: |
9472 | case BFD_RELOC_VTABLE_ENTRY: | |
9473 | fixP->fx_done = 0; | |
94f592af | 9474 | return; |
47926f60 KH |
9475 | |
9476 | default: | |
9477 | break; | |
9478 | } | |
9479 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
c6682705 | 9480 | *valP = value; |
f86103b7 | 9481 | #endif /* !defined (TE_Mach) */ |
3e73aa7c | 9482 | |
3e73aa7c | 9483 | /* Are we finished with this relocation now? */ |
c6682705 | 9484 | if (fixP->fx_addsy == NULL) |
3e73aa7c | 9485 | fixP->fx_done = 1; |
fbeb56a4 DK |
9486 | #if defined (OBJ_COFF) && defined (TE_PE) |
9487 | else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) | |
9488 | { | |
9489 | fixP->fx_done = 0; | |
9490 | /* Remember value for tc_gen_reloc. */ | |
9491 | fixP->fx_addnumber = value; | |
9492 | /* Clear out the frag for now. */ | |
9493 | value = 0; | |
9494 | } | |
9495 | #endif | |
3e73aa7c JH |
9496 | else if (use_rela_relocations) |
9497 | { | |
9498 | fixP->fx_no_overflow = 1; | |
062cd5e7 AS |
9499 | /* Remember value for tc_gen_reloc. */ |
9500 | fixP->fx_addnumber = value; | |
3e73aa7c JH |
9501 | value = 0; |
9502 | } | |
f86103b7 | 9503 | |
94f592af | 9504 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 9505 | } |
252b5132 | 9506 | \f |
6d4af3c2 | 9507 | const char * |
499ac353 | 9508 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 9509 | { |
499ac353 NC |
9510 | /* This outputs the LITTLENUMs in REVERSE order; |
9511 | in accord with the bigendian 386. */ | |
9512 | return ieee_md_atof (type, litP, sizeP, FALSE); | |
252b5132 RH |
9513 | } |
9514 | \f | |
2d545b82 | 9515 | static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; |
252b5132 | 9516 | |
252b5132 | 9517 | static char * |
e3bb37b5 | 9518 | output_invalid (int c) |
252b5132 | 9519 | { |
3882b010 | 9520 | if (ISPRINT (c)) |
f9f21a03 L |
9521 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
9522 | "'%c'", c); | |
252b5132 | 9523 | else |
f9f21a03 | 9524 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
2d545b82 | 9525 | "(0x%x)", (unsigned char) c); |
252b5132 RH |
9526 | return output_invalid_buf; |
9527 | } | |
9528 | ||
af6bdddf | 9529 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
9530 | |
9531 | static const reg_entry * | |
4d1bb795 | 9532 | parse_real_register (char *reg_string, char **end_op) |
252b5132 | 9533 | { |
af6bdddf AM |
9534 | char *s = reg_string; |
9535 | char *p; | |
252b5132 RH |
9536 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
9537 | const reg_entry *r; | |
9538 | ||
9539 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
9540 | if (*s == REGISTER_PREFIX) | |
9541 | ++s; | |
9542 | ||
9543 | if (is_space_char (*s)) | |
9544 | ++s; | |
9545 | ||
9546 | p = reg_name_given; | |
af6bdddf | 9547 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
9548 | { |
9549 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
9550 | return (const reg_entry *) NULL; |
9551 | s++; | |
252b5132 RH |
9552 | } |
9553 | ||
6588847e DN |
9554 | /* For naked regs, make sure that we are not dealing with an identifier. |
9555 | This prevents confusing an identifier like `eax_var' with register | |
9556 | `eax'. */ | |
9557 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
9558 | return (const reg_entry *) NULL; | |
9559 | ||
af6bdddf | 9560 | *end_op = s; |
252b5132 RH |
9561 | |
9562 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
9563 | ||
5f47d35b | 9564 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
47926f60 | 9565 | if (r == i386_regtab /* %st is first entry of table */) |
5f47d35b | 9566 | { |
5f47d35b AM |
9567 | if (is_space_char (*s)) |
9568 | ++s; | |
9569 | if (*s == '(') | |
9570 | { | |
af6bdddf | 9571 | ++s; |
5f47d35b AM |
9572 | if (is_space_char (*s)) |
9573 | ++s; | |
9574 | if (*s >= '0' && *s <= '7') | |
9575 | { | |
db557034 | 9576 | int fpr = *s - '0'; |
af6bdddf | 9577 | ++s; |
5f47d35b AM |
9578 | if (is_space_char (*s)) |
9579 | ++s; | |
9580 | if (*s == ')') | |
9581 | { | |
9582 | *end_op = s + 1; | |
1e9cc1c2 | 9583 | r = (const reg_entry *) hash_find (reg_hash, "st(0)"); |
db557034 AM |
9584 | know (r); |
9585 | return r + fpr; | |
5f47d35b | 9586 | } |
5f47d35b | 9587 | } |
47926f60 | 9588 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
9589 | return (const reg_entry *) NULL; |
9590 | } | |
9591 | } | |
9592 | ||
a60de03c JB |
9593 | if (r == NULL || allow_pseudo_reg) |
9594 | return r; | |
9595 | ||
0dfbf9d7 | 9596 | if (operand_type_all_zero (&r->reg_type)) |
a60de03c JB |
9597 | return (const reg_entry *) NULL; |
9598 | ||
192dc9c6 JB |
9599 | if ((r->reg_type.bitfield.reg32 |
9600 | || r->reg_type.bitfield.sreg3 | |
9601 | || r->reg_type.bitfield.control | |
9602 | || r->reg_type.bitfield.debug | |
9603 | || r->reg_type.bitfield.test) | |
9604 | && !cpu_arch_flags.bitfield.cpui386) | |
9605 | return (const reg_entry *) NULL; | |
9606 | ||
309d3373 JB |
9607 | if (r->reg_type.bitfield.floatreg |
9608 | && !cpu_arch_flags.bitfield.cpu8087 | |
9609 | && !cpu_arch_flags.bitfield.cpu287 | |
9610 | && !cpu_arch_flags.bitfield.cpu387) | |
9611 | return (const reg_entry *) NULL; | |
9612 | ||
1848e567 | 9613 | if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx) |
192dc9c6 JB |
9614 | return (const reg_entry *) NULL; |
9615 | ||
1848e567 | 9616 | if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpuregxmm) |
192dc9c6 JB |
9617 | return (const reg_entry *) NULL; |
9618 | ||
1848e567 | 9619 | if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuregymm) |
40f12533 L |
9620 | return (const reg_entry *) NULL; |
9621 | ||
1848e567 L |
9622 | if (r->reg_type.bitfield.regzmm && !cpu_arch_flags.bitfield.cpuregzmm) |
9623 | return (const reg_entry *) NULL; | |
9624 | ||
9625 | if (r->reg_type.bitfield.regmask | |
9626 | && !cpu_arch_flags.bitfield.cpuregmask) | |
43234a1e L |
9627 | return (const reg_entry *) NULL; |
9628 | ||
db51cc60 | 9629 | /* Don't allow fake index register unless allow_index_reg isn't 0. */ |
a60de03c | 9630 | if (!allow_index_reg |
db51cc60 L |
9631 | && (r->reg_num == RegEiz || r->reg_num == RegRiz)) |
9632 | return (const reg_entry *) NULL; | |
9633 | ||
43234a1e L |
9634 | /* Upper 16 vector register is only available with VREX in 64bit |
9635 | mode. */ | |
9636 | if ((r->reg_flags & RegVRex)) | |
9637 | { | |
9638 | if (!cpu_arch_flags.bitfield.cpuvrex | |
9639 | || flag_code != CODE_64BIT) | |
9640 | return (const reg_entry *) NULL; | |
9641 | ||
9642 | i.need_vrex = 1; | |
9643 | } | |
9644 | ||
a60de03c JB |
9645 | if (((r->reg_flags & (RegRex64 | RegRex)) |
9646 | || r->reg_type.bitfield.reg64) | |
40fb9820 | 9647 | && (!cpu_arch_flags.bitfield.cpulm |
0dfbf9d7 | 9648 | || !operand_type_equal (&r->reg_type, &control)) |
1ae00879 | 9649 | && flag_code != CODE_64BIT) |
20f0a1fc | 9650 | return (const reg_entry *) NULL; |
1ae00879 | 9651 | |
b7240065 JB |
9652 | if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax) |
9653 | return (const reg_entry *) NULL; | |
9654 | ||
252b5132 RH |
9655 | return r; |
9656 | } | |
4d1bb795 JB |
9657 | |
9658 | /* REG_STRING starts *before* REGISTER_PREFIX. */ | |
9659 | ||
9660 | static const reg_entry * | |
9661 | parse_register (char *reg_string, char **end_op) | |
9662 | { | |
9663 | const reg_entry *r; | |
9664 | ||
9665 | if (*reg_string == REGISTER_PREFIX || allow_naked_reg) | |
9666 | r = parse_real_register (reg_string, end_op); | |
9667 | else | |
9668 | r = NULL; | |
9669 | if (!r) | |
9670 | { | |
9671 | char *save = input_line_pointer; | |
9672 | char c; | |
9673 | symbolS *symbolP; | |
9674 | ||
9675 | input_line_pointer = reg_string; | |
d02603dc | 9676 | c = get_symbol_name (®_string); |
4d1bb795 JB |
9677 | symbolP = symbol_find (reg_string); |
9678 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) | |
9679 | { | |
9680 | const expressionS *e = symbol_get_value_expression (symbolP); | |
9681 | ||
0398aac5 | 9682 | know (e->X_op == O_register); |
4eed87de | 9683 | know (e->X_add_number >= 0 |
c3fe08fa | 9684 | && (valueT) e->X_add_number < i386_regtab_size); |
4d1bb795 | 9685 | r = i386_regtab + e->X_add_number; |
d3bb6b49 IT |
9686 | if ((r->reg_flags & RegVRex)) |
9687 | i.need_vrex = 1; | |
4d1bb795 JB |
9688 | *end_op = input_line_pointer; |
9689 | } | |
9690 | *input_line_pointer = c; | |
9691 | input_line_pointer = save; | |
9692 | } | |
9693 | return r; | |
9694 | } | |
9695 | ||
9696 | int | |
9697 | i386_parse_name (char *name, expressionS *e, char *nextcharP) | |
9698 | { | |
9699 | const reg_entry *r; | |
9700 | char *end = input_line_pointer; | |
9701 | ||
9702 | *end = *nextcharP; | |
9703 | r = parse_register (name, &input_line_pointer); | |
9704 | if (r && end <= input_line_pointer) | |
9705 | { | |
9706 | *nextcharP = *input_line_pointer; | |
9707 | *input_line_pointer = 0; | |
9708 | e->X_op = O_register; | |
9709 | e->X_add_number = r - i386_regtab; | |
9710 | return 1; | |
9711 | } | |
9712 | input_line_pointer = end; | |
9713 | *end = 0; | |
ee86248c | 9714 | return intel_syntax ? i386_intel_parse_name (name, e) : 0; |
4d1bb795 JB |
9715 | } |
9716 | ||
9717 | void | |
9718 | md_operand (expressionS *e) | |
9719 | { | |
ee86248c JB |
9720 | char *end; |
9721 | const reg_entry *r; | |
4d1bb795 | 9722 | |
ee86248c JB |
9723 | switch (*input_line_pointer) |
9724 | { | |
9725 | case REGISTER_PREFIX: | |
9726 | r = parse_real_register (input_line_pointer, &end); | |
4d1bb795 JB |
9727 | if (r) |
9728 | { | |
9729 | e->X_op = O_register; | |
9730 | e->X_add_number = r - i386_regtab; | |
9731 | input_line_pointer = end; | |
9732 | } | |
ee86248c JB |
9733 | break; |
9734 | ||
9735 | case '[': | |
9c2799c2 | 9736 | gas_assert (intel_syntax); |
ee86248c JB |
9737 | end = input_line_pointer++; |
9738 | expression (e); | |
9739 | if (*input_line_pointer == ']') | |
9740 | { | |
9741 | ++input_line_pointer; | |
9742 | e->X_op_symbol = make_expr_symbol (e); | |
9743 | e->X_add_symbol = NULL; | |
9744 | e->X_add_number = 0; | |
9745 | e->X_op = O_index; | |
9746 | } | |
9747 | else | |
9748 | { | |
9749 | e->X_op = O_absent; | |
9750 | input_line_pointer = end; | |
9751 | } | |
9752 | break; | |
4d1bb795 JB |
9753 | } |
9754 | } | |
9755 | ||
252b5132 | 9756 | \f |
4cc782b5 | 9757 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
12b55ccc | 9758 | const char *md_shortopts = "kVQ:sqn"; |
252b5132 | 9759 | #else |
12b55ccc | 9760 | const char *md_shortopts = "qn"; |
252b5132 | 9761 | #endif |
6e0b89ee | 9762 | |
3e73aa7c | 9763 | #define OPTION_32 (OPTION_MD_BASE + 0) |
b3b91714 AM |
9764 | #define OPTION_64 (OPTION_MD_BASE + 1) |
9765 | #define OPTION_DIVIDE (OPTION_MD_BASE + 2) | |
9103f4f4 L |
9766 | #define OPTION_MARCH (OPTION_MD_BASE + 3) |
9767 | #define OPTION_MTUNE (OPTION_MD_BASE + 4) | |
1efbbeb4 L |
9768 | #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) |
9769 | #define OPTION_MSYNTAX (OPTION_MD_BASE + 6) | |
9770 | #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) | |
9771 | #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) | |
9772 | #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9) | |
c0f3af97 | 9773 | #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10) |
daf50ae7 | 9774 | #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11) |
7bab8ab5 JB |
9775 | #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12) |
9776 | #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13) | |
9777 | #define OPTION_X32 (OPTION_MD_BASE + 14) | |
7e8b059b | 9778 | #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15) |
43234a1e L |
9779 | #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16) |
9780 | #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17) | |
167ad85b | 9781 | #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18) |
d1982f93 | 9782 | #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19) |
d3d3c6db | 9783 | #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20) |
8dcea932 | 9784 | #define OPTION_MSHARED (OPTION_MD_BASE + 21) |
5db04b09 L |
9785 | #define OPTION_MAMD64 (OPTION_MD_BASE + 22) |
9786 | #define OPTION_MINTEL64 (OPTION_MD_BASE + 23) | |
e4e00185 | 9787 | #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24) |
0cb4071e | 9788 | #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25) |
b3b91714 | 9789 | |
99ad8390 NC |
9790 | struct option md_longopts[] = |
9791 | { | |
3e73aa7c | 9792 | {"32", no_argument, NULL, OPTION_32}, |
321098a5 | 9793 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 9794 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c | 9795 | {"64", no_argument, NULL, OPTION_64}, |
351f65ca L |
9796 | #endif |
9797 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
570561f7 | 9798 | {"x32", no_argument, NULL, OPTION_X32}, |
8dcea932 | 9799 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
6e0b89ee | 9800 | #endif |
b3b91714 | 9801 | {"divide", no_argument, NULL, OPTION_DIVIDE}, |
9103f4f4 L |
9802 | {"march", required_argument, NULL, OPTION_MARCH}, |
9803 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1efbbeb4 L |
9804 | {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, |
9805 | {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, | |
9806 | {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, | |
9807 | {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, | |
9808 | {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC}, | |
c0f3af97 | 9809 | {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX}, |
daf50ae7 | 9810 | {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK}, |
7bab8ab5 | 9811 | {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK}, |
539f890d | 9812 | {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR}, |
7e8b059b | 9813 | {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX}, |
43234a1e L |
9814 | {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG}, |
9815 | {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG}, | |
167ad85b TG |
9816 | # if defined (TE_PE) || defined (TE_PEP) |
9817 | {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ}, | |
9818 | #endif | |
d1982f93 | 9819 | {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX}, |
e4e00185 | 9820 | {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD}, |
0cb4071e | 9821 | {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS}, |
d3d3c6db | 9822 | {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG}, |
5db04b09 L |
9823 | {"mamd64", no_argument, NULL, OPTION_MAMD64}, |
9824 | {"mintel64", no_argument, NULL, OPTION_MINTEL64}, | |
252b5132 RH |
9825 | {NULL, no_argument, NULL, 0} |
9826 | }; | |
9827 | size_t md_longopts_size = sizeof (md_longopts); | |
9828 | ||
9829 | int | |
17b9d67d | 9830 | md_parse_option (int c, const char *arg) |
252b5132 | 9831 | { |
91d6fa6a | 9832 | unsigned int j; |
293f5f65 | 9833 | char *arch, *next, *saved; |
9103f4f4 | 9834 | |
252b5132 RH |
9835 | switch (c) |
9836 | { | |
12b55ccc L |
9837 | case 'n': |
9838 | optimize_align_code = 0; | |
9839 | break; | |
9840 | ||
a38cf1db AM |
9841 | case 'q': |
9842 | quiet_warnings = 1; | |
252b5132 RH |
9843 | break; |
9844 | ||
9845 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
9846 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
9847 | should be emitted or not. FIXME: Not implemented. */ | |
9848 | case 'Q': | |
252b5132 RH |
9849 | break; |
9850 | ||
9851 | /* -V: SVR4 argument to print version ID. */ | |
9852 | case 'V': | |
9853 | print_version_id (); | |
9854 | break; | |
9855 | ||
a38cf1db AM |
9856 | /* -k: Ignore for FreeBSD compatibility. */ |
9857 | case 'k': | |
252b5132 | 9858 | break; |
4cc782b5 ILT |
9859 | |
9860 | case 's': | |
9861 | /* -s: On i386 Solaris, this tells the native assembler to use | |
29b0f896 | 9862 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
4cc782b5 | 9863 | break; |
8dcea932 L |
9864 | |
9865 | case OPTION_MSHARED: | |
9866 | shared = 1; | |
9867 | break; | |
99ad8390 | 9868 | #endif |
321098a5 | 9869 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 9870 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c JH |
9871 | case OPTION_64: |
9872 | { | |
9873 | const char **list, **l; | |
9874 | ||
3e73aa7c JH |
9875 | list = bfd_target_list (); |
9876 | for (l = list; *l != NULL; l++) | |
8620418b | 9877 | if (CONST_STRNEQ (*l, "elf64-x86-64") |
99ad8390 NC |
9878 | || strcmp (*l, "coff-x86-64") == 0 |
9879 | || strcmp (*l, "pe-x86-64") == 0 | |
d382c579 TG |
9880 | || strcmp (*l, "pei-x86-64") == 0 |
9881 | || strcmp (*l, "mach-o-x86-64") == 0) | |
6e0b89ee AM |
9882 | { |
9883 | default_arch = "x86_64"; | |
9884 | break; | |
9885 | } | |
3e73aa7c | 9886 | if (*l == NULL) |
2b5d6a91 | 9887 | as_fatal (_("no compiled in support for x86_64")); |
3e73aa7c JH |
9888 | free (list); |
9889 | } | |
9890 | break; | |
9891 | #endif | |
252b5132 | 9892 | |
351f65ca | 9893 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
570561f7 | 9894 | case OPTION_X32: |
351f65ca L |
9895 | if (IS_ELF) |
9896 | { | |
9897 | const char **list, **l; | |
9898 | ||
9899 | list = bfd_target_list (); | |
9900 | for (l = list; *l != NULL; l++) | |
9901 | if (CONST_STRNEQ (*l, "elf32-x86-64")) | |
9902 | { | |
9903 | default_arch = "x86_64:32"; | |
9904 | break; | |
9905 | } | |
9906 | if (*l == NULL) | |
2b5d6a91 | 9907 | as_fatal (_("no compiled in support for 32bit x86_64")); |
351f65ca L |
9908 | free (list); |
9909 | } | |
9910 | else | |
9911 | as_fatal (_("32bit x86_64 is only supported for ELF")); | |
9912 | break; | |
9913 | #endif | |
9914 | ||
6e0b89ee AM |
9915 | case OPTION_32: |
9916 | default_arch = "i386"; | |
9917 | break; | |
9918 | ||
b3b91714 AM |
9919 | case OPTION_DIVIDE: |
9920 | #ifdef SVR4_COMMENT_CHARS | |
9921 | { | |
9922 | char *n, *t; | |
9923 | const char *s; | |
9924 | ||
add39d23 | 9925 | n = XNEWVEC (char, strlen (i386_comment_chars) + 1); |
b3b91714 AM |
9926 | t = n; |
9927 | for (s = i386_comment_chars; *s != '\0'; s++) | |
9928 | if (*s != '/') | |
9929 | *t++ = *s; | |
9930 | *t = '\0'; | |
9931 | i386_comment_chars = n; | |
9932 | } | |
9933 | #endif | |
9934 | break; | |
9935 | ||
9103f4f4 | 9936 | case OPTION_MARCH: |
293f5f65 L |
9937 | saved = xstrdup (arg); |
9938 | arch = saved; | |
9939 | /* Allow -march=+nosse. */ | |
9940 | if (*arch == '+') | |
9941 | arch++; | |
6305a203 | 9942 | do |
9103f4f4 | 9943 | { |
6305a203 | 9944 | if (*arch == '.') |
2b5d6a91 | 9945 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
9946 | next = strchr (arch, '+'); |
9947 | if (next) | |
9948 | *next++ = '\0'; | |
91d6fa6a | 9949 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 9950 | { |
91d6fa6a | 9951 | if (strcmp (arch, cpu_arch [j].name) == 0) |
ccc9c027 | 9952 | { |
6305a203 | 9953 | /* Processor. */ |
1ded5609 JB |
9954 | if (! cpu_arch[j].flags.bitfield.cpui386) |
9955 | continue; | |
9956 | ||
91d6fa6a | 9957 | cpu_arch_name = cpu_arch[j].name; |
6305a203 | 9958 | cpu_sub_arch_name = NULL; |
91d6fa6a NC |
9959 | cpu_arch_flags = cpu_arch[j].flags; |
9960 | cpu_arch_isa = cpu_arch[j].type; | |
9961 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
6305a203 L |
9962 | if (!cpu_arch_tune_set) |
9963 | { | |
9964 | cpu_arch_tune = cpu_arch_isa; | |
9965 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
9966 | } | |
9967 | break; | |
9968 | } | |
91d6fa6a NC |
9969 | else if (*cpu_arch [j].name == '.' |
9970 | && strcmp (arch, cpu_arch [j].name + 1) == 0) | |
6305a203 L |
9971 | { |
9972 | /* ISA entension. */ | |
9973 | i386_cpu_flags flags; | |
309d3373 | 9974 | |
293f5f65 L |
9975 | flags = cpu_flags_or (cpu_arch_flags, |
9976 | cpu_arch[j].flags); | |
81486035 L |
9977 | |
9978 | if (!valid_iamcu_cpu_flags (&flags)) | |
9979 | as_fatal (_("`%s' isn't valid for Intel MCU"), arch); | |
9980 | else if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
6305a203 L |
9981 | { |
9982 | if (cpu_sub_arch_name) | |
9983 | { | |
9984 | char *name = cpu_sub_arch_name; | |
9985 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 9986 | cpu_arch[j].name, |
1bf57e9f | 9987 | (const char *) NULL); |
6305a203 L |
9988 | free (name); |
9989 | } | |
9990 | else | |
91d6fa6a | 9991 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
6305a203 | 9992 | cpu_arch_flags = flags; |
a586129e | 9993 | cpu_arch_isa_flags = flags; |
6305a203 L |
9994 | } |
9995 | break; | |
ccc9c027 | 9996 | } |
9103f4f4 | 9997 | } |
6305a203 | 9998 | |
293f5f65 L |
9999 | if (j >= ARRAY_SIZE (cpu_arch)) |
10000 | { | |
10001 | /* Disable an ISA entension. */ | |
10002 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) | |
10003 | if (strcmp (arch, cpu_noarch [j].name) == 0) | |
10004 | { | |
10005 | i386_cpu_flags flags; | |
10006 | ||
10007 | flags = cpu_flags_and_not (cpu_arch_flags, | |
10008 | cpu_noarch[j].flags); | |
10009 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
10010 | { | |
10011 | if (cpu_sub_arch_name) | |
10012 | { | |
10013 | char *name = cpu_sub_arch_name; | |
10014 | cpu_sub_arch_name = concat (arch, | |
10015 | (const char *) NULL); | |
10016 | free (name); | |
10017 | } | |
10018 | else | |
10019 | cpu_sub_arch_name = xstrdup (arch); | |
10020 | cpu_arch_flags = flags; | |
10021 | cpu_arch_isa_flags = flags; | |
10022 | } | |
10023 | break; | |
10024 | } | |
10025 | ||
10026 | if (j >= ARRAY_SIZE (cpu_noarch)) | |
10027 | j = ARRAY_SIZE (cpu_arch); | |
10028 | } | |
10029 | ||
91d6fa6a | 10030 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 10031 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
10032 | |
10033 | arch = next; | |
9103f4f4 | 10034 | } |
293f5f65 L |
10035 | while (next != NULL); |
10036 | free (saved); | |
9103f4f4 L |
10037 | break; |
10038 | ||
10039 | case OPTION_MTUNE: | |
10040 | if (*arg == '.') | |
2b5d6a91 | 10041 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
91d6fa6a | 10042 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 10043 | { |
91d6fa6a | 10044 | if (strcmp (arg, cpu_arch [j].name) == 0) |
9103f4f4 | 10045 | { |
ccc9c027 | 10046 | cpu_arch_tune_set = 1; |
91d6fa6a NC |
10047 | cpu_arch_tune = cpu_arch [j].type; |
10048 | cpu_arch_tune_flags = cpu_arch[j].flags; | |
9103f4f4 L |
10049 | break; |
10050 | } | |
10051 | } | |
91d6fa6a | 10052 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 10053 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
9103f4f4 L |
10054 | break; |
10055 | ||
1efbbeb4 L |
10056 | case OPTION_MMNEMONIC: |
10057 | if (strcasecmp (arg, "att") == 0) | |
10058 | intel_mnemonic = 0; | |
10059 | else if (strcasecmp (arg, "intel") == 0) | |
10060 | intel_mnemonic = 1; | |
10061 | else | |
2b5d6a91 | 10062 | as_fatal (_("invalid -mmnemonic= option: `%s'"), arg); |
1efbbeb4 L |
10063 | break; |
10064 | ||
10065 | case OPTION_MSYNTAX: | |
10066 | if (strcasecmp (arg, "att") == 0) | |
10067 | intel_syntax = 0; | |
10068 | else if (strcasecmp (arg, "intel") == 0) | |
10069 | intel_syntax = 1; | |
10070 | else | |
2b5d6a91 | 10071 | as_fatal (_("invalid -msyntax= option: `%s'"), arg); |
1efbbeb4 L |
10072 | break; |
10073 | ||
10074 | case OPTION_MINDEX_REG: | |
10075 | allow_index_reg = 1; | |
10076 | break; | |
10077 | ||
10078 | case OPTION_MNAKED_REG: | |
10079 | allow_naked_reg = 1; | |
10080 | break; | |
10081 | ||
10082 | case OPTION_MOLD_GCC: | |
10083 | old_gcc = 1; | |
1efbbeb4 L |
10084 | break; |
10085 | ||
c0f3af97 L |
10086 | case OPTION_MSSE2AVX: |
10087 | sse2avx = 1; | |
10088 | break; | |
10089 | ||
daf50ae7 L |
10090 | case OPTION_MSSE_CHECK: |
10091 | if (strcasecmp (arg, "error") == 0) | |
7bab8ab5 | 10092 | sse_check = check_error; |
daf50ae7 | 10093 | else if (strcasecmp (arg, "warning") == 0) |
7bab8ab5 | 10094 | sse_check = check_warning; |
daf50ae7 | 10095 | else if (strcasecmp (arg, "none") == 0) |
7bab8ab5 | 10096 | sse_check = check_none; |
daf50ae7 | 10097 | else |
2b5d6a91 | 10098 | as_fatal (_("invalid -msse-check= option: `%s'"), arg); |
daf50ae7 L |
10099 | break; |
10100 | ||
7bab8ab5 JB |
10101 | case OPTION_MOPERAND_CHECK: |
10102 | if (strcasecmp (arg, "error") == 0) | |
10103 | operand_check = check_error; | |
10104 | else if (strcasecmp (arg, "warning") == 0) | |
10105 | operand_check = check_warning; | |
10106 | else if (strcasecmp (arg, "none") == 0) | |
10107 | operand_check = check_none; | |
10108 | else | |
10109 | as_fatal (_("invalid -moperand-check= option: `%s'"), arg); | |
10110 | break; | |
10111 | ||
539f890d L |
10112 | case OPTION_MAVXSCALAR: |
10113 | if (strcasecmp (arg, "128") == 0) | |
10114 | avxscalar = vex128; | |
10115 | else if (strcasecmp (arg, "256") == 0) | |
10116 | avxscalar = vex256; | |
10117 | else | |
2b5d6a91 | 10118 | as_fatal (_("invalid -mavxscalar= option: `%s'"), arg); |
539f890d L |
10119 | break; |
10120 | ||
7e8b059b L |
10121 | case OPTION_MADD_BND_PREFIX: |
10122 | add_bnd_prefix = 1; | |
10123 | break; | |
10124 | ||
43234a1e L |
10125 | case OPTION_MEVEXLIG: |
10126 | if (strcmp (arg, "128") == 0) | |
10127 | evexlig = evexl128; | |
10128 | else if (strcmp (arg, "256") == 0) | |
10129 | evexlig = evexl256; | |
10130 | else if (strcmp (arg, "512") == 0) | |
10131 | evexlig = evexl512; | |
10132 | else | |
10133 | as_fatal (_("invalid -mevexlig= option: `%s'"), arg); | |
10134 | break; | |
10135 | ||
d3d3c6db IT |
10136 | case OPTION_MEVEXRCIG: |
10137 | if (strcmp (arg, "rne") == 0) | |
10138 | evexrcig = rne; | |
10139 | else if (strcmp (arg, "rd") == 0) | |
10140 | evexrcig = rd; | |
10141 | else if (strcmp (arg, "ru") == 0) | |
10142 | evexrcig = ru; | |
10143 | else if (strcmp (arg, "rz") == 0) | |
10144 | evexrcig = rz; | |
10145 | else | |
10146 | as_fatal (_("invalid -mevexrcig= option: `%s'"), arg); | |
10147 | break; | |
10148 | ||
43234a1e L |
10149 | case OPTION_MEVEXWIG: |
10150 | if (strcmp (arg, "0") == 0) | |
10151 | evexwig = evexw0; | |
10152 | else if (strcmp (arg, "1") == 0) | |
10153 | evexwig = evexw1; | |
10154 | else | |
10155 | as_fatal (_("invalid -mevexwig= option: `%s'"), arg); | |
10156 | break; | |
10157 | ||
167ad85b TG |
10158 | # if defined (TE_PE) || defined (TE_PEP) |
10159 | case OPTION_MBIG_OBJ: | |
10160 | use_big_obj = 1; | |
10161 | break; | |
10162 | #endif | |
10163 | ||
d1982f93 | 10164 | case OPTION_MOMIT_LOCK_PREFIX: |
d022bddd IT |
10165 | if (strcasecmp (arg, "yes") == 0) |
10166 | omit_lock_prefix = 1; | |
10167 | else if (strcasecmp (arg, "no") == 0) | |
10168 | omit_lock_prefix = 0; | |
10169 | else | |
10170 | as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg); | |
10171 | break; | |
10172 | ||
e4e00185 AS |
10173 | case OPTION_MFENCE_AS_LOCK_ADD: |
10174 | if (strcasecmp (arg, "yes") == 0) | |
10175 | avoid_fence = 1; | |
10176 | else if (strcasecmp (arg, "no") == 0) | |
10177 | avoid_fence = 0; | |
10178 | else | |
10179 | as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg); | |
10180 | break; | |
10181 | ||
0cb4071e L |
10182 | case OPTION_MRELAX_RELOCATIONS: |
10183 | if (strcasecmp (arg, "yes") == 0) | |
10184 | generate_relax_relocations = 1; | |
10185 | else if (strcasecmp (arg, "no") == 0) | |
10186 | generate_relax_relocations = 0; | |
10187 | else | |
10188 | as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg); | |
10189 | break; | |
10190 | ||
5db04b09 | 10191 | case OPTION_MAMD64: |
e89c5eaa | 10192 | intel64 = 0; |
5db04b09 L |
10193 | break; |
10194 | ||
10195 | case OPTION_MINTEL64: | |
e89c5eaa | 10196 | intel64 = 1; |
5db04b09 L |
10197 | break; |
10198 | ||
252b5132 RH |
10199 | default: |
10200 | return 0; | |
10201 | } | |
10202 | return 1; | |
10203 | } | |
10204 | ||
8a2c8fef L |
10205 | #define MESSAGE_TEMPLATE \ |
10206 | " " | |
10207 | ||
293f5f65 L |
10208 | static char * |
10209 | output_message (FILE *stream, char *p, char *message, char *start, | |
10210 | int *left_p, const char *name, int len) | |
10211 | { | |
10212 | int size = sizeof (MESSAGE_TEMPLATE); | |
10213 | int left = *left_p; | |
10214 | ||
10215 | /* Reserve 2 spaces for ", " or ",\0" */ | |
10216 | left -= len + 2; | |
10217 | ||
10218 | /* Check if there is any room. */ | |
10219 | if (left >= 0) | |
10220 | { | |
10221 | if (p != start) | |
10222 | { | |
10223 | *p++ = ','; | |
10224 | *p++ = ' '; | |
10225 | } | |
10226 | p = mempcpy (p, name, len); | |
10227 | } | |
10228 | else | |
10229 | { | |
10230 | /* Output the current message now and start a new one. */ | |
10231 | *p++ = ','; | |
10232 | *p = '\0'; | |
10233 | fprintf (stream, "%s\n", message); | |
10234 | p = start; | |
10235 | left = size - (start - message) - len - 2; | |
10236 | ||
10237 | gas_assert (left >= 0); | |
10238 | ||
10239 | p = mempcpy (p, name, len); | |
10240 | } | |
10241 | ||
10242 | *left_p = left; | |
10243 | return p; | |
10244 | } | |
10245 | ||
8a2c8fef | 10246 | static void |
1ded5609 | 10247 | show_arch (FILE *stream, int ext, int check) |
8a2c8fef L |
10248 | { |
10249 | static char message[] = MESSAGE_TEMPLATE; | |
10250 | char *start = message + 27; | |
10251 | char *p; | |
10252 | int size = sizeof (MESSAGE_TEMPLATE); | |
10253 | int left; | |
10254 | const char *name; | |
10255 | int len; | |
10256 | unsigned int j; | |
10257 | ||
10258 | p = start; | |
10259 | left = size - (start - message); | |
10260 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) | |
10261 | { | |
10262 | /* Should it be skipped? */ | |
10263 | if (cpu_arch [j].skip) | |
10264 | continue; | |
10265 | ||
10266 | name = cpu_arch [j].name; | |
10267 | len = cpu_arch [j].len; | |
10268 | if (*name == '.') | |
10269 | { | |
10270 | /* It is an extension. Skip if we aren't asked to show it. */ | |
10271 | if (ext) | |
10272 | { | |
10273 | name++; | |
10274 | len--; | |
10275 | } | |
10276 | else | |
10277 | continue; | |
10278 | } | |
10279 | else if (ext) | |
10280 | { | |
10281 | /* It is an processor. Skip if we show only extension. */ | |
10282 | continue; | |
10283 | } | |
1ded5609 JB |
10284 | else if (check && ! cpu_arch[j].flags.bitfield.cpui386) |
10285 | { | |
10286 | /* It is an impossible processor - skip. */ | |
10287 | continue; | |
10288 | } | |
8a2c8fef | 10289 | |
293f5f65 | 10290 | p = output_message (stream, p, message, start, &left, name, len); |
8a2c8fef L |
10291 | } |
10292 | ||
293f5f65 L |
10293 | /* Display disabled extensions. */ |
10294 | if (ext) | |
10295 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) | |
10296 | { | |
10297 | name = cpu_noarch [j].name; | |
10298 | len = cpu_noarch [j].len; | |
10299 | p = output_message (stream, p, message, start, &left, name, | |
10300 | len); | |
10301 | } | |
10302 | ||
8a2c8fef L |
10303 | *p = '\0'; |
10304 | fprintf (stream, "%s\n", message); | |
10305 | } | |
10306 | ||
252b5132 | 10307 | void |
8a2c8fef | 10308 | md_show_usage (FILE *stream) |
252b5132 | 10309 | { |
4cc782b5 ILT |
10310 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
10311 | fprintf (stream, _("\ | |
a38cf1db AM |
10312 | -Q ignored\n\ |
10313 | -V print assembler version number\n\ | |
b3b91714 AM |
10314 | -k ignored\n")); |
10315 | #endif | |
10316 | fprintf (stream, _("\ | |
12b55ccc | 10317 | -n Do not optimize code alignment\n\ |
b3b91714 AM |
10318 | -q quieten some warnings\n")); |
10319 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
10320 | fprintf (stream, _("\ | |
a38cf1db | 10321 | -s ignored\n")); |
b3b91714 | 10322 | #endif |
321098a5 L |
10323 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
10324 | || defined (TE_PE) || defined (TE_PEP)) | |
751d281c | 10325 | fprintf (stream, _("\ |
570561f7 | 10326 | --32/--64/--x32 generate 32bit/64bit/x32 code\n")); |
751d281c | 10327 | #endif |
b3b91714 AM |
10328 | #ifdef SVR4_COMMENT_CHARS |
10329 | fprintf (stream, _("\ | |
10330 | --divide do not treat `/' as a comment character\n")); | |
a38cf1db AM |
10331 | #else |
10332 | fprintf (stream, _("\ | |
b3b91714 | 10333 | --divide ignored\n")); |
4cc782b5 | 10334 | #endif |
9103f4f4 | 10335 | fprintf (stream, _("\ |
6305a203 | 10336 | -march=CPU[,+EXTENSION...]\n\ |
8a2c8fef | 10337 | generate code for CPU and EXTENSION, CPU is one of:\n")); |
1ded5609 | 10338 | show_arch (stream, 0, 1); |
8a2c8fef L |
10339 | fprintf (stream, _("\ |
10340 | EXTENSION is combination of:\n")); | |
1ded5609 | 10341 | show_arch (stream, 1, 0); |
6305a203 | 10342 | fprintf (stream, _("\ |
8a2c8fef | 10343 | -mtune=CPU optimize for CPU, CPU is one of:\n")); |
1ded5609 | 10344 | show_arch (stream, 0, 0); |
ba104c83 | 10345 | fprintf (stream, _("\ |
c0f3af97 L |
10346 | -msse2avx encode SSE instructions with VEX prefix\n")); |
10347 | fprintf (stream, _("\ | |
daf50ae7 L |
10348 | -msse-check=[none|error|warning]\n\ |
10349 | check SSE instructions\n")); | |
10350 | fprintf (stream, _("\ | |
7bab8ab5 JB |
10351 | -moperand-check=[none|error|warning]\n\ |
10352 | check operand combinations for validity\n")); | |
10353 | fprintf (stream, _("\ | |
539f890d L |
10354 | -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\ |
10355 | length\n")); | |
10356 | fprintf (stream, _("\ | |
43234a1e L |
10357 | -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\ |
10358 | length\n")); | |
10359 | fprintf (stream, _("\ | |
10360 | -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\ | |
10361 | for EVEX.W bit ignored instructions\n")); | |
10362 | fprintf (stream, _("\ | |
d3d3c6db IT |
10363 | -mevexrcig=[rne|rd|ru|rz]\n\ |
10364 | encode EVEX instructions with specific EVEX.RC value\n\ | |
10365 | for SAE-only ignored instructions\n")); | |
10366 | fprintf (stream, _("\ | |
ba104c83 L |
10367 | -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n")); |
10368 | fprintf (stream, _("\ | |
10369 | -msyntax=[att|intel] use AT&T/Intel syntax\n")); | |
10370 | fprintf (stream, _("\ | |
10371 | -mindex-reg support pseudo index registers\n")); | |
10372 | fprintf (stream, _("\ | |
10373 | -mnaked-reg don't require `%%' prefix for registers\n")); | |
10374 | fprintf (stream, _("\ | |
10375 | -mold-gcc support old (<= 2.8.1) versions of gcc\n")); | |
7e8b059b L |
10376 | fprintf (stream, _("\ |
10377 | -madd-bnd-prefix add BND prefix for all valid branches\n")); | |
8dcea932 L |
10378 | fprintf (stream, _("\ |
10379 | -mshared disable branch optimization for shared code\n")); | |
167ad85b TG |
10380 | # if defined (TE_PE) || defined (TE_PEP) |
10381 | fprintf (stream, _("\ | |
10382 | -mbig-obj generate big object files\n")); | |
10383 | #endif | |
d022bddd IT |
10384 | fprintf (stream, _("\ |
10385 | -momit-lock-prefix=[no|yes]\n\ | |
10386 | strip all lock prefixes\n")); | |
5db04b09 | 10387 | fprintf (stream, _("\ |
e4e00185 AS |
10388 | -mfence-as-lock-add=[no|yes]\n\ |
10389 | encode lfence, mfence and sfence as\n\ | |
10390 | lock addl $0x0, (%%{re}sp)\n")); | |
10391 | fprintf (stream, _("\ | |
0cb4071e L |
10392 | -mrelax-relocations=[no|yes]\n\ |
10393 | generate relax relocations\n")); | |
10394 | fprintf (stream, _("\ | |
5db04b09 L |
10395 | -mamd64 accept only AMD64 ISA\n")); |
10396 | fprintf (stream, _("\ | |
10397 | -mintel64 accept only Intel64 ISA\n")); | |
252b5132 RH |
10398 | } |
10399 | ||
3e73aa7c | 10400 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
321098a5 | 10401 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
e57f8c65 | 10402 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
252b5132 RH |
10403 | |
10404 | /* Pick the target format to use. */ | |
10405 | ||
47926f60 | 10406 | const char * |
e3bb37b5 | 10407 | i386_target_format (void) |
252b5132 | 10408 | { |
351f65ca L |
10409 | if (!strncmp (default_arch, "x86_64", 6)) |
10410 | { | |
10411 | update_code_flag (CODE_64BIT, 1); | |
10412 | if (default_arch[6] == '\0') | |
7f56bc95 | 10413 | x86_elf_abi = X86_64_ABI; |
351f65ca | 10414 | else |
7f56bc95 | 10415 | x86_elf_abi = X86_64_X32_ABI; |
351f65ca | 10416 | } |
3e73aa7c | 10417 | else if (!strcmp (default_arch, "i386")) |
78f12dd3 | 10418 | update_code_flag (CODE_32BIT, 1); |
5197d474 L |
10419 | else if (!strcmp (default_arch, "iamcu")) |
10420 | { | |
10421 | update_code_flag (CODE_32BIT, 1); | |
10422 | if (cpu_arch_isa == PROCESSOR_UNKNOWN) | |
10423 | { | |
10424 | static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS; | |
10425 | cpu_arch_name = "iamcu"; | |
10426 | cpu_sub_arch_name = NULL; | |
10427 | cpu_arch_flags = iamcu_flags; | |
10428 | cpu_arch_isa = PROCESSOR_IAMCU; | |
10429 | cpu_arch_isa_flags = iamcu_flags; | |
10430 | if (!cpu_arch_tune_set) | |
10431 | { | |
10432 | cpu_arch_tune = cpu_arch_isa; | |
10433 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
10434 | } | |
10435 | } | |
10436 | else | |
10437 | as_fatal (_("Intel MCU doesn't support `%s' architecture"), | |
10438 | cpu_arch_name); | |
10439 | } | |
3e73aa7c | 10440 | else |
2b5d6a91 | 10441 | as_fatal (_("unknown architecture")); |
89507696 JB |
10442 | |
10443 | if (cpu_flags_all_zero (&cpu_arch_isa_flags)) | |
10444 | cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
10445 | if (cpu_flags_all_zero (&cpu_arch_tune_flags)) | |
10446 | cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
10447 | ||
252b5132 RH |
10448 | switch (OUTPUT_FLAVOR) |
10449 | { | |
9384f2ff | 10450 | #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT) |
4c63da97 | 10451 | case bfd_target_aout_flavour: |
47926f60 | 10452 | return AOUT_TARGET_FORMAT; |
4c63da97 | 10453 | #endif |
9384f2ff AM |
10454 | #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF) |
10455 | # if defined (TE_PE) || defined (TE_PEP) | |
10456 | case bfd_target_coff_flavour: | |
167ad85b TG |
10457 | if (flag_code == CODE_64BIT) |
10458 | return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64"; | |
10459 | else | |
10460 | return "pe-i386"; | |
9384f2ff | 10461 | # elif defined (TE_GO32) |
0561d57c JK |
10462 | case bfd_target_coff_flavour: |
10463 | return "coff-go32"; | |
9384f2ff | 10464 | # else |
252b5132 RH |
10465 | case bfd_target_coff_flavour: |
10466 | return "coff-i386"; | |
9384f2ff | 10467 | # endif |
4c63da97 | 10468 | #endif |
3e73aa7c | 10469 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 10470 | case bfd_target_elf_flavour: |
3e73aa7c | 10471 | { |
351f65ca L |
10472 | const char *format; |
10473 | ||
10474 | switch (x86_elf_abi) | |
4fa24527 | 10475 | { |
351f65ca L |
10476 | default: |
10477 | format = ELF_TARGET_FORMAT; | |
10478 | break; | |
7f56bc95 | 10479 | case X86_64_ABI: |
351f65ca | 10480 | use_rela_relocations = 1; |
4fa24527 | 10481 | object_64bit = 1; |
351f65ca L |
10482 | format = ELF_TARGET_FORMAT64; |
10483 | break; | |
7f56bc95 | 10484 | case X86_64_X32_ABI: |
4fa24527 | 10485 | use_rela_relocations = 1; |
351f65ca | 10486 | object_64bit = 1; |
862be3fb | 10487 | disallow_64bit_reloc = 1; |
351f65ca L |
10488 | format = ELF_TARGET_FORMAT32; |
10489 | break; | |
4fa24527 | 10490 | } |
3632d14b | 10491 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 10492 | { |
7f56bc95 | 10493 | if (x86_elf_abi != X86_64_ABI) |
8a9036a4 L |
10494 | as_fatal (_("Intel L1OM is 64bit only")); |
10495 | return ELF_TARGET_L1OM_FORMAT; | |
10496 | } | |
b49f93f6 | 10497 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
7a9068fe L |
10498 | { |
10499 | if (x86_elf_abi != X86_64_ABI) | |
10500 | as_fatal (_("Intel K1OM is 64bit only")); | |
10501 | return ELF_TARGET_K1OM_FORMAT; | |
10502 | } | |
81486035 L |
10503 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
10504 | { | |
10505 | if (x86_elf_abi != I386_ABI) | |
10506 | as_fatal (_("Intel MCU is 32bit only")); | |
10507 | return ELF_TARGET_IAMCU_FORMAT; | |
10508 | } | |
8a9036a4 | 10509 | else |
351f65ca | 10510 | return format; |
3e73aa7c | 10511 | } |
e57f8c65 TG |
10512 | #endif |
10513 | #if defined (OBJ_MACH_O) | |
10514 | case bfd_target_mach_o_flavour: | |
d382c579 TG |
10515 | if (flag_code == CODE_64BIT) |
10516 | { | |
10517 | use_rela_relocations = 1; | |
10518 | object_64bit = 1; | |
10519 | return "mach-o-x86-64"; | |
10520 | } | |
10521 | else | |
10522 | return "mach-o-i386"; | |
4c63da97 | 10523 | #endif |
252b5132 RH |
10524 | default: |
10525 | abort (); | |
10526 | return NULL; | |
10527 | } | |
10528 | } | |
10529 | ||
47926f60 | 10530 | #endif /* OBJ_MAYBE_ more than one */ |
252b5132 | 10531 | \f |
252b5132 | 10532 | symbolS * |
7016a5d5 | 10533 | md_undefined_symbol (char *name) |
252b5132 | 10534 | { |
18dc2407 ILT |
10535 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
10536 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
10537 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
10538 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
10539 | { |
10540 | if (!GOT_symbol) | |
10541 | { | |
10542 | if (symbol_find (name)) | |
10543 | as_bad (_("GOT already in symbol table")); | |
10544 | GOT_symbol = symbol_new (name, undefined_section, | |
10545 | (valueT) 0, &zero_address_frag); | |
10546 | }; | |
10547 | return GOT_symbol; | |
10548 | } | |
252b5132 RH |
10549 | return 0; |
10550 | } | |
10551 | ||
10552 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 10553 | |
252b5132 | 10554 | valueT |
7016a5d5 | 10555 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
252b5132 | 10556 | { |
4c63da97 AM |
10557 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
10558 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
10559 | { | |
10560 | /* For a.out, force the section size to be aligned. If we don't do | |
10561 | this, BFD will align it for us, but it will not write out the | |
10562 | final bytes of the section. This may be a bug in BFD, but it is | |
10563 | easier to fix it here since that is how the other a.out targets | |
10564 | work. */ | |
10565 | int align; | |
10566 | ||
10567 | align = bfd_get_section_alignment (stdoutput, segment); | |
8d3842cd | 10568 | size = ((size + (1 << align) - 1) & (-((valueT) 1 << align))); |
4c63da97 | 10569 | } |
252b5132 RH |
10570 | #endif |
10571 | ||
10572 | return size; | |
10573 | } | |
10574 | ||
10575 | /* On the i386, PC-relative offsets are relative to the start of the | |
10576 | next instruction. That is, the address of the offset, plus its | |
10577 | size, since the offset is always the last part of the insn. */ | |
10578 | ||
10579 | long | |
e3bb37b5 | 10580 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
10581 | { |
10582 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
10583 | } | |
10584 | ||
10585 | #ifndef I386COFF | |
10586 | ||
10587 | static void | |
e3bb37b5 | 10588 | s_bss (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 10589 | { |
29b0f896 | 10590 | int temp; |
252b5132 | 10591 | |
8a75718c JB |
10592 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
10593 | if (IS_ELF) | |
10594 | obj_elf_section_change_hook (); | |
10595 | #endif | |
252b5132 RH |
10596 | temp = get_absolute_expression (); |
10597 | subseg_set (bss_section, (subsegT) temp); | |
10598 | demand_empty_rest_of_line (); | |
10599 | } | |
10600 | ||
10601 | #endif | |
10602 | ||
252b5132 | 10603 | void |
e3bb37b5 | 10604 | i386_validate_fix (fixS *fixp) |
252b5132 | 10605 | { |
02a86693 | 10606 | if (fixp->fx_subsy) |
252b5132 | 10607 | { |
02a86693 | 10608 | if (fixp->fx_subsy == GOT_symbol) |
23df1078 | 10609 | { |
02a86693 L |
10610 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
10611 | { | |
10612 | if (!object_64bit) | |
10613 | abort (); | |
10614 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
10615 | if (fixp->fx_tcbit2) | |
56ceb5b5 L |
10616 | fixp->fx_r_type = (fixp->fx_tcbit |
10617 | ? BFD_RELOC_X86_64_REX_GOTPCRELX | |
10618 | : BFD_RELOC_X86_64_GOTPCRELX); | |
02a86693 L |
10619 | else |
10620 | #endif | |
10621 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
10622 | } | |
d6ab8113 | 10623 | else |
02a86693 L |
10624 | { |
10625 | if (!object_64bit) | |
10626 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
10627 | else | |
10628 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; | |
10629 | } | |
10630 | fixp->fx_subsy = 0; | |
23df1078 | 10631 | } |
252b5132 | 10632 | } |
02a86693 L |
10633 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
10634 | else if (!object_64bit) | |
10635 | { | |
10636 | if (fixp->fx_r_type == BFD_RELOC_386_GOT32 | |
10637 | && fixp->fx_tcbit2) | |
10638 | fixp->fx_r_type = BFD_RELOC_386_GOT32X; | |
10639 | } | |
10640 | #endif | |
252b5132 RH |
10641 | } |
10642 | ||
252b5132 | 10643 | arelent * |
7016a5d5 | 10644 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
10645 | { |
10646 | arelent *rel; | |
10647 | bfd_reloc_code_real_type code; | |
10648 | ||
10649 | switch (fixp->fx_r_type) | |
10650 | { | |
8ce3d284 | 10651 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
10652 | case BFD_RELOC_SIZE32: |
10653 | case BFD_RELOC_SIZE64: | |
10654 | if (S_IS_DEFINED (fixp->fx_addsy) | |
10655 | && !S_IS_EXTERNAL (fixp->fx_addsy)) | |
10656 | { | |
10657 | /* Resolve size relocation against local symbol to size of | |
10658 | the symbol plus addend. */ | |
10659 | valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset; | |
10660 | if (fixp->fx_r_type == BFD_RELOC_SIZE32 | |
10661 | && !fits_in_unsigned_long (value)) | |
10662 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
10663 | _("symbol size computation overflow")); | |
10664 | fixp->fx_addsy = NULL; | |
10665 | fixp->fx_subsy = NULL; | |
10666 | md_apply_fix (fixp, (valueT *) &value, NULL); | |
10667 | return NULL; | |
10668 | } | |
8ce3d284 | 10669 | #endif |
8fd4256d | 10670 | |
3e73aa7c JH |
10671 | case BFD_RELOC_X86_64_PLT32: |
10672 | case BFD_RELOC_X86_64_GOT32: | |
10673 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
10674 | case BFD_RELOC_X86_64_GOTPCRELX: |
10675 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
252b5132 RH |
10676 | case BFD_RELOC_386_PLT32: |
10677 | case BFD_RELOC_386_GOT32: | |
02a86693 | 10678 | case BFD_RELOC_386_GOT32X: |
252b5132 RH |
10679 | case BFD_RELOC_386_GOTOFF: |
10680 | case BFD_RELOC_386_GOTPC: | |
13ae64f3 JJ |
10681 | case BFD_RELOC_386_TLS_GD: |
10682 | case BFD_RELOC_386_TLS_LDM: | |
10683 | case BFD_RELOC_386_TLS_LDO_32: | |
10684 | case BFD_RELOC_386_TLS_IE_32: | |
37e55690 JJ |
10685 | case BFD_RELOC_386_TLS_IE: |
10686 | case BFD_RELOC_386_TLS_GOTIE: | |
13ae64f3 JJ |
10687 | case BFD_RELOC_386_TLS_LE_32: |
10688 | case BFD_RELOC_386_TLS_LE: | |
67a4f2b7 AO |
10689 | case BFD_RELOC_386_TLS_GOTDESC: |
10690 | case BFD_RELOC_386_TLS_DESC_CALL: | |
bffbf940 JJ |
10691 | case BFD_RELOC_X86_64_TLSGD: |
10692 | case BFD_RELOC_X86_64_TLSLD: | |
10693 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 10694 | case BFD_RELOC_X86_64_DTPOFF64: |
bffbf940 JJ |
10695 | case BFD_RELOC_X86_64_GOTTPOFF: |
10696 | case BFD_RELOC_X86_64_TPOFF32: | |
d6ab8113 JB |
10697 | case BFD_RELOC_X86_64_TPOFF64: |
10698 | case BFD_RELOC_X86_64_GOTOFF64: | |
10699 | case BFD_RELOC_X86_64_GOTPC32: | |
7b81dfbb AJ |
10700 | case BFD_RELOC_X86_64_GOT64: |
10701 | case BFD_RELOC_X86_64_GOTPCREL64: | |
10702 | case BFD_RELOC_X86_64_GOTPC64: | |
10703 | case BFD_RELOC_X86_64_GOTPLT64: | |
10704 | case BFD_RELOC_X86_64_PLTOFF64: | |
67a4f2b7 AO |
10705 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
10706 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
252b5132 RH |
10707 | case BFD_RELOC_RVA: |
10708 | case BFD_RELOC_VTABLE_ENTRY: | |
10709 | case BFD_RELOC_VTABLE_INHERIT: | |
6482c264 NC |
10710 | #ifdef TE_PE |
10711 | case BFD_RELOC_32_SECREL: | |
10712 | #endif | |
252b5132 RH |
10713 | code = fixp->fx_r_type; |
10714 | break; | |
dbbaec26 L |
10715 | case BFD_RELOC_X86_64_32S: |
10716 | if (!fixp->fx_pcrel) | |
10717 | { | |
10718 | /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ | |
10719 | code = fixp->fx_r_type; | |
10720 | break; | |
10721 | } | |
252b5132 | 10722 | default: |
93382f6d | 10723 | if (fixp->fx_pcrel) |
252b5132 | 10724 | { |
93382f6d AM |
10725 | switch (fixp->fx_size) |
10726 | { | |
10727 | default: | |
b091f402 AM |
10728 | as_bad_where (fixp->fx_file, fixp->fx_line, |
10729 | _("can not do %d byte pc-relative relocation"), | |
10730 | fixp->fx_size); | |
93382f6d AM |
10731 | code = BFD_RELOC_32_PCREL; |
10732 | break; | |
10733 | case 1: code = BFD_RELOC_8_PCREL; break; | |
10734 | case 2: code = BFD_RELOC_16_PCREL; break; | |
d258b828 | 10735 | case 4: code = BFD_RELOC_32_PCREL; break; |
d6ab8113 JB |
10736 | #ifdef BFD64 |
10737 | case 8: code = BFD_RELOC_64_PCREL; break; | |
10738 | #endif | |
93382f6d AM |
10739 | } |
10740 | } | |
10741 | else | |
10742 | { | |
10743 | switch (fixp->fx_size) | |
10744 | { | |
10745 | default: | |
b091f402 AM |
10746 | as_bad_where (fixp->fx_file, fixp->fx_line, |
10747 | _("can not do %d byte relocation"), | |
10748 | fixp->fx_size); | |
93382f6d AM |
10749 | code = BFD_RELOC_32; |
10750 | break; | |
10751 | case 1: code = BFD_RELOC_8; break; | |
10752 | case 2: code = BFD_RELOC_16; break; | |
10753 | case 4: code = BFD_RELOC_32; break; | |
937149dd | 10754 | #ifdef BFD64 |
3e73aa7c | 10755 | case 8: code = BFD_RELOC_64; break; |
937149dd | 10756 | #endif |
93382f6d | 10757 | } |
252b5132 RH |
10758 | } |
10759 | break; | |
10760 | } | |
252b5132 | 10761 | |
d182319b JB |
10762 | if ((code == BFD_RELOC_32 |
10763 | || code == BFD_RELOC_32_PCREL | |
10764 | || code == BFD_RELOC_X86_64_32S) | |
252b5132 RH |
10765 | && GOT_symbol |
10766 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c | 10767 | { |
4fa24527 | 10768 | if (!object_64bit) |
d6ab8113 JB |
10769 | code = BFD_RELOC_386_GOTPC; |
10770 | else | |
10771 | code = BFD_RELOC_X86_64_GOTPC32; | |
3e73aa7c | 10772 | } |
7b81dfbb AJ |
10773 | if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) |
10774 | && GOT_symbol | |
10775 | && fixp->fx_addsy == GOT_symbol) | |
10776 | { | |
10777 | code = BFD_RELOC_X86_64_GOTPC64; | |
10778 | } | |
252b5132 | 10779 | |
add39d23 TS |
10780 | rel = XNEW (arelent); |
10781 | rel->sym_ptr_ptr = XNEW (asymbol *); | |
49309057 | 10782 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
10783 | |
10784 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
c87db184 | 10785 | |
3e73aa7c JH |
10786 | if (!use_rela_relocations) |
10787 | { | |
10788 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
10789 | vtable entry to be used in the relocation's section offset. */ | |
10790 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
10791 | rel->address = fixp->fx_offset; | |
fbeb56a4 DK |
10792 | #if defined (OBJ_COFF) && defined (TE_PE) |
10793 | else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy)) | |
10794 | rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2); | |
10795 | else | |
10796 | #endif | |
c6682705 | 10797 | rel->addend = 0; |
3e73aa7c JH |
10798 | } |
10799 | /* Use the rela in 64bit mode. */ | |
252b5132 | 10800 | else |
3e73aa7c | 10801 | { |
862be3fb L |
10802 | if (disallow_64bit_reloc) |
10803 | switch (code) | |
10804 | { | |
862be3fb L |
10805 | case BFD_RELOC_X86_64_DTPOFF64: |
10806 | case BFD_RELOC_X86_64_TPOFF64: | |
10807 | case BFD_RELOC_64_PCREL: | |
10808 | case BFD_RELOC_X86_64_GOTOFF64: | |
10809 | case BFD_RELOC_X86_64_GOT64: | |
10810 | case BFD_RELOC_X86_64_GOTPCREL64: | |
10811 | case BFD_RELOC_X86_64_GOTPC64: | |
10812 | case BFD_RELOC_X86_64_GOTPLT64: | |
10813 | case BFD_RELOC_X86_64_PLTOFF64: | |
10814 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
10815 | _("cannot represent relocation type %s in x32 mode"), | |
10816 | bfd_get_reloc_code_name (code)); | |
10817 | break; | |
10818 | default: | |
10819 | break; | |
10820 | } | |
10821 | ||
062cd5e7 AS |
10822 | if (!fixp->fx_pcrel) |
10823 | rel->addend = fixp->fx_offset; | |
10824 | else | |
10825 | switch (code) | |
10826 | { | |
10827 | case BFD_RELOC_X86_64_PLT32: | |
10828 | case BFD_RELOC_X86_64_GOT32: | |
10829 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
10830 | case BFD_RELOC_X86_64_GOTPCRELX: |
10831 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
bffbf940 JJ |
10832 | case BFD_RELOC_X86_64_TLSGD: |
10833 | case BFD_RELOC_X86_64_TLSLD: | |
10834 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 AO |
10835 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
10836 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
062cd5e7 AS |
10837 | rel->addend = fixp->fx_offset - fixp->fx_size; |
10838 | break; | |
10839 | default: | |
10840 | rel->addend = (section->vma | |
10841 | - fixp->fx_size | |
10842 | + fixp->fx_addnumber | |
10843 | + md_pcrel_from (fixp)); | |
10844 | break; | |
10845 | } | |
3e73aa7c JH |
10846 | } |
10847 | ||
252b5132 RH |
10848 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
10849 | if (rel->howto == NULL) | |
10850 | { | |
10851 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 10852 | _("cannot represent relocation type %s"), |
252b5132 RH |
10853 | bfd_get_reloc_code_name (code)); |
10854 | /* Set howto to a garbage value so that we can keep going. */ | |
10855 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
9c2799c2 | 10856 | gas_assert (rel->howto != NULL); |
252b5132 RH |
10857 | } |
10858 | ||
10859 | return rel; | |
10860 | } | |
10861 | ||
ee86248c | 10862 | #include "tc-i386-intel.c" |
54cfded0 | 10863 | |
a60de03c JB |
10864 | void |
10865 | tc_x86_parse_to_dw2regnum (expressionS *exp) | |
54cfded0 | 10866 | { |
a60de03c JB |
10867 | int saved_naked_reg; |
10868 | char saved_register_dot; | |
54cfded0 | 10869 | |
a60de03c JB |
10870 | saved_naked_reg = allow_naked_reg; |
10871 | allow_naked_reg = 1; | |
10872 | saved_register_dot = register_chars['.']; | |
10873 | register_chars['.'] = '.'; | |
10874 | allow_pseudo_reg = 1; | |
10875 | expression_and_evaluate (exp); | |
10876 | allow_pseudo_reg = 0; | |
10877 | register_chars['.'] = saved_register_dot; | |
10878 | allow_naked_reg = saved_naked_reg; | |
10879 | ||
e96d56a1 | 10880 | if (exp->X_op == O_register && exp->X_add_number >= 0) |
54cfded0 | 10881 | { |
a60de03c JB |
10882 | if ((addressT) exp->X_add_number < i386_regtab_size) |
10883 | { | |
10884 | exp->X_op = O_constant; | |
10885 | exp->X_add_number = i386_regtab[exp->X_add_number] | |
10886 | .dw2_regnum[flag_code >> 1]; | |
10887 | } | |
10888 | else | |
10889 | exp->X_op = O_illegal; | |
54cfded0 | 10890 | } |
54cfded0 AM |
10891 | } |
10892 | ||
10893 | void | |
10894 | tc_x86_frame_initial_instructions (void) | |
10895 | { | |
a60de03c JB |
10896 | static unsigned int sp_regno[2]; |
10897 | ||
10898 | if (!sp_regno[flag_code >> 1]) | |
10899 | { | |
10900 | char *saved_input = input_line_pointer; | |
10901 | char sp[][4] = {"esp", "rsp"}; | |
10902 | expressionS exp; | |
a4447b93 | 10903 | |
a60de03c JB |
10904 | input_line_pointer = sp[flag_code >> 1]; |
10905 | tc_x86_parse_to_dw2regnum (&exp); | |
9c2799c2 | 10906 | gas_assert (exp.X_op == O_constant); |
a60de03c JB |
10907 | sp_regno[flag_code >> 1] = exp.X_add_number; |
10908 | input_line_pointer = saved_input; | |
10909 | } | |
a4447b93 | 10910 | |
61ff971f L |
10911 | cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment); |
10912 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); | |
54cfded0 | 10913 | } |
d2b2c203 | 10914 | |
d7921315 L |
10915 | int |
10916 | x86_dwarf2_addr_size (void) | |
10917 | { | |
10918 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) | |
10919 | if (x86_elf_abi == X86_64_X32_ABI) | |
10920 | return 4; | |
10921 | #endif | |
10922 | return bfd_arch_bits_per_address (stdoutput) / 8; | |
10923 | } | |
10924 | ||
d2b2c203 DJ |
10925 | int |
10926 | i386_elf_section_type (const char *str, size_t len) | |
10927 | { | |
10928 | if (flag_code == CODE_64BIT | |
10929 | && len == sizeof ("unwind") - 1 | |
10930 | && strncmp (str, "unwind", 6) == 0) | |
10931 | return SHT_X86_64_UNWIND; | |
10932 | ||
10933 | return -1; | |
10934 | } | |
bb41ade5 | 10935 | |
ad5fec3b EB |
10936 | #ifdef TE_SOLARIS |
10937 | void | |
10938 | i386_solaris_fix_up_eh_frame (segT sec) | |
10939 | { | |
10940 | if (flag_code == CODE_64BIT) | |
10941 | elf_section_type (sec) = SHT_X86_64_UNWIND; | |
10942 | } | |
10943 | #endif | |
10944 | ||
bb41ade5 AM |
10945 | #ifdef TE_PE |
10946 | void | |
10947 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) | |
10948 | { | |
91d6fa6a | 10949 | expressionS exp; |
bb41ade5 | 10950 | |
91d6fa6a NC |
10951 | exp.X_op = O_secrel; |
10952 | exp.X_add_symbol = symbol; | |
10953 | exp.X_add_number = 0; | |
10954 | emit_expr (&exp, size); | |
bb41ade5 AM |
10955 | } |
10956 | #endif | |
3b22753a L |
10957 | |
10958 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
10959 | /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ | |
10960 | ||
01e1a5bc | 10961 | bfd_vma |
6d4af3c2 | 10962 | x86_64_section_letter (int letter, const char **ptr_msg) |
3b22753a L |
10963 | { |
10964 | if (flag_code == CODE_64BIT) | |
10965 | { | |
10966 | if (letter == 'l') | |
10967 | return SHF_X86_64_LARGE; | |
10968 | ||
8f3bae45 | 10969 | *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string"); |
64e74474 | 10970 | } |
3b22753a | 10971 | else |
8f3bae45 | 10972 | *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string"); |
3b22753a L |
10973 | return -1; |
10974 | } | |
10975 | ||
01e1a5bc | 10976 | bfd_vma |
3b22753a L |
10977 | x86_64_section_word (char *str, size_t len) |
10978 | { | |
8620418b | 10979 | if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large")) |
3b22753a L |
10980 | return SHF_X86_64_LARGE; |
10981 | ||
10982 | return -1; | |
10983 | } | |
10984 | ||
10985 | static void | |
10986 | handle_large_common (int small ATTRIBUTE_UNUSED) | |
10987 | { | |
10988 | if (flag_code != CODE_64BIT) | |
10989 | { | |
10990 | s_comm_internal (0, elf_common_parse); | |
10991 | as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); | |
10992 | } | |
10993 | else | |
10994 | { | |
10995 | static segT lbss_section; | |
10996 | asection *saved_com_section_ptr = elf_com_section_ptr; | |
10997 | asection *saved_bss_section = bss_section; | |
10998 | ||
10999 | if (lbss_section == NULL) | |
11000 | { | |
11001 | flagword applicable; | |
11002 | segT seg = now_seg; | |
11003 | subsegT subseg = now_subseg; | |
11004 | ||
11005 | /* The .lbss section is for local .largecomm symbols. */ | |
11006 | lbss_section = subseg_new (".lbss", 0); | |
11007 | applicable = bfd_applicable_section_flags (stdoutput); | |
11008 | bfd_set_section_flags (stdoutput, lbss_section, | |
11009 | applicable & SEC_ALLOC); | |
11010 | seg_info (lbss_section)->bss = 1; | |
11011 | ||
11012 | subseg_set (seg, subseg); | |
11013 | } | |
11014 | ||
11015 | elf_com_section_ptr = &_bfd_elf_large_com_section; | |
11016 | bss_section = lbss_section; | |
11017 | ||
11018 | s_comm_internal (0, elf_common_parse); | |
11019 | ||
11020 | elf_com_section_ptr = saved_com_section_ptr; | |
11021 | bss_section = saved_bss_section; | |
11022 | } | |
11023 | } | |
11024 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |