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x86/Intel: don't accept bogus instructions
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
6f2750fe 2 Copyright (C) 1989-2016 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d
L		 68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 86#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 87/* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89#define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91#define END_OF_INSN '\0'
92
93/*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100typedef struct
101{
d3ce72d0
NC		 102 const insn_template *start;
103 const insn_template *end;
6305a203
L		 104}
105templates;
106
107/* 386 operand encoding bytes: see 386 book for details of this. */
108typedef struct
109{
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113}
114modrm_byte;
115
116/* x86-64 extension prefix. */
117typedef int rex_byte;
118
6305a203
L		 119/* 386 opcode byte to code indirect addressing. */
120typedef struct
121{
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125}
126sib_byte;
127
6305a203
L		 128/* x86 arch names, types and features */
129typedef struct
130{
131 const char *name; /* arch name */
8a2c8fef 132 unsigned int len; /* arch string length */
6305a203
L		 133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 135 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 136}
137arch_entry;
138
293f5f65
L		 139/* Used to turn off indicated flags. */
140typedef struct
141{
142 const char *name; /* arch name */
143 unsigned int len; /* arch string length */
144 i386_cpu_flags flags; /* cpu feature flags */
145}
146noarch_entry;
147
78f12dd3 148static void update_code_flag (int, int);
e3bb37b5
L		 149static void set_code_flag (int);
150static void set_16bit_gcc_code_flag (int);
151static void set_intel_syntax (int);
1efbbeb4 152static void set_intel_mnemonic (int);
db51cc60 153static void set_allow_index_reg (int);
7bab8ab5 154static void set_check (int);
e3bb37b5 155static void set_cpu_arch (int);
6482c264 156#ifdef TE_PE
e3bb37b5 157static void pe_directive_secrel (int);
6482c264 158#endif
e3bb37b5
L		 159static void signed_cons (int);
160static char *output_invalid (int c);
ee86248c
JB		 161static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
162 const char *);
163static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
164 const char *);
a7619375 165static int i386_att_operand (char *);
e3bb37b5 166static int i386_intel_operand (char *, int);
ee86248c
JB		 167static int i386_intel_simplify (expressionS *);
168static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 169static const reg_entry *parse_register (char *, char **);
170static char *parse_insn (char *, char *);
171static char *parse_operands (char *, const char *);
172static void swap_operands (void);
4d456e3d 173static void swap_2_operands (int, int);
e3bb37b5
L		 174static void optimize_imm (void);
175static void optimize_disp (void);
83b16ac6 176static const insn_template *match_template (char);
e3bb37b5
L		 177static int check_string (void);
178static int process_suffix (void);
179static int check_byte_reg (void);
180static int check_long_reg (void);
181static int check_qword_reg (void);
182static int check_word_reg (void);
183static int finalize_imm (void);
184static int process_operands (void);
185static const seg_entry *build_modrm_byte (void);
186static void output_insn (void);
187static void output_imm (fragS *, offsetT);
188static void output_disp (fragS *, offsetT);
29b0f896 189#ifndef I386COFF
e3bb37b5 190static void s_bss (int);
252b5132 191#endif
17d4e2a2
L		 192#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193static void handle_large_common (int small ATTRIBUTE_UNUSED);
194#endif
252b5132 195
a847613f 196static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 197
43234a1e
L		 198/* This struct describes rounding control and SAE in the instruction. */
199struct RC_Operation
200{
201 enum rc_type
202 {
203 rne = 0,
204 rd,
205 ru,
206 rz,
207 saeonly
208 } type;
209 int operand;
210};
211
212static struct RC_Operation rc_op;
213
214/* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217struct Mask_Operation
218{
219 const reg_entry *mask;
220 unsigned int zeroing;
221 /* The operand where this operation is associated. */
222 int operand;
223};
224
225static struct Mask_Operation mask_op;
226
227/* The struct describes broadcasting, applied to OPERAND. FACTOR is
228 broadcast factor. */
229struct Broadcast_Operation
230{
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
232 int type;
233
234 /* Index of broadcasted operand. */
235 int operand;
236};
237
238static struct Broadcast_Operation broadcast_op;
239
c0f3af97
L		 240/* VEX prefix. */
241typedef struct
242{
43234a1e
L		 243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes[4];
c0f3af97
L		 245 unsigned int length;
246 /* Destination or source register specifier. */
247 const reg_entry *register_specifier;
248} vex_prefix;
249
252b5132 250/* 'md_assemble ()' gathers together information and puts it into a
47926f60 251 i386_insn. */
252b5132 252
520dc8e8
AM		 253union i386_op
254 {
255 expressionS *disps;
256 expressionS *imms;
257 const reg_entry *regs;
258 };
259
a65babc9
L		 260enum i386_error
261 {
86e026a4 262 operand_size_mismatch,
a65babc9
L		 263 operand_type_mismatch,
264 register_type_mismatch,
265 number_of_operands_mismatch,
266 invalid_instruction_suffix,
267 bad_imm4,
268 old_gcc_only,
269 unsupported_with_intel_mnemonic,
270 unsupported_syntax,
6c30d220
L		 271 unsupported,
272 invalid_vsib_address,
7bab8ab5 273 invalid_vector_register_set,
43234a1e
L		 274 unsupported_vector_index_register,
275 unsupported_broadcast,
276 broadcast_not_on_src_operand,
277 broadcast_needed,
278 unsupported_masking,
279 mask_not_on_destination,
280 no_default_mask,
281 unsupported_rc_sae,
282 rc_sae_operand_not_last_imm,
283 invalid_register_operand,
284 try_vector_disp8
a65babc9
L		 285 };
286
252b5132
RH		 287struct _i386_insn
288 {
47926f60 289 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 290 insn_template tm;
252b5132 291
7d5e4556
L		 292 /* SUFFIX holds the instruction size suffix for byte, word, dword
293 or qword, if given. */
252b5132
RH		 294 char suffix;
295
47926f60 296 /* OPERANDS gives the number of given operands. */
252b5132
RH		 297 unsigned int operands;
298
299 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
300 of given register, displacement, memory operands and immediate
47926f60 301 operands. */
252b5132
RH		 302 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
303
304 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 305 use OP[i] for the corresponding operand. */
40fb9820 306 i386_operand_type types[MAX_OPERANDS];
252b5132 307
520dc8e8
AM		 308 /* Displacement expression, immediate expression, or register for each
309 operand. */
310 union i386_op op[MAX_OPERANDS];
252b5132 311
3e73aa7c
JH		 312 /* Flags for operands. */
313 unsigned int flags[MAX_OPERANDS];
314#define Operand_PCrel 1
315
252b5132 316 /* Relocation type for operand */
f86103b7 317 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 318
252b5132
RH		 319 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
320 the base index byte below. */
321 const reg_entry *base_reg;
322 const reg_entry *index_reg;
323 unsigned int log2_scale_factor;
324
325 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 326 explicit segment overrides are given. */
ce8a8b2f 327 const seg_entry *seg[2];
252b5132 328
8325cc63
JB		 329 /* Copied first memory operand string, for re-checking. */
330 char *memop1_string;
331
252b5132
RH		 332 /* PREFIX holds all the given prefix opcodes (usually null).
333 PREFIXES is the number of prefix opcodes. */
334 unsigned int prefixes;
335 unsigned char prefix[MAX_PREFIXES];
336
337 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 338 addressing modes of this insn are encoded. */
252b5132 339 modrm_byte rm;
3e73aa7c 340 rex_byte rex;
43234a1e 341 rex_byte vrex;
252b5132 342 sib_byte sib;
c0f3af97 343 vex_prefix vex;
b6169b20 344
43234a1e
L		 345 /* Masking attributes. */
346 struct Mask_Operation *mask;
347
348 /* Rounding control and SAE attributes. */
349 struct RC_Operation *rounding;
350
351 /* Broadcasting attributes. */
352 struct Broadcast_Operation *broadcast;
353
354 /* Compressed disp8*N attribute. */
355 unsigned int memshift;
356
b6169b20 357 /* Swap operand in encoding. */
4473e004 358 unsigned int swap_operand;
891edac4 359
a501d77e
L		 360 /* Prefer 8bit or 32bit displacement in encoding. */
361 enum
362 {
363 disp_encoding_default = 0,
364 disp_encoding_8bit,
365 disp_encoding_32bit
366 } disp_encoding;
f8a5c266 367
d5de92cf
L		 368 /* REP prefix. */
369 const char *rep_prefix;
370
165de32a
L		 371 /* HLE prefix. */
372 const char *hle_prefix;
42164a71 373
7e8b059b
L		 374 /* Have BND prefix. */
375 const char *bnd_prefix;
376
43234a1e
L		 377 /* Need VREX to support upper 16 registers. */
378 int need_vrex;
379
891edac4 380 /* Error message. */
a65babc9 381 enum i386_error error;
252b5132
RH		 382 };
383
384typedef struct _i386_insn i386_insn;
385
43234a1e
L		 386/* Link RC type with corresponding string, that'll be looked for in
387 asm. */
388struct RC_name
389{
390 enum rc_type type;
391 const char *name;
392 unsigned int len;
393};
394
395static const struct RC_name RC_NamesTable[] =
396{
397 { rne, STRING_COMMA_LEN ("rn-sae") },
398 { rd, STRING_COMMA_LEN ("rd-sae") },
399 { ru, STRING_COMMA_LEN ("ru-sae") },
400 { rz, STRING_COMMA_LEN ("rz-sae") },
401 { saeonly, STRING_COMMA_LEN ("sae") },
402};
403
252b5132
RH		 404/* List of chars besides those in app.c:symbol_chars that can start an
405 operand. Used to prevent the scrubber eating vital white-space. */
43234a1e 406const char extra_symbol_chars[] = "*%-([{"
252b5132 407#ifdef LEX_AT
32137342
NC		 408 "@"
409#endif
410#ifdef LEX_QM
411 "?"
252b5132 412#endif
32137342 413 ;
252b5132 414
29b0f896
AM		 415#if (defined (TE_I386AIX) \
416 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 417 && !defined (TE_GNU) \
29b0f896 418 && !defined (TE_LINUX) \
8d63c93e
RM		 419 && !defined (TE_NACL) \
420 && !defined (TE_NETWARE) \
29b0f896 421 && !defined (TE_FreeBSD) \
5b806d27 422 && !defined (TE_DragonFly) \
29b0f896 423 && !defined (TE_NetBSD)))
252b5132 424/* This array holds the chars that always start a comment. If the
b3b91714
AM		 425 pre-processor is disabled, these aren't very useful. The option
426 --divide will remove '/' from this list. */
427const char *i386_comment_chars = "#/";
428#define SVR4_COMMENT_CHARS 1
252b5132 429#define PREFIX_SEPARATOR '\\'
252b5132 430
b3b91714
AM		 431#else
432const char *i386_comment_chars = "#";
433#define PREFIX_SEPARATOR '/'
434#endif
435
252b5132
RH		 436/* This array holds the chars that only start a comment at the beginning of
437 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 438 .line and .file directives will appear in the pre-processed output.
439 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 440 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 441 #NO_APP at the beginning of its output.
442 Also note that comments started like this one will always work if
252b5132 443 '/' isn't otherwise defined. */
b3b91714 444const char line_comment_chars[] = "#/";
252b5132 445
63a0b638 446const char line_separator_chars[] = ";";
252b5132 447
ce8a8b2f
AM		 448/* Chars that can be used to separate mant from exp in floating point
449 nums. */
252b5132
RH		 450const char EXP_CHARS[] = "eE";
451
ce8a8b2f
AM		 452/* Chars that mean this number is a floating point constant
453 As in 0f12.456
454 or 0d1.2345e12. */
252b5132
RH		 455const char FLT_CHARS[] = "fFdDxX";
456
ce8a8b2f 457/* Tables for lexical analysis. */
252b5132
RH		 458static char mnemonic_chars[256];
459static char register_chars[256];
460static char operand_chars[256];
461static char identifier_chars[256];
462static char digit_chars[256];
463
ce8a8b2f 464/* Lexical macros. */
252b5132
RH		 465#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
466#define is_operand_char(x) (operand_chars[(unsigned char) x])
467#define is_register_char(x) (register_chars[(unsigned char) x])
468#define is_space_char(x) ((x) == ' ')
469#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
470#define is_digit_char(x) (digit_chars[(unsigned char) x])
471
0234cb7c 472/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 473static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
474
475/* md_assemble() always leaves the strings it's passed unaltered. To
476 effect this we maintain a stack of saved characters that we've smashed
477 with '\0's (indicating end of strings for various sub-fields of the
47926f60 478 assembler instruction). */
252b5132 479static char save_stack[32];
ce8a8b2f 480static char *save_stack_p;
252b5132
RH		 481#define END_STRING_AND_SAVE(s) \
482 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
483#define RESTORE_END_STRING(s) \
484 do { *(s) = *--save_stack_p; } while (0)
485
47926f60 486/* The instruction we're assembling. */
252b5132
RH		 487static i386_insn i;
488
489/* Possible templates for current insn. */
490static const templates *current_templates;
491
31b2323c
L		 492/* Per instruction expressionS buffers: max displacements & immediates. */
493static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
494static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 495
47926f60 496/* Current operand we are working on. */
ee86248c 497static int this_operand = -1;
252b5132 498
3e73aa7c
JH		 499/* We support four different modes. FLAG_CODE variable is used to distinguish
500 these. */
501
502enum flag_code {
503 CODE_32BIT,
504 CODE_16BIT,
505 CODE_64BIT };
506
507static enum flag_code flag_code;
4fa24527 508static unsigned int object_64bit;
862be3fb 509static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 510static int use_rela_relocations = 0;
511
7af8ed2d
NC		 512#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
513 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
514 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
515
351f65ca
L		 516/* The ELF ABI to use. */
517enum x86_elf_abi
518{
519 I386_ABI,
7f56bc95
L		 520 X86_64_ABI,
521 X86_64_X32_ABI
351f65ca
L		 522};
523
524static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 525#endif
351f65ca 526
167ad85b
TG		 527#if defined (TE_PE) || defined (TE_PEP)
528/* Use big object file format. */
529static int use_big_obj = 0;
530#endif
531
8dcea932
L		 532#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
533/* 1 if generating code for a shared library. */
534static int shared = 0;
535#endif
536
47926f60
KH		 537/* 1 for intel syntax,
538 0 if att syntax. */
539static int intel_syntax = 0;
252b5132 540
e89c5eaa
L		 541/* 1 for Intel64 ISA,
542 0 if AMD64 ISA. */
543static int intel64;
544
1efbbeb4
L		 545/* 1 for intel mnemonic,
546 0 if att mnemonic. */
547static int intel_mnemonic = !SYSV386_COMPAT;
548
5209009a 549/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 550static int old_gcc = OLDGCC_COMPAT;
551
a60de03c
JB		 552/* 1 if pseudo registers are permitted. */
553static int allow_pseudo_reg = 0;
554
47926f60
KH		 555/* 1 if register prefix % not required. */
556static int allow_naked_reg = 0;
252b5132 557
7e8b059b
L		 558/* 1 if the assembler should add BND prefix for all control-tranferring
559 instructions supporting it, even if this prefix wasn't specified
560 explicitly. */
561static int add_bnd_prefix = 0;
562
ba104c83 563/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 564static int allow_index_reg = 0;
565
d022bddd
IT		 566/* 1 if the assembler should ignore LOCK prefix, even if it was
567 specified explicitly. */
568static int omit_lock_prefix = 0;
569
e4e00185
AS		 570/* 1 if the assembler should encode lfence, mfence, and sfence as
571 "lock addl $0, (%{re}sp)". */
572static int avoid_fence = 0;
573
0cb4071e
L		 574/* 1 if the assembler should generate relax relocations. */
575
576static int generate_relax_relocations
577 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
578
7bab8ab5 579static enum check_kind
daf50ae7 580 {
7bab8ab5
JB		 581 check_none = 0,
582 check_warning,
583 check_error
daf50ae7 584 }
7bab8ab5 585sse_check, operand_check = check_warning;
daf50ae7 586
2ca3ace5
L		 587/* Register prefix used for error message. */
588static const char *register_prefix = "%";
589
47926f60
KH		 590/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
591 leave, push, and pop instructions so that gcc has the same stack
592 frame as in 32 bit mode. */
593static char stackop_size = '\0';
eecb386c 594
12b55ccc
L		 595/* Non-zero to optimize code alignment. */
596int optimize_align_code = 1;
597
47926f60
KH		 598/* Non-zero to quieten some warnings. */
599static int quiet_warnings = 0;
a38cf1db 600
47926f60
KH		 601/* CPU name. */
602static const char *cpu_arch_name = NULL;
6305a203 603static char *cpu_sub_arch_name = NULL;
a38cf1db 604
47926f60 605/* CPU feature flags. */
40fb9820
L		 606static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
607
ccc9c027
L		 608/* If we have selected a cpu we are generating instructions for. */
609static int cpu_arch_tune_set = 0;
610
9103f4f4 611/* Cpu we are generating instructions for. */
fbf3f584 612enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 613
614/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 615static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 616
ccc9c027 617/* CPU instruction set architecture used. */
fbf3f584 618enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 619
9103f4f4 620/* CPU feature flags of instruction set architecture used. */
fbf3f584 621i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 622
fddf5b5b
AM		 623/* If set, conditional jumps are not automatically promoted to handle
624 larger than a byte offset. */
625static unsigned int no_cond_jump_promotion = 0;
626
c0f3af97
L		 627/* Encode SSE instructions with VEX prefix. */
628static unsigned int sse2avx;
629
539f890d
L		 630/* Encode scalar AVX instructions with specific vector length. */
631static enum
632 {
633 vex128 = 0,
634 vex256
635 } avxscalar;
636
43234a1e
L		 637/* Encode scalar EVEX LIG instructions with specific vector length. */
638static enum
639 {
640 evexl128 = 0,
641 evexl256,
642 evexl512
643 } evexlig;
644
645/* Encode EVEX WIG instructions with specific evex.w. */
646static enum
647 {
648 evexw0 = 0,
649 evexw1
650 } evexwig;
651
d3d3c6db
IT		 652/* Value to encode in EVEX RC bits, for SAE-only instructions. */
653static enum rc_type evexrcig = rne;
654
29b0f896 655/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 656static symbolS *GOT_symbol;
29b0f896 657
a4447b93
RH		 658/* The dwarf2 return column, adjusted for 32 or 64 bit. */
659unsigned int x86_dwarf2_return_column;
660
661/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
662int x86_cie_data_alignment;
663
252b5132 664/* Interface to relax_segment.
fddf5b5b
AM		 665 There are 3 major relax states for 386 jump insns because the
666 different types of jumps add different sizes to frags when we're
667 figuring out what sort of jump to choose to reach a given label. */
252b5132 668
47926f60 669/* Types. */
93c2a809
AM		 670#define UNCOND_JUMP 0
671#define COND_JUMP 1
672#define COND_JUMP86 2
fddf5b5b 673
47926f60 674/* Sizes. */
252b5132
RH		 675#define CODE16 1
676#define SMALL 0
29b0f896 677#define SMALL16 (SMALL | CODE16)
252b5132 678#define BIG 2
29b0f896 679#define BIG16 (BIG | CODE16)
252b5132
RH		 680
681#ifndef INLINE
682#ifdef __GNUC__
683#define INLINE __inline__
684#else
685#define INLINE
686#endif
687#endif
688
fddf5b5b
AM		 689#define ENCODE_RELAX_STATE(type, size) \
690 ((relax_substateT) (((type) << 2) | (size)))
691#define TYPE_FROM_RELAX_STATE(s) \
692 ((s) >> 2)
693#define DISP_SIZE_FROM_RELAX_STATE(s) \
694 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 695
696/* This table is used by relax_frag to promote short jumps to long
697 ones where necessary. SMALL (short) jumps may be promoted to BIG
698 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
699 don't allow a short jump in a 32 bit code segment to be promoted to
700 a 16 bit offset jump because it's slower (requires data size
701 prefix), and doesn't work, unless the destination is in the bottom
702 64k of the code segment (The top 16 bits of eip are zeroed). */
703
704const relax_typeS md_relax_table[] =
705{
24eab124
AM		 706 /* The fields are:
707 1) most positive reach of this state,
708 2) most negative reach of this state,
93c2a809 709 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 710 4) which index into the table to try if we can't fit into this one. */
252b5132 711
fddf5b5b 712 /* UNCOND_JUMP states. */
93c2a809
AM		 713 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
714 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
715 /* dword jmp adds 4 bytes to frag:
716 0 extra opcode bytes, 4 displacement bytes. */
252b5132 717 {0, 0, 4, 0},
93c2a809
AM		 718 /* word jmp adds 2 byte2 to frag:
719 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 720 {0, 0, 2, 0},
721
93c2a809
AM		 722 /* COND_JUMP states. */
723 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
724 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
725 /* dword conditionals adds 5 bytes to frag:
726 1 extra opcode byte, 4 displacement bytes. */
727 {0, 0, 5, 0},
fddf5b5b 728 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 729 1 extra opcode byte, 2 displacement bytes. */
730 {0, 0, 3, 0},
731
732 /* COND_JUMP86 states. */
733 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
734 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
735 /* dword conditionals adds 5 bytes to frag:
736 1 extra opcode byte, 4 displacement bytes. */
737 {0, 0, 5, 0},
738 /* word conditionals add 4 bytes to frag:
739 1 displacement byte and a 3 byte long branch insn. */
740 {0, 0, 4, 0}
252b5132
RH		 741};
742
9103f4f4
L		 743static const arch_entry cpu_arch[] =
744{
89507696
JB		 745 /* Do not replace the first two entries - i386_target_format()
746 relies on them being there in this order. */
8a2c8fef 747 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
293f5f65 748 CPU_GENERIC32_FLAGS, 0 },
8a2c8fef 749 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
293f5f65 750 CPU_GENERIC64_FLAGS, 0 },
8a2c8fef 751 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
293f5f65 752 CPU_NONE_FLAGS, 0 },
8a2c8fef 753 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
293f5f65 754 CPU_I186_FLAGS, 0 },
8a2c8fef 755 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
293f5f65 756 CPU_I286_FLAGS, 0 },
8a2c8fef 757 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
293f5f65 758 CPU_I386_FLAGS, 0 },
8a2c8fef 759 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
293f5f65 760 CPU_I486_FLAGS, 0 },
8a2c8fef 761 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
293f5f65 762 CPU_I586_FLAGS, 0 },
8a2c8fef 763 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
293f5f65 764 CPU_I686_FLAGS, 0 },
8a2c8fef 765 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
293f5f65 766 CPU_I586_FLAGS, 0 },
8a2c8fef 767 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
293f5f65 768 CPU_PENTIUMPRO_FLAGS, 0 },
8a2c8fef 769 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
293f5f65 770 CPU_P2_FLAGS, 0 },
8a2c8fef 771 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
293f5f65 772 CPU_P3_FLAGS, 0 },
8a2c8fef 773 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
293f5f65 774 CPU_P4_FLAGS, 0 },
8a2c8fef 775 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
293f5f65 776 CPU_CORE_FLAGS, 0 },
8a2c8fef 777 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
293f5f65 778 CPU_NOCONA_FLAGS, 0 },
8a2c8fef 779 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
293f5f65 780 CPU_CORE_FLAGS, 1 },
8a2c8fef 781 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
293f5f65 782 CPU_CORE_FLAGS, 0 },
8a2c8fef 783 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
293f5f65 784 CPU_CORE2_FLAGS, 1 },
8a2c8fef 785 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
293f5f65 786 CPU_CORE2_FLAGS, 0 },
8a2c8fef 787 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
293f5f65 788 CPU_COREI7_FLAGS, 0 },
8a2c8fef 789 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
293f5f65 790 CPU_L1OM_FLAGS, 0 },
7a9068fe 791 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
293f5f65 792 CPU_K1OM_FLAGS, 0 },
81486035 793 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
293f5f65 794 CPU_IAMCU_FLAGS, 0 },
8a2c8fef 795 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
293f5f65 796 CPU_K6_FLAGS, 0 },
8a2c8fef 797 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
293f5f65 798 CPU_K6_2_FLAGS, 0 },
8a2c8fef 799 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
293f5f65 800 CPU_ATHLON_FLAGS, 0 },
8a2c8fef 801 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
293f5f65 802 CPU_K8_FLAGS, 1 },
8a2c8fef 803 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
293f5f65 804 CPU_K8_FLAGS, 0 },
8a2c8fef 805 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
293f5f65 806 CPU_K8_FLAGS, 0 },
8a2c8fef 807 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
293f5f65 808 CPU_AMDFAM10_FLAGS, 0 },
8aedb9fe 809 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
293f5f65 810 CPU_BDVER1_FLAGS, 0 },
8aedb9fe 811 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
293f5f65 812 CPU_BDVER2_FLAGS, 0 },
5e5c50d3 813 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
293f5f65 814 CPU_BDVER3_FLAGS, 0 },
c7b0bd56 815 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
293f5f65 816 CPU_BDVER4_FLAGS, 0 },
029f3522 817 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
293f5f65 818 CPU_ZNVER1_FLAGS, 0 },
7b458c12 819 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
293f5f65 820 CPU_BTVER1_FLAGS, 0 },
7b458c12 821 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
293f5f65 822 CPU_BTVER2_FLAGS, 0 },
8a2c8fef 823 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
293f5f65 824 CPU_8087_FLAGS, 0 },
8a2c8fef 825 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
293f5f65 826 CPU_287_FLAGS, 0 },
8a2c8fef 827 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
293f5f65 828 CPU_387_FLAGS, 0 },
1848e567
L		 829 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
830 CPU_687_FLAGS, 0 },
8a2c8fef 831 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
293f5f65 832 CPU_MMX_FLAGS, 0 },
8a2c8fef 833 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
293f5f65 834 CPU_SSE_FLAGS, 0 },
8a2c8fef 835 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
293f5f65 836 CPU_SSE2_FLAGS, 0 },
8a2c8fef 837 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
293f5f65 838 CPU_SSE3_FLAGS, 0 },
8a2c8fef 839 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
293f5f65 840 CPU_SSSE3_FLAGS, 0 },
8a2c8fef 841 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
293f5f65 842 CPU_SSE4_1_FLAGS, 0 },
8a2c8fef 843 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
293f5f65 844 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 845 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
293f5f65 846 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 847 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
293f5f65 848 CPU_AVX_FLAGS, 0 },
6c30d220 849 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
293f5f65 850 CPU_AVX2_FLAGS, 0 },
43234a1e 851 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
293f5f65 852 CPU_AVX512F_FLAGS, 0 },
43234a1e 853 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
293f5f65 854 CPU_AVX512CD_FLAGS, 0 },
43234a1e 855 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
293f5f65 856 CPU_AVX512ER_FLAGS, 0 },
43234a1e 857 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
293f5f65 858 CPU_AVX512PF_FLAGS, 0 },
1dfc6506 859 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
293f5f65 860 CPU_AVX512DQ_FLAGS, 0 },
1dfc6506 861 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
293f5f65 862 CPU_AVX512BW_FLAGS, 0 },
1dfc6506 863 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
293f5f65 864 CPU_AVX512VL_FLAGS, 0 },
8a2c8fef 865 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
293f5f65 866 CPU_VMX_FLAGS, 0 },
8729a6f6 867 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
293f5f65 868 CPU_VMFUNC_FLAGS, 0 },
8a2c8fef 869 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
293f5f65 870 CPU_SMX_FLAGS, 0 },
8a2c8fef 871 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
293f5f65 872 CPU_XSAVE_FLAGS, 0 },
c7b8aa3a 873 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
293f5f65 874 CPU_XSAVEOPT_FLAGS, 0 },
1dfc6506 875 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
293f5f65 876 CPU_XSAVEC_FLAGS, 0 },
1dfc6506 877 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
293f5f65 878 CPU_XSAVES_FLAGS, 0 },
8a2c8fef 879 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
293f5f65 880 CPU_AES_FLAGS, 0 },
8a2c8fef 881 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
293f5f65 882 CPU_PCLMUL_FLAGS, 0 },
8a2c8fef 883 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
293f5f65 884 CPU_PCLMUL_FLAGS, 1 },
c7b8aa3a 885 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
293f5f65 886 CPU_FSGSBASE_FLAGS, 0 },
c7b8aa3a 887 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
293f5f65 888 CPU_RDRND_FLAGS, 0 },
c7b8aa3a 889 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
293f5f65 890 CPU_F16C_FLAGS, 0 },
6c30d220 891 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
293f5f65 892 CPU_BMI2_FLAGS, 0 },
8a2c8fef 893 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
293f5f65 894 CPU_FMA_FLAGS, 0 },
8a2c8fef 895 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
293f5f65 896 CPU_FMA4_FLAGS, 0 },
8a2c8fef 897 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
293f5f65 898 CPU_XOP_FLAGS, 0 },
8a2c8fef 899 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
293f5f65 900 CPU_LWP_FLAGS, 0 },
8a2c8fef 901 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
293f5f65 902 CPU_MOVBE_FLAGS, 0 },
60aa667e 903 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
293f5f65 904 CPU_CX16_FLAGS, 0 },
8a2c8fef 905 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
293f5f65 906 CPU_EPT_FLAGS, 0 },
6c30d220 907 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
293f5f65 908 CPU_LZCNT_FLAGS, 0 },
42164a71 909 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
293f5f65 910 CPU_HLE_FLAGS, 0 },
42164a71 911 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
293f5f65 912 CPU_RTM_FLAGS, 0 },
6c30d220 913 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
293f5f65 914 CPU_INVPCID_FLAGS, 0 },
8a2c8fef 915 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
293f5f65 916 CPU_CLFLUSH_FLAGS, 0 },
22109423 917 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
293f5f65 918 CPU_NOP_FLAGS, 0 },
8a2c8fef 919 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
293f5f65 920 CPU_SYSCALL_FLAGS, 0 },
8a2c8fef 921 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
293f5f65 922 CPU_RDTSCP_FLAGS, 0 },
8a2c8fef 923 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
293f5f65 924 CPU_3DNOW_FLAGS, 0 },
8a2c8fef 925 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
293f5f65 926 CPU_3DNOWA_FLAGS, 0 },
8a2c8fef 927 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
293f5f65 928 CPU_PADLOCK_FLAGS, 0 },
8a2c8fef 929 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
293f5f65 930 CPU_SVME_FLAGS, 1 },
8a2c8fef 931 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
293f5f65 932 CPU_SVME_FLAGS, 0 },
8a2c8fef 933 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
293f5f65 934 CPU_SSE4A_FLAGS, 0 },
8a2c8fef 935 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
293f5f65 936 CPU_ABM_FLAGS, 0 },
87973e9f 937 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
293f5f65 938 CPU_BMI_FLAGS, 0 },
2a2a0f38 939 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
293f5f65 940 CPU_TBM_FLAGS, 0 },
e2e1fcde 941 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
293f5f65 942 CPU_ADX_FLAGS, 0 },
e2e1fcde 943 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
293f5f65 944 CPU_RDSEED_FLAGS, 0 },
e2e1fcde 945 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
293f5f65 946 CPU_PRFCHW_FLAGS, 0 },
5c111e37 947 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
293f5f65 948 CPU_SMAP_FLAGS, 0 },
7e8b059b 949 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
293f5f65 950 CPU_MPX_FLAGS, 0 },
a0046408 951 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
293f5f65 952 CPU_SHA_FLAGS, 0 },
963f3586 953 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
293f5f65 954 CPU_CLFLUSHOPT_FLAGS, 0 },
dcf893b5 955 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
293f5f65 956 CPU_PREFETCHWT1_FLAGS, 0 },
2cf200a4 957 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
293f5f65 958 CPU_SE1_FLAGS, 0 },
c5e7287a 959 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
293f5f65 960 CPU_CLWB_FLAGS, 0 },
9d8596f0 961 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN,
293f5f65 962 CPU_PCOMMIT_FLAGS, 0 },
2cc1b5aa 963 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
293f5f65 964 CPU_AVX512IFMA_FLAGS, 0 },
14f195c9 965 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
293f5f65 966 CPU_AVX512VBMI_FLAGS, 0 },
029f3522 967 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
293f5f65 968 CPU_CLZERO_FLAGS, 0 },
9916071f 969 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
293f5f65 970 CPU_MWAITX_FLAGS, 0 },
8eab4136 971 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
293f5f65 972 CPU_OSPKE_FLAGS, 0 },
8bc52696 973 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
293f5f65
L		 974 CPU_RDPID_FLAGS, 0 },
975};
976
977static const noarch_entry cpu_noarch[] =
978{
979 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1848e567
L		 980 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
981 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
982 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
293f5f65
L		 983 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
984 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1848e567
L		 985 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
986 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
987 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
988 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
989 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
990 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
293f5f65 991 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1848e567 992 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
144b71e2
L		 993 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
994 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
995 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
996 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
997 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
998 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
999 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1000 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1001 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
e413e4e9
AM		 1002};
1003
704209c0 1004#ifdef I386COFF
a6c24e68
NC		 1005/* Like s_lcomm_internal in gas/read.c but the alignment string
1006 is allowed to be optional. */
1007
1008static symbolS *
1009pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1010{
1011 addressT align = 0;
1012
1013 SKIP_WHITESPACE ();
1014
7ab9ffdd 1015 if (needs_align
a6c24e68
NC		 1016 && *input_line_pointer == ',')
1017 {
1018 align = parse_align (needs_align - 1);
7ab9ffdd 1019
a6c24e68
NC		 1020 if (align == (addressT) -1)
1021 return NULL;
1022 }
1023 else
1024 {
1025 if (size >= 8)
1026 align = 3;
1027 else if (size >= 4)
1028 align = 2;
1029 else if (size >= 2)
1030 align = 1;
1031 else
1032 align = 0;
1033 }
1034
1035 bss_alloc (symbolP, size, align);
1036 return symbolP;
1037}
1038
704209c0 1039static void
a6c24e68
NC		 1040pe_lcomm (int needs_align)
1041{
1042 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1043}
704209c0 1044#endif
a6c24e68 1045
29b0f896
AM		 1046const pseudo_typeS md_pseudo_table[] =
1047{
1048#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1049 {"align", s_align_bytes, 0},
1050#else
1051 {"align", s_align_ptwo, 0},
1052#endif
1053 {"arch", set_cpu_arch, 0},
1054#ifndef I386COFF
1055 {"bss", s_bss, 0},
a6c24e68
NC		 1056#else
1057 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1058#endif
1059 {"ffloat", float_cons, 'f'},
1060 {"dfloat", float_cons, 'd'},
1061 {"tfloat", float_cons, 'x'},
1062 {"value", cons, 2},
d182319b 1063 {"slong", signed_cons, 4},
29b0f896
AM		 1064 {"noopt", s_ignore, 0},
1065 {"optim", s_ignore, 0},
1066 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1067 {"code16", set_code_flag, CODE_16BIT},
1068 {"code32", set_code_flag, CODE_32BIT},
1069 {"code64", set_code_flag, CODE_64BIT},
1070 {"intel_syntax", set_intel_syntax, 1},
1071 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1072 {"intel_mnemonic", set_intel_mnemonic, 1},
1073 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1074 {"allow_index_reg", set_allow_index_reg, 1},
1075 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1076 {"sse_check", set_check, 0},
1077 {"operand_check", set_check, 1},
3b22753a
L		 1078#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1079 {"largecomm", handle_large_common, 0},
07a53e5c 1080#else
e3bb37b5 1081 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 1082 {"loc", dwarf2_directive_loc, 0},
1083 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1084#endif
6482c264
NC		 1085#ifdef TE_PE
1086 {"secrel32", pe_directive_secrel, 0},
1087#endif
29b0f896
AM		 1088 {0, 0, 0}
1089};
1090
1091/* For interface with expression (). */
1092extern char *input_line_pointer;
1093
1094/* Hash table for instruction mnemonic lookup. */
1095static struct hash_control *op_hash;
1096
1097/* Hash table for register lookup. */
1098static struct hash_control *reg_hash;
1099\f
252b5132 1100void
e3bb37b5 1101i386_align_code (fragS *fragP, int count)
252b5132 1102{
ce8a8b2f
AM		 1103 /* Various efficient no-op patterns for aligning code labels.
1104 Note: Don't try to assemble the instructions in the comments.
1105 0L and 0w are not legal. */
bad6e36d 1106 static const unsigned char f32_1[] =
252b5132 1107 {0x90}; /* nop */
bad6e36d 1108 static const unsigned char f32_2[] =
ccc9c027 1109 {0x66,0x90}; /* xchg %ax,%ax */
bad6e36d 1110 static const unsigned char f32_3[] =
252b5132 1111 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
bad6e36d 1112 static const unsigned char f32_4[] =
252b5132 1113 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
bad6e36d 1114 static const unsigned char f32_5[] =
252b5132
RH		 1115 {0x90, /* nop */
1116 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
bad6e36d 1117 static const unsigned char f32_6[] =
252b5132 1118 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
bad6e36d 1119 static const unsigned char f32_7[] =
252b5132 1120 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
bad6e36d 1121 static const unsigned char f32_8[] =
252b5132
RH		 1122 {0x90, /* nop */
1123 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
bad6e36d 1124 static const unsigned char f32_9[] =
252b5132
RH		 1125 {0x89,0xf6, /* movl %esi,%esi */
1126 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1127 static const unsigned char f32_10[] =
252b5132
RH		 1128 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1129 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1130 static const unsigned char f32_11[] =
252b5132
RH		 1131 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1132 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1133 static const unsigned char f32_12[] =
252b5132
RH		 1134 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1135 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
bad6e36d 1136 static const unsigned char f32_13[] =
252b5132
RH		 1137 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1138 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1139 static const unsigned char f32_14[] =
252b5132
RH		 1140 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1141 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1142 static const unsigned char f16_3[] =
c3332e24 1143 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
bad6e36d 1144 static const unsigned char f16_4[] =
252b5132 1145 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
bad6e36d 1146 static const unsigned char f16_5[] =
252b5132
RH		 1147 {0x90, /* nop */
1148 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
bad6e36d 1149 static const unsigned char f16_6[] =
252b5132
RH		 1150 {0x89,0xf6, /* mov %si,%si */
1151 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1152 static const unsigned char f16_7[] =
252b5132
RH		 1153 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1154 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1155 static const unsigned char f16_8[] =
252b5132
RH		 1156 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1157 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1158 static const unsigned char jump_31[] =
76bc74dc
L		 1159 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1160 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1161 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1162 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
bad6e36d 1163 static const unsigned char *const f32_patt[] = {
252b5132 1164 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1165 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132 1166 };
bad6e36d 1167 static const unsigned char *const f16_patt[] = {
76bc74dc 1168 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1169 };
ccc9c027 1170 /* nopl (%[re]ax) */
bad6e36d 1171 static const unsigned char alt_3[] =
ccc9c027
L		 1172 {0x0f,0x1f,0x00};
1173 /* nopl 0(%[re]ax) */
bad6e36d 1174 static const unsigned char alt_4[] =
ccc9c027
L		 1175 {0x0f,0x1f,0x40,0x00};
1176 /* nopl 0(%[re]ax,%[re]ax,1) */
bad6e36d 1177 static const unsigned char alt_5[] =
ccc9c027
L		 1178 {0x0f,0x1f,0x44,0x00,0x00};
1179 /* nopw 0(%[re]ax,%[re]ax,1) */
bad6e36d 1180 static const unsigned char alt_6[] =
ccc9c027
L		 1181 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1182 /* nopl 0L(%[re]ax) */
bad6e36d 1183 static const unsigned char alt_7[] =
ccc9c027
L		 1184 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1185 /* nopl 0L(%[re]ax,%[re]ax,1) */
bad6e36d 1186 static const unsigned char alt_8[] =
ccc9c027
L		 1187 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1188 /* nopw 0L(%[re]ax,%[re]ax,1) */
bad6e36d 1189 static const unsigned char alt_9[] =
ccc9c027
L		 1190 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1191 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
bad6e36d 1192 static const unsigned char alt_10[] =
ccc9c027 1193 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
bad6e36d 1194 static const unsigned char *const alt_patt[] = {
ccc9c027 1195 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
80b8656c 1196 alt_9, alt_10
ccc9c027 1197 };
252b5132 1198
76bc74dc
L		 1199 /* Only align for at least a positive non-zero boundary. */
1200 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1201 return;
3e73aa7c 1202
ccc9c027
L		 1203 /* We need to decide which NOP sequence to use for 32bit and
1204 64bit. When -mtune= is used:
4eed87de 1205
76bc74dc
L		 1206 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1207 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1208 2. For the rest, alt_patt will be used.
1209
1210 When -mtune= isn't used, alt_patt will be used if
22109423 1211 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1212 be used.
ccc9c027
L		 1213
1214 When -march= or .arch is used, we can't use anything beyond
1215 cpu_arch_isa_flags. */
1216
1217 if (flag_code == CODE_16BIT)
1218 {
ccc9c027 1219 if (count > 8)
33fef721 1220 {
76bc74dc
L		 1221 memcpy (fragP->fr_literal + fragP->fr_fix,
1222 jump_31, count);
1223 /* Adjust jump offset. */
1224 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1225 }
76bc74dc
L		 1226 else
1227 memcpy (fragP->fr_literal + fragP->fr_fix,
1228 f16_patt[count - 1], count);
252b5132 1229 }
33fef721 1230 else
ccc9c027 1231 {
bad6e36d 1232 const unsigned char *const *patt = NULL;
ccc9c027 1233
fbf3f584 1234 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1235 {
1236 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1237 switch (cpu_arch_tune)
1238 {
1239 case PROCESSOR_UNKNOWN:
1240 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1241 optimize with nops. */
1242 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1243 patt = alt_patt;
ccc9c027
L		 1244 else
1245 patt = f32_patt;
1246 break;
ccc9c027
L		 1247 case PROCESSOR_PENTIUM4:
1248 case PROCESSOR_NOCONA:
ef05d495 1249 case PROCESSOR_CORE:
76bc74dc 1250 case PROCESSOR_CORE2:
bd5295b2 1251 case PROCESSOR_COREI7:
3632d14b 1252 case PROCESSOR_L1OM:
7a9068fe 1253 case PROCESSOR_K1OM:
76bc74dc 1254 case PROCESSOR_GENERIC64:
ccc9c027
L		 1255 case PROCESSOR_K6:
1256 case PROCESSOR_ATHLON:
1257 case PROCESSOR_K8:
4eed87de 1258 case PROCESSOR_AMDFAM10:
8aedb9fe 1259 case PROCESSOR_BD:
029f3522 1260 case PROCESSOR_ZNVER:
7b458c12 1261 case PROCESSOR_BT:
80b8656c 1262 patt = alt_patt;
ccc9c027 1263 break;
76bc74dc 1264 case PROCESSOR_I386:
ccc9c027
L		 1265 case PROCESSOR_I486:
1266 case PROCESSOR_PENTIUM:
2dde1948 1267 case PROCESSOR_PENTIUMPRO:
81486035 1268 case PROCESSOR_IAMCU:
ccc9c027
L		 1269 case PROCESSOR_GENERIC32:
1270 patt = f32_patt;
1271 break;
4eed87de 1272 }
ccc9c027
L		 1273 }
1274 else
1275 {
fbf3f584 1276 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1277 {
1278 case PROCESSOR_UNKNOWN:
e6a14101 1279 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1280 PROCESSOR_UNKNOWN. */
1281 abort ();
1282 break;
1283
76bc74dc 1284 case PROCESSOR_I386:
ccc9c027
L		 1285 case PROCESSOR_I486:
1286 case PROCESSOR_PENTIUM:
81486035 1287 case PROCESSOR_IAMCU:
ccc9c027
L		 1288 case PROCESSOR_K6:
1289 case PROCESSOR_ATHLON:
1290 case PROCESSOR_K8:
4eed87de 1291 case PROCESSOR_AMDFAM10:
8aedb9fe 1292 case PROCESSOR_BD:
029f3522 1293 case PROCESSOR_ZNVER:
7b458c12 1294 case PROCESSOR_BT:
ccc9c027
L		 1295 case PROCESSOR_GENERIC32:
1296 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1297 with nops. */
1298 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1299 patt = alt_patt;
ccc9c027
L		 1300 else
1301 patt = f32_patt;
1302 break;
76bc74dc
L		 1303 case PROCESSOR_PENTIUMPRO:
1304 case PROCESSOR_PENTIUM4:
1305 case PROCESSOR_NOCONA:
1306 case PROCESSOR_CORE:
ef05d495 1307 case PROCESSOR_CORE2:
bd5295b2 1308 case PROCESSOR_COREI7:
3632d14b 1309 case PROCESSOR_L1OM:
7a9068fe 1310 case PROCESSOR_K1OM:
22109423 1311 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1312 patt = alt_patt;
ccc9c027
L		 1313 else
1314 patt = f32_patt;
1315 break;
1316 case PROCESSOR_GENERIC64:
80b8656c 1317 patt = alt_patt;
ccc9c027 1318 break;
4eed87de 1319 }
ccc9c027
L		 1320 }
1321
76bc74dc
L		 1322 if (patt == f32_patt)
1323 {
1324 /* If the padding is less than 15 bytes, we use the normal
1325 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1326 its offset. */
1327 int limit;
76ba9986 1328
711eedef
L		 1329 /* For 64bit, the limit is 3 bytes. */
1330 if (flag_code == CODE_64BIT
1331 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1332 limit = 3;
1333 else
1334 limit = 15;
1335 if (count < limit)
76bc74dc
L		 1336 memcpy (fragP->fr_literal + fragP->fr_fix,
1337 patt[count - 1], count);
1338 else
1339 {
1340 memcpy (fragP->fr_literal + fragP->fr_fix,
1341 jump_31, count);
1342 /* Adjust jump offset. */
1343 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1344 }
1345 }
1346 else
1347 {
80b8656c
L		 1348 /* Maximum length of an instruction is 10 byte. If the
1349 padding is greater than 10 bytes and we don't use jump,
76bc74dc
L		 1350 we have to break it into smaller pieces. */
1351 int padding = count;
80b8656c 1352 while (padding > 10)
76bc74dc 1353 {
80b8656c 1354 padding -= 10;
76bc74dc 1355 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
80b8656c 1356 patt [9], 10);
76bc74dc
L		 1357 }
1358
1359 if (padding)
1360 memcpy (fragP->fr_literal + fragP->fr_fix,
1361 patt [padding - 1], padding);
1362 }
ccc9c027 1363 }
33fef721 1364 fragP->fr_var = count;
252b5132
RH		 1365}
1366
c6fb90c8 1367static INLINE int
0dfbf9d7 1368operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1369{
0dfbf9d7 1370 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1371 {
1372 case 3:
0dfbf9d7 1373 if (x->array[2])
c6fb90c8
L		 1374 return 0;
1375 case 2:
0dfbf9d7 1376 if (x->array[1])
c6fb90c8
L		 1377 return 0;
1378 case 1:
0dfbf9d7 1379 return !x->array[0];
c6fb90c8
L		 1380 default:
1381 abort ();
1382 }
40fb9820
L		 1383}
1384
c6fb90c8 1385static INLINE void
0dfbf9d7 1386operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1387{
0dfbf9d7 1388 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1389 {
1390 case 3:
0dfbf9d7 1391 x->array[2] = v;
c6fb90c8 1392 case 2:
0dfbf9d7 1393 x->array[1] = v;
c6fb90c8 1394 case 1:
0dfbf9d7 1395 x->array[0] = v;
c6fb90c8
L		 1396 break;
1397 default:
1398 abort ();
1399 }
1400}
40fb9820 1401
c6fb90c8 1402static INLINE int
0dfbf9d7
L		 1403operand_type_equal (const union i386_operand_type *x,
1404 const union i386_operand_type *y)
c6fb90c8 1405{
0dfbf9d7 1406 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1407 {
1408 case 3:
0dfbf9d7 1409 if (x->array[2] != y->array[2])
c6fb90c8
L		 1410 return 0;
1411 case 2:
0dfbf9d7 1412 if (x->array[1] != y->array[1])
c6fb90c8
L		 1413 return 0;
1414 case 1:
0dfbf9d7 1415 return x->array[0] == y->array[0];
c6fb90c8
L		 1416 break;
1417 default:
1418 abort ();
1419 }
1420}
40fb9820 1421
0dfbf9d7
L		 1422static INLINE int
1423cpu_flags_all_zero (const union i386_cpu_flags *x)
1424{
1425 switch (ARRAY_SIZE(x->array))
1426 {
1427 case 3:
1428 if (x->array[2])
1429 return 0;
1430 case 2:
1431 if (x->array[1])
1432 return 0;
1433 case 1:
1434 return !x->array[0];
1435 default:
1436 abort ();
1437 }
1438}
1439
0dfbf9d7
L		 1440static INLINE int
1441cpu_flags_equal (const union i386_cpu_flags *x,
1442 const union i386_cpu_flags *y)
1443{
1444 switch (ARRAY_SIZE(x->array))
1445 {
1446 case 3:
1447 if (x->array[2] != y->array[2])
1448 return 0;
1449 case 2:
1450 if (x->array[1] != y->array[1])
1451 return 0;
1452 case 1:
1453 return x->array[0] == y->array[0];
1454 break;
1455 default:
1456 abort ();
1457 }
1458}
c6fb90c8
L		 1459
1460static INLINE int
1461cpu_flags_check_cpu64 (i386_cpu_flags f)
1462{
1463 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1464 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1465}
1466
c6fb90c8
L		 1467static INLINE i386_cpu_flags
1468cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1469{
c6fb90c8
L		 1470 switch (ARRAY_SIZE (x.array))
1471 {
1472 case 3:
1473 x.array [2] &= y.array [2];
1474 case 2:
1475 x.array [1] &= y.array [1];
1476 case 1:
1477 x.array [0] &= y.array [0];
1478 break;
1479 default:
1480 abort ();
1481 }
1482 return x;
1483}
40fb9820 1484
c6fb90c8
L		 1485static INLINE i386_cpu_flags
1486cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1487{
c6fb90c8 1488 switch (ARRAY_SIZE (x.array))
40fb9820 1489 {
c6fb90c8
L		 1490 case 3:
1491 x.array [2] |= y.array [2];
1492 case 2:
1493 x.array [1] |= y.array [1];
1494 case 1:
1495 x.array [0] |= y.array [0];
40fb9820
L		 1496 break;
1497 default:
1498 abort ();
1499 }
40fb9820
L		 1500 return x;
1501}
1502
309d3373
JB		 1503static INLINE i386_cpu_flags
1504cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1505{
1506 switch (ARRAY_SIZE (x.array))
1507 {
1508 case 3:
1509 x.array [2] &= ~y.array [2];
1510 case 2:
1511 x.array [1] &= ~y.array [1];
1512 case 1:
1513 x.array [0] &= ~y.array [0];
1514 break;
1515 default:
1516 abort ();
1517 }
1518 return x;
1519}
1520
81486035
L		 1521static int
1522valid_iamcu_cpu_flags (const i386_cpu_flags *flags)
1523{
1524 if (cpu_arch_isa == PROCESSOR_IAMCU)
1525 {
1526 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_COMPAT_FLAGS;
1527 i386_cpu_flags compat_flags;
1528 compat_flags = cpu_flags_and_not (*flags, iamcu_flags);
1529 return cpu_flags_all_zero (&compat_flags);
1530 }
1531 else
1532 return 1;
1533}
1534
c0f3af97
L		 1535#define CPU_FLAGS_ARCH_MATCH 0x1
1536#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1537#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1538#define CPU_FLAGS_PCLMUL_MATCH 0x8
1539#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1540
a5ff0eb2 1541#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1542 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1543 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1544#define CPU_FLAGS_PERFECT_MATCH \
1545 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1546
1547/* Return CPU flags match bits. */
3629bb00 1548
40fb9820 1549static int
d3ce72d0 1550cpu_flags_match (const insn_template *t)
40fb9820 1551{
c0f3af97
L		 1552 i386_cpu_flags x = t->cpu_flags;
1553 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1554
1555 x.bitfield.cpu64 = 0;
1556 x.bitfield.cpuno64 = 0;
1557
0dfbf9d7 1558 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1559 {
1560 /* This instruction is available on all archs. */
1561 match |= CPU_FLAGS_32BIT_MATCH;
1562 }
3629bb00
L		 1563 else
1564 {
c0f3af97 1565 /* This instruction is available only on some archs. */
3629bb00
L		 1566 i386_cpu_flags cpu = cpu_arch_flags;
1567
3629bb00 1568 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1569 if (!cpu_flags_all_zero (&cpu))
1570 {
a5ff0eb2
L		 1571 if (x.bitfield.cpuavx)
1572 {
ce2f5b3c 1573 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1574 if (cpu.bitfield.cpuavx)
1575 {
1576 /* Check SSE2AVX. */
1577 if (!t->opcode_modifier.sse2avx|| sse2avx)
1578 {
1579 match |= (CPU_FLAGS_ARCH_MATCH
1580 | CPU_FLAGS_AVX_MATCH);
1581 /* Check AES. */
1582 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1583 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1584 /* Check PCLMUL. */
1585 if (!x.bitfield.cpupclmul
1586 || cpu.bitfield.cpupclmul)
1587 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1588 }
1589 }
1590 else
1591 match |= CPU_FLAGS_ARCH_MATCH;
1592 }
73b090a9
L		 1593 else if (x.bitfield.cpuavx512vl)
1594 {
1595 /* Match AVX512VL. */
1596 if (cpu.bitfield.cpuavx512vl)
1597 {
1598 /* Need another match. */
1599 cpu.bitfield.cpuavx512vl = 0;
1600 if (!cpu_flags_all_zero (&cpu))
1601 match |= CPU_FLAGS_32BIT_MATCH;
1602 else
1603 match |= CPU_FLAGS_ARCH_MATCH;
1604 }
1605 else
1606 match |= CPU_FLAGS_ARCH_MATCH;
1607 }
a5ff0eb2 1608 else
c0f3af97
L		 1609 match |= CPU_FLAGS_32BIT_MATCH;
1610 }
3629bb00 1611 }
c0f3af97 1612 return match;
40fb9820
L		 1613}
1614
c6fb90c8
L		 1615static INLINE i386_operand_type
1616operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1617{
c6fb90c8
L		 1618 switch (ARRAY_SIZE (x.array))
1619 {
1620 case 3:
1621 x.array [2] &= y.array [2];
1622 case 2:
1623 x.array [1] &= y.array [1];
1624 case 1:
1625 x.array [0] &= y.array [0];
1626 break;
1627 default:
1628 abort ();
1629 }
1630 return x;
40fb9820
L		 1631}
1632
c6fb90c8
L		 1633static INLINE i386_operand_type
1634operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1635{
c6fb90c8 1636 switch (ARRAY_SIZE (x.array))
40fb9820 1637 {
c6fb90c8
L		 1638 case 3:
1639 x.array [2] |= y.array [2];
1640 case 2:
1641 x.array [1] |= y.array [1];
1642 case 1:
1643 x.array [0] |= y.array [0];
40fb9820
L		 1644 break;
1645 default:
1646 abort ();
1647 }
c6fb90c8
L		 1648 return x;
1649}
40fb9820 1650
c6fb90c8
L		 1651static INLINE i386_operand_type
1652operand_type_xor (i386_operand_type x, i386_operand_type y)
1653{
1654 switch (ARRAY_SIZE (x.array))
1655 {
1656 case 3:
1657 x.array [2] ^= y.array [2];
1658 case 2:
1659 x.array [1] ^= y.array [1];
1660 case 1:
1661 x.array [0] ^= y.array [0];
1662 break;
1663 default:
1664 abort ();
1665 }
40fb9820
L		 1666 return x;
1667}
1668
1669static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1670static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1671static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1672static const i386_operand_type inoutportreg
1673 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1674static const i386_operand_type reg16_inoutportreg
1675 = OPERAND_TYPE_REG16_INOUTPORTREG;
1676static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1677static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1678static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1679static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1680static const i386_operand_type anydisp
1681 = OPERAND_TYPE_ANYDISP;
40fb9820 1682static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1683static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1684static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1685static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1686static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1687static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1688static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1689static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1690static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1691static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1692static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1693static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1694static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1695static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1696
1697enum operand_type
1698{
1699 reg,
40fb9820
L		 1700 imm,
1701 disp,
1702 anymem
1703};
1704
c6fb90c8 1705static INLINE int
40fb9820
L		 1706operand_type_check (i386_operand_type t, enum operand_type c)
1707{
1708 switch (c)
1709 {
1710 case reg:
1711 return (t.bitfield.reg8
1712 || t.bitfield.reg16
1713 || t.bitfield.reg32
1714 || t.bitfield.reg64);
1715
40fb9820
L		 1716 case imm:
1717 return (t.bitfield.imm8
1718 || t.bitfield.imm8s
1719 || t.bitfield.imm16
1720 || t.bitfield.imm32
1721 || t.bitfield.imm32s
1722 || t.bitfield.imm64);
1723
1724 case disp:
1725 return (t.bitfield.disp8
1726 || t.bitfield.disp16
1727 || t.bitfield.disp32
1728 || t.bitfield.disp32s
1729 || t.bitfield.disp64);
1730
1731 case anymem:
1732 return (t.bitfield.disp8
1733 || t.bitfield.disp16
1734 || t.bitfield.disp32
1735 || t.bitfield.disp32s
1736 || t.bitfield.disp64
1737 || t.bitfield.baseindex);
1738
1739 default:
1740 abort ();
1741 }
2cfe26b6
AM		 1742
1743 return 0;
40fb9820
L		 1744}
1745
5c07affc
L		 1746/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1747 operand J for instruction template T. */
1748
1749static INLINE int
d3ce72d0 1750match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1751{
1752 return !((i.types[j].bitfield.byte
1753 && !t->operand_types[j].bitfield.byte)
1754 || (i.types[j].bitfield.word
1755 && !t->operand_types[j].bitfield.word)
1756 || (i.types[j].bitfield.dword
1757 && !t->operand_types[j].bitfield.dword)
1758 || (i.types[j].bitfield.qword
1759 && !t->operand_types[j].bitfield.qword));
1760}
1761
1762/* Return 1 if there is no conflict in any size on operand J for
1763 instruction template T. */
1764
1765static INLINE int
d3ce72d0 1766match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1767{
1768 return (match_reg_size (t, j)
1769 && !((i.types[j].bitfield.unspecified
af508cb9 1770 && !i.broadcast
5c07affc
L		 1771 && !t->operand_types[j].bitfield.unspecified)
1772 || (i.types[j].bitfield.fword
1773 && !t->operand_types[j].bitfield.fword)
1774 || (i.types[j].bitfield.tbyte
1775 && !t->operand_types[j].bitfield.tbyte)
1776 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1777 && !t->operand_types[j].bitfield.xmmword)
1778 || (i.types[j].bitfield.ymmword
43234a1e
L		 1779 && !t->operand_types[j].bitfield.ymmword)
1780 || (i.types[j].bitfield.zmmword
1781 && !t->operand_types[j].bitfield.zmmword)));
5c07affc
L		 1782}
1783
1784/* Return 1 if there is no size conflict on any operands for
1785 instruction template T. */
1786
1787static INLINE int
d3ce72d0 1788operand_size_match (const insn_template *t)
5c07affc
L		 1789{
1790 unsigned int j;
1791 int match = 1;
1792
1793 /* Don't check jump instructions. */
1794 if (t->opcode_modifier.jump
1795 || t->opcode_modifier.jumpbyte
1796 || t->opcode_modifier.jumpdword
1797 || t->opcode_modifier.jumpintersegment)
1798 return match;
1799
1800 /* Check memory and accumulator operand size. */
1801 for (j = 0; j < i.operands; j++)
1802 {
1803 if (t->operand_types[j].bitfield.anysize)
1804 continue;
1805
1806 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1807 {
1808 match = 0;
1809 break;
1810 }
1811
1812 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1813 {
1814 match = 0;
1815 break;
1816 }
1817 }
1818
891edac4 1819 if (match)
5c07affc 1820 return match;
891edac4
L		 1821 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1822 {
1823mismatch:
86e026a4 1824 i.error = operand_size_mismatch;
891edac4
L		 1825 return 0;
1826 }
5c07affc
L		 1827
1828 /* Check reverse. */
9c2799c2 1829 gas_assert (i.operands == 2);
5c07affc
L		 1830
1831 match = 1;
1832 for (j = 0; j < 2; j++)
1833 {
1834 if (t->operand_types[j].bitfield.acc
1835 && !match_reg_size (t, j ? 0 : 1))
891edac4 1836 goto mismatch;
5c07affc
L		 1837
1838 if (i.types[j].bitfield.mem
1839 && !match_mem_size (t, j ? 0 : 1))
891edac4 1840 goto mismatch;
5c07affc
L		 1841 }
1842
1843 return match;
1844}
1845
c6fb90c8 1846static INLINE int
40fb9820
L		 1847operand_type_match (i386_operand_type overlap,
1848 i386_operand_type given)
1849{
1850 i386_operand_type temp = overlap;
1851
1852 temp.bitfield.jumpabsolute = 0;
7d5e4556 1853 temp.bitfield.unspecified = 0;
5c07affc
L		 1854 temp.bitfield.byte = 0;
1855 temp.bitfield.word = 0;
1856 temp.bitfield.dword = 0;
1857 temp.bitfield.fword = 0;
1858 temp.bitfield.qword = 0;
1859 temp.bitfield.tbyte = 0;
1860 temp.bitfield.xmmword = 0;
c0f3af97 1861 temp.bitfield.ymmword = 0;
43234a1e 1862 temp.bitfield.zmmword = 0;
0dfbf9d7 1863 if (operand_type_all_zero (&temp))
891edac4 1864 goto mismatch;
40fb9820 1865
891edac4
L		 1866 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1867 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1868 return 1;
1869
1870mismatch:
a65babc9 1871 i.error = operand_type_mismatch;
891edac4 1872 return 0;
40fb9820
L		 1873}
1874
7d5e4556 1875/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1876 unless the expected operand type register overlap is null.
1877 Note that Acc in a template matches every size of reg. */
1878
c6fb90c8 1879static INLINE int
40fb9820
L		 1880operand_type_register_match (i386_operand_type m0,
1881 i386_operand_type g0,
1882 i386_operand_type t0,
1883 i386_operand_type m1,
1884 i386_operand_type g1,
1885 i386_operand_type t1)
1886{
1887 if (!operand_type_check (g0, reg))
1888 return 1;
1889
1890 if (!operand_type_check (g1, reg))
1891 return 1;
1892
1893 if (g0.bitfield.reg8 == g1.bitfield.reg8
1894 && g0.bitfield.reg16 == g1.bitfield.reg16
1895 && g0.bitfield.reg32 == g1.bitfield.reg32
1896 && g0.bitfield.reg64 == g1.bitfield.reg64)
1897 return 1;
1898
1899 if (m0.bitfield.acc)
1900 {
1901 t0.bitfield.reg8 = 1;
1902 t0.bitfield.reg16 = 1;
1903 t0.bitfield.reg32 = 1;
1904 t0.bitfield.reg64 = 1;
1905 }
1906
1907 if (m1.bitfield.acc)
1908 {
1909 t1.bitfield.reg8 = 1;
1910 t1.bitfield.reg16 = 1;
1911 t1.bitfield.reg32 = 1;
1912 t1.bitfield.reg64 = 1;
1913 }
1914
891edac4
L		 1915 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1916 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1917 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1918 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1919 return 1;
1920
a65babc9 1921 i.error = register_type_mismatch;
891edac4
L		 1922
1923 return 0;
40fb9820
L		 1924}
1925
4c692bc7
JB		 1926static INLINE unsigned int
1927register_number (const reg_entry *r)
1928{
1929 unsigned int nr = r->reg_num;
1930
1931 if (r->reg_flags & RegRex)
1932 nr += 8;
1933
200cbe0f
L		 1934 if (r->reg_flags & RegVRex)
1935 nr += 16;
1936
4c692bc7
JB		 1937 return nr;
1938}
1939
252b5132 1940static INLINE unsigned int
40fb9820 1941mode_from_disp_size (i386_operand_type t)
252b5132 1942{
43234a1e 1943 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
40fb9820
L		 1944 return 1;
1945 else if (t.bitfield.disp16
1946 || t.bitfield.disp32
1947 || t.bitfield.disp32s)
1948 return 2;
1949 else
1950 return 0;
252b5132
RH		 1951}
1952
1953static INLINE int
65879393 1954fits_in_signed_byte (addressT num)
252b5132 1955{
65879393 1956 return num + 0x80 <= 0xff;
47926f60 1957}
252b5132
RH		 1958
1959static INLINE int
65879393 1960fits_in_unsigned_byte (addressT num)
252b5132 1961{
65879393 1962 return num <= 0xff;
47926f60 1963}
252b5132
RH		 1964
1965static INLINE int
65879393 1966fits_in_unsigned_word (addressT num)
252b5132 1967{
65879393 1968 return num <= 0xffff;
47926f60 1969}
252b5132
RH		 1970
1971static INLINE int
65879393 1972fits_in_signed_word (addressT num)
252b5132 1973{
65879393 1974 return num + 0x8000 <= 0xffff;
47926f60 1975}
2a962e6d 1976
3e73aa7c 1977static INLINE int
65879393 1978fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1979{
1980#ifndef BFD64
1981 return 1;
1982#else
65879393 1983 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 1984#endif
1985} /* fits_in_signed_long() */
2a962e6d 1986
3e73aa7c 1987static INLINE int
65879393 1988fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1989{
1990#ifndef BFD64
1991 return 1;
1992#else
65879393 1993 return num <= 0xffffffff;
3e73aa7c
JH		 1994#endif
1995} /* fits_in_unsigned_long() */
252b5132 1996
43234a1e
L		 1997static INLINE int
1998fits_in_vec_disp8 (offsetT num)
1999{
2000 int shift = i.memshift;
2001 unsigned int mask;
2002
2003 if (shift == -1)
2004 abort ();
2005
2006 mask = (1 << shift) - 1;
2007
2008 /* Return 0 if NUM isn't properly aligned. */
2009 if ((num & mask))
2010 return 0;
2011
2012 /* Check if NUM will fit in 8bit after shift. */
2013 return fits_in_signed_byte (num >> shift);
2014}
2015
a683cc34
SP		 2016static INLINE int
2017fits_in_imm4 (offsetT num)
2018{
2019 return (num & 0xf) == num;
2020}
2021
40fb9820 2022static i386_operand_type
e3bb37b5 2023smallest_imm_type (offsetT num)
252b5132 2024{
40fb9820 2025 i386_operand_type t;
7ab9ffdd 2026
0dfbf9d7 2027 operand_type_set (&t, 0);
40fb9820
L		 2028 t.bitfield.imm64 = 1;
2029
2030 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2031 {
2032 /* This code is disabled on the 486 because all the Imm1 forms
2033 in the opcode table are slower on the i486. They're the
2034 versions with the implicitly specified single-position
2035 displacement, which has another syntax if you really want to
2036 use that form. */
40fb9820
L		 2037 t.bitfield.imm1 = 1;
2038 t.bitfield.imm8 = 1;
2039 t.bitfield.imm8s = 1;
2040 t.bitfield.imm16 = 1;
2041 t.bitfield.imm32 = 1;
2042 t.bitfield.imm32s = 1;
2043 }
2044 else if (fits_in_signed_byte (num))
2045 {
2046 t.bitfield.imm8 = 1;
2047 t.bitfield.imm8s = 1;
2048 t.bitfield.imm16 = 1;
2049 t.bitfield.imm32 = 1;
2050 t.bitfield.imm32s = 1;
2051 }
2052 else if (fits_in_unsigned_byte (num))
2053 {
2054 t.bitfield.imm8 = 1;
2055 t.bitfield.imm16 = 1;
2056 t.bitfield.imm32 = 1;
2057 t.bitfield.imm32s = 1;
2058 }
2059 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2060 {
2061 t.bitfield.imm16 = 1;
2062 t.bitfield.imm32 = 1;
2063 t.bitfield.imm32s = 1;
2064 }
2065 else if (fits_in_signed_long (num))
2066 {
2067 t.bitfield.imm32 = 1;
2068 t.bitfield.imm32s = 1;
2069 }
2070 else if (fits_in_unsigned_long (num))
2071 t.bitfield.imm32 = 1;
2072
2073 return t;
47926f60 2074}
252b5132 2075
847f7ad4 2076static offsetT
e3bb37b5 2077offset_in_range (offsetT val, int size)
847f7ad4 2078{
508866be 2079 addressT mask;
ba2adb93 2080
847f7ad4
AM		 2081 switch (size)
2082 {
508866be
L		 2083 case 1: mask = ((addressT) 1 << 8) - 1; break;
2084 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2085 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2086#ifdef BFD64
2087 case 8: mask = ((addressT) 2 << 63) - 1; break;
2088#endif
47926f60 2089 default: abort ();
847f7ad4
AM		 2090 }
2091
9de868bf
L		 2092#ifdef BFD64
2093 /* If BFD64, sign extend val for 32bit address mode. */
2094 if (flag_code != CODE_64BIT
2095 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2096 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2097 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2098#endif
ba2adb93 2099
47926f60 2100 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2101 {
2102 char buf1[40], buf2[40];
2103
2104 sprint_value (buf1, val);
2105 sprint_value (buf2, val & mask);
2106 as_warn (_("%s shortened to %s"), buf1, buf2);
2107 }
2108 return val & mask;
2109}
2110
c32fa91d
L		 2111enum PREFIX_GROUP
2112{
2113 PREFIX_EXIST = 0,
2114 PREFIX_LOCK,
2115 PREFIX_REP,
2116 PREFIX_OTHER
2117};
2118
2119/* Returns
2120 a. PREFIX_EXIST if attempting to add a prefix where one from the
2121 same class already exists.
2122 b. PREFIX_LOCK if lock prefix is added.
2123 c. PREFIX_REP if rep/repne prefix is added.
2124 d. PREFIX_OTHER if other prefix is added.
2125 */
2126
2127static enum PREFIX_GROUP
e3bb37b5 2128add_prefix (unsigned int prefix)
252b5132 2129{
c32fa91d 2130 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2131 unsigned int q;
252b5132 2132
29b0f896
AM		 2133 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2134 && flag_code == CODE_64BIT)
b1905489 2135 {
161a04f6
L		 2136 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2137 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2138 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2139 ret = PREFIX_EXIST;
b1905489
JB		 2140 q = REX_PREFIX;
2141 }
3e73aa7c 2142 else
b1905489
JB		 2143 {
2144 switch (prefix)
2145 {
2146 default:
2147 abort ();
2148
2149 case CS_PREFIX_OPCODE:
2150 case DS_PREFIX_OPCODE:
2151 case ES_PREFIX_OPCODE:
2152 case FS_PREFIX_OPCODE:
2153 case GS_PREFIX_OPCODE:
2154 case SS_PREFIX_OPCODE:
2155 q = SEG_PREFIX;
2156 break;
2157
2158 case REPNE_PREFIX_OPCODE:
2159 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2160 q = REP_PREFIX;
2161 ret = PREFIX_REP;
2162 break;
2163
b1905489 2164 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2165 q = LOCK_PREFIX;
2166 ret = PREFIX_LOCK;
b1905489
JB		 2167 break;
2168
2169 case FWAIT_OPCODE:
2170 q = WAIT_PREFIX;
2171 break;
2172
2173 case ADDR_PREFIX_OPCODE:
2174 q = ADDR_PREFIX;
2175 break;
2176
2177 case DATA_PREFIX_OPCODE:
2178 q = DATA_PREFIX;
2179 break;
2180 }
2181 if (i.prefix[q] != 0)
c32fa91d 2182 ret = PREFIX_EXIST;
b1905489 2183 }
252b5132 2184
b1905489 2185 if (ret)
252b5132 2186 {
b1905489
JB		 2187 if (!i.prefix[q])
2188 ++i.prefixes;
2189 i.prefix[q] |= prefix;
252b5132 2190 }
b1905489
JB		 2191 else
2192 as_bad (_("same type of prefix used twice"));
252b5132 2193
252b5132
RH		 2194 return ret;
2195}
2196
2197static void
78f12dd3 2198update_code_flag (int value, int check)
eecb386c 2199{
78f12dd3
L		 2200 PRINTF_LIKE ((*as_error));
2201
1e9cc1c2 2202 flag_code = (enum flag_code) value;
40fb9820
L		 2203 if (flag_code == CODE_64BIT)
2204 {
2205 cpu_arch_flags.bitfield.cpu64 = 1;
2206 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2207 }
2208 else
2209 {
2210 cpu_arch_flags.bitfield.cpu64 = 0;
2211 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2212 }
2213 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2214 {
78f12dd3
L		 2215 if (check)
2216 as_error = as_fatal;
2217 else
2218 as_error = as_bad;
2219 (*as_error) (_("64bit mode not supported on `%s'."),
2220 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2221 }
40fb9820 2222 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2223 {
78f12dd3
L		 2224 if (check)
2225 as_error = as_fatal;
2226 else
2227 as_error = as_bad;
2228 (*as_error) (_("32bit mode not supported on `%s'."),
2229 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2230 }
eecb386c
AM		 2231 stackop_size = '\0';
2232}
2233
78f12dd3
L		 2234static void
2235set_code_flag (int value)
2236{
2237 update_code_flag (value, 0);
2238}
2239
eecb386c 2240static void
e3bb37b5 2241set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2242{
1e9cc1c2 2243 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2244 if (flag_code != CODE_16BIT)
2245 abort ();
2246 cpu_arch_flags.bitfield.cpu64 = 0;
2247 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2248 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2249}
2250
2251static void
e3bb37b5 2252set_intel_syntax (int syntax_flag)
252b5132
RH		 2253{
2254 /* Find out if register prefixing is specified. */
2255 int ask_naked_reg = 0;
2256
2257 SKIP_WHITESPACE ();
29b0f896 2258 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132 2259 {
d02603dc
NC		 2260 char *string;
2261 int e = get_symbol_name (&string);
252b5132 2262
47926f60 2263 if (strcmp (string, "prefix") == 0)
252b5132 2264 ask_naked_reg = 1;
47926f60 2265 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2266 ask_naked_reg = -1;
2267 else
d0b47220 2268 as_bad (_("bad argument to syntax directive."));
d02603dc 2269 (void) restore_line_pointer (e);
252b5132
RH		 2270 }
2271 demand_empty_rest_of_line ();
c3332e24 2272
252b5132
RH		 2273 intel_syntax = syntax_flag;
2274
2275 if (ask_naked_reg == 0)
f86103b7
AM		 2276 allow_naked_reg = (intel_syntax
2277 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2278 else
2279 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2280
ee86248c 2281 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2282
e4a3b5a4 2283 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2284 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2285 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2286}
2287
1efbbeb4
L		 2288static void
2289set_intel_mnemonic (int mnemonic_flag)
2290{
e1d4d893 2291 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2292}
2293
db51cc60
L		 2294static void
2295set_allow_index_reg (int flag)
2296{
2297 allow_index_reg = flag;
2298}
2299
cb19c032 2300static void
7bab8ab5 2301set_check (int what)
cb19c032 2302{
7bab8ab5
JB		 2303 enum check_kind *kind;
2304 const char *str;
2305
2306 if (what)
2307 {
2308 kind = &operand_check;
2309 str = "operand";
2310 }
2311 else
2312 {
2313 kind = &sse_check;
2314 str = "sse";
2315 }
2316
cb19c032
L		 2317 SKIP_WHITESPACE ();
2318
2319 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2320 {
d02603dc
NC		 2321 char *string;
2322 int e = get_symbol_name (&string);
cb19c032
L		 2323
2324 if (strcmp (string, "none") == 0)
7bab8ab5 2325 *kind = check_none;
cb19c032 2326 else if (strcmp (string, "warning") == 0)
7bab8ab5 2327 *kind = check_warning;
cb19c032 2328 else if (strcmp (string, "error") == 0)
7bab8ab5 2329 *kind = check_error;
cb19c032 2330 else
7bab8ab5 2331 as_bad (_("bad argument to %s_check directive."), str);
d02603dc 2332 (void) restore_line_pointer (e);
cb19c032
L		 2333 }
2334 else
7bab8ab5 2335 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2336
2337 demand_empty_rest_of_line ();
2338}
2339
8a9036a4
L		 2340static void
2341check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2342 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2343{
2344#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2345 static const char *arch;
2346
2347 /* Intel LIOM is only supported on ELF. */
2348 if (!IS_ELF)
2349 return;
2350
2351 if (!arch)
2352 {
2353 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2354 use default_arch. */
2355 arch = cpu_arch_name;
2356 if (!arch)
2357 arch = default_arch;
2358 }
2359
81486035
L		 2360 /* If we are targeting Intel MCU, we must enable it. */
2361 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2362 || new_flag.bitfield.cpuiamcu)
2363 return;
2364
3632d14b 2365 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2366 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2367 || new_flag.bitfield.cpul1om)
8a9036a4 2368 return;
76ba9986 2369
7a9068fe
L		 2370 /* If we are targeting Intel K1OM, we must enable it. */
2371 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2372 || new_flag.bitfield.cpuk1om)
2373 return;
2374
8a9036a4
L		 2375 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2376#endif
2377}
2378
e413e4e9 2379static void
e3bb37b5 2380set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2381{
47926f60 2382 SKIP_WHITESPACE ();
e413e4e9 2383
29b0f896 2384 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9 2385 {
d02603dc
NC		 2386 char *string;
2387 int e = get_symbol_name (&string);
91d6fa6a 2388 unsigned int j;
40fb9820 2389 i386_cpu_flags flags;
e413e4e9 2390
91d6fa6a 2391 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2392 {
91d6fa6a 2393 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2394 {
91d6fa6a 2395 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2396
5c6af06e
JB		 2397 if (*string != '.')
2398 {
91d6fa6a 2399 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2400 cpu_sub_arch_name = NULL;
91d6fa6a 2401 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2402 if (flag_code == CODE_64BIT)
2403 {
2404 cpu_arch_flags.bitfield.cpu64 = 1;
2405 cpu_arch_flags.bitfield.cpuno64 = 0;
2406 }
2407 else
2408 {
2409 cpu_arch_flags.bitfield.cpu64 = 0;
2410 cpu_arch_flags.bitfield.cpuno64 = 1;
2411 }
91d6fa6a
NC		 2412 cpu_arch_isa = cpu_arch[j].type;
2413 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2414 if (!cpu_arch_tune_set)
2415 {
2416 cpu_arch_tune = cpu_arch_isa;
2417 cpu_arch_tune_flags = cpu_arch_isa_flags;
2418 }
5c6af06e
JB		 2419 break;
2420 }
40fb9820 2421
293f5f65
L		 2422 flags = cpu_flags_or (cpu_arch_flags,
2423 cpu_arch[j].flags);
81486035
L		 2424
2425 if (!valid_iamcu_cpu_flags (&flags))
2426 as_fatal (_("`%s' isn't valid for Intel MCU"),
2427 cpu_arch[j].name);
2428 else if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2429 {
6305a203
L		 2430 if (cpu_sub_arch_name)
2431 {
2432 char *name = cpu_sub_arch_name;
2433 cpu_sub_arch_name = concat (name,
91d6fa6a 2434 cpu_arch[j].name,
1bf57e9f 2435 (const char *) NULL);
6305a203
L		 2436 free (name);
2437 }
2438 else
91d6fa6a 2439 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2440 cpu_arch_flags = flags;
a586129e 2441 cpu_arch_isa_flags = flags;
5c6af06e 2442 }
d02603dc 2443 (void) restore_line_pointer (e);
5c6af06e
JB		 2444 demand_empty_rest_of_line ();
2445 return;
e413e4e9
AM		 2446 }
2447 }
293f5f65
L		 2448
2449 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2450 {
2451 /* Disable an ISA entension. */
2452 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2453 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2454 {
2455 flags = cpu_flags_and_not (cpu_arch_flags,
2456 cpu_noarch[j].flags);
2457 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2458 {
2459 if (cpu_sub_arch_name)
2460 {
2461 char *name = cpu_sub_arch_name;
2462 cpu_sub_arch_name = concat (name, string,
2463 (const char *) NULL);
2464 free (name);
2465 }
2466 else
2467 cpu_sub_arch_name = xstrdup (string);
2468 cpu_arch_flags = flags;
2469 cpu_arch_isa_flags = flags;
2470 }
2471 (void) restore_line_pointer (e);
2472 demand_empty_rest_of_line ();
2473 return;
2474 }
2475
2476 j = ARRAY_SIZE (cpu_arch);
2477 }
2478
91d6fa6a 2479 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2480 as_bad (_("no such architecture: `%s'"), string);
2481
2482 *input_line_pointer = e;
2483 }
2484 else
2485 as_bad (_("missing cpu architecture"));
2486
fddf5b5b
AM		 2487 no_cond_jump_promotion = 0;
2488 if (*input_line_pointer == ','
29b0f896 2489 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b 2490 {
d02603dc
NC		 2491 char *string;
2492 char e;
2493
2494 ++input_line_pointer;
2495 e = get_symbol_name (&string);
fddf5b5b
AM		 2496
2497 if (strcmp (string, "nojumps") == 0)
2498 no_cond_jump_promotion = 1;
2499 else if (strcmp (string, "jumps") == 0)
2500 ;
2501 else
2502 as_bad (_("no such architecture modifier: `%s'"), string);
2503
d02603dc 2504 (void) restore_line_pointer (e);
fddf5b5b
AM		 2505 }
2506
e413e4e9
AM		 2507 demand_empty_rest_of_line ();
2508}
2509
8a9036a4
L		 2510enum bfd_architecture
2511i386_arch (void)
2512{
3632d14b 2513 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2514 {
2515 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2516 || flag_code != CODE_64BIT)
2517 as_fatal (_("Intel L1OM is 64bit ELF only"));
2518 return bfd_arch_l1om;
2519 }
7a9068fe
L		 2520 else if (cpu_arch_isa == PROCESSOR_K1OM)
2521 {
2522 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2523 || flag_code != CODE_64BIT)
2524 as_fatal (_("Intel K1OM is 64bit ELF only"));
2525 return bfd_arch_k1om;
2526 }
81486035
L		 2527 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2528 {
2529 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2530 || flag_code == CODE_64BIT)
2531 as_fatal (_("Intel MCU is 32bit ELF only"));
2532 return bfd_arch_iamcu;
2533 }
8a9036a4
L		 2534 else
2535 return bfd_arch_i386;
2536}
2537
b9d79e03 2538unsigned long
7016a5d5 2539i386_mach (void)
b9d79e03 2540{
351f65ca 2541 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2542 {
3632d14b 2543 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2544 {
351f65ca
L		 2545 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2546 || default_arch[6] != '\0')
8a9036a4
L		 2547 as_fatal (_("Intel L1OM is 64bit ELF only"));
2548 return bfd_mach_l1om;
2549 }
7a9068fe
L		 2550 else if (cpu_arch_isa == PROCESSOR_K1OM)
2551 {
2552 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2553 || default_arch[6] != '\0')
2554 as_fatal (_("Intel K1OM is 64bit ELF only"));
2555 return bfd_mach_k1om;
2556 }
351f65ca 2557 else if (default_arch[6] == '\0')
8a9036a4 2558 return bfd_mach_x86_64;
351f65ca
L		 2559 else
2560 return bfd_mach_x64_32;
8a9036a4 2561 }
5197d474
L		 2562 else if (!strcmp (default_arch, "i386")
2563 || !strcmp (default_arch, "iamcu"))
81486035
L		 2564 {
2565 if (cpu_arch_isa == PROCESSOR_IAMCU)
2566 {
2567 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2568 as_fatal (_("Intel MCU is 32bit ELF only"));
2569 return bfd_mach_i386_iamcu;
2570 }
2571 else
2572 return bfd_mach_i386_i386;
2573 }
b9d79e03 2574 else
2b5d6a91 2575 as_fatal (_("unknown architecture"));
b9d79e03 2576}
b9d79e03 2577\f
252b5132 2578void
7016a5d5 2579md_begin (void)
252b5132
RH		 2580{
2581 const char *hash_err;
2582
47926f60 2583 /* Initialize op_hash hash table. */
252b5132
RH		 2584 op_hash = hash_new ();
2585
2586 {
d3ce72d0 2587 const insn_template *optab;
29b0f896 2588 templates *core_optab;
252b5132 2589
47926f60
KH		 2590 /* Setup for loop. */
2591 optab = i386_optab;
add39d23 2592 core_optab = XNEW (templates);
252b5132
RH		 2593 core_optab->start = optab;
2594
2595 while (1)
2596 {
2597 ++optab;
2598 if (optab->name == NULL
2599 || strcmp (optab->name, (optab - 1)->name) != 0)
2600 {
2601 /* different name --> ship out current template list;
47926f60 2602 add to hash table; & begin anew. */
252b5132
RH		 2603 core_optab->end = optab;
2604 hash_err = hash_insert (op_hash,
2605 (optab - 1)->name,
5a49b8ac 2606 (void *) core_optab);
252b5132
RH		 2607 if (hash_err)
2608 {
b37df7c4 2609 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2610 (optab - 1)->name,
2611 hash_err);
2612 }
2613 if (optab->name == NULL)
2614 break;
add39d23 2615 core_optab = XNEW (templates);
252b5132
RH		 2616 core_optab->start = optab;
2617 }
2618 }
2619 }
2620
47926f60 2621 /* Initialize reg_hash hash table. */
252b5132
RH		 2622 reg_hash = hash_new ();
2623 {
29b0f896 2624 const reg_entry *regtab;
c3fe08fa 2625 unsigned int regtab_size = i386_regtab_size;
252b5132 2626
c3fe08fa 2627 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2628 {
5a49b8ac 2629 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2630 if (hash_err)
b37df7c4 2631 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2632 regtab->reg_name,
2633 hash_err);
252b5132
RH		 2634 }
2635 }
2636
47926f60 2637 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2638 {
29b0f896
AM		 2639 int c;
2640 char *p;
252b5132
RH		 2641
2642 for (c = 0; c < 256; c++)
2643 {
3882b010 2644 if (ISDIGIT (c))
252b5132
RH		 2645 {
2646 digit_chars[c] = c;
2647 mnemonic_chars[c] = c;
2648 register_chars[c] = c;
2649 operand_chars[c] = c;
2650 }
3882b010 2651 else if (ISLOWER (c))
252b5132
RH		 2652 {
2653 mnemonic_chars[c] = c;
2654 register_chars[c] = c;
2655 operand_chars[c] = c;
2656 }
3882b010 2657 else if (ISUPPER (c))
252b5132 2658 {
3882b010 2659 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2660 register_chars[c] = mnemonic_chars[c];
2661 operand_chars[c] = c;
2662 }
43234a1e
L		 2663 else if (c == '{' || c == '}')
2664 operand_chars[c] = c;
252b5132 2665
3882b010 2666 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2667 identifier_chars[c] = c;
2668 else if (c >= 128)
2669 {
2670 identifier_chars[c] = c;
2671 operand_chars[c] = c;
2672 }
2673 }
2674
2675#ifdef LEX_AT
2676 identifier_chars['@'] = '@';
32137342
NC		 2677#endif
2678#ifdef LEX_QM
2679 identifier_chars['?'] = '?';
2680 operand_chars['?'] = '?';
252b5132 2681#endif
252b5132 2682 digit_chars['-'] = '-';
c0f3af97 2683 mnemonic_chars['_'] = '_';
791fe849 2684 mnemonic_chars['-'] = '-';
0003779b 2685 mnemonic_chars['.'] = '.';
252b5132
RH		 2686 identifier_chars['_'] = '_';
2687 identifier_chars['.'] = '.';
2688
2689 for (p = operand_special_chars; *p != '\0'; p++)
2690 operand_chars[(unsigned char) *p] = *p;
2691 }
2692
a4447b93
RH		 2693 if (flag_code == CODE_64BIT)
2694 {
ca19b261
KT		 2695#if defined (OBJ_COFF) && defined (TE_PE)
2696 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2697 ? 32 : 16);
2698#else
a4447b93 2699 x86_dwarf2_return_column = 16;
ca19b261 2700#endif
61ff971f 2701 x86_cie_data_alignment = -8;
a4447b93
RH		 2702 }
2703 else
2704 {
2705 x86_dwarf2_return_column = 8;
2706 x86_cie_data_alignment = -4;
2707 }
252b5132
RH		 2708}
2709
2710void
e3bb37b5 2711i386_print_statistics (FILE *file)
252b5132
RH		 2712{
2713 hash_print_statistics (file, "i386 opcode", op_hash);
2714 hash_print_statistics (file, "i386 register", reg_hash);
2715}
2716\f
252b5132
RH		 2717#ifdef DEBUG386
2718
ce8a8b2f 2719/* Debugging routines for md_assemble. */
d3ce72d0 2720static void pte (insn_template *);
40fb9820 2721static void pt (i386_operand_type);
e3bb37b5
L		 2722static void pe (expressionS *);
2723static void ps (symbolS *);
252b5132
RH		 2724
2725static void
e3bb37b5 2726pi (char *line, i386_insn *x)
252b5132 2727{
09137c09 2728 unsigned int j;
252b5132
RH		 2729
2730 fprintf (stdout, "%s: template ", line);
2731 pte (&x->tm);
09f131f2
JH		 2732 fprintf (stdout, " address: base %s index %s scale %x\n",
2733 x->base_reg ? x->base_reg->reg_name : "none",
2734 x->index_reg ? x->index_reg->reg_name : "none",
2735 x->log2_scale_factor);
2736 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2737 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2738 fprintf (stdout, " sib: base %x index %x scale %x\n",
2739 x->sib.base, x->sib.index, x->sib.scale);
2740 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2741 (x->rex & REX_W) != 0,
2742 (x->rex & REX_R) != 0,
2743 (x->rex & REX_X) != 0,
2744 (x->rex & REX_B) != 0);
09137c09 2745 for (j = 0; j < x->operands; j++)
252b5132 2746 {
09137c09
SP		 2747 fprintf (stdout, " #%d: ", j + 1);
2748 pt (x->types[j]);
252b5132 2749 fprintf (stdout, "\n");
09137c09
SP		 2750 if (x->types[j].bitfield.reg8
2751 || x->types[j].bitfield.reg16
2752 || x->types[j].bitfield.reg32
2753 || x->types[j].bitfield.reg64
2754 || x->types[j].bitfield.regmmx
2755 || x->types[j].bitfield.regxmm
2756 || x->types[j].bitfield.regymm
43234a1e 2757 || x->types[j].bitfield.regzmm
09137c09
SP		 2758 || x->types[j].bitfield.sreg2
2759 || x->types[j].bitfield.sreg3
2760 || x->types[j].bitfield.control
2761 || x->types[j].bitfield.debug
2762 || x->types[j].bitfield.test)
2763 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2764 if (operand_type_check (x->types[j], imm))
2765 pe (x->op[j].imms);
2766 if (operand_type_check (x->types[j], disp))
2767 pe (x->op[j].disps);
252b5132
RH		 2768 }
2769}
2770
2771static void
d3ce72d0 2772pte (insn_template *t)
252b5132 2773{
09137c09 2774 unsigned int j;
252b5132 2775 fprintf (stdout, " %d operands ", t->operands);
47926f60 2776 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2777 if (t->extension_opcode != None)
2778 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2779 if (t->opcode_modifier.d)
252b5132 2780 fprintf (stdout, "D");
40fb9820 2781 if (t->opcode_modifier.w)
252b5132
RH		 2782 fprintf (stdout, "W");
2783 fprintf (stdout, "\n");
09137c09 2784 for (j = 0; j < t->operands; j++)
252b5132 2785 {
09137c09
SP		 2786 fprintf (stdout, " #%d type ", j + 1);
2787 pt (t->operand_types[j]);
252b5132
RH		 2788 fprintf (stdout, "\n");
2789 }
2790}
2791
2792static void
e3bb37b5 2793pe (expressionS *e)
252b5132 2794{
24eab124 2795 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2796 fprintf (stdout, " add_number %ld (%lx)\n",
2797 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2798 if (e->X_add_symbol)
2799 {
2800 fprintf (stdout, " add_symbol ");
2801 ps (e->X_add_symbol);
2802 fprintf (stdout, "\n");
2803 }
2804 if (e->X_op_symbol)
2805 {
2806 fprintf (stdout, " op_symbol ");
2807 ps (e->X_op_symbol);
2808 fprintf (stdout, "\n");
2809 }
2810}
2811
2812static void
e3bb37b5 2813ps (symbolS *s)
252b5132
RH		 2814{
2815 fprintf (stdout, "%s type %s%s",
2816 S_GET_NAME (s),
2817 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2818 segment_name (S_GET_SEGMENT (s)));
2819}
2820
7b81dfbb 2821static struct type_name
252b5132 2822 {
40fb9820
L		 2823 i386_operand_type mask;
2824 const char *name;
252b5132 2825 }
7b81dfbb 2826const type_names[] =
252b5132 2827{
40fb9820
L		 2828 { OPERAND_TYPE_REG8, "r8" },
2829 { OPERAND_TYPE_REG16, "r16" },
2830 { OPERAND_TYPE_REG32, "r32" },
2831 { OPERAND_TYPE_REG64, "r64" },
2832 { OPERAND_TYPE_IMM8, "i8" },
2833 { OPERAND_TYPE_IMM8, "i8s" },
2834 { OPERAND_TYPE_IMM16, "i16" },
2835 { OPERAND_TYPE_IMM32, "i32" },
2836 { OPERAND_TYPE_IMM32S, "i32s" },
2837 { OPERAND_TYPE_IMM64, "i64" },
2838 { OPERAND_TYPE_IMM1, "i1" },
2839 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2840 { OPERAND_TYPE_DISP8, "d8" },
2841 { OPERAND_TYPE_DISP16, "d16" },
2842 { OPERAND_TYPE_DISP32, "d32" },
2843 { OPERAND_TYPE_DISP32S, "d32s" },
2844 { OPERAND_TYPE_DISP64, "d64" },
43234a1e 2845 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
40fb9820
L		 2846 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2847 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2848 { OPERAND_TYPE_CONTROL, "control reg" },
2849 { OPERAND_TYPE_TEST, "test reg" },
2850 { OPERAND_TYPE_DEBUG, "debug reg" },
2851 { OPERAND_TYPE_FLOATREG, "FReg" },
2852 { OPERAND_TYPE_FLOATACC, "FAcc" },
2853 { OPERAND_TYPE_SREG2, "SReg2" },
2854 { OPERAND_TYPE_SREG3, "SReg3" },
2855 { OPERAND_TYPE_ACC, "Acc" },
2856 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2857 { OPERAND_TYPE_REGMMX, "rMMX" },
2858 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2859 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2860 { OPERAND_TYPE_REGZMM, "rZMM" },
2861 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2862 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2863};
2864
2865static void
40fb9820 2866pt (i386_operand_type t)
252b5132 2867{
40fb9820 2868 unsigned int j;
c6fb90c8 2869 i386_operand_type a;
252b5132 2870
40fb9820 2871 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2872 {
2873 a = operand_type_and (t, type_names[j].mask);
0349dc08 2874 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2875 fprintf (stdout, "%s, ", type_names[j].name);
2876 }
252b5132
RH		 2877 fflush (stdout);
2878}
2879
2880#endif /* DEBUG386 */
2881\f
252b5132 2882static bfd_reloc_code_real_type
3956db08 2883reloc (unsigned int size,
64e74474
AM		 2884 int pcrel,
2885 int sign,
2886 bfd_reloc_code_real_type other)
252b5132 2887{
47926f60 2888 if (other != NO_RELOC)
3956db08 2889 {
91d6fa6a 2890 reloc_howto_type *rel;
3956db08
JB		 2891
2892 if (size == 8)
2893 switch (other)
2894 {
64e74474
AM		 2895 case BFD_RELOC_X86_64_GOT32:
2896 return BFD_RELOC_X86_64_GOT64;
2897 break;
553d1284
L		 2898 case BFD_RELOC_X86_64_GOTPLT64:
2899 return BFD_RELOC_X86_64_GOTPLT64;
2900 break;
64e74474
AM		 2901 case BFD_RELOC_X86_64_PLTOFF64:
2902 return BFD_RELOC_X86_64_PLTOFF64;
2903 break;
2904 case BFD_RELOC_X86_64_GOTPC32:
2905 other = BFD_RELOC_X86_64_GOTPC64;
2906 break;
2907 case BFD_RELOC_X86_64_GOTPCREL:
2908 other = BFD_RELOC_X86_64_GOTPCREL64;
2909 break;
2910 case BFD_RELOC_X86_64_TPOFF32:
2911 other = BFD_RELOC_X86_64_TPOFF64;
2912 break;
2913 case BFD_RELOC_X86_64_DTPOFF32:
2914 other = BFD_RELOC_X86_64_DTPOFF64;
2915 break;
2916 default:
2917 break;
3956db08 2918 }
e05278af 2919
8ce3d284 2920#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2921 if (other == BFD_RELOC_SIZE32)
2922 {
2923 if (size == 8)
1ab668bf 2924 other = BFD_RELOC_SIZE64;
8fd4256d 2925 if (pcrel)
1ab668bf
AM		 2926 {
2927 as_bad (_("there are no pc-relative size relocations"));
2928 return NO_RELOC;
2929 }
8fd4256d 2930 }
8ce3d284 2931#endif
8fd4256d 2932
e05278af 2933 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2934 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2935 sign = -1;
2936
91d6fa6a
NC		 2937 rel = bfd_reloc_type_lookup (stdoutput, other);
2938 if (!rel)
3956db08 2939 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2940 else if (size != bfd_get_reloc_size (rel))
3956db08 2941 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2942 bfd_get_reloc_size (rel),
3956db08 2943 size);
91d6fa6a 2944 else if (pcrel && !rel->pc_relative)
3956db08 2945 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2946 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2947 && !sign)
91d6fa6a 2948 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2949 && sign > 0))
3956db08
JB		 2950 as_bad (_("relocated field and relocation type differ in signedness"));
2951 else
2952 return other;
2953 return NO_RELOC;
2954 }
252b5132
RH		 2955
2956 if (pcrel)
2957 {
3e73aa7c 2958 if (!sign)
3956db08 2959 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2960 switch (size)
2961 {
2962 case 1: return BFD_RELOC_8_PCREL;
2963 case 2: return BFD_RELOC_16_PCREL;
d258b828 2964 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2965 case 8: return BFD_RELOC_64_PCREL;
252b5132 2966 }
3956db08 2967 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2968 }
2969 else
2970 {
3956db08 2971 if (sign > 0)
e5cb08ac 2972 switch (size)
3e73aa7c
JH		 2973 {
2974 case 4: return BFD_RELOC_X86_64_32S;
2975 }
2976 else
2977 switch (size)
2978 {
2979 case 1: return BFD_RELOC_8;
2980 case 2: return BFD_RELOC_16;
2981 case 4: return BFD_RELOC_32;
2982 case 8: return BFD_RELOC_64;
2983 }
3956db08
JB		 2984 as_bad (_("cannot do %s %u byte relocation"),
2985 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2986 }
2987
0cc9e1d3 2988 return NO_RELOC;
252b5132
RH		 2989}
2990
47926f60
KH		 2991/* Here we decide which fixups can be adjusted to make them relative to
2992 the beginning of the section instead of the symbol. Basically we need
2993 to make sure that the dynamic relocations are done correctly, so in
2994 some cases we force the original symbol to be used. */
2995
252b5132 2996int
e3bb37b5 2997tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2998{
6d249963 2999#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 3000 if (!IS_ELF)
31312f95
AM		 3001 return 1;
3002
a161fe53
AM		 3003 /* Don't adjust pc-relative references to merge sections in 64-bit
3004 mode. */
3005 if (use_rela_relocations
3006 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3007 && fixP->fx_pcrel)
252b5132 3008 return 0;
31312f95 3009
8d01d9a9
AJ		 3010 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3011 and changed later by validate_fix. */
3012 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3013 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3014 return 0;
3015
8fd4256d
L		 3016 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3017 for size relocations. */
3018 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3019 || fixP->fx_r_type == BFD_RELOC_SIZE64
3020 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 3021 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3022 || fixP->fx_r_type == BFD_RELOC_386_GOT32
02a86693 3023 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
13ae64f3
JJ		 3024 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3025 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3026 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3027 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 3028 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3029 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 3030 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3031 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 3032 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3033 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 3034 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3035 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 3036 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
56ceb5b5
L		 3037 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3038 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
bffbf940
JJ		 3039 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3040 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3041 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 3042 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 3043 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3044 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 3045 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3046 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 3047 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3048 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 3049 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3050 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3051 return 0;
31312f95 3052#endif
252b5132
RH		 3053 return 1;
3054}
252b5132 3055
b4cac588 3056static int
e3bb37b5 3057intel_float_operand (const char *mnemonic)
252b5132 3058{
9306ca4a
JB		 3059 /* Note that the value returned is meaningful only for opcodes with (memory)
3060 operands, hence the code here is free to improperly handle opcodes that
3061 have no operands (for better performance and smaller code). */
3062
3063 if (mnemonic[0] != 'f')
3064 return 0; /* non-math */
3065
3066 switch (mnemonic[1])
3067 {
3068 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3069 the fs segment override prefix not currently handled because no
3070 call path can make opcodes without operands get here */
3071 case 'i':
3072 return 2 /* integer op */;
3073 case 'l':
3074 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3075 return 3; /* fldcw/fldenv */
3076 break;
3077 case 'n':
3078 if (mnemonic[2] != 'o' /* fnop */)
3079 return 3; /* non-waiting control op */
3080 break;
3081 case 'r':
3082 if (mnemonic[2] == 's')
3083 return 3; /* frstor/frstpm */
3084 break;
3085 case 's':
3086 if (mnemonic[2] == 'a')
3087 return 3; /* fsave */
3088 if (mnemonic[2] == 't')
3089 {
3090 switch (mnemonic[3])
3091 {
3092 case 'c': /* fstcw */
3093 case 'd': /* fstdw */
3094 case 'e': /* fstenv */
3095 case 's': /* fsts[gw] */
3096 return 3;
3097 }
3098 }
3099 break;
3100 case 'x':
3101 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3102 return 0; /* fxsave/fxrstor are not really math ops */
3103 break;
3104 }
252b5132 3105
9306ca4a 3106 return 1;
252b5132
RH		 3107}
3108
c0f3af97
L		 3109/* Build the VEX prefix. */
3110
3111static void
d3ce72d0 3112build_vex_prefix (const insn_template *t)
c0f3af97
L		 3113{
3114 unsigned int register_specifier;
3115 unsigned int implied_prefix;
3116 unsigned int vector_length;
3117
3118 /* Check register specifier. */
3119 if (i.vex.register_specifier)
43234a1e
L		 3120 {
3121 register_specifier =
3122 ~register_number (i.vex.register_specifier) & 0xf;
3123 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3124 }
c0f3af97
L		 3125 else
3126 register_specifier = 0xf;
3127
fa99fab2
L		 3128 /* Use 2-byte VEX prefix by swappping destination and source
3129 operand. */
3130 if (!i.swap_operand
3131 && i.operands == i.reg_operands
7f399153 3132 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 3133 && i.tm.opcode_modifier.s
3134 && i.rex == REX_B)
3135 {
3136 unsigned int xchg = i.operands - 1;
3137 union i386_op temp_op;
3138 i386_operand_type temp_type;
3139
3140 temp_type = i.types[xchg];
3141 i.types[xchg] = i.types[0];
3142 i.types[0] = temp_type;
3143 temp_op = i.op[xchg];
3144 i.op[xchg] = i.op[0];
3145 i.op[0] = temp_op;
3146
9c2799c2 3147 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3148
3149 i.rex = REX_R;
3150 xchg = i.rm.regmem;
3151 i.rm.regmem = i.rm.reg;
3152 i.rm.reg = xchg;
3153
3154 /* Use the next insn. */
3155 i.tm = t[1];
3156 }
3157
539f890d
L		 3158 if (i.tm.opcode_modifier.vex == VEXScalar)
3159 vector_length = avxscalar;
3160 else
3161 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3162
3163 switch ((i.tm.base_opcode >> 8) & 0xff)
3164 {
3165 case 0:
3166 implied_prefix = 0;
3167 break;
3168 case DATA_PREFIX_OPCODE:
3169 implied_prefix = 1;
3170 break;
3171 case REPE_PREFIX_OPCODE:
3172 implied_prefix = 2;
3173 break;
3174 case REPNE_PREFIX_OPCODE:
3175 implied_prefix = 3;
3176 break;
3177 default:
3178 abort ();
3179 }
3180
3181 /* Use 2-byte VEX prefix if possible. */
7f399153 3182 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3183 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3184 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3185 {
3186 /* 2-byte VEX prefix. */
3187 unsigned int r;
3188
3189 i.vex.length = 2;
3190 i.vex.bytes[0] = 0xc5;
3191
3192 /* Check the REX.R bit. */
3193 r = (i.rex & REX_R) ? 0 : 1;
3194 i.vex.bytes[1] = (r << 7
3195 | register_specifier << 3
3196 | vector_length << 2
3197 | implied_prefix);
3198 }
3199 else
3200 {
3201 /* 3-byte VEX prefix. */
3202 unsigned int m, w;
3203
f88c9eb0 3204 i.vex.length = 3;
f88c9eb0 3205
7f399153 3206 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3207 {
7f399153
L		 3208 case VEX0F:
3209 m = 0x1;
80de6e00 3210 i.vex.bytes[0] = 0xc4;
7f399153
L		 3211 break;
3212 case VEX0F38:
3213 m = 0x2;
80de6e00 3214 i.vex.bytes[0] = 0xc4;
7f399153
L		 3215 break;
3216 case VEX0F3A:
3217 m = 0x3;
80de6e00 3218 i.vex.bytes[0] = 0xc4;
7f399153
L		 3219 break;
3220 case XOP08:
5dd85c99
SP		 3221 m = 0x8;
3222 i.vex.bytes[0] = 0x8f;
7f399153
L		 3223 break;
3224 case XOP09:
f88c9eb0
SP		 3225 m = 0x9;
3226 i.vex.bytes[0] = 0x8f;
7f399153
L		 3227 break;
3228 case XOP0A:
f88c9eb0
SP		 3229 m = 0xa;
3230 i.vex.bytes[0] = 0x8f;
7f399153
L		 3231 break;
3232 default:
3233 abort ();
f88c9eb0 3234 }
c0f3af97 3235
c0f3af97
L		 3236 /* The high 3 bits of the second VEX byte are 1's compliment
3237 of RXB bits from REX. */
3238 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3239
3240 /* Check the REX.W bit. */
3241 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3242 if (i.tm.opcode_modifier.vexw == VEXW1)
3243 w = 1;
c0f3af97
L		 3244
3245 i.vex.bytes[2] = (w << 7
3246 | register_specifier << 3
3247 | vector_length << 2
3248 | implied_prefix);
3249 }
3250}
3251
43234a1e
L		 3252/* Build the EVEX prefix. */
3253
3254static void
3255build_evex_prefix (void)
3256{
3257 unsigned int register_specifier;
3258 unsigned int implied_prefix;
3259 unsigned int m, w;
3260 rex_byte vrex_used = 0;
3261
3262 /* Check register specifier. */
3263 if (i.vex.register_specifier)
3264 {
3265 gas_assert ((i.vrex & REX_X) == 0);
3266
3267 register_specifier = i.vex.register_specifier->reg_num;
3268 if ((i.vex.register_specifier->reg_flags & RegRex))
3269 register_specifier += 8;
3270 /* The upper 16 registers are encoded in the fourth byte of the
3271 EVEX prefix. */
3272 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3273 i.vex.bytes[3] = 0x8;
3274 register_specifier = ~register_specifier & 0xf;
3275 }
3276 else
3277 {
3278 register_specifier = 0xf;
3279
3280 /* Encode upper 16 vector index register in the fourth byte of
3281 the EVEX prefix. */
3282 if (!(i.vrex & REX_X))
3283 i.vex.bytes[3] = 0x8;
3284 else
3285 vrex_used |= REX_X;
3286 }
3287
3288 switch ((i.tm.base_opcode >> 8) & 0xff)
3289 {
3290 case 0:
3291 implied_prefix = 0;
3292 break;
3293 case DATA_PREFIX_OPCODE:
3294 implied_prefix = 1;
3295 break;
3296 case REPE_PREFIX_OPCODE:
3297 implied_prefix = 2;
3298 break;
3299 case REPNE_PREFIX_OPCODE:
3300 implied_prefix = 3;
3301 break;
3302 default:
3303 abort ();
3304 }
3305
3306 /* 4 byte EVEX prefix. */
3307 i.vex.length = 4;
3308 i.vex.bytes[0] = 0x62;
3309
3310 /* mmmm bits. */
3311 switch (i.tm.opcode_modifier.vexopcode)
3312 {
3313 case VEX0F:
3314 m = 1;
3315 break;
3316 case VEX0F38:
3317 m = 2;
3318 break;
3319 case VEX0F3A:
3320 m = 3;
3321 break;
3322 default:
3323 abort ();
3324 break;
3325 }
3326
3327 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3328 bits from REX. */
3329 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3330
3331 /* The fifth bit of the second EVEX byte is 1's compliment of the
3332 REX_R bit in VREX. */
3333 if (!(i.vrex & REX_R))
3334 i.vex.bytes[1] |= 0x10;
3335 else
3336 vrex_used |= REX_R;
3337
3338 if ((i.reg_operands + i.imm_operands) == i.operands)
3339 {
3340 /* When all operands are registers, the REX_X bit in REX is not
3341 used. We reuse it to encode the upper 16 registers, which is
3342 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3343 as 1's compliment. */
3344 if ((i.vrex & REX_B))
3345 {
3346 vrex_used |= REX_B;
3347 i.vex.bytes[1] &= ~0x40;
3348 }
3349 }
3350
3351 /* EVEX instructions shouldn't need the REX prefix. */
3352 i.vrex &= ~vrex_used;
3353 gas_assert (i.vrex == 0);
3354
3355 /* Check the REX.W bit. */
3356 w = (i.rex & REX_W) ? 1 : 0;
3357 if (i.tm.opcode_modifier.vexw)
3358 {
3359 if (i.tm.opcode_modifier.vexw == VEXW1)
3360 w = 1;
3361 }
3362 /* If w is not set it means we are dealing with WIG instruction. */
3363 else if (!w)
3364 {
3365 if (evexwig == evexw1)
3366 w = 1;
3367 }
3368
3369 /* Encode the U bit. */
3370 implied_prefix |= 0x4;
3371
3372 /* The third byte of the EVEX prefix. */
3373 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3374
3375 /* The fourth byte of the EVEX prefix. */
3376 /* The zeroing-masking bit. */
3377 if (i.mask && i.mask->zeroing)
3378 i.vex.bytes[3] |= 0x80;
3379
3380 /* Don't always set the broadcast bit if there is no RC. */
3381 if (!i.rounding)
3382 {
3383 /* Encode the vector length. */
3384 unsigned int vec_length;
3385
3386 switch (i.tm.opcode_modifier.evex)
3387 {
3388 case EVEXLIG: /* LL' is ignored */
3389 vec_length = evexlig << 5;
3390 break;
3391 case EVEX128:
3392 vec_length = 0 << 5;
3393 break;
3394 case EVEX256:
3395 vec_length = 1 << 5;
3396 break;
3397 case EVEX512:
3398 vec_length = 2 << 5;
3399 break;
3400 default:
3401 abort ();
3402 break;
3403 }
3404 i.vex.bytes[3] |= vec_length;
3405 /* Encode the broadcast bit. */
3406 if (i.broadcast)
3407 i.vex.bytes[3] |= 0x10;
3408 }
3409 else
3410 {
3411 if (i.rounding->type != saeonly)
3412 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3413 else
d3d3c6db 3414 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3415 }
3416
3417 if (i.mask && i.mask->mask)
3418 i.vex.bytes[3] |= i.mask->mask->reg_num;
3419}
3420
65da13b5
L		 3421static void
3422process_immext (void)
3423{
3424 expressionS *exp;
3425
4c692bc7
JB		 3426 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3427 && i.operands > 0)
65da13b5 3428 {
4c692bc7
JB		 3429 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3430 with an opcode suffix which is coded in the same place as an
3431 8-bit immediate field would be.
3432 Here we check those operands and remove them afterwards. */
65da13b5
L		 3433 unsigned int x;
3434
3435 for (x = 0; x < i.operands; x++)
4c692bc7 3436 if (register_number (i.op[x].regs) != x)
65da13b5 3437 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3438 register_prefix, i.op[x].regs->reg_name, x + 1,
3439 i.tm.name);
3440
3441 i.operands = 0;
65da13b5
L		 3442 }
3443
9916071f
AP		 3444 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3445 {
3446 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3447 suffix which is coded in the same place as an 8-bit immediate
3448 field would be.
3449 Here we check those operands and remove them afterwards. */
3450 unsigned int x;
3451
3452 if (i.operands != 3)
3453 abort();
3454
3455 for (x = 0; x < 2; x++)
3456 if (register_number (i.op[x].regs) != x)
3457 goto bad_register_operand;
3458
3459 /* Check for third operand for mwaitx/monitorx insn. */
3460 if (register_number (i.op[x].regs)
3461 != (x + (i.tm.extension_opcode == 0xfb)))
3462 {
3463bad_register_operand:
3464 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3465 register_prefix, i.op[x].regs->reg_name, x+1,
3466 i.tm.name);
3467 }
3468
3469 i.operands = 0;
3470 }
3471
c0f3af97 3472 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3473 which is coded in the same place as an 8-bit immediate field
3474 would be. Here we fake an 8-bit immediate operand from the
3475 opcode suffix stored in tm.extension_opcode.
3476
c1e679ec 3477 AVX instructions also use this encoding, for some of
c0f3af97 3478 3 argument instructions. */
65da13b5 3479
43234a1e 3480 gas_assert (i.imm_operands <= 1
7ab9ffdd 3481 && (i.operands <= 2
43234a1e
L		 3482 || ((i.tm.opcode_modifier.vex
3483 || i.tm.opcode_modifier.evex)
7ab9ffdd 3484 && i.operands <= 4)));
65da13b5
L		 3485
3486 exp = &im_expressions[i.imm_operands++];
3487 i.op[i.operands].imms = exp;
3488 i.types[i.operands] = imm8;
3489 i.operands++;
3490 exp->X_op = O_constant;
3491 exp->X_add_number = i.tm.extension_opcode;
3492 i.tm.extension_opcode = None;
3493}
3494
42164a71
L		 3495
3496static int
3497check_hle (void)
3498{
3499 switch (i.tm.opcode_modifier.hleprefixok)
3500 {
3501 default:
3502 abort ();
82c2def5 3503 case HLEPrefixNone:
165de32a
L		 3504 as_bad (_("invalid instruction `%s' after `%s'"),
3505 i.tm.name, i.hle_prefix);
42164a71 3506 return 0;
82c2def5 3507 case HLEPrefixLock:
42164a71
L		 3508 if (i.prefix[LOCK_PREFIX])
3509 return 1;
165de32a 3510 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3511 return 0;
82c2def5 3512 case HLEPrefixAny:
42164a71 3513 return 1;
82c2def5 3514 case HLEPrefixRelease:
42164a71
L		 3515 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3516 {
3517 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3518 i.tm.name);
3519 return 0;
3520 }
3521 if (i.mem_operands == 0
3522 || !operand_type_check (i.types[i.operands - 1], anymem))
3523 {
3524 as_bad (_("memory destination needed for instruction `%s'"
3525 " after `xrelease'"), i.tm.name);
3526 return 0;
3527 }
3528 return 1;
3529 }
3530}
3531
252b5132
RH		 3532/* This is the guts of the machine-dependent assembler. LINE points to a
3533 machine dependent instruction. This function is supposed to emit
3534 the frags/bytes it assembles to. */
3535
3536void
65da13b5 3537md_assemble (char *line)
252b5132 3538{
40fb9820 3539 unsigned int j;
83b16ac6 3540 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
d3ce72d0 3541 const insn_template *t;
252b5132 3542
47926f60 3543 /* Initialize globals. */
252b5132
RH		 3544 memset (&i, '\0', sizeof (i));
3545 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3546 i.reloc[j] = NO_RELOC;
252b5132
RH		 3547 memset (disp_expressions, '\0', sizeof (disp_expressions));
3548 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3549 save_stack_p = save_stack;
252b5132
RH		 3550
3551 /* First parse an instruction mnemonic & call i386_operand for the operands.
3552 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3553 start of a (possibly prefixed) mnemonic. */
252b5132 3554
29b0f896
AM		 3555 line = parse_insn (line, mnemonic);
3556 if (line == NULL)
3557 return;
83b16ac6 3558 mnem_suffix = i.suffix;
252b5132 3559
29b0f896 3560 line = parse_operands (line, mnemonic);
ee86248c 3561 this_operand = -1;
8325cc63
JB		 3562 xfree (i.memop1_string);
3563 i.memop1_string = NULL;
29b0f896
AM		 3564 if (line == NULL)
3565 return;
252b5132 3566
29b0f896
AM		 3567 /* Now we've parsed the mnemonic into a set of templates, and have the
3568 operands at hand. */
3569
3570 /* All intel opcodes have reversed operands except for "bound" and
3571 "enter". We also don't reverse intersegment "jmp" and "call"
3572 instructions with 2 immediate operands so that the immediate segment
050dfa73 3573 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3574 if (intel_syntax
3575 && i.operands > 1
29b0f896 3576 && (strcmp (mnemonic, "bound") != 0)
30123838 3577 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3578 && !(operand_type_check (i.types[0], imm)
3579 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3580 swap_operands ();
3581
ec56d5c0
JB		 3582 /* The order of the immediates should be reversed
3583 for 2 immediates extrq and insertq instructions */
3584 if (i.imm_operands == 2
3585 && (strcmp (mnemonic, "extrq") == 0
3586 || strcmp (mnemonic, "insertq") == 0))
3587 swap_2_operands (0, 1);
3588
29b0f896
AM		 3589 if (i.imm_operands)
3590 optimize_imm ();
3591
b300c311
L		 3592 /* Don't optimize displacement for movabs since it only takes 64bit
3593 displacement. */
3594 if (i.disp_operands
a501d77e 3595 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3596 && (flag_code != CODE_64BIT
3597 || strcmp (mnemonic, "movabs") != 0))
3598 optimize_disp ();
29b0f896
AM		 3599
3600 /* Next, we find a template that matches the given insn,
3601 making sure the overlap of the given operands types is consistent
3602 with the template operand types. */
252b5132 3603
83b16ac6 3604 if (!(t = match_template (mnem_suffix)))
29b0f896 3605 return;
252b5132 3606
7bab8ab5 3607 if (sse_check != check_none
81f8a913 3608 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3609 && (i.tm.cpu_flags.bitfield.cpusse
3610 || i.tm.cpu_flags.bitfield.cpusse2
3611 || i.tm.cpu_flags.bitfield.cpusse3
3612 || i.tm.cpu_flags.bitfield.cpussse3
3613 || i.tm.cpu_flags.bitfield.cpusse4_1
3614 || i.tm.cpu_flags.bitfield.cpusse4_2))
3615 {
7bab8ab5 3616 (sse_check == check_warning
daf50ae7
L		 3617 ? as_warn
3618 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3619 }
3620
321fd21e
L		 3621 /* Zap movzx and movsx suffix. The suffix has been set from
3622 "word ptr" or "byte ptr" on the source operand in Intel syntax
3623 or extracted from mnemonic in AT&T syntax. But we'll use
3624 the destination register to choose the suffix for encoding. */
3625 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3626 {
321fd21e
L		 3627 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3628 there is no suffix, the default will be byte extension. */
3629 if (i.reg_operands != 2
3630 && !i.suffix
7ab9ffdd 3631 && intel_syntax)
321fd21e
L		 3632 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3633
3634 i.suffix = 0;
cd61ebfe 3635 }
24eab124 3636
40fb9820 3637 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3638 if (!add_prefix (FWAIT_OPCODE))
3639 return;
252b5132 3640
d5de92cf
L		 3641 /* Check if REP prefix is OK. */
3642 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3643 {
3644 as_bad (_("invalid instruction `%s' after `%s'"),
3645 i.tm.name, i.rep_prefix);
3646 return;
3647 }
3648
c1ba0266
L		 3649 /* Check for lock without a lockable instruction. Destination operand
3650 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3651 if (i.prefix[LOCK_PREFIX]
3652 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3653 || i.mem_operands == 0
3654 || (i.tm.base_opcode != 0x86
3655 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3656 {
3657 as_bad (_("expecting lockable instruction after `lock'"));
3658 return;
3659 }
3660
42164a71 3661 /* Check if HLE prefix is OK. */
165de32a 3662 if (i.hle_prefix && !check_hle ())
42164a71
L		 3663 return;
3664
7e8b059b
L		 3665 /* Check BND prefix. */
3666 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3667 as_bad (_("expecting valid branch instruction after `bnd'"));
3668
3669 if (i.tm.cpu_flags.bitfield.cpumpx
3670 && flag_code == CODE_64BIT
3671 && i.prefix[ADDR_PREFIX])
3672 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3673
3674 /* Insert BND prefix. */
3675 if (add_bnd_prefix
3676 && i.tm.opcode_modifier.bndprefixok
3677 && !i.prefix[BND_PREFIX])
3678 add_prefix (BND_PREFIX_OPCODE);
3679
29b0f896 3680 /* Check string instruction segment overrides. */
40fb9820 3681 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3682 {
3683 if (!check_string ())
5dd0794d 3684 return;
fc0763e6 3685 i.disp_operands = 0;
29b0f896 3686 }
5dd0794d 3687
29b0f896
AM		 3688 if (!process_suffix ())
3689 return;
e413e4e9 3690
bc0844ae
L		 3691 /* Update operand types. */
3692 for (j = 0; j < i.operands; j++)
3693 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3694
29b0f896
AM		 3695 /* Make still unresolved immediate matches conform to size of immediate
3696 given in i.suffix. */
3697 if (!finalize_imm ())
3698 return;
252b5132 3699
40fb9820 3700 if (i.types[0].bitfield.imm1)
29b0f896 3701 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3702
9afe6eb8
L		 3703 /* We only need to check those implicit registers for instructions
3704 with 3 operands or less. */
3705 if (i.operands <= 3)
3706 for (j = 0; j < i.operands; j++)
3707 if (i.types[j].bitfield.inoutportreg
3708 || i.types[j].bitfield.shiftcount
3709 || i.types[j].bitfield.acc
3710 || i.types[j].bitfield.floatacc)
3711 i.reg_operands--;
40fb9820 3712
c0f3af97
L		 3713 /* ImmExt should be processed after SSE2AVX. */
3714 if (!i.tm.opcode_modifier.sse2avx
3715 && i.tm.opcode_modifier.immext)
65da13b5 3716 process_immext ();
252b5132 3717
29b0f896
AM		 3718 /* For insns with operands there are more diddles to do to the opcode. */
3719 if (i.operands)
3720 {
3721 if (!process_operands ())
3722 return;
3723 }
40fb9820 3724 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3725 {
3726 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3727 as_warn (_("translating to `%sp'"), i.tm.name);
3728 }
252b5132 3729
9e5e5283
L		 3730 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3731 {
3732 if (flag_code == CODE_16BIT)
3733 {
3734 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3735 i.tm.name);
3736 return;
3737 }
c0f3af97 3738
9e5e5283
L		 3739 if (i.tm.opcode_modifier.vex)
3740 build_vex_prefix (t);
3741 else
3742 build_evex_prefix ();
3743 }
43234a1e 3744
5dd85c99
SP		 3745 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3746 instructions may define INT_OPCODE as well, so avoid this corner
3747 case for those instructions that use MODRM. */
3748 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3749 && !i.tm.opcode_modifier.modrm
3750 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3751 {
3752 i.tm.base_opcode = INT3_OPCODE;
3753 i.imm_operands = 0;
3754 }
252b5132 3755
40fb9820
L		 3756 if ((i.tm.opcode_modifier.jump
3757 || i.tm.opcode_modifier.jumpbyte
3758 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3759 && i.op[0].disps->X_op == O_constant)
3760 {
3761 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3762 the absolute address given by the constant. Since ix86 jumps and
3763 calls are pc relative, we need to generate a reloc. */
3764 i.op[0].disps->X_add_symbol = &abs_symbol;
3765 i.op[0].disps->X_op = O_symbol;
3766 }
252b5132 3767
40fb9820 3768 if (i.tm.opcode_modifier.rex64)
161a04f6 3769 i.rex |= REX_W;
252b5132 3770
29b0f896
AM		 3771 /* For 8 bit registers we need an empty rex prefix. Also if the
3772 instruction already has a prefix, we need to convert old
3773 registers to new ones. */
773f551c 3774
40fb9820 3775 if ((i.types[0].bitfield.reg8
29b0f896 3776 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3777 || (i.types[1].bitfield.reg8
29b0f896 3778 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3779 || ((i.types[0].bitfield.reg8
3780 || i.types[1].bitfield.reg8)
29b0f896
AM		 3781 && i.rex != 0))
3782 {
3783 int x;
726c5dcd 3784
29b0f896
AM		 3785 i.rex |= REX_OPCODE;
3786 for (x = 0; x < 2; x++)
3787 {
3788 /* Look for 8 bit operand that uses old registers. */
40fb9820 3789 if (i.types[x].bitfield.reg8
29b0f896 3790 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3791 {
29b0f896
AM		 3792 /* In case it is "hi" register, give up. */
3793 if (i.op[x].regs->reg_num > 3)
a540244d 3794 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3795 "instruction requiring REX prefix."),
a540244d 3796 register_prefix, i.op[x].regs->reg_name);
773f551c 3797
29b0f896
AM		 3798 /* Otherwise it is equivalent to the extended register.
3799 Since the encoding doesn't change this is merely
3800 cosmetic cleanup for debug output. */
3801
3802 i.op[x].regs = i.op[x].regs + 8;
773f551c 3803 }
29b0f896
AM		 3804 }
3805 }
773f551c 3806
7ab9ffdd 3807 if (i.rex != 0)
29b0f896
AM		 3808 add_prefix (REX_OPCODE | i.rex);
3809
3810 /* We are ready to output the insn. */
3811 output_insn ();
3812}
3813
3814static char *
e3bb37b5 3815parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3816{
3817 char *l = line;
3818 char *token_start = l;
3819 char *mnem_p;
5c6af06e 3820 int supported;
d3ce72d0 3821 const insn_template *t;
b6169b20 3822 char *dot_p = NULL;
29b0f896 3823
29b0f896
AM		 3824 while (1)
3825 {
3826 mnem_p = mnemonic;
3827 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3828 {
b6169b20
L		 3829 if (*mnem_p == '.')
3830 dot_p = mnem_p;
29b0f896
AM		 3831 mnem_p++;
3832 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3833 {
29b0f896
AM		 3834 as_bad (_("no such instruction: `%s'"), token_start);
3835 return NULL;
3836 }
3837 l++;
3838 }
3839 if (!is_space_char (*l)
3840 && *l != END_OF_INSN
e44823cf
JB		 3841 && (intel_syntax
3842 || (*l != PREFIX_SEPARATOR
3843 && *l != ',')))
29b0f896
AM		 3844 {
3845 as_bad (_("invalid character %s in mnemonic"),
3846 output_invalid (*l));
3847 return NULL;
3848 }
3849 if (token_start == l)
3850 {
e44823cf 3851 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3852 as_bad (_("expecting prefix; got nothing"));
3853 else
3854 as_bad (_("expecting mnemonic; got nothing"));
3855 return NULL;
3856 }
45288df1 3857
29b0f896 3858 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3859 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3860
29b0f896
AM		 3861 if (*l != END_OF_INSN
3862 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3863 && current_templates
40fb9820 3864 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3865 {
c6fb90c8 3866 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3867 {
3868 as_bad ((flag_code != CODE_64BIT
3869 ? _("`%s' is only supported in 64-bit mode")
3870 : _("`%s' is not supported in 64-bit mode")),
3871 current_templates->start->name);
3872 return NULL;
3873 }
29b0f896
AM		 3874 /* If we are in 16-bit mode, do not allow addr16 or data16.
3875 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3876 if ((current_templates->start->opcode_modifier.size16
3877 || current_templates->start->opcode_modifier.size32)
29b0f896 3878 && flag_code != CODE_64BIT
40fb9820 3879 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3880 ^ (flag_code == CODE_16BIT)))
3881 {
3882 as_bad (_("redundant %s prefix"),
3883 current_templates->start->name);
3884 return NULL;
45288df1 3885 }
29b0f896
AM		 3886 /* Add prefix, checking for repeated prefixes. */
3887 switch (add_prefix (current_templates->start->base_opcode))
3888 {
c32fa91d 3889 case PREFIX_EXIST:
29b0f896 3890 return NULL;
c32fa91d 3891 case PREFIX_REP:
42164a71 3892 if (current_templates->start->cpu_flags.bitfield.cpuhle)
165de32a 3893 i.hle_prefix = current_templates->start->name;
7e8b059b
L		 3894 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3895 i.bnd_prefix = current_templates->start->name;
42164a71 3896 else
d5de92cf 3897 i.rep_prefix = current_templates->start->name;
29b0f896 3898 break;
c32fa91d
L		 3899 default:
3900 break;
29b0f896
AM		 3901 }
3902 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3903 token_start = ++l;
3904 }
3905 else
3906 break;
3907 }
45288df1 3908
30a55f88 3909 if (!current_templates)
b6169b20 3910 {
f8a5c266
L		 3911 /* Check if we should swap operand or force 32bit displacement in
3912 encoding. */
30a55f88
L		 3913 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3914 i.swap_operand = 1;
8d63c93e 3915 else if (mnem_p - 3 == dot_p
a501d77e
L		 3916 && dot_p[1] == 'd'
3917 && dot_p[2] == '8')
3918 i.disp_encoding = disp_encoding_8bit;
8d63c93e 3919 else if (mnem_p - 4 == dot_p
f8a5c266
L		 3920 && dot_p[1] == 'd'
3921 && dot_p[2] == '3'
3922 && dot_p[3] == '2')
a501d77e 3923 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 3924 else
3925 goto check_suffix;
3926 mnem_p = dot_p;
3927 *dot_p = '\0';
d3ce72d0 3928 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3929 }
3930
29b0f896
AM		 3931 if (!current_templates)
3932 {
b6169b20 3933check_suffix:
29b0f896
AM		 3934 /* See if we can get a match by trimming off a suffix. */
3935 switch (mnem_p[-1])
3936 {
3937 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3938 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3939 i.suffix = SHORT_MNEM_SUFFIX;
3940 else
29b0f896
AM		 3941 case BYTE_MNEM_SUFFIX:
3942 case QWORD_MNEM_SUFFIX:
3943 i.suffix = mnem_p[-1];
3944 mnem_p[-1] = '\0';
d3ce72d0
NC		 3945 current_templates = (const templates *) hash_find (op_hash,
3946 mnemonic);
29b0f896
AM		 3947 break;
3948 case SHORT_MNEM_SUFFIX:
3949 case LONG_MNEM_SUFFIX:
3950 if (!intel_syntax)
3951 {
3952 i.suffix = mnem_p[-1];
3953 mnem_p[-1] = '\0';
d3ce72d0
NC		 3954 current_templates = (const templates *) hash_find (op_hash,
3955 mnemonic);
29b0f896
AM		 3956 }
3957 break;
252b5132 3958
29b0f896
AM		 3959 /* Intel Syntax. */
3960 case 'd':
3961 if (intel_syntax)
3962 {
9306ca4a 3963 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3964 i.suffix = SHORT_MNEM_SUFFIX;
3965 else
3966 i.suffix = LONG_MNEM_SUFFIX;
3967 mnem_p[-1] = '\0';
d3ce72d0
NC		 3968 current_templates = (const templates *) hash_find (op_hash,
3969 mnemonic);
29b0f896
AM		 3970 }
3971 break;
3972 }
3973 if (!current_templates)
3974 {
3975 as_bad (_("no such instruction: `%s'"), token_start);
3976 return NULL;
3977 }
3978 }
252b5132 3979
40fb9820
L		 3980 if (current_templates->start->opcode_modifier.jump
3981 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3982 {
3983 /* Check for a branch hint. We allow ",pt" and ",pn" for
3984 predict taken and predict not taken respectively.
3985 I'm not sure that branch hints actually do anything on loop
3986 and jcxz insns (JumpByte) for current Pentium4 chips. They
3987 may work in the future and it doesn't hurt to accept them
3988 now. */
3989 if (l[0] == ',' && l[1] == 'p')
3990 {
3991 if (l[2] == 't')
3992 {
3993 if (!add_prefix (DS_PREFIX_OPCODE))
3994 return NULL;
3995 l += 3;
3996 }
3997 else if (l[2] == 'n')
3998 {
3999 if (!add_prefix (CS_PREFIX_OPCODE))
4000 return NULL;
4001 l += 3;
4002 }
4003 }
4004 }
4005 /* Any other comma loses. */
4006 if (*l == ',')
4007 {
4008 as_bad (_("invalid character %s in mnemonic"),
4009 output_invalid (*l));
4010 return NULL;
4011 }
252b5132 4012
29b0f896 4013 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 4014 supported = 0;
4015 for (t = current_templates->start; t < current_templates->end; ++t)
4016 {
c0f3af97
L		 4017 supported |= cpu_flags_match (t);
4018 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 4019 goto skip;
5c6af06e 4020 }
3629bb00 4021
c0f3af97 4022 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 4023 {
4024 as_bad (flag_code == CODE_64BIT
4025 ? _("`%s' is not supported in 64-bit mode")
4026 : _("`%s' is only supported in 64-bit mode"),
4027 current_templates->start->name);
4028 return NULL;
4029 }
c0f3af97 4030 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 4031 {
3629bb00 4032 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 4033 current_templates->start->name,
41aacd83 4034 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 4035 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4036 return NULL;
29b0f896 4037 }
3629bb00
L		 4038
4039skip:
4040 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 4041 && (flag_code != CODE_16BIT))
29b0f896
AM		 4042 {
4043 as_warn (_("use .code16 to ensure correct addressing mode"));
4044 }
252b5132 4045
29b0f896
AM		 4046 return l;
4047}
252b5132 4048
29b0f896 4049static char *
e3bb37b5 4050parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 4051{
4052 char *token_start;
3138f287 4053
29b0f896
AM		 4054 /* 1 if operand is pending after ','. */
4055 unsigned int expecting_operand = 0;
252b5132 4056
29b0f896
AM		 4057 /* Non-zero if operand parens not balanced. */
4058 unsigned int paren_not_balanced;
4059
4060 while (*l != END_OF_INSN)
4061 {
4062 /* Skip optional white space before operand. */
4063 if (is_space_char (*l))
4064 ++l;
d02603dc 4065 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
29b0f896
AM		 4066 {
4067 as_bad (_("invalid character %s before operand %d"),
4068 output_invalid (*l),
4069 i.operands + 1);
4070 return NULL;
4071 }
d02603dc 4072 token_start = l; /* After white space. */
29b0f896
AM		 4073 paren_not_balanced = 0;
4074 while (paren_not_balanced || *l != ',')
4075 {
4076 if (*l == END_OF_INSN)
4077 {
4078 if (paren_not_balanced)
4079 {
4080 if (!intel_syntax)
4081 as_bad (_("unbalanced parenthesis in operand %d."),
4082 i.operands + 1);
4083 else
4084 as_bad (_("unbalanced brackets in operand %d."),
4085 i.operands + 1);
4086 return NULL;
4087 }
4088 else
4089 break; /* we are done */
4090 }
d02603dc 4091 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
29b0f896
AM		 4092 {
4093 as_bad (_("invalid character %s in operand %d"),
4094 output_invalid (*l),
4095 i.operands + 1);
4096 return NULL;
4097 }
4098 if (!intel_syntax)
4099 {
4100 if (*l == '(')
4101 ++paren_not_balanced;
4102 if (*l == ')')
4103 --paren_not_balanced;
4104 }
4105 else
4106 {
4107 if (*l == '[')
4108 ++paren_not_balanced;
4109 if (*l == ']')
4110 --paren_not_balanced;
4111 }
4112 l++;
4113 }
4114 if (l != token_start)
4115 { /* Yes, we've read in another operand. */
4116 unsigned int operand_ok;
4117 this_operand = i.operands++;
7d5e4556 4118 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4119 if (i.operands > MAX_OPERANDS)
4120 {
4121 as_bad (_("spurious operands; (%d operands/instruction max)"),
4122 MAX_OPERANDS);
4123 return NULL;
4124 }
4125 /* Now parse operand adding info to 'i' as we go along. */
4126 END_STRING_AND_SAVE (l);
4127
4128 if (intel_syntax)
4129 operand_ok =
4130 i386_intel_operand (token_start,
4131 intel_float_operand (mnemonic));
4132 else
a7619375 4133 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4134
4135 RESTORE_END_STRING (l);
4136 if (!operand_ok)
4137 return NULL;
4138 }
4139 else
4140 {
4141 if (expecting_operand)
4142 {
4143 expecting_operand_after_comma:
4144 as_bad (_("expecting operand after ','; got nothing"));
4145 return NULL;
4146 }
4147 if (*l == ',')
4148 {
4149 as_bad (_("expecting operand before ','; got nothing"));
4150 return NULL;
4151 }
4152 }
7f3f1ea2 4153
29b0f896
AM		 4154 /* Now *l must be either ',' or END_OF_INSN. */
4155 if (*l == ',')
4156 {
4157 if (*++l == END_OF_INSN)
4158 {
4159 /* Just skip it, if it's \n complain. */
4160 goto expecting_operand_after_comma;
4161 }
4162 expecting_operand = 1;
4163 }
4164 }
4165 return l;
4166}
7f3f1ea2 4167
050dfa73 4168static void
4d456e3d 4169swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4170{
4171 union i386_op temp_op;
40fb9820 4172 i386_operand_type temp_type;
050dfa73 4173 enum bfd_reloc_code_real temp_reloc;
4eed87de 4174
050dfa73
MM		 4175 temp_type = i.types[xchg2];
4176 i.types[xchg2] = i.types[xchg1];
4177 i.types[xchg1] = temp_type;
4178 temp_op = i.op[xchg2];
4179 i.op[xchg2] = i.op[xchg1];
4180 i.op[xchg1] = temp_op;
4181 temp_reloc = i.reloc[xchg2];
4182 i.reloc[xchg2] = i.reloc[xchg1];
4183 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4184
4185 if (i.mask)
4186 {
4187 if (i.mask->operand == xchg1)
4188 i.mask->operand = xchg2;
4189 else if (i.mask->operand == xchg2)
4190 i.mask->operand = xchg1;
4191 }
4192 if (i.broadcast)
4193 {
4194 if (i.broadcast->operand == xchg1)
4195 i.broadcast->operand = xchg2;
4196 else if (i.broadcast->operand == xchg2)
4197 i.broadcast->operand = xchg1;
4198 }
4199 if (i.rounding)
4200 {
4201 if (i.rounding->operand == xchg1)
4202 i.rounding->operand = xchg2;
4203 else if (i.rounding->operand == xchg2)
4204 i.rounding->operand = xchg1;
4205 }
050dfa73
MM		 4206}
4207
29b0f896 4208static void
e3bb37b5 4209swap_operands (void)
29b0f896 4210{
b7c61d9a 4211 switch (i.operands)
050dfa73 4212 {
c0f3af97 4213 case 5:
b7c61d9a 4214 case 4:
4d456e3d 4215 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 4216 case 3:
4217 case 2:
4d456e3d 4218 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4219 break;
4220 default:
4221 abort ();
29b0f896 4222 }
29b0f896
AM		 4223
4224 if (i.mem_operands == 2)
4225 {
4226 const seg_entry *temp_seg;
4227 temp_seg = i.seg[0];
4228 i.seg[0] = i.seg[1];
4229 i.seg[1] = temp_seg;
4230 }
4231}
252b5132 4232
29b0f896
AM		 4233/* Try to ensure constant immediates are represented in the smallest
4234 opcode possible. */
4235static void
e3bb37b5 4236optimize_imm (void)
29b0f896
AM		 4237{
4238 char guess_suffix = 0;
4239 int op;
252b5132 4240
29b0f896
AM		 4241 if (i.suffix)
4242 guess_suffix = i.suffix;
4243 else if (i.reg_operands)
4244 {
4245 /* Figure out a suffix from the last register operand specified.
4246 We can't do this properly yet, ie. excluding InOutPortReg,
4247 but the following works for instructions with immediates.
4248 In any case, we can't set i.suffix yet. */
4249 for (op = i.operands; --op >= 0;)
40fb9820 4250 if (i.types[op].bitfield.reg8)
7ab9ffdd 4251 {
40fb9820
L		 4252 guess_suffix = BYTE_MNEM_SUFFIX;
4253 break;
4254 }
4255 else if (i.types[op].bitfield.reg16)
252b5132 4256 {
40fb9820
L		 4257 guess_suffix = WORD_MNEM_SUFFIX;
4258 break;
4259 }
4260 else if (i.types[op].bitfield.reg32)
4261 {
4262 guess_suffix = LONG_MNEM_SUFFIX;
4263 break;
4264 }
4265 else if (i.types[op].bitfield.reg64)
4266 {
4267 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4268 break;
252b5132 4269 }
29b0f896
AM		 4270 }
4271 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4272 guess_suffix = WORD_MNEM_SUFFIX;
4273
4274 for (op = i.operands; --op >= 0;)
40fb9820 4275 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4276 {
4277 switch (i.op[op].imms->X_op)
252b5132 4278 {
29b0f896
AM		 4279 case O_constant:
4280 /* If a suffix is given, this operand may be shortened. */
4281 switch (guess_suffix)
252b5132 4282 {
29b0f896 4283 case LONG_MNEM_SUFFIX:
40fb9820
L		 4284 i.types[op].bitfield.imm32 = 1;
4285 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4286 break;
4287 case WORD_MNEM_SUFFIX:
40fb9820
L		 4288 i.types[op].bitfield.imm16 = 1;
4289 i.types[op].bitfield.imm32 = 1;
4290 i.types[op].bitfield.imm32s = 1;
4291 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4292 break;
4293 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4294 i.types[op].bitfield.imm8 = 1;
4295 i.types[op].bitfield.imm8s = 1;
4296 i.types[op].bitfield.imm16 = 1;
4297 i.types[op].bitfield.imm32 = 1;
4298 i.types[op].bitfield.imm32s = 1;
4299 i.types[op].bitfield.imm64 = 1;
29b0f896 4300 break;
252b5132 4301 }
252b5132 4302
29b0f896
AM		 4303 /* If this operand is at most 16 bits, convert it
4304 to a signed 16 bit number before trying to see
4305 whether it will fit in an even smaller size.
4306 This allows a 16-bit operand such as $0xffe0 to
4307 be recognised as within Imm8S range. */
40fb9820 4308 if ((i.types[op].bitfield.imm16)
29b0f896 4309 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4310 {
29b0f896
AM		 4311 i.op[op].imms->X_add_number =
4312 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4313 }
a28def75
L		 4314#ifdef BFD64
4315 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
40fb9820 4316 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4317 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4318 == 0))
4319 {
4320 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4321 ^ ((offsetT) 1 << 31))
4322 - ((offsetT) 1 << 31));
4323 }
a28def75 4324#endif
40fb9820 4325 i.types[op]
c6fb90c8
L		 4326 = operand_type_or (i.types[op],
4327 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4328
29b0f896
AM		 4329 /* We must avoid matching of Imm32 templates when 64bit
4330 only immediate is available. */
4331 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4332 i.types[op].bitfield.imm32 = 0;
29b0f896 4333 break;
252b5132 4334
29b0f896
AM		 4335 case O_absent:
4336 case O_register:
4337 abort ();
4338
4339 /* Symbols and expressions. */
4340 default:
9cd96992
JB		 4341 /* Convert symbolic operand to proper sizes for matching, but don't
4342 prevent matching a set of insns that only supports sizes other
4343 than those matching the insn suffix. */
4344 {
40fb9820 4345 i386_operand_type mask, allowed;
d3ce72d0 4346 const insn_template *t;
9cd96992 4347
0dfbf9d7
L		 4348 operand_type_set (&mask, 0);
4349 operand_type_set (&allowed, 0);
40fb9820 4350
4eed87de
AM		 4351 for (t = current_templates->start;
4352 t < current_templates->end;
4353 ++t)
c6fb90c8
L		 4354 allowed = operand_type_or (allowed,
4355 t->operand_types[op]);
9cd96992
JB		 4356 switch (guess_suffix)
4357 {
4358 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4359 mask.bitfield.imm64 = 1;
4360 mask.bitfield.imm32s = 1;
9cd96992
JB		 4361 break;
4362 case LONG_MNEM_SUFFIX:
40fb9820 4363 mask.bitfield.imm32 = 1;
9cd96992
JB		 4364 break;
4365 case WORD_MNEM_SUFFIX:
40fb9820 4366 mask.bitfield.imm16 = 1;
9cd96992
JB		 4367 break;
4368 case BYTE_MNEM_SUFFIX:
40fb9820 4369 mask.bitfield.imm8 = 1;
9cd96992
JB		 4370 break;
4371 default:
9cd96992
JB		 4372 break;
4373 }
c6fb90c8 4374 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4375 if (!operand_type_all_zero (&allowed))
c6fb90c8 4376 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4377 }
29b0f896 4378 break;
252b5132 4379 }
29b0f896
AM		 4380 }
4381}
47926f60 4382
29b0f896
AM		 4383/* Try to use the smallest displacement type too. */
4384static void
e3bb37b5 4385optimize_disp (void)
29b0f896
AM		 4386{
4387 int op;
3e73aa7c 4388
29b0f896 4389 for (op = i.operands; --op >= 0;)
40fb9820 4390 if (operand_type_check (i.types[op], disp))
252b5132 4391 {
b300c311 4392 if (i.op[op].disps->X_op == O_constant)
252b5132 4393 {
91d6fa6a 4394 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4395
40fb9820 4396 if (i.types[op].bitfield.disp16
91d6fa6a 4397 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4398 {
4399 /* If this operand is at most 16 bits, convert
4400 to a signed 16 bit number and don't use 64bit
4401 displacement. */
91d6fa6a 4402 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4403 i.types[op].bitfield.disp64 = 0;
b300c311 4404 }
a28def75
L		 4405#ifdef BFD64
4406 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
40fb9820 4407 if (i.types[op].bitfield.disp32
91d6fa6a 4408 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4409 {
4410 /* If this operand is at most 32 bits, convert
4411 to a signed 32 bit number and don't use 64bit
4412 displacement. */
91d6fa6a
NC		 4413 op_disp &= (((offsetT) 2 << 31) - 1);
4414 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4415 i.types[op].bitfield.disp64 = 0;
b300c311 4416 }
a28def75 4417#endif
91d6fa6a 4418 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4419 {
40fb9820
L		 4420 i.types[op].bitfield.disp8 = 0;
4421 i.types[op].bitfield.disp16 = 0;
4422 i.types[op].bitfield.disp32 = 0;
4423 i.types[op].bitfield.disp32s = 0;
4424 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4425 i.op[op].disps = 0;
4426 i.disp_operands--;
4427 }
4428 else if (flag_code == CODE_64BIT)
4429 {
91d6fa6a 4430 if (fits_in_signed_long (op_disp))
28a9d8f5 4431 {
40fb9820
L		 4432 i.types[op].bitfield.disp64 = 0;
4433 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4434 }
0e1147d9 4435 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4436 && fits_in_unsigned_long (op_disp))
40fb9820 4437 i.types[op].bitfield.disp32 = 1;
b300c311 4438 }
40fb9820
L		 4439 if ((i.types[op].bitfield.disp32
4440 || i.types[op].bitfield.disp32s
4441 || i.types[op].bitfield.disp16)
91d6fa6a 4442 && fits_in_signed_byte (op_disp))
40fb9820 4443 i.types[op].bitfield.disp8 = 1;
252b5132 4444 }
67a4f2b7
AO		 4445 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4446 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4447 {
4448 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4449 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4450 i.types[op].bitfield.disp8 = 0;
4451 i.types[op].bitfield.disp16 = 0;
4452 i.types[op].bitfield.disp32 = 0;
4453 i.types[op].bitfield.disp32s = 0;
4454 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4455 }
4456 else
b300c311 4457 /* We only support 64bit displacement on constants. */
40fb9820 4458 i.types[op].bitfield.disp64 = 0;
252b5132 4459 }
29b0f896
AM		 4460}
4461
6c30d220
L		 4462/* Check if operands are valid for the instruction. */
4463
4464static int
4465check_VecOperands (const insn_template *t)
4466{
43234a1e
L		 4467 unsigned int op;
4468
6c30d220
L		 4469 /* Without VSIB byte, we can't have a vector register for index. */
4470 if (!t->opcode_modifier.vecsib
4471 && i.index_reg
4472 && (i.index_reg->reg_type.bitfield.regxmm
43234a1e
L		 4473 || i.index_reg->reg_type.bitfield.regymm
4474 || i.index_reg->reg_type.bitfield.regzmm))
6c30d220
L		 4475 {
4476 i.error = unsupported_vector_index_register;
4477 return 1;
4478 }
4479
ad8ecc81
MZ		 4480 /* Check if default mask is allowed. */
4481 if (t->opcode_modifier.nodefmask
4482 && (!i.mask || i.mask->mask->reg_num == 0))
4483 {
4484 i.error = no_default_mask;
4485 return 1;
4486 }
4487
7bab8ab5
JB		 4488 /* For VSIB byte, we need a vector register for index, and all vector
4489 registers must be distinct. */
4490 if (t->opcode_modifier.vecsib)
4491 {
4492 if (!i.index_reg
6c30d220
L		 4493 || !((t->opcode_modifier.vecsib == VecSIB128
4494 && i.index_reg->reg_type.bitfield.regxmm)
4495 || (t->opcode_modifier.vecsib == VecSIB256
43234a1e
L		 4496 && i.index_reg->reg_type.bitfield.regymm)
4497 || (t->opcode_modifier.vecsib == VecSIB512
4498 && i.index_reg->reg_type.bitfield.regzmm)))
7bab8ab5
JB		 4499 {
4500 i.error = invalid_vsib_address;
4501 return 1;
4502 }
4503
43234a1e
L		 4504 gas_assert (i.reg_operands == 2 || i.mask);
4505 if (i.reg_operands == 2 && !i.mask)
4506 {
4507 gas_assert (i.types[0].bitfield.regxmm
7c84a0ca 4508 || i.types[0].bitfield.regymm);
43234a1e 4509 gas_assert (i.types[2].bitfield.regxmm
7c84a0ca 4510 || i.types[2].bitfield.regymm);
43234a1e
L		 4511 if (operand_check == check_none)
4512 return 0;
4513 if (register_number (i.op[0].regs)
4514 != register_number (i.index_reg)
4515 && register_number (i.op[2].regs)
4516 != register_number (i.index_reg)
4517 && register_number (i.op[0].regs)
4518 != register_number (i.op[2].regs))
4519 return 0;
4520 if (operand_check == check_error)
4521 {
4522 i.error = invalid_vector_register_set;
4523 return 1;
4524 }
4525 as_warn (_("mask, index, and destination registers should be distinct"));
4526 }
8444f82a
MZ		 4527 else if (i.reg_operands == 1 && i.mask)
4528 {
4529 if ((i.types[1].bitfield.regymm
4530 || i.types[1].bitfield.regzmm)
4531 && (register_number (i.op[1].regs)
4532 == register_number (i.index_reg)))
4533 {
4534 if (operand_check == check_error)
4535 {
4536 i.error = invalid_vector_register_set;
4537 return 1;
4538 }
4539 if (operand_check != check_none)
4540 as_warn (_("index and destination registers should be distinct"));
4541 }
4542 }
43234a1e 4543 }
7bab8ab5 4544
43234a1e
L		 4545 /* Check if broadcast is supported by the instruction and is applied
4546 to the memory operand. */
4547 if (i.broadcast)
4548 {
4549 int broadcasted_opnd_size;
4550
4551 /* Check if specified broadcast is supported in this instruction,
4552 and it's applied to memory operand of DWORD or QWORD type,
4553 depending on VecESize. */
4554 if (i.broadcast->type != t->opcode_modifier.broadcast
4555 || !i.types[i.broadcast->operand].bitfield.mem
4556 || (t->opcode_modifier.vecesize == 0
4557 && !i.types[i.broadcast->operand].bitfield.dword
4558 && !i.types[i.broadcast->operand].bitfield.unspecified)
4559 || (t->opcode_modifier.vecesize == 1
4560 && !i.types[i.broadcast->operand].bitfield.qword
4561 && !i.types[i.broadcast->operand].bitfield.unspecified))
4562 goto bad_broadcast;
4563
4564 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4565 if (i.broadcast->type == BROADCAST_1TO16)
4566 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4567 else if (i.broadcast->type == BROADCAST_1TO8)
4568 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
b28d1bda
IT		 4569 else if (i.broadcast->type == BROADCAST_1TO4)
4570 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4571 else if (i.broadcast->type == BROADCAST_1TO2)
4572 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
43234a1e
L		 4573 else
4574 goto bad_broadcast;
4575
4576 if ((broadcasted_opnd_size == 256
4577 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4578 || (broadcasted_opnd_size == 512
4579 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4580 {
4581 bad_broadcast:
4582 i.error = unsupported_broadcast;
4583 return 1;
4584 }
4585 }
4586 /* If broadcast is supported in this instruction, we need to check if
4587 operand of one-element size isn't specified without broadcast. */
4588 else if (t->opcode_modifier.broadcast && i.mem_operands)
4589 {
4590 /* Find memory operand. */
4591 for (op = 0; op < i.operands; op++)
4592 if (operand_type_check (i.types[op], anymem))
4593 break;
4594 gas_assert (op < i.operands);
4595 /* Check size of the memory operand. */
4596 if ((t->opcode_modifier.vecesize == 0
4597 && i.types[op].bitfield.dword)
4598 || (t->opcode_modifier.vecesize == 1
4599 && i.types[op].bitfield.qword))
4600 {
4601 i.error = broadcast_needed;
4602 return 1;
4603 }
4604 }
4605
4606 /* Check if requested masking is supported. */
4607 if (i.mask
4608 && (!t->opcode_modifier.masking
4609 || (i.mask->zeroing
4610 && t->opcode_modifier.masking == MERGING_MASKING)))
4611 {
4612 i.error = unsupported_masking;
4613 return 1;
4614 }
4615
4616 /* Check if masking is applied to dest operand. */
4617 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4618 {
4619 i.error = mask_not_on_destination;
4620 return 1;
4621 }
4622
43234a1e
L		 4623 /* Check RC/SAE. */
4624 if (i.rounding)
4625 {
4626 if ((i.rounding->type != saeonly
4627 && !t->opcode_modifier.staticrounding)
4628 || (i.rounding->type == saeonly
4629 && (t->opcode_modifier.staticrounding
4630 || !t->opcode_modifier.sae)))
4631 {
4632 i.error = unsupported_rc_sae;
4633 return 1;
4634 }
4635 /* If the instruction has several immediate operands and one of
4636 them is rounding, the rounding operand should be the last
4637 immediate operand. */
4638 if (i.imm_operands > 1
4639 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4640 {
43234a1e 4641 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4642 return 1;
4643 }
6c30d220
L		 4644 }
4645
43234a1e
L		 4646 /* Check vector Disp8 operand. */
4647 if (t->opcode_modifier.disp8memshift)
4648 {
4649 if (i.broadcast)
4650 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4651 else
4652 i.memshift = t->opcode_modifier.disp8memshift;
4653
4654 for (op = 0; op < i.operands; op++)
4655 if (operand_type_check (i.types[op], disp)
4656 && i.op[op].disps->X_op == O_constant)
4657 {
4658 offsetT value = i.op[op].disps->X_add_number;
5be33403
L		 4659 int vec_disp8_ok
4660 = (i.disp_encoding != disp_encoding_32bit
4661 && fits_in_vec_disp8 (value));
43234a1e
L		 4662 if (t->operand_types [op].bitfield.vec_disp8)
4663 {
4664 if (vec_disp8_ok)
4665 i.types[op].bitfield.vec_disp8 = 1;
4666 else
4667 {
4668 /* Vector insn can only have Vec_Disp8/Disp32 in
4669 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4670 mode. */
4671 i.types[op].bitfield.disp8 = 0;
4672 if (flag_code != CODE_16BIT)
4673 i.types[op].bitfield.disp16 = 0;
4674 }
4675 }
4676 else if (flag_code != CODE_16BIT)
4677 {
4678 /* One form of this instruction supports vector Disp8.
4679 Try vector Disp8 if we need to use Disp32. */
4680 if (vec_disp8_ok && !fits_in_signed_byte (value))
4681 {
4682 i.error = try_vector_disp8;
4683 return 1;
4684 }
4685 }
4686 }
4687 }
4688 else
4689 i.memshift = -1;
4690
6c30d220
L		 4691 return 0;
4692}
4693
43f3e2ee 4694/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4695 operand types. */
4696
4697static int
4698VEX_check_operands (const insn_template *t)
4699{
43234a1e
L		 4700 /* VREX is only valid with EVEX prefix. */
4701 if (i.need_vrex && !t->opcode_modifier.evex)
4702 {
4703 i.error = invalid_register_operand;
4704 return 1;
4705 }
4706
a683cc34
SP		 4707 if (!t->opcode_modifier.vex)
4708 return 0;
4709
4710 /* Only check VEX_Imm4, which must be the first operand. */
4711 if (t->operand_types[0].bitfield.vec_imm4)
4712 {
4713 if (i.op[0].imms->X_op != O_constant
4714 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4715 {
a65babc9 4716 i.error = bad_imm4;
891edac4
L		 4717 return 1;
4718 }
a683cc34
SP		 4719
4720 /* Turn off Imm8 so that update_imm won't complain. */
4721 i.types[0] = vec_imm4;
4722 }
4723
4724 return 0;
4725}
4726
d3ce72d0 4727static const insn_template *
83b16ac6 4728match_template (char mnem_suffix)
29b0f896
AM		 4729{
4730 /* Points to template once we've found it. */
d3ce72d0 4731 const insn_template *t;
40fb9820 4732 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4733 i386_operand_type overlap4;
29b0f896 4734 unsigned int found_reverse_match;
83b16ac6 4735 i386_opcode_modifier suffix_check, mnemsuf_check;
40fb9820 4736 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4737 int addr_prefix_disp;
a5c311ca 4738 unsigned int j;
3629bb00 4739 unsigned int found_cpu_match;
45664ddb 4740 unsigned int check_register;
5614d22c 4741 enum i386_error specific_error = 0;
29b0f896 4742
c0f3af97
L		 4743#if MAX_OPERANDS != 5
4744# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4745#endif
4746
29b0f896 4747 found_reverse_match = 0;
539e75ad 4748 addr_prefix_disp = -1;
40fb9820
L		 4749
4750 memset (&suffix_check, 0, sizeof (suffix_check));
4751 if (i.suffix == BYTE_MNEM_SUFFIX)
4752 suffix_check.no_bsuf = 1;
4753 else if (i.suffix == WORD_MNEM_SUFFIX)
4754 suffix_check.no_wsuf = 1;
4755 else if (i.suffix == SHORT_MNEM_SUFFIX)
4756 suffix_check.no_ssuf = 1;
4757 else if (i.suffix == LONG_MNEM_SUFFIX)
4758 suffix_check.no_lsuf = 1;
4759 else if (i.suffix == QWORD_MNEM_SUFFIX)
4760 suffix_check.no_qsuf = 1;
4761 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4762 suffix_check.no_ldsuf = 1;
29b0f896 4763
83b16ac6
JB		 4764 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
4765 if (intel_syntax)
4766 {
4767 switch (mnem_suffix)
4768 {
4769 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
4770 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
4771 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
4772 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
4773 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
4774 }
4775 }
4776
01559ecc
L		 4777 /* Must have right number of operands. */
4778 i.error = number_of_operands_mismatch;
4779
45aa61fe 4780 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4781 {
539e75ad
L		 4782 addr_prefix_disp = -1;
4783
29b0f896
AM		 4784 if (i.operands != t->operands)
4785 continue;
4786
50aecf8c 4787 /* Check processor support. */
a65babc9 4788 i.error = unsupported;
c0f3af97
L		 4789 found_cpu_match = (cpu_flags_match (t)
4790 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4791 if (!found_cpu_match)
4792 continue;
4793
e1d4d893 4794 /* Check old gcc support. */
a65babc9 4795 i.error = old_gcc_only;
e1d4d893
L		 4796 if (!old_gcc && t->opcode_modifier.oldgcc)
4797 continue;
4798
4799 /* Check AT&T mnemonic. */
a65babc9 4800 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4801 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4802 continue;
4803
e92bae62 4804 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
a65babc9 4805 i.error = unsupported_syntax;
5c07affc 4806 if ((intel_syntax && t->opcode_modifier.attsyntax)
e92bae62
L		 4807 || (!intel_syntax && t->opcode_modifier.intelsyntax)
4808 || (intel64 && t->opcode_modifier.amd64)
4809 || (!intel64 && t->opcode_modifier.intel64))
1efbbeb4
L		 4810 continue;
4811
20592a94 4812 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4813 i.error = invalid_instruction_suffix;
567e4e96
L		 4814 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4815 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4816 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4817 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4818 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4819 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4820 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896 4821 continue;
83b16ac6
JB		 4822 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
4823 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
4824 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
4825 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
4826 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
4827 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
4828 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
4829 continue;
29b0f896 4830
5c07affc 4831 if (!operand_size_match (t))
7d5e4556 4832 continue;
539e75ad 4833
5c07affc
L		 4834 for (j = 0; j < MAX_OPERANDS; j++)
4835 operand_types[j] = t->operand_types[j];
4836
45aa61fe
AM		 4837 /* In general, don't allow 64-bit operands in 32-bit mode. */
4838 if (i.suffix == QWORD_MNEM_SUFFIX
4839 && flag_code != CODE_64BIT
4840 && (intel_syntax
40fb9820 4841 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4842 && !intel_float_operand (t->name))
4843 : intel_float_operand (t->name) != 2)
40fb9820 4844 && ((!operand_types[0].bitfield.regmmx
c0f3af97 4845 && !operand_types[0].bitfield.regxmm
43234a1e
L		 4846 && !operand_types[0].bitfield.regymm
4847 && !operand_types[0].bitfield.regzmm)
40fb9820 4848 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736
AM		 4849 && operand_types[t->operands > 1].bitfield.regxmm
4850 && operand_types[t->operands > 1].bitfield.regymm
4851 && operand_types[t->operands > 1].bitfield.regzmm))
45aa61fe
AM		 4852 && (t->base_opcode != 0x0fc7
4853 || t->extension_opcode != 1 /* cmpxchg8b */))
4854 continue;
4855
192dc9c6
JB		 4856 /* In general, don't allow 32-bit operands on pre-386. */
4857 else if (i.suffix == LONG_MNEM_SUFFIX
4858 && !cpu_arch_flags.bitfield.cpui386
4859 && (intel_syntax
4860 ? (!t->opcode_modifier.ignoresize
4861 && !intel_float_operand (t->name))
4862 : intel_float_operand (t->name) != 2)
4863 && ((!operand_types[0].bitfield.regmmx
4864 && !operand_types[0].bitfield.regxmm)
4865 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736 4866 && operand_types[t->operands > 1].bitfield.regxmm)))
192dc9c6
JB		 4867 continue;
4868
29b0f896 4869 /* Do not verify operands when there are none. */
50aecf8c 4870 else
29b0f896 4871 {
c6fb90c8 4872 if (!t->operands)
2dbab7d5
L		 4873 /* We've found a match; break out of loop. */
4874 break;
29b0f896 4875 }
252b5132 4876
539e75ad
L		 4877 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4878 into Disp32/Disp16/Disp32 operand. */
4879 if (i.prefix[ADDR_PREFIX] != 0)
4880 {
40fb9820 4881 /* There should be only one Disp operand. */
539e75ad
L		 4882 switch (flag_code)
4883 {
4884 case CODE_16BIT:
40fb9820
L		 4885 for (j = 0; j < MAX_OPERANDS; j++)
4886 {
4887 if (operand_types[j].bitfield.disp16)
4888 {
4889 addr_prefix_disp = j;
4890 operand_types[j].bitfield.disp32 = 1;
4891 operand_types[j].bitfield.disp16 = 0;
4892 break;
4893 }
4894 }
539e75ad
L		 4895 break;
4896 case CODE_32BIT:
40fb9820
L		 4897 for (j = 0; j < MAX_OPERANDS; j++)
4898 {
4899 if (operand_types[j].bitfield.disp32)
4900 {
4901 addr_prefix_disp = j;
4902 operand_types[j].bitfield.disp32 = 0;
4903 operand_types[j].bitfield.disp16 = 1;
4904 break;
4905 }
4906 }
539e75ad
L		 4907 break;
4908 case CODE_64BIT:
40fb9820
L		 4909 for (j = 0; j < MAX_OPERANDS; j++)
4910 {
4911 if (operand_types[j].bitfield.disp64)
4912 {
4913 addr_prefix_disp = j;
4914 operand_types[j].bitfield.disp64 = 0;
4915 operand_types[j].bitfield.disp32 = 1;
4916 break;
4917 }
4918 }
539e75ad
L		 4919 break;
4920 }
539e75ad
L		 4921 }
4922
02a86693
L		 4923 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
4924 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
4925 continue;
4926
56ffb741
L		 4927 /* We check register size if needed. */
4928 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4929 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4930 switch (t->operands)
4931 {
4932 case 1:
40fb9820 4933 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4934 continue;
4935 break;
4936 case 2:
8b38ad71
L		 4937 /* xchg %eax, %eax is a special case. It is an aliase for nop
4938 only in 32bit mode and we can use opcode 0x90. In 64bit
4939 mode, we can't use 0x90 for xchg %eax, %eax since it should
4940 zero-extend %eax to %rax. */
4941 if (flag_code == CODE_64BIT
4942 && t->base_opcode == 0x90
0dfbf9d7
L		 4943 && operand_type_equal (&i.types [0], &acc32)
4944 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4945 continue;
b6169b20
L		 4946 if (i.swap_operand)
4947 {
4948 /* If we swap operand in encoding, we either match
4949 the next one or reverse direction of operands. */
4950 if (t->opcode_modifier.s)
4951 continue;
4952 else if (t->opcode_modifier.d)
4953 goto check_reverse;
4954 }
4955
29b0f896 4956 case 3:
fa99fab2
L		 4957 /* If we swap operand in encoding, we match the next one. */
4958 if (i.swap_operand && t->opcode_modifier.s)
4959 continue;
f48ff2ae 4960 case 4:
c0f3af97 4961 case 5:
c6fb90c8 4962 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4963 if (!operand_type_match (overlap0, i.types[0])
4964 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4965 || (check_register
4966 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4967 operand_types[0],
4968 overlap1, i.types[1],
4969 operand_types[1])))
29b0f896
AM		 4970 {
4971 /* Check if other direction is valid ... */
40fb9820 4972 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4973 continue;
4974
b6169b20 4975check_reverse:
29b0f896 4976 /* Try reversing direction of operands. */
c6fb90c8
L		 4977 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4978 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4979 if (!operand_type_match (overlap0, i.types[0])
4980 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4981 || (check_register
4982 && !operand_type_register_match (overlap0,
4983 i.types[0],
4984 operand_types[1],
4985 overlap1,
4986 i.types[1],
4987 operand_types[0])))
29b0f896
AM		 4988 {
4989 /* Does not match either direction. */
4990 continue;
4991 }
4992 /* found_reverse_match holds which of D or FloatDR
4993 we've found. */
40fb9820 4994 if (t->opcode_modifier.d)
8a2ed489 4995 found_reverse_match = Opcode_D;
40fb9820 4996 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4997 found_reverse_match = Opcode_FloatD;
4998 else
4999 found_reverse_match = 0;
40fb9820 5000 if (t->opcode_modifier.floatr)
8a2ed489 5001 found_reverse_match |= Opcode_FloatR;
29b0f896 5002 }
f48ff2ae 5003 else
29b0f896 5004 {
f48ff2ae 5005 /* Found a forward 2 operand match here. */
d1cbb4db
L		 5006 switch (t->operands)
5007 {
c0f3af97
L		 5008 case 5:
5009 overlap4 = operand_type_and (i.types[4],
5010 operand_types[4]);
d1cbb4db 5011 case 4:
c6fb90c8
L		 5012 overlap3 = operand_type_and (i.types[3],
5013 operand_types[3]);
d1cbb4db 5014 case 3:
c6fb90c8
L		 5015 overlap2 = operand_type_and (i.types[2],
5016 operand_types[2]);
d1cbb4db
L		 5017 break;
5018 }
29b0f896 5019
f48ff2ae
L		 5020 switch (t->operands)
5021 {
c0f3af97
L		 5022 case 5:
5023 if (!operand_type_match (overlap4, i.types[4])
5024 || !operand_type_register_match (overlap3,
5025 i.types[3],
5026 operand_types[3],
5027 overlap4,
5028 i.types[4],
5029 operand_types[4]))
5030 continue;
f48ff2ae 5031 case 4:
40fb9820 5032 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 5033 || (check_register
5034 && !operand_type_register_match (overlap2,
5035 i.types[2],
5036 operand_types[2],
5037 overlap3,
5038 i.types[3],
5039 operand_types[3])))
f48ff2ae
L		 5040 continue;
5041 case 3:
5042 /* Here we make use of the fact that there are no
5043 reverse match 3 operand instructions, and all 3
5044 operand instructions only need to be checked for
5045 register consistency between operands 2 and 3. */
40fb9820 5046 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 5047 || (check_register
5048 && !operand_type_register_match (overlap1,
5049 i.types[1],
5050 operand_types[1],
5051 overlap2,
5052 i.types[2],
5053 operand_types[2])))
f48ff2ae
L		 5054 continue;
5055 break;
5056 }
29b0f896 5057 }
f48ff2ae 5058 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 5059 slip through to break. */
5060 }
3629bb00 5061 if (!found_cpu_match)
29b0f896
AM		 5062 {
5063 found_reverse_match = 0;
5064 continue;
5065 }
c0f3af97 5066
5614d22c
JB		 5067 /* Check if vector and VEX operands are valid. */
5068 if (check_VecOperands (t) || VEX_check_operands (t))
5069 {
5070 specific_error = i.error;
5071 continue;
5072 }
a683cc34 5073
29b0f896
AM		 5074 /* We've found a match; break out of loop. */
5075 break;
5076 }
5077
5078 if (t == current_templates->end)
5079 {
5080 /* We found no match. */
a65babc9 5081 const char *err_msg;
5614d22c 5082 switch (specific_error ? specific_error : i.error)
a65babc9
L		 5083 {
5084 default:
5085 abort ();
86e026a4 5086 case operand_size_mismatch:
a65babc9
L		 5087 err_msg = _("operand size mismatch");
5088 break;
5089 case operand_type_mismatch:
5090 err_msg = _("operand type mismatch");
5091 break;
5092 case register_type_mismatch:
5093 err_msg = _("register type mismatch");
5094 break;
5095 case number_of_operands_mismatch:
5096 err_msg = _("number of operands mismatch");
5097 break;
5098 case invalid_instruction_suffix:
5099 err_msg = _("invalid instruction suffix");
5100 break;
5101 case bad_imm4:
4a2608e3 5102 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 5103 break;
5104 case old_gcc_only:
5105 err_msg = _("only supported with old gcc");
5106 break;
5107 case unsupported_with_intel_mnemonic:
5108 err_msg = _("unsupported with Intel mnemonic");
5109 break;
5110 case unsupported_syntax:
5111 err_msg = _("unsupported syntax");
5112 break;
5113 case unsupported:
35262a23 5114 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 5115 current_templates->start->name);
5116 return NULL;
6c30d220
L		 5117 case invalid_vsib_address:
5118 err_msg = _("invalid VSIB address");
5119 break;
7bab8ab5
JB		 5120 case invalid_vector_register_set:
5121 err_msg = _("mask, index, and destination registers must be distinct");
5122 break;
6c30d220
L		 5123 case unsupported_vector_index_register:
5124 err_msg = _("unsupported vector index register");
5125 break;
43234a1e
L		 5126 case unsupported_broadcast:
5127 err_msg = _("unsupported broadcast");
5128 break;
5129 case broadcast_not_on_src_operand:
5130 err_msg = _("broadcast not on source memory operand");
5131 break;
5132 case broadcast_needed:
5133 err_msg = _("broadcast is needed for operand of such type");
5134 break;
5135 case unsupported_masking:
5136 err_msg = _("unsupported masking");
5137 break;
5138 case mask_not_on_destination:
5139 err_msg = _("mask not on destination operand");
5140 break;
5141 case no_default_mask:
5142 err_msg = _("default mask isn't allowed");
5143 break;
5144 case unsupported_rc_sae:
5145 err_msg = _("unsupported static rounding/sae");
5146 break;
5147 case rc_sae_operand_not_last_imm:
5148 if (intel_syntax)
5149 err_msg = _("RC/SAE operand must precede immediate operands");
5150 else
5151 err_msg = _("RC/SAE operand must follow immediate operands");
5152 break;
5153 case invalid_register_operand:
5154 err_msg = _("invalid register operand");
5155 break;
a65babc9
L		 5156 }
5157 as_bad (_("%s for `%s'"), err_msg,
891edac4 5158 current_templates->start->name);
fa99fab2 5159 return NULL;
29b0f896 5160 }
252b5132 5161
29b0f896
AM		 5162 if (!quiet_warnings)
5163 {
5164 if (!intel_syntax
40fb9820
L		 5165 && (i.types[0].bitfield.jumpabsolute
5166 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5167 {
5168 as_warn (_("indirect %s without `*'"), t->name);
5169 }
5170
40fb9820
L		 5171 if (t->opcode_modifier.isprefix
5172 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5173 {
5174 /* Warn them that a data or address size prefix doesn't
5175 affect assembly of the next line of code. */
5176 as_warn (_("stand-alone `%s' prefix"), t->name);
5177 }
5178 }
5179
5180 /* Copy the template we found. */
5181 i.tm = *t;
539e75ad
L		 5182
5183 if (addr_prefix_disp != -1)
5184 i.tm.operand_types[addr_prefix_disp]
5185 = operand_types[addr_prefix_disp];
5186
29b0f896
AM		 5187 if (found_reverse_match)
5188 {
5189 /* If we found a reverse match we must alter the opcode
5190 direction bit. found_reverse_match holds bits to change
5191 (different for int & float insns). */
5192
5193 i.tm.base_opcode ^= found_reverse_match;
5194
539e75ad
L		 5195 i.tm.operand_types[0] = operand_types[1];
5196 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5197 }
5198
fa99fab2 5199 return t;
29b0f896
AM		 5200}
5201
5202static int
e3bb37b5 5203check_string (void)
29b0f896 5204{
40fb9820
L		 5205 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5206 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5207 {
5208 if (i.seg[0] != NULL && i.seg[0] != &es)
5209 {
a87af027 5210 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5211 i.tm.name,
a87af027
JB		 5212 mem_op + 1,
5213 register_prefix);
29b0f896
AM		 5214 return 0;
5215 }
5216 /* There's only ever one segment override allowed per instruction.
5217 This instruction possibly has a legal segment override on the
5218 second operand, so copy the segment to where non-string
5219 instructions store it, allowing common code. */
5220 i.seg[0] = i.seg[1];
5221 }
40fb9820 5222 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5223 {
5224 if (i.seg[1] != NULL && i.seg[1] != &es)
5225 {
a87af027 5226 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5227 i.tm.name,
a87af027
JB		 5228 mem_op + 2,
5229 register_prefix);
29b0f896
AM		 5230 return 0;
5231 }
5232 }
5233 return 1;
5234}
5235
5236static int
543613e9 5237process_suffix (void)
29b0f896
AM		 5238{
5239 /* If matched instruction specifies an explicit instruction mnemonic
5240 suffix, use it. */
40fb9820
L		 5241 if (i.tm.opcode_modifier.size16)
5242 i.suffix = WORD_MNEM_SUFFIX;
5243 else if (i.tm.opcode_modifier.size32)
5244 i.suffix = LONG_MNEM_SUFFIX;
5245 else if (i.tm.opcode_modifier.size64)
5246 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5247 else if (i.reg_operands)
5248 {
5249 /* If there's no instruction mnemonic suffix we try to invent one
5250 based on register operands. */
5251 if (!i.suffix)
5252 {
5253 /* We take i.suffix from the last register operand specified,
5254 Destination register type is more significant than source
381d071f
L		 5255 register type. crc32 in SSE4.2 prefers source register
5256 type. */
5257 if (i.tm.base_opcode == 0xf20f38f1)
5258 {
40fb9820
L		 5259 if (i.types[0].bitfield.reg16)
5260 i.suffix = WORD_MNEM_SUFFIX;
5261 else if (i.types[0].bitfield.reg32)
5262 i.suffix = LONG_MNEM_SUFFIX;
5263 else if (i.types[0].bitfield.reg64)
5264 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5265 }
9344ff29 5266 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5267 {
40fb9820 5268 if (i.types[0].bitfield.reg8)
20592a94
L		 5269 i.suffix = BYTE_MNEM_SUFFIX;
5270 }
381d071f
L		 5271
5272 if (!i.suffix)
5273 {
5274 int op;
5275
20592a94
L		 5276 if (i.tm.base_opcode == 0xf20f38f1
5277 || i.tm.base_opcode == 0xf20f38f0)
5278 {
5279 /* We have to know the operand size for crc32. */
5280 as_bad (_("ambiguous memory operand size for `%s`"),
5281 i.tm.name);
5282 return 0;
5283 }
5284
381d071f 5285 for (op = i.operands; --op >= 0;)
40fb9820 5286 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 5287 {
40fb9820
L		 5288 if (i.types[op].bitfield.reg8)
5289 {
5290 i.suffix = BYTE_MNEM_SUFFIX;
5291 break;
5292 }
5293 else if (i.types[op].bitfield.reg16)
5294 {
5295 i.suffix = WORD_MNEM_SUFFIX;
5296 break;
5297 }
5298 else if (i.types[op].bitfield.reg32)
5299 {
5300 i.suffix = LONG_MNEM_SUFFIX;
5301 break;
5302 }
5303 else if (i.types[op].bitfield.reg64)
5304 {
5305 i.suffix = QWORD_MNEM_SUFFIX;
5306 break;
5307 }
381d071f
L		 5308 }
5309 }
29b0f896
AM		 5310 }
5311 else if (i.suffix == BYTE_MNEM_SUFFIX)
5312 {
2eb952a4
L		 5313 if (intel_syntax
5314 && i.tm.opcode_modifier.ignoresize
5315 && i.tm.opcode_modifier.no_bsuf)
5316 i.suffix = 0;
5317 else if (!check_byte_reg ())
29b0f896
AM		 5318 return 0;
5319 }
5320 else if (i.suffix == LONG_MNEM_SUFFIX)
5321 {
2eb952a4
L		 5322 if (intel_syntax
5323 && i.tm.opcode_modifier.ignoresize
5324 && i.tm.opcode_modifier.no_lsuf)
5325 i.suffix = 0;
5326 else if (!check_long_reg ())
29b0f896
AM		 5327 return 0;
5328 }
5329 else if (i.suffix == QWORD_MNEM_SUFFIX)
5330 {
955e1e6a
L		 5331 if (intel_syntax
5332 && i.tm.opcode_modifier.ignoresize
5333 && i.tm.opcode_modifier.no_qsuf)
5334 i.suffix = 0;
5335 else if (!check_qword_reg ())
29b0f896
AM		 5336 return 0;
5337 }
5338 else if (i.suffix == WORD_MNEM_SUFFIX)
5339 {
2eb952a4
L		 5340 if (intel_syntax
5341 && i.tm.opcode_modifier.ignoresize
5342 && i.tm.opcode_modifier.no_wsuf)
5343 i.suffix = 0;
5344 else if (!check_word_reg ())
29b0f896
AM		 5345 return 0;
5346 }
c0f3af97 5347 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5348 || i.suffix == YMMWORD_MNEM_SUFFIX
5349 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5350 {
43234a1e 5351 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5352 should check if it is a valid suffix. */
5353 }
40fb9820 5354 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5355 /* Do nothing if the instruction is going to ignore the prefix. */
5356 ;
5357 else
5358 abort ();
5359 }
40fb9820 5360 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5361 && !i.suffix
5362 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5363 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5364 {
5365 i.suffix = stackop_size;
5366 }
9306ca4a
JB		 5367 else if (intel_syntax
5368 && !i.suffix
40fb9820
L		 5369 && (i.tm.operand_types[0].bitfield.jumpabsolute
5370 || i.tm.opcode_modifier.jumpbyte
5371 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5372 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5373 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5374 {
5375 switch (flag_code)
5376 {
5377 case CODE_64BIT:
40fb9820 5378 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5379 {
5380 i.suffix = QWORD_MNEM_SUFFIX;
5381 break;
5382 }
5383 case CODE_32BIT:
40fb9820 5384 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5385 i.suffix = LONG_MNEM_SUFFIX;
5386 break;
5387 case CODE_16BIT:
40fb9820 5388 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5389 i.suffix = WORD_MNEM_SUFFIX;
5390 break;
5391 }
5392 }
252b5132 5393
9306ca4a 5394 if (!i.suffix)
29b0f896 5395 {
9306ca4a
JB		 5396 if (!intel_syntax)
5397 {
40fb9820 5398 if (i.tm.opcode_modifier.w)
9306ca4a 5399 {
4eed87de
AM		 5400 as_bad (_("no instruction mnemonic suffix given and "
5401 "no register operands; can't size instruction"));
9306ca4a
JB		 5402 return 0;
5403 }
5404 }
5405 else
5406 {
40fb9820 5407 unsigned int suffixes;
7ab9ffdd 5408
40fb9820
L		 5409 suffixes = !i.tm.opcode_modifier.no_bsuf;
5410 if (!i.tm.opcode_modifier.no_wsuf)
5411 suffixes |= 1 << 1;
5412 if (!i.tm.opcode_modifier.no_lsuf)
5413 suffixes |= 1 << 2;
fc4adea1 5414 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5415 suffixes |= 1 << 3;
5416 if (!i.tm.opcode_modifier.no_ssuf)
5417 suffixes |= 1 << 4;
5418 if (!i.tm.opcode_modifier.no_qsuf)
5419 suffixes |= 1 << 5;
5420
5421 /* There are more than suffix matches. */
5422 if (i.tm.opcode_modifier.w
9306ca4a 5423 || ((suffixes & (suffixes - 1))
40fb9820
L		 5424 && !i.tm.opcode_modifier.defaultsize
5425 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5426 {
5427 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5428 return 0;
5429 }
5430 }
29b0f896 5431 }
252b5132 5432
9306ca4a
JB		 5433 /* Change the opcode based on the operand size given by i.suffix;
5434 We don't need to change things for byte insns. */
5435
582d5edd
L		 5436 if (i.suffix
5437 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5438 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5439 && i.suffix != YMMWORD_MNEM_SUFFIX
5440 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5441 {
5442 /* It's not a byte, select word/dword operation. */
40fb9820 5443 if (i.tm.opcode_modifier.w)
29b0f896 5444 {
40fb9820 5445 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5446 i.tm.base_opcode |= 8;
5447 else
5448 i.tm.base_opcode |= 1;
5449 }
0f3f3d8b 5450
29b0f896
AM		 5451 /* Now select between word & dword operations via the operand
5452 size prefix, except for instructions that will ignore this
5453 prefix anyway. */
ca61edf2 5454 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5455 {
ca61edf2
L		 5456 /* The address size override prefix changes the size of the
5457 first operand. */
40fb9820
L		 5458 if ((flag_code == CODE_32BIT
5459 && i.op->regs[0].reg_type.bitfield.reg16)
5460 || (flag_code != CODE_32BIT
5461 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 5462 if (!add_prefix (ADDR_PREFIX_OPCODE))
5463 return 0;
5464 }
5465 else if (i.suffix != QWORD_MNEM_SUFFIX
5466 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5467 && !i.tm.opcode_modifier.ignoresize
5468 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5469 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5470 || (flag_code == CODE_64BIT
40fb9820 5471 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5472 {
5473 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5474
40fb9820 5475 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5476 prefix = ADDR_PREFIX_OPCODE;
252b5132 5477
29b0f896
AM		 5478 if (!add_prefix (prefix))
5479 return 0;
24eab124 5480 }
252b5132 5481
29b0f896
AM		 5482 /* Set mode64 for an operand. */
5483 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5484 && flag_code == CODE_64BIT
40fb9820 5485 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5486 {
5487 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5488 need rex64. cmpxchg8b is also a special case. */
5489 if (! (i.operands == 2
5490 && i.tm.base_opcode == 0x90
5491 && i.tm.extension_opcode == None
0dfbf9d7
L		 5492 && operand_type_equal (&i.types [0], &acc64)
5493 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5494 && ! (i.operands == 1
5495 && i.tm.base_opcode == 0xfc7
5496 && i.tm.extension_opcode == 1
40fb9820
L		 5497 && !operand_type_check (i.types [0], reg)
5498 && operand_type_check (i.types [0], anymem)))
f6bee062 5499 i.rex |= REX_W;
46e883c5 5500 }
3e73aa7c 5501
29b0f896
AM		 5502 /* Size floating point instruction. */
5503 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5504 if (i.tm.opcode_modifier.floatmf)
543613e9 5505 i.tm.base_opcode ^= 4;
29b0f896 5506 }
7ecd2f8b 5507
29b0f896
AM		 5508 return 1;
5509}
3e73aa7c 5510
29b0f896 5511static int
543613e9 5512check_byte_reg (void)
29b0f896
AM		 5513{
5514 int op;
543613e9 5515
29b0f896
AM		 5516 for (op = i.operands; --op >= 0;)
5517 {
5518 /* If this is an eight bit register, it's OK. If it's the 16 or
5519 32 bit version of an eight bit register, we will just use the
5520 low portion, and that's OK too. */
40fb9820 5521 if (i.types[op].bitfield.reg8)
29b0f896
AM		 5522 continue;
5523
5a819eb9
JB		 5524 /* I/O port address operands are OK too. */
5525 if (i.tm.operand_types[op].bitfield.inoutportreg)
5526 continue;
5527
9344ff29
L		 5528 /* crc32 doesn't generate this warning. */
5529 if (i.tm.base_opcode == 0xf20f38f0)
5530 continue;
5531
40fb9820
L		 5532 if ((i.types[op].bitfield.reg16
5533 || i.types[op].bitfield.reg32
5534 || i.types[op].bitfield.reg64)
5a819eb9
JB		 5535 && i.op[op].regs->reg_num < 4
5536 /* Prohibit these changes in 64bit mode, since the lowering
5537 would be more complicated. */
5538 && flag_code != CODE_64BIT)
29b0f896 5539 {
29b0f896 5540#if REGISTER_WARNINGS
5a819eb9 5541 if (!quiet_warnings)
a540244d
L		 5542 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5543 register_prefix,
40fb9820 5544 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 5545 ? REGNAM_AL - REGNAM_AX
5546 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5547 register_prefix,
29b0f896
AM		 5548 i.op[op].regs->reg_name,
5549 i.suffix);
5550#endif
5551 continue;
5552 }
5553 /* Any other register is bad. */
40fb9820
L		 5554 if (i.types[op].bitfield.reg16
5555 || i.types[op].bitfield.reg32
5556 || i.types[op].bitfield.reg64
5557 || i.types[op].bitfield.regmmx
5558 || i.types[op].bitfield.regxmm
c0f3af97 5559 || i.types[op].bitfield.regymm
43234a1e 5560 || i.types[op].bitfield.regzmm
40fb9820
L		 5561 || i.types[op].bitfield.sreg2
5562 || i.types[op].bitfield.sreg3
5563 || i.types[op].bitfield.control
5564 || i.types[op].bitfield.debug
5565 || i.types[op].bitfield.test
5566 || i.types[op].bitfield.floatreg
5567 || i.types[op].bitfield.floatacc)
29b0f896 5568 {
a540244d
L		 5569 as_bad (_("`%s%s' not allowed with `%s%c'"),
5570 register_prefix,
29b0f896
AM		 5571 i.op[op].regs->reg_name,
5572 i.tm.name,
5573 i.suffix);
5574 return 0;
5575 }
5576 }
5577 return 1;
5578}
5579
5580static int
e3bb37b5 5581check_long_reg (void)
29b0f896
AM		 5582{
5583 int op;
5584
5585 for (op = i.operands; --op >= 0;)
5586 /* Reject eight bit registers, except where the template requires
5587 them. (eg. movzb) */
40fb9820
L		 5588 if (i.types[op].bitfield.reg8
5589 && (i.tm.operand_types[op].bitfield.reg16
5590 || i.tm.operand_types[op].bitfield.reg32
5591 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5592 {
a540244d
L		 5593 as_bad (_("`%s%s' not allowed with `%s%c'"),
5594 register_prefix,
29b0f896
AM		 5595 i.op[op].regs->reg_name,
5596 i.tm.name,
5597 i.suffix);
5598 return 0;
5599 }
e4630f71 5600 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5601 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5602 && i.types[op].bitfield.reg16
5603 && (i.tm.operand_types[op].bitfield.reg32
5604 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5605 {
5606 /* Prohibit these changes in the 64bit mode, since the
5607 lowering is more complicated. */
5608 if (flag_code == CODE_64BIT)
252b5132 5609 {
2b5d6a91 5610 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5611 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5612 i.suffix);
5613 return 0;
252b5132 5614 }
29b0f896 5615#if REGISTER_WARNINGS
cecf1424
JB		 5616 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5617 register_prefix,
5618 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5619 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5620#endif
252b5132 5621 }
e4630f71 5622 /* Warn if the r prefix on a general reg is present. */
40fb9820
L		 5623 else if (i.types[op].bitfield.reg64
5624 && (i.tm.operand_types[op].bitfield.reg32
5625 || i.tm.operand_types[op].bitfield.acc))
252b5132 5626 {
34828aad 5627 if (intel_syntax
ca61edf2 5628 && i.tm.opcode_modifier.toqword
40fb9820 5629 && !i.types[0].bitfield.regxmm)
34828aad 5630 {
ca61edf2 5631 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5632 i.suffix = QWORD_MNEM_SUFFIX;
5633 }
5634 else
5635 {
2b5d6a91 5636 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5637 register_prefix, i.op[op].regs->reg_name,
5638 i.suffix);
5639 return 0;
5640 }
29b0f896
AM		 5641 }
5642 return 1;
5643}
252b5132 5644
29b0f896 5645static int
e3bb37b5 5646check_qword_reg (void)
29b0f896
AM		 5647{
5648 int op;
252b5132 5649
29b0f896
AM		 5650 for (op = i.operands; --op >= 0; )
5651 /* Reject eight bit registers, except where the template requires
5652 them. (eg. movzb) */
40fb9820
L		 5653 if (i.types[op].bitfield.reg8
5654 && (i.tm.operand_types[op].bitfield.reg16
5655 || i.tm.operand_types[op].bitfield.reg32
5656 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5657 {
a540244d
L		 5658 as_bad (_("`%s%s' not allowed with `%s%c'"),
5659 register_prefix,
29b0f896
AM		 5660 i.op[op].regs->reg_name,
5661 i.tm.name,
5662 i.suffix);
5663 return 0;
5664 }
e4630f71 5665 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 5666 else if ((i.types[op].bitfield.reg16
5667 || i.types[op].bitfield.reg32)
5668 && (i.tm.operand_types[op].bitfield.reg32
5669 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5670 {
5671 /* Prohibit these changes in the 64bit mode, since the
5672 lowering is more complicated. */
34828aad 5673 if (intel_syntax
ca61edf2 5674 && i.tm.opcode_modifier.todword
40fb9820 5675 && !i.types[0].bitfield.regxmm)
34828aad 5676 {
ca61edf2 5677 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5678 i.suffix = LONG_MNEM_SUFFIX;
5679 }
5680 else
5681 {
2b5d6a91 5682 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5683 register_prefix, i.op[op].regs->reg_name,
5684 i.suffix);
5685 return 0;
5686 }
252b5132 5687 }
29b0f896
AM		 5688 return 1;
5689}
252b5132 5690
29b0f896 5691static int
e3bb37b5 5692check_word_reg (void)
29b0f896
AM		 5693{
5694 int op;
5695 for (op = i.operands; --op >= 0;)
5696 /* Reject eight bit registers, except where the template requires
5697 them. (eg. movzb) */
40fb9820
L		 5698 if (i.types[op].bitfield.reg8
5699 && (i.tm.operand_types[op].bitfield.reg16
5700 || i.tm.operand_types[op].bitfield.reg32
5701 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5702 {
a540244d
L		 5703 as_bad (_("`%s%s' not allowed with `%s%c'"),
5704 register_prefix,
29b0f896
AM		 5705 i.op[op].regs->reg_name,
5706 i.tm.name,
5707 i.suffix);
5708 return 0;
5709 }
e4630f71 5710 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5711 else if ((!quiet_warnings || flag_code == CODE_64BIT)
e4630f71
JB		 5712 && (i.types[op].bitfield.reg32
5713 || i.types[op].bitfield.reg64)
40fb9820
L		 5714 && (i.tm.operand_types[op].bitfield.reg16
5715 || i.tm.operand_types[op].bitfield.acc))
252b5132 5716 {
29b0f896
AM		 5717 /* Prohibit these changes in the 64bit mode, since the
5718 lowering is more complicated. */
5719 if (flag_code == CODE_64BIT)
252b5132 5720 {
2b5d6a91 5721 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5722 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5723 i.suffix);
5724 return 0;
252b5132 5725 }
29b0f896 5726#if REGISTER_WARNINGS
cecf1424
JB		 5727 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5728 register_prefix,
5729 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5730 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5731#endif
5732 }
5733 return 1;
5734}
252b5132 5735
29b0f896 5736static int
40fb9820 5737update_imm (unsigned int j)
29b0f896 5738{
bc0844ae 5739 i386_operand_type overlap = i.types[j];
40fb9820
L		 5740 if ((overlap.bitfield.imm8
5741 || overlap.bitfield.imm8s
5742 || overlap.bitfield.imm16
5743 || overlap.bitfield.imm32
5744 || overlap.bitfield.imm32s
5745 || overlap.bitfield.imm64)
0dfbf9d7
L		 5746 && !operand_type_equal (&overlap, &imm8)
5747 && !operand_type_equal (&overlap, &imm8s)
5748 && !operand_type_equal (&overlap, &imm16)
5749 && !operand_type_equal (&overlap, &imm32)
5750 && !operand_type_equal (&overlap, &imm32s)
5751 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5752 {
5753 if (i.suffix)
5754 {
40fb9820
L		 5755 i386_operand_type temp;
5756
0dfbf9d7 5757 operand_type_set (&temp, 0);
7ab9ffdd 5758 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5759 {
5760 temp.bitfield.imm8 = overlap.bitfield.imm8;
5761 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5762 }
5763 else if (i.suffix == WORD_MNEM_SUFFIX)
5764 temp.bitfield.imm16 = overlap.bitfield.imm16;
5765 else if (i.suffix == QWORD_MNEM_SUFFIX)
5766 {
5767 temp.bitfield.imm64 = overlap.bitfield.imm64;
5768 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5769 }
5770 else
5771 temp.bitfield.imm32 = overlap.bitfield.imm32;
5772 overlap = temp;
29b0f896 5773 }
0dfbf9d7
L		 5774 else if (operand_type_equal (&overlap, &imm16_32_32s)
5775 || operand_type_equal (&overlap, &imm16_32)
5776 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5777 {
40fb9820 5778 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5779 overlap = imm16;
40fb9820 5780 else
65da13b5 5781 overlap = imm32s;
29b0f896 5782 }
0dfbf9d7
L		 5783 if (!operand_type_equal (&overlap, &imm8)
5784 && !operand_type_equal (&overlap, &imm8s)
5785 && !operand_type_equal (&overlap, &imm16)
5786 && !operand_type_equal (&overlap, &imm32)
5787 && !operand_type_equal (&overlap, &imm32s)
5788 && !operand_type_equal (&overlap, &imm64))
29b0f896 5789 {
4eed87de
AM		 5790 as_bad (_("no instruction mnemonic suffix given; "
5791 "can't determine immediate size"));
29b0f896
AM		 5792 return 0;
5793 }
5794 }
40fb9820 5795 i.types[j] = overlap;
29b0f896 5796
40fb9820
L		 5797 return 1;
5798}
5799
5800static int
5801finalize_imm (void)
5802{
bc0844ae 5803 unsigned int j, n;
29b0f896 5804
bc0844ae
L		 5805 /* Update the first 2 immediate operands. */
5806 n = i.operands > 2 ? 2 : i.operands;
5807 if (n)
5808 {
5809 for (j = 0; j < n; j++)
5810 if (update_imm (j) == 0)
5811 return 0;
40fb9820 5812
bc0844ae
L		 5813 /* The 3rd operand can't be immediate operand. */
5814 gas_assert (operand_type_check (i.types[2], imm) == 0);
5815 }
29b0f896
AM		 5816
5817 return 1;
5818}
5819
c0f3af97
L		 5820static int
5821bad_implicit_operand (int xmm)
5822{
91d6fa6a
NC		 5823 const char *ireg = xmm ? "xmm0" : "ymm0";
5824
c0f3af97
L		 5825 if (intel_syntax)
5826 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5827 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5828 else
5829 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5830 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5831 return 0;
5832}
5833
29b0f896 5834static int
e3bb37b5 5835process_operands (void)
29b0f896
AM		 5836{
5837 /* Default segment register this instruction will use for memory
5838 accesses. 0 means unknown. This is only for optimizing out
5839 unnecessary segment overrides. */
5840 const seg_entry *default_seg = 0;
5841
2426c15f 5842 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5843 {
91d6fa6a
NC		 5844 unsigned int dupl = i.operands;
5845 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5846 unsigned int j;
5847
c0f3af97 5848 /* The destination must be an xmm register. */
9c2799c2 5849 gas_assert (i.reg_operands
91d6fa6a 5850 && MAX_OPERANDS > dupl
7ab9ffdd 5851 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5852
5853 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5854 {
c0f3af97 5855 /* The first operand is implicit and must be xmm0. */
9c2799c2 5856 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5857 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5858 return bad_implicit_operand (1);
5859
8cd7925b 5860 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5861 {
5862 /* Keep xmm0 for instructions with VEX prefix and 3
5863 sources. */
5864 goto duplicate;
5865 }
e2ec9d29 5866 else
c0f3af97
L		 5867 {
5868 /* We remove the first xmm0 and keep the number of
5869 operands unchanged, which in fact duplicates the
5870 destination. */
5871 for (j = 1; j < i.operands; j++)
5872 {
5873 i.op[j - 1] = i.op[j];
5874 i.types[j - 1] = i.types[j];
5875 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5876 }
5877 }
5878 }
5879 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5880 {
91d6fa6a 5881 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5882 && (i.tm.opcode_modifier.vexsources
5883 == VEX3SOURCES));
c0f3af97
L		 5884
5885 /* Add the implicit xmm0 for instructions with VEX prefix
5886 and 3 sources. */
5887 for (j = i.operands; j > 0; j--)
5888 {
5889 i.op[j] = i.op[j - 1];
5890 i.types[j] = i.types[j - 1];
5891 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5892 }
5893 i.op[0].regs
5894 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5895 i.types[0] = regxmm;
c0f3af97
L		 5896 i.tm.operand_types[0] = regxmm;
5897
5898 i.operands += 2;
5899 i.reg_operands += 2;
5900 i.tm.operands += 2;
5901
91d6fa6a 5902 dupl++;
c0f3af97 5903 dest++;
91d6fa6a
NC		 5904 i.op[dupl] = i.op[dest];
5905 i.types[dupl] = i.types[dest];
5906 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5907 }
c0f3af97
L		 5908 else
5909 {
5910duplicate:
5911 i.operands++;
5912 i.reg_operands++;
5913 i.tm.operands++;
5914
91d6fa6a
NC		 5915 i.op[dupl] = i.op[dest];
5916 i.types[dupl] = i.types[dest];
5917 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5918 }
5919
5920 if (i.tm.opcode_modifier.immext)
5921 process_immext ();
5922 }
5923 else if (i.tm.opcode_modifier.firstxmm0)
5924 {
5925 unsigned int j;
5926
43234a1e 5927 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
9c2799c2 5928 gas_assert (i.reg_operands
7ab9ffdd 5929 && (operand_type_equal (&i.types[0], &regxmm)
43234a1e
L		 5930 || operand_type_equal (&i.types[0], &regymm)
5931 || operand_type_equal (&i.types[0], &regzmm)));
4c692bc7 5932 if (register_number (i.op[0].regs) != 0)
c0f3af97 5933 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5934
5935 for (j = 1; j < i.operands; j++)
5936 {
5937 i.op[j - 1] = i.op[j];
5938 i.types[j - 1] = i.types[j];
5939
5940 /* We need to adjust fields in i.tm since they are used by
5941 build_modrm_byte. */
5942 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5943 }
5944
e2ec9d29
L		 5945 i.operands--;
5946 i.reg_operands--;
e2ec9d29
L		 5947 i.tm.operands--;
5948 }
5949 else if (i.tm.opcode_modifier.regkludge)
5950 {
5951 /* The imul $imm, %reg instruction is converted into
5952 imul $imm, %reg, %reg, and the clr %reg instruction
5953 is converted into xor %reg, %reg. */
5954
5955 unsigned int first_reg_op;
5956
5957 if (operand_type_check (i.types[0], reg))
5958 first_reg_op = 0;
5959 else
5960 first_reg_op = 1;
5961 /* Pretend we saw the extra register operand. */
9c2799c2 5962 gas_assert (i.reg_operands == 1
7ab9ffdd 5963 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5964 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5965 i.types[first_reg_op + 1] = i.types[first_reg_op];
5966 i.operands++;
5967 i.reg_operands++;
29b0f896
AM		 5968 }
5969
40fb9820 5970 if (i.tm.opcode_modifier.shortform)
29b0f896 5971 {
40fb9820
L		 5972 if (i.types[0].bitfield.sreg2
5973 || i.types[0].bitfield.sreg3)
29b0f896 5974 {
4eed87de
AM		 5975 if (i.tm.base_opcode == POP_SEG_SHORT
5976 && i.op[0].regs->reg_num == 1)
29b0f896 5977 {
a87af027 5978 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5979 return 0;
29b0f896 5980 }
4eed87de
AM		 5981 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5982 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5983 i.rex |= REX_B;
4eed87de
AM		 5984 }
5985 else
5986 {
7ab9ffdd 5987 /* The register or float register operand is in operand
85f10a01 5988 0 or 1. */
40fb9820 5989 unsigned int op;
7ab9ffdd
L		 5990
5991 if (i.types[0].bitfield.floatreg
5992 || operand_type_check (i.types[0], reg))
5993 op = 0;
5994 else
5995 op = 1;
4eed87de
AM		 5996 /* Register goes in low 3 bits of opcode. */
5997 i.tm.base_opcode |= i.op[op].regs->reg_num;
5998 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5999 i.rex |= REX_B;
40fb9820 6000 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 6001 {
4eed87de
AM		 6002 /* Warn about some common errors, but press on regardless.
6003 The first case can be generated by gcc (<= 2.8.1). */
6004 if (i.operands == 2)
6005 {
6006 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 6007 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 6008 register_prefix, i.op[!intel_syntax].regs->reg_name,
6009 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 6010 }
6011 else
6012 {
6013 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 6014 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6015 register_prefix, i.op[0].regs->reg_name);
4eed87de 6016 }
29b0f896
AM		 6017 }
6018 }
6019 }
40fb9820 6020 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 6021 {
6022 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 6023 must be put into the modrm byte). Now, we make the modrm and
6024 index base bytes based on all the info we've collected. */
29b0f896
AM		 6025
6026 default_seg = build_modrm_byte ();
6027 }
8a2ed489 6028 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 6029 {
6030 default_seg = &ds;
6031 }
40fb9820 6032 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 6033 {
6034 /* For the string instructions that allow a segment override
6035 on one of their operands, the default segment is ds. */
6036 default_seg = &ds;
6037 }
6038
75178d9d
L		 6039 if (i.tm.base_opcode == 0x8d /* lea */
6040 && i.seg[0]
6041 && !quiet_warnings)
30123838 6042 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 6043
6044 /* If a segment was explicitly specified, and the specified segment
6045 is not the default, use an opcode prefix to select it. If we
6046 never figured out what the default segment is, then default_seg
6047 will be zero at this point, and the specified segment prefix will
6048 always be used. */
29b0f896
AM		 6049 if ((i.seg[0]) && (i.seg[0] != default_seg))
6050 {
6051 if (!add_prefix (i.seg[0]->seg_prefix))
6052 return 0;
6053 }
6054 return 1;
6055}
6056
6057static const seg_entry *
e3bb37b5 6058build_modrm_byte (void)
29b0f896
AM		 6059{
6060 const seg_entry *default_seg = 0;
c0f3af97 6061 unsigned int source, dest;
8cd7925b 6062 int vex_3_sources;
c0f3af97
L		 6063
6064 /* The first operand of instructions with VEX prefix and 3 sources
6065 must be VEX_Imm4. */
8cd7925b 6066 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 6067 if (vex_3_sources)
6068 {
91d6fa6a 6069 unsigned int nds, reg_slot;
4c2c6516 6070 expressionS *exp;
c0f3af97 6071
922d8de8 6072 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 6073 && i.tm.opcode_modifier.immext)
6074 {
6075 dest = i.operands - 2;
6076 gas_assert (dest == 3);
6077 }
922d8de8 6078 else
a683cc34 6079 dest = i.operands - 1;
c0f3af97 6080 nds = dest - 1;
922d8de8 6081
a683cc34
SP		 6082 /* There are 2 kinds of instructions:
6083 1. 5 operands: 4 register operands or 3 register operands
6084 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 6085 VexW0 or VexW1. The destination must be either XMM, YMM or
6086 ZMM register.
a683cc34
SP		 6087 2. 4 operands: 4 register operands or 3 register operands
6088 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 6089 gas_assert ((i.reg_operands == 4
a683cc34
SP		 6090 || (i.reg_operands == 3 && i.mem_operands == 1))
6091 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6092 && (i.tm.opcode_modifier.veximmext
6093 || (i.imm_operands == 1
6094 && i.types[0].bitfield.vec_imm4
6095 && (i.tm.opcode_modifier.vexw == VEXW0
6096 || i.tm.opcode_modifier.vexw == VEXW1)
6097 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 6098 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
6099 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 6100
6101 if (i.imm_operands == 0)
6102 {
6103 /* When there is no immediate operand, generate an 8bit
6104 immediate operand to encode the first operand. */
6105 exp = &im_expressions[i.imm_operands++];
6106 i.op[i.operands].imms = exp;
6107 i.types[i.operands] = imm8;
6108 i.operands++;
6109 /* If VexW1 is set, the first operand is the source and
6110 the second operand is encoded in the immediate operand. */
6111 if (i.tm.opcode_modifier.vexw == VEXW1)
6112 {
6113 source = 0;
6114 reg_slot = 1;
6115 }
6116 else
6117 {
6118 source = 1;
6119 reg_slot = 0;
6120 }
6121
6122 /* FMA swaps REG and NDS. */
6123 if (i.tm.cpu_flags.bitfield.cpufma)
6124 {
6125 unsigned int tmp;
6126 tmp = reg_slot;
6127 reg_slot = nds;
6128 nds = tmp;
6129 }
6130
24981e7b
L		 6131 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6132 &regxmm)
a683cc34 6133 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6134 &regymm)
6135 || operand_type_equal (&i.tm.operand_types[reg_slot],
6136 &regzmm));
a683cc34 6137 exp->X_op = O_constant;
4c692bc7 6138 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6139 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6140 }
922d8de8 6141 else
a683cc34
SP		 6142 {
6143 unsigned int imm_slot;
6144
6145 if (i.tm.opcode_modifier.vexw == VEXW0)
6146 {
6147 /* If VexW0 is set, the third operand is the source and
6148 the second operand is encoded in the immediate
6149 operand. */
6150 source = 2;
6151 reg_slot = 1;
6152 }
6153 else
6154 {
6155 /* VexW1 is set, the second operand is the source and
6156 the third operand is encoded in the immediate
6157 operand. */
6158 source = 1;
6159 reg_slot = 2;
6160 }
6161
6162 if (i.tm.opcode_modifier.immext)
6163 {
6164 /* When ImmExt is set, the immdiate byte is the last
6165 operand. */
6166 imm_slot = i.operands - 1;
6167 source--;
6168 reg_slot--;
6169 }
6170 else
6171 {
6172 imm_slot = 0;
6173
6174 /* Turn on Imm8 so that output_imm will generate it. */
6175 i.types[imm_slot].bitfield.imm8 = 1;
6176 }
6177
24981e7b
L		 6178 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6179 &regxmm)
6180 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6181 &regymm)
6182 || operand_type_equal (&i.tm.operand_types[reg_slot],
6183 &regzmm));
a683cc34 6184 i.op[imm_slot].imms->X_add_number
4c692bc7 6185 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6186 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6187 }
6188
6189 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6190 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 6191 &regymm)
6192 || operand_type_equal (&i.tm.operand_types[nds],
6193 &regzmm));
dae39acc 6194 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6195 }
6196 else
6197 source = dest = 0;
29b0f896
AM		 6198
6199 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6200 implicit registers do not count. If there are 3 register
6201 operands, it must be a instruction with VexNDS. For a
6202 instruction with VexNDD, the destination register is encoded
6203 in VEX prefix. If there are 4 register operands, it must be
6204 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6205 if (i.mem_operands == 0
6206 && ((i.reg_operands == 2
2426c15f 6207 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6208 || (i.reg_operands == 3
2426c15f 6209 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6210 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6211 {
cab737b9
L		 6212 switch (i.operands)
6213 {
6214 case 2:
6215 source = 0;
6216 break;
6217 case 3:
c81128dc
L		 6218 /* When there are 3 operands, one of them may be immediate,
6219 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6220 the first operand must be shift count register (cl) or it
6221 is an instruction with VexNDS. */
9c2799c2 6222 gas_assert (i.imm_operands == 1
7ab9ffdd 6223 || (i.imm_operands == 0
2426c15f 6224 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6225 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6226 if (operand_type_check (i.types[0], imm)
6227 || i.types[0].bitfield.shiftcount)
6228 source = 1;
6229 else
6230 source = 0;
cab737b9
L		 6231 break;
6232 case 4:
368d64cc
L		 6233 /* When there are 4 operands, the first two must be 8bit
6234 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6235 one.
6236
6237 For instructions with VexNDS, if the first operand
6238 an imm8, the source operand is the 2nd one. If the last
6239 operand is imm8, the source operand is the first one. */
9c2799c2 6240 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6241 && i.types[0].bitfield.imm8
6242 && i.types[1].bitfield.imm8)
2426c15f 6243 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6244 && i.imm_operands == 1
6245 && (i.types[0].bitfield.imm8
43234a1e
L		 6246 || i.types[i.operands - 1].bitfield.imm8
6247 || i.rounding)));
9f2670f2
L		 6248 if (i.imm_operands == 2)
6249 source = 2;
6250 else
c0f3af97
L		 6251 {
6252 if (i.types[0].bitfield.imm8)
6253 source = 1;
6254 else
6255 source = 0;
6256 }
c0f3af97
L		 6257 break;
6258 case 5:
43234a1e
L		 6259 if (i.tm.opcode_modifier.evex)
6260 {
6261 /* For EVEX instructions, when there are 5 operands, the
6262 first one must be immediate operand. If the second one
6263 is immediate operand, the source operand is the 3th
6264 one. If the last one is immediate operand, the source
6265 operand is the 2nd one. */
6266 gas_assert (i.imm_operands == 2
6267 && i.tm.opcode_modifier.sae
6268 && operand_type_check (i.types[0], imm));
6269 if (operand_type_check (i.types[1], imm))
6270 source = 2;
6271 else if (operand_type_check (i.types[4], imm))
6272 source = 1;
6273 else
6274 abort ();
6275 }
cab737b9
L		 6276 break;
6277 default:
6278 abort ();
6279 }
6280
c0f3af97
L		 6281 if (!vex_3_sources)
6282 {
6283 dest = source + 1;
6284
43234a1e
L		 6285 /* RC/SAE operand could be between DEST and SRC. That happens
6286 when one operand is GPR and the other one is XMM/YMM/ZMM
6287 register. */
6288 if (i.rounding && i.rounding->operand == (int) dest)
6289 dest++;
6290
2426c15f 6291 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6292 {
43234a1e
L		 6293 /* For instructions with VexNDS, the register-only source
6294 operand must be 32/64bit integer, XMM, YMM or ZMM
6295 register. It is encoded in VEX prefix. We need to
6296 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6297
6298 i386_operand_type op;
6299 unsigned int vvvv;
6300
6301 /* Check register-only source operand when two source
6302 operands are swapped. */
6303 if (!i.tm.operand_types[source].bitfield.baseindex
6304 && i.tm.operand_types[dest].bitfield.baseindex)
6305 {
6306 vvvv = source;
6307 source = dest;
6308 }
6309 else
6310 vvvv = dest;
6311
6312 op = i.tm.operand_types[vvvv];
fa99fab2 6313 op.bitfield.regmem = 0;
c0f3af97 6314 if ((dest + 1) >= i.operands
ac4eb736
AM		 6315 || (!op.bitfield.reg32
6316 && op.bitfield.reg64
f12dc422 6317 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6318 && !operand_type_equal (&op, &regymm)
6319 && !operand_type_equal (&op, &regzmm)
6320 && !operand_type_equal (&op, &regmask)))
c0f3af97 6321 abort ();
f12dc422 6322 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6323 dest++;
6324 }
6325 }
29b0f896
AM		 6326
6327 i.rm.mode = 3;
6328 /* One of the register operands will be encoded in the i.tm.reg
6329 field, the other in the combined i.tm.mode and i.tm.regmem
6330 fields. If no form of this instruction supports a memory
6331 destination operand, then we assume the source operand may
6332 sometimes be a memory operand and so we need to store the
6333 destination in the i.rm.reg field. */
40fb9820
L		 6334 if (!i.tm.operand_types[dest].bitfield.regmem
6335 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6336 {
6337 i.rm.reg = i.op[dest].regs->reg_num;
6338 i.rm.regmem = i.op[source].regs->reg_num;
6339 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6340 i.rex |= REX_R;
43234a1e
L		 6341 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6342 i.vrex |= REX_R;
29b0f896 6343 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6344 i.rex |= REX_B;
43234a1e
L		 6345 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6346 i.vrex |= REX_B;
29b0f896
AM		 6347 }
6348 else
6349 {
6350 i.rm.reg = i.op[source].regs->reg_num;
6351 i.rm.regmem = i.op[dest].regs->reg_num;
6352 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6353 i.rex |= REX_B;
43234a1e
L		 6354 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6355 i.vrex |= REX_B;
29b0f896 6356 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6357 i.rex |= REX_R;
43234a1e
L		 6358 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6359 i.vrex |= REX_R;
29b0f896 6360 }
161a04f6 6361 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6362 {
40fb9820
L		 6363 if (!i.types[0].bitfield.control
6364 && !i.types[1].bitfield.control)
c4a530c5 6365 abort ();
161a04f6 6366 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6367 add_prefix (LOCK_PREFIX_OPCODE);
6368 }
29b0f896
AM		 6369 }
6370 else
6371 { /* If it's not 2 reg operands... */
c0f3af97
L		 6372 unsigned int mem;
6373
29b0f896
AM		 6374 if (i.mem_operands)
6375 {
6376 unsigned int fake_zero_displacement = 0;
99018f42 6377 unsigned int op;
4eed87de 6378
7ab9ffdd
L		 6379 for (op = 0; op < i.operands; op++)
6380 if (operand_type_check (i.types[op], anymem))
6381 break;
7ab9ffdd 6382 gas_assert (op < i.operands);
29b0f896 6383
6c30d220
L		 6384 if (i.tm.opcode_modifier.vecsib)
6385 {
6386 if (i.index_reg->reg_num == RegEiz
6387 || i.index_reg->reg_num == RegRiz)
6388 abort ();
6389
6390 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6391 if (!i.base_reg)
6392 {
6393 i.sib.base = NO_BASE_REGISTER;
6394 i.sib.scale = i.log2_scale_factor;
43234a1e
L		 6395 /* No Vec_Disp8 if there is no base. */
6396 i.types[op].bitfield.vec_disp8 = 0;
6c30d220
L		 6397 i.types[op].bitfield.disp8 = 0;
6398 i.types[op].bitfield.disp16 = 0;
6399 i.types[op].bitfield.disp64 = 0;
6400 if (flag_code != CODE_64BIT)
6401 {
6402 /* Must be 32 bit */
6403 i.types[op].bitfield.disp32 = 1;
6404 i.types[op].bitfield.disp32s = 0;
6405 }
6406 else
6407 {
6408 i.types[op].bitfield.disp32 = 0;
6409 i.types[op].bitfield.disp32s = 1;
6410 }
6411 }
6412 i.sib.index = i.index_reg->reg_num;
6413 if ((i.index_reg->reg_flags & RegRex) != 0)
6414 i.rex |= REX_X;
43234a1e
L		 6415 if ((i.index_reg->reg_flags & RegVRex) != 0)
6416 i.vrex |= REX_X;
6c30d220
L		 6417 }
6418
29b0f896
AM		 6419 default_seg = &ds;
6420
6421 if (i.base_reg == 0)
6422 {
6423 i.rm.mode = 0;
6424 if (!i.disp_operands)
6c30d220
L		 6425 {
6426 fake_zero_displacement = 1;
6427 /* Instructions with VSIB byte need 32bit displacement
6428 if there is no base register. */
6429 if (i.tm.opcode_modifier.vecsib)
6430 i.types[op].bitfield.disp32 = 1;
6431 }
29b0f896
AM		 6432 if (i.index_reg == 0)
6433 {
6c30d220 6434 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6435 /* Operand is just <disp> */
20f0a1fc 6436 if (flag_code == CODE_64BIT)
29b0f896
AM		 6437 {
6438 /* 64bit mode overwrites the 32bit absolute
6439 addressing by RIP relative addressing and
6440 absolute addressing is encoded by one of the
6441 redundant SIB forms. */
6442 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6443 i.sib.base = NO_BASE_REGISTER;
6444 i.sib.index = NO_INDEX_REGISTER;
fc225355 6445 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6446 ? disp32s : disp32);
20f0a1fc 6447 }
fc225355
L		 6448 else if ((flag_code == CODE_16BIT)
6449 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6450 {
6451 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6452 i.types[op] = disp16;
20f0a1fc
NC		 6453 }
6454 else
6455 {
6456 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6457 i.types[op] = disp32;
29b0f896
AM		 6458 }
6459 }
6c30d220 6460 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6461 {
6c30d220 6462 /* !i.base_reg && i.index_reg */
db51cc60
L		 6463 if (i.index_reg->reg_num == RegEiz
6464 || i.index_reg->reg_num == RegRiz)
6465 i.sib.index = NO_INDEX_REGISTER;
6466 else
6467 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6468 i.sib.base = NO_BASE_REGISTER;
6469 i.sib.scale = i.log2_scale_factor;
6470 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
43234a1e
L		 6471 /* No Vec_Disp8 if there is no base. */
6472 i.types[op].bitfield.vec_disp8 = 0;
40fb9820
L		 6473 i.types[op].bitfield.disp8 = 0;
6474 i.types[op].bitfield.disp16 = 0;
6475 i.types[op].bitfield.disp64 = 0;
29b0f896 6476 if (flag_code != CODE_64BIT)
40fb9820
L		 6477 {
6478 /* Must be 32 bit */
6479 i.types[op].bitfield.disp32 = 1;
6480 i.types[op].bitfield.disp32s = 0;
6481 }
29b0f896 6482 else
40fb9820
L		 6483 {
6484 i.types[op].bitfield.disp32 = 0;
6485 i.types[op].bitfield.disp32s = 1;
6486 }
29b0f896 6487 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6488 i.rex |= REX_X;
29b0f896
AM		 6489 }
6490 }
6491 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6492 else if (i.base_reg->reg_num == RegRip ||
6493 i.base_reg->reg_num == RegEip)
29b0f896 6494 {
6c30d220 6495 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6496 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6497 i.types[op].bitfield.disp8 = 0;
6498 i.types[op].bitfield.disp16 = 0;
6499 i.types[op].bitfield.disp32 = 0;
6500 i.types[op].bitfield.disp32s = 1;
6501 i.types[op].bitfield.disp64 = 0;
43234a1e 6502 i.types[op].bitfield.vec_disp8 = 0;
71903a11 6503 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6504 if (! i.disp_operands)
6505 fake_zero_displacement = 1;
29b0f896 6506 }
40fb9820 6507 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 6508 {
6c30d220 6509 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6510 switch (i.base_reg->reg_num)
6511 {
6512 case 3: /* (%bx) */
6513 if (i.index_reg == 0)
6514 i.rm.regmem = 7;
6515 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6516 i.rm.regmem = i.index_reg->reg_num - 6;
6517 break;
6518 case 5: /* (%bp) */
6519 default_seg = &ss;
6520 if (i.index_reg == 0)
6521 {
6522 i.rm.regmem = 6;
40fb9820 6523 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6524 {
6525 /* fake (%bp) into 0(%bp) */
43234a1e
L		 6526 if (i.tm.operand_types[op].bitfield.vec_disp8)
6527 i.types[op].bitfield.vec_disp8 = 1;
6528 else
6529 i.types[op].bitfield.disp8 = 1;
252b5132 6530 fake_zero_displacement = 1;
29b0f896
AM		 6531 }
6532 }
6533 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6534 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6535 break;
6536 default: /* (%si) -> 4 or (%di) -> 5 */
6537 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6538 }
6539 i.rm.mode = mode_from_disp_size (i.types[op]);
6540 }
6541 else /* i.base_reg and 32/64 bit mode */
6542 {
6543 if (flag_code == CODE_64BIT
40fb9820
L		 6544 && operand_type_check (i.types[op], disp))
6545 {
6546 i386_operand_type temp;
0dfbf9d7 6547 operand_type_set (&temp, 0);
40fb9820 6548 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
43234a1e
L		 6549 temp.bitfield.vec_disp8
6550 = i.types[op].bitfield.vec_disp8;
40fb9820
L		 6551 i.types[op] = temp;
6552 if (i.prefix[ADDR_PREFIX] == 0)
6553 i.types[op].bitfield.disp32s = 1;
6554 else
6555 i.types[op].bitfield.disp32 = 1;
6556 }
20f0a1fc 6557
6c30d220
L		 6558 if (!i.tm.opcode_modifier.vecsib)
6559 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6560 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6561 i.rex |= REX_B;
29b0f896
AM		 6562 i.sib.base = i.base_reg->reg_num;
6563 /* x86-64 ignores REX prefix bit here to avoid decoder
6564 complications. */
848930b2
JB		 6565 if (!(i.base_reg->reg_flags & RegRex)
6566 && (i.base_reg->reg_num == EBP_REG_NUM
6567 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6568 default_seg = &ss;
848930b2 6569 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6570 {
848930b2 6571 fake_zero_displacement = 1;
43234a1e
L		 6572 if (i.tm.operand_types [op].bitfield.vec_disp8)
6573 i.types[op].bitfield.vec_disp8 = 1;
6574 else
6575 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6576 }
6577 i.sib.scale = i.log2_scale_factor;
6578 if (i.index_reg == 0)
6579 {
6c30d220 6580 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6581 /* <disp>(%esp) becomes two byte modrm with no index
6582 register. We've already stored the code for esp
6583 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6584 Any base register besides %esp will not use the
6585 extra modrm byte. */
6586 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6587 }
6c30d220 6588 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6589 {
db51cc60
L		 6590 if (i.index_reg->reg_num == RegEiz
6591 || i.index_reg->reg_num == RegRiz)
6592 i.sib.index = NO_INDEX_REGISTER;
6593 else
6594 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6595 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6596 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6597 i.rex |= REX_X;
29b0f896 6598 }
67a4f2b7
AO		 6599
6600 if (i.disp_operands
6601 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6602 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6603 i.rm.mode = 0;
6604 else
a501d77e
L		 6605 {
6606 if (!fake_zero_displacement
6607 && !i.disp_operands
6608 && i.disp_encoding)
6609 {
6610 fake_zero_displacement = 1;
6611 if (i.disp_encoding == disp_encoding_8bit)
6612 i.types[op].bitfield.disp8 = 1;
6613 else
6614 i.types[op].bitfield.disp32 = 1;
6615 }
6616 i.rm.mode = mode_from_disp_size (i.types[op]);
6617 }
29b0f896 6618 }
252b5132 6619
29b0f896
AM		 6620 if (fake_zero_displacement)
6621 {
6622 /* Fakes a zero displacement assuming that i.types[op]
6623 holds the correct displacement size. */
6624 expressionS *exp;
6625
9c2799c2 6626 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6627 exp = &disp_expressions[i.disp_operands++];
6628 i.op[op].disps = exp;
6629 exp->X_op = O_constant;
6630 exp->X_add_number = 0;
6631 exp->X_add_symbol = (symbolS *) 0;
6632 exp->X_op_symbol = (symbolS *) 0;
6633 }
c0f3af97
L		 6634
6635 mem = op;
29b0f896 6636 }
c0f3af97
L		 6637 else
6638 mem = ~0;
252b5132 6639
8c43a48b 6640 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6641 {
6642 if (operand_type_check (i.types[0], imm))
6643 i.vex.register_specifier = NULL;
6644 else
6645 {
6646 /* VEX.vvvv encodes one of the sources when the first
6647 operand is not an immediate. */
1ef99a7b 6648 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6649 i.vex.register_specifier = i.op[0].regs;
6650 else
6651 i.vex.register_specifier = i.op[1].regs;
6652 }
6653
6654 /* Destination is a XMM register encoded in the ModRM.reg
6655 and VEX.R bit. */
6656 i.rm.reg = i.op[2].regs->reg_num;
6657 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6658 i.rex |= REX_R;
6659
6660 /* ModRM.rm and VEX.B encodes the other source. */
6661 if (!i.mem_operands)
6662 {
6663 i.rm.mode = 3;
6664
1ef99a7b 6665 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6666 i.rm.regmem = i.op[1].regs->reg_num;
6667 else
6668 i.rm.regmem = i.op[0].regs->reg_num;
6669
6670 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6671 i.rex |= REX_B;
6672 }
6673 }
2426c15f 6674 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6675 {
6676 i.vex.register_specifier = i.op[2].regs;
6677 if (!i.mem_operands)
6678 {
6679 i.rm.mode = 3;
6680 i.rm.regmem = i.op[1].regs->reg_num;
6681 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6682 i.rex |= REX_B;
6683 }
6684 }
29b0f896
AM		 6685 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6686 (if any) based on i.tm.extension_opcode. Again, we must be
6687 careful to make sure that segment/control/debug/test/MMX
6688 registers are coded into the i.rm.reg field. */
f88c9eb0 6689 else if (i.reg_operands)
29b0f896 6690 {
99018f42 6691 unsigned int op;
7ab9ffdd
L		 6692 unsigned int vex_reg = ~0;
6693
6694 for (op = 0; op < i.operands; op++)
6695 if (i.types[op].bitfield.reg8
6696 || i.types[op].bitfield.reg16
6697 || i.types[op].bitfield.reg32
6698 || i.types[op].bitfield.reg64
6699 || i.types[op].bitfield.regmmx
6700 || i.types[op].bitfield.regxmm
6701 || i.types[op].bitfield.regymm
7e8b059b 6702 || i.types[op].bitfield.regbnd
43234a1e
L		 6703 || i.types[op].bitfield.regzmm
6704 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6705 || i.types[op].bitfield.sreg2
6706 || i.types[op].bitfield.sreg3
6707 || i.types[op].bitfield.control
6708 || i.types[op].bitfield.debug
6709 || i.types[op].bitfield.test)
6710 break;
c0209578 6711
7ab9ffdd
L		 6712 if (vex_3_sources)
6713 op = dest;
2426c15f 6714 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6715 {
6716 /* For instructions with VexNDS, the register-only
6717 source operand is encoded in VEX prefix. */
6718 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6719
7ab9ffdd 6720 if (op > mem)
c0f3af97 6721 {
7ab9ffdd
L		 6722 vex_reg = op++;
6723 gas_assert (op < i.operands);
c0f3af97
L		 6724 }
6725 else
c0f3af97 6726 {
f12dc422
L		 6727 /* Check register-only source operand when two source
6728 operands are swapped. */
6729 if (!i.tm.operand_types[op].bitfield.baseindex
6730 && i.tm.operand_types[op + 1].bitfield.baseindex)
6731 {
6732 vex_reg = op;
6733 op += 2;
6734 gas_assert (mem == (vex_reg + 1)
6735 && op < i.operands);
6736 }
6737 else
6738 {
6739 vex_reg = op + 1;
6740 gas_assert (vex_reg < i.operands);
6741 }
c0f3af97 6742 }
7ab9ffdd 6743 }
2426c15f 6744 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6745 {
f12dc422 6746 /* For instructions with VexNDD, the register destination
7ab9ffdd 6747 is encoded in VEX prefix. */
f12dc422
L		 6748 if (i.mem_operands == 0)
6749 {
6750 /* There is no memory operand. */
6751 gas_assert ((op + 2) == i.operands);
6752 vex_reg = op + 1;
6753 }
6754 else
8d63c93e 6755 {
f12dc422
L		 6756 /* There are only 2 operands. */
6757 gas_assert (op < 2 && i.operands == 2);
6758 vex_reg = 1;
6759 }
7ab9ffdd
L		 6760 }
6761 else
6762 gas_assert (op < i.operands);
99018f42 6763
7ab9ffdd
L		 6764 if (vex_reg != (unsigned int) ~0)
6765 {
f12dc422 6766 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6767
f12dc422
L		 6768 if (type->bitfield.reg32 != 1
6769 && type->bitfield.reg64 != 1
6770 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6771 && !operand_type_equal (type, &regymm)
6772 && !operand_type_equal (type, &regzmm)
6773 && !operand_type_equal (type, &regmask))
7ab9ffdd 6774 abort ();
f88c9eb0 6775
7ab9ffdd
L		 6776 i.vex.register_specifier = i.op[vex_reg].regs;
6777 }
6778
1b9f0c97
L		 6779 /* Don't set OP operand twice. */
6780 if (vex_reg != op)
7ab9ffdd 6781 {
1b9f0c97
L		 6782 /* If there is an extension opcode to put here, the
6783 register number must be put into the regmem field. */
6784 if (i.tm.extension_opcode != None)
6785 {
6786 i.rm.regmem = i.op[op].regs->reg_num;
6787 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6788 i.rex |= REX_B;
43234a1e
L		 6789 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6790 i.vrex |= REX_B;
1b9f0c97
L		 6791 }
6792 else
6793 {
6794 i.rm.reg = i.op[op].regs->reg_num;
6795 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6796 i.rex |= REX_R;
43234a1e
L		 6797 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6798 i.vrex |= REX_R;
1b9f0c97 6799 }
7ab9ffdd 6800 }
252b5132 6801
29b0f896
AM		 6802 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6803 must set it to 3 to indicate this is a register operand
6804 in the regmem field. */
6805 if (!i.mem_operands)
6806 i.rm.mode = 3;
6807 }
252b5132 6808
29b0f896 6809 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6810 if (i.tm.extension_opcode != None)
29b0f896
AM		 6811 i.rm.reg = i.tm.extension_opcode;
6812 }
6813 return default_seg;
6814}
252b5132 6815
29b0f896 6816static void
e3bb37b5 6817output_branch (void)
29b0f896
AM		 6818{
6819 char *p;
f8a5c266 6820 int size;
29b0f896
AM		 6821 int code16;
6822 int prefix;
6823 relax_substateT subtype;
6824 symbolS *sym;
6825 offsetT off;
6826
f8a5c266 6827 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6828 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6829
6830 prefix = 0;
6831 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6832 {
29b0f896
AM		 6833 prefix = 1;
6834 i.prefixes -= 1;
6835 code16 ^= CODE16;
252b5132 6836 }
29b0f896
AM		 6837 /* Pentium4 branch hints. */
6838 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6839 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6840 {
29b0f896
AM		 6841 prefix++;
6842 i.prefixes--;
6843 }
6844 if (i.prefix[REX_PREFIX] != 0)
6845 {
6846 prefix++;
6847 i.prefixes--;
2f66722d
AM		 6848 }
6849
7e8b059b
L		 6850 /* BND prefixed jump. */
6851 if (i.prefix[BND_PREFIX] != 0)
6852 {
6853 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6854 i.prefixes -= 1;
6855 }
6856
29b0f896
AM		 6857 if (i.prefixes != 0 && !intel_syntax)
6858 as_warn (_("skipping prefixes on this instruction"));
6859
6860 /* It's always a symbol; End frag & setup for relax.
6861 Make sure there is enough room in this frag for the largest
6862 instruction we may generate in md_convert_frag. This is 2
6863 bytes for the opcode and room for the prefix and largest
6864 displacement. */
6865 frag_grow (prefix + 2 + 4);
6866 /* Prefix and 1 opcode byte go in fr_fix. */
6867 p = frag_more (prefix + 1);
6868 if (i.prefix[DATA_PREFIX] != 0)
6869 *p++ = DATA_PREFIX_OPCODE;
6870 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6871 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6872 *p++ = i.prefix[SEG_PREFIX];
6873 if (i.prefix[REX_PREFIX] != 0)
6874 *p++ = i.prefix[REX_PREFIX];
6875 *p = i.tm.base_opcode;
6876
6877 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6878 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6879 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6880 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6881 else
f8a5c266 6882 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 6883 subtype |= code16;
3e73aa7c 6884
29b0f896
AM		 6885 sym = i.op[0].disps->X_add_symbol;
6886 off = i.op[0].disps->X_add_number;
3e73aa7c 6887
29b0f896
AM		 6888 if (i.op[0].disps->X_op != O_constant
6889 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 6890 {
29b0f896
AM		 6891 /* Handle complex expressions. */
6892 sym = make_expr_symbol (i.op[0].disps);
6893 off = 0;
6894 }
3e73aa7c 6895
29b0f896
AM		 6896 /* 1 possible extra opcode + 4 byte displacement go in var part.
6897 Pass reloc in fr_var. */
d258b828 6898 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 6899}
3e73aa7c 6900
29b0f896 6901static void
e3bb37b5 6902output_jump (void)
29b0f896
AM		 6903{
6904 char *p;
6905 int size;
3e02c1cc 6906 fixS *fixP;
29b0f896 6907
40fb9820 6908 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 6909 {
6910 /* This is a loop or jecxz type instruction. */
6911 size = 1;
6912 if (i.prefix[ADDR_PREFIX] != 0)
6913 {
6914 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6915 i.prefixes -= 1;
6916 }
6917 /* Pentium4 branch hints. */
6918 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6919 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6920 {
6921 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6922 i.prefixes--;
3e73aa7c
JH		 6923 }
6924 }
29b0f896
AM		 6925 else
6926 {
6927 int code16;
3e73aa7c 6928
29b0f896
AM		 6929 code16 = 0;
6930 if (flag_code == CODE_16BIT)
6931 code16 = CODE16;
3e73aa7c 6932
29b0f896
AM		 6933 if (i.prefix[DATA_PREFIX] != 0)
6934 {
6935 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6936 i.prefixes -= 1;
6937 code16 ^= CODE16;
6938 }
252b5132 6939
29b0f896
AM		 6940 size = 4;
6941 if (code16)
6942 size = 2;
6943 }
9fcc94b6 6944
29b0f896
AM		 6945 if (i.prefix[REX_PREFIX] != 0)
6946 {
6947 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6948 i.prefixes -= 1;
6949 }
252b5132 6950
7e8b059b
L		 6951 /* BND prefixed jump. */
6952 if (i.prefix[BND_PREFIX] != 0)
6953 {
6954 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6955 i.prefixes -= 1;
6956 }
6957
29b0f896
AM		 6958 if (i.prefixes != 0 && !intel_syntax)
6959 as_warn (_("skipping prefixes on this instruction"));
e0890092 6960
42164a71
L		 6961 p = frag_more (i.tm.opcode_length + size);
6962 switch (i.tm.opcode_length)
6963 {
6964 case 2:
6965 *p++ = i.tm.base_opcode >> 8;
6966 case 1:
6967 *p++ = i.tm.base_opcode;
6968 break;
6969 default:
6970 abort ();
6971 }
e0890092 6972
3e02c1cc 6973 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 6974 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3e02c1cc
AM		 6975
6976 /* All jumps handled here are signed, but don't use a signed limit
6977 check for 32 and 16 bit jumps as we want to allow wrap around at
6978 4G and 64k respectively. */
6979 if (size == 1)
6980 fixP->fx_signed = 1;
29b0f896 6981}
e0890092 6982
29b0f896 6983static void
e3bb37b5 6984output_interseg_jump (void)
29b0f896
AM		 6985{
6986 char *p;
6987 int size;
6988 int prefix;
6989 int code16;
252b5132 6990
29b0f896
AM		 6991 code16 = 0;
6992 if (flag_code == CODE_16BIT)
6993 code16 = CODE16;
a217f122 6994
29b0f896
AM		 6995 prefix = 0;
6996 if (i.prefix[DATA_PREFIX] != 0)
6997 {
6998 prefix = 1;
6999 i.prefixes -= 1;
7000 code16 ^= CODE16;
7001 }
7002 if (i.prefix[REX_PREFIX] != 0)
7003 {
7004 prefix++;
7005 i.prefixes -= 1;
7006 }
252b5132 7007
29b0f896
AM		 7008 size = 4;
7009 if (code16)
7010 size = 2;
252b5132 7011
29b0f896
AM		 7012 if (i.prefixes != 0 && !intel_syntax)
7013 as_warn (_("skipping prefixes on this instruction"));
252b5132 7014
29b0f896
AM		 7015 /* 1 opcode; 2 segment; offset */
7016 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 7017
29b0f896
AM		 7018 if (i.prefix[DATA_PREFIX] != 0)
7019 *p++ = DATA_PREFIX_OPCODE;
252b5132 7020
29b0f896
AM		 7021 if (i.prefix[REX_PREFIX] != 0)
7022 *p++ = i.prefix[REX_PREFIX];
252b5132 7023
29b0f896
AM		 7024 *p++ = i.tm.base_opcode;
7025 if (i.op[1].imms->X_op == O_constant)
7026 {
7027 offsetT n = i.op[1].imms->X_add_number;
252b5132 7028
29b0f896
AM		 7029 if (size == 2
7030 && !fits_in_unsigned_word (n)
7031 && !fits_in_signed_word (n))
7032 {
7033 as_bad (_("16-bit jump out of range"));
7034 return;
7035 }
7036 md_number_to_chars (p, n, size);
7037 }
7038 else
7039 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 7040 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 7041 if (i.op[0].imms->X_op != O_constant)
7042 as_bad (_("can't handle non absolute segment in `%s'"),
7043 i.tm.name);
7044 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7045}
a217f122 7046
29b0f896 7047static void
e3bb37b5 7048output_insn (void)
29b0f896 7049{
2bbd9c25
JJ		 7050 fragS *insn_start_frag;
7051 offsetT insn_start_off;
7052
29b0f896
AM		 7053 /* Tie dwarf2 debug info to the address at the start of the insn.
7054 We can't do this after the insn has been output as the current
7055 frag may have been closed off. eg. by frag_var. */
7056 dwarf2_emit_insn (0);
7057
2bbd9c25
JJ		 7058 insn_start_frag = frag_now;
7059 insn_start_off = frag_now_fix ();
7060
29b0f896 7061 /* Output jumps. */
40fb9820 7062 if (i.tm.opcode_modifier.jump)
29b0f896 7063 output_branch ();
40fb9820
L		 7064 else if (i.tm.opcode_modifier.jumpbyte
7065 || i.tm.opcode_modifier.jumpdword)
29b0f896 7066 output_jump ();
40fb9820 7067 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 7068 output_interseg_jump ();
7069 else
7070 {
7071 /* Output normal instructions here. */
7072 char *p;
7073 unsigned char *q;
47465058 7074 unsigned int j;
331d2d0d 7075 unsigned int prefix;
4dffcebc 7076
e4e00185
AS		 7077 if (avoid_fence
7078 && i.tm.base_opcode == 0xfae
7079 && i.operands == 1
7080 && i.imm_operands == 1
7081 && (i.op[0].imms->X_add_number == 0xe8
7082 || i.op[0].imms->X_add_number == 0xf0
7083 || i.op[0].imms->X_add_number == 0xf8))
7084 {
7085 /* Encode lfence, mfence, and sfence as
7086 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7087 offsetT val = 0x240483f0ULL;
7088 p = frag_more (5);
7089 md_number_to_chars (p, val, 5);
7090 return;
7091 }
7092
d022bddd
IT		 7093 /* Some processors fail on LOCK prefix. This options makes
7094 assembler ignore LOCK prefix and serves as a workaround. */
7095 if (omit_lock_prefix)
7096 {
7097 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7098 return;
7099 i.prefix[LOCK_PREFIX] = 0;
7100 }
7101
43234a1e
L		 7102 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7103 don't need the explicit prefix. */
7104 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 7105 {
c0f3af97 7106 switch (i.tm.opcode_length)
bc4bd9ab 7107 {
c0f3af97
L		 7108 case 3:
7109 if (i.tm.base_opcode & 0xff000000)
4dffcebc 7110 {
c0f3af97
L		 7111 prefix = (i.tm.base_opcode >> 24) & 0xff;
7112 goto check_prefix;
7113 }
7114 break;
7115 case 2:
7116 if ((i.tm.base_opcode & 0xff0000) != 0)
7117 {
7118 prefix = (i.tm.base_opcode >> 16) & 0xff;
7119 if (i.tm.cpu_flags.bitfield.cpupadlock)
7120 {
4dffcebc 7121check_prefix:
c0f3af97 7122 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 7123 || (i.prefix[REP_PREFIX]
c0f3af97
L		 7124 != REPE_PREFIX_OPCODE))
7125 add_prefix (prefix);
7126 }
7127 else
4dffcebc
L		 7128 add_prefix (prefix);
7129 }
c0f3af97
L		 7130 break;
7131 case 1:
7132 break;
7133 default:
7134 abort ();
bc4bd9ab 7135 }
c0f3af97 7136
6d19a37a 7137#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 7138 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7139 R_X86_64_GOTTPOFF relocation so that linker can safely
7140 perform IE->LE optimization. */
7141 if (x86_elf_abi == X86_64_X32_ABI
7142 && i.operands == 2
7143 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7144 && i.prefix[REX_PREFIX] == 0)
7145 add_prefix (REX_OPCODE);
6d19a37a 7146#endif
cf61b747 7147
c0f3af97
L		 7148 /* The prefix bytes. */
7149 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7150 if (*q)
7151 FRAG_APPEND_1_CHAR (*q);
0f10071e 7152 }
ae5c1c7b 7153 else
c0f3af97
L		 7154 {
7155 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7156 if (*q)
7157 switch (j)
7158 {
7159 case REX_PREFIX:
7160 /* REX byte is encoded in VEX prefix. */
7161 break;
7162 case SEG_PREFIX:
7163 case ADDR_PREFIX:
7164 FRAG_APPEND_1_CHAR (*q);
7165 break;
7166 default:
7167 /* There should be no other prefixes for instructions
7168 with VEX prefix. */
7169 abort ();
7170 }
7171
43234a1e
L		 7172 /* For EVEX instructions i.vrex should become 0 after
7173 build_evex_prefix. For VEX instructions upper 16 registers
7174 aren't available, so VREX should be 0. */
7175 if (i.vrex)
7176 abort ();
c0f3af97
L		 7177 /* Now the VEX prefix. */
7178 p = frag_more (i.vex.length);
7179 for (j = 0; j < i.vex.length; j++)
7180 p[j] = i.vex.bytes[j];
7181 }
252b5132 7182
29b0f896 7183 /* Now the opcode; be careful about word order here! */
4dffcebc 7184 if (i.tm.opcode_length == 1)
29b0f896
AM		 7185 {
7186 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7187 }
7188 else
7189 {
4dffcebc 7190 switch (i.tm.opcode_length)
331d2d0d 7191 {
43234a1e
L		 7192 case 4:
7193 p = frag_more (4);
7194 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7195 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7196 break;
4dffcebc 7197 case 3:
331d2d0d
L		 7198 p = frag_more (3);
7199 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7200 break;
7201 case 2:
7202 p = frag_more (2);
7203 break;
7204 default:
7205 abort ();
7206 break;
331d2d0d 7207 }
0f10071e 7208
29b0f896
AM		 7209 /* Put out high byte first: can't use md_number_to_chars! */
7210 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7211 *p = i.tm.base_opcode & 0xff;
7212 }
3e73aa7c 7213
29b0f896 7214 /* Now the modrm byte and sib byte (if present). */
40fb9820 7215 if (i.tm.opcode_modifier.modrm)
29b0f896 7216 {
4a3523fa
L		 7217 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7218 | i.rm.reg << 3
7219 | i.rm.mode << 6));
29b0f896
AM		 7220 /* If i.rm.regmem == ESP (4)
7221 && i.rm.mode != (Register mode)
7222 && not 16 bit
7223 ==> need second modrm byte. */
7224 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7225 && i.rm.mode != 3
40fb9820 7226 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 7227 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7228 | i.sib.index << 3
7229 | i.sib.scale << 6));
29b0f896 7230 }
3e73aa7c 7231
29b0f896 7232 if (i.disp_operands)
2bbd9c25 7233 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7234
29b0f896 7235 if (i.imm_operands)
2bbd9c25 7236 output_imm (insn_start_frag, insn_start_off);
29b0f896 7237 }
252b5132 7238
29b0f896
AM		 7239#ifdef DEBUG386
7240 if (flag_debug)
7241 {
7b81dfbb 7242 pi ("" /*line*/, &i);
29b0f896
AM		 7243 }
7244#endif /* DEBUG386 */
7245}
252b5132 7246
e205caa7
L		 7247/* Return the size of the displacement operand N. */
7248
7249static int
7250disp_size (unsigned int n)
7251{
7252 int size = 4;
43234a1e
L		 7253
7254 /* Vec_Disp8 has to be 8bit. */
7255 if (i.types[n].bitfield.vec_disp8)
7256 size = 1;
7257 else if (i.types[n].bitfield.disp64)
40fb9820
L		 7258 size = 8;
7259 else if (i.types[n].bitfield.disp8)
7260 size = 1;
7261 else if (i.types[n].bitfield.disp16)
7262 size = 2;
e205caa7
L		 7263 return size;
7264}
7265
7266/* Return the size of the immediate operand N. */
7267
7268static int
7269imm_size (unsigned int n)
7270{
7271 int size = 4;
40fb9820
L		 7272 if (i.types[n].bitfield.imm64)
7273 size = 8;
7274 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7275 size = 1;
7276 else if (i.types[n].bitfield.imm16)
7277 size = 2;
e205caa7
L		 7278 return size;
7279}
7280
29b0f896 7281static void
64e74474 7282output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7283{
7284 char *p;
7285 unsigned int n;
252b5132 7286
29b0f896
AM		 7287 for (n = 0; n < i.operands; n++)
7288 {
43234a1e
L		 7289 if (i.types[n].bitfield.vec_disp8
7290 || operand_type_check (i.types[n], disp))
29b0f896
AM		 7291 {
7292 if (i.op[n].disps->X_op == O_constant)
7293 {
e205caa7 7294 int size = disp_size (n);
43234a1e 7295 offsetT val = i.op[n].disps->X_add_number;
252b5132 7296
43234a1e
L		 7297 if (i.types[n].bitfield.vec_disp8)
7298 val >>= i.memshift;
7299 val = offset_in_range (val, size);
29b0f896
AM		 7300 p = frag_more (size);
7301 md_number_to_chars (p, val, size);
7302 }
7303 else
7304 {
f86103b7 7305 enum bfd_reloc_code_real reloc_type;
e205caa7 7306 int size = disp_size (n);
40fb9820 7307 int sign = i.types[n].bitfield.disp32s;
29b0f896 7308 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
02a86693 7309 fixS *fixP;
29b0f896 7310
e205caa7 7311 /* We can't have 8 bit displacement here. */
9c2799c2 7312 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7313
29b0f896
AM		 7314 /* The PC relative address is computed relative
7315 to the instruction boundary, so in case immediate
7316 fields follows, we need to adjust the value. */
7317 if (pcrel && i.imm_operands)
7318 {
29b0f896 7319 unsigned int n1;
e205caa7 7320 int sz = 0;
252b5132 7321
29b0f896 7322 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7323 if (operand_type_check (i.types[n1], imm))
252b5132 7324 {
e205caa7
L		 7325 /* Only one immediate is allowed for PC
7326 relative address. */
9c2799c2 7327 gas_assert (sz == 0);
e205caa7
L		 7328 sz = imm_size (n1);
7329 i.op[n].disps->X_add_number -= sz;
252b5132 7330 }
29b0f896 7331 /* We should find the immediate. */
9c2799c2 7332 gas_assert (sz != 0);
29b0f896 7333 }
520dc8e8 7334
29b0f896 7335 p = frag_more (size);
d258b828 7336 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7337 if (GOT_symbol
2bbd9c25 7338 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7339 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7340 || reloc_type == BFD_RELOC_X86_64_32S
7341 || (reloc_type == BFD_RELOC_64
7342 && object_64bit))
d6ab8113
JB		 7343 && (i.op[n].disps->X_op == O_symbol
7344 || (i.op[n].disps->X_op == O_add
7345 && ((symbol_get_value_expression
7346 (i.op[n].disps->X_op_symbol)->X_op)
7347 == O_subtract))))
7348 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7349 {
7350 offsetT add;
7351
7352 if (insn_start_frag == frag_now)
7353 add = (p - frag_now->fr_literal) - insn_start_off;
7354 else
7355 {
7356 fragS *fr;
7357
7358 add = insn_start_frag->fr_fix - insn_start_off;
7359 for (fr = insn_start_frag->fr_next;
7360 fr && fr != frag_now; fr = fr->fr_next)
7361 add += fr->fr_fix;
7362 add += p - frag_now->fr_literal;
7363 }
7364
4fa24527 7365 if (!object_64bit)
7b81dfbb
AJ		 7366 {
7367 reloc_type = BFD_RELOC_386_GOTPC;
7368 i.op[n].imms->X_add_number += add;
7369 }
7370 else if (reloc_type == BFD_RELOC_64)
7371 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7372 else
7b81dfbb
AJ		 7373 /* Don't do the adjustment for x86-64, as there
7374 the pcrel addressing is relative to the _next_
7375 insn, and that is taken care of in other code. */
d6ab8113 7376 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7377 }
02a86693
L		 7378 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7379 size, i.op[n].disps, pcrel,
7380 reloc_type);
7381 /* Check for "call/jmp *mem", "mov mem, %reg",
7382 "test %reg, mem" and "binop mem, %reg" where binop
7383 is one of adc, add, and, cmp, or, sbb, sub, xor
0cb4071e
L		 7384 instructions. Always generate R_386_GOT32X for
7385 "sym*GOT" operand in 32-bit mode. */
7386 if ((generate_relax_relocations
7387 || (!object_64bit
7388 && i.rm.mode == 0
7389 && i.rm.regmem == 5))
7390 && (i.rm.mode == 2
7391 || (i.rm.mode == 0 && i.rm.regmem == 5))
02a86693
L		 7392 && ((i.operands == 1
7393 && i.tm.base_opcode == 0xff
7394 && (i.rm.reg == 2 || i.rm.reg == 4))
7395 || (i.operands == 2
7396 && (i.tm.base_opcode == 0x8b
7397 || i.tm.base_opcode == 0x85
7398 || (i.tm.base_opcode & 0xc7) == 0x03))))
7399 {
7400 if (object_64bit)
7401 {
7402 fixP->fx_tcbit = i.rex != 0;
7403 if (i.base_reg
7404 && (i.base_reg->reg_num == RegRip
7405 || i.base_reg->reg_num == RegEip))
7406 fixP->fx_tcbit2 = 1;
7407 }
7408 else
7409 fixP->fx_tcbit2 = 1;
7410 }
29b0f896
AM		 7411 }
7412 }
7413 }
7414}
252b5132 7415
29b0f896 7416static void
64e74474 7417output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7418{
7419 char *p;
7420 unsigned int n;
252b5132 7421
29b0f896
AM		 7422 for (n = 0; n < i.operands; n++)
7423 {
43234a1e
L		 7424 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7425 if (i.rounding && (int) n == i.rounding->operand)
7426 continue;
7427
40fb9820 7428 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7429 {
7430 if (i.op[n].imms->X_op == O_constant)
7431 {
e205caa7 7432 int size = imm_size (n);
29b0f896 7433 offsetT val;
b4cac588 7434
29b0f896
AM		 7435 val = offset_in_range (i.op[n].imms->X_add_number,
7436 size);
7437 p = frag_more (size);
7438 md_number_to_chars (p, val, size);
7439 }
7440 else
7441 {
7442 /* Not absolute_section.
7443 Need a 32-bit fixup (don't support 8bit
7444 non-absolute imms). Try to support other
7445 sizes ... */
f86103b7 7446 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7447 int size = imm_size (n);
7448 int sign;
29b0f896 7449
40fb9820 7450 if (i.types[n].bitfield.imm32s
a7d61044 7451 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7452 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7453 sign = 1;
e205caa7
L		 7454 else
7455 sign = 0;
520dc8e8 7456
29b0f896 7457 p = frag_more (size);
d258b828 7458 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 7459
2bbd9c25
JJ		 7460 /* This is tough to explain. We end up with this one if we
7461 * have operands that look like
7462 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7463 * obtain the absolute address of the GOT, and it is strongly
7464 * preferable from a performance point of view to avoid using
7465 * a runtime relocation for this. The actual sequence of
7466 * instructions often look something like:
7467 *
7468 * call .L66
7469 * .L66:
7470 * popl %ebx
7471 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7472 *
7473 * The call and pop essentially return the absolute address
7474 * of the label .L66 and store it in %ebx. The linker itself
7475 * will ultimately change the first operand of the addl so
7476 * that %ebx points to the GOT, but to keep things simple, the
7477 * .o file must have this operand set so that it generates not
7478 * the absolute address of .L66, but the absolute address of
7479 * itself. This allows the linker itself simply treat a GOTPC
7480 * relocation as asking for a pcrel offset to the GOT to be
7481 * added in, and the addend of the relocation is stored in the
7482 * operand field for the instruction itself.
7483 *
7484 * Our job here is to fix the operand so that it would add
7485 * the correct offset so that %ebx would point to itself. The
7486 * thing that is tricky is that .-.L66 will point to the
7487 * beginning of the instruction, so we need to further modify
7488 * the operand so that it will point to itself. There are
7489 * other cases where you have something like:
7490 *
7491 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7492 *
7493 * and here no correction would be required. Internally in
7494 * the assembler we treat operands of this form as not being
7495 * pcrel since the '.' is explicitly mentioned, and I wonder
7496 * whether it would simplify matters to do it this way. Who
7497 * knows. In earlier versions of the PIC patches, the
7498 * pcrel_adjust field was used to store the correction, but
7499 * since the expression is not pcrel, I felt it would be
7500 * confusing to do it this way. */
7501
d6ab8113 7502 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7503 || reloc_type == BFD_RELOC_X86_64_32S
7504 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7505 && GOT_symbol
7506 && GOT_symbol == i.op[n].imms->X_add_symbol
7507 && (i.op[n].imms->X_op == O_symbol
7508 || (i.op[n].imms->X_op == O_add
7509 && ((symbol_get_value_expression
7510 (i.op[n].imms->X_op_symbol)->X_op)
7511 == O_subtract))))
7512 {
2bbd9c25
JJ		 7513 offsetT add;
7514
7515 if (insn_start_frag == frag_now)
7516 add = (p - frag_now->fr_literal) - insn_start_off;
7517 else
7518 {
7519 fragS *fr;
7520
7521 add = insn_start_frag->fr_fix - insn_start_off;
7522 for (fr = insn_start_frag->fr_next;
7523 fr && fr != frag_now; fr = fr->fr_next)
7524 add += fr->fr_fix;
7525 add += p - frag_now->fr_literal;
7526 }
7527
4fa24527 7528 if (!object_64bit)
d6ab8113 7529 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7530 else if (size == 4)
d6ab8113 7531 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7532 else if (size == 8)
7533 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7534 i.op[n].imms->X_add_number += add;
29b0f896 7535 }
29b0f896
AM		 7536 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7537 i.op[n].imms, 0, reloc_type);
7538 }
7539 }
7540 }
252b5132
RH		 7541}
7542\f
d182319b
JB		 7543/* x86_cons_fix_new is called via the expression parsing code when a
7544 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 7545static int cons_sign = -1;
7546
7547void
e3bb37b5 7548x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 7549 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 7550{
d258b828 7551 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 7552
7553#ifdef TE_PE
7554 if (exp->X_op == O_secrel)
7555 {
7556 exp->X_op = O_symbol;
7557 r = BFD_RELOC_32_SECREL;
7558 }
7559#endif
7560
7561 fix_new_exp (frag, off, len, exp, 0, r);
7562}
7563
357d1bd8
L		 7564/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7565 purpose of the `.dc.a' internal pseudo-op. */
7566
7567int
7568x86_address_bytes (void)
7569{
7570 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7571 return 4;
7572 return stdoutput->arch_info->bits_per_address / 8;
7573}
7574
d382c579
TG		 7575#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7576 || defined (LEX_AT)
d258b828 7577# define lex_got(reloc, adjust, types) NULL
718ddfc0 7578#else
f3c180ae
AM		 7579/* Parse operands of the form
7580 <symbol>@GOTOFF+<nnn>
7581 and similar .plt or .got references.
7582
7583 If we find one, set up the correct relocation in RELOC and copy the
7584 input string, minus the `@GOTOFF' into a malloc'd buffer for
7585 parsing by the calling routine. Return this buffer, and if ADJUST
7586 is non-null set it to the length of the string we removed from the
7587 input line. Otherwise return NULL. */
7588static char *
91d6fa6a 7589lex_got (enum bfd_reloc_code_real *rel,
64e74474 7590 int *adjust,
d258b828 7591 i386_operand_type *types)
f3c180ae 7592{
7b81dfbb
AJ		 7593 /* Some of the relocations depend on the size of what field is to
7594 be relocated. But in our callers i386_immediate and i386_displacement
7595 we don't yet know the operand size (this will be set by insn
7596 matching). Hence we record the word32 relocation here,
7597 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7598 static const struct {
7599 const char *str;
cff8d58a 7600 int len;
4fa24527 7601 const enum bfd_reloc_code_real rel[2];
40fb9820 7602 const i386_operand_type types64;
f3c180ae 7603 } gotrel[] = {
8ce3d284 7604#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7605 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7606 BFD_RELOC_SIZE32 },
7607 OPERAND_TYPE_IMM32_64 },
8ce3d284 7608#endif
cff8d58a
L		 7609 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7610 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7611 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7612 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7613 BFD_RELOC_X86_64_PLT32 },
40fb9820 7614 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7615 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7616 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7617 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7618 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7619 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7620 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7621 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7622 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7623 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7624 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7625 BFD_RELOC_X86_64_TLSGD },
40fb9820 7626 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7627 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7628 _dummy_first_bfd_reloc_code_real },
40fb9820 7629 OPERAND_TYPE_NONE },
cff8d58a
L		 7630 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7631 BFD_RELOC_X86_64_TLSLD },
40fb9820 7632 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7633 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7634 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7635 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7636 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7637 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7638 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7639 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7640 _dummy_first_bfd_reloc_code_real },
40fb9820 7641 OPERAND_TYPE_NONE },
cff8d58a
L		 7642 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7643 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7644 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7645 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7646 _dummy_first_bfd_reloc_code_real },
40fb9820 7647 OPERAND_TYPE_NONE },
cff8d58a
L		 7648 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7649 _dummy_first_bfd_reloc_code_real },
40fb9820 7650 OPERAND_TYPE_NONE },
cff8d58a
L		 7651 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7652 BFD_RELOC_X86_64_GOT32 },
40fb9820 7653 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7654 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7655 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7656 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7657 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7658 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7659 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7660 };
7661 char *cp;
7662 unsigned int j;
7663
d382c579 7664#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7665 if (!IS_ELF)
7666 return NULL;
d382c579 7667#endif
718ddfc0 7668
f3c180ae 7669 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7670 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7671 return NULL;
7672
47465058 7673 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7674 {
cff8d58a 7675 int len = gotrel[j].len;
28f81592 7676 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7677 {
4fa24527 7678 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7679 {
28f81592
AM		 7680 int first, second;
7681 char *tmpbuf, *past_reloc;
f3c180ae 7682
91d6fa6a 7683 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7684
3956db08
JB		 7685 if (types)
7686 {
7687 if (flag_code != CODE_64BIT)
40fb9820
L		 7688 {
7689 types->bitfield.imm32 = 1;
7690 types->bitfield.disp32 = 1;
7691 }
3956db08
JB		 7692 else
7693 *types = gotrel[j].types64;
7694 }
7695
8fd4256d 7696 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7697 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7698
28f81592 7699 /* The length of the first part of our input line. */
f3c180ae 7700 first = cp - input_line_pointer;
28f81592
AM		 7701
7702 /* The second part goes from after the reloc token until
67c11a9b 7703 (and including) an end_of_line char or comma. */
28f81592 7704 past_reloc = cp + 1 + len;
67c11a9b
AM		 7705 cp = past_reloc;
7706 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7707 ++cp;
7708 second = cp + 1 - past_reloc;
28f81592
AM		 7709
7710 /* Allocate and copy string. The trailing NUL shouldn't
7711 be necessary, but be safe. */
add39d23 7712 tmpbuf = XNEWVEC (char, first + second + 2);
f3c180ae 7713 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7714 if (second != 0 && *past_reloc != ' ')
7715 /* Replace the relocation token with ' ', so that
7716 errors like foo@GOTOFF1 will be detected. */
7717 tmpbuf[first++] = ' ';
af89796a
L		 7718 else
7719 /* Increment length by 1 if the relocation token is
7720 removed. */
7721 len++;
7722 if (adjust)
7723 *adjust = len;
0787a12d
AM		 7724 memcpy (tmpbuf + first, past_reloc, second);
7725 tmpbuf[first + second] = '\0';
f3c180ae
AM		 7726 return tmpbuf;
7727 }
7728
4fa24527
JB		 7729 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7730 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7731 return NULL;
7732 }
7733 }
7734
7735 /* Might be a symbol version string. Don't as_bad here. */
7736 return NULL;
7737}
4e4f7c87 7738#endif
f3c180ae 7739
a988325c
NC		 7740#ifdef TE_PE
7741#ifdef lex_got
7742#undef lex_got
7743#endif
7744/* Parse operands of the form
7745 <symbol>@SECREL32+<nnn>
7746
7747 If we find one, set up the correct relocation in RELOC and copy the
7748 input string, minus the `@SECREL32' into a malloc'd buffer for
7749 parsing by the calling routine. Return this buffer, and if ADJUST
7750 is non-null set it to the length of the string we removed from the
34bca508
L		 7751 input line. Otherwise return NULL.
7752
a988325c
NC		 7753 This function is copied from the ELF version above adjusted for PE targets. */
7754
7755static char *
7756lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7757 int *adjust ATTRIBUTE_UNUSED,
d258b828 7758 i386_operand_type *types)
a988325c
NC		 7759{
7760 static const struct
7761 {
7762 const char *str;
7763 int len;
7764 const enum bfd_reloc_code_real rel[2];
7765 const i386_operand_type types64;
7766 }
7767 gotrel[] =
7768 {
7769 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7770 BFD_RELOC_32_SECREL },
7771 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7772 };
7773
7774 char *cp;
7775 unsigned j;
7776
7777 for (cp = input_line_pointer; *cp != '@'; cp++)
7778 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7779 return NULL;
7780
7781 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7782 {
7783 int len = gotrel[j].len;
7784
7785 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7786 {
7787 if (gotrel[j].rel[object_64bit] != 0)
7788 {
7789 int first, second;
7790 char *tmpbuf, *past_reloc;
7791
7792 *rel = gotrel[j].rel[object_64bit];
7793 if (adjust)
7794 *adjust = len;
7795
7796 if (types)
7797 {
7798 if (flag_code != CODE_64BIT)
7799 {
7800 types->bitfield.imm32 = 1;
7801 types->bitfield.disp32 = 1;
7802 }
7803 else
7804 *types = gotrel[j].types64;
7805 }
7806
7807 /* The length of the first part of our input line. */
7808 first = cp - input_line_pointer;
7809
7810 /* The second part goes from after the reloc token until
7811 (and including) an end_of_line char or comma. */
7812 past_reloc = cp + 1 + len;
7813 cp = past_reloc;
7814 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7815 ++cp;
7816 second = cp + 1 - past_reloc;
7817
7818 /* Allocate and copy string. The trailing NUL shouldn't
7819 be necessary, but be safe. */
add39d23 7820 tmpbuf = XNEWVEC (char, first + second + 2);
a988325c
NC		 7821 memcpy (tmpbuf, input_line_pointer, first);
7822 if (second != 0 && *past_reloc != ' ')
7823 /* Replace the relocation token with ' ', so that
7824 errors like foo@SECLREL321 will be detected. */
7825 tmpbuf[first++] = ' ';
7826 memcpy (tmpbuf + first, past_reloc, second);
7827 tmpbuf[first + second] = '\0';
7828 return tmpbuf;
7829 }
7830
7831 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7832 gotrel[j].str, 1 << (5 + object_64bit));
7833 return NULL;
7834 }
7835 }
7836
7837 /* Might be a symbol version string. Don't as_bad here. */
7838 return NULL;
7839}
7840
7841#endif /* TE_PE */
7842
62ebcb5c 7843bfd_reloc_code_real_type
e3bb37b5 7844x86_cons (expressionS *exp, int size)
f3c180ae 7845{
62ebcb5c
AM		 7846 bfd_reloc_code_real_type got_reloc = NO_RELOC;
7847
ee86248c
JB		 7848 intel_syntax = -intel_syntax;
7849
3c7b9c2c 7850 exp->X_md = 0;
4fa24527 7851 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 7852 {
7853 /* Handle @GOTOFF and the like in an expression. */
7854 char *save;
7855 char *gotfree_input_line;
4a57f2cf 7856 int adjust = 0;
f3c180ae
AM		 7857
7858 save = input_line_pointer;
d258b828 7859 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 7860 if (gotfree_input_line)
7861 input_line_pointer = gotfree_input_line;
7862
7863 expression (exp);
7864
7865 if (gotfree_input_line)
7866 {
7867 /* expression () has merrily parsed up to the end of line,
7868 or a comma - in the wrong buffer. Transfer how far
7869 input_line_pointer has moved to the right buffer. */
7870 input_line_pointer = (save
7871 + (input_line_pointer - gotfree_input_line)
7872 + adjust);
7873 free (gotfree_input_line);
3992d3b7
AM		 7874 if (exp->X_op == O_constant
7875 || exp->X_op == O_absent
7876 || exp->X_op == O_illegal
0398aac5 7877 || exp->X_op == O_register
3992d3b7
AM		 7878 || exp->X_op == O_big)
7879 {
7880 char c = *input_line_pointer;
7881 *input_line_pointer = 0;
7882 as_bad (_("missing or invalid expression `%s'"), save);
7883 *input_line_pointer = c;
7884 }
f3c180ae
AM		 7885 }
7886 }
7887 else
7888 expression (exp);
ee86248c
JB		 7889
7890 intel_syntax = -intel_syntax;
7891
7892 if (intel_syntax)
7893 i386_intel_simplify (exp);
62ebcb5c
AM		 7894
7895 return got_reloc;
f3c180ae 7896}
f3c180ae 7897
9f32dd5b
L		 7898static void
7899signed_cons (int size)
6482c264 7900{
d182319b
JB		 7901 if (flag_code == CODE_64BIT)
7902 cons_sign = 1;
7903 cons (size);
7904 cons_sign = -1;
6482c264
NC		 7905}
7906
d182319b 7907#ifdef TE_PE
6482c264 7908static void
7016a5d5 7909pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 7910{
7911 expressionS exp;
7912
7913 do
7914 {
7915 expression (&exp);
7916 if (exp.X_op == O_symbol)
7917 exp.X_op = O_secrel;
7918
7919 emit_expr (&exp, 4);
7920 }
7921 while (*input_line_pointer++ == ',');
7922
7923 input_line_pointer--;
7924 demand_empty_rest_of_line ();
7925}
6482c264
NC		 7926#endif
7927
43234a1e
L		 7928/* Handle Vector operations. */
7929
7930static char *
7931check_VecOperations (char *op_string, char *op_end)
7932{
7933 const reg_entry *mask;
7934 const char *saved;
7935 char *end_op;
7936
7937 while (*op_string
7938 && (op_end == NULL || op_string < op_end))
7939 {
7940 saved = op_string;
7941 if (*op_string == '{')
7942 {
7943 op_string++;
7944
7945 /* Check broadcasts. */
7946 if (strncmp (op_string, "1to", 3) == 0)
7947 {
7948 int bcst_type;
7949
7950 if (i.broadcast)
7951 goto duplicated_vec_op;
7952
7953 op_string += 3;
7954 if (*op_string == '8')
7955 bcst_type = BROADCAST_1TO8;
b28d1bda
IT		 7956 else if (*op_string == '4')
7957 bcst_type = BROADCAST_1TO4;
7958 else if (*op_string == '2')
7959 bcst_type = BROADCAST_1TO2;
43234a1e
L		 7960 else if (*op_string == '1'
7961 && *(op_string+1) == '6')
7962 {
7963 bcst_type = BROADCAST_1TO16;
7964 op_string++;
7965 }
7966 else
7967 {
7968 as_bad (_("Unsupported broadcast: `%s'"), saved);
7969 return NULL;
7970 }
7971 op_string++;
7972
7973 broadcast_op.type = bcst_type;
7974 broadcast_op.operand = this_operand;
7975 i.broadcast = &broadcast_op;
7976 }
7977 /* Check masking operation. */
7978 else if ((mask = parse_register (op_string, &end_op)) != NULL)
7979 {
7980 /* k0 can't be used for write mask. */
7981 if (mask->reg_num == 0)
7982 {
7983 as_bad (_("`%s' can't be used for write mask"),
7984 op_string);
7985 return NULL;
7986 }
7987
7988 if (!i.mask)
7989 {
7990 mask_op.mask = mask;
7991 mask_op.zeroing = 0;
7992 mask_op.operand = this_operand;
7993 i.mask = &mask_op;
7994 }
7995 else
7996 {
7997 if (i.mask->mask)
7998 goto duplicated_vec_op;
7999
8000 i.mask->mask = mask;
8001
8002 /* Only "{z}" is allowed here. No need to check
8003 zeroing mask explicitly. */
8004 if (i.mask->operand != this_operand)
8005 {
8006 as_bad (_("invalid write mask `%s'"), saved);
8007 return NULL;
8008 }
8009 }
8010
8011 op_string = end_op;
8012 }
8013 /* Check zeroing-flag for masking operation. */
8014 else if (*op_string == 'z')
8015 {
8016 if (!i.mask)
8017 {
8018 mask_op.mask = NULL;
8019 mask_op.zeroing = 1;
8020 mask_op.operand = this_operand;
8021 i.mask = &mask_op;
8022 }
8023 else
8024 {
8025 if (i.mask->zeroing)
8026 {
8027 duplicated_vec_op:
8028 as_bad (_("duplicated `%s'"), saved);
8029 return NULL;
8030 }
8031
8032 i.mask->zeroing = 1;
8033
8034 /* Only "{%k}" is allowed here. No need to check mask
8035 register explicitly. */
8036 if (i.mask->operand != this_operand)
8037 {
8038 as_bad (_("invalid zeroing-masking `%s'"),
8039 saved);
8040 return NULL;
8041 }
8042 }
8043
8044 op_string++;
8045 }
8046 else
8047 goto unknown_vec_op;
8048
8049 if (*op_string != '}')
8050 {
8051 as_bad (_("missing `}' in `%s'"), saved);
8052 return NULL;
8053 }
8054 op_string++;
8055 continue;
8056 }
8057 unknown_vec_op:
8058 /* We don't know this one. */
8059 as_bad (_("unknown vector operation: `%s'"), saved);
8060 return NULL;
8061 }
8062
8063 return op_string;
8064}
8065
252b5132 8066static int
70e41ade 8067i386_immediate (char *imm_start)
252b5132
RH		 8068{
8069 char *save_input_line_pointer;
f3c180ae 8070 char *gotfree_input_line;
252b5132 8071 segT exp_seg = 0;
47926f60 8072 expressionS *exp;
40fb9820
L		 8073 i386_operand_type types;
8074
0dfbf9d7 8075 operand_type_set (&types, ~0);
252b5132
RH		 8076
8077 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8078 {
31b2323c
L		 8079 as_bad (_("at most %d immediate operands are allowed"),
8080 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 8081 return 0;
8082 }
8083
8084 exp = &im_expressions[i.imm_operands++];
520dc8e8 8085 i.op[this_operand].imms = exp;
252b5132
RH		 8086
8087 if (is_space_char (*imm_start))
8088 ++imm_start;
8089
8090 save_input_line_pointer = input_line_pointer;
8091 input_line_pointer = imm_start;
8092
d258b828 8093 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8094 if (gotfree_input_line)
8095 input_line_pointer = gotfree_input_line;
252b5132
RH		 8096
8097 exp_seg = expression (exp);
8098
83183c0c 8099 SKIP_WHITESPACE ();
43234a1e
L		 8100
8101 /* Handle vector operations. */
8102 if (*input_line_pointer == '{')
8103 {
8104 input_line_pointer = check_VecOperations (input_line_pointer,
8105 NULL);
8106 if (input_line_pointer == NULL)
8107 return 0;
8108 }
8109
252b5132 8110 if (*input_line_pointer)
f3c180ae 8111 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 8112
8113 input_line_pointer = save_input_line_pointer;
f3c180ae 8114 if (gotfree_input_line)
ee86248c
JB		 8115 {
8116 free (gotfree_input_line);
8117
8118 if (exp->X_op == O_constant || exp->X_op == O_register)
8119 exp->X_op = O_illegal;
8120 }
8121
8122 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8123}
252b5132 8124
ee86248c
JB		 8125static int
8126i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8127 i386_operand_type types, const char *imm_start)
8128{
8129 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 8130 {
313c53d1
L		 8131 if (imm_start)
8132 as_bad (_("missing or invalid immediate expression `%s'"),
8133 imm_start);
3992d3b7 8134 return 0;
252b5132 8135 }
3e73aa7c 8136 else if (exp->X_op == O_constant)
252b5132 8137 {
47926f60 8138 /* Size it properly later. */
40fb9820 8139 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 8140 /* If not 64bit, sign extend val. */
8141 if (flag_code != CODE_64BIT
4eed87de
AM		 8142 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8143 exp->X_add_number
8144 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 8145 }
4c63da97 8146#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 8147 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 8148 && exp_seg != absolute_section
47926f60 8149 && exp_seg != text_section
24eab124
AM		 8150 && exp_seg != data_section
8151 && exp_seg != bss_section
8152 && exp_seg != undefined_section
f86103b7 8153 && !bfd_is_com_section (exp_seg))
252b5132 8154 {
d0b47220 8155 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 8156 return 0;
8157 }
8158#endif
a841bdf5 8159 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 8160 {
313c53d1
L		 8161 if (imm_start)
8162 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 8163 return 0;
8164 }
252b5132
RH		 8165 else
8166 {
8167 /* This is an address. The size of the address will be
24eab124 8168 determined later, depending on destination register,
3e73aa7c 8169 suffix, or the default for the section. */
40fb9820
L		 8170 i.types[this_operand].bitfield.imm8 = 1;
8171 i.types[this_operand].bitfield.imm16 = 1;
8172 i.types[this_operand].bitfield.imm32 = 1;
8173 i.types[this_operand].bitfield.imm32s = 1;
8174 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8175 i.types[this_operand] = operand_type_and (i.types[this_operand],
8176 types);
252b5132
RH		 8177 }
8178
8179 return 1;
8180}
8181
551c1ca1 8182static char *
e3bb37b5 8183i386_scale (char *scale)
252b5132 8184{
551c1ca1
AM		 8185 offsetT val;
8186 char *save = input_line_pointer;
252b5132 8187
551c1ca1
AM		 8188 input_line_pointer = scale;
8189 val = get_absolute_expression ();
8190
8191 switch (val)
252b5132 8192 {
551c1ca1 8193 case 1:
252b5132
RH		 8194 i.log2_scale_factor = 0;
8195 break;
551c1ca1 8196 case 2:
252b5132
RH		 8197 i.log2_scale_factor = 1;
8198 break;
551c1ca1 8199 case 4:
252b5132
RH		 8200 i.log2_scale_factor = 2;
8201 break;
551c1ca1 8202 case 8:
252b5132
RH		 8203 i.log2_scale_factor = 3;
8204 break;
8205 default:
a724f0f4
JB		 8206 {
8207 char sep = *input_line_pointer;
8208
8209 *input_line_pointer = '\0';
8210 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8211 scale);
8212 *input_line_pointer = sep;
8213 input_line_pointer = save;
8214 return NULL;
8215 }
252b5132 8216 }
29b0f896 8217 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8218 {
8219 as_warn (_("scale factor of %d without an index register"),
24eab124 8220 1 << i.log2_scale_factor);
252b5132 8221 i.log2_scale_factor = 0;
252b5132 8222 }
551c1ca1
AM		 8223 scale = input_line_pointer;
8224 input_line_pointer = save;
8225 return scale;
252b5132
RH		 8226}
8227
252b5132 8228static int
e3bb37b5 8229i386_displacement (char *disp_start, char *disp_end)
252b5132 8230{
29b0f896 8231 expressionS *exp;
252b5132
RH		 8232 segT exp_seg = 0;
8233 char *save_input_line_pointer;
f3c180ae 8234 char *gotfree_input_line;
40fb9820
L		 8235 int override;
8236 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8237 int ret;
252b5132 8238
31b2323c
L		 8239 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8240 {
8241 as_bad (_("at most %d displacement operands are allowed"),
8242 MAX_MEMORY_OPERANDS);
8243 return 0;
8244 }
8245
0dfbf9d7 8246 operand_type_set (&bigdisp, 0);
40fb9820
L		 8247 if ((i.types[this_operand].bitfield.jumpabsolute)
8248 || (!current_templates->start->opcode_modifier.jump
8249 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8250 {
40fb9820 8251 bigdisp.bitfield.disp32 = 1;
e05278af 8252 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8253 if (flag_code == CODE_64BIT)
8254 {
8255 if (!override)
8256 {
8257 bigdisp.bitfield.disp32s = 1;
8258 bigdisp.bitfield.disp64 = 1;
8259 }
8260 }
8261 else if ((flag_code == CODE_16BIT) ^ override)
8262 {
8263 bigdisp.bitfield.disp32 = 0;
8264 bigdisp.bitfield.disp16 = 1;
8265 }
e05278af
JB		 8266 }
8267 else
8268 {
8269 /* For PC-relative branches, the width of the displacement
8270 is dependent upon data size, not address size. */
e05278af 8271 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8272 if (flag_code == CODE_64BIT)
8273 {
8274 if (override || i.suffix == WORD_MNEM_SUFFIX)
8275 bigdisp.bitfield.disp16 = 1;
8276 else
8277 {
8278 bigdisp.bitfield.disp32 = 1;
8279 bigdisp.bitfield.disp32s = 1;
8280 }
8281 }
8282 else
e05278af
JB		 8283 {
8284 if (!override)
8285 override = (i.suffix == (flag_code != CODE_16BIT
8286 ? WORD_MNEM_SUFFIX
8287 : LONG_MNEM_SUFFIX));
40fb9820
L		 8288 bigdisp.bitfield.disp32 = 1;
8289 if ((flag_code == CODE_16BIT) ^ override)
8290 {
8291 bigdisp.bitfield.disp32 = 0;
8292 bigdisp.bitfield.disp16 = 1;
8293 }
e05278af 8294 }
e05278af 8295 }
c6fb90c8
L		 8296 i.types[this_operand] = operand_type_or (i.types[this_operand],
8297 bigdisp);
252b5132
RH		 8298
8299 exp = &disp_expressions[i.disp_operands];
520dc8e8 8300 i.op[this_operand].disps = exp;
252b5132
RH		 8301 i.disp_operands++;
8302 save_input_line_pointer = input_line_pointer;
8303 input_line_pointer = disp_start;
8304 END_STRING_AND_SAVE (disp_end);
8305
8306#ifndef GCC_ASM_O_HACK
8307#define GCC_ASM_O_HACK 0
8308#endif
8309#if GCC_ASM_O_HACK
8310 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8311 if (i.types[this_operand].bitfield.baseIndex
24eab124 8312 && displacement_string_end[-1] == '+')
252b5132
RH		 8313 {
8314 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8315 constraint within gcc asm statements.
8316 For instance:
8317
8318 #define _set_tssldt_desc(n,addr,limit,type) \
8319 __asm__ __volatile__ ( \
8320 "movw %w2,%0\n\t" \
8321 "movw %w1,2+%0\n\t" \
8322 "rorl $16,%1\n\t" \
8323 "movb %b1,4+%0\n\t" \
8324 "movb %4,5+%0\n\t" \
8325 "movb $0,6+%0\n\t" \
8326 "movb %h1,7+%0\n\t" \
8327 "rorl $16,%1" \
8328 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8329
8330 This works great except that the output assembler ends
8331 up looking a bit weird if it turns out that there is
8332 no offset. You end up producing code that looks like:
8333
8334 #APP
8335 movw $235,(%eax)
8336 movw %dx,2+(%eax)
8337 rorl $16,%edx
8338 movb %dl,4+(%eax)
8339 movb $137,5+(%eax)
8340 movb $0,6+(%eax)
8341 movb %dh,7+(%eax)
8342 rorl $16,%edx
8343 #NO_APP
8344
47926f60 8345 So here we provide the missing zero. */
24eab124
AM		 8346
8347 *displacement_string_end = '0';
252b5132
RH		 8348 }
8349#endif
d258b828 8350 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8351 if (gotfree_input_line)
8352 input_line_pointer = gotfree_input_line;
252b5132 8353
24eab124 8354 exp_seg = expression (exp);
252b5132 8355
636c26b0
AM		 8356 SKIP_WHITESPACE ();
8357 if (*input_line_pointer)
8358 as_bad (_("junk `%s' after expression"), input_line_pointer);
8359#if GCC_ASM_O_HACK
8360 RESTORE_END_STRING (disp_end + 1);
8361#endif
636c26b0 8362 input_line_pointer = save_input_line_pointer;
636c26b0 8363 if (gotfree_input_line)
ee86248c
JB		 8364 {
8365 free (gotfree_input_line);
8366
8367 if (exp->X_op == O_constant || exp->X_op == O_register)
8368 exp->X_op = O_illegal;
8369 }
8370
8371 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8372
8373 RESTORE_END_STRING (disp_end);
8374
8375 return ret;
8376}
8377
8378static int
8379i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8380 i386_operand_type types, const char *disp_start)
8381{
8382 i386_operand_type bigdisp;
8383 int ret = 1;
636c26b0 8384
24eab124
AM		 8385 /* We do this to make sure that the section symbol is in
8386 the symbol table. We will ultimately change the relocation
47926f60 8387 to be relative to the beginning of the section. */
1ae12ab7 8388 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8389 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8390 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8391 {
636c26b0 8392 if (exp->X_op != O_symbol)
3992d3b7 8393 goto inv_disp;
636c26b0 8394
e5cb08ac 8395 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8396 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8397 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8398 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8399 exp->X_op = O_subtract;
8400 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8401 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8402 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8403 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8404 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8405 else
29b0f896 8406 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8407 }
252b5132 8408
3992d3b7
AM		 8409 else if (exp->X_op == O_absent
8410 || exp->X_op == O_illegal
ee86248c 8411 || exp->X_op == O_big)
2daf4fd8 8412 {
3992d3b7
AM		 8413 inv_disp:
8414 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8415 disp_start);
3992d3b7 8416 ret = 0;
2daf4fd8
AM		 8417 }
8418
0e1147d9
L		 8419 else if (flag_code == CODE_64BIT
8420 && !i.prefix[ADDR_PREFIX]
8421 && exp->X_op == O_constant)
8422 {
8423 /* Since displacement is signed extended to 64bit, don't allow
8424 disp32 and turn off disp32s if they are out of range. */
8425 i.types[this_operand].bitfield.disp32 = 0;
8426 if (!fits_in_signed_long (exp->X_add_number))
8427 {
8428 i.types[this_operand].bitfield.disp32s = 0;
8429 if (i.types[this_operand].bitfield.baseindex)
8430 {
8431 as_bad (_("0x%lx out range of signed 32bit displacement"),
8432 (long) exp->X_add_number);
8433 ret = 0;
8434 }
8435 }
8436 }
8437
4c63da97 8438#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8439 else if (exp->X_op != O_constant
8440 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8441 && exp_seg != absolute_section
8442 && exp_seg != text_section
8443 && exp_seg != data_section
8444 && exp_seg != bss_section
8445 && exp_seg != undefined_section
8446 && !bfd_is_com_section (exp_seg))
24eab124 8447 {
d0b47220 8448 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8449 ret = 0;
24eab124 8450 }
252b5132 8451#endif
3956db08 8452
40fb9820
L		 8453 /* Check if this is a displacement only operand. */
8454 bigdisp = i.types[this_operand];
8455 bigdisp.bitfield.disp8 = 0;
8456 bigdisp.bitfield.disp16 = 0;
8457 bigdisp.bitfield.disp32 = 0;
8458 bigdisp.bitfield.disp32s = 0;
8459 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8460 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8461 i.types[this_operand] = operand_type_and (i.types[this_operand],
8462 types);
3956db08 8463
3992d3b7 8464 return ret;
252b5132
RH		 8465}
8466
eecb386c 8467/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 8468 Return 1 on success, 0 on a failure. */
8469
252b5132 8470static int
e3bb37b5 8471i386_index_check (const char *operand_string)
252b5132 8472{
fc0763e6 8473 const char *kind = "base/index";
be05d201
L		 8474 enum flag_code addr_mode;
8475
8476 if (i.prefix[ADDR_PREFIX])
8477 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8478 else
8479 {
8480 addr_mode = flag_code;
8481
24eab124 8482#if INFER_ADDR_PREFIX
be05d201
L		 8483 if (i.mem_operands == 0)
8484 {
8485 /* Infer address prefix from the first memory operand. */
8486 const reg_entry *addr_reg = i.base_reg;
8487
8488 if (addr_reg == NULL)
8489 addr_reg = i.index_reg;
eecb386c 8490
be05d201
L		 8491 if (addr_reg)
8492 {
8493 if (addr_reg->reg_num == RegEip
8494 || addr_reg->reg_num == RegEiz
8495 || addr_reg->reg_type.bitfield.reg32)
8496 addr_mode = CODE_32BIT;
8497 else if (flag_code != CODE_64BIT
8498 && addr_reg->reg_type.bitfield.reg16)
8499 addr_mode = CODE_16BIT;
8500
8501 if (addr_mode != flag_code)
8502 {
8503 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8504 i.prefixes += 1;
8505 /* Change the size of any displacement too. At most one
8506 of Disp16 or Disp32 is set.
8507 FIXME. There doesn't seem to be any real need for
8508 separate Disp16 and Disp32 flags. The same goes for
8509 Imm16 and Imm32. Removing them would probably clean
8510 up the code quite a lot. */
8511 if (flag_code != CODE_64BIT
8512 && (i.types[this_operand].bitfield.disp16
8513 || i.types[this_operand].bitfield.disp32))
8514 i.types[this_operand]
8515 = operand_type_xor (i.types[this_operand], disp16_32);
8516 }
8517 }
8518 }
24eab124 8519#endif
be05d201
L		 8520 }
8521
fc0763e6
JB		 8522 if (current_templates->start->opcode_modifier.isstring
8523 && !current_templates->start->opcode_modifier.immext
8524 && (current_templates->end[-1].opcode_modifier.isstring
8525 || i.mem_operands))
8526 {
8527 /* Memory operands of string insns are special in that they only allow
8528 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8529 const reg_entry *expected_reg;
8530 static const char *di_si[][2] =
8531 {
8532 { "esi", "edi" },
8533 { "si", "di" },
8534 { "rsi", "rdi" }
8535 };
8536 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8537
8538 kind = "string address";
8539
8325cc63 8540 if (current_templates->start->opcode_modifier.repprefixok)
fc0763e6
JB		 8541 {
8542 i386_operand_type type = current_templates->end[-1].operand_types[0];
8543
8544 if (!type.bitfield.baseindex
8545 || ((!i.mem_operands != !intel_syntax)
8546 && current_templates->end[-1].operand_types[1]
8547 .bitfield.baseindex))
8548 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8549 expected_reg = hash_find (reg_hash,
8550 di_si[addr_mode][type.bitfield.esseg]);
8551
fc0763e6
JB		 8552 }
8553 else
be05d201 8554 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8555
be05d201
L		 8556 if (i.base_reg != expected_reg
8557 || i.index_reg
fc0763e6 8558 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8559 {
be05d201
L		 8560 /* The second memory operand must have the same size as
8561 the first one. */
8562 if (i.mem_operands
8563 && i.base_reg
8564 && !((addr_mode == CODE_64BIT
8565 && i.base_reg->reg_type.bitfield.reg64)
8566 || (addr_mode == CODE_32BIT
8567 ? i.base_reg->reg_type.bitfield.reg32
8568 : i.base_reg->reg_type.bitfield.reg16)))
8569 goto bad_address;
8570
fc0763e6
JB		 8571 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8572 operand_string,
8573 intel_syntax ? '[' : '(',
8574 register_prefix,
be05d201 8575 expected_reg->reg_name,
fc0763e6 8576 intel_syntax ? ']' : ')');
be05d201 8577 return 1;
fc0763e6 8578 }
be05d201
L		 8579 else
8580 return 1;
8581
8582bad_address:
8583 as_bad (_("`%s' is not a valid %s expression"),
8584 operand_string, kind);
8585 return 0;
3e73aa7c
JH		 8586 }
8587 else
8588 {
be05d201
L		 8589 if (addr_mode != CODE_16BIT)
8590 {
8591 /* 32-bit/64-bit checks. */
8592 if ((i.base_reg
8593 && (addr_mode == CODE_64BIT
8594 ? !i.base_reg->reg_type.bitfield.reg64
8595 : !i.base_reg->reg_type.bitfield.reg32)
8596 && (i.index_reg
8597 || (i.base_reg->reg_num
8598 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8599 || (i.index_reg
8600 && !i.index_reg->reg_type.bitfield.regxmm
8601 && !i.index_reg->reg_type.bitfield.regymm
43234a1e 8602 && !i.index_reg->reg_type.bitfield.regzmm
be05d201
L		 8603 && ((addr_mode == CODE_64BIT
8604 ? !(i.index_reg->reg_type.bitfield.reg64
8605 || i.index_reg->reg_num == RegRiz)
8606 : !(i.index_reg->reg_type.bitfield.reg32
8607 || i.index_reg->reg_num == RegEiz))
8608 || !i.index_reg->reg_type.bitfield.baseindex)))
8609 goto bad_address;
8610 }
8611 else
3e73aa7c 8612 {
be05d201 8613 /* 16-bit checks. */
3e73aa7c 8614 if ((i.base_reg
40fb9820
L		 8615 && (!i.base_reg->reg_type.bitfield.reg16
8616 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8617 || (i.index_reg
40fb9820
L		 8618 && (!i.index_reg->reg_type.bitfield.reg16
8619 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8620 || !(i.base_reg
8621 && i.base_reg->reg_num < 6
8622 && i.index_reg->reg_num >= 6
8623 && i.log2_scale_factor == 0))))
be05d201 8624 goto bad_address;
3e73aa7c
JH		 8625 }
8626 }
be05d201 8627 return 1;
24eab124 8628}
252b5132 8629
43234a1e
L		 8630/* Handle vector immediates. */
8631
8632static int
8633RC_SAE_immediate (const char *imm_start)
8634{
8635 unsigned int match_found, j;
8636 const char *pstr = imm_start;
8637 expressionS *exp;
8638
8639 if (*pstr != '{')
8640 return 0;
8641
8642 pstr++;
8643 match_found = 0;
8644 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8645 {
8646 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8647 {
8648 if (!i.rounding)
8649 {
8650 rc_op.type = RC_NamesTable[j].type;
8651 rc_op.operand = this_operand;
8652 i.rounding = &rc_op;
8653 }
8654 else
8655 {
8656 as_bad (_("duplicated `%s'"), imm_start);
8657 return 0;
8658 }
8659 pstr += RC_NamesTable[j].len;
8660 match_found = 1;
8661 break;
8662 }
8663 }
8664 if (!match_found)
8665 return 0;
8666
8667 if (*pstr++ != '}')
8668 {
8669 as_bad (_("Missing '}': '%s'"), imm_start);
8670 return 0;
8671 }
8672 /* RC/SAE immediate string should contain nothing more. */;
8673 if (*pstr != 0)
8674 {
8675 as_bad (_("Junk after '}': '%s'"), imm_start);
8676 return 0;
8677 }
8678
8679 exp = &im_expressions[i.imm_operands++];
8680 i.op[this_operand].imms = exp;
8681
8682 exp->X_op = O_constant;
8683 exp->X_add_number = 0;
8684 exp->X_add_symbol = (symbolS *) 0;
8685 exp->X_op_symbol = (symbolS *) 0;
8686
8687 i.types[this_operand].bitfield.imm8 = 1;
8688 return 1;
8689}
8690
8325cc63
JB		 8691/* Only string instructions can have a second memory operand, so
8692 reduce current_templates to just those if it contains any. */
8693static int
8694maybe_adjust_templates (void)
8695{
8696 const insn_template *t;
8697
8698 gas_assert (i.mem_operands == 1);
8699
8700 for (t = current_templates->start; t < current_templates->end; ++t)
8701 if (t->opcode_modifier.isstring)
8702 break;
8703
8704 if (t < current_templates->end)
8705 {
8706 static templates aux_templates;
8707 bfd_boolean recheck;
8708
8709 aux_templates.start = t;
8710 for (; t < current_templates->end; ++t)
8711 if (!t->opcode_modifier.isstring)
8712 break;
8713 aux_templates.end = t;
8714
8715 /* Determine whether to re-check the first memory operand. */
8716 recheck = (aux_templates.start != current_templates->start
8717 || t != current_templates->end);
8718
8719 current_templates = &aux_templates;
8720
8721 if (recheck)
8722 {
8723 i.mem_operands = 0;
8724 if (i.memop1_string != NULL
8725 && i386_index_check (i.memop1_string) == 0)
8726 return 0;
8727 i.mem_operands = 1;
8728 }
8729 }
8730
8731 return 1;
8732}
8733
fc0763e6 8734/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8735 on error. */
252b5132 8736
252b5132 8737static int
a7619375 8738i386_att_operand (char *operand_string)
252b5132 8739{
af6bdddf
AM		 8740 const reg_entry *r;
8741 char *end_op;
24eab124 8742 char *op_string = operand_string;
252b5132 8743
24eab124 8744 if (is_space_char (*op_string))
252b5132
RH		 8745 ++op_string;
8746
24eab124 8747 /* We check for an absolute prefix (differentiating,
47926f60 8748 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8749 if (*op_string == ABSOLUTE_PREFIX)
8750 {
8751 ++op_string;
8752 if (is_space_char (*op_string))
8753 ++op_string;
40fb9820 8754 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8755 }
252b5132 8756
47926f60 8757 /* Check if operand is a register. */
4d1bb795 8758 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8759 {
40fb9820
L		 8760 i386_operand_type temp;
8761
24eab124
AM		 8762 /* Check for a segment override by searching for ':' after a
8763 segment register. */
8764 op_string = end_op;
8765 if (is_space_char (*op_string))
8766 ++op_string;
40fb9820
L		 8767 if (*op_string == ':'
8768 && (r->reg_type.bitfield.sreg2
8769 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8770 {
8771 switch (r->reg_num)
8772 {
8773 case 0:
8774 i.seg[i.mem_operands] = &es;
8775 break;
8776 case 1:
8777 i.seg[i.mem_operands] = &cs;
8778 break;
8779 case 2:
8780 i.seg[i.mem_operands] = &ss;
8781 break;
8782 case 3:
8783 i.seg[i.mem_operands] = &ds;
8784 break;
8785 case 4:
8786 i.seg[i.mem_operands] = &fs;
8787 break;
8788 case 5:
8789 i.seg[i.mem_operands] = &gs;
8790 break;
8791 }
252b5132 8792
24eab124 8793 /* Skip the ':' and whitespace. */
252b5132
RH		 8794 ++op_string;
8795 if (is_space_char (*op_string))
24eab124 8796 ++op_string;
252b5132 8797
24eab124
AM		 8798 if (!is_digit_char (*op_string)
8799 && !is_identifier_char (*op_string)
8800 && *op_string != '('
8801 && *op_string != ABSOLUTE_PREFIX)
8802 {
8803 as_bad (_("bad memory operand `%s'"), op_string);
8804 return 0;
8805 }
47926f60 8806 /* Handle case of %es:*foo. */
24eab124
AM		 8807 if (*op_string == ABSOLUTE_PREFIX)
8808 {
8809 ++op_string;
8810 if (is_space_char (*op_string))
8811 ++op_string;
40fb9820 8812 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8813 }
8814 goto do_memory_reference;
8815 }
43234a1e
L		 8816
8817 /* Handle vector operations. */
8818 if (*op_string == '{')
8819 {
8820 op_string = check_VecOperations (op_string, NULL);
8821 if (op_string == NULL)
8822 return 0;
8823 }
8824
24eab124
AM		 8825 if (*op_string)
8826 {
d0b47220 8827 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 8828 return 0;
8829 }
40fb9820
L		 8830 temp = r->reg_type;
8831 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8832 i.types[this_operand] = operand_type_or (i.types[this_operand],
8833 temp);
7d5e4556 8834 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 8835 i.op[this_operand].regs = r;
24eab124
AM		 8836 i.reg_operands++;
8837 }
af6bdddf
AM		 8838 else if (*op_string == REGISTER_PREFIX)
8839 {
8840 as_bad (_("bad register name `%s'"), op_string);
8841 return 0;
8842 }
24eab124 8843 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 8844 {
24eab124 8845 ++op_string;
40fb9820 8846 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 8847 {
d0b47220 8848 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 8849 return 0;
8850 }
8851 if (!i386_immediate (op_string))
8852 return 0;
8853 }
43234a1e
L		 8854 else if (RC_SAE_immediate (operand_string))
8855 {
8856 /* If it is a RC or SAE immediate, do nothing. */
8857 ;
8858 }
24eab124
AM		 8859 else if (is_digit_char (*op_string)
8860 || is_identifier_char (*op_string)
d02603dc 8861 || *op_string == '"'
e5cb08ac 8862 || *op_string == '(')
24eab124 8863 {
47926f60 8864 /* This is a memory reference of some sort. */
af6bdddf 8865 char *base_string;
252b5132 8866
47926f60 8867 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 8868 char *displacement_string_start;
8869 char *displacement_string_end;
43234a1e 8870 char *vop_start;
252b5132 8871
24eab124 8872 do_memory_reference:
8325cc63
JB		 8873 if (i.mem_operands == 1 && !maybe_adjust_templates ())
8874 return 0;
24eab124 8875 if ((i.mem_operands == 1
40fb9820 8876 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 8877 || i.mem_operands == 2)
8878 {
8879 as_bad (_("too many memory references for `%s'"),
8880 current_templates->start->name);
8881 return 0;
8882 }
252b5132 8883
24eab124
AM		 8884 /* Check for base index form. We detect the base index form by
8885 looking for an ')' at the end of the operand, searching
8886 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8887 after the '('. */
af6bdddf 8888 base_string = op_string + strlen (op_string);
c3332e24 8889
43234a1e
L		 8890 /* Handle vector operations. */
8891 vop_start = strchr (op_string, '{');
8892 if (vop_start && vop_start < base_string)
8893 {
8894 if (check_VecOperations (vop_start, base_string) == NULL)
8895 return 0;
8896 base_string = vop_start;
8897 }
8898
af6bdddf
AM		 8899 --base_string;
8900 if (is_space_char (*base_string))
8901 --base_string;
252b5132 8902
47926f60 8903 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 8904 displacement_string_start = op_string;
8905 displacement_string_end = base_string + 1;
252b5132 8906
24eab124
AM		 8907 if (*base_string == ')')
8908 {
af6bdddf 8909 char *temp_string;
24eab124
AM		 8910 unsigned int parens_balanced = 1;
8911 /* We've already checked that the number of left & right ()'s are
47926f60 8912 equal, so this loop will not be infinite. */
24eab124
AM		 8913 do
8914 {
8915 base_string--;
8916 if (*base_string == ')')
8917 parens_balanced++;
8918 if (*base_string == '(')
8919 parens_balanced--;
8920 }
8921 while (parens_balanced);
c3332e24 8922
af6bdddf 8923 temp_string = base_string;
c3332e24 8924
24eab124 8925 /* Skip past '(' and whitespace. */
252b5132
RH		 8926 ++base_string;
8927 if (is_space_char (*base_string))
24eab124 8928 ++base_string;
252b5132 8929
af6bdddf 8930 if (*base_string == ','
4eed87de
AM		 8931 || ((i.base_reg = parse_register (base_string, &end_op))
8932 != NULL))
252b5132 8933 {
af6bdddf 8934 displacement_string_end = temp_string;
252b5132 8935
40fb9820 8936 i.types[this_operand].bitfield.baseindex = 1;
252b5132 8937
af6bdddf 8938 if (i.base_reg)
24eab124 8939 {
24eab124
AM		 8940 base_string = end_op;
8941 if (is_space_char (*base_string))
8942 ++base_string;
af6bdddf
AM		 8943 }
8944
8945 /* There may be an index reg or scale factor here. */
8946 if (*base_string == ',')
8947 {
8948 ++base_string;
8949 if (is_space_char (*base_string))
8950 ++base_string;
8951
4eed87de
AM		 8952 if ((i.index_reg = parse_register (base_string, &end_op))
8953 != NULL)
24eab124 8954 {
af6bdddf 8955 base_string = end_op;
24eab124
AM		 8956 if (is_space_char (*base_string))
8957 ++base_string;
af6bdddf
AM		 8958 if (*base_string == ',')
8959 {
8960 ++base_string;
8961 if (is_space_char (*base_string))
8962 ++base_string;
8963 }
e5cb08ac 8964 else if (*base_string != ')')
af6bdddf 8965 {
4eed87de
AM		 8966 as_bad (_("expecting `,' or `)' "
8967 "after index register in `%s'"),
af6bdddf
AM		 8968 operand_string);
8969 return 0;
8970 }
24eab124 8971 }
af6bdddf 8972 else if (*base_string == REGISTER_PREFIX)
24eab124 8973 {
f76bf5e0
L		 8974 end_op = strchr (base_string, ',');
8975 if (end_op)
8976 *end_op = '\0';
af6bdddf 8977 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 8978 return 0;
8979 }
252b5132 8980
47926f60 8981 /* Check for scale factor. */
551c1ca1 8982 if (*base_string != ')')
af6bdddf 8983 {
551c1ca1
AM		 8984 char *end_scale = i386_scale (base_string);
8985
8986 if (!end_scale)
af6bdddf 8987 return 0;
24eab124 8988
551c1ca1 8989 base_string = end_scale;
af6bdddf
AM		 8990 if (is_space_char (*base_string))
8991 ++base_string;
8992 if (*base_string != ')')
8993 {
4eed87de
AM		 8994 as_bad (_("expecting `)' "
8995 "after scale factor in `%s'"),
af6bdddf
AM		 8996 operand_string);
8997 return 0;
8998 }
8999 }
9000 else if (!i.index_reg)
24eab124 9001 {
4eed87de
AM		 9002 as_bad (_("expecting index register or scale factor "
9003 "after `,'; got '%c'"),
af6bdddf 9004 *base_string);
24eab124
AM		 9005 return 0;
9006 }
9007 }
af6bdddf 9008 else if (*base_string != ')')
24eab124 9009 {
4eed87de
AM		 9010 as_bad (_("expecting `,' or `)' "
9011 "after base register in `%s'"),
af6bdddf 9012 operand_string);
24eab124
AM		 9013 return 0;
9014 }
c3332e24 9015 }
af6bdddf 9016 else if (*base_string == REGISTER_PREFIX)
c3332e24 9017 {
f76bf5e0
L		 9018 end_op = strchr (base_string, ',');
9019 if (end_op)
9020 *end_op = '\0';
af6bdddf 9021 as_bad (_("bad register name `%s'"), base_string);
24eab124 9022 return 0;
c3332e24 9023 }
24eab124
AM		 9024 }
9025
9026 /* If there's an expression beginning the operand, parse it,
9027 assuming displacement_string_start and
9028 displacement_string_end are meaningful. */
9029 if (displacement_string_start != displacement_string_end)
9030 {
9031 if (!i386_displacement (displacement_string_start,
9032 displacement_string_end))
9033 return 0;
9034 }
9035
9036 /* Special case for (%dx) while doing input/output op. */
9037 if (i.base_reg
0dfbf9d7
L		 9038 && operand_type_equal (&i.base_reg->reg_type,
9039 &reg16_inoutportreg)
24eab124
AM		 9040 && i.index_reg == 0
9041 && i.log2_scale_factor == 0
9042 && i.seg[i.mem_operands] == 0
40fb9820 9043 && !operand_type_check (i.types[this_operand], disp))
24eab124 9044 {
65da13b5 9045 i.types[this_operand] = inoutportreg;
24eab124
AM		 9046 return 1;
9047 }
9048
eecb386c
AM		 9049 if (i386_index_check (operand_string) == 0)
9050 return 0;
5c07affc 9051 i.types[this_operand].bitfield.mem = 1;
8325cc63
JB		 9052 if (i.mem_operands == 0)
9053 i.memop1_string = xstrdup (operand_string);
24eab124
AM		 9054 i.mem_operands++;
9055 }
9056 else
ce8a8b2f
AM		 9057 {
9058 /* It's not a memory operand; argh! */
24eab124
AM		 9059 as_bad (_("invalid char %s beginning operand %d `%s'"),
9060 output_invalid (*op_string),
9061 this_operand + 1,
9062 op_string);
9063 return 0;
9064 }
47926f60 9065 return 1; /* Normal return. */
252b5132
RH		 9066}
9067\f
fa94de6b
RM		 9068/* Calculate the maximum variable size (i.e., excluding fr_fix)
9069 that an rs_machine_dependent frag may reach. */
9070
9071unsigned int
9072i386_frag_max_var (fragS *frag)
9073{
9074 /* The only relaxable frags are for jumps.
9075 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9076 gas_assert (frag->fr_type == rs_machine_dependent);
9077 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9078}
9079
b084df0b
L		 9080#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9081static int
8dcea932 9082elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
b084df0b
L		 9083{
9084 /* STT_GNU_IFUNC symbol must go through PLT. */
9085 if ((symbol_get_bfdsym (fr_symbol)->flags
9086 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9087 return 0;
9088
9089 if (!S_IS_EXTERNAL (fr_symbol))
9090 /* Symbol may be weak or local. */
9091 return !S_IS_WEAK (fr_symbol);
9092
8dcea932
L		 9093 /* Global symbols with non-default visibility can't be preempted. */
9094 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9095 return 1;
9096
9097 if (fr_var != NO_RELOC)
9098 switch ((enum bfd_reloc_code_real) fr_var)
9099 {
9100 case BFD_RELOC_386_PLT32:
9101 case BFD_RELOC_X86_64_PLT32:
9102 /* Symbol with PLT relocatin may be preempted. */
9103 return 0;
9104 default:
9105 abort ();
9106 }
9107
b084df0b
L		 9108 /* Global symbols with default visibility in a shared library may be
9109 preempted by another definition. */
8dcea932 9110 return !shared;
b084df0b
L		 9111}
9112#endif
9113
ee7fcc42
AM		 9114/* md_estimate_size_before_relax()
9115
9116 Called just before relax() for rs_machine_dependent frags. The x86
9117 assembler uses these frags to handle variable size jump
9118 instructions.
9119
9120 Any symbol that is now undefined will not become defined.
9121 Return the correct fr_subtype in the frag.
9122 Return the initial "guess for variable size of frag" to caller.
9123 The guess is actually the growth beyond the fixed part. Whatever
9124 we do to grow the fixed or variable part contributes to our
9125 returned value. */
9126
252b5132 9127int
7016a5d5 9128md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 9129{
252b5132 9130 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 9131 check for un-relaxable symbols. On an ELF system, we can't relax
9132 an externally visible symbol, because it may be overridden by a
9133 shared library. */
9134 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 9135#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9136 || (IS_ELF
8dcea932
L		 9137 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9138 fragP->fr_var))
fbeb56a4
DK		 9139#endif
9140#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 9141 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 9142 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 9143#endif
9144 )
252b5132 9145 {
b98ef147
AM		 9146 /* Symbol is undefined in this segment, or we need to keep a
9147 reloc so that weak symbols can be overridden. */
9148 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 9149 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 9150 unsigned char *opcode;
9151 int old_fr_fix;
f6af82bd 9152
ee7fcc42 9153 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 9154 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 9155 else if (size == 2)
f6af82bd
AM		 9156 reloc_type = BFD_RELOC_16_PCREL;
9157 else
9158 reloc_type = BFD_RELOC_32_PCREL;
252b5132 9159
ee7fcc42
AM		 9160 old_fr_fix = fragP->fr_fix;
9161 opcode = (unsigned char *) fragP->fr_opcode;
9162
fddf5b5b 9163 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 9164 {
fddf5b5b
AM		 9165 case UNCOND_JUMP:
9166 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 9167 opcode[0] = 0xe9;
252b5132 9168 fragP->fr_fix += size;
062cd5e7
AS		 9169 fix_new (fragP, old_fr_fix, size,
9170 fragP->fr_symbol,
9171 fragP->fr_offset, 1,
9172 reloc_type);
252b5132
RH		 9173 break;
9174
fddf5b5b 9175 case COND_JUMP86:
412167cb
AM		 9176 if (size == 2
9177 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 9178 {
9179 /* Negate the condition, and branch past an
9180 unconditional jump. */
9181 opcode[0] ^= 1;
9182 opcode[1] = 3;
9183 /* Insert an unconditional jump. */
9184 opcode[2] = 0xe9;
9185 /* We added two extra opcode bytes, and have a two byte
9186 offset. */
9187 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 9188 fix_new (fragP, old_fr_fix + 2, 2,
9189 fragP->fr_symbol,
9190 fragP->fr_offset, 1,
9191 reloc_type);
fddf5b5b
AM		 9192 break;
9193 }
9194 /* Fall through. */
9195
9196 case COND_JUMP:
412167cb
AM		 9197 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9198 {
3e02c1cc
AM		 9199 fixS *fixP;
9200
412167cb 9201 fragP->fr_fix += 1;
3e02c1cc
AM		 9202 fixP = fix_new (fragP, old_fr_fix, 1,
9203 fragP->fr_symbol,
9204 fragP->fr_offset, 1,
9205 BFD_RELOC_8_PCREL);
9206 fixP->fx_signed = 1;
412167cb
AM		 9207 break;
9208 }
93c2a809 9209
24eab124 9210 /* This changes the byte-displacement jump 0x7N
fddf5b5b 9211 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 9212 opcode[1] = opcode[0] + 0x10;
f6af82bd 9213 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 9214 /* We've added an opcode byte. */
9215 fragP->fr_fix += 1 + size;
062cd5e7
AS		 9216 fix_new (fragP, old_fr_fix + 1, size,
9217 fragP->fr_symbol,
9218 fragP->fr_offset, 1,
9219 reloc_type);
252b5132 9220 break;
fddf5b5b
AM		 9221
9222 default:
9223 BAD_CASE (fragP->fr_subtype);
9224 break;
252b5132
RH		 9225 }
9226 frag_wane (fragP);
ee7fcc42 9227 return fragP->fr_fix - old_fr_fix;
252b5132 9228 }
93c2a809 9229
93c2a809
AM		 9230 /* Guess size depending on current relax state. Initially the relax
9231 state will correspond to a short jump and we return 1, because
9232 the variable part of the frag (the branch offset) is one byte
9233 long. However, we can relax a section more than once and in that
9234 case we must either set fr_subtype back to the unrelaxed state,
9235 or return the value for the appropriate branch. */
9236 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 9237}
9238
47926f60
KH		 9239/* Called after relax() is finished.
9240
9241 In: Address of frag.
9242 fr_type == rs_machine_dependent.
9243 fr_subtype is what the address relaxed to.
9244
9245 Out: Any fixSs and constants are set up.
9246 Caller will turn frag into a ".space 0". */
9247
252b5132 9248void
7016a5d5
TG		 9249md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9250 fragS *fragP)
252b5132 9251{
29b0f896 9252 unsigned char *opcode;
252b5132 9253 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9254 offsetT target_address;
9255 offsetT opcode_address;
252b5132 9256 unsigned int extension = 0;
847f7ad4 9257 offsetT displacement_from_opcode_start;
252b5132
RH		 9258
9259 opcode = (unsigned char *) fragP->fr_opcode;
9260
47926f60 9261 /* Address we want to reach in file space. */
252b5132 9262 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9263
47926f60 9264 /* Address opcode resides at in file space. */
252b5132
RH		 9265 opcode_address = fragP->fr_address + fragP->fr_fix;
9266
47926f60 9267 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9268 displacement_from_opcode_start = target_address - opcode_address;
9269
fddf5b5b 9270 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9271 {
47926f60
KH		 9272 /* Don't have to change opcode. */
9273 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9274 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9275 }
9276 else
9277 {
9278 if (no_cond_jump_promotion
9279 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9280 as_warn_where (fragP->fr_file, fragP->fr_line,
9281 _("long jump required"));
252b5132 9282
fddf5b5b
AM		 9283 switch (fragP->fr_subtype)
9284 {
9285 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9286 extension = 4; /* 1 opcode + 4 displacement */
9287 opcode[0] = 0xe9;
9288 where_to_put_displacement = &opcode[1];
9289 break;
252b5132 9290
fddf5b5b
AM		 9291 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9292 extension = 2; /* 1 opcode + 2 displacement */
9293 opcode[0] = 0xe9;
9294 where_to_put_displacement = &opcode[1];
9295 break;
252b5132 9296
fddf5b5b
AM		 9297 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9298 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9299 extension = 5; /* 2 opcode + 4 displacement */
9300 opcode[1] = opcode[0] + 0x10;
9301 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9302 where_to_put_displacement = &opcode[2];
9303 break;
252b5132 9304
fddf5b5b
AM		 9305 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9306 extension = 3; /* 2 opcode + 2 displacement */
9307 opcode[1] = opcode[0] + 0x10;
9308 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9309 where_to_put_displacement = &opcode[2];
9310 break;
252b5132 9311
fddf5b5b
AM		 9312 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9313 extension = 4;
9314 opcode[0] ^= 1;
9315 opcode[1] = 3;
9316 opcode[2] = 0xe9;
9317 where_to_put_displacement = &opcode[3];
9318 break;
9319
9320 default:
9321 BAD_CASE (fragP->fr_subtype);
9322 break;
9323 }
252b5132 9324 }
fddf5b5b 9325
7b81dfbb
AJ		 9326 /* If size if less then four we are sure that the operand fits,
9327 but if it's 4, then it could be that the displacement is larger
9328 then -/+ 2GB. */
9329 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9330 && object_64bit
9331 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9332 + ((addressT) 1 << 31))
9333 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9334 {
9335 as_bad_where (fragP->fr_file, fragP->fr_line,
9336 _("jump target out of range"));
9337 /* Make us emit 0. */
9338 displacement_from_opcode_start = extension;
9339 }
47926f60 9340 /* Now put displacement after opcode. */
252b5132
RH		 9341 md_number_to_chars ((char *) where_to_put_displacement,
9342 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9343 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9344 fragP->fr_fix += extension;
9345}
9346\f
7016a5d5 9347/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9348 by our caller that we have all the info we need to fix it up.
9349
7016a5d5
TG		 9350 Parameter valP is the pointer to the value of the bits.
9351
252b5132
RH		 9352 On the 386, immediates, displacements, and data pointers are all in
9353 the same (little-endian) format, so we don't need to care about which
9354 we are handling. */
9355
94f592af 9356void
7016a5d5 9357md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9358{
94f592af 9359 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9360 valueT value = *valP;
252b5132 9361
f86103b7 9362#if !defined (TE_Mach)
93382f6d
AM		 9363 if (fixP->fx_pcrel)
9364 {
9365 switch (fixP->fx_r_type)
9366 {
5865bb77
ILT		 9367 default:
9368 break;
9369
d6ab8113
JB		 9370 case BFD_RELOC_64:
9371 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9372 break;
93382f6d 9373 case BFD_RELOC_32:
ae8887b5 9374 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9375 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9376 break;
9377 case BFD_RELOC_16:
9378 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9379 break;
9380 case BFD_RELOC_8:
9381 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9382 break;
9383 }
9384 }
252b5132 9385
a161fe53 9386 if (fixP->fx_addsy != NULL
31312f95 9387 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9388 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9389 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 9390 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 9391 && !use_rela_relocations)
252b5132 9392 {
31312f95
AM		 9393 /* This is a hack. There should be a better way to handle this.
9394 This covers for the fact that bfd_install_relocation will
9395 subtract the current location (for partial_inplace, PC relative
9396 relocations); see more below. */
252b5132 9397#ifndef OBJ_AOUT
718ddfc0 9398 if (IS_ELF
252b5132
RH		 9399#ifdef TE_PE
9400 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9401#endif
9402 )
9403 value += fixP->fx_where + fixP->fx_frag->fr_address;
9404#endif
9405#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9406 if (IS_ELF)
252b5132 9407 {
6539b54b 9408 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9409
6539b54b 9410 if ((sym_seg == seg
2f66722d 9411 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9412 && sym_seg != absolute_section))
af65af87 9413 && !generic_force_reloc (fixP))
2f66722d
AM		 9414 {
9415 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9416 bfd_install_relocation subtracts them out again. I think
9417 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9418 it. FIXME. */
9419 value += fixP->fx_where + fixP->fx_frag->fr_address;
9420 }
252b5132
RH		 9421 }
9422#endif
9423#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9424 /* For some reason, the PE format does not store a
9425 section address offset for a PC relative symbol. */
9426 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9427 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9428 value += md_pcrel_from (fixP);
9429#endif
9430 }
fbeb56a4 9431#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9432 if (fixP->fx_addsy != NULL
9433 && S_IS_WEAK (fixP->fx_addsy)
9434 /* PR 16858: Do not modify weak function references. */
9435 && ! fixP->fx_pcrel)
fbeb56a4 9436 {
296a8689
NC		 9437#if !defined (TE_PEP)
9438 /* For x86 PE weak function symbols are neither PC-relative
9439 nor do they set S_IS_FUNCTION. So the only reliable way
9440 to detect them is to check the flags of their containing
9441 section. */
9442 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9443 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9444 ;
9445 else
9446#endif
fbeb56a4
DK		 9447 value -= S_GET_VALUE (fixP->fx_addsy);
9448 }
9449#endif
252b5132
RH		 9450
9451 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9452 and we must not disappoint it. */
252b5132 9453#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9454 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9455 switch (fixP->fx_r_type)
9456 {
9457 case BFD_RELOC_386_PLT32:
3e73aa7c 9458 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 9459 /* Make the jump instruction point to the address of the operand. At
9460 runtime we merely add the offset to the actual PLT entry. */
9461 value = -4;
9462 break;
31312f95 9463
13ae64f3
JJ		 9464 case BFD_RELOC_386_TLS_GD:
9465 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9466 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9467 case BFD_RELOC_386_TLS_IE:
9468 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9469 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9470 case BFD_RELOC_X86_64_TLSGD:
9471 case BFD_RELOC_X86_64_TLSLD:
9472 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9473 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9474 value = 0; /* Fully resolved at runtime. No addend. */
9475 /* Fallthrough */
9476 case BFD_RELOC_386_TLS_LE:
9477 case BFD_RELOC_386_TLS_LDO_32:
9478 case BFD_RELOC_386_TLS_LE_32:
9479 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9480 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9481 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9482 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9483 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9484 break;
9485
67a4f2b7
AO		 9486 case BFD_RELOC_386_TLS_DESC_CALL:
9487 case BFD_RELOC_X86_64_TLSDESC_CALL:
9488 value = 0; /* Fully resolved at runtime. No addend. */
9489 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9490 fixP->fx_done = 0;
9491 return;
9492
47926f60
KH		 9493 case BFD_RELOC_VTABLE_INHERIT:
9494 case BFD_RELOC_VTABLE_ENTRY:
9495 fixP->fx_done = 0;
94f592af 9496 return;
47926f60
KH		 9497
9498 default:
9499 break;
9500 }
9501#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9502 *valP = value;
f86103b7 9503#endif /* !defined (TE_Mach) */
3e73aa7c 9504
3e73aa7c 9505 /* Are we finished with this relocation now? */
c6682705 9506 if (fixP->fx_addsy == NULL)
3e73aa7c 9507 fixP->fx_done = 1;
fbeb56a4
DK		 9508#if defined (OBJ_COFF) && defined (TE_PE)
9509 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9510 {
9511 fixP->fx_done = 0;
9512 /* Remember value for tc_gen_reloc. */
9513 fixP->fx_addnumber = value;
9514 /* Clear out the frag for now. */
9515 value = 0;
9516 }
9517#endif
3e73aa7c
JH		 9518 else if (use_rela_relocations)
9519 {
9520 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9521 /* Remember value for tc_gen_reloc. */
9522 fixP->fx_addnumber = value;
3e73aa7c
JH		 9523 value = 0;
9524 }
f86103b7 9525
94f592af 9526 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9527}
252b5132 9528\f
6d4af3c2 9529const char *
499ac353 9530md_atof (int type, char *litP, int *sizeP)
252b5132 9531{
499ac353
NC		 9532 /* This outputs the LITTLENUMs in REVERSE order;
9533 in accord with the bigendian 386. */
9534 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9535}
9536\f
2d545b82 9537static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9538
252b5132 9539static char *
e3bb37b5 9540output_invalid (int c)
252b5132 9541{
3882b010 9542 if (ISPRINT (c))
f9f21a03
L		 9543 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9544 "'%c'", c);
252b5132 9545 else
f9f21a03 9546 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9547 "(0x%x)", (unsigned char) c);
252b5132
RH		 9548 return output_invalid_buf;
9549}
9550
af6bdddf 9551/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9552
9553static const reg_entry *
4d1bb795 9554parse_real_register (char *reg_string, char **end_op)
252b5132 9555{
af6bdddf
AM		 9556 char *s = reg_string;
9557 char *p;
252b5132
RH		 9558 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9559 const reg_entry *r;
9560
9561 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9562 if (*s == REGISTER_PREFIX)
9563 ++s;
9564
9565 if (is_space_char (*s))
9566 ++s;
9567
9568 p = reg_name_given;
af6bdddf 9569 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9570 {
9571 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9572 return (const reg_entry *) NULL;
9573 s++;
252b5132
RH		 9574 }
9575
6588847e
DN		 9576 /* For naked regs, make sure that we are not dealing with an identifier.
9577 This prevents confusing an identifier like `eax_var' with register
9578 `eax'. */
9579 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9580 return (const reg_entry *) NULL;
9581
af6bdddf 9582 *end_op = s;
252b5132
RH		 9583
9584 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9585
5f47d35b 9586 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9587 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9588 {
5f47d35b
AM		 9589 if (is_space_char (*s))
9590 ++s;
9591 if (*s == '(')
9592 {
af6bdddf 9593 ++s;
5f47d35b
AM		 9594 if (is_space_char (*s))
9595 ++s;
9596 if (*s >= '0' && *s <= '7')
9597 {
db557034 9598 int fpr = *s - '0';
af6bdddf 9599 ++s;
5f47d35b
AM		 9600 if (is_space_char (*s))
9601 ++s;
9602 if (*s == ')')
9603 {
9604 *end_op = s + 1;
1e9cc1c2 9605 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9606 know (r);
9607 return r + fpr;
5f47d35b 9608 }
5f47d35b 9609 }
47926f60 9610 /* We have "%st(" then garbage. */
5f47d35b
AM		 9611 return (const reg_entry *) NULL;
9612 }
9613 }
9614
a60de03c
JB		 9615 if (r == NULL || allow_pseudo_reg)
9616 return r;
9617
0dfbf9d7 9618 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9619 return (const reg_entry *) NULL;
9620
192dc9c6
JB		 9621 if ((r->reg_type.bitfield.reg32
9622 || r->reg_type.bitfield.sreg3
9623 || r->reg_type.bitfield.control
9624 || r->reg_type.bitfield.debug
9625 || r->reg_type.bitfield.test)
9626 && !cpu_arch_flags.bitfield.cpui386)
9627 return (const reg_entry *) NULL;
9628
309d3373
JB		 9629 if (r->reg_type.bitfield.floatreg
9630 && !cpu_arch_flags.bitfield.cpu8087
9631 && !cpu_arch_flags.bitfield.cpu287
9632 && !cpu_arch_flags.bitfield.cpu387)
9633 return (const reg_entry *) NULL;
9634
1848e567 9635 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
192dc9c6
JB		 9636 return (const reg_entry *) NULL;
9637
1848e567 9638 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpuregxmm)
192dc9c6
JB		 9639 return (const reg_entry *) NULL;
9640
1848e567 9641 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuregymm)
40f12533
L		 9642 return (const reg_entry *) NULL;
9643
1848e567
L		 9644 if (r->reg_type.bitfield.regzmm && !cpu_arch_flags.bitfield.cpuregzmm)
9645 return (const reg_entry *) NULL;
9646
9647 if (r->reg_type.bitfield.regmask
9648 && !cpu_arch_flags.bitfield.cpuregmask)
43234a1e
L		 9649 return (const reg_entry *) NULL;
9650
db51cc60 9651 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9652 if (!allow_index_reg
db51cc60
L		 9653 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9654 return (const reg_entry *) NULL;
9655
43234a1e
L		 9656 /* Upper 16 vector register is only available with VREX in 64bit
9657 mode. */
9658 if ((r->reg_flags & RegVRex))
9659 {
9660 if (!cpu_arch_flags.bitfield.cpuvrex
9661 || flag_code != CODE_64BIT)
9662 return (const reg_entry *) NULL;
9663
9664 i.need_vrex = 1;
9665 }
9666
a60de03c
JB		 9667 if (((r->reg_flags & (RegRex64 | RegRex))
9668 || r->reg_type.bitfield.reg64)
40fb9820 9669 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9670 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9671 && flag_code != CODE_64BIT)
20f0a1fc 9672 return (const reg_entry *) NULL;
1ae00879 9673
b7240065
JB		 9674 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9675 return (const reg_entry *) NULL;
9676
252b5132
RH		 9677 return r;
9678}
4d1bb795
JB		 9679
9680/* REG_STRING starts *before* REGISTER_PREFIX. */
9681
9682static const reg_entry *
9683parse_register (char *reg_string, char **end_op)
9684{
9685 const reg_entry *r;
9686
9687 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9688 r = parse_real_register (reg_string, end_op);
9689 else
9690 r = NULL;
9691 if (!r)
9692 {
9693 char *save = input_line_pointer;
9694 char c;
9695 symbolS *symbolP;
9696
9697 input_line_pointer = reg_string;
d02603dc 9698 c = get_symbol_name (&reg_string);
4d1bb795
JB		 9699 symbolP = symbol_find (reg_string);
9700 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9701 {
9702 const expressionS *e = symbol_get_value_expression (symbolP);
9703
0398aac5 9704 know (e->X_op == O_register);
4eed87de 9705 know (e->X_add_number >= 0
c3fe08fa 9706 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 9707 r = i386_regtab + e->X_add_number;
d3bb6b49
IT		 9708 if ((r->reg_flags & RegVRex))
9709 i.need_vrex = 1;
4d1bb795
JB		 9710 *end_op = input_line_pointer;
9711 }
9712 *input_line_pointer = c;
9713 input_line_pointer = save;
9714 }
9715 return r;
9716}
9717
9718int
9719i386_parse_name (char *name, expressionS *e, char *nextcharP)
9720{
9721 const reg_entry *r;
9722 char *end = input_line_pointer;
9723
9724 *end = *nextcharP;
9725 r = parse_register (name, &input_line_pointer);
9726 if (r && end <= input_line_pointer)
9727 {
9728 *nextcharP = *input_line_pointer;
9729 *input_line_pointer = 0;
9730 e->X_op = O_register;
9731 e->X_add_number = r - i386_regtab;
9732 return 1;
9733 }
9734 input_line_pointer = end;
9735 *end = 0;
ee86248c 9736 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9737}
9738
9739void
9740md_operand (expressionS *e)
9741{
ee86248c
JB		 9742 char *end;
9743 const reg_entry *r;
4d1bb795 9744
ee86248c
JB		 9745 switch (*input_line_pointer)
9746 {
9747 case REGISTER_PREFIX:
9748 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9749 if (r)
9750 {
9751 e->X_op = O_register;
9752 e->X_add_number = r - i386_regtab;
9753 input_line_pointer = end;
9754 }
ee86248c
JB		 9755 break;
9756
9757 case '[':
9c2799c2 9758 gas_assert (intel_syntax);
ee86248c
JB		 9759 end = input_line_pointer++;
9760 expression (e);
9761 if (*input_line_pointer == ']')
9762 {
9763 ++input_line_pointer;
9764 e->X_op_symbol = make_expr_symbol (e);
9765 e->X_add_symbol = NULL;
9766 e->X_add_number = 0;
9767 e->X_op = O_index;
9768 }
9769 else
9770 {
9771 e->X_op = O_absent;
9772 input_line_pointer = end;
9773 }
9774 break;
4d1bb795
JB		 9775 }
9776}
9777
252b5132 9778\f
4cc782b5 9779#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9780const char *md_shortopts = "kVQ:sqn";
252b5132 9781#else
12b55ccc 9782const char *md_shortopts = "qn";
252b5132 9783#endif
6e0b89ee 9784
3e73aa7c 9785#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9786#define OPTION_64 (OPTION_MD_BASE + 1)
9787#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9788#define OPTION_MARCH (OPTION_MD_BASE + 3)
9789#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9790#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9791#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9792#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9793#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9794#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9795#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9796#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9797#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9798#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9799#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9800#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9801#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9802#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 9803#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
d1982f93 9804#define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 9805#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
8dcea932 9806#define OPTION_MSHARED (OPTION_MD_BASE + 21)
5db04b09
L		 9807#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9808#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
e4e00185 9809#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
0cb4071e 9810#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
b3b91714 9811
99ad8390
NC		 9812struct option md_longopts[] =
9813{
3e73aa7c 9814 {"32", no_argument, NULL, OPTION_32},
321098a5 9815#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9816 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9817 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 9818#endif
9819#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9820 {"x32", no_argument, NULL, OPTION_X32},
8dcea932 9821 {"mshared", no_argument, NULL, OPTION_MSHARED},
6e0b89ee 9822#endif
b3b91714 9823 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 9824 {"march", required_argument, NULL, OPTION_MARCH},
9825 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 9826 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9827 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9828 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9829 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9830 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 9831 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 9832 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 9833 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 9834 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 9835 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 9836 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9837 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 9838# if defined (TE_PE) || defined (TE_PEP)
9839 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
9840#endif
d1982f93 9841 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
e4e00185 9842 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
0cb4071e 9843 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
d3d3c6db 9844 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
5db04b09
L		 9845 {"mamd64", no_argument, NULL, OPTION_MAMD64},
9846 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
252b5132
RH		 9847 {NULL, no_argument, NULL, 0}
9848};
9849size_t md_longopts_size = sizeof (md_longopts);
9850
9851int
17b9d67d 9852md_parse_option (int c, const char *arg)
252b5132 9853{
91d6fa6a 9854 unsigned int j;
293f5f65 9855 char *arch, *next, *saved;
9103f4f4 9856
252b5132
RH		 9857 switch (c)
9858 {
12b55ccc
L		 9859 case 'n':
9860 optimize_align_code = 0;
9861 break;
9862
a38cf1db
AM		 9863 case 'q':
9864 quiet_warnings = 1;
252b5132
RH		 9865 break;
9866
9867#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 9868 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9869 should be emitted or not. FIXME: Not implemented. */
9870 case 'Q':
252b5132
RH		 9871 break;
9872
9873 /* -V: SVR4 argument to print version ID. */
9874 case 'V':
9875 print_version_id ();
9876 break;
9877
a38cf1db
AM		 9878 /* -k: Ignore for FreeBSD compatibility. */
9879 case 'k':
252b5132 9880 break;
4cc782b5
ILT		 9881
9882 case 's':
9883 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 9884 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 9885 break;
8dcea932
L		 9886
9887 case OPTION_MSHARED:
9888 shared = 1;
9889 break;
99ad8390 9890#endif
321098a5 9891#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9892 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 9893 case OPTION_64:
9894 {
9895 const char **list, **l;
9896
3e73aa7c
JH		 9897 list = bfd_target_list ();
9898 for (l = list; *l != NULL; l++)
8620418b 9899 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 9900 || strcmp (*l, "coff-x86-64") == 0
9901 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 9902 || strcmp (*l, "pei-x86-64") == 0
9903 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 9904 {
9905 default_arch = "x86_64";
9906 break;
9907 }
3e73aa7c 9908 if (*l == NULL)
2b5d6a91 9909 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 9910 free (list);
9911 }
9912 break;
9913#endif
252b5132 9914
351f65ca 9915#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9916 case OPTION_X32:
351f65ca
L		 9917 if (IS_ELF)
9918 {
9919 const char **list, **l;
9920
9921 list = bfd_target_list ();
9922 for (l = list; *l != NULL; l++)
9923 if (CONST_STRNEQ (*l, "elf32-x86-64"))
9924 {
9925 default_arch = "x86_64:32";
9926 break;
9927 }
9928 if (*l == NULL)
2b5d6a91 9929 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 9930 free (list);
9931 }
9932 else
9933 as_fatal (_("32bit x86_64 is only supported for ELF"));
9934 break;
9935#endif
9936
6e0b89ee
AM		 9937 case OPTION_32:
9938 default_arch = "i386";
9939 break;
9940
b3b91714
AM		 9941 case OPTION_DIVIDE:
9942#ifdef SVR4_COMMENT_CHARS
9943 {
9944 char *n, *t;
9945 const char *s;
9946
add39d23 9947 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
b3b91714
AM		 9948 t = n;
9949 for (s = i386_comment_chars; *s != '\0'; s++)
9950 if (*s != '/')
9951 *t++ = *s;
9952 *t = '\0';
9953 i386_comment_chars = n;
9954 }
9955#endif
9956 break;
9957
9103f4f4 9958 case OPTION_MARCH:
293f5f65
L		 9959 saved = xstrdup (arg);
9960 arch = saved;
9961 /* Allow -march=+nosse. */
9962 if (*arch == '+')
9963 arch++;
6305a203 9964 do
9103f4f4 9965 {
6305a203 9966 if (*arch == '.')
2b5d6a91 9967 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9968 next = strchr (arch, '+');
9969 if (next)
9970 *next++ = '\0';
91d6fa6a 9971 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9972 {
91d6fa6a 9973 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 9974 {
6305a203 9975 /* Processor. */
1ded5609
JB		 9976 if (! cpu_arch[j].flags.bitfield.cpui386)
9977 continue;
9978
91d6fa6a 9979 cpu_arch_name = cpu_arch[j].name;
6305a203 9980 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 9981 cpu_arch_flags = cpu_arch[j].flags;
9982 cpu_arch_isa = cpu_arch[j].type;
9983 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 9984 if (!cpu_arch_tune_set)
9985 {
9986 cpu_arch_tune = cpu_arch_isa;
9987 cpu_arch_tune_flags = cpu_arch_isa_flags;
9988 }
9989 break;
9990 }
91d6fa6a
NC		 9991 else if (*cpu_arch [j].name == '.'
9992 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 9993 {
9994 /* ISA entension. */
9995 i386_cpu_flags flags;
309d3373 9996
293f5f65
L		 9997 flags = cpu_flags_or (cpu_arch_flags,
9998 cpu_arch[j].flags);
81486035
L		 9999
10000 if (!valid_iamcu_cpu_flags (&flags))
10001 as_fatal (_("`%s' isn't valid for Intel MCU"), arch);
10002 else if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 10003 {
10004 if (cpu_sub_arch_name)
10005 {
10006 char *name = cpu_sub_arch_name;
10007 cpu_sub_arch_name = concat (name,
91d6fa6a 10008 cpu_arch[j].name,
1bf57e9f 10009 (const char *) NULL);
6305a203
L		 10010 free (name);
10011 }
10012 else
91d6fa6a 10013 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 10014 cpu_arch_flags = flags;
a586129e 10015 cpu_arch_isa_flags = flags;
6305a203
L		 10016 }
10017 break;
ccc9c027 10018 }
9103f4f4 10019 }
6305a203 10020
293f5f65
L		 10021 if (j >= ARRAY_SIZE (cpu_arch))
10022 {
10023 /* Disable an ISA entension. */
10024 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10025 if (strcmp (arch, cpu_noarch [j].name) == 0)
10026 {
10027 i386_cpu_flags flags;
10028
10029 flags = cpu_flags_and_not (cpu_arch_flags,
10030 cpu_noarch[j].flags);
10031 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10032 {
10033 if (cpu_sub_arch_name)
10034 {
10035 char *name = cpu_sub_arch_name;
10036 cpu_sub_arch_name = concat (arch,
10037 (const char *) NULL);
10038 free (name);
10039 }
10040 else
10041 cpu_sub_arch_name = xstrdup (arch);
10042 cpu_arch_flags = flags;
10043 cpu_arch_isa_flags = flags;
10044 }
10045 break;
10046 }
10047
10048 if (j >= ARRAY_SIZE (cpu_noarch))
10049 j = ARRAY_SIZE (cpu_arch);
10050 }
10051
91d6fa6a 10052 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10053 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10054
10055 arch = next;
9103f4f4 10056 }
293f5f65
L		 10057 while (next != NULL);
10058 free (saved);
9103f4f4
L		 10059 break;
10060
10061 case OPTION_MTUNE:
10062 if (*arg == '.')
2b5d6a91 10063 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 10064 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10065 {
91d6fa6a 10066 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 10067 {
ccc9c027 10068 cpu_arch_tune_set = 1;
91d6fa6a
NC		 10069 cpu_arch_tune = cpu_arch [j].type;
10070 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 10071 break;
10072 }
10073 }
91d6fa6a 10074 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10075 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 10076 break;
10077
1efbbeb4
L		 10078 case OPTION_MMNEMONIC:
10079 if (strcasecmp (arg, "att") == 0)
10080 intel_mnemonic = 0;
10081 else if (strcasecmp (arg, "intel") == 0)
10082 intel_mnemonic = 1;
10083 else
2b5d6a91 10084 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 10085 break;
10086
10087 case OPTION_MSYNTAX:
10088 if (strcasecmp (arg, "att") == 0)
10089 intel_syntax = 0;
10090 else if (strcasecmp (arg, "intel") == 0)
10091 intel_syntax = 1;
10092 else
2b5d6a91 10093 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 10094 break;
10095
10096 case OPTION_MINDEX_REG:
10097 allow_index_reg = 1;
10098 break;
10099
10100 case OPTION_MNAKED_REG:
10101 allow_naked_reg = 1;
10102 break;
10103
10104 case OPTION_MOLD_GCC:
10105 old_gcc = 1;
1efbbeb4
L		 10106 break;
10107
c0f3af97
L		 10108 case OPTION_MSSE2AVX:
10109 sse2avx = 1;
10110 break;
10111
daf50ae7
L		 10112 case OPTION_MSSE_CHECK:
10113 if (strcasecmp (arg, "error") == 0)
7bab8ab5 10114 sse_check = check_error;
daf50ae7 10115 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 10116 sse_check = check_warning;
daf50ae7 10117 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 10118 sse_check = check_none;
daf50ae7 10119 else
2b5d6a91 10120 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 10121 break;
10122
7bab8ab5
JB		 10123 case OPTION_MOPERAND_CHECK:
10124 if (strcasecmp (arg, "error") == 0)
10125 operand_check = check_error;
10126 else if (strcasecmp (arg, "warning") == 0)
10127 operand_check = check_warning;
10128 else if (strcasecmp (arg, "none") == 0)
10129 operand_check = check_none;
10130 else
10131 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10132 break;
10133
539f890d
L		 10134 case OPTION_MAVXSCALAR:
10135 if (strcasecmp (arg, "128") == 0)
10136 avxscalar = vex128;
10137 else if (strcasecmp (arg, "256") == 0)
10138 avxscalar = vex256;
10139 else
2b5d6a91 10140 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 10141 break;
10142
7e8b059b
L		 10143 case OPTION_MADD_BND_PREFIX:
10144 add_bnd_prefix = 1;
10145 break;
10146
43234a1e
L		 10147 case OPTION_MEVEXLIG:
10148 if (strcmp (arg, "128") == 0)
10149 evexlig = evexl128;
10150 else if (strcmp (arg, "256") == 0)
10151 evexlig = evexl256;
10152 else if (strcmp (arg, "512") == 0)
10153 evexlig = evexl512;
10154 else
10155 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10156 break;
10157
d3d3c6db
IT		 10158 case OPTION_MEVEXRCIG:
10159 if (strcmp (arg, "rne") == 0)
10160 evexrcig = rne;
10161 else if (strcmp (arg, "rd") == 0)
10162 evexrcig = rd;
10163 else if (strcmp (arg, "ru") == 0)
10164 evexrcig = ru;
10165 else if (strcmp (arg, "rz") == 0)
10166 evexrcig = rz;
10167 else
10168 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10169 break;
10170
43234a1e
L		 10171 case OPTION_MEVEXWIG:
10172 if (strcmp (arg, "0") == 0)
10173 evexwig = evexw0;
10174 else if (strcmp (arg, "1") == 0)
10175 evexwig = evexw1;
10176 else
10177 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10178 break;
10179
167ad85b
TG		 10180# if defined (TE_PE) || defined (TE_PEP)
10181 case OPTION_MBIG_OBJ:
10182 use_big_obj = 1;
10183 break;
10184#endif
10185
d1982f93 10186 case OPTION_MOMIT_LOCK_PREFIX:
d022bddd
IT		 10187 if (strcasecmp (arg, "yes") == 0)
10188 omit_lock_prefix = 1;
10189 else if (strcasecmp (arg, "no") == 0)
10190 omit_lock_prefix = 0;
10191 else
10192 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10193 break;
10194
e4e00185
AS		 10195 case OPTION_MFENCE_AS_LOCK_ADD:
10196 if (strcasecmp (arg, "yes") == 0)
10197 avoid_fence = 1;
10198 else if (strcasecmp (arg, "no") == 0)
10199 avoid_fence = 0;
10200 else
10201 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10202 break;
10203
0cb4071e
L		 10204 case OPTION_MRELAX_RELOCATIONS:
10205 if (strcasecmp (arg, "yes") == 0)
10206 generate_relax_relocations = 1;
10207 else if (strcasecmp (arg, "no") == 0)
10208 generate_relax_relocations = 0;
10209 else
10210 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10211 break;
10212
5db04b09 10213 case OPTION_MAMD64:
e89c5eaa 10214 intel64 = 0;
5db04b09
L		 10215 break;
10216
10217 case OPTION_MINTEL64:
e89c5eaa 10218 intel64 = 1;
5db04b09
L		 10219 break;
10220
252b5132
RH		 10221 default:
10222 return 0;
10223 }
10224 return 1;
10225}
10226
8a2c8fef
L		 10227#define MESSAGE_TEMPLATE \
10228" "
10229
293f5f65
L		 10230static char *
10231output_message (FILE *stream, char *p, char *message, char *start,
10232 int *left_p, const char *name, int len)
10233{
10234 int size = sizeof (MESSAGE_TEMPLATE);
10235 int left = *left_p;
10236
10237 /* Reserve 2 spaces for ", " or ",\0" */
10238 left -= len + 2;
10239
10240 /* Check if there is any room. */
10241 if (left >= 0)
10242 {
10243 if (p != start)
10244 {
10245 *p++ = ',';
10246 *p++ = ' ';
10247 }
10248 p = mempcpy (p, name, len);
10249 }
10250 else
10251 {
10252 /* Output the current message now and start a new one. */
10253 *p++ = ',';
10254 *p = '\0';
10255 fprintf (stream, "%s\n", message);
10256 p = start;
10257 left = size - (start - message) - len - 2;
10258
10259 gas_assert (left >= 0);
10260
10261 p = mempcpy (p, name, len);
10262 }
10263
10264 *left_p = left;
10265 return p;
10266}
10267
8a2c8fef 10268static void
1ded5609 10269show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 10270{
10271 static char message[] = MESSAGE_TEMPLATE;
10272 char *start = message + 27;
10273 char *p;
10274 int size = sizeof (MESSAGE_TEMPLATE);
10275 int left;
10276 const char *name;
10277 int len;
10278 unsigned int j;
10279
10280 p = start;
10281 left = size - (start - message);
10282 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10283 {
10284 /* Should it be skipped? */
10285 if (cpu_arch [j].skip)
10286 continue;
10287
10288 name = cpu_arch [j].name;
10289 len = cpu_arch [j].len;
10290 if (*name == '.')
10291 {
10292 /* It is an extension. Skip if we aren't asked to show it. */
10293 if (ext)
10294 {
10295 name++;
10296 len--;
10297 }
10298 else
10299 continue;
10300 }
10301 else if (ext)
10302 {
10303 /* It is an processor. Skip if we show only extension. */
10304 continue;
10305 }
1ded5609
JB		 10306 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10307 {
10308 /* It is an impossible processor - skip. */
10309 continue;
10310 }
8a2c8fef 10311
293f5f65 10312 p = output_message (stream, p, message, start, &left, name, len);
8a2c8fef
L		 10313 }
10314
293f5f65
L		 10315 /* Display disabled extensions. */
10316 if (ext)
10317 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10318 {
10319 name = cpu_noarch [j].name;
10320 len = cpu_noarch [j].len;
10321 p = output_message (stream, p, message, start, &left, name,
10322 len);
10323 }
10324
8a2c8fef
L		 10325 *p = '\0';
10326 fprintf (stream, "%s\n", message);
10327}
10328
252b5132 10329void
8a2c8fef 10330md_show_usage (FILE *stream)
252b5132 10331{
4cc782b5
ILT		 10332#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10333 fprintf (stream, _("\
a38cf1db
AM		 10334 -Q ignored\n\
10335 -V print assembler version number\n\
b3b91714
AM		 10336 -k ignored\n"));
10337#endif
10338 fprintf (stream, _("\
12b55ccc 10339 -n Do not optimize code alignment\n\
b3b91714
AM		 10340 -q quieten some warnings\n"));
10341#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10342 fprintf (stream, _("\
a38cf1db 10343 -s ignored\n"));
b3b91714 10344#endif
321098a5
L		 10345#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10346 || defined (TE_PE) || defined (TE_PEP))
751d281c 10347 fprintf (stream, _("\
570561f7 10348 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10349#endif
b3b91714
AM		 10350#ifdef SVR4_COMMENT_CHARS
10351 fprintf (stream, _("\
10352 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10353#else
10354 fprintf (stream, _("\
b3b91714 10355 --divide ignored\n"));
4cc782b5 10356#endif
9103f4f4 10357 fprintf (stream, _("\
6305a203 10358 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10359 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10360 show_arch (stream, 0, 1);
8a2c8fef
L		 10361 fprintf (stream, _("\
10362 EXTENSION is combination of:\n"));
1ded5609 10363 show_arch (stream, 1, 0);
6305a203 10364 fprintf (stream, _("\
8a2c8fef 10365 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10366 show_arch (stream, 0, 0);
ba104c83 10367 fprintf (stream, _("\
c0f3af97
L		 10368 -msse2avx encode SSE instructions with VEX prefix\n"));
10369 fprintf (stream, _("\
daf50ae7
L		 10370 -msse-check=[none|error|warning]\n\
10371 check SSE instructions\n"));
10372 fprintf (stream, _("\
7bab8ab5
JB		 10373 -moperand-check=[none|error|warning]\n\
10374 check operand combinations for validity\n"));
10375 fprintf (stream, _("\
539f890d
L		 10376 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10377 length\n"));
10378 fprintf (stream, _("\
43234a1e
L		 10379 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10380 length\n"));
10381 fprintf (stream, _("\
10382 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10383 for EVEX.W bit ignored instructions\n"));
10384 fprintf (stream, _("\
d3d3c6db
IT		 10385 -mevexrcig=[rne|rd|ru|rz]\n\
10386 encode EVEX instructions with specific EVEX.RC value\n\
10387 for SAE-only ignored instructions\n"));
10388 fprintf (stream, _("\
ba104c83
L		 10389 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10390 fprintf (stream, _("\
10391 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10392 fprintf (stream, _("\
10393 -mindex-reg support pseudo index registers\n"));
10394 fprintf (stream, _("\
10395 -mnaked-reg don't require `%%' prefix for registers\n"));
10396 fprintf (stream, _("\
10397 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 10398 fprintf (stream, _("\
10399 -madd-bnd-prefix add BND prefix for all valid branches\n"));
8dcea932
L		 10400 fprintf (stream, _("\
10401 -mshared disable branch optimization for shared code\n"));
167ad85b
TG		 10402# if defined (TE_PE) || defined (TE_PEP)
10403 fprintf (stream, _("\
10404 -mbig-obj generate big object files\n"));
10405#endif
d022bddd
IT		 10406 fprintf (stream, _("\
10407 -momit-lock-prefix=[no|yes]\n\
10408 strip all lock prefixes\n"));
5db04b09 10409 fprintf (stream, _("\
e4e00185
AS		 10410 -mfence-as-lock-add=[no|yes]\n\
10411 encode lfence, mfence and sfence as\n\
10412 lock addl $0x0, (%%{re}sp)\n"));
10413 fprintf (stream, _("\
0cb4071e
L		 10414 -mrelax-relocations=[no|yes]\n\
10415 generate relax relocations\n"));
10416 fprintf (stream, _("\
5db04b09
L		 10417 -mamd64 accept only AMD64 ISA\n"));
10418 fprintf (stream, _("\
10419 -mintel64 accept only Intel64 ISA\n"));
252b5132
RH		 10420}
10421
3e73aa7c 10422#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 10423 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 10424 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 10425
10426/* Pick the target format to use. */
10427
47926f60 10428const char *
e3bb37b5 10429i386_target_format (void)
252b5132 10430{
351f65ca
L		 10431 if (!strncmp (default_arch, "x86_64", 6))
10432 {
10433 update_code_flag (CODE_64BIT, 1);
10434 if (default_arch[6] == '\0')
7f56bc95 10435 x86_elf_abi = X86_64_ABI;
351f65ca 10436 else
7f56bc95 10437 x86_elf_abi = X86_64_X32_ABI;
351f65ca 10438 }
3e73aa7c 10439 else if (!strcmp (default_arch, "i386"))
78f12dd3 10440 update_code_flag (CODE_32BIT, 1);
5197d474
L		 10441 else if (!strcmp (default_arch, "iamcu"))
10442 {
10443 update_code_flag (CODE_32BIT, 1);
10444 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10445 {
10446 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10447 cpu_arch_name = "iamcu";
10448 cpu_sub_arch_name = NULL;
10449 cpu_arch_flags = iamcu_flags;
10450 cpu_arch_isa = PROCESSOR_IAMCU;
10451 cpu_arch_isa_flags = iamcu_flags;
10452 if (!cpu_arch_tune_set)
10453 {
10454 cpu_arch_tune = cpu_arch_isa;
10455 cpu_arch_tune_flags = cpu_arch_isa_flags;
10456 }
10457 }
10458 else
10459 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10460 cpu_arch_name);
10461 }
3e73aa7c 10462 else
2b5d6a91 10463 as_fatal (_("unknown architecture"));
89507696
JB		 10464
10465 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10466 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10467 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10468 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10469
252b5132
RH		 10470 switch (OUTPUT_FLAVOR)
10471 {
9384f2ff 10472#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 10473 case bfd_target_aout_flavour:
47926f60 10474 return AOUT_TARGET_FORMAT;
4c63da97 10475#endif
9384f2ff
AM		 10476#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10477# if defined (TE_PE) || defined (TE_PEP)
10478 case bfd_target_coff_flavour:
167ad85b
TG		 10479 if (flag_code == CODE_64BIT)
10480 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10481 else
10482 return "pe-i386";
9384f2ff 10483# elif defined (TE_GO32)
0561d57c
JK		 10484 case bfd_target_coff_flavour:
10485 return "coff-go32";
9384f2ff 10486# else
252b5132
RH		 10487 case bfd_target_coff_flavour:
10488 return "coff-i386";
9384f2ff 10489# endif
4c63da97 10490#endif
3e73aa7c 10491#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 10492 case bfd_target_elf_flavour:
3e73aa7c 10493 {
351f65ca
L		 10494 const char *format;
10495
10496 switch (x86_elf_abi)
4fa24527 10497 {
351f65ca
L		 10498 default:
10499 format = ELF_TARGET_FORMAT;
10500 break;
7f56bc95 10501 case X86_64_ABI:
351f65ca 10502 use_rela_relocations = 1;
4fa24527 10503 object_64bit = 1;
351f65ca
L		 10504 format = ELF_TARGET_FORMAT64;
10505 break;
7f56bc95 10506 case X86_64_X32_ABI:
4fa24527 10507 use_rela_relocations = 1;
351f65ca 10508 object_64bit = 1;
862be3fb 10509 disallow_64bit_reloc = 1;
351f65ca
L		 10510 format = ELF_TARGET_FORMAT32;
10511 break;
4fa24527 10512 }
3632d14b 10513 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10514 {
7f56bc95 10515 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10516 as_fatal (_("Intel L1OM is 64bit only"));
10517 return ELF_TARGET_L1OM_FORMAT;
10518 }
b49f93f6 10519 else if (cpu_arch_isa == PROCESSOR_K1OM)
7a9068fe
L		 10520 {
10521 if (x86_elf_abi != X86_64_ABI)
10522 as_fatal (_("Intel K1OM is 64bit only"));
10523 return ELF_TARGET_K1OM_FORMAT;
10524 }
81486035
L		 10525 else if (cpu_arch_isa == PROCESSOR_IAMCU)
10526 {
10527 if (x86_elf_abi != I386_ABI)
10528 as_fatal (_("Intel MCU is 32bit only"));
10529 return ELF_TARGET_IAMCU_FORMAT;
10530 }
8a9036a4 10531 else
351f65ca 10532 return format;
3e73aa7c 10533 }
e57f8c65
TG		 10534#endif
10535#if defined (OBJ_MACH_O)
10536 case bfd_target_mach_o_flavour:
d382c579
TG		 10537 if (flag_code == CODE_64BIT)
10538 {
10539 use_rela_relocations = 1;
10540 object_64bit = 1;
10541 return "mach-o-x86-64";
10542 }
10543 else
10544 return "mach-o-i386";
4c63da97 10545#endif
252b5132
RH		 10546 default:
10547 abort ();
10548 return NULL;
10549 }
10550}
10551
47926f60 10552#endif /* OBJ_MAYBE_ more than one */
252b5132 10553\f
252b5132 10554symbolS *
7016a5d5 10555md_undefined_symbol (char *name)
252b5132 10556{
18dc2407
ILT		 10557 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10558 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10559 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10560 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10561 {
10562 if (!GOT_symbol)
10563 {
10564 if (symbol_find (name))
10565 as_bad (_("GOT already in symbol table"));
10566 GOT_symbol = symbol_new (name, undefined_section,
10567 (valueT) 0, &zero_address_frag);
10568 };
10569 return GOT_symbol;
10570 }
252b5132
RH		 10571 return 0;
10572}
10573
10574/* Round up a section size to the appropriate boundary. */
47926f60 10575
252b5132 10576valueT
7016a5d5 10577md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10578{
4c63da97
AM		 10579#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10580 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10581 {
10582 /* For a.out, force the section size to be aligned. If we don't do
10583 this, BFD will align it for us, but it will not write out the
10584 final bytes of the section. This may be a bug in BFD, but it is
10585 easier to fix it here since that is how the other a.out targets
10586 work. */
10587 int align;
10588
10589 align = bfd_get_section_alignment (stdoutput, segment);
8d3842cd 10590 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
4c63da97 10591 }
252b5132
RH		 10592#endif
10593
10594 return size;
10595}
10596
10597/* On the i386, PC-relative offsets are relative to the start of the
10598 next instruction. That is, the address of the offset, plus its
10599 size, since the offset is always the last part of the insn. */
10600
10601long
e3bb37b5 10602md_pcrel_from (fixS *fixP)
252b5132
RH		 10603{
10604 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10605}
10606
10607#ifndef I386COFF
10608
10609static void
e3bb37b5 10610s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10611{
29b0f896 10612 int temp;
252b5132 10613
8a75718c
JB		 10614#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10615 if (IS_ELF)
10616 obj_elf_section_change_hook ();
10617#endif
252b5132
RH		 10618 temp = get_absolute_expression ();
10619 subseg_set (bss_section, (subsegT) temp);
10620 demand_empty_rest_of_line ();
10621}
10622
10623#endif
10624
252b5132 10625void
e3bb37b5 10626i386_validate_fix (fixS *fixp)
252b5132 10627{
02a86693 10628 if (fixp->fx_subsy)
252b5132 10629 {
02a86693 10630 if (fixp->fx_subsy == GOT_symbol)
23df1078 10631 {
02a86693
L		 10632 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10633 {
10634 if (!object_64bit)
10635 abort ();
10636#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10637 if (fixp->fx_tcbit2)
56ceb5b5
L		 10638 fixp->fx_r_type = (fixp->fx_tcbit
10639 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10640 : BFD_RELOC_X86_64_GOTPCRELX);
02a86693
L		 10641 else
10642#endif
10643 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10644 }
d6ab8113 10645 else
02a86693
L		 10646 {
10647 if (!object_64bit)
10648 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10649 else
10650 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
10651 }
10652 fixp->fx_subsy = 0;
23df1078 10653 }
252b5132 10654 }
02a86693
L		 10655#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10656 else if (!object_64bit)
10657 {
10658 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
10659 && fixp->fx_tcbit2)
10660 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
10661 }
10662#endif
252b5132
RH		 10663}
10664
252b5132 10665arelent *
7016a5d5 10666tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10667{
10668 arelent *rel;
10669 bfd_reloc_code_real_type code;
10670
10671 switch (fixp->fx_r_type)
10672 {
8ce3d284 10673#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10674 case BFD_RELOC_SIZE32:
10675 case BFD_RELOC_SIZE64:
10676 if (S_IS_DEFINED (fixp->fx_addsy)
10677 && !S_IS_EXTERNAL (fixp->fx_addsy))
10678 {
10679 /* Resolve size relocation against local symbol to size of
10680 the symbol plus addend. */
10681 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10682 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10683 && !fits_in_unsigned_long (value))
10684 as_bad_where (fixp->fx_file, fixp->fx_line,
10685 _("symbol size computation overflow"));
10686 fixp->fx_addsy = NULL;
10687 fixp->fx_subsy = NULL;
10688 md_apply_fix (fixp, (valueT *) &value, NULL);
10689 return NULL;
10690 }
8ce3d284 10691#endif
8fd4256d 10692
3e73aa7c
JH		 10693 case BFD_RELOC_X86_64_PLT32:
10694 case BFD_RELOC_X86_64_GOT32:
10695 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 10696 case BFD_RELOC_X86_64_GOTPCRELX:
10697 case BFD_RELOC_X86_64_REX_GOTPCRELX:
252b5132
RH		 10698 case BFD_RELOC_386_PLT32:
10699 case BFD_RELOC_386_GOT32:
02a86693 10700 case BFD_RELOC_386_GOT32X:
252b5132
RH		 10701 case BFD_RELOC_386_GOTOFF:
10702 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10703 case BFD_RELOC_386_TLS_GD:
10704 case BFD_RELOC_386_TLS_LDM:
10705 case BFD_RELOC_386_TLS_LDO_32:
10706 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10707 case BFD_RELOC_386_TLS_IE:
10708 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10709 case BFD_RELOC_386_TLS_LE_32:
10710 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10711 case BFD_RELOC_386_TLS_GOTDESC:
10712 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10713 case BFD_RELOC_X86_64_TLSGD:
10714 case BFD_RELOC_X86_64_TLSLD:
10715 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10716 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10717 case BFD_RELOC_X86_64_GOTTPOFF:
10718 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10719 case BFD_RELOC_X86_64_TPOFF64:
10720 case BFD_RELOC_X86_64_GOTOFF64:
10721 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10722 case BFD_RELOC_X86_64_GOT64:
10723 case BFD_RELOC_X86_64_GOTPCREL64:
10724 case BFD_RELOC_X86_64_GOTPC64:
10725 case BFD_RELOC_X86_64_GOTPLT64:
10726 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10727 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10728 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10729 case BFD_RELOC_RVA:
10730 case BFD_RELOC_VTABLE_ENTRY:
10731 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10732#ifdef TE_PE
10733 case BFD_RELOC_32_SECREL:
10734#endif
252b5132
RH		 10735 code = fixp->fx_r_type;
10736 break;
dbbaec26
L		 10737 case BFD_RELOC_X86_64_32S:
10738 if (!fixp->fx_pcrel)
10739 {
10740 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10741 code = fixp->fx_r_type;
10742 break;
10743 }
252b5132 10744 default:
93382f6d 10745 if (fixp->fx_pcrel)
252b5132 10746 {
93382f6d
AM		 10747 switch (fixp->fx_size)
10748 {
10749 default:
b091f402
AM		 10750 as_bad_where (fixp->fx_file, fixp->fx_line,
10751 _("can not do %d byte pc-relative relocation"),
10752 fixp->fx_size);
93382f6d
AM		 10753 code = BFD_RELOC_32_PCREL;
10754 break;
10755 case 1: code = BFD_RELOC_8_PCREL; break;
10756 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 10757 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 10758#ifdef BFD64
10759 case 8: code = BFD_RELOC_64_PCREL; break;
10760#endif
93382f6d
AM		 10761 }
10762 }
10763 else
10764 {
10765 switch (fixp->fx_size)
10766 {
10767 default:
b091f402
AM		 10768 as_bad_where (fixp->fx_file, fixp->fx_line,
10769 _("can not do %d byte relocation"),
10770 fixp->fx_size);
93382f6d
AM		 10771 code = BFD_RELOC_32;
10772 break;
10773 case 1: code = BFD_RELOC_8; break;
10774 case 2: code = BFD_RELOC_16; break;
10775 case 4: code = BFD_RELOC_32; break;
937149dd 10776#ifdef BFD64
3e73aa7c 10777 case 8: code = BFD_RELOC_64; break;
937149dd 10778#endif
93382f6d 10779 }
252b5132
RH		 10780 }
10781 break;
10782 }
252b5132 10783
d182319b
JB		 10784 if ((code == BFD_RELOC_32
10785 || code == BFD_RELOC_32_PCREL
10786 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10787 && GOT_symbol
10788 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10789 {
4fa24527 10790 if (!object_64bit)
d6ab8113
JB		 10791 code = BFD_RELOC_386_GOTPC;
10792 else
10793 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10794 }
7b81dfbb
AJ		 10795 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10796 && GOT_symbol
10797 && fixp->fx_addsy == GOT_symbol)
10798 {
10799 code = BFD_RELOC_X86_64_GOTPC64;
10800 }
252b5132 10801
add39d23
TS		 10802 rel = XNEW (arelent);
10803 rel->sym_ptr_ptr = XNEW (asymbol *);
49309057 10804 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10805
10806 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10807
3e73aa7c
JH		 10808 if (!use_rela_relocations)
10809 {
10810 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10811 vtable entry to be used in the relocation's section offset. */
10812 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10813 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10814#if defined (OBJ_COFF) && defined (TE_PE)
10815 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10816 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10817 else
10818#endif
c6682705 10819 rel->addend = 0;
3e73aa7c
JH		 10820 }
10821 /* Use the rela in 64bit mode. */
252b5132 10822 else
3e73aa7c 10823 {
862be3fb
L		 10824 if (disallow_64bit_reloc)
10825 switch (code)
10826 {
862be3fb
L		 10827 case BFD_RELOC_X86_64_DTPOFF64:
10828 case BFD_RELOC_X86_64_TPOFF64:
10829 case BFD_RELOC_64_PCREL:
10830 case BFD_RELOC_X86_64_GOTOFF64:
10831 case BFD_RELOC_X86_64_GOT64:
10832 case BFD_RELOC_X86_64_GOTPCREL64:
10833 case BFD_RELOC_X86_64_GOTPC64:
10834 case BFD_RELOC_X86_64_GOTPLT64:
10835 case BFD_RELOC_X86_64_PLTOFF64:
10836 as_bad_where (fixp->fx_file, fixp->fx_line,
10837 _("cannot represent relocation type %s in x32 mode"),
10838 bfd_get_reloc_code_name (code));
10839 break;
10840 default:
10841 break;
10842 }
10843
062cd5e7
AS		 10844 if (!fixp->fx_pcrel)
10845 rel->addend = fixp->fx_offset;
10846 else
10847 switch (code)
10848 {
10849 case BFD_RELOC_X86_64_PLT32:
10850 case BFD_RELOC_X86_64_GOT32:
10851 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 10852 case BFD_RELOC_X86_64_GOTPCRELX:
10853 case BFD_RELOC_X86_64_REX_GOTPCRELX:
bffbf940
JJ		 10854 case BFD_RELOC_X86_64_TLSGD:
10855 case BFD_RELOC_X86_64_TLSLD:
10856 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 10857 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10858 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 10859 rel->addend = fixp->fx_offset - fixp->fx_size;
10860 break;
10861 default:
10862 rel->addend = (section->vma
10863 - fixp->fx_size
10864 + fixp->fx_addnumber
10865 + md_pcrel_from (fixp));
10866 break;
10867 }
3e73aa7c
JH		 10868 }
10869
252b5132
RH		 10870 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
10871 if (rel->howto == NULL)
10872 {
10873 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 10874 _("cannot represent relocation type %s"),
252b5132
RH		 10875 bfd_get_reloc_code_name (code));
10876 /* Set howto to a garbage value so that we can keep going. */
10877 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 10878 gas_assert (rel->howto != NULL);
252b5132
RH		 10879 }
10880
10881 return rel;
10882}
10883
ee86248c 10884#include "tc-i386-intel.c"
54cfded0 10885
a60de03c
JB		 10886void
10887tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 10888{
a60de03c
JB		 10889 int saved_naked_reg;
10890 char saved_register_dot;
54cfded0 10891
a60de03c
JB		 10892 saved_naked_reg = allow_naked_reg;
10893 allow_naked_reg = 1;
10894 saved_register_dot = register_chars['.'];
10895 register_chars['.'] = '.';
10896 allow_pseudo_reg = 1;
10897 expression_and_evaluate (exp);
10898 allow_pseudo_reg = 0;
10899 register_chars['.'] = saved_register_dot;
10900 allow_naked_reg = saved_naked_reg;
10901
e96d56a1 10902 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 10903 {
a60de03c
JB		 10904 if ((addressT) exp->X_add_number < i386_regtab_size)
10905 {
10906 exp->X_op = O_constant;
10907 exp->X_add_number = i386_regtab[exp->X_add_number]
10908 .dw2_regnum[flag_code >> 1];
10909 }
10910 else
10911 exp->X_op = O_illegal;
54cfded0 10912 }
54cfded0
AM		 10913}
10914
10915void
10916tc_x86_frame_initial_instructions (void)
10917{
a60de03c
JB		 10918 static unsigned int sp_regno[2];
10919
10920 if (!sp_regno[flag_code >> 1])
10921 {
10922 char *saved_input = input_line_pointer;
10923 char sp[][4] = {"esp", "rsp"};
10924 expressionS exp;
a4447b93 10925
a60de03c
JB		 10926 input_line_pointer = sp[flag_code >> 1];
10927 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 10928 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 10929 sp_regno[flag_code >> 1] = exp.X_add_number;
10930 input_line_pointer = saved_input;
10931 }
a4447b93 10932
61ff971f
L		 10933 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
10934 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 10935}
d2b2c203 10936
d7921315
L		 10937int
10938x86_dwarf2_addr_size (void)
10939{
10940#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10941 if (x86_elf_abi == X86_64_X32_ABI)
10942 return 4;
10943#endif
10944 return bfd_arch_bits_per_address (stdoutput) / 8;
10945}
10946
d2b2c203
DJ		 10947int
10948i386_elf_section_type (const char *str, size_t len)
10949{
10950 if (flag_code == CODE_64BIT
10951 && len == sizeof ("unwind") - 1
10952 && strncmp (str, "unwind", 6) == 0)
10953 return SHT_X86_64_UNWIND;
10954
10955 return -1;
10956}
bb41ade5 10957
ad5fec3b
EB		 10958#ifdef TE_SOLARIS
10959void
10960i386_solaris_fix_up_eh_frame (segT sec)
10961{
10962 if (flag_code == CODE_64BIT)
10963 elf_section_type (sec) = SHT_X86_64_UNWIND;
10964}
10965#endif
10966
bb41ade5
AM		 10967#ifdef TE_PE
10968void
10969tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10970{
91d6fa6a 10971 expressionS exp;
bb41ade5 10972
91d6fa6a
NC		 10973 exp.X_op = O_secrel;
10974 exp.X_add_symbol = symbol;
10975 exp.X_add_number = 0;
10976 emit_expr (&exp, size);
bb41ade5
AM		 10977}
10978#endif
3b22753a
L		 10979
10980#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10981/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10982
01e1a5bc 10983bfd_vma
6d4af3c2 10984x86_64_section_letter (int letter, const char **ptr_msg)
3b22753a
L		 10985{
10986 if (flag_code == CODE_64BIT)
10987 {
10988 if (letter == 'l')
10989 return SHF_X86_64_LARGE;
10990
8f3bae45 10991 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 10992 }
3b22753a 10993 else
8f3bae45 10994 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 10995 return -1;
10996}
10997
01e1a5bc 10998bfd_vma
3b22753a
L		 10999x86_64_section_word (char *str, size_t len)
11000{
8620418b 11001 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 11002 return SHF_X86_64_LARGE;
11003
11004 return -1;
11005}
11006
11007static void
11008handle_large_common (int small ATTRIBUTE_UNUSED)
11009{
11010 if (flag_code != CODE_64BIT)
11011 {
11012 s_comm_internal (0, elf_common_parse);
11013 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11014 }
11015 else
11016 {
11017 static segT lbss_section;
11018 asection *saved_com_section_ptr = elf_com_section_ptr;
11019 asection *saved_bss_section = bss_section;
11020
11021 if (lbss_section == NULL)
11022 {
11023 flagword applicable;
11024 segT seg = now_seg;
11025 subsegT subseg = now_subseg;
11026
11027 /* The .lbss section is for local .largecomm symbols. */
11028 lbss_section = subseg_new (".lbss", 0);
11029 applicable = bfd_applicable_section_flags (stdoutput);
11030 bfd_set_section_flags (stdoutput, lbss_section,
11031 applicable & SEC_ALLOC);
11032 seg_info (lbss_section)->bss = 1;
11033
11034 subseg_set (seg, subseg);
11035 }
11036
11037 elf_com_section_ptr = &_bfd_elf_large_com_section;
11038 bss_section = lbss_section;
11039
11040 s_comm_internal (0, elf_common_parse);
11041
11042 elf_com_section_ptr = saved_com_section_ptr;
11043 bss_section = saved_bss_section;
11044 }
11045}
11046#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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