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[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
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b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
2571583a 2 Copyright (C) 1989-2017 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d 68#define LOCK_PREFIX 5
4e9ac44a
L		 69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 86#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 87/* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89#define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91#define END_OF_INSN '\0'
92
93/*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100typedef struct
101{
d3ce72d0
NC		 102 const insn_template *start;
103 const insn_template *end;
6305a203
L		 104}
105templates;
106
107/* 386 operand encoding bytes: see 386 book for details of this. */
108typedef struct
109{
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113}
114modrm_byte;
115
116/* x86-64 extension prefix. */
117typedef int rex_byte;
118
6305a203
L		 119/* 386 opcode byte to code indirect addressing. */
120typedef struct
121{
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125}
126sib_byte;
127
6305a203
L		 128/* x86 arch names, types and features */
129typedef struct
130{
131 const char *name; /* arch name */
8a2c8fef 132 unsigned int len; /* arch string length */
6305a203
L		 133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 135 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 136}
137arch_entry;
138
293f5f65
L		 139/* Used to turn off indicated flags. */
140typedef struct
141{
142 const char *name; /* arch name */
143 unsigned int len; /* arch string length */
144 i386_cpu_flags flags; /* cpu feature flags */
145}
146noarch_entry;
147
78f12dd3 148static void update_code_flag (int, int);
e3bb37b5
L		 149static void set_code_flag (int);
150static void set_16bit_gcc_code_flag (int);
151static void set_intel_syntax (int);
1efbbeb4 152static void set_intel_mnemonic (int);
db51cc60 153static void set_allow_index_reg (int);
7bab8ab5 154static void set_check (int);
e3bb37b5 155static void set_cpu_arch (int);
6482c264 156#ifdef TE_PE
e3bb37b5 157static void pe_directive_secrel (int);
6482c264 158#endif
e3bb37b5
L		 159static void signed_cons (int);
160static char *output_invalid (int c);
ee86248c
JB		 161static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
162 const char *);
163static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
164 const char *);
a7619375 165static int i386_att_operand (char *);
e3bb37b5 166static int i386_intel_operand (char *, int);
ee86248c
JB		 167static int i386_intel_simplify (expressionS *);
168static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 169static const reg_entry *parse_register (char *, char **);
170static char *parse_insn (char *, char *);
171static char *parse_operands (char *, const char *);
172static void swap_operands (void);
4d456e3d 173static void swap_2_operands (int, int);
e3bb37b5
L		 174static void optimize_imm (void);
175static void optimize_disp (void);
83b16ac6 176static const insn_template *match_template (char);
e3bb37b5
L		 177static int check_string (void);
178static int process_suffix (void);
179static int check_byte_reg (void);
180static int check_long_reg (void);
181static int check_qword_reg (void);
182static int check_word_reg (void);
183static int finalize_imm (void);
184static int process_operands (void);
185static const seg_entry *build_modrm_byte (void);
186static void output_insn (void);
187static void output_imm (fragS *, offsetT);
188static void output_disp (fragS *, offsetT);
29b0f896 189#ifndef I386COFF
e3bb37b5 190static void s_bss (int);
252b5132 191#endif
17d4e2a2
L		 192#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193static void handle_large_common (int small ATTRIBUTE_UNUSED);
194#endif
252b5132 195
a847613f 196static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 197
43234a1e
L		 198/* This struct describes rounding control and SAE in the instruction. */
199struct RC_Operation
200{
201 enum rc_type
202 {
203 rne = 0,
204 rd,
205 ru,
206 rz,
207 saeonly
208 } type;
209 int operand;
210};
211
212static struct RC_Operation rc_op;
213
214/* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217struct Mask_Operation
218{
219 const reg_entry *mask;
220 unsigned int zeroing;
221 /* The operand where this operation is associated. */
222 int operand;
223};
224
225static struct Mask_Operation mask_op;
226
227/* The struct describes broadcasting, applied to OPERAND. FACTOR is
228 broadcast factor. */
229struct Broadcast_Operation
230{
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
232 int type;
233
234 /* Index of broadcasted operand. */
235 int operand;
236};
237
238static struct Broadcast_Operation broadcast_op;
239
c0f3af97
L		 240/* VEX prefix. */
241typedef struct
242{
43234a1e
L		 243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes[4];
c0f3af97
L		 245 unsigned int length;
246 /* Destination or source register specifier. */
247 const reg_entry *register_specifier;
248} vex_prefix;
249
252b5132 250/* 'md_assemble ()' gathers together information and puts it into a
47926f60 251 i386_insn. */
252b5132 252
520dc8e8
AM		 253union i386_op
254 {
255 expressionS *disps;
256 expressionS *imms;
257 const reg_entry *regs;
258 };
259
a65babc9
L		 260enum i386_error
261 {
86e026a4 262 operand_size_mismatch,
a65babc9
L		 263 operand_type_mismatch,
264 register_type_mismatch,
265 number_of_operands_mismatch,
266 invalid_instruction_suffix,
267 bad_imm4,
268 old_gcc_only,
269 unsupported_with_intel_mnemonic,
270 unsupported_syntax,
6c30d220
L		 271 unsupported,
272 invalid_vsib_address,
7bab8ab5 273 invalid_vector_register_set,
43234a1e
L		 274 unsupported_vector_index_register,
275 unsupported_broadcast,
276 broadcast_not_on_src_operand,
277 broadcast_needed,
278 unsupported_masking,
279 mask_not_on_destination,
280 no_default_mask,
281 unsupported_rc_sae,
282 rc_sae_operand_not_last_imm,
283 invalid_register_operand,
284 try_vector_disp8
a65babc9
L		 285 };
286
252b5132
RH		 287struct _i386_insn
288 {
47926f60 289 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 290 insn_template tm;
252b5132 291
7d5e4556
L		 292 /* SUFFIX holds the instruction size suffix for byte, word, dword
293 or qword, if given. */
252b5132
RH		 294 char suffix;
295
47926f60 296 /* OPERANDS gives the number of given operands. */
252b5132
RH		 297 unsigned int operands;
298
299 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
300 of given register, displacement, memory operands and immediate
47926f60 301 operands. */
252b5132
RH		 302 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
303
304 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 305 use OP[i] for the corresponding operand. */
40fb9820 306 i386_operand_type types[MAX_OPERANDS];
252b5132 307
520dc8e8
AM		 308 /* Displacement expression, immediate expression, or register for each
309 operand. */
310 union i386_op op[MAX_OPERANDS];
252b5132 311
3e73aa7c
JH		 312 /* Flags for operands. */
313 unsigned int flags[MAX_OPERANDS];
314#define Operand_PCrel 1
315
252b5132 316 /* Relocation type for operand */
f86103b7 317 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 318
252b5132
RH		 319 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
320 the base index byte below. */
321 const reg_entry *base_reg;
322 const reg_entry *index_reg;
323 unsigned int log2_scale_factor;
324
325 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 326 explicit segment overrides are given. */
ce8a8b2f 327 const seg_entry *seg[2];
252b5132 328
8325cc63
JB		 329 /* Copied first memory operand string, for re-checking. */
330 char *memop1_string;
331
252b5132
RH		 332 /* PREFIX holds all the given prefix opcodes (usually null).
333 PREFIXES is the number of prefix opcodes. */
334 unsigned int prefixes;
335 unsigned char prefix[MAX_PREFIXES];
336
337 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 338 addressing modes of this insn are encoded. */
252b5132 339 modrm_byte rm;
3e73aa7c 340 rex_byte rex;
43234a1e 341 rex_byte vrex;
252b5132 342 sib_byte sib;
c0f3af97 343 vex_prefix vex;
b6169b20 344
43234a1e
L		 345 /* Masking attributes. */
346 struct Mask_Operation *mask;
347
348 /* Rounding control and SAE attributes. */
349 struct RC_Operation *rounding;
350
351 /* Broadcasting attributes. */
352 struct Broadcast_Operation *broadcast;
353
354 /* Compressed disp8*N attribute. */
355 unsigned int memshift;
356
86fa6981
L		 357 /* Prefer load or store in encoding. */
358 enum
359 {
360 dir_encoding_default = 0,
361 dir_encoding_load,
362 dir_encoding_store
363 } dir_encoding;
891edac4 364
a501d77e
L		 365 /* Prefer 8bit or 32bit displacement in encoding. */
366 enum
367 {
368 disp_encoding_default = 0,
369 disp_encoding_8bit,
370 disp_encoding_32bit
371 } disp_encoding;
f8a5c266 372
86fa6981
L		 373 /* How to encode vector instructions. */
374 enum
375 {
376 vex_encoding_default = 0,
377 vex_encoding_vex2,
378 vex_encoding_vex3,
379 vex_encoding_evex
380 } vec_encoding;
381
d5de92cf
L		 382 /* REP prefix. */
383 const char *rep_prefix;
384
165de32a
L		 385 /* HLE prefix. */
386 const char *hle_prefix;
42164a71 387
7e8b059b
L		 388 /* Have BND prefix. */
389 const char *bnd_prefix;
390
04ef582a
L		 391 /* Have NOTRACK prefix. */
392 const char *notrack_prefix;
393
891edac4 394 /* Error message. */
a65babc9 395 enum i386_error error;
252b5132
RH		 396 };
397
398typedef struct _i386_insn i386_insn;
399
43234a1e
L		 400/* Link RC type with corresponding string, that'll be looked for in
401 asm. */
402struct RC_name
403{
404 enum rc_type type;
405 const char *name;
406 unsigned int len;
407};
408
409static const struct RC_name RC_NamesTable[] =
410{
411 { rne, STRING_COMMA_LEN ("rn-sae") },
412 { rd, STRING_COMMA_LEN ("rd-sae") },
413 { ru, STRING_COMMA_LEN ("ru-sae") },
414 { rz, STRING_COMMA_LEN ("rz-sae") },
415 { saeonly, STRING_COMMA_LEN ("sae") },
416};
417
252b5132
RH		 418/* List of chars besides those in app.c:symbol_chars that can start an
419 operand. Used to prevent the scrubber eating vital white-space. */
86fa6981 420const char extra_symbol_chars[] = "*%-([{}"
252b5132 421#ifdef LEX_AT
32137342
NC		 422 "@"
423#endif
424#ifdef LEX_QM
425 "?"
252b5132 426#endif
32137342 427 ;
252b5132 428
29b0f896
AM		 429#if (defined (TE_I386AIX) \
430 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 431 && !defined (TE_GNU) \
29b0f896 432 && !defined (TE_LINUX) \
8d63c93e
RM		 433 && !defined (TE_NACL) \
434 && !defined (TE_NETWARE) \
29b0f896 435 && !defined (TE_FreeBSD) \
5b806d27 436 && !defined (TE_DragonFly) \
29b0f896 437 && !defined (TE_NetBSD)))
252b5132 438/* This array holds the chars that always start a comment. If the
b3b91714
AM		 439 pre-processor is disabled, these aren't very useful. The option
440 --divide will remove '/' from this list. */
441const char *i386_comment_chars = "#/";
442#define SVR4_COMMENT_CHARS 1
252b5132 443#define PREFIX_SEPARATOR '\\'
252b5132 444
b3b91714
AM		 445#else
446const char *i386_comment_chars = "#";
447#define PREFIX_SEPARATOR '/'
448#endif
449
252b5132
RH		 450/* This array holds the chars that only start a comment at the beginning of
451 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 452 .line and .file directives will appear in the pre-processed output.
453 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 454 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 455 #NO_APP at the beginning of its output.
456 Also note that comments started like this one will always work if
252b5132 457 '/' isn't otherwise defined. */
b3b91714 458const char line_comment_chars[] = "#/";
252b5132 459
63a0b638 460const char line_separator_chars[] = ";";
252b5132 461
ce8a8b2f
AM		 462/* Chars that can be used to separate mant from exp in floating point
463 nums. */
252b5132
RH		 464const char EXP_CHARS[] = "eE";
465
ce8a8b2f
AM		 466/* Chars that mean this number is a floating point constant
467 As in 0f12.456
468 or 0d1.2345e12. */
252b5132
RH		 469const char FLT_CHARS[] = "fFdDxX";
470
ce8a8b2f 471/* Tables for lexical analysis. */
252b5132
RH		 472static char mnemonic_chars[256];
473static char register_chars[256];
474static char operand_chars[256];
475static char identifier_chars[256];
476static char digit_chars[256];
477
ce8a8b2f 478/* Lexical macros. */
252b5132
RH		 479#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
480#define is_operand_char(x) (operand_chars[(unsigned char) x])
481#define is_register_char(x) (register_chars[(unsigned char) x])
482#define is_space_char(x) ((x) == ' ')
483#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
484#define is_digit_char(x) (digit_chars[(unsigned char) x])
485
0234cb7c 486/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 487static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
488
489/* md_assemble() always leaves the strings it's passed unaltered. To
490 effect this we maintain a stack of saved characters that we've smashed
491 with '\0's (indicating end of strings for various sub-fields of the
47926f60 492 assembler instruction). */
252b5132 493static char save_stack[32];
ce8a8b2f 494static char *save_stack_p;
252b5132
RH		 495#define END_STRING_AND_SAVE(s) \
496 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
497#define RESTORE_END_STRING(s) \
498 do { *(s) = *--save_stack_p; } while (0)
499
47926f60 500/* The instruction we're assembling. */
252b5132
RH		 501static i386_insn i;
502
503/* Possible templates for current insn. */
504static const templates *current_templates;
505
31b2323c
L		 506/* Per instruction expressionS buffers: max displacements & immediates. */
507static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
508static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 509
47926f60 510/* Current operand we are working on. */
ee86248c 511static int this_operand = -1;
252b5132 512
3e73aa7c
JH		 513/* We support four different modes. FLAG_CODE variable is used to distinguish
514 these. */
515
516enum flag_code {
517 CODE_32BIT,
518 CODE_16BIT,
519 CODE_64BIT };
520
521static enum flag_code flag_code;
4fa24527 522static unsigned int object_64bit;
862be3fb 523static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 524static int use_rela_relocations = 0;
525
7af8ed2d
NC		 526#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
527 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
528 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
529
351f65ca
L		 530/* The ELF ABI to use. */
531enum x86_elf_abi
532{
533 I386_ABI,
7f56bc95
L		 534 X86_64_ABI,
535 X86_64_X32_ABI
351f65ca
L		 536};
537
538static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 539#endif
351f65ca 540
167ad85b
TG		 541#if defined (TE_PE) || defined (TE_PEP)
542/* Use big object file format. */
543static int use_big_obj = 0;
544#endif
545
8dcea932
L		 546#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547/* 1 if generating code for a shared library. */
548static int shared = 0;
549#endif
550
47926f60
KH		 551/* 1 for intel syntax,
552 0 if att syntax. */
553static int intel_syntax = 0;
252b5132 554
e89c5eaa
L		 555/* 1 for Intel64 ISA,
556 0 if AMD64 ISA. */
557static int intel64;
558
1efbbeb4
L		 559/* 1 for intel mnemonic,
560 0 if att mnemonic. */
561static int intel_mnemonic = !SYSV386_COMPAT;
562
5209009a 563/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 564static int old_gcc = OLDGCC_COMPAT;
565
a60de03c
JB		 566/* 1 if pseudo registers are permitted. */
567static int allow_pseudo_reg = 0;
568
47926f60
KH		 569/* 1 if register prefix % not required. */
570static int allow_naked_reg = 0;
252b5132 571
33eaf5de 572/* 1 if the assembler should add BND prefix for all control-transferring
7e8b059b
L		 573 instructions supporting it, even if this prefix wasn't specified
574 explicitly. */
575static int add_bnd_prefix = 0;
576
ba104c83 577/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 578static int allow_index_reg = 0;
579
d022bddd
IT		 580/* 1 if the assembler should ignore LOCK prefix, even if it was
581 specified explicitly. */
582static int omit_lock_prefix = 0;
583
e4e00185
AS		 584/* 1 if the assembler should encode lfence, mfence, and sfence as
585 "lock addl $0, (%{re}sp)". */
586static int avoid_fence = 0;
587
0cb4071e
L		 588/* 1 if the assembler should generate relax relocations. */
589
590static int generate_relax_relocations
591 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
592
7bab8ab5 593static enum check_kind
daf50ae7 594 {
7bab8ab5
JB		 595 check_none = 0,
596 check_warning,
597 check_error
daf50ae7 598 }
7bab8ab5 599sse_check, operand_check = check_warning;
daf50ae7 600
2ca3ace5
L		 601/* Register prefix used for error message. */
602static const char *register_prefix = "%";
603
47926f60
KH		 604/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
605 leave, push, and pop instructions so that gcc has the same stack
606 frame as in 32 bit mode. */
607static char stackop_size = '\0';
eecb386c 608
12b55ccc
L		 609/* Non-zero to optimize code alignment. */
610int optimize_align_code = 1;
611
47926f60
KH		 612/* Non-zero to quieten some warnings. */
613static int quiet_warnings = 0;
a38cf1db 614
47926f60
KH		 615/* CPU name. */
616static const char *cpu_arch_name = NULL;
6305a203 617static char *cpu_sub_arch_name = NULL;
a38cf1db 618
47926f60 619/* CPU feature flags. */
40fb9820
L		 620static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
621
ccc9c027
L		 622/* If we have selected a cpu we are generating instructions for. */
623static int cpu_arch_tune_set = 0;
624
9103f4f4 625/* Cpu we are generating instructions for. */
fbf3f584 626enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 627
628/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 629static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 630
ccc9c027 631/* CPU instruction set architecture used. */
fbf3f584 632enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 633
9103f4f4 634/* CPU feature flags of instruction set architecture used. */
fbf3f584 635i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 636
fddf5b5b
AM		 637/* If set, conditional jumps are not automatically promoted to handle
638 larger than a byte offset. */
639static unsigned int no_cond_jump_promotion = 0;
640
c0f3af97
L		 641/* Encode SSE instructions with VEX prefix. */
642static unsigned int sse2avx;
643
539f890d
L		 644/* Encode scalar AVX instructions with specific vector length. */
645static enum
646 {
647 vex128 = 0,
648 vex256
649 } avxscalar;
650
43234a1e
L		 651/* Encode scalar EVEX LIG instructions with specific vector length. */
652static enum
653 {
654 evexl128 = 0,
655 evexl256,
656 evexl512
657 } evexlig;
658
659/* Encode EVEX WIG instructions with specific evex.w. */
660static enum
661 {
662 evexw0 = 0,
663 evexw1
664 } evexwig;
665
d3d3c6db
IT		 666/* Value to encode in EVEX RC bits, for SAE-only instructions. */
667static enum rc_type evexrcig = rne;
668
29b0f896 669/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 670static symbolS *GOT_symbol;
29b0f896 671
a4447b93
RH		 672/* The dwarf2 return column, adjusted for 32 or 64 bit. */
673unsigned int x86_dwarf2_return_column;
674
675/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
676int x86_cie_data_alignment;
677
252b5132 678/* Interface to relax_segment.
fddf5b5b
AM		 679 There are 3 major relax states for 386 jump insns because the
680 different types of jumps add different sizes to frags when we're
681 figuring out what sort of jump to choose to reach a given label. */
252b5132 682
47926f60 683/* Types. */
93c2a809
AM		 684#define UNCOND_JUMP 0
685#define COND_JUMP 1
686#define COND_JUMP86 2
fddf5b5b 687
47926f60 688/* Sizes. */
252b5132
RH		 689#define CODE16 1
690#define SMALL 0
29b0f896 691#define SMALL16 (SMALL | CODE16)
252b5132 692#define BIG 2
29b0f896 693#define BIG16 (BIG | CODE16)
252b5132
RH		 694
695#ifndef INLINE
696#ifdef __GNUC__
697#define INLINE __inline__
698#else
699#define INLINE
700#endif
701#endif
702
fddf5b5b
AM		 703#define ENCODE_RELAX_STATE(type, size) \
704 ((relax_substateT) (((type) << 2) | (size)))
705#define TYPE_FROM_RELAX_STATE(s) \
706 ((s) >> 2)
707#define DISP_SIZE_FROM_RELAX_STATE(s) \
708 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 709
710/* This table is used by relax_frag to promote short jumps to long
711 ones where necessary. SMALL (short) jumps may be promoted to BIG
712 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
713 don't allow a short jump in a 32 bit code segment to be promoted to
714 a 16 bit offset jump because it's slower (requires data size
715 prefix), and doesn't work, unless the destination is in the bottom
716 64k of the code segment (The top 16 bits of eip are zeroed). */
717
718const relax_typeS md_relax_table[] =
719{
24eab124
AM		 720 /* The fields are:
721 1) most positive reach of this state,
722 2) most negative reach of this state,
93c2a809 723 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 724 4) which index into the table to try if we can't fit into this one. */
252b5132 725
fddf5b5b 726 /* UNCOND_JUMP states. */
93c2a809
AM		 727 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
728 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
729 /* dword jmp adds 4 bytes to frag:
730 0 extra opcode bytes, 4 displacement bytes. */
252b5132 731 {0, 0, 4, 0},
93c2a809
AM		 732 /* word jmp adds 2 byte2 to frag:
733 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 734 {0, 0, 2, 0},
735
93c2a809
AM		 736 /* COND_JUMP states. */
737 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
738 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
739 /* dword conditionals adds 5 bytes to frag:
740 1 extra opcode byte, 4 displacement bytes. */
741 {0, 0, 5, 0},
fddf5b5b 742 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 743 1 extra opcode byte, 2 displacement bytes. */
744 {0, 0, 3, 0},
745
746 /* COND_JUMP86 states. */
747 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
748 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
749 /* dword conditionals adds 5 bytes to frag:
750 1 extra opcode byte, 4 displacement bytes. */
751 {0, 0, 5, 0},
752 /* word conditionals add 4 bytes to frag:
753 1 displacement byte and a 3 byte long branch insn. */
754 {0, 0, 4, 0}
252b5132
RH		 755};
756
9103f4f4
L		 757static const arch_entry cpu_arch[] =
758{
89507696
JB		 759 /* Do not replace the first two entries - i386_target_format()
760 relies on them being there in this order. */
8a2c8fef 761 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
293f5f65 762 CPU_GENERIC32_FLAGS, 0 },
8a2c8fef 763 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
293f5f65 764 CPU_GENERIC64_FLAGS, 0 },
8a2c8fef 765 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
293f5f65 766 CPU_NONE_FLAGS, 0 },
8a2c8fef 767 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
293f5f65 768 CPU_I186_FLAGS, 0 },
8a2c8fef 769 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
293f5f65 770 CPU_I286_FLAGS, 0 },
8a2c8fef 771 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
293f5f65 772 CPU_I386_FLAGS, 0 },
8a2c8fef 773 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
293f5f65 774 CPU_I486_FLAGS, 0 },
8a2c8fef 775 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
293f5f65 776 CPU_I586_FLAGS, 0 },
8a2c8fef 777 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
293f5f65 778 CPU_I686_FLAGS, 0 },
8a2c8fef 779 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
293f5f65 780 CPU_I586_FLAGS, 0 },
8a2c8fef 781 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
293f5f65 782 CPU_PENTIUMPRO_FLAGS, 0 },
8a2c8fef 783 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
293f5f65 784 CPU_P2_FLAGS, 0 },
8a2c8fef 785 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
293f5f65 786 CPU_P3_FLAGS, 0 },
8a2c8fef 787 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
293f5f65 788 CPU_P4_FLAGS, 0 },
8a2c8fef 789 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
293f5f65 790 CPU_CORE_FLAGS, 0 },
8a2c8fef 791 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
293f5f65 792 CPU_NOCONA_FLAGS, 0 },
8a2c8fef 793 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
293f5f65 794 CPU_CORE_FLAGS, 1 },
8a2c8fef 795 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
293f5f65 796 CPU_CORE_FLAGS, 0 },
8a2c8fef 797 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
293f5f65 798 CPU_CORE2_FLAGS, 1 },
8a2c8fef 799 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
293f5f65 800 CPU_CORE2_FLAGS, 0 },
8a2c8fef 801 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
293f5f65 802 CPU_COREI7_FLAGS, 0 },
8a2c8fef 803 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
293f5f65 804 CPU_L1OM_FLAGS, 0 },
7a9068fe 805 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
293f5f65 806 CPU_K1OM_FLAGS, 0 },
81486035 807 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
293f5f65 808 CPU_IAMCU_FLAGS, 0 },
8a2c8fef 809 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
293f5f65 810 CPU_K6_FLAGS, 0 },
8a2c8fef 811 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
293f5f65 812 CPU_K6_2_FLAGS, 0 },
8a2c8fef 813 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
293f5f65 814 CPU_ATHLON_FLAGS, 0 },
8a2c8fef 815 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
293f5f65 816 CPU_K8_FLAGS, 1 },
8a2c8fef 817 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
293f5f65 818 CPU_K8_FLAGS, 0 },
8a2c8fef 819 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
293f5f65 820 CPU_K8_FLAGS, 0 },
8a2c8fef 821 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
293f5f65 822 CPU_AMDFAM10_FLAGS, 0 },
8aedb9fe 823 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
293f5f65 824 CPU_BDVER1_FLAGS, 0 },
8aedb9fe 825 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
293f5f65 826 CPU_BDVER2_FLAGS, 0 },
5e5c50d3 827 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
293f5f65 828 CPU_BDVER3_FLAGS, 0 },
c7b0bd56 829 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
293f5f65 830 CPU_BDVER4_FLAGS, 0 },
029f3522 831 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
293f5f65 832 CPU_ZNVER1_FLAGS, 0 },
7b458c12 833 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
293f5f65 834 CPU_BTVER1_FLAGS, 0 },
7b458c12 835 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
293f5f65 836 CPU_BTVER2_FLAGS, 0 },
8a2c8fef 837 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
293f5f65 838 CPU_8087_FLAGS, 0 },
8a2c8fef 839 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
293f5f65 840 CPU_287_FLAGS, 0 },
8a2c8fef 841 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
293f5f65 842 CPU_387_FLAGS, 0 },
1848e567
L		 843 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
844 CPU_687_FLAGS, 0 },
8a2c8fef 845 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
293f5f65 846 CPU_MMX_FLAGS, 0 },
8a2c8fef 847 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
293f5f65 848 CPU_SSE_FLAGS, 0 },
8a2c8fef 849 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
293f5f65 850 CPU_SSE2_FLAGS, 0 },
8a2c8fef 851 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
293f5f65 852 CPU_SSE3_FLAGS, 0 },
8a2c8fef 853 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
293f5f65 854 CPU_SSSE3_FLAGS, 0 },
8a2c8fef 855 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
293f5f65 856 CPU_SSE4_1_FLAGS, 0 },
8a2c8fef 857 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
293f5f65 858 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 859 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
293f5f65 860 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 861 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
293f5f65 862 CPU_AVX_FLAGS, 0 },
6c30d220 863 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
293f5f65 864 CPU_AVX2_FLAGS, 0 },
43234a1e 865 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
293f5f65 866 CPU_AVX512F_FLAGS, 0 },
43234a1e 867 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
293f5f65 868 CPU_AVX512CD_FLAGS, 0 },
43234a1e 869 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
293f5f65 870 CPU_AVX512ER_FLAGS, 0 },
43234a1e 871 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
293f5f65 872 CPU_AVX512PF_FLAGS, 0 },
1dfc6506 873 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
293f5f65 874 CPU_AVX512DQ_FLAGS, 0 },
1dfc6506 875 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
293f5f65 876 CPU_AVX512BW_FLAGS, 0 },
1dfc6506 877 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
293f5f65 878 CPU_AVX512VL_FLAGS, 0 },
8a2c8fef 879 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
293f5f65 880 CPU_VMX_FLAGS, 0 },
8729a6f6 881 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
293f5f65 882 CPU_VMFUNC_FLAGS, 0 },
8a2c8fef 883 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
293f5f65 884 CPU_SMX_FLAGS, 0 },
8a2c8fef 885 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
293f5f65 886 CPU_XSAVE_FLAGS, 0 },
c7b8aa3a 887 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
293f5f65 888 CPU_XSAVEOPT_FLAGS, 0 },
1dfc6506 889 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
293f5f65 890 CPU_XSAVEC_FLAGS, 0 },
1dfc6506 891 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
293f5f65 892 CPU_XSAVES_FLAGS, 0 },
8a2c8fef 893 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
293f5f65 894 CPU_AES_FLAGS, 0 },
8a2c8fef 895 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
293f5f65 896 CPU_PCLMUL_FLAGS, 0 },
8a2c8fef 897 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
293f5f65 898 CPU_PCLMUL_FLAGS, 1 },
c7b8aa3a 899 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
293f5f65 900 CPU_FSGSBASE_FLAGS, 0 },
c7b8aa3a 901 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
293f5f65 902 CPU_RDRND_FLAGS, 0 },
c7b8aa3a 903 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
293f5f65 904 CPU_F16C_FLAGS, 0 },
6c30d220 905 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
293f5f65 906 CPU_BMI2_FLAGS, 0 },
8a2c8fef 907 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
293f5f65 908 CPU_FMA_FLAGS, 0 },
8a2c8fef 909 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
293f5f65 910 CPU_FMA4_FLAGS, 0 },
8a2c8fef 911 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
293f5f65 912 CPU_XOP_FLAGS, 0 },
8a2c8fef 913 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
293f5f65 914 CPU_LWP_FLAGS, 0 },
8a2c8fef 915 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
293f5f65 916 CPU_MOVBE_FLAGS, 0 },
60aa667e 917 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
293f5f65 918 CPU_CX16_FLAGS, 0 },
8a2c8fef 919 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
293f5f65 920 CPU_EPT_FLAGS, 0 },
6c30d220 921 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
293f5f65 922 CPU_LZCNT_FLAGS, 0 },
42164a71 923 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
293f5f65 924 CPU_HLE_FLAGS, 0 },
42164a71 925 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
293f5f65 926 CPU_RTM_FLAGS, 0 },
6c30d220 927 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
293f5f65 928 CPU_INVPCID_FLAGS, 0 },
8a2c8fef 929 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
293f5f65 930 CPU_CLFLUSH_FLAGS, 0 },
22109423 931 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
293f5f65 932 CPU_NOP_FLAGS, 0 },
8a2c8fef 933 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
293f5f65 934 CPU_SYSCALL_FLAGS, 0 },
8a2c8fef 935 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
293f5f65 936 CPU_RDTSCP_FLAGS, 0 },
8a2c8fef 937 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
293f5f65 938 CPU_3DNOW_FLAGS, 0 },
8a2c8fef 939 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
293f5f65 940 CPU_3DNOWA_FLAGS, 0 },
8a2c8fef 941 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
293f5f65 942 CPU_PADLOCK_FLAGS, 0 },
8a2c8fef 943 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
293f5f65 944 CPU_SVME_FLAGS, 1 },
8a2c8fef 945 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
293f5f65 946 CPU_SVME_FLAGS, 0 },
8a2c8fef 947 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
293f5f65 948 CPU_SSE4A_FLAGS, 0 },
8a2c8fef 949 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
293f5f65 950 CPU_ABM_FLAGS, 0 },
87973e9f 951 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
293f5f65 952 CPU_BMI_FLAGS, 0 },
2a2a0f38 953 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
293f5f65 954 CPU_TBM_FLAGS, 0 },
e2e1fcde 955 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
293f5f65 956 CPU_ADX_FLAGS, 0 },
e2e1fcde 957 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
293f5f65 958 CPU_RDSEED_FLAGS, 0 },
e2e1fcde 959 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
293f5f65 960 CPU_PRFCHW_FLAGS, 0 },
5c111e37 961 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
293f5f65 962 CPU_SMAP_FLAGS, 0 },
7e8b059b 963 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
293f5f65 964 CPU_MPX_FLAGS, 0 },
a0046408 965 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
293f5f65 966 CPU_SHA_FLAGS, 0 },
963f3586 967 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
293f5f65 968 CPU_CLFLUSHOPT_FLAGS, 0 },
dcf893b5 969 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
293f5f65 970 CPU_PREFETCHWT1_FLAGS, 0 },
2cf200a4 971 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
293f5f65 972 CPU_SE1_FLAGS, 0 },
c5e7287a 973 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
293f5f65 974 CPU_CLWB_FLAGS, 0 },
2cc1b5aa 975 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
293f5f65 976 CPU_AVX512IFMA_FLAGS, 0 },
14f195c9 977 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
293f5f65 978 CPU_AVX512VBMI_FLAGS, 0 },
920d2ddc
IT		 979 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
980 CPU_AVX512_4FMAPS_FLAGS, 0 },
47acf0bd
IT		 981 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
982 CPU_AVX512_4VNNIW_FLAGS, 0 },
620214f7
IT		 983 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
984 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
53467f57
IT		 985 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
986 CPU_AVX512_VBMI2_FLAGS, 0 },
8cfcb765
IT		 987 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
988 CPU_AVX512_VNNI_FLAGS, 0 },
029f3522 989 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
293f5f65 990 CPU_CLZERO_FLAGS, 0 },
9916071f 991 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
293f5f65 992 CPU_MWAITX_FLAGS, 0 },
8eab4136 993 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
293f5f65 994 CPU_OSPKE_FLAGS, 0 },
8bc52696 995 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
293f5f65 996 CPU_RDPID_FLAGS, 0 },
6b40c462
L		 997 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
998 CPU_PTWRITE_FLAGS, 0 },
603555e5
L		 999 { STRING_COMMA_LEN (".cet"), PROCESSOR_UNKNOWN,
1000 CPU_CET_FLAGS, 0 },
48521003
IT		 1001 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1002 CPU_GFNI_FLAGS, 0 },
8dcf1fad
IT		 1003 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1004 CPU_VAES_FLAGS, 0 },
ff1982d5
IT		 1005 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1006 CPU_VPCLMULQDQ_FLAGS, 0 },
293f5f65
L		 1007};
1008
1009static const noarch_entry cpu_noarch[] =
1010{
1011 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1848e567
L		 1012 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1013 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1014 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
293f5f65
L		 1015 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1016 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1848e567
L		 1017 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1018 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1019 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1020 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1021 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1022 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
293f5f65 1023 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1848e567 1024 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
144b71e2
L		 1025 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1026 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1027 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1028 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1029 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1030 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1031 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1032 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1033 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
920d2ddc 1034 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
47acf0bd 1035 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
620214f7 1036 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
53467f57 1037 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
8cfcb765 1038 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
e413e4e9
AM		 1039};
1040
704209c0 1041#ifdef I386COFF
a6c24e68
NC		 1042/* Like s_lcomm_internal in gas/read.c but the alignment string
1043 is allowed to be optional. */
1044
1045static symbolS *
1046pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1047{
1048 addressT align = 0;
1049
1050 SKIP_WHITESPACE ();
1051
7ab9ffdd 1052 if (needs_align
a6c24e68
NC		 1053 && *input_line_pointer == ',')
1054 {
1055 align = parse_align (needs_align - 1);
7ab9ffdd 1056
a6c24e68
NC		 1057 if (align == (addressT) -1)
1058 return NULL;
1059 }
1060 else
1061 {
1062 if (size >= 8)
1063 align = 3;
1064 else if (size >= 4)
1065 align = 2;
1066 else if (size >= 2)
1067 align = 1;
1068 else
1069 align = 0;
1070 }
1071
1072 bss_alloc (symbolP, size, align);
1073 return symbolP;
1074}
1075
704209c0 1076static void
a6c24e68
NC		 1077pe_lcomm (int needs_align)
1078{
1079 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1080}
704209c0 1081#endif
a6c24e68 1082
29b0f896
AM		 1083const pseudo_typeS md_pseudo_table[] =
1084{
1085#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1086 {"align", s_align_bytes, 0},
1087#else
1088 {"align", s_align_ptwo, 0},
1089#endif
1090 {"arch", set_cpu_arch, 0},
1091#ifndef I386COFF
1092 {"bss", s_bss, 0},
a6c24e68
NC		 1093#else
1094 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1095#endif
1096 {"ffloat", float_cons, 'f'},
1097 {"dfloat", float_cons, 'd'},
1098 {"tfloat", float_cons, 'x'},
1099 {"value", cons, 2},
d182319b 1100 {"slong", signed_cons, 4},
29b0f896
AM		 1101 {"noopt", s_ignore, 0},
1102 {"optim", s_ignore, 0},
1103 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1104 {"code16", set_code_flag, CODE_16BIT},
1105 {"code32", set_code_flag, CODE_32BIT},
1106 {"code64", set_code_flag, CODE_64BIT},
1107 {"intel_syntax", set_intel_syntax, 1},
1108 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1109 {"intel_mnemonic", set_intel_mnemonic, 1},
1110 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1111 {"allow_index_reg", set_allow_index_reg, 1},
1112 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1113 {"sse_check", set_check, 0},
1114 {"operand_check", set_check, 1},
3b22753a
L		 1115#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1116 {"largecomm", handle_large_common, 0},
07a53e5c 1117#else
e3bb37b5 1118 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 1119 {"loc", dwarf2_directive_loc, 0},
1120 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1121#endif
6482c264
NC		 1122#ifdef TE_PE
1123 {"secrel32", pe_directive_secrel, 0},
1124#endif
29b0f896
AM		 1125 {0, 0, 0}
1126};
1127
1128/* For interface with expression (). */
1129extern char *input_line_pointer;
1130
1131/* Hash table for instruction mnemonic lookup. */
1132static struct hash_control *op_hash;
1133
1134/* Hash table for register lookup. */
1135static struct hash_control *reg_hash;
1136\f
252b5132 1137void
e3bb37b5 1138i386_align_code (fragS *fragP, int count)
252b5132 1139{
ce8a8b2f
AM		 1140 /* Various efficient no-op patterns for aligning code labels.
1141 Note: Don't try to assemble the instructions in the comments.
1142 0L and 0w are not legal. */
bad6e36d 1143 static const unsigned char f32_1[] =
252b5132 1144 {0x90}; /* nop */
bad6e36d 1145 static const unsigned char f32_2[] =
ccc9c027 1146 {0x66,0x90}; /* xchg %ax,%ax */
bad6e36d 1147 static const unsigned char f32_3[] =
252b5132 1148 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
bad6e36d 1149 static const unsigned char f32_4[] =
252b5132 1150 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
bad6e36d 1151 static const unsigned char f32_5[] =
252b5132
RH		 1152 {0x90, /* nop */
1153 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
bad6e36d 1154 static const unsigned char f32_6[] =
252b5132 1155 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
bad6e36d 1156 static const unsigned char f32_7[] =
252b5132 1157 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
bad6e36d 1158 static const unsigned char f32_8[] =
252b5132
RH		 1159 {0x90, /* nop */
1160 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
bad6e36d 1161 static const unsigned char f32_9[] =
252b5132
RH		 1162 {0x89,0xf6, /* movl %esi,%esi */
1163 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1164 static const unsigned char f32_10[] =
252b5132
RH		 1165 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1166 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1167 static const unsigned char f32_11[] =
252b5132
RH		 1168 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1169 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1170 static const unsigned char f32_12[] =
252b5132
RH		 1171 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1172 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
bad6e36d 1173 static const unsigned char f32_13[] =
252b5132
RH		 1174 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1175 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1176 static const unsigned char f32_14[] =
252b5132
RH		 1177 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1178 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1179 static const unsigned char f16_3[] =
c3332e24 1180 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
bad6e36d 1181 static const unsigned char f16_4[] =
252b5132 1182 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
bad6e36d 1183 static const unsigned char f16_5[] =
252b5132
RH		 1184 {0x90, /* nop */
1185 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
bad6e36d 1186 static const unsigned char f16_6[] =
252b5132
RH		 1187 {0x89,0xf6, /* mov %si,%si */
1188 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1189 static const unsigned char f16_7[] =
252b5132
RH		 1190 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1191 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1192 static const unsigned char f16_8[] =
252b5132
RH		 1193 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1194 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1195 static const unsigned char jump_31[] =
76bc74dc
L		 1196 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1197 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1198 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1199 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
bad6e36d 1200 static const unsigned char *const f32_patt[] = {
252b5132 1201 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1202 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132 1203 };
bad6e36d 1204 static const unsigned char *const f16_patt[] = {
76bc74dc 1205 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1206 };
ccc9c027 1207 /* nopl (%[re]ax) */
bad6e36d 1208 static const unsigned char alt_3[] =
ccc9c027
L		 1209 {0x0f,0x1f,0x00};
1210 /* nopl 0(%[re]ax) */
bad6e36d 1211 static const unsigned char alt_4[] =
ccc9c027
L		 1212 {0x0f,0x1f,0x40,0x00};
1213 /* nopl 0(%[re]ax,%[re]ax,1) */
bad6e36d 1214 static const unsigned char alt_5[] =
ccc9c027
L		 1215 {0x0f,0x1f,0x44,0x00,0x00};
1216 /* nopw 0(%[re]ax,%[re]ax,1) */
bad6e36d 1217 static const unsigned char alt_6[] =
ccc9c027
L		 1218 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1219 /* nopl 0L(%[re]ax) */
bad6e36d 1220 static const unsigned char alt_7[] =
ccc9c027
L		 1221 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1222 /* nopl 0L(%[re]ax,%[re]ax,1) */
bad6e36d 1223 static const unsigned char alt_8[] =
ccc9c027
L		 1224 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1225 /* nopw 0L(%[re]ax,%[re]ax,1) */
bad6e36d 1226 static const unsigned char alt_9[] =
ccc9c027
L		 1227 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1228 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
bad6e36d 1229 static const unsigned char alt_10[] =
ccc9c027 1230 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
bad6e36d 1231 static const unsigned char *const alt_patt[] = {
ccc9c027 1232 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
80b8656c 1233 alt_9, alt_10
ccc9c027 1234 };
252b5132 1235
76bc74dc
L		 1236 /* Only align for at least a positive non-zero boundary. */
1237 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1238 return;
3e73aa7c 1239
ccc9c027
L		 1240 /* We need to decide which NOP sequence to use for 32bit and
1241 64bit. When -mtune= is used:
4eed87de 1242
76bc74dc
L		 1243 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1244 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1245 2. For the rest, alt_patt will be used.
1246
1247 When -mtune= isn't used, alt_patt will be used if
22109423 1248 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1249 be used.
ccc9c027
L		 1250
1251 When -march= or .arch is used, we can't use anything beyond
1252 cpu_arch_isa_flags. */
1253
1254 if (flag_code == CODE_16BIT)
1255 {
ccc9c027 1256 if (count > 8)
33fef721 1257 {
76bc74dc
L		 1258 memcpy (fragP->fr_literal + fragP->fr_fix,
1259 jump_31, count);
1260 /* Adjust jump offset. */
1261 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1262 }
76bc74dc
L		 1263 else
1264 memcpy (fragP->fr_literal + fragP->fr_fix,
1265 f16_patt[count - 1], count);
252b5132 1266 }
33fef721 1267 else
ccc9c027 1268 {
bad6e36d 1269 const unsigned char *const *patt = NULL;
ccc9c027 1270
fbf3f584 1271 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1272 {
1273 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1274 switch (cpu_arch_tune)
1275 {
1276 case PROCESSOR_UNKNOWN:
1277 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1278 optimize with nops. */
1279 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1280 patt = alt_patt;
ccc9c027
L		 1281 else
1282 patt = f32_patt;
1283 break;
ccc9c027
L		 1284 case PROCESSOR_PENTIUM4:
1285 case PROCESSOR_NOCONA:
ef05d495 1286 case PROCESSOR_CORE:
76bc74dc 1287 case PROCESSOR_CORE2:
bd5295b2 1288 case PROCESSOR_COREI7:
3632d14b 1289 case PROCESSOR_L1OM:
7a9068fe 1290 case PROCESSOR_K1OM:
76bc74dc 1291 case PROCESSOR_GENERIC64:
ccc9c027
L		 1292 case PROCESSOR_K6:
1293 case PROCESSOR_ATHLON:
1294 case PROCESSOR_K8:
4eed87de 1295 case PROCESSOR_AMDFAM10:
8aedb9fe 1296 case PROCESSOR_BD:
029f3522 1297 case PROCESSOR_ZNVER:
7b458c12 1298 case PROCESSOR_BT:
80b8656c 1299 patt = alt_patt;
ccc9c027 1300 break;
76bc74dc 1301 case PROCESSOR_I386:
ccc9c027
L		 1302 case PROCESSOR_I486:
1303 case PROCESSOR_PENTIUM:
2dde1948 1304 case PROCESSOR_PENTIUMPRO:
81486035 1305 case PROCESSOR_IAMCU:
ccc9c027
L		 1306 case PROCESSOR_GENERIC32:
1307 patt = f32_patt;
1308 break;
4eed87de 1309 }
ccc9c027
L		 1310 }
1311 else
1312 {
fbf3f584 1313 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1314 {
1315 case PROCESSOR_UNKNOWN:
e6a14101 1316 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1317 PROCESSOR_UNKNOWN. */
1318 abort ();
1319 break;
1320
76bc74dc 1321 case PROCESSOR_I386:
ccc9c027
L		 1322 case PROCESSOR_I486:
1323 case PROCESSOR_PENTIUM:
81486035 1324 case PROCESSOR_IAMCU:
ccc9c027
L		 1325 case PROCESSOR_K6:
1326 case PROCESSOR_ATHLON:
1327 case PROCESSOR_K8:
4eed87de 1328 case PROCESSOR_AMDFAM10:
8aedb9fe 1329 case PROCESSOR_BD:
029f3522 1330 case PROCESSOR_ZNVER:
7b458c12 1331 case PROCESSOR_BT:
ccc9c027
L		 1332 case PROCESSOR_GENERIC32:
1333 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1334 with nops. */
1335 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1336 patt = alt_patt;
ccc9c027
L		 1337 else
1338 patt = f32_patt;
1339 break;
76bc74dc
L		 1340 case PROCESSOR_PENTIUMPRO:
1341 case PROCESSOR_PENTIUM4:
1342 case PROCESSOR_NOCONA:
1343 case PROCESSOR_CORE:
ef05d495 1344 case PROCESSOR_CORE2:
bd5295b2 1345 case PROCESSOR_COREI7:
3632d14b 1346 case PROCESSOR_L1OM:
7a9068fe 1347 case PROCESSOR_K1OM:
22109423 1348 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1349 patt = alt_patt;
ccc9c027
L		 1350 else
1351 patt = f32_patt;
1352 break;
1353 case PROCESSOR_GENERIC64:
80b8656c 1354 patt = alt_patt;
ccc9c027 1355 break;
4eed87de 1356 }
ccc9c027
L		 1357 }
1358
76bc74dc
L		 1359 if (patt == f32_patt)
1360 {
1361 /* If the padding is less than 15 bytes, we use the normal
1362 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1363 its offset. */
1364 int limit;
76ba9986 1365
711eedef
L		 1366 /* For 64bit, the limit is 3 bytes. */
1367 if (flag_code == CODE_64BIT
1368 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1369 limit = 3;
1370 else
1371 limit = 15;
1372 if (count < limit)
76bc74dc
L		 1373 memcpy (fragP->fr_literal + fragP->fr_fix,
1374 patt[count - 1], count);
1375 else
1376 {
1377 memcpy (fragP->fr_literal + fragP->fr_fix,
1378 jump_31, count);
1379 /* Adjust jump offset. */
1380 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1381 }
1382 }
1383 else
1384 {
80b8656c
L		 1385 /* Maximum length of an instruction is 10 byte. If the
1386 padding is greater than 10 bytes and we don't use jump,
76bc74dc
L		 1387 we have to break it into smaller pieces. */
1388 int padding = count;
80b8656c 1389 while (padding > 10)
76bc74dc 1390 {
80b8656c 1391 padding -= 10;
76bc74dc 1392 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
80b8656c 1393 patt [9], 10);
76bc74dc
L		 1394 }
1395
1396 if (padding)
1397 memcpy (fragP->fr_literal + fragP->fr_fix,
1398 patt [padding - 1], padding);
1399 }
ccc9c027 1400 }
33fef721 1401 fragP->fr_var = count;
252b5132
RH		 1402}
1403
c6fb90c8 1404static INLINE int
0dfbf9d7 1405operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1406{
0dfbf9d7 1407 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1408 {
1409 case 3:
0dfbf9d7 1410 if (x->array[2])
c6fb90c8 1411 return 0;
1a0670f3 1412 /* Fall through. */
c6fb90c8 1413 case 2:
0dfbf9d7 1414 if (x->array[1])
c6fb90c8 1415 return 0;
1a0670f3 1416 /* Fall through. */
c6fb90c8 1417 case 1:
0dfbf9d7 1418 return !x->array[0];
c6fb90c8
L		 1419 default:
1420 abort ();
1421 }
40fb9820
L		 1422}
1423
c6fb90c8 1424static INLINE void
0dfbf9d7 1425operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1426{
0dfbf9d7 1427 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1428 {
1429 case 3:
0dfbf9d7 1430 x->array[2] = v;
1a0670f3 1431 /* Fall through. */
c6fb90c8 1432 case 2:
0dfbf9d7 1433 x->array[1] = v;
1a0670f3 1434 /* Fall through. */
c6fb90c8 1435 case 1:
0dfbf9d7 1436 x->array[0] = v;
1a0670f3 1437 /* Fall through. */
c6fb90c8
L		 1438 break;
1439 default:
1440 abort ();
1441 }
1442}
40fb9820 1443
c6fb90c8 1444static INLINE int
0dfbf9d7
L		 1445operand_type_equal (const union i386_operand_type *x,
1446 const union i386_operand_type *y)
c6fb90c8 1447{
0dfbf9d7 1448 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1449 {
1450 case 3:
0dfbf9d7 1451 if (x->array[2] != y->array[2])
c6fb90c8 1452 return 0;
1a0670f3 1453 /* Fall through. */
c6fb90c8 1454 case 2:
0dfbf9d7 1455 if (x->array[1] != y->array[1])
c6fb90c8 1456 return 0;
1a0670f3 1457 /* Fall through. */
c6fb90c8 1458 case 1:
0dfbf9d7 1459 return x->array[0] == y->array[0];
c6fb90c8
L		 1460 break;
1461 default:
1462 abort ();
1463 }
1464}
40fb9820 1465
0dfbf9d7
L		 1466static INLINE int
1467cpu_flags_all_zero (const union i386_cpu_flags *x)
1468{
1469 switch (ARRAY_SIZE(x->array))
1470 {
53467f57
IT		 1471 case 4:
1472 if (x->array[3])
1473 return 0;
1474 /* Fall through. */
0dfbf9d7
L		 1475 case 3:
1476 if (x->array[2])
1477 return 0;
1a0670f3 1478 /* Fall through. */
0dfbf9d7
L		 1479 case 2:
1480 if (x->array[1])
1481 return 0;
1a0670f3 1482 /* Fall through. */
0dfbf9d7
L		 1483 case 1:
1484 return !x->array[0];
1485 default:
1486 abort ();
1487 }
1488}
1489
0dfbf9d7
L		 1490static INLINE int
1491cpu_flags_equal (const union i386_cpu_flags *x,
1492 const union i386_cpu_flags *y)
1493{
1494 switch (ARRAY_SIZE(x->array))
1495 {
53467f57
IT		 1496 case 4:
1497 if (x->array[3] != y->array[3])
1498 return 0;
1499 /* Fall through. */
0dfbf9d7
L		 1500 case 3:
1501 if (x->array[2] != y->array[2])
1502 return 0;
1a0670f3 1503 /* Fall through. */
0dfbf9d7
L		 1504 case 2:
1505 if (x->array[1] != y->array[1])
1506 return 0;
1a0670f3 1507 /* Fall through. */
0dfbf9d7
L		 1508 case 1:
1509 return x->array[0] == y->array[0];
1510 break;
1511 default:
1512 abort ();
1513 }
1514}
c6fb90c8
L		 1515
1516static INLINE int
1517cpu_flags_check_cpu64 (i386_cpu_flags f)
1518{
1519 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1520 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1521}
1522
c6fb90c8
L		 1523static INLINE i386_cpu_flags
1524cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1525{
c6fb90c8
L		 1526 switch (ARRAY_SIZE (x.array))
1527 {
53467f57
IT		 1528 case 4:
1529 x.array [3] &= y.array [3];
1530 /* Fall through. */
c6fb90c8
L		 1531 case 3:
1532 x.array [2] &= y.array [2];
1a0670f3 1533 /* Fall through. */
c6fb90c8
L		 1534 case 2:
1535 x.array [1] &= y.array [1];
1a0670f3 1536 /* Fall through. */
c6fb90c8
L		 1537 case 1:
1538 x.array [0] &= y.array [0];
1539 break;
1540 default:
1541 abort ();
1542 }
1543 return x;
1544}
40fb9820 1545
c6fb90c8
L		 1546static INLINE i386_cpu_flags
1547cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1548{
c6fb90c8 1549 switch (ARRAY_SIZE (x.array))
40fb9820 1550 {
53467f57
IT		 1551 case 4:
1552 x.array [3] |= y.array [3];
1553 /* Fall through. */
c6fb90c8
L		 1554 case 3:
1555 x.array [2] |= y.array [2];
1a0670f3 1556 /* Fall through. */
c6fb90c8
L		 1557 case 2:
1558 x.array [1] |= y.array [1];
1a0670f3 1559 /* Fall through. */
c6fb90c8
L		 1560 case 1:
1561 x.array [0] |= y.array [0];
40fb9820
L		 1562 break;
1563 default:
1564 abort ();
1565 }
40fb9820
L		 1566 return x;
1567}
1568
309d3373
JB		 1569static INLINE i386_cpu_flags
1570cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1571{
1572 switch (ARRAY_SIZE (x.array))
1573 {
53467f57
IT		 1574 case 4:
1575 x.array [3] &= ~y.array [3];
1576 /* Fall through. */
309d3373
JB		 1577 case 3:
1578 x.array [2] &= ~y.array [2];
1a0670f3 1579 /* Fall through. */
309d3373
JB		 1580 case 2:
1581 x.array [1] &= ~y.array [1];
1a0670f3 1582 /* Fall through. */
309d3373
JB		 1583 case 1:
1584 x.array [0] &= ~y.array [0];
1585 break;
1586 default:
1587 abort ();
1588 }
1589 return x;
1590}
1591
c0f3af97
L		 1592#define CPU_FLAGS_ARCH_MATCH 0x1
1593#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1594#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1595#define CPU_FLAGS_PCLMUL_MATCH 0x8
1596#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1597
a5ff0eb2 1598#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1599 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1600 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1601#define CPU_FLAGS_PERFECT_MATCH \
1602 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1603
1604/* Return CPU flags match bits. */
3629bb00 1605
40fb9820 1606static int
d3ce72d0 1607cpu_flags_match (const insn_template *t)
40fb9820 1608{
c0f3af97
L		 1609 i386_cpu_flags x = t->cpu_flags;
1610 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1611
1612 x.bitfield.cpu64 = 0;
1613 x.bitfield.cpuno64 = 0;
1614
0dfbf9d7 1615 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1616 {
1617 /* This instruction is available on all archs. */
1618 match |= CPU_FLAGS_32BIT_MATCH;
1619 }
3629bb00
L		 1620 else
1621 {
c0f3af97 1622 /* This instruction is available only on some archs. */
3629bb00
L		 1623 i386_cpu_flags cpu = cpu_arch_flags;
1624
3629bb00 1625 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1626 if (!cpu_flags_all_zero (&cpu))
1627 {
a5ff0eb2
L		 1628 if (x.bitfield.cpuavx)
1629 {
ce2f5b3c 1630 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1631 if (cpu.bitfield.cpuavx)
1632 {
1633 /* Check SSE2AVX. */
1634 if (!t->opcode_modifier.sse2avx|| sse2avx)
1635 {
1636 match |= (CPU_FLAGS_ARCH_MATCH
1637 | CPU_FLAGS_AVX_MATCH);
1638 /* Check AES. */
1639 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1640 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1641 /* Check PCLMUL. */
1642 if (!x.bitfield.cpupclmul
1643 || cpu.bitfield.cpupclmul)
1644 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1645 }
1646 }
1647 else
1648 match |= CPU_FLAGS_ARCH_MATCH;
1649 }
73b090a9
L		 1650 else if (x.bitfield.cpuavx512vl)
1651 {
1652 /* Match AVX512VL. */
1653 if (cpu.bitfield.cpuavx512vl)
1654 {
1655 /* Need another match. */
1656 cpu.bitfield.cpuavx512vl = 0;
1657 if (!cpu_flags_all_zero (&cpu))
1658 match |= CPU_FLAGS_32BIT_MATCH;
1659 else
1660 match |= CPU_FLAGS_ARCH_MATCH;
1661 }
1662 else
1663 match |= CPU_FLAGS_ARCH_MATCH;
1664 }
a5ff0eb2 1665 else
c0f3af97
L		 1666 match |= CPU_FLAGS_32BIT_MATCH;
1667 }
3629bb00 1668 }
c0f3af97 1669 return match;
40fb9820
L		 1670}
1671
c6fb90c8
L		 1672static INLINE i386_operand_type
1673operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1674{
c6fb90c8
L		 1675 switch (ARRAY_SIZE (x.array))
1676 {
1677 case 3:
1678 x.array [2] &= y.array [2];
1a0670f3 1679 /* Fall through. */
c6fb90c8
L		 1680 case 2:
1681 x.array [1] &= y.array [1];
1a0670f3 1682 /* Fall through. */
c6fb90c8
L		 1683 case 1:
1684 x.array [0] &= y.array [0];
1685 break;
1686 default:
1687 abort ();
1688 }
1689 return x;
40fb9820
L		 1690}
1691
c6fb90c8
L		 1692static INLINE i386_operand_type
1693operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1694{
c6fb90c8 1695 switch (ARRAY_SIZE (x.array))
40fb9820 1696 {
c6fb90c8
L		 1697 case 3:
1698 x.array [2] |= y.array [2];
1a0670f3 1699 /* Fall through. */
c6fb90c8
L		 1700 case 2:
1701 x.array [1] |= y.array [1];
1a0670f3 1702 /* Fall through. */
c6fb90c8
L		 1703 case 1:
1704 x.array [0] |= y.array [0];
40fb9820
L		 1705 break;
1706 default:
1707 abort ();
1708 }
c6fb90c8
L		 1709 return x;
1710}
40fb9820 1711
c6fb90c8
L		 1712static INLINE i386_operand_type
1713operand_type_xor (i386_operand_type x, i386_operand_type y)
1714{
1715 switch (ARRAY_SIZE (x.array))
1716 {
1717 case 3:
1718 x.array [2] ^= y.array [2];
1a0670f3 1719 /* Fall through. */
c6fb90c8
L		 1720 case 2:
1721 x.array [1] ^= y.array [1];
1a0670f3 1722 /* Fall through. */
c6fb90c8
L		 1723 case 1:
1724 x.array [0] ^= y.array [0];
1725 break;
1726 default:
1727 abort ();
1728 }
40fb9820
L		 1729 return x;
1730}
1731
1732static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1733static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1734static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1735static const i386_operand_type inoutportreg
1736 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1737static const i386_operand_type reg16_inoutportreg
1738 = OPERAND_TYPE_REG16_INOUTPORTREG;
1739static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1740static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1741static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1742static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1743static const i386_operand_type anydisp
1744 = OPERAND_TYPE_ANYDISP;
40fb9820 1745static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1746static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1747static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1748static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1749static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1750static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1751static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1752static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1753static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1754static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1755static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1756static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1757static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1758static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1759
1760enum operand_type
1761{
1762 reg,
40fb9820
L		 1763 imm,
1764 disp,
1765 anymem
1766};
1767
c6fb90c8 1768static INLINE int
40fb9820
L		 1769operand_type_check (i386_operand_type t, enum operand_type c)
1770{
1771 switch (c)
1772 {
1773 case reg:
1774 return (t.bitfield.reg8
1775 || t.bitfield.reg16
1776 || t.bitfield.reg32
1777 || t.bitfield.reg64);
1778
40fb9820
L		 1779 case imm:
1780 return (t.bitfield.imm8
1781 || t.bitfield.imm8s
1782 || t.bitfield.imm16
1783 || t.bitfield.imm32
1784 || t.bitfield.imm32s
1785 || t.bitfield.imm64);
1786
1787 case disp:
1788 return (t.bitfield.disp8
1789 || t.bitfield.disp16
1790 || t.bitfield.disp32
1791 || t.bitfield.disp32s
1792 || t.bitfield.disp64);
1793
1794 case anymem:
1795 return (t.bitfield.disp8
1796 || t.bitfield.disp16
1797 || t.bitfield.disp32
1798 || t.bitfield.disp32s
1799 || t.bitfield.disp64
1800 || t.bitfield.baseindex);
1801
1802 default:
1803 abort ();
1804 }
2cfe26b6
AM		 1805
1806 return 0;
40fb9820
L		 1807}
1808
5c07affc
L		 1809/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1810 operand J for instruction template T. */
1811
1812static INLINE int
d3ce72d0 1813match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1814{
1815 return !((i.types[j].bitfield.byte
1816 && !t->operand_types[j].bitfield.byte)
1817 || (i.types[j].bitfield.word
1818 && !t->operand_types[j].bitfield.word)
1819 || (i.types[j].bitfield.dword
1820 && !t->operand_types[j].bitfield.dword)
1821 || (i.types[j].bitfield.qword
1822 && !t->operand_types[j].bitfield.qword));
1823}
1824
1825/* Return 1 if there is no conflict in any size on operand J for
1826 instruction template T. */
1827
1828static INLINE int
d3ce72d0 1829match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1830{
1831 return (match_reg_size (t, j)
1832 && !((i.types[j].bitfield.unspecified
af508cb9 1833 && !i.broadcast
5c07affc
L		 1834 && !t->operand_types[j].bitfield.unspecified)
1835 || (i.types[j].bitfield.fword
1836 && !t->operand_types[j].bitfield.fword)
1837 || (i.types[j].bitfield.tbyte
1838 && !t->operand_types[j].bitfield.tbyte)
1839 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1840 && !t->operand_types[j].bitfield.xmmword)
1841 || (i.types[j].bitfield.ymmword
43234a1e
L		 1842 && !t->operand_types[j].bitfield.ymmword)
1843 || (i.types[j].bitfield.zmmword
1844 && !t->operand_types[j].bitfield.zmmword)));
5c07affc
L		 1845}
1846
1847/* Return 1 if there is no size conflict on any operands for
1848 instruction template T. */
1849
1850static INLINE int
d3ce72d0 1851operand_size_match (const insn_template *t)
5c07affc
L		 1852{
1853 unsigned int j;
1854 int match = 1;
1855
1856 /* Don't check jump instructions. */
1857 if (t->opcode_modifier.jump
1858 || t->opcode_modifier.jumpbyte
1859 || t->opcode_modifier.jumpdword
1860 || t->opcode_modifier.jumpintersegment)
1861 return match;
1862
1863 /* Check memory and accumulator operand size. */
1864 for (j = 0; j < i.operands; j++)
1865 {
1866 if (t->operand_types[j].bitfield.anysize)
1867 continue;
1868
1869 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1870 {
1871 match = 0;
1872 break;
1873 }
1874
1875 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1876 {
1877 match = 0;
1878 break;
1879 }
1880 }
1881
891edac4 1882 if (match)
5c07affc 1883 return match;
891edac4
L		 1884 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1885 {
1886mismatch:
86e026a4 1887 i.error = operand_size_mismatch;
891edac4
L		 1888 return 0;
1889 }
5c07affc
L		 1890
1891 /* Check reverse. */
9c2799c2 1892 gas_assert (i.operands == 2);
5c07affc
L		 1893
1894 match = 1;
1895 for (j = 0; j < 2; j++)
1896 {
1897 if (t->operand_types[j].bitfield.acc
1898 && !match_reg_size (t, j ? 0 : 1))
891edac4 1899 goto mismatch;
5c07affc
L		 1900
1901 if (i.types[j].bitfield.mem
1902 && !match_mem_size (t, j ? 0 : 1))
891edac4 1903 goto mismatch;
5c07affc
L		 1904 }
1905
1906 return match;
1907}
1908
c6fb90c8 1909static INLINE int
40fb9820
L		 1910operand_type_match (i386_operand_type overlap,
1911 i386_operand_type given)
1912{
1913 i386_operand_type temp = overlap;
1914
1915 temp.bitfield.jumpabsolute = 0;
7d5e4556 1916 temp.bitfield.unspecified = 0;
5c07affc
L		 1917 temp.bitfield.byte = 0;
1918 temp.bitfield.word = 0;
1919 temp.bitfield.dword = 0;
1920 temp.bitfield.fword = 0;
1921 temp.bitfield.qword = 0;
1922 temp.bitfield.tbyte = 0;
1923 temp.bitfield.xmmword = 0;
c0f3af97 1924 temp.bitfield.ymmword = 0;
43234a1e 1925 temp.bitfield.zmmword = 0;
0dfbf9d7 1926 if (operand_type_all_zero (&temp))
891edac4 1927 goto mismatch;
40fb9820 1928
891edac4
L		 1929 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1930 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1931 return 1;
1932
1933mismatch:
a65babc9 1934 i.error = operand_type_mismatch;
891edac4 1935 return 0;
40fb9820
L		 1936}
1937
7d5e4556 1938/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1939 unless the expected operand type register overlap is null.
1940 Note that Acc in a template matches every size of reg. */
1941
c6fb90c8 1942static INLINE int
40fb9820
L		 1943operand_type_register_match (i386_operand_type m0,
1944 i386_operand_type g0,
1945 i386_operand_type t0,
1946 i386_operand_type m1,
1947 i386_operand_type g1,
1948 i386_operand_type t1)
1949{
1950 if (!operand_type_check (g0, reg))
1951 return 1;
1952
1953 if (!operand_type_check (g1, reg))
1954 return 1;
1955
1956 if (g0.bitfield.reg8 == g1.bitfield.reg8
1957 && g0.bitfield.reg16 == g1.bitfield.reg16
1958 && g0.bitfield.reg32 == g1.bitfield.reg32
1959 && g0.bitfield.reg64 == g1.bitfield.reg64)
1960 return 1;
1961
1962 if (m0.bitfield.acc)
1963 {
1964 t0.bitfield.reg8 = 1;
1965 t0.bitfield.reg16 = 1;
1966 t0.bitfield.reg32 = 1;
1967 t0.bitfield.reg64 = 1;
1968 }
1969
1970 if (m1.bitfield.acc)
1971 {
1972 t1.bitfield.reg8 = 1;
1973 t1.bitfield.reg16 = 1;
1974 t1.bitfield.reg32 = 1;
1975 t1.bitfield.reg64 = 1;
1976 }
1977
891edac4
L		 1978 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1979 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1980 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1981 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1982 return 1;
1983
a65babc9 1984 i.error = register_type_mismatch;
891edac4
L		 1985
1986 return 0;
40fb9820
L		 1987}
1988
4c692bc7
JB		 1989static INLINE unsigned int
1990register_number (const reg_entry *r)
1991{
1992 unsigned int nr = r->reg_num;
1993
1994 if (r->reg_flags & RegRex)
1995 nr += 8;
1996
200cbe0f
L		 1997 if (r->reg_flags & RegVRex)
1998 nr += 16;
1999
4c692bc7
JB		 2000 return nr;
2001}
2002
252b5132 2003static INLINE unsigned int
40fb9820 2004mode_from_disp_size (i386_operand_type t)
252b5132 2005{
43234a1e 2006 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
40fb9820
L		 2007 return 1;
2008 else if (t.bitfield.disp16
2009 || t.bitfield.disp32
2010 || t.bitfield.disp32s)
2011 return 2;
2012 else
2013 return 0;
252b5132
RH		 2014}
2015
2016static INLINE int
65879393 2017fits_in_signed_byte (addressT num)
252b5132 2018{
65879393 2019 return num + 0x80 <= 0xff;
47926f60 2020}
252b5132
RH		 2021
2022static INLINE int
65879393 2023fits_in_unsigned_byte (addressT num)
252b5132 2024{
65879393 2025 return num <= 0xff;
47926f60 2026}
252b5132
RH		 2027
2028static INLINE int
65879393 2029fits_in_unsigned_word (addressT num)
252b5132 2030{
65879393 2031 return num <= 0xffff;
47926f60 2032}
252b5132
RH		 2033
2034static INLINE int
65879393 2035fits_in_signed_word (addressT num)
252b5132 2036{
65879393 2037 return num + 0x8000 <= 0xffff;
47926f60 2038}
2a962e6d 2039
3e73aa7c 2040static INLINE int
65879393 2041fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2042{
2043#ifndef BFD64
2044 return 1;
2045#else
65879393 2046 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 2047#endif
2048} /* fits_in_signed_long() */
2a962e6d 2049
3e73aa7c 2050static INLINE int
65879393 2051fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2052{
2053#ifndef BFD64
2054 return 1;
2055#else
65879393 2056 return num <= 0xffffffff;
3e73aa7c
JH		 2057#endif
2058} /* fits_in_unsigned_long() */
252b5132 2059
43234a1e
L		 2060static INLINE int
2061fits_in_vec_disp8 (offsetT num)
2062{
2063 int shift = i.memshift;
2064 unsigned int mask;
2065
2066 if (shift == -1)
2067 abort ();
2068
2069 mask = (1 << shift) - 1;
2070
2071 /* Return 0 if NUM isn't properly aligned. */
2072 if ((num & mask))
2073 return 0;
2074
2075 /* Check if NUM will fit in 8bit after shift. */
2076 return fits_in_signed_byte (num >> shift);
2077}
2078
a683cc34
SP		 2079static INLINE int
2080fits_in_imm4 (offsetT num)
2081{
2082 return (num & 0xf) == num;
2083}
2084
40fb9820 2085static i386_operand_type
e3bb37b5 2086smallest_imm_type (offsetT num)
252b5132 2087{
40fb9820 2088 i386_operand_type t;
7ab9ffdd 2089
0dfbf9d7 2090 operand_type_set (&t, 0);
40fb9820
L		 2091 t.bitfield.imm64 = 1;
2092
2093 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2094 {
2095 /* This code is disabled on the 486 because all the Imm1 forms
2096 in the opcode table are slower on the i486. They're the
2097 versions with the implicitly specified single-position
2098 displacement, which has another syntax if you really want to
2099 use that form. */
40fb9820
L		 2100 t.bitfield.imm1 = 1;
2101 t.bitfield.imm8 = 1;
2102 t.bitfield.imm8s = 1;
2103 t.bitfield.imm16 = 1;
2104 t.bitfield.imm32 = 1;
2105 t.bitfield.imm32s = 1;
2106 }
2107 else if (fits_in_signed_byte (num))
2108 {
2109 t.bitfield.imm8 = 1;
2110 t.bitfield.imm8s = 1;
2111 t.bitfield.imm16 = 1;
2112 t.bitfield.imm32 = 1;
2113 t.bitfield.imm32s = 1;
2114 }
2115 else if (fits_in_unsigned_byte (num))
2116 {
2117 t.bitfield.imm8 = 1;
2118 t.bitfield.imm16 = 1;
2119 t.bitfield.imm32 = 1;
2120 t.bitfield.imm32s = 1;
2121 }
2122 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2123 {
2124 t.bitfield.imm16 = 1;
2125 t.bitfield.imm32 = 1;
2126 t.bitfield.imm32s = 1;
2127 }
2128 else if (fits_in_signed_long (num))
2129 {
2130 t.bitfield.imm32 = 1;
2131 t.bitfield.imm32s = 1;
2132 }
2133 else if (fits_in_unsigned_long (num))
2134 t.bitfield.imm32 = 1;
2135
2136 return t;
47926f60 2137}
252b5132 2138
847f7ad4 2139static offsetT
e3bb37b5 2140offset_in_range (offsetT val, int size)
847f7ad4 2141{
508866be 2142 addressT mask;
ba2adb93 2143
847f7ad4
AM		 2144 switch (size)
2145 {
508866be
L		 2146 case 1: mask = ((addressT) 1 << 8) - 1; break;
2147 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2148 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2149#ifdef BFD64
2150 case 8: mask = ((addressT) 2 << 63) - 1; break;
2151#endif
47926f60 2152 default: abort ();
847f7ad4
AM		 2153 }
2154
9de868bf
L		 2155#ifdef BFD64
2156 /* If BFD64, sign extend val for 32bit address mode. */
2157 if (flag_code != CODE_64BIT
2158 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2159 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2160 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2161#endif
ba2adb93 2162
47926f60 2163 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2164 {
2165 char buf1[40], buf2[40];
2166
2167 sprint_value (buf1, val);
2168 sprint_value (buf2, val & mask);
2169 as_warn (_("%s shortened to %s"), buf1, buf2);
2170 }
2171 return val & mask;
2172}
2173
c32fa91d
L		 2174enum PREFIX_GROUP
2175{
2176 PREFIX_EXIST = 0,
2177 PREFIX_LOCK,
2178 PREFIX_REP,
04ef582a 2179 PREFIX_DS,
c32fa91d
L		 2180 PREFIX_OTHER
2181};
2182
2183/* Returns
2184 a. PREFIX_EXIST if attempting to add a prefix where one from the
2185 same class already exists.
2186 b. PREFIX_LOCK if lock prefix is added.
2187 c. PREFIX_REP if rep/repne prefix is added.
04ef582a
L		 2188 d. PREFIX_DS if ds prefix is added.
2189 e. PREFIX_OTHER if other prefix is added.
c32fa91d
L		 2190 */
2191
2192static enum PREFIX_GROUP
e3bb37b5 2193add_prefix (unsigned int prefix)
252b5132 2194{
c32fa91d 2195 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2196 unsigned int q;
252b5132 2197
29b0f896
AM		 2198 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2199 && flag_code == CODE_64BIT)
b1905489 2200 {
161a04f6
L		 2201 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2202 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2203 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2204 ret = PREFIX_EXIST;
b1905489
JB		 2205 q = REX_PREFIX;
2206 }
3e73aa7c 2207 else
b1905489
JB		 2208 {
2209 switch (prefix)
2210 {
2211 default:
2212 abort ();
2213
b1905489 2214 case DS_PREFIX_OPCODE:
04ef582a
L		 2215 ret = PREFIX_DS;
2216 /* Fall through. */
2217 case CS_PREFIX_OPCODE:
b1905489
JB		 2218 case ES_PREFIX_OPCODE:
2219 case FS_PREFIX_OPCODE:
2220 case GS_PREFIX_OPCODE:
2221 case SS_PREFIX_OPCODE:
2222 q = SEG_PREFIX;
2223 break;
2224
2225 case REPNE_PREFIX_OPCODE:
2226 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2227 q = REP_PREFIX;
2228 ret = PREFIX_REP;
2229 break;
2230
b1905489 2231 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2232 q = LOCK_PREFIX;
2233 ret = PREFIX_LOCK;
b1905489
JB		 2234 break;
2235
2236 case FWAIT_OPCODE:
2237 q = WAIT_PREFIX;
2238 break;
2239
2240 case ADDR_PREFIX_OPCODE:
2241 q = ADDR_PREFIX;
2242 break;
2243
2244 case DATA_PREFIX_OPCODE:
2245 q = DATA_PREFIX;
2246 break;
2247 }
2248 if (i.prefix[q] != 0)
c32fa91d 2249 ret = PREFIX_EXIST;
b1905489 2250 }
252b5132 2251
b1905489 2252 if (ret)
252b5132 2253 {
b1905489
JB		 2254 if (!i.prefix[q])
2255 ++i.prefixes;
2256 i.prefix[q] |= prefix;
252b5132 2257 }
b1905489
JB		 2258 else
2259 as_bad (_("same type of prefix used twice"));
252b5132 2260
252b5132
RH		 2261 return ret;
2262}
2263
2264static void
78f12dd3 2265update_code_flag (int value, int check)
eecb386c 2266{
78f12dd3
L		 2267 PRINTF_LIKE ((*as_error));
2268
1e9cc1c2 2269 flag_code = (enum flag_code) value;
40fb9820
L		 2270 if (flag_code == CODE_64BIT)
2271 {
2272 cpu_arch_flags.bitfield.cpu64 = 1;
2273 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2274 }
2275 else
2276 {
2277 cpu_arch_flags.bitfield.cpu64 = 0;
2278 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2279 }
2280 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2281 {
78f12dd3
L		 2282 if (check)
2283 as_error = as_fatal;
2284 else
2285 as_error = as_bad;
2286 (*as_error) (_("64bit mode not supported on `%s'."),
2287 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2288 }
40fb9820 2289 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2290 {
78f12dd3
L		 2291 if (check)
2292 as_error = as_fatal;
2293 else
2294 as_error = as_bad;
2295 (*as_error) (_("32bit mode not supported on `%s'."),
2296 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2297 }
eecb386c
AM		 2298 stackop_size = '\0';
2299}
2300
78f12dd3
L		 2301static void
2302set_code_flag (int value)
2303{
2304 update_code_flag (value, 0);
2305}
2306
eecb386c 2307static void
e3bb37b5 2308set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2309{
1e9cc1c2 2310 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2311 if (flag_code != CODE_16BIT)
2312 abort ();
2313 cpu_arch_flags.bitfield.cpu64 = 0;
2314 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2315 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2316}
2317
2318static void
e3bb37b5 2319set_intel_syntax (int syntax_flag)
252b5132
RH		 2320{
2321 /* Find out if register prefixing is specified. */
2322 int ask_naked_reg = 0;
2323
2324 SKIP_WHITESPACE ();
29b0f896 2325 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132 2326 {
d02603dc
NC		 2327 char *string;
2328 int e = get_symbol_name (&string);
252b5132 2329
47926f60 2330 if (strcmp (string, "prefix") == 0)
252b5132 2331 ask_naked_reg = 1;
47926f60 2332 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2333 ask_naked_reg = -1;
2334 else
d0b47220 2335 as_bad (_("bad argument to syntax directive."));
d02603dc 2336 (void) restore_line_pointer (e);
252b5132
RH		 2337 }
2338 demand_empty_rest_of_line ();
c3332e24 2339
252b5132
RH		 2340 intel_syntax = syntax_flag;
2341
2342 if (ask_naked_reg == 0)
f86103b7
AM		 2343 allow_naked_reg = (intel_syntax
2344 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2345 else
2346 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2347
ee86248c 2348 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2349
e4a3b5a4 2350 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2351 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2352 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2353}
2354
1efbbeb4
L		 2355static void
2356set_intel_mnemonic (int mnemonic_flag)
2357{
e1d4d893 2358 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2359}
2360
db51cc60
L		 2361static void
2362set_allow_index_reg (int flag)
2363{
2364 allow_index_reg = flag;
2365}
2366
cb19c032 2367static void
7bab8ab5 2368set_check (int what)
cb19c032 2369{
7bab8ab5
JB		 2370 enum check_kind *kind;
2371 const char *str;
2372
2373 if (what)
2374 {
2375 kind = &operand_check;
2376 str = "operand";
2377 }
2378 else
2379 {
2380 kind = &sse_check;
2381 str = "sse";
2382 }
2383
cb19c032
L		 2384 SKIP_WHITESPACE ();
2385
2386 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2387 {
d02603dc
NC		 2388 char *string;
2389 int e = get_symbol_name (&string);
cb19c032
L		 2390
2391 if (strcmp (string, "none") == 0)
7bab8ab5 2392 *kind = check_none;
cb19c032 2393 else if (strcmp (string, "warning") == 0)
7bab8ab5 2394 *kind = check_warning;
cb19c032 2395 else if (strcmp (string, "error") == 0)
7bab8ab5 2396 *kind = check_error;
cb19c032 2397 else
7bab8ab5 2398 as_bad (_("bad argument to %s_check directive."), str);
d02603dc 2399 (void) restore_line_pointer (e);
cb19c032
L		 2400 }
2401 else
7bab8ab5 2402 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2403
2404 demand_empty_rest_of_line ();
2405}
2406
8a9036a4
L		 2407static void
2408check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2409 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2410{
2411#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2412 static const char *arch;
2413
2414 /* Intel LIOM is only supported on ELF. */
2415 if (!IS_ELF)
2416 return;
2417
2418 if (!arch)
2419 {
2420 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2421 use default_arch. */
2422 arch = cpu_arch_name;
2423 if (!arch)
2424 arch = default_arch;
2425 }
2426
81486035
L		 2427 /* If we are targeting Intel MCU, we must enable it. */
2428 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2429 || new_flag.bitfield.cpuiamcu)
2430 return;
2431
3632d14b 2432 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2433 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2434 || new_flag.bitfield.cpul1om)
8a9036a4 2435 return;
76ba9986 2436
7a9068fe
L		 2437 /* If we are targeting Intel K1OM, we must enable it. */
2438 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2439 || new_flag.bitfield.cpuk1om)
2440 return;
2441
8a9036a4
L		 2442 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2443#endif
2444}
2445
e413e4e9 2446static void
e3bb37b5 2447set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2448{
47926f60 2449 SKIP_WHITESPACE ();
e413e4e9 2450
29b0f896 2451 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9 2452 {
d02603dc
NC		 2453 char *string;
2454 int e = get_symbol_name (&string);
91d6fa6a 2455 unsigned int j;
40fb9820 2456 i386_cpu_flags flags;
e413e4e9 2457
91d6fa6a 2458 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2459 {
91d6fa6a 2460 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2461 {
91d6fa6a 2462 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2463
5c6af06e
JB		 2464 if (*string != '.')
2465 {
91d6fa6a 2466 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2467 cpu_sub_arch_name = NULL;
91d6fa6a 2468 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2469 if (flag_code == CODE_64BIT)
2470 {
2471 cpu_arch_flags.bitfield.cpu64 = 1;
2472 cpu_arch_flags.bitfield.cpuno64 = 0;
2473 }
2474 else
2475 {
2476 cpu_arch_flags.bitfield.cpu64 = 0;
2477 cpu_arch_flags.bitfield.cpuno64 = 1;
2478 }
91d6fa6a
NC		 2479 cpu_arch_isa = cpu_arch[j].type;
2480 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2481 if (!cpu_arch_tune_set)
2482 {
2483 cpu_arch_tune = cpu_arch_isa;
2484 cpu_arch_tune_flags = cpu_arch_isa_flags;
2485 }
5c6af06e
JB		 2486 break;
2487 }
40fb9820 2488
293f5f65
L		 2489 flags = cpu_flags_or (cpu_arch_flags,
2490 cpu_arch[j].flags);
81486035 2491
5b64d091 2492 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2493 {
6305a203
L		 2494 if (cpu_sub_arch_name)
2495 {
2496 char *name = cpu_sub_arch_name;
2497 cpu_sub_arch_name = concat (name,
91d6fa6a 2498 cpu_arch[j].name,
1bf57e9f 2499 (const char *) NULL);
6305a203
L		 2500 free (name);
2501 }
2502 else
91d6fa6a 2503 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2504 cpu_arch_flags = flags;
a586129e 2505 cpu_arch_isa_flags = flags;
5c6af06e 2506 }
d02603dc 2507 (void) restore_line_pointer (e);
5c6af06e
JB		 2508 demand_empty_rest_of_line ();
2509 return;
e413e4e9
AM		 2510 }
2511 }
293f5f65
L		 2512
2513 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2514 {
33eaf5de 2515 /* Disable an ISA extension. */
293f5f65
L		 2516 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2517 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2518 {
2519 flags = cpu_flags_and_not (cpu_arch_flags,
2520 cpu_noarch[j].flags);
2521 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2522 {
2523 if (cpu_sub_arch_name)
2524 {
2525 char *name = cpu_sub_arch_name;
2526 cpu_sub_arch_name = concat (name, string,
2527 (const char *) NULL);
2528 free (name);
2529 }
2530 else
2531 cpu_sub_arch_name = xstrdup (string);
2532 cpu_arch_flags = flags;
2533 cpu_arch_isa_flags = flags;
2534 }
2535 (void) restore_line_pointer (e);
2536 demand_empty_rest_of_line ();
2537 return;
2538 }
2539
2540 j = ARRAY_SIZE (cpu_arch);
2541 }
2542
91d6fa6a 2543 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2544 as_bad (_("no such architecture: `%s'"), string);
2545
2546 *input_line_pointer = e;
2547 }
2548 else
2549 as_bad (_("missing cpu architecture"));
2550
fddf5b5b
AM		 2551 no_cond_jump_promotion = 0;
2552 if (*input_line_pointer == ','
29b0f896 2553 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b 2554 {
d02603dc
NC		 2555 char *string;
2556 char e;
2557
2558 ++input_line_pointer;
2559 e = get_symbol_name (&string);
fddf5b5b
AM		 2560
2561 if (strcmp (string, "nojumps") == 0)
2562 no_cond_jump_promotion = 1;
2563 else if (strcmp (string, "jumps") == 0)
2564 ;
2565 else
2566 as_bad (_("no such architecture modifier: `%s'"), string);
2567
d02603dc 2568 (void) restore_line_pointer (e);
fddf5b5b
AM		 2569 }
2570
e413e4e9
AM		 2571 demand_empty_rest_of_line ();
2572}
2573
8a9036a4
L		 2574enum bfd_architecture
2575i386_arch (void)
2576{
3632d14b 2577 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2578 {
2579 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2580 || flag_code != CODE_64BIT)
2581 as_fatal (_("Intel L1OM is 64bit ELF only"));
2582 return bfd_arch_l1om;
2583 }
7a9068fe
L		 2584 else if (cpu_arch_isa == PROCESSOR_K1OM)
2585 {
2586 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2587 || flag_code != CODE_64BIT)
2588 as_fatal (_("Intel K1OM is 64bit ELF only"));
2589 return bfd_arch_k1om;
2590 }
81486035
L		 2591 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2592 {
2593 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2594 || flag_code == CODE_64BIT)
2595 as_fatal (_("Intel MCU is 32bit ELF only"));
2596 return bfd_arch_iamcu;
2597 }
8a9036a4
L		 2598 else
2599 return bfd_arch_i386;
2600}
2601
b9d79e03 2602unsigned long
7016a5d5 2603i386_mach (void)
b9d79e03 2604{
351f65ca 2605 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2606 {
3632d14b 2607 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2608 {
351f65ca
L		 2609 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2610 || default_arch[6] != '\0')
8a9036a4
L		 2611 as_fatal (_("Intel L1OM is 64bit ELF only"));
2612 return bfd_mach_l1om;
2613 }
7a9068fe
L		 2614 else if (cpu_arch_isa == PROCESSOR_K1OM)
2615 {
2616 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2617 || default_arch[6] != '\0')
2618 as_fatal (_("Intel K1OM is 64bit ELF only"));
2619 return bfd_mach_k1om;
2620 }
351f65ca 2621 else if (default_arch[6] == '\0')
8a9036a4 2622 return bfd_mach_x86_64;
351f65ca
L		 2623 else
2624 return bfd_mach_x64_32;
8a9036a4 2625 }
5197d474
L		 2626 else if (!strcmp (default_arch, "i386")
2627 || !strcmp (default_arch, "iamcu"))
81486035
L		 2628 {
2629 if (cpu_arch_isa == PROCESSOR_IAMCU)
2630 {
2631 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2632 as_fatal (_("Intel MCU is 32bit ELF only"));
2633 return bfd_mach_i386_iamcu;
2634 }
2635 else
2636 return bfd_mach_i386_i386;
2637 }
b9d79e03 2638 else
2b5d6a91 2639 as_fatal (_("unknown architecture"));
b9d79e03 2640}
b9d79e03 2641\f
252b5132 2642void
7016a5d5 2643md_begin (void)
252b5132
RH		 2644{
2645 const char *hash_err;
2646
86fa6981
L		 2647 /* Support pseudo prefixes like {disp32}. */
2648 lex_type ['{'] = LEX_BEGIN_NAME;
2649
47926f60 2650 /* Initialize op_hash hash table. */
252b5132
RH		 2651 op_hash = hash_new ();
2652
2653 {
d3ce72d0 2654 const insn_template *optab;
29b0f896 2655 templates *core_optab;
252b5132 2656
47926f60
KH		 2657 /* Setup for loop. */
2658 optab = i386_optab;
add39d23 2659 core_optab = XNEW (templates);
252b5132
RH		 2660 core_optab->start = optab;
2661
2662 while (1)
2663 {
2664 ++optab;
2665 if (optab->name == NULL
2666 || strcmp (optab->name, (optab - 1)->name) != 0)
2667 {
2668 /* different name --> ship out current template list;
47926f60 2669 add to hash table; & begin anew. */
252b5132
RH		 2670 core_optab->end = optab;
2671 hash_err = hash_insert (op_hash,
2672 (optab - 1)->name,
5a49b8ac 2673 (void *) core_optab);
252b5132
RH		 2674 if (hash_err)
2675 {
b37df7c4 2676 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2677 (optab - 1)->name,
2678 hash_err);
2679 }
2680 if (optab->name == NULL)
2681 break;
add39d23 2682 core_optab = XNEW (templates);
252b5132
RH		 2683 core_optab->start = optab;
2684 }
2685 }
2686 }
2687
47926f60 2688 /* Initialize reg_hash hash table. */
252b5132
RH		 2689 reg_hash = hash_new ();
2690 {
29b0f896 2691 const reg_entry *regtab;
c3fe08fa 2692 unsigned int regtab_size = i386_regtab_size;
252b5132 2693
c3fe08fa 2694 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2695 {
5a49b8ac 2696 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2697 if (hash_err)
b37df7c4 2698 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2699 regtab->reg_name,
2700 hash_err);
252b5132
RH		 2701 }
2702 }
2703
47926f60 2704 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2705 {
29b0f896
AM		 2706 int c;
2707 char *p;
252b5132
RH		 2708
2709 for (c = 0; c < 256; c++)
2710 {
3882b010 2711 if (ISDIGIT (c))
252b5132
RH		 2712 {
2713 digit_chars[c] = c;
2714 mnemonic_chars[c] = c;
2715 register_chars[c] = c;
2716 operand_chars[c] = c;
2717 }
3882b010 2718 else if (ISLOWER (c))
252b5132
RH		 2719 {
2720 mnemonic_chars[c] = c;
2721 register_chars[c] = c;
2722 operand_chars[c] = c;
2723 }
3882b010 2724 else if (ISUPPER (c))
252b5132 2725 {
3882b010 2726 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2727 register_chars[c] = mnemonic_chars[c];
2728 operand_chars[c] = c;
2729 }
43234a1e 2730 else if (c == '{' || c == '}')
86fa6981
L		 2731 {
2732 mnemonic_chars[c] = c;
2733 operand_chars[c] = c;
2734 }
252b5132 2735
3882b010 2736 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2737 identifier_chars[c] = c;
2738 else if (c >= 128)
2739 {
2740 identifier_chars[c] = c;
2741 operand_chars[c] = c;
2742 }
2743 }
2744
2745#ifdef LEX_AT
2746 identifier_chars['@'] = '@';
32137342
NC		 2747#endif
2748#ifdef LEX_QM
2749 identifier_chars['?'] = '?';
2750 operand_chars['?'] = '?';
252b5132 2751#endif
252b5132 2752 digit_chars['-'] = '-';
c0f3af97 2753 mnemonic_chars['_'] = '_';
791fe849 2754 mnemonic_chars['-'] = '-';
0003779b 2755 mnemonic_chars['.'] = '.';
252b5132
RH		 2756 identifier_chars['_'] = '_';
2757 identifier_chars['.'] = '.';
2758
2759 for (p = operand_special_chars; *p != '\0'; p++)
2760 operand_chars[(unsigned char) *p] = *p;
2761 }
2762
a4447b93
RH		 2763 if (flag_code == CODE_64BIT)
2764 {
ca19b261
KT		 2765#if defined (OBJ_COFF) && defined (TE_PE)
2766 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2767 ? 32 : 16);
2768#else
a4447b93 2769 x86_dwarf2_return_column = 16;
ca19b261 2770#endif
61ff971f 2771 x86_cie_data_alignment = -8;
a4447b93
RH		 2772 }
2773 else
2774 {
2775 x86_dwarf2_return_column = 8;
2776 x86_cie_data_alignment = -4;
2777 }
252b5132
RH		 2778}
2779
2780void
e3bb37b5 2781i386_print_statistics (FILE *file)
252b5132
RH		 2782{
2783 hash_print_statistics (file, "i386 opcode", op_hash);
2784 hash_print_statistics (file, "i386 register", reg_hash);
2785}
2786\f
252b5132
RH		 2787#ifdef DEBUG386
2788
ce8a8b2f 2789/* Debugging routines for md_assemble. */
d3ce72d0 2790static void pte (insn_template *);
40fb9820 2791static void pt (i386_operand_type);
e3bb37b5
L		 2792static void pe (expressionS *);
2793static void ps (symbolS *);
252b5132
RH		 2794
2795static void
e3bb37b5 2796pi (char *line, i386_insn *x)
252b5132 2797{
09137c09 2798 unsigned int j;
252b5132
RH		 2799
2800 fprintf (stdout, "%s: template ", line);
2801 pte (&x->tm);
09f131f2
JH		 2802 fprintf (stdout, " address: base %s index %s scale %x\n",
2803 x->base_reg ? x->base_reg->reg_name : "none",
2804 x->index_reg ? x->index_reg->reg_name : "none",
2805 x->log2_scale_factor);
2806 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2807 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2808 fprintf (stdout, " sib: base %x index %x scale %x\n",
2809 x->sib.base, x->sib.index, x->sib.scale);
2810 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2811 (x->rex & REX_W) != 0,
2812 (x->rex & REX_R) != 0,
2813 (x->rex & REX_X) != 0,
2814 (x->rex & REX_B) != 0);
09137c09 2815 for (j = 0; j < x->operands; j++)
252b5132 2816 {
09137c09
SP		 2817 fprintf (stdout, " #%d: ", j + 1);
2818 pt (x->types[j]);
252b5132 2819 fprintf (stdout, "\n");
09137c09
SP		 2820 if (x->types[j].bitfield.reg8
2821 || x->types[j].bitfield.reg16
2822 || x->types[j].bitfield.reg32
2823 || x->types[j].bitfield.reg64
2824 || x->types[j].bitfield.regmmx
2825 || x->types[j].bitfield.regxmm
2826 || x->types[j].bitfield.regymm
43234a1e 2827 || x->types[j].bitfield.regzmm
09137c09
SP		 2828 || x->types[j].bitfield.sreg2
2829 || x->types[j].bitfield.sreg3
2830 || x->types[j].bitfield.control
2831 || x->types[j].bitfield.debug
2832 || x->types[j].bitfield.test)
2833 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2834 if (operand_type_check (x->types[j], imm))
2835 pe (x->op[j].imms);
2836 if (operand_type_check (x->types[j], disp))
2837 pe (x->op[j].disps);
252b5132
RH		 2838 }
2839}
2840
2841static void
d3ce72d0 2842pte (insn_template *t)
252b5132 2843{
09137c09 2844 unsigned int j;
252b5132 2845 fprintf (stdout, " %d operands ", t->operands);
47926f60 2846 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2847 if (t->extension_opcode != None)
2848 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2849 if (t->opcode_modifier.d)
252b5132 2850 fprintf (stdout, "D");
40fb9820 2851 if (t->opcode_modifier.w)
252b5132
RH		 2852 fprintf (stdout, "W");
2853 fprintf (stdout, "\n");
09137c09 2854 for (j = 0; j < t->operands; j++)
252b5132 2855 {
09137c09
SP		 2856 fprintf (stdout, " #%d type ", j + 1);
2857 pt (t->operand_types[j]);
252b5132
RH		 2858 fprintf (stdout, "\n");
2859 }
2860}
2861
2862static void
e3bb37b5 2863pe (expressionS *e)
252b5132 2864{
24eab124 2865 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2866 fprintf (stdout, " add_number %ld (%lx)\n",
2867 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2868 if (e->X_add_symbol)
2869 {
2870 fprintf (stdout, " add_symbol ");
2871 ps (e->X_add_symbol);
2872 fprintf (stdout, "\n");
2873 }
2874 if (e->X_op_symbol)
2875 {
2876 fprintf (stdout, " op_symbol ");
2877 ps (e->X_op_symbol);
2878 fprintf (stdout, "\n");
2879 }
2880}
2881
2882static void
e3bb37b5 2883ps (symbolS *s)
252b5132
RH		 2884{
2885 fprintf (stdout, "%s type %s%s",
2886 S_GET_NAME (s),
2887 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2888 segment_name (S_GET_SEGMENT (s)));
2889}
2890
7b81dfbb 2891static struct type_name
252b5132 2892 {
40fb9820
L		 2893 i386_operand_type mask;
2894 const char *name;
252b5132 2895 }
7b81dfbb 2896const type_names[] =
252b5132 2897{
40fb9820
L		 2898 { OPERAND_TYPE_REG8, "r8" },
2899 { OPERAND_TYPE_REG16, "r16" },
2900 { OPERAND_TYPE_REG32, "r32" },
2901 { OPERAND_TYPE_REG64, "r64" },
2902 { OPERAND_TYPE_IMM8, "i8" },
2903 { OPERAND_TYPE_IMM8, "i8s" },
2904 { OPERAND_TYPE_IMM16, "i16" },
2905 { OPERAND_TYPE_IMM32, "i32" },
2906 { OPERAND_TYPE_IMM32S, "i32s" },
2907 { OPERAND_TYPE_IMM64, "i64" },
2908 { OPERAND_TYPE_IMM1, "i1" },
2909 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2910 { OPERAND_TYPE_DISP8, "d8" },
2911 { OPERAND_TYPE_DISP16, "d16" },
2912 { OPERAND_TYPE_DISP32, "d32" },
2913 { OPERAND_TYPE_DISP32S, "d32s" },
2914 { OPERAND_TYPE_DISP64, "d64" },
43234a1e 2915 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
40fb9820
L		 2916 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2917 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2918 { OPERAND_TYPE_CONTROL, "control reg" },
2919 { OPERAND_TYPE_TEST, "test reg" },
2920 { OPERAND_TYPE_DEBUG, "debug reg" },
2921 { OPERAND_TYPE_FLOATREG, "FReg" },
2922 { OPERAND_TYPE_FLOATACC, "FAcc" },
2923 { OPERAND_TYPE_SREG2, "SReg2" },
2924 { OPERAND_TYPE_SREG3, "SReg3" },
2925 { OPERAND_TYPE_ACC, "Acc" },
2926 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2927 { OPERAND_TYPE_REGMMX, "rMMX" },
2928 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2929 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2930 { OPERAND_TYPE_REGZMM, "rZMM" },
2931 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2932 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2933};
2934
2935static void
40fb9820 2936pt (i386_operand_type t)
252b5132 2937{
40fb9820 2938 unsigned int j;
c6fb90c8 2939 i386_operand_type a;
252b5132 2940
40fb9820 2941 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2942 {
2943 a = operand_type_and (t, type_names[j].mask);
0349dc08 2944 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2945 fprintf (stdout, "%s, ", type_names[j].name);
2946 }
252b5132
RH		 2947 fflush (stdout);
2948}
2949
2950#endif /* DEBUG386 */
2951\f
252b5132 2952static bfd_reloc_code_real_type
3956db08 2953reloc (unsigned int size,
64e74474
AM		 2954 int pcrel,
2955 int sign,
2956 bfd_reloc_code_real_type other)
252b5132 2957{
47926f60 2958 if (other != NO_RELOC)
3956db08 2959 {
91d6fa6a 2960 reloc_howto_type *rel;
3956db08
JB		 2961
2962 if (size == 8)
2963 switch (other)
2964 {
64e74474
AM		 2965 case BFD_RELOC_X86_64_GOT32:
2966 return BFD_RELOC_X86_64_GOT64;
2967 break;
553d1284
L		 2968 case BFD_RELOC_X86_64_GOTPLT64:
2969 return BFD_RELOC_X86_64_GOTPLT64;
2970 break;
64e74474
AM		 2971 case BFD_RELOC_X86_64_PLTOFF64:
2972 return BFD_RELOC_X86_64_PLTOFF64;
2973 break;
2974 case BFD_RELOC_X86_64_GOTPC32:
2975 other = BFD_RELOC_X86_64_GOTPC64;
2976 break;
2977 case BFD_RELOC_X86_64_GOTPCREL:
2978 other = BFD_RELOC_X86_64_GOTPCREL64;
2979 break;
2980 case BFD_RELOC_X86_64_TPOFF32:
2981 other = BFD_RELOC_X86_64_TPOFF64;
2982 break;
2983 case BFD_RELOC_X86_64_DTPOFF32:
2984 other = BFD_RELOC_X86_64_DTPOFF64;
2985 break;
2986 default:
2987 break;
3956db08 2988 }
e05278af 2989
8ce3d284 2990#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2991 if (other == BFD_RELOC_SIZE32)
2992 {
2993 if (size == 8)
1ab668bf 2994 other = BFD_RELOC_SIZE64;
8fd4256d 2995 if (pcrel)
1ab668bf
AM		 2996 {
2997 as_bad (_("there are no pc-relative size relocations"));
2998 return NO_RELOC;
2999 }
8fd4256d 3000 }
8ce3d284 3001#endif
8fd4256d 3002
e05278af 3003 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 3004 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 3005 sign = -1;
3006
91d6fa6a
NC		 3007 rel = bfd_reloc_type_lookup (stdoutput, other);
3008 if (!rel)
3956db08 3009 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 3010 else if (size != bfd_get_reloc_size (rel))
3956db08 3011 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 3012 bfd_get_reloc_size (rel),
3956db08 3013 size);
91d6fa6a 3014 else if (pcrel && !rel->pc_relative)
3956db08 3015 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 3016 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 3017 && !sign)
91d6fa6a 3018 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 3019 && sign > 0))
3956db08
JB		 3020 as_bad (_("relocated field and relocation type differ in signedness"));
3021 else
3022 return other;
3023 return NO_RELOC;
3024 }
252b5132
RH		 3025
3026 if (pcrel)
3027 {
3e73aa7c 3028 if (!sign)
3956db08 3029 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 3030 switch (size)
3031 {
3032 case 1: return BFD_RELOC_8_PCREL;
3033 case 2: return BFD_RELOC_16_PCREL;
d258b828 3034 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 3035 case 8: return BFD_RELOC_64_PCREL;
252b5132 3036 }
3956db08 3037 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 3038 }
3039 else
3040 {
3956db08 3041 if (sign > 0)
e5cb08ac 3042 switch (size)
3e73aa7c
JH		 3043 {
3044 case 4: return BFD_RELOC_X86_64_32S;
3045 }
3046 else
3047 switch (size)
3048 {
3049 case 1: return BFD_RELOC_8;
3050 case 2: return BFD_RELOC_16;
3051 case 4: return BFD_RELOC_32;
3052 case 8: return BFD_RELOC_64;
3053 }
3956db08
JB		 3054 as_bad (_("cannot do %s %u byte relocation"),
3055 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 3056 }
3057
0cc9e1d3 3058 return NO_RELOC;
252b5132
RH		 3059}
3060
47926f60
KH		 3061/* Here we decide which fixups can be adjusted to make them relative to
3062 the beginning of the section instead of the symbol. Basically we need
3063 to make sure that the dynamic relocations are done correctly, so in
3064 some cases we force the original symbol to be used. */
3065
252b5132 3066int
e3bb37b5 3067tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 3068{
6d249963 3069#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 3070 if (!IS_ELF)
31312f95
AM		 3071 return 1;
3072
a161fe53
AM		 3073 /* Don't adjust pc-relative references to merge sections in 64-bit
3074 mode. */
3075 if (use_rela_relocations
3076 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3077 && fixP->fx_pcrel)
252b5132 3078 return 0;
31312f95 3079
8d01d9a9
AJ		 3080 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3081 and changed later by validate_fix. */
3082 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3083 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3084 return 0;
3085
8fd4256d
L		 3086 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3087 for size relocations. */
3088 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3089 || fixP->fx_r_type == BFD_RELOC_SIZE64
3090 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 3091 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3092 || fixP->fx_r_type == BFD_RELOC_386_GOT32
02a86693 3093 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
13ae64f3
JJ		 3094 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3095 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3096 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3097 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 3098 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3099 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 3100 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3101 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 3102 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3103 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 3104 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3105 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 3106 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
56ceb5b5
L		 3107 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3108 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
bffbf940
JJ		 3109 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3110 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3111 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 3112 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 3113 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3114 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 3115 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3116 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 3117 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3118 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 3119 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3120 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3121 return 0;
31312f95 3122#endif
252b5132
RH		 3123 return 1;
3124}
252b5132 3125
b4cac588 3126static int
e3bb37b5 3127intel_float_operand (const char *mnemonic)
252b5132 3128{
9306ca4a
JB		 3129 /* Note that the value returned is meaningful only for opcodes with (memory)
3130 operands, hence the code here is free to improperly handle opcodes that
3131 have no operands (for better performance and smaller code). */
3132
3133 if (mnemonic[0] != 'f')
3134 return 0; /* non-math */
3135
3136 switch (mnemonic[1])
3137 {
3138 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3139 the fs segment override prefix not currently handled because no
3140 call path can make opcodes without operands get here */
3141 case 'i':
3142 return 2 /* integer op */;
3143 case 'l':
3144 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3145 return 3; /* fldcw/fldenv */
3146 break;
3147 case 'n':
3148 if (mnemonic[2] != 'o' /* fnop */)
3149 return 3; /* non-waiting control op */
3150 break;
3151 case 'r':
3152 if (mnemonic[2] == 's')
3153 return 3; /* frstor/frstpm */
3154 break;
3155 case 's':
3156 if (mnemonic[2] == 'a')
3157 return 3; /* fsave */
3158 if (mnemonic[2] == 't')
3159 {
3160 switch (mnemonic[3])
3161 {
3162 case 'c': /* fstcw */
3163 case 'd': /* fstdw */
3164 case 'e': /* fstenv */
3165 case 's': /* fsts[gw] */
3166 return 3;
3167 }
3168 }
3169 break;
3170 case 'x':
3171 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3172 return 0; /* fxsave/fxrstor are not really math ops */
3173 break;
3174 }
252b5132 3175
9306ca4a 3176 return 1;
252b5132
RH		 3177}
3178
c0f3af97
L		 3179/* Build the VEX prefix. */
3180
3181static void
d3ce72d0 3182build_vex_prefix (const insn_template *t)
c0f3af97
L		 3183{
3184 unsigned int register_specifier;
3185 unsigned int implied_prefix;
3186 unsigned int vector_length;
3187
3188 /* Check register specifier. */
3189 if (i.vex.register_specifier)
43234a1e
L		 3190 {
3191 register_specifier =
3192 ~register_number (i.vex.register_specifier) & 0xf;
3193 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3194 }
c0f3af97
L		 3195 else
3196 register_specifier = 0xf;
3197
33eaf5de 3198 /* Use 2-byte VEX prefix by swapping destination and source
fa99fab2 3199 operand. */
86fa6981
L		 3200 if (i.vec_encoding != vex_encoding_vex3
3201 && i.dir_encoding == dir_encoding_default
fa99fab2 3202 && i.operands == i.reg_operands
7f399153 3203 && i.tm.opcode_modifier.vexopcode == VEX0F
86fa6981 3204 && i.tm.opcode_modifier.load
fa99fab2
L		 3205 && i.rex == REX_B)
3206 {
3207 unsigned int xchg = i.operands - 1;
3208 union i386_op temp_op;
3209 i386_operand_type temp_type;
3210
3211 temp_type = i.types[xchg];
3212 i.types[xchg] = i.types[0];
3213 i.types[0] = temp_type;
3214 temp_op = i.op[xchg];
3215 i.op[xchg] = i.op[0];
3216 i.op[0] = temp_op;
3217
9c2799c2 3218 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3219
3220 i.rex = REX_R;
3221 xchg = i.rm.regmem;
3222 i.rm.regmem = i.rm.reg;
3223 i.rm.reg = xchg;
3224
3225 /* Use the next insn. */
3226 i.tm = t[1];
3227 }
3228
539f890d
L		 3229 if (i.tm.opcode_modifier.vex == VEXScalar)
3230 vector_length = avxscalar;
3231 else
3232 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3233
3234 switch ((i.tm.base_opcode >> 8) & 0xff)
3235 {
3236 case 0:
3237 implied_prefix = 0;
3238 break;
3239 case DATA_PREFIX_OPCODE:
3240 implied_prefix = 1;
3241 break;
3242 case REPE_PREFIX_OPCODE:
3243 implied_prefix = 2;
3244 break;
3245 case REPNE_PREFIX_OPCODE:
3246 implied_prefix = 3;
3247 break;
3248 default:
3249 abort ();
3250 }
3251
3252 /* Use 2-byte VEX prefix if possible. */
86fa6981
L		 3253 if (i.vec_encoding != vex_encoding_vex3
3254 && i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3255 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3256 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3257 {
3258 /* 2-byte VEX prefix. */
3259 unsigned int r;
3260
3261 i.vex.length = 2;
3262 i.vex.bytes[0] = 0xc5;
3263
3264 /* Check the REX.R bit. */
3265 r = (i.rex & REX_R) ? 0 : 1;
3266 i.vex.bytes[1] = (r << 7
3267 | register_specifier << 3
3268 | vector_length << 2
3269 | implied_prefix);
3270 }
3271 else
3272 {
3273 /* 3-byte VEX prefix. */
3274 unsigned int m, w;
3275
f88c9eb0 3276 i.vex.length = 3;
f88c9eb0 3277
7f399153 3278 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3279 {
7f399153
L		 3280 case VEX0F:
3281 m = 0x1;
80de6e00 3282 i.vex.bytes[0] = 0xc4;
7f399153
L		 3283 break;
3284 case VEX0F38:
3285 m = 0x2;
80de6e00 3286 i.vex.bytes[0] = 0xc4;
7f399153
L		 3287 break;
3288 case VEX0F3A:
3289 m = 0x3;
80de6e00 3290 i.vex.bytes[0] = 0xc4;
7f399153
L		 3291 break;
3292 case XOP08:
5dd85c99
SP		 3293 m = 0x8;
3294 i.vex.bytes[0] = 0x8f;
7f399153
L		 3295 break;
3296 case XOP09:
f88c9eb0
SP		 3297 m = 0x9;
3298 i.vex.bytes[0] = 0x8f;
7f399153
L		 3299 break;
3300 case XOP0A:
f88c9eb0
SP		 3301 m = 0xa;
3302 i.vex.bytes[0] = 0x8f;
7f399153
L		 3303 break;
3304 default:
3305 abort ();
f88c9eb0 3306 }
c0f3af97 3307
c0f3af97
L		 3308 /* The high 3 bits of the second VEX byte are 1's compliment
3309 of RXB bits from REX. */
3310 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3311
3312 /* Check the REX.W bit. */
3313 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3314 if (i.tm.opcode_modifier.vexw == VEXW1)
3315 w = 1;
c0f3af97
L		 3316
3317 i.vex.bytes[2] = (w << 7
3318 | register_specifier << 3
3319 | vector_length << 2
3320 | implied_prefix);
3321 }
3322}
3323
43234a1e
L		 3324/* Build the EVEX prefix. */
3325
3326static void
3327build_evex_prefix (void)
3328{
3329 unsigned int register_specifier;
3330 unsigned int implied_prefix;
3331 unsigned int m, w;
3332 rex_byte vrex_used = 0;
3333
3334 /* Check register specifier. */
3335 if (i.vex.register_specifier)
3336 {
3337 gas_assert ((i.vrex & REX_X) == 0);
3338
3339 register_specifier = i.vex.register_specifier->reg_num;
3340 if ((i.vex.register_specifier->reg_flags & RegRex))
3341 register_specifier += 8;
3342 /* The upper 16 registers are encoded in the fourth byte of the
3343 EVEX prefix. */
3344 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3345 i.vex.bytes[3] = 0x8;
3346 register_specifier = ~register_specifier & 0xf;
3347 }
3348 else
3349 {
3350 register_specifier = 0xf;
3351
3352 /* Encode upper 16 vector index register in the fourth byte of
3353 the EVEX prefix. */
3354 if (!(i.vrex & REX_X))
3355 i.vex.bytes[3] = 0x8;
3356 else
3357 vrex_used |= REX_X;
3358 }
3359
3360 switch ((i.tm.base_opcode >> 8) & 0xff)
3361 {
3362 case 0:
3363 implied_prefix = 0;
3364 break;
3365 case DATA_PREFIX_OPCODE:
3366 implied_prefix = 1;
3367 break;
3368 case REPE_PREFIX_OPCODE:
3369 implied_prefix = 2;
3370 break;
3371 case REPNE_PREFIX_OPCODE:
3372 implied_prefix = 3;
3373 break;
3374 default:
3375 abort ();
3376 }
3377
3378 /* 4 byte EVEX prefix. */
3379 i.vex.length = 4;
3380 i.vex.bytes[0] = 0x62;
3381
3382 /* mmmm bits. */
3383 switch (i.tm.opcode_modifier.vexopcode)
3384 {
3385 case VEX0F:
3386 m = 1;
3387 break;
3388 case VEX0F38:
3389 m = 2;
3390 break;
3391 case VEX0F3A:
3392 m = 3;
3393 break;
3394 default:
3395 abort ();
3396 break;
3397 }
3398
3399 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3400 bits from REX. */
3401 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3402
3403 /* The fifth bit of the second EVEX byte is 1's compliment of the
3404 REX_R bit in VREX. */
3405 if (!(i.vrex & REX_R))
3406 i.vex.bytes[1] |= 0x10;
3407 else
3408 vrex_used |= REX_R;
3409
3410 if ((i.reg_operands + i.imm_operands) == i.operands)
3411 {
3412 /* When all operands are registers, the REX_X bit in REX is not
3413 used. We reuse it to encode the upper 16 registers, which is
3414 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3415 as 1's compliment. */
3416 if ((i.vrex & REX_B))
3417 {
3418 vrex_used |= REX_B;
3419 i.vex.bytes[1] &= ~0x40;
3420 }
3421 }
3422
3423 /* EVEX instructions shouldn't need the REX prefix. */
3424 i.vrex &= ~vrex_used;
3425 gas_assert (i.vrex == 0);
3426
3427 /* Check the REX.W bit. */
3428 w = (i.rex & REX_W) ? 1 : 0;
3429 if (i.tm.opcode_modifier.vexw)
3430 {
3431 if (i.tm.opcode_modifier.vexw == VEXW1)
3432 w = 1;
3433 }
3434 /* If w is not set it means we are dealing with WIG instruction. */
3435 else if (!w)
3436 {
3437 if (evexwig == evexw1)
3438 w = 1;
3439 }
3440
3441 /* Encode the U bit. */
3442 implied_prefix |= 0x4;
3443
3444 /* The third byte of the EVEX prefix. */
3445 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3446
3447 /* The fourth byte of the EVEX prefix. */
3448 /* The zeroing-masking bit. */
3449 if (i.mask && i.mask->zeroing)
3450 i.vex.bytes[3] |= 0x80;
3451
3452 /* Don't always set the broadcast bit if there is no RC. */
3453 if (!i.rounding)
3454 {
3455 /* Encode the vector length. */
3456 unsigned int vec_length;
3457
3458 switch (i.tm.opcode_modifier.evex)
3459 {
3460 case EVEXLIG: /* LL' is ignored */
3461 vec_length = evexlig << 5;
3462 break;
3463 case EVEX128:
3464 vec_length = 0 << 5;
3465 break;
3466 case EVEX256:
3467 vec_length = 1 << 5;
3468 break;
3469 case EVEX512:
3470 vec_length = 2 << 5;
3471 break;
3472 default:
3473 abort ();
3474 break;
3475 }
3476 i.vex.bytes[3] |= vec_length;
3477 /* Encode the broadcast bit. */
3478 if (i.broadcast)
3479 i.vex.bytes[3] |= 0x10;
3480 }
3481 else
3482 {
3483 if (i.rounding->type != saeonly)
3484 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3485 else
d3d3c6db 3486 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3487 }
3488
3489 if (i.mask && i.mask->mask)
3490 i.vex.bytes[3] |= i.mask->mask->reg_num;
3491}
3492
65da13b5
L		 3493static void
3494process_immext (void)
3495{
3496 expressionS *exp;
3497
4c692bc7
JB		 3498 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3499 && i.operands > 0)
65da13b5 3500 {
4c692bc7
JB		 3501 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3502 with an opcode suffix which is coded in the same place as an
3503 8-bit immediate field would be.
3504 Here we check those operands and remove them afterwards. */
65da13b5
L		 3505 unsigned int x;
3506
3507 for (x = 0; x < i.operands; x++)
4c692bc7 3508 if (register_number (i.op[x].regs) != x)
65da13b5 3509 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3510 register_prefix, i.op[x].regs->reg_name, x + 1,
3511 i.tm.name);
3512
3513 i.operands = 0;
65da13b5
L		 3514 }
3515
9916071f
AP		 3516 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3517 {
3518 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3519 suffix which is coded in the same place as an 8-bit immediate
3520 field would be.
3521 Here we check those operands and remove them afterwards. */
3522 unsigned int x;
3523
3524 if (i.operands != 3)
3525 abort();
3526
3527 for (x = 0; x < 2; x++)
3528 if (register_number (i.op[x].regs) != x)
3529 goto bad_register_operand;
3530
3531 /* Check for third operand for mwaitx/monitorx insn. */
3532 if (register_number (i.op[x].regs)
3533 != (x + (i.tm.extension_opcode == 0xfb)))
3534 {
3535bad_register_operand:
3536 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3537 register_prefix, i.op[x].regs->reg_name, x+1,
3538 i.tm.name);
3539 }
3540
3541 i.operands = 0;
3542 }
3543
c0f3af97 3544 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3545 which is coded in the same place as an 8-bit immediate field
3546 would be. Here we fake an 8-bit immediate operand from the
3547 opcode suffix stored in tm.extension_opcode.
3548
c1e679ec 3549 AVX instructions also use this encoding, for some of
c0f3af97 3550 3 argument instructions. */
65da13b5 3551
43234a1e 3552 gas_assert (i.imm_operands <= 1
7ab9ffdd 3553 && (i.operands <= 2
43234a1e
L		 3554 || ((i.tm.opcode_modifier.vex
3555 || i.tm.opcode_modifier.evex)
7ab9ffdd 3556 && i.operands <= 4)));
65da13b5
L		 3557
3558 exp = &im_expressions[i.imm_operands++];
3559 i.op[i.operands].imms = exp;
3560 i.types[i.operands] = imm8;
3561 i.operands++;
3562 exp->X_op = O_constant;
3563 exp->X_add_number = i.tm.extension_opcode;
3564 i.tm.extension_opcode = None;
3565}
3566
42164a71
L		 3567
3568static int
3569check_hle (void)
3570{
3571 switch (i.tm.opcode_modifier.hleprefixok)
3572 {
3573 default:
3574 abort ();
82c2def5 3575 case HLEPrefixNone:
165de32a
L		 3576 as_bad (_("invalid instruction `%s' after `%s'"),
3577 i.tm.name, i.hle_prefix);
42164a71 3578 return 0;
82c2def5 3579 case HLEPrefixLock:
42164a71
L		 3580 if (i.prefix[LOCK_PREFIX])
3581 return 1;
165de32a 3582 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3583 return 0;
82c2def5 3584 case HLEPrefixAny:
42164a71 3585 return 1;
82c2def5 3586 case HLEPrefixRelease:
42164a71
L		 3587 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3588 {
3589 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3590 i.tm.name);
3591 return 0;
3592 }
3593 if (i.mem_operands == 0
3594 || !operand_type_check (i.types[i.operands - 1], anymem))
3595 {
3596 as_bad (_("memory destination needed for instruction `%s'"
3597 " after `xrelease'"), i.tm.name);
3598 return 0;
3599 }
3600 return 1;
3601 }
3602}
3603
252b5132
RH		 3604/* This is the guts of the machine-dependent assembler. LINE points to a
3605 machine dependent instruction. This function is supposed to emit
3606 the frags/bytes it assembles to. */
3607
3608void
65da13b5 3609md_assemble (char *line)
252b5132 3610{
40fb9820 3611 unsigned int j;
83b16ac6 3612 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
d3ce72d0 3613 const insn_template *t;
252b5132 3614
47926f60 3615 /* Initialize globals. */
252b5132
RH		 3616 memset (&i, '\0', sizeof (i));
3617 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3618 i.reloc[j] = NO_RELOC;
252b5132
RH		 3619 memset (disp_expressions, '\0', sizeof (disp_expressions));
3620 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3621 save_stack_p = save_stack;
252b5132
RH		 3622
3623 /* First parse an instruction mnemonic & call i386_operand for the operands.
3624 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3625 start of a (possibly prefixed) mnemonic. */
252b5132 3626
29b0f896
AM		 3627 line = parse_insn (line, mnemonic);
3628 if (line == NULL)
3629 return;
83b16ac6 3630 mnem_suffix = i.suffix;
252b5132 3631
29b0f896 3632 line = parse_operands (line, mnemonic);
ee86248c 3633 this_operand = -1;
8325cc63
JB		 3634 xfree (i.memop1_string);
3635 i.memop1_string = NULL;
29b0f896
AM		 3636 if (line == NULL)
3637 return;
252b5132 3638
29b0f896
AM		 3639 /* Now we've parsed the mnemonic into a set of templates, and have the
3640 operands at hand. */
3641
3642 /* All intel opcodes have reversed operands except for "bound" and
3643 "enter". We also don't reverse intersegment "jmp" and "call"
3644 instructions with 2 immediate operands so that the immediate segment
050dfa73 3645 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3646 if (intel_syntax
3647 && i.operands > 1
29b0f896 3648 && (strcmp (mnemonic, "bound") != 0)
30123838 3649 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3650 && !(operand_type_check (i.types[0], imm)
3651 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3652 swap_operands ();
3653
ec56d5c0
JB		 3654 /* The order of the immediates should be reversed
3655 for 2 immediates extrq and insertq instructions */
3656 if (i.imm_operands == 2
3657 && (strcmp (mnemonic, "extrq") == 0
3658 || strcmp (mnemonic, "insertq") == 0))
3659 swap_2_operands (0, 1);
3660
29b0f896
AM		 3661 if (i.imm_operands)
3662 optimize_imm ();
3663
b300c311
L		 3664 /* Don't optimize displacement for movabs since it only takes 64bit
3665 displacement. */
3666 if (i.disp_operands
a501d77e 3667 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3668 && (flag_code != CODE_64BIT
3669 || strcmp (mnemonic, "movabs") != 0))
3670 optimize_disp ();
29b0f896
AM		 3671
3672 /* Next, we find a template that matches the given insn,
3673 making sure the overlap of the given operands types is consistent
3674 with the template operand types. */
252b5132 3675
83b16ac6 3676 if (!(t = match_template (mnem_suffix)))
29b0f896 3677 return;
252b5132 3678
7bab8ab5 3679 if (sse_check != check_none
81f8a913 3680 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3681 && (i.tm.cpu_flags.bitfield.cpusse
3682 || i.tm.cpu_flags.bitfield.cpusse2
3683 || i.tm.cpu_flags.bitfield.cpusse3
3684 || i.tm.cpu_flags.bitfield.cpussse3
3685 || i.tm.cpu_flags.bitfield.cpusse4_1
3686 || i.tm.cpu_flags.bitfield.cpusse4_2))
3687 {
7bab8ab5 3688 (sse_check == check_warning
daf50ae7
L		 3689 ? as_warn
3690 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3691 }
3692
321fd21e
L		 3693 /* Zap movzx and movsx suffix. The suffix has been set from
3694 "word ptr" or "byte ptr" on the source operand in Intel syntax
3695 or extracted from mnemonic in AT&T syntax. But we'll use
3696 the destination register to choose the suffix for encoding. */
3697 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3698 {
321fd21e
L		 3699 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3700 there is no suffix, the default will be byte extension. */
3701 if (i.reg_operands != 2
3702 && !i.suffix
7ab9ffdd 3703 && intel_syntax)
321fd21e
L		 3704 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3705
3706 i.suffix = 0;
cd61ebfe 3707 }
24eab124 3708
40fb9820 3709 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3710 if (!add_prefix (FWAIT_OPCODE))
3711 return;
252b5132 3712
d5de92cf
L		 3713 /* Check if REP prefix is OK. */
3714 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3715 {
3716 as_bad (_("invalid instruction `%s' after `%s'"),
3717 i.tm.name, i.rep_prefix);
3718 return;
3719 }
3720
c1ba0266
L		 3721 /* Check for lock without a lockable instruction. Destination operand
3722 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3723 if (i.prefix[LOCK_PREFIX]
3724 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3725 || i.mem_operands == 0
3726 || (i.tm.base_opcode != 0x86
3727 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3728 {
3729 as_bad (_("expecting lockable instruction after `lock'"));
3730 return;
3731 }
3732
42164a71 3733 /* Check if HLE prefix is OK. */
165de32a 3734 if (i.hle_prefix && !check_hle ())
42164a71
L		 3735 return;
3736
7e8b059b
L		 3737 /* Check BND prefix. */
3738 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3739 as_bad (_("expecting valid branch instruction after `bnd'"));
3740
04ef582a 3741 /* Check NOTRACK prefix. */
9fef80d6
L		 3742 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
3743 as_bad (_("expecting indirect branch instruction after `notrack'"));
04ef582a 3744
327e8c42
JB		 3745 if (i.tm.cpu_flags.bitfield.cpumpx)
3746 {
3747 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
3748 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3749 else if (flag_code != CODE_16BIT
3750 ? i.prefix[ADDR_PREFIX]
3751 : i.mem_operands && !i.prefix[ADDR_PREFIX])
3752 as_bad (_("16-bit address isn't allowed in MPX instructions"));
3753 }
7e8b059b
L		 3754
3755 /* Insert BND prefix. */
3756 if (add_bnd_prefix
3757 && i.tm.opcode_modifier.bndprefixok
3758 && !i.prefix[BND_PREFIX])
3759 add_prefix (BND_PREFIX_OPCODE);
3760
29b0f896 3761 /* Check string instruction segment overrides. */
40fb9820 3762 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3763 {
3764 if (!check_string ())
5dd0794d 3765 return;
fc0763e6 3766 i.disp_operands = 0;
29b0f896 3767 }
5dd0794d 3768
29b0f896
AM		 3769 if (!process_suffix ())
3770 return;
e413e4e9 3771
bc0844ae
L		 3772 /* Update operand types. */
3773 for (j = 0; j < i.operands; j++)
3774 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3775
29b0f896
AM		 3776 /* Make still unresolved immediate matches conform to size of immediate
3777 given in i.suffix. */
3778 if (!finalize_imm ())
3779 return;
252b5132 3780
40fb9820 3781 if (i.types[0].bitfield.imm1)
29b0f896 3782 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3783
9afe6eb8
L		 3784 /* We only need to check those implicit registers for instructions
3785 with 3 operands or less. */
3786 if (i.operands <= 3)
3787 for (j = 0; j < i.operands; j++)
3788 if (i.types[j].bitfield.inoutportreg
3789 || i.types[j].bitfield.shiftcount
3790 || i.types[j].bitfield.acc
3791 || i.types[j].bitfield.floatacc)
3792 i.reg_operands--;
40fb9820 3793
c0f3af97
L		 3794 /* ImmExt should be processed after SSE2AVX. */
3795 if (!i.tm.opcode_modifier.sse2avx
3796 && i.tm.opcode_modifier.immext)
65da13b5 3797 process_immext ();
252b5132 3798
29b0f896
AM		 3799 /* For insns with operands there are more diddles to do to the opcode. */
3800 if (i.operands)
3801 {
3802 if (!process_operands ())
3803 return;
3804 }
40fb9820 3805 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3806 {
3807 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3808 as_warn (_("translating to `%sp'"), i.tm.name);
3809 }
252b5132 3810
9e5e5283
L		 3811 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3812 {
3813 if (flag_code == CODE_16BIT)
3814 {
3815 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3816 i.tm.name);
3817 return;
3818 }
c0f3af97 3819
9e5e5283
L		 3820 if (i.tm.opcode_modifier.vex)
3821 build_vex_prefix (t);
3822 else
3823 build_evex_prefix ();
3824 }
43234a1e 3825
5dd85c99
SP		 3826 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3827 instructions may define INT_OPCODE as well, so avoid this corner
3828 case for those instructions that use MODRM. */
3829 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3830 && !i.tm.opcode_modifier.modrm
3831 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3832 {
3833 i.tm.base_opcode = INT3_OPCODE;
3834 i.imm_operands = 0;
3835 }
252b5132 3836
40fb9820
L		 3837 if ((i.tm.opcode_modifier.jump
3838 || i.tm.opcode_modifier.jumpbyte
3839 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3840 && i.op[0].disps->X_op == O_constant)
3841 {
3842 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3843 the absolute address given by the constant. Since ix86 jumps and
3844 calls are pc relative, we need to generate a reloc. */
3845 i.op[0].disps->X_add_symbol = &abs_symbol;
3846 i.op[0].disps->X_op = O_symbol;
3847 }
252b5132 3848
40fb9820 3849 if (i.tm.opcode_modifier.rex64)
161a04f6 3850 i.rex |= REX_W;
252b5132 3851
29b0f896
AM		 3852 /* For 8 bit registers we need an empty rex prefix. Also if the
3853 instruction already has a prefix, we need to convert old
3854 registers to new ones. */
773f551c 3855
40fb9820 3856 if ((i.types[0].bitfield.reg8
29b0f896 3857 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3858 || (i.types[1].bitfield.reg8
29b0f896 3859 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3860 || ((i.types[0].bitfield.reg8
3861 || i.types[1].bitfield.reg8)
29b0f896
AM		 3862 && i.rex != 0))
3863 {
3864 int x;
726c5dcd 3865
29b0f896
AM		 3866 i.rex |= REX_OPCODE;
3867 for (x = 0; x < 2; x++)
3868 {
3869 /* Look for 8 bit operand that uses old registers. */
40fb9820 3870 if (i.types[x].bitfield.reg8
29b0f896 3871 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3872 {
29b0f896
AM		 3873 /* In case it is "hi" register, give up. */
3874 if (i.op[x].regs->reg_num > 3)
a540244d 3875 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3876 "instruction requiring REX prefix."),
a540244d 3877 register_prefix, i.op[x].regs->reg_name);
773f551c 3878
29b0f896
AM		 3879 /* Otherwise it is equivalent to the extended register.
3880 Since the encoding doesn't change this is merely
3881 cosmetic cleanup for debug output. */
3882
3883 i.op[x].regs = i.op[x].regs + 8;
773f551c 3884 }
29b0f896
AM		 3885 }
3886 }
773f551c 3887
7ab9ffdd 3888 if (i.rex != 0)
29b0f896
AM		 3889 add_prefix (REX_OPCODE | i.rex);
3890
3891 /* We are ready to output the insn. */
3892 output_insn ();
3893}
3894
3895static char *
e3bb37b5 3896parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3897{
3898 char *l = line;
3899 char *token_start = l;
3900 char *mnem_p;
5c6af06e 3901 int supported;
d3ce72d0 3902 const insn_template *t;
b6169b20 3903 char *dot_p = NULL;
29b0f896 3904
29b0f896
AM		 3905 while (1)
3906 {
3907 mnem_p = mnemonic;
3908 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3909 {
b6169b20
L		 3910 if (*mnem_p == '.')
3911 dot_p = mnem_p;
29b0f896
AM		 3912 mnem_p++;
3913 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3914 {
29b0f896
AM		 3915 as_bad (_("no such instruction: `%s'"), token_start);
3916 return NULL;
3917 }
3918 l++;
3919 }
3920 if (!is_space_char (*l)
3921 && *l != END_OF_INSN
e44823cf
JB		 3922 && (intel_syntax
3923 || (*l != PREFIX_SEPARATOR
3924 && *l != ',')))
29b0f896
AM		 3925 {
3926 as_bad (_("invalid character %s in mnemonic"),
3927 output_invalid (*l));
3928 return NULL;
3929 }
3930 if (token_start == l)
3931 {
e44823cf 3932 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3933 as_bad (_("expecting prefix; got nothing"));
3934 else
3935 as_bad (_("expecting mnemonic; got nothing"));
3936 return NULL;
3937 }
45288df1 3938
29b0f896 3939 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3940 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3941
29b0f896
AM		 3942 if (*l != END_OF_INSN
3943 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3944 && current_templates
40fb9820 3945 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3946 {
c6fb90c8 3947 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3948 {
3949 as_bad ((flag_code != CODE_64BIT
3950 ? _("`%s' is only supported in 64-bit mode")
3951 : _("`%s' is not supported in 64-bit mode")),
3952 current_templates->start->name);
3953 return NULL;
3954 }
29b0f896
AM		 3955 /* If we are in 16-bit mode, do not allow addr16 or data16.
3956 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3957 if ((current_templates->start->opcode_modifier.size16
3958 || current_templates->start->opcode_modifier.size32)
29b0f896 3959 && flag_code != CODE_64BIT
40fb9820 3960 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3961 ^ (flag_code == CODE_16BIT)))
3962 {
3963 as_bad (_("redundant %s prefix"),
3964 current_templates->start->name);
3965 return NULL;
45288df1 3966 }
86fa6981 3967 if (current_templates->start->opcode_length == 0)
29b0f896 3968 {
86fa6981
L		 3969 /* Handle pseudo prefixes. */
3970 switch (current_templates->start->base_opcode)
3971 {
3972 case 0x0:
3973 /* {disp8} */
3974 i.disp_encoding = disp_encoding_8bit;
3975 break;
3976 case 0x1:
3977 /* {disp32} */
3978 i.disp_encoding = disp_encoding_32bit;
3979 break;
3980 case 0x2:
3981 /* {load} */
3982 i.dir_encoding = dir_encoding_load;
3983 break;
3984 case 0x3:
3985 /* {store} */
3986 i.dir_encoding = dir_encoding_store;
3987 break;
3988 case 0x4:
3989 /* {vex2} */
3990 i.vec_encoding = vex_encoding_vex2;
3991 break;
3992 case 0x5:
3993 /* {vex3} */
3994 i.vec_encoding = vex_encoding_vex3;
3995 break;
3996 case 0x6:
3997 /* {evex} */
3998 i.vec_encoding = vex_encoding_evex;
3999 break;
4000 default:
4001 abort ();
4002 }
4003 }
4004 else
4005 {
4006 /* Add prefix, checking for repeated prefixes. */
4e9ac44a 4007 switch (add_prefix (current_templates->start->base_opcode))
86fa6981 4008 {
4e9ac44a
L		 4009 case PREFIX_EXIST:
4010 return NULL;
4011 case PREFIX_DS:
4012 if (current_templates->start->cpu_flags.bitfield.cpucet)
4013 i.notrack_prefix = current_templates->start->name;
4014 break;
4015 case PREFIX_REP:
4016 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4017 i.hle_prefix = current_templates->start->name;
4018 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4019 i.bnd_prefix = current_templates->start->name;
4020 else
4021 i.rep_prefix = current_templates->start->name;
4022 break;
4023 default:
4024 break;
86fa6981 4025 }
29b0f896
AM		 4026 }
4027 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4028 token_start = ++l;
4029 }
4030 else
4031 break;
4032 }
45288df1 4033
30a55f88 4034 if (!current_templates)
b6169b20 4035 {
f8a5c266
L		 4036 /* Check if we should swap operand or force 32bit displacement in
4037 encoding. */
30a55f88 4038 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
86fa6981 4039 i.dir_encoding = dir_encoding_store;
8d63c93e 4040 else if (mnem_p - 3 == dot_p
a501d77e
L		 4041 && dot_p[1] == 'd'
4042 && dot_p[2] == '8')
4043 i.disp_encoding = disp_encoding_8bit;
8d63c93e 4044 else if (mnem_p - 4 == dot_p
f8a5c266
L		 4045 && dot_p[1] == 'd'
4046 && dot_p[2] == '3'
4047 && dot_p[3] == '2')
a501d77e 4048 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 4049 else
4050 goto check_suffix;
4051 mnem_p = dot_p;
4052 *dot_p = '\0';
d3ce72d0 4053 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 4054 }
4055
29b0f896
AM		 4056 if (!current_templates)
4057 {
b6169b20 4058check_suffix:
29b0f896
AM		 4059 /* See if we can get a match by trimming off a suffix. */
4060 switch (mnem_p[-1])
4061 {
4062 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 4063 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4064 i.suffix = SHORT_MNEM_SUFFIX;
4065 else
1a0670f3 4066 /* Fall through. */
29b0f896
AM		 4067 case BYTE_MNEM_SUFFIX:
4068 case QWORD_MNEM_SUFFIX:
4069 i.suffix = mnem_p[-1];
4070 mnem_p[-1] = '\0';
d3ce72d0
NC		 4071 current_templates = (const templates *) hash_find (op_hash,
4072 mnemonic);
29b0f896
AM		 4073 break;
4074 case SHORT_MNEM_SUFFIX:
4075 case LONG_MNEM_SUFFIX:
4076 if (!intel_syntax)
4077 {
4078 i.suffix = mnem_p[-1];
4079 mnem_p[-1] = '\0';
d3ce72d0
NC		 4080 current_templates = (const templates *) hash_find (op_hash,
4081 mnemonic);
29b0f896
AM		 4082 }
4083 break;
252b5132 4084
29b0f896
AM		 4085 /* Intel Syntax. */
4086 case 'd':
4087 if (intel_syntax)
4088 {
9306ca4a 4089 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 4090 i.suffix = SHORT_MNEM_SUFFIX;
4091 else
4092 i.suffix = LONG_MNEM_SUFFIX;
4093 mnem_p[-1] = '\0';
d3ce72d0
NC		 4094 current_templates = (const templates *) hash_find (op_hash,
4095 mnemonic);
29b0f896
AM		 4096 }
4097 break;
4098 }
4099 if (!current_templates)
4100 {
4101 as_bad (_("no such instruction: `%s'"), token_start);
4102 return NULL;
4103 }
4104 }
252b5132 4105
40fb9820
L		 4106 if (current_templates->start->opcode_modifier.jump
4107 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 4108 {
4109 /* Check for a branch hint. We allow ",pt" and ",pn" for
4110 predict taken and predict not taken respectively.
4111 I'm not sure that branch hints actually do anything on loop
4112 and jcxz insns (JumpByte) for current Pentium4 chips. They
4113 may work in the future and it doesn't hurt to accept them
4114 now. */
4115 if (l[0] == ',' && l[1] == 'p')
4116 {
4117 if (l[2] == 't')
4118 {
4119 if (!add_prefix (DS_PREFIX_OPCODE))
4120 return NULL;
4121 l += 3;
4122 }
4123 else if (l[2] == 'n')
4124 {
4125 if (!add_prefix (CS_PREFIX_OPCODE))
4126 return NULL;
4127 l += 3;
4128 }
4129 }
4130 }
4131 /* Any other comma loses. */
4132 if (*l == ',')
4133 {
4134 as_bad (_("invalid character %s in mnemonic"),
4135 output_invalid (*l));
4136 return NULL;
4137 }
252b5132 4138
29b0f896 4139 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 4140 supported = 0;
4141 for (t = current_templates->start; t < current_templates->end; ++t)
4142 {
c0f3af97
L		 4143 supported |= cpu_flags_match (t);
4144 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 4145 goto skip;
5c6af06e 4146 }
3629bb00 4147
c0f3af97 4148 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 4149 {
4150 as_bad (flag_code == CODE_64BIT
4151 ? _("`%s' is not supported in 64-bit mode")
4152 : _("`%s' is only supported in 64-bit mode"),
4153 current_templates->start->name);
4154 return NULL;
4155 }
c0f3af97 4156 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 4157 {
3629bb00 4158 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 4159 current_templates->start->name,
41aacd83 4160 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 4161 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4162 return NULL;
29b0f896 4163 }
3629bb00
L		 4164
4165skip:
4166 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 4167 && (flag_code != CODE_16BIT))
29b0f896
AM		 4168 {
4169 as_warn (_("use .code16 to ensure correct addressing mode"));
4170 }
252b5132 4171
29b0f896
AM		 4172 return l;
4173}
252b5132 4174
29b0f896 4175static char *
e3bb37b5 4176parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 4177{
4178 char *token_start;
3138f287 4179
29b0f896
AM		 4180 /* 1 if operand is pending after ','. */
4181 unsigned int expecting_operand = 0;
252b5132 4182
29b0f896
AM		 4183 /* Non-zero if operand parens not balanced. */
4184 unsigned int paren_not_balanced;
4185
4186 while (*l != END_OF_INSN)
4187 {
4188 /* Skip optional white space before operand. */
4189 if (is_space_char (*l))
4190 ++l;
d02603dc 4191 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
29b0f896
AM		 4192 {
4193 as_bad (_("invalid character %s before operand %d"),
4194 output_invalid (*l),
4195 i.operands + 1);
4196 return NULL;
4197 }
d02603dc 4198 token_start = l; /* After white space. */
29b0f896
AM		 4199 paren_not_balanced = 0;
4200 while (paren_not_balanced || *l != ',')
4201 {
4202 if (*l == END_OF_INSN)
4203 {
4204 if (paren_not_balanced)
4205 {
4206 if (!intel_syntax)
4207 as_bad (_("unbalanced parenthesis in operand %d."),
4208 i.operands + 1);
4209 else
4210 as_bad (_("unbalanced brackets in operand %d."),
4211 i.operands + 1);
4212 return NULL;
4213 }
4214 else
4215 break; /* we are done */
4216 }
d02603dc 4217 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
29b0f896
AM		 4218 {
4219 as_bad (_("invalid character %s in operand %d"),
4220 output_invalid (*l),
4221 i.operands + 1);
4222 return NULL;
4223 }
4224 if (!intel_syntax)
4225 {
4226 if (*l == '(')
4227 ++paren_not_balanced;
4228 if (*l == ')')
4229 --paren_not_balanced;
4230 }
4231 else
4232 {
4233 if (*l == '[')
4234 ++paren_not_balanced;
4235 if (*l == ']')
4236 --paren_not_balanced;
4237 }
4238 l++;
4239 }
4240 if (l != token_start)
4241 { /* Yes, we've read in another operand. */
4242 unsigned int operand_ok;
4243 this_operand = i.operands++;
4244 if (i.operands > MAX_OPERANDS)
4245 {
4246 as_bad (_("spurious operands; (%d operands/instruction max)"),
4247 MAX_OPERANDS);
4248 return NULL;
4249 }
9d46ce34 4250 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4251 /* Now parse operand adding info to 'i' as we go along. */
4252 END_STRING_AND_SAVE (l);
4253
4254 if (intel_syntax)
4255 operand_ok =
4256 i386_intel_operand (token_start,
4257 intel_float_operand (mnemonic));
4258 else
a7619375 4259 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4260
4261 RESTORE_END_STRING (l);
4262 if (!operand_ok)
4263 return NULL;
4264 }
4265 else
4266 {
4267 if (expecting_operand)
4268 {
4269 expecting_operand_after_comma:
4270 as_bad (_("expecting operand after ','; got nothing"));
4271 return NULL;
4272 }
4273 if (*l == ',')
4274 {
4275 as_bad (_("expecting operand before ','; got nothing"));
4276 return NULL;
4277 }
4278 }
7f3f1ea2 4279
29b0f896
AM		 4280 /* Now *l must be either ',' or END_OF_INSN. */
4281 if (*l == ',')
4282 {
4283 if (*++l == END_OF_INSN)
4284 {
4285 /* Just skip it, if it's \n complain. */
4286 goto expecting_operand_after_comma;
4287 }
4288 expecting_operand = 1;
4289 }
4290 }
4291 return l;
4292}
7f3f1ea2 4293
050dfa73 4294static void
4d456e3d 4295swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4296{
4297 union i386_op temp_op;
40fb9820 4298 i386_operand_type temp_type;
050dfa73 4299 enum bfd_reloc_code_real temp_reloc;
4eed87de 4300
050dfa73
MM		 4301 temp_type = i.types[xchg2];
4302 i.types[xchg2] = i.types[xchg1];
4303 i.types[xchg1] = temp_type;
4304 temp_op = i.op[xchg2];
4305 i.op[xchg2] = i.op[xchg1];
4306 i.op[xchg1] = temp_op;
4307 temp_reloc = i.reloc[xchg2];
4308 i.reloc[xchg2] = i.reloc[xchg1];
4309 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4310
4311 if (i.mask)
4312 {
4313 if (i.mask->operand == xchg1)
4314 i.mask->operand = xchg2;
4315 else if (i.mask->operand == xchg2)
4316 i.mask->operand = xchg1;
4317 }
4318 if (i.broadcast)
4319 {
4320 if (i.broadcast->operand == xchg1)
4321 i.broadcast->operand = xchg2;
4322 else if (i.broadcast->operand == xchg2)
4323 i.broadcast->operand = xchg1;
4324 }
4325 if (i.rounding)
4326 {
4327 if (i.rounding->operand == xchg1)
4328 i.rounding->operand = xchg2;
4329 else if (i.rounding->operand == xchg2)
4330 i.rounding->operand = xchg1;
4331 }
050dfa73
MM		 4332}
4333
29b0f896 4334static void
e3bb37b5 4335swap_operands (void)
29b0f896 4336{
b7c61d9a 4337 switch (i.operands)
050dfa73 4338 {
c0f3af97 4339 case 5:
b7c61d9a 4340 case 4:
4d456e3d 4341 swap_2_operands (1, i.operands - 2);
1a0670f3 4342 /* Fall through. */
b7c61d9a
L		 4343 case 3:
4344 case 2:
4d456e3d 4345 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4346 break;
4347 default:
4348 abort ();
29b0f896 4349 }
29b0f896
AM		 4350
4351 if (i.mem_operands == 2)
4352 {
4353 const seg_entry *temp_seg;
4354 temp_seg = i.seg[0];
4355 i.seg[0] = i.seg[1];
4356 i.seg[1] = temp_seg;
4357 }
4358}
252b5132 4359
29b0f896
AM		 4360/* Try to ensure constant immediates are represented in the smallest
4361 opcode possible. */
4362static void
e3bb37b5 4363optimize_imm (void)
29b0f896
AM		 4364{
4365 char guess_suffix = 0;
4366 int op;
252b5132 4367
29b0f896
AM		 4368 if (i.suffix)
4369 guess_suffix = i.suffix;
4370 else if (i.reg_operands)
4371 {
4372 /* Figure out a suffix from the last register operand specified.
4373 We can't do this properly yet, ie. excluding InOutPortReg,
4374 but the following works for instructions with immediates.
4375 In any case, we can't set i.suffix yet. */
4376 for (op = i.operands; --op >= 0;)
40fb9820 4377 if (i.types[op].bitfield.reg8)
7ab9ffdd 4378 {
40fb9820
L		 4379 guess_suffix = BYTE_MNEM_SUFFIX;
4380 break;
4381 }
4382 else if (i.types[op].bitfield.reg16)
252b5132 4383 {
40fb9820
L		 4384 guess_suffix = WORD_MNEM_SUFFIX;
4385 break;
4386 }
4387 else if (i.types[op].bitfield.reg32)
4388 {
4389 guess_suffix = LONG_MNEM_SUFFIX;
4390 break;
4391 }
4392 else if (i.types[op].bitfield.reg64)
4393 {
4394 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4395 break;
252b5132 4396 }
29b0f896
AM		 4397 }
4398 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4399 guess_suffix = WORD_MNEM_SUFFIX;
4400
4401 for (op = i.operands; --op >= 0;)
40fb9820 4402 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4403 {
4404 switch (i.op[op].imms->X_op)
252b5132 4405 {
29b0f896
AM		 4406 case O_constant:
4407 /* If a suffix is given, this operand may be shortened. */
4408 switch (guess_suffix)
252b5132 4409 {
29b0f896 4410 case LONG_MNEM_SUFFIX:
40fb9820
L		 4411 i.types[op].bitfield.imm32 = 1;
4412 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4413 break;
4414 case WORD_MNEM_SUFFIX:
40fb9820
L		 4415 i.types[op].bitfield.imm16 = 1;
4416 i.types[op].bitfield.imm32 = 1;
4417 i.types[op].bitfield.imm32s = 1;
4418 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4419 break;
4420 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4421 i.types[op].bitfield.imm8 = 1;
4422 i.types[op].bitfield.imm8s = 1;
4423 i.types[op].bitfield.imm16 = 1;
4424 i.types[op].bitfield.imm32 = 1;
4425 i.types[op].bitfield.imm32s = 1;
4426 i.types[op].bitfield.imm64 = 1;
29b0f896 4427 break;
252b5132 4428 }
252b5132 4429
29b0f896
AM		 4430 /* If this operand is at most 16 bits, convert it
4431 to a signed 16 bit number before trying to see
4432 whether it will fit in an even smaller size.
4433 This allows a 16-bit operand such as $0xffe0 to
4434 be recognised as within Imm8S range. */
40fb9820 4435 if ((i.types[op].bitfield.imm16)
29b0f896 4436 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4437 {
29b0f896
AM		 4438 i.op[op].imms->X_add_number =
4439 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4440 }
a28def75
L		 4441#ifdef BFD64
4442 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
40fb9820 4443 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4444 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4445 == 0))
4446 {
4447 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4448 ^ ((offsetT) 1 << 31))
4449 - ((offsetT) 1 << 31));
4450 }
a28def75 4451#endif
40fb9820 4452 i.types[op]
c6fb90c8
L		 4453 = operand_type_or (i.types[op],
4454 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4455
29b0f896
AM		 4456 /* We must avoid matching of Imm32 templates when 64bit
4457 only immediate is available. */
4458 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4459 i.types[op].bitfield.imm32 = 0;
29b0f896 4460 break;
252b5132 4461
29b0f896
AM		 4462 case O_absent:
4463 case O_register:
4464 abort ();
4465
4466 /* Symbols and expressions. */
4467 default:
9cd96992
JB		 4468 /* Convert symbolic operand to proper sizes for matching, but don't
4469 prevent matching a set of insns that only supports sizes other
4470 than those matching the insn suffix. */
4471 {
40fb9820 4472 i386_operand_type mask, allowed;
d3ce72d0 4473 const insn_template *t;
9cd96992 4474
0dfbf9d7
L		 4475 operand_type_set (&mask, 0);
4476 operand_type_set (&allowed, 0);
40fb9820 4477
4eed87de
AM		 4478 for (t = current_templates->start;
4479 t < current_templates->end;
4480 ++t)
c6fb90c8
L		 4481 allowed = operand_type_or (allowed,
4482 t->operand_types[op]);
9cd96992
JB		 4483 switch (guess_suffix)
4484 {
4485 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4486 mask.bitfield.imm64 = 1;
4487 mask.bitfield.imm32s = 1;
9cd96992
JB		 4488 break;
4489 case LONG_MNEM_SUFFIX:
40fb9820 4490 mask.bitfield.imm32 = 1;
9cd96992
JB		 4491 break;
4492 case WORD_MNEM_SUFFIX:
40fb9820 4493 mask.bitfield.imm16 = 1;
9cd96992
JB		 4494 break;
4495 case BYTE_MNEM_SUFFIX:
40fb9820 4496 mask.bitfield.imm8 = 1;
9cd96992
JB		 4497 break;
4498 default:
9cd96992
JB		 4499 break;
4500 }
c6fb90c8 4501 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4502 if (!operand_type_all_zero (&allowed))
c6fb90c8 4503 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4504 }
29b0f896 4505 break;
252b5132 4506 }
29b0f896
AM		 4507 }
4508}
47926f60 4509
29b0f896
AM		 4510/* Try to use the smallest displacement type too. */
4511static void
e3bb37b5 4512optimize_disp (void)
29b0f896
AM		 4513{
4514 int op;
3e73aa7c 4515
29b0f896 4516 for (op = i.operands; --op >= 0;)
40fb9820 4517 if (operand_type_check (i.types[op], disp))
252b5132 4518 {
b300c311 4519 if (i.op[op].disps->X_op == O_constant)
252b5132 4520 {
91d6fa6a 4521 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4522
40fb9820 4523 if (i.types[op].bitfield.disp16
91d6fa6a 4524 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4525 {
4526 /* If this operand is at most 16 bits, convert
4527 to a signed 16 bit number and don't use 64bit
4528 displacement. */
91d6fa6a 4529 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4530 i.types[op].bitfield.disp64 = 0;
b300c311 4531 }
a28def75
L		 4532#ifdef BFD64
4533 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
40fb9820 4534 if (i.types[op].bitfield.disp32
91d6fa6a 4535 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4536 {
4537 /* If this operand is at most 32 bits, convert
4538 to a signed 32 bit number and don't use 64bit
4539 displacement. */
91d6fa6a
NC		 4540 op_disp &= (((offsetT) 2 << 31) - 1);
4541 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4542 i.types[op].bitfield.disp64 = 0;
b300c311 4543 }
a28def75 4544#endif
91d6fa6a 4545 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4546 {
40fb9820
L		 4547 i.types[op].bitfield.disp8 = 0;
4548 i.types[op].bitfield.disp16 = 0;
4549 i.types[op].bitfield.disp32 = 0;
4550 i.types[op].bitfield.disp32s = 0;
4551 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4552 i.op[op].disps = 0;
4553 i.disp_operands--;
4554 }
4555 else if (flag_code == CODE_64BIT)
4556 {
91d6fa6a 4557 if (fits_in_signed_long (op_disp))
28a9d8f5 4558 {
40fb9820
L		 4559 i.types[op].bitfield.disp64 = 0;
4560 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4561 }
0e1147d9 4562 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4563 && fits_in_unsigned_long (op_disp))
40fb9820 4564 i.types[op].bitfield.disp32 = 1;
b300c311 4565 }
40fb9820
L		 4566 if ((i.types[op].bitfield.disp32
4567 || i.types[op].bitfield.disp32s
4568 || i.types[op].bitfield.disp16)
91d6fa6a 4569 && fits_in_signed_byte (op_disp))
40fb9820 4570 i.types[op].bitfield.disp8 = 1;
252b5132 4571 }
67a4f2b7
AO		 4572 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4573 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4574 {
4575 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4576 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4577 i.types[op].bitfield.disp8 = 0;
4578 i.types[op].bitfield.disp16 = 0;
4579 i.types[op].bitfield.disp32 = 0;
4580 i.types[op].bitfield.disp32s = 0;
4581 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4582 }
4583 else
b300c311 4584 /* We only support 64bit displacement on constants. */
40fb9820 4585 i.types[op].bitfield.disp64 = 0;
252b5132 4586 }
29b0f896
AM		 4587}
4588
6c30d220
L		 4589/* Check if operands are valid for the instruction. */
4590
4591static int
4592check_VecOperands (const insn_template *t)
4593{
43234a1e
L		 4594 unsigned int op;
4595
6c30d220
L		 4596 /* Without VSIB byte, we can't have a vector register for index. */
4597 if (!t->opcode_modifier.vecsib
4598 && i.index_reg
4599 && (i.index_reg->reg_type.bitfield.regxmm
43234a1e
L		 4600 || i.index_reg->reg_type.bitfield.regymm
4601 || i.index_reg->reg_type.bitfield.regzmm))
6c30d220
L		 4602 {
4603 i.error = unsupported_vector_index_register;
4604 return 1;
4605 }
4606
ad8ecc81
MZ		 4607 /* Check if default mask is allowed. */
4608 if (t->opcode_modifier.nodefmask
4609 && (!i.mask || i.mask->mask->reg_num == 0))
4610 {
4611 i.error = no_default_mask;
4612 return 1;
4613 }
4614
7bab8ab5
JB		 4615 /* For VSIB byte, we need a vector register for index, and all vector
4616 registers must be distinct. */
4617 if (t->opcode_modifier.vecsib)
4618 {
4619 if (!i.index_reg
6c30d220
L		 4620 || !((t->opcode_modifier.vecsib == VecSIB128
4621 && i.index_reg->reg_type.bitfield.regxmm)
4622 || (t->opcode_modifier.vecsib == VecSIB256
43234a1e
L		 4623 && i.index_reg->reg_type.bitfield.regymm)
4624 || (t->opcode_modifier.vecsib == VecSIB512
4625 && i.index_reg->reg_type.bitfield.regzmm)))
7bab8ab5
JB		 4626 {
4627 i.error = invalid_vsib_address;
4628 return 1;
4629 }
4630
43234a1e
L		 4631 gas_assert (i.reg_operands == 2 || i.mask);
4632 if (i.reg_operands == 2 && !i.mask)
4633 {
4634 gas_assert (i.types[0].bitfield.regxmm
7c84a0ca 4635 || i.types[0].bitfield.regymm);
43234a1e 4636 gas_assert (i.types[2].bitfield.regxmm
7c84a0ca 4637 || i.types[2].bitfield.regymm);
43234a1e
L		 4638 if (operand_check == check_none)
4639 return 0;
4640 if (register_number (i.op[0].regs)
4641 != register_number (i.index_reg)
4642 && register_number (i.op[2].regs)
4643 != register_number (i.index_reg)
4644 && register_number (i.op[0].regs)
4645 != register_number (i.op[2].regs))
4646 return 0;
4647 if (operand_check == check_error)
4648 {
4649 i.error = invalid_vector_register_set;
4650 return 1;
4651 }
4652 as_warn (_("mask, index, and destination registers should be distinct"));
4653 }
8444f82a
MZ		 4654 else if (i.reg_operands == 1 && i.mask)
4655 {
4656 if ((i.types[1].bitfield.regymm
4657 || i.types[1].bitfield.regzmm)
4658 && (register_number (i.op[1].regs)
4659 == register_number (i.index_reg)))
4660 {
4661 if (operand_check == check_error)
4662 {
4663 i.error = invalid_vector_register_set;
4664 return 1;
4665 }
4666 if (operand_check != check_none)
4667 as_warn (_("index and destination registers should be distinct"));
4668 }
4669 }
43234a1e 4670 }
7bab8ab5 4671
43234a1e
L		 4672 /* Check if broadcast is supported by the instruction and is applied
4673 to the memory operand. */
4674 if (i.broadcast)
4675 {
4676 int broadcasted_opnd_size;
4677
4678 /* Check if specified broadcast is supported in this instruction,
4679 and it's applied to memory operand of DWORD or QWORD type,
4680 depending on VecESize. */
4681 if (i.broadcast->type != t->opcode_modifier.broadcast
4682 || !i.types[i.broadcast->operand].bitfield.mem
4683 || (t->opcode_modifier.vecesize == 0
4684 && !i.types[i.broadcast->operand].bitfield.dword
4685 && !i.types[i.broadcast->operand].bitfield.unspecified)
4686 || (t->opcode_modifier.vecesize == 1
4687 && !i.types[i.broadcast->operand].bitfield.qword
4688 && !i.types[i.broadcast->operand].bitfield.unspecified))
4689 goto bad_broadcast;
4690
4691 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4692 if (i.broadcast->type == BROADCAST_1TO16)
4693 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4694 else if (i.broadcast->type == BROADCAST_1TO8)
4695 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
b28d1bda
IT		 4696 else if (i.broadcast->type == BROADCAST_1TO4)
4697 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4698 else if (i.broadcast->type == BROADCAST_1TO2)
4699 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
43234a1e
L		 4700 else
4701 goto bad_broadcast;
4702
4703 if ((broadcasted_opnd_size == 256
4704 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4705 || (broadcasted_opnd_size == 512
4706 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4707 {
4708 bad_broadcast:
4709 i.error = unsupported_broadcast;
4710 return 1;
4711 }
4712 }
4713 /* If broadcast is supported in this instruction, we need to check if
4714 operand of one-element size isn't specified without broadcast. */
4715 else if (t->opcode_modifier.broadcast && i.mem_operands)
4716 {
4717 /* Find memory operand. */
4718 for (op = 0; op < i.operands; op++)
4719 if (operand_type_check (i.types[op], anymem))
4720 break;
4721 gas_assert (op < i.operands);
4722 /* Check size of the memory operand. */
4723 if ((t->opcode_modifier.vecesize == 0
4724 && i.types[op].bitfield.dword)
4725 || (t->opcode_modifier.vecesize == 1
4726 && i.types[op].bitfield.qword))
4727 {
4728 i.error = broadcast_needed;
4729 return 1;
4730 }
4731 }
4732
4733 /* Check if requested masking is supported. */
4734 if (i.mask
4735 && (!t->opcode_modifier.masking
4736 || (i.mask->zeroing
4737 && t->opcode_modifier.masking == MERGING_MASKING)))
4738 {
4739 i.error = unsupported_masking;
4740 return 1;
4741 }
4742
4743 /* Check if masking is applied to dest operand. */
4744 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4745 {
4746 i.error = mask_not_on_destination;
4747 return 1;
4748 }
4749
43234a1e
L		 4750 /* Check RC/SAE. */
4751 if (i.rounding)
4752 {
4753 if ((i.rounding->type != saeonly
4754 && !t->opcode_modifier.staticrounding)
4755 || (i.rounding->type == saeonly
4756 && (t->opcode_modifier.staticrounding
4757 || !t->opcode_modifier.sae)))
4758 {
4759 i.error = unsupported_rc_sae;
4760 return 1;
4761 }
4762 /* If the instruction has several immediate operands and one of
4763 them is rounding, the rounding operand should be the last
4764 immediate operand. */
4765 if (i.imm_operands > 1
4766 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4767 {
43234a1e 4768 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4769 return 1;
4770 }
6c30d220
L		 4771 }
4772
43234a1e
L		 4773 /* Check vector Disp8 operand. */
4774 if (t->opcode_modifier.disp8memshift)
4775 {
4776 if (i.broadcast)
4777 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4778 else
4779 i.memshift = t->opcode_modifier.disp8memshift;
4780
4781 for (op = 0; op < i.operands; op++)
4782 if (operand_type_check (i.types[op], disp)
4783 && i.op[op].disps->X_op == O_constant)
4784 {
4785 offsetT value = i.op[op].disps->X_add_number;
5be33403
L		 4786 int vec_disp8_ok
4787 = (i.disp_encoding != disp_encoding_32bit
4788 && fits_in_vec_disp8 (value));
43234a1e
L		 4789 if (t->operand_types [op].bitfield.vec_disp8)
4790 {
4791 if (vec_disp8_ok)
4792 i.types[op].bitfield.vec_disp8 = 1;
4793 else
4794 {
4795 /* Vector insn can only have Vec_Disp8/Disp32 in
4796 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4797 mode. */
4798 i.types[op].bitfield.disp8 = 0;
4799 if (flag_code != CODE_16BIT)
4800 i.types[op].bitfield.disp16 = 0;
4801 }
4802 }
4803 else if (flag_code != CODE_16BIT)
4804 {
4805 /* One form of this instruction supports vector Disp8.
4806 Try vector Disp8 if we need to use Disp32. */
4807 if (vec_disp8_ok && !fits_in_signed_byte (value))
4808 {
4809 i.error = try_vector_disp8;
4810 return 1;
4811 }
4812 }
4813 }
4814 }
4815 else
4816 i.memshift = -1;
4817
6c30d220
L		 4818 return 0;
4819}
4820
43f3e2ee 4821/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4822 operand types. */
4823
4824static int
4825VEX_check_operands (const insn_template *t)
4826{
86fa6981 4827 if (i.vec_encoding == vex_encoding_evex)
43234a1e 4828 {
86fa6981
L		 4829 /* This instruction must be encoded with EVEX prefix. */
4830 if (!t->opcode_modifier.evex)
4831 {
4832 i.error = unsupported;
4833 return 1;
4834 }
4835 return 0;
43234a1e
L		 4836 }
4837
a683cc34 4838 if (!t->opcode_modifier.vex)
86fa6981
L		 4839 {
4840 /* This instruction template doesn't have VEX prefix. */
4841 if (i.vec_encoding != vex_encoding_default)
4842 {
4843 i.error = unsupported;
4844 return 1;
4845 }
4846 return 0;
4847 }
a683cc34
SP		 4848
4849 /* Only check VEX_Imm4, which must be the first operand. */
4850 if (t->operand_types[0].bitfield.vec_imm4)
4851 {
4852 if (i.op[0].imms->X_op != O_constant
4853 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4854 {
a65babc9 4855 i.error = bad_imm4;
891edac4
L		 4856 return 1;
4857 }
a683cc34
SP		 4858
4859 /* Turn off Imm8 so that update_imm won't complain. */
4860 i.types[0] = vec_imm4;
4861 }
4862
4863 return 0;
4864}
4865
d3ce72d0 4866static const insn_template *
83b16ac6 4867match_template (char mnem_suffix)
29b0f896
AM		 4868{
4869 /* Points to template once we've found it. */
d3ce72d0 4870 const insn_template *t;
40fb9820 4871 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4872 i386_operand_type overlap4;
29b0f896 4873 unsigned int found_reverse_match;
83b16ac6 4874 i386_opcode_modifier suffix_check, mnemsuf_check;
40fb9820 4875 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4876 int addr_prefix_disp;
a5c311ca 4877 unsigned int j;
3629bb00 4878 unsigned int found_cpu_match;
45664ddb 4879 unsigned int check_register;
5614d22c 4880 enum i386_error specific_error = 0;
29b0f896 4881
c0f3af97
L		 4882#if MAX_OPERANDS != 5
4883# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4884#endif
4885
29b0f896 4886 found_reverse_match = 0;
539e75ad 4887 addr_prefix_disp = -1;
40fb9820
L		 4888
4889 memset (&suffix_check, 0, sizeof (suffix_check));
4890 if (i.suffix == BYTE_MNEM_SUFFIX)
4891 suffix_check.no_bsuf = 1;
4892 else if (i.suffix == WORD_MNEM_SUFFIX)
4893 suffix_check.no_wsuf = 1;
4894 else if (i.suffix == SHORT_MNEM_SUFFIX)
4895 suffix_check.no_ssuf = 1;
4896 else if (i.suffix == LONG_MNEM_SUFFIX)
4897 suffix_check.no_lsuf = 1;
4898 else if (i.suffix == QWORD_MNEM_SUFFIX)
4899 suffix_check.no_qsuf = 1;
4900 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4901 suffix_check.no_ldsuf = 1;
29b0f896 4902
83b16ac6
JB		 4903 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
4904 if (intel_syntax)
4905 {
4906 switch (mnem_suffix)
4907 {
4908 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
4909 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
4910 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
4911 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
4912 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
4913 }
4914 }
4915
01559ecc
L		 4916 /* Must have right number of operands. */
4917 i.error = number_of_operands_mismatch;
4918
45aa61fe 4919 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4920 {
539e75ad
L		 4921 addr_prefix_disp = -1;
4922
29b0f896
AM		 4923 if (i.operands != t->operands)
4924 continue;
4925
50aecf8c 4926 /* Check processor support. */
a65babc9 4927 i.error = unsupported;
c0f3af97
L		 4928 found_cpu_match = (cpu_flags_match (t)
4929 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4930 if (!found_cpu_match)
4931 continue;
4932
e1d4d893 4933 /* Check old gcc support. */
a65babc9 4934 i.error = old_gcc_only;
e1d4d893
L		 4935 if (!old_gcc && t->opcode_modifier.oldgcc)
4936 continue;
4937
4938 /* Check AT&T mnemonic. */
a65babc9 4939 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4940 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4941 continue;
4942
e92bae62 4943 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
a65babc9 4944 i.error = unsupported_syntax;
5c07affc 4945 if ((intel_syntax && t->opcode_modifier.attsyntax)
e92bae62
L		 4946 || (!intel_syntax && t->opcode_modifier.intelsyntax)
4947 || (intel64 && t->opcode_modifier.amd64)
4948 || (!intel64 && t->opcode_modifier.intel64))
1efbbeb4
L		 4949 continue;
4950
20592a94 4951 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4952 i.error = invalid_instruction_suffix;
567e4e96
L		 4953 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4954 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4955 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4956 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4957 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4958 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4959 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896 4960 continue;
83b16ac6
JB		 4961 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
4962 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
4963 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
4964 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
4965 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
4966 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
4967 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
4968 continue;
29b0f896 4969
5c07affc 4970 if (!operand_size_match (t))
7d5e4556 4971 continue;
539e75ad 4972
5c07affc
L		 4973 for (j = 0; j < MAX_OPERANDS; j++)
4974 operand_types[j] = t->operand_types[j];
4975
45aa61fe
AM		 4976 /* In general, don't allow 64-bit operands in 32-bit mode. */
4977 if (i.suffix == QWORD_MNEM_SUFFIX
4978 && flag_code != CODE_64BIT
4979 && (intel_syntax
40fb9820 4980 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4981 && !intel_float_operand (t->name))
4982 : intel_float_operand (t->name) != 2)
40fb9820 4983 && ((!operand_types[0].bitfield.regmmx
c0f3af97 4984 && !operand_types[0].bitfield.regxmm
43234a1e
L		 4985 && !operand_types[0].bitfield.regymm
4986 && !operand_types[0].bitfield.regzmm)
40fb9820 4987 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736
AM		 4988 && operand_types[t->operands > 1].bitfield.regxmm
4989 && operand_types[t->operands > 1].bitfield.regymm
4990 && operand_types[t->operands > 1].bitfield.regzmm))
45aa61fe
AM		 4991 && (t->base_opcode != 0x0fc7
4992 || t->extension_opcode != 1 /* cmpxchg8b */))
4993 continue;
4994
192dc9c6
JB		 4995 /* In general, don't allow 32-bit operands on pre-386. */
4996 else if (i.suffix == LONG_MNEM_SUFFIX
4997 && !cpu_arch_flags.bitfield.cpui386
4998 && (intel_syntax
4999 ? (!t->opcode_modifier.ignoresize
5000 && !intel_float_operand (t->name))
5001 : intel_float_operand (t->name) != 2)
5002 && ((!operand_types[0].bitfield.regmmx
5003 && !operand_types[0].bitfield.regxmm)
5004 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736 5005 && operand_types[t->operands > 1].bitfield.regxmm)))
192dc9c6
JB		 5006 continue;
5007
29b0f896 5008 /* Do not verify operands when there are none. */
50aecf8c 5009 else
29b0f896 5010 {
c6fb90c8 5011 if (!t->operands)
2dbab7d5
L		 5012 /* We've found a match; break out of loop. */
5013 break;
29b0f896 5014 }
252b5132 5015
539e75ad
L		 5016 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5017 into Disp32/Disp16/Disp32 operand. */
5018 if (i.prefix[ADDR_PREFIX] != 0)
5019 {
40fb9820 5020 /* There should be only one Disp operand. */
539e75ad
L		 5021 switch (flag_code)
5022 {
5023 case CODE_16BIT:
40fb9820
L		 5024 for (j = 0; j < MAX_OPERANDS; j++)
5025 {
5026 if (operand_types[j].bitfield.disp16)
5027 {
5028 addr_prefix_disp = j;
5029 operand_types[j].bitfield.disp32 = 1;
5030 operand_types[j].bitfield.disp16 = 0;
5031 break;
5032 }
5033 }
539e75ad
L		 5034 break;
5035 case CODE_32BIT:
40fb9820
L		 5036 for (j = 0; j < MAX_OPERANDS; j++)
5037 {
5038 if (operand_types[j].bitfield.disp32)
5039 {
5040 addr_prefix_disp = j;
5041 operand_types[j].bitfield.disp32 = 0;
5042 operand_types[j].bitfield.disp16 = 1;
5043 break;
5044 }
5045 }
539e75ad
L		 5046 break;
5047 case CODE_64BIT:
40fb9820
L		 5048 for (j = 0; j < MAX_OPERANDS; j++)
5049 {
5050 if (operand_types[j].bitfield.disp64)
5051 {
5052 addr_prefix_disp = j;
5053 operand_types[j].bitfield.disp64 = 0;
5054 operand_types[j].bitfield.disp32 = 1;
5055 break;
5056 }
5057 }
539e75ad
L		 5058 break;
5059 }
539e75ad
L		 5060 }
5061
02a86693
L		 5062 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5063 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5064 continue;
5065
56ffb741
L		 5066 /* We check register size if needed. */
5067 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 5068 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 5069 switch (t->operands)
5070 {
5071 case 1:
40fb9820 5072 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 5073 continue;
5074 break;
5075 case 2:
33eaf5de 5076 /* xchg %eax, %eax is a special case. It is an alias for nop
8b38ad71
L		 5077 only in 32bit mode and we can use opcode 0x90. In 64bit
5078 mode, we can't use 0x90 for xchg %eax, %eax since it should
5079 zero-extend %eax to %rax. */
5080 if (flag_code == CODE_64BIT
5081 && t->base_opcode == 0x90
0dfbf9d7
L		 5082 && operand_type_equal (&i.types [0], &acc32)
5083 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 5084 continue;
86fa6981
L		 5085 /* If we want store form, we reverse direction of operands. */
5086 if (i.dir_encoding == dir_encoding_store
5087 && t->opcode_modifier.d)
5088 goto check_reverse;
1a0670f3 5089 /* Fall through. */
b6169b20 5090
29b0f896 5091 case 3:
86fa6981
L		 5092 /* If we want store form, we skip the current load. */
5093 if (i.dir_encoding == dir_encoding_store
5094 && i.mem_operands == 0
5095 && t->opcode_modifier.load)
fa99fab2 5096 continue;
1a0670f3 5097 /* Fall through. */
f48ff2ae 5098 case 4:
c0f3af97 5099 case 5:
c6fb90c8 5100 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 5101 if (!operand_type_match (overlap0, i.types[0])
5102 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 5103 || (check_register
5104 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 5105 operand_types[0],
5106 overlap1, i.types[1],
5107 operand_types[1])))
29b0f896
AM		 5108 {
5109 /* Check if other direction is valid ... */
40fb9820 5110 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 5111 continue;
5112
b6169b20 5113check_reverse:
29b0f896 5114 /* Try reversing direction of operands. */
c6fb90c8
L		 5115 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5116 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 5117 if (!operand_type_match (overlap0, i.types[0])
5118 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 5119 || (check_register
5120 && !operand_type_register_match (overlap0,
5121 i.types[0],
5122 operand_types[1],
5123 overlap1,
5124 i.types[1],
5125 operand_types[0])))
29b0f896
AM		 5126 {
5127 /* Does not match either direction. */
5128 continue;
5129 }
5130 /* found_reverse_match holds which of D or FloatDR
5131 we've found. */
40fb9820 5132 if (t->opcode_modifier.d)
8a2ed489 5133 found_reverse_match = Opcode_D;
40fb9820 5134 else if (t->opcode_modifier.floatd)
8a2ed489
L		 5135 found_reverse_match = Opcode_FloatD;
5136 else
5137 found_reverse_match = 0;
40fb9820 5138 if (t->opcode_modifier.floatr)
8a2ed489 5139 found_reverse_match |= Opcode_FloatR;
29b0f896 5140 }
f48ff2ae 5141 else
29b0f896 5142 {
f48ff2ae 5143 /* Found a forward 2 operand match here. */
d1cbb4db
L		 5144 switch (t->operands)
5145 {
c0f3af97
L		 5146 case 5:
5147 overlap4 = operand_type_and (i.types[4],
5148 operand_types[4]);
1a0670f3 5149 /* Fall through. */
d1cbb4db 5150 case 4:
c6fb90c8
L		 5151 overlap3 = operand_type_and (i.types[3],
5152 operand_types[3]);
1a0670f3 5153 /* Fall through. */
d1cbb4db 5154 case 3:
c6fb90c8
L		 5155 overlap2 = operand_type_and (i.types[2],
5156 operand_types[2]);
d1cbb4db
L		 5157 break;
5158 }
29b0f896 5159
f48ff2ae
L		 5160 switch (t->operands)
5161 {
c0f3af97
L		 5162 case 5:
5163 if (!operand_type_match (overlap4, i.types[4])
5164 || !operand_type_register_match (overlap3,
5165 i.types[3],
5166 operand_types[3],
5167 overlap4,
5168 i.types[4],
5169 operand_types[4]))
5170 continue;
1a0670f3 5171 /* Fall through. */
f48ff2ae 5172 case 4:
40fb9820 5173 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 5174 || (check_register
5175 && !operand_type_register_match (overlap2,
5176 i.types[2],
5177 operand_types[2],
5178 overlap3,
5179 i.types[3],
5180 operand_types[3])))
f48ff2ae 5181 continue;
1a0670f3 5182 /* Fall through. */
f48ff2ae
L		 5183 case 3:
5184 /* Here we make use of the fact that there are no
5185 reverse match 3 operand instructions, and all 3
5186 operand instructions only need to be checked for
5187 register consistency between operands 2 and 3. */
40fb9820 5188 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 5189 || (check_register
5190 && !operand_type_register_match (overlap1,
5191 i.types[1],
5192 operand_types[1],
5193 overlap2,
5194 i.types[2],
5195 operand_types[2])))
f48ff2ae
L		 5196 continue;
5197 break;
5198 }
29b0f896 5199 }
f48ff2ae 5200 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 5201 slip through to break. */
5202 }
3629bb00 5203 if (!found_cpu_match)
29b0f896
AM		 5204 {
5205 found_reverse_match = 0;
5206 continue;
5207 }
c0f3af97 5208
5614d22c
JB		 5209 /* Check if vector and VEX operands are valid. */
5210 if (check_VecOperands (t) || VEX_check_operands (t))
5211 {
5212 specific_error = i.error;
5213 continue;
5214 }
a683cc34 5215
29b0f896
AM		 5216 /* We've found a match; break out of loop. */
5217 break;
5218 }
5219
5220 if (t == current_templates->end)
5221 {
5222 /* We found no match. */
a65babc9 5223 const char *err_msg;
5614d22c 5224 switch (specific_error ? specific_error : i.error)
a65babc9
L		 5225 {
5226 default:
5227 abort ();
86e026a4 5228 case operand_size_mismatch:
a65babc9
L		 5229 err_msg = _("operand size mismatch");
5230 break;
5231 case operand_type_mismatch:
5232 err_msg = _("operand type mismatch");
5233 break;
5234 case register_type_mismatch:
5235 err_msg = _("register type mismatch");
5236 break;
5237 case number_of_operands_mismatch:
5238 err_msg = _("number of operands mismatch");
5239 break;
5240 case invalid_instruction_suffix:
5241 err_msg = _("invalid instruction suffix");
5242 break;
5243 case bad_imm4:
4a2608e3 5244 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 5245 break;
5246 case old_gcc_only:
5247 err_msg = _("only supported with old gcc");
5248 break;
5249 case unsupported_with_intel_mnemonic:
5250 err_msg = _("unsupported with Intel mnemonic");
5251 break;
5252 case unsupported_syntax:
5253 err_msg = _("unsupported syntax");
5254 break;
5255 case unsupported:
35262a23 5256 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 5257 current_templates->start->name);
5258 return NULL;
6c30d220
L		 5259 case invalid_vsib_address:
5260 err_msg = _("invalid VSIB address");
5261 break;
7bab8ab5
JB		 5262 case invalid_vector_register_set:
5263 err_msg = _("mask, index, and destination registers must be distinct");
5264 break;
6c30d220
L		 5265 case unsupported_vector_index_register:
5266 err_msg = _("unsupported vector index register");
5267 break;
43234a1e
L		 5268 case unsupported_broadcast:
5269 err_msg = _("unsupported broadcast");
5270 break;
5271 case broadcast_not_on_src_operand:
5272 err_msg = _("broadcast not on source memory operand");
5273 break;
5274 case broadcast_needed:
5275 err_msg = _("broadcast is needed for operand of such type");
5276 break;
5277 case unsupported_masking:
5278 err_msg = _("unsupported masking");
5279 break;
5280 case mask_not_on_destination:
5281 err_msg = _("mask not on destination operand");
5282 break;
5283 case no_default_mask:
5284 err_msg = _("default mask isn't allowed");
5285 break;
5286 case unsupported_rc_sae:
5287 err_msg = _("unsupported static rounding/sae");
5288 break;
5289 case rc_sae_operand_not_last_imm:
5290 if (intel_syntax)
5291 err_msg = _("RC/SAE operand must precede immediate operands");
5292 else
5293 err_msg = _("RC/SAE operand must follow immediate operands");
5294 break;
5295 case invalid_register_operand:
5296 err_msg = _("invalid register operand");
5297 break;
a65babc9
L		 5298 }
5299 as_bad (_("%s for `%s'"), err_msg,
891edac4 5300 current_templates->start->name);
fa99fab2 5301 return NULL;
29b0f896 5302 }
252b5132 5303
29b0f896
AM		 5304 if (!quiet_warnings)
5305 {
5306 if (!intel_syntax
40fb9820
L		 5307 && (i.types[0].bitfield.jumpabsolute
5308 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5309 {
5310 as_warn (_("indirect %s without `*'"), t->name);
5311 }
5312
40fb9820
L		 5313 if (t->opcode_modifier.isprefix
5314 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5315 {
5316 /* Warn them that a data or address size prefix doesn't
5317 affect assembly of the next line of code. */
5318 as_warn (_("stand-alone `%s' prefix"), t->name);
5319 }
5320 }
5321
5322 /* Copy the template we found. */
5323 i.tm = *t;
539e75ad
L		 5324
5325 if (addr_prefix_disp != -1)
5326 i.tm.operand_types[addr_prefix_disp]
5327 = operand_types[addr_prefix_disp];
5328
29b0f896
AM		 5329 if (found_reverse_match)
5330 {
5331 /* If we found a reverse match we must alter the opcode
5332 direction bit. found_reverse_match holds bits to change
5333 (different for int & float insns). */
5334
5335 i.tm.base_opcode ^= found_reverse_match;
5336
539e75ad
L		 5337 i.tm.operand_types[0] = operand_types[1];
5338 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5339 }
5340
fa99fab2 5341 return t;
29b0f896
AM		 5342}
5343
5344static int
e3bb37b5 5345check_string (void)
29b0f896 5346{
40fb9820
L		 5347 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5348 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5349 {
5350 if (i.seg[0] != NULL && i.seg[0] != &es)
5351 {
a87af027 5352 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5353 i.tm.name,
a87af027
JB		 5354 mem_op + 1,
5355 register_prefix);
29b0f896
AM		 5356 return 0;
5357 }
5358 /* There's only ever one segment override allowed per instruction.
5359 This instruction possibly has a legal segment override on the
5360 second operand, so copy the segment to where non-string
5361 instructions store it, allowing common code. */
5362 i.seg[0] = i.seg[1];
5363 }
40fb9820 5364 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5365 {
5366 if (i.seg[1] != NULL && i.seg[1] != &es)
5367 {
a87af027 5368 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5369 i.tm.name,
a87af027
JB		 5370 mem_op + 2,
5371 register_prefix);
29b0f896
AM		 5372 return 0;
5373 }
5374 }
5375 return 1;
5376}
5377
5378static int
543613e9 5379process_suffix (void)
29b0f896
AM		 5380{
5381 /* If matched instruction specifies an explicit instruction mnemonic
5382 suffix, use it. */
40fb9820
L		 5383 if (i.tm.opcode_modifier.size16)
5384 i.suffix = WORD_MNEM_SUFFIX;
5385 else if (i.tm.opcode_modifier.size32)
5386 i.suffix = LONG_MNEM_SUFFIX;
5387 else if (i.tm.opcode_modifier.size64)
5388 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5389 else if (i.reg_operands)
5390 {
5391 /* If there's no instruction mnemonic suffix we try to invent one
5392 based on register operands. */
5393 if (!i.suffix)
5394 {
5395 /* We take i.suffix from the last register operand specified,
5396 Destination register type is more significant than source
381d071f
L		 5397 register type. crc32 in SSE4.2 prefers source register
5398 type. */
5399 if (i.tm.base_opcode == 0xf20f38f1)
5400 {
40fb9820
L		 5401 if (i.types[0].bitfield.reg16)
5402 i.suffix = WORD_MNEM_SUFFIX;
5403 else if (i.types[0].bitfield.reg32)
5404 i.suffix = LONG_MNEM_SUFFIX;
5405 else if (i.types[0].bitfield.reg64)
5406 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5407 }
9344ff29 5408 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5409 {
40fb9820 5410 if (i.types[0].bitfield.reg8)
20592a94
L		 5411 i.suffix = BYTE_MNEM_SUFFIX;
5412 }
381d071f
L		 5413
5414 if (!i.suffix)
5415 {
5416 int op;
5417
20592a94
L		 5418 if (i.tm.base_opcode == 0xf20f38f1
5419 || i.tm.base_opcode == 0xf20f38f0)
5420 {
5421 /* We have to know the operand size for crc32. */
5422 as_bad (_("ambiguous memory operand size for `%s`"),
5423 i.tm.name);
5424 return 0;
5425 }
5426
381d071f 5427 for (op = i.operands; --op >= 0;)
40fb9820 5428 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 5429 {
40fb9820
L		 5430 if (i.types[op].bitfield.reg8)
5431 {
5432 i.suffix = BYTE_MNEM_SUFFIX;
5433 break;
5434 }
5435 else if (i.types[op].bitfield.reg16)
5436 {
5437 i.suffix = WORD_MNEM_SUFFIX;
5438 break;
5439 }
5440 else if (i.types[op].bitfield.reg32)
5441 {
5442 i.suffix = LONG_MNEM_SUFFIX;
5443 break;
5444 }
5445 else if (i.types[op].bitfield.reg64)
5446 {
5447 i.suffix = QWORD_MNEM_SUFFIX;
5448 break;
5449 }
381d071f
L		 5450 }
5451 }
29b0f896
AM		 5452 }
5453 else if (i.suffix == BYTE_MNEM_SUFFIX)
5454 {
2eb952a4
L		 5455 if (intel_syntax
5456 && i.tm.opcode_modifier.ignoresize
5457 && i.tm.opcode_modifier.no_bsuf)
5458 i.suffix = 0;
5459 else if (!check_byte_reg ())
29b0f896
AM		 5460 return 0;
5461 }
5462 else if (i.suffix == LONG_MNEM_SUFFIX)
5463 {
2eb952a4
L		 5464 if (intel_syntax
5465 && i.tm.opcode_modifier.ignoresize
5466 && i.tm.opcode_modifier.no_lsuf)
5467 i.suffix = 0;
5468 else if (!check_long_reg ())
29b0f896
AM		 5469 return 0;
5470 }
5471 else if (i.suffix == QWORD_MNEM_SUFFIX)
5472 {
955e1e6a
L		 5473 if (intel_syntax
5474 && i.tm.opcode_modifier.ignoresize
5475 && i.tm.opcode_modifier.no_qsuf)
5476 i.suffix = 0;
5477 else if (!check_qword_reg ())
29b0f896
AM		 5478 return 0;
5479 }
5480 else if (i.suffix == WORD_MNEM_SUFFIX)
5481 {
2eb952a4
L		 5482 if (intel_syntax
5483 && i.tm.opcode_modifier.ignoresize
5484 && i.tm.opcode_modifier.no_wsuf)
5485 i.suffix = 0;
5486 else if (!check_word_reg ())
29b0f896
AM		 5487 return 0;
5488 }
c0f3af97 5489 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5490 || i.suffix == YMMWORD_MNEM_SUFFIX
5491 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5492 {
43234a1e 5493 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5494 should check if it is a valid suffix. */
5495 }
40fb9820 5496 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5497 /* Do nothing if the instruction is going to ignore the prefix. */
5498 ;
5499 else
5500 abort ();
5501 }
40fb9820 5502 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5503 && !i.suffix
5504 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5505 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5506 {
5507 i.suffix = stackop_size;
5508 }
9306ca4a
JB		 5509 else if (intel_syntax
5510 && !i.suffix
40fb9820
L		 5511 && (i.tm.operand_types[0].bitfield.jumpabsolute
5512 || i.tm.opcode_modifier.jumpbyte
5513 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5514 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5515 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5516 {
5517 switch (flag_code)
5518 {
5519 case CODE_64BIT:
40fb9820 5520 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5521 {
5522 i.suffix = QWORD_MNEM_SUFFIX;
5523 break;
5524 }
1a0670f3 5525 /* Fall through. */
9306ca4a 5526 case CODE_32BIT:
40fb9820 5527 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5528 i.suffix = LONG_MNEM_SUFFIX;
5529 break;
5530 case CODE_16BIT:
40fb9820 5531 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5532 i.suffix = WORD_MNEM_SUFFIX;
5533 break;
5534 }
5535 }
252b5132 5536
9306ca4a 5537 if (!i.suffix)
29b0f896 5538 {
9306ca4a
JB		 5539 if (!intel_syntax)
5540 {
40fb9820 5541 if (i.tm.opcode_modifier.w)
9306ca4a 5542 {
4eed87de
AM		 5543 as_bad (_("no instruction mnemonic suffix given and "
5544 "no register operands; can't size instruction"));
9306ca4a
JB		 5545 return 0;
5546 }
5547 }
5548 else
5549 {
40fb9820 5550 unsigned int suffixes;
7ab9ffdd 5551
40fb9820
L		 5552 suffixes = !i.tm.opcode_modifier.no_bsuf;
5553 if (!i.tm.opcode_modifier.no_wsuf)
5554 suffixes |= 1 << 1;
5555 if (!i.tm.opcode_modifier.no_lsuf)
5556 suffixes |= 1 << 2;
fc4adea1 5557 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5558 suffixes |= 1 << 3;
5559 if (!i.tm.opcode_modifier.no_ssuf)
5560 suffixes |= 1 << 4;
5561 if (!i.tm.opcode_modifier.no_qsuf)
5562 suffixes |= 1 << 5;
5563
5564 /* There are more than suffix matches. */
5565 if (i.tm.opcode_modifier.w
9306ca4a 5566 || ((suffixes & (suffixes - 1))
40fb9820
L		 5567 && !i.tm.opcode_modifier.defaultsize
5568 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5569 {
5570 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5571 return 0;
5572 }
5573 }
29b0f896 5574 }
252b5132 5575
9306ca4a
JB		 5576 /* Change the opcode based on the operand size given by i.suffix;
5577 We don't need to change things for byte insns. */
5578
582d5edd
L		 5579 if (i.suffix
5580 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5581 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5582 && i.suffix != YMMWORD_MNEM_SUFFIX
5583 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5584 {
5585 /* It's not a byte, select word/dword operation. */
40fb9820 5586 if (i.tm.opcode_modifier.w)
29b0f896 5587 {
40fb9820 5588 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5589 i.tm.base_opcode |= 8;
5590 else
5591 i.tm.base_opcode |= 1;
5592 }
0f3f3d8b 5593
29b0f896
AM		 5594 /* Now select between word & dword operations via the operand
5595 size prefix, except for instructions that will ignore this
5596 prefix anyway. */
ca61edf2 5597 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5598 {
ca61edf2
L		 5599 /* The address size override prefix changes the size of the
5600 first operand. */
40fb9820
L		 5601 if ((flag_code == CODE_32BIT
5602 && i.op->regs[0].reg_type.bitfield.reg16)
5603 || (flag_code != CODE_32BIT
5604 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 5605 if (!add_prefix (ADDR_PREFIX_OPCODE))
5606 return 0;
5607 }
5608 else if (i.suffix != QWORD_MNEM_SUFFIX
5609 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5610 && !i.tm.opcode_modifier.ignoresize
5611 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5612 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5613 || (flag_code == CODE_64BIT
40fb9820 5614 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5615 {
5616 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5617
40fb9820 5618 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5619 prefix = ADDR_PREFIX_OPCODE;
252b5132 5620
29b0f896
AM		 5621 if (!add_prefix (prefix))
5622 return 0;
24eab124 5623 }
252b5132 5624
29b0f896
AM		 5625 /* Set mode64 for an operand. */
5626 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5627 && flag_code == CODE_64BIT
40fb9820 5628 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5629 {
5630 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5631 need rex64. cmpxchg8b is also a special case. */
5632 if (! (i.operands == 2
5633 && i.tm.base_opcode == 0x90
5634 && i.tm.extension_opcode == None
0dfbf9d7
L		 5635 && operand_type_equal (&i.types [0], &acc64)
5636 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5637 && ! (i.operands == 1
5638 && i.tm.base_opcode == 0xfc7
5639 && i.tm.extension_opcode == 1
40fb9820
L		 5640 && !operand_type_check (i.types [0], reg)
5641 && operand_type_check (i.types [0], anymem)))
f6bee062 5642 i.rex |= REX_W;
46e883c5 5643 }
3e73aa7c 5644
29b0f896
AM		 5645 /* Size floating point instruction. */
5646 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5647 if (i.tm.opcode_modifier.floatmf)
543613e9 5648 i.tm.base_opcode ^= 4;
29b0f896 5649 }
7ecd2f8b 5650
29b0f896
AM		 5651 return 1;
5652}
3e73aa7c 5653
29b0f896 5654static int
543613e9 5655check_byte_reg (void)
29b0f896
AM		 5656{
5657 int op;
543613e9 5658
29b0f896
AM		 5659 for (op = i.operands; --op >= 0;)
5660 {
5661 /* If this is an eight bit register, it's OK. If it's the 16 or
5662 32 bit version of an eight bit register, we will just use the
5663 low portion, and that's OK too. */
40fb9820 5664 if (i.types[op].bitfield.reg8)
29b0f896
AM		 5665 continue;
5666
5a819eb9
JB		 5667 /* I/O port address operands are OK too. */
5668 if (i.tm.operand_types[op].bitfield.inoutportreg)
5669 continue;
5670
9344ff29
L		 5671 /* crc32 doesn't generate this warning. */
5672 if (i.tm.base_opcode == 0xf20f38f0)
5673 continue;
5674
40fb9820
L		 5675 if ((i.types[op].bitfield.reg16
5676 || i.types[op].bitfield.reg32
5677 || i.types[op].bitfield.reg64)
5a819eb9
JB		 5678 && i.op[op].regs->reg_num < 4
5679 /* Prohibit these changes in 64bit mode, since the lowering
5680 would be more complicated. */
5681 && flag_code != CODE_64BIT)
29b0f896 5682 {
29b0f896 5683#if REGISTER_WARNINGS
5a819eb9 5684 if (!quiet_warnings)
a540244d
L		 5685 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5686 register_prefix,
40fb9820 5687 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 5688 ? REGNAM_AL - REGNAM_AX
5689 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5690 register_prefix,
29b0f896
AM		 5691 i.op[op].regs->reg_name,
5692 i.suffix);
5693#endif
5694 continue;
5695 }
5696 /* Any other register is bad. */
40fb9820
L		 5697 if (i.types[op].bitfield.reg16
5698 || i.types[op].bitfield.reg32
5699 || i.types[op].bitfield.reg64
5700 || i.types[op].bitfield.regmmx
5701 || i.types[op].bitfield.regxmm
c0f3af97 5702 || i.types[op].bitfield.regymm
43234a1e 5703 || i.types[op].bitfield.regzmm
40fb9820
L		 5704 || i.types[op].bitfield.sreg2
5705 || i.types[op].bitfield.sreg3
5706 || i.types[op].bitfield.control
5707 || i.types[op].bitfield.debug
5708 || i.types[op].bitfield.test
5709 || i.types[op].bitfield.floatreg
5710 || i.types[op].bitfield.floatacc)
29b0f896 5711 {
a540244d
L		 5712 as_bad (_("`%s%s' not allowed with `%s%c'"),
5713 register_prefix,
29b0f896
AM		 5714 i.op[op].regs->reg_name,
5715 i.tm.name,
5716 i.suffix);
5717 return 0;
5718 }
5719 }
5720 return 1;
5721}
5722
5723static int
e3bb37b5 5724check_long_reg (void)
29b0f896
AM		 5725{
5726 int op;
5727
5728 for (op = i.operands; --op >= 0;)
5729 /* Reject eight bit registers, except where the template requires
5730 them. (eg. movzb) */
40fb9820
L		 5731 if (i.types[op].bitfield.reg8
5732 && (i.tm.operand_types[op].bitfield.reg16
5733 || i.tm.operand_types[op].bitfield.reg32
5734 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5735 {
a540244d
L		 5736 as_bad (_("`%s%s' not allowed with `%s%c'"),
5737 register_prefix,
29b0f896
AM		 5738 i.op[op].regs->reg_name,
5739 i.tm.name,
5740 i.suffix);
5741 return 0;
5742 }
e4630f71 5743 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5744 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5745 && i.types[op].bitfield.reg16
5746 && (i.tm.operand_types[op].bitfield.reg32
5747 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5748 {
5749 /* Prohibit these changes in the 64bit mode, since the
5750 lowering is more complicated. */
5751 if (flag_code == CODE_64BIT)
252b5132 5752 {
2b5d6a91 5753 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5754 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5755 i.suffix);
5756 return 0;
252b5132 5757 }
29b0f896 5758#if REGISTER_WARNINGS
cecf1424
JB		 5759 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5760 register_prefix,
5761 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5762 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5763#endif
252b5132 5764 }
e4630f71 5765 /* Warn if the r prefix on a general reg is present. */
40fb9820
L		 5766 else if (i.types[op].bitfield.reg64
5767 && (i.tm.operand_types[op].bitfield.reg32
5768 || i.tm.operand_types[op].bitfield.acc))
252b5132 5769 {
34828aad 5770 if (intel_syntax
ca61edf2 5771 && i.tm.opcode_modifier.toqword
40fb9820 5772 && !i.types[0].bitfield.regxmm)
34828aad 5773 {
ca61edf2 5774 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5775 i.suffix = QWORD_MNEM_SUFFIX;
5776 }
5777 else
5778 {
2b5d6a91 5779 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5780 register_prefix, i.op[op].regs->reg_name,
5781 i.suffix);
5782 return 0;
5783 }
29b0f896
AM		 5784 }
5785 return 1;
5786}
252b5132 5787
29b0f896 5788static int
e3bb37b5 5789check_qword_reg (void)
29b0f896
AM		 5790{
5791 int op;
252b5132 5792
29b0f896
AM		 5793 for (op = i.operands; --op >= 0; )
5794 /* Reject eight bit registers, except where the template requires
5795 them. (eg. movzb) */
40fb9820
L		 5796 if (i.types[op].bitfield.reg8
5797 && (i.tm.operand_types[op].bitfield.reg16
5798 || i.tm.operand_types[op].bitfield.reg32
5799 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5800 {
a540244d
L		 5801 as_bad (_("`%s%s' not allowed with `%s%c'"),
5802 register_prefix,
29b0f896
AM		 5803 i.op[op].regs->reg_name,
5804 i.tm.name,
5805 i.suffix);
5806 return 0;
5807 }
e4630f71 5808 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 5809 else if ((i.types[op].bitfield.reg16
5810 || i.types[op].bitfield.reg32)
33d0ab95 5811 && (i.tm.operand_types[op].bitfield.reg64
40fb9820 5812 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5813 {
5814 /* Prohibit these changes in the 64bit mode, since the
5815 lowering is more complicated. */
34828aad 5816 if (intel_syntax
ca61edf2 5817 && i.tm.opcode_modifier.todword
40fb9820 5818 && !i.types[0].bitfield.regxmm)
34828aad 5819 {
ca61edf2 5820 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5821 i.suffix = LONG_MNEM_SUFFIX;
5822 }
5823 else
5824 {
2b5d6a91 5825 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5826 register_prefix, i.op[op].regs->reg_name,
5827 i.suffix);
5828 return 0;
5829 }
252b5132 5830 }
29b0f896
AM		 5831 return 1;
5832}
252b5132 5833
29b0f896 5834static int
e3bb37b5 5835check_word_reg (void)
29b0f896
AM		 5836{
5837 int op;
5838 for (op = i.operands; --op >= 0;)
5839 /* Reject eight bit registers, except where the template requires
5840 them. (eg. movzb) */
40fb9820
L		 5841 if (i.types[op].bitfield.reg8
5842 && (i.tm.operand_types[op].bitfield.reg16
5843 || i.tm.operand_types[op].bitfield.reg32
5844 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5845 {
a540244d
L		 5846 as_bad (_("`%s%s' not allowed with `%s%c'"),
5847 register_prefix,
29b0f896
AM		 5848 i.op[op].regs->reg_name,
5849 i.tm.name,
5850 i.suffix);
5851 return 0;
5852 }
e4630f71 5853 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5854 else if ((!quiet_warnings || flag_code == CODE_64BIT)
e4630f71
JB		 5855 && (i.types[op].bitfield.reg32
5856 || i.types[op].bitfield.reg64)
40fb9820
L		 5857 && (i.tm.operand_types[op].bitfield.reg16
5858 || i.tm.operand_types[op].bitfield.acc))
252b5132 5859 {
29b0f896
AM		 5860 /* Prohibit these changes in the 64bit mode, since the
5861 lowering is more complicated. */
5862 if (flag_code == CODE_64BIT)
252b5132 5863 {
2b5d6a91 5864 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5865 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5866 i.suffix);
5867 return 0;
252b5132 5868 }
29b0f896 5869#if REGISTER_WARNINGS
cecf1424
JB		 5870 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5871 register_prefix,
5872 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5873 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5874#endif
5875 }
5876 return 1;
5877}
252b5132 5878
29b0f896 5879static int
40fb9820 5880update_imm (unsigned int j)
29b0f896 5881{
bc0844ae 5882 i386_operand_type overlap = i.types[j];
40fb9820
L		 5883 if ((overlap.bitfield.imm8
5884 || overlap.bitfield.imm8s
5885 || overlap.bitfield.imm16
5886 || overlap.bitfield.imm32
5887 || overlap.bitfield.imm32s
5888 || overlap.bitfield.imm64)
0dfbf9d7
L		 5889 && !operand_type_equal (&overlap, &imm8)
5890 && !operand_type_equal (&overlap, &imm8s)
5891 && !operand_type_equal (&overlap, &imm16)
5892 && !operand_type_equal (&overlap, &imm32)
5893 && !operand_type_equal (&overlap, &imm32s)
5894 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5895 {
5896 if (i.suffix)
5897 {
40fb9820
L		 5898 i386_operand_type temp;
5899
0dfbf9d7 5900 operand_type_set (&temp, 0);
7ab9ffdd 5901 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5902 {
5903 temp.bitfield.imm8 = overlap.bitfield.imm8;
5904 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5905 }
5906 else if (i.suffix == WORD_MNEM_SUFFIX)
5907 temp.bitfield.imm16 = overlap.bitfield.imm16;
5908 else if (i.suffix == QWORD_MNEM_SUFFIX)
5909 {
5910 temp.bitfield.imm64 = overlap.bitfield.imm64;
5911 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5912 }
5913 else
5914 temp.bitfield.imm32 = overlap.bitfield.imm32;
5915 overlap = temp;
29b0f896 5916 }
0dfbf9d7
L		 5917 else if (operand_type_equal (&overlap, &imm16_32_32s)
5918 || operand_type_equal (&overlap, &imm16_32)
5919 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5920 {
40fb9820 5921 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5922 overlap = imm16;
40fb9820 5923 else
65da13b5 5924 overlap = imm32s;
29b0f896 5925 }
0dfbf9d7
L		 5926 if (!operand_type_equal (&overlap, &imm8)
5927 && !operand_type_equal (&overlap, &imm8s)
5928 && !operand_type_equal (&overlap, &imm16)
5929 && !operand_type_equal (&overlap, &imm32)
5930 && !operand_type_equal (&overlap, &imm32s)
5931 && !operand_type_equal (&overlap, &imm64))
29b0f896 5932 {
4eed87de
AM		 5933 as_bad (_("no instruction mnemonic suffix given; "
5934 "can't determine immediate size"));
29b0f896
AM		 5935 return 0;
5936 }
5937 }
40fb9820 5938 i.types[j] = overlap;
29b0f896 5939
40fb9820
L		 5940 return 1;
5941}
5942
5943static int
5944finalize_imm (void)
5945{
bc0844ae 5946 unsigned int j, n;
29b0f896 5947
bc0844ae
L		 5948 /* Update the first 2 immediate operands. */
5949 n = i.operands > 2 ? 2 : i.operands;
5950 if (n)
5951 {
5952 for (j = 0; j < n; j++)
5953 if (update_imm (j) == 0)
5954 return 0;
40fb9820 5955
bc0844ae
L		 5956 /* The 3rd operand can't be immediate operand. */
5957 gas_assert (operand_type_check (i.types[2], imm) == 0);
5958 }
29b0f896
AM		 5959
5960 return 1;
5961}
5962
c0f3af97
L		 5963static int
5964bad_implicit_operand (int xmm)
5965{
91d6fa6a
NC		 5966 const char *ireg = xmm ? "xmm0" : "ymm0";
5967
c0f3af97
L		 5968 if (intel_syntax)
5969 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5970 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5971 else
5972 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5973 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5974 return 0;
5975}
5976
29b0f896 5977static int
e3bb37b5 5978process_operands (void)
29b0f896
AM		 5979{
5980 /* Default segment register this instruction will use for memory
5981 accesses. 0 means unknown. This is only for optimizing out
5982 unnecessary segment overrides. */
5983 const seg_entry *default_seg = 0;
5984
2426c15f 5985 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5986 {
91d6fa6a
NC		 5987 unsigned int dupl = i.operands;
5988 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5989 unsigned int j;
5990
c0f3af97 5991 /* The destination must be an xmm register. */
9c2799c2 5992 gas_assert (i.reg_operands
91d6fa6a 5993 && MAX_OPERANDS > dupl
7ab9ffdd 5994 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5995
5996 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5997 {
c0f3af97 5998 /* The first operand is implicit and must be xmm0. */
9c2799c2 5999 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 6000 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 6001 return bad_implicit_operand (1);
6002
8cd7925b 6003 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 6004 {
6005 /* Keep xmm0 for instructions with VEX prefix and 3
6006 sources. */
6007 goto duplicate;
6008 }
e2ec9d29 6009 else
c0f3af97
L		 6010 {
6011 /* We remove the first xmm0 and keep the number of
6012 operands unchanged, which in fact duplicates the
6013 destination. */
6014 for (j = 1; j < i.operands; j++)
6015 {
6016 i.op[j - 1] = i.op[j];
6017 i.types[j - 1] = i.types[j];
6018 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6019 }
6020 }
6021 }
6022 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 6023 {
91d6fa6a 6024 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 6025 && (i.tm.opcode_modifier.vexsources
6026 == VEX3SOURCES));
c0f3af97
L		 6027
6028 /* Add the implicit xmm0 for instructions with VEX prefix
6029 and 3 sources. */
6030 for (j = i.operands; j > 0; j--)
6031 {
6032 i.op[j] = i.op[j - 1];
6033 i.types[j] = i.types[j - 1];
6034 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6035 }
6036 i.op[0].regs
6037 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 6038 i.types[0] = regxmm;
c0f3af97
L		 6039 i.tm.operand_types[0] = regxmm;
6040
6041 i.operands += 2;
6042 i.reg_operands += 2;
6043 i.tm.operands += 2;
6044
91d6fa6a 6045 dupl++;
c0f3af97 6046 dest++;
91d6fa6a
NC		 6047 i.op[dupl] = i.op[dest];
6048 i.types[dupl] = i.types[dest];
6049 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 6050 }
c0f3af97
L		 6051 else
6052 {
6053duplicate:
6054 i.operands++;
6055 i.reg_operands++;
6056 i.tm.operands++;
6057
91d6fa6a
NC		 6058 i.op[dupl] = i.op[dest];
6059 i.types[dupl] = i.types[dest];
6060 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 6061 }
6062
6063 if (i.tm.opcode_modifier.immext)
6064 process_immext ();
6065 }
6066 else if (i.tm.opcode_modifier.firstxmm0)
6067 {
6068 unsigned int j;
6069
43234a1e 6070 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
9c2799c2 6071 gas_assert (i.reg_operands
7ab9ffdd 6072 && (operand_type_equal (&i.types[0], &regxmm)
43234a1e
L		 6073 || operand_type_equal (&i.types[0], &regymm)
6074 || operand_type_equal (&i.types[0], &regzmm)));
4c692bc7 6075 if (register_number (i.op[0].regs) != 0)
c0f3af97 6076 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 6077
6078 for (j = 1; j < i.operands; j++)
6079 {
6080 i.op[j - 1] = i.op[j];
6081 i.types[j - 1] = i.types[j];
6082
6083 /* We need to adjust fields in i.tm since they are used by
6084 build_modrm_byte. */
6085 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6086 }
6087
e2ec9d29
L		 6088 i.operands--;
6089 i.reg_operands--;
e2ec9d29
L		 6090 i.tm.operands--;
6091 }
920d2ddc
IT		 6092 else if (i.tm.opcode_modifier.implicitquadgroup)
6093 {
6094 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6095 gas_assert (i.operands >= 2
6096 && (operand_type_equal (&i.types[1], &regxmm)
6097 || operand_type_equal (&i.types[1], &regymm)
6098 || operand_type_equal (&i.types[1], &regzmm)));
6099 unsigned int regnum = register_number (i.op[1].regs);
6100 unsigned int first_reg_in_group = regnum & ~3;
6101 unsigned int last_reg_in_group = first_reg_in_group + 3;
6102 if (regnum != first_reg_in_group) {
6103 as_warn (_("the second source register `%s%s' implicitly denotes"
6104 " `%s%.3s%d' to `%s%.3s%d' source group in `%s'"),
6105 register_prefix, i.op[1].regs->reg_name,
6106 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6107 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6108 i.tm.name);
6109 }
6110 }
e2ec9d29
L		 6111 else if (i.tm.opcode_modifier.regkludge)
6112 {
6113 /* The imul $imm, %reg instruction is converted into
6114 imul $imm, %reg, %reg, and the clr %reg instruction
6115 is converted into xor %reg, %reg. */
6116
6117 unsigned int first_reg_op;
6118
6119 if (operand_type_check (i.types[0], reg))
6120 first_reg_op = 0;
6121 else
6122 first_reg_op = 1;
6123 /* Pretend we saw the extra register operand. */
9c2799c2 6124 gas_assert (i.reg_operands == 1
7ab9ffdd 6125 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 6126 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6127 i.types[first_reg_op + 1] = i.types[first_reg_op];
6128 i.operands++;
6129 i.reg_operands++;
29b0f896
AM		 6130 }
6131
40fb9820 6132 if (i.tm.opcode_modifier.shortform)
29b0f896 6133 {
40fb9820
L		 6134 if (i.types[0].bitfield.sreg2
6135 || i.types[0].bitfield.sreg3)
29b0f896 6136 {
4eed87de
AM		 6137 if (i.tm.base_opcode == POP_SEG_SHORT
6138 && i.op[0].regs->reg_num == 1)
29b0f896 6139 {
a87af027 6140 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 6141 return 0;
29b0f896 6142 }
4eed87de
AM		 6143 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6144 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 6145 i.rex |= REX_B;
4eed87de
AM		 6146 }
6147 else
6148 {
7ab9ffdd 6149 /* The register or float register operand is in operand
85f10a01 6150 0 or 1. */
40fb9820 6151 unsigned int op;
7ab9ffdd
L		 6152
6153 if (i.types[0].bitfield.floatreg
6154 || operand_type_check (i.types[0], reg))
6155 op = 0;
6156 else
6157 op = 1;
4eed87de
AM		 6158 /* Register goes in low 3 bits of opcode. */
6159 i.tm.base_opcode |= i.op[op].regs->reg_num;
6160 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 6161 i.rex |= REX_B;
40fb9820 6162 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 6163 {
4eed87de
AM		 6164 /* Warn about some common errors, but press on regardless.
6165 The first case can be generated by gcc (<= 2.8.1). */
6166 if (i.operands == 2)
6167 {
6168 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 6169 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 6170 register_prefix, i.op[!intel_syntax].regs->reg_name,
6171 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 6172 }
6173 else
6174 {
6175 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 6176 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6177 register_prefix, i.op[0].regs->reg_name);
4eed87de 6178 }
29b0f896
AM		 6179 }
6180 }
6181 }
40fb9820 6182 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 6183 {
6184 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 6185 must be put into the modrm byte). Now, we make the modrm and
6186 index base bytes based on all the info we've collected. */
29b0f896
AM		 6187
6188 default_seg = build_modrm_byte ();
6189 }
8a2ed489 6190 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 6191 {
6192 default_seg = &ds;
6193 }
40fb9820 6194 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 6195 {
6196 /* For the string instructions that allow a segment override
6197 on one of their operands, the default segment is ds. */
6198 default_seg = &ds;
6199 }
6200
75178d9d
L		 6201 if (i.tm.base_opcode == 0x8d /* lea */
6202 && i.seg[0]
6203 && !quiet_warnings)
30123838 6204 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 6205
6206 /* If a segment was explicitly specified, and the specified segment
6207 is not the default, use an opcode prefix to select it. If we
6208 never figured out what the default segment is, then default_seg
6209 will be zero at this point, and the specified segment prefix will
6210 always be used. */
29b0f896
AM		 6211 if ((i.seg[0]) && (i.seg[0] != default_seg))
6212 {
6213 if (!add_prefix (i.seg[0]->seg_prefix))
6214 return 0;
6215 }
6216 return 1;
6217}
6218
6219static const seg_entry *
e3bb37b5 6220build_modrm_byte (void)
29b0f896
AM		 6221{
6222 const seg_entry *default_seg = 0;
c0f3af97 6223 unsigned int source, dest;
8cd7925b 6224 int vex_3_sources;
c0f3af97
L		 6225
6226 /* The first operand of instructions with VEX prefix and 3 sources
6227 must be VEX_Imm4. */
8cd7925b 6228 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 6229 if (vex_3_sources)
6230 {
91d6fa6a 6231 unsigned int nds, reg_slot;
4c2c6516 6232 expressionS *exp;
c0f3af97 6233
922d8de8 6234 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 6235 && i.tm.opcode_modifier.immext)
6236 {
6237 dest = i.operands - 2;
6238 gas_assert (dest == 3);
6239 }
922d8de8 6240 else
a683cc34 6241 dest = i.operands - 1;
c0f3af97 6242 nds = dest - 1;
922d8de8 6243
a683cc34
SP		 6244 /* There are 2 kinds of instructions:
6245 1. 5 operands: 4 register operands or 3 register operands
6246 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 6247 VexW0 or VexW1. The destination must be either XMM, YMM or
6248 ZMM register.
a683cc34
SP		 6249 2. 4 operands: 4 register operands or 3 register operands
6250 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 6251 gas_assert ((i.reg_operands == 4
a683cc34
SP		 6252 || (i.reg_operands == 3 && i.mem_operands == 1))
6253 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6254 && (i.tm.opcode_modifier.veximmext
6255 || (i.imm_operands == 1
6256 && i.types[0].bitfield.vec_imm4
6257 && (i.tm.opcode_modifier.vexw == VEXW0
6258 || i.tm.opcode_modifier.vexw == VEXW1)
6259 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 6260 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
6261 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 6262
6263 if (i.imm_operands == 0)
6264 {
6265 /* When there is no immediate operand, generate an 8bit
6266 immediate operand to encode the first operand. */
6267 exp = &im_expressions[i.imm_operands++];
6268 i.op[i.operands].imms = exp;
6269 i.types[i.operands] = imm8;
6270 i.operands++;
6271 /* If VexW1 is set, the first operand is the source and
6272 the second operand is encoded in the immediate operand. */
6273 if (i.tm.opcode_modifier.vexw == VEXW1)
6274 {
6275 source = 0;
6276 reg_slot = 1;
6277 }
6278 else
6279 {
6280 source = 1;
6281 reg_slot = 0;
6282 }
6283
6284 /* FMA swaps REG and NDS. */
6285 if (i.tm.cpu_flags.bitfield.cpufma)
6286 {
6287 unsigned int tmp;
6288 tmp = reg_slot;
6289 reg_slot = nds;
6290 nds = tmp;
6291 }
6292
24981e7b
L		 6293 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6294 &regxmm)
a683cc34 6295 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6296 &regymm)
6297 || operand_type_equal (&i.tm.operand_types[reg_slot],
6298 &regzmm));
a683cc34 6299 exp->X_op = O_constant;
4c692bc7 6300 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6301 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6302 }
922d8de8 6303 else
a683cc34
SP		 6304 {
6305 unsigned int imm_slot;
6306
6307 if (i.tm.opcode_modifier.vexw == VEXW0)
6308 {
6309 /* If VexW0 is set, the third operand is the source and
6310 the second operand is encoded in the immediate
6311 operand. */
6312 source = 2;
6313 reg_slot = 1;
6314 }
6315 else
6316 {
6317 /* VexW1 is set, the second operand is the source and
6318 the third operand is encoded in the immediate
6319 operand. */
6320 source = 1;
6321 reg_slot = 2;
6322 }
6323
6324 if (i.tm.opcode_modifier.immext)
6325 {
33eaf5de 6326 /* When ImmExt is set, the immediate byte is the last
a683cc34
SP		 6327 operand. */
6328 imm_slot = i.operands - 1;
6329 source--;
6330 reg_slot--;
6331 }
6332 else
6333 {
6334 imm_slot = 0;
6335
6336 /* Turn on Imm8 so that output_imm will generate it. */
6337 i.types[imm_slot].bitfield.imm8 = 1;
6338 }
6339
24981e7b
L		 6340 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6341 &regxmm)
6342 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6343 &regymm)
6344 || operand_type_equal (&i.tm.operand_types[reg_slot],
6345 &regzmm));
a683cc34 6346 i.op[imm_slot].imms->X_add_number
4c692bc7 6347 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6348 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6349 }
6350
6351 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6352 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 6353 &regymm)
6354 || operand_type_equal (&i.tm.operand_types[nds],
6355 &regzmm));
dae39acc 6356 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6357 }
6358 else
6359 source = dest = 0;
29b0f896
AM		 6360
6361 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6362 implicit registers do not count. If there are 3 register
6363 operands, it must be a instruction with VexNDS. For a
6364 instruction with VexNDD, the destination register is encoded
6365 in VEX prefix. If there are 4 register operands, it must be
6366 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6367 if (i.mem_operands == 0
6368 && ((i.reg_operands == 2
2426c15f 6369 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6370 || (i.reg_operands == 3
2426c15f 6371 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6372 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6373 {
cab737b9
L		 6374 switch (i.operands)
6375 {
6376 case 2:
6377 source = 0;
6378 break;
6379 case 3:
c81128dc
L		 6380 /* When there are 3 operands, one of them may be immediate,
6381 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6382 the first operand must be shift count register (cl) or it
6383 is an instruction with VexNDS. */
9c2799c2 6384 gas_assert (i.imm_operands == 1
7ab9ffdd 6385 || (i.imm_operands == 0
2426c15f 6386 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6387 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6388 if (operand_type_check (i.types[0], imm)
6389 || i.types[0].bitfield.shiftcount)
6390 source = 1;
6391 else
6392 source = 0;
cab737b9
L		 6393 break;
6394 case 4:
368d64cc
L		 6395 /* When there are 4 operands, the first two must be 8bit
6396 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6397 one.
6398
6399 For instructions with VexNDS, if the first operand
6400 an imm8, the source operand is the 2nd one. If the last
6401 operand is imm8, the source operand is the first one. */
9c2799c2 6402 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6403 && i.types[0].bitfield.imm8
6404 && i.types[1].bitfield.imm8)
2426c15f 6405 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6406 && i.imm_operands == 1
6407 && (i.types[0].bitfield.imm8
43234a1e
L		 6408 || i.types[i.operands - 1].bitfield.imm8
6409 || i.rounding)));
9f2670f2
L		 6410 if (i.imm_operands == 2)
6411 source = 2;
6412 else
c0f3af97
L		 6413 {
6414 if (i.types[0].bitfield.imm8)
6415 source = 1;
6416 else
6417 source = 0;
6418 }
c0f3af97
L		 6419 break;
6420 case 5:
43234a1e
L		 6421 if (i.tm.opcode_modifier.evex)
6422 {
6423 /* For EVEX instructions, when there are 5 operands, the
6424 first one must be immediate operand. If the second one
6425 is immediate operand, the source operand is the 3th
6426 one. If the last one is immediate operand, the source
6427 operand is the 2nd one. */
6428 gas_assert (i.imm_operands == 2
6429 && i.tm.opcode_modifier.sae
6430 && operand_type_check (i.types[0], imm));
6431 if (operand_type_check (i.types[1], imm))
6432 source = 2;
6433 else if (operand_type_check (i.types[4], imm))
6434 source = 1;
6435 else
6436 abort ();
6437 }
cab737b9
L		 6438 break;
6439 default:
6440 abort ();
6441 }
6442
c0f3af97
L		 6443 if (!vex_3_sources)
6444 {
6445 dest = source + 1;
6446
43234a1e
L		 6447 /* RC/SAE operand could be between DEST and SRC. That happens
6448 when one operand is GPR and the other one is XMM/YMM/ZMM
6449 register. */
6450 if (i.rounding && i.rounding->operand == (int) dest)
6451 dest++;
6452
2426c15f 6453 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6454 {
43234a1e
L		 6455 /* For instructions with VexNDS, the register-only source
6456 operand must be 32/64bit integer, XMM, YMM or ZMM
6457 register. It is encoded in VEX prefix. We need to
6458 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6459
6460 i386_operand_type op;
6461 unsigned int vvvv;
6462
6463 /* Check register-only source operand when two source
6464 operands are swapped. */
6465 if (!i.tm.operand_types[source].bitfield.baseindex
6466 && i.tm.operand_types[dest].bitfield.baseindex)
6467 {
6468 vvvv = source;
6469 source = dest;
6470 }
6471 else
6472 vvvv = dest;
6473
6474 op = i.tm.operand_types[vvvv];
fa99fab2 6475 op.bitfield.regmem = 0;
c0f3af97 6476 if ((dest + 1) >= i.operands
ac4eb736
AM		 6477 || (!op.bitfield.reg32
6478 && op.bitfield.reg64
f12dc422 6479 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6480 && !operand_type_equal (&op, &regymm)
6481 && !operand_type_equal (&op, &regzmm)
6482 && !operand_type_equal (&op, &regmask)))
c0f3af97 6483 abort ();
f12dc422 6484 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6485 dest++;
6486 }
6487 }
29b0f896
AM		 6488
6489 i.rm.mode = 3;
6490 /* One of the register operands will be encoded in the i.tm.reg
6491 field, the other in the combined i.tm.mode and i.tm.regmem
6492 fields. If no form of this instruction supports a memory
6493 destination operand, then we assume the source operand may
6494 sometimes be a memory operand and so we need to store the
6495 destination in the i.rm.reg field. */
40fb9820
L		 6496 if (!i.tm.operand_types[dest].bitfield.regmem
6497 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6498 {
6499 i.rm.reg = i.op[dest].regs->reg_num;
6500 i.rm.regmem = i.op[source].regs->reg_num;
6501 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6502 i.rex |= REX_R;
43234a1e
L		 6503 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6504 i.vrex |= REX_R;
29b0f896 6505 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6506 i.rex |= REX_B;
43234a1e
L		 6507 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6508 i.vrex |= REX_B;
29b0f896
AM		 6509 }
6510 else
6511 {
6512 i.rm.reg = i.op[source].regs->reg_num;
6513 i.rm.regmem = i.op[dest].regs->reg_num;
6514 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6515 i.rex |= REX_B;
43234a1e
L		 6516 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6517 i.vrex |= REX_B;
29b0f896 6518 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6519 i.rex |= REX_R;
43234a1e
L		 6520 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6521 i.vrex |= REX_R;
29b0f896 6522 }
161a04f6 6523 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6524 {
40fb9820
L		 6525 if (!i.types[0].bitfield.control
6526 && !i.types[1].bitfield.control)
c4a530c5 6527 abort ();
161a04f6 6528 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6529 add_prefix (LOCK_PREFIX_OPCODE);
6530 }
29b0f896
AM		 6531 }
6532 else
6533 { /* If it's not 2 reg operands... */
c0f3af97
L		 6534 unsigned int mem;
6535
29b0f896
AM		 6536 if (i.mem_operands)
6537 {
6538 unsigned int fake_zero_displacement = 0;
99018f42 6539 unsigned int op;
4eed87de 6540
7ab9ffdd
L		 6541 for (op = 0; op < i.operands; op++)
6542 if (operand_type_check (i.types[op], anymem))
6543 break;
7ab9ffdd 6544 gas_assert (op < i.operands);
29b0f896 6545
6c30d220
L		 6546 if (i.tm.opcode_modifier.vecsib)
6547 {
6548 if (i.index_reg->reg_num == RegEiz
6549 || i.index_reg->reg_num == RegRiz)
6550 abort ();
6551
6552 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6553 if (!i.base_reg)
6554 {
6555 i.sib.base = NO_BASE_REGISTER;
6556 i.sib.scale = i.log2_scale_factor;
43234a1e
L		 6557 /* No Vec_Disp8 if there is no base. */
6558 i.types[op].bitfield.vec_disp8 = 0;
6c30d220
L		 6559 i.types[op].bitfield.disp8 = 0;
6560 i.types[op].bitfield.disp16 = 0;
6561 i.types[op].bitfield.disp64 = 0;
6562 if (flag_code != CODE_64BIT)
6563 {
6564 /* Must be 32 bit */
6565 i.types[op].bitfield.disp32 = 1;
6566 i.types[op].bitfield.disp32s = 0;
6567 }
6568 else
6569 {
6570 i.types[op].bitfield.disp32 = 0;
6571 i.types[op].bitfield.disp32s = 1;
6572 }
6573 }
6574 i.sib.index = i.index_reg->reg_num;
6575 if ((i.index_reg->reg_flags & RegRex) != 0)
6576 i.rex |= REX_X;
43234a1e
L		 6577 if ((i.index_reg->reg_flags & RegVRex) != 0)
6578 i.vrex |= REX_X;
6c30d220
L		 6579 }
6580
29b0f896
AM		 6581 default_seg = &ds;
6582
6583 if (i.base_reg == 0)
6584 {
6585 i.rm.mode = 0;
6586 if (!i.disp_operands)
6c30d220
L		 6587 {
6588 fake_zero_displacement = 1;
6589 /* Instructions with VSIB byte need 32bit displacement
6590 if there is no base register. */
6591 if (i.tm.opcode_modifier.vecsib)
6592 i.types[op].bitfield.disp32 = 1;
6593 }
29b0f896
AM		 6594 if (i.index_reg == 0)
6595 {
6c30d220 6596 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6597 /* Operand is just <disp> */
20f0a1fc 6598 if (flag_code == CODE_64BIT)
29b0f896
AM		 6599 {
6600 /* 64bit mode overwrites the 32bit absolute
6601 addressing by RIP relative addressing and
6602 absolute addressing is encoded by one of the
6603 redundant SIB forms. */
6604 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6605 i.sib.base = NO_BASE_REGISTER;
6606 i.sib.index = NO_INDEX_REGISTER;
fc225355 6607 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6608 ? disp32s : disp32);
20f0a1fc 6609 }
fc225355
L		 6610 else if ((flag_code == CODE_16BIT)
6611 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6612 {
6613 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6614 i.types[op] = disp16;
20f0a1fc
NC		 6615 }
6616 else
6617 {
6618 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6619 i.types[op] = disp32;
29b0f896
AM		 6620 }
6621 }
6c30d220 6622 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6623 {
6c30d220 6624 /* !i.base_reg && i.index_reg */
db51cc60
L		 6625 if (i.index_reg->reg_num == RegEiz
6626 || i.index_reg->reg_num == RegRiz)
6627 i.sib.index = NO_INDEX_REGISTER;
6628 else
6629 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6630 i.sib.base = NO_BASE_REGISTER;
6631 i.sib.scale = i.log2_scale_factor;
6632 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
43234a1e
L		 6633 /* No Vec_Disp8 if there is no base. */
6634 i.types[op].bitfield.vec_disp8 = 0;
40fb9820
L		 6635 i.types[op].bitfield.disp8 = 0;
6636 i.types[op].bitfield.disp16 = 0;
6637 i.types[op].bitfield.disp64 = 0;
29b0f896 6638 if (flag_code != CODE_64BIT)
40fb9820
L		 6639 {
6640 /* Must be 32 bit */
6641 i.types[op].bitfield.disp32 = 1;
6642 i.types[op].bitfield.disp32s = 0;
6643 }
29b0f896 6644 else
40fb9820
L		 6645 {
6646 i.types[op].bitfield.disp32 = 0;
6647 i.types[op].bitfield.disp32s = 1;
6648 }
29b0f896 6649 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6650 i.rex |= REX_X;
29b0f896
AM		 6651 }
6652 }
6653 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6654 else if (i.base_reg->reg_num == RegRip ||
6655 i.base_reg->reg_num == RegEip)
29b0f896 6656 {
6c30d220 6657 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6658 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6659 i.types[op].bitfield.disp8 = 0;
6660 i.types[op].bitfield.disp16 = 0;
6661 i.types[op].bitfield.disp32 = 0;
6662 i.types[op].bitfield.disp32s = 1;
6663 i.types[op].bitfield.disp64 = 0;
43234a1e 6664 i.types[op].bitfield.vec_disp8 = 0;
71903a11 6665 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6666 if (! i.disp_operands)
6667 fake_zero_displacement = 1;
29b0f896 6668 }
40fb9820 6669 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 6670 {
6c30d220 6671 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6672 switch (i.base_reg->reg_num)
6673 {
6674 case 3: /* (%bx) */
6675 if (i.index_reg == 0)
6676 i.rm.regmem = 7;
6677 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6678 i.rm.regmem = i.index_reg->reg_num - 6;
6679 break;
6680 case 5: /* (%bp) */
6681 default_seg = &ss;
6682 if (i.index_reg == 0)
6683 {
6684 i.rm.regmem = 6;
40fb9820 6685 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6686 {
6687 /* fake (%bp) into 0(%bp) */
43234a1e
L		 6688 if (i.tm.operand_types[op].bitfield.vec_disp8)
6689 i.types[op].bitfield.vec_disp8 = 1;
6690 else
6691 i.types[op].bitfield.disp8 = 1;
252b5132 6692 fake_zero_displacement = 1;
29b0f896
AM		 6693 }
6694 }
6695 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6696 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6697 break;
6698 default: /* (%si) -> 4 or (%di) -> 5 */
6699 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6700 }
6701 i.rm.mode = mode_from_disp_size (i.types[op]);
6702 }
6703 else /* i.base_reg and 32/64 bit mode */
6704 {
6705 if (flag_code == CODE_64BIT
40fb9820
L		 6706 && operand_type_check (i.types[op], disp))
6707 {
6708 i386_operand_type temp;
0dfbf9d7 6709 operand_type_set (&temp, 0);
40fb9820 6710 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
43234a1e
L		 6711 temp.bitfield.vec_disp8
6712 = i.types[op].bitfield.vec_disp8;
40fb9820
L		 6713 i.types[op] = temp;
6714 if (i.prefix[ADDR_PREFIX] == 0)
6715 i.types[op].bitfield.disp32s = 1;
6716 else
6717 i.types[op].bitfield.disp32 = 1;
6718 }
20f0a1fc 6719
6c30d220
L		 6720 if (!i.tm.opcode_modifier.vecsib)
6721 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6722 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6723 i.rex |= REX_B;
29b0f896
AM		 6724 i.sib.base = i.base_reg->reg_num;
6725 /* x86-64 ignores REX prefix bit here to avoid decoder
6726 complications. */
848930b2
JB		 6727 if (!(i.base_reg->reg_flags & RegRex)
6728 && (i.base_reg->reg_num == EBP_REG_NUM
6729 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6730 default_seg = &ss;
848930b2 6731 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6732 {
848930b2 6733 fake_zero_displacement = 1;
43234a1e
L		 6734 if (i.tm.operand_types [op].bitfield.vec_disp8)
6735 i.types[op].bitfield.vec_disp8 = 1;
6736 else
6737 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6738 }
6739 i.sib.scale = i.log2_scale_factor;
6740 if (i.index_reg == 0)
6741 {
6c30d220 6742 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6743 /* <disp>(%esp) becomes two byte modrm with no index
6744 register. We've already stored the code for esp
6745 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6746 Any base register besides %esp will not use the
6747 extra modrm byte. */
6748 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6749 }
6c30d220 6750 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6751 {
db51cc60
L		 6752 if (i.index_reg->reg_num == RegEiz
6753 || i.index_reg->reg_num == RegRiz)
6754 i.sib.index = NO_INDEX_REGISTER;
6755 else
6756 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6757 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6758 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6759 i.rex |= REX_X;
29b0f896 6760 }
67a4f2b7
AO		 6761
6762 if (i.disp_operands
6763 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6764 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6765 i.rm.mode = 0;
6766 else
a501d77e
L		 6767 {
6768 if (!fake_zero_displacement
6769 && !i.disp_operands
6770 && i.disp_encoding)
6771 {
6772 fake_zero_displacement = 1;
6773 if (i.disp_encoding == disp_encoding_8bit)
6774 i.types[op].bitfield.disp8 = 1;
6775 else
6776 i.types[op].bitfield.disp32 = 1;
6777 }
6778 i.rm.mode = mode_from_disp_size (i.types[op]);
6779 }
29b0f896 6780 }
252b5132 6781
29b0f896
AM		 6782 if (fake_zero_displacement)
6783 {
6784 /* Fakes a zero displacement assuming that i.types[op]
6785 holds the correct displacement size. */
6786 expressionS *exp;
6787
9c2799c2 6788 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6789 exp = &disp_expressions[i.disp_operands++];
6790 i.op[op].disps = exp;
6791 exp->X_op = O_constant;
6792 exp->X_add_number = 0;
6793 exp->X_add_symbol = (symbolS *) 0;
6794 exp->X_op_symbol = (symbolS *) 0;
6795 }
c0f3af97
L		 6796
6797 mem = op;
29b0f896 6798 }
c0f3af97
L		 6799 else
6800 mem = ~0;
252b5132 6801
8c43a48b 6802 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6803 {
6804 if (operand_type_check (i.types[0], imm))
6805 i.vex.register_specifier = NULL;
6806 else
6807 {
6808 /* VEX.vvvv encodes one of the sources when the first
6809 operand is not an immediate. */
1ef99a7b 6810 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6811 i.vex.register_specifier = i.op[0].regs;
6812 else
6813 i.vex.register_specifier = i.op[1].regs;
6814 }
6815
6816 /* Destination is a XMM register encoded in the ModRM.reg
6817 and VEX.R bit. */
6818 i.rm.reg = i.op[2].regs->reg_num;
6819 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6820 i.rex |= REX_R;
6821
6822 /* ModRM.rm and VEX.B encodes the other source. */
6823 if (!i.mem_operands)
6824 {
6825 i.rm.mode = 3;
6826
1ef99a7b 6827 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6828 i.rm.regmem = i.op[1].regs->reg_num;
6829 else
6830 i.rm.regmem = i.op[0].regs->reg_num;
6831
6832 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6833 i.rex |= REX_B;
6834 }
6835 }
2426c15f 6836 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6837 {
6838 i.vex.register_specifier = i.op[2].regs;
6839 if (!i.mem_operands)
6840 {
6841 i.rm.mode = 3;
6842 i.rm.regmem = i.op[1].regs->reg_num;
6843 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6844 i.rex |= REX_B;
6845 }
6846 }
29b0f896
AM		 6847 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6848 (if any) based on i.tm.extension_opcode. Again, we must be
6849 careful to make sure that segment/control/debug/test/MMX
6850 registers are coded into the i.rm.reg field. */
f88c9eb0 6851 else if (i.reg_operands)
29b0f896 6852 {
99018f42 6853 unsigned int op;
7ab9ffdd
L		 6854 unsigned int vex_reg = ~0;
6855
6856 for (op = 0; op < i.operands; op++)
6857 if (i.types[op].bitfield.reg8
6858 || i.types[op].bitfield.reg16
6859 || i.types[op].bitfield.reg32
6860 || i.types[op].bitfield.reg64
6861 || i.types[op].bitfield.regmmx
6862 || i.types[op].bitfield.regxmm
6863 || i.types[op].bitfield.regymm
7e8b059b 6864 || i.types[op].bitfield.regbnd
43234a1e
L		 6865 || i.types[op].bitfield.regzmm
6866 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6867 || i.types[op].bitfield.sreg2
6868 || i.types[op].bitfield.sreg3
6869 || i.types[op].bitfield.control
6870 || i.types[op].bitfield.debug
6871 || i.types[op].bitfield.test)
6872 break;
c0209578 6873
7ab9ffdd
L		 6874 if (vex_3_sources)
6875 op = dest;
2426c15f 6876 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6877 {
6878 /* For instructions with VexNDS, the register-only
6879 source operand is encoded in VEX prefix. */
6880 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6881
7ab9ffdd 6882 if (op > mem)
c0f3af97 6883 {
7ab9ffdd
L		 6884 vex_reg = op++;
6885 gas_assert (op < i.operands);
c0f3af97
L		 6886 }
6887 else
c0f3af97 6888 {
f12dc422
L		 6889 /* Check register-only source operand when two source
6890 operands are swapped. */
6891 if (!i.tm.operand_types[op].bitfield.baseindex
6892 && i.tm.operand_types[op + 1].bitfield.baseindex)
6893 {
6894 vex_reg = op;
6895 op += 2;
6896 gas_assert (mem == (vex_reg + 1)
6897 && op < i.operands);
6898 }
6899 else
6900 {
6901 vex_reg = op + 1;
6902 gas_assert (vex_reg < i.operands);
6903 }
c0f3af97 6904 }
7ab9ffdd 6905 }
2426c15f 6906 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6907 {
f12dc422 6908 /* For instructions with VexNDD, the register destination
7ab9ffdd 6909 is encoded in VEX prefix. */
f12dc422
L		 6910 if (i.mem_operands == 0)
6911 {
6912 /* There is no memory operand. */
6913 gas_assert ((op + 2) == i.operands);
6914 vex_reg = op + 1;
6915 }
6916 else
8d63c93e 6917 {
f12dc422
L		 6918 /* There are only 2 operands. */
6919 gas_assert (op < 2 && i.operands == 2);
6920 vex_reg = 1;
6921 }
7ab9ffdd
L		 6922 }
6923 else
6924 gas_assert (op < i.operands);
99018f42 6925
7ab9ffdd
L		 6926 if (vex_reg != (unsigned int) ~0)
6927 {
f12dc422 6928 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6929
f12dc422
L		 6930 if (type->bitfield.reg32 != 1
6931 && type->bitfield.reg64 != 1
6932 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6933 && !operand_type_equal (type, &regymm)
6934 && !operand_type_equal (type, &regzmm)
6935 && !operand_type_equal (type, &regmask))
7ab9ffdd 6936 abort ();
f88c9eb0 6937
7ab9ffdd
L		 6938 i.vex.register_specifier = i.op[vex_reg].regs;
6939 }
6940
1b9f0c97
L		 6941 /* Don't set OP operand twice. */
6942 if (vex_reg != op)
7ab9ffdd 6943 {
1b9f0c97
L		 6944 /* If there is an extension opcode to put here, the
6945 register number must be put into the regmem field. */
6946 if (i.tm.extension_opcode != None)
6947 {
6948 i.rm.regmem = i.op[op].regs->reg_num;
6949 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6950 i.rex |= REX_B;
43234a1e
L		 6951 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6952 i.vrex |= REX_B;
1b9f0c97
L		 6953 }
6954 else
6955 {
6956 i.rm.reg = i.op[op].regs->reg_num;
6957 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6958 i.rex |= REX_R;
43234a1e
L		 6959 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6960 i.vrex |= REX_R;
1b9f0c97 6961 }
7ab9ffdd 6962 }
252b5132 6963
29b0f896
AM		 6964 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6965 must set it to 3 to indicate this is a register operand
6966 in the regmem field. */
6967 if (!i.mem_operands)
6968 i.rm.mode = 3;
6969 }
252b5132 6970
29b0f896 6971 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6972 if (i.tm.extension_opcode != None)
29b0f896
AM		 6973 i.rm.reg = i.tm.extension_opcode;
6974 }
6975 return default_seg;
6976}
252b5132 6977
29b0f896 6978static void
e3bb37b5 6979output_branch (void)
29b0f896
AM		 6980{
6981 char *p;
f8a5c266 6982 int size;
29b0f896
AM		 6983 int code16;
6984 int prefix;
6985 relax_substateT subtype;
6986 symbolS *sym;
6987 offsetT off;
6988
f8a5c266 6989 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6990 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6991
6992 prefix = 0;
6993 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6994 {
29b0f896
AM		 6995 prefix = 1;
6996 i.prefixes -= 1;
6997 code16 ^= CODE16;
252b5132 6998 }
29b0f896
AM		 6999 /* Pentium4 branch hints. */
7000 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7001 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 7002 {
29b0f896
AM		 7003 prefix++;
7004 i.prefixes--;
7005 }
7006 if (i.prefix[REX_PREFIX] != 0)
7007 {
7008 prefix++;
7009 i.prefixes--;
2f66722d
AM		 7010 }
7011
7e8b059b
L		 7012 /* BND prefixed jump. */
7013 if (i.prefix[BND_PREFIX] != 0)
7014 {
7015 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7016 i.prefixes -= 1;
7017 }
7018
29b0f896
AM		 7019 if (i.prefixes != 0 && !intel_syntax)
7020 as_warn (_("skipping prefixes on this instruction"));
7021
7022 /* It's always a symbol; End frag & setup for relax.
7023 Make sure there is enough room in this frag for the largest
7024 instruction we may generate in md_convert_frag. This is 2
7025 bytes for the opcode and room for the prefix and largest
7026 displacement. */
7027 frag_grow (prefix + 2 + 4);
7028 /* Prefix and 1 opcode byte go in fr_fix. */
7029 p = frag_more (prefix + 1);
7030 if (i.prefix[DATA_PREFIX] != 0)
7031 *p++ = DATA_PREFIX_OPCODE;
7032 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
7033 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
7034 *p++ = i.prefix[SEG_PREFIX];
7035 if (i.prefix[REX_PREFIX] != 0)
7036 *p++ = i.prefix[REX_PREFIX];
7037 *p = i.tm.base_opcode;
7038
7039 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 7040 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 7041 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 7042 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 7043 else
f8a5c266 7044 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 7045 subtype |= code16;
3e73aa7c 7046
29b0f896
AM		 7047 sym = i.op[0].disps->X_add_symbol;
7048 off = i.op[0].disps->X_add_number;
3e73aa7c 7049
29b0f896
AM		 7050 if (i.op[0].disps->X_op != O_constant
7051 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 7052 {
29b0f896
AM		 7053 /* Handle complex expressions. */
7054 sym = make_expr_symbol (i.op[0].disps);
7055 off = 0;
7056 }
3e73aa7c 7057
29b0f896
AM		 7058 /* 1 possible extra opcode + 4 byte displacement go in var part.
7059 Pass reloc in fr_var. */
d258b828 7060 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 7061}
3e73aa7c 7062
29b0f896 7063static void
e3bb37b5 7064output_jump (void)
29b0f896
AM		 7065{
7066 char *p;
7067 int size;
3e02c1cc 7068 fixS *fixP;
29b0f896 7069
40fb9820 7070 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 7071 {
7072 /* This is a loop or jecxz type instruction. */
7073 size = 1;
7074 if (i.prefix[ADDR_PREFIX] != 0)
7075 {
7076 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7077 i.prefixes -= 1;
7078 }
7079 /* Pentium4 branch hints. */
7080 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7081 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7082 {
7083 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7084 i.prefixes--;
3e73aa7c
JH		 7085 }
7086 }
29b0f896
AM		 7087 else
7088 {
7089 int code16;
3e73aa7c 7090
29b0f896
AM		 7091 code16 = 0;
7092 if (flag_code == CODE_16BIT)
7093 code16 = CODE16;
3e73aa7c 7094
29b0f896
AM		 7095 if (i.prefix[DATA_PREFIX] != 0)
7096 {
7097 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7098 i.prefixes -= 1;
7099 code16 ^= CODE16;
7100 }
252b5132 7101
29b0f896
AM		 7102 size = 4;
7103 if (code16)
7104 size = 2;
7105 }
9fcc94b6 7106
29b0f896
AM		 7107 if (i.prefix[REX_PREFIX] != 0)
7108 {
7109 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7110 i.prefixes -= 1;
7111 }
252b5132 7112
7e8b059b
L		 7113 /* BND prefixed jump. */
7114 if (i.prefix[BND_PREFIX] != 0)
7115 {
7116 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7117 i.prefixes -= 1;
7118 }
7119
29b0f896
AM		 7120 if (i.prefixes != 0 && !intel_syntax)
7121 as_warn (_("skipping prefixes on this instruction"));
e0890092 7122
42164a71
L		 7123 p = frag_more (i.tm.opcode_length + size);
7124 switch (i.tm.opcode_length)
7125 {
7126 case 2:
7127 *p++ = i.tm.base_opcode >> 8;
1a0670f3 7128 /* Fall through. */
42164a71
L		 7129 case 1:
7130 *p++ = i.tm.base_opcode;
7131 break;
7132 default:
7133 abort ();
7134 }
e0890092 7135
3e02c1cc 7136 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 7137 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3e02c1cc
AM		 7138
7139 /* All jumps handled here are signed, but don't use a signed limit
7140 check for 32 and 16 bit jumps as we want to allow wrap around at
7141 4G and 64k respectively. */
7142 if (size == 1)
7143 fixP->fx_signed = 1;
29b0f896 7144}
e0890092 7145
29b0f896 7146static void
e3bb37b5 7147output_interseg_jump (void)
29b0f896
AM		 7148{
7149 char *p;
7150 int size;
7151 int prefix;
7152 int code16;
252b5132 7153
29b0f896
AM		 7154 code16 = 0;
7155 if (flag_code == CODE_16BIT)
7156 code16 = CODE16;
a217f122 7157
29b0f896
AM		 7158 prefix = 0;
7159 if (i.prefix[DATA_PREFIX] != 0)
7160 {
7161 prefix = 1;
7162 i.prefixes -= 1;
7163 code16 ^= CODE16;
7164 }
7165 if (i.prefix[REX_PREFIX] != 0)
7166 {
7167 prefix++;
7168 i.prefixes -= 1;
7169 }
252b5132 7170
29b0f896
AM		 7171 size = 4;
7172 if (code16)
7173 size = 2;
252b5132 7174
29b0f896
AM		 7175 if (i.prefixes != 0 && !intel_syntax)
7176 as_warn (_("skipping prefixes on this instruction"));
252b5132 7177
29b0f896
AM		 7178 /* 1 opcode; 2 segment; offset */
7179 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 7180
29b0f896
AM		 7181 if (i.prefix[DATA_PREFIX] != 0)
7182 *p++ = DATA_PREFIX_OPCODE;
252b5132 7183
29b0f896
AM		 7184 if (i.prefix[REX_PREFIX] != 0)
7185 *p++ = i.prefix[REX_PREFIX];
252b5132 7186
29b0f896
AM		 7187 *p++ = i.tm.base_opcode;
7188 if (i.op[1].imms->X_op == O_constant)
7189 {
7190 offsetT n = i.op[1].imms->X_add_number;
252b5132 7191
29b0f896
AM		 7192 if (size == 2
7193 && !fits_in_unsigned_word (n)
7194 && !fits_in_signed_word (n))
7195 {
7196 as_bad (_("16-bit jump out of range"));
7197 return;
7198 }
7199 md_number_to_chars (p, n, size);
7200 }
7201 else
7202 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 7203 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 7204 if (i.op[0].imms->X_op != O_constant)
7205 as_bad (_("can't handle non absolute segment in `%s'"),
7206 i.tm.name);
7207 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7208}
a217f122 7209
29b0f896 7210static void
e3bb37b5 7211output_insn (void)
29b0f896 7212{
2bbd9c25
JJ		 7213 fragS *insn_start_frag;
7214 offsetT insn_start_off;
7215
29b0f896
AM		 7216 /* Tie dwarf2 debug info to the address at the start of the insn.
7217 We can't do this after the insn has been output as the current
7218 frag may have been closed off. eg. by frag_var. */
7219 dwarf2_emit_insn (0);
7220
2bbd9c25
JJ		 7221 insn_start_frag = frag_now;
7222 insn_start_off = frag_now_fix ();
7223
29b0f896 7224 /* Output jumps. */
40fb9820 7225 if (i.tm.opcode_modifier.jump)
29b0f896 7226 output_branch ();
40fb9820
L		 7227 else if (i.tm.opcode_modifier.jumpbyte
7228 || i.tm.opcode_modifier.jumpdword)
29b0f896 7229 output_jump ();
40fb9820 7230 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 7231 output_interseg_jump ();
7232 else
7233 {
7234 /* Output normal instructions here. */
7235 char *p;
7236 unsigned char *q;
47465058 7237 unsigned int j;
331d2d0d 7238 unsigned int prefix;
4dffcebc 7239
e4e00185
AS		 7240 if (avoid_fence
7241 && i.tm.base_opcode == 0xfae
7242 && i.operands == 1
7243 && i.imm_operands == 1
7244 && (i.op[0].imms->X_add_number == 0xe8
7245 || i.op[0].imms->X_add_number == 0xf0
7246 || i.op[0].imms->X_add_number == 0xf8))
7247 {
7248 /* Encode lfence, mfence, and sfence as
7249 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7250 offsetT val = 0x240483f0ULL;
7251 p = frag_more (5);
7252 md_number_to_chars (p, val, 5);
7253 return;
7254 }
7255
d022bddd
IT		 7256 /* Some processors fail on LOCK prefix. This options makes
7257 assembler ignore LOCK prefix and serves as a workaround. */
7258 if (omit_lock_prefix)
7259 {
7260 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7261 return;
7262 i.prefix[LOCK_PREFIX] = 0;
7263 }
7264
43234a1e
L		 7265 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7266 don't need the explicit prefix. */
7267 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 7268 {
c0f3af97 7269 switch (i.tm.opcode_length)
bc4bd9ab 7270 {
c0f3af97
L		 7271 case 3:
7272 if (i.tm.base_opcode & 0xff000000)
4dffcebc 7273 {
c0f3af97
L		 7274 prefix = (i.tm.base_opcode >> 24) & 0xff;
7275 goto check_prefix;
7276 }
7277 break;
7278 case 2:
7279 if ((i.tm.base_opcode & 0xff0000) != 0)
7280 {
7281 prefix = (i.tm.base_opcode >> 16) & 0xff;
7282 if (i.tm.cpu_flags.bitfield.cpupadlock)
7283 {
4dffcebc 7284check_prefix:
c0f3af97 7285 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 7286 || (i.prefix[REP_PREFIX]
c0f3af97
L		 7287 != REPE_PREFIX_OPCODE))
7288 add_prefix (prefix);
7289 }
7290 else
4dffcebc
L		 7291 add_prefix (prefix);
7292 }
c0f3af97
L		 7293 break;
7294 case 1:
7295 break;
7296 default:
7297 abort ();
bc4bd9ab 7298 }
c0f3af97 7299
6d19a37a 7300#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 7301 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7302 R_X86_64_GOTTPOFF relocation so that linker can safely
7303 perform IE->LE optimization. */
7304 if (x86_elf_abi == X86_64_X32_ABI
7305 && i.operands == 2
7306 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7307 && i.prefix[REX_PREFIX] == 0)
7308 add_prefix (REX_OPCODE);
6d19a37a 7309#endif
cf61b747 7310
c0f3af97
L		 7311 /* The prefix bytes. */
7312 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7313 if (*q)
7314 FRAG_APPEND_1_CHAR (*q);
0f10071e 7315 }
ae5c1c7b 7316 else
c0f3af97
L		 7317 {
7318 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7319 if (*q)
7320 switch (j)
7321 {
7322 case REX_PREFIX:
7323 /* REX byte is encoded in VEX prefix. */
7324 break;
7325 case SEG_PREFIX:
7326 case ADDR_PREFIX:
7327 FRAG_APPEND_1_CHAR (*q);
7328 break;
7329 default:
7330 /* There should be no other prefixes for instructions
7331 with VEX prefix. */
7332 abort ();
7333 }
7334
43234a1e
L		 7335 /* For EVEX instructions i.vrex should become 0 after
7336 build_evex_prefix. For VEX instructions upper 16 registers
7337 aren't available, so VREX should be 0. */
7338 if (i.vrex)
7339 abort ();
c0f3af97
L		 7340 /* Now the VEX prefix. */
7341 p = frag_more (i.vex.length);
7342 for (j = 0; j < i.vex.length; j++)
7343 p[j] = i.vex.bytes[j];
7344 }
252b5132 7345
29b0f896 7346 /* Now the opcode; be careful about word order here! */
4dffcebc 7347 if (i.tm.opcode_length == 1)
29b0f896
AM		 7348 {
7349 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7350 }
7351 else
7352 {
4dffcebc 7353 switch (i.tm.opcode_length)
331d2d0d 7354 {
43234a1e
L		 7355 case 4:
7356 p = frag_more (4);
7357 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7358 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7359 break;
4dffcebc 7360 case 3:
331d2d0d
L		 7361 p = frag_more (3);
7362 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7363 break;
7364 case 2:
7365 p = frag_more (2);
7366 break;
7367 default:
7368 abort ();
7369 break;
331d2d0d 7370 }
0f10071e 7371
29b0f896
AM		 7372 /* Put out high byte first: can't use md_number_to_chars! */
7373 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7374 *p = i.tm.base_opcode & 0xff;
7375 }
3e73aa7c 7376
29b0f896 7377 /* Now the modrm byte and sib byte (if present). */
40fb9820 7378 if (i.tm.opcode_modifier.modrm)
29b0f896 7379 {
4a3523fa
L		 7380 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7381 | i.rm.reg << 3
7382 | i.rm.mode << 6));
29b0f896
AM		 7383 /* If i.rm.regmem == ESP (4)
7384 && i.rm.mode != (Register mode)
7385 && not 16 bit
7386 ==> need second modrm byte. */
7387 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7388 && i.rm.mode != 3
40fb9820 7389 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 7390 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7391 | i.sib.index << 3
7392 | i.sib.scale << 6));
29b0f896 7393 }
3e73aa7c 7394
29b0f896 7395 if (i.disp_operands)
2bbd9c25 7396 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7397
29b0f896 7398 if (i.imm_operands)
2bbd9c25 7399 output_imm (insn_start_frag, insn_start_off);
29b0f896 7400 }
252b5132 7401
29b0f896
AM		 7402#ifdef DEBUG386
7403 if (flag_debug)
7404 {
7b81dfbb 7405 pi ("" /*line*/, &i);
29b0f896
AM		 7406 }
7407#endif /* DEBUG386 */
7408}
252b5132 7409
e205caa7
L		 7410/* Return the size of the displacement operand N. */
7411
7412static int
7413disp_size (unsigned int n)
7414{
7415 int size = 4;
43234a1e
L		 7416
7417 /* Vec_Disp8 has to be 8bit. */
7418 if (i.types[n].bitfield.vec_disp8)
7419 size = 1;
7420 else if (i.types[n].bitfield.disp64)
40fb9820
L		 7421 size = 8;
7422 else if (i.types[n].bitfield.disp8)
7423 size = 1;
7424 else if (i.types[n].bitfield.disp16)
7425 size = 2;
e205caa7
L		 7426 return size;
7427}
7428
7429/* Return the size of the immediate operand N. */
7430
7431static int
7432imm_size (unsigned int n)
7433{
7434 int size = 4;
40fb9820
L		 7435 if (i.types[n].bitfield.imm64)
7436 size = 8;
7437 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7438 size = 1;
7439 else if (i.types[n].bitfield.imm16)
7440 size = 2;
e205caa7
L		 7441 return size;
7442}
7443
29b0f896 7444static void
64e74474 7445output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7446{
7447 char *p;
7448 unsigned int n;
252b5132 7449
29b0f896
AM		 7450 for (n = 0; n < i.operands; n++)
7451 {
43234a1e
L		 7452 if (i.types[n].bitfield.vec_disp8
7453 || operand_type_check (i.types[n], disp))
29b0f896
AM		 7454 {
7455 if (i.op[n].disps->X_op == O_constant)
7456 {
e205caa7 7457 int size = disp_size (n);
43234a1e 7458 offsetT val = i.op[n].disps->X_add_number;
252b5132 7459
43234a1e
L		 7460 if (i.types[n].bitfield.vec_disp8)
7461 val >>= i.memshift;
7462 val = offset_in_range (val, size);
29b0f896
AM		 7463 p = frag_more (size);
7464 md_number_to_chars (p, val, size);
7465 }
7466 else
7467 {
f86103b7 7468 enum bfd_reloc_code_real reloc_type;
e205caa7 7469 int size = disp_size (n);
40fb9820 7470 int sign = i.types[n].bitfield.disp32s;
29b0f896 7471 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
02a86693 7472 fixS *fixP;
29b0f896 7473
e205caa7 7474 /* We can't have 8 bit displacement here. */
9c2799c2 7475 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7476
29b0f896
AM		 7477 /* The PC relative address is computed relative
7478 to the instruction boundary, so in case immediate
7479 fields follows, we need to adjust the value. */
7480 if (pcrel && i.imm_operands)
7481 {
29b0f896 7482 unsigned int n1;
e205caa7 7483 int sz = 0;
252b5132 7484
29b0f896 7485 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7486 if (operand_type_check (i.types[n1], imm))
252b5132 7487 {
e205caa7
L		 7488 /* Only one immediate is allowed for PC
7489 relative address. */
9c2799c2 7490 gas_assert (sz == 0);
e205caa7
L		 7491 sz = imm_size (n1);
7492 i.op[n].disps->X_add_number -= sz;
252b5132 7493 }
29b0f896 7494 /* We should find the immediate. */
9c2799c2 7495 gas_assert (sz != 0);
29b0f896 7496 }
520dc8e8 7497
29b0f896 7498 p = frag_more (size);
d258b828 7499 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7500 if (GOT_symbol
2bbd9c25 7501 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7502 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7503 || reloc_type == BFD_RELOC_X86_64_32S
7504 || (reloc_type == BFD_RELOC_64
7505 && object_64bit))
d6ab8113
JB		 7506 && (i.op[n].disps->X_op == O_symbol
7507 || (i.op[n].disps->X_op == O_add
7508 && ((symbol_get_value_expression
7509 (i.op[n].disps->X_op_symbol)->X_op)
7510 == O_subtract))))
7511 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7512 {
7513 offsetT add;
7514
7515 if (insn_start_frag == frag_now)
7516 add = (p - frag_now->fr_literal) - insn_start_off;
7517 else
7518 {
7519 fragS *fr;
7520
7521 add = insn_start_frag->fr_fix - insn_start_off;
7522 for (fr = insn_start_frag->fr_next;
7523 fr && fr != frag_now; fr = fr->fr_next)
7524 add += fr->fr_fix;
7525 add += p - frag_now->fr_literal;
7526 }
7527
4fa24527 7528 if (!object_64bit)
7b81dfbb
AJ		 7529 {
7530 reloc_type = BFD_RELOC_386_GOTPC;
7531 i.op[n].imms->X_add_number += add;
7532 }
7533 else if (reloc_type == BFD_RELOC_64)
7534 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7535 else
7b81dfbb
AJ		 7536 /* Don't do the adjustment for x86-64, as there
7537 the pcrel addressing is relative to the _next_
7538 insn, and that is taken care of in other code. */
d6ab8113 7539 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7540 }
02a86693
L		 7541 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7542 size, i.op[n].disps, pcrel,
7543 reloc_type);
7544 /* Check for "call/jmp *mem", "mov mem, %reg",
7545 "test %reg, mem" and "binop mem, %reg" where binop
7546 is one of adc, add, and, cmp, or, sbb, sub, xor
0cb4071e
L		 7547 instructions. Always generate R_386_GOT32X for
7548 "sym*GOT" operand in 32-bit mode. */
7549 if ((generate_relax_relocations
7550 || (!object_64bit
7551 && i.rm.mode == 0
7552 && i.rm.regmem == 5))
7553 && (i.rm.mode == 2
7554 || (i.rm.mode == 0 && i.rm.regmem == 5))
02a86693
L		 7555 && ((i.operands == 1
7556 && i.tm.base_opcode == 0xff
7557 && (i.rm.reg == 2 || i.rm.reg == 4))
7558 || (i.operands == 2
7559 && (i.tm.base_opcode == 0x8b
7560 || i.tm.base_opcode == 0x85
7561 || (i.tm.base_opcode & 0xc7) == 0x03))))
7562 {
7563 if (object_64bit)
7564 {
7565 fixP->fx_tcbit = i.rex != 0;
7566 if (i.base_reg
7567 && (i.base_reg->reg_num == RegRip
7568 || i.base_reg->reg_num == RegEip))
7569 fixP->fx_tcbit2 = 1;
7570 }
7571 else
7572 fixP->fx_tcbit2 = 1;
7573 }
29b0f896
AM		 7574 }
7575 }
7576 }
7577}
252b5132 7578
29b0f896 7579static void
64e74474 7580output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7581{
7582 char *p;
7583 unsigned int n;
252b5132 7584
29b0f896
AM		 7585 for (n = 0; n < i.operands; n++)
7586 {
43234a1e
L		 7587 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7588 if (i.rounding && (int) n == i.rounding->operand)
7589 continue;
7590
40fb9820 7591 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7592 {
7593 if (i.op[n].imms->X_op == O_constant)
7594 {
e205caa7 7595 int size = imm_size (n);
29b0f896 7596 offsetT val;
b4cac588 7597
29b0f896
AM		 7598 val = offset_in_range (i.op[n].imms->X_add_number,
7599 size);
7600 p = frag_more (size);
7601 md_number_to_chars (p, val, size);
7602 }
7603 else
7604 {
7605 /* Not absolute_section.
7606 Need a 32-bit fixup (don't support 8bit
7607 non-absolute imms). Try to support other
7608 sizes ... */
f86103b7 7609 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7610 int size = imm_size (n);
7611 int sign;
29b0f896 7612
40fb9820 7613 if (i.types[n].bitfield.imm32s
a7d61044 7614 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7615 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7616 sign = 1;
e205caa7
L		 7617 else
7618 sign = 0;
520dc8e8 7619
29b0f896 7620 p = frag_more (size);
d258b828 7621 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 7622
2bbd9c25
JJ		 7623 /* This is tough to explain. We end up with this one if we
7624 * have operands that look like
7625 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7626 * obtain the absolute address of the GOT, and it is strongly
7627 * preferable from a performance point of view to avoid using
7628 * a runtime relocation for this. The actual sequence of
7629 * instructions often look something like:
7630 *
7631 * call .L66
7632 * .L66:
7633 * popl %ebx
7634 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7635 *
7636 * The call and pop essentially return the absolute address
7637 * of the label .L66 and store it in %ebx. The linker itself
7638 * will ultimately change the first operand of the addl so
7639 * that %ebx points to the GOT, but to keep things simple, the
7640 * .o file must have this operand set so that it generates not
7641 * the absolute address of .L66, but the absolute address of
7642 * itself. This allows the linker itself simply treat a GOTPC
7643 * relocation as asking for a pcrel offset to the GOT to be
7644 * added in, and the addend of the relocation is stored in the
7645 * operand field for the instruction itself.
7646 *
7647 * Our job here is to fix the operand so that it would add
7648 * the correct offset so that %ebx would point to itself. The
7649 * thing that is tricky is that .-.L66 will point to the
7650 * beginning of the instruction, so we need to further modify
7651 * the operand so that it will point to itself. There are
7652 * other cases where you have something like:
7653 *
7654 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7655 *
7656 * and here no correction would be required. Internally in
7657 * the assembler we treat operands of this form as not being
7658 * pcrel since the '.' is explicitly mentioned, and I wonder
7659 * whether it would simplify matters to do it this way. Who
7660 * knows. In earlier versions of the PIC patches, the
7661 * pcrel_adjust field was used to store the correction, but
7662 * since the expression is not pcrel, I felt it would be
7663 * confusing to do it this way. */
7664
d6ab8113 7665 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7666 || reloc_type == BFD_RELOC_X86_64_32S
7667 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7668 && GOT_symbol
7669 && GOT_symbol == i.op[n].imms->X_add_symbol
7670 && (i.op[n].imms->X_op == O_symbol
7671 || (i.op[n].imms->X_op == O_add
7672 && ((symbol_get_value_expression
7673 (i.op[n].imms->X_op_symbol)->X_op)
7674 == O_subtract))))
7675 {
2bbd9c25
JJ		 7676 offsetT add;
7677
7678 if (insn_start_frag == frag_now)
7679 add = (p - frag_now->fr_literal) - insn_start_off;
7680 else
7681 {
7682 fragS *fr;
7683
7684 add = insn_start_frag->fr_fix - insn_start_off;
7685 for (fr = insn_start_frag->fr_next;
7686 fr && fr != frag_now; fr = fr->fr_next)
7687 add += fr->fr_fix;
7688 add += p - frag_now->fr_literal;
7689 }
7690
4fa24527 7691 if (!object_64bit)
d6ab8113 7692 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7693 else if (size == 4)
d6ab8113 7694 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7695 else if (size == 8)
7696 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7697 i.op[n].imms->X_add_number += add;
29b0f896 7698 }
29b0f896
AM		 7699 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7700 i.op[n].imms, 0, reloc_type);
7701 }
7702 }
7703 }
252b5132
RH		 7704}
7705\f
d182319b
JB		 7706/* x86_cons_fix_new is called via the expression parsing code when a
7707 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 7708static int cons_sign = -1;
7709
7710void
e3bb37b5 7711x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 7712 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 7713{
d258b828 7714 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 7715
7716#ifdef TE_PE
7717 if (exp->X_op == O_secrel)
7718 {
7719 exp->X_op = O_symbol;
7720 r = BFD_RELOC_32_SECREL;
7721 }
7722#endif
7723
7724 fix_new_exp (frag, off, len, exp, 0, r);
7725}
7726
357d1bd8
L		 7727/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7728 purpose of the `.dc.a' internal pseudo-op. */
7729
7730int
7731x86_address_bytes (void)
7732{
7733 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7734 return 4;
7735 return stdoutput->arch_info->bits_per_address / 8;
7736}
7737
d382c579
TG		 7738#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7739 || defined (LEX_AT)
d258b828 7740# define lex_got(reloc, adjust, types) NULL
718ddfc0 7741#else
f3c180ae
AM		 7742/* Parse operands of the form
7743 <symbol>@GOTOFF+<nnn>
7744 and similar .plt or .got references.
7745
7746 If we find one, set up the correct relocation in RELOC and copy the
7747 input string, minus the `@GOTOFF' into a malloc'd buffer for
7748 parsing by the calling routine. Return this buffer, and if ADJUST
7749 is non-null set it to the length of the string we removed from the
7750 input line. Otherwise return NULL. */
7751static char *
91d6fa6a 7752lex_got (enum bfd_reloc_code_real *rel,
64e74474 7753 int *adjust,
d258b828 7754 i386_operand_type *types)
f3c180ae 7755{
7b81dfbb
AJ		 7756 /* Some of the relocations depend on the size of what field is to
7757 be relocated. But in our callers i386_immediate and i386_displacement
7758 we don't yet know the operand size (this will be set by insn
7759 matching). Hence we record the word32 relocation here,
7760 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7761 static const struct {
7762 const char *str;
cff8d58a 7763 int len;
4fa24527 7764 const enum bfd_reloc_code_real rel[2];
40fb9820 7765 const i386_operand_type types64;
f3c180ae 7766 } gotrel[] = {
8ce3d284 7767#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7768 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7769 BFD_RELOC_SIZE32 },
7770 OPERAND_TYPE_IMM32_64 },
8ce3d284 7771#endif
cff8d58a
L		 7772 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7773 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7774 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7775 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7776 BFD_RELOC_X86_64_PLT32 },
40fb9820 7777 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7778 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7779 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7780 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7781 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7782 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7783 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7784 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7785 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7786 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7787 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7788 BFD_RELOC_X86_64_TLSGD },
40fb9820 7789 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7790 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7791 _dummy_first_bfd_reloc_code_real },
40fb9820 7792 OPERAND_TYPE_NONE },
cff8d58a
L		 7793 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7794 BFD_RELOC_X86_64_TLSLD },
40fb9820 7795 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7796 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7797 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7798 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7799 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7800 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7801 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7802 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7803 _dummy_first_bfd_reloc_code_real },
40fb9820 7804 OPERAND_TYPE_NONE },
cff8d58a
L		 7805 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7806 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7807 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7808 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7809 _dummy_first_bfd_reloc_code_real },
40fb9820 7810 OPERAND_TYPE_NONE },
cff8d58a
L		 7811 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7812 _dummy_first_bfd_reloc_code_real },
40fb9820 7813 OPERAND_TYPE_NONE },
cff8d58a
L		 7814 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7815 BFD_RELOC_X86_64_GOT32 },
40fb9820 7816 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7817 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7818 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7819 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7820 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7821 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7822 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7823 };
7824 char *cp;
7825 unsigned int j;
7826
d382c579 7827#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7828 if (!IS_ELF)
7829 return NULL;
d382c579 7830#endif
718ddfc0 7831
f3c180ae 7832 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7833 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7834 return NULL;
7835
47465058 7836 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7837 {
cff8d58a 7838 int len = gotrel[j].len;
28f81592 7839 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7840 {
4fa24527 7841 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7842 {
28f81592
AM		 7843 int first, second;
7844 char *tmpbuf, *past_reloc;
f3c180ae 7845
91d6fa6a 7846 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7847
3956db08
JB		 7848 if (types)
7849 {
7850 if (flag_code != CODE_64BIT)
40fb9820
L		 7851 {
7852 types->bitfield.imm32 = 1;
7853 types->bitfield.disp32 = 1;
7854 }
3956db08
JB		 7855 else
7856 *types = gotrel[j].types64;
7857 }
7858
8fd4256d 7859 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7860 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7861
28f81592 7862 /* The length of the first part of our input line. */
f3c180ae 7863 first = cp - input_line_pointer;
28f81592
AM		 7864
7865 /* The second part goes from after the reloc token until
67c11a9b 7866 (and including) an end_of_line char or comma. */
28f81592 7867 past_reloc = cp + 1 + len;
67c11a9b
AM		 7868 cp = past_reloc;
7869 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7870 ++cp;
7871 second = cp + 1 - past_reloc;
28f81592
AM		 7872
7873 /* Allocate and copy string. The trailing NUL shouldn't
7874 be necessary, but be safe. */
add39d23 7875 tmpbuf = XNEWVEC (char, first + second + 2);
f3c180ae 7876 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7877 if (second != 0 && *past_reloc != ' ')
7878 /* Replace the relocation token with ' ', so that
7879 errors like foo@GOTOFF1 will be detected. */
7880 tmpbuf[first++] = ' ';
af89796a
L		 7881 else
7882 /* Increment length by 1 if the relocation token is
7883 removed. */
7884 len++;
7885 if (adjust)
7886 *adjust = len;
0787a12d
AM		 7887 memcpy (tmpbuf + first, past_reloc, second);
7888 tmpbuf[first + second] = '\0';
f3c180ae
AM		 7889 return tmpbuf;
7890 }
7891
4fa24527
JB		 7892 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7893 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7894 return NULL;
7895 }
7896 }
7897
7898 /* Might be a symbol version string. Don't as_bad here. */
7899 return NULL;
7900}
4e4f7c87 7901#endif
f3c180ae 7902
a988325c
NC		 7903#ifdef TE_PE
7904#ifdef lex_got
7905#undef lex_got
7906#endif
7907/* Parse operands of the form
7908 <symbol>@SECREL32+<nnn>
7909
7910 If we find one, set up the correct relocation in RELOC and copy the
7911 input string, minus the `@SECREL32' into a malloc'd buffer for
7912 parsing by the calling routine. Return this buffer, and if ADJUST
7913 is non-null set it to the length of the string we removed from the
34bca508
L		 7914 input line. Otherwise return NULL.
7915
a988325c
NC		 7916 This function is copied from the ELF version above adjusted for PE targets. */
7917
7918static char *
7919lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7920 int *adjust ATTRIBUTE_UNUSED,
d258b828 7921 i386_operand_type *types)
a988325c
NC		 7922{
7923 static const struct
7924 {
7925 const char *str;
7926 int len;
7927 const enum bfd_reloc_code_real rel[2];
7928 const i386_operand_type types64;
7929 }
7930 gotrel[] =
7931 {
7932 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7933 BFD_RELOC_32_SECREL },
7934 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7935 };
7936
7937 char *cp;
7938 unsigned j;
7939
7940 for (cp = input_line_pointer; *cp != '@'; cp++)
7941 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7942 return NULL;
7943
7944 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7945 {
7946 int len = gotrel[j].len;
7947
7948 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7949 {
7950 if (gotrel[j].rel[object_64bit] != 0)
7951 {
7952 int first, second;
7953 char *tmpbuf, *past_reloc;
7954
7955 *rel = gotrel[j].rel[object_64bit];
7956 if (adjust)
7957 *adjust = len;
7958
7959 if (types)
7960 {
7961 if (flag_code != CODE_64BIT)
7962 {
7963 types->bitfield.imm32 = 1;
7964 types->bitfield.disp32 = 1;
7965 }
7966 else
7967 *types = gotrel[j].types64;
7968 }
7969
7970 /* The length of the first part of our input line. */
7971 first = cp - input_line_pointer;
7972
7973 /* The second part goes from after the reloc token until
7974 (and including) an end_of_line char or comma. */
7975 past_reloc = cp + 1 + len;
7976 cp = past_reloc;
7977 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7978 ++cp;
7979 second = cp + 1 - past_reloc;
7980
7981 /* Allocate and copy string. The trailing NUL shouldn't
7982 be necessary, but be safe. */
add39d23 7983 tmpbuf = XNEWVEC (char, first + second + 2);
a988325c
NC		 7984 memcpy (tmpbuf, input_line_pointer, first);
7985 if (second != 0 && *past_reloc != ' ')
7986 /* Replace the relocation token with ' ', so that
7987 errors like foo@SECLREL321 will be detected. */
7988 tmpbuf[first++] = ' ';
7989 memcpy (tmpbuf + first, past_reloc, second);
7990 tmpbuf[first + second] = '\0';
7991 return tmpbuf;
7992 }
7993
7994 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7995 gotrel[j].str, 1 << (5 + object_64bit));
7996 return NULL;
7997 }
7998 }
7999
8000 /* Might be a symbol version string. Don't as_bad here. */
8001 return NULL;
8002}
8003
8004#endif /* TE_PE */
8005
62ebcb5c 8006bfd_reloc_code_real_type
e3bb37b5 8007x86_cons (expressionS *exp, int size)
f3c180ae 8008{
62ebcb5c
AM		 8009 bfd_reloc_code_real_type got_reloc = NO_RELOC;
8010
ee86248c
JB		 8011 intel_syntax = -intel_syntax;
8012
3c7b9c2c 8013 exp->X_md = 0;
4fa24527 8014 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 8015 {
8016 /* Handle @GOTOFF and the like in an expression. */
8017 char *save;
8018 char *gotfree_input_line;
4a57f2cf 8019 int adjust = 0;
f3c180ae
AM		 8020
8021 save = input_line_pointer;
d258b828 8022 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 8023 if (gotfree_input_line)
8024 input_line_pointer = gotfree_input_line;
8025
8026 expression (exp);
8027
8028 if (gotfree_input_line)
8029 {
8030 /* expression () has merrily parsed up to the end of line,
8031 or a comma - in the wrong buffer. Transfer how far
8032 input_line_pointer has moved to the right buffer. */
8033 input_line_pointer = (save
8034 + (input_line_pointer - gotfree_input_line)
8035 + adjust);
8036 free (gotfree_input_line);
3992d3b7
AM		 8037 if (exp->X_op == O_constant
8038 || exp->X_op == O_absent
8039 || exp->X_op == O_illegal
0398aac5 8040 || exp->X_op == O_register
3992d3b7
AM		 8041 || exp->X_op == O_big)
8042 {
8043 char c = *input_line_pointer;
8044 *input_line_pointer = 0;
8045 as_bad (_("missing or invalid expression `%s'"), save);
8046 *input_line_pointer = c;
8047 }
f3c180ae
AM		 8048 }
8049 }
8050 else
8051 expression (exp);
ee86248c
JB		 8052
8053 intel_syntax = -intel_syntax;
8054
8055 if (intel_syntax)
8056 i386_intel_simplify (exp);
62ebcb5c
AM		 8057
8058 return got_reloc;
f3c180ae 8059}
f3c180ae 8060
9f32dd5b
L		 8061static void
8062signed_cons (int size)
6482c264 8063{
d182319b
JB		 8064 if (flag_code == CODE_64BIT)
8065 cons_sign = 1;
8066 cons (size);
8067 cons_sign = -1;
6482c264
NC		 8068}
8069
d182319b 8070#ifdef TE_PE
6482c264 8071static void
7016a5d5 8072pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 8073{
8074 expressionS exp;
8075
8076 do
8077 {
8078 expression (&exp);
8079 if (exp.X_op == O_symbol)
8080 exp.X_op = O_secrel;
8081
8082 emit_expr (&exp, 4);
8083 }
8084 while (*input_line_pointer++ == ',');
8085
8086 input_line_pointer--;
8087 demand_empty_rest_of_line ();
8088}
6482c264
NC		 8089#endif
8090
43234a1e
L		 8091/* Handle Vector operations. */
8092
8093static char *
8094check_VecOperations (char *op_string, char *op_end)
8095{
8096 const reg_entry *mask;
8097 const char *saved;
8098 char *end_op;
8099
8100 while (*op_string
8101 && (op_end == NULL || op_string < op_end))
8102 {
8103 saved = op_string;
8104 if (*op_string == '{')
8105 {
8106 op_string++;
8107
8108 /* Check broadcasts. */
8109 if (strncmp (op_string, "1to", 3) == 0)
8110 {
8111 int bcst_type;
8112
8113 if (i.broadcast)
8114 goto duplicated_vec_op;
8115
8116 op_string += 3;
8117 if (*op_string == '8')
8118 bcst_type = BROADCAST_1TO8;
b28d1bda
IT		 8119 else if (*op_string == '4')
8120 bcst_type = BROADCAST_1TO4;
8121 else if (*op_string == '2')
8122 bcst_type = BROADCAST_1TO2;
43234a1e
L		 8123 else if (*op_string == '1'
8124 && *(op_string+1) == '6')
8125 {
8126 bcst_type = BROADCAST_1TO16;
8127 op_string++;
8128 }
8129 else
8130 {
8131 as_bad (_("Unsupported broadcast: `%s'"), saved);
8132 return NULL;
8133 }
8134 op_string++;
8135
8136 broadcast_op.type = bcst_type;
8137 broadcast_op.operand = this_operand;
8138 i.broadcast = &broadcast_op;
8139 }
8140 /* Check masking operation. */
8141 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8142 {
8143 /* k0 can't be used for write mask. */
8144 if (mask->reg_num == 0)
8145 {
8146 as_bad (_("`%s' can't be used for write mask"),
8147 op_string);
8148 return NULL;
8149 }
8150
8151 if (!i.mask)
8152 {
8153 mask_op.mask = mask;
8154 mask_op.zeroing = 0;
8155 mask_op.operand = this_operand;
8156 i.mask = &mask_op;
8157 }
8158 else
8159 {
8160 if (i.mask->mask)
8161 goto duplicated_vec_op;
8162
8163 i.mask->mask = mask;
8164
8165 /* Only "{z}" is allowed here. No need to check
8166 zeroing mask explicitly. */
8167 if (i.mask->operand != this_operand)
8168 {
8169 as_bad (_("invalid write mask `%s'"), saved);
8170 return NULL;
8171 }
8172 }
8173
8174 op_string = end_op;
8175 }
8176 /* Check zeroing-flag for masking operation. */
8177 else if (*op_string == 'z')
8178 {
8179 if (!i.mask)
8180 {
8181 mask_op.mask = NULL;
8182 mask_op.zeroing = 1;
8183 mask_op.operand = this_operand;
8184 i.mask = &mask_op;
8185 }
8186 else
8187 {
8188 if (i.mask->zeroing)
8189 {
8190 duplicated_vec_op:
8191 as_bad (_("duplicated `%s'"), saved);
8192 return NULL;
8193 }
8194
8195 i.mask->zeroing = 1;
8196
8197 /* Only "{%k}" is allowed here. No need to check mask
8198 register explicitly. */
8199 if (i.mask->operand != this_operand)
8200 {
8201 as_bad (_("invalid zeroing-masking `%s'"),
8202 saved);
8203 return NULL;
8204 }
8205 }
8206
8207 op_string++;
8208 }
8209 else
8210 goto unknown_vec_op;
8211
8212 if (*op_string != '}')
8213 {
8214 as_bad (_("missing `}' in `%s'"), saved);
8215 return NULL;
8216 }
8217 op_string++;
8218 continue;
8219 }
8220 unknown_vec_op:
8221 /* We don't know this one. */
8222 as_bad (_("unknown vector operation: `%s'"), saved);
8223 return NULL;
8224 }
8225
8226 return op_string;
8227}
8228
252b5132 8229static int
70e41ade 8230i386_immediate (char *imm_start)
252b5132
RH		 8231{
8232 char *save_input_line_pointer;
f3c180ae 8233 char *gotfree_input_line;
252b5132 8234 segT exp_seg = 0;
47926f60 8235 expressionS *exp;
40fb9820
L		 8236 i386_operand_type types;
8237
0dfbf9d7 8238 operand_type_set (&types, ~0);
252b5132
RH		 8239
8240 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8241 {
31b2323c
L		 8242 as_bad (_("at most %d immediate operands are allowed"),
8243 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 8244 return 0;
8245 }
8246
8247 exp = &im_expressions[i.imm_operands++];
520dc8e8 8248 i.op[this_operand].imms = exp;
252b5132
RH		 8249
8250 if (is_space_char (*imm_start))
8251 ++imm_start;
8252
8253 save_input_line_pointer = input_line_pointer;
8254 input_line_pointer = imm_start;
8255
d258b828 8256 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8257 if (gotfree_input_line)
8258 input_line_pointer = gotfree_input_line;
252b5132
RH		 8259
8260 exp_seg = expression (exp);
8261
83183c0c 8262 SKIP_WHITESPACE ();
43234a1e
L		 8263
8264 /* Handle vector operations. */
8265 if (*input_line_pointer == '{')
8266 {
8267 input_line_pointer = check_VecOperations (input_line_pointer,
8268 NULL);
8269 if (input_line_pointer == NULL)
8270 return 0;
8271 }
8272
252b5132 8273 if (*input_line_pointer)
f3c180ae 8274 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 8275
8276 input_line_pointer = save_input_line_pointer;
f3c180ae 8277 if (gotfree_input_line)
ee86248c
JB		 8278 {
8279 free (gotfree_input_line);
8280
8281 if (exp->X_op == O_constant || exp->X_op == O_register)
8282 exp->X_op = O_illegal;
8283 }
8284
8285 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8286}
252b5132 8287
ee86248c
JB		 8288static int
8289i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8290 i386_operand_type types, const char *imm_start)
8291{
8292 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 8293 {
313c53d1
L		 8294 if (imm_start)
8295 as_bad (_("missing or invalid immediate expression `%s'"),
8296 imm_start);
3992d3b7 8297 return 0;
252b5132 8298 }
3e73aa7c 8299 else if (exp->X_op == O_constant)
252b5132 8300 {
47926f60 8301 /* Size it properly later. */
40fb9820 8302 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 8303 /* If not 64bit, sign extend val. */
8304 if (flag_code != CODE_64BIT
4eed87de
AM		 8305 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8306 exp->X_add_number
8307 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 8308 }
4c63da97 8309#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 8310 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 8311 && exp_seg != absolute_section
47926f60 8312 && exp_seg != text_section
24eab124
AM		 8313 && exp_seg != data_section
8314 && exp_seg != bss_section
8315 && exp_seg != undefined_section
f86103b7 8316 && !bfd_is_com_section (exp_seg))
252b5132 8317 {
d0b47220 8318 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 8319 return 0;
8320 }
8321#endif
a841bdf5 8322 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 8323 {
313c53d1
L		 8324 if (imm_start)
8325 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 8326 return 0;
8327 }
252b5132
RH		 8328 else
8329 {
8330 /* This is an address. The size of the address will be
24eab124 8331 determined later, depending on destination register,
3e73aa7c 8332 suffix, or the default for the section. */
40fb9820
L		 8333 i.types[this_operand].bitfield.imm8 = 1;
8334 i.types[this_operand].bitfield.imm16 = 1;
8335 i.types[this_operand].bitfield.imm32 = 1;
8336 i.types[this_operand].bitfield.imm32s = 1;
8337 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8338 i.types[this_operand] = operand_type_and (i.types[this_operand],
8339 types);
252b5132
RH		 8340 }
8341
8342 return 1;
8343}
8344
551c1ca1 8345static char *
e3bb37b5 8346i386_scale (char *scale)
252b5132 8347{
551c1ca1
AM		 8348 offsetT val;
8349 char *save = input_line_pointer;
252b5132 8350
551c1ca1
AM		 8351 input_line_pointer = scale;
8352 val = get_absolute_expression ();
8353
8354 switch (val)
252b5132 8355 {
551c1ca1 8356 case 1:
252b5132
RH		 8357 i.log2_scale_factor = 0;
8358 break;
551c1ca1 8359 case 2:
252b5132
RH		 8360 i.log2_scale_factor = 1;
8361 break;
551c1ca1 8362 case 4:
252b5132
RH		 8363 i.log2_scale_factor = 2;
8364 break;
551c1ca1 8365 case 8:
252b5132
RH		 8366 i.log2_scale_factor = 3;
8367 break;
8368 default:
a724f0f4
JB		 8369 {
8370 char sep = *input_line_pointer;
8371
8372 *input_line_pointer = '\0';
8373 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8374 scale);
8375 *input_line_pointer = sep;
8376 input_line_pointer = save;
8377 return NULL;
8378 }
252b5132 8379 }
29b0f896 8380 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8381 {
8382 as_warn (_("scale factor of %d without an index register"),
24eab124 8383 1 << i.log2_scale_factor);
252b5132 8384 i.log2_scale_factor = 0;
252b5132 8385 }
551c1ca1
AM		 8386 scale = input_line_pointer;
8387 input_line_pointer = save;
8388 return scale;
252b5132
RH		 8389}
8390
252b5132 8391static int
e3bb37b5 8392i386_displacement (char *disp_start, char *disp_end)
252b5132 8393{
29b0f896 8394 expressionS *exp;
252b5132
RH		 8395 segT exp_seg = 0;
8396 char *save_input_line_pointer;
f3c180ae 8397 char *gotfree_input_line;
40fb9820
L		 8398 int override;
8399 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8400 int ret;
252b5132 8401
31b2323c
L		 8402 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8403 {
8404 as_bad (_("at most %d displacement operands are allowed"),
8405 MAX_MEMORY_OPERANDS);
8406 return 0;
8407 }
8408
0dfbf9d7 8409 operand_type_set (&bigdisp, 0);
40fb9820
L		 8410 if ((i.types[this_operand].bitfield.jumpabsolute)
8411 || (!current_templates->start->opcode_modifier.jump
8412 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8413 {
40fb9820 8414 bigdisp.bitfield.disp32 = 1;
e05278af 8415 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8416 if (flag_code == CODE_64BIT)
8417 {
8418 if (!override)
8419 {
8420 bigdisp.bitfield.disp32s = 1;
8421 bigdisp.bitfield.disp64 = 1;
8422 }
8423 }
8424 else if ((flag_code == CODE_16BIT) ^ override)
8425 {
8426 bigdisp.bitfield.disp32 = 0;
8427 bigdisp.bitfield.disp16 = 1;
8428 }
e05278af
JB		 8429 }
8430 else
8431 {
8432 /* For PC-relative branches, the width of the displacement
8433 is dependent upon data size, not address size. */
e05278af 8434 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8435 if (flag_code == CODE_64BIT)
8436 {
8437 if (override || i.suffix == WORD_MNEM_SUFFIX)
8438 bigdisp.bitfield.disp16 = 1;
8439 else
8440 {
8441 bigdisp.bitfield.disp32 = 1;
8442 bigdisp.bitfield.disp32s = 1;
8443 }
8444 }
8445 else
e05278af
JB		 8446 {
8447 if (!override)
8448 override = (i.suffix == (flag_code != CODE_16BIT
8449 ? WORD_MNEM_SUFFIX
8450 : LONG_MNEM_SUFFIX));
40fb9820
L		 8451 bigdisp.bitfield.disp32 = 1;
8452 if ((flag_code == CODE_16BIT) ^ override)
8453 {
8454 bigdisp.bitfield.disp32 = 0;
8455 bigdisp.bitfield.disp16 = 1;
8456 }
e05278af 8457 }
e05278af 8458 }
c6fb90c8
L		 8459 i.types[this_operand] = operand_type_or (i.types[this_operand],
8460 bigdisp);
252b5132
RH		 8461
8462 exp = &disp_expressions[i.disp_operands];
520dc8e8 8463 i.op[this_operand].disps = exp;
252b5132
RH		 8464 i.disp_operands++;
8465 save_input_line_pointer = input_line_pointer;
8466 input_line_pointer = disp_start;
8467 END_STRING_AND_SAVE (disp_end);
8468
8469#ifndef GCC_ASM_O_HACK
8470#define GCC_ASM_O_HACK 0
8471#endif
8472#if GCC_ASM_O_HACK
8473 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8474 if (i.types[this_operand].bitfield.baseIndex
24eab124 8475 && displacement_string_end[-1] == '+')
252b5132
RH		 8476 {
8477 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8478 constraint within gcc asm statements.
8479 For instance:
8480
8481 #define _set_tssldt_desc(n,addr,limit,type) \
8482 __asm__ __volatile__ ( \
8483 "movw %w2,%0\n\t" \
8484 "movw %w1,2+%0\n\t" \
8485 "rorl $16,%1\n\t" \
8486 "movb %b1,4+%0\n\t" \
8487 "movb %4,5+%0\n\t" \
8488 "movb $0,6+%0\n\t" \
8489 "movb %h1,7+%0\n\t" \
8490 "rorl $16,%1" \
8491 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8492
8493 This works great except that the output assembler ends
8494 up looking a bit weird if it turns out that there is
8495 no offset. You end up producing code that looks like:
8496
8497 #APP
8498 movw $235,(%eax)
8499 movw %dx,2+(%eax)
8500 rorl $16,%edx
8501 movb %dl,4+(%eax)
8502 movb $137,5+(%eax)
8503 movb $0,6+(%eax)
8504 movb %dh,7+(%eax)
8505 rorl $16,%edx
8506 #NO_APP
8507
47926f60 8508 So here we provide the missing zero. */
24eab124
AM		 8509
8510 *displacement_string_end = '0';
252b5132
RH		 8511 }
8512#endif
d258b828 8513 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8514 if (gotfree_input_line)
8515 input_line_pointer = gotfree_input_line;
252b5132 8516
24eab124 8517 exp_seg = expression (exp);
252b5132 8518
636c26b0
AM		 8519 SKIP_WHITESPACE ();
8520 if (*input_line_pointer)
8521 as_bad (_("junk `%s' after expression"), input_line_pointer);
8522#if GCC_ASM_O_HACK
8523 RESTORE_END_STRING (disp_end + 1);
8524#endif
636c26b0 8525 input_line_pointer = save_input_line_pointer;
636c26b0 8526 if (gotfree_input_line)
ee86248c
JB		 8527 {
8528 free (gotfree_input_line);
8529
8530 if (exp->X_op == O_constant || exp->X_op == O_register)
8531 exp->X_op = O_illegal;
8532 }
8533
8534 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8535
8536 RESTORE_END_STRING (disp_end);
8537
8538 return ret;
8539}
8540
8541static int
8542i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8543 i386_operand_type types, const char *disp_start)
8544{
8545 i386_operand_type bigdisp;
8546 int ret = 1;
636c26b0 8547
24eab124
AM		 8548 /* We do this to make sure that the section symbol is in
8549 the symbol table. We will ultimately change the relocation
47926f60 8550 to be relative to the beginning of the section. */
1ae12ab7 8551 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8552 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8553 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8554 {
636c26b0 8555 if (exp->X_op != O_symbol)
3992d3b7 8556 goto inv_disp;
636c26b0 8557
e5cb08ac 8558 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8559 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8560 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8561 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8562 exp->X_op = O_subtract;
8563 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8564 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8565 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8566 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8567 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8568 else
29b0f896 8569 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8570 }
252b5132 8571
3992d3b7
AM		 8572 else if (exp->X_op == O_absent
8573 || exp->X_op == O_illegal
ee86248c 8574 || exp->X_op == O_big)
2daf4fd8 8575 {
3992d3b7
AM		 8576 inv_disp:
8577 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8578 disp_start);
3992d3b7 8579 ret = 0;
2daf4fd8
AM		 8580 }
8581
0e1147d9
L		 8582 else if (flag_code == CODE_64BIT
8583 && !i.prefix[ADDR_PREFIX]
8584 && exp->X_op == O_constant)
8585 {
8586 /* Since displacement is signed extended to 64bit, don't allow
8587 disp32 and turn off disp32s if they are out of range. */
8588 i.types[this_operand].bitfield.disp32 = 0;
8589 if (!fits_in_signed_long (exp->X_add_number))
8590 {
8591 i.types[this_operand].bitfield.disp32s = 0;
8592 if (i.types[this_operand].bitfield.baseindex)
8593 {
8594 as_bad (_("0x%lx out range of signed 32bit displacement"),
8595 (long) exp->X_add_number);
8596 ret = 0;
8597 }
8598 }
8599 }
8600
4c63da97 8601#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8602 else if (exp->X_op != O_constant
8603 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8604 && exp_seg != absolute_section
8605 && exp_seg != text_section
8606 && exp_seg != data_section
8607 && exp_seg != bss_section
8608 && exp_seg != undefined_section
8609 && !bfd_is_com_section (exp_seg))
24eab124 8610 {
d0b47220 8611 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8612 ret = 0;
24eab124 8613 }
252b5132 8614#endif
3956db08 8615
40fb9820
L		 8616 /* Check if this is a displacement only operand. */
8617 bigdisp = i.types[this_operand];
8618 bigdisp.bitfield.disp8 = 0;
8619 bigdisp.bitfield.disp16 = 0;
8620 bigdisp.bitfield.disp32 = 0;
8621 bigdisp.bitfield.disp32s = 0;
8622 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8623 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8624 i.types[this_operand] = operand_type_and (i.types[this_operand],
8625 types);
3956db08 8626
3992d3b7 8627 return ret;
252b5132
RH		 8628}
8629
eecb386c 8630/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 8631 Return 1 on success, 0 on a failure. */
8632
252b5132 8633static int
e3bb37b5 8634i386_index_check (const char *operand_string)
252b5132 8635{
fc0763e6 8636 const char *kind = "base/index";
be05d201
L		 8637 enum flag_code addr_mode;
8638
8639 if (i.prefix[ADDR_PREFIX])
8640 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8641 else
8642 {
8643 addr_mode = flag_code;
8644
24eab124 8645#if INFER_ADDR_PREFIX
be05d201
L		 8646 if (i.mem_operands == 0)
8647 {
8648 /* Infer address prefix from the first memory operand. */
8649 const reg_entry *addr_reg = i.base_reg;
8650
8651 if (addr_reg == NULL)
8652 addr_reg = i.index_reg;
eecb386c 8653
be05d201
L		 8654 if (addr_reg)
8655 {
8656 if (addr_reg->reg_num == RegEip
8657 || addr_reg->reg_num == RegEiz
8658 || addr_reg->reg_type.bitfield.reg32)
8659 addr_mode = CODE_32BIT;
8660 else if (flag_code != CODE_64BIT
8661 && addr_reg->reg_type.bitfield.reg16)
8662 addr_mode = CODE_16BIT;
8663
8664 if (addr_mode != flag_code)
8665 {
8666 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8667 i.prefixes += 1;
8668 /* Change the size of any displacement too. At most one
8669 of Disp16 or Disp32 is set.
8670 FIXME. There doesn't seem to be any real need for
8671 separate Disp16 and Disp32 flags. The same goes for
8672 Imm16 and Imm32. Removing them would probably clean
8673 up the code quite a lot. */
8674 if (flag_code != CODE_64BIT
8675 && (i.types[this_operand].bitfield.disp16
8676 || i.types[this_operand].bitfield.disp32))
8677 i.types[this_operand]
8678 = operand_type_xor (i.types[this_operand], disp16_32);
8679 }
8680 }
8681 }
24eab124 8682#endif
be05d201
L		 8683 }
8684
fc0763e6
JB		 8685 if (current_templates->start->opcode_modifier.isstring
8686 && !current_templates->start->opcode_modifier.immext
8687 && (current_templates->end[-1].opcode_modifier.isstring
8688 || i.mem_operands))
8689 {
8690 /* Memory operands of string insns are special in that they only allow
8691 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8692 const reg_entry *expected_reg;
8693 static const char *di_si[][2] =
8694 {
8695 { "esi", "edi" },
8696 { "si", "di" },
8697 { "rsi", "rdi" }
8698 };
8699 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8700
8701 kind = "string address";
8702
8325cc63 8703 if (current_templates->start->opcode_modifier.repprefixok)
fc0763e6
JB		 8704 {
8705 i386_operand_type type = current_templates->end[-1].operand_types[0];
8706
8707 if (!type.bitfield.baseindex
8708 || ((!i.mem_operands != !intel_syntax)
8709 && current_templates->end[-1].operand_types[1]
8710 .bitfield.baseindex))
8711 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8712 expected_reg = hash_find (reg_hash,
8713 di_si[addr_mode][type.bitfield.esseg]);
8714
fc0763e6
JB		 8715 }
8716 else
be05d201 8717 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8718
be05d201
L		 8719 if (i.base_reg != expected_reg
8720 || i.index_reg
fc0763e6 8721 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8722 {
be05d201
L		 8723 /* The second memory operand must have the same size as
8724 the first one. */
8725 if (i.mem_operands
8726 && i.base_reg
8727 && !((addr_mode == CODE_64BIT
8728 && i.base_reg->reg_type.bitfield.reg64)
8729 || (addr_mode == CODE_32BIT
8730 ? i.base_reg->reg_type.bitfield.reg32
8731 : i.base_reg->reg_type.bitfield.reg16)))
8732 goto bad_address;
8733
fc0763e6
JB		 8734 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8735 operand_string,
8736 intel_syntax ? '[' : '(',
8737 register_prefix,
be05d201 8738 expected_reg->reg_name,
fc0763e6 8739 intel_syntax ? ']' : ')');
be05d201 8740 return 1;
fc0763e6 8741 }
be05d201
L		 8742 else
8743 return 1;
8744
8745bad_address:
8746 as_bad (_("`%s' is not a valid %s expression"),
8747 operand_string, kind);
8748 return 0;
3e73aa7c
JH		 8749 }
8750 else
8751 {
be05d201
L		 8752 if (addr_mode != CODE_16BIT)
8753 {
8754 /* 32-bit/64-bit checks. */
8755 if ((i.base_reg
8756 && (addr_mode == CODE_64BIT
8757 ? !i.base_reg->reg_type.bitfield.reg64
8758 : !i.base_reg->reg_type.bitfield.reg32)
8759 && (i.index_reg
8760 || (i.base_reg->reg_num
8761 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8762 || (i.index_reg
8763 && !i.index_reg->reg_type.bitfield.regxmm
8764 && !i.index_reg->reg_type.bitfield.regymm
43234a1e 8765 && !i.index_reg->reg_type.bitfield.regzmm
be05d201
L		 8766 && ((addr_mode == CODE_64BIT
8767 ? !(i.index_reg->reg_type.bitfield.reg64
8768 || i.index_reg->reg_num == RegRiz)
8769 : !(i.index_reg->reg_type.bitfield.reg32
8770 || i.index_reg->reg_num == RegEiz))
8771 || !i.index_reg->reg_type.bitfield.baseindex)))
8772 goto bad_address;
8178be5b
JB		 8773
8774 /* bndmk, bndldx, and bndstx have special restrictions. */
8775 if (current_templates->start->base_opcode == 0xf30f1b
8776 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
8777 {
8778 /* They cannot use RIP-relative addressing. */
8779 if (i.base_reg && i.base_reg->reg_num == RegRip)
8780 {
8781 as_bad (_("`%s' cannot be used here"), operand_string);
8782 return 0;
8783 }
8784
8785 /* bndldx and bndstx ignore their scale factor. */
8786 if (current_templates->start->base_opcode != 0xf30f1b
8787 && i.log2_scale_factor)
8788 as_warn (_("register scaling is being ignored here"));
8789 }
be05d201
L		 8790 }
8791 else
3e73aa7c 8792 {
be05d201 8793 /* 16-bit checks. */
3e73aa7c 8794 if ((i.base_reg
40fb9820
L		 8795 && (!i.base_reg->reg_type.bitfield.reg16
8796 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8797 || (i.index_reg
40fb9820
L		 8798 && (!i.index_reg->reg_type.bitfield.reg16
8799 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8800 || !(i.base_reg
8801 && i.base_reg->reg_num < 6
8802 && i.index_reg->reg_num >= 6
8803 && i.log2_scale_factor == 0))))
be05d201 8804 goto bad_address;
3e73aa7c
JH		 8805 }
8806 }
be05d201 8807 return 1;
24eab124 8808}
252b5132 8809
43234a1e
L		 8810/* Handle vector immediates. */
8811
8812static int
8813RC_SAE_immediate (const char *imm_start)
8814{
8815 unsigned int match_found, j;
8816 const char *pstr = imm_start;
8817 expressionS *exp;
8818
8819 if (*pstr != '{')
8820 return 0;
8821
8822 pstr++;
8823 match_found = 0;
8824 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8825 {
8826 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8827 {
8828 if (!i.rounding)
8829 {
8830 rc_op.type = RC_NamesTable[j].type;
8831 rc_op.operand = this_operand;
8832 i.rounding = &rc_op;
8833 }
8834 else
8835 {
8836 as_bad (_("duplicated `%s'"), imm_start);
8837 return 0;
8838 }
8839 pstr += RC_NamesTable[j].len;
8840 match_found = 1;
8841 break;
8842 }
8843 }
8844 if (!match_found)
8845 return 0;
8846
8847 if (*pstr++ != '}')
8848 {
8849 as_bad (_("Missing '}': '%s'"), imm_start);
8850 return 0;
8851 }
8852 /* RC/SAE immediate string should contain nothing more. */;
8853 if (*pstr != 0)
8854 {
8855 as_bad (_("Junk after '}': '%s'"), imm_start);
8856 return 0;
8857 }
8858
8859 exp = &im_expressions[i.imm_operands++];
8860 i.op[this_operand].imms = exp;
8861
8862 exp->X_op = O_constant;
8863 exp->X_add_number = 0;
8864 exp->X_add_symbol = (symbolS *) 0;
8865 exp->X_op_symbol = (symbolS *) 0;
8866
8867 i.types[this_operand].bitfield.imm8 = 1;
8868 return 1;
8869}
8870
8325cc63
JB		 8871/* Only string instructions can have a second memory operand, so
8872 reduce current_templates to just those if it contains any. */
8873static int
8874maybe_adjust_templates (void)
8875{
8876 const insn_template *t;
8877
8878 gas_assert (i.mem_operands == 1);
8879
8880 for (t = current_templates->start; t < current_templates->end; ++t)
8881 if (t->opcode_modifier.isstring)
8882 break;
8883
8884 if (t < current_templates->end)
8885 {
8886 static templates aux_templates;
8887 bfd_boolean recheck;
8888
8889 aux_templates.start = t;
8890 for (; t < current_templates->end; ++t)
8891 if (!t->opcode_modifier.isstring)
8892 break;
8893 aux_templates.end = t;
8894
8895 /* Determine whether to re-check the first memory operand. */
8896 recheck = (aux_templates.start != current_templates->start
8897 || t != current_templates->end);
8898
8899 current_templates = &aux_templates;
8900
8901 if (recheck)
8902 {
8903 i.mem_operands = 0;
8904 if (i.memop1_string != NULL
8905 && i386_index_check (i.memop1_string) == 0)
8906 return 0;
8907 i.mem_operands = 1;
8908 }
8909 }
8910
8911 return 1;
8912}
8913
fc0763e6 8914/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8915 on error. */
252b5132 8916
252b5132 8917static int
a7619375 8918i386_att_operand (char *operand_string)
252b5132 8919{
af6bdddf
AM		 8920 const reg_entry *r;
8921 char *end_op;
24eab124 8922 char *op_string = operand_string;
252b5132 8923
24eab124 8924 if (is_space_char (*op_string))
252b5132
RH		 8925 ++op_string;
8926
24eab124 8927 /* We check for an absolute prefix (differentiating,
47926f60 8928 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8929 if (*op_string == ABSOLUTE_PREFIX)
8930 {
8931 ++op_string;
8932 if (is_space_char (*op_string))
8933 ++op_string;
40fb9820 8934 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8935 }
252b5132 8936
47926f60 8937 /* Check if operand is a register. */
4d1bb795 8938 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8939 {
40fb9820
L		 8940 i386_operand_type temp;
8941
24eab124
AM		 8942 /* Check for a segment override by searching for ':' after a
8943 segment register. */
8944 op_string = end_op;
8945 if (is_space_char (*op_string))
8946 ++op_string;
40fb9820
L		 8947 if (*op_string == ':'
8948 && (r->reg_type.bitfield.sreg2
8949 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8950 {
8951 switch (r->reg_num)
8952 {
8953 case 0:
8954 i.seg[i.mem_operands] = &es;
8955 break;
8956 case 1:
8957 i.seg[i.mem_operands] = &cs;
8958 break;
8959 case 2:
8960 i.seg[i.mem_operands] = &ss;
8961 break;
8962 case 3:
8963 i.seg[i.mem_operands] = &ds;
8964 break;
8965 case 4:
8966 i.seg[i.mem_operands] = &fs;
8967 break;
8968 case 5:
8969 i.seg[i.mem_operands] = &gs;
8970 break;
8971 }
252b5132 8972
24eab124 8973 /* Skip the ':' and whitespace. */
252b5132
RH		 8974 ++op_string;
8975 if (is_space_char (*op_string))
24eab124 8976 ++op_string;
252b5132 8977
24eab124
AM		 8978 if (!is_digit_char (*op_string)
8979 && !is_identifier_char (*op_string)
8980 && *op_string != '('
8981 && *op_string != ABSOLUTE_PREFIX)
8982 {
8983 as_bad (_("bad memory operand `%s'"), op_string);
8984 return 0;
8985 }
47926f60 8986 /* Handle case of %es:*foo. */
24eab124
AM		 8987 if (*op_string == ABSOLUTE_PREFIX)
8988 {
8989 ++op_string;
8990 if (is_space_char (*op_string))
8991 ++op_string;
40fb9820 8992 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8993 }
8994 goto do_memory_reference;
8995 }
43234a1e
L		 8996
8997 /* Handle vector operations. */
8998 if (*op_string == '{')
8999 {
9000 op_string = check_VecOperations (op_string, NULL);
9001 if (op_string == NULL)
9002 return 0;
9003 }
9004
24eab124
AM		 9005 if (*op_string)
9006 {
d0b47220 9007 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 9008 return 0;
9009 }
40fb9820
L		 9010 temp = r->reg_type;
9011 temp.bitfield.baseindex = 0;
c6fb90c8
L		 9012 i.types[this_operand] = operand_type_or (i.types[this_operand],
9013 temp);
7d5e4556 9014 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 9015 i.op[this_operand].regs = r;
24eab124
AM		 9016 i.reg_operands++;
9017 }
af6bdddf
AM		 9018 else if (*op_string == REGISTER_PREFIX)
9019 {
9020 as_bad (_("bad register name `%s'"), op_string);
9021 return 0;
9022 }
24eab124 9023 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 9024 {
24eab124 9025 ++op_string;
40fb9820 9026 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 9027 {
d0b47220 9028 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 9029 return 0;
9030 }
9031 if (!i386_immediate (op_string))
9032 return 0;
9033 }
43234a1e
L		 9034 else if (RC_SAE_immediate (operand_string))
9035 {
9036 /* If it is a RC or SAE immediate, do nothing. */
9037 ;
9038 }
24eab124
AM		 9039 else if (is_digit_char (*op_string)
9040 || is_identifier_char (*op_string)
d02603dc 9041 || *op_string == '"'
e5cb08ac 9042 || *op_string == '(')
24eab124 9043 {
47926f60 9044 /* This is a memory reference of some sort. */
af6bdddf 9045 char *base_string;
252b5132 9046
47926f60 9047 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 9048 char *displacement_string_start;
9049 char *displacement_string_end;
43234a1e 9050 char *vop_start;
252b5132 9051
24eab124 9052 do_memory_reference:
8325cc63
JB		 9053 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9054 return 0;
24eab124 9055 if ((i.mem_operands == 1
40fb9820 9056 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 9057 || i.mem_operands == 2)
9058 {
9059 as_bad (_("too many memory references for `%s'"),
9060 current_templates->start->name);
9061 return 0;
9062 }
252b5132 9063
24eab124
AM		 9064 /* Check for base index form. We detect the base index form by
9065 looking for an ')' at the end of the operand, searching
9066 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9067 after the '('. */
af6bdddf 9068 base_string = op_string + strlen (op_string);
c3332e24 9069
43234a1e
L		 9070 /* Handle vector operations. */
9071 vop_start = strchr (op_string, '{');
9072 if (vop_start && vop_start < base_string)
9073 {
9074 if (check_VecOperations (vop_start, base_string) == NULL)
9075 return 0;
9076 base_string = vop_start;
9077 }
9078
af6bdddf
AM		 9079 --base_string;
9080 if (is_space_char (*base_string))
9081 --base_string;
252b5132 9082
47926f60 9083 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 9084 displacement_string_start = op_string;
9085 displacement_string_end = base_string + 1;
252b5132 9086
24eab124
AM		 9087 if (*base_string == ')')
9088 {
af6bdddf 9089 char *temp_string;
24eab124
AM		 9090 unsigned int parens_balanced = 1;
9091 /* We've already checked that the number of left & right ()'s are
47926f60 9092 equal, so this loop will not be infinite. */
24eab124
AM		 9093 do
9094 {
9095 base_string--;
9096 if (*base_string == ')')
9097 parens_balanced++;
9098 if (*base_string == '(')
9099 parens_balanced--;
9100 }
9101 while (parens_balanced);
c3332e24 9102
af6bdddf 9103 temp_string = base_string;
c3332e24 9104
24eab124 9105 /* Skip past '(' and whitespace. */
252b5132
RH		 9106 ++base_string;
9107 if (is_space_char (*base_string))
24eab124 9108 ++base_string;
252b5132 9109
af6bdddf 9110 if (*base_string == ','
4eed87de
AM		 9111 || ((i.base_reg = parse_register (base_string, &end_op))
9112 != NULL))
252b5132 9113 {
af6bdddf 9114 displacement_string_end = temp_string;
252b5132 9115
40fb9820 9116 i.types[this_operand].bitfield.baseindex = 1;
252b5132 9117
af6bdddf 9118 if (i.base_reg)
24eab124 9119 {
24eab124
AM		 9120 base_string = end_op;
9121 if (is_space_char (*base_string))
9122 ++base_string;
af6bdddf
AM		 9123 }
9124
9125 /* There may be an index reg or scale factor here. */
9126 if (*base_string == ',')
9127 {
9128 ++base_string;
9129 if (is_space_char (*base_string))
9130 ++base_string;
9131
4eed87de
AM		 9132 if ((i.index_reg = parse_register (base_string, &end_op))
9133 != NULL)
24eab124 9134 {
af6bdddf 9135 base_string = end_op;
24eab124
AM		 9136 if (is_space_char (*base_string))
9137 ++base_string;
af6bdddf
AM		 9138 if (*base_string == ',')
9139 {
9140 ++base_string;
9141 if (is_space_char (*base_string))
9142 ++base_string;
9143 }
e5cb08ac 9144 else if (*base_string != ')')
af6bdddf 9145 {
4eed87de
AM		 9146 as_bad (_("expecting `,' or `)' "
9147 "after index register in `%s'"),
af6bdddf
AM		 9148 operand_string);
9149 return 0;
9150 }
24eab124 9151 }
af6bdddf 9152 else if (*base_string == REGISTER_PREFIX)
24eab124 9153 {
f76bf5e0
L		 9154 end_op = strchr (base_string, ',');
9155 if (end_op)
9156 *end_op = '\0';
af6bdddf 9157 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 9158 return 0;
9159 }
252b5132 9160
47926f60 9161 /* Check for scale factor. */
551c1ca1 9162 if (*base_string != ')')
af6bdddf 9163 {
551c1ca1
AM		 9164 char *end_scale = i386_scale (base_string);
9165
9166 if (!end_scale)
af6bdddf 9167 return 0;
24eab124 9168
551c1ca1 9169 base_string = end_scale;
af6bdddf
AM		 9170 if (is_space_char (*base_string))
9171 ++base_string;
9172 if (*base_string != ')')
9173 {
4eed87de
AM		 9174 as_bad (_("expecting `)' "
9175 "after scale factor in `%s'"),
af6bdddf
AM		 9176 operand_string);
9177 return 0;
9178 }
9179 }
9180 else if (!i.index_reg)
24eab124 9181 {
4eed87de
AM		 9182 as_bad (_("expecting index register or scale factor "
9183 "after `,'; got '%c'"),
af6bdddf 9184 *base_string);
24eab124
AM		 9185 return 0;
9186 }
9187 }
af6bdddf 9188 else if (*base_string != ')')
24eab124 9189 {
4eed87de
AM		 9190 as_bad (_("expecting `,' or `)' "
9191 "after base register in `%s'"),
af6bdddf 9192 operand_string);
24eab124
AM		 9193 return 0;
9194 }
c3332e24 9195 }
af6bdddf 9196 else if (*base_string == REGISTER_PREFIX)
c3332e24 9197 {
f76bf5e0
L		 9198 end_op = strchr (base_string, ',');
9199 if (end_op)
9200 *end_op = '\0';
af6bdddf 9201 as_bad (_("bad register name `%s'"), base_string);
24eab124 9202 return 0;
c3332e24 9203 }
24eab124
AM		 9204 }
9205
9206 /* If there's an expression beginning the operand, parse it,
9207 assuming displacement_string_start and
9208 displacement_string_end are meaningful. */
9209 if (displacement_string_start != displacement_string_end)
9210 {
9211 if (!i386_displacement (displacement_string_start,
9212 displacement_string_end))
9213 return 0;
9214 }
9215
9216 /* Special case for (%dx) while doing input/output op. */
9217 if (i.base_reg
0dfbf9d7
L		 9218 && operand_type_equal (&i.base_reg->reg_type,
9219 &reg16_inoutportreg)
24eab124
AM		 9220 && i.index_reg == 0
9221 && i.log2_scale_factor == 0
9222 && i.seg[i.mem_operands] == 0
40fb9820 9223 && !operand_type_check (i.types[this_operand], disp))
24eab124 9224 {
65da13b5 9225 i.types[this_operand] = inoutportreg;
24eab124
AM		 9226 return 1;
9227 }
9228
eecb386c
AM		 9229 if (i386_index_check (operand_string) == 0)
9230 return 0;
5c07affc 9231 i.types[this_operand].bitfield.mem = 1;
8325cc63
JB		 9232 if (i.mem_operands == 0)
9233 i.memop1_string = xstrdup (operand_string);
24eab124
AM		 9234 i.mem_operands++;
9235 }
9236 else
ce8a8b2f
AM		 9237 {
9238 /* It's not a memory operand; argh! */
24eab124
AM		 9239 as_bad (_("invalid char %s beginning operand %d `%s'"),
9240 output_invalid (*op_string),
9241 this_operand + 1,
9242 op_string);
9243 return 0;
9244 }
47926f60 9245 return 1; /* Normal return. */
252b5132
RH		 9246}
9247\f
fa94de6b
RM		 9248/* Calculate the maximum variable size (i.e., excluding fr_fix)
9249 that an rs_machine_dependent frag may reach. */
9250
9251unsigned int
9252i386_frag_max_var (fragS *frag)
9253{
9254 /* The only relaxable frags are for jumps.
9255 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9256 gas_assert (frag->fr_type == rs_machine_dependent);
9257 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9258}
9259
b084df0b
L		 9260#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9261static int
8dcea932 9262elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
b084df0b
L		 9263{
9264 /* STT_GNU_IFUNC symbol must go through PLT. */
9265 if ((symbol_get_bfdsym (fr_symbol)->flags
9266 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9267 return 0;
9268
9269 if (!S_IS_EXTERNAL (fr_symbol))
9270 /* Symbol may be weak or local. */
9271 return !S_IS_WEAK (fr_symbol);
9272
8dcea932
L		 9273 /* Global symbols with non-default visibility can't be preempted. */
9274 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9275 return 1;
9276
9277 if (fr_var != NO_RELOC)
9278 switch ((enum bfd_reloc_code_real) fr_var)
9279 {
9280 case BFD_RELOC_386_PLT32:
9281 case BFD_RELOC_X86_64_PLT32:
33eaf5de 9282 /* Symbol with PLT relocation may be preempted. */
8dcea932
L		 9283 return 0;
9284 default:
9285 abort ();
9286 }
9287
b084df0b
L		 9288 /* Global symbols with default visibility in a shared library may be
9289 preempted by another definition. */
8dcea932 9290 return !shared;
b084df0b
L		 9291}
9292#endif
9293
ee7fcc42
AM		 9294/* md_estimate_size_before_relax()
9295
9296 Called just before relax() for rs_machine_dependent frags. The x86
9297 assembler uses these frags to handle variable size jump
9298 instructions.
9299
9300 Any symbol that is now undefined will not become defined.
9301 Return the correct fr_subtype in the frag.
9302 Return the initial "guess for variable size of frag" to caller.
9303 The guess is actually the growth beyond the fixed part. Whatever
9304 we do to grow the fixed or variable part contributes to our
9305 returned value. */
9306
252b5132 9307int
7016a5d5 9308md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 9309{
252b5132 9310 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 9311 check for un-relaxable symbols. On an ELF system, we can't relax
9312 an externally visible symbol, because it may be overridden by a
9313 shared library. */
9314 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 9315#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9316 || (IS_ELF
8dcea932
L		 9317 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9318 fragP->fr_var))
fbeb56a4
DK		 9319#endif
9320#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 9321 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 9322 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 9323#endif
9324 )
252b5132 9325 {
b98ef147
AM		 9326 /* Symbol is undefined in this segment, or we need to keep a
9327 reloc so that weak symbols can be overridden. */
9328 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 9329 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 9330 unsigned char *opcode;
9331 int old_fr_fix;
f6af82bd 9332
ee7fcc42 9333 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 9334 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 9335 else if (size == 2)
f6af82bd
AM		 9336 reloc_type = BFD_RELOC_16_PCREL;
9337 else
9338 reloc_type = BFD_RELOC_32_PCREL;
252b5132 9339
ee7fcc42
AM		 9340 old_fr_fix = fragP->fr_fix;
9341 opcode = (unsigned char *) fragP->fr_opcode;
9342
fddf5b5b 9343 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 9344 {
fddf5b5b
AM		 9345 case UNCOND_JUMP:
9346 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 9347 opcode[0] = 0xe9;
252b5132 9348 fragP->fr_fix += size;
062cd5e7
AS		 9349 fix_new (fragP, old_fr_fix, size,
9350 fragP->fr_symbol,
9351 fragP->fr_offset, 1,
9352 reloc_type);
252b5132
RH		 9353 break;
9354
fddf5b5b 9355 case COND_JUMP86:
412167cb
AM		 9356 if (size == 2
9357 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 9358 {
9359 /* Negate the condition, and branch past an
9360 unconditional jump. */
9361 opcode[0] ^= 1;
9362 opcode[1] = 3;
9363 /* Insert an unconditional jump. */
9364 opcode[2] = 0xe9;
9365 /* We added two extra opcode bytes, and have a two byte
9366 offset. */
9367 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 9368 fix_new (fragP, old_fr_fix + 2, 2,
9369 fragP->fr_symbol,
9370 fragP->fr_offset, 1,
9371 reloc_type);
fddf5b5b
AM		 9372 break;
9373 }
9374 /* Fall through. */
9375
9376 case COND_JUMP:
412167cb
AM		 9377 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9378 {
3e02c1cc
AM		 9379 fixS *fixP;
9380
412167cb 9381 fragP->fr_fix += 1;
3e02c1cc
AM		 9382 fixP = fix_new (fragP, old_fr_fix, 1,
9383 fragP->fr_symbol,
9384 fragP->fr_offset, 1,
9385 BFD_RELOC_8_PCREL);
9386 fixP->fx_signed = 1;
412167cb
AM		 9387 break;
9388 }
93c2a809 9389
24eab124 9390 /* This changes the byte-displacement jump 0x7N
fddf5b5b 9391 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 9392 opcode[1] = opcode[0] + 0x10;
f6af82bd 9393 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 9394 /* We've added an opcode byte. */
9395 fragP->fr_fix += 1 + size;
062cd5e7
AS		 9396 fix_new (fragP, old_fr_fix + 1, size,
9397 fragP->fr_symbol,
9398 fragP->fr_offset, 1,
9399 reloc_type);
252b5132 9400 break;
fddf5b5b
AM		 9401
9402 default:
9403 BAD_CASE (fragP->fr_subtype);
9404 break;
252b5132
RH		 9405 }
9406 frag_wane (fragP);
ee7fcc42 9407 return fragP->fr_fix - old_fr_fix;
252b5132 9408 }
93c2a809 9409
93c2a809
AM		 9410 /* Guess size depending on current relax state. Initially the relax
9411 state will correspond to a short jump and we return 1, because
9412 the variable part of the frag (the branch offset) is one byte
9413 long. However, we can relax a section more than once and in that
9414 case we must either set fr_subtype back to the unrelaxed state,
9415 or return the value for the appropriate branch. */
9416 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 9417}
9418
47926f60
KH		 9419/* Called after relax() is finished.
9420
9421 In: Address of frag.
9422 fr_type == rs_machine_dependent.
9423 fr_subtype is what the address relaxed to.
9424
9425 Out: Any fixSs and constants are set up.
9426 Caller will turn frag into a ".space 0". */
9427
252b5132 9428void
7016a5d5
TG		 9429md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9430 fragS *fragP)
252b5132 9431{
29b0f896 9432 unsigned char *opcode;
252b5132 9433 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9434 offsetT target_address;
9435 offsetT opcode_address;
252b5132 9436 unsigned int extension = 0;
847f7ad4 9437 offsetT displacement_from_opcode_start;
252b5132
RH		 9438
9439 opcode = (unsigned char *) fragP->fr_opcode;
9440
47926f60 9441 /* Address we want to reach in file space. */
252b5132 9442 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9443
47926f60 9444 /* Address opcode resides at in file space. */
252b5132
RH		 9445 opcode_address = fragP->fr_address + fragP->fr_fix;
9446
47926f60 9447 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9448 displacement_from_opcode_start = target_address - opcode_address;
9449
fddf5b5b 9450 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9451 {
47926f60
KH		 9452 /* Don't have to change opcode. */
9453 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9454 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9455 }
9456 else
9457 {
9458 if (no_cond_jump_promotion
9459 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9460 as_warn_where (fragP->fr_file, fragP->fr_line,
9461 _("long jump required"));
252b5132 9462
fddf5b5b
AM		 9463 switch (fragP->fr_subtype)
9464 {
9465 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9466 extension = 4; /* 1 opcode + 4 displacement */
9467 opcode[0] = 0xe9;
9468 where_to_put_displacement = &opcode[1];
9469 break;
252b5132 9470
fddf5b5b
AM		 9471 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9472 extension = 2; /* 1 opcode + 2 displacement */
9473 opcode[0] = 0xe9;
9474 where_to_put_displacement = &opcode[1];
9475 break;
252b5132 9476
fddf5b5b
AM		 9477 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9478 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9479 extension = 5; /* 2 opcode + 4 displacement */
9480 opcode[1] = opcode[0] + 0x10;
9481 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9482 where_to_put_displacement = &opcode[2];
9483 break;
252b5132 9484
fddf5b5b
AM		 9485 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9486 extension = 3; /* 2 opcode + 2 displacement */
9487 opcode[1] = opcode[0] + 0x10;
9488 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9489 where_to_put_displacement = &opcode[2];
9490 break;
252b5132 9491
fddf5b5b
AM		 9492 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9493 extension = 4;
9494 opcode[0] ^= 1;
9495 opcode[1] = 3;
9496 opcode[2] = 0xe9;
9497 where_to_put_displacement = &opcode[3];
9498 break;
9499
9500 default:
9501 BAD_CASE (fragP->fr_subtype);
9502 break;
9503 }
252b5132 9504 }
fddf5b5b 9505
7b81dfbb
AJ		 9506 /* If size if less then four we are sure that the operand fits,
9507 but if it's 4, then it could be that the displacement is larger
9508 then -/+ 2GB. */
9509 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9510 && object_64bit
9511 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9512 + ((addressT) 1 << 31))
9513 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9514 {
9515 as_bad_where (fragP->fr_file, fragP->fr_line,
9516 _("jump target out of range"));
9517 /* Make us emit 0. */
9518 displacement_from_opcode_start = extension;
9519 }
47926f60 9520 /* Now put displacement after opcode. */
252b5132
RH		 9521 md_number_to_chars ((char *) where_to_put_displacement,
9522 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9523 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9524 fragP->fr_fix += extension;
9525}
9526\f
7016a5d5 9527/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9528 by our caller that we have all the info we need to fix it up.
9529
7016a5d5
TG		 9530 Parameter valP is the pointer to the value of the bits.
9531
252b5132
RH		 9532 On the 386, immediates, displacements, and data pointers are all in
9533 the same (little-endian) format, so we don't need to care about which
9534 we are handling. */
9535
94f592af 9536void
7016a5d5 9537md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9538{
94f592af 9539 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9540 valueT value = *valP;
252b5132 9541
f86103b7 9542#if !defined (TE_Mach)
93382f6d
AM		 9543 if (fixP->fx_pcrel)
9544 {
9545 switch (fixP->fx_r_type)
9546 {
5865bb77
ILT		 9547 default:
9548 break;
9549
d6ab8113
JB		 9550 case BFD_RELOC_64:
9551 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9552 break;
93382f6d 9553 case BFD_RELOC_32:
ae8887b5 9554 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9555 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9556 break;
9557 case BFD_RELOC_16:
9558 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9559 break;
9560 case BFD_RELOC_8:
9561 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9562 break;
9563 }
9564 }
252b5132 9565
a161fe53 9566 if (fixP->fx_addsy != NULL
31312f95 9567 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9568 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9569 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 9570 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 9571 && !use_rela_relocations)
252b5132 9572 {
31312f95
AM		 9573 /* This is a hack. There should be a better way to handle this.
9574 This covers for the fact that bfd_install_relocation will
9575 subtract the current location (for partial_inplace, PC relative
9576 relocations); see more below. */
252b5132 9577#ifndef OBJ_AOUT
718ddfc0 9578 if (IS_ELF
252b5132
RH		 9579#ifdef TE_PE
9580 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9581#endif
9582 )
9583 value += fixP->fx_where + fixP->fx_frag->fr_address;
9584#endif
9585#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9586 if (IS_ELF)
252b5132 9587 {
6539b54b 9588 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9589
6539b54b 9590 if ((sym_seg == seg
2f66722d 9591 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9592 && sym_seg != absolute_section))
af65af87 9593 && !generic_force_reloc (fixP))
2f66722d
AM		 9594 {
9595 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9596 bfd_install_relocation subtracts them out again. I think
9597 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9598 it. FIXME. */
9599 value += fixP->fx_where + fixP->fx_frag->fr_address;
9600 }
252b5132
RH		 9601 }
9602#endif
9603#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9604 /* For some reason, the PE format does not store a
9605 section address offset for a PC relative symbol. */
9606 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9607 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9608 value += md_pcrel_from (fixP);
9609#endif
9610 }
fbeb56a4 9611#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9612 if (fixP->fx_addsy != NULL
9613 && S_IS_WEAK (fixP->fx_addsy)
9614 /* PR 16858: Do not modify weak function references. */
9615 && ! fixP->fx_pcrel)
fbeb56a4 9616 {
296a8689
NC		 9617#if !defined (TE_PEP)
9618 /* For x86 PE weak function symbols are neither PC-relative
9619 nor do they set S_IS_FUNCTION. So the only reliable way
9620 to detect them is to check the flags of their containing
9621 section. */
9622 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9623 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9624 ;
9625 else
9626#endif
fbeb56a4
DK		 9627 value -= S_GET_VALUE (fixP->fx_addsy);
9628 }
9629#endif
252b5132
RH		 9630
9631 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9632 and we must not disappoint it. */
252b5132 9633#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9634 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9635 switch (fixP->fx_r_type)
9636 {
9637 case BFD_RELOC_386_PLT32:
3e73aa7c 9638 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 9639 /* Make the jump instruction point to the address of the operand. At
9640 runtime we merely add the offset to the actual PLT entry. */
9641 value = -4;
9642 break;
31312f95 9643
13ae64f3
JJ		 9644 case BFD_RELOC_386_TLS_GD:
9645 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9646 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9647 case BFD_RELOC_386_TLS_IE:
9648 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9649 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9650 case BFD_RELOC_X86_64_TLSGD:
9651 case BFD_RELOC_X86_64_TLSLD:
9652 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9653 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9654 value = 0; /* Fully resolved at runtime. No addend. */
9655 /* Fallthrough */
9656 case BFD_RELOC_386_TLS_LE:
9657 case BFD_RELOC_386_TLS_LDO_32:
9658 case BFD_RELOC_386_TLS_LE_32:
9659 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9660 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9661 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9662 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9663 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9664 break;
9665
67a4f2b7
AO		 9666 case BFD_RELOC_386_TLS_DESC_CALL:
9667 case BFD_RELOC_X86_64_TLSDESC_CALL:
9668 value = 0; /* Fully resolved at runtime. No addend. */
9669 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9670 fixP->fx_done = 0;
9671 return;
9672
47926f60
KH		 9673 case BFD_RELOC_VTABLE_INHERIT:
9674 case BFD_RELOC_VTABLE_ENTRY:
9675 fixP->fx_done = 0;
94f592af 9676 return;
47926f60
KH		 9677
9678 default:
9679 break;
9680 }
9681#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9682 *valP = value;
f86103b7 9683#endif /* !defined (TE_Mach) */
3e73aa7c 9684
3e73aa7c 9685 /* Are we finished with this relocation now? */
c6682705 9686 if (fixP->fx_addsy == NULL)
3e73aa7c 9687 fixP->fx_done = 1;
fbeb56a4
DK		 9688#if defined (OBJ_COFF) && defined (TE_PE)
9689 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9690 {
9691 fixP->fx_done = 0;
9692 /* Remember value for tc_gen_reloc. */
9693 fixP->fx_addnumber = value;
9694 /* Clear out the frag for now. */
9695 value = 0;
9696 }
9697#endif
3e73aa7c
JH		 9698 else if (use_rela_relocations)
9699 {
9700 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9701 /* Remember value for tc_gen_reloc. */
9702 fixP->fx_addnumber = value;
3e73aa7c
JH		 9703 value = 0;
9704 }
f86103b7 9705
94f592af 9706 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9707}
252b5132 9708\f
6d4af3c2 9709const char *
499ac353 9710md_atof (int type, char *litP, int *sizeP)
252b5132 9711{
499ac353
NC		 9712 /* This outputs the LITTLENUMs in REVERSE order;
9713 in accord with the bigendian 386. */
9714 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9715}
9716\f
2d545b82 9717static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9718
252b5132 9719static char *
e3bb37b5 9720output_invalid (int c)
252b5132 9721{
3882b010 9722 if (ISPRINT (c))
f9f21a03
L		 9723 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9724 "'%c'", c);
252b5132 9725 else
f9f21a03 9726 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9727 "(0x%x)", (unsigned char) c);
252b5132
RH		 9728 return output_invalid_buf;
9729}
9730
af6bdddf 9731/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9732
9733static const reg_entry *
4d1bb795 9734parse_real_register (char *reg_string, char **end_op)
252b5132 9735{
af6bdddf
AM		 9736 char *s = reg_string;
9737 char *p;
252b5132
RH		 9738 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9739 const reg_entry *r;
9740
9741 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9742 if (*s == REGISTER_PREFIX)
9743 ++s;
9744
9745 if (is_space_char (*s))
9746 ++s;
9747
9748 p = reg_name_given;
af6bdddf 9749 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9750 {
9751 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9752 return (const reg_entry *) NULL;
9753 s++;
252b5132
RH		 9754 }
9755
6588847e
DN		 9756 /* For naked regs, make sure that we are not dealing with an identifier.
9757 This prevents confusing an identifier like `eax_var' with register
9758 `eax'. */
9759 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9760 return (const reg_entry *) NULL;
9761
af6bdddf 9762 *end_op = s;
252b5132
RH		 9763
9764 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9765
5f47d35b 9766 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9767 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9768 {
5f47d35b
AM		 9769 if (is_space_char (*s))
9770 ++s;
9771 if (*s == '(')
9772 {
af6bdddf 9773 ++s;
5f47d35b
AM		 9774 if (is_space_char (*s))
9775 ++s;
9776 if (*s >= '0' && *s <= '7')
9777 {
db557034 9778 int fpr = *s - '0';
af6bdddf 9779 ++s;
5f47d35b
AM		 9780 if (is_space_char (*s))
9781 ++s;
9782 if (*s == ')')
9783 {
9784 *end_op = s + 1;
1e9cc1c2 9785 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9786 know (r);
9787 return r + fpr;
5f47d35b 9788 }
5f47d35b 9789 }
47926f60 9790 /* We have "%st(" then garbage. */
5f47d35b
AM		 9791 return (const reg_entry *) NULL;
9792 }
9793 }
9794
a60de03c
JB		 9795 if (r == NULL || allow_pseudo_reg)
9796 return r;
9797
0dfbf9d7 9798 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9799 return (const reg_entry *) NULL;
9800
192dc9c6
JB		 9801 if ((r->reg_type.bitfield.reg32
9802 || r->reg_type.bitfield.sreg3
9803 || r->reg_type.bitfield.control
9804 || r->reg_type.bitfield.debug
9805 || r->reg_type.bitfield.test)
9806 && !cpu_arch_flags.bitfield.cpui386)
9807 return (const reg_entry *) NULL;
9808
309d3373
JB		 9809 if (r->reg_type.bitfield.floatreg
9810 && !cpu_arch_flags.bitfield.cpu8087
9811 && !cpu_arch_flags.bitfield.cpu287
9812 && !cpu_arch_flags.bitfield.cpu387)
9813 return (const reg_entry *) NULL;
9814
1848e567 9815 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
192dc9c6
JB		 9816 return (const reg_entry *) NULL;
9817
1848e567 9818 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpuregxmm)
192dc9c6
JB		 9819 return (const reg_entry *) NULL;
9820
1848e567 9821 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuregymm)
40f12533
L		 9822 return (const reg_entry *) NULL;
9823
1848e567
L		 9824 if (r->reg_type.bitfield.regzmm && !cpu_arch_flags.bitfield.cpuregzmm)
9825 return (const reg_entry *) NULL;
9826
9827 if (r->reg_type.bitfield.regmask
9828 && !cpu_arch_flags.bitfield.cpuregmask)
43234a1e
L		 9829 return (const reg_entry *) NULL;
9830
db51cc60 9831 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9832 if (!allow_index_reg
db51cc60
L		 9833 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9834 return (const reg_entry *) NULL;
9835
43234a1e
L		 9836 /* Upper 16 vector register is only available with VREX in 64bit
9837 mode. */
9838 if ((r->reg_flags & RegVRex))
9839 {
86fa6981
L		 9840 if (i.vec_encoding == vex_encoding_default)
9841 i.vec_encoding = vex_encoding_evex;
9842
43234a1e 9843 if (!cpu_arch_flags.bitfield.cpuvrex
86fa6981 9844 || i.vec_encoding != vex_encoding_evex
43234a1e
L		 9845 || flag_code != CODE_64BIT)
9846 return (const reg_entry *) NULL;
43234a1e
L		 9847 }
9848
a60de03c
JB		 9849 if (((r->reg_flags & (RegRex64 | RegRex))
9850 || r->reg_type.bitfield.reg64)
40fb9820 9851 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9852 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9853 && flag_code != CODE_64BIT)
20f0a1fc 9854 return (const reg_entry *) NULL;
1ae00879 9855
b7240065
JB		 9856 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9857 return (const reg_entry *) NULL;
9858
252b5132
RH		 9859 return r;
9860}
4d1bb795
JB		 9861
9862/* REG_STRING starts *before* REGISTER_PREFIX. */
9863
9864static const reg_entry *
9865parse_register (char *reg_string, char **end_op)
9866{
9867 const reg_entry *r;
9868
9869 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9870 r = parse_real_register (reg_string, end_op);
9871 else
9872 r = NULL;
9873 if (!r)
9874 {
9875 char *save = input_line_pointer;
9876 char c;
9877 symbolS *symbolP;
9878
9879 input_line_pointer = reg_string;
d02603dc 9880 c = get_symbol_name (&reg_string);
4d1bb795
JB		 9881 symbolP = symbol_find (reg_string);
9882 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9883 {
9884 const expressionS *e = symbol_get_value_expression (symbolP);
9885
0398aac5 9886 know (e->X_op == O_register);
4eed87de 9887 know (e->X_add_number >= 0
c3fe08fa 9888 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 9889 r = i386_regtab + e->X_add_number;
d3bb6b49 9890 if ((r->reg_flags & RegVRex))
86fa6981 9891 i.vec_encoding = vex_encoding_evex;
4d1bb795
JB		 9892 *end_op = input_line_pointer;
9893 }
9894 *input_line_pointer = c;
9895 input_line_pointer = save;
9896 }
9897 return r;
9898}
9899
9900int
9901i386_parse_name (char *name, expressionS *e, char *nextcharP)
9902{
9903 const reg_entry *r;
9904 char *end = input_line_pointer;
9905
9906 *end = *nextcharP;
9907 r = parse_register (name, &input_line_pointer);
9908 if (r && end <= input_line_pointer)
9909 {
9910 *nextcharP = *input_line_pointer;
9911 *input_line_pointer = 0;
9912 e->X_op = O_register;
9913 e->X_add_number = r - i386_regtab;
9914 return 1;
9915 }
9916 input_line_pointer = end;
9917 *end = 0;
ee86248c 9918 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9919}
9920
9921void
9922md_operand (expressionS *e)
9923{
ee86248c
JB		 9924 char *end;
9925 const reg_entry *r;
4d1bb795 9926
ee86248c
JB		 9927 switch (*input_line_pointer)
9928 {
9929 case REGISTER_PREFIX:
9930 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9931 if (r)
9932 {
9933 e->X_op = O_register;
9934 e->X_add_number = r - i386_regtab;
9935 input_line_pointer = end;
9936 }
ee86248c
JB		 9937 break;
9938
9939 case '[':
9c2799c2 9940 gas_assert (intel_syntax);
ee86248c
JB		 9941 end = input_line_pointer++;
9942 expression (e);
9943 if (*input_line_pointer == ']')
9944 {
9945 ++input_line_pointer;
9946 e->X_op_symbol = make_expr_symbol (e);
9947 e->X_add_symbol = NULL;
9948 e->X_add_number = 0;
9949 e->X_op = O_index;
9950 }
9951 else
9952 {
9953 e->X_op = O_absent;
9954 input_line_pointer = end;
9955 }
9956 break;
4d1bb795
JB		 9957 }
9958}
9959
252b5132 9960\f
4cc782b5 9961#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9962const char *md_shortopts = "kVQ:sqn";
252b5132 9963#else
12b55ccc 9964const char *md_shortopts = "qn";
252b5132 9965#endif
6e0b89ee 9966
3e73aa7c 9967#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9968#define OPTION_64 (OPTION_MD_BASE + 1)
9969#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9970#define OPTION_MARCH (OPTION_MD_BASE + 3)
9971#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9972#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9973#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9974#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9975#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9976#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9977#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9978#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9979#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9980#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9981#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9982#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9983#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9984#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 9985#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
d1982f93 9986#define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 9987#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
8dcea932 9988#define OPTION_MSHARED (OPTION_MD_BASE + 21)
5db04b09
L		 9989#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9990#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
e4e00185 9991#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
0cb4071e 9992#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
b3b91714 9993
99ad8390
NC		 9994struct option md_longopts[] =
9995{
3e73aa7c 9996 {"32", no_argument, NULL, OPTION_32},
321098a5 9997#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9998 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9999 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 10000#endif
10001#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 10002 {"x32", no_argument, NULL, OPTION_X32},
8dcea932 10003 {"mshared", no_argument, NULL, OPTION_MSHARED},
6e0b89ee 10004#endif
b3b91714 10005 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 10006 {"march", required_argument, NULL, OPTION_MARCH},
10007 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 10008 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
10009 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
10010 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
10011 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
10012 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 10013 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 10014 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 10015 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 10016 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 10017 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 10018 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
10019 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 10020# if defined (TE_PE) || defined (TE_PEP)
10021 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
10022#endif
d1982f93 10023 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
e4e00185 10024 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
0cb4071e 10025 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
d3d3c6db 10026 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
5db04b09
L		 10027 {"mamd64", no_argument, NULL, OPTION_MAMD64},
10028 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
252b5132
RH		 10029 {NULL, no_argument, NULL, 0}
10030};
10031size_t md_longopts_size = sizeof (md_longopts);
10032
10033int
17b9d67d 10034md_parse_option (int c, const char *arg)
252b5132 10035{
91d6fa6a 10036 unsigned int j;
293f5f65 10037 char *arch, *next, *saved;
9103f4f4 10038
252b5132
RH		 10039 switch (c)
10040 {
12b55ccc
L		 10041 case 'n':
10042 optimize_align_code = 0;
10043 break;
10044
a38cf1db
AM		 10045 case 'q':
10046 quiet_warnings = 1;
252b5132
RH		 10047 break;
10048
10049#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 10050 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10051 should be emitted or not. FIXME: Not implemented. */
10052 case 'Q':
252b5132
RH		 10053 break;
10054
10055 /* -V: SVR4 argument to print version ID. */
10056 case 'V':
10057 print_version_id ();
10058 break;
10059
a38cf1db
AM		 10060 /* -k: Ignore for FreeBSD compatibility. */
10061 case 'k':
252b5132 10062 break;
4cc782b5
ILT		 10063
10064 case 's':
10065 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 10066 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 10067 break;
8dcea932
L		 10068
10069 case OPTION_MSHARED:
10070 shared = 1;
10071 break;
99ad8390 10072#endif
321098a5 10073#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 10074 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 10075 case OPTION_64:
10076 {
10077 const char **list, **l;
10078
3e73aa7c
JH		 10079 list = bfd_target_list ();
10080 for (l = list; *l != NULL; l++)
8620418b 10081 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 10082 || strcmp (*l, "coff-x86-64") == 0
10083 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 10084 || strcmp (*l, "pei-x86-64") == 0
10085 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 10086 {
10087 default_arch = "x86_64";
10088 break;
10089 }
3e73aa7c 10090 if (*l == NULL)
2b5d6a91 10091 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 10092 free (list);
10093 }
10094 break;
10095#endif
252b5132 10096
351f65ca 10097#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 10098 case OPTION_X32:
351f65ca
L		 10099 if (IS_ELF)
10100 {
10101 const char **list, **l;
10102
10103 list = bfd_target_list ();
10104 for (l = list; *l != NULL; l++)
10105 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10106 {
10107 default_arch = "x86_64:32";
10108 break;
10109 }
10110 if (*l == NULL)
2b5d6a91 10111 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 10112 free (list);
10113 }
10114 else
10115 as_fatal (_("32bit x86_64 is only supported for ELF"));
10116 break;
10117#endif
10118
6e0b89ee
AM		 10119 case OPTION_32:
10120 default_arch = "i386";
10121 break;
10122
b3b91714
AM		 10123 case OPTION_DIVIDE:
10124#ifdef SVR4_COMMENT_CHARS
10125 {
10126 char *n, *t;
10127 const char *s;
10128
add39d23 10129 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
b3b91714
AM		 10130 t = n;
10131 for (s = i386_comment_chars; *s != '\0'; s++)
10132 if (*s != '/')
10133 *t++ = *s;
10134 *t = '\0';
10135 i386_comment_chars = n;
10136 }
10137#endif
10138 break;
10139
9103f4f4 10140 case OPTION_MARCH:
293f5f65
L		 10141 saved = xstrdup (arg);
10142 arch = saved;
10143 /* Allow -march=+nosse. */
10144 if (*arch == '+')
10145 arch++;
6305a203 10146 do
9103f4f4 10147 {
6305a203 10148 if (*arch == '.')
2b5d6a91 10149 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10150 next = strchr (arch, '+');
10151 if (next)
10152 *next++ = '\0';
91d6fa6a 10153 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10154 {
91d6fa6a 10155 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 10156 {
6305a203 10157 /* Processor. */
1ded5609
JB		 10158 if (! cpu_arch[j].flags.bitfield.cpui386)
10159 continue;
10160
91d6fa6a 10161 cpu_arch_name = cpu_arch[j].name;
6305a203 10162 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 10163 cpu_arch_flags = cpu_arch[j].flags;
10164 cpu_arch_isa = cpu_arch[j].type;
10165 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 10166 if (!cpu_arch_tune_set)
10167 {
10168 cpu_arch_tune = cpu_arch_isa;
10169 cpu_arch_tune_flags = cpu_arch_isa_flags;
10170 }
10171 break;
10172 }
91d6fa6a
NC		 10173 else if (*cpu_arch [j].name == '.'
10174 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203 10175 {
33eaf5de 10176 /* ISA extension. */
6305a203 10177 i386_cpu_flags flags;
309d3373 10178
293f5f65
L		 10179 flags = cpu_flags_or (cpu_arch_flags,
10180 cpu_arch[j].flags);
81486035 10181
5b64d091 10182 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 10183 {
10184 if (cpu_sub_arch_name)
10185 {
10186 char *name = cpu_sub_arch_name;
10187 cpu_sub_arch_name = concat (name,
91d6fa6a 10188 cpu_arch[j].name,
1bf57e9f 10189 (const char *) NULL);
6305a203
L		 10190 free (name);
10191 }
10192 else
91d6fa6a 10193 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 10194 cpu_arch_flags = flags;
a586129e 10195 cpu_arch_isa_flags = flags;
6305a203
L		 10196 }
10197 break;
ccc9c027 10198 }
9103f4f4 10199 }
6305a203 10200
293f5f65
L		 10201 if (j >= ARRAY_SIZE (cpu_arch))
10202 {
33eaf5de 10203 /* Disable an ISA extension. */
293f5f65
L		 10204 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10205 if (strcmp (arch, cpu_noarch [j].name) == 0)
10206 {
10207 i386_cpu_flags flags;
10208
10209 flags = cpu_flags_and_not (cpu_arch_flags,
10210 cpu_noarch[j].flags);
10211 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10212 {
10213 if (cpu_sub_arch_name)
10214 {
10215 char *name = cpu_sub_arch_name;
10216 cpu_sub_arch_name = concat (arch,
10217 (const char *) NULL);
10218 free (name);
10219 }
10220 else
10221 cpu_sub_arch_name = xstrdup (arch);
10222 cpu_arch_flags = flags;
10223 cpu_arch_isa_flags = flags;
10224 }
10225 break;
10226 }
10227
10228 if (j >= ARRAY_SIZE (cpu_noarch))
10229 j = ARRAY_SIZE (cpu_arch);
10230 }
10231
91d6fa6a 10232 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10233 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10234
10235 arch = next;
9103f4f4 10236 }
293f5f65
L		 10237 while (next != NULL);
10238 free (saved);
9103f4f4
L		 10239 break;
10240
10241 case OPTION_MTUNE:
10242 if (*arg == '.')
2b5d6a91 10243 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 10244 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10245 {
91d6fa6a 10246 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 10247 {
ccc9c027 10248 cpu_arch_tune_set = 1;
91d6fa6a
NC		 10249 cpu_arch_tune = cpu_arch [j].type;
10250 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 10251 break;
10252 }
10253 }
91d6fa6a 10254 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10255 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 10256 break;
10257
1efbbeb4
L		 10258 case OPTION_MMNEMONIC:
10259 if (strcasecmp (arg, "att") == 0)
10260 intel_mnemonic = 0;
10261 else if (strcasecmp (arg, "intel") == 0)
10262 intel_mnemonic = 1;
10263 else
2b5d6a91 10264 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 10265 break;
10266
10267 case OPTION_MSYNTAX:
10268 if (strcasecmp (arg, "att") == 0)
10269 intel_syntax = 0;
10270 else if (strcasecmp (arg, "intel") == 0)
10271 intel_syntax = 1;
10272 else
2b5d6a91 10273 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 10274 break;
10275
10276 case OPTION_MINDEX_REG:
10277 allow_index_reg = 1;
10278 break;
10279
10280 case OPTION_MNAKED_REG:
10281 allow_naked_reg = 1;
10282 break;
10283
10284 case OPTION_MOLD_GCC:
10285 old_gcc = 1;
1efbbeb4
L		 10286 break;
10287
c0f3af97
L		 10288 case OPTION_MSSE2AVX:
10289 sse2avx = 1;
10290 break;
10291
daf50ae7
L		 10292 case OPTION_MSSE_CHECK:
10293 if (strcasecmp (arg, "error") == 0)
7bab8ab5 10294 sse_check = check_error;
daf50ae7 10295 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 10296 sse_check = check_warning;
daf50ae7 10297 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 10298 sse_check = check_none;
daf50ae7 10299 else
2b5d6a91 10300 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 10301 break;
10302
7bab8ab5
JB		 10303 case OPTION_MOPERAND_CHECK:
10304 if (strcasecmp (arg, "error") == 0)
10305 operand_check = check_error;
10306 else if (strcasecmp (arg, "warning") == 0)
10307 operand_check = check_warning;
10308 else if (strcasecmp (arg, "none") == 0)
10309 operand_check = check_none;
10310 else
10311 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10312 break;
10313
539f890d
L		 10314 case OPTION_MAVXSCALAR:
10315 if (strcasecmp (arg, "128") == 0)
10316 avxscalar = vex128;
10317 else if (strcasecmp (arg, "256") == 0)
10318 avxscalar = vex256;
10319 else
2b5d6a91 10320 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 10321 break;
10322
7e8b059b
L		 10323 case OPTION_MADD_BND_PREFIX:
10324 add_bnd_prefix = 1;
10325 break;
10326
43234a1e
L		 10327 case OPTION_MEVEXLIG:
10328 if (strcmp (arg, "128") == 0)
10329 evexlig = evexl128;
10330 else if (strcmp (arg, "256") == 0)
10331 evexlig = evexl256;
10332 else if (strcmp (arg, "512") == 0)
10333 evexlig = evexl512;
10334 else
10335 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10336 break;
10337
d3d3c6db
IT		 10338 case OPTION_MEVEXRCIG:
10339 if (strcmp (arg, "rne") == 0)
10340 evexrcig = rne;
10341 else if (strcmp (arg, "rd") == 0)
10342 evexrcig = rd;
10343 else if (strcmp (arg, "ru") == 0)
10344 evexrcig = ru;
10345 else if (strcmp (arg, "rz") == 0)
10346 evexrcig = rz;
10347 else
10348 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10349 break;
10350
43234a1e
L		 10351 case OPTION_MEVEXWIG:
10352 if (strcmp (arg, "0") == 0)
10353 evexwig = evexw0;
10354 else if (strcmp (arg, "1") == 0)
10355 evexwig = evexw1;
10356 else
10357 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10358 break;
10359
167ad85b
TG		 10360# if defined (TE_PE) || defined (TE_PEP)
10361 case OPTION_MBIG_OBJ:
10362 use_big_obj = 1;
10363 break;
10364#endif
10365
d1982f93 10366 case OPTION_MOMIT_LOCK_PREFIX:
d022bddd
IT		 10367 if (strcasecmp (arg, "yes") == 0)
10368 omit_lock_prefix = 1;
10369 else if (strcasecmp (arg, "no") == 0)
10370 omit_lock_prefix = 0;
10371 else
10372 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10373 break;
10374
e4e00185
AS		 10375 case OPTION_MFENCE_AS_LOCK_ADD:
10376 if (strcasecmp (arg, "yes") == 0)
10377 avoid_fence = 1;
10378 else if (strcasecmp (arg, "no") == 0)
10379 avoid_fence = 0;
10380 else
10381 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10382 break;
10383
0cb4071e
L		 10384 case OPTION_MRELAX_RELOCATIONS:
10385 if (strcasecmp (arg, "yes") == 0)
10386 generate_relax_relocations = 1;
10387 else if (strcasecmp (arg, "no") == 0)
10388 generate_relax_relocations = 0;
10389 else
10390 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10391 break;
10392
5db04b09 10393 case OPTION_MAMD64:
e89c5eaa 10394 intel64 = 0;
5db04b09
L		 10395 break;
10396
10397 case OPTION_MINTEL64:
e89c5eaa 10398 intel64 = 1;
5db04b09
L		 10399 break;
10400
252b5132
RH		 10401 default:
10402 return 0;
10403 }
10404 return 1;
10405}
10406
8a2c8fef
L		 10407#define MESSAGE_TEMPLATE \
10408" "
10409
293f5f65
L		 10410static char *
10411output_message (FILE *stream, char *p, char *message, char *start,
10412 int *left_p, const char *name, int len)
10413{
10414 int size = sizeof (MESSAGE_TEMPLATE);
10415 int left = *left_p;
10416
10417 /* Reserve 2 spaces for ", " or ",\0" */
10418 left -= len + 2;
10419
10420 /* Check if there is any room. */
10421 if (left >= 0)
10422 {
10423 if (p != start)
10424 {
10425 *p++ = ',';
10426 *p++ = ' ';
10427 }
10428 p = mempcpy (p, name, len);
10429 }
10430 else
10431 {
10432 /* Output the current message now and start a new one. */
10433 *p++ = ',';
10434 *p = '\0';
10435 fprintf (stream, "%s\n", message);
10436 p = start;
10437 left = size - (start - message) - len - 2;
10438
10439 gas_assert (left >= 0);
10440
10441 p = mempcpy (p, name, len);
10442 }
10443
10444 *left_p = left;
10445 return p;
10446}
10447
8a2c8fef 10448static void
1ded5609 10449show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 10450{
10451 static char message[] = MESSAGE_TEMPLATE;
10452 char *start = message + 27;
10453 char *p;
10454 int size = sizeof (MESSAGE_TEMPLATE);
10455 int left;
10456 const char *name;
10457 int len;
10458 unsigned int j;
10459
10460 p = start;
10461 left = size - (start - message);
10462 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10463 {
10464 /* Should it be skipped? */
10465 if (cpu_arch [j].skip)
10466 continue;
10467
10468 name = cpu_arch [j].name;
10469 len = cpu_arch [j].len;
10470 if (*name == '.')
10471 {
10472 /* It is an extension. Skip if we aren't asked to show it. */
10473 if (ext)
10474 {
10475 name++;
10476 len--;
10477 }
10478 else
10479 continue;
10480 }
10481 else if (ext)
10482 {
10483 /* It is an processor. Skip if we show only extension. */
10484 continue;
10485 }
1ded5609
JB		 10486 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10487 {
10488 /* It is an impossible processor - skip. */
10489 continue;
10490 }
8a2c8fef 10491
293f5f65 10492 p = output_message (stream, p, message, start, &left, name, len);
8a2c8fef
L		 10493 }
10494
293f5f65
L		 10495 /* Display disabled extensions. */
10496 if (ext)
10497 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10498 {
10499 name = cpu_noarch [j].name;
10500 len = cpu_noarch [j].len;
10501 p = output_message (stream, p, message, start, &left, name,
10502 len);
10503 }
10504
8a2c8fef
L		 10505 *p = '\0';
10506 fprintf (stream, "%s\n", message);
10507}
10508
252b5132 10509void
8a2c8fef 10510md_show_usage (FILE *stream)
252b5132 10511{
4cc782b5
ILT		 10512#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10513 fprintf (stream, _("\
a38cf1db
AM		 10514 -Q ignored\n\
10515 -V print assembler version number\n\
b3b91714
AM		 10516 -k ignored\n"));
10517#endif
10518 fprintf (stream, _("\
12b55ccc 10519 -n Do not optimize code alignment\n\
b3b91714
AM		 10520 -q quieten some warnings\n"));
10521#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10522 fprintf (stream, _("\
a38cf1db 10523 -s ignored\n"));
b3b91714 10524#endif
321098a5
L		 10525#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10526 || defined (TE_PE) || defined (TE_PEP))
751d281c 10527 fprintf (stream, _("\
570561f7 10528 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10529#endif
b3b91714
AM		 10530#ifdef SVR4_COMMENT_CHARS
10531 fprintf (stream, _("\
10532 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10533#else
10534 fprintf (stream, _("\
b3b91714 10535 --divide ignored\n"));
4cc782b5 10536#endif
9103f4f4 10537 fprintf (stream, _("\
6305a203 10538 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10539 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10540 show_arch (stream, 0, 1);
8a2c8fef
L		 10541 fprintf (stream, _("\
10542 EXTENSION is combination of:\n"));
1ded5609 10543 show_arch (stream, 1, 0);
6305a203 10544 fprintf (stream, _("\
8a2c8fef 10545 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10546 show_arch (stream, 0, 0);
ba104c83 10547 fprintf (stream, _("\
c0f3af97
L		 10548 -msse2avx encode SSE instructions with VEX prefix\n"));
10549 fprintf (stream, _("\
daf50ae7
L		 10550 -msse-check=[none|error|warning]\n\
10551 check SSE instructions\n"));
10552 fprintf (stream, _("\
7bab8ab5
JB		 10553 -moperand-check=[none|error|warning]\n\
10554 check operand combinations for validity\n"));
10555 fprintf (stream, _("\
539f890d
L		 10556 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10557 length\n"));
10558 fprintf (stream, _("\
43234a1e
L		 10559 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10560 length\n"));
10561 fprintf (stream, _("\
10562 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10563 for EVEX.W bit ignored instructions\n"));
10564 fprintf (stream, _("\
d3d3c6db
IT		 10565 -mevexrcig=[rne|rd|ru|rz]\n\
10566 encode EVEX instructions with specific EVEX.RC value\n\
10567 for SAE-only ignored instructions\n"));
10568 fprintf (stream, _("\
ba104c83
L		 10569 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10570 fprintf (stream, _("\
10571 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10572 fprintf (stream, _("\
10573 -mindex-reg support pseudo index registers\n"));
10574 fprintf (stream, _("\
10575 -mnaked-reg don't require `%%' prefix for registers\n"));
10576 fprintf (stream, _("\
10577 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 10578 fprintf (stream, _("\
10579 -madd-bnd-prefix add BND prefix for all valid branches\n"));
8dcea932
L		 10580 fprintf (stream, _("\
10581 -mshared disable branch optimization for shared code\n"));
167ad85b
TG		 10582# if defined (TE_PE) || defined (TE_PEP)
10583 fprintf (stream, _("\
10584 -mbig-obj generate big object files\n"));
10585#endif
d022bddd
IT		 10586 fprintf (stream, _("\
10587 -momit-lock-prefix=[no|yes]\n\
10588 strip all lock prefixes\n"));
5db04b09 10589 fprintf (stream, _("\
e4e00185
AS		 10590 -mfence-as-lock-add=[no|yes]\n\
10591 encode lfence, mfence and sfence as\n\
10592 lock addl $0x0, (%%{re}sp)\n"));
10593 fprintf (stream, _("\
0cb4071e
L		 10594 -mrelax-relocations=[no|yes]\n\
10595 generate relax relocations\n"));
10596 fprintf (stream, _("\
5db04b09
L		 10597 -mamd64 accept only AMD64 ISA\n"));
10598 fprintf (stream, _("\
10599 -mintel64 accept only Intel64 ISA\n"));
252b5132
RH		 10600}
10601
3e73aa7c 10602#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 10603 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 10604 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 10605
10606/* Pick the target format to use. */
10607
47926f60 10608const char *
e3bb37b5 10609i386_target_format (void)
252b5132 10610{
351f65ca
L		 10611 if (!strncmp (default_arch, "x86_64", 6))
10612 {
10613 update_code_flag (CODE_64BIT, 1);
10614 if (default_arch[6] == '\0')
7f56bc95 10615 x86_elf_abi = X86_64_ABI;
351f65ca 10616 else
7f56bc95 10617 x86_elf_abi = X86_64_X32_ABI;
351f65ca 10618 }
3e73aa7c 10619 else if (!strcmp (default_arch, "i386"))
78f12dd3 10620 update_code_flag (CODE_32BIT, 1);
5197d474
L		 10621 else if (!strcmp (default_arch, "iamcu"))
10622 {
10623 update_code_flag (CODE_32BIT, 1);
10624 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10625 {
10626 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10627 cpu_arch_name = "iamcu";
10628 cpu_sub_arch_name = NULL;
10629 cpu_arch_flags = iamcu_flags;
10630 cpu_arch_isa = PROCESSOR_IAMCU;
10631 cpu_arch_isa_flags = iamcu_flags;
10632 if (!cpu_arch_tune_set)
10633 {
10634 cpu_arch_tune = cpu_arch_isa;
10635 cpu_arch_tune_flags = cpu_arch_isa_flags;
10636 }
10637 }
8d471ec1 10638 else if (cpu_arch_isa != PROCESSOR_IAMCU)
5197d474
L		 10639 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10640 cpu_arch_name);
10641 }
3e73aa7c 10642 else
2b5d6a91 10643 as_fatal (_("unknown architecture"));
89507696
JB		 10644
10645 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10646 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10647 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10648 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10649
252b5132
RH		 10650 switch (OUTPUT_FLAVOR)
10651 {
9384f2ff 10652#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 10653 case bfd_target_aout_flavour:
47926f60 10654 return AOUT_TARGET_FORMAT;
4c63da97 10655#endif
9384f2ff
AM		 10656#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10657# if defined (TE_PE) || defined (TE_PEP)
10658 case bfd_target_coff_flavour:
167ad85b
TG		 10659 if (flag_code == CODE_64BIT)
10660 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10661 else
10662 return "pe-i386";
9384f2ff 10663# elif defined (TE_GO32)
0561d57c
JK		 10664 case bfd_target_coff_flavour:
10665 return "coff-go32";
9384f2ff 10666# else
252b5132
RH		 10667 case bfd_target_coff_flavour:
10668 return "coff-i386";
9384f2ff 10669# endif
4c63da97 10670#endif
3e73aa7c 10671#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 10672 case bfd_target_elf_flavour:
3e73aa7c 10673 {
351f65ca
L		 10674 const char *format;
10675
10676 switch (x86_elf_abi)
4fa24527 10677 {
351f65ca
L		 10678 default:
10679 format = ELF_TARGET_FORMAT;
10680 break;
7f56bc95 10681 case X86_64_ABI:
351f65ca 10682 use_rela_relocations = 1;
4fa24527 10683 object_64bit = 1;
351f65ca
L		 10684 format = ELF_TARGET_FORMAT64;
10685 break;
7f56bc95 10686 case X86_64_X32_ABI:
4fa24527 10687 use_rela_relocations = 1;
351f65ca 10688 object_64bit = 1;
862be3fb 10689 disallow_64bit_reloc = 1;
351f65ca
L		 10690 format = ELF_TARGET_FORMAT32;
10691 break;
4fa24527 10692 }
3632d14b 10693 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10694 {
7f56bc95 10695 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10696 as_fatal (_("Intel L1OM is 64bit only"));
10697 return ELF_TARGET_L1OM_FORMAT;
10698 }
b49f93f6 10699 else if (cpu_arch_isa == PROCESSOR_K1OM)
7a9068fe
L		 10700 {
10701 if (x86_elf_abi != X86_64_ABI)
10702 as_fatal (_("Intel K1OM is 64bit only"));
10703 return ELF_TARGET_K1OM_FORMAT;
10704 }
81486035
L		 10705 else if (cpu_arch_isa == PROCESSOR_IAMCU)
10706 {
10707 if (x86_elf_abi != I386_ABI)
10708 as_fatal (_("Intel MCU is 32bit only"));
10709 return ELF_TARGET_IAMCU_FORMAT;
10710 }
8a9036a4 10711 else
351f65ca 10712 return format;
3e73aa7c 10713 }
e57f8c65
TG		 10714#endif
10715#if defined (OBJ_MACH_O)
10716 case bfd_target_mach_o_flavour:
d382c579
TG		 10717 if (flag_code == CODE_64BIT)
10718 {
10719 use_rela_relocations = 1;
10720 object_64bit = 1;
10721 return "mach-o-x86-64";
10722 }
10723 else
10724 return "mach-o-i386";
4c63da97 10725#endif
252b5132
RH		 10726 default:
10727 abort ();
10728 return NULL;
10729 }
10730}
10731
47926f60 10732#endif /* OBJ_MAYBE_ more than one */
252b5132 10733\f
252b5132 10734symbolS *
7016a5d5 10735md_undefined_symbol (char *name)
252b5132 10736{
18dc2407
ILT		 10737 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10738 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10739 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10740 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10741 {
10742 if (!GOT_symbol)
10743 {
10744 if (symbol_find (name))
10745 as_bad (_("GOT already in symbol table"));
10746 GOT_symbol = symbol_new (name, undefined_section,
10747 (valueT) 0, &zero_address_frag);
10748 };
10749 return GOT_symbol;
10750 }
252b5132
RH		 10751 return 0;
10752}
10753
10754/* Round up a section size to the appropriate boundary. */
47926f60 10755
252b5132 10756valueT
7016a5d5 10757md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10758{
4c63da97
AM		 10759#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10760 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10761 {
10762 /* For a.out, force the section size to be aligned. If we don't do
10763 this, BFD will align it for us, but it will not write out the
10764 final bytes of the section. This may be a bug in BFD, but it is
10765 easier to fix it here since that is how the other a.out targets
10766 work. */
10767 int align;
10768
10769 align = bfd_get_section_alignment (stdoutput, segment);
8d3842cd 10770 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
4c63da97 10771 }
252b5132
RH		 10772#endif
10773
10774 return size;
10775}
10776
10777/* On the i386, PC-relative offsets are relative to the start of the
10778 next instruction. That is, the address of the offset, plus its
10779 size, since the offset is always the last part of the insn. */
10780
10781long
e3bb37b5 10782md_pcrel_from (fixS *fixP)
252b5132
RH		 10783{
10784 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10785}
10786
10787#ifndef I386COFF
10788
10789static void
e3bb37b5 10790s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10791{
29b0f896 10792 int temp;
252b5132 10793
8a75718c
JB		 10794#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10795 if (IS_ELF)
10796 obj_elf_section_change_hook ();
10797#endif
252b5132
RH		 10798 temp = get_absolute_expression ();
10799 subseg_set (bss_section, (subsegT) temp);
10800 demand_empty_rest_of_line ();
10801}
10802
10803#endif
10804
252b5132 10805void
e3bb37b5 10806i386_validate_fix (fixS *fixp)
252b5132 10807{
02a86693 10808 if (fixp->fx_subsy)
252b5132 10809 {
02a86693 10810 if (fixp->fx_subsy == GOT_symbol)
23df1078 10811 {
02a86693
L		 10812 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10813 {
10814 if (!object_64bit)
10815 abort ();
10816#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10817 if (fixp->fx_tcbit2)
56ceb5b5
L		 10818 fixp->fx_r_type = (fixp->fx_tcbit
10819 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10820 : BFD_RELOC_X86_64_GOTPCRELX);
02a86693
L		 10821 else
10822#endif
10823 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10824 }
d6ab8113 10825 else
02a86693
L		 10826 {
10827 if (!object_64bit)
10828 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10829 else
10830 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
10831 }
10832 fixp->fx_subsy = 0;
23df1078 10833 }
252b5132 10834 }
02a86693
L		 10835#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10836 else if (!object_64bit)
10837 {
10838 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
10839 && fixp->fx_tcbit2)
10840 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
10841 }
10842#endif
252b5132
RH		 10843}
10844
252b5132 10845arelent *
7016a5d5 10846tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10847{
10848 arelent *rel;
10849 bfd_reloc_code_real_type code;
10850
10851 switch (fixp->fx_r_type)
10852 {
8ce3d284 10853#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10854 case BFD_RELOC_SIZE32:
10855 case BFD_RELOC_SIZE64:
10856 if (S_IS_DEFINED (fixp->fx_addsy)
10857 && !S_IS_EXTERNAL (fixp->fx_addsy))
10858 {
10859 /* Resolve size relocation against local symbol to size of
10860 the symbol plus addend. */
10861 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10862 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10863 && !fits_in_unsigned_long (value))
10864 as_bad_where (fixp->fx_file, fixp->fx_line,
10865 _("symbol size computation overflow"));
10866 fixp->fx_addsy = NULL;
10867 fixp->fx_subsy = NULL;
10868 md_apply_fix (fixp, (valueT *) &value, NULL);
10869 return NULL;
10870 }
8ce3d284 10871#endif
1a0670f3 10872 /* Fall through. */
8fd4256d 10873
3e73aa7c
JH		 10874 case BFD_RELOC_X86_64_PLT32:
10875 case BFD_RELOC_X86_64_GOT32:
10876 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 10877 case BFD_RELOC_X86_64_GOTPCRELX:
10878 case BFD_RELOC_X86_64_REX_GOTPCRELX:
252b5132
RH		 10879 case BFD_RELOC_386_PLT32:
10880 case BFD_RELOC_386_GOT32:
02a86693 10881 case BFD_RELOC_386_GOT32X:
252b5132
RH		 10882 case BFD_RELOC_386_GOTOFF:
10883 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10884 case BFD_RELOC_386_TLS_GD:
10885 case BFD_RELOC_386_TLS_LDM:
10886 case BFD_RELOC_386_TLS_LDO_32:
10887 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10888 case BFD_RELOC_386_TLS_IE:
10889 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10890 case BFD_RELOC_386_TLS_LE_32:
10891 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10892 case BFD_RELOC_386_TLS_GOTDESC:
10893 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10894 case BFD_RELOC_X86_64_TLSGD:
10895 case BFD_RELOC_X86_64_TLSLD:
10896 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10897 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10898 case BFD_RELOC_X86_64_GOTTPOFF:
10899 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10900 case BFD_RELOC_X86_64_TPOFF64:
10901 case BFD_RELOC_X86_64_GOTOFF64:
10902 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10903 case BFD_RELOC_X86_64_GOT64:
10904 case BFD_RELOC_X86_64_GOTPCREL64:
10905 case BFD_RELOC_X86_64_GOTPC64:
10906 case BFD_RELOC_X86_64_GOTPLT64:
10907 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10908 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10909 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10910 case BFD_RELOC_RVA:
10911 case BFD_RELOC_VTABLE_ENTRY:
10912 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10913#ifdef TE_PE
10914 case BFD_RELOC_32_SECREL:
10915#endif
252b5132
RH		 10916 code = fixp->fx_r_type;
10917 break;
dbbaec26
L		 10918 case BFD_RELOC_X86_64_32S:
10919 if (!fixp->fx_pcrel)
10920 {
10921 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10922 code = fixp->fx_r_type;
10923 break;
10924 }
1a0670f3 10925 /* Fall through. */
252b5132 10926 default:
93382f6d 10927 if (fixp->fx_pcrel)
252b5132 10928 {
93382f6d
AM		 10929 switch (fixp->fx_size)
10930 {
10931 default:
b091f402
AM		 10932 as_bad_where (fixp->fx_file, fixp->fx_line,
10933 _("can not do %d byte pc-relative relocation"),
10934 fixp->fx_size);
93382f6d
AM		 10935 code = BFD_RELOC_32_PCREL;
10936 break;
10937 case 1: code = BFD_RELOC_8_PCREL; break;
10938 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 10939 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 10940#ifdef BFD64
10941 case 8: code = BFD_RELOC_64_PCREL; break;
10942#endif
93382f6d
AM		 10943 }
10944 }
10945 else
10946 {
10947 switch (fixp->fx_size)
10948 {
10949 default:
b091f402
AM		 10950 as_bad_where (fixp->fx_file, fixp->fx_line,
10951 _("can not do %d byte relocation"),
10952 fixp->fx_size);
93382f6d
AM		 10953 code = BFD_RELOC_32;
10954 break;
10955 case 1: code = BFD_RELOC_8; break;
10956 case 2: code = BFD_RELOC_16; break;
10957 case 4: code = BFD_RELOC_32; break;
937149dd 10958#ifdef BFD64
3e73aa7c 10959 case 8: code = BFD_RELOC_64; break;
937149dd 10960#endif
93382f6d 10961 }
252b5132
RH		 10962 }
10963 break;
10964 }
252b5132 10965
d182319b
JB		 10966 if ((code == BFD_RELOC_32
10967 || code == BFD_RELOC_32_PCREL
10968 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10969 && GOT_symbol
10970 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10971 {
4fa24527 10972 if (!object_64bit)
d6ab8113
JB		 10973 code = BFD_RELOC_386_GOTPC;
10974 else
10975 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10976 }
7b81dfbb
AJ		 10977 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10978 && GOT_symbol
10979 && fixp->fx_addsy == GOT_symbol)
10980 {
10981 code = BFD_RELOC_X86_64_GOTPC64;
10982 }
252b5132 10983
add39d23
TS		 10984 rel = XNEW (arelent);
10985 rel->sym_ptr_ptr = XNEW (asymbol *);
49309057 10986 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10987
10988 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10989
3e73aa7c
JH		 10990 if (!use_rela_relocations)
10991 {
10992 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10993 vtable entry to be used in the relocation's section offset. */
10994 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10995 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10996#if defined (OBJ_COFF) && defined (TE_PE)
10997 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10998 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10999 else
11000#endif
c6682705 11001 rel->addend = 0;
3e73aa7c
JH		 11002 }
11003 /* Use the rela in 64bit mode. */
252b5132 11004 else
3e73aa7c 11005 {
862be3fb
L		 11006 if (disallow_64bit_reloc)
11007 switch (code)
11008 {
862be3fb
L		 11009 case BFD_RELOC_X86_64_DTPOFF64:
11010 case BFD_RELOC_X86_64_TPOFF64:
11011 case BFD_RELOC_64_PCREL:
11012 case BFD_RELOC_X86_64_GOTOFF64:
11013 case BFD_RELOC_X86_64_GOT64:
11014 case BFD_RELOC_X86_64_GOTPCREL64:
11015 case BFD_RELOC_X86_64_GOTPC64:
11016 case BFD_RELOC_X86_64_GOTPLT64:
11017 case BFD_RELOC_X86_64_PLTOFF64:
11018 as_bad_where (fixp->fx_file, fixp->fx_line,
11019 _("cannot represent relocation type %s in x32 mode"),
11020 bfd_get_reloc_code_name (code));
11021 break;
11022 default:
11023 break;
11024 }
11025
062cd5e7
AS		 11026 if (!fixp->fx_pcrel)
11027 rel->addend = fixp->fx_offset;
11028 else
11029 switch (code)
11030 {
11031 case BFD_RELOC_X86_64_PLT32:
11032 case BFD_RELOC_X86_64_GOT32:
11033 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 11034 case BFD_RELOC_X86_64_GOTPCRELX:
11035 case BFD_RELOC_X86_64_REX_GOTPCRELX:
bffbf940
JJ		 11036 case BFD_RELOC_X86_64_TLSGD:
11037 case BFD_RELOC_X86_64_TLSLD:
11038 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 11039 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11040 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 11041 rel->addend = fixp->fx_offset - fixp->fx_size;
11042 break;
11043 default:
11044 rel->addend = (section->vma
11045 - fixp->fx_size
11046 + fixp->fx_addnumber
11047 + md_pcrel_from (fixp));
11048 break;
11049 }
3e73aa7c
JH		 11050 }
11051
252b5132
RH		 11052 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11053 if (rel->howto == NULL)
11054 {
11055 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 11056 _("cannot represent relocation type %s"),
252b5132
RH		 11057 bfd_get_reloc_code_name (code));
11058 /* Set howto to a garbage value so that we can keep going. */
11059 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 11060 gas_assert (rel->howto != NULL);
252b5132
RH		 11061 }
11062
11063 return rel;
11064}
11065
ee86248c 11066#include "tc-i386-intel.c"
54cfded0 11067
a60de03c
JB		 11068void
11069tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 11070{
a60de03c
JB		 11071 int saved_naked_reg;
11072 char saved_register_dot;
54cfded0 11073
a60de03c
JB		 11074 saved_naked_reg = allow_naked_reg;
11075 allow_naked_reg = 1;
11076 saved_register_dot = register_chars['.'];
11077 register_chars['.'] = '.';
11078 allow_pseudo_reg = 1;
11079 expression_and_evaluate (exp);
11080 allow_pseudo_reg = 0;
11081 register_chars['.'] = saved_register_dot;
11082 allow_naked_reg = saved_naked_reg;
11083
e96d56a1 11084 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 11085 {
a60de03c
JB		 11086 if ((addressT) exp->X_add_number < i386_regtab_size)
11087 {
11088 exp->X_op = O_constant;
11089 exp->X_add_number = i386_regtab[exp->X_add_number]
11090 .dw2_regnum[flag_code >> 1];
11091 }
11092 else
11093 exp->X_op = O_illegal;
54cfded0 11094 }
54cfded0
AM		 11095}
11096
11097void
11098tc_x86_frame_initial_instructions (void)
11099{
a60de03c
JB		 11100 static unsigned int sp_regno[2];
11101
11102 if (!sp_regno[flag_code >> 1])
11103 {
11104 char *saved_input = input_line_pointer;
11105 char sp[][4] = {"esp", "rsp"};
11106 expressionS exp;
a4447b93 11107
a60de03c
JB		 11108 input_line_pointer = sp[flag_code >> 1];
11109 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 11110 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 11111 sp_regno[flag_code >> 1] = exp.X_add_number;
11112 input_line_pointer = saved_input;
11113 }
a4447b93 11114
61ff971f
L		 11115 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11116 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 11117}
d2b2c203 11118
d7921315
L		 11119int
11120x86_dwarf2_addr_size (void)
11121{
11122#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11123 if (x86_elf_abi == X86_64_X32_ABI)
11124 return 4;
11125#endif
11126 return bfd_arch_bits_per_address (stdoutput) / 8;
11127}
11128
d2b2c203
DJ		 11129int
11130i386_elf_section_type (const char *str, size_t len)
11131{
11132 if (flag_code == CODE_64BIT
11133 && len == sizeof ("unwind") - 1
11134 && strncmp (str, "unwind", 6) == 0)
11135 return SHT_X86_64_UNWIND;
11136
11137 return -1;
11138}
bb41ade5 11139
ad5fec3b
EB		 11140#ifdef TE_SOLARIS
11141void
11142i386_solaris_fix_up_eh_frame (segT sec)
11143{
11144 if (flag_code == CODE_64BIT)
11145 elf_section_type (sec) = SHT_X86_64_UNWIND;
11146}
11147#endif
11148
bb41ade5
AM		 11149#ifdef TE_PE
11150void
11151tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11152{
91d6fa6a 11153 expressionS exp;
bb41ade5 11154
91d6fa6a
NC		 11155 exp.X_op = O_secrel;
11156 exp.X_add_symbol = symbol;
11157 exp.X_add_number = 0;
11158 emit_expr (&exp, size);
bb41ade5
AM		 11159}
11160#endif
3b22753a
L		 11161
11162#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11163/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11164
01e1a5bc 11165bfd_vma
6d4af3c2 11166x86_64_section_letter (int letter, const char **ptr_msg)
3b22753a
L		 11167{
11168 if (flag_code == CODE_64BIT)
11169 {
11170 if (letter == 'l')
11171 return SHF_X86_64_LARGE;
11172
8f3bae45 11173 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 11174 }
3b22753a 11175 else
8f3bae45 11176 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 11177 return -1;
11178}
11179
01e1a5bc 11180bfd_vma
3b22753a
L		 11181x86_64_section_word (char *str, size_t len)
11182{
8620418b 11183 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 11184 return SHF_X86_64_LARGE;
11185
11186 return -1;
11187}
11188
11189static void
11190handle_large_common (int small ATTRIBUTE_UNUSED)
11191{
11192 if (flag_code != CODE_64BIT)
11193 {
11194 s_comm_internal (0, elf_common_parse);
11195 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11196 }
11197 else
11198 {
11199 static segT lbss_section;
11200 asection *saved_com_section_ptr = elf_com_section_ptr;
11201 asection *saved_bss_section = bss_section;
11202
11203 if (lbss_section == NULL)
11204 {
11205 flagword applicable;
11206 segT seg = now_seg;
11207 subsegT subseg = now_subseg;
11208
11209 /* The .lbss section is for local .largecomm symbols. */
11210 lbss_section = subseg_new (".lbss", 0);
11211 applicable = bfd_applicable_section_flags (stdoutput);
11212 bfd_set_section_flags (stdoutput, lbss_section,
11213 applicable & SEC_ALLOC);
11214 seg_info (lbss_section)->bss = 1;
11215
11216 subseg_set (seg, subseg);
11217 }
11218
11219 elf_com_section_ptr = &_bfd_elf_large_com_section;
11220 bss_section = lbss_section;
11221
11222 s_comm_internal (0, elf_common_parse);
11223
11224 elf_com_section_ptr = saved_com_section_ptr;
11225 bss_section = saved_bss_section;
11226 }
11227}
11228#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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