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PR gas/12011
[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
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b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
c75ef631 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
6305a203
L		 58/* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
c32fa91d 62 REP_PREFIX, LOCK_PREFIX. */
6305a203
L		 63#define WAIT_PREFIX 0
64#define SEG_PREFIX 1
65#define ADDR_PREFIX 2
66#define DATA_PREFIX 3
c32fa91d
L		 67#define REP_PREFIX 4
68#define LOCK_PREFIX 5
69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 86/* Intel Syntax. Use a non-ascii letter since since it never appears
87 in instructions. */
88#define LONG_DOUBLE_MNEM_SUFFIX '\1'
89
90#define END_OF_INSN '\0'
91
92/*
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
97 END.
98 */
99typedef struct
100{
d3ce72d0
NC		 101 const insn_template *start;
102 const insn_template *end;
6305a203
L		 103}
104templates;
105
106/* 386 operand encoding bytes: see 386 book for details of this. */
107typedef struct
108{
109 unsigned int regmem; /* codes register or memory operand */
110 unsigned int reg; /* codes register operand (or extended opcode) */
111 unsigned int mode; /* how to interpret regmem & reg */
112}
113modrm_byte;
114
115/* x86-64 extension prefix. */
116typedef int rex_byte;
117
6305a203
L		 118/* 386 opcode byte to code indirect addressing. */
119typedef struct
120{
121 unsigned base;
122 unsigned index;
123 unsigned scale;
124}
125sib_byte;
126
6305a203
L		 127/* x86 arch names, types and features */
128typedef struct
129{
130 const char *name; /* arch name */
8a2c8fef 131 unsigned int len; /* arch string length */
6305a203
L		 132 enum processor_type type; /* arch type */
133 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 134 unsigned int skip; /* show_arch should skip this. */
22109423 135 unsigned int negated; /* turn off indicated flags. */
6305a203
L		 136}
137arch_entry;
138
78f12dd3 139static void update_code_flag (int, int);
e3bb37b5
L		 140static void set_code_flag (int);
141static void set_16bit_gcc_code_flag (int);
142static void set_intel_syntax (int);
1efbbeb4 143static void set_intel_mnemonic (int);
db51cc60 144static void set_allow_index_reg (int);
cb19c032 145static void set_sse_check (int);
e3bb37b5 146static void set_cpu_arch (int);
6482c264 147#ifdef TE_PE
e3bb37b5 148static void pe_directive_secrel (int);
6482c264 149#endif
e3bb37b5
L		 150static void signed_cons (int);
151static char *output_invalid (int c);
ee86248c
JB		 152static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
153 const char *);
154static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
155 const char *);
a7619375 156static int i386_att_operand (char *);
e3bb37b5 157static int i386_intel_operand (char *, int);
ee86248c
JB		 158static int i386_intel_simplify (expressionS *);
159static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 160static const reg_entry *parse_register (char *, char **);
161static char *parse_insn (char *, char *);
162static char *parse_operands (char *, const char *);
163static void swap_operands (void);
4d456e3d 164static void swap_2_operands (int, int);
e3bb37b5
L		 165static void optimize_imm (void);
166static void optimize_disp (void);
d3ce72d0 167static const insn_template *match_template (void);
e3bb37b5
L		 168static int check_string (void);
169static int process_suffix (void);
170static int check_byte_reg (void);
171static int check_long_reg (void);
172static int check_qword_reg (void);
173static int check_word_reg (void);
174static int finalize_imm (void);
175static int process_operands (void);
176static const seg_entry *build_modrm_byte (void);
177static void output_insn (void);
178static void output_imm (fragS *, offsetT);
179static void output_disp (fragS *, offsetT);
29b0f896 180#ifndef I386COFF
e3bb37b5 181static void s_bss (int);
252b5132 182#endif
17d4e2a2
L		 183#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
184static void handle_large_common (int small ATTRIBUTE_UNUSED);
185#endif
252b5132 186
a847613f 187static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 188
c0f3af97
L		 189/* VEX prefix. */
190typedef struct
191{
192 /* VEX prefix is either 2 byte or 3 byte. */
193 unsigned char bytes[3];
194 unsigned int length;
195 /* Destination or source register specifier. */
196 const reg_entry *register_specifier;
197} vex_prefix;
198
252b5132 199/* 'md_assemble ()' gathers together information and puts it into a
47926f60 200 i386_insn. */
252b5132 201
520dc8e8
AM		 202union i386_op
203 {
204 expressionS *disps;
205 expressionS *imms;
206 const reg_entry *regs;
207 };
208
a65babc9
L		 209enum i386_error
210 {
86e026a4 211 operand_size_mismatch,
a65babc9
L		 212 operand_type_mismatch,
213 register_type_mismatch,
214 number_of_operands_mismatch,
215 invalid_instruction_suffix,
216 bad_imm4,
217 old_gcc_only,
218 unsupported_with_intel_mnemonic,
219 unsupported_syntax,
220 unsupported
221 };
222
252b5132
RH		 223struct _i386_insn
224 {
47926f60 225 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 226 insn_template tm;
252b5132 227
7d5e4556
L		 228 /* SUFFIX holds the instruction size suffix for byte, word, dword
229 or qword, if given. */
252b5132
RH		 230 char suffix;
231
47926f60 232 /* OPERANDS gives the number of given operands. */
252b5132
RH		 233 unsigned int operands;
234
235 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
236 of given register, displacement, memory operands and immediate
47926f60 237 operands. */
252b5132
RH		 238 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
239
240 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 241 use OP[i] for the corresponding operand. */
40fb9820 242 i386_operand_type types[MAX_OPERANDS];
252b5132 243
520dc8e8
AM		 244 /* Displacement expression, immediate expression, or register for each
245 operand. */
246 union i386_op op[MAX_OPERANDS];
252b5132 247
3e73aa7c
JH		 248 /* Flags for operands. */
249 unsigned int flags[MAX_OPERANDS];
250#define Operand_PCrel 1
251
252b5132 252 /* Relocation type for operand */
f86103b7 253 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 254
252b5132
RH		 255 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
256 the base index byte below. */
257 const reg_entry *base_reg;
258 const reg_entry *index_reg;
259 unsigned int log2_scale_factor;
260
261 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 262 explicit segment overrides are given. */
ce8a8b2f 263 const seg_entry *seg[2];
252b5132
RH		 264
265 /* PREFIX holds all the given prefix opcodes (usually null).
266 PREFIXES is the number of prefix opcodes. */
267 unsigned int prefixes;
268 unsigned char prefix[MAX_PREFIXES];
269
270 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 271 addressing modes of this insn are encoded. */
252b5132 272 modrm_byte rm;
3e73aa7c 273 rex_byte rex;
252b5132 274 sib_byte sib;
c0f3af97 275 vex_prefix vex;
b6169b20
L		 276
277 /* Swap operand in encoding. */
4473e004 278 unsigned int swap_operand;
891edac4
L		 279
280 /* Error message. */
a65babc9 281 enum i386_error error;
252b5132
RH		 282 };
283
284typedef struct _i386_insn i386_insn;
285
286/* List of chars besides those in app.c:symbol_chars that can start an
287 operand. Used to prevent the scrubber eating vital white-space. */
32137342 288const char extra_symbol_chars[] = "*%-(["
252b5132 289#ifdef LEX_AT
32137342
NC		 290 "@"
291#endif
292#ifdef LEX_QM
293 "?"
252b5132 294#endif
32137342 295 ;
252b5132 296
29b0f896
AM		 297#if (defined (TE_I386AIX) \
298 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 299 && !defined (TE_GNU) \
29b0f896 300 && !defined (TE_LINUX) \
32137342 301 && !defined (TE_NETWARE) \
29b0f896
AM		 302 && !defined (TE_FreeBSD) \
303 && !defined (TE_NetBSD)))
252b5132 304/* This array holds the chars that always start a comment. If the
b3b91714
AM		 305 pre-processor is disabled, these aren't very useful. The option
306 --divide will remove '/' from this list. */
307const char *i386_comment_chars = "#/";
308#define SVR4_COMMENT_CHARS 1
252b5132 309#define PREFIX_SEPARATOR '\\'
252b5132 310
b3b91714
AM		 311#else
312const char *i386_comment_chars = "#";
313#define PREFIX_SEPARATOR '/'
314#endif
315
252b5132
RH		 316/* This array holds the chars that only start a comment at the beginning of
317 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 318 .line and .file directives will appear in the pre-processed output.
319 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 320 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 321 #NO_APP at the beginning of its output.
322 Also note that comments started like this one will always work if
252b5132 323 '/' isn't otherwise defined. */
b3b91714 324const char line_comment_chars[] = "#/";
252b5132 325
63a0b638 326const char line_separator_chars[] = ";";
252b5132 327
ce8a8b2f
AM		 328/* Chars that can be used to separate mant from exp in floating point
329 nums. */
252b5132
RH		 330const char EXP_CHARS[] = "eE";
331
ce8a8b2f
AM		 332/* Chars that mean this number is a floating point constant
333 As in 0f12.456
334 or 0d1.2345e12. */
252b5132
RH		 335const char FLT_CHARS[] = "fFdDxX";
336
ce8a8b2f 337/* Tables for lexical analysis. */
252b5132
RH		 338static char mnemonic_chars[256];
339static char register_chars[256];
340static char operand_chars[256];
341static char identifier_chars[256];
342static char digit_chars[256];
343
ce8a8b2f 344/* Lexical macros. */
252b5132
RH		 345#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
346#define is_operand_char(x) (operand_chars[(unsigned char) x])
347#define is_register_char(x) (register_chars[(unsigned char) x])
348#define is_space_char(x) ((x) == ' ')
349#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
350#define is_digit_char(x) (digit_chars[(unsigned char) x])
351
0234cb7c 352/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 353static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
354
355/* md_assemble() always leaves the strings it's passed unaltered. To
356 effect this we maintain a stack of saved characters that we've smashed
357 with '\0's (indicating end of strings for various sub-fields of the
47926f60 358 assembler instruction). */
252b5132 359static char save_stack[32];
ce8a8b2f 360static char *save_stack_p;
252b5132
RH		 361#define END_STRING_AND_SAVE(s) \
362 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
363#define RESTORE_END_STRING(s) \
364 do { *(s) = *--save_stack_p; } while (0)
365
47926f60 366/* The instruction we're assembling. */
252b5132
RH		 367static i386_insn i;
368
369/* Possible templates for current insn. */
370static const templates *current_templates;
371
31b2323c
L		 372/* Per instruction expressionS buffers: max displacements & immediates. */
373static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
374static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 375
47926f60 376/* Current operand we are working on. */
ee86248c 377static int this_operand = -1;
252b5132 378
3e73aa7c
JH		 379/* We support four different modes. FLAG_CODE variable is used to distinguish
380 these. */
381
382enum flag_code {
383 CODE_32BIT,
384 CODE_16BIT,
385 CODE_64BIT };
386
387static enum flag_code flag_code;
4fa24527 388static unsigned int object_64bit;
3e73aa7c
JH		 389static int use_rela_relocations = 0;
390
391/* The names used to print error messages. */
b77a7acd 392static const char *flag_code_names[] =
3e73aa7c
JH		 393 {
394 "32",
395 "16",
396 "64"
397 };
252b5132 398
47926f60
KH		 399/* 1 for intel syntax,
400 0 if att syntax. */
401static int intel_syntax = 0;
252b5132 402
1efbbeb4
L		 403/* 1 for intel mnemonic,
404 0 if att mnemonic. */
405static int intel_mnemonic = !SYSV386_COMPAT;
406
5209009a 407/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 408static int old_gcc = OLDGCC_COMPAT;
409
a60de03c
JB		 410/* 1 if pseudo registers are permitted. */
411static int allow_pseudo_reg = 0;
412
47926f60
KH		 413/* 1 if register prefix % not required. */
414static int allow_naked_reg = 0;
252b5132 415
ba104c83 416/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 417static int allow_index_reg = 0;
418
daf50ae7
L		 419static enum
420 {
421 sse_check_none = 0,
422 sse_check_warning,
423 sse_check_error
424 }
425sse_check;
426
2ca3ace5
L		 427/* Register prefix used for error message. */
428static const char *register_prefix = "%";
429
47926f60
KH		 430/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
431 leave, push, and pop instructions so that gcc has the same stack
432 frame as in 32 bit mode. */
433static char stackop_size = '\0';
eecb386c 434
12b55ccc
L		 435/* Non-zero to optimize code alignment. */
436int optimize_align_code = 1;
437
47926f60
KH		 438/* Non-zero to quieten some warnings. */
439static int quiet_warnings = 0;
a38cf1db 440
47926f60
KH		 441/* CPU name. */
442static const char *cpu_arch_name = NULL;
6305a203 443static char *cpu_sub_arch_name = NULL;
a38cf1db 444
47926f60 445/* CPU feature flags. */
40fb9820
L		 446static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
447
ccc9c027
L		 448/* If we have selected a cpu we are generating instructions for. */
449static int cpu_arch_tune_set = 0;
450
9103f4f4 451/* Cpu we are generating instructions for. */
fbf3f584 452enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 453
454/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 455static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 456
ccc9c027 457/* CPU instruction set architecture used. */
fbf3f584 458enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 459
9103f4f4 460/* CPU feature flags of instruction set architecture used. */
fbf3f584 461i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 462
fddf5b5b
AM		 463/* If set, conditional jumps are not automatically promoted to handle
464 larger than a byte offset. */
465static unsigned int no_cond_jump_promotion = 0;
466
c0f3af97
L		 467/* Encode SSE instructions with VEX prefix. */
468static unsigned int sse2avx;
469
539f890d
L		 470/* Encode scalar AVX instructions with specific vector length. */
471static enum
472 {
473 vex128 = 0,
474 vex256
475 } avxscalar;
476
29b0f896 477/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 478static symbolS *GOT_symbol;
29b0f896 479
a4447b93
RH		 480/* The dwarf2 return column, adjusted for 32 or 64 bit. */
481unsigned int x86_dwarf2_return_column;
482
483/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
484int x86_cie_data_alignment;
485
252b5132 486/* Interface to relax_segment.
fddf5b5b
AM		 487 There are 3 major relax states for 386 jump insns because the
488 different types of jumps add different sizes to frags when we're
489 figuring out what sort of jump to choose to reach a given label. */
252b5132 490
47926f60 491/* Types. */
93c2a809
AM		 492#define UNCOND_JUMP 0
493#define COND_JUMP 1
494#define COND_JUMP86 2
fddf5b5b 495
47926f60 496/* Sizes. */
252b5132
RH		 497#define CODE16 1
498#define SMALL 0
29b0f896 499#define SMALL16 (SMALL | CODE16)
252b5132 500#define BIG 2
29b0f896 501#define BIG16 (BIG | CODE16)
252b5132
RH		 502
503#ifndef INLINE
504#ifdef __GNUC__
505#define INLINE __inline__
506#else
507#define INLINE
508#endif
509#endif
510
fddf5b5b
AM		 511#define ENCODE_RELAX_STATE(type, size) \
512 ((relax_substateT) (((type) << 2) | (size)))
513#define TYPE_FROM_RELAX_STATE(s) \
514 ((s) >> 2)
515#define DISP_SIZE_FROM_RELAX_STATE(s) \
516 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 517
518/* This table is used by relax_frag to promote short jumps to long
519 ones where necessary. SMALL (short) jumps may be promoted to BIG
520 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
521 don't allow a short jump in a 32 bit code segment to be promoted to
522 a 16 bit offset jump because it's slower (requires data size
523 prefix), and doesn't work, unless the destination is in the bottom
524 64k of the code segment (The top 16 bits of eip are zeroed). */
525
526const relax_typeS md_relax_table[] =
527{
24eab124
AM		 528 /* The fields are:
529 1) most positive reach of this state,
530 2) most negative reach of this state,
93c2a809 531 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 532 4) which index into the table to try if we can't fit into this one. */
252b5132 533
fddf5b5b 534 /* UNCOND_JUMP states. */
93c2a809
AM		 535 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
536 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
537 /* dword jmp adds 4 bytes to frag:
538 0 extra opcode bytes, 4 displacement bytes. */
252b5132 539 {0, 0, 4, 0},
93c2a809
AM		 540 /* word jmp adds 2 byte2 to frag:
541 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 542 {0, 0, 2, 0},
543
93c2a809
AM		 544 /* COND_JUMP states. */
545 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
546 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
547 /* dword conditionals adds 5 bytes to frag:
548 1 extra opcode byte, 4 displacement bytes. */
549 {0, 0, 5, 0},
fddf5b5b 550 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 551 1 extra opcode byte, 2 displacement bytes. */
552 {0, 0, 3, 0},
553
554 /* COND_JUMP86 states. */
555 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
556 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
557 /* dword conditionals adds 5 bytes to frag:
558 1 extra opcode byte, 4 displacement bytes. */
559 {0, 0, 5, 0},
560 /* word conditionals add 4 bytes to frag:
561 1 displacement byte and a 3 byte long branch insn. */
562 {0, 0, 4, 0}
252b5132
RH		 563};
564
9103f4f4
L		 565static const arch_entry cpu_arch[] =
566{
89507696
JB		 567 /* Do not replace the first two entries - i386_target_format()
568 relies on them being there in this order. */
8a2c8fef 569 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
22109423 570 CPU_GENERIC32_FLAGS, 0, 0 },
8a2c8fef 571 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
22109423 572 CPU_GENERIC64_FLAGS, 0, 0 },
8a2c8fef 573 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
22109423 574 CPU_NONE_FLAGS, 0, 0 },
8a2c8fef 575 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
22109423 576 CPU_I186_FLAGS, 0, 0 },
8a2c8fef 577 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
22109423 578 CPU_I286_FLAGS, 0, 0 },
8a2c8fef 579 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
22109423 580 CPU_I386_FLAGS, 0, 0 },
8a2c8fef 581 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
22109423 582 CPU_I486_FLAGS, 0, 0 },
8a2c8fef 583 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
22109423 584 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 585 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
22109423 586 CPU_I686_FLAGS, 0, 0 },
8a2c8fef 587 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
22109423 588 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 589 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
22109423 590 CPU_PENTIUMPRO_FLAGS, 0, 0 },
8a2c8fef 591 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
22109423 592 CPU_P2_FLAGS, 0, 0 },
8a2c8fef 593 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
22109423 594 CPU_P3_FLAGS, 0, 0 },
8a2c8fef 595 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
22109423 596 CPU_P4_FLAGS, 0, 0 },
8a2c8fef 597 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
22109423 598 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 599 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
22109423 600 CPU_NOCONA_FLAGS, 0, 0 },
8a2c8fef 601 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
22109423 602 CPU_CORE_FLAGS, 1, 0 },
8a2c8fef 603 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
22109423 604 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 605 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
22109423 606 CPU_CORE2_FLAGS, 1, 0 },
8a2c8fef 607 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
22109423 608 CPU_CORE2_FLAGS, 0, 0 },
8a2c8fef 609 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
22109423 610 CPU_COREI7_FLAGS, 0, 0 },
8a2c8fef 611 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
22109423 612 CPU_L1OM_FLAGS, 0, 0 },
8a2c8fef 613 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
22109423 614 CPU_K6_FLAGS, 0, 0 },
8a2c8fef 615 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
22109423 616 CPU_K6_2_FLAGS, 0, 0 },
8a2c8fef 617 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
22109423 618 CPU_ATHLON_FLAGS, 0, 0 },
8a2c8fef 619 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
22109423 620 CPU_K8_FLAGS, 1, 0 },
8a2c8fef 621 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
22109423 622 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 623 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
22109423 624 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 625 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
22109423 626 CPU_AMDFAM10_FLAGS, 0, 0 },
68339fdf 627 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BDVER1,
22109423 628 CPU_BDVER1_FLAGS, 0, 0 },
8a2c8fef 629 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
22109423 630 CPU_8087_FLAGS, 0, 0 },
8a2c8fef 631 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
22109423 632 CPU_287_FLAGS, 0, 0 },
8a2c8fef 633 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
22109423 634 CPU_387_FLAGS, 0, 0 },
8a2c8fef 635 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
22109423 636 CPU_ANY87_FLAGS, 0, 1 },
8a2c8fef 637 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
22109423 638 CPU_MMX_FLAGS, 0, 0 },
8a2c8fef 639 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
22109423 640 CPU_3DNOWA_FLAGS, 0, 1 },
8a2c8fef 641 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
22109423 642 CPU_SSE_FLAGS, 0, 0 },
8a2c8fef 643 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
22109423 644 CPU_SSE2_FLAGS, 0, 0 },
8a2c8fef 645 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
22109423 646 CPU_SSE3_FLAGS, 0, 0 },
8a2c8fef 647 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
22109423 648 CPU_SSSE3_FLAGS, 0, 0 },
8a2c8fef 649 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
22109423 650 CPU_SSE4_1_FLAGS, 0, 0 },
8a2c8fef 651 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
22109423 652 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 653 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
22109423 654 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 655 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
22109423 656 CPU_ANY_SSE_FLAGS, 0, 1 },
8a2c8fef 657 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
22109423 658 CPU_AVX_FLAGS, 0, 0 },
8a2c8fef 659 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
22109423 660 CPU_ANY_AVX_FLAGS, 0, 1 },
8a2c8fef 661 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
22109423 662 CPU_VMX_FLAGS, 0, 0 },
8a2c8fef 663 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
22109423 664 CPU_SMX_FLAGS, 0, 0 },
8a2c8fef 665 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
22109423 666 CPU_XSAVE_FLAGS, 0, 0 },
c7b8aa3a 667 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
22109423 668 CPU_XSAVEOPT_FLAGS, 0, 0 },
8a2c8fef 669 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
22109423 670 CPU_AES_FLAGS, 0, 0 },
8a2c8fef 671 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
22109423 672 CPU_PCLMUL_FLAGS, 0, 0 },
8a2c8fef 673 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
22109423 674 CPU_PCLMUL_FLAGS, 1, 0 },
c7b8aa3a 675 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
22109423 676 CPU_FSGSBASE_FLAGS, 0, 0 },
c7b8aa3a 677 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
22109423 678 CPU_RDRND_FLAGS, 0, 0 },
c7b8aa3a 679 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
22109423 680 CPU_F16C_FLAGS, 0, 0 },
8a2c8fef 681 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
22109423 682 CPU_FMA_FLAGS, 0, 0 },
8a2c8fef 683 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
22109423 684 CPU_FMA4_FLAGS, 0, 0 },
8a2c8fef 685 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
22109423 686 CPU_XOP_FLAGS, 0, 0 },
8a2c8fef 687 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
22109423 688 CPU_LWP_FLAGS, 0, 0 },
8a2c8fef 689 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
22109423 690 CPU_MOVBE_FLAGS, 0, 0 },
8a2c8fef 691 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
22109423 692 CPU_EPT_FLAGS, 0, 0 },
8a2c8fef 693 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
22109423
L		 694 CPU_CLFLUSH_FLAGS, 0, 0 },
695 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
696 CPU_NOP_FLAGS, 0, 0 },
8a2c8fef 697 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
22109423 698 CPU_SYSCALL_FLAGS, 0, 0 },
8a2c8fef 699 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
22109423 700 CPU_RDTSCP_FLAGS, 0, 0 },
8a2c8fef 701 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
22109423 702 CPU_3DNOW_FLAGS, 0, 0 },
8a2c8fef 703 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
22109423 704 CPU_3DNOWA_FLAGS, 0, 0 },
8a2c8fef 705 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
22109423 706 CPU_PADLOCK_FLAGS, 0, 0 },
8a2c8fef 707 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
22109423 708 CPU_SVME_FLAGS, 1, 0 },
8a2c8fef 709 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
22109423 710 CPU_SVME_FLAGS, 0, 0 },
8a2c8fef 711 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
22109423 712 CPU_SSE4A_FLAGS, 0, 0 },
8a2c8fef 713 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
22109423 714 CPU_ABM_FLAGS, 0, 0 },
e413e4e9
AM		 715};
716
704209c0 717#ifdef I386COFF
a6c24e68
NC		 718/* Like s_lcomm_internal in gas/read.c but the alignment string
719 is allowed to be optional. */
720
721static symbolS *
722pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
723{
724 addressT align = 0;
725
726 SKIP_WHITESPACE ();
727
7ab9ffdd 728 if (needs_align
a6c24e68
NC		 729 && *input_line_pointer == ',')
730 {
731 align = parse_align (needs_align - 1);
7ab9ffdd 732
a6c24e68
NC		 733 if (align == (addressT) -1)
734 return NULL;
735 }
736 else
737 {
738 if (size >= 8)
739 align = 3;
740 else if (size >= 4)
741 align = 2;
742 else if (size >= 2)
743 align = 1;
744 else
745 align = 0;
746 }
747
748 bss_alloc (symbolP, size, align);
749 return symbolP;
750}
751
704209c0 752static void
a6c24e68
NC		 753pe_lcomm (int needs_align)
754{
755 s_comm_internal (needs_align * 2, pe_lcomm_internal);
756}
704209c0 757#endif
a6c24e68 758
29b0f896
AM		 759const pseudo_typeS md_pseudo_table[] =
760{
761#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
762 {"align", s_align_bytes, 0},
763#else
764 {"align", s_align_ptwo, 0},
765#endif
766 {"arch", set_cpu_arch, 0},
767#ifndef I386COFF
768 {"bss", s_bss, 0},
a6c24e68
NC		 769#else
770 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 771#endif
772 {"ffloat", float_cons, 'f'},
773 {"dfloat", float_cons, 'd'},
774 {"tfloat", float_cons, 'x'},
775 {"value", cons, 2},
d182319b 776 {"slong", signed_cons, 4},
29b0f896
AM		 777 {"noopt", s_ignore, 0},
778 {"optim", s_ignore, 0},
779 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
780 {"code16", set_code_flag, CODE_16BIT},
781 {"code32", set_code_flag, CODE_32BIT},
782 {"code64", set_code_flag, CODE_64BIT},
783 {"intel_syntax", set_intel_syntax, 1},
784 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 785 {"intel_mnemonic", set_intel_mnemonic, 1},
786 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 787 {"allow_index_reg", set_allow_index_reg, 1},
788 {"disallow_index_reg", set_allow_index_reg, 0},
cb19c032 789 {"sse_check", set_sse_check, 0},
3b22753a
L		 790#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
791 {"largecomm", handle_large_common, 0},
07a53e5c 792#else
e3bb37b5 793 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 794 {"loc", dwarf2_directive_loc, 0},
795 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 796#endif
6482c264
NC		 797#ifdef TE_PE
798 {"secrel32", pe_directive_secrel, 0},
799#endif
29b0f896
AM		 800 {0, 0, 0}
801};
802
803/* For interface with expression (). */
804extern char *input_line_pointer;
805
806/* Hash table for instruction mnemonic lookup. */
807static struct hash_control *op_hash;
808
809/* Hash table for register lookup. */
810static struct hash_control *reg_hash;
811\f
252b5132 812void
e3bb37b5 813i386_align_code (fragS *fragP, int count)
252b5132 814{
ce8a8b2f
AM		 815 /* Various efficient no-op patterns for aligning code labels.
816 Note: Don't try to assemble the instructions in the comments.
817 0L and 0w are not legal. */
252b5132
RH		 818 static const char f32_1[] =
819 {0x90}; /* nop */
820 static const char f32_2[] =
ccc9c027 821 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 822 static const char f32_3[] =
823 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
824 static const char f32_4[] =
825 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
826 static const char f32_5[] =
827 {0x90, /* nop */
828 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
829 static const char f32_6[] =
830 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
831 static const char f32_7[] =
832 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
833 static const char f32_8[] =
834 {0x90, /* nop */
835 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
836 static const char f32_9[] =
837 {0x89,0xf6, /* movl %esi,%esi */
838 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
839 static const char f32_10[] =
840 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
841 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
842 static const char f32_11[] =
843 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
844 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
845 static const char f32_12[] =
846 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
847 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
848 static const char f32_13[] =
849 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
850 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
851 static const char f32_14[] =
852 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
853 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 854 static const char f16_3[] =
855 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 856 static const char f16_4[] =
857 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
858 static const char f16_5[] =
859 {0x90, /* nop */
860 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
861 static const char f16_6[] =
862 {0x89,0xf6, /* mov %si,%si */
863 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
864 static const char f16_7[] =
865 {0x8d,0x74,0x00, /* lea 0(%si),%si */
866 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
867 static const char f16_8[] =
868 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
869 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 870 static const char jump_31[] =
871 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
872 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
873 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
874 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 875 static const char *const f32_patt[] = {
876 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 877 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 878 };
879 static const char *const f16_patt[] = {
76bc74dc 880 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 881 };
ccc9c027
L		 882 /* nopl (%[re]ax) */
883 static const char alt_3[] =
884 {0x0f,0x1f,0x00};
885 /* nopl 0(%[re]ax) */
886 static const char alt_4[] =
887 {0x0f,0x1f,0x40,0x00};
888 /* nopl 0(%[re]ax,%[re]ax,1) */
889 static const char alt_5[] =
890 {0x0f,0x1f,0x44,0x00,0x00};
891 /* nopw 0(%[re]ax,%[re]ax,1) */
892 static const char alt_6[] =
893 {0x66,0x0f,0x1f,0x44,0x00,0x00};
894 /* nopl 0L(%[re]ax) */
895 static const char alt_7[] =
896 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
897 /* nopl 0L(%[re]ax,%[re]ax,1) */
898 static const char alt_8[] =
899 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
900 /* nopw 0L(%[re]ax,%[re]ax,1) */
901 static const char alt_9[] =
902 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
903 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
904 static const char alt_10[] =
905 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
906 /* data16
907 nopw %cs:0L(%[re]ax,%[re]ax,1) */
908 static const char alt_long_11[] =
909 {0x66,
910 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
911 /* data16
912 data16
913 nopw %cs:0L(%[re]ax,%[re]ax,1) */
914 static const char alt_long_12[] =
915 {0x66,
916 0x66,
917 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
918 /* data16
919 data16
920 data16
921 nopw %cs:0L(%[re]ax,%[re]ax,1) */
922 static const char alt_long_13[] =
923 {0x66,
924 0x66,
925 0x66,
926 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
927 /* data16
928 data16
929 data16
930 data16
931 nopw %cs:0L(%[re]ax,%[re]ax,1) */
932 static const char alt_long_14[] =
933 {0x66,
934 0x66,
935 0x66,
936 0x66,
937 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
938 /* data16
939 data16
940 data16
941 data16
942 data16
943 nopw %cs:0L(%[re]ax,%[re]ax,1) */
944 static const char alt_long_15[] =
945 {0x66,
946 0x66,
947 0x66,
948 0x66,
949 0x66,
950 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
951 /* nopl 0(%[re]ax,%[re]ax,1)
952 nopw 0(%[re]ax,%[re]ax,1) */
953 static const char alt_short_11[] =
954 {0x0f,0x1f,0x44,0x00,0x00,
955 0x66,0x0f,0x1f,0x44,0x00,0x00};
956 /* nopw 0(%[re]ax,%[re]ax,1)
957 nopw 0(%[re]ax,%[re]ax,1) */
958 static const char alt_short_12[] =
959 {0x66,0x0f,0x1f,0x44,0x00,0x00,
960 0x66,0x0f,0x1f,0x44,0x00,0x00};
961 /* nopw 0(%[re]ax,%[re]ax,1)
962 nopl 0L(%[re]ax) */
963 static const char alt_short_13[] =
964 {0x66,0x0f,0x1f,0x44,0x00,0x00,
965 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
966 /* nopl 0L(%[re]ax)
967 nopl 0L(%[re]ax) */
968 static const char alt_short_14[] =
969 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
970 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
971 /* nopl 0L(%[re]ax)
972 nopl 0L(%[re]ax,%[re]ax,1) */
973 static const char alt_short_15[] =
974 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
975 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
976 static const char *const alt_short_patt[] = {
977 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
978 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
979 alt_short_14, alt_short_15
980 };
981 static const char *const alt_long_patt[] = {
982 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
983 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
984 alt_long_14, alt_long_15
985 };
252b5132 986
76bc74dc
L		 987 /* Only align for at least a positive non-zero boundary. */
988 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 989 return;
3e73aa7c 990
ccc9c027
L		 991 /* We need to decide which NOP sequence to use for 32bit and
992 64bit. When -mtune= is used:
4eed87de 993
76bc74dc
L		 994 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
995 PROCESSOR_GENERIC32, f32_patt will be used.
996 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 997 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
998 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc 999 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
68339fdf 1000 PROCESSOR_AMDFAM10, and PROCESSOR_BDVER1, alt_short_patt
69dd9865 1001 will be used.
ccc9c027 1002
76bc74dc 1003 When -mtune= isn't used, alt_long_patt will be used if
22109423 1004 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1005 be used.
ccc9c027
L		 1006
1007 When -march= or .arch is used, we can't use anything beyond
1008 cpu_arch_isa_flags. */
1009
1010 if (flag_code == CODE_16BIT)
1011 {
ccc9c027 1012 if (count > 8)
33fef721 1013 {
76bc74dc
L		 1014 memcpy (fragP->fr_literal + fragP->fr_fix,
1015 jump_31, count);
1016 /* Adjust jump offset. */
1017 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1018 }
76bc74dc
L		 1019 else
1020 memcpy (fragP->fr_literal + fragP->fr_fix,
1021 f16_patt[count - 1], count);
252b5132 1022 }
33fef721 1023 else
ccc9c027
L		 1024 {
1025 const char *const *patt = NULL;
1026
fbf3f584 1027 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1028 {
1029 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1030 switch (cpu_arch_tune)
1031 {
1032 case PROCESSOR_UNKNOWN:
1033 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1034 optimize with nops. */
1035 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
76bc74dc 1036 patt = alt_long_patt;
ccc9c027
L		 1037 else
1038 patt = f32_patt;
1039 break;
ccc9c027
L		 1040 case PROCESSOR_PENTIUMPRO:
1041 case PROCESSOR_PENTIUM4:
1042 case PROCESSOR_NOCONA:
ef05d495 1043 case PROCESSOR_CORE:
76bc74dc 1044 case PROCESSOR_CORE2:
bd5295b2 1045 case PROCESSOR_COREI7:
3632d14b 1046 case PROCESSOR_L1OM:
76bc74dc
L		 1047 case PROCESSOR_GENERIC64:
1048 patt = alt_long_patt;
1049 break;
ccc9c027
L		 1050 case PROCESSOR_K6:
1051 case PROCESSOR_ATHLON:
1052 case PROCESSOR_K8:
4eed87de 1053 case PROCESSOR_AMDFAM10:
68339fdf 1054 case PROCESSOR_BDVER1:
ccc9c027
L		 1055 patt = alt_short_patt;
1056 break;
76bc74dc 1057 case PROCESSOR_I386:
ccc9c027
L		 1058 case PROCESSOR_I486:
1059 case PROCESSOR_PENTIUM:
1060 case PROCESSOR_GENERIC32:
1061 patt = f32_patt;
1062 break;
4eed87de 1063 }
ccc9c027
L		 1064 }
1065 else
1066 {
fbf3f584 1067 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1068 {
1069 case PROCESSOR_UNKNOWN:
e6a14101 1070 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1071 PROCESSOR_UNKNOWN. */
1072 abort ();
1073 break;
1074
76bc74dc 1075 case PROCESSOR_I386:
ccc9c027
L		 1076 case PROCESSOR_I486:
1077 case PROCESSOR_PENTIUM:
ccc9c027
L		 1078 case PROCESSOR_K6:
1079 case PROCESSOR_ATHLON:
1080 case PROCESSOR_K8:
4eed87de 1081 case PROCESSOR_AMDFAM10:
68339fdf 1082 case PROCESSOR_BDVER1:
ccc9c027
L		 1083 case PROCESSOR_GENERIC32:
1084 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1085 with nops. */
1086 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1087 patt = alt_short_patt;
1088 else
1089 patt = f32_patt;
1090 break;
76bc74dc
L		 1091 case PROCESSOR_PENTIUMPRO:
1092 case PROCESSOR_PENTIUM4:
1093 case PROCESSOR_NOCONA:
1094 case PROCESSOR_CORE:
ef05d495 1095 case PROCESSOR_CORE2:
bd5295b2 1096 case PROCESSOR_COREI7:
3632d14b 1097 case PROCESSOR_L1OM:
22109423 1098 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
ccc9c027
L		 1099 patt = alt_long_patt;
1100 else
1101 patt = f32_patt;
1102 break;
1103 case PROCESSOR_GENERIC64:
76bc74dc 1104 patt = alt_long_patt;
ccc9c027 1105 break;
4eed87de 1106 }
ccc9c027
L		 1107 }
1108
76bc74dc
L		 1109 if (patt == f32_patt)
1110 {
1111 /* If the padding is less than 15 bytes, we use the normal
1112 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1113 its offset. */
1114 int limit;
76ba9986 1115
711eedef
L		 1116 /* For 64bit, the limit is 3 bytes. */
1117 if (flag_code == CODE_64BIT
1118 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1119 limit = 3;
1120 else
1121 limit = 15;
1122 if (count < limit)
76bc74dc
L		 1123 memcpy (fragP->fr_literal + fragP->fr_fix,
1124 patt[count - 1], count);
1125 else
1126 {
1127 memcpy (fragP->fr_literal + fragP->fr_fix,
1128 jump_31, count);
1129 /* Adjust jump offset. */
1130 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1131 }
1132 }
1133 else
1134 {
1135 /* Maximum length of an instruction is 15 byte. If the
1136 padding is greater than 15 bytes and we don't use jump,
1137 we have to break it into smaller pieces. */
1138 int padding = count;
1139 while (padding > 15)
1140 {
1141 padding -= 15;
1142 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1143 patt [14], 15);
1144 }
1145
1146 if (padding)
1147 memcpy (fragP->fr_literal + fragP->fr_fix,
1148 patt [padding - 1], padding);
1149 }
ccc9c027 1150 }
33fef721 1151 fragP->fr_var = count;
252b5132
RH		 1152}
1153
c6fb90c8 1154static INLINE int
0dfbf9d7 1155operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1156{
0dfbf9d7 1157 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1158 {
1159 case 3:
0dfbf9d7 1160 if (x->array[2])
c6fb90c8
L		 1161 return 0;
1162 case 2:
0dfbf9d7 1163 if (x->array[1])
c6fb90c8
L		 1164 return 0;
1165 case 1:
0dfbf9d7 1166 return !x->array[0];
c6fb90c8
L		 1167 default:
1168 abort ();
1169 }
40fb9820
L		 1170}
1171
c6fb90c8 1172static INLINE void
0dfbf9d7 1173operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1174{
0dfbf9d7 1175 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1176 {
1177 case 3:
0dfbf9d7 1178 x->array[2] = v;
c6fb90c8 1179 case 2:
0dfbf9d7 1180 x->array[1] = v;
c6fb90c8 1181 case 1:
0dfbf9d7 1182 x->array[0] = v;
c6fb90c8
L		 1183 break;
1184 default:
1185 abort ();
1186 }
1187}
40fb9820 1188
c6fb90c8 1189static INLINE int
0dfbf9d7
L		 1190operand_type_equal (const union i386_operand_type *x,
1191 const union i386_operand_type *y)
c6fb90c8 1192{
0dfbf9d7 1193 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1194 {
1195 case 3:
0dfbf9d7 1196 if (x->array[2] != y->array[2])
c6fb90c8
L		 1197 return 0;
1198 case 2:
0dfbf9d7 1199 if (x->array[1] != y->array[1])
c6fb90c8
L		 1200 return 0;
1201 case 1:
0dfbf9d7 1202 return x->array[0] == y->array[0];
c6fb90c8
L		 1203 break;
1204 default:
1205 abort ();
1206 }
1207}
40fb9820 1208
0dfbf9d7
L		 1209static INLINE int
1210cpu_flags_all_zero (const union i386_cpu_flags *x)
1211{
1212 switch (ARRAY_SIZE(x->array))
1213 {
1214 case 3:
1215 if (x->array[2])
1216 return 0;
1217 case 2:
1218 if (x->array[1])
1219 return 0;
1220 case 1:
1221 return !x->array[0];
1222 default:
1223 abort ();
1224 }
1225}
1226
1227static INLINE void
1228cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1229{
1230 switch (ARRAY_SIZE(x->array))
1231 {
1232 case 3:
1233 x->array[2] = v;
1234 case 2:
1235 x->array[1] = v;
1236 case 1:
1237 x->array[0] = v;
1238 break;
1239 default:
1240 abort ();
1241 }
1242}
1243
1244static INLINE int
1245cpu_flags_equal (const union i386_cpu_flags *x,
1246 const union i386_cpu_flags *y)
1247{
1248 switch (ARRAY_SIZE(x->array))
1249 {
1250 case 3:
1251 if (x->array[2] != y->array[2])
1252 return 0;
1253 case 2:
1254 if (x->array[1] != y->array[1])
1255 return 0;
1256 case 1:
1257 return x->array[0] == y->array[0];
1258 break;
1259 default:
1260 abort ();
1261 }
1262}
c6fb90c8
L		 1263
1264static INLINE int
1265cpu_flags_check_cpu64 (i386_cpu_flags f)
1266{
1267 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1268 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1269}
1270
c6fb90c8
L		 1271static INLINE i386_cpu_flags
1272cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1273{
c6fb90c8
L		 1274 switch (ARRAY_SIZE (x.array))
1275 {
1276 case 3:
1277 x.array [2] &= y.array [2];
1278 case 2:
1279 x.array [1] &= y.array [1];
1280 case 1:
1281 x.array [0] &= y.array [0];
1282 break;
1283 default:
1284 abort ();
1285 }
1286 return x;
1287}
40fb9820 1288
c6fb90c8
L		 1289static INLINE i386_cpu_flags
1290cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1291{
c6fb90c8 1292 switch (ARRAY_SIZE (x.array))
40fb9820 1293 {
c6fb90c8
L		 1294 case 3:
1295 x.array [2] |= y.array [2];
1296 case 2:
1297 x.array [1] |= y.array [1];
1298 case 1:
1299 x.array [0] |= y.array [0];
40fb9820
L		 1300 break;
1301 default:
1302 abort ();
1303 }
40fb9820
L		 1304 return x;
1305}
1306
309d3373
JB		 1307static INLINE i386_cpu_flags
1308cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1309{
1310 switch (ARRAY_SIZE (x.array))
1311 {
1312 case 3:
1313 x.array [2] &= ~y.array [2];
1314 case 2:
1315 x.array [1] &= ~y.array [1];
1316 case 1:
1317 x.array [0] &= ~y.array [0];
1318 break;
1319 default:
1320 abort ();
1321 }
1322 return x;
1323}
1324
c0f3af97
L		 1325#define CPU_FLAGS_ARCH_MATCH 0x1
1326#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1327#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1328#define CPU_FLAGS_PCLMUL_MATCH 0x8
1329#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1330
a5ff0eb2 1331#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1332 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1333 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1334#define CPU_FLAGS_PERFECT_MATCH \
1335 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1336
1337/* Return CPU flags match bits. */
3629bb00 1338
40fb9820 1339static int
d3ce72d0 1340cpu_flags_match (const insn_template *t)
40fb9820 1341{
c0f3af97
L		 1342 i386_cpu_flags x = t->cpu_flags;
1343 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1344
1345 x.bitfield.cpu64 = 0;
1346 x.bitfield.cpuno64 = 0;
1347
0dfbf9d7 1348 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1349 {
1350 /* This instruction is available on all archs. */
1351 match |= CPU_FLAGS_32BIT_MATCH;
1352 }
3629bb00
L		 1353 else
1354 {
c0f3af97 1355 /* This instruction is available only on some archs. */
3629bb00
L		 1356 i386_cpu_flags cpu = cpu_arch_flags;
1357
1358 cpu.bitfield.cpu64 = 0;
1359 cpu.bitfield.cpuno64 = 0;
1360 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1361 if (!cpu_flags_all_zero (&cpu))
1362 {
a5ff0eb2
L		 1363 if (x.bitfield.cpuavx)
1364 {
ce2f5b3c 1365 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1366 if (cpu.bitfield.cpuavx)
1367 {
1368 /* Check SSE2AVX. */
1369 if (!t->opcode_modifier.sse2avx|| sse2avx)
1370 {
1371 match |= (CPU_FLAGS_ARCH_MATCH
1372 | CPU_FLAGS_AVX_MATCH);
1373 /* Check AES. */
1374 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1375 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1376 /* Check PCLMUL. */
1377 if (!x.bitfield.cpupclmul
1378 || cpu.bitfield.cpupclmul)
1379 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1380 }
1381 }
1382 else
1383 match |= CPU_FLAGS_ARCH_MATCH;
1384 }
1385 else
c0f3af97
L		 1386 match |= CPU_FLAGS_32BIT_MATCH;
1387 }
3629bb00 1388 }
c0f3af97 1389 return match;
40fb9820
L		 1390}
1391
c6fb90c8
L		 1392static INLINE i386_operand_type
1393operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1394{
c6fb90c8
L		 1395 switch (ARRAY_SIZE (x.array))
1396 {
1397 case 3:
1398 x.array [2] &= y.array [2];
1399 case 2:
1400 x.array [1] &= y.array [1];
1401 case 1:
1402 x.array [0] &= y.array [0];
1403 break;
1404 default:
1405 abort ();
1406 }
1407 return x;
40fb9820
L		 1408}
1409
c6fb90c8
L		 1410static INLINE i386_operand_type
1411operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1412{
c6fb90c8 1413 switch (ARRAY_SIZE (x.array))
40fb9820 1414 {
c6fb90c8
L		 1415 case 3:
1416 x.array [2] |= y.array [2];
1417 case 2:
1418 x.array [1] |= y.array [1];
1419 case 1:
1420 x.array [0] |= y.array [0];
40fb9820
L		 1421 break;
1422 default:
1423 abort ();
1424 }
c6fb90c8
L		 1425 return x;
1426}
40fb9820 1427
c6fb90c8
L		 1428static INLINE i386_operand_type
1429operand_type_xor (i386_operand_type x, i386_operand_type y)
1430{
1431 switch (ARRAY_SIZE (x.array))
1432 {
1433 case 3:
1434 x.array [2] ^= y.array [2];
1435 case 2:
1436 x.array [1] ^= y.array [1];
1437 case 1:
1438 x.array [0] ^= y.array [0];
1439 break;
1440 default:
1441 abort ();
1442 }
40fb9820
L		 1443 return x;
1444}
1445
1446static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1447static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1448static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1449static const i386_operand_type inoutportreg
1450 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1451static const i386_operand_type reg16_inoutportreg
1452 = OPERAND_TYPE_REG16_INOUTPORTREG;
1453static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1454static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1455static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1456static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1457static const i386_operand_type anydisp
1458 = OPERAND_TYPE_ANYDISP;
40fb9820 1459static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1460static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1461static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1462static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1463static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1464static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1465static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1466static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1467static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1468static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1469static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1470static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1471
1472enum operand_type
1473{
1474 reg,
40fb9820
L		 1475 imm,
1476 disp,
1477 anymem
1478};
1479
c6fb90c8 1480static INLINE int
40fb9820
L		 1481operand_type_check (i386_operand_type t, enum operand_type c)
1482{
1483 switch (c)
1484 {
1485 case reg:
1486 return (t.bitfield.reg8
1487 || t.bitfield.reg16
1488 || t.bitfield.reg32
1489 || t.bitfield.reg64);
1490
40fb9820
L		 1491 case imm:
1492 return (t.bitfield.imm8
1493 || t.bitfield.imm8s
1494 || t.bitfield.imm16
1495 || t.bitfield.imm32
1496 || t.bitfield.imm32s
1497 || t.bitfield.imm64);
1498
1499 case disp:
1500 return (t.bitfield.disp8
1501 || t.bitfield.disp16
1502 || t.bitfield.disp32
1503 || t.bitfield.disp32s
1504 || t.bitfield.disp64);
1505
1506 case anymem:
1507 return (t.bitfield.disp8
1508 || t.bitfield.disp16
1509 || t.bitfield.disp32
1510 || t.bitfield.disp32s
1511 || t.bitfield.disp64
1512 || t.bitfield.baseindex);
1513
1514 default:
1515 abort ();
1516 }
2cfe26b6
AM		 1517
1518 return 0;
40fb9820
L		 1519}
1520
5c07affc
L		 1521/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1522 operand J for instruction template T. */
1523
1524static INLINE int
d3ce72d0 1525match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1526{
1527 return !((i.types[j].bitfield.byte
1528 && !t->operand_types[j].bitfield.byte)
1529 || (i.types[j].bitfield.word
1530 && !t->operand_types[j].bitfield.word)
1531 || (i.types[j].bitfield.dword
1532 && !t->operand_types[j].bitfield.dword)
1533 || (i.types[j].bitfield.qword
1534 && !t->operand_types[j].bitfield.qword));
1535}
1536
1537/* Return 1 if there is no conflict in any size on operand J for
1538 instruction template T. */
1539
1540static INLINE int
d3ce72d0 1541match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1542{
1543 return (match_reg_size (t, j)
1544 && !((i.types[j].bitfield.unspecified
1545 && !t->operand_types[j].bitfield.unspecified)
1546 || (i.types[j].bitfield.fword
1547 && !t->operand_types[j].bitfield.fword)
1548 || (i.types[j].bitfield.tbyte
1549 && !t->operand_types[j].bitfield.tbyte)
1550 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1551 && !t->operand_types[j].bitfield.xmmword)
1552 || (i.types[j].bitfield.ymmword
1553 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1554}
1555
1556/* Return 1 if there is no size conflict on any operands for
1557 instruction template T. */
1558
1559static INLINE int
d3ce72d0 1560operand_size_match (const insn_template *t)
5c07affc
L		 1561{
1562 unsigned int j;
1563 int match = 1;
1564
1565 /* Don't check jump instructions. */
1566 if (t->opcode_modifier.jump
1567 || t->opcode_modifier.jumpbyte
1568 || t->opcode_modifier.jumpdword
1569 || t->opcode_modifier.jumpintersegment)
1570 return match;
1571
1572 /* Check memory and accumulator operand size. */
1573 for (j = 0; j < i.operands; j++)
1574 {
1575 if (t->operand_types[j].bitfield.anysize)
1576 continue;
1577
1578 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1579 {
1580 match = 0;
1581 break;
1582 }
1583
1584 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1585 {
1586 match = 0;
1587 break;
1588 }
1589 }
1590
891edac4 1591 if (match)
5c07affc 1592 return match;
891edac4
L		 1593 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1594 {
1595mismatch:
86e026a4 1596 i.error = operand_size_mismatch;
891edac4
L		 1597 return 0;
1598 }
5c07affc
L		 1599
1600 /* Check reverse. */
9c2799c2 1601 gas_assert (i.operands == 2);
5c07affc
L		 1602
1603 match = 1;
1604 for (j = 0; j < 2; j++)
1605 {
1606 if (t->operand_types[j].bitfield.acc
1607 && !match_reg_size (t, j ? 0 : 1))
891edac4 1608 goto mismatch;
5c07affc
L		 1609
1610 if (i.types[j].bitfield.mem
1611 && !match_mem_size (t, j ? 0 : 1))
891edac4 1612 goto mismatch;
5c07affc
L		 1613 }
1614
1615 return match;
1616}
1617
c6fb90c8 1618static INLINE int
40fb9820
L		 1619operand_type_match (i386_operand_type overlap,
1620 i386_operand_type given)
1621{
1622 i386_operand_type temp = overlap;
1623
1624 temp.bitfield.jumpabsolute = 0;
7d5e4556 1625 temp.bitfield.unspecified = 0;
5c07affc
L		 1626 temp.bitfield.byte = 0;
1627 temp.bitfield.word = 0;
1628 temp.bitfield.dword = 0;
1629 temp.bitfield.fword = 0;
1630 temp.bitfield.qword = 0;
1631 temp.bitfield.tbyte = 0;
1632 temp.bitfield.xmmword = 0;
c0f3af97 1633 temp.bitfield.ymmword = 0;
0dfbf9d7 1634 if (operand_type_all_zero (&temp))
891edac4 1635 goto mismatch;
40fb9820 1636
891edac4
L		 1637 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1638 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1639 return 1;
1640
1641mismatch:
a65babc9 1642 i.error = operand_type_mismatch;
891edac4 1643 return 0;
40fb9820
L		 1644}
1645
7d5e4556 1646/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1647 unless the expected operand type register overlap is null.
1648 Note that Acc in a template matches every size of reg. */
1649
c6fb90c8 1650static INLINE int
40fb9820
L		 1651operand_type_register_match (i386_operand_type m0,
1652 i386_operand_type g0,
1653 i386_operand_type t0,
1654 i386_operand_type m1,
1655 i386_operand_type g1,
1656 i386_operand_type t1)
1657{
1658 if (!operand_type_check (g0, reg))
1659 return 1;
1660
1661 if (!operand_type_check (g1, reg))
1662 return 1;
1663
1664 if (g0.bitfield.reg8 == g1.bitfield.reg8
1665 && g0.bitfield.reg16 == g1.bitfield.reg16
1666 && g0.bitfield.reg32 == g1.bitfield.reg32
1667 && g0.bitfield.reg64 == g1.bitfield.reg64)
1668 return 1;
1669
1670 if (m0.bitfield.acc)
1671 {
1672 t0.bitfield.reg8 = 1;
1673 t0.bitfield.reg16 = 1;
1674 t0.bitfield.reg32 = 1;
1675 t0.bitfield.reg64 = 1;
1676 }
1677
1678 if (m1.bitfield.acc)
1679 {
1680 t1.bitfield.reg8 = 1;
1681 t1.bitfield.reg16 = 1;
1682 t1.bitfield.reg32 = 1;
1683 t1.bitfield.reg64 = 1;
1684 }
1685
891edac4
L		 1686 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1687 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1688 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1689 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1690 return 1;
1691
a65babc9 1692 i.error = register_type_mismatch;
891edac4
L		 1693
1694 return 0;
40fb9820
L		 1695}
1696
252b5132 1697static INLINE unsigned int
40fb9820 1698mode_from_disp_size (i386_operand_type t)
252b5132 1699{
40fb9820
L		 1700 if (t.bitfield.disp8)
1701 return 1;
1702 else if (t.bitfield.disp16
1703 || t.bitfield.disp32
1704 || t.bitfield.disp32s)
1705 return 2;
1706 else
1707 return 0;
252b5132
RH		 1708}
1709
1710static INLINE int
e3bb37b5 1711fits_in_signed_byte (offsetT num)
252b5132
RH		 1712{
1713 return (num >= -128) && (num <= 127);
47926f60 1714}
252b5132
RH		 1715
1716static INLINE int
e3bb37b5 1717fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1718{
1719 return (num & 0xff) == num;
47926f60 1720}
252b5132
RH		 1721
1722static INLINE int
e3bb37b5 1723fits_in_unsigned_word (offsetT num)
252b5132
RH		 1724{
1725 return (num & 0xffff) == num;
47926f60 1726}
252b5132
RH		 1727
1728static INLINE int
e3bb37b5 1729fits_in_signed_word (offsetT num)
252b5132
RH		 1730{
1731 return (-32768 <= num) && (num <= 32767);
47926f60 1732}
2a962e6d 1733
3e73aa7c 1734static INLINE int
e3bb37b5 1735fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1736{
1737#ifndef BFD64
1738 return 1;
1739#else
1740 return (!(((offsetT) -1 << 31) & num)
1741 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1742#endif
1743} /* fits_in_signed_long() */
2a962e6d 1744
3e73aa7c 1745static INLINE int
e3bb37b5 1746fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1747{
1748#ifndef BFD64
1749 return 1;
1750#else
1751 return (num & (((offsetT) 2 << 31) - 1)) == num;
1752#endif
1753} /* fits_in_unsigned_long() */
252b5132 1754
a683cc34
SP		 1755static INLINE int
1756fits_in_imm4 (offsetT num)
1757{
1758 return (num & 0xf) == num;
1759}
1760
40fb9820 1761static i386_operand_type
e3bb37b5 1762smallest_imm_type (offsetT num)
252b5132 1763{
40fb9820 1764 i386_operand_type t;
7ab9ffdd 1765
0dfbf9d7 1766 operand_type_set (&t, 0);
40fb9820
L		 1767 t.bitfield.imm64 = 1;
1768
1769 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1770 {
1771 /* This code is disabled on the 486 because all the Imm1 forms
1772 in the opcode table are slower on the i486. They're the
1773 versions with the implicitly specified single-position
1774 displacement, which has another syntax if you really want to
1775 use that form. */
40fb9820
L		 1776 t.bitfield.imm1 = 1;
1777 t.bitfield.imm8 = 1;
1778 t.bitfield.imm8s = 1;
1779 t.bitfield.imm16 = 1;
1780 t.bitfield.imm32 = 1;
1781 t.bitfield.imm32s = 1;
1782 }
1783 else if (fits_in_signed_byte (num))
1784 {
1785 t.bitfield.imm8 = 1;
1786 t.bitfield.imm8s = 1;
1787 t.bitfield.imm16 = 1;
1788 t.bitfield.imm32 = 1;
1789 t.bitfield.imm32s = 1;
1790 }
1791 else if (fits_in_unsigned_byte (num))
1792 {
1793 t.bitfield.imm8 = 1;
1794 t.bitfield.imm16 = 1;
1795 t.bitfield.imm32 = 1;
1796 t.bitfield.imm32s = 1;
1797 }
1798 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1799 {
1800 t.bitfield.imm16 = 1;
1801 t.bitfield.imm32 = 1;
1802 t.bitfield.imm32s = 1;
1803 }
1804 else if (fits_in_signed_long (num))
1805 {
1806 t.bitfield.imm32 = 1;
1807 t.bitfield.imm32s = 1;
1808 }
1809 else if (fits_in_unsigned_long (num))
1810 t.bitfield.imm32 = 1;
1811
1812 return t;
47926f60 1813}
252b5132 1814
847f7ad4 1815static offsetT
e3bb37b5 1816offset_in_range (offsetT val, int size)
847f7ad4 1817{
508866be 1818 addressT mask;
ba2adb93 1819
847f7ad4
AM		 1820 switch (size)
1821 {
508866be
L		 1822 case 1: mask = ((addressT) 1 << 8) - 1; break;
1823 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1824 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1825#ifdef BFD64
1826 case 8: mask = ((addressT) 2 << 63) - 1; break;
1827#endif
47926f60 1828 default: abort ();
847f7ad4
AM		 1829 }
1830
9de868bf
L		 1831#ifdef BFD64
1832 /* If BFD64, sign extend val for 32bit address mode. */
1833 if (flag_code != CODE_64BIT
1834 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 1835 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1836 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 1837#endif
ba2adb93 1838
47926f60 1839 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1840 {
1841 char buf1[40], buf2[40];
1842
1843 sprint_value (buf1, val);
1844 sprint_value (buf2, val & mask);
1845 as_warn (_("%s shortened to %s"), buf1, buf2);
1846 }
1847 return val & mask;
1848}
1849
c32fa91d
L		 1850enum PREFIX_GROUP
1851{
1852 PREFIX_EXIST = 0,
1853 PREFIX_LOCK,
1854 PREFIX_REP,
1855 PREFIX_OTHER
1856};
1857
1858/* Returns
1859 a. PREFIX_EXIST if attempting to add a prefix where one from the
1860 same class already exists.
1861 b. PREFIX_LOCK if lock prefix is added.
1862 c. PREFIX_REP if rep/repne prefix is added.
1863 d. PREFIX_OTHER if other prefix is added.
1864 */
1865
1866static enum PREFIX_GROUP
e3bb37b5 1867add_prefix (unsigned int prefix)
252b5132 1868{
c32fa91d 1869 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 1870 unsigned int q;
252b5132 1871
29b0f896
AM		 1872 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1873 && flag_code == CODE_64BIT)
b1905489 1874 {
161a04f6
L		 1875 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1876 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1877 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 1878 ret = PREFIX_EXIST;
b1905489
JB		 1879 q = REX_PREFIX;
1880 }
3e73aa7c 1881 else
b1905489
JB		 1882 {
1883 switch (prefix)
1884 {
1885 default:
1886 abort ();
1887
1888 case CS_PREFIX_OPCODE:
1889 case DS_PREFIX_OPCODE:
1890 case ES_PREFIX_OPCODE:
1891 case FS_PREFIX_OPCODE:
1892 case GS_PREFIX_OPCODE:
1893 case SS_PREFIX_OPCODE:
1894 q = SEG_PREFIX;
1895 break;
1896
1897 case REPNE_PREFIX_OPCODE:
1898 case REPE_PREFIX_OPCODE:
c32fa91d
L		 1899 q = REP_PREFIX;
1900 ret = PREFIX_REP;
1901 break;
1902
b1905489 1903 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 1904 q = LOCK_PREFIX;
1905 ret = PREFIX_LOCK;
b1905489
JB		 1906 break;
1907
1908 case FWAIT_OPCODE:
1909 q = WAIT_PREFIX;
1910 break;
1911
1912 case ADDR_PREFIX_OPCODE:
1913 q = ADDR_PREFIX;
1914 break;
1915
1916 case DATA_PREFIX_OPCODE:
1917 q = DATA_PREFIX;
1918 break;
1919 }
1920 if (i.prefix[q] != 0)
c32fa91d 1921 ret = PREFIX_EXIST;
b1905489 1922 }
252b5132 1923
b1905489 1924 if (ret)
252b5132 1925 {
b1905489
JB		 1926 if (!i.prefix[q])
1927 ++i.prefixes;
1928 i.prefix[q] |= prefix;
252b5132 1929 }
b1905489
JB		 1930 else
1931 as_bad (_("same type of prefix used twice"));
252b5132 1932
252b5132
RH		 1933 return ret;
1934}
1935
1936static void
78f12dd3 1937update_code_flag (int value, int check)
eecb386c 1938{
78f12dd3
L		 1939 PRINTF_LIKE ((*as_error));
1940
1e9cc1c2 1941 flag_code = (enum flag_code) value;
40fb9820
L		 1942 if (flag_code == CODE_64BIT)
1943 {
1944 cpu_arch_flags.bitfield.cpu64 = 1;
1945 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1946 }
1947 else
1948 {
1949 cpu_arch_flags.bitfield.cpu64 = 0;
1950 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1951 }
1952 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 1953 {
78f12dd3
L		 1954 if (check)
1955 as_error = as_fatal;
1956 else
1957 as_error = as_bad;
1958 (*as_error) (_("64bit mode not supported on `%s'."),
1959 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 1960 }
40fb9820 1961 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 1962 {
78f12dd3
L		 1963 if (check)
1964 as_error = as_fatal;
1965 else
1966 as_error = as_bad;
1967 (*as_error) (_("32bit mode not supported on `%s'."),
1968 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 1969 }
eecb386c
AM		 1970 stackop_size = '\0';
1971}
1972
78f12dd3
L		 1973static void
1974set_code_flag (int value)
1975{
1976 update_code_flag (value, 0);
1977}
1978
eecb386c 1979static void
e3bb37b5 1980set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1981{
1e9cc1c2 1982 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 1983 if (flag_code != CODE_16BIT)
1984 abort ();
1985 cpu_arch_flags.bitfield.cpu64 = 0;
1986 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 1987 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1988}
1989
1990static void
e3bb37b5 1991set_intel_syntax (int syntax_flag)
252b5132
RH		 1992{
1993 /* Find out if register prefixing is specified. */
1994 int ask_naked_reg = 0;
1995
1996 SKIP_WHITESPACE ();
29b0f896 1997 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1998 {
1999 char *string = input_line_pointer;
2000 int e = get_symbol_end ();
2001
47926f60 2002 if (strcmp (string, "prefix") == 0)
252b5132 2003 ask_naked_reg = 1;
47926f60 2004 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2005 ask_naked_reg = -1;
2006 else
d0b47220 2007 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 2008 *input_line_pointer = e;
2009 }
2010 demand_empty_rest_of_line ();
c3332e24 2011
252b5132
RH		 2012 intel_syntax = syntax_flag;
2013
2014 if (ask_naked_reg == 0)
f86103b7
AM		 2015 allow_naked_reg = (intel_syntax
2016 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2017 else
2018 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2019
ee86248c 2020 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2021
e4a3b5a4 2022 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2023 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2024 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2025}
2026
1efbbeb4
L		 2027static void
2028set_intel_mnemonic (int mnemonic_flag)
2029{
e1d4d893 2030 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2031}
2032
db51cc60
L		 2033static void
2034set_allow_index_reg (int flag)
2035{
2036 allow_index_reg = flag;
2037}
2038
cb19c032
L		 2039static void
2040set_sse_check (int dummy ATTRIBUTE_UNUSED)
2041{
2042 SKIP_WHITESPACE ();
2043
2044 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2045 {
2046 char *string = input_line_pointer;
2047 int e = get_symbol_end ();
2048
2049 if (strcmp (string, "none") == 0)
2050 sse_check = sse_check_none;
2051 else if (strcmp (string, "warning") == 0)
2052 sse_check = sse_check_warning;
2053 else if (strcmp (string, "error") == 0)
2054 sse_check = sse_check_error;
2055 else
2056 as_bad (_("bad argument to sse_check directive."));
2057 *input_line_pointer = e;
2058 }
2059 else
2060 as_bad (_("missing argument for sse_check directive"));
2061
2062 demand_empty_rest_of_line ();
2063}
2064
8a9036a4
L		 2065static void
2066check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2067 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2068{
2069#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2070 static const char *arch;
2071
2072 /* Intel LIOM is only supported on ELF. */
2073 if (!IS_ELF)
2074 return;
2075
2076 if (!arch)
2077 {
2078 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2079 use default_arch. */
2080 arch = cpu_arch_name;
2081 if (!arch)
2082 arch = default_arch;
2083 }
2084
3632d14b 2085 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2086 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2087 || new_flag.bitfield.cpul1om)
8a9036a4 2088 return;
76ba9986 2089
8a9036a4
L		 2090 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2091#endif
2092}
2093
e413e4e9 2094static void
e3bb37b5 2095set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2096{
47926f60 2097 SKIP_WHITESPACE ();
e413e4e9 2098
29b0f896 2099 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2100 {
2101 char *string = input_line_pointer;
2102 int e = get_symbol_end ();
91d6fa6a 2103 unsigned int j;
40fb9820 2104 i386_cpu_flags flags;
e413e4e9 2105
91d6fa6a 2106 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2107 {
91d6fa6a 2108 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2109 {
91d6fa6a 2110 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2111
5c6af06e
JB		 2112 if (*string != '.')
2113 {
91d6fa6a 2114 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2115 cpu_sub_arch_name = NULL;
91d6fa6a 2116 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2117 if (flag_code == CODE_64BIT)
2118 {
2119 cpu_arch_flags.bitfield.cpu64 = 1;
2120 cpu_arch_flags.bitfield.cpuno64 = 0;
2121 }
2122 else
2123 {
2124 cpu_arch_flags.bitfield.cpu64 = 0;
2125 cpu_arch_flags.bitfield.cpuno64 = 1;
2126 }
91d6fa6a
NC		 2127 cpu_arch_isa = cpu_arch[j].type;
2128 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2129 if (!cpu_arch_tune_set)
2130 {
2131 cpu_arch_tune = cpu_arch_isa;
2132 cpu_arch_tune_flags = cpu_arch_isa_flags;
2133 }
5c6af06e
JB		 2134 break;
2135 }
40fb9820 2136
22109423 2137 if (!cpu_arch[j].negated)
309d3373 2138 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2139 cpu_arch[j].flags);
309d3373
JB		 2140 else
2141 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 2142 cpu_arch[j].flags);
0dfbf9d7 2143 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2144 {
6305a203
L		 2145 if (cpu_sub_arch_name)
2146 {
2147 char *name = cpu_sub_arch_name;
2148 cpu_sub_arch_name = concat (name,
91d6fa6a 2149 cpu_arch[j].name,
1bf57e9f 2150 (const char *) NULL);
6305a203
L		 2151 free (name);
2152 }
2153 else
91d6fa6a 2154 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2155 cpu_arch_flags = flags;
5c6af06e
JB		 2156 }
2157 *input_line_pointer = e;
2158 demand_empty_rest_of_line ();
2159 return;
e413e4e9
AM		 2160 }
2161 }
91d6fa6a 2162 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2163 as_bad (_("no such architecture: `%s'"), string);
2164
2165 *input_line_pointer = e;
2166 }
2167 else
2168 as_bad (_("missing cpu architecture"));
2169
fddf5b5b
AM		 2170 no_cond_jump_promotion = 0;
2171 if (*input_line_pointer == ','
29b0f896 2172 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2173 {
2174 char *string = ++input_line_pointer;
2175 int e = get_symbol_end ();
2176
2177 if (strcmp (string, "nojumps") == 0)
2178 no_cond_jump_promotion = 1;
2179 else if (strcmp (string, "jumps") == 0)
2180 ;
2181 else
2182 as_bad (_("no such architecture modifier: `%s'"), string);
2183
2184 *input_line_pointer = e;
2185 }
2186
e413e4e9
AM		 2187 demand_empty_rest_of_line ();
2188}
2189
8a9036a4
L		 2190enum bfd_architecture
2191i386_arch (void)
2192{
3632d14b 2193 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2194 {
2195 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2196 || flag_code != CODE_64BIT)
2197 as_fatal (_("Intel L1OM is 64bit ELF only"));
2198 return bfd_arch_l1om;
2199 }
2200 else
2201 return bfd_arch_i386;
2202}
2203
b9d79e03
JH		 2204unsigned long
2205i386_mach ()
2206{
2207 if (!strcmp (default_arch, "x86_64"))
8a9036a4 2208 {
3632d14b 2209 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2210 {
2211 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2212 as_fatal (_("Intel L1OM is 64bit ELF only"));
2213 return bfd_mach_l1om;
2214 }
2215 else
2216 return bfd_mach_x86_64;
2217 }
b9d79e03
JH		 2218 else if (!strcmp (default_arch, "i386"))
2219 return bfd_mach_i386_i386;
2220 else
2221 as_fatal (_("Unknown architecture"));
2222}
b9d79e03 2223\f
252b5132
RH		 2224void
2225md_begin ()
2226{
2227 const char *hash_err;
2228
47926f60 2229 /* Initialize op_hash hash table. */
252b5132
RH		 2230 op_hash = hash_new ();
2231
2232 {
d3ce72d0 2233 const insn_template *optab;
29b0f896 2234 templates *core_optab;
252b5132 2235
47926f60
KH		 2236 /* Setup for loop. */
2237 optab = i386_optab;
252b5132
RH		 2238 core_optab = (templates *) xmalloc (sizeof (templates));
2239 core_optab->start = optab;
2240
2241 while (1)
2242 {
2243 ++optab;
2244 if (optab->name == NULL
2245 || strcmp (optab->name, (optab - 1)->name) != 0)
2246 {
2247 /* different name --> ship out current template list;
47926f60 2248 add to hash table; & begin anew. */
252b5132
RH		 2249 core_optab->end = optab;
2250 hash_err = hash_insert (op_hash,
2251 (optab - 1)->name,
5a49b8ac 2252 (void *) core_optab);
252b5132
RH		 2253 if (hash_err)
2254 {
252b5132
RH		 2255 as_fatal (_("Internal Error: Can't hash %s: %s"),
2256 (optab - 1)->name,
2257 hash_err);
2258 }
2259 if (optab->name == NULL)
2260 break;
2261 core_optab = (templates *) xmalloc (sizeof (templates));
2262 core_optab->start = optab;
2263 }
2264 }
2265 }
2266
47926f60 2267 /* Initialize reg_hash hash table. */
252b5132
RH		 2268 reg_hash = hash_new ();
2269 {
29b0f896 2270 const reg_entry *regtab;
c3fe08fa 2271 unsigned int regtab_size = i386_regtab_size;
252b5132 2272
c3fe08fa 2273 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2274 {
5a49b8ac 2275 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2276 if (hash_err)
3e73aa7c
JH		 2277 as_fatal (_("Internal Error: Can't hash %s: %s"),
2278 regtab->reg_name,
2279 hash_err);
252b5132
RH		 2280 }
2281 }
2282
47926f60 2283 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2284 {
29b0f896
AM		 2285 int c;
2286 char *p;
252b5132
RH		 2287
2288 for (c = 0; c < 256; c++)
2289 {
3882b010 2290 if (ISDIGIT (c))
252b5132
RH		 2291 {
2292 digit_chars[c] = c;
2293 mnemonic_chars[c] = c;
2294 register_chars[c] = c;
2295 operand_chars[c] = c;
2296 }
3882b010 2297 else if (ISLOWER (c))
252b5132
RH		 2298 {
2299 mnemonic_chars[c] = c;
2300 register_chars[c] = c;
2301 operand_chars[c] = c;
2302 }
3882b010 2303 else if (ISUPPER (c))
252b5132 2304 {
3882b010 2305 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2306 register_chars[c] = mnemonic_chars[c];
2307 operand_chars[c] = c;
2308 }
2309
3882b010 2310 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2311 identifier_chars[c] = c;
2312 else if (c >= 128)
2313 {
2314 identifier_chars[c] = c;
2315 operand_chars[c] = c;
2316 }
2317 }
2318
2319#ifdef LEX_AT
2320 identifier_chars['@'] = '@';
32137342
NC		 2321#endif
2322#ifdef LEX_QM
2323 identifier_chars['?'] = '?';
2324 operand_chars['?'] = '?';
252b5132 2325#endif
252b5132 2326 digit_chars['-'] = '-';
c0f3af97 2327 mnemonic_chars['_'] = '_';
791fe849 2328 mnemonic_chars['-'] = '-';
0003779b 2329 mnemonic_chars['.'] = '.';
252b5132
RH		 2330 identifier_chars['_'] = '_';
2331 identifier_chars['.'] = '.';
2332
2333 for (p = operand_special_chars; *p != '\0'; p++)
2334 operand_chars[(unsigned char) *p] = *p;
2335 }
2336
2337#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2338 if (IS_ELF)
252b5132
RH		 2339 {
2340 record_alignment (text_section, 2);
2341 record_alignment (data_section, 2);
2342 record_alignment (bss_section, 2);
2343 }
2344#endif
a4447b93
RH		 2345
2346 if (flag_code == CODE_64BIT)
2347 {
2348 x86_dwarf2_return_column = 16;
2349 x86_cie_data_alignment = -8;
2350 }
2351 else
2352 {
2353 x86_dwarf2_return_column = 8;
2354 x86_cie_data_alignment = -4;
2355 }
252b5132
RH		 2356}
2357
2358void
e3bb37b5 2359i386_print_statistics (FILE *file)
252b5132
RH		 2360{
2361 hash_print_statistics (file, "i386 opcode", op_hash);
2362 hash_print_statistics (file, "i386 register", reg_hash);
2363}
2364\f
252b5132
RH		 2365#ifdef DEBUG386
2366
ce8a8b2f 2367/* Debugging routines for md_assemble. */
d3ce72d0 2368static void pte (insn_template *);
40fb9820 2369static void pt (i386_operand_type);
e3bb37b5
L		 2370static void pe (expressionS *);
2371static void ps (symbolS *);
252b5132
RH		 2372
2373static void
e3bb37b5 2374pi (char *line, i386_insn *x)
252b5132 2375{
09137c09 2376 unsigned int j;
252b5132
RH		 2377
2378 fprintf (stdout, "%s: template ", line);
2379 pte (&x->tm);
09f131f2
JH		 2380 fprintf (stdout, " address: base %s index %s scale %x\n",
2381 x->base_reg ? x->base_reg->reg_name : "none",
2382 x->index_reg ? x->index_reg->reg_name : "none",
2383 x->log2_scale_factor);
2384 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2385 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2386 fprintf (stdout, " sib: base %x index %x scale %x\n",
2387 x->sib.base, x->sib.index, x->sib.scale);
2388 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2389 (x->rex & REX_W) != 0,
2390 (x->rex & REX_R) != 0,
2391 (x->rex & REX_X) != 0,
2392 (x->rex & REX_B) != 0);
09137c09 2393 for (j = 0; j < x->operands; j++)
252b5132 2394 {
09137c09
SP		 2395 fprintf (stdout, " #%d: ", j + 1);
2396 pt (x->types[j]);
252b5132 2397 fprintf (stdout, "\n");
09137c09
SP		 2398 if (x->types[j].bitfield.reg8
2399 || x->types[j].bitfield.reg16
2400 || x->types[j].bitfield.reg32
2401 || x->types[j].bitfield.reg64
2402 || x->types[j].bitfield.regmmx
2403 || x->types[j].bitfield.regxmm
2404 || x->types[j].bitfield.regymm
2405 || x->types[j].bitfield.sreg2
2406 || x->types[j].bitfield.sreg3
2407 || x->types[j].bitfield.control
2408 || x->types[j].bitfield.debug
2409 || x->types[j].bitfield.test)
2410 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2411 if (operand_type_check (x->types[j], imm))
2412 pe (x->op[j].imms);
2413 if (operand_type_check (x->types[j], disp))
2414 pe (x->op[j].disps);
252b5132
RH		 2415 }
2416}
2417
2418static void
d3ce72d0 2419pte (insn_template *t)
252b5132 2420{
09137c09 2421 unsigned int j;
252b5132 2422 fprintf (stdout, " %d operands ", t->operands);
47926f60 2423 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2424 if (t->extension_opcode != None)
2425 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2426 if (t->opcode_modifier.d)
252b5132 2427 fprintf (stdout, "D");
40fb9820 2428 if (t->opcode_modifier.w)
252b5132
RH		 2429 fprintf (stdout, "W");
2430 fprintf (stdout, "\n");
09137c09 2431 for (j = 0; j < t->operands; j++)
252b5132 2432 {
09137c09
SP		 2433 fprintf (stdout, " #%d type ", j + 1);
2434 pt (t->operand_types[j]);
252b5132
RH		 2435 fprintf (stdout, "\n");
2436 }
2437}
2438
2439static void
e3bb37b5 2440pe (expressionS *e)
252b5132 2441{
24eab124 2442 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2443 fprintf (stdout, " add_number %ld (%lx)\n",
2444 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2445 if (e->X_add_symbol)
2446 {
2447 fprintf (stdout, " add_symbol ");
2448 ps (e->X_add_symbol);
2449 fprintf (stdout, "\n");
2450 }
2451 if (e->X_op_symbol)
2452 {
2453 fprintf (stdout, " op_symbol ");
2454 ps (e->X_op_symbol);
2455 fprintf (stdout, "\n");
2456 }
2457}
2458
2459static void
e3bb37b5 2460ps (symbolS *s)
252b5132
RH		 2461{
2462 fprintf (stdout, "%s type %s%s",
2463 S_GET_NAME (s),
2464 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2465 segment_name (S_GET_SEGMENT (s)));
2466}
2467
7b81dfbb 2468static struct type_name
252b5132 2469 {
40fb9820
L		 2470 i386_operand_type mask;
2471 const char *name;
252b5132 2472 }
7b81dfbb 2473const type_names[] =
252b5132 2474{
40fb9820
L		 2475 { OPERAND_TYPE_REG8, "r8" },
2476 { OPERAND_TYPE_REG16, "r16" },
2477 { OPERAND_TYPE_REG32, "r32" },
2478 { OPERAND_TYPE_REG64, "r64" },
2479 { OPERAND_TYPE_IMM8, "i8" },
2480 { OPERAND_TYPE_IMM8, "i8s" },
2481 { OPERAND_TYPE_IMM16, "i16" },
2482 { OPERAND_TYPE_IMM32, "i32" },
2483 { OPERAND_TYPE_IMM32S, "i32s" },
2484 { OPERAND_TYPE_IMM64, "i64" },
2485 { OPERAND_TYPE_IMM1, "i1" },
2486 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2487 { OPERAND_TYPE_DISP8, "d8" },
2488 { OPERAND_TYPE_DISP16, "d16" },
2489 { OPERAND_TYPE_DISP32, "d32" },
2490 { OPERAND_TYPE_DISP32S, "d32s" },
2491 { OPERAND_TYPE_DISP64, "d64" },
2492 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2493 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2494 { OPERAND_TYPE_CONTROL, "control reg" },
2495 { OPERAND_TYPE_TEST, "test reg" },
2496 { OPERAND_TYPE_DEBUG, "debug reg" },
2497 { OPERAND_TYPE_FLOATREG, "FReg" },
2498 { OPERAND_TYPE_FLOATACC, "FAcc" },
2499 { OPERAND_TYPE_SREG2, "SReg2" },
2500 { OPERAND_TYPE_SREG3, "SReg3" },
2501 { OPERAND_TYPE_ACC, "Acc" },
2502 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2503 { OPERAND_TYPE_REGMMX, "rMMX" },
2504 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2505 { OPERAND_TYPE_REGYMM, "rYMM" },
40fb9820 2506 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2507};
2508
2509static void
40fb9820 2510pt (i386_operand_type t)
252b5132 2511{
40fb9820 2512 unsigned int j;
c6fb90c8 2513 i386_operand_type a;
252b5132 2514
40fb9820 2515 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2516 {
2517 a = operand_type_and (t, type_names[j].mask);
0349dc08 2518 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2519 fprintf (stdout, "%s, ", type_names[j].name);
2520 }
252b5132
RH		 2521 fflush (stdout);
2522}
2523
2524#endif /* DEBUG386 */
2525\f
252b5132 2526static bfd_reloc_code_real_type
3956db08 2527reloc (unsigned int size,
64e74474
AM		 2528 int pcrel,
2529 int sign,
2530 bfd_reloc_code_real_type other)
252b5132 2531{
47926f60 2532 if (other != NO_RELOC)
3956db08 2533 {
91d6fa6a 2534 reloc_howto_type *rel;
3956db08
JB		 2535
2536 if (size == 8)
2537 switch (other)
2538 {
64e74474
AM		 2539 case BFD_RELOC_X86_64_GOT32:
2540 return BFD_RELOC_X86_64_GOT64;
2541 break;
2542 case BFD_RELOC_X86_64_PLTOFF64:
2543 return BFD_RELOC_X86_64_PLTOFF64;
2544 break;
2545 case BFD_RELOC_X86_64_GOTPC32:
2546 other = BFD_RELOC_X86_64_GOTPC64;
2547 break;
2548 case BFD_RELOC_X86_64_GOTPCREL:
2549 other = BFD_RELOC_X86_64_GOTPCREL64;
2550 break;
2551 case BFD_RELOC_X86_64_TPOFF32:
2552 other = BFD_RELOC_X86_64_TPOFF64;
2553 break;
2554 case BFD_RELOC_X86_64_DTPOFF32:
2555 other = BFD_RELOC_X86_64_DTPOFF64;
2556 break;
2557 default:
2558 break;
3956db08 2559 }
e05278af
JB		 2560
2561 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2562 if (size == 4 && flag_code != CODE_64BIT)
2563 sign = -1;
2564
91d6fa6a
NC		 2565 rel = bfd_reloc_type_lookup (stdoutput, other);
2566 if (!rel)
3956db08 2567 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2568 else if (size != bfd_get_reloc_size (rel))
3956db08 2569 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2570 bfd_get_reloc_size (rel),
3956db08 2571 size);
91d6fa6a 2572 else if (pcrel && !rel->pc_relative)
3956db08 2573 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2574 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2575 && !sign)
91d6fa6a 2576 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2577 && sign > 0))
3956db08
JB		 2578 as_bad (_("relocated field and relocation type differ in signedness"));
2579 else
2580 return other;
2581 return NO_RELOC;
2582 }
252b5132
RH		 2583
2584 if (pcrel)
2585 {
3e73aa7c 2586 if (!sign)
3956db08 2587 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2588 switch (size)
2589 {
2590 case 1: return BFD_RELOC_8_PCREL;
2591 case 2: return BFD_RELOC_16_PCREL;
2592 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2593 case 8: return BFD_RELOC_64_PCREL;
252b5132 2594 }
3956db08 2595 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2596 }
2597 else
2598 {
3956db08 2599 if (sign > 0)
e5cb08ac 2600 switch (size)
3e73aa7c
JH		 2601 {
2602 case 4: return BFD_RELOC_X86_64_32S;
2603 }
2604 else
2605 switch (size)
2606 {
2607 case 1: return BFD_RELOC_8;
2608 case 2: return BFD_RELOC_16;
2609 case 4: return BFD_RELOC_32;
2610 case 8: return BFD_RELOC_64;
2611 }
3956db08
JB		 2612 as_bad (_("cannot do %s %u byte relocation"),
2613 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2614 }
2615
0cc9e1d3 2616 return NO_RELOC;
252b5132
RH		 2617}
2618
47926f60
KH		 2619/* Here we decide which fixups can be adjusted to make them relative to
2620 the beginning of the section instead of the symbol. Basically we need
2621 to make sure that the dynamic relocations are done correctly, so in
2622 some cases we force the original symbol to be used. */
2623
252b5132 2624int
e3bb37b5 2625tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2626{
6d249963 2627#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2628 if (!IS_ELF)
31312f95
AM		 2629 return 1;
2630
a161fe53
AM		 2631 /* Don't adjust pc-relative references to merge sections in 64-bit
2632 mode. */
2633 if (use_rela_relocations
2634 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2635 && fixP->fx_pcrel)
252b5132 2636 return 0;
31312f95 2637
8d01d9a9
AJ		 2638 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2639 and changed later by validate_fix. */
2640 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2641 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2642 return 0;
2643
ce8a8b2f 2644 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2645 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2646 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2647 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2648 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2649 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2650 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2651 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2652 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2653 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2654 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2655 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2656 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2657 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2658 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2659 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2660 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2661 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2662 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2663 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2664 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2665 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2666 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2667 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2668 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2669 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2670 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2671 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2672 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2673 return 0;
31312f95 2674#endif
252b5132
RH		 2675 return 1;
2676}
252b5132 2677
b4cac588 2678static int
e3bb37b5 2679intel_float_operand (const char *mnemonic)
252b5132 2680{
9306ca4a
JB		 2681 /* Note that the value returned is meaningful only for opcodes with (memory)
2682 operands, hence the code here is free to improperly handle opcodes that
2683 have no operands (for better performance and smaller code). */
2684
2685 if (mnemonic[0] != 'f')
2686 return 0; /* non-math */
2687
2688 switch (mnemonic[1])
2689 {
2690 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2691 the fs segment override prefix not currently handled because no
2692 call path can make opcodes without operands get here */
2693 case 'i':
2694 return 2 /* integer op */;
2695 case 'l':
2696 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2697 return 3; /* fldcw/fldenv */
2698 break;
2699 case 'n':
2700 if (mnemonic[2] != 'o' /* fnop */)
2701 return 3; /* non-waiting control op */
2702 break;
2703 case 'r':
2704 if (mnemonic[2] == 's')
2705 return 3; /* frstor/frstpm */
2706 break;
2707 case 's':
2708 if (mnemonic[2] == 'a')
2709 return 3; /* fsave */
2710 if (mnemonic[2] == 't')
2711 {
2712 switch (mnemonic[3])
2713 {
2714 case 'c': /* fstcw */
2715 case 'd': /* fstdw */
2716 case 'e': /* fstenv */
2717 case 's': /* fsts[gw] */
2718 return 3;
2719 }
2720 }
2721 break;
2722 case 'x':
2723 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2724 return 0; /* fxsave/fxrstor are not really math ops */
2725 break;
2726 }
252b5132 2727
9306ca4a 2728 return 1;
252b5132
RH		 2729}
2730
c0f3af97
L		 2731/* Build the VEX prefix. */
2732
2733static void
d3ce72d0 2734build_vex_prefix (const insn_template *t)
c0f3af97
L		 2735{
2736 unsigned int register_specifier;
2737 unsigned int implied_prefix;
2738 unsigned int vector_length;
2739
2740 /* Check register specifier. */
2741 if (i.vex.register_specifier)
2742 {
2743 register_specifier = i.vex.register_specifier->reg_num;
2744 if ((i.vex.register_specifier->reg_flags & RegRex))
2745 register_specifier += 8;
2746 register_specifier = ~register_specifier & 0xf;
2747 }
2748 else
2749 register_specifier = 0xf;
2750
fa99fab2
L		 2751 /* Use 2-byte VEX prefix by swappping destination and source
2752 operand. */
2753 if (!i.swap_operand
2754 && i.operands == i.reg_operands
7f399153 2755 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 2756 && i.tm.opcode_modifier.s
2757 && i.rex == REX_B)
2758 {
2759 unsigned int xchg = i.operands - 1;
2760 union i386_op temp_op;
2761 i386_operand_type temp_type;
2762
2763 temp_type = i.types[xchg];
2764 i.types[xchg] = i.types[0];
2765 i.types[0] = temp_type;
2766 temp_op = i.op[xchg];
2767 i.op[xchg] = i.op[0];
2768 i.op[0] = temp_op;
2769
9c2799c2 2770 gas_assert (i.rm.mode == 3);
fa99fab2
L		 2771
2772 i.rex = REX_R;
2773 xchg = i.rm.regmem;
2774 i.rm.regmem = i.rm.reg;
2775 i.rm.reg = xchg;
2776
2777 /* Use the next insn. */
2778 i.tm = t[1];
2779 }
2780
539f890d
L		 2781 if (i.tm.opcode_modifier.vex == VEXScalar)
2782 vector_length = avxscalar;
2783 else
2784 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 2785
2786 switch ((i.tm.base_opcode >> 8) & 0xff)
2787 {
2788 case 0:
2789 implied_prefix = 0;
2790 break;
2791 case DATA_PREFIX_OPCODE:
2792 implied_prefix = 1;
2793 break;
2794 case REPE_PREFIX_OPCODE:
2795 implied_prefix = 2;
2796 break;
2797 case REPNE_PREFIX_OPCODE:
2798 implied_prefix = 3;
2799 break;
2800 default:
2801 abort ();
2802 }
2803
2804 /* Use 2-byte VEX prefix if possible. */
7f399153 2805 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 2806 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 2807 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2808 {
2809 /* 2-byte VEX prefix. */
2810 unsigned int r;
2811
2812 i.vex.length = 2;
2813 i.vex.bytes[0] = 0xc5;
2814
2815 /* Check the REX.R bit. */
2816 r = (i.rex & REX_R) ? 0 : 1;
2817 i.vex.bytes[1] = (r << 7
2818 | register_specifier << 3
2819 | vector_length << 2
2820 | implied_prefix);
2821 }
2822 else
2823 {
2824 /* 3-byte VEX prefix. */
2825 unsigned int m, w;
2826
f88c9eb0 2827 i.vex.length = 3;
f88c9eb0 2828
7f399153 2829 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 2830 {
7f399153
L		 2831 case VEX0F:
2832 m = 0x1;
80de6e00 2833 i.vex.bytes[0] = 0xc4;
7f399153
L		 2834 break;
2835 case VEX0F38:
2836 m = 0x2;
80de6e00 2837 i.vex.bytes[0] = 0xc4;
7f399153
L		 2838 break;
2839 case VEX0F3A:
2840 m = 0x3;
80de6e00 2841 i.vex.bytes[0] = 0xc4;
7f399153
L		 2842 break;
2843 case XOP08:
5dd85c99
SP		 2844 m = 0x8;
2845 i.vex.bytes[0] = 0x8f;
7f399153
L		 2846 break;
2847 case XOP09:
f88c9eb0
SP		 2848 m = 0x9;
2849 i.vex.bytes[0] = 0x8f;
7f399153
L		 2850 break;
2851 case XOP0A:
f88c9eb0
SP		 2852 m = 0xa;
2853 i.vex.bytes[0] = 0x8f;
7f399153
L		 2854 break;
2855 default:
2856 abort ();
f88c9eb0 2857 }
c0f3af97 2858
c0f3af97
L		 2859 /* The high 3 bits of the second VEX byte are 1's compliment
2860 of RXB bits from REX. */
2861 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2862
2863 /* Check the REX.W bit. */
2864 w = (i.rex & REX_W) ? 1 : 0;
1ef99a7b 2865 if (i.tm.opcode_modifier.vexw)
c0f3af97
L		 2866 {
2867 if (w)
2868 abort ();
2869
1ef99a7b 2870 if (i.tm.opcode_modifier.vexw == VEXW1)
c0f3af97
L		 2871 w = 1;
2872 }
2873
2874 i.vex.bytes[2] = (w << 7
2875 | register_specifier << 3
2876 | vector_length << 2
2877 | implied_prefix);
2878 }
2879}
2880
65da13b5
L		 2881static void
2882process_immext (void)
2883{
2884 expressionS *exp;
2885
2886 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2887 {
1fed0ba1
L		 2888 /* SSE3 Instructions have the fixed operands with an opcode
2889 suffix which is coded in the same place as an 8-bit immediate
2890 field would be. Here we check those operands and remove them
2891 afterwards. */
65da13b5
L		 2892 unsigned int x;
2893
2894 for (x = 0; x < i.operands; x++)
2895 if (i.op[x].regs->reg_num != x)
2896 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 2897 register_prefix, i.op[x].regs->reg_name, x + 1,
2898 i.tm.name);
2899
2900 i.operands = 0;
65da13b5
L		 2901 }
2902
c0f3af97 2903 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 2904 which is coded in the same place as an 8-bit immediate field
2905 would be. Here we fake an 8-bit immediate operand from the
2906 opcode suffix stored in tm.extension_opcode.
2907
c1e679ec 2908 AVX instructions also use this encoding, for some of
c0f3af97 2909 3 argument instructions. */
65da13b5 2910
9c2799c2 2911 gas_assert (i.imm_operands == 0
7ab9ffdd
L		 2912 && (i.operands <= 2
2913 || (i.tm.opcode_modifier.vex
2914 && i.operands <= 4)));
65da13b5
L		 2915
2916 exp = &im_expressions[i.imm_operands++];
2917 i.op[i.operands].imms = exp;
2918 i.types[i.operands] = imm8;
2919 i.operands++;
2920 exp->X_op = O_constant;
2921 exp->X_add_number = i.tm.extension_opcode;
2922 i.tm.extension_opcode = None;
2923}
2924
252b5132
RH		 2925/* This is the guts of the machine-dependent assembler. LINE points to a
2926 machine dependent instruction. This function is supposed to emit
2927 the frags/bytes it assembles to. */
2928
2929void
65da13b5 2930md_assemble (char *line)
252b5132 2931{
40fb9820 2932 unsigned int j;
252b5132 2933 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 2934 const insn_template *t;
252b5132 2935
47926f60 2936 /* Initialize globals. */
252b5132
RH		 2937 memset (&i, '\0', sizeof (i));
2938 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2939 i.reloc[j] = NO_RELOC;
252b5132
RH		 2940 memset (disp_expressions, '\0', sizeof (disp_expressions));
2941 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2942 save_stack_p = save_stack;
252b5132
RH		 2943
2944 /* First parse an instruction mnemonic & call i386_operand for the operands.
2945 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2946 start of a (possibly prefixed) mnemonic. */
252b5132 2947
29b0f896
AM		 2948 line = parse_insn (line, mnemonic);
2949 if (line == NULL)
2950 return;
252b5132 2951
29b0f896 2952 line = parse_operands (line, mnemonic);
ee86248c 2953 this_operand = -1;
29b0f896
AM		 2954 if (line == NULL)
2955 return;
252b5132 2956
29b0f896
AM		 2957 /* Now we've parsed the mnemonic into a set of templates, and have the
2958 operands at hand. */
2959
2960 /* All intel opcodes have reversed operands except for "bound" and
2961 "enter". We also don't reverse intersegment "jmp" and "call"
2962 instructions with 2 immediate operands so that the immediate segment
050dfa73 2963 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2964 if (intel_syntax
2965 && i.operands > 1
29b0f896 2966 && (strcmp (mnemonic, "bound") != 0)
30123838 2967 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2968 && !(operand_type_check (i.types[0], imm)
2969 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2970 swap_operands ();
2971
ec56d5c0
JB		 2972 /* The order of the immediates should be reversed
2973 for 2 immediates extrq and insertq instructions */
2974 if (i.imm_operands == 2
2975 && (strcmp (mnemonic, "extrq") == 0
2976 || strcmp (mnemonic, "insertq") == 0))
2977 swap_2_operands (0, 1);
2978
29b0f896
AM		 2979 if (i.imm_operands)
2980 optimize_imm ();
2981
b300c311
L		 2982 /* Don't optimize displacement for movabs since it only takes 64bit
2983 displacement. */
2984 if (i.disp_operands
2985 && (flag_code != CODE_64BIT
2986 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2987 optimize_disp ();
2988
2989 /* Next, we find a template that matches the given insn,
2990 making sure the overlap of the given operands types is consistent
2991 with the template operand types. */
252b5132 2992
fa99fab2 2993 if (!(t = match_template ()))
29b0f896 2994 return;
252b5132 2995
daf50ae7 2996 if (sse_check != sse_check_none
81f8a913 2997 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 2998 && (i.tm.cpu_flags.bitfield.cpusse
2999 || i.tm.cpu_flags.bitfield.cpusse2
3000 || i.tm.cpu_flags.bitfield.cpusse3
3001 || i.tm.cpu_flags.bitfield.cpussse3
3002 || i.tm.cpu_flags.bitfield.cpusse4_1
3003 || i.tm.cpu_flags.bitfield.cpusse4_2))
3004 {
3005 (sse_check == sse_check_warning
3006 ? as_warn
3007 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3008 }
3009
321fd21e
L		 3010 /* Zap movzx and movsx suffix. The suffix has been set from
3011 "word ptr" or "byte ptr" on the source operand in Intel syntax
3012 or extracted from mnemonic in AT&T syntax. But we'll use
3013 the destination register to choose the suffix for encoding. */
3014 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3015 {
321fd21e
L		 3016 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3017 there is no suffix, the default will be byte extension. */
3018 if (i.reg_operands != 2
3019 && !i.suffix
7ab9ffdd 3020 && intel_syntax)
321fd21e
L		 3021 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3022
3023 i.suffix = 0;
cd61ebfe 3024 }
24eab124 3025
40fb9820 3026 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3027 if (!add_prefix (FWAIT_OPCODE))
3028 return;
252b5132 3029
c1ba0266
L		 3030 /* Check for lock without a lockable instruction. Destination operand
3031 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3032 if (i.prefix[LOCK_PREFIX]
3033 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3034 || i.mem_operands == 0
3035 || (i.tm.base_opcode != 0x86
3036 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3037 {
3038 as_bad (_("expecting lockable instruction after `lock'"));
3039 return;
3040 }
3041
29b0f896 3042 /* Check string instruction segment overrides. */
40fb9820 3043 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3044 {
3045 if (!check_string ())
5dd0794d 3046 return;
fc0763e6 3047 i.disp_operands = 0;
29b0f896 3048 }
5dd0794d 3049
29b0f896
AM		 3050 if (!process_suffix ())
3051 return;
e413e4e9 3052
bc0844ae
L		 3053 /* Update operand types. */
3054 for (j = 0; j < i.operands; j++)
3055 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3056
29b0f896
AM		 3057 /* Make still unresolved immediate matches conform to size of immediate
3058 given in i.suffix. */
3059 if (!finalize_imm ())
3060 return;
252b5132 3061
40fb9820 3062 if (i.types[0].bitfield.imm1)
29b0f896 3063 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3064
9afe6eb8
L		 3065 /* We only need to check those implicit registers for instructions
3066 with 3 operands or less. */
3067 if (i.operands <= 3)
3068 for (j = 0; j < i.operands; j++)
3069 if (i.types[j].bitfield.inoutportreg
3070 || i.types[j].bitfield.shiftcount
3071 || i.types[j].bitfield.acc
3072 || i.types[j].bitfield.floatacc)
3073 i.reg_operands--;
40fb9820 3074
c0f3af97
L		 3075 /* ImmExt should be processed after SSE2AVX. */
3076 if (!i.tm.opcode_modifier.sse2avx
3077 && i.tm.opcode_modifier.immext)
65da13b5 3078 process_immext ();
252b5132 3079
29b0f896
AM		 3080 /* For insns with operands there are more diddles to do to the opcode. */
3081 if (i.operands)
3082 {
3083 if (!process_operands ())
3084 return;
3085 }
40fb9820 3086 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3087 {
3088 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3089 as_warn (_("translating to `%sp'"), i.tm.name);
3090 }
252b5132 3091
c0f3af97 3092 if (i.tm.opcode_modifier.vex)
fa99fab2 3093 build_vex_prefix (t);
c0f3af97 3094
5dd85c99
SP		 3095 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3096 instructions may define INT_OPCODE as well, so avoid this corner
3097 case for those instructions that use MODRM. */
3098 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3099 && !i.tm.opcode_modifier.modrm
3100 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3101 {
3102 i.tm.base_opcode = INT3_OPCODE;
3103 i.imm_operands = 0;
3104 }
252b5132 3105
40fb9820
L		 3106 if ((i.tm.opcode_modifier.jump
3107 || i.tm.opcode_modifier.jumpbyte
3108 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3109 && i.op[0].disps->X_op == O_constant)
3110 {
3111 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3112 the absolute address given by the constant. Since ix86 jumps and
3113 calls are pc relative, we need to generate a reloc. */
3114 i.op[0].disps->X_add_symbol = &abs_symbol;
3115 i.op[0].disps->X_op = O_symbol;
3116 }
252b5132 3117
40fb9820 3118 if (i.tm.opcode_modifier.rex64)
161a04f6 3119 i.rex |= REX_W;
252b5132 3120
29b0f896
AM		 3121 /* For 8 bit registers we need an empty rex prefix. Also if the
3122 instruction already has a prefix, we need to convert old
3123 registers to new ones. */
773f551c 3124
40fb9820 3125 if ((i.types[0].bitfield.reg8
29b0f896 3126 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3127 || (i.types[1].bitfield.reg8
29b0f896 3128 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3129 || ((i.types[0].bitfield.reg8
3130 || i.types[1].bitfield.reg8)
29b0f896
AM		 3131 && i.rex != 0))
3132 {
3133 int x;
726c5dcd 3134
29b0f896
AM		 3135 i.rex |= REX_OPCODE;
3136 for (x = 0; x < 2; x++)
3137 {
3138 /* Look for 8 bit operand that uses old registers. */
40fb9820 3139 if (i.types[x].bitfield.reg8
29b0f896 3140 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3141 {
29b0f896
AM		 3142 /* In case it is "hi" register, give up. */
3143 if (i.op[x].regs->reg_num > 3)
a540244d 3144 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3145 "instruction requiring REX prefix."),
a540244d 3146 register_prefix, i.op[x].regs->reg_name);
773f551c 3147
29b0f896
AM		 3148 /* Otherwise it is equivalent to the extended register.
3149 Since the encoding doesn't change this is merely
3150 cosmetic cleanup for debug output. */
3151
3152 i.op[x].regs = i.op[x].regs + 8;
773f551c 3153 }
29b0f896
AM		 3154 }
3155 }
773f551c 3156
7ab9ffdd 3157 if (i.rex != 0)
29b0f896
AM		 3158 add_prefix (REX_OPCODE | i.rex);
3159
3160 /* We are ready to output the insn. */
3161 output_insn ();
3162}
3163
3164static char *
e3bb37b5 3165parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3166{
3167 char *l = line;
3168 char *token_start = l;
3169 char *mnem_p;
5c6af06e 3170 int supported;
d3ce72d0 3171 const insn_template *t;
b6169b20 3172 char *dot_p = NULL;
29b0f896
AM		 3173
3174 /* Non-zero if we found a prefix only acceptable with string insns. */
3175 const char *expecting_string_instruction = NULL;
45288df1 3176
29b0f896
AM		 3177 while (1)
3178 {
3179 mnem_p = mnemonic;
3180 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3181 {
b6169b20
L		 3182 if (*mnem_p == '.')
3183 dot_p = mnem_p;
29b0f896
AM		 3184 mnem_p++;
3185 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3186 {
29b0f896
AM		 3187 as_bad (_("no such instruction: `%s'"), token_start);
3188 return NULL;
3189 }
3190 l++;
3191 }
3192 if (!is_space_char (*l)
3193 && *l != END_OF_INSN
e44823cf
JB		 3194 && (intel_syntax
3195 || (*l != PREFIX_SEPARATOR
3196 && *l != ',')))
29b0f896
AM		 3197 {
3198 as_bad (_("invalid character %s in mnemonic"),
3199 output_invalid (*l));
3200 return NULL;
3201 }
3202 if (token_start == l)
3203 {
e44823cf 3204 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3205 as_bad (_("expecting prefix; got nothing"));
3206 else
3207 as_bad (_("expecting mnemonic; got nothing"));
3208 return NULL;
3209 }
45288df1 3210
29b0f896 3211 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3212 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3213
29b0f896
AM		 3214 if (*l != END_OF_INSN
3215 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3216 && current_templates
40fb9820 3217 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3218 {
c6fb90c8 3219 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3220 {
3221 as_bad ((flag_code != CODE_64BIT
3222 ? _("`%s' is only supported in 64-bit mode")
3223 : _("`%s' is not supported in 64-bit mode")),
3224 current_templates->start->name);
3225 return NULL;
3226 }
29b0f896
AM		 3227 /* If we are in 16-bit mode, do not allow addr16 or data16.
3228 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3229 if ((current_templates->start->opcode_modifier.size16
3230 || current_templates->start->opcode_modifier.size32)
29b0f896 3231 && flag_code != CODE_64BIT
40fb9820 3232 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3233 ^ (flag_code == CODE_16BIT)))
3234 {
3235 as_bad (_("redundant %s prefix"),
3236 current_templates->start->name);
3237 return NULL;
45288df1 3238 }
29b0f896
AM		 3239 /* Add prefix, checking for repeated prefixes. */
3240 switch (add_prefix (current_templates->start->base_opcode))
3241 {
c32fa91d 3242 case PREFIX_EXIST:
29b0f896 3243 return NULL;
c32fa91d 3244 case PREFIX_REP:
29b0f896
AM		 3245 expecting_string_instruction = current_templates->start->name;
3246 break;
c32fa91d
L		 3247 default:
3248 break;
29b0f896
AM		 3249 }
3250 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3251 token_start = ++l;
3252 }
3253 else
3254 break;
3255 }
45288df1 3256
30a55f88 3257 if (!current_templates)
b6169b20 3258 {
30a55f88
L		 3259 /* Check if we should swap operand in encoding. */
3260 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3261 i.swap_operand = 1;
3262 else
3263 goto check_suffix;
3264 mnem_p = dot_p;
3265 *dot_p = '\0';
d3ce72d0 3266 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3267 }
3268
29b0f896
AM		 3269 if (!current_templates)
3270 {
b6169b20 3271check_suffix:
29b0f896
AM		 3272 /* See if we can get a match by trimming off a suffix. */
3273 switch (mnem_p[-1])
3274 {
3275 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3276 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3277 i.suffix = SHORT_MNEM_SUFFIX;
3278 else
29b0f896
AM		 3279 case BYTE_MNEM_SUFFIX:
3280 case QWORD_MNEM_SUFFIX:
3281 i.suffix = mnem_p[-1];
3282 mnem_p[-1] = '\0';
d3ce72d0
NC		 3283 current_templates = (const templates *) hash_find (op_hash,
3284 mnemonic);
29b0f896
AM		 3285 break;
3286 case SHORT_MNEM_SUFFIX:
3287 case LONG_MNEM_SUFFIX:
3288 if (!intel_syntax)
3289 {
3290 i.suffix = mnem_p[-1];
3291 mnem_p[-1] = '\0';
d3ce72d0
NC		 3292 current_templates = (const templates *) hash_find (op_hash,
3293 mnemonic);
29b0f896
AM		 3294 }
3295 break;
252b5132 3296
29b0f896
AM		 3297 /* Intel Syntax. */
3298 case 'd':
3299 if (intel_syntax)
3300 {
9306ca4a 3301 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3302 i.suffix = SHORT_MNEM_SUFFIX;
3303 else
3304 i.suffix = LONG_MNEM_SUFFIX;
3305 mnem_p[-1] = '\0';
d3ce72d0
NC		 3306 current_templates = (const templates *) hash_find (op_hash,
3307 mnemonic);
29b0f896
AM		 3308 }
3309 break;
3310 }
3311 if (!current_templates)
3312 {
3313 as_bad (_("no such instruction: `%s'"), token_start);
3314 return NULL;
3315 }
3316 }
252b5132 3317
40fb9820
L		 3318 if (current_templates->start->opcode_modifier.jump
3319 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3320 {
3321 /* Check for a branch hint. We allow ",pt" and ",pn" for
3322 predict taken and predict not taken respectively.
3323 I'm not sure that branch hints actually do anything on loop
3324 and jcxz insns (JumpByte) for current Pentium4 chips. They
3325 may work in the future and it doesn't hurt to accept them
3326 now. */
3327 if (l[0] == ',' && l[1] == 'p')
3328 {
3329 if (l[2] == 't')
3330 {
3331 if (!add_prefix (DS_PREFIX_OPCODE))
3332 return NULL;
3333 l += 3;
3334 }
3335 else if (l[2] == 'n')
3336 {
3337 if (!add_prefix (CS_PREFIX_OPCODE))
3338 return NULL;
3339 l += 3;
3340 }
3341 }
3342 }
3343 /* Any other comma loses. */
3344 if (*l == ',')
3345 {
3346 as_bad (_("invalid character %s in mnemonic"),
3347 output_invalid (*l));
3348 return NULL;
3349 }
252b5132 3350
29b0f896 3351 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3352 supported = 0;
3353 for (t = current_templates->start; t < current_templates->end; ++t)
3354 {
c0f3af97
L		 3355 supported |= cpu_flags_match (t);
3356 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3357 goto skip;
5c6af06e 3358 }
3629bb00 3359
c0f3af97 3360 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3361 {
3362 as_bad (flag_code == CODE_64BIT
3363 ? _("`%s' is not supported in 64-bit mode")
3364 : _("`%s' is only supported in 64-bit mode"),
3365 current_templates->start->name);
3366 return NULL;
3367 }
c0f3af97 3368 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3369 {
3629bb00 3370 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3371 current_templates->start->name,
41aacd83 3372 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3373 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3374 return NULL;
29b0f896 3375 }
3629bb00
L		 3376
3377skip:
3378 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3379 && (flag_code != CODE_16BIT))
29b0f896
AM		 3380 {
3381 as_warn (_("use .code16 to ensure correct addressing mode"));
3382 }
252b5132 3383
29b0f896 3384 /* Check for rep/repne without a string instruction. */
f41bbced 3385 if (expecting_string_instruction)
29b0f896 3386 {
f41bbced
JB		 3387 static templates override;
3388
3389 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 3390 if (t->opcode_modifier.isstring)
f41bbced
JB		 3391 break;
3392 if (t >= current_templates->end)
3393 {
3394 as_bad (_("expecting string instruction after `%s'"),
64e74474 3395 expecting_string_instruction);
f41bbced
JB		 3396 return NULL;
3397 }
3398 for (override.start = t; t < current_templates->end; ++t)
40fb9820 3399 if (!t->opcode_modifier.isstring)
f41bbced
JB		 3400 break;
3401 override.end = t;
3402 current_templates = &override;
29b0f896 3403 }
252b5132 3404
29b0f896
AM		 3405 return l;
3406}
252b5132 3407
29b0f896 3408static char *
e3bb37b5 3409parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3410{
3411 char *token_start;
3138f287 3412
29b0f896
AM		 3413 /* 1 if operand is pending after ','. */
3414 unsigned int expecting_operand = 0;
252b5132 3415
29b0f896
AM		 3416 /* Non-zero if operand parens not balanced. */
3417 unsigned int paren_not_balanced;
3418
3419 while (*l != END_OF_INSN)
3420 {
3421 /* Skip optional white space before operand. */
3422 if (is_space_char (*l))
3423 ++l;
3424 if (!is_operand_char (*l) && *l != END_OF_INSN)
3425 {
3426 as_bad (_("invalid character %s before operand %d"),
3427 output_invalid (*l),
3428 i.operands + 1);
3429 return NULL;
3430 }
3431 token_start = l; /* after white space */
3432 paren_not_balanced = 0;
3433 while (paren_not_balanced || *l != ',')
3434 {
3435 if (*l == END_OF_INSN)
3436 {
3437 if (paren_not_balanced)
3438 {
3439 if (!intel_syntax)
3440 as_bad (_("unbalanced parenthesis in operand %d."),
3441 i.operands + 1);
3442 else
3443 as_bad (_("unbalanced brackets in operand %d."),
3444 i.operands + 1);
3445 return NULL;
3446 }
3447 else
3448 break; /* we are done */
3449 }
3450 else if (!is_operand_char (*l) && !is_space_char (*l))
3451 {
3452 as_bad (_("invalid character %s in operand %d"),
3453 output_invalid (*l),
3454 i.operands + 1);
3455 return NULL;
3456 }
3457 if (!intel_syntax)
3458 {
3459 if (*l == '(')
3460 ++paren_not_balanced;
3461 if (*l == ')')
3462 --paren_not_balanced;
3463 }
3464 else
3465 {
3466 if (*l == '[')
3467 ++paren_not_balanced;
3468 if (*l == ']')
3469 --paren_not_balanced;
3470 }
3471 l++;
3472 }
3473 if (l != token_start)
3474 { /* Yes, we've read in another operand. */
3475 unsigned int operand_ok;
3476 this_operand = i.operands++;
7d5e4556 3477 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3478 if (i.operands > MAX_OPERANDS)
3479 {
3480 as_bad (_("spurious operands; (%d operands/instruction max)"),
3481 MAX_OPERANDS);
3482 return NULL;
3483 }
3484 /* Now parse operand adding info to 'i' as we go along. */
3485 END_STRING_AND_SAVE (l);
3486
3487 if (intel_syntax)
3488 operand_ok =
3489 i386_intel_operand (token_start,
3490 intel_float_operand (mnemonic));
3491 else
a7619375 3492 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3493
3494 RESTORE_END_STRING (l);
3495 if (!operand_ok)
3496 return NULL;
3497 }
3498 else
3499 {
3500 if (expecting_operand)
3501 {
3502 expecting_operand_after_comma:
3503 as_bad (_("expecting operand after ','; got nothing"));
3504 return NULL;
3505 }
3506 if (*l == ',')
3507 {
3508 as_bad (_("expecting operand before ','; got nothing"));
3509 return NULL;
3510 }
3511 }
7f3f1ea2 3512
29b0f896
AM		 3513 /* Now *l must be either ',' or END_OF_INSN. */
3514 if (*l == ',')
3515 {
3516 if (*++l == END_OF_INSN)
3517 {
3518 /* Just skip it, if it's \n complain. */
3519 goto expecting_operand_after_comma;
3520 }
3521 expecting_operand = 1;
3522 }
3523 }
3524 return l;
3525}
7f3f1ea2 3526
050dfa73 3527static void
4d456e3d 3528swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3529{
3530 union i386_op temp_op;
40fb9820 3531 i386_operand_type temp_type;
050dfa73 3532 enum bfd_reloc_code_real temp_reloc;
4eed87de 3533
050dfa73
MM		 3534 temp_type = i.types[xchg2];
3535 i.types[xchg2] = i.types[xchg1];
3536 i.types[xchg1] = temp_type;
3537 temp_op = i.op[xchg2];
3538 i.op[xchg2] = i.op[xchg1];
3539 i.op[xchg1] = temp_op;
3540 temp_reloc = i.reloc[xchg2];
3541 i.reloc[xchg2] = i.reloc[xchg1];
3542 i.reloc[xchg1] = temp_reloc;
3543}
3544
29b0f896 3545static void
e3bb37b5 3546swap_operands (void)
29b0f896 3547{
b7c61d9a 3548 switch (i.operands)
050dfa73 3549 {
c0f3af97 3550 case 5:
b7c61d9a 3551 case 4:
4d456e3d 3552 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3553 case 3:
3554 case 2:
4d456e3d 3555 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3556 break;
3557 default:
3558 abort ();
29b0f896 3559 }
29b0f896
AM		 3560
3561 if (i.mem_operands == 2)
3562 {
3563 const seg_entry *temp_seg;
3564 temp_seg = i.seg[0];
3565 i.seg[0] = i.seg[1];
3566 i.seg[1] = temp_seg;
3567 }
3568}
252b5132 3569
29b0f896
AM		 3570/* Try to ensure constant immediates are represented in the smallest
3571 opcode possible. */
3572static void
e3bb37b5 3573optimize_imm (void)
29b0f896
AM		 3574{
3575 char guess_suffix = 0;
3576 int op;
252b5132 3577
29b0f896
AM		 3578 if (i.suffix)
3579 guess_suffix = i.suffix;
3580 else if (i.reg_operands)
3581 {
3582 /* Figure out a suffix from the last register operand specified.
3583 We can't do this properly yet, ie. excluding InOutPortReg,
3584 but the following works for instructions with immediates.
3585 In any case, we can't set i.suffix yet. */
3586 for (op = i.operands; --op >= 0;)
40fb9820 3587 if (i.types[op].bitfield.reg8)
7ab9ffdd 3588 {
40fb9820
L		 3589 guess_suffix = BYTE_MNEM_SUFFIX;
3590 break;
3591 }
3592 else if (i.types[op].bitfield.reg16)
252b5132 3593 {
40fb9820
L		 3594 guess_suffix = WORD_MNEM_SUFFIX;
3595 break;
3596 }
3597 else if (i.types[op].bitfield.reg32)
3598 {
3599 guess_suffix = LONG_MNEM_SUFFIX;
3600 break;
3601 }
3602 else if (i.types[op].bitfield.reg64)
3603 {
3604 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3605 break;
252b5132 3606 }
29b0f896
AM		 3607 }
3608 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3609 guess_suffix = WORD_MNEM_SUFFIX;
3610
3611 for (op = i.operands; --op >= 0;)
40fb9820 3612 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3613 {
3614 switch (i.op[op].imms->X_op)
252b5132 3615 {
29b0f896
AM		 3616 case O_constant:
3617 /* If a suffix is given, this operand may be shortened. */
3618 switch (guess_suffix)
252b5132 3619 {
29b0f896 3620 case LONG_MNEM_SUFFIX:
40fb9820
L		 3621 i.types[op].bitfield.imm32 = 1;
3622 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3623 break;
3624 case WORD_MNEM_SUFFIX:
40fb9820
L		 3625 i.types[op].bitfield.imm16 = 1;
3626 i.types[op].bitfield.imm32 = 1;
3627 i.types[op].bitfield.imm32s = 1;
3628 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3629 break;
3630 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3631 i.types[op].bitfield.imm8 = 1;
3632 i.types[op].bitfield.imm8s = 1;
3633 i.types[op].bitfield.imm16 = 1;
3634 i.types[op].bitfield.imm32 = 1;
3635 i.types[op].bitfield.imm32s = 1;
3636 i.types[op].bitfield.imm64 = 1;
29b0f896 3637 break;
252b5132 3638 }
252b5132 3639
29b0f896
AM		 3640 /* If this operand is at most 16 bits, convert it
3641 to a signed 16 bit number before trying to see
3642 whether it will fit in an even smaller size.
3643 This allows a 16-bit operand such as $0xffe0 to
3644 be recognised as within Imm8S range. */
40fb9820 3645 if ((i.types[op].bitfield.imm16)
29b0f896 3646 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3647 {
29b0f896
AM		 3648 i.op[op].imms->X_add_number =
3649 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3650 }
40fb9820 3651 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3652 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3653 == 0))
3654 {
3655 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3656 ^ ((offsetT) 1 << 31))
3657 - ((offsetT) 1 << 31));
3658 }
40fb9820 3659 i.types[op]
c6fb90c8
L		 3660 = operand_type_or (i.types[op],
3661 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3662
29b0f896
AM		 3663 /* We must avoid matching of Imm32 templates when 64bit
3664 only immediate is available. */
3665 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3666 i.types[op].bitfield.imm32 = 0;
29b0f896 3667 break;
252b5132 3668
29b0f896
AM		 3669 case O_absent:
3670 case O_register:
3671 abort ();
3672
3673 /* Symbols and expressions. */
3674 default:
9cd96992
JB		 3675 /* Convert symbolic operand to proper sizes for matching, but don't
3676 prevent matching a set of insns that only supports sizes other
3677 than those matching the insn suffix. */
3678 {
40fb9820 3679 i386_operand_type mask, allowed;
d3ce72d0 3680 const insn_template *t;
9cd96992 3681
0dfbf9d7
L		 3682 operand_type_set (&mask, 0);
3683 operand_type_set (&allowed, 0);
40fb9820 3684
4eed87de
AM		 3685 for (t = current_templates->start;
3686 t < current_templates->end;
3687 ++t)
c6fb90c8
L		 3688 allowed = operand_type_or (allowed,
3689 t->operand_types[op]);
9cd96992
JB		 3690 switch (guess_suffix)
3691 {
3692 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3693 mask.bitfield.imm64 = 1;
3694 mask.bitfield.imm32s = 1;
9cd96992
JB		 3695 break;
3696 case LONG_MNEM_SUFFIX:
40fb9820 3697 mask.bitfield.imm32 = 1;
9cd96992
JB		 3698 break;
3699 case WORD_MNEM_SUFFIX:
40fb9820 3700 mask.bitfield.imm16 = 1;
9cd96992
JB		 3701 break;
3702 case BYTE_MNEM_SUFFIX:
40fb9820 3703 mask.bitfield.imm8 = 1;
9cd96992
JB		 3704 break;
3705 default:
9cd96992
JB		 3706 break;
3707 }
c6fb90c8 3708 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3709 if (!operand_type_all_zero (&allowed))
c6fb90c8 3710 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3711 }
29b0f896 3712 break;
252b5132 3713 }
29b0f896
AM		 3714 }
3715}
47926f60 3716
29b0f896
AM		 3717/* Try to use the smallest displacement type too. */
3718static void
e3bb37b5 3719optimize_disp (void)
29b0f896
AM		 3720{
3721 int op;
3e73aa7c 3722
29b0f896 3723 for (op = i.operands; --op >= 0;)
40fb9820 3724 if (operand_type_check (i.types[op], disp))
252b5132 3725 {
b300c311 3726 if (i.op[op].disps->X_op == O_constant)
252b5132 3727 {
91d6fa6a 3728 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 3729
40fb9820 3730 if (i.types[op].bitfield.disp16
91d6fa6a 3731 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 3732 {
3733 /* If this operand is at most 16 bits, convert
3734 to a signed 16 bit number and don't use 64bit
3735 displacement. */
91d6fa6a 3736 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3737 i.types[op].bitfield.disp64 = 0;
b300c311 3738 }
40fb9820 3739 if (i.types[op].bitfield.disp32
91d6fa6a 3740 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 3741 {
3742 /* If this operand is at most 32 bits, convert
3743 to a signed 32 bit number and don't use 64bit
3744 displacement. */
91d6fa6a
NC		 3745 op_disp &= (((offsetT) 2 << 31) - 1);
3746 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3747 i.types[op].bitfield.disp64 = 0;
b300c311 3748 }
91d6fa6a 3749 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 3750 {
40fb9820
L		 3751 i.types[op].bitfield.disp8 = 0;
3752 i.types[op].bitfield.disp16 = 0;
3753 i.types[op].bitfield.disp32 = 0;
3754 i.types[op].bitfield.disp32s = 0;
3755 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3756 i.op[op].disps = 0;
3757 i.disp_operands--;
3758 }
3759 else if (flag_code == CODE_64BIT)
3760 {
91d6fa6a 3761 if (fits_in_signed_long (op_disp))
28a9d8f5 3762 {
40fb9820
L		 3763 i.types[op].bitfield.disp64 = 0;
3764 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3765 }
0e1147d9 3766 if (i.prefix[ADDR_PREFIX]
91d6fa6a 3767 && fits_in_unsigned_long (op_disp))
40fb9820 3768 i.types[op].bitfield.disp32 = 1;
b300c311 3769 }
40fb9820
L		 3770 if ((i.types[op].bitfield.disp32
3771 || i.types[op].bitfield.disp32s
3772 || i.types[op].bitfield.disp16)
91d6fa6a 3773 && fits_in_signed_byte (op_disp))
40fb9820 3774 i.types[op].bitfield.disp8 = 1;
252b5132 3775 }
67a4f2b7
AO		 3776 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3777 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3778 {
3779 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3780 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3781 i.types[op].bitfield.disp8 = 0;
3782 i.types[op].bitfield.disp16 = 0;
3783 i.types[op].bitfield.disp32 = 0;
3784 i.types[op].bitfield.disp32s = 0;
3785 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3786 }
3787 else
b300c311 3788 /* We only support 64bit displacement on constants. */
40fb9820 3789 i.types[op].bitfield.disp64 = 0;
252b5132 3790 }
29b0f896
AM		 3791}
3792
43f3e2ee 3793/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 3794 operand types. */
3795
3796static int
3797VEX_check_operands (const insn_template *t)
3798{
3799 if (!t->opcode_modifier.vex)
3800 return 0;
3801
3802 /* Only check VEX_Imm4, which must be the first operand. */
3803 if (t->operand_types[0].bitfield.vec_imm4)
3804 {
3805 if (i.op[0].imms->X_op != O_constant
3806 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 3807 {
a65babc9 3808 i.error = bad_imm4;
891edac4
L		 3809 return 1;
3810 }
a683cc34
SP		 3811
3812 /* Turn off Imm8 so that update_imm won't complain. */
3813 i.types[0] = vec_imm4;
3814 }
3815
3816 return 0;
3817}
3818
d3ce72d0 3819static const insn_template *
e3bb37b5 3820match_template (void)
29b0f896
AM		 3821{
3822 /* Points to template once we've found it. */
d3ce72d0 3823 const insn_template *t;
40fb9820 3824 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 3825 i386_operand_type overlap4;
29b0f896 3826 unsigned int found_reverse_match;
40fb9820
L		 3827 i386_opcode_modifier suffix_check;
3828 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3829 int addr_prefix_disp;
a5c311ca 3830 unsigned int j;
3629bb00 3831 unsigned int found_cpu_match;
45664ddb 3832 unsigned int check_register;
29b0f896 3833
c0f3af97
L		 3834#if MAX_OPERANDS != 5
3835# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 3836#endif
3837
29b0f896 3838 found_reverse_match = 0;
539e75ad 3839 addr_prefix_disp = -1;
40fb9820
L		 3840
3841 memset (&suffix_check, 0, sizeof (suffix_check));
3842 if (i.suffix == BYTE_MNEM_SUFFIX)
3843 suffix_check.no_bsuf = 1;
3844 else if (i.suffix == WORD_MNEM_SUFFIX)
3845 suffix_check.no_wsuf = 1;
3846 else if (i.suffix == SHORT_MNEM_SUFFIX)
3847 suffix_check.no_ssuf = 1;
3848 else if (i.suffix == LONG_MNEM_SUFFIX)
3849 suffix_check.no_lsuf = 1;
3850 else if (i.suffix == QWORD_MNEM_SUFFIX)
3851 suffix_check.no_qsuf = 1;
3852 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3853 suffix_check.no_ldsuf = 1;
29b0f896 3854
01559ecc
L		 3855 /* Must have right number of operands. */
3856 i.error = number_of_operands_mismatch;
3857
45aa61fe 3858 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3859 {
539e75ad
L		 3860 addr_prefix_disp = -1;
3861
29b0f896
AM		 3862 if (i.operands != t->operands)
3863 continue;
3864
50aecf8c 3865 /* Check processor support. */
a65babc9 3866 i.error = unsupported;
c0f3af97
L		 3867 found_cpu_match = (cpu_flags_match (t)
3868 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 3869 if (!found_cpu_match)
3870 continue;
3871
e1d4d893 3872 /* Check old gcc support. */
a65babc9 3873 i.error = old_gcc_only;
e1d4d893
L		 3874 if (!old_gcc && t->opcode_modifier.oldgcc)
3875 continue;
3876
3877 /* Check AT&T mnemonic. */
a65babc9 3878 i.error = unsupported_with_intel_mnemonic;
e1d4d893 3879 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3880 continue;
3881
891edac4 3882 /* Check AT&T/Intel syntax. */
a65babc9 3883 i.error = unsupported_syntax;
5c07affc
L		 3884 if ((intel_syntax && t->opcode_modifier.attsyntax)
3885 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3886 continue;
3887
20592a94 3888 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 3889 i.error = invalid_instruction_suffix;
567e4e96
L		 3890 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3891 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3892 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3893 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3894 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3895 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3896 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3897 continue;
3898
5c07affc 3899 if (!operand_size_match (t))
7d5e4556 3900 continue;
539e75ad 3901
5c07affc
L		 3902 for (j = 0; j < MAX_OPERANDS; j++)
3903 operand_types[j] = t->operand_types[j];
3904
45aa61fe
AM		 3905 /* In general, don't allow 64-bit operands in 32-bit mode. */
3906 if (i.suffix == QWORD_MNEM_SUFFIX
3907 && flag_code != CODE_64BIT
3908 && (intel_syntax
40fb9820 3909 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3910 && !intel_float_operand (t->name))
3911 : intel_float_operand (t->name) != 2)
40fb9820 3912 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 3913 && !operand_types[0].bitfield.regxmm
3914 && !operand_types[0].bitfield.regymm)
40fb9820 3915 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 3916 && !!operand_types[t->operands > 1].bitfield.regxmm
3917 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 3918 && (t->base_opcode != 0x0fc7
3919 || t->extension_opcode != 1 /* cmpxchg8b */))
3920 continue;
3921
192dc9c6
JB		 3922 /* In general, don't allow 32-bit operands on pre-386. */
3923 else if (i.suffix == LONG_MNEM_SUFFIX
3924 && !cpu_arch_flags.bitfield.cpui386
3925 && (intel_syntax
3926 ? (!t->opcode_modifier.ignoresize
3927 && !intel_float_operand (t->name))
3928 : intel_float_operand (t->name) != 2)
3929 && ((!operand_types[0].bitfield.regmmx
3930 && !operand_types[0].bitfield.regxmm)
3931 || (!operand_types[t->operands > 1].bitfield.regmmx
3932 && !!operand_types[t->operands > 1].bitfield.regxmm)))
3933 continue;
3934
29b0f896 3935 /* Do not verify operands when there are none. */
50aecf8c 3936 else
29b0f896 3937 {
c6fb90c8 3938 if (!t->operands)
2dbab7d5
L		 3939 /* We've found a match; break out of loop. */
3940 break;
29b0f896 3941 }
252b5132 3942
539e75ad
L		 3943 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3944 into Disp32/Disp16/Disp32 operand. */
3945 if (i.prefix[ADDR_PREFIX] != 0)
3946 {
40fb9820 3947 /* There should be only one Disp operand. */
539e75ad
L		 3948 switch (flag_code)
3949 {
3950 case CODE_16BIT:
40fb9820
L		 3951 for (j = 0; j < MAX_OPERANDS; j++)
3952 {
3953 if (operand_types[j].bitfield.disp16)
3954 {
3955 addr_prefix_disp = j;
3956 operand_types[j].bitfield.disp32 = 1;
3957 operand_types[j].bitfield.disp16 = 0;
3958 break;
3959 }
3960 }
539e75ad
L		 3961 break;
3962 case CODE_32BIT:
40fb9820
L		 3963 for (j = 0; j < MAX_OPERANDS; j++)
3964 {
3965 if (operand_types[j].bitfield.disp32)
3966 {
3967 addr_prefix_disp = j;
3968 operand_types[j].bitfield.disp32 = 0;
3969 operand_types[j].bitfield.disp16 = 1;
3970 break;
3971 }
3972 }
539e75ad
L		 3973 break;
3974 case CODE_64BIT:
40fb9820
L		 3975 for (j = 0; j < MAX_OPERANDS; j++)
3976 {
3977 if (operand_types[j].bitfield.disp64)
3978 {
3979 addr_prefix_disp = j;
3980 operand_types[j].bitfield.disp64 = 0;
3981 operand_types[j].bitfield.disp32 = 1;
3982 break;
3983 }
3984 }
539e75ad
L		 3985 break;
3986 }
539e75ad
L		 3987 }
3988
45664ddb
L		 3989 /* We check register size only if size of operands can be
3990 encoded the canonical way. */
3991 check_register = t->opcode_modifier.w;
c6fb90c8 3992 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3993 switch (t->operands)
3994 {
3995 case 1:
40fb9820 3996 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3997 continue;
3998 break;
3999 case 2:
8b38ad71
L		 4000 /* xchg %eax, %eax is a special case. It is an aliase for nop
4001 only in 32bit mode and we can use opcode 0x90. In 64bit
4002 mode, we can't use 0x90 for xchg %eax, %eax since it should
4003 zero-extend %eax to %rax. */
4004 if (flag_code == CODE_64BIT
4005 && t->base_opcode == 0x90
0dfbf9d7
L		 4006 && operand_type_equal (&i.types [0], &acc32)
4007 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4008 continue;
b6169b20
L		 4009 if (i.swap_operand)
4010 {
4011 /* If we swap operand in encoding, we either match
4012 the next one or reverse direction of operands. */
4013 if (t->opcode_modifier.s)
4014 continue;
4015 else if (t->opcode_modifier.d)
4016 goto check_reverse;
4017 }
4018
29b0f896 4019 case 3:
fa99fab2
L		 4020 /* If we swap operand in encoding, we match the next one. */
4021 if (i.swap_operand && t->opcode_modifier.s)
4022 continue;
f48ff2ae 4023 case 4:
c0f3af97 4024 case 5:
c6fb90c8 4025 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4026 if (!operand_type_match (overlap0, i.types[0])
4027 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4028 || (check_register
4029 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4030 operand_types[0],
4031 overlap1, i.types[1],
4032 operand_types[1])))
29b0f896
AM		 4033 {
4034 /* Check if other direction is valid ... */
40fb9820 4035 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4036 continue;
4037
b6169b20 4038check_reverse:
29b0f896 4039 /* Try reversing direction of operands. */
c6fb90c8
L		 4040 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4041 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4042 if (!operand_type_match (overlap0, i.types[0])
4043 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4044 || (check_register
4045 && !operand_type_register_match (overlap0,
4046 i.types[0],
4047 operand_types[1],
4048 overlap1,
4049 i.types[1],
4050 operand_types[0])))
29b0f896
AM		 4051 {
4052 /* Does not match either direction. */
4053 continue;
4054 }
4055 /* found_reverse_match holds which of D or FloatDR
4056 we've found. */
40fb9820 4057 if (t->opcode_modifier.d)
8a2ed489 4058 found_reverse_match = Opcode_D;
40fb9820 4059 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4060 found_reverse_match = Opcode_FloatD;
4061 else
4062 found_reverse_match = 0;
40fb9820 4063 if (t->opcode_modifier.floatr)
8a2ed489 4064 found_reverse_match |= Opcode_FloatR;
29b0f896 4065 }
f48ff2ae 4066 else
29b0f896 4067 {
f48ff2ae 4068 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4069 switch (t->operands)
4070 {
c0f3af97
L		 4071 case 5:
4072 overlap4 = operand_type_and (i.types[4],
4073 operand_types[4]);
d1cbb4db 4074 case 4:
c6fb90c8
L		 4075 overlap3 = operand_type_and (i.types[3],
4076 operand_types[3]);
d1cbb4db 4077 case 3:
c6fb90c8
L		 4078 overlap2 = operand_type_and (i.types[2],
4079 operand_types[2]);
d1cbb4db
L		 4080 break;
4081 }
29b0f896 4082
f48ff2ae
L		 4083 switch (t->operands)
4084 {
c0f3af97
L		 4085 case 5:
4086 if (!operand_type_match (overlap4, i.types[4])
4087 || !operand_type_register_match (overlap3,
4088 i.types[3],
4089 operand_types[3],
4090 overlap4,
4091 i.types[4],
4092 operand_types[4]))
4093 continue;
f48ff2ae 4094 case 4:
40fb9820 4095 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4096 || (check_register
4097 && !operand_type_register_match (overlap2,
4098 i.types[2],
4099 operand_types[2],
4100 overlap3,
4101 i.types[3],
4102 operand_types[3])))
f48ff2ae
L		 4103 continue;
4104 case 3:
4105 /* Here we make use of the fact that there are no
4106 reverse match 3 operand instructions, and all 3
4107 operand instructions only need to be checked for
4108 register consistency between operands 2 and 3. */
40fb9820 4109 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4110 || (check_register
4111 && !operand_type_register_match (overlap1,
4112 i.types[1],
4113 operand_types[1],
4114 overlap2,
4115 i.types[2],
4116 operand_types[2])))
f48ff2ae
L		 4117 continue;
4118 break;
4119 }
29b0f896 4120 }
f48ff2ae 4121 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4122 slip through to break. */
4123 }
3629bb00 4124 if (!found_cpu_match)
29b0f896
AM		 4125 {
4126 found_reverse_match = 0;
4127 continue;
4128 }
c0f3af97 4129
a683cc34
SP		 4130 /* Check if VEX operands are valid. */
4131 if (VEX_check_operands (t))
4132 continue;
4133
29b0f896
AM		 4134 /* We've found a match; break out of loop. */
4135 break;
4136 }
4137
4138 if (t == current_templates->end)
4139 {
4140 /* We found no match. */
a65babc9
L		 4141 const char *err_msg;
4142 switch (i.error)
4143 {
4144 default:
4145 abort ();
86e026a4 4146 case operand_size_mismatch:
a65babc9
L		 4147 err_msg = _("operand size mismatch");
4148 break;
4149 case operand_type_mismatch:
4150 err_msg = _("operand type mismatch");
4151 break;
4152 case register_type_mismatch:
4153 err_msg = _("register type mismatch");
4154 break;
4155 case number_of_operands_mismatch:
4156 err_msg = _("number of operands mismatch");
4157 break;
4158 case invalid_instruction_suffix:
4159 err_msg = _("invalid instruction suffix");
4160 break;
4161 case bad_imm4:
4162 err_msg = _("Imm4 isn't the first operand");
4163 break;
4164 case old_gcc_only:
4165 err_msg = _("only supported with old gcc");
4166 break;
4167 case unsupported_with_intel_mnemonic:
4168 err_msg = _("unsupported with Intel mnemonic");
4169 break;
4170 case unsupported_syntax:
4171 err_msg = _("unsupported syntax");
4172 break;
4173 case unsupported:
4174 err_msg = _("unsupported");
4175 break;
4176 }
4177 as_bad (_("%s for `%s'"), err_msg,
891edac4 4178 current_templates->start->name);
fa99fab2 4179 return NULL;
29b0f896 4180 }
252b5132 4181
29b0f896
AM		 4182 if (!quiet_warnings)
4183 {
4184 if (!intel_syntax
40fb9820
L		 4185 && (i.types[0].bitfield.jumpabsolute
4186 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 4187 {
4188 as_warn (_("indirect %s without `*'"), t->name);
4189 }
4190
40fb9820
L		 4191 if (t->opcode_modifier.isprefix
4192 && t->opcode_modifier.ignoresize)
29b0f896
AM		 4193 {
4194 /* Warn them that a data or address size prefix doesn't
4195 affect assembly of the next line of code. */
4196 as_warn (_("stand-alone `%s' prefix"), t->name);
4197 }
4198 }
4199
4200 /* Copy the template we found. */
4201 i.tm = *t;
539e75ad
L		 4202
4203 if (addr_prefix_disp != -1)
4204 i.tm.operand_types[addr_prefix_disp]
4205 = operand_types[addr_prefix_disp];
4206
29b0f896
AM		 4207 if (found_reverse_match)
4208 {
4209 /* If we found a reverse match we must alter the opcode
4210 direction bit. found_reverse_match holds bits to change
4211 (different for int & float insns). */
4212
4213 i.tm.base_opcode ^= found_reverse_match;
4214
539e75ad
L		 4215 i.tm.operand_types[0] = operand_types[1];
4216 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 4217 }
4218
fa99fab2 4219 return t;
29b0f896
AM		 4220}
4221
4222static int
e3bb37b5 4223check_string (void)
29b0f896 4224{
40fb9820
L		 4225 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
4226 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 4227 {
4228 if (i.seg[0] != NULL && i.seg[0] != &es)
4229 {
a87af027 4230 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4231 i.tm.name,
a87af027
JB		 4232 mem_op + 1,
4233 register_prefix);
29b0f896
AM		 4234 return 0;
4235 }
4236 /* There's only ever one segment override allowed per instruction.
4237 This instruction possibly has a legal segment override on the
4238 second operand, so copy the segment to where non-string
4239 instructions store it, allowing common code. */
4240 i.seg[0] = i.seg[1];
4241 }
40fb9820 4242 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 4243 {
4244 if (i.seg[1] != NULL && i.seg[1] != &es)
4245 {
a87af027 4246 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 4247 i.tm.name,
a87af027
JB		 4248 mem_op + 2,
4249 register_prefix);
29b0f896
AM		 4250 return 0;
4251 }
4252 }
4253 return 1;
4254}
4255
4256static int
543613e9 4257process_suffix (void)
29b0f896
AM		 4258{
4259 /* If matched instruction specifies an explicit instruction mnemonic
4260 suffix, use it. */
40fb9820
L		 4261 if (i.tm.opcode_modifier.size16)
4262 i.suffix = WORD_MNEM_SUFFIX;
4263 else if (i.tm.opcode_modifier.size32)
4264 i.suffix = LONG_MNEM_SUFFIX;
4265 else if (i.tm.opcode_modifier.size64)
4266 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 4267 else if (i.reg_operands)
4268 {
4269 /* If there's no instruction mnemonic suffix we try to invent one
4270 based on register operands. */
4271 if (!i.suffix)
4272 {
4273 /* We take i.suffix from the last register operand specified,
4274 Destination register type is more significant than source
381d071f
L		 4275 register type. crc32 in SSE4.2 prefers source register
4276 type. */
4277 if (i.tm.base_opcode == 0xf20f38f1)
4278 {
40fb9820
L		 4279 if (i.types[0].bitfield.reg16)
4280 i.suffix = WORD_MNEM_SUFFIX;
4281 else if (i.types[0].bitfield.reg32)
4282 i.suffix = LONG_MNEM_SUFFIX;
4283 else if (i.types[0].bitfield.reg64)
4284 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 4285 }
9344ff29 4286 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 4287 {
40fb9820 4288 if (i.types[0].bitfield.reg8)
20592a94
L		 4289 i.suffix = BYTE_MNEM_SUFFIX;
4290 }
381d071f
L		 4291
4292 if (!i.suffix)
4293 {
4294 int op;
4295
20592a94
L		 4296 if (i.tm.base_opcode == 0xf20f38f1
4297 || i.tm.base_opcode == 0xf20f38f0)
4298 {
4299 /* We have to know the operand size for crc32. */
4300 as_bad (_("ambiguous memory operand size for `%s`"),
4301 i.tm.name);
4302 return 0;
4303 }
4304
381d071f 4305 for (op = i.operands; --op >= 0;)
40fb9820 4306 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 4307 {
40fb9820
L		 4308 if (i.types[op].bitfield.reg8)
4309 {
4310 i.suffix = BYTE_MNEM_SUFFIX;
4311 break;
4312 }
4313 else if (i.types[op].bitfield.reg16)
4314 {
4315 i.suffix = WORD_MNEM_SUFFIX;
4316 break;
4317 }
4318 else if (i.types[op].bitfield.reg32)
4319 {
4320 i.suffix = LONG_MNEM_SUFFIX;
4321 break;
4322 }
4323 else if (i.types[op].bitfield.reg64)
4324 {
4325 i.suffix = QWORD_MNEM_SUFFIX;
4326 break;
4327 }
381d071f
L		 4328 }
4329 }
29b0f896
AM		 4330 }
4331 else if (i.suffix == BYTE_MNEM_SUFFIX)
4332 {
2eb952a4
L		 4333 if (intel_syntax
4334 && i.tm.opcode_modifier.ignoresize
4335 && i.tm.opcode_modifier.no_bsuf)
4336 i.suffix = 0;
4337 else if (!check_byte_reg ())
29b0f896
AM		 4338 return 0;
4339 }
4340 else if (i.suffix == LONG_MNEM_SUFFIX)
4341 {
2eb952a4
L		 4342 if (intel_syntax
4343 && i.tm.opcode_modifier.ignoresize
4344 && i.tm.opcode_modifier.no_lsuf)
4345 i.suffix = 0;
4346 else if (!check_long_reg ())
29b0f896
AM		 4347 return 0;
4348 }
4349 else if (i.suffix == QWORD_MNEM_SUFFIX)
4350 {
955e1e6a
L		 4351 if (intel_syntax
4352 && i.tm.opcode_modifier.ignoresize
4353 && i.tm.opcode_modifier.no_qsuf)
4354 i.suffix = 0;
4355 else if (!check_qword_reg ())
29b0f896
AM		 4356 return 0;
4357 }
4358 else if (i.suffix == WORD_MNEM_SUFFIX)
4359 {
2eb952a4
L		 4360 if (intel_syntax
4361 && i.tm.opcode_modifier.ignoresize
4362 && i.tm.opcode_modifier.no_wsuf)
4363 i.suffix = 0;
4364 else if (!check_word_reg ())
29b0f896
AM		 4365 return 0;
4366 }
c0f3af97
L		 4367 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4368 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 4369 {
c0f3af97 4370 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 4371 should check if it is a valid suffix. */
4372 }
40fb9820 4373 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 4374 /* Do nothing if the instruction is going to ignore the prefix. */
4375 ;
4376 else
4377 abort ();
4378 }
40fb9820 4379 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 4380 && !i.suffix
4381 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 4382 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 4383 {
4384 i.suffix = stackop_size;
4385 }
9306ca4a
JB		 4386 else if (intel_syntax
4387 && !i.suffix
40fb9820
L		 4388 && (i.tm.operand_types[0].bitfield.jumpabsolute
4389 || i.tm.opcode_modifier.jumpbyte
4390 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 4391 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4392 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 4393 {
4394 switch (flag_code)
4395 {
4396 case CODE_64BIT:
40fb9820 4397 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 4398 {
4399 i.suffix = QWORD_MNEM_SUFFIX;
4400 break;
4401 }
4402 case CODE_32BIT:
40fb9820 4403 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 4404 i.suffix = LONG_MNEM_SUFFIX;
4405 break;
4406 case CODE_16BIT:
40fb9820 4407 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 4408 i.suffix = WORD_MNEM_SUFFIX;
4409 break;
4410 }
4411 }
252b5132 4412
9306ca4a 4413 if (!i.suffix)
29b0f896 4414 {
9306ca4a
JB		 4415 if (!intel_syntax)
4416 {
40fb9820 4417 if (i.tm.opcode_modifier.w)
9306ca4a 4418 {
4eed87de
AM		 4419 as_bad (_("no instruction mnemonic suffix given and "
4420 "no register operands; can't size instruction"));
9306ca4a
JB		 4421 return 0;
4422 }
4423 }
4424 else
4425 {
40fb9820 4426 unsigned int suffixes;
7ab9ffdd 4427
40fb9820
L		 4428 suffixes = !i.tm.opcode_modifier.no_bsuf;
4429 if (!i.tm.opcode_modifier.no_wsuf)
4430 suffixes |= 1 << 1;
4431 if (!i.tm.opcode_modifier.no_lsuf)
4432 suffixes |= 1 << 2;
fc4adea1 4433 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 4434 suffixes |= 1 << 3;
4435 if (!i.tm.opcode_modifier.no_ssuf)
4436 suffixes |= 1 << 4;
4437 if (!i.tm.opcode_modifier.no_qsuf)
4438 suffixes |= 1 << 5;
4439
4440 /* There are more than suffix matches. */
4441 if (i.tm.opcode_modifier.w
9306ca4a 4442 || ((suffixes & (suffixes - 1))
40fb9820
L		 4443 && !i.tm.opcode_modifier.defaultsize
4444 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 4445 {
4446 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4447 return 0;
4448 }
4449 }
29b0f896 4450 }
252b5132 4451
9306ca4a
JB		 4452 /* Change the opcode based on the operand size given by i.suffix;
4453 We don't need to change things for byte insns. */
4454
582d5edd
L		 4455 if (i.suffix
4456 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 4457 && i.suffix != XMMWORD_MNEM_SUFFIX
4458 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 4459 {
4460 /* It's not a byte, select word/dword operation. */
40fb9820 4461 if (i.tm.opcode_modifier.w)
29b0f896 4462 {
40fb9820 4463 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4464 i.tm.base_opcode |= 8;
4465 else
4466 i.tm.base_opcode |= 1;
4467 }
0f3f3d8b 4468
29b0f896
AM		 4469 /* Now select between word & dword operations via the operand
4470 size prefix, except for instructions that will ignore this
4471 prefix anyway. */
ca61edf2 4472 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4473 {
ca61edf2
L		 4474 /* The address size override prefix changes the size of the
4475 first operand. */
40fb9820
L		 4476 if ((flag_code == CODE_32BIT
4477 && i.op->regs[0].reg_type.bitfield.reg16)
4478 || (flag_code != CODE_32BIT
4479 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4480 if (!add_prefix (ADDR_PREFIX_OPCODE))
4481 return 0;
4482 }
4483 else if (i.suffix != QWORD_MNEM_SUFFIX
4484 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4485 && !i.tm.opcode_modifier.ignoresize
4486 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4487 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4488 || (flag_code == CODE_64BIT
40fb9820 4489 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4490 {
4491 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4492
40fb9820 4493 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4494 prefix = ADDR_PREFIX_OPCODE;
252b5132 4495
29b0f896
AM		 4496 if (!add_prefix (prefix))
4497 return 0;
24eab124 4498 }
252b5132 4499
29b0f896
AM		 4500 /* Set mode64 for an operand. */
4501 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4502 && flag_code == CODE_64BIT
40fb9820 4503 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4504 {
4505 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4506 need rex64. cmpxchg8b is also a special case. */
4507 if (! (i.operands == 2
4508 && i.tm.base_opcode == 0x90
4509 && i.tm.extension_opcode == None
0dfbf9d7
L		 4510 && operand_type_equal (&i.types [0], &acc64)
4511 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4512 && ! (i.operands == 1
4513 && i.tm.base_opcode == 0xfc7
4514 && i.tm.extension_opcode == 1
40fb9820
L		 4515 && !operand_type_check (i.types [0], reg)
4516 && operand_type_check (i.types [0], anymem)))
f6bee062 4517 i.rex |= REX_W;
46e883c5 4518 }
3e73aa7c 4519
29b0f896
AM		 4520 /* Size floating point instruction. */
4521 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4522 if (i.tm.opcode_modifier.floatmf)
543613e9 4523 i.tm.base_opcode ^= 4;
29b0f896 4524 }
7ecd2f8b 4525
29b0f896
AM		 4526 return 1;
4527}
3e73aa7c 4528
29b0f896 4529static int
543613e9 4530check_byte_reg (void)
29b0f896
AM		 4531{
4532 int op;
543613e9 4533
29b0f896
AM		 4534 for (op = i.operands; --op >= 0;)
4535 {
4536 /* If this is an eight bit register, it's OK. If it's the 16 or
4537 32 bit version of an eight bit register, we will just use the
4538 low portion, and that's OK too. */
40fb9820 4539 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4540 continue;
4541
9344ff29
L		 4542 /* crc32 doesn't generate this warning. */
4543 if (i.tm.base_opcode == 0xf20f38f0)
4544 continue;
4545
40fb9820
L		 4546 if ((i.types[op].bitfield.reg16
4547 || i.types[op].bitfield.reg32
4548 || i.types[op].bitfield.reg64)
4549 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 4550 {
4551 /* Prohibit these changes in the 64bit mode, since the
4552 lowering is more complicated. */
4553 if (flag_code == CODE_64BIT
40fb9820 4554 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 4555 {
2ca3ace5
L		 4556 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4557 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4558 i.suffix);
4559 return 0;
4560 }
4561#if REGISTER_WARNINGS
4562 if (!quiet_warnings
40fb9820 4563 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 4564 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4565 register_prefix,
40fb9820 4566 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4567 ? REGNAM_AL - REGNAM_AX
4568 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4569 register_prefix,
29b0f896
AM		 4570 i.op[op].regs->reg_name,
4571 i.suffix);
4572#endif
4573 continue;
4574 }
4575 /* Any other register is bad. */
40fb9820
L		 4576 if (i.types[op].bitfield.reg16
4577 || i.types[op].bitfield.reg32
4578 || i.types[op].bitfield.reg64
4579 || i.types[op].bitfield.regmmx
4580 || i.types[op].bitfield.regxmm
c0f3af97 4581 || i.types[op].bitfield.regymm
40fb9820
L		 4582 || i.types[op].bitfield.sreg2
4583 || i.types[op].bitfield.sreg3
4584 || i.types[op].bitfield.control
4585 || i.types[op].bitfield.debug
4586 || i.types[op].bitfield.test
4587 || i.types[op].bitfield.floatreg
4588 || i.types[op].bitfield.floatacc)
29b0f896 4589 {
a540244d
L		 4590 as_bad (_("`%s%s' not allowed with `%s%c'"),
4591 register_prefix,
29b0f896
AM		 4592 i.op[op].regs->reg_name,
4593 i.tm.name,
4594 i.suffix);
4595 return 0;
4596 }
4597 }
4598 return 1;
4599}
4600
4601static int
e3bb37b5 4602check_long_reg (void)
29b0f896
AM		 4603{
4604 int op;
4605
4606 for (op = i.operands; --op >= 0;)
4607 /* Reject eight bit registers, except where the template requires
4608 them. (eg. movzb) */
40fb9820
L		 4609 if (i.types[op].bitfield.reg8
4610 && (i.tm.operand_types[op].bitfield.reg16
4611 || i.tm.operand_types[op].bitfield.reg32
4612 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4613 {
a540244d
L		 4614 as_bad (_("`%s%s' not allowed with `%s%c'"),
4615 register_prefix,
29b0f896
AM		 4616 i.op[op].regs->reg_name,
4617 i.tm.name,
4618 i.suffix);
4619 return 0;
4620 }
4621 /* Warn if the e prefix on a general reg is missing. */
4622 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4623 && i.types[op].bitfield.reg16
4624 && (i.tm.operand_types[op].bitfield.reg32
4625 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4626 {
4627 /* Prohibit these changes in the 64bit mode, since the
4628 lowering is more complicated. */
4629 if (flag_code == CODE_64BIT)
252b5132 4630 {
2ca3ace5
L		 4631 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4632 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4633 i.suffix);
4634 return 0;
252b5132 4635 }
29b0f896
AM		 4636#if REGISTER_WARNINGS
4637 else
a540244d
L		 4638 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4639 register_prefix,
29b0f896 4640 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4641 register_prefix,
29b0f896
AM		 4642 i.op[op].regs->reg_name,
4643 i.suffix);
4644#endif
252b5132 4645 }
29b0f896 4646 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4647 else if (i.types[op].bitfield.reg64
4648 && (i.tm.operand_types[op].bitfield.reg32
4649 || i.tm.operand_types[op].bitfield.acc))
252b5132 4650 {
34828aad 4651 if (intel_syntax
ca61edf2 4652 && i.tm.opcode_modifier.toqword
40fb9820 4653 && !i.types[0].bitfield.regxmm)
34828aad 4654 {
ca61edf2 4655 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4656 i.suffix = QWORD_MNEM_SUFFIX;
4657 }
4658 else
4659 {
4660 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4661 register_prefix, i.op[op].regs->reg_name,
4662 i.suffix);
4663 return 0;
4664 }
29b0f896
AM		 4665 }
4666 return 1;
4667}
252b5132 4668
29b0f896 4669static int
e3bb37b5 4670check_qword_reg (void)
29b0f896
AM		 4671{
4672 int op;
252b5132 4673
29b0f896
AM		 4674 for (op = i.operands; --op >= 0; )
4675 /* Reject eight bit registers, except where the template requires
4676 them. (eg. movzb) */
40fb9820
L		 4677 if (i.types[op].bitfield.reg8
4678 && (i.tm.operand_types[op].bitfield.reg16
4679 || i.tm.operand_types[op].bitfield.reg32
4680 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4681 {
a540244d
L		 4682 as_bad (_("`%s%s' not allowed with `%s%c'"),
4683 register_prefix,
29b0f896
AM		 4684 i.op[op].regs->reg_name,
4685 i.tm.name,
4686 i.suffix);
4687 return 0;
4688 }
4689 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4690 else if ((i.types[op].bitfield.reg16
4691 || i.types[op].bitfield.reg32)
4692 && (i.tm.operand_types[op].bitfield.reg32
4693 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4694 {
4695 /* Prohibit these changes in the 64bit mode, since the
4696 lowering is more complicated. */
34828aad 4697 if (intel_syntax
ca61edf2 4698 && i.tm.opcode_modifier.todword
40fb9820 4699 && !i.types[0].bitfield.regxmm)
34828aad 4700 {
ca61edf2 4701 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4702 i.suffix = LONG_MNEM_SUFFIX;
4703 }
4704 else
4705 {
4706 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4707 register_prefix, i.op[op].regs->reg_name,
4708 i.suffix);
4709 return 0;
4710 }
252b5132 4711 }
29b0f896
AM		 4712 return 1;
4713}
252b5132 4714
29b0f896 4715static int
e3bb37b5 4716check_word_reg (void)
29b0f896
AM		 4717{
4718 int op;
4719 for (op = i.operands; --op >= 0;)
4720 /* Reject eight bit registers, except where the template requires
4721 them. (eg. movzb) */
40fb9820
L		 4722 if (i.types[op].bitfield.reg8
4723 && (i.tm.operand_types[op].bitfield.reg16
4724 || i.tm.operand_types[op].bitfield.reg32
4725 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4726 {
a540244d
L		 4727 as_bad (_("`%s%s' not allowed with `%s%c'"),
4728 register_prefix,
29b0f896
AM		 4729 i.op[op].regs->reg_name,
4730 i.tm.name,
4731 i.suffix);
4732 return 0;
4733 }
4734 /* Warn if the e prefix on a general reg is present. */
4735 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4736 && i.types[op].bitfield.reg32
4737 && (i.tm.operand_types[op].bitfield.reg16
4738 || i.tm.operand_types[op].bitfield.acc))
252b5132 4739 {
29b0f896
AM		 4740 /* Prohibit these changes in the 64bit mode, since the
4741 lowering is more complicated. */
4742 if (flag_code == CODE_64BIT)
252b5132 4743 {
2ca3ace5
L		 4744 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4745 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4746 i.suffix);
4747 return 0;
252b5132 4748 }
29b0f896
AM		 4749 else
4750#if REGISTER_WARNINGS
a540244d
L		 4751 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4752 register_prefix,
29b0f896 4753 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4754 register_prefix,
29b0f896
AM		 4755 i.op[op].regs->reg_name,
4756 i.suffix);
4757#endif
4758 }
4759 return 1;
4760}
252b5132 4761
29b0f896 4762static int
40fb9820 4763update_imm (unsigned int j)
29b0f896 4764{
bc0844ae 4765 i386_operand_type overlap = i.types[j];
40fb9820
L		 4766 if ((overlap.bitfield.imm8
4767 || overlap.bitfield.imm8s
4768 || overlap.bitfield.imm16
4769 || overlap.bitfield.imm32
4770 || overlap.bitfield.imm32s
4771 || overlap.bitfield.imm64)
0dfbf9d7
L		 4772 && !operand_type_equal (&overlap, &imm8)
4773 && !operand_type_equal (&overlap, &imm8s)
4774 && !operand_type_equal (&overlap, &imm16)
4775 && !operand_type_equal (&overlap, &imm32)
4776 && !operand_type_equal (&overlap, &imm32s)
4777 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 4778 {
4779 if (i.suffix)
4780 {
40fb9820
L		 4781 i386_operand_type temp;
4782
0dfbf9d7 4783 operand_type_set (&temp, 0);
7ab9ffdd 4784 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 4785 {
4786 temp.bitfield.imm8 = overlap.bitfield.imm8;
4787 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4788 }
4789 else if (i.suffix == WORD_MNEM_SUFFIX)
4790 temp.bitfield.imm16 = overlap.bitfield.imm16;
4791 else if (i.suffix == QWORD_MNEM_SUFFIX)
4792 {
4793 temp.bitfield.imm64 = overlap.bitfield.imm64;
4794 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4795 }
4796 else
4797 temp.bitfield.imm32 = overlap.bitfield.imm32;
4798 overlap = temp;
29b0f896 4799 }
0dfbf9d7
L		 4800 else if (operand_type_equal (&overlap, &imm16_32_32s)
4801 || operand_type_equal (&overlap, &imm16_32)
4802 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 4803 {
40fb9820 4804 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 4805 overlap = imm16;
40fb9820 4806 else
65da13b5 4807 overlap = imm32s;
29b0f896 4808 }
0dfbf9d7
L		 4809 if (!operand_type_equal (&overlap, &imm8)
4810 && !operand_type_equal (&overlap, &imm8s)
4811 && !operand_type_equal (&overlap, &imm16)
4812 && !operand_type_equal (&overlap, &imm32)
4813 && !operand_type_equal (&overlap, &imm32s)
4814 && !operand_type_equal (&overlap, &imm64))
29b0f896 4815 {
4eed87de
AM		 4816 as_bad (_("no instruction mnemonic suffix given; "
4817 "can't determine immediate size"));
29b0f896
AM		 4818 return 0;
4819 }
4820 }
40fb9820 4821 i.types[j] = overlap;
29b0f896 4822
40fb9820
L		 4823 return 1;
4824}
4825
4826static int
4827finalize_imm (void)
4828{
bc0844ae 4829 unsigned int j, n;
29b0f896 4830
bc0844ae
L		 4831 /* Update the first 2 immediate operands. */
4832 n = i.operands > 2 ? 2 : i.operands;
4833 if (n)
4834 {
4835 for (j = 0; j < n; j++)
4836 if (update_imm (j) == 0)
4837 return 0;
40fb9820 4838
bc0844ae
L		 4839 /* The 3rd operand can't be immediate operand. */
4840 gas_assert (operand_type_check (i.types[2], imm) == 0);
4841 }
29b0f896
AM		 4842
4843 return 1;
4844}
4845
c0f3af97
L		 4846static int
4847bad_implicit_operand (int xmm)
4848{
91d6fa6a
NC		 4849 const char *ireg = xmm ? "xmm0" : "ymm0";
4850
c0f3af97
L		 4851 if (intel_syntax)
4852 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 4853 i.tm.name, register_prefix, ireg);
c0f3af97
L		 4854 else
4855 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 4856 i.tm.name, register_prefix, ireg);
c0f3af97
L		 4857 return 0;
4858}
4859
29b0f896 4860static int
e3bb37b5 4861process_operands (void)
29b0f896
AM		 4862{
4863 /* Default segment register this instruction will use for memory
4864 accesses. 0 means unknown. This is only for optimizing out
4865 unnecessary segment overrides. */
4866 const seg_entry *default_seg = 0;
4867
2426c15f 4868 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 4869 {
91d6fa6a
NC		 4870 unsigned int dupl = i.operands;
4871 unsigned int dest = dupl - 1;
9fcfb3d7
L		 4872 unsigned int j;
4873
c0f3af97 4874 /* The destination must be an xmm register. */
9c2799c2 4875 gas_assert (i.reg_operands
91d6fa6a 4876 && MAX_OPERANDS > dupl
7ab9ffdd 4877 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 4878
4879 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 4880 {
c0f3af97 4881 /* The first operand is implicit and must be xmm0. */
9c2799c2 4882 gas_assert (operand_type_equal (&i.types[0], &regxmm));
c0f3af97
L		 4883 if (i.op[0].regs->reg_num != 0)
4884 return bad_implicit_operand (1);
4885
8cd7925b 4886 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 4887 {
4888 /* Keep xmm0 for instructions with VEX prefix and 3
4889 sources. */
4890 goto duplicate;
4891 }
e2ec9d29 4892 else
c0f3af97
L		 4893 {
4894 /* We remove the first xmm0 and keep the number of
4895 operands unchanged, which in fact duplicates the
4896 destination. */
4897 for (j = 1; j < i.operands; j++)
4898 {
4899 i.op[j - 1] = i.op[j];
4900 i.types[j - 1] = i.types[j];
4901 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
4902 }
4903 }
4904 }
4905 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 4906 {
91d6fa6a 4907 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 4908 && (i.tm.opcode_modifier.vexsources
4909 == VEX3SOURCES));
c0f3af97
L		 4910
4911 /* Add the implicit xmm0 for instructions with VEX prefix
4912 and 3 sources. */
4913 for (j = i.operands; j > 0; j--)
4914 {
4915 i.op[j] = i.op[j - 1];
4916 i.types[j] = i.types[j - 1];
4917 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
4918 }
4919 i.op[0].regs
4920 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 4921 i.types[0] = regxmm;
c0f3af97
L		 4922 i.tm.operand_types[0] = regxmm;
4923
4924 i.operands += 2;
4925 i.reg_operands += 2;
4926 i.tm.operands += 2;
4927
91d6fa6a 4928 dupl++;
c0f3af97 4929 dest++;
91d6fa6a
NC		 4930 i.op[dupl] = i.op[dest];
4931 i.types[dupl] = i.types[dest];
4932 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 4933 }
c0f3af97
L		 4934 else
4935 {
4936duplicate:
4937 i.operands++;
4938 i.reg_operands++;
4939 i.tm.operands++;
4940
91d6fa6a
NC		 4941 i.op[dupl] = i.op[dest];
4942 i.types[dupl] = i.types[dest];
4943 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 4944 }
4945
4946 if (i.tm.opcode_modifier.immext)
4947 process_immext ();
4948 }
4949 else if (i.tm.opcode_modifier.firstxmm0)
4950 {
4951 unsigned int j;
4952
4953 /* The first operand is implicit and must be xmm0/ymm0. */
9c2799c2 4954 gas_assert (i.reg_operands
7ab9ffdd
L		 4955 && (operand_type_equal (&i.types[0], &regxmm)
4956 || operand_type_equal (&i.types[0], &regymm)));
c0f3af97
L		 4957 if (i.op[0].regs->reg_num != 0)
4958 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 4959
4960 for (j = 1; j < i.operands; j++)
4961 {
4962 i.op[j - 1] = i.op[j];
4963 i.types[j - 1] = i.types[j];
4964
4965 /* We need to adjust fields in i.tm since they are used by
4966 build_modrm_byte. */
4967 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4968 }
4969
e2ec9d29
L		 4970 i.operands--;
4971 i.reg_operands--;
e2ec9d29
L		 4972 i.tm.operands--;
4973 }
4974 else if (i.tm.opcode_modifier.regkludge)
4975 {
4976 /* The imul $imm, %reg instruction is converted into
4977 imul $imm, %reg, %reg, and the clr %reg instruction
4978 is converted into xor %reg, %reg. */
4979
4980 unsigned int first_reg_op;
4981
4982 if (operand_type_check (i.types[0], reg))
4983 first_reg_op = 0;
4984 else
4985 first_reg_op = 1;
4986 /* Pretend we saw the extra register operand. */
9c2799c2 4987 gas_assert (i.reg_operands == 1
7ab9ffdd 4988 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 4989 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4990 i.types[first_reg_op + 1] = i.types[first_reg_op];
4991 i.operands++;
4992 i.reg_operands++;
29b0f896
AM		 4993 }
4994
40fb9820 4995 if (i.tm.opcode_modifier.shortform)
29b0f896 4996 {
40fb9820
L		 4997 if (i.types[0].bitfield.sreg2
4998 || i.types[0].bitfield.sreg3)
29b0f896 4999 {
4eed87de
AM		 5000 if (i.tm.base_opcode == POP_SEG_SHORT
5001 && i.op[0].regs->reg_num == 1)
29b0f896 5002 {
a87af027 5003 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5004 return 0;
29b0f896 5005 }
4eed87de
AM		 5006 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5007 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5008 i.rex |= REX_B;
4eed87de
AM		 5009 }
5010 else
5011 {
7ab9ffdd 5012 /* The register or float register operand is in operand
85f10a01 5013 0 or 1. */
40fb9820 5014 unsigned int op;
7ab9ffdd
L		 5015
5016 if (i.types[0].bitfield.floatreg
5017 || operand_type_check (i.types[0], reg))
5018 op = 0;
5019 else
5020 op = 1;
4eed87de
AM		 5021 /* Register goes in low 3 bits of opcode. */
5022 i.tm.base_opcode |= i.op[op].regs->reg_num;
5023 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5024 i.rex |= REX_B;
40fb9820 5025 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5026 {
4eed87de
AM		 5027 /* Warn about some common errors, but press on regardless.
5028 The first case can be generated by gcc (<= 2.8.1). */
5029 if (i.operands == 2)
5030 {
5031 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5032 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5033 register_prefix, i.op[!intel_syntax].regs->reg_name,
5034 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5035 }
5036 else
5037 {
5038 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5039 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5040 register_prefix, i.op[0].regs->reg_name);
4eed87de 5041 }
29b0f896
AM		 5042 }
5043 }
5044 }
40fb9820 5045 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5046 {
5047 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5048 must be put into the modrm byte). Now, we make the modrm and
5049 index base bytes based on all the info we've collected. */
29b0f896
AM		 5050
5051 default_seg = build_modrm_byte ();
5052 }
8a2ed489 5053 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5054 {
5055 default_seg = &ds;
5056 }
40fb9820 5057 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5058 {
5059 /* For the string instructions that allow a segment override
5060 on one of their operands, the default segment is ds. */
5061 default_seg = &ds;
5062 }
5063
75178d9d
L		 5064 if (i.tm.base_opcode == 0x8d /* lea */
5065 && i.seg[0]
5066 && !quiet_warnings)
30123838 5067 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5068
5069 /* If a segment was explicitly specified, and the specified segment
5070 is not the default, use an opcode prefix to select it. If we
5071 never figured out what the default segment is, then default_seg
5072 will be zero at this point, and the specified segment prefix will
5073 always be used. */
29b0f896
AM		 5074 if ((i.seg[0]) && (i.seg[0] != default_seg))
5075 {
5076 if (!add_prefix (i.seg[0]->seg_prefix))
5077 return 0;
5078 }
5079 return 1;
5080}
5081
5082static const seg_entry *
e3bb37b5 5083build_modrm_byte (void)
29b0f896
AM		 5084{
5085 const seg_entry *default_seg = 0;
c0f3af97 5086 unsigned int source, dest;
8cd7925b 5087 int vex_3_sources;
c0f3af97
L		 5088
5089 /* The first operand of instructions with VEX prefix and 3 sources
5090 must be VEX_Imm4. */
8cd7925b 5091 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5092 if (vex_3_sources)
5093 {
91d6fa6a 5094 unsigned int nds, reg_slot;
4c2c6516 5095 expressionS *exp;
c0f3af97 5096
922d8de8 5097 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5098 && i.tm.opcode_modifier.immext)
5099 {
5100 dest = i.operands - 2;
5101 gas_assert (dest == 3);
5102 }
922d8de8 5103 else
a683cc34 5104 dest = i.operands - 1;
c0f3af97 5105 nds = dest - 1;
922d8de8 5106
a683cc34
SP		 5107 /* There are 2 kinds of instructions:
5108 1. 5 operands: 4 register operands or 3 register operands
5109 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5110 VexW0 or VexW1. The destination must be either XMM or YMM
5111 register.
5112 2. 4 operands: 4 register operands or 3 register operands
5113 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5114 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5115 || (i.reg_operands == 3 && i.mem_operands == 1))
5116 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5117 && (i.tm.opcode_modifier.veximmext
5118 || (i.imm_operands == 1
5119 && i.types[0].bitfield.vec_imm4
5120 && (i.tm.opcode_modifier.vexw == VEXW0
5121 || i.tm.opcode_modifier.vexw == VEXW1)
5122 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
5123 || operand_type_equal (&i.tm.operand_types[dest], &regymm)))));
5124
5125 if (i.imm_operands == 0)
5126 {
5127 /* When there is no immediate operand, generate an 8bit
5128 immediate operand to encode the first operand. */
5129 exp = &im_expressions[i.imm_operands++];
5130 i.op[i.operands].imms = exp;
5131 i.types[i.operands] = imm8;
5132 i.operands++;
5133 /* If VexW1 is set, the first operand is the source and
5134 the second operand is encoded in the immediate operand. */
5135 if (i.tm.opcode_modifier.vexw == VEXW1)
5136 {
5137 source = 0;
5138 reg_slot = 1;
5139 }
5140 else
5141 {
5142 source = 1;
5143 reg_slot = 0;
5144 }
5145
5146 /* FMA swaps REG and NDS. */
5147 if (i.tm.cpu_flags.bitfield.cpufma)
5148 {
5149 unsigned int tmp;
5150 tmp = reg_slot;
5151 reg_slot = nds;
5152 nds = tmp;
5153 }
5154
24981e7b
L		 5155 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5156 &regxmm)
a683cc34
SP		 5157 || operand_type_equal (&i.tm.operand_types[reg_slot],
5158 &regymm));
5159 exp->X_op = O_constant;
5160 exp->X_add_number
5161 = ((i.op[reg_slot].regs->reg_num
24981e7b
L		 5162 + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0))
5163 << 4);
a683cc34 5164 }
922d8de8 5165 else
a683cc34
SP		 5166 {
5167 unsigned int imm_slot;
5168
5169 if (i.tm.opcode_modifier.vexw == VEXW0)
5170 {
5171 /* If VexW0 is set, the third operand is the source and
5172 the second operand is encoded in the immediate
5173 operand. */
5174 source = 2;
5175 reg_slot = 1;
5176 }
5177 else
5178 {
5179 /* VexW1 is set, the second operand is the source and
5180 the third operand is encoded in the immediate
5181 operand. */
5182 source = 1;
5183 reg_slot = 2;
5184 }
5185
5186 if (i.tm.opcode_modifier.immext)
5187 {
5188 /* When ImmExt is set, the immdiate byte is the last
5189 operand. */
5190 imm_slot = i.operands - 1;
5191 source--;
5192 reg_slot--;
5193 }
5194 else
5195 {
5196 imm_slot = 0;
5197
5198 /* Turn on Imm8 so that output_imm will generate it. */
5199 i.types[imm_slot].bitfield.imm8 = 1;
5200 }
5201
24981e7b
L		 5202 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5203 &regxmm)
5204 || operand_type_equal (&i.tm.operand_types[reg_slot],
5205 &regymm));
a683cc34
SP		 5206 i.op[imm_slot].imms->X_add_number
5207 |= ((i.op[reg_slot].regs->reg_num
24981e7b
L		 5208 + ((i.op[reg_slot].regs->reg_flags & RegRex) ? 8 : 0))
5209 << 4);
a683cc34
SP		 5210 }
5211
5212 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
5213 || operand_type_equal (&i.tm.operand_types[nds],
5214 &regymm));
dae39acc 5215 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 5216 }
5217 else
5218 source = dest = 0;
29b0f896
AM		 5219
5220 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 5221 implicit registers do not count. If there are 3 register
5222 operands, it must be a instruction with VexNDS. For a
5223 instruction with VexNDD, the destination register is encoded
5224 in VEX prefix. If there are 4 register operands, it must be
5225 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 5226 if (i.mem_operands == 0
5227 && ((i.reg_operands == 2
2426c15f 5228 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 5229 || (i.reg_operands == 3
2426c15f 5230 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 5231 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 5232 {
cab737b9
L		 5233 switch (i.operands)
5234 {
5235 case 2:
5236 source = 0;
5237 break;
5238 case 3:
c81128dc
L		 5239 /* When there are 3 operands, one of them may be immediate,
5240 which may be the first or the last operand. Otherwise,
c0f3af97
L		 5241 the first operand must be shift count register (cl) or it
5242 is an instruction with VexNDS. */
9c2799c2 5243 gas_assert (i.imm_operands == 1
7ab9ffdd 5244 || (i.imm_operands == 0
2426c15f 5245 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 5246 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 5247 if (operand_type_check (i.types[0], imm)
5248 || i.types[0].bitfield.shiftcount)
5249 source = 1;
5250 else
5251 source = 0;
cab737b9
L		 5252 break;
5253 case 4:
368d64cc
L		 5254 /* When there are 4 operands, the first two must be 8bit
5255 immediate operands. The source operand will be the 3rd
c0f3af97
L		 5256 one.
5257
5258 For instructions with VexNDS, if the first operand
5259 an imm8, the source operand is the 2nd one. If the last
5260 operand is imm8, the source operand is the first one. */
9c2799c2 5261 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 5262 && i.types[0].bitfield.imm8
5263 && i.types[1].bitfield.imm8)
2426c15f 5264 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 5265 && i.imm_operands == 1
5266 && (i.types[0].bitfield.imm8
5267 || i.types[i.operands - 1].bitfield.imm8)));
9f2670f2
L		 5268 if (i.imm_operands == 2)
5269 source = 2;
5270 else
c0f3af97
L		 5271 {
5272 if (i.types[0].bitfield.imm8)
5273 source = 1;
5274 else
5275 source = 0;
5276 }
c0f3af97
L		 5277 break;
5278 case 5:
cab737b9
L		 5279 break;
5280 default:
5281 abort ();
5282 }
5283
c0f3af97
L		 5284 if (!vex_3_sources)
5285 {
5286 dest = source + 1;
5287
2426c15f 5288 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97
L		 5289 {
5290 /* For instructions with VexNDS, the register-only
5291 source operand must be XMM or YMM register. It is
fa99fab2
L		 5292 encoded in VEX prefix. We need to clear RegMem bit
5293 before calling operand_type_equal. */
5294 i386_operand_type op = i.tm.operand_types[dest];
5295 op.bitfield.regmem = 0;
c0f3af97 5296 if ((dest + 1) >= i.operands
fa99fab2
L		 5297 || (!operand_type_equal (&op, &regxmm)
5298 && !operand_type_equal (&op, &regymm)))
c0f3af97
L		 5299 abort ();
5300 i.vex.register_specifier = i.op[dest].regs;
5301 dest++;
5302 }
5303 }
29b0f896
AM		 5304
5305 i.rm.mode = 3;
5306 /* One of the register operands will be encoded in the i.tm.reg
5307 field, the other in the combined i.tm.mode and i.tm.regmem
5308 fields. If no form of this instruction supports a memory
5309 destination operand, then we assume the source operand may
5310 sometimes be a memory operand and so we need to store the
5311 destination in the i.rm.reg field. */
40fb9820
L		 5312 if (!i.tm.operand_types[dest].bitfield.regmem
5313 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 5314 {
5315 i.rm.reg = i.op[dest].regs->reg_num;
5316 i.rm.regmem = i.op[source].regs->reg_num;
5317 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5318 i.rex |= REX_R;
29b0f896 5319 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5320 i.rex |= REX_B;
29b0f896
AM		 5321 }
5322 else
5323 {
5324 i.rm.reg = i.op[source].regs->reg_num;
5325 i.rm.regmem = i.op[dest].regs->reg_num;
5326 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5327 i.rex |= REX_B;
29b0f896 5328 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5329 i.rex |= REX_R;
29b0f896 5330 }
161a04f6 5331 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 5332 {
40fb9820
L		 5333 if (!i.types[0].bitfield.control
5334 && !i.types[1].bitfield.control)
c4a530c5 5335 abort ();
161a04f6 5336 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 5337 add_prefix (LOCK_PREFIX_OPCODE);
5338 }
29b0f896
AM		 5339 }
5340 else
5341 { /* If it's not 2 reg operands... */
c0f3af97
L		 5342 unsigned int mem;
5343
29b0f896
AM		 5344 if (i.mem_operands)
5345 {
5346 unsigned int fake_zero_displacement = 0;
99018f42 5347 unsigned int op;
4eed87de 5348
7ab9ffdd
L		 5349 for (op = 0; op < i.operands; op++)
5350 if (operand_type_check (i.types[op], anymem))
5351 break;
7ab9ffdd 5352 gas_assert (op < i.operands);
29b0f896
AM		 5353
5354 default_seg = &ds;
5355
5356 if (i.base_reg == 0)
5357 {
5358 i.rm.mode = 0;
5359 if (!i.disp_operands)
5360 fake_zero_displacement = 1;
5361 if (i.index_reg == 0)
5362 {
5363 /* Operand is just <disp> */
20f0a1fc 5364 if (flag_code == CODE_64BIT)
29b0f896
AM		 5365 {
5366 /* 64bit mode overwrites the 32bit absolute
5367 addressing by RIP relative addressing and
5368 absolute addressing is encoded by one of the
5369 redundant SIB forms. */
5370 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5371 i.sib.base = NO_BASE_REGISTER;
5372 i.sib.index = NO_INDEX_REGISTER;
fc225355 5373 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 5374 ? disp32s : disp32);
20f0a1fc 5375 }
fc225355
L		 5376 else if ((flag_code == CODE_16BIT)
5377 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 5378 {
5379 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 5380 i.types[op] = disp16;
20f0a1fc
NC		 5381 }
5382 else
5383 {
5384 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 5385 i.types[op] = disp32;
29b0f896
AM		 5386 }
5387 }
5388 else /* !i.base_reg && i.index_reg */
5389 {
db51cc60
L		 5390 if (i.index_reg->reg_num == RegEiz
5391 || i.index_reg->reg_num == RegRiz)
5392 i.sib.index = NO_INDEX_REGISTER;
5393 else
5394 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5395 i.sib.base = NO_BASE_REGISTER;
5396 i.sib.scale = i.log2_scale_factor;
5397 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 5398 i.types[op].bitfield.disp8 = 0;
5399 i.types[op].bitfield.disp16 = 0;
5400 i.types[op].bitfield.disp64 = 0;
29b0f896 5401 if (flag_code != CODE_64BIT)
40fb9820
L		 5402 {
5403 /* Must be 32 bit */
5404 i.types[op].bitfield.disp32 = 1;
5405 i.types[op].bitfield.disp32s = 0;
5406 }
29b0f896 5407 else
40fb9820
L		 5408 {
5409 i.types[op].bitfield.disp32 = 0;
5410 i.types[op].bitfield.disp32s = 1;
5411 }
29b0f896 5412 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5413 i.rex |= REX_X;
29b0f896
AM		 5414 }
5415 }
5416 /* RIP addressing for 64bit mode. */
9a04903e
JB		 5417 else if (i.base_reg->reg_num == RegRip ||
5418 i.base_reg->reg_num == RegEip)
29b0f896
AM		 5419 {
5420 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5421 i.types[op].bitfield.disp8 = 0;
5422 i.types[op].bitfield.disp16 = 0;
5423 i.types[op].bitfield.disp32 = 0;
5424 i.types[op].bitfield.disp32s = 1;
5425 i.types[op].bitfield.disp64 = 0;
71903a11 5426 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5427 if (! i.disp_operands)
5428 fake_zero_displacement = 1;
29b0f896 5429 }
40fb9820 5430 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 5431 {
5432 switch (i.base_reg->reg_num)
5433 {
5434 case 3: /* (%bx) */
5435 if (i.index_reg == 0)
5436 i.rm.regmem = 7;
5437 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5438 i.rm.regmem = i.index_reg->reg_num - 6;
5439 break;
5440 case 5: /* (%bp) */
5441 default_seg = &ss;
5442 if (i.index_reg == 0)
5443 {
5444 i.rm.regmem = 6;
40fb9820 5445 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5446 {
5447 /* fake (%bp) into 0(%bp) */
40fb9820 5448 i.types[op].bitfield.disp8 = 1;
252b5132 5449 fake_zero_displacement = 1;
29b0f896
AM		 5450 }
5451 }
5452 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5453 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5454 break;
5455 default: /* (%si) -> 4 or (%di) -> 5 */
5456 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5457 }
5458 i.rm.mode = mode_from_disp_size (i.types[op]);
5459 }
5460 else /* i.base_reg and 32/64 bit mode */
5461 {
5462 if (flag_code == CODE_64BIT
40fb9820
L		 5463 && operand_type_check (i.types[op], disp))
5464 {
5465 i386_operand_type temp;
0dfbf9d7 5466 operand_type_set (&temp, 0);
40fb9820
L		 5467 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5468 i.types[op] = temp;
5469 if (i.prefix[ADDR_PREFIX] == 0)
5470 i.types[op].bitfield.disp32s = 1;
5471 else
5472 i.types[op].bitfield.disp32 = 1;
5473 }
20f0a1fc 5474
29b0f896
AM		 5475 i.rm.regmem = i.base_reg->reg_num;
5476 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5477 i.rex |= REX_B;
29b0f896
AM		 5478 i.sib.base = i.base_reg->reg_num;
5479 /* x86-64 ignores REX prefix bit here to avoid decoder
5480 complications. */
5481 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5482 {
5483 default_seg = &ss;
5484 if (i.disp_operands == 0)
5485 {
5486 fake_zero_displacement = 1;
40fb9820 5487 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5488 }
5489 }
5490 else if (i.base_reg->reg_num == ESP_REG_NUM)
5491 {
5492 default_seg = &ss;
5493 }
5494 i.sib.scale = i.log2_scale_factor;
5495 if (i.index_reg == 0)
5496 {
5497 /* <disp>(%esp) becomes two byte modrm with no index
5498 register. We've already stored the code for esp
5499 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5500 Any base register besides %esp will not use the
5501 extra modrm byte. */
5502 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 5503 }
5504 else
5505 {
db51cc60
L		 5506 if (i.index_reg->reg_num == RegEiz
5507 || i.index_reg->reg_num == RegRiz)
5508 i.sib.index = NO_INDEX_REGISTER;
5509 else
5510 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5511 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5512 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5513 i.rex |= REX_X;
29b0f896 5514 }
67a4f2b7
AO		 5515
5516 if (i.disp_operands
5517 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5518 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5519 i.rm.mode = 0;
5520 else
5521 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 5522 }
252b5132 5523
29b0f896
AM		 5524 if (fake_zero_displacement)
5525 {
5526 /* Fakes a zero displacement assuming that i.types[op]
5527 holds the correct displacement size. */
5528 expressionS *exp;
5529
9c2799c2 5530 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 5531 exp = &disp_expressions[i.disp_operands++];
5532 i.op[op].disps = exp;
5533 exp->X_op = O_constant;
5534 exp->X_add_number = 0;
5535 exp->X_add_symbol = (symbolS *) 0;
5536 exp->X_op_symbol = (symbolS *) 0;
5537 }
c0f3af97
L		 5538
5539 mem = op;
29b0f896 5540 }
c0f3af97
L		 5541 else
5542 mem = ~0;
252b5132 5543
8c43a48b 5544 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 5545 {
5546 if (operand_type_check (i.types[0], imm))
5547 i.vex.register_specifier = NULL;
5548 else
5549 {
5550 /* VEX.vvvv encodes one of the sources when the first
5551 operand is not an immediate. */
1ef99a7b 5552 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5553 i.vex.register_specifier = i.op[0].regs;
5554 else
5555 i.vex.register_specifier = i.op[1].regs;
5556 }
5557
5558 /* Destination is a XMM register encoded in the ModRM.reg
5559 and VEX.R bit. */
5560 i.rm.reg = i.op[2].regs->reg_num;
5561 if ((i.op[2].regs->reg_flags & RegRex) != 0)
5562 i.rex |= REX_R;
5563
5564 /* ModRM.rm and VEX.B encodes the other source. */
5565 if (!i.mem_operands)
5566 {
5567 i.rm.mode = 3;
5568
1ef99a7b 5569 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 5570 i.rm.regmem = i.op[1].regs->reg_num;
5571 else
5572 i.rm.regmem = i.op[0].regs->reg_num;
5573
5574 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5575 i.rex |= REX_B;
5576 }
5577 }
2426c15f 5578 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 5579 {
5580 i.vex.register_specifier = i.op[2].regs;
5581 if (!i.mem_operands)
5582 {
5583 i.rm.mode = 3;
5584 i.rm.regmem = i.op[1].regs->reg_num;
5585 if ((i.op[1].regs->reg_flags & RegRex) != 0)
5586 i.rex |= REX_B;
5587 }
5588 }
29b0f896
AM		 5589 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5590 (if any) based on i.tm.extension_opcode. Again, we must be
5591 careful to make sure that segment/control/debug/test/MMX
5592 registers are coded into the i.rm.reg field. */
f88c9eb0 5593 else if (i.reg_operands)
29b0f896 5594 {
99018f42 5595 unsigned int op;
7ab9ffdd
L		 5596 unsigned int vex_reg = ~0;
5597
5598 for (op = 0; op < i.operands; op++)
5599 if (i.types[op].bitfield.reg8
5600 || i.types[op].bitfield.reg16
5601 || i.types[op].bitfield.reg32
5602 || i.types[op].bitfield.reg64
5603 || i.types[op].bitfield.regmmx
5604 || i.types[op].bitfield.regxmm
5605 || i.types[op].bitfield.regymm
5606 || i.types[op].bitfield.sreg2
5607 || i.types[op].bitfield.sreg3
5608 || i.types[op].bitfield.control
5609 || i.types[op].bitfield.debug
5610 || i.types[op].bitfield.test)
5611 break;
c0209578 5612
7ab9ffdd
L		 5613 if (vex_3_sources)
5614 op = dest;
2426c15f 5615 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 5616 {
5617 /* For instructions with VexNDS, the register-only
5618 source operand is encoded in VEX prefix. */
5619 gas_assert (mem != (unsigned int) ~0);
c0f3af97 5620
7ab9ffdd 5621 if (op > mem)
c0f3af97 5622 {
7ab9ffdd
L		 5623 vex_reg = op++;
5624 gas_assert (op < i.operands);
c0f3af97
L		 5625 }
5626 else
c0f3af97 5627 {
7ab9ffdd
L		 5628 vex_reg = op + 1;
5629 gas_assert (vex_reg < i.operands);
c0f3af97 5630 }
7ab9ffdd 5631 }
2426c15f 5632 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd
L		 5633 {
5634 /* For instructions with VexNDD, there should be
5635 no memory operand and the register destination
5636 is encoded in VEX prefix. */
5637 gas_assert (i.mem_operands == 0
5638 && (op + 2) == i.operands);
5639 vex_reg = op + 1;
5640 }
5641 else
5642 gas_assert (op < i.operands);
99018f42 5643
7ab9ffdd
L		 5644 if (vex_reg != (unsigned int) ~0)
5645 {
5646 gas_assert (i.reg_operands == 2);
5647
5648 if (!operand_type_equal (&i.tm.operand_types[vex_reg],
76ba9986 5649 &regxmm)
7ab9ffdd
L		 5650 && !operand_type_equal (&i.tm.operand_types[vex_reg],
5651 &regymm))
5652 abort ();
f88c9eb0 5653
7ab9ffdd
L		 5654 i.vex.register_specifier = i.op[vex_reg].regs;
5655 }
5656
1b9f0c97
L		 5657 /* Don't set OP operand twice. */
5658 if (vex_reg != op)
7ab9ffdd 5659 {
1b9f0c97
L		 5660 /* If there is an extension opcode to put here, the
5661 register number must be put into the regmem field. */
5662 if (i.tm.extension_opcode != None)
5663 {
5664 i.rm.regmem = i.op[op].regs->reg_num;
5665 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5666 i.rex |= REX_B;
5667 }
5668 else
5669 {
5670 i.rm.reg = i.op[op].regs->reg_num;
5671 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5672 i.rex |= REX_R;
5673 }
7ab9ffdd 5674 }
252b5132 5675
29b0f896
AM		 5676 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5677 must set it to 3 to indicate this is a register operand
5678 in the regmem field. */
5679 if (!i.mem_operands)
5680 i.rm.mode = 3;
5681 }
252b5132 5682
29b0f896 5683 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 5684 if (i.tm.extension_opcode != None)
29b0f896
AM		 5685 i.rm.reg = i.tm.extension_opcode;
5686 }
5687 return default_seg;
5688}
252b5132 5689
29b0f896 5690static void
e3bb37b5 5691output_branch (void)
29b0f896
AM		 5692{
5693 char *p;
5694 int code16;
5695 int prefix;
5696 relax_substateT subtype;
5697 symbolS *sym;
5698 offsetT off;
5699
5700 code16 = 0;
5701 if (flag_code == CODE_16BIT)
5702 code16 = CODE16;
5703
5704 prefix = 0;
5705 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5706 {
29b0f896
AM		 5707 prefix = 1;
5708 i.prefixes -= 1;
5709 code16 ^= CODE16;
252b5132 5710 }
29b0f896
AM		 5711 /* Pentium4 branch hints. */
5712 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5713 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5714 {
29b0f896
AM		 5715 prefix++;
5716 i.prefixes--;
5717 }
5718 if (i.prefix[REX_PREFIX] != 0)
5719 {
5720 prefix++;
5721 i.prefixes--;
2f66722d
AM		 5722 }
5723
29b0f896
AM		 5724 if (i.prefixes != 0 && !intel_syntax)
5725 as_warn (_("skipping prefixes on this instruction"));
5726
5727 /* It's always a symbol; End frag & setup for relax.
5728 Make sure there is enough room in this frag for the largest
5729 instruction we may generate in md_convert_frag. This is 2
5730 bytes for the opcode and room for the prefix and largest
5731 displacement. */
5732 frag_grow (prefix + 2 + 4);
5733 /* Prefix and 1 opcode byte go in fr_fix. */
5734 p = frag_more (prefix + 1);
5735 if (i.prefix[DATA_PREFIX] != 0)
5736 *p++ = DATA_PREFIX_OPCODE;
5737 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5738 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5739 *p++ = i.prefix[SEG_PREFIX];
5740 if (i.prefix[REX_PREFIX] != 0)
5741 *p++ = i.prefix[REX_PREFIX];
5742 *p = i.tm.base_opcode;
5743
5744 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5745 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 5746 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 5747 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5748 else
5749 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5750 subtype |= code16;
3e73aa7c 5751
29b0f896
AM		 5752 sym = i.op[0].disps->X_add_symbol;
5753 off = i.op[0].disps->X_add_number;
3e73aa7c 5754
29b0f896
AM		 5755 if (i.op[0].disps->X_op != O_constant
5756 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5757 {
29b0f896
AM		 5758 /* Handle complex expressions. */
5759 sym = make_expr_symbol (i.op[0].disps);
5760 off = 0;
5761 }
3e73aa7c 5762
29b0f896
AM		 5763 /* 1 possible extra opcode + 4 byte displacement go in var part.
5764 Pass reloc in fr_var. */
5765 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5766}
3e73aa7c 5767
29b0f896 5768static void
e3bb37b5 5769output_jump (void)
29b0f896
AM		 5770{
5771 char *p;
5772 int size;
3e02c1cc 5773 fixS *fixP;
29b0f896 5774
40fb9820 5775 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 5776 {
5777 /* This is a loop or jecxz type instruction. */
5778 size = 1;
5779 if (i.prefix[ADDR_PREFIX] != 0)
5780 {
5781 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5782 i.prefixes -= 1;
5783 }
5784 /* Pentium4 branch hints. */
5785 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5786 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5787 {
5788 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5789 i.prefixes--;
3e73aa7c
JH		 5790 }
5791 }
29b0f896
AM		 5792 else
5793 {
5794 int code16;
3e73aa7c 5795
29b0f896
AM		 5796 code16 = 0;
5797 if (flag_code == CODE_16BIT)
5798 code16 = CODE16;
3e73aa7c 5799
29b0f896
AM		 5800 if (i.prefix[DATA_PREFIX] != 0)
5801 {
5802 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5803 i.prefixes -= 1;
5804 code16 ^= CODE16;
5805 }
252b5132 5806
29b0f896
AM		 5807 size = 4;
5808 if (code16)
5809 size = 2;
5810 }
9fcc94b6 5811
29b0f896
AM		 5812 if (i.prefix[REX_PREFIX] != 0)
5813 {
5814 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5815 i.prefixes -= 1;
5816 }
252b5132 5817
29b0f896
AM		 5818 if (i.prefixes != 0 && !intel_syntax)
5819 as_warn (_("skipping prefixes on this instruction"));
e0890092 5820
29b0f896
AM		 5821 p = frag_more (1 + size);
5822 *p++ = i.tm.base_opcode;
e0890092 5823
3e02c1cc
AM		 5824 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5825 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5826
5827 /* All jumps handled here are signed, but don't use a signed limit
5828 check for 32 and 16 bit jumps as we want to allow wrap around at
5829 4G and 64k respectively. */
5830 if (size == 1)
5831 fixP->fx_signed = 1;
29b0f896 5832}
e0890092 5833
29b0f896 5834static void
e3bb37b5 5835output_interseg_jump (void)
29b0f896
AM		 5836{
5837 char *p;
5838 int size;
5839 int prefix;
5840 int code16;
252b5132 5841
29b0f896
AM		 5842 code16 = 0;
5843 if (flag_code == CODE_16BIT)
5844 code16 = CODE16;
a217f122 5845
29b0f896
AM		 5846 prefix = 0;
5847 if (i.prefix[DATA_PREFIX] != 0)
5848 {
5849 prefix = 1;
5850 i.prefixes -= 1;
5851 code16 ^= CODE16;
5852 }
5853 if (i.prefix[REX_PREFIX] != 0)
5854 {
5855 prefix++;
5856 i.prefixes -= 1;
5857 }
252b5132 5858
29b0f896
AM		 5859 size = 4;
5860 if (code16)
5861 size = 2;
252b5132 5862
29b0f896
AM		 5863 if (i.prefixes != 0 && !intel_syntax)
5864 as_warn (_("skipping prefixes on this instruction"));
252b5132 5865
29b0f896
AM		 5866 /* 1 opcode; 2 segment; offset */
5867 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 5868
29b0f896
AM		 5869 if (i.prefix[DATA_PREFIX] != 0)
5870 *p++ = DATA_PREFIX_OPCODE;
252b5132 5871
29b0f896
AM		 5872 if (i.prefix[REX_PREFIX] != 0)
5873 *p++ = i.prefix[REX_PREFIX];
252b5132 5874
29b0f896
AM		 5875 *p++ = i.tm.base_opcode;
5876 if (i.op[1].imms->X_op == O_constant)
5877 {
5878 offsetT n = i.op[1].imms->X_add_number;
252b5132 5879
29b0f896
AM		 5880 if (size == 2
5881 && !fits_in_unsigned_word (n)
5882 && !fits_in_signed_word (n))
5883 {
5884 as_bad (_("16-bit jump out of range"));
5885 return;
5886 }
5887 md_number_to_chars (p, n, size);
5888 }
5889 else
5890 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5891 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5892 if (i.op[0].imms->X_op != O_constant)
5893 as_bad (_("can't handle non absolute segment in `%s'"),
5894 i.tm.name);
5895 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5896}
a217f122 5897
29b0f896 5898static void
e3bb37b5 5899output_insn (void)
29b0f896 5900{
2bbd9c25
JJ		 5901 fragS *insn_start_frag;
5902 offsetT insn_start_off;
5903
29b0f896
AM		 5904 /* Tie dwarf2 debug info to the address at the start of the insn.
5905 We can't do this after the insn has been output as the current
5906 frag may have been closed off. eg. by frag_var. */
5907 dwarf2_emit_insn (0);
5908
2bbd9c25
JJ		 5909 insn_start_frag = frag_now;
5910 insn_start_off = frag_now_fix ();
5911
29b0f896 5912 /* Output jumps. */
40fb9820 5913 if (i.tm.opcode_modifier.jump)
29b0f896 5914 output_branch ();
40fb9820
L		 5915 else if (i.tm.opcode_modifier.jumpbyte
5916 || i.tm.opcode_modifier.jumpdword)
29b0f896 5917 output_jump ();
40fb9820 5918 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 5919 output_interseg_jump ();
5920 else
5921 {
5922 /* Output normal instructions here. */
5923 char *p;
5924 unsigned char *q;
47465058 5925 unsigned int j;
331d2d0d 5926 unsigned int prefix;
4dffcebc 5927
c0f3af97
L		 5928 /* Since the VEX prefix contains the implicit prefix, we don't
5929 need the explicit prefix. */
5930 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 5931 {
c0f3af97 5932 switch (i.tm.opcode_length)
bc4bd9ab 5933 {
c0f3af97
L		 5934 case 3:
5935 if (i.tm.base_opcode & 0xff000000)
4dffcebc 5936 {
c0f3af97
L		 5937 prefix = (i.tm.base_opcode >> 24) & 0xff;
5938 goto check_prefix;
5939 }
5940 break;
5941 case 2:
5942 if ((i.tm.base_opcode & 0xff0000) != 0)
5943 {
5944 prefix = (i.tm.base_opcode >> 16) & 0xff;
5945 if (i.tm.cpu_flags.bitfield.cpupadlock)
5946 {
4dffcebc 5947check_prefix:
c0f3af97 5948 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 5949 || (i.prefix[REP_PREFIX]
c0f3af97
L		 5950 != REPE_PREFIX_OPCODE))
5951 add_prefix (prefix);
5952 }
5953 else
4dffcebc
L		 5954 add_prefix (prefix);
5955 }
c0f3af97
L		 5956 break;
5957 case 1:
5958 break;
5959 default:
5960 abort ();
bc4bd9ab 5961 }
c0f3af97
L		 5962
5963 /* The prefix bytes. */
5964 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5965 if (*q)
5966 FRAG_APPEND_1_CHAR (*q);
0f10071e 5967 }
252b5132 5968
c0f3af97
L		 5969 if (i.tm.opcode_modifier.vex)
5970 {
5971 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
5972 if (*q)
5973 switch (j)
5974 {
5975 case REX_PREFIX:
5976 /* REX byte is encoded in VEX prefix. */
5977 break;
5978 case SEG_PREFIX:
5979 case ADDR_PREFIX:
5980 FRAG_APPEND_1_CHAR (*q);
5981 break;
5982 default:
5983 /* There should be no other prefixes for instructions
5984 with VEX prefix. */
5985 abort ();
5986 }
5987
5988 /* Now the VEX prefix. */
5989 p = frag_more (i.vex.length);
5990 for (j = 0; j < i.vex.length; j++)
5991 p[j] = i.vex.bytes[j];
5992 }
252b5132 5993
29b0f896 5994 /* Now the opcode; be careful about word order here! */
4dffcebc 5995 if (i.tm.opcode_length == 1)
29b0f896
AM		 5996 {
5997 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5998 }
5999 else
6000 {
4dffcebc 6001 switch (i.tm.opcode_length)
331d2d0d 6002 {
4dffcebc 6003 case 3:
331d2d0d
L		 6004 p = frag_more (3);
6005 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 6006 break;
6007 case 2:
6008 p = frag_more (2);
6009 break;
6010 default:
6011 abort ();
6012 break;
331d2d0d 6013 }
0f10071e 6014
29b0f896
AM		 6015 /* Put out high byte first: can't use md_number_to_chars! */
6016 *p++ = (i.tm.base_opcode >> 8) & 0xff;
6017 *p = i.tm.base_opcode & 0xff;
6018 }
3e73aa7c 6019
29b0f896 6020 /* Now the modrm byte and sib byte (if present). */
40fb9820 6021 if (i.tm.opcode_modifier.modrm)
29b0f896 6022 {
4a3523fa
L		 6023 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
6024 | i.rm.reg << 3
6025 | i.rm.mode << 6));
29b0f896
AM		 6026 /* If i.rm.regmem == ESP (4)
6027 && i.rm.mode != (Register mode)
6028 && not 16 bit
6029 ==> need second modrm byte. */
6030 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
6031 && i.rm.mode != 3
40fb9820 6032 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 6033 FRAG_APPEND_1_CHAR ((i.sib.base << 0
6034 | i.sib.index << 3
6035 | i.sib.scale << 6));
29b0f896 6036 }
3e73aa7c 6037
29b0f896 6038 if (i.disp_operands)
2bbd9c25 6039 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 6040
29b0f896 6041 if (i.imm_operands)
2bbd9c25 6042 output_imm (insn_start_frag, insn_start_off);
29b0f896 6043 }
252b5132 6044
29b0f896
AM		 6045#ifdef DEBUG386
6046 if (flag_debug)
6047 {
7b81dfbb 6048 pi ("" /*line*/, &i);
29b0f896
AM		 6049 }
6050#endif /* DEBUG386 */
6051}
252b5132 6052
e205caa7
L		 6053/* Return the size of the displacement operand N. */
6054
6055static int
6056disp_size (unsigned int n)
6057{
6058 int size = 4;
40fb9820
L		 6059 if (i.types[n].bitfield.disp64)
6060 size = 8;
6061 else if (i.types[n].bitfield.disp8)
6062 size = 1;
6063 else if (i.types[n].bitfield.disp16)
6064 size = 2;
e205caa7
L		 6065 return size;
6066}
6067
6068/* Return the size of the immediate operand N. */
6069
6070static int
6071imm_size (unsigned int n)
6072{
6073 int size = 4;
40fb9820
L		 6074 if (i.types[n].bitfield.imm64)
6075 size = 8;
6076 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
6077 size = 1;
6078 else if (i.types[n].bitfield.imm16)
6079 size = 2;
e205caa7
L		 6080 return size;
6081}
6082
29b0f896 6083static void
64e74474 6084output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6085{
6086 char *p;
6087 unsigned int n;
252b5132 6088
29b0f896
AM		 6089 for (n = 0; n < i.operands; n++)
6090 {
40fb9820 6091 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 6092 {
6093 if (i.op[n].disps->X_op == O_constant)
6094 {
e205caa7 6095 int size = disp_size (n);
29b0f896 6096 offsetT val;
252b5132 6097
29b0f896
AM		 6098 val = offset_in_range (i.op[n].disps->X_add_number,
6099 size);
6100 p = frag_more (size);
6101 md_number_to_chars (p, val, size);
6102 }
6103 else
6104 {
f86103b7 6105 enum bfd_reloc_code_real reloc_type;
e205caa7 6106 int size = disp_size (n);
40fb9820 6107 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 6108 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
6109
e205caa7 6110 /* We can't have 8 bit displacement here. */
9c2799c2 6111 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 6112
29b0f896
AM		 6113 /* The PC relative address is computed relative
6114 to the instruction boundary, so in case immediate
6115 fields follows, we need to adjust the value. */
6116 if (pcrel && i.imm_operands)
6117 {
29b0f896 6118 unsigned int n1;
e205caa7 6119 int sz = 0;
252b5132 6120
29b0f896 6121 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 6122 if (operand_type_check (i.types[n1], imm))
252b5132 6123 {
e205caa7
L		 6124 /* Only one immediate is allowed for PC
6125 relative address. */
9c2799c2 6126 gas_assert (sz == 0);
e205caa7
L		 6127 sz = imm_size (n1);
6128 i.op[n].disps->X_add_number -= sz;
252b5132 6129 }
29b0f896 6130 /* We should find the immediate. */
9c2799c2 6131 gas_assert (sz != 0);
29b0f896 6132 }
520dc8e8 6133
29b0f896 6134 p = frag_more (size);
2bbd9c25 6135 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 6136 if (GOT_symbol
2bbd9c25 6137 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 6138 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6139 || reloc_type == BFD_RELOC_X86_64_32S
6140 || (reloc_type == BFD_RELOC_64
6141 && object_64bit))
d6ab8113
JB		 6142 && (i.op[n].disps->X_op == O_symbol
6143 || (i.op[n].disps->X_op == O_add
6144 && ((symbol_get_value_expression
6145 (i.op[n].disps->X_op_symbol)->X_op)
6146 == O_subtract))))
6147 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 6148 {
6149 offsetT add;
6150
6151 if (insn_start_frag == frag_now)
6152 add = (p - frag_now->fr_literal) - insn_start_off;
6153 else
6154 {
6155 fragS *fr;
6156
6157 add = insn_start_frag->fr_fix - insn_start_off;
6158 for (fr = insn_start_frag->fr_next;
6159 fr && fr != frag_now; fr = fr->fr_next)
6160 add += fr->fr_fix;
6161 add += p - frag_now->fr_literal;
6162 }
6163
4fa24527 6164 if (!object_64bit)
7b81dfbb
AJ		 6165 {
6166 reloc_type = BFD_RELOC_386_GOTPC;
6167 i.op[n].imms->X_add_number += add;
6168 }
6169 else if (reloc_type == BFD_RELOC_64)
6170 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 6171 else
7b81dfbb
AJ		 6172 /* Don't do the adjustment for x86-64, as there
6173 the pcrel addressing is relative to the _next_
6174 insn, and that is taken care of in other code. */
d6ab8113 6175 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 6176 }
062cd5e7 6177 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 6178 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 6179 }
6180 }
6181 }
6182}
252b5132 6183
29b0f896 6184static void
64e74474 6185output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6186{
6187 char *p;
6188 unsigned int n;
252b5132 6189
29b0f896
AM		 6190 for (n = 0; n < i.operands; n++)
6191 {
40fb9820 6192 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 6193 {
6194 if (i.op[n].imms->X_op == O_constant)
6195 {
e205caa7 6196 int size = imm_size (n);
29b0f896 6197 offsetT val;
b4cac588 6198
29b0f896
AM		 6199 val = offset_in_range (i.op[n].imms->X_add_number,
6200 size);
6201 p = frag_more (size);
6202 md_number_to_chars (p, val, size);
6203 }
6204 else
6205 {
6206 /* Not absolute_section.
6207 Need a 32-bit fixup (don't support 8bit
6208 non-absolute imms). Try to support other
6209 sizes ... */
f86103b7 6210 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 6211 int size = imm_size (n);
6212 int sign;
29b0f896 6213
40fb9820 6214 if (i.types[n].bitfield.imm32s
a7d61044 6215 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 6216 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 6217 sign = 1;
e205caa7
L		 6218 else
6219 sign = 0;
520dc8e8 6220
29b0f896
AM		 6221 p = frag_more (size);
6222 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 6223
2bbd9c25
JJ		 6224 /* This is tough to explain. We end up with this one if we
6225 * have operands that look like
6226 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6227 * obtain the absolute address of the GOT, and it is strongly
6228 * preferable from a performance point of view to avoid using
6229 * a runtime relocation for this. The actual sequence of
6230 * instructions often look something like:
6231 *
6232 * call .L66
6233 * .L66:
6234 * popl %ebx
6235 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6236 *
6237 * The call and pop essentially return the absolute address
6238 * of the label .L66 and store it in %ebx. The linker itself
6239 * will ultimately change the first operand of the addl so
6240 * that %ebx points to the GOT, but to keep things simple, the
6241 * .o file must have this operand set so that it generates not
6242 * the absolute address of .L66, but the absolute address of
6243 * itself. This allows the linker itself simply treat a GOTPC
6244 * relocation as asking for a pcrel offset to the GOT to be
6245 * added in, and the addend of the relocation is stored in the
6246 * operand field for the instruction itself.
6247 *
6248 * Our job here is to fix the operand so that it would add
6249 * the correct offset so that %ebx would point to itself. The
6250 * thing that is tricky is that .-.L66 will point to the
6251 * beginning of the instruction, so we need to further modify
6252 * the operand so that it will point to itself. There are
6253 * other cases where you have something like:
6254 *
6255 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6256 *
6257 * and here no correction would be required. Internally in
6258 * the assembler we treat operands of this form as not being
6259 * pcrel since the '.' is explicitly mentioned, and I wonder
6260 * whether it would simplify matters to do it this way. Who
6261 * knows. In earlier versions of the PIC patches, the
6262 * pcrel_adjust field was used to store the correction, but
6263 * since the expression is not pcrel, I felt it would be
6264 * confusing to do it this way. */
6265
d6ab8113 6266 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6267 || reloc_type == BFD_RELOC_X86_64_32S
6268 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 6269 && GOT_symbol
6270 && GOT_symbol == i.op[n].imms->X_add_symbol
6271 && (i.op[n].imms->X_op == O_symbol
6272 || (i.op[n].imms->X_op == O_add
6273 && ((symbol_get_value_expression
6274 (i.op[n].imms->X_op_symbol)->X_op)
6275 == O_subtract))))
6276 {
2bbd9c25
JJ		 6277 offsetT add;
6278
6279 if (insn_start_frag == frag_now)
6280 add = (p - frag_now->fr_literal) - insn_start_off;
6281 else
6282 {
6283 fragS *fr;
6284
6285 add = insn_start_frag->fr_fix - insn_start_off;
6286 for (fr = insn_start_frag->fr_next;
6287 fr && fr != frag_now; fr = fr->fr_next)
6288 add += fr->fr_fix;
6289 add += p - frag_now->fr_literal;
6290 }
6291
4fa24527 6292 if (!object_64bit)
d6ab8113 6293 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 6294 else if (size == 4)
d6ab8113 6295 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 6296 else if (size == 8)
6297 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 6298 i.op[n].imms->X_add_number += add;
29b0f896 6299 }
29b0f896
AM		 6300 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6301 i.op[n].imms, 0, reloc_type);
6302 }
6303 }
6304 }
252b5132
RH		 6305}
6306\f
d182319b
JB		 6307/* x86_cons_fix_new is called via the expression parsing code when a
6308 reloc is needed. We use this hook to get the correct .got reloc. */
6309static enum bfd_reloc_code_real got_reloc = NO_RELOC;
6310static int cons_sign = -1;
6311
6312void
e3bb37b5 6313x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 6314 expressionS *exp)
d182319b
JB		 6315{
6316 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
6317
6318 got_reloc = NO_RELOC;
6319
6320#ifdef TE_PE
6321 if (exp->X_op == O_secrel)
6322 {
6323 exp->X_op = O_symbol;
6324 r = BFD_RELOC_32_SECREL;
6325 }
6326#endif
6327
6328 fix_new_exp (frag, off, len, exp, 0, r);
6329}
6330
718ddfc0
JB		 6331#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6332# define lex_got(reloc, adjust, types) NULL
6333#else
f3c180ae
AM		 6334/* Parse operands of the form
6335 <symbol>@GOTOFF+<nnn>
6336 and similar .plt or .got references.
6337
6338 If we find one, set up the correct relocation in RELOC and copy the
6339 input string, minus the `@GOTOFF' into a malloc'd buffer for
6340 parsing by the calling routine. Return this buffer, and if ADJUST
6341 is non-null set it to the length of the string we removed from the
6342 input line. Otherwise return NULL. */
6343static char *
91d6fa6a 6344lex_got (enum bfd_reloc_code_real *rel,
64e74474 6345 int *adjust,
40fb9820 6346 i386_operand_type *types)
f3c180ae 6347{
7b81dfbb
AJ		 6348 /* Some of the relocations depend on the size of what field is to
6349 be relocated. But in our callers i386_immediate and i386_displacement
6350 we don't yet know the operand size (this will be set by insn
6351 matching). Hence we record the word32 relocation here,
6352 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 6353 static const struct {
6354 const char *str;
cff8d58a 6355 int len;
4fa24527 6356 const enum bfd_reloc_code_real rel[2];
40fb9820 6357 const i386_operand_type types64;
f3c180ae 6358 } gotrel[] = {
cff8d58a
L		 6359 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
6360 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 6361 OPERAND_TYPE_IMM64 },
cff8d58a
L		 6362 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
6363 BFD_RELOC_X86_64_PLT32 },
40fb9820 6364 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6365 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
6366 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 6367 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 6368 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
6369 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 6370 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 6371 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
6372 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 6373 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6374 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
6375 BFD_RELOC_X86_64_TLSGD },
40fb9820 6376 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6377 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
6378 _dummy_first_bfd_reloc_code_real },
40fb9820 6379 OPERAND_TYPE_NONE },
cff8d58a
L		 6380 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
6381 BFD_RELOC_X86_64_TLSLD },
40fb9820 6382 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6383 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
6384 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 6385 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6386 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
6387 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 6388 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 6389 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
6390 _dummy_first_bfd_reloc_code_real },
40fb9820 6391 OPERAND_TYPE_NONE },
cff8d58a
L		 6392 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
6393 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 6394 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 6395 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
6396 _dummy_first_bfd_reloc_code_real },
40fb9820 6397 OPERAND_TYPE_NONE },
cff8d58a
L		 6398 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
6399 _dummy_first_bfd_reloc_code_real },
40fb9820 6400 OPERAND_TYPE_NONE },
cff8d58a
L		 6401 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
6402 BFD_RELOC_X86_64_GOT32 },
40fb9820 6403 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 6404 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
6405 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 6406 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 6407 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
6408 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 6409 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 6410 };
6411 char *cp;
6412 unsigned int j;
6413
718ddfc0
JB		 6414 if (!IS_ELF)
6415 return NULL;
6416
f3c180ae 6417 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 6418 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 6419 return NULL;
6420
47465058 6421 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 6422 {
cff8d58a 6423 int len = gotrel[j].len;
28f81592 6424 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 6425 {
4fa24527 6426 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 6427 {
28f81592
AM		 6428 int first, second;
6429 char *tmpbuf, *past_reloc;
f3c180ae 6430
91d6fa6a 6431 *rel = gotrel[j].rel[object_64bit];
28f81592
AM		 6432 if (adjust)
6433 *adjust = len;
f3c180ae 6434
3956db08
JB		 6435 if (types)
6436 {
6437 if (flag_code != CODE_64BIT)
40fb9820
L		 6438 {
6439 types->bitfield.imm32 = 1;
6440 types->bitfield.disp32 = 1;
6441 }
3956db08
JB		 6442 else
6443 *types = gotrel[j].types64;
6444 }
6445
f3c180ae
AM		 6446 if (GOT_symbol == NULL)
6447 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6448
28f81592 6449 /* The length of the first part of our input line. */
f3c180ae 6450 first = cp - input_line_pointer;
28f81592
AM		 6451
6452 /* The second part goes from after the reloc token until
67c11a9b 6453 (and including) an end_of_line char or comma. */
28f81592 6454 past_reloc = cp + 1 + len;
67c11a9b
AM		 6455 cp = past_reloc;
6456 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6457 ++cp;
6458 second = cp + 1 - past_reloc;
28f81592
AM		 6459
6460 /* Allocate and copy string. The trailing NUL shouldn't
6461 be necessary, but be safe. */
1e9cc1c2 6462 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 6463 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 6464 if (second != 0 && *past_reloc != ' ')
6465 /* Replace the relocation token with ' ', so that
6466 errors like foo@GOTOFF1 will be detected. */
6467 tmpbuf[first++] = ' ';
6468 memcpy (tmpbuf + first, past_reloc, second);
6469 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6470 return tmpbuf;
6471 }
6472
4fa24527
JB		 6473 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6474 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6475 return NULL;
6476 }
6477 }
6478
6479 /* Might be a symbol version string. Don't as_bad here. */
6480 return NULL;
6481}
6482
f3c180ae 6483void
e3bb37b5 6484x86_cons (expressionS *exp, int size)
f3c180ae 6485{
ee86248c
JB		 6486 intel_syntax = -intel_syntax;
6487
3c7b9c2c 6488 exp->X_md = 0;
4fa24527 6489 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6490 {
6491 /* Handle @GOTOFF and the like in an expression. */
6492 char *save;
6493 char *gotfree_input_line;
6494 int adjust;
6495
6496 save = input_line_pointer;
3956db08 6497 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6498 if (gotfree_input_line)
6499 input_line_pointer = gotfree_input_line;
6500
6501 expression (exp);
6502
6503 if (gotfree_input_line)
6504 {
6505 /* expression () has merrily parsed up to the end of line,
6506 or a comma - in the wrong buffer. Transfer how far
6507 input_line_pointer has moved to the right buffer. */
6508 input_line_pointer = (save
6509 + (input_line_pointer - gotfree_input_line)
6510 + adjust);
6511 free (gotfree_input_line);
3992d3b7
AM		 6512 if (exp->X_op == O_constant
6513 || exp->X_op == O_absent
6514 || exp->X_op == O_illegal
0398aac5 6515 || exp->X_op == O_register
3992d3b7
AM		 6516 || exp->X_op == O_big)
6517 {
6518 char c = *input_line_pointer;
6519 *input_line_pointer = 0;
6520 as_bad (_("missing or invalid expression `%s'"), save);
6521 *input_line_pointer = c;
6522 }
f3c180ae
AM		 6523 }
6524 }
6525 else
6526 expression (exp);
ee86248c
JB		 6527
6528 intel_syntax = -intel_syntax;
6529
6530 if (intel_syntax)
6531 i386_intel_simplify (exp);
f3c180ae
AM		 6532}
6533#endif
6534
9f32dd5b
L		 6535static void
6536signed_cons (int size)
6482c264 6537{
d182319b
JB		 6538 if (flag_code == CODE_64BIT)
6539 cons_sign = 1;
6540 cons (size);
6541 cons_sign = -1;
6482c264
NC		 6542}
6543
d182319b 6544#ifdef TE_PE
6482c264
NC		 6545static void
6546pe_directive_secrel (dummy)
6547 int dummy ATTRIBUTE_UNUSED;
6548{
6549 expressionS exp;
6550
6551 do
6552 {
6553 expression (&exp);
6554 if (exp.X_op == O_symbol)
6555 exp.X_op = O_secrel;
6556
6557 emit_expr (&exp, 4);
6558 }
6559 while (*input_line_pointer++ == ',');
6560
6561 input_line_pointer--;
6562 demand_empty_rest_of_line ();
6563}
6482c264
NC		 6564#endif
6565
252b5132 6566static int
70e41ade 6567i386_immediate (char *imm_start)
252b5132
RH		 6568{
6569 char *save_input_line_pointer;
f3c180ae 6570 char *gotfree_input_line;
252b5132 6571 segT exp_seg = 0;
47926f60 6572 expressionS *exp;
40fb9820
L		 6573 i386_operand_type types;
6574
0dfbf9d7 6575 operand_type_set (&types, ~0);
252b5132
RH		 6576
6577 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6578 {
31b2323c
L		 6579 as_bad (_("at most %d immediate operands are allowed"),
6580 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 6581 return 0;
6582 }
6583
6584 exp = &im_expressions[i.imm_operands++];
520dc8e8 6585 i.op[this_operand].imms = exp;
252b5132
RH		 6586
6587 if (is_space_char (*imm_start))
6588 ++imm_start;
6589
6590 save_input_line_pointer = input_line_pointer;
6591 input_line_pointer = imm_start;
6592
3956db08 6593 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6594 if (gotfree_input_line)
6595 input_line_pointer = gotfree_input_line;
252b5132
RH		 6596
6597 exp_seg = expression (exp);
6598
83183c0c 6599 SKIP_WHITESPACE ();
252b5132 6600 if (*input_line_pointer)
f3c180ae 6601 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 6602
6603 input_line_pointer = save_input_line_pointer;
f3c180ae 6604 if (gotfree_input_line)
ee86248c
JB		 6605 {
6606 free (gotfree_input_line);
6607
6608 if (exp->X_op == O_constant || exp->X_op == O_register)
6609 exp->X_op = O_illegal;
6610 }
6611
6612 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
6613}
252b5132 6614
ee86248c
JB		 6615static int
6616i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6617 i386_operand_type types, const char *imm_start)
6618{
6619 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 6620 {
313c53d1
L		 6621 if (imm_start)
6622 as_bad (_("missing or invalid immediate expression `%s'"),
6623 imm_start);
3992d3b7 6624 return 0;
252b5132 6625 }
3e73aa7c 6626 else if (exp->X_op == O_constant)
252b5132 6627 {
47926f60 6628 /* Size it properly later. */
40fb9820 6629 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 6630 /* If not 64bit, sign extend val. */
6631 if (flag_code != CODE_64BIT
4eed87de
AM		 6632 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6633 exp->X_add_number
6634 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 6635 }
4c63da97 6636#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 6637 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 6638 && exp_seg != absolute_section
47926f60 6639 && exp_seg != text_section
24eab124
AM		 6640 && exp_seg != data_section
6641 && exp_seg != bss_section
6642 && exp_seg != undefined_section
f86103b7 6643 && !bfd_is_com_section (exp_seg))
252b5132 6644 {
d0b47220 6645 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 6646 return 0;
6647 }
6648#endif
bb8f5920
L		 6649 else if (!intel_syntax && exp->X_op == O_register)
6650 {
313c53d1
L		 6651 if (imm_start)
6652 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 6653 return 0;
6654 }
252b5132
RH		 6655 else
6656 {
6657 /* This is an address. The size of the address will be
24eab124 6658 determined later, depending on destination register,
3e73aa7c 6659 suffix, or the default for the section. */
40fb9820
L		 6660 i.types[this_operand].bitfield.imm8 = 1;
6661 i.types[this_operand].bitfield.imm16 = 1;
6662 i.types[this_operand].bitfield.imm32 = 1;
6663 i.types[this_operand].bitfield.imm32s = 1;
6664 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 6665 i.types[this_operand] = operand_type_and (i.types[this_operand],
6666 types);
252b5132
RH		 6667 }
6668
6669 return 1;
6670}
6671
551c1ca1 6672static char *
e3bb37b5 6673i386_scale (char *scale)
252b5132 6674{
551c1ca1
AM		 6675 offsetT val;
6676 char *save = input_line_pointer;
252b5132 6677
551c1ca1
AM		 6678 input_line_pointer = scale;
6679 val = get_absolute_expression ();
6680
6681 switch (val)
252b5132 6682 {
551c1ca1 6683 case 1:
252b5132
RH		 6684 i.log2_scale_factor = 0;
6685 break;
551c1ca1 6686 case 2:
252b5132
RH		 6687 i.log2_scale_factor = 1;
6688 break;
551c1ca1 6689 case 4:
252b5132
RH		 6690 i.log2_scale_factor = 2;
6691 break;
551c1ca1 6692 case 8:
252b5132
RH		 6693 i.log2_scale_factor = 3;
6694 break;
6695 default:
a724f0f4
JB		 6696 {
6697 char sep = *input_line_pointer;
6698
6699 *input_line_pointer = '\0';
6700 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6701 scale);
6702 *input_line_pointer = sep;
6703 input_line_pointer = save;
6704 return NULL;
6705 }
252b5132 6706 }
29b0f896 6707 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 6708 {
6709 as_warn (_("scale factor of %d without an index register"),
24eab124 6710 1 << i.log2_scale_factor);
252b5132 6711 i.log2_scale_factor = 0;
252b5132 6712 }
551c1ca1
AM		 6713 scale = input_line_pointer;
6714 input_line_pointer = save;
6715 return scale;
252b5132
RH		 6716}
6717
252b5132 6718static int
e3bb37b5 6719i386_displacement (char *disp_start, char *disp_end)
252b5132 6720{
29b0f896 6721 expressionS *exp;
252b5132
RH		 6722 segT exp_seg = 0;
6723 char *save_input_line_pointer;
f3c180ae 6724 char *gotfree_input_line;
40fb9820
L		 6725 int override;
6726 i386_operand_type bigdisp, types = anydisp;
3992d3b7 6727 int ret;
252b5132 6728
31b2323c
L		 6729 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6730 {
6731 as_bad (_("at most %d displacement operands are allowed"),
6732 MAX_MEMORY_OPERANDS);
6733 return 0;
6734 }
6735
0dfbf9d7 6736 operand_type_set (&bigdisp, 0);
40fb9820
L		 6737 if ((i.types[this_operand].bitfield.jumpabsolute)
6738 || (!current_templates->start->opcode_modifier.jump
6739 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 6740 {
40fb9820 6741 bigdisp.bitfield.disp32 = 1;
e05278af 6742 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 6743 if (flag_code == CODE_64BIT)
6744 {
6745 if (!override)
6746 {
6747 bigdisp.bitfield.disp32s = 1;
6748 bigdisp.bitfield.disp64 = 1;
6749 }
6750 }
6751 else if ((flag_code == CODE_16BIT) ^ override)
6752 {
6753 bigdisp.bitfield.disp32 = 0;
6754 bigdisp.bitfield.disp16 = 1;
6755 }
e05278af
JB		 6756 }
6757 else
6758 {
6759 /* For PC-relative branches, the width of the displacement
6760 is dependent upon data size, not address size. */
e05278af 6761 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 6762 if (flag_code == CODE_64BIT)
6763 {
6764 if (override || i.suffix == WORD_MNEM_SUFFIX)
6765 bigdisp.bitfield.disp16 = 1;
6766 else
6767 {
6768 bigdisp.bitfield.disp32 = 1;
6769 bigdisp.bitfield.disp32s = 1;
6770 }
6771 }
6772 else
e05278af
JB		 6773 {
6774 if (!override)
6775 override = (i.suffix == (flag_code != CODE_16BIT
6776 ? WORD_MNEM_SUFFIX
6777 : LONG_MNEM_SUFFIX));
40fb9820
L		 6778 bigdisp.bitfield.disp32 = 1;
6779 if ((flag_code == CODE_16BIT) ^ override)
6780 {
6781 bigdisp.bitfield.disp32 = 0;
6782 bigdisp.bitfield.disp16 = 1;
6783 }
e05278af 6784 }
e05278af 6785 }
c6fb90c8
L		 6786 i.types[this_operand] = operand_type_or (i.types[this_operand],
6787 bigdisp);
252b5132
RH		 6788
6789 exp = &disp_expressions[i.disp_operands];
520dc8e8 6790 i.op[this_operand].disps = exp;
252b5132
RH		 6791 i.disp_operands++;
6792 save_input_line_pointer = input_line_pointer;
6793 input_line_pointer = disp_start;
6794 END_STRING_AND_SAVE (disp_end);
6795
6796#ifndef GCC_ASM_O_HACK
6797#define GCC_ASM_O_HACK 0
6798#endif
6799#if GCC_ASM_O_HACK
6800 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 6801 if (i.types[this_operand].bitfield.baseIndex
24eab124 6802 && displacement_string_end[-1] == '+')
252b5132
RH		 6803 {
6804 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 6805 constraint within gcc asm statements.
6806 For instance:
6807
6808 #define _set_tssldt_desc(n,addr,limit,type) \
6809 __asm__ __volatile__ ( \
6810 "movw %w2,%0\n\t" \
6811 "movw %w1,2+%0\n\t" \
6812 "rorl $16,%1\n\t" \
6813 "movb %b1,4+%0\n\t" \
6814 "movb %4,5+%0\n\t" \
6815 "movb $0,6+%0\n\t" \
6816 "movb %h1,7+%0\n\t" \
6817 "rorl $16,%1" \
6818 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6819
6820 This works great except that the output assembler ends
6821 up looking a bit weird if it turns out that there is
6822 no offset. You end up producing code that looks like:
6823
6824 #APP
6825 movw $235,(%eax)
6826 movw %dx,2+(%eax)
6827 rorl $16,%edx
6828 movb %dl,4+(%eax)
6829 movb $137,5+(%eax)
6830 movb $0,6+(%eax)
6831 movb %dh,7+(%eax)
6832 rorl $16,%edx
6833 #NO_APP
6834
47926f60 6835 So here we provide the missing zero. */
24eab124
AM		 6836
6837 *displacement_string_end = '0';
252b5132
RH		 6838 }
6839#endif
3956db08 6840 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6841 if (gotfree_input_line)
6842 input_line_pointer = gotfree_input_line;
252b5132 6843
24eab124 6844 exp_seg = expression (exp);
252b5132 6845
636c26b0
AM		 6846 SKIP_WHITESPACE ();
6847 if (*input_line_pointer)
6848 as_bad (_("junk `%s' after expression"), input_line_pointer);
6849#if GCC_ASM_O_HACK
6850 RESTORE_END_STRING (disp_end + 1);
6851#endif
636c26b0 6852 input_line_pointer = save_input_line_pointer;
636c26b0 6853 if (gotfree_input_line)
ee86248c
JB		 6854 {
6855 free (gotfree_input_line);
6856
6857 if (exp->X_op == O_constant || exp->X_op == O_register)
6858 exp->X_op = O_illegal;
6859 }
6860
6861 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
6862
6863 RESTORE_END_STRING (disp_end);
6864
6865 return ret;
6866}
6867
6868static int
6869i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
6870 i386_operand_type types, const char *disp_start)
6871{
6872 i386_operand_type bigdisp;
6873 int ret = 1;
636c26b0 6874
24eab124
AM		 6875 /* We do this to make sure that the section symbol is in
6876 the symbol table. We will ultimately change the relocation
47926f60 6877 to be relative to the beginning of the section. */
1ae12ab7 6878 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 6879 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6880 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 6881 {
636c26b0 6882 if (exp->X_op != O_symbol)
3992d3b7 6883 goto inv_disp;
636c26b0 6884
e5cb08ac 6885 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 6886 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
6887 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 6888 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 6889 exp->X_op = O_subtract;
6890 exp->X_op_symbol = GOT_symbol;
1ae12ab7 6891 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 6892 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 6893 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6894 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 6895 else
29b0f896 6896 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 6897 }
252b5132 6898
3992d3b7
AM		 6899 else if (exp->X_op == O_absent
6900 || exp->X_op == O_illegal
ee86248c 6901 || exp->X_op == O_big)
2daf4fd8 6902 {
3992d3b7
AM		 6903 inv_disp:
6904 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 6905 disp_start);
3992d3b7 6906 ret = 0;
2daf4fd8
AM		 6907 }
6908
0e1147d9
L		 6909 else if (flag_code == CODE_64BIT
6910 && !i.prefix[ADDR_PREFIX]
6911 && exp->X_op == O_constant)
6912 {
6913 /* Since displacement is signed extended to 64bit, don't allow
6914 disp32 and turn off disp32s if they are out of range. */
6915 i.types[this_operand].bitfield.disp32 = 0;
6916 if (!fits_in_signed_long (exp->X_add_number))
6917 {
6918 i.types[this_operand].bitfield.disp32s = 0;
6919 if (i.types[this_operand].bitfield.baseindex)
6920 {
6921 as_bad (_("0x%lx out range of signed 32bit displacement"),
6922 (long) exp->X_add_number);
6923 ret = 0;
6924 }
6925 }
6926 }
6927
4c63da97 6928#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 6929 else if (exp->X_op != O_constant
6930 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6931 && exp_seg != absolute_section
6932 && exp_seg != text_section
6933 && exp_seg != data_section
6934 && exp_seg != bss_section
6935 && exp_seg != undefined_section
6936 && !bfd_is_com_section (exp_seg))
24eab124 6937 {
d0b47220 6938 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 6939 ret = 0;
24eab124 6940 }
252b5132 6941#endif
3956db08 6942
40fb9820
L		 6943 /* Check if this is a displacement only operand. */
6944 bigdisp = i.types[this_operand];
6945 bigdisp.bitfield.disp8 = 0;
6946 bigdisp.bitfield.disp16 = 0;
6947 bigdisp.bitfield.disp32 = 0;
6948 bigdisp.bitfield.disp32s = 0;
6949 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 6950 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 6951 i.types[this_operand] = operand_type_and (i.types[this_operand],
6952 types);
3956db08 6953
3992d3b7 6954 return ret;
252b5132
RH		 6955}
6956
eecb386c 6957/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 6958 Return 1 on success, 0 on a failure. */
6959
252b5132 6960static int
e3bb37b5 6961i386_index_check (const char *operand_string)
252b5132 6962{
3e73aa7c 6963 int ok;
fc0763e6 6964 const char *kind = "base/index";
24eab124 6965#if INFER_ADDR_PREFIX
eecb386c
AM		 6966 int fudged = 0;
6967
24eab124
AM		 6968 tryprefix:
6969#endif
3e73aa7c 6970 ok = 1;
fc0763e6
JB		 6971 if (current_templates->start->opcode_modifier.isstring
6972 && !current_templates->start->opcode_modifier.immext
6973 && (current_templates->end[-1].opcode_modifier.isstring
6974 || i.mem_operands))
6975 {
6976 /* Memory operands of string insns are special in that they only allow
6977 a single register (rDI, rSI, or rBX) as their memory address. */
6978 unsigned int expected;
6979
6980 kind = "string address";
6981
6982 if (current_templates->start->opcode_modifier.w)
6983 {
6984 i386_operand_type type = current_templates->end[-1].operand_types[0];
6985
6986 if (!type.bitfield.baseindex
6987 || ((!i.mem_operands != !intel_syntax)
6988 && current_templates->end[-1].operand_types[1]
6989 .bitfield.baseindex))
6990 type = current_templates->end[-1].operand_types[1];
6991 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
6992 }
6993 else
6994 expected = 3 /* rBX */;
6995
6996 if (!i.base_reg || i.index_reg
6997 || operand_type_check (i.types[this_operand], disp))
6998 ok = -1;
6999 else if (!(flag_code == CODE_64BIT
7000 ? i.prefix[ADDR_PREFIX]
7001 ? i.base_reg->reg_type.bitfield.reg32
7002 : i.base_reg->reg_type.bitfield.reg64
7003 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
7004 ? i.base_reg->reg_type.bitfield.reg32
7005 : i.base_reg->reg_type.bitfield.reg16))
7006 ok = 0;
7007 else if (i.base_reg->reg_num != expected)
7008 ok = -1;
7009
7010 if (ok < 0)
7011 {
7012 unsigned int j;
7013
7014 for (j = 0; j < i386_regtab_size; ++j)
7015 if ((flag_code == CODE_64BIT
7016 ? i.prefix[ADDR_PREFIX]
7017 ? i386_regtab[j].reg_type.bitfield.reg32
7018 : i386_regtab[j].reg_type.bitfield.reg64
7019 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
7020 ? i386_regtab[j].reg_type.bitfield.reg32
7021 : i386_regtab[j].reg_type.bitfield.reg16)
7022 && i386_regtab[j].reg_num == expected)
7023 break;
9c2799c2 7024 gas_assert (j < i386_regtab_size);
fc0763e6
JB		 7025 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
7026 operand_string,
7027 intel_syntax ? '[' : '(',
7028 register_prefix,
7029 i386_regtab[j].reg_name,
7030 intel_syntax ? ']' : ')');
7031 ok = 1;
7032 }
7033 }
7034 else if (flag_code == CODE_64BIT)
64e74474 7035 {
64e74474 7036 if ((i.base_reg
40fb9820
L		 7037 && ((i.prefix[ADDR_PREFIX] == 0
7038 && !i.base_reg->reg_type.bitfield.reg64)
7039 || (i.prefix[ADDR_PREFIX]
7040 && !i.base_reg->reg_type.bitfield.reg32))
7041 && (i.index_reg
9a04903e
JB		 7042 || i.base_reg->reg_num !=
7043 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 7044 || (i.index_reg
40fb9820
L		 7045 && (!i.index_reg->reg_type.bitfield.baseindex
7046 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 7047 && i.index_reg->reg_num != RegRiz
7048 && !i.index_reg->reg_type.bitfield.reg64
7049 )
40fb9820 7050 || (i.prefix[ADDR_PREFIX]
db51cc60 7051 && i.index_reg->reg_num != RegEiz
40fb9820 7052 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 7053 ok = 0;
3e73aa7c
JH		 7054 }
7055 else
7056 {
7057 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
7058 {
7059 /* 16bit checks. */
7060 if ((i.base_reg
40fb9820
L		 7061 && (!i.base_reg->reg_type.bitfield.reg16
7062 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 7063 || (i.index_reg
40fb9820
L		 7064 && (!i.index_reg->reg_type.bitfield.reg16
7065 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 7066 || !(i.base_reg
7067 && i.base_reg->reg_num < 6
7068 && i.index_reg->reg_num >= 6
7069 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 7070 ok = 0;
7071 }
7072 else
e5cb08ac 7073 {
3e73aa7c
JH		 7074 /* 32bit checks. */
7075 if ((i.base_reg
40fb9820 7076 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 7077 || (i.index_reg
db51cc60
L		 7078 && ((!i.index_reg->reg_type.bitfield.reg32
7079 && i.index_reg->reg_num != RegEiz)
40fb9820 7080 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 7081 ok = 0;
3e73aa7c
JH		 7082 }
7083 }
7084 if (!ok)
24eab124
AM		 7085 {
7086#if INFER_ADDR_PREFIX
fc0763e6 7087 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
24eab124
AM		 7088 {
7089 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
7090 i.prefixes += 1;
b23bac36
AM		 7091 /* Change the size of any displacement too. At most one of
7092 Disp16 or Disp32 is set.
7093 FIXME. There doesn't seem to be any real need for separate
7094 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 7095 Removing them would probably clean up the code quite a lot. */
4eed87de 7096 if (flag_code != CODE_64BIT
40fb9820
L		 7097 && (i.types[this_operand].bitfield.disp16
7098 || i.types[this_operand].bitfield.disp32))
7099 i.types[this_operand]
c6fb90c8 7100 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 7101 fudged = 1;
24eab124
AM		 7102 goto tryprefix;
7103 }
eecb386c 7104 if (fudged)
fc0763e6
JB		 7105 as_bad (_("`%s' is not a valid %s expression"),
7106 operand_string,
7107 kind);
eecb386c 7108 else
c388dee8 7109#endif
fc0763e6 7110 as_bad (_("`%s' is not a valid %s-bit %s expression"),
eecb386c 7111 operand_string,
fc0763e6
JB		 7112 flag_code_names[i.prefix[ADDR_PREFIX]
7113 ? flag_code == CODE_32BIT
7114 ? CODE_16BIT
7115 : CODE_32BIT
7116 : flag_code],
7117 kind);
24eab124 7118 }
20f0a1fc 7119 return ok;
24eab124 7120}
252b5132 7121
fc0763e6 7122/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 7123 on error. */
252b5132 7124
252b5132 7125static int
a7619375 7126i386_att_operand (char *operand_string)
252b5132 7127{
af6bdddf
AM		 7128 const reg_entry *r;
7129 char *end_op;
24eab124 7130 char *op_string = operand_string;
252b5132 7131
24eab124 7132 if (is_space_char (*op_string))
252b5132
RH		 7133 ++op_string;
7134
24eab124 7135 /* We check for an absolute prefix (differentiating,
47926f60 7136 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 7137 if (*op_string == ABSOLUTE_PREFIX)
7138 {
7139 ++op_string;
7140 if (is_space_char (*op_string))
7141 ++op_string;
40fb9820 7142 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 7143 }
252b5132 7144
47926f60 7145 /* Check if operand is a register. */
4d1bb795 7146 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 7147 {
40fb9820
L		 7148 i386_operand_type temp;
7149
24eab124
AM		 7150 /* Check for a segment override by searching for ':' after a
7151 segment register. */
7152 op_string = end_op;
7153 if (is_space_char (*op_string))
7154 ++op_string;
40fb9820
L		 7155 if (*op_string == ':'
7156 && (r->reg_type.bitfield.sreg2
7157 || r->reg_type.bitfield.sreg3))
24eab124
AM		 7158 {
7159 switch (r->reg_num)
7160 {
7161 case 0:
7162 i.seg[i.mem_operands] = &es;
7163 break;
7164 case 1:
7165 i.seg[i.mem_operands] = &cs;
7166 break;
7167 case 2:
7168 i.seg[i.mem_operands] = &ss;
7169 break;
7170 case 3:
7171 i.seg[i.mem_operands] = &ds;
7172 break;
7173 case 4:
7174 i.seg[i.mem_operands] = &fs;
7175 break;
7176 case 5:
7177 i.seg[i.mem_operands] = &gs;
7178 break;
7179 }
252b5132 7180
24eab124 7181 /* Skip the ':' and whitespace. */
252b5132
RH		 7182 ++op_string;
7183 if (is_space_char (*op_string))
24eab124 7184 ++op_string;
252b5132 7185
24eab124
AM		 7186 if (!is_digit_char (*op_string)
7187 && !is_identifier_char (*op_string)
7188 && *op_string != '('
7189 && *op_string != ABSOLUTE_PREFIX)
7190 {
7191 as_bad (_("bad memory operand `%s'"), op_string);
7192 return 0;
7193 }
47926f60 7194 /* Handle case of %es:*foo. */
24eab124
AM		 7195 if (*op_string == ABSOLUTE_PREFIX)
7196 {
7197 ++op_string;
7198 if (is_space_char (*op_string))
7199 ++op_string;
40fb9820 7200 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 7201 }
7202 goto do_memory_reference;
7203 }
7204 if (*op_string)
7205 {
d0b47220 7206 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 7207 return 0;
7208 }
40fb9820
L		 7209 temp = r->reg_type;
7210 temp.bitfield.baseindex = 0;
c6fb90c8
L		 7211 i.types[this_operand] = operand_type_or (i.types[this_operand],
7212 temp);
7d5e4556 7213 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 7214 i.op[this_operand].regs = r;
24eab124
AM		 7215 i.reg_operands++;
7216 }
af6bdddf
AM		 7217 else if (*op_string == REGISTER_PREFIX)
7218 {
7219 as_bad (_("bad register name `%s'"), op_string);
7220 return 0;
7221 }
24eab124 7222 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 7223 {
24eab124 7224 ++op_string;
40fb9820 7225 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 7226 {
d0b47220 7227 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 7228 return 0;
7229 }
7230 if (!i386_immediate (op_string))
7231 return 0;
7232 }
7233 else if (is_digit_char (*op_string)
7234 || is_identifier_char (*op_string)
e5cb08ac 7235 || *op_string == '(')
24eab124 7236 {
47926f60 7237 /* This is a memory reference of some sort. */
af6bdddf 7238 char *base_string;
252b5132 7239
47926f60 7240 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 7241 char *displacement_string_start;
7242 char *displacement_string_end;
252b5132 7243
24eab124 7244 do_memory_reference:
24eab124 7245 if ((i.mem_operands == 1
40fb9820 7246 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 7247 || i.mem_operands == 2)
7248 {
7249 as_bad (_("too many memory references for `%s'"),
7250 current_templates->start->name);
7251 return 0;
7252 }
252b5132 7253
24eab124
AM		 7254 /* Check for base index form. We detect the base index form by
7255 looking for an ')' at the end of the operand, searching
7256 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7257 after the '('. */
af6bdddf 7258 base_string = op_string + strlen (op_string);
c3332e24 7259
af6bdddf
AM		 7260 --base_string;
7261 if (is_space_char (*base_string))
7262 --base_string;
252b5132 7263
47926f60 7264 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 7265 displacement_string_start = op_string;
7266 displacement_string_end = base_string + 1;
252b5132 7267
24eab124
AM		 7268 if (*base_string == ')')
7269 {
af6bdddf 7270 char *temp_string;
24eab124
AM		 7271 unsigned int parens_balanced = 1;
7272 /* We've already checked that the number of left & right ()'s are
47926f60 7273 equal, so this loop will not be infinite. */
24eab124
AM		 7274 do
7275 {
7276 base_string--;
7277 if (*base_string == ')')
7278 parens_balanced++;
7279 if (*base_string == '(')
7280 parens_balanced--;
7281 }
7282 while (parens_balanced);
c3332e24 7283
af6bdddf 7284 temp_string = base_string;
c3332e24 7285
24eab124 7286 /* Skip past '(' and whitespace. */
252b5132
RH		 7287 ++base_string;
7288 if (is_space_char (*base_string))
24eab124 7289 ++base_string;
252b5132 7290
af6bdddf 7291 if (*base_string == ','
4eed87de
AM		 7292 || ((i.base_reg = parse_register (base_string, &end_op))
7293 != NULL))
252b5132 7294 {
af6bdddf 7295 displacement_string_end = temp_string;
252b5132 7296
40fb9820 7297 i.types[this_operand].bitfield.baseindex = 1;
252b5132 7298
af6bdddf 7299 if (i.base_reg)
24eab124 7300 {
24eab124
AM		 7301 base_string = end_op;
7302 if (is_space_char (*base_string))
7303 ++base_string;
af6bdddf
AM		 7304 }
7305
7306 /* There may be an index reg or scale factor here. */
7307 if (*base_string == ',')
7308 {
7309 ++base_string;
7310 if (is_space_char (*base_string))
7311 ++base_string;
7312
4eed87de
AM		 7313 if ((i.index_reg = parse_register (base_string, &end_op))
7314 != NULL)
24eab124 7315 {
af6bdddf 7316 base_string = end_op;
24eab124
AM		 7317 if (is_space_char (*base_string))
7318 ++base_string;
af6bdddf
AM		 7319 if (*base_string == ',')
7320 {
7321 ++base_string;
7322 if (is_space_char (*base_string))
7323 ++base_string;
7324 }
e5cb08ac 7325 else if (*base_string != ')')
af6bdddf 7326 {
4eed87de
AM		 7327 as_bad (_("expecting `,' or `)' "
7328 "after index register in `%s'"),
af6bdddf
AM		 7329 operand_string);
7330 return 0;
7331 }
24eab124 7332 }
af6bdddf 7333 else if (*base_string == REGISTER_PREFIX)
24eab124 7334 {
af6bdddf 7335 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 7336 return 0;
7337 }
252b5132 7338
47926f60 7339 /* Check for scale factor. */
551c1ca1 7340 if (*base_string != ')')
af6bdddf 7341 {
551c1ca1
AM		 7342 char *end_scale = i386_scale (base_string);
7343
7344 if (!end_scale)
af6bdddf 7345 return 0;
24eab124 7346
551c1ca1 7347 base_string = end_scale;
af6bdddf
AM		 7348 if (is_space_char (*base_string))
7349 ++base_string;
7350 if (*base_string != ')')
7351 {
4eed87de
AM		 7352 as_bad (_("expecting `)' "
7353 "after scale factor in `%s'"),
af6bdddf
AM		 7354 operand_string);
7355 return 0;
7356 }
7357 }
7358 else if (!i.index_reg)
24eab124 7359 {
4eed87de
AM		 7360 as_bad (_("expecting index register or scale factor "
7361 "after `,'; got '%c'"),
af6bdddf 7362 *base_string);
24eab124
AM		 7363 return 0;
7364 }
7365 }
af6bdddf 7366 else if (*base_string != ')')
24eab124 7367 {
4eed87de
AM		 7368 as_bad (_("expecting `,' or `)' "
7369 "after base register in `%s'"),
af6bdddf 7370 operand_string);
24eab124
AM		 7371 return 0;
7372 }
c3332e24 7373 }
af6bdddf 7374 else if (*base_string == REGISTER_PREFIX)
c3332e24 7375 {
af6bdddf 7376 as_bad (_("bad register name `%s'"), base_string);
24eab124 7377 return 0;
c3332e24 7378 }
24eab124
AM		 7379 }
7380
7381 /* If there's an expression beginning the operand, parse it,
7382 assuming displacement_string_start and
7383 displacement_string_end are meaningful. */
7384 if (displacement_string_start != displacement_string_end)
7385 {
7386 if (!i386_displacement (displacement_string_start,
7387 displacement_string_end))
7388 return 0;
7389 }
7390
7391 /* Special case for (%dx) while doing input/output op. */
7392 if (i.base_reg
0dfbf9d7
L		 7393 && operand_type_equal (&i.base_reg->reg_type,
7394 &reg16_inoutportreg)
24eab124
AM		 7395 && i.index_reg == 0
7396 && i.log2_scale_factor == 0
7397 && i.seg[i.mem_operands] == 0
40fb9820 7398 && !operand_type_check (i.types[this_operand], disp))
24eab124 7399 {
65da13b5 7400 i.types[this_operand] = inoutportreg;
24eab124
AM		 7401 return 1;
7402 }
7403
eecb386c
AM		 7404 if (i386_index_check (operand_string) == 0)
7405 return 0;
5c07affc 7406 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 7407 i.mem_operands++;
7408 }
7409 else
ce8a8b2f
AM		 7410 {
7411 /* It's not a memory operand; argh! */
24eab124
AM		 7412 as_bad (_("invalid char %s beginning operand %d `%s'"),
7413 output_invalid (*op_string),
7414 this_operand + 1,
7415 op_string);
7416 return 0;
7417 }
47926f60 7418 return 1; /* Normal return. */
252b5132
RH		 7419}
7420\f
ee7fcc42
AM		 7421/* md_estimate_size_before_relax()
7422
7423 Called just before relax() for rs_machine_dependent frags. The x86
7424 assembler uses these frags to handle variable size jump
7425 instructions.
7426
7427 Any symbol that is now undefined will not become defined.
7428 Return the correct fr_subtype in the frag.
7429 Return the initial "guess for variable size of frag" to caller.
7430 The guess is actually the growth beyond the fixed part. Whatever
7431 we do to grow the fixed or variable part contributes to our
7432 returned value. */
7433
252b5132
RH		 7434int
7435md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 7436 fragS *fragP;
7437 segT segment;
252b5132 7438{
252b5132 7439 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 7440 check for un-relaxable symbols. On an ELF system, we can't relax
7441 an externally visible symbol, because it may be overridden by a
7442 shared library. */
7443 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 7444#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7445 || (IS_ELF
31312f95 7446 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 7447 || S_IS_WEAK (fragP->fr_symbol)
7448 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
7449 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 7450#endif
7451#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 7452 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 7453 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 7454#endif
7455 )
252b5132 7456 {
b98ef147
AM		 7457 /* Symbol is undefined in this segment, or we need to keep a
7458 reloc so that weak symbols can be overridden. */
7459 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 7460 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 7461 unsigned char *opcode;
7462 int old_fr_fix;
f6af82bd 7463
ee7fcc42 7464 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 7465 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 7466 else if (size == 2)
f6af82bd
AM		 7467 reloc_type = BFD_RELOC_16_PCREL;
7468 else
7469 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7470
ee7fcc42
AM		 7471 old_fr_fix = fragP->fr_fix;
7472 opcode = (unsigned char *) fragP->fr_opcode;
7473
fddf5b5b 7474 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7475 {
fddf5b5b
AM		 7476 case UNCOND_JUMP:
7477 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7478 opcode[0] = 0xe9;
252b5132 7479 fragP->fr_fix += size;
062cd5e7
AS		 7480 fix_new (fragP, old_fr_fix, size,
7481 fragP->fr_symbol,
7482 fragP->fr_offset, 1,
7483 reloc_type);
252b5132
RH		 7484 break;
7485
fddf5b5b 7486 case COND_JUMP86:
412167cb
AM		 7487 if (size == 2
7488 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 7489 {
7490 /* Negate the condition, and branch past an
7491 unconditional jump. */
7492 opcode[0] ^= 1;
7493 opcode[1] = 3;
7494 /* Insert an unconditional jump. */
7495 opcode[2] = 0xe9;
7496 /* We added two extra opcode bytes, and have a two byte
7497 offset. */
7498 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7499 fix_new (fragP, old_fr_fix + 2, 2,
7500 fragP->fr_symbol,
7501 fragP->fr_offset, 1,
7502 reloc_type);
fddf5b5b
AM		 7503 break;
7504 }
7505 /* Fall through. */
7506
7507 case COND_JUMP:
412167cb
AM		 7508 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7509 {
3e02c1cc
AM		 7510 fixS *fixP;
7511
412167cb 7512 fragP->fr_fix += 1;
3e02c1cc
AM		 7513 fixP = fix_new (fragP, old_fr_fix, 1,
7514 fragP->fr_symbol,
7515 fragP->fr_offset, 1,
7516 BFD_RELOC_8_PCREL);
7517 fixP->fx_signed = 1;
412167cb
AM		 7518 break;
7519 }
93c2a809 7520
24eab124 7521 /* This changes the byte-displacement jump 0x7N
fddf5b5b 7522 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 7523 opcode[1] = opcode[0] + 0x10;
f6af82bd 7524 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 7525 /* We've added an opcode byte. */
7526 fragP->fr_fix += 1 + size;
062cd5e7
AS		 7527 fix_new (fragP, old_fr_fix + 1, size,
7528 fragP->fr_symbol,
7529 fragP->fr_offset, 1,
7530 reloc_type);
252b5132 7531 break;
fddf5b5b
AM		 7532
7533 default:
7534 BAD_CASE (fragP->fr_subtype);
7535 break;
252b5132
RH		 7536 }
7537 frag_wane (fragP);
ee7fcc42 7538 return fragP->fr_fix - old_fr_fix;
252b5132 7539 }
93c2a809 7540
93c2a809
AM		 7541 /* Guess size depending on current relax state. Initially the relax
7542 state will correspond to a short jump and we return 1, because
7543 the variable part of the frag (the branch offset) is one byte
7544 long. However, we can relax a section more than once and in that
7545 case we must either set fr_subtype back to the unrelaxed state,
7546 or return the value for the appropriate branch. */
7547 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 7548}
7549
47926f60
KH		 7550/* Called after relax() is finished.
7551
7552 In: Address of frag.
7553 fr_type == rs_machine_dependent.
7554 fr_subtype is what the address relaxed to.
7555
7556 Out: Any fixSs and constants are set up.
7557 Caller will turn frag into a ".space 0". */
7558
252b5132
RH		 7559void
7560md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 7561 bfd *abfd ATTRIBUTE_UNUSED;
7562 segT sec ATTRIBUTE_UNUSED;
29b0f896 7563 fragS *fragP;
252b5132 7564{
29b0f896 7565 unsigned char *opcode;
252b5132 7566 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 7567 offsetT target_address;
7568 offsetT opcode_address;
252b5132 7569 unsigned int extension = 0;
847f7ad4 7570 offsetT displacement_from_opcode_start;
252b5132
RH		 7571
7572 opcode = (unsigned char *) fragP->fr_opcode;
7573
47926f60 7574 /* Address we want to reach in file space. */
252b5132 7575 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 7576
47926f60 7577 /* Address opcode resides at in file space. */
252b5132
RH		 7578 opcode_address = fragP->fr_address + fragP->fr_fix;
7579
47926f60 7580 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 7581 displacement_from_opcode_start = target_address - opcode_address;
7582
fddf5b5b 7583 if ((fragP->fr_subtype & BIG) == 0)
252b5132 7584 {
47926f60
KH		 7585 /* Don't have to change opcode. */
7586 extension = 1; /* 1 opcode + 1 displacement */
252b5132 7587 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 7588 }
7589 else
7590 {
7591 if (no_cond_jump_promotion
7592 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 7593 as_warn_where (fragP->fr_file, fragP->fr_line,
7594 _("long jump required"));
252b5132 7595
fddf5b5b
AM		 7596 switch (fragP->fr_subtype)
7597 {
7598 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7599 extension = 4; /* 1 opcode + 4 displacement */
7600 opcode[0] = 0xe9;
7601 where_to_put_displacement = &opcode[1];
7602 break;
252b5132 7603
fddf5b5b
AM		 7604 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7605 extension = 2; /* 1 opcode + 2 displacement */
7606 opcode[0] = 0xe9;
7607 where_to_put_displacement = &opcode[1];
7608 break;
252b5132 7609
fddf5b5b
AM		 7610 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7611 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7612 extension = 5; /* 2 opcode + 4 displacement */
7613 opcode[1] = opcode[0] + 0x10;
7614 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7615 where_to_put_displacement = &opcode[2];
7616 break;
252b5132 7617
fddf5b5b
AM		 7618 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7619 extension = 3; /* 2 opcode + 2 displacement */
7620 opcode[1] = opcode[0] + 0x10;
7621 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7622 where_to_put_displacement = &opcode[2];
7623 break;
252b5132 7624
fddf5b5b
AM		 7625 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7626 extension = 4;
7627 opcode[0] ^= 1;
7628 opcode[1] = 3;
7629 opcode[2] = 0xe9;
7630 where_to_put_displacement = &opcode[3];
7631 break;
7632
7633 default:
7634 BAD_CASE (fragP->fr_subtype);
7635 break;
7636 }
252b5132 7637 }
fddf5b5b 7638
7b81dfbb
AJ		 7639 /* If size if less then four we are sure that the operand fits,
7640 but if it's 4, then it could be that the displacement is larger
7641 then -/+ 2GB. */
7642 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7643 && object_64bit
7644 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 7645 + ((addressT) 1 << 31))
7646 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 7647 {
7648 as_bad_where (fragP->fr_file, fragP->fr_line,
7649 _("jump target out of range"));
7650 /* Make us emit 0. */
7651 displacement_from_opcode_start = extension;
7652 }
47926f60 7653 /* Now put displacement after opcode. */
252b5132
RH		 7654 md_number_to_chars ((char *) where_to_put_displacement,
7655 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 7656 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 7657 fragP->fr_fix += extension;
7658}
7659\f
252b5132
RH		 7660/* Apply a fixup (fixS) to segment data, once it has been determined
7661 by our caller that we have all the info we need to fix it up.
7662
7663 On the 386, immediates, displacements, and data pointers are all in
7664 the same (little-endian) format, so we don't need to care about which
7665 we are handling. */
7666
94f592af 7667void
55cf6793 7668md_apply_fix (fixP, valP, seg)
47926f60
KH		 7669 /* The fix we're to put in. */
7670 fixS *fixP;
47926f60 7671 /* Pointer to the value of the bits. */
c6682705 7672 valueT *valP;
47926f60
KH		 7673 /* Segment fix is from. */
7674 segT seg ATTRIBUTE_UNUSED;
252b5132 7675{
94f592af 7676 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 7677 valueT value = *valP;
252b5132 7678
f86103b7 7679#if !defined (TE_Mach)
93382f6d
AM		 7680 if (fixP->fx_pcrel)
7681 {
7682 switch (fixP->fx_r_type)
7683 {
5865bb77
ILT		 7684 default:
7685 break;
7686
d6ab8113
JB		 7687 case BFD_RELOC_64:
7688 fixP->fx_r_type = BFD_RELOC_64_PCREL;
7689 break;
93382f6d 7690 case BFD_RELOC_32:
ae8887b5 7691 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 7692 fixP->fx_r_type = BFD_RELOC_32_PCREL;
7693 break;
7694 case BFD_RELOC_16:
7695 fixP->fx_r_type = BFD_RELOC_16_PCREL;
7696 break;
7697 case BFD_RELOC_8:
7698 fixP->fx_r_type = BFD_RELOC_8_PCREL;
7699 break;
7700 }
7701 }
252b5132 7702
a161fe53 7703 if (fixP->fx_addsy != NULL
31312f95 7704 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 7705 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 7706 || fixP->fx_r_type == BFD_RELOC_16_PCREL
7707 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7708 && !use_rela_relocations)
252b5132 7709 {
31312f95
AM		 7710 /* This is a hack. There should be a better way to handle this.
7711 This covers for the fact that bfd_install_relocation will
7712 subtract the current location (for partial_inplace, PC relative
7713 relocations); see more below. */
252b5132 7714#ifndef OBJ_AOUT
718ddfc0 7715 if (IS_ELF
252b5132
RH		 7716#ifdef TE_PE
7717 || OUTPUT_FLAVOR == bfd_target_coff_flavour
7718#endif
7719 )
7720 value += fixP->fx_where + fixP->fx_frag->fr_address;
7721#endif
7722#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7723 if (IS_ELF)
252b5132 7724 {
6539b54b 7725 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 7726
6539b54b 7727 if ((sym_seg == seg
2f66722d 7728 || (symbol_section_p (fixP->fx_addsy)
6539b54b 7729 && sym_seg != absolute_section))
af65af87 7730 && !generic_force_reloc (fixP))
2f66722d
AM		 7731 {
7732 /* Yes, we add the values in twice. This is because
6539b54b
AM		 7733 bfd_install_relocation subtracts them out again. I think
7734 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 7735 it. FIXME. */
7736 value += fixP->fx_where + fixP->fx_frag->fr_address;
7737 }
252b5132
RH		 7738 }
7739#endif
7740#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 7741 /* For some reason, the PE format does not store a
7742 section address offset for a PC relative symbol. */
7743 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 7744 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 7745 value += md_pcrel_from (fixP);
7746#endif
7747 }
fbeb56a4
DK		 7748#if defined (OBJ_COFF) && defined (TE_PE)
7749 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7750 {
7751 value -= S_GET_VALUE (fixP->fx_addsy);
7752 }
7753#endif
252b5132
RH		 7754
7755 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 7756 and we must not disappoint it. */
252b5132 7757#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7758 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 7759 switch (fixP->fx_r_type)
7760 {
7761 case BFD_RELOC_386_PLT32:
3e73aa7c 7762 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 7763 /* Make the jump instruction point to the address of the operand. At
7764 runtime we merely add the offset to the actual PLT entry. */
7765 value = -4;
7766 break;
31312f95 7767
13ae64f3
JJ		 7768 case BFD_RELOC_386_TLS_GD:
7769 case BFD_RELOC_386_TLS_LDM:
13ae64f3 7770 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7771 case BFD_RELOC_386_TLS_IE:
7772 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 7773 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 7774 case BFD_RELOC_X86_64_TLSGD:
7775 case BFD_RELOC_X86_64_TLSLD:
7776 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 7777 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 7778 value = 0; /* Fully resolved at runtime. No addend. */
7779 /* Fallthrough */
7780 case BFD_RELOC_386_TLS_LE:
7781 case BFD_RELOC_386_TLS_LDO_32:
7782 case BFD_RELOC_386_TLS_LE_32:
7783 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7784 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 7785 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 7786 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 7787 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7788 break;
7789
67a4f2b7
AO		 7790 case BFD_RELOC_386_TLS_DESC_CALL:
7791 case BFD_RELOC_X86_64_TLSDESC_CALL:
7792 value = 0; /* Fully resolved at runtime. No addend. */
7793 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7794 fixP->fx_done = 0;
7795 return;
7796
00f7efb6
JJ		 7797 case BFD_RELOC_386_GOT32:
7798 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 7799 value = 0; /* Fully resolved at runtime. No addend. */
7800 break;
47926f60
KH		 7801
7802 case BFD_RELOC_VTABLE_INHERIT:
7803 case BFD_RELOC_VTABLE_ENTRY:
7804 fixP->fx_done = 0;
94f592af 7805 return;
47926f60
KH		 7806
7807 default:
7808 break;
7809 }
7810#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 7811 *valP = value;
f86103b7 7812#endif /* !defined (TE_Mach) */
3e73aa7c 7813
3e73aa7c 7814 /* Are we finished with this relocation now? */
c6682705 7815 if (fixP->fx_addsy == NULL)
3e73aa7c 7816 fixP->fx_done = 1;
fbeb56a4
DK		 7817#if defined (OBJ_COFF) && defined (TE_PE)
7818 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
7819 {
7820 fixP->fx_done = 0;
7821 /* Remember value for tc_gen_reloc. */
7822 fixP->fx_addnumber = value;
7823 /* Clear out the frag for now. */
7824 value = 0;
7825 }
7826#endif
3e73aa7c
JH		 7827 else if (use_rela_relocations)
7828 {
7829 fixP->fx_no_overflow = 1;
062cd5e7
AS		 7830 /* Remember value for tc_gen_reloc. */
7831 fixP->fx_addnumber = value;
3e73aa7c
JH		 7832 value = 0;
7833 }
f86103b7 7834
94f592af 7835 md_number_to_chars (p, value, fixP->fx_size);
252b5132 7836}
252b5132 7837\f
252b5132 7838char *
499ac353 7839md_atof (int type, char *litP, int *sizeP)
252b5132 7840{
499ac353
NC		 7841 /* This outputs the LITTLENUMs in REVERSE order;
7842 in accord with the bigendian 386. */
7843 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 7844}
7845\f
2d545b82 7846static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 7847
252b5132 7848static char *
e3bb37b5 7849output_invalid (int c)
252b5132 7850{
3882b010 7851 if (ISPRINT (c))
f9f21a03
L		 7852 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7853 "'%c'", c);
252b5132 7854 else
f9f21a03 7855 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 7856 "(0x%x)", (unsigned char) c);
252b5132
RH		 7857 return output_invalid_buf;
7858}
7859
af6bdddf 7860/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 7861
7862static const reg_entry *
4d1bb795 7863parse_real_register (char *reg_string, char **end_op)
252b5132 7864{
af6bdddf
AM		 7865 char *s = reg_string;
7866 char *p;
252b5132
RH		 7867 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7868 const reg_entry *r;
7869
7870 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7871 if (*s == REGISTER_PREFIX)
7872 ++s;
7873
7874 if (is_space_char (*s))
7875 ++s;
7876
7877 p = reg_name_given;
af6bdddf 7878 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 7879 {
7880 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 7881 return (const reg_entry *) NULL;
7882 s++;
252b5132
RH		 7883 }
7884
6588847e
DN		 7885 /* For naked regs, make sure that we are not dealing with an identifier.
7886 This prevents confusing an identifier like `eax_var' with register
7887 `eax'. */
7888 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7889 return (const reg_entry *) NULL;
7890
af6bdddf 7891 *end_op = s;
252b5132
RH		 7892
7893 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7894
5f47d35b 7895 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 7896 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 7897 {
5f47d35b
AM		 7898 if (is_space_char (*s))
7899 ++s;
7900 if (*s == '(')
7901 {
af6bdddf 7902 ++s;
5f47d35b
AM		 7903 if (is_space_char (*s))
7904 ++s;
7905 if (*s >= '0' && *s <= '7')
7906 {
db557034 7907 int fpr = *s - '0';
af6bdddf 7908 ++s;
5f47d35b
AM		 7909 if (is_space_char (*s))
7910 ++s;
7911 if (*s == ')')
7912 {
7913 *end_op = s + 1;
1e9cc1c2 7914 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 7915 know (r);
7916 return r + fpr;
5f47d35b 7917 }
5f47d35b 7918 }
47926f60 7919 /* We have "%st(" then garbage. */
5f47d35b
AM		 7920 return (const reg_entry *) NULL;
7921 }
7922 }
7923
a60de03c
JB		 7924 if (r == NULL || allow_pseudo_reg)
7925 return r;
7926
0dfbf9d7 7927 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 7928 return (const reg_entry *) NULL;
7929
192dc9c6
JB		 7930 if ((r->reg_type.bitfield.reg32
7931 || r->reg_type.bitfield.sreg3
7932 || r->reg_type.bitfield.control
7933 || r->reg_type.bitfield.debug
7934 || r->reg_type.bitfield.test)
7935 && !cpu_arch_flags.bitfield.cpui386)
7936 return (const reg_entry *) NULL;
7937
309d3373
JB		 7938 if (r->reg_type.bitfield.floatreg
7939 && !cpu_arch_flags.bitfield.cpu8087
7940 && !cpu_arch_flags.bitfield.cpu287
7941 && !cpu_arch_flags.bitfield.cpu387)
7942 return (const reg_entry *) NULL;
7943
192dc9c6
JB		 7944 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
7945 return (const reg_entry *) NULL;
7946
7947 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
7948 return (const reg_entry *) NULL;
7949
40f12533
L		 7950 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
7951 return (const reg_entry *) NULL;
7952
db51cc60 7953 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 7954 if (!allow_index_reg
db51cc60
L		 7955 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7956 return (const reg_entry *) NULL;
7957
a60de03c
JB		 7958 if (((r->reg_flags & (RegRex64 | RegRex))
7959 || r->reg_type.bitfield.reg64)
40fb9820 7960 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 7961 || !operand_type_equal (&r->reg_type, &control))
1ae00879 7962 && flag_code != CODE_64BIT)
20f0a1fc 7963 return (const reg_entry *) NULL;
1ae00879 7964
b7240065
JB		 7965 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7966 return (const reg_entry *) NULL;
7967
252b5132
RH		 7968 return r;
7969}
4d1bb795
JB		 7970
7971/* REG_STRING starts *before* REGISTER_PREFIX. */
7972
7973static const reg_entry *
7974parse_register (char *reg_string, char **end_op)
7975{
7976 const reg_entry *r;
7977
7978 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7979 r = parse_real_register (reg_string, end_op);
7980 else
7981 r = NULL;
7982 if (!r)
7983 {
7984 char *save = input_line_pointer;
7985 char c;
7986 symbolS *symbolP;
7987
7988 input_line_pointer = reg_string;
7989 c = get_symbol_end ();
7990 symbolP = symbol_find (reg_string);
7991 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7992 {
7993 const expressionS *e = symbol_get_value_expression (symbolP);
7994
0398aac5 7995 know (e->X_op == O_register);
4eed87de 7996 know (e->X_add_number >= 0
c3fe08fa 7997 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 7998 r = i386_regtab + e->X_add_number;
7999 *end_op = input_line_pointer;
8000 }
8001 *input_line_pointer = c;
8002 input_line_pointer = save;
8003 }
8004 return r;
8005}
8006
8007int
8008i386_parse_name (char *name, expressionS *e, char *nextcharP)
8009{
8010 const reg_entry *r;
8011 char *end = input_line_pointer;
8012
8013 *end = *nextcharP;
8014 r = parse_register (name, &input_line_pointer);
8015 if (r && end <= input_line_pointer)
8016 {
8017 *nextcharP = *input_line_pointer;
8018 *input_line_pointer = 0;
8019 e->X_op = O_register;
8020 e->X_add_number = r - i386_regtab;
8021 return 1;
8022 }
8023 input_line_pointer = end;
8024 *end = 0;
ee86248c 8025 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 8026}
8027
8028void
8029md_operand (expressionS *e)
8030{
ee86248c
JB		 8031 char *end;
8032 const reg_entry *r;
4d1bb795 8033
ee86248c
JB		 8034 switch (*input_line_pointer)
8035 {
8036 case REGISTER_PREFIX:
8037 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 8038 if (r)
8039 {
8040 e->X_op = O_register;
8041 e->X_add_number = r - i386_regtab;
8042 input_line_pointer = end;
8043 }
ee86248c
JB		 8044 break;
8045
8046 case '[':
9c2799c2 8047 gas_assert (intel_syntax);
ee86248c
JB		 8048 end = input_line_pointer++;
8049 expression (e);
8050 if (*input_line_pointer == ']')
8051 {
8052 ++input_line_pointer;
8053 e->X_op_symbol = make_expr_symbol (e);
8054 e->X_add_symbol = NULL;
8055 e->X_add_number = 0;
8056 e->X_op = O_index;
8057 }
8058 else
8059 {
8060 e->X_op = O_absent;
8061 input_line_pointer = end;
8062 }
8063 break;
4d1bb795
JB		 8064 }
8065}
8066
252b5132 8067\f
4cc782b5 8068#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 8069const char *md_shortopts = "kVQ:sqn";
252b5132 8070#else
12b55ccc 8071const char *md_shortopts = "qn";
252b5132 8072#endif
6e0b89ee 8073
3e73aa7c 8074#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 8075#define OPTION_64 (OPTION_MD_BASE + 1)
8076#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 8077#define OPTION_MARCH (OPTION_MD_BASE + 3)
8078#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 8079#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
8080#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
8081#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
8082#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
8083#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 8084#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 8085#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
40a9833c 8086#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 12)
b3b91714 8087
99ad8390
NC		 8088struct option md_longopts[] =
8089{
3e73aa7c 8090 {"32", no_argument, NULL, OPTION_32},
321098a5
L		 8091#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8092 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c 8093 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 8094#endif
b3b91714 8095 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 8096 {"march", required_argument, NULL, OPTION_MARCH},
8097 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 8098 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
8099 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
8100 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
8101 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
8102 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 8103 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 8104 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
539f890d 8105 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
252b5132
RH		 8106 {NULL, no_argument, NULL, 0}
8107};
8108size_t md_longopts_size = sizeof (md_longopts);
8109
8110int
9103f4f4 8111md_parse_option (int c, char *arg)
252b5132 8112{
91d6fa6a 8113 unsigned int j;
6305a203 8114 char *arch, *next;
9103f4f4 8115
252b5132
RH		 8116 switch (c)
8117 {
12b55ccc
L		 8118 case 'n':
8119 optimize_align_code = 0;
8120 break;
8121
a38cf1db
AM		 8122 case 'q':
8123 quiet_warnings = 1;
252b5132
RH		 8124 break;
8125
8126#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 8127 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8128 should be emitted or not. FIXME: Not implemented. */
8129 case 'Q':
252b5132
RH		 8130 break;
8131
8132 /* -V: SVR4 argument to print version ID. */
8133 case 'V':
8134 print_version_id ();
8135 break;
8136
a38cf1db
AM		 8137 /* -k: Ignore for FreeBSD compatibility. */
8138 case 'k':
252b5132 8139 break;
4cc782b5
ILT		 8140
8141 case 's':
8142 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 8143 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 8144 break;
99ad8390 8145#endif
321098a5
L		 8146#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8147 || defined (TE_PE) || defined (TE_PEP))
3e73aa7c
JH		 8148 case OPTION_64:
8149 {
8150 const char **list, **l;
8151
3e73aa7c
JH		 8152 list = bfd_target_list ();
8153 for (l = list; *l != NULL; l++)
8620418b 8154 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 8155 || strcmp (*l, "coff-x86-64") == 0
8156 || strcmp (*l, "pe-x86-64") == 0
8157 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 8158 {
8159 default_arch = "x86_64";
8160 break;
8161 }
3e73aa7c 8162 if (*l == NULL)
6e0b89ee 8163 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 8164 free (list);
8165 }
8166 break;
8167#endif
252b5132 8168
6e0b89ee
AM		 8169 case OPTION_32:
8170 default_arch = "i386";
8171 break;
8172
b3b91714
AM		 8173 case OPTION_DIVIDE:
8174#ifdef SVR4_COMMENT_CHARS
8175 {
8176 char *n, *t;
8177 const char *s;
8178
8179 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
8180 t = n;
8181 for (s = i386_comment_chars; *s != '\0'; s++)
8182 if (*s != '/')
8183 *t++ = *s;
8184 *t = '\0';
8185 i386_comment_chars = n;
8186 }
8187#endif
8188 break;
8189
9103f4f4 8190 case OPTION_MARCH:
6305a203
L		 8191 arch = xstrdup (arg);
8192 do
9103f4f4 8193 {
6305a203
L		 8194 if (*arch == '.')
8195 as_fatal (_("Invalid -march= option: `%s'"), arg);
8196 next = strchr (arch, '+');
8197 if (next)
8198 *next++ = '\0';
91d6fa6a 8199 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8200 {
91d6fa6a 8201 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 8202 {
6305a203 8203 /* Processor. */
1ded5609
JB		 8204 if (! cpu_arch[j].flags.bitfield.cpui386)
8205 continue;
8206
91d6fa6a 8207 cpu_arch_name = cpu_arch[j].name;
6305a203 8208 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 8209 cpu_arch_flags = cpu_arch[j].flags;
8210 cpu_arch_isa = cpu_arch[j].type;
8211 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 8212 if (!cpu_arch_tune_set)
8213 {
8214 cpu_arch_tune = cpu_arch_isa;
8215 cpu_arch_tune_flags = cpu_arch_isa_flags;
8216 }
8217 break;
8218 }
91d6fa6a
NC		 8219 else if (*cpu_arch [j].name == '.'
8220 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 8221 {
8222 /* ISA entension. */
8223 i386_cpu_flags flags;
309d3373 8224
49021df2 8225 if (!cpu_arch[j].negated)
309d3373 8226 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 8227 cpu_arch[j].flags);
309d3373
JB		 8228 else
8229 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 8230 cpu_arch[j].flags);
0dfbf9d7 8231 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 8232 {
8233 if (cpu_sub_arch_name)
8234 {
8235 char *name = cpu_sub_arch_name;
8236 cpu_sub_arch_name = concat (name,
91d6fa6a 8237 cpu_arch[j].name,
1bf57e9f 8238 (const char *) NULL);
6305a203
L		 8239 free (name);
8240 }
8241 else
91d6fa6a 8242 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203
L		 8243 cpu_arch_flags = flags;
8244 }
8245 break;
ccc9c027 8246 }
9103f4f4 8247 }
6305a203 8248
91d6fa6a 8249 if (j >= ARRAY_SIZE (cpu_arch))
6305a203
L		 8250 as_fatal (_("Invalid -march= option: `%s'"), arg);
8251
8252 arch = next;
9103f4f4 8253 }
6305a203 8254 while (next != NULL );
9103f4f4
L		 8255 break;
8256
8257 case OPTION_MTUNE:
8258 if (*arg == '.')
8259 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
91d6fa6a 8260 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 8261 {
91d6fa6a 8262 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 8263 {
ccc9c027 8264 cpu_arch_tune_set = 1;
91d6fa6a
NC		 8265 cpu_arch_tune = cpu_arch [j].type;
8266 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 8267 break;
8268 }
8269 }
91d6fa6a 8270 if (j >= ARRAY_SIZE (cpu_arch))
9103f4f4
L		 8271 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8272 break;
8273
1efbbeb4
L		 8274 case OPTION_MMNEMONIC:
8275 if (strcasecmp (arg, "att") == 0)
8276 intel_mnemonic = 0;
8277 else if (strcasecmp (arg, "intel") == 0)
8278 intel_mnemonic = 1;
8279 else
8280 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
8281 break;
8282
8283 case OPTION_MSYNTAX:
8284 if (strcasecmp (arg, "att") == 0)
8285 intel_syntax = 0;
8286 else if (strcasecmp (arg, "intel") == 0)
8287 intel_syntax = 1;
8288 else
8289 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
8290 break;
8291
8292 case OPTION_MINDEX_REG:
8293 allow_index_reg = 1;
8294 break;
8295
8296 case OPTION_MNAKED_REG:
8297 allow_naked_reg = 1;
8298 break;
8299
8300 case OPTION_MOLD_GCC:
8301 old_gcc = 1;
1efbbeb4
L		 8302 break;
8303
c0f3af97
L		 8304 case OPTION_MSSE2AVX:
8305 sse2avx = 1;
8306 break;
8307
daf50ae7
L		 8308 case OPTION_MSSE_CHECK:
8309 if (strcasecmp (arg, "error") == 0)
8310 sse_check = sse_check_error;
8311 else if (strcasecmp (arg, "warning") == 0)
8312 sse_check = sse_check_warning;
8313 else if (strcasecmp (arg, "none") == 0)
8314 sse_check = sse_check_none;
8315 else
8316 as_fatal (_("Invalid -msse-check= option: `%s'"), arg);
8317 break;
8318
539f890d
L		 8319 case OPTION_MAVXSCALAR:
8320 if (strcasecmp (arg, "128") == 0)
8321 avxscalar = vex128;
8322 else if (strcasecmp (arg, "256") == 0)
8323 avxscalar = vex256;
8324 else
8325 as_fatal (_("Invalid -mavxscalar= option: `%s'"), arg);
8326 break;
8327
252b5132
RH		 8328 default:
8329 return 0;
8330 }
8331 return 1;
8332}
8333
8a2c8fef
L		 8334#define MESSAGE_TEMPLATE \
8335" "
8336
8337static void
1ded5609 8338show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 8339{
8340 static char message[] = MESSAGE_TEMPLATE;
8341 char *start = message + 27;
8342 char *p;
8343 int size = sizeof (MESSAGE_TEMPLATE);
8344 int left;
8345 const char *name;
8346 int len;
8347 unsigned int j;
8348
8349 p = start;
8350 left = size - (start - message);
8351 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
8352 {
8353 /* Should it be skipped? */
8354 if (cpu_arch [j].skip)
8355 continue;
8356
8357 name = cpu_arch [j].name;
8358 len = cpu_arch [j].len;
8359 if (*name == '.')
8360 {
8361 /* It is an extension. Skip if we aren't asked to show it. */
8362 if (ext)
8363 {
8364 name++;
8365 len--;
8366 }
8367 else
8368 continue;
8369 }
8370 else if (ext)
8371 {
8372 /* It is an processor. Skip if we show only extension. */
8373 continue;
8374 }
1ded5609
JB		 8375 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
8376 {
8377 /* It is an impossible processor - skip. */
8378 continue;
8379 }
8a2c8fef
L		 8380
8381 /* Reserve 2 spaces for ", " or ",\0" */
8382 left -= len + 2;
8383
8384 /* Check if there is any room. */
8385 if (left >= 0)
8386 {
8387 if (p != start)
8388 {
8389 *p++ = ',';
8390 *p++ = ' ';
8391 }
8392 p = mempcpy (p, name, len);
8393 }
8394 else
8395 {
8396 /* Output the current message now and start a new one. */
8397 *p++ = ',';
8398 *p = '\0';
8399 fprintf (stream, "%s\n", message);
8400 p = start;
8401 left = size - (start - message) - len - 2;
8402
8403 gas_assert (left >= 0);
8404
8405 p = mempcpy (p, name, len);
8406 }
8407 }
8408
8409 *p = '\0';
8410 fprintf (stream, "%s\n", message);
8411}
8412
252b5132 8413void
8a2c8fef 8414md_show_usage (FILE *stream)
252b5132 8415{
4cc782b5
ILT		 8416#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8417 fprintf (stream, _("\
a38cf1db
AM		 8418 -Q ignored\n\
8419 -V print assembler version number\n\
b3b91714
AM		 8420 -k ignored\n"));
8421#endif
8422 fprintf (stream, _("\
12b55ccc 8423 -n Do not optimize code alignment\n\
b3b91714
AM		 8424 -q quieten some warnings\n"));
8425#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8426 fprintf (stream, _("\
a38cf1db 8427 -s ignored\n"));
b3b91714 8428#endif
321098a5
L		 8429#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8430 || defined (TE_PE) || defined (TE_PEP))
751d281c
L		 8431 fprintf (stream, _("\
8432 --32/--64 generate 32bit/64bit code\n"));
8433#endif
b3b91714
AM		 8434#ifdef SVR4_COMMENT_CHARS
8435 fprintf (stream, _("\
8436 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 8437#else
8438 fprintf (stream, _("\
b3b91714 8439 --divide ignored\n"));
4cc782b5 8440#endif
9103f4f4 8441 fprintf (stream, _("\
6305a203 8442 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 8443 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 8444 show_arch (stream, 0, 1);
8a2c8fef
L		 8445 fprintf (stream, _("\
8446 EXTENSION is combination of:\n"));
1ded5609 8447 show_arch (stream, 1, 0);
6305a203 8448 fprintf (stream, _("\
8a2c8fef 8449 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 8450 show_arch (stream, 0, 0);
ba104c83 8451 fprintf (stream, _("\
c0f3af97
L		 8452 -msse2avx encode SSE instructions with VEX prefix\n"));
8453 fprintf (stream, _("\
daf50ae7
L		 8454 -msse-check=[none|error|warning]\n\
8455 check SSE instructions\n"));
8456 fprintf (stream, _("\
539f890d
L		 8457 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
8458 length\n"));
8459 fprintf (stream, _("\
ba104c83
L		 8460 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8461 fprintf (stream, _("\
8462 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8463 fprintf (stream, _("\
8464 -mindex-reg support pseudo index registers\n"));
8465 fprintf (stream, _("\
8466 -mnaked-reg don't require `%%' prefix for registers\n"));
8467 fprintf (stream, _("\
8468 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 8469}
8470
3e73aa7c 8471#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 8472 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 8473 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 8474
8475/* Pick the target format to use. */
8476
47926f60 8477const char *
e3bb37b5 8478i386_target_format (void)
252b5132 8479{
3e73aa7c 8480 if (!strcmp (default_arch, "x86_64"))
78f12dd3 8481 update_code_flag (CODE_64BIT, 1);
3e73aa7c 8482 else if (!strcmp (default_arch, "i386"))
78f12dd3 8483 update_code_flag (CODE_32BIT, 1);
3e73aa7c
JH		 8484 else
8485 as_fatal (_("Unknown architecture"));
89507696
JB		 8486
8487 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
8488 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
8489 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
8490 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
8491
252b5132
RH		 8492 switch (OUTPUT_FLAVOR)
8493 {
9384f2ff 8494#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 8495 case bfd_target_aout_flavour:
47926f60 8496 return AOUT_TARGET_FORMAT;
4c63da97 8497#endif
9384f2ff
AM		 8498#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8499# if defined (TE_PE) || defined (TE_PEP)
8500 case bfd_target_coff_flavour:
8501 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
8502# elif defined (TE_GO32)
0561d57c
JK		 8503 case bfd_target_coff_flavour:
8504 return "coff-go32";
9384f2ff 8505# else
252b5132
RH		 8506 case bfd_target_coff_flavour:
8507 return "coff-i386";
9384f2ff 8508# endif
4c63da97 8509#endif
3e73aa7c 8510#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 8511 case bfd_target_elf_flavour:
3e73aa7c 8512 {
e5cb08ac 8513 if (flag_code == CODE_64BIT)
4fa24527
JB		 8514 {
8515 object_64bit = 1;
8516 use_rela_relocations = 1;
8517 }
3632d14b 8518 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 8519 {
8520 if (flag_code != CODE_64BIT)
8521 as_fatal (_("Intel L1OM is 64bit only"));
8522 return ELF_TARGET_L1OM_FORMAT;
8523 }
8524 else
8525 return (flag_code == CODE_64BIT
8526 ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT);
3e73aa7c 8527 }
e57f8c65
TG		 8528#endif
8529#if defined (OBJ_MACH_O)
8530 case bfd_target_mach_o_flavour:
8531 return flag_code == CODE_64BIT ? "mach-o-x86-64" : "mach-o-i386";
4c63da97 8532#endif
252b5132
RH		 8533 default:
8534 abort ();
8535 return NULL;
8536 }
8537}
8538
47926f60 8539#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 8540
8541#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 8542void
8543i386_elf_emit_arch_note (void)
a847613f 8544{
718ddfc0 8545 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 8546 {
8547 char *p;
8548 asection *seg = now_seg;
8549 subsegT subseg = now_subseg;
8550 Elf_Internal_Note i_note;
8551 Elf_External_Note e_note;
8552 asection *note_secp;
8553 int len;
8554
8555 /* Create the .note section. */
8556 note_secp = subseg_new (".note", 0);
8557 bfd_set_section_flags (stdoutput,
8558 note_secp,
8559 SEC_HAS_CONTENTS | SEC_READONLY);
8560
8561 /* Process the arch string. */
8562 len = strlen (cpu_arch_name);
8563
8564 i_note.namesz = len + 1;
8565 i_note.descsz = 0;
8566 i_note.type = NT_ARCH;
8567 p = frag_more (sizeof (e_note.namesz));
8568 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8569 p = frag_more (sizeof (e_note.descsz));
8570 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8571 p = frag_more (sizeof (e_note.type));
8572 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8573 p = frag_more (len + 1);
8574 strcpy (p, cpu_arch_name);
8575
8576 frag_align (2, 0, 0);
8577
8578 subseg_set (seg, subseg);
8579 }
8580}
8581#endif
252b5132 8582\f
252b5132
RH		 8583symbolS *
8584md_undefined_symbol (name)
8585 char *name;
8586{
18dc2407
ILT		 8587 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8588 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8589 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8590 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 8591 {
8592 if (!GOT_symbol)
8593 {
8594 if (symbol_find (name))
8595 as_bad (_("GOT already in symbol table"));
8596 GOT_symbol = symbol_new (name, undefined_section,
8597 (valueT) 0, &zero_address_frag);
8598 };
8599 return GOT_symbol;
8600 }
252b5132
RH		 8601 return 0;
8602}
8603
8604/* Round up a section size to the appropriate boundary. */
47926f60 8605
252b5132
RH		 8606valueT
8607md_section_align (segment, size)
ab9da554 8608 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 8609 valueT size;
8610{
4c63da97
AM		 8611#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8612 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8613 {
8614 /* For a.out, force the section size to be aligned. If we don't do
8615 this, BFD will align it for us, but it will not write out the
8616 final bytes of the section. This may be a bug in BFD, but it is
8617 easier to fix it here since that is how the other a.out targets
8618 work. */
8619 int align;
8620
8621 align = bfd_get_section_alignment (stdoutput, segment);
8622 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8623 }
252b5132
RH		 8624#endif
8625
8626 return size;
8627}
8628
8629/* On the i386, PC-relative offsets are relative to the start of the
8630 next instruction. That is, the address of the offset, plus its
8631 size, since the offset is always the last part of the insn. */
8632
8633long
e3bb37b5 8634md_pcrel_from (fixS *fixP)
252b5132
RH		 8635{
8636 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8637}
8638
8639#ifndef I386COFF
8640
8641static void
e3bb37b5 8642s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 8643{
29b0f896 8644 int temp;
252b5132 8645
8a75718c
JB		 8646#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8647 if (IS_ELF)
8648 obj_elf_section_change_hook ();
8649#endif
252b5132
RH		 8650 temp = get_absolute_expression ();
8651 subseg_set (bss_section, (subsegT) temp);
8652 demand_empty_rest_of_line ();
8653}
8654
8655#endif
8656
252b5132 8657void
e3bb37b5 8658i386_validate_fix (fixS *fixp)
252b5132
RH		 8659{
8660 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8661 {
23df1078
JH		 8662 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8663 {
4fa24527 8664 if (!object_64bit)
23df1078
JH		 8665 abort ();
8666 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8667 }
8668 else
8669 {
4fa24527 8670 if (!object_64bit)
d6ab8113
JB		 8671 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8672 else
8673 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 8674 }
252b5132
RH		 8675 fixp->fx_subsy = 0;
8676 }
8677}
8678
252b5132
RH		 8679arelent *
8680tc_gen_reloc (section, fixp)
ab9da554 8681 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 8682 fixS *fixp;
8683{
8684 arelent *rel;
8685 bfd_reloc_code_real_type code;
8686
8687 switch (fixp->fx_r_type)
8688 {
3e73aa7c
JH		 8689 case BFD_RELOC_X86_64_PLT32:
8690 case BFD_RELOC_X86_64_GOT32:
8691 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 8692 case BFD_RELOC_386_PLT32:
8693 case BFD_RELOC_386_GOT32:
8694 case BFD_RELOC_386_GOTOFF:
8695 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 8696 case BFD_RELOC_386_TLS_GD:
8697 case BFD_RELOC_386_TLS_LDM:
8698 case BFD_RELOC_386_TLS_LDO_32:
8699 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8700 case BFD_RELOC_386_TLS_IE:
8701 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 8702 case BFD_RELOC_386_TLS_LE_32:
8703 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 8704 case BFD_RELOC_386_TLS_GOTDESC:
8705 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 8706 case BFD_RELOC_X86_64_TLSGD:
8707 case BFD_RELOC_X86_64_TLSLD:
8708 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8709 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 8710 case BFD_RELOC_X86_64_GOTTPOFF:
8711 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 8712 case BFD_RELOC_X86_64_TPOFF64:
8713 case BFD_RELOC_X86_64_GOTOFF64:
8714 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 8715 case BFD_RELOC_X86_64_GOT64:
8716 case BFD_RELOC_X86_64_GOTPCREL64:
8717 case BFD_RELOC_X86_64_GOTPC64:
8718 case BFD_RELOC_X86_64_GOTPLT64:
8719 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 8720 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8721 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 8722 case BFD_RELOC_RVA:
8723 case BFD_RELOC_VTABLE_ENTRY:
8724 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 8725#ifdef TE_PE
8726 case BFD_RELOC_32_SECREL:
8727#endif
252b5132
RH		 8728 code = fixp->fx_r_type;
8729 break;
dbbaec26
L		 8730 case BFD_RELOC_X86_64_32S:
8731 if (!fixp->fx_pcrel)
8732 {
8733 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8734 code = fixp->fx_r_type;
8735 break;
8736 }
252b5132 8737 default:
93382f6d 8738 if (fixp->fx_pcrel)
252b5132 8739 {
93382f6d
AM		 8740 switch (fixp->fx_size)
8741 {
8742 default:
b091f402
AM		 8743 as_bad_where (fixp->fx_file, fixp->fx_line,
8744 _("can not do %d byte pc-relative relocation"),
8745 fixp->fx_size);
93382f6d
AM		 8746 code = BFD_RELOC_32_PCREL;
8747 break;
8748 case 1: code = BFD_RELOC_8_PCREL; break;
8749 case 2: code = BFD_RELOC_16_PCREL; break;
8750 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 8751#ifdef BFD64
8752 case 8: code = BFD_RELOC_64_PCREL; break;
8753#endif
93382f6d
AM		 8754 }
8755 }
8756 else
8757 {
8758 switch (fixp->fx_size)
8759 {
8760 default:
b091f402
AM		 8761 as_bad_where (fixp->fx_file, fixp->fx_line,
8762 _("can not do %d byte relocation"),
8763 fixp->fx_size);
93382f6d
AM		 8764 code = BFD_RELOC_32;
8765 break;
8766 case 1: code = BFD_RELOC_8; break;
8767 case 2: code = BFD_RELOC_16; break;
8768 case 4: code = BFD_RELOC_32; break;
937149dd 8769#ifdef BFD64
3e73aa7c 8770 case 8: code = BFD_RELOC_64; break;
937149dd 8771#endif
93382f6d 8772 }
252b5132
RH		 8773 }
8774 break;
8775 }
252b5132 8776
d182319b
JB		 8777 if ((code == BFD_RELOC_32
8778 || code == BFD_RELOC_32_PCREL
8779 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 8780 && GOT_symbol
8781 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 8782 {
4fa24527 8783 if (!object_64bit)
d6ab8113
JB		 8784 code = BFD_RELOC_386_GOTPC;
8785 else
8786 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 8787 }
7b81dfbb
AJ		 8788 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
8789 && GOT_symbol
8790 && fixp->fx_addsy == GOT_symbol)
8791 {
8792 code = BFD_RELOC_X86_64_GOTPC64;
8793 }
252b5132
RH		 8794
8795 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 8796 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
8797 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 8798
8799 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 8800
3e73aa7c
JH		 8801 if (!use_rela_relocations)
8802 {
8803 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8804 vtable entry to be used in the relocation's section offset. */
8805 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8806 rel->address = fixp->fx_offset;
fbeb56a4
DK		 8807#if defined (OBJ_COFF) && defined (TE_PE)
8808 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
8809 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
8810 else
8811#endif
c6682705 8812 rel->addend = 0;
3e73aa7c
JH		 8813 }
8814 /* Use the rela in 64bit mode. */
252b5132 8815 else
3e73aa7c 8816 {
062cd5e7
AS		 8817 if (!fixp->fx_pcrel)
8818 rel->addend = fixp->fx_offset;
8819 else
8820 switch (code)
8821 {
8822 case BFD_RELOC_X86_64_PLT32:
8823 case BFD_RELOC_X86_64_GOT32:
8824 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 8825 case BFD_RELOC_X86_64_TLSGD:
8826 case BFD_RELOC_X86_64_TLSLD:
8827 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 8828 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8829 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 8830 rel->addend = fixp->fx_offset - fixp->fx_size;
8831 break;
8832 default:
8833 rel->addend = (section->vma
8834 - fixp->fx_size
8835 + fixp->fx_addnumber
8836 + md_pcrel_from (fixp));
8837 break;
8838 }
3e73aa7c
JH		 8839 }
8840
252b5132
RH		 8841 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
8842 if (rel->howto == NULL)
8843 {
8844 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 8845 _("cannot represent relocation type %s"),
252b5132
RH		 8846 bfd_get_reloc_code_name (code));
8847 /* Set howto to a garbage value so that we can keep going. */
8848 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 8849 gas_assert (rel->howto != NULL);
252b5132
RH		 8850 }
8851
8852 return rel;
8853}
8854
ee86248c 8855#include "tc-i386-intel.c"
54cfded0 8856
a60de03c
JB		 8857void
8858tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 8859{
a60de03c
JB		 8860 int saved_naked_reg;
8861 char saved_register_dot;
54cfded0 8862
a60de03c
JB		 8863 saved_naked_reg = allow_naked_reg;
8864 allow_naked_reg = 1;
8865 saved_register_dot = register_chars['.'];
8866 register_chars['.'] = '.';
8867 allow_pseudo_reg = 1;
8868 expression_and_evaluate (exp);
8869 allow_pseudo_reg = 0;
8870 register_chars['.'] = saved_register_dot;
8871 allow_naked_reg = saved_naked_reg;
8872
e96d56a1 8873 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 8874 {
a60de03c
JB		 8875 if ((addressT) exp->X_add_number < i386_regtab_size)
8876 {
8877 exp->X_op = O_constant;
8878 exp->X_add_number = i386_regtab[exp->X_add_number]
8879 .dw2_regnum[flag_code >> 1];
8880 }
8881 else
8882 exp->X_op = O_illegal;
54cfded0 8883 }
54cfded0
AM		 8884}
8885
8886void
8887tc_x86_frame_initial_instructions (void)
8888{
a60de03c
JB		 8889 static unsigned int sp_regno[2];
8890
8891 if (!sp_regno[flag_code >> 1])
8892 {
8893 char *saved_input = input_line_pointer;
8894 char sp[][4] = {"esp", "rsp"};
8895 expressionS exp;
a4447b93 8896
a60de03c
JB		 8897 input_line_pointer = sp[flag_code >> 1];
8898 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 8899 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 8900 sp_regno[flag_code >> 1] = exp.X_add_number;
8901 input_line_pointer = saved_input;
8902 }
a4447b93 8903
a60de03c 8904 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
a4447b93 8905 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 8906}
d2b2c203
DJ		 8907
8908int
8909i386_elf_section_type (const char *str, size_t len)
8910{
8911 if (flag_code == CODE_64BIT
8912 && len == sizeof ("unwind") - 1
8913 && strncmp (str, "unwind", 6) == 0)
8914 return SHT_X86_64_UNWIND;
8915
8916 return -1;
8917}
bb41ade5 8918
ad5fec3b
EB		 8919#ifdef TE_SOLARIS
8920void
8921i386_solaris_fix_up_eh_frame (segT sec)
8922{
8923 if (flag_code == CODE_64BIT)
8924 elf_section_type (sec) = SHT_X86_64_UNWIND;
8925}
8926#endif
8927
bb41ade5
AM		 8928#ifdef TE_PE
8929void
8930tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
8931{
91d6fa6a 8932 expressionS exp;
bb41ade5 8933
91d6fa6a
NC		 8934 exp.X_op = O_secrel;
8935 exp.X_add_symbol = symbol;
8936 exp.X_add_number = 0;
8937 emit_expr (&exp, size);
bb41ade5
AM		 8938}
8939#endif
3b22753a
L		 8940
8941#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8942/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8943
01e1a5bc 8944bfd_vma
3b22753a
L		 8945x86_64_section_letter (int letter, char **ptr_msg)
8946{
8947 if (flag_code == CODE_64BIT)
8948 {
8949 if (letter == 'l')
8950 return SHF_X86_64_LARGE;
8951
8f3bae45 8952 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 8953 }
3b22753a 8954 else
8f3bae45 8955 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 8956 return -1;
8957}
8958
01e1a5bc 8959bfd_vma
3b22753a
L		 8960x86_64_section_word (char *str, size_t len)
8961{
8620418b 8962 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 8963 return SHF_X86_64_LARGE;
8964
8965 return -1;
8966}
8967
8968static void
8969handle_large_common (int small ATTRIBUTE_UNUSED)
8970{
8971 if (flag_code != CODE_64BIT)
8972 {
8973 s_comm_internal (0, elf_common_parse);
8974 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8975 }
8976 else
8977 {
8978 static segT lbss_section;
8979 asection *saved_com_section_ptr = elf_com_section_ptr;
8980 asection *saved_bss_section = bss_section;
8981
8982 if (lbss_section == NULL)
8983 {
8984 flagword applicable;
8985 segT seg = now_seg;
8986 subsegT subseg = now_subseg;
8987
8988 /* The .lbss section is for local .largecomm symbols. */
8989 lbss_section = subseg_new (".lbss", 0);
8990 applicable = bfd_applicable_section_flags (stdoutput);
8991 bfd_set_section_flags (stdoutput, lbss_section,
8992 applicable & SEC_ALLOC);
8993 seg_info (lbss_section)->bss = 1;
8994
8995 subseg_set (seg, subseg);
8996 }
8997
8998 elf_com_section_ptr = &_bfd_elf_large_com_section;
8999 bss_section = lbss_section;
9000
9001 s_comm_internal (0, elf_common_parse);
9002
9003 elf_com_section_ptr = saved_com_section_ptr;
9004 bss_section = saved_bss_section;
9005 }
9006}
9007#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
GDB Binutils - Deliverables
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