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b534c6d3 | 1 | /* tc-i386.c -- Assemble code for the Intel 80386 |
82704155 | 2 | Copyright (C) 1989-2019 Free Software Foundation, Inc. |
252b5132 RH |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
19 | 02110-1301, USA. */ | |
252b5132 | 20 | |
47926f60 KH |
21 | /* Intel 80386 machine specific gas. |
22 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 23 | x86_64 support by Jan Hubicka (jh@suse.cz) |
0f10071e | 24 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
47926f60 KH |
25 | Bugs & suggestions are completely welcome. This is free software. |
26 | Please help us make it better. */ | |
252b5132 | 27 | |
252b5132 | 28 | #include "as.h" |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | #include "subsegs.h" |
316e2c05 | 31 | #include "dwarf2dbg.h" |
54cfded0 | 32 | #include "dw2gencfi.h" |
d2b2c203 | 33 | #include "elf/x86-64.h" |
40fb9820 | 34 | #include "opcodes/i386-init.h" |
252b5132 | 35 | |
41fd2579 L |
36 | #ifdef HAVE_LIMITS_H |
37 | #include <limits.h> | |
38 | #else | |
39 | #ifdef HAVE_SYS_PARAM_H | |
40 | #include <sys/param.h> | |
41 | #endif | |
42 | #ifndef INT_MAX | |
43 | #define INT_MAX (int) (((unsigned) (-1)) >> 1) | |
44 | #endif | |
45 | #endif | |
46 | ||
252b5132 RH |
47 | #ifndef REGISTER_WARNINGS |
48 | #define REGISTER_WARNINGS 1 | |
49 | #endif | |
50 | ||
c3332e24 | 51 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 52 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
53 | #endif |
54 | ||
29b0f896 AM |
55 | #ifndef DEFAULT_ARCH |
56 | #define DEFAULT_ARCH "i386" | |
246fcdee | 57 | #endif |
252b5132 | 58 | |
edde18a5 AM |
59 | #ifndef INLINE |
60 | #if __GNUC__ >= 2 | |
61 | #define INLINE __inline__ | |
62 | #else | |
63 | #define INLINE | |
64 | #endif | |
65 | #endif | |
66 | ||
6305a203 L |
67 | /* Prefixes will be emitted in the order defined below. |
68 | WAIT_PREFIX must be the first prefix since FWAIT is really is an | |
69 | instruction, and so must come before any prefixes. | |
70 | The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, | |
42164a71 | 71 | REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */ |
6305a203 L |
72 | #define WAIT_PREFIX 0 |
73 | #define SEG_PREFIX 1 | |
74 | #define ADDR_PREFIX 2 | |
75 | #define DATA_PREFIX 3 | |
c32fa91d | 76 | #define REP_PREFIX 4 |
42164a71 | 77 | #define HLE_PREFIX REP_PREFIX |
7e8b059b | 78 | #define BND_PREFIX REP_PREFIX |
c32fa91d | 79 | #define LOCK_PREFIX 5 |
4e9ac44a L |
80 | #define REX_PREFIX 6 /* must come last. */ |
81 | #define MAX_PREFIXES 7 /* max prefixes per opcode */ | |
6305a203 L |
82 | |
83 | /* we define the syntax here (modulo base,index,scale syntax) */ | |
84 | #define REGISTER_PREFIX '%' | |
85 | #define IMMEDIATE_PREFIX '$' | |
86 | #define ABSOLUTE_PREFIX '*' | |
87 | ||
88 | /* these are the instruction mnemonic suffixes in AT&T syntax or | |
89 | memory operand size in Intel syntax. */ | |
90 | #define WORD_MNEM_SUFFIX 'w' | |
91 | #define BYTE_MNEM_SUFFIX 'b' | |
92 | #define SHORT_MNEM_SUFFIX 's' | |
93 | #define LONG_MNEM_SUFFIX 'l' | |
94 | #define QWORD_MNEM_SUFFIX 'q' | |
6305a203 L |
95 | /* Intel Syntax. Use a non-ascii letter since since it never appears |
96 | in instructions. */ | |
97 | #define LONG_DOUBLE_MNEM_SUFFIX '\1' | |
98 | ||
99 | #define END_OF_INSN '\0' | |
100 | ||
101 | /* | |
102 | 'templates' is for grouping together 'template' structures for opcodes | |
103 | of the same name. This is only used for storing the insns in the grand | |
104 | ole hash table of insns. | |
105 | The templates themselves start at START and range up to (but not including) | |
106 | END. | |
107 | */ | |
108 | typedef struct | |
109 | { | |
d3ce72d0 NC |
110 | const insn_template *start; |
111 | const insn_template *end; | |
6305a203 L |
112 | } |
113 | templates; | |
114 | ||
115 | /* 386 operand encoding bytes: see 386 book for details of this. */ | |
116 | typedef struct | |
117 | { | |
118 | unsigned int regmem; /* codes register or memory operand */ | |
119 | unsigned int reg; /* codes register operand (or extended opcode) */ | |
120 | unsigned int mode; /* how to interpret regmem & reg */ | |
121 | } | |
122 | modrm_byte; | |
123 | ||
124 | /* x86-64 extension prefix. */ | |
125 | typedef int rex_byte; | |
126 | ||
6305a203 L |
127 | /* 386 opcode byte to code indirect addressing. */ |
128 | typedef struct | |
129 | { | |
130 | unsigned base; | |
131 | unsigned index; | |
132 | unsigned scale; | |
133 | } | |
134 | sib_byte; | |
135 | ||
6305a203 L |
136 | /* x86 arch names, types and features */ |
137 | typedef struct | |
138 | { | |
139 | const char *name; /* arch name */ | |
8a2c8fef | 140 | unsigned int len; /* arch string length */ |
6305a203 L |
141 | enum processor_type type; /* arch type */ |
142 | i386_cpu_flags flags; /* cpu feature flags */ | |
8a2c8fef | 143 | unsigned int skip; /* show_arch should skip this. */ |
6305a203 L |
144 | } |
145 | arch_entry; | |
146 | ||
293f5f65 L |
147 | /* Used to turn off indicated flags. */ |
148 | typedef struct | |
149 | { | |
150 | const char *name; /* arch name */ | |
151 | unsigned int len; /* arch string length */ | |
152 | i386_cpu_flags flags; /* cpu feature flags */ | |
153 | } | |
154 | noarch_entry; | |
155 | ||
78f12dd3 | 156 | static void update_code_flag (int, int); |
e3bb37b5 L |
157 | static void set_code_flag (int); |
158 | static void set_16bit_gcc_code_flag (int); | |
159 | static void set_intel_syntax (int); | |
1efbbeb4 | 160 | static void set_intel_mnemonic (int); |
db51cc60 | 161 | static void set_allow_index_reg (int); |
7bab8ab5 | 162 | static void set_check (int); |
e3bb37b5 | 163 | static void set_cpu_arch (int); |
6482c264 | 164 | #ifdef TE_PE |
e3bb37b5 | 165 | static void pe_directive_secrel (int); |
6482c264 | 166 | #endif |
e3bb37b5 L |
167 | static void signed_cons (int); |
168 | static char *output_invalid (int c); | |
ee86248c JB |
169 | static int i386_finalize_immediate (segT, expressionS *, i386_operand_type, |
170 | const char *); | |
171 | static int i386_finalize_displacement (segT, expressionS *, i386_operand_type, | |
172 | const char *); | |
a7619375 | 173 | static int i386_att_operand (char *); |
e3bb37b5 | 174 | static int i386_intel_operand (char *, int); |
ee86248c JB |
175 | static int i386_intel_simplify (expressionS *); |
176 | static int i386_intel_parse_name (const char *, expressionS *); | |
e3bb37b5 L |
177 | static const reg_entry *parse_register (char *, char **); |
178 | static char *parse_insn (char *, char *); | |
179 | static char *parse_operands (char *, const char *); | |
180 | static void swap_operands (void); | |
4d456e3d | 181 | static void swap_2_operands (int, int); |
e3bb37b5 L |
182 | static void optimize_imm (void); |
183 | static void optimize_disp (void); | |
83b16ac6 | 184 | static const insn_template *match_template (char); |
e3bb37b5 L |
185 | static int check_string (void); |
186 | static int process_suffix (void); | |
187 | static int check_byte_reg (void); | |
188 | static int check_long_reg (void); | |
189 | static int check_qword_reg (void); | |
190 | static int check_word_reg (void); | |
191 | static int finalize_imm (void); | |
192 | static int process_operands (void); | |
193 | static const seg_entry *build_modrm_byte (void); | |
194 | static void output_insn (void); | |
195 | static void output_imm (fragS *, offsetT); | |
196 | static void output_disp (fragS *, offsetT); | |
29b0f896 | 197 | #ifndef I386COFF |
e3bb37b5 | 198 | static void s_bss (int); |
252b5132 | 199 | #endif |
17d4e2a2 L |
200 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
201 | static void handle_large_common (int small ATTRIBUTE_UNUSED); | |
b4a3a7b4 L |
202 | |
203 | /* GNU_PROPERTY_X86_ISA_1_USED. */ | |
204 | static unsigned int x86_isa_1_used; | |
205 | /* GNU_PROPERTY_X86_FEATURE_2_USED. */ | |
206 | static unsigned int x86_feature_2_used; | |
207 | /* Generate x86 used ISA and feature properties. */ | |
208 | static unsigned int x86_used_note = DEFAULT_X86_USED_NOTE; | |
17d4e2a2 | 209 | #endif |
252b5132 | 210 | |
a847613f | 211 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 212 | |
43234a1e L |
213 | /* This struct describes rounding control and SAE in the instruction. */ |
214 | struct RC_Operation | |
215 | { | |
216 | enum rc_type | |
217 | { | |
218 | rne = 0, | |
219 | rd, | |
220 | ru, | |
221 | rz, | |
222 | saeonly | |
223 | } type; | |
224 | int operand; | |
225 | }; | |
226 | ||
227 | static struct RC_Operation rc_op; | |
228 | ||
229 | /* The struct describes masking, applied to OPERAND in the instruction. | |
230 | MASK is a pointer to the corresponding mask register. ZEROING tells | |
231 | whether merging or zeroing mask is used. */ | |
232 | struct Mask_Operation | |
233 | { | |
234 | const reg_entry *mask; | |
235 | unsigned int zeroing; | |
236 | /* The operand where this operation is associated. */ | |
237 | int operand; | |
238 | }; | |
239 | ||
240 | static struct Mask_Operation mask_op; | |
241 | ||
242 | /* The struct describes broadcasting, applied to OPERAND. FACTOR is | |
243 | broadcast factor. */ | |
244 | struct Broadcast_Operation | |
245 | { | |
8e6e0792 | 246 | /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */ |
43234a1e L |
247 | int type; |
248 | ||
249 | /* Index of broadcasted operand. */ | |
250 | int operand; | |
4a1b91ea L |
251 | |
252 | /* Number of bytes to broadcast. */ | |
253 | int bytes; | |
43234a1e L |
254 | }; |
255 | ||
256 | static struct Broadcast_Operation broadcast_op; | |
257 | ||
c0f3af97 L |
258 | /* VEX prefix. */ |
259 | typedef struct | |
260 | { | |
43234a1e L |
261 | /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */ |
262 | unsigned char bytes[4]; | |
c0f3af97 L |
263 | unsigned int length; |
264 | /* Destination or source register specifier. */ | |
265 | const reg_entry *register_specifier; | |
266 | } vex_prefix; | |
267 | ||
252b5132 | 268 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 269 | i386_insn. */ |
252b5132 | 270 | |
520dc8e8 AM |
271 | union i386_op |
272 | { | |
273 | expressionS *disps; | |
274 | expressionS *imms; | |
275 | const reg_entry *regs; | |
276 | }; | |
277 | ||
a65babc9 L |
278 | enum i386_error |
279 | { | |
86e026a4 | 280 | operand_size_mismatch, |
a65babc9 L |
281 | operand_type_mismatch, |
282 | register_type_mismatch, | |
283 | number_of_operands_mismatch, | |
284 | invalid_instruction_suffix, | |
285 | bad_imm4, | |
a65babc9 L |
286 | unsupported_with_intel_mnemonic, |
287 | unsupported_syntax, | |
6c30d220 L |
288 | unsupported, |
289 | invalid_vsib_address, | |
7bab8ab5 | 290 | invalid_vector_register_set, |
43234a1e L |
291 | unsupported_vector_index_register, |
292 | unsupported_broadcast, | |
43234a1e L |
293 | broadcast_needed, |
294 | unsupported_masking, | |
295 | mask_not_on_destination, | |
296 | no_default_mask, | |
297 | unsupported_rc_sae, | |
298 | rc_sae_operand_not_last_imm, | |
299 | invalid_register_operand, | |
a65babc9 L |
300 | }; |
301 | ||
252b5132 RH |
302 | struct _i386_insn |
303 | { | |
47926f60 | 304 | /* TM holds the template for the insn were currently assembling. */ |
d3ce72d0 | 305 | insn_template tm; |
252b5132 | 306 | |
7d5e4556 L |
307 | /* SUFFIX holds the instruction size suffix for byte, word, dword |
308 | or qword, if given. */ | |
252b5132 RH |
309 | char suffix; |
310 | ||
47926f60 | 311 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
312 | unsigned int operands; |
313 | ||
314 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
315 | of given register, displacement, memory operands and immediate | |
47926f60 | 316 | operands. */ |
252b5132 RH |
317 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
318 | ||
319 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 320 | use OP[i] for the corresponding operand. */ |
40fb9820 | 321 | i386_operand_type types[MAX_OPERANDS]; |
252b5132 | 322 | |
520dc8e8 AM |
323 | /* Displacement expression, immediate expression, or register for each |
324 | operand. */ | |
325 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 326 | |
3e73aa7c JH |
327 | /* Flags for operands. */ |
328 | unsigned int flags[MAX_OPERANDS]; | |
329 | #define Operand_PCrel 1 | |
c48dadc9 | 330 | #define Operand_Mem 2 |
3e73aa7c | 331 | |
252b5132 | 332 | /* Relocation type for operand */ |
f86103b7 | 333 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
252b5132 | 334 | |
252b5132 RH |
335 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
336 | the base index byte below. */ | |
337 | const reg_entry *base_reg; | |
338 | const reg_entry *index_reg; | |
339 | unsigned int log2_scale_factor; | |
340 | ||
341 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 342 | explicit segment overrides are given. */ |
ce8a8b2f | 343 | const seg_entry *seg[2]; |
252b5132 | 344 | |
8325cc63 JB |
345 | /* Copied first memory operand string, for re-checking. */ |
346 | char *memop1_string; | |
347 | ||
252b5132 RH |
348 | /* PREFIX holds all the given prefix opcodes (usually null). |
349 | PREFIXES is the number of prefix opcodes. */ | |
350 | unsigned int prefixes; | |
351 | unsigned char prefix[MAX_PREFIXES]; | |
352 | ||
b4a3a7b4 L |
353 | /* Has MMX register operands. */ |
354 | bfd_boolean has_regmmx; | |
355 | ||
356 | /* Has XMM register operands. */ | |
357 | bfd_boolean has_regxmm; | |
358 | ||
359 | /* Has YMM register operands. */ | |
360 | bfd_boolean has_regymm; | |
361 | ||
362 | /* Has ZMM register operands. */ | |
363 | bfd_boolean has_regzmm; | |
364 | ||
252b5132 | 365 | /* RM and SIB are the modrm byte and the sib byte where the |
c1e679ec | 366 | addressing modes of this insn are encoded. */ |
252b5132 | 367 | modrm_byte rm; |
3e73aa7c | 368 | rex_byte rex; |
43234a1e | 369 | rex_byte vrex; |
252b5132 | 370 | sib_byte sib; |
c0f3af97 | 371 | vex_prefix vex; |
b6169b20 | 372 | |
43234a1e L |
373 | /* Masking attributes. */ |
374 | struct Mask_Operation *mask; | |
375 | ||
376 | /* Rounding control and SAE attributes. */ | |
377 | struct RC_Operation *rounding; | |
378 | ||
379 | /* Broadcasting attributes. */ | |
380 | struct Broadcast_Operation *broadcast; | |
381 | ||
382 | /* Compressed disp8*N attribute. */ | |
383 | unsigned int memshift; | |
384 | ||
86fa6981 L |
385 | /* Prefer load or store in encoding. */ |
386 | enum | |
387 | { | |
388 | dir_encoding_default = 0, | |
389 | dir_encoding_load, | |
64c49ab3 JB |
390 | dir_encoding_store, |
391 | dir_encoding_swap | |
86fa6981 | 392 | } dir_encoding; |
891edac4 | 393 | |
a501d77e L |
394 | /* Prefer 8bit or 32bit displacement in encoding. */ |
395 | enum | |
396 | { | |
397 | disp_encoding_default = 0, | |
398 | disp_encoding_8bit, | |
399 | disp_encoding_32bit | |
400 | } disp_encoding; | |
f8a5c266 | 401 | |
6b6b6807 L |
402 | /* Prefer the REX byte in encoding. */ |
403 | bfd_boolean rex_encoding; | |
404 | ||
b6f8c7c4 L |
405 | /* Disable instruction size optimization. */ |
406 | bfd_boolean no_optimize; | |
407 | ||
86fa6981 L |
408 | /* How to encode vector instructions. */ |
409 | enum | |
410 | { | |
411 | vex_encoding_default = 0, | |
412 | vex_encoding_vex2, | |
413 | vex_encoding_vex3, | |
414 | vex_encoding_evex | |
415 | } vec_encoding; | |
416 | ||
d5de92cf L |
417 | /* REP prefix. */ |
418 | const char *rep_prefix; | |
419 | ||
165de32a L |
420 | /* HLE prefix. */ |
421 | const char *hle_prefix; | |
42164a71 | 422 | |
7e8b059b L |
423 | /* Have BND prefix. */ |
424 | const char *bnd_prefix; | |
425 | ||
04ef582a L |
426 | /* Have NOTRACK prefix. */ |
427 | const char *notrack_prefix; | |
428 | ||
891edac4 | 429 | /* Error message. */ |
a65babc9 | 430 | enum i386_error error; |
252b5132 RH |
431 | }; |
432 | ||
433 | typedef struct _i386_insn i386_insn; | |
434 | ||
43234a1e L |
435 | /* Link RC type with corresponding string, that'll be looked for in |
436 | asm. */ | |
437 | struct RC_name | |
438 | { | |
439 | enum rc_type type; | |
440 | const char *name; | |
441 | unsigned int len; | |
442 | }; | |
443 | ||
444 | static const struct RC_name RC_NamesTable[] = | |
445 | { | |
446 | { rne, STRING_COMMA_LEN ("rn-sae") }, | |
447 | { rd, STRING_COMMA_LEN ("rd-sae") }, | |
448 | { ru, STRING_COMMA_LEN ("ru-sae") }, | |
449 | { rz, STRING_COMMA_LEN ("rz-sae") }, | |
450 | { saeonly, STRING_COMMA_LEN ("sae") }, | |
451 | }; | |
452 | ||
252b5132 RH |
453 | /* List of chars besides those in app.c:symbol_chars that can start an |
454 | operand. Used to prevent the scrubber eating vital white-space. */ | |
86fa6981 | 455 | const char extra_symbol_chars[] = "*%-([{}" |
252b5132 | 456 | #ifdef LEX_AT |
32137342 NC |
457 | "@" |
458 | #endif | |
459 | #ifdef LEX_QM | |
460 | "?" | |
252b5132 | 461 | #endif |
32137342 | 462 | ; |
252b5132 | 463 | |
29b0f896 AM |
464 | #if (defined (TE_I386AIX) \ |
465 | || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ | |
3896cfd5 | 466 | && !defined (TE_GNU) \ |
29b0f896 | 467 | && !defined (TE_LINUX) \ |
8d63c93e | 468 | && !defined (TE_NACL) \ |
29b0f896 | 469 | && !defined (TE_FreeBSD) \ |
5b806d27 | 470 | && !defined (TE_DragonFly) \ |
29b0f896 | 471 | && !defined (TE_NetBSD))) |
252b5132 | 472 | /* This array holds the chars that always start a comment. If the |
b3b91714 AM |
473 | pre-processor is disabled, these aren't very useful. The option |
474 | --divide will remove '/' from this list. */ | |
475 | const char *i386_comment_chars = "#/"; | |
476 | #define SVR4_COMMENT_CHARS 1 | |
252b5132 | 477 | #define PREFIX_SEPARATOR '\\' |
252b5132 | 478 | |
b3b91714 AM |
479 | #else |
480 | const char *i386_comment_chars = "#"; | |
481 | #define PREFIX_SEPARATOR '/' | |
482 | #endif | |
483 | ||
252b5132 RH |
484 | /* This array holds the chars that only start a comment at the beginning of |
485 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
486 | .line and .file directives will appear in the pre-processed output. |
487 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 488 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
489 | #NO_APP at the beginning of its output. |
490 | Also note that comments started like this one will always work if | |
252b5132 | 491 | '/' isn't otherwise defined. */ |
b3b91714 | 492 | const char line_comment_chars[] = "#/"; |
252b5132 | 493 | |
63a0b638 | 494 | const char line_separator_chars[] = ";"; |
252b5132 | 495 | |
ce8a8b2f AM |
496 | /* Chars that can be used to separate mant from exp in floating point |
497 | nums. */ | |
252b5132 RH |
498 | const char EXP_CHARS[] = "eE"; |
499 | ||
ce8a8b2f AM |
500 | /* Chars that mean this number is a floating point constant |
501 | As in 0f12.456 | |
502 | or 0d1.2345e12. */ | |
252b5132 RH |
503 | const char FLT_CHARS[] = "fFdDxX"; |
504 | ||
ce8a8b2f | 505 | /* Tables for lexical analysis. */ |
252b5132 RH |
506 | static char mnemonic_chars[256]; |
507 | static char register_chars[256]; | |
508 | static char operand_chars[256]; | |
509 | static char identifier_chars[256]; | |
510 | static char digit_chars[256]; | |
511 | ||
ce8a8b2f | 512 | /* Lexical macros. */ |
252b5132 RH |
513 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
514 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
515 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
516 | #define is_space_char(x) ((x) == ' ') | |
517 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
518 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
519 | ||
0234cb7c | 520 | /* All non-digit non-letter characters that may occur in an operand. */ |
252b5132 RH |
521 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
522 | ||
523 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
524 | effect this we maintain a stack of saved characters that we've smashed | |
525 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 526 | assembler instruction). */ |
252b5132 | 527 | static char save_stack[32]; |
ce8a8b2f | 528 | static char *save_stack_p; |
252b5132 RH |
529 | #define END_STRING_AND_SAVE(s) \ |
530 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
531 | #define RESTORE_END_STRING(s) \ | |
532 | do { *(s) = *--save_stack_p; } while (0) | |
533 | ||
47926f60 | 534 | /* The instruction we're assembling. */ |
252b5132 RH |
535 | static i386_insn i; |
536 | ||
537 | /* Possible templates for current insn. */ | |
538 | static const templates *current_templates; | |
539 | ||
31b2323c L |
540 | /* Per instruction expressionS buffers: max displacements & immediates. */ |
541 | static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; | |
542 | static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; | |
252b5132 | 543 | |
47926f60 | 544 | /* Current operand we are working on. */ |
ee86248c | 545 | static int this_operand = -1; |
252b5132 | 546 | |
3e73aa7c JH |
547 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
548 | these. */ | |
549 | ||
550 | enum flag_code { | |
551 | CODE_32BIT, | |
552 | CODE_16BIT, | |
553 | CODE_64BIT }; | |
554 | ||
555 | static enum flag_code flag_code; | |
4fa24527 | 556 | static unsigned int object_64bit; |
862be3fb | 557 | static unsigned int disallow_64bit_reloc; |
3e73aa7c JH |
558 | static int use_rela_relocations = 0; |
559 | ||
7af8ed2d NC |
560 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
561 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ | |
562 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) | |
563 | ||
351f65ca L |
564 | /* The ELF ABI to use. */ |
565 | enum x86_elf_abi | |
566 | { | |
567 | I386_ABI, | |
7f56bc95 L |
568 | X86_64_ABI, |
569 | X86_64_X32_ABI | |
351f65ca L |
570 | }; |
571 | ||
572 | static enum x86_elf_abi x86_elf_abi = I386_ABI; | |
7af8ed2d | 573 | #endif |
351f65ca | 574 | |
167ad85b TG |
575 | #if defined (TE_PE) || defined (TE_PEP) |
576 | /* Use big object file format. */ | |
577 | static int use_big_obj = 0; | |
578 | #endif | |
579 | ||
8dcea932 L |
580 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
581 | /* 1 if generating code for a shared library. */ | |
582 | static int shared = 0; | |
583 | #endif | |
584 | ||
47926f60 KH |
585 | /* 1 for intel syntax, |
586 | 0 if att syntax. */ | |
587 | static int intel_syntax = 0; | |
252b5132 | 588 | |
e89c5eaa L |
589 | /* 1 for Intel64 ISA, |
590 | 0 if AMD64 ISA. */ | |
591 | static int intel64; | |
592 | ||
1efbbeb4 L |
593 | /* 1 for intel mnemonic, |
594 | 0 if att mnemonic. */ | |
595 | static int intel_mnemonic = !SYSV386_COMPAT; | |
596 | ||
a60de03c JB |
597 | /* 1 if pseudo registers are permitted. */ |
598 | static int allow_pseudo_reg = 0; | |
599 | ||
47926f60 KH |
600 | /* 1 if register prefix % not required. */ |
601 | static int allow_naked_reg = 0; | |
252b5132 | 602 | |
33eaf5de | 603 | /* 1 if the assembler should add BND prefix for all control-transferring |
7e8b059b L |
604 | instructions supporting it, even if this prefix wasn't specified |
605 | explicitly. */ | |
606 | static int add_bnd_prefix = 0; | |
607 | ||
ba104c83 | 608 | /* 1 if pseudo index register, eiz/riz, is allowed . */ |
db51cc60 L |
609 | static int allow_index_reg = 0; |
610 | ||
d022bddd IT |
611 | /* 1 if the assembler should ignore LOCK prefix, even if it was |
612 | specified explicitly. */ | |
613 | static int omit_lock_prefix = 0; | |
614 | ||
e4e00185 AS |
615 | /* 1 if the assembler should encode lfence, mfence, and sfence as |
616 | "lock addl $0, (%{re}sp)". */ | |
617 | static int avoid_fence = 0; | |
618 | ||
0cb4071e L |
619 | /* 1 if the assembler should generate relax relocations. */ |
620 | ||
621 | static int generate_relax_relocations | |
622 | = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS; | |
623 | ||
7bab8ab5 | 624 | static enum check_kind |
daf50ae7 | 625 | { |
7bab8ab5 JB |
626 | check_none = 0, |
627 | check_warning, | |
628 | check_error | |
daf50ae7 | 629 | } |
7bab8ab5 | 630 | sse_check, operand_check = check_warning; |
daf50ae7 | 631 | |
b6f8c7c4 L |
632 | /* Optimization: |
633 | 1. Clear the REX_W bit with register operand if possible. | |
634 | 2. Above plus use 128bit vector instruction to clear the full vector | |
635 | register. | |
636 | */ | |
637 | static int optimize = 0; | |
638 | ||
639 | /* Optimization: | |
640 | 1. Clear the REX_W bit with register operand if possible. | |
641 | 2. Above plus use 128bit vector instruction to clear the full vector | |
642 | register. | |
643 | 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to | |
644 | "testb $imm7,%r8". | |
645 | */ | |
646 | static int optimize_for_space = 0; | |
647 | ||
2ca3ace5 L |
648 | /* Register prefix used for error message. */ |
649 | static const char *register_prefix = "%"; | |
650 | ||
47926f60 KH |
651 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
652 | leave, push, and pop instructions so that gcc has the same stack | |
653 | frame as in 32 bit mode. */ | |
654 | static char stackop_size = '\0'; | |
eecb386c | 655 | |
12b55ccc L |
656 | /* Non-zero to optimize code alignment. */ |
657 | int optimize_align_code = 1; | |
658 | ||
47926f60 KH |
659 | /* Non-zero to quieten some warnings. */ |
660 | static int quiet_warnings = 0; | |
a38cf1db | 661 | |
47926f60 KH |
662 | /* CPU name. */ |
663 | static const char *cpu_arch_name = NULL; | |
6305a203 | 664 | static char *cpu_sub_arch_name = NULL; |
a38cf1db | 665 | |
47926f60 | 666 | /* CPU feature flags. */ |
40fb9820 L |
667 | static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; |
668 | ||
ccc9c027 L |
669 | /* If we have selected a cpu we are generating instructions for. */ |
670 | static int cpu_arch_tune_set = 0; | |
671 | ||
9103f4f4 | 672 | /* Cpu we are generating instructions for. */ |
fbf3f584 | 673 | enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; |
9103f4f4 L |
674 | |
675 | /* CPU feature flags of cpu we are generating instructions for. */ | |
40fb9820 | 676 | static i386_cpu_flags cpu_arch_tune_flags; |
9103f4f4 | 677 | |
ccc9c027 | 678 | /* CPU instruction set architecture used. */ |
fbf3f584 | 679 | enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; |
ccc9c027 | 680 | |
9103f4f4 | 681 | /* CPU feature flags of instruction set architecture used. */ |
fbf3f584 | 682 | i386_cpu_flags cpu_arch_isa_flags; |
9103f4f4 | 683 | |
fddf5b5b AM |
684 | /* If set, conditional jumps are not automatically promoted to handle |
685 | larger than a byte offset. */ | |
686 | static unsigned int no_cond_jump_promotion = 0; | |
687 | ||
c0f3af97 L |
688 | /* Encode SSE instructions with VEX prefix. */ |
689 | static unsigned int sse2avx; | |
690 | ||
539f890d L |
691 | /* Encode scalar AVX instructions with specific vector length. */ |
692 | static enum | |
693 | { | |
694 | vex128 = 0, | |
695 | vex256 | |
696 | } avxscalar; | |
697 | ||
03751133 L |
698 | /* Encode VEX WIG instructions with specific vex.w. */ |
699 | static enum | |
700 | { | |
701 | vexw0 = 0, | |
702 | vexw1 | |
703 | } vexwig; | |
704 | ||
43234a1e L |
705 | /* Encode scalar EVEX LIG instructions with specific vector length. */ |
706 | static enum | |
707 | { | |
708 | evexl128 = 0, | |
709 | evexl256, | |
710 | evexl512 | |
711 | } evexlig; | |
712 | ||
713 | /* Encode EVEX WIG instructions with specific evex.w. */ | |
714 | static enum | |
715 | { | |
716 | evexw0 = 0, | |
717 | evexw1 | |
718 | } evexwig; | |
719 | ||
d3d3c6db IT |
720 | /* Value to encode in EVEX RC bits, for SAE-only instructions. */ |
721 | static enum rc_type evexrcig = rne; | |
722 | ||
29b0f896 | 723 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
87c245cc | 724 | static symbolS *GOT_symbol; |
29b0f896 | 725 | |
a4447b93 RH |
726 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
727 | unsigned int x86_dwarf2_return_column; | |
728 | ||
729 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
730 | int x86_cie_data_alignment; | |
731 | ||
252b5132 | 732 | /* Interface to relax_segment. |
fddf5b5b AM |
733 | There are 3 major relax states for 386 jump insns because the |
734 | different types of jumps add different sizes to frags when we're | |
735 | figuring out what sort of jump to choose to reach a given label. */ | |
252b5132 | 736 | |
47926f60 | 737 | /* Types. */ |
93c2a809 AM |
738 | #define UNCOND_JUMP 0 |
739 | #define COND_JUMP 1 | |
740 | #define COND_JUMP86 2 | |
fddf5b5b | 741 | |
47926f60 | 742 | /* Sizes. */ |
252b5132 RH |
743 | #define CODE16 1 |
744 | #define SMALL 0 | |
29b0f896 | 745 | #define SMALL16 (SMALL | CODE16) |
252b5132 | 746 | #define BIG 2 |
29b0f896 | 747 | #define BIG16 (BIG | CODE16) |
252b5132 RH |
748 | |
749 | #ifndef INLINE | |
750 | #ifdef __GNUC__ | |
751 | #define INLINE __inline__ | |
752 | #else | |
753 | #define INLINE | |
754 | #endif | |
755 | #endif | |
756 | ||
fddf5b5b AM |
757 | #define ENCODE_RELAX_STATE(type, size) \ |
758 | ((relax_substateT) (((type) << 2) | (size))) | |
759 | #define TYPE_FROM_RELAX_STATE(s) \ | |
760 | ((s) >> 2) | |
761 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
762 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
763 | |
764 | /* This table is used by relax_frag to promote short jumps to long | |
765 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
766 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
767 | don't allow a short jump in a 32 bit code segment to be promoted to | |
768 | a 16 bit offset jump because it's slower (requires data size | |
769 | prefix), and doesn't work, unless the destination is in the bottom | |
770 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
771 | ||
772 | const relax_typeS md_relax_table[] = | |
773 | { | |
24eab124 AM |
774 | /* The fields are: |
775 | 1) most positive reach of this state, | |
776 | 2) most negative reach of this state, | |
93c2a809 | 777 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 778 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 779 | |
fddf5b5b | 780 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
781 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
782 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
783 | /* dword jmp adds 4 bytes to frag: | |
784 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 785 | {0, 0, 4, 0}, |
93c2a809 AM |
786 | /* word jmp adds 2 byte2 to frag: |
787 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
788 | {0, 0, 2, 0}, |
789 | ||
93c2a809 AM |
790 | /* COND_JUMP states. */ |
791 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
792 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
793 | /* dword conditionals adds 5 bytes to frag: | |
794 | 1 extra opcode byte, 4 displacement bytes. */ | |
795 | {0, 0, 5, 0}, | |
fddf5b5b | 796 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
797 | 1 extra opcode byte, 2 displacement bytes. */ |
798 | {0, 0, 3, 0}, | |
799 | ||
800 | /* COND_JUMP86 states. */ | |
801 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
802 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
803 | /* dword conditionals adds 5 bytes to frag: | |
804 | 1 extra opcode byte, 4 displacement bytes. */ | |
805 | {0, 0, 5, 0}, | |
806 | /* word conditionals add 4 bytes to frag: | |
807 | 1 displacement byte and a 3 byte long branch insn. */ | |
808 | {0, 0, 4, 0} | |
252b5132 RH |
809 | }; |
810 | ||
9103f4f4 L |
811 | static const arch_entry cpu_arch[] = |
812 | { | |
89507696 JB |
813 | /* Do not replace the first two entries - i386_target_format() |
814 | relies on them being there in this order. */ | |
8a2c8fef | 815 | { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32, |
293f5f65 | 816 | CPU_GENERIC32_FLAGS, 0 }, |
8a2c8fef | 817 | { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64, |
293f5f65 | 818 | CPU_GENERIC64_FLAGS, 0 }, |
8a2c8fef | 819 | { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN, |
293f5f65 | 820 | CPU_NONE_FLAGS, 0 }, |
8a2c8fef | 821 | { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN, |
293f5f65 | 822 | CPU_I186_FLAGS, 0 }, |
8a2c8fef | 823 | { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN, |
293f5f65 | 824 | CPU_I286_FLAGS, 0 }, |
8a2c8fef | 825 | { STRING_COMMA_LEN ("i386"), PROCESSOR_I386, |
293f5f65 | 826 | CPU_I386_FLAGS, 0 }, |
8a2c8fef | 827 | { STRING_COMMA_LEN ("i486"), PROCESSOR_I486, |
293f5f65 | 828 | CPU_I486_FLAGS, 0 }, |
8a2c8fef | 829 | { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM, |
293f5f65 | 830 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 831 | { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 832 | CPU_I686_FLAGS, 0 }, |
8a2c8fef | 833 | { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM, |
293f5f65 | 834 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 835 | { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 836 | CPU_PENTIUMPRO_FLAGS, 0 }, |
8a2c8fef | 837 | { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 838 | CPU_P2_FLAGS, 0 }, |
8a2c8fef | 839 | { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO, |
293f5f65 | 840 | CPU_P3_FLAGS, 0 }, |
8a2c8fef | 841 | { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4, |
293f5f65 | 842 | CPU_P4_FLAGS, 0 }, |
8a2c8fef | 843 | { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA, |
293f5f65 | 844 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 845 | { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA, |
293f5f65 | 846 | CPU_NOCONA_FLAGS, 0 }, |
8a2c8fef | 847 | { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE, |
293f5f65 | 848 | CPU_CORE_FLAGS, 1 }, |
8a2c8fef | 849 | { STRING_COMMA_LEN ("core"), PROCESSOR_CORE, |
293f5f65 | 850 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 851 | { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2, |
293f5f65 | 852 | CPU_CORE2_FLAGS, 1 }, |
8a2c8fef | 853 | { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2, |
293f5f65 | 854 | CPU_CORE2_FLAGS, 0 }, |
8a2c8fef | 855 | { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7, |
293f5f65 | 856 | CPU_COREI7_FLAGS, 0 }, |
8a2c8fef | 857 | { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM, |
293f5f65 | 858 | CPU_L1OM_FLAGS, 0 }, |
7a9068fe | 859 | { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM, |
293f5f65 | 860 | CPU_K1OM_FLAGS, 0 }, |
81486035 | 861 | { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU, |
293f5f65 | 862 | CPU_IAMCU_FLAGS, 0 }, |
8a2c8fef | 863 | { STRING_COMMA_LEN ("k6"), PROCESSOR_K6, |
293f5f65 | 864 | CPU_K6_FLAGS, 0 }, |
8a2c8fef | 865 | { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6, |
293f5f65 | 866 | CPU_K6_2_FLAGS, 0 }, |
8a2c8fef | 867 | { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON, |
293f5f65 | 868 | CPU_ATHLON_FLAGS, 0 }, |
8a2c8fef | 869 | { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8, |
293f5f65 | 870 | CPU_K8_FLAGS, 1 }, |
8a2c8fef | 871 | { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8, |
293f5f65 | 872 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 873 | { STRING_COMMA_LEN ("k8"), PROCESSOR_K8, |
293f5f65 | 874 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 875 | { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10, |
293f5f65 | 876 | CPU_AMDFAM10_FLAGS, 0 }, |
8aedb9fe | 877 | { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD, |
293f5f65 | 878 | CPU_BDVER1_FLAGS, 0 }, |
8aedb9fe | 879 | { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD, |
293f5f65 | 880 | CPU_BDVER2_FLAGS, 0 }, |
5e5c50d3 | 881 | { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD, |
293f5f65 | 882 | CPU_BDVER3_FLAGS, 0 }, |
c7b0bd56 | 883 | { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD, |
293f5f65 | 884 | CPU_BDVER4_FLAGS, 0 }, |
029f3522 | 885 | { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER, |
293f5f65 | 886 | CPU_ZNVER1_FLAGS, 0 }, |
a9660a6f AP |
887 | { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER, |
888 | CPU_ZNVER2_FLAGS, 0 }, | |
7b458c12 | 889 | { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT, |
293f5f65 | 890 | CPU_BTVER1_FLAGS, 0 }, |
7b458c12 | 891 | { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT, |
293f5f65 | 892 | CPU_BTVER2_FLAGS, 0 }, |
8a2c8fef | 893 | { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN, |
293f5f65 | 894 | CPU_8087_FLAGS, 0 }, |
8a2c8fef | 895 | { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN, |
293f5f65 | 896 | CPU_287_FLAGS, 0 }, |
8a2c8fef | 897 | { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN, |
293f5f65 | 898 | CPU_387_FLAGS, 0 }, |
1848e567 L |
899 | { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN, |
900 | CPU_687_FLAGS, 0 }, | |
d871f3f4 L |
901 | { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN, |
902 | CPU_CMOV_FLAGS, 0 }, | |
903 | { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN, | |
904 | CPU_FXSR_FLAGS, 0 }, | |
8a2c8fef | 905 | { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 906 | CPU_MMX_FLAGS, 0 }, |
8a2c8fef | 907 | { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN, |
293f5f65 | 908 | CPU_SSE_FLAGS, 0 }, |
8a2c8fef | 909 | { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN, |
293f5f65 | 910 | CPU_SSE2_FLAGS, 0 }, |
8a2c8fef | 911 | { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 912 | CPU_SSE3_FLAGS, 0 }, |
8a2c8fef | 913 | { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 914 | CPU_SSSE3_FLAGS, 0 }, |
8a2c8fef | 915 | { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN, |
293f5f65 | 916 | CPU_SSE4_1_FLAGS, 0 }, |
8a2c8fef | 917 | { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN, |
293f5f65 | 918 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 919 | { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN, |
293f5f65 | 920 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 921 | { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN, |
293f5f65 | 922 | CPU_AVX_FLAGS, 0 }, |
6c30d220 | 923 | { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN, |
293f5f65 | 924 | CPU_AVX2_FLAGS, 0 }, |
43234a1e | 925 | { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN, |
293f5f65 | 926 | CPU_AVX512F_FLAGS, 0 }, |
43234a1e | 927 | { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN, |
293f5f65 | 928 | CPU_AVX512CD_FLAGS, 0 }, |
43234a1e | 929 | { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN, |
293f5f65 | 930 | CPU_AVX512ER_FLAGS, 0 }, |
43234a1e | 931 | { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN, |
293f5f65 | 932 | CPU_AVX512PF_FLAGS, 0 }, |
1dfc6506 | 933 | { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN, |
293f5f65 | 934 | CPU_AVX512DQ_FLAGS, 0 }, |
1dfc6506 | 935 | { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN, |
293f5f65 | 936 | CPU_AVX512BW_FLAGS, 0 }, |
1dfc6506 | 937 | { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN, |
293f5f65 | 938 | CPU_AVX512VL_FLAGS, 0 }, |
8a2c8fef | 939 | { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 940 | CPU_VMX_FLAGS, 0 }, |
8729a6f6 | 941 | { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN, |
293f5f65 | 942 | CPU_VMFUNC_FLAGS, 0 }, |
8a2c8fef | 943 | { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN, |
293f5f65 | 944 | CPU_SMX_FLAGS, 0 }, |
8a2c8fef | 945 | { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN, |
293f5f65 | 946 | CPU_XSAVE_FLAGS, 0 }, |
c7b8aa3a | 947 | { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 948 | CPU_XSAVEOPT_FLAGS, 0 }, |
1dfc6506 | 949 | { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN, |
293f5f65 | 950 | CPU_XSAVEC_FLAGS, 0 }, |
1dfc6506 | 951 | { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN, |
293f5f65 | 952 | CPU_XSAVES_FLAGS, 0 }, |
8a2c8fef | 953 | { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN, |
293f5f65 | 954 | CPU_AES_FLAGS, 0 }, |
8a2c8fef | 955 | { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 956 | CPU_PCLMUL_FLAGS, 0 }, |
8a2c8fef | 957 | { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 958 | CPU_PCLMUL_FLAGS, 1 }, |
c7b8aa3a | 959 | { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN, |
293f5f65 | 960 | CPU_FSGSBASE_FLAGS, 0 }, |
c7b8aa3a | 961 | { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN, |
293f5f65 | 962 | CPU_RDRND_FLAGS, 0 }, |
c7b8aa3a | 963 | { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN, |
293f5f65 | 964 | CPU_F16C_FLAGS, 0 }, |
6c30d220 | 965 | { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN, |
293f5f65 | 966 | CPU_BMI2_FLAGS, 0 }, |
8a2c8fef | 967 | { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN, |
293f5f65 | 968 | CPU_FMA_FLAGS, 0 }, |
8a2c8fef | 969 | { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN, |
293f5f65 | 970 | CPU_FMA4_FLAGS, 0 }, |
8a2c8fef | 971 | { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN, |
293f5f65 | 972 | CPU_XOP_FLAGS, 0 }, |
8a2c8fef | 973 | { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN, |
293f5f65 | 974 | CPU_LWP_FLAGS, 0 }, |
8a2c8fef | 975 | { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN, |
293f5f65 | 976 | CPU_MOVBE_FLAGS, 0 }, |
60aa667e | 977 | { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN, |
293f5f65 | 978 | CPU_CX16_FLAGS, 0 }, |
8a2c8fef | 979 | { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN, |
293f5f65 | 980 | CPU_EPT_FLAGS, 0 }, |
6c30d220 | 981 | { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN, |
293f5f65 | 982 | CPU_LZCNT_FLAGS, 0 }, |
42164a71 | 983 | { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN, |
293f5f65 | 984 | CPU_HLE_FLAGS, 0 }, |
42164a71 | 985 | { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN, |
293f5f65 | 986 | CPU_RTM_FLAGS, 0 }, |
6c30d220 | 987 | { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN, |
293f5f65 | 988 | CPU_INVPCID_FLAGS, 0 }, |
8a2c8fef | 989 | { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN, |
293f5f65 | 990 | CPU_CLFLUSH_FLAGS, 0 }, |
22109423 | 991 | { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN, |
293f5f65 | 992 | CPU_NOP_FLAGS, 0 }, |
8a2c8fef | 993 | { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN, |
293f5f65 | 994 | CPU_SYSCALL_FLAGS, 0 }, |
8a2c8fef | 995 | { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN, |
293f5f65 | 996 | CPU_RDTSCP_FLAGS, 0 }, |
8a2c8fef | 997 | { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN, |
293f5f65 | 998 | CPU_3DNOW_FLAGS, 0 }, |
8a2c8fef | 999 | { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN, |
293f5f65 | 1000 | CPU_3DNOWA_FLAGS, 0 }, |
8a2c8fef | 1001 | { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN, |
293f5f65 | 1002 | CPU_PADLOCK_FLAGS, 0 }, |
8a2c8fef | 1003 | { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN, |
293f5f65 | 1004 | CPU_SVME_FLAGS, 1 }, |
8a2c8fef | 1005 | { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN, |
293f5f65 | 1006 | CPU_SVME_FLAGS, 0 }, |
8a2c8fef | 1007 | { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, |
293f5f65 | 1008 | CPU_SSE4A_FLAGS, 0 }, |
8a2c8fef | 1009 | { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN, |
293f5f65 | 1010 | CPU_ABM_FLAGS, 0 }, |
87973e9f | 1011 | { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 1012 | CPU_BMI_FLAGS, 0 }, |
2a2a0f38 | 1013 | { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN, |
293f5f65 | 1014 | CPU_TBM_FLAGS, 0 }, |
e2e1fcde | 1015 | { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1016 | CPU_ADX_FLAGS, 0 }, |
e2e1fcde | 1017 | { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN, |
293f5f65 | 1018 | CPU_RDSEED_FLAGS, 0 }, |
e2e1fcde | 1019 | { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN, |
293f5f65 | 1020 | CPU_PRFCHW_FLAGS, 0 }, |
5c111e37 | 1021 | { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN, |
293f5f65 | 1022 | CPU_SMAP_FLAGS, 0 }, |
7e8b059b | 1023 | { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1024 | CPU_MPX_FLAGS, 0 }, |
a0046408 | 1025 | { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN, |
293f5f65 | 1026 | CPU_SHA_FLAGS, 0 }, |
963f3586 | 1027 | { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 1028 | CPU_CLFLUSHOPT_FLAGS, 0 }, |
dcf893b5 | 1029 | { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN, |
293f5f65 | 1030 | CPU_PREFETCHWT1_FLAGS, 0 }, |
2cf200a4 | 1031 | { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN, |
293f5f65 | 1032 | CPU_SE1_FLAGS, 0 }, |
c5e7287a | 1033 | { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN, |
293f5f65 | 1034 | CPU_CLWB_FLAGS, 0 }, |
2cc1b5aa | 1035 | { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN, |
293f5f65 | 1036 | CPU_AVX512IFMA_FLAGS, 0 }, |
14f195c9 | 1037 | { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 1038 | CPU_AVX512VBMI_FLAGS, 0 }, |
920d2ddc IT |
1039 | { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN, |
1040 | CPU_AVX512_4FMAPS_FLAGS, 0 }, | |
47acf0bd IT |
1041 | { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN, |
1042 | CPU_AVX512_4VNNIW_FLAGS, 0 }, | |
620214f7 IT |
1043 | { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN, |
1044 | CPU_AVX512_VPOPCNTDQ_FLAGS, 0 }, | |
53467f57 IT |
1045 | { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN, |
1046 | CPU_AVX512_VBMI2_FLAGS, 0 }, | |
8cfcb765 IT |
1047 | { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN, |
1048 | CPU_AVX512_VNNI_FLAGS, 0 }, | |
ee6872be IT |
1049 | { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN, |
1050 | CPU_AVX512_BITALG_FLAGS, 0 }, | |
029f3522 | 1051 | { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN, |
293f5f65 | 1052 | CPU_CLZERO_FLAGS, 0 }, |
9916071f | 1053 | { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1054 | CPU_MWAITX_FLAGS, 0 }, |
8eab4136 | 1055 | { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN, |
293f5f65 | 1056 | CPU_OSPKE_FLAGS, 0 }, |
8bc52696 | 1057 | { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN, |
293f5f65 | 1058 | CPU_RDPID_FLAGS, 0 }, |
6b40c462 L |
1059 | { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN, |
1060 | CPU_PTWRITE_FLAGS, 0 }, | |
d777820b IT |
1061 | { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN, |
1062 | CPU_IBT_FLAGS, 0 }, | |
1063 | { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN, | |
1064 | CPU_SHSTK_FLAGS, 0 }, | |
48521003 IT |
1065 | { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN, |
1066 | CPU_GFNI_FLAGS, 0 }, | |
8dcf1fad IT |
1067 | { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN, |
1068 | CPU_VAES_FLAGS, 0 }, | |
ff1982d5 IT |
1069 | { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN, |
1070 | CPU_VPCLMULQDQ_FLAGS, 0 }, | |
3233d7d0 IT |
1071 | { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN, |
1072 | CPU_WBNOINVD_FLAGS, 0 }, | |
be3a8dca IT |
1073 | { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN, |
1074 | CPU_PCONFIG_FLAGS, 0 }, | |
de89d0a3 IT |
1075 | { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN, |
1076 | CPU_WAITPKG_FLAGS, 0 }, | |
c48935d7 IT |
1077 | { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN, |
1078 | CPU_CLDEMOTE_FLAGS, 0 }, | |
c0a30a9f L |
1079 | { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN, |
1080 | CPU_MOVDIRI_FLAGS, 0 }, | |
1081 | { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN, | |
1082 | CPU_MOVDIR64B_FLAGS, 0 }, | |
293f5f65 L |
1083 | }; |
1084 | ||
1085 | static const noarch_entry cpu_noarch[] = | |
1086 | { | |
1087 | { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS }, | |
1848e567 L |
1088 | { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS }, |
1089 | { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS }, | |
1090 | { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS }, | |
d871f3f4 L |
1091 | { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS }, |
1092 | { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS }, | |
293f5f65 L |
1093 | { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS }, |
1094 | { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS }, | |
1848e567 L |
1095 | { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS }, |
1096 | { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS }, | |
1097 | { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS }, | |
1098 | { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS }, | |
1099 | { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS }, | |
1100 | { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS }, | |
293f5f65 | 1101 | { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS }, |
1848e567 | 1102 | { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS }, |
144b71e2 L |
1103 | { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS }, |
1104 | { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS }, | |
1105 | { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS }, | |
1106 | { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS }, | |
1107 | { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS }, | |
1108 | { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS }, | |
1109 | { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS }, | |
1110 | { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS }, | |
1111 | { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS }, | |
920d2ddc | 1112 | { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS }, |
47acf0bd | 1113 | { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS }, |
620214f7 | 1114 | { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS }, |
53467f57 | 1115 | { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS }, |
8cfcb765 | 1116 | { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS }, |
ee6872be | 1117 | { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS }, |
d777820b IT |
1118 | { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS }, |
1119 | { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS }, | |
c0a30a9f L |
1120 | { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS }, |
1121 | { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS }, | |
e413e4e9 AM |
1122 | }; |
1123 | ||
704209c0 | 1124 | #ifdef I386COFF |
a6c24e68 NC |
1125 | /* Like s_lcomm_internal in gas/read.c but the alignment string |
1126 | is allowed to be optional. */ | |
1127 | ||
1128 | static symbolS * | |
1129 | pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size) | |
1130 | { | |
1131 | addressT align = 0; | |
1132 | ||
1133 | SKIP_WHITESPACE (); | |
1134 | ||
7ab9ffdd | 1135 | if (needs_align |
a6c24e68 NC |
1136 | && *input_line_pointer == ',') |
1137 | { | |
1138 | align = parse_align (needs_align - 1); | |
7ab9ffdd | 1139 | |
a6c24e68 NC |
1140 | if (align == (addressT) -1) |
1141 | return NULL; | |
1142 | } | |
1143 | else | |
1144 | { | |
1145 | if (size >= 8) | |
1146 | align = 3; | |
1147 | else if (size >= 4) | |
1148 | align = 2; | |
1149 | else if (size >= 2) | |
1150 | align = 1; | |
1151 | else | |
1152 | align = 0; | |
1153 | } | |
1154 | ||
1155 | bss_alloc (symbolP, size, align); | |
1156 | return symbolP; | |
1157 | } | |
1158 | ||
704209c0 | 1159 | static void |
a6c24e68 NC |
1160 | pe_lcomm (int needs_align) |
1161 | { | |
1162 | s_comm_internal (needs_align * 2, pe_lcomm_internal); | |
1163 | } | |
704209c0 | 1164 | #endif |
a6c24e68 | 1165 | |
29b0f896 AM |
1166 | const pseudo_typeS md_pseudo_table[] = |
1167 | { | |
1168 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) | |
1169 | {"align", s_align_bytes, 0}, | |
1170 | #else | |
1171 | {"align", s_align_ptwo, 0}, | |
1172 | #endif | |
1173 | {"arch", set_cpu_arch, 0}, | |
1174 | #ifndef I386COFF | |
1175 | {"bss", s_bss, 0}, | |
a6c24e68 NC |
1176 | #else |
1177 | {"lcomm", pe_lcomm, 1}, | |
29b0f896 AM |
1178 | #endif |
1179 | {"ffloat", float_cons, 'f'}, | |
1180 | {"dfloat", float_cons, 'd'}, | |
1181 | {"tfloat", float_cons, 'x'}, | |
1182 | {"value", cons, 2}, | |
d182319b | 1183 | {"slong", signed_cons, 4}, |
29b0f896 AM |
1184 | {"noopt", s_ignore, 0}, |
1185 | {"optim", s_ignore, 0}, | |
1186 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, | |
1187 | {"code16", set_code_flag, CODE_16BIT}, | |
1188 | {"code32", set_code_flag, CODE_32BIT}, | |
da5f19a2 | 1189 | #ifdef BFD64 |
29b0f896 | 1190 | {"code64", set_code_flag, CODE_64BIT}, |
da5f19a2 | 1191 | #endif |
29b0f896 AM |
1192 | {"intel_syntax", set_intel_syntax, 1}, |
1193 | {"att_syntax", set_intel_syntax, 0}, | |
1efbbeb4 L |
1194 | {"intel_mnemonic", set_intel_mnemonic, 1}, |
1195 | {"att_mnemonic", set_intel_mnemonic, 0}, | |
db51cc60 L |
1196 | {"allow_index_reg", set_allow_index_reg, 1}, |
1197 | {"disallow_index_reg", set_allow_index_reg, 0}, | |
7bab8ab5 JB |
1198 | {"sse_check", set_check, 0}, |
1199 | {"operand_check", set_check, 1}, | |
3b22753a L |
1200 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
1201 | {"largecomm", handle_large_common, 0}, | |
07a53e5c | 1202 | #else |
68d20676 | 1203 | {"file", dwarf2_directive_file, 0}, |
07a53e5c RH |
1204 | {"loc", dwarf2_directive_loc, 0}, |
1205 | {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, | |
3b22753a | 1206 | #endif |
6482c264 NC |
1207 | #ifdef TE_PE |
1208 | {"secrel32", pe_directive_secrel, 0}, | |
1209 | #endif | |
29b0f896 AM |
1210 | {0, 0, 0} |
1211 | }; | |
1212 | ||
1213 | /* For interface with expression (). */ | |
1214 | extern char *input_line_pointer; | |
1215 | ||
1216 | /* Hash table for instruction mnemonic lookup. */ | |
1217 | static struct hash_control *op_hash; | |
1218 | ||
1219 | /* Hash table for register lookup. */ | |
1220 | static struct hash_control *reg_hash; | |
1221 | \f | |
ce8a8b2f AM |
1222 | /* Various efficient no-op patterns for aligning code labels. |
1223 | Note: Don't try to assemble the instructions in the comments. | |
1224 | 0L and 0w are not legal. */ | |
62a02d25 L |
1225 | static const unsigned char f32_1[] = |
1226 | {0x90}; /* nop */ | |
1227 | static const unsigned char f32_2[] = | |
1228 | {0x66,0x90}; /* xchg %ax,%ax */ | |
1229 | static const unsigned char f32_3[] = | |
1230 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
1231 | static const unsigned char f32_4[] = | |
1232 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
62a02d25 L |
1233 | static const unsigned char f32_6[] = |
1234 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
1235 | static const unsigned char f32_7[] = | |
1236 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
62a02d25 | 1237 | static const unsigned char f16_3[] = |
3ae729d5 | 1238 | {0x8d,0x74,0x00}; /* lea 0(%si),%si */ |
62a02d25 | 1239 | static const unsigned char f16_4[] = |
3ae729d5 L |
1240 | {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */ |
1241 | static const unsigned char jump_disp8[] = | |
1242 | {0xeb}; /* jmp disp8 */ | |
1243 | static const unsigned char jump32_disp32[] = | |
1244 | {0xe9}; /* jmp disp32 */ | |
1245 | static const unsigned char jump16_disp32[] = | |
1246 | {0x66,0xe9}; /* jmp disp32 */ | |
62a02d25 L |
1247 | /* 32-bit NOPs patterns. */ |
1248 | static const unsigned char *const f32_patt[] = { | |
3ae729d5 | 1249 | f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7 |
62a02d25 L |
1250 | }; |
1251 | /* 16-bit NOPs patterns. */ | |
1252 | static const unsigned char *const f16_patt[] = { | |
3ae729d5 | 1253 | f32_1, f32_2, f16_3, f16_4 |
62a02d25 L |
1254 | }; |
1255 | /* nopl (%[re]ax) */ | |
1256 | static const unsigned char alt_3[] = | |
1257 | {0x0f,0x1f,0x00}; | |
1258 | /* nopl 0(%[re]ax) */ | |
1259 | static const unsigned char alt_4[] = | |
1260 | {0x0f,0x1f,0x40,0x00}; | |
1261 | /* nopl 0(%[re]ax,%[re]ax,1) */ | |
1262 | static const unsigned char alt_5[] = | |
1263 | {0x0f,0x1f,0x44,0x00,0x00}; | |
1264 | /* nopw 0(%[re]ax,%[re]ax,1) */ | |
1265 | static const unsigned char alt_6[] = | |
1266 | {0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
1267 | /* nopl 0L(%[re]ax) */ | |
1268 | static const unsigned char alt_7[] = | |
1269 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
1270 | /* nopl 0L(%[re]ax,%[re]ax,1) */ | |
1271 | static const unsigned char alt_8[] = | |
1272 | {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1273 | /* nopw 0L(%[re]ax,%[re]ax,1) */ | |
1274 | static const unsigned char alt_9[] = | |
1275 | {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1276 | /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
1277 | static const unsigned char alt_10[] = | |
1278 | {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
3ae729d5 L |
1279 | /* data16 nopw %cs:0L(%eax,%eax,1) */ |
1280 | static const unsigned char alt_11[] = | |
1281 | {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
62a02d25 L |
1282 | /* 32-bit and 64-bit NOPs patterns. */ |
1283 | static const unsigned char *const alt_patt[] = { | |
1284 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
3ae729d5 | 1285 | alt_9, alt_10, alt_11 |
62a02d25 L |
1286 | }; |
1287 | ||
1288 | /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum | |
1289 | size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */ | |
1290 | ||
1291 | static void | |
1292 | i386_output_nops (char *where, const unsigned char *const *patt, | |
1293 | int count, int max_single_nop_size) | |
1294 | ||
1295 | { | |
3ae729d5 L |
1296 | /* Place the longer NOP first. */ |
1297 | int last; | |
1298 | int offset; | |
1299 | const unsigned char *nops = patt[max_single_nop_size - 1]; | |
1300 | ||
1301 | /* Use the smaller one if the requsted one isn't available. */ | |
1302 | if (nops == NULL) | |
62a02d25 | 1303 | { |
3ae729d5 L |
1304 | max_single_nop_size--; |
1305 | nops = patt[max_single_nop_size - 1]; | |
62a02d25 L |
1306 | } |
1307 | ||
3ae729d5 L |
1308 | last = count % max_single_nop_size; |
1309 | ||
1310 | count -= last; | |
1311 | for (offset = 0; offset < count; offset += max_single_nop_size) | |
1312 | memcpy (where + offset, nops, max_single_nop_size); | |
1313 | ||
1314 | if (last) | |
1315 | { | |
1316 | nops = patt[last - 1]; | |
1317 | if (nops == NULL) | |
1318 | { | |
1319 | /* Use the smaller one plus one-byte NOP if the needed one | |
1320 | isn't available. */ | |
1321 | last--; | |
1322 | nops = patt[last - 1]; | |
1323 | memcpy (where + offset, nops, last); | |
1324 | where[offset + last] = *patt[0]; | |
1325 | } | |
1326 | else | |
1327 | memcpy (where + offset, nops, last); | |
1328 | } | |
62a02d25 L |
1329 | } |
1330 | ||
3ae729d5 L |
1331 | static INLINE int |
1332 | fits_in_imm7 (offsetT num) | |
1333 | { | |
1334 | return (num & 0x7f) == num; | |
1335 | } | |
1336 | ||
1337 | static INLINE int | |
1338 | fits_in_imm31 (offsetT num) | |
1339 | { | |
1340 | return (num & 0x7fffffff) == num; | |
1341 | } | |
62a02d25 L |
1342 | |
1343 | /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a | |
1344 | single NOP instruction LIMIT. */ | |
1345 | ||
1346 | void | |
3ae729d5 | 1347 | i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit) |
62a02d25 | 1348 | { |
3ae729d5 | 1349 | const unsigned char *const *patt = NULL; |
62a02d25 | 1350 | int max_single_nop_size; |
3ae729d5 L |
1351 | /* Maximum number of NOPs before switching to jump over NOPs. */ |
1352 | int max_number_of_nops; | |
62a02d25 | 1353 | |
3ae729d5 | 1354 | switch (fragP->fr_type) |
62a02d25 | 1355 | { |
3ae729d5 L |
1356 | case rs_fill_nop: |
1357 | case rs_align_code: | |
1358 | break; | |
1359 | default: | |
62a02d25 L |
1360 | return; |
1361 | } | |
1362 | ||
ccc9c027 L |
1363 | /* We need to decide which NOP sequence to use for 32bit and |
1364 | 64bit. When -mtune= is used: | |
4eed87de | 1365 | |
76bc74dc L |
1366 | 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and |
1367 | PROCESSOR_GENERIC32, f32_patt will be used. | |
80b8656c L |
1368 | 2. For the rest, alt_patt will be used. |
1369 | ||
1370 | When -mtune= isn't used, alt_patt will be used if | |
22109423 | 1371 | cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will |
76bc74dc | 1372 | be used. |
ccc9c027 L |
1373 | |
1374 | When -march= or .arch is used, we can't use anything beyond | |
1375 | cpu_arch_isa_flags. */ | |
1376 | ||
1377 | if (flag_code == CODE_16BIT) | |
1378 | { | |
3ae729d5 L |
1379 | patt = f16_patt; |
1380 | max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]); | |
1381 | /* Limit number of NOPs to 2 in 16-bit mode. */ | |
1382 | max_number_of_nops = 2; | |
252b5132 | 1383 | } |
33fef721 | 1384 | else |
ccc9c027 | 1385 | { |
fbf3f584 | 1386 | if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN) |
ccc9c027 L |
1387 | { |
1388 | /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ | |
1389 | switch (cpu_arch_tune) | |
1390 | { | |
1391 | case PROCESSOR_UNKNOWN: | |
1392 | /* We use cpu_arch_isa_flags to check if we SHOULD | |
22109423 L |
1393 | optimize with nops. */ |
1394 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1395 | patt = alt_patt; |
ccc9c027 L |
1396 | else |
1397 | patt = f32_patt; | |
1398 | break; | |
ccc9c027 L |
1399 | case PROCESSOR_PENTIUM4: |
1400 | case PROCESSOR_NOCONA: | |
ef05d495 | 1401 | case PROCESSOR_CORE: |
76bc74dc | 1402 | case PROCESSOR_CORE2: |
bd5295b2 | 1403 | case PROCESSOR_COREI7: |
3632d14b | 1404 | case PROCESSOR_L1OM: |
7a9068fe | 1405 | case PROCESSOR_K1OM: |
76bc74dc | 1406 | case PROCESSOR_GENERIC64: |
ccc9c027 L |
1407 | case PROCESSOR_K6: |
1408 | case PROCESSOR_ATHLON: | |
1409 | case PROCESSOR_K8: | |
4eed87de | 1410 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1411 | case PROCESSOR_BD: |
029f3522 | 1412 | case PROCESSOR_ZNVER: |
7b458c12 | 1413 | case PROCESSOR_BT: |
80b8656c | 1414 | patt = alt_patt; |
ccc9c027 | 1415 | break; |
76bc74dc | 1416 | case PROCESSOR_I386: |
ccc9c027 L |
1417 | case PROCESSOR_I486: |
1418 | case PROCESSOR_PENTIUM: | |
2dde1948 | 1419 | case PROCESSOR_PENTIUMPRO: |
81486035 | 1420 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1421 | case PROCESSOR_GENERIC32: |
1422 | patt = f32_patt; | |
1423 | break; | |
4eed87de | 1424 | } |
ccc9c027 L |
1425 | } |
1426 | else | |
1427 | { | |
fbf3f584 | 1428 | switch (fragP->tc_frag_data.tune) |
ccc9c027 L |
1429 | { |
1430 | case PROCESSOR_UNKNOWN: | |
e6a14101 | 1431 | /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be |
ccc9c027 L |
1432 | PROCESSOR_UNKNOWN. */ |
1433 | abort (); | |
1434 | break; | |
1435 | ||
76bc74dc | 1436 | case PROCESSOR_I386: |
ccc9c027 L |
1437 | case PROCESSOR_I486: |
1438 | case PROCESSOR_PENTIUM: | |
81486035 | 1439 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1440 | case PROCESSOR_K6: |
1441 | case PROCESSOR_ATHLON: | |
1442 | case PROCESSOR_K8: | |
4eed87de | 1443 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1444 | case PROCESSOR_BD: |
029f3522 | 1445 | case PROCESSOR_ZNVER: |
7b458c12 | 1446 | case PROCESSOR_BT: |
ccc9c027 L |
1447 | case PROCESSOR_GENERIC32: |
1448 | /* We use cpu_arch_isa_flags to check if we CAN optimize | |
22109423 L |
1449 | with nops. */ |
1450 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1451 | patt = alt_patt; |
ccc9c027 L |
1452 | else |
1453 | patt = f32_patt; | |
1454 | break; | |
76bc74dc L |
1455 | case PROCESSOR_PENTIUMPRO: |
1456 | case PROCESSOR_PENTIUM4: | |
1457 | case PROCESSOR_NOCONA: | |
1458 | case PROCESSOR_CORE: | |
ef05d495 | 1459 | case PROCESSOR_CORE2: |
bd5295b2 | 1460 | case PROCESSOR_COREI7: |
3632d14b | 1461 | case PROCESSOR_L1OM: |
7a9068fe | 1462 | case PROCESSOR_K1OM: |
22109423 | 1463 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) |
80b8656c | 1464 | patt = alt_patt; |
ccc9c027 L |
1465 | else |
1466 | patt = f32_patt; | |
1467 | break; | |
1468 | case PROCESSOR_GENERIC64: | |
80b8656c | 1469 | patt = alt_patt; |
ccc9c027 | 1470 | break; |
4eed87de | 1471 | } |
ccc9c027 L |
1472 | } |
1473 | ||
76bc74dc L |
1474 | if (patt == f32_patt) |
1475 | { | |
3ae729d5 L |
1476 | max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]); |
1477 | /* Limit number of NOPs to 2 for older processors. */ | |
1478 | max_number_of_nops = 2; | |
76bc74dc L |
1479 | } |
1480 | else | |
1481 | { | |
3ae729d5 L |
1482 | max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]); |
1483 | /* Limit number of NOPs to 7 for newer processors. */ | |
1484 | max_number_of_nops = 7; | |
1485 | } | |
1486 | } | |
1487 | ||
1488 | if (limit == 0) | |
1489 | limit = max_single_nop_size; | |
1490 | ||
1491 | if (fragP->fr_type == rs_fill_nop) | |
1492 | { | |
1493 | /* Output NOPs for .nop directive. */ | |
1494 | if (limit > max_single_nop_size) | |
1495 | { | |
1496 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1497 | _("invalid single nop size: %d " | |
1498 | "(expect within [0, %d])"), | |
1499 | limit, max_single_nop_size); | |
1500 | return; | |
1501 | } | |
1502 | } | |
1503 | else | |
1504 | fragP->fr_var = count; | |
1505 | ||
1506 | if ((count / max_single_nop_size) > max_number_of_nops) | |
1507 | { | |
1508 | /* Generate jump over NOPs. */ | |
1509 | offsetT disp = count - 2; | |
1510 | if (fits_in_imm7 (disp)) | |
1511 | { | |
1512 | /* Use "jmp disp8" if possible. */ | |
1513 | count = disp; | |
1514 | where[0] = jump_disp8[0]; | |
1515 | where[1] = count; | |
1516 | where += 2; | |
1517 | } | |
1518 | else | |
1519 | { | |
1520 | unsigned int size_of_jump; | |
1521 | ||
1522 | if (flag_code == CODE_16BIT) | |
1523 | { | |
1524 | where[0] = jump16_disp32[0]; | |
1525 | where[1] = jump16_disp32[1]; | |
1526 | size_of_jump = 2; | |
1527 | } | |
1528 | else | |
1529 | { | |
1530 | where[0] = jump32_disp32[0]; | |
1531 | size_of_jump = 1; | |
1532 | } | |
1533 | ||
1534 | count -= size_of_jump + 4; | |
1535 | if (!fits_in_imm31 (count)) | |
1536 | { | |
1537 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1538 | _("jump over nop padding out of range")); | |
1539 | return; | |
1540 | } | |
1541 | ||
1542 | md_number_to_chars (where + size_of_jump, count, 4); | |
1543 | where += size_of_jump + 4; | |
76bc74dc | 1544 | } |
ccc9c027 | 1545 | } |
3ae729d5 L |
1546 | |
1547 | /* Generate multiple NOPs. */ | |
1548 | i386_output_nops (where, patt, count, limit); | |
252b5132 RH |
1549 | } |
1550 | ||
c6fb90c8 | 1551 | static INLINE int |
0dfbf9d7 | 1552 | operand_type_all_zero (const union i386_operand_type *x) |
40fb9820 | 1553 | { |
0dfbf9d7 | 1554 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1555 | { |
1556 | case 3: | |
0dfbf9d7 | 1557 | if (x->array[2]) |
c6fb90c8 | 1558 | return 0; |
1a0670f3 | 1559 | /* Fall through. */ |
c6fb90c8 | 1560 | case 2: |
0dfbf9d7 | 1561 | if (x->array[1]) |
c6fb90c8 | 1562 | return 0; |
1a0670f3 | 1563 | /* Fall through. */ |
c6fb90c8 | 1564 | case 1: |
0dfbf9d7 | 1565 | return !x->array[0]; |
c6fb90c8 L |
1566 | default: |
1567 | abort (); | |
1568 | } | |
40fb9820 L |
1569 | } |
1570 | ||
c6fb90c8 | 1571 | static INLINE void |
0dfbf9d7 | 1572 | operand_type_set (union i386_operand_type *x, unsigned int v) |
40fb9820 | 1573 | { |
0dfbf9d7 | 1574 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1575 | { |
1576 | case 3: | |
0dfbf9d7 | 1577 | x->array[2] = v; |
1a0670f3 | 1578 | /* Fall through. */ |
c6fb90c8 | 1579 | case 2: |
0dfbf9d7 | 1580 | x->array[1] = v; |
1a0670f3 | 1581 | /* Fall through. */ |
c6fb90c8 | 1582 | case 1: |
0dfbf9d7 | 1583 | x->array[0] = v; |
1a0670f3 | 1584 | /* Fall through. */ |
c6fb90c8 L |
1585 | break; |
1586 | default: | |
1587 | abort (); | |
1588 | } | |
1589 | } | |
40fb9820 | 1590 | |
c6fb90c8 | 1591 | static INLINE int |
0dfbf9d7 L |
1592 | operand_type_equal (const union i386_operand_type *x, |
1593 | const union i386_operand_type *y) | |
c6fb90c8 | 1594 | { |
0dfbf9d7 | 1595 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1596 | { |
1597 | case 3: | |
0dfbf9d7 | 1598 | if (x->array[2] != y->array[2]) |
c6fb90c8 | 1599 | return 0; |
1a0670f3 | 1600 | /* Fall through. */ |
c6fb90c8 | 1601 | case 2: |
0dfbf9d7 | 1602 | if (x->array[1] != y->array[1]) |
c6fb90c8 | 1603 | return 0; |
1a0670f3 | 1604 | /* Fall through. */ |
c6fb90c8 | 1605 | case 1: |
0dfbf9d7 | 1606 | return x->array[0] == y->array[0]; |
c6fb90c8 L |
1607 | break; |
1608 | default: | |
1609 | abort (); | |
1610 | } | |
1611 | } | |
40fb9820 | 1612 | |
0dfbf9d7 L |
1613 | static INLINE int |
1614 | cpu_flags_all_zero (const union i386_cpu_flags *x) | |
1615 | { | |
1616 | switch (ARRAY_SIZE(x->array)) | |
1617 | { | |
53467f57 IT |
1618 | case 4: |
1619 | if (x->array[3]) | |
1620 | return 0; | |
1621 | /* Fall through. */ | |
0dfbf9d7 L |
1622 | case 3: |
1623 | if (x->array[2]) | |
1624 | return 0; | |
1a0670f3 | 1625 | /* Fall through. */ |
0dfbf9d7 L |
1626 | case 2: |
1627 | if (x->array[1]) | |
1628 | return 0; | |
1a0670f3 | 1629 | /* Fall through. */ |
0dfbf9d7 L |
1630 | case 1: |
1631 | return !x->array[0]; | |
1632 | default: | |
1633 | abort (); | |
1634 | } | |
1635 | } | |
1636 | ||
0dfbf9d7 L |
1637 | static INLINE int |
1638 | cpu_flags_equal (const union i386_cpu_flags *x, | |
1639 | const union i386_cpu_flags *y) | |
1640 | { | |
1641 | switch (ARRAY_SIZE(x->array)) | |
1642 | { | |
53467f57 IT |
1643 | case 4: |
1644 | if (x->array[3] != y->array[3]) | |
1645 | return 0; | |
1646 | /* Fall through. */ | |
0dfbf9d7 L |
1647 | case 3: |
1648 | if (x->array[2] != y->array[2]) | |
1649 | return 0; | |
1a0670f3 | 1650 | /* Fall through. */ |
0dfbf9d7 L |
1651 | case 2: |
1652 | if (x->array[1] != y->array[1]) | |
1653 | return 0; | |
1a0670f3 | 1654 | /* Fall through. */ |
0dfbf9d7 L |
1655 | case 1: |
1656 | return x->array[0] == y->array[0]; | |
1657 | break; | |
1658 | default: | |
1659 | abort (); | |
1660 | } | |
1661 | } | |
c6fb90c8 L |
1662 | |
1663 | static INLINE int | |
1664 | cpu_flags_check_cpu64 (i386_cpu_flags f) | |
1665 | { | |
1666 | return !((flag_code == CODE_64BIT && f.bitfield.cpuno64) | |
1667 | || (flag_code != CODE_64BIT && f.bitfield.cpu64)); | |
40fb9820 L |
1668 | } |
1669 | ||
c6fb90c8 L |
1670 | static INLINE i386_cpu_flags |
1671 | cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1672 | { |
c6fb90c8 L |
1673 | switch (ARRAY_SIZE (x.array)) |
1674 | { | |
53467f57 IT |
1675 | case 4: |
1676 | x.array [3] &= y.array [3]; | |
1677 | /* Fall through. */ | |
c6fb90c8 L |
1678 | case 3: |
1679 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1680 | /* Fall through. */ |
c6fb90c8 L |
1681 | case 2: |
1682 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1683 | /* Fall through. */ |
c6fb90c8 L |
1684 | case 1: |
1685 | x.array [0] &= y.array [0]; | |
1686 | break; | |
1687 | default: | |
1688 | abort (); | |
1689 | } | |
1690 | return x; | |
1691 | } | |
40fb9820 | 1692 | |
c6fb90c8 L |
1693 | static INLINE i386_cpu_flags |
1694 | cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1695 | { |
c6fb90c8 | 1696 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1697 | { |
53467f57 IT |
1698 | case 4: |
1699 | x.array [3] |= y.array [3]; | |
1700 | /* Fall through. */ | |
c6fb90c8 L |
1701 | case 3: |
1702 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1703 | /* Fall through. */ |
c6fb90c8 L |
1704 | case 2: |
1705 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1706 | /* Fall through. */ |
c6fb90c8 L |
1707 | case 1: |
1708 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1709 | break; |
1710 | default: | |
1711 | abort (); | |
1712 | } | |
40fb9820 L |
1713 | return x; |
1714 | } | |
1715 | ||
309d3373 JB |
1716 | static INLINE i386_cpu_flags |
1717 | cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y) | |
1718 | { | |
1719 | switch (ARRAY_SIZE (x.array)) | |
1720 | { | |
53467f57 IT |
1721 | case 4: |
1722 | x.array [3] &= ~y.array [3]; | |
1723 | /* Fall through. */ | |
309d3373 JB |
1724 | case 3: |
1725 | x.array [2] &= ~y.array [2]; | |
1a0670f3 | 1726 | /* Fall through. */ |
309d3373 JB |
1727 | case 2: |
1728 | x.array [1] &= ~y.array [1]; | |
1a0670f3 | 1729 | /* Fall through. */ |
309d3373 JB |
1730 | case 1: |
1731 | x.array [0] &= ~y.array [0]; | |
1732 | break; | |
1733 | default: | |
1734 | abort (); | |
1735 | } | |
1736 | return x; | |
1737 | } | |
1738 | ||
c0f3af97 L |
1739 | #define CPU_FLAGS_ARCH_MATCH 0x1 |
1740 | #define CPU_FLAGS_64BIT_MATCH 0x2 | |
1741 | ||
c0f3af97 | 1742 | #define CPU_FLAGS_PERFECT_MATCH \ |
db12e14e | 1743 | (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH) |
c0f3af97 L |
1744 | |
1745 | /* Return CPU flags match bits. */ | |
3629bb00 | 1746 | |
40fb9820 | 1747 | static int |
d3ce72d0 | 1748 | cpu_flags_match (const insn_template *t) |
40fb9820 | 1749 | { |
c0f3af97 L |
1750 | i386_cpu_flags x = t->cpu_flags; |
1751 | int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0; | |
40fb9820 L |
1752 | |
1753 | x.bitfield.cpu64 = 0; | |
1754 | x.bitfield.cpuno64 = 0; | |
1755 | ||
0dfbf9d7 | 1756 | if (cpu_flags_all_zero (&x)) |
c0f3af97 L |
1757 | { |
1758 | /* This instruction is available on all archs. */ | |
db12e14e | 1759 | match |= CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1760 | } |
3629bb00 L |
1761 | else |
1762 | { | |
c0f3af97 | 1763 | /* This instruction is available only on some archs. */ |
3629bb00 L |
1764 | i386_cpu_flags cpu = cpu_arch_flags; |
1765 | ||
ab592e75 JB |
1766 | /* AVX512VL is no standalone feature - match it and then strip it. */ |
1767 | if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl) | |
1768 | return match; | |
1769 | x.bitfield.cpuavx512vl = 0; | |
1770 | ||
3629bb00 | 1771 | cpu = cpu_flags_and (x, cpu); |
c0f3af97 L |
1772 | if (!cpu_flags_all_zero (&cpu)) |
1773 | { | |
a5ff0eb2 L |
1774 | if (x.bitfield.cpuavx) |
1775 | { | |
929f69fa | 1776 | /* We need to check a few extra flags with AVX. */ |
b9d49817 JB |
1777 | if (cpu.bitfield.cpuavx |
1778 | && (!t->opcode_modifier.sse2avx || sse2avx) | |
1779 | && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes) | |
929f69fa | 1780 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) |
b9d49817 JB |
1781 | && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul)) |
1782 | match |= CPU_FLAGS_ARCH_MATCH; | |
a5ff0eb2 | 1783 | } |
929f69fa JB |
1784 | else if (x.bitfield.cpuavx512f) |
1785 | { | |
1786 | /* We need to check a few extra flags with AVX512F. */ | |
1787 | if (cpu.bitfield.cpuavx512f | |
1788 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) | |
1789 | && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes) | |
1790 | && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq)) | |
1791 | match |= CPU_FLAGS_ARCH_MATCH; | |
1792 | } | |
a5ff0eb2 | 1793 | else |
db12e14e | 1794 | match |= CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1795 | } |
3629bb00 | 1796 | } |
c0f3af97 | 1797 | return match; |
40fb9820 L |
1798 | } |
1799 | ||
c6fb90c8 L |
1800 | static INLINE i386_operand_type |
1801 | operand_type_and (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1802 | { |
c6fb90c8 L |
1803 | switch (ARRAY_SIZE (x.array)) |
1804 | { | |
1805 | case 3: | |
1806 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1807 | /* Fall through. */ |
c6fb90c8 L |
1808 | case 2: |
1809 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1810 | /* Fall through. */ |
c6fb90c8 L |
1811 | case 1: |
1812 | x.array [0] &= y.array [0]; | |
1813 | break; | |
1814 | default: | |
1815 | abort (); | |
1816 | } | |
1817 | return x; | |
40fb9820 L |
1818 | } |
1819 | ||
73053c1f JB |
1820 | static INLINE i386_operand_type |
1821 | operand_type_and_not (i386_operand_type x, i386_operand_type y) | |
1822 | { | |
1823 | switch (ARRAY_SIZE (x.array)) | |
1824 | { | |
1825 | case 3: | |
1826 | x.array [2] &= ~y.array [2]; | |
1827 | /* Fall through. */ | |
1828 | case 2: | |
1829 | x.array [1] &= ~y.array [1]; | |
1830 | /* Fall through. */ | |
1831 | case 1: | |
1832 | x.array [0] &= ~y.array [0]; | |
1833 | break; | |
1834 | default: | |
1835 | abort (); | |
1836 | } | |
1837 | return x; | |
1838 | } | |
1839 | ||
c6fb90c8 L |
1840 | static INLINE i386_operand_type |
1841 | operand_type_or (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1842 | { |
c6fb90c8 | 1843 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1844 | { |
c6fb90c8 L |
1845 | case 3: |
1846 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1847 | /* Fall through. */ |
c6fb90c8 L |
1848 | case 2: |
1849 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1850 | /* Fall through. */ |
c6fb90c8 L |
1851 | case 1: |
1852 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1853 | break; |
1854 | default: | |
1855 | abort (); | |
1856 | } | |
c6fb90c8 L |
1857 | return x; |
1858 | } | |
40fb9820 | 1859 | |
c6fb90c8 L |
1860 | static INLINE i386_operand_type |
1861 | operand_type_xor (i386_operand_type x, i386_operand_type y) | |
1862 | { | |
1863 | switch (ARRAY_SIZE (x.array)) | |
1864 | { | |
1865 | case 3: | |
1866 | x.array [2] ^= y.array [2]; | |
1a0670f3 | 1867 | /* Fall through. */ |
c6fb90c8 L |
1868 | case 2: |
1869 | x.array [1] ^= y.array [1]; | |
1a0670f3 | 1870 | /* Fall through. */ |
c6fb90c8 L |
1871 | case 1: |
1872 | x.array [0] ^= y.array [0]; | |
1873 | break; | |
1874 | default: | |
1875 | abort (); | |
1876 | } | |
40fb9820 L |
1877 | return x; |
1878 | } | |
1879 | ||
1880 | static const i386_operand_type acc32 = OPERAND_TYPE_ACC32; | |
1881 | static const i386_operand_type acc64 = OPERAND_TYPE_ACC64; | |
40fb9820 L |
1882 | static const i386_operand_type disp16 = OPERAND_TYPE_DISP16; |
1883 | static const i386_operand_type disp32 = OPERAND_TYPE_DISP32; | |
1884 | static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S; | |
1885 | static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32; | |
1886 | static const i386_operand_type anydisp | |
1887 | = OPERAND_TYPE_ANYDISP; | |
40fb9820 | 1888 | static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM; |
43234a1e | 1889 | static const i386_operand_type regmask = OPERAND_TYPE_REGMASK; |
40fb9820 L |
1890 | static const i386_operand_type imm8 = OPERAND_TYPE_IMM8; |
1891 | static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S; | |
1892 | static const i386_operand_type imm16 = OPERAND_TYPE_IMM16; | |
1893 | static const i386_operand_type imm32 = OPERAND_TYPE_IMM32; | |
1894 | static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S; | |
1895 | static const i386_operand_type imm64 = OPERAND_TYPE_IMM64; | |
1896 | static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32; | |
1897 | static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S; | |
1898 | static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S; | |
a683cc34 | 1899 | static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4; |
40fb9820 L |
1900 | |
1901 | enum operand_type | |
1902 | { | |
1903 | reg, | |
40fb9820 L |
1904 | imm, |
1905 | disp, | |
1906 | anymem | |
1907 | }; | |
1908 | ||
c6fb90c8 | 1909 | static INLINE int |
40fb9820 L |
1910 | operand_type_check (i386_operand_type t, enum operand_type c) |
1911 | { | |
1912 | switch (c) | |
1913 | { | |
1914 | case reg: | |
dc821c5f | 1915 | return t.bitfield.reg; |
40fb9820 | 1916 | |
40fb9820 L |
1917 | case imm: |
1918 | return (t.bitfield.imm8 | |
1919 | || t.bitfield.imm8s | |
1920 | || t.bitfield.imm16 | |
1921 | || t.bitfield.imm32 | |
1922 | || t.bitfield.imm32s | |
1923 | || t.bitfield.imm64); | |
1924 | ||
1925 | case disp: | |
1926 | return (t.bitfield.disp8 | |
1927 | || t.bitfield.disp16 | |
1928 | || t.bitfield.disp32 | |
1929 | || t.bitfield.disp32s | |
1930 | || t.bitfield.disp64); | |
1931 | ||
1932 | case anymem: | |
1933 | return (t.bitfield.disp8 | |
1934 | || t.bitfield.disp16 | |
1935 | || t.bitfield.disp32 | |
1936 | || t.bitfield.disp32s | |
1937 | || t.bitfield.disp64 | |
1938 | || t.bitfield.baseindex); | |
1939 | ||
1940 | default: | |
1941 | abort (); | |
1942 | } | |
2cfe26b6 AM |
1943 | |
1944 | return 0; | |
40fb9820 L |
1945 | } |
1946 | ||
7a54636a L |
1947 | /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size |
1948 | between operand GIVEN and opeand WANTED for instruction template T. */ | |
5c07affc L |
1949 | |
1950 | static INLINE int | |
7a54636a L |
1951 | match_operand_size (const insn_template *t, unsigned int wanted, |
1952 | unsigned int given) | |
5c07affc | 1953 | { |
3ac21baa JB |
1954 | return !((i.types[given].bitfield.byte |
1955 | && !t->operand_types[wanted].bitfield.byte) | |
1956 | || (i.types[given].bitfield.word | |
1957 | && !t->operand_types[wanted].bitfield.word) | |
1958 | || (i.types[given].bitfield.dword | |
1959 | && !t->operand_types[wanted].bitfield.dword) | |
1960 | || (i.types[given].bitfield.qword | |
1961 | && !t->operand_types[wanted].bitfield.qword) | |
1962 | || (i.types[given].bitfield.tbyte | |
1963 | && !t->operand_types[wanted].bitfield.tbyte)); | |
5c07affc L |
1964 | } |
1965 | ||
dd40ce22 L |
1966 | /* Return 1 if there is no conflict in SIMD register between operand |
1967 | GIVEN and opeand WANTED for instruction template T. */ | |
1b54b8d7 JB |
1968 | |
1969 | static INLINE int | |
dd40ce22 L |
1970 | match_simd_size (const insn_template *t, unsigned int wanted, |
1971 | unsigned int given) | |
1b54b8d7 | 1972 | { |
3ac21baa JB |
1973 | return !((i.types[given].bitfield.xmmword |
1974 | && !t->operand_types[wanted].bitfield.xmmword) | |
1975 | || (i.types[given].bitfield.ymmword | |
1976 | && !t->operand_types[wanted].bitfield.ymmword) | |
1977 | || (i.types[given].bitfield.zmmword | |
1978 | && !t->operand_types[wanted].bitfield.zmmword)); | |
1b54b8d7 JB |
1979 | } |
1980 | ||
7a54636a L |
1981 | /* Return 1 if there is no conflict in any size between operand GIVEN |
1982 | and opeand WANTED for instruction template T. */ | |
5c07affc L |
1983 | |
1984 | static INLINE int | |
dd40ce22 L |
1985 | match_mem_size (const insn_template *t, unsigned int wanted, |
1986 | unsigned int given) | |
5c07affc | 1987 | { |
7a54636a | 1988 | return (match_operand_size (t, wanted, given) |
3ac21baa | 1989 | && !((i.types[given].bitfield.unspecified |
af508cb9 | 1990 | && !i.broadcast |
3ac21baa JB |
1991 | && !t->operand_types[wanted].bitfield.unspecified) |
1992 | || (i.types[given].bitfield.fword | |
1993 | && !t->operand_types[wanted].bitfield.fword) | |
1b54b8d7 JB |
1994 | /* For scalar opcode templates to allow register and memory |
1995 | operands at the same time, some special casing is needed | |
d6793fa1 JB |
1996 | here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and |
1997 | down-conversion vpmov*. */ | |
3ac21baa | 1998 | || ((t->operand_types[wanted].bitfield.regsimd |
1b54b8d7 | 1999 | && !t->opcode_modifier.broadcast |
3ac21baa JB |
2000 | && (t->operand_types[wanted].bitfield.byte |
2001 | || t->operand_types[wanted].bitfield.word | |
2002 | || t->operand_types[wanted].bitfield.dword | |
2003 | || t->operand_types[wanted].bitfield.qword)) | |
2004 | ? (i.types[given].bitfield.xmmword | |
2005 | || i.types[given].bitfield.ymmword | |
2006 | || i.types[given].bitfield.zmmword) | |
2007 | : !match_simd_size(t, wanted, given)))); | |
5c07affc L |
2008 | } |
2009 | ||
3ac21baa JB |
2010 | /* Return value has MATCH_STRAIGHT set if there is no size conflict on any |
2011 | operands for instruction template T, and it has MATCH_REVERSE set if there | |
2012 | is no size conflict on any operands for the template with operands reversed | |
2013 | (and the template allows for reversing in the first place). */ | |
5c07affc | 2014 | |
3ac21baa JB |
2015 | #define MATCH_STRAIGHT 1 |
2016 | #define MATCH_REVERSE 2 | |
2017 | ||
2018 | static INLINE unsigned int | |
d3ce72d0 | 2019 | operand_size_match (const insn_template *t) |
5c07affc | 2020 | { |
3ac21baa | 2021 | unsigned int j, match = MATCH_STRAIGHT; |
5c07affc L |
2022 | |
2023 | /* Don't check jump instructions. */ | |
2024 | if (t->opcode_modifier.jump | |
2025 | || t->opcode_modifier.jumpbyte | |
2026 | || t->opcode_modifier.jumpdword | |
2027 | || t->opcode_modifier.jumpintersegment) | |
2028 | return match; | |
2029 | ||
2030 | /* Check memory and accumulator operand size. */ | |
2031 | for (j = 0; j < i.operands; j++) | |
2032 | { | |
1b54b8d7 JB |
2033 | if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd |
2034 | && t->operand_types[j].bitfield.anysize) | |
5c07affc L |
2035 | continue; |
2036 | ||
1b54b8d7 | 2037 | if (t->operand_types[j].bitfield.reg |
7a54636a | 2038 | && !match_operand_size (t, j, j)) |
5c07affc L |
2039 | { |
2040 | match = 0; | |
2041 | break; | |
2042 | } | |
2043 | ||
1b54b8d7 | 2044 | if (t->operand_types[j].bitfield.regsimd |
3ac21baa | 2045 | && !match_simd_size (t, j, j)) |
1b54b8d7 JB |
2046 | { |
2047 | match = 0; | |
2048 | break; | |
2049 | } | |
2050 | ||
2051 | if (t->operand_types[j].bitfield.acc | |
7a54636a | 2052 | && (!match_operand_size (t, j, j) || !match_simd_size (t, j, j))) |
1b54b8d7 JB |
2053 | { |
2054 | match = 0; | |
2055 | break; | |
2056 | } | |
2057 | ||
c48dadc9 | 2058 | if ((i.flags[j] & Operand_Mem) && !match_mem_size (t, j, j)) |
5c07affc L |
2059 | { |
2060 | match = 0; | |
2061 | break; | |
2062 | } | |
2063 | } | |
2064 | ||
3ac21baa | 2065 | if (!t->opcode_modifier.d) |
891edac4 L |
2066 | { |
2067 | mismatch: | |
3ac21baa JB |
2068 | if (!match) |
2069 | i.error = operand_size_mismatch; | |
2070 | return match; | |
891edac4 | 2071 | } |
5c07affc L |
2072 | |
2073 | /* Check reverse. */ | |
f5eb1d70 | 2074 | gas_assert (i.operands >= 2 && i.operands <= 3); |
5c07affc | 2075 | |
f5eb1d70 | 2076 | for (j = 0; j < i.operands; j++) |
5c07affc | 2077 | { |
f5eb1d70 JB |
2078 | unsigned int given = i.operands - j - 1; |
2079 | ||
dbbc8b7e | 2080 | if (t->operand_types[j].bitfield.reg |
f5eb1d70 | 2081 | && !match_operand_size (t, j, given)) |
891edac4 | 2082 | goto mismatch; |
5c07affc | 2083 | |
dbbc8b7e | 2084 | if (t->operand_types[j].bitfield.regsimd |
f5eb1d70 | 2085 | && !match_simd_size (t, j, given)) |
dbbc8b7e JB |
2086 | goto mismatch; |
2087 | ||
2088 | if (t->operand_types[j].bitfield.acc | |
f5eb1d70 JB |
2089 | && (!match_operand_size (t, j, given) |
2090 | || !match_simd_size (t, j, given))) | |
dbbc8b7e JB |
2091 | goto mismatch; |
2092 | ||
f5eb1d70 | 2093 | if ((i.flags[given] & Operand_Mem) && !match_mem_size (t, j, given)) |
891edac4 | 2094 | goto mismatch; |
5c07affc L |
2095 | } |
2096 | ||
3ac21baa | 2097 | return match | MATCH_REVERSE; |
5c07affc L |
2098 | } |
2099 | ||
c6fb90c8 | 2100 | static INLINE int |
40fb9820 L |
2101 | operand_type_match (i386_operand_type overlap, |
2102 | i386_operand_type given) | |
2103 | { | |
2104 | i386_operand_type temp = overlap; | |
2105 | ||
2106 | temp.bitfield.jumpabsolute = 0; | |
7d5e4556 | 2107 | temp.bitfield.unspecified = 0; |
5c07affc L |
2108 | temp.bitfield.byte = 0; |
2109 | temp.bitfield.word = 0; | |
2110 | temp.bitfield.dword = 0; | |
2111 | temp.bitfield.fword = 0; | |
2112 | temp.bitfield.qword = 0; | |
2113 | temp.bitfield.tbyte = 0; | |
2114 | temp.bitfield.xmmword = 0; | |
c0f3af97 | 2115 | temp.bitfield.ymmword = 0; |
43234a1e | 2116 | temp.bitfield.zmmword = 0; |
0dfbf9d7 | 2117 | if (operand_type_all_zero (&temp)) |
891edac4 | 2118 | goto mismatch; |
40fb9820 | 2119 | |
891edac4 L |
2120 | if (given.bitfield.baseindex == overlap.bitfield.baseindex |
2121 | && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute) | |
2122 | return 1; | |
2123 | ||
2124 | mismatch: | |
a65babc9 | 2125 | i.error = operand_type_mismatch; |
891edac4 | 2126 | return 0; |
40fb9820 L |
2127 | } |
2128 | ||
7d5e4556 | 2129 | /* If given types g0 and g1 are registers they must be of the same type |
10c17abd JB |
2130 | unless the expected operand type register overlap is null. |
2131 | Memory operand size of certain SIMD instructions is also being checked | |
2132 | here. */ | |
40fb9820 | 2133 | |
c6fb90c8 | 2134 | static INLINE int |
dc821c5f | 2135 | operand_type_register_match (i386_operand_type g0, |
40fb9820 | 2136 | i386_operand_type t0, |
40fb9820 L |
2137 | i386_operand_type g1, |
2138 | i386_operand_type t1) | |
2139 | { | |
10c17abd JB |
2140 | if (!g0.bitfield.reg |
2141 | && !g0.bitfield.regsimd | |
2142 | && (!operand_type_check (g0, anymem) | |
2143 | || g0.bitfield.unspecified | |
2144 | || !t0.bitfield.regsimd)) | |
40fb9820 L |
2145 | return 1; |
2146 | ||
10c17abd JB |
2147 | if (!g1.bitfield.reg |
2148 | && !g1.bitfield.regsimd | |
2149 | && (!operand_type_check (g1, anymem) | |
2150 | || g1.bitfield.unspecified | |
2151 | || !t1.bitfield.regsimd)) | |
40fb9820 L |
2152 | return 1; |
2153 | ||
dc821c5f JB |
2154 | if (g0.bitfield.byte == g1.bitfield.byte |
2155 | && g0.bitfield.word == g1.bitfield.word | |
2156 | && g0.bitfield.dword == g1.bitfield.dword | |
10c17abd JB |
2157 | && g0.bitfield.qword == g1.bitfield.qword |
2158 | && g0.bitfield.xmmword == g1.bitfield.xmmword | |
2159 | && g0.bitfield.ymmword == g1.bitfield.ymmword | |
2160 | && g0.bitfield.zmmword == g1.bitfield.zmmword) | |
40fb9820 L |
2161 | return 1; |
2162 | ||
dc821c5f JB |
2163 | if (!(t0.bitfield.byte & t1.bitfield.byte) |
2164 | && !(t0.bitfield.word & t1.bitfield.word) | |
2165 | && !(t0.bitfield.dword & t1.bitfield.dword) | |
10c17abd JB |
2166 | && !(t0.bitfield.qword & t1.bitfield.qword) |
2167 | && !(t0.bitfield.xmmword & t1.bitfield.xmmword) | |
2168 | && !(t0.bitfield.ymmword & t1.bitfield.ymmword) | |
2169 | && !(t0.bitfield.zmmword & t1.bitfield.zmmword)) | |
891edac4 L |
2170 | return 1; |
2171 | ||
a65babc9 | 2172 | i.error = register_type_mismatch; |
891edac4 L |
2173 | |
2174 | return 0; | |
40fb9820 L |
2175 | } |
2176 | ||
4c692bc7 JB |
2177 | static INLINE unsigned int |
2178 | register_number (const reg_entry *r) | |
2179 | { | |
2180 | unsigned int nr = r->reg_num; | |
2181 | ||
2182 | if (r->reg_flags & RegRex) | |
2183 | nr += 8; | |
2184 | ||
200cbe0f L |
2185 | if (r->reg_flags & RegVRex) |
2186 | nr += 16; | |
2187 | ||
4c692bc7 JB |
2188 | return nr; |
2189 | } | |
2190 | ||
252b5132 | 2191 | static INLINE unsigned int |
40fb9820 | 2192 | mode_from_disp_size (i386_operand_type t) |
252b5132 | 2193 | { |
b5014f7a | 2194 | if (t.bitfield.disp8) |
40fb9820 L |
2195 | return 1; |
2196 | else if (t.bitfield.disp16 | |
2197 | || t.bitfield.disp32 | |
2198 | || t.bitfield.disp32s) | |
2199 | return 2; | |
2200 | else | |
2201 | return 0; | |
252b5132 RH |
2202 | } |
2203 | ||
2204 | static INLINE int | |
65879393 | 2205 | fits_in_signed_byte (addressT num) |
252b5132 | 2206 | { |
65879393 | 2207 | return num + 0x80 <= 0xff; |
47926f60 | 2208 | } |
252b5132 RH |
2209 | |
2210 | static INLINE int | |
65879393 | 2211 | fits_in_unsigned_byte (addressT num) |
252b5132 | 2212 | { |
65879393 | 2213 | return num <= 0xff; |
47926f60 | 2214 | } |
252b5132 RH |
2215 | |
2216 | static INLINE int | |
65879393 | 2217 | fits_in_unsigned_word (addressT num) |
252b5132 | 2218 | { |
65879393 | 2219 | return num <= 0xffff; |
47926f60 | 2220 | } |
252b5132 RH |
2221 | |
2222 | static INLINE int | |
65879393 | 2223 | fits_in_signed_word (addressT num) |
252b5132 | 2224 | { |
65879393 | 2225 | return num + 0x8000 <= 0xffff; |
47926f60 | 2226 | } |
2a962e6d | 2227 | |
3e73aa7c | 2228 | static INLINE int |
65879393 | 2229 | fits_in_signed_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2230 | { |
2231 | #ifndef BFD64 | |
2232 | return 1; | |
2233 | #else | |
65879393 | 2234 | return num + 0x80000000 <= 0xffffffff; |
3e73aa7c JH |
2235 | #endif |
2236 | } /* fits_in_signed_long() */ | |
2a962e6d | 2237 | |
3e73aa7c | 2238 | static INLINE int |
65879393 | 2239 | fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2240 | { |
2241 | #ifndef BFD64 | |
2242 | return 1; | |
2243 | #else | |
65879393 | 2244 | return num <= 0xffffffff; |
3e73aa7c JH |
2245 | #endif |
2246 | } /* fits_in_unsigned_long() */ | |
252b5132 | 2247 | |
43234a1e | 2248 | static INLINE int |
b5014f7a | 2249 | fits_in_disp8 (offsetT num) |
43234a1e L |
2250 | { |
2251 | int shift = i.memshift; | |
2252 | unsigned int mask; | |
2253 | ||
2254 | if (shift == -1) | |
2255 | abort (); | |
2256 | ||
2257 | mask = (1 << shift) - 1; | |
2258 | ||
2259 | /* Return 0 if NUM isn't properly aligned. */ | |
2260 | if ((num & mask)) | |
2261 | return 0; | |
2262 | ||
2263 | /* Check if NUM will fit in 8bit after shift. */ | |
2264 | return fits_in_signed_byte (num >> shift); | |
2265 | } | |
2266 | ||
a683cc34 SP |
2267 | static INLINE int |
2268 | fits_in_imm4 (offsetT num) | |
2269 | { | |
2270 | return (num & 0xf) == num; | |
2271 | } | |
2272 | ||
40fb9820 | 2273 | static i386_operand_type |
e3bb37b5 | 2274 | smallest_imm_type (offsetT num) |
252b5132 | 2275 | { |
40fb9820 | 2276 | i386_operand_type t; |
7ab9ffdd | 2277 | |
0dfbf9d7 | 2278 | operand_type_set (&t, 0); |
40fb9820 L |
2279 | t.bitfield.imm64 = 1; |
2280 | ||
2281 | if (cpu_arch_tune != PROCESSOR_I486 && num == 1) | |
e413e4e9 AM |
2282 | { |
2283 | /* This code is disabled on the 486 because all the Imm1 forms | |
2284 | in the opcode table are slower on the i486. They're the | |
2285 | versions with the implicitly specified single-position | |
2286 | displacement, which has another syntax if you really want to | |
2287 | use that form. */ | |
40fb9820 L |
2288 | t.bitfield.imm1 = 1; |
2289 | t.bitfield.imm8 = 1; | |
2290 | t.bitfield.imm8s = 1; | |
2291 | t.bitfield.imm16 = 1; | |
2292 | t.bitfield.imm32 = 1; | |
2293 | t.bitfield.imm32s = 1; | |
2294 | } | |
2295 | else if (fits_in_signed_byte (num)) | |
2296 | { | |
2297 | t.bitfield.imm8 = 1; | |
2298 | t.bitfield.imm8s = 1; | |
2299 | t.bitfield.imm16 = 1; | |
2300 | t.bitfield.imm32 = 1; | |
2301 | t.bitfield.imm32s = 1; | |
2302 | } | |
2303 | else if (fits_in_unsigned_byte (num)) | |
2304 | { | |
2305 | t.bitfield.imm8 = 1; | |
2306 | t.bitfield.imm16 = 1; | |
2307 | t.bitfield.imm32 = 1; | |
2308 | t.bitfield.imm32s = 1; | |
2309 | } | |
2310 | else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
2311 | { | |
2312 | t.bitfield.imm16 = 1; | |
2313 | t.bitfield.imm32 = 1; | |
2314 | t.bitfield.imm32s = 1; | |
2315 | } | |
2316 | else if (fits_in_signed_long (num)) | |
2317 | { | |
2318 | t.bitfield.imm32 = 1; | |
2319 | t.bitfield.imm32s = 1; | |
2320 | } | |
2321 | else if (fits_in_unsigned_long (num)) | |
2322 | t.bitfield.imm32 = 1; | |
2323 | ||
2324 | return t; | |
47926f60 | 2325 | } |
252b5132 | 2326 | |
847f7ad4 | 2327 | static offsetT |
e3bb37b5 | 2328 | offset_in_range (offsetT val, int size) |
847f7ad4 | 2329 | { |
508866be | 2330 | addressT mask; |
ba2adb93 | 2331 | |
847f7ad4 AM |
2332 | switch (size) |
2333 | { | |
508866be L |
2334 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
2335 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 2336 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
3e73aa7c JH |
2337 | #ifdef BFD64 |
2338 | case 8: mask = ((addressT) 2 << 63) - 1; break; | |
2339 | #endif | |
47926f60 | 2340 | default: abort (); |
847f7ad4 AM |
2341 | } |
2342 | ||
9de868bf L |
2343 | #ifdef BFD64 |
2344 | /* If BFD64, sign extend val for 32bit address mode. */ | |
2345 | if (flag_code != CODE_64BIT | |
2346 | || i.prefix[ADDR_PREFIX]) | |
3e73aa7c JH |
2347 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) |
2348 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
fa289fb8 | 2349 | #endif |
ba2adb93 | 2350 | |
47926f60 | 2351 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
847f7ad4 AM |
2352 | { |
2353 | char buf1[40], buf2[40]; | |
2354 | ||
2355 | sprint_value (buf1, val); | |
2356 | sprint_value (buf2, val & mask); | |
2357 | as_warn (_("%s shortened to %s"), buf1, buf2); | |
2358 | } | |
2359 | return val & mask; | |
2360 | } | |
2361 | ||
c32fa91d L |
2362 | enum PREFIX_GROUP |
2363 | { | |
2364 | PREFIX_EXIST = 0, | |
2365 | PREFIX_LOCK, | |
2366 | PREFIX_REP, | |
04ef582a | 2367 | PREFIX_DS, |
c32fa91d L |
2368 | PREFIX_OTHER |
2369 | }; | |
2370 | ||
2371 | /* Returns | |
2372 | a. PREFIX_EXIST if attempting to add a prefix where one from the | |
2373 | same class already exists. | |
2374 | b. PREFIX_LOCK if lock prefix is added. | |
2375 | c. PREFIX_REP if rep/repne prefix is added. | |
04ef582a L |
2376 | d. PREFIX_DS if ds prefix is added. |
2377 | e. PREFIX_OTHER if other prefix is added. | |
c32fa91d L |
2378 | */ |
2379 | ||
2380 | static enum PREFIX_GROUP | |
e3bb37b5 | 2381 | add_prefix (unsigned int prefix) |
252b5132 | 2382 | { |
c32fa91d | 2383 | enum PREFIX_GROUP ret = PREFIX_OTHER; |
b1905489 | 2384 | unsigned int q; |
252b5132 | 2385 | |
29b0f896 AM |
2386 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
2387 | && flag_code == CODE_64BIT) | |
b1905489 | 2388 | { |
161a04f6 | 2389 | if ((i.prefix[REX_PREFIX] & prefix & REX_W) |
44846f29 JB |
2390 | || (i.prefix[REX_PREFIX] & prefix & REX_R) |
2391 | || (i.prefix[REX_PREFIX] & prefix & REX_X) | |
2392 | || (i.prefix[REX_PREFIX] & prefix & REX_B)) | |
c32fa91d | 2393 | ret = PREFIX_EXIST; |
b1905489 JB |
2394 | q = REX_PREFIX; |
2395 | } | |
3e73aa7c | 2396 | else |
b1905489 JB |
2397 | { |
2398 | switch (prefix) | |
2399 | { | |
2400 | default: | |
2401 | abort (); | |
2402 | ||
b1905489 | 2403 | case DS_PREFIX_OPCODE: |
04ef582a L |
2404 | ret = PREFIX_DS; |
2405 | /* Fall through. */ | |
2406 | case CS_PREFIX_OPCODE: | |
b1905489 JB |
2407 | case ES_PREFIX_OPCODE: |
2408 | case FS_PREFIX_OPCODE: | |
2409 | case GS_PREFIX_OPCODE: | |
2410 | case SS_PREFIX_OPCODE: | |
2411 | q = SEG_PREFIX; | |
2412 | break; | |
2413 | ||
2414 | case REPNE_PREFIX_OPCODE: | |
2415 | case REPE_PREFIX_OPCODE: | |
c32fa91d L |
2416 | q = REP_PREFIX; |
2417 | ret = PREFIX_REP; | |
2418 | break; | |
2419 | ||
b1905489 | 2420 | case LOCK_PREFIX_OPCODE: |
c32fa91d L |
2421 | q = LOCK_PREFIX; |
2422 | ret = PREFIX_LOCK; | |
b1905489 JB |
2423 | break; |
2424 | ||
2425 | case FWAIT_OPCODE: | |
2426 | q = WAIT_PREFIX; | |
2427 | break; | |
2428 | ||
2429 | case ADDR_PREFIX_OPCODE: | |
2430 | q = ADDR_PREFIX; | |
2431 | break; | |
2432 | ||
2433 | case DATA_PREFIX_OPCODE: | |
2434 | q = DATA_PREFIX; | |
2435 | break; | |
2436 | } | |
2437 | if (i.prefix[q] != 0) | |
c32fa91d | 2438 | ret = PREFIX_EXIST; |
b1905489 | 2439 | } |
252b5132 | 2440 | |
b1905489 | 2441 | if (ret) |
252b5132 | 2442 | { |
b1905489 JB |
2443 | if (!i.prefix[q]) |
2444 | ++i.prefixes; | |
2445 | i.prefix[q] |= prefix; | |
252b5132 | 2446 | } |
b1905489 JB |
2447 | else |
2448 | as_bad (_("same type of prefix used twice")); | |
252b5132 | 2449 | |
252b5132 RH |
2450 | return ret; |
2451 | } | |
2452 | ||
2453 | static void | |
78f12dd3 | 2454 | update_code_flag (int value, int check) |
eecb386c | 2455 | { |
78f12dd3 L |
2456 | PRINTF_LIKE ((*as_error)); |
2457 | ||
1e9cc1c2 | 2458 | flag_code = (enum flag_code) value; |
40fb9820 L |
2459 | if (flag_code == CODE_64BIT) |
2460 | { | |
2461 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2462 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
40fb9820 L |
2463 | } |
2464 | else | |
2465 | { | |
2466 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2467 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
40fb9820 L |
2468 | } |
2469 | if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm ) | |
3e73aa7c | 2470 | { |
78f12dd3 L |
2471 | if (check) |
2472 | as_error = as_fatal; | |
2473 | else | |
2474 | as_error = as_bad; | |
2475 | (*as_error) (_("64bit mode not supported on `%s'."), | |
2476 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2477 | } |
40fb9820 | 2478 | if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) |
3e73aa7c | 2479 | { |
78f12dd3 L |
2480 | if (check) |
2481 | as_error = as_fatal; | |
2482 | else | |
2483 | as_error = as_bad; | |
2484 | (*as_error) (_("32bit mode not supported on `%s'."), | |
2485 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2486 | } |
eecb386c AM |
2487 | stackop_size = '\0'; |
2488 | } | |
2489 | ||
78f12dd3 L |
2490 | static void |
2491 | set_code_flag (int value) | |
2492 | { | |
2493 | update_code_flag (value, 0); | |
2494 | } | |
2495 | ||
eecb386c | 2496 | static void |
e3bb37b5 | 2497 | set_16bit_gcc_code_flag (int new_code_flag) |
252b5132 | 2498 | { |
1e9cc1c2 | 2499 | flag_code = (enum flag_code) new_code_flag; |
40fb9820 L |
2500 | if (flag_code != CODE_16BIT) |
2501 | abort (); | |
2502 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2503 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
9306ca4a | 2504 | stackop_size = LONG_MNEM_SUFFIX; |
252b5132 RH |
2505 | } |
2506 | ||
2507 | static void | |
e3bb37b5 | 2508 | set_intel_syntax (int syntax_flag) |
252b5132 RH |
2509 | { |
2510 | /* Find out if register prefixing is specified. */ | |
2511 | int ask_naked_reg = 0; | |
2512 | ||
2513 | SKIP_WHITESPACE (); | |
29b0f896 | 2514 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
252b5132 | 2515 | { |
d02603dc NC |
2516 | char *string; |
2517 | int e = get_symbol_name (&string); | |
252b5132 | 2518 | |
47926f60 | 2519 | if (strcmp (string, "prefix") == 0) |
252b5132 | 2520 | ask_naked_reg = 1; |
47926f60 | 2521 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
2522 | ask_naked_reg = -1; |
2523 | else | |
d0b47220 | 2524 | as_bad (_("bad argument to syntax directive.")); |
d02603dc | 2525 | (void) restore_line_pointer (e); |
252b5132 RH |
2526 | } |
2527 | demand_empty_rest_of_line (); | |
c3332e24 | 2528 | |
252b5132 RH |
2529 | intel_syntax = syntax_flag; |
2530 | ||
2531 | if (ask_naked_reg == 0) | |
f86103b7 AM |
2532 | allow_naked_reg = (intel_syntax |
2533 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); | |
252b5132 RH |
2534 | else |
2535 | allow_naked_reg = (ask_naked_reg < 0); | |
9306ca4a | 2536 | |
ee86248c | 2537 | expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0); |
7ab9ffdd | 2538 | |
e4a3b5a4 | 2539 | identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; |
9306ca4a | 2540 | identifier_chars['$'] = intel_syntax ? '$' : 0; |
e4a3b5a4 | 2541 | register_prefix = allow_naked_reg ? "" : "%"; |
252b5132 RH |
2542 | } |
2543 | ||
1efbbeb4 L |
2544 | static void |
2545 | set_intel_mnemonic (int mnemonic_flag) | |
2546 | { | |
e1d4d893 | 2547 | intel_mnemonic = mnemonic_flag; |
1efbbeb4 L |
2548 | } |
2549 | ||
db51cc60 L |
2550 | static void |
2551 | set_allow_index_reg (int flag) | |
2552 | { | |
2553 | allow_index_reg = flag; | |
2554 | } | |
2555 | ||
cb19c032 | 2556 | static void |
7bab8ab5 | 2557 | set_check (int what) |
cb19c032 | 2558 | { |
7bab8ab5 JB |
2559 | enum check_kind *kind; |
2560 | const char *str; | |
2561 | ||
2562 | if (what) | |
2563 | { | |
2564 | kind = &operand_check; | |
2565 | str = "operand"; | |
2566 | } | |
2567 | else | |
2568 | { | |
2569 | kind = &sse_check; | |
2570 | str = "sse"; | |
2571 | } | |
2572 | ||
cb19c032 L |
2573 | SKIP_WHITESPACE (); |
2574 | ||
2575 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
2576 | { | |
d02603dc NC |
2577 | char *string; |
2578 | int e = get_symbol_name (&string); | |
cb19c032 L |
2579 | |
2580 | if (strcmp (string, "none") == 0) | |
7bab8ab5 | 2581 | *kind = check_none; |
cb19c032 | 2582 | else if (strcmp (string, "warning") == 0) |
7bab8ab5 | 2583 | *kind = check_warning; |
cb19c032 | 2584 | else if (strcmp (string, "error") == 0) |
7bab8ab5 | 2585 | *kind = check_error; |
cb19c032 | 2586 | else |
7bab8ab5 | 2587 | as_bad (_("bad argument to %s_check directive."), str); |
d02603dc | 2588 | (void) restore_line_pointer (e); |
cb19c032 L |
2589 | } |
2590 | else | |
7bab8ab5 | 2591 | as_bad (_("missing argument for %s_check directive"), str); |
cb19c032 L |
2592 | |
2593 | demand_empty_rest_of_line (); | |
2594 | } | |
2595 | ||
8a9036a4 L |
2596 | static void |
2597 | check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED, | |
1e9cc1c2 | 2598 | i386_cpu_flags new_flag ATTRIBUTE_UNUSED) |
8a9036a4 L |
2599 | { |
2600 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2601 | static const char *arch; | |
2602 | ||
2603 | /* Intel LIOM is only supported on ELF. */ | |
2604 | if (!IS_ELF) | |
2605 | return; | |
2606 | ||
2607 | if (!arch) | |
2608 | { | |
2609 | /* Use cpu_arch_name if it is set in md_parse_option. Otherwise | |
2610 | use default_arch. */ | |
2611 | arch = cpu_arch_name; | |
2612 | if (!arch) | |
2613 | arch = default_arch; | |
2614 | } | |
2615 | ||
81486035 L |
2616 | /* If we are targeting Intel MCU, we must enable it. */ |
2617 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU | |
2618 | || new_flag.bitfield.cpuiamcu) | |
2619 | return; | |
2620 | ||
3632d14b | 2621 | /* If we are targeting Intel L1OM, we must enable it. */ |
8a9036a4 | 2622 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM |
1e9cc1c2 | 2623 | || new_flag.bitfield.cpul1om) |
8a9036a4 | 2624 | return; |
76ba9986 | 2625 | |
7a9068fe L |
2626 | /* If we are targeting Intel K1OM, we must enable it. */ |
2627 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM | |
2628 | || new_flag.bitfield.cpuk1om) | |
2629 | return; | |
2630 | ||
8a9036a4 L |
2631 | as_bad (_("`%s' is not supported on `%s'"), name, arch); |
2632 | #endif | |
2633 | } | |
2634 | ||
e413e4e9 | 2635 | static void |
e3bb37b5 | 2636 | set_cpu_arch (int dummy ATTRIBUTE_UNUSED) |
e413e4e9 | 2637 | { |
47926f60 | 2638 | SKIP_WHITESPACE (); |
e413e4e9 | 2639 | |
29b0f896 | 2640 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
e413e4e9 | 2641 | { |
d02603dc NC |
2642 | char *string; |
2643 | int e = get_symbol_name (&string); | |
91d6fa6a | 2644 | unsigned int j; |
40fb9820 | 2645 | i386_cpu_flags flags; |
e413e4e9 | 2646 | |
91d6fa6a | 2647 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
e413e4e9 | 2648 | { |
91d6fa6a | 2649 | if (strcmp (string, cpu_arch[j].name) == 0) |
e413e4e9 | 2650 | { |
91d6fa6a | 2651 | check_cpu_arch_compatible (string, cpu_arch[j].flags); |
8a9036a4 | 2652 | |
5c6af06e JB |
2653 | if (*string != '.') |
2654 | { | |
91d6fa6a | 2655 | cpu_arch_name = cpu_arch[j].name; |
5c6af06e | 2656 | cpu_sub_arch_name = NULL; |
91d6fa6a | 2657 | cpu_arch_flags = cpu_arch[j].flags; |
40fb9820 L |
2658 | if (flag_code == CODE_64BIT) |
2659 | { | |
2660 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2661 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
2662 | } | |
2663 | else | |
2664 | { | |
2665 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2666 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
2667 | } | |
91d6fa6a NC |
2668 | cpu_arch_isa = cpu_arch[j].type; |
2669 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
ccc9c027 L |
2670 | if (!cpu_arch_tune_set) |
2671 | { | |
2672 | cpu_arch_tune = cpu_arch_isa; | |
2673 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
2674 | } | |
5c6af06e JB |
2675 | break; |
2676 | } | |
40fb9820 | 2677 | |
293f5f65 L |
2678 | flags = cpu_flags_or (cpu_arch_flags, |
2679 | cpu_arch[j].flags); | |
81486035 | 2680 | |
5b64d091 | 2681 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
5c6af06e | 2682 | { |
6305a203 L |
2683 | if (cpu_sub_arch_name) |
2684 | { | |
2685 | char *name = cpu_sub_arch_name; | |
2686 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 2687 | cpu_arch[j].name, |
1bf57e9f | 2688 | (const char *) NULL); |
6305a203 L |
2689 | free (name); |
2690 | } | |
2691 | else | |
91d6fa6a | 2692 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
40fb9820 | 2693 | cpu_arch_flags = flags; |
a586129e | 2694 | cpu_arch_isa_flags = flags; |
5c6af06e | 2695 | } |
0089dace L |
2696 | else |
2697 | cpu_arch_isa_flags | |
2698 | = cpu_flags_or (cpu_arch_isa_flags, | |
2699 | cpu_arch[j].flags); | |
d02603dc | 2700 | (void) restore_line_pointer (e); |
5c6af06e JB |
2701 | demand_empty_rest_of_line (); |
2702 | return; | |
e413e4e9 AM |
2703 | } |
2704 | } | |
293f5f65 L |
2705 | |
2706 | if (*string == '.' && j >= ARRAY_SIZE (cpu_arch)) | |
2707 | { | |
33eaf5de | 2708 | /* Disable an ISA extension. */ |
293f5f65 L |
2709 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
2710 | if (strcmp (string + 1, cpu_noarch [j].name) == 0) | |
2711 | { | |
2712 | flags = cpu_flags_and_not (cpu_arch_flags, | |
2713 | cpu_noarch[j].flags); | |
2714 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
2715 | { | |
2716 | if (cpu_sub_arch_name) | |
2717 | { | |
2718 | char *name = cpu_sub_arch_name; | |
2719 | cpu_sub_arch_name = concat (name, string, | |
2720 | (const char *) NULL); | |
2721 | free (name); | |
2722 | } | |
2723 | else | |
2724 | cpu_sub_arch_name = xstrdup (string); | |
2725 | cpu_arch_flags = flags; | |
2726 | cpu_arch_isa_flags = flags; | |
2727 | } | |
2728 | (void) restore_line_pointer (e); | |
2729 | demand_empty_rest_of_line (); | |
2730 | return; | |
2731 | } | |
2732 | ||
2733 | j = ARRAY_SIZE (cpu_arch); | |
2734 | } | |
2735 | ||
91d6fa6a | 2736 | if (j >= ARRAY_SIZE (cpu_arch)) |
e413e4e9 AM |
2737 | as_bad (_("no such architecture: `%s'"), string); |
2738 | ||
2739 | *input_line_pointer = e; | |
2740 | } | |
2741 | else | |
2742 | as_bad (_("missing cpu architecture")); | |
2743 | ||
fddf5b5b AM |
2744 | no_cond_jump_promotion = 0; |
2745 | if (*input_line_pointer == ',' | |
29b0f896 | 2746 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
fddf5b5b | 2747 | { |
d02603dc NC |
2748 | char *string; |
2749 | char e; | |
2750 | ||
2751 | ++input_line_pointer; | |
2752 | e = get_symbol_name (&string); | |
fddf5b5b AM |
2753 | |
2754 | if (strcmp (string, "nojumps") == 0) | |
2755 | no_cond_jump_promotion = 1; | |
2756 | else if (strcmp (string, "jumps") == 0) | |
2757 | ; | |
2758 | else | |
2759 | as_bad (_("no such architecture modifier: `%s'"), string); | |
2760 | ||
d02603dc | 2761 | (void) restore_line_pointer (e); |
fddf5b5b AM |
2762 | } |
2763 | ||
e413e4e9 AM |
2764 | demand_empty_rest_of_line (); |
2765 | } | |
2766 | ||
8a9036a4 L |
2767 | enum bfd_architecture |
2768 | i386_arch (void) | |
2769 | { | |
3632d14b | 2770 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 L |
2771 | { |
2772 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2773 | || flag_code != CODE_64BIT) | |
2774 | as_fatal (_("Intel L1OM is 64bit ELF only")); | |
2775 | return bfd_arch_l1om; | |
2776 | } | |
7a9068fe L |
2777 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2778 | { | |
2779 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2780 | || flag_code != CODE_64BIT) | |
2781 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2782 | return bfd_arch_k1om; | |
2783 | } | |
81486035 L |
2784 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
2785 | { | |
2786 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2787 | || flag_code == CODE_64BIT) | |
2788 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2789 | return bfd_arch_iamcu; | |
2790 | } | |
8a9036a4 L |
2791 | else |
2792 | return bfd_arch_i386; | |
2793 | } | |
2794 | ||
b9d79e03 | 2795 | unsigned long |
7016a5d5 | 2796 | i386_mach (void) |
b9d79e03 | 2797 | { |
351f65ca | 2798 | if (!strncmp (default_arch, "x86_64", 6)) |
8a9036a4 | 2799 | { |
3632d14b | 2800 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 2801 | { |
351f65ca L |
2802 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour |
2803 | || default_arch[6] != '\0') | |
8a9036a4 L |
2804 | as_fatal (_("Intel L1OM is 64bit ELF only")); |
2805 | return bfd_mach_l1om; | |
2806 | } | |
7a9068fe L |
2807 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2808 | { | |
2809 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2810 | || default_arch[6] != '\0') | |
2811 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2812 | return bfd_mach_k1om; | |
2813 | } | |
351f65ca | 2814 | else if (default_arch[6] == '\0') |
8a9036a4 | 2815 | return bfd_mach_x86_64; |
351f65ca L |
2816 | else |
2817 | return bfd_mach_x64_32; | |
8a9036a4 | 2818 | } |
5197d474 L |
2819 | else if (!strcmp (default_arch, "i386") |
2820 | || !strcmp (default_arch, "iamcu")) | |
81486035 L |
2821 | { |
2822 | if (cpu_arch_isa == PROCESSOR_IAMCU) | |
2823 | { | |
2824 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
2825 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2826 | return bfd_mach_i386_iamcu; | |
2827 | } | |
2828 | else | |
2829 | return bfd_mach_i386_i386; | |
2830 | } | |
b9d79e03 | 2831 | else |
2b5d6a91 | 2832 | as_fatal (_("unknown architecture")); |
b9d79e03 | 2833 | } |
b9d79e03 | 2834 | \f |
252b5132 | 2835 | void |
7016a5d5 | 2836 | md_begin (void) |
252b5132 RH |
2837 | { |
2838 | const char *hash_err; | |
2839 | ||
86fa6981 L |
2840 | /* Support pseudo prefixes like {disp32}. */ |
2841 | lex_type ['{'] = LEX_BEGIN_NAME; | |
2842 | ||
47926f60 | 2843 | /* Initialize op_hash hash table. */ |
252b5132 RH |
2844 | op_hash = hash_new (); |
2845 | ||
2846 | { | |
d3ce72d0 | 2847 | const insn_template *optab; |
29b0f896 | 2848 | templates *core_optab; |
252b5132 | 2849 | |
47926f60 KH |
2850 | /* Setup for loop. */ |
2851 | optab = i386_optab; | |
add39d23 | 2852 | core_optab = XNEW (templates); |
252b5132 RH |
2853 | core_optab->start = optab; |
2854 | ||
2855 | while (1) | |
2856 | { | |
2857 | ++optab; | |
2858 | if (optab->name == NULL | |
2859 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
2860 | { | |
2861 | /* different name --> ship out current template list; | |
47926f60 | 2862 | add to hash table; & begin anew. */ |
252b5132 RH |
2863 | core_optab->end = optab; |
2864 | hash_err = hash_insert (op_hash, | |
2865 | (optab - 1)->name, | |
5a49b8ac | 2866 | (void *) core_optab); |
252b5132 RH |
2867 | if (hash_err) |
2868 | { | |
b37df7c4 | 2869 | as_fatal (_("can't hash %s: %s"), |
252b5132 RH |
2870 | (optab - 1)->name, |
2871 | hash_err); | |
2872 | } | |
2873 | if (optab->name == NULL) | |
2874 | break; | |
add39d23 | 2875 | core_optab = XNEW (templates); |
252b5132 RH |
2876 | core_optab->start = optab; |
2877 | } | |
2878 | } | |
2879 | } | |
2880 | ||
47926f60 | 2881 | /* Initialize reg_hash hash table. */ |
252b5132 RH |
2882 | reg_hash = hash_new (); |
2883 | { | |
29b0f896 | 2884 | const reg_entry *regtab; |
c3fe08fa | 2885 | unsigned int regtab_size = i386_regtab_size; |
252b5132 | 2886 | |
c3fe08fa | 2887 | for (regtab = i386_regtab; regtab_size--; regtab++) |
252b5132 | 2888 | { |
5a49b8ac | 2889 | hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab); |
252b5132 | 2890 | if (hash_err) |
b37df7c4 | 2891 | as_fatal (_("can't hash %s: %s"), |
3e73aa7c JH |
2892 | regtab->reg_name, |
2893 | hash_err); | |
252b5132 RH |
2894 | } |
2895 | } | |
2896 | ||
47926f60 | 2897 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 | 2898 | { |
29b0f896 AM |
2899 | int c; |
2900 | char *p; | |
252b5132 RH |
2901 | |
2902 | for (c = 0; c < 256; c++) | |
2903 | { | |
3882b010 | 2904 | if (ISDIGIT (c)) |
252b5132 RH |
2905 | { |
2906 | digit_chars[c] = c; | |
2907 | mnemonic_chars[c] = c; | |
2908 | register_chars[c] = c; | |
2909 | operand_chars[c] = c; | |
2910 | } | |
3882b010 | 2911 | else if (ISLOWER (c)) |
252b5132 RH |
2912 | { |
2913 | mnemonic_chars[c] = c; | |
2914 | register_chars[c] = c; | |
2915 | operand_chars[c] = c; | |
2916 | } | |
3882b010 | 2917 | else if (ISUPPER (c)) |
252b5132 | 2918 | { |
3882b010 | 2919 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
2920 | register_chars[c] = mnemonic_chars[c]; |
2921 | operand_chars[c] = c; | |
2922 | } | |
43234a1e | 2923 | else if (c == '{' || c == '}') |
86fa6981 L |
2924 | { |
2925 | mnemonic_chars[c] = c; | |
2926 | operand_chars[c] = c; | |
2927 | } | |
252b5132 | 2928 | |
3882b010 | 2929 | if (ISALPHA (c) || ISDIGIT (c)) |
252b5132 RH |
2930 | identifier_chars[c] = c; |
2931 | else if (c >= 128) | |
2932 | { | |
2933 | identifier_chars[c] = c; | |
2934 | operand_chars[c] = c; | |
2935 | } | |
2936 | } | |
2937 | ||
2938 | #ifdef LEX_AT | |
2939 | identifier_chars['@'] = '@'; | |
32137342 NC |
2940 | #endif |
2941 | #ifdef LEX_QM | |
2942 | identifier_chars['?'] = '?'; | |
2943 | operand_chars['?'] = '?'; | |
252b5132 | 2944 | #endif |
252b5132 | 2945 | digit_chars['-'] = '-'; |
c0f3af97 | 2946 | mnemonic_chars['_'] = '_'; |
791fe849 | 2947 | mnemonic_chars['-'] = '-'; |
0003779b | 2948 | mnemonic_chars['.'] = '.'; |
252b5132 RH |
2949 | identifier_chars['_'] = '_'; |
2950 | identifier_chars['.'] = '.'; | |
2951 | ||
2952 | for (p = operand_special_chars; *p != '\0'; p++) | |
2953 | operand_chars[(unsigned char) *p] = *p; | |
2954 | } | |
2955 | ||
a4447b93 RH |
2956 | if (flag_code == CODE_64BIT) |
2957 | { | |
ca19b261 KT |
2958 | #if defined (OBJ_COFF) && defined (TE_PE) |
2959 | x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour | |
2960 | ? 32 : 16); | |
2961 | #else | |
a4447b93 | 2962 | x86_dwarf2_return_column = 16; |
ca19b261 | 2963 | #endif |
61ff971f | 2964 | x86_cie_data_alignment = -8; |
a4447b93 RH |
2965 | } |
2966 | else | |
2967 | { | |
2968 | x86_dwarf2_return_column = 8; | |
2969 | x86_cie_data_alignment = -4; | |
2970 | } | |
252b5132 RH |
2971 | } |
2972 | ||
2973 | void | |
e3bb37b5 | 2974 | i386_print_statistics (FILE *file) |
252b5132 RH |
2975 | { |
2976 | hash_print_statistics (file, "i386 opcode", op_hash); | |
2977 | hash_print_statistics (file, "i386 register", reg_hash); | |
2978 | } | |
2979 | \f | |
252b5132 RH |
2980 | #ifdef DEBUG386 |
2981 | ||
ce8a8b2f | 2982 | /* Debugging routines for md_assemble. */ |
d3ce72d0 | 2983 | static void pte (insn_template *); |
40fb9820 | 2984 | static void pt (i386_operand_type); |
e3bb37b5 L |
2985 | static void pe (expressionS *); |
2986 | static void ps (symbolS *); | |
252b5132 RH |
2987 | |
2988 | static void | |
e3bb37b5 | 2989 | pi (char *line, i386_insn *x) |
252b5132 | 2990 | { |
09137c09 | 2991 | unsigned int j; |
252b5132 RH |
2992 | |
2993 | fprintf (stdout, "%s: template ", line); | |
2994 | pte (&x->tm); | |
09f131f2 JH |
2995 | fprintf (stdout, " address: base %s index %s scale %x\n", |
2996 | x->base_reg ? x->base_reg->reg_name : "none", | |
2997 | x->index_reg ? x->index_reg->reg_name : "none", | |
2998 | x->log2_scale_factor); | |
2999 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 3000 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
3001 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
3002 | x->sib.base, x->sib.index, x->sib.scale); | |
3003 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
161a04f6 L |
3004 | (x->rex & REX_W) != 0, |
3005 | (x->rex & REX_R) != 0, | |
3006 | (x->rex & REX_X) != 0, | |
3007 | (x->rex & REX_B) != 0); | |
09137c09 | 3008 | for (j = 0; j < x->operands; j++) |
252b5132 | 3009 | { |
09137c09 SP |
3010 | fprintf (stdout, " #%d: ", j + 1); |
3011 | pt (x->types[j]); | |
252b5132 | 3012 | fprintf (stdout, "\n"); |
dc821c5f | 3013 | if (x->types[j].bitfield.reg |
09137c09 | 3014 | || x->types[j].bitfield.regmmx |
1b54b8d7 | 3015 | || x->types[j].bitfield.regsimd |
09137c09 SP |
3016 | || x->types[j].bitfield.sreg2 |
3017 | || x->types[j].bitfield.sreg3 | |
3018 | || x->types[j].bitfield.control | |
3019 | || x->types[j].bitfield.debug | |
3020 | || x->types[j].bitfield.test) | |
3021 | fprintf (stdout, "%s\n", x->op[j].regs->reg_name); | |
3022 | if (operand_type_check (x->types[j], imm)) | |
3023 | pe (x->op[j].imms); | |
3024 | if (operand_type_check (x->types[j], disp)) | |
3025 | pe (x->op[j].disps); | |
252b5132 RH |
3026 | } |
3027 | } | |
3028 | ||
3029 | static void | |
d3ce72d0 | 3030 | pte (insn_template *t) |
252b5132 | 3031 | { |
09137c09 | 3032 | unsigned int j; |
252b5132 | 3033 | fprintf (stdout, " %d operands ", t->operands); |
47926f60 | 3034 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
3035 | if (t->extension_opcode != None) |
3036 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
40fb9820 | 3037 | if (t->opcode_modifier.d) |
252b5132 | 3038 | fprintf (stdout, "D"); |
40fb9820 | 3039 | if (t->opcode_modifier.w) |
252b5132 RH |
3040 | fprintf (stdout, "W"); |
3041 | fprintf (stdout, "\n"); | |
09137c09 | 3042 | for (j = 0; j < t->operands; j++) |
252b5132 | 3043 | { |
09137c09 SP |
3044 | fprintf (stdout, " #%d type ", j + 1); |
3045 | pt (t->operand_types[j]); | |
252b5132 RH |
3046 | fprintf (stdout, "\n"); |
3047 | } | |
3048 | } | |
3049 | ||
3050 | static void | |
e3bb37b5 | 3051 | pe (expressionS *e) |
252b5132 | 3052 | { |
24eab124 | 3053 | fprintf (stdout, " operation %d\n", e->X_op); |
b77ad1d4 AM |
3054 | fprintf (stdout, " add_number %ld (%lx)\n", |
3055 | (long) e->X_add_number, (long) e->X_add_number); | |
252b5132 RH |
3056 | if (e->X_add_symbol) |
3057 | { | |
3058 | fprintf (stdout, " add_symbol "); | |
3059 | ps (e->X_add_symbol); | |
3060 | fprintf (stdout, "\n"); | |
3061 | } | |
3062 | if (e->X_op_symbol) | |
3063 | { | |
3064 | fprintf (stdout, " op_symbol "); | |
3065 | ps (e->X_op_symbol); | |
3066 | fprintf (stdout, "\n"); | |
3067 | } | |
3068 | } | |
3069 | ||
3070 | static void | |
e3bb37b5 | 3071 | ps (symbolS *s) |
252b5132 RH |
3072 | { |
3073 | fprintf (stdout, "%s type %s%s", | |
3074 | S_GET_NAME (s), | |
3075 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
3076 | segment_name (S_GET_SEGMENT (s))); | |
3077 | } | |
3078 | ||
7b81dfbb | 3079 | static struct type_name |
252b5132 | 3080 | { |
40fb9820 L |
3081 | i386_operand_type mask; |
3082 | const char *name; | |
252b5132 | 3083 | } |
7b81dfbb | 3084 | const type_names[] = |
252b5132 | 3085 | { |
40fb9820 L |
3086 | { OPERAND_TYPE_REG8, "r8" }, |
3087 | { OPERAND_TYPE_REG16, "r16" }, | |
3088 | { OPERAND_TYPE_REG32, "r32" }, | |
3089 | { OPERAND_TYPE_REG64, "r64" }, | |
3090 | { OPERAND_TYPE_IMM8, "i8" }, | |
3091 | { OPERAND_TYPE_IMM8, "i8s" }, | |
3092 | { OPERAND_TYPE_IMM16, "i16" }, | |
3093 | { OPERAND_TYPE_IMM32, "i32" }, | |
3094 | { OPERAND_TYPE_IMM32S, "i32s" }, | |
3095 | { OPERAND_TYPE_IMM64, "i64" }, | |
3096 | { OPERAND_TYPE_IMM1, "i1" }, | |
3097 | { OPERAND_TYPE_BASEINDEX, "BaseIndex" }, | |
3098 | { OPERAND_TYPE_DISP8, "d8" }, | |
3099 | { OPERAND_TYPE_DISP16, "d16" }, | |
3100 | { OPERAND_TYPE_DISP32, "d32" }, | |
3101 | { OPERAND_TYPE_DISP32S, "d32s" }, | |
3102 | { OPERAND_TYPE_DISP64, "d64" }, | |
3103 | { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" }, | |
3104 | { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" }, | |
3105 | { OPERAND_TYPE_CONTROL, "control reg" }, | |
3106 | { OPERAND_TYPE_TEST, "test reg" }, | |
3107 | { OPERAND_TYPE_DEBUG, "debug reg" }, | |
3108 | { OPERAND_TYPE_FLOATREG, "FReg" }, | |
3109 | { OPERAND_TYPE_FLOATACC, "FAcc" }, | |
3110 | { OPERAND_TYPE_SREG2, "SReg2" }, | |
3111 | { OPERAND_TYPE_SREG3, "SReg3" }, | |
3112 | { OPERAND_TYPE_ACC, "Acc" }, | |
3113 | { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" }, | |
3114 | { OPERAND_TYPE_REGMMX, "rMMX" }, | |
3115 | { OPERAND_TYPE_REGXMM, "rXMM" }, | |
0349dc08 | 3116 | { OPERAND_TYPE_REGYMM, "rYMM" }, |
43234a1e L |
3117 | { OPERAND_TYPE_REGZMM, "rZMM" }, |
3118 | { OPERAND_TYPE_REGMASK, "Mask reg" }, | |
40fb9820 | 3119 | { OPERAND_TYPE_ESSEG, "es" }, |
252b5132 RH |
3120 | }; |
3121 | ||
3122 | static void | |
40fb9820 | 3123 | pt (i386_operand_type t) |
252b5132 | 3124 | { |
40fb9820 | 3125 | unsigned int j; |
c6fb90c8 | 3126 | i386_operand_type a; |
252b5132 | 3127 | |
40fb9820 | 3128 | for (j = 0; j < ARRAY_SIZE (type_names); j++) |
c6fb90c8 L |
3129 | { |
3130 | a = operand_type_and (t, type_names[j].mask); | |
0349dc08 | 3131 | if (!operand_type_all_zero (&a)) |
c6fb90c8 L |
3132 | fprintf (stdout, "%s, ", type_names[j].name); |
3133 | } | |
252b5132 RH |
3134 | fflush (stdout); |
3135 | } | |
3136 | ||
3137 | #endif /* DEBUG386 */ | |
3138 | \f | |
252b5132 | 3139 | static bfd_reloc_code_real_type |
3956db08 | 3140 | reloc (unsigned int size, |
64e74474 AM |
3141 | int pcrel, |
3142 | int sign, | |
3143 | bfd_reloc_code_real_type other) | |
252b5132 | 3144 | { |
47926f60 | 3145 | if (other != NO_RELOC) |
3956db08 | 3146 | { |
91d6fa6a | 3147 | reloc_howto_type *rel; |
3956db08 JB |
3148 | |
3149 | if (size == 8) | |
3150 | switch (other) | |
3151 | { | |
64e74474 AM |
3152 | case BFD_RELOC_X86_64_GOT32: |
3153 | return BFD_RELOC_X86_64_GOT64; | |
3154 | break; | |
553d1284 L |
3155 | case BFD_RELOC_X86_64_GOTPLT64: |
3156 | return BFD_RELOC_X86_64_GOTPLT64; | |
3157 | break; | |
64e74474 AM |
3158 | case BFD_RELOC_X86_64_PLTOFF64: |
3159 | return BFD_RELOC_X86_64_PLTOFF64; | |
3160 | break; | |
3161 | case BFD_RELOC_X86_64_GOTPC32: | |
3162 | other = BFD_RELOC_X86_64_GOTPC64; | |
3163 | break; | |
3164 | case BFD_RELOC_X86_64_GOTPCREL: | |
3165 | other = BFD_RELOC_X86_64_GOTPCREL64; | |
3166 | break; | |
3167 | case BFD_RELOC_X86_64_TPOFF32: | |
3168 | other = BFD_RELOC_X86_64_TPOFF64; | |
3169 | break; | |
3170 | case BFD_RELOC_X86_64_DTPOFF32: | |
3171 | other = BFD_RELOC_X86_64_DTPOFF64; | |
3172 | break; | |
3173 | default: | |
3174 | break; | |
3956db08 | 3175 | } |
e05278af | 3176 | |
8ce3d284 | 3177 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
3178 | if (other == BFD_RELOC_SIZE32) |
3179 | { | |
3180 | if (size == 8) | |
1ab668bf | 3181 | other = BFD_RELOC_SIZE64; |
8fd4256d | 3182 | if (pcrel) |
1ab668bf AM |
3183 | { |
3184 | as_bad (_("there are no pc-relative size relocations")); | |
3185 | return NO_RELOC; | |
3186 | } | |
8fd4256d | 3187 | } |
8ce3d284 | 3188 | #endif |
8fd4256d | 3189 | |
e05278af | 3190 | /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ |
f2d8a97c | 3191 | if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc)) |
e05278af JB |
3192 | sign = -1; |
3193 | ||
91d6fa6a NC |
3194 | rel = bfd_reloc_type_lookup (stdoutput, other); |
3195 | if (!rel) | |
3956db08 | 3196 | as_bad (_("unknown relocation (%u)"), other); |
91d6fa6a | 3197 | else if (size != bfd_get_reloc_size (rel)) |
3956db08 | 3198 | as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), |
91d6fa6a | 3199 | bfd_get_reloc_size (rel), |
3956db08 | 3200 | size); |
91d6fa6a | 3201 | else if (pcrel && !rel->pc_relative) |
3956db08 | 3202 | as_bad (_("non-pc-relative relocation for pc-relative field")); |
91d6fa6a | 3203 | else if ((rel->complain_on_overflow == complain_overflow_signed |
3956db08 | 3204 | && !sign) |
91d6fa6a | 3205 | || (rel->complain_on_overflow == complain_overflow_unsigned |
64e74474 | 3206 | && sign > 0)) |
3956db08 JB |
3207 | as_bad (_("relocated field and relocation type differ in signedness")); |
3208 | else | |
3209 | return other; | |
3210 | return NO_RELOC; | |
3211 | } | |
252b5132 RH |
3212 | |
3213 | if (pcrel) | |
3214 | { | |
3e73aa7c | 3215 | if (!sign) |
3956db08 | 3216 | as_bad (_("there are no unsigned pc-relative relocations")); |
252b5132 RH |
3217 | switch (size) |
3218 | { | |
3219 | case 1: return BFD_RELOC_8_PCREL; | |
3220 | case 2: return BFD_RELOC_16_PCREL; | |
d258b828 | 3221 | case 4: return BFD_RELOC_32_PCREL; |
d6ab8113 | 3222 | case 8: return BFD_RELOC_64_PCREL; |
252b5132 | 3223 | } |
3956db08 | 3224 | as_bad (_("cannot do %u byte pc-relative relocation"), size); |
252b5132 RH |
3225 | } |
3226 | else | |
3227 | { | |
3956db08 | 3228 | if (sign > 0) |
e5cb08ac | 3229 | switch (size) |
3e73aa7c JH |
3230 | { |
3231 | case 4: return BFD_RELOC_X86_64_32S; | |
3232 | } | |
3233 | else | |
3234 | switch (size) | |
3235 | { | |
3236 | case 1: return BFD_RELOC_8; | |
3237 | case 2: return BFD_RELOC_16; | |
3238 | case 4: return BFD_RELOC_32; | |
3239 | case 8: return BFD_RELOC_64; | |
3240 | } | |
3956db08 JB |
3241 | as_bad (_("cannot do %s %u byte relocation"), |
3242 | sign > 0 ? "signed" : "unsigned", size); | |
252b5132 RH |
3243 | } |
3244 | ||
0cc9e1d3 | 3245 | return NO_RELOC; |
252b5132 RH |
3246 | } |
3247 | ||
47926f60 KH |
3248 | /* Here we decide which fixups can be adjusted to make them relative to |
3249 | the beginning of the section instead of the symbol. Basically we need | |
3250 | to make sure that the dynamic relocations are done correctly, so in | |
3251 | some cases we force the original symbol to be used. */ | |
3252 | ||
252b5132 | 3253 | int |
e3bb37b5 | 3254 | tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) |
252b5132 | 3255 | { |
6d249963 | 3256 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 3257 | if (!IS_ELF) |
31312f95 AM |
3258 | return 1; |
3259 | ||
a161fe53 AM |
3260 | /* Don't adjust pc-relative references to merge sections in 64-bit |
3261 | mode. */ | |
3262 | if (use_rela_relocations | |
3263 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 | |
3264 | && fixP->fx_pcrel) | |
252b5132 | 3265 | return 0; |
31312f95 | 3266 | |
8d01d9a9 AJ |
3267 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
3268 | and changed later by validate_fix. */ | |
3269 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol | |
3270 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) | |
3271 | return 0; | |
3272 | ||
8fd4256d L |
3273 | /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol |
3274 | for size relocations. */ | |
3275 | if (fixP->fx_r_type == BFD_RELOC_SIZE32 | |
3276 | || fixP->fx_r_type == BFD_RELOC_SIZE64 | |
3277 | || fixP->fx_r_type == BFD_RELOC_386_GOTOFF | |
252b5132 RH |
3278 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 |
3279 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 | |
02a86693 | 3280 | || fixP->fx_r_type == BFD_RELOC_386_GOT32X |
13ae64f3 JJ |
3281 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
3282 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM | |
3283 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 | |
3284 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 | |
37e55690 JJ |
3285 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
3286 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE | |
13ae64f3 JJ |
3287 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
3288 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE | |
67a4f2b7 AO |
3289 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC |
3290 | || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL | |
3e73aa7c JH |
3291 | || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 |
3292 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 | |
80b3ee89 | 3293 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
56ceb5b5 L |
3294 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX |
3295 | || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX | |
bffbf940 JJ |
3296 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
3297 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD | |
3298 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 | |
d6ab8113 | 3299 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 |
bffbf940 JJ |
3300 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF |
3301 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 | |
d6ab8113 JB |
3302 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 |
3303 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 | |
67a4f2b7 AO |
3304 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
3305 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL | |
252b5132 RH |
3306 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
3307 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
3308 | return 0; | |
31312f95 | 3309 | #endif |
252b5132 RH |
3310 | return 1; |
3311 | } | |
252b5132 | 3312 | |
b4cac588 | 3313 | static int |
e3bb37b5 | 3314 | intel_float_operand (const char *mnemonic) |
252b5132 | 3315 | { |
9306ca4a JB |
3316 | /* Note that the value returned is meaningful only for opcodes with (memory) |
3317 | operands, hence the code here is free to improperly handle opcodes that | |
3318 | have no operands (for better performance and smaller code). */ | |
3319 | ||
3320 | if (mnemonic[0] != 'f') | |
3321 | return 0; /* non-math */ | |
3322 | ||
3323 | switch (mnemonic[1]) | |
3324 | { | |
3325 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and | |
3326 | the fs segment override prefix not currently handled because no | |
3327 | call path can make opcodes without operands get here */ | |
3328 | case 'i': | |
3329 | return 2 /* integer op */; | |
3330 | case 'l': | |
3331 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) | |
3332 | return 3; /* fldcw/fldenv */ | |
3333 | break; | |
3334 | case 'n': | |
3335 | if (mnemonic[2] != 'o' /* fnop */) | |
3336 | return 3; /* non-waiting control op */ | |
3337 | break; | |
3338 | case 'r': | |
3339 | if (mnemonic[2] == 's') | |
3340 | return 3; /* frstor/frstpm */ | |
3341 | break; | |
3342 | case 's': | |
3343 | if (mnemonic[2] == 'a') | |
3344 | return 3; /* fsave */ | |
3345 | if (mnemonic[2] == 't') | |
3346 | { | |
3347 | switch (mnemonic[3]) | |
3348 | { | |
3349 | case 'c': /* fstcw */ | |
3350 | case 'd': /* fstdw */ | |
3351 | case 'e': /* fstenv */ | |
3352 | case 's': /* fsts[gw] */ | |
3353 | return 3; | |
3354 | } | |
3355 | } | |
3356 | break; | |
3357 | case 'x': | |
3358 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') | |
3359 | return 0; /* fxsave/fxrstor are not really math ops */ | |
3360 | break; | |
3361 | } | |
252b5132 | 3362 | |
9306ca4a | 3363 | return 1; |
252b5132 RH |
3364 | } |
3365 | ||
c0f3af97 L |
3366 | /* Build the VEX prefix. */ |
3367 | ||
3368 | static void | |
d3ce72d0 | 3369 | build_vex_prefix (const insn_template *t) |
c0f3af97 L |
3370 | { |
3371 | unsigned int register_specifier; | |
3372 | unsigned int implied_prefix; | |
3373 | unsigned int vector_length; | |
03751133 | 3374 | unsigned int w; |
c0f3af97 L |
3375 | |
3376 | /* Check register specifier. */ | |
3377 | if (i.vex.register_specifier) | |
43234a1e L |
3378 | { |
3379 | register_specifier = | |
3380 | ~register_number (i.vex.register_specifier) & 0xf; | |
3381 | gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0); | |
3382 | } | |
c0f3af97 L |
3383 | else |
3384 | register_specifier = 0xf; | |
3385 | ||
79f0fa25 L |
3386 | /* Use 2-byte VEX prefix by swapping destination and source operand |
3387 | if there are more than 1 register operand. */ | |
3388 | if (i.reg_operands > 1 | |
3389 | && i.vec_encoding != vex_encoding_vex3 | |
86fa6981 | 3390 | && i.dir_encoding == dir_encoding_default |
fa99fab2 | 3391 | && i.operands == i.reg_operands |
dbbc8b7e | 3392 | && operand_type_equal (&i.types[0], &i.types[i.operands - 1]) |
7f399153 | 3393 | && i.tm.opcode_modifier.vexopcode == VEX0F |
dbbc8b7e | 3394 | && (i.tm.opcode_modifier.load || i.tm.opcode_modifier.d) |
fa99fab2 L |
3395 | && i.rex == REX_B) |
3396 | { | |
3397 | unsigned int xchg = i.operands - 1; | |
3398 | union i386_op temp_op; | |
3399 | i386_operand_type temp_type; | |
3400 | ||
3401 | temp_type = i.types[xchg]; | |
3402 | i.types[xchg] = i.types[0]; | |
3403 | i.types[0] = temp_type; | |
3404 | temp_op = i.op[xchg]; | |
3405 | i.op[xchg] = i.op[0]; | |
3406 | i.op[0] = temp_op; | |
3407 | ||
9c2799c2 | 3408 | gas_assert (i.rm.mode == 3); |
fa99fab2 L |
3409 | |
3410 | i.rex = REX_R; | |
3411 | xchg = i.rm.regmem; | |
3412 | i.rm.regmem = i.rm.reg; | |
3413 | i.rm.reg = xchg; | |
3414 | ||
dbbc8b7e JB |
3415 | if (i.tm.opcode_modifier.d) |
3416 | i.tm.base_opcode ^= (i.tm.base_opcode & 0xee) != 0x6e | |
3417 | ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD; | |
3418 | else /* Use the next insn. */ | |
3419 | i.tm = t[1]; | |
fa99fab2 L |
3420 | } |
3421 | ||
539f890d L |
3422 | if (i.tm.opcode_modifier.vex == VEXScalar) |
3423 | vector_length = avxscalar; | |
10c17abd JB |
3424 | else if (i.tm.opcode_modifier.vex == VEX256) |
3425 | vector_length = 1; | |
539f890d | 3426 | else |
10c17abd | 3427 | { |
56522fc5 | 3428 | unsigned int op; |
10c17abd | 3429 | |
c7213af9 L |
3430 | /* Determine vector length from the last multi-length vector |
3431 | operand. */ | |
10c17abd | 3432 | vector_length = 0; |
56522fc5 | 3433 | for (op = t->operands; op--;) |
10c17abd JB |
3434 | if (t->operand_types[op].bitfield.xmmword |
3435 | && t->operand_types[op].bitfield.ymmword | |
3436 | && i.types[op].bitfield.ymmword) | |
3437 | { | |
3438 | vector_length = 1; | |
3439 | break; | |
3440 | } | |
3441 | } | |
c0f3af97 L |
3442 | |
3443 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
3444 | { | |
3445 | case 0: | |
3446 | implied_prefix = 0; | |
3447 | break; | |
3448 | case DATA_PREFIX_OPCODE: | |
3449 | implied_prefix = 1; | |
3450 | break; | |
3451 | case REPE_PREFIX_OPCODE: | |
3452 | implied_prefix = 2; | |
3453 | break; | |
3454 | case REPNE_PREFIX_OPCODE: | |
3455 | implied_prefix = 3; | |
3456 | break; | |
3457 | default: | |
3458 | abort (); | |
3459 | } | |
3460 | ||
03751133 L |
3461 | /* Check the REX.W bit and VEXW. */ |
3462 | if (i.tm.opcode_modifier.vexw == VEXWIG) | |
3463 | w = (vexwig == vexw1 || (i.rex & REX_W)) ? 1 : 0; | |
3464 | else if (i.tm.opcode_modifier.vexw) | |
3465 | w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0; | |
3466 | else | |
931d03b7 | 3467 | w = (flag_code == CODE_64BIT ? i.rex & REX_W : vexwig == vexw1) ? 1 : 0; |
03751133 | 3468 | |
c0f3af97 | 3469 | /* Use 2-byte VEX prefix if possible. */ |
03751133 L |
3470 | if (w == 0 |
3471 | && i.vec_encoding != vex_encoding_vex3 | |
86fa6981 | 3472 | && i.tm.opcode_modifier.vexopcode == VEX0F |
c0f3af97 L |
3473 | && (i.rex & (REX_W | REX_X | REX_B)) == 0) |
3474 | { | |
3475 | /* 2-byte VEX prefix. */ | |
3476 | unsigned int r; | |
3477 | ||
3478 | i.vex.length = 2; | |
3479 | i.vex.bytes[0] = 0xc5; | |
3480 | ||
3481 | /* Check the REX.R bit. */ | |
3482 | r = (i.rex & REX_R) ? 0 : 1; | |
3483 | i.vex.bytes[1] = (r << 7 | |
3484 | | register_specifier << 3 | |
3485 | | vector_length << 2 | |
3486 | | implied_prefix); | |
3487 | } | |
3488 | else | |
3489 | { | |
3490 | /* 3-byte VEX prefix. */ | |
03751133 | 3491 | unsigned int m; |
c0f3af97 | 3492 | |
f88c9eb0 | 3493 | i.vex.length = 3; |
f88c9eb0 | 3494 | |
7f399153 | 3495 | switch (i.tm.opcode_modifier.vexopcode) |
5dd85c99 | 3496 | { |
7f399153 L |
3497 | case VEX0F: |
3498 | m = 0x1; | |
80de6e00 | 3499 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3500 | break; |
3501 | case VEX0F38: | |
3502 | m = 0x2; | |
80de6e00 | 3503 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3504 | break; |
3505 | case VEX0F3A: | |
3506 | m = 0x3; | |
80de6e00 | 3507 | i.vex.bytes[0] = 0xc4; |
7f399153 L |
3508 | break; |
3509 | case XOP08: | |
5dd85c99 SP |
3510 | m = 0x8; |
3511 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3512 | break; |
3513 | case XOP09: | |
f88c9eb0 SP |
3514 | m = 0x9; |
3515 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3516 | break; |
3517 | case XOP0A: | |
f88c9eb0 SP |
3518 | m = 0xa; |
3519 | i.vex.bytes[0] = 0x8f; | |
7f399153 L |
3520 | break; |
3521 | default: | |
3522 | abort (); | |
f88c9eb0 | 3523 | } |
c0f3af97 | 3524 | |
c0f3af97 L |
3525 | /* The high 3 bits of the second VEX byte are 1's compliment |
3526 | of RXB bits from REX. */ | |
3527 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
3528 | ||
c0f3af97 L |
3529 | i.vex.bytes[2] = (w << 7 |
3530 | | register_specifier << 3 | |
3531 | | vector_length << 2 | |
3532 | | implied_prefix); | |
3533 | } | |
3534 | } | |
3535 | ||
e771e7c9 JB |
3536 | static INLINE bfd_boolean |
3537 | is_evex_encoding (const insn_template *t) | |
3538 | { | |
7091c612 | 3539 | return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift |
e771e7c9 JB |
3540 | || t->opcode_modifier.broadcast || t->opcode_modifier.masking |
3541 | || t->opcode_modifier.staticrounding || t->opcode_modifier.sae; | |
3542 | } | |
3543 | ||
7a8655d2 JB |
3544 | static INLINE bfd_boolean |
3545 | is_any_vex_encoding (const insn_template *t) | |
3546 | { | |
3547 | return t->opcode_modifier.vex || t->opcode_modifier.vexopcode | |
3548 | || is_evex_encoding (t); | |
3549 | } | |
3550 | ||
43234a1e L |
3551 | /* Build the EVEX prefix. */ |
3552 | ||
3553 | static void | |
3554 | build_evex_prefix (void) | |
3555 | { | |
3556 | unsigned int register_specifier; | |
3557 | unsigned int implied_prefix; | |
3558 | unsigned int m, w; | |
3559 | rex_byte vrex_used = 0; | |
3560 | ||
3561 | /* Check register specifier. */ | |
3562 | if (i.vex.register_specifier) | |
3563 | { | |
3564 | gas_assert ((i.vrex & REX_X) == 0); | |
3565 | ||
3566 | register_specifier = i.vex.register_specifier->reg_num; | |
3567 | if ((i.vex.register_specifier->reg_flags & RegRex)) | |
3568 | register_specifier += 8; | |
3569 | /* The upper 16 registers are encoded in the fourth byte of the | |
3570 | EVEX prefix. */ | |
3571 | if (!(i.vex.register_specifier->reg_flags & RegVRex)) | |
3572 | i.vex.bytes[3] = 0x8; | |
3573 | register_specifier = ~register_specifier & 0xf; | |
3574 | } | |
3575 | else | |
3576 | { | |
3577 | register_specifier = 0xf; | |
3578 | ||
3579 | /* Encode upper 16 vector index register in the fourth byte of | |
3580 | the EVEX prefix. */ | |
3581 | if (!(i.vrex & REX_X)) | |
3582 | i.vex.bytes[3] = 0x8; | |
3583 | else | |
3584 | vrex_used |= REX_X; | |
3585 | } | |
3586 | ||
3587 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
3588 | { | |
3589 | case 0: | |
3590 | implied_prefix = 0; | |
3591 | break; | |
3592 | case DATA_PREFIX_OPCODE: | |
3593 | implied_prefix = 1; | |
3594 | break; | |
3595 | case REPE_PREFIX_OPCODE: | |
3596 | implied_prefix = 2; | |
3597 | break; | |
3598 | case REPNE_PREFIX_OPCODE: | |
3599 | implied_prefix = 3; | |
3600 | break; | |
3601 | default: | |
3602 | abort (); | |
3603 | } | |
3604 | ||
3605 | /* 4 byte EVEX prefix. */ | |
3606 | i.vex.length = 4; | |
3607 | i.vex.bytes[0] = 0x62; | |
3608 | ||
3609 | /* mmmm bits. */ | |
3610 | switch (i.tm.opcode_modifier.vexopcode) | |
3611 | { | |
3612 | case VEX0F: | |
3613 | m = 1; | |
3614 | break; | |
3615 | case VEX0F38: | |
3616 | m = 2; | |
3617 | break; | |
3618 | case VEX0F3A: | |
3619 | m = 3; | |
3620 | break; | |
3621 | default: | |
3622 | abort (); | |
3623 | break; | |
3624 | } | |
3625 | ||
3626 | /* The high 3 bits of the second EVEX byte are 1's compliment of RXB | |
3627 | bits from REX. */ | |
3628 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
3629 | ||
3630 | /* The fifth bit of the second EVEX byte is 1's compliment of the | |
3631 | REX_R bit in VREX. */ | |
3632 | if (!(i.vrex & REX_R)) | |
3633 | i.vex.bytes[1] |= 0x10; | |
3634 | else | |
3635 | vrex_used |= REX_R; | |
3636 | ||
3637 | if ((i.reg_operands + i.imm_operands) == i.operands) | |
3638 | { | |
3639 | /* When all operands are registers, the REX_X bit in REX is not | |
3640 | used. We reuse it to encode the upper 16 registers, which is | |
3641 | indicated by the REX_B bit in VREX. The REX_X bit is encoded | |
3642 | as 1's compliment. */ | |
3643 | if ((i.vrex & REX_B)) | |
3644 | { | |
3645 | vrex_used |= REX_B; | |
3646 | i.vex.bytes[1] &= ~0x40; | |
3647 | } | |
3648 | } | |
3649 | ||
3650 | /* EVEX instructions shouldn't need the REX prefix. */ | |
3651 | i.vrex &= ~vrex_used; | |
3652 | gas_assert (i.vrex == 0); | |
3653 | ||
6865c043 L |
3654 | /* Check the REX.W bit and VEXW. */ |
3655 | if (i.tm.opcode_modifier.vexw == VEXWIG) | |
3656 | w = (evexwig == evexw1 || (i.rex & REX_W)) ? 1 : 0; | |
3657 | else if (i.tm.opcode_modifier.vexw) | |
3658 | w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0; | |
3659 | else | |
931d03b7 | 3660 | w = (flag_code == CODE_64BIT ? i.rex & REX_W : evexwig == evexw1) ? 1 : 0; |
43234a1e L |
3661 | |
3662 | /* Encode the U bit. */ | |
3663 | implied_prefix |= 0x4; | |
3664 | ||
3665 | /* The third byte of the EVEX prefix. */ | |
3666 | i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix); | |
3667 | ||
3668 | /* The fourth byte of the EVEX prefix. */ | |
3669 | /* The zeroing-masking bit. */ | |
3670 | if (i.mask && i.mask->zeroing) | |
3671 | i.vex.bytes[3] |= 0x80; | |
3672 | ||
3673 | /* Don't always set the broadcast bit if there is no RC. */ | |
3674 | if (!i.rounding) | |
3675 | { | |
3676 | /* Encode the vector length. */ | |
3677 | unsigned int vec_length; | |
3678 | ||
e771e7c9 JB |
3679 | if (!i.tm.opcode_modifier.evex |
3680 | || i.tm.opcode_modifier.evex == EVEXDYN) | |
3681 | { | |
56522fc5 | 3682 | unsigned int op; |
e771e7c9 | 3683 | |
c7213af9 L |
3684 | /* Determine vector length from the last multi-length vector |
3685 | operand. */ | |
e771e7c9 | 3686 | vec_length = 0; |
56522fc5 | 3687 | for (op = i.operands; op--;) |
e771e7c9 JB |
3688 | if (i.tm.operand_types[op].bitfield.xmmword |
3689 | + i.tm.operand_types[op].bitfield.ymmword | |
3690 | + i.tm.operand_types[op].bitfield.zmmword > 1) | |
3691 | { | |
3692 | if (i.types[op].bitfield.zmmword) | |
c7213af9 L |
3693 | { |
3694 | i.tm.opcode_modifier.evex = EVEX512; | |
3695 | break; | |
3696 | } | |
e771e7c9 | 3697 | else if (i.types[op].bitfield.ymmword) |
c7213af9 L |
3698 | { |
3699 | i.tm.opcode_modifier.evex = EVEX256; | |
3700 | break; | |
3701 | } | |
e771e7c9 | 3702 | else if (i.types[op].bitfield.xmmword) |
c7213af9 L |
3703 | { |
3704 | i.tm.opcode_modifier.evex = EVEX128; | |
3705 | break; | |
3706 | } | |
625cbd7a JB |
3707 | else if (i.broadcast && (int) op == i.broadcast->operand) |
3708 | { | |
4a1b91ea | 3709 | switch (i.broadcast->bytes) |
625cbd7a JB |
3710 | { |
3711 | case 64: | |
3712 | i.tm.opcode_modifier.evex = EVEX512; | |
3713 | break; | |
3714 | case 32: | |
3715 | i.tm.opcode_modifier.evex = EVEX256; | |
3716 | break; | |
3717 | case 16: | |
3718 | i.tm.opcode_modifier.evex = EVEX128; | |
3719 | break; | |
3720 | default: | |
c7213af9 | 3721 | abort (); |
625cbd7a | 3722 | } |
c7213af9 | 3723 | break; |
625cbd7a | 3724 | } |
e771e7c9 | 3725 | } |
c7213af9 | 3726 | |
56522fc5 | 3727 | if (op >= MAX_OPERANDS) |
c7213af9 | 3728 | abort (); |
e771e7c9 JB |
3729 | } |
3730 | ||
43234a1e L |
3731 | switch (i.tm.opcode_modifier.evex) |
3732 | { | |
3733 | case EVEXLIG: /* LL' is ignored */ | |
3734 | vec_length = evexlig << 5; | |
3735 | break; | |
3736 | case EVEX128: | |
3737 | vec_length = 0 << 5; | |
3738 | break; | |
3739 | case EVEX256: | |
3740 | vec_length = 1 << 5; | |
3741 | break; | |
3742 | case EVEX512: | |
3743 | vec_length = 2 << 5; | |
3744 | break; | |
3745 | default: | |
3746 | abort (); | |
3747 | break; | |
3748 | } | |
3749 | i.vex.bytes[3] |= vec_length; | |
3750 | /* Encode the broadcast bit. */ | |
3751 | if (i.broadcast) | |
3752 | i.vex.bytes[3] |= 0x10; | |
3753 | } | |
3754 | else | |
3755 | { | |
3756 | if (i.rounding->type != saeonly) | |
3757 | i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5); | |
3758 | else | |
d3d3c6db | 3759 | i.vex.bytes[3] |= 0x10 | (evexrcig << 5); |
43234a1e L |
3760 | } |
3761 | ||
3762 | if (i.mask && i.mask->mask) | |
3763 | i.vex.bytes[3] |= i.mask->mask->reg_num; | |
3764 | } | |
3765 | ||
65da13b5 L |
3766 | static void |
3767 | process_immext (void) | |
3768 | { | |
3769 | expressionS *exp; | |
3770 | ||
4c692bc7 JB |
3771 | if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme) |
3772 | && i.operands > 0) | |
65da13b5 | 3773 | { |
4c692bc7 JB |
3774 | /* MONITOR/MWAIT as well as SVME instructions have fixed operands |
3775 | with an opcode suffix which is coded in the same place as an | |
3776 | 8-bit immediate field would be. | |
3777 | Here we check those operands and remove them afterwards. */ | |
65da13b5 L |
3778 | unsigned int x; |
3779 | ||
3780 | for (x = 0; x < i.operands; x++) | |
4c692bc7 | 3781 | if (register_number (i.op[x].regs) != x) |
65da13b5 | 3782 | as_bad (_("can't use register '%s%s' as operand %d in '%s'."), |
1fed0ba1 L |
3783 | register_prefix, i.op[x].regs->reg_name, x + 1, |
3784 | i.tm.name); | |
3785 | ||
3786 | i.operands = 0; | |
65da13b5 L |
3787 | } |
3788 | ||
9916071f AP |
3789 | if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0) |
3790 | { | |
3791 | /* MONITORX/MWAITX instructions have fixed operands with an opcode | |
3792 | suffix which is coded in the same place as an 8-bit immediate | |
3793 | field would be. | |
3794 | Here we check those operands and remove them afterwards. */ | |
3795 | unsigned int x; | |
3796 | ||
3797 | if (i.operands != 3) | |
3798 | abort(); | |
3799 | ||
3800 | for (x = 0; x < 2; x++) | |
3801 | if (register_number (i.op[x].regs) != x) | |
3802 | goto bad_register_operand; | |
3803 | ||
3804 | /* Check for third operand for mwaitx/monitorx insn. */ | |
3805 | if (register_number (i.op[x].regs) | |
3806 | != (x + (i.tm.extension_opcode == 0xfb))) | |
3807 | { | |
3808 | bad_register_operand: | |
3809 | as_bad (_("can't use register '%s%s' as operand %d in '%s'."), | |
3810 | register_prefix, i.op[x].regs->reg_name, x+1, | |
3811 | i.tm.name); | |
3812 | } | |
3813 | ||
3814 | i.operands = 0; | |
3815 | } | |
3816 | ||
c0f3af97 | 3817 | /* These AMD 3DNow! and SSE2 instructions have an opcode suffix |
65da13b5 L |
3818 | which is coded in the same place as an 8-bit immediate field |
3819 | would be. Here we fake an 8-bit immediate operand from the | |
3820 | opcode suffix stored in tm.extension_opcode. | |
3821 | ||
c1e679ec | 3822 | AVX instructions also use this encoding, for some of |
c0f3af97 | 3823 | 3 argument instructions. */ |
65da13b5 | 3824 | |
43234a1e | 3825 | gas_assert (i.imm_operands <= 1 |
7ab9ffdd | 3826 | && (i.operands <= 2 |
7a8655d2 | 3827 | || (is_any_vex_encoding (&i.tm) |
7ab9ffdd | 3828 | && i.operands <= 4))); |
65da13b5 L |
3829 | |
3830 | exp = &im_expressions[i.imm_operands++]; | |
3831 | i.op[i.operands].imms = exp; | |
3832 | i.types[i.operands] = imm8; | |
3833 | i.operands++; | |
3834 | exp->X_op = O_constant; | |
3835 | exp->X_add_number = i.tm.extension_opcode; | |
3836 | i.tm.extension_opcode = None; | |
3837 | } | |
3838 | ||
42164a71 L |
3839 | |
3840 | static int | |
3841 | check_hle (void) | |
3842 | { | |
3843 | switch (i.tm.opcode_modifier.hleprefixok) | |
3844 | { | |
3845 | default: | |
3846 | abort (); | |
82c2def5 | 3847 | case HLEPrefixNone: |
165de32a L |
3848 | as_bad (_("invalid instruction `%s' after `%s'"), |
3849 | i.tm.name, i.hle_prefix); | |
42164a71 | 3850 | return 0; |
82c2def5 | 3851 | case HLEPrefixLock: |
42164a71 L |
3852 | if (i.prefix[LOCK_PREFIX]) |
3853 | return 1; | |
165de32a | 3854 | as_bad (_("missing `lock' with `%s'"), i.hle_prefix); |
42164a71 | 3855 | return 0; |
82c2def5 | 3856 | case HLEPrefixAny: |
42164a71 | 3857 | return 1; |
82c2def5 | 3858 | case HLEPrefixRelease: |
42164a71 L |
3859 | if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE) |
3860 | { | |
3861 | as_bad (_("instruction `%s' after `xacquire' not allowed"), | |
3862 | i.tm.name); | |
3863 | return 0; | |
3864 | } | |
3865 | if (i.mem_operands == 0 | |
3866 | || !operand_type_check (i.types[i.operands - 1], anymem)) | |
3867 | { | |
3868 | as_bad (_("memory destination needed for instruction `%s'" | |
3869 | " after `xrelease'"), i.tm.name); | |
3870 | return 0; | |
3871 | } | |
3872 | return 1; | |
3873 | } | |
3874 | } | |
3875 | ||
b6f8c7c4 L |
3876 | /* Try the shortest encoding by shortening operand size. */ |
3877 | ||
3878 | static void | |
3879 | optimize_encoding (void) | |
3880 | { | |
3881 | int j; | |
3882 | ||
3883 | if (optimize_for_space | |
3884 | && i.reg_operands == 1 | |
3885 | && i.imm_operands == 1 | |
3886 | && !i.types[1].bitfield.byte | |
3887 | && i.op[0].imms->X_op == O_constant | |
3888 | && fits_in_imm7 (i.op[0].imms->X_add_number) | |
3889 | && ((i.tm.base_opcode == 0xa8 | |
3890 | && i.tm.extension_opcode == None) | |
3891 | || (i.tm.base_opcode == 0xf6 | |
3892 | && i.tm.extension_opcode == 0x0))) | |
3893 | { | |
3894 | /* Optimize: -Os: | |
3895 | test $imm7, %r64/%r32/%r16 -> test $imm7, %r8 | |
3896 | */ | |
3897 | unsigned int base_regnum = i.op[1].regs->reg_num; | |
3898 | if (flag_code == CODE_64BIT || base_regnum < 4) | |
3899 | { | |
3900 | i.types[1].bitfield.byte = 1; | |
3901 | /* Ignore the suffix. */ | |
3902 | i.suffix = 0; | |
3903 | if (base_regnum >= 4 | |
3904 | && !(i.op[1].regs->reg_flags & RegRex)) | |
3905 | { | |
3906 | /* Handle SP, BP, SI and DI registers. */ | |
3907 | if (i.types[1].bitfield.word) | |
3908 | j = 16; | |
3909 | else if (i.types[1].bitfield.dword) | |
3910 | j = 32; | |
3911 | else | |
3912 | j = 48; | |
3913 | i.op[1].regs -= j; | |
3914 | } | |
3915 | } | |
3916 | } | |
3917 | else if (flag_code == CODE_64BIT | |
d3d50934 L |
3918 | && ((i.types[1].bitfield.qword |
3919 | && i.reg_operands == 1 | |
b6f8c7c4 L |
3920 | && i.imm_operands == 1 |
3921 | && i.op[0].imms->X_op == O_constant | |
3922 | && ((i.tm.base_opcode == 0xb0 | |
3923 | && i.tm.extension_opcode == None | |
3924 | && fits_in_unsigned_long (i.op[0].imms->X_add_number)) | |
3925 | || (fits_in_imm31 (i.op[0].imms->X_add_number) | |
3926 | && (((i.tm.base_opcode == 0x24 | |
3927 | || i.tm.base_opcode == 0xa8) | |
3928 | && i.tm.extension_opcode == None) | |
3929 | || (i.tm.base_opcode == 0x80 | |
3930 | && i.tm.extension_opcode == 0x4) | |
3931 | || ((i.tm.base_opcode == 0xf6 | |
3932 | || i.tm.base_opcode == 0xc6) | |
3933 | && i.tm.extension_opcode == 0x0))))) | |
d3d50934 L |
3934 | || (i.types[0].bitfield.qword |
3935 | && ((i.reg_operands == 2 | |
3936 | && i.op[0].regs == i.op[1].regs | |
3937 | && ((i.tm.base_opcode == 0x30 | |
3938 | || i.tm.base_opcode == 0x28) | |
3939 | && i.tm.extension_opcode == None)) | |
3940 | || (i.reg_operands == 1 | |
3941 | && i.operands == 1 | |
3942 | && i.tm.base_opcode == 0x30 | |
3943 | && i.tm.extension_opcode == None))))) | |
b6f8c7c4 L |
3944 | { |
3945 | /* Optimize: -O: | |
3946 | andq $imm31, %r64 -> andl $imm31, %r32 | |
3947 | testq $imm31, %r64 -> testl $imm31, %r32 | |
3948 | xorq %r64, %r64 -> xorl %r32, %r32 | |
3949 | subq %r64, %r64 -> subl %r32, %r32 | |
3950 | movq $imm31, %r64 -> movl $imm31, %r32 | |
3951 | movq $imm32, %r64 -> movl $imm32, %r32 | |
3952 | */ | |
3953 | i.tm.opcode_modifier.norex64 = 1; | |
3954 | if (i.tm.base_opcode == 0xb0 || i.tm.base_opcode == 0xc6) | |
3955 | { | |
3956 | /* Handle | |
3957 | movq $imm31, %r64 -> movl $imm31, %r32 | |
3958 | movq $imm32, %r64 -> movl $imm32, %r32 | |
3959 | */ | |
3960 | i.tm.operand_types[0].bitfield.imm32 = 1; | |
3961 | i.tm.operand_types[0].bitfield.imm32s = 0; | |
3962 | i.tm.operand_types[0].bitfield.imm64 = 0; | |
3963 | i.types[0].bitfield.imm32 = 1; | |
3964 | i.types[0].bitfield.imm32s = 0; | |
3965 | i.types[0].bitfield.imm64 = 0; | |
3966 | i.types[1].bitfield.dword = 1; | |
3967 | i.types[1].bitfield.qword = 0; | |
3968 | if (i.tm.base_opcode == 0xc6) | |
3969 | { | |
3970 | /* Handle | |
3971 | movq $imm31, %r64 -> movl $imm31, %r32 | |
3972 | */ | |
3973 | i.tm.base_opcode = 0xb0; | |
3974 | i.tm.extension_opcode = None; | |
3975 | i.tm.opcode_modifier.shortform = 1; | |
3976 | i.tm.opcode_modifier.modrm = 0; | |
3977 | } | |
3978 | } | |
3979 | } | |
99112332 | 3980 | else if (i.reg_operands == 3 |
b6f8c7c4 L |
3981 | && i.op[0].regs == i.op[1].regs |
3982 | && !i.types[2].bitfield.xmmword | |
3983 | && (i.tm.opcode_modifier.vex | |
7a69eac3 | 3984 | || ((!i.mask || i.mask->zeroing) |
b6f8c7c4 | 3985 | && !i.rounding |
e771e7c9 | 3986 | && is_evex_encoding (&i.tm) |
80c34c38 | 3987 | && (i.vec_encoding != vex_encoding_evex |
dd22218c L |
3988 | || cpu_arch_flags.bitfield.cpuavx |
3989 | || cpu_arch_isa_flags.bitfield.cpuavx | |
3990 | || cpu_arch_flags.bitfield.cpuavx512vl | |
3991 | || cpu_arch_isa_flags.bitfield.cpuavx512vl | |
80c34c38 | 3992 | || i.tm.cpu_flags.bitfield.cpuavx512vl |
7091c612 | 3993 | || (i.tm.operand_types[2].bitfield.zmmword |
dd22218c | 3994 | && i.types[2].bitfield.ymmword)))) |
b6f8c7c4 L |
3995 | && ((i.tm.base_opcode == 0x55 |
3996 | || i.tm.base_opcode == 0x6655 | |
3997 | || i.tm.base_opcode == 0x66df | |
3998 | || i.tm.base_opcode == 0x57 | |
3999 | || i.tm.base_opcode == 0x6657 | |
8305403a L |
4000 | || i.tm.base_opcode == 0x66ef |
4001 | || i.tm.base_opcode == 0x66f8 | |
4002 | || i.tm.base_opcode == 0x66f9 | |
4003 | || i.tm.base_opcode == 0x66fa | |
1424ad86 JB |
4004 | || i.tm.base_opcode == 0x66fb |
4005 | || i.tm.base_opcode == 0x42 | |
4006 | || i.tm.base_opcode == 0x6642 | |
4007 | || i.tm.base_opcode == 0x47 | |
4008 | || i.tm.base_opcode == 0x6647) | |
b6f8c7c4 L |
4009 | && i.tm.extension_opcode == None)) |
4010 | { | |
99112332 | 4011 | /* Optimize: -O1: |
8305403a L |
4012 | VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd, |
4013 | vpsubq and vpsubw: | |
b6f8c7c4 L |
4014 | EVEX VOP %zmmM, %zmmM, %zmmN |
4015 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4016 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4017 | EVEX VOP %ymmM, %ymmM, %ymmN |
4018 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4019 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4020 | VEX VOP %ymmM, %ymmM, %ymmN |
4021 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
4022 | VOP, one of vpandn and vpxor: | |
4023 | VEX VOP %ymmM, %ymmM, %ymmN | |
4024 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
4025 | VOP, one of vpandnd and vpandnq: | |
4026 | EVEX VOP %zmmM, %zmmM, %zmmN | |
4027 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4028 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4029 | EVEX VOP %ymmM, %ymmM, %ymmN |
4030 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4031 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4032 | VOP, one of vpxord and vpxorq: |
4033 | EVEX VOP %zmmM, %zmmM, %zmmN | |
4034 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4035 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4036 | EVEX VOP %ymmM, %ymmM, %ymmN |
4037 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4038 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
1424ad86 JB |
4039 | VOP, one of kxord and kxorq: |
4040 | VEX VOP %kM, %kM, %kN | |
4041 | -> VEX kxorw %kM, %kM, %kN | |
4042 | VOP, one of kandnd and kandnq: | |
4043 | VEX VOP %kM, %kM, %kN | |
4044 | -> VEX kandnw %kM, %kM, %kN | |
b6f8c7c4 | 4045 | */ |
e771e7c9 | 4046 | if (is_evex_encoding (&i.tm)) |
b6f8c7c4 | 4047 | { |
dd22218c L |
4048 | if (i.vec_encoding != vex_encoding_evex |
4049 | && (cpu_arch_flags.bitfield.cpuavx | |
4050 | || cpu_arch_isa_flags.bitfield.cpuavx)) | |
b6f8c7c4 L |
4051 | { |
4052 | i.tm.opcode_modifier.vex = VEX128; | |
4053 | i.tm.opcode_modifier.vexw = VEXW0; | |
4054 | i.tm.opcode_modifier.evex = 0; | |
4055 | } | |
99112332 L |
4056 | else if (optimize > 1 |
4057 | && (cpu_arch_flags.bitfield.cpuavx512vl | |
4058 | || cpu_arch_isa_flags.bitfield.cpuavx512vl)) | |
dd22218c L |
4059 | i.tm.opcode_modifier.evex = EVEX128; |
4060 | else | |
4061 | return; | |
b6f8c7c4 | 4062 | } |
1424ad86 JB |
4063 | else if (i.tm.operand_types[0].bitfield.regmask) |
4064 | { | |
4065 | i.tm.base_opcode &= 0xff; | |
4066 | i.tm.opcode_modifier.vexw = VEXW0; | |
4067 | } | |
b6f8c7c4 L |
4068 | else |
4069 | i.tm.opcode_modifier.vex = VEX128; | |
4070 | ||
4071 | if (i.tm.opcode_modifier.vex) | |
4072 | for (j = 0; j < 3; j++) | |
4073 | { | |
4074 | i.types[j].bitfield.xmmword = 1; | |
4075 | i.types[j].bitfield.ymmword = 0; | |
4076 | } | |
4077 | } | |
97ed31ae L |
4078 | else if ((cpu_arch_flags.bitfield.cpuavx |
4079 | || cpu_arch_isa_flags.bitfield.cpuavx) | |
4080 | && i.vec_encoding != vex_encoding_evex | |
4081 | && !i.types[0].bitfield.zmmword | |
4082 | && !i.mask | |
4083 | && is_evex_encoding (&i.tm) | |
4084 | && (i.tm.base_opcode == 0x666f | |
4085 | || (i.tm.base_opcode ^ Opcode_SIMD_IntD) == 0x666f | |
4086 | || i.tm.base_opcode == 0xf36f | |
4087 | || (i.tm.base_opcode ^ Opcode_SIMD_IntD) == 0xf36f | |
4088 | || i.tm.base_opcode == 0xf26f | |
4089 | || (i.tm.base_opcode ^ Opcode_SIMD_IntD) == 0xf26f) | |
4090 | && i.tm.extension_opcode == None) | |
4091 | { | |
4092 | /* Optimize: -O1: | |
4093 | VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, | |
4094 | vmovdqu32 and vmovdqu64: | |
4095 | EVEX VOP %xmmM, %xmmN | |
4096 | -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16) | |
4097 | EVEX VOP %ymmM, %ymmN | |
4098 | -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16) | |
4099 | EVEX VOP %xmmM, mem | |
4100 | -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16) | |
4101 | EVEX VOP %ymmM, mem | |
4102 | -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16) | |
4103 | EVEX VOP mem, %xmmN | |
4104 | -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16) | |
4105 | EVEX VOP mem, %ymmN | |
4106 | -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16) | |
4107 | */ | |
4108 | if (i.tm.base_opcode == 0xf26f) | |
4109 | i.tm.base_opcode = 0xf36f; | |
4110 | else if ((i.tm.base_opcode ^ Opcode_SIMD_IntD) == 0xf26f) | |
4111 | i.tm.base_opcode = 0xf36f ^ Opcode_SIMD_IntD; | |
4112 | i.tm.opcode_modifier.vex | |
4113 | = i.types[0].bitfield.ymmword ? VEX256 : VEX128; | |
4114 | i.tm.opcode_modifier.vexw = VEXW0; | |
4115 | i.tm.opcode_modifier.evex = 0; | |
4116 | i.tm.opcode_modifier.masking = 0; | |
4117 | i.tm.opcode_modifier.disp8memshift = 0; | |
4118 | i.memshift = 0; | |
4119 | for (j = 0; j < 2; j++) | |
4120 | if (operand_type_check (i.types[j], disp) | |
4121 | && i.op[j].disps->X_op == O_constant) | |
4122 | { | |
4123 | i.types[j].bitfield.disp8 | |
4124 | = fits_in_disp8 (i.op[j].disps->X_add_number); | |
4125 | break; | |
4126 | } | |
4127 | } | |
b6f8c7c4 L |
4128 | } |
4129 | ||
252b5132 RH |
4130 | /* This is the guts of the machine-dependent assembler. LINE points to a |
4131 | machine dependent instruction. This function is supposed to emit | |
4132 | the frags/bytes it assembles to. */ | |
4133 | ||
4134 | void | |
65da13b5 | 4135 | md_assemble (char *line) |
252b5132 | 4136 | { |
40fb9820 | 4137 | unsigned int j; |
83b16ac6 | 4138 | char mnemonic[MAX_MNEM_SIZE], mnem_suffix; |
d3ce72d0 | 4139 | const insn_template *t; |
252b5132 | 4140 | |
47926f60 | 4141 | /* Initialize globals. */ |
252b5132 RH |
4142 | memset (&i, '\0', sizeof (i)); |
4143 | for (j = 0; j < MAX_OPERANDS; j++) | |
1ae12ab7 | 4144 | i.reloc[j] = NO_RELOC; |
252b5132 RH |
4145 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
4146 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 4147 | save_stack_p = save_stack; |
252b5132 RH |
4148 | |
4149 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
4150 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 4151 | start of a (possibly prefixed) mnemonic. */ |
252b5132 | 4152 | |
29b0f896 AM |
4153 | line = parse_insn (line, mnemonic); |
4154 | if (line == NULL) | |
4155 | return; | |
83b16ac6 | 4156 | mnem_suffix = i.suffix; |
252b5132 | 4157 | |
29b0f896 | 4158 | line = parse_operands (line, mnemonic); |
ee86248c | 4159 | this_operand = -1; |
8325cc63 JB |
4160 | xfree (i.memop1_string); |
4161 | i.memop1_string = NULL; | |
29b0f896 AM |
4162 | if (line == NULL) |
4163 | return; | |
252b5132 | 4164 | |
29b0f896 AM |
4165 | /* Now we've parsed the mnemonic into a set of templates, and have the |
4166 | operands at hand. */ | |
4167 | ||
4168 | /* All intel opcodes have reversed operands except for "bound" and | |
4169 | "enter". We also don't reverse intersegment "jmp" and "call" | |
4170 | instructions with 2 immediate operands so that the immediate segment | |
050dfa73 | 4171 | precedes the offset, as it does when in AT&T mode. */ |
4d456e3d L |
4172 | if (intel_syntax |
4173 | && i.operands > 1 | |
29b0f896 | 4174 | && (strcmp (mnemonic, "bound") != 0) |
30123838 | 4175 | && (strcmp (mnemonic, "invlpga") != 0) |
40fb9820 L |
4176 | && !(operand_type_check (i.types[0], imm) |
4177 | && operand_type_check (i.types[1], imm))) | |
29b0f896 AM |
4178 | swap_operands (); |
4179 | ||
ec56d5c0 JB |
4180 | /* The order of the immediates should be reversed |
4181 | for 2 immediates extrq and insertq instructions */ | |
4182 | if (i.imm_operands == 2 | |
4183 | && (strcmp (mnemonic, "extrq") == 0 | |
4184 | || strcmp (mnemonic, "insertq") == 0)) | |
4185 | swap_2_operands (0, 1); | |
4186 | ||
29b0f896 AM |
4187 | if (i.imm_operands) |
4188 | optimize_imm (); | |
4189 | ||
b300c311 L |
4190 | /* Don't optimize displacement for movabs since it only takes 64bit |
4191 | displacement. */ | |
4192 | if (i.disp_operands | |
a501d77e | 4193 | && i.disp_encoding != disp_encoding_32bit |
862be3fb L |
4194 | && (flag_code != CODE_64BIT |
4195 | || strcmp (mnemonic, "movabs") != 0)) | |
4196 | optimize_disp (); | |
29b0f896 AM |
4197 | |
4198 | /* Next, we find a template that matches the given insn, | |
4199 | making sure the overlap of the given operands types is consistent | |
4200 | with the template operand types. */ | |
252b5132 | 4201 | |
83b16ac6 | 4202 | if (!(t = match_template (mnem_suffix))) |
29b0f896 | 4203 | return; |
252b5132 | 4204 | |
7bab8ab5 | 4205 | if (sse_check != check_none |
81f8a913 | 4206 | && !i.tm.opcode_modifier.noavx |
6e3e5c9e | 4207 | && !i.tm.cpu_flags.bitfield.cpuavx |
daf50ae7 L |
4208 | && (i.tm.cpu_flags.bitfield.cpusse |
4209 | || i.tm.cpu_flags.bitfield.cpusse2 | |
4210 | || i.tm.cpu_flags.bitfield.cpusse3 | |
4211 | || i.tm.cpu_flags.bitfield.cpussse3 | |
4212 | || i.tm.cpu_flags.bitfield.cpusse4_1 | |
6e3e5c9e JB |
4213 | || i.tm.cpu_flags.bitfield.cpusse4_2 |
4214 | || i.tm.cpu_flags.bitfield.cpupclmul | |
4215 | || i.tm.cpu_flags.bitfield.cpuaes | |
4216 | || i.tm.cpu_flags.bitfield.cpugfni)) | |
daf50ae7 | 4217 | { |
7bab8ab5 | 4218 | (sse_check == check_warning |
daf50ae7 L |
4219 | ? as_warn |
4220 | : as_bad) (_("SSE instruction `%s' is used"), i.tm.name); | |
4221 | } | |
4222 | ||
321fd21e L |
4223 | /* Zap movzx and movsx suffix. The suffix has been set from |
4224 | "word ptr" or "byte ptr" on the source operand in Intel syntax | |
4225 | or extracted from mnemonic in AT&T syntax. But we'll use | |
4226 | the destination register to choose the suffix for encoding. */ | |
4227 | if ((i.tm.base_opcode & ~9) == 0x0fb6) | |
cd61ebfe | 4228 | { |
321fd21e L |
4229 | /* In Intel syntax, there must be a suffix. In AT&T syntax, if |
4230 | there is no suffix, the default will be byte extension. */ | |
4231 | if (i.reg_operands != 2 | |
4232 | && !i.suffix | |
7ab9ffdd | 4233 | && intel_syntax) |
321fd21e L |
4234 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); |
4235 | ||
4236 | i.suffix = 0; | |
cd61ebfe | 4237 | } |
24eab124 | 4238 | |
40fb9820 | 4239 | if (i.tm.opcode_modifier.fwait) |
29b0f896 AM |
4240 | if (!add_prefix (FWAIT_OPCODE)) |
4241 | return; | |
252b5132 | 4242 | |
d5de92cf L |
4243 | /* Check if REP prefix is OK. */ |
4244 | if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok) | |
4245 | { | |
4246 | as_bad (_("invalid instruction `%s' after `%s'"), | |
4247 | i.tm.name, i.rep_prefix); | |
4248 | return; | |
4249 | } | |
4250 | ||
c1ba0266 L |
4251 | /* Check for lock without a lockable instruction. Destination operand |
4252 | must be memory unless it is xchg (0x86). */ | |
c32fa91d L |
4253 | if (i.prefix[LOCK_PREFIX] |
4254 | && (!i.tm.opcode_modifier.islockable | |
c1ba0266 L |
4255 | || i.mem_operands == 0 |
4256 | || (i.tm.base_opcode != 0x86 | |
4257 | && !operand_type_check (i.types[i.operands - 1], anymem)))) | |
c32fa91d L |
4258 | { |
4259 | as_bad (_("expecting lockable instruction after `lock'")); | |
4260 | return; | |
4261 | } | |
4262 | ||
7a8655d2 JB |
4263 | /* Check for data size prefix on VEX/XOP/EVEX encoded insns. */ |
4264 | if (i.prefix[DATA_PREFIX] && is_any_vex_encoding (&i.tm)) | |
4265 | { | |
4266 | as_bad (_("data size prefix invalid with `%s'"), i.tm.name); | |
4267 | return; | |
4268 | } | |
4269 | ||
42164a71 | 4270 | /* Check if HLE prefix is OK. */ |
165de32a | 4271 | if (i.hle_prefix && !check_hle ()) |
42164a71 L |
4272 | return; |
4273 | ||
7e8b059b L |
4274 | /* Check BND prefix. */ |
4275 | if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok) | |
4276 | as_bad (_("expecting valid branch instruction after `bnd'")); | |
4277 | ||
04ef582a | 4278 | /* Check NOTRACK prefix. */ |
9fef80d6 L |
4279 | if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok) |
4280 | as_bad (_("expecting indirect branch instruction after `notrack'")); | |
04ef582a | 4281 | |
327e8c42 JB |
4282 | if (i.tm.cpu_flags.bitfield.cpumpx) |
4283 | { | |
4284 | if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX]) | |
4285 | as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions.")); | |
4286 | else if (flag_code != CODE_16BIT | |
4287 | ? i.prefix[ADDR_PREFIX] | |
4288 | : i.mem_operands && !i.prefix[ADDR_PREFIX]) | |
4289 | as_bad (_("16-bit address isn't allowed in MPX instructions")); | |
4290 | } | |
7e8b059b L |
4291 | |
4292 | /* Insert BND prefix. */ | |
76d3a78a JB |
4293 | if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok) |
4294 | { | |
4295 | if (!i.prefix[BND_PREFIX]) | |
4296 | add_prefix (BND_PREFIX_OPCODE); | |
4297 | else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE) | |
4298 | { | |
4299 | as_warn (_("replacing `rep'/`repe' prefix by `bnd'")); | |
4300 | i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE; | |
4301 | } | |
4302 | } | |
7e8b059b | 4303 | |
29b0f896 | 4304 | /* Check string instruction segment overrides. */ |
40fb9820 | 4305 | if (i.tm.opcode_modifier.isstring && i.mem_operands != 0) |
29b0f896 AM |
4306 | { |
4307 | if (!check_string ()) | |
5dd0794d | 4308 | return; |
fc0763e6 | 4309 | i.disp_operands = 0; |
29b0f896 | 4310 | } |
5dd0794d | 4311 | |
b6f8c7c4 L |
4312 | if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize) |
4313 | optimize_encoding (); | |
4314 | ||
29b0f896 AM |
4315 | if (!process_suffix ()) |
4316 | return; | |
e413e4e9 | 4317 | |
bc0844ae L |
4318 | /* Update operand types. */ |
4319 | for (j = 0; j < i.operands; j++) | |
4320 | i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]); | |
4321 | ||
29b0f896 AM |
4322 | /* Make still unresolved immediate matches conform to size of immediate |
4323 | given in i.suffix. */ | |
4324 | if (!finalize_imm ()) | |
4325 | return; | |
252b5132 | 4326 | |
40fb9820 | 4327 | if (i.types[0].bitfield.imm1) |
29b0f896 | 4328 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 | 4329 | |
9afe6eb8 L |
4330 | /* We only need to check those implicit registers for instructions |
4331 | with 3 operands or less. */ | |
4332 | if (i.operands <= 3) | |
4333 | for (j = 0; j < i.operands; j++) | |
4334 | if (i.types[j].bitfield.inoutportreg | |
4335 | || i.types[j].bitfield.shiftcount | |
1b54b8d7 | 4336 | || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword)) |
9afe6eb8 | 4337 | i.reg_operands--; |
40fb9820 | 4338 | |
c0f3af97 L |
4339 | /* ImmExt should be processed after SSE2AVX. */ |
4340 | if (!i.tm.opcode_modifier.sse2avx | |
4341 | && i.tm.opcode_modifier.immext) | |
65da13b5 | 4342 | process_immext (); |
252b5132 | 4343 | |
29b0f896 AM |
4344 | /* For insns with operands there are more diddles to do to the opcode. */ |
4345 | if (i.operands) | |
4346 | { | |
4347 | if (!process_operands ()) | |
4348 | return; | |
4349 | } | |
40fb9820 | 4350 | else if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 AM |
4351 | { |
4352 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ | |
4353 | as_warn (_("translating to `%sp'"), i.tm.name); | |
4354 | } | |
252b5132 | 4355 | |
7a8655d2 | 4356 | if (is_any_vex_encoding (&i.tm)) |
9e5e5283 L |
4357 | { |
4358 | if (flag_code == CODE_16BIT) | |
4359 | { | |
4360 | as_bad (_("instruction `%s' isn't supported in 16-bit mode."), | |
4361 | i.tm.name); | |
4362 | return; | |
4363 | } | |
c0f3af97 | 4364 | |
9e5e5283 L |
4365 | if (i.tm.opcode_modifier.vex) |
4366 | build_vex_prefix (t); | |
4367 | else | |
4368 | build_evex_prefix (); | |
4369 | } | |
43234a1e | 4370 | |
5dd85c99 SP |
4371 | /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4 |
4372 | instructions may define INT_OPCODE as well, so avoid this corner | |
4373 | case for those instructions that use MODRM. */ | |
4374 | if (i.tm.base_opcode == INT_OPCODE | |
a6461c02 SP |
4375 | && !i.tm.opcode_modifier.modrm |
4376 | && i.op[0].imms->X_add_number == 3) | |
29b0f896 AM |
4377 | { |
4378 | i.tm.base_opcode = INT3_OPCODE; | |
4379 | i.imm_operands = 0; | |
4380 | } | |
252b5132 | 4381 | |
40fb9820 L |
4382 | if ((i.tm.opcode_modifier.jump |
4383 | || i.tm.opcode_modifier.jumpbyte | |
4384 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 AM |
4385 | && i.op[0].disps->X_op == O_constant) |
4386 | { | |
4387 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
4388 | the absolute address given by the constant. Since ix86 jumps and | |
4389 | calls are pc relative, we need to generate a reloc. */ | |
4390 | i.op[0].disps->X_add_symbol = &abs_symbol; | |
4391 | i.op[0].disps->X_op = O_symbol; | |
4392 | } | |
252b5132 | 4393 | |
40fb9820 | 4394 | if (i.tm.opcode_modifier.rex64) |
161a04f6 | 4395 | i.rex |= REX_W; |
252b5132 | 4396 | |
29b0f896 AM |
4397 | /* For 8 bit registers we need an empty rex prefix. Also if the |
4398 | instruction already has a prefix, we need to convert old | |
4399 | registers to new ones. */ | |
773f551c | 4400 | |
dc821c5f | 4401 | if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte |
29b0f896 | 4402 | && (i.op[0].regs->reg_flags & RegRex64) != 0) |
dc821c5f | 4403 | || (i.types[1].bitfield.reg && i.types[1].bitfield.byte |
29b0f896 | 4404 | && (i.op[1].regs->reg_flags & RegRex64) != 0) |
dc821c5f JB |
4405 | || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte) |
4406 | || (i.types[1].bitfield.reg && i.types[1].bitfield.byte)) | |
29b0f896 AM |
4407 | && i.rex != 0)) |
4408 | { | |
4409 | int x; | |
726c5dcd | 4410 | |
29b0f896 AM |
4411 | i.rex |= REX_OPCODE; |
4412 | for (x = 0; x < 2; x++) | |
4413 | { | |
4414 | /* Look for 8 bit operand that uses old registers. */ | |
dc821c5f | 4415 | if (i.types[x].bitfield.reg && i.types[x].bitfield.byte |
29b0f896 | 4416 | && (i.op[x].regs->reg_flags & RegRex64) == 0) |
773f551c | 4417 | { |
29b0f896 AM |
4418 | /* In case it is "hi" register, give up. */ |
4419 | if (i.op[x].regs->reg_num > 3) | |
a540244d | 4420 | as_bad (_("can't encode register '%s%s' in an " |
4eed87de | 4421 | "instruction requiring REX prefix."), |
a540244d | 4422 | register_prefix, i.op[x].regs->reg_name); |
773f551c | 4423 | |
29b0f896 AM |
4424 | /* Otherwise it is equivalent to the extended register. |
4425 | Since the encoding doesn't change this is merely | |
4426 | cosmetic cleanup for debug output. */ | |
4427 | ||
4428 | i.op[x].regs = i.op[x].regs + 8; | |
773f551c | 4429 | } |
29b0f896 AM |
4430 | } |
4431 | } | |
773f551c | 4432 | |
6b6b6807 L |
4433 | if (i.rex == 0 && i.rex_encoding) |
4434 | { | |
4435 | /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand | |
4436 | that uses legacy register. If it is "hi" register, don't add | |
4437 | the REX_OPCODE byte. */ | |
4438 | int x; | |
4439 | for (x = 0; x < 2; x++) | |
4440 | if (i.types[x].bitfield.reg | |
4441 | && i.types[x].bitfield.byte | |
4442 | && (i.op[x].regs->reg_flags & RegRex64) == 0 | |
4443 | && i.op[x].regs->reg_num > 3) | |
4444 | { | |
4445 | i.rex_encoding = FALSE; | |
4446 | break; | |
4447 | } | |
4448 | ||
4449 | if (i.rex_encoding) | |
4450 | i.rex = REX_OPCODE; | |
4451 | } | |
4452 | ||
7ab9ffdd | 4453 | if (i.rex != 0) |
29b0f896 AM |
4454 | add_prefix (REX_OPCODE | i.rex); |
4455 | ||
4456 | /* We are ready to output the insn. */ | |
4457 | output_insn (); | |
4458 | } | |
4459 | ||
4460 | static char * | |
e3bb37b5 | 4461 | parse_insn (char *line, char *mnemonic) |
29b0f896 AM |
4462 | { |
4463 | char *l = line; | |
4464 | char *token_start = l; | |
4465 | char *mnem_p; | |
5c6af06e | 4466 | int supported; |
d3ce72d0 | 4467 | const insn_template *t; |
b6169b20 | 4468 | char *dot_p = NULL; |
29b0f896 | 4469 | |
29b0f896 AM |
4470 | while (1) |
4471 | { | |
4472 | mnem_p = mnemonic; | |
4473 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
4474 | { | |
b6169b20 L |
4475 | if (*mnem_p == '.') |
4476 | dot_p = mnem_p; | |
29b0f896 AM |
4477 | mnem_p++; |
4478 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
45288df1 | 4479 | { |
29b0f896 AM |
4480 | as_bad (_("no such instruction: `%s'"), token_start); |
4481 | return NULL; | |
4482 | } | |
4483 | l++; | |
4484 | } | |
4485 | if (!is_space_char (*l) | |
4486 | && *l != END_OF_INSN | |
e44823cf JB |
4487 | && (intel_syntax |
4488 | || (*l != PREFIX_SEPARATOR | |
4489 | && *l != ','))) | |
29b0f896 AM |
4490 | { |
4491 | as_bad (_("invalid character %s in mnemonic"), | |
4492 | output_invalid (*l)); | |
4493 | return NULL; | |
4494 | } | |
4495 | if (token_start == l) | |
4496 | { | |
e44823cf | 4497 | if (!intel_syntax && *l == PREFIX_SEPARATOR) |
29b0f896 AM |
4498 | as_bad (_("expecting prefix; got nothing")); |
4499 | else | |
4500 | as_bad (_("expecting mnemonic; got nothing")); | |
4501 | return NULL; | |
4502 | } | |
45288df1 | 4503 | |
29b0f896 | 4504 | /* Look up instruction (or prefix) via hash table. */ |
d3ce72d0 | 4505 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
47926f60 | 4506 | |
29b0f896 AM |
4507 | if (*l != END_OF_INSN |
4508 | && (!is_space_char (*l) || l[1] != END_OF_INSN) | |
4509 | && current_templates | |
40fb9820 | 4510 | && current_templates->start->opcode_modifier.isprefix) |
29b0f896 | 4511 | { |
c6fb90c8 | 4512 | if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags)) |
2dd88dca JB |
4513 | { |
4514 | as_bad ((flag_code != CODE_64BIT | |
4515 | ? _("`%s' is only supported in 64-bit mode") | |
4516 | : _("`%s' is not supported in 64-bit mode")), | |
4517 | current_templates->start->name); | |
4518 | return NULL; | |
4519 | } | |
29b0f896 AM |
4520 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
4521 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
673fe0f0 JB |
4522 | if ((current_templates->start->opcode_modifier.size == SIZE16 |
4523 | || current_templates->start->opcode_modifier.size == SIZE32) | |
29b0f896 | 4524 | && flag_code != CODE_64BIT |
673fe0f0 | 4525 | && ((current_templates->start->opcode_modifier.size == SIZE32) |
29b0f896 AM |
4526 | ^ (flag_code == CODE_16BIT))) |
4527 | { | |
4528 | as_bad (_("redundant %s prefix"), | |
4529 | current_templates->start->name); | |
4530 | return NULL; | |
45288df1 | 4531 | } |
86fa6981 | 4532 | if (current_templates->start->opcode_length == 0) |
29b0f896 | 4533 | { |
86fa6981 L |
4534 | /* Handle pseudo prefixes. */ |
4535 | switch (current_templates->start->base_opcode) | |
4536 | { | |
4537 | case 0x0: | |
4538 | /* {disp8} */ | |
4539 | i.disp_encoding = disp_encoding_8bit; | |
4540 | break; | |
4541 | case 0x1: | |
4542 | /* {disp32} */ | |
4543 | i.disp_encoding = disp_encoding_32bit; | |
4544 | break; | |
4545 | case 0x2: | |
4546 | /* {load} */ | |
4547 | i.dir_encoding = dir_encoding_load; | |
4548 | break; | |
4549 | case 0x3: | |
4550 | /* {store} */ | |
4551 | i.dir_encoding = dir_encoding_store; | |
4552 | break; | |
4553 | case 0x4: | |
4554 | /* {vex2} */ | |
4555 | i.vec_encoding = vex_encoding_vex2; | |
4556 | break; | |
4557 | case 0x5: | |
4558 | /* {vex3} */ | |
4559 | i.vec_encoding = vex_encoding_vex3; | |
4560 | break; | |
4561 | case 0x6: | |
4562 | /* {evex} */ | |
4563 | i.vec_encoding = vex_encoding_evex; | |
4564 | break; | |
6b6b6807 L |
4565 | case 0x7: |
4566 | /* {rex} */ | |
4567 | i.rex_encoding = TRUE; | |
4568 | break; | |
b6f8c7c4 L |
4569 | case 0x8: |
4570 | /* {nooptimize} */ | |
4571 | i.no_optimize = TRUE; | |
4572 | break; | |
86fa6981 L |
4573 | default: |
4574 | abort (); | |
4575 | } | |
4576 | } | |
4577 | else | |
4578 | { | |
4579 | /* Add prefix, checking for repeated prefixes. */ | |
4e9ac44a | 4580 | switch (add_prefix (current_templates->start->base_opcode)) |
86fa6981 | 4581 | { |
4e9ac44a L |
4582 | case PREFIX_EXIST: |
4583 | return NULL; | |
4584 | case PREFIX_DS: | |
d777820b | 4585 | if (current_templates->start->cpu_flags.bitfield.cpuibt) |
4e9ac44a L |
4586 | i.notrack_prefix = current_templates->start->name; |
4587 | break; | |
4588 | case PREFIX_REP: | |
4589 | if (current_templates->start->cpu_flags.bitfield.cpuhle) | |
4590 | i.hle_prefix = current_templates->start->name; | |
4591 | else if (current_templates->start->cpu_flags.bitfield.cpumpx) | |
4592 | i.bnd_prefix = current_templates->start->name; | |
4593 | else | |
4594 | i.rep_prefix = current_templates->start->name; | |
4595 | break; | |
4596 | default: | |
4597 | break; | |
86fa6981 | 4598 | } |
29b0f896 AM |
4599 | } |
4600 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
4601 | token_start = ++l; | |
4602 | } | |
4603 | else | |
4604 | break; | |
4605 | } | |
45288df1 | 4606 | |
30a55f88 | 4607 | if (!current_templates) |
b6169b20 | 4608 | { |
07d5e953 JB |
4609 | /* Deprecated functionality (new code should use pseudo-prefixes instead): |
4610 | Check if we should swap operand or force 32bit displacement in | |
f8a5c266 | 4611 | encoding. */ |
30a55f88 | 4612 | if (mnem_p - 2 == dot_p && dot_p[1] == 's') |
64c49ab3 | 4613 | i.dir_encoding = dir_encoding_swap; |
8d63c93e | 4614 | else if (mnem_p - 3 == dot_p |
a501d77e L |
4615 | && dot_p[1] == 'd' |
4616 | && dot_p[2] == '8') | |
4617 | i.disp_encoding = disp_encoding_8bit; | |
8d63c93e | 4618 | else if (mnem_p - 4 == dot_p |
f8a5c266 L |
4619 | && dot_p[1] == 'd' |
4620 | && dot_p[2] == '3' | |
4621 | && dot_p[3] == '2') | |
a501d77e | 4622 | i.disp_encoding = disp_encoding_32bit; |
30a55f88 L |
4623 | else |
4624 | goto check_suffix; | |
4625 | mnem_p = dot_p; | |
4626 | *dot_p = '\0'; | |
d3ce72d0 | 4627 | current_templates = (const templates *) hash_find (op_hash, mnemonic); |
b6169b20 L |
4628 | } |
4629 | ||
29b0f896 AM |
4630 | if (!current_templates) |
4631 | { | |
b6169b20 | 4632 | check_suffix: |
1c529385 | 4633 | if (mnem_p > mnemonic) |
29b0f896 | 4634 | { |
1c529385 LH |
4635 | /* See if we can get a match by trimming off a suffix. */ |
4636 | switch (mnem_p[-1]) | |
29b0f896 | 4637 | { |
1c529385 LH |
4638 | case WORD_MNEM_SUFFIX: |
4639 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) | |
29b0f896 AM |
4640 | i.suffix = SHORT_MNEM_SUFFIX; |
4641 | else | |
1c529385 LH |
4642 | /* Fall through. */ |
4643 | case BYTE_MNEM_SUFFIX: | |
4644 | case QWORD_MNEM_SUFFIX: | |
4645 | i.suffix = mnem_p[-1]; | |
29b0f896 | 4646 | mnem_p[-1] = '\0'; |
d3ce72d0 | 4647 | current_templates = (const templates *) hash_find (op_hash, |
1c529385 LH |
4648 | mnemonic); |
4649 | break; | |
4650 | case SHORT_MNEM_SUFFIX: | |
4651 | case LONG_MNEM_SUFFIX: | |
4652 | if (!intel_syntax) | |
4653 | { | |
4654 | i.suffix = mnem_p[-1]; | |
4655 | mnem_p[-1] = '\0'; | |
4656 | current_templates = (const templates *) hash_find (op_hash, | |
4657 | mnemonic); | |
4658 | } | |
4659 | break; | |
4660 | ||
4661 | /* Intel Syntax. */ | |
4662 | case 'd': | |
4663 | if (intel_syntax) | |
4664 | { | |
4665 | if (intel_float_operand (mnemonic) == 1) | |
4666 | i.suffix = SHORT_MNEM_SUFFIX; | |
4667 | else | |
4668 | i.suffix = LONG_MNEM_SUFFIX; | |
4669 | mnem_p[-1] = '\0'; | |
4670 | current_templates = (const templates *) hash_find (op_hash, | |
4671 | mnemonic); | |
4672 | } | |
4673 | break; | |
29b0f896 | 4674 | } |
29b0f896 | 4675 | } |
1c529385 | 4676 | |
29b0f896 AM |
4677 | if (!current_templates) |
4678 | { | |
4679 | as_bad (_("no such instruction: `%s'"), token_start); | |
4680 | return NULL; | |
4681 | } | |
4682 | } | |
252b5132 | 4683 | |
40fb9820 L |
4684 | if (current_templates->start->opcode_modifier.jump |
4685 | || current_templates->start->opcode_modifier.jumpbyte) | |
29b0f896 AM |
4686 | { |
4687 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
4688 | predict taken and predict not taken respectively. | |
4689 | I'm not sure that branch hints actually do anything on loop | |
4690 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
4691 | may work in the future and it doesn't hurt to accept them | |
4692 | now. */ | |
4693 | if (l[0] == ',' && l[1] == 'p') | |
4694 | { | |
4695 | if (l[2] == 't') | |
4696 | { | |
4697 | if (!add_prefix (DS_PREFIX_OPCODE)) | |
4698 | return NULL; | |
4699 | l += 3; | |
4700 | } | |
4701 | else if (l[2] == 'n') | |
4702 | { | |
4703 | if (!add_prefix (CS_PREFIX_OPCODE)) | |
4704 | return NULL; | |
4705 | l += 3; | |
4706 | } | |
4707 | } | |
4708 | } | |
4709 | /* Any other comma loses. */ | |
4710 | if (*l == ',') | |
4711 | { | |
4712 | as_bad (_("invalid character %s in mnemonic"), | |
4713 | output_invalid (*l)); | |
4714 | return NULL; | |
4715 | } | |
252b5132 | 4716 | |
29b0f896 | 4717 | /* Check if instruction is supported on specified architecture. */ |
5c6af06e JB |
4718 | supported = 0; |
4719 | for (t = current_templates->start; t < current_templates->end; ++t) | |
4720 | { | |
c0f3af97 L |
4721 | supported |= cpu_flags_match (t); |
4722 | if (supported == CPU_FLAGS_PERFECT_MATCH) | |
548d0ee6 JB |
4723 | { |
4724 | if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT)) | |
4725 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
3629bb00 | 4726 | |
548d0ee6 JB |
4727 | return l; |
4728 | } | |
29b0f896 | 4729 | } |
3629bb00 | 4730 | |
548d0ee6 JB |
4731 | if (!(supported & CPU_FLAGS_64BIT_MATCH)) |
4732 | as_bad (flag_code == CODE_64BIT | |
4733 | ? _("`%s' is not supported in 64-bit mode") | |
4734 | : _("`%s' is only supported in 64-bit mode"), | |
4735 | current_templates->start->name); | |
4736 | else | |
4737 | as_bad (_("`%s' is not supported on `%s%s'"), | |
4738 | current_templates->start->name, | |
4739 | cpu_arch_name ? cpu_arch_name : default_arch, | |
4740 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); | |
252b5132 | 4741 | |
548d0ee6 | 4742 | return NULL; |
29b0f896 | 4743 | } |
252b5132 | 4744 | |
29b0f896 | 4745 | static char * |
e3bb37b5 | 4746 | parse_operands (char *l, const char *mnemonic) |
29b0f896 AM |
4747 | { |
4748 | char *token_start; | |
3138f287 | 4749 | |
29b0f896 AM |
4750 | /* 1 if operand is pending after ','. */ |
4751 | unsigned int expecting_operand = 0; | |
252b5132 | 4752 | |
29b0f896 AM |
4753 | /* Non-zero if operand parens not balanced. */ |
4754 | unsigned int paren_not_balanced; | |
4755 | ||
4756 | while (*l != END_OF_INSN) | |
4757 | { | |
4758 | /* Skip optional white space before operand. */ | |
4759 | if (is_space_char (*l)) | |
4760 | ++l; | |
d02603dc | 4761 | if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"') |
29b0f896 AM |
4762 | { |
4763 | as_bad (_("invalid character %s before operand %d"), | |
4764 | output_invalid (*l), | |
4765 | i.operands + 1); | |
4766 | return NULL; | |
4767 | } | |
d02603dc | 4768 | token_start = l; /* After white space. */ |
29b0f896 AM |
4769 | paren_not_balanced = 0; |
4770 | while (paren_not_balanced || *l != ',') | |
4771 | { | |
4772 | if (*l == END_OF_INSN) | |
4773 | { | |
4774 | if (paren_not_balanced) | |
4775 | { | |
4776 | if (!intel_syntax) | |
4777 | as_bad (_("unbalanced parenthesis in operand %d."), | |
4778 | i.operands + 1); | |
4779 | else | |
4780 | as_bad (_("unbalanced brackets in operand %d."), | |
4781 | i.operands + 1); | |
4782 | return NULL; | |
4783 | } | |
4784 | else | |
4785 | break; /* we are done */ | |
4786 | } | |
d02603dc | 4787 | else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"') |
29b0f896 AM |
4788 | { |
4789 | as_bad (_("invalid character %s in operand %d"), | |
4790 | output_invalid (*l), | |
4791 | i.operands + 1); | |
4792 | return NULL; | |
4793 | } | |
4794 | if (!intel_syntax) | |
4795 | { | |
4796 | if (*l == '(') | |
4797 | ++paren_not_balanced; | |
4798 | if (*l == ')') | |
4799 | --paren_not_balanced; | |
4800 | } | |
4801 | else | |
4802 | { | |
4803 | if (*l == '[') | |
4804 | ++paren_not_balanced; | |
4805 | if (*l == ']') | |
4806 | --paren_not_balanced; | |
4807 | } | |
4808 | l++; | |
4809 | } | |
4810 | if (l != token_start) | |
4811 | { /* Yes, we've read in another operand. */ | |
4812 | unsigned int operand_ok; | |
4813 | this_operand = i.operands++; | |
4814 | if (i.operands > MAX_OPERANDS) | |
4815 | { | |
4816 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
4817 | MAX_OPERANDS); | |
4818 | return NULL; | |
4819 | } | |
9d46ce34 | 4820 | i.types[this_operand].bitfield.unspecified = 1; |
29b0f896 AM |
4821 | /* Now parse operand adding info to 'i' as we go along. */ |
4822 | END_STRING_AND_SAVE (l); | |
4823 | ||
1286ab78 L |
4824 | if (i.mem_operands > 1) |
4825 | { | |
4826 | as_bad (_("too many memory references for `%s'"), | |
4827 | mnemonic); | |
4828 | return 0; | |
4829 | } | |
4830 | ||
29b0f896 AM |
4831 | if (intel_syntax) |
4832 | operand_ok = | |
4833 | i386_intel_operand (token_start, | |
4834 | intel_float_operand (mnemonic)); | |
4835 | else | |
a7619375 | 4836 | operand_ok = i386_att_operand (token_start); |
29b0f896 AM |
4837 | |
4838 | RESTORE_END_STRING (l); | |
4839 | if (!operand_ok) | |
4840 | return NULL; | |
4841 | } | |
4842 | else | |
4843 | { | |
4844 | if (expecting_operand) | |
4845 | { | |
4846 | expecting_operand_after_comma: | |
4847 | as_bad (_("expecting operand after ','; got nothing")); | |
4848 | return NULL; | |
4849 | } | |
4850 | if (*l == ',') | |
4851 | { | |
4852 | as_bad (_("expecting operand before ','; got nothing")); | |
4853 | return NULL; | |
4854 | } | |
4855 | } | |
7f3f1ea2 | 4856 | |
29b0f896 AM |
4857 | /* Now *l must be either ',' or END_OF_INSN. */ |
4858 | if (*l == ',') | |
4859 | { | |
4860 | if (*++l == END_OF_INSN) | |
4861 | { | |
4862 | /* Just skip it, if it's \n complain. */ | |
4863 | goto expecting_operand_after_comma; | |
4864 | } | |
4865 | expecting_operand = 1; | |
4866 | } | |
4867 | } | |
4868 | return l; | |
4869 | } | |
7f3f1ea2 | 4870 | |
050dfa73 | 4871 | static void |
4d456e3d | 4872 | swap_2_operands (int xchg1, int xchg2) |
050dfa73 MM |
4873 | { |
4874 | union i386_op temp_op; | |
40fb9820 | 4875 | i386_operand_type temp_type; |
c48dadc9 | 4876 | unsigned int temp_flags; |
050dfa73 | 4877 | enum bfd_reloc_code_real temp_reloc; |
4eed87de | 4878 | |
050dfa73 MM |
4879 | temp_type = i.types[xchg2]; |
4880 | i.types[xchg2] = i.types[xchg1]; | |
4881 | i.types[xchg1] = temp_type; | |
c48dadc9 JB |
4882 | |
4883 | temp_flags = i.flags[xchg2]; | |
4884 | i.flags[xchg2] = i.flags[xchg1]; | |
4885 | i.flags[xchg1] = temp_flags; | |
4886 | ||
050dfa73 MM |
4887 | temp_op = i.op[xchg2]; |
4888 | i.op[xchg2] = i.op[xchg1]; | |
4889 | i.op[xchg1] = temp_op; | |
c48dadc9 | 4890 | |
050dfa73 MM |
4891 | temp_reloc = i.reloc[xchg2]; |
4892 | i.reloc[xchg2] = i.reloc[xchg1]; | |
4893 | i.reloc[xchg1] = temp_reloc; | |
43234a1e L |
4894 | |
4895 | if (i.mask) | |
4896 | { | |
4897 | if (i.mask->operand == xchg1) | |
4898 | i.mask->operand = xchg2; | |
4899 | else if (i.mask->operand == xchg2) | |
4900 | i.mask->operand = xchg1; | |
4901 | } | |
4902 | if (i.broadcast) | |
4903 | { | |
4904 | if (i.broadcast->operand == xchg1) | |
4905 | i.broadcast->operand = xchg2; | |
4906 | else if (i.broadcast->operand == xchg2) | |
4907 | i.broadcast->operand = xchg1; | |
4908 | } | |
4909 | if (i.rounding) | |
4910 | { | |
4911 | if (i.rounding->operand == xchg1) | |
4912 | i.rounding->operand = xchg2; | |
4913 | else if (i.rounding->operand == xchg2) | |
4914 | i.rounding->operand = xchg1; | |
4915 | } | |
050dfa73 MM |
4916 | } |
4917 | ||
29b0f896 | 4918 | static void |
e3bb37b5 | 4919 | swap_operands (void) |
29b0f896 | 4920 | { |
b7c61d9a | 4921 | switch (i.operands) |
050dfa73 | 4922 | { |
c0f3af97 | 4923 | case 5: |
b7c61d9a | 4924 | case 4: |
4d456e3d | 4925 | swap_2_operands (1, i.operands - 2); |
1a0670f3 | 4926 | /* Fall through. */ |
b7c61d9a L |
4927 | case 3: |
4928 | case 2: | |
4d456e3d | 4929 | swap_2_operands (0, i.operands - 1); |
b7c61d9a L |
4930 | break; |
4931 | default: | |
4932 | abort (); | |
29b0f896 | 4933 | } |
29b0f896 AM |
4934 | |
4935 | if (i.mem_operands == 2) | |
4936 | { | |
4937 | const seg_entry *temp_seg; | |
4938 | temp_seg = i.seg[0]; | |
4939 | i.seg[0] = i.seg[1]; | |
4940 | i.seg[1] = temp_seg; | |
4941 | } | |
4942 | } | |
252b5132 | 4943 | |
29b0f896 AM |
4944 | /* Try to ensure constant immediates are represented in the smallest |
4945 | opcode possible. */ | |
4946 | static void | |
e3bb37b5 | 4947 | optimize_imm (void) |
29b0f896 AM |
4948 | { |
4949 | char guess_suffix = 0; | |
4950 | int op; | |
252b5132 | 4951 | |
29b0f896 AM |
4952 | if (i.suffix) |
4953 | guess_suffix = i.suffix; | |
4954 | else if (i.reg_operands) | |
4955 | { | |
4956 | /* Figure out a suffix from the last register operand specified. | |
4957 | We can't do this properly yet, ie. excluding InOutPortReg, | |
4958 | but the following works for instructions with immediates. | |
4959 | In any case, we can't set i.suffix yet. */ | |
4960 | for (op = i.operands; --op >= 0;) | |
dc821c5f | 4961 | if (i.types[op].bitfield.reg && i.types[op].bitfield.byte) |
7ab9ffdd | 4962 | { |
40fb9820 L |
4963 | guess_suffix = BYTE_MNEM_SUFFIX; |
4964 | break; | |
4965 | } | |
dc821c5f | 4966 | else if (i.types[op].bitfield.reg && i.types[op].bitfield.word) |
252b5132 | 4967 | { |
40fb9820 L |
4968 | guess_suffix = WORD_MNEM_SUFFIX; |
4969 | break; | |
4970 | } | |
dc821c5f | 4971 | else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword) |
40fb9820 L |
4972 | { |
4973 | guess_suffix = LONG_MNEM_SUFFIX; | |
4974 | break; | |
4975 | } | |
dc821c5f | 4976 | else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword) |
40fb9820 L |
4977 | { |
4978 | guess_suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 | 4979 | break; |
252b5132 | 4980 | } |
29b0f896 AM |
4981 | } |
4982 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) | |
4983 | guess_suffix = WORD_MNEM_SUFFIX; | |
4984 | ||
4985 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 4986 | if (operand_type_check (i.types[op], imm)) |
29b0f896 AM |
4987 | { |
4988 | switch (i.op[op].imms->X_op) | |
252b5132 | 4989 | { |
29b0f896 AM |
4990 | case O_constant: |
4991 | /* If a suffix is given, this operand may be shortened. */ | |
4992 | switch (guess_suffix) | |
252b5132 | 4993 | { |
29b0f896 | 4994 | case LONG_MNEM_SUFFIX: |
40fb9820 L |
4995 | i.types[op].bitfield.imm32 = 1; |
4996 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
4997 | break; |
4998 | case WORD_MNEM_SUFFIX: | |
40fb9820 L |
4999 | i.types[op].bitfield.imm16 = 1; |
5000 | i.types[op].bitfield.imm32 = 1; | |
5001 | i.types[op].bitfield.imm32s = 1; | |
5002 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
5003 | break; |
5004 | case BYTE_MNEM_SUFFIX: | |
40fb9820 L |
5005 | i.types[op].bitfield.imm8 = 1; |
5006 | i.types[op].bitfield.imm8s = 1; | |
5007 | i.types[op].bitfield.imm16 = 1; | |
5008 | i.types[op].bitfield.imm32 = 1; | |
5009 | i.types[op].bitfield.imm32s = 1; | |
5010 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 | 5011 | break; |
252b5132 | 5012 | } |
252b5132 | 5013 | |
29b0f896 AM |
5014 | /* If this operand is at most 16 bits, convert it |
5015 | to a signed 16 bit number before trying to see | |
5016 | whether it will fit in an even smaller size. | |
5017 | This allows a 16-bit operand such as $0xffe0 to | |
5018 | be recognised as within Imm8S range. */ | |
40fb9820 | 5019 | if ((i.types[op].bitfield.imm16) |
29b0f896 | 5020 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) |
252b5132 | 5021 | { |
29b0f896 AM |
5022 | i.op[op].imms->X_add_number = |
5023 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
5024 | } | |
a28def75 L |
5025 | #ifdef BFD64 |
5026 | /* Store 32-bit immediate in 64-bit for 64-bit BFD. */ | |
40fb9820 | 5027 | if ((i.types[op].bitfield.imm32) |
29b0f896 AM |
5028 | && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) |
5029 | == 0)) | |
5030 | { | |
5031 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number | |
5032 | ^ ((offsetT) 1 << 31)) | |
5033 | - ((offsetT) 1 << 31)); | |
5034 | } | |
a28def75 | 5035 | #endif |
40fb9820 | 5036 | i.types[op] |
c6fb90c8 L |
5037 | = operand_type_or (i.types[op], |
5038 | smallest_imm_type (i.op[op].imms->X_add_number)); | |
252b5132 | 5039 | |
29b0f896 AM |
5040 | /* We must avoid matching of Imm32 templates when 64bit |
5041 | only immediate is available. */ | |
5042 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
40fb9820 | 5043 | i.types[op].bitfield.imm32 = 0; |
29b0f896 | 5044 | break; |
252b5132 | 5045 | |
29b0f896 AM |
5046 | case O_absent: |
5047 | case O_register: | |
5048 | abort (); | |
5049 | ||
5050 | /* Symbols and expressions. */ | |
5051 | default: | |
9cd96992 JB |
5052 | /* Convert symbolic operand to proper sizes for matching, but don't |
5053 | prevent matching a set of insns that only supports sizes other | |
5054 | than those matching the insn suffix. */ | |
5055 | { | |
40fb9820 | 5056 | i386_operand_type mask, allowed; |
d3ce72d0 | 5057 | const insn_template *t; |
9cd96992 | 5058 | |
0dfbf9d7 L |
5059 | operand_type_set (&mask, 0); |
5060 | operand_type_set (&allowed, 0); | |
40fb9820 | 5061 | |
4eed87de AM |
5062 | for (t = current_templates->start; |
5063 | t < current_templates->end; | |
5064 | ++t) | |
c6fb90c8 L |
5065 | allowed = operand_type_or (allowed, |
5066 | t->operand_types[op]); | |
9cd96992 JB |
5067 | switch (guess_suffix) |
5068 | { | |
5069 | case QWORD_MNEM_SUFFIX: | |
40fb9820 L |
5070 | mask.bitfield.imm64 = 1; |
5071 | mask.bitfield.imm32s = 1; | |
9cd96992 JB |
5072 | break; |
5073 | case LONG_MNEM_SUFFIX: | |
40fb9820 | 5074 | mask.bitfield.imm32 = 1; |
9cd96992 JB |
5075 | break; |
5076 | case WORD_MNEM_SUFFIX: | |
40fb9820 | 5077 | mask.bitfield.imm16 = 1; |
9cd96992 JB |
5078 | break; |
5079 | case BYTE_MNEM_SUFFIX: | |
40fb9820 | 5080 | mask.bitfield.imm8 = 1; |
9cd96992 JB |
5081 | break; |
5082 | default: | |
9cd96992 JB |
5083 | break; |
5084 | } | |
c6fb90c8 | 5085 | allowed = operand_type_and (mask, allowed); |
0dfbf9d7 | 5086 | if (!operand_type_all_zero (&allowed)) |
c6fb90c8 | 5087 | i.types[op] = operand_type_and (i.types[op], mask); |
9cd96992 | 5088 | } |
29b0f896 | 5089 | break; |
252b5132 | 5090 | } |
29b0f896 AM |
5091 | } |
5092 | } | |
47926f60 | 5093 | |
29b0f896 AM |
5094 | /* Try to use the smallest displacement type too. */ |
5095 | static void | |
e3bb37b5 | 5096 | optimize_disp (void) |
29b0f896 AM |
5097 | { |
5098 | int op; | |
3e73aa7c | 5099 | |
29b0f896 | 5100 | for (op = i.operands; --op >= 0;) |
40fb9820 | 5101 | if (operand_type_check (i.types[op], disp)) |
252b5132 | 5102 | { |
b300c311 | 5103 | if (i.op[op].disps->X_op == O_constant) |
252b5132 | 5104 | { |
91d6fa6a | 5105 | offsetT op_disp = i.op[op].disps->X_add_number; |
29b0f896 | 5106 | |
40fb9820 | 5107 | if (i.types[op].bitfield.disp16 |
91d6fa6a | 5108 | && (op_disp & ~(offsetT) 0xffff) == 0) |
b300c311 L |
5109 | { |
5110 | /* If this operand is at most 16 bits, convert | |
5111 | to a signed 16 bit number and don't use 64bit | |
5112 | displacement. */ | |
91d6fa6a | 5113 | op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000); |
40fb9820 | 5114 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 5115 | } |
a28def75 L |
5116 | #ifdef BFD64 |
5117 | /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */ | |
40fb9820 | 5118 | if (i.types[op].bitfield.disp32 |
91d6fa6a | 5119 | && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0) |
b300c311 L |
5120 | { |
5121 | /* If this operand is at most 32 bits, convert | |
5122 | to a signed 32 bit number and don't use 64bit | |
5123 | displacement. */ | |
91d6fa6a NC |
5124 | op_disp &= (((offsetT) 2 << 31) - 1); |
5125 | op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
40fb9820 | 5126 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 5127 | } |
a28def75 | 5128 | #endif |
91d6fa6a | 5129 | if (!op_disp && i.types[op].bitfield.baseindex) |
b300c311 | 5130 | { |
40fb9820 L |
5131 | i.types[op].bitfield.disp8 = 0; |
5132 | i.types[op].bitfield.disp16 = 0; | |
5133 | i.types[op].bitfield.disp32 = 0; | |
5134 | i.types[op].bitfield.disp32s = 0; | |
5135 | i.types[op].bitfield.disp64 = 0; | |
b300c311 L |
5136 | i.op[op].disps = 0; |
5137 | i.disp_operands--; | |
5138 | } | |
5139 | else if (flag_code == CODE_64BIT) | |
5140 | { | |
91d6fa6a | 5141 | if (fits_in_signed_long (op_disp)) |
28a9d8f5 | 5142 | { |
40fb9820 L |
5143 | i.types[op].bitfield.disp64 = 0; |
5144 | i.types[op].bitfield.disp32s = 1; | |
28a9d8f5 | 5145 | } |
0e1147d9 | 5146 | if (i.prefix[ADDR_PREFIX] |
91d6fa6a | 5147 | && fits_in_unsigned_long (op_disp)) |
40fb9820 | 5148 | i.types[op].bitfield.disp32 = 1; |
b300c311 | 5149 | } |
40fb9820 L |
5150 | if ((i.types[op].bitfield.disp32 |
5151 | || i.types[op].bitfield.disp32s | |
5152 | || i.types[op].bitfield.disp16) | |
b5014f7a | 5153 | && fits_in_disp8 (op_disp)) |
40fb9820 | 5154 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 5155 | } |
67a4f2b7 AO |
5156 | else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
5157 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) | |
5158 | { | |
5159 | fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, | |
5160 | i.op[op].disps, 0, i.reloc[op]); | |
40fb9820 L |
5161 | i.types[op].bitfield.disp8 = 0; |
5162 | i.types[op].bitfield.disp16 = 0; | |
5163 | i.types[op].bitfield.disp32 = 0; | |
5164 | i.types[op].bitfield.disp32s = 0; | |
5165 | i.types[op].bitfield.disp64 = 0; | |
67a4f2b7 AO |
5166 | } |
5167 | else | |
b300c311 | 5168 | /* We only support 64bit displacement on constants. */ |
40fb9820 | 5169 | i.types[op].bitfield.disp64 = 0; |
252b5132 | 5170 | } |
29b0f896 AM |
5171 | } |
5172 | ||
4a1b91ea L |
5173 | /* Return 1 if there is a match in broadcast bytes between operand |
5174 | GIVEN and instruction template T. */ | |
5175 | ||
5176 | static INLINE int | |
5177 | match_broadcast_size (const insn_template *t, unsigned int given) | |
5178 | { | |
5179 | return ((t->opcode_modifier.broadcast == BYTE_BROADCAST | |
5180 | && i.types[given].bitfield.byte) | |
5181 | || (t->opcode_modifier.broadcast == WORD_BROADCAST | |
5182 | && i.types[given].bitfield.word) | |
5183 | || (t->opcode_modifier.broadcast == DWORD_BROADCAST | |
5184 | && i.types[given].bitfield.dword) | |
5185 | || (t->opcode_modifier.broadcast == QWORD_BROADCAST | |
5186 | && i.types[given].bitfield.qword)); | |
5187 | } | |
5188 | ||
6c30d220 L |
5189 | /* Check if operands are valid for the instruction. */ |
5190 | ||
5191 | static int | |
5192 | check_VecOperands (const insn_template *t) | |
5193 | { | |
43234a1e | 5194 | unsigned int op; |
e2195274 JB |
5195 | i386_cpu_flags cpu; |
5196 | static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS; | |
5197 | ||
5198 | /* Templates allowing for ZMMword as well as YMMword and/or XMMword for | |
5199 | any one operand are implicity requiring AVX512VL support if the actual | |
5200 | operand size is YMMword or XMMword. Since this function runs after | |
5201 | template matching, there's no need to check for YMMword/XMMword in | |
5202 | the template. */ | |
5203 | cpu = cpu_flags_and (t->cpu_flags, avx512); | |
5204 | if (!cpu_flags_all_zero (&cpu) | |
5205 | && !t->cpu_flags.bitfield.cpuavx512vl | |
5206 | && !cpu_arch_flags.bitfield.cpuavx512vl) | |
5207 | { | |
5208 | for (op = 0; op < t->operands; ++op) | |
5209 | { | |
5210 | if (t->operand_types[op].bitfield.zmmword | |
5211 | && (i.types[op].bitfield.ymmword | |
5212 | || i.types[op].bitfield.xmmword)) | |
5213 | { | |
5214 | i.error = unsupported; | |
5215 | return 1; | |
5216 | } | |
5217 | } | |
5218 | } | |
43234a1e | 5219 | |
6c30d220 L |
5220 | /* Without VSIB byte, we can't have a vector register for index. */ |
5221 | if (!t->opcode_modifier.vecsib | |
5222 | && i.index_reg | |
1b54b8d7 JB |
5223 | && (i.index_reg->reg_type.bitfield.xmmword |
5224 | || i.index_reg->reg_type.bitfield.ymmword | |
5225 | || i.index_reg->reg_type.bitfield.zmmword)) | |
6c30d220 L |
5226 | { |
5227 | i.error = unsupported_vector_index_register; | |
5228 | return 1; | |
5229 | } | |
5230 | ||
ad8ecc81 MZ |
5231 | /* Check if default mask is allowed. */ |
5232 | if (t->opcode_modifier.nodefmask | |
5233 | && (!i.mask || i.mask->mask->reg_num == 0)) | |
5234 | { | |
5235 | i.error = no_default_mask; | |
5236 | return 1; | |
5237 | } | |
5238 | ||
7bab8ab5 JB |
5239 | /* For VSIB byte, we need a vector register for index, and all vector |
5240 | registers must be distinct. */ | |
5241 | if (t->opcode_modifier.vecsib) | |
5242 | { | |
5243 | if (!i.index_reg | |
6c30d220 | 5244 | || !((t->opcode_modifier.vecsib == VecSIB128 |
1b54b8d7 | 5245 | && i.index_reg->reg_type.bitfield.xmmword) |
6c30d220 | 5246 | || (t->opcode_modifier.vecsib == VecSIB256 |
1b54b8d7 | 5247 | && i.index_reg->reg_type.bitfield.ymmword) |
43234a1e | 5248 | || (t->opcode_modifier.vecsib == VecSIB512 |
1b54b8d7 | 5249 | && i.index_reg->reg_type.bitfield.zmmword))) |
7bab8ab5 JB |
5250 | { |
5251 | i.error = invalid_vsib_address; | |
5252 | return 1; | |
5253 | } | |
5254 | ||
43234a1e L |
5255 | gas_assert (i.reg_operands == 2 || i.mask); |
5256 | if (i.reg_operands == 2 && !i.mask) | |
5257 | { | |
1b54b8d7 JB |
5258 | gas_assert (i.types[0].bitfield.regsimd); |
5259 | gas_assert (i.types[0].bitfield.xmmword | |
5260 | || i.types[0].bitfield.ymmword); | |
5261 | gas_assert (i.types[2].bitfield.regsimd); | |
5262 | gas_assert (i.types[2].bitfield.xmmword | |
5263 | || i.types[2].bitfield.ymmword); | |
43234a1e L |
5264 | if (operand_check == check_none) |
5265 | return 0; | |
5266 | if (register_number (i.op[0].regs) | |
5267 | != register_number (i.index_reg) | |
5268 | && register_number (i.op[2].regs) | |
5269 | != register_number (i.index_reg) | |
5270 | && register_number (i.op[0].regs) | |
5271 | != register_number (i.op[2].regs)) | |
5272 | return 0; | |
5273 | if (operand_check == check_error) | |
5274 | { | |
5275 | i.error = invalid_vector_register_set; | |
5276 | return 1; | |
5277 | } | |
5278 | as_warn (_("mask, index, and destination registers should be distinct")); | |
5279 | } | |
8444f82a MZ |
5280 | else if (i.reg_operands == 1 && i.mask) |
5281 | { | |
1b54b8d7 JB |
5282 | if (i.types[1].bitfield.regsimd |
5283 | && (i.types[1].bitfield.xmmword | |
5284 | || i.types[1].bitfield.ymmword | |
5285 | || i.types[1].bitfield.zmmword) | |
8444f82a MZ |
5286 | && (register_number (i.op[1].regs) |
5287 | == register_number (i.index_reg))) | |
5288 | { | |
5289 | if (operand_check == check_error) | |
5290 | { | |
5291 | i.error = invalid_vector_register_set; | |
5292 | return 1; | |
5293 | } | |
5294 | if (operand_check != check_none) | |
5295 | as_warn (_("index and destination registers should be distinct")); | |
5296 | } | |
5297 | } | |
43234a1e | 5298 | } |
7bab8ab5 | 5299 | |
43234a1e L |
5300 | /* Check if broadcast is supported by the instruction and is applied |
5301 | to the memory operand. */ | |
5302 | if (i.broadcast) | |
5303 | { | |
8e6e0792 | 5304 | i386_operand_type type, overlap; |
43234a1e L |
5305 | |
5306 | /* Check if specified broadcast is supported in this instruction, | |
4a1b91ea | 5307 | and its broadcast bytes match the memory operand. */ |
32546502 | 5308 | op = i.broadcast->operand; |
8e6e0792 | 5309 | if (!t->opcode_modifier.broadcast |
c48dadc9 | 5310 | || !(i.flags[op] & Operand_Mem) |
c39e5b26 | 5311 | || (!i.types[op].bitfield.unspecified |
4a1b91ea | 5312 | && !match_broadcast_size (t, op))) |
43234a1e L |
5313 | { |
5314 | bad_broadcast: | |
5315 | i.error = unsupported_broadcast; | |
5316 | return 1; | |
5317 | } | |
8e6e0792 | 5318 | |
4a1b91ea L |
5319 | i.broadcast->bytes = ((1 << (t->opcode_modifier.broadcast - 1)) |
5320 | * i.broadcast->type); | |
8e6e0792 | 5321 | operand_type_set (&type, 0); |
4a1b91ea | 5322 | switch (i.broadcast->bytes) |
8e6e0792 | 5323 | { |
4a1b91ea L |
5324 | case 2: |
5325 | type.bitfield.word = 1; | |
5326 | break; | |
5327 | case 4: | |
5328 | type.bitfield.dword = 1; | |
5329 | break; | |
8e6e0792 JB |
5330 | case 8: |
5331 | type.bitfield.qword = 1; | |
5332 | break; | |
5333 | case 16: | |
5334 | type.bitfield.xmmword = 1; | |
5335 | break; | |
5336 | case 32: | |
5337 | type.bitfield.ymmword = 1; | |
5338 | break; | |
5339 | case 64: | |
5340 | type.bitfield.zmmword = 1; | |
5341 | break; | |
5342 | default: | |
5343 | goto bad_broadcast; | |
5344 | } | |
5345 | ||
5346 | overlap = operand_type_and (type, t->operand_types[op]); | |
5347 | if (operand_type_all_zero (&overlap)) | |
5348 | goto bad_broadcast; | |
5349 | ||
5350 | if (t->opcode_modifier.checkregsize) | |
5351 | { | |
5352 | unsigned int j; | |
5353 | ||
e2195274 | 5354 | type.bitfield.baseindex = 1; |
8e6e0792 JB |
5355 | for (j = 0; j < i.operands; ++j) |
5356 | { | |
5357 | if (j != op | |
5358 | && !operand_type_register_match(i.types[j], | |
5359 | t->operand_types[j], | |
5360 | type, | |
5361 | t->operand_types[op])) | |
5362 | goto bad_broadcast; | |
5363 | } | |
5364 | } | |
43234a1e L |
5365 | } |
5366 | /* If broadcast is supported in this instruction, we need to check if | |
5367 | operand of one-element size isn't specified without broadcast. */ | |
5368 | else if (t->opcode_modifier.broadcast && i.mem_operands) | |
5369 | { | |
5370 | /* Find memory operand. */ | |
5371 | for (op = 0; op < i.operands; op++) | |
5372 | if (operand_type_check (i.types[op], anymem)) | |
5373 | break; | |
5374 | gas_assert (op < i.operands); | |
5375 | /* Check size of the memory operand. */ | |
4a1b91ea | 5376 | if (match_broadcast_size (t, op)) |
43234a1e L |
5377 | { |
5378 | i.error = broadcast_needed; | |
5379 | return 1; | |
5380 | } | |
5381 | } | |
c39e5b26 JB |
5382 | else |
5383 | op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */ | |
43234a1e L |
5384 | |
5385 | /* Check if requested masking is supported. */ | |
ae2387fe | 5386 | if (i.mask) |
43234a1e | 5387 | { |
ae2387fe JB |
5388 | switch (t->opcode_modifier.masking) |
5389 | { | |
5390 | case BOTH_MASKING: | |
5391 | break; | |
5392 | case MERGING_MASKING: | |
5393 | if (i.mask->zeroing) | |
5394 | { | |
5395 | case 0: | |
5396 | i.error = unsupported_masking; | |
5397 | return 1; | |
5398 | } | |
5399 | break; | |
5400 | case DYNAMIC_MASKING: | |
5401 | /* Memory destinations allow only merging masking. */ | |
5402 | if (i.mask->zeroing && i.mem_operands) | |
5403 | { | |
5404 | /* Find memory operand. */ | |
5405 | for (op = 0; op < i.operands; op++) | |
c48dadc9 | 5406 | if (i.flags[op] & Operand_Mem) |
ae2387fe JB |
5407 | break; |
5408 | gas_assert (op < i.operands); | |
5409 | if (op == i.operands - 1) | |
5410 | { | |
5411 | i.error = unsupported_masking; | |
5412 | return 1; | |
5413 | } | |
5414 | } | |
5415 | break; | |
5416 | default: | |
5417 | abort (); | |
5418 | } | |
43234a1e L |
5419 | } |
5420 | ||
5421 | /* Check if masking is applied to dest operand. */ | |
5422 | if (i.mask && (i.mask->operand != (int) (i.operands - 1))) | |
5423 | { | |
5424 | i.error = mask_not_on_destination; | |
5425 | return 1; | |
5426 | } | |
5427 | ||
43234a1e L |
5428 | /* Check RC/SAE. */ |
5429 | if (i.rounding) | |
5430 | { | |
5431 | if ((i.rounding->type != saeonly | |
5432 | && !t->opcode_modifier.staticrounding) | |
5433 | || (i.rounding->type == saeonly | |
5434 | && (t->opcode_modifier.staticrounding | |
5435 | || !t->opcode_modifier.sae))) | |
5436 | { | |
5437 | i.error = unsupported_rc_sae; | |
5438 | return 1; | |
5439 | } | |
5440 | /* If the instruction has several immediate operands and one of | |
5441 | them is rounding, the rounding operand should be the last | |
5442 | immediate operand. */ | |
5443 | if (i.imm_operands > 1 | |
5444 | && i.rounding->operand != (int) (i.imm_operands - 1)) | |
7bab8ab5 | 5445 | { |
43234a1e | 5446 | i.error = rc_sae_operand_not_last_imm; |
7bab8ab5 JB |
5447 | return 1; |
5448 | } | |
6c30d220 L |
5449 | } |
5450 | ||
43234a1e | 5451 | /* Check vector Disp8 operand. */ |
b5014f7a JB |
5452 | if (t->opcode_modifier.disp8memshift |
5453 | && i.disp_encoding != disp_encoding_32bit) | |
43234a1e L |
5454 | { |
5455 | if (i.broadcast) | |
4a1b91ea | 5456 | i.memshift = t->opcode_modifier.broadcast - 1; |
7091c612 | 5457 | else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL) |
43234a1e | 5458 | i.memshift = t->opcode_modifier.disp8memshift; |
7091c612 JB |
5459 | else |
5460 | { | |
5461 | const i386_operand_type *type = NULL; | |
5462 | ||
5463 | i.memshift = 0; | |
5464 | for (op = 0; op < i.operands; op++) | |
5465 | if (operand_type_check (i.types[op], anymem)) | |
5466 | { | |
4174bfff JB |
5467 | if (t->opcode_modifier.evex == EVEXLIG) |
5468 | i.memshift = 2 + (i.suffix == QWORD_MNEM_SUFFIX); | |
5469 | else if (t->operand_types[op].bitfield.xmmword | |
5470 | + t->operand_types[op].bitfield.ymmword | |
5471 | + t->operand_types[op].bitfield.zmmword <= 1) | |
7091c612 JB |
5472 | type = &t->operand_types[op]; |
5473 | else if (!i.types[op].bitfield.unspecified) | |
5474 | type = &i.types[op]; | |
5475 | } | |
4174bfff JB |
5476 | else if (i.types[op].bitfield.regsimd |
5477 | && t->opcode_modifier.evex != EVEXLIG) | |
7091c612 JB |
5478 | { |
5479 | if (i.types[op].bitfield.zmmword) | |
5480 | i.memshift = 6; | |
5481 | else if (i.types[op].bitfield.ymmword && i.memshift < 5) | |
5482 | i.memshift = 5; | |
5483 | else if (i.types[op].bitfield.xmmword && i.memshift < 4) | |
5484 | i.memshift = 4; | |
5485 | } | |
5486 | ||
5487 | if (type) | |
5488 | { | |
5489 | if (type->bitfield.zmmword) | |
5490 | i.memshift = 6; | |
5491 | else if (type->bitfield.ymmword) | |
5492 | i.memshift = 5; | |
5493 | else if (type->bitfield.xmmword) | |
5494 | i.memshift = 4; | |
5495 | } | |
5496 | ||
5497 | /* For the check in fits_in_disp8(). */ | |
5498 | if (i.memshift == 0) | |
5499 | i.memshift = -1; | |
5500 | } | |
43234a1e L |
5501 | |
5502 | for (op = 0; op < i.operands; op++) | |
5503 | if (operand_type_check (i.types[op], disp) | |
5504 | && i.op[op].disps->X_op == O_constant) | |
5505 | { | |
b5014f7a | 5506 | if (fits_in_disp8 (i.op[op].disps->X_add_number)) |
43234a1e | 5507 | { |
b5014f7a JB |
5508 | i.types[op].bitfield.disp8 = 1; |
5509 | return 0; | |
43234a1e | 5510 | } |
b5014f7a | 5511 | i.types[op].bitfield.disp8 = 0; |
43234a1e L |
5512 | } |
5513 | } | |
b5014f7a JB |
5514 | |
5515 | i.memshift = 0; | |
43234a1e | 5516 | |
6c30d220 L |
5517 | return 0; |
5518 | } | |
5519 | ||
43f3e2ee | 5520 | /* Check if operands are valid for the instruction. Update VEX |
a683cc34 SP |
5521 | operand types. */ |
5522 | ||
5523 | static int | |
5524 | VEX_check_operands (const insn_template *t) | |
5525 | { | |
86fa6981 | 5526 | if (i.vec_encoding == vex_encoding_evex) |
43234a1e | 5527 | { |
86fa6981 | 5528 | /* This instruction must be encoded with EVEX prefix. */ |
e771e7c9 | 5529 | if (!is_evex_encoding (t)) |
86fa6981 L |
5530 | { |
5531 | i.error = unsupported; | |
5532 | return 1; | |
5533 | } | |
5534 | return 0; | |
43234a1e L |
5535 | } |
5536 | ||
a683cc34 | 5537 | if (!t->opcode_modifier.vex) |
86fa6981 L |
5538 | { |
5539 | /* This instruction template doesn't have VEX prefix. */ | |
5540 | if (i.vec_encoding != vex_encoding_default) | |
5541 | { | |
5542 | i.error = unsupported; | |
5543 | return 1; | |
5544 | } | |
5545 | return 0; | |
5546 | } | |
a683cc34 SP |
5547 | |
5548 | /* Only check VEX_Imm4, which must be the first operand. */ | |
5549 | if (t->operand_types[0].bitfield.vec_imm4) | |
5550 | { | |
5551 | if (i.op[0].imms->X_op != O_constant | |
5552 | || !fits_in_imm4 (i.op[0].imms->X_add_number)) | |
891edac4 | 5553 | { |
a65babc9 | 5554 | i.error = bad_imm4; |
891edac4 L |
5555 | return 1; |
5556 | } | |
a683cc34 SP |
5557 | |
5558 | /* Turn off Imm8 so that update_imm won't complain. */ | |
5559 | i.types[0] = vec_imm4; | |
5560 | } | |
5561 | ||
5562 | return 0; | |
5563 | } | |
5564 | ||
d3ce72d0 | 5565 | static const insn_template * |
83b16ac6 | 5566 | match_template (char mnem_suffix) |
29b0f896 AM |
5567 | { |
5568 | /* Points to template once we've found it. */ | |
d3ce72d0 | 5569 | const insn_template *t; |
40fb9820 | 5570 | i386_operand_type overlap0, overlap1, overlap2, overlap3; |
c0f3af97 | 5571 | i386_operand_type overlap4; |
29b0f896 | 5572 | unsigned int found_reverse_match; |
83b16ac6 | 5573 | i386_opcode_modifier suffix_check, mnemsuf_check; |
40fb9820 | 5574 | i386_operand_type operand_types [MAX_OPERANDS]; |
539e75ad | 5575 | int addr_prefix_disp; |
a5c311ca | 5576 | unsigned int j; |
3ac21baa | 5577 | unsigned int found_cpu_match, size_match; |
45664ddb | 5578 | unsigned int check_register; |
5614d22c | 5579 | enum i386_error specific_error = 0; |
29b0f896 | 5580 | |
c0f3af97 L |
5581 | #if MAX_OPERANDS != 5 |
5582 | # error "MAX_OPERANDS must be 5." | |
f48ff2ae L |
5583 | #endif |
5584 | ||
29b0f896 | 5585 | found_reverse_match = 0; |
539e75ad | 5586 | addr_prefix_disp = -1; |
40fb9820 L |
5587 | |
5588 | memset (&suffix_check, 0, sizeof (suffix_check)); | |
e2195274 JB |
5589 | if (intel_syntax && i.broadcast) |
5590 | /* nothing */; | |
5591 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
40fb9820 L |
5592 | suffix_check.no_bsuf = 1; |
5593 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
5594 | suffix_check.no_wsuf = 1; | |
5595 | else if (i.suffix == SHORT_MNEM_SUFFIX) | |
5596 | suffix_check.no_ssuf = 1; | |
5597 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
5598 | suffix_check.no_lsuf = 1; | |
5599 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
5600 | suffix_check.no_qsuf = 1; | |
5601 | else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX) | |
7ce189b3 | 5602 | suffix_check.no_ldsuf = 1; |
29b0f896 | 5603 | |
83b16ac6 JB |
5604 | memset (&mnemsuf_check, 0, sizeof (mnemsuf_check)); |
5605 | if (intel_syntax) | |
5606 | { | |
5607 | switch (mnem_suffix) | |
5608 | { | |
5609 | case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break; | |
5610 | case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break; | |
5611 | case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break; | |
5612 | case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break; | |
5613 | case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break; | |
5614 | } | |
5615 | } | |
5616 | ||
01559ecc L |
5617 | /* Must have right number of operands. */ |
5618 | i.error = number_of_operands_mismatch; | |
5619 | ||
45aa61fe | 5620 | for (t = current_templates->start; t < current_templates->end; t++) |
29b0f896 | 5621 | { |
539e75ad | 5622 | addr_prefix_disp = -1; |
dbbc8b7e | 5623 | found_reverse_match = 0; |
539e75ad | 5624 | |
29b0f896 AM |
5625 | if (i.operands != t->operands) |
5626 | continue; | |
5627 | ||
50aecf8c | 5628 | /* Check processor support. */ |
a65babc9 | 5629 | i.error = unsupported; |
c0f3af97 L |
5630 | found_cpu_match = (cpu_flags_match (t) |
5631 | == CPU_FLAGS_PERFECT_MATCH); | |
50aecf8c L |
5632 | if (!found_cpu_match) |
5633 | continue; | |
5634 | ||
e1d4d893 | 5635 | /* Check AT&T mnemonic. */ |
a65babc9 | 5636 | i.error = unsupported_with_intel_mnemonic; |
e1d4d893 | 5637 | if (intel_mnemonic && t->opcode_modifier.attmnemonic) |
1efbbeb4 L |
5638 | continue; |
5639 | ||
e92bae62 | 5640 | /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */ |
a65babc9 | 5641 | i.error = unsupported_syntax; |
5c07affc | 5642 | if ((intel_syntax && t->opcode_modifier.attsyntax) |
e92bae62 L |
5643 | || (!intel_syntax && t->opcode_modifier.intelsyntax) |
5644 | || (intel64 && t->opcode_modifier.amd64) | |
5645 | || (!intel64 && t->opcode_modifier.intel64)) | |
1efbbeb4 L |
5646 | continue; |
5647 | ||
20592a94 | 5648 | /* Check the suffix, except for some instructions in intel mode. */ |
a65babc9 | 5649 | i.error = invalid_instruction_suffix; |
567e4e96 L |
5650 | if ((!intel_syntax || !t->opcode_modifier.ignoresize) |
5651 | && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf) | |
5652 | || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf) | |
5653 | || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf) | |
5654 | || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf) | |
5655 | || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf) | |
5656 | || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf))) | |
29b0f896 | 5657 | continue; |
83b16ac6 JB |
5658 | /* In Intel mode all mnemonic suffixes must be explicitly allowed. */ |
5659 | if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf) | |
5660 | || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf) | |
5661 | || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf) | |
5662 | || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf) | |
5663 | || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf) | |
5664 | || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf)) | |
5665 | continue; | |
29b0f896 | 5666 | |
3ac21baa JB |
5667 | size_match = operand_size_match (t); |
5668 | if (!size_match) | |
7d5e4556 | 5669 | continue; |
539e75ad | 5670 | |
5c07affc L |
5671 | for (j = 0; j < MAX_OPERANDS; j++) |
5672 | operand_types[j] = t->operand_types[j]; | |
5673 | ||
45aa61fe AM |
5674 | /* In general, don't allow 64-bit operands in 32-bit mode. */ |
5675 | if (i.suffix == QWORD_MNEM_SUFFIX | |
5676 | && flag_code != CODE_64BIT | |
5677 | && (intel_syntax | |
40fb9820 | 5678 | ? (!t->opcode_modifier.ignoresize |
625cbd7a | 5679 | && !t->opcode_modifier.broadcast |
45aa61fe AM |
5680 | && !intel_float_operand (t->name)) |
5681 | : intel_float_operand (t->name) != 2) | |
40fb9820 | 5682 | && ((!operand_types[0].bitfield.regmmx |
1b54b8d7 | 5683 | && !operand_types[0].bitfield.regsimd) |
40fb9820 | 5684 | || (!operand_types[t->operands > 1].bitfield.regmmx |
1b54b8d7 | 5685 | && !operand_types[t->operands > 1].bitfield.regsimd)) |
45aa61fe AM |
5686 | && (t->base_opcode != 0x0fc7 |
5687 | || t->extension_opcode != 1 /* cmpxchg8b */)) | |
5688 | continue; | |
5689 | ||
192dc9c6 JB |
5690 | /* In general, don't allow 32-bit operands on pre-386. */ |
5691 | else if (i.suffix == LONG_MNEM_SUFFIX | |
5692 | && !cpu_arch_flags.bitfield.cpui386 | |
5693 | && (intel_syntax | |
5694 | ? (!t->opcode_modifier.ignoresize | |
5695 | && !intel_float_operand (t->name)) | |
5696 | : intel_float_operand (t->name) != 2) | |
5697 | && ((!operand_types[0].bitfield.regmmx | |
1b54b8d7 | 5698 | && !operand_types[0].bitfield.regsimd) |
192dc9c6 | 5699 | || (!operand_types[t->operands > 1].bitfield.regmmx |
1b54b8d7 | 5700 | && !operand_types[t->operands > 1].bitfield.regsimd))) |
192dc9c6 JB |
5701 | continue; |
5702 | ||
29b0f896 | 5703 | /* Do not verify operands when there are none. */ |
50aecf8c | 5704 | else |
29b0f896 | 5705 | { |
c6fb90c8 | 5706 | if (!t->operands) |
2dbab7d5 L |
5707 | /* We've found a match; break out of loop. */ |
5708 | break; | |
29b0f896 | 5709 | } |
252b5132 | 5710 | |
539e75ad L |
5711 | /* Address size prefix will turn Disp64/Disp32/Disp16 operand |
5712 | into Disp32/Disp16/Disp32 operand. */ | |
5713 | if (i.prefix[ADDR_PREFIX] != 0) | |
5714 | { | |
40fb9820 | 5715 | /* There should be only one Disp operand. */ |
539e75ad L |
5716 | switch (flag_code) |
5717 | { | |
5718 | case CODE_16BIT: | |
40fb9820 L |
5719 | for (j = 0; j < MAX_OPERANDS; j++) |
5720 | { | |
5721 | if (operand_types[j].bitfield.disp16) | |
5722 | { | |
5723 | addr_prefix_disp = j; | |
5724 | operand_types[j].bitfield.disp32 = 1; | |
5725 | operand_types[j].bitfield.disp16 = 0; | |
5726 | break; | |
5727 | } | |
5728 | } | |
539e75ad L |
5729 | break; |
5730 | case CODE_32BIT: | |
40fb9820 L |
5731 | for (j = 0; j < MAX_OPERANDS; j++) |
5732 | { | |
5733 | if (operand_types[j].bitfield.disp32) | |
5734 | { | |
5735 | addr_prefix_disp = j; | |
5736 | operand_types[j].bitfield.disp32 = 0; | |
5737 | operand_types[j].bitfield.disp16 = 1; | |
5738 | break; | |
5739 | } | |
5740 | } | |
539e75ad L |
5741 | break; |
5742 | case CODE_64BIT: | |
40fb9820 L |
5743 | for (j = 0; j < MAX_OPERANDS; j++) |
5744 | { | |
5745 | if (operand_types[j].bitfield.disp64) | |
5746 | { | |
5747 | addr_prefix_disp = j; | |
5748 | operand_types[j].bitfield.disp64 = 0; | |
5749 | operand_types[j].bitfield.disp32 = 1; | |
5750 | break; | |
5751 | } | |
5752 | } | |
539e75ad L |
5753 | break; |
5754 | } | |
539e75ad L |
5755 | } |
5756 | ||
02a86693 L |
5757 | /* Force 0x8b encoding for "mov foo@GOT, %eax". */ |
5758 | if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0) | |
5759 | continue; | |
5760 | ||
56ffb741 | 5761 | /* We check register size if needed. */ |
e2195274 JB |
5762 | if (t->opcode_modifier.checkregsize) |
5763 | { | |
5764 | check_register = (1 << t->operands) - 1; | |
5765 | if (i.broadcast) | |
5766 | check_register &= ~(1 << i.broadcast->operand); | |
5767 | } | |
5768 | else | |
5769 | check_register = 0; | |
5770 | ||
c6fb90c8 | 5771 | overlap0 = operand_type_and (i.types[0], operand_types[0]); |
29b0f896 AM |
5772 | switch (t->operands) |
5773 | { | |
5774 | case 1: | |
40fb9820 | 5775 | if (!operand_type_match (overlap0, i.types[0])) |
29b0f896 AM |
5776 | continue; |
5777 | break; | |
5778 | case 2: | |
33eaf5de | 5779 | /* xchg %eax, %eax is a special case. It is an alias for nop |
8b38ad71 L |
5780 | only in 32bit mode and we can use opcode 0x90. In 64bit |
5781 | mode, we can't use 0x90 for xchg %eax, %eax since it should | |
5782 | zero-extend %eax to %rax. */ | |
5783 | if (flag_code == CODE_64BIT | |
5784 | && t->base_opcode == 0x90 | |
0dfbf9d7 L |
5785 | && operand_type_equal (&i.types [0], &acc32) |
5786 | && operand_type_equal (&i.types [1], &acc32)) | |
8b38ad71 | 5787 | continue; |
1212781b JB |
5788 | /* xrelease mov %eax, <disp> is another special case. It must not |
5789 | match the accumulator-only encoding of mov. */ | |
5790 | if (flag_code != CODE_64BIT | |
5791 | && i.hle_prefix | |
5792 | && t->base_opcode == 0xa0 | |
5793 | && i.types[0].bitfield.acc | |
5794 | && operand_type_check (i.types[1], anymem)) | |
5795 | continue; | |
f5eb1d70 JB |
5796 | /* Fall through. */ |
5797 | ||
5798 | case 3: | |
3ac21baa JB |
5799 | if (!(size_match & MATCH_STRAIGHT)) |
5800 | goto check_reverse; | |
64c49ab3 JB |
5801 | /* Reverse direction of operands if swapping is possible in the first |
5802 | place (operands need to be symmetric) and | |
5803 | - the load form is requested, and the template is a store form, | |
5804 | - the store form is requested, and the template is a load form, | |
5805 | - the non-default (swapped) form is requested. */ | |
5806 | overlap1 = operand_type_and (operand_types[0], operand_types[1]); | |
f5eb1d70 | 5807 | if (t->opcode_modifier.d && i.reg_operands == i.operands |
64c49ab3 JB |
5808 | && !operand_type_all_zero (&overlap1)) |
5809 | switch (i.dir_encoding) | |
5810 | { | |
5811 | case dir_encoding_load: | |
5812 | if (operand_type_check (operand_types[i.operands - 1], anymem) | |
5813 | || operand_types[i.operands - 1].bitfield.regmem) | |
5814 | goto check_reverse; | |
5815 | break; | |
5816 | ||
5817 | case dir_encoding_store: | |
5818 | if (!operand_type_check (operand_types[i.operands - 1], anymem) | |
5819 | && !operand_types[i.operands - 1].bitfield.regmem) | |
5820 | goto check_reverse; | |
5821 | break; | |
5822 | ||
5823 | case dir_encoding_swap: | |
5824 | goto check_reverse; | |
5825 | ||
5826 | case dir_encoding_default: | |
5827 | break; | |
5828 | } | |
86fa6981 | 5829 | /* If we want store form, we skip the current load. */ |
64c49ab3 JB |
5830 | if ((i.dir_encoding == dir_encoding_store |
5831 | || i.dir_encoding == dir_encoding_swap) | |
86fa6981 L |
5832 | && i.mem_operands == 0 |
5833 | && t->opcode_modifier.load) | |
fa99fab2 | 5834 | continue; |
1a0670f3 | 5835 | /* Fall through. */ |
f48ff2ae | 5836 | case 4: |
c0f3af97 | 5837 | case 5: |
c6fb90c8 | 5838 | overlap1 = operand_type_and (i.types[1], operand_types[1]); |
40fb9820 L |
5839 | if (!operand_type_match (overlap0, i.types[0]) |
5840 | || !operand_type_match (overlap1, i.types[1]) | |
e2195274 | 5841 | || ((check_register & 3) == 3 |
dc821c5f | 5842 | && !operand_type_register_match (i.types[0], |
40fb9820 | 5843 | operand_types[0], |
dc821c5f | 5844 | i.types[1], |
40fb9820 | 5845 | operand_types[1]))) |
29b0f896 AM |
5846 | { |
5847 | /* Check if other direction is valid ... */ | |
38e314eb | 5848 | if (!t->opcode_modifier.d) |
29b0f896 AM |
5849 | continue; |
5850 | ||
b6169b20 | 5851 | check_reverse: |
3ac21baa JB |
5852 | if (!(size_match & MATCH_REVERSE)) |
5853 | continue; | |
29b0f896 | 5854 | /* Try reversing direction of operands. */ |
f5eb1d70 JB |
5855 | overlap0 = operand_type_and (i.types[0], operand_types[i.operands - 1]); |
5856 | overlap1 = operand_type_and (i.types[i.operands - 1], operand_types[0]); | |
40fb9820 | 5857 | if (!operand_type_match (overlap0, i.types[0]) |
f5eb1d70 | 5858 | || !operand_type_match (overlap1, i.types[i.operands - 1]) |
45664ddb | 5859 | || (check_register |
dc821c5f | 5860 | && !operand_type_register_match (i.types[0], |
f5eb1d70 JB |
5861 | operand_types[i.operands - 1], |
5862 | i.types[i.operands - 1], | |
45664ddb | 5863 | operand_types[0]))) |
29b0f896 AM |
5864 | { |
5865 | /* Does not match either direction. */ | |
5866 | continue; | |
5867 | } | |
38e314eb | 5868 | /* found_reverse_match holds which of D or FloatR |
29b0f896 | 5869 | we've found. */ |
38e314eb JB |
5870 | if (!t->opcode_modifier.d) |
5871 | found_reverse_match = 0; | |
5872 | else if (operand_types[0].bitfield.tbyte) | |
8a2ed489 | 5873 | found_reverse_match = Opcode_FloatD; |
dbbc8b7e | 5874 | else if (operand_types[0].bitfield.xmmword |
f5eb1d70 | 5875 | || operand_types[i.operands - 1].bitfield.xmmword |
dbbc8b7e | 5876 | || operand_types[0].bitfield.regmmx |
f5eb1d70 | 5877 | || operand_types[i.operands - 1].bitfield.regmmx |
dbbc8b7e JB |
5878 | || is_any_vex_encoding(t)) |
5879 | found_reverse_match = (t->base_opcode & 0xee) != 0x6e | |
5880 | ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD; | |
8a2ed489 | 5881 | else |
38e314eb | 5882 | found_reverse_match = Opcode_D; |
40fb9820 | 5883 | if (t->opcode_modifier.floatr) |
8a2ed489 | 5884 | found_reverse_match |= Opcode_FloatR; |
29b0f896 | 5885 | } |
f48ff2ae | 5886 | else |
29b0f896 | 5887 | { |
f48ff2ae | 5888 | /* Found a forward 2 operand match here. */ |
d1cbb4db L |
5889 | switch (t->operands) |
5890 | { | |
c0f3af97 L |
5891 | case 5: |
5892 | overlap4 = operand_type_and (i.types[4], | |
5893 | operand_types[4]); | |
1a0670f3 | 5894 | /* Fall through. */ |
d1cbb4db | 5895 | case 4: |
c6fb90c8 L |
5896 | overlap3 = operand_type_and (i.types[3], |
5897 | operand_types[3]); | |
1a0670f3 | 5898 | /* Fall through. */ |
d1cbb4db | 5899 | case 3: |
c6fb90c8 L |
5900 | overlap2 = operand_type_and (i.types[2], |
5901 | operand_types[2]); | |
d1cbb4db L |
5902 | break; |
5903 | } | |
29b0f896 | 5904 | |
f48ff2ae L |
5905 | switch (t->operands) |
5906 | { | |
c0f3af97 L |
5907 | case 5: |
5908 | if (!operand_type_match (overlap4, i.types[4]) | |
dc821c5f | 5909 | || !operand_type_register_match (i.types[3], |
c0f3af97 | 5910 | operand_types[3], |
c0f3af97 L |
5911 | i.types[4], |
5912 | operand_types[4])) | |
5913 | continue; | |
1a0670f3 | 5914 | /* Fall through. */ |
f48ff2ae | 5915 | case 4: |
40fb9820 | 5916 | if (!operand_type_match (overlap3, i.types[3]) |
e2195274 JB |
5917 | || ((check_register & 0xa) == 0xa |
5918 | && !operand_type_register_match (i.types[1], | |
f7768225 JB |
5919 | operand_types[1], |
5920 | i.types[3], | |
e2195274 JB |
5921 | operand_types[3])) |
5922 | || ((check_register & 0xc) == 0xc | |
5923 | && !operand_type_register_match (i.types[2], | |
5924 | operand_types[2], | |
5925 | i.types[3], | |
5926 | operand_types[3]))) | |
f48ff2ae | 5927 | continue; |
1a0670f3 | 5928 | /* Fall through. */ |
f48ff2ae L |
5929 | case 3: |
5930 | /* Here we make use of the fact that there are no | |
23e42951 | 5931 | reverse match 3 operand instructions. */ |
40fb9820 | 5932 | if (!operand_type_match (overlap2, i.types[2]) |
e2195274 JB |
5933 | || ((check_register & 5) == 5 |
5934 | && !operand_type_register_match (i.types[0], | |
23e42951 JB |
5935 | operand_types[0], |
5936 | i.types[2], | |
e2195274 JB |
5937 | operand_types[2])) |
5938 | || ((check_register & 6) == 6 | |
5939 | && !operand_type_register_match (i.types[1], | |
5940 | operand_types[1], | |
5941 | i.types[2], | |
5942 | operand_types[2]))) | |
f48ff2ae L |
5943 | continue; |
5944 | break; | |
5945 | } | |
29b0f896 | 5946 | } |
f48ff2ae | 5947 | /* Found either forward/reverse 2, 3 or 4 operand match here: |
29b0f896 AM |
5948 | slip through to break. */ |
5949 | } | |
3629bb00 | 5950 | if (!found_cpu_match) |
dbbc8b7e | 5951 | continue; |
c0f3af97 | 5952 | |
5614d22c JB |
5953 | /* Check if vector and VEX operands are valid. */ |
5954 | if (check_VecOperands (t) || VEX_check_operands (t)) | |
5955 | { | |
5956 | specific_error = i.error; | |
5957 | continue; | |
5958 | } | |
a683cc34 | 5959 | |
29b0f896 AM |
5960 | /* We've found a match; break out of loop. */ |
5961 | break; | |
5962 | } | |
5963 | ||
5964 | if (t == current_templates->end) | |
5965 | { | |
5966 | /* We found no match. */ | |
a65babc9 | 5967 | const char *err_msg; |
5614d22c | 5968 | switch (specific_error ? specific_error : i.error) |
a65babc9 L |
5969 | { |
5970 | default: | |
5971 | abort (); | |
86e026a4 | 5972 | case operand_size_mismatch: |
a65babc9 L |
5973 | err_msg = _("operand size mismatch"); |
5974 | break; | |
5975 | case operand_type_mismatch: | |
5976 | err_msg = _("operand type mismatch"); | |
5977 | break; | |
5978 | case register_type_mismatch: | |
5979 | err_msg = _("register type mismatch"); | |
5980 | break; | |
5981 | case number_of_operands_mismatch: | |
5982 | err_msg = _("number of operands mismatch"); | |
5983 | break; | |
5984 | case invalid_instruction_suffix: | |
5985 | err_msg = _("invalid instruction suffix"); | |
5986 | break; | |
5987 | case bad_imm4: | |
4a2608e3 | 5988 | err_msg = _("constant doesn't fit in 4 bits"); |
a65babc9 | 5989 | break; |
a65babc9 L |
5990 | case unsupported_with_intel_mnemonic: |
5991 | err_msg = _("unsupported with Intel mnemonic"); | |
5992 | break; | |
5993 | case unsupported_syntax: | |
5994 | err_msg = _("unsupported syntax"); | |
5995 | break; | |
5996 | case unsupported: | |
35262a23 | 5997 | as_bad (_("unsupported instruction `%s'"), |
10efe3f6 L |
5998 | current_templates->start->name); |
5999 | return NULL; | |
6c30d220 L |
6000 | case invalid_vsib_address: |
6001 | err_msg = _("invalid VSIB address"); | |
6002 | break; | |
7bab8ab5 JB |
6003 | case invalid_vector_register_set: |
6004 | err_msg = _("mask, index, and destination registers must be distinct"); | |
6005 | break; | |
6c30d220 L |
6006 | case unsupported_vector_index_register: |
6007 | err_msg = _("unsupported vector index register"); | |
6008 | break; | |
43234a1e L |
6009 | case unsupported_broadcast: |
6010 | err_msg = _("unsupported broadcast"); | |
6011 | break; | |
43234a1e L |
6012 | case broadcast_needed: |
6013 | err_msg = _("broadcast is needed for operand of such type"); | |
6014 | break; | |
6015 | case unsupported_masking: | |
6016 | err_msg = _("unsupported masking"); | |
6017 | break; | |
6018 | case mask_not_on_destination: | |
6019 | err_msg = _("mask not on destination operand"); | |
6020 | break; | |
6021 | case no_default_mask: | |
6022 | err_msg = _("default mask isn't allowed"); | |
6023 | break; | |
6024 | case unsupported_rc_sae: | |
6025 | err_msg = _("unsupported static rounding/sae"); | |
6026 | break; | |
6027 | case rc_sae_operand_not_last_imm: | |
6028 | if (intel_syntax) | |
6029 | err_msg = _("RC/SAE operand must precede immediate operands"); | |
6030 | else | |
6031 | err_msg = _("RC/SAE operand must follow immediate operands"); | |
6032 | break; | |
6033 | case invalid_register_operand: | |
6034 | err_msg = _("invalid register operand"); | |
6035 | break; | |
a65babc9 L |
6036 | } |
6037 | as_bad (_("%s for `%s'"), err_msg, | |
891edac4 | 6038 | current_templates->start->name); |
fa99fab2 | 6039 | return NULL; |
29b0f896 | 6040 | } |
252b5132 | 6041 | |
29b0f896 AM |
6042 | if (!quiet_warnings) |
6043 | { | |
6044 | if (!intel_syntax | |
40fb9820 L |
6045 | && (i.types[0].bitfield.jumpabsolute |
6046 | != operand_types[0].bitfield.jumpabsolute)) | |
29b0f896 AM |
6047 | { |
6048 | as_warn (_("indirect %s without `*'"), t->name); | |
6049 | } | |
6050 | ||
40fb9820 L |
6051 | if (t->opcode_modifier.isprefix |
6052 | && t->opcode_modifier.ignoresize) | |
29b0f896 AM |
6053 | { |
6054 | /* Warn them that a data or address size prefix doesn't | |
6055 | affect assembly of the next line of code. */ | |
6056 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
6057 | } | |
6058 | } | |
6059 | ||
6060 | /* Copy the template we found. */ | |
6061 | i.tm = *t; | |
539e75ad L |
6062 | |
6063 | if (addr_prefix_disp != -1) | |
6064 | i.tm.operand_types[addr_prefix_disp] | |
6065 | = operand_types[addr_prefix_disp]; | |
6066 | ||
29b0f896 AM |
6067 | if (found_reverse_match) |
6068 | { | |
6069 | /* If we found a reverse match we must alter the opcode | |
6070 | direction bit. found_reverse_match holds bits to change | |
6071 | (different for int & float insns). */ | |
6072 | ||
6073 | i.tm.base_opcode ^= found_reverse_match; | |
6074 | ||
f5eb1d70 JB |
6075 | i.tm.operand_types[0] = operand_types[i.operands - 1]; |
6076 | i.tm.operand_types[i.operands - 1] = operand_types[0]; | |
29b0f896 AM |
6077 | } |
6078 | ||
fa99fab2 | 6079 | return t; |
29b0f896 AM |
6080 | } |
6081 | ||
6082 | static int | |
e3bb37b5 | 6083 | check_string (void) |
29b0f896 | 6084 | { |
40fb9820 L |
6085 | int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1; |
6086 | if (i.tm.operand_types[mem_op].bitfield.esseg) | |
29b0f896 AM |
6087 | { |
6088 | if (i.seg[0] != NULL && i.seg[0] != &es) | |
6089 | { | |
a87af027 | 6090 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
29b0f896 | 6091 | i.tm.name, |
a87af027 JB |
6092 | mem_op + 1, |
6093 | register_prefix); | |
29b0f896 AM |
6094 | return 0; |
6095 | } | |
6096 | /* There's only ever one segment override allowed per instruction. | |
6097 | This instruction possibly has a legal segment override on the | |
6098 | second operand, so copy the segment to where non-string | |
6099 | instructions store it, allowing common code. */ | |
6100 | i.seg[0] = i.seg[1]; | |
6101 | } | |
40fb9820 | 6102 | else if (i.tm.operand_types[mem_op + 1].bitfield.esseg) |
29b0f896 AM |
6103 | { |
6104 | if (i.seg[1] != NULL && i.seg[1] != &es) | |
6105 | { | |
a87af027 | 6106 | as_bad (_("`%s' operand %d must use `%ses' segment"), |
29b0f896 | 6107 | i.tm.name, |
a87af027 JB |
6108 | mem_op + 2, |
6109 | register_prefix); | |
29b0f896 AM |
6110 | return 0; |
6111 | } | |
6112 | } | |
6113 | return 1; | |
6114 | } | |
6115 | ||
6116 | static int | |
543613e9 | 6117 | process_suffix (void) |
29b0f896 AM |
6118 | { |
6119 | /* If matched instruction specifies an explicit instruction mnemonic | |
6120 | suffix, use it. */ | |
673fe0f0 | 6121 | if (i.tm.opcode_modifier.size == SIZE16) |
40fb9820 | 6122 | i.suffix = WORD_MNEM_SUFFIX; |
673fe0f0 | 6123 | else if (i.tm.opcode_modifier.size == SIZE32) |
40fb9820 | 6124 | i.suffix = LONG_MNEM_SUFFIX; |
673fe0f0 | 6125 | else if (i.tm.opcode_modifier.size == SIZE64) |
40fb9820 | 6126 | i.suffix = QWORD_MNEM_SUFFIX; |
29b0f896 AM |
6127 | else if (i.reg_operands) |
6128 | { | |
6129 | /* If there's no instruction mnemonic suffix we try to invent one | |
6130 | based on register operands. */ | |
6131 | if (!i.suffix) | |
6132 | { | |
6133 | /* We take i.suffix from the last register operand specified, | |
6134 | Destination register type is more significant than source | |
381d071f L |
6135 | register type. crc32 in SSE4.2 prefers source register |
6136 | type. */ | |
556059dd | 6137 | if (i.tm.base_opcode == 0xf20f38f0 && i.types[0].bitfield.reg) |
381d071f | 6138 | { |
556059dd JB |
6139 | if (i.types[0].bitfield.byte) |
6140 | i.suffix = BYTE_MNEM_SUFFIX; | |
6141 | else if (i.types[0].bitfield.word) | |
40fb9820 | 6142 | i.suffix = WORD_MNEM_SUFFIX; |
556059dd | 6143 | else if (i.types[0].bitfield.dword) |
40fb9820 | 6144 | i.suffix = LONG_MNEM_SUFFIX; |
556059dd | 6145 | else if (i.types[0].bitfield.qword) |
40fb9820 | 6146 | i.suffix = QWORD_MNEM_SUFFIX; |
381d071f L |
6147 | } |
6148 | ||
6149 | if (!i.suffix) | |
6150 | { | |
6151 | int op; | |
6152 | ||
556059dd | 6153 | if (i.tm.base_opcode == 0xf20f38f0) |
20592a94 L |
6154 | { |
6155 | /* We have to know the operand size for crc32. */ | |
6156 | as_bad (_("ambiguous memory operand size for `%s`"), | |
6157 | i.tm.name); | |
6158 | return 0; | |
6159 | } | |
6160 | ||
381d071f | 6161 | for (op = i.operands; --op >= 0;) |
b76bc5d5 JB |
6162 | if (!i.tm.operand_types[op].bitfield.inoutportreg |
6163 | && !i.tm.operand_types[op].bitfield.shiftcount) | |
381d071f | 6164 | { |
8819ada6 JB |
6165 | if (!i.types[op].bitfield.reg) |
6166 | continue; | |
6167 | if (i.types[op].bitfield.byte) | |
6168 | i.suffix = BYTE_MNEM_SUFFIX; | |
6169 | else if (i.types[op].bitfield.word) | |
6170 | i.suffix = WORD_MNEM_SUFFIX; | |
6171 | else if (i.types[op].bitfield.dword) | |
6172 | i.suffix = LONG_MNEM_SUFFIX; | |
6173 | else if (i.types[op].bitfield.qword) | |
6174 | i.suffix = QWORD_MNEM_SUFFIX; | |
6175 | else | |
6176 | continue; | |
6177 | break; | |
381d071f L |
6178 | } |
6179 | } | |
29b0f896 AM |
6180 | } |
6181 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
6182 | { | |
2eb952a4 L |
6183 | if (intel_syntax |
6184 | && i.tm.opcode_modifier.ignoresize | |
6185 | && i.tm.opcode_modifier.no_bsuf) | |
6186 | i.suffix = 0; | |
6187 | else if (!check_byte_reg ()) | |
29b0f896 AM |
6188 | return 0; |
6189 | } | |
6190 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
6191 | { | |
2eb952a4 L |
6192 | if (intel_syntax |
6193 | && i.tm.opcode_modifier.ignoresize | |
9f123b91 JB |
6194 | && i.tm.opcode_modifier.no_lsuf |
6195 | && !i.tm.opcode_modifier.todword | |
6196 | && !i.tm.opcode_modifier.toqword) | |
2eb952a4 L |
6197 | i.suffix = 0; |
6198 | else if (!check_long_reg ()) | |
29b0f896 AM |
6199 | return 0; |
6200 | } | |
6201 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
6202 | { | |
955e1e6a L |
6203 | if (intel_syntax |
6204 | && i.tm.opcode_modifier.ignoresize | |
9f123b91 JB |
6205 | && i.tm.opcode_modifier.no_qsuf |
6206 | && !i.tm.opcode_modifier.todword | |
6207 | && !i.tm.opcode_modifier.toqword) | |
955e1e6a L |
6208 | i.suffix = 0; |
6209 | else if (!check_qword_reg ()) | |
29b0f896 AM |
6210 | return 0; |
6211 | } | |
6212 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
6213 | { | |
2eb952a4 L |
6214 | if (intel_syntax |
6215 | && i.tm.opcode_modifier.ignoresize | |
6216 | && i.tm.opcode_modifier.no_wsuf) | |
6217 | i.suffix = 0; | |
6218 | else if (!check_word_reg ()) | |
29b0f896 AM |
6219 | return 0; |
6220 | } | |
40fb9820 | 6221 | else if (intel_syntax && i.tm.opcode_modifier.ignoresize) |
29b0f896 AM |
6222 | /* Do nothing if the instruction is going to ignore the prefix. */ |
6223 | ; | |
6224 | else | |
6225 | abort (); | |
6226 | } | |
40fb9820 | 6227 | else if (i.tm.opcode_modifier.defaultsize |
9306ca4a JB |
6228 | && !i.suffix |
6229 | /* exclude fldenv/frstor/fsave/fstenv */ | |
40fb9820 | 6230 | && i.tm.opcode_modifier.no_ssuf) |
29b0f896 AM |
6231 | { |
6232 | i.suffix = stackop_size; | |
6233 | } | |
9306ca4a JB |
6234 | else if (intel_syntax |
6235 | && !i.suffix | |
40fb9820 L |
6236 | && (i.tm.operand_types[0].bitfield.jumpabsolute |
6237 | || i.tm.opcode_modifier.jumpbyte | |
6238 | || i.tm.opcode_modifier.jumpintersegment | |
64e74474 AM |
6239 | || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */ |
6240 | && i.tm.extension_opcode <= 3))) | |
9306ca4a JB |
6241 | { |
6242 | switch (flag_code) | |
6243 | { | |
6244 | case CODE_64BIT: | |
40fb9820 | 6245 | if (!i.tm.opcode_modifier.no_qsuf) |
9306ca4a JB |
6246 | { |
6247 | i.suffix = QWORD_MNEM_SUFFIX; | |
6248 | break; | |
6249 | } | |
1a0670f3 | 6250 | /* Fall through. */ |
9306ca4a | 6251 | case CODE_32BIT: |
40fb9820 | 6252 | if (!i.tm.opcode_modifier.no_lsuf) |
9306ca4a JB |
6253 | i.suffix = LONG_MNEM_SUFFIX; |
6254 | break; | |
6255 | case CODE_16BIT: | |
40fb9820 | 6256 | if (!i.tm.opcode_modifier.no_wsuf) |
9306ca4a JB |
6257 | i.suffix = WORD_MNEM_SUFFIX; |
6258 | break; | |
6259 | } | |
6260 | } | |
252b5132 | 6261 | |
9306ca4a | 6262 | if (!i.suffix) |
29b0f896 | 6263 | { |
9306ca4a JB |
6264 | if (!intel_syntax) |
6265 | { | |
40fb9820 | 6266 | if (i.tm.opcode_modifier.w) |
9306ca4a | 6267 | { |
4eed87de AM |
6268 | as_bad (_("no instruction mnemonic suffix given and " |
6269 | "no register operands; can't size instruction")); | |
9306ca4a JB |
6270 | return 0; |
6271 | } | |
6272 | } | |
6273 | else | |
6274 | { | |
40fb9820 | 6275 | unsigned int suffixes; |
7ab9ffdd | 6276 | |
40fb9820 L |
6277 | suffixes = !i.tm.opcode_modifier.no_bsuf; |
6278 | if (!i.tm.opcode_modifier.no_wsuf) | |
6279 | suffixes |= 1 << 1; | |
6280 | if (!i.tm.opcode_modifier.no_lsuf) | |
6281 | suffixes |= 1 << 2; | |
fc4adea1 | 6282 | if (!i.tm.opcode_modifier.no_ldsuf) |
40fb9820 L |
6283 | suffixes |= 1 << 3; |
6284 | if (!i.tm.opcode_modifier.no_ssuf) | |
6285 | suffixes |= 1 << 4; | |
c2b9da16 | 6286 | if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf) |
40fb9820 L |
6287 | suffixes |= 1 << 5; |
6288 | ||
6289 | /* There are more than suffix matches. */ | |
6290 | if (i.tm.opcode_modifier.w | |
9306ca4a | 6291 | || ((suffixes & (suffixes - 1)) |
40fb9820 L |
6292 | && !i.tm.opcode_modifier.defaultsize |
6293 | && !i.tm.opcode_modifier.ignoresize)) | |
9306ca4a JB |
6294 | { |
6295 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); | |
6296 | return 0; | |
6297 | } | |
6298 | } | |
29b0f896 | 6299 | } |
252b5132 | 6300 | |
d2224064 JB |
6301 | /* Change the opcode based on the operand size given by i.suffix. */ |
6302 | switch (i.suffix) | |
29b0f896 | 6303 | { |
d2224064 JB |
6304 | /* Size floating point instruction. */ |
6305 | case LONG_MNEM_SUFFIX: | |
6306 | if (i.tm.opcode_modifier.floatmf) | |
6307 | { | |
6308 | i.tm.base_opcode ^= 4; | |
6309 | break; | |
6310 | } | |
6311 | /* fall through */ | |
6312 | case WORD_MNEM_SUFFIX: | |
6313 | case QWORD_MNEM_SUFFIX: | |
29b0f896 | 6314 | /* It's not a byte, select word/dword operation. */ |
40fb9820 | 6315 | if (i.tm.opcode_modifier.w) |
29b0f896 | 6316 | { |
40fb9820 | 6317 | if (i.tm.opcode_modifier.shortform) |
29b0f896 AM |
6318 | i.tm.base_opcode |= 8; |
6319 | else | |
6320 | i.tm.base_opcode |= 1; | |
6321 | } | |
d2224064 JB |
6322 | /* fall through */ |
6323 | case SHORT_MNEM_SUFFIX: | |
29b0f896 AM |
6324 | /* Now select between word & dword operations via the operand |
6325 | size prefix, except for instructions that will ignore this | |
6326 | prefix anyway. */ | |
75c0a438 L |
6327 | if (i.reg_operands > 0 |
6328 | && i.types[0].bitfield.reg | |
6329 | && i.tm.opcode_modifier.addrprefixopreg | |
6330 | && (i.tm.opcode_modifier.immext | |
6331 | || i.operands == 1)) | |
cb712a9e | 6332 | { |
ca61edf2 L |
6333 | /* The address size override prefix changes the size of the |
6334 | first operand. */ | |
40fb9820 | 6335 | if ((flag_code == CODE_32BIT |
75c0a438 | 6336 | && i.op[0].regs->reg_type.bitfield.word) |
40fb9820 | 6337 | || (flag_code != CODE_32BIT |
75c0a438 | 6338 | && i.op[0].regs->reg_type.bitfield.dword)) |
cb712a9e L |
6339 | if (!add_prefix (ADDR_PREFIX_OPCODE)) |
6340 | return 0; | |
6341 | } | |
6342 | else if (i.suffix != QWORD_MNEM_SUFFIX | |
40fb9820 L |
6343 | && !i.tm.opcode_modifier.ignoresize |
6344 | && !i.tm.opcode_modifier.floatmf | |
7a8655d2 JB |
6345 | && !i.tm.opcode_modifier.vex |
6346 | && !i.tm.opcode_modifier.vexopcode | |
6347 | && !is_evex_encoding (&i.tm) | |
cb712a9e L |
6348 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) |
6349 | || (flag_code == CODE_64BIT | |
40fb9820 | 6350 | && i.tm.opcode_modifier.jumpbyte))) |
24eab124 AM |
6351 | { |
6352 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
543613e9 | 6353 | |
40fb9820 | 6354 | if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */ |
29b0f896 | 6355 | prefix = ADDR_PREFIX_OPCODE; |
252b5132 | 6356 | |
29b0f896 AM |
6357 | if (!add_prefix (prefix)) |
6358 | return 0; | |
24eab124 | 6359 | } |
252b5132 | 6360 | |
29b0f896 AM |
6361 | /* Set mode64 for an operand. */ |
6362 | if (i.suffix == QWORD_MNEM_SUFFIX | |
9146926a | 6363 | && flag_code == CODE_64BIT |
d2224064 | 6364 | && !i.tm.opcode_modifier.norex64 |
46e883c5 | 6365 | /* Special case for xchg %rax,%rax. It is NOP and doesn't |
d2224064 JB |
6366 | need rex64. */ |
6367 | && ! (i.operands == 2 | |
6368 | && i.tm.base_opcode == 0x90 | |
6369 | && i.tm.extension_opcode == None | |
6370 | && operand_type_equal (&i.types [0], &acc64) | |
6371 | && operand_type_equal (&i.types [1], &acc64))) | |
6372 | i.rex |= REX_W; | |
3e73aa7c | 6373 | |
d2224064 | 6374 | break; |
29b0f896 | 6375 | } |
7ecd2f8b | 6376 | |
c0a30a9f L |
6377 | if (i.reg_operands != 0 |
6378 | && i.operands > 1 | |
6379 | && i.tm.opcode_modifier.addrprefixopreg | |
6380 | && !i.tm.opcode_modifier.immext) | |
6381 | { | |
6382 | /* Check invalid register operand when the address size override | |
6383 | prefix changes the size of register operands. */ | |
6384 | unsigned int op; | |
6385 | enum { need_word, need_dword, need_qword } need; | |
6386 | ||
6387 | if (flag_code == CODE_32BIT) | |
6388 | need = i.prefix[ADDR_PREFIX] ? need_word : need_dword; | |
6389 | else | |
6390 | { | |
6391 | if (i.prefix[ADDR_PREFIX]) | |
6392 | need = need_dword; | |
6393 | else | |
6394 | need = flag_code == CODE_64BIT ? need_qword : need_word; | |
6395 | } | |
6396 | ||
6397 | for (op = 0; op < i.operands; op++) | |
6398 | if (i.types[op].bitfield.reg | |
6399 | && ((need == need_word | |
6400 | && !i.op[op].regs->reg_type.bitfield.word) | |
6401 | || (need == need_dword | |
6402 | && !i.op[op].regs->reg_type.bitfield.dword) | |
6403 | || (need == need_qword | |
6404 | && !i.op[op].regs->reg_type.bitfield.qword))) | |
6405 | { | |
6406 | as_bad (_("invalid register operand size for `%s'"), | |
6407 | i.tm.name); | |
6408 | return 0; | |
6409 | } | |
6410 | } | |
6411 | ||
29b0f896 AM |
6412 | return 1; |
6413 | } | |
3e73aa7c | 6414 | |
29b0f896 | 6415 | static int |
543613e9 | 6416 | check_byte_reg (void) |
29b0f896 AM |
6417 | { |
6418 | int op; | |
543613e9 | 6419 | |
29b0f896 AM |
6420 | for (op = i.operands; --op >= 0;) |
6421 | { | |
dc821c5f JB |
6422 | /* Skip non-register operands. */ |
6423 | if (!i.types[op].bitfield.reg) | |
6424 | continue; | |
6425 | ||
29b0f896 AM |
6426 | /* If this is an eight bit register, it's OK. If it's the 16 or |
6427 | 32 bit version of an eight bit register, we will just use the | |
6428 | low portion, and that's OK too. */ | |
dc821c5f | 6429 | if (i.types[op].bitfield.byte) |
29b0f896 AM |
6430 | continue; |
6431 | ||
5a819eb9 JB |
6432 | /* I/O port address operands are OK too. */ |
6433 | if (i.tm.operand_types[op].bitfield.inoutportreg) | |
6434 | continue; | |
6435 | ||
9344ff29 L |
6436 | /* crc32 doesn't generate this warning. */ |
6437 | if (i.tm.base_opcode == 0xf20f38f0) | |
6438 | continue; | |
6439 | ||
dc821c5f JB |
6440 | if ((i.types[op].bitfield.word |
6441 | || i.types[op].bitfield.dword | |
6442 | || i.types[op].bitfield.qword) | |
5a819eb9 JB |
6443 | && i.op[op].regs->reg_num < 4 |
6444 | /* Prohibit these changes in 64bit mode, since the lowering | |
6445 | would be more complicated. */ | |
6446 | && flag_code != CODE_64BIT) | |
29b0f896 | 6447 | { |
29b0f896 | 6448 | #if REGISTER_WARNINGS |
5a819eb9 | 6449 | if (!quiet_warnings) |
a540244d L |
6450 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
6451 | register_prefix, | |
dc821c5f | 6452 | (i.op[op].regs + (i.types[op].bitfield.word |
29b0f896 AM |
6453 | ? REGNAM_AL - REGNAM_AX |
6454 | : REGNAM_AL - REGNAM_EAX))->reg_name, | |
a540244d | 6455 | register_prefix, |
29b0f896 AM |
6456 | i.op[op].regs->reg_name, |
6457 | i.suffix); | |
6458 | #endif | |
6459 | continue; | |
6460 | } | |
6461 | /* Any other register is bad. */ | |
dc821c5f | 6462 | if (i.types[op].bitfield.reg |
40fb9820 | 6463 | || i.types[op].bitfield.regmmx |
1b54b8d7 | 6464 | || i.types[op].bitfield.regsimd |
40fb9820 L |
6465 | || i.types[op].bitfield.sreg2 |
6466 | || i.types[op].bitfield.sreg3 | |
6467 | || i.types[op].bitfield.control | |
6468 | || i.types[op].bitfield.debug | |
ca0d63fe | 6469 | || i.types[op].bitfield.test) |
29b0f896 | 6470 | { |
a540244d L |
6471 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6472 | register_prefix, | |
29b0f896 AM |
6473 | i.op[op].regs->reg_name, |
6474 | i.tm.name, | |
6475 | i.suffix); | |
6476 | return 0; | |
6477 | } | |
6478 | } | |
6479 | return 1; | |
6480 | } | |
6481 | ||
6482 | static int | |
e3bb37b5 | 6483 | check_long_reg (void) |
29b0f896 AM |
6484 | { |
6485 | int op; | |
6486 | ||
6487 | for (op = i.operands; --op >= 0;) | |
dc821c5f JB |
6488 | /* Skip non-register operands. */ |
6489 | if (!i.types[op].bitfield.reg) | |
6490 | continue; | |
29b0f896 AM |
6491 | /* Reject eight bit registers, except where the template requires |
6492 | them. (eg. movzb) */ | |
dc821c5f JB |
6493 | else if (i.types[op].bitfield.byte |
6494 | && (i.tm.operand_types[op].bitfield.reg | |
6495 | || i.tm.operand_types[op].bitfield.acc) | |
6496 | && (i.tm.operand_types[op].bitfield.word | |
6497 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 6498 | { |
a540244d L |
6499 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6500 | register_prefix, | |
29b0f896 AM |
6501 | i.op[op].regs->reg_name, |
6502 | i.tm.name, | |
6503 | i.suffix); | |
6504 | return 0; | |
6505 | } | |
e4630f71 | 6506 | /* Warn if the e prefix on a general reg is missing. */ |
29b0f896 | 6507 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
dc821c5f JB |
6508 | && i.types[op].bitfield.word |
6509 | && (i.tm.operand_types[op].bitfield.reg | |
6510 | || i.tm.operand_types[op].bitfield.acc) | |
6511 | && i.tm.operand_types[op].bitfield.dword) | |
29b0f896 AM |
6512 | { |
6513 | /* Prohibit these changes in the 64bit mode, since the | |
6514 | lowering is more complicated. */ | |
6515 | if (flag_code == CODE_64BIT) | |
252b5132 | 6516 | { |
2b5d6a91 | 6517 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
2ca3ace5 | 6518 | register_prefix, i.op[op].regs->reg_name, |
29b0f896 AM |
6519 | i.suffix); |
6520 | return 0; | |
252b5132 | 6521 | } |
29b0f896 | 6522 | #if REGISTER_WARNINGS |
cecf1424 JB |
6523 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
6524 | register_prefix, | |
6525 | (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name, | |
6526 | register_prefix, i.op[op].regs->reg_name, i.suffix); | |
29b0f896 | 6527 | #endif |
252b5132 | 6528 | } |
e4630f71 | 6529 | /* Warn if the r prefix on a general reg is present. */ |
dc821c5f JB |
6530 | else if (i.types[op].bitfield.qword |
6531 | && (i.tm.operand_types[op].bitfield.reg | |
6532 | || i.tm.operand_types[op].bitfield.acc) | |
6533 | && i.tm.operand_types[op].bitfield.dword) | |
252b5132 | 6534 | { |
34828aad | 6535 | if (intel_syntax |
ca61edf2 | 6536 | && i.tm.opcode_modifier.toqword |
1b54b8d7 | 6537 | && !i.types[0].bitfield.regsimd) |
34828aad | 6538 | { |
ca61edf2 | 6539 | /* Convert to QWORD. We want REX byte. */ |
34828aad L |
6540 | i.suffix = QWORD_MNEM_SUFFIX; |
6541 | } | |
6542 | else | |
6543 | { | |
2b5d6a91 | 6544 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
6545 | register_prefix, i.op[op].regs->reg_name, |
6546 | i.suffix); | |
6547 | return 0; | |
6548 | } | |
29b0f896 AM |
6549 | } |
6550 | return 1; | |
6551 | } | |
252b5132 | 6552 | |
29b0f896 | 6553 | static int |
e3bb37b5 | 6554 | check_qword_reg (void) |
29b0f896 AM |
6555 | { |
6556 | int op; | |
252b5132 | 6557 | |
29b0f896 | 6558 | for (op = i.operands; --op >= 0; ) |
dc821c5f JB |
6559 | /* Skip non-register operands. */ |
6560 | if (!i.types[op].bitfield.reg) | |
6561 | continue; | |
29b0f896 AM |
6562 | /* Reject eight bit registers, except where the template requires |
6563 | them. (eg. movzb) */ | |
dc821c5f JB |
6564 | else if (i.types[op].bitfield.byte |
6565 | && (i.tm.operand_types[op].bitfield.reg | |
6566 | || i.tm.operand_types[op].bitfield.acc) | |
6567 | && (i.tm.operand_types[op].bitfield.word | |
6568 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 6569 | { |
a540244d L |
6570 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6571 | register_prefix, | |
29b0f896 AM |
6572 | i.op[op].regs->reg_name, |
6573 | i.tm.name, | |
6574 | i.suffix); | |
6575 | return 0; | |
6576 | } | |
e4630f71 | 6577 | /* Warn if the r prefix on a general reg is missing. */ |
dc821c5f JB |
6578 | else if ((i.types[op].bitfield.word |
6579 | || i.types[op].bitfield.dword) | |
6580 | && (i.tm.operand_types[op].bitfield.reg | |
6581 | || i.tm.operand_types[op].bitfield.acc) | |
6582 | && i.tm.operand_types[op].bitfield.qword) | |
29b0f896 AM |
6583 | { |
6584 | /* Prohibit these changes in the 64bit mode, since the | |
6585 | lowering is more complicated. */ | |
34828aad | 6586 | if (intel_syntax |
ca61edf2 | 6587 | && i.tm.opcode_modifier.todword |
1b54b8d7 | 6588 | && !i.types[0].bitfield.regsimd) |
34828aad | 6589 | { |
ca61edf2 | 6590 | /* Convert to DWORD. We don't want REX byte. */ |
34828aad L |
6591 | i.suffix = LONG_MNEM_SUFFIX; |
6592 | } | |
6593 | else | |
6594 | { | |
2b5d6a91 | 6595 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
6596 | register_prefix, i.op[op].regs->reg_name, |
6597 | i.suffix); | |
6598 | return 0; | |
6599 | } | |
252b5132 | 6600 | } |
29b0f896 AM |
6601 | return 1; |
6602 | } | |
252b5132 | 6603 | |
29b0f896 | 6604 | static int |
e3bb37b5 | 6605 | check_word_reg (void) |
29b0f896 AM |
6606 | { |
6607 | int op; | |
6608 | for (op = i.operands; --op >= 0;) | |
dc821c5f JB |
6609 | /* Skip non-register operands. */ |
6610 | if (!i.types[op].bitfield.reg) | |
6611 | continue; | |
29b0f896 AM |
6612 | /* Reject eight bit registers, except where the template requires |
6613 | them. (eg. movzb) */ | |
dc821c5f JB |
6614 | else if (i.types[op].bitfield.byte |
6615 | && (i.tm.operand_types[op].bitfield.reg | |
6616 | || i.tm.operand_types[op].bitfield.acc) | |
6617 | && (i.tm.operand_types[op].bitfield.word | |
6618 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 6619 | { |
a540244d L |
6620 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
6621 | register_prefix, | |
29b0f896 AM |
6622 | i.op[op].regs->reg_name, |
6623 | i.tm.name, | |
6624 | i.suffix); | |
6625 | return 0; | |
6626 | } | |
e4630f71 | 6627 | /* Warn if the e or r prefix on a general reg is present. */ |
29b0f896 | 6628 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
dc821c5f JB |
6629 | && (i.types[op].bitfield.dword |
6630 | || i.types[op].bitfield.qword) | |
6631 | && (i.tm.operand_types[op].bitfield.reg | |
6632 | || i.tm.operand_types[op].bitfield.acc) | |
6633 | && i.tm.operand_types[op].bitfield.word) | |
252b5132 | 6634 | { |
29b0f896 AM |
6635 | /* Prohibit these changes in the 64bit mode, since the |
6636 | lowering is more complicated. */ | |
6637 | if (flag_code == CODE_64BIT) | |
252b5132 | 6638 | { |
2b5d6a91 | 6639 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
2ca3ace5 | 6640 | register_prefix, i.op[op].regs->reg_name, |
29b0f896 AM |
6641 | i.suffix); |
6642 | return 0; | |
252b5132 | 6643 | } |
29b0f896 | 6644 | #if REGISTER_WARNINGS |
cecf1424 JB |
6645 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
6646 | register_prefix, | |
6647 | (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name, | |
6648 | register_prefix, i.op[op].regs->reg_name, i.suffix); | |
29b0f896 AM |
6649 | #endif |
6650 | } | |
6651 | return 1; | |
6652 | } | |
252b5132 | 6653 | |
29b0f896 | 6654 | static int |
40fb9820 | 6655 | update_imm (unsigned int j) |
29b0f896 | 6656 | { |
bc0844ae | 6657 | i386_operand_type overlap = i.types[j]; |
40fb9820 L |
6658 | if ((overlap.bitfield.imm8 |
6659 | || overlap.bitfield.imm8s | |
6660 | || overlap.bitfield.imm16 | |
6661 | || overlap.bitfield.imm32 | |
6662 | || overlap.bitfield.imm32s | |
6663 | || overlap.bitfield.imm64) | |
0dfbf9d7 L |
6664 | && !operand_type_equal (&overlap, &imm8) |
6665 | && !operand_type_equal (&overlap, &imm8s) | |
6666 | && !operand_type_equal (&overlap, &imm16) | |
6667 | && !operand_type_equal (&overlap, &imm32) | |
6668 | && !operand_type_equal (&overlap, &imm32s) | |
6669 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 AM |
6670 | { |
6671 | if (i.suffix) | |
6672 | { | |
40fb9820 L |
6673 | i386_operand_type temp; |
6674 | ||
0dfbf9d7 | 6675 | operand_type_set (&temp, 0); |
7ab9ffdd | 6676 | if (i.suffix == BYTE_MNEM_SUFFIX) |
40fb9820 L |
6677 | { |
6678 | temp.bitfield.imm8 = overlap.bitfield.imm8; | |
6679 | temp.bitfield.imm8s = overlap.bitfield.imm8s; | |
6680 | } | |
6681 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
6682 | temp.bitfield.imm16 = overlap.bitfield.imm16; | |
6683 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
6684 | { | |
6685 | temp.bitfield.imm64 = overlap.bitfield.imm64; | |
6686 | temp.bitfield.imm32s = overlap.bitfield.imm32s; | |
6687 | } | |
6688 | else | |
6689 | temp.bitfield.imm32 = overlap.bitfield.imm32; | |
6690 | overlap = temp; | |
29b0f896 | 6691 | } |
0dfbf9d7 L |
6692 | else if (operand_type_equal (&overlap, &imm16_32_32s) |
6693 | || operand_type_equal (&overlap, &imm16_32) | |
6694 | || operand_type_equal (&overlap, &imm16_32s)) | |
29b0f896 | 6695 | { |
40fb9820 | 6696 | if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
65da13b5 | 6697 | overlap = imm16; |
40fb9820 | 6698 | else |
65da13b5 | 6699 | overlap = imm32s; |
29b0f896 | 6700 | } |
0dfbf9d7 L |
6701 | if (!operand_type_equal (&overlap, &imm8) |
6702 | && !operand_type_equal (&overlap, &imm8s) | |
6703 | && !operand_type_equal (&overlap, &imm16) | |
6704 | && !operand_type_equal (&overlap, &imm32) | |
6705 | && !operand_type_equal (&overlap, &imm32s) | |
6706 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 | 6707 | { |
4eed87de AM |
6708 | as_bad (_("no instruction mnemonic suffix given; " |
6709 | "can't determine immediate size")); | |
29b0f896 AM |
6710 | return 0; |
6711 | } | |
6712 | } | |
40fb9820 | 6713 | i.types[j] = overlap; |
29b0f896 | 6714 | |
40fb9820 L |
6715 | return 1; |
6716 | } | |
6717 | ||
6718 | static int | |
6719 | finalize_imm (void) | |
6720 | { | |
bc0844ae | 6721 | unsigned int j, n; |
29b0f896 | 6722 | |
bc0844ae L |
6723 | /* Update the first 2 immediate operands. */ |
6724 | n = i.operands > 2 ? 2 : i.operands; | |
6725 | if (n) | |
6726 | { | |
6727 | for (j = 0; j < n; j++) | |
6728 | if (update_imm (j) == 0) | |
6729 | return 0; | |
40fb9820 | 6730 | |
bc0844ae L |
6731 | /* The 3rd operand can't be immediate operand. */ |
6732 | gas_assert (operand_type_check (i.types[2], imm) == 0); | |
6733 | } | |
29b0f896 AM |
6734 | |
6735 | return 1; | |
6736 | } | |
6737 | ||
6738 | static int | |
e3bb37b5 | 6739 | process_operands (void) |
29b0f896 AM |
6740 | { |
6741 | /* Default segment register this instruction will use for memory | |
6742 | accesses. 0 means unknown. This is only for optimizing out | |
6743 | unnecessary segment overrides. */ | |
6744 | const seg_entry *default_seg = 0; | |
6745 | ||
2426c15f | 6746 | if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv) |
29b0f896 | 6747 | { |
91d6fa6a NC |
6748 | unsigned int dupl = i.operands; |
6749 | unsigned int dest = dupl - 1; | |
9fcfb3d7 L |
6750 | unsigned int j; |
6751 | ||
c0f3af97 | 6752 | /* The destination must be an xmm register. */ |
9c2799c2 | 6753 | gas_assert (i.reg_operands |
91d6fa6a | 6754 | && MAX_OPERANDS > dupl |
7ab9ffdd | 6755 | && operand_type_equal (&i.types[dest], ®xmm)); |
c0f3af97 | 6756 | |
1b54b8d7 JB |
6757 | if (i.tm.operand_types[0].bitfield.acc |
6758 | && i.tm.operand_types[0].bitfield.xmmword) | |
e2ec9d29 | 6759 | { |
8cd7925b | 6760 | if (i.tm.opcode_modifier.vexsources == VEX3SOURCES) |
c0f3af97 L |
6761 | { |
6762 | /* Keep xmm0 for instructions with VEX prefix and 3 | |
6763 | sources. */ | |
1b54b8d7 JB |
6764 | i.tm.operand_types[0].bitfield.acc = 0; |
6765 | i.tm.operand_types[0].bitfield.regsimd = 1; | |
c0f3af97 L |
6766 | goto duplicate; |
6767 | } | |
e2ec9d29 | 6768 | else |
c0f3af97 L |
6769 | { |
6770 | /* We remove the first xmm0 and keep the number of | |
6771 | operands unchanged, which in fact duplicates the | |
6772 | destination. */ | |
6773 | for (j = 1; j < i.operands; j++) | |
6774 | { | |
6775 | i.op[j - 1] = i.op[j]; | |
6776 | i.types[j - 1] = i.types[j]; | |
6777 | i.tm.operand_types[j - 1] = i.tm.operand_types[j]; | |
6778 | } | |
6779 | } | |
6780 | } | |
6781 | else if (i.tm.opcode_modifier.implicit1stxmm0) | |
7ab9ffdd | 6782 | { |
91d6fa6a | 6783 | gas_assert ((MAX_OPERANDS - 1) > dupl |
8cd7925b L |
6784 | && (i.tm.opcode_modifier.vexsources |
6785 | == VEX3SOURCES)); | |
c0f3af97 L |
6786 | |
6787 | /* Add the implicit xmm0 for instructions with VEX prefix | |
6788 | and 3 sources. */ | |
6789 | for (j = i.operands; j > 0; j--) | |
6790 | { | |
6791 | i.op[j] = i.op[j - 1]; | |
6792 | i.types[j] = i.types[j - 1]; | |
6793 | i.tm.operand_types[j] = i.tm.operand_types[j - 1]; | |
6794 | } | |
6795 | i.op[0].regs | |
6796 | = (const reg_entry *) hash_find (reg_hash, "xmm0"); | |
7ab9ffdd | 6797 | i.types[0] = regxmm; |
c0f3af97 L |
6798 | i.tm.operand_types[0] = regxmm; |
6799 | ||
6800 | i.operands += 2; | |
6801 | i.reg_operands += 2; | |
6802 | i.tm.operands += 2; | |
6803 | ||
91d6fa6a | 6804 | dupl++; |
c0f3af97 | 6805 | dest++; |
91d6fa6a NC |
6806 | i.op[dupl] = i.op[dest]; |
6807 | i.types[dupl] = i.types[dest]; | |
6808 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
e2ec9d29 | 6809 | } |
c0f3af97 L |
6810 | else |
6811 | { | |
6812 | duplicate: | |
6813 | i.operands++; | |
6814 | i.reg_operands++; | |
6815 | i.tm.operands++; | |
6816 | ||
91d6fa6a NC |
6817 | i.op[dupl] = i.op[dest]; |
6818 | i.types[dupl] = i.types[dest]; | |
6819 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
c0f3af97 L |
6820 | } |
6821 | ||
6822 | if (i.tm.opcode_modifier.immext) | |
6823 | process_immext (); | |
6824 | } | |
1b54b8d7 JB |
6825 | else if (i.tm.operand_types[0].bitfield.acc |
6826 | && i.tm.operand_types[0].bitfield.xmmword) | |
c0f3af97 L |
6827 | { |
6828 | unsigned int j; | |
6829 | ||
9fcfb3d7 L |
6830 | for (j = 1; j < i.operands; j++) |
6831 | { | |
6832 | i.op[j - 1] = i.op[j]; | |
6833 | i.types[j - 1] = i.types[j]; | |
6834 | ||
6835 | /* We need to adjust fields in i.tm since they are used by | |
6836 | build_modrm_byte. */ | |
6837 | i.tm.operand_types [j - 1] = i.tm.operand_types [j]; | |
6838 | } | |
6839 | ||
e2ec9d29 L |
6840 | i.operands--; |
6841 | i.reg_operands--; | |
e2ec9d29 L |
6842 | i.tm.operands--; |
6843 | } | |
920d2ddc IT |
6844 | else if (i.tm.opcode_modifier.implicitquadgroup) |
6845 | { | |
a477a8c4 JB |
6846 | unsigned int regnum, first_reg_in_group, last_reg_in_group; |
6847 | ||
920d2ddc | 6848 | /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */ |
10c17abd | 6849 | gas_assert (i.operands >= 2 && i.types[1].bitfield.regsimd); |
a477a8c4 JB |
6850 | regnum = register_number (i.op[1].regs); |
6851 | first_reg_in_group = regnum & ~3; | |
6852 | last_reg_in_group = first_reg_in_group + 3; | |
6853 | if (regnum != first_reg_in_group) | |
6854 | as_warn (_("source register `%s%s' implicitly denotes" | |
6855 | " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"), | |
6856 | register_prefix, i.op[1].regs->reg_name, | |
6857 | register_prefix, i.op[1].regs->reg_name, first_reg_in_group, | |
6858 | register_prefix, i.op[1].regs->reg_name, last_reg_in_group, | |
6859 | i.tm.name); | |
6860 | } | |
e2ec9d29 L |
6861 | else if (i.tm.opcode_modifier.regkludge) |
6862 | { | |
6863 | /* The imul $imm, %reg instruction is converted into | |
6864 | imul $imm, %reg, %reg, and the clr %reg instruction | |
6865 | is converted into xor %reg, %reg. */ | |
6866 | ||
6867 | unsigned int first_reg_op; | |
6868 | ||
6869 | if (operand_type_check (i.types[0], reg)) | |
6870 | first_reg_op = 0; | |
6871 | else | |
6872 | first_reg_op = 1; | |
6873 | /* Pretend we saw the extra register operand. */ | |
9c2799c2 | 6874 | gas_assert (i.reg_operands == 1 |
7ab9ffdd | 6875 | && i.op[first_reg_op + 1].regs == 0); |
e2ec9d29 L |
6876 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; |
6877 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
6878 | i.operands++; | |
6879 | i.reg_operands++; | |
29b0f896 AM |
6880 | } |
6881 | ||
40fb9820 | 6882 | if (i.tm.opcode_modifier.shortform) |
29b0f896 | 6883 | { |
40fb9820 L |
6884 | if (i.types[0].bitfield.sreg2 |
6885 | || i.types[0].bitfield.sreg3) | |
29b0f896 | 6886 | { |
4eed87de AM |
6887 | if (i.tm.base_opcode == POP_SEG_SHORT |
6888 | && i.op[0].regs->reg_num == 1) | |
29b0f896 | 6889 | { |
a87af027 | 6890 | as_bad (_("you can't `pop %scs'"), register_prefix); |
4eed87de | 6891 | return 0; |
29b0f896 | 6892 | } |
4eed87de AM |
6893 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); |
6894 | if ((i.op[0].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 6895 | i.rex |= REX_B; |
4eed87de AM |
6896 | } |
6897 | else | |
6898 | { | |
7ab9ffdd | 6899 | /* The register or float register operand is in operand |
85f10a01 | 6900 | 0 or 1. */ |
40fb9820 | 6901 | unsigned int op; |
7ab9ffdd | 6902 | |
ca0d63fe | 6903 | if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte) |
7ab9ffdd L |
6904 | || operand_type_check (i.types[0], reg)) |
6905 | op = 0; | |
6906 | else | |
6907 | op = 1; | |
4eed87de AM |
6908 | /* Register goes in low 3 bits of opcode. */ |
6909 | i.tm.base_opcode |= i.op[op].regs->reg_num; | |
6910 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 6911 | i.rex |= REX_B; |
40fb9820 | 6912 | if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 | 6913 | { |
4eed87de AM |
6914 | /* Warn about some common errors, but press on regardless. |
6915 | The first case can be generated by gcc (<= 2.8.1). */ | |
6916 | if (i.operands == 2) | |
6917 | { | |
6918 | /* Reversed arguments on faddp, fsubp, etc. */ | |
a540244d | 6919 | as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, |
d8a1b51e JB |
6920 | register_prefix, i.op[!intel_syntax].regs->reg_name, |
6921 | register_prefix, i.op[intel_syntax].regs->reg_name); | |
4eed87de AM |
6922 | } |
6923 | else | |
6924 | { | |
6925 | /* Extraneous `l' suffix on fp insn. */ | |
a540244d L |
6926 | as_warn (_("translating to `%s %s%s'"), i.tm.name, |
6927 | register_prefix, i.op[0].regs->reg_name); | |
4eed87de | 6928 | } |
29b0f896 AM |
6929 | } |
6930 | } | |
6931 | } | |
40fb9820 | 6932 | else if (i.tm.opcode_modifier.modrm) |
29b0f896 AM |
6933 | { |
6934 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
52271982 AM |
6935 | must be put into the modrm byte). Now, we make the modrm and |
6936 | index base bytes based on all the info we've collected. */ | |
29b0f896 AM |
6937 | |
6938 | default_seg = build_modrm_byte (); | |
6939 | } | |
8a2ed489 | 6940 | else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32) |
29b0f896 AM |
6941 | { |
6942 | default_seg = &ds; | |
6943 | } | |
40fb9820 | 6944 | else if (i.tm.opcode_modifier.isstring) |
29b0f896 AM |
6945 | { |
6946 | /* For the string instructions that allow a segment override | |
6947 | on one of their operands, the default segment is ds. */ | |
6948 | default_seg = &ds; | |
6949 | } | |
6950 | ||
75178d9d L |
6951 | if (i.tm.base_opcode == 0x8d /* lea */ |
6952 | && i.seg[0] | |
6953 | && !quiet_warnings) | |
30123838 | 6954 | as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); |
52271982 AM |
6955 | |
6956 | /* If a segment was explicitly specified, and the specified segment | |
6957 | is not the default, use an opcode prefix to select it. If we | |
6958 | never figured out what the default segment is, then default_seg | |
6959 | will be zero at this point, and the specified segment prefix will | |
6960 | always be used. */ | |
29b0f896 AM |
6961 | if ((i.seg[0]) && (i.seg[0] != default_seg)) |
6962 | { | |
6963 | if (!add_prefix (i.seg[0]->seg_prefix)) | |
6964 | return 0; | |
6965 | } | |
6966 | return 1; | |
6967 | } | |
6968 | ||
6969 | static const seg_entry * | |
e3bb37b5 | 6970 | build_modrm_byte (void) |
29b0f896 AM |
6971 | { |
6972 | const seg_entry *default_seg = 0; | |
c0f3af97 | 6973 | unsigned int source, dest; |
8cd7925b | 6974 | int vex_3_sources; |
c0f3af97 | 6975 | |
8cd7925b | 6976 | vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES; |
c0f3af97 L |
6977 | if (vex_3_sources) |
6978 | { | |
91d6fa6a | 6979 | unsigned int nds, reg_slot; |
4c2c6516 | 6980 | expressionS *exp; |
c0f3af97 | 6981 | |
6b8d3588 | 6982 | dest = i.operands - 1; |
c0f3af97 | 6983 | nds = dest - 1; |
922d8de8 | 6984 | |
a683cc34 | 6985 | /* There are 2 kinds of instructions: |
bed3d976 JB |
6986 | 1. 5 operands: 4 register operands or 3 register operands |
6987 | plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and | |
6988 | VexW0 or VexW1. The destination must be either XMM, YMM or | |
43234a1e | 6989 | ZMM register. |
bed3d976 | 6990 | 2. 4 operands: 4 register operands or 3 register operands |
2f1bada2 | 6991 | plus 1 memory operand, with VexXDS. */ |
922d8de8 | 6992 | gas_assert ((i.reg_operands == 4 |
bed3d976 JB |
6993 | || (i.reg_operands == 3 && i.mem_operands == 1)) |
6994 | && i.tm.opcode_modifier.vexvvvv == VEXXDS | |
dcd7e323 JB |
6995 | && i.tm.opcode_modifier.vexw |
6996 | && i.tm.operand_types[dest].bitfield.regsimd); | |
a683cc34 | 6997 | |
48db9223 JB |
6998 | /* If VexW1 is set, the first non-immediate operand is the source and |
6999 | the second non-immediate one is encoded in the immediate operand. */ | |
7000 | if (i.tm.opcode_modifier.vexw == VEXW1) | |
7001 | { | |
7002 | source = i.imm_operands; | |
7003 | reg_slot = i.imm_operands + 1; | |
7004 | } | |
7005 | else | |
7006 | { | |
7007 | source = i.imm_operands + 1; | |
7008 | reg_slot = i.imm_operands; | |
7009 | } | |
7010 | ||
a683cc34 | 7011 | if (i.imm_operands == 0) |
bed3d976 JB |
7012 | { |
7013 | /* When there is no immediate operand, generate an 8bit | |
7014 | immediate operand to encode the first operand. */ | |
7015 | exp = &im_expressions[i.imm_operands++]; | |
7016 | i.op[i.operands].imms = exp; | |
7017 | i.types[i.operands] = imm8; | |
7018 | i.operands++; | |
7019 | ||
7020 | gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd); | |
7021 | exp->X_op = O_constant; | |
7022 | exp->X_add_number = register_number (i.op[reg_slot].regs) << 4; | |
43234a1e L |
7023 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
7024 | } | |
922d8de8 | 7025 | else |
bed3d976 JB |
7026 | { |
7027 | unsigned int imm_slot; | |
a683cc34 | 7028 | |
2f1bada2 JB |
7029 | gas_assert (i.imm_operands == 1 && i.types[0].bitfield.vec_imm4); |
7030 | ||
bed3d976 JB |
7031 | if (i.tm.opcode_modifier.immext) |
7032 | { | |
7033 | /* When ImmExt is set, the immediate byte is the last | |
7034 | operand. */ | |
7035 | imm_slot = i.operands - 1; | |
7036 | source--; | |
7037 | reg_slot--; | |
7038 | } | |
7039 | else | |
7040 | { | |
7041 | imm_slot = 0; | |
7042 | ||
7043 | /* Turn on Imm8 so that output_imm will generate it. */ | |
7044 | i.types[imm_slot].bitfield.imm8 = 1; | |
7045 | } | |
7046 | ||
7047 | gas_assert (i.tm.operand_types[reg_slot].bitfield.regsimd); | |
7048 | i.op[imm_slot].imms->X_add_number | |
7049 | |= register_number (i.op[reg_slot].regs) << 4; | |
43234a1e | 7050 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
bed3d976 | 7051 | } |
a683cc34 | 7052 | |
10c17abd | 7053 | gas_assert (i.tm.operand_types[nds].bitfield.regsimd); |
dae39acc | 7054 | i.vex.register_specifier = i.op[nds].regs; |
c0f3af97 L |
7055 | } |
7056 | else | |
7057 | source = dest = 0; | |
29b0f896 AM |
7058 | |
7059 | /* i.reg_operands MUST be the number of real register operands; | |
c0f3af97 L |
7060 | implicit registers do not count. If there are 3 register |
7061 | operands, it must be a instruction with VexNDS. For a | |
7062 | instruction with VexNDD, the destination register is encoded | |
7063 | in VEX prefix. If there are 4 register operands, it must be | |
7064 | a instruction with VEX prefix and 3 sources. */ | |
7ab9ffdd L |
7065 | if (i.mem_operands == 0 |
7066 | && ((i.reg_operands == 2 | |
2426c15f | 7067 | && i.tm.opcode_modifier.vexvvvv <= VEXXDS) |
7ab9ffdd | 7068 | || (i.reg_operands == 3 |
2426c15f | 7069 | && i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd | 7070 | || (i.reg_operands == 4 && vex_3_sources))) |
29b0f896 | 7071 | { |
cab737b9 L |
7072 | switch (i.operands) |
7073 | { | |
7074 | case 2: | |
7075 | source = 0; | |
7076 | break; | |
7077 | case 3: | |
c81128dc L |
7078 | /* When there are 3 operands, one of them may be immediate, |
7079 | which may be the first or the last operand. Otherwise, | |
c0f3af97 L |
7080 | the first operand must be shift count register (cl) or it |
7081 | is an instruction with VexNDS. */ | |
9c2799c2 | 7082 | gas_assert (i.imm_operands == 1 |
7ab9ffdd | 7083 | || (i.imm_operands == 0 |
2426c15f | 7084 | && (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd | 7085 | || i.types[0].bitfield.shiftcount))); |
40fb9820 L |
7086 | if (operand_type_check (i.types[0], imm) |
7087 | || i.types[0].bitfield.shiftcount) | |
7088 | source = 1; | |
7089 | else | |
7090 | source = 0; | |
cab737b9 L |
7091 | break; |
7092 | case 4: | |
368d64cc L |
7093 | /* When there are 4 operands, the first two must be 8bit |
7094 | immediate operands. The source operand will be the 3rd | |
c0f3af97 L |
7095 | one. |
7096 | ||
7097 | For instructions with VexNDS, if the first operand | |
7098 | an imm8, the source operand is the 2nd one. If the last | |
7099 | operand is imm8, the source operand is the first one. */ | |
9c2799c2 | 7100 | gas_assert ((i.imm_operands == 2 |
7ab9ffdd L |
7101 | && i.types[0].bitfield.imm8 |
7102 | && i.types[1].bitfield.imm8) | |
2426c15f | 7103 | || (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd L |
7104 | && i.imm_operands == 1 |
7105 | && (i.types[0].bitfield.imm8 | |
43234a1e L |
7106 | || i.types[i.operands - 1].bitfield.imm8 |
7107 | || i.rounding))); | |
9f2670f2 L |
7108 | if (i.imm_operands == 2) |
7109 | source = 2; | |
7110 | else | |
c0f3af97 L |
7111 | { |
7112 | if (i.types[0].bitfield.imm8) | |
7113 | source = 1; | |
7114 | else | |
7115 | source = 0; | |
7116 | } | |
c0f3af97 L |
7117 | break; |
7118 | case 5: | |
e771e7c9 | 7119 | if (is_evex_encoding (&i.tm)) |
43234a1e L |
7120 | { |
7121 | /* For EVEX instructions, when there are 5 operands, the | |
7122 | first one must be immediate operand. If the second one | |
7123 | is immediate operand, the source operand is the 3th | |
7124 | one. If the last one is immediate operand, the source | |
7125 | operand is the 2nd one. */ | |
7126 | gas_assert (i.imm_operands == 2 | |
7127 | && i.tm.opcode_modifier.sae | |
7128 | && operand_type_check (i.types[0], imm)); | |
7129 | if (operand_type_check (i.types[1], imm)) | |
7130 | source = 2; | |
7131 | else if (operand_type_check (i.types[4], imm)) | |
7132 | source = 1; | |
7133 | else | |
7134 | abort (); | |
7135 | } | |
cab737b9 L |
7136 | break; |
7137 | default: | |
7138 | abort (); | |
7139 | } | |
7140 | ||
c0f3af97 L |
7141 | if (!vex_3_sources) |
7142 | { | |
7143 | dest = source + 1; | |
7144 | ||
43234a1e L |
7145 | /* RC/SAE operand could be between DEST and SRC. That happens |
7146 | when one operand is GPR and the other one is XMM/YMM/ZMM | |
7147 | register. */ | |
7148 | if (i.rounding && i.rounding->operand == (int) dest) | |
7149 | dest++; | |
7150 | ||
2426c15f | 7151 | if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
c0f3af97 | 7152 | { |
43234a1e | 7153 | /* For instructions with VexNDS, the register-only source |
c5d0745b | 7154 | operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask |
43234a1e L |
7155 | register. It is encoded in VEX prefix. We need to |
7156 | clear RegMem bit before calling operand_type_equal. */ | |
f12dc422 L |
7157 | |
7158 | i386_operand_type op; | |
7159 | unsigned int vvvv; | |
7160 | ||
7161 | /* Check register-only source operand when two source | |
7162 | operands are swapped. */ | |
7163 | if (!i.tm.operand_types[source].bitfield.baseindex | |
7164 | && i.tm.operand_types[dest].bitfield.baseindex) | |
7165 | { | |
7166 | vvvv = source; | |
7167 | source = dest; | |
7168 | } | |
7169 | else | |
7170 | vvvv = dest; | |
7171 | ||
7172 | op = i.tm.operand_types[vvvv]; | |
fa99fab2 | 7173 | op.bitfield.regmem = 0; |
c0f3af97 | 7174 | if ((dest + 1) >= i.operands |
dc821c5f JB |
7175 | || ((!op.bitfield.reg |
7176 | || (!op.bitfield.dword && !op.bitfield.qword)) | |
10c17abd | 7177 | && !op.bitfield.regsimd |
43234a1e | 7178 | && !operand_type_equal (&op, ®mask))) |
c0f3af97 | 7179 | abort (); |
f12dc422 | 7180 | i.vex.register_specifier = i.op[vvvv].regs; |
c0f3af97 L |
7181 | dest++; |
7182 | } | |
7183 | } | |
29b0f896 AM |
7184 | |
7185 | i.rm.mode = 3; | |
7186 | /* One of the register operands will be encoded in the i.tm.reg | |
7187 | field, the other in the combined i.tm.mode and i.tm.regmem | |
7188 | fields. If no form of this instruction supports a memory | |
7189 | destination operand, then we assume the source operand may | |
7190 | sometimes be a memory operand and so we need to store the | |
7191 | destination in the i.rm.reg field. */ | |
40fb9820 L |
7192 | if (!i.tm.operand_types[dest].bitfield.regmem |
7193 | && operand_type_check (i.tm.operand_types[dest], anymem) == 0) | |
29b0f896 AM |
7194 | { |
7195 | i.rm.reg = i.op[dest].regs->reg_num; | |
7196 | i.rm.regmem = i.op[source].regs->reg_num; | |
b4a3a7b4 L |
7197 | if (i.op[dest].regs->reg_type.bitfield.regmmx |
7198 | || i.op[source].regs->reg_type.bitfield.regmmx) | |
7199 | i.has_regmmx = TRUE; | |
7200 | else if (i.op[dest].regs->reg_type.bitfield.regsimd | |
7201 | || i.op[source].regs->reg_type.bitfield.regsimd) | |
7202 | { | |
7203 | if (i.types[dest].bitfield.zmmword | |
7204 | || i.types[source].bitfield.zmmword) | |
7205 | i.has_regzmm = TRUE; | |
7206 | else if (i.types[dest].bitfield.ymmword | |
7207 | || i.types[source].bitfield.ymmword) | |
7208 | i.has_regymm = TRUE; | |
7209 | else | |
7210 | i.has_regxmm = TRUE; | |
7211 | } | |
29b0f896 | 7212 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) |
161a04f6 | 7213 | i.rex |= REX_R; |
43234a1e L |
7214 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
7215 | i.vrex |= REX_R; | |
29b0f896 | 7216 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 7217 | i.rex |= REX_B; |
43234a1e L |
7218 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
7219 | i.vrex |= REX_B; | |
29b0f896 AM |
7220 | } |
7221 | else | |
7222 | { | |
7223 | i.rm.reg = i.op[source].regs->reg_num; | |
7224 | i.rm.regmem = i.op[dest].regs->reg_num; | |
7225 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 7226 | i.rex |= REX_B; |
43234a1e L |
7227 | if ((i.op[dest].regs->reg_flags & RegVRex) != 0) |
7228 | i.vrex |= REX_B; | |
29b0f896 | 7229 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 7230 | i.rex |= REX_R; |
43234a1e L |
7231 | if ((i.op[source].regs->reg_flags & RegVRex) != 0) |
7232 | i.vrex |= REX_R; | |
29b0f896 | 7233 | } |
e0c7f900 | 7234 | if (flag_code != CODE_64BIT && (i.rex & REX_R)) |
c4a530c5 | 7235 | { |
e0c7f900 | 7236 | if (!i.types[i.tm.operand_types[0].bitfield.regmem].bitfield.control) |
c4a530c5 | 7237 | abort (); |
e0c7f900 | 7238 | i.rex &= ~REX_R; |
c4a530c5 JB |
7239 | add_prefix (LOCK_PREFIX_OPCODE); |
7240 | } | |
29b0f896 AM |
7241 | } |
7242 | else | |
7243 | { /* If it's not 2 reg operands... */ | |
c0f3af97 L |
7244 | unsigned int mem; |
7245 | ||
29b0f896 AM |
7246 | if (i.mem_operands) |
7247 | { | |
7248 | unsigned int fake_zero_displacement = 0; | |
99018f42 | 7249 | unsigned int op; |
4eed87de | 7250 | |
7ab9ffdd L |
7251 | for (op = 0; op < i.operands; op++) |
7252 | if (operand_type_check (i.types[op], anymem)) | |
7253 | break; | |
7ab9ffdd | 7254 | gas_assert (op < i.operands); |
29b0f896 | 7255 | |
6c30d220 L |
7256 | if (i.tm.opcode_modifier.vecsib) |
7257 | { | |
e968fc9b | 7258 | if (i.index_reg->reg_num == RegIZ) |
6c30d220 L |
7259 | abort (); |
7260 | ||
7261 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
7262 | if (!i.base_reg) | |
7263 | { | |
7264 | i.sib.base = NO_BASE_REGISTER; | |
7265 | i.sib.scale = i.log2_scale_factor; | |
7266 | i.types[op].bitfield.disp8 = 0; | |
7267 | i.types[op].bitfield.disp16 = 0; | |
7268 | i.types[op].bitfield.disp64 = 0; | |
43083a50 | 7269 | if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX]) |
6c30d220 L |
7270 | { |
7271 | /* Must be 32 bit */ | |
7272 | i.types[op].bitfield.disp32 = 1; | |
7273 | i.types[op].bitfield.disp32s = 0; | |
7274 | } | |
7275 | else | |
7276 | { | |
7277 | i.types[op].bitfield.disp32 = 0; | |
7278 | i.types[op].bitfield.disp32s = 1; | |
7279 | } | |
7280 | } | |
7281 | i.sib.index = i.index_reg->reg_num; | |
7282 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
7283 | i.rex |= REX_X; | |
43234a1e L |
7284 | if ((i.index_reg->reg_flags & RegVRex) != 0) |
7285 | i.vrex |= REX_X; | |
6c30d220 L |
7286 | } |
7287 | ||
29b0f896 AM |
7288 | default_seg = &ds; |
7289 | ||
7290 | if (i.base_reg == 0) | |
7291 | { | |
7292 | i.rm.mode = 0; | |
7293 | if (!i.disp_operands) | |
9bb129e8 | 7294 | fake_zero_displacement = 1; |
29b0f896 AM |
7295 | if (i.index_reg == 0) |
7296 | { | |
73053c1f JB |
7297 | i386_operand_type newdisp; |
7298 | ||
6c30d220 | 7299 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 7300 | /* Operand is just <disp> */ |
20f0a1fc | 7301 | if (flag_code == CODE_64BIT) |
29b0f896 AM |
7302 | { |
7303 | /* 64bit mode overwrites the 32bit absolute | |
7304 | addressing by RIP relative addressing and | |
7305 | absolute addressing is encoded by one of the | |
7306 | redundant SIB forms. */ | |
7307 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
7308 | i.sib.base = NO_BASE_REGISTER; | |
7309 | i.sib.index = NO_INDEX_REGISTER; | |
73053c1f | 7310 | newdisp = (!i.prefix[ADDR_PREFIX] ? disp32s : disp32); |
20f0a1fc | 7311 | } |
fc225355 L |
7312 | else if ((flag_code == CODE_16BIT) |
7313 | ^ (i.prefix[ADDR_PREFIX] != 0)) | |
20f0a1fc NC |
7314 | { |
7315 | i.rm.regmem = NO_BASE_REGISTER_16; | |
73053c1f | 7316 | newdisp = disp16; |
20f0a1fc NC |
7317 | } |
7318 | else | |
7319 | { | |
7320 | i.rm.regmem = NO_BASE_REGISTER; | |
73053c1f | 7321 | newdisp = disp32; |
29b0f896 | 7322 | } |
73053c1f JB |
7323 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
7324 | i.types[op] = operand_type_or (i.types[op], newdisp); | |
29b0f896 | 7325 | } |
6c30d220 | 7326 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 7327 | { |
6c30d220 | 7328 | /* !i.base_reg && i.index_reg */ |
e968fc9b | 7329 | if (i.index_reg->reg_num == RegIZ) |
db51cc60 L |
7330 | i.sib.index = NO_INDEX_REGISTER; |
7331 | else | |
7332 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
7333 | i.sib.base = NO_BASE_REGISTER; |
7334 | i.sib.scale = i.log2_scale_factor; | |
7335 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
40fb9820 L |
7336 | i.types[op].bitfield.disp8 = 0; |
7337 | i.types[op].bitfield.disp16 = 0; | |
7338 | i.types[op].bitfield.disp64 = 0; | |
43083a50 | 7339 | if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX]) |
40fb9820 L |
7340 | { |
7341 | /* Must be 32 bit */ | |
7342 | i.types[op].bitfield.disp32 = 1; | |
7343 | i.types[op].bitfield.disp32s = 0; | |
7344 | } | |
29b0f896 | 7345 | else |
40fb9820 L |
7346 | { |
7347 | i.types[op].bitfield.disp32 = 0; | |
7348 | i.types[op].bitfield.disp32s = 1; | |
7349 | } | |
29b0f896 | 7350 | if ((i.index_reg->reg_flags & RegRex) != 0) |
161a04f6 | 7351 | i.rex |= REX_X; |
29b0f896 AM |
7352 | } |
7353 | } | |
7354 | /* RIP addressing for 64bit mode. */ | |
e968fc9b | 7355 | else if (i.base_reg->reg_num == RegIP) |
29b0f896 | 7356 | { |
6c30d220 | 7357 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 | 7358 | i.rm.regmem = NO_BASE_REGISTER; |
40fb9820 L |
7359 | i.types[op].bitfield.disp8 = 0; |
7360 | i.types[op].bitfield.disp16 = 0; | |
7361 | i.types[op].bitfield.disp32 = 0; | |
7362 | i.types[op].bitfield.disp32s = 1; | |
7363 | i.types[op].bitfield.disp64 = 0; | |
71903a11 | 7364 | i.flags[op] |= Operand_PCrel; |
20f0a1fc NC |
7365 | if (! i.disp_operands) |
7366 | fake_zero_displacement = 1; | |
29b0f896 | 7367 | } |
dc821c5f | 7368 | else if (i.base_reg->reg_type.bitfield.word) |
29b0f896 | 7369 | { |
6c30d220 | 7370 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
7371 | switch (i.base_reg->reg_num) |
7372 | { | |
7373 | case 3: /* (%bx) */ | |
7374 | if (i.index_reg == 0) | |
7375 | i.rm.regmem = 7; | |
7376 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
7377 | i.rm.regmem = i.index_reg->reg_num - 6; | |
7378 | break; | |
7379 | case 5: /* (%bp) */ | |
7380 | default_seg = &ss; | |
7381 | if (i.index_reg == 0) | |
7382 | { | |
7383 | i.rm.regmem = 6; | |
40fb9820 | 7384 | if (operand_type_check (i.types[op], disp) == 0) |
29b0f896 AM |
7385 | { |
7386 | /* fake (%bp) into 0(%bp) */ | |
b5014f7a | 7387 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 7388 | fake_zero_displacement = 1; |
29b0f896 AM |
7389 | } |
7390 | } | |
7391 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
7392 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
7393 | break; | |
7394 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
7395 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
7396 | } | |
7397 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
7398 | } | |
7399 | else /* i.base_reg and 32/64 bit mode */ | |
7400 | { | |
7401 | if (flag_code == CODE_64BIT | |
40fb9820 L |
7402 | && operand_type_check (i.types[op], disp)) |
7403 | { | |
73053c1f JB |
7404 | i.types[op].bitfield.disp16 = 0; |
7405 | i.types[op].bitfield.disp64 = 0; | |
40fb9820 | 7406 | if (i.prefix[ADDR_PREFIX] == 0) |
73053c1f JB |
7407 | { |
7408 | i.types[op].bitfield.disp32 = 0; | |
7409 | i.types[op].bitfield.disp32s = 1; | |
7410 | } | |
40fb9820 | 7411 | else |
73053c1f JB |
7412 | { |
7413 | i.types[op].bitfield.disp32 = 1; | |
7414 | i.types[op].bitfield.disp32s = 0; | |
7415 | } | |
40fb9820 | 7416 | } |
20f0a1fc | 7417 | |
6c30d220 L |
7418 | if (!i.tm.opcode_modifier.vecsib) |
7419 | i.rm.regmem = i.base_reg->reg_num; | |
29b0f896 | 7420 | if ((i.base_reg->reg_flags & RegRex) != 0) |
161a04f6 | 7421 | i.rex |= REX_B; |
29b0f896 AM |
7422 | i.sib.base = i.base_reg->reg_num; |
7423 | /* x86-64 ignores REX prefix bit here to avoid decoder | |
7424 | complications. */ | |
848930b2 JB |
7425 | if (!(i.base_reg->reg_flags & RegRex) |
7426 | && (i.base_reg->reg_num == EBP_REG_NUM | |
7427 | || i.base_reg->reg_num == ESP_REG_NUM)) | |
29b0f896 | 7428 | default_seg = &ss; |
848930b2 | 7429 | if (i.base_reg->reg_num == 5 && i.disp_operands == 0) |
29b0f896 | 7430 | { |
848930b2 | 7431 | fake_zero_displacement = 1; |
b5014f7a | 7432 | i.types[op].bitfield.disp8 = 1; |
29b0f896 AM |
7433 | } |
7434 | i.sib.scale = i.log2_scale_factor; | |
7435 | if (i.index_reg == 0) | |
7436 | { | |
6c30d220 | 7437 | gas_assert (!i.tm.opcode_modifier.vecsib); |
29b0f896 AM |
7438 | /* <disp>(%esp) becomes two byte modrm with no index |
7439 | register. We've already stored the code for esp | |
7440 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. | |
7441 | Any base register besides %esp will not use the | |
7442 | extra modrm byte. */ | |
7443 | i.sib.index = NO_INDEX_REGISTER; | |
29b0f896 | 7444 | } |
6c30d220 | 7445 | else if (!i.tm.opcode_modifier.vecsib) |
29b0f896 | 7446 | { |
e968fc9b | 7447 | if (i.index_reg->reg_num == RegIZ) |
db51cc60 L |
7448 | i.sib.index = NO_INDEX_REGISTER; |
7449 | else | |
7450 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
7451 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
7452 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
161a04f6 | 7453 | i.rex |= REX_X; |
29b0f896 | 7454 | } |
67a4f2b7 AO |
7455 | |
7456 | if (i.disp_operands | |
7457 | && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL | |
7458 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) | |
7459 | i.rm.mode = 0; | |
7460 | else | |
a501d77e L |
7461 | { |
7462 | if (!fake_zero_displacement | |
7463 | && !i.disp_operands | |
7464 | && i.disp_encoding) | |
7465 | { | |
7466 | fake_zero_displacement = 1; | |
7467 | if (i.disp_encoding == disp_encoding_8bit) | |
7468 | i.types[op].bitfield.disp8 = 1; | |
7469 | else | |
7470 | i.types[op].bitfield.disp32 = 1; | |
7471 | } | |
7472 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
7473 | } | |
29b0f896 | 7474 | } |
252b5132 | 7475 | |
29b0f896 AM |
7476 | if (fake_zero_displacement) |
7477 | { | |
7478 | /* Fakes a zero displacement assuming that i.types[op] | |
7479 | holds the correct displacement size. */ | |
7480 | expressionS *exp; | |
7481 | ||
9c2799c2 | 7482 | gas_assert (i.op[op].disps == 0); |
29b0f896 AM |
7483 | exp = &disp_expressions[i.disp_operands++]; |
7484 | i.op[op].disps = exp; | |
7485 | exp->X_op = O_constant; | |
7486 | exp->X_add_number = 0; | |
7487 | exp->X_add_symbol = (symbolS *) 0; | |
7488 | exp->X_op_symbol = (symbolS *) 0; | |
7489 | } | |
c0f3af97 L |
7490 | |
7491 | mem = op; | |
29b0f896 | 7492 | } |
c0f3af97 L |
7493 | else |
7494 | mem = ~0; | |
252b5132 | 7495 | |
8c43a48b | 7496 | if (i.tm.opcode_modifier.vexsources == XOP2SOURCES) |
5dd85c99 SP |
7497 | { |
7498 | if (operand_type_check (i.types[0], imm)) | |
7499 | i.vex.register_specifier = NULL; | |
7500 | else | |
7501 | { | |
7502 | /* VEX.vvvv encodes one of the sources when the first | |
7503 | operand is not an immediate. */ | |
1ef99a7b | 7504 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
7505 | i.vex.register_specifier = i.op[0].regs; |
7506 | else | |
7507 | i.vex.register_specifier = i.op[1].regs; | |
7508 | } | |
7509 | ||
7510 | /* Destination is a XMM register encoded in the ModRM.reg | |
7511 | and VEX.R bit. */ | |
7512 | i.rm.reg = i.op[2].regs->reg_num; | |
7513 | if ((i.op[2].regs->reg_flags & RegRex) != 0) | |
7514 | i.rex |= REX_R; | |
7515 | ||
7516 | /* ModRM.rm and VEX.B encodes the other source. */ | |
7517 | if (!i.mem_operands) | |
7518 | { | |
7519 | i.rm.mode = 3; | |
7520 | ||
1ef99a7b | 7521 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
7522 | i.rm.regmem = i.op[1].regs->reg_num; |
7523 | else | |
7524 | i.rm.regmem = i.op[0].regs->reg_num; | |
7525 | ||
7526 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
7527 | i.rex |= REX_B; | |
7528 | } | |
7529 | } | |
2426c15f | 7530 | else if (i.tm.opcode_modifier.vexvvvv == VEXLWP) |
f88c9eb0 SP |
7531 | { |
7532 | i.vex.register_specifier = i.op[2].regs; | |
7533 | if (!i.mem_operands) | |
7534 | { | |
7535 | i.rm.mode = 3; | |
7536 | i.rm.regmem = i.op[1].regs->reg_num; | |
7537 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
7538 | i.rex |= REX_B; | |
7539 | } | |
7540 | } | |
29b0f896 AM |
7541 | /* Fill in i.rm.reg or i.rm.regmem field with register operand |
7542 | (if any) based on i.tm.extension_opcode. Again, we must be | |
7543 | careful to make sure that segment/control/debug/test/MMX | |
7544 | registers are coded into the i.rm.reg field. */ | |
f88c9eb0 | 7545 | else if (i.reg_operands) |
29b0f896 | 7546 | { |
99018f42 | 7547 | unsigned int op; |
7ab9ffdd L |
7548 | unsigned int vex_reg = ~0; |
7549 | ||
7550 | for (op = 0; op < i.operands; op++) | |
b4a3a7b4 L |
7551 | { |
7552 | if (i.types[op].bitfield.reg | |
7553 | || i.types[op].bitfield.regbnd | |
7554 | || i.types[op].bitfield.regmask | |
7555 | || i.types[op].bitfield.sreg2 | |
7556 | || i.types[op].bitfield.sreg3 | |
7557 | || i.types[op].bitfield.control | |
7558 | || i.types[op].bitfield.debug | |
7559 | || i.types[op].bitfield.test) | |
7560 | break; | |
7561 | if (i.types[op].bitfield.regsimd) | |
7562 | { | |
7563 | if (i.types[op].bitfield.zmmword) | |
7564 | i.has_regzmm = TRUE; | |
7565 | else if (i.types[op].bitfield.ymmword) | |
7566 | i.has_regymm = TRUE; | |
7567 | else | |
7568 | i.has_regxmm = TRUE; | |
7569 | break; | |
7570 | } | |
7571 | if (i.types[op].bitfield.regmmx) | |
7572 | { | |
7573 | i.has_regmmx = TRUE; | |
7574 | break; | |
7575 | } | |
7576 | } | |
c0209578 | 7577 | |
7ab9ffdd L |
7578 | if (vex_3_sources) |
7579 | op = dest; | |
2426c15f | 7580 | else if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd L |
7581 | { |
7582 | /* For instructions with VexNDS, the register-only | |
7583 | source operand is encoded in VEX prefix. */ | |
7584 | gas_assert (mem != (unsigned int) ~0); | |
c0f3af97 | 7585 | |
7ab9ffdd | 7586 | if (op > mem) |
c0f3af97 | 7587 | { |
7ab9ffdd L |
7588 | vex_reg = op++; |
7589 | gas_assert (op < i.operands); | |
c0f3af97 L |
7590 | } |
7591 | else | |
c0f3af97 | 7592 | { |
f12dc422 L |
7593 | /* Check register-only source operand when two source |
7594 | operands are swapped. */ | |
7595 | if (!i.tm.operand_types[op].bitfield.baseindex | |
7596 | && i.tm.operand_types[op + 1].bitfield.baseindex) | |
7597 | { | |
7598 | vex_reg = op; | |
7599 | op += 2; | |
7600 | gas_assert (mem == (vex_reg + 1) | |
7601 | && op < i.operands); | |
7602 | } | |
7603 | else | |
7604 | { | |
7605 | vex_reg = op + 1; | |
7606 | gas_assert (vex_reg < i.operands); | |
7607 | } | |
c0f3af97 | 7608 | } |
7ab9ffdd | 7609 | } |
2426c15f | 7610 | else if (i.tm.opcode_modifier.vexvvvv == VEXNDD) |
7ab9ffdd | 7611 | { |
f12dc422 | 7612 | /* For instructions with VexNDD, the register destination |
7ab9ffdd | 7613 | is encoded in VEX prefix. */ |
f12dc422 L |
7614 | if (i.mem_operands == 0) |
7615 | { | |
7616 | /* There is no memory operand. */ | |
7617 | gas_assert ((op + 2) == i.operands); | |
7618 | vex_reg = op + 1; | |
7619 | } | |
7620 | else | |
8d63c93e | 7621 | { |
ed438a93 JB |
7622 | /* There are only 2 non-immediate operands. */ |
7623 | gas_assert (op < i.imm_operands + 2 | |
7624 | && i.operands == i.imm_operands + 2); | |
7625 | vex_reg = i.imm_operands + 1; | |
f12dc422 | 7626 | } |
7ab9ffdd L |
7627 | } |
7628 | else | |
7629 | gas_assert (op < i.operands); | |
99018f42 | 7630 | |
7ab9ffdd L |
7631 | if (vex_reg != (unsigned int) ~0) |
7632 | { | |
f12dc422 | 7633 | i386_operand_type *type = &i.tm.operand_types[vex_reg]; |
7ab9ffdd | 7634 | |
dc821c5f JB |
7635 | if ((!type->bitfield.reg |
7636 | || (!type->bitfield.dword && !type->bitfield.qword)) | |
10c17abd | 7637 | && !type->bitfield.regsimd |
43234a1e | 7638 | && !operand_type_equal (type, ®mask)) |
7ab9ffdd | 7639 | abort (); |
f88c9eb0 | 7640 | |
7ab9ffdd L |
7641 | i.vex.register_specifier = i.op[vex_reg].regs; |
7642 | } | |
7643 | ||
1b9f0c97 L |
7644 | /* Don't set OP operand twice. */ |
7645 | if (vex_reg != op) | |
7ab9ffdd | 7646 | { |
1b9f0c97 L |
7647 | /* If there is an extension opcode to put here, the |
7648 | register number must be put into the regmem field. */ | |
7649 | if (i.tm.extension_opcode != None) | |
7650 | { | |
7651 | i.rm.regmem = i.op[op].regs->reg_num; | |
7652 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
7653 | i.rex |= REX_B; | |
43234a1e L |
7654 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
7655 | i.vrex |= REX_B; | |
1b9f0c97 L |
7656 | } |
7657 | else | |
7658 | { | |
7659 | i.rm.reg = i.op[op].regs->reg_num; | |
7660 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
7661 | i.rex |= REX_R; | |
43234a1e L |
7662 | if ((i.op[op].regs->reg_flags & RegVRex) != 0) |
7663 | i.vrex |= REX_R; | |
1b9f0c97 | 7664 | } |
7ab9ffdd | 7665 | } |
252b5132 | 7666 | |
29b0f896 AM |
7667 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we |
7668 | must set it to 3 to indicate this is a register operand | |
7669 | in the regmem field. */ | |
7670 | if (!i.mem_operands) | |
7671 | i.rm.mode = 3; | |
7672 | } | |
252b5132 | 7673 | |
29b0f896 | 7674 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
c1e679ec | 7675 | if (i.tm.extension_opcode != None) |
29b0f896 AM |
7676 | i.rm.reg = i.tm.extension_opcode; |
7677 | } | |
7678 | return default_seg; | |
7679 | } | |
252b5132 | 7680 | |
29b0f896 | 7681 | static void |
e3bb37b5 | 7682 | output_branch (void) |
29b0f896 AM |
7683 | { |
7684 | char *p; | |
f8a5c266 | 7685 | int size; |
29b0f896 AM |
7686 | int code16; |
7687 | int prefix; | |
7688 | relax_substateT subtype; | |
7689 | symbolS *sym; | |
7690 | offsetT off; | |
7691 | ||
f8a5c266 | 7692 | code16 = flag_code == CODE_16BIT ? CODE16 : 0; |
a501d77e | 7693 | size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL; |
29b0f896 AM |
7694 | |
7695 | prefix = 0; | |
7696 | if (i.prefix[DATA_PREFIX] != 0) | |
252b5132 | 7697 | { |
29b0f896 AM |
7698 | prefix = 1; |
7699 | i.prefixes -= 1; | |
7700 | code16 ^= CODE16; | |
252b5132 | 7701 | } |
29b0f896 AM |
7702 | /* Pentium4 branch hints. */ |
7703 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
7704 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2f66722d | 7705 | { |
29b0f896 AM |
7706 | prefix++; |
7707 | i.prefixes--; | |
7708 | } | |
7709 | if (i.prefix[REX_PREFIX] != 0) | |
7710 | { | |
7711 | prefix++; | |
7712 | i.prefixes--; | |
2f66722d AM |
7713 | } |
7714 | ||
7e8b059b L |
7715 | /* BND prefixed jump. */ |
7716 | if (i.prefix[BND_PREFIX] != 0) | |
7717 | { | |
7718 | FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]); | |
7719 | i.prefixes -= 1; | |
7720 | } | |
7721 | ||
29b0f896 AM |
7722 | if (i.prefixes != 0 && !intel_syntax) |
7723 | as_warn (_("skipping prefixes on this instruction")); | |
7724 | ||
7725 | /* It's always a symbol; End frag & setup for relax. | |
7726 | Make sure there is enough room in this frag for the largest | |
7727 | instruction we may generate in md_convert_frag. This is 2 | |
7728 | bytes for the opcode and room for the prefix and largest | |
7729 | displacement. */ | |
7730 | frag_grow (prefix + 2 + 4); | |
7731 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
7732 | p = frag_more (prefix + 1); | |
7733 | if (i.prefix[DATA_PREFIX] != 0) | |
7734 | *p++ = DATA_PREFIX_OPCODE; | |
7735 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE | |
7736 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
7737 | *p++ = i.prefix[SEG_PREFIX]; | |
7738 | if (i.prefix[REX_PREFIX] != 0) | |
7739 | *p++ = i.prefix[REX_PREFIX]; | |
7740 | *p = i.tm.base_opcode; | |
7741 | ||
7742 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
f8a5c266 | 7743 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size); |
40fb9820 | 7744 | else if (cpu_arch_flags.bitfield.cpui386) |
f8a5c266 | 7745 | subtype = ENCODE_RELAX_STATE (COND_JUMP, size); |
29b0f896 | 7746 | else |
f8a5c266 | 7747 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, size); |
29b0f896 | 7748 | subtype |= code16; |
3e73aa7c | 7749 | |
29b0f896 AM |
7750 | sym = i.op[0].disps->X_add_symbol; |
7751 | off = i.op[0].disps->X_add_number; | |
3e73aa7c | 7752 | |
29b0f896 AM |
7753 | if (i.op[0].disps->X_op != O_constant |
7754 | && i.op[0].disps->X_op != O_symbol) | |
3e73aa7c | 7755 | { |
29b0f896 AM |
7756 | /* Handle complex expressions. */ |
7757 | sym = make_expr_symbol (i.op[0].disps); | |
7758 | off = 0; | |
7759 | } | |
3e73aa7c | 7760 | |
29b0f896 AM |
7761 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
7762 | Pass reloc in fr_var. */ | |
d258b828 | 7763 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); |
29b0f896 | 7764 | } |
3e73aa7c | 7765 | |
bd7ab16b L |
7766 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
7767 | /* Return TRUE iff PLT32 relocation should be used for branching to | |
7768 | symbol S. */ | |
7769 | ||
7770 | static bfd_boolean | |
7771 | need_plt32_p (symbolS *s) | |
7772 | { | |
7773 | /* PLT32 relocation is ELF only. */ | |
7774 | if (!IS_ELF) | |
7775 | return FALSE; | |
7776 | ||
7777 | /* Since there is no need to prepare for PLT branch on x86-64, we | |
7778 | can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can | |
7779 | be used as a marker for 32-bit PC-relative branches. */ | |
7780 | if (!object_64bit) | |
7781 | return FALSE; | |
7782 | ||
7783 | /* Weak or undefined symbol need PLT32 relocation. */ | |
7784 | if (S_IS_WEAK (s) || !S_IS_DEFINED (s)) | |
7785 | return TRUE; | |
7786 | ||
7787 | /* Non-global symbol doesn't need PLT32 relocation. */ | |
7788 | if (! S_IS_EXTERNAL (s)) | |
7789 | return FALSE; | |
7790 | ||
7791 | /* Other global symbols need PLT32 relocation. NB: Symbol with | |
7792 | non-default visibilities are treated as normal global symbol | |
7793 | so that PLT32 relocation can be used as a marker for 32-bit | |
7794 | PC-relative branches. It is useful for linker relaxation. */ | |
7795 | return TRUE; | |
7796 | } | |
7797 | #endif | |
7798 | ||
29b0f896 | 7799 | static void |
e3bb37b5 | 7800 | output_jump (void) |
29b0f896 AM |
7801 | { |
7802 | char *p; | |
7803 | int size; | |
3e02c1cc | 7804 | fixS *fixP; |
bd7ab16b | 7805 | bfd_reloc_code_real_type jump_reloc = i.reloc[0]; |
29b0f896 | 7806 | |
40fb9820 | 7807 | if (i.tm.opcode_modifier.jumpbyte) |
29b0f896 AM |
7808 | { |
7809 | /* This is a loop or jecxz type instruction. */ | |
7810 | size = 1; | |
7811 | if (i.prefix[ADDR_PREFIX] != 0) | |
7812 | { | |
7813 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); | |
7814 | i.prefixes -= 1; | |
7815 | } | |
7816 | /* Pentium4 branch hints. */ | |
7817 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
7818 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
7819 | { | |
7820 | FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); | |
7821 | i.prefixes--; | |
3e73aa7c JH |
7822 | } |
7823 | } | |
29b0f896 AM |
7824 | else |
7825 | { | |
7826 | int code16; | |
3e73aa7c | 7827 | |
29b0f896 AM |
7828 | code16 = 0; |
7829 | if (flag_code == CODE_16BIT) | |
7830 | code16 = CODE16; | |
3e73aa7c | 7831 | |
29b0f896 AM |
7832 | if (i.prefix[DATA_PREFIX] != 0) |
7833 | { | |
7834 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); | |
7835 | i.prefixes -= 1; | |
7836 | code16 ^= CODE16; | |
7837 | } | |
252b5132 | 7838 | |
29b0f896 AM |
7839 | size = 4; |
7840 | if (code16) | |
7841 | size = 2; | |
7842 | } | |
9fcc94b6 | 7843 | |
29b0f896 AM |
7844 | if (i.prefix[REX_PREFIX] != 0) |
7845 | { | |
7846 | FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); | |
7847 | i.prefixes -= 1; | |
7848 | } | |
252b5132 | 7849 | |
7e8b059b L |
7850 | /* BND prefixed jump. */ |
7851 | if (i.prefix[BND_PREFIX] != 0) | |
7852 | { | |
7853 | FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]); | |
7854 | i.prefixes -= 1; | |
7855 | } | |
7856 | ||
29b0f896 AM |
7857 | if (i.prefixes != 0 && !intel_syntax) |
7858 | as_warn (_("skipping prefixes on this instruction")); | |
e0890092 | 7859 | |
42164a71 L |
7860 | p = frag_more (i.tm.opcode_length + size); |
7861 | switch (i.tm.opcode_length) | |
7862 | { | |
7863 | case 2: | |
7864 | *p++ = i.tm.base_opcode >> 8; | |
1a0670f3 | 7865 | /* Fall through. */ |
42164a71 L |
7866 | case 1: |
7867 | *p++ = i.tm.base_opcode; | |
7868 | break; | |
7869 | default: | |
7870 | abort (); | |
7871 | } | |
e0890092 | 7872 | |
bd7ab16b L |
7873 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
7874 | if (size == 4 | |
7875 | && jump_reloc == NO_RELOC | |
7876 | && need_plt32_p (i.op[0].disps->X_add_symbol)) | |
7877 | jump_reloc = BFD_RELOC_X86_64_PLT32; | |
7878 | #endif | |
7879 | ||
7880 | jump_reloc = reloc (size, 1, 1, jump_reloc); | |
7881 | ||
3e02c1cc | 7882 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
bd7ab16b | 7883 | i.op[0].disps, 1, jump_reloc); |
3e02c1cc AM |
7884 | |
7885 | /* All jumps handled here are signed, but don't use a signed limit | |
7886 | check for 32 and 16 bit jumps as we want to allow wrap around at | |
7887 | 4G and 64k respectively. */ | |
7888 | if (size == 1) | |
7889 | fixP->fx_signed = 1; | |
29b0f896 | 7890 | } |
e0890092 | 7891 | |
29b0f896 | 7892 | static void |
e3bb37b5 | 7893 | output_interseg_jump (void) |
29b0f896 AM |
7894 | { |
7895 | char *p; | |
7896 | int size; | |
7897 | int prefix; | |
7898 | int code16; | |
252b5132 | 7899 | |
29b0f896 AM |
7900 | code16 = 0; |
7901 | if (flag_code == CODE_16BIT) | |
7902 | code16 = CODE16; | |
a217f122 | 7903 | |
29b0f896 AM |
7904 | prefix = 0; |
7905 | if (i.prefix[DATA_PREFIX] != 0) | |
7906 | { | |
7907 | prefix = 1; | |
7908 | i.prefixes -= 1; | |
7909 | code16 ^= CODE16; | |
7910 | } | |
7911 | if (i.prefix[REX_PREFIX] != 0) | |
7912 | { | |
7913 | prefix++; | |
7914 | i.prefixes -= 1; | |
7915 | } | |
252b5132 | 7916 | |
29b0f896 AM |
7917 | size = 4; |
7918 | if (code16) | |
7919 | size = 2; | |
252b5132 | 7920 | |
29b0f896 AM |
7921 | if (i.prefixes != 0 && !intel_syntax) |
7922 | as_warn (_("skipping prefixes on this instruction")); | |
252b5132 | 7923 | |
29b0f896 AM |
7924 | /* 1 opcode; 2 segment; offset */ |
7925 | p = frag_more (prefix + 1 + 2 + size); | |
3e73aa7c | 7926 | |
29b0f896 AM |
7927 | if (i.prefix[DATA_PREFIX] != 0) |
7928 | *p++ = DATA_PREFIX_OPCODE; | |
252b5132 | 7929 | |
29b0f896 AM |
7930 | if (i.prefix[REX_PREFIX] != 0) |
7931 | *p++ = i.prefix[REX_PREFIX]; | |
252b5132 | 7932 | |
29b0f896 AM |
7933 | *p++ = i.tm.base_opcode; |
7934 | if (i.op[1].imms->X_op == O_constant) | |
7935 | { | |
7936 | offsetT n = i.op[1].imms->X_add_number; | |
252b5132 | 7937 | |
29b0f896 AM |
7938 | if (size == 2 |
7939 | && !fits_in_unsigned_word (n) | |
7940 | && !fits_in_signed_word (n)) | |
7941 | { | |
7942 | as_bad (_("16-bit jump out of range")); | |
7943 | return; | |
7944 | } | |
7945 | md_number_to_chars (p, n, size); | |
7946 | } | |
7947 | else | |
7948 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
d258b828 | 7949 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); |
29b0f896 AM |
7950 | if (i.op[0].imms->X_op != O_constant) |
7951 | as_bad (_("can't handle non absolute segment in `%s'"), | |
7952 | i.tm.name); | |
7953 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); | |
7954 | } | |
a217f122 | 7955 | |
b4a3a7b4 L |
7956 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
7957 | void | |
7958 | x86_cleanup (void) | |
7959 | { | |
7960 | char *p; | |
7961 | asection *seg = now_seg; | |
7962 | subsegT subseg = now_subseg; | |
7963 | asection *sec; | |
7964 | unsigned int alignment, align_size_1; | |
7965 | unsigned int isa_1_descsz, feature_2_descsz, descsz; | |
7966 | unsigned int isa_1_descsz_raw, feature_2_descsz_raw; | |
7967 | unsigned int padding; | |
7968 | ||
7969 | if (!IS_ELF || !x86_used_note) | |
7970 | return; | |
7971 | ||
b4a3a7b4 L |
7972 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X86; |
7973 | ||
7974 | /* The .note.gnu.property section layout: | |
7975 | ||
7976 | Field Length Contents | |
7977 | ---- ---- ---- | |
7978 | n_namsz 4 4 | |
7979 | n_descsz 4 The note descriptor size | |
7980 | n_type 4 NT_GNU_PROPERTY_TYPE_0 | |
7981 | n_name 4 "GNU" | |
7982 | n_desc n_descsz The program property array | |
7983 | .... .... .... | |
7984 | */ | |
7985 | ||
7986 | /* Create the .note.gnu.property section. */ | |
7987 | sec = subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME, 0); | |
7988 | bfd_set_section_flags (stdoutput, sec, | |
7989 | (SEC_ALLOC | |
7990 | | SEC_LOAD | |
7991 | | SEC_DATA | |
7992 | | SEC_HAS_CONTENTS | |
7993 | | SEC_READONLY)); | |
7994 | ||
7995 | if (get_elf_backend_data (stdoutput)->s->elfclass == ELFCLASS64) | |
7996 | { | |
7997 | align_size_1 = 7; | |
7998 | alignment = 3; | |
7999 | } | |
8000 | else | |
8001 | { | |
8002 | align_size_1 = 3; | |
8003 | alignment = 2; | |
8004 | } | |
8005 | ||
8006 | bfd_set_section_alignment (stdoutput, sec, alignment); | |
8007 | elf_section_type (sec) = SHT_NOTE; | |
8008 | ||
8009 | /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size | |
8010 | + 4-byte data */ | |
8011 | isa_1_descsz_raw = 4 + 4 + 4; | |
8012 | /* Align GNU_PROPERTY_X86_ISA_1_USED. */ | |
8013 | isa_1_descsz = (isa_1_descsz_raw + align_size_1) & ~align_size_1; | |
8014 | ||
8015 | feature_2_descsz_raw = isa_1_descsz; | |
8016 | /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size | |
8017 | + 4-byte data */ | |
8018 | feature_2_descsz_raw += 4 + 4 + 4; | |
8019 | /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */ | |
8020 | feature_2_descsz = ((feature_2_descsz_raw + align_size_1) | |
8021 | & ~align_size_1); | |
8022 | ||
8023 | descsz = feature_2_descsz; | |
8024 | /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */ | |
8025 | p = frag_more (4 + 4 + 4 + 4 + descsz); | |
8026 | ||
8027 | /* Write n_namsz. */ | |
8028 | md_number_to_chars (p, (valueT) 4, 4); | |
8029 | ||
8030 | /* Write n_descsz. */ | |
8031 | md_number_to_chars (p + 4, (valueT) descsz, 4); | |
8032 | ||
8033 | /* Write n_type. */ | |
8034 | md_number_to_chars (p + 4 * 2, (valueT) NT_GNU_PROPERTY_TYPE_0, 4); | |
8035 | ||
8036 | /* Write n_name. */ | |
8037 | memcpy (p + 4 * 3, "GNU", 4); | |
8038 | ||
8039 | /* Write 4-byte type. */ | |
8040 | md_number_to_chars (p + 4 * 4, | |
8041 | (valueT) GNU_PROPERTY_X86_ISA_1_USED, 4); | |
8042 | ||
8043 | /* Write 4-byte data size. */ | |
8044 | md_number_to_chars (p + 4 * 5, (valueT) 4, 4); | |
8045 | ||
8046 | /* Write 4-byte data. */ | |
8047 | md_number_to_chars (p + 4 * 6, (valueT) x86_isa_1_used, 4); | |
8048 | ||
8049 | /* Zero out paddings. */ | |
8050 | padding = isa_1_descsz - isa_1_descsz_raw; | |
8051 | if (padding) | |
8052 | memset (p + 4 * 7, 0, padding); | |
8053 | ||
8054 | /* Write 4-byte type. */ | |
8055 | md_number_to_chars (p + isa_1_descsz + 4 * 4, | |
8056 | (valueT) GNU_PROPERTY_X86_FEATURE_2_USED, 4); | |
8057 | ||
8058 | /* Write 4-byte data size. */ | |
8059 | md_number_to_chars (p + isa_1_descsz + 4 * 5, (valueT) 4, 4); | |
8060 | ||
8061 | /* Write 4-byte data. */ | |
8062 | md_number_to_chars (p + isa_1_descsz + 4 * 6, | |
8063 | (valueT) x86_feature_2_used, 4); | |
8064 | ||
8065 | /* Zero out paddings. */ | |
8066 | padding = feature_2_descsz - feature_2_descsz_raw; | |
8067 | if (padding) | |
8068 | memset (p + isa_1_descsz + 4 * 7, 0, padding); | |
8069 | ||
8070 | /* We probably can't restore the current segment, for there likely | |
8071 | isn't one yet... */ | |
8072 | if (seg && subseg) | |
8073 | subseg_set (seg, subseg); | |
8074 | } | |
8075 | #endif | |
8076 | ||
29b0f896 | 8077 | static void |
e3bb37b5 | 8078 | output_insn (void) |
29b0f896 | 8079 | { |
2bbd9c25 JJ |
8080 | fragS *insn_start_frag; |
8081 | offsetT insn_start_off; | |
8082 | ||
b4a3a7b4 L |
8083 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8084 | if (IS_ELF && x86_used_note) | |
8085 | { | |
8086 | if (i.tm.cpu_flags.bitfield.cpucmov) | |
8087 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_CMOV; | |
8088 | if (i.tm.cpu_flags.bitfield.cpusse) | |
8089 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE; | |
8090 | if (i.tm.cpu_flags.bitfield.cpusse2) | |
8091 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE2; | |
8092 | if (i.tm.cpu_flags.bitfield.cpusse3) | |
8093 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE3; | |
8094 | if (i.tm.cpu_flags.bitfield.cpussse3) | |
8095 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSSE3; | |
8096 | if (i.tm.cpu_flags.bitfield.cpusse4_1) | |
8097 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_1; | |
8098 | if (i.tm.cpu_flags.bitfield.cpusse4_2) | |
8099 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_SSE4_2; | |
8100 | if (i.tm.cpu_flags.bitfield.cpuavx) | |
8101 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX; | |
8102 | if (i.tm.cpu_flags.bitfield.cpuavx2) | |
8103 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX2; | |
8104 | if (i.tm.cpu_flags.bitfield.cpufma) | |
8105 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_FMA; | |
8106 | if (i.tm.cpu_flags.bitfield.cpuavx512f) | |
8107 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512F; | |
8108 | if (i.tm.cpu_flags.bitfield.cpuavx512cd) | |
8109 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512CD; | |
8110 | if (i.tm.cpu_flags.bitfield.cpuavx512er) | |
8111 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512ER; | |
8112 | if (i.tm.cpu_flags.bitfield.cpuavx512pf) | |
8113 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512PF; | |
8114 | if (i.tm.cpu_flags.bitfield.cpuavx512vl) | |
8115 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512VL; | |
8116 | if (i.tm.cpu_flags.bitfield.cpuavx512dq) | |
8117 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512DQ; | |
8118 | if (i.tm.cpu_flags.bitfield.cpuavx512bw) | |
8119 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512BW; | |
8120 | if (i.tm.cpu_flags.bitfield.cpuavx512_4fmaps) | |
8121 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4FMAPS; | |
8122 | if (i.tm.cpu_flags.bitfield.cpuavx512_4vnniw) | |
8123 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_4VNNIW; | |
8124 | if (i.tm.cpu_flags.bitfield.cpuavx512_bitalg) | |
8125 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_BITALG; | |
8126 | if (i.tm.cpu_flags.bitfield.cpuavx512ifma) | |
8127 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_IFMA; | |
8128 | if (i.tm.cpu_flags.bitfield.cpuavx512vbmi) | |
8129 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI; | |
8130 | if (i.tm.cpu_flags.bitfield.cpuavx512_vbmi2) | |
8131 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VBMI2; | |
8132 | if (i.tm.cpu_flags.bitfield.cpuavx512_vnni) | |
8133 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_AVX512_VNNI; | |
8134 | ||
8135 | if (i.tm.cpu_flags.bitfield.cpu8087 | |
8136 | || i.tm.cpu_flags.bitfield.cpu287 | |
8137 | || i.tm.cpu_flags.bitfield.cpu387 | |
8138 | || i.tm.cpu_flags.bitfield.cpu687 | |
8139 | || i.tm.cpu_flags.bitfield.cpufisttp) | |
8140 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X87; | |
8141 | /* Don't set GNU_PROPERTY_X86_FEATURE_2_MMX for prefetchtXXX nor | |
8142 | Xfence instructions. */ | |
8143 | if (i.tm.base_opcode != 0xf18 | |
8144 | && i.tm.base_opcode != 0xf0d | |
8145 | && i.tm.base_opcode != 0xfae | |
8146 | && (i.has_regmmx | |
8147 | || i.tm.cpu_flags.bitfield.cpummx | |
8148 | || i.tm.cpu_flags.bitfield.cpua3dnow | |
8149 | || i.tm.cpu_flags.bitfield.cpua3dnowa)) | |
8150 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MMX; | |
8151 | if (i.has_regxmm) | |
8152 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XMM; | |
8153 | if (i.has_regymm) | |
8154 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_YMM; | |
8155 | if (i.has_regzmm) | |
8156 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_ZMM; | |
8157 | if (i.tm.cpu_flags.bitfield.cpufxsr) | |
8158 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_FXSR; | |
8159 | if (i.tm.cpu_flags.bitfield.cpuxsave) | |
8160 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVE; | |
8161 | if (i.tm.cpu_flags.bitfield.cpuxsaveopt) | |
8162 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT; | |
8163 | if (i.tm.cpu_flags.bitfield.cpuxsavec) | |
8164 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEC; | |
8165 | } | |
8166 | #endif | |
8167 | ||
29b0f896 AM |
8168 | /* Tie dwarf2 debug info to the address at the start of the insn. |
8169 | We can't do this after the insn has been output as the current | |
8170 | frag may have been closed off. eg. by frag_var. */ | |
8171 | dwarf2_emit_insn (0); | |
8172 | ||
2bbd9c25 JJ |
8173 | insn_start_frag = frag_now; |
8174 | insn_start_off = frag_now_fix (); | |
8175 | ||
29b0f896 | 8176 | /* Output jumps. */ |
40fb9820 | 8177 | if (i.tm.opcode_modifier.jump) |
29b0f896 | 8178 | output_branch (); |
40fb9820 L |
8179 | else if (i.tm.opcode_modifier.jumpbyte |
8180 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 | 8181 | output_jump (); |
40fb9820 | 8182 | else if (i.tm.opcode_modifier.jumpintersegment) |
29b0f896 AM |
8183 | output_interseg_jump (); |
8184 | else | |
8185 | { | |
8186 | /* Output normal instructions here. */ | |
8187 | char *p; | |
8188 | unsigned char *q; | |
47465058 | 8189 | unsigned int j; |
331d2d0d | 8190 | unsigned int prefix; |
4dffcebc | 8191 | |
e4e00185 AS |
8192 | if (avoid_fence |
8193 | && i.tm.base_opcode == 0xfae | |
8194 | && i.operands == 1 | |
8195 | && i.imm_operands == 1 | |
8196 | && (i.op[0].imms->X_add_number == 0xe8 | |
8197 | || i.op[0].imms->X_add_number == 0xf0 | |
8198 | || i.op[0].imms->X_add_number == 0xf8)) | |
8199 | { | |
8200 | /* Encode lfence, mfence, and sfence as | |
8201 | f0 83 04 24 00 lock addl $0x0, (%{re}sp). */ | |
8202 | offsetT val = 0x240483f0ULL; | |
8203 | p = frag_more (5); | |
8204 | md_number_to_chars (p, val, 5); | |
8205 | return; | |
8206 | } | |
8207 | ||
d022bddd IT |
8208 | /* Some processors fail on LOCK prefix. This options makes |
8209 | assembler ignore LOCK prefix and serves as a workaround. */ | |
8210 | if (omit_lock_prefix) | |
8211 | { | |
8212 | if (i.tm.base_opcode == LOCK_PREFIX_OPCODE) | |
8213 | return; | |
8214 | i.prefix[LOCK_PREFIX] = 0; | |
8215 | } | |
8216 | ||
43234a1e L |
8217 | /* Since the VEX/EVEX prefix contains the implicit prefix, we |
8218 | don't need the explicit prefix. */ | |
8219 | if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex) | |
bc4bd9ab | 8220 | { |
c0f3af97 | 8221 | switch (i.tm.opcode_length) |
bc4bd9ab | 8222 | { |
c0f3af97 L |
8223 | case 3: |
8224 | if (i.tm.base_opcode & 0xff000000) | |
4dffcebc | 8225 | { |
c0f3af97 | 8226 | prefix = (i.tm.base_opcode >> 24) & 0xff; |
bd59a631 | 8227 | add_prefix (prefix); |
c0f3af97 L |
8228 | } |
8229 | break; | |
8230 | case 2: | |
8231 | if ((i.tm.base_opcode & 0xff0000) != 0) | |
8232 | { | |
8233 | prefix = (i.tm.base_opcode >> 16) & 0xff; | |
bd59a631 JB |
8234 | if (!i.tm.cpu_flags.bitfield.cpupadlock |
8235 | || prefix != REPE_PREFIX_OPCODE | |
8236 | || (i.prefix[REP_PREFIX] != REPE_PREFIX_OPCODE)) | |
4dffcebc L |
8237 | add_prefix (prefix); |
8238 | } | |
c0f3af97 L |
8239 | break; |
8240 | case 1: | |
8241 | break; | |
390c91cf L |
8242 | case 0: |
8243 | /* Check for pseudo prefixes. */ | |
8244 | as_bad_where (insn_start_frag->fr_file, | |
8245 | insn_start_frag->fr_line, | |
8246 | _("pseudo prefix without instruction")); | |
8247 | return; | |
c0f3af97 L |
8248 | default: |
8249 | abort (); | |
bc4bd9ab | 8250 | } |
c0f3af97 | 8251 | |
6d19a37a | 8252 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
cf61b747 L |
8253 | /* For x32, add a dummy REX_OPCODE prefix for mov/add with |
8254 | R_X86_64_GOTTPOFF relocation so that linker can safely | |
8255 | perform IE->LE optimization. */ | |
8256 | if (x86_elf_abi == X86_64_X32_ABI | |
8257 | && i.operands == 2 | |
8258 | && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF | |
8259 | && i.prefix[REX_PREFIX] == 0) | |
8260 | add_prefix (REX_OPCODE); | |
6d19a37a | 8261 | #endif |
cf61b747 | 8262 | |
c0f3af97 L |
8263 | /* The prefix bytes. */ |
8264 | for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) | |
8265 | if (*q) | |
8266 | FRAG_APPEND_1_CHAR (*q); | |
0f10071e | 8267 | } |
ae5c1c7b | 8268 | else |
c0f3af97 L |
8269 | { |
8270 | for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++) | |
8271 | if (*q) | |
8272 | switch (j) | |
8273 | { | |
8274 | case REX_PREFIX: | |
8275 | /* REX byte is encoded in VEX prefix. */ | |
8276 | break; | |
8277 | case SEG_PREFIX: | |
8278 | case ADDR_PREFIX: | |
8279 | FRAG_APPEND_1_CHAR (*q); | |
8280 | break; | |
8281 | default: | |
8282 | /* There should be no other prefixes for instructions | |
8283 | with VEX prefix. */ | |
8284 | abort (); | |
8285 | } | |
8286 | ||
43234a1e L |
8287 | /* For EVEX instructions i.vrex should become 0 after |
8288 | build_evex_prefix. For VEX instructions upper 16 registers | |
8289 | aren't available, so VREX should be 0. */ | |
8290 | if (i.vrex) | |
8291 | abort (); | |
c0f3af97 L |
8292 | /* Now the VEX prefix. */ |
8293 | p = frag_more (i.vex.length); | |
8294 | for (j = 0; j < i.vex.length; j++) | |
8295 | p[j] = i.vex.bytes[j]; | |
8296 | } | |
252b5132 | 8297 | |
29b0f896 | 8298 | /* Now the opcode; be careful about word order here! */ |
4dffcebc | 8299 | if (i.tm.opcode_length == 1) |
29b0f896 AM |
8300 | { |
8301 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
8302 | } | |
8303 | else | |
8304 | { | |
4dffcebc | 8305 | switch (i.tm.opcode_length) |
331d2d0d | 8306 | { |
43234a1e L |
8307 | case 4: |
8308 | p = frag_more (4); | |
8309 | *p++ = (i.tm.base_opcode >> 24) & 0xff; | |
8310 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
8311 | break; | |
4dffcebc | 8312 | case 3: |
331d2d0d L |
8313 | p = frag_more (3); |
8314 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
4dffcebc L |
8315 | break; |
8316 | case 2: | |
8317 | p = frag_more (2); | |
8318 | break; | |
8319 | default: | |
8320 | abort (); | |
8321 | break; | |
331d2d0d | 8322 | } |
0f10071e | 8323 | |
29b0f896 AM |
8324 | /* Put out high byte first: can't use md_number_to_chars! */ |
8325 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
8326 | *p = i.tm.base_opcode & 0xff; | |
8327 | } | |
3e73aa7c | 8328 | |
29b0f896 | 8329 | /* Now the modrm byte and sib byte (if present). */ |
40fb9820 | 8330 | if (i.tm.opcode_modifier.modrm) |
29b0f896 | 8331 | { |
4a3523fa L |
8332 | FRAG_APPEND_1_CHAR ((i.rm.regmem << 0 |
8333 | | i.rm.reg << 3 | |
8334 | | i.rm.mode << 6)); | |
29b0f896 AM |
8335 | /* If i.rm.regmem == ESP (4) |
8336 | && i.rm.mode != (Register mode) | |
8337 | && not 16 bit | |
8338 | ==> need second modrm byte. */ | |
8339 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
8340 | && i.rm.mode != 3 | |
dc821c5f | 8341 | && !(i.base_reg && i.base_reg->reg_type.bitfield.word)) |
4a3523fa L |
8342 | FRAG_APPEND_1_CHAR ((i.sib.base << 0 |
8343 | | i.sib.index << 3 | |
8344 | | i.sib.scale << 6)); | |
29b0f896 | 8345 | } |
3e73aa7c | 8346 | |
29b0f896 | 8347 | if (i.disp_operands) |
2bbd9c25 | 8348 | output_disp (insn_start_frag, insn_start_off); |
3e73aa7c | 8349 | |
29b0f896 | 8350 | if (i.imm_operands) |
2bbd9c25 | 8351 | output_imm (insn_start_frag, insn_start_off); |
29b0f896 | 8352 | } |
252b5132 | 8353 | |
29b0f896 AM |
8354 | #ifdef DEBUG386 |
8355 | if (flag_debug) | |
8356 | { | |
7b81dfbb | 8357 | pi ("" /*line*/, &i); |
29b0f896 AM |
8358 | } |
8359 | #endif /* DEBUG386 */ | |
8360 | } | |
252b5132 | 8361 | |
e205caa7 L |
8362 | /* Return the size of the displacement operand N. */ |
8363 | ||
8364 | static int | |
8365 | disp_size (unsigned int n) | |
8366 | { | |
8367 | int size = 4; | |
43234a1e | 8368 | |
b5014f7a | 8369 | if (i.types[n].bitfield.disp64) |
40fb9820 L |
8370 | size = 8; |
8371 | else if (i.types[n].bitfield.disp8) | |
8372 | size = 1; | |
8373 | else if (i.types[n].bitfield.disp16) | |
8374 | size = 2; | |
e205caa7 L |
8375 | return size; |
8376 | } | |
8377 | ||
8378 | /* Return the size of the immediate operand N. */ | |
8379 | ||
8380 | static int | |
8381 | imm_size (unsigned int n) | |
8382 | { | |
8383 | int size = 4; | |
40fb9820 L |
8384 | if (i.types[n].bitfield.imm64) |
8385 | size = 8; | |
8386 | else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) | |
8387 | size = 1; | |
8388 | else if (i.types[n].bitfield.imm16) | |
8389 | size = 2; | |
e205caa7 L |
8390 | return size; |
8391 | } | |
8392 | ||
29b0f896 | 8393 | static void |
64e74474 | 8394 | output_disp (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
8395 | { |
8396 | char *p; | |
8397 | unsigned int n; | |
252b5132 | 8398 | |
29b0f896 AM |
8399 | for (n = 0; n < i.operands; n++) |
8400 | { | |
b5014f7a | 8401 | if (operand_type_check (i.types[n], disp)) |
29b0f896 AM |
8402 | { |
8403 | if (i.op[n].disps->X_op == O_constant) | |
8404 | { | |
e205caa7 | 8405 | int size = disp_size (n); |
43234a1e | 8406 | offsetT val = i.op[n].disps->X_add_number; |
252b5132 | 8407 | |
629cfaf1 JB |
8408 | val = offset_in_range (val >> (size == 1 ? i.memshift : 0), |
8409 | size); | |
29b0f896 AM |
8410 | p = frag_more (size); |
8411 | md_number_to_chars (p, val, size); | |
8412 | } | |
8413 | else | |
8414 | { | |
f86103b7 | 8415 | enum bfd_reloc_code_real reloc_type; |
e205caa7 | 8416 | int size = disp_size (n); |
40fb9820 | 8417 | int sign = i.types[n].bitfield.disp32s; |
29b0f896 | 8418 | int pcrel = (i.flags[n] & Operand_PCrel) != 0; |
02a86693 | 8419 | fixS *fixP; |
29b0f896 | 8420 | |
e205caa7 | 8421 | /* We can't have 8 bit displacement here. */ |
9c2799c2 | 8422 | gas_assert (!i.types[n].bitfield.disp8); |
e205caa7 | 8423 | |
29b0f896 AM |
8424 | /* The PC relative address is computed relative |
8425 | to the instruction boundary, so in case immediate | |
8426 | fields follows, we need to adjust the value. */ | |
8427 | if (pcrel && i.imm_operands) | |
8428 | { | |
29b0f896 | 8429 | unsigned int n1; |
e205caa7 | 8430 | int sz = 0; |
252b5132 | 8431 | |
29b0f896 | 8432 | for (n1 = 0; n1 < i.operands; n1++) |
40fb9820 | 8433 | if (operand_type_check (i.types[n1], imm)) |
252b5132 | 8434 | { |
e205caa7 L |
8435 | /* Only one immediate is allowed for PC |
8436 | relative address. */ | |
9c2799c2 | 8437 | gas_assert (sz == 0); |
e205caa7 L |
8438 | sz = imm_size (n1); |
8439 | i.op[n].disps->X_add_number -= sz; | |
252b5132 | 8440 | } |
29b0f896 | 8441 | /* We should find the immediate. */ |
9c2799c2 | 8442 | gas_assert (sz != 0); |
29b0f896 | 8443 | } |
520dc8e8 | 8444 | |
29b0f896 | 8445 | p = frag_more (size); |
d258b828 | 8446 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
d6ab8113 | 8447 | if (GOT_symbol |
2bbd9c25 | 8448 | && GOT_symbol == i.op[n].disps->X_add_symbol |
d6ab8113 | 8449 | && (((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
8450 | || reloc_type == BFD_RELOC_X86_64_32S |
8451 | || (reloc_type == BFD_RELOC_64 | |
8452 | && object_64bit)) | |
d6ab8113 JB |
8453 | && (i.op[n].disps->X_op == O_symbol |
8454 | || (i.op[n].disps->X_op == O_add | |
8455 | && ((symbol_get_value_expression | |
8456 | (i.op[n].disps->X_op_symbol)->X_op) | |
8457 | == O_subtract)))) | |
8458 | || reloc_type == BFD_RELOC_32_PCREL)) | |
2bbd9c25 JJ |
8459 | { |
8460 | offsetT add; | |
8461 | ||
8462 | if (insn_start_frag == frag_now) | |
8463 | add = (p - frag_now->fr_literal) - insn_start_off; | |
8464 | else | |
8465 | { | |
8466 | fragS *fr; | |
8467 | ||
8468 | add = insn_start_frag->fr_fix - insn_start_off; | |
8469 | for (fr = insn_start_frag->fr_next; | |
8470 | fr && fr != frag_now; fr = fr->fr_next) | |
8471 | add += fr->fr_fix; | |
8472 | add += p - frag_now->fr_literal; | |
8473 | } | |
8474 | ||
4fa24527 | 8475 | if (!object_64bit) |
7b81dfbb AJ |
8476 | { |
8477 | reloc_type = BFD_RELOC_386_GOTPC; | |
8478 | i.op[n].imms->X_add_number += add; | |
8479 | } | |
8480 | else if (reloc_type == BFD_RELOC_64) | |
8481 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
d6ab8113 | 8482 | else |
7b81dfbb AJ |
8483 | /* Don't do the adjustment for x86-64, as there |
8484 | the pcrel addressing is relative to the _next_ | |
8485 | insn, and that is taken care of in other code. */ | |
d6ab8113 | 8486 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
2bbd9c25 | 8487 | } |
02a86693 L |
8488 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, |
8489 | size, i.op[n].disps, pcrel, | |
8490 | reloc_type); | |
8491 | /* Check for "call/jmp *mem", "mov mem, %reg", | |
8492 | "test %reg, mem" and "binop mem, %reg" where binop | |
8493 | is one of adc, add, and, cmp, or, sbb, sub, xor | |
e60f4d3b L |
8494 | instructions without data prefix. Always generate |
8495 | R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */ | |
8496 | if (i.prefix[DATA_PREFIX] == 0 | |
8497 | && (generate_relax_relocations | |
8498 | || (!object_64bit | |
8499 | && i.rm.mode == 0 | |
8500 | && i.rm.regmem == 5)) | |
0cb4071e L |
8501 | && (i.rm.mode == 2 |
8502 | || (i.rm.mode == 0 && i.rm.regmem == 5)) | |
02a86693 L |
8503 | && ((i.operands == 1 |
8504 | && i.tm.base_opcode == 0xff | |
8505 | && (i.rm.reg == 2 || i.rm.reg == 4)) | |
8506 | || (i.operands == 2 | |
8507 | && (i.tm.base_opcode == 0x8b | |
8508 | || i.tm.base_opcode == 0x85 | |
8509 | || (i.tm.base_opcode & 0xc7) == 0x03)))) | |
8510 | { | |
8511 | if (object_64bit) | |
8512 | { | |
8513 | fixP->fx_tcbit = i.rex != 0; | |
8514 | if (i.base_reg | |
e968fc9b | 8515 | && (i.base_reg->reg_num == RegIP)) |
02a86693 L |
8516 | fixP->fx_tcbit2 = 1; |
8517 | } | |
8518 | else | |
8519 | fixP->fx_tcbit2 = 1; | |
8520 | } | |
29b0f896 AM |
8521 | } |
8522 | } | |
8523 | } | |
8524 | } | |
252b5132 | 8525 | |
29b0f896 | 8526 | static void |
64e74474 | 8527 | output_imm (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
8528 | { |
8529 | char *p; | |
8530 | unsigned int n; | |
252b5132 | 8531 | |
29b0f896 AM |
8532 | for (n = 0; n < i.operands; n++) |
8533 | { | |
43234a1e L |
8534 | /* Skip SAE/RC Imm operand in EVEX. They are already handled. */ |
8535 | if (i.rounding && (int) n == i.rounding->operand) | |
8536 | continue; | |
8537 | ||
40fb9820 | 8538 | if (operand_type_check (i.types[n], imm)) |
29b0f896 AM |
8539 | { |
8540 | if (i.op[n].imms->X_op == O_constant) | |
8541 | { | |
e205caa7 | 8542 | int size = imm_size (n); |
29b0f896 | 8543 | offsetT val; |
b4cac588 | 8544 | |
29b0f896 AM |
8545 | val = offset_in_range (i.op[n].imms->X_add_number, |
8546 | size); | |
8547 | p = frag_more (size); | |
8548 | md_number_to_chars (p, val, size); | |
8549 | } | |
8550 | else | |
8551 | { | |
8552 | /* Not absolute_section. | |
8553 | Need a 32-bit fixup (don't support 8bit | |
8554 | non-absolute imms). Try to support other | |
8555 | sizes ... */ | |
f86103b7 | 8556 | enum bfd_reloc_code_real reloc_type; |
e205caa7 L |
8557 | int size = imm_size (n); |
8558 | int sign; | |
29b0f896 | 8559 | |
40fb9820 | 8560 | if (i.types[n].bitfield.imm32s |
a7d61044 | 8561 | && (i.suffix == QWORD_MNEM_SUFFIX |
40fb9820 | 8562 | || (!i.suffix && i.tm.opcode_modifier.no_lsuf))) |
29b0f896 | 8563 | sign = 1; |
e205caa7 L |
8564 | else |
8565 | sign = 0; | |
520dc8e8 | 8566 | |
29b0f896 | 8567 | p = frag_more (size); |
d258b828 | 8568 | reloc_type = reloc (size, 0, sign, i.reloc[n]); |
f86103b7 | 8569 | |
2bbd9c25 JJ |
8570 | /* This is tough to explain. We end up with this one if we |
8571 | * have operands that look like | |
8572 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to | |
8573 | * obtain the absolute address of the GOT, and it is strongly | |
8574 | * preferable from a performance point of view to avoid using | |
8575 | * a runtime relocation for this. The actual sequence of | |
8576 | * instructions often look something like: | |
8577 | * | |
8578 | * call .L66 | |
8579 | * .L66: | |
8580 | * popl %ebx | |
8581 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
8582 | * | |
8583 | * The call and pop essentially return the absolute address | |
8584 | * of the label .L66 and store it in %ebx. The linker itself | |
8585 | * will ultimately change the first operand of the addl so | |
8586 | * that %ebx points to the GOT, but to keep things simple, the | |
8587 | * .o file must have this operand set so that it generates not | |
8588 | * the absolute address of .L66, but the absolute address of | |
8589 | * itself. This allows the linker itself simply treat a GOTPC | |
8590 | * relocation as asking for a pcrel offset to the GOT to be | |
8591 | * added in, and the addend of the relocation is stored in the | |
8592 | * operand field for the instruction itself. | |
8593 | * | |
8594 | * Our job here is to fix the operand so that it would add | |
8595 | * the correct offset so that %ebx would point to itself. The | |
8596 | * thing that is tricky is that .-.L66 will point to the | |
8597 | * beginning of the instruction, so we need to further modify | |
8598 | * the operand so that it will point to itself. There are | |
8599 | * other cases where you have something like: | |
8600 | * | |
8601 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
8602 | * | |
8603 | * and here no correction would be required. Internally in | |
8604 | * the assembler we treat operands of this form as not being | |
8605 | * pcrel since the '.' is explicitly mentioned, and I wonder | |
8606 | * whether it would simplify matters to do it this way. Who | |
8607 | * knows. In earlier versions of the PIC patches, the | |
8608 | * pcrel_adjust field was used to store the correction, but | |
8609 | * since the expression is not pcrel, I felt it would be | |
8610 | * confusing to do it this way. */ | |
8611 | ||
d6ab8113 | 8612 | if ((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
8613 | || reloc_type == BFD_RELOC_X86_64_32S |
8614 | || reloc_type == BFD_RELOC_64) | |
29b0f896 AM |
8615 | && GOT_symbol |
8616 | && GOT_symbol == i.op[n].imms->X_add_symbol | |
8617 | && (i.op[n].imms->X_op == O_symbol | |
8618 | || (i.op[n].imms->X_op == O_add | |
8619 | && ((symbol_get_value_expression | |
8620 | (i.op[n].imms->X_op_symbol)->X_op) | |
8621 | == O_subtract)))) | |
8622 | { | |
2bbd9c25 JJ |
8623 | offsetT add; |
8624 | ||
8625 | if (insn_start_frag == frag_now) | |
8626 | add = (p - frag_now->fr_literal) - insn_start_off; | |
8627 | else | |
8628 | { | |
8629 | fragS *fr; | |
8630 | ||
8631 | add = insn_start_frag->fr_fix - insn_start_off; | |
8632 | for (fr = insn_start_frag->fr_next; | |
8633 | fr && fr != frag_now; fr = fr->fr_next) | |
8634 | add += fr->fr_fix; | |
8635 | add += p - frag_now->fr_literal; | |
8636 | } | |
8637 | ||
4fa24527 | 8638 | if (!object_64bit) |
d6ab8113 | 8639 | reloc_type = BFD_RELOC_386_GOTPC; |
7b81dfbb | 8640 | else if (size == 4) |
d6ab8113 | 8641 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
7b81dfbb AJ |
8642 | else if (size == 8) |
8643 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
2bbd9c25 | 8644 | i.op[n].imms->X_add_number += add; |
29b0f896 | 8645 | } |
29b0f896 AM |
8646 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
8647 | i.op[n].imms, 0, reloc_type); | |
8648 | } | |
8649 | } | |
8650 | } | |
252b5132 RH |
8651 | } |
8652 | \f | |
d182319b JB |
8653 | /* x86_cons_fix_new is called via the expression parsing code when a |
8654 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
d182319b JB |
8655 | static int cons_sign = -1; |
8656 | ||
8657 | void | |
e3bb37b5 | 8658 | x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, |
62ebcb5c | 8659 | expressionS *exp, bfd_reloc_code_real_type r) |
d182319b | 8660 | { |
d258b828 | 8661 | r = reloc (len, 0, cons_sign, r); |
d182319b JB |
8662 | |
8663 | #ifdef TE_PE | |
8664 | if (exp->X_op == O_secrel) | |
8665 | { | |
8666 | exp->X_op = O_symbol; | |
8667 | r = BFD_RELOC_32_SECREL; | |
8668 | } | |
8669 | #endif | |
8670 | ||
8671 | fix_new_exp (frag, off, len, exp, 0, r); | |
8672 | } | |
8673 | ||
357d1bd8 L |
8674 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
8675 | purpose of the `.dc.a' internal pseudo-op. */ | |
8676 | ||
8677 | int | |
8678 | x86_address_bytes (void) | |
8679 | { | |
8680 | if ((stdoutput->arch_info->mach & bfd_mach_x64_32)) | |
8681 | return 4; | |
8682 | return stdoutput->arch_info->bits_per_address / 8; | |
8683 | } | |
8684 | ||
d382c579 TG |
8685 | #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \ |
8686 | || defined (LEX_AT) | |
d258b828 | 8687 | # define lex_got(reloc, adjust, types) NULL |
718ddfc0 | 8688 | #else |
f3c180ae AM |
8689 | /* Parse operands of the form |
8690 | <symbol>@GOTOFF+<nnn> | |
8691 | and similar .plt or .got references. | |
8692 | ||
8693 | If we find one, set up the correct relocation in RELOC and copy the | |
8694 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
8695 | parsing by the calling routine. Return this buffer, and if ADJUST | |
8696 | is non-null set it to the length of the string we removed from the | |
8697 | input line. Otherwise return NULL. */ | |
8698 | static char * | |
91d6fa6a | 8699 | lex_got (enum bfd_reloc_code_real *rel, |
64e74474 | 8700 | int *adjust, |
d258b828 | 8701 | i386_operand_type *types) |
f3c180ae | 8702 | { |
7b81dfbb AJ |
8703 | /* Some of the relocations depend on the size of what field is to |
8704 | be relocated. But in our callers i386_immediate and i386_displacement | |
8705 | we don't yet know the operand size (this will be set by insn | |
8706 | matching). Hence we record the word32 relocation here, | |
8707 | and adjust the reloc according to the real size in reloc(). */ | |
f3c180ae AM |
8708 | static const struct { |
8709 | const char *str; | |
cff8d58a | 8710 | int len; |
4fa24527 | 8711 | const enum bfd_reloc_code_real rel[2]; |
40fb9820 | 8712 | const i386_operand_type types64; |
f3c180ae | 8713 | } gotrel[] = { |
8ce3d284 | 8714 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
8715 | { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32, |
8716 | BFD_RELOC_SIZE32 }, | |
8717 | OPERAND_TYPE_IMM32_64 }, | |
8ce3d284 | 8718 | #endif |
cff8d58a L |
8719 | { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real, |
8720 | BFD_RELOC_X86_64_PLTOFF64 }, | |
40fb9820 | 8721 | OPERAND_TYPE_IMM64 }, |
cff8d58a L |
8722 | { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32, |
8723 | BFD_RELOC_X86_64_PLT32 }, | |
40fb9820 | 8724 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8725 | { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real, |
8726 | BFD_RELOC_X86_64_GOTPLT64 }, | |
40fb9820 | 8727 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
8728 | { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF, |
8729 | BFD_RELOC_X86_64_GOTOFF64 }, | |
40fb9820 | 8730 | OPERAND_TYPE_IMM64_DISP64 }, |
cff8d58a L |
8731 | { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real, |
8732 | BFD_RELOC_X86_64_GOTPCREL }, | |
40fb9820 | 8733 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8734 | { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD, |
8735 | BFD_RELOC_X86_64_TLSGD }, | |
40fb9820 | 8736 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8737 | { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM, |
8738 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 8739 | OPERAND_TYPE_NONE }, |
cff8d58a L |
8740 | { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real, |
8741 | BFD_RELOC_X86_64_TLSLD }, | |
40fb9820 | 8742 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8743 | { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32, |
8744 | BFD_RELOC_X86_64_GOTTPOFF }, | |
40fb9820 | 8745 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8746 | { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32, |
8747 | BFD_RELOC_X86_64_TPOFF32 }, | |
40fb9820 | 8748 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
8749 | { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE, |
8750 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 8751 | OPERAND_TYPE_NONE }, |
cff8d58a L |
8752 | { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32, |
8753 | BFD_RELOC_X86_64_DTPOFF32 }, | |
40fb9820 | 8754 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
cff8d58a L |
8755 | { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE, |
8756 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 8757 | OPERAND_TYPE_NONE }, |
cff8d58a L |
8758 | { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE, |
8759 | _dummy_first_bfd_reloc_code_real }, | |
40fb9820 | 8760 | OPERAND_TYPE_NONE }, |
cff8d58a L |
8761 | { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32, |
8762 | BFD_RELOC_X86_64_GOT32 }, | |
40fb9820 | 8763 | OPERAND_TYPE_IMM32_32S_64_DISP32 }, |
cff8d58a L |
8764 | { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC, |
8765 | BFD_RELOC_X86_64_GOTPC32_TLSDESC }, | |
40fb9820 | 8766 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
cff8d58a L |
8767 | { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL, |
8768 | BFD_RELOC_X86_64_TLSDESC_CALL }, | |
40fb9820 | 8769 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
f3c180ae AM |
8770 | }; |
8771 | char *cp; | |
8772 | unsigned int j; | |
8773 | ||
d382c579 | 8774 | #if defined (OBJ_MAYBE_ELF) |
718ddfc0 JB |
8775 | if (!IS_ELF) |
8776 | return NULL; | |
d382c579 | 8777 | #endif |
718ddfc0 | 8778 | |
f3c180ae | 8779 | for (cp = input_line_pointer; *cp != '@'; cp++) |
67c11a9b | 8780 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') |
f3c180ae AM |
8781 | return NULL; |
8782 | ||
47465058 | 8783 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) |
f3c180ae | 8784 | { |
cff8d58a | 8785 | int len = gotrel[j].len; |
28f81592 | 8786 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae | 8787 | { |
4fa24527 | 8788 | if (gotrel[j].rel[object_64bit] != 0) |
f3c180ae | 8789 | { |
28f81592 AM |
8790 | int first, second; |
8791 | char *tmpbuf, *past_reloc; | |
f3c180ae | 8792 | |
91d6fa6a | 8793 | *rel = gotrel[j].rel[object_64bit]; |
f3c180ae | 8794 | |
3956db08 JB |
8795 | if (types) |
8796 | { | |
8797 | if (flag_code != CODE_64BIT) | |
40fb9820 L |
8798 | { |
8799 | types->bitfield.imm32 = 1; | |
8800 | types->bitfield.disp32 = 1; | |
8801 | } | |
3956db08 JB |
8802 | else |
8803 | *types = gotrel[j].types64; | |
8804 | } | |
8805 | ||
8fd4256d | 8806 | if (j != 0 && GOT_symbol == NULL) |
f3c180ae AM |
8807 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); |
8808 | ||
28f81592 | 8809 | /* The length of the first part of our input line. */ |
f3c180ae | 8810 | first = cp - input_line_pointer; |
28f81592 AM |
8811 | |
8812 | /* The second part goes from after the reloc token until | |
67c11a9b | 8813 | (and including) an end_of_line char or comma. */ |
28f81592 | 8814 | past_reloc = cp + 1 + len; |
67c11a9b AM |
8815 | cp = past_reloc; |
8816 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
8817 | ++cp; | |
8818 | second = cp + 1 - past_reloc; | |
28f81592 AM |
8819 | |
8820 | /* Allocate and copy string. The trailing NUL shouldn't | |
8821 | be necessary, but be safe. */ | |
add39d23 | 8822 | tmpbuf = XNEWVEC (char, first + second + 2); |
f3c180ae | 8823 | memcpy (tmpbuf, input_line_pointer, first); |
0787a12d AM |
8824 | if (second != 0 && *past_reloc != ' ') |
8825 | /* Replace the relocation token with ' ', so that | |
8826 | errors like foo@GOTOFF1 will be detected. */ | |
8827 | tmpbuf[first++] = ' '; | |
af89796a L |
8828 | else |
8829 | /* Increment length by 1 if the relocation token is | |
8830 | removed. */ | |
8831 | len++; | |
8832 | if (adjust) | |
8833 | *adjust = len; | |
0787a12d AM |
8834 | memcpy (tmpbuf + first, past_reloc, second); |
8835 | tmpbuf[first + second] = '\0'; | |
f3c180ae AM |
8836 | return tmpbuf; |
8837 | } | |
8838 | ||
4fa24527 JB |
8839 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
8840 | gotrel[j].str, 1 << (5 + object_64bit)); | |
f3c180ae AM |
8841 | return NULL; |
8842 | } | |
8843 | } | |
8844 | ||
8845 | /* Might be a symbol version string. Don't as_bad here. */ | |
8846 | return NULL; | |
8847 | } | |
4e4f7c87 | 8848 | #endif |
f3c180ae | 8849 | |
a988325c NC |
8850 | #ifdef TE_PE |
8851 | #ifdef lex_got | |
8852 | #undef lex_got | |
8853 | #endif | |
8854 | /* Parse operands of the form | |
8855 | <symbol>@SECREL32+<nnn> | |
8856 | ||
8857 | If we find one, set up the correct relocation in RELOC and copy the | |
8858 | input string, minus the `@SECREL32' into a malloc'd buffer for | |
8859 | parsing by the calling routine. Return this buffer, and if ADJUST | |
8860 | is non-null set it to the length of the string we removed from the | |
34bca508 L |
8861 | input line. Otherwise return NULL. |
8862 | ||
a988325c NC |
8863 | This function is copied from the ELF version above adjusted for PE targets. */ |
8864 | ||
8865 | static char * | |
8866 | lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED, | |
8867 | int *adjust ATTRIBUTE_UNUSED, | |
d258b828 | 8868 | i386_operand_type *types) |
a988325c NC |
8869 | { |
8870 | static const struct | |
8871 | { | |
8872 | const char *str; | |
8873 | int len; | |
8874 | const enum bfd_reloc_code_real rel[2]; | |
8875 | const i386_operand_type types64; | |
8876 | } | |
8877 | gotrel[] = | |
8878 | { | |
8879 | { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL, | |
8880 | BFD_RELOC_32_SECREL }, | |
8881 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, | |
8882 | }; | |
8883 | ||
8884 | char *cp; | |
8885 | unsigned j; | |
8886 | ||
8887 | for (cp = input_line_pointer; *cp != '@'; cp++) | |
8888 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') | |
8889 | return NULL; | |
8890 | ||
8891 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) | |
8892 | { | |
8893 | int len = gotrel[j].len; | |
8894 | ||
8895 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) | |
8896 | { | |
8897 | if (gotrel[j].rel[object_64bit] != 0) | |
8898 | { | |
8899 | int first, second; | |
8900 | char *tmpbuf, *past_reloc; | |
8901 | ||
8902 | *rel = gotrel[j].rel[object_64bit]; | |
8903 | if (adjust) | |
8904 | *adjust = len; | |
8905 | ||
8906 | if (types) | |
8907 | { | |
8908 | if (flag_code != CODE_64BIT) | |
8909 | { | |
8910 | types->bitfield.imm32 = 1; | |
8911 | types->bitfield.disp32 = 1; | |
8912 | } | |
8913 | else | |
8914 | *types = gotrel[j].types64; | |
8915 | } | |
8916 | ||
8917 | /* The length of the first part of our input line. */ | |
8918 | first = cp - input_line_pointer; | |
8919 | ||
8920 | /* The second part goes from after the reloc token until | |
8921 | (and including) an end_of_line char or comma. */ | |
8922 | past_reloc = cp + 1 + len; | |
8923 | cp = past_reloc; | |
8924 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
8925 | ++cp; | |
8926 | second = cp + 1 - past_reloc; | |
8927 | ||
8928 | /* Allocate and copy string. The trailing NUL shouldn't | |
8929 | be necessary, but be safe. */ | |
add39d23 | 8930 | tmpbuf = XNEWVEC (char, first + second + 2); |
a988325c NC |
8931 | memcpy (tmpbuf, input_line_pointer, first); |
8932 | if (second != 0 && *past_reloc != ' ') | |
8933 | /* Replace the relocation token with ' ', so that | |
8934 | errors like foo@SECLREL321 will be detected. */ | |
8935 | tmpbuf[first++] = ' '; | |
8936 | memcpy (tmpbuf + first, past_reloc, second); | |
8937 | tmpbuf[first + second] = '\0'; | |
8938 | return tmpbuf; | |
8939 | } | |
8940 | ||
8941 | as_bad (_("@%s reloc is not supported with %d-bit output format"), | |
8942 | gotrel[j].str, 1 << (5 + object_64bit)); | |
8943 | return NULL; | |
8944 | } | |
8945 | } | |
8946 | ||
8947 | /* Might be a symbol version string. Don't as_bad here. */ | |
8948 | return NULL; | |
8949 | } | |
8950 | ||
8951 | #endif /* TE_PE */ | |
8952 | ||
62ebcb5c | 8953 | bfd_reloc_code_real_type |
e3bb37b5 | 8954 | x86_cons (expressionS *exp, int size) |
f3c180ae | 8955 | { |
62ebcb5c AM |
8956 | bfd_reloc_code_real_type got_reloc = NO_RELOC; |
8957 | ||
ee86248c JB |
8958 | intel_syntax = -intel_syntax; |
8959 | ||
3c7b9c2c | 8960 | exp->X_md = 0; |
4fa24527 | 8961 | if (size == 4 || (object_64bit && size == 8)) |
f3c180ae AM |
8962 | { |
8963 | /* Handle @GOTOFF and the like in an expression. */ | |
8964 | char *save; | |
8965 | char *gotfree_input_line; | |
4a57f2cf | 8966 | int adjust = 0; |
f3c180ae AM |
8967 | |
8968 | save = input_line_pointer; | |
d258b828 | 8969 | gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); |
f3c180ae AM |
8970 | if (gotfree_input_line) |
8971 | input_line_pointer = gotfree_input_line; | |
8972 | ||
8973 | expression (exp); | |
8974 | ||
8975 | if (gotfree_input_line) | |
8976 | { | |
8977 | /* expression () has merrily parsed up to the end of line, | |
8978 | or a comma - in the wrong buffer. Transfer how far | |
8979 | input_line_pointer has moved to the right buffer. */ | |
8980 | input_line_pointer = (save | |
8981 | + (input_line_pointer - gotfree_input_line) | |
8982 | + adjust); | |
8983 | free (gotfree_input_line); | |
3992d3b7 AM |
8984 | if (exp->X_op == O_constant |
8985 | || exp->X_op == O_absent | |
8986 | || exp->X_op == O_illegal | |
0398aac5 | 8987 | || exp->X_op == O_register |
3992d3b7 AM |
8988 | || exp->X_op == O_big) |
8989 | { | |
8990 | char c = *input_line_pointer; | |
8991 | *input_line_pointer = 0; | |
8992 | as_bad (_("missing or invalid expression `%s'"), save); | |
8993 | *input_line_pointer = c; | |
8994 | } | |
b9519cfe L |
8995 | else if ((got_reloc == BFD_RELOC_386_PLT32 |
8996 | || got_reloc == BFD_RELOC_X86_64_PLT32) | |
8997 | && exp->X_op != O_symbol) | |
8998 | { | |
8999 | char c = *input_line_pointer; | |
9000 | *input_line_pointer = 0; | |
9001 | as_bad (_("invalid PLT expression `%s'"), save); | |
9002 | *input_line_pointer = c; | |
9003 | } | |
f3c180ae AM |
9004 | } |
9005 | } | |
9006 | else | |
9007 | expression (exp); | |
ee86248c JB |
9008 | |
9009 | intel_syntax = -intel_syntax; | |
9010 | ||
9011 | if (intel_syntax) | |
9012 | i386_intel_simplify (exp); | |
62ebcb5c AM |
9013 | |
9014 | return got_reloc; | |
f3c180ae | 9015 | } |
f3c180ae | 9016 | |
9f32dd5b L |
9017 | static void |
9018 | signed_cons (int size) | |
6482c264 | 9019 | { |
d182319b JB |
9020 | if (flag_code == CODE_64BIT) |
9021 | cons_sign = 1; | |
9022 | cons (size); | |
9023 | cons_sign = -1; | |
6482c264 NC |
9024 | } |
9025 | ||
d182319b | 9026 | #ifdef TE_PE |
6482c264 | 9027 | static void |
7016a5d5 | 9028 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
6482c264 NC |
9029 | { |
9030 | expressionS exp; | |
9031 | ||
9032 | do | |
9033 | { | |
9034 | expression (&exp); | |
9035 | if (exp.X_op == O_symbol) | |
9036 | exp.X_op = O_secrel; | |
9037 | ||
9038 | emit_expr (&exp, 4); | |
9039 | } | |
9040 | while (*input_line_pointer++ == ','); | |
9041 | ||
9042 | input_line_pointer--; | |
9043 | demand_empty_rest_of_line (); | |
9044 | } | |
6482c264 NC |
9045 | #endif |
9046 | ||
43234a1e L |
9047 | /* Handle Vector operations. */ |
9048 | ||
9049 | static char * | |
9050 | check_VecOperations (char *op_string, char *op_end) | |
9051 | { | |
9052 | const reg_entry *mask; | |
9053 | const char *saved; | |
9054 | char *end_op; | |
9055 | ||
9056 | while (*op_string | |
9057 | && (op_end == NULL || op_string < op_end)) | |
9058 | { | |
9059 | saved = op_string; | |
9060 | if (*op_string == '{') | |
9061 | { | |
9062 | op_string++; | |
9063 | ||
9064 | /* Check broadcasts. */ | |
9065 | if (strncmp (op_string, "1to", 3) == 0) | |
9066 | { | |
9067 | int bcst_type; | |
9068 | ||
9069 | if (i.broadcast) | |
9070 | goto duplicated_vec_op; | |
9071 | ||
9072 | op_string += 3; | |
9073 | if (*op_string == '8') | |
8e6e0792 | 9074 | bcst_type = 8; |
b28d1bda | 9075 | else if (*op_string == '4') |
8e6e0792 | 9076 | bcst_type = 4; |
b28d1bda | 9077 | else if (*op_string == '2') |
8e6e0792 | 9078 | bcst_type = 2; |
43234a1e L |
9079 | else if (*op_string == '1' |
9080 | && *(op_string+1) == '6') | |
9081 | { | |
8e6e0792 | 9082 | bcst_type = 16; |
43234a1e L |
9083 | op_string++; |
9084 | } | |
9085 | else | |
9086 | { | |
9087 | as_bad (_("Unsupported broadcast: `%s'"), saved); | |
9088 | return NULL; | |
9089 | } | |
9090 | op_string++; | |
9091 | ||
9092 | broadcast_op.type = bcst_type; | |
9093 | broadcast_op.operand = this_operand; | |
1f75763a | 9094 | broadcast_op.bytes = 0; |
43234a1e L |
9095 | i.broadcast = &broadcast_op; |
9096 | } | |
9097 | /* Check masking operation. */ | |
9098 | else if ((mask = parse_register (op_string, &end_op)) != NULL) | |
9099 | { | |
9100 | /* k0 can't be used for write mask. */ | |
6d2cd6b2 | 9101 | if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0) |
43234a1e | 9102 | { |
6d2cd6b2 JB |
9103 | as_bad (_("`%s%s' can't be used for write mask"), |
9104 | register_prefix, mask->reg_name); | |
43234a1e L |
9105 | return NULL; |
9106 | } | |
9107 | ||
9108 | if (!i.mask) | |
9109 | { | |
9110 | mask_op.mask = mask; | |
9111 | mask_op.zeroing = 0; | |
9112 | mask_op.operand = this_operand; | |
9113 | i.mask = &mask_op; | |
9114 | } | |
9115 | else | |
9116 | { | |
9117 | if (i.mask->mask) | |
9118 | goto duplicated_vec_op; | |
9119 | ||
9120 | i.mask->mask = mask; | |
9121 | ||
9122 | /* Only "{z}" is allowed here. No need to check | |
9123 | zeroing mask explicitly. */ | |
9124 | if (i.mask->operand != this_operand) | |
9125 | { | |
9126 | as_bad (_("invalid write mask `%s'"), saved); | |
9127 | return NULL; | |
9128 | } | |
9129 | } | |
9130 | ||
9131 | op_string = end_op; | |
9132 | } | |
9133 | /* Check zeroing-flag for masking operation. */ | |
9134 | else if (*op_string == 'z') | |
9135 | { | |
9136 | if (!i.mask) | |
9137 | { | |
9138 | mask_op.mask = NULL; | |
9139 | mask_op.zeroing = 1; | |
9140 | mask_op.operand = this_operand; | |
9141 | i.mask = &mask_op; | |
9142 | } | |
9143 | else | |
9144 | { | |
9145 | if (i.mask->zeroing) | |
9146 | { | |
9147 | duplicated_vec_op: | |
9148 | as_bad (_("duplicated `%s'"), saved); | |
9149 | return NULL; | |
9150 | } | |
9151 | ||
9152 | i.mask->zeroing = 1; | |
9153 | ||
9154 | /* Only "{%k}" is allowed here. No need to check mask | |
9155 | register explicitly. */ | |
9156 | if (i.mask->operand != this_operand) | |
9157 | { | |
9158 | as_bad (_("invalid zeroing-masking `%s'"), | |
9159 | saved); | |
9160 | return NULL; | |
9161 | } | |
9162 | } | |
9163 | ||
9164 | op_string++; | |
9165 | } | |
9166 | else | |
9167 | goto unknown_vec_op; | |
9168 | ||
9169 | if (*op_string != '}') | |
9170 | { | |
9171 | as_bad (_("missing `}' in `%s'"), saved); | |
9172 | return NULL; | |
9173 | } | |
9174 | op_string++; | |
0ba3a731 L |
9175 | |
9176 | /* Strip whitespace since the addition of pseudo prefixes | |
9177 | changed how the scrubber treats '{'. */ | |
9178 | if (is_space_char (*op_string)) | |
9179 | ++op_string; | |
9180 | ||
43234a1e L |
9181 | continue; |
9182 | } | |
9183 | unknown_vec_op: | |
9184 | /* We don't know this one. */ | |
9185 | as_bad (_("unknown vector operation: `%s'"), saved); | |
9186 | return NULL; | |
9187 | } | |
9188 | ||
6d2cd6b2 JB |
9189 | if (i.mask && i.mask->zeroing && !i.mask->mask) |
9190 | { | |
9191 | as_bad (_("zeroing-masking only allowed with write mask")); | |
9192 | return NULL; | |
9193 | } | |
9194 | ||
43234a1e L |
9195 | return op_string; |
9196 | } | |
9197 | ||
252b5132 | 9198 | static int |
70e41ade | 9199 | i386_immediate (char *imm_start) |
252b5132 RH |
9200 | { |
9201 | char *save_input_line_pointer; | |
f3c180ae | 9202 | char *gotfree_input_line; |
252b5132 | 9203 | segT exp_seg = 0; |
47926f60 | 9204 | expressionS *exp; |
40fb9820 L |
9205 | i386_operand_type types; |
9206 | ||
0dfbf9d7 | 9207 | operand_type_set (&types, ~0); |
252b5132 RH |
9208 | |
9209 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
9210 | { | |
31b2323c L |
9211 | as_bad (_("at most %d immediate operands are allowed"), |
9212 | MAX_IMMEDIATE_OPERANDS); | |
252b5132 RH |
9213 | return 0; |
9214 | } | |
9215 | ||
9216 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 9217 | i.op[this_operand].imms = exp; |
252b5132 RH |
9218 | |
9219 | if (is_space_char (*imm_start)) | |
9220 | ++imm_start; | |
9221 | ||
9222 | save_input_line_pointer = input_line_pointer; | |
9223 | input_line_pointer = imm_start; | |
9224 | ||
d258b828 | 9225 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
9226 | if (gotfree_input_line) |
9227 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
9228 | |
9229 | exp_seg = expression (exp); | |
9230 | ||
83183c0c | 9231 | SKIP_WHITESPACE (); |
43234a1e L |
9232 | |
9233 | /* Handle vector operations. */ | |
9234 | if (*input_line_pointer == '{') | |
9235 | { | |
9236 | input_line_pointer = check_VecOperations (input_line_pointer, | |
9237 | NULL); | |
9238 | if (input_line_pointer == NULL) | |
9239 | return 0; | |
9240 | } | |
9241 | ||
252b5132 | 9242 | if (*input_line_pointer) |
f3c180ae | 9243 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
9244 | |
9245 | input_line_pointer = save_input_line_pointer; | |
f3c180ae | 9246 | if (gotfree_input_line) |
ee86248c JB |
9247 | { |
9248 | free (gotfree_input_line); | |
9249 | ||
9250 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
9251 | exp->X_op = O_illegal; | |
9252 | } | |
9253 | ||
9254 | return i386_finalize_immediate (exp_seg, exp, types, imm_start); | |
9255 | } | |
252b5132 | 9256 | |
ee86248c JB |
9257 | static int |
9258 | i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
9259 | i386_operand_type types, const char *imm_start) | |
9260 | { | |
9261 | if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big) | |
252b5132 | 9262 | { |
313c53d1 L |
9263 | if (imm_start) |
9264 | as_bad (_("missing or invalid immediate expression `%s'"), | |
9265 | imm_start); | |
3992d3b7 | 9266 | return 0; |
252b5132 | 9267 | } |
3e73aa7c | 9268 | else if (exp->X_op == O_constant) |
252b5132 | 9269 | { |
47926f60 | 9270 | /* Size it properly later. */ |
40fb9820 | 9271 | i.types[this_operand].bitfield.imm64 = 1; |
13f864ae L |
9272 | /* If not 64bit, sign extend val. */ |
9273 | if (flag_code != CODE_64BIT | |
4eed87de AM |
9274 | && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) |
9275 | exp->X_add_number | |
9276 | = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
252b5132 | 9277 | } |
4c63da97 | 9278 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
f86103b7 | 9279 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 9280 | && exp_seg != absolute_section |
47926f60 | 9281 | && exp_seg != text_section |
24eab124 AM |
9282 | && exp_seg != data_section |
9283 | && exp_seg != bss_section | |
9284 | && exp_seg != undefined_section | |
f86103b7 | 9285 | && !bfd_is_com_section (exp_seg)) |
252b5132 | 9286 | { |
d0b47220 | 9287 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
252b5132 RH |
9288 | return 0; |
9289 | } | |
9290 | #endif | |
a841bdf5 | 9291 | else if (!intel_syntax && exp_seg == reg_section) |
bb8f5920 | 9292 | { |
313c53d1 L |
9293 | if (imm_start) |
9294 | as_bad (_("illegal immediate register operand %s"), imm_start); | |
bb8f5920 L |
9295 | return 0; |
9296 | } | |
252b5132 RH |
9297 | else |
9298 | { | |
9299 | /* This is an address. The size of the address will be | |
24eab124 | 9300 | determined later, depending on destination register, |
3e73aa7c | 9301 | suffix, or the default for the section. */ |
40fb9820 L |
9302 | i.types[this_operand].bitfield.imm8 = 1; |
9303 | i.types[this_operand].bitfield.imm16 = 1; | |
9304 | i.types[this_operand].bitfield.imm32 = 1; | |
9305 | i.types[this_operand].bitfield.imm32s = 1; | |
9306 | i.types[this_operand].bitfield.imm64 = 1; | |
c6fb90c8 L |
9307 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
9308 | types); | |
252b5132 RH |
9309 | } |
9310 | ||
9311 | return 1; | |
9312 | } | |
9313 | ||
551c1ca1 | 9314 | static char * |
e3bb37b5 | 9315 | i386_scale (char *scale) |
252b5132 | 9316 | { |
551c1ca1 AM |
9317 | offsetT val; |
9318 | char *save = input_line_pointer; | |
252b5132 | 9319 | |
551c1ca1 AM |
9320 | input_line_pointer = scale; |
9321 | val = get_absolute_expression (); | |
9322 | ||
9323 | switch (val) | |
252b5132 | 9324 | { |
551c1ca1 | 9325 | case 1: |
252b5132 RH |
9326 | i.log2_scale_factor = 0; |
9327 | break; | |
551c1ca1 | 9328 | case 2: |
252b5132 RH |
9329 | i.log2_scale_factor = 1; |
9330 | break; | |
551c1ca1 | 9331 | case 4: |
252b5132 RH |
9332 | i.log2_scale_factor = 2; |
9333 | break; | |
551c1ca1 | 9334 | case 8: |
252b5132 RH |
9335 | i.log2_scale_factor = 3; |
9336 | break; | |
9337 | default: | |
a724f0f4 JB |
9338 | { |
9339 | char sep = *input_line_pointer; | |
9340 | ||
9341 | *input_line_pointer = '\0'; | |
9342 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
9343 | scale); | |
9344 | *input_line_pointer = sep; | |
9345 | input_line_pointer = save; | |
9346 | return NULL; | |
9347 | } | |
252b5132 | 9348 | } |
29b0f896 | 9349 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
252b5132 RH |
9350 | { |
9351 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 9352 | 1 << i.log2_scale_factor); |
252b5132 | 9353 | i.log2_scale_factor = 0; |
252b5132 | 9354 | } |
551c1ca1 AM |
9355 | scale = input_line_pointer; |
9356 | input_line_pointer = save; | |
9357 | return scale; | |
252b5132 RH |
9358 | } |
9359 | ||
252b5132 | 9360 | static int |
e3bb37b5 | 9361 | i386_displacement (char *disp_start, char *disp_end) |
252b5132 | 9362 | { |
29b0f896 | 9363 | expressionS *exp; |
252b5132 RH |
9364 | segT exp_seg = 0; |
9365 | char *save_input_line_pointer; | |
f3c180ae | 9366 | char *gotfree_input_line; |
40fb9820 L |
9367 | int override; |
9368 | i386_operand_type bigdisp, types = anydisp; | |
3992d3b7 | 9369 | int ret; |
252b5132 | 9370 | |
31b2323c L |
9371 | if (i.disp_operands == MAX_MEMORY_OPERANDS) |
9372 | { | |
9373 | as_bad (_("at most %d displacement operands are allowed"), | |
9374 | MAX_MEMORY_OPERANDS); | |
9375 | return 0; | |
9376 | } | |
9377 | ||
0dfbf9d7 | 9378 | operand_type_set (&bigdisp, 0); |
40fb9820 L |
9379 | if ((i.types[this_operand].bitfield.jumpabsolute) |
9380 | || (!current_templates->start->opcode_modifier.jump | |
9381 | && !current_templates->start->opcode_modifier.jumpdword)) | |
e05278af | 9382 | { |
40fb9820 | 9383 | bigdisp.bitfield.disp32 = 1; |
e05278af | 9384 | override = (i.prefix[ADDR_PREFIX] != 0); |
40fb9820 L |
9385 | if (flag_code == CODE_64BIT) |
9386 | { | |
9387 | if (!override) | |
9388 | { | |
9389 | bigdisp.bitfield.disp32s = 1; | |
9390 | bigdisp.bitfield.disp64 = 1; | |
9391 | } | |
9392 | } | |
9393 | else if ((flag_code == CODE_16BIT) ^ override) | |
9394 | { | |
9395 | bigdisp.bitfield.disp32 = 0; | |
9396 | bigdisp.bitfield.disp16 = 1; | |
9397 | } | |
e05278af JB |
9398 | } |
9399 | else | |
9400 | { | |
9401 | /* For PC-relative branches, the width of the displacement | |
9402 | is dependent upon data size, not address size. */ | |
e05278af | 9403 | override = (i.prefix[DATA_PREFIX] != 0); |
40fb9820 L |
9404 | if (flag_code == CODE_64BIT) |
9405 | { | |
9406 | if (override || i.suffix == WORD_MNEM_SUFFIX) | |
9407 | bigdisp.bitfield.disp16 = 1; | |
9408 | else | |
9409 | { | |
9410 | bigdisp.bitfield.disp32 = 1; | |
9411 | bigdisp.bitfield.disp32s = 1; | |
9412 | } | |
9413 | } | |
9414 | else | |
e05278af JB |
9415 | { |
9416 | if (!override) | |
9417 | override = (i.suffix == (flag_code != CODE_16BIT | |
9418 | ? WORD_MNEM_SUFFIX | |
9419 | : LONG_MNEM_SUFFIX)); | |
40fb9820 L |
9420 | bigdisp.bitfield.disp32 = 1; |
9421 | if ((flag_code == CODE_16BIT) ^ override) | |
9422 | { | |
9423 | bigdisp.bitfield.disp32 = 0; | |
9424 | bigdisp.bitfield.disp16 = 1; | |
9425 | } | |
e05278af | 9426 | } |
e05278af | 9427 | } |
c6fb90c8 L |
9428 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
9429 | bigdisp); | |
252b5132 RH |
9430 | |
9431 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 9432 | i.op[this_operand].disps = exp; |
252b5132 RH |
9433 | i.disp_operands++; |
9434 | save_input_line_pointer = input_line_pointer; | |
9435 | input_line_pointer = disp_start; | |
9436 | END_STRING_AND_SAVE (disp_end); | |
9437 | ||
9438 | #ifndef GCC_ASM_O_HACK | |
9439 | #define GCC_ASM_O_HACK 0 | |
9440 | #endif | |
9441 | #if GCC_ASM_O_HACK | |
9442 | END_STRING_AND_SAVE (disp_end + 1); | |
40fb9820 | 9443 | if (i.types[this_operand].bitfield.baseIndex |
24eab124 | 9444 | && displacement_string_end[-1] == '+') |
252b5132 RH |
9445 | { |
9446 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
9447 | constraint within gcc asm statements. |
9448 | For instance: | |
9449 | ||
9450 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
9451 | __asm__ __volatile__ ( \ | |
9452 | "movw %w2,%0\n\t" \ | |
9453 | "movw %w1,2+%0\n\t" \ | |
9454 | "rorl $16,%1\n\t" \ | |
9455 | "movb %b1,4+%0\n\t" \ | |
9456 | "movb %4,5+%0\n\t" \ | |
9457 | "movb $0,6+%0\n\t" \ | |
9458 | "movb %h1,7+%0\n\t" \ | |
9459 | "rorl $16,%1" \ | |
9460 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
9461 | ||
9462 | This works great except that the output assembler ends | |
9463 | up looking a bit weird if it turns out that there is | |
9464 | no offset. You end up producing code that looks like: | |
9465 | ||
9466 | #APP | |
9467 | movw $235,(%eax) | |
9468 | movw %dx,2+(%eax) | |
9469 | rorl $16,%edx | |
9470 | movb %dl,4+(%eax) | |
9471 | movb $137,5+(%eax) | |
9472 | movb $0,6+(%eax) | |
9473 | movb %dh,7+(%eax) | |
9474 | rorl $16,%edx | |
9475 | #NO_APP | |
9476 | ||
47926f60 | 9477 | So here we provide the missing zero. */ |
24eab124 AM |
9478 | |
9479 | *displacement_string_end = '0'; | |
252b5132 RH |
9480 | } |
9481 | #endif | |
d258b828 | 9482 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
9483 | if (gotfree_input_line) |
9484 | input_line_pointer = gotfree_input_line; | |
252b5132 | 9485 | |
24eab124 | 9486 | exp_seg = expression (exp); |
252b5132 | 9487 | |
636c26b0 AM |
9488 | SKIP_WHITESPACE (); |
9489 | if (*input_line_pointer) | |
9490 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
9491 | #if GCC_ASM_O_HACK | |
9492 | RESTORE_END_STRING (disp_end + 1); | |
9493 | #endif | |
636c26b0 | 9494 | input_line_pointer = save_input_line_pointer; |
636c26b0 | 9495 | if (gotfree_input_line) |
ee86248c JB |
9496 | { |
9497 | free (gotfree_input_line); | |
9498 | ||
9499 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
9500 | exp->X_op = O_illegal; | |
9501 | } | |
9502 | ||
9503 | ret = i386_finalize_displacement (exp_seg, exp, types, disp_start); | |
9504 | ||
9505 | RESTORE_END_STRING (disp_end); | |
9506 | ||
9507 | return ret; | |
9508 | } | |
9509 | ||
9510 | static int | |
9511 | i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
9512 | i386_operand_type types, const char *disp_start) | |
9513 | { | |
9514 | i386_operand_type bigdisp; | |
9515 | int ret = 1; | |
636c26b0 | 9516 | |
24eab124 AM |
9517 | /* We do this to make sure that the section symbol is in |
9518 | the symbol table. We will ultimately change the relocation | |
47926f60 | 9519 | to be relative to the beginning of the section. */ |
1ae12ab7 | 9520 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
d6ab8113 JB |
9521 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
9522 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) | |
24eab124 | 9523 | { |
636c26b0 | 9524 | if (exp->X_op != O_symbol) |
3992d3b7 | 9525 | goto inv_disp; |
636c26b0 | 9526 | |
e5cb08ac | 9527 | if (S_IS_LOCAL (exp->X_add_symbol) |
c64efb4b L |
9528 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section |
9529 | && S_GET_SEGMENT (exp->X_add_symbol) != expr_section) | |
24eab124 | 9530 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); |
24eab124 AM |
9531 | exp->X_op = O_subtract; |
9532 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 | 9533 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
29b0f896 | 9534 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
d6ab8113 JB |
9535 | else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
9536 | i.reloc[this_operand] = BFD_RELOC_64; | |
23df1078 | 9537 | else |
29b0f896 | 9538 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 9539 | } |
252b5132 | 9540 | |
3992d3b7 AM |
9541 | else if (exp->X_op == O_absent |
9542 | || exp->X_op == O_illegal | |
ee86248c | 9543 | || exp->X_op == O_big) |
2daf4fd8 | 9544 | { |
3992d3b7 AM |
9545 | inv_disp: |
9546 | as_bad (_("missing or invalid displacement expression `%s'"), | |
2daf4fd8 | 9547 | disp_start); |
3992d3b7 | 9548 | ret = 0; |
2daf4fd8 AM |
9549 | } |
9550 | ||
0e1147d9 L |
9551 | else if (flag_code == CODE_64BIT |
9552 | && !i.prefix[ADDR_PREFIX] | |
9553 | && exp->X_op == O_constant) | |
9554 | { | |
9555 | /* Since displacement is signed extended to 64bit, don't allow | |
9556 | disp32 and turn off disp32s if they are out of range. */ | |
9557 | i.types[this_operand].bitfield.disp32 = 0; | |
9558 | if (!fits_in_signed_long (exp->X_add_number)) | |
9559 | { | |
9560 | i.types[this_operand].bitfield.disp32s = 0; | |
9561 | if (i.types[this_operand].bitfield.baseindex) | |
9562 | { | |
9563 | as_bad (_("0x%lx out range of signed 32bit displacement"), | |
9564 | (long) exp->X_add_number); | |
9565 | ret = 0; | |
9566 | } | |
9567 | } | |
9568 | } | |
9569 | ||
4c63da97 | 9570 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
3992d3b7 AM |
9571 | else if (exp->X_op != O_constant |
9572 | && OUTPUT_FLAVOR == bfd_target_aout_flavour | |
9573 | && exp_seg != absolute_section | |
9574 | && exp_seg != text_section | |
9575 | && exp_seg != data_section | |
9576 | && exp_seg != bss_section | |
9577 | && exp_seg != undefined_section | |
9578 | && !bfd_is_com_section (exp_seg)) | |
24eab124 | 9579 | { |
d0b47220 | 9580 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
3992d3b7 | 9581 | ret = 0; |
24eab124 | 9582 | } |
252b5132 | 9583 | #endif |
3956db08 | 9584 | |
40fb9820 L |
9585 | /* Check if this is a displacement only operand. */ |
9586 | bigdisp = i.types[this_operand]; | |
9587 | bigdisp.bitfield.disp8 = 0; | |
9588 | bigdisp.bitfield.disp16 = 0; | |
9589 | bigdisp.bitfield.disp32 = 0; | |
9590 | bigdisp.bitfield.disp32s = 0; | |
9591 | bigdisp.bitfield.disp64 = 0; | |
0dfbf9d7 | 9592 | if (operand_type_all_zero (&bigdisp)) |
c6fb90c8 L |
9593 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
9594 | types); | |
3956db08 | 9595 | |
3992d3b7 | 9596 | return ret; |
252b5132 RH |
9597 | } |
9598 | ||
2abc2bec JB |
9599 | /* Return the active addressing mode, taking address override and |
9600 | registers forming the address into consideration. Update the | |
9601 | address override prefix if necessary. */ | |
47926f60 | 9602 | |
2abc2bec JB |
9603 | static enum flag_code |
9604 | i386_addressing_mode (void) | |
252b5132 | 9605 | { |
be05d201 L |
9606 | enum flag_code addr_mode; |
9607 | ||
9608 | if (i.prefix[ADDR_PREFIX]) | |
9609 | addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT; | |
9610 | else | |
9611 | { | |
9612 | addr_mode = flag_code; | |
9613 | ||
24eab124 | 9614 | #if INFER_ADDR_PREFIX |
be05d201 L |
9615 | if (i.mem_operands == 0) |
9616 | { | |
9617 | /* Infer address prefix from the first memory operand. */ | |
9618 | const reg_entry *addr_reg = i.base_reg; | |
9619 | ||
9620 | if (addr_reg == NULL) | |
9621 | addr_reg = i.index_reg; | |
eecb386c | 9622 | |
be05d201 L |
9623 | if (addr_reg) |
9624 | { | |
e968fc9b | 9625 | if (addr_reg->reg_type.bitfield.dword) |
be05d201 L |
9626 | addr_mode = CODE_32BIT; |
9627 | else if (flag_code != CODE_64BIT | |
dc821c5f | 9628 | && addr_reg->reg_type.bitfield.word) |
be05d201 L |
9629 | addr_mode = CODE_16BIT; |
9630 | ||
9631 | if (addr_mode != flag_code) | |
9632 | { | |
9633 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
9634 | i.prefixes += 1; | |
9635 | /* Change the size of any displacement too. At most one | |
9636 | of Disp16 or Disp32 is set. | |
9637 | FIXME. There doesn't seem to be any real need for | |
9638 | separate Disp16 and Disp32 flags. The same goes for | |
9639 | Imm16 and Imm32. Removing them would probably clean | |
9640 | up the code quite a lot. */ | |
9641 | if (flag_code != CODE_64BIT | |
9642 | && (i.types[this_operand].bitfield.disp16 | |
9643 | || i.types[this_operand].bitfield.disp32)) | |
9644 | i.types[this_operand] | |
9645 | = operand_type_xor (i.types[this_operand], disp16_32); | |
9646 | } | |
9647 | } | |
9648 | } | |
24eab124 | 9649 | #endif |
be05d201 L |
9650 | } |
9651 | ||
2abc2bec JB |
9652 | return addr_mode; |
9653 | } | |
9654 | ||
9655 | /* Make sure the memory operand we've been dealt is valid. | |
9656 | Return 1 on success, 0 on a failure. */ | |
9657 | ||
9658 | static int | |
9659 | i386_index_check (const char *operand_string) | |
9660 | { | |
9661 | const char *kind = "base/index"; | |
9662 | enum flag_code addr_mode = i386_addressing_mode (); | |
9663 | ||
fc0763e6 JB |
9664 | if (current_templates->start->opcode_modifier.isstring |
9665 | && !current_templates->start->opcode_modifier.immext | |
9666 | && (current_templates->end[-1].opcode_modifier.isstring | |
9667 | || i.mem_operands)) | |
9668 | { | |
9669 | /* Memory operands of string insns are special in that they only allow | |
9670 | a single register (rDI, rSI, or rBX) as their memory address. */ | |
be05d201 L |
9671 | const reg_entry *expected_reg; |
9672 | static const char *di_si[][2] = | |
9673 | { | |
9674 | { "esi", "edi" }, | |
9675 | { "si", "di" }, | |
9676 | { "rsi", "rdi" } | |
9677 | }; | |
9678 | static const char *bx[] = { "ebx", "bx", "rbx" }; | |
fc0763e6 JB |
9679 | |
9680 | kind = "string address"; | |
9681 | ||
8325cc63 | 9682 | if (current_templates->start->opcode_modifier.repprefixok) |
fc0763e6 JB |
9683 | { |
9684 | i386_operand_type type = current_templates->end[-1].operand_types[0]; | |
9685 | ||
9686 | if (!type.bitfield.baseindex | |
9687 | || ((!i.mem_operands != !intel_syntax) | |
9688 | && current_templates->end[-1].operand_types[1] | |
9689 | .bitfield.baseindex)) | |
9690 | type = current_templates->end[-1].operand_types[1]; | |
be05d201 L |
9691 | expected_reg = hash_find (reg_hash, |
9692 | di_si[addr_mode][type.bitfield.esseg]); | |
9693 | ||
fc0763e6 JB |
9694 | } |
9695 | else | |
be05d201 | 9696 | expected_reg = hash_find (reg_hash, bx[addr_mode]); |
fc0763e6 | 9697 | |
be05d201 L |
9698 | if (i.base_reg != expected_reg |
9699 | || i.index_reg | |
fc0763e6 | 9700 | || operand_type_check (i.types[this_operand], disp)) |
fc0763e6 | 9701 | { |
be05d201 L |
9702 | /* The second memory operand must have the same size as |
9703 | the first one. */ | |
9704 | if (i.mem_operands | |
9705 | && i.base_reg | |
9706 | && !((addr_mode == CODE_64BIT | |
dc821c5f | 9707 | && i.base_reg->reg_type.bitfield.qword) |
be05d201 | 9708 | || (addr_mode == CODE_32BIT |
dc821c5f JB |
9709 | ? i.base_reg->reg_type.bitfield.dword |
9710 | : i.base_reg->reg_type.bitfield.word))) | |
be05d201 L |
9711 | goto bad_address; |
9712 | ||
fc0763e6 JB |
9713 | as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"), |
9714 | operand_string, | |
9715 | intel_syntax ? '[' : '(', | |
9716 | register_prefix, | |
be05d201 | 9717 | expected_reg->reg_name, |
fc0763e6 | 9718 | intel_syntax ? ']' : ')'); |
be05d201 | 9719 | return 1; |
fc0763e6 | 9720 | } |
be05d201 L |
9721 | else |
9722 | return 1; | |
9723 | ||
9724 | bad_address: | |
9725 | as_bad (_("`%s' is not a valid %s expression"), | |
9726 | operand_string, kind); | |
9727 | return 0; | |
3e73aa7c JH |
9728 | } |
9729 | else | |
9730 | { | |
be05d201 L |
9731 | if (addr_mode != CODE_16BIT) |
9732 | { | |
9733 | /* 32-bit/64-bit checks. */ | |
9734 | if ((i.base_reg | |
e968fc9b JB |
9735 | && ((addr_mode == CODE_64BIT |
9736 | ? !i.base_reg->reg_type.bitfield.qword | |
9737 | : !i.base_reg->reg_type.bitfield.dword) | |
9738 | || (i.index_reg && i.base_reg->reg_num == RegIP) | |
9739 | || i.base_reg->reg_num == RegIZ)) | |
be05d201 | 9740 | || (i.index_reg |
1b54b8d7 JB |
9741 | && !i.index_reg->reg_type.bitfield.xmmword |
9742 | && !i.index_reg->reg_type.bitfield.ymmword | |
9743 | && !i.index_reg->reg_type.bitfield.zmmword | |
be05d201 | 9744 | && ((addr_mode == CODE_64BIT |
e968fc9b JB |
9745 | ? !i.index_reg->reg_type.bitfield.qword |
9746 | : !i.index_reg->reg_type.bitfield.dword) | |
be05d201 L |
9747 | || !i.index_reg->reg_type.bitfield.baseindex))) |
9748 | goto bad_address; | |
8178be5b JB |
9749 | |
9750 | /* bndmk, bndldx, and bndstx have special restrictions. */ | |
9751 | if (current_templates->start->base_opcode == 0xf30f1b | |
9752 | || (current_templates->start->base_opcode & ~1) == 0x0f1a) | |
9753 | { | |
9754 | /* They cannot use RIP-relative addressing. */ | |
e968fc9b | 9755 | if (i.base_reg && i.base_reg->reg_num == RegIP) |
8178be5b JB |
9756 | { |
9757 | as_bad (_("`%s' cannot be used here"), operand_string); | |
9758 | return 0; | |
9759 | } | |
9760 | ||
9761 | /* bndldx and bndstx ignore their scale factor. */ | |
9762 | if (current_templates->start->base_opcode != 0xf30f1b | |
9763 | && i.log2_scale_factor) | |
9764 | as_warn (_("register scaling is being ignored here")); | |
9765 | } | |
be05d201 L |
9766 | } |
9767 | else | |
3e73aa7c | 9768 | { |
be05d201 | 9769 | /* 16-bit checks. */ |
3e73aa7c | 9770 | if ((i.base_reg |
dc821c5f | 9771 | && (!i.base_reg->reg_type.bitfield.word |
40fb9820 | 9772 | || !i.base_reg->reg_type.bitfield.baseindex)) |
3e73aa7c | 9773 | || (i.index_reg |
dc821c5f | 9774 | && (!i.index_reg->reg_type.bitfield.word |
40fb9820 | 9775 | || !i.index_reg->reg_type.bitfield.baseindex |
29b0f896 AM |
9776 | || !(i.base_reg |
9777 | && i.base_reg->reg_num < 6 | |
9778 | && i.index_reg->reg_num >= 6 | |
9779 | && i.log2_scale_factor == 0)))) | |
be05d201 | 9780 | goto bad_address; |
3e73aa7c JH |
9781 | } |
9782 | } | |
be05d201 | 9783 | return 1; |
24eab124 | 9784 | } |
252b5132 | 9785 | |
43234a1e L |
9786 | /* Handle vector immediates. */ |
9787 | ||
9788 | static int | |
9789 | RC_SAE_immediate (const char *imm_start) | |
9790 | { | |
9791 | unsigned int match_found, j; | |
9792 | const char *pstr = imm_start; | |
9793 | expressionS *exp; | |
9794 | ||
9795 | if (*pstr != '{') | |
9796 | return 0; | |
9797 | ||
9798 | pstr++; | |
9799 | match_found = 0; | |
9800 | for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++) | |
9801 | { | |
9802 | if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len)) | |
9803 | { | |
9804 | if (!i.rounding) | |
9805 | { | |
9806 | rc_op.type = RC_NamesTable[j].type; | |
9807 | rc_op.operand = this_operand; | |
9808 | i.rounding = &rc_op; | |
9809 | } | |
9810 | else | |
9811 | { | |
9812 | as_bad (_("duplicated `%s'"), imm_start); | |
9813 | return 0; | |
9814 | } | |
9815 | pstr += RC_NamesTable[j].len; | |
9816 | match_found = 1; | |
9817 | break; | |
9818 | } | |
9819 | } | |
9820 | if (!match_found) | |
9821 | return 0; | |
9822 | ||
9823 | if (*pstr++ != '}') | |
9824 | { | |
9825 | as_bad (_("Missing '}': '%s'"), imm_start); | |
9826 | return 0; | |
9827 | } | |
9828 | /* RC/SAE immediate string should contain nothing more. */; | |
9829 | if (*pstr != 0) | |
9830 | { | |
9831 | as_bad (_("Junk after '}': '%s'"), imm_start); | |
9832 | return 0; | |
9833 | } | |
9834 | ||
9835 | exp = &im_expressions[i.imm_operands++]; | |
9836 | i.op[this_operand].imms = exp; | |
9837 | ||
9838 | exp->X_op = O_constant; | |
9839 | exp->X_add_number = 0; | |
9840 | exp->X_add_symbol = (symbolS *) 0; | |
9841 | exp->X_op_symbol = (symbolS *) 0; | |
9842 | ||
9843 | i.types[this_operand].bitfield.imm8 = 1; | |
9844 | return 1; | |
9845 | } | |
9846 | ||
8325cc63 JB |
9847 | /* Only string instructions can have a second memory operand, so |
9848 | reduce current_templates to just those if it contains any. */ | |
9849 | static int | |
9850 | maybe_adjust_templates (void) | |
9851 | { | |
9852 | const insn_template *t; | |
9853 | ||
9854 | gas_assert (i.mem_operands == 1); | |
9855 | ||
9856 | for (t = current_templates->start; t < current_templates->end; ++t) | |
9857 | if (t->opcode_modifier.isstring) | |
9858 | break; | |
9859 | ||
9860 | if (t < current_templates->end) | |
9861 | { | |
9862 | static templates aux_templates; | |
9863 | bfd_boolean recheck; | |
9864 | ||
9865 | aux_templates.start = t; | |
9866 | for (; t < current_templates->end; ++t) | |
9867 | if (!t->opcode_modifier.isstring) | |
9868 | break; | |
9869 | aux_templates.end = t; | |
9870 | ||
9871 | /* Determine whether to re-check the first memory operand. */ | |
9872 | recheck = (aux_templates.start != current_templates->start | |
9873 | || t != current_templates->end); | |
9874 | ||
9875 | current_templates = &aux_templates; | |
9876 | ||
9877 | if (recheck) | |
9878 | { | |
9879 | i.mem_operands = 0; | |
9880 | if (i.memop1_string != NULL | |
9881 | && i386_index_check (i.memop1_string) == 0) | |
9882 | return 0; | |
9883 | i.mem_operands = 1; | |
9884 | } | |
9885 | } | |
9886 | ||
9887 | return 1; | |
9888 | } | |
9889 | ||
fc0763e6 | 9890 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero |
47926f60 | 9891 | on error. */ |
252b5132 | 9892 | |
252b5132 | 9893 | static int |
a7619375 | 9894 | i386_att_operand (char *operand_string) |
252b5132 | 9895 | { |
af6bdddf AM |
9896 | const reg_entry *r; |
9897 | char *end_op; | |
24eab124 | 9898 | char *op_string = operand_string; |
252b5132 | 9899 | |
24eab124 | 9900 | if (is_space_char (*op_string)) |
252b5132 RH |
9901 | ++op_string; |
9902 | ||
24eab124 | 9903 | /* We check for an absolute prefix (differentiating, |
47926f60 | 9904 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
9905 | if (*op_string == ABSOLUTE_PREFIX) |
9906 | { | |
9907 | ++op_string; | |
9908 | if (is_space_char (*op_string)) | |
9909 | ++op_string; | |
40fb9820 | 9910 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 | 9911 | } |
252b5132 | 9912 | |
47926f60 | 9913 | /* Check if operand is a register. */ |
4d1bb795 | 9914 | if ((r = parse_register (op_string, &end_op)) != NULL) |
24eab124 | 9915 | { |
40fb9820 L |
9916 | i386_operand_type temp; |
9917 | ||
24eab124 AM |
9918 | /* Check for a segment override by searching for ':' after a |
9919 | segment register. */ | |
9920 | op_string = end_op; | |
9921 | if (is_space_char (*op_string)) | |
9922 | ++op_string; | |
40fb9820 L |
9923 | if (*op_string == ':' |
9924 | && (r->reg_type.bitfield.sreg2 | |
9925 | || r->reg_type.bitfield.sreg3)) | |
24eab124 AM |
9926 | { |
9927 | switch (r->reg_num) | |
9928 | { | |
9929 | case 0: | |
9930 | i.seg[i.mem_operands] = &es; | |
9931 | break; | |
9932 | case 1: | |
9933 | i.seg[i.mem_operands] = &cs; | |
9934 | break; | |
9935 | case 2: | |
9936 | i.seg[i.mem_operands] = &ss; | |
9937 | break; | |
9938 | case 3: | |
9939 | i.seg[i.mem_operands] = &ds; | |
9940 | break; | |
9941 | case 4: | |
9942 | i.seg[i.mem_operands] = &fs; | |
9943 | break; | |
9944 | case 5: | |
9945 | i.seg[i.mem_operands] = &gs; | |
9946 | break; | |
9947 | } | |
252b5132 | 9948 | |
24eab124 | 9949 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
9950 | ++op_string; |
9951 | if (is_space_char (*op_string)) | |
24eab124 | 9952 | ++op_string; |
252b5132 | 9953 | |
24eab124 AM |
9954 | if (!is_digit_char (*op_string) |
9955 | && !is_identifier_char (*op_string) | |
9956 | && *op_string != '(' | |
9957 | && *op_string != ABSOLUTE_PREFIX) | |
9958 | { | |
9959 | as_bad (_("bad memory operand `%s'"), op_string); | |
9960 | return 0; | |
9961 | } | |
47926f60 | 9962 | /* Handle case of %es:*foo. */ |
24eab124 AM |
9963 | if (*op_string == ABSOLUTE_PREFIX) |
9964 | { | |
9965 | ++op_string; | |
9966 | if (is_space_char (*op_string)) | |
9967 | ++op_string; | |
40fb9820 | 9968 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 AM |
9969 | } |
9970 | goto do_memory_reference; | |
9971 | } | |
43234a1e L |
9972 | |
9973 | /* Handle vector operations. */ | |
9974 | if (*op_string == '{') | |
9975 | { | |
9976 | op_string = check_VecOperations (op_string, NULL); | |
9977 | if (op_string == NULL) | |
9978 | return 0; | |
9979 | } | |
9980 | ||
24eab124 AM |
9981 | if (*op_string) |
9982 | { | |
d0b47220 | 9983 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
9984 | return 0; |
9985 | } | |
40fb9820 L |
9986 | temp = r->reg_type; |
9987 | temp.bitfield.baseindex = 0; | |
c6fb90c8 L |
9988 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
9989 | temp); | |
7d5e4556 | 9990 | i.types[this_operand].bitfield.unspecified = 0; |
520dc8e8 | 9991 | i.op[this_operand].regs = r; |
24eab124 AM |
9992 | i.reg_operands++; |
9993 | } | |
af6bdddf AM |
9994 | else if (*op_string == REGISTER_PREFIX) |
9995 | { | |
9996 | as_bad (_("bad register name `%s'"), op_string); | |
9997 | return 0; | |
9998 | } | |
24eab124 | 9999 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 10000 | { |
24eab124 | 10001 | ++op_string; |
40fb9820 | 10002 | if (i.types[this_operand].bitfield.jumpabsolute) |
24eab124 | 10003 | { |
d0b47220 | 10004 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
10005 | return 0; |
10006 | } | |
10007 | if (!i386_immediate (op_string)) | |
10008 | return 0; | |
10009 | } | |
43234a1e L |
10010 | else if (RC_SAE_immediate (operand_string)) |
10011 | { | |
10012 | /* If it is a RC or SAE immediate, do nothing. */ | |
10013 | ; | |
10014 | } | |
24eab124 AM |
10015 | else if (is_digit_char (*op_string) |
10016 | || is_identifier_char (*op_string) | |
d02603dc | 10017 | || *op_string == '"' |
e5cb08ac | 10018 | || *op_string == '(') |
24eab124 | 10019 | { |
47926f60 | 10020 | /* This is a memory reference of some sort. */ |
af6bdddf | 10021 | char *base_string; |
252b5132 | 10022 | |
47926f60 | 10023 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
10024 | char *displacement_string_start; |
10025 | char *displacement_string_end; | |
43234a1e | 10026 | char *vop_start; |
252b5132 | 10027 | |
24eab124 | 10028 | do_memory_reference: |
8325cc63 JB |
10029 | if (i.mem_operands == 1 && !maybe_adjust_templates ()) |
10030 | return 0; | |
24eab124 | 10031 | if ((i.mem_operands == 1 |
40fb9820 | 10032 | && !current_templates->start->opcode_modifier.isstring) |
24eab124 AM |
10033 | || i.mem_operands == 2) |
10034 | { | |
10035 | as_bad (_("too many memory references for `%s'"), | |
10036 | current_templates->start->name); | |
10037 | return 0; | |
10038 | } | |
252b5132 | 10039 | |
24eab124 AM |
10040 | /* Check for base index form. We detect the base index form by |
10041 | looking for an ')' at the end of the operand, searching | |
10042 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
10043 | after the '('. */ | |
af6bdddf | 10044 | base_string = op_string + strlen (op_string); |
c3332e24 | 10045 | |
43234a1e L |
10046 | /* Handle vector operations. */ |
10047 | vop_start = strchr (op_string, '{'); | |
10048 | if (vop_start && vop_start < base_string) | |
10049 | { | |
10050 | if (check_VecOperations (vop_start, base_string) == NULL) | |
10051 | return 0; | |
10052 | base_string = vop_start; | |
10053 | } | |
10054 | ||
af6bdddf AM |
10055 | --base_string; |
10056 | if (is_space_char (*base_string)) | |
10057 | --base_string; | |
252b5132 | 10058 | |
47926f60 | 10059 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
10060 | displacement_string_start = op_string; |
10061 | displacement_string_end = base_string + 1; | |
252b5132 | 10062 | |
24eab124 AM |
10063 | if (*base_string == ')') |
10064 | { | |
af6bdddf | 10065 | char *temp_string; |
24eab124 AM |
10066 | unsigned int parens_balanced = 1; |
10067 | /* We've already checked that the number of left & right ()'s are | |
47926f60 | 10068 | equal, so this loop will not be infinite. */ |
24eab124 AM |
10069 | do |
10070 | { | |
10071 | base_string--; | |
10072 | if (*base_string == ')') | |
10073 | parens_balanced++; | |
10074 | if (*base_string == '(') | |
10075 | parens_balanced--; | |
10076 | } | |
10077 | while (parens_balanced); | |
c3332e24 | 10078 | |
af6bdddf | 10079 | temp_string = base_string; |
c3332e24 | 10080 | |
24eab124 | 10081 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
10082 | ++base_string; |
10083 | if (is_space_char (*base_string)) | |
24eab124 | 10084 | ++base_string; |
252b5132 | 10085 | |
af6bdddf | 10086 | if (*base_string == ',' |
4eed87de AM |
10087 | || ((i.base_reg = parse_register (base_string, &end_op)) |
10088 | != NULL)) | |
252b5132 | 10089 | { |
af6bdddf | 10090 | displacement_string_end = temp_string; |
252b5132 | 10091 | |
40fb9820 | 10092 | i.types[this_operand].bitfield.baseindex = 1; |
252b5132 | 10093 | |
af6bdddf | 10094 | if (i.base_reg) |
24eab124 | 10095 | { |
24eab124 AM |
10096 | base_string = end_op; |
10097 | if (is_space_char (*base_string)) | |
10098 | ++base_string; | |
af6bdddf AM |
10099 | } |
10100 | ||
10101 | /* There may be an index reg or scale factor here. */ | |
10102 | if (*base_string == ',') | |
10103 | { | |
10104 | ++base_string; | |
10105 | if (is_space_char (*base_string)) | |
10106 | ++base_string; | |
10107 | ||
4eed87de AM |
10108 | if ((i.index_reg = parse_register (base_string, &end_op)) |
10109 | != NULL) | |
24eab124 | 10110 | { |
af6bdddf | 10111 | base_string = end_op; |
24eab124 AM |
10112 | if (is_space_char (*base_string)) |
10113 | ++base_string; | |
af6bdddf AM |
10114 | if (*base_string == ',') |
10115 | { | |
10116 | ++base_string; | |
10117 | if (is_space_char (*base_string)) | |
10118 | ++base_string; | |
10119 | } | |
e5cb08ac | 10120 | else if (*base_string != ')') |
af6bdddf | 10121 | { |
4eed87de AM |
10122 | as_bad (_("expecting `,' or `)' " |
10123 | "after index register in `%s'"), | |
af6bdddf AM |
10124 | operand_string); |
10125 | return 0; | |
10126 | } | |
24eab124 | 10127 | } |
af6bdddf | 10128 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 10129 | { |
f76bf5e0 L |
10130 | end_op = strchr (base_string, ','); |
10131 | if (end_op) | |
10132 | *end_op = '\0'; | |
af6bdddf | 10133 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
10134 | return 0; |
10135 | } | |
252b5132 | 10136 | |
47926f60 | 10137 | /* Check for scale factor. */ |
551c1ca1 | 10138 | if (*base_string != ')') |
af6bdddf | 10139 | { |
551c1ca1 AM |
10140 | char *end_scale = i386_scale (base_string); |
10141 | ||
10142 | if (!end_scale) | |
af6bdddf | 10143 | return 0; |
24eab124 | 10144 | |
551c1ca1 | 10145 | base_string = end_scale; |
af6bdddf AM |
10146 | if (is_space_char (*base_string)) |
10147 | ++base_string; | |
10148 | if (*base_string != ')') | |
10149 | { | |
4eed87de AM |
10150 | as_bad (_("expecting `)' " |
10151 | "after scale factor in `%s'"), | |
af6bdddf AM |
10152 | operand_string); |
10153 | return 0; | |
10154 | } | |
10155 | } | |
10156 | else if (!i.index_reg) | |
24eab124 | 10157 | { |
4eed87de AM |
10158 | as_bad (_("expecting index register or scale factor " |
10159 | "after `,'; got '%c'"), | |
af6bdddf | 10160 | *base_string); |
24eab124 AM |
10161 | return 0; |
10162 | } | |
10163 | } | |
af6bdddf | 10164 | else if (*base_string != ')') |
24eab124 | 10165 | { |
4eed87de AM |
10166 | as_bad (_("expecting `,' or `)' " |
10167 | "after base register in `%s'"), | |
af6bdddf | 10168 | operand_string); |
24eab124 AM |
10169 | return 0; |
10170 | } | |
c3332e24 | 10171 | } |
af6bdddf | 10172 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 10173 | { |
f76bf5e0 L |
10174 | end_op = strchr (base_string, ','); |
10175 | if (end_op) | |
10176 | *end_op = '\0'; | |
af6bdddf | 10177 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 10178 | return 0; |
c3332e24 | 10179 | } |
24eab124 AM |
10180 | } |
10181 | ||
10182 | /* If there's an expression beginning the operand, parse it, | |
10183 | assuming displacement_string_start and | |
10184 | displacement_string_end are meaningful. */ | |
10185 | if (displacement_string_start != displacement_string_end) | |
10186 | { | |
10187 | if (!i386_displacement (displacement_string_start, | |
10188 | displacement_string_end)) | |
10189 | return 0; | |
10190 | } | |
10191 | ||
10192 | /* Special case for (%dx) while doing input/output op. */ | |
10193 | if (i.base_reg | |
2fb5be8d | 10194 | && i.base_reg->reg_type.bitfield.inoutportreg |
24eab124 AM |
10195 | && i.index_reg == 0 |
10196 | && i.log2_scale_factor == 0 | |
10197 | && i.seg[i.mem_operands] == 0 | |
40fb9820 | 10198 | && !operand_type_check (i.types[this_operand], disp)) |
24eab124 | 10199 | { |
2fb5be8d | 10200 | i.types[this_operand] = i.base_reg->reg_type; |
24eab124 AM |
10201 | return 1; |
10202 | } | |
10203 | ||
eecb386c AM |
10204 | if (i386_index_check (operand_string) == 0) |
10205 | return 0; | |
c48dadc9 | 10206 | i.flags[this_operand] |= Operand_Mem; |
8325cc63 JB |
10207 | if (i.mem_operands == 0) |
10208 | i.memop1_string = xstrdup (operand_string); | |
24eab124 AM |
10209 | i.mem_operands++; |
10210 | } | |
10211 | else | |
ce8a8b2f AM |
10212 | { |
10213 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
10214 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
10215 | output_invalid (*op_string), | |
10216 | this_operand + 1, | |
10217 | op_string); | |
10218 | return 0; | |
10219 | } | |
47926f60 | 10220 | return 1; /* Normal return. */ |
252b5132 RH |
10221 | } |
10222 | \f | |
fa94de6b RM |
10223 | /* Calculate the maximum variable size (i.e., excluding fr_fix) |
10224 | that an rs_machine_dependent frag may reach. */ | |
10225 | ||
10226 | unsigned int | |
10227 | i386_frag_max_var (fragS *frag) | |
10228 | { | |
10229 | /* The only relaxable frags are for jumps. | |
10230 | Unconditional jumps can grow by 4 bytes and others by 5 bytes. */ | |
10231 | gas_assert (frag->fr_type == rs_machine_dependent); | |
10232 | return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5; | |
10233 | } | |
10234 | ||
b084df0b L |
10235 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
10236 | static int | |
8dcea932 | 10237 | elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var) |
b084df0b L |
10238 | { |
10239 | /* STT_GNU_IFUNC symbol must go through PLT. */ | |
10240 | if ((symbol_get_bfdsym (fr_symbol)->flags | |
10241 | & BSF_GNU_INDIRECT_FUNCTION) != 0) | |
10242 | return 0; | |
10243 | ||
10244 | if (!S_IS_EXTERNAL (fr_symbol)) | |
10245 | /* Symbol may be weak or local. */ | |
10246 | return !S_IS_WEAK (fr_symbol); | |
10247 | ||
8dcea932 L |
10248 | /* Global symbols with non-default visibility can't be preempted. */ |
10249 | if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT) | |
10250 | return 1; | |
10251 | ||
10252 | if (fr_var != NO_RELOC) | |
10253 | switch ((enum bfd_reloc_code_real) fr_var) | |
10254 | { | |
10255 | case BFD_RELOC_386_PLT32: | |
10256 | case BFD_RELOC_X86_64_PLT32: | |
33eaf5de | 10257 | /* Symbol with PLT relocation may be preempted. */ |
8dcea932 L |
10258 | return 0; |
10259 | default: | |
10260 | abort (); | |
10261 | } | |
10262 | ||
b084df0b L |
10263 | /* Global symbols with default visibility in a shared library may be |
10264 | preempted by another definition. */ | |
8dcea932 | 10265 | return !shared; |
b084df0b L |
10266 | } |
10267 | #endif | |
10268 | ||
ee7fcc42 AM |
10269 | /* md_estimate_size_before_relax() |
10270 | ||
10271 | Called just before relax() for rs_machine_dependent frags. The x86 | |
10272 | assembler uses these frags to handle variable size jump | |
10273 | instructions. | |
10274 | ||
10275 | Any symbol that is now undefined will not become defined. | |
10276 | Return the correct fr_subtype in the frag. | |
10277 | Return the initial "guess for variable size of frag" to caller. | |
10278 | The guess is actually the growth beyond the fixed part. Whatever | |
10279 | we do to grow the fixed or variable part contributes to our | |
10280 | returned value. */ | |
10281 | ||
252b5132 | 10282 | int |
7016a5d5 | 10283 | md_estimate_size_before_relax (fragS *fragP, segT segment) |
252b5132 | 10284 | { |
252b5132 | 10285 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
10286 | check for un-relaxable symbols. On an ELF system, we can't relax |
10287 | an externally visible symbol, because it may be overridden by a | |
10288 | shared library. */ | |
10289 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 10290 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 10291 | || (IS_ELF |
8dcea932 L |
10292 | && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol, |
10293 | fragP->fr_var)) | |
fbeb56a4 DK |
10294 | #endif |
10295 | #if defined (OBJ_COFF) && defined (TE_PE) | |
7ab9ffdd | 10296 | || (OUTPUT_FLAVOR == bfd_target_coff_flavour |
fbeb56a4 | 10297 | && S_IS_WEAK (fragP->fr_symbol)) |
b98ef147 AM |
10298 | #endif |
10299 | ) | |
252b5132 | 10300 | { |
b98ef147 AM |
10301 | /* Symbol is undefined in this segment, or we need to keep a |
10302 | reloc so that weak symbols can be overridden. */ | |
10303 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f86103b7 | 10304 | enum bfd_reloc_code_real reloc_type; |
ee7fcc42 AM |
10305 | unsigned char *opcode; |
10306 | int old_fr_fix; | |
f6af82bd | 10307 | |
ee7fcc42 | 10308 | if (fragP->fr_var != NO_RELOC) |
1e9cc1c2 | 10309 | reloc_type = (enum bfd_reloc_code_real) fragP->fr_var; |
b98ef147 | 10310 | else if (size == 2) |
f6af82bd | 10311 | reloc_type = BFD_RELOC_16_PCREL; |
bd7ab16b L |
10312 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
10313 | else if (need_plt32_p (fragP->fr_symbol)) | |
10314 | reloc_type = BFD_RELOC_X86_64_PLT32; | |
10315 | #endif | |
f6af82bd AM |
10316 | else |
10317 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 10318 | |
ee7fcc42 AM |
10319 | old_fr_fix = fragP->fr_fix; |
10320 | opcode = (unsigned char *) fragP->fr_opcode; | |
10321 | ||
fddf5b5b | 10322 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 10323 | { |
fddf5b5b AM |
10324 | case UNCOND_JUMP: |
10325 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 10326 | opcode[0] = 0xe9; |
252b5132 | 10327 | fragP->fr_fix += size; |
062cd5e7 AS |
10328 | fix_new (fragP, old_fr_fix, size, |
10329 | fragP->fr_symbol, | |
10330 | fragP->fr_offset, 1, | |
10331 | reloc_type); | |
252b5132 RH |
10332 | break; |
10333 | ||
fddf5b5b | 10334 | case COND_JUMP86: |
412167cb AM |
10335 | if (size == 2 |
10336 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) | |
fddf5b5b AM |
10337 | { |
10338 | /* Negate the condition, and branch past an | |
10339 | unconditional jump. */ | |
10340 | opcode[0] ^= 1; | |
10341 | opcode[1] = 3; | |
10342 | /* Insert an unconditional jump. */ | |
10343 | opcode[2] = 0xe9; | |
10344 | /* We added two extra opcode bytes, and have a two byte | |
10345 | offset. */ | |
10346 | fragP->fr_fix += 2 + 2; | |
062cd5e7 AS |
10347 | fix_new (fragP, old_fr_fix + 2, 2, |
10348 | fragP->fr_symbol, | |
10349 | fragP->fr_offset, 1, | |
10350 | reloc_type); | |
fddf5b5b AM |
10351 | break; |
10352 | } | |
10353 | /* Fall through. */ | |
10354 | ||
10355 | case COND_JUMP: | |
412167cb AM |
10356 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
10357 | { | |
3e02c1cc AM |
10358 | fixS *fixP; |
10359 | ||
412167cb | 10360 | fragP->fr_fix += 1; |
3e02c1cc AM |
10361 | fixP = fix_new (fragP, old_fr_fix, 1, |
10362 | fragP->fr_symbol, | |
10363 | fragP->fr_offset, 1, | |
10364 | BFD_RELOC_8_PCREL); | |
10365 | fixP->fx_signed = 1; | |
412167cb AM |
10366 | break; |
10367 | } | |
93c2a809 | 10368 | |
24eab124 | 10369 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 10370 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 10371 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 10372 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
10373 | /* We've added an opcode byte. */ |
10374 | fragP->fr_fix += 1 + size; | |
062cd5e7 AS |
10375 | fix_new (fragP, old_fr_fix + 1, size, |
10376 | fragP->fr_symbol, | |
10377 | fragP->fr_offset, 1, | |
10378 | reloc_type); | |
252b5132 | 10379 | break; |
fddf5b5b AM |
10380 | |
10381 | default: | |
10382 | BAD_CASE (fragP->fr_subtype); | |
10383 | break; | |
252b5132 RH |
10384 | } |
10385 | frag_wane (fragP); | |
ee7fcc42 | 10386 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 10387 | } |
93c2a809 | 10388 | |
93c2a809 AM |
10389 | /* Guess size depending on current relax state. Initially the relax |
10390 | state will correspond to a short jump and we return 1, because | |
10391 | the variable part of the frag (the branch offset) is one byte | |
10392 | long. However, we can relax a section more than once and in that | |
10393 | case we must either set fr_subtype back to the unrelaxed state, | |
10394 | or return the value for the appropriate branch. */ | |
10395 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
10396 | } |
10397 | ||
47926f60 KH |
10398 | /* Called after relax() is finished. |
10399 | ||
10400 | In: Address of frag. | |
10401 | fr_type == rs_machine_dependent. | |
10402 | fr_subtype is what the address relaxed to. | |
10403 | ||
10404 | Out: Any fixSs and constants are set up. | |
10405 | Caller will turn frag into a ".space 0". */ | |
10406 | ||
252b5132 | 10407 | void |
7016a5d5 TG |
10408 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, |
10409 | fragS *fragP) | |
252b5132 | 10410 | { |
29b0f896 | 10411 | unsigned char *opcode; |
252b5132 | 10412 | unsigned char *where_to_put_displacement = NULL; |
847f7ad4 AM |
10413 | offsetT target_address; |
10414 | offsetT opcode_address; | |
252b5132 | 10415 | unsigned int extension = 0; |
847f7ad4 | 10416 | offsetT displacement_from_opcode_start; |
252b5132 RH |
10417 | |
10418 | opcode = (unsigned char *) fragP->fr_opcode; | |
10419 | ||
47926f60 | 10420 | /* Address we want to reach in file space. */ |
252b5132 | 10421 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 10422 | |
47926f60 | 10423 | /* Address opcode resides at in file space. */ |
252b5132 RH |
10424 | opcode_address = fragP->fr_address + fragP->fr_fix; |
10425 | ||
47926f60 | 10426 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
10427 | displacement_from_opcode_start = target_address - opcode_address; |
10428 | ||
fddf5b5b | 10429 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 10430 | { |
47926f60 KH |
10431 | /* Don't have to change opcode. */ |
10432 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 10433 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
10434 | } |
10435 | else | |
10436 | { | |
10437 | if (no_cond_jump_promotion | |
10438 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4eed87de AM |
10439 | as_warn_where (fragP->fr_file, fragP->fr_line, |
10440 | _("long jump required")); | |
252b5132 | 10441 | |
fddf5b5b AM |
10442 | switch (fragP->fr_subtype) |
10443 | { | |
10444 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
10445 | extension = 4; /* 1 opcode + 4 displacement */ | |
10446 | opcode[0] = 0xe9; | |
10447 | where_to_put_displacement = &opcode[1]; | |
10448 | break; | |
252b5132 | 10449 | |
fddf5b5b AM |
10450 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
10451 | extension = 2; /* 1 opcode + 2 displacement */ | |
10452 | opcode[0] = 0xe9; | |
10453 | where_to_put_displacement = &opcode[1]; | |
10454 | break; | |
252b5132 | 10455 | |
fddf5b5b AM |
10456 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
10457 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
10458 | extension = 5; /* 2 opcode + 4 displacement */ | |
10459 | opcode[1] = opcode[0] + 0x10; | |
10460 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
10461 | where_to_put_displacement = &opcode[2]; | |
10462 | break; | |
252b5132 | 10463 | |
fddf5b5b AM |
10464 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
10465 | extension = 3; /* 2 opcode + 2 displacement */ | |
10466 | opcode[1] = opcode[0] + 0x10; | |
10467 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
10468 | where_to_put_displacement = &opcode[2]; | |
10469 | break; | |
252b5132 | 10470 | |
fddf5b5b AM |
10471 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
10472 | extension = 4; | |
10473 | opcode[0] ^= 1; | |
10474 | opcode[1] = 3; | |
10475 | opcode[2] = 0xe9; | |
10476 | where_to_put_displacement = &opcode[3]; | |
10477 | break; | |
10478 | ||
10479 | default: | |
10480 | BAD_CASE (fragP->fr_subtype); | |
10481 | break; | |
10482 | } | |
252b5132 | 10483 | } |
fddf5b5b | 10484 | |
7b81dfbb AJ |
10485 | /* If size if less then four we are sure that the operand fits, |
10486 | but if it's 4, then it could be that the displacement is larger | |
10487 | then -/+ 2GB. */ | |
10488 | if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 | |
10489 | && object_64bit | |
10490 | && ((addressT) (displacement_from_opcode_start - extension | |
4eed87de AM |
10491 | + ((addressT) 1 << 31)) |
10492 | > (((addressT) 2 << 31) - 1))) | |
7b81dfbb AJ |
10493 | { |
10494 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
10495 | _("jump target out of range")); | |
10496 | /* Make us emit 0. */ | |
10497 | displacement_from_opcode_start = extension; | |
10498 | } | |
47926f60 | 10499 | /* Now put displacement after opcode. */ |
252b5132 RH |
10500 | md_number_to_chars ((char *) where_to_put_displacement, |
10501 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 10502 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
10503 | fragP->fr_fix += extension; |
10504 | } | |
10505 | \f | |
7016a5d5 | 10506 | /* Apply a fixup (fixP) to segment data, once it has been determined |
252b5132 RH |
10507 | by our caller that we have all the info we need to fix it up. |
10508 | ||
7016a5d5 TG |
10509 | Parameter valP is the pointer to the value of the bits. |
10510 | ||
252b5132 RH |
10511 | On the 386, immediates, displacements, and data pointers are all in |
10512 | the same (little-endian) format, so we don't need to care about which | |
10513 | we are handling. */ | |
10514 | ||
94f592af | 10515 | void |
7016a5d5 | 10516 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 10517 | { |
94f592af | 10518 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
c6682705 | 10519 | valueT value = *valP; |
252b5132 | 10520 | |
f86103b7 | 10521 | #if !defined (TE_Mach) |
93382f6d AM |
10522 | if (fixP->fx_pcrel) |
10523 | { | |
10524 | switch (fixP->fx_r_type) | |
10525 | { | |
5865bb77 ILT |
10526 | default: |
10527 | break; | |
10528 | ||
d6ab8113 JB |
10529 | case BFD_RELOC_64: |
10530 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
10531 | break; | |
93382f6d | 10532 | case BFD_RELOC_32: |
ae8887b5 | 10533 | case BFD_RELOC_X86_64_32S: |
93382f6d AM |
10534 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
10535 | break; | |
10536 | case BFD_RELOC_16: | |
10537 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
10538 | break; | |
10539 | case BFD_RELOC_8: | |
10540 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
10541 | break; | |
10542 | } | |
10543 | } | |
252b5132 | 10544 | |
a161fe53 | 10545 | if (fixP->fx_addsy != NULL |
31312f95 | 10546 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
d6ab8113 | 10547 | || fixP->fx_r_type == BFD_RELOC_64_PCREL |
31312f95 | 10548 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
d258b828 | 10549 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) |
31312f95 | 10550 | && !use_rela_relocations) |
252b5132 | 10551 | { |
31312f95 AM |
10552 | /* This is a hack. There should be a better way to handle this. |
10553 | This covers for the fact that bfd_install_relocation will | |
10554 | subtract the current location (for partial_inplace, PC relative | |
10555 | relocations); see more below. */ | |
252b5132 | 10556 | #ifndef OBJ_AOUT |
718ddfc0 | 10557 | if (IS_ELF |
252b5132 RH |
10558 | #ifdef TE_PE |
10559 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
10560 | #endif | |
10561 | ) | |
10562 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
10563 | #endif | |
10564 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 10565 | if (IS_ELF) |
252b5132 | 10566 | { |
6539b54b | 10567 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
2f66722d | 10568 | |
6539b54b | 10569 | if ((sym_seg == seg |
2f66722d | 10570 | || (symbol_section_p (fixP->fx_addsy) |
6539b54b | 10571 | && sym_seg != absolute_section)) |
af65af87 | 10572 | && !generic_force_reloc (fixP)) |
2f66722d AM |
10573 | { |
10574 | /* Yes, we add the values in twice. This is because | |
6539b54b AM |
10575 | bfd_install_relocation subtracts them out again. I think |
10576 | bfd_install_relocation is broken, but I don't dare change | |
2f66722d AM |
10577 | it. FIXME. */ |
10578 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
10579 | } | |
252b5132 RH |
10580 | } |
10581 | #endif | |
10582 | #if defined (OBJ_COFF) && defined (TE_PE) | |
977cdf5a NC |
10583 | /* For some reason, the PE format does not store a |
10584 | section address offset for a PC relative symbol. */ | |
10585 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg | |
7be1c489 | 10586 | || S_IS_WEAK (fixP->fx_addsy)) |
252b5132 RH |
10587 | value += md_pcrel_from (fixP); |
10588 | #endif | |
10589 | } | |
fbeb56a4 | 10590 | #if defined (OBJ_COFF) && defined (TE_PE) |
f01c1a09 NC |
10591 | if (fixP->fx_addsy != NULL |
10592 | && S_IS_WEAK (fixP->fx_addsy) | |
10593 | /* PR 16858: Do not modify weak function references. */ | |
10594 | && ! fixP->fx_pcrel) | |
fbeb56a4 | 10595 | { |
296a8689 NC |
10596 | #if !defined (TE_PEP) |
10597 | /* For x86 PE weak function symbols are neither PC-relative | |
10598 | nor do they set S_IS_FUNCTION. So the only reliable way | |
10599 | to detect them is to check the flags of their containing | |
10600 | section. */ | |
10601 | if (S_GET_SEGMENT (fixP->fx_addsy) != NULL | |
10602 | && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE) | |
10603 | ; | |
10604 | else | |
10605 | #endif | |
fbeb56a4 DK |
10606 | value -= S_GET_VALUE (fixP->fx_addsy); |
10607 | } | |
10608 | #endif | |
252b5132 RH |
10609 | |
10610 | /* Fix a few things - the dynamic linker expects certain values here, | |
0234cb7c | 10611 | and we must not disappoint it. */ |
252b5132 | 10612 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 10613 | if (IS_ELF && fixP->fx_addsy) |
47926f60 KH |
10614 | switch (fixP->fx_r_type) |
10615 | { | |
10616 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 10617 | case BFD_RELOC_X86_64_PLT32: |
b9519cfe L |
10618 | /* Make the jump instruction point to the address of the operand. |
10619 | At runtime we merely add the offset to the actual PLT entry. | |
10620 | NB: Subtract the offset size only for jump instructions. */ | |
10621 | if (fixP->fx_pcrel) | |
10622 | value = -4; | |
47926f60 | 10623 | break; |
31312f95 | 10624 | |
13ae64f3 JJ |
10625 | case BFD_RELOC_386_TLS_GD: |
10626 | case BFD_RELOC_386_TLS_LDM: | |
13ae64f3 | 10627 | case BFD_RELOC_386_TLS_IE_32: |
37e55690 JJ |
10628 | case BFD_RELOC_386_TLS_IE: |
10629 | case BFD_RELOC_386_TLS_GOTIE: | |
67a4f2b7 | 10630 | case BFD_RELOC_386_TLS_GOTDESC: |
bffbf940 JJ |
10631 | case BFD_RELOC_X86_64_TLSGD: |
10632 | case BFD_RELOC_X86_64_TLSLD: | |
10633 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 | 10634 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
00f7efb6 JJ |
10635 | value = 0; /* Fully resolved at runtime. No addend. */ |
10636 | /* Fallthrough */ | |
10637 | case BFD_RELOC_386_TLS_LE: | |
10638 | case BFD_RELOC_386_TLS_LDO_32: | |
10639 | case BFD_RELOC_386_TLS_LE_32: | |
10640 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 10641 | case BFD_RELOC_X86_64_DTPOFF64: |
00f7efb6 | 10642 | case BFD_RELOC_X86_64_TPOFF32: |
d6ab8113 | 10643 | case BFD_RELOC_X86_64_TPOFF64: |
00f7efb6 JJ |
10644 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
10645 | break; | |
10646 | ||
67a4f2b7 AO |
10647 | case BFD_RELOC_386_TLS_DESC_CALL: |
10648 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
10649 | value = 0; /* Fully resolved at runtime. No addend. */ | |
10650 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
10651 | fixP->fx_done = 0; | |
10652 | return; | |
10653 | ||
47926f60 KH |
10654 | case BFD_RELOC_VTABLE_INHERIT: |
10655 | case BFD_RELOC_VTABLE_ENTRY: | |
10656 | fixP->fx_done = 0; | |
94f592af | 10657 | return; |
47926f60 KH |
10658 | |
10659 | default: | |
10660 | break; | |
10661 | } | |
10662 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
c6682705 | 10663 | *valP = value; |
f86103b7 | 10664 | #endif /* !defined (TE_Mach) */ |
3e73aa7c | 10665 | |
3e73aa7c | 10666 | /* Are we finished with this relocation now? */ |
c6682705 | 10667 | if (fixP->fx_addsy == NULL) |
3e73aa7c | 10668 | fixP->fx_done = 1; |
fbeb56a4 DK |
10669 | #if defined (OBJ_COFF) && defined (TE_PE) |
10670 | else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) | |
10671 | { | |
10672 | fixP->fx_done = 0; | |
10673 | /* Remember value for tc_gen_reloc. */ | |
10674 | fixP->fx_addnumber = value; | |
10675 | /* Clear out the frag for now. */ | |
10676 | value = 0; | |
10677 | } | |
10678 | #endif | |
3e73aa7c JH |
10679 | else if (use_rela_relocations) |
10680 | { | |
10681 | fixP->fx_no_overflow = 1; | |
062cd5e7 AS |
10682 | /* Remember value for tc_gen_reloc. */ |
10683 | fixP->fx_addnumber = value; | |
3e73aa7c JH |
10684 | value = 0; |
10685 | } | |
f86103b7 | 10686 | |
94f592af | 10687 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 10688 | } |
252b5132 | 10689 | \f |
6d4af3c2 | 10690 | const char * |
499ac353 | 10691 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 10692 | { |
499ac353 NC |
10693 | /* This outputs the LITTLENUMs in REVERSE order; |
10694 | in accord with the bigendian 386. */ | |
10695 | return ieee_md_atof (type, litP, sizeP, FALSE); | |
252b5132 RH |
10696 | } |
10697 | \f | |
2d545b82 | 10698 | static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; |
252b5132 | 10699 | |
252b5132 | 10700 | static char * |
e3bb37b5 | 10701 | output_invalid (int c) |
252b5132 | 10702 | { |
3882b010 | 10703 | if (ISPRINT (c)) |
f9f21a03 L |
10704 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
10705 | "'%c'", c); | |
252b5132 | 10706 | else |
f9f21a03 | 10707 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
2d545b82 | 10708 | "(0x%x)", (unsigned char) c); |
252b5132 RH |
10709 | return output_invalid_buf; |
10710 | } | |
10711 | ||
af6bdddf | 10712 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
10713 | |
10714 | static const reg_entry * | |
4d1bb795 | 10715 | parse_real_register (char *reg_string, char **end_op) |
252b5132 | 10716 | { |
af6bdddf AM |
10717 | char *s = reg_string; |
10718 | char *p; | |
252b5132 RH |
10719 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
10720 | const reg_entry *r; | |
10721 | ||
10722 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
10723 | if (*s == REGISTER_PREFIX) | |
10724 | ++s; | |
10725 | ||
10726 | if (is_space_char (*s)) | |
10727 | ++s; | |
10728 | ||
10729 | p = reg_name_given; | |
af6bdddf | 10730 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
10731 | { |
10732 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
10733 | return (const reg_entry *) NULL; |
10734 | s++; | |
252b5132 RH |
10735 | } |
10736 | ||
6588847e DN |
10737 | /* For naked regs, make sure that we are not dealing with an identifier. |
10738 | This prevents confusing an identifier like `eax_var' with register | |
10739 | `eax'. */ | |
10740 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
10741 | return (const reg_entry *) NULL; | |
10742 | ||
af6bdddf | 10743 | *end_op = s; |
252b5132 RH |
10744 | |
10745 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
10746 | ||
5f47d35b | 10747 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
47926f60 | 10748 | if (r == i386_regtab /* %st is first entry of table */) |
5f47d35b | 10749 | { |
0e0eea78 JB |
10750 | if (!cpu_arch_flags.bitfield.cpu8087 |
10751 | && !cpu_arch_flags.bitfield.cpu287 | |
10752 | && !cpu_arch_flags.bitfield.cpu387) | |
10753 | return (const reg_entry *) NULL; | |
10754 | ||
5f47d35b AM |
10755 | if (is_space_char (*s)) |
10756 | ++s; | |
10757 | if (*s == '(') | |
10758 | { | |
af6bdddf | 10759 | ++s; |
5f47d35b AM |
10760 | if (is_space_char (*s)) |
10761 | ++s; | |
10762 | if (*s >= '0' && *s <= '7') | |
10763 | { | |
db557034 | 10764 | int fpr = *s - '0'; |
af6bdddf | 10765 | ++s; |
5f47d35b AM |
10766 | if (is_space_char (*s)) |
10767 | ++s; | |
10768 | if (*s == ')') | |
10769 | { | |
10770 | *end_op = s + 1; | |
1e9cc1c2 | 10771 | r = (const reg_entry *) hash_find (reg_hash, "st(0)"); |
db557034 AM |
10772 | know (r); |
10773 | return r + fpr; | |
5f47d35b | 10774 | } |
5f47d35b | 10775 | } |
47926f60 | 10776 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
10777 | return (const reg_entry *) NULL; |
10778 | } | |
10779 | } | |
10780 | ||
a60de03c JB |
10781 | if (r == NULL || allow_pseudo_reg) |
10782 | return r; | |
10783 | ||
0dfbf9d7 | 10784 | if (operand_type_all_zero (&r->reg_type)) |
a60de03c JB |
10785 | return (const reg_entry *) NULL; |
10786 | ||
dc821c5f | 10787 | if ((r->reg_type.bitfield.dword |
192dc9c6 JB |
10788 | || r->reg_type.bitfield.sreg3 |
10789 | || r->reg_type.bitfield.control | |
10790 | || r->reg_type.bitfield.debug | |
10791 | || r->reg_type.bitfield.test) | |
10792 | && !cpu_arch_flags.bitfield.cpui386) | |
10793 | return (const reg_entry *) NULL; | |
10794 | ||
6e041cf4 | 10795 | if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx) |
192dc9c6 JB |
10796 | return (const reg_entry *) NULL; |
10797 | ||
6e041cf4 JB |
10798 | if (!cpu_arch_flags.bitfield.cpuavx512f) |
10799 | { | |
10800 | if (r->reg_type.bitfield.zmmword || r->reg_type.bitfield.regmask) | |
10801 | return (const reg_entry *) NULL; | |
40f12533 | 10802 | |
6e041cf4 JB |
10803 | if (!cpu_arch_flags.bitfield.cpuavx) |
10804 | { | |
10805 | if (r->reg_type.bitfield.ymmword) | |
10806 | return (const reg_entry *) NULL; | |
1848e567 | 10807 | |
6e041cf4 JB |
10808 | if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword) |
10809 | return (const reg_entry *) NULL; | |
10810 | } | |
10811 | } | |
43234a1e | 10812 | |
1adf7f56 JB |
10813 | if (r->reg_type.bitfield.regbnd && !cpu_arch_flags.bitfield.cpumpx) |
10814 | return (const reg_entry *) NULL; | |
10815 | ||
db51cc60 | 10816 | /* Don't allow fake index register unless allow_index_reg isn't 0. */ |
e968fc9b | 10817 | if (!allow_index_reg && r->reg_num == RegIZ) |
db51cc60 L |
10818 | return (const reg_entry *) NULL; |
10819 | ||
1d3f8286 JB |
10820 | /* Upper 16 vector registers are only available with VREX in 64bit |
10821 | mode, and require EVEX encoding. */ | |
10822 | if (r->reg_flags & RegVRex) | |
43234a1e | 10823 | { |
e951d5ca | 10824 | if (!cpu_arch_flags.bitfield.cpuavx512f |
43234a1e L |
10825 | || flag_code != CODE_64BIT) |
10826 | return (const reg_entry *) NULL; | |
1d3f8286 JB |
10827 | |
10828 | i.vec_encoding = vex_encoding_evex; | |
43234a1e L |
10829 | } |
10830 | ||
4787f4a5 JB |
10831 | if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword) |
10832 | && (!cpu_arch_flags.bitfield.cpulm || !r->reg_type.bitfield.control) | |
1ae00879 | 10833 | && flag_code != CODE_64BIT) |
20f0a1fc | 10834 | return (const reg_entry *) NULL; |
1ae00879 | 10835 | |
b7240065 JB |
10836 | if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax) |
10837 | return (const reg_entry *) NULL; | |
10838 | ||
252b5132 RH |
10839 | return r; |
10840 | } | |
4d1bb795 JB |
10841 | |
10842 | /* REG_STRING starts *before* REGISTER_PREFIX. */ | |
10843 | ||
10844 | static const reg_entry * | |
10845 | parse_register (char *reg_string, char **end_op) | |
10846 | { | |
10847 | const reg_entry *r; | |
10848 | ||
10849 | if (*reg_string == REGISTER_PREFIX || allow_naked_reg) | |
10850 | r = parse_real_register (reg_string, end_op); | |
10851 | else | |
10852 | r = NULL; | |
10853 | if (!r) | |
10854 | { | |
10855 | char *save = input_line_pointer; | |
10856 | char c; | |
10857 | symbolS *symbolP; | |
10858 | ||
10859 | input_line_pointer = reg_string; | |
d02603dc | 10860 | c = get_symbol_name (®_string); |
4d1bb795 JB |
10861 | symbolP = symbol_find (reg_string); |
10862 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) | |
10863 | { | |
10864 | const expressionS *e = symbol_get_value_expression (symbolP); | |
10865 | ||
0398aac5 | 10866 | know (e->X_op == O_register); |
4eed87de | 10867 | know (e->X_add_number >= 0 |
c3fe08fa | 10868 | && (valueT) e->X_add_number < i386_regtab_size); |
4d1bb795 | 10869 | r = i386_regtab + e->X_add_number; |
d3bb6b49 | 10870 | if ((r->reg_flags & RegVRex)) |
86fa6981 | 10871 | i.vec_encoding = vex_encoding_evex; |
4d1bb795 JB |
10872 | *end_op = input_line_pointer; |
10873 | } | |
10874 | *input_line_pointer = c; | |
10875 | input_line_pointer = save; | |
10876 | } | |
10877 | return r; | |
10878 | } | |
10879 | ||
10880 | int | |
10881 | i386_parse_name (char *name, expressionS *e, char *nextcharP) | |
10882 | { | |
10883 | const reg_entry *r; | |
10884 | char *end = input_line_pointer; | |
10885 | ||
10886 | *end = *nextcharP; | |
10887 | r = parse_register (name, &input_line_pointer); | |
10888 | if (r && end <= input_line_pointer) | |
10889 | { | |
10890 | *nextcharP = *input_line_pointer; | |
10891 | *input_line_pointer = 0; | |
10892 | e->X_op = O_register; | |
10893 | e->X_add_number = r - i386_regtab; | |
10894 | return 1; | |
10895 | } | |
10896 | input_line_pointer = end; | |
10897 | *end = 0; | |
ee86248c | 10898 | return intel_syntax ? i386_intel_parse_name (name, e) : 0; |
4d1bb795 JB |
10899 | } |
10900 | ||
10901 | void | |
10902 | md_operand (expressionS *e) | |
10903 | { | |
ee86248c JB |
10904 | char *end; |
10905 | const reg_entry *r; | |
4d1bb795 | 10906 | |
ee86248c JB |
10907 | switch (*input_line_pointer) |
10908 | { | |
10909 | case REGISTER_PREFIX: | |
10910 | r = parse_real_register (input_line_pointer, &end); | |
4d1bb795 JB |
10911 | if (r) |
10912 | { | |
10913 | e->X_op = O_register; | |
10914 | e->X_add_number = r - i386_regtab; | |
10915 | input_line_pointer = end; | |
10916 | } | |
ee86248c JB |
10917 | break; |
10918 | ||
10919 | case '[': | |
9c2799c2 | 10920 | gas_assert (intel_syntax); |
ee86248c JB |
10921 | end = input_line_pointer++; |
10922 | expression (e); | |
10923 | if (*input_line_pointer == ']') | |
10924 | { | |
10925 | ++input_line_pointer; | |
10926 | e->X_op_symbol = make_expr_symbol (e); | |
10927 | e->X_add_symbol = NULL; | |
10928 | e->X_add_number = 0; | |
10929 | e->X_op = O_index; | |
10930 | } | |
10931 | else | |
10932 | { | |
10933 | e->X_op = O_absent; | |
10934 | input_line_pointer = end; | |
10935 | } | |
10936 | break; | |
4d1bb795 JB |
10937 | } |
10938 | } | |
10939 | ||
252b5132 | 10940 | \f |
4cc782b5 | 10941 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
b6f8c7c4 | 10942 | const char *md_shortopts = "kVQ:sqnO::"; |
252b5132 | 10943 | #else |
b6f8c7c4 | 10944 | const char *md_shortopts = "qnO::"; |
252b5132 | 10945 | #endif |
6e0b89ee | 10946 | |
3e73aa7c | 10947 | #define OPTION_32 (OPTION_MD_BASE + 0) |
b3b91714 AM |
10948 | #define OPTION_64 (OPTION_MD_BASE + 1) |
10949 | #define OPTION_DIVIDE (OPTION_MD_BASE + 2) | |
9103f4f4 L |
10950 | #define OPTION_MARCH (OPTION_MD_BASE + 3) |
10951 | #define OPTION_MTUNE (OPTION_MD_BASE + 4) | |
1efbbeb4 L |
10952 | #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) |
10953 | #define OPTION_MSYNTAX (OPTION_MD_BASE + 6) | |
10954 | #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) | |
10955 | #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) | |
bd5dea88 | 10956 | #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9) |
c0f3af97 | 10957 | #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10) |
daf50ae7 | 10958 | #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11) |
7bab8ab5 JB |
10959 | #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12) |
10960 | #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13) | |
10961 | #define OPTION_X32 (OPTION_MD_BASE + 14) | |
7e8b059b | 10962 | #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15) |
43234a1e L |
10963 | #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16) |
10964 | #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17) | |
167ad85b | 10965 | #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18) |
d1982f93 | 10966 | #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19) |
d3d3c6db | 10967 | #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20) |
8dcea932 | 10968 | #define OPTION_MSHARED (OPTION_MD_BASE + 21) |
5db04b09 L |
10969 | #define OPTION_MAMD64 (OPTION_MD_BASE + 22) |
10970 | #define OPTION_MINTEL64 (OPTION_MD_BASE + 23) | |
e4e00185 | 10971 | #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24) |
b4a3a7b4 | 10972 | #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25) |
03751133 | 10973 | #define OPTION_MVEXWIG (OPTION_MD_BASE + 26) |
b3b91714 | 10974 | |
99ad8390 NC |
10975 | struct option md_longopts[] = |
10976 | { | |
3e73aa7c | 10977 | {"32", no_argument, NULL, OPTION_32}, |
321098a5 | 10978 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 10979 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c | 10980 | {"64", no_argument, NULL, OPTION_64}, |
351f65ca L |
10981 | #endif |
10982 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
570561f7 | 10983 | {"x32", no_argument, NULL, OPTION_X32}, |
8dcea932 | 10984 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
b4a3a7b4 | 10985 | {"mx86-used-note", required_argument, NULL, OPTION_X86_USED_NOTE}, |
6e0b89ee | 10986 | #endif |
b3b91714 | 10987 | {"divide", no_argument, NULL, OPTION_DIVIDE}, |
9103f4f4 L |
10988 | {"march", required_argument, NULL, OPTION_MARCH}, |
10989 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1efbbeb4 L |
10990 | {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, |
10991 | {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, | |
10992 | {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, | |
10993 | {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, | |
c0f3af97 | 10994 | {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX}, |
daf50ae7 | 10995 | {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK}, |
7bab8ab5 | 10996 | {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK}, |
539f890d | 10997 | {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR}, |
03751133 | 10998 | {"mvexwig", required_argument, NULL, OPTION_MVEXWIG}, |
7e8b059b | 10999 | {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX}, |
43234a1e L |
11000 | {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG}, |
11001 | {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG}, | |
167ad85b TG |
11002 | # if defined (TE_PE) || defined (TE_PEP) |
11003 | {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ}, | |
11004 | #endif | |
d1982f93 | 11005 | {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX}, |
e4e00185 | 11006 | {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD}, |
0cb4071e | 11007 | {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS}, |
d3d3c6db | 11008 | {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG}, |
5db04b09 L |
11009 | {"mamd64", no_argument, NULL, OPTION_MAMD64}, |
11010 | {"mintel64", no_argument, NULL, OPTION_MINTEL64}, | |
252b5132 RH |
11011 | {NULL, no_argument, NULL, 0} |
11012 | }; | |
11013 | size_t md_longopts_size = sizeof (md_longopts); | |
11014 | ||
11015 | int | |
17b9d67d | 11016 | md_parse_option (int c, const char *arg) |
252b5132 | 11017 | { |
91d6fa6a | 11018 | unsigned int j; |
293f5f65 | 11019 | char *arch, *next, *saved; |
9103f4f4 | 11020 | |
252b5132 RH |
11021 | switch (c) |
11022 | { | |
12b55ccc L |
11023 | case 'n': |
11024 | optimize_align_code = 0; | |
11025 | break; | |
11026 | ||
a38cf1db AM |
11027 | case 'q': |
11028 | quiet_warnings = 1; | |
252b5132 RH |
11029 | break; |
11030 | ||
11031 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
11032 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
11033 | should be emitted or not. FIXME: Not implemented. */ | |
11034 | case 'Q': | |
252b5132 RH |
11035 | break; |
11036 | ||
11037 | /* -V: SVR4 argument to print version ID. */ | |
11038 | case 'V': | |
11039 | print_version_id (); | |
11040 | break; | |
11041 | ||
a38cf1db AM |
11042 | /* -k: Ignore for FreeBSD compatibility. */ |
11043 | case 'k': | |
252b5132 | 11044 | break; |
4cc782b5 ILT |
11045 | |
11046 | case 's': | |
11047 | /* -s: On i386 Solaris, this tells the native assembler to use | |
29b0f896 | 11048 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
4cc782b5 | 11049 | break; |
8dcea932 L |
11050 | |
11051 | case OPTION_MSHARED: | |
11052 | shared = 1; | |
11053 | break; | |
b4a3a7b4 L |
11054 | |
11055 | case OPTION_X86_USED_NOTE: | |
11056 | if (strcasecmp (arg, "yes") == 0) | |
11057 | x86_used_note = 1; | |
11058 | else if (strcasecmp (arg, "no") == 0) | |
11059 | x86_used_note = 0; | |
11060 | else | |
11061 | as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg); | |
11062 | break; | |
11063 | ||
11064 | ||
99ad8390 | 11065 | #endif |
321098a5 | 11066 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 11067 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c JH |
11068 | case OPTION_64: |
11069 | { | |
11070 | const char **list, **l; | |
11071 | ||
3e73aa7c JH |
11072 | list = bfd_target_list (); |
11073 | for (l = list; *l != NULL; l++) | |
8620418b | 11074 | if (CONST_STRNEQ (*l, "elf64-x86-64") |
99ad8390 NC |
11075 | || strcmp (*l, "coff-x86-64") == 0 |
11076 | || strcmp (*l, "pe-x86-64") == 0 | |
d382c579 TG |
11077 | || strcmp (*l, "pei-x86-64") == 0 |
11078 | || strcmp (*l, "mach-o-x86-64") == 0) | |
6e0b89ee AM |
11079 | { |
11080 | default_arch = "x86_64"; | |
11081 | break; | |
11082 | } | |
3e73aa7c | 11083 | if (*l == NULL) |
2b5d6a91 | 11084 | as_fatal (_("no compiled in support for x86_64")); |
3e73aa7c JH |
11085 | free (list); |
11086 | } | |
11087 | break; | |
11088 | #endif | |
252b5132 | 11089 | |
351f65ca | 11090 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
570561f7 | 11091 | case OPTION_X32: |
351f65ca L |
11092 | if (IS_ELF) |
11093 | { | |
11094 | const char **list, **l; | |
11095 | ||
11096 | list = bfd_target_list (); | |
11097 | for (l = list; *l != NULL; l++) | |
11098 | if (CONST_STRNEQ (*l, "elf32-x86-64")) | |
11099 | { | |
11100 | default_arch = "x86_64:32"; | |
11101 | break; | |
11102 | } | |
11103 | if (*l == NULL) | |
2b5d6a91 | 11104 | as_fatal (_("no compiled in support for 32bit x86_64")); |
351f65ca L |
11105 | free (list); |
11106 | } | |
11107 | else | |
11108 | as_fatal (_("32bit x86_64 is only supported for ELF")); | |
11109 | break; | |
11110 | #endif | |
11111 | ||
6e0b89ee AM |
11112 | case OPTION_32: |
11113 | default_arch = "i386"; | |
11114 | break; | |
11115 | ||
b3b91714 AM |
11116 | case OPTION_DIVIDE: |
11117 | #ifdef SVR4_COMMENT_CHARS | |
11118 | { | |
11119 | char *n, *t; | |
11120 | const char *s; | |
11121 | ||
add39d23 | 11122 | n = XNEWVEC (char, strlen (i386_comment_chars) + 1); |
b3b91714 AM |
11123 | t = n; |
11124 | for (s = i386_comment_chars; *s != '\0'; s++) | |
11125 | if (*s != '/') | |
11126 | *t++ = *s; | |
11127 | *t = '\0'; | |
11128 | i386_comment_chars = n; | |
11129 | } | |
11130 | #endif | |
11131 | break; | |
11132 | ||
9103f4f4 | 11133 | case OPTION_MARCH: |
293f5f65 L |
11134 | saved = xstrdup (arg); |
11135 | arch = saved; | |
11136 | /* Allow -march=+nosse. */ | |
11137 | if (*arch == '+') | |
11138 | arch++; | |
6305a203 | 11139 | do |
9103f4f4 | 11140 | { |
6305a203 | 11141 | if (*arch == '.') |
2b5d6a91 | 11142 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
11143 | next = strchr (arch, '+'); |
11144 | if (next) | |
11145 | *next++ = '\0'; | |
91d6fa6a | 11146 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 11147 | { |
91d6fa6a | 11148 | if (strcmp (arch, cpu_arch [j].name) == 0) |
ccc9c027 | 11149 | { |
6305a203 | 11150 | /* Processor. */ |
1ded5609 JB |
11151 | if (! cpu_arch[j].flags.bitfield.cpui386) |
11152 | continue; | |
11153 | ||
91d6fa6a | 11154 | cpu_arch_name = cpu_arch[j].name; |
6305a203 | 11155 | cpu_sub_arch_name = NULL; |
91d6fa6a NC |
11156 | cpu_arch_flags = cpu_arch[j].flags; |
11157 | cpu_arch_isa = cpu_arch[j].type; | |
11158 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
6305a203 L |
11159 | if (!cpu_arch_tune_set) |
11160 | { | |
11161 | cpu_arch_tune = cpu_arch_isa; | |
11162 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
11163 | } | |
11164 | break; | |
11165 | } | |
91d6fa6a NC |
11166 | else if (*cpu_arch [j].name == '.' |
11167 | && strcmp (arch, cpu_arch [j].name + 1) == 0) | |
6305a203 | 11168 | { |
33eaf5de | 11169 | /* ISA extension. */ |
6305a203 | 11170 | i386_cpu_flags flags; |
309d3373 | 11171 | |
293f5f65 L |
11172 | flags = cpu_flags_or (cpu_arch_flags, |
11173 | cpu_arch[j].flags); | |
81486035 | 11174 | |
5b64d091 | 11175 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
6305a203 L |
11176 | { |
11177 | if (cpu_sub_arch_name) | |
11178 | { | |
11179 | char *name = cpu_sub_arch_name; | |
11180 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 11181 | cpu_arch[j].name, |
1bf57e9f | 11182 | (const char *) NULL); |
6305a203 L |
11183 | free (name); |
11184 | } | |
11185 | else | |
91d6fa6a | 11186 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
6305a203 | 11187 | cpu_arch_flags = flags; |
a586129e | 11188 | cpu_arch_isa_flags = flags; |
6305a203 | 11189 | } |
0089dace L |
11190 | else |
11191 | cpu_arch_isa_flags | |
11192 | = cpu_flags_or (cpu_arch_isa_flags, | |
11193 | cpu_arch[j].flags); | |
6305a203 | 11194 | break; |
ccc9c027 | 11195 | } |
9103f4f4 | 11196 | } |
6305a203 | 11197 | |
293f5f65 L |
11198 | if (j >= ARRAY_SIZE (cpu_arch)) |
11199 | { | |
33eaf5de | 11200 | /* Disable an ISA extension. */ |
293f5f65 L |
11201 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
11202 | if (strcmp (arch, cpu_noarch [j].name) == 0) | |
11203 | { | |
11204 | i386_cpu_flags flags; | |
11205 | ||
11206 | flags = cpu_flags_and_not (cpu_arch_flags, | |
11207 | cpu_noarch[j].flags); | |
11208 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
11209 | { | |
11210 | if (cpu_sub_arch_name) | |
11211 | { | |
11212 | char *name = cpu_sub_arch_name; | |
11213 | cpu_sub_arch_name = concat (arch, | |
11214 | (const char *) NULL); | |
11215 | free (name); | |
11216 | } | |
11217 | else | |
11218 | cpu_sub_arch_name = xstrdup (arch); | |
11219 | cpu_arch_flags = flags; | |
11220 | cpu_arch_isa_flags = flags; | |
11221 | } | |
11222 | break; | |
11223 | } | |
11224 | ||
11225 | if (j >= ARRAY_SIZE (cpu_noarch)) | |
11226 | j = ARRAY_SIZE (cpu_arch); | |
11227 | } | |
11228 | ||
91d6fa6a | 11229 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 11230 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
11231 | |
11232 | arch = next; | |
9103f4f4 | 11233 | } |
293f5f65 L |
11234 | while (next != NULL); |
11235 | free (saved); | |
9103f4f4 L |
11236 | break; |
11237 | ||
11238 | case OPTION_MTUNE: | |
11239 | if (*arg == '.') | |
2b5d6a91 | 11240 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
91d6fa6a | 11241 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 11242 | { |
91d6fa6a | 11243 | if (strcmp (arg, cpu_arch [j].name) == 0) |
9103f4f4 | 11244 | { |
ccc9c027 | 11245 | cpu_arch_tune_set = 1; |
91d6fa6a NC |
11246 | cpu_arch_tune = cpu_arch [j].type; |
11247 | cpu_arch_tune_flags = cpu_arch[j].flags; | |
9103f4f4 L |
11248 | break; |
11249 | } | |
11250 | } | |
91d6fa6a | 11251 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 11252 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
9103f4f4 L |
11253 | break; |
11254 | ||
1efbbeb4 L |
11255 | case OPTION_MMNEMONIC: |
11256 | if (strcasecmp (arg, "att") == 0) | |
11257 | intel_mnemonic = 0; | |
11258 | else if (strcasecmp (arg, "intel") == 0) | |
11259 | intel_mnemonic = 1; | |
11260 | else | |
2b5d6a91 | 11261 | as_fatal (_("invalid -mmnemonic= option: `%s'"), arg); |
1efbbeb4 L |
11262 | break; |
11263 | ||
11264 | case OPTION_MSYNTAX: | |
11265 | if (strcasecmp (arg, "att") == 0) | |
11266 | intel_syntax = 0; | |
11267 | else if (strcasecmp (arg, "intel") == 0) | |
11268 | intel_syntax = 1; | |
11269 | else | |
2b5d6a91 | 11270 | as_fatal (_("invalid -msyntax= option: `%s'"), arg); |
1efbbeb4 L |
11271 | break; |
11272 | ||
11273 | case OPTION_MINDEX_REG: | |
11274 | allow_index_reg = 1; | |
11275 | break; | |
11276 | ||
11277 | case OPTION_MNAKED_REG: | |
11278 | allow_naked_reg = 1; | |
11279 | break; | |
11280 | ||
c0f3af97 L |
11281 | case OPTION_MSSE2AVX: |
11282 | sse2avx = 1; | |
11283 | break; | |
11284 | ||
daf50ae7 L |
11285 | case OPTION_MSSE_CHECK: |
11286 | if (strcasecmp (arg, "error") == 0) | |
7bab8ab5 | 11287 | sse_check = check_error; |
daf50ae7 | 11288 | else if (strcasecmp (arg, "warning") == 0) |
7bab8ab5 | 11289 | sse_check = check_warning; |
daf50ae7 | 11290 | else if (strcasecmp (arg, "none") == 0) |
7bab8ab5 | 11291 | sse_check = check_none; |
daf50ae7 | 11292 | else |
2b5d6a91 | 11293 | as_fatal (_("invalid -msse-check= option: `%s'"), arg); |
daf50ae7 L |
11294 | break; |
11295 | ||
7bab8ab5 JB |
11296 | case OPTION_MOPERAND_CHECK: |
11297 | if (strcasecmp (arg, "error") == 0) | |
11298 | operand_check = check_error; | |
11299 | else if (strcasecmp (arg, "warning") == 0) | |
11300 | operand_check = check_warning; | |
11301 | else if (strcasecmp (arg, "none") == 0) | |
11302 | operand_check = check_none; | |
11303 | else | |
11304 | as_fatal (_("invalid -moperand-check= option: `%s'"), arg); | |
11305 | break; | |
11306 | ||
539f890d L |
11307 | case OPTION_MAVXSCALAR: |
11308 | if (strcasecmp (arg, "128") == 0) | |
11309 | avxscalar = vex128; | |
11310 | else if (strcasecmp (arg, "256") == 0) | |
11311 | avxscalar = vex256; | |
11312 | else | |
2b5d6a91 | 11313 | as_fatal (_("invalid -mavxscalar= option: `%s'"), arg); |
539f890d L |
11314 | break; |
11315 | ||
03751133 L |
11316 | case OPTION_MVEXWIG: |
11317 | if (strcmp (arg, "0") == 0) | |
11318 | vexwig = evexw0; | |
11319 | else if (strcmp (arg, "1") == 0) | |
11320 | vexwig = evexw1; | |
11321 | else | |
11322 | as_fatal (_("invalid -mvexwig= option: `%s'"), arg); | |
11323 | break; | |
11324 | ||
7e8b059b L |
11325 | case OPTION_MADD_BND_PREFIX: |
11326 | add_bnd_prefix = 1; | |
11327 | break; | |
11328 | ||
43234a1e L |
11329 | case OPTION_MEVEXLIG: |
11330 | if (strcmp (arg, "128") == 0) | |
11331 | evexlig = evexl128; | |
11332 | else if (strcmp (arg, "256") == 0) | |
11333 | evexlig = evexl256; | |
11334 | else if (strcmp (arg, "512") == 0) | |
11335 | evexlig = evexl512; | |
11336 | else | |
11337 | as_fatal (_("invalid -mevexlig= option: `%s'"), arg); | |
11338 | break; | |
11339 | ||
d3d3c6db IT |
11340 | case OPTION_MEVEXRCIG: |
11341 | if (strcmp (arg, "rne") == 0) | |
11342 | evexrcig = rne; | |
11343 | else if (strcmp (arg, "rd") == 0) | |
11344 | evexrcig = rd; | |
11345 | else if (strcmp (arg, "ru") == 0) | |
11346 | evexrcig = ru; | |
11347 | else if (strcmp (arg, "rz") == 0) | |
11348 | evexrcig = rz; | |
11349 | else | |
11350 | as_fatal (_("invalid -mevexrcig= option: `%s'"), arg); | |
11351 | break; | |
11352 | ||
43234a1e L |
11353 | case OPTION_MEVEXWIG: |
11354 | if (strcmp (arg, "0") == 0) | |
11355 | evexwig = evexw0; | |
11356 | else if (strcmp (arg, "1") == 0) | |
11357 | evexwig = evexw1; | |
11358 | else | |
11359 | as_fatal (_("invalid -mevexwig= option: `%s'"), arg); | |
11360 | break; | |
11361 | ||
167ad85b TG |
11362 | # if defined (TE_PE) || defined (TE_PEP) |
11363 | case OPTION_MBIG_OBJ: | |
11364 | use_big_obj = 1; | |
11365 | break; | |
11366 | #endif | |
11367 | ||
d1982f93 | 11368 | case OPTION_MOMIT_LOCK_PREFIX: |
d022bddd IT |
11369 | if (strcasecmp (arg, "yes") == 0) |
11370 | omit_lock_prefix = 1; | |
11371 | else if (strcasecmp (arg, "no") == 0) | |
11372 | omit_lock_prefix = 0; | |
11373 | else | |
11374 | as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg); | |
11375 | break; | |
11376 | ||
e4e00185 AS |
11377 | case OPTION_MFENCE_AS_LOCK_ADD: |
11378 | if (strcasecmp (arg, "yes") == 0) | |
11379 | avoid_fence = 1; | |
11380 | else if (strcasecmp (arg, "no") == 0) | |
11381 | avoid_fence = 0; | |
11382 | else | |
11383 | as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg); | |
11384 | break; | |
11385 | ||
0cb4071e L |
11386 | case OPTION_MRELAX_RELOCATIONS: |
11387 | if (strcasecmp (arg, "yes") == 0) | |
11388 | generate_relax_relocations = 1; | |
11389 | else if (strcasecmp (arg, "no") == 0) | |
11390 | generate_relax_relocations = 0; | |
11391 | else | |
11392 | as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg); | |
11393 | break; | |
11394 | ||
5db04b09 | 11395 | case OPTION_MAMD64: |
e89c5eaa | 11396 | intel64 = 0; |
5db04b09 L |
11397 | break; |
11398 | ||
11399 | case OPTION_MINTEL64: | |
e89c5eaa | 11400 | intel64 = 1; |
5db04b09 L |
11401 | break; |
11402 | ||
b6f8c7c4 L |
11403 | case 'O': |
11404 | if (arg == NULL) | |
11405 | { | |
11406 | optimize = 1; | |
11407 | /* Turn off -Os. */ | |
11408 | optimize_for_space = 0; | |
11409 | } | |
11410 | else if (*arg == 's') | |
11411 | { | |
11412 | optimize_for_space = 1; | |
11413 | /* Turn on all encoding optimizations. */ | |
41fd2579 | 11414 | optimize = INT_MAX; |
b6f8c7c4 L |
11415 | } |
11416 | else | |
11417 | { | |
11418 | optimize = atoi (arg); | |
11419 | /* Turn off -Os. */ | |
11420 | optimize_for_space = 0; | |
11421 | } | |
11422 | break; | |
11423 | ||
252b5132 RH |
11424 | default: |
11425 | return 0; | |
11426 | } | |
11427 | return 1; | |
11428 | } | |
11429 | ||
8a2c8fef L |
11430 | #define MESSAGE_TEMPLATE \ |
11431 | " " | |
11432 | ||
293f5f65 L |
11433 | static char * |
11434 | output_message (FILE *stream, char *p, char *message, char *start, | |
11435 | int *left_p, const char *name, int len) | |
11436 | { | |
11437 | int size = sizeof (MESSAGE_TEMPLATE); | |
11438 | int left = *left_p; | |
11439 | ||
11440 | /* Reserve 2 spaces for ", " or ",\0" */ | |
11441 | left -= len + 2; | |
11442 | ||
11443 | /* Check if there is any room. */ | |
11444 | if (left >= 0) | |
11445 | { | |
11446 | if (p != start) | |
11447 | { | |
11448 | *p++ = ','; | |
11449 | *p++ = ' '; | |
11450 | } | |
11451 | p = mempcpy (p, name, len); | |
11452 | } | |
11453 | else | |
11454 | { | |
11455 | /* Output the current message now and start a new one. */ | |
11456 | *p++ = ','; | |
11457 | *p = '\0'; | |
11458 | fprintf (stream, "%s\n", message); | |
11459 | p = start; | |
11460 | left = size - (start - message) - len - 2; | |
11461 | ||
11462 | gas_assert (left >= 0); | |
11463 | ||
11464 | p = mempcpy (p, name, len); | |
11465 | } | |
11466 | ||
11467 | *left_p = left; | |
11468 | return p; | |
11469 | } | |
11470 | ||
8a2c8fef | 11471 | static void |
1ded5609 | 11472 | show_arch (FILE *stream, int ext, int check) |
8a2c8fef L |
11473 | { |
11474 | static char message[] = MESSAGE_TEMPLATE; | |
11475 | char *start = message + 27; | |
11476 | char *p; | |
11477 | int size = sizeof (MESSAGE_TEMPLATE); | |
11478 | int left; | |
11479 | const char *name; | |
11480 | int len; | |
11481 | unsigned int j; | |
11482 | ||
11483 | p = start; | |
11484 | left = size - (start - message); | |
11485 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) | |
11486 | { | |
11487 | /* Should it be skipped? */ | |
11488 | if (cpu_arch [j].skip) | |
11489 | continue; | |
11490 | ||
11491 | name = cpu_arch [j].name; | |
11492 | len = cpu_arch [j].len; | |
11493 | if (*name == '.') | |
11494 | { | |
11495 | /* It is an extension. Skip if we aren't asked to show it. */ | |
11496 | if (ext) | |
11497 | { | |
11498 | name++; | |
11499 | len--; | |
11500 | } | |
11501 | else | |
11502 | continue; | |
11503 | } | |
11504 | else if (ext) | |
11505 | { | |
11506 | /* It is an processor. Skip if we show only extension. */ | |
11507 | continue; | |
11508 | } | |
1ded5609 JB |
11509 | else if (check && ! cpu_arch[j].flags.bitfield.cpui386) |
11510 | { | |
11511 | /* It is an impossible processor - skip. */ | |
11512 | continue; | |
11513 | } | |
8a2c8fef | 11514 | |
293f5f65 | 11515 | p = output_message (stream, p, message, start, &left, name, len); |
8a2c8fef L |
11516 | } |
11517 | ||
293f5f65 L |
11518 | /* Display disabled extensions. */ |
11519 | if (ext) | |
11520 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) | |
11521 | { | |
11522 | name = cpu_noarch [j].name; | |
11523 | len = cpu_noarch [j].len; | |
11524 | p = output_message (stream, p, message, start, &left, name, | |
11525 | len); | |
11526 | } | |
11527 | ||
8a2c8fef L |
11528 | *p = '\0'; |
11529 | fprintf (stream, "%s\n", message); | |
11530 | } | |
11531 | ||
252b5132 | 11532 | void |
8a2c8fef | 11533 | md_show_usage (FILE *stream) |
252b5132 | 11534 | { |
4cc782b5 ILT |
11535 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
11536 | fprintf (stream, _("\ | |
a38cf1db AM |
11537 | -Q ignored\n\ |
11538 | -V print assembler version number\n\ | |
b3b91714 AM |
11539 | -k ignored\n")); |
11540 | #endif | |
11541 | fprintf (stream, _("\ | |
12b55ccc | 11542 | -n Do not optimize code alignment\n\ |
b3b91714 AM |
11543 | -q quieten some warnings\n")); |
11544 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
11545 | fprintf (stream, _("\ | |
a38cf1db | 11546 | -s ignored\n")); |
b3b91714 | 11547 | #endif |
d7f449c0 L |
11548 | #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
11549 | || defined (TE_PE) || defined (TE_PEP)) | |
751d281c | 11550 | fprintf (stream, _("\ |
570561f7 | 11551 | --32/--64/--x32 generate 32bit/64bit/x32 code\n")); |
751d281c | 11552 | #endif |
b3b91714 AM |
11553 | #ifdef SVR4_COMMENT_CHARS |
11554 | fprintf (stream, _("\ | |
11555 | --divide do not treat `/' as a comment character\n")); | |
a38cf1db AM |
11556 | #else |
11557 | fprintf (stream, _("\ | |
b3b91714 | 11558 | --divide ignored\n")); |
4cc782b5 | 11559 | #endif |
9103f4f4 | 11560 | fprintf (stream, _("\ |
6305a203 | 11561 | -march=CPU[,+EXTENSION...]\n\ |
8a2c8fef | 11562 | generate code for CPU and EXTENSION, CPU is one of:\n")); |
1ded5609 | 11563 | show_arch (stream, 0, 1); |
8a2c8fef L |
11564 | fprintf (stream, _("\ |
11565 | EXTENSION is combination of:\n")); | |
1ded5609 | 11566 | show_arch (stream, 1, 0); |
6305a203 | 11567 | fprintf (stream, _("\ |
8a2c8fef | 11568 | -mtune=CPU optimize for CPU, CPU is one of:\n")); |
1ded5609 | 11569 | show_arch (stream, 0, 0); |
ba104c83 | 11570 | fprintf (stream, _("\ |
c0f3af97 L |
11571 | -msse2avx encode SSE instructions with VEX prefix\n")); |
11572 | fprintf (stream, _("\ | |
7c5c05ef | 11573 | -msse-check=[none|error|warning] (default: warning)\n\ |
daf50ae7 L |
11574 | check SSE instructions\n")); |
11575 | fprintf (stream, _("\ | |
7c5c05ef | 11576 | -moperand-check=[none|error|warning] (default: warning)\n\ |
7bab8ab5 JB |
11577 | check operand combinations for validity\n")); |
11578 | fprintf (stream, _("\ | |
7c5c05ef L |
11579 | -mavxscalar=[128|256] (default: 128)\n\ |
11580 | encode scalar AVX instructions with specific vector\n\ | |
539f890d L |
11581 | length\n")); |
11582 | fprintf (stream, _("\ | |
03751133 L |
11583 | -mvexwig=[0|1] (default: 0)\n\ |
11584 | encode VEX instructions with specific VEX.W value\n\ | |
11585 | for VEX.W bit ignored instructions\n")); | |
11586 | fprintf (stream, _("\ | |
7c5c05ef L |
11587 | -mevexlig=[128|256|512] (default: 128)\n\ |
11588 | encode scalar EVEX instructions with specific vector\n\ | |
43234a1e L |
11589 | length\n")); |
11590 | fprintf (stream, _("\ | |
7c5c05ef L |
11591 | -mevexwig=[0|1] (default: 0)\n\ |
11592 | encode EVEX instructions with specific EVEX.W value\n\ | |
43234a1e L |
11593 | for EVEX.W bit ignored instructions\n")); |
11594 | fprintf (stream, _("\ | |
7c5c05ef | 11595 | -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\ |
d3d3c6db IT |
11596 | encode EVEX instructions with specific EVEX.RC value\n\ |
11597 | for SAE-only ignored instructions\n")); | |
11598 | fprintf (stream, _("\ | |
7c5c05ef L |
11599 | -mmnemonic=[att|intel] ")); |
11600 | if (SYSV386_COMPAT) | |
11601 | fprintf (stream, _("(default: att)\n")); | |
11602 | else | |
11603 | fprintf (stream, _("(default: intel)\n")); | |
11604 | fprintf (stream, _("\ | |
11605 | use AT&T/Intel mnemonic\n")); | |
ba104c83 | 11606 | fprintf (stream, _("\ |
7c5c05ef L |
11607 | -msyntax=[att|intel] (default: att)\n\ |
11608 | use AT&T/Intel syntax\n")); | |
ba104c83 L |
11609 | fprintf (stream, _("\ |
11610 | -mindex-reg support pseudo index registers\n")); | |
11611 | fprintf (stream, _("\ | |
11612 | -mnaked-reg don't require `%%' prefix for registers\n")); | |
11613 | fprintf (stream, _("\ | |
7e8b059b | 11614 | -madd-bnd-prefix add BND prefix for all valid branches\n")); |
b4a3a7b4 | 11615 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8dcea932 L |
11616 | fprintf (stream, _("\ |
11617 | -mshared disable branch optimization for shared code\n")); | |
b4a3a7b4 L |
11618 | fprintf (stream, _("\ |
11619 | -mx86-used-note=[no|yes] ")); | |
11620 | if (DEFAULT_X86_USED_NOTE) | |
11621 | fprintf (stream, _("(default: yes)\n")); | |
11622 | else | |
11623 | fprintf (stream, _("(default: no)\n")); | |
11624 | fprintf (stream, _("\ | |
11625 | generate x86 used ISA and feature properties\n")); | |
11626 | #endif | |
11627 | #if defined (TE_PE) || defined (TE_PEP) | |
167ad85b TG |
11628 | fprintf (stream, _("\ |
11629 | -mbig-obj generate big object files\n")); | |
11630 | #endif | |
d022bddd | 11631 | fprintf (stream, _("\ |
7c5c05ef | 11632 | -momit-lock-prefix=[no|yes] (default: no)\n\ |
d022bddd | 11633 | strip all lock prefixes\n")); |
5db04b09 | 11634 | fprintf (stream, _("\ |
7c5c05ef | 11635 | -mfence-as-lock-add=[no|yes] (default: no)\n\ |
e4e00185 AS |
11636 | encode lfence, mfence and sfence as\n\ |
11637 | lock addl $0x0, (%%{re}sp)\n")); | |
11638 | fprintf (stream, _("\ | |
7c5c05ef L |
11639 | -mrelax-relocations=[no|yes] ")); |
11640 | if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS) | |
11641 | fprintf (stream, _("(default: yes)\n")); | |
11642 | else | |
11643 | fprintf (stream, _("(default: no)\n")); | |
11644 | fprintf (stream, _("\ | |
0cb4071e L |
11645 | generate relax relocations\n")); |
11646 | fprintf (stream, _("\ | |
7c5c05ef | 11647 | -mamd64 accept only AMD64 ISA [default]\n")); |
5db04b09 L |
11648 | fprintf (stream, _("\ |
11649 | -mintel64 accept only Intel64 ISA\n")); | |
252b5132 RH |
11650 | } |
11651 | ||
3e73aa7c | 11652 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
321098a5 | 11653 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
e57f8c65 | 11654 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
252b5132 RH |
11655 | |
11656 | /* Pick the target format to use. */ | |
11657 | ||
47926f60 | 11658 | const char * |
e3bb37b5 | 11659 | i386_target_format (void) |
252b5132 | 11660 | { |
351f65ca L |
11661 | if (!strncmp (default_arch, "x86_64", 6)) |
11662 | { | |
11663 | update_code_flag (CODE_64BIT, 1); | |
11664 | if (default_arch[6] == '\0') | |
7f56bc95 | 11665 | x86_elf_abi = X86_64_ABI; |
351f65ca | 11666 | else |
7f56bc95 | 11667 | x86_elf_abi = X86_64_X32_ABI; |
351f65ca | 11668 | } |
3e73aa7c | 11669 | else if (!strcmp (default_arch, "i386")) |
78f12dd3 | 11670 | update_code_flag (CODE_32BIT, 1); |
5197d474 L |
11671 | else if (!strcmp (default_arch, "iamcu")) |
11672 | { | |
11673 | update_code_flag (CODE_32BIT, 1); | |
11674 | if (cpu_arch_isa == PROCESSOR_UNKNOWN) | |
11675 | { | |
11676 | static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS; | |
11677 | cpu_arch_name = "iamcu"; | |
11678 | cpu_sub_arch_name = NULL; | |
11679 | cpu_arch_flags = iamcu_flags; | |
11680 | cpu_arch_isa = PROCESSOR_IAMCU; | |
11681 | cpu_arch_isa_flags = iamcu_flags; | |
11682 | if (!cpu_arch_tune_set) | |
11683 | { | |
11684 | cpu_arch_tune = cpu_arch_isa; | |
11685 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
11686 | } | |
11687 | } | |
8d471ec1 | 11688 | else if (cpu_arch_isa != PROCESSOR_IAMCU) |
5197d474 L |
11689 | as_fatal (_("Intel MCU doesn't support `%s' architecture"), |
11690 | cpu_arch_name); | |
11691 | } | |
3e73aa7c | 11692 | else |
2b5d6a91 | 11693 | as_fatal (_("unknown architecture")); |
89507696 JB |
11694 | |
11695 | if (cpu_flags_all_zero (&cpu_arch_isa_flags)) | |
11696 | cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
11697 | if (cpu_flags_all_zero (&cpu_arch_tune_flags)) | |
11698 | cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
11699 | ||
252b5132 RH |
11700 | switch (OUTPUT_FLAVOR) |
11701 | { | |
9384f2ff | 11702 | #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT) |
4c63da97 | 11703 | case bfd_target_aout_flavour: |
47926f60 | 11704 | return AOUT_TARGET_FORMAT; |
4c63da97 | 11705 | #endif |
9384f2ff AM |
11706 | #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF) |
11707 | # if defined (TE_PE) || defined (TE_PEP) | |
11708 | case bfd_target_coff_flavour: | |
167ad85b TG |
11709 | if (flag_code == CODE_64BIT) |
11710 | return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64"; | |
11711 | else | |
11712 | return "pe-i386"; | |
9384f2ff | 11713 | # elif defined (TE_GO32) |
0561d57c JK |
11714 | case bfd_target_coff_flavour: |
11715 | return "coff-go32"; | |
9384f2ff | 11716 | # else |
252b5132 RH |
11717 | case bfd_target_coff_flavour: |
11718 | return "coff-i386"; | |
9384f2ff | 11719 | # endif |
4c63da97 | 11720 | #endif |
3e73aa7c | 11721 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 11722 | case bfd_target_elf_flavour: |
3e73aa7c | 11723 | { |
351f65ca L |
11724 | const char *format; |
11725 | ||
11726 | switch (x86_elf_abi) | |
4fa24527 | 11727 | { |
351f65ca L |
11728 | default: |
11729 | format = ELF_TARGET_FORMAT; | |
11730 | break; | |
7f56bc95 | 11731 | case X86_64_ABI: |
351f65ca | 11732 | use_rela_relocations = 1; |
4fa24527 | 11733 | object_64bit = 1; |
351f65ca L |
11734 | format = ELF_TARGET_FORMAT64; |
11735 | break; | |
7f56bc95 | 11736 | case X86_64_X32_ABI: |
4fa24527 | 11737 | use_rela_relocations = 1; |
351f65ca | 11738 | object_64bit = 1; |
862be3fb | 11739 | disallow_64bit_reloc = 1; |
351f65ca L |
11740 | format = ELF_TARGET_FORMAT32; |
11741 | break; | |
4fa24527 | 11742 | } |
3632d14b | 11743 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 11744 | { |
7f56bc95 | 11745 | if (x86_elf_abi != X86_64_ABI) |
8a9036a4 L |
11746 | as_fatal (_("Intel L1OM is 64bit only")); |
11747 | return ELF_TARGET_L1OM_FORMAT; | |
11748 | } | |
b49f93f6 | 11749 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
7a9068fe L |
11750 | { |
11751 | if (x86_elf_abi != X86_64_ABI) | |
11752 | as_fatal (_("Intel K1OM is 64bit only")); | |
11753 | return ELF_TARGET_K1OM_FORMAT; | |
11754 | } | |
81486035 L |
11755 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
11756 | { | |
11757 | if (x86_elf_abi != I386_ABI) | |
11758 | as_fatal (_("Intel MCU is 32bit only")); | |
11759 | return ELF_TARGET_IAMCU_FORMAT; | |
11760 | } | |
8a9036a4 | 11761 | else |
351f65ca | 11762 | return format; |
3e73aa7c | 11763 | } |
e57f8c65 TG |
11764 | #endif |
11765 | #if defined (OBJ_MACH_O) | |
11766 | case bfd_target_mach_o_flavour: | |
d382c579 TG |
11767 | if (flag_code == CODE_64BIT) |
11768 | { | |
11769 | use_rela_relocations = 1; | |
11770 | object_64bit = 1; | |
11771 | return "mach-o-x86-64"; | |
11772 | } | |
11773 | else | |
11774 | return "mach-o-i386"; | |
4c63da97 | 11775 | #endif |
252b5132 RH |
11776 | default: |
11777 | abort (); | |
11778 | return NULL; | |
11779 | } | |
11780 | } | |
11781 | ||
47926f60 | 11782 | #endif /* OBJ_MAYBE_ more than one */ |
252b5132 | 11783 | \f |
252b5132 | 11784 | symbolS * |
7016a5d5 | 11785 | md_undefined_symbol (char *name) |
252b5132 | 11786 | { |
18dc2407 ILT |
11787 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
11788 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
11789 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
11790 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
11791 | { |
11792 | if (!GOT_symbol) | |
11793 | { | |
11794 | if (symbol_find (name)) | |
11795 | as_bad (_("GOT already in symbol table")); | |
11796 | GOT_symbol = symbol_new (name, undefined_section, | |
11797 | (valueT) 0, &zero_address_frag); | |
11798 | }; | |
11799 | return GOT_symbol; | |
11800 | } | |
252b5132 RH |
11801 | return 0; |
11802 | } | |
11803 | ||
11804 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 11805 | |
252b5132 | 11806 | valueT |
7016a5d5 | 11807 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
252b5132 | 11808 | { |
4c63da97 AM |
11809 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
11810 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
11811 | { | |
11812 | /* For a.out, force the section size to be aligned. If we don't do | |
11813 | this, BFD will align it for us, but it will not write out the | |
11814 | final bytes of the section. This may be a bug in BFD, but it is | |
11815 | easier to fix it here since that is how the other a.out targets | |
11816 | work. */ | |
11817 | int align; | |
11818 | ||
11819 | align = bfd_get_section_alignment (stdoutput, segment); | |
8d3842cd | 11820 | size = ((size + (1 << align) - 1) & (-((valueT) 1 << align))); |
4c63da97 | 11821 | } |
252b5132 RH |
11822 | #endif |
11823 | ||
11824 | return size; | |
11825 | } | |
11826 | ||
11827 | /* On the i386, PC-relative offsets are relative to the start of the | |
11828 | next instruction. That is, the address of the offset, plus its | |
11829 | size, since the offset is always the last part of the insn. */ | |
11830 | ||
11831 | long | |
e3bb37b5 | 11832 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
11833 | { |
11834 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
11835 | } | |
11836 | ||
11837 | #ifndef I386COFF | |
11838 | ||
11839 | static void | |
e3bb37b5 | 11840 | s_bss (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 11841 | { |
29b0f896 | 11842 | int temp; |
252b5132 | 11843 | |
8a75718c JB |
11844 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
11845 | if (IS_ELF) | |
11846 | obj_elf_section_change_hook (); | |
11847 | #endif | |
252b5132 RH |
11848 | temp = get_absolute_expression (); |
11849 | subseg_set (bss_section, (subsegT) temp); | |
11850 | demand_empty_rest_of_line (); | |
11851 | } | |
11852 | ||
11853 | #endif | |
11854 | ||
252b5132 | 11855 | void |
e3bb37b5 | 11856 | i386_validate_fix (fixS *fixp) |
252b5132 | 11857 | { |
02a86693 | 11858 | if (fixp->fx_subsy) |
252b5132 | 11859 | { |
02a86693 | 11860 | if (fixp->fx_subsy == GOT_symbol) |
23df1078 | 11861 | { |
02a86693 L |
11862 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
11863 | { | |
11864 | if (!object_64bit) | |
11865 | abort (); | |
11866 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
11867 | if (fixp->fx_tcbit2) | |
56ceb5b5 L |
11868 | fixp->fx_r_type = (fixp->fx_tcbit |
11869 | ? BFD_RELOC_X86_64_REX_GOTPCRELX | |
11870 | : BFD_RELOC_X86_64_GOTPCRELX); | |
02a86693 L |
11871 | else |
11872 | #endif | |
11873 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
11874 | } | |
d6ab8113 | 11875 | else |
02a86693 L |
11876 | { |
11877 | if (!object_64bit) | |
11878 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
11879 | else | |
11880 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; | |
11881 | } | |
11882 | fixp->fx_subsy = 0; | |
23df1078 | 11883 | } |
252b5132 | 11884 | } |
02a86693 L |
11885 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
11886 | else if (!object_64bit) | |
11887 | { | |
11888 | if (fixp->fx_r_type == BFD_RELOC_386_GOT32 | |
11889 | && fixp->fx_tcbit2) | |
11890 | fixp->fx_r_type = BFD_RELOC_386_GOT32X; | |
11891 | } | |
11892 | #endif | |
252b5132 RH |
11893 | } |
11894 | ||
252b5132 | 11895 | arelent * |
7016a5d5 | 11896 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
11897 | { |
11898 | arelent *rel; | |
11899 | bfd_reloc_code_real_type code; | |
11900 | ||
11901 | switch (fixp->fx_r_type) | |
11902 | { | |
8ce3d284 | 11903 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
11904 | case BFD_RELOC_SIZE32: |
11905 | case BFD_RELOC_SIZE64: | |
11906 | if (S_IS_DEFINED (fixp->fx_addsy) | |
11907 | && !S_IS_EXTERNAL (fixp->fx_addsy)) | |
11908 | { | |
11909 | /* Resolve size relocation against local symbol to size of | |
11910 | the symbol plus addend. */ | |
11911 | valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset; | |
11912 | if (fixp->fx_r_type == BFD_RELOC_SIZE32 | |
11913 | && !fits_in_unsigned_long (value)) | |
11914 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
11915 | _("symbol size computation overflow")); | |
11916 | fixp->fx_addsy = NULL; | |
11917 | fixp->fx_subsy = NULL; | |
11918 | md_apply_fix (fixp, (valueT *) &value, NULL); | |
11919 | return NULL; | |
11920 | } | |
8ce3d284 | 11921 | #endif |
1a0670f3 | 11922 | /* Fall through. */ |
8fd4256d | 11923 | |
3e73aa7c JH |
11924 | case BFD_RELOC_X86_64_PLT32: |
11925 | case BFD_RELOC_X86_64_GOT32: | |
11926 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
11927 | case BFD_RELOC_X86_64_GOTPCRELX: |
11928 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
252b5132 RH |
11929 | case BFD_RELOC_386_PLT32: |
11930 | case BFD_RELOC_386_GOT32: | |
02a86693 | 11931 | case BFD_RELOC_386_GOT32X: |
252b5132 RH |
11932 | case BFD_RELOC_386_GOTOFF: |
11933 | case BFD_RELOC_386_GOTPC: | |
13ae64f3 JJ |
11934 | case BFD_RELOC_386_TLS_GD: |
11935 | case BFD_RELOC_386_TLS_LDM: | |
11936 | case BFD_RELOC_386_TLS_LDO_32: | |
11937 | case BFD_RELOC_386_TLS_IE_32: | |
37e55690 JJ |
11938 | case BFD_RELOC_386_TLS_IE: |
11939 | case BFD_RELOC_386_TLS_GOTIE: | |
13ae64f3 JJ |
11940 | case BFD_RELOC_386_TLS_LE_32: |
11941 | case BFD_RELOC_386_TLS_LE: | |
67a4f2b7 AO |
11942 | case BFD_RELOC_386_TLS_GOTDESC: |
11943 | case BFD_RELOC_386_TLS_DESC_CALL: | |
bffbf940 JJ |
11944 | case BFD_RELOC_X86_64_TLSGD: |
11945 | case BFD_RELOC_X86_64_TLSLD: | |
11946 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 11947 | case BFD_RELOC_X86_64_DTPOFF64: |
bffbf940 JJ |
11948 | case BFD_RELOC_X86_64_GOTTPOFF: |
11949 | case BFD_RELOC_X86_64_TPOFF32: | |
d6ab8113 JB |
11950 | case BFD_RELOC_X86_64_TPOFF64: |
11951 | case BFD_RELOC_X86_64_GOTOFF64: | |
11952 | case BFD_RELOC_X86_64_GOTPC32: | |
7b81dfbb AJ |
11953 | case BFD_RELOC_X86_64_GOT64: |
11954 | case BFD_RELOC_X86_64_GOTPCREL64: | |
11955 | case BFD_RELOC_X86_64_GOTPC64: | |
11956 | case BFD_RELOC_X86_64_GOTPLT64: | |
11957 | case BFD_RELOC_X86_64_PLTOFF64: | |
67a4f2b7 AO |
11958 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
11959 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
252b5132 RH |
11960 | case BFD_RELOC_RVA: |
11961 | case BFD_RELOC_VTABLE_ENTRY: | |
11962 | case BFD_RELOC_VTABLE_INHERIT: | |
6482c264 NC |
11963 | #ifdef TE_PE |
11964 | case BFD_RELOC_32_SECREL: | |
11965 | #endif | |
252b5132 RH |
11966 | code = fixp->fx_r_type; |
11967 | break; | |
dbbaec26 L |
11968 | case BFD_RELOC_X86_64_32S: |
11969 | if (!fixp->fx_pcrel) | |
11970 | { | |
11971 | /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ | |
11972 | code = fixp->fx_r_type; | |
11973 | break; | |
11974 | } | |
1a0670f3 | 11975 | /* Fall through. */ |
252b5132 | 11976 | default: |
93382f6d | 11977 | if (fixp->fx_pcrel) |
252b5132 | 11978 | { |
93382f6d AM |
11979 | switch (fixp->fx_size) |
11980 | { | |
11981 | default: | |
b091f402 AM |
11982 | as_bad_where (fixp->fx_file, fixp->fx_line, |
11983 | _("can not do %d byte pc-relative relocation"), | |
11984 | fixp->fx_size); | |
93382f6d AM |
11985 | code = BFD_RELOC_32_PCREL; |
11986 | break; | |
11987 | case 1: code = BFD_RELOC_8_PCREL; break; | |
11988 | case 2: code = BFD_RELOC_16_PCREL; break; | |
d258b828 | 11989 | case 4: code = BFD_RELOC_32_PCREL; break; |
d6ab8113 JB |
11990 | #ifdef BFD64 |
11991 | case 8: code = BFD_RELOC_64_PCREL; break; | |
11992 | #endif | |
93382f6d AM |
11993 | } |
11994 | } | |
11995 | else | |
11996 | { | |
11997 | switch (fixp->fx_size) | |
11998 | { | |
11999 | default: | |
b091f402 AM |
12000 | as_bad_where (fixp->fx_file, fixp->fx_line, |
12001 | _("can not do %d byte relocation"), | |
12002 | fixp->fx_size); | |
93382f6d AM |
12003 | code = BFD_RELOC_32; |
12004 | break; | |
12005 | case 1: code = BFD_RELOC_8; break; | |
12006 | case 2: code = BFD_RELOC_16; break; | |
12007 | case 4: code = BFD_RELOC_32; break; | |
937149dd | 12008 | #ifdef BFD64 |
3e73aa7c | 12009 | case 8: code = BFD_RELOC_64; break; |
937149dd | 12010 | #endif |
93382f6d | 12011 | } |
252b5132 RH |
12012 | } |
12013 | break; | |
12014 | } | |
252b5132 | 12015 | |
d182319b JB |
12016 | if ((code == BFD_RELOC_32 |
12017 | || code == BFD_RELOC_32_PCREL | |
12018 | || code == BFD_RELOC_X86_64_32S) | |
252b5132 RH |
12019 | && GOT_symbol |
12020 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c | 12021 | { |
4fa24527 | 12022 | if (!object_64bit) |
d6ab8113 JB |
12023 | code = BFD_RELOC_386_GOTPC; |
12024 | else | |
12025 | code = BFD_RELOC_X86_64_GOTPC32; | |
3e73aa7c | 12026 | } |
7b81dfbb AJ |
12027 | if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) |
12028 | && GOT_symbol | |
12029 | && fixp->fx_addsy == GOT_symbol) | |
12030 | { | |
12031 | code = BFD_RELOC_X86_64_GOTPC64; | |
12032 | } | |
252b5132 | 12033 | |
add39d23 TS |
12034 | rel = XNEW (arelent); |
12035 | rel->sym_ptr_ptr = XNEW (asymbol *); | |
49309057 | 12036 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
12037 | |
12038 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
c87db184 | 12039 | |
3e73aa7c JH |
12040 | if (!use_rela_relocations) |
12041 | { | |
12042 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
12043 | vtable entry to be used in the relocation's section offset. */ | |
12044 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
12045 | rel->address = fixp->fx_offset; | |
fbeb56a4 DK |
12046 | #if defined (OBJ_COFF) && defined (TE_PE) |
12047 | else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy)) | |
12048 | rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2); | |
12049 | else | |
12050 | #endif | |
c6682705 | 12051 | rel->addend = 0; |
3e73aa7c JH |
12052 | } |
12053 | /* Use the rela in 64bit mode. */ | |
252b5132 | 12054 | else |
3e73aa7c | 12055 | { |
862be3fb L |
12056 | if (disallow_64bit_reloc) |
12057 | switch (code) | |
12058 | { | |
862be3fb L |
12059 | case BFD_RELOC_X86_64_DTPOFF64: |
12060 | case BFD_RELOC_X86_64_TPOFF64: | |
12061 | case BFD_RELOC_64_PCREL: | |
12062 | case BFD_RELOC_X86_64_GOTOFF64: | |
12063 | case BFD_RELOC_X86_64_GOT64: | |
12064 | case BFD_RELOC_X86_64_GOTPCREL64: | |
12065 | case BFD_RELOC_X86_64_GOTPC64: | |
12066 | case BFD_RELOC_X86_64_GOTPLT64: | |
12067 | case BFD_RELOC_X86_64_PLTOFF64: | |
12068 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
12069 | _("cannot represent relocation type %s in x32 mode"), | |
12070 | bfd_get_reloc_code_name (code)); | |
12071 | break; | |
12072 | default: | |
12073 | break; | |
12074 | } | |
12075 | ||
062cd5e7 AS |
12076 | if (!fixp->fx_pcrel) |
12077 | rel->addend = fixp->fx_offset; | |
12078 | else | |
12079 | switch (code) | |
12080 | { | |
12081 | case BFD_RELOC_X86_64_PLT32: | |
12082 | case BFD_RELOC_X86_64_GOT32: | |
12083 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
12084 | case BFD_RELOC_X86_64_GOTPCRELX: |
12085 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
bffbf940 JJ |
12086 | case BFD_RELOC_X86_64_TLSGD: |
12087 | case BFD_RELOC_X86_64_TLSLD: | |
12088 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 AO |
12089 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
12090 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
062cd5e7 AS |
12091 | rel->addend = fixp->fx_offset - fixp->fx_size; |
12092 | break; | |
12093 | default: | |
12094 | rel->addend = (section->vma | |
12095 | - fixp->fx_size | |
12096 | + fixp->fx_addnumber | |
12097 | + md_pcrel_from (fixp)); | |
12098 | break; | |
12099 | } | |
3e73aa7c JH |
12100 | } |
12101 | ||
252b5132 RH |
12102 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
12103 | if (rel->howto == NULL) | |
12104 | { | |
12105 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 12106 | _("cannot represent relocation type %s"), |
252b5132 RH |
12107 | bfd_get_reloc_code_name (code)); |
12108 | /* Set howto to a garbage value so that we can keep going. */ | |
12109 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
9c2799c2 | 12110 | gas_assert (rel->howto != NULL); |
252b5132 RH |
12111 | } |
12112 | ||
12113 | return rel; | |
12114 | } | |
12115 | ||
ee86248c | 12116 | #include "tc-i386-intel.c" |
54cfded0 | 12117 | |
a60de03c JB |
12118 | void |
12119 | tc_x86_parse_to_dw2regnum (expressionS *exp) | |
54cfded0 | 12120 | { |
a60de03c JB |
12121 | int saved_naked_reg; |
12122 | char saved_register_dot; | |
54cfded0 | 12123 | |
a60de03c JB |
12124 | saved_naked_reg = allow_naked_reg; |
12125 | allow_naked_reg = 1; | |
12126 | saved_register_dot = register_chars['.']; | |
12127 | register_chars['.'] = '.'; | |
12128 | allow_pseudo_reg = 1; | |
12129 | expression_and_evaluate (exp); | |
12130 | allow_pseudo_reg = 0; | |
12131 | register_chars['.'] = saved_register_dot; | |
12132 | allow_naked_reg = saved_naked_reg; | |
12133 | ||
e96d56a1 | 12134 | if (exp->X_op == O_register && exp->X_add_number >= 0) |
54cfded0 | 12135 | { |
a60de03c JB |
12136 | if ((addressT) exp->X_add_number < i386_regtab_size) |
12137 | { | |
12138 | exp->X_op = O_constant; | |
12139 | exp->X_add_number = i386_regtab[exp->X_add_number] | |
12140 | .dw2_regnum[flag_code >> 1]; | |
12141 | } | |
12142 | else | |
12143 | exp->X_op = O_illegal; | |
54cfded0 | 12144 | } |
54cfded0 AM |
12145 | } |
12146 | ||
12147 | void | |
12148 | tc_x86_frame_initial_instructions (void) | |
12149 | { | |
a60de03c JB |
12150 | static unsigned int sp_regno[2]; |
12151 | ||
12152 | if (!sp_regno[flag_code >> 1]) | |
12153 | { | |
12154 | char *saved_input = input_line_pointer; | |
12155 | char sp[][4] = {"esp", "rsp"}; | |
12156 | expressionS exp; | |
a4447b93 | 12157 | |
a60de03c JB |
12158 | input_line_pointer = sp[flag_code >> 1]; |
12159 | tc_x86_parse_to_dw2regnum (&exp); | |
9c2799c2 | 12160 | gas_assert (exp.X_op == O_constant); |
a60de03c JB |
12161 | sp_regno[flag_code >> 1] = exp.X_add_number; |
12162 | input_line_pointer = saved_input; | |
12163 | } | |
a4447b93 | 12164 | |
61ff971f L |
12165 | cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment); |
12166 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); | |
54cfded0 | 12167 | } |
d2b2c203 | 12168 | |
d7921315 L |
12169 | int |
12170 | x86_dwarf2_addr_size (void) | |
12171 | { | |
12172 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) | |
12173 | if (x86_elf_abi == X86_64_X32_ABI) | |
12174 | return 4; | |
12175 | #endif | |
12176 | return bfd_arch_bits_per_address (stdoutput) / 8; | |
12177 | } | |
12178 | ||
d2b2c203 DJ |
12179 | int |
12180 | i386_elf_section_type (const char *str, size_t len) | |
12181 | { | |
12182 | if (flag_code == CODE_64BIT | |
12183 | && len == sizeof ("unwind") - 1 | |
12184 | && strncmp (str, "unwind", 6) == 0) | |
12185 | return SHT_X86_64_UNWIND; | |
12186 | ||
12187 | return -1; | |
12188 | } | |
bb41ade5 | 12189 | |
ad5fec3b EB |
12190 | #ifdef TE_SOLARIS |
12191 | void | |
12192 | i386_solaris_fix_up_eh_frame (segT sec) | |
12193 | { | |
12194 | if (flag_code == CODE_64BIT) | |
12195 | elf_section_type (sec) = SHT_X86_64_UNWIND; | |
12196 | } | |
12197 | #endif | |
12198 | ||
bb41ade5 AM |
12199 | #ifdef TE_PE |
12200 | void | |
12201 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) | |
12202 | { | |
91d6fa6a | 12203 | expressionS exp; |
bb41ade5 | 12204 | |
91d6fa6a NC |
12205 | exp.X_op = O_secrel; |
12206 | exp.X_add_symbol = symbol; | |
12207 | exp.X_add_number = 0; | |
12208 | emit_expr (&exp, size); | |
bb41ade5 AM |
12209 | } |
12210 | #endif | |
3b22753a L |
12211 | |
12212 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
12213 | /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ | |
12214 | ||
01e1a5bc | 12215 | bfd_vma |
6d4af3c2 | 12216 | x86_64_section_letter (int letter, const char **ptr_msg) |
3b22753a L |
12217 | { |
12218 | if (flag_code == CODE_64BIT) | |
12219 | { | |
12220 | if (letter == 'l') | |
12221 | return SHF_X86_64_LARGE; | |
12222 | ||
8f3bae45 | 12223 | *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string"); |
64e74474 | 12224 | } |
3b22753a | 12225 | else |
8f3bae45 | 12226 | *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string"); |
3b22753a L |
12227 | return -1; |
12228 | } | |
12229 | ||
01e1a5bc | 12230 | bfd_vma |
3b22753a L |
12231 | x86_64_section_word (char *str, size_t len) |
12232 | { | |
8620418b | 12233 | if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large")) |
3b22753a L |
12234 | return SHF_X86_64_LARGE; |
12235 | ||
12236 | return -1; | |
12237 | } | |
12238 | ||
12239 | static void | |
12240 | handle_large_common (int small ATTRIBUTE_UNUSED) | |
12241 | { | |
12242 | if (flag_code != CODE_64BIT) | |
12243 | { | |
12244 | s_comm_internal (0, elf_common_parse); | |
12245 | as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); | |
12246 | } | |
12247 | else | |
12248 | { | |
12249 | static segT lbss_section; | |
12250 | asection *saved_com_section_ptr = elf_com_section_ptr; | |
12251 | asection *saved_bss_section = bss_section; | |
12252 | ||
12253 | if (lbss_section == NULL) | |
12254 | { | |
12255 | flagword applicable; | |
12256 | segT seg = now_seg; | |
12257 | subsegT subseg = now_subseg; | |
12258 | ||
12259 | /* The .lbss section is for local .largecomm symbols. */ | |
12260 | lbss_section = subseg_new (".lbss", 0); | |
12261 | applicable = bfd_applicable_section_flags (stdoutput); | |
12262 | bfd_set_section_flags (stdoutput, lbss_section, | |
12263 | applicable & SEC_ALLOC); | |
12264 | seg_info (lbss_section)->bss = 1; | |
12265 | ||
12266 | subseg_set (seg, subseg); | |
12267 | } | |
12268 | ||
12269 | elf_com_section_ptr = &_bfd_elf_large_com_section; | |
12270 | bss_section = lbss_section; | |
12271 | ||
12272 | s_comm_internal (0, elf_common_parse); | |
12273 | ||
12274 | elf_com_section_ptr = saved_com_section_ptr; | |
12275 | bss_section = saved_bss_section; | |
12276 | } | |
12277 | } | |
12278 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |