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[deliverable/binutils-gdb.git] / gas / config / tc-i386.c
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252b5132 1/* i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
5db1645b 3 2000, 2001, 2002
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
47926f60
KH		 26 Bugs & suggestions are completely welcome. This is free software.
27 Please help us make it better. */
252b5132 28
252b5132 29#include "as.h"
3882b010 30#include "safe-ctype.h"
252b5132 31#include "subsegs.h"
316e2c05 32#include "dwarf2dbg.h"
252b5132
RH		 33#include "opcode/i386.h"
34
252b5132
RH		 35#ifndef REGISTER_WARNINGS
36#define REGISTER_WARNINGS 1
37#endif
38
c3332e24 39#ifndef INFER_ADDR_PREFIX
eecb386c 40#define INFER_ADDR_PREFIX 1
c3332e24
AM		 41#endif
42
252b5132
RH		 43#ifndef SCALE1_WHEN_NO_INDEX
44/* Specifying a scale factor besides 1 when there is no index is
45 futile. eg. `mov (%ebx,2),%al' does exactly the same as
46 `mov (%ebx),%al'. To slavishly follow what the programmer
47 specified, set SCALE1_WHEN_NO_INDEX to 0. */
48#define SCALE1_WHEN_NO_INDEX 1
49#endif
50
29b0f896
AM		 51#ifdef BFD_ASSEMBLER
52#define RELOC_ENUM enum bfd_reloc_code_real
53#else
54#define RELOC_ENUM int
246fcdee 55#endif
29b0f896
AM		 56
57#ifndef DEFAULT_ARCH
58#define DEFAULT_ARCH "i386"
246fcdee 59#endif
252b5132 60
edde18a5
AM		 61#ifndef INLINE
62#if __GNUC__ >= 2
63#define INLINE __inline__
64#else
65#define INLINE
66#endif
67#endif
68
29b0f896
AM		 69static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
70static INLINE int fits_in_signed_byte PARAMS ((offsetT));
71static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
72static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
73static INLINE int fits_in_signed_word PARAMS ((offsetT));
74static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
75static INLINE int fits_in_signed_long PARAMS ((offsetT));
847f7ad4
AM		 76static int smallest_imm_type PARAMS ((offsetT));
77static offsetT offset_in_range PARAMS ((offsetT, int));
252b5132 78static int add_prefix PARAMS ((unsigned int));
3e73aa7c 79static void set_code_flag PARAMS ((int));
47926f60 80static void set_16bit_gcc_code_flag PARAMS ((int));
252b5132 81static void set_intel_syntax PARAMS ((int));
e413e4e9 82static void set_cpu_arch PARAMS ((int));
29b0f896
AM		 83static char *output_invalid PARAMS ((int c));
84static int i386_operand PARAMS ((char *operand_string));
85static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
86static const reg_entry *parse_register PARAMS ((char *reg_string,
87 char **end_op));
88static char *parse_insn PARAMS ((char *, char *));
89static char *parse_operands PARAMS ((char *, const char *));
90static void swap_operands PARAMS ((void));
91static void optimize_imm PARAMS ((void));
92static void optimize_disp PARAMS ((void));
93static int match_template PARAMS ((void));
94static int check_string PARAMS ((void));
95static int process_suffix PARAMS ((void));
96static int check_byte_reg PARAMS ((void));
97static int check_long_reg PARAMS ((void));
98static int check_qword_reg PARAMS ((void));
99static int check_word_reg PARAMS ((void));
100static int finalize_imm PARAMS ((void));
101static int process_operands PARAMS ((void));
102static const seg_entry *build_modrm_byte PARAMS ((void));
103static void output_insn PARAMS ((void));
104static void output_branch PARAMS ((void));
105static void output_jump PARAMS ((void));
106static void output_interseg_jump PARAMS ((void));
107static void output_imm PARAMS ((void));
108static void output_disp PARAMS ((void));
109#ifndef I386COFF
110static void s_bss PARAMS ((int));
252b5132
RH		 111#endif
112
a847613f 113static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 114
252b5132 115/* 'md_assemble ()' gathers together information and puts it into a
47926f60 116 i386_insn. */
252b5132 117
520dc8e8
AM		 118union i386_op
119 {
120 expressionS *disps;
121 expressionS *imms;
122 const reg_entry *regs;
123 };
124
252b5132
RH		 125struct _i386_insn
126 {
47926f60 127 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 128 template tm;
129
130 /* SUFFIX holds the instruction mnemonic suffix if given.
131 (e.g. 'l' for 'movl') */
132 char suffix;
133
47926f60 134 /* OPERANDS gives the number of given operands. */
252b5132
RH		 135 unsigned int operands;
136
137 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
138 of given register, displacement, memory operands and immediate
47926f60 139 operands. */
252b5132
RH		 140 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
141
142 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 143 use OP[i] for the corresponding operand. */
252b5132
RH		 144 unsigned int types[MAX_OPERANDS];
145
520dc8e8
AM		 146 /* Displacement expression, immediate expression, or register for each
147 operand. */
148 union i386_op op[MAX_OPERANDS];
252b5132 149
3e73aa7c
JH		 150 /* Flags for operands. */
151 unsigned int flags[MAX_OPERANDS];
152#define Operand_PCrel 1
153
252b5132 154 /* Relocation type for operand */
f3c180ae 155 RELOC_ENUM reloc[MAX_OPERANDS];
252b5132 156
252b5132
RH		 157 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
158 the base index byte below. */
159 const reg_entry *base_reg;
160 const reg_entry *index_reg;
161 unsigned int log2_scale_factor;
162
163 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 164 explicit segment overrides are given. */
ce8a8b2f 165 const seg_entry *seg[2];
252b5132
RH		 166
167 /* PREFIX holds all the given prefix opcodes (usually null).
168 PREFIXES is the number of prefix opcodes. */
169 unsigned int prefixes;
170 unsigned char prefix[MAX_PREFIXES];
171
172 /* RM and SIB are the modrm byte and the sib byte where the
173 addressing modes of this insn are encoded. */
174
175 modrm_byte rm;
3e73aa7c 176 rex_byte rex;
252b5132
RH		 177 sib_byte sib;
178 };
179
180typedef struct _i386_insn i386_insn;
181
182/* List of chars besides those in app.c:symbol_chars that can start an
183 operand. Used to prevent the scrubber eating vital white-space. */
184#ifdef LEX_AT
200dbde8 185const char extra_symbol_chars[] = "*%-(@[";
252b5132 186#else
200dbde8 187const char extra_symbol_chars[] = "*%-([";
252b5132
RH		 188#endif
189
29b0f896
AM		 190#if (defined (TE_I386AIX) \
191 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
192 && !defined (TE_LINUX) \
193 && !defined (TE_FreeBSD) \
194 && !defined (TE_NetBSD)))
252b5132 195/* This array holds the chars that always start a comment. If the
ce8a8b2f 196 pre-processor is disabled, these aren't very useful. */
252b5132
RH		 197const char comment_chars[] = "#/";
198#define PREFIX_SEPARATOR '\\'
252b5132
RH		 199
200/* This array holds the chars that only start a comment at the beginning of
201 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 202 .line and .file directives will appear in the pre-processed output.
203 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 204 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 205 #NO_APP at the beginning of its output.
206 Also note that comments started like this one will always work if
252b5132 207 '/' isn't otherwise defined. */
252b5132 208const char line_comment_chars[] = "";
29b0f896 209
252b5132 210#else
29b0f896
AM		 211/* Putting '/' here makes it impossible to use the divide operator.
212 However, we need it for compatibility with SVR4 systems. */
213const char comment_chars[] = "#";
214#define PREFIX_SEPARATOR '/'
215
252b5132
RH		 216const char line_comment_chars[] = "/";
217#endif
218
63a0b638 219const char line_separator_chars[] = ";";
252b5132 220
ce8a8b2f
AM		 221/* Chars that can be used to separate mant from exp in floating point
222 nums. */
252b5132
RH		 223const char EXP_CHARS[] = "eE";
224
ce8a8b2f
AM		 225/* Chars that mean this number is a floating point constant
226 As in 0f12.456
227 or 0d1.2345e12. */
252b5132
RH		 228const char FLT_CHARS[] = "fFdDxX";
229
ce8a8b2f 230/* Tables for lexical analysis. */
252b5132
RH		 231static char mnemonic_chars[256];
232static char register_chars[256];
233static char operand_chars[256];
234static char identifier_chars[256];
235static char digit_chars[256];
236
ce8a8b2f 237/* Lexical macros. */
252b5132
RH		 238#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
239#define is_operand_char(x) (operand_chars[(unsigned char) x])
240#define is_register_char(x) (register_chars[(unsigned char) x])
241#define is_space_char(x) ((x) == ' ')
242#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
243#define is_digit_char(x) (digit_chars[(unsigned char) x])
244
ce8a8b2f 245/* All non-digit non-letter charcters that may occur in an operand. */
252b5132
RH		 246static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
247
248/* md_assemble() always leaves the strings it's passed unaltered. To
249 effect this we maintain a stack of saved characters that we've smashed
250 with '\0's (indicating end of strings for various sub-fields of the
47926f60 251 assembler instruction). */
252b5132 252static char save_stack[32];
ce8a8b2f 253static char *save_stack_p;
252b5132
RH		 254#define END_STRING_AND_SAVE(s) \
255 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
256#define RESTORE_END_STRING(s) \
257 do { *(s) = *--save_stack_p; } while (0)
258
47926f60 259/* The instruction we're assembling. */
252b5132
RH		 260static i386_insn i;
261
262/* Possible templates for current insn. */
263static const templates *current_templates;
264
47926f60 265/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
252b5132
RH		 266static expressionS disp_expressions[2], im_expressions[2];
267
47926f60
KH		 268/* Current operand we are working on. */
269static int this_operand;
252b5132 270
3e73aa7c
JH		 271/* We support four different modes. FLAG_CODE variable is used to distinguish
272 these. */
273
274enum flag_code {
275 CODE_32BIT,
276 CODE_16BIT,
277 CODE_64BIT };
f3c180ae 278#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 279
280static enum flag_code flag_code;
281static int use_rela_relocations = 0;
282
283/* The names used to print error messages. */
b77a7acd 284static const char *flag_code_names[] =
3e73aa7c
JH		 285 {
286 "32",
287 "16",
288 "64"
289 };
252b5132 290
47926f60
KH		 291/* 1 for intel syntax,
292 0 if att syntax. */
293static int intel_syntax = 0;
252b5132 294
47926f60
KH		 295/* 1 if register prefix % not required. */
296static int allow_naked_reg = 0;
252b5132 297
47926f60
KH		 298/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
299 leave, push, and pop instructions so that gcc has the same stack
300 frame as in 32 bit mode. */
301static char stackop_size = '\0';
eecb386c 302
47926f60
KH		 303/* Non-zero to quieten some warnings. */
304static int quiet_warnings = 0;
a38cf1db 305
47926f60
KH		 306/* CPU name. */
307static const char *cpu_arch_name = NULL;
a38cf1db 308
47926f60 309/* CPU feature flags. */
29b0f896 310static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 311
fddf5b5b
AM		 312/* If set, conditional jumps are not automatically promoted to handle
313 larger than a byte offset. */
314static unsigned int no_cond_jump_promotion = 0;
315
29b0f896
AM		 316/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
317symbolS *GOT_symbol;
318
252b5132 319/* Interface to relax_segment.
fddf5b5b
AM		 320 There are 3 major relax states for 386 jump insns because the
321 different types of jumps add different sizes to frags when we're
322 figuring out what sort of jump to choose to reach a given label. */
252b5132 323
47926f60 324/* Types. */
93c2a809
AM		 325#define UNCOND_JUMP 0
326#define COND_JUMP 1
327#define COND_JUMP86 2
fddf5b5b 328
47926f60 329/* Sizes. */
252b5132
RH		 330#define CODE16 1
331#define SMALL 0
29b0f896 332#define SMALL16 (SMALL | CODE16)
252b5132 333#define BIG 2
29b0f896 334#define BIG16 (BIG | CODE16)
252b5132
RH		 335
336#ifndef INLINE
337#ifdef __GNUC__
338#define INLINE __inline__
339#else
340#define INLINE
341#endif
342#endif
343
fddf5b5b
AM		 344#define ENCODE_RELAX_STATE(type, size) \
345 ((relax_substateT) (((type) << 2) | (size)))
346#define TYPE_FROM_RELAX_STATE(s) \
347 ((s) >> 2)
348#define DISP_SIZE_FROM_RELAX_STATE(s) \
349 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 350
351/* This table is used by relax_frag to promote short jumps to long
352 ones where necessary. SMALL (short) jumps may be promoted to BIG
353 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
354 don't allow a short jump in a 32 bit code segment to be promoted to
355 a 16 bit offset jump because it's slower (requires data size
356 prefix), and doesn't work, unless the destination is in the bottom
357 64k of the code segment (The top 16 bits of eip are zeroed). */
358
359const relax_typeS md_relax_table[] =
360{
24eab124
AM		 361 /* The fields are:
362 1) most positive reach of this state,
363 2) most negative reach of this state,
93c2a809 364 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 365 4) which index into the table to try if we can't fit into this one. */
252b5132 366
fddf5b5b 367 /* UNCOND_JUMP states. */
93c2a809
AM		 368 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
369 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
370 /* dword jmp adds 4 bytes to frag:
371 0 extra opcode bytes, 4 displacement bytes. */
252b5132 372 {0, 0, 4, 0},
93c2a809
AM		 373 /* word jmp adds 2 byte2 to frag:
374 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 375 {0, 0, 2, 0},
376
93c2a809
AM		 377 /* COND_JUMP states. */
378 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
379 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
380 /* dword conditionals adds 5 bytes to frag:
381 1 extra opcode byte, 4 displacement bytes. */
382 {0, 0, 5, 0},
fddf5b5b 383 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 384 1 extra opcode byte, 2 displacement bytes. */
385 {0, 0, 3, 0},
386
387 /* COND_JUMP86 states. */
388 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
389 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
390 /* dword conditionals adds 5 bytes to frag:
391 1 extra opcode byte, 4 displacement bytes. */
392 {0, 0, 5, 0},
393 /* word conditionals add 4 bytes to frag:
394 1 displacement byte and a 3 byte long branch insn. */
395 {0, 0, 4, 0}
252b5132
RH		 396};
397
e413e4e9
AM		 398static const arch_entry cpu_arch[] = {
399 {"i8086", Cpu086 },
400 {"i186", Cpu086|Cpu186 },
401 {"i286", Cpu086|Cpu186|Cpu286 },
402 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
403 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
404 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
405 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
406 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
407 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
a167610d 408 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2 },
3e73aa7c
JH		 409 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
410 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|Cpu3dnow },
a167610d 411 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|Cpu3dnow|CpuSSE|CpuSSE2 },
e413e4e9
AM		 412 {NULL, 0 }
413};
414
29b0f896
AM		 415const pseudo_typeS md_pseudo_table[] =
416{
417#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
418 {"align", s_align_bytes, 0},
419#else
420 {"align", s_align_ptwo, 0},
421#endif
422 {"arch", set_cpu_arch, 0},
423#ifndef I386COFF
424 {"bss", s_bss, 0},
425#endif
426 {"ffloat", float_cons, 'f'},
427 {"dfloat", float_cons, 'd'},
428 {"tfloat", float_cons, 'x'},
429 {"value", cons, 2},
430 {"noopt", s_ignore, 0},
431 {"optim", s_ignore, 0},
432 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
433 {"code16", set_code_flag, CODE_16BIT},
434 {"code32", set_code_flag, CODE_32BIT},
435 {"code64", set_code_flag, CODE_64BIT},
436 {"intel_syntax", set_intel_syntax, 1},
437 {"att_syntax", set_intel_syntax, 0},
c6682705 438 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
29b0f896
AM		 439 {"loc", dwarf2_directive_loc, 0},
440 {0, 0, 0}
441};
442
443/* For interface with expression (). */
444extern char *input_line_pointer;
445
446/* Hash table for instruction mnemonic lookup. */
447static struct hash_control *op_hash;
448
449/* Hash table for register lookup. */
450static struct hash_control *reg_hash;
451\f
252b5132
RH		 452void
453i386_align_code (fragP, count)
454 fragS *fragP;
455 int count;
456{
ce8a8b2f
AM		 457 /* Various efficient no-op patterns for aligning code labels.
458 Note: Don't try to assemble the instructions in the comments.
459 0L and 0w are not legal. */
252b5132
RH		 460 static const char f32_1[] =
461 {0x90}; /* nop */
462 static const char f32_2[] =
463 {0x89,0xf6}; /* movl %esi,%esi */
464 static const char f32_3[] =
465 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
466 static const char f32_4[] =
467 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
468 static const char f32_5[] =
469 {0x90, /* nop */
470 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
471 static const char f32_6[] =
472 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
473 static const char f32_7[] =
474 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
475 static const char f32_8[] =
476 {0x90, /* nop */
477 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
478 static const char f32_9[] =
479 {0x89,0xf6, /* movl %esi,%esi */
480 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
481 static const char f32_10[] =
482 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
483 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
484 static const char f32_11[] =
485 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
486 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
487 static const char f32_12[] =
488 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
489 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
490 static const char f32_13[] =
491 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
492 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
493 static const char f32_14[] =
494 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
495 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
496 static const char f32_15[] =
497 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
498 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 499 static const char f16_3[] =
500 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 501 static const char f16_4[] =
502 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
503 static const char f16_5[] =
504 {0x90, /* nop */
505 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
506 static const char f16_6[] =
507 {0x89,0xf6, /* mov %si,%si */
508 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
509 static const char f16_7[] =
510 {0x8d,0x74,0x00, /* lea 0(%si),%si */
511 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
512 static const char f16_8[] =
513 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
514 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
515 static const char *const f32_patt[] = {
516 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
517 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
518 };
519 static const char *const f16_patt[] = {
c3332e24 520 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 521 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
522 };
523
33fef721
JH		 524 if (count <= 0 || count > 15)
525 return;
3e73aa7c 526
33fef721
JH		 527 /* The recommended way to pad 64bit code is to use NOPs preceded by
528 maximally four 0x66 prefixes. Balance the size of nops. */
529 if (flag_code == CODE_64BIT)
252b5132 530 {
33fef721
JH		 531 int i;
532 int nnops = (count + 3) / 4;
533 int len = count / nnops;
534 int remains = count - nnops * len;
535 int pos = 0;
536
537 for (i = 0; i < remains; i++)
252b5132 538 {
33fef721
JH		 539 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
540 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
541 pos += len + 1;
542 }
543 for (; i < nnops; i++)
544 {
545 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
546 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
547 pos += len;
252b5132 548 }
252b5132 549 }
33fef721
JH		 550 else
551 if (flag_code == CODE_16BIT)
552 {
553 memcpy (fragP->fr_literal + fragP->fr_fix,
554 f16_patt[count - 1], count);
555 if (count > 8)
556 /* Adjust jump offset. */
557 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
558 }
559 else
560 memcpy (fragP->fr_literal + fragP->fr_fix,
561 f32_patt[count - 1], count);
562 fragP->fr_var = count;
252b5132
RH		 563}
564
252b5132
RH		 565static INLINE unsigned int
566mode_from_disp_size (t)
567 unsigned int t;
568{
3e73aa7c 569 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 570}
571
572static INLINE int
573fits_in_signed_byte (num)
847f7ad4 574 offsetT num;
252b5132
RH		 575{
576 return (num >= -128) && (num <= 127);
47926f60 577}
252b5132
RH		 578
579static INLINE int
580fits_in_unsigned_byte (num)
847f7ad4 581 offsetT num;
252b5132
RH		 582{
583 return (num & 0xff) == num;
47926f60 584}
252b5132
RH		 585
586static INLINE int
587fits_in_unsigned_word (num)
847f7ad4 588 offsetT num;
252b5132
RH		 589{
590 return (num & 0xffff) == num;
47926f60 591}
252b5132
RH		 592
593static INLINE int
594fits_in_signed_word (num)
847f7ad4 595 offsetT num;
252b5132
RH		 596{
597 return (-32768 <= num) && (num <= 32767);
47926f60 598}
3e73aa7c
JH		 599static INLINE int
600fits_in_signed_long (num)
601 offsetT num ATTRIBUTE_UNUSED;
602{
603#ifndef BFD64
604 return 1;
605#else
606 return (!(((offsetT) -1 << 31) & num)
607 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
608#endif
609} /* fits_in_signed_long() */
610static INLINE int
611fits_in_unsigned_long (num)
612 offsetT num ATTRIBUTE_UNUSED;
613{
614#ifndef BFD64
615 return 1;
616#else
617 return (num & (((offsetT) 2 << 31) - 1)) == num;
618#endif
619} /* fits_in_unsigned_long() */
252b5132
RH		 620
621static int
622smallest_imm_type (num)
847f7ad4 623 offsetT num;
252b5132 624{
a847613f 625 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 626 {
627 /* This code is disabled on the 486 because all the Imm1 forms
628 in the opcode table are slower on the i486. They're the
629 versions with the implicitly specified single-position
630 displacement, which has another syntax if you really want to
631 use that form. */
632 if (num == 1)
3e73aa7c 633 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 634 }
252b5132 635 return (fits_in_signed_byte (num)
3e73aa7c 636 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 637 : fits_in_unsigned_byte (num)
3e73aa7c 638 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 639 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 640 ? (Imm16 | Imm32 | Imm32S | Imm64)
641 : fits_in_signed_long (num)
642 ? (Imm32 | Imm32S | Imm64)
643 : fits_in_unsigned_long (num)
644 ? (Imm32 | Imm64)
645 : Imm64);
47926f60 646}
252b5132 647
847f7ad4
AM		 648static offsetT
649offset_in_range (val, size)
650 offsetT val;
651 int size;
652{
508866be 653 addressT mask;
ba2adb93 654
847f7ad4
AM		 655 switch (size)
656 {
508866be
L		 657 case 1: mask = ((addressT) 1 << 8) - 1; break;
658 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 659 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 660#ifdef BFD64
661 case 8: mask = ((addressT) 2 << 63) - 1; break;
662#endif
47926f60 663 default: abort ();
847f7ad4
AM		 664 }
665
ba2adb93 666 /* If BFD64, sign extend val. */
3e73aa7c
JH		 667 if (!use_rela_relocations)
668 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
669 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 670
47926f60 671 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 672 {
673 char buf1[40], buf2[40];
674
675 sprint_value (buf1, val);
676 sprint_value (buf2, val & mask);
677 as_warn (_("%s shortened to %s"), buf1, buf2);
678 }
679 return val & mask;
680}
681
252b5132
RH		 682/* Returns 0 if attempting to add a prefix where one from the same
683 class already exists, 1 if non rep/repne added, 2 if rep/repne
684 added. */
685static int
686add_prefix (prefix)
687 unsigned int prefix;
688{
689 int ret = 1;
690 int q;
691
29b0f896
AM		 692 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
693 && flag_code == CODE_64BIT)
3e73aa7c
JH		 694 q = REX_PREFIX;
695 else
696 switch (prefix)
697 {
698 default:
699 abort ();
700
701 case CS_PREFIX_OPCODE:
702 case DS_PREFIX_OPCODE:
703 case ES_PREFIX_OPCODE:
704 case FS_PREFIX_OPCODE:
705 case GS_PREFIX_OPCODE:
706 case SS_PREFIX_OPCODE:
707 q = SEG_PREFIX;
708 break;
252b5132 709
3e73aa7c
JH		 710 case REPNE_PREFIX_OPCODE:
711 case REPE_PREFIX_OPCODE:
712 ret = 2;
713 /* fall thru */
714 case LOCK_PREFIX_OPCODE:
715 q = LOCKREP_PREFIX;
716 break;
252b5132 717
3e73aa7c
JH		 718 case FWAIT_OPCODE:
719 q = WAIT_PREFIX;
720 break;
252b5132 721
3e73aa7c
JH		 722 case ADDR_PREFIX_OPCODE:
723 q = ADDR_PREFIX;
724 break;
252b5132 725
3e73aa7c
JH		 726 case DATA_PREFIX_OPCODE:
727 q = DATA_PREFIX;
728 break;
729 }
252b5132 730
29b0f896 731 if (i.prefix[q] != 0)
252b5132
RH		 732 {
733 as_bad (_("same type of prefix used twice"));
734 return 0;
735 }
736
737 i.prefixes += 1;
738 i.prefix[q] = prefix;
739 return ret;
740}
741
742static void
3e73aa7c 743set_code_flag (value)
e5cb08ac 744 int value;
eecb386c 745{
3e73aa7c
JH		 746 flag_code = value;
747 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
748 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
749 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
750 {
751 as_bad (_("64bit mode not supported on this CPU."));
752 }
753 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
754 {
755 as_bad (_("32bit mode not supported on this CPU."));
756 }
eecb386c
AM		 757 stackop_size = '\0';
758}
759
760static void
3e73aa7c
JH		 761set_16bit_gcc_code_flag (new_code_flag)
762 int new_code_flag;
252b5132 763{
3e73aa7c
JH		 764 flag_code = new_code_flag;
765 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
766 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
767 stackop_size = 'l';
252b5132
RH		 768}
769
770static void
771set_intel_syntax (syntax_flag)
eecb386c 772 int syntax_flag;
252b5132
RH		 773{
774 /* Find out if register prefixing is specified. */
775 int ask_naked_reg = 0;
776
777 SKIP_WHITESPACE ();
29b0f896 778 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 779 {
780 char *string = input_line_pointer;
781 int e = get_symbol_end ();
782
47926f60 783 if (strcmp (string, "prefix") == 0)
252b5132 784 ask_naked_reg = 1;
47926f60 785 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 786 ask_naked_reg = -1;
787 else
d0b47220 788 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 789 *input_line_pointer = e;
790 }
791 demand_empty_rest_of_line ();
c3332e24 792
252b5132
RH		 793 intel_syntax = syntax_flag;
794
795 if (ask_naked_reg == 0)
796 {
797#ifdef BFD_ASSEMBLER
798 allow_naked_reg = (intel_syntax
24eab124 799 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132 800#else
47926f60
KH		 801 /* Conservative default. */
802 allow_naked_reg = 0;
252b5132
RH		 803#endif
804 }
805 else
806 allow_naked_reg = (ask_naked_reg < 0);
807}
808
e413e4e9
AM		 809static void
810set_cpu_arch (dummy)
47926f60 811 int dummy ATTRIBUTE_UNUSED;
e413e4e9 812{
47926f60 813 SKIP_WHITESPACE ();
e413e4e9 814
29b0f896 815 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 816 {
817 char *string = input_line_pointer;
818 int e = get_symbol_end ();
819 int i;
820
821 for (i = 0; cpu_arch[i].name; i++)
822 {
823 if (strcmp (string, cpu_arch[i].name) == 0)
824 {
825 cpu_arch_name = cpu_arch[i].name;
fddf5b5b
AM		 826 cpu_arch_flags = (cpu_arch[i].flags
827 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
e413e4e9
AM		 828 break;
829 }
830 }
831 if (!cpu_arch[i].name)
832 as_bad (_("no such architecture: `%s'"), string);
833
834 *input_line_pointer = e;
835 }
836 else
837 as_bad (_("missing cpu architecture"));
838
fddf5b5b
AM		 839 no_cond_jump_promotion = 0;
840 if (*input_line_pointer == ','
29b0f896 841 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 842 {
843 char *string = ++input_line_pointer;
844 int e = get_symbol_end ();
845
846 if (strcmp (string, "nojumps") == 0)
847 no_cond_jump_promotion = 1;
848 else if (strcmp (string, "jumps") == 0)
849 ;
850 else
851 as_bad (_("no such architecture modifier: `%s'"), string);
852
853 *input_line_pointer = e;
854 }
855
e413e4e9
AM		 856 demand_empty_rest_of_line ();
857}
858
b9d79e03
JH		 859#ifdef BFD_ASSEMBLER
860unsigned long
861i386_mach ()
862{
863 if (!strcmp (default_arch, "x86_64"))
864 return bfd_mach_x86_64;
865 else if (!strcmp (default_arch, "i386"))
866 return bfd_mach_i386_i386;
867 else
868 as_fatal (_("Unknown architecture"));
869}
870#endif
871\f
252b5132
RH		 872void
873md_begin ()
874{
875 const char *hash_err;
876
47926f60 877 /* Initialize op_hash hash table. */
252b5132
RH		 878 op_hash = hash_new ();
879
880 {
29b0f896
AM		 881 const template *optab;
882 templates *core_optab;
252b5132 883
47926f60
KH		 884 /* Setup for loop. */
885 optab = i386_optab;
252b5132
RH		 886 core_optab = (templates *) xmalloc (sizeof (templates));
887 core_optab->start = optab;
888
889 while (1)
890 {
891 ++optab;
892 if (optab->name == NULL
893 || strcmp (optab->name, (optab - 1)->name) != 0)
894 {
895 /* different name --> ship out current template list;
47926f60 896 add to hash table; & begin anew. */
252b5132
RH		 897 core_optab->end = optab;
898 hash_err = hash_insert (op_hash,
899 (optab - 1)->name,
900 (PTR) core_optab);
901 if (hash_err)
902 {
252b5132
RH		 903 as_fatal (_("Internal Error: Can't hash %s: %s"),
904 (optab - 1)->name,
905 hash_err);
906 }
907 if (optab->name == NULL)
908 break;
909 core_optab = (templates *) xmalloc (sizeof (templates));
910 core_optab->start = optab;
911 }
912 }
913 }
914
47926f60 915 /* Initialize reg_hash hash table. */
252b5132
RH		 916 reg_hash = hash_new ();
917 {
29b0f896 918 const reg_entry *regtab;
252b5132
RH		 919
920 for (regtab = i386_regtab;
921 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
922 regtab++)
923 {
924 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
925 if (hash_err)
3e73aa7c
JH		 926 as_fatal (_("Internal Error: Can't hash %s: %s"),
927 regtab->reg_name,
928 hash_err);
252b5132
RH		 929 }
930 }
931
47926f60 932 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 933 {
29b0f896
AM		 934 int c;
935 char *p;
252b5132
RH		 936
937 for (c = 0; c < 256; c++)
938 {
3882b010 939 if (ISDIGIT (c))
252b5132
RH		 940 {
941 digit_chars[c] = c;
942 mnemonic_chars[c] = c;
943 register_chars[c] = c;
944 operand_chars[c] = c;
945 }
3882b010 946 else if (ISLOWER (c))
252b5132
RH		 947 {
948 mnemonic_chars[c] = c;
949 register_chars[c] = c;
950 operand_chars[c] = c;
951 }
3882b010 952 else if (ISUPPER (c))
252b5132 953 {
3882b010 954 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 955 register_chars[c] = mnemonic_chars[c];
956 operand_chars[c] = c;
957 }
958
3882b010 959 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 960 identifier_chars[c] = c;
961 else if (c >= 128)
962 {
963 identifier_chars[c] = c;
964 operand_chars[c] = c;
965 }
966 }
967
968#ifdef LEX_AT
969 identifier_chars['@'] = '@';
970#endif
252b5132
RH		 971 digit_chars['-'] = '-';
972 identifier_chars['_'] = '_';
973 identifier_chars['.'] = '.';
974
975 for (p = operand_special_chars; *p != '\0'; p++)
976 operand_chars[(unsigned char) *p] = *p;
977 }
978
979#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
980 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
981 {
982 record_alignment (text_section, 2);
983 record_alignment (data_section, 2);
984 record_alignment (bss_section, 2);
985 }
986#endif
987}
988
989void
990i386_print_statistics (file)
991 FILE *file;
992{
993 hash_print_statistics (file, "i386 opcode", op_hash);
994 hash_print_statistics (file, "i386 register", reg_hash);
995}
996\f
252b5132
RH		 997#ifdef DEBUG386
998
ce8a8b2f 999/* Debugging routines for md_assemble. */
252b5132
RH		 1000static void pi PARAMS ((char *, i386_insn *));
1001static void pte PARAMS ((template *));
1002static void pt PARAMS ((unsigned int));
1003static void pe PARAMS ((expressionS *));
1004static void ps PARAMS ((symbolS *));
1005
1006static void
1007pi (line, x)
1008 char *line;
1009 i386_insn *x;
1010{
09f131f2 1011 unsigned int i;
252b5132
RH		 1012
1013 fprintf (stdout, "%s: template ", line);
1014 pte (&x->tm);
09f131f2
JH		 1015 fprintf (stdout, " address: base %s index %s scale %x\n",
1016 x->base_reg ? x->base_reg->reg_name : "none",
1017 x->index_reg ? x->index_reg->reg_name : "none",
1018 x->log2_scale_factor);
1019 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1020 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1021 fprintf (stdout, " sib: base %x index %x scale %x\n",
1022 x->sib.base, x->sib.index, x->sib.scale);
1023 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
29b0f896
AM		 1024 (x->rex & REX_MODE64) != 0,
1025 (x->rex & REX_EXTX) != 0,
1026 (x->rex & REX_EXTY) != 0,
1027 (x->rex & REX_EXTZ) != 0);
252b5132
RH		 1028 for (i = 0; i < x->operands; i++)
1029 {
1030 fprintf (stdout, " #%d: ", i + 1);
1031 pt (x->types[i]);
1032 fprintf (stdout, "\n");
1033 if (x->types[i]
3f4438ab 1034 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1035 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1036 if (x->types[i] & Imm)
520dc8e8 1037 pe (x->op[i].imms);
252b5132 1038 if (x->types[i] & Disp)
520dc8e8 1039 pe (x->op[i].disps);
252b5132
RH		 1040 }
1041}
1042
1043static void
1044pte (t)
1045 template *t;
1046{
09f131f2 1047 unsigned int i;
252b5132 1048 fprintf (stdout, " %d operands ", t->operands);
47926f60 1049 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1050 if (t->extension_opcode != None)
1051 fprintf (stdout, "ext %x ", t->extension_opcode);
1052 if (t->opcode_modifier & D)
1053 fprintf (stdout, "D");
1054 if (t->opcode_modifier & W)
1055 fprintf (stdout, "W");
1056 fprintf (stdout, "\n");
1057 for (i = 0; i < t->operands; i++)
1058 {
1059 fprintf (stdout, " #%d type ", i + 1);
1060 pt (t->operand_types[i]);
1061 fprintf (stdout, "\n");
1062 }
1063}
1064
1065static void
1066pe (e)
1067 expressionS *e;
1068{
24eab124 1069 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1070 fprintf (stdout, " add_number %ld (%lx)\n",
1071 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1072 if (e->X_add_symbol)
1073 {
1074 fprintf (stdout, " add_symbol ");
1075 ps (e->X_add_symbol);
1076 fprintf (stdout, "\n");
1077 }
1078 if (e->X_op_symbol)
1079 {
1080 fprintf (stdout, " op_symbol ");
1081 ps (e->X_op_symbol);
1082 fprintf (stdout, "\n");
1083 }
1084}
1085
1086static void
1087ps (s)
1088 symbolS *s;
1089{
1090 fprintf (stdout, "%s type %s%s",
1091 S_GET_NAME (s),
1092 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1093 segment_name (S_GET_SEGMENT (s)));
1094}
1095
1096struct type_name
1097 {
1098 unsigned int mask;
1099 char *tname;
1100 }
1101
29b0f896 1102static const type_names[] =
252b5132
RH		 1103{
1104 { Reg8, "r8" },
1105 { Reg16, "r16" },
1106 { Reg32, "r32" },
09f131f2 1107 { Reg64, "r64" },
252b5132
RH		 1108 { Imm8, "i8" },
1109 { Imm8S, "i8s" },
1110 { Imm16, "i16" },
1111 { Imm32, "i32" },
09f131f2
JH		 1112 { Imm32S, "i32s" },
1113 { Imm64, "i64" },
252b5132
RH		 1114 { Imm1, "i1" },
1115 { BaseIndex, "BaseIndex" },
1116 { Disp8, "d8" },
1117 { Disp16, "d16" },
1118 { Disp32, "d32" },
09f131f2
JH		 1119 { Disp32S, "d32s" },
1120 { Disp64, "d64" },
252b5132
RH		 1121 { InOutPortReg, "InOutPortReg" },
1122 { ShiftCount, "ShiftCount" },
1123 { Control, "control reg" },
1124 { Test, "test reg" },
1125 { Debug, "debug reg" },
1126 { FloatReg, "FReg" },
1127 { FloatAcc, "FAcc" },
1128 { SReg2, "SReg2" },
1129 { SReg3, "SReg3" },
1130 { Acc, "Acc" },
1131 { JumpAbsolute, "Jump Absolute" },
1132 { RegMMX, "rMMX" },
3f4438ab 1133 { RegXMM, "rXMM" },
252b5132
RH		 1134 { EsSeg, "es" },
1135 { 0, "" }
1136};
1137
1138static void
1139pt (t)
1140 unsigned int t;
1141{
29b0f896 1142 const struct type_name *ty;
252b5132 1143
09f131f2
JH		 1144 for (ty = type_names; ty->mask; ty++)
1145 if (t & ty->mask)
1146 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1147 fflush (stdout);
1148}
1149
1150#endif /* DEBUG386 */
1151\f
252b5132 1152#ifdef BFD_ASSEMBLER
29b0f896
AM		 1153static bfd_reloc_code_real_type reloc
1154 PARAMS ((int, int, int, bfd_reloc_code_real_type));
252b5132
RH		 1155
1156static bfd_reloc_code_real_type
3e73aa7c 1157reloc (size, pcrel, sign, other)
252b5132
RH		 1158 int size;
1159 int pcrel;
3e73aa7c 1160 int sign;
252b5132
RH		 1161 bfd_reloc_code_real_type other;
1162{
47926f60
KH		 1163 if (other != NO_RELOC)
1164 return other;
252b5132
RH		 1165
1166 if (pcrel)
1167 {
3e73aa7c 1168 if (!sign)
e5cb08ac 1169 as_bad (_("There are no unsigned pc-relative relocations"));
252b5132
RH		 1170 switch (size)
1171 {
1172 case 1: return BFD_RELOC_8_PCREL;
1173 case 2: return BFD_RELOC_16_PCREL;
1174 case 4: return BFD_RELOC_32_PCREL;
1175 }
d0b47220 1176 as_bad (_("can not do %d byte pc-relative relocation"), size);
252b5132
RH		 1177 }
1178 else
1179 {
3e73aa7c 1180 if (sign)
e5cb08ac 1181 switch (size)
3e73aa7c
JH		 1182 {
1183 case 4: return BFD_RELOC_X86_64_32S;
1184 }
1185 else
1186 switch (size)
1187 {
1188 case 1: return BFD_RELOC_8;
1189 case 2: return BFD_RELOC_16;
1190 case 4: return BFD_RELOC_32;
1191 case 8: return BFD_RELOC_64;
1192 }
1193 as_bad (_("can not do %s %d byte relocation"),
1194 sign ? "signed" : "unsigned", size);
252b5132
RH		 1195 }
1196
bfb32b52 1197 abort ();
252b5132
RH		 1198 return BFD_RELOC_NONE;
1199}
1200
47926f60
KH		 1201/* Here we decide which fixups can be adjusted to make them relative to
1202 the beginning of the section instead of the symbol. Basically we need
1203 to make sure that the dynamic relocations are done correctly, so in
1204 some cases we force the original symbol to be used. */
1205
252b5132 1206int
c0c949c7 1207tc_i386_fix_adjustable (fixP)
47926f60 1208 fixS *fixP;
252b5132 1209{
6d249963 1210#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
79d292aa
ILT		 1211 /* Prevent all adjustments to global symbols, or else dynamic
1212 linking will not work correctly. */
b98ef147 1213 if (S_IS_EXTERNAL (fixP->fx_addsy)
3bf057fa
AS		 1214 || S_IS_WEAK (fixP->fx_addsy)
1215 /* Don't adjust pc-relative references to merge sections in 64-bit
1216 mode. */
1217 || (use_rela_relocations
1218 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1219 && fixP->fx_pcrel))
252b5132
RH		 1220 return 0;
1221#endif
ce8a8b2f 1222 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1223 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1224 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1225 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1226 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1227 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1228 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1229 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
1230 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1231 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3e73aa7c
JH		 1232 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1233 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1234 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
252b5132
RH		 1235 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1236 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1237 return 0;
1238 return 1;
1239}
1240#else
ec56dfb4 1241#define reloc(SIZE,PCREL,SIGN,OTHER) 0
c6682705 1242#define BFD_RELOC_8 0
ec56dfb4
L		 1243#define BFD_RELOC_16 0
1244#define BFD_RELOC_32 0
c6682705 1245#define BFD_RELOC_8_PCREL 0
ec56dfb4
L		 1246#define BFD_RELOC_16_PCREL 0
1247#define BFD_RELOC_32_PCREL 0
1248#define BFD_RELOC_386_PLT32 0
1249#define BFD_RELOC_386_GOT32 0
1250#define BFD_RELOC_386_GOTOFF 0
13ae64f3
JJ		 1251#define BFD_RELOC_386_TLS_GD 0
1252#define BFD_RELOC_386_TLS_LDM 0
1253#define BFD_RELOC_386_TLS_LDO_32 0
1254#define BFD_RELOC_386_TLS_IE_32 0
1255#define BFD_RELOC_386_TLS_LE_32 0
1256#define BFD_RELOC_386_TLS_LE 0
ec56dfb4
L		 1257#define BFD_RELOC_X86_64_PLT32 0
1258#define BFD_RELOC_X86_64_GOT32 0
1259#define BFD_RELOC_X86_64_GOTPCREL 0
252b5132
RH		 1260#endif
1261
29b0f896 1262static int intel_float_operand PARAMS ((const char *mnemonic));
b4cac588
AM		 1263
1264static int
252b5132 1265intel_float_operand (mnemonic)
29b0f896 1266 const char *mnemonic;
252b5132 1267{
47926f60 1268 if (mnemonic[0] == 'f' && mnemonic[1] == 'i')
cc5ca5ce 1269 return 2;
252b5132
RH		 1270
1271 if (mnemonic[0] == 'f')
1272 return 1;
1273
1274 return 0;
1275}
1276
1277/* This is the guts of the machine-dependent assembler. LINE points to a
1278 machine dependent instruction. This function is supposed to emit
1279 the frags/bytes it assembles to. */
1280
1281void
1282md_assemble (line)
1283 char *line;
1284{
252b5132 1285 int j;
252b5132
RH		 1286 char mnemonic[MAX_MNEM_SIZE];
1287
47926f60 1288 /* Initialize globals. */
252b5132
RH		 1289 memset (&i, '\0', sizeof (i));
1290 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1291 i.reloc[j] = NO_RELOC;
252b5132
RH		 1292 memset (disp_expressions, '\0', sizeof (disp_expressions));
1293 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1294 save_stack_p = save_stack;
252b5132
RH		 1295
1296 /* First parse an instruction mnemonic & call i386_operand for the operands.
1297 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1298 start of a (possibly prefixed) mnemonic. */
252b5132 1299
29b0f896
AM		 1300 line = parse_insn (line, mnemonic);
1301 if (line == NULL)
1302 return;
252b5132 1303
29b0f896
AM		 1304 line = parse_operands (line, mnemonic);
1305 if (line == NULL)
1306 return;
252b5132 1307
29b0f896
AM		 1308 /* Now we've parsed the mnemonic into a set of templates, and have the
1309 operands at hand. */
1310
1311 /* All intel opcodes have reversed operands except for "bound" and
1312 "enter". We also don't reverse intersegment "jmp" and "call"
1313 instructions with 2 immediate operands so that the immediate segment
1314 precedes the offset, as it does when in AT&T mode. "enter" and the
1315 intersegment "jmp" and "call" instructions are the only ones that
1316 have two immediate operands. */
1317 if (intel_syntax && i.operands > 1
1318 && (strcmp (mnemonic, "bound") != 0)
1319 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1320 swap_operands ();
1321
1322 if (i.imm_operands)
1323 optimize_imm ();
1324
1325 if (i.disp_operands)
1326 optimize_disp ();
1327
1328 /* Next, we find a template that matches the given insn,
1329 making sure the overlap of the given operands types is consistent
1330 with the template operand types. */
252b5132 1331
29b0f896
AM		 1332 if (!match_template ())
1333 return;
252b5132 1334
cd61ebfe
AM		 1335 if (intel_syntax)
1336 {
1337 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1338 if (SYSV386_COMPAT
1339 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1340 i.tm.base_opcode ^= FloatR;
1341
1342 /* Zap movzx and movsx suffix. The suffix may have been set from
1343 "word ptr" or "byte ptr" on the source operand, but we'll use
1344 the suffix later to choose the destination register. */
1345 if ((i.tm.base_opcode & ~9) == 0x0fb6)
1346 i.suffix = 0;
1347 }
24eab124 1348
29b0f896
AM		 1349 if (i.tm.opcode_modifier & FWait)
1350 if (!add_prefix (FWAIT_OPCODE))
1351 return;
252b5132 1352
29b0f896
AM		 1353 /* Check string instruction segment overrides. */
1354 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1355 {
1356 if (!check_string ())
5dd0794d 1357 return;
29b0f896 1358 }
5dd0794d 1359
29b0f896
AM		 1360 if (!process_suffix ())
1361 return;
e413e4e9 1362
29b0f896
AM		 1363 /* Make still unresolved immediate matches conform to size of immediate
1364 given in i.suffix. */
1365 if (!finalize_imm ())
1366 return;
252b5132 1367
29b0f896
AM		 1368 if (i.types[0] & Imm1)
1369 i.imm_operands = 0; /* kludge for shift insns. */
1370 if (i.types[0] & ImplicitRegister)
1371 i.reg_operands--;
1372 if (i.types[1] & ImplicitRegister)
1373 i.reg_operands--;
1374 if (i.types[2] & ImplicitRegister)
1375 i.reg_operands--;
252b5132 1376
29b0f896
AM		 1377 if (i.tm.opcode_modifier & ImmExt)
1378 {
1379 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1380 opcode suffix which is coded in the same place as an 8-bit
1381 immediate field would be. Here we fake an 8-bit immediate
1382 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1383
29b0f896 1384 expressionS *exp;
252b5132 1385
29b0f896 1386 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1387
29b0f896
AM		 1388 exp = &im_expressions[i.imm_operands++];
1389 i.op[i.operands].imms = exp;
1390 i.types[i.operands++] = Imm8;
1391 exp->X_op = O_constant;
1392 exp->X_add_number = i.tm.extension_opcode;
1393 i.tm.extension_opcode = None;
1394 }
252b5132 1395
29b0f896
AM		 1396 /* For insns with operands there are more diddles to do to the opcode. */
1397 if (i.operands)
1398 {
1399 if (!process_operands ())
1400 return;
1401 }
1402 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1403 {
1404 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1405 as_warn (_("translating to `%sp'"), i.tm.name);
1406 }
252b5132 1407
29b0f896
AM		 1408 /* Handle conversion of 'int $3' --> special int3 insn. */
1409 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1410 {
1411 i.tm.base_opcode = INT3_OPCODE;
1412 i.imm_operands = 0;
1413 }
252b5132 1414
29b0f896
AM		 1415 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1416 && i.op[0].disps->X_op == O_constant)
1417 {
1418 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1419 the absolute address given by the constant. Since ix86 jumps and
1420 calls are pc relative, we need to generate a reloc. */
1421 i.op[0].disps->X_add_symbol = &abs_symbol;
1422 i.op[0].disps->X_op = O_symbol;
1423 }
252b5132 1424
29b0f896
AM		 1425 if ((i.tm.opcode_modifier & Rex64) != 0)
1426 i.rex |= REX_MODE64;
252b5132 1427
29b0f896
AM		 1428 /* For 8 bit registers we need an empty rex prefix. Also if the
1429 instruction already has a prefix, we need to convert old
1430 registers to new ones. */
773f551c 1431
29b0f896
AM		 1432 if (((i.types[0] & Reg8) != 0
1433 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1434 || ((i.types[1] & Reg8) != 0
1435 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1436 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1437 && i.rex != 0))
1438 {
1439 int x;
726c5dcd 1440
29b0f896
AM		 1441 i.rex |= REX_OPCODE;
1442 for (x = 0; x < 2; x++)
1443 {
1444 /* Look for 8 bit operand that uses old registers. */
1445 if ((i.types[x] & Reg8) != 0
1446 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1447 {
29b0f896
AM		 1448 /* In case it is "hi" register, give up. */
1449 if (i.op[x].regs->reg_num > 3)
1450 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix.\n"),
1451 i.op[x].regs->reg_name);
773f551c 1452
29b0f896
AM		 1453 /* Otherwise it is equivalent to the extended register.
1454 Since the encoding doesn't change this is merely
1455 cosmetic cleanup for debug output. */
1456
1457 i.op[x].regs = i.op[x].regs + 8;
773f551c 1458 }
29b0f896
AM		 1459 }
1460 }
773f551c 1461
29b0f896
AM		 1462 if (i.rex != 0)
1463 add_prefix (REX_OPCODE | i.rex);
1464
1465 /* We are ready to output the insn. */
1466 output_insn ();
1467}
1468
1469static char *
1470parse_insn (line, mnemonic)
1471 char *line;
1472 char *mnemonic;
1473{
1474 char *l = line;
1475 char *token_start = l;
1476 char *mnem_p;
1477
1478 /* Non-zero if we found a prefix only acceptable with string insns. */
1479 const char *expecting_string_instruction = NULL;
45288df1 1480
29b0f896
AM		 1481 while (1)
1482 {
1483 mnem_p = mnemonic;
1484 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1485 {
1486 mnem_p++;
1487 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1488 {
29b0f896
AM		 1489 as_bad (_("no such instruction: `%s'"), token_start);
1490 return NULL;
1491 }
1492 l++;
1493 }
1494 if (!is_space_char (*l)
1495 && *l != END_OF_INSN
1496 && *l != PREFIX_SEPARATOR
1497 && *l != ',')
1498 {
1499 as_bad (_("invalid character %s in mnemonic"),
1500 output_invalid (*l));
1501 return NULL;
1502 }
1503 if (token_start == l)
1504 {
1505 if (*l == PREFIX_SEPARATOR)
1506 as_bad (_("expecting prefix; got nothing"));
1507 else
1508 as_bad (_("expecting mnemonic; got nothing"));
1509 return NULL;
1510 }
45288df1 1511
29b0f896
AM		 1512 /* Look up instruction (or prefix) via hash table. */
1513 current_templates = hash_find (op_hash, mnemonic);
47926f60 1514
29b0f896
AM		 1515 if (*l != END_OF_INSN
1516 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1517 && current_templates
1518 && (current_templates->start->opcode_modifier & IsPrefix))
1519 {
1520 /* If we are in 16-bit mode, do not allow addr16 or data16.
1521 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1522 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1523 && flag_code != CODE_64BIT
1524 && (((current_templates->start->opcode_modifier & Size32) != 0)
1525 ^ (flag_code == CODE_16BIT)))
1526 {
1527 as_bad (_("redundant %s prefix"),
1528 current_templates->start->name);
1529 return NULL;
45288df1 1530 }
29b0f896
AM		 1531 /* Add prefix, checking for repeated prefixes. */
1532 switch (add_prefix (current_templates->start->base_opcode))
1533 {
1534 case 0:
1535 return NULL;
1536 case 2:
1537 expecting_string_instruction = current_templates->start->name;
1538 break;
1539 }
1540 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1541 token_start = ++l;
1542 }
1543 else
1544 break;
1545 }
45288df1 1546
29b0f896
AM		 1547 if (!current_templates)
1548 {
1549 /* See if we can get a match by trimming off a suffix. */
1550 switch (mnem_p[-1])
1551 {
1552 case WORD_MNEM_SUFFIX:
1553 case BYTE_MNEM_SUFFIX:
1554 case QWORD_MNEM_SUFFIX:
1555 i.suffix = mnem_p[-1];
1556 mnem_p[-1] = '\0';
1557 current_templates = hash_find (op_hash, mnemonic);
1558 break;
1559 case SHORT_MNEM_SUFFIX:
1560 case LONG_MNEM_SUFFIX:
1561 if (!intel_syntax)
1562 {
1563 i.suffix = mnem_p[-1];
1564 mnem_p[-1] = '\0';
1565 current_templates = hash_find (op_hash, mnemonic);
1566 }
1567 break;
252b5132 1568
29b0f896
AM		 1569 /* Intel Syntax. */
1570 case 'd':
1571 if (intel_syntax)
1572 {
1573 if (intel_float_operand (mnemonic))
1574 i.suffix = SHORT_MNEM_SUFFIX;
1575 else
1576 i.suffix = LONG_MNEM_SUFFIX;
1577 mnem_p[-1] = '\0';
1578 current_templates = hash_find (op_hash, mnemonic);
1579 }
1580 break;
1581 }
1582 if (!current_templates)
1583 {
1584 as_bad (_("no such instruction: `%s'"), token_start);
1585 return NULL;
1586 }
1587 }
252b5132 1588
29b0f896
AM		 1589 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
1590 {
1591 /* Check for a branch hint. We allow ",pt" and ",pn" for
1592 predict taken and predict not taken respectively.
1593 I'm not sure that branch hints actually do anything on loop
1594 and jcxz insns (JumpByte) for current Pentium4 chips. They
1595 may work in the future and it doesn't hurt to accept them
1596 now. */
1597 if (l[0] == ',' && l[1] == 'p')
1598 {
1599 if (l[2] == 't')
1600 {
1601 if (!add_prefix (DS_PREFIX_OPCODE))
1602 return NULL;
1603 l += 3;
1604 }
1605 else if (l[2] == 'n')
1606 {
1607 if (!add_prefix (CS_PREFIX_OPCODE))
1608 return NULL;
1609 l += 3;
1610 }
1611 }
1612 }
1613 /* Any other comma loses. */
1614 if (*l == ',')
1615 {
1616 as_bad (_("invalid character %s in mnemonic"),
1617 output_invalid (*l));
1618 return NULL;
1619 }
252b5132 1620
29b0f896
AM		 1621 /* Check if instruction is supported on specified architecture. */
1622 if ((current_templates->start->cpu_flags & ~(Cpu64 | CpuNo64))
1623 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64)))
1624 {
1625 as_warn (_("`%s' is not supported on `%s'"),
1626 current_templates->start->name, cpu_arch_name);
1627 }
1628 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
1629 {
1630 as_warn (_("use .code16 to ensure correct addressing mode"));
1631 }
252b5132 1632
29b0f896
AM		 1633 /* Check for rep/repne without a string instruction. */
1634 if (expecting_string_instruction
1635 && !(current_templates->start->opcode_modifier & IsString))
1636 {
1637 as_bad (_("expecting string instruction after `%s'"),
1638 expecting_string_instruction);
1639 return NULL;
1640 }
252b5132 1641
29b0f896
AM		 1642 return l;
1643}
252b5132 1644
29b0f896
AM		 1645static char *
1646parse_operands (l, mnemonic)
1647 char *l;
1648 const char *mnemonic;
1649{
1650 char *token_start;
3138f287 1651
29b0f896
AM		 1652 /* 1 if operand is pending after ','. */
1653 unsigned int expecting_operand = 0;
252b5132 1654
29b0f896
AM		 1655 /* Non-zero if operand parens not balanced. */
1656 unsigned int paren_not_balanced;
1657
1658 while (*l != END_OF_INSN)
1659 {
1660 /* Skip optional white space before operand. */
1661 if (is_space_char (*l))
1662 ++l;
1663 if (!is_operand_char (*l) && *l != END_OF_INSN)
1664 {
1665 as_bad (_("invalid character %s before operand %d"),
1666 output_invalid (*l),
1667 i.operands + 1);
1668 return NULL;
1669 }
1670 token_start = l; /* after white space */
1671 paren_not_balanced = 0;
1672 while (paren_not_balanced || *l != ',')
1673 {
1674 if (*l == END_OF_INSN)
1675 {
1676 if (paren_not_balanced)
1677 {
1678 if (!intel_syntax)
1679 as_bad (_("unbalanced parenthesis in operand %d."),
1680 i.operands + 1);
1681 else
1682 as_bad (_("unbalanced brackets in operand %d."),
1683 i.operands + 1);
1684 return NULL;
1685 }
1686 else
1687 break; /* we are done */
1688 }
1689 else if (!is_operand_char (*l) && !is_space_char (*l))
1690 {
1691 as_bad (_("invalid character %s in operand %d"),
1692 output_invalid (*l),
1693 i.operands + 1);
1694 return NULL;
1695 }
1696 if (!intel_syntax)
1697 {
1698 if (*l == '(')
1699 ++paren_not_balanced;
1700 if (*l == ')')
1701 --paren_not_balanced;
1702 }
1703 else
1704 {
1705 if (*l == '[')
1706 ++paren_not_balanced;
1707 if (*l == ']')
1708 --paren_not_balanced;
1709 }
1710 l++;
1711 }
1712 if (l != token_start)
1713 { /* Yes, we've read in another operand. */
1714 unsigned int operand_ok;
1715 this_operand = i.operands++;
1716 if (i.operands > MAX_OPERANDS)
1717 {
1718 as_bad (_("spurious operands; (%d operands/instruction max)"),
1719 MAX_OPERANDS);
1720 return NULL;
1721 }
1722 /* Now parse operand adding info to 'i' as we go along. */
1723 END_STRING_AND_SAVE (l);
1724
1725 if (intel_syntax)
1726 operand_ok =
1727 i386_intel_operand (token_start,
1728 intel_float_operand (mnemonic));
1729 else
1730 operand_ok = i386_operand (token_start);
1731
1732 RESTORE_END_STRING (l);
1733 if (!operand_ok)
1734 return NULL;
1735 }
1736 else
1737 {
1738 if (expecting_operand)
1739 {
1740 expecting_operand_after_comma:
1741 as_bad (_("expecting operand after ','; got nothing"));
1742 return NULL;
1743 }
1744 if (*l == ',')
1745 {
1746 as_bad (_("expecting operand before ','; got nothing"));
1747 return NULL;
1748 }
1749 }
7f3f1ea2 1750
29b0f896
AM		 1751 /* Now *l must be either ',' or END_OF_INSN. */
1752 if (*l == ',')
1753 {
1754 if (*++l == END_OF_INSN)
1755 {
1756 /* Just skip it, if it's \n complain. */
1757 goto expecting_operand_after_comma;
1758 }
1759 expecting_operand = 1;
1760 }
1761 }
1762 return l;
1763}
7f3f1ea2 1764
29b0f896
AM		 1765static void
1766swap_operands ()
1767{
1768 union i386_op temp_op;
1769 unsigned int temp_type;
1770 RELOC_ENUM temp_reloc;
1771 int xchg1 = 0;
1772 int xchg2 = 0;
252b5132 1773
29b0f896
AM		 1774 if (i.operands == 2)
1775 {
1776 xchg1 = 0;
1777 xchg2 = 1;
1778 }
1779 else if (i.operands == 3)
1780 {
1781 xchg1 = 0;
1782 xchg2 = 2;
1783 }
1784 temp_type = i.types[xchg2];
1785 i.types[xchg2] = i.types[xchg1];
1786 i.types[xchg1] = temp_type;
1787 temp_op = i.op[xchg2];
1788 i.op[xchg2] = i.op[xchg1];
1789 i.op[xchg1] = temp_op;
1790 temp_reloc = i.reloc[xchg2];
1791 i.reloc[xchg2] = i.reloc[xchg1];
1792 i.reloc[xchg1] = temp_reloc;
1793
1794 if (i.mem_operands == 2)
1795 {
1796 const seg_entry *temp_seg;
1797 temp_seg = i.seg[0];
1798 i.seg[0] = i.seg[1];
1799 i.seg[1] = temp_seg;
1800 }
1801}
252b5132 1802
29b0f896
AM		 1803/* Try to ensure constant immediates are represented in the smallest
1804 opcode possible. */
1805static void
1806optimize_imm ()
1807{
1808 char guess_suffix = 0;
1809 int op;
252b5132 1810
29b0f896
AM		 1811 if (i.suffix)
1812 guess_suffix = i.suffix;
1813 else if (i.reg_operands)
1814 {
1815 /* Figure out a suffix from the last register operand specified.
1816 We can't do this properly yet, ie. excluding InOutPortReg,
1817 but the following works for instructions with immediates.
1818 In any case, we can't set i.suffix yet. */
1819 for (op = i.operands; --op >= 0;)
1820 if (i.types[op] & Reg)
252b5132 1821 {
29b0f896
AM		 1822 if (i.types[op] & Reg8)
1823 guess_suffix = BYTE_MNEM_SUFFIX;
1824 else if (i.types[op] & Reg16)
1825 guess_suffix = WORD_MNEM_SUFFIX;
1826 else if (i.types[op] & Reg32)
1827 guess_suffix = LONG_MNEM_SUFFIX;
1828 else if (i.types[op] & Reg64)
1829 guess_suffix = QWORD_MNEM_SUFFIX;
1830 break;
252b5132 1831 }
29b0f896
AM		 1832 }
1833 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
1834 guess_suffix = WORD_MNEM_SUFFIX;
1835
1836 for (op = i.operands; --op >= 0;)
1837 if (i.types[op] & Imm)
1838 {
1839 switch (i.op[op].imms->X_op)
252b5132 1840 {
29b0f896
AM		 1841 case O_constant:
1842 /* If a suffix is given, this operand may be shortened. */
1843 switch (guess_suffix)
252b5132 1844 {
29b0f896
AM		 1845 case LONG_MNEM_SUFFIX:
1846 i.types[op] |= Imm32 | Imm64;
1847 break;
1848 case WORD_MNEM_SUFFIX:
1849 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
1850 break;
1851 case BYTE_MNEM_SUFFIX:
1852 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
1853 break;
252b5132 1854 }
252b5132 1855
29b0f896
AM		 1856 /* If this operand is at most 16 bits, convert it
1857 to a signed 16 bit number before trying to see
1858 whether it will fit in an even smaller size.
1859 This allows a 16-bit operand such as $0xffe0 to
1860 be recognised as within Imm8S range. */
1861 if ((i.types[op] & Imm16)
1862 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 1863 {
29b0f896
AM		 1864 i.op[op].imms->X_add_number =
1865 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
1866 }
1867 if ((i.types[op] & Imm32)
1868 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
1869 == 0))
1870 {
1871 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
1872 ^ ((offsetT) 1 << 31))
1873 - ((offsetT) 1 << 31));
1874 }
1875 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 1876
29b0f896
AM		 1877 /* We must avoid matching of Imm32 templates when 64bit
1878 only immediate is available. */
1879 if (guess_suffix == QWORD_MNEM_SUFFIX)
1880 i.types[op] &= ~Imm32;
1881 break;
252b5132 1882
29b0f896
AM		 1883 case O_absent:
1884 case O_register:
1885 abort ();
1886
1887 /* Symbols and expressions. */
1888 default:
1889 /* Convert symbolic operand to proper sizes for matching. */
1890 switch (guess_suffix)
1891 {
1892 case QWORD_MNEM_SUFFIX:
1893 i.types[op] = Imm64 | Imm32S;
1894 break;
1895 case LONG_MNEM_SUFFIX:
1896 i.types[op] = Imm32 | Imm64;
1897 break;
1898 case WORD_MNEM_SUFFIX:
1899 i.types[op] = Imm16 | Imm32 | Imm64;
1900 break;
1901 break;
1902 case BYTE_MNEM_SUFFIX:
1903 i.types[op] = Imm8 | Imm8S | Imm16 | Imm32S | Imm32;
1904 break;
1905 break;
252b5132 1906 }
29b0f896 1907 break;
252b5132 1908 }
29b0f896
AM		 1909 }
1910}
47926f60 1911
29b0f896
AM		 1912/* Try to use the smallest displacement type too. */
1913static void
1914optimize_disp ()
1915{
1916 int op;
3e73aa7c 1917
29b0f896
AM		 1918 for (op = i.operands; --op >= 0;)
1919 if ((i.types[op] & Disp) && i.op[op].disps->X_op == O_constant)
252b5132 1920 {
29b0f896
AM		 1921 offsetT disp = i.op[op].disps->X_add_number;
1922
1923 if (i.types[op] & Disp16)
252b5132 1924 {
29b0f896
AM		 1925 /* We know this operand is at most 16 bits, so
1926 convert to a signed 16 bit number before trying
1927 to see whether it will fit in an even smaller
1928 size. */
1929
1930 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
252b5132 1931 }
29b0f896 1932 else if (i.types[op] & Disp32)
252b5132 1933 {
29b0f896
AM		 1934 /* We know this operand is at most 32 bits, so convert to a
1935 signed 32 bit number before trying to see whether it will
1936 fit in an even smaller size. */
1937 disp &= (((offsetT) 2 << 31) - 1);
1938 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 1939 }
29b0f896 1940 if (flag_code == CODE_64BIT)
252b5132 1941 {
29b0f896
AM		 1942 if (fits_in_signed_long (disp))
1943 i.types[op] |= Disp32S;
1944 if (fits_in_unsigned_long (disp))
1945 i.types[op] |= Disp32;
252b5132 1946 }
29b0f896
AM		 1947 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
1948 && fits_in_signed_byte (disp))
1949 i.types[op] |= Disp8;
252b5132 1950 }
29b0f896
AM		 1951}
1952
1953static int
1954match_template ()
1955{
1956 /* Points to template once we've found it. */
1957 const template *t;
1958 unsigned int overlap0, overlap1, overlap2;
1959 unsigned int found_reverse_match;
1960 int suffix_check;
1961
1962#define MATCH(overlap, given, template) \
1963 ((overlap & ~JumpAbsolute) \
1964 && (((given) & (BaseIndex | JumpAbsolute)) \
1965 == ((overlap) & (BaseIndex | JumpAbsolute))))
1966
1967 /* If given types r0 and r1 are registers they must be of the same type
1968 unless the expected operand type register overlap is null.
1969 Note that Acc in a template matches every size of reg. */
1970#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1971 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
1972 || ((g0) & Reg) == ((g1) & Reg) \
1973 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1974
1975 overlap0 = 0;
1976 overlap1 = 0;
1977 overlap2 = 0;
1978 found_reverse_match = 0;
1979 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
1980 ? No_bSuf
1981 : (i.suffix == WORD_MNEM_SUFFIX
1982 ? No_wSuf
1983 : (i.suffix == SHORT_MNEM_SUFFIX
1984 ? No_sSuf
1985 : (i.suffix == LONG_MNEM_SUFFIX
1986 ? No_lSuf
1987 : (i.suffix == QWORD_MNEM_SUFFIX
1988 ? No_qSuf
1989 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
1990 ? No_xSuf : 0))))));
1991
1992 for (t = current_templates->start;
1993 t < current_templates->end;
1994 t++)
1995 {
1996 /* Must have right number of operands. */
1997 if (i.operands != t->operands)
1998 continue;
1999
2000 /* Check the suffix, except for some instructions in intel mode. */
2001 if ((t->opcode_modifier & suffix_check)
2002 && !(intel_syntax
2003 && (t->opcode_modifier & IgnoreSize))
2004 && !(intel_syntax
2005 && t->base_opcode == 0xd9
2006 && (t->extension_opcode == 5 /* 0xd9,5 "fldcw" */
2007 || t->extension_opcode == 7))) /* 0xd9,7 "f{n}stcw" */
2008 continue;
2009
2010 /* Do not verify operands when there are none. */
2011 else if (!t->operands)
2012 {
2013 if (t->cpu_flags & ~cpu_arch_flags)
2014 continue;
2015 /* We've found a match; break out of loop. */
2016 break;
2017 }
252b5132 2018
29b0f896
AM		 2019 overlap0 = i.types[0] & t->operand_types[0];
2020 switch (t->operands)
2021 {
2022 case 1:
2023 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
2024 continue;
2025 break;
2026 case 2:
2027 case 3:
2028 overlap1 = i.types[1] & t->operand_types[1];
2029 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
2030 || !MATCH (overlap1, i.types[1], t->operand_types[1])
2031 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2032 t->operand_types[0],
2033 overlap1, i.types[1],
2034 t->operand_types[1]))
2035 {
2036 /* Check if other direction is valid ... */
2037 if ((t->opcode_modifier & (D | FloatD)) == 0)
2038 continue;
2039
2040 /* Try reversing direction of operands. */
2041 overlap0 = i.types[0] & t->operand_types[1];
2042 overlap1 = i.types[1] & t->operand_types[0];
2043 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
2044 || !MATCH (overlap1, i.types[1], t->operand_types[0])
2045 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2046 t->operand_types[1],
2047 overlap1, i.types[1],
2048 t->operand_types[0]))
2049 {
2050 /* Does not match either direction. */
2051 continue;
2052 }
2053 /* found_reverse_match holds which of D or FloatDR
2054 we've found. */
2055 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2056 }
2057 /* Found a forward 2 operand match here. */
2058 else if (t->operands == 3)
2059 {
2060 /* Here we make use of the fact that there are no
2061 reverse match 3 operand instructions, and all 3
2062 operand instructions only need to be checked for
2063 register consistency between operands 2 and 3. */
2064 overlap2 = i.types[2] & t->operand_types[2];
2065 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
2066 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2067 t->operand_types[1],
2068 overlap2, i.types[2],
2069 t->operand_types[2]))
2070
2071 continue;
2072 }
2073 /* Found either forward/reverse 2 or 3 operand match here:
2074 slip through to break. */
2075 }
2076 if (t->cpu_flags & ~cpu_arch_flags)
2077 {
2078 found_reverse_match = 0;
2079 continue;
2080 }
2081 /* We've found a match; break out of loop. */
2082 break;
2083 }
2084
2085 if (t == current_templates->end)
2086 {
2087 /* We found no match. */
2088 as_bad (_("suffix or operands invalid for `%s'"),
2089 current_templates->start->name);
2090 return 0;
2091 }
252b5132 2092
29b0f896
AM		 2093 if (!quiet_warnings)
2094 {
2095 if (!intel_syntax
2096 && ((i.types[0] & JumpAbsolute)
2097 != (t->operand_types[0] & JumpAbsolute)))
2098 {
2099 as_warn (_("indirect %s without `*'"), t->name);
2100 }
2101
2102 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2103 == (IsPrefix | IgnoreSize))
2104 {
2105 /* Warn them that a data or address size prefix doesn't
2106 affect assembly of the next line of code. */
2107 as_warn (_("stand-alone `%s' prefix"), t->name);
2108 }
2109 }
2110
2111 /* Copy the template we found. */
2112 i.tm = *t;
2113 if (found_reverse_match)
2114 {
2115 /* If we found a reverse match we must alter the opcode
2116 direction bit. found_reverse_match holds bits to change
2117 (different for int & float insns). */
2118
2119 i.tm.base_opcode ^= found_reverse_match;
2120
2121 i.tm.operand_types[0] = t->operand_types[1];
2122 i.tm.operand_types[1] = t->operand_types[0];
2123 }
2124
2125 return 1;
2126}
2127
2128static int
2129check_string ()
2130{
2131 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2132 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2133 {
2134 if (i.seg[0] != NULL && i.seg[0] != &es)
2135 {
2136 as_bad (_("`%s' operand %d must use `%%es' segment"),
2137 i.tm.name,
2138 mem_op + 1);
2139 return 0;
2140 }
2141 /* There's only ever one segment override allowed per instruction.
2142 This instruction possibly has a legal segment override on the
2143 second operand, so copy the segment to where non-string
2144 instructions store it, allowing common code. */
2145 i.seg[0] = i.seg[1];
2146 }
2147 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2148 {
2149 if (i.seg[1] != NULL && i.seg[1] != &es)
2150 {
2151 as_bad (_("`%s' operand %d must use `%%es' segment"),
2152 i.tm.name,
2153 mem_op + 2);
2154 return 0;
2155 }
2156 }
2157 return 1;
2158}
2159
2160static int
2161process_suffix ()
2162{
2163 /* If matched instruction specifies an explicit instruction mnemonic
2164 suffix, use it. */
2165 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2166 {
2167 if (i.tm.opcode_modifier & Size16)
2168 i.suffix = WORD_MNEM_SUFFIX;
2169 else if (i.tm.opcode_modifier & Size64)
2170 i.suffix = QWORD_MNEM_SUFFIX;
2171 else
2172 i.suffix = LONG_MNEM_SUFFIX;
2173 }
2174 else if (i.reg_operands)
2175 {
2176 /* If there's no instruction mnemonic suffix we try to invent one
2177 based on register operands. */
2178 if (!i.suffix)
2179 {
2180 /* We take i.suffix from the last register operand specified,
2181 Destination register type is more significant than source
2182 register type. */
2183 int op;
2184 for (op = i.operands; --op >= 0;)
2185 if ((i.types[op] & Reg)
2186 && !(i.tm.operand_types[op] & InOutPortReg))
2187 {
2188 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2189 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2190 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2191 LONG_MNEM_SUFFIX);
2192 break;
2193 }
2194 }
2195 else if (i.suffix == BYTE_MNEM_SUFFIX)
2196 {
2197 if (!check_byte_reg ())
2198 return 0;
2199 }
2200 else if (i.suffix == LONG_MNEM_SUFFIX)
2201 {
2202 if (!check_long_reg ())
2203 return 0;
2204 }
2205 else if (i.suffix == QWORD_MNEM_SUFFIX)
2206 {
2207 if (!check_qword_reg ())
2208 return 0;
2209 }
2210 else if (i.suffix == WORD_MNEM_SUFFIX)
2211 {
2212 if (!check_word_reg ())
2213 return 0;
2214 }
2215 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2216 /* Do nothing if the instruction is going to ignore the prefix. */
2217 ;
2218 else
2219 abort ();
2220 }
2221 else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix)
2222 {
2223 i.suffix = stackop_size;
2224 }
252b5132 2225
29b0f896
AM		 2226 /* Change the opcode based on the operand size given by i.suffix;
2227 We need not change things for byte insns. */
252b5132 2228
29b0f896
AM		 2229 if (!i.suffix && (i.tm.opcode_modifier & W))
2230 {
2231 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2232 return 0;
2233 }
252b5132 2234
29b0f896
AM		 2235 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2236 {
2237 /* It's not a byte, select word/dword operation. */
2238 if (i.tm.opcode_modifier & W)
2239 {
2240 if (i.tm.opcode_modifier & ShortForm)
2241 i.tm.base_opcode |= 8;
2242 else
2243 i.tm.base_opcode |= 1;
2244 }
0f3f3d8b 2245
29b0f896
AM		 2246 /* Now select between word & dword operations via the operand
2247 size prefix, except for instructions that will ignore this
2248 prefix anyway. */
2249 if (i.suffix != QWORD_MNEM_SUFFIX
9146926a
AM		 2250 && !(i.tm.opcode_modifier & IgnoreSize)
2251 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2252 || (flag_code == CODE_64BIT
2253 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 2254 {
2255 unsigned int prefix = DATA_PREFIX_OPCODE;
29b0f896
AM		 2256 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2257 prefix = ADDR_PREFIX_OPCODE;
252b5132 2258
29b0f896
AM		 2259 if (!add_prefix (prefix))
2260 return 0;
24eab124 2261 }
252b5132 2262
29b0f896
AM		 2263 /* Set mode64 for an operand. */
2264 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 2265 && flag_code == CODE_64BIT
29b0f896 2266 && (i.tm.opcode_modifier & NoRex64) == 0)
9146926a 2267 i.rex |= REX_MODE64;
3e73aa7c 2268
29b0f896
AM		 2269 /* Size floating point instruction. */
2270 if (i.suffix == LONG_MNEM_SUFFIX)
2271 {
2272 if (i.tm.opcode_modifier & FloatMF)
2273 i.tm.base_opcode ^= 4;
2274 }
2275 }
7ecd2f8b 2276
29b0f896
AM		 2277 return 1;
2278}
3e73aa7c 2279
29b0f896
AM		 2280static int
2281check_byte_reg ()
2282{
2283 int op;
2284 for (op = i.operands; --op >= 0;)
2285 {
2286 /* If this is an eight bit register, it's OK. If it's the 16 or
2287 32 bit version of an eight bit register, we will just use the
2288 low portion, and that's OK too. */
2289 if (i.types[op] & Reg8)
2290 continue;
2291
2292 /* movzx and movsx should not generate this warning. */
2293 if (intel_syntax
2294 && (i.tm.base_opcode == 0xfb7
2295 || i.tm.base_opcode == 0xfb6
2296 || i.tm.base_opcode == 0x63
2297 || i.tm.base_opcode == 0xfbe
2298 || i.tm.base_opcode == 0xfbf))
2299 continue;
2300
2301 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4
2302#if 0
2303 /* Check that the template allows eight bit regs. This
2304 kills insns such as `orb $1,%edx', which maybe should be
2305 allowed. */
2306 && (i.tm.operand_types[op] & (Reg8 | InOutPortReg))
2307#endif
2308 )
2309 {
2310 /* Prohibit these changes in the 64bit mode, since the
2311 lowering is more complicated. */
2312 if (flag_code == CODE_64BIT
2313 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2314 {
0f3f3d8b 2315 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2316 i.op[op].regs->reg_name,
2317 i.suffix);
2318 return 0;
2319 }
2320#if REGISTER_WARNINGS
2321 if (!quiet_warnings
2322 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2323 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2324 (i.op[op].regs + (i.types[op] & Reg16
2325 ? REGNAM_AL - REGNAM_AX
2326 : REGNAM_AL - REGNAM_EAX))->reg_name,
2327 i.op[op].regs->reg_name,
2328 i.suffix);
2329#endif
2330 continue;
2331 }
2332 /* Any other register is bad. */
2333 if (i.types[op] & (Reg | RegMMX | RegXMM
2334 | SReg2 | SReg3
2335 | Control | Debug | Test
2336 | FloatReg | FloatAcc))
2337 {
2338 as_bad (_("`%%%s' not allowed with `%s%c'"),
2339 i.op[op].regs->reg_name,
2340 i.tm.name,
2341 i.suffix);
2342 return 0;
2343 }
2344 }
2345 return 1;
2346}
2347
2348static int
2349check_long_reg ()
2350{
2351 int op;
2352
2353 for (op = i.operands; --op >= 0;)
2354 /* Reject eight bit registers, except where the template requires
2355 them. (eg. movzb) */
2356 if ((i.types[op] & Reg8) != 0
2357 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2358 {
2359 as_bad (_("`%%%s' not allowed with `%s%c'"),
2360 i.op[op].regs->reg_name,
2361 i.tm.name,
2362 i.suffix);
2363 return 0;
2364 }
2365 /* Warn if the e prefix on a general reg is missing. */
2366 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2367 && (i.types[op] & Reg16) != 0
2368 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2369 {
2370 /* Prohibit these changes in the 64bit mode, since the
2371 lowering is more complicated. */
2372 if (flag_code == CODE_64BIT)
252b5132 2373 {
0f3f3d8b 2374 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2375 i.op[op].regs->reg_name,
2376 i.suffix);
2377 return 0;
252b5132 2378 }
29b0f896
AM		 2379#if REGISTER_WARNINGS
2380 else
2381 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2382 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
2383 i.op[op].regs->reg_name,
2384 i.suffix);
2385#endif
252b5132 2386 }
29b0f896
AM		 2387 /* Warn if the r prefix on a general reg is missing. */
2388 else if ((i.types[op] & Reg64) != 0
2389 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 2390 {
0f3f3d8b 2391 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2392 i.op[op].regs->reg_name,
2393 i.suffix);
2394 return 0;
2395 }
2396 return 1;
2397}
252b5132 2398
29b0f896
AM		 2399static int
2400check_qword_reg ()
2401{
2402 int op;
252b5132 2403
29b0f896
AM		 2404 for (op = i.operands; --op >= 0; )
2405 /* Reject eight bit registers, except where the template requires
2406 them. (eg. movzb) */
2407 if ((i.types[op] & Reg8) != 0
2408 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2409 {
2410 as_bad (_("`%%%s' not allowed with `%s%c'"),
2411 i.op[op].regs->reg_name,
2412 i.tm.name,
2413 i.suffix);
2414 return 0;
2415 }
2416 /* Warn if the e prefix on a general reg is missing. */
2417 else if (((i.types[op] & Reg16) != 0
2418 || (i.types[op] & Reg32) != 0)
2419 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2420 {
2421 /* Prohibit these changes in the 64bit mode, since the
2422 lowering is more complicated. */
0f3f3d8b 2423 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2424 i.op[op].regs->reg_name,
2425 i.suffix);
2426 return 0;
252b5132 2427 }
29b0f896
AM		 2428 return 1;
2429}
252b5132 2430
29b0f896
AM		 2431static int
2432check_word_reg ()
2433{
2434 int op;
2435 for (op = i.operands; --op >= 0;)
2436 /* Reject eight bit registers, except where the template requires
2437 them. (eg. movzb) */
2438 if ((i.types[op] & Reg8) != 0
2439 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2440 {
2441 as_bad (_("`%%%s' not allowed with `%s%c'"),
2442 i.op[op].regs->reg_name,
2443 i.tm.name,
2444 i.suffix);
2445 return 0;
2446 }
2447 /* Warn if the e prefix on a general reg is present. */
2448 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2449 && (i.types[op] & Reg32) != 0
2450 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 2451 {
29b0f896
AM		 2452 /* Prohibit these changes in the 64bit mode, since the
2453 lowering is more complicated. */
2454 if (flag_code == CODE_64BIT)
252b5132 2455 {
0f3f3d8b 2456 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2457 i.op[op].regs->reg_name,
2458 i.suffix);
2459 return 0;
252b5132 2460 }
29b0f896
AM		 2461 else
2462#if REGISTER_WARNINGS
2463 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2464 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
2465 i.op[op].regs->reg_name,
2466 i.suffix);
2467#endif
2468 }
2469 return 1;
2470}
252b5132 2471
29b0f896
AM		 2472static int
2473finalize_imm ()
2474{
2475 unsigned int overlap0, overlap1, overlap2;
2476
2477 overlap0 = i.types[0] & i.tm.operand_types[0];
2478 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S))
2479 && overlap0 != Imm8 && overlap0 != Imm8S
2480 && overlap0 != Imm16 && overlap0 != Imm32S
2481 && overlap0 != Imm32 && overlap0 != Imm64)
2482 {
2483 if (i.suffix)
2484 {
2485 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
2486 ? Imm8 | Imm8S
2487 : (i.suffix == WORD_MNEM_SUFFIX
2488 ? Imm16
2489 : (i.suffix == QWORD_MNEM_SUFFIX
2490 ? Imm64 | Imm32S
2491 : Imm32)));
2492 }
2493 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2494 || overlap0 == (Imm16 | Imm32)
2495 || overlap0 == (Imm16 | Imm32S))
2496 {
2497 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2498 ? Imm16 : Imm32S);
2499 }
2500 if (overlap0 != Imm8 && overlap0 != Imm8S
2501 && overlap0 != Imm16 && overlap0 != Imm32S
2502 && overlap0 != Imm32 && overlap0 != Imm64)
2503 {
2504 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2505 return 0;
2506 }
2507 }
2508 i.types[0] = overlap0;
2509
2510 overlap1 = i.types[1] & i.tm.operand_types[1];
2511 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32))
2512 && overlap1 != Imm8 && overlap1 != Imm8S
2513 && overlap1 != Imm16 && overlap1 != Imm32S
2514 && overlap1 != Imm32 && overlap1 != Imm64)
2515 {
2516 if (i.suffix)
2517 {
2518 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
2519 ? Imm8 | Imm8S
2520 : (i.suffix == WORD_MNEM_SUFFIX
2521 ? Imm16
2522 : (i.suffix == QWORD_MNEM_SUFFIX
2523 ? Imm64 | Imm32S
2524 : Imm32)));
2525 }
2526 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2527 || overlap1 == (Imm16 | Imm32)
2528 || overlap1 == (Imm16 | Imm32S))
2529 {
2530 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2531 ? Imm16 : Imm32S);
2532 }
2533 if (overlap1 != Imm8 && overlap1 != Imm8S
2534 && overlap1 != Imm16 && overlap1 != Imm32S
2535 && overlap1 != Imm32 && overlap1 != Imm64)
2536 {
2537 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
2538 return 0;
2539 }
2540 }
2541 i.types[1] = overlap1;
2542
2543 overlap2 = i.types[2] & i.tm.operand_types[2];
2544 assert ((overlap2 & Imm) == 0);
2545 i.types[2] = overlap2;
2546
2547 return 1;
2548}
2549
2550static int
2551process_operands ()
2552{
2553 /* Default segment register this instruction will use for memory
2554 accesses. 0 means unknown. This is only for optimizing out
2555 unnecessary segment overrides. */
2556 const seg_entry *default_seg = 0;
2557
2558 /* The imul $imm, %reg instruction is converted into
2559 imul $imm, %reg, %reg, and the clr %reg instruction
2560 is converted into xor %reg, %reg. */
2561 if (i.tm.opcode_modifier & regKludge)
2562 {
2563 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
2564 /* Pretend we saw the extra register operand. */
2565 assert (i.op[first_reg_op + 1].regs == 0);
2566 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2567 i.types[first_reg_op + 1] = i.types[first_reg_op];
2568 i.reg_operands = 2;
2569 }
2570
2571 if (i.tm.opcode_modifier & ShortForm)
2572 {
2573 /* The register or float register operand is in operand 0 or 1. */
2574 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2575 /* Register goes in low 3 bits of opcode. */
2576 i.tm.base_opcode |= i.op[op].regs->reg_num;
2577 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2578 i.rex |= REX_EXTZ;
2579 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2580 {
2581 /* Warn about some common errors, but press on regardless.
2582 The first case can be generated by gcc (<= 2.8.1). */
2583 if (i.operands == 2)
2584 {
2585 /* Reversed arguments on faddp, fsubp, etc. */
2586 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
2587 i.op[1].regs->reg_name,
2588 i.op[0].regs->reg_name);
2589 }
2590 else
2591 {
2592 /* Extraneous `l' suffix on fp insn. */
2593 as_warn (_("translating to `%s %%%s'"), i.tm.name,
2594 i.op[0].regs->reg_name);
2595 }
2596 }
2597 }
2598 else if (i.tm.opcode_modifier & Modrm)
2599 {
2600 /* The opcode is completed (modulo i.tm.extension_opcode which
2601 must be put into the modrm byte).
2602 Now, we make the modrm & index base bytes based on all the
2603 info we've collected. */
2604
2605 default_seg = build_modrm_byte ();
2606 }
2607 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2608 {
2609 if (i.tm.base_opcode == POP_SEG_SHORT
2610 && i.op[0].regs->reg_num == 1)
2611 {
2612 as_bad (_("you can't `pop %%cs'"));
2613 return 0;
2614 }
2615 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2616 if ((i.op[0].regs->reg_flags & RegRex) != 0)
2617 i.rex |= REX_EXTZ;
2618 }
2619 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
2620 {
2621 default_seg = &ds;
2622 }
2623 else if ((i.tm.opcode_modifier & IsString) != 0)
2624 {
2625 /* For the string instructions that allow a segment override
2626 on one of their operands, the default segment is ds. */
2627 default_seg = &ds;
2628 }
2629
2630 /* If a segment was explicitly specified,
2631 and the specified segment is not the default,
2632 use an opcode prefix to select it.
2633 If we never figured out what the default segment is,
2634 then default_seg will be zero at this point,
2635 and the specified segment prefix will always be used. */
2636 if ((i.seg[0]) && (i.seg[0] != default_seg))
2637 {
2638 if (!add_prefix (i.seg[0]->seg_prefix))
2639 return 0;
2640 }
2641 return 1;
2642}
2643
2644static const seg_entry *
2645build_modrm_byte ()
2646{
2647 const seg_entry *default_seg = 0;
2648
2649 /* i.reg_operands MUST be the number of real register operands;
2650 implicit registers do not count. */
2651 if (i.reg_operands == 2)
2652 {
2653 unsigned int source, dest;
2654 source = ((i.types[0]
2655 & (Reg | RegMMX | RegXMM
2656 | SReg2 | SReg3
2657 | Control | Debug | Test))
2658 ? 0 : 1);
2659 dest = source + 1;
2660
2661 i.rm.mode = 3;
2662 /* One of the register operands will be encoded in the i.tm.reg
2663 field, the other in the combined i.tm.mode and i.tm.regmem
2664 fields. If no form of this instruction supports a memory
2665 destination operand, then we assume the source operand may
2666 sometimes be a memory operand and so we need to store the
2667 destination in the i.rm.reg field. */
2668 if ((i.tm.operand_types[dest] & AnyMem) == 0)
2669 {
2670 i.rm.reg = i.op[dest].regs->reg_num;
2671 i.rm.regmem = i.op[source].regs->reg_num;
2672 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2673 i.rex |= REX_EXTX;
2674 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2675 i.rex |= REX_EXTZ;
2676 }
2677 else
2678 {
2679 i.rm.reg = i.op[source].regs->reg_num;
2680 i.rm.regmem = i.op[dest].regs->reg_num;
2681 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2682 i.rex |= REX_EXTZ;
2683 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2684 i.rex |= REX_EXTX;
2685 }
2686 }
2687 else
2688 { /* If it's not 2 reg operands... */
2689 if (i.mem_operands)
2690 {
2691 unsigned int fake_zero_displacement = 0;
2692 unsigned int op = ((i.types[0] & AnyMem)
2693 ? 0
2694 : (i.types[1] & AnyMem) ? 1 : 2);
2695
2696 default_seg = &ds;
2697
2698 if (i.base_reg == 0)
2699 {
2700 i.rm.mode = 0;
2701 if (!i.disp_operands)
2702 fake_zero_displacement = 1;
2703 if (i.index_reg == 0)
2704 {
2705 /* Operand is just <disp> */
2706 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
2707 && (flag_code != CODE_64BIT))
2708 {
2709 i.rm.regmem = NO_BASE_REGISTER_16;
2710 i.types[op] &= ~Disp;
2711 i.types[op] |= Disp16;
2712 }
2713 else if (flag_code != CODE_64BIT
2714 || (i.prefix[ADDR_PREFIX] != 0))
2715 {
2716 i.rm.regmem = NO_BASE_REGISTER;
2717 i.types[op] &= ~Disp;
2718 i.types[op] |= Disp32;
2719 }
2720 else
2721 {
2722 /* 64bit mode overwrites the 32bit absolute
2723 addressing by RIP relative addressing and
2724 absolute addressing is encoded by one of the
2725 redundant SIB forms. */
2726 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2727 i.sib.base = NO_BASE_REGISTER;
2728 i.sib.index = NO_INDEX_REGISTER;
2729 i.types[op] &= ~Disp;
2730 i.types[op] |= Disp32S;
2731 }
2732 }
2733 else /* !i.base_reg && i.index_reg */
2734 {
2735 i.sib.index = i.index_reg->reg_num;
2736 i.sib.base = NO_BASE_REGISTER;
2737 i.sib.scale = i.log2_scale_factor;
2738 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2739 i.types[op] &= ~Disp;
2740 if (flag_code != CODE_64BIT)
2741 i.types[op] |= Disp32; /* Must be 32 bit */
2742 else
2743 i.types[op] |= Disp32S;
2744 if ((i.index_reg->reg_flags & RegRex) != 0)
2745 i.rex |= REX_EXTY;
2746 }
2747 }
2748 /* RIP addressing for 64bit mode. */
2749 else if (i.base_reg->reg_type == BaseIndex)
2750 {
2751 i.rm.regmem = NO_BASE_REGISTER;
2752 i.types[op] &= ~Disp;
2753 i.types[op] |= Disp32S;
2754 i.flags[op] = Operand_PCrel;
2755 }
2756 else if (i.base_reg->reg_type & Reg16)
2757 {
2758 switch (i.base_reg->reg_num)
2759 {
2760 case 3: /* (%bx) */
2761 if (i.index_reg == 0)
2762 i.rm.regmem = 7;
2763 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2764 i.rm.regmem = i.index_reg->reg_num - 6;
2765 break;
2766 case 5: /* (%bp) */
2767 default_seg = &ss;
2768 if (i.index_reg == 0)
2769 {
2770 i.rm.regmem = 6;
2771 if ((i.types[op] & Disp) == 0)
2772 {
2773 /* fake (%bp) into 0(%bp) */
2774 i.types[op] |= Disp8;
252b5132 2775 fake_zero_displacement = 1;
29b0f896
AM		 2776 }
2777 }
2778 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2779 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
2780 break;
2781 default: /* (%si) -> 4 or (%di) -> 5 */
2782 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
2783 }
2784 i.rm.mode = mode_from_disp_size (i.types[op]);
2785 }
2786 else /* i.base_reg and 32/64 bit mode */
2787 {
2788 if (flag_code == CODE_64BIT
2789 && (i.types[op] & Disp))
2790 {
2791 if (i.types[op] & Disp8)
2792 i.types[op] = Disp8 | Disp32S;
2793 else
2794 i.types[op] = Disp32S;
2795 }
2796 i.rm.regmem = i.base_reg->reg_num;
2797 if ((i.base_reg->reg_flags & RegRex) != 0)
2798 i.rex |= REX_EXTZ;
2799 i.sib.base = i.base_reg->reg_num;
2800 /* x86-64 ignores REX prefix bit here to avoid decoder
2801 complications. */
2802 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
2803 {
2804 default_seg = &ss;
2805 if (i.disp_operands == 0)
2806 {
2807 fake_zero_displacement = 1;
2808 i.types[op] |= Disp8;
2809 }
2810 }
2811 else if (i.base_reg->reg_num == ESP_REG_NUM)
2812 {
2813 default_seg = &ss;
2814 }
2815 i.sib.scale = i.log2_scale_factor;
2816 if (i.index_reg == 0)
2817 {
2818 /* <disp>(%esp) becomes two byte modrm with no index
2819 register. We've already stored the code for esp
2820 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
2821 Any base register besides %esp will not use the
2822 extra modrm byte. */
2823 i.sib.index = NO_INDEX_REGISTER;
2824#if !SCALE1_WHEN_NO_INDEX
2825 /* Another case where we force the second modrm byte. */
2826 if (i.log2_scale_factor)
2827 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 2828#endif
29b0f896
AM		 2829 }
2830 else
2831 {
2832 i.sib.index = i.index_reg->reg_num;
2833 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2834 if ((i.index_reg->reg_flags & RegRex) != 0)
2835 i.rex |= REX_EXTY;
2836 }
2837 i.rm.mode = mode_from_disp_size (i.types[op]);
2838 }
252b5132 2839
29b0f896
AM		 2840 if (fake_zero_displacement)
2841 {
2842 /* Fakes a zero displacement assuming that i.types[op]
2843 holds the correct displacement size. */
2844 expressionS *exp;
2845
2846 assert (i.op[op].disps == 0);
2847 exp = &disp_expressions[i.disp_operands++];
2848 i.op[op].disps = exp;
2849 exp->X_op = O_constant;
2850 exp->X_add_number = 0;
2851 exp->X_add_symbol = (symbolS *) 0;
2852 exp->X_op_symbol = (symbolS *) 0;
2853 }
2854 }
252b5132 2855
29b0f896
AM		 2856 /* Fill in i.rm.reg or i.rm.regmem field with register operand
2857 (if any) based on i.tm.extension_opcode. Again, we must be
2858 careful to make sure that segment/control/debug/test/MMX
2859 registers are coded into the i.rm.reg field. */
2860 if (i.reg_operands)
2861 {
2862 unsigned int op =
2863 ((i.types[0]
2864 & (Reg | RegMMX | RegXMM
2865 | SReg2 | SReg3
2866 | Control | Debug | Test))
2867 ? 0
2868 : ((i.types[1]
2869 & (Reg | RegMMX | RegXMM
2870 | SReg2 | SReg3
2871 | Control | Debug | Test))
2872 ? 1
2873 : 2));
2874 /* If there is an extension opcode to put here, the register
2875 number must be put into the regmem field. */
2876 if (i.tm.extension_opcode != None)
2877 {
2878 i.rm.regmem = i.op[op].regs->reg_num;
2879 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2880 i.rex |= REX_EXTZ;
2881 }
2882 else
2883 {
2884 i.rm.reg = i.op[op].regs->reg_num;
2885 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2886 i.rex |= REX_EXTX;
2887 }
252b5132 2888
29b0f896
AM		 2889 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
2890 must set it to 3 to indicate this is a register operand
2891 in the regmem field. */
2892 if (!i.mem_operands)
2893 i.rm.mode = 3;
2894 }
252b5132 2895
29b0f896
AM		 2896 /* Fill in i.rm.reg field with extension opcode (if any). */
2897 if (i.tm.extension_opcode != None)
2898 i.rm.reg = i.tm.extension_opcode;
2899 }
2900 return default_seg;
2901}
252b5132 2902
29b0f896
AM		 2903static void
2904output_branch ()
2905{
2906 char *p;
2907 int code16;
2908 int prefix;
2909 relax_substateT subtype;
2910 symbolS *sym;
2911 offsetT off;
2912
2913 code16 = 0;
2914 if (flag_code == CODE_16BIT)
2915 code16 = CODE16;
2916
2917 prefix = 0;
2918 if (i.prefix[DATA_PREFIX] != 0)
252b5132 2919 {
29b0f896
AM		 2920 prefix = 1;
2921 i.prefixes -= 1;
2922 code16 ^= CODE16;
252b5132 2923 }
29b0f896
AM		 2924 /* Pentium4 branch hints. */
2925 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
2926 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 2927 {
29b0f896
AM		 2928 prefix++;
2929 i.prefixes--;
2930 }
2931 if (i.prefix[REX_PREFIX] != 0)
2932 {
2933 prefix++;
2934 i.prefixes--;
2f66722d
AM		 2935 }
2936
29b0f896
AM		 2937 if (i.prefixes != 0 && !intel_syntax)
2938 as_warn (_("skipping prefixes on this instruction"));
2939
2940 /* It's always a symbol; End frag & setup for relax.
2941 Make sure there is enough room in this frag for the largest
2942 instruction we may generate in md_convert_frag. This is 2
2943 bytes for the opcode and room for the prefix and largest
2944 displacement. */
2945 frag_grow (prefix + 2 + 4);
2946 /* Prefix and 1 opcode byte go in fr_fix. */
2947 p = frag_more (prefix + 1);
2948 if (i.prefix[DATA_PREFIX] != 0)
2949 *p++ = DATA_PREFIX_OPCODE;
2950 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
2951 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
2952 *p++ = i.prefix[SEG_PREFIX];
2953 if (i.prefix[REX_PREFIX] != 0)
2954 *p++ = i.prefix[REX_PREFIX];
2955 *p = i.tm.base_opcode;
2956
2957 if ((unsigned char) *p == JUMP_PC_RELATIVE)
2958 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
2959 else if ((cpu_arch_flags & Cpu386) != 0)
2960 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
2961 else
2962 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
2963 subtype |= code16;
3e73aa7c 2964
29b0f896
AM		 2965 sym = i.op[0].disps->X_add_symbol;
2966 off = i.op[0].disps->X_add_number;
3e73aa7c 2967
29b0f896
AM		 2968 if (i.op[0].disps->X_op != O_constant
2969 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 2970 {
29b0f896
AM		 2971 /* Handle complex expressions. */
2972 sym = make_expr_symbol (i.op[0].disps);
2973 off = 0;
2974 }
3e73aa7c 2975
29b0f896
AM		 2976 /* 1 possible extra opcode + 4 byte displacement go in var part.
2977 Pass reloc in fr_var. */
2978 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
2979}
3e73aa7c 2980
29b0f896
AM		 2981static void
2982output_jump ()
2983{
2984 char *p;
2985 int size;
2986
2987 if (i.tm.opcode_modifier & JumpByte)
2988 {
2989 /* This is a loop or jecxz type instruction. */
2990 size = 1;
2991 if (i.prefix[ADDR_PREFIX] != 0)
2992 {
2993 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
2994 i.prefixes -= 1;
2995 }
2996 /* Pentium4 branch hints. */
2997 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
2998 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2999 {
3000 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3001 i.prefixes--;
3e73aa7c
JH		 3002 }
3003 }
29b0f896
AM		 3004 else
3005 {
3006 int code16;
3e73aa7c 3007
29b0f896
AM		 3008 code16 = 0;
3009 if (flag_code == CODE_16BIT)
3010 code16 = CODE16;
3e73aa7c 3011
29b0f896
AM		 3012 if (i.prefix[DATA_PREFIX] != 0)
3013 {
3014 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3015 i.prefixes -= 1;
3016 code16 ^= CODE16;
3017 }
252b5132 3018
29b0f896
AM		 3019 size = 4;
3020 if (code16)
3021 size = 2;
3022 }
9fcc94b6 3023
29b0f896
AM		 3024 if (i.prefix[REX_PREFIX] != 0)
3025 {
3026 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3027 i.prefixes -= 1;
3028 }
252b5132 3029
29b0f896
AM		 3030 if (i.prefixes != 0 && !intel_syntax)
3031 as_warn (_("skipping prefixes on this instruction"));
e0890092 3032
29b0f896
AM		 3033 p = frag_more (1 + size);
3034 *p++ = i.tm.base_opcode;
e0890092 3035
062cd5e7
AS		 3036 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3037 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
29b0f896 3038}
e0890092 3039
29b0f896
AM		 3040static void
3041output_interseg_jump ()
3042{
3043 char *p;
3044 int size;
3045 int prefix;
3046 int code16;
252b5132 3047
29b0f896
AM		 3048 code16 = 0;
3049 if (flag_code == CODE_16BIT)
3050 code16 = CODE16;
a217f122 3051
29b0f896
AM		 3052 prefix = 0;
3053 if (i.prefix[DATA_PREFIX] != 0)
3054 {
3055 prefix = 1;
3056 i.prefixes -= 1;
3057 code16 ^= CODE16;
3058 }
3059 if (i.prefix[REX_PREFIX] != 0)
3060 {
3061 prefix++;
3062 i.prefixes -= 1;
3063 }
252b5132 3064
29b0f896
AM		 3065 size = 4;
3066 if (code16)
3067 size = 2;
252b5132 3068
29b0f896
AM		 3069 if (i.prefixes != 0 && !intel_syntax)
3070 as_warn (_("skipping prefixes on this instruction"));
252b5132 3071
29b0f896
AM		 3072 /* 1 opcode; 2 segment; offset */
3073 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3074
29b0f896
AM		 3075 if (i.prefix[DATA_PREFIX] != 0)
3076 *p++ = DATA_PREFIX_OPCODE;
252b5132 3077
29b0f896
AM		 3078 if (i.prefix[REX_PREFIX] != 0)
3079 *p++ = i.prefix[REX_PREFIX];
252b5132 3080
29b0f896
AM		 3081 *p++ = i.tm.base_opcode;
3082 if (i.op[1].imms->X_op == O_constant)
3083 {
3084 offsetT n = i.op[1].imms->X_add_number;
252b5132 3085
29b0f896
AM		 3086 if (size == 2
3087 && !fits_in_unsigned_word (n)
3088 && !fits_in_signed_word (n))
3089 {
3090 as_bad (_("16-bit jump out of range"));
3091 return;
3092 }
3093 md_number_to_chars (p, n, size);
3094 }
3095 else
3096 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3097 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3098 if (i.op[0].imms->X_op != O_constant)
3099 as_bad (_("can't handle non absolute segment in `%s'"),
3100 i.tm.name);
3101 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3102}
a217f122 3103
29b0f896
AM		 3104static void
3105output_insn ()
3106{
3107 /* Tie dwarf2 debug info to the address at the start of the insn.
3108 We can't do this after the insn has been output as the current
3109 frag may have been closed off. eg. by frag_var. */
3110 dwarf2_emit_insn (0);
3111
3112 /* Output jumps. */
3113 if (i.tm.opcode_modifier & Jump)
3114 output_branch ();
3115 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3116 output_jump ();
3117 else if (i.tm.opcode_modifier & JumpInterSegment)
3118 output_interseg_jump ();
3119 else
3120 {
3121 /* Output normal instructions here. */
3122 char *p;
3123 unsigned char *q;
252b5132 3124
29b0f896
AM		 3125 /* All opcodes on i386 have either 1 or 2 bytes. We may use third
3126 byte for the SSE instructions to specify a prefix they require. */
3127 if (i.tm.base_opcode & 0xff0000)
3128 add_prefix ((i.tm.base_opcode >> 16) & 0xff);
252b5132 3129
29b0f896
AM		 3130 /* The prefix bytes. */
3131 for (q = i.prefix;
3132 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3133 q++)
3134 {
3135 if (*q)
3136 {
3137 p = frag_more (1);
3138 md_number_to_chars (p, (valueT) *q, 1);
3139 }
3140 }
252b5132 3141
29b0f896
AM		 3142 /* Now the opcode; be careful about word order here! */
3143 if (fits_in_unsigned_byte (i.tm.base_opcode))
3144 {
3145 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3146 }
3147 else
3148 {
3149 p = frag_more (2);
3150 /* Put out high byte first: can't use md_number_to_chars! */
3151 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3152 *p = i.tm.base_opcode & 0xff;
3153 }
3e73aa7c 3154
29b0f896
AM		 3155 /* Now the modrm byte and sib byte (if present). */
3156 if (i.tm.opcode_modifier & Modrm)
3157 {
3158 p = frag_more (1);
3159 md_number_to_chars (p,
3160 (valueT) (i.rm.regmem << 0
3161 | i.rm.reg << 3
3162 | i.rm.mode << 6),
3163 1);
3164 /* If i.rm.regmem == ESP (4)
3165 && i.rm.mode != (Register mode)
3166 && not 16 bit
3167 ==> need second modrm byte. */
3168 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3169 && i.rm.mode != 3
3170 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3171 {
3172 p = frag_more (1);
3173 md_number_to_chars (p,
3174 (valueT) (i.sib.base << 0
3175 | i.sib.index << 3
3176 | i.sib.scale << 6),
3177 1);
3178 }
3179 }
3e73aa7c 3180
29b0f896
AM		 3181 if (i.disp_operands)
3182 output_disp ();
3e73aa7c 3183
29b0f896
AM		 3184 if (i.imm_operands)
3185 output_imm ();
3186 }
252b5132 3187
29b0f896
AM		 3188#ifdef DEBUG386
3189 if (flag_debug)
3190 {
3191 pi (line, &i);
3192 }
3193#endif /* DEBUG386 */
3194}
252b5132 3195
29b0f896
AM		 3196static void
3197output_disp ()
3198{
3199 char *p;
3200 unsigned int n;
252b5132 3201
29b0f896
AM		 3202 for (n = 0; n < i.operands; n++)
3203 {
3204 if (i.types[n] & Disp)
3205 {
3206 if (i.op[n].disps->X_op == O_constant)
3207 {
3208 int size;
3209 offsetT val;
252b5132 3210
29b0f896
AM		 3211 size = 4;
3212 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3213 {
3214 size = 2;
3215 if (i.types[n] & Disp8)
3216 size = 1;
3217 if (i.types[n] & Disp64)
3218 size = 8;
3219 }
3220 val = offset_in_range (i.op[n].disps->X_add_number,
3221 size);
3222 p = frag_more (size);
3223 md_number_to_chars (p, val, size);
3224 }
3225 else
3226 {
3227 int size = 4;
3228 int sign = 0;
3229 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
3230
3231 /* The PC relative address is computed relative
3232 to the instruction boundary, so in case immediate
3233 fields follows, we need to adjust the value. */
3234 if (pcrel && i.imm_operands)
3235 {
3236 int imm_size = 4;
3237 unsigned int n1;
252b5132 3238
29b0f896
AM		 3239 for (n1 = 0; n1 < i.operands; n1++)
3240 if (i.types[n1] & Imm)
252b5132 3241 {
29b0f896 3242 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 3243 {
29b0f896
AM		 3244 imm_size = 2;
3245 if (i.types[n1] & (Imm8 | Imm8S))
3246 imm_size = 1;
3247 if (i.types[n1] & Imm64)
3248 imm_size = 8;
252b5132 3249 }
29b0f896 3250 break;
252b5132 3251 }
29b0f896
AM		 3252 /* We should find the immediate. */
3253 if (n1 == i.operands)
3254 abort ();
3255 i.op[n].disps->X_add_number -= imm_size;
3256 }
520dc8e8 3257
29b0f896
AM		 3258 if (i.types[n] & Disp32S)
3259 sign = 1;
3e73aa7c 3260
29b0f896
AM		 3261 if (i.types[n] & (Disp16 | Disp64))
3262 {
3263 size = 2;
3264 if (i.types[n] & Disp64)
3265 size = 8;
3266 }
520dc8e8 3267
29b0f896 3268 p = frag_more (size);
062cd5e7
AS		 3269 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3270 i.op[n].disps, pcrel,
3271 reloc (size, pcrel, sign, i.reloc[n]));
29b0f896
AM		 3272 }
3273 }
3274 }
3275}
252b5132 3276
29b0f896
AM		 3277static void
3278output_imm ()
3279{
3280 char *p;
3281 unsigned int n;
252b5132 3282
29b0f896
AM		 3283 for (n = 0; n < i.operands; n++)
3284 {
3285 if (i.types[n] & Imm)
3286 {
3287 if (i.op[n].imms->X_op == O_constant)
3288 {
3289 int size;
3290 offsetT val;
b4cac588 3291
29b0f896
AM		 3292 size = 4;
3293 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3294 {
3295 size = 2;
3296 if (i.types[n] & (Imm8 | Imm8S))
3297 size = 1;
3298 else if (i.types[n] & Imm64)
3299 size = 8;
3300 }
3301 val = offset_in_range (i.op[n].imms->X_add_number,
3302 size);
3303 p = frag_more (size);
3304 md_number_to_chars (p, val, size);
3305 }
3306 else
3307 {
3308 /* Not absolute_section.
3309 Need a 32-bit fixup (don't support 8bit
3310 non-absolute imms). Try to support other
3311 sizes ... */
3312 RELOC_ENUM reloc_type;
3313 int size = 4;
3314 int sign = 0;
3315
3316 if ((i.types[n] & (Imm32S))
3317 && i.suffix == QWORD_MNEM_SUFFIX)
3318 sign = 1;
3319 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3320 {
3321 size = 2;
3322 if (i.types[n] & (Imm8 | Imm8S))
3323 size = 1;
3324 if (i.types[n] & Imm64)
3325 size = 8;
3326 }
520dc8e8 3327
29b0f896
AM		 3328 p = frag_more (size);
3329 reloc_type = reloc (size, 0, sign, i.reloc[n]);
252b5132 3330#ifdef BFD_ASSEMBLER
29b0f896
AM		 3331 if (reloc_type == BFD_RELOC_32
3332 && GOT_symbol
3333 && GOT_symbol == i.op[n].imms->X_add_symbol
3334 && (i.op[n].imms->X_op == O_symbol
3335 || (i.op[n].imms->X_op == O_add
3336 && ((symbol_get_value_expression
3337 (i.op[n].imms->X_op_symbol)->X_op)
3338 == O_subtract))))
3339 {
3340 /* We don't support dynamic linking on x86-64 yet. */
3341 if (flag_code == CODE_64BIT)
3342 abort ();
3343 reloc_type = BFD_RELOC_386_GOTPC;
3344 i.op[n].imms->X_add_number += 3;
3345 }
252b5132 3346#endif
29b0f896
AM		 3347 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3348 i.op[n].imms, 0, reloc_type);
3349 }
3350 }
3351 }
252b5132
RH		 3352}
3353\f
f3c180ae
AM		 3354#ifndef LEX_AT
3355static char *lex_got PARAMS ((RELOC_ENUM *, int *));
3356
3357/* Parse operands of the form
3358 <symbol>@GOTOFF+<nnn>
3359 and similar .plt or .got references.
3360
3361 If we find one, set up the correct relocation in RELOC and copy the
3362 input string, minus the `@GOTOFF' into a malloc'd buffer for
3363 parsing by the calling routine. Return this buffer, and if ADJUST
3364 is non-null set it to the length of the string we removed from the
3365 input line. Otherwise return NULL. */
3366static char *
3367lex_got (reloc, adjust)
3368 RELOC_ENUM *reloc;
3369 int *adjust;
3370{
3371 static const char * const mode_name[NUM_FLAG_CODE] = { "32", "16", "64" };
3372 static const struct {
3373 const char *str;
3374 const RELOC_ENUM rel[NUM_FLAG_CODE];
3375 } gotrel[] = {
13ae64f3
JJ		 3376 { "PLT", { BFD_RELOC_386_PLT32, 0, BFD_RELOC_X86_64_PLT32 } },
3377 { "GOTOFF", { BFD_RELOC_386_GOTOFF, 0, 0 } },
3378 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL } },
3379 { "TLSGD", { BFD_RELOC_386_TLS_GD, 0, 0 } },
3380 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0, 0 } },
3381 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, 0, 0 } },
3382 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, 0, 0 } },
3383 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0, 0 } },
3384 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, 0, 0 } },
3385 { "GOT", { BFD_RELOC_386_GOT32, 0, BFD_RELOC_X86_64_GOT32 } }
f3c180ae
AM		 3386 };
3387 char *cp;
3388 unsigned int j;
3389
3390 for (cp = input_line_pointer; *cp != '@'; cp++)
3391 if (is_end_of_line[(unsigned char) *cp])
3392 return NULL;
3393
3394 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
3395 {
3396 int len;
3397
3398 len = strlen (gotrel[j].str);
28f81592 3399 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae
AM		 3400 {
3401 if (gotrel[j].rel[(unsigned int) flag_code] != 0)
3402 {
28f81592
AM		 3403 int first, second;
3404 char *tmpbuf, *past_reloc;
f3c180ae
AM		 3405
3406 *reloc = gotrel[j].rel[(unsigned int) flag_code];
28f81592
AM		 3407 if (adjust)
3408 *adjust = len;
f3c180ae
AM		 3409
3410 if (GOT_symbol == NULL)
3411 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3412
3413 /* Replace the relocation token with ' ', so that
3414 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 3415
3416 /* The length of the first part of our input line. */
f3c180ae 3417 first = cp - input_line_pointer;
28f81592
AM		 3418
3419 /* The second part goes from after the reloc token until
3420 (and including) an end_of_line char. Don't use strlen
3421 here as the end_of_line char may not be a NUL. */
3422 past_reloc = cp + 1 + len;
3423 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
3424 ;
3425 second = cp - past_reloc;
3426
3427 /* Allocate and copy string. The trailing NUL shouldn't
3428 be necessary, but be safe. */
3429 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 3430 memcpy (tmpbuf, input_line_pointer, first);
3431 tmpbuf[first] = ' ';
28f81592
AM		 3432 memcpy (tmpbuf + first + 1, past_reloc, second);
3433 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 3434 return tmpbuf;
3435 }
3436
3437 as_bad (_("@%s reloc is not supported in %s bit mode"),
3438 gotrel[j].str, mode_name[(unsigned int) flag_code]);
3439 return NULL;
3440 }
3441 }
3442
3443 /* Might be a symbol version string. Don't as_bad here. */
3444 return NULL;
3445}
3446
3447/* x86_cons_fix_new is called via the expression parsing code when a
3448 reloc is needed. We use this hook to get the correct .got reloc. */
3449static RELOC_ENUM got_reloc = NO_RELOC;
3450
3451void
3452x86_cons_fix_new (frag, off, len, exp)
3453 fragS *frag;
3454 unsigned int off;
3455 unsigned int len;
3456 expressionS *exp;
3457{
3458 RELOC_ENUM r = reloc (len, 0, 0, got_reloc);
3459 got_reloc = NO_RELOC;
3460 fix_new_exp (frag, off, len, exp, 0, r);
3461}
3462
3463void
3464x86_cons (exp, size)
3465 expressionS *exp;
3466 int size;
3467{
3468 if (size == 4)
3469 {
3470 /* Handle @GOTOFF and the like in an expression. */
3471 char *save;
3472 char *gotfree_input_line;
3473 int adjust;
3474
3475 save = input_line_pointer;
3476 gotfree_input_line = lex_got (&got_reloc, &adjust);
3477 if (gotfree_input_line)
3478 input_line_pointer = gotfree_input_line;
3479
3480 expression (exp);
3481
3482 if (gotfree_input_line)
3483 {
3484 /* expression () has merrily parsed up to the end of line,
3485 or a comma - in the wrong buffer. Transfer how far
3486 input_line_pointer has moved to the right buffer. */
3487 input_line_pointer = (save
3488 + (input_line_pointer - gotfree_input_line)
3489 + adjust);
3490 free (gotfree_input_line);
3491 }
3492 }
3493 else
3494 expression (exp);
3495}
3496#endif
3497
252b5132
RH		 3498static int i386_immediate PARAMS ((char *));
3499
3500static int
3501i386_immediate (imm_start)
3502 char *imm_start;
3503{
3504 char *save_input_line_pointer;
f3c180ae
AM		 3505#ifndef LEX_AT
3506 char *gotfree_input_line;
3507#endif
252b5132 3508 segT exp_seg = 0;
47926f60 3509 expressionS *exp;
252b5132
RH		 3510
3511 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
3512 {
d0b47220 3513 as_bad (_("only 1 or 2 immediate operands are allowed"));
252b5132
RH		 3514 return 0;
3515 }
3516
3517 exp = &im_expressions[i.imm_operands++];
520dc8e8 3518 i.op[this_operand].imms = exp;
252b5132
RH		 3519
3520 if (is_space_char (*imm_start))
3521 ++imm_start;
3522
3523 save_input_line_pointer = input_line_pointer;
3524 input_line_pointer = imm_start;
3525
3526#ifndef LEX_AT
f3c180ae
AM		 3527 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3528 if (gotfree_input_line)
3529 input_line_pointer = gotfree_input_line;
252b5132
RH		 3530#endif
3531
3532 exp_seg = expression (exp);
3533
83183c0c 3534 SKIP_WHITESPACE ();
252b5132 3535 if (*input_line_pointer)
f3c180ae 3536 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 3537
3538 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 3539#ifndef LEX_AT
3540 if (gotfree_input_line)
3541 free (gotfree_input_line);
3542#endif
252b5132 3543
2daf4fd8 3544 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 3545 {
47926f60 3546 /* Missing or bad expr becomes absolute 0. */
d0b47220 3547 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 3548 imm_start);
252b5132
RH		 3549 exp->X_op = O_constant;
3550 exp->X_add_number = 0;
3551 exp->X_add_symbol = (symbolS *) 0;
3552 exp->X_op_symbol = (symbolS *) 0;
252b5132 3553 }
3e73aa7c 3554 else if (exp->X_op == O_constant)
252b5132 3555 {
47926f60 3556 /* Size it properly later. */
3e73aa7c
JH		 3557 i.types[this_operand] |= Imm64;
3558 /* If BFD64, sign extend val. */
3559 if (!use_rela_relocations)
3560 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
3561 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 3562 }
4c63da97 3563#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
47926f60 3564 else if (1
4c63da97 3565#ifdef BFD_ASSEMBLER
47926f60 3566 && OUTPUT_FLAVOR == bfd_target_aout_flavour
4c63da97 3567#endif
47926f60 3568 && exp_seg != text_section
24eab124
AM		 3569 && exp_seg != data_section
3570 && exp_seg != bss_section
3571 && exp_seg != undefined_section
252b5132 3572#ifdef BFD_ASSEMBLER
24eab124 3573 && !bfd_is_com_section (exp_seg)
252b5132 3574#endif
24eab124 3575 )
252b5132 3576 {
4c63da97 3577#ifdef BFD_ASSEMBLER
d0b47220 3578 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4c63da97 3579#else
d0b47220 3580 as_bad (_("unimplemented segment type %d in operand"), exp_seg);
4c63da97 3581#endif
252b5132
RH		 3582 return 0;
3583 }
3584#endif
3585 else
3586 {
3587 /* This is an address. The size of the address will be
24eab124 3588 determined later, depending on destination register,
3e73aa7c
JH		 3589 suffix, or the default for the section. */
3590 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
252b5132
RH		 3591 }
3592
3593 return 1;
3594}
3595
551c1ca1 3596static char *i386_scale PARAMS ((char *));
252b5132 3597
551c1ca1 3598static char *
252b5132
RH		 3599i386_scale (scale)
3600 char *scale;
3601{
551c1ca1
AM		 3602 offsetT val;
3603 char *save = input_line_pointer;
252b5132 3604
551c1ca1
AM		 3605 input_line_pointer = scale;
3606 val = get_absolute_expression ();
3607
3608 switch (val)
252b5132 3609 {
551c1ca1
AM		 3610 case 0:
3611 case 1:
252b5132
RH		 3612 i.log2_scale_factor = 0;
3613 break;
551c1ca1 3614 case 2:
252b5132
RH		 3615 i.log2_scale_factor = 1;
3616 break;
551c1ca1 3617 case 4:
252b5132
RH		 3618 i.log2_scale_factor = 2;
3619 break;
551c1ca1 3620 case 8:
252b5132
RH		 3621 i.log2_scale_factor = 3;
3622 break;
3623 default:
252b5132 3624 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
24eab124 3625 scale);
551c1ca1
AM		 3626 input_line_pointer = save;
3627 return NULL;
252b5132 3628 }
29b0f896 3629 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 3630 {
3631 as_warn (_("scale factor of %d without an index register"),
24eab124 3632 1 << i.log2_scale_factor);
252b5132
RH		 3633#if SCALE1_WHEN_NO_INDEX
3634 i.log2_scale_factor = 0;
3635#endif
3636 }
551c1ca1
AM		 3637 scale = input_line_pointer;
3638 input_line_pointer = save;
3639 return scale;
252b5132
RH		 3640}
3641
3642static int i386_displacement PARAMS ((char *, char *));
3643
3644static int
3645i386_displacement (disp_start, disp_end)
3646 char *disp_start;
3647 char *disp_end;
3648{
29b0f896 3649 expressionS *exp;
252b5132
RH		 3650 segT exp_seg = 0;
3651 char *save_input_line_pointer;
f3c180ae
AM		 3652#ifndef LEX_AT
3653 char *gotfree_input_line;
3654#endif
252b5132
RH		 3655 int bigdisp = Disp32;
3656
3e73aa7c 3657 if (flag_code == CODE_64BIT)
7ecd2f8b 3658 {
29b0f896
AM		 3659 if (i.prefix[ADDR_PREFIX] == 0)
3660 bigdisp = Disp64;
7ecd2f8b
JH		 3661 }
3662 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3663 bigdisp = Disp16;
252b5132
RH		 3664 i.types[this_operand] |= bigdisp;
3665
3666 exp = &disp_expressions[i.disp_operands];
520dc8e8 3667 i.op[this_operand].disps = exp;
252b5132
RH		 3668 i.disp_operands++;
3669 save_input_line_pointer = input_line_pointer;
3670 input_line_pointer = disp_start;
3671 END_STRING_AND_SAVE (disp_end);
3672
3673#ifndef GCC_ASM_O_HACK
3674#define GCC_ASM_O_HACK 0
3675#endif
3676#if GCC_ASM_O_HACK
3677 END_STRING_AND_SAVE (disp_end + 1);
3678 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 3679 && displacement_string_end[-1] == '+')
252b5132
RH		 3680 {
3681 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 3682 constraint within gcc asm statements.
3683 For instance:
3684
3685 #define _set_tssldt_desc(n,addr,limit,type) \
3686 __asm__ __volatile__ ( \
3687 "movw %w2,%0\n\t" \
3688 "movw %w1,2+%0\n\t" \
3689 "rorl $16,%1\n\t" \
3690 "movb %b1,4+%0\n\t" \
3691 "movb %4,5+%0\n\t" \
3692 "movb $0,6+%0\n\t" \
3693 "movb %h1,7+%0\n\t" \
3694 "rorl $16,%1" \
3695 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3696
3697 This works great except that the output assembler ends
3698 up looking a bit weird if it turns out that there is
3699 no offset. You end up producing code that looks like:
3700
3701 #APP
3702 movw $235,(%eax)
3703 movw %dx,2+(%eax)
3704 rorl $16,%edx
3705 movb %dl,4+(%eax)
3706 movb $137,5+(%eax)
3707 movb $0,6+(%eax)
3708 movb %dh,7+(%eax)
3709 rorl $16,%edx
3710 #NO_APP
3711
47926f60 3712 So here we provide the missing zero. */
24eab124
AM		 3713
3714 *displacement_string_end = '0';
252b5132
RH		 3715 }
3716#endif
3717#ifndef LEX_AT
f3c180ae
AM		 3718 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3719 if (gotfree_input_line)
3720 input_line_pointer = gotfree_input_line;
252b5132
RH		 3721#endif
3722
24eab124 3723 exp_seg = expression (exp);
252b5132 3724
636c26b0
AM		 3725 SKIP_WHITESPACE ();
3726 if (*input_line_pointer)
3727 as_bad (_("junk `%s' after expression"), input_line_pointer);
3728#if GCC_ASM_O_HACK
3729 RESTORE_END_STRING (disp_end + 1);
3730#endif
3731 RESTORE_END_STRING (disp_end);
3732 input_line_pointer = save_input_line_pointer;
3733#ifndef LEX_AT
3734 if (gotfree_input_line)
3735 free (gotfree_input_line);
3736#endif
3737
252b5132 3738#ifdef BFD_ASSEMBLER
24eab124
AM		 3739 /* We do this to make sure that the section symbol is in
3740 the symbol table. We will ultimately change the relocation
47926f60 3741 to be relative to the beginning of the section. */
1ae12ab7
AM		 3742 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
3743 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
24eab124 3744 {
636c26b0
AM		 3745 if (exp->X_op != O_symbol)
3746 {
3747 as_bad (_("bad expression used with @%s"),
3748 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
3749 ? "GOTPCREL"
3750 : "GOTOFF"));
3751 return 0;
3752 }
3753
e5cb08ac 3754 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 3755 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
3756 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 3757 exp->X_op = O_subtract;
3758 exp->X_op_symbol = GOT_symbol;
1ae12ab7 3759 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 3760 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
23df1078 3761 else
29b0f896 3762 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 3763 }
252b5132
RH		 3764#endif
3765
2daf4fd8
AM		 3766 if (exp->X_op == O_absent || exp->X_op == O_big)
3767 {
47926f60 3768 /* Missing or bad expr becomes absolute 0. */
d0b47220 3769 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 3770 disp_start);
3771 exp->X_op = O_constant;
3772 exp->X_add_number = 0;
3773 exp->X_add_symbol = (symbolS *) 0;
3774 exp->X_op_symbol = (symbolS *) 0;
3775 }
3776
4c63da97 3777#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 3778 if (exp->X_op != O_constant
4c63da97 3779#ifdef BFD_ASSEMBLER
45288df1 3780 && OUTPUT_FLAVOR == bfd_target_aout_flavour
4c63da97 3781#endif
45288df1
AM		 3782 && exp_seg != text_section
3783 && exp_seg != data_section
3784 && exp_seg != bss_section
3785 && exp_seg != undefined_section)
24eab124 3786 {
4c63da97 3787#ifdef BFD_ASSEMBLER
d0b47220 3788 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4c63da97 3789#else
d0b47220 3790 as_bad (_("unimplemented segment type %d in operand"), exp_seg);
4c63da97 3791#endif
24eab124
AM		 3792 return 0;
3793 }
252b5132 3794#endif
3e73aa7c
JH		 3795 else if (flag_code == CODE_64BIT)
3796 i.types[this_operand] |= Disp32S | Disp32;
252b5132
RH		 3797 return 1;
3798}
3799
e5cb08ac 3800static int i386_index_check PARAMS ((const char *));
252b5132 3801
eecb386c 3802/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 3803 Return 1 on success, 0 on a failure. */
3804
252b5132 3805static int
eecb386c
AM		 3806i386_index_check (operand_string)
3807 const char *operand_string;
252b5132 3808{
3e73aa7c 3809 int ok;
24eab124 3810#if INFER_ADDR_PREFIX
eecb386c
AM		 3811 int fudged = 0;
3812
24eab124
AM		 3813 tryprefix:
3814#endif
3e73aa7c
JH		 3815 ok = 1;
3816 if (flag_code == CODE_64BIT)
3817 {
7ecd2f8b
JH		 3818 if (i.prefix[ADDR_PREFIX] == 0)
3819 {
3820 /* 64bit checks. */
3821 if ((i.base_reg
3822 && ((i.base_reg->reg_type & Reg64) == 0)
3823 && (i.base_reg->reg_type != BaseIndex
3824 || i.index_reg))
3825 || (i.index_reg
29b0f896
AM		 3826 && ((i.index_reg->reg_type & (Reg64 | BaseIndex))
3827 != (Reg64 | BaseIndex))))
7ecd2f8b
JH		 3828 ok = 0;
3829 }
3830 else
3831 {
3832 /* 32bit checks. */
3833 if ((i.base_reg
3834 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
3835 || (i.index_reg
29b0f896
AM		 3836 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
3837 != (Reg32 | BaseIndex))))
7ecd2f8b
JH		 3838 ok = 0;
3839 }
3e73aa7c
JH		 3840 }
3841 else
3842 {
3843 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3844 {
3845 /* 16bit checks. */
3846 if ((i.base_reg
29b0f896
AM		 3847 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
3848 != (Reg16 | BaseIndex)))
3e73aa7c 3849 || (i.index_reg
29b0f896
AM		 3850 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
3851 != (Reg16 | BaseIndex))
3852 || !(i.base_reg
3853 && i.base_reg->reg_num < 6
3854 && i.index_reg->reg_num >= 6
3855 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 3856 ok = 0;
3857 }
3858 else
e5cb08ac 3859 {
3e73aa7c
JH		 3860 /* 32bit checks. */
3861 if ((i.base_reg
3862 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
3863 || (i.index_reg
29b0f896
AM		 3864 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
3865 != (Reg32 | BaseIndex))))
e5cb08ac 3866 ok = 0;
3e73aa7c
JH		 3867 }
3868 }
3869 if (!ok)
24eab124
AM		 3870 {
3871#if INFER_ADDR_PREFIX
3e73aa7c
JH		 3872 if (flag_code != CODE_64BIT
3873 && i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0')
24eab124
AM		 3874 {
3875 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
3876 i.prefixes += 1;
b23bac36
AM		 3877 /* Change the size of any displacement too. At most one of
3878 Disp16 or Disp32 is set.
3879 FIXME. There doesn't seem to be any real need for separate
3880 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 3881 Removing them would probably clean up the code quite a lot. */
29b0f896
AM		 3882 if (i.types[this_operand] & (Disp16 | Disp32))
3883 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 3884 fudged = 1;
24eab124
AM		 3885 goto tryprefix;
3886 }
eecb386c
AM		 3887 if (fudged)
3888 as_bad (_("`%s' is not a valid base/index expression"),
3889 operand_string);
3890 else
c388dee8 3891#endif
eecb386c
AM		 3892 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3893 operand_string,
3e73aa7c 3894 flag_code_names[flag_code]);
eecb386c 3895 return 0;
24eab124
AM		 3896 }
3897 return 1;
3898}
252b5132 3899
252b5132 3900/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 3901 on error. */
252b5132 3902
252b5132
RH		 3903static int
3904i386_operand (operand_string)
3905 char *operand_string;
3906{
af6bdddf
AM		 3907 const reg_entry *r;
3908 char *end_op;
24eab124 3909 char *op_string = operand_string;
252b5132 3910
24eab124 3911 if (is_space_char (*op_string))
252b5132
RH		 3912 ++op_string;
3913
24eab124 3914 /* We check for an absolute prefix (differentiating,
47926f60 3915 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 3916 if (*op_string == ABSOLUTE_PREFIX)
3917 {
3918 ++op_string;
3919 if (is_space_char (*op_string))
3920 ++op_string;
3921 i.types[this_operand] |= JumpAbsolute;
3922 }
252b5132 3923
47926f60 3924 /* Check if operand is a register. */
af6bdddf
AM		 3925 if ((*op_string == REGISTER_PREFIX || allow_naked_reg)
3926 && (r = parse_register (op_string, &end_op)) != NULL)
24eab124 3927 {
24eab124
AM		 3928 /* Check for a segment override by searching for ':' after a
3929 segment register. */
3930 op_string = end_op;
3931 if (is_space_char (*op_string))
3932 ++op_string;
3933 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
3934 {
3935 switch (r->reg_num)
3936 {
3937 case 0:
3938 i.seg[i.mem_operands] = &es;
3939 break;
3940 case 1:
3941 i.seg[i.mem_operands] = &cs;
3942 break;
3943 case 2:
3944 i.seg[i.mem_operands] = &ss;
3945 break;
3946 case 3:
3947 i.seg[i.mem_operands] = &ds;
3948 break;
3949 case 4:
3950 i.seg[i.mem_operands] = &fs;
3951 break;
3952 case 5:
3953 i.seg[i.mem_operands] = &gs;
3954 break;
3955 }
252b5132 3956
24eab124 3957 /* Skip the ':' and whitespace. */
252b5132
RH		 3958 ++op_string;
3959 if (is_space_char (*op_string))
24eab124 3960 ++op_string;
252b5132 3961
24eab124
AM		 3962 if (!is_digit_char (*op_string)
3963 && !is_identifier_char (*op_string)
3964 && *op_string != '('
3965 && *op_string != ABSOLUTE_PREFIX)
3966 {
3967 as_bad (_("bad memory operand `%s'"), op_string);
3968 return 0;
3969 }
47926f60 3970 /* Handle case of %es:*foo. */
24eab124
AM		 3971 if (*op_string == ABSOLUTE_PREFIX)
3972 {
3973 ++op_string;
3974 if (is_space_char (*op_string))
3975 ++op_string;
3976 i.types[this_operand] |= JumpAbsolute;
3977 }
3978 goto do_memory_reference;
3979 }
3980 if (*op_string)
3981 {
d0b47220 3982 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 3983 return 0;
3984 }
3985 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 3986 i.op[this_operand].regs = r;
24eab124
AM		 3987 i.reg_operands++;
3988 }
af6bdddf
AM		 3989 else if (*op_string == REGISTER_PREFIX)
3990 {
3991 as_bad (_("bad register name `%s'"), op_string);
3992 return 0;
3993 }
24eab124 3994 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 3995 {
24eab124
AM		 3996 ++op_string;
3997 if (i.types[this_operand] & JumpAbsolute)
3998 {
d0b47220 3999 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 4000 return 0;
4001 }
4002 if (!i386_immediate (op_string))
4003 return 0;
4004 }
4005 else if (is_digit_char (*op_string)
4006 || is_identifier_char (*op_string)
e5cb08ac 4007 || *op_string == '(')
24eab124 4008 {
47926f60 4009 /* This is a memory reference of some sort. */
af6bdddf 4010 char *base_string;
252b5132 4011
47926f60 4012 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 4013 char *displacement_string_start;
4014 char *displacement_string_end;
252b5132 4015
24eab124 4016 do_memory_reference:
24eab124
AM		 4017 if ((i.mem_operands == 1
4018 && (current_templates->start->opcode_modifier & IsString) == 0)
4019 || i.mem_operands == 2)
4020 {
4021 as_bad (_("too many memory references for `%s'"),
4022 current_templates->start->name);
4023 return 0;
4024 }
252b5132 4025
24eab124
AM		 4026 /* Check for base index form. We detect the base index form by
4027 looking for an ')' at the end of the operand, searching
4028 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4029 after the '('. */
af6bdddf 4030 base_string = op_string + strlen (op_string);
c3332e24 4031
af6bdddf
AM		 4032 --base_string;
4033 if (is_space_char (*base_string))
4034 --base_string;
252b5132 4035
47926f60 4036 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 4037 displacement_string_start = op_string;
4038 displacement_string_end = base_string + 1;
252b5132 4039
24eab124
AM		 4040 if (*base_string == ')')
4041 {
af6bdddf 4042 char *temp_string;
24eab124
AM		 4043 unsigned int parens_balanced = 1;
4044 /* We've already checked that the number of left & right ()'s are
47926f60 4045 equal, so this loop will not be infinite. */
24eab124
AM		 4046 do
4047 {
4048 base_string--;
4049 if (*base_string == ')')
4050 parens_balanced++;
4051 if (*base_string == '(')
4052 parens_balanced--;
4053 }
4054 while (parens_balanced);
c3332e24 4055
af6bdddf 4056 temp_string = base_string;
c3332e24 4057
24eab124 4058 /* Skip past '(' and whitespace. */
252b5132
RH		 4059 ++base_string;
4060 if (is_space_char (*base_string))
24eab124 4061 ++base_string;
252b5132 4062
af6bdddf
AM		 4063 if (*base_string == ','
4064 || ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4065 && (i.base_reg = parse_register (base_string, &end_op)) != NULL))
252b5132 4066 {
af6bdddf 4067 displacement_string_end = temp_string;
252b5132 4068
af6bdddf 4069 i.types[this_operand] |= BaseIndex;
252b5132 4070
af6bdddf 4071 if (i.base_reg)
24eab124 4072 {
24eab124
AM		 4073 base_string = end_op;
4074 if (is_space_char (*base_string))
4075 ++base_string;
af6bdddf
AM		 4076 }
4077
4078 /* There may be an index reg or scale factor here. */
4079 if (*base_string == ',')
4080 {
4081 ++base_string;
4082 if (is_space_char (*base_string))
4083 ++base_string;
4084
4085 if ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4086 && (i.index_reg = parse_register (base_string, &end_op)) != NULL)
24eab124 4087 {
af6bdddf 4088 base_string = end_op;
24eab124
AM		 4089 if (is_space_char (*base_string))
4090 ++base_string;
af6bdddf
AM		 4091 if (*base_string == ',')
4092 {
4093 ++base_string;
4094 if (is_space_char (*base_string))
4095 ++base_string;
4096 }
e5cb08ac 4097 else if (*base_string != ')')
af6bdddf
AM		 4098 {
4099 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4100 operand_string);
4101 return 0;
4102 }
24eab124 4103 }
af6bdddf 4104 else if (*base_string == REGISTER_PREFIX)
24eab124 4105 {
af6bdddf 4106 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 4107 return 0;
4108 }
252b5132 4109
47926f60 4110 /* Check for scale factor. */
551c1ca1 4111 if (*base_string != ')')
af6bdddf 4112 {
551c1ca1
AM		 4113 char *end_scale = i386_scale (base_string);
4114
4115 if (!end_scale)
af6bdddf 4116 return 0;
24eab124 4117
551c1ca1 4118 base_string = end_scale;
af6bdddf
AM		 4119 if (is_space_char (*base_string))
4120 ++base_string;
4121 if (*base_string != ')')
4122 {
4123 as_bad (_("expecting `)' after scale factor in `%s'"),
4124 operand_string);
4125 return 0;
4126 }
4127 }
4128 else if (!i.index_reg)
24eab124 4129 {
af6bdddf
AM		 4130 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4131 *base_string);
24eab124
AM		 4132 return 0;
4133 }
4134 }
af6bdddf 4135 else if (*base_string != ')')
24eab124 4136 {
af6bdddf
AM		 4137 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4138 operand_string);
24eab124
AM		 4139 return 0;
4140 }
c3332e24 4141 }
af6bdddf 4142 else if (*base_string == REGISTER_PREFIX)
c3332e24 4143 {
af6bdddf 4144 as_bad (_("bad register name `%s'"), base_string);
24eab124 4145 return 0;
c3332e24 4146 }
24eab124
AM		 4147 }
4148
4149 /* If there's an expression beginning the operand, parse it,
4150 assuming displacement_string_start and
4151 displacement_string_end are meaningful. */
4152 if (displacement_string_start != displacement_string_end)
4153 {
4154 if (!i386_displacement (displacement_string_start,
4155 displacement_string_end))
4156 return 0;
4157 }
4158
4159 /* Special case for (%dx) while doing input/output op. */
4160 if (i.base_reg
4161 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
4162 && i.index_reg == 0
4163 && i.log2_scale_factor == 0
4164 && i.seg[i.mem_operands] == 0
4165 && (i.types[this_operand] & Disp) == 0)
4166 {
4167 i.types[this_operand] = InOutPortReg;
4168 return 1;
4169 }
4170
eecb386c
AM		 4171 if (i386_index_check (operand_string) == 0)
4172 return 0;
24eab124
AM		 4173 i.mem_operands++;
4174 }
4175 else
ce8a8b2f
AM		 4176 {
4177 /* It's not a memory operand; argh! */
24eab124
AM		 4178 as_bad (_("invalid char %s beginning operand %d `%s'"),
4179 output_invalid (*op_string),
4180 this_operand + 1,
4181 op_string);
4182 return 0;
4183 }
47926f60 4184 return 1; /* Normal return. */
252b5132
RH		 4185}
4186\f
ee7fcc42
AM		 4187/* md_estimate_size_before_relax()
4188
4189 Called just before relax() for rs_machine_dependent frags. The x86
4190 assembler uses these frags to handle variable size jump
4191 instructions.
4192
4193 Any symbol that is now undefined will not become defined.
4194 Return the correct fr_subtype in the frag.
4195 Return the initial "guess for variable size of frag" to caller.
4196 The guess is actually the growth beyond the fixed part. Whatever
4197 we do to grow the fixed or variable part contributes to our
4198 returned value. */
4199
252b5132
RH		 4200int
4201md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 4202 fragS *fragP;
4203 segT segment;
252b5132 4204{
252b5132 4205 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 4206 check for un-relaxable symbols. On an ELF system, we can't relax
4207 an externally visible symbol, because it may be overridden by a
4208 shared library. */
4209 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 4210#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
b98ef147
AM		 4211 || S_IS_EXTERNAL (fragP->fr_symbol)
4212 || S_IS_WEAK (fragP->fr_symbol)
4213#endif
4214 )
252b5132 4215 {
b98ef147
AM		 4216 /* Symbol is undefined in this segment, or we need to keep a
4217 reloc so that weak symbols can be overridden. */
4218 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f3c180ae 4219 RELOC_ENUM reloc_type;
ee7fcc42
AM		 4220 unsigned char *opcode;
4221 int old_fr_fix;
f6af82bd 4222
ee7fcc42
AM		 4223 if (fragP->fr_var != NO_RELOC)
4224 reloc_type = fragP->fr_var;
b98ef147 4225 else if (size == 2)
f6af82bd
AM		 4226 reloc_type = BFD_RELOC_16_PCREL;
4227 else
4228 reloc_type = BFD_RELOC_32_PCREL;
252b5132 4229
ee7fcc42
AM		 4230 old_fr_fix = fragP->fr_fix;
4231 opcode = (unsigned char *) fragP->fr_opcode;
4232
fddf5b5b 4233 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 4234 {
fddf5b5b
AM		 4235 case UNCOND_JUMP:
4236 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 4237 opcode[0] = 0xe9;
252b5132 4238 fragP->fr_fix += size;
062cd5e7
AS		 4239 fix_new (fragP, old_fr_fix, size,
4240 fragP->fr_symbol,
4241 fragP->fr_offset, 1,
4242 reloc_type);
252b5132
RH		 4243 break;
4244
fddf5b5b 4245 case COND_JUMP86:
412167cb
AM		 4246 if (size == 2
4247 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 4248 {
4249 /* Negate the condition, and branch past an
4250 unconditional jump. */
4251 opcode[0] ^= 1;
4252 opcode[1] = 3;
4253 /* Insert an unconditional jump. */
4254 opcode[2] = 0xe9;
4255 /* We added two extra opcode bytes, and have a two byte
4256 offset. */
4257 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 4258 fix_new (fragP, old_fr_fix + 2, 2,
4259 fragP->fr_symbol,
4260 fragP->fr_offset, 1,
4261 reloc_type);
fddf5b5b
AM		 4262 break;
4263 }
4264 /* Fall through. */
4265
4266 case COND_JUMP:
412167cb
AM		 4267 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
4268 {
4269 fragP->fr_fix += 1;
4270 fix_new (fragP, old_fr_fix, 1,
4271 fragP->fr_symbol,
4272 fragP->fr_offset, 1,
4273 BFD_RELOC_8_PCREL);
4274 break;
4275 }
93c2a809 4276
24eab124 4277 /* This changes the byte-displacement jump 0x7N
fddf5b5b 4278 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 4279 opcode[1] = opcode[0] + 0x10;
f6af82bd 4280 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 4281 /* We've added an opcode byte. */
4282 fragP->fr_fix += 1 + size;
062cd5e7
AS		 4283 fix_new (fragP, old_fr_fix + 1, size,
4284 fragP->fr_symbol,
4285 fragP->fr_offset, 1,
4286 reloc_type);
252b5132 4287 break;
fddf5b5b
AM		 4288
4289 default:
4290 BAD_CASE (fragP->fr_subtype);
4291 break;
252b5132
RH		 4292 }
4293 frag_wane (fragP);
ee7fcc42 4294 return fragP->fr_fix - old_fr_fix;
252b5132 4295 }
93c2a809 4296
93c2a809
AM		 4297 /* Guess size depending on current relax state. Initially the relax
4298 state will correspond to a short jump and we return 1, because
4299 the variable part of the frag (the branch offset) is one byte
4300 long. However, we can relax a section more than once and in that
4301 case we must either set fr_subtype back to the unrelaxed state,
4302 or return the value for the appropriate branch. */
4303 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 4304}
4305
47926f60
KH		 4306/* Called after relax() is finished.
4307
4308 In: Address of frag.
4309 fr_type == rs_machine_dependent.
4310 fr_subtype is what the address relaxed to.
4311
4312 Out: Any fixSs and constants are set up.
4313 Caller will turn frag into a ".space 0". */
4314
252b5132
RH		 4315#ifndef BFD_ASSEMBLER
4316void
4317md_convert_frag (headers, sec, fragP)
a04b544b
ILT		 4318 object_headers *headers ATTRIBUTE_UNUSED;
4319 segT sec ATTRIBUTE_UNUSED;
29b0f896 4320 fragS *fragP;
252b5132
RH		 4321#else
4322void
4323md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 4324 bfd *abfd ATTRIBUTE_UNUSED;
4325 segT sec ATTRIBUTE_UNUSED;
29b0f896 4326 fragS *fragP;
252b5132
RH		 4327#endif
4328{
29b0f896 4329 unsigned char *opcode;
252b5132 4330 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 4331 offsetT target_address;
4332 offsetT opcode_address;
252b5132 4333 unsigned int extension = 0;
847f7ad4 4334 offsetT displacement_from_opcode_start;
252b5132
RH		 4335
4336 opcode = (unsigned char *) fragP->fr_opcode;
4337
47926f60 4338 /* Address we want to reach in file space. */
252b5132 4339 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 4340
47926f60 4341 /* Address opcode resides at in file space. */
252b5132
RH		 4342 opcode_address = fragP->fr_address + fragP->fr_fix;
4343
47926f60 4344 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 4345 displacement_from_opcode_start = target_address - opcode_address;
4346
fddf5b5b 4347 if ((fragP->fr_subtype & BIG) == 0)
252b5132 4348 {
47926f60
KH		 4349 /* Don't have to change opcode. */
4350 extension = 1; /* 1 opcode + 1 displacement */
252b5132 4351 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 4352 }
4353 else
4354 {
4355 if (no_cond_jump_promotion
4356 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4357 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
252b5132 4358
fddf5b5b
AM		 4359 switch (fragP->fr_subtype)
4360 {
4361 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
4362 extension = 4; /* 1 opcode + 4 displacement */
4363 opcode[0] = 0xe9;
4364 where_to_put_displacement = &opcode[1];
4365 break;
252b5132 4366
fddf5b5b
AM		 4367 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
4368 extension = 2; /* 1 opcode + 2 displacement */
4369 opcode[0] = 0xe9;
4370 where_to_put_displacement = &opcode[1];
4371 break;
252b5132 4372
fddf5b5b
AM		 4373 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
4374 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
4375 extension = 5; /* 2 opcode + 4 displacement */
4376 opcode[1] = opcode[0] + 0x10;
4377 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4378 where_to_put_displacement = &opcode[2];
4379 break;
252b5132 4380
fddf5b5b
AM		 4381 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
4382 extension = 3; /* 2 opcode + 2 displacement */
4383 opcode[1] = opcode[0] + 0x10;
4384 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4385 where_to_put_displacement = &opcode[2];
4386 break;
252b5132 4387
fddf5b5b
AM		 4388 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
4389 extension = 4;
4390 opcode[0] ^= 1;
4391 opcode[1] = 3;
4392 opcode[2] = 0xe9;
4393 where_to_put_displacement = &opcode[3];
4394 break;
4395
4396 default:
4397 BAD_CASE (fragP->fr_subtype);
4398 break;
4399 }
252b5132 4400 }
fddf5b5b 4401
47926f60 4402 /* Now put displacement after opcode. */
252b5132
RH		 4403 md_number_to_chars ((char *) where_to_put_displacement,
4404 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 4405 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 4406 fragP->fr_fix += extension;
4407}
4408\f
47926f60
KH		 4409/* Size of byte displacement jmp. */
4410int md_short_jump_size = 2;
4411
4412/* Size of dword displacement jmp. */
4413int md_long_jump_size = 5;
252b5132 4414
47926f60
KH		 4415/* Size of relocation record. */
4416const int md_reloc_size = 8;
252b5132
RH		 4417
4418void
4419md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4420 char *ptr;
4421 addressT from_addr, to_addr;
ab9da554
ILT		 4422 fragS *frag ATTRIBUTE_UNUSED;
4423 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4424{
847f7ad4 4425 offsetT offset;
252b5132
RH		 4426
4427 offset = to_addr - (from_addr + 2);
47926f60
KH		 4428 /* Opcode for byte-disp jump. */
4429 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 4430 md_number_to_chars (ptr + 1, (valueT) offset, 1);
4431}
4432
4433void
4434md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4435 char *ptr;
4436 addressT from_addr, to_addr;
a38cf1db
AM		 4437 fragS *frag ATTRIBUTE_UNUSED;
4438 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4439{
847f7ad4 4440 offsetT offset;
252b5132 4441
a38cf1db
AM		 4442 offset = to_addr - (from_addr + 5);
4443 md_number_to_chars (ptr, (valueT) 0xe9, 1);
4444 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 4445}
4446\f
4447/* Apply a fixup (fixS) to segment data, once it has been determined
4448 by our caller that we have all the info we need to fix it up.
4449
4450 On the 386, immediates, displacements, and data pointers are all in
4451 the same (little-endian) format, so we don't need to care about which
4452 we are handling. */
4453
94f592af
NC		 4454void
4455md_apply_fix3 (fixP, valP, seg)
47926f60
KH		 4456 /* The fix we're to put in. */
4457 fixS *fixP;
47926f60 4458 /* Pointer to the value of the bits. */
c6682705 4459 valueT *valP;
47926f60
KH		 4460 /* Segment fix is from. */
4461 segT seg ATTRIBUTE_UNUSED;
252b5132 4462{
94f592af 4463 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 4464 valueT value = *valP;
252b5132 4465
e1b283bb 4466#if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
93382f6d
AM		 4467 if (fixP->fx_pcrel)
4468 {
4469 switch (fixP->fx_r_type)
4470 {
5865bb77
ILT		 4471 default:
4472 break;
4473
93382f6d
AM		 4474 case BFD_RELOC_32:
4475 fixP->fx_r_type = BFD_RELOC_32_PCREL;
4476 break;
4477 case BFD_RELOC_16:
4478 fixP->fx_r_type = BFD_RELOC_16_PCREL;
4479 break;
4480 case BFD_RELOC_8:
4481 fixP->fx_r_type = BFD_RELOC_8_PCREL;
4482 break;
4483 }
4484 }
252b5132 4485
0723899b
ILT		 4486 /* This is a hack. There should be a better way to handle this.
4487 This covers for the fact that bfd_install_relocation will
4488 subtract the current location (for partial_inplace, PC relative
4489 relocations); see more below. */
93382f6d
AM		 4490 if ((fixP->fx_r_type == BFD_RELOC_32_PCREL
4491 || fixP->fx_r_type == BFD_RELOC_16_PCREL
4492 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7c44d1d3 4493 && fixP->fx_addsy && !use_rela_relocations)
252b5132
RH		 4494 {
4495#ifndef OBJ_AOUT
4496 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4497#ifdef TE_PE
4498 || OUTPUT_FLAVOR == bfd_target_coff_flavour
4499#endif
4500 )
4501 value += fixP->fx_where + fixP->fx_frag->fr_address;
4502#endif
4503#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2f66722d 4504 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
252b5132 4505 {
2f66722d
AM		 4506 segT fseg = S_GET_SEGMENT (fixP->fx_addsy);
4507
4508 if ((fseg == seg
4509 || (symbol_section_p (fixP->fx_addsy)
4510 && fseg != absolute_section))
29b0f896
AM		 4511 && !S_IS_EXTERNAL (fixP->fx_addsy)
4512 && !S_IS_WEAK (fixP->fx_addsy)
2f66722d 4513 && S_IS_DEFINED (fixP->fx_addsy)
29b0f896 4514 && !S_IS_COMMON (fixP->fx_addsy))
2f66722d
AM		 4515 {
4516 /* Yes, we add the values in twice. This is because
4517 bfd_perform_relocation subtracts them out again. I think
4518 bfd_perform_relocation is broken, but I don't dare change
4519 it. FIXME. */
4520 value += fixP->fx_where + fixP->fx_frag->fr_address;
4521 }
252b5132
RH		 4522 }
4523#endif
4524#if defined (OBJ_COFF) && defined (TE_PE)
4525 /* For some reason, the PE format does not store a section
24eab124 4526 address offset for a PC relative symbol. */
252b5132
RH		 4527 if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
4528 value += md_pcrel_from (fixP);
4529#endif
4530 }
4531
4532 /* Fix a few things - the dynamic linker expects certain values here,
47926f60 4533 and we must not dissappoint it. */
252b5132
RH		 4534#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4535 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4536 && fixP->fx_addsy)
47926f60
KH		 4537 switch (fixP->fx_r_type)
4538 {
4539 case BFD_RELOC_386_PLT32:
3e73aa7c 4540 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 4541 /* Make the jump instruction point to the address of the operand. At
4542 runtime we merely add the offset to the actual PLT entry. */
4543 value = -4;
4544 break;
4545 case BFD_RELOC_386_GOTPC:
4546
4547/* This is tough to explain. We end up with this one if we have
252b5132
RH		 4548 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
4549 * here is to obtain the absolute address of the GOT, and it is strongly
4550 * preferable from a performance point of view to avoid using a runtime
c3332e24 4551 * relocation for this. The actual sequence of instructions often look
252b5132 4552 * something like:
c3332e24 4553 *
24eab124 4554 * call .L66
252b5132 4555 * .L66:
24eab124
AM		 4556 * popl %ebx
4557 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
c3332e24 4558 *
24eab124 4559 * The call and pop essentially return the absolute address of
252b5132
RH		 4560 * the label .L66 and store it in %ebx. The linker itself will
4561 * ultimately change the first operand of the addl so that %ebx points to
4562 * the GOT, but to keep things simple, the .o file must have this operand
4563 * set so that it generates not the absolute address of .L66, but the
4564 * absolute address of itself. This allows the linker itself simply
4565 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
4566 * added in, and the addend of the relocation is stored in the operand
4567 * field for the instruction itself.
c3332e24 4568 *
24eab124 4569 * Our job here is to fix the operand so that it would add the correct
252b5132
RH		 4570 * offset so that %ebx would point to itself. The thing that is tricky is
4571 * that .-.L66 will point to the beginning of the instruction, so we need
4572 * to further modify the operand so that it will point to itself.
4573 * There are other cases where you have something like:
c3332e24 4574 *
24eab124 4575 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
c3332e24 4576 *
252b5132 4577 * and here no correction would be required. Internally in the assembler
c3332e24 4578 * we treat operands of this form as not being pcrel since the '.' is
252b5132
RH		 4579 * explicitly mentioned, and I wonder whether it would simplify matters
4580 * to do it this way. Who knows. In earlier versions of the PIC patches,
4581 * the pcrel_adjust field was used to store the correction, but since the
47926f60
KH		 4582 * expression is not pcrel, I felt it would be confusing to do it this
4583 * way. */
4584
4585 value -= 1;
4586 break;
4587 case BFD_RELOC_386_GOT32:
13ae64f3
JJ		 4588 case BFD_RELOC_386_TLS_GD:
4589 case BFD_RELOC_386_TLS_LDM:
4590 case BFD_RELOC_386_TLS_LDO_32:
4591 case BFD_RELOC_386_TLS_IE_32:
4592 case BFD_RELOC_386_TLS_LE_32:
4593 case BFD_RELOC_386_TLS_LE:
3e73aa7c 4594 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 4595 value = 0; /* Fully resolved at runtime. No addend. */
4596 break;
4597 case BFD_RELOC_386_GOTOFF:
3e73aa7c 4598 case BFD_RELOC_X86_64_GOTPCREL:
47926f60
KH		 4599 break;
4600
4601 case BFD_RELOC_VTABLE_INHERIT:
4602 case BFD_RELOC_VTABLE_ENTRY:
4603 fixP->fx_done = 0;
94f592af 4604 return;
47926f60
KH		 4605
4606 default:
4607 break;
4608 }
4609#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 4610 *valP = value;
47926f60 4611#endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
3e73aa7c 4612
3e73aa7c 4613 /* Are we finished with this relocation now? */
c6682705 4614 if (fixP->fx_addsy == NULL)
3e73aa7c 4615 fixP->fx_done = 1;
94f592af 4616#ifdef BFD_ASSEMBLER
3e73aa7c
JH		 4617 else if (use_rela_relocations)
4618 {
4619 fixP->fx_no_overflow = 1;
062cd5e7
AS		 4620 /* Remember value for tc_gen_reloc. */
4621 fixP->fx_addnumber = value;
3e73aa7c
JH		 4622 value = 0;
4623 }
3e73aa7c 4624#endif
94f592af 4625 md_number_to_chars (p, value, fixP->fx_size);
252b5132 4626}
252b5132 4627\f
252b5132
RH		 4628#define MAX_LITTLENUMS 6
4629
47926f60
KH		 4630/* Turn the string pointed to by litP into a floating point constant
4631 of type TYPE, and emit the appropriate bytes. The number of
4632 LITTLENUMS emitted is stored in *SIZEP. An error message is
4633 returned, or NULL on OK. */
4634
252b5132
RH		 4635char *
4636md_atof (type, litP, sizeP)
2ab9b79e 4637 int type;
252b5132
RH		 4638 char *litP;
4639 int *sizeP;
4640{
4641 int prec;
4642 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4643 LITTLENUM_TYPE *wordP;
4644 char *t;
4645
4646 switch (type)
4647 {
4648 case 'f':
4649 case 'F':
4650 prec = 2;
4651 break;
4652
4653 case 'd':
4654 case 'D':
4655 prec = 4;
4656 break;
4657
4658 case 'x':
4659 case 'X':
4660 prec = 5;
4661 break;
4662
4663 default:
4664 *sizeP = 0;
4665 return _("Bad call to md_atof ()");
4666 }
4667 t = atof_ieee (input_line_pointer, type, words);
4668 if (t)
4669 input_line_pointer = t;
4670
4671 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4672 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4673 the bigendian 386. */
4674 for (wordP = words + prec - 1; prec--;)
4675 {
4676 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
4677 litP += sizeof (LITTLENUM_TYPE);
4678 }
4679 return 0;
4680}
4681\f
4682char output_invalid_buf[8];
4683
252b5132
RH		 4684static char *
4685output_invalid (c)
4686 int c;
4687{
3882b010 4688 if (ISPRINT (c))
252b5132
RH		 4689 sprintf (output_invalid_buf, "'%c'", c);
4690 else
4691 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
4692 return output_invalid_buf;
4693}
4694
af6bdddf 4695/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 4696
4697static const reg_entry *
4698parse_register (reg_string, end_op)
4699 char *reg_string;
4700 char **end_op;
4701{
af6bdddf
AM		 4702 char *s = reg_string;
4703 char *p;
252b5132
RH		 4704 char reg_name_given[MAX_REG_NAME_SIZE + 1];
4705 const reg_entry *r;
4706
4707 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4708 if (*s == REGISTER_PREFIX)
4709 ++s;
4710
4711 if (is_space_char (*s))
4712 ++s;
4713
4714 p = reg_name_given;
af6bdddf 4715 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 4716 {
4717 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 4718 return (const reg_entry *) NULL;
4719 s++;
252b5132
RH		 4720 }
4721
6588847e
DN		 4722 /* For naked regs, make sure that we are not dealing with an identifier.
4723 This prevents confusing an identifier like `eax_var' with register
4724 `eax'. */
4725 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
4726 return (const reg_entry *) NULL;
4727
af6bdddf 4728 *end_op = s;
252b5132
RH		 4729
4730 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
4731
5f47d35b 4732 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 4733 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 4734 {
5f47d35b
AM		 4735 if (is_space_char (*s))
4736 ++s;
4737 if (*s == '(')
4738 {
af6bdddf 4739 ++s;
5f47d35b
AM		 4740 if (is_space_char (*s))
4741 ++s;
4742 if (*s >= '0' && *s <= '7')
4743 {
4744 r = &i386_float_regtab[*s - '0'];
af6bdddf 4745 ++s;
5f47d35b
AM		 4746 if (is_space_char (*s))
4747 ++s;
4748 if (*s == ')')
4749 {
4750 *end_op = s + 1;
4751 return r;
4752 }
5f47d35b 4753 }
47926f60 4754 /* We have "%st(" then garbage. */
5f47d35b
AM		 4755 return (const reg_entry *) NULL;
4756 }
4757 }
4758
1ae00879 4759 if (r != NULL
29b0f896 4760 && (r->reg_flags & (RegRex64 | RegRex)) != 0
1ae00879
AM		 4761 && flag_code != CODE_64BIT)
4762 {
4763 return (const reg_entry *) NULL;
4764 }
4765
252b5132
RH		 4766 return r;
4767}
4768\f
4cc782b5 4769#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
65172ab8 4770const char *md_shortopts = "kVQ:sq";
252b5132 4771#else
65172ab8 4772const char *md_shortopts = "q";
252b5132 4773#endif
6e0b89ee 4774
252b5132 4775struct option md_longopts[] = {
3e73aa7c
JH		 4776#define OPTION_32 (OPTION_MD_BASE + 0)
4777 {"32", no_argument, NULL, OPTION_32},
6e0b89ee 4778#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3e73aa7c
JH		 4779#define OPTION_64 (OPTION_MD_BASE + 1)
4780 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 4781#endif
252b5132
RH		 4782 {NULL, no_argument, NULL, 0}
4783};
4784size_t md_longopts_size = sizeof (md_longopts);
4785
4786int
4787md_parse_option (c, arg)
4788 int c;
ab9da554 4789 char *arg ATTRIBUTE_UNUSED;
252b5132
RH		 4790{
4791 switch (c)
4792 {
a38cf1db
AM		 4793 case 'q':
4794 quiet_warnings = 1;
252b5132
RH		 4795 break;
4796
4797#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 4798 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4799 should be emitted or not. FIXME: Not implemented. */
4800 case 'Q':
252b5132
RH		 4801 break;
4802
4803 /* -V: SVR4 argument to print version ID. */
4804 case 'V':
4805 print_version_id ();
4806 break;
4807
a38cf1db
AM		 4808 /* -k: Ignore for FreeBSD compatibility. */
4809 case 'k':
252b5132 4810 break;
4cc782b5
ILT		 4811
4812 case 's':
4813 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 4814 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 4815 break;
6e0b89ee 4816
3e73aa7c
JH		 4817 case OPTION_64:
4818 {
4819 const char **list, **l;
4820
3e73aa7c
JH		 4821 list = bfd_target_list ();
4822 for (l = list; *l != NULL; l++)
6e0b89ee
AM		 4823 if (strcmp (*l, "elf64-x86-64") == 0)
4824 {
4825 default_arch = "x86_64";
4826 break;
4827 }
3e73aa7c 4828 if (*l == NULL)
6e0b89ee 4829 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 4830 free (list);
4831 }
4832 break;
4833#endif
252b5132 4834
6e0b89ee
AM		 4835 case OPTION_32:
4836 default_arch = "i386";
4837 break;
4838
252b5132
RH		 4839 default:
4840 return 0;
4841 }
4842 return 1;
4843}
4844
4845void
4846md_show_usage (stream)
4847 FILE *stream;
4848{
4cc782b5
ILT		 4849#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4850 fprintf (stream, _("\
a38cf1db
AM		 4851 -Q ignored\n\
4852 -V print assembler version number\n\
4853 -k ignored\n\
4854 -q quieten some warnings\n\
4855 -s ignored\n"));
4856#else
4857 fprintf (stream, _("\
4858 -q quieten some warnings\n"));
4cc782b5 4859#endif
252b5132
RH		 4860}
4861
4862#ifdef BFD_ASSEMBLER
3e73aa7c
JH		 4863#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4864 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 4865
4866/* Pick the target format to use. */
4867
47926f60 4868const char *
252b5132
RH		 4869i386_target_format ()
4870{
3e73aa7c
JH		 4871 if (!strcmp (default_arch, "x86_64"))
4872 set_code_flag (CODE_64BIT);
4873 else if (!strcmp (default_arch, "i386"))
4874 set_code_flag (CODE_32BIT);
4875 else
4876 as_fatal (_("Unknown architecture"));
252b5132
RH		 4877 switch (OUTPUT_FLAVOR)
4878 {
4c63da97
AM		 4879#ifdef OBJ_MAYBE_AOUT
4880 case bfd_target_aout_flavour:
47926f60 4881 return AOUT_TARGET_FORMAT;
4c63da97
AM		 4882#endif
4883#ifdef OBJ_MAYBE_COFF
252b5132
RH		 4884 case bfd_target_coff_flavour:
4885 return "coff-i386";
4c63da97 4886#endif
3e73aa7c 4887#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 4888 case bfd_target_elf_flavour:
3e73aa7c 4889 {
e5cb08ac
KH		 4890 if (flag_code == CODE_64BIT)
4891 use_rela_relocations = 1;
4892 return flag_code == CODE_64BIT ? "elf64-x86-64" : "elf32-i386";
3e73aa7c 4893 }
4c63da97 4894#endif
252b5132
RH		 4895 default:
4896 abort ();
4897 return NULL;
4898 }
4899}
4900
47926f60 4901#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 4902
4903#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4904void i386_elf_emit_arch_note ()
4905{
4906 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4907 && cpu_arch_name != NULL)
4908 {
4909 char *p;
4910 asection *seg = now_seg;
4911 subsegT subseg = now_subseg;
4912 Elf_Internal_Note i_note;
4913 Elf_External_Note e_note;
4914 asection *note_secp;
4915 int len;
4916
4917 /* Create the .note section. */
4918 note_secp = subseg_new (".note", 0);
4919 bfd_set_section_flags (stdoutput,
4920 note_secp,
4921 SEC_HAS_CONTENTS | SEC_READONLY);
4922
4923 /* Process the arch string. */
4924 len = strlen (cpu_arch_name);
4925
4926 i_note.namesz = len + 1;
4927 i_note.descsz = 0;
4928 i_note.type = NT_ARCH;
4929 p = frag_more (sizeof (e_note.namesz));
4930 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
4931 p = frag_more (sizeof (e_note.descsz));
4932 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
4933 p = frag_more (sizeof (e_note.type));
4934 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
4935 p = frag_more (len + 1);
4936 strcpy (p, cpu_arch_name);
4937
4938 frag_align (2, 0, 0);
4939
4940 subseg_set (seg, subseg);
4941 }
4942}
4943#endif
47926f60 4944#endif /* BFD_ASSEMBLER */
252b5132 4945\f
252b5132
RH		 4946symbolS *
4947md_undefined_symbol (name)
4948 char *name;
4949{
18dc2407
ILT		 4950 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
4951 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
4952 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
4953 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 4954 {
4955 if (!GOT_symbol)
4956 {
4957 if (symbol_find (name))
4958 as_bad (_("GOT already in symbol table"));
4959 GOT_symbol = symbol_new (name, undefined_section,
4960 (valueT) 0, &zero_address_frag);
4961 };
4962 return GOT_symbol;
4963 }
252b5132
RH		 4964 return 0;
4965}
4966
4967/* Round up a section size to the appropriate boundary. */
47926f60 4968
252b5132
RH		 4969valueT
4970md_section_align (segment, size)
ab9da554 4971 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 4972 valueT size;
4973{
252b5132 4974#ifdef BFD_ASSEMBLER
4c63da97
AM		 4975#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4976 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
4977 {
4978 /* For a.out, force the section size to be aligned. If we don't do
4979 this, BFD will align it for us, but it will not write out the
4980 final bytes of the section. This may be a bug in BFD, but it is
4981 easier to fix it here since that is how the other a.out targets
4982 work. */
4983 int align;
4984
4985 align = bfd_get_section_alignment (stdoutput, segment);
4986 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
4987 }
252b5132
RH		 4988#endif
4989#endif
4990
4991 return size;
4992}
4993
4994/* On the i386, PC-relative offsets are relative to the start of the
4995 next instruction. That is, the address of the offset, plus its
4996 size, since the offset is always the last part of the insn. */
4997
4998long
4999md_pcrel_from (fixP)
5000 fixS *fixP;
5001{
5002 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
5003}
5004
5005#ifndef I386COFF
5006
5007static void
5008s_bss (ignore)
ab9da554 5009 int ignore ATTRIBUTE_UNUSED;
252b5132 5010{
29b0f896 5011 int temp;
252b5132
RH		 5012
5013 temp = get_absolute_expression ();
5014 subseg_set (bss_section, (subsegT) temp);
5015 demand_empty_rest_of_line ();
5016}
5017
5018#endif
5019
252b5132
RH		 5020#ifdef BFD_ASSEMBLER
5021
5022void
5023i386_validate_fix (fixp)
5024 fixS *fixp;
5025{
5026 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
5027 {
3e73aa7c 5028 /* GOTOFF relocation are nonsense in 64bit mode. */
23df1078
JH		 5029 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
5030 {
5031 if (flag_code != CODE_64BIT)
5032 abort ();
5033 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
5034 }
5035 else
5036 {
5037 if (flag_code == CODE_64BIT)
5038 abort ();
5039 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
5040 }
252b5132
RH		 5041 fixp->fx_subsy = 0;
5042 }
5043}
5044
252b5132
RH		 5045arelent *
5046tc_gen_reloc (section, fixp)
ab9da554 5047 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 5048 fixS *fixp;
5049{
5050 arelent *rel;
5051 bfd_reloc_code_real_type code;
5052
5053 switch (fixp->fx_r_type)
5054 {
3e73aa7c
JH		 5055 case BFD_RELOC_X86_64_PLT32:
5056 case BFD_RELOC_X86_64_GOT32:
5057 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 5058 case BFD_RELOC_386_PLT32:
5059 case BFD_RELOC_386_GOT32:
5060 case BFD_RELOC_386_GOTOFF:
5061 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 5062 case BFD_RELOC_386_TLS_GD:
5063 case BFD_RELOC_386_TLS_LDM:
5064 case BFD_RELOC_386_TLS_LDO_32:
5065 case BFD_RELOC_386_TLS_IE_32:
5066 case BFD_RELOC_386_TLS_LE_32:
5067 case BFD_RELOC_386_TLS_LE:
3e73aa7c 5068 case BFD_RELOC_X86_64_32S:
252b5132
RH		 5069 case BFD_RELOC_RVA:
5070 case BFD_RELOC_VTABLE_ENTRY:
5071 case BFD_RELOC_VTABLE_INHERIT:
5072 code = fixp->fx_r_type;
5073 break;
5074 default:
93382f6d 5075 if (fixp->fx_pcrel)
252b5132 5076 {
93382f6d
AM		 5077 switch (fixp->fx_size)
5078 {
5079 default:
b091f402
AM		 5080 as_bad_where (fixp->fx_file, fixp->fx_line,
5081 _("can not do %d byte pc-relative relocation"),
5082 fixp->fx_size);
93382f6d
AM		 5083 code = BFD_RELOC_32_PCREL;
5084 break;
5085 case 1: code = BFD_RELOC_8_PCREL; break;
5086 case 2: code = BFD_RELOC_16_PCREL; break;
5087 case 4: code = BFD_RELOC_32_PCREL; break;
5088 }
5089 }
5090 else
5091 {
5092 switch (fixp->fx_size)
5093 {
5094 default:
b091f402
AM		 5095 as_bad_where (fixp->fx_file, fixp->fx_line,
5096 _("can not do %d byte relocation"),
5097 fixp->fx_size);
93382f6d
AM		 5098 code = BFD_RELOC_32;
5099 break;
5100 case 1: code = BFD_RELOC_8; break;
5101 case 2: code = BFD_RELOC_16; break;
5102 case 4: code = BFD_RELOC_32; break;
937149dd 5103#ifdef BFD64
3e73aa7c 5104 case 8: code = BFD_RELOC_64; break;
937149dd 5105#endif
93382f6d 5106 }
252b5132
RH		 5107 }
5108 break;
5109 }
252b5132
RH		 5110
5111 if (code == BFD_RELOC_32
5112 && GOT_symbol
5113 && fixp->fx_addsy == GOT_symbol)
3e73aa7c
JH		 5114 {
5115 /* We don't support GOTPC on 64bit targets. */
5116 if (flag_code == CODE_64BIT)
bfb32b52 5117 abort ();
3e73aa7c
JH		 5118 code = BFD_RELOC_386_GOTPC;
5119 }
252b5132
RH		 5120
5121 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 5122 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5123 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 5124
5125 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
3e73aa7c
JH		 5126 if (!use_rela_relocations)
5127 {
5128 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5129 vtable entry to be used in the relocation's section offset. */
5130 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5131 rel->address = fixp->fx_offset;
252b5132 5132
c6682705 5133 rel->addend = 0;
3e73aa7c
JH		 5134 }
5135 /* Use the rela in 64bit mode. */
252b5132 5136 else
3e73aa7c 5137 {
062cd5e7
AS		 5138 if (!fixp->fx_pcrel)
5139 rel->addend = fixp->fx_offset;
5140 else
5141 switch (code)
5142 {
5143 case BFD_RELOC_X86_64_PLT32:
5144 case BFD_RELOC_X86_64_GOT32:
5145 case BFD_RELOC_X86_64_GOTPCREL:
5146 rel->addend = fixp->fx_offset - fixp->fx_size;
5147 break;
5148 default:
5149 rel->addend = (section->vma
5150 - fixp->fx_size
5151 + fixp->fx_addnumber
5152 + md_pcrel_from (fixp));
5153 break;
5154 }
3e73aa7c
JH		 5155 }
5156
252b5132
RH		 5157 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
5158 if (rel->howto == NULL)
5159 {
5160 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 5161 _("cannot represent relocation type %s"),
252b5132
RH		 5162 bfd_get_reloc_code_name (code));
5163 /* Set howto to a garbage value so that we can keep going. */
5164 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
5165 assert (rel->howto != NULL);
5166 }
5167
5168 return rel;
5169}
5170
29b0f896 5171#else /* !BFD_ASSEMBLER */
252b5132
RH		 5172
5173#if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
5174void
5175tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
5176 char *where;
5177 fixS *fixP;
5178 relax_addressT segment_address_in_file;
5179{
47926f60
KH		 5180 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
5181 Out: GNU LD relocation length code: 0, 1, or 2. */
252b5132 5182
47926f60 5183 static const unsigned char nbytes_r_length[] = { 42, 0, 1, 42, 2 };
252b5132
RH		 5184 long r_symbolnum;
5185
5186 know (fixP->fx_addsy != NULL);
5187
5188 md_number_to_chars (where,
5189 (valueT) (fixP->fx_frag->fr_address
5190 + fixP->fx_where - segment_address_in_file),
5191 4);
5192
5193 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
5194 ? S_GET_TYPE (fixP->fx_addsy)
5195 : fixP->fx_addsy->sy_number);
5196
5197 where[6] = (r_symbolnum >> 16) & 0x0ff;
5198 where[5] = (r_symbolnum >> 8) & 0x0ff;
5199 where[4] = r_symbolnum & 0x0ff;
5200 where[7] = ((((!S_IS_DEFINED (fixP->fx_addsy)) << 3) & 0x08)
5201 | ((nbytes_r_length[fixP->fx_size] << 1) & 0x06)
5202 | (((fixP->fx_pcrel << 0) & 0x01) & 0x0f));
5203}
5204
47926f60 5205#endif /* OBJ_AOUT or OBJ_BOUT. */
252b5132
RH		 5206
5207#if defined (I386COFF)
5208
5209short
5210tc_coff_fix2rtype (fixP)
5211 fixS *fixP;
5212{
5213 if (fixP->fx_r_type == R_IMAGEBASE)
5214 return R_IMAGEBASE;
5215
5216 return (fixP->fx_pcrel ?
5217 (fixP->fx_size == 1 ? R_PCRBYTE :
5218 fixP->fx_size == 2 ? R_PCRWORD :
5219 R_PCRLONG) :
5220 (fixP->fx_size == 1 ? R_RELBYTE :
5221 fixP->fx_size == 2 ? R_RELWORD :
5222 R_DIR32));
5223}
5224
5225int
5226tc_coff_sizemachdep (frag)
5227 fragS *frag;
5228{
5229 if (frag->fr_next)
5230 return (frag->fr_next->fr_address - frag->fr_address);
5231 else
5232 return 0;
5233}
5234
47926f60 5235#endif /* I386COFF */
252b5132 5236
29b0f896 5237#endif /* !BFD_ASSEMBLER */
64a0c779
DN		 5238\f
5239/* Parse operands using Intel syntax. This implements a recursive descent
5240 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5241 Programmer's Guide.
5242
5243 FIXME: We do not recognize the full operand grammar defined in the MASM
5244 documentation. In particular, all the structure/union and
5245 high-level macro operands are missing.
5246
5247 Uppercase words are terminals, lower case words are non-terminals.
5248 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5249 bars '|' denote choices. Most grammar productions are implemented in
5250 functions called 'intel_<production>'.
5251
5252 Initial production is 'expr'.
5253
64a0c779
DN		 5254 addOp + | -
5255
5256 alpha [a-zA-Z]
5257
5258 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5259
5260 constant digits [[ radixOverride ]]
5261
5262 dataType BYTE | WORD | DWORD | QWORD | XWORD
5263
5264 digits decdigit
b77a7acd
AJ		 5265 | digits decdigit
5266 | digits hexdigit
64a0c779
DN		 5267
5268 decdigit [0-9]
5269
5270 e05 e05 addOp e06
b77a7acd 5271 | e06
64a0c779
DN		 5272
5273 e06 e06 mulOp e09
b77a7acd 5274 | e09
64a0c779
DN		 5275
5276 e09 OFFSET e10
5277 | e09 PTR e10
5278 | e09 : e10
5279 | e10
5280
5281 e10 e10 [ expr ]
b77a7acd 5282 | e11
64a0c779
DN		 5283
5284 e11 ( expr )
b77a7acd 5285 | [ expr ]
64a0c779
DN		 5286 | constant
5287 | dataType
5288 | id
5289 | $
5290 | register
5291
5292 => expr SHORT e05
b77a7acd 5293 | e05
64a0c779
DN		 5294
5295 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 5296 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 5297
5298 hexdigit a | b | c | d | e | f
b77a7acd 5299 | A | B | C | D | E | F
64a0c779
DN		 5300
5301 id alpha
b77a7acd 5302 | id alpha
64a0c779
DN		 5303 | id decdigit
5304
5305 mulOp * | / | MOD
5306
5307 quote " | '
5308
5309 register specialRegister
b77a7acd 5310 | gpRegister
64a0c779
DN		 5311 | byteRegister
5312
5313 segmentRegister CS | DS | ES | FS | GS | SS
5314
5315 specialRegister CR0 | CR2 | CR3
b77a7acd 5316 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 5317 | TR3 | TR4 | TR5 | TR6 | TR7
5318
64a0c779
DN		 5319 We simplify the grammar in obvious places (e.g., register parsing is
5320 done by calling parse_register) and eliminate immediate left recursion
5321 to implement a recursive-descent parser.
5322
5323 expr SHORT e05
b77a7acd 5324 | e05
64a0c779
DN		 5325
5326 e05 e06 e05'
5327
5328 e05' addOp e06 e05'
b77a7acd 5329 | Empty
64a0c779
DN		 5330
5331 e06 e09 e06'
5332
5333 e06' mulOp e09 e06'
b77a7acd 5334 | Empty
64a0c779
DN		 5335
5336 e09 OFFSET e10 e09'
b77a7acd 5337 | e10 e09'
64a0c779
DN		 5338
5339 e09' PTR e10 e09'
b77a7acd 5340 | : e10 e09'
64a0c779
DN		 5341 | Empty
5342
5343 e10 e11 e10'
5344
5345 e10' [ expr ] e10'
b77a7acd 5346 | Empty
64a0c779
DN		 5347
5348 e11 ( expr )
b77a7acd 5349 | [ expr ]
64a0c779
DN		 5350 | BYTE
5351 | WORD
5352 | DWORD
5353 | QWORD
5354 | XWORD
5355 | .
5356 | $
5357 | register
5358 | id
5359 | constant */
5360
5361/* Parsing structure for the intel syntax parser. Used to implement the
5362 semantic actions for the operand grammar. */
5363struct intel_parser_s
5364 {
5365 char *op_string; /* The string being parsed. */
5366 int got_a_float; /* Whether the operand is a float. */
4a1805b1 5367 int op_modifier; /* Operand modifier. */
64a0c779
DN		 5368 int is_mem; /* 1 if operand is memory reference. */
5369 const reg_entry *reg; /* Last register reference found. */
5370 char *disp; /* Displacement string being built. */
5371 };
5372
5373static struct intel_parser_s intel_parser;
5374
5375/* Token structure for parsing intel syntax. */
5376struct intel_token
5377 {
5378 int code; /* Token code. */
5379 const reg_entry *reg; /* Register entry for register tokens. */
5380 char *str; /* String representation. */
5381 };
5382
5383static struct intel_token cur_token, prev_token;
5384
50705ef4
AM		 5385/* Token codes for the intel parser. Since T_SHORT is already used
5386 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 5387#define T_NIL -1
5388#define T_CONST 1
5389#define T_REG 2
5390#define T_BYTE 3
5391#define T_WORD 4
5392#define T_DWORD 5
5393#define T_QWORD 6
5394#define T_XWORD 7
50705ef4 5395#undef T_SHORT
64a0c779
DN		 5396#define T_SHORT 8
5397#define T_OFFSET 9
5398#define T_PTR 10
5399#define T_ID 11
5400
5401/* Prototypes for intel parser functions. */
5402static int intel_match_token PARAMS ((int code));
cce0cbdc
DN		 5403static void intel_get_token PARAMS ((void));
5404static void intel_putback_token PARAMS ((void));
5405static int intel_expr PARAMS ((void));
5406static int intel_e05 PARAMS ((void));
5407static int intel_e05_1 PARAMS ((void));
5408static int intel_e06 PARAMS ((void));
5409static int intel_e06_1 PARAMS ((void));
5410static int intel_e09 PARAMS ((void));
5411static int intel_e09_1 PARAMS ((void));
5412static int intel_e10 PARAMS ((void));
5413static int intel_e10_1 PARAMS ((void));
5414static int intel_e11 PARAMS ((void));
64a0c779 5415
64a0c779
DN		 5416static int
5417i386_intel_operand (operand_string, got_a_float)
5418 char *operand_string;
5419 int got_a_float;
5420{
5421 int ret;
5422 char *p;
5423
5424 /* Initialize token holders. */
5425 cur_token.code = prev_token.code = T_NIL;
5426 cur_token.reg = prev_token.reg = NULL;
5427 cur_token.str = prev_token.str = NULL;
5428
5429 /* Initialize parser structure. */
e5cb08ac 5430 p = intel_parser.op_string = (char *) malloc (strlen (operand_string) + 1);
64a0c779
DN		 5431 if (p == NULL)
5432 abort ();
5433 strcpy (intel_parser.op_string, operand_string);
5434 intel_parser.got_a_float = got_a_float;
5435 intel_parser.op_modifier = -1;
5436 intel_parser.is_mem = 0;
5437 intel_parser.reg = NULL;
e5cb08ac 5438 intel_parser.disp = (char *) malloc (strlen (operand_string) + 1);
64a0c779
DN		 5439 if (intel_parser.disp == NULL)
5440 abort ();
5441 intel_parser.disp[0] = '\0';
5442
5443 /* Read the first token and start the parser. */
5444 intel_get_token ();
5445 ret = intel_expr ();
5446
5447 if (ret)
5448 {
5449 /* If we found a memory reference, hand it over to i386_displacement
5450 to fill in the rest of the operand fields. */
5451 if (intel_parser.is_mem)
5452 {
5453 if ((i.mem_operands == 1
5454 && (current_templates->start->opcode_modifier & IsString) == 0)
5455 || i.mem_operands == 2)
5456 {
5457 as_bad (_("too many memory references for '%s'"),
5458 current_templates->start->name);
5459 ret = 0;
5460 }
5461 else
5462 {
5463 char *s = intel_parser.disp;
5464 i.mem_operands++;
5465
5466 /* Add the displacement expression. */
5467 if (*s != '\0')
5468 ret = i386_displacement (s, s + strlen (s))
5469 && i386_index_check (s);
5470 }
5471 }
5472
5473 /* Constant and OFFSET expressions are handled by i386_immediate. */
5474 else if (intel_parser.op_modifier == OFFSET_FLAT
5475 || intel_parser.reg == NULL)
5476 ret = i386_immediate (intel_parser.disp);
5477 }
5478
5479 free (p);
5480 free (intel_parser.disp);
5481
5482 return ret;
5483}
5484
64a0c779 5485/* expr SHORT e05
b77a7acd 5486 | e05 */
64a0c779
DN		 5487static int
5488intel_expr ()
5489{
5490 /* expr SHORT e05 */
5491 if (cur_token.code == T_SHORT)
5492 {
5493 intel_parser.op_modifier = SHORT;
5494 intel_match_token (T_SHORT);
5495
5496 return (intel_e05 ());
5497 }
5498
5499 /* expr e05 */
5500 else
5501 return intel_e05 ();
5502}
5503
64a0c779
DN		 5504/* e05 e06 e05'
5505
4a1805b1 5506 e05' addOp e06 e05'
64a0c779
DN		 5507 | Empty */
5508static int
5509intel_e05 ()
5510{
5511 return (intel_e06 () && intel_e05_1 ());
5512}
5513
5514static int
5515intel_e05_1 ()
5516{
5517 /* e05' addOp e06 e05' */
5518 if (cur_token.code == '+' || cur_token.code == '-')
5519 {
5520 strcat (intel_parser.disp, cur_token.str);
5521 intel_match_token (cur_token.code);
5522
5523 return (intel_e06 () && intel_e05_1 ());
5524 }
5525
5526 /* e05' Empty */
5527 else
5528 return 1;
4a1805b1 5529}
64a0c779
DN		 5530
5531/* e06 e09 e06'
5532
5533 e06' mulOp e09 e06'
b77a7acd 5534 | Empty */
64a0c779
DN		 5535static int
5536intel_e06 ()
5537{
5538 return (intel_e09 () && intel_e06_1 ());
5539}
5540
5541static int
5542intel_e06_1 ()
5543{
5544 /* e06' mulOp e09 e06' */
5545 if (cur_token.code == '*' || cur_token.code == '/')
5546 {
5547 strcat (intel_parser.disp, cur_token.str);
5548 intel_match_token (cur_token.code);
5549
5550 return (intel_e09 () && intel_e06_1 ());
5551 }
4a1805b1 5552
64a0c779 5553 /* e06' Empty */
4a1805b1 5554 else
64a0c779
DN		 5555 return 1;
5556}
5557
64a0c779 5558/* e09 OFFSET e10 e09'
b77a7acd 5559 | e10 e09'
64a0c779
DN		 5560
5561 e09' PTR e10 e09'
b77a7acd 5562 | : e10 e09'
64a0c779
DN		 5563 | Empty */
5564static int
5565intel_e09 ()
5566{
5567 /* e09 OFFSET e10 e09' */
5568 if (cur_token.code == T_OFFSET)
5569 {
5570 intel_parser.is_mem = 0;
5571 intel_parser.op_modifier = OFFSET_FLAT;
5572 intel_match_token (T_OFFSET);
5573
5574 return (intel_e10 () && intel_e09_1 ());
5575 }
5576
5577 /* e09 e10 e09' */
5578 else
5579 return (intel_e10 () && intel_e09_1 ());
5580}
5581
5582static int
5583intel_e09_1 ()
5584{
5585 /* e09' PTR e10 e09' */
5586 if (cur_token.code == T_PTR)
5587 {
5588 if (prev_token.code == T_BYTE)
5589 i.suffix = BYTE_MNEM_SUFFIX;
5590
5591 else if (prev_token.code == T_WORD)
5592 {
5593 if (intel_parser.got_a_float == 2) /* "fi..." */
5594 i.suffix = SHORT_MNEM_SUFFIX;
5595 else
5596 i.suffix = WORD_MNEM_SUFFIX;
5597 }
5598
5599 else if (prev_token.code == T_DWORD)
5600 {
5601 if (intel_parser.got_a_float == 1) /* "f..." */
5602 i.suffix = SHORT_MNEM_SUFFIX;
5603 else
5604 i.suffix = LONG_MNEM_SUFFIX;
5605 }
5606
5607 else if (prev_token.code == T_QWORD)
f16b83df
JH		 5608 {
5609 if (intel_parser.got_a_float == 1) /* "f..." */
5610 i.suffix = LONG_MNEM_SUFFIX;
5611 else
3e73aa7c 5612 i.suffix = QWORD_MNEM_SUFFIX;
f16b83df 5613 }
64a0c779
DN		 5614
5615 else if (prev_token.code == T_XWORD)
5616 i.suffix = LONG_DOUBLE_MNEM_SUFFIX;
5617
5618 else
5619 {
5620 as_bad (_("Unknown operand modifier `%s'\n"), prev_token.str);
5621 return 0;
5622 }
5623
5624 intel_match_token (T_PTR);
5625
5626 return (intel_e10 () && intel_e09_1 ());
5627 }
5628
5629 /* e09 : e10 e09' */
5630 else if (cur_token.code == ':')
5631 {
21d6c4af
DN		 5632 /* Mark as a memory operand only if it's not already known to be an
5633 offset expression. */
5634 if (intel_parser.op_modifier != OFFSET_FLAT)
5635 intel_parser.is_mem = 1;
64a0c779
DN		 5636
5637 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5638 }
5639
5640 /* e09' Empty */
5641 else
5642 return 1;
5643}
5644
5645/* e10 e11 e10'
5646
5647 e10' [ expr ] e10'
b77a7acd 5648 | Empty */
64a0c779
DN		 5649static int
5650intel_e10 ()
5651{
5652 return (intel_e11 () && intel_e10_1 ());
5653}
5654
5655static int
5656intel_e10_1 ()
5657{
5658 /* e10' [ expr ] e10' */
5659 if (cur_token.code == '[')
5660 {
5661 intel_match_token ('[');
21d6c4af
DN		 5662
5663 /* Mark as a memory operand only if it's not already known to be an
5664 offset expression. If it's an offset expression, we need to keep
5665 the brace in. */
5666 if (intel_parser.op_modifier != OFFSET_FLAT)
5667 intel_parser.is_mem = 1;
5668 else
5669 strcat (intel_parser.disp, "[");
4a1805b1 5670
64a0c779 5671 /* Add a '+' to the displacement string if necessary. */
21d6c4af
DN		 5672 if (*intel_parser.disp != '\0'
5673 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
64a0c779
DN		 5674 strcat (intel_parser.disp, "+");
5675
21d6c4af
DN		 5676 if (intel_expr () && intel_match_token (']'))
5677 {
5678 /* Preserve brackets when the operand is an offset expression. */
5679 if (intel_parser.op_modifier == OFFSET_FLAT)
5680 strcat (intel_parser.disp, "]");
5681
5682 return intel_e10_1 ();
5683 }
5684 else
5685 return 0;
64a0c779
DN		 5686 }
5687
5688 /* e10' Empty */
5689 else
5690 return 1;
5691}
5692
64a0c779 5693/* e11 ( expr )
b77a7acd 5694 | [ expr ]
64a0c779
DN		 5695 | BYTE
5696 | WORD
5697 | DWORD
5698 | QWORD
5699 | XWORD
4a1805b1 5700 | $
64a0c779
DN		 5701 | .
5702 | register
5703 | id
5704 | constant */
5705static int
5706intel_e11 ()
5707{
5708 /* e11 ( expr ) */
5709 if (cur_token.code == '(')
5710 {
5711 intel_match_token ('(');
5712 strcat (intel_parser.disp, "(");
5713
5714 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 5715 {
5716 strcat (intel_parser.disp, ")");
5717 return 1;
5718 }
64a0c779
DN		 5719 else
5720 return 0;
5721 }
5722
5723 /* e11 [ expr ] */
5724 else if (cur_token.code == '[')
5725 {
5726 intel_match_token ('[');
21d6c4af
DN		 5727
5728 /* Mark as a memory operand only if it's not already known to be an
5729 offset expression. If it's an offset expression, we need to keep
5730 the brace in. */
5731 if (intel_parser.op_modifier != OFFSET_FLAT)
5732 intel_parser.is_mem = 1;
5733 else
5734 strcat (intel_parser.disp, "[");
4a1805b1 5735
64a0c779
DN		 5736 /* Operands for jump/call inside brackets denote absolute addresses. */
5737 if (current_templates->start->opcode_modifier & Jump
5738 || current_templates->start->opcode_modifier & JumpDword
5739 || current_templates->start->opcode_modifier & JumpByte
5740 || current_templates->start->opcode_modifier & JumpInterSegment)
5741 i.types[this_operand] |= JumpAbsolute;
5742
5743 /* Add a '+' to the displacement string if necessary. */
21d6c4af
DN		 5744 if (*intel_parser.disp != '\0'
5745 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
64a0c779
DN		 5746 strcat (intel_parser.disp, "+");
5747
21d6c4af
DN		 5748 if (intel_expr () && intel_match_token (']'))
5749 {
5750 /* Preserve brackets when the operand is an offset expression. */
5751 if (intel_parser.op_modifier == OFFSET_FLAT)
5752 strcat (intel_parser.disp, "]");
5753
5754 return 1;
5755 }
5756 else
5757 return 0;
64a0c779
DN		 5758 }
5759
4a1805b1 5760 /* e11 BYTE
64a0c779
DN		 5761 | WORD
5762 | DWORD
5763 | QWORD
5764 | XWORD */
5765 else if (cur_token.code == T_BYTE
5766 || cur_token.code == T_WORD
5767 || cur_token.code == T_DWORD
5768 || cur_token.code == T_QWORD
5769 || cur_token.code == T_XWORD)
5770 {
5771 intel_match_token (cur_token.code);
5772
5773 return 1;
5774 }
5775
5776 /* e11 $
5777 | . */
5778 else if (cur_token.code == '$' || cur_token.code == '.')
5779 {
5780 strcat (intel_parser.disp, cur_token.str);
5781 intel_match_token (cur_token.code);
21d6c4af
DN		 5782
5783 /* Mark as a memory operand only if it's not already known to be an
5784 offset expression. */
5785 if (intel_parser.op_modifier != OFFSET_FLAT)
5786 intel_parser.is_mem = 1;
64a0c779
DN		 5787
5788 return 1;
5789 }
5790
5791 /* e11 register */
5792 else if (cur_token.code == T_REG)
5793 {
5794 const reg_entry *reg = intel_parser.reg = cur_token.reg;
5795
5796 intel_match_token (T_REG);
5797
5798 /* Check for segment change. */
5799 if (cur_token.code == ':')
5800 {
5801 if (reg->reg_type & (SReg2 | SReg3))
5802 {
5803 switch (reg->reg_num)
5804 {
5805 case 0:
5806 i.seg[i.mem_operands] = &es;
5807 break;
5808 case 1:
5809 i.seg[i.mem_operands] = &cs;
5810 break;
5811 case 2:
5812 i.seg[i.mem_operands] = &ss;
5813 break;
5814 case 3:
5815 i.seg[i.mem_operands] = &ds;
5816 break;
5817 case 4:
5818 i.seg[i.mem_operands] = &fs;
5819 break;
5820 case 5:
5821 i.seg[i.mem_operands] = &gs;
5822 break;
5823 }
5824 }
5825 else
5826 {
5827 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
5828 return 0;
5829 }
5830 }
5831
5832 /* Not a segment register. Check for register scaling. */
5833 else if (cur_token.code == '*')
5834 {
5835 if (!intel_parser.is_mem)
5836 {
5837 as_bad (_("Register scaling only allowed in memory operands."));
5838 return 0;
5839 }
5840
4a1805b1 5841 /* What follows must be a valid scale. */
64a0c779
DN		 5842 if (intel_match_token ('*')
5843 && strchr ("01248", *cur_token.str))
5844 {
5845 i.index_reg = reg;
5846 i.types[this_operand] |= BaseIndex;
5847
5848 /* Set the scale after setting the register (otherwise,
5849 i386_scale will complain) */
5850 i386_scale (cur_token.str);
5851 intel_match_token (T_CONST);
5852 }
5853 else
5854 {
5855 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5856 cur_token.str);
5857 return 0;
5858 }
5859 }
5860
5861 /* No scaling. If this is a memory operand, the register is either a
5862 base register (first occurrence) or an index register (second
5863 occurrence). */
5864 else if (intel_parser.is_mem && !(reg->reg_type & (SReg2 | SReg3)))
5865 {
5866 if (i.base_reg && i.index_reg)
5867 {
5868 as_bad (_("Too many register references in memory operand.\n"));
5869 return 0;
5870 }
5871
5872 if (i.base_reg == NULL)
5873 i.base_reg = reg;
5874 else
5875 i.index_reg = reg;
5876
5877 i.types[this_operand] |= BaseIndex;
5878 }
5879
5880 /* Offset modifier. Add the register to the displacement string to be
5881 parsed as an immediate expression after we're done. */
5882 else if (intel_parser.op_modifier == OFFSET_FLAT)
5883 strcat (intel_parser.disp, reg->reg_name);
4a1805b1 5884
64a0c779
DN		 5885 /* It's neither base nor index nor offset. */
5886 else
5887 {
5888 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
5889 i.op[this_operand].regs = reg;
5890 i.reg_operands++;
5891 }
5892
5893 /* Since registers are not part of the displacement string (except
5894 when we're parsing offset operands), we may need to remove any
5895 preceding '+' from the displacement string. */
5896 if (*intel_parser.disp != '\0'
5897 && intel_parser.op_modifier != OFFSET_FLAT)
5898 {
5899 char *s = intel_parser.disp;
5900 s += strlen (s) - 1;
5901 if (*s == '+')
5902 *s = '\0';
5903 }
5904
5905 return 1;
5906 }
4a1805b1 5907
64a0c779
DN		 5908 /* e11 id */
5909 else if (cur_token.code == T_ID)
5910 {
5911 /* Add the identifier to the displacement string. */
5912 strcat (intel_parser.disp, cur_token.str);
5913 intel_match_token (T_ID);
5914
5915 /* The identifier represents a memory reference only if it's not
5916 preceded by an offset modifier. */
21d6c4af 5917 if (intel_parser.op_modifier != OFFSET_FLAT)
64a0c779
DN		 5918 intel_parser.is_mem = 1;
5919
5920 return 1;
5921 }
5922
5923 /* e11 constant */
5924 else if (cur_token.code == T_CONST
e5cb08ac 5925 || cur_token.code == '-'
64a0c779
DN		 5926 || cur_token.code == '+')
5927 {
5928 char *save_str;
5929
5930 /* Allow constants that start with `+' or `-'. */
5931 if (cur_token.code == '-' || cur_token.code == '+')
5932 {
5933 strcat (intel_parser.disp, cur_token.str);
5934 intel_match_token (cur_token.code);
5935 if (cur_token.code != T_CONST)
5936 {
5937 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
5938 cur_token.str);
5939 return 0;
5940 }
5941 }
5942
e5cb08ac 5943 save_str = (char *) malloc (strlen (cur_token.str) + 1);
64a0c779 5944 if (save_str == NULL)
bc805888 5945 abort ();
64a0c779
DN		 5946 strcpy (save_str, cur_token.str);
5947
5948 /* Get the next token to check for register scaling. */
5949 intel_match_token (cur_token.code);
5950
5951 /* Check if this constant is a scaling factor for an index register. */
5952 if (cur_token.code == '*')
5953 {
5954 if (intel_match_token ('*') && cur_token.code == T_REG)
5955 {
5956 if (!intel_parser.is_mem)
5957 {
5958 as_bad (_("Register scaling only allowed in memory operands."));
5959 return 0;
5960 }
5961
4a1805b1 5962 /* The constant is followed by `* reg', so it must be
64a0c779
DN		 5963 a valid scale. */
5964 if (strchr ("01248", *save_str))
5965 {
5966 i.index_reg = cur_token.reg;
5967 i.types[this_operand] |= BaseIndex;
5968
5969 /* Set the scale after setting the register (otherwise,
5970 i386_scale will complain) */
5971 i386_scale (save_str);
5972 intel_match_token (T_REG);
5973
5974 /* Since registers are not part of the displacement
5975 string, we may need to remove any preceding '+' from
5976 the displacement string. */
5977 if (*intel_parser.disp != '\0')
5978 {
5979 char *s = intel_parser.disp;
5980 s += strlen (s) - 1;
5981 if (*s == '+')
5982 *s = '\0';
5983 }
5984
5985 free (save_str);
5986
5987 return 1;
5988 }
5989 else
5990 return 0;
5991 }
5992
5993 /* The constant was not used for register scaling. Since we have
5994 already consumed the token following `*' we now need to put it
5995 back in the stream. */
5996 else
5997 intel_putback_token ();
5998 }
5999
6000 /* Add the constant to the displacement string. */
6001 strcat (intel_parser.disp, save_str);
6002 free (save_str);
6003
6004 return 1;
6005 }
6006
64a0c779
DN		 6007 as_bad (_("Unrecognized token '%s'"), cur_token.str);
6008 return 0;
6009}
6010
64a0c779
DN		 6011/* Match the given token against cur_token. If they match, read the next
6012 token from the operand string. */
6013static int
6014intel_match_token (code)
e5cb08ac 6015 int code;
64a0c779
DN		 6016{
6017 if (cur_token.code == code)
6018 {
6019 intel_get_token ();
6020 return 1;
6021 }
6022 else
6023 {
6024 as_bad (_("Unexpected token `%s'\n"), cur_token.str);
6025 return 0;
6026 }
6027}
6028
64a0c779
DN		 6029/* Read a new token from intel_parser.op_string and store it in cur_token. */
6030static void
6031intel_get_token ()
6032{
6033 char *end_op;
6034 const reg_entry *reg;
6035 struct intel_token new_token;
6036
6037 new_token.code = T_NIL;
6038 new_token.reg = NULL;
6039 new_token.str = NULL;
6040
4a1805b1 6041 /* Free the memory allocated to the previous token and move
64a0c779
DN		 6042 cur_token to prev_token. */
6043 if (prev_token.str)
6044 free (prev_token.str);
6045
6046 prev_token = cur_token;
6047
6048 /* Skip whitespace. */
6049 while (is_space_char (*intel_parser.op_string))
6050 intel_parser.op_string++;
6051
6052 /* Return an empty token if we find nothing else on the line. */
6053 if (*intel_parser.op_string == '\0')
6054 {
6055 cur_token = new_token;
6056 return;
6057 }
6058
6059 /* The new token cannot be larger than the remainder of the operand
6060 string. */
e5cb08ac 6061 new_token.str = (char *) malloc (strlen (intel_parser.op_string) + 1);
64a0c779 6062 if (new_token.str == NULL)
bc805888 6063 abort ();
64a0c779
DN		 6064 new_token.str[0] = '\0';
6065
6066 if (strchr ("0123456789", *intel_parser.op_string))
6067 {
6068 char *p = new_token.str;
6069 char *q = intel_parser.op_string;
6070 new_token.code = T_CONST;
6071
6072 /* Allow any kind of identifier char to encompass floating point and
6073 hexadecimal numbers. */
6074 while (is_identifier_char (*q))
6075 *p++ = *q++;
6076 *p = '\0';
6077
6078 /* Recognize special symbol names [0-9][bf]. */
6079 if (strlen (intel_parser.op_string) == 2
4a1805b1 6080 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 6081 || intel_parser.op_string[1] == 'f'))
6082 new_token.code = T_ID;
6083 }
6084
6085 else if (strchr ("+-/*:[]()", *intel_parser.op_string))
6086 {
6087 new_token.code = *intel_parser.op_string;
6088 new_token.str[0] = *intel_parser.op_string;
6089 new_token.str[1] = '\0';
6090 }
6091
6092 else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg)
6093 && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL))
6094 {
6095 new_token.code = T_REG;
6096 new_token.reg = reg;
6097
6098 if (*intel_parser.op_string == REGISTER_PREFIX)
6099 {
6100 new_token.str[0] = REGISTER_PREFIX;
6101 new_token.str[1] = '\0';
6102 }
6103
6104 strcat (new_token.str, reg->reg_name);
6105 }
6106
6107 else if (is_identifier_char (*intel_parser.op_string))
6108 {
6109 char *p = new_token.str;
6110 char *q = intel_parser.op_string;
6111
6112 /* A '.' or '$' followed by an identifier char is an identifier.
6113 Otherwise, it's operator '.' followed by an expression. */
6114 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
6115 {
6116 new_token.code = *q;
6117 new_token.str[0] = *q;
6118 new_token.str[1] = '\0';
6119 }
6120 else
6121 {
6122 while (is_identifier_char (*q) || *q == '@')
6123 *p++ = *q++;
6124 *p = '\0';
6125
6126 if (strcasecmp (new_token.str, "BYTE") == 0)
6127 new_token.code = T_BYTE;
6128
6129 else if (strcasecmp (new_token.str, "WORD") == 0)
6130 new_token.code = T_WORD;
6131
6132 else if (strcasecmp (new_token.str, "DWORD") == 0)
6133 new_token.code = T_DWORD;
6134
6135 else if (strcasecmp (new_token.str, "QWORD") == 0)
6136 new_token.code = T_QWORD;
6137
6138 else if (strcasecmp (new_token.str, "XWORD") == 0)
6139 new_token.code = T_XWORD;
6140
6141 else if (strcasecmp (new_token.str, "PTR") == 0)
6142 new_token.code = T_PTR;
6143
6144 else if (strcasecmp (new_token.str, "SHORT") == 0)
6145 new_token.code = T_SHORT;
6146
6147 else if (strcasecmp (new_token.str, "OFFSET") == 0)
6148 {
6149 new_token.code = T_OFFSET;
6150
6151 /* ??? This is not mentioned in the MASM grammar but gcc
6152 makes use of it with -mintel-syntax. OFFSET may be
6153 followed by FLAT: */
6154 if (strncasecmp (q, " FLAT:", 6) == 0)
6155 strcat (new_token.str, " FLAT:");
6156 }
6157
6158 /* ??? This is not mentioned in the MASM grammar. */
6159 else if (strcasecmp (new_token.str, "FLAT") == 0)
6160 new_token.code = T_OFFSET;
6161
6162 else
6163 new_token.code = T_ID;
6164 }
6165 }
6166
6167 else
6168 as_bad (_("Unrecognized token `%s'\n"), intel_parser.op_string);
6169
6170 intel_parser.op_string += strlen (new_token.str);
6171 cur_token = new_token;
6172}
6173
64a0c779
DN		 6174/* Put cur_token back into the token stream and make cur_token point to
6175 prev_token. */
6176static void
6177intel_putback_token ()
6178{
6179 intel_parser.op_string -= strlen (cur_token.str);
6180 free (cur_token.str);
6181 cur_token = prev_token;
4a1805b1 6182
64a0c779
DN		 6183 /* Forget prev_token. */
6184 prev_token.code = T_NIL;
6185 prev_token.reg = NULL;
6186 prev_token.str = NULL;
6187}
GDB Binutils - Deliverables
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