Commit | Line | Data |
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b534c6d3 | 1 | /* tc-i386.c -- Assemble code for the Intel 80386 |
f7e42eb4 | 2 | Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
5dd15031 | 3 | 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 |
47926f60 | 4 | Free Software Foundation, Inc. |
252b5132 RH |
5 | |
6 | This file is part of GAS, the GNU Assembler. | |
7 | ||
8 | GAS is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 10 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
11 | any later version. |
12 | ||
13 | GAS is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
20 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
21 | 02110-1301, USA. */ | |
252b5132 | 22 | |
47926f60 KH |
23 | /* Intel 80386 machine specific gas. |
24 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 25 | x86_64 support by Jan Hubicka (jh@suse.cz) |
0f10071e | 26 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
47926f60 KH |
27 | Bugs & suggestions are completely welcome. This is free software. |
28 | Please help us make it better. */ | |
252b5132 | 29 | |
252b5132 | 30 | #include "as.h" |
3882b010 | 31 | #include "safe-ctype.h" |
252b5132 | 32 | #include "subsegs.h" |
316e2c05 | 33 | #include "dwarf2dbg.h" |
54cfded0 | 34 | #include "dw2gencfi.h" |
d2b2c203 | 35 | #include "elf/x86-64.h" |
40fb9820 | 36 | #include "opcodes/i386-init.h" |
252b5132 | 37 | |
252b5132 RH |
38 | #ifndef REGISTER_WARNINGS |
39 | #define REGISTER_WARNINGS 1 | |
40 | #endif | |
41 | ||
c3332e24 | 42 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 43 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
44 | #endif |
45 | ||
29b0f896 AM |
46 | #ifndef DEFAULT_ARCH |
47 | #define DEFAULT_ARCH "i386" | |
246fcdee | 48 | #endif |
252b5132 | 49 | |
edde18a5 AM |
50 | #ifndef INLINE |
51 | #if __GNUC__ >= 2 | |
52 | #define INLINE __inline__ | |
53 | #else | |
54 | #define INLINE | |
55 | #endif | |
56 | #endif | |
57 | ||
6305a203 L |
58 | /* Prefixes will be emitted in the order defined below. |
59 | WAIT_PREFIX must be the first prefix since FWAIT is really is an | |
60 | instruction, and so must come before any prefixes. | |
61 | The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, | |
62 | LOCKREP_PREFIX. */ | |
63 | #define WAIT_PREFIX 0 | |
64 | #define SEG_PREFIX 1 | |
65 | #define ADDR_PREFIX 2 | |
66 | #define DATA_PREFIX 3 | |
67 | #define LOCKREP_PREFIX 4 | |
68 | #define REX_PREFIX 5 /* must come last. */ | |
69 | #define MAX_PREFIXES 6 /* max prefixes per opcode */ | |
70 | ||
71 | /* we define the syntax here (modulo base,index,scale syntax) */ | |
72 | #define REGISTER_PREFIX '%' | |
73 | #define IMMEDIATE_PREFIX '$' | |
74 | #define ABSOLUTE_PREFIX '*' | |
75 | ||
76 | /* these are the instruction mnemonic suffixes in AT&T syntax or | |
77 | memory operand size in Intel syntax. */ | |
78 | #define WORD_MNEM_SUFFIX 'w' | |
79 | #define BYTE_MNEM_SUFFIX 'b' | |
80 | #define SHORT_MNEM_SUFFIX 's' | |
81 | #define LONG_MNEM_SUFFIX 'l' | |
82 | #define QWORD_MNEM_SUFFIX 'q' | |
83 | #define XMMWORD_MNEM_SUFFIX 'x' | |
c0f3af97 | 84 | #define YMMWORD_MNEM_SUFFIX 'y' |
6305a203 L |
85 | /* Intel Syntax. Use a non-ascii letter since since it never appears |
86 | in instructions. */ | |
87 | #define LONG_DOUBLE_MNEM_SUFFIX '\1' | |
88 | ||
89 | #define END_OF_INSN '\0' | |
90 | ||
91 | /* | |
92 | 'templates' is for grouping together 'template' structures for opcodes | |
93 | of the same name. This is only used for storing the insns in the grand | |
94 | ole hash table of insns. | |
95 | The templates themselves start at START and range up to (but not including) | |
96 | END. | |
97 | */ | |
98 | typedef struct | |
99 | { | |
100 | const template *start; | |
101 | const template *end; | |
102 | } | |
103 | templates; | |
104 | ||
105 | /* 386 operand encoding bytes: see 386 book for details of this. */ | |
106 | typedef struct | |
107 | { | |
108 | unsigned int regmem; /* codes register or memory operand */ | |
109 | unsigned int reg; /* codes register operand (or extended opcode) */ | |
110 | unsigned int mode; /* how to interpret regmem & reg */ | |
111 | } | |
112 | modrm_byte; | |
113 | ||
114 | /* x86-64 extension prefix. */ | |
115 | typedef int rex_byte; | |
116 | ||
117 | /* The SSE5 instructions have a two bit instruction modifier (OC) that | |
118 | is stored in two separate bytes in the instruction. Pick apart OC | |
119 | into the 2 separate bits for instruction. */ | |
120 | #define DREX_OC0(x) (((x) & 1) != 0) | |
121 | #define DREX_OC1(x) (((x) & 2) != 0) | |
122 | ||
123 | #define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */ | |
124 | #define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */ | |
125 | ||
126 | /* OC mappings */ | |
127 | #define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */ | |
128 | #define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */ | |
129 | #define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */ | |
130 | #define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */ | |
131 | ||
132 | #define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */ | |
133 | #define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */ | |
134 | ||
135 | /* Information needed to create the DREX byte in SSE5 instructions. */ | |
136 | typedef struct | |
137 | { | |
138 | unsigned int reg; /* register */ | |
139 | unsigned int rex; /* REX flags */ | |
140 | unsigned int modrm_reg; /* which arg goes in the modrm.reg field */ | |
141 | unsigned int modrm_regmem; /* which arg goes in the modrm.regmem field */ | |
142 | } drex_byte; | |
143 | ||
144 | /* 386 opcode byte to code indirect addressing. */ | |
145 | typedef struct | |
146 | { | |
147 | unsigned base; | |
148 | unsigned index; | |
149 | unsigned scale; | |
150 | } | |
151 | sib_byte; | |
152 | ||
153 | enum processor_type | |
154 | { | |
155 | PROCESSOR_UNKNOWN, | |
156 | PROCESSOR_I386, | |
157 | PROCESSOR_I486, | |
158 | PROCESSOR_PENTIUM, | |
159 | PROCESSOR_PENTIUMPRO, | |
160 | PROCESSOR_PENTIUM4, | |
161 | PROCESSOR_NOCONA, | |
162 | PROCESSOR_CORE, | |
163 | PROCESSOR_CORE2, | |
164 | PROCESSOR_K6, | |
165 | PROCESSOR_ATHLON, | |
166 | PROCESSOR_K8, | |
167 | PROCESSOR_GENERIC32, | |
168 | PROCESSOR_GENERIC64, | |
169 | PROCESSOR_AMDFAM10 | |
170 | }; | |
171 | ||
172 | /* x86 arch names, types and features */ | |
173 | typedef struct | |
174 | { | |
175 | const char *name; /* arch name */ | |
176 | enum processor_type type; /* arch type */ | |
177 | i386_cpu_flags flags; /* cpu feature flags */ | |
178 | } | |
179 | arch_entry; | |
180 | ||
e3bb37b5 L |
181 | static void set_code_flag (int); |
182 | static void set_16bit_gcc_code_flag (int); | |
183 | static void set_intel_syntax (int); | |
1efbbeb4 | 184 | static void set_intel_mnemonic (int); |
db51cc60 | 185 | static void set_allow_index_reg (int); |
cb19c032 | 186 | static void set_sse_check (int); |
e3bb37b5 | 187 | static void set_cpu_arch (int); |
6482c264 | 188 | #ifdef TE_PE |
e3bb37b5 | 189 | static void pe_directive_secrel (int); |
6482c264 | 190 | #endif |
e3bb37b5 L |
191 | static void signed_cons (int); |
192 | static char *output_invalid (int c); | |
a7619375 | 193 | static int i386_att_operand (char *); |
e3bb37b5 L |
194 | static int i386_intel_operand (char *, int); |
195 | static const reg_entry *parse_register (char *, char **); | |
196 | static char *parse_insn (char *, char *); | |
197 | static char *parse_operands (char *, const char *); | |
198 | static void swap_operands (void); | |
4d456e3d | 199 | static void swap_2_operands (int, int); |
e3bb37b5 L |
200 | static void optimize_imm (void); |
201 | static void optimize_disp (void); | |
202 | static int match_template (void); | |
203 | static int check_string (void); | |
204 | static int process_suffix (void); | |
205 | static int check_byte_reg (void); | |
206 | static int check_long_reg (void); | |
207 | static int check_qword_reg (void); | |
208 | static int check_word_reg (void); | |
209 | static int finalize_imm (void); | |
85f10a01 | 210 | static void process_drex (void); |
e3bb37b5 L |
211 | static int process_operands (void); |
212 | static const seg_entry *build_modrm_byte (void); | |
213 | static void output_insn (void); | |
214 | static void output_imm (fragS *, offsetT); | |
215 | static void output_disp (fragS *, offsetT); | |
29b0f896 | 216 | #ifndef I386COFF |
e3bb37b5 | 217 | static void s_bss (int); |
252b5132 | 218 | #endif |
17d4e2a2 L |
219 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
220 | static void handle_large_common (int small ATTRIBUTE_UNUSED); | |
221 | #endif | |
252b5132 | 222 | |
a847613f | 223 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 224 | |
c0f3af97 L |
225 | /* VEX prefix. */ |
226 | typedef struct | |
227 | { | |
228 | /* VEX prefix is either 2 byte or 3 byte. */ | |
229 | unsigned char bytes[3]; | |
230 | unsigned int length; | |
231 | /* Destination or source register specifier. */ | |
232 | const reg_entry *register_specifier; | |
233 | } vex_prefix; | |
234 | ||
252b5132 | 235 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 236 | i386_insn. */ |
252b5132 | 237 | |
520dc8e8 AM |
238 | union i386_op |
239 | { | |
240 | expressionS *disps; | |
241 | expressionS *imms; | |
242 | const reg_entry *regs; | |
243 | }; | |
244 | ||
252b5132 RH |
245 | struct _i386_insn |
246 | { | |
47926f60 | 247 | /* TM holds the template for the insn were currently assembling. */ |
252b5132 RH |
248 | template tm; |
249 | ||
7d5e4556 L |
250 | /* SUFFIX holds the instruction size suffix for byte, word, dword |
251 | or qword, if given. */ | |
252b5132 RH |
252 | char suffix; |
253 | ||
47926f60 | 254 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
255 | unsigned int operands; |
256 | ||
257 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
258 | of given register, displacement, memory operands and immediate | |
47926f60 | 259 | operands. */ |
252b5132 RH |
260 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
261 | ||
262 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 263 | use OP[i] for the corresponding operand. */ |
40fb9820 | 264 | i386_operand_type types[MAX_OPERANDS]; |
252b5132 | 265 | |
520dc8e8 AM |
266 | /* Displacement expression, immediate expression, or register for each |
267 | operand. */ | |
268 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 269 | |
3e73aa7c JH |
270 | /* Flags for operands. */ |
271 | unsigned int flags[MAX_OPERANDS]; | |
272 | #define Operand_PCrel 1 | |
273 | ||
252b5132 | 274 | /* Relocation type for operand */ |
f86103b7 | 275 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
252b5132 | 276 | |
252b5132 RH |
277 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
278 | the base index byte below. */ | |
279 | const reg_entry *base_reg; | |
280 | const reg_entry *index_reg; | |
281 | unsigned int log2_scale_factor; | |
282 | ||
283 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 284 | explicit segment overrides are given. */ |
ce8a8b2f | 285 | const seg_entry *seg[2]; |
252b5132 RH |
286 | |
287 | /* PREFIX holds all the given prefix opcodes (usually null). | |
288 | PREFIXES is the number of prefix opcodes. */ | |
289 | unsigned int prefixes; | |
290 | unsigned char prefix[MAX_PREFIXES]; | |
291 | ||
292 | /* RM and SIB are the modrm byte and the sib byte where the | |
85f10a01 MM |
293 | addressing modes of this insn are encoded. DREX is the byte |
294 | added by the SSE5 instructions. */ | |
252b5132 RH |
295 | |
296 | modrm_byte rm; | |
3e73aa7c | 297 | rex_byte rex; |
252b5132 | 298 | sib_byte sib; |
85f10a01 | 299 | drex_byte drex; |
c0f3af97 | 300 | vex_prefix vex; |
252b5132 RH |
301 | }; |
302 | ||
303 | typedef struct _i386_insn i386_insn; | |
304 | ||
305 | /* List of chars besides those in app.c:symbol_chars that can start an | |
306 | operand. Used to prevent the scrubber eating vital white-space. */ | |
32137342 | 307 | const char extra_symbol_chars[] = "*%-([" |
252b5132 | 308 | #ifdef LEX_AT |
32137342 NC |
309 | "@" |
310 | #endif | |
311 | #ifdef LEX_QM | |
312 | "?" | |
252b5132 | 313 | #endif |
32137342 | 314 | ; |
252b5132 | 315 | |
29b0f896 AM |
316 | #if (defined (TE_I386AIX) \ |
317 | || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ | |
3896cfd5 | 318 | && !defined (TE_GNU) \ |
29b0f896 | 319 | && !defined (TE_LINUX) \ |
32137342 | 320 | && !defined (TE_NETWARE) \ |
29b0f896 AM |
321 | && !defined (TE_FreeBSD) \ |
322 | && !defined (TE_NetBSD))) | |
252b5132 | 323 | /* This array holds the chars that always start a comment. If the |
b3b91714 AM |
324 | pre-processor is disabled, these aren't very useful. The option |
325 | --divide will remove '/' from this list. */ | |
326 | const char *i386_comment_chars = "#/"; | |
327 | #define SVR4_COMMENT_CHARS 1 | |
252b5132 | 328 | #define PREFIX_SEPARATOR '\\' |
252b5132 | 329 | |
b3b91714 AM |
330 | #else |
331 | const char *i386_comment_chars = "#"; | |
332 | #define PREFIX_SEPARATOR '/' | |
333 | #endif | |
334 | ||
252b5132 RH |
335 | /* This array holds the chars that only start a comment at the beginning of |
336 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
337 | .line and .file directives will appear in the pre-processed output. |
338 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 339 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
340 | #NO_APP at the beginning of its output. |
341 | Also note that comments started like this one will always work if | |
252b5132 | 342 | '/' isn't otherwise defined. */ |
b3b91714 | 343 | const char line_comment_chars[] = "#/"; |
252b5132 | 344 | |
63a0b638 | 345 | const char line_separator_chars[] = ";"; |
252b5132 | 346 | |
ce8a8b2f AM |
347 | /* Chars that can be used to separate mant from exp in floating point |
348 | nums. */ | |
252b5132 RH |
349 | const char EXP_CHARS[] = "eE"; |
350 | ||
ce8a8b2f AM |
351 | /* Chars that mean this number is a floating point constant |
352 | As in 0f12.456 | |
353 | or 0d1.2345e12. */ | |
252b5132 RH |
354 | const char FLT_CHARS[] = "fFdDxX"; |
355 | ||
ce8a8b2f | 356 | /* Tables for lexical analysis. */ |
252b5132 RH |
357 | static char mnemonic_chars[256]; |
358 | static char register_chars[256]; | |
359 | static char operand_chars[256]; | |
360 | static char identifier_chars[256]; | |
361 | static char digit_chars[256]; | |
362 | ||
ce8a8b2f | 363 | /* Lexical macros. */ |
252b5132 RH |
364 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
365 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
366 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
367 | #define is_space_char(x) ((x) == ' ') | |
368 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
369 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
370 | ||
0234cb7c | 371 | /* All non-digit non-letter characters that may occur in an operand. */ |
252b5132 RH |
372 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
373 | ||
374 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
375 | effect this we maintain a stack of saved characters that we've smashed | |
376 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 377 | assembler instruction). */ |
252b5132 | 378 | static char save_stack[32]; |
ce8a8b2f | 379 | static char *save_stack_p; |
252b5132 RH |
380 | #define END_STRING_AND_SAVE(s) \ |
381 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
382 | #define RESTORE_END_STRING(s) \ | |
383 | do { *(s) = *--save_stack_p; } while (0) | |
384 | ||
47926f60 | 385 | /* The instruction we're assembling. */ |
252b5132 RH |
386 | static i386_insn i; |
387 | ||
388 | /* Possible templates for current insn. */ | |
389 | static const templates *current_templates; | |
390 | ||
31b2323c L |
391 | /* Per instruction expressionS buffers: max displacements & immediates. */ |
392 | static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; | |
393 | static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; | |
252b5132 | 394 | |
47926f60 KH |
395 | /* Current operand we are working on. */ |
396 | static int this_operand; | |
252b5132 | 397 | |
3e73aa7c JH |
398 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
399 | these. */ | |
400 | ||
401 | enum flag_code { | |
402 | CODE_32BIT, | |
403 | CODE_16BIT, | |
404 | CODE_64BIT }; | |
405 | ||
406 | static enum flag_code flag_code; | |
4fa24527 | 407 | static unsigned int object_64bit; |
3e73aa7c JH |
408 | static int use_rela_relocations = 0; |
409 | ||
410 | /* The names used to print error messages. */ | |
b77a7acd | 411 | static const char *flag_code_names[] = |
3e73aa7c JH |
412 | { |
413 | "32", | |
414 | "16", | |
415 | "64" | |
416 | }; | |
252b5132 | 417 | |
47926f60 KH |
418 | /* 1 for intel syntax, |
419 | 0 if att syntax. */ | |
420 | static int intel_syntax = 0; | |
252b5132 | 421 | |
1efbbeb4 L |
422 | /* 1 for intel mnemonic, |
423 | 0 if att mnemonic. */ | |
424 | static int intel_mnemonic = !SYSV386_COMPAT; | |
425 | ||
5209009a | 426 | /* 1 if support old (<= 2.8.1) versions of gcc. */ |
1efbbeb4 L |
427 | static int old_gcc = OLDGCC_COMPAT; |
428 | ||
a60de03c JB |
429 | /* 1 if pseudo registers are permitted. */ |
430 | static int allow_pseudo_reg = 0; | |
431 | ||
47926f60 KH |
432 | /* 1 if register prefix % not required. */ |
433 | static int allow_naked_reg = 0; | |
252b5132 | 434 | |
ba104c83 | 435 | /* 1 if pseudo index register, eiz/riz, is allowed . */ |
db51cc60 L |
436 | static int allow_index_reg = 0; |
437 | ||
daf50ae7 L |
438 | static enum |
439 | { | |
440 | sse_check_none = 0, | |
441 | sse_check_warning, | |
442 | sse_check_error | |
443 | } | |
444 | sse_check; | |
445 | ||
2ca3ace5 L |
446 | /* Register prefix used for error message. */ |
447 | static const char *register_prefix = "%"; | |
448 | ||
47926f60 KH |
449 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
450 | leave, push, and pop instructions so that gcc has the same stack | |
451 | frame as in 32 bit mode. */ | |
452 | static char stackop_size = '\0'; | |
eecb386c | 453 | |
12b55ccc L |
454 | /* Non-zero to optimize code alignment. */ |
455 | int optimize_align_code = 1; | |
456 | ||
47926f60 KH |
457 | /* Non-zero to quieten some warnings. */ |
458 | static int quiet_warnings = 0; | |
a38cf1db | 459 | |
47926f60 KH |
460 | /* CPU name. */ |
461 | static const char *cpu_arch_name = NULL; | |
6305a203 | 462 | static char *cpu_sub_arch_name = NULL; |
a38cf1db | 463 | |
47926f60 | 464 | /* CPU feature flags. */ |
40fb9820 L |
465 | static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; |
466 | ||
ccc9c027 L |
467 | /* If we have selected a cpu we are generating instructions for. */ |
468 | static int cpu_arch_tune_set = 0; | |
469 | ||
9103f4f4 L |
470 | /* Cpu we are generating instructions for. */ |
471 | static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; | |
472 | ||
473 | /* CPU feature flags of cpu we are generating instructions for. */ | |
40fb9820 | 474 | static i386_cpu_flags cpu_arch_tune_flags; |
9103f4f4 | 475 | |
ccc9c027 L |
476 | /* CPU instruction set architecture used. */ |
477 | static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; | |
478 | ||
9103f4f4 | 479 | /* CPU feature flags of instruction set architecture used. */ |
40fb9820 | 480 | static i386_cpu_flags cpu_arch_isa_flags; |
9103f4f4 | 481 | |
fddf5b5b AM |
482 | /* If set, conditional jumps are not automatically promoted to handle |
483 | larger than a byte offset. */ | |
484 | static unsigned int no_cond_jump_promotion = 0; | |
485 | ||
c0f3af97 L |
486 | /* Encode SSE instructions with VEX prefix. */ |
487 | static unsigned int sse2avx; | |
488 | ||
29b0f896 | 489 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
87c245cc | 490 | static symbolS *GOT_symbol; |
29b0f896 | 491 | |
a4447b93 RH |
492 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
493 | unsigned int x86_dwarf2_return_column; | |
494 | ||
495 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
496 | int x86_cie_data_alignment; | |
497 | ||
252b5132 | 498 | /* Interface to relax_segment. |
fddf5b5b AM |
499 | There are 3 major relax states for 386 jump insns because the |
500 | different types of jumps add different sizes to frags when we're | |
501 | figuring out what sort of jump to choose to reach a given label. */ | |
252b5132 | 502 | |
47926f60 | 503 | /* Types. */ |
93c2a809 AM |
504 | #define UNCOND_JUMP 0 |
505 | #define COND_JUMP 1 | |
506 | #define COND_JUMP86 2 | |
fddf5b5b | 507 | |
47926f60 | 508 | /* Sizes. */ |
252b5132 RH |
509 | #define CODE16 1 |
510 | #define SMALL 0 | |
29b0f896 | 511 | #define SMALL16 (SMALL | CODE16) |
252b5132 | 512 | #define BIG 2 |
29b0f896 | 513 | #define BIG16 (BIG | CODE16) |
252b5132 RH |
514 | |
515 | #ifndef INLINE | |
516 | #ifdef __GNUC__ | |
517 | #define INLINE __inline__ | |
518 | #else | |
519 | #define INLINE | |
520 | #endif | |
521 | #endif | |
522 | ||
fddf5b5b AM |
523 | #define ENCODE_RELAX_STATE(type, size) \ |
524 | ((relax_substateT) (((type) << 2) | (size))) | |
525 | #define TYPE_FROM_RELAX_STATE(s) \ | |
526 | ((s) >> 2) | |
527 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
528 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
529 | |
530 | /* This table is used by relax_frag to promote short jumps to long | |
531 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
532 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
533 | don't allow a short jump in a 32 bit code segment to be promoted to | |
534 | a 16 bit offset jump because it's slower (requires data size | |
535 | prefix), and doesn't work, unless the destination is in the bottom | |
536 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
537 | ||
538 | const relax_typeS md_relax_table[] = | |
539 | { | |
24eab124 AM |
540 | /* The fields are: |
541 | 1) most positive reach of this state, | |
542 | 2) most negative reach of this state, | |
93c2a809 | 543 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 544 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 545 | |
fddf5b5b | 546 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
547 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
548 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
549 | /* dword jmp adds 4 bytes to frag: | |
550 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 551 | {0, 0, 4, 0}, |
93c2a809 AM |
552 | /* word jmp adds 2 byte2 to frag: |
553 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
554 | {0, 0, 2, 0}, |
555 | ||
93c2a809 AM |
556 | /* COND_JUMP states. */ |
557 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
558 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
559 | /* dword conditionals adds 5 bytes to frag: | |
560 | 1 extra opcode byte, 4 displacement bytes. */ | |
561 | {0, 0, 5, 0}, | |
fddf5b5b | 562 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
563 | 1 extra opcode byte, 2 displacement bytes. */ |
564 | {0, 0, 3, 0}, | |
565 | ||
566 | /* COND_JUMP86 states. */ | |
567 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
568 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
569 | /* dword conditionals adds 5 bytes to frag: | |
570 | 1 extra opcode byte, 4 displacement bytes. */ | |
571 | {0, 0, 5, 0}, | |
572 | /* word conditionals add 4 bytes to frag: | |
573 | 1 displacement byte and a 3 byte long branch insn. */ | |
574 | {0, 0, 4, 0} | |
252b5132 RH |
575 | }; |
576 | ||
9103f4f4 L |
577 | static const arch_entry cpu_arch[] = |
578 | { | |
6305a203 L |
579 | { "generic32", PROCESSOR_GENERIC32, |
580 | CPU_GENERIC32_FLAGS }, | |
581 | { "generic64", PROCESSOR_GENERIC64, | |
582 | CPU_GENERIC64_FLAGS }, | |
583 | { "i8086", PROCESSOR_UNKNOWN, | |
584 | CPU_NONE_FLAGS }, | |
585 | { "i186", PROCESSOR_UNKNOWN, | |
586 | CPU_I186_FLAGS }, | |
587 | { "i286", PROCESSOR_UNKNOWN, | |
588 | CPU_I286_FLAGS }, | |
589 | { "i386", PROCESSOR_I386, | |
590 | CPU_I386_FLAGS }, | |
591 | { "i486", PROCESSOR_I486, | |
592 | CPU_I486_FLAGS }, | |
593 | { "i586", PROCESSOR_PENTIUM, | |
594 | CPU_I586_FLAGS }, | |
595 | { "i686", PROCESSOR_PENTIUMPRO, | |
596 | CPU_I686_FLAGS }, | |
597 | { "pentium", PROCESSOR_PENTIUM, | |
598 | CPU_I586_FLAGS }, | |
599 | { "pentiumpro", PROCESSOR_PENTIUMPRO, | |
600 | CPU_I686_FLAGS }, | |
601 | { "pentiumii", PROCESSOR_PENTIUMPRO, | |
602 | CPU_P2_FLAGS }, | |
603 | { "pentiumiii",PROCESSOR_PENTIUMPRO, | |
604 | CPU_P3_FLAGS }, | |
605 | { "pentium4", PROCESSOR_PENTIUM4, | |
606 | CPU_P4_FLAGS }, | |
607 | { "prescott", PROCESSOR_NOCONA, | |
608 | CPU_CORE_FLAGS }, | |
609 | { "nocona", PROCESSOR_NOCONA, | |
610 | CPU_NOCONA_FLAGS }, | |
611 | { "yonah", PROCESSOR_CORE, | |
612 | CPU_CORE_FLAGS }, | |
613 | { "core", PROCESSOR_CORE, | |
614 | CPU_CORE_FLAGS }, | |
615 | { "merom", PROCESSOR_CORE2, | |
616 | CPU_CORE2_FLAGS }, | |
617 | { "core2", PROCESSOR_CORE2, | |
618 | CPU_CORE2_FLAGS }, | |
619 | { "k6", PROCESSOR_K6, | |
620 | CPU_K6_FLAGS }, | |
621 | { "k6_2", PROCESSOR_K6, | |
622 | CPU_K6_2_FLAGS }, | |
623 | { "athlon", PROCESSOR_ATHLON, | |
624 | CPU_ATHLON_FLAGS }, | |
625 | { "sledgehammer", PROCESSOR_K8, | |
626 | CPU_K8_FLAGS }, | |
627 | { "opteron", PROCESSOR_K8, | |
628 | CPU_K8_FLAGS }, | |
629 | { "k8", PROCESSOR_K8, | |
630 | CPU_K8_FLAGS }, | |
631 | { "amdfam10", PROCESSOR_AMDFAM10, | |
632 | CPU_AMDFAM10_FLAGS }, | |
633 | { ".mmx", PROCESSOR_UNKNOWN, | |
634 | CPU_MMX_FLAGS }, | |
635 | { ".sse", PROCESSOR_UNKNOWN, | |
636 | CPU_SSE_FLAGS }, | |
637 | { ".sse2", PROCESSOR_UNKNOWN, | |
638 | CPU_SSE2_FLAGS }, | |
639 | { ".sse3", PROCESSOR_UNKNOWN, | |
640 | CPU_SSE3_FLAGS }, | |
641 | { ".ssse3", PROCESSOR_UNKNOWN, | |
642 | CPU_SSSE3_FLAGS }, | |
643 | { ".sse4.1", PROCESSOR_UNKNOWN, | |
644 | CPU_SSE4_1_FLAGS }, | |
645 | { ".sse4.2", PROCESSOR_UNKNOWN, | |
646 | CPU_SSE4_2_FLAGS }, | |
647 | { ".sse4", PROCESSOR_UNKNOWN, | |
648 | CPU_SSE4_2_FLAGS }, | |
c0f3af97 L |
649 | { ".avx", PROCESSOR_UNKNOWN, |
650 | CPU_AVX_FLAGS }, | |
6305a203 L |
651 | { ".vmx", PROCESSOR_UNKNOWN, |
652 | CPU_VMX_FLAGS }, | |
653 | { ".smx", PROCESSOR_UNKNOWN, | |
654 | CPU_SMX_FLAGS }, | |
f03fe4c1 L |
655 | { ".xsave", PROCESSOR_UNKNOWN, |
656 | CPU_XSAVE_FLAGS }, | |
c0f3af97 L |
657 | { ".aes", PROCESSOR_UNKNOWN, |
658 | CPU_AES_FLAGS }, | |
594ab6a3 L |
659 | { ".pclmul", PROCESSOR_UNKNOWN, |
660 | CPU_PCLMUL_FLAGS }, | |
c0f3af97 | 661 | { ".clmul", PROCESSOR_UNKNOWN, |
594ab6a3 | 662 | CPU_PCLMUL_FLAGS }, |
c0f3af97 L |
663 | { ".fma", PROCESSOR_UNKNOWN, |
664 | CPU_FMA_FLAGS }, | |
f1f8f695 L |
665 | { ".movbe", PROCESSOR_UNKNOWN, |
666 | CPU_MOVBE_FLAGS }, | |
667 | { ".ept", PROCESSOR_UNKNOWN, | |
668 | CPU_EPT_FLAGS }, | |
6305a203 L |
669 | { ".3dnow", PROCESSOR_UNKNOWN, |
670 | CPU_3DNOW_FLAGS }, | |
671 | { ".3dnowa", PROCESSOR_UNKNOWN, | |
672 | CPU_3DNOWA_FLAGS }, | |
673 | { ".padlock", PROCESSOR_UNKNOWN, | |
674 | CPU_PADLOCK_FLAGS }, | |
675 | { ".pacifica", PROCESSOR_UNKNOWN, | |
676 | CPU_SVME_FLAGS }, | |
677 | { ".svme", PROCESSOR_UNKNOWN, | |
678 | CPU_SVME_FLAGS }, | |
679 | { ".sse4a", PROCESSOR_UNKNOWN, | |
680 | CPU_SSE4A_FLAGS }, | |
681 | { ".abm", PROCESSOR_UNKNOWN, | |
682 | CPU_ABM_FLAGS }, | |
683 | { ".sse5", PROCESSOR_UNKNOWN, | |
684 | CPU_SSE5_FLAGS }, | |
e413e4e9 AM |
685 | }; |
686 | ||
29b0f896 AM |
687 | const pseudo_typeS md_pseudo_table[] = |
688 | { | |
689 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) | |
690 | {"align", s_align_bytes, 0}, | |
691 | #else | |
692 | {"align", s_align_ptwo, 0}, | |
693 | #endif | |
694 | {"arch", set_cpu_arch, 0}, | |
695 | #ifndef I386COFF | |
696 | {"bss", s_bss, 0}, | |
697 | #endif | |
698 | {"ffloat", float_cons, 'f'}, | |
699 | {"dfloat", float_cons, 'd'}, | |
700 | {"tfloat", float_cons, 'x'}, | |
701 | {"value", cons, 2}, | |
d182319b | 702 | {"slong", signed_cons, 4}, |
29b0f896 AM |
703 | {"noopt", s_ignore, 0}, |
704 | {"optim", s_ignore, 0}, | |
705 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, | |
706 | {"code16", set_code_flag, CODE_16BIT}, | |
707 | {"code32", set_code_flag, CODE_32BIT}, | |
708 | {"code64", set_code_flag, CODE_64BIT}, | |
709 | {"intel_syntax", set_intel_syntax, 1}, | |
710 | {"att_syntax", set_intel_syntax, 0}, | |
1efbbeb4 L |
711 | {"intel_mnemonic", set_intel_mnemonic, 1}, |
712 | {"att_mnemonic", set_intel_mnemonic, 0}, | |
db51cc60 L |
713 | {"allow_index_reg", set_allow_index_reg, 1}, |
714 | {"disallow_index_reg", set_allow_index_reg, 0}, | |
cb19c032 | 715 | {"sse_check", set_sse_check, 0}, |
3b22753a L |
716 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
717 | {"largecomm", handle_large_common, 0}, | |
07a53e5c | 718 | #else |
e3bb37b5 | 719 | {"file", (void (*) (int)) dwarf2_directive_file, 0}, |
07a53e5c RH |
720 | {"loc", dwarf2_directive_loc, 0}, |
721 | {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, | |
3b22753a | 722 | #endif |
6482c264 NC |
723 | #ifdef TE_PE |
724 | {"secrel32", pe_directive_secrel, 0}, | |
725 | #endif | |
29b0f896 AM |
726 | {0, 0, 0} |
727 | }; | |
728 | ||
729 | /* For interface with expression (). */ | |
730 | extern char *input_line_pointer; | |
731 | ||
732 | /* Hash table for instruction mnemonic lookup. */ | |
733 | static struct hash_control *op_hash; | |
734 | ||
735 | /* Hash table for register lookup. */ | |
736 | static struct hash_control *reg_hash; | |
737 | \f | |
252b5132 | 738 | void |
e3bb37b5 | 739 | i386_align_code (fragS *fragP, int count) |
252b5132 | 740 | { |
ce8a8b2f AM |
741 | /* Various efficient no-op patterns for aligning code labels. |
742 | Note: Don't try to assemble the instructions in the comments. | |
743 | 0L and 0w are not legal. */ | |
252b5132 RH |
744 | static const char f32_1[] = |
745 | {0x90}; /* nop */ | |
746 | static const char f32_2[] = | |
ccc9c027 | 747 | {0x66,0x90}; /* xchg %ax,%ax */ |
252b5132 RH |
748 | static const char f32_3[] = |
749 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
750 | static const char f32_4[] = | |
751 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
752 | static const char f32_5[] = | |
753 | {0x90, /* nop */ | |
754 | 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
755 | static const char f32_6[] = | |
756 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
757 | static const char f32_7[] = | |
758 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
759 | static const char f32_8[] = | |
760 | {0x90, /* nop */ | |
761 | 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
762 | static const char f32_9[] = | |
763 | {0x89,0xf6, /* movl %esi,%esi */ | |
764 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
765 | static const char f32_10[] = | |
766 | {0x8d,0x76,0x00, /* leal 0(%esi),%esi */ | |
767 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
768 | static const char f32_11[] = | |
769 | {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */ | |
770 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
771 | static const char f32_12[] = | |
772 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
773 | 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */ | |
774 | static const char f32_13[] = | |
775 | {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */ | |
776 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
777 | static const char f32_14[] = | |
778 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */ | |
779 | 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */ | |
c3332e24 AM |
780 | static const char f16_3[] = |
781 | {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */ | |
252b5132 RH |
782 | static const char f16_4[] = |
783 | {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
784 | static const char f16_5[] = | |
785 | {0x90, /* nop */ | |
786 | 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ | |
787 | static const char f16_6[] = | |
788 | {0x89,0xf6, /* mov %si,%si */ | |
789 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
790 | static const char f16_7[] = | |
791 | {0x8d,0x74,0x00, /* lea 0(%si),%si */ | |
792 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
793 | static const char f16_8[] = | |
794 | {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ | |
795 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ | |
76bc74dc L |
796 | static const char jump_31[] = |
797 | {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */ | |
798 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90, | |
799 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90, | |
800 | 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90}; | |
252b5132 RH |
801 | static const char *const f32_patt[] = { |
802 | f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8, | |
76bc74dc | 803 | f32_9, f32_10, f32_11, f32_12, f32_13, f32_14 |
252b5132 RH |
804 | }; |
805 | static const char *const f16_patt[] = { | |
76bc74dc | 806 | f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8 |
252b5132 | 807 | }; |
ccc9c027 L |
808 | /* nopl (%[re]ax) */ |
809 | static const char alt_3[] = | |
810 | {0x0f,0x1f,0x00}; | |
811 | /* nopl 0(%[re]ax) */ | |
812 | static const char alt_4[] = | |
813 | {0x0f,0x1f,0x40,0x00}; | |
814 | /* nopl 0(%[re]ax,%[re]ax,1) */ | |
815 | static const char alt_5[] = | |
816 | {0x0f,0x1f,0x44,0x00,0x00}; | |
817 | /* nopw 0(%[re]ax,%[re]ax,1) */ | |
818 | static const char alt_6[] = | |
819 | {0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
820 | /* nopl 0L(%[re]ax) */ | |
821 | static const char alt_7[] = | |
822 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
823 | /* nopl 0L(%[re]ax,%[re]ax,1) */ | |
824 | static const char alt_8[] = | |
825 | {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
826 | /* nopw 0L(%[re]ax,%[re]ax,1) */ | |
827 | static const char alt_9[] = | |
828 | {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
829 | /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
830 | static const char alt_10[] = | |
831 | {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
832 | /* data16 | |
833 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
834 | static const char alt_long_11[] = | |
835 | {0x66, | |
836 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
837 | /* data16 | |
838 | data16 | |
839 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
840 | static const char alt_long_12[] = | |
841 | {0x66, | |
842 | 0x66, | |
843 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
844 | /* data16 | |
845 | data16 | |
846 | data16 | |
847 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
848 | static const char alt_long_13[] = | |
849 | {0x66, | |
850 | 0x66, | |
851 | 0x66, | |
852 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
853 | /* data16 | |
854 | data16 | |
855 | data16 | |
856 | data16 | |
857 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
858 | static const char alt_long_14[] = | |
859 | {0x66, | |
860 | 0x66, | |
861 | 0x66, | |
862 | 0x66, | |
863 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
864 | /* data16 | |
865 | data16 | |
866 | data16 | |
867 | data16 | |
868 | data16 | |
869 | nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
870 | static const char alt_long_15[] = | |
871 | {0x66, | |
872 | 0x66, | |
873 | 0x66, | |
874 | 0x66, | |
875 | 0x66, | |
876 | 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
877 | /* nopl 0(%[re]ax,%[re]ax,1) | |
878 | nopw 0(%[re]ax,%[re]ax,1) */ | |
879 | static const char alt_short_11[] = | |
880 | {0x0f,0x1f,0x44,0x00,0x00, | |
881 | 0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
882 | /* nopw 0(%[re]ax,%[re]ax,1) | |
883 | nopw 0(%[re]ax,%[re]ax,1) */ | |
884 | static const char alt_short_12[] = | |
885 | {0x66,0x0f,0x1f,0x44,0x00,0x00, | |
886 | 0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
887 | /* nopw 0(%[re]ax,%[re]ax,1) | |
888 | nopl 0L(%[re]ax) */ | |
889 | static const char alt_short_13[] = | |
890 | {0x66,0x0f,0x1f,0x44,0x00,0x00, | |
891 | 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
892 | /* nopl 0L(%[re]ax) | |
893 | nopl 0L(%[re]ax) */ | |
894 | static const char alt_short_14[] = | |
895 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00, | |
896 | 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
897 | /* nopl 0L(%[re]ax) | |
898 | nopl 0L(%[re]ax,%[re]ax,1) */ | |
899 | static const char alt_short_15[] = | |
900 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00, | |
901 | 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
902 | static const char *const alt_short_patt[] = { | |
903 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
904 | alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13, | |
905 | alt_short_14, alt_short_15 | |
906 | }; | |
907 | static const char *const alt_long_patt[] = { | |
908 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
909 | alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13, | |
910 | alt_long_14, alt_long_15 | |
911 | }; | |
252b5132 | 912 | |
76bc74dc L |
913 | /* Only align for at least a positive non-zero boundary. */ |
914 | if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE) | |
33fef721 | 915 | return; |
3e73aa7c | 916 | |
ccc9c027 L |
917 | /* We need to decide which NOP sequence to use for 32bit and |
918 | 64bit. When -mtune= is used: | |
4eed87de | 919 | |
76bc74dc L |
920 | 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and |
921 | PROCESSOR_GENERIC32, f32_patt will be used. | |
922 | 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA, | |
923 | PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64, | |
924 | alt_long_patt will be used. | |
925 | 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and | |
926 | PROCESSOR_AMDFAM10, alt_short_patt will be used. | |
ccc9c027 | 927 | |
76bc74dc L |
928 | When -mtune= isn't used, alt_long_patt will be used if |
929 | cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will | |
930 | be used. | |
ccc9c027 L |
931 | |
932 | When -march= or .arch is used, we can't use anything beyond | |
933 | cpu_arch_isa_flags. */ | |
934 | ||
935 | if (flag_code == CODE_16BIT) | |
936 | { | |
ccc9c027 | 937 | if (count > 8) |
33fef721 | 938 | { |
76bc74dc L |
939 | memcpy (fragP->fr_literal + fragP->fr_fix, |
940 | jump_31, count); | |
941 | /* Adjust jump offset. */ | |
942 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; | |
252b5132 | 943 | } |
76bc74dc L |
944 | else |
945 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
946 | f16_patt[count - 1], count); | |
252b5132 | 947 | } |
33fef721 | 948 | else |
ccc9c027 L |
949 | { |
950 | const char *const *patt = NULL; | |
951 | ||
952 | if (cpu_arch_isa == PROCESSOR_UNKNOWN) | |
953 | { | |
954 | /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ | |
955 | switch (cpu_arch_tune) | |
956 | { | |
957 | case PROCESSOR_UNKNOWN: | |
958 | /* We use cpu_arch_isa_flags to check if we SHOULD | |
959 | optimize for Cpu686. */ | |
40fb9820 | 960 | if (cpu_arch_isa_flags.bitfield.cpui686) |
76bc74dc | 961 | patt = alt_long_patt; |
ccc9c027 L |
962 | else |
963 | patt = f32_patt; | |
964 | break; | |
ccc9c027 L |
965 | case PROCESSOR_PENTIUMPRO: |
966 | case PROCESSOR_PENTIUM4: | |
967 | case PROCESSOR_NOCONA: | |
ef05d495 | 968 | case PROCESSOR_CORE: |
76bc74dc L |
969 | case PROCESSOR_CORE2: |
970 | case PROCESSOR_GENERIC64: | |
971 | patt = alt_long_patt; | |
972 | break; | |
ccc9c027 L |
973 | case PROCESSOR_K6: |
974 | case PROCESSOR_ATHLON: | |
975 | case PROCESSOR_K8: | |
4eed87de | 976 | case PROCESSOR_AMDFAM10: |
ccc9c027 L |
977 | patt = alt_short_patt; |
978 | break; | |
76bc74dc | 979 | case PROCESSOR_I386: |
ccc9c027 L |
980 | case PROCESSOR_I486: |
981 | case PROCESSOR_PENTIUM: | |
982 | case PROCESSOR_GENERIC32: | |
983 | patt = f32_patt; | |
984 | break; | |
4eed87de | 985 | } |
ccc9c027 L |
986 | } |
987 | else | |
988 | { | |
989 | switch (cpu_arch_tune) | |
990 | { | |
991 | case PROCESSOR_UNKNOWN: | |
e6a14101 | 992 | /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be |
ccc9c027 L |
993 | PROCESSOR_UNKNOWN. */ |
994 | abort (); | |
995 | break; | |
996 | ||
76bc74dc | 997 | case PROCESSOR_I386: |
ccc9c027 L |
998 | case PROCESSOR_I486: |
999 | case PROCESSOR_PENTIUM: | |
ccc9c027 L |
1000 | case PROCESSOR_K6: |
1001 | case PROCESSOR_ATHLON: | |
1002 | case PROCESSOR_K8: | |
4eed87de | 1003 | case PROCESSOR_AMDFAM10: |
ccc9c027 L |
1004 | case PROCESSOR_GENERIC32: |
1005 | /* We use cpu_arch_isa_flags to check if we CAN optimize | |
1006 | for Cpu686. */ | |
40fb9820 | 1007 | if (cpu_arch_isa_flags.bitfield.cpui686) |
ccc9c027 L |
1008 | patt = alt_short_patt; |
1009 | else | |
1010 | patt = f32_patt; | |
1011 | break; | |
76bc74dc L |
1012 | case PROCESSOR_PENTIUMPRO: |
1013 | case PROCESSOR_PENTIUM4: | |
1014 | case PROCESSOR_NOCONA: | |
1015 | case PROCESSOR_CORE: | |
ef05d495 | 1016 | case PROCESSOR_CORE2: |
40fb9820 | 1017 | if (cpu_arch_isa_flags.bitfield.cpui686) |
ccc9c027 L |
1018 | patt = alt_long_patt; |
1019 | else | |
1020 | patt = f32_patt; | |
1021 | break; | |
1022 | case PROCESSOR_GENERIC64: | |
76bc74dc | 1023 | patt = alt_long_patt; |
ccc9c027 | 1024 | break; |
4eed87de | 1025 | } |
ccc9c027 L |
1026 | } |
1027 | ||
76bc74dc L |
1028 | if (patt == f32_patt) |
1029 | { | |
1030 | /* If the padding is less than 15 bytes, we use the normal | |
1031 | ones. Otherwise, we use a jump instruction and adjust | |
1032 | its offset. */ | |
1033 | if (count < 15) | |
1034 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
1035 | patt[count - 1], count); | |
1036 | else | |
1037 | { | |
1038 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
1039 | jump_31, count); | |
1040 | /* Adjust jump offset. */ | |
1041 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; | |
1042 | } | |
1043 | } | |
1044 | else | |
1045 | { | |
1046 | /* Maximum length of an instruction is 15 byte. If the | |
1047 | padding is greater than 15 bytes and we don't use jump, | |
1048 | we have to break it into smaller pieces. */ | |
1049 | int padding = count; | |
1050 | while (padding > 15) | |
1051 | { | |
1052 | padding -= 15; | |
1053 | memcpy (fragP->fr_literal + fragP->fr_fix + padding, | |
1054 | patt [14], 15); | |
1055 | } | |
1056 | ||
1057 | if (padding) | |
1058 | memcpy (fragP->fr_literal + fragP->fr_fix, | |
1059 | patt [padding - 1], padding); | |
1060 | } | |
ccc9c027 | 1061 | } |
33fef721 | 1062 | fragP->fr_var = count; |
252b5132 RH |
1063 | } |
1064 | ||
c6fb90c8 | 1065 | static INLINE int |
0dfbf9d7 | 1066 | operand_type_all_zero (const union i386_operand_type *x) |
40fb9820 | 1067 | { |
0dfbf9d7 | 1068 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1069 | { |
1070 | case 3: | |
0dfbf9d7 | 1071 | if (x->array[2]) |
c6fb90c8 L |
1072 | return 0; |
1073 | case 2: | |
0dfbf9d7 | 1074 | if (x->array[1]) |
c6fb90c8 L |
1075 | return 0; |
1076 | case 1: | |
0dfbf9d7 | 1077 | return !x->array[0]; |
c6fb90c8 L |
1078 | default: |
1079 | abort (); | |
1080 | } | |
40fb9820 L |
1081 | } |
1082 | ||
c6fb90c8 | 1083 | static INLINE void |
0dfbf9d7 | 1084 | operand_type_set (union i386_operand_type *x, unsigned int v) |
40fb9820 | 1085 | { |
0dfbf9d7 | 1086 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1087 | { |
1088 | case 3: | |
0dfbf9d7 | 1089 | x->array[2] = v; |
c6fb90c8 | 1090 | case 2: |
0dfbf9d7 | 1091 | x->array[1] = v; |
c6fb90c8 | 1092 | case 1: |
0dfbf9d7 | 1093 | x->array[0] = v; |
c6fb90c8 L |
1094 | break; |
1095 | default: | |
1096 | abort (); | |
1097 | } | |
1098 | } | |
40fb9820 | 1099 | |
c6fb90c8 | 1100 | static INLINE int |
0dfbf9d7 L |
1101 | operand_type_equal (const union i386_operand_type *x, |
1102 | const union i386_operand_type *y) | |
c6fb90c8 | 1103 | { |
0dfbf9d7 | 1104 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1105 | { |
1106 | case 3: | |
0dfbf9d7 | 1107 | if (x->array[2] != y->array[2]) |
c6fb90c8 L |
1108 | return 0; |
1109 | case 2: | |
0dfbf9d7 | 1110 | if (x->array[1] != y->array[1]) |
c6fb90c8 L |
1111 | return 0; |
1112 | case 1: | |
0dfbf9d7 | 1113 | return x->array[0] == y->array[0]; |
c6fb90c8 L |
1114 | break; |
1115 | default: | |
1116 | abort (); | |
1117 | } | |
1118 | } | |
40fb9820 | 1119 | |
0dfbf9d7 L |
1120 | static INLINE int |
1121 | cpu_flags_all_zero (const union i386_cpu_flags *x) | |
1122 | { | |
1123 | switch (ARRAY_SIZE(x->array)) | |
1124 | { | |
1125 | case 3: | |
1126 | if (x->array[2]) | |
1127 | return 0; | |
1128 | case 2: | |
1129 | if (x->array[1]) | |
1130 | return 0; | |
1131 | case 1: | |
1132 | return !x->array[0]; | |
1133 | default: | |
1134 | abort (); | |
1135 | } | |
1136 | } | |
1137 | ||
1138 | static INLINE void | |
1139 | cpu_flags_set (union i386_cpu_flags *x, unsigned int v) | |
1140 | { | |
1141 | switch (ARRAY_SIZE(x->array)) | |
1142 | { | |
1143 | case 3: | |
1144 | x->array[2] = v; | |
1145 | case 2: | |
1146 | x->array[1] = v; | |
1147 | case 1: | |
1148 | x->array[0] = v; | |
1149 | break; | |
1150 | default: | |
1151 | abort (); | |
1152 | } | |
1153 | } | |
1154 | ||
1155 | static INLINE int | |
1156 | cpu_flags_equal (const union i386_cpu_flags *x, | |
1157 | const union i386_cpu_flags *y) | |
1158 | { | |
1159 | switch (ARRAY_SIZE(x->array)) | |
1160 | { | |
1161 | case 3: | |
1162 | if (x->array[2] != y->array[2]) | |
1163 | return 0; | |
1164 | case 2: | |
1165 | if (x->array[1] != y->array[1]) | |
1166 | return 0; | |
1167 | case 1: | |
1168 | return x->array[0] == y->array[0]; | |
1169 | break; | |
1170 | default: | |
1171 | abort (); | |
1172 | } | |
1173 | } | |
c6fb90c8 L |
1174 | |
1175 | static INLINE int | |
1176 | cpu_flags_check_cpu64 (i386_cpu_flags f) | |
1177 | { | |
1178 | return !((flag_code == CODE_64BIT && f.bitfield.cpuno64) | |
1179 | || (flag_code != CODE_64BIT && f.bitfield.cpu64)); | |
40fb9820 L |
1180 | } |
1181 | ||
c6fb90c8 L |
1182 | static INLINE i386_cpu_flags |
1183 | cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1184 | { |
c6fb90c8 L |
1185 | switch (ARRAY_SIZE (x.array)) |
1186 | { | |
1187 | case 3: | |
1188 | x.array [2] &= y.array [2]; | |
1189 | case 2: | |
1190 | x.array [1] &= y.array [1]; | |
1191 | case 1: | |
1192 | x.array [0] &= y.array [0]; | |
1193 | break; | |
1194 | default: | |
1195 | abort (); | |
1196 | } | |
1197 | return x; | |
1198 | } | |
40fb9820 | 1199 | |
c6fb90c8 L |
1200 | static INLINE i386_cpu_flags |
1201 | cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1202 | { |
c6fb90c8 | 1203 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1204 | { |
c6fb90c8 L |
1205 | case 3: |
1206 | x.array [2] |= y.array [2]; | |
1207 | case 2: | |
1208 | x.array [1] |= y.array [1]; | |
1209 | case 1: | |
1210 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1211 | break; |
1212 | default: | |
1213 | abort (); | |
1214 | } | |
40fb9820 L |
1215 | return x; |
1216 | } | |
1217 | ||
c0f3af97 L |
1218 | #define CPU_FLAGS_ARCH_MATCH 0x1 |
1219 | #define CPU_FLAGS_64BIT_MATCH 0x2 | |
a5ff0eb2 L |
1220 | #define CPU_FLAGS_AES_MATCH 0x4 |
1221 | #define CPU_FLAGS_AVX_MATCH 0x8 | |
c0f3af97 | 1222 | |
a5ff0eb2 L |
1223 | #define CPU_FLAGS_32BIT_MATCH \ |
1224 | (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH | CPU_FLAGS_AVX_MATCH) | |
c0f3af97 L |
1225 | #define CPU_FLAGS_PERFECT_MATCH \ |
1226 | (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH) | |
1227 | ||
1228 | /* Return CPU flags match bits. */ | |
3629bb00 | 1229 | |
40fb9820 | 1230 | static int |
c0f3af97 | 1231 | cpu_flags_match (const template *t) |
40fb9820 | 1232 | { |
c0f3af97 L |
1233 | i386_cpu_flags x = t->cpu_flags; |
1234 | int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0; | |
40fb9820 L |
1235 | |
1236 | x.bitfield.cpu64 = 0; | |
1237 | x.bitfield.cpuno64 = 0; | |
1238 | ||
0dfbf9d7 | 1239 | if (cpu_flags_all_zero (&x)) |
c0f3af97 L |
1240 | { |
1241 | /* This instruction is available on all archs. */ | |
1242 | match |= CPU_FLAGS_32BIT_MATCH; | |
1243 | } | |
3629bb00 L |
1244 | else |
1245 | { | |
c0f3af97 | 1246 | /* This instruction is available only on some archs. */ |
3629bb00 L |
1247 | i386_cpu_flags cpu = cpu_arch_flags; |
1248 | ||
1249 | cpu.bitfield.cpu64 = 0; | |
1250 | cpu.bitfield.cpuno64 = 0; | |
1251 | cpu = cpu_flags_and (x, cpu); | |
c0f3af97 L |
1252 | if (!cpu_flags_all_zero (&cpu)) |
1253 | { | |
a5ff0eb2 L |
1254 | if (x.bitfield.cpuavx) |
1255 | { | |
1256 | /* We only need to check AES/SSE2AVX with AVX. */ | |
1257 | if (cpu.bitfield.cpuavx) | |
1258 | { | |
1259 | /* Check SSE2AVX. */ | |
1260 | if (!t->opcode_modifier.sse2avx|| sse2avx) | |
1261 | { | |
1262 | match |= (CPU_FLAGS_ARCH_MATCH | |
1263 | | CPU_FLAGS_AVX_MATCH); | |
1264 | /* Check AES. */ | |
1265 | if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes) | |
1266 | match |= CPU_FLAGS_AES_MATCH; | |
1267 | } | |
1268 | } | |
1269 | else | |
1270 | match |= CPU_FLAGS_ARCH_MATCH; | |
1271 | } | |
1272 | else | |
c0f3af97 L |
1273 | match |= CPU_FLAGS_32BIT_MATCH; |
1274 | } | |
3629bb00 | 1275 | } |
c0f3af97 | 1276 | return match; |
40fb9820 L |
1277 | } |
1278 | ||
c6fb90c8 L |
1279 | static INLINE i386_operand_type |
1280 | operand_type_and (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1281 | { |
c6fb90c8 L |
1282 | switch (ARRAY_SIZE (x.array)) |
1283 | { | |
1284 | case 3: | |
1285 | x.array [2] &= y.array [2]; | |
1286 | case 2: | |
1287 | x.array [1] &= y.array [1]; | |
1288 | case 1: | |
1289 | x.array [0] &= y.array [0]; | |
1290 | break; | |
1291 | default: | |
1292 | abort (); | |
1293 | } | |
1294 | return x; | |
40fb9820 L |
1295 | } |
1296 | ||
c6fb90c8 L |
1297 | static INLINE i386_operand_type |
1298 | operand_type_or (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1299 | { |
c6fb90c8 | 1300 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1301 | { |
c6fb90c8 L |
1302 | case 3: |
1303 | x.array [2] |= y.array [2]; | |
1304 | case 2: | |
1305 | x.array [1] |= y.array [1]; | |
1306 | case 1: | |
1307 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1308 | break; |
1309 | default: | |
1310 | abort (); | |
1311 | } | |
c6fb90c8 L |
1312 | return x; |
1313 | } | |
40fb9820 | 1314 | |
c6fb90c8 L |
1315 | static INLINE i386_operand_type |
1316 | operand_type_xor (i386_operand_type x, i386_operand_type y) | |
1317 | { | |
1318 | switch (ARRAY_SIZE (x.array)) | |
1319 | { | |
1320 | case 3: | |
1321 | x.array [2] ^= y.array [2]; | |
1322 | case 2: | |
1323 | x.array [1] ^= y.array [1]; | |
1324 | case 1: | |
1325 | x.array [0] ^= y.array [0]; | |
1326 | break; | |
1327 | default: | |
1328 | abort (); | |
1329 | } | |
40fb9820 L |
1330 | return x; |
1331 | } | |
1332 | ||
1333 | static const i386_operand_type acc32 = OPERAND_TYPE_ACC32; | |
1334 | static const i386_operand_type acc64 = OPERAND_TYPE_ACC64; | |
1335 | static const i386_operand_type control = OPERAND_TYPE_CONTROL; | |
65da13b5 L |
1336 | static const i386_operand_type inoutportreg |
1337 | = OPERAND_TYPE_INOUTPORTREG; | |
40fb9820 L |
1338 | static const i386_operand_type reg16_inoutportreg |
1339 | = OPERAND_TYPE_REG16_INOUTPORTREG; | |
1340 | static const i386_operand_type disp16 = OPERAND_TYPE_DISP16; | |
1341 | static const i386_operand_type disp32 = OPERAND_TYPE_DISP32; | |
1342 | static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S; | |
1343 | static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32; | |
1344 | static const i386_operand_type anydisp | |
1345 | = OPERAND_TYPE_ANYDISP; | |
40fb9820 | 1346 | static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM; |
c0f3af97 | 1347 | static const i386_operand_type regymm = OPERAND_TYPE_REGYMM; |
40fb9820 L |
1348 | static const i386_operand_type imm8 = OPERAND_TYPE_IMM8; |
1349 | static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S; | |
1350 | static const i386_operand_type imm16 = OPERAND_TYPE_IMM16; | |
1351 | static const i386_operand_type imm32 = OPERAND_TYPE_IMM32; | |
1352 | static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S; | |
1353 | static const i386_operand_type imm64 = OPERAND_TYPE_IMM64; | |
1354 | static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32; | |
1355 | static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S; | |
1356 | static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S; | |
c0f3af97 | 1357 | static const i386_operand_type vex_imm4 = OPERAND_TYPE_VEX_IMM4; |
40fb9820 L |
1358 | |
1359 | enum operand_type | |
1360 | { | |
1361 | reg, | |
40fb9820 L |
1362 | imm, |
1363 | disp, | |
1364 | anymem | |
1365 | }; | |
1366 | ||
c6fb90c8 | 1367 | static INLINE int |
40fb9820 L |
1368 | operand_type_check (i386_operand_type t, enum operand_type c) |
1369 | { | |
1370 | switch (c) | |
1371 | { | |
1372 | case reg: | |
1373 | return (t.bitfield.reg8 | |
1374 | || t.bitfield.reg16 | |
1375 | || t.bitfield.reg32 | |
1376 | || t.bitfield.reg64); | |
1377 | ||
40fb9820 L |
1378 | case imm: |
1379 | return (t.bitfield.imm8 | |
1380 | || t.bitfield.imm8s | |
1381 | || t.bitfield.imm16 | |
1382 | || t.bitfield.imm32 | |
1383 | || t.bitfield.imm32s | |
1384 | || t.bitfield.imm64); | |
1385 | ||
1386 | case disp: | |
1387 | return (t.bitfield.disp8 | |
1388 | || t.bitfield.disp16 | |
1389 | || t.bitfield.disp32 | |
1390 | || t.bitfield.disp32s | |
1391 | || t.bitfield.disp64); | |
1392 | ||
1393 | case anymem: | |
1394 | return (t.bitfield.disp8 | |
1395 | || t.bitfield.disp16 | |
1396 | || t.bitfield.disp32 | |
1397 | || t.bitfield.disp32s | |
1398 | || t.bitfield.disp64 | |
1399 | || t.bitfield.baseindex); | |
1400 | ||
1401 | default: | |
1402 | abort (); | |
1403 | } | |
2cfe26b6 AM |
1404 | |
1405 | return 0; | |
40fb9820 L |
1406 | } |
1407 | ||
5c07affc L |
1408 | /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on |
1409 | operand J for instruction template T. */ | |
1410 | ||
1411 | static INLINE int | |
1412 | match_reg_size (const template *t, unsigned int j) | |
1413 | { | |
1414 | return !((i.types[j].bitfield.byte | |
1415 | && !t->operand_types[j].bitfield.byte) | |
1416 | || (i.types[j].bitfield.word | |
1417 | && !t->operand_types[j].bitfield.word) | |
1418 | || (i.types[j].bitfield.dword | |
1419 | && !t->operand_types[j].bitfield.dword) | |
1420 | || (i.types[j].bitfield.qword | |
1421 | && !t->operand_types[j].bitfield.qword)); | |
1422 | } | |
1423 | ||
1424 | /* Return 1 if there is no conflict in any size on operand J for | |
1425 | instruction template T. */ | |
1426 | ||
1427 | static INLINE int | |
1428 | match_mem_size (const template *t, unsigned int j) | |
1429 | { | |
1430 | return (match_reg_size (t, j) | |
1431 | && !((i.types[j].bitfield.unspecified | |
1432 | && !t->operand_types[j].bitfield.unspecified) | |
1433 | || (i.types[j].bitfield.fword | |
1434 | && !t->operand_types[j].bitfield.fword) | |
1435 | || (i.types[j].bitfield.tbyte | |
1436 | && !t->operand_types[j].bitfield.tbyte) | |
1437 | || (i.types[j].bitfield.xmmword | |
c0f3af97 L |
1438 | && !t->operand_types[j].bitfield.xmmword) |
1439 | || (i.types[j].bitfield.ymmword | |
1440 | && !t->operand_types[j].bitfield.ymmword))); | |
5c07affc L |
1441 | } |
1442 | ||
1443 | /* Return 1 if there is no size conflict on any operands for | |
1444 | instruction template T. */ | |
1445 | ||
1446 | static INLINE int | |
1447 | operand_size_match (const template *t) | |
1448 | { | |
1449 | unsigned int j; | |
1450 | int match = 1; | |
1451 | ||
1452 | /* Don't check jump instructions. */ | |
1453 | if (t->opcode_modifier.jump | |
1454 | || t->opcode_modifier.jumpbyte | |
1455 | || t->opcode_modifier.jumpdword | |
1456 | || t->opcode_modifier.jumpintersegment) | |
1457 | return match; | |
1458 | ||
1459 | /* Check memory and accumulator operand size. */ | |
1460 | for (j = 0; j < i.operands; j++) | |
1461 | { | |
1462 | if (t->operand_types[j].bitfield.anysize) | |
1463 | continue; | |
1464 | ||
1465 | if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j)) | |
1466 | { | |
1467 | match = 0; | |
1468 | break; | |
1469 | } | |
1470 | ||
1471 | if (i.types[j].bitfield.mem && !match_mem_size (t, j)) | |
1472 | { | |
1473 | match = 0; | |
1474 | break; | |
1475 | } | |
1476 | } | |
1477 | ||
1478 | if (match | |
1479 | || (!t->opcode_modifier.d && !t->opcode_modifier.floatd)) | |
1480 | return match; | |
1481 | ||
1482 | /* Check reverse. */ | |
1483 | assert (i.operands == 2); | |
1484 | ||
1485 | match = 1; | |
1486 | for (j = 0; j < 2; j++) | |
1487 | { | |
1488 | if (t->operand_types[j].bitfield.acc | |
1489 | && !match_reg_size (t, j ? 0 : 1)) | |
1490 | { | |
1491 | match = 0; | |
1492 | break; | |
1493 | } | |
1494 | ||
1495 | if (i.types[j].bitfield.mem | |
1496 | && !match_mem_size (t, j ? 0 : 1)) | |
1497 | { | |
1498 | match = 0; | |
1499 | break; | |
1500 | } | |
1501 | } | |
1502 | ||
1503 | return match; | |
1504 | } | |
1505 | ||
c6fb90c8 | 1506 | static INLINE int |
40fb9820 L |
1507 | operand_type_match (i386_operand_type overlap, |
1508 | i386_operand_type given) | |
1509 | { | |
1510 | i386_operand_type temp = overlap; | |
1511 | ||
1512 | temp.bitfield.jumpabsolute = 0; | |
7d5e4556 | 1513 | temp.bitfield.unspecified = 0; |
5c07affc L |
1514 | temp.bitfield.byte = 0; |
1515 | temp.bitfield.word = 0; | |
1516 | temp.bitfield.dword = 0; | |
1517 | temp.bitfield.fword = 0; | |
1518 | temp.bitfield.qword = 0; | |
1519 | temp.bitfield.tbyte = 0; | |
1520 | temp.bitfield.xmmword = 0; | |
c0f3af97 | 1521 | temp.bitfield.ymmword = 0; |
0dfbf9d7 | 1522 | if (operand_type_all_zero (&temp)) |
40fb9820 L |
1523 | return 0; |
1524 | ||
1525 | return (given.bitfield.baseindex == overlap.bitfield.baseindex | |
1526 | && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute); | |
1527 | } | |
1528 | ||
7d5e4556 | 1529 | /* If given types g0 and g1 are registers they must be of the same type |
40fb9820 L |
1530 | unless the expected operand type register overlap is null. |
1531 | Note that Acc in a template matches every size of reg. */ | |
1532 | ||
c6fb90c8 | 1533 | static INLINE int |
40fb9820 L |
1534 | operand_type_register_match (i386_operand_type m0, |
1535 | i386_operand_type g0, | |
1536 | i386_operand_type t0, | |
1537 | i386_operand_type m1, | |
1538 | i386_operand_type g1, | |
1539 | i386_operand_type t1) | |
1540 | { | |
1541 | if (!operand_type_check (g0, reg)) | |
1542 | return 1; | |
1543 | ||
1544 | if (!operand_type_check (g1, reg)) | |
1545 | return 1; | |
1546 | ||
1547 | if (g0.bitfield.reg8 == g1.bitfield.reg8 | |
1548 | && g0.bitfield.reg16 == g1.bitfield.reg16 | |
1549 | && g0.bitfield.reg32 == g1.bitfield.reg32 | |
1550 | && g0.bitfield.reg64 == g1.bitfield.reg64) | |
1551 | return 1; | |
1552 | ||
1553 | if (m0.bitfield.acc) | |
1554 | { | |
1555 | t0.bitfield.reg8 = 1; | |
1556 | t0.bitfield.reg16 = 1; | |
1557 | t0.bitfield.reg32 = 1; | |
1558 | t0.bitfield.reg64 = 1; | |
1559 | } | |
1560 | ||
1561 | if (m1.bitfield.acc) | |
1562 | { | |
1563 | t1.bitfield.reg8 = 1; | |
1564 | t1.bitfield.reg16 = 1; | |
1565 | t1.bitfield.reg32 = 1; | |
1566 | t1.bitfield.reg64 = 1; | |
1567 | } | |
1568 | ||
1569 | return (!(t0.bitfield.reg8 & t1.bitfield.reg8) | |
1570 | && !(t0.bitfield.reg16 & t1.bitfield.reg16) | |
1571 | && !(t0.bitfield.reg32 & t1.bitfield.reg32) | |
1572 | && !(t0.bitfield.reg64 & t1.bitfield.reg64)); | |
1573 | } | |
1574 | ||
252b5132 | 1575 | static INLINE unsigned int |
40fb9820 | 1576 | mode_from_disp_size (i386_operand_type t) |
252b5132 | 1577 | { |
40fb9820 L |
1578 | if (t.bitfield.disp8) |
1579 | return 1; | |
1580 | else if (t.bitfield.disp16 | |
1581 | || t.bitfield.disp32 | |
1582 | || t.bitfield.disp32s) | |
1583 | return 2; | |
1584 | else | |
1585 | return 0; | |
252b5132 RH |
1586 | } |
1587 | ||
1588 | static INLINE int | |
e3bb37b5 | 1589 | fits_in_signed_byte (offsetT num) |
252b5132 RH |
1590 | { |
1591 | return (num >= -128) && (num <= 127); | |
47926f60 | 1592 | } |
252b5132 RH |
1593 | |
1594 | static INLINE int | |
e3bb37b5 | 1595 | fits_in_unsigned_byte (offsetT num) |
252b5132 RH |
1596 | { |
1597 | return (num & 0xff) == num; | |
47926f60 | 1598 | } |
252b5132 RH |
1599 | |
1600 | static INLINE int | |
e3bb37b5 | 1601 | fits_in_unsigned_word (offsetT num) |
252b5132 RH |
1602 | { |
1603 | return (num & 0xffff) == num; | |
47926f60 | 1604 | } |
252b5132 RH |
1605 | |
1606 | static INLINE int | |
e3bb37b5 | 1607 | fits_in_signed_word (offsetT num) |
252b5132 RH |
1608 | { |
1609 | return (-32768 <= num) && (num <= 32767); | |
47926f60 | 1610 | } |
2a962e6d | 1611 | |
3e73aa7c | 1612 | static INLINE int |
e3bb37b5 | 1613 | fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
1614 | { |
1615 | #ifndef BFD64 | |
1616 | return 1; | |
1617 | #else | |
1618 | return (!(((offsetT) -1 << 31) & num) | |
1619 | || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31)); | |
1620 | #endif | |
1621 | } /* fits_in_signed_long() */ | |
2a962e6d | 1622 | |
3e73aa7c | 1623 | static INLINE int |
e3bb37b5 | 1624 | fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
1625 | { |
1626 | #ifndef BFD64 | |
1627 | return 1; | |
1628 | #else | |
1629 | return (num & (((offsetT) 2 << 31) - 1)) == num; | |
1630 | #endif | |
1631 | } /* fits_in_unsigned_long() */ | |
252b5132 | 1632 | |
c0f3af97 L |
1633 | static INLINE int |
1634 | fits_in_imm4 (offsetT num) | |
1635 | { | |
1636 | return (num & 0xf) == num; | |
1637 | } | |
1638 | ||
40fb9820 | 1639 | static i386_operand_type |
e3bb37b5 | 1640 | smallest_imm_type (offsetT num) |
252b5132 | 1641 | { |
40fb9820 L |
1642 | i386_operand_type t; |
1643 | ||
0dfbf9d7 | 1644 | operand_type_set (&t, 0); |
40fb9820 L |
1645 | t.bitfield.imm64 = 1; |
1646 | ||
1647 | if (cpu_arch_tune != PROCESSOR_I486 && num == 1) | |
e413e4e9 AM |
1648 | { |
1649 | /* This code is disabled on the 486 because all the Imm1 forms | |
1650 | in the opcode table are slower on the i486. They're the | |
1651 | versions with the implicitly specified single-position | |
1652 | displacement, which has another syntax if you really want to | |
1653 | use that form. */ | |
40fb9820 L |
1654 | t.bitfield.imm1 = 1; |
1655 | t.bitfield.imm8 = 1; | |
1656 | t.bitfield.imm8s = 1; | |
1657 | t.bitfield.imm16 = 1; | |
1658 | t.bitfield.imm32 = 1; | |
1659 | t.bitfield.imm32s = 1; | |
1660 | } | |
1661 | else if (fits_in_signed_byte (num)) | |
1662 | { | |
1663 | t.bitfield.imm8 = 1; | |
1664 | t.bitfield.imm8s = 1; | |
1665 | t.bitfield.imm16 = 1; | |
1666 | t.bitfield.imm32 = 1; | |
1667 | t.bitfield.imm32s = 1; | |
1668 | } | |
1669 | else if (fits_in_unsigned_byte (num)) | |
1670 | { | |
1671 | t.bitfield.imm8 = 1; | |
1672 | t.bitfield.imm16 = 1; | |
1673 | t.bitfield.imm32 = 1; | |
1674 | t.bitfield.imm32s = 1; | |
1675 | } | |
1676 | else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
1677 | { | |
1678 | t.bitfield.imm16 = 1; | |
1679 | t.bitfield.imm32 = 1; | |
1680 | t.bitfield.imm32s = 1; | |
1681 | } | |
1682 | else if (fits_in_signed_long (num)) | |
1683 | { | |
1684 | t.bitfield.imm32 = 1; | |
1685 | t.bitfield.imm32s = 1; | |
1686 | } | |
1687 | else if (fits_in_unsigned_long (num)) | |
1688 | t.bitfield.imm32 = 1; | |
1689 | ||
1690 | return t; | |
47926f60 | 1691 | } |
252b5132 | 1692 | |
847f7ad4 | 1693 | static offsetT |
e3bb37b5 | 1694 | offset_in_range (offsetT val, int size) |
847f7ad4 | 1695 | { |
508866be | 1696 | addressT mask; |
ba2adb93 | 1697 | |
847f7ad4 AM |
1698 | switch (size) |
1699 | { | |
508866be L |
1700 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
1701 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 1702 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
3e73aa7c JH |
1703 | #ifdef BFD64 |
1704 | case 8: mask = ((addressT) 2 << 63) - 1; break; | |
1705 | #endif | |
47926f60 | 1706 | default: abort (); |
847f7ad4 AM |
1707 | } |
1708 | ||
ba2adb93 | 1709 | /* If BFD64, sign extend val. */ |
3e73aa7c JH |
1710 | if (!use_rela_relocations) |
1711 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) | |
1712 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
ba2adb93 | 1713 | |
47926f60 | 1714 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
847f7ad4 AM |
1715 | { |
1716 | char buf1[40], buf2[40]; | |
1717 | ||
1718 | sprint_value (buf1, val); | |
1719 | sprint_value (buf2, val & mask); | |
1720 | as_warn (_("%s shortened to %s"), buf1, buf2); | |
1721 | } | |
1722 | return val & mask; | |
1723 | } | |
1724 | ||
252b5132 RH |
1725 | /* Returns 0 if attempting to add a prefix where one from the same |
1726 | class already exists, 1 if non rep/repne added, 2 if rep/repne | |
1727 | added. */ | |
1728 | static int | |
e3bb37b5 | 1729 | add_prefix (unsigned int prefix) |
252b5132 RH |
1730 | { |
1731 | int ret = 1; | |
b1905489 | 1732 | unsigned int q; |
252b5132 | 1733 | |
29b0f896 AM |
1734 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
1735 | && flag_code == CODE_64BIT) | |
b1905489 | 1736 | { |
161a04f6 L |
1737 | if ((i.prefix[REX_PREFIX] & prefix & REX_W) |
1738 | || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B)) | |
1739 | && (prefix & (REX_R | REX_X | REX_B)))) | |
b1905489 JB |
1740 | ret = 0; |
1741 | q = REX_PREFIX; | |
1742 | } | |
3e73aa7c | 1743 | else |
b1905489 JB |
1744 | { |
1745 | switch (prefix) | |
1746 | { | |
1747 | default: | |
1748 | abort (); | |
1749 | ||
1750 | case CS_PREFIX_OPCODE: | |
1751 | case DS_PREFIX_OPCODE: | |
1752 | case ES_PREFIX_OPCODE: | |
1753 | case FS_PREFIX_OPCODE: | |
1754 | case GS_PREFIX_OPCODE: | |
1755 | case SS_PREFIX_OPCODE: | |
1756 | q = SEG_PREFIX; | |
1757 | break; | |
1758 | ||
1759 | case REPNE_PREFIX_OPCODE: | |
1760 | case REPE_PREFIX_OPCODE: | |
1761 | ret = 2; | |
1762 | /* fall thru */ | |
1763 | case LOCK_PREFIX_OPCODE: | |
1764 | q = LOCKREP_PREFIX; | |
1765 | break; | |
1766 | ||
1767 | case FWAIT_OPCODE: | |
1768 | q = WAIT_PREFIX; | |
1769 | break; | |
1770 | ||
1771 | case ADDR_PREFIX_OPCODE: | |
1772 | q = ADDR_PREFIX; | |
1773 | break; | |
1774 | ||
1775 | case DATA_PREFIX_OPCODE: | |
1776 | q = DATA_PREFIX; | |
1777 | break; | |
1778 | } | |
1779 | if (i.prefix[q] != 0) | |
1780 | ret = 0; | |
1781 | } | |
252b5132 | 1782 | |
b1905489 | 1783 | if (ret) |
252b5132 | 1784 | { |
b1905489 JB |
1785 | if (!i.prefix[q]) |
1786 | ++i.prefixes; | |
1787 | i.prefix[q] |= prefix; | |
252b5132 | 1788 | } |
b1905489 JB |
1789 | else |
1790 | as_bad (_("same type of prefix used twice")); | |
252b5132 | 1791 | |
252b5132 RH |
1792 | return ret; |
1793 | } | |
1794 | ||
1795 | static void | |
e3bb37b5 | 1796 | set_code_flag (int value) |
eecb386c | 1797 | { |
3e73aa7c | 1798 | flag_code = value; |
40fb9820 L |
1799 | if (flag_code == CODE_64BIT) |
1800 | { | |
1801 | cpu_arch_flags.bitfield.cpu64 = 1; | |
1802 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
40fb9820 L |
1803 | } |
1804 | else | |
1805 | { | |
1806 | cpu_arch_flags.bitfield.cpu64 = 0; | |
1807 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
40fb9820 L |
1808 | } |
1809 | if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm ) | |
3e73aa7c JH |
1810 | { |
1811 | as_bad (_("64bit mode not supported on this CPU.")); | |
1812 | } | |
40fb9820 | 1813 | if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) |
3e73aa7c JH |
1814 | { |
1815 | as_bad (_("32bit mode not supported on this CPU.")); | |
1816 | } | |
eecb386c AM |
1817 | stackop_size = '\0'; |
1818 | } | |
1819 | ||
1820 | static void | |
e3bb37b5 | 1821 | set_16bit_gcc_code_flag (int new_code_flag) |
252b5132 | 1822 | { |
3e73aa7c | 1823 | flag_code = new_code_flag; |
40fb9820 L |
1824 | if (flag_code != CODE_16BIT) |
1825 | abort (); | |
1826 | cpu_arch_flags.bitfield.cpu64 = 0; | |
1827 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
9306ca4a | 1828 | stackop_size = LONG_MNEM_SUFFIX; |
252b5132 RH |
1829 | } |
1830 | ||
1831 | static void | |
e3bb37b5 | 1832 | set_intel_syntax (int syntax_flag) |
252b5132 RH |
1833 | { |
1834 | /* Find out if register prefixing is specified. */ | |
1835 | int ask_naked_reg = 0; | |
1836 | ||
1837 | SKIP_WHITESPACE (); | |
29b0f896 | 1838 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
252b5132 RH |
1839 | { |
1840 | char *string = input_line_pointer; | |
1841 | int e = get_symbol_end (); | |
1842 | ||
47926f60 | 1843 | if (strcmp (string, "prefix") == 0) |
252b5132 | 1844 | ask_naked_reg = 1; |
47926f60 | 1845 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
1846 | ask_naked_reg = -1; |
1847 | else | |
d0b47220 | 1848 | as_bad (_("bad argument to syntax directive.")); |
252b5132 RH |
1849 | *input_line_pointer = e; |
1850 | } | |
1851 | demand_empty_rest_of_line (); | |
c3332e24 | 1852 | |
252b5132 RH |
1853 | intel_syntax = syntax_flag; |
1854 | ||
1855 | if (ask_naked_reg == 0) | |
f86103b7 AM |
1856 | allow_naked_reg = (intel_syntax |
1857 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); | |
252b5132 RH |
1858 | else |
1859 | allow_naked_reg = (ask_naked_reg < 0); | |
9306ca4a | 1860 | |
e4a3b5a4 | 1861 | identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; |
9306ca4a | 1862 | identifier_chars['$'] = intel_syntax ? '$' : 0; |
e4a3b5a4 | 1863 | register_prefix = allow_naked_reg ? "" : "%"; |
252b5132 RH |
1864 | } |
1865 | ||
1efbbeb4 L |
1866 | static void |
1867 | set_intel_mnemonic (int mnemonic_flag) | |
1868 | { | |
e1d4d893 | 1869 | intel_mnemonic = mnemonic_flag; |
1efbbeb4 L |
1870 | } |
1871 | ||
db51cc60 L |
1872 | static void |
1873 | set_allow_index_reg (int flag) | |
1874 | { | |
1875 | allow_index_reg = flag; | |
1876 | } | |
1877 | ||
cb19c032 L |
1878 | static void |
1879 | set_sse_check (int dummy ATTRIBUTE_UNUSED) | |
1880 | { | |
1881 | SKIP_WHITESPACE (); | |
1882 | ||
1883 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
1884 | { | |
1885 | char *string = input_line_pointer; | |
1886 | int e = get_symbol_end (); | |
1887 | ||
1888 | if (strcmp (string, "none") == 0) | |
1889 | sse_check = sse_check_none; | |
1890 | else if (strcmp (string, "warning") == 0) | |
1891 | sse_check = sse_check_warning; | |
1892 | else if (strcmp (string, "error") == 0) | |
1893 | sse_check = sse_check_error; | |
1894 | else | |
1895 | as_bad (_("bad argument to sse_check directive.")); | |
1896 | *input_line_pointer = e; | |
1897 | } | |
1898 | else | |
1899 | as_bad (_("missing argument for sse_check directive")); | |
1900 | ||
1901 | demand_empty_rest_of_line (); | |
1902 | } | |
1903 | ||
e413e4e9 | 1904 | static void |
e3bb37b5 | 1905 | set_cpu_arch (int dummy ATTRIBUTE_UNUSED) |
e413e4e9 | 1906 | { |
47926f60 | 1907 | SKIP_WHITESPACE (); |
e413e4e9 | 1908 | |
29b0f896 | 1909 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
e413e4e9 AM |
1910 | { |
1911 | char *string = input_line_pointer; | |
1912 | int e = get_symbol_end (); | |
9103f4f4 | 1913 | unsigned int i; |
40fb9820 | 1914 | i386_cpu_flags flags; |
e413e4e9 | 1915 | |
9103f4f4 | 1916 | for (i = 0; i < ARRAY_SIZE (cpu_arch); i++) |
e413e4e9 AM |
1917 | { |
1918 | if (strcmp (string, cpu_arch[i].name) == 0) | |
1919 | { | |
5c6af06e JB |
1920 | if (*string != '.') |
1921 | { | |
1922 | cpu_arch_name = cpu_arch[i].name; | |
1923 | cpu_sub_arch_name = NULL; | |
40fb9820 L |
1924 | cpu_arch_flags = cpu_arch[i].flags; |
1925 | if (flag_code == CODE_64BIT) | |
1926 | { | |
1927 | cpu_arch_flags.bitfield.cpu64 = 1; | |
1928 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
1929 | } | |
1930 | else | |
1931 | { | |
1932 | cpu_arch_flags.bitfield.cpu64 = 0; | |
1933 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
1934 | } | |
ccc9c027 | 1935 | cpu_arch_isa = cpu_arch[i].type; |
9103f4f4 | 1936 | cpu_arch_isa_flags = cpu_arch[i].flags; |
ccc9c027 L |
1937 | if (!cpu_arch_tune_set) |
1938 | { | |
1939 | cpu_arch_tune = cpu_arch_isa; | |
1940 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
1941 | } | |
5c6af06e JB |
1942 | break; |
1943 | } | |
40fb9820 | 1944 | |
c6fb90c8 L |
1945 | flags = cpu_flags_or (cpu_arch_flags, |
1946 | cpu_arch[i].flags); | |
0dfbf9d7 | 1947 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
5c6af06e | 1948 | { |
6305a203 L |
1949 | if (cpu_sub_arch_name) |
1950 | { | |
1951 | char *name = cpu_sub_arch_name; | |
1952 | cpu_sub_arch_name = concat (name, | |
1953 | cpu_arch[i].name, | |
1bf57e9f | 1954 | (const char *) NULL); |
6305a203 L |
1955 | free (name); |
1956 | } | |
1957 | else | |
1958 | cpu_sub_arch_name = xstrdup (cpu_arch[i].name); | |
40fb9820 | 1959 | cpu_arch_flags = flags; |
5c6af06e JB |
1960 | } |
1961 | *input_line_pointer = e; | |
1962 | demand_empty_rest_of_line (); | |
1963 | return; | |
e413e4e9 AM |
1964 | } |
1965 | } | |
9103f4f4 | 1966 | if (i >= ARRAY_SIZE (cpu_arch)) |
e413e4e9 AM |
1967 | as_bad (_("no such architecture: `%s'"), string); |
1968 | ||
1969 | *input_line_pointer = e; | |
1970 | } | |
1971 | else | |
1972 | as_bad (_("missing cpu architecture")); | |
1973 | ||
fddf5b5b AM |
1974 | no_cond_jump_promotion = 0; |
1975 | if (*input_line_pointer == ',' | |
29b0f896 | 1976 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
fddf5b5b AM |
1977 | { |
1978 | char *string = ++input_line_pointer; | |
1979 | int e = get_symbol_end (); | |
1980 | ||
1981 | if (strcmp (string, "nojumps") == 0) | |
1982 | no_cond_jump_promotion = 1; | |
1983 | else if (strcmp (string, "jumps") == 0) | |
1984 | ; | |
1985 | else | |
1986 | as_bad (_("no such architecture modifier: `%s'"), string); | |
1987 | ||
1988 | *input_line_pointer = e; | |
1989 | } | |
1990 | ||
e413e4e9 AM |
1991 | demand_empty_rest_of_line (); |
1992 | } | |
1993 | ||
b9d79e03 JH |
1994 | unsigned long |
1995 | i386_mach () | |
1996 | { | |
1997 | if (!strcmp (default_arch, "x86_64")) | |
1998 | return bfd_mach_x86_64; | |
1999 | else if (!strcmp (default_arch, "i386")) | |
2000 | return bfd_mach_i386_i386; | |
2001 | else | |
2002 | as_fatal (_("Unknown architecture")); | |
2003 | } | |
b9d79e03 | 2004 | \f |
252b5132 RH |
2005 | void |
2006 | md_begin () | |
2007 | { | |
2008 | const char *hash_err; | |
2009 | ||
47926f60 | 2010 | /* Initialize op_hash hash table. */ |
252b5132 RH |
2011 | op_hash = hash_new (); |
2012 | ||
2013 | { | |
29b0f896 AM |
2014 | const template *optab; |
2015 | templates *core_optab; | |
252b5132 | 2016 | |
47926f60 KH |
2017 | /* Setup for loop. */ |
2018 | optab = i386_optab; | |
252b5132 RH |
2019 | core_optab = (templates *) xmalloc (sizeof (templates)); |
2020 | core_optab->start = optab; | |
2021 | ||
2022 | while (1) | |
2023 | { | |
2024 | ++optab; | |
2025 | if (optab->name == NULL | |
2026 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
2027 | { | |
2028 | /* different name --> ship out current template list; | |
47926f60 | 2029 | add to hash table; & begin anew. */ |
252b5132 RH |
2030 | core_optab->end = optab; |
2031 | hash_err = hash_insert (op_hash, | |
2032 | (optab - 1)->name, | |
5a49b8ac | 2033 | (void *) core_optab); |
252b5132 RH |
2034 | if (hash_err) |
2035 | { | |
252b5132 RH |
2036 | as_fatal (_("Internal Error: Can't hash %s: %s"), |
2037 | (optab - 1)->name, | |
2038 | hash_err); | |
2039 | } | |
2040 | if (optab->name == NULL) | |
2041 | break; | |
2042 | core_optab = (templates *) xmalloc (sizeof (templates)); | |
2043 | core_optab->start = optab; | |
2044 | } | |
2045 | } | |
2046 | } | |
2047 | ||
47926f60 | 2048 | /* Initialize reg_hash hash table. */ |
252b5132 RH |
2049 | reg_hash = hash_new (); |
2050 | { | |
29b0f896 | 2051 | const reg_entry *regtab; |
c3fe08fa | 2052 | unsigned int regtab_size = i386_regtab_size; |
252b5132 | 2053 | |
c3fe08fa | 2054 | for (regtab = i386_regtab; regtab_size--; regtab++) |
252b5132 | 2055 | { |
5a49b8ac | 2056 | hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab); |
252b5132 | 2057 | if (hash_err) |
3e73aa7c JH |
2058 | as_fatal (_("Internal Error: Can't hash %s: %s"), |
2059 | regtab->reg_name, | |
2060 | hash_err); | |
252b5132 RH |
2061 | } |
2062 | } | |
2063 | ||
47926f60 | 2064 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 | 2065 | { |
29b0f896 AM |
2066 | int c; |
2067 | char *p; | |
252b5132 RH |
2068 | |
2069 | for (c = 0; c < 256; c++) | |
2070 | { | |
3882b010 | 2071 | if (ISDIGIT (c)) |
252b5132 RH |
2072 | { |
2073 | digit_chars[c] = c; | |
2074 | mnemonic_chars[c] = c; | |
2075 | register_chars[c] = c; | |
2076 | operand_chars[c] = c; | |
2077 | } | |
3882b010 | 2078 | else if (ISLOWER (c)) |
252b5132 RH |
2079 | { |
2080 | mnemonic_chars[c] = c; | |
2081 | register_chars[c] = c; | |
2082 | operand_chars[c] = c; | |
2083 | } | |
3882b010 | 2084 | else if (ISUPPER (c)) |
252b5132 | 2085 | { |
3882b010 | 2086 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
2087 | register_chars[c] = mnemonic_chars[c]; |
2088 | operand_chars[c] = c; | |
2089 | } | |
2090 | ||
3882b010 | 2091 | if (ISALPHA (c) || ISDIGIT (c)) |
252b5132 RH |
2092 | identifier_chars[c] = c; |
2093 | else if (c >= 128) | |
2094 | { | |
2095 | identifier_chars[c] = c; | |
2096 | operand_chars[c] = c; | |
2097 | } | |
2098 | } | |
2099 | ||
2100 | #ifdef LEX_AT | |
2101 | identifier_chars['@'] = '@'; | |
32137342 NC |
2102 | #endif |
2103 | #ifdef LEX_QM | |
2104 | identifier_chars['?'] = '?'; | |
2105 | operand_chars['?'] = '?'; | |
252b5132 | 2106 | #endif |
252b5132 | 2107 | digit_chars['-'] = '-'; |
c0f3af97 | 2108 | mnemonic_chars['_'] = '_'; |
791fe849 | 2109 | mnemonic_chars['-'] = '-'; |
0003779b | 2110 | mnemonic_chars['.'] = '.'; |
252b5132 RH |
2111 | identifier_chars['_'] = '_'; |
2112 | identifier_chars['.'] = '.'; | |
2113 | ||
2114 | for (p = operand_special_chars; *p != '\0'; p++) | |
2115 | operand_chars[(unsigned char) *p] = *p; | |
2116 | } | |
2117 | ||
2118 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 2119 | if (IS_ELF) |
252b5132 RH |
2120 | { |
2121 | record_alignment (text_section, 2); | |
2122 | record_alignment (data_section, 2); | |
2123 | record_alignment (bss_section, 2); | |
2124 | } | |
2125 | #endif | |
a4447b93 RH |
2126 | |
2127 | if (flag_code == CODE_64BIT) | |
2128 | { | |
2129 | x86_dwarf2_return_column = 16; | |
2130 | x86_cie_data_alignment = -8; | |
2131 | } | |
2132 | else | |
2133 | { | |
2134 | x86_dwarf2_return_column = 8; | |
2135 | x86_cie_data_alignment = -4; | |
2136 | } | |
252b5132 RH |
2137 | } |
2138 | ||
2139 | void | |
e3bb37b5 | 2140 | i386_print_statistics (FILE *file) |
252b5132 RH |
2141 | { |
2142 | hash_print_statistics (file, "i386 opcode", op_hash); | |
2143 | hash_print_statistics (file, "i386 register", reg_hash); | |
2144 | } | |
2145 | \f | |
252b5132 RH |
2146 | #ifdef DEBUG386 |
2147 | ||
ce8a8b2f | 2148 | /* Debugging routines for md_assemble. */ |
e3bb37b5 | 2149 | static void pte (template *); |
40fb9820 | 2150 | static void pt (i386_operand_type); |
e3bb37b5 L |
2151 | static void pe (expressionS *); |
2152 | static void ps (symbolS *); | |
252b5132 RH |
2153 | |
2154 | static void | |
e3bb37b5 | 2155 | pi (char *line, i386_insn *x) |
252b5132 | 2156 | { |
09f131f2 | 2157 | unsigned int i; |
252b5132 RH |
2158 | |
2159 | fprintf (stdout, "%s: template ", line); | |
2160 | pte (&x->tm); | |
09f131f2 JH |
2161 | fprintf (stdout, " address: base %s index %s scale %x\n", |
2162 | x->base_reg ? x->base_reg->reg_name : "none", | |
2163 | x->index_reg ? x->index_reg->reg_name : "none", | |
2164 | x->log2_scale_factor); | |
2165 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 2166 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
2167 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
2168 | x->sib.base, x->sib.index, x->sib.scale); | |
2169 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
161a04f6 L |
2170 | (x->rex & REX_W) != 0, |
2171 | (x->rex & REX_R) != 0, | |
2172 | (x->rex & REX_X) != 0, | |
2173 | (x->rex & REX_B) != 0); | |
85f10a01 MM |
2174 | fprintf (stdout, " drex: reg %d rex 0x%x\n", |
2175 | x->drex.reg, x->drex.rex); | |
252b5132 RH |
2176 | for (i = 0; i < x->operands; i++) |
2177 | { | |
2178 | fprintf (stdout, " #%d: ", i + 1); | |
2179 | pt (x->types[i]); | |
2180 | fprintf (stdout, "\n"); | |
40fb9820 L |
2181 | if (x->types[i].bitfield.reg8 |
2182 | || x->types[i].bitfield.reg16 | |
2183 | || x->types[i].bitfield.reg32 | |
2184 | || x->types[i].bitfield.reg64 | |
2185 | || x->types[i].bitfield.regmmx | |
2186 | || x->types[i].bitfield.regxmm | |
c0f3af97 | 2187 | || x->types[i].bitfield.regymm |
40fb9820 L |
2188 | || x->types[i].bitfield.sreg2 |
2189 | || x->types[i].bitfield.sreg3 | |
2190 | || x->types[i].bitfield.control | |
2191 | || x->types[i].bitfield.debug | |
2192 | || x->types[i].bitfield.test) | |
520dc8e8 | 2193 | fprintf (stdout, "%s\n", x->op[i].regs->reg_name); |
40fb9820 | 2194 | if (operand_type_check (x->types[i], imm)) |
520dc8e8 | 2195 | pe (x->op[i].imms); |
40fb9820 | 2196 | if (operand_type_check (x->types[i], disp)) |
520dc8e8 | 2197 | pe (x->op[i].disps); |
252b5132 RH |
2198 | } |
2199 | } | |
2200 | ||
2201 | static void | |
e3bb37b5 | 2202 | pte (template *t) |
252b5132 | 2203 | { |
09f131f2 | 2204 | unsigned int i; |
252b5132 | 2205 | fprintf (stdout, " %d operands ", t->operands); |
47926f60 | 2206 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
2207 | if (t->extension_opcode != None) |
2208 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
40fb9820 | 2209 | if (t->opcode_modifier.d) |
252b5132 | 2210 | fprintf (stdout, "D"); |
40fb9820 | 2211 | if (t->opcode_modifier.w) |
252b5132 RH |
2212 | fprintf (stdout, "W"); |
2213 | fprintf (stdout, "\n"); | |
2214 | for (i = 0; i < t->operands; i++) | |
2215 | { | |
2216 | fprintf (stdout, " #%d type ", i + 1); | |
2217 | pt (t->operand_types[i]); | |
2218 | fprintf (stdout, "\n"); | |
2219 | } | |
2220 | } | |
2221 | ||
2222 | static void | |
e3bb37b5 | 2223 | pe (expressionS *e) |
252b5132 | 2224 | { |
24eab124 | 2225 | fprintf (stdout, " operation %d\n", e->X_op); |
b77ad1d4 AM |
2226 | fprintf (stdout, " add_number %ld (%lx)\n", |
2227 | (long) e->X_add_number, (long) e->X_add_number); | |
252b5132 RH |
2228 | if (e->X_add_symbol) |
2229 | { | |
2230 | fprintf (stdout, " add_symbol "); | |
2231 | ps (e->X_add_symbol); | |
2232 | fprintf (stdout, "\n"); | |
2233 | } | |
2234 | if (e->X_op_symbol) | |
2235 | { | |
2236 | fprintf (stdout, " op_symbol "); | |
2237 | ps (e->X_op_symbol); | |
2238 | fprintf (stdout, "\n"); | |
2239 | } | |
2240 | } | |
2241 | ||
2242 | static void | |
e3bb37b5 | 2243 | ps (symbolS *s) |
252b5132 RH |
2244 | { |
2245 | fprintf (stdout, "%s type %s%s", | |
2246 | S_GET_NAME (s), | |
2247 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
2248 | segment_name (S_GET_SEGMENT (s))); | |
2249 | } | |
2250 | ||
7b81dfbb | 2251 | static struct type_name |
252b5132 | 2252 | { |
40fb9820 L |
2253 | i386_operand_type mask; |
2254 | const char *name; | |
252b5132 | 2255 | } |
7b81dfbb | 2256 | const type_names[] = |
252b5132 | 2257 | { |
40fb9820 L |
2258 | { OPERAND_TYPE_REG8, "r8" }, |
2259 | { OPERAND_TYPE_REG16, "r16" }, | |
2260 | { OPERAND_TYPE_REG32, "r32" }, | |
2261 | { OPERAND_TYPE_REG64, "r64" }, | |
2262 | { OPERAND_TYPE_IMM8, "i8" }, | |
2263 | { OPERAND_TYPE_IMM8, "i8s" }, | |
2264 | { OPERAND_TYPE_IMM16, "i16" }, | |
2265 | { OPERAND_TYPE_IMM32, "i32" }, | |
2266 | { OPERAND_TYPE_IMM32S, "i32s" }, | |
2267 | { OPERAND_TYPE_IMM64, "i64" }, | |
2268 | { OPERAND_TYPE_IMM1, "i1" }, | |
2269 | { OPERAND_TYPE_BASEINDEX, "BaseIndex" }, | |
2270 | { OPERAND_TYPE_DISP8, "d8" }, | |
2271 | { OPERAND_TYPE_DISP16, "d16" }, | |
2272 | { OPERAND_TYPE_DISP32, "d32" }, | |
2273 | { OPERAND_TYPE_DISP32S, "d32s" }, | |
2274 | { OPERAND_TYPE_DISP64, "d64" }, | |
2275 | { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" }, | |
2276 | { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" }, | |
2277 | { OPERAND_TYPE_CONTROL, "control reg" }, | |
2278 | { OPERAND_TYPE_TEST, "test reg" }, | |
2279 | { OPERAND_TYPE_DEBUG, "debug reg" }, | |
2280 | { OPERAND_TYPE_FLOATREG, "FReg" }, | |
2281 | { OPERAND_TYPE_FLOATACC, "FAcc" }, | |
2282 | { OPERAND_TYPE_SREG2, "SReg2" }, | |
2283 | { OPERAND_TYPE_SREG3, "SReg3" }, | |
2284 | { OPERAND_TYPE_ACC, "Acc" }, | |
2285 | { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" }, | |
2286 | { OPERAND_TYPE_REGMMX, "rMMX" }, | |
2287 | { OPERAND_TYPE_REGXMM, "rXMM" }, | |
2288 | { OPERAND_TYPE_ESSEG, "es" }, | |
c0f3af97 | 2289 | { OPERAND_TYPE_VEX_IMM4, "VEX i4" }, |
252b5132 RH |
2290 | }; |
2291 | ||
2292 | static void | |
40fb9820 | 2293 | pt (i386_operand_type t) |
252b5132 | 2294 | { |
40fb9820 | 2295 | unsigned int j; |
c6fb90c8 | 2296 | i386_operand_type a; |
252b5132 | 2297 | |
40fb9820 | 2298 | for (j = 0; j < ARRAY_SIZE (type_names); j++) |
c6fb90c8 L |
2299 | { |
2300 | a = operand_type_and (t, type_names[j].mask); | |
2301 | if (!UINTS_ALL_ZERO (a)) | |
2302 | fprintf (stdout, "%s, ", type_names[j].name); | |
2303 | } | |
252b5132 RH |
2304 | fflush (stdout); |
2305 | } | |
2306 | ||
2307 | #endif /* DEBUG386 */ | |
2308 | \f | |
252b5132 | 2309 | static bfd_reloc_code_real_type |
3956db08 | 2310 | reloc (unsigned int size, |
64e74474 AM |
2311 | int pcrel, |
2312 | int sign, | |
2313 | bfd_reloc_code_real_type other) | |
252b5132 | 2314 | { |
47926f60 | 2315 | if (other != NO_RELOC) |
3956db08 JB |
2316 | { |
2317 | reloc_howto_type *reloc; | |
2318 | ||
2319 | if (size == 8) | |
2320 | switch (other) | |
2321 | { | |
64e74474 AM |
2322 | case BFD_RELOC_X86_64_GOT32: |
2323 | return BFD_RELOC_X86_64_GOT64; | |
2324 | break; | |
2325 | case BFD_RELOC_X86_64_PLTOFF64: | |
2326 | return BFD_RELOC_X86_64_PLTOFF64; | |
2327 | break; | |
2328 | case BFD_RELOC_X86_64_GOTPC32: | |
2329 | other = BFD_RELOC_X86_64_GOTPC64; | |
2330 | break; | |
2331 | case BFD_RELOC_X86_64_GOTPCREL: | |
2332 | other = BFD_RELOC_X86_64_GOTPCREL64; | |
2333 | break; | |
2334 | case BFD_RELOC_X86_64_TPOFF32: | |
2335 | other = BFD_RELOC_X86_64_TPOFF64; | |
2336 | break; | |
2337 | case BFD_RELOC_X86_64_DTPOFF32: | |
2338 | other = BFD_RELOC_X86_64_DTPOFF64; | |
2339 | break; | |
2340 | default: | |
2341 | break; | |
3956db08 | 2342 | } |
e05278af JB |
2343 | |
2344 | /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ | |
2345 | if (size == 4 && flag_code != CODE_64BIT) | |
2346 | sign = -1; | |
2347 | ||
3956db08 JB |
2348 | reloc = bfd_reloc_type_lookup (stdoutput, other); |
2349 | if (!reloc) | |
2350 | as_bad (_("unknown relocation (%u)"), other); | |
2351 | else if (size != bfd_get_reloc_size (reloc)) | |
2352 | as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), | |
2353 | bfd_get_reloc_size (reloc), | |
2354 | size); | |
2355 | else if (pcrel && !reloc->pc_relative) | |
2356 | as_bad (_("non-pc-relative relocation for pc-relative field")); | |
2357 | else if ((reloc->complain_on_overflow == complain_overflow_signed | |
2358 | && !sign) | |
2359 | || (reloc->complain_on_overflow == complain_overflow_unsigned | |
64e74474 | 2360 | && sign > 0)) |
3956db08 JB |
2361 | as_bad (_("relocated field and relocation type differ in signedness")); |
2362 | else | |
2363 | return other; | |
2364 | return NO_RELOC; | |
2365 | } | |
252b5132 RH |
2366 | |
2367 | if (pcrel) | |
2368 | { | |
3e73aa7c | 2369 | if (!sign) |
3956db08 | 2370 | as_bad (_("there are no unsigned pc-relative relocations")); |
252b5132 RH |
2371 | switch (size) |
2372 | { | |
2373 | case 1: return BFD_RELOC_8_PCREL; | |
2374 | case 2: return BFD_RELOC_16_PCREL; | |
2375 | case 4: return BFD_RELOC_32_PCREL; | |
d6ab8113 | 2376 | case 8: return BFD_RELOC_64_PCREL; |
252b5132 | 2377 | } |
3956db08 | 2378 | as_bad (_("cannot do %u byte pc-relative relocation"), size); |
252b5132 RH |
2379 | } |
2380 | else | |
2381 | { | |
3956db08 | 2382 | if (sign > 0) |
e5cb08ac | 2383 | switch (size) |
3e73aa7c JH |
2384 | { |
2385 | case 4: return BFD_RELOC_X86_64_32S; | |
2386 | } | |
2387 | else | |
2388 | switch (size) | |
2389 | { | |
2390 | case 1: return BFD_RELOC_8; | |
2391 | case 2: return BFD_RELOC_16; | |
2392 | case 4: return BFD_RELOC_32; | |
2393 | case 8: return BFD_RELOC_64; | |
2394 | } | |
3956db08 JB |
2395 | as_bad (_("cannot do %s %u byte relocation"), |
2396 | sign > 0 ? "signed" : "unsigned", size); | |
252b5132 RH |
2397 | } |
2398 | ||
bfb32b52 | 2399 | abort (); |
252b5132 RH |
2400 | return BFD_RELOC_NONE; |
2401 | } | |
2402 | ||
47926f60 KH |
2403 | /* Here we decide which fixups can be adjusted to make them relative to |
2404 | the beginning of the section instead of the symbol. Basically we need | |
2405 | to make sure that the dynamic relocations are done correctly, so in | |
2406 | some cases we force the original symbol to be used. */ | |
2407 | ||
252b5132 | 2408 | int |
e3bb37b5 | 2409 | tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) |
252b5132 | 2410 | { |
6d249963 | 2411 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 2412 | if (!IS_ELF) |
31312f95 AM |
2413 | return 1; |
2414 | ||
a161fe53 AM |
2415 | /* Don't adjust pc-relative references to merge sections in 64-bit |
2416 | mode. */ | |
2417 | if (use_rela_relocations | |
2418 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 | |
2419 | && fixP->fx_pcrel) | |
252b5132 | 2420 | return 0; |
31312f95 | 2421 | |
8d01d9a9 AJ |
2422 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
2423 | and changed later by validate_fix. */ | |
2424 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol | |
2425 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) | |
2426 | return 0; | |
2427 | ||
ce8a8b2f | 2428 | /* adjust_reloc_syms doesn't know about the GOT. */ |
252b5132 RH |
2429 | if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF |
2430 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 | |
2431 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 | |
13ae64f3 JJ |
2432 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
2433 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM | |
2434 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 | |
2435 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 | |
37e55690 JJ |
2436 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
2437 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE | |
13ae64f3 JJ |
2438 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
2439 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE | |
67a4f2b7 AO |
2440 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC |
2441 | || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL | |
3e73aa7c JH |
2442 | || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 |
2443 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 | |
80b3ee89 | 2444 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
bffbf940 JJ |
2445 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
2446 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD | |
2447 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 | |
d6ab8113 | 2448 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 |
bffbf940 JJ |
2449 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF |
2450 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 | |
d6ab8113 JB |
2451 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 |
2452 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 | |
67a4f2b7 AO |
2453 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
2454 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL | |
252b5132 RH |
2455 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
2456 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
2457 | return 0; | |
31312f95 | 2458 | #endif |
252b5132 RH |
2459 | return 1; |
2460 | } | |
252b5132 | 2461 | |
b4cac588 | 2462 | static int |
e3bb37b5 | 2463 | intel_float_operand (const char *mnemonic) |
252b5132 | 2464 | { |
9306ca4a JB |
2465 | /* Note that the value returned is meaningful only for opcodes with (memory) |
2466 | operands, hence the code here is free to improperly handle opcodes that | |
2467 | have no operands (for better performance and smaller code). */ | |
2468 | ||
2469 | if (mnemonic[0] != 'f') | |
2470 | return 0; /* non-math */ | |
2471 | ||
2472 | switch (mnemonic[1]) | |
2473 | { | |
2474 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and | |
2475 | the fs segment override prefix not currently handled because no | |
2476 | call path can make opcodes without operands get here */ | |
2477 | case 'i': | |
2478 | return 2 /* integer op */; | |
2479 | case 'l': | |
2480 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) | |
2481 | return 3; /* fldcw/fldenv */ | |
2482 | break; | |
2483 | case 'n': | |
2484 | if (mnemonic[2] != 'o' /* fnop */) | |
2485 | return 3; /* non-waiting control op */ | |
2486 | break; | |
2487 | case 'r': | |
2488 | if (mnemonic[2] == 's') | |
2489 | return 3; /* frstor/frstpm */ | |
2490 | break; | |
2491 | case 's': | |
2492 | if (mnemonic[2] == 'a') | |
2493 | return 3; /* fsave */ | |
2494 | if (mnemonic[2] == 't') | |
2495 | { | |
2496 | switch (mnemonic[3]) | |
2497 | { | |
2498 | case 'c': /* fstcw */ | |
2499 | case 'd': /* fstdw */ | |
2500 | case 'e': /* fstenv */ | |
2501 | case 's': /* fsts[gw] */ | |
2502 | return 3; | |
2503 | } | |
2504 | } | |
2505 | break; | |
2506 | case 'x': | |
2507 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') | |
2508 | return 0; /* fxsave/fxrstor are not really math ops */ | |
2509 | break; | |
2510 | } | |
252b5132 | 2511 | |
9306ca4a | 2512 | return 1; |
252b5132 RH |
2513 | } |
2514 | ||
c0f3af97 L |
2515 | /* Build the VEX prefix. */ |
2516 | ||
2517 | static void | |
2518 | build_vex_prefix (void) | |
2519 | { | |
2520 | unsigned int register_specifier; | |
2521 | unsigned int implied_prefix; | |
2522 | unsigned int vector_length; | |
2523 | ||
2524 | /* Check register specifier. */ | |
2525 | if (i.vex.register_specifier) | |
2526 | { | |
2527 | register_specifier = i.vex.register_specifier->reg_num; | |
2528 | if ((i.vex.register_specifier->reg_flags & RegRex)) | |
2529 | register_specifier += 8; | |
2530 | register_specifier = ~register_specifier & 0xf; | |
2531 | } | |
2532 | else | |
2533 | register_specifier = 0xf; | |
2534 | ||
2535 | vector_length = i.tm.opcode_modifier.vex256 ? 1 : 0; | |
2536 | ||
2537 | switch ((i.tm.base_opcode >> 8) & 0xff) | |
2538 | { | |
2539 | case 0: | |
2540 | implied_prefix = 0; | |
2541 | break; | |
2542 | case DATA_PREFIX_OPCODE: | |
2543 | implied_prefix = 1; | |
2544 | break; | |
2545 | case REPE_PREFIX_OPCODE: | |
2546 | implied_prefix = 2; | |
2547 | break; | |
2548 | case REPNE_PREFIX_OPCODE: | |
2549 | implied_prefix = 3; | |
2550 | break; | |
2551 | default: | |
2552 | abort (); | |
2553 | } | |
2554 | ||
2555 | /* Use 2-byte VEX prefix if possible. */ | |
2556 | if (i.tm.opcode_modifier.vex0f | |
2557 | && (i.rex & (REX_W | REX_X | REX_B)) == 0) | |
2558 | { | |
2559 | /* 2-byte VEX prefix. */ | |
2560 | unsigned int r; | |
2561 | ||
2562 | i.vex.length = 2; | |
2563 | i.vex.bytes[0] = 0xc5; | |
2564 | ||
2565 | /* Check the REX.R bit. */ | |
2566 | r = (i.rex & REX_R) ? 0 : 1; | |
2567 | i.vex.bytes[1] = (r << 7 | |
2568 | | register_specifier << 3 | |
2569 | | vector_length << 2 | |
2570 | | implied_prefix); | |
2571 | } | |
2572 | else | |
2573 | { | |
2574 | /* 3-byte VEX prefix. */ | |
2575 | unsigned int m, w; | |
2576 | ||
2577 | if (i.tm.opcode_modifier.vex0f) | |
2578 | m = 0x1; | |
2579 | else if (i.tm.opcode_modifier.vex0f38) | |
2580 | m = 0x2; | |
2581 | else if (i.tm.opcode_modifier.vex0f3a) | |
2582 | m = 0x3; | |
2583 | else | |
2584 | abort (); | |
2585 | ||
2586 | i.vex.length = 3; | |
2587 | i.vex.bytes[0] = 0xc4; | |
2588 | ||
2589 | /* The high 3 bits of the second VEX byte are 1's compliment | |
2590 | of RXB bits from REX. */ | |
2591 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; | |
2592 | ||
2593 | /* Check the REX.W bit. */ | |
2594 | w = (i.rex & REX_W) ? 1 : 0; | |
2595 | if (i.tm.opcode_modifier.vexw0 || i.tm.opcode_modifier.vexw1) | |
2596 | { | |
2597 | if (w) | |
2598 | abort (); | |
2599 | ||
2600 | if (i.tm.opcode_modifier.vexw1) | |
2601 | w = 1; | |
2602 | } | |
2603 | ||
2604 | i.vex.bytes[2] = (w << 7 | |
2605 | | register_specifier << 3 | |
2606 | | vector_length << 2 | |
2607 | | implied_prefix); | |
2608 | } | |
2609 | } | |
2610 | ||
65da13b5 L |
2611 | static void |
2612 | process_immext (void) | |
2613 | { | |
2614 | expressionS *exp; | |
2615 | ||
2616 | if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0) | |
2617 | { | |
1fed0ba1 L |
2618 | /* SSE3 Instructions have the fixed operands with an opcode |
2619 | suffix which is coded in the same place as an 8-bit immediate | |
2620 | field would be. Here we check those operands and remove them | |
2621 | afterwards. */ | |
65da13b5 L |
2622 | unsigned int x; |
2623 | ||
2624 | for (x = 0; x < i.operands; x++) | |
2625 | if (i.op[x].regs->reg_num != x) | |
2626 | as_bad (_("can't use register '%s%s' as operand %d in '%s'."), | |
1fed0ba1 L |
2627 | register_prefix, i.op[x].regs->reg_name, x + 1, |
2628 | i.tm.name); | |
2629 | ||
2630 | i.operands = 0; | |
65da13b5 L |
2631 | } |
2632 | ||
c0f3af97 | 2633 | /* These AMD 3DNow! and SSE2 instructions have an opcode suffix |
65da13b5 L |
2634 | which is coded in the same place as an 8-bit immediate field |
2635 | would be. Here we fake an 8-bit immediate operand from the | |
2636 | opcode suffix stored in tm.extension_opcode. | |
2637 | ||
c0f3af97 L |
2638 | SSE5 and AVX instructions also use this encoding, for some of |
2639 | 3 argument instructions. */ | |
65da13b5 L |
2640 | |
2641 | assert (i.imm_operands == 0 | |
2642 | && (i.operands <= 2 | |
2643 | || (i.tm.cpu_flags.bitfield.cpusse5 | |
c0f3af97 L |
2644 | && i.operands <= 3) |
2645 | || (i.tm.opcode_modifier.vex | |
2646 | && i.operands <= 4))); | |
65da13b5 L |
2647 | |
2648 | exp = &im_expressions[i.imm_operands++]; | |
2649 | i.op[i.operands].imms = exp; | |
2650 | i.types[i.operands] = imm8; | |
2651 | i.operands++; | |
2652 | exp->X_op = O_constant; | |
2653 | exp->X_add_number = i.tm.extension_opcode; | |
2654 | i.tm.extension_opcode = None; | |
2655 | } | |
2656 | ||
252b5132 RH |
2657 | /* This is the guts of the machine-dependent assembler. LINE points to a |
2658 | machine dependent instruction. This function is supposed to emit | |
2659 | the frags/bytes it assembles to. */ | |
2660 | ||
2661 | void | |
65da13b5 | 2662 | md_assemble (char *line) |
252b5132 | 2663 | { |
40fb9820 | 2664 | unsigned int j; |
252b5132 RH |
2665 | char mnemonic[MAX_MNEM_SIZE]; |
2666 | ||
47926f60 | 2667 | /* Initialize globals. */ |
252b5132 RH |
2668 | memset (&i, '\0', sizeof (i)); |
2669 | for (j = 0; j < MAX_OPERANDS; j++) | |
1ae12ab7 | 2670 | i.reloc[j] = NO_RELOC; |
252b5132 RH |
2671 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
2672 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 2673 | save_stack_p = save_stack; |
252b5132 RH |
2674 | |
2675 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
2676 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 2677 | start of a (possibly prefixed) mnemonic. */ |
252b5132 | 2678 | |
29b0f896 AM |
2679 | line = parse_insn (line, mnemonic); |
2680 | if (line == NULL) | |
2681 | return; | |
252b5132 | 2682 | |
29b0f896 AM |
2683 | line = parse_operands (line, mnemonic); |
2684 | if (line == NULL) | |
2685 | return; | |
252b5132 | 2686 | |
29b0f896 AM |
2687 | /* Now we've parsed the mnemonic into a set of templates, and have the |
2688 | operands at hand. */ | |
2689 | ||
2690 | /* All intel opcodes have reversed operands except for "bound" and | |
2691 | "enter". We also don't reverse intersegment "jmp" and "call" | |
2692 | instructions with 2 immediate operands so that the immediate segment | |
050dfa73 | 2693 | precedes the offset, as it does when in AT&T mode. */ |
4d456e3d L |
2694 | if (intel_syntax |
2695 | && i.operands > 1 | |
29b0f896 | 2696 | && (strcmp (mnemonic, "bound") != 0) |
30123838 | 2697 | && (strcmp (mnemonic, "invlpga") != 0) |
40fb9820 L |
2698 | && !(operand_type_check (i.types[0], imm) |
2699 | && operand_type_check (i.types[1], imm))) | |
29b0f896 AM |
2700 | swap_operands (); |
2701 | ||
ec56d5c0 JB |
2702 | /* The order of the immediates should be reversed |
2703 | for 2 immediates extrq and insertq instructions */ | |
2704 | if (i.imm_operands == 2 | |
2705 | && (strcmp (mnemonic, "extrq") == 0 | |
2706 | || strcmp (mnemonic, "insertq") == 0)) | |
2707 | swap_2_operands (0, 1); | |
2708 | ||
29b0f896 AM |
2709 | if (i.imm_operands) |
2710 | optimize_imm (); | |
2711 | ||
b300c311 L |
2712 | /* Don't optimize displacement for movabs since it only takes 64bit |
2713 | displacement. */ | |
2714 | if (i.disp_operands | |
2715 | && (flag_code != CODE_64BIT | |
2716 | || strcmp (mnemonic, "movabs") != 0)) | |
29b0f896 AM |
2717 | optimize_disp (); |
2718 | ||
2719 | /* Next, we find a template that matches the given insn, | |
2720 | making sure the overlap of the given operands types is consistent | |
2721 | with the template operand types. */ | |
252b5132 | 2722 | |
29b0f896 AM |
2723 | if (!match_template ()) |
2724 | return; | |
252b5132 | 2725 | |
daf50ae7 | 2726 | if (sse_check != sse_check_none |
81f8a913 | 2727 | && !i.tm.opcode_modifier.noavx |
daf50ae7 L |
2728 | && (i.tm.cpu_flags.bitfield.cpusse |
2729 | || i.tm.cpu_flags.bitfield.cpusse2 | |
2730 | || i.tm.cpu_flags.bitfield.cpusse3 | |
2731 | || i.tm.cpu_flags.bitfield.cpussse3 | |
2732 | || i.tm.cpu_flags.bitfield.cpusse4_1 | |
2733 | || i.tm.cpu_flags.bitfield.cpusse4_2)) | |
2734 | { | |
2735 | (sse_check == sse_check_warning | |
2736 | ? as_warn | |
2737 | : as_bad) (_("SSE instruction `%s' is used"), i.tm.name); | |
2738 | } | |
2739 | ||
321fd21e L |
2740 | /* Zap movzx and movsx suffix. The suffix has been set from |
2741 | "word ptr" or "byte ptr" on the source operand in Intel syntax | |
2742 | or extracted from mnemonic in AT&T syntax. But we'll use | |
2743 | the destination register to choose the suffix for encoding. */ | |
2744 | if ((i.tm.base_opcode & ~9) == 0x0fb6) | |
cd61ebfe | 2745 | { |
321fd21e L |
2746 | /* In Intel syntax, there must be a suffix. In AT&T syntax, if |
2747 | there is no suffix, the default will be byte extension. */ | |
2748 | if (i.reg_operands != 2 | |
2749 | && !i.suffix | |
2750 | && intel_syntax) | |
2751 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); | |
2752 | ||
2753 | i.suffix = 0; | |
cd61ebfe | 2754 | } |
24eab124 | 2755 | |
40fb9820 | 2756 | if (i.tm.opcode_modifier.fwait) |
29b0f896 AM |
2757 | if (!add_prefix (FWAIT_OPCODE)) |
2758 | return; | |
252b5132 | 2759 | |
29b0f896 | 2760 | /* Check string instruction segment overrides. */ |
40fb9820 | 2761 | if (i.tm.opcode_modifier.isstring && i.mem_operands != 0) |
29b0f896 AM |
2762 | { |
2763 | if (!check_string ()) | |
5dd0794d | 2764 | return; |
29b0f896 | 2765 | } |
5dd0794d | 2766 | |
29b0f896 AM |
2767 | if (!process_suffix ()) |
2768 | return; | |
e413e4e9 | 2769 | |
29b0f896 AM |
2770 | /* Make still unresolved immediate matches conform to size of immediate |
2771 | given in i.suffix. */ | |
2772 | if (!finalize_imm ()) | |
2773 | return; | |
252b5132 | 2774 | |
40fb9820 | 2775 | if (i.types[0].bitfield.imm1) |
29b0f896 | 2776 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 | 2777 | |
40fb9820 | 2778 | for (j = 0; j < 3; j++) |
c6fb90c8 L |
2779 | if (i.types[j].bitfield.inoutportreg |
2780 | || i.types[j].bitfield.shiftcount | |
2781 | || i.types[j].bitfield.acc | |
2782 | || i.types[j].bitfield.floatacc) | |
40fb9820 L |
2783 | i.reg_operands--; |
2784 | ||
c0f3af97 L |
2785 | /* ImmExt should be processed after SSE2AVX. */ |
2786 | if (!i.tm.opcode_modifier.sse2avx | |
2787 | && i.tm.opcode_modifier.immext) | |
65da13b5 | 2788 | process_immext (); |
252b5132 | 2789 | |
29b0f896 AM |
2790 | /* For insns with operands there are more diddles to do to the opcode. */ |
2791 | if (i.operands) | |
2792 | { | |
2793 | if (!process_operands ()) | |
2794 | return; | |
2795 | } | |
40fb9820 | 2796 | else if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 AM |
2797 | { |
2798 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ | |
2799 | as_warn (_("translating to `%sp'"), i.tm.name); | |
2800 | } | |
252b5132 | 2801 | |
c0f3af97 L |
2802 | if (i.tm.opcode_modifier.vex) |
2803 | build_vex_prefix (); | |
2804 | ||
29b0f896 AM |
2805 | /* Handle conversion of 'int $3' --> special int3 insn. */ |
2806 | if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3) | |
2807 | { | |
2808 | i.tm.base_opcode = INT3_OPCODE; | |
2809 | i.imm_operands = 0; | |
2810 | } | |
252b5132 | 2811 | |
40fb9820 L |
2812 | if ((i.tm.opcode_modifier.jump |
2813 | || i.tm.opcode_modifier.jumpbyte | |
2814 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 AM |
2815 | && i.op[0].disps->X_op == O_constant) |
2816 | { | |
2817 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
2818 | the absolute address given by the constant. Since ix86 jumps and | |
2819 | calls are pc relative, we need to generate a reloc. */ | |
2820 | i.op[0].disps->X_add_symbol = &abs_symbol; | |
2821 | i.op[0].disps->X_op = O_symbol; | |
2822 | } | |
252b5132 | 2823 | |
40fb9820 | 2824 | if (i.tm.opcode_modifier.rex64) |
161a04f6 | 2825 | i.rex |= REX_W; |
252b5132 | 2826 | |
29b0f896 AM |
2827 | /* For 8 bit registers we need an empty rex prefix. Also if the |
2828 | instruction already has a prefix, we need to convert old | |
2829 | registers to new ones. */ | |
773f551c | 2830 | |
40fb9820 | 2831 | if ((i.types[0].bitfield.reg8 |
29b0f896 | 2832 | && (i.op[0].regs->reg_flags & RegRex64) != 0) |
40fb9820 | 2833 | || (i.types[1].bitfield.reg8 |
29b0f896 | 2834 | && (i.op[1].regs->reg_flags & RegRex64) != 0) |
40fb9820 L |
2835 | || ((i.types[0].bitfield.reg8 |
2836 | || i.types[1].bitfield.reg8) | |
29b0f896 AM |
2837 | && i.rex != 0)) |
2838 | { | |
2839 | int x; | |
726c5dcd | 2840 | |
29b0f896 AM |
2841 | i.rex |= REX_OPCODE; |
2842 | for (x = 0; x < 2; x++) | |
2843 | { | |
2844 | /* Look for 8 bit operand that uses old registers. */ | |
40fb9820 | 2845 | if (i.types[x].bitfield.reg8 |
29b0f896 | 2846 | && (i.op[x].regs->reg_flags & RegRex64) == 0) |
773f551c | 2847 | { |
29b0f896 AM |
2848 | /* In case it is "hi" register, give up. */ |
2849 | if (i.op[x].regs->reg_num > 3) | |
a540244d | 2850 | as_bad (_("can't encode register '%s%s' in an " |
4eed87de | 2851 | "instruction requiring REX prefix."), |
a540244d | 2852 | register_prefix, i.op[x].regs->reg_name); |
773f551c | 2853 | |
29b0f896 AM |
2854 | /* Otherwise it is equivalent to the extended register. |
2855 | Since the encoding doesn't change this is merely | |
2856 | cosmetic cleanup for debug output. */ | |
2857 | ||
2858 | i.op[x].regs = i.op[x].regs + 8; | |
773f551c | 2859 | } |
29b0f896 AM |
2860 | } |
2861 | } | |
773f551c | 2862 | |
85f10a01 MM |
2863 | /* If the instruction has the DREX attribute (aka SSE5), don't emit a |
2864 | REX prefix. */ | |
2865 | if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc) | |
2866 | { | |
2867 | i.drex.rex = i.rex; | |
2868 | i.rex = 0; | |
2869 | } | |
2870 | else if (i.rex != 0) | |
29b0f896 AM |
2871 | add_prefix (REX_OPCODE | i.rex); |
2872 | ||
2873 | /* We are ready to output the insn. */ | |
2874 | output_insn (); | |
2875 | } | |
2876 | ||
2877 | static char * | |
e3bb37b5 | 2878 | parse_insn (char *line, char *mnemonic) |
29b0f896 AM |
2879 | { |
2880 | char *l = line; | |
2881 | char *token_start = l; | |
2882 | char *mnem_p; | |
5c6af06e JB |
2883 | int supported; |
2884 | const template *t; | |
29b0f896 AM |
2885 | |
2886 | /* Non-zero if we found a prefix only acceptable with string insns. */ | |
2887 | const char *expecting_string_instruction = NULL; | |
45288df1 | 2888 | |
29b0f896 AM |
2889 | while (1) |
2890 | { | |
2891 | mnem_p = mnemonic; | |
2892 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
2893 | { | |
2894 | mnem_p++; | |
2895 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
45288df1 | 2896 | { |
29b0f896 AM |
2897 | as_bad (_("no such instruction: `%s'"), token_start); |
2898 | return NULL; | |
2899 | } | |
2900 | l++; | |
2901 | } | |
2902 | if (!is_space_char (*l) | |
2903 | && *l != END_OF_INSN | |
e44823cf JB |
2904 | && (intel_syntax |
2905 | || (*l != PREFIX_SEPARATOR | |
2906 | && *l != ','))) | |
29b0f896 AM |
2907 | { |
2908 | as_bad (_("invalid character %s in mnemonic"), | |
2909 | output_invalid (*l)); | |
2910 | return NULL; | |
2911 | } | |
2912 | if (token_start == l) | |
2913 | { | |
e44823cf | 2914 | if (!intel_syntax && *l == PREFIX_SEPARATOR) |
29b0f896 AM |
2915 | as_bad (_("expecting prefix; got nothing")); |
2916 | else | |
2917 | as_bad (_("expecting mnemonic; got nothing")); | |
2918 | return NULL; | |
2919 | } | |
45288df1 | 2920 | |
29b0f896 AM |
2921 | /* Look up instruction (or prefix) via hash table. */ |
2922 | current_templates = hash_find (op_hash, mnemonic); | |
47926f60 | 2923 | |
29b0f896 AM |
2924 | if (*l != END_OF_INSN |
2925 | && (!is_space_char (*l) || l[1] != END_OF_INSN) | |
2926 | && current_templates | |
40fb9820 | 2927 | && current_templates->start->opcode_modifier.isprefix) |
29b0f896 | 2928 | { |
c6fb90c8 | 2929 | if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags)) |
2dd88dca JB |
2930 | { |
2931 | as_bad ((flag_code != CODE_64BIT | |
2932 | ? _("`%s' is only supported in 64-bit mode") | |
2933 | : _("`%s' is not supported in 64-bit mode")), | |
2934 | current_templates->start->name); | |
2935 | return NULL; | |
2936 | } | |
29b0f896 AM |
2937 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
2938 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
40fb9820 L |
2939 | if ((current_templates->start->opcode_modifier.size16 |
2940 | || current_templates->start->opcode_modifier.size32) | |
29b0f896 | 2941 | && flag_code != CODE_64BIT |
40fb9820 | 2942 | && (current_templates->start->opcode_modifier.size32 |
29b0f896 AM |
2943 | ^ (flag_code == CODE_16BIT))) |
2944 | { | |
2945 | as_bad (_("redundant %s prefix"), | |
2946 | current_templates->start->name); | |
2947 | return NULL; | |
45288df1 | 2948 | } |
29b0f896 AM |
2949 | /* Add prefix, checking for repeated prefixes. */ |
2950 | switch (add_prefix (current_templates->start->base_opcode)) | |
2951 | { | |
2952 | case 0: | |
2953 | return NULL; | |
2954 | case 2: | |
2955 | expecting_string_instruction = current_templates->start->name; | |
2956 | break; | |
2957 | } | |
2958 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
2959 | token_start = ++l; | |
2960 | } | |
2961 | else | |
2962 | break; | |
2963 | } | |
45288df1 | 2964 | |
29b0f896 AM |
2965 | if (!current_templates) |
2966 | { | |
2967 | /* See if we can get a match by trimming off a suffix. */ | |
2968 | switch (mnem_p[-1]) | |
2969 | { | |
2970 | case WORD_MNEM_SUFFIX: | |
9306ca4a JB |
2971 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) |
2972 | i.suffix = SHORT_MNEM_SUFFIX; | |
2973 | else | |
29b0f896 AM |
2974 | case BYTE_MNEM_SUFFIX: |
2975 | case QWORD_MNEM_SUFFIX: | |
2976 | i.suffix = mnem_p[-1]; | |
2977 | mnem_p[-1] = '\0'; | |
2978 | current_templates = hash_find (op_hash, mnemonic); | |
2979 | break; | |
2980 | case SHORT_MNEM_SUFFIX: | |
2981 | case LONG_MNEM_SUFFIX: | |
2982 | if (!intel_syntax) | |
2983 | { | |
2984 | i.suffix = mnem_p[-1]; | |
2985 | mnem_p[-1] = '\0'; | |
2986 | current_templates = hash_find (op_hash, mnemonic); | |
2987 | } | |
2988 | break; | |
252b5132 | 2989 | |
29b0f896 AM |
2990 | /* Intel Syntax. */ |
2991 | case 'd': | |
2992 | if (intel_syntax) | |
2993 | { | |
9306ca4a | 2994 | if (intel_float_operand (mnemonic) == 1) |
29b0f896 AM |
2995 | i.suffix = SHORT_MNEM_SUFFIX; |
2996 | else | |
2997 | i.suffix = LONG_MNEM_SUFFIX; | |
2998 | mnem_p[-1] = '\0'; | |
2999 | current_templates = hash_find (op_hash, mnemonic); | |
3000 | } | |
3001 | break; | |
3002 | } | |
3003 | if (!current_templates) | |
3004 | { | |
3005 | as_bad (_("no such instruction: `%s'"), token_start); | |
3006 | return NULL; | |
3007 | } | |
3008 | } | |
252b5132 | 3009 | |
40fb9820 L |
3010 | if (current_templates->start->opcode_modifier.jump |
3011 | || current_templates->start->opcode_modifier.jumpbyte) | |
29b0f896 AM |
3012 | { |
3013 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
3014 | predict taken and predict not taken respectively. | |
3015 | I'm not sure that branch hints actually do anything on loop | |
3016 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
3017 | may work in the future and it doesn't hurt to accept them | |
3018 | now. */ | |
3019 | if (l[0] == ',' && l[1] == 'p') | |
3020 | { | |
3021 | if (l[2] == 't') | |
3022 | { | |
3023 | if (!add_prefix (DS_PREFIX_OPCODE)) | |
3024 | return NULL; | |
3025 | l += 3; | |
3026 | } | |
3027 | else if (l[2] == 'n') | |
3028 | { | |
3029 | if (!add_prefix (CS_PREFIX_OPCODE)) | |
3030 | return NULL; | |
3031 | l += 3; | |
3032 | } | |
3033 | } | |
3034 | } | |
3035 | /* Any other comma loses. */ | |
3036 | if (*l == ',') | |
3037 | { | |
3038 | as_bad (_("invalid character %s in mnemonic"), | |
3039 | output_invalid (*l)); | |
3040 | return NULL; | |
3041 | } | |
252b5132 | 3042 | |
29b0f896 | 3043 | /* Check if instruction is supported on specified architecture. */ |
5c6af06e JB |
3044 | supported = 0; |
3045 | for (t = current_templates->start; t < current_templates->end; ++t) | |
3046 | { | |
c0f3af97 L |
3047 | supported |= cpu_flags_match (t); |
3048 | if (supported == CPU_FLAGS_PERFECT_MATCH) | |
3629bb00 | 3049 | goto skip; |
5c6af06e | 3050 | } |
3629bb00 | 3051 | |
c0f3af97 | 3052 | if (!(supported & CPU_FLAGS_64BIT_MATCH)) |
5c6af06e JB |
3053 | { |
3054 | as_bad (flag_code == CODE_64BIT | |
3055 | ? _("`%s' is not supported in 64-bit mode") | |
3056 | : _("`%s' is only supported in 64-bit mode"), | |
3057 | current_templates->start->name); | |
3058 | return NULL; | |
3059 | } | |
c0f3af97 | 3060 | if (supported != CPU_FLAGS_PERFECT_MATCH) |
29b0f896 | 3061 | { |
3629bb00 L |
3062 | as_bad (_("`%s' is not supported on `%s%s'"), |
3063 | current_templates->start->name, cpu_arch_name, | |
3064 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); | |
3065 | return NULL; | |
29b0f896 | 3066 | } |
3629bb00 L |
3067 | |
3068 | skip: | |
3069 | if (!cpu_arch_flags.bitfield.cpui386 | |
40fb9820 | 3070 | && (flag_code != CODE_16BIT)) |
29b0f896 AM |
3071 | { |
3072 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
3073 | } | |
252b5132 | 3074 | |
29b0f896 | 3075 | /* Check for rep/repne without a string instruction. */ |
f41bbced | 3076 | if (expecting_string_instruction) |
29b0f896 | 3077 | { |
f41bbced JB |
3078 | static templates override; |
3079 | ||
3080 | for (t = current_templates->start; t < current_templates->end; ++t) | |
40fb9820 | 3081 | if (t->opcode_modifier.isstring) |
f41bbced JB |
3082 | break; |
3083 | if (t >= current_templates->end) | |
3084 | { | |
3085 | as_bad (_("expecting string instruction after `%s'"), | |
64e74474 | 3086 | expecting_string_instruction); |
f41bbced JB |
3087 | return NULL; |
3088 | } | |
3089 | for (override.start = t; t < current_templates->end; ++t) | |
40fb9820 | 3090 | if (!t->opcode_modifier.isstring) |
f41bbced JB |
3091 | break; |
3092 | override.end = t; | |
3093 | current_templates = &override; | |
29b0f896 | 3094 | } |
252b5132 | 3095 | |
29b0f896 AM |
3096 | return l; |
3097 | } | |
252b5132 | 3098 | |
29b0f896 | 3099 | static char * |
e3bb37b5 | 3100 | parse_operands (char *l, const char *mnemonic) |
29b0f896 AM |
3101 | { |
3102 | char *token_start; | |
3138f287 | 3103 | |
29b0f896 AM |
3104 | /* 1 if operand is pending after ','. */ |
3105 | unsigned int expecting_operand = 0; | |
252b5132 | 3106 | |
29b0f896 AM |
3107 | /* Non-zero if operand parens not balanced. */ |
3108 | unsigned int paren_not_balanced; | |
3109 | ||
3110 | while (*l != END_OF_INSN) | |
3111 | { | |
3112 | /* Skip optional white space before operand. */ | |
3113 | if (is_space_char (*l)) | |
3114 | ++l; | |
3115 | if (!is_operand_char (*l) && *l != END_OF_INSN) | |
3116 | { | |
3117 | as_bad (_("invalid character %s before operand %d"), | |
3118 | output_invalid (*l), | |
3119 | i.operands + 1); | |
3120 | return NULL; | |
3121 | } | |
3122 | token_start = l; /* after white space */ | |
3123 | paren_not_balanced = 0; | |
3124 | while (paren_not_balanced || *l != ',') | |
3125 | { | |
3126 | if (*l == END_OF_INSN) | |
3127 | { | |
3128 | if (paren_not_balanced) | |
3129 | { | |
3130 | if (!intel_syntax) | |
3131 | as_bad (_("unbalanced parenthesis in operand %d."), | |
3132 | i.operands + 1); | |
3133 | else | |
3134 | as_bad (_("unbalanced brackets in operand %d."), | |
3135 | i.operands + 1); | |
3136 | return NULL; | |
3137 | } | |
3138 | else | |
3139 | break; /* we are done */ | |
3140 | } | |
3141 | else if (!is_operand_char (*l) && !is_space_char (*l)) | |
3142 | { | |
3143 | as_bad (_("invalid character %s in operand %d"), | |
3144 | output_invalid (*l), | |
3145 | i.operands + 1); | |
3146 | return NULL; | |
3147 | } | |
3148 | if (!intel_syntax) | |
3149 | { | |
3150 | if (*l == '(') | |
3151 | ++paren_not_balanced; | |
3152 | if (*l == ')') | |
3153 | --paren_not_balanced; | |
3154 | } | |
3155 | else | |
3156 | { | |
3157 | if (*l == '[') | |
3158 | ++paren_not_balanced; | |
3159 | if (*l == ']') | |
3160 | --paren_not_balanced; | |
3161 | } | |
3162 | l++; | |
3163 | } | |
3164 | if (l != token_start) | |
3165 | { /* Yes, we've read in another operand. */ | |
3166 | unsigned int operand_ok; | |
3167 | this_operand = i.operands++; | |
7d5e4556 | 3168 | i.types[this_operand].bitfield.unspecified = 1; |
29b0f896 AM |
3169 | if (i.operands > MAX_OPERANDS) |
3170 | { | |
3171 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
3172 | MAX_OPERANDS); | |
3173 | return NULL; | |
3174 | } | |
3175 | /* Now parse operand adding info to 'i' as we go along. */ | |
3176 | END_STRING_AND_SAVE (l); | |
3177 | ||
3178 | if (intel_syntax) | |
3179 | operand_ok = | |
3180 | i386_intel_operand (token_start, | |
3181 | intel_float_operand (mnemonic)); | |
3182 | else | |
a7619375 | 3183 | operand_ok = i386_att_operand (token_start); |
29b0f896 AM |
3184 | |
3185 | RESTORE_END_STRING (l); | |
3186 | if (!operand_ok) | |
3187 | return NULL; | |
3188 | } | |
3189 | else | |
3190 | { | |
3191 | if (expecting_operand) | |
3192 | { | |
3193 | expecting_operand_after_comma: | |
3194 | as_bad (_("expecting operand after ','; got nothing")); | |
3195 | return NULL; | |
3196 | } | |
3197 | if (*l == ',') | |
3198 | { | |
3199 | as_bad (_("expecting operand before ','; got nothing")); | |
3200 | return NULL; | |
3201 | } | |
3202 | } | |
7f3f1ea2 | 3203 | |
29b0f896 AM |
3204 | /* Now *l must be either ',' or END_OF_INSN. */ |
3205 | if (*l == ',') | |
3206 | { | |
3207 | if (*++l == END_OF_INSN) | |
3208 | { | |
3209 | /* Just skip it, if it's \n complain. */ | |
3210 | goto expecting_operand_after_comma; | |
3211 | } | |
3212 | expecting_operand = 1; | |
3213 | } | |
3214 | } | |
3215 | return l; | |
3216 | } | |
7f3f1ea2 | 3217 | |
050dfa73 | 3218 | static void |
4d456e3d | 3219 | swap_2_operands (int xchg1, int xchg2) |
050dfa73 MM |
3220 | { |
3221 | union i386_op temp_op; | |
40fb9820 | 3222 | i386_operand_type temp_type; |
050dfa73 | 3223 | enum bfd_reloc_code_real temp_reloc; |
4eed87de | 3224 | |
050dfa73 MM |
3225 | temp_type = i.types[xchg2]; |
3226 | i.types[xchg2] = i.types[xchg1]; | |
3227 | i.types[xchg1] = temp_type; | |
3228 | temp_op = i.op[xchg2]; | |
3229 | i.op[xchg2] = i.op[xchg1]; | |
3230 | i.op[xchg1] = temp_op; | |
3231 | temp_reloc = i.reloc[xchg2]; | |
3232 | i.reloc[xchg2] = i.reloc[xchg1]; | |
3233 | i.reloc[xchg1] = temp_reloc; | |
3234 | } | |
3235 | ||
29b0f896 | 3236 | static void |
e3bb37b5 | 3237 | swap_operands (void) |
29b0f896 | 3238 | { |
b7c61d9a | 3239 | switch (i.operands) |
050dfa73 | 3240 | { |
c0f3af97 | 3241 | case 5: |
b7c61d9a | 3242 | case 4: |
4d456e3d | 3243 | swap_2_operands (1, i.operands - 2); |
b7c61d9a L |
3244 | case 3: |
3245 | case 2: | |
4d456e3d | 3246 | swap_2_operands (0, i.operands - 1); |
b7c61d9a L |
3247 | break; |
3248 | default: | |
3249 | abort (); | |
29b0f896 | 3250 | } |
29b0f896 AM |
3251 | |
3252 | if (i.mem_operands == 2) | |
3253 | { | |
3254 | const seg_entry *temp_seg; | |
3255 | temp_seg = i.seg[0]; | |
3256 | i.seg[0] = i.seg[1]; | |
3257 | i.seg[1] = temp_seg; | |
3258 | } | |
3259 | } | |
252b5132 | 3260 | |
29b0f896 AM |
3261 | /* Try to ensure constant immediates are represented in the smallest |
3262 | opcode possible. */ | |
3263 | static void | |
e3bb37b5 | 3264 | optimize_imm (void) |
29b0f896 AM |
3265 | { |
3266 | char guess_suffix = 0; | |
3267 | int op; | |
252b5132 | 3268 | |
29b0f896 AM |
3269 | if (i.suffix) |
3270 | guess_suffix = i.suffix; | |
3271 | else if (i.reg_operands) | |
3272 | { | |
3273 | /* Figure out a suffix from the last register operand specified. | |
3274 | We can't do this properly yet, ie. excluding InOutPortReg, | |
3275 | but the following works for instructions with immediates. | |
3276 | In any case, we can't set i.suffix yet. */ | |
3277 | for (op = i.operands; --op >= 0;) | |
40fb9820 L |
3278 | if (i.types[op].bitfield.reg8) |
3279 | { | |
3280 | guess_suffix = BYTE_MNEM_SUFFIX; | |
3281 | break; | |
3282 | } | |
3283 | else if (i.types[op].bitfield.reg16) | |
252b5132 | 3284 | { |
40fb9820 L |
3285 | guess_suffix = WORD_MNEM_SUFFIX; |
3286 | break; | |
3287 | } | |
3288 | else if (i.types[op].bitfield.reg32) | |
3289 | { | |
3290 | guess_suffix = LONG_MNEM_SUFFIX; | |
3291 | break; | |
3292 | } | |
3293 | else if (i.types[op].bitfield.reg64) | |
3294 | { | |
3295 | guess_suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 | 3296 | break; |
252b5132 | 3297 | } |
29b0f896 AM |
3298 | } |
3299 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) | |
3300 | guess_suffix = WORD_MNEM_SUFFIX; | |
3301 | ||
3302 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 3303 | if (operand_type_check (i.types[op], imm)) |
29b0f896 AM |
3304 | { |
3305 | switch (i.op[op].imms->X_op) | |
252b5132 | 3306 | { |
29b0f896 AM |
3307 | case O_constant: |
3308 | /* If a suffix is given, this operand may be shortened. */ | |
3309 | switch (guess_suffix) | |
252b5132 | 3310 | { |
29b0f896 | 3311 | case LONG_MNEM_SUFFIX: |
40fb9820 L |
3312 | i.types[op].bitfield.imm32 = 1; |
3313 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
3314 | break; |
3315 | case WORD_MNEM_SUFFIX: | |
40fb9820 L |
3316 | i.types[op].bitfield.imm16 = 1; |
3317 | i.types[op].bitfield.imm32 = 1; | |
3318 | i.types[op].bitfield.imm32s = 1; | |
3319 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
3320 | break; |
3321 | case BYTE_MNEM_SUFFIX: | |
40fb9820 L |
3322 | i.types[op].bitfield.imm8 = 1; |
3323 | i.types[op].bitfield.imm8s = 1; | |
3324 | i.types[op].bitfield.imm16 = 1; | |
3325 | i.types[op].bitfield.imm32 = 1; | |
3326 | i.types[op].bitfield.imm32s = 1; | |
3327 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 | 3328 | break; |
252b5132 | 3329 | } |
252b5132 | 3330 | |
29b0f896 AM |
3331 | /* If this operand is at most 16 bits, convert it |
3332 | to a signed 16 bit number before trying to see | |
3333 | whether it will fit in an even smaller size. | |
3334 | This allows a 16-bit operand such as $0xffe0 to | |
3335 | be recognised as within Imm8S range. */ | |
40fb9820 | 3336 | if ((i.types[op].bitfield.imm16) |
29b0f896 | 3337 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) |
252b5132 | 3338 | { |
29b0f896 AM |
3339 | i.op[op].imms->X_add_number = |
3340 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); | |
3341 | } | |
40fb9820 | 3342 | if ((i.types[op].bitfield.imm32) |
29b0f896 AM |
3343 | && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) |
3344 | == 0)) | |
3345 | { | |
3346 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number | |
3347 | ^ ((offsetT) 1 << 31)) | |
3348 | - ((offsetT) 1 << 31)); | |
3349 | } | |
40fb9820 | 3350 | i.types[op] |
c6fb90c8 L |
3351 | = operand_type_or (i.types[op], |
3352 | smallest_imm_type (i.op[op].imms->X_add_number)); | |
252b5132 | 3353 | |
29b0f896 AM |
3354 | /* We must avoid matching of Imm32 templates when 64bit |
3355 | only immediate is available. */ | |
3356 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
40fb9820 | 3357 | i.types[op].bitfield.imm32 = 0; |
29b0f896 | 3358 | break; |
252b5132 | 3359 | |
29b0f896 AM |
3360 | case O_absent: |
3361 | case O_register: | |
3362 | abort (); | |
3363 | ||
3364 | /* Symbols and expressions. */ | |
3365 | default: | |
9cd96992 JB |
3366 | /* Convert symbolic operand to proper sizes for matching, but don't |
3367 | prevent matching a set of insns that only supports sizes other | |
3368 | than those matching the insn suffix. */ | |
3369 | { | |
40fb9820 | 3370 | i386_operand_type mask, allowed; |
9cd96992 JB |
3371 | const template *t; |
3372 | ||
0dfbf9d7 L |
3373 | operand_type_set (&mask, 0); |
3374 | operand_type_set (&allowed, 0); | |
40fb9820 | 3375 | |
4eed87de AM |
3376 | for (t = current_templates->start; |
3377 | t < current_templates->end; | |
3378 | ++t) | |
c6fb90c8 L |
3379 | allowed = operand_type_or (allowed, |
3380 | t->operand_types[op]); | |
9cd96992 JB |
3381 | switch (guess_suffix) |
3382 | { | |
3383 | case QWORD_MNEM_SUFFIX: | |
40fb9820 L |
3384 | mask.bitfield.imm64 = 1; |
3385 | mask.bitfield.imm32s = 1; | |
9cd96992 JB |
3386 | break; |
3387 | case LONG_MNEM_SUFFIX: | |
40fb9820 | 3388 | mask.bitfield.imm32 = 1; |
9cd96992 JB |
3389 | break; |
3390 | case WORD_MNEM_SUFFIX: | |
40fb9820 | 3391 | mask.bitfield.imm16 = 1; |
9cd96992 JB |
3392 | break; |
3393 | case BYTE_MNEM_SUFFIX: | |
40fb9820 | 3394 | mask.bitfield.imm8 = 1; |
9cd96992 JB |
3395 | break; |
3396 | default: | |
9cd96992 JB |
3397 | break; |
3398 | } | |
c6fb90c8 | 3399 | allowed = operand_type_and (mask, allowed); |
0dfbf9d7 | 3400 | if (!operand_type_all_zero (&allowed)) |
c6fb90c8 | 3401 | i.types[op] = operand_type_and (i.types[op], mask); |
9cd96992 | 3402 | } |
29b0f896 | 3403 | break; |
252b5132 | 3404 | } |
29b0f896 AM |
3405 | } |
3406 | } | |
47926f60 | 3407 | |
29b0f896 AM |
3408 | /* Try to use the smallest displacement type too. */ |
3409 | static void | |
e3bb37b5 | 3410 | optimize_disp (void) |
29b0f896 AM |
3411 | { |
3412 | int op; | |
3e73aa7c | 3413 | |
29b0f896 | 3414 | for (op = i.operands; --op >= 0;) |
40fb9820 | 3415 | if (operand_type_check (i.types[op], disp)) |
252b5132 | 3416 | { |
b300c311 | 3417 | if (i.op[op].disps->X_op == O_constant) |
252b5132 | 3418 | { |
b300c311 | 3419 | offsetT disp = i.op[op].disps->X_add_number; |
29b0f896 | 3420 | |
40fb9820 | 3421 | if (i.types[op].bitfield.disp16 |
b300c311 L |
3422 | && (disp & ~(offsetT) 0xffff) == 0) |
3423 | { | |
3424 | /* If this operand is at most 16 bits, convert | |
3425 | to a signed 16 bit number and don't use 64bit | |
3426 | displacement. */ | |
3427 | disp = (((disp & 0xffff) ^ 0x8000) - 0x8000); | |
40fb9820 | 3428 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 3429 | } |
40fb9820 | 3430 | if (i.types[op].bitfield.disp32 |
b300c311 L |
3431 | && (disp & ~(((offsetT) 2 << 31) - 1)) == 0) |
3432 | { | |
3433 | /* If this operand is at most 32 bits, convert | |
3434 | to a signed 32 bit number and don't use 64bit | |
3435 | displacement. */ | |
3436 | disp &= (((offsetT) 2 << 31) - 1); | |
3437 | disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
40fb9820 | 3438 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 3439 | } |
40fb9820 | 3440 | if (!disp && i.types[op].bitfield.baseindex) |
b300c311 | 3441 | { |
40fb9820 L |
3442 | i.types[op].bitfield.disp8 = 0; |
3443 | i.types[op].bitfield.disp16 = 0; | |
3444 | i.types[op].bitfield.disp32 = 0; | |
3445 | i.types[op].bitfield.disp32s = 0; | |
3446 | i.types[op].bitfield.disp64 = 0; | |
b300c311 L |
3447 | i.op[op].disps = 0; |
3448 | i.disp_operands--; | |
3449 | } | |
3450 | else if (flag_code == CODE_64BIT) | |
3451 | { | |
3452 | if (fits_in_signed_long (disp)) | |
28a9d8f5 | 3453 | { |
40fb9820 L |
3454 | i.types[op].bitfield.disp64 = 0; |
3455 | i.types[op].bitfield.disp32s = 1; | |
28a9d8f5 | 3456 | } |
b300c311 | 3457 | if (fits_in_unsigned_long (disp)) |
40fb9820 | 3458 | i.types[op].bitfield.disp32 = 1; |
b300c311 | 3459 | } |
40fb9820 L |
3460 | if ((i.types[op].bitfield.disp32 |
3461 | || i.types[op].bitfield.disp32s | |
3462 | || i.types[op].bitfield.disp16) | |
b300c311 | 3463 | && fits_in_signed_byte (disp)) |
40fb9820 | 3464 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 3465 | } |
67a4f2b7 AO |
3466 | else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
3467 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) | |
3468 | { | |
3469 | fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, | |
3470 | i.op[op].disps, 0, i.reloc[op]); | |
40fb9820 L |
3471 | i.types[op].bitfield.disp8 = 0; |
3472 | i.types[op].bitfield.disp16 = 0; | |
3473 | i.types[op].bitfield.disp32 = 0; | |
3474 | i.types[op].bitfield.disp32s = 0; | |
3475 | i.types[op].bitfield.disp64 = 0; | |
67a4f2b7 AO |
3476 | } |
3477 | else | |
b300c311 | 3478 | /* We only support 64bit displacement on constants. */ |
40fb9820 | 3479 | i.types[op].bitfield.disp64 = 0; |
252b5132 | 3480 | } |
29b0f896 AM |
3481 | } |
3482 | ||
c0f3af97 L |
3483 | /* Check if operands are valid for the instrucrtion. Update VEX |
3484 | operand types. */ | |
3485 | ||
3486 | static int | |
3487 | VEX_check_operands (const template *t) | |
3488 | { | |
3489 | if (!t->opcode_modifier.vex) | |
3490 | return 0; | |
3491 | ||
3492 | /* Only check VEX_Imm4, which must be the first operand. */ | |
3493 | if (t->operand_types[0].bitfield.vex_imm4) | |
3494 | { | |
3495 | if (i.op[0].imms->X_op != O_constant | |
3496 | || !fits_in_imm4 (i.op[0].imms->X_add_number)) | |
3497 | return 1; | |
3498 | ||
3499 | /* Turn off Imm8 so that update_imm won't complain. */ | |
3500 | i.types[0] = vex_imm4; | |
3501 | } | |
3502 | ||
3503 | return 0; | |
3504 | } | |
3505 | ||
29b0f896 | 3506 | static int |
e3bb37b5 | 3507 | match_template (void) |
29b0f896 AM |
3508 | { |
3509 | /* Points to template once we've found it. */ | |
3510 | const template *t; | |
40fb9820 | 3511 | i386_operand_type overlap0, overlap1, overlap2, overlap3; |
c0f3af97 | 3512 | i386_operand_type overlap4; |
29b0f896 | 3513 | unsigned int found_reverse_match; |
40fb9820 L |
3514 | i386_opcode_modifier suffix_check; |
3515 | i386_operand_type operand_types [MAX_OPERANDS]; | |
539e75ad | 3516 | int addr_prefix_disp; |
a5c311ca | 3517 | unsigned int j; |
3629bb00 | 3518 | unsigned int found_cpu_match; |
45664ddb | 3519 | unsigned int check_register; |
29b0f896 | 3520 | |
c0f3af97 L |
3521 | #if MAX_OPERANDS != 5 |
3522 | # error "MAX_OPERANDS must be 5." | |
f48ff2ae L |
3523 | #endif |
3524 | ||
29b0f896 | 3525 | found_reverse_match = 0; |
539e75ad | 3526 | addr_prefix_disp = -1; |
40fb9820 L |
3527 | |
3528 | memset (&suffix_check, 0, sizeof (suffix_check)); | |
3529 | if (i.suffix == BYTE_MNEM_SUFFIX) | |
3530 | suffix_check.no_bsuf = 1; | |
3531 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
3532 | suffix_check.no_wsuf = 1; | |
3533 | else if (i.suffix == SHORT_MNEM_SUFFIX) | |
3534 | suffix_check.no_ssuf = 1; | |
3535 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
3536 | suffix_check.no_lsuf = 1; | |
3537 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
3538 | suffix_check.no_qsuf = 1; | |
3539 | else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX) | |
7ce189b3 | 3540 | suffix_check.no_ldsuf = 1; |
29b0f896 | 3541 | |
45aa61fe | 3542 | for (t = current_templates->start; t < current_templates->end; t++) |
29b0f896 | 3543 | { |
539e75ad L |
3544 | addr_prefix_disp = -1; |
3545 | ||
29b0f896 AM |
3546 | /* Must have right number of operands. */ |
3547 | if (i.operands != t->operands) | |
3548 | continue; | |
3549 | ||
50aecf8c | 3550 | /* Check processor support. */ |
c0f3af97 L |
3551 | found_cpu_match = (cpu_flags_match (t) |
3552 | == CPU_FLAGS_PERFECT_MATCH); | |
50aecf8c L |
3553 | if (!found_cpu_match) |
3554 | continue; | |
3555 | ||
e1d4d893 L |
3556 | /* Check old gcc support. */ |
3557 | if (!old_gcc && t->opcode_modifier.oldgcc) | |
3558 | continue; | |
3559 | ||
3560 | /* Check AT&T mnemonic. */ | |
3561 | if (intel_mnemonic && t->opcode_modifier.attmnemonic) | |
1efbbeb4 L |
3562 | continue; |
3563 | ||
5c07affc L |
3564 | /* Check AT&T syntax Intel syntax. */ |
3565 | if ((intel_syntax && t->opcode_modifier.attsyntax) | |
3566 | || (!intel_syntax && t->opcode_modifier.intelsyntax)) | |
1efbbeb4 L |
3567 | continue; |
3568 | ||
20592a94 | 3569 | /* Check the suffix, except for some instructions in intel mode. */ |
567e4e96 L |
3570 | if ((!intel_syntax || !t->opcode_modifier.ignoresize) |
3571 | && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf) | |
3572 | || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf) | |
3573 | || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf) | |
3574 | || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf) | |
3575 | || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf) | |
3576 | || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf))) | |
29b0f896 AM |
3577 | continue; |
3578 | ||
5c07affc | 3579 | if (!operand_size_match (t)) |
7d5e4556 | 3580 | continue; |
539e75ad | 3581 | |
5c07affc L |
3582 | for (j = 0; j < MAX_OPERANDS; j++) |
3583 | operand_types[j] = t->operand_types[j]; | |
3584 | ||
45aa61fe AM |
3585 | /* In general, don't allow 64-bit operands in 32-bit mode. */ |
3586 | if (i.suffix == QWORD_MNEM_SUFFIX | |
3587 | && flag_code != CODE_64BIT | |
3588 | && (intel_syntax | |
40fb9820 | 3589 | ? (!t->opcode_modifier.ignoresize |
45aa61fe AM |
3590 | && !intel_float_operand (t->name)) |
3591 | : intel_float_operand (t->name) != 2) | |
40fb9820 | 3592 | && ((!operand_types[0].bitfield.regmmx |
c0f3af97 L |
3593 | && !operand_types[0].bitfield.regxmm |
3594 | && !operand_types[0].bitfield.regymm) | |
40fb9820 | 3595 | || (!operand_types[t->operands > 1].bitfield.regmmx |
c0f3af97 L |
3596 | && !!operand_types[t->operands > 1].bitfield.regxmm |
3597 | && !!operand_types[t->operands > 1].bitfield.regymm)) | |
45aa61fe AM |
3598 | && (t->base_opcode != 0x0fc7 |
3599 | || t->extension_opcode != 1 /* cmpxchg8b */)) | |
3600 | continue; | |
3601 | ||
192dc9c6 JB |
3602 | /* In general, don't allow 32-bit operands on pre-386. */ |
3603 | else if (i.suffix == LONG_MNEM_SUFFIX | |
3604 | && !cpu_arch_flags.bitfield.cpui386 | |
3605 | && (intel_syntax | |
3606 | ? (!t->opcode_modifier.ignoresize | |
3607 | && !intel_float_operand (t->name)) | |
3608 | : intel_float_operand (t->name) != 2) | |
3609 | && ((!operand_types[0].bitfield.regmmx | |
3610 | && !operand_types[0].bitfield.regxmm) | |
3611 | || (!operand_types[t->operands > 1].bitfield.regmmx | |
3612 | && !!operand_types[t->operands > 1].bitfield.regxmm))) | |
3613 | continue; | |
3614 | ||
29b0f896 | 3615 | /* Do not verify operands when there are none. */ |
50aecf8c | 3616 | else |
29b0f896 | 3617 | { |
c6fb90c8 | 3618 | if (!t->operands) |
2dbab7d5 L |
3619 | /* We've found a match; break out of loop. */ |
3620 | break; | |
29b0f896 | 3621 | } |
252b5132 | 3622 | |
539e75ad L |
3623 | /* Address size prefix will turn Disp64/Disp32/Disp16 operand |
3624 | into Disp32/Disp16/Disp32 operand. */ | |
3625 | if (i.prefix[ADDR_PREFIX] != 0) | |
3626 | { | |
40fb9820 | 3627 | /* There should be only one Disp operand. */ |
539e75ad L |
3628 | switch (flag_code) |
3629 | { | |
3630 | case CODE_16BIT: | |
40fb9820 L |
3631 | for (j = 0; j < MAX_OPERANDS; j++) |
3632 | { | |
3633 | if (operand_types[j].bitfield.disp16) | |
3634 | { | |
3635 | addr_prefix_disp = j; | |
3636 | operand_types[j].bitfield.disp32 = 1; | |
3637 | operand_types[j].bitfield.disp16 = 0; | |
3638 | break; | |
3639 | } | |
3640 | } | |
539e75ad L |
3641 | break; |
3642 | case CODE_32BIT: | |
40fb9820 L |
3643 | for (j = 0; j < MAX_OPERANDS; j++) |
3644 | { | |
3645 | if (operand_types[j].bitfield.disp32) | |
3646 | { | |
3647 | addr_prefix_disp = j; | |
3648 | operand_types[j].bitfield.disp32 = 0; | |
3649 | operand_types[j].bitfield.disp16 = 1; | |
3650 | break; | |
3651 | } | |
3652 | } | |
539e75ad L |
3653 | break; |
3654 | case CODE_64BIT: | |
40fb9820 L |
3655 | for (j = 0; j < MAX_OPERANDS; j++) |
3656 | { | |
3657 | if (operand_types[j].bitfield.disp64) | |
3658 | { | |
3659 | addr_prefix_disp = j; | |
3660 | operand_types[j].bitfield.disp64 = 0; | |
3661 | operand_types[j].bitfield.disp32 = 1; | |
3662 | break; | |
3663 | } | |
3664 | } | |
539e75ad L |
3665 | break; |
3666 | } | |
539e75ad L |
3667 | } |
3668 | ||
45664ddb L |
3669 | /* We check register size only if size of operands can be |
3670 | encoded the canonical way. */ | |
3671 | check_register = t->opcode_modifier.w; | |
c6fb90c8 | 3672 | overlap0 = operand_type_and (i.types[0], operand_types[0]); |
29b0f896 AM |
3673 | switch (t->operands) |
3674 | { | |
3675 | case 1: | |
40fb9820 | 3676 | if (!operand_type_match (overlap0, i.types[0])) |
29b0f896 AM |
3677 | continue; |
3678 | break; | |
3679 | case 2: | |
8b38ad71 L |
3680 | /* xchg %eax, %eax is a special case. It is an aliase for nop |
3681 | only in 32bit mode and we can use opcode 0x90. In 64bit | |
3682 | mode, we can't use 0x90 for xchg %eax, %eax since it should | |
3683 | zero-extend %eax to %rax. */ | |
3684 | if (flag_code == CODE_64BIT | |
3685 | && t->base_opcode == 0x90 | |
0dfbf9d7 L |
3686 | && operand_type_equal (&i.types [0], &acc32) |
3687 | && operand_type_equal (&i.types [1], &acc32)) | |
8b38ad71 | 3688 | continue; |
29b0f896 | 3689 | case 3: |
f48ff2ae | 3690 | case 4: |
c0f3af97 | 3691 | case 5: |
c6fb90c8 | 3692 | overlap1 = operand_type_and (i.types[1], operand_types[1]); |
40fb9820 L |
3693 | if (!operand_type_match (overlap0, i.types[0]) |
3694 | || !operand_type_match (overlap1, i.types[1]) | |
45664ddb L |
3695 | || (check_register |
3696 | && !operand_type_register_match (overlap0, i.types[0], | |
40fb9820 L |
3697 | operand_types[0], |
3698 | overlap1, i.types[1], | |
3699 | operand_types[1]))) | |
29b0f896 AM |
3700 | { |
3701 | /* Check if other direction is valid ... */ | |
40fb9820 | 3702 | if (!t->opcode_modifier.d && !t->opcode_modifier.floatd) |
29b0f896 AM |
3703 | continue; |
3704 | ||
3705 | /* Try reversing direction of operands. */ | |
c6fb90c8 L |
3706 | overlap0 = operand_type_and (i.types[0], operand_types[1]); |
3707 | overlap1 = operand_type_and (i.types[1], operand_types[0]); | |
40fb9820 L |
3708 | if (!operand_type_match (overlap0, i.types[0]) |
3709 | || !operand_type_match (overlap1, i.types[1]) | |
45664ddb L |
3710 | || (check_register |
3711 | && !operand_type_register_match (overlap0, | |
3712 | i.types[0], | |
3713 | operand_types[1], | |
3714 | overlap1, | |
3715 | i.types[1], | |
3716 | operand_types[0]))) | |
29b0f896 AM |
3717 | { |
3718 | /* Does not match either direction. */ | |
3719 | continue; | |
3720 | } | |
3721 | /* found_reverse_match holds which of D or FloatDR | |
3722 | we've found. */ | |
40fb9820 | 3723 | if (t->opcode_modifier.d) |
8a2ed489 | 3724 | found_reverse_match = Opcode_D; |
40fb9820 | 3725 | else if (t->opcode_modifier.floatd) |
8a2ed489 L |
3726 | found_reverse_match = Opcode_FloatD; |
3727 | else | |
3728 | found_reverse_match = 0; | |
40fb9820 | 3729 | if (t->opcode_modifier.floatr) |
8a2ed489 | 3730 | found_reverse_match |= Opcode_FloatR; |
29b0f896 | 3731 | } |
f48ff2ae | 3732 | else |
29b0f896 | 3733 | { |
f48ff2ae | 3734 | /* Found a forward 2 operand match here. */ |
d1cbb4db L |
3735 | switch (t->operands) |
3736 | { | |
c0f3af97 L |
3737 | case 5: |
3738 | overlap4 = operand_type_and (i.types[4], | |
3739 | operand_types[4]); | |
d1cbb4db | 3740 | case 4: |
c6fb90c8 L |
3741 | overlap3 = operand_type_and (i.types[3], |
3742 | operand_types[3]); | |
d1cbb4db | 3743 | case 3: |
c6fb90c8 L |
3744 | overlap2 = operand_type_and (i.types[2], |
3745 | operand_types[2]); | |
d1cbb4db L |
3746 | break; |
3747 | } | |
29b0f896 | 3748 | |
f48ff2ae L |
3749 | switch (t->operands) |
3750 | { | |
c0f3af97 L |
3751 | case 5: |
3752 | if (!operand_type_match (overlap4, i.types[4]) | |
3753 | || !operand_type_register_match (overlap3, | |
3754 | i.types[3], | |
3755 | operand_types[3], | |
3756 | overlap4, | |
3757 | i.types[4], | |
3758 | operand_types[4])) | |
3759 | continue; | |
f48ff2ae | 3760 | case 4: |
40fb9820 | 3761 | if (!operand_type_match (overlap3, i.types[3]) |
45664ddb L |
3762 | || (check_register |
3763 | && !operand_type_register_match (overlap2, | |
3764 | i.types[2], | |
3765 | operand_types[2], | |
3766 | overlap3, | |
3767 | i.types[3], | |
3768 | operand_types[3]))) | |
f48ff2ae L |
3769 | continue; |
3770 | case 3: | |
3771 | /* Here we make use of the fact that there are no | |
3772 | reverse match 3 operand instructions, and all 3 | |
3773 | operand instructions only need to be checked for | |
3774 | register consistency between operands 2 and 3. */ | |
40fb9820 | 3775 | if (!operand_type_match (overlap2, i.types[2]) |
45664ddb L |
3776 | || (check_register |
3777 | && !operand_type_register_match (overlap1, | |
3778 | i.types[1], | |
3779 | operand_types[1], | |
3780 | overlap2, | |
3781 | i.types[2], | |
3782 | operand_types[2]))) | |
f48ff2ae L |
3783 | continue; |
3784 | break; | |
3785 | } | |
29b0f896 | 3786 | } |
f48ff2ae | 3787 | /* Found either forward/reverse 2, 3 or 4 operand match here: |
29b0f896 AM |
3788 | slip through to break. */ |
3789 | } | |
3629bb00 | 3790 | if (!found_cpu_match) |
29b0f896 AM |
3791 | { |
3792 | found_reverse_match = 0; | |
3793 | continue; | |
3794 | } | |
c0f3af97 L |
3795 | |
3796 | /* Check if VEX operands are valid. */ | |
3797 | if (VEX_check_operands (t)) | |
3798 | continue; | |
3799 | ||
29b0f896 AM |
3800 | /* We've found a match; break out of loop. */ |
3801 | break; | |
3802 | } | |
3803 | ||
3804 | if (t == current_templates->end) | |
3805 | { | |
3806 | /* We found no match. */ | |
95f283e8 L |
3807 | if (intel_syntax) |
3808 | as_bad (_("ambiguous operand size or operands invalid for `%s'"), | |
3809 | current_templates->start->name); | |
3810 | else | |
3811 | as_bad (_("suffix or operands invalid for `%s'"), | |
3812 | current_templates->start->name); | |
29b0f896 AM |
3813 | return 0; |
3814 | } | |
252b5132 | 3815 | |
29b0f896 AM |
3816 | if (!quiet_warnings) |
3817 | { | |
3818 | if (!intel_syntax | |
40fb9820 L |
3819 | && (i.types[0].bitfield.jumpabsolute |
3820 | != operand_types[0].bitfield.jumpabsolute)) | |
29b0f896 AM |
3821 | { |
3822 | as_warn (_("indirect %s without `*'"), t->name); | |
3823 | } | |
3824 | ||
40fb9820 L |
3825 | if (t->opcode_modifier.isprefix |
3826 | && t->opcode_modifier.ignoresize) | |
29b0f896 AM |
3827 | { |
3828 | /* Warn them that a data or address size prefix doesn't | |
3829 | affect assembly of the next line of code. */ | |
3830 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
3831 | } | |
3832 | } | |
3833 | ||
3834 | /* Copy the template we found. */ | |
3835 | i.tm = *t; | |
539e75ad L |
3836 | |
3837 | if (addr_prefix_disp != -1) | |
3838 | i.tm.operand_types[addr_prefix_disp] | |
3839 | = operand_types[addr_prefix_disp]; | |
3840 | ||
29b0f896 AM |
3841 | if (found_reverse_match) |
3842 | { | |
3843 | /* If we found a reverse match we must alter the opcode | |
3844 | direction bit. found_reverse_match holds bits to change | |
3845 | (different for int & float insns). */ | |
3846 | ||
3847 | i.tm.base_opcode ^= found_reverse_match; | |
3848 | ||
539e75ad L |
3849 | i.tm.operand_types[0] = operand_types[1]; |
3850 | i.tm.operand_types[1] = operand_types[0]; | |
29b0f896 AM |
3851 | } |
3852 | ||
3853 | return 1; | |
3854 | } | |
3855 | ||
3856 | static int | |
e3bb37b5 | 3857 | check_string (void) |
29b0f896 | 3858 | { |
40fb9820 L |
3859 | int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1; |
3860 | if (i.tm.operand_types[mem_op].bitfield.esseg) | |
29b0f896 AM |
3861 | { |
3862 | if (i.seg[0] != NULL && i.seg[0] != &es) | |
3863 | { | |
3864 | as_bad (_("`%s' operand %d must use `%%es' segment"), | |
3865 | i.tm.name, | |
3866 | mem_op + 1); | |
3867 | return 0; | |
3868 | } | |
3869 | /* There's only ever one segment override allowed per instruction. | |
3870 | This instruction possibly has a legal segment override on the | |
3871 | second operand, so copy the segment to where non-string | |
3872 | instructions store it, allowing common code. */ | |
3873 | i.seg[0] = i.seg[1]; | |
3874 | } | |
40fb9820 | 3875 | else if (i.tm.operand_types[mem_op + 1].bitfield.esseg) |
29b0f896 AM |
3876 | { |
3877 | if (i.seg[1] != NULL && i.seg[1] != &es) | |
3878 | { | |
3879 | as_bad (_("`%s' operand %d must use `%%es' segment"), | |
3880 | i.tm.name, | |
3881 | mem_op + 2); | |
3882 | return 0; | |
3883 | } | |
3884 | } | |
3885 | return 1; | |
3886 | } | |
3887 | ||
3888 | static int | |
543613e9 | 3889 | process_suffix (void) |
29b0f896 AM |
3890 | { |
3891 | /* If matched instruction specifies an explicit instruction mnemonic | |
3892 | suffix, use it. */ | |
40fb9820 L |
3893 | if (i.tm.opcode_modifier.size16) |
3894 | i.suffix = WORD_MNEM_SUFFIX; | |
3895 | else if (i.tm.opcode_modifier.size32) | |
3896 | i.suffix = LONG_MNEM_SUFFIX; | |
3897 | else if (i.tm.opcode_modifier.size64) | |
3898 | i.suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 AM |
3899 | else if (i.reg_operands) |
3900 | { | |
3901 | /* If there's no instruction mnemonic suffix we try to invent one | |
3902 | based on register operands. */ | |
3903 | if (!i.suffix) | |
3904 | { | |
3905 | /* We take i.suffix from the last register operand specified, | |
3906 | Destination register type is more significant than source | |
381d071f L |
3907 | register type. crc32 in SSE4.2 prefers source register |
3908 | type. */ | |
3909 | if (i.tm.base_opcode == 0xf20f38f1) | |
3910 | { | |
40fb9820 L |
3911 | if (i.types[0].bitfield.reg16) |
3912 | i.suffix = WORD_MNEM_SUFFIX; | |
3913 | else if (i.types[0].bitfield.reg32) | |
3914 | i.suffix = LONG_MNEM_SUFFIX; | |
3915 | else if (i.types[0].bitfield.reg64) | |
3916 | i.suffix = QWORD_MNEM_SUFFIX; | |
381d071f | 3917 | } |
9344ff29 | 3918 | else if (i.tm.base_opcode == 0xf20f38f0) |
20592a94 | 3919 | { |
40fb9820 | 3920 | if (i.types[0].bitfield.reg8) |
20592a94 L |
3921 | i.suffix = BYTE_MNEM_SUFFIX; |
3922 | } | |
381d071f L |
3923 | |
3924 | if (!i.suffix) | |
3925 | { | |
3926 | int op; | |
3927 | ||
20592a94 L |
3928 | if (i.tm.base_opcode == 0xf20f38f1 |
3929 | || i.tm.base_opcode == 0xf20f38f0) | |
3930 | { | |
3931 | /* We have to know the operand size for crc32. */ | |
3932 | as_bad (_("ambiguous memory operand size for `%s`"), | |
3933 | i.tm.name); | |
3934 | return 0; | |
3935 | } | |
3936 | ||
381d071f | 3937 | for (op = i.operands; --op >= 0;) |
40fb9820 | 3938 | if (!i.tm.operand_types[op].bitfield.inoutportreg) |
381d071f | 3939 | { |
40fb9820 L |
3940 | if (i.types[op].bitfield.reg8) |
3941 | { | |
3942 | i.suffix = BYTE_MNEM_SUFFIX; | |
3943 | break; | |
3944 | } | |
3945 | else if (i.types[op].bitfield.reg16) | |
3946 | { | |
3947 | i.suffix = WORD_MNEM_SUFFIX; | |
3948 | break; | |
3949 | } | |
3950 | else if (i.types[op].bitfield.reg32) | |
3951 | { | |
3952 | i.suffix = LONG_MNEM_SUFFIX; | |
3953 | break; | |
3954 | } | |
3955 | else if (i.types[op].bitfield.reg64) | |
3956 | { | |
3957 | i.suffix = QWORD_MNEM_SUFFIX; | |
3958 | break; | |
3959 | } | |
381d071f L |
3960 | } |
3961 | } | |
29b0f896 AM |
3962 | } |
3963 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
3964 | { | |
3965 | if (!check_byte_reg ()) | |
3966 | return 0; | |
3967 | } | |
3968 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
3969 | { | |
3970 | if (!check_long_reg ()) | |
3971 | return 0; | |
3972 | } | |
3973 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
3974 | { | |
955e1e6a L |
3975 | if (intel_syntax |
3976 | && i.tm.opcode_modifier.ignoresize | |
3977 | && i.tm.opcode_modifier.no_qsuf) | |
3978 | i.suffix = 0; | |
3979 | else if (!check_qword_reg ()) | |
29b0f896 AM |
3980 | return 0; |
3981 | } | |
3982 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
3983 | { | |
3984 | if (!check_word_reg ()) | |
3985 | return 0; | |
3986 | } | |
c0f3af97 L |
3987 | else if (i.suffix == XMMWORD_MNEM_SUFFIX |
3988 | || i.suffix == YMMWORD_MNEM_SUFFIX) | |
582d5edd | 3989 | { |
c0f3af97 | 3990 | /* Skip if the instruction has x/y suffix. match_template |
582d5edd L |
3991 | should check if it is a valid suffix. */ |
3992 | } | |
40fb9820 | 3993 | else if (intel_syntax && i.tm.opcode_modifier.ignoresize) |
29b0f896 AM |
3994 | /* Do nothing if the instruction is going to ignore the prefix. */ |
3995 | ; | |
3996 | else | |
3997 | abort (); | |
3998 | } | |
40fb9820 | 3999 | else if (i.tm.opcode_modifier.defaultsize |
9306ca4a JB |
4000 | && !i.suffix |
4001 | /* exclude fldenv/frstor/fsave/fstenv */ | |
40fb9820 | 4002 | && i.tm.opcode_modifier.no_ssuf) |
29b0f896 AM |
4003 | { |
4004 | i.suffix = stackop_size; | |
4005 | } | |
9306ca4a JB |
4006 | else if (intel_syntax |
4007 | && !i.suffix | |
40fb9820 L |
4008 | && (i.tm.operand_types[0].bitfield.jumpabsolute |
4009 | || i.tm.opcode_modifier.jumpbyte | |
4010 | || i.tm.opcode_modifier.jumpintersegment | |
64e74474 AM |
4011 | || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */ |
4012 | && i.tm.extension_opcode <= 3))) | |
9306ca4a JB |
4013 | { |
4014 | switch (flag_code) | |
4015 | { | |
4016 | case CODE_64BIT: | |
40fb9820 | 4017 | if (!i.tm.opcode_modifier.no_qsuf) |
9306ca4a JB |
4018 | { |
4019 | i.suffix = QWORD_MNEM_SUFFIX; | |
4020 | break; | |
4021 | } | |
4022 | case CODE_32BIT: | |
40fb9820 | 4023 | if (!i.tm.opcode_modifier.no_lsuf) |
9306ca4a JB |
4024 | i.suffix = LONG_MNEM_SUFFIX; |
4025 | break; | |
4026 | case CODE_16BIT: | |
40fb9820 | 4027 | if (!i.tm.opcode_modifier.no_wsuf) |
9306ca4a JB |
4028 | i.suffix = WORD_MNEM_SUFFIX; |
4029 | break; | |
4030 | } | |
4031 | } | |
252b5132 | 4032 | |
9306ca4a | 4033 | if (!i.suffix) |
29b0f896 | 4034 | { |
9306ca4a JB |
4035 | if (!intel_syntax) |
4036 | { | |
40fb9820 | 4037 | if (i.tm.opcode_modifier.w) |
9306ca4a | 4038 | { |
4eed87de AM |
4039 | as_bad (_("no instruction mnemonic suffix given and " |
4040 | "no register operands; can't size instruction")); | |
9306ca4a JB |
4041 | return 0; |
4042 | } | |
4043 | } | |
4044 | else | |
4045 | { | |
40fb9820 L |
4046 | unsigned int suffixes; |
4047 | ||
4048 | suffixes = !i.tm.opcode_modifier.no_bsuf; | |
4049 | if (!i.tm.opcode_modifier.no_wsuf) | |
4050 | suffixes |= 1 << 1; | |
4051 | if (!i.tm.opcode_modifier.no_lsuf) | |
4052 | suffixes |= 1 << 2; | |
fc4adea1 | 4053 | if (!i.tm.opcode_modifier.no_ldsuf) |
40fb9820 L |
4054 | suffixes |= 1 << 3; |
4055 | if (!i.tm.opcode_modifier.no_ssuf) | |
4056 | suffixes |= 1 << 4; | |
4057 | if (!i.tm.opcode_modifier.no_qsuf) | |
4058 | suffixes |= 1 << 5; | |
4059 | ||
4060 | /* There are more than suffix matches. */ | |
4061 | if (i.tm.opcode_modifier.w | |
9306ca4a | 4062 | || ((suffixes & (suffixes - 1)) |
40fb9820 L |
4063 | && !i.tm.opcode_modifier.defaultsize |
4064 | && !i.tm.opcode_modifier.ignoresize)) | |
9306ca4a JB |
4065 | { |
4066 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); | |
4067 | return 0; | |
4068 | } | |
4069 | } | |
29b0f896 | 4070 | } |
252b5132 | 4071 | |
9306ca4a JB |
4072 | /* Change the opcode based on the operand size given by i.suffix; |
4073 | We don't need to change things for byte insns. */ | |
4074 | ||
582d5edd L |
4075 | if (i.suffix |
4076 | && i.suffix != BYTE_MNEM_SUFFIX | |
c0f3af97 L |
4077 | && i.suffix != XMMWORD_MNEM_SUFFIX |
4078 | && i.suffix != YMMWORD_MNEM_SUFFIX) | |
29b0f896 AM |
4079 | { |
4080 | /* It's not a byte, select word/dword operation. */ | |
40fb9820 | 4081 | if (i.tm.opcode_modifier.w) |
29b0f896 | 4082 | { |
40fb9820 | 4083 | if (i.tm.opcode_modifier.shortform) |
29b0f896 AM |
4084 | i.tm.base_opcode |= 8; |
4085 | else | |
4086 | i.tm.base_opcode |= 1; | |
4087 | } | |
0f3f3d8b | 4088 | |
29b0f896 AM |
4089 | /* Now select between word & dword operations via the operand |
4090 | size prefix, except for instructions that will ignore this | |
4091 | prefix anyway. */ | |
ca61edf2 | 4092 | if (i.tm.opcode_modifier.addrprefixop0) |
cb712a9e | 4093 | { |
ca61edf2 L |
4094 | /* The address size override prefix changes the size of the |
4095 | first operand. */ | |
40fb9820 L |
4096 | if ((flag_code == CODE_32BIT |
4097 | && i.op->regs[0].reg_type.bitfield.reg16) | |
4098 | || (flag_code != CODE_32BIT | |
4099 | && i.op->regs[0].reg_type.bitfield.reg32)) | |
cb712a9e L |
4100 | if (!add_prefix (ADDR_PREFIX_OPCODE)) |
4101 | return 0; | |
4102 | } | |
4103 | else if (i.suffix != QWORD_MNEM_SUFFIX | |
4104 | && i.suffix != LONG_DOUBLE_MNEM_SUFFIX | |
40fb9820 L |
4105 | && !i.tm.opcode_modifier.ignoresize |
4106 | && !i.tm.opcode_modifier.floatmf | |
cb712a9e L |
4107 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) |
4108 | || (flag_code == CODE_64BIT | |
40fb9820 | 4109 | && i.tm.opcode_modifier.jumpbyte))) |
24eab124 AM |
4110 | { |
4111 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
543613e9 | 4112 | |
40fb9820 | 4113 | if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */ |
29b0f896 | 4114 | prefix = ADDR_PREFIX_OPCODE; |
252b5132 | 4115 | |
29b0f896 AM |
4116 | if (!add_prefix (prefix)) |
4117 | return 0; | |
24eab124 | 4118 | } |
252b5132 | 4119 | |
29b0f896 AM |
4120 | /* Set mode64 for an operand. */ |
4121 | if (i.suffix == QWORD_MNEM_SUFFIX | |
9146926a | 4122 | && flag_code == CODE_64BIT |
40fb9820 | 4123 | && !i.tm.opcode_modifier.norex64) |
46e883c5 L |
4124 | { |
4125 | /* Special case for xchg %rax,%rax. It is NOP and doesn't | |
d9a5e5e5 L |
4126 | need rex64. cmpxchg8b is also a special case. */ |
4127 | if (! (i.operands == 2 | |
4128 | && i.tm.base_opcode == 0x90 | |
4129 | && i.tm.extension_opcode == None | |
0dfbf9d7 L |
4130 | && operand_type_equal (&i.types [0], &acc64) |
4131 | && operand_type_equal (&i.types [1], &acc64)) | |
d9a5e5e5 L |
4132 | && ! (i.operands == 1 |
4133 | && i.tm.base_opcode == 0xfc7 | |
4134 | && i.tm.extension_opcode == 1 | |
40fb9820 L |
4135 | && !operand_type_check (i.types [0], reg) |
4136 | && operand_type_check (i.types [0], anymem))) | |
f6bee062 | 4137 | i.rex |= REX_W; |
46e883c5 | 4138 | } |
3e73aa7c | 4139 | |
29b0f896 AM |
4140 | /* Size floating point instruction. */ |
4141 | if (i.suffix == LONG_MNEM_SUFFIX) | |
40fb9820 | 4142 | if (i.tm.opcode_modifier.floatmf) |
543613e9 | 4143 | i.tm.base_opcode ^= 4; |
29b0f896 | 4144 | } |
7ecd2f8b | 4145 | |
29b0f896 AM |
4146 | return 1; |
4147 | } | |
3e73aa7c | 4148 | |
29b0f896 | 4149 | static int |
543613e9 | 4150 | check_byte_reg (void) |
29b0f896 AM |
4151 | { |
4152 | int op; | |
543613e9 | 4153 | |
29b0f896 AM |
4154 | for (op = i.operands; --op >= 0;) |
4155 | { | |
4156 | /* If this is an eight bit register, it's OK. If it's the 16 or | |
4157 | 32 bit version of an eight bit register, we will just use the | |
4158 | low portion, and that's OK too. */ | |
40fb9820 | 4159 | if (i.types[op].bitfield.reg8) |
29b0f896 AM |
4160 | continue; |
4161 | ||
ca61edf2 L |
4162 | /* Don't generate this warning if not needed. */ |
4163 | if (intel_syntax && i.tm.opcode_modifier.byteokintel) | |
29b0f896 AM |
4164 | continue; |
4165 | ||
9344ff29 L |
4166 | /* crc32 doesn't generate this warning. */ |
4167 | if (i.tm.base_opcode == 0xf20f38f0) | |
4168 | continue; | |
4169 | ||
40fb9820 L |
4170 | if ((i.types[op].bitfield.reg16 |
4171 | || i.types[op].bitfield.reg32 | |
4172 | || i.types[op].bitfield.reg64) | |
4173 | && i.op[op].regs->reg_num < 4) | |
29b0f896 AM |
4174 | { |
4175 | /* Prohibit these changes in the 64bit mode, since the | |
4176 | lowering is more complicated. */ | |
4177 | if (flag_code == CODE_64BIT | |
40fb9820 | 4178 | && !i.tm.operand_types[op].bitfield.inoutportreg) |
29b0f896 | 4179 | { |
2ca3ace5 L |
4180 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), |
4181 | register_prefix, i.op[op].regs->reg_name, | |
29b0f896 AM |
4182 | i.suffix); |
4183 | return 0; | |
4184 | } | |
4185 | #if REGISTER_WARNINGS | |
4186 | if (!quiet_warnings | |
40fb9820 | 4187 | && !i.tm.operand_types[op].bitfield.inoutportreg) |
a540244d L |
4188 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
4189 | register_prefix, | |
40fb9820 | 4190 | (i.op[op].regs + (i.types[op].bitfield.reg16 |
29b0f896 AM |
4191 | ? REGNAM_AL - REGNAM_AX |
4192 | : REGNAM_AL - REGNAM_EAX))->reg_name, | |
a540244d | 4193 | register_prefix, |
29b0f896 AM |
4194 | i.op[op].regs->reg_name, |
4195 | i.suffix); | |
4196 | #endif | |
4197 | continue; | |
4198 | } | |
4199 | /* Any other register is bad. */ | |
40fb9820 L |
4200 | if (i.types[op].bitfield.reg16 |
4201 | || i.types[op].bitfield.reg32 | |
4202 | || i.types[op].bitfield.reg64 | |
4203 | || i.types[op].bitfield.regmmx | |
4204 | || i.types[op].bitfield.regxmm | |
c0f3af97 | 4205 | || i.types[op].bitfield.regymm |
40fb9820 L |
4206 | || i.types[op].bitfield.sreg2 |
4207 | || i.types[op].bitfield.sreg3 | |
4208 | || i.types[op].bitfield.control | |
4209 | || i.types[op].bitfield.debug | |
4210 | || i.types[op].bitfield.test | |
4211 | || i.types[op].bitfield.floatreg | |
4212 | || i.types[op].bitfield.floatacc) | |
29b0f896 | 4213 | { |
a540244d L |
4214 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
4215 | register_prefix, | |
29b0f896 AM |
4216 | i.op[op].regs->reg_name, |
4217 | i.tm.name, | |
4218 | i.suffix); | |
4219 | return 0; | |
4220 | } | |
4221 | } | |
4222 | return 1; | |
4223 | } | |
4224 | ||
4225 | static int | |
e3bb37b5 | 4226 | check_long_reg (void) |
29b0f896 AM |
4227 | { |
4228 | int op; | |
4229 | ||
4230 | for (op = i.operands; --op >= 0;) | |
4231 | /* Reject eight bit registers, except where the template requires | |
4232 | them. (eg. movzb) */ | |
40fb9820 L |
4233 | if (i.types[op].bitfield.reg8 |
4234 | && (i.tm.operand_types[op].bitfield.reg16 | |
4235 | || i.tm.operand_types[op].bitfield.reg32 | |
4236 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 | 4237 | { |
a540244d L |
4238 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
4239 | register_prefix, | |
29b0f896 AM |
4240 | i.op[op].regs->reg_name, |
4241 | i.tm.name, | |
4242 | i.suffix); | |
4243 | return 0; | |
4244 | } | |
4245 | /* Warn if the e prefix on a general reg is missing. */ | |
4246 | else if ((!quiet_warnings || flag_code == CODE_64BIT) | |
40fb9820 L |
4247 | && i.types[op].bitfield.reg16 |
4248 | && (i.tm.operand_types[op].bitfield.reg32 | |
4249 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 AM |
4250 | { |
4251 | /* Prohibit these changes in the 64bit mode, since the | |
4252 | lowering is more complicated. */ | |
4253 | if (flag_code == CODE_64BIT) | |
252b5132 | 4254 | { |
2ca3ace5 L |
4255 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), |
4256 | register_prefix, i.op[op].regs->reg_name, | |
29b0f896 AM |
4257 | i.suffix); |
4258 | return 0; | |
252b5132 | 4259 | } |
29b0f896 AM |
4260 | #if REGISTER_WARNINGS |
4261 | else | |
a540244d L |
4262 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
4263 | register_prefix, | |
29b0f896 | 4264 | (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name, |
a540244d | 4265 | register_prefix, |
29b0f896 AM |
4266 | i.op[op].regs->reg_name, |
4267 | i.suffix); | |
4268 | #endif | |
252b5132 | 4269 | } |
29b0f896 | 4270 | /* Warn if the r prefix on a general reg is missing. */ |
40fb9820 L |
4271 | else if (i.types[op].bitfield.reg64 |
4272 | && (i.tm.operand_types[op].bitfield.reg32 | |
4273 | || i.tm.operand_types[op].bitfield.acc)) | |
252b5132 | 4274 | { |
34828aad | 4275 | if (intel_syntax |
ca61edf2 | 4276 | && i.tm.opcode_modifier.toqword |
40fb9820 | 4277 | && !i.types[0].bitfield.regxmm) |
34828aad | 4278 | { |
ca61edf2 | 4279 | /* Convert to QWORD. We want REX byte. */ |
34828aad L |
4280 | i.suffix = QWORD_MNEM_SUFFIX; |
4281 | } | |
4282 | else | |
4283 | { | |
4284 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), | |
4285 | register_prefix, i.op[op].regs->reg_name, | |
4286 | i.suffix); | |
4287 | return 0; | |
4288 | } | |
29b0f896 AM |
4289 | } |
4290 | return 1; | |
4291 | } | |
252b5132 | 4292 | |
29b0f896 | 4293 | static int |
e3bb37b5 | 4294 | check_qword_reg (void) |
29b0f896 AM |
4295 | { |
4296 | int op; | |
252b5132 | 4297 | |
29b0f896 AM |
4298 | for (op = i.operands; --op >= 0; ) |
4299 | /* Reject eight bit registers, except where the template requires | |
4300 | them. (eg. movzb) */ | |
40fb9820 L |
4301 | if (i.types[op].bitfield.reg8 |
4302 | && (i.tm.operand_types[op].bitfield.reg16 | |
4303 | || i.tm.operand_types[op].bitfield.reg32 | |
4304 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 | 4305 | { |
a540244d L |
4306 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
4307 | register_prefix, | |
29b0f896 AM |
4308 | i.op[op].regs->reg_name, |
4309 | i.tm.name, | |
4310 | i.suffix); | |
4311 | return 0; | |
4312 | } | |
4313 | /* Warn if the e prefix on a general reg is missing. */ | |
40fb9820 L |
4314 | else if ((i.types[op].bitfield.reg16 |
4315 | || i.types[op].bitfield.reg32) | |
4316 | && (i.tm.operand_types[op].bitfield.reg32 | |
4317 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 AM |
4318 | { |
4319 | /* Prohibit these changes in the 64bit mode, since the | |
4320 | lowering is more complicated. */ | |
34828aad | 4321 | if (intel_syntax |
ca61edf2 | 4322 | && i.tm.opcode_modifier.todword |
40fb9820 | 4323 | && !i.types[0].bitfield.regxmm) |
34828aad | 4324 | { |
ca61edf2 | 4325 | /* Convert to DWORD. We don't want REX byte. */ |
34828aad L |
4326 | i.suffix = LONG_MNEM_SUFFIX; |
4327 | } | |
4328 | else | |
4329 | { | |
4330 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), | |
4331 | register_prefix, i.op[op].regs->reg_name, | |
4332 | i.suffix); | |
4333 | return 0; | |
4334 | } | |
252b5132 | 4335 | } |
29b0f896 AM |
4336 | return 1; |
4337 | } | |
252b5132 | 4338 | |
29b0f896 | 4339 | static int |
e3bb37b5 | 4340 | check_word_reg (void) |
29b0f896 AM |
4341 | { |
4342 | int op; | |
4343 | for (op = i.operands; --op >= 0;) | |
4344 | /* Reject eight bit registers, except where the template requires | |
4345 | them. (eg. movzb) */ | |
40fb9820 L |
4346 | if (i.types[op].bitfield.reg8 |
4347 | && (i.tm.operand_types[op].bitfield.reg16 | |
4348 | || i.tm.operand_types[op].bitfield.reg32 | |
4349 | || i.tm.operand_types[op].bitfield.acc)) | |
29b0f896 | 4350 | { |
a540244d L |
4351 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
4352 | register_prefix, | |
29b0f896 AM |
4353 | i.op[op].regs->reg_name, |
4354 | i.tm.name, | |
4355 | i.suffix); | |
4356 | return 0; | |
4357 | } | |
4358 | /* Warn if the e prefix on a general reg is present. */ | |
4359 | else if ((!quiet_warnings || flag_code == CODE_64BIT) | |
40fb9820 L |
4360 | && i.types[op].bitfield.reg32 |
4361 | && (i.tm.operand_types[op].bitfield.reg16 | |
4362 | || i.tm.operand_types[op].bitfield.acc)) | |
252b5132 | 4363 | { |
29b0f896 AM |
4364 | /* Prohibit these changes in the 64bit mode, since the |
4365 | lowering is more complicated. */ | |
4366 | if (flag_code == CODE_64BIT) | |
252b5132 | 4367 | { |
2ca3ace5 L |
4368 | as_bad (_("Incorrect register `%s%s' used with `%c' suffix"), |
4369 | register_prefix, i.op[op].regs->reg_name, | |
29b0f896 AM |
4370 | i.suffix); |
4371 | return 0; | |
252b5132 | 4372 | } |
29b0f896 AM |
4373 | else |
4374 | #if REGISTER_WARNINGS | |
a540244d L |
4375 | as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"), |
4376 | register_prefix, | |
29b0f896 | 4377 | (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name, |
a540244d | 4378 | register_prefix, |
29b0f896 AM |
4379 | i.op[op].regs->reg_name, |
4380 | i.suffix); | |
4381 | #endif | |
4382 | } | |
4383 | return 1; | |
4384 | } | |
252b5132 | 4385 | |
29b0f896 | 4386 | static int |
40fb9820 | 4387 | update_imm (unsigned int j) |
29b0f896 | 4388 | { |
40fb9820 L |
4389 | i386_operand_type overlap; |
4390 | ||
c6fb90c8 | 4391 | overlap = operand_type_and (i.types[j], i.tm.operand_types[j]); |
40fb9820 L |
4392 | if ((overlap.bitfield.imm8 |
4393 | || overlap.bitfield.imm8s | |
4394 | || overlap.bitfield.imm16 | |
4395 | || overlap.bitfield.imm32 | |
4396 | || overlap.bitfield.imm32s | |
4397 | || overlap.bitfield.imm64) | |
0dfbf9d7 L |
4398 | && !operand_type_equal (&overlap, &imm8) |
4399 | && !operand_type_equal (&overlap, &imm8s) | |
4400 | && !operand_type_equal (&overlap, &imm16) | |
4401 | && !operand_type_equal (&overlap, &imm32) | |
4402 | && !operand_type_equal (&overlap, &imm32s) | |
4403 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 AM |
4404 | { |
4405 | if (i.suffix) | |
4406 | { | |
40fb9820 L |
4407 | i386_operand_type temp; |
4408 | ||
0dfbf9d7 | 4409 | operand_type_set (&temp, 0); |
40fb9820 L |
4410 | if (i.suffix == BYTE_MNEM_SUFFIX) |
4411 | { | |
4412 | temp.bitfield.imm8 = overlap.bitfield.imm8; | |
4413 | temp.bitfield.imm8s = overlap.bitfield.imm8s; | |
4414 | } | |
4415 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
4416 | temp.bitfield.imm16 = overlap.bitfield.imm16; | |
4417 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
4418 | { | |
4419 | temp.bitfield.imm64 = overlap.bitfield.imm64; | |
4420 | temp.bitfield.imm32s = overlap.bitfield.imm32s; | |
4421 | } | |
4422 | else | |
4423 | temp.bitfield.imm32 = overlap.bitfield.imm32; | |
4424 | overlap = temp; | |
29b0f896 | 4425 | } |
0dfbf9d7 L |
4426 | else if (operand_type_equal (&overlap, &imm16_32_32s) |
4427 | || operand_type_equal (&overlap, &imm16_32) | |
4428 | || operand_type_equal (&overlap, &imm16_32s)) | |
29b0f896 | 4429 | { |
40fb9820 | 4430 | if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
65da13b5 | 4431 | overlap = imm16; |
40fb9820 | 4432 | else |
65da13b5 | 4433 | overlap = imm32s; |
29b0f896 | 4434 | } |
0dfbf9d7 L |
4435 | if (!operand_type_equal (&overlap, &imm8) |
4436 | && !operand_type_equal (&overlap, &imm8s) | |
4437 | && !operand_type_equal (&overlap, &imm16) | |
4438 | && !operand_type_equal (&overlap, &imm32) | |
4439 | && !operand_type_equal (&overlap, &imm32s) | |
4440 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 | 4441 | { |
4eed87de AM |
4442 | as_bad (_("no instruction mnemonic suffix given; " |
4443 | "can't determine immediate size")); | |
29b0f896 AM |
4444 | return 0; |
4445 | } | |
4446 | } | |
40fb9820 | 4447 | i.types[j] = overlap; |
29b0f896 | 4448 | |
40fb9820 L |
4449 | return 1; |
4450 | } | |
4451 | ||
4452 | static int | |
4453 | finalize_imm (void) | |
4454 | { | |
4455 | unsigned int j; | |
29b0f896 | 4456 | |
40fb9820 L |
4457 | for (j = 0; j < 2; j++) |
4458 | if (update_imm (j) == 0) | |
4459 | return 0; | |
4460 | ||
c6fb90c8 | 4461 | i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]); |
40fb9820 | 4462 | assert (operand_type_check (i.types[2], imm) == 0); |
29b0f896 AM |
4463 | |
4464 | return 1; | |
4465 | } | |
4466 | ||
85f10a01 MM |
4467 | static void |
4468 | process_drex (void) | |
4469 | { | |
5dd15031 JJ |
4470 | i.drex.modrm_reg = 0; |
4471 | i.drex.modrm_regmem = 0; | |
85f10a01 MM |
4472 | |
4473 | /* SSE5 4 operand instructions must have the destination the same as | |
4474 | one of the inputs. Figure out the destination register and cache | |
4475 | it away in the drex field, and remember which fields to use for | |
4476 | the modrm byte. */ | |
4477 | if (i.tm.opcode_modifier.drex | |
4478 | && i.tm.opcode_modifier.drexv | |
4479 | && i.operands == 4) | |
4480 | { | |
4481 | i.tm.extension_opcode = None; | |
4482 | ||
4483 | /* Case 1: 4 operand insn, dest = src1, src3 = register. */ | |
4484 | if (i.types[0].bitfield.regxmm != 0 | |
4485 | && i.types[1].bitfield.regxmm != 0 | |
4486 | && i.types[2].bitfield.regxmm != 0 | |
4487 | && i.types[3].bitfield.regxmm != 0 | |
4488 | && i.op[0].regs->reg_num == i.op[3].regs->reg_num | |
4489 | && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags) | |
4490 | { | |
4491 | /* Clear the arguments that are stored in drex. */ | |
0dfbf9d7 L |
4492 | operand_type_set (&i.types[0], 0); |
4493 | operand_type_set (&i.types[3], 0); | |
85f10a01 MM |
4494 | i.reg_operands -= 2; |
4495 | ||
4496 | /* There are two different ways to encode a 4 operand | |
4497 | instruction with all registers that uses OC1 set to | |
4498 | 0 or 1. Favor setting OC1 to 0 since this mimics the | |
4499 | actions of other SSE5 assemblers. Use modrm encoding 2 | |
4500 | for register/register. Include the high order bit that | |
4501 | is normally stored in the REX byte in the register | |
4502 | field. */ | |
4503 | i.tm.extension_opcode = DREX_X1_XMEM_X2_X1; | |
4504 | i.drex.modrm_reg = 2; | |
4505 | i.drex.modrm_regmem = 1; | |
4506 | i.drex.reg = (i.op[3].regs->reg_num | |
4507 | + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); | |
4508 | } | |
4509 | ||
4510 | /* Case 2: 4 operand insn, dest = src1, src3 = memory. */ | |
4511 | else if (i.types[0].bitfield.regxmm != 0 | |
4512 | && i.types[1].bitfield.regxmm != 0 | |
4513 | && (i.types[2].bitfield.regxmm | |
4514 | || operand_type_check (i.types[2], anymem)) | |
4515 | && i.types[3].bitfield.regxmm != 0 | |
4516 | && i.op[0].regs->reg_num == i.op[3].regs->reg_num | |
4517 | && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags) | |
4518 | { | |
4519 | /* clear the arguments that are stored in drex */ | |
0dfbf9d7 L |
4520 | operand_type_set (&i.types[0], 0); |
4521 | operand_type_set (&i.types[3], 0); | |
85f10a01 MM |
4522 | i.reg_operands -= 2; |
4523 | ||
4524 | /* Specify the modrm encoding for memory addressing. Include | |
4525 | the high order bit that is normally stored in the REX byte | |
4526 | in the register field. */ | |
4527 | i.tm.extension_opcode = DREX_X1_X2_XMEM_X1; | |
4528 | i.drex.modrm_reg = 1; | |
4529 | i.drex.modrm_regmem = 2; | |
4530 | i.drex.reg = (i.op[3].regs->reg_num | |
4531 | + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); | |
4532 | } | |
4533 | ||
4534 | /* Case 3: 4 operand insn, dest = src1, src2 = memory. */ | |
4535 | else if (i.types[0].bitfield.regxmm != 0 | |
4536 | && operand_type_check (i.types[1], anymem) != 0 | |
4537 | && i.types[2].bitfield.regxmm != 0 | |
4538 | && i.types[3].bitfield.regxmm != 0 | |
4539 | && i.op[0].regs->reg_num == i.op[3].regs->reg_num | |
4540 | && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags) | |
4541 | { | |
4542 | /* Clear the arguments that are stored in drex. */ | |
0dfbf9d7 L |
4543 | operand_type_set (&i.types[0], 0); |
4544 | operand_type_set (&i.types[3], 0); | |
85f10a01 MM |
4545 | i.reg_operands -= 2; |
4546 | ||
4547 | /* Specify the modrm encoding for memory addressing. Include | |
4548 | the high order bit that is normally stored in the REX byte | |
4549 | in the register field. */ | |
4550 | i.tm.extension_opcode = DREX_X1_XMEM_X2_X1; | |
4551 | i.drex.modrm_reg = 2; | |
4552 | i.drex.modrm_regmem = 1; | |
4553 | i.drex.reg = (i.op[3].regs->reg_num | |
4554 | + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); | |
4555 | } | |
4556 | ||
4557 | /* Case 4: 4 operand insn, dest = src3, src2 = register. */ | |
4558 | else if (i.types[0].bitfield.regxmm != 0 | |
4559 | && i.types[1].bitfield.regxmm != 0 | |
4560 | && i.types[2].bitfield.regxmm != 0 | |
4561 | && i.types[3].bitfield.regxmm != 0 | |
4562 | && i.op[2].regs->reg_num == i.op[3].regs->reg_num | |
4563 | && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags) | |
4564 | { | |
4565 | /* clear the arguments that are stored in drex */ | |
0dfbf9d7 L |
4566 | operand_type_set (&i.types[2], 0); |
4567 | operand_type_set (&i.types[3], 0); | |
85f10a01 MM |
4568 | i.reg_operands -= 2; |
4569 | ||
4570 | /* There are two different ways to encode a 4 operand | |
4571 | instruction with all registers that uses OC1 set to | |
4572 | 0 or 1. Favor setting OC1 to 0 since this mimics the | |
4573 | actions of other SSE5 assemblers. Use modrm encoding | |
4574 | 2 for register/register. Include the high order bit that | |
4575 | is normally stored in the REX byte in the register | |
4576 | field. */ | |
4577 | i.tm.extension_opcode = DREX_XMEM_X1_X2_X2; | |
4578 | i.drex.modrm_reg = 1; | |
4579 | i.drex.modrm_regmem = 0; | |
4580 | ||
4581 | /* Remember the register, including the upper bits */ | |
4582 | i.drex.reg = (i.op[3].regs->reg_num | |
4583 | + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); | |
4584 | } | |
4585 | ||
4586 | /* Case 5: 4 operand insn, dest = src3, src2 = memory. */ | |
4587 | else if (i.types[0].bitfield.regxmm != 0 | |
4588 | && (i.types[1].bitfield.regxmm | |
4589 | || operand_type_check (i.types[1], anymem)) | |
4590 | && i.types[2].bitfield.regxmm != 0 | |
4591 | && i.types[3].bitfield.regxmm != 0 | |
4592 | && i.op[2].regs->reg_num == i.op[3].regs->reg_num | |
4593 | && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags) | |
4594 | { | |
4595 | /* Clear the arguments that are stored in drex. */ | |
0dfbf9d7 L |
4596 | operand_type_set (&i.types[2], 0); |
4597 | operand_type_set (&i.types[3], 0); | |
85f10a01 MM |
4598 | i.reg_operands -= 2; |
4599 | ||
4600 | /* Specify the modrm encoding and remember the register | |
4601 | including the bits normally stored in the REX byte. */ | |
4602 | i.tm.extension_opcode = DREX_X1_XMEM_X2_X2; | |
4603 | i.drex.modrm_reg = 0; | |
4604 | i.drex.modrm_regmem = 1; | |
4605 | i.drex.reg = (i.op[3].regs->reg_num | |
4606 | + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); | |
4607 | } | |
4608 | ||
4609 | /* Case 6: 4 operand insn, dest = src3, src1 = memory. */ | |
4610 | else if (operand_type_check (i.types[0], anymem) != 0 | |
4611 | && i.types[1].bitfield.regxmm != 0 | |
4612 | && i.types[2].bitfield.regxmm != 0 | |
4613 | && i.types[3].bitfield.regxmm != 0 | |
4614 | && i.op[2].regs->reg_num == i.op[3].regs->reg_num | |
4615 | && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags) | |
4616 | { | |
4617 | /* clear the arguments that are stored in drex */ | |
0dfbf9d7 L |
4618 | operand_type_set (&i.types[2], 0); |
4619 | operand_type_set (&i.types[3], 0); | |
85f10a01 MM |
4620 | i.reg_operands -= 2; |
4621 | ||
4622 | /* Specify the modrm encoding and remember the register | |
4623 | including the bits normally stored in the REX byte. */ | |
4624 | i.tm.extension_opcode = DREX_XMEM_X1_X2_X2; | |
4625 | i.drex.modrm_reg = 1; | |
4626 | i.drex.modrm_regmem = 0; | |
4627 | i.drex.reg = (i.op[3].regs->reg_num | |
4628 | + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); | |
4629 | } | |
4630 | ||
4631 | else | |
4632 | as_bad (_("Incorrect operands for the '%s' instruction"), | |
4633 | i.tm.name); | |
4634 | } | |
4635 | ||
4636 | /* SSE5 instructions with the DREX byte where the only memory operand | |
4637 | is in the 2nd argument, and the first and last xmm register must | |
4638 | match, and is encoded in the DREX byte. */ | |
4639 | else if (i.tm.opcode_modifier.drex | |
4640 | && !i.tm.opcode_modifier.drexv | |
4641 | && i.operands == 4) | |
4642 | { | |
4643 | /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */ | |
4644 | if (i.types[0].bitfield.regxmm != 0 | |
4645 | && (i.types[1].bitfield.regxmm | |
4646 | || operand_type_check(i.types[1], anymem)) | |
4647 | && i.types[2].bitfield.regxmm != 0 | |
4648 | && i.types[3].bitfield.regxmm != 0 | |
4649 | && i.op[0].regs->reg_num == i.op[3].regs->reg_num | |
4650 | && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags) | |
4651 | { | |
4652 | /* clear the arguments that are stored in drex */ | |
0dfbf9d7 L |
4653 | operand_type_set (&i.types[0], 0); |
4654 | operand_type_set (&i.types[3], 0); | |
85f10a01 MM |
4655 | i.reg_operands -= 2; |
4656 | ||
4657 | /* Specify the modrm encoding and remember the register | |
4658 | including the high bit normally stored in the REX | |
4659 | byte. */ | |
4660 | i.drex.modrm_reg = 2; | |
4661 | i.drex.modrm_regmem = 1; | |
4662 | i.drex.reg = (i.op[3].regs->reg_num | |
4663 | + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); | |
4664 | } | |
4665 | ||
4666 | else | |
4667 | as_bad (_("Incorrect operands for the '%s' instruction"), | |
4668 | i.tm.name); | |
4669 | } | |
4670 | ||
4671 | /* SSE5 3 operand instructions that the result is a register, being | |
4672 | either operand can be a memory operand, using OC0 to note which | |
4673 | one is the memory. */ | |
4674 | else if (i.tm.opcode_modifier.drex | |
4675 | && i.tm.opcode_modifier.drexv | |
4676 | && i.operands == 3) | |
4677 | { | |
4678 | i.tm.extension_opcode = None; | |
4679 | ||
4680 | /* Case 1: 3 operand insn, src1 = register. */ | |
4681 | if (i.types[0].bitfield.regxmm != 0 | |
4682 | && i.types[1].bitfield.regxmm != 0 | |
4683 | && i.types[2].bitfield.regxmm != 0) | |
4684 | { | |
4685 | /* Clear the arguments that are stored in drex. */ | |
0dfbf9d7 | 4686 | operand_type_set (&i.types[2], 0); |
85f10a01 MM |
4687 | i.reg_operands--; |
4688 | ||
4689 | /* Specify the modrm encoding and remember the register | |
4690 | including the high bit normally stored in the REX byte. */ | |
4691 | i.tm.extension_opcode = DREX_XMEM_X1_X2; | |
4692 | i.drex.modrm_reg = 1; | |
4693 | i.drex.modrm_regmem = 0; | |
4694 | i.drex.reg = (i.op[2].regs->reg_num | |
4695 | + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0)); | |
4696 | } | |
4697 | ||
4698 | /* Case 2: 3 operand insn, src1 = memory. */ | |
4699 | else if (operand_type_check (i.types[0], anymem) != 0 | |
4700 | && i.types[1].bitfield.regxmm != 0 | |
4701 | && i.types[2].bitfield.regxmm != 0) | |
4702 | { | |
4703 | /* Clear the arguments that are stored in drex. */ | |
0dfbf9d7 | 4704 | operand_type_set (&i.types[2], 0); |
85f10a01 MM |
4705 | i.reg_operands--; |
4706 | ||
4707 | /* Specify the modrm encoding and remember the register | |
4708 | including the high bit normally stored in the REX | |
4709 | byte. */ | |
4710 | i.tm.extension_opcode = DREX_XMEM_X1_X2; | |
4711 | i.drex.modrm_reg = 1; | |
4712 | i.drex.modrm_regmem = 0; | |
4713 | i.drex.reg = (i.op[2].regs->reg_num | |
4714 | + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0)); | |
4715 | } | |
4716 | ||
4717 | /* Case 3: 3 operand insn, src2 = memory. */ | |
4718 | else if (i.types[0].bitfield.regxmm != 0 | |
4719 | && operand_type_check (i.types[1], anymem) != 0 | |
4720 | && i.types[2].bitfield.regxmm != 0) | |
4721 | { | |
4722 | /* Clear the arguments that are stored in drex. */ | |
0dfbf9d7 | 4723 | operand_type_set (&i.types[2], 0); |
85f10a01 MM |
4724 | i.reg_operands--; |
4725 | ||
4726 | /* Specify the modrm encoding and remember the register | |
4727 | including the high bit normally stored in the REX byte. */ | |
4728 | i.tm.extension_opcode = DREX_X1_XMEM_X2; | |
4729 | i.drex.modrm_reg = 0; | |
4730 | i.drex.modrm_regmem = 1; | |
4731 | i.drex.reg = (i.op[2].regs->reg_num | |
4732 | + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0)); | |
4733 | } | |
4734 | ||
4735 | else | |
4736 | as_bad (_("Incorrect operands for the '%s' instruction"), | |
4737 | i.tm.name); | |
4738 | } | |
4739 | ||
4740 | /* SSE5 4 operand instructions that are the comparison instructions | |
4741 | where the first operand is the immediate value of the comparison | |
4742 | to be done. */ | |
4743 | else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4) | |
4744 | { | |
4745 | /* Case 1: 4 operand insn, src1 = reg/memory. */ | |
4746 | if (operand_type_check (i.types[0], imm) != 0 | |
4747 | && (i.types[1].bitfield.regxmm | |
4748 | || operand_type_check (i.types[1], anymem)) | |
4749 | && i.types[2].bitfield.regxmm != 0 | |
4750 | && i.types[3].bitfield.regxmm != 0) | |
4751 | { | |
4752 | /* clear the arguments that are stored in drex */ | |
0dfbf9d7 | 4753 | operand_type_set (&i.types[3], 0); |
85f10a01 MM |
4754 | i.reg_operands--; |
4755 | ||
4756 | /* Specify the modrm encoding and remember the register | |
4757 | including the high bit normally stored in the REX byte. */ | |
4758 | i.drex.modrm_reg = 2; | |
4759 | i.drex.modrm_regmem = 1; | |
4760 | i.drex.reg = (i.op[3].regs->reg_num | |
4761 | + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0)); | |
4762 | } | |
4763 | ||
4764 | /* Case 2: 3 operand insn with ImmExt that places the | |
4765 | opcode_extension as an immediate argument. This is used for | |
4766 | all of the varients of comparison that supplies the appropriate | |
4767 | value as part of the instruction. */ | |
4768 | else if ((i.types[0].bitfield.regxmm | |
4769 | || operand_type_check (i.types[0], anymem)) | |
4770 | && i.types[1].bitfield.regxmm != 0 | |
4771 | && i.types[2].bitfield.regxmm != 0 | |
4772 | && operand_type_check (i.types[3], imm) != 0) | |
4773 | { | |
4774 | /* clear the arguments that are stored in drex */ | |
0dfbf9d7 | 4775 | operand_type_set (&i.types[2], 0); |
85f10a01 MM |
4776 | i.reg_operands--; |
4777 | ||
4778 | /* Specify the modrm encoding and remember the register | |
4779 | including the high bit normally stored in the REX byte. */ | |
4780 | i.drex.modrm_reg = 1; | |
4781 | i.drex.modrm_regmem = 0; | |
4782 | i.drex.reg = (i.op[2].regs->reg_num | |
4783 | + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0)); | |
4784 | } | |
4785 | ||
4786 | else | |
4787 | as_bad (_("Incorrect operands for the '%s' instruction"), | |
4788 | i.tm.name); | |
4789 | } | |
4790 | ||
4791 | else if (i.tm.opcode_modifier.drex | |
4792 | || i.tm.opcode_modifier.drexv | |
4793 | || i.tm.opcode_modifier.drexc) | |
4794 | as_bad (_("Internal error for the '%s' instruction"), i.tm.name); | |
4795 | } | |
4796 | ||
c0f3af97 L |
4797 | static int |
4798 | bad_implicit_operand (int xmm) | |
4799 | { | |
4800 | const char *reg = xmm ? "xmm0" : "ymm0"; | |
4801 | if (intel_syntax) | |
4802 | as_bad (_("the last operand of `%s' must be `%s%s'"), | |
4803 | i.tm.name, register_prefix, reg); | |
4804 | else | |
4805 | as_bad (_("the first operand of `%s' must be `%s%s'"), | |
4806 | i.tm.name, register_prefix, reg); | |
4807 | return 0; | |
4808 | } | |
4809 | ||
29b0f896 | 4810 | static int |
e3bb37b5 | 4811 | process_operands (void) |
29b0f896 AM |
4812 | { |
4813 | /* Default segment register this instruction will use for memory | |
4814 | accesses. 0 means unknown. This is only for optimizing out | |
4815 | unnecessary segment overrides. */ | |
4816 | const seg_entry *default_seg = 0; | |
4817 | ||
85f10a01 MM |
4818 | /* Handle all of the DREX munging that SSE5 needs. */ |
4819 | if (i.tm.opcode_modifier.drex | |
4820 | || i.tm.opcode_modifier.drexv | |
4821 | || i.tm.opcode_modifier.drexc) | |
4822 | process_drex (); | |
4823 | ||
c0f3af97 L |
4824 | if (i.tm.opcode_modifier.sse2avx |
4825 | && (i.tm.opcode_modifier.vexnds | |
4826 | || i.tm.opcode_modifier.vexndd)) | |
29b0f896 | 4827 | { |
c0f3af97 L |
4828 | unsigned int dup = i.operands; |
4829 | unsigned int dest = dup - 1; | |
9fcfb3d7 L |
4830 | unsigned int j; |
4831 | ||
c0f3af97 | 4832 | /* The destination must be an xmm register. */ |
0dfbf9d7 | 4833 | assert (i.reg_operands |
c0f3af97 L |
4834 | && MAX_OPERANDS > dup |
4835 | && operand_type_equal (&i.types[dest], ®xmm)); | |
4836 | ||
4837 | if (i.tm.opcode_modifier.firstxmm0) | |
e2ec9d29 | 4838 | { |
c0f3af97 L |
4839 | /* The first operand is implicit and must be xmm0. */ |
4840 | assert (operand_type_equal (&i.types[0], ®xmm)); | |
4841 | if (i.op[0].regs->reg_num != 0) | |
4842 | return bad_implicit_operand (1); | |
4843 | ||
4844 | if (i.tm.opcode_modifier.vex3sources) | |
4845 | { | |
4846 | /* Keep xmm0 for instructions with VEX prefix and 3 | |
4847 | sources. */ | |
4848 | goto duplicate; | |
4849 | } | |
e2ec9d29 | 4850 | else |
c0f3af97 L |
4851 | { |
4852 | /* We remove the first xmm0 and keep the number of | |
4853 | operands unchanged, which in fact duplicates the | |
4854 | destination. */ | |
4855 | for (j = 1; j < i.operands; j++) | |
4856 | { | |
4857 | i.op[j - 1] = i.op[j]; | |
4858 | i.types[j - 1] = i.types[j]; | |
4859 | i.tm.operand_types[j - 1] = i.tm.operand_types[j]; | |
4860 | } | |
4861 | } | |
4862 | } | |
4863 | else if (i.tm.opcode_modifier.implicit1stxmm0) | |
4864 | { | |
4865 | assert ((MAX_OPERANDS - 1) > dup | |
4866 | && i.tm.opcode_modifier.vex3sources); | |
4867 | ||
4868 | /* Add the implicit xmm0 for instructions with VEX prefix | |
4869 | and 3 sources. */ | |
4870 | for (j = i.operands; j > 0; j--) | |
4871 | { | |
4872 | i.op[j] = i.op[j - 1]; | |
4873 | i.types[j] = i.types[j - 1]; | |
4874 | i.tm.operand_types[j] = i.tm.operand_types[j - 1]; | |
4875 | } | |
4876 | i.op[0].regs | |
4877 | = (const reg_entry *) hash_find (reg_hash, "xmm0"); | |
4878 | i.types[0] = regxmm; | |
4879 | i.tm.operand_types[0] = regxmm; | |
4880 | ||
4881 | i.operands += 2; | |
4882 | i.reg_operands += 2; | |
4883 | i.tm.operands += 2; | |
4884 | ||
4885 | dup++; | |
4886 | dest++; | |
4887 | i.op[dup] = i.op[dest]; | |
4888 | i.types[dup] = i.types[dest]; | |
4889 | i.tm.operand_types[dup] = i.tm.operand_types[dest]; | |
e2ec9d29 | 4890 | } |
c0f3af97 L |
4891 | else |
4892 | { | |
4893 | duplicate: | |
4894 | i.operands++; | |
4895 | i.reg_operands++; | |
4896 | i.tm.operands++; | |
4897 | ||
4898 | i.op[dup] = i.op[dest]; | |
4899 | i.types[dup] = i.types[dest]; | |
4900 | i.tm.operand_types[dup] = i.tm.operand_types[dest]; | |
4901 | } | |
4902 | ||
4903 | if (i.tm.opcode_modifier.immext) | |
4904 | process_immext (); | |
4905 | } | |
4906 | else if (i.tm.opcode_modifier.firstxmm0) | |
4907 | { | |
4908 | unsigned int j; | |
4909 | ||
4910 | /* The first operand is implicit and must be xmm0/ymm0. */ | |
4911 | assert (i.reg_operands | |
4912 | && (operand_type_equal (&i.types[0], ®xmm) | |
4913 | || operand_type_equal (&i.types[0], ®ymm))); | |
4914 | if (i.op[0].regs->reg_num != 0) | |
4915 | return bad_implicit_operand (i.types[0].bitfield.regxmm); | |
9fcfb3d7 L |
4916 | |
4917 | for (j = 1; j < i.operands; j++) | |
4918 | { | |
4919 | i.op[j - 1] = i.op[j]; | |
4920 | i.types[j - 1] = i.types[j]; | |
4921 | ||
4922 | /* We need to adjust fields in i.tm since they are used by | |
4923 | build_modrm_byte. */ | |
4924 | i.tm.operand_types [j - 1] = i.tm.operand_types [j]; | |
4925 | } | |
4926 | ||
e2ec9d29 L |
4927 | i.operands--; |
4928 | i.reg_operands--; | |
e2ec9d29 L |
4929 | i.tm.operands--; |
4930 | } | |
4931 | else if (i.tm.opcode_modifier.regkludge) | |
4932 | { | |
4933 | /* The imul $imm, %reg instruction is converted into | |
4934 | imul $imm, %reg, %reg, and the clr %reg instruction | |
4935 | is converted into xor %reg, %reg. */ | |
4936 | ||
4937 | unsigned int first_reg_op; | |
4938 | ||
4939 | if (operand_type_check (i.types[0], reg)) | |
4940 | first_reg_op = 0; | |
4941 | else | |
4942 | first_reg_op = 1; | |
4943 | /* Pretend we saw the extra register operand. */ | |
4944 | assert (i.reg_operands == 1 | |
4945 | && i.op[first_reg_op + 1].regs == 0); | |
4946 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; | |
4947 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
4948 | i.operands++; | |
4949 | i.reg_operands++; | |
29b0f896 AM |
4950 | } |
4951 | ||
40fb9820 | 4952 | if (i.tm.opcode_modifier.shortform) |
29b0f896 | 4953 | { |
40fb9820 L |
4954 | if (i.types[0].bitfield.sreg2 |
4955 | || i.types[0].bitfield.sreg3) | |
29b0f896 | 4956 | { |
4eed87de AM |
4957 | if (i.tm.base_opcode == POP_SEG_SHORT |
4958 | && i.op[0].regs->reg_num == 1) | |
29b0f896 | 4959 | { |
4eed87de AM |
4960 | as_bad (_("you can't `pop %%cs'")); |
4961 | return 0; | |
29b0f896 | 4962 | } |
4eed87de AM |
4963 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); |
4964 | if ((i.op[0].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 4965 | i.rex |= REX_B; |
4eed87de AM |
4966 | } |
4967 | else | |
4968 | { | |
85f10a01 MM |
4969 | /* The register or float register operand is in operand |
4970 | 0 or 1. */ | |
40fb9820 L |
4971 | unsigned int op; |
4972 | ||
4973 | if (i.types[0].bitfield.floatreg | |
4974 | || operand_type_check (i.types[0], reg)) | |
4975 | op = 0; | |
4976 | else | |
4977 | op = 1; | |
4eed87de AM |
4978 | /* Register goes in low 3 bits of opcode. */ |
4979 | i.tm.base_opcode |= i.op[op].regs->reg_num; | |
4980 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 4981 | i.rex |= REX_B; |
40fb9820 | 4982 | if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 | 4983 | { |
4eed87de AM |
4984 | /* Warn about some common errors, but press on regardless. |
4985 | The first case can be generated by gcc (<= 2.8.1). */ | |
4986 | if (i.operands == 2) | |
4987 | { | |
4988 | /* Reversed arguments on faddp, fsubp, etc. */ | |
a540244d L |
4989 | as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, |
4990 | register_prefix, i.op[1].regs->reg_name, | |
4991 | register_prefix, i.op[0].regs->reg_name); | |
4eed87de AM |
4992 | } |
4993 | else | |
4994 | { | |
4995 | /* Extraneous `l' suffix on fp insn. */ | |
a540244d L |
4996 | as_warn (_("translating to `%s %s%s'"), i.tm.name, |
4997 | register_prefix, i.op[0].regs->reg_name); | |
4eed87de | 4998 | } |
29b0f896 AM |
4999 | } |
5000 | } | |
5001 | } | |
40fb9820 | 5002 | else if (i.tm.opcode_modifier.modrm) |
29b0f896 AM |
5003 | { |
5004 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
52271982 AM |
5005 | must be put into the modrm byte). Now, we make the modrm and |
5006 | index base bytes based on all the info we've collected. */ | |
29b0f896 AM |
5007 | |
5008 | default_seg = build_modrm_byte (); | |
5009 | } | |
8a2ed489 | 5010 | else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32) |
29b0f896 AM |
5011 | { |
5012 | default_seg = &ds; | |
5013 | } | |
40fb9820 | 5014 | else if (i.tm.opcode_modifier.isstring) |
29b0f896 AM |
5015 | { |
5016 | /* For the string instructions that allow a segment override | |
5017 | on one of their operands, the default segment is ds. */ | |
5018 | default_seg = &ds; | |
5019 | } | |
5020 | ||
75178d9d L |
5021 | if (i.tm.base_opcode == 0x8d /* lea */ |
5022 | && i.seg[0] | |
5023 | && !quiet_warnings) | |
30123838 | 5024 | as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); |
52271982 AM |
5025 | |
5026 | /* If a segment was explicitly specified, and the specified segment | |
5027 | is not the default, use an opcode prefix to select it. If we | |
5028 | never figured out what the default segment is, then default_seg | |
5029 | will be zero at this point, and the specified segment prefix will | |
5030 | always be used. */ | |
29b0f896 AM |
5031 | if ((i.seg[0]) && (i.seg[0] != default_seg)) |
5032 | { | |
5033 | if (!add_prefix (i.seg[0]->seg_prefix)) | |
5034 | return 0; | |
5035 | } | |
5036 | return 1; | |
5037 | } | |
5038 | ||
5039 | static const seg_entry * | |
e3bb37b5 | 5040 | build_modrm_byte (void) |
29b0f896 AM |
5041 | { |
5042 | const seg_entry *default_seg = 0; | |
c0f3af97 L |
5043 | unsigned int source, dest; |
5044 | int vex_3_sources; | |
5045 | ||
5046 | /* The first operand of instructions with VEX prefix and 3 sources | |
5047 | must be VEX_Imm4. */ | |
5048 | vex_3_sources = i.tm.opcode_modifier.vex3sources; | |
5049 | if (vex_3_sources) | |
5050 | { | |
5051 | unsigned int nds, reg; | |
5052 | ||
5053 | if (i.tm.opcode_modifier.veximmext | |
5054 | && i.tm.opcode_modifier.immext) | |
5055 | { | |
5056 | dest = i.operands - 2; | |
5057 | assert (dest == 3); | |
5058 | } | |
5059 | else | |
5060 | dest = i.operands - 1; | |
5061 | nds = dest - 1; | |
5062 | ||
5063 | /* There are 2 kinds of instructions: | |
dae39acc | 5064 | 1. 5 operands: one immediate operand and 4 register |
c0f3af97 L |
5065 | operands or 3 register operands plus 1 memory operand. |
5066 | It must have VexNDS and VexW0 or VexW1. The destination | |
5067 | must be either XMM or YMM register. | |
5068 | 2. 4 operands: 4 register operands or 3 register operands | |
5069 | plus 1 memory operand. It must have VexNDS and VexImmExt. */ | |
5070 | if (!((i.reg_operands == 4 | |
5071 | || (i.reg_operands == 3 && i.mem_operands == 1)) | |
5072 | && i.tm.opcode_modifier.vexnds | |
5073 | && (operand_type_equal (&i.tm.operand_types[dest], ®xmm) | |
5074 | || operand_type_equal (&i.tm.operand_types[dest], ®ymm)) | |
c0f3af97 L |
5075 | && ((dest == 4 |
5076 | && i.imm_operands == 1 | |
5077 | && i.types[0].bitfield.vex_imm4 | |
5078 | && (i.tm.opcode_modifier.vexw0 | |
5079 | || i.tm.opcode_modifier.vexw1)) | |
5080 | || (dest == 3 | |
5081 | && (i.imm_operands == 0 | |
5082 | || (i.imm_operands == 1 | |
5083 | && i.tm.opcode_modifier.immext)) | |
5084 | && i.tm.opcode_modifier.veximmext)))) | |
5085 | abort (); | |
5086 | ||
c0f3af97 L |
5087 | if (i.imm_operands == 0) |
5088 | { | |
5089 | /* When there is no immediate operand, generate an 8bit | |
5090 | immediate operand to encode the first operand. */ | |
5091 | expressionS *exp = &im_expressions[i.imm_operands++]; | |
5092 | i.op[i.operands].imms = exp; | |
5093 | i.types[i.operands] = imm8; | |
5094 | i.operands++; | |
5095 | /* If VexW1 is set, the first operand is the source and | |
5096 | the second operand is encoded in the immediate operand. */ | |
5097 | if (i.tm.opcode_modifier.vexw1) | |
5098 | { | |
5099 | source = 0; | |
5100 | reg = 1; | |
5101 | } | |
5102 | else | |
5103 | { | |
5104 | source = 1; | |
5105 | reg = 0; | |
5106 | } | |
dae39acc L |
5107 | |
5108 | /* FMA swaps REG and NDS. */ | |
5109 | if (i.tm.cpu_flags.bitfield.cpufma) | |
5110 | { | |
5111 | unsigned int tmp; | |
5112 | tmp = reg; | |
5113 | reg = nds; | |
5114 | nds = tmp; | |
5115 | } | |
5116 | ||
c0f3af97 L |
5117 | assert (operand_type_equal (&i.tm.operand_types[reg], ®xmm) |
5118 | || operand_type_equal (&i.tm.operand_types[reg], | |
5119 | ®ymm)); | |
5120 | exp->X_op = O_constant; | |
5121 | exp->X_add_number | |
5122 | = ((i.op[reg].regs->reg_num | |
5123 | + ((i.op[reg].regs->reg_flags & RegRex) ? 8 : 0)) << 4); | |
5124 | } | |
5125 | else | |
5126 | { | |
5127 | unsigned int imm; | |
5128 | ||
5129 | if (i.tm.opcode_modifier.vexw0) | |
5130 | { | |
5131 | /* If VexW0 is set, the third operand is the source and | |
5132 | the second operand is encoded in the immediate | |
5133 | operand. */ | |
5134 | source = 2; | |
5135 | reg = 1; | |
5136 | } | |
5137 | else | |
5138 | { | |
5139 | /* VexW1 is set, the second operand is the source and | |
5140 | the third operand is encoded in the immediate | |
5141 | operand. */ | |
5142 | source = 1; | |
5143 | reg = 2; | |
5144 | } | |
5145 | ||
5146 | if (i.tm.opcode_modifier.immext) | |
5147 | { | |
5148 | /* When ImmExt is set, the immdiate byte is the last | |
5149 | operand. */ | |
5150 | imm = i.operands - 1; | |
5151 | source--; | |
5152 | reg--; | |
5153 | } | |
5154 | else | |
5155 | { | |
5156 | imm = 0; | |
5157 | ||
5158 | /* Turn on Imm8 so that output_imm will generate it. */ | |
5159 | i.types[imm].bitfield.imm8 = 1; | |
5160 | } | |
5161 | ||
5162 | assert (operand_type_equal (&i.tm.operand_types[reg], ®xmm) | |
5163 | || operand_type_equal (&i.tm.operand_types[reg], | |
5164 | ®ymm)); | |
5165 | i.op[imm].imms->X_add_number | |
5166 | |= ((i.op[reg].regs->reg_num | |
5167 | + ((i.op[reg].regs->reg_flags & RegRex) ? 8 : 0)) << 4); | |
5168 | } | |
dae39acc L |
5169 | |
5170 | assert (operand_type_equal (&i.tm.operand_types[nds], ®xmm) | |
5171 | || operand_type_equal (&i.tm.operand_types[nds], ®ymm)); | |
5172 | i.vex.register_specifier = i.op[nds].regs; | |
5173 | ||
c0f3af97 L |
5174 | } |
5175 | else | |
5176 | source = dest = 0; | |
29b0f896 | 5177 | |
85f10a01 MM |
5178 | /* SSE5 4 operand instructions are encoded in such a way that one of |
5179 | the inputs must match the destination register. Process_drex hides | |
5180 | the 3rd argument in the drex field, so that by the time we get | |
5181 | here, it looks to GAS as if this is a 2 operand instruction. */ | |
5182 | if ((i.tm.opcode_modifier.drex | |
5183 | || i.tm.opcode_modifier.drexv | |
b5016f89 | 5184 | || i.tm.opcode_modifier.drexc) |
85f10a01 MM |
5185 | && i.reg_operands == 2) |
5186 | { | |
5187 | const reg_entry *reg = i.op[i.drex.modrm_reg].regs; | |
5188 | const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs; | |
5189 | ||
5190 | i.rm.reg = reg->reg_num; | |
5191 | i.rm.regmem = regmem->reg_num; | |
5192 | i.rm.mode = 3; | |
5193 | if ((reg->reg_flags & RegRex) != 0) | |
5194 | i.rex |= REX_R; | |
5195 | if ((regmem->reg_flags & RegRex) != 0) | |
5196 | i.rex |= REX_B; | |
5197 | } | |
5198 | ||
29b0f896 | 5199 | /* i.reg_operands MUST be the number of real register operands; |
c0f3af97 L |
5200 | implicit registers do not count. If there are 3 register |
5201 | operands, it must be a instruction with VexNDS. For a | |
5202 | instruction with VexNDD, the destination register is encoded | |
5203 | in VEX prefix. If there are 4 register operands, it must be | |
5204 | a instruction with VEX prefix and 3 sources. */ | |
5205 | else if (i.mem_operands == 0 | |
5206 | && ((i.reg_operands == 2 | |
5207 | && !i.tm.opcode_modifier.vexndd) | |
5208 | || (i.reg_operands == 3 | |
5209 | && i.tm.opcode_modifier.vexnds) | |
5210 | || (i.reg_operands == 4 && vex_3_sources))) | |
29b0f896 | 5211 | { |
cab737b9 L |
5212 | switch (i.operands) |
5213 | { | |
5214 | case 2: | |
5215 | source = 0; | |
5216 | break; | |
5217 | case 3: | |
c81128dc L |
5218 | /* When there are 3 operands, one of them may be immediate, |
5219 | which may be the first or the last operand. Otherwise, | |
c0f3af97 L |
5220 | the first operand must be shift count register (cl) or it |
5221 | is an instruction with VexNDS. */ | |
c81128dc L |
5222 | assert (i.imm_operands == 1 |
5223 | || (i.imm_operands == 0 | |
c0f3af97 L |
5224 | && (i.tm.opcode_modifier.vexnds |
5225 | || i.types[0].bitfield.shiftcount))); | |
40fb9820 L |
5226 | if (operand_type_check (i.types[0], imm) |
5227 | || i.types[0].bitfield.shiftcount) | |
5228 | source = 1; | |
5229 | else | |
5230 | source = 0; | |
cab737b9 L |
5231 | break; |
5232 | case 4: | |
368d64cc L |
5233 | /* When there are 4 operands, the first two must be 8bit |
5234 | immediate operands. The source operand will be the 3rd | |
c0f3af97 L |
5235 | one. |
5236 | ||
5237 | For instructions with VexNDS, if the first operand | |
5238 | an imm8, the source operand is the 2nd one. If the last | |
5239 | operand is imm8, the source operand is the first one. */ | |
5240 | assert ((i.imm_operands == 2 | |
5241 | && i.types[0].bitfield.imm8 | |
5242 | && i.types[1].bitfield.imm8) | |
5243 | || (i.tm.opcode_modifier.vexnds | |
5244 | && i.imm_operands == 1 | |
5245 | && (i.types[0].bitfield.imm8 | |
5246 | || i.types[i.operands - 1].bitfield.imm8))); | |
5247 | if (i.tm.opcode_modifier.vexnds) | |
5248 | { | |
5249 | if (i.types[0].bitfield.imm8) | |
5250 | source = 1; | |
5251 | else | |
5252 | source = 0; | |
5253 | } | |
5254 | else | |
5255 | source = 2; | |
5256 | break; | |
5257 | case 5: | |
cab737b9 L |
5258 | break; |
5259 | default: | |
5260 | abort (); | |
5261 | } | |
5262 | ||
c0f3af97 L |
5263 | if (!vex_3_sources) |
5264 | { | |
5265 | dest = source + 1; | |
5266 | ||
5267 | if (i.tm.opcode_modifier.vexnds) | |
5268 | { | |
5269 | /* For instructions with VexNDS, the register-only | |
5270 | source operand must be XMM or YMM register. It is | |
5271 | encoded in VEX prefix. */ | |
5272 | if ((dest + 1) >= i.operands | |
5273 | || (!operand_type_equal (&i.tm.operand_types[dest], | |
5274 | ®xmm) | |
5275 | && !operand_type_equal (&i.tm.operand_types[dest], | |
5276 | ®ymm))) | |
5277 | abort (); | |
5278 | i.vex.register_specifier = i.op[dest].regs; | |
5279 | dest++; | |
5280 | } | |
5281 | } | |
29b0f896 AM |
5282 | |
5283 | i.rm.mode = 3; | |
5284 | /* One of the register operands will be encoded in the i.tm.reg | |
5285 | field, the other in the combined i.tm.mode and i.tm.regmem | |
5286 | fields. If no form of this instruction supports a memory | |
5287 | destination operand, then we assume the source operand may | |
5288 | sometimes be a memory operand and so we need to store the | |
5289 | destination in the i.rm.reg field. */ | |
40fb9820 L |
5290 | if (!i.tm.operand_types[dest].bitfield.regmem |
5291 | && operand_type_check (i.tm.operand_types[dest], anymem) == 0) | |
29b0f896 AM |
5292 | { |
5293 | i.rm.reg = i.op[dest].regs->reg_num; | |
5294 | i.rm.regmem = i.op[source].regs->reg_num; | |
5295 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 5296 | i.rex |= REX_R; |
29b0f896 | 5297 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 5298 | i.rex |= REX_B; |
29b0f896 AM |
5299 | } |
5300 | else | |
5301 | { | |
5302 | i.rm.reg = i.op[source].regs->reg_num; | |
5303 | i.rm.regmem = i.op[dest].regs->reg_num; | |
5304 | if ((i.op[dest].regs->reg_flags & RegRex) != 0) | |
161a04f6 | 5305 | i.rex |= REX_B; |
29b0f896 | 5306 | if ((i.op[source].regs->reg_flags & RegRex) != 0) |
161a04f6 | 5307 | i.rex |= REX_R; |
29b0f896 | 5308 | } |
161a04f6 | 5309 | if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B))) |
c4a530c5 | 5310 | { |
40fb9820 L |
5311 | if (!i.types[0].bitfield.control |
5312 | && !i.types[1].bitfield.control) | |
c4a530c5 | 5313 | abort (); |
161a04f6 | 5314 | i.rex &= ~(REX_R | REX_B); |
c4a530c5 JB |
5315 | add_prefix (LOCK_PREFIX_OPCODE); |
5316 | } | |
29b0f896 AM |
5317 | } |
5318 | else | |
5319 | { /* If it's not 2 reg operands... */ | |
c0f3af97 L |
5320 | unsigned int mem; |
5321 | ||
29b0f896 AM |
5322 | if (i.mem_operands) |
5323 | { | |
5324 | unsigned int fake_zero_displacement = 0; | |
99018f42 | 5325 | unsigned int op; |
4eed87de | 5326 | |
85f10a01 MM |
5327 | /* This has been precalculated for SSE5 instructions |
5328 | that have a DREX field earlier in process_drex. */ | |
b5016f89 L |
5329 | if (i.tm.opcode_modifier.drex |
5330 | || i.tm.opcode_modifier.drexv | |
5331 | || i.tm.opcode_modifier.drexc) | |
85f10a01 MM |
5332 | op = i.drex.modrm_regmem; |
5333 | else | |
5334 | { | |
c0209578 L |
5335 | for (op = 0; op < i.operands; op++) |
5336 | if (operand_type_check (i.types[op], anymem)) | |
5337 | break; | |
5338 | assert (op < i.operands); | |
85f10a01 | 5339 | } |
29b0f896 AM |
5340 | |
5341 | default_seg = &ds; | |
5342 | ||
5343 | if (i.base_reg == 0) | |
5344 | { | |
5345 | i.rm.mode = 0; | |
5346 | if (!i.disp_operands) | |
5347 | fake_zero_displacement = 1; | |
5348 | if (i.index_reg == 0) | |
5349 | { | |
5350 | /* Operand is just <disp> */ | |
20f0a1fc | 5351 | if (flag_code == CODE_64BIT) |
29b0f896 AM |
5352 | { |
5353 | /* 64bit mode overwrites the 32bit absolute | |
5354 | addressing by RIP relative addressing and | |
5355 | absolute addressing is encoded by one of the | |
5356 | redundant SIB forms. */ | |
5357 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
5358 | i.sib.base = NO_BASE_REGISTER; | |
5359 | i.sib.index = NO_INDEX_REGISTER; | |
fc225355 | 5360 | i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) |
40fb9820 | 5361 | ? disp32s : disp32); |
20f0a1fc | 5362 | } |
fc225355 L |
5363 | else if ((flag_code == CODE_16BIT) |
5364 | ^ (i.prefix[ADDR_PREFIX] != 0)) | |
20f0a1fc NC |
5365 | { |
5366 | i.rm.regmem = NO_BASE_REGISTER_16; | |
40fb9820 | 5367 | i.types[op] = disp16; |
20f0a1fc NC |
5368 | } |
5369 | else | |
5370 | { | |
5371 | i.rm.regmem = NO_BASE_REGISTER; | |
40fb9820 | 5372 | i.types[op] = disp32; |
29b0f896 AM |
5373 | } |
5374 | } | |
5375 | else /* !i.base_reg && i.index_reg */ | |
5376 | { | |
db51cc60 L |
5377 | if (i.index_reg->reg_num == RegEiz |
5378 | || i.index_reg->reg_num == RegRiz) | |
5379 | i.sib.index = NO_INDEX_REGISTER; | |
5380 | else | |
5381 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
5382 | i.sib.base = NO_BASE_REGISTER; |
5383 | i.sib.scale = i.log2_scale_factor; | |
5384 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
40fb9820 L |
5385 | i.types[op].bitfield.disp8 = 0; |
5386 | i.types[op].bitfield.disp16 = 0; | |
5387 | i.types[op].bitfield.disp64 = 0; | |
29b0f896 | 5388 | if (flag_code != CODE_64BIT) |
40fb9820 L |
5389 | { |
5390 | /* Must be 32 bit */ | |
5391 | i.types[op].bitfield.disp32 = 1; | |
5392 | i.types[op].bitfield.disp32s = 0; | |
5393 | } | |
29b0f896 | 5394 | else |
40fb9820 L |
5395 | { |
5396 | i.types[op].bitfield.disp32 = 0; | |
5397 | i.types[op].bitfield.disp32s = 1; | |
5398 | } | |
29b0f896 | 5399 | if ((i.index_reg->reg_flags & RegRex) != 0) |
161a04f6 | 5400 | i.rex |= REX_X; |
29b0f896 AM |
5401 | } |
5402 | } | |
5403 | /* RIP addressing for 64bit mode. */ | |
9a04903e JB |
5404 | else if (i.base_reg->reg_num == RegRip || |
5405 | i.base_reg->reg_num == RegEip) | |
29b0f896 AM |
5406 | { |
5407 | i.rm.regmem = NO_BASE_REGISTER; | |
40fb9820 L |
5408 | i.types[op].bitfield.disp8 = 0; |
5409 | i.types[op].bitfield.disp16 = 0; | |
5410 | i.types[op].bitfield.disp32 = 0; | |
5411 | i.types[op].bitfield.disp32s = 1; | |
5412 | i.types[op].bitfield.disp64 = 0; | |
71903a11 | 5413 | i.flags[op] |= Operand_PCrel; |
20f0a1fc NC |
5414 | if (! i.disp_operands) |
5415 | fake_zero_displacement = 1; | |
29b0f896 | 5416 | } |
40fb9820 | 5417 | else if (i.base_reg->reg_type.bitfield.reg16) |
29b0f896 AM |
5418 | { |
5419 | switch (i.base_reg->reg_num) | |
5420 | { | |
5421 | case 3: /* (%bx) */ | |
5422 | if (i.index_reg == 0) | |
5423 | i.rm.regmem = 7; | |
5424 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
5425 | i.rm.regmem = i.index_reg->reg_num - 6; | |
5426 | break; | |
5427 | case 5: /* (%bp) */ | |
5428 | default_seg = &ss; | |
5429 | if (i.index_reg == 0) | |
5430 | { | |
5431 | i.rm.regmem = 6; | |
40fb9820 | 5432 | if (operand_type_check (i.types[op], disp) == 0) |
29b0f896 AM |
5433 | { |
5434 | /* fake (%bp) into 0(%bp) */ | |
40fb9820 | 5435 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 5436 | fake_zero_displacement = 1; |
29b0f896 AM |
5437 | } |
5438 | } | |
5439 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
5440 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
5441 | break; | |
5442 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
5443 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
5444 | } | |
5445 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
5446 | } | |
5447 | else /* i.base_reg and 32/64 bit mode */ | |
5448 | { | |
5449 | if (flag_code == CODE_64BIT | |
40fb9820 L |
5450 | && operand_type_check (i.types[op], disp)) |
5451 | { | |
5452 | i386_operand_type temp; | |
0dfbf9d7 | 5453 | operand_type_set (&temp, 0); |
40fb9820 L |
5454 | temp.bitfield.disp8 = i.types[op].bitfield.disp8; |
5455 | i.types[op] = temp; | |
5456 | if (i.prefix[ADDR_PREFIX] == 0) | |
5457 | i.types[op].bitfield.disp32s = 1; | |
5458 | else | |
5459 | i.types[op].bitfield.disp32 = 1; | |
5460 | } | |
20f0a1fc | 5461 | |
29b0f896 AM |
5462 | i.rm.regmem = i.base_reg->reg_num; |
5463 | if ((i.base_reg->reg_flags & RegRex) != 0) | |
161a04f6 | 5464 | i.rex |= REX_B; |
29b0f896 AM |
5465 | i.sib.base = i.base_reg->reg_num; |
5466 | /* x86-64 ignores REX prefix bit here to avoid decoder | |
5467 | complications. */ | |
5468 | if ((i.base_reg->reg_num & 7) == EBP_REG_NUM) | |
5469 | { | |
5470 | default_seg = &ss; | |
5471 | if (i.disp_operands == 0) | |
5472 | { | |
5473 | fake_zero_displacement = 1; | |
40fb9820 | 5474 | i.types[op].bitfield.disp8 = 1; |
29b0f896 AM |
5475 | } |
5476 | } | |
5477 | else if (i.base_reg->reg_num == ESP_REG_NUM) | |
5478 | { | |
5479 | default_seg = &ss; | |
5480 | } | |
5481 | i.sib.scale = i.log2_scale_factor; | |
5482 | if (i.index_reg == 0) | |
5483 | { | |
5484 | /* <disp>(%esp) becomes two byte modrm with no index | |
5485 | register. We've already stored the code for esp | |
5486 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. | |
5487 | Any base register besides %esp will not use the | |
5488 | extra modrm byte. */ | |
5489 | i.sib.index = NO_INDEX_REGISTER; | |
29b0f896 AM |
5490 | } |
5491 | else | |
5492 | { | |
db51cc60 L |
5493 | if (i.index_reg->reg_num == RegEiz |
5494 | || i.index_reg->reg_num == RegRiz) | |
5495 | i.sib.index = NO_INDEX_REGISTER; | |
5496 | else | |
5497 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
5498 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
5499 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
161a04f6 | 5500 | i.rex |= REX_X; |
29b0f896 | 5501 | } |
67a4f2b7 AO |
5502 | |
5503 | if (i.disp_operands | |
5504 | && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL | |
5505 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) | |
5506 | i.rm.mode = 0; | |
5507 | else | |
5508 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
29b0f896 | 5509 | } |
252b5132 | 5510 | |
29b0f896 AM |
5511 | if (fake_zero_displacement) |
5512 | { | |
5513 | /* Fakes a zero displacement assuming that i.types[op] | |
5514 | holds the correct displacement size. */ | |
5515 | expressionS *exp; | |
5516 | ||
5517 | assert (i.op[op].disps == 0); | |
5518 | exp = &disp_expressions[i.disp_operands++]; | |
5519 | i.op[op].disps = exp; | |
5520 | exp->X_op = O_constant; | |
5521 | exp->X_add_number = 0; | |
5522 | exp->X_add_symbol = (symbolS *) 0; | |
5523 | exp->X_op_symbol = (symbolS *) 0; | |
5524 | } | |
c0f3af97 L |
5525 | |
5526 | mem = op; | |
29b0f896 | 5527 | } |
c0f3af97 L |
5528 | else |
5529 | mem = ~0; | |
252b5132 | 5530 | |
29b0f896 AM |
5531 | /* Fill in i.rm.reg or i.rm.regmem field with register operand |
5532 | (if any) based on i.tm.extension_opcode. Again, we must be | |
5533 | careful to make sure that segment/control/debug/test/MMX | |
5534 | registers are coded into the i.rm.reg field. */ | |
5535 | if (i.reg_operands) | |
5536 | { | |
99018f42 L |
5537 | unsigned int op; |
5538 | ||
85f10a01 MM |
5539 | /* This has been precalculated for SSE5 instructions |
5540 | that have a DREX field earlier in process_drex. */ | |
b5016f89 L |
5541 | if (i.tm.opcode_modifier.drex |
5542 | || i.tm.opcode_modifier.drexv | |
5543 | || i.tm.opcode_modifier.drexc) | |
85f10a01 MM |
5544 | { |
5545 | op = i.drex.modrm_reg; | |
5546 | i.rm.reg = i.op[op].regs->reg_num; | |
5547 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
5548 | i.rex |= REX_R; | |
5549 | } | |
5550 | else | |
5551 | { | |
c0f3af97 L |
5552 | unsigned int vex_reg = ~0; |
5553 | ||
c0209578 L |
5554 | for (op = 0; op < i.operands; op++) |
5555 | if (i.types[op].bitfield.reg8 | |
5556 | || i.types[op].bitfield.reg16 | |
5557 | || i.types[op].bitfield.reg32 | |
5558 | || i.types[op].bitfield.reg64 | |
5559 | || i.types[op].bitfield.regmmx | |
5560 | || i.types[op].bitfield.regxmm | |
c0f3af97 | 5561 | || i.types[op].bitfield.regymm |
c0209578 L |
5562 | || i.types[op].bitfield.sreg2 |
5563 | || i.types[op].bitfield.sreg3 | |
5564 | || i.types[op].bitfield.control | |
5565 | || i.types[op].bitfield.debug | |
5566 | || i.types[op].bitfield.test) | |
5567 | break; | |
5568 | ||
c0f3af97 L |
5569 | if (vex_3_sources) |
5570 | op = dest; | |
5571 | else if (i.tm.opcode_modifier.vexnds) | |
5572 | { | |
5573 | /* For instructions with VexNDS, the register-only | |
5574 | source operand is encoded in VEX prefix. */ | |
5575 | assert (mem != (unsigned int) ~0); | |
5576 | ||
5577 | if (op > mem) | |
5578 | { | |
5579 | vex_reg = op++; | |
5580 | assert (op < i.operands); | |
5581 | } | |
5582 | else | |
5583 | { | |
5584 | vex_reg = op + 1; | |
5585 | assert (vex_reg < i.operands); | |
5586 | } | |
5587 | } | |
5588 | else if (i.tm.opcode_modifier.vexndd) | |
5589 | { | |
5590 | /* For instructions with VexNDD, there should be | |
5591 | no memory operand and the register destination | |
5592 | is encoded in VEX prefix. */ | |
5593 | assert (i.mem_operands == 0 | |
5594 | && (op + 2) == i.operands); | |
5595 | vex_reg = op + 1; | |
5596 | } | |
5597 | else | |
5598 | assert (op < i.operands); | |
5599 | ||
5600 | if (vex_reg != (unsigned int) ~0) | |
5601 | { | |
5602 | assert (i.reg_operands == 2); | |
5603 | ||
5604 | if (!operand_type_equal (&i.tm.operand_types[vex_reg], | |
5605 | & regxmm) | |
5606 | && !operand_type_equal (&i.tm.operand_types[vex_reg], | |
5607 | ®ymm)) | |
5608 | abort (); | |
5609 | i.vex.register_specifier = i.op[vex_reg].regs; | |
5610 | } | |
99018f42 | 5611 | |
85f10a01 MM |
5612 | /* If there is an extension opcode to put here, the |
5613 | register number must be put into the regmem field. */ | |
c0209578 L |
5614 | if (i.tm.extension_opcode != None) |
5615 | { | |
5616 | i.rm.regmem = i.op[op].regs->reg_num; | |
5617 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
5618 | i.rex |= REX_B; | |
5619 | } | |
5620 | else | |
5621 | { | |
5622 | i.rm.reg = i.op[op].regs->reg_num; | |
5623 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
5624 | i.rex |= REX_R; | |
5625 | } | |
85f10a01 | 5626 | } |
252b5132 | 5627 | |
29b0f896 AM |
5628 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we |
5629 | must set it to 3 to indicate this is a register operand | |
5630 | in the regmem field. */ | |
5631 | if (!i.mem_operands) | |
5632 | i.rm.mode = 3; | |
5633 | } | |
252b5132 | 5634 | |
29b0f896 | 5635 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
85f10a01 MM |
5636 | if (i.tm.extension_opcode != None |
5637 | && !(i.tm.opcode_modifier.drex | |
5638 | || i.tm.opcode_modifier.drexv | |
5639 | || i.tm.opcode_modifier.drexc)) | |
29b0f896 AM |
5640 | i.rm.reg = i.tm.extension_opcode; |
5641 | } | |
5642 | return default_seg; | |
5643 | } | |
252b5132 | 5644 | |
29b0f896 | 5645 | static void |
e3bb37b5 | 5646 | output_branch (void) |
29b0f896 AM |
5647 | { |
5648 | char *p; | |
5649 | int code16; | |
5650 | int prefix; | |
5651 | relax_substateT subtype; | |
5652 | symbolS *sym; | |
5653 | offsetT off; | |
5654 | ||
5655 | code16 = 0; | |
5656 | if (flag_code == CODE_16BIT) | |
5657 | code16 = CODE16; | |
5658 | ||
5659 | prefix = 0; | |
5660 | if (i.prefix[DATA_PREFIX] != 0) | |
252b5132 | 5661 | { |
29b0f896 AM |
5662 | prefix = 1; |
5663 | i.prefixes -= 1; | |
5664 | code16 ^= CODE16; | |
252b5132 | 5665 | } |
29b0f896 AM |
5666 | /* Pentium4 branch hints. */ |
5667 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
5668 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2f66722d | 5669 | { |
29b0f896 AM |
5670 | prefix++; |
5671 | i.prefixes--; | |
5672 | } | |
5673 | if (i.prefix[REX_PREFIX] != 0) | |
5674 | { | |
5675 | prefix++; | |
5676 | i.prefixes--; | |
2f66722d AM |
5677 | } |
5678 | ||
29b0f896 AM |
5679 | if (i.prefixes != 0 && !intel_syntax) |
5680 | as_warn (_("skipping prefixes on this instruction")); | |
5681 | ||
5682 | /* It's always a symbol; End frag & setup for relax. | |
5683 | Make sure there is enough room in this frag for the largest | |
5684 | instruction we may generate in md_convert_frag. This is 2 | |
5685 | bytes for the opcode and room for the prefix and largest | |
5686 | displacement. */ | |
5687 | frag_grow (prefix + 2 + 4); | |
5688 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
5689 | p = frag_more (prefix + 1); | |
5690 | if (i.prefix[DATA_PREFIX] != 0) | |
5691 | *p++ = DATA_PREFIX_OPCODE; | |
5692 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE | |
5693 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
5694 | *p++ = i.prefix[SEG_PREFIX]; | |
5695 | if (i.prefix[REX_PREFIX] != 0) | |
5696 | *p++ = i.prefix[REX_PREFIX]; | |
5697 | *p = i.tm.base_opcode; | |
5698 | ||
5699 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
5700 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL); | |
40fb9820 | 5701 | else if (cpu_arch_flags.bitfield.cpui386) |
29b0f896 AM |
5702 | subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL); |
5703 | else | |
5704 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL); | |
5705 | subtype |= code16; | |
3e73aa7c | 5706 | |
29b0f896 AM |
5707 | sym = i.op[0].disps->X_add_symbol; |
5708 | off = i.op[0].disps->X_add_number; | |
3e73aa7c | 5709 | |
29b0f896 AM |
5710 | if (i.op[0].disps->X_op != O_constant |
5711 | && i.op[0].disps->X_op != O_symbol) | |
3e73aa7c | 5712 | { |
29b0f896 AM |
5713 | /* Handle complex expressions. */ |
5714 | sym = make_expr_symbol (i.op[0].disps); | |
5715 | off = 0; | |
5716 | } | |
3e73aa7c | 5717 | |
29b0f896 AM |
5718 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
5719 | Pass reloc in fr_var. */ | |
5720 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); | |
5721 | } | |
3e73aa7c | 5722 | |
29b0f896 | 5723 | static void |
e3bb37b5 | 5724 | output_jump (void) |
29b0f896 AM |
5725 | { |
5726 | char *p; | |
5727 | int size; | |
3e02c1cc | 5728 | fixS *fixP; |
29b0f896 | 5729 | |
40fb9820 | 5730 | if (i.tm.opcode_modifier.jumpbyte) |
29b0f896 AM |
5731 | { |
5732 | /* This is a loop or jecxz type instruction. */ | |
5733 | size = 1; | |
5734 | if (i.prefix[ADDR_PREFIX] != 0) | |
5735 | { | |
5736 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); | |
5737 | i.prefixes -= 1; | |
5738 | } | |
5739 | /* Pentium4 branch hints. */ | |
5740 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
5741 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
5742 | { | |
5743 | FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); | |
5744 | i.prefixes--; | |
3e73aa7c JH |
5745 | } |
5746 | } | |
29b0f896 AM |
5747 | else |
5748 | { | |
5749 | int code16; | |
3e73aa7c | 5750 | |
29b0f896 AM |
5751 | code16 = 0; |
5752 | if (flag_code == CODE_16BIT) | |
5753 | code16 = CODE16; | |
3e73aa7c | 5754 | |
29b0f896 AM |
5755 | if (i.prefix[DATA_PREFIX] != 0) |
5756 | { | |
5757 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); | |
5758 | i.prefixes -= 1; | |
5759 | code16 ^= CODE16; | |
5760 | } | |
252b5132 | 5761 | |
29b0f896 AM |
5762 | size = 4; |
5763 | if (code16) | |
5764 | size = 2; | |
5765 | } | |
9fcc94b6 | 5766 | |
29b0f896 AM |
5767 | if (i.prefix[REX_PREFIX] != 0) |
5768 | { | |
5769 | FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); | |
5770 | i.prefixes -= 1; | |
5771 | } | |
252b5132 | 5772 | |
29b0f896 AM |
5773 | if (i.prefixes != 0 && !intel_syntax) |
5774 | as_warn (_("skipping prefixes on this instruction")); | |
e0890092 | 5775 | |
29b0f896 AM |
5776 | p = frag_more (1 + size); |
5777 | *p++ = i.tm.base_opcode; | |
e0890092 | 5778 | |
3e02c1cc AM |
5779 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
5780 | i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0])); | |
5781 | ||
5782 | /* All jumps handled here are signed, but don't use a signed limit | |
5783 | check for 32 and 16 bit jumps as we want to allow wrap around at | |
5784 | 4G and 64k respectively. */ | |
5785 | if (size == 1) | |
5786 | fixP->fx_signed = 1; | |
29b0f896 | 5787 | } |
e0890092 | 5788 | |
29b0f896 | 5789 | static void |
e3bb37b5 | 5790 | output_interseg_jump (void) |
29b0f896 AM |
5791 | { |
5792 | char *p; | |
5793 | int size; | |
5794 | int prefix; | |
5795 | int code16; | |
252b5132 | 5796 | |
29b0f896 AM |
5797 | code16 = 0; |
5798 | if (flag_code == CODE_16BIT) | |
5799 | code16 = CODE16; | |
a217f122 | 5800 | |
29b0f896 AM |
5801 | prefix = 0; |
5802 | if (i.prefix[DATA_PREFIX] != 0) | |
5803 | { | |
5804 | prefix = 1; | |
5805 | i.prefixes -= 1; | |
5806 | code16 ^= CODE16; | |
5807 | } | |
5808 | if (i.prefix[REX_PREFIX] != 0) | |
5809 | { | |
5810 | prefix++; | |
5811 | i.prefixes -= 1; | |
5812 | } | |
252b5132 | 5813 | |
29b0f896 AM |
5814 | size = 4; |
5815 | if (code16) | |
5816 | size = 2; | |
252b5132 | 5817 | |
29b0f896 AM |
5818 | if (i.prefixes != 0 && !intel_syntax) |
5819 | as_warn (_("skipping prefixes on this instruction")); | |
252b5132 | 5820 | |
29b0f896 AM |
5821 | /* 1 opcode; 2 segment; offset */ |
5822 | p = frag_more (prefix + 1 + 2 + size); | |
3e73aa7c | 5823 | |
29b0f896 AM |
5824 | if (i.prefix[DATA_PREFIX] != 0) |
5825 | *p++ = DATA_PREFIX_OPCODE; | |
252b5132 | 5826 | |
29b0f896 AM |
5827 | if (i.prefix[REX_PREFIX] != 0) |
5828 | *p++ = i.prefix[REX_PREFIX]; | |
252b5132 | 5829 | |
29b0f896 AM |
5830 | *p++ = i.tm.base_opcode; |
5831 | if (i.op[1].imms->X_op == O_constant) | |
5832 | { | |
5833 | offsetT n = i.op[1].imms->X_add_number; | |
252b5132 | 5834 | |
29b0f896 AM |
5835 | if (size == 2 |
5836 | && !fits_in_unsigned_word (n) | |
5837 | && !fits_in_signed_word (n)) | |
5838 | { | |
5839 | as_bad (_("16-bit jump out of range")); | |
5840 | return; | |
5841 | } | |
5842 | md_number_to_chars (p, n, size); | |
5843 | } | |
5844 | else | |
5845 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
5846 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); | |
5847 | if (i.op[0].imms->X_op != O_constant) | |
5848 | as_bad (_("can't handle non absolute segment in `%s'"), | |
5849 | i.tm.name); | |
5850 | md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); | |
5851 | } | |
a217f122 | 5852 | |
29b0f896 | 5853 | static void |
e3bb37b5 | 5854 | output_insn (void) |
29b0f896 | 5855 | { |
2bbd9c25 JJ |
5856 | fragS *insn_start_frag; |
5857 | offsetT insn_start_off; | |
5858 | ||
29b0f896 AM |
5859 | /* Tie dwarf2 debug info to the address at the start of the insn. |
5860 | We can't do this after the insn has been output as the current | |
5861 | frag may have been closed off. eg. by frag_var. */ | |
5862 | dwarf2_emit_insn (0); | |
5863 | ||
2bbd9c25 JJ |
5864 | insn_start_frag = frag_now; |
5865 | insn_start_off = frag_now_fix (); | |
5866 | ||
29b0f896 | 5867 | /* Output jumps. */ |
40fb9820 | 5868 | if (i.tm.opcode_modifier.jump) |
29b0f896 | 5869 | output_branch (); |
40fb9820 L |
5870 | else if (i.tm.opcode_modifier.jumpbyte |
5871 | || i.tm.opcode_modifier.jumpdword) | |
29b0f896 | 5872 | output_jump (); |
40fb9820 | 5873 | else if (i.tm.opcode_modifier.jumpintersegment) |
29b0f896 AM |
5874 | output_interseg_jump (); |
5875 | else | |
5876 | { | |
5877 | /* Output normal instructions here. */ | |
5878 | char *p; | |
5879 | unsigned char *q; | |
47465058 | 5880 | unsigned int j; |
331d2d0d | 5881 | unsigned int prefix; |
4dffcebc | 5882 | |
c0f3af97 L |
5883 | /* Since the VEX prefix contains the implicit prefix, we don't |
5884 | need the explicit prefix. */ | |
5885 | if (!i.tm.opcode_modifier.vex) | |
bc4bd9ab | 5886 | { |
c0f3af97 | 5887 | switch (i.tm.opcode_length) |
bc4bd9ab | 5888 | { |
c0f3af97 L |
5889 | case 3: |
5890 | if (i.tm.base_opcode & 0xff000000) | |
4dffcebc | 5891 | { |
c0f3af97 L |
5892 | prefix = (i.tm.base_opcode >> 24) & 0xff; |
5893 | goto check_prefix; | |
5894 | } | |
5895 | break; | |
5896 | case 2: | |
5897 | if ((i.tm.base_opcode & 0xff0000) != 0) | |
5898 | { | |
5899 | prefix = (i.tm.base_opcode >> 16) & 0xff; | |
5900 | if (i.tm.cpu_flags.bitfield.cpupadlock) | |
5901 | { | |
4dffcebc | 5902 | check_prefix: |
c0f3af97 L |
5903 | if (prefix != REPE_PREFIX_OPCODE |
5904 | || (i.prefix[LOCKREP_PREFIX] | |
5905 | != REPE_PREFIX_OPCODE)) | |
5906 | add_prefix (prefix); | |
5907 | } | |
5908 | else | |
4dffcebc L |
5909 | add_prefix (prefix); |
5910 | } | |
c0f3af97 L |
5911 | break; |
5912 | case 1: | |
5913 | break; | |
5914 | default: | |
5915 | abort (); | |
bc4bd9ab | 5916 | } |
c0f3af97 L |
5917 | |
5918 | /* The prefix bytes. */ | |
5919 | for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) | |
5920 | if (*q) | |
5921 | FRAG_APPEND_1_CHAR (*q); | |
0f10071e | 5922 | } |
252b5132 | 5923 | |
c0f3af97 L |
5924 | if (i.tm.opcode_modifier.vex) |
5925 | { | |
5926 | for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++) | |
5927 | if (*q) | |
5928 | switch (j) | |
5929 | { | |
5930 | case REX_PREFIX: | |
5931 | /* REX byte is encoded in VEX prefix. */ | |
5932 | break; | |
5933 | case SEG_PREFIX: | |
5934 | case ADDR_PREFIX: | |
5935 | FRAG_APPEND_1_CHAR (*q); | |
5936 | break; | |
5937 | default: | |
5938 | /* There should be no other prefixes for instructions | |
5939 | with VEX prefix. */ | |
5940 | abort (); | |
5941 | } | |
5942 | ||
5943 | /* Now the VEX prefix. */ | |
5944 | p = frag_more (i.vex.length); | |
5945 | for (j = 0; j < i.vex.length; j++) | |
5946 | p[j] = i.vex.bytes[j]; | |
5947 | } | |
252b5132 | 5948 | |
29b0f896 | 5949 | /* Now the opcode; be careful about word order here! */ |
4dffcebc | 5950 | if (i.tm.opcode_length == 1) |
29b0f896 AM |
5951 | { |
5952 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
5953 | } | |
5954 | else | |
5955 | { | |
4dffcebc | 5956 | switch (i.tm.opcode_length) |
331d2d0d | 5957 | { |
4dffcebc | 5958 | case 3: |
331d2d0d L |
5959 | p = frag_more (3); |
5960 | *p++ = (i.tm.base_opcode >> 16) & 0xff; | |
4dffcebc L |
5961 | break; |
5962 | case 2: | |
5963 | p = frag_more (2); | |
5964 | break; | |
5965 | default: | |
5966 | abort (); | |
5967 | break; | |
331d2d0d | 5968 | } |
0f10071e | 5969 | |
29b0f896 AM |
5970 | /* Put out high byte first: can't use md_number_to_chars! */ |
5971 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
5972 | *p = i.tm.base_opcode & 0xff; | |
85f10a01 MM |
5973 | |
5974 | /* On SSE5, encode the OC1 bit in the DREX field if this | |
5975 | encoding has multiple formats. */ | |
5976 | if (i.tm.opcode_modifier.drex | |
5977 | && i.tm.opcode_modifier.drexv | |
5978 | && DREX_OC1 (i.tm.extension_opcode)) | |
5979 | *p |= DREX_OC1_MASK; | |
29b0f896 | 5980 | } |
3e73aa7c | 5981 | |
29b0f896 | 5982 | /* Now the modrm byte and sib byte (if present). */ |
40fb9820 | 5983 | if (i.tm.opcode_modifier.modrm) |
29b0f896 | 5984 | { |
4a3523fa L |
5985 | FRAG_APPEND_1_CHAR ((i.rm.regmem << 0 |
5986 | | i.rm.reg << 3 | |
5987 | | i.rm.mode << 6)); | |
29b0f896 AM |
5988 | /* If i.rm.regmem == ESP (4) |
5989 | && i.rm.mode != (Register mode) | |
5990 | && not 16 bit | |
5991 | ==> need second modrm byte. */ | |
5992 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
5993 | && i.rm.mode != 3 | |
40fb9820 | 5994 | && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16)) |
4a3523fa L |
5995 | FRAG_APPEND_1_CHAR ((i.sib.base << 0 |
5996 | | i.sib.index << 3 | |
5997 | | i.sib.scale << 6)); | |
29b0f896 | 5998 | } |
3e73aa7c | 5999 | |
85f10a01 MM |
6000 | /* Write the DREX byte if needed. */ |
6001 | if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc) | |
6002 | { | |
6003 | p = frag_more (1); | |
6004 | *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7)); | |
6005 | ||
6006 | /* Encode the OC0 bit if this encoding has multiple | |
6007 | formats. */ | |
6008 | if ((i.tm.opcode_modifier.drex | |
6009 | || i.tm.opcode_modifier.drexv) | |
6010 | && DREX_OC0 (i.tm.extension_opcode)) | |
6011 | *p |= DREX_OC0_MASK; | |
6012 | } | |
6013 | ||
29b0f896 | 6014 | if (i.disp_operands) |
2bbd9c25 | 6015 | output_disp (insn_start_frag, insn_start_off); |
3e73aa7c | 6016 | |
29b0f896 | 6017 | if (i.imm_operands) |
2bbd9c25 | 6018 | output_imm (insn_start_frag, insn_start_off); |
29b0f896 | 6019 | } |
252b5132 | 6020 | |
29b0f896 AM |
6021 | #ifdef DEBUG386 |
6022 | if (flag_debug) | |
6023 | { | |
7b81dfbb | 6024 | pi ("" /*line*/, &i); |
29b0f896 AM |
6025 | } |
6026 | #endif /* DEBUG386 */ | |
6027 | } | |
252b5132 | 6028 | |
e205caa7 L |
6029 | /* Return the size of the displacement operand N. */ |
6030 | ||
6031 | static int | |
6032 | disp_size (unsigned int n) | |
6033 | { | |
6034 | int size = 4; | |
40fb9820 L |
6035 | if (i.types[n].bitfield.disp64) |
6036 | size = 8; | |
6037 | else if (i.types[n].bitfield.disp8) | |
6038 | size = 1; | |
6039 | else if (i.types[n].bitfield.disp16) | |
6040 | size = 2; | |
e205caa7 L |
6041 | return size; |
6042 | } | |
6043 | ||
6044 | /* Return the size of the immediate operand N. */ | |
6045 | ||
6046 | static int | |
6047 | imm_size (unsigned int n) | |
6048 | { | |
6049 | int size = 4; | |
40fb9820 L |
6050 | if (i.types[n].bitfield.imm64) |
6051 | size = 8; | |
6052 | else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) | |
6053 | size = 1; | |
6054 | else if (i.types[n].bitfield.imm16) | |
6055 | size = 2; | |
e205caa7 L |
6056 | return size; |
6057 | } | |
6058 | ||
29b0f896 | 6059 | static void |
64e74474 | 6060 | output_disp (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
6061 | { |
6062 | char *p; | |
6063 | unsigned int n; | |
252b5132 | 6064 | |
29b0f896 AM |
6065 | for (n = 0; n < i.operands; n++) |
6066 | { | |
40fb9820 | 6067 | if (operand_type_check (i.types[n], disp)) |
29b0f896 AM |
6068 | { |
6069 | if (i.op[n].disps->X_op == O_constant) | |
6070 | { | |
e205caa7 | 6071 | int size = disp_size (n); |
29b0f896 | 6072 | offsetT val; |
252b5132 | 6073 | |
29b0f896 AM |
6074 | val = offset_in_range (i.op[n].disps->X_add_number, |
6075 | size); | |
6076 | p = frag_more (size); | |
6077 | md_number_to_chars (p, val, size); | |
6078 | } | |
6079 | else | |
6080 | { | |
f86103b7 | 6081 | enum bfd_reloc_code_real reloc_type; |
e205caa7 | 6082 | int size = disp_size (n); |
40fb9820 | 6083 | int sign = i.types[n].bitfield.disp32s; |
29b0f896 AM |
6084 | int pcrel = (i.flags[n] & Operand_PCrel) != 0; |
6085 | ||
e205caa7 | 6086 | /* We can't have 8 bit displacement here. */ |
40fb9820 | 6087 | assert (!i.types[n].bitfield.disp8); |
e205caa7 | 6088 | |
29b0f896 AM |
6089 | /* The PC relative address is computed relative |
6090 | to the instruction boundary, so in case immediate | |
6091 | fields follows, we need to adjust the value. */ | |
6092 | if (pcrel && i.imm_operands) | |
6093 | { | |
29b0f896 | 6094 | unsigned int n1; |
e205caa7 | 6095 | int sz = 0; |
252b5132 | 6096 | |
29b0f896 | 6097 | for (n1 = 0; n1 < i.operands; n1++) |
40fb9820 | 6098 | if (operand_type_check (i.types[n1], imm)) |
252b5132 | 6099 | { |
e205caa7 L |
6100 | /* Only one immediate is allowed for PC |
6101 | relative address. */ | |
6102 | assert (sz == 0); | |
6103 | sz = imm_size (n1); | |
6104 | i.op[n].disps->X_add_number -= sz; | |
252b5132 | 6105 | } |
29b0f896 | 6106 | /* We should find the immediate. */ |
e205caa7 | 6107 | assert (sz != 0); |
29b0f896 | 6108 | } |
520dc8e8 | 6109 | |
29b0f896 | 6110 | p = frag_more (size); |
2bbd9c25 | 6111 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
d6ab8113 | 6112 | if (GOT_symbol |
2bbd9c25 | 6113 | && GOT_symbol == i.op[n].disps->X_add_symbol |
d6ab8113 | 6114 | && (((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
6115 | || reloc_type == BFD_RELOC_X86_64_32S |
6116 | || (reloc_type == BFD_RELOC_64 | |
6117 | && object_64bit)) | |
d6ab8113 JB |
6118 | && (i.op[n].disps->X_op == O_symbol |
6119 | || (i.op[n].disps->X_op == O_add | |
6120 | && ((symbol_get_value_expression | |
6121 | (i.op[n].disps->X_op_symbol)->X_op) | |
6122 | == O_subtract)))) | |
6123 | || reloc_type == BFD_RELOC_32_PCREL)) | |
2bbd9c25 JJ |
6124 | { |
6125 | offsetT add; | |
6126 | ||
6127 | if (insn_start_frag == frag_now) | |
6128 | add = (p - frag_now->fr_literal) - insn_start_off; | |
6129 | else | |
6130 | { | |
6131 | fragS *fr; | |
6132 | ||
6133 | add = insn_start_frag->fr_fix - insn_start_off; | |
6134 | for (fr = insn_start_frag->fr_next; | |
6135 | fr && fr != frag_now; fr = fr->fr_next) | |
6136 | add += fr->fr_fix; | |
6137 | add += p - frag_now->fr_literal; | |
6138 | } | |
6139 | ||
4fa24527 | 6140 | if (!object_64bit) |
7b81dfbb AJ |
6141 | { |
6142 | reloc_type = BFD_RELOC_386_GOTPC; | |
6143 | i.op[n].imms->X_add_number += add; | |
6144 | } | |
6145 | else if (reloc_type == BFD_RELOC_64) | |
6146 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
d6ab8113 | 6147 | else |
7b81dfbb AJ |
6148 | /* Don't do the adjustment for x86-64, as there |
6149 | the pcrel addressing is relative to the _next_ | |
6150 | insn, and that is taken care of in other code. */ | |
d6ab8113 | 6151 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
2bbd9c25 | 6152 | } |
062cd5e7 | 6153 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
2bbd9c25 | 6154 | i.op[n].disps, pcrel, reloc_type); |
29b0f896 AM |
6155 | } |
6156 | } | |
6157 | } | |
6158 | } | |
252b5132 | 6159 | |
29b0f896 | 6160 | static void |
64e74474 | 6161 | output_imm (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
6162 | { |
6163 | char *p; | |
6164 | unsigned int n; | |
252b5132 | 6165 | |
29b0f896 AM |
6166 | for (n = 0; n < i.operands; n++) |
6167 | { | |
40fb9820 | 6168 | if (operand_type_check (i.types[n], imm)) |
29b0f896 AM |
6169 | { |
6170 | if (i.op[n].imms->X_op == O_constant) | |
6171 | { | |
e205caa7 | 6172 | int size = imm_size (n); |
29b0f896 | 6173 | offsetT val; |
b4cac588 | 6174 | |
29b0f896 AM |
6175 | val = offset_in_range (i.op[n].imms->X_add_number, |
6176 | size); | |
6177 | p = frag_more (size); | |
6178 | md_number_to_chars (p, val, size); | |
6179 | } | |
6180 | else | |
6181 | { | |
6182 | /* Not absolute_section. | |
6183 | Need a 32-bit fixup (don't support 8bit | |
6184 | non-absolute imms). Try to support other | |
6185 | sizes ... */ | |
f86103b7 | 6186 | enum bfd_reloc_code_real reloc_type; |
e205caa7 L |
6187 | int size = imm_size (n); |
6188 | int sign; | |
29b0f896 | 6189 | |
40fb9820 | 6190 | if (i.types[n].bitfield.imm32s |
a7d61044 | 6191 | && (i.suffix == QWORD_MNEM_SUFFIX |
40fb9820 | 6192 | || (!i.suffix && i.tm.opcode_modifier.no_lsuf))) |
29b0f896 | 6193 | sign = 1; |
e205caa7 L |
6194 | else |
6195 | sign = 0; | |
520dc8e8 | 6196 | |
29b0f896 AM |
6197 | p = frag_more (size); |
6198 | reloc_type = reloc (size, 0, sign, i.reloc[n]); | |
f86103b7 | 6199 | |
2bbd9c25 JJ |
6200 | /* This is tough to explain. We end up with this one if we |
6201 | * have operands that look like | |
6202 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to | |
6203 | * obtain the absolute address of the GOT, and it is strongly | |
6204 | * preferable from a performance point of view to avoid using | |
6205 | * a runtime relocation for this. The actual sequence of | |
6206 | * instructions often look something like: | |
6207 | * | |
6208 | * call .L66 | |
6209 | * .L66: | |
6210 | * popl %ebx | |
6211 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
6212 | * | |
6213 | * The call and pop essentially return the absolute address | |
6214 | * of the label .L66 and store it in %ebx. The linker itself | |
6215 | * will ultimately change the first operand of the addl so | |
6216 | * that %ebx points to the GOT, but to keep things simple, the | |
6217 | * .o file must have this operand set so that it generates not | |
6218 | * the absolute address of .L66, but the absolute address of | |
6219 | * itself. This allows the linker itself simply treat a GOTPC | |
6220 | * relocation as asking for a pcrel offset to the GOT to be | |
6221 | * added in, and the addend of the relocation is stored in the | |
6222 | * operand field for the instruction itself. | |
6223 | * | |
6224 | * Our job here is to fix the operand so that it would add | |
6225 | * the correct offset so that %ebx would point to itself. The | |
6226 | * thing that is tricky is that .-.L66 will point to the | |
6227 | * beginning of the instruction, so we need to further modify | |
6228 | * the operand so that it will point to itself. There are | |
6229 | * other cases where you have something like: | |
6230 | * | |
6231 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
6232 | * | |
6233 | * and here no correction would be required. Internally in | |
6234 | * the assembler we treat operands of this form as not being | |
6235 | * pcrel since the '.' is explicitly mentioned, and I wonder | |
6236 | * whether it would simplify matters to do it this way. Who | |
6237 | * knows. In earlier versions of the PIC patches, the | |
6238 | * pcrel_adjust field was used to store the correction, but | |
6239 | * since the expression is not pcrel, I felt it would be | |
6240 | * confusing to do it this way. */ | |
6241 | ||
d6ab8113 | 6242 | if ((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
6243 | || reloc_type == BFD_RELOC_X86_64_32S |
6244 | || reloc_type == BFD_RELOC_64) | |
29b0f896 AM |
6245 | && GOT_symbol |
6246 | && GOT_symbol == i.op[n].imms->X_add_symbol | |
6247 | && (i.op[n].imms->X_op == O_symbol | |
6248 | || (i.op[n].imms->X_op == O_add | |
6249 | && ((symbol_get_value_expression | |
6250 | (i.op[n].imms->X_op_symbol)->X_op) | |
6251 | == O_subtract)))) | |
6252 | { | |
2bbd9c25 JJ |
6253 | offsetT add; |
6254 | ||
6255 | if (insn_start_frag == frag_now) | |
6256 | add = (p - frag_now->fr_literal) - insn_start_off; | |
6257 | else | |
6258 | { | |
6259 | fragS *fr; | |
6260 | ||
6261 | add = insn_start_frag->fr_fix - insn_start_off; | |
6262 | for (fr = insn_start_frag->fr_next; | |
6263 | fr && fr != frag_now; fr = fr->fr_next) | |
6264 | add += fr->fr_fix; | |
6265 | add += p - frag_now->fr_literal; | |
6266 | } | |
6267 | ||
4fa24527 | 6268 | if (!object_64bit) |
d6ab8113 | 6269 | reloc_type = BFD_RELOC_386_GOTPC; |
7b81dfbb | 6270 | else if (size == 4) |
d6ab8113 | 6271 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
7b81dfbb AJ |
6272 | else if (size == 8) |
6273 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
2bbd9c25 | 6274 | i.op[n].imms->X_add_number += add; |
29b0f896 | 6275 | } |
29b0f896 AM |
6276 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
6277 | i.op[n].imms, 0, reloc_type); | |
6278 | } | |
6279 | } | |
6280 | } | |
252b5132 RH |
6281 | } |
6282 | \f | |
d182319b JB |
6283 | /* x86_cons_fix_new is called via the expression parsing code when a |
6284 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
6285 | static enum bfd_reloc_code_real got_reloc = NO_RELOC; | |
6286 | static int cons_sign = -1; | |
6287 | ||
6288 | void | |
e3bb37b5 | 6289 | x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, |
64e74474 | 6290 | expressionS *exp) |
d182319b JB |
6291 | { |
6292 | enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc); | |
6293 | ||
6294 | got_reloc = NO_RELOC; | |
6295 | ||
6296 | #ifdef TE_PE | |
6297 | if (exp->X_op == O_secrel) | |
6298 | { | |
6299 | exp->X_op = O_symbol; | |
6300 | r = BFD_RELOC_32_SECREL; | |
6301 | } | |
6302 | #endif | |
6303 | ||
6304 | fix_new_exp (frag, off, len, exp, 0, r); | |
6305 | } | |
6306 | ||
718ddfc0 JB |
6307 | #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT) |
6308 | # define lex_got(reloc, adjust, types) NULL | |
6309 | #else | |
f3c180ae AM |
6310 | /* Parse operands of the form |
6311 | <symbol>@GOTOFF+<nnn> | |
6312 | and similar .plt or .got references. | |
6313 | ||
6314 | If we find one, set up the correct relocation in RELOC and copy the | |
6315 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
6316 | parsing by the calling routine. Return this buffer, and if ADJUST | |
6317 | is non-null set it to the length of the string we removed from the | |
6318 | input line. Otherwise return NULL. */ | |
6319 | static char * | |
3956db08 | 6320 | lex_got (enum bfd_reloc_code_real *reloc, |
64e74474 | 6321 | int *adjust, |
40fb9820 | 6322 | i386_operand_type *types) |
f3c180ae | 6323 | { |
7b81dfbb AJ |
6324 | /* Some of the relocations depend on the size of what field is to |
6325 | be relocated. But in our callers i386_immediate and i386_displacement | |
6326 | we don't yet know the operand size (this will be set by insn | |
6327 | matching). Hence we record the word32 relocation here, | |
6328 | and adjust the reloc according to the real size in reloc(). */ | |
f3c180ae AM |
6329 | static const struct { |
6330 | const char *str; | |
4fa24527 | 6331 | const enum bfd_reloc_code_real rel[2]; |
40fb9820 | 6332 | const i386_operand_type types64; |
f3c180ae | 6333 | } gotrel[] = { |
4eed87de AM |
6334 | { "PLTOFF", { 0, |
6335 | BFD_RELOC_X86_64_PLTOFF64 }, | |
40fb9820 | 6336 | OPERAND_TYPE_IMM64 }, |
4eed87de AM |
6337 | { "PLT", { BFD_RELOC_386_PLT32, |
6338 | BFD_RELOC_X86_64_PLT32 }, | |
40fb9820 | 6339 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
4eed87de AM |
6340 | { "GOTPLT", { 0, |
6341 | BFD_RELOC_X86_64_GOTPLT64 }, | |
40fb9820 | 6342 | OPERAND_TYPE_IMM64_DISP64 }, |
4eed87de AM |
6343 | { "GOTOFF", { BFD_RELOC_386_GOTOFF, |
6344 | BFD_RELOC_X86_64_GOTOFF64 }, | |
40fb9820 | 6345 | OPERAND_TYPE_IMM64_DISP64 }, |
4eed87de AM |
6346 | { "GOTPCREL", { 0, |
6347 | BFD_RELOC_X86_64_GOTPCREL }, | |
40fb9820 | 6348 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
4eed87de AM |
6349 | { "TLSGD", { BFD_RELOC_386_TLS_GD, |
6350 | BFD_RELOC_X86_64_TLSGD }, | |
40fb9820 | 6351 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
4eed87de AM |
6352 | { "TLSLDM", { BFD_RELOC_386_TLS_LDM, |
6353 | 0 }, | |
40fb9820 | 6354 | OPERAND_TYPE_NONE }, |
4eed87de AM |
6355 | { "TLSLD", { 0, |
6356 | BFD_RELOC_X86_64_TLSLD }, | |
40fb9820 | 6357 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
4eed87de AM |
6358 | { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, |
6359 | BFD_RELOC_X86_64_GOTTPOFF }, | |
40fb9820 | 6360 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
4eed87de AM |
6361 | { "TPOFF", { BFD_RELOC_386_TLS_LE_32, |
6362 | BFD_RELOC_X86_64_TPOFF32 }, | |
40fb9820 | 6363 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, |
4eed87de AM |
6364 | { "NTPOFF", { BFD_RELOC_386_TLS_LE, |
6365 | 0 }, | |
40fb9820 | 6366 | OPERAND_TYPE_NONE }, |
4eed87de AM |
6367 | { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, |
6368 | BFD_RELOC_X86_64_DTPOFF32 }, | |
40fb9820 L |
6369 | |
6370 | OPERAND_TYPE_IMM32_32S_64_DISP32_64 }, | |
4eed87de AM |
6371 | { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, |
6372 | 0 }, | |
40fb9820 | 6373 | OPERAND_TYPE_NONE }, |
4eed87de AM |
6374 | { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, |
6375 | 0 }, | |
40fb9820 | 6376 | OPERAND_TYPE_NONE }, |
4eed87de AM |
6377 | { "GOT", { BFD_RELOC_386_GOT32, |
6378 | BFD_RELOC_X86_64_GOT32 }, | |
40fb9820 | 6379 | OPERAND_TYPE_IMM32_32S_64_DISP32 }, |
4eed87de AM |
6380 | { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC, |
6381 | BFD_RELOC_X86_64_GOTPC32_TLSDESC }, | |
40fb9820 | 6382 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
4eed87de AM |
6383 | { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL, |
6384 | BFD_RELOC_X86_64_TLSDESC_CALL }, | |
40fb9820 | 6385 | OPERAND_TYPE_IMM32_32S_DISP32 }, |
f3c180ae AM |
6386 | }; |
6387 | char *cp; | |
6388 | unsigned int j; | |
6389 | ||
718ddfc0 JB |
6390 | if (!IS_ELF) |
6391 | return NULL; | |
6392 | ||
f3c180ae | 6393 | for (cp = input_line_pointer; *cp != '@'; cp++) |
67c11a9b | 6394 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') |
f3c180ae AM |
6395 | return NULL; |
6396 | ||
47465058 | 6397 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) |
f3c180ae AM |
6398 | { |
6399 | int len; | |
6400 | ||
6401 | len = strlen (gotrel[j].str); | |
28f81592 | 6402 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae | 6403 | { |
4fa24527 | 6404 | if (gotrel[j].rel[object_64bit] != 0) |
f3c180ae | 6405 | { |
28f81592 AM |
6406 | int first, second; |
6407 | char *tmpbuf, *past_reloc; | |
f3c180ae | 6408 | |
4fa24527 | 6409 | *reloc = gotrel[j].rel[object_64bit]; |
28f81592 AM |
6410 | if (adjust) |
6411 | *adjust = len; | |
f3c180ae | 6412 | |
3956db08 JB |
6413 | if (types) |
6414 | { | |
6415 | if (flag_code != CODE_64BIT) | |
40fb9820 L |
6416 | { |
6417 | types->bitfield.imm32 = 1; | |
6418 | types->bitfield.disp32 = 1; | |
6419 | } | |
3956db08 JB |
6420 | else |
6421 | *types = gotrel[j].types64; | |
6422 | } | |
6423 | ||
f3c180ae AM |
6424 | if (GOT_symbol == NULL) |
6425 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); | |
6426 | ||
28f81592 | 6427 | /* The length of the first part of our input line. */ |
f3c180ae | 6428 | first = cp - input_line_pointer; |
28f81592 AM |
6429 | |
6430 | /* The second part goes from after the reloc token until | |
67c11a9b | 6431 | (and including) an end_of_line char or comma. */ |
28f81592 | 6432 | past_reloc = cp + 1 + len; |
67c11a9b AM |
6433 | cp = past_reloc; |
6434 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
6435 | ++cp; | |
6436 | second = cp + 1 - past_reloc; | |
28f81592 AM |
6437 | |
6438 | /* Allocate and copy string. The trailing NUL shouldn't | |
6439 | be necessary, but be safe. */ | |
6440 | tmpbuf = xmalloc (first + second + 2); | |
f3c180ae | 6441 | memcpy (tmpbuf, input_line_pointer, first); |
0787a12d AM |
6442 | if (second != 0 && *past_reloc != ' ') |
6443 | /* Replace the relocation token with ' ', so that | |
6444 | errors like foo@GOTOFF1 will be detected. */ | |
6445 | tmpbuf[first++] = ' '; | |
6446 | memcpy (tmpbuf + first, past_reloc, second); | |
6447 | tmpbuf[first + second] = '\0'; | |
f3c180ae AM |
6448 | return tmpbuf; |
6449 | } | |
6450 | ||
4fa24527 JB |
6451 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
6452 | gotrel[j].str, 1 << (5 + object_64bit)); | |
f3c180ae AM |
6453 | return NULL; |
6454 | } | |
6455 | } | |
6456 | ||
6457 | /* Might be a symbol version string. Don't as_bad here. */ | |
6458 | return NULL; | |
6459 | } | |
6460 | ||
f3c180ae | 6461 | void |
e3bb37b5 | 6462 | x86_cons (expressionS *exp, int size) |
f3c180ae | 6463 | { |
4fa24527 | 6464 | if (size == 4 || (object_64bit && size == 8)) |
f3c180ae AM |
6465 | { |
6466 | /* Handle @GOTOFF and the like in an expression. */ | |
6467 | char *save; | |
6468 | char *gotfree_input_line; | |
6469 | int adjust; | |
6470 | ||
6471 | save = input_line_pointer; | |
3956db08 | 6472 | gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); |
f3c180ae AM |
6473 | if (gotfree_input_line) |
6474 | input_line_pointer = gotfree_input_line; | |
6475 | ||
6476 | expression (exp); | |
6477 | ||
6478 | if (gotfree_input_line) | |
6479 | { | |
6480 | /* expression () has merrily parsed up to the end of line, | |
6481 | or a comma - in the wrong buffer. Transfer how far | |
6482 | input_line_pointer has moved to the right buffer. */ | |
6483 | input_line_pointer = (save | |
6484 | + (input_line_pointer - gotfree_input_line) | |
6485 | + adjust); | |
6486 | free (gotfree_input_line); | |
3992d3b7 AM |
6487 | if (exp->X_op == O_constant |
6488 | || exp->X_op == O_absent | |
6489 | || exp->X_op == O_illegal | |
6490 | || exp->X_op == O_register | |
6491 | || exp->X_op == O_big) | |
6492 | { | |
6493 | char c = *input_line_pointer; | |
6494 | *input_line_pointer = 0; | |
6495 | as_bad (_("missing or invalid expression `%s'"), save); | |
6496 | *input_line_pointer = c; | |
6497 | } | |
f3c180ae AM |
6498 | } |
6499 | } | |
6500 | else | |
6501 | expression (exp); | |
6502 | } | |
6503 | #endif | |
6504 | ||
d182319b | 6505 | static void signed_cons (int size) |
6482c264 | 6506 | { |
d182319b JB |
6507 | if (flag_code == CODE_64BIT) |
6508 | cons_sign = 1; | |
6509 | cons (size); | |
6510 | cons_sign = -1; | |
6482c264 NC |
6511 | } |
6512 | ||
d182319b | 6513 | #ifdef TE_PE |
6482c264 NC |
6514 | static void |
6515 | pe_directive_secrel (dummy) | |
6516 | int dummy ATTRIBUTE_UNUSED; | |
6517 | { | |
6518 | expressionS exp; | |
6519 | ||
6520 | do | |
6521 | { | |
6522 | expression (&exp); | |
6523 | if (exp.X_op == O_symbol) | |
6524 | exp.X_op = O_secrel; | |
6525 | ||
6526 | emit_expr (&exp, 4); | |
6527 | } | |
6528 | while (*input_line_pointer++ == ','); | |
6529 | ||
6530 | input_line_pointer--; | |
6531 | demand_empty_rest_of_line (); | |
6532 | } | |
6482c264 NC |
6533 | #endif |
6534 | ||
252b5132 | 6535 | static int |
70e41ade | 6536 | i386_immediate (char *imm_start) |
252b5132 RH |
6537 | { |
6538 | char *save_input_line_pointer; | |
f3c180ae | 6539 | char *gotfree_input_line; |
252b5132 | 6540 | segT exp_seg = 0; |
47926f60 | 6541 | expressionS *exp; |
40fb9820 L |
6542 | i386_operand_type types; |
6543 | ||
0dfbf9d7 | 6544 | operand_type_set (&types, ~0); |
252b5132 RH |
6545 | |
6546 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
6547 | { | |
31b2323c L |
6548 | as_bad (_("at most %d immediate operands are allowed"), |
6549 | MAX_IMMEDIATE_OPERANDS); | |
252b5132 RH |
6550 | return 0; |
6551 | } | |
6552 | ||
6553 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 6554 | i.op[this_operand].imms = exp; |
252b5132 RH |
6555 | |
6556 | if (is_space_char (*imm_start)) | |
6557 | ++imm_start; | |
6558 | ||
6559 | save_input_line_pointer = input_line_pointer; | |
6560 | input_line_pointer = imm_start; | |
6561 | ||
3956db08 | 6562 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
6563 | if (gotfree_input_line) |
6564 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
6565 | |
6566 | exp_seg = expression (exp); | |
6567 | ||
83183c0c | 6568 | SKIP_WHITESPACE (); |
252b5132 | 6569 | if (*input_line_pointer) |
f3c180ae | 6570 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
6571 | |
6572 | input_line_pointer = save_input_line_pointer; | |
f3c180ae AM |
6573 | if (gotfree_input_line) |
6574 | free (gotfree_input_line); | |
252b5132 | 6575 | |
3992d3b7 AM |
6576 | if (exp->X_op == O_absent |
6577 | || exp->X_op == O_illegal | |
6578 | || exp->X_op == O_big | |
6579 | || (gotfree_input_line | |
6580 | && (exp->X_op == O_constant | |
6581 | || exp->X_op == O_register))) | |
252b5132 | 6582 | { |
3992d3b7 | 6583 | as_bad (_("missing or invalid immediate expression `%s'"), |
24eab124 | 6584 | imm_start); |
3992d3b7 | 6585 | return 0; |
252b5132 | 6586 | } |
3e73aa7c | 6587 | else if (exp->X_op == O_constant) |
252b5132 | 6588 | { |
47926f60 | 6589 | /* Size it properly later. */ |
40fb9820 | 6590 | i.types[this_operand].bitfield.imm64 = 1; |
3e73aa7c | 6591 | /* If BFD64, sign extend val. */ |
4eed87de AM |
6592 | if (!use_rela_relocations |
6593 | && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) | |
6594 | exp->X_add_number | |
6595 | = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
252b5132 | 6596 | } |
4c63da97 | 6597 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
f86103b7 | 6598 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 6599 | && exp_seg != absolute_section |
47926f60 | 6600 | && exp_seg != text_section |
24eab124 AM |
6601 | && exp_seg != data_section |
6602 | && exp_seg != bss_section | |
6603 | && exp_seg != undefined_section | |
f86103b7 | 6604 | && !bfd_is_com_section (exp_seg)) |
252b5132 | 6605 | { |
d0b47220 | 6606 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
252b5132 RH |
6607 | return 0; |
6608 | } | |
6609 | #endif | |
bb8f5920 L |
6610 | else if (!intel_syntax && exp->X_op == O_register) |
6611 | { | |
6612 | as_bad (_("illegal immediate register operand %s"), imm_start); | |
6613 | return 0; | |
6614 | } | |
252b5132 RH |
6615 | else |
6616 | { | |
6617 | /* This is an address. The size of the address will be | |
24eab124 | 6618 | determined later, depending on destination register, |
3e73aa7c | 6619 | suffix, or the default for the section. */ |
40fb9820 L |
6620 | i.types[this_operand].bitfield.imm8 = 1; |
6621 | i.types[this_operand].bitfield.imm16 = 1; | |
6622 | i.types[this_operand].bitfield.imm32 = 1; | |
6623 | i.types[this_operand].bitfield.imm32s = 1; | |
6624 | i.types[this_operand].bitfield.imm64 = 1; | |
c6fb90c8 L |
6625 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
6626 | types); | |
252b5132 RH |
6627 | } |
6628 | ||
6629 | return 1; | |
6630 | } | |
6631 | ||
551c1ca1 | 6632 | static char * |
e3bb37b5 | 6633 | i386_scale (char *scale) |
252b5132 | 6634 | { |
551c1ca1 AM |
6635 | offsetT val; |
6636 | char *save = input_line_pointer; | |
252b5132 | 6637 | |
551c1ca1 AM |
6638 | input_line_pointer = scale; |
6639 | val = get_absolute_expression (); | |
6640 | ||
6641 | switch (val) | |
252b5132 | 6642 | { |
551c1ca1 | 6643 | case 1: |
252b5132 RH |
6644 | i.log2_scale_factor = 0; |
6645 | break; | |
551c1ca1 | 6646 | case 2: |
252b5132 RH |
6647 | i.log2_scale_factor = 1; |
6648 | break; | |
551c1ca1 | 6649 | case 4: |
252b5132 RH |
6650 | i.log2_scale_factor = 2; |
6651 | break; | |
551c1ca1 | 6652 | case 8: |
252b5132 RH |
6653 | i.log2_scale_factor = 3; |
6654 | break; | |
6655 | default: | |
a724f0f4 JB |
6656 | { |
6657 | char sep = *input_line_pointer; | |
6658 | ||
6659 | *input_line_pointer = '\0'; | |
6660 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
6661 | scale); | |
6662 | *input_line_pointer = sep; | |
6663 | input_line_pointer = save; | |
6664 | return NULL; | |
6665 | } | |
252b5132 | 6666 | } |
29b0f896 | 6667 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
252b5132 RH |
6668 | { |
6669 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 6670 | 1 << i.log2_scale_factor); |
252b5132 | 6671 | i.log2_scale_factor = 0; |
252b5132 | 6672 | } |
551c1ca1 AM |
6673 | scale = input_line_pointer; |
6674 | input_line_pointer = save; | |
6675 | return scale; | |
252b5132 RH |
6676 | } |
6677 | ||
252b5132 | 6678 | static int |
e3bb37b5 | 6679 | i386_displacement (char *disp_start, char *disp_end) |
252b5132 | 6680 | { |
29b0f896 | 6681 | expressionS *exp; |
252b5132 RH |
6682 | segT exp_seg = 0; |
6683 | char *save_input_line_pointer; | |
f3c180ae | 6684 | char *gotfree_input_line; |
40fb9820 L |
6685 | int override; |
6686 | i386_operand_type bigdisp, types = anydisp; | |
3992d3b7 | 6687 | int ret; |
252b5132 | 6688 | |
31b2323c L |
6689 | if (i.disp_operands == MAX_MEMORY_OPERANDS) |
6690 | { | |
6691 | as_bad (_("at most %d displacement operands are allowed"), | |
6692 | MAX_MEMORY_OPERANDS); | |
6693 | return 0; | |
6694 | } | |
6695 | ||
0dfbf9d7 | 6696 | operand_type_set (&bigdisp, 0); |
40fb9820 L |
6697 | if ((i.types[this_operand].bitfield.jumpabsolute) |
6698 | || (!current_templates->start->opcode_modifier.jump | |
6699 | && !current_templates->start->opcode_modifier.jumpdword)) | |
e05278af | 6700 | { |
40fb9820 | 6701 | bigdisp.bitfield.disp32 = 1; |
e05278af | 6702 | override = (i.prefix[ADDR_PREFIX] != 0); |
40fb9820 L |
6703 | if (flag_code == CODE_64BIT) |
6704 | { | |
6705 | if (!override) | |
6706 | { | |
6707 | bigdisp.bitfield.disp32s = 1; | |
6708 | bigdisp.bitfield.disp64 = 1; | |
6709 | } | |
6710 | } | |
6711 | else if ((flag_code == CODE_16BIT) ^ override) | |
6712 | { | |
6713 | bigdisp.bitfield.disp32 = 0; | |
6714 | bigdisp.bitfield.disp16 = 1; | |
6715 | } | |
e05278af JB |
6716 | } |
6717 | else | |
6718 | { | |
6719 | /* For PC-relative branches, the width of the displacement | |
6720 | is dependent upon data size, not address size. */ | |
e05278af | 6721 | override = (i.prefix[DATA_PREFIX] != 0); |
40fb9820 L |
6722 | if (flag_code == CODE_64BIT) |
6723 | { | |
6724 | if (override || i.suffix == WORD_MNEM_SUFFIX) | |
6725 | bigdisp.bitfield.disp16 = 1; | |
6726 | else | |
6727 | { | |
6728 | bigdisp.bitfield.disp32 = 1; | |
6729 | bigdisp.bitfield.disp32s = 1; | |
6730 | } | |
6731 | } | |
6732 | else | |
e05278af JB |
6733 | { |
6734 | if (!override) | |
6735 | override = (i.suffix == (flag_code != CODE_16BIT | |
6736 | ? WORD_MNEM_SUFFIX | |
6737 | : LONG_MNEM_SUFFIX)); | |
40fb9820 L |
6738 | bigdisp.bitfield.disp32 = 1; |
6739 | if ((flag_code == CODE_16BIT) ^ override) | |
6740 | { | |
6741 | bigdisp.bitfield.disp32 = 0; | |
6742 | bigdisp.bitfield.disp16 = 1; | |
6743 | } | |
e05278af | 6744 | } |
e05278af | 6745 | } |
c6fb90c8 L |
6746 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
6747 | bigdisp); | |
252b5132 RH |
6748 | |
6749 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 6750 | i.op[this_operand].disps = exp; |
252b5132 RH |
6751 | i.disp_operands++; |
6752 | save_input_line_pointer = input_line_pointer; | |
6753 | input_line_pointer = disp_start; | |
6754 | END_STRING_AND_SAVE (disp_end); | |
6755 | ||
6756 | #ifndef GCC_ASM_O_HACK | |
6757 | #define GCC_ASM_O_HACK 0 | |
6758 | #endif | |
6759 | #if GCC_ASM_O_HACK | |
6760 | END_STRING_AND_SAVE (disp_end + 1); | |
40fb9820 | 6761 | if (i.types[this_operand].bitfield.baseIndex |
24eab124 | 6762 | && displacement_string_end[-1] == '+') |
252b5132 RH |
6763 | { |
6764 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
6765 | constraint within gcc asm statements. |
6766 | For instance: | |
6767 | ||
6768 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
6769 | __asm__ __volatile__ ( \ | |
6770 | "movw %w2,%0\n\t" \ | |
6771 | "movw %w1,2+%0\n\t" \ | |
6772 | "rorl $16,%1\n\t" \ | |
6773 | "movb %b1,4+%0\n\t" \ | |
6774 | "movb %4,5+%0\n\t" \ | |
6775 | "movb $0,6+%0\n\t" \ | |
6776 | "movb %h1,7+%0\n\t" \ | |
6777 | "rorl $16,%1" \ | |
6778 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
6779 | ||
6780 | This works great except that the output assembler ends | |
6781 | up looking a bit weird if it turns out that there is | |
6782 | no offset. You end up producing code that looks like: | |
6783 | ||
6784 | #APP | |
6785 | movw $235,(%eax) | |
6786 | movw %dx,2+(%eax) | |
6787 | rorl $16,%edx | |
6788 | movb %dl,4+(%eax) | |
6789 | movb $137,5+(%eax) | |
6790 | movb $0,6+(%eax) | |
6791 | movb %dh,7+(%eax) | |
6792 | rorl $16,%edx | |
6793 | #NO_APP | |
6794 | ||
47926f60 | 6795 | So here we provide the missing zero. */ |
24eab124 AM |
6796 | |
6797 | *displacement_string_end = '0'; | |
252b5132 RH |
6798 | } |
6799 | #endif | |
3956db08 | 6800 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
6801 | if (gotfree_input_line) |
6802 | input_line_pointer = gotfree_input_line; | |
252b5132 | 6803 | |
24eab124 | 6804 | exp_seg = expression (exp); |
252b5132 | 6805 | |
636c26b0 AM |
6806 | SKIP_WHITESPACE (); |
6807 | if (*input_line_pointer) | |
6808 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
6809 | #if GCC_ASM_O_HACK | |
6810 | RESTORE_END_STRING (disp_end + 1); | |
6811 | #endif | |
636c26b0 | 6812 | input_line_pointer = save_input_line_pointer; |
636c26b0 AM |
6813 | if (gotfree_input_line) |
6814 | free (gotfree_input_line); | |
3992d3b7 | 6815 | ret = 1; |
636c26b0 | 6816 | |
24eab124 AM |
6817 | /* We do this to make sure that the section symbol is in |
6818 | the symbol table. We will ultimately change the relocation | |
47926f60 | 6819 | to be relative to the beginning of the section. */ |
1ae12ab7 | 6820 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
d6ab8113 JB |
6821 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
6822 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) | |
24eab124 | 6823 | { |
636c26b0 | 6824 | if (exp->X_op != O_symbol) |
3992d3b7 | 6825 | goto inv_disp; |
636c26b0 | 6826 | |
e5cb08ac | 6827 | if (S_IS_LOCAL (exp->X_add_symbol) |
24eab124 AM |
6828 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section) |
6829 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); | |
24eab124 AM |
6830 | exp->X_op = O_subtract; |
6831 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 | 6832 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
29b0f896 | 6833 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
d6ab8113 JB |
6834 | else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
6835 | i.reloc[this_operand] = BFD_RELOC_64; | |
23df1078 | 6836 | else |
29b0f896 | 6837 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 6838 | } |
252b5132 | 6839 | |
3992d3b7 AM |
6840 | else if (exp->X_op == O_absent |
6841 | || exp->X_op == O_illegal | |
6842 | || exp->X_op == O_big | |
6843 | || (gotfree_input_line | |
6844 | && (exp->X_op == O_constant | |
6845 | || exp->X_op == O_register))) | |
2daf4fd8 | 6846 | { |
3992d3b7 AM |
6847 | inv_disp: |
6848 | as_bad (_("missing or invalid displacement expression `%s'"), | |
2daf4fd8 | 6849 | disp_start); |
3992d3b7 | 6850 | ret = 0; |
2daf4fd8 AM |
6851 | } |
6852 | ||
4c63da97 | 6853 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
3992d3b7 AM |
6854 | else if (exp->X_op != O_constant |
6855 | && OUTPUT_FLAVOR == bfd_target_aout_flavour | |
6856 | && exp_seg != absolute_section | |
6857 | && exp_seg != text_section | |
6858 | && exp_seg != data_section | |
6859 | && exp_seg != bss_section | |
6860 | && exp_seg != undefined_section | |
6861 | && !bfd_is_com_section (exp_seg)) | |
24eab124 | 6862 | { |
d0b47220 | 6863 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
3992d3b7 | 6864 | ret = 0; |
24eab124 | 6865 | } |
252b5132 | 6866 | #endif |
3956db08 | 6867 | |
3992d3b7 AM |
6868 | RESTORE_END_STRING (disp_end); |
6869 | ||
40fb9820 L |
6870 | /* Check if this is a displacement only operand. */ |
6871 | bigdisp = i.types[this_operand]; | |
6872 | bigdisp.bitfield.disp8 = 0; | |
6873 | bigdisp.bitfield.disp16 = 0; | |
6874 | bigdisp.bitfield.disp32 = 0; | |
6875 | bigdisp.bitfield.disp32s = 0; | |
6876 | bigdisp.bitfield.disp64 = 0; | |
0dfbf9d7 | 6877 | if (operand_type_all_zero (&bigdisp)) |
c6fb90c8 L |
6878 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
6879 | types); | |
3956db08 | 6880 | |
3992d3b7 | 6881 | return ret; |
252b5132 RH |
6882 | } |
6883 | ||
eecb386c | 6884 | /* Make sure the memory operand we've been dealt is valid. |
47926f60 KH |
6885 | Return 1 on success, 0 on a failure. */ |
6886 | ||
252b5132 | 6887 | static int |
e3bb37b5 | 6888 | i386_index_check (const char *operand_string) |
252b5132 | 6889 | { |
3e73aa7c | 6890 | int ok; |
24eab124 | 6891 | #if INFER_ADDR_PREFIX |
eecb386c AM |
6892 | int fudged = 0; |
6893 | ||
24eab124 AM |
6894 | tryprefix: |
6895 | #endif | |
3e73aa7c | 6896 | ok = 1; |
75178d9d | 6897 | if (flag_code == CODE_64BIT) |
64e74474 | 6898 | { |
64e74474 | 6899 | if ((i.base_reg |
40fb9820 L |
6900 | && ((i.prefix[ADDR_PREFIX] == 0 |
6901 | && !i.base_reg->reg_type.bitfield.reg64) | |
6902 | || (i.prefix[ADDR_PREFIX] | |
6903 | && !i.base_reg->reg_type.bitfield.reg32)) | |
6904 | && (i.index_reg | |
9a04903e JB |
6905 | || i.base_reg->reg_num != |
6906 | (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip))) | |
64e74474 | 6907 | || (i.index_reg |
40fb9820 L |
6908 | && (!i.index_reg->reg_type.bitfield.baseindex |
6909 | || (i.prefix[ADDR_PREFIX] == 0 | |
db51cc60 L |
6910 | && i.index_reg->reg_num != RegRiz |
6911 | && !i.index_reg->reg_type.bitfield.reg64 | |
6912 | ) | |
40fb9820 | 6913 | || (i.prefix[ADDR_PREFIX] |
db51cc60 | 6914 | && i.index_reg->reg_num != RegEiz |
40fb9820 | 6915 | && !i.index_reg->reg_type.bitfield.reg32)))) |
64e74474 | 6916 | ok = 0; |
3e73aa7c JH |
6917 | } |
6918 | else | |
6919 | { | |
6920 | if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) | |
6921 | { | |
6922 | /* 16bit checks. */ | |
6923 | if ((i.base_reg | |
40fb9820 L |
6924 | && (!i.base_reg->reg_type.bitfield.reg16 |
6925 | || !i.base_reg->reg_type.bitfield.baseindex)) | |
3e73aa7c | 6926 | || (i.index_reg |
40fb9820 L |
6927 | && (!i.index_reg->reg_type.bitfield.reg16 |
6928 | || !i.index_reg->reg_type.bitfield.baseindex | |
29b0f896 AM |
6929 | || !(i.base_reg |
6930 | && i.base_reg->reg_num < 6 | |
6931 | && i.index_reg->reg_num >= 6 | |
6932 | && i.log2_scale_factor == 0)))) | |
3e73aa7c JH |
6933 | ok = 0; |
6934 | } | |
6935 | else | |
e5cb08ac | 6936 | { |
3e73aa7c JH |
6937 | /* 32bit checks. */ |
6938 | if ((i.base_reg | |
40fb9820 | 6939 | && !i.base_reg->reg_type.bitfield.reg32) |
3e73aa7c | 6940 | || (i.index_reg |
db51cc60 L |
6941 | && ((!i.index_reg->reg_type.bitfield.reg32 |
6942 | && i.index_reg->reg_num != RegEiz) | |
40fb9820 | 6943 | || !i.index_reg->reg_type.bitfield.baseindex))) |
e5cb08ac | 6944 | ok = 0; |
3e73aa7c JH |
6945 | } |
6946 | } | |
6947 | if (!ok) | |
24eab124 AM |
6948 | { |
6949 | #if INFER_ADDR_PREFIX | |
20f0a1fc | 6950 | if (i.prefix[ADDR_PREFIX] == 0) |
24eab124 AM |
6951 | { |
6952 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
6953 | i.prefixes += 1; | |
b23bac36 AM |
6954 | /* Change the size of any displacement too. At most one of |
6955 | Disp16 or Disp32 is set. | |
6956 | FIXME. There doesn't seem to be any real need for separate | |
6957 | Disp16 and Disp32 flags. The same goes for Imm16 and Imm32. | |
47926f60 | 6958 | Removing them would probably clean up the code quite a lot. */ |
4eed87de | 6959 | if (flag_code != CODE_64BIT |
40fb9820 L |
6960 | && (i.types[this_operand].bitfield.disp16 |
6961 | || i.types[this_operand].bitfield.disp32)) | |
6962 | i.types[this_operand] | |
c6fb90c8 | 6963 | = operand_type_xor (i.types[this_operand], disp16_32); |
eecb386c | 6964 | fudged = 1; |
24eab124 AM |
6965 | goto tryprefix; |
6966 | } | |
eecb386c AM |
6967 | if (fudged) |
6968 | as_bad (_("`%s' is not a valid base/index expression"), | |
6969 | operand_string); | |
6970 | else | |
c388dee8 | 6971 | #endif |
eecb386c AM |
6972 | as_bad (_("`%s' is not a valid %s bit base/index expression"), |
6973 | operand_string, | |
3e73aa7c | 6974 | flag_code_names[flag_code]); |
24eab124 | 6975 | } |
20f0a1fc | 6976 | return ok; |
24eab124 | 6977 | } |
252b5132 | 6978 | |
252b5132 | 6979 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero |
47926f60 | 6980 | on error. */ |
252b5132 | 6981 | |
252b5132 | 6982 | static int |
a7619375 | 6983 | i386_att_operand (char *operand_string) |
252b5132 | 6984 | { |
af6bdddf AM |
6985 | const reg_entry *r; |
6986 | char *end_op; | |
24eab124 | 6987 | char *op_string = operand_string; |
252b5132 | 6988 | |
24eab124 | 6989 | if (is_space_char (*op_string)) |
252b5132 RH |
6990 | ++op_string; |
6991 | ||
24eab124 | 6992 | /* We check for an absolute prefix (differentiating, |
47926f60 | 6993 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
6994 | if (*op_string == ABSOLUTE_PREFIX) |
6995 | { | |
6996 | ++op_string; | |
6997 | if (is_space_char (*op_string)) | |
6998 | ++op_string; | |
40fb9820 | 6999 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 | 7000 | } |
252b5132 | 7001 | |
47926f60 | 7002 | /* Check if operand is a register. */ |
4d1bb795 | 7003 | if ((r = parse_register (op_string, &end_op)) != NULL) |
24eab124 | 7004 | { |
40fb9820 L |
7005 | i386_operand_type temp; |
7006 | ||
24eab124 AM |
7007 | /* Check for a segment override by searching for ':' after a |
7008 | segment register. */ | |
7009 | op_string = end_op; | |
7010 | if (is_space_char (*op_string)) | |
7011 | ++op_string; | |
40fb9820 L |
7012 | if (*op_string == ':' |
7013 | && (r->reg_type.bitfield.sreg2 | |
7014 | || r->reg_type.bitfield.sreg3)) | |
24eab124 AM |
7015 | { |
7016 | switch (r->reg_num) | |
7017 | { | |
7018 | case 0: | |
7019 | i.seg[i.mem_operands] = &es; | |
7020 | break; | |
7021 | case 1: | |
7022 | i.seg[i.mem_operands] = &cs; | |
7023 | break; | |
7024 | case 2: | |
7025 | i.seg[i.mem_operands] = &ss; | |
7026 | break; | |
7027 | case 3: | |
7028 | i.seg[i.mem_operands] = &ds; | |
7029 | break; | |
7030 | case 4: | |
7031 | i.seg[i.mem_operands] = &fs; | |
7032 | break; | |
7033 | case 5: | |
7034 | i.seg[i.mem_operands] = &gs; | |
7035 | break; | |
7036 | } | |
252b5132 | 7037 | |
24eab124 | 7038 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
7039 | ++op_string; |
7040 | if (is_space_char (*op_string)) | |
24eab124 | 7041 | ++op_string; |
252b5132 | 7042 | |
24eab124 AM |
7043 | if (!is_digit_char (*op_string) |
7044 | && !is_identifier_char (*op_string) | |
7045 | && *op_string != '(' | |
7046 | && *op_string != ABSOLUTE_PREFIX) | |
7047 | { | |
7048 | as_bad (_("bad memory operand `%s'"), op_string); | |
7049 | return 0; | |
7050 | } | |
47926f60 | 7051 | /* Handle case of %es:*foo. */ |
24eab124 AM |
7052 | if (*op_string == ABSOLUTE_PREFIX) |
7053 | { | |
7054 | ++op_string; | |
7055 | if (is_space_char (*op_string)) | |
7056 | ++op_string; | |
40fb9820 | 7057 | i.types[this_operand].bitfield.jumpabsolute = 1; |
24eab124 AM |
7058 | } |
7059 | goto do_memory_reference; | |
7060 | } | |
7061 | if (*op_string) | |
7062 | { | |
d0b47220 | 7063 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
7064 | return 0; |
7065 | } | |
40fb9820 L |
7066 | temp = r->reg_type; |
7067 | temp.bitfield.baseindex = 0; | |
c6fb90c8 L |
7068 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
7069 | temp); | |
7d5e4556 | 7070 | i.types[this_operand].bitfield.unspecified = 0; |
520dc8e8 | 7071 | i.op[this_operand].regs = r; |
24eab124 AM |
7072 | i.reg_operands++; |
7073 | } | |
af6bdddf AM |
7074 | else if (*op_string == REGISTER_PREFIX) |
7075 | { | |
7076 | as_bad (_("bad register name `%s'"), op_string); | |
7077 | return 0; | |
7078 | } | |
24eab124 | 7079 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 7080 | { |
24eab124 | 7081 | ++op_string; |
40fb9820 | 7082 | if (i.types[this_operand].bitfield.jumpabsolute) |
24eab124 | 7083 | { |
d0b47220 | 7084 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
7085 | return 0; |
7086 | } | |
7087 | if (!i386_immediate (op_string)) | |
7088 | return 0; | |
7089 | } | |
7090 | else if (is_digit_char (*op_string) | |
7091 | || is_identifier_char (*op_string) | |
e5cb08ac | 7092 | || *op_string == '(') |
24eab124 | 7093 | { |
47926f60 | 7094 | /* This is a memory reference of some sort. */ |
af6bdddf | 7095 | char *base_string; |
252b5132 | 7096 | |
47926f60 | 7097 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
7098 | char *displacement_string_start; |
7099 | char *displacement_string_end; | |
252b5132 | 7100 | |
24eab124 | 7101 | do_memory_reference: |
24eab124 | 7102 | if ((i.mem_operands == 1 |
40fb9820 | 7103 | && !current_templates->start->opcode_modifier.isstring) |
24eab124 AM |
7104 | || i.mem_operands == 2) |
7105 | { | |
7106 | as_bad (_("too many memory references for `%s'"), | |
7107 | current_templates->start->name); | |
7108 | return 0; | |
7109 | } | |
252b5132 | 7110 | |
24eab124 AM |
7111 | /* Check for base index form. We detect the base index form by |
7112 | looking for an ')' at the end of the operand, searching | |
7113 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
7114 | after the '('. */ | |
af6bdddf | 7115 | base_string = op_string + strlen (op_string); |
c3332e24 | 7116 | |
af6bdddf AM |
7117 | --base_string; |
7118 | if (is_space_char (*base_string)) | |
7119 | --base_string; | |
252b5132 | 7120 | |
47926f60 | 7121 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
7122 | displacement_string_start = op_string; |
7123 | displacement_string_end = base_string + 1; | |
252b5132 | 7124 | |
24eab124 AM |
7125 | if (*base_string == ')') |
7126 | { | |
af6bdddf | 7127 | char *temp_string; |
24eab124 AM |
7128 | unsigned int parens_balanced = 1; |
7129 | /* We've already checked that the number of left & right ()'s are | |
47926f60 | 7130 | equal, so this loop will not be infinite. */ |
24eab124 AM |
7131 | do |
7132 | { | |
7133 | base_string--; | |
7134 | if (*base_string == ')') | |
7135 | parens_balanced++; | |
7136 | if (*base_string == '(') | |
7137 | parens_balanced--; | |
7138 | } | |
7139 | while (parens_balanced); | |
c3332e24 | 7140 | |
af6bdddf | 7141 | temp_string = base_string; |
c3332e24 | 7142 | |
24eab124 | 7143 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
7144 | ++base_string; |
7145 | if (is_space_char (*base_string)) | |
24eab124 | 7146 | ++base_string; |
252b5132 | 7147 | |
af6bdddf | 7148 | if (*base_string == ',' |
4eed87de AM |
7149 | || ((i.base_reg = parse_register (base_string, &end_op)) |
7150 | != NULL)) | |
252b5132 | 7151 | { |
af6bdddf | 7152 | displacement_string_end = temp_string; |
252b5132 | 7153 | |
40fb9820 | 7154 | i.types[this_operand].bitfield.baseindex = 1; |
252b5132 | 7155 | |
af6bdddf | 7156 | if (i.base_reg) |
24eab124 | 7157 | { |
24eab124 AM |
7158 | base_string = end_op; |
7159 | if (is_space_char (*base_string)) | |
7160 | ++base_string; | |
af6bdddf AM |
7161 | } |
7162 | ||
7163 | /* There may be an index reg or scale factor here. */ | |
7164 | if (*base_string == ',') | |
7165 | { | |
7166 | ++base_string; | |
7167 | if (is_space_char (*base_string)) | |
7168 | ++base_string; | |
7169 | ||
4eed87de AM |
7170 | if ((i.index_reg = parse_register (base_string, &end_op)) |
7171 | != NULL) | |
24eab124 | 7172 | { |
af6bdddf | 7173 | base_string = end_op; |
24eab124 AM |
7174 | if (is_space_char (*base_string)) |
7175 | ++base_string; | |
af6bdddf AM |
7176 | if (*base_string == ',') |
7177 | { | |
7178 | ++base_string; | |
7179 | if (is_space_char (*base_string)) | |
7180 | ++base_string; | |
7181 | } | |
e5cb08ac | 7182 | else if (*base_string != ')') |
af6bdddf | 7183 | { |
4eed87de AM |
7184 | as_bad (_("expecting `,' or `)' " |
7185 | "after index register in `%s'"), | |
af6bdddf AM |
7186 | operand_string); |
7187 | return 0; | |
7188 | } | |
24eab124 | 7189 | } |
af6bdddf | 7190 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 7191 | { |
af6bdddf | 7192 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
7193 | return 0; |
7194 | } | |
252b5132 | 7195 | |
47926f60 | 7196 | /* Check for scale factor. */ |
551c1ca1 | 7197 | if (*base_string != ')') |
af6bdddf | 7198 | { |
551c1ca1 AM |
7199 | char *end_scale = i386_scale (base_string); |
7200 | ||
7201 | if (!end_scale) | |
af6bdddf | 7202 | return 0; |
24eab124 | 7203 | |
551c1ca1 | 7204 | base_string = end_scale; |
af6bdddf AM |
7205 | if (is_space_char (*base_string)) |
7206 | ++base_string; | |
7207 | if (*base_string != ')') | |
7208 | { | |
4eed87de AM |
7209 | as_bad (_("expecting `)' " |
7210 | "after scale factor in `%s'"), | |
af6bdddf AM |
7211 | operand_string); |
7212 | return 0; | |
7213 | } | |
7214 | } | |
7215 | else if (!i.index_reg) | |
24eab124 | 7216 | { |
4eed87de AM |
7217 | as_bad (_("expecting index register or scale factor " |
7218 | "after `,'; got '%c'"), | |
af6bdddf | 7219 | *base_string); |
24eab124 AM |
7220 | return 0; |
7221 | } | |
7222 | } | |
af6bdddf | 7223 | else if (*base_string != ')') |
24eab124 | 7224 | { |
4eed87de AM |
7225 | as_bad (_("expecting `,' or `)' " |
7226 | "after base register in `%s'"), | |
af6bdddf | 7227 | operand_string); |
24eab124 AM |
7228 | return 0; |
7229 | } | |
c3332e24 | 7230 | } |
af6bdddf | 7231 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 7232 | { |
af6bdddf | 7233 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 7234 | return 0; |
c3332e24 | 7235 | } |
24eab124 AM |
7236 | } |
7237 | ||
7238 | /* If there's an expression beginning the operand, parse it, | |
7239 | assuming displacement_string_start and | |
7240 | displacement_string_end are meaningful. */ | |
7241 | if (displacement_string_start != displacement_string_end) | |
7242 | { | |
7243 | if (!i386_displacement (displacement_string_start, | |
7244 | displacement_string_end)) | |
7245 | return 0; | |
7246 | } | |
7247 | ||
7248 | /* Special case for (%dx) while doing input/output op. */ | |
7249 | if (i.base_reg | |
0dfbf9d7 L |
7250 | && operand_type_equal (&i.base_reg->reg_type, |
7251 | ®16_inoutportreg) | |
24eab124 AM |
7252 | && i.index_reg == 0 |
7253 | && i.log2_scale_factor == 0 | |
7254 | && i.seg[i.mem_operands] == 0 | |
40fb9820 | 7255 | && !operand_type_check (i.types[this_operand], disp)) |
24eab124 | 7256 | { |
65da13b5 | 7257 | i.types[this_operand] = inoutportreg; |
24eab124 AM |
7258 | return 1; |
7259 | } | |
7260 | ||
eecb386c AM |
7261 | if (i386_index_check (operand_string) == 0) |
7262 | return 0; | |
5c07affc | 7263 | i.types[this_operand].bitfield.mem = 1; |
24eab124 AM |
7264 | i.mem_operands++; |
7265 | } | |
7266 | else | |
ce8a8b2f AM |
7267 | { |
7268 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
7269 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
7270 | output_invalid (*op_string), | |
7271 | this_operand + 1, | |
7272 | op_string); | |
7273 | return 0; | |
7274 | } | |
47926f60 | 7275 | return 1; /* Normal return. */ |
252b5132 RH |
7276 | } |
7277 | \f | |
ee7fcc42 AM |
7278 | /* md_estimate_size_before_relax() |
7279 | ||
7280 | Called just before relax() for rs_machine_dependent frags. The x86 | |
7281 | assembler uses these frags to handle variable size jump | |
7282 | instructions. | |
7283 | ||
7284 | Any symbol that is now undefined will not become defined. | |
7285 | Return the correct fr_subtype in the frag. | |
7286 | Return the initial "guess for variable size of frag" to caller. | |
7287 | The guess is actually the growth beyond the fixed part. Whatever | |
7288 | we do to grow the fixed or variable part contributes to our | |
7289 | returned value. */ | |
7290 | ||
252b5132 RH |
7291 | int |
7292 | md_estimate_size_before_relax (fragP, segment) | |
29b0f896 AM |
7293 | fragS *fragP; |
7294 | segT segment; | |
252b5132 | 7295 | { |
252b5132 | 7296 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
7297 | check for un-relaxable symbols. On an ELF system, we can't relax |
7298 | an externally visible symbol, because it may be overridden by a | |
7299 | shared library. */ | |
7300 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 7301 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 7302 | || (IS_ELF |
31312f95 AM |
7303 | && (S_IS_EXTERNAL (fragP->fr_symbol) |
7304 | || S_IS_WEAK (fragP->fr_symbol))) | |
b98ef147 AM |
7305 | #endif |
7306 | ) | |
252b5132 | 7307 | { |
b98ef147 AM |
7308 | /* Symbol is undefined in this segment, or we need to keep a |
7309 | reloc so that weak symbols can be overridden. */ | |
7310 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f86103b7 | 7311 | enum bfd_reloc_code_real reloc_type; |
ee7fcc42 AM |
7312 | unsigned char *opcode; |
7313 | int old_fr_fix; | |
f6af82bd | 7314 | |
ee7fcc42 AM |
7315 | if (fragP->fr_var != NO_RELOC) |
7316 | reloc_type = fragP->fr_var; | |
b98ef147 | 7317 | else if (size == 2) |
f6af82bd AM |
7318 | reloc_type = BFD_RELOC_16_PCREL; |
7319 | else | |
7320 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 7321 | |
ee7fcc42 AM |
7322 | old_fr_fix = fragP->fr_fix; |
7323 | opcode = (unsigned char *) fragP->fr_opcode; | |
7324 | ||
fddf5b5b | 7325 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 7326 | { |
fddf5b5b AM |
7327 | case UNCOND_JUMP: |
7328 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 7329 | opcode[0] = 0xe9; |
252b5132 | 7330 | fragP->fr_fix += size; |
062cd5e7 AS |
7331 | fix_new (fragP, old_fr_fix, size, |
7332 | fragP->fr_symbol, | |
7333 | fragP->fr_offset, 1, | |
7334 | reloc_type); | |
252b5132 RH |
7335 | break; |
7336 | ||
fddf5b5b | 7337 | case COND_JUMP86: |
412167cb AM |
7338 | if (size == 2 |
7339 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) | |
fddf5b5b AM |
7340 | { |
7341 | /* Negate the condition, and branch past an | |
7342 | unconditional jump. */ | |
7343 | opcode[0] ^= 1; | |
7344 | opcode[1] = 3; | |
7345 | /* Insert an unconditional jump. */ | |
7346 | opcode[2] = 0xe9; | |
7347 | /* We added two extra opcode bytes, and have a two byte | |
7348 | offset. */ | |
7349 | fragP->fr_fix += 2 + 2; | |
062cd5e7 AS |
7350 | fix_new (fragP, old_fr_fix + 2, 2, |
7351 | fragP->fr_symbol, | |
7352 | fragP->fr_offset, 1, | |
7353 | reloc_type); | |
fddf5b5b AM |
7354 | break; |
7355 | } | |
7356 | /* Fall through. */ | |
7357 | ||
7358 | case COND_JUMP: | |
412167cb AM |
7359 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
7360 | { | |
3e02c1cc AM |
7361 | fixS *fixP; |
7362 | ||
412167cb | 7363 | fragP->fr_fix += 1; |
3e02c1cc AM |
7364 | fixP = fix_new (fragP, old_fr_fix, 1, |
7365 | fragP->fr_symbol, | |
7366 | fragP->fr_offset, 1, | |
7367 | BFD_RELOC_8_PCREL); | |
7368 | fixP->fx_signed = 1; | |
412167cb AM |
7369 | break; |
7370 | } | |
93c2a809 | 7371 | |
24eab124 | 7372 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 7373 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 7374 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 7375 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
7376 | /* We've added an opcode byte. */ |
7377 | fragP->fr_fix += 1 + size; | |
062cd5e7 AS |
7378 | fix_new (fragP, old_fr_fix + 1, size, |
7379 | fragP->fr_symbol, | |
7380 | fragP->fr_offset, 1, | |
7381 | reloc_type); | |
252b5132 | 7382 | break; |
fddf5b5b AM |
7383 | |
7384 | default: | |
7385 | BAD_CASE (fragP->fr_subtype); | |
7386 | break; | |
252b5132 RH |
7387 | } |
7388 | frag_wane (fragP); | |
ee7fcc42 | 7389 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 7390 | } |
93c2a809 | 7391 | |
93c2a809 AM |
7392 | /* Guess size depending on current relax state. Initially the relax |
7393 | state will correspond to a short jump and we return 1, because | |
7394 | the variable part of the frag (the branch offset) is one byte | |
7395 | long. However, we can relax a section more than once and in that | |
7396 | case we must either set fr_subtype back to the unrelaxed state, | |
7397 | or return the value for the appropriate branch. */ | |
7398 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
7399 | } |
7400 | ||
47926f60 KH |
7401 | /* Called after relax() is finished. |
7402 | ||
7403 | In: Address of frag. | |
7404 | fr_type == rs_machine_dependent. | |
7405 | fr_subtype is what the address relaxed to. | |
7406 | ||
7407 | Out: Any fixSs and constants are set up. | |
7408 | Caller will turn frag into a ".space 0". */ | |
7409 | ||
252b5132 RH |
7410 | void |
7411 | md_convert_frag (abfd, sec, fragP) | |
ab9da554 ILT |
7412 | bfd *abfd ATTRIBUTE_UNUSED; |
7413 | segT sec ATTRIBUTE_UNUSED; | |
29b0f896 | 7414 | fragS *fragP; |
252b5132 | 7415 | { |
29b0f896 | 7416 | unsigned char *opcode; |
252b5132 | 7417 | unsigned char *where_to_put_displacement = NULL; |
847f7ad4 AM |
7418 | offsetT target_address; |
7419 | offsetT opcode_address; | |
252b5132 | 7420 | unsigned int extension = 0; |
847f7ad4 | 7421 | offsetT displacement_from_opcode_start; |
252b5132 RH |
7422 | |
7423 | opcode = (unsigned char *) fragP->fr_opcode; | |
7424 | ||
47926f60 | 7425 | /* Address we want to reach in file space. */ |
252b5132 | 7426 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 7427 | |
47926f60 | 7428 | /* Address opcode resides at in file space. */ |
252b5132 RH |
7429 | opcode_address = fragP->fr_address + fragP->fr_fix; |
7430 | ||
47926f60 | 7431 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
7432 | displacement_from_opcode_start = target_address - opcode_address; |
7433 | ||
fddf5b5b | 7434 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 7435 | { |
47926f60 KH |
7436 | /* Don't have to change opcode. */ |
7437 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 7438 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
7439 | } |
7440 | else | |
7441 | { | |
7442 | if (no_cond_jump_promotion | |
7443 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4eed87de AM |
7444 | as_warn_where (fragP->fr_file, fragP->fr_line, |
7445 | _("long jump required")); | |
252b5132 | 7446 | |
fddf5b5b AM |
7447 | switch (fragP->fr_subtype) |
7448 | { | |
7449 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
7450 | extension = 4; /* 1 opcode + 4 displacement */ | |
7451 | opcode[0] = 0xe9; | |
7452 | where_to_put_displacement = &opcode[1]; | |
7453 | break; | |
252b5132 | 7454 | |
fddf5b5b AM |
7455 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
7456 | extension = 2; /* 1 opcode + 2 displacement */ | |
7457 | opcode[0] = 0xe9; | |
7458 | where_to_put_displacement = &opcode[1]; | |
7459 | break; | |
252b5132 | 7460 | |
fddf5b5b AM |
7461 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
7462 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
7463 | extension = 5; /* 2 opcode + 4 displacement */ | |
7464 | opcode[1] = opcode[0] + 0x10; | |
7465 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
7466 | where_to_put_displacement = &opcode[2]; | |
7467 | break; | |
252b5132 | 7468 | |
fddf5b5b AM |
7469 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
7470 | extension = 3; /* 2 opcode + 2 displacement */ | |
7471 | opcode[1] = opcode[0] + 0x10; | |
7472 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
7473 | where_to_put_displacement = &opcode[2]; | |
7474 | break; | |
252b5132 | 7475 | |
fddf5b5b AM |
7476 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
7477 | extension = 4; | |
7478 | opcode[0] ^= 1; | |
7479 | opcode[1] = 3; | |
7480 | opcode[2] = 0xe9; | |
7481 | where_to_put_displacement = &opcode[3]; | |
7482 | break; | |
7483 | ||
7484 | default: | |
7485 | BAD_CASE (fragP->fr_subtype); | |
7486 | break; | |
7487 | } | |
252b5132 | 7488 | } |
fddf5b5b | 7489 | |
7b81dfbb AJ |
7490 | /* If size if less then four we are sure that the operand fits, |
7491 | but if it's 4, then it could be that the displacement is larger | |
7492 | then -/+ 2GB. */ | |
7493 | if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 | |
7494 | && object_64bit | |
7495 | && ((addressT) (displacement_from_opcode_start - extension | |
4eed87de AM |
7496 | + ((addressT) 1 << 31)) |
7497 | > (((addressT) 2 << 31) - 1))) | |
7b81dfbb AJ |
7498 | { |
7499 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
7500 | _("jump target out of range")); | |
7501 | /* Make us emit 0. */ | |
7502 | displacement_from_opcode_start = extension; | |
7503 | } | |
47926f60 | 7504 | /* Now put displacement after opcode. */ |
252b5132 RH |
7505 | md_number_to_chars ((char *) where_to_put_displacement, |
7506 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 7507 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
7508 | fragP->fr_fix += extension; |
7509 | } | |
7510 | \f | |
252b5132 RH |
7511 | /* Apply a fixup (fixS) to segment data, once it has been determined |
7512 | by our caller that we have all the info we need to fix it up. | |
7513 | ||
7514 | On the 386, immediates, displacements, and data pointers are all in | |
7515 | the same (little-endian) format, so we don't need to care about which | |
7516 | we are handling. */ | |
7517 | ||
94f592af | 7518 | void |
55cf6793 | 7519 | md_apply_fix (fixP, valP, seg) |
47926f60 KH |
7520 | /* The fix we're to put in. */ |
7521 | fixS *fixP; | |
47926f60 | 7522 | /* Pointer to the value of the bits. */ |
c6682705 | 7523 | valueT *valP; |
47926f60 KH |
7524 | /* Segment fix is from. */ |
7525 | segT seg ATTRIBUTE_UNUSED; | |
252b5132 | 7526 | { |
94f592af | 7527 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
c6682705 | 7528 | valueT value = *valP; |
252b5132 | 7529 | |
f86103b7 | 7530 | #if !defined (TE_Mach) |
93382f6d AM |
7531 | if (fixP->fx_pcrel) |
7532 | { | |
7533 | switch (fixP->fx_r_type) | |
7534 | { | |
5865bb77 ILT |
7535 | default: |
7536 | break; | |
7537 | ||
d6ab8113 JB |
7538 | case BFD_RELOC_64: |
7539 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
7540 | break; | |
93382f6d | 7541 | case BFD_RELOC_32: |
ae8887b5 | 7542 | case BFD_RELOC_X86_64_32S: |
93382f6d AM |
7543 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
7544 | break; | |
7545 | case BFD_RELOC_16: | |
7546 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
7547 | break; | |
7548 | case BFD_RELOC_8: | |
7549 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
7550 | break; | |
7551 | } | |
7552 | } | |
252b5132 | 7553 | |
a161fe53 | 7554 | if (fixP->fx_addsy != NULL |
31312f95 | 7555 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
d6ab8113 | 7556 | || fixP->fx_r_type == BFD_RELOC_64_PCREL |
31312f95 AM |
7557 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
7558 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) | |
7559 | && !use_rela_relocations) | |
252b5132 | 7560 | { |
31312f95 AM |
7561 | /* This is a hack. There should be a better way to handle this. |
7562 | This covers for the fact that bfd_install_relocation will | |
7563 | subtract the current location (for partial_inplace, PC relative | |
7564 | relocations); see more below. */ | |
252b5132 | 7565 | #ifndef OBJ_AOUT |
718ddfc0 | 7566 | if (IS_ELF |
252b5132 RH |
7567 | #ifdef TE_PE |
7568 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
7569 | #endif | |
7570 | ) | |
7571 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
7572 | #endif | |
7573 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 7574 | if (IS_ELF) |
252b5132 | 7575 | { |
6539b54b | 7576 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
2f66722d | 7577 | |
6539b54b | 7578 | if ((sym_seg == seg |
2f66722d | 7579 | || (symbol_section_p (fixP->fx_addsy) |
6539b54b | 7580 | && sym_seg != absolute_section)) |
ae6063d4 | 7581 | && !generic_force_reloc (fixP)) |
2f66722d AM |
7582 | { |
7583 | /* Yes, we add the values in twice. This is because | |
6539b54b AM |
7584 | bfd_install_relocation subtracts them out again. I think |
7585 | bfd_install_relocation is broken, but I don't dare change | |
2f66722d AM |
7586 | it. FIXME. */ |
7587 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
7588 | } | |
252b5132 RH |
7589 | } |
7590 | #endif | |
7591 | #if defined (OBJ_COFF) && defined (TE_PE) | |
977cdf5a NC |
7592 | /* For some reason, the PE format does not store a |
7593 | section address offset for a PC relative symbol. */ | |
7594 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg | |
7be1c489 | 7595 | || S_IS_WEAK (fixP->fx_addsy)) |
252b5132 RH |
7596 | value += md_pcrel_from (fixP); |
7597 | #endif | |
7598 | } | |
7599 | ||
7600 | /* Fix a few things - the dynamic linker expects certain values here, | |
0234cb7c | 7601 | and we must not disappoint it. */ |
252b5132 | 7602 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 7603 | if (IS_ELF && fixP->fx_addsy) |
47926f60 KH |
7604 | switch (fixP->fx_r_type) |
7605 | { | |
7606 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 7607 | case BFD_RELOC_X86_64_PLT32: |
47926f60 KH |
7608 | /* Make the jump instruction point to the address of the operand. At |
7609 | runtime we merely add the offset to the actual PLT entry. */ | |
7610 | value = -4; | |
7611 | break; | |
31312f95 | 7612 | |
13ae64f3 JJ |
7613 | case BFD_RELOC_386_TLS_GD: |
7614 | case BFD_RELOC_386_TLS_LDM: | |
13ae64f3 | 7615 | case BFD_RELOC_386_TLS_IE_32: |
37e55690 JJ |
7616 | case BFD_RELOC_386_TLS_IE: |
7617 | case BFD_RELOC_386_TLS_GOTIE: | |
67a4f2b7 | 7618 | case BFD_RELOC_386_TLS_GOTDESC: |
bffbf940 JJ |
7619 | case BFD_RELOC_X86_64_TLSGD: |
7620 | case BFD_RELOC_X86_64_TLSLD: | |
7621 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 | 7622 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
00f7efb6 JJ |
7623 | value = 0; /* Fully resolved at runtime. No addend. */ |
7624 | /* Fallthrough */ | |
7625 | case BFD_RELOC_386_TLS_LE: | |
7626 | case BFD_RELOC_386_TLS_LDO_32: | |
7627 | case BFD_RELOC_386_TLS_LE_32: | |
7628 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 7629 | case BFD_RELOC_X86_64_DTPOFF64: |
00f7efb6 | 7630 | case BFD_RELOC_X86_64_TPOFF32: |
d6ab8113 | 7631 | case BFD_RELOC_X86_64_TPOFF64: |
00f7efb6 JJ |
7632 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
7633 | break; | |
7634 | ||
67a4f2b7 AO |
7635 | case BFD_RELOC_386_TLS_DESC_CALL: |
7636 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
7637 | value = 0; /* Fully resolved at runtime. No addend. */ | |
7638 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
7639 | fixP->fx_done = 0; | |
7640 | return; | |
7641 | ||
00f7efb6 JJ |
7642 | case BFD_RELOC_386_GOT32: |
7643 | case BFD_RELOC_X86_64_GOT32: | |
47926f60 KH |
7644 | value = 0; /* Fully resolved at runtime. No addend. */ |
7645 | break; | |
47926f60 KH |
7646 | |
7647 | case BFD_RELOC_VTABLE_INHERIT: | |
7648 | case BFD_RELOC_VTABLE_ENTRY: | |
7649 | fixP->fx_done = 0; | |
94f592af | 7650 | return; |
47926f60 KH |
7651 | |
7652 | default: | |
7653 | break; | |
7654 | } | |
7655 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
c6682705 | 7656 | *valP = value; |
f86103b7 | 7657 | #endif /* !defined (TE_Mach) */ |
3e73aa7c | 7658 | |
3e73aa7c | 7659 | /* Are we finished with this relocation now? */ |
c6682705 | 7660 | if (fixP->fx_addsy == NULL) |
3e73aa7c JH |
7661 | fixP->fx_done = 1; |
7662 | else if (use_rela_relocations) | |
7663 | { | |
7664 | fixP->fx_no_overflow = 1; | |
062cd5e7 AS |
7665 | /* Remember value for tc_gen_reloc. */ |
7666 | fixP->fx_addnumber = value; | |
3e73aa7c JH |
7667 | value = 0; |
7668 | } | |
f86103b7 | 7669 | |
94f592af | 7670 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 7671 | } |
252b5132 | 7672 | \f |
252b5132 | 7673 | char * |
499ac353 | 7674 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 7675 | { |
499ac353 NC |
7676 | /* This outputs the LITTLENUMs in REVERSE order; |
7677 | in accord with the bigendian 386. */ | |
7678 | return ieee_md_atof (type, litP, sizeP, FALSE); | |
252b5132 RH |
7679 | } |
7680 | \f | |
2d545b82 | 7681 | static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; |
252b5132 | 7682 | |
252b5132 | 7683 | static char * |
e3bb37b5 | 7684 | output_invalid (int c) |
252b5132 | 7685 | { |
3882b010 | 7686 | if (ISPRINT (c)) |
f9f21a03 L |
7687 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
7688 | "'%c'", c); | |
252b5132 | 7689 | else |
f9f21a03 | 7690 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
2d545b82 | 7691 | "(0x%x)", (unsigned char) c); |
252b5132 RH |
7692 | return output_invalid_buf; |
7693 | } | |
7694 | ||
af6bdddf | 7695 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
7696 | |
7697 | static const reg_entry * | |
4d1bb795 | 7698 | parse_real_register (char *reg_string, char **end_op) |
252b5132 | 7699 | { |
af6bdddf AM |
7700 | char *s = reg_string; |
7701 | char *p; | |
252b5132 RH |
7702 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
7703 | const reg_entry *r; | |
7704 | ||
7705 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
7706 | if (*s == REGISTER_PREFIX) | |
7707 | ++s; | |
7708 | ||
7709 | if (is_space_char (*s)) | |
7710 | ++s; | |
7711 | ||
7712 | p = reg_name_given; | |
af6bdddf | 7713 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
7714 | { |
7715 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
7716 | return (const reg_entry *) NULL; |
7717 | s++; | |
252b5132 RH |
7718 | } |
7719 | ||
6588847e DN |
7720 | /* For naked regs, make sure that we are not dealing with an identifier. |
7721 | This prevents confusing an identifier like `eax_var' with register | |
7722 | `eax'. */ | |
7723 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
7724 | return (const reg_entry *) NULL; | |
7725 | ||
af6bdddf | 7726 | *end_op = s; |
252b5132 RH |
7727 | |
7728 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); | |
7729 | ||
5f47d35b | 7730 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
47926f60 | 7731 | if (r == i386_regtab /* %st is first entry of table */) |
5f47d35b | 7732 | { |
5f47d35b AM |
7733 | if (is_space_char (*s)) |
7734 | ++s; | |
7735 | if (*s == '(') | |
7736 | { | |
af6bdddf | 7737 | ++s; |
5f47d35b AM |
7738 | if (is_space_char (*s)) |
7739 | ++s; | |
7740 | if (*s >= '0' && *s <= '7') | |
7741 | { | |
db557034 | 7742 | int fpr = *s - '0'; |
af6bdddf | 7743 | ++s; |
5f47d35b AM |
7744 | if (is_space_char (*s)) |
7745 | ++s; | |
7746 | if (*s == ')') | |
7747 | { | |
7748 | *end_op = s + 1; | |
db557034 AM |
7749 | r = hash_find (reg_hash, "st(0)"); |
7750 | know (r); | |
7751 | return r + fpr; | |
5f47d35b | 7752 | } |
5f47d35b | 7753 | } |
47926f60 | 7754 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
7755 | return (const reg_entry *) NULL; |
7756 | } | |
7757 | } | |
7758 | ||
a60de03c JB |
7759 | if (r == NULL || allow_pseudo_reg) |
7760 | return r; | |
7761 | ||
0dfbf9d7 | 7762 | if (operand_type_all_zero (&r->reg_type)) |
a60de03c JB |
7763 | return (const reg_entry *) NULL; |
7764 | ||
192dc9c6 JB |
7765 | if ((r->reg_type.bitfield.reg32 |
7766 | || r->reg_type.bitfield.sreg3 | |
7767 | || r->reg_type.bitfield.control | |
7768 | || r->reg_type.bitfield.debug | |
7769 | || r->reg_type.bitfield.test) | |
7770 | && !cpu_arch_flags.bitfield.cpui386) | |
7771 | return (const reg_entry *) NULL; | |
7772 | ||
7773 | if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx) | |
7774 | return (const reg_entry *) NULL; | |
7775 | ||
7776 | if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse) | |
7777 | return (const reg_entry *) NULL; | |
7778 | ||
40f12533 L |
7779 | if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx) |
7780 | return (const reg_entry *) NULL; | |
7781 | ||
db51cc60 | 7782 | /* Don't allow fake index register unless allow_index_reg isn't 0. */ |
a60de03c | 7783 | if (!allow_index_reg |
db51cc60 L |
7784 | && (r->reg_num == RegEiz || r->reg_num == RegRiz)) |
7785 | return (const reg_entry *) NULL; | |
7786 | ||
a60de03c JB |
7787 | if (((r->reg_flags & (RegRex64 | RegRex)) |
7788 | || r->reg_type.bitfield.reg64) | |
40fb9820 | 7789 | && (!cpu_arch_flags.bitfield.cpulm |
0dfbf9d7 | 7790 | || !operand_type_equal (&r->reg_type, &control)) |
1ae00879 | 7791 | && flag_code != CODE_64BIT) |
20f0a1fc | 7792 | return (const reg_entry *) NULL; |
1ae00879 | 7793 | |
b7240065 JB |
7794 | if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax) |
7795 | return (const reg_entry *) NULL; | |
7796 | ||
252b5132 RH |
7797 | return r; |
7798 | } | |
4d1bb795 JB |
7799 | |
7800 | /* REG_STRING starts *before* REGISTER_PREFIX. */ | |
7801 | ||
7802 | static const reg_entry * | |
7803 | parse_register (char *reg_string, char **end_op) | |
7804 | { | |
7805 | const reg_entry *r; | |
7806 | ||
7807 | if (*reg_string == REGISTER_PREFIX || allow_naked_reg) | |
7808 | r = parse_real_register (reg_string, end_op); | |
7809 | else | |
7810 | r = NULL; | |
7811 | if (!r) | |
7812 | { | |
7813 | char *save = input_line_pointer; | |
7814 | char c; | |
7815 | symbolS *symbolP; | |
7816 | ||
7817 | input_line_pointer = reg_string; | |
7818 | c = get_symbol_end (); | |
7819 | symbolP = symbol_find (reg_string); | |
7820 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) | |
7821 | { | |
7822 | const expressionS *e = symbol_get_value_expression (symbolP); | |
7823 | ||
7824 | know (e->X_op == O_register); | |
4eed87de | 7825 | know (e->X_add_number >= 0 |
c3fe08fa | 7826 | && (valueT) e->X_add_number < i386_regtab_size); |
4d1bb795 JB |
7827 | r = i386_regtab + e->X_add_number; |
7828 | *end_op = input_line_pointer; | |
7829 | } | |
7830 | *input_line_pointer = c; | |
7831 | input_line_pointer = save; | |
7832 | } | |
7833 | return r; | |
7834 | } | |
7835 | ||
7836 | int | |
7837 | i386_parse_name (char *name, expressionS *e, char *nextcharP) | |
7838 | { | |
7839 | const reg_entry *r; | |
7840 | char *end = input_line_pointer; | |
7841 | ||
7842 | *end = *nextcharP; | |
7843 | r = parse_register (name, &input_line_pointer); | |
7844 | if (r && end <= input_line_pointer) | |
7845 | { | |
7846 | *nextcharP = *input_line_pointer; | |
7847 | *input_line_pointer = 0; | |
7848 | e->X_op = O_register; | |
7849 | e->X_add_number = r - i386_regtab; | |
7850 | return 1; | |
7851 | } | |
7852 | input_line_pointer = end; | |
7853 | *end = 0; | |
7854 | return 0; | |
7855 | } | |
7856 | ||
7857 | void | |
7858 | md_operand (expressionS *e) | |
7859 | { | |
7860 | if (*input_line_pointer == REGISTER_PREFIX) | |
7861 | { | |
7862 | char *end; | |
7863 | const reg_entry *r = parse_real_register (input_line_pointer, &end); | |
7864 | ||
7865 | if (r) | |
7866 | { | |
7867 | e->X_op = O_register; | |
7868 | e->X_add_number = r - i386_regtab; | |
7869 | input_line_pointer = end; | |
7870 | } | |
7871 | } | |
7872 | } | |
7873 | ||
252b5132 | 7874 | \f |
4cc782b5 | 7875 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
12b55ccc | 7876 | const char *md_shortopts = "kVQ:sqn"; |
252b5132 | 7877 | #else |
12b55ccc | 7878 | const char *md_shortopts = "qn"; |
252b5132 | 7879 | #endif |
6e0b89ee | 7880 | |
3e73aa7c | 7881 | #define OPTION_32 (OPTION_MD_BASE + 0) |
b3b91714 AM |
7882 | #define OPTION_64 (OPTION_MD_BASE + 1) |
7883 | #define OPTION_DIVIDE (OPTION_MD_BASE + 2) | |
9103f4f4 L |
7884 | #define OPTION_MARCH (OPTION_MD_BASE + 3) |
7885 | #define OPTION_MTUNE (OPTION_MD_BASE + 4) | |
1efbbeb4 L |
7886 | #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) |
7887 | #define OPTION_MSYNTAX (OPTION_MD_BASE + 6) | |
7888 | #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) | |
7889 | #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) | |
7890 | #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9) | |
c0f3af97 | 7891 | #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10) |
daf50ae7 | 7892 | #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11) |
b3b91714 | 7893 | |
99ad8390 NC |
7894 | struct option md_longopts[] = |
7895 | { | |
3e73aa7c | 7896 | {"32", no_argument, NULL, OPTION_32}, |
99ad8390 | 7897 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP) |
3e73aa7c | 7898 | {"64", no_argument, NULL, OPTION_64}, |
6e0b89ee | 7899 | #endif |
b3b91714 | 7900 | {"divide", no_argument, NULL, OPTION_DIVIDE}, |
9103f4f4 L |
7901 | {"march", required_argument, NULL, OPTION_MARCH}, |
7902 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1efbbeb4 L |
7903 | {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, |
7904 | {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, | |
7905 | {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, | |
7906 | {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, | |
7907 | {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC}, | |
c0f3af97 | 7908 | {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX}, |
daf50ae7 | 7909 | {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK}, |
252b5132 RH |
7910 | {NULL, no_argument, NULL, 0} |
7911 | }; | |
7912 | size_t md_longopts_size = sizeof (md_longopts); | |
7913 | ||
7914 | int | |
9103f4f4 | 7915 | md_parse_option (int c, char *arg) |
252b5132 | 7916 | { |
9103f4f4 | 7917 | unsigned int i; |
6305a203 | 7918 | char *arch, *next; |
9103f4f4 | 7919 | |
252b5132 RH |
7920 | switch (c) |
7921 | { | |
12b55ccc L |
7922 | case 'n': |
7923 | optimize_align_code = 0; | |
7924 | break; | |
7925 | ||
a38cf1db AM |
7926 | case 'q': |
7927 | quiet_warnings = 1; | |
252b5132 RH |
7928 | break; |
7929 | ||
7930 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
7931 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
7932 | should be emitted or not. FIXME: Not implemented. */ | |
7933 | case 'Q': | |
252b5132 RH |
7934 | break; |
7935 | ||
7936 | /* -V: SVR4 argument to print version ID. */ | |
7937 | case 'V': | |
7938 | print_version_id (); | |
7939 | break; | |
7940 | ||
a38cf1db AM |
7941 | /* -k: Ignore for FreeBSD compatibility. */ |
7942 | case 'k': | |
252b5132 | 7943 | break; |
4cc782b5 ILT |
7944 | |
7945 | case 's': | |
7946 | /* -s: On i386 Solaris, this tells the native assembler to use | |
29b0f896 | 7947 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
4cc782b5 | 7948 | break; |
99ad8390 NC |
7949 | #endif |
7950 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP) | |
3e73aa7c JH |
7951 | case OPTION_64: |
7952 | { | |
7953 | const char **list, **l; | |
7954 | ||
3e73aa7c JH |
7955 | list = bfd_target_list (); |
7956 | for (l = list; *l != NULL; l++) | |
8620418b | 7957 | if (CONST_STRNEQ (*l, "elf64-x86-64") |
99ad8390 NC |
7958 | || strcmp (*l, "coff-x86-64") == 0 |
7959 | || strcmp (*l, "pe-x86-64") == 0 | |
7960 | || strcmp (*l, "pei-x86-64") == 0) | |
6e0b89ee AM |
7961 | { |
7962 | default_arch = "x86_64"; | |
7963 | break; | |
7964 | } | |
3e73aa7c | 7965 | if (*l == NULL) |
6e0b89ee | 7966 | as_fatal (_("No compiled in support for x86_64")); |
3e73aa7c JH |
7967 | free (list); |
7968 | } | |
7969 | break; | |
7970 | #endif | |
252b5132 | 7971 | |
6e0b89ee AM |
7972 | case OPTION_32: |
7973 | default_arch = "i386"; | |
7974 | break; | |
7975 | ||
b3b91714 AM |
7976 | case OPTION_DIVIDE: |
7977 | #ifdef SVR4_COMMENT_CHARS | |
7978 | { | |
7979 | char *n, *t; | |
7980 | const char *s; | |
7981 | ||
7982 | n = (char *) xmalloc (strlen (i386_comment_chars) + 1); | |
7983 | t = n; | |
7984 | for (s = i386_comment_chars; *s != '\0'; s++) | |
7985 | if (*s != '/') | |
7986 | *t++ = *s; | |
7987 | *t = '\0'; | |
7988 | i386_comment_chars = n; | |
7989 | } | |
7990 | #endif | |
7991 | break; | |
7992 | ||
9103f4f4 | 7993 | case OPTION_MARCH: |
6305a203 L |
7994 | arch = xstrdup (arg); |
7995 | do | |
9103f4f4 | 7996 | { |
6305a203 L |
7997 | if (*arch == '.') |
7998 | as_fatal (_("Invalid -march= option: `%s'"), arg); | |
7999 | next = strchr (arch, '+'); | |
8000 | if (next) | |
8001 | *next++ = '\0'; | |
8002 | for (i = 0; i < ARRAY_SIZE (cpu_arch); i++) | |
9103f4f4 | 8003 | { |
6305a203 | 8004 | if (strcmp (arch, cpu_arch [i].name) == 0) |
ccc9c027 | 8005 | { |
6305a203 L |
8006 | /* Processor. */ |
8007 | cpu_arch_name = cpu_arch[i].name; | |
8008 | cpu_sub_arch_name = NULL; | |
8009 | cpu_arch_flags = cpu_arch[i].flags; | |
8010 | cpu_arch_isa = cpu_arch[i].type; | |
8011 | cpu_arch_isa_flags = cpu_arch[i].flags; | |
8012 | if (!cpu_arch_tune_set) | |
8013 | { | |
8014 | cpu_arch_tune = cpu_arch_isa; | |
8015 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
8016 | } | |
8017 | break; | |
8018 | } | |
8019 | else if (*cpu_arch [i].name == '.' | |
8020 | && strcmp (arch, cpu_arch [i].name + 1) == 0) | |
8021 | { | |
8022 | /* ISA entension. */ | |
8023 | i386_cpu_flags flags; | |
8024 | flags = cpu_flags_or (cpu_arch_flags, | |
8025 | cpu_arch[i].flags); | |
0dfbf9d7 | 8026 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
6305a203 L |
8027 | { |
8028 | if (cpu_sub_arch_name) | |
8029 | { | |
8030 | char *name = cpu_sub_arch_name; | |
8031 | cpu_sub_arch_name = concat (name, | |
8032 | cpu_arch[i].name, | |
1bf57e9f | 8033 | (const char *) NULL); |
6305a203 L |
8034 | free (name); |
8035 | } | |
8036 | else | |
8037 | cpu_sub_arch_name = xstrdup (cpu_arch[i].name); | |
8038 | cpu_arch_flags = flags; | |
8039 | } | |
8040 | break; | |
ccc9c027 | 8041 | } |
9103f4f4 | 8042 | } |
6305a203 L |
8043 | |
8044 | if (i >= ARRAY_SIZE (cpu_arch)) | |
8045 | as_fatal (_("Invalid -march= option: `%s'"), arg); | |
8046 | ||
8047 | arch = next; | |
9103f4f4 | 8048 | } |
6305a203 | 8049 | while (next != NULL ); |
9103f4f4 L |
8050 | break; |
8051 | ||
8052 | case OPTION_MTUNE: | |
8053 | if (*arg == '.') | |
8054 | as_fatal (_("Invalid -mtune= option: `%s'"), arg); | |
8055 | for (i = 0; i < ARRAY_SIZE (cpu_arch); i++) | |
8056 | { | |
8057 | if (strcmp (arg, cpu_arch [i].name) == 0) | |
8058 | { | |
ccc9c027 | 8059 | cpu_arch_tune_set = 1; |
9103f4f4 L |
8060 | cpu_arch_tune = cpu_arch [i].type; |
8061 | cpu_arch_tune_flags = cpu_arch[i].flags; | |
8062 | break; | |
8063 | } | |
8064 | } | |
8065 | if (i >= ARRAY_SIZE (cpu_arch)) | |
8066 | as_fatal (_("Invalid -mtune= option: `%s'"), arg); | |
8067 | break; | |
8068 | ||
1efbbeb4 L |
8069 | case OPTION_MMNEMONIC: |
8070 | if (strcasecmp (arg, "att") == 0) | |
8071 | intel_mnemonic = 0; | |
8072 | else if (strcasecmp (arg, "intel") == 0) | |
8073 | intel_mnemonic = 1; | |
8074 | else | |
8075 | as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg); | |
8076 | break; | |
8077 | ||
8078 | case OPTION_MSYNTAX: | |
8079 | if (strcasecmp (arg, "att") == 0) | |
8080 | intel_syntax = 0; | |
8081 | else if (strcasecmp (arg, "intel") == 0) | |
8082 | intel_syntax = 1; | |
8083 | else | |
8084 | as_fatal (_("Invalid -msyntax= option: `%s'"), arg); | |
8085 | break; | |
8086 | ||
8087 | case OPTION_MINDEX_REG: | |
8088 | allow_index_reg = 1; | |
8089 | break; | |
8090 | ||
8091 | case OPTION_MNAKED_REG: | |
8092 | allow_naked_reg = 1; | |
8093 | break; | |
8094 | ||
8095 | case OPTION_MOLD_GCC: | |
8096 | old_gcc = 1; | |
1efbbeb4 L |
8097 | break; |
8098 | ||
c0f3af97 L |
8099 | case OPTION_MSSE2AVX: |
8100 | sse2avx = 1; | |
8101 | break; | |
8102 | ||
daf50ae7 L |
8103 | case OPTION_MSSE_CHECK: |
8104 | if (strcasecmp (arg, "error") == 0) | |
8105 | sse_check = sse_check_error; | |
8106 | else if (strcasecmp (arg, "warning") == 0) | |
8107 | sse_check = sse_check_warning; | |
8108 | else if (strcasecmp (arg, "none") == 0) | |
8109 | sse_check = sse_check_none; | |
8110 | else | |
8111 | as_fatal (_("Invalid -msse-check= option: `%s'"), arg); | |
8112 | break; | |
8113 | ||
252b5132 RH |
8114 | default: |
8115 | return 0; | |
8116 | } | |
8117 | return 1; | |
8118 | } | |
8119 | ||
8120 | void | |
8121 | md_show_usage (stream) | |
8122 | FILE *stream; | |
8123 | { | |
4cc782b5 ILT |
8124 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8125 | fprintf (stream, _("\ | |
a38cf1db AM |
8126 | -Q ignored\n\ |
8127 | -V print assembler version number\n\ | |
b3b91714 AM |
8128 | -k ignored\n")); |
8129 | #endif | |
8130 | fprintf (stream, _("\ | |
12b55ccc | 8131 | -n Do not optimize code alignment\n\ |
b3b91714 AM |
8132 | -q quieten some warnings\n")); |
8133 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
8134 | fprintf (stream, _("\ | |
a38cf1db | 8135 | -s ignored\n")); |
b3b91714 | 8136 | #endif |
751d281c L |
8137 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP) |
8138 | fprintf (stream, _("\ | |
8139 | --32/--64 generate 32bit/64bit code\n")); | |
8140 | #endif | |
b3b91714 AM |
8141 | #ifdef SVR4_COMMENT_CHARS |
8142 | fprintf (stream, _("\ | |
8143 | --divide do not treat `/' as a comment character\n")); | |
a38cf1db AM |
8144 | #else |
8145 | fprintf (stream, _("\ | |
b3b91714 | 8146 | --divide ignored\n")); |
4cc782b5 | 8147 | #endif |
9103f4f4 | 8148 | fprintf (stream, _("\ |
6305a203 L |
8149 | -march=CPU[,+EXTENSION...]\n\ |
8150 | generate code for CPU and EXTENSION, CPU is one of:\n\ | |
2cb4f3d5 L |
8151 | i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\ |
8152 | pentiumii, pentiumiii, pentium4, prescott, nocona,\n\ | |
8153 | core, core2, k6, k6_2, athlon, k8, amdfam10,\n\ | |
8154 | generic32, generic64\n\ | |
599121aa L |
8155 | EXTENSION is combination of:\n\ |
8156 | mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\ | |
f1f8f695 L |
8157 | avx, vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\ |
8158 | 3dnow, 3dnowa, sse4a, sse5, svme, abm, padlock\n")); | |
6305a203 | 8159 | fprintf (stream, _("\ |
2cb4f3d5 L |
8160 | -mtune=CPU optimize for CPU, CPU is one of:\n\ |
8161 | i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\ | |
8162 | pentiumii, pentiumiii, pentium4, prescott, nocona,\n\ | |
8163 | core, core2, k6, k6_2, athlon, k8, amdfam10,\n\ | |
8164 | generic32, generic64\n")); | |
ba104c83 | 8165 | fprintf (stream, _("\ |
c0f3af97 L |
8166 | -msse2avx encode SSE instructions with VEX prefix\n")); |
8167 | fprintf (stream, _("\ | |
daf50ae7 L |
8168 | -msse-check=[none|error|warning]\n\ |
8169 | check SSE instructions\n")); | |
8170 | fprintf (stream, _("\ | |
ba104c83 L |
8171 | -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n")); |
8172 | fprintf (stream, _("\ | |
8173 | -msyntax=[att|intel] use AT&T/Intel syntax\n")); | |
8174 | fprintf (stream, _("\ | |
8175 | -mindex-reg support pseudo index registers\n")); | |
8176 | fprintf (stream, _("\ | |
8177 | -mnaked-reg don't require `%%' prefix for registers\n")); | |
8178 | fprintf (stream, _("\ | |
8179 | -mold-gcc support old (<= 2.8.1) versions of gcc\n")); | |
252b5132 RH |
8180 | } |
8181 | ||
3e73aa7c | 8182 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
872ce6ff | 8183 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP)) |
252b5132 RH |
8184 | |
8185 | /* Pick the target format to use. */ | |
8186 | ||
47926f60 | 8187 | const char * |
e3bb37b5 | 8188 | i386_target_format (void) |
252b5132 | 8189 | { |
3e73aa7c | 8190 | if (!strcmp (default_arch, "x86_64")) |
9103f4f4 L |
8191 | { |
8192 | set_code_flag (CODE_64BIT); | |
0dfbf9d7 | 8193 | if (cpu_flags_all_zero (&cpu_arch_isa_flags)) |
40fb9820 L |
8194 | { |
8195 | cpu_arch_isa_flags.bitfield.cpui186 = 1; | |
8196 | cpu_arch_isa_flags.bitfield.cpui286 = 1; | |
8197 | cpu_arch_isa_flags.bitfield.cpui386 = 1; | |
8198 | cpu_arch_isa_flags.bitfield.cpui486 = 1; | |
8199 | cpu_arch_isa_flags.bitfield.cpui586 = 1; | |
8200 | cpu_arch_isa_flags.bitfield.cpui686 = 1; | |
8201 | cpu_arch_isa_flags.bitfield.cpup4 = 1; | |
8202 | cpu_arch_isa_flags.bitfield.cpummx= 1; | |
40fb9820 L |
8203 | cpu_arch_isa_flags.bitfield.cpusse = 1; |
8204 | cpu_arch_isa_flags.bitfield.cpusse2 = 1; | |
8205 | } | |
0dfbf9d7 | 8206 | if (cpu_flags_all_zero (&cpu_arch_tune_flags)) |
40fb9820 L |
8207 | { |
8208 | cpu_arch_tune_flags.bitfield.cpui186 = 1; | |
8209 | cpu_arch_tune_flags.bitfield.cpui286 = 1; | |
8210 | cpu_arch_tune_flags.bitfield.cpui386 = 1; | |
8211 | cpu_arch_tune_flags.bitfield.cpui486 = 1; | |
8212 | cpu_arch_tune_flags.bitfield.cpui586 = 1; | |
8213 | cpu_arch_tune_flags.bitfield.cpui686 = 1; | |
8214 | cpu_arch_tune_flags.bitfield.cpup4 = 1; | |
8215 | cpu_arch_tune_flags.bitfield.cpummx= 1; | |
40fb9820 L |
8216 | cpu_arch_tune_flags.bitfield.cpusse = 1; |
8217 | cpu_arch_tune_flags.bitfield.cpusse2 = 1; | |
8218 | } | |
9103f4f4 | 8219 | } |
3e73aa7c | 8220 | else if (!strcmp (default_arch, "i386")) |
9103f4f4 L |
8221 | { |
8222 | set_code_flag (CODE_32BIT); | |
0dfbf9d7 | 8223 | if (cpu_flags_all_zero (&cpu_arch_isa_flags)) |
40fb9820 L |
8224 | { |
8225 | cpu_arch_isa_flags.bitfield.cpui186 = 1; | |
8226 | cpu_arch_isa_flags.bitfield.cpui286 = 1; | |
8227 | cpu_arch_isa_flags.bitfield.cpui386 = 1; | |
8228 | } | |
0dfbf9d7 | 8229 | if (cpu_flags_all_zero (&cpu_arch_tune_flags)) |
40fb9820 L |
8230 | { |
8231 | cpu_arch_tune_flags.bitfield.cpui186 = 1; | |
8232 | cpu_arch_tune_flags.bitfield.cpui286 = 1; | |
8233 | cpu_arch_tune_flags.bitfield.cpui386 = 1; | |
8234 | } | |
9103f4f4 | 8235 | } |
3e73aa7c JH |
8236 | else |
8237 | as_fatal (_("Unknown architecture")); | |
252b5132 RH |
8238 | switch (OUTPUT_FLAVOR) |
8239 | { | |
872ce6ff L |
8240 | #ifdef TE_PEP |
8241 | case bfd_target_coff_flavour: | |
8242 | return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386"; | |
8243 | break; | |
8244 | #endif | |
4c63da97 AM |
8245 | #ifdef OBJ_MAYBE_AOUT |
8246 | case bfd_target_aout_flavour: | |
47926f60 | 8247 | return AOUT_TARGET_FORMAT; |
4c63da97 AM |
8248 | #endif |
8249 | #ifdef OBJ_MAYBE_COFF | |
252b5132 RH |
8250 | case bfd_target_coff_flavour: |
8251 | return "coff-i386"; | |
4c63da97 | 8252 | #endif |
3e73aa7c | 8253 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 8254 | case bfd_target_elf_flavour: |
3e73aa7c | 8255 | { |
e5cb08ac | 8256 | if (flag_code == CODE_64BIT) |
4fa24527 JB |
8257 | { |
8258 | object_64bit = 1; | |
8259 | use_rela_relocations = 1; | |
8260 | } | |
9d7cbccd | 8261 | return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT; |
3e73aa7c | 8262 | } |
4c63da97 | 8263 | #endif |
252b5132 RH |
8264 | default: |
8265 | abort (); | |
8266 | return NULL; | |
8267 | } | |
8268 | } | |
8269 | ||
47926f60 | 8270 | #endif /* OBJ_MAYBE_ more than one */ |
a847613f AM |
8271 | |
8272 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) | |
e3bb37b5 L |
8273 | void |
8274 | i386_elf_emit_arch_note (void) | |
a847613f | 8275 | { |
718ddfc0 | 8276 | if (IS_ELF && cpu_arch_name != NULL) |
a847613f AM |
8277 | { |
8278 | char *p; | |
8279 | asection *seg = now_seg; | |
8280 | subsegT subseg = now_subseg; | |
8281 | Elf_Internal_Note i_note; | |
8282 | Elf_External_Note e_note; | |
8283 | asection *note_secp; | |
8284 | int len; | |
8285 | ||
8286 | /* Create the .note section. */ | |
8287 | note_secp = subseg_new (".note", 0); | |
8288 | bfd_set_section_flags (stdoutput, | |
8289 | note_secp, | |
8290 | SEC_HAS_CONTENTS | SEC_READONLY); | |
8291 | ||
8292 | /* Process the arch string. */ | |
8293 | len = strlen (cpu_arch_name); | |
8294 | ||
8295 | i_note.namesz = len + 1; | |
8296 | i_note.descsz = 0; | |
8297 | i_note.type = NT_ARCH; | |
8298 | p = frag_more (sizeof (e_note.namesz)); | |
8299 | md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz)); | |
8300 | p = frag_more (sizeof (e_note.descsz)); | |
8301 | md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz)); | |
8302 | p = frag_more (sizeof (e_note.type)); | |
8303 | md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type)); | |
8304 | p = frag_more (len + 1); | |
8305 | strcpy (p, cpu_arch_name); | |
8306 | ||
8307 | frag_align (2, 0, 0); | |
8308 | ||
8309 | subseg_set (seg, subseg); | |
8310 | } | |
8311 | } | |
8312 | #endif | |
252b5132 | 8313 | \f |
252b5132 RH |
8314 | symbolS * |
8315 | md_undefined_symbol (name) | |
8316 | char *name; | |
8317 | { | |
18dc2407 ILT |
8318 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
8319 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
8320 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
8321 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
8322 | { |
8323 | if (!GOT_symbol) | |
8324 | { | |
8325 | if (symbol_find (name)) | |
8326 | as_bad (_("GOT already in symbol table")); | |
8327 | GOT_symbol = symbol_new (name, undefined_section, | |
8328 | (valueT) 0, &zero_address_frag); | |
8329 | }; | |
8330 | return GOT_symbol; | |
8331 | } | |
252b5132 RH |
8332 | return 0; |
8333 | } | |
8334 | ||
8335 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 8336 | |
252b5132 RH |
8337 | valueT |
8338 | md_section_align (segment, size) | |
ab9da554 | 8339 | segT segment ATTRIBUTE_UNUSED; |
252b5132 RH |
8340 | valueT size; |
8341 | { | |
4c63da97 AM |
8342 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
8343 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
8344 | { | |
8345 | /* For a.out, force the section size to be aligned. If we don't do | |
8346 | this, BFD will align it for us, but it will not write out the | |
8347 | final bytes of the section. This may be a bug in BFD, but it is | |
8348 | easier to fix it here since that is how the other a.out targets | |
8349 | work. */ | |
8350 | int align; | |
8351 | ||
8352 | align = bfd_get_section_alignment (stdoutput, segment); | |
8353 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); | |
8354 | } | |
252b5132 RH |
8355 | #endif |
8356 | ||
8357 | return size; | |
8358 | } | |
8359 | ||
8360 | /* On the i386, PC-relative offsets are relative to the start of the | |
8361 | next instruction. That is, the address of the offset, plus its | |
8362 | size, since the offset is always the last part of the insn. */ | |
8363 | ||
8364 | long | |
e3bb37b5 | 8365 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
8366 | { |
8367 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
8368 | } | |
8369 | ||
8370 | #ifndef I386COFF | |
8371 | ||
8372 | static void | |
e3bb37b5 | 8373 | s_bss (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 8374 | { |
29b0f896 | 8375 | int temp; |
252b5132 | 8376 | |
8a75718c JB |
8377 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8378 | if (IS_ELF) | |
8379 | obj_elf_section_change_hook (); | |
8380 | #endif | |
252b5132 RH |
8381 | temp = get_absolute_expression (); |
8382 | subseg_set (bss_section, (subsegT) temp); | |
8383 | demand_empty_rest_of_line (); | |
8384 | } | |
8385 | ||
8386 | #endif | |
8387 | ||
252b5132 | 8388 | void |
e3bb37b5 | 8389 | i386_validate_fix (fixS *fixp) |
252b5132 RH |
8390 | { |
8391 | if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol) | |
8392 | { | |
23df1078 JH |
8393 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
8394 | { | |
4fa24527 | 8395 | if (!object_64bit) |
23df1078 JH |
8396 | abort (); |
8397 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
8398 | } | |
8399 | else | |
8400 | { | |
4fa24527 | 8401 | if (!object_64bit) |
d6ab8113 JB |
8402 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; |
8403 | else | |
8404 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; | |
23df1078 | 8405 | } |
252b5132 RH |
8406 | fixp->fx_subsy = 0; |
8407 | } | |
8408 | } | |
8409 | ||
252b5132 RH |
8410 | arelent * |
8411 | tc_gen_reloc (section, fixp) | |
ab9da554 | 8412 | asection *section ATTRIBUTE_UNUSED; |
252b5132 RH |
8413 | fixS *fixp; |
8414 | { | |
8415 | arelent *rel; | |
8416 | bfd_reloc_code_real_type code; | |
8417 | ||
8418 | switch (fixp->fx_r_type) | |
8419 | { | |
3e73aa7c JH |
8420 | case BFD_RELOC_X86_64_PLT32: |
8421 | case BFD_RELOC_X86_64_GOT32: | |
8422 | case BFD_RELOC_X86_64_GOTPCREL: | |
252b5132 RH |
8423 | case BFD_RELOC_386_PLT32: |
8424 | case BFD_RELOC_386_GOT32: | |
8425 | case BFD_RELOC_386_GOTOFF: | |
8426 | case BFD_RELOC_386_GOTPC: | |
13ae64f3 JJ |
8427 | case BFD_RELOC_386_TLS_GD: |
8428 | case BFD_RELOC_386_TLS_LDM: | |
8429 | case BFD_RELOC_386_TLS_LDO_32: | |
8430 | case BFD_RELOC_386_TLS_IE_32: | |
37e55690 JJ |
8431 | case BFD_RELOC_386_TLS_IE: |
8432 | case BFD_RELOC_386_TLS_GOTIE: | |
13ae64f3 JJ |
8433 | case BFD_RELOC_386_TLS_LE_32: |
8434 | case BFD_RELOC_386_TLS_LE: | |
67a4f2b7 AO |
8435 | case BFD_RELOC_386_TLS_GOTDESC: |
8436 | case BFD_RELOC_386_TLS_DESC_CALL: | |
bffbf940 JJ |
8437 | case BFD_RELOC_X86_64_TLSGD: |
8438 | case BFD_RELOC_X86_64_TLSLD: | |
8439 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 8440 | case BFD_RELOC_X86_64_DTPOFF64: |
bffbf940 JJ |
8441 | case BFD_RELOC_X86_64_GOTTPOFF: |
8442 | case BFD_RELOC_X86_64_TPOFF32: | |
d6ab8113 JB |
8443 | case BFD_RELOC_X86_64_TPOFF64: |
8444 | case BFD_RELOC_X86_64_GOTOFF64: | |
8445 | case BFD_RELOC_X86_64_GOTPC32: | |
7b81dfbb AJ |
8446 | case BFD_RELOC_X86_64_GOT64: |
8447 | case BFD_RELOC_X86_64_GOTPCREL64: | |
8448 | case BFD_RELOC_X86_64_GOTPC64: | |
8449 | case BFD_RELOC_X86_64_GOTPLT64: | |
8450 | case BFD_RELOC_X86_64_PLTOFF64: | |
67a4f2b7 AO |
8451 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
8452 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
252b5132 RH |
8453 | case BFD_RELOC_RVA: |
8454 | case BFD_RELOC_VTABLE_ENTRY: | |
8455 | case BFD_RELOC_VTABLE_INHERIT: | |
6482c264 NC |
8456 | #ifdef TE_PE |
8457 | case BFD_RELOC_32_SECREL: | |
8458 | #endif | |
252b5132 RH |
8459 | code = fixp->fx_r_type; |
8460 | break; | |
dbbaec26 L |
8461 | case BFD_RELOC_X86_64_32S: |
8462 | if (!fixp->fx_pcrel) | |
8463 | { | |
8464 | /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ | |
8465 | code = fixp->fx_r_type; | |
8466 | break; | |
8467 | } | |
252b5132 | 8468 | default: |
93382f6d | 8469 | if (fixp->fx_pcrel) |
252b5132 | 8470 | { |
93382f6d AM |
8471 | switch (fixp->fx_size) |
8472 | { | |
8473 | default: | |
b091f402 AM |
8474 | as_bad_where (fixp->fx_file, fixp->fx_line, |
8475 | _("can not do %d byte pc-relative relocation"), | |
8476 | fixp->fx_size); | |
93382f6d AM |
8477 | code = BFD_RELOC_32_PCREL; |
8478 | break; | |
8479 | case 1: code = BFD_RELOC_8_PCREL; break; | |
8480 | case 2: code = BFD_RELOC_16_PCREL; break; | |
8481 | case 4: code = BFD_RELOC_32_PCREL; break; | |
d6ab8113 JB |
8482 | #ifdef BFD64 |
8483 | case 8: code = BFD_RELOC_64_PCREL; break; | |
8484 | #endif | |
93382f6d AM |
8485 | } |
8486 | } | |
8487 | else | |
8488 | { | |
8489 | switch (fixp->fx_size) | |
8490 | { | |
8491 | default: | |
b091f402 AM |
8492 | as_bad_where (fixp->fx_file, fixp->fx_line, |
8493 | _("can not do %d byte relocation"), | |
8494 | fixp->fx_size); | |
93382f6d AM |
8495 | code = BFD_RELOC_32; |
8496 | break; | |
8497 | case 1: code = BFD_RELOC_8; break; | |
8498 | case 2: code = BFD_RELOC_16; break; | |
8499 | case 4: code = BFD_RELOC_32; break; | |
937149dd | 8500 | #ifdef BFD64 |
3e73aa7c | 8501 | case 8: code = BFD_RELOC_64; break; |
937149dd | 8502 | #endif |
93382f6d | 8503 | } |
252b5132 RH |
8504 | } |
8505 | break; | |
8506 | } | |
252b5132 | 8507 | |
d182319b JB |
8508 | if ((code == BFD_RELOC_32 |
8509 | || code == BFD_RELOC_32_PCREL | |
8510 | || code == BFD_RELOC_X86_64_32S) | |
252b5132 RH |
8511 | && GOT_symbol |
8512 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c | 8513 | { |
4fa24527 | 8514 | if (!object_64bit) |
d6ab8113 JB |
8515 | code = BFD_RELOC_386_GOTPC; |
8516 | else | |
8517 | code = BFD_RELOC_X86_64_GOTPC32; | |
3e73aa7c | 8518 | } |
7b81dfbb AJ |
8519 | if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) |
8520 | && GOT_symbol | |
8521 | && fixp->fx_addsy == GOT_symbol) | |
8522 | { | |
8523 | code = BFD_RELOC_X86_64_GOTPC64; | |
8524 | } | |
252b5132 RH |
8525 | |
8526 | rel = (arelent *) xmalloc (sizeof (arelent)); | |
49309057 ILT |
8527 | rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
8528 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
252b5132 RH |
8529 | |
8530 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
c87db184 | 8531 | |
3e73aa7c JH |
8532 | if (!use_rela_relocations) |
8533 | { | |
8534 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
8535 | vtable entry to be used in the relocation's section offset. */ | |
8536 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
8537 | rel->address = fixp->fx_offset; | |
252b5132 | 8538 | |
c6682705 | 8539 | rel->addend = 0; |
3e73aa7c JH |
8540 | } |
8541 | /* Use the rela in 64bit mode. */ | |
252b5132 | 8542 | else |
3e73aa7c | 8543 | { |
062cd5e7 AS |
8544 | if (!fixp->fx_pcrel) |
8545 | rel->addend = fixp->fx_offset; | |
8546 | else | |
8547 | switch (code) | |
8548 | { | |
8549 | case BFD_RELOC_X86_64_PLT32: | |
8550 | case BFD_RELOC_X86_64_GOT32: | |
8551 | case BFD_RELOC_X86_64_GOTPCREL: | |
bffbf940 JJ |
8552 | case BFD_RELOC_X86_64_TLSGD: |
8553 | case BFD_RELOC_X86_64_TLSLD: | |
8554 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 AO |
8555 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
8556 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
062cd5e7 AS |
8557 | rel->addend = fixp->fx_offset - fixp->fx_size; |
8558 | break; | |
8559 | default: | |
8560 | rel->addend = (section->vma | |
8561 | - fixp->fx_size | |
8562 | + fixp->fx_addnumber | |
8563 | + md_pcrel_from (fixp)); | |
8564 | break; | |
8565 | } | |
3e73aa7c JH |
8566 | } |
8567 | ||
252b5132 RH |
8568 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
8569 | if (rel->howto == NULL) | |
8570 | { | |
8571 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 8572 | _("cannot represent relocation type %s"), |
252b5132 RH |
8573 | bfd_get_reloc_code_name (code)); |
8574 | /* Set howto to a garbage value so that we can keep going. */ | |
8575 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
8576 | assert (rel->howto != NULL); | |
8577 | } | |
8578 | ||
8579 | return rel; | |
8580 | } | |
8581 | ||
64a0c779 DN |
8582 | \f |
8583 | /* Parse operands using Intel syntax. This implements a recursive descent | |
8584 | parser based on the BNF grammar published in Appendix B of the MASM 6.1 | |
8585 | Programmer's Guide. | |
8586 | ||
8587 | FIXME: We do not recognize the full operand grammar defined in the MASM | |
8588 | documentation. In particular, all the structure/union and | |
8589 | high-level macro operands are missing. | |
8590 | ||
8591 | Uppercase words are terminals, lower case words are non-terminals. | |
8592 | Objects surrounded by double brackets '[[' ']]' are optional. Vertical | |
8593 | bars '|' denote choices. Most grammar productions are implemented in | |
8594 | functions called 'intel_<production>'. | |
8595 | ||
8596 | Initial production is 'expr'. | |
8597 | ||
9306ca4a | 8598 | addOp + | - |
64a0c779 DN |
8599 | |
8600 | alpha [a-zA-Z] | |
8601 | ||
9306ca4a JB |
8602 | binOp & | AND | \| | OR | ^ | XOR |
8603 | ||
64a0c779 DN |
8604 | byteRegister AL | AH | BL | BH | CL | CH | DL | DH |
8605 | ||
8606 | constant digits [[ radixOverride ]] | |
8607 | ||
c0f3af97 | 8608 | dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD | YMMWORD |
64a0c779 DN |
8609 | |
8610 | digits decdigit | |
b77a7acd AJ |
8611 | | digits decdigit |
8612 | | digits hexdigit | |
64a0c779 DN |
8613 | |
8614 | decdigit [0-9] | |
8615 | ||
9306ca4a JB |
8616 | e04 e04 addOp e05 |
8617 | | e05 | |
8618 | ||
8619 | e05 e05 binOp e06 | |
b77a7acd | 8620 | | e06 |
64a0c779 DN |
8621 | |
8622 | e06 e06 mulOp e09 | |
b77a7acd | 8623 | | e09 |
64a0c779 DN |
8624 | |
8625 | e09 OFFSET e10 | |
a724f0f4 JB |
8626 | | SHORT e10 |
8627 | | + e10 | |
8628 | | - e10 | |
9306ca4a JB |
8629 | | ~ e10 |
8630 | | NOT e10 | |
64a0c779 DN |
8631 | | e09 PTR e10 |
8632 | | e09 : e10 | |
8633 | | e10 | |
8634 | ||
8635 | e10 e10 [ expr ] | |
b77a7acd | 8636 | | e11 |
64a0c779 DN |
8637 | |
8638 | e11 ( expr ) | |
b77a7acd | 8639 | | [ expr ] |
64a0c779 DN |
8640 | | constant |
8641 | | dataType | |
8642 | | id | |
8643 | | $ | |
8644 | | register | |
8645 | ||
a724f0f4 | 8646 | => expr expr cmpOp e04 |
9306ca4a | 8647 | | e04 |
64a0c779 DN |
8648 | |
8649 | gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX | |
b77a7acd | 8650 | | BP | EBP | SP | ESP | DI | EDI | SI | ESI |
64a0c779 DN |
8651 | |
8652 | hexdigit a | b | c | d | e | f | |
b77a7acd | 8653 | | A | B | C | D | E | F |
64a0c779 DN |
8654 | |
8655 | id alpha | |
b77a7acd | 8656 | | id alpha |
64a0c779 DN |
8657 | | id decdigit |
8658 | ||
9306ca4a | 8659 | mulOp * | / | % | MOD | << | SHL | >> | SHR |
64a0c779 DN |
8660 | |
8661 | quote " | ' | |
8662 | ||
8663 | register specialRegister | |
b77a7acd | 8664 | | gpRegister |
64a0c779 DN |
8665 | | byteRegister |
8666 | ||
8667 | segmentRegister CS | DS | ES | FS | GS | SS | |
8668 | ||
9306ca4a | 8669 | specialRegister CR0 | CR2 | CR3 | CR4 |
b77a7acd | 8670 | | DR0 | DR1 | DR2 | DR3 | DR6 | DR7 |
64a0c779 DN |
8671 | | TR3 | TR4 | TR5 | TR6 | TR7 |
8672 | ||
64a0c779 DN |
8673 | We simplify the grammar in obvious places (e.g., register parsing is |
8674 | done by calling parse_register) and eliminate immediate left recursion | |
8675 | to implement a recursive-descent parser. | |
8676 | ||
a724f0f4 JB |
8677 | expr e04 expr' |
8678 | ||
8679 | expr' cmpOp e04 expr' | |
8680 | | Empty | |
9306ca4a JB |
8681 | |
8682 | e04 e05 e04' | |
8683 | ||
8684 | e04' addOp e05 e04' | |
8685 | | Empty | |
64a0c779 DN |
8686 | |
8687 | e05 e06 e05' | |
8688 | ||
9306ca4a | 8689 | e05' binOp e06 e05' |
b77a7acd | 8690 | | Empty |
64a0c779 DN |
8691 | |
8692 | e06 e09 e06' | |
8693 | ||
8694 | e06' mulOp e09 e06' | |
b77a7acd | 8695 | | Empty |
64a0c779 DN |
8696 | |
8697 | e09 OFFSET e10 e09' | |
a724f0f4 JB |
8698 | | SHORT e10' |
8699 | | + e10' | |
8700 | | - e10' | |
8701 | | ~ e10' | |
8702 | | NOT e10' | |
b77a7acd | 8703 | | e10 e09' |
64a0c779 DN |
8704 | |
8705 | e09' PTR e10 e09' | |
b77a7acd | 8706 | | : e10 e09' |
64a0c779 DN |
8707 | | Empty |
8708 | ||
8709 | e10 e11 e10' | |
8710 | ||
8711 | e10' [ expr ] e10' | |
b77a7acd | 8712 | | Empty |
64a0c779 DN |
8713 | |
8714 | e11 ( expr ) | |
b77a7acd | 8715 | | [ expr ] |
64a0c779 DN |
8716 | | BYTE |
8717 | | WORD | |
8718 | | DWORD | |
9306ca4a | 8719 | | FWORD |
64a0c779 | 8720 | | QWORD |
9306ca4a JB |
8721 | | TBYTE |
8722 | | OWORD | |
8723 | | XMMWORD | |
c0f3af97 | 8724 | | YMMWORD |
64a0c779 DN |
8725 | | . |
8726 | | $ | |
8727 | | register | |
8728 | | id | |
8729 | | constant */ | |
8730 | ||
8731 | /* Parsing structure for the intel syntax parser. Used to implement the | |
8732 | semantic actions for the operand grammar. */ | |
8733 | struct intel_parser_s | |
8734 | { | |
8735 | char *op_string; /* The string being parsed. */ | |
8736 | int got_a_float; /* Whether the operand is a float. */ | |
4a1805b1 | 8737 | int op_modifier; /* Operand modifier. */ |
64a0c779 | 8738 | int is_mem; /* 1 if operand is memory reference. */ |
4eed87de AM |
8739 | int in_offset; /* >=1 if parsing operand of offset. */ |
8740 | int in_bracket; /* >=1 if parsing operand in brackets. */ | |
64a0c779 DN |
8741 | const reg_entry *reg; /* Last register reference found. */ |
8742 | char *disp; /* Displacement string being built. */ | |
a724f0f4 | 8743 | char *next_operand; /* Resume point when splitting operands. */ |
64a0c779 DN |
8744 | }; |
8745 | ||
8746 | static struct intel_parser_s intel_parser; | |
8747 | ||
8748 | /* Token structure for parsing intel syntax. */ | |
8749 | struct intel_token | |
8750 | { | |
8751 | int code; /* Token code. */ | |
8752 | const reg_entry *reg; /* Register entry for register tokens. */ | |
8753 | char *str; /* String representation. */ | |
8754 | }; | |
8755 | ||
8756 | static struct intel_token cur_token, prev_token; | |
8757 | ||
50705ef4 AM |
8758 | /* Token codes for the intel parser. Since T_SHORT is already used |
8759 | by COFF, undefine it first to prevent a warning. */ | |
64a0c779 DN |
8760 | #define T_NIL -1 |
8761 | #define T_CONST 1 | |
8762 | #define T_REG 2 | |
8763 | #define T_BYTE 3 | |
8764 | #define T_WORD 4 | |
9306ca4a JB |
8765 | #define T_DWORD 5 |
8766 | #define T_FWORD 6 | |
8767 | #define T_QWORD 7 | |
8768 | #define T_TBYTE 8 | |
8769 | #define T_XMMWORD 9 | |
50705ef4 | 8770 | #undef T_SHORT |
9306ca4a JB |
8771 | #define T_SHORT 10 |
8772 | #define T_OFFSET 11 | |
8773 | #define T_PTR 12 | |
8774 | #define T_ID 13 | |
8775 | #define T_SHL 14 | |
8776 | #define T_SHR 15 | |
c0f3af97 | 8777 | #define T_YMMWORD 16 |
64a0c779 DN |
8778 | |
8779 | /* Prototypes for intel parser functions. */ | |
e3bb37b5 L |
8780 | static int intel_match_token (int); |
8781 | static void intel_putback_token (void); | |
8782 | static void intel_get_token (void); | |
8783 | static int intel_expr (void); | |
8784 | static int intel_e04 (void); | |
8785 | static int intel_e05 (void); | |
8786 | static int intel_e06 (void); | |
8787 | static int intel_e09 (void); | |
8788 | static int intel_e10 (void); | |
8789 | static int intel_e11 (void); | |
64a0c779 | 8790 | |
64a0c779 | 8791 | static int |
e3bb37b5 | 8792 | i386_intel_operand (char *operand_string, int got_a_float) |
64a0c779 DN |
8793 | { |
8794 | int ret; | |
8795 | char *p; | |
8796 | ||
a724f0f4 JB |
8797 | p = intel_parser.op_string = xstrdup (operand_string); |
8798 | intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1); | |
8799 | ||
8800 | for (;;) | |
64a0c779 | 8801 | { |
a724f0f4 JB |
8802 | /* Initialize token holders. */ |
8803 | cur_token.code = prev_token.code = T_NIL; | |
8804 | cur_token.reg = prev_token.reg = NULL; | |
8805 | cur_token.str = prev_token.str = NULL; | |
8806 | ||
8807 | /* Initialize parser structure. */ | |
8808 | intel_parser.got_a_float = got_a_float; | |
8809 | intel_parser.op_modifier = 0; | |
8810 | intel_parser.is_mem = 0; | |
8811 | intel_parser.in_offset = 0; | |
8812 | intel_parser.in_bracket = 0; | |
8813 | intel_parser.reg = NULL; | |
8814 | intel_parser.disp[0] = '\0'; | |
8815 | intel_parser.next_operand = NULL; | |
8816 | ||
8817 | /* Read the first token and start the parser. */ | |
8818 | intel_get_token (); | |
8819 | ret = intel_expr (); | |
8820 | ||
8821 | if (!ret) | |
8822 | break; | |
8823 | ||
9306ca4a JB |
8824 | if (cur_token.code != T_NIL) |
8825 | { | |
8826 | as_bad (_("invalid operand for '%s' ('%s' unexpected)"), | |
8827 | current_templates->start->name, cur_token.str); | |
8828 | ret = 0; | |
8829 | } | |
64a0c779 DN |
8830 | /* If we found a memory reference, hand it over to i386_displacement |
8831 | to fill in the rest of the operand fields. */ | |
9306ca4a | 8832 | else if (intel_parser.is_mem) |
64a0c779 DN |
8833 | { |
8834 | if ((i.mem_operands == 1 | |
40fb9820 | 8835 | && !current_templates->start->opcode_modifier.isstring) |
64a0c779 DN |
8836 | || i.mem_operands == 2) |
8837 | { | |
8838 | as_bad (_("too many memory references for '%s'"), | |
8839 | current_templates->start->name); | |
8840 | ret = 0; | |
8841 | } | |
8842 | else | |
8843 | { | |
8844 | char *s = intel_parser.disp; | |
5c07affc | 8845 | i.types[this_operand].bitfield.mem = 1; |
64a0c779 DN |
8846 | i.mem_operands++; |
8847 | ||
a724f0f4 JB |
8848 | if (!quiet_warnings && intel_parser.is_mem < 0) |
8849 | /* See the comments in intel_bracket_expr. */ | |
8850 | as_warn (_("Treating `%s' as memory reference"), operand_string); | |
8851 | ||
64a0c779 DN |
8852 | /* Add the displacement expression. */ |
8853 | if (*s != '\0') | |
a4622f40 AM |
8854 | ret = i386_displacement (s, s + strlen (s)); |
8855 | if (ret) | |
a724f0f4 JB |
8856 | { |
8857 | /* Swap base and index in 16-bit memory operands like | |
8858 | [si+bx]. Since i386_index_check is also used in AT&T | |
8859 | mode we have to do that here. */ | |
8860 | if (i.base_reg | |
8861 | && i.index_reg | |
40fb9820 L |
8862 | && i.base_reg->reg_type.bitfield.reg16 |
8863 | && i.index_reg->reg_type.bitfield.reg16 | |
a724f0f4 JB |
8864 | && i.base_reg->reg_num >= 6 |
8865 | && i.index_reg->reg_num < 6) | |
8866 | { | |
8867 | const reg_entry *base = i.index_reg; | |
8868 | ||
8869 | i.index_reg = i.base_reg; | |
8870 | i.base_reg = base; | |
8871 | } | |
8872 | ret = i386_index_check (operand_string); | |
8873 | } | |
64a0c779 DN |
8874 | } |
8875 | } | |
8876 | ||
8877 | /* Constant and OFFSET expressions are handled by i386_immediate. */ | |
a724f0f4 | 8878 | else if ((intel_parser.op_modifier & (1 << T_OFFSET)) |
64a0c779 | 8879 | || intel_parser.reg == NULL) |
b7240065 JB |
8880 | { |
8881 | if (i.mem_operands < 2 && i.seg[i.mem_operands]) | |
8882 | { | |
8883 | if (!(intel_parser.op_modifier & (1 << T_OFFSET))) | |
8884 | as_warn (_("Segment override ignored")); | |
8885 | i.seg[i.mem_operands] = NULL; | |
8886 | } | |
8887 | ret = i386_immediate (intel_parser.disp); | |
8888 | } | |
a724f0f4 JB |
8889 | |
8890 | if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1) | |
4eed87de | 8891 | ret = 0; |
a724f0f4 JB |
8892 | if (!ret || !intel_parser.next_operand) |
8893 | break; | |
8894 | intel_parser.op_string = intel_parser.next_operand; | |
8895 | this_operand = i.operands++; | |
7d5e4556 | 8896 | i.types[this_operand].bitfield.unspecified = 1; |
64a0c779 DN |
8897 | } |
8898 | ||
8899 | free (p); | |
8900 | free (intel_parser.disp); | |
8901 | ||
8902 | return ret; | |
8903 | } | |
8904 | ||
a724f0f4 JB |
8905 | #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg) |
8906 | ||
8907 | /* expr e04 expr' | |
8908 | ||
8909 | expr' cmpOp e04 expr' | |
8910 | | Empty */ | |
64a0c779 | 8911 | static int |
e3bb37b5 | 8912 | intel_expr (void) |
64a0c779 | 8913 | { |
a724f0f4 JB |
8914 | /* XXX Implement the comparison operators. */ |
8915 | return intel_e04 (); | |
9306ca4a JB |
8916 | } |
8917 | ||
a724f0f4 | 8918 | /* e04 e05 e04' |
9306ca4a | 8919 | |
a724f0f4 | 8920 | e04' addOp e05 e04' |
9306ca4a JB |
8921 | | Empty */ |
8922 | static int | |
e3bb37b5 | 8923 | intel_e04 (void) |
9306ca4a | 8924 | { |
a724f0f4 | 8925 | int nregs = -1; |
9306ca4a | 8926 | |
a724f0f4 | 8927 | for (;;) |
9306ca4a | 8928 | { |
a724f0f4 JB |
8929 | if (!intel_e05()) |
8930 | return 0; | |
9306ca4a | 8931 | |
a724f0f4 JB |
8932 | if (nregs >= 0 && NUM_ADDRESS_REGS > nregs) |
8933 | i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */ | |
9306ca4a | 8934 | |
a724f0f4 JB |
8935 | if (cur_token.code == '+') |
8936 | nregs = -1; | |
8937 | else if (cur_token.code == '-') | |
8938 | nregs = NUM_ADDRESS_REGS; | |
8939 | else | |
8940 | return 1; | |
64a0c779 | 8941 | |
a724f0f4 JB |
8942 | strcat (intel_parser.disp, cur_token.str); |
8943 | intel_match_token (cur_token.code); | |
8944 | } | |
64a0c779 DN |
8945 | } |
8946 | ||
64a0c779 DN |
8947 | /* e05 e06 e05' |
8948 | ||
9306ca4a | 8949 | e05' binOp e06 e05' |
64a0c779 DN |
8950 | | Empty */ |
8951 | static int | |
e3bb37b5 | 8952 | intel_e05 (void) |
64a0c779 | 8953 | { |
a724f0f4 | 8954 | int nregs = ~NUM_ADDRESS_REGS; |
64a0c779 | 8955 | |
a724f0f4 | 8956 | for (;;) |
64a0c779 | 8957 | { |
a724f0f4 JB |
8958 | if (!intel_e06()) |
8959 | return 0; | |
8960 | ||
4eed87de AM |
8961 | if (cur_token.code == '&' |
8962 | || cur_token.code == '|' | |
8963 | || cur_token.code == '^') | |
a724f0f4 JB |
8964 | { |
8965 | char str[2]; | |
8966 | ||
8967 | str[0] = cur_token.code; | |
8968 | str[1] = 0; | |
8969 | strcat (intel_parser.disp, str); | |
8970 | } | |
8971 | else | |
8972 | break; | |
9306ca4a | 8973 | |
64a0c779 DN |
8974 | intel_match_token (cur_token.code); |
8975 | ||
a724f0f4 JB |
8976 | if (nregs < 0) |
8977 | nregs = ~nregs; | |
64a0c779 | 8978 | } |
a724f0f4 JB |
8979 | if (nregs >= 0 && NUM_ADDRESS_REGS > nregs) |
8980 | i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */ | |
8981 | return 1; | |
4a1805b1 | 8982 | } |
64a0c779 DN |
8983 | |
8984 | /* e06 e09 e06' | |
8985 | ||
8986 | e06' mulOp e09 e06' | |
b77a7acd | 8987 | | Empty */ |
64a0c779 | 8988 | static int |
e3bb37b5 | 8989 | intel_e06 (void) |
64a0c779 | 8990 | { |
a724f0f4 | 8991 | int nregs = ~NUM_ADDRESS_REGS; |
64a0c779 | 8992 | |
a724f0f4 | 8993 | for (;;) |
64a0c779 | 8994 | { |
a724f0f4 JB |
8995 | if (!intel_e09()) |
8996 | return 0; | |
9306ca4a | 8997 | |
4eed87de AM |
8998 | if (cur_token.code == '*' |
8999 | || cur_token.code == '/' | |
9000 | || cur_token.code == '%') | |
a724f0f4 JB |
9001 | { |
9002 | char str[2]; | |
9306ca4a | 9003 | |
a724f0f4 JB |
9004 | str[0] = cur_token.code; |
9005 | str[1] = 0; | |
9006 | strcat (intel_parser.disp, str); | |
9007 | } | |
9008 | else if (cur_token.code == T_SHL) | |
9009 | strcat (intel_parser.disp, "<<"); | |
9010 | else if (cur_token.code == T_SHR) | |
9011 | strcat (intel_parser.disp, ">>"); | |
9012 | else | |
9013 | break; | |
9306ca4a | 9014 | |
64e74474 | 9015 | intel_match_token (cur_token.code); |
64a0c779 | 9016 | |
a724f0f4 JB |
9017 | if (nregs < 0) |
9018 | nregs = ~nregs; | |
64a0c779 | 9019 | } |
a724f0f4 JB |
9020 | if (nregs >= 0 && NUM_ADDRESS_REGS > nregs) |
9021 | i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */ | |
9022 | return 1; | |
64a0c779 DN |
9023 | } |
9024 | ||
a724f0f4 JB |
9025 | /* e09 OFFSET e09 |
9026 | | SHORT e09 | |
9027 | | + e09 | |
9028 | | - e09 | |
9029 | | ~ e09 | |
9030 | | NOT e09 | |
9306ca4a JB |
9031 | | e10 e09' |
9032 | ||
64a0c779 | 9033 | e09' PTR e10 e09' |
b77a7acd | 9034 | | : e10 e09' |
64a0c779 DN |
9035 | | Empty */ |
9036 | static int | |
e3bb37b5 | 9037 | intel_e09 (void) |
64a0c779 | 9038 | { |
a724f0f4 JB |
9039 | int nregs = ~NUM_ADDRESS_REGS; |
9040 | int in_offset = 0; | |
9041 | ||
9042 | for (;;) | |
64a0c779 | 9043 | { |
a724f0f4 JB |
9044 | /* Don't consume constants here. */ |
9045 | if (cur_token.code == '+' || cur_token.code == '-') | |
9046 | { | |
9047 | /* Need to look one token ahead - if the next token | |
9048 | is a constant, the current token is its sign. */ | |
9049 | int next_code; | |
9050 | ||
9051 | intel_match_token (cur_token.code); | |
9052 | next_code = cur_token.code; | |
9053 | intel_putback_token (); | |
9054 | if (next_code == T_CONST) | |
9055 | break; | |
9056 | } | |
9057 | ||
9058 | /* e09 OFFSET e09 */ | |
9059 | if (cur_token.code == T_OFFSET) | |
9060 | { | |
9061 | if (!in_offset++) | |
9062 | ++intel_parser.in_offset; | |
9063 | } | |
9064 | ||
9065 | /* e09 SHORT e09 */ | |
9066 | else if (cur_token.code == T_SHORT) | |
9067 | intel_parser.op_modifier |= 1 << T_SHORT; | |
9068 | ||
9069 | /* e09 + e09 */ | |
9070 | else if (cur_token.code == '+') | |
9071 | strcat (intel_parser.disp, "+"); | |
9072 | ||
9073 | /* e09 - e09 | |
9074 | | ~ e09 | |
9075 | | NOT e09 */ | |
9076 | else if (cur_token.code == '-' || cur_token.code == '~') | |
9077 | { | |
9078 | char str[2]; | |
64a0c779 | 9079 | |
a724f0f4 JB |
9080 | if (nregs < 0) |
9081 | nregs = ~nregs; | |
9082 | str[0] = cur_token.code; | |
9083 | str[1] = 0; | |
9084 | strcat (intel_parser.disp, str); | |
9085 | } | |
9086 | ||
9087 | /* e09 e10 e09' */ | |
9088 | else | |
9089 | break; | |
9090 | ||
9091 | intel_match_token (cur_token.code); | |
64a0c779 DN |
9092 | } |
9093 | ||
a724f0f4 | 9094 | for (;;) |
9306ca4a | 9095 | { |
a724f0f4 JB |
9096 | if (!intel_e10 ()) |
9097 | return 0; | |
9306ca4a | 9098 | |
a724f0f4 JB |
9099 | /* e09' PTR e10 e09' */ |
9100 | if (cur_token.code == T_PTR) | |
9101 | { | |
9102 | char suffix; | |
9306ca4a | 9103 | |
a724f0f4 | 9104 | if (prev_token.code == T_BYTE) |
7d5e4556 L |
9105 | { |
9106 | suffix = BYTE_MNEM_SUFFIX; | |
9107 | i.types[this_operand].bitfield.byte = 1; | |
9108 | } | |
9306ca4a | 9109 | |
a724f0f4 JB |
9110 | else if (prev_token.code == T_WORD) |
9111 | { | |
34b772a6 JB |
9112 | if ((current_templates->start->name[0] == 'l' |
9113 | && current_templates->start->name[2] == 's' | |
9114 | && current_templates->start->name[3] == 0) | |
9115 | || current_templates->start->base_opcode == 0x62 /* bound */) | |
a724f0f4 JB |
9116 | suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */ |
9117 | else if (intel_parser.got_a_float == 2) /* "fi..." */ | |
9118 | suffix = SHORT_MNEM_SUFFIX; | |
9119 | else | |
9120 | suffix = WORD_MNEM_SUFFIX; | |
7d5e4556 | 9121 | i.types[this_operand].bitfield.word = 1; |
a724f0f4 | 9122 | } |
64a0c779 | 9123 | |
a724f0f4 JB |
9124 | else if (prev_token.code == T_DWORD) |
9125 | { | |
34b772a6 JB |
9126 | if ((current_templates->start->name[0] == 'l' |
9127 | && current_templates->start->name[2] == 's' | |
9128 | && current_templates->start->name[3] == 0) | |
9129 | || current_templates->start->base_opcode == 0x62 /* bound */) | |
a724f0f4 JB |
9130 | suffix = WORD_MNEM_SUFFIX; |
9131 | else if (flag_code == CODE_16BIT | |
40fb9820 L |
9132 | && (current_templates->start->opcode_modifier.jump |
9133 | || current_templates->start->opcode_modifier.jumpdword)) | |
a724f0f4 JB |
9134 | suffix = LONG_DOUBLE_MNEM_SUFFIX; |
9135 | else if (intel_parser.got_a_float == 1) /* "f..." */ | |
9136 | suffix = SHORT_MNEM_SUFFIX; | |
9137 | else | |
9138 | suffix = LONG_MNEM_SUFFIX; | |
7d5e4556 | 9139 | i.types[this_operand].bitfield.dword = 1; |
a724f0f4 | 9140 | } |
9306ca4a | 9141 | |
a724f0f4 JB |
9142 | else if (prev_token.code == T_FWORD) |
9143 | { | |
9144 | if (current_templates->start->name[0] == 'l' | |
9145 | && current_templates->start->name[2] == 's' | |
9146 | && current_templates->start->name[3] == 0) | |
9147 | suffix = LONG_MNEM_SUFFIX; | |
9148 | else if (!intel_parser.got_a_float) | |
9149 | { | |
9150 | if (flag_code == CODE_16BIT) | |
9151 | add_prefix (DATA_PREFIX_OPCODE); | |
9152 | suffix = LONG_DOUBLE_MNEM_SUFFIX; | |
9153 | } | |
9154 | else | |
9155 | suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */ | |
7d5e4556 | 9156 | i.types[this_operand].bitfield.fword = 1; |
a724f0f4 | 9157 | } |
64a0c779 | 9158 | |
a724f0f4 JB |
9159 | else if (prev_token.code == T_QWORD) |
9160 | { | |
34b772a6 JB |
9161 | if (current_templates->start->base_opcode == 0x62 /* bound */ |
9162 | || intel_parser.got_a_float == 1) /* "f..." */ | |
a724f0f4 JB |
9163 | suffix = LONG_MNEM_SUFFIX; |
9164 | else | |
34b772a6 | 9165 | suffix = QWORD_MNEM_SUFFIX; |
7d5e4556 | 9166 | i.types[this_operand].bitfield.qword = 1; |
a724f0f4 | 9167 | } |
64a0c779 | 9168 | |
a724f0f4 JB |
9169 | else if (prev_token.code == T_TBYTE) |
9170 | { | |
9171 | if (intel_parser.got_a_float == 1) | |
9172 | suffix = LONG_DOUBLE_MNEM_SUFFIX; | |
9173 | else | |
9174 | suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */ | |
9175 | } | |
9306ca4a | 9176 | |
a724f0f4 | 9177 | else if (prev_token.code == T_XMMWORD) |
9306ca4a | 9178 | { |
582d5edd | 9179 | suffix = XMMWORD_MNEM_SUFFIX; |
7d5e4556 | 9180 | i.types[this_operand].bitfield.xmmword = 1; |
9306ca4a | 9181 | } |
64a0c779 | 9182 | |
c0f3af97 L |
9183 | else if (prev_token.code == T_YMMWORD) |
9184 | { | |
9185 | suffix = YMMWORD_MNEM_SUFFIX; | |
9186 | i.types[this_operand].bitfield.ymmword = 1; | |
9187 | } | |
9188 | ||
f16b83df | 9189 | else |
a724f0f4 JB |
9190 | { |
9191 | as_bad (_("Unknown operand modifier `%s'"), prev_token.str); | |
9192 | return 0; | |
9193 | } | |
9194 | ||
7d5e4556 L |
9195 | i.types[this_operand].bitfield.unspecified = 0; |
9196 | ||
435acd52 JB |
9197 | /* Operands for jump/call using 'ptr' notation denote absolute |
9198 | addresses. */ | |
40fb9820 L |
9199 | if (current_templates->start->opcode_modifier.jump |
9200 | || current_templates->start->opcode_modifier.jumpdword) | |
9201 | i.types[this_operand].bitfield.jumpabsolute = 1; | |
435acd52 | 9202 | |
a724f0f4 JB |
9203 | if (current_templates->start->base_opcode == 0x8d /* lea */) |
9204 | ; | |
9205 | else if (!i.suffix) | |
9206 | i.suffix = suffix; | |
9207 | else if (i.suffix != suffix) | |
9208 | { | |
9209 | as_bad (_("Conflicting operand modifiers")); | |
9210 | return 0; | |
9211 | } | |
64a0c779 | 9212 | |
9306ca4a JB |
9213 | } |
9214 | ||
a724f0f4 JB |
9215 | /* e09' : e10 e09' */ |
9216 | else if (cur_token.code == ':') | |
9306ca4a | 9217 | { |
a724f0f4 JB |
9218 | if (prev_token.code != T_REG) |
9219 | { | |
9220 | /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a | |
9221 | segment/group identifier (which we don't have), using comma | |
9222 | as the operand separator there is even less consistent, since | |
9223 | there all branches only have a single operand. */ | |
9224 | if (this_operand != 0 | |
9225 | || intel_parser.in_offset | |
9226 | || intel_parser.in_bracket | |
40fb9820 L |
9227 | || (!current_templates->start->opcode_modifier.jump |
9228 | && !current_templates->start->opcode_modifier.jumpdword | |
9229 | && !current_templates->start->opcode_modifier.jumpintersegment | |
9230 | && !current_templates->start->operand_types[0].bitfield.jumpabsolute)) | |
a724f0f4 JB |
9231 | return intel_match_token (T_NIL); |
9232 | /* Remember the start of the 2nd operand and terminate 1st | |
9233 | operand here. | |
9234 | XXX This isn't right, yet (when SSSS:OOOO is right operand of | |
9235 | another expression), but it gets at least the simplest case | |
9236 | (a plain number or symbol on the left side) right. */ | |
9237 | intel_parser.next_operand = intel_parser.op_string; | |
9238 | *--intel_parser.op_string = '\0'; | |
9239 | return intel_match_token (':'); | |
9240 | } | |
9306ca4a | 9241 | } |
64a0c779 | 9242 | |
a724f0f4 | 9243 | /* e09' Empty */ |
64a0c779 | 9244 | else |
a724f0f4 | 9245 | break; |
64a0c779 | 9246 | |
a724f0f4 JB |
9247 | intel_match_token (cur_token.code); |
9248 | ||
9249 | } | |
9250 | ||
9251 | if (in_offset) | |
9252 | { | |
9253 | --intel_parser.in_offset; | |
9254 | if (nregs < 0) | |
9255 | nregs = ~nregs; | |
9256 | if (NUM_ADDRESS_REGS > nregs) | |
9306ca4a | 9257 | { |
a724f0f4 | 9258 | as_bad (_("Invalid operand to `OFFSET'")); |
9306ca4a JB |
9259 | return 0; |
9260 | } | |
a724f0f4 JB |
9261 | intel_parser.op_modifier |= 1 << T_OFFSET; |
9262 | } | |
9306ca4a | 9263 | |
a724f0f4 JB |
9264 | if (nregs >= 0 && NUM_ADDRESS_REGS > nregs) |
9265 | i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */ | |
9266 | return 1; | |
9267 | } | |
64a0c779 | 9268 | |
a724f0f4 | 9269 | static int |
e3bb37b5 | 9270 | intel_bracket_expr (void) |
a724f0f4 JB |
9271 | { |
9272 | int was_offset = intel_parser.op_modifier & (1 << T_OFFSET); | |
9273 | const char *start = intel_parser.op_string; | |
9274 | int len; | |
9275 | ||
9276 | if (i.op[this_operand].regs) | |
9277 | return intel_match_token (T_NIL); | |
9278 | ||
9279 | intel_match_token ('['); | |
9280 | ||
9281 | /* Mark as a memory operand only if it's not already known to be an | |
9282 | offset expression. If it's an offset expression, we need to keep | |
9283 | the brace in. */ | |
9284 | if (!intel_parser.in_offset) | |
9285 | { | |
9286 | ++intel_parser.in_bracket; | |
435acd52 JB |
9287 | |
9288 | /* Operands for jump/call inside brackets denote absolute addresses. */ | |
40fb9820 L |
9289 | if (current_templates->start->opcode_modifier.jump |
9290 | || current_templates->start->opcode_modifier.jumpdword) | |
9291 | i.types[this_operand].bitfield.jumpabsolute = 1; | |
435acd52 | 9292 | |
a724f0f4 JB |
9293 | /* Unfortunately gas always diverged from MASM in a respect that can't |
9294 | be easily fixed without risking to break code sequences likely to be | |
9295 | encountered (the testsuite even check for this): MASM doesn't consider | |
9296 | an expression inside brackets unconditionally as a memory reference. | |
9297 | When that is e.g. a constant, an offset expression, or the sum of the | |
9298 | two, this is still taken as a constant load. gas, however, always | |
9299 | treated these as memory references. As a compromise, we'll try to make | |
9300 | offset expressions inside brackets work the MASM way (since that's | |
9301 | less likely to be found in real world code), but make constants alone | |
9302 | continue to work the traditional gas way. In either case, issue a | |
9303 | warning. */ | |
9304 | intel_parser.op_modifier &= ~was_offset; | |
64a0c779 | 9305 | } |
a724f0f4 | 9306 | else |
64e74474 | 9307 | strcat (intel_parser.disp, "["); |
a724f0f4 JB |
9308 | |
9309 | /* Add a '+' to the displacement string if necessary. */ | |
9310 | if (*intel_parser.disp != '\0' | |
9311 | && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+') | |
9312 | strcat (intel_parser.disp, "+"); | |
64a0c779 | 9313 | |
a724f0f4 JB |
9314 | if (intel_expr () |
9315 | && (len = intel_parser.op_string - start - 1, | |
9316 | intel_match_token (']'))) | |
64a0c779 | 9317 | { |
a724f0f4 JB |
9318 | /* Preserve brackets when the operand is an offset expression. */ |
9319 | if (intel_parser.in_offset) | |
9320 | strcat (intel_parser.disp, "]"); | |
9321 | else | |
9322 | { | |
9323 | --intel_parser.in_bracket; | |
9324 | if (i.base_reg || i.index_reg) | |
9325 | intel_parser.is_mem = 1; | |
9326 | if (!intel_parser.is_mem) | |
9327 | { | |
9328 | if (!(intel_parser.op_modifier & (1 << T_OFFSET))) | |
9329 | /* Defer the warning until all of the operand was parsed. */ | |
9330 | intel_parser.is_mem = -1; | |
9331 | else if (!quiet_warnings) | |
4eed87de AM |
9332 | as_warn (_("`[%.*s]' taken to mean just `%.*s'"), |
9333 | len, start, len, start); | |
a724f0f4 JB |
9334 | } |
9335 | } | |
9336 | intel_parser.op_modifier |= was_offset; | |
64a0c779 | 9337 | |
a724f0f4 | 9338 | return 1; |
64a0c779 | 9339 | } |
a724f0f4 | 9340 | return 0; |
64a0c779 DN |
9341 | } |
9342 | ||
9343 | /* e10 e11 e10' | |
9344 | ||
9345 | e10' [ expr ] e10' | |
b77a7acd | 9346 | | Empty */ |
64a0c779 | 9347 | static int |
e3bb37b5 | 9348 | intel_e10 (void) |
64a0c779 | 9349 | { |
a724f0f4 JB |
9350 | if (!intel_e11 ()) |
9351 | return 0; | |
64a0c779 | 9352 | |
a724f0f4 | 9353 | while (cur_token.code == '[') |
64a0c779 | 9354 | { |
a724f0f4 | 9355 | if (!intel_bracket_expr ()) |
21d6c4af | 9356 | return 0; |
64a0c779 DN |
9357 | } |
9358 | ||
a724f0f4 | 9359 | return 1; |
64a0c779 DN |
9360 | } |
9361 | ||
64a0c779 | 9362 | /* e11 ( expr ) |
b77a7acd | 9363 | | [ expr ] |
64a0c779 DN |
9364 | | BYTE |
9365 | | WORD | |
9366 | | DWORD | |
9306ca4a | 9367 | | FWORD |
64a0c779 | 9368 | | QWORD |
9306ca4a JB |
9369 | | TBYTE |
9370 | | OWORD | |
9371 | | XMMWORD | |
c0f3af97 | 9372 | | YMMWORD |
4a1805b1 | 9373 | | $ |
64a0c779 DN |
9374 | | . |
9375 | | register | |
9376 | | id | |
9377 | | constant */ | |
9378 | static int | |
e3bb37b5 | 9379 | intel_e11 (void) |
64a0c779 | 9380 | { |
a724f0f4 | 9381 | switch (cur_token.code) |
64a0c779 | 9382 | { |
a724f0f4 JB |
9383 | /* e11 ( expr ) */ |
9384 | case '(': | |
64a0c779 DN |
9385 | intel_match_token ('('); |
9386 | strcat (intel_parser.disp, "("); | |
9387 | ||
9388 | if (intel_expr () && intel_match_token (')')) | |
e5cb08ac KH |
9389 | { |
9390 | strcat (intel_parser.disp, ")"); | |
9391 | return 1; | |
9392 | } | |
a724f0f4 | 9393 | return 0; |
4a1805b1 | 9394 | |
a724f0f4 JB |
9395 | /* e11 [ expr ] */ |
9396 | case '[': | |
a724f0f4 | 9397 | return intel_bracket_expr (); |
64a0c779 | 9398 | |
a724f0f4 JB |
9399 | /* e11 $ |
9400 | | . */ | |
9401 | case '.': | |
64a0c779 DN |
9402 | strcat (intel_parser.disp, cur_token.str); |
9403 | intel_match_token (cur_token.code); | |
21d6c4af DN |
9404 | |
9405 | /* Mark as a memory operand only if it's not already known to be an | |
9406 | offset expression. */ | |
a724f0f4 | 9407 | if (!intel_parser.in_offset) |
21d6c4af | 9408 | intel_parser.is_mem = 1; |
64a0c779 DN |
9409 | |
9410 | return 1; | |
64a0c779 | 9411 | |
a724f0f4 JB |
9412 | /* e11 register */ |
9413 | case T_REG: | |
9414 | { | |
9415 | const reg_entry *reg = intel_parser.reg = cur_token.reg; | |
64a0c779 | 9416 | |
a724f0f4 | 9417 | intel_match_token (T_REG); |
64a0c779 | 9418 | |
a724f0f4 JB |
9419 | /* Check for segment change. */ |
9420 | if (cur_token.code == ':') | |
9421 | { | |
40fb9820 L |
9422 | if (!reg->reg_type.bitfield.sreg2 |
9423 | && !reg->reg_type.bitfield.sreg3) | |
a724f0f4 | 9424 | { |
4eed87de AM |
9425 | as_bad (_("`%s' is not a valid segment register"), |
9426 | reg->reg_name); | |
a724f0f4 JB |
9427 | return 0; |
9428 | } | |
b7240065 JB |
9429 | else if (i.mem_operands >= 2) |
9430 | as_warn (_("Segment override ignored")); | |
a724f0f4 JB |
9431 | else if (i.seg[i.mem_operands]) |
9432 | as_warn (_("Extra segment override ignored")); | |
9433 | else | |
9434 | { | |
9435 | if (!intel_parser.in_offset) | |
9436 | intel_parser.is_mem = 1; | |
9437 | switch (reg->reg_num) | |
9438 | { | |
9439 | case 0: | |
9440 | i.seg[i.mem_operands] = &es; | |
9441 | break; | |
9442 | case 1: | |
9443 | i.seg[i.mem_operands] = &cs; | |
9444 | break; | |
9445 | case 2: | |
9446 | i.seg[i.mem_operands] = &ss; | |
9447 | break; | |
9448 | case 3: | |
9449 | i.seg[i.mem_operands] = &ds; | |
9450 | break; | |
9451 | case 4: | |
9452 | i.seg[i.mem_operands] = &fs; | |
9453 | break; | |
9454 | case 5: | |
9455 | i.seg[i.mem_operands] = &gs; | |
9456 | break; | |
9457 | } | |
9458 | } | |
9459 | } | |
64a0c779 | 9460 | |
b7240065 JB |
9461 | else if (reg->reg_type.bitfield.sreg3 && reg->reg_num == RegFlat) |
9462 | { | |
9463 | as_bad (_("cannot use `FLAT' here")); | |
9464 | return 0; | |
9465 | } | |
9466 | ||
a724f0f4 JB |
9467 | /* Not a segment register. Check for register scaling. */ |
9468 | else if (cur_token.code == '*') | |
9469 | { | |
9470 | if (!intel_parser.in_bracket) | |
9471 | { | |
9472 | as_bad (_("Register scaling only allowed in memory operands")); | |
9473 | return 0; | |
9474 | } | |
64a0c779 | 9475 | |
40fb9820 | 9476 | if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */ |
a724f0f4 JB |
9477 | reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */ |
9478 | else if (i.index_reg) | |
9479 | reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */ | |
64a0c779 | 9480 | |
a724f0f4 JB |
9481 | /* What follows must be a valid scale. */ |
9482 | intel_match_token ('*'); | |
9483 | i.index_reg = reg; | |
40fb9820 | 9484 | i.types[this_operand].bitfield.baseindex = 1; |
64a0c779 | 9485 | |
a724f0f4 JB |
9486 | /* Set the scale after setting the register (otherwise, |
9487 | i386_scale will complain) */ | |
9488 | if (cur_token.code == '+' || cur_token.code == '-') | |
9489 | { | |
9490 | char *str, sign = cur_token.code; | |
9491 | intel_match_token (cur_token.code); | |
9492 | if (cur_token.code != T_CONST) | |
9493 | { | |
9494 | as_bad (_("Syntax error: Expecting a constant, got `%s'"), | |
9495 | cur_token.str); | |
9496 | return 0; | |
9497 | } | |
9498 | str = (char *) xmalloc (strlen (cur_token.str) + 2); | |
9499 | strcpy (str + 1, cur_token.str); | |
9500 | *str = sign; | |
9501 | if (!i386_scale (str)) | |
9502 | return 0; | |
9503 | free (str); | |
9504 | } | |
9505 | else if (!i386_scale (cur_token.str)) | |
64a0c779 | 9506 | return 0; |
a724f0f4 JB |
9507 | intel_match_token (cur_token.code); |
9508 | } | |
64a0c779 | 9509 | |
a724f0f4 JB |
9510 | /* No scaling. If this is a memory operand, the register is either a |
9511 | base register (first occurrence) or an index register (second | |
9512 | occurrence). */ | |
7b0441f6 | 9513 | else if (intel_parser.in_bracket) |
a724f0f4 | 9514 | { |
64a0c779 | 9515 | |
a724f0f4 JB |
9516 | if (!i.base_reg) |
9517 | i.base_reg = reg; | |
9518 | else if (!i.index_reg) | |
9519 | i.index_reg = reg; | |
9520 | else | |
9521 | { | |
9522 | as_bad (_("Too many register references in memory operand")); | |
9523 | return 0; | |
9524 | } | |
64a0c779 | 9525 | |
40fb9820 | 9526 | i.types[this_operand].bitfield.baseindex = 1; |
a724f0f4 | 9527 | } |
4a1805b1 | 9528 | |
4d1bb795 JB |
9529 | /* It's neither base nor index. */ |
9530 | else if (!intel_parser.in_offset && !intel_parser.is_mem) | |
a724f0f4 | 9531 | { |
40fb9820 L |
9532 | i386_operand_type temp = reg->reg_type; |
9533 | temp.bitfield.baseindex = 0; | |
c6fb90c8 L |
9534 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
9535 | temp); | |
7d5e4556 | 9536 | i.types[this_operand].bitfield.unspecified = 0; |
a724f0f4 JB |
9537 | i.op[this_operand].regs = reg; |
9538 | i.reg_operands++; | |
9539 | } | |
9540 | else | |
9541 | { | |
9542 | as_bad (_("Invalid use of register")); | |
9543 | return 0; | |
9544 | } | |
64a0c779 | 9545 | |
a724f0f4 JB |
9546 | /* Since registers are not part of the displacement string (except |
9547 | when we're parsing offset operands), we may need to remove any | |
9548 | preceding '+' from the displacement string. */ | |
9549 | if (*intel_parser.disp != '\0' | |
9550 | && !intel_parser.in_offset) | |
9551 | { | |
9552 | char *s = intel_parser.disp; | |
9553 | s += strlen (s) - 1; | |
9554 | if (*s == '+') | |
9555 | *s = '\0'; | |
9556 | } | |
4a1805b1 | 9557 | |
a724f0f4 JB |
9558 | return 1; |
9559 | } | |
9560 | ||
9561 | /* e11 BYTE | |
9562 | | WORD | |
9563 | | DWORD | |
9564 | | FWORD | |
9565 | | QWORD | |
9566 | | TBYTE | |
9567 | | OWORD | |
c0f3af97 L |
9568 | | XMMWORD |
9569 | | YMMWORD */ | |
a724f0f4 JB |
9570 | case T_BYTE: |
9571 | case T_WORD: | |
9572 | case T_DWORD: | |
9573 | case T_FWORD: | |
9574 | case T_QWORD: | |
9575 | case T_TBYTE: | |
9576 | case T_XMMWORD: | |
c0f3af97 | 9577 | case T_YMMWORD: |
a724f0f4 | 9578 | intel_match_token (cur_token.code); |
64a0c779 | 9579 | |
a724f0f4 JB |
9580 | if (cur_token.code == T_PTR) |
9581 | return 1; | |
9582 | ||
9583 | /* It must have been an identifier. */ | |
9584 | intel_putback_token (); | |
9585 | cur_token.code = T_ID; | |
9586 | /* FALLTHRU */ | |
9587 | ||
9588 | /* e11 id | |
9589 | | constant */ | |
9590 | case T_ID: | |
9591 | if (!intel_parser.in_offset && intel_parser.is_mem <= 0) | |
9306ca4a JB |
9592 | { |
9593 | symbolS *symbolP; | |
9594 | ||
a724f0f4 JB |
9595 | /* The identifier represents a memory reference only if it's not |
9596 | preceded by an offset modifier and if it's not an equate. */ | |
9306ca4a JB |
9597 | symbolP = symbol_find(cur_token.str); |
9598 | if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section) | |
9599 | intel_parser.is_mem = 1; | |
9600 | } | |
a724f0f4 | 9601 | /* FALLTHRU */ |
64a0c779 | 9602 | |
a724f0f4 JB |
9603 | case T_CONST: |
9604 | case '-': | |
9605 | case '+': | |
9606 | { | |
9607 | char *save_str, sign = 0; | |
64a0c779 | 9608 | |
a724f0f4 JB |
9609 | /* Allow constants that start with `+' or `-'. */ |
9610 | if (cur_token.code == '-' || cur_token.code == '+') | |
9611 | { | |
9612 | sign = cur_token.code; | |
9613 | intel_match_token (cur_token.code); | |
9614 | if (cur_token.code != T_CONST) | |
9615 | { | |
9616 | as_bad (_("Syntax error: Expecting a constant, got `%s'"), | |
9617 | cur_token.str); | |
9618 | return 0; | |
9619 | } | |
9620 | } | |
64a0c779 | 9621 | |
a724f0f4 JB |
9622 | save_str = (char *) xmalloc (strlen (cur_token.str) + 2); |
9623 | strcpy (save_str + !!sign, cur_token.str); | |
9624 | if (sign) | |
9625 | *save_str = sign; | |
64a0c779 | 9626 | |
a724f0f4 JB |
9627 | /* Get the next token to check for register scaling. */ |
9628 | intel_match_token (cur_token.code); | |
64a0c779 | 9629 | |
4eed87de AM |
9630 | /* Check if this constant is a scaling factor for an |
9631 | index register. */ | |
a724f0f4 JB |
9632 | if (cur_token.code == '*') |
9633 | { | |
9634 | if (intel_match_token ('*') && cur_token.code == T_REG) | |
9635 | { | |
9636 | const reg_entry *reg = cur_token.reg; | |
9637 | ||
9638 | if (!intel_parser.in_bracket) | |
9639 | { | |
4eed87de AM |
9640 | as_bad (_("Register scaling only allowed " |
9641 | "in memory operands")); | |
a724f0f4 JB |
9642 | return 0; |
9643 | } | |
9644 | ||
4eed87de AM |
9645 | /* Disallow things like [1*si]. |
9646 | sp and esp are invalid as index. */ | |
40fb9820 | 9647 | if (reg->reg_type.bitfield.reg16) |
4eed87de | 9648 | reg = i386_regtab + REGNAM_AX + 4; |
a724f0f4 | 9649 | else if (i.index_reg) |
4eed87de | 9650 | reg = i386_regtab + REGNAM_EAX + 4; |
a724f0f4 JB |
9651 | |
9652 | /* The constant is followed by `* reg', so it must be | |
9653 | a valid scale. */ | |
9654 | i.index_reg = reg; | |
40fb9820 | 9655 | i.types[this_operand].bitfield.baseindex = 1; |
a724f0f4 JB |
9656 | |
9657 | /* Set the scale after setting the register (otherwise, | |
9658 | i386_scale will complain) */ | |
9659 | if (!i386_scale (save_str)) | |
64a0c779 | 9660 | return 0; |
a724f0f4 JB |
9661 | intel_match_token (T_REG); |
9662 | ||
9663 | /* Since registers are not part of the displacement | |
9664 | string, we may need to remove any preceding '+' from | |
9665 | the displacement string. */ | |
9666 | if (*intel_parser.disp != '\0') | |
9667 | { | |
9668 | char *s = intel_parser.disp; | |
9669 | s += strlen (s) - 1; | |
9670 | if (*s == '+') | |
9671 | *s = '\0'; | |
9672 | } | |
9673 | ||
9674 | free (save_str); | |
9675 | ||
9676 | return 1; | |
9677 | } | |
64a0c779 | 9678 | |
a724f0f4 JB |
9679 | /* The constant was not used for register scaling. Since we have |
9680 | already consumed the token following `*' we now need to put it | |
9681 | back in the stream. */ | |
64a0c779 | 9682 | intel_putback_token (); |
a724f0f4 | 9683 | } |
64a0c779 | 9684 | |
a724f0f4 JB |
9685 | /* Add the constant to the displacement string. */ |
9686 | strcat (intel_parser.disp, save_str); | |
9687 | free (save_str); | |
64a0c779 | 9688 | |
a724f0f4 JB |
9689 | return 1; |
9690 | } | |
64a0c779 DN |
9691 | } |
9692 | ||
64a0c779 DN |
9693 | as_bad (_("Unrecognized token '%s'"), cur_token.str); |
9694 | return 0; | |
9695 | } | |
9696 | ||
64a0c779 DN |
9697 | /* Match the given token against cur_token. If they match, read the next |
9698 | token from the operand string. */ | |
9699 | static int | |
e3bb37b5 | 9700 | intel_match_token (int code) |
64a0c779 DN |
9701 | { |
9702 | if (cur_token.code == code) | |
9703 | { | |
9704 | intel_get_token (); | |
9705 | return 1; | |
9706 | } | |
9707 | else | |
9708 | { | |
0477af35 | 9709 | as_bad (_("Unexpected token `%s'"), cur_token.str); |
64a0c779 DN |
9710 | return 0; |
9711 | } | |
9712 | } | |
9713 | ||
64a0c779 DN |
9714 | /* Read a new token from intel_parser.op_string and store it in cur_token. */ |
9715 | static void | |
e3bb37b5 | 9716 | intel_get_token (void) |
64a0c779 DN |
9717 | { |
9718 | char *end_op; | |
9719 | const reg_entry *reg; | |
9720 | struct intel_token new_token; | |
9721 | ||
9722 | new_token.code = T_NIL; | |
9723 | new_token.reg = NULL; | |
9724 | new_token.str = NULL; | |
9725 | ||
4a1805b1 | 9726 | /* Free the memory allocated to the previous token and move |
64a0c779 DN |
9727 | cur_token to prev_token. */ |
9728 | if (prev_token.str) | |
9729 | free (prev_token.str); | |
9730 | ||
9731 | prev_token = cur_token; | |
9732 | ||
9733 | /* Skip whitespace. */ | |
9734 | while (is_space_char (*intel_parser.op_string)) | |
9735 | intel_parser.op_string++; | |
9736 | ||
9737 | /* Return an empty token if we find nothing else on the line. */ | |
9738 | if (*intel_parser.op_string == '\0') | |
9739 | { | |
9740 | cur_token = new_token; | |
9741 | return; | |
9742 | } | |
9743 | ||
9744 | /* The new token cannot be larger than the remainder of the operand | |
9745 | string. */ | |
a724f0f4 | 9746 | new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1); |
64a0c779 DN |
9747 | new_token.str[0] = '\0'; |
9748 | ||
9749 | if (strchr ("0123456789", *intel_parser.op_string)) | |
9750 | { | |
9751 | char *p = new_token.str; | |
9752 | char *q = intel_parser.op_string; | |
9753 | new_token.code = T_CONST; | |
9754 | ||
9755 | /* Allow any kind of identifier char to encompass floating point and | |
9756 | hexadecimal numbers. */ | |
9757 | while (is_identifier_char (*q)) | |
9758 | *p++ = *q++; | |
9759 | *p = '\0'; | |
9760 | ||
9761 | /* Recognize special symbol names [0-9][bf]. */ | |
9762 | if (strlen (intel_parser.op_string) == 2 | |
4a1805b1 | 9763 | && (intel_parser.op_string[1] == 'b' |
64a0c779 DN |
9764 | || intel_parser.op_string[1] == 'f')) |
9765 | new_token.code = T_ID; | |
9766 | } | |
9767 | ||
4d1bb795 | 9768 | else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL) |
64a0c779 | 9769 | { |
4d1bb795 JB |
9770 | size_t len = end_op - intel_parser.op_string; |
9771 | ||
64a0c779 DN |
9772 | new_token.code = T_REG; |
9773 | new_token.reg = reg; | |
9774 | ||
4d1bb795 JB |
9775 | memcpy (new_token.str, intel_parser.op_string, len); |
9776 | new_token.str[len] = '\0'; | |
64a0c779 DN |
9777 | } |
9778 | ||
9779 | else if (is_identifier_char (*intel_parser.op_string)) | |
9780 | { | |
9781 | char *p = new_token.str; | |
9782 | char *q = intel_parser.op_string; | |
9783 | ||
9784 | /* A '.' or '$' followed by an identifier char is an identifier. | |
9785 | Otherwise, it's operator '.' followed by an expression. */ | |
9786 | if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1))) | |
9787 | { | |
9306ca4a JB |
9788 | new_token.code = '.'; |
9789 | new_token.str[0] = '.'; | |
64a0c779 DN |
9790 | new_token.str[1] = '\0'; |
9791 | } | |
9792 | else | |
9793 | { | |
9794 | while (is_identifier_char (*q) || *q == '@') | |
9795 | *p++ = *q++; | |
9796 | *p = '\0'; | |
9797 | ||
9306ca4a JB |
9798 | if (strcasecmp (new_token.str, "NOT") == 0) |
9799 | new_token.code = '~'; | |
9800 | ||
9801 | else if (strcasecmp (new_token.str, "MOD") == 0) | |
9802 | new_token.code = '%'; | |
9803 | ||
9804 | else if (strcasecmp (new_token.str, "AND") == 0) | |
9805 | new_token.code = '&'; | |
9806 | ||
9807 | else if (strcasecmp (new_token.str, "OR") == 0) | |
9808 | new_token.code = '|'; | |
9809 | ||
9810 | else if (strcasecmp (new_token.str, "XOR") == 0) | |
9811 | new_token.code = '^'; | |
9812 | ||
9813 | else if (strcasecmp (new_token.str, "SHL") == 0) | |
9814 | new_token.code = T_SHL; | |
9815 | ||
9816 | else if (strcasecmp (new_token.str, "SHR") == 0) | |
9817 | new_token.code = T_SHR; | |
9818 | ||
9819 | else if (strcasecmp (new_token.str, "BYTE") == 0) | |
64a0c779 DN |
9820 | new_token.code = T_BYTE; |
9821 | ||
9822 | else if (strcasecmp (new_token.str, "WORD") == 0) | |
9823 | new_token.code = T_WORD; | |
9824 | ||
9825 | else if (strcasecmp (new_token.str, "DWORD") == 0) | |
9826 | new_token.code = T_DWORD; | |
9827 | ||
9306ca4a JB |
9828 | else if (strcasecmp (new_token.str, "FWORD") == 0) |
9829 | new_token.code = T_FWORD; | |
9830 | ||
64a0c779 DN |
9831 | else if (strcasecmp (new_token.str, "QWORD") == 0) |
9832 | new_token.code = T_QWORD; | |
9833 | ||
9306ca4a JB |
9834 | else if (strcasecmp (new_token.str, "TBYTE") == 0 |
9835 | /* XXX remove (gcc still uses it) */ | |
9836 | || strcasecmp (new_token.str, "XWORD") == 0) | |
9837 | new_token.code = T_TBYTE; | |
9838 | ||
9839 | else if (strcasecmp (new_token.str, "XMMWORD") == 0 | |
9840 | || strcasecmp (new_token.str, "OWORD") == 0) | |
9841 | new_token.code = T_XMMWORD; | |
64a0c779 | 9842 | |
c0f3af97 L |
9843 | else if (strcasecmp (new_token.str, "YMMWORD") == 0) |
9844 | new_token.code = T_YMMWORD; | |
9845 | ||
64a0c779 DN |
9846 | else if (strcasecmp (new_token.str, "PTR") == 0) |
9847 | new_token.code = T_PTR; | |
9848 | ||
9849 | else if (strcasecmp (new_token.str, "SHORT") == 0) | |
9850 | new_token.code = T_SHORT; | |
9851 | ||
9852 | else if (strcasecmp (new_token.str, "OFFSET") == 0) | |
9853 | { | |
9854 | new_token.code = T_OFFSET; | |
9855 | ||
9856 | /* ??? This is not mentioned in the MASM grammar but gcc | |
9857 | makes use of it with -mintel-syntax. OFFSET may be | |
9858 | followed by FLAT: */ | |
9859 | if (strncasecmp (q, " FLAT:", 6) == 0) | |
9860 | strcat (new_token.str, " FLAT:"); | |
9861 | } | |
9862 | ||
64a0c779 DN |
9863 | else |
9864 | new_token.code = T_ID; | |
9865 | } | |
9866 | } | |
9867 | ||
9306ca4a JB |
9868 | else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string)) |
9869 | { | |
9870 | new_token.code = *intel_parser.op_string; | |
9871 | new_token.str[0] = *intel_parser.op_string; | |
9872 | new_token.str[1] = '\0'; | |
9873 | } | |
9874 | ||
9875 | else if (strchr ("<>", *intel_parser.op_string) | |
9876 | && *intel_parser.op_string == *(intel_parser.op_string + 1)) | |
9877 | { | |
9878 | new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR; | |
9879 | new_token.str[0] = *intel_parser.op_string; | |
9880 | new_token.str[1] = *intel_parser.op_string; | |
9881 | new_token.str[2] = '\0'; | |
9882 | } | |
9883 | ||
64a0c779 | 9884 | else |
0477af35 | 9885 | as_bad (_("Unrecognized token `%s'"), intel_parser.op_string); |
64a0c779 DN |
9886 | |
9887 | intel_parser.op_string += strlen (new_token.str); | |
9888 | cur_token = new_token; | |
9889 | } | |
9890 | ||
64a0c779 DN |
9891 | /* Put cur_token back into the token stream and make cur_token point to |
9892 | prev_token. */ | |
9893 | static void | |
e3bb37b5 | 9894 | intel_putback_token (void) |
64a0c779 | 9895 | { |
a724f0f4 JB |
9896 | if (cur_token.code != T_NIL) |
9897 | { | |
9898 | intel_parser.op_string -= strlen (cur_token.str); | |
9899 | free (cur_token.str); | |
9900 | } | |
64a0c779 | 9901 | cur_token = prev_token; |
4a1805b1 | 9902 | |
64a0c779 DN |
9903 | /* Forget prev_token. */ |
9904 | prev_token.code = T_NIL; | |
9905 | prev_token.reg = NULL; | |
9906 | prev_token.str = NULL; | |
9907 | } | |
54cfded0 | 9908 | |
a60de03c JB |
9909 | void |
9910 | tc_x86_parse_to_dw2regnum (expressionS *exp) | |
54cfded0 | 9911 | { |
a60de03c JB |
9912 | int saved_naked_reg; |
9913 | char saved_register_dot; | |
54cfded0 | 9914 | |
a60de03c JB |
9915 | saved_naked_reg = allow_naked_reg; |
9916 | allow_naked_reg = 1; | |
9917 | saved_register_dot = register_chars['.']; | |
9918 | register_chars['.'] = '.'; | |
9919 | allow_pseudo_reg = 1; | |
9920 | expression_and_evaluate (exp); | |
9921 | allow_pseudo_reg = 0; | |
9922 | register_chars['.'] = saved_register_dot; | |
9923 | allow_naked_reg = saved_naked_reg; | |
9924 | ||
9925 | if (exp->X_op == O_register && exp->X_add_number >= 0) | |
54cfded0 | 9926 | { |
a60de03c JB |
9927 | if ((addressT) exp->X_add_number < i386_regtab_size) |
9928 | { | |
9929 | exp->X_op = O_constant; | |
9930 | exp->X_add_number = i386_regtab[exp->X_add_number] | |
9931 | .dw2_regnum[flag_code >> 1]; | |
9932 | } | |
9933 | else | |
9934 | exp->X_op = O_illegal; | |
54cfded0 | 9935 | } |
54cfded0 AM |
9936 | } |
9937 | ||
9938 | void | |
9939 | tc_x86_frame_initial_instructions (void) | |
9940 | { | |
a60de03c JB |
9941 | static unsigned int sp_regno[2]; |
9942 | ||
9943 | if (!sp_regno[flag_code >> 1]) | |
9944 | { | |
9945 | char *saved_input = input_line_pointer; | |
9946 | char sp[][4] = {"esp", "rsp"}; | |
9947 | expressionS exp; | |
a4447b93 | 9948 | |
a60de03c JB |
9949 | input_line_pointer = sp[flag_code >> 1]; |
9950 | tc_x86_parse_to_dw2regnum (&exp); | |
9951 | assert (exp.X_op == O_constant); | |
9952 | sp_regno[flag_code >> 1] = exp.X_add_number; | |
9953 | input_line_pointer = saved_input; | |
9954 | } | |
a4447b93 | 9955 | |
a60de03c | 9956 | cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment); |
a4447b93 | 9957 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); |
54cfded0 | 9958 | } |
d2b2c203 DJ |
9959 | |
9960 | int | |
9961 | i386_elf_section_type (const char *str, size_t len) | |
9962 | { | |
9963 | if (flag_code == CODE_64BIT | |
9964 | && len == sizeof ("unwind") - 1 | |
9965 | && strncmp (str, "unwind", 6) == 0) | |
9966 | return SHT_X86_64_UNWIND; | |
9967 | ||
9968 | return -1; | |
9969 | } | |
bb41ade5 AM |
9970 | |
9971 | #ifdef TE_PE | |
9972 | void | |
9973 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) | |
9974 | { | |
9975 | expressionS expr; | |
9976 | ||
9977 | expr.X_op = O_secrel; | |
9978 | expr.X_add_symbol = symbol; | |
9979 | expr.X_add_number = 0; | |
9980 | emit_expr (&expr, size); | |
9981 | } | |
9982 | #endif | |
3b22753a L |
9983 | |
9984 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
9985 | /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ | |
9986 | ||
9987 | int | |
9988 | x86_64_section_letter (int letter, char **ptr_msg) | |
9989 | { | |
9990 | if (flag_code == CODE_64BIT) | |
9991 | { | |
9992 | if (letter == 'l') | |
9993 | return SHF_X86_64_LARGE; | |
9994 | ||
9995 | *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string"); | |
64e74474 | 9996 | } |
3b22753a | 9997 | else |
64e74474 | 9998 | *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string"); |
3b22753a L |
9999 | return -1; |
10000 | } | |
10001 | ||
10002 | int | |
10003 | x86_64_section_word (char *str, size_t len) | |
10004 | { | |
8620418b | 10005 | if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large")) |
3b22753a L |
10006 | return SHF_X86_64_LARGE; |
10007 | ||
10008 | return -1; | |
10009 | } | |
10010 | ||
10011 | static void | |
10012 | handle_large_common (int small ATTRIBUTE_UNUSED) | |
10013 | { | |
10014 | if (flag_code != CODE_64BIT) | |
10015 | { | |
10016 | s_comm_internal (0, elf_common_parse); | |
10017 | as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); | |
10018 | } | |
10019 | else | |
10020 | { | |
10021 | static segT lbss_section; | |
10022 | asection *saved_com_section_ptr = elf_com_section_ptr; | |
10023 | asection *saved_bss_section = bss_section; | |
10024 | ||
10025 | if (lbss_section == NULL) | |
10026 | { | |
10027 | flagword applicable; | |
10028 | segT seg = now_seg; | |
10029 | subsegT subseg = now_subseg; | |
10030 | ||
10031 | /* The .lbss section is for local .largecomm symbols. */ | |
10032 | lbss_section = subseg_new (".lbss", 0); | |
10033 | applicable = bfd_applicable_section_flags (stdoutput); | |
10034 | bfd_set_section_flags (stdoutput, lbss_section, | |
10035 | applicable & SEC_ALLOC); | |
10036 | seg_info (lbss_section)->bss = 1; | |
10037 | ||
10038 | subseg_set (seg, subseg); | |
10039 | } | |
10040 | ||
10041 | elf_com_section_ptr = &_bfd_elf_large_com_section; | |
10042 | bss_section = lbss_section; | |
10043 | ||
10044 | s_comm_internal (0, elf_common_parse); | |
10045 | ||
10046 | elf_com_section_ptr = saved_com_section_ptr; | |
10047 | bss_section = saved_bss_section; | |
10048 | } | |
10049 | } | |
10050 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |